History

Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net

Conflicts: net/ipv4/ip_gre.c Minor conflicts between tunnel bug fixes in net and ipv6 tunnel cleanups in net-next.

David S. Miller committed 10 years ago

Commit cba65322 parents 26879da 7391daf263 files · +2446 −1230Browse files

Showing the changes to include/uapi (1 of 263 files). Show all

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include/uapi/linux/v4l2-dv-timings.h+20−10
@@ -183,7 +183,8 @@ · 182 unmodified lines
183183
184184 #define V4L2_DV_BT_CEA_3840X2160P24 { \
185185 .type = V4L2_DV_BT_656_1120, \
186− V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
186+ V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
187+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
187188 297000000, 1276, 88, 296, 8, 10, 72, 0, 0, 0, \
188189 V4L2_DV_BT_STD_CEA861, \
189190 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
@@ -191,14 +192,16 @@ · 1 unmodified line
191192
192193 #define V4L2_DV_BT_CEA_3840X2160P25 { \
193194 .type = V4L2_DV_BT_656_1120, \
194− V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
195+ V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
196+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
195197 297000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \
196198 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \
197199 }
198200
199201 #define V4L2_DV_BT_CEA_3840X2160P30 { \
200202 .type = V4L2_DV_BT_656_1120, \
201− V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
203+ V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
204+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
202205 297000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \
203206 V4L2_DV_BT_STD_CEA861, \
204207 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
@@ -206,14 +209,16 @@ · 1 unmodified line
206209
207210 #define V4L2_DV_BT_CEA_3840X2160P50 { \
208211 .type = V4L2_DV_BT_656_1120, \
209− V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
212+ V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
213+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
210214 594000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \
211215 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \
212216 }
213217
214218 #define V4L2_DV_BT_CEA_3840X2160P60 { \
215219 .type = V4L2_DV_BT_656_1120, \
216− V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
220+ V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
221+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
217222 594000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \
218223 V4L2_DV_BT_STD_CEA861, \
219224 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
@@ -221,7 +226,8 @@ · 1 unmodified line
221226
222227 #define V4L2_DV_BT_CEA_4096X2160P24 { \
223228 .type = V4L2_DV_BT_656_1120, \
224− V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
229+ V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
230+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
225231 297000000, 1020, 88, 296, 8, 10, 72, 0, 0, 0, \
226232 V4L2_DV_BT_STD_CEA861, \
227233 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
@@ -229,14 +235,16 @@ · 1 unmodified line
229235
230236 #define V4L2_DV_BT_CEA_4096X2160P25 { \
231237 .type = V4L2_DV_BT_656_1120, \
232− V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
238+ V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
239+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
233240 297000000, 968, 88, 128, 8, 10, 72, 0, 0, 0, \
234241 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \
235242 }
236243
237244 #define V4L2_DV_BT_CEA_4096X2160P30 { \
238245 .type = V4L2_DV_BT_656_1120, \
239− V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
246+ V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
247+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
240248 297000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \
241249 V4L2_DV_BT_STD_CEA861, \
242250 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \
@@ -244,14 +252,16 @@ · 1 unmodified line
244252
245253 #define V4L2_DV_BT_CEA_4096X2160P50 { \
246254 .type = V4L2_DV_BT_656_1120, \
247− V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
255+ V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
256+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
248257 594000000, 968, 88, 128, 8, 10, 72, 0, 0, 0, \
249258 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_IS_CE_VIDEO) \
250259 }
251260
252261 #define V4L2_DV_BT_CEA_4096X2160P60 { \
253262 .type = V4L2_DV_BT_656_1120, \
254− V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
263+ V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
264+ V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
255265 594000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \
256266 V4L2_DV_BT_STD_CEA861, \
257267 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO) \