This small patch fixes a mistake in the comments for the PERF_MEM_LVL_* events. The L2, L3 bits simply represent cache levels, not hits or misses. That is encoded in PERF_MEM_LVL_MISS/PERF_MEM_LVL_HIT.
Unified · Split
| @@ -645,8 +645,8 @@ union perf_mem_data_src { · 644 unmodified lines | |||
| 645 | #define PERF_MEM_LVL_MISS 0x04 /* miss level */ | 645 | #define PERF_MEM_LVL_MISS 0x04 /* miss level */ |
| 646 | #define PERF_MEM_LVL_L1 0x08 /* L1 */ | 646 | #define PERF_MEM_LVL_L1 0x08 /* L1 */ |
| 647 | #define PERF_MEM_LVL_LFB 0x10 /* Line Fill Buffer */ | 647 | #define PERF_MEM_LVL_LFB 0x10 /* Line Fill Buffer */ |
| 648 | #define PERF_MEM_LVL_L2 0x20 /* L2 hit */ | 648 | #define PERF_MEM_LVL_L2 0x20 /* L2 */ |
| 649 | #define PERF_MEM_LVL_L3 0x40 /* L3 hit */ | 649 | #define PERF_MEM_LVL_L3 0x40 /* L3 */ |
| 650 | #define PERF_MEM_LVL_LOC_RAM 0x80 /* Local DRAM */ | 650 | #define PERF_MEM_LVL_LOC_RAM 0x80 /* Local DRAM */ |
| 651 | #define PERF_MEM_LVL_REM_RAM1 0x100 /* Remote DRAM (1 hop) */ | 651 | #define PERF_MEM_LVL_REM_RAM1 0x100 /* Remote DRAM (1 hop) */ |
| 652 | #define PERF_MEM_LVL_REM_RAM2 0x200 /* Remote DRAM (2 hops) */ | 652 | #define PERF_MEM_LVL_REM_RAM2 0x200 /* Remote DRAM (2 hops) */ |