lael-labs/linux

CREDITS+24−0

@@ -710,6 +710,10 @@ S: Las Cuevas 2385 - Bo Guemes · 709 unmodified lines
710	S: Las Heras, Mendoza CP 5539	710	S: Las Heras, Mendoza CP 5539
711	S: Argentina	711	S: Argentina
712		712
		713	N: Jay Cliburn
		714	E: jcliburn@gmail.com
		715	D: ATLX Ethernet drivers
		716
713	N: Steven P. Cole	717	N: Steven P. Cole
714	E: scole@lanl.gov	718	E: scole@lanl.gov
715	E: elenstev@mesatop.com	719	E: elenstev@mesatop.com
@@ -1284,6 +1288,10 @@ D: Major kbuild rework during the 2.5 cycle · 568 unmodified lines
1284	D: ISDN Maintainer	1288	D: ISDN Maintainer
1285	S: USA	1289	S: USA
1286		1290
		1291	N: Gerrit Renker
		1292	E: gerrit@erg.abdn.ac.uk
		1293	D: DCCP protocol support.
		1294
1287	N: Philip Gladstone	1295	N: Philip Gladstone
1288	E: philip@gladstonefamily.net	1296	E: philip@gladstonefamily.net
1289	D: Kernel / timekeeping stuff	1297	D: Kernel / timekeeping stuff
@@ -2138,6 +2146,10 @@ E: seasons@falcon.sch.bme.hu · 848 unmodified lines
2138	E: seasons@makosteszta.sote.hu	2146	E: seasons@makosteszta.sote.hu
2139	D: Original author of software suspend	2147	D: Original author of software suspend
2140		2148
		2149	N: Alexey Kuznetsov
		2150	E: kuznet@ms2.inr.ac.ru
		2151	D: Author and maintainer of large parts of the networking stack
		2152
2141	N: Jaroslav Kysela	2153	N: Jaroslav Kysela
2142	E: perex@perex.cz	2154	E: perex@perex.cz
2143	W: https://www.perex.cz	2155	W: https://www.perex.cz
@@ -2696,6 +2708,10 @@ N: Wolfgang Muees · 552 unmodified lines
2696	E: wolfgang@iksw-muees.de	2708	E: wolfgang@iksw-muees.de
2697	D: Auerswald USB driver	2709	D: Auerswald USB driver
2698		2710
		2711	N: Shrijeet Mukherjee
		2712	E: shrijeet@gmail.com
		2713	D: Network routing domains (VRF).
		2714
2699	N: Paul Mundt	2715	N: Paul Mundt
2700	E: paul.mundt@gmail.com	2716	E: paul.mundt@gmail.com
2701	D: SuperH maintainer	2717	D: SuperH maintainer
@@ -4110,6 +4126,10 @@ S: B-1206 Jingmao Guojigongyu · 1408 unmodified lines
4110	S: 16 Baliqiao Nanjie, Beijing 101100	4126	S: 16 Baliqiao Nanjie, Beijing 101100
4111	S: People's Repulic of China	4127	S: People's Repulic of China
4112		4128
		4129	N: Aviad Yehezkel
		4130	E: aviadye@nvidia.com
		4131	D: Kernel TLS implementation and offload support.
		4132
4113	N: Victor Yodaiken	4133	N: Victor Yodaiken
4114	E: yodaiken@fsmlabs.com	4134	E: yodaiken@fsmlabs.com
4115	D: RTLinux (RealTime Linux)	4135	D: RTLinux (RealTime Linux)
@@ -4167,6 +4187,10 @@ S: 1507 145th Place SE #B5 · 51 unmodified lines
4167	S: Bellevue, Washington 98007	4187	S: Bellevue, Washington 98007
4168	S: USA	4188	S: USA
4169		4189
		4190	N: Wensong Zhang
		4191	E: wensong@linux-vs.org
		4192	D: IP virtual server (IPVS).
		4193
4170	N: Haojian Zhuang	4194	N: Haojian Zhuang
4171	E: haojian.zhuang@gmail.com	4195	E: haojian.zhuang@gmail.com
4172	D: MMP support	4196	D: MMP support

Documentation/RCU/Design/Memory-Ordering/Tree-RCU-Memory-Ordering.rst+4−4

@@ -473,7 +473,7 @@ read-side critical sections that follow the idle period (the oval near · 472 unmodified lines
473	the bottom of the diagram above).	473	the bottom of the diagram above).
474		474
475	Plumbing this into the full grace-period execution is described	475	Plumbing this into the full grace-period execution is described
476	`below <#Forcing%20Quiescent%20States>`__.	476	`below <Forcing Quiescent States_>`__.
477		477
478	CPU-Hotplug Interface	478	CPU-Hotplug Interface
479	^^^^^^^^^^^^^^^^^^^^^	479	^^^^^^^^^^^^^^^^^^^^^
@@ -494,7 +494,7 @@ mask to detect CPUs having gone offline since the beginning of this · 14 unmodified lines
494	grace period.	494	grace period.
495		495
496	Plumbing this into the full grace-period execution is described	496	Plumbing this into the full grace-period execution is described
497	`below <#Forcing%20Quiescent%20States>`__.	497	`below <Forcing Quiescent States_>`__.
498		498
499	Forcing Quiescent States	499	Forcing Quiescent States
500	^^^^^^^^^^^^^^^^^^^^^^^^	500	^^^^^^^^^^^^^^^^^^^^^^^^
@@ -532,7 +532,7 @@ from other CPUs. · 31 unmodified lines
532	\| RCU. But this diagram is complex enough as it is, so simplicity \|	532	\| RCU. But this diagram is complex enough as it is, so simplicity \|
533	\| overrode accuracy. You can think of it as poetic license, or you can \|	533	\| overrode accuracy. You can think of it as poetic license, or you can \|
534	\| think of it as misdirection that is resolved in the \|	534	\| think of it as misdirection that is resolved in the \|
535	\| `stitched-together diagram <#Putting%20It%20All%20Together>`__. \|	535	\| `stitched-together diagram <Putting It All Together_>`__. \|
536	+-----------------------------------------------------------------------+	536	+-----------------------------------------------------------------------+
537		537
538	Grace-Period Cleanup	538	Grace-Period Cleanup
@@ -596,7 +596,7 @@ maintain ordering. For example, if the callback function wakes up a task · 57 unmodified lines
596	that runs on some other CPU, proper ordering must in place in both the	596	that runs on some other CPU, proper ordering must in place in both the
597	callback function and the task being awakened. To see why this is	597	callback function and the task being awakened. To see why this is
598	important, consider the top half of the `grace-period	598	important, consider the top half of the `grace-period
599	cleanup <#Grace-Period%20Cleanup>`__ diagram. The callback might be	599	cleanup`_ diagram. The callback might be
600	running on a CPU corresponding to the leftmost leaf ``rcu_node``	600	running on a CPU corresponding to the leftmost leaf ``rcu_node``
601	structure, and awaken a task that is to run on a CPU corresponding to	601	structure, and awaken a task that is to run on a CPU corresponding to
602	the rightmost leaf ``rcu_node`` structure, and the grace-period kernel	602	the rightmost leaf ``rcu_node`` structure, and the grace-period kernel

Documentation/RCU/Design/Requirements/Requirements.rst+10−10

Documentation/admin-guide/binfmt-misc.rst+2−2

Documentation/admin-guide/bootconfig.rst+1−1

@@ -154,7 +154,7 @@ get the boot configuration data. · 153 unmodified lines
154	Because of this "piggyback" method, there is no need to change or	154	Because of this "piggyback" method, there is no need to change or
155	update the boot loader and the kernel image itself as long as the boot	155	update the boot loader and the kernel image itself as long as the boot
156	loader passes the correct initrd file size. If by any chance, the boot	156	loader passes the correct initrd file size. If by any chance, the boot
157	loader passes a longer size, the kernel feils to find the bootconfig data.	157	loader passes a longer size, the kernel fails to find the bootconfig data.
158		158
159	To do this operation, Linux kernel provides "bootconfig" command under	159	To do this operation, Linux kernel provides "bootconfig" command under
160	tools/bootconfig, which allows admin to apply or delete the config file	160	tools/bootconfig, which allows admin to apply or delete the config file

Documentation/admin-guide/kernel-parameters.rst+2−2

@@ -3,8 +3,8 @@ · 2 unmodified lines
3	The kernel's command-line parameters	3	The kernel's command-line parameters
4	====================================	4	====================================
5		5
6	The following is a consolidated list of the kernel parameters as	6	The following is a consolidated list of the kernel parameters as implemented
7	implemented by the __setup(), core_param() and module_param() macros	7	by the __setup(), early_param(), core_param() and module_param() macros
8	and sorted into English Dictionary order (defined as ignoring all	8	and sorted into English Dictionary order (defined as ignoring all
9	punctuation and sorting digits before letters in a case insensitive	9	punctuation and sorting digits before letters in a case insensitive
10	manner), and with descriptions where known.	10	manner), and with descriptions where known.

Documentation/admin-guide/kernel-parameters.txt+10−6

 	ftrace_filter=[function-list]
 			[FTRACE] Limit the functions traced by the function
-			tracer at boot up. function-list is a comma separated
+			tracer at boot up. function-list is a comma-separated
 			list of functions. This list can be changed at run
 			time by the set_ftrace_filter file in the debugfs
 			tracing directory.
 	ftrace_graph_filter=[function-list]
 			[FTRACE] Limit the top level callers functions traced
 			by the function graph tracer at boot up.
-			function-list is a comma separated list of functions
+			function-list is a comma-separated list of functions
 			that can be changed at run time by the
 			set_graph_function file in the debugfs tracing directory.
 	ftrace_graph_notrace=[function-list]
 			[FTRACE] Do not trace from the functions specified in
-			function-list.  This list is a comma separated list of
+			function-list.  This list is a comma-separated list of
 			functions that can be changed at run time by the
 			set_graph_notrace file in the debugfs tracing directory.
 			when set.
 			Format: <int>
-	libata.force=	[LIBATA] Force configurations.  The format is comma
+	libata.force=	[LIBATA] Force configurations.  The format is comma-
 			separated list of "[ID:]VAL" where ID is
 			PORT[.DEVICE].  PORT and DEVICE are decimal numbers
 			matching port, link or device.  Basically, it matches
 	stacktrace_filter=[function-list]
 			[FTRACE] Limit the functions that the stack tracer
-			will trace at boot up. function-list is a comma separated
+			will trace at boot up. function-list is a comma-separated
 			list of functions. This list can be changed at run
 			time by the stack_trace_filter file in the debugfs
 			tracing directory. Note, this enables stack tracing
 	trace_event=[event-list]
 			[FTRACE] Set and start specified trace events in order
 			to facilitate early boot debugging. The event-list is a
-			comma separated list of trace events to enable. See
+			comma-separated list of trace events to enable. See
 			also Documentation/trace/events.rst
 	trace_options=[option-list]
 			This option is obsoleted by the "nopv" option, which
 			has equivalent effect for XEN platform.
+	xen_no_vector_callback
+			[KNL,X86,XEN] Disable the vector callback for Xen
+			event channel interrupts.
 	xen_scrub_pages=	[XEN]
 			Boolean option to control scrubbing pages before giving them back
 			to Xen, for use by other domains. Can be also changed at runtime

Documentation/admin-guide/mm/concepts.rst+1−1

@@ -184,7 +184,7 @@ pages either asynchronously or synchronously, depending on the state · 183 unmodified lines
184	of the system. When the system is not loaded, most of the memory is free	184	of the system. When the system is not loaded, most of the memory is free
185	and allocation requests will be satisfied immediately from the free	185	and allocation requests will be satisfied immediately from the free
186	pages supply. As the load increases, the amount of the free pages goes	186	pages supply. As the load increases, the amount of the free pages goes
187	down and when it reaches a certain threshold (high watermark), an	187	down and when it reaches a certain threshold (low watermark), an
188	allocation request will awaken the ``kswapd`` daemon. It will	188	allocation request will awaken the ``kswapd`` daemon. It will
189	asynchronously scan memory pages and either just free them if the data	189	asynchronously scan memory pages and either just free them if the data
190	they contain is available elsewhere, or evict to the backing storage	190	they contain is available elsewhere, or evict to the backing storage

Documentation/core-api/index.rst+0−1

@@ -53,7 +53,6 @@ How Linux keeps everything from happening at the same time. See · 52 unmodified lines
53	.. toctree::	53	.. toctree::
54	:maxdepth: 1	54	:maxdepth: 1
55		55
56	atomic_ops
57	refcount-vs-atomic	56	refcount-vs-atomic
58	irq/index	57	irq/index
59	local_ops	58	local_ops

Documentation/devicetree/bindings/dma/ti/k3-bcdma.yaml+3−1

 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2020 Texas Instruments Incorporated
+# Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
 %YAML 1.2
 ---
 $id: http://devicetree.org/schemas/dma/ti/k3-bcdma.yaml#
 title: Texas Instruments K3 DMSS BCDMA Device Tree Bindings
 maintainers:
-  - Peter Ujfalusi <peter.ujfalusi@ti.com>
+  - Peter Ujfalusi <peter.ujfalusi@gmail.com>
 description: |
   The Block Copy DMA (BCDMA) is intended to perform similar functions as the TR

Documentation/devicetree/bindings/dma/ti/k3-pktdma.yaml+3−1

 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2020 Texas Instruments Incorporated
+# Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
 %YAML 1.2
 ---
 $id: http://devicetree.org/schemas/dma/ti/k3-pktdma.yaml#
 title: Texas Instruments K3 DMSS PKTDMA Device Tree Bindings
 maintainers:
-  - Peter Ujfalusi <peter.ujfalusi@ti.com>
+  - Peter Ujfalusi <peter.ujfalusi@gmail.com>
 description: |
   The Packet DMA (PKTDMA) is intended to perform similar functions as the packet

Documentation/devicetree/bindings/dma/ti/k3-udma.yaml+3−1

 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2019 Texas Instruments Incorporated
+# Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
 %YAML 1.2
 ---
 $id: http://devicetree.org/schemas/dma/ti/k3-udma.yaml#
 title: Texas Instruments K3 NAVSS Unified DMA Device Tree Bindings
 maintainers:
-  - Peter Ujfalusi <peter.ujfalusi@ti.com>
+  - Peter Ujfalusi <peter.ujfalusi@gmail.com>
 description: |
   The UDMA-P is intended to perform similar (but significantly upgraded)

Documentation/devicetree/bindings/net/renesas,etheravb.yaml+1−0

@@ -163,6 +163,7 @@ allOf: · 162 unmodified lines
163	enum:	163	enum:
164	- renesas,etheravb-r8a774a1	164	- renesas,etheravb-r8a774a1
165	- renesas,etheravb-r8a774b1	165	- renesas,etheravb-r8a774b1
		166	- renesas,etheravb-r8a774e1
166	- renesas,etheravb-r8a7795	167	- renesas,etheravb-r8a7795
167	- renesas,etheravb-r8a7796	168	- renesas,etheravb-r8a7796
168	- renesas,etheravb-r8a77961	169	- renesas,etheravb-r8a77961

Documentation/devicetree/bindings/net/snps,dwmac.yaml+6−2

             * snps,route-dcbcp, DCB Control Packets
             * snps,route-up, Untagged Packets
             * snps,route-multi-broad, Multicast & Broadcast Packets
-          * snps,priority, RX queue priority (Range 0x0 to 0xF)
+          * snps,priority, bitmask of the tagged frames priorities assigned to
+            the queue
   snps,mtl-tx-config:
     $ref: /schemas/types.yaml#/definitions/phandle
             * snps,idle_slope, unlock on WoL
             * snps,high_credit, max write outstanding req. limit
             * snps,low_credit, max read outstanding req. limit
-          * snps,priority, TX queue priority (Range 0x0 to 0xF)
+          * snps,priority, bitmask of the priorities assigned to the queue.
+            When a PFC frame is received with priorities matching the bitmask,
+            the queue is blocked from transmitting for the pause time specified
+            in the PFC frame.
   snps,reset-gpio:
     deprecated: true

Documentation/devicetree/bindings/regulator/nxp,pf8x00-regulator.yaml+4−2

 properties:
   compatible:
     enum:
-      - nxp,pf8x00
+      - nxp,pf8100
+      - nxp,pf8121a
+      - nxp,pf8200
   reg:
     maxItems: 1
         #size-cells = <0>;
         pmic@8 {
-            compatible = "nxp,pf8x00";
+            compatible = "nxp,pf8100";
             reg = <0x08>;
             regulators {

Documentation/devicetree/bindings/regulator/qcom,rpmh-regulator.txt+1−0

@@ -44,6 +44,7 @@ First Level Nodes - PMIC · 43 unmodified lines
44	Definition: Must be one of below:	44	Definition: Must be one of below:
45	"qcom,pm8005-rpmh-regulators"	45	"qcom,pm8005-rpmh-regulators"
46	"qcom,pm8009-rpmh-regulators"	46	"qcom,pm8009-rpmh-regulators"
		47	"qcom,pm8009-1-rpmh-regulators"
47	"qcom,pm8150-rpmh-regulators"	48	"qcom,pm8150-rpmh-regulators"
48	"qcom,pm8150l-rpmh-regulators"	49	"qcom,pm8150l-rpmh-regulators"
49	"qcom,pm8350-rpmh-regulators"	50	"qcom,pm8350-rpmh-regulators"

Documentation/devicetree/bindings/sound/ti,j721e-cpb-audio.yaml+3−1

 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2020 Texas Instruments Incorporated
+# Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
 %YAML 1.2
 ---
 $id: http://devicetree.org/schemas/sound/ti,j721e-cpb-audio.yaml#
 title: Texas Instruments J721e Common Processor Board Audio Support
 maintainers:
-  - Peter Ujfalusi <peter.ujfalusi@ti.com>
+  - Peter Ujfalusi <peter.ujfalusi@gmail.com>
 description: |
   The audio support on the board is using pcm3168a codec connected to McASP10

Documentation/devicetree/bindings/sound/ti,j721e-cpb-ivi-audio.yaml+3−1

 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2020 Texas Instruments Incorporated
+# Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
 %YAML 1.2
 ---
 $id: http://devicetree.org/schemas/sound/ti,j721e-cpb-ivi-audio.yaml#
 title: Texas Instruments J721e Common Processor Board Audio Support
 maintainers:
-  - Peter Ujfalusi <peter.ujfalusi@ti.com>
+  - Peter Ujfalusi <peter.ujfalusi@gmail.com>
 description: |
   The Infotainment board plugs into the Common Processor Board, the support of the

Documentation/devicetree/bindings/usb/ti,j721e-usb.yaml+5−1

 properties:
   compatible:
-    items:
+    oneOf:
       - const: ti,j721e-usb
+      - const: ti,am64-usb
+      - items:
+          - const: ti,j721e-usb
+          - const: ti,am64-usb
   reg:
     description: module registers

Documentation/doc-guide/sphinx.rst+16−16

@@ -48,12 +48,12 @@ or ``virtualenv``, depending on how your distribution packaged Python 3. · 47 unmodified lines
48	those versions, you should run ``pip install 'docutils==0.12'``.	48	those versions, you should run ``pip install 'docutils==0.12'``.
49		49
50	#) It is recommended to use the RTD theme for html output. Depending	50	#) It is recommended to use the RTD theme for html output. Depending
51	on the Sphinx version, it should be installed in separate,	51	on the Sphinx version, it should be installed separately,
52	with ``pip install sphinx_rtd_theme``.	52	with ``pip install sphinx_rtd_theme``.
53		53
54	#) Some ReST pages contain math expressions. Due to the way Sphinx work,	54	#) Some ReST pages contain math expressions. Due to the way Sphinx works,
55	those expressions are written using LaTeX notation. It needs texlive	55	those expressions are written using LaTeX notation. It needs texlive
56	installed with amdfonts and amsmath in order to evaluate them.	56	installed with amsfonts and amsmath in order to evaluate them.
57		57
58	In summary, if you want to install Sphinx version 1.7.9, you should do::	58	In summary, if you want to install Sphinx version 1.7.9, you should do::
59		59
@@ -128,7 +128,7 @@ Sphinx Build · 68 unmodified lines
128	============	128	============
129		129
130	The usual way to generate the documentation is to run ``make htmldocs`` or	130	The usual way to generate the documentation is to run ``make htmldocs`` or
131	``make pdfdocs``. There are also other formats available, see the documentation	131	``make pdfdocs``. There are also other formats available: see the documentation
132	section of ``make help``. The generated documentation is placed in	132	section of ``make help``. The generated documentation is placed in
133	format-specific subdirectories under ``Documentation/output``.	133	format-specific subdirectories under ``Documentation/output``.
134		134
@@ -303,17 +303,17 @@ and targets (e.g. a ref to ``:ref:`last row <last row>``` / :ref:`last row · 168 unmodified lines
303	- head col 3	303	- head col 3
304	- head col 4	304	- head col 4
305		305
306	* - column 1	306	* - row 1
307	- field 1.1	307	- field 1.1
308	- field 1.2 with autospan	308	- field 1.2 with autospan
309		309
310	* - column 2	310	* - row 2
311	- field 2.1	311	- field 2.1
312	- :rspan:`1` :cspan:`1` field 2.2 - 3.3	312	- :rspan:`1` :cspan:`1` field 2.2 - 3.3
313		313
314	* .. _`last row`:	314	* .. _`last row`:
315		315
316	- column 3	316	- row 3
317		317
318	Rendered as:	318	Rendered as:
319		319
@@ -325,17 +325,17 @@ Rendered as: · 5 unmodified lines
325	- head col 3	325	- head col 3
326	- head col 4	326	- head col 4
327		327
328	* - column 1	328	* - row 1
329	- field 1.1	329	- field 1.1
330	- field 1.2 with autospan	330	- field 1.2 with autospan
331		331
332	* - column 2	332	* - row 2
333	- field 2.1	333	- field 2.1
334	- :rspan:`1` :cspan:`1` field 2.2 - 3.3	334	- :rspan:`1` :cspan:`1` field 2.2 - 3.3
335		335
336	* .. _`last row`:	336	* .. _`last row`:
337		337
338	- column 3	338	- row 3
339		339
340	Cross-referencing	340	Cross-referencing
341	-----------------	341	-----------------
@@ -361,7 +361,7 @@ Figures & Images · 19 unmodified lines
361		361
362	If you want to add an image, you should use the ``kernel-figure`` and	362	If you want to add an image, you should use the ``kernel-figure`` and
363	``kernel-image`` directives. E.g. to insert a figure with a scalable	363	``kernel-image`` directives. E.g. to insert a figure with a scalable
364	image format use SVG (:ref:`svg_image_example`)::	364	image format, use SVG (:ref:`svg_image_example`)::
365		365
366	.. kernel-figure:: svg_image.svg	366	.. kernel-figure:: svg_image.svg
367	:alt: simple SVG image	367	:alt: simple SVG image
@@ -375,7 +375,7 @@ image format use SVG (:ref:`svg_image_example`):: · 7 unmodified lines
375		375
376	SVG image example	376	SVG image example
377		377
378	The kernel figure (and image) directive support DOT formatted files, see	378	The kernel figure (and image) directive supports DOT formatted files, see
379		379
380	* DOT: http://graphviz.org/pdf/dotguide.pdf	380	* DOT: http://graphviz.org/pdf/dotguide.pdf
381	* Graphviz: http://www.graphviz.org/content/dot-language	381	* Graphviz: http://www.graphviz.org/content/dot-language
@@ -394,7 +394,7 @@ A simple example (:ref:`hello_dot_file`):: · 12 unmodified lines
394		394
395	DOT's hello world example	395	DOT's hello world example
396		396
397	Embed render markups (or languages) like Graphviz's DOT is provided by the	397	Embedded render markups (or languages) like Graphviz's DOT are provided by the
398	``kernel-render`` directives.::	398	``kernel-render`` directives.::
399		399
400	.. kernel-render:: DOT	400	.. kernel-render:: DOT
@@ -406,7 +406,7 @@ Embed render markups (or languages) like Graphviz's DOT is provided by the · 5 unmodified lines
406	}	406	}
407		407
408	How this will be rendered depends on the installed tools. If Graphviz is	408	How this will be rendered depends on the installed tools. If Graphviz is
409	installed, you will see an vector image. If not the raw markup is inserted as	409	installed, you will see a vector image. If not, the raw markup is inserted as
410	literal-block (:ref:`hello_dot_render`).	410	literal-block (:ref:`hello_dot_render`).
411		411
412	.. _hello_dot_render:	412	.. _hello_dot_render:
@@ -421,8 +421,8 @@ installed, you will see an vector image. If not the raw markup is inserted as · 8 unmodified lines
421		421
422	The render directive has all the options known from the figure directive,	422	The render directive has all the options known from the figure directive,
423	plus option ``caption``. If ``caption`` has a value, a figure node is	423	plus option ``caption``. If ``caption`` has a value, a figure node is
424	inserted. If not, a image node is inserted. A ``caption`` is also needed, if	424	inserted. If not, an image node is inserted. A ``caption`` is also needed, if
425	you want to refer it (:ref:`hello_svg_render`).	425	you want to refer to it (:ref:`hello_svg_render`).
426		426
427	Embedded SVG::	427	Embedded SVG::
428		428

Documentation/firmware-guide/acpi/apei/einj.rst+2−2

@@ -50,8 +50,8 @@ The following files belong to it: · 49 unmodified lines
50	0x00000010 Memory Uncorrectable non-fatal	50	0x00000010 Memory Uncorrectable non-fatal
51	0x00000020 Memory Uncorrectable fatal	51	0x00000020 Memory Uncorrectable fatal
52	0x00000040 PCI Express Correctable	52	0x00000040 PCI Express Correctable
53	0x00000080 PCI Express Uncorrectable fatal	53	0x00000080 PCI Express Uncorrectable non-fatal
54	0x00000100 PCI Express Uncorrectable non-fatal	54	0x00000100 PCI Express Uncorrectable fatal
55	0x00000200 Platform Correctable	55	0x00000200 Platform Correctable
56	0x00000400 Platform Uncorrectable non-fatal	56	0x00000400 Platform Uncorrectable non-fatal
57	0x00000800 Platform Uncorrectable fatal	57	0x00000800 Platform Uncorrectable fatal

Documentation/hwmon/sbtsi_temp.rst+1−1

@@ -1,7 +1,7 @@
1	.. SPDX-License-Identifier: GPL-2.0-or-later	1	.. SPDX-License-Identifier: GPL-2.0-or-later
2		2
3	Kernel driver sbtsi_temp	3	Kernel driver sbtsi_temp
4	==================	4	========================
5		5
6	Supported hardware:	6	Supported hardware:
7		7

Documentation/kbuild/makefiles.rst+1−1

@@ -598,7 +598,7 @@ more details, with real examples. · 597 unmodified lines
598	explicitly added to $(targets).	598	explicitly added to $(targets).
599		599
600	Assignments to $(targets) are without $(obj)/ prefix. if_changed may be	600	Assignments to $(targets) are without $(obj)/ prefix. if_changed may be
601	used in conjunction with custom rules as defined in "3.9 Custom Rules".	601	used in conjunction with custom rules as defined in "3.11 Custom Rules".
602		602
603	Note: It is a typical mistake to forget the FORCE prerequisite.	603	Note: It is a typical mistake to forget the FORCE prerequisite.
604	Another common pitfall is that whitespace is sometimes significant; for	604	Another common pitfall is that whitespace is sometimes significant; for

Documentation/kernel-hacking/locking.rst+4−4

Documentation/networking/device_drivers/ethernet/marvell/octeontx2.rst+36−26

@@ -164,46 +164,56 @@ Devlink health reporters · 163 unmodified lines
164		164
165	NPA Reporters	165	NPA Reporters
166	-------------	166	-------------
167	The NPA reporters are responsible for reporting and recovering the following group of errors	167	The NPA reporters are responsible for reporting and recovering the following group of errors:
		168
168	1. GENERAL events	169	1. GENERAL events
		170
169	- Error due to operation of unmapped PF.	171	- Error due to operation of unmapped PF.
170	- Error due to disabled alloc/free for other HW blocks (NIX, SSO, TIM, DPI and AURA).	172	- Error due to disabled alloc/free for other HW blocks (NIX, SSO, TIM, DPI and AURA).
		173
171	2. ERROR events	174	2. ERROR events
		175
172	- Fault due to NPA_AQ_INST_S read or NPA_AQ_RES_S write.	176	- Fault due to NPA_AQ_INST_S read or NPA_AQ_RES_S write.
173	- AQ Doorbell Error.	177	- AQ Doorbell Error.
		178
174	3. RAS events	179	3. RAS events
		180
175	- RAS Error Reporting for NPA_AQ_INST_S/NPA_AQ_RES_S.	181	- RAS Error Reporting for NPA_AQ_INST_S/NPA_AQ_RES_S.
		182
176	4. RVU events	183	4. RVU events
		184
177	- Error due to unmapped slot.	185	- Error due to unmapped slot.
178		186
179	Sample Output	187	Sample Output::
180	-------------	188
181	~# devlink health	189	~# devlink health
182	pci/0002:01:00.0:	190	pci/0002:01:00.0:
183	reporter hw_npa_intr	191	reporter hw_npa_intr
184	state healthy error 2872 recover 2872 last_dump_date 2020-12-10 last_dump_time 09:39:09 grace_period 0 auto_recover true auto_dump true	192	state healthy error 2872 recover 2872 last_dump_date 2020-12-10 last_dump_time 09:39:09 grace_period 0 auto_recover true auto_dump true
185	reporter hw_npa_gen	193	reporter hw_npa_gen
186	state healthy error 2872 recover 2872 last_dump_date 2020-12-11 last_dump_time 04:43:04 grace_period 0 auto_recover true auto_dump true	194	state healthy error 2872 recover 2872 last_dump_date 2020-12-11 last_dump_time 04:43:04 grace_period 0 auto_recover true auto_dump true
187	reporter hw_npa_err	195	reporter hw_npa_err
188	state healthy error 2871 recover 2871 last_dump_date 2020-12-10 last_dump_time 09:39:17 grace_period 0 auto_recover true auto_dump true	196	state healthy error 2871 recover 2871 last_dump_date 2020-12-10 last_dump_time 09:39:17 grace_period 0 auto_recover true auto_dump true
189	reporter hw_npa_ras	197	reporter hw_npa_ras
190	state healthy error 0 recover 0 last_dump_date 2020-12-10 last_dump_time 09:32:40 grace_period 0 auto_recover true auto_dump true	198	state healthy error 0 recover 0 last_dump_date 2020-12-10 last_dump_time 09:32:40 grace_period 0 auto_recover true auto_dump true
191		199
192	Each reporter dumps the	200	Each reporter dumps the
		201
193	- Error Type	202	- Error Type
194	- Error Register value	203	- Error Register value
195	- Reason in words	204	- Reason in words
196		205
197	For eg:	206	For example::
198	~# devlink health dump show pci/0002:01:00.0 reporter hw_npa_gen	207
199	NPA_AF_GENERAL:	208	~# devlink health dump show pci/0002:01:00.0 reporter hw_npa_gen
200	NPA General Interrupt Reg : 1	209	NPA_AF_GENERAL:
201	NIX0: free disabled RX	210	NPA General Interrupt Reg : 1
202	~# devlink health dump show pci/0002:01:00.0 reporter hw_npa_intr	211	NIX0: free disabled RX
203	NPA_AF_RVU:	212	~# devlink health dump show pci/0002:01:00.0 reporter hw_npa_intr
204	NPA RVU Interrupt Reg : 1	213	NPA_AF_RVU:
205	Unmap Slot Error	214	NPA RVU Interrupt Reg : 1
206	~# devlink health dump show pci/0002:01:00.0 reporter hw_npa_err	215	Unmap Slot Error
207	NPA_AF_ERR:	216	~# devlink health dump show pci/0002:01:00.0 reporter hw_npa_err
208	NPA Error Interrupt Reg : 4096	217	NPA_AF_ERR:
209	AQ Doorbell Error	218	NPA Error Interrupt Reg : 4096
		219	AQ Doorbell Error

Documentation/networking/netdev-FAQ.rst+59−67

Documentation/networking/netdevices.rst+167−8

@@ -10,18 +10,177 @@ Introduction · 9 unmodified lines
10	The following is a random collection of documentation regarding	10	The following is a random collection of documentation regarding
11	network devices.	11	network devices.
12		12
13	struct net_device allocation rules	13	struct net_device lifetime rules
14	==================================	14	================================
15	Network device structures need to persist even after module is unloaded and	15	Network device structures need to persist even after module is unloaded and
16	must be allocated with alloc_netdev_mqs() and friends.	16	must be allocated with alloc_netdev_mqs() and friends.
17	If device has registered successfully, it will be freed on last use	17	If device has registered successfully, it will be freed on last use
18	by free_netdev(). This is required to handle the pathologic case cleanly	18	by free_netdev(). This is required to handle the pathological case cleanly
19	(example: rmmod mydriver </sys/class/net/myeth/mtu )	19	(example: ``rmmod mydriver </sys/class/net/myeth/mtu``)
20		20
21	alloc_netdev_mqs()/alloc_netdev() reserve extra space for driver	21	alloc_netdev_mqs() / alloc_netdev() reserve extra space for driver
22	private data which gets freed when the network device is freed. If	22	private data which gets freed when the network device is freed. If
23	separately allocated data is attached to the network device	23	separately allocated data is attached to the network device
24	(netdev_priv(dev)) then it is up to the module exit handler to free that.	24	(netdev_priv()) then it is up to the module exit handler to free that.
		25
		26	There are two groups of APIs for registering struct net_device.
		27	First group can be used in normal contexts where ``rtnl_lock`` is not already
		28	held: register_netdev(), unregister_netdev().
		29	Second group can be used when ``rtnl_lock`` is already held:
		30	register_netdevice(), unregister_netdevice(), free_netdevice().
		31
		32	Simple drivers
		33	--------------
		34
		35	Most drivers (especially device drivers) handle lifetime of struct net_device
		36	in context where ``rtnl_lock`` is not held (e.g. driver probe and remove paths).
		37
		38	In that case the struct net_device registration is done using
		39	the register_netdev(), and unregister_netdev() functions:
		40
		41	.. code-block:: c
		42
		43	int probe()
		44	{
		45	struct my_device_priv *priv;
		46	int err;
		47
		48	dev = alloc_netdev_mqs(...);
		49	if (!dev)
		50	return -ENOMEM;
		51	priv = netdev_priv(dev);
		52
		53	/* ... do all device setup before calling register_netdev() ...
		54	*/
		55
		56	err = register_netdev(dev);
		57	if (err)
		58	goto err_undo;
		59
		60	/* net_device is visible to the user! */
		61
		62	err_undo:
		63	/* ... undo the device setup ... */
		64	free_netdev(dev);
		65	return err;
		66	}
		67
		68	void remove()
		69	{
		70	unregister_netdev(dev);
		71	free_netdev(dev);
		72	}
		73
		74	Note that after calling register_netdev() the device is visible in the system.
		75	Users can open it and start sending / receiving traffic immediately,
		76	or run any other callback, so all initialization must be done prior to
		77	registration.
		78
		79	unregister_netdev() closes the device and waits for all users to be done
		80	with it. The memory of struct net_device itself may still be referenced
		81	by sysfs but all operations on that device will fail.
		82
		83	free_netdev() can be called after unregister_netdev() returns on when
		84	register_netdev() failed.
		85
		86	Device management under RTNL
		87	----------------------------
		88
		89	Registering struct net_device while in context which already holds
		90	the ``rtnl_lock`` requires extra care. In those scenarios most drivers
		91	will want to make use of struct net_device's ``needs_free_netdev``
		92	and ``priv_destructor`` members for freeing of state.
		93
		94	Example flow of netdev handling under ``rtnl_lock``:
		95
		96	.. code-block:: c
		97
		98	static void my_setup(struct net_device *dev)
		99	{
		100	dev->needs_free_netdev = true;
		101	}
		102
		103	static void my_destructor(struct net_device *dev)
		104	{
		105	some_obj_destroy(priv->obj);
		106	some_uninit(priv);
		107	}
		108
		109	int create_link()
		110	{
		111	struct my_device_priv *priv;
		112	int err;
		113
		114	ASSERT_RTNL();
		115
		116	dev = alloc_netdev(sizeof(*priv), "net%d", NET_NAME_UNKNOWN, my_setup);
		117	if (!dev)
		118	return -ENOMEM;
		119	priv = netdev_priv(dev);
		120
		121	/* Implicit constructor */
		122	err = some_init(priv);
		123	if (err)
		124	goto err_free_dev;
		125
		126	priv->obj = some_obj_create();
		127	if (!priv->obj) {
		128	err = -ENOMEM;
		129	goto err_some_uninit;
		130	}
		131	/* End of constructor, set the destructor: */
		132	dev->priv_destructor = my_destructor;
		133
		134	err = register_netdevice(dev);
		135	if (err)
		136	/* register_netdevice() calls destructor on failure */
		137	goto err_free_dev;
		138
		139	/* If anything fails now unregister_netdevice() (or unregister_netdev())
		140	* will take care of calling my_destructor and free_netdev().
		141	*/
		142
		143	return 0;
		144
		145	err_some_uninit:
		146	some_uninit(priv);
		147	err_free_dev:
		148	free_netdev(dev);
		149	return err;
		150	}
		151
		152	If struct net_device.priv_destructor is set it will be called by the core
		153	some time after unregister_netdevice(), it will also be called if
		154	register_netdevice() fails. The callback may be invoked with or without
		155	``rtnl_lock`` held.
		156
		157	There is no explicit constructor callback, driver "constructs" the private
		158	netdev state after allocating it and before registration.
		159
		160	Setting struct net_device.needs_free_netdev makes core call free_netdevice()
		161	automatically after unregister_netdevice() when all references to the device
		162	are gone. It only takes effect after a successful call to register_netdevice()
		163	so if register_netdevice() fails driver is responsible for calling
		164	free_netdev().
		165
		166	free_netdev() is safe to call on error paths right after unregister_netdevice()
		167	or when register_netdevice() fails. Parts of netdev (de)registration process
		168	happen after ``rtnl_lock`` is released, therefore in those cases free_netdev()
		169	will defer some of the processing until ``rtnl_lock`` is released.
		170
		171	Devices spawned from struct rtnl_link_ops should never free the
		172	struct net_device directly.
		173
		174	.ndo_init and .ndo_uninit
		175	~~~~~~~~~~~~~~~~~~~~~~~~~
		176
		177	``.ndo_init`` and ``.ndo_uninit`` callbacks are called during net_device
		178	registration and de-registration, under ``rtnl_lock``. Drivers can use
		179	those e.g. when parts of their init process need to run under ``rtnl_lock``.
		180
		181	``.ndo_init`` runs before device is visible in the system, ``.ndo_uninit``
		182	runs during de-registering after device is closed but other subsystems
		183	may still have outstanding references to the netdevice.
25		184
26	MTU	185	MTU
27	===	186	===
@@ -64,8 +223,8 @@ ndo_do_ioctl: · 36 unmodified lines
64	Context: process	223	Context: process
65		224
66	ndo_get_stats:	225	ndo_get_stats:
67	Synchronization: dev_base_lock rwlock.	226	Synchronization: rtnl_lock() semaphore, dev_base_lock rwlock, or RCU.
68	Context: nominally process, but don't sleep inside an rwlock	227	Context: atomic (can't sleep under rwlock or RCU)
69		228
70	ndo_start_xmit:	229	ndo_start_xmit:
71	Synchronization: __netif_tx_lock spinlock.	230	Synchronization: __netif_tx_lock spinlock.

Documentation/networking/packet_mmap.rst+5−6

 ========
 This file documents the mmap() facility available with the PACKET
-socket interface on 2.4/2.6/3.x kernels. This type of sockets is used for
+socket interface. This type of sockets is used for
 i) capture network traffic with utilities like tcpdump,
 ii) transmit network traffic, or any other that needs raw
 Why use PACKET_MMAP
 ===================
-In Linux 2.4/2.6/3.x if PACKET_MMAP is not enabled, the capture process is very
+Non PACKET_MMAP capture process (plain AF_PACKET) is very
 inefficient. It uses very limited buffers and requires one system call to
 capture each packet, it requires two if you want to get packet's timestamp
 (like libpcap always does).
-In the other hand PACKET_MMAP is very efficient. PACKET_MMAP provides a size
+On the other hand PACKET_MMAP is very efficient. PACKET_MMAP provides a size
 configurable circular buffer mapped in user space that can be used to either
 send or receive packets. This way reading packets just needs to wait for them,
 most of the time there is no need to issue a single system call. Concerning
 In kernel versions prior to 2.4.26 (for the 2.4 branch) and 2.6.5 (2.6 branch),
 the PACKET_MMAP buffer could hold only 32768 frames in a 32 bit architecture or
-16384 in a 64 bit architecture. For information on these kernel versions
+16384 in a 64 bit architecture.
-see http://pusa.uv.es/~ulisses/packet_mmap/packet_mmap.pre-2.4.26_2.6.5.txt
 Block size limit
 ----------------
 Capture process
 ^^^^^^^^^^^^^^^
-     from include/linux/if_packet.h
+From include/linux/if_packet.h::
      #define TP_STATUS_COPY          (1 << 1)
      #define TP_STATUS_LOSING        (1 << 2)

Documentation/networking/tls-offload.rst+1−1

@@ -530,7 +530,7 @@ TLS device feature flags only control adding of new TLS connection · 529 unmodified lines
530	offloads, old connections will remain active after flags are cleared.	530	offloads, old connections will remain active after flags are cleared.
531		531
532	TLS encryption cannot be offloaded to devices without checksum calculation	532	TLS encryption cannot be offloaded to devices without checksum calculation
533	offload. Hence, TLS TX device feature flag requires NETIF_F_HW_CSUM being set.	533	offload. Hence, TLS TX device feature flag requires TX csum offload being set.
534	Disabling the latter implies clearing the former. Disabling TX checksum offload	534	Disabling the latter implies clearing the former. Disabling TX checksum offload
535	should not affect old connections, and drivers should make sure checksum	535	should not affect old connections, and drivers should make sure checksum
536	calculation does not break for them.	536	calculation does not break for them.

Documentation/process/4.Coding.rst+2−4

 of these options should be turned on for any kernel used for development or
 testing purposes.  In particular, you should turn on:
- - ENABLE_MUST_CHECK and FRAME_WARN to get an
+ - FRAME_WARN to get warnings for stack frames larger than a given amount.
-   extra set of warnings for problems like the use of deprecated interfaces
+   The output generated can be verbose, but one need not worry about
-   or ignoring an important return value from a function.  The output
-   generated by these warnings can be verbose, but one need not worry about
    warnings from other parts of the kernel.
  - DEBUG_OBJECTS will add code to track the lifetime of various objects

Documentation/sound/alsa-configuration.rst+1−1

@@ -1501,7 +1501,7 @@ Module for Digigram miXart8 sound cards. · 1500 unmodified lines
1501		1501
1502	This module supports multiple cards.	1502	This module supports multiple cards.
1503	Note: One miXart8 board will be represented as 4 alsa cards.	1503	Note: One miXart8 board will be represented as 4 alsa cards.
1504	See MIXART.txt for details.	1504	See Documentation/sound/cards/mixart.rst for details.
1505		1505
1506	When the driver is compiled as a module and the hotplug firmware	1506	When the driver is compiled as a module and the hotplug firmware
1507	is supported, the firmware data is loaded via hotplug automatically.	1507	is supported, the firmware data is loaded via hotplug automatically.

Documentation/sound/kernel-api/writing-an-alsa-driver.rst+8−8

@@ -71,7 +71,7 @@ core/oss · 70 unmodified lines
71	The codes for PCM and mixer OSS emulation modules are stored in this	71	The codes for PCM and mixer OSS emulation modules are stored in this
72	directory. The rawmidi OSS emulation is included in the ALSA rawmidi	72	directory. The rawmidi OSS emulation is included in the ALSA rawmidi
73	code since it's quite small. The sequencer code is stored in	73	code since it's quite small. The sequencer code is stored in
74	``core/seq/oss`` directory (see `below <#core-seq-oss>`__).	74	``core/seq/oss`` directory (see `below <core/seq/oss_>`__).
75		75
76	core/seq	76	core/seq
77	~~~~~~~~	77	~~~~~~~~
@@ -382,7 +382,7 @@ where ``enable[dev]`` is the module option. · 304 unmodified lines
382	Each time the ``probe`` callback is called, check the availability of	382	Each time the ``probe`` callback is called, check the availability of
383	the device. If not available, simply increment the device index and	383	the device. If not available, simply increment the device index and
384	returns. dev will be incremented also later (`step 7	384	returns. dev will be incremented also later (`step 7
385	<#set-the-pci-driver-data-and-return-zero>`__).	385	<7) Set the PCI driver data and return zero._>`__).
386		386
387	2) Create a card instance	387	2) Create a card instance
388	~~~~~~~~~~~~~~~~~~~~~~~~~	388	~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -450,10 +450,10 @@ field contains the information shown in ``/proc/asound/cards``. · 61 unmodified lines
450	5) Create other components, such as mixer, MIDI, etc.	450	5) Create other components, such as mixer, MIDI, etc.
451	~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~	451	~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
452		452
453	Here you define the basic components such as `PCM <#PCM-Interface>`__,	453	Here you define the basic components such as `PCM <PCM Interface_>`__,
454	mixer (e.g. `AC97 <#API-for-AC97-Codec>`__), MIDI (e.g.	454	mixer (e.g. `AC97 <API for AC97 Codec_>`__), MIDI (e.g.
455	`MPU-401 <#MIDI-MPU401-UART-Interface>`__), and other interfaces.	455	`MPU-401 <MIDI (MPU401-UART) Interface_>`__), and other interfaces.
456	Also, if you want a `proc file <#Proc-Interface>`__, define it here,	456	Also, if you want a `proc file <Proc Interface_>`__, define it here,
457	too.	457	too.
458		458
459	6) Register the card instance.	459	6) Register the card instance.
@@ -941,7 +941,7 @@ The allocation of an interrupt source is done like this: · 481 unmodified lines
941	chip->irq = pci->irq;	941	chip->irq = pci->irq;
942		942
943	where :c:func:`snd_mychip_interrupt()` is the interrupt handler	943	where :c:func:`snd_mychip_interrupt()` is the interrupt handler
944	defined `later <#pcm-interface-interrupt-handler>`__. Note that	944	defined `later <PCM Interrupt Handler_>`__. Note that
945	``chip->irq`` should be defined only when :c:func:`request_irq()`	945	``chip->irq`` should be defined only when :c:func:`request_irq()`
946	succeeded.	946	succeeded.
947		947
@@ -3104,7 +3104,7 @@ processing the output stream in the irq handler. · 2156 unmodified lines
3104		3104
3105	If the MPU-401 interface shares its interrupt with the other logical	3105	If the MPU-401 interface shares its interrupt with the other logical
3106	devices on the card, set ``MPU401_INFO_IRQ_HOOK`` (see	3106	devices on the card, set ``MPU401_INFO_IRQ_HOOK`` (see
3107	`below <#MIDI-Interrupt-Handler>`__).	3107	`below <MIDI Interrupt Handler_>`__).
3108		3108
3109	Usually, the port address corresponds to the command port and port + 1	3109	Usually, the port address corresponds to the command port and port + 1
3110	corresponds to the data port. If not, you may change the ``cport``	3110	corresponds to the data port. If not, you may change the ``cport``

Documentation/virt/kvm/api.rst+7−2

 Errors:
-  =====      =============================
+  =======    ==============================================================
   EINTR      an unmasked signal is pending
-  =====      =============================
+  ENOEXEC    the vcpu hasn't been initialized or the guest tried to execute
+             instructions from device memory (arm64)
+  ENOSYS     data abort outside memslots with no syndrome info and
+             KVM_CAP_ARM_NISV_TO_USER not enabled (arm64)
+  EPERM      SVE feature set but not finalized (arm64)
+  =======    ==============================================================
 This ioctl is used to run a guest virtual cpu.  While there are no
 explicit parameters, there is an implicit parameter block that can be

MAINTAINERS+42−35

 F:	net/wireless/
 8169 10/100/1000 GIGABIT ETHERNET DRIVER
-M:	Realtek linux nic maintainers <nic_swsd@realtek.com>
 M:	Heiner Kallweit <hkallweit1@gmail.com>
+M:	nic_swsd@realtek.com
 L:	netdev@vger.kernel.org
 S:	Maintained
 F:	drivers/net/ethernet/realtek/r8169*
 M:	Arthur Kiyanovski <akiyano@amazon.com>
 R:	Guy Tzalik <gtzalik@amazon.com>
 R:	Saeed Bishara <saeedb@amazon.com>
-R:	Zorik Machulsky <zorik@amazon.com>
 L:	netdev@vger.kernel.org
 S:	Supported
 F:	Documentation/networking/device_drivers/ethernet/amazon/ena.rst
 M:	Felix Kuehling <Felix.Kuehling@amd.com>
 L:	amd-gfx@lists.freedesktop.org
 S:	Supported
-T:	git git://people.freedesktop.org/~agd5f/linux
+T:	git https://gitlab.freedesktop.org/agd5f/linux.git
 F:	drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd*.[ch]
 F:	drivers/gpu/drm/amd/amdkfd/
 F:	drivers/gpu/drm/amd/include/cik_structs.h
 ARM/Microchip Sparx5 SoC support
 M:	Lars Povlsen <lars.povlsen@microchip.com>
 M:	Steen Hegelund <Steen.Hegelund@microchip.com>
-M:	Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>
+M:	UNGLinuxDriver@microchip.com
 L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 S:	Supported
 T:	git git://github.com/microchip-ung/linux-upstream.git
 F:	drivers/hwmon/asus_atk0110.c
 ATLX ETHERNET DRIVERS
-M:	Jay Cliburn <jcliburn@gmail.com>
 M:	Chris Snook <chris.snook@gmail.com>
 L:	netdev@vger.kernel.org
 S:	Maintained
 F:	drivers/net/ethernet/broadcom/bnxt/
 BROADCOM BRCM80211 IEEE802.11n WIRELESS DRIVER
-M:	Arend van Spriel <arend.vanspriel@broadcom.com>
+M:	Arend van Spriel <aspriel@gmail.com>
 M:	Franky Lin <franky.lin@broadcom.com>
 M:	Hante Meuleman <hante.meuleman@broadcom.com>
 M:	Chi-hsien Lin <chi-hsien.lin@infineon.com>
 CADENCE USB3 DRD IP DRIVER
 M:	Peter Chen <peter.chen@nxp.com>
 M:	Pawel Laszczak <pawell@cadence.com>
-M:	Roger Quadros <rogerq@ti.com>
+R:	Roger Quadros <rogerq@kernel.org>
 R:	Aswath Govindraju <a-govindraju@ti.com>
 L:	linux-usb@vger.kernel.org
 S:	Maintained
 CAN-J1939 NETWORK LAYER
 M:	Robin van der Gracht <robin@protonic.nl>
 M:	Oleksij Rempel <o.rempel@pengutronix.de>
-R:	Pengutronix Kernel Team <kernel@pengutronix.de>
+R:	kernel@pengutronix.de
 L:	linux-can@vger.kernel.org
 S:	Maintained
 F:	Documentation/networking/j1939.rst
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git
 F:	Documentation/admin-guide/pm/cpuidle.rst
 F:	Documentation/driver-api/pm/cpuidle.rst
-F:	drivers/cpuidle/*
+F:	drivers/cpuidle/
 F:	include/linux/cpuidle.h
 CPU POWER MONITORING SUBSYSTEM
 F:	drivers/scsi/dc395x.*
 DCCP PROTOCOL
-M:	Gerrit Renker <gerrit@erg.abdn.ac.uk>
 L:	dccp@vger.kernel.org
-S:	Maintained
+S:	Orphan
 W:	http://www.linuxfoundation.org/collaborate/workgroups/networking/dccp
 F:	include/linux/dccp.h
 F:	include/linux/tfrc.h
 S:	Maintained
 F:	Documentation/kbuild/gcc-plugins.rst
 F:	scripts/Makefile.gcc-plugins
-F:	scripts/gcc-plugin.sh
 F:	scripts/gcc-plugins/
 GCOV BASED KERNEL PROFILING
 K:	\bSGX_
 INTERCONNECT API
-M:	Georgi Djakov <georgi.djakov@linaro.org>
+M:	Georgi Djakov <djakov@kernel.org>
 L:	linux-pm@vger.kernel.org
 S:	Maintained
 F:	Documentation/devicetree/bindings/interconnect/
 IOMAP FILESYSTEM LIBRARY
 M:	Christoph Hellwig <hch@infradead.org>
-M:	Darrick J. Wong <darrick.wong@oracle.com>
+M:	Darrick J. Wong <djwong@kernel.org>
 M:	linux-xfs@vger.kernel.org
 M:	linux-fsdevel@vger.kernel.org
 L:	linux-xfs@vger.kernel.org
 F:	drivers/scsi/ips*
 IPVS
-M:	Wensong Zhang <wensong@linux-vs.org>
 M:	Simon Horman <horms@verge.net.au>
 M:	Julian Anastasov <ja@ssi.bg>
 L:	netdev@vger.kernel.org
 KERNEL VIRTUAL MACHINE FOR X86 (KVM/x86)
 M:	Paolo Bonzini <pbonzini@redhat.com>
-R:	Sean Christopherson <sean.j.christopherson@intel.com>
+R:	Sean Christopherson <seanjc@google.com>
 R:	Vitaly Kuznetsov <vkuznets@redhat.com>
 R:	Wanpeng Li <wanpengli@tencent.com>
 R:	Jim Mattson <jmattson@google.com>
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/paulmck/linux-rcu.git dev
 F:	Documentation/atomic_bitops.txt
 F:	Documentation/atomic_t.txt
-F:	Documentation/core-api/atomic_ops.rst
 F:	Documentation/core-api/refcount-vs-atomic.rst
 F:	Documentation/litmus-tests/
 F:	Documentation/memory-barriers.txt
 MCAN MMIO DEVICE DRIVER
 M:	Dan Murphy <dmurphy@ti.com>
-M:	Sriram Dash <sriram.dash@samsung.com>
+M:	Pankaj Sharma <pankj.sharma@samsung.com>
 L:	linux-can@vger.kernel.org
 S:	Maintained
 F:	Documentation/devicetree/bindings/net/can/bosch,m_can.yaml
 MICROCHIP KSZ SERIES ETHERNET SWITCH DRIVER
 M:	Woojung Huh <woojung.huh@microchip.com>
-M:	Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>
+M:	UNGLinuxDriver@microchip.com
 L:	netdev@vger.kernel.org
 S:	Maintained
 F:	Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml
 MICROCHIP LAN743X ETHERNET DRIVER
 M:	Bryan Whitehead <bryan.whitehead@microchip.com>
-M:	Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>
+M:	UNGLinuxDriver@microchip.com
 L:	netdev@vger.kernel.org
 S:	Maintained
 F:	drivers/net/ethernet/microchip/lan743x_*
 MICROSEMI MIPS SOCS
 M:	Alexandre Belloni <alexandre.belloni@bootlin.com>
-M:	Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>
+M:	UNGLinuxDriver@microchip.com
 L:	linux-mips@vger.kernel.org
 S:	Supported
 F:	Documentation/devicetree/bindings/mips/mscc.txt
 NETWORKING [IPv4/IPv6]
 M:	"David S. Miller" <davem@davemloft.net>
-M:	Alexey Kuznetsov <kuznet@ms2.inr.ac.ru>
 M:	Hideaki YOSHIFUJI <yoshfuji@linux-ipv6.org>
 L:	netdev@vger.kernel.org
 S:	Maintained
 NETWORKING [TLS]
 M:	Boris Pismenny <borisp@nvidia.com>
-M:	Aviad Yehezkel <aviadye@nvidia.com>
 M:	John Fastabend <john.fastabend@gmail.com>
 M:	Daniel Borkmann <daniel@iogearbox.net>
 M:	Jakub Kicinski <kuba@kernel.org>
 F:	include/linux/objtool.h
 OCELOT ETHERNET SWITCH DRIVER
-M:	Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>
 M:	Vladimir Oltean <vladimir.oltean@nxp.com>
 M:	Claudiu Manoil <claudiu.manoil@nxp.com>
 M:	Alexandre Belloni <alexandre.belloni@bootlin.com>
+M:	UNGLinuxDriver@microchip.com
 L:	netdev@vger.kernel.org
 S:	Supported
 F:	drivers/net/dsa/ocelot/*
 F:	include/uapi/misc/ocxl.h
 OMAP AUDIO SUPPORT
-M:	Peter Ujfalusi <peter.ujfalusi@ti.com>
+M:	Peter Ujfalusi <peter.ujfalusi@gmail.com>
 M:	Jarkko Nikula <jarkko.nikula@bitmer.com>
 L:	alsa-devel@alsa-project.org (moderated for non-subscribers)
 L:	linux-omap@vger.kernel.org
 PENSANDO ETHERNET DRIVERS
 M:	Shannon Nelson <snelson@pensando.io>
-M:	Pensando Drivers <drivers@pensando.io>
+M:	drivers@pensando.io
 L:	netdev@vger.kernel.org
 S:	Supported
 F:	Documentation/networking/device_drivers/ethernet/pensando/ionic.rst
 F:	drivers/net/wireless/ath/ath11k/
 QUALCOMM ATHEROS ATH9K WIRELESS DRIVER
-M:	QCA ath9k Development <ath9k-devel@qca.qualcomm.com>
+M:	ath9k-devel@qca.qualcomm.com
 L:	linux-wireless@vger.kernel.org
 S:	Supported
 W:	https://wireless.wiki.kernel.org/en/users/Drivers/ath9k
 M:	Christian König <christian.koenig@amd.com>
 L:	amd-gfx@lists.freedesktop.org
 S:	Supported
-T:	git git://people.freedesktop.org/~agd5f/linux
+T:	git https://gitlab.freedesktop.org/agd5f/linux.git
 F:	drivers/gpu/drm/amd/
 F:	drivers/gpu/drm/radeon/
 F:	include/uapi/drm/amdgpu_drm.h
 M:	David Rientjes <rientjes@google.com>
 M:	Joonsoo Kim <iamjoonsoo.kim@lge.com>
 M:	Andrew Morton <akpm@linux-foundation.org>
+M:	Vlastimil Babka <vbabka@suse.cz>
 L:	linux-mm@kvack.org
 S:	Maintained
 F:	include/linux/sl?b*.h
 L:	speakup@linux-speakup.org
 S:	Odd Fixes
 W:	http://www.linux-speakup.org/
+W:	https://github.com/linux-speakup/speakup
+B:	https://github.com/linux-speakup/speakup/issues
 F:	drivers/accessibility/speakup/
 SPEAR CLOCK FRAMEWORK SUPPORT
 F:	drivers/irqchip/irq-xtensa-*
 TEXAS INSTRUMENTS ASoC DRIVERS
-M:	Peter Ujfalusi <peter.ujfalusi@ti.com>
+M:	Peter Ujfalusi <peter.ujfalusi@gmail.com>
 L:	alsa-devel@alsa-project.org (moderated for non-subscribers)
 S:	Maintained
 F:	sound/soc/ti/
 F:	Documentation/devicetree/bindings/iio/dac/ti,dac7612.txt
 F:	drivers/iio/dac/ti-dac7612.c
+TEXAS INSTRUMENTS DMA DRIVERS
+M:	Peter Ujfalusi <peter.ujfalusi@gmail.com>
+L:	dmaengine@vger.kernel.org
+S:	Maintained
+F:	Documentation/devicetree/bindings/dma/ti-dma-crossbar.txt
+F:	Documentation/devicetree/bindings/dma/ti-edma.txt
+F:	Documentation/devicetree/bindings/dma/ti/
+F:	drivers/dma/ti/
+X:	drivers/dma/ti/cppi41.c
+F:	include/linux/dma/k3-udma-glue.h
+F:	include/linux/dma/ti-cppi5.h
+F:	include/linux/dma/k3-psil.h
 TEXAS INSTRUMENTS' SYSTEM CONTROL INTERFACE (TISCI) PROTOCOL DRIVER
 M:	Nishanth Menon <nm@ti.com>
 M:	Tero Kristo <t-kristo@ti.com>
 F:	drivers/nfc/trf7970a.c
 TI TWL4030 SERIES SOC CODEC DRIVER
-M:	Peter Ujfalusi <peter.ujfalusi@ti.com>
+M:	Peter Ujfalusi <peter.ujfalusi@gmail.com>
 L:	alsa-devel@alsa-project.org (moderated for non-subscribers)
 S:	Maintained
 F:	sound/soc/codecs/twl4030*
 USB LAN78XX ETHERNET DRIVER
 M:	Woojung Huh <woojung.huh@microchip.com>
-M:	Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>
+M:	UNGLinuxDriver@microchip.com
 L:	netdev@vger.kernel.org
 S:	Maintained
 F:	Documentation/devicetree/bindings/net/microchip,lan78xx.txt
 USB SMSC95XX ETHERNET DRIVER
 M:	Steve Glendinning <steve.glendinning@shawell.net>
-M:	Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>
+M:	UNGLinuxDriver@microchip.com
 L:	netdev@vger.kernel.org
 S:	Maintained
 F:	drivers/net/usb/smsc95xx.*
 VMWARE VMXNET3 ETHERNET DRIVER
 M:	Ronak Doshi <doshir@vmware.com>
-M:	"VMware, Inc." <pv-drivers@vmware.com>
+M:	pv-drivers@vmware.com
 L:	netdev@vger.kernel.org
 S:	Maintained
 F:	drivers/net/vmxnet3/
 VRF
 M:	David Ahern <dsahern@kernel.org>
-M:	Shrijeet Mukherjee <shrijeet@gmail.com>
 L:	netdev@vger.kernel.org
 S:	Maintained
 F:	Documentation/networking/vrf.rst
 F:	drivers/xen/*swiotlb*
 XFS FILESYSTEM
-M:	Darrick J. Wong <darrick.wong@oracle.com>
+M:	Darrick J. Wong <djwong@kernel.org>
 M:	linux-xfs@vger.kernel.org
 L:	linux-xfs@vger.kernel.org
 S:	Supported

Makefile+1−1

@@ -2,7 +2,7 @@ · 1 unmodified line
2	VERSION = 5	2	VERSION = 5
3	PATCHLEVEL = 11	3	PATCHLEVEL = 11
4	SUBLEVEL = 0	4	SUBLEVEL = 0
5	EXTRAVERSION = -rc1	5	EXTRAVERSION = -rc4
6	NAME = Kleptomaniac Octopus	6	NAME = Kleptomaniac Octopus
7		7
8	# DOCUMENTATION	8	# DOCUMENTATION

arch/Kconfig+6−0

 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
 	bool
+config ARCH_SPLIT_ARG64
+	bool
+	help
+	   If a 32-bit architecture requires 64-bit arguments to be split into
+	   pairs of 32-bit arguments, select this option.
 source "kernel/gcov/Kconfig"
 source "scripts/gcc-plugins/Kconfig"

arch/alpha/include/asm/local64.h+0−1

@@ -1 +0,0 @@
1	#include <asm-generic/local64.h>

arch/arc/Makefile+13−7

 boot		:= arch/arc/boot
-#default target for make without any arguments.
+boot_targets := uImage.bin uImage.gz uImage.lzma
-KBUILD_IMAGE	:= $(boot)/bootpImage
-all:	bootpImage
-bootpImage: vmlinux
-boot_targets += uImage uImage.bin uImage.gz
+PHONY += $(boot_targets)
 $(boot_targets): vmlinux
 	$(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
+uimage-default-y			:= uImage.bin
+uimage-default-$(CONFIG_KERNEL_GZIP)	:= uImage.gz
+uimage-default-$(CONFIG_KERNEL_LZMA)	:= uImage.lzma
+PHONY += uImage
+uImage: $(uimage-default-y)
+	@ln -sf $< $(boot)/uImage
+	@$(kecho) '  Image $(boot)/uImage is ready'
+CLEAN_FILES += $(boot)/uImage
 archclean:
 	$(Q)$(MAKE) $(clean)=$(boot)

arch/arc/boot/Makefile+4−14

 # SPDX-License-Identifier: GPL-2.0
-targets := vmlinux.bin vmlinux.bin.gz uImage
 # uImage build relies on mkimage being availble on your host for ARC target
 # You will need to build u-boot for ARC, rename mkimage to arc-elf32-mkimage
 OBJCOPYFLAGS= -O binary -R .note -R .note.gnu.build-id -R .comment -S
-LINUX_START_TEXT = $$(readelf -h vmlinux | \
+LINUX_START_TEXT = $$($(READELF) -h vmlinux | \
 			grep "Entry point address" | grep -o 0x.*)
 UIMAGE_LOADADDR    = $(CONFIG_LINUX_LINK_BASE)
 UIMAGE_ENTRYADDR   = $(LINUX_START_TEXT)
-suffix-y := bin
+targets += vmlinux.bin
-suffix-$(CONFIG_KERNEL_GZIP)	:= gz
+targets += vmlinux.bin.gz
-suffix-$(CONFIG_KERNEL_LZMA)	:= lzma
+targets += vmlinux.bin.lzma
-targets += uImage
 targets += uImage.bin
 targets += uImage.gz
 targets += uImage.lzma
-extra-y += vmlinux.bin
-extra-y += vmlinux.bin.gz
-extra-y += vmlinux.bin.lzma
 $(obj)/vmlinux.bin: vmlinux FORCE
 	$(call if_changed,objcopy)
 $(obj)/uImage.lzma: $(obj)/vmlinux.bin.lzma FORCE
 	$(call if_changed,uimage,lzma)
-$(obj)/uImage: $(obj)/uImage.$(suffix-y)
-	@ln -sf $(notdir $<) $@
-	@echo '  Image $@ is ready'

arch/arc/include/asm/Kbuild+0−1

@@ -1,7 +1,6 @@
1	# SPDX-License-Identifier: GPL-2.0	1	# SPDX-License-Identifier: GPL-2.0
2	generic-y += extable.h	2	generic-y += extable.h
3	generic-y += kvm_para.h	3	generic-y += kvm_para.h
4	generic-y += local64.h
5	generic-y += mcs_spinlock.h	4	generic-y += mcs_spinlock.h
6	generic-y += parport.h	5	generic-y += parport.h
7	generic-y += user.h	6	generic-y += user.h

arch/arc/include/asm/page.h+1−0

@@ -10,6 +10,7 @@ · 9 unmodified lines
10	#ifndef __ASSEMBLY__	10	#ifndef __ASSEMBLY__
11		11
12	#define clear_page(paddr) memset((paddr), 0, PAGE_SIZE)	12	#define clear_page(paddr) memset((paddr), 0, PAGE_SIZE)
		13	#define copy_user_page(to, from, vaddr, pg) copy_page(to, from)
13	#define copy_page(to, from) memcpy((to), (from), PAGE_SIZE)	14	#define copy_page(to, from) memcpy((to), (from), PAGE_SIZE)
14		15
15	struct vm_area_struct;	16	struct vm_area_struct;

arch/arc/kernel/entry.S+1−1

@@ -307,7 +307,7 @@ resume_user_mode_begin: · 306 unmodified lines
307	mov r0, sp ; pt_regs for arg to do_signal()/do_notify_resume()	307	mov r0, sp ; pt_regs for arg to do_signal()/do_notify_resume()
308		308
309	GET_CURR_THR_INFO_FLAGS r9	309	GET_CURR_THR_INFO_FLAGS r9
310	and.f 0, r9, TIF_SIGPENDING\|TIF_NOTIFY_SIGNAL	310	and.f 0, r9, _TIF_SIGPENDING\|_TIF_NOTIFY_SIGNAL
311	bz .Lchk_notify_resume	311	bz .Lchk_notify_resume
312		312
313	; Normal Trap/IRQ entry only saves Scratch (caller-saved) regs	313	; Normal Trap/IRQ entry only saves Scratch (caller-saved) regs

arch/arc/plat-hsdk/Kconfig+1−0

@@ -7,6 +7,7 @@ menuconfig ARC_SOC_HSDK · 6 unmodified lines
7	depends on ISA_ARCV2	7	depends on ISA_ARCV2
8	select ARC_HAS_ACCL_REGS	8	select ARC_HAS_ACCL_REGS
9	select ARC_IRQ_NO_AUTOSAVE	9	select ARC_IRQ_NO_AUTOSAVE
		10	select ARC_FPU_SAVE_RESTORE
10	select CLK_HSDK	11	select CLK_HSDK
11	select RESET_CONTROLLER	12	select RESET_CONTROLLER
12	select RESET_HSDK	13	select RESET_HSDK

arch/arm/boot/dts/omap3-n950-n9.dtsi+8−0

@@ -494,3 +494,11 @@ · 493 unmodified lines
494	clock-names = "sysclk";	494	clock-names = "sysclk";
495	};	495	};
496	};	496	};
		497
		498	&aes1_target {
		499	status = "disabled";
		500	};
		501
		502	&aes2_target {
		503	status = "disabled";
		504	};

arch/arm/boot/dts/picoxcell-pc3x2.dtsi+4−0

 		emac: gem@30000 {
 			compatible = "cadence,gem";
 			reg = <0x30000 0x10000>;
+			interrupt-parent = <&vic0>;
 			interrupts = <31>;
 		};
 		dmac1: dmac@40000 {
 			compatible = "snps,dw-dmac";
 			reg = <0x40000 0x10000>;
+			interrupt-parent = <&vic0>;
 			interrupts = <25>;
 		};
 		dmac2: dmac@50000 {
 			compatible = "snps,dw-dmac";
 			reg = <0x50000 0x10000>;
+			interrupt-parent = <&vic0>;
 			interrupts = <26>;
 		};
 		axi2pico@c0000000 {
 			compatible = "picochip,axi2pico-pc3x2";
 			reg = <0xc0000000 0x10000>;
+			interrupt-parent = <&vic0>;
 			interrupts = <13 14 15 16 17 18 19 20 21>;
 		};
 	};

arch/arm/boot/dts/ste-ux500-samsung-golden.dts+1−0

@@ -329,6 +329,7 @@ · 328 unmodified lines
329	panel@0 {	329	panel@0 {
330	compatible = "samsung,s6e63m0";	330	compatible = "samsung,s6e63m0";
331	reg = <0>;	331	reg = <0>;
		332	max-brightness = <15>;
332	vdd3-supply = <&panel_reg_3v0>;	333	vdd3-supply = <&panel_reg_3v0>;
333	vci-supply = <&panel_reg_1v8>;	334	vci-supply = <&panel_reg_1v8>;
334	reset-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;	335	reset-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;

arch/arm/configs/omap2plus_defconfig+1−1

 CONFIG_SERIAL_DEV_BUS=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_SPI=y
+CONFIG_SPI_GPIO=m
 CONFIG_SPI_OMAP24XX=y
 CONFIG_SPI_TI_QSPI=m
 CONFIG_HSI=m
 CONFIG_W1=m
 CONFIG_HDQ_MASTER_OMAP=m
 CONFIG_W1_SLAVE_DS250X=m
-CONFIG_POWER_AVS=y
 CONFIG_POWER_RESET=y
 CONFIG_POWER_RESET_GPIO=y
 CONFIG_BATTERY_BQ27XXX=m

arch/arm/crypto/chacha-glue.c+1−0

@@ -60,6 +60,7 @@ static void chacha_doneon(u32 state, u8 dst, const u8 *src, · 59 unmodified lines
60	chacha_block_xor_neon(state, d, s, nrounds);	60	chacha_block_xor_neon(state, d, s, nrounds);
61	if (d != dst)	61	if (d != dst)
62	memcpy(dst, buf, bytes);	62	memcpy(dst, buf, bytes);
		63	state[12]++;
63	}	64	}
64	}	65	}
65		66

arch/arm/include/asm/Kbuild+0−1

@@ -2,7 +2,6 @@ · 1 unmodified line
2	generic-y += early_ioremap.h	2	generic-y += early_ioremap.h
3	generic-y += extable.h	3	generic-y += extable.h
4	generic-y += flat.h	4	generic-y += flat.h
5	generic-y += local64.h
6	generic-y += parport.h	5	generic-y += parport.h
7		6
8	generated-y += mach-types.h	7	generated-y += mach-types.h

arch/arm/mach-omap2/omap_device.c+5−3

 		break;
 	case BUS_NOTIFY_BIND_DRIVER:
 		od = to_omap_device(pdev);
-		if (od && (od->_state == OMAP_DEVICE_STATE_ENABLED) &&
+		if (od) {
-		    pm_runtime_status_suspended(dev)) {
 			od->_driver_status = BUS_NOTIFY_BIND_DRIVER;
-			pm_runtime_set_active(dev);
+			if (od->_state == OMAP_DEVICE_STATE_ENABLED &&
+			    pm_runtime_status_suspended(dev)) {
+				pm_runtime_set_active(dev);
+			}
 		}
 		break;
 	case BUS_NOTIFY_ADD_DEVICE:

arch/arm/mach-omap2/pmic-cpcap.c+1−1

@@ -71,7 +71,7 @@ static struct omap_voltdm_pmic omap_cpcap_iva = { · 70 unmodified lines
71	.vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,	71	.vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
72	.vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX,	72	.vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX,
73	.vddmin = 900000,	73	.vddmin = 900000,
74	.vddmax = 1350000,	74	.vddmax = 1375000,
75	.vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,	75	.vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
76	.i2c_slave_addr = 0x44,	76	.i2c_slave_addr = 0x44,
77	.volt_reg_addr = 0x0,	77	.volt_reg_addr = 0x0,

arch/arm/xen/enlighten.c+1−1

@@ -371,7 +371,7 @@ static int __init xen_guest_init(void) · 370 unmodified lines
371	}	371	}
372	gnttab_init();	372	gnttab_init();
373	if (!xen_initial_domain())	373	if (!xen_initial_domain())
374	xenbus_probe(NULL);	374	xenbus_probe();
375		375
376	/*	376	/*
377	* Making sure board specific code will not set up ops for	377	* Making sure board specific code will not set up ops for

arch/arm64/Kconfig+0−2

 	select HAVE_NMI
 	select HAVE_PATA_PLATFORM
 	select HAVE_PERF_EVENTS
-	select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI && HW_PERF_EVENTS
-	select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && HAVE_PERF_EVENTS_NMI
 	select HAVE_PERF_REGS
 	select HAVE_PERF_USER_STACK_DUMP
 	select HAVE_REGS_AND_STACK_ACCESS_API

arch/arm64/Makefile+7−3

 #
 # Copyright (C) 1995-2001 by Russell King
-LDFLAGS_vmlinux	:=--no-undefined -X -z norelro
+LDFLAGS_vmlinux	:=--no-undefined -X
 ifeq ($(CONFIG_RELOCATABLE), y)
 # Pass --no-apply-dynamic-relocs to restore pre-binutils-2.27 behaviour
 CHECKFLAGS	+= -D__AARCH64EB__
 # Prefer the baremetal ELF build target, but not all toolchains include
 # it so fall back to the standard linux version if needed.
-KBUILD_LDFLAGS	+= -EB $(call ld-option, -maarch64elfb, -maarch64linuxb)
+KBUILD_LDFLAGS	+= -EB $(call ld-option, -maarch64elfb, -maarch64linuxb -z norelro)
 UTS_MACHINE	:= aarch64_be
 else
 KBUILD_CPPFLAGS	+= -mlittle-endian
 CHECKFLAGS	+= -D__AARCH64EL__
 # Same as above, prefer ELF but fall back to linux target if needed.
-KBUILD_LDFLAGS	+= -EL $(call ld-option, -maarch64elf, -maarch64linux)
+KBUILD_LDFLAGS	+= -EL $(call ld-option, -maarch64elf, -maarch64linux -z norelro)
 UTS_MACHINE	:= aarch64
 endif
+ifeq ($(CONFIG_LD_IS_LLD), y)
+KBUILD_LDFLAGS	+= -z norelro
+endif
 CHECKFLAGS	+= -D__aarch64__
 ifeq ($(CONFIG_DYNAMIC_FTRACE_WITH_REGS),y)

arch/arm64/boot/dts/bitmain/bm1880.dtsi+3−3

@@ -127,7 +127,7 @@ · 126 unmodified lines
127	compatible = "snps,dw-apb-gpio-port";	127	compatible = "snps,dw-apb-gpio-port";
128	gpio-controller;	128	gpio-controller;
129	#gpio-cells = <2>;	129	#gpio-cells = <2>;
130	snps,nr-gpios = <32>;	130	ngpios = <32>;
131	reg = <0>;	131	reg = <0>;
132	interrupt-controller;	132	interrupt-controller;
133	#interrupt-cells = <2>;	133	#interrupt-cells = <2>;
@@ -145,7 +145,7 @@ · 11 unmodified lines
145	compatible = "snps,dw-apb-gpio-port";	145	compatible = "snps,dw-apb-gpio-port";
146	gpio-controller;	146	gpio-controller;
147	#gpio-cells = <2>;	147	#gpio-cells = <2>;
148	snps,nr-gpios = <32>;	148	ngpios = <32>;
149	reg = <0>;	149	reg = <0>;
150	interrupt-controller;	150	interrupt-controller;
151	#interrupt-cells = <2>;	151	#interrupt-cells = <2>;
@@ -163,7 +163,7 @@ · 11 unmodified lines
163	compatible = "snps,dw-apb-gpio-port";	163	compatible = "snps,dw-apb-gpio-port";
164	gpio-controller;	164	gpio-controller;
165	#gpio-cells = <2>;	165	#gpio-cells = <2>;
166	snps,nr-gpios = <8>;	166	ngpios = <8>;
167	reg = <0>;	167	reg = <0>;
168	interrupt-controller;	168	interrupt-controller;
169	#interrupt-cells = <2>;	169	#interrupt-cells = <2>;

arch/arm64/include/asm/Kbuild+0−1

@@ -1,6 +1,5 @@
1	# SPDX-License-Identifier: GPL-2.0	1	# SPDX-License-Identifier: GPL-2.0
2	generic-y += early_ioremap.h	2	generic-y += early_ioremap.h
3	generic-y += local64.h
4	generic-y += mcs_spinlock.h	3	generic-y += mcs_spinlock.h
5	generic-y += qrwlock.h	4	generic-y += qrwlock.h
6	generic-y += qspinlock.h	5	generic-y += qspinlock.h

arch/arm64/include/asm/atomic.h+5−5

@@ -17,7 +17,7 @@ · 16 unmodified lines
17	#include <asm/lse.h>	17	#include <asm/lse.h>
18		18
19	#define ATOMIC_OP(op) \	19	#define ATOMIC_OP(op) \
20	static inline void arch_##op(int i, atomic_t *v) \	20	static __always_inline void arch_##op(int i, atomic_t *v) \
21	{ \	21	{ \
22	__lse_ll_sc_body(op, i, v); \	22	__lse_ll_sc_body(op, i, v); \
23	}	23	}
@@ -32,7 +32,7 @@ ATOMIC_OP(atomic_sub) · 8 unmodified lines
32	#undef ATOMIC_OP	32	#undef ATOMIC_OP
33		33
34	#define ATOMIC_FETCH_OP(name, op) \	34	#define ATOMIC_FETCH_OP(name, op) \
35	static inline int arch_##op##name(int i, atomic_t *v) \	35	static __always_inline int arch_##op##name(int i, atomic_t *v) \
36	{ \	36	{ \
37	return __lse_ll_sc_body(op##name, i, v); \	37	return __lse_ll_sc_body(op##name, i, v); \
38	}	38	}
@@ -56,7 +56,7 @@ ATOMIC_FETCH_OPS(atomic_sub_return) · 17 unmodified lines
56	#undef ATOMIC_FETCH_OPS	56	#undef ATOMIC_FETCH_OPS
57		57
58	#define ATOMIC64_OP(op) \	58	#define ATOMIC64_OP(op) \
59	static inline void arch_##op(long i, atomic64_t *v) \	59	static __always_inline void arch_##op(long i, atomic64_t *v) \
60	{ \	60	{ \
61	__lse_ll_sc_body(op, i, v); \	61	__lse_ll_sc_body(op, i, v); \
62	}	62	}
@@ -71,7 +71,7 @@ ATOMIC64_OP(atomic64_sub) · 8 unmodified lines
71	#undef ATOMIC64_OP	71	#undef ATOMIC64_OP
72		72
73	#define ATOMIC64_FETCH_OP(name, op) \	73	#define ATOMIC64_FETCH_OP(name, op) \
74	static inline long arch_##op##name(long i, atomic64_t *v) \	74	static __always_inline long arch_##op##name(long i, atomic64_t *v) \
75	{ \	75	{ \
76	return __lse_ll_sc_body(op##name, i, v); \	76	return __lse_ll_sc_body(op##name, i, v); \
77	}	77	}
@@ -94,7 +94,7 @@ ATOMIC64_FETCH_OPS(atomic64_sub_return) · 16 unmodified lines
94	#undef ATOMIC64_FETCH_OP	94	#undef ATOMIC64_FETCH_OP
95	#undef ATOMIC64_FETCH_OPS	95	#undef ATOMIC64_FETCH_OPS
96		96
97	static inline long arch_atomic64_dec_if_positive(atomic64_t *v)	97	static __always_inline long arch_atomic64_dec_if_positive(atomic64_t *v)
98	{	98	{
99	return __lse_ll_sc_body(atomic64_dec_if_positive, v);	99	return __lse_ll_sc_body(atomic64_dec_if_positive, v);
100	}	100	}

arch/arm64/include/asm/kvm_host.h+23−0

@@ -17,6 +17,7 @@ · 16 unmodified lines
17	#include <linux/jump_label.h>	17	#include <linux/jump_label.h>
18	#include <linux/kvm_types.h>	18	#include <linux/kvm_types.h>
19	#include <linux/percpu.h>	19	#include <linux/percpu.h>
		20	#include <linux/psci.h>
20	#include <asm/arch_gicv3.h>	21	#include <asm/arch_gicv3.h>
21	#include <asm/barrier.h>	22	#include <asm/barrier.h>
22	#include <asm/cpufeature.h>	23	#include <asm/cpufeature.h>
@@ -240,6 +241,28 @@ struct kvm_host_data { · 217 unmodified lines
240	struct kvm_pmu_events pmu_events;	241	struct kvm_pmu_events pmu_events;
241	};	242	};
242		243
		244	struct kvm_host_psci_config {
		245	/* PSCI version used by host. */
		246	u32 version;
		247
		248	/* Function IDs used by host if version is v0.1. */
		249	struct psci_0_1_function_ids function_ids_0_1;
		250
		251	bool psci_0_1_cpu_suspend_implemented;
		252	bool psci_0_1_cpu_on_implemented;
		253	bool psci_0_1_cpu_off_implemented;
		254	bool psci_0_1_migrate_implemented;
		255	};
		256
		257	extern struct kvm_host_psci_config kvm_nvhe_sym(kvm_host_psci_config);
		258	#define kvm_host_psci_config CHOOSE_NVHE_SYM(kvm_host_psci_config)
		259
		260	extern s64 kvm_nvhe_sym(hyp_physvirt_offset);
		261	#define hyp_physvirt_offset CHOOSE_NVHE_SYM(hyp_physvirt_offset)
		262
		263	extern u64 kvm_nvhe_sym(hyp_cpu_logical_map)[NR_CPUS];
		264	#define hyp_cpu_logical_map CHOOSE_NVHE_SYM(hyp_cpu_logical_map)
		265
243	struct vcpu_reset_state {	266	struct vcpu_reset_state {
244	unsigned long pc;	267	unsigned long pc;
245	unsigned long r0;	268	unsigned long r0;

arch/arm64/include/asm/uaccess.h+13−3

  * The Tag check override (TCO) bit disables temporarily the tag checking
  * preventing the issue.
  */
-static inline void uaccess_disable_privileged(void)
+static inline void __uaccess_disable_tco(void)
 {
 	asm volatile(ALTERNATIVE("nop", SET_PSTATE_TCO(0),
 				 ARM64_MTE, CONFIG_KASAN_HW_TAGS));
+}
+static inline void __uaccess_enable_tco(void)
+{
+	asm volatile(ALTERNATIVE("nop", SET_PSTATE_TCO(1),
+				 ARM64_MTE, CONFIG_KASAN_HW_TAGS));
+}
+static inline void uaccess_disable_privileged(void)
+{
+	__uaccess_disable_tco();
 	if (uaccess_ttbr0_disable())
 		return;
 static inline void uaccess_enable_privileged(void)
 {
-	asm volatile(ALTERNATIVE("nop", SET_PSTATE_TCO(1),
+	__uaccess_enable_tco();
-				 ARM64_MTE, CONFIG_KASAN_HW_TAGS));
 	if (uaccess_ttbr0_enable())
 		return;

arch/arm64/kernel/asm-offsets.c+1−1

@@ -75,7 +75,7 @@ int main(void) · 74 unmodified lines
75	DEFINE(S_SDEI_TTBR1, offsetof(struct pt_regs, sdei_ttbr1));	75	DEFINE(S_SDEI_TTBR1, offsetof(struct pt_regs, sdei_ttbr1));
76	DEFINE(S_PMR_SAVE, offsetof(struct pt_regs, pmr_save));	76	DEFINE(S_PMR_SAVE, offsetof(struct pt_regs, pmr_save));
77	DEFINE(S_STACKFRAME, offsetof(struct pt_regs, stackframe));	77	DEFINE(S_STACKFRAME, offsetof(struct pt_regs, stackframe));
78	DEFINE(S_FRAME_SIZE, sizeof(struct pt_regs));	78	DEFINE(PT_REGS_SIZE, sizeof(struct pt_regs));
79	BLANK();	79	BLANK();
80	#ifdef CONFIG_COMPAT	80	#ifdef CONFIG_COMPAT
81	DEFINE(COMPAT_SIGFRAME_REGS_OFFSET, offsetof(struct compat_sigframe, uc.uc_mcontext.arm_r0));	81	DEFINE(COMPAT_SIGFRAME_REGS_OFFSET, offsetof(struct compat_sigframe, uc.uc_mcontext.arm_r0));

arch/arm64/kernel/cpufeature.c+1−1

@@ -2568,7 +2568,7 @@ static void verify_hyp_capabilities(void) · 2567 unmodified lines
2568	int parange, ipa_max;	2568	int parange, ipa_max;
2569	unsigned int safe_vmid_bits, vmid_bits;	2569	unsigned int safe_vmid_bits, vmid_bits;
2570		2570
2571	if (!IS_ENABLED(CONFIG_KVM) \|\| !IS_ENABLED(CONFIG_KVM_ARM_HOST))	2571	if (!IS_ENABLED(CONFIG_KVM))
2572	return;	2572	return;
2573		2573
2574	safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);	2574	safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);

arch/arm64/kernel/entry-ftrace.S+6−6

@@ -35,7 +35,7 @@ · 34 unmodified lines
35	*/	35	*/
36	.macro ftrace_regs_entry, allregs=0	36	.macro ftrace_regs_entry, allregs=0
37	/* Make room for pt_regs, plus a callee frame */	37	/* Make room for pt_regs, plus a callee frame */
38	sub sp, sp, #(S_FRAME_SIZE + 16)	38	sub sp, sp, #(PT_REGS_SIZE + 16)
39		39
40	/* Save function arguments (and x9 for simplicity) */	40	/* Save function arguments (and x9 for simplicity) */
41	stp x0, x1, [sp, #S_X0]	41	stp x0, x1, [sp, #S_X0]
@@ -61,15 +61,15 @@ · 19 unmodified lines
61	.endif	61	.endif
62		62
63	/* Save the callsite's SP and LR */	63	/* Save the callsite's SP and LR */
64	add x10, sp, #(S_FRAME_SIZE + 16)	64	add x10, sp, #(PT_REGS_SIZE + 16)
65	stp x9, x10, [sp, #S_LR]	65	stp x9, x10, [sp, #S_LR]
66		66
67	/* Save the PC after the ftrace callsite */	67	/* Save the PC after the ftrace callsite */
68	str x30, [sp, #S_PC]	68	str x30, [sp, #S_PC]
69		69
70	/* Create a frame record for the callsite above pt_regs */	70	/* Create a frame record for the callsite above pt_regs */
71	stp x29, x9, [sp, #S_FRAME_SIZE]	71	stp x29, x9, [sp, #PT_REGS_SIZE]
72	add x29, sp, #S_FRAME_SIZE	72	add x29, sp, #PT_REGS_SIZE
73		73
74	/* Create our frame record within pt_regs. */	74	/* Create our frame record within pt_regs. */
75	stp x29, x30, [sp, #S_STACKFRAME]	75	stp x29, x30, [sp, #S_STACKFRAME]
@@ -120,7 +120,7 @@ ftrace_common_return: · 44 unmodified lines
120	ldr x9, [sp, #S_PC]	120	ldr x9, [sp, #S_PC]
121		121
122	/* Restore the callsite's SP */	122	/* Restore the callsite's SP */
123	add sp, sp, #S_FRAME_SIZE + 16	123	add sp, sp, #PT_REGS_SIZE + 16
124		124
125	ret x9	125	ret x9
126	SYM_CODE_END(ftrace_common)	126	SYM_CODE_END(ftrace_common)
@@ -130,7 +130,7 @@ SYM_CODE_START(ftrace_graph_caller) · 3 unmodified lines
130	ldr x0, [sp, #S_PC]	130	ldr x0, [sp, #S_PC]
131	sub x0, x0, #AARCH64_INSN_SIZE // ip (callsite's BL insn)	131	sub x0, x0, #AARCH64_INSN_SIZE // ip (callsite's BL insn)
132	add x1, sp, #S_LR // parent_ip (callsite's LR)	132	add x1, sp, #S_LR // parent_ip (callsite's LR)
133	ldr x2, [sp, #S_FRAME_SIZE] // parent fp (callsite's FP)	133	ldr x2, [sp, #PT_REGS_SIZE] // parent fp (callsite's FP)
134	bl prepare_ftrace_return	134	bl prepare_ftrace_return
135	b ftrace_common_return	135	b ftrace_common_return
136	SYM_CODE_END(ftrace_graph_caller)	136	SYM_CODE_END(ftrace_graph_caller)

arch/arm64/kernel/entry.S+8−8

 	.endif
 #endif
-	sub	sp, sp, #S_FRAME_SIZE
+	sub	sp, sp, #PT_REGS_SIZE
 #ifdef CONFIG_VMAP_STACK
 	/*
 	 * Test whether the SP has overflowed, without corrupting a GPR.
 	 * userspace, and can clobber EL0 registers to free up GPRs.
 	 */
-	/* Stash the original SP (minus S_FRAME_SIZE) in tpidr_el0. */
+	/* Stash the original SP (minus PT_REGS_SIZE) in tpidr_el0. */
 	msr	tpidr_el0, x0
 	/* Recover the original x0 value and stash it in tpidrro_el0 */
 	mrs_s	\tmp2, SYS_GCR_EL1
 	bfi	\tmp2, \tmp, #0, #16
 	msr_s	SYS_GCR_EL1, \tmp2
-	isb
 #endif
 	.endm
 	ldr_l	\tmp, gcr_kernel_excl
 	mte_set_gcr \tmp, \tmp2
+	isb
 1:
 #endif
 	.endm
 	scs_load tsk, x20
 	.else
-	add	x21, sp, #S_FRAME_SIZE
+	add	x21, sp, #PT_REGS_SIZE
 	get_current_task tsk
 	.endif /* \el == 0 */
 	mrs	x22, elr_el1
 	ldp	x26, x27, [sp, #16 * 13]
 	ldp	x28, x29, [sp, #16 * 14]
 	ldr	lr, [sp, #S_LR]
-	add	sp, sp, #S_FRAME_SIZE		// restore sp
+	add	sp, sp, #PT_REGS_SIZE		// restore sp
 	.if	\el == 0
 alternative_insn eret, nop, ARM64_UNMAP_KERNEL_AT_EL0
 	/*
 	 * Store the original GPRs to the new stack. The orginal SP (minus
-	 * S_FRAME_SIZE) was stashed in tpidr_el0 by kernel_ventry.
+	 * PT_REGS_SIZE) was stashed in tpidr_el0 by kernel_ventry.
 	 */
-	sub	sp, sp, #S_FRAME_SIZE
+	sub	sp, sp, #PT_REGS_SIZE
 	kernel_entry 1
 	mrs	x0, tpidr_el0
-	add	x0, x0, #S_FRAME_SIZE
+	add	x0, x0, #PT_REGS_SIZE
 	str	x0, [sp, #S_SP]
 	/* Stash the regs for handle_bad_stack */

arch/arm64/kernel/perf_event.c+2−39

@@ -23,8 +23,6 @@ · 22 unmodified lines
23	#include <linux/platform_device.h>	23	#include <linux/platform_device.h>
24	#include <linux/sched_clock.h>	24	#include <linux/sched_clock.h>
25	#include <linux/smp.h>	25	#include <linux/smp.h>
26	#include <linux/nmi.h>
27	#include <linux/cpufreq.h>
28		26
29	/* ARMv8 Cortex-A53 specific event types. */	27	/* ARMv8 Cortex-A53 specific event types. */
30	#define ARMV8_A53_PERFCTR_PREF_LINEFILL 0xC2	28	#define ARMV8_A53_PERFCTR_PREF_LINEFILL 0xC2
@@ -1250,21 +1248,10 @@ static struct platform_driver armv8_pmu_driver = { · 1219 unmodified lines
1250		1248
1251	static int __init armv8_pmu_driver_init(void)	1249	static int __init armv8_pmu_driver_init(void)
1252	{	1250	{
1253	int ret;
1254
1255	if (acpi_disabled)	1251	if (acpi_disabled)
1256	ret = platform_driver_register(&armv8_pmu_driver);	1252	return platform_driver_register(&armv8_pmu_driver);
1257	else	1253	else
1258	ret = arm_pmu_acpi_probe(armv8_pmuv3_init);	1254	return arm_pmu_acpi_probe(armv8_pmuv3_init);
1259
1260	/*
1261	* Try to re-initialize lockup detector after PMU init in
1262	* case PMU events are triggered via NMIs.
1263	*/
1264	if (ret == 0 && arm_pmu_irq_is_nmi())
1265	lockup_detector_init();
1266
1267	return ret;
1268	}	1255	}
1269	device_initcall(armv8_pmu_driver_init)	1256	device_initcall(armv8_pmu_driver_init)
1270		1257
@@ -1322,27 +1309,3 @@ void arch_perf_update_userpage(struct perf_event *event, · 51 unmodified lines
1322	userpg->cap_user_time_zero = 1;	1309	userpg->cap_user_time_zero = 1;
1323	userpg->cap_user_time_short = 1;	1310	userpg->cap_user_time_short = 1;
1324	}	1311	}
1325
1326	#ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF
1327	/*
1328	* Safe maximum CPU frequency in case a particular platform doesn't implement
1329	* cpufreq driver. Although, architecture doesn't put any restrictions on
1330	* maximum frequency but 5 GHz seems to be safe maximum given the available
1331	* Arm CPUs in the market which are clocked much less than 5 GHz. On the other
1332	* hand, we can't make it much higher as it would lead to a large hard-lockup
1333	* detection timeout on parts which are running slower (eg. 1GHz on
1334	* Developerbox) and doesn't possess a cpufreq driver.
1335	*/
1336	#define SAFE_MAX_CPU_FREQ 5000000000UL // 5 GHz
1337	u64 hw_nmi_get_sample_period(int watchdog_thresh)
1338	{
1339	unsigned int cpu = smp_processor_id();
1340	unsigned long max_cpu_freq;
1341
1342	max_cpu_freq = cpufreq_get_hw_max_freq(cpu) * 1000UL;
1343	if (!max_cpu_freq)
1344	max_cpu_freq = SAFE_MAX_CPU_FREQ;
1345
1346	return (u64)max_cpu_freq * watchdog_thresh;
1347	}
1348	#endif

arch/arm64/kernel/probes/kprobes_trampoline.S+3−3

@@ -25,7 +25,7 @@ · 24 unmodified lines
25	stp x24, x25, [sp, #S_X24]	25	stp x24, x25, [sp, #S_X24]
26	stp x26, x27, [sp, #S_X26]	26	stp x26, x27, [sp, #S_X26]
27	stp x28, x29, [sp, #S_X28]	27	stp x28, x29, [sp, #S_X28]
28	add x0, sp, #S_FRAME_SIZE	28	add x0, sp, #PT_REGS_SIZE
29	stp lr, x0, [sp, #S_LR]	29	stp lr, x0, [sp, #S_LR]
30	/*	30	/*
31	* Construct a useful saved PSTATE	31	* Construct a useful saved PSTATE
@@ -62,7 +62,7 @@ · 30 unmodified lines
62	.endm	62	.endm
63		63
64	SYM_CODE_START(kretprobe_trampoline)	64	SYM_CODE_START(kretprobe_trampoline)
65	sub sp, sp, #S_FRAME_SIZE	65	sub sp, sp, #PT_REGS_SIZE
66		66
67	save_all_base_regs	67	save_all_base_regs
68		68
@@ -76,7 +76,7 @@ SYM_CODE_START(kretprobe_trampoline) · 7 unmodified lines
76		76
77	restore_all_base_regs	77	restore_all_base_regs
78		78
79	add sp, sp, #S_FRAME_SIZE	79	add sp, sp, #PT_REGS_SIZE
80	ret	80	ret
81		81
82	SYM_CODE_END(kretprobe_trampoline)	82	SYM_CODE_END(kretprobe_trampoline)

arch/arm64/kernel/signal.c+0−7

@@ -914,13 +914,6 @@ static void do_signal(struct pt_regs *regs) · 913 unmodified lines
914	asmlinkage void do_notify_resume(struct pt_regs *regs,	914	asmlinkage void do_notify_resume(struct pt_regs *regs,
915	unsigned long thread_flags)	915	unsigned long thread_flags)
916	{	916	{
917	/*
918	* The assembly code enters us with IRQs off, but it hasn't
919	* informed the tracing code of that for efficiency reasons.
920	* Update the trace code with the current status.
921	*/
922	trace_hardirqs_off();
923
924	do {	917	do {
925	if (thread_flags & _TIF_NEED_RESCHED) {	918	if (thread_flags & _TIF_NEED_RESCHED) {
926	/* Unmask Debug and SError for the next task */	919	/* Unmask Debug and SError for the next task */

arch/arm64/kernel/smp.c+1−2

 			   "CPU: CPUs started in inconsistent modes");
 	else
 		pr_info("CPU: All CPU(s) started at EL1\n");
-	if (IS_ENABLED(CONFIG_KVM))
+	if (IS_ENABLED(CONFIG_KVM) && !is_kernel_in_hyp_mode())
 		kvm_compute_layout();
 }
 	unsigned int cpu, i;
 	for (i = 0; i < NR_IPI; i++) {
-		unsigned int irq = irq_desc_get_irq(ipi_desc[i]);
 		seq_printf(p, "%*s%u:%s", prec - 1, "IPI", i,
 			   prec >= 4 ? " " : "");
 		for_each_online_cpu(cpu)

arch/arm64/kernel/syscall.c+2−8

 #include <asm/daifflags.h>
 #include <asm/debug-monitors.h>
+#include <asm/exception.h>
 #include <asm/fpsimd.h>
 #include <asm/syscall.h>
 #include <asm/thread_info.h>
 	if (!has_syscall_work(flags) && !IS_ENABLED(CONFIG_DEBUG_RSEQ)) {
 		local_daif_mask();
 		flags = current_thread_info()->flags;
-		if (!has_syscall_work(flags) && !(flags & _TIF_SINGLESTEP)) {
+		if (!has_syscall_work(flags) && !(flags & _TIF_SINGLESTEP))
-			/*
-			 * We're off to userspace, where interrupts are
-			 * always enabled after we restore the flags from
-			 * the SPSR.
-			 */
-			trace_hardirqs_on();
 			return;
-		}
 		local_daif_restore(DAIF_PROCCTX);
 	}

arch/arm64/kernel/traps.c+0−1

@@ -42,7 +42,6 @@ · 41 unmodified lines
42	#include <asm/smp.h>	42	#include <asm/smp.h>
43	#include <asm/stack_pointer.h>	43	#include <asm/stack_pointer.h>
44	#include <asm/stacktrace.h>	44	#include <asm/stacktrace.h>
45	#include <asm/exception.h>
46	#include <asm/system_misc.h>	45	#include <asm/system_misc.h>
47	#include <asm/sysreg.h>	46	#include <asm/sysreg.h>
48		47

arch/arm64/kernel/vdso/Makefile+1−2

@@ -24,8 +24,7 @@ btildflags-$(CONFIG_ARM64_BTI_KERNEL) += -z force-bti · 23 unmodified lines
24	# routines, as x86 does (see 6f121e548f83 ("x86, vdso: Reimplement vdso.so	24	# routines, as x86 does (see 6f121e548f83 ("x86, vdso: Reimplement vdso.so
25	# preparation in build-time C")).	25	# preparation in build-time C")).
26	ldflags-y := -shared -nostdlib -soname=linux-vdso.so.1 --hash-style=sysv \	26	ldflags-y := -shared -nostdlib -soname=linux-vdso.so.1 --hash-style=sysv \
27	-Bsymbolic $(call ld-option, --no-eh-frame-hdr) --build-id=sha1 -n \	27	-Bsymbolic --build-id=sha1 -n $(btildflags-y) -T
28	$(btildflags-y) -T
29		28
30	ccflags-y := -fno-common -fno-builtin -fno-stack-protector -ffixed-x18	29	ccflags-y := -fno-common -fno-builtin -fno-stack-protector -ffixed-x18
31	ccflags-y += -DDISABLE_BRANCH_PROFILING -DBUILD_VDSO	30	ccflags-y += -DDISABLE_BRANCH_PROFILING -DBUILD_VDSO

arch/arm64/kernel/vdso/vdso.lds.S+1−4

 	PROVIDE (_etext = .);
 	PROVIDE (etext = .);
-	.eh_frame_hdr	: { *(.eh_frame_hdr) }		:text	:eh_frame_hdr
-	.eh_frame	: { KEEP (*(.eh_frame)) }	:text
 	.dynamic	: { *(.dynamic) }		:text	:dynamic
 	.rodata		: { *(.rodata*) }		:text
 		*(.note.GNU-stack)
 		*(.data .data.* .gnu.linkonce.d.* .sdata*)
 		*(.bss .sbss .dynbss .dynsbss)
+		*(.eh_frame .eh_frame_hdr)
 	}
 }
 	text		PT_LOAD		FLAGS(5) FILEHDR PHDRS; /* PF_R|PF_X */
 	dynamic		PT_DYNAMIC	FLAGS(4);		/* PF_R */
 	note		PT_NOTE		FLAGS(4);		/* PF_R */
-	eh_frame_hdr	PT_GNU_EH_FRAME;
 }
 /*

arch/arm64/kvm/Kconfig+0−8

@@ -49,14 +49,6 @@ if KVM · 48 unmodified lines
49		49
50	source "virt/kvm/Kconfig"	50	source "virt/kvm/Kconfig"
51		51
52	config KVM_ARM_PMU
53	bool "Virtual Performance Monitoring Unit (PMU) support"
54	depends on HW_PERF_EVENTS
55	default y
56	help
57	Adds support for a virtual Performance Monitoring Unit (PMU) in
58	virtual machines.
59
60	endif # KVM	52	endif # KVM
61		53
62	endif # VIRTUALIZATION	54	endif # VIRTUALIZATION

arch/arm64/kvm/Makefile+1−1

@@ -24,4 +24,4 @@ kvm-y := $(KVM)/kvm_main.o $(KVM)/coalesced_mmio.o $(KVM)/eventfd.o \ · 23 unmodified lines
24	vgic/vgic-mmio-v3.o vgic/vgic-kvm-device.o \	24	vgic/vgic-mmio-v3.o vgic/vgic-kvm-device.o \
25	vgic/vgic-its.o vgic/vgic-debug.o	25	vgic/vgic-its.o vgic/vgic-debug.o
26		26
27	kvm-$(CONFIG_KVM_ARM_PMU) += pmu-emul.o	27	kvm-$(CONFIG_HW_PERF_EVENTS) += pmu-emul.o

arch/arm64/kvm/arch_timer.c+4−3

@@ -1129,9 +1129,10 @@ int kvm_timer_enable(struct kvm_vcpu *vcpu) · 1128 unmodified lines
1129	if (!irqchip_in_kernel(vcpu->kvm))	1129	if (!irqchip_in_kernel(vcpu->kvm))
1130	goto no_vgic;	1130	goto no_vgic;
1131		1131
1132	if (!vgic_initialized(vcpu->kvm))	1132	/*
1133	return -ENODEV;	1133	* At this stage, we have the guarantee that the vgic is both
1134		1134	* available and initialized.
		1135	*/
1135	if (!timer_irqs_are_valid(vcpu)) {	1136	if (!timer_irqs_are_valid(vcpu)) {
1136	kvm_debug("incorrectly configured timer irqs\n");	1137	kvm_debug("incorrectly configured timer irqs\n");
1137	return -EINVAL;	1138	return -EINVAL;

arch/arm64/kvm/arm.c+18−14

@@ -65,10 +65,6 @@ static bool vgic_present; · 64 unmodified lines
65	static DEFINE_PER_CPU(unsigned char, kvm_arm_hardware_enabled);	65	static DEFINE_PER_CPU(unsigned char, kvm_arm_hardware_enabled);
66	DEFINE_STATIC_KEY_FALSE(userspace_irqchip_in_use);	66	DEFINE_STATIC_KEY_FALSE(userspace_irqchip_in_use);
67		67
68	extern u64 kvm_nvhe_sym(__cpu_logical_map)[NR_CPUS];
69	extern u32 kvm_nvhe_sym(kvm_host_psci_version);
70	extern struct psci_0_1_function_ids kvm_nvhe_sym(kvm_host_psci_0_1_function_ids);
71
72	int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)	68	int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
73	{	69	{
74	return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;	70	return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
@@ -584,11 +580,9 @@ static int kvm_vcpu_first_run_init(struct kvm_vcpu *vcpu) · 509 unmodified lines
584	* Map the VGIC hardware resources before running a vcpu the	580	* Map the VGIC hardware resources before running a vcpu the
585	* first time on this VM.	581	* first time on this VM.
586	*/	582	*/
587	if (unlikely(!vgic_ready(kvm))) {	583	ret = kvm_vgic_map_resources(kvm);
588	ret = kvm_vgic_map_resources(kvm);	584	if (ret)
589	if (ret)	585	return ret;
590	return ret;
591	}
592	} else {	586	} else {
593	/*	587	/*
594	* Tell the rest of the code that there are userspace irqchip	588	* Tell the rest of the code that there are userspace irqchip
@@ -1574,12 +1568,12 @@ static struct notifier_block hyp_init_cpu_pm_nb = { · 979 unmodified lines
1574	.notifier_call = hyp_init_cpu_pm_notifier,	1568	.notifier_call = hyp_init_cpu_pm_notifier,
1575	};	1569	};
1576		1570
1577	static void __init hyp_cpu_pm_init(void)	1571	static void hyp_cpu_pm_init(void)
1578	{	1572	{
1579	if (!is_protected_kvm_enabled())	1573	if (!is_protected_kvm_enabled())
1580	cpu_pm_register_notifier(&hyp_init_cpu_pm_nb);	1574	cpu_pm_register_notifier(&hyp_init_cpu_pm_nb);
1581	}	1575	}
1582	static void __init hyp_cpu_pm_exit(void)	1576	static void hyp_cpu_pm_exit(void)
1583	{	1577	{
1584	if (!is_protected_kvm_enabled())	1578	if (!is_protected_kvm_enabled())
1585	cpu_pm_unregister_notifier(&hyp_init_cpu_pm_nb);	1579	cpu_pm_unregister_notifier(&hyp_init_cpu_pm_nb);
@@ -1604,9 +1598,12 @@ static void init_cpu_logical_map(void) · 18 unmodified lines
1604	* allow any other CPUs from the `possible` set to boot.	1598	* allow any other CPUs from the `possible` set to boot.
1605	*/	1599	*/
1606	for_each_online_cpu(cpu)	1600	for_each_online_cpu(cpu)
1607	kvm_nvhe_sym(__cpu_logical_map)[cpu] = cpu_logical_map(cpu);	1601	hyp_cpu_logical_map[cpu] = cpu_logical_map(cpu);
1608	}	1602	}
1609		1603
		1604	#define init_psci_0_1_impl_state(config, what) \
		1605	config.psci_0_1_ ## what ## _implemented = psci_ops.what
		1606
1610	static bool init_psci_relay(void)	1607	static bool init_psci_relay(void)
1611	{	1608	{
1612	/*	1609	/*
@@ -1618,8 +1615,15 @@ static bool init_psci_relay(void) · 5 unmodified lines
1618	return false;	1615	return false;
1619	}	1616	}
1620		1617
1621	kvm_nvhe_sym(kvm_host_psci_version) = psci_ops.get_version();	1618	kvm_host_psci_config.version = psci_ops.get_version();
1622	kvm_nvhe_sym(kvm_host_psci_0_1_function_ids) = get_psci_0_1_function_ids();	1619
		1620	if (kvm_host_psci_config.version == PSCI_VERSION(0, 1)) {
		1621	kvm_host_psci_config.function_ids_0_1 = get_psci_0_1_function_ids();
		1622	init_psci_0_1_impl_state(kvm_host_psci_config, cpu_suspend);
		1623	init_psci_0_1_impl_state(kvm_host_psci_config, cpu_on);
		1624	init_psci_0_1_impl_state(kvm_host_psci_config, cpu_off);
		1625	init_psci_0_1_impl_state(kvm_host_psci_config, migrate);
		1626	}
1623	return true;	1627	return true;
1624	}	1628	}
1625		1629

arch/arm64/kvm/hyp/include/hyp/adjust_pc.h+9−0

@@ -59,4 +59,13 @@ static inline void __adjust_pc(struct kvm_vcpu *vcpu) · 58 unmodified lines
59	}	59	}
60	}	60	}
61		61
		62	/*
		63	* Skip an instruction while host sysregs are live.
		64	* Assumes host is always 64-bit.
		65	*/
		66	static inline void kvm_skip_host_instr(void)
		67	{
		68	write_sysreg_el2(read_sysreg_el2(SYS_ELR) + 4, SYS_ELR);
		69	}
		70
62	#endif	71	#endif

arch/arm64/kvm/hyp/nvhe/hyp-main.c+2−10

 	__kvm_hyp_host_forward_smc(host_ctxt);
 }
-static void skip_host_instruction(void)
-{
-	write_sysreg_el2(read_sysreg_el2(SYS_ELR) + 4, SYS_ELR);
-}
 static void handle_host_smc(struct kvm_cpu_context *host_ctxt)
 {
 	bool handled;
 	if (!handled)
 		default_host_smc_handler(host_ctxt);
-	/*
+	/* SMC was trapped, move ELR past the current PC. */
-	 * Unlike HVC, the return address of an SMC is the instruction's PC.
+	kvm_skip_host_instr();
-	 * Move the return address past the instruction.
-	 */
-	skip_host_instruction();
 }
 void handle_trap(struct kvm_cpu_context *host_ctxt)

arch/arm64/kvm/hyp/nvhe/hyp-smp.c+3−3

@@ -14,14 +14,14 @@ · 13 unmodified lines
14	* Other CPUs should not be allowed to boot because their features were	14	* Other CPUs should not be allowed to boot because their features were
15	* not checked against the finalized system capabilities.	15	* not checked against the finalized system capabilities.
16	*/	16	*/
17	u64 __ro_after_init __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID };	17	u64 __ro_after_init hyp_cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID };
18		18
19	u64 cpu_logical_map(unsigned int cpu)	19	u64 cpu_logical_map(unsigned int cpu)
20	{	20	{
21	if (cpu >= ARRAY_SIZE(__cpu_logical_map))	21	if (cpu >= ARRAY_SIZE(hyp_cpu_logical_map))
22	hyp_panic();	22	hyp_panic();
23		23
24	return __cpu_logical_map[cpu];	24	return hyp_cpu_logical_map[cpu];
25	}	25	}
26		26
27	unsigned long __hyp_per_cpu_offset(unsigned int cpu)	27	unsigned long __hyp_per_cpu_offset(unsigned int cpu)

arch/arm64/kvm/hyp/nvhe/psci-relay.c+22−37

@@ -7,11 +7,8 @@ · 6 unmodified lines
7	#include <asm/kvm_asm.h>	7	#include <asm/kvm_asm.h>
8	#include <asm/kvm_hyp.h>	8	#include <asm/kvm_hyp.h>
9	#include <asm/kvm_mmu.h>	9	#include <asm/kvm_mmu.h>
10	#include <kvm/arm_hypercalls.h>
11	#include <linux/arm-smccc.h>	10	#include <linux/arm-smccc.h>
12	#include <linux/kvm_host.h>	11	#include <linux/kvm_host.h>
13	#include <linux/psci.h>
14	#include <kvm/arm_psci.h>
15	#include <uapi/linux/psci.h>	12	#include <uapi/linux/psci.h>
16		13
17	#include <nvhe/trap_handler.h>	14	#include <nvhe/trap_handler.h>
@@ -22,9 +19,8 @@ void kvm_hyp_cpu_resume(unsigned long r0); · 4 unmodified lines
22	void __noreturn __host_enter(struct kvm_cpu_context *host_ctxt);	19	void __noreturn __host_enter(struct kvm_cpu_context *host_ctxt);
23		20
24	/* Config options set by the host. */	21	/* Config options set by the host. */
25	__ro_after_init u32 kvm_host_psci_version;	22	struct kvm_host_psci_config __ro_after_init kvm_host_psci_config;
26	__ro_after_init struct psci_0_1_function_ids kvm_host_psci_0_1_function_ids;	23	s64 __ro_after_init hyp_physvirt_offset;
27	__ro_after_init s64 hyp_physvirt_offset;
28		24
29	#define __hyp_pa(x) ((phys_addr_t)((x)) + hyp_physvirt_offset)	25	#define __hyp_pa(x) ((phys_addr_t)((x)) + hyp_physvirt_offset)
30		26
@@ -47,19 +43,16 @@ struct psci_boot_args { · 16 unmodified lines
47	static DEFINE_PER_CPU(struct psci_boot_args, cpu_on_args) = PSCI_BOOT_ARGS_INIT;	43	static DEFINE_PER_CPU(struct psci_boot_args, cpu_on_args) = PSCI_BOOT_ARGS_INIT;
48	static DEFINE_PER_CPU(struct psci_boot_args, suspend_args) = PSCI_BOOT_ARGS_INIT;	44	static DEFINE_PER_CPU(struct psci_boot_args, suspend_args) = PSCI_BOOT_ARGS_INIT;
49		45
50	static u64 get_psci_func_id(struct kvm_cpu_context *host_ctxt)	46	#define is_psci_0_1(what, func_id) \
51	{	47	(kvm_host_psci_config.psci_0_1_ ## what ## _implemented && \
52	DECLARE_REG(u64, func_id, host_ctxt, 0);	48	(func_id) == kvm_host_psci_config.function_ids_0_1.what)
53
54	return func_id;
55	}
56		49
57	static bool is_psci_0_1_call(u64 func_id)	50	static bool is_psci_0_1_call(u64 func_id)
58	{	51	{
59	return (func_id == kvm_host_psci_0_1_function_ids.cpu_suspend) \|\|	52	return (is_psci_0_1(cpu_suspend, func_id) \|\|
60	(func_id == kvm_host_psci_0_1_function_ids.cpu_on) \|\|	53	is_psci_0_1(cpu_on, func_id) \|\|
61	(func_id == kvm_host_psci_0_1_function_ids.cpu_off) \|\|	54	is_psci_0_1(cpu_off, func_id) \|\|
62	(func_id == kvm_host_psci_0_1_function_ids.migrate);	55	is_psci_0_1(migrate, func_id));
63	}	56	}
64		57
65	static bool is_psci_0_2_call(u64 func_id)	58	static bool is_psci_0_2_call(u64 func_id)
@@ -69,16 +62,6 @@ static bool is_psci_0_2_call(u64 func_id) · 3 unmodified lines
69	(PSCI_0_2_FN64(0) <= func_id && func_id <= PSCI_0_2_FN64(31));	62	(PSCI_0_2_FN64(0) <= func_id && func_id <= PSCI_0_2_FN64(31));
70	}	63	}
71		64
72	static bool is_psci_call(u64 func_id)
73	{
74	switch (kvm_host_psci_version) {
75	case PSCI_VERSION(0, 1):
76	return is_psci_0_1_call(func_id);
77	default:
78	return is_psci_0_2_call(func_id);
79	}
80	}
81
82	static unsigned long psci_call(unsigned long fn, unsigned long arg0,	65	static unsigned long psci_call(unsigned long fn, unsigned long arg0,
83	unsigned long arg1, unsigned long arg2)	66	unsigned long arg1, unsigned long arg2)
84	{	67	{
@@ -248,15 +231,14 @@ asmlinkage void __noreturn kvm_host_psci_cpu_entry(bool is_cpu_on) · 163 unmodified lines
248		231
249	static unsigned long psci_0_1_handler(u64 func_id, struct kvm_cpu_context *host_ctxt)	232	static unsigned long psci_0_1_handler(u64 func_id, struct kvm_cpu_context *host_ctxt)
250	{	233	{
251	if ((func_id == kvm_host_psci_0_1_function_ids.cpu_off) \|\|	234	if (is_psci_0_1(cpu_off, func_id) \|\| is_psci_0_1(migrate, func_id))
252	(func_id == kvm_host_psci_0_1_function_ids.migrate))
253	return psci_forward(host_ctxt);	235	return psci_forward(host_ctxt);
254	else if (func_id == kvm_host_psci_0_1_function_ids.cpu_on)	236	if (is_psci_0_1(cpu_on, func_id))
255	return psci_cpu_on(func_id, host_ctxt);	237	return psci_cpu_on(func_id, host_ctxt);
256	else if (func_id == kvm_host_psci_0_1_function_ids.cpu_suspend)	238	if (is_psci_0_1(cpu_suspend, func_id))
257	return psci_cpu_suspend(func_id, host_ctxt);	239	return psci_cpu_suspend(func_id, host_ctxt);
258	else	240
259	return PSCI_RET_NOT_SUPPORTED;	241	return PSCI_RET_NOT_SUPPORTED;
260	}	242	}
261		243
262	static unsigned long psci_0_2_handler(u64 func_id, struct kvm_cpu_context *host_ctxt)	244	static unsigned long psci_0_2_handler(u64 func_id, struct kvm_cpu_context *host_ctxt)
@@ -298,20 +280,23 @@ static unsigned long psci_1_0_handler(u64 func_id, struct kvm_cpu_context *host_ · 35 unmodified lines
298		280
299	bool kvm_host_psci_handler(struct kvm_cpu_context *host_ctxt)	281	bool kvm_host_psci_handler(struct kvm_cpu_context *host_ctxt)
300	{	282	{
301	u64 func_id = get_psci_func_id(host_ctxt);	283	DECLARE_REG(u64, func_id, host_ctxt, 0);
302	unsigned long ret;	284	unsigned long ret;
303		285
304	if (!is_psci_call(func_id))	286	switch (kvm_host_psci_config.version) {
305	return false;
306
307	switch (kvm_host_psci_version) {
308	case PSCI_VERSION(0, 1):	287	case PSCI_VERSION(0, 1):
		288	if (!is_psci_0_1_call(func_id))
		289	return false;
309	ret = psci_0_1_handler(func_id, host_ctxt);	290	ret = psci_0_1_handler(func_id, host_ctxt);
310	break;	291	break;
311	case PSCI_VERSION(0, 2):	292	case PSCI_VERSION(0, 2):
		293	if (!is_psci_0_2_call(func_id))
		294	return false;
312	ret = psci_0_2_handler(func_id, host_ctxt);	295	ret = psci_0_2_handler(func_id, host_ctxt);
313	break;	296	break;
314	default:	297	default:
		298	if (!is_psci_0_2_call(func_id))
		299	return false;
315	ret = psci_1_0_handler(func_id, host_ctxt);	300	ret = psci_1_0_handler(func_id, host_ctxt);
316	break;	301	break;
317	}	302	}

arch/arm64/kvm/pmu-emul.c+0−2

@@ -850,8 +850,6 @@ int kvm_arm_pmu_v3_enable(struct kvm_vcpu *vcpu) · 849 unmodified lines
850	return -EINVAL;	850	return -EINVAL;
851	}	851	}
852		852
853	kvm_pmu_vcpu_reset(vcpu);
854
855	return 0;	853	return 0;
856	}	854	}
857		855

arch/arm64/kvm/sys_regs.c+5−1

 {
 	u64 pmcr, val;
+	/* No PMU available, PMCR_EL0 may UNDEF... */
+	if (!kvm_arm_support_pmu_v3())
+		return;
 	pmcr = read_sysreg(pmcr_el0);
 	/*
 	 * Writable bits of PMCR_EL0 (ARMV8_PMU_PMCR_MASK) are reset to UNKNOWN
 #define reg_to_encoding(x)						\
 	sys_reg((u32)(x)->Op0, (u32)(x)->Op1,				\
-		(u32)(x)->CRn, (u32)(x)->CRm, (u32)(x)->Op2);
+		(u32)(x)->CRn, (u32)(x)->CRm, (u32)(x)->Op2)
 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
 #define DBG_BCR_BVR_WCR_WVR_EL1(n)					\

arch/arm64/kvm/va_layout.c+3−4

 }
 /*
- * Store a hyp VA <-> PA offset into a hyp-owned variable.
+ * Store a hyp VA <-> PA offset into a EL2-owned variable.
  */
 static void init_hyp_physvirt_offset(void)
 {
-	extern s64 kvm_nvhe_sym(hyp_physvirt_offset);
 	u64 kern_va, hyp_va;
 	/* Compute the offset from the hyp VA and PA of a random symbol. */
-	kern_va = (u64)kvm_ksym_ref(__hyp_text_start);
+	kern_va = (u64)lm_alias(__hyp_text_start);
 	hyp_va = __early_kern_hyp_va(kern_va);
-	CHOOSE_NVHE_SYM(hyp_physvirt_offset) = (s64)__pa(kern_va) - (s64)hyp_va;
+	hyp_physvirt_offset = (s64)__pa(kern_va) - (s64)hyp_va;
 }
 /*

arch/arm64/kvm/vgic/vgic-init.c+10−1

  * Map the MMIO regions depending on the VGIC model exposed to the guest
  * called on the first VCPU run.
  * Also map the virtual CPU interface into the VM.
- * v2/v3 derivatives call vgic_init if not already done.
+ * v2 calls vgic_init() if not already done.
+ * v3 and derivatives return an error if the VGIC is not initialized.
  * vgic_ready() returns true if this function has succeeded.
  * @kvm: kvm struct pointer
  */
 	struct vgic_dist *dist = &kvm->arch.vgic;
 	int ret = 0;
+	if (likely(vgic_ready(kvm)))
+		return 0;
 	mutex_lock(&kvm->lock);
+	if (vgic_ready(kvm))
+		goto out;
 	if (!irqchip_in_kernel(kvm))
 		goto out;
 	if (ret)
 		__kvm_vgic_destroy(kvm);
+	else
+		dist->ready = true;
 out:
 	mutex_unlock(&kvm->lock);

arch/arm64/kvm/vgic/vgic-v2.c+6−14

 	struct vgic_dist *dist = &kvm->arch.vgic;
 	int ret = 0;
-	if (vgic_ready(kvm))
-		goto out;
 	if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) ||
 	    IS_VGIC_ADDR_UNDEF(dist->vgic_cpu_base)) {
 		kvm_err("Need to set vgic cpu and dist addresses first\n");
-		ret = -ENXIO;
+		return -ENXIO;
-		goto out;
 	}
 	if (!vgic_v2_check_base(dist->vgic_dist_base, dist->vgic_cpu_base)) {
 		kvm_err("VGIC CPU and dist frames overlap\n");
-		ret = -EINVAL;
+		return -EINVAL;
-		goto out;
 	}
 	/*
 	ret = vgic_init(kvm);
 	if (ret) {
 		kvm_err("Unable to initialize VGIC dynamic data structures\n");
-		goto out;
+		return ret;
 	}
 	ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V2);
 	if (ret) {
 		kvm_err("Unable to register VGIC MMIO regions\n");
-		goto out;
+		return ret;
 	}
 	if (!static_branch_unlikely(&vgic_v2_cpuif_trap)) {
 					    KVM_VGIC_V2_CPU_SIZE, true);
 		if (ret) {
 			kvm_err("Unable to remap VGIC CPU to VCPU\n");
-			goto out;
+			return ret;
 		}
 	}
-	dist->ready = true;
+	return 0;
-out:
-	return ret;
 }
 DEFINE_STATIC_KEY_FALSE(vgic_v2_cpuif_trap);

arch/arm64/kvm/vgic/vgic-v3.c+6−15

 	int ret = 0;
 	int c;
-	if (vgic_ready(kvm))
-		goto out;
 	kvm_for_each_vcpu(c, vcpu, kvm) {
 		struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
 		if (IS_VGIC_ADDR_UNDEF(vgic_cpu->rd_iodev.base_addr)) {
 			kvm_debug("vcpu %d redistributor base not set\n", c);
-			ret = -ENXIO;
+			return -ENXIO;
-			goto out;
 		}
 	}
 	if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base)) {
 		kvm_err("Need to set vgic distributor addresses first\n");
-		ret = -ENXIO;
+		return -ENXIO;
-		goto out;
 	}
 	if (!vgic_v3_check_base(kvm)) {
 		kvm_err("VGIC redist and dist frames overlap\n");
-		ret = -EINVAL;
+		return -EINVAL;
-		goto out;
 	}
 	/*
 	 * the VGIC before we need to use it.
 	 */
 	if (!vgic_initialized(kvm)) {
-		ret = -EBUSY;
+		return -EBUSY;
-		goto out;
 	}
 	ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V3);
 	if (ret) {
 		kvm_err("Unable to register VGICv3 dist MMIO regions\n");
-		goto out;
+		return ret;
 	}
 	if (kvm_vgic_global_state.has_gicv4_1)
 		vgic_v4_configure_vsgis(kvm);
-	dist->ready = true;
-out:
+	return 0;
-	return ret;
 }
 DEFINE_STATIC_KEY_FALSE(vgic_v3_cpuif_trap);

arch/arm64/mm/init.c+18−15

 EXPORT_SYMBOL(memstart_addr);
 /*
- * We create both ZONE_DMA and ZONE_DMA32. ZONE_DMA covers the first 1G of
+ * If the corresponding config options are enabled, we create both ZONE_DMA
- * memory as some devices, namely the Raspberry Pi 4, have peripherals with
+ * and ZONE_DMA32. By default ZONE_DMA covers the 32-bit addressable memory
- * this limited view of the memory. ZONE_DMA32 will cover the rest of the 32
+ * unless restricted on specific platforms (e.g. 30-bit on Raspberry Pi 4).
- * bit addressable memory area.
+ * In such case, ZONE_DMA32 covers the rest of the 32-bit addressable memory,
+ * otherwise it is empty.
  */
 phys_addr_t arm64_dma_phys_limit __ro_after_init;
-static phys_addr_t arm64_dma32_phys_limit __ro_after_init;
 #ifdef CONFIG_KEXEC_CORE
 /*
 	if (crash_base == 0) {
 		/* Current arm64 boot protocol requires 2MB alignment */
-		crash_base = memblock_find_in_range(0, arm64_dma32_phys_limit,
+		crash_base = memblock_find_in_range(0, arm64_dma_phys_limit,
 				crash_size, SZ_2M);
 		if (crash_base == 0) {
 			pr_warn("cannot allocate crashkernel (size:0x%llx)\n",
 	unsigned long max_zone_pfns[MAX_NR_ZONES]  = {0};
 	unsigned int __maybe_unused acpi_zone_dma_bits;
 	unsigned int __maybe_unused dt_zone_dma_bits;
+	phys_addr_t __maybe_unused dma32_phys_limit = max_zone_phys(32);
 #ifdef CONFIG_ZONE_DMA
 	acpi_zone_dma_bits = fls64(acpi_iort_dma_get_max_cpu_address());
 	max_zone_pfns[ZONE_DMA] = PFN_DOWN(arm64_dma_phys_limit);
 #endif
 #ifdef CONFIG_ZONE_DMA32
-	max_zone_pfns[ZONE_DMA32] = PFN_DOWN(arm64_dma32_phys_limit);
+	max_zone_pfns[ZONE_DMA32] = PFN_DOWN(dma32_phys_limit);
+	if (!arm64_dma_phys_limit)
+		arm64_dma_phys_limit = dma32_phys_limit;
 #endif
+	if (!arm64_dma_phys_limit)
+		arm64_dma_phys_limit = PHYS_MASK + 1;
 	max_zone_pfns[ZONE_NORMAL] = max;
 	free_area_init(max_zone_pfns);
 	early_init_fdt_scan_reserved_mem();
-	if (IS_ENABLED(CONFIG_ZONE_DMA32))
-		arm64_dma32_phys_limit = max_zone_phys(32);
-	else
-		arm64_dma32_phys_limit = PHYS_MASK + 1;
 	reserve_elfcorehdr();
 	high_memory = __va(memblock_end_of_DRAM() - 1) + 1;
-	dma_contiguous_reserve(arm64_dma32_phys_limit);
 }
 void __init bootmem_init(void)
 	sparse_init();
 	zone_sizes_init(min, max);
+	/*
+	 * Reserve the CMA area after arm64_dma_phys_limit was initialised.
+	 */
+	dma_contiguous_reserve(arm64_dma_phys_limit);
 	/*
 	 * request_standard_resources() depends on crashkernel's memory being
 	 * reserved, so do it here.
 void __init mem_init(void)
 {
 	if (swiotlb_force == SWIOTLB_FORCE ||
-	    max_pfn > PFN_DOWN(arm64_dma_phys_limit ? : arm64_dma32_phys_limit))
+	    max_pfn > PFN_DOWN(arm64_dma_phys_limit))
 		swiotlb_init(1);
 	else
 		swiotlb_force = SWIOTLB_NO_FORCE;

arch/arm64/mm/proc.S+1−1

@@ -46,7 +46,7 @@ · 45 unmodified lines
46	#endif	46	#endif
47		47
48	#ifdef CONFIG_KASAN_HW_TAGS	48	#ifdef CONFIG_KASAN_HW_TAGS
49	#define TCR_KASAN_HW_FLAGS SYS_TCR_EL1_TCMA1 \| TCR_TBI1	49	#define TCR_KASAN_HW_FLAGS SYS_TCR_EL1_TCMA1 \| TCR_TBI1 \| TCR_TBID1
50	#else	50	#else
51	#define TCR_KASAN_HW_FLAGS 0	51	#define TCR_KASAN_HW_FLAGS 0
52	#endif	52	#endif

arch/csky/include/asm/Kbuild+0−1

@@ -2,7 +2,6 @@ · 1 unmodified line
2	generic-y += asm-offsets.h	2	generic-y += asm-offsets.h
3	generic-y += gpio.h	3	generic-y += gpio.h
4	generic-y += kvm_para.h	4	generic-y += kvm_para.h
5	generic-y += local64.h
6	generic-y += qrwlock.h	5	generic-y += qrwlock.h
7	generic-y += user.h	6	generic-y += user.h
8	generic-y += vmlinux.lds.h	7	generic-y += vmlinux.lds.h

arch/h8300/include/asm/Kbuild+0−1

@@ -2,7 +2,6 @@ · 1 unmodified line
2	generic-y += asm-offsets.h	2	generic-y += asm-offsets.h
3	generic-y += extable.h	3	generic-y += extable.h
4	generic-y += kvm_para.h	4	generic-y += kvm_para.h
5	generic-y += local64.h
6	generic-y += mcs_spinlock.h	5	generic-y += mcs_spinlock.h
7	generic-y += parport.h	6	generic-y += parport.h
8	generic-y += spinlock.h	7	generic-y += spinlock.h

arch/hexagon/include/asm/Kbuild+0−1

@@ -2,5 +2,4 @@ · 1 unmodified line
2	generic-y += extable.h	2	generic-y += extable.h
3	generic-y += iomap.h	3	generic-y += iomap.h
4	generic-y += kvm_para.h	4	generic-y += kvm_para.h
5	generic-y += local64.h
6	generic-y += mcs_spinlock.h	5	generic-y += mcs_spinlock.h

arch/ia64/include/asm/local64.h+0−1

@@ -1 +0,0 @@
1	#include <asm-generic/local64.h>

arch/ia64/include/asm/sparsemem.h+1−0

@@ -3,6 +3,7 @@ · 2 unmodified lines
3	#define _ASM_IA64_SPARSEMEM_H	3	#define _ASM_IA64_SPARSEMEM_H
4		4
5	#ifdef CONFIG_SPARSEMEM	5	#ifdef CONFIG_SPARSEMEM
		6	#include <asm/page.h>
6	/*	7	/*
7	* SECTION_SIZE_BITS 2^N: how big each section will be	8	* SECTION_SIZE_BITS 2^N: how big each section will be
8	* MAX_PHYSMEM_BITS 2^N: how much memory we can have in that space	9	* MAX_PHYSMEM_BITS 2^N: how much memory we can have in that space

arch/ia64/mm/init.c+2−2

@@ -536,7 +536,7 @@ virtual_memmap_init(u64 start, u64 end, void *arg) · 535 unmodified lines
536		536
537	if (map_start < map_end)	537	if (map_start < map_end)
538	memmap_init_zone((unsigned long)(map_end - map_start),	538	memmap_init_zone((unsigned long)(map_end - map_start),
539	args->nid, args->zone, page_to_pfn(map_start),	539	args->nid, args->zone, page_to_pfn(map_start), page_to_pfn(map_end),
540	MEMINIT_EARLY, NULL, MIGRATE_MOVABLE);	540	MEMINIT_EARLY, NULL, MIGRATE_MOVABLE);
541	return 0;	541	return 0;
542	}	542	}
@@ -546,7 +546,7 @@ memmap_init (unsigned long size, int nid, unsigned long zone, · 3 unmodified lines
546	unsigned long start_pfn)	546	unsigned long start_pfn)
547	{	547	{
548	if (!vmem_map) {	548	if (!vmem_map) {
549	memmap_init_zone(size, nid, zone, start_pfn,	549	memmap_init_zone(size, nid, zone, start_pfn, start_pfn + size,
550	MEMINIT_EARLY, NULL, MIGRATE_MOVABLE);	550	MEMINIT_EARLY, NULL, MIGRATE_MOVABLE);
551	} else {	551	} else {
552	struct page *start;	552	struct page *start;

arch/m68k/include/asm/Kbuild+0−1

@@ -2,6 +2,5 @@ · 1 unmodified line
2	generated-y += syscall_table.h	2	generated-y += syscall_table.h
3	generic-y += extable.h	3	generic-y += extable.h
4	generic-y += kvm_para.h	4	generic-y += kvm_para.h
5	generic-y += local64.h
6	generic-y += mcs_spinlock.h	5	generic-y += mcs_spinlock.h
7	generic-y += spinlock.h	6	generic-y += spinlock.h

arch/microblaze/include/asm/Kbuild+0−1

@@ -2,7 +2,6 @@ · 1 unmodified line
2	generated-y += syscall_table.h	2	generated-y += syscall_table.h
3	generic-y += extable.h	3	generic-y += extable.h
4	generic-y += kvm_para.h	4	generic-y += kvm_para.h
5	generic-y += local64.h
6	generic-y += mcs_spinlock.h	5	generic-y += mcs_spinlock.h
7	generic-y += parport.h	6	generic-y += parport.h
8	generic-y += syscalls.h	7	generic-y += syscalls.h

arch/mips/boot/compressed/decompress.c+2−1

 #include <linux/libfdt.h>
 #include <asm/addrspace.h>
+#include <asm/unaligned.h>
 /*
  * These two variables specify the free mem region
 		dtb_size = fdt_totalsize((void *)&__appended_dtb);
 		/* last four bytes is always image size in little endian */
-		image_size = le32_to_cpup((void *)&__image_end - 4);
+		image_size = get_unaligned_le32((void *)&__image_end - 4);
 		/* copy dtb to where the booted kernel will expect it */
 		memcpy((void *)VMLINUX_LOAD_ADDRESS_ULL + image_size,

arch/mips/cavium-octeon/octeon-irq.c+1−1

@@ -1444,7 +1444,7 @@ static void octeon_irq_setup_secondary_ciu2(void) · 1443 unmodified lines
1444	static int __init octeon_irq_init_ciu(	1444	static int __init octeon_irq_init_ciu(
1445	struct device_node ciu_node, struct device_node parent)	1445	struct device_node ciu_node, struct device_node parent)
1446	{	1446	{
1447	unsigned int i, r;	1447	int i, r;
1448	struct irq_chip *chip;	1448	struct irq_chip *chip;
1449	struct irq_chip *chip_edge;	1449	struct irq_chip *chip_edge;
1450	struct irq_chip *chip_mbox;	1450	struct irq_chip *chip_mbox;

arch/mips/include/asm/Kbuild+0−1

@@ -6,7 +6,6 @@ generated-y += syscall_table_64_n64.h · 5 unmodified lines
6	generated-y += syscall_table_64_o32.h	6	generated-y += syscall_table_64_o32.h
7	generic-y += export.h	7	generic-y += export.h
8	generic-y += kvm_para.h	8	generic-y += kvm_para.h
9	generic-y += local64.h
10	generic-y += mcs_spinlock.h	9	generic-y += mcs_spinlock.h
11	generic-y += parport.h	10	generic-y += parport.h
12	generic-y += qrwlock.h	11	generic-y += qrwlock.h

arch/mips/kernel/binfmt_elfn32.c+7−0

@@ -103,4 +103,11 @@ jiffies_to_old_timeval32(unsigned long jiffies, struct old_timeval32 *value) · 102 unmodified lines
103	#undef ns_to_kernel_old_timeval	103	#undef ns_to_kernel_old_timeval
104	#define ns_to_kernel_old_timeval ns_to_old_timeval32	104	#define ns_to_kernel_old_timeval ns_to_old_timeval32
105		105
		106	/*
		107	* Some data types as stored in coredump.
		108	*/
		109	#define user_long_t compat_long_t
		110	#define user_siginfo_t compat_siginfo_t
		111	#define copy_siginfo_to_external copy_siginfo_to_external32
		112
106	#include "../../../fs/binfmt_elf.c"	113	#include "../../../fs/binfmt_elf.c"

arch/mips/kernel/binfmt_elfo32.c+7−0

@@ -106,4 +106,11 @@ jiffies_to_old_timeval32(unsigned long jiffies, struct old_timeval32 *value) · 105 unmodified lines
106	#undef ns_to_kernel_old_timeval	106	#undef ns_to_kernel_old_timeval
107	#define ns_to_kernel_old_timeval ns_to_old_timeval32	107	#define ns_to_kernel_old_timeval ns_to_old_timeval32
108		108
		109	/*
		110	* Some data types as stored in coredump.
		111	*/
		112	#define user_long_t compat_long_t
		113	#define user_siginfo_t compat_siginfo_t
		114	#define copy_siginfo_to_external copy_siginfo_to_external32
		115
109	#include "../../../fs/binfmt_elf.c"	116	#include "../../../fs/binfmt_elf.c"

arch/mips/kernel/relocate.c+8−2

 static inline __init unsigned long rotate_xor(unsigned long hash,
 					      const void *area, size_t size)
 {
-	size_t i;
+	const typeof(hash) *ptr = PTR_ALIGN(area, sizeof(hash));
-	unsigned long *ptr = (unsigned long *)area;
+	size_t diff, i;
+	diff = (void *)ptr - area;
+	if (unlikely(size < diff + sizeof(hash)))
+		return hash;
+	size = ALIGN_DOWN(size - diff, sizeof(hash));
 	for (i = 0; i < size / sizeof(hash); i++) {
 		/* Rotate by odd number of bits and XOR. */

arch/nds32/include/asm/Kbuild+0−1

@@ -4,6 +4,5 @@ generic-y += cmpxchg.h · 3 unmodified lines
4	generic-y += export.h	4	generic-y += export.h
5	generic-y += gpio.h	5	generic-y += gpio.h
6	generic-y += kvm_para.h	6	generic-y += kvm_para.h
7	generic-y += local64.h
8	generic-y += parport.h	7	generic-y += parport.h
9	generic-y += user.h	8	generic-y += user.h

arch/openrisc/include/asm/Kbuild+0−1

@@ -1,7 +1,6 @@
1	# SPDX-License-Identifier: GPL-2.0	1	# SPDX-License-Identifier: GPL-2.0
2	generic-y += extable.h	2	generic-y += extable.h
3	generic-y += kvm_para.h	3	generic-y += kvm_para.h
4	generic-y += local64.h
5	generic-y += mcs_spinlock.h	4	generic-y += mcs_spinlock.h
6	generic-y += qspinlock_types.h	5	generic-y += qspinlock_types.h
7	generic-y += qspinlock.h	6	generic-y += qspinlock.h

arch/parisc/include/asm/Kbuild+0−1

@@ -3,6 +3,5 @@ generated-y += syscall_table_32.h · 2 unmodified lines
3	generated-y += syscall_table_64.h	3	generated-y += syscall_table_64.h
4	generated-y += syscall_table_c32.h	4	generated-y += syscall_table_c32.h
5	generic-y += kvm_para.h	5	generic-y += kvm_para.h
6	generic-y += local64.h
7	generic-y += mcs_spinlock.h	6	generic-y += mcs_spinlock.h
8	generic-y += user.h	7	generic-y += user.h

arch/powerpc/include/asm/Kbuild+0−1

@@ -5,7 +5,6 @@ generated-y += syscall_table_c32.h · 4 unmodified lines
5	generated-y += syscall_table_spu.h	5	generated-y += syscall_table_spu.h
6	generic-y += export.h	6	generic-y += export.h
7	generic-y += kvm_types.h	7	generic-y += kvm_types.h
8	generic-y += local64.h
9	generic-y += mcs_spinlock.h	8	generic-y += mcs_spinlock.h
10	generic-y += qrwlock.h	9	generic-y += qrwlock.h
11	generic-y += vtime.h	10	generic-y += vtime.h

arch/powerpc/include/asm/vdso/gettimeofday.h+15−1

 	return do_syscall_2(__NR_gettimeofday, (unsigned long)_tv, (unsigned long)_tz);
 }
+#ifdef __powerpc64__
 static __always_inline
 int clock_gettime_fallback(clockid_t _clkid, struct __kernel_timespec *_ts)
 {
 	return do_syscall_2(__NR_clock_getres, _clkid, (unsigned long)_ts);
 }
-#ifdef CONFIG_VDSO32
+#else
 #define BUILD_VDSO32		1
+static __always_inline
+int clock_gettime_fallback(clockid_t _clkid, struct __kernel_timespec *_ts)
+{
+	return do_syscall_2(__NR_clock_gettime64, _clkid, (unsigned long)_ts);
+}
+static __always_inline
+int clock_getres_fallback(clockid_t _clkid, struct __kernel_timespec *_ts)
+{
+	return do_syscall_2(__NR_clock_getres_time64, _clkid, (unsigned long)_ts);
+}
 static __always_inline
 int clock_gettime32_fallback(clockid_t _clkid, struct old_timespec32 *_ts)
 {

arch/powerpc/kernel/head_book3s_32.S+9−0

 MachineCheck:
 	EXCEPTION_PROLOG_0
 #ifdef CONFIG_PPC_CHRP
+#ifdef CONFIG_VMAP_STACK
+	mtspr	SPRN_SPRG_SCRATCH2,r1
+	mfspr	r1, SPRN_SPRG_THREAD
+	lwz	r1, RTAS_SP(r1)
+	cmpwi	cr1, r1, 0
+	bne	cr1, 7f
+	mfspr	r1, SPRN_SPRG_SCRATCH2
+#else
 	mfspr	r11, SPRN_SPRG_THREAD
 	lwz	r11, RTAS_SP(r11)
 	cmpwi	cr1, r11, 0
 	bne	cr1, 7f
+#endif
 #endif /* CONFIG_PPC_CHRP */
 	EXCEPTION_PROLOG_1 for_rtas=1
 7:	EXCEPTION_PROLOG_2

arch/powerpc/kernel/vmlinux.lds.S+9−1

 		ALIGN_FUNCTION();
 #endif
 		/* careful! __ftr_alt_* sections need to be close to .text */
-		*(.text.hot TEXT_MAIN .text.fixup .text.unlikely .fixup __ftr_alt_* .ref.text);
+		*(.text.hot .text.hot.* TEXT_MAIN .text.fixup .text.unlikely .text.unlikely.* .fixup __ftr_alt_* .ref.text);
 #ifdef CONFIG_PPC64
 		*(.tramp.ftrace.text);
 #endif
 	.init.text : AT(ADDR(.init.text) - LOAD_OFFSET) {
 		_sinittext = .;
 		INIT_TEXT
+		/*
+		 *.init.text might be RO so we must ensure this section ends on
+		 * a page boundary.
+		 */
+		. = ALIGN(PAGE_SIZE);
 		_einittext = .;
 #ifdef CONFIG_PPC64
 		*(.tramp.ftrace.init);
 		EXIT_TEXT
 	}
+	. = ALIGN(PAGE_SIZE);
 	INIT_DATA_SECTION(16)
 	. = ALIGN(8);

arch/riscv/Kconfig+4−2

 config PAGE_OFFSET
 	hex
-	default 0xC0000000 if 32BIT && MAXPHYSMEM_2GB
+	default 0xC0000000 if 32BIT && MAXPHYSMEM_1GB
 	default 0x80000000 if 64BIT && !MMU
 	default 0xffffffff80000000 if 64BIT && MAXPHYSMEM_2GB
 	default 0xffffffe000000000 if 64BIT && MAXPHYSMEM_128GB
 choice
 	prompt "Maximum Physical Memory"
-	default MAXPHYSMEM_2GB if 32BIT
+	default MAXPHYSMEM_1GB if 32BIT
 	default MAXPHYSMEM_2GB if 64BIT && CMODEL_MEDLOW
 	default MAXPHYSMEM_128GB if 64BIT && CMODEL_MEDANY
+	config MAXPHYSMEM_1GB
+		bool "1GiB"
 	config MAXPHYSMEM_2GB
 		bool "2GiB"
 	config MAXPHYSMEM_128GB

arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts+2−0

 	phy-mode = "gmii";
 	phy-handle = <&phy0>;
 	phy0: ethernet-phy@0 {
+		compatible = "ethernet-phy-id0007.0771";
 		reg = <0>;
+		reset-gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
 	};
 };

arch/riscv/configs/defconfig+2−0

 CONFIG_HW_RANDOM_VIRTIO=y
 CONFIG_SPI=y
 CONFIG_SPI_SIFIVE=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SIFIVE=y
 # CONFIG_PTP_1588_CLOCK is not set
 CONFIG_POWER_RESET=y
 CONFIG_DRM=y

arch/riscv/include/asm/Kbuild+0−1

@@ -3,6 +3,5 @@ generic-y += early_ioremap.h · 2 unmodified lines
3	generic-y += extable.h	3	generic-y += extable.h
4	generic-y += flat.h	4	generic-y += flat.h
5	generic-y += kvm_para.h	5	generic-y += kvm_para.h
6	generic-y += local64.h
7	generic-y += user.h	6	generic-y += user.h
8	generic-y += vmlinux.lds.h	7	generic-y += vmlinux.lds.h

arch/riscv/include/asm/pgtable.h+0−1

@@ -99,7 +99,6 @@ · 98 unmodified lines
99	\| _PAGE_DIRTY)	99	\| _PAGE_DIRTY)
100		100
101	#define PAGE_KERNEL __pgprot(_PAGE_KERNEL)	101	#define PAGE_KERNEL __pgprot(_PAGE_KERNEL)
102	#define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL \| _PAGE_EXEC)
103	#define PAGE_KERNEL_READ __pgprot(_PAGE_KERNEL & ~_PAGE_WRITE)	102	#define PAGE_KERNEL_READ __pgprot(_PAGE_KERNEL & ~_PAGE_WRITE)
104	#define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL \| _PAGE_EXEC)	103	#define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL \| _PAGE_EXEC)
105	#define PAGE_KERNEL_READ_EXEC __pgprot((_PAGE_KERNEL & ~_PAGE_WRITE) \	104	#define PAGE_KERNEL_READ_EXEC __pgprot((_PAGE_KERNEL & ~_PAGE_WRITE) \

arch/riscv/include/asm/vdso.h+1−1

@@ -10,7 +10,7 @@ · 9 unmodified lines
10		10
11	#include <linux/types.h>	11	#include <linux/types.h>
12		12
13	#ifndef GENERIC_TIME_VSYSCALL	13	#ifndef CONFIG_GENERIC_TIME_VSYSCALL
14	struct vdso_data {	14	struct vdso_data {
15	};	15	};
16	#endif	16	#endif

arch/riscv/kernel/cacheinfo.c+10−1

@@ -26,7 +26,16 @@ cache_get_priv_group(struct cacheinfo *this_leaf) · 25 unmodified lines
26		26
27	static struct cacheinfo *get_cacheinfo(u32 level, enum cache_type type)	27	static struct cacheinfo *get_cacheinfo(u32 level, enum cache_type type)
28	{	28	{
29	struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(smp_processor_id());	29	/*
		30	* Using raw_smp_processor_id() elides a preemptability check, but this
		31	* is really indicative of a larger problem: the cacheinfo UABI assumes
		32	* that cores have a homonogenous view of the cache hierarchy. That
		33	* happens to be the case for the current set of RISC-V systems, but
		34	* likely won't be true in general. Since there's no way to provide
		35	* correct information for these systems via the current UABI we're
		36	* just eliding the check for now.
		37	*/
		38	struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(raw_smp_processor_id());
30	struct cacheinfo *this_leaf;	39	struct cacheinfo *this_leaf;
31	int index;	40	int index;
32		41

arch/riscv/kernel/entry.S+13−11

 	REG_L a1, (a1)
 	jr a1
 1:
-#ifdef CONFIG_TRACE_IRQFLAGS
-	call trace_hardirqs_on
-#endif
 	/*
 	 * Exceptions run with interrupts enabled or disabled depending on the
 	 * state of SR_PIE in m/sstatus.
 	 */
 	andi t0, s1, SR_PIE
 	beqz t0, 1f
+#ifdef CONFIG_TRACE_IRQFLAGS
+	call trace_hardirqs_on
+#endif
 	csrs CSR_STATUS, SR_IE
 1:
 	tail do_trap_unknown
 handle_syscall:
+#ifdef CONFIG_RISCV_M_MODE
+	/*
+	 * When running is M-Mode (no MMU config), MPIE does not get set.
+	 * As a result, we need to force enable interrupts here because
+	 * handle_exception did not do set SR_IE as it always sees SR_PIE
+	 * being cleared.
+	 */
+	csrs CSR_STATUS, SR_IE
+#endif
 #if defined(CONFIG_TRACE_IRQFLAGS) || defined(CONFIG_CONTEXT_TRACKING)
 	/* Recover a0 - a7 for system calls */
 	REG_L a0, PT_A0(sp)
 	 * Syscall number held in a7.
 	 * If syscall number is above allowed value, redirect to ni_syscall.
 	 */
-	bge a7, t0, 1f
+	bgeu a7, t0, 1f
-	/*
-	 * Check if syscall is rejected by tracer, i.e., a7 == -1.
-	 * If yes, we pretend it was executed.
-	 */
-	li t1, -1
-	beq a7, t1, ret_from_syscall_rejected
-	blt a7, t1, 1f
 	/* Call syscall */
 	la s0, sys_call_table
 	slli t0, a7, RISCV_LGPTR

arch/riscv/kernel/setup.c+13−11

 {
 	struct memblock_region *region = NULL;
 	struct resource *res = NULL;
-	int ret = 0;
+	struct resource *mem_res = NULL;
+	size_t mem_res_sz = 0;
+	int ret = 0, i = 0;
 	code_res.start = __pa_symbol(_text);
 	code_res.end = __pa_symbol(_etext) - 1;
 	bss_res.end = __pa_symbol(__bss_stop) - 1;
 	bss_res.flags = IORESOURCE_SYSTEM_RAM | IORESOURCE_BUSY;
+	mem_res_sz = (memblock.memory.cnt + memblock.reserved.cnt) * sizeof(*mem_res);
+	mem_res = memblock_alloc(mem_res_sz, SMP_CACHE_BYTES);
+	if (!mem_res)
+		panic("%s: Failed to allocate %zu bytes\n", __func__, mem_res_sz);
 	/*
 	 * Start by adding the reserved regions, if they overlap
 	 * with /memory regions, insert_resource later on will take
 	 * care of it.
 	 */
 	for_each_reserved_mem_region(region) {
-		res = memblock_alloc(sizeof(struct resource), SMP_CACHE_BYTES);
+		res = &mem_res[i++];
-		if (!res)
-			panic("%s: Failed to allocate %zu bytes\n", __func__,
-			      sizeof(struct resource));
 		res->name = "Reserved";
 		res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
 		 * Ignore any other reserved regions within
 		 * system memory.
 		 */
-		if (memblock_is_memory(res->start))
+		if (memblock_is_memory(res->start)) {
+			memblock_free((phys_addr_t) res, sizeof(struct resource));
 			continue;
+		}
 		ret = add_resource(&iomem_resource, res);
 		if (ret < 0)
 	/* Add /memory regions to the resource tree */
 	for_each_mem_region(region) {
-		res = memblock_alloc(sizeof(struct resource), SMP_CACHE_BYTES);
+		res = &mem_res[i++];
-		if (!res)
-			panic("%s: Failed to allocate %zu bytes\n", __func__,
-			      sizeof(struct resource));
 		if (unlikely(memblock_is_nomap(region))) {
 			res->name = "Reserved";
 	return;
  error:
-	memblock_free((phys_addr_t) res, sizeof(struct resource));
 	/* Better an empty resource tree than an inconsistent one */
 	release_child_resources(&iomem_resource);
+	memblock_free((phys_addr_t) mem_res, mem_res_sz);
 }

arch/riscv/kernel/stacktrace.c+2−3

 #include <asm/stacktrace.h>
-register unsigned long sp_in_global __asm__("sp");
+register const unsigned long sp_in_global __asm__("sp");
 #ifdef CONFIG_FRAME_POINTER
 		sp = user_stack_pointer(regs);
 		pc = instruction_pointer(regs);
 	} else if (task == NULL || task == current) {
-		const register unsigned long current_sp = sp_in_global;
 		fp = (unsigned long)__builtin_frame_address(0);
-		sp = current_sp;
+		sp = sp_in_global;
 		pc = (unsigned long)walk_stackframe;
 	} else {
 		/* task blocked in __switch_to */

arch/riscv/kernel/time.c+3−0

  * Copyright (C) 2017 SiFive
  */
+#include <linux/of_clk.h>
 #include <linux/clocksource.h>
 #include <linux/delay.h>
 #include <asm/sbi.h>
 	riscv_timebase = prop;
 	lpj_fine = riscv_timebase / HZ;
+	of_clk_init(NULL);
 	timer_probe();
 }

arch/riscv/kernel/vdso.c+1−1

@@ -12,7 +12,7 @@ · 11 unmodified lines
12	#include <linux/binfmts.h>	12	#include <linux/binfmts.h>
13	#include <linux/err.h>	13	#include <linux/err.h>
14	#include <asm/page.h>	14	#include <asm/page.h>
15	#ifdef GENERIC_TIME_VSYSCALL	15	#ifdef CONFIG_GENERIC_TIME_VSYSCALL
16	#include <vdso/datapage.h>	16	#include <vdso/datapage.h>
17	#else	17	#else
18	#include <asm/vdso.h>	18	#include <asm/vdso.h>

arch/riscv/mm/init.c+14−2

 void __init setup_bootmem(void)
 {
 	phys_addr_t mem_start = 0;
-	phys_addr_t start, end = 0;
+	phys_addr_t start, dram_end, end = 0;
 	phys_addr_t vmlinux_end = __pa_symbol(&_end);
 	phys_addr_t vmlinux_start = __pa_symbol(&_start);
+	phys_addr_t max_mapped_addr = __pa(~(ulong)0);
 	u64 i;
 	/* Find the memory region containing the kernel */
 	/* Reserve from the start of the kernel to the end of the kernel */
 	memblock_reserve(vmlinux_start, vmlinux_end - vmlinux_start);
-	max_pfn = PFN_DOWN(memblock_end_of_DRAM());
+	dram_end = memblock_end_of_DRAM();
+	/*
+	 * memblock allocator is not aware of the fact that last 4K bytes of
+	 * the addressable memory can not be mapped because of IS_ERR_VALUE
+	 * macro. Make sure that last 4k bytes are not usable by memblock
+	 * if end of dram is equal to maximum addressable memory.
+	 */
+	if (max_mapped_addr == (dram_end - 1))
+		memblock_set_current_limit(max_mapped_addr - 4096);
+	max_pfn = PFN_DOWN(dram_end);
 	max_low_pfn = max_pfn;
 	dma32_phys_limit = min(4UL * SZ_1G, (unsigned long)PFN_PHYS(max_low_pfn));
 	set_max_mapnr(max_low_pfn);

arch/riscv/mm/kasan_init.c+2−2

@@ -93,8 +93,8 @@ void __init kasan_init(void) · 92 unmodified lines
93	VMALLOC_END));	93	VMALLOC_END));
94		94
95	for_each_mem_range(i, &_start, &_end) {	95	for_each_mem_range(i, &_start, &_end) {
96	void start = (void )_start;	96	void start = (void )__va(_start);
97	void end = (void )_end;	97	void end = (void )__va(_end);
98		98
99	if (start >= end)	99	if (start >= end)
100	break;	100	break;

arch/s390/Kconfig+17−14

 config S390
 	def_bool y
+	#
+	# Note: keep this list sorted alphabetically
+	#
+	imply IMA_SECURE_AND_OR_TRUSTED_BOOT
 	select ARCH_BINFMT_ELF_STATE
 	select ARCH_HAS_DEBUG_VM_PGTABLE
 	select ARCH_HAS_DEBUG_WX
 	select ARCH_HAS_DEVMEM_IS_ALLOWED
 	select ARCH_HAS_ELF_RANDOMIZE
+	select ARCH_HAS_FORCE_DMA_UNENCRYPTED
 	select ARCH_HAS_FORTIFY_SOURCE
 	select ARCH_HAS_GCOV_PROFILE_ALL
 	select ARCH_HAS_GIGANTIC_PAGE
 	select ARCH_HAS_KCOV
 	select ARCH_HAS_MEM_ENCRYPT
 	select ARCH_HAS_PTE_SPECIAL
+	select ARCH_HAS_SCALED_CPUTIME
 	select ARCH_HAS_SET_MEMORY
 	select ARCH_HAS_STRICT_KERNEL_RWX
 	select ARCH_HAS_STRICT_MODULE_RWX
 	select ARCH_WANT_IPC_PARSE_VERSION
 	select BUILDTIME_TABLE_SORT
 	select CLONE_BACKWARDS2
+	select CPU_NO_EFFICIENT_FFS if !HAVE_MARCH_Z9_109_FEATURES
 	select DMA_OPS if PCI
 	select DYNAMIC_FTRACE if FUNCTION_TRACER
+	select GENERIC_ALLOCATOR
 	select GENERIC_CPU_AUTOPROBE
 	select GENERIC_CPU_VULNERABILITIES
 	select GENERIC_FIND_FIRST_BIT
 	select HAVE_ARCH_JUMP_LABEL_RELATIVE
 	select HAVE_ARCH_KASAN
 	select HAVE_ARCH_KASAN_VMALLOC
-	select CPU_NO_EFFICIENT_FFS if !HAVE_MARCH_Z9_109_FEATURES
 	select HAVE_ARCH_SECCOMP_FILTER
 	select HAVE_ARCH_SOFT_DIRTY
 	select HAVE_ARCH_TRACEHOOK
 	select HAVE_ARCH_TRANSPARENT_HUGEPAGE
 	select HAVE_ARCH_VMAP_STACK
 	select HAVE_ASM_MODVERSIONS
-	select HAVE_EBPF_JIT if PACK_STACK && HAVE_MARCH_Z196_FEATURES
 	select HAVE_CMPXCHG_DOUBLE
 	select HAVE_CMPXCHG_LOCAL
 	select HAVE_DEBUG_KMEMLEAK
 	select HAVE_DMA_CONTIGUOUS
 	select HAVE_DYNAMIC_FTRACE
 	select HAVE_DYNAMIC_FTRACE_WITH_REGS
-	select HAVE_FAST_GUP
+	select HAVE_EBPF_JIT if PACK_STACK && HAVE_MARCH_Z196_FEATURES
 	select HAVE_EFFICIENT_UNALIGNED_ACCESS
+	select HAVE_FAST_GUP
 	select HAVE_FENTRY
 	select HAVE_FTRACE_MCOUNT_RECORD
 	select HAVE_FUNCTION_ERROR_INJECTION
 	select HAVE_KRETPROBES
 	select HAVE_KVM
 	select HAVE_LIVEPATCH
-	select HAVE_PERF_REGS
-	select HAVE_PERF_USER_STACK_DUMP
 	select HAVE_MEMBLOCK_PHYS_MAP
-	select MMU_GATHER_NO_GATHER
 	select HAVE_MOD_ARCH_SPECIFIC
+	select HAVE_NMI
 	select HAVE_NOP_MCOUNT
 	select HAVE_OPROFILE
 	select HAVE_PCI
 	select HAVE_PERF_EVENTS
-	select MMU_GATHER_RCU_TABLE_FREE
+	select HAVE_PERF_REGS
+	select HAVE_PERF_USER_STACK_DUMP
 	select HAVE_REGS_AND_STACK_ACCESS_API
 	select HAVE_RELIABLE_STACKTRACE
 	select HAVE_RSEQ
 	select HAVE_VIRT_CPU_ACCOUNTING_IDLE
 	select IOMMU_HELPER		if PCI
 	select IOMMU_SUPPORT		if PCI
+	select MMU_GATHER_NO_GATHER
+	select MMU_GATHER_RCU_TABLE_FREE
 	select MODULES_USE_ELF_RELA
 	select NEED_DMA_MAP_STATE	if PCI
 	select NEED_SG_DMA_LENGTH	if PCI
 	select PCI_MSI			if PCI
 	select PCI_MSI_ARCH_FALLBACKS	if PCI_MSI
 	select SPARSE_IRQ
+	select SWIOTLB
 	select SYSCTL_EXCEPTION_TRACE
 	select THREAD_INFO_IN_TASK
 	select TTY
 	select VIRT_CPU_ACCOUNTING
-	select ARCH_HAS_SCALED_CPUTIME
+	# Note: keep the above list sorted alphabetically
-	select HAVE_NMI
-	select ARCH_HAS_FORCE_DMA_UNENCRYPTED
-	select SWIOTLB
-	select GENERIC_ALLOCATOR
-	imply IMA_SECURE_AND_OR_TRUSTED_BOOT
 config SCHED_OMIT_FRAME_POINTER
 	def_bool y

arch/s390/configs/debug_defconfig+9−3

 CONFIG_KPROBES=y
 CONFIG_JUMP_LABEL=y
 CONFIG_STATIC_KEYS_SELFTEST=y
+CONFIG_SECCOMP_CACHE_DEBUG=y
 CONFIG_LOCK_EVENT_COUNTS=y
+# CONFIG_GCC_PLUGINS is not set
 CONFIG_MODULES=y
 CONFIG_MODULE_FORCE_LOAD=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_SCSI_CONSTANTS=y
 CONFIG_SCSI_LOGGING=y
 CONFIG_SCSI_SPI_ATTRS=m
-CONFIG_SCSI_FC_ATTRS=y
+CONFIG_SCSI_FC_ATTRS=m
 CONFIG_SCSI_SAS_LIBSAS=m
 CONFIG_SCSI_SRP_ATTRS=m
 CONFIG_ISCSI_TCP=m
 CONFIG_SCSI_DEBUG=m
-CONFIG_ZFCP=y
+CONFIG_ZFCP=m
 CONFIG_SCSI_VIRTIO=m
 CONFIG_SCSI_DH=y
 CONFIG_SCSI_DH_RDAC=m
 CONFIG_DM_MULTIPATH_QL=m
 CONFIG_DM_MULTIPATH_ST=m
 CONFIG_DM_MULTIPATH_HST=m
+CONFIG_DM_MULTIPATH_IOA=m
 CONFIG_DM_DELAY=m
 CONFIG_DM_UEVENT=y
 CONFIG_DM_FLAKEY=m
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_SERIO is not set
 CONFIG_LEGACY_PTY_COUNT=0
-CONFIG_NULL_TTY=m
 CONFIG_VIRTIO_CONSOLE=y
 CONFIG_HW_RANDOM_VIRTIO=m
 CONFIG_RAW_DRIVER=m
 CONFIG_VIRTIO_INPUT=y
 CONFIG_VHOST_NET=m
 CONFIG_VHOST_VSOCK=m
+# CONFIG_SURFACE_PLATFORMS is not set
 CONFIG_S390_CCW_IOMMU=y
 CONFIG_S390_AP_IOMMU=y
 CONFIG_EXT4_FS=y
 CONFIG_CIFS_POSIX=y
 # CONFIG_CIFS_DEBUG is not set
 CONFIG_CIFS_DFS_UPCALL=y
+CONFIG_CIFS_SWN_UPCALL=y
 CONFIG_NLS_DEFAULT="utf8"
 CONFIG_NLS_CODEPAGE_437=m
 CONFIG_NLS_CODEPAGE_850=m
 CONFIG_BLK_DEV_IO_TRACE=y
 CONFIG_BPF_KPROBE_OVERRIDE=y
 CONFIG_HIST_TRIGGERS=y
+CONFIG_FTRACE_STARTUP_TEST=y
+# CONFIG_EVENT_TRACE_STARTUP_TEST is not set
 CONFIG_DEBUG_USER_ASCE=y
 CONFIG_NOTIFIER_ERROR_INJECTION=m
 CONFIG_NETDEV_NOTIFIER_ERROR_INJECT=m

arch/s390/configs/defconfig+7−4

 CONFIG_OPROFILE=m
 CONFIG_KPROBES=y
 CONFIG_JUMP_LABEL=y
+# CONFIG_GCC_PLUGINS is not set
 CONFIG_MODULES=y
 CONFIG_MODULE_FORCE_LOAD=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_DEFERRED_STRUCT_PAGE_INIT=y
 CONFIG_IDLE_PAGE_TRACKING=y
 CONFIG_PERCPU_STATS=y
-CONFIG_GUP_TEST=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_PACKET_DIAG=m
 CONFIG_SCSI_CONSTANTS=y
 CONFIG_SCSI_LOGGING=y
 CONFIG_SCSI_SPI_ATTRS=m
-CONFIG_SCSI_FC_ATTRS=y
+CONFIG_SCSI_FC_ATTRS=m
 CONFIG_SCSI_SAS_LIBSAS=m
 CONFIG_SCSI_SRP_ATTRS=m
 CONFIG_ISCSI_TCP=m
 CONFIG_SCSI_DEBUG=m
-CONFIG_ZFCP=y
+CONFIG_ZFCP=m
 CONFIG_SCSI_VIRTIO=m
 CONFIG_SCSI_DH=y
 CONFIG_SCSI_DH_RDAC=m
 CONFIG_DM_MULTIPATH_QL=m
 CONFIG_DM_MULTIPATH_ST=m
 CONFIG_DM_MULTIPATH_HST=m
+CONFIG_DM_MULTIPATH_IOA=m
 CONFIG_DM_DELAY=m
 CONFIG_DM_UEVENT=y
 CONFIG_DM_FLAKEY=m
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_SERIO is not set
 CONFIG_LEGACY_PTY_COUNT=0
-CONFIG_NULL_TTY=m
 CONFIG_VIRTIO_CONSOLE=y
 CONFIG_HW_RANDOM_VIRTIO=m
 CONFIG_RAW_DRIVER=m
 CONFIG_VIRTIO_INPUT=y
 CONFIG_VHOST_NET=m
 CONFIG_VHOST_VSOCK=m
+# CONFIG_SURFACE_PLATFORMS is not set
 CONFIG_S390_CCW_IOMMU=y
 CONFIG_S390_AP_IOMMU=y
 CONFIG_EXT4_FS=y
 CONFIG_CIFS_POSIX=y
 # CONFIG_CIFS_DEBUG is not set
 CONFIG_CIFS_DFS_UPCALL=y
+CONFIG_CIFS_SWN_UPCALL=y
 CONFIG_NLS_DEFAULT="utf8"
 CONFIG_NLS_CODEPAGE_437=m
 CONFIG_NLS_CODEPAGE_850=m
 CONFIG_BLK_DEV_IO_TRACE=y
 CONFIG_BPF_KPROBE_OVERRIDE=y
 CONFIG_HIST_TRIGGERS=y
+CONFIG_DEBUG_USER_ASCE=y
 CONFIG_LKDTM=m
 CONFIG_PERCPU_TEST=m
 CONFIG_ATOMIC64_SELFTEST=y

arch/s390/configs/zfcpdump_defconfig+2−0

 # CONFIG_VIRTUALIZATION is not set
 # CONFIG_S390_GUEST is not set
 # CONFIG_SECCOMP is not set
+# CONFIG_GCC_PLUGINS is not set
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_IBM_PARTITION=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 # CONFIG_HID is not set
 # CONFIG_VIRTIO_MENU is not set
 # CONFIG_VHOST_MENU is not set
+# CONFIG_SURFACE_PLATFORMS is not set
 # CONFIG_IOMMU_SUPPORT is not set
 # CONFIG_DNOTIFY is not set
 # CONFIG_INOTIFY_USER is not set

arch/s390/include/asm/Kbuild+0−1

@@ -7,5 +7,4 @@ generated-y += unistd_nr.h · 6 unmodified lines
7	generic-y += asm-offsets.h	7	generic-y += asm-offsets.h
8	generic-y += export.h	8	generic-y += export.h
9	generic-y += kvm_types.h	9	generic-y += kvm_types.h
10	generic-y += local64.h
11	generic-y += mcs_spinlock.h	10	generic-y += mcs_spinlock.h

arch/sh/include/asm/Kbuild+0−1

@@ -1,6 +1,5 @@
1	# SPDX-License-Identifier: GPL-2.0	1	# SPDX-License-Identifier: GPL-2.0
2	generated-y += syscall_table.h	2	generated-y += syscall_table.h
3	generic-y += kvm_para.h	3	generic-y += kvm_para.h
4	generic-y += local64.h
5	generic-y += mcs_spinlock.h	4	generic-y += mcs_spinlock.h
6	generic-y += parport.h	5	generic-y += parport.h

arch/sparc/include/asm/Kbuild+0−1

@@ -6,5 +6,4 @@ generated-y += syscall_table_64.h · 5 unmodified lines
6	generated-y += syscall_table_c32.h	6	generated-y += syscall_table_c32.h
7	generic-y += export.h	7	generic-y += export.h
8	generic-y += kvm_para.h	8	generic-y += kvm_para.h
9	generic-y += local64.h
10	generic-y += mcs_spinlock.h	9	generic-y += mcs_spinlock.h

arch/x86/Kconfig+1−0

@@ -19,6 +19,7 @@ config X86_32 · 18 unmodified lines
19	select KMAP_LOCAL	19	select KMAP_LOCAL
20	select MODULES_USE_ELF_REL	20	select MODULES_USE_ELF_REL
21	select OLD_SIGACTION	21	select OLD_SIGACTION
		22	select ARCH_SPLIT_ARG64
22		23
23	config X86_64	24	config X86_64
24	def_bool y	25	def_bool y

arch/x86/hyperv/hv_init.c+30−3

 #include <asm/hyperv-tlfs.h>
 #include <asm/mshyperv.h>
 #include <asm/idtentry.h>
+#include <linux/kexec.h>
 #include <linux/version.h>
 #include <linux/vmalloc.h>
 #include <linux/mm.h>
 #include <linux/syscore_ops.h>
 #include <clocksource/hyperv_timer.h>
+int hyperv_init_cpuhp;
 void *hv_hypercall_pg;
 EXPORT_SYMBOL_GPL(hv_hypercall_pg);
 	.resume		= hv_resume,
 };
+static void (* __initdata old_setup_percpu_clockev)(void);
+static void __init hv_stimer_setup_percpu_clockev(void)
+{
+	/*
+	 * Ignore any errors in setting up stimer clockevents
+	 * as we can run with the LAPIC timer as a fallback.
+	 */
+	(void)hv_stimer_alloc();
+	/*
+	 * Still register the LAPIC timer, because the direct-mode STIMER is
+	 * not supported by old versions of Hyper-V. This also allows users
+	 * to switch to LAPIC timer via /sys, if they want to.
+	 */
+	if (old_setup_percpu_clockev)
+		old_setup_percpu_clockev();
+}
 /*
  * This function is to be invoked early in the boot sequence after the
  * hypervisor has been detected.
 	wrmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64);
 	/*
-	 * Ignore any errors in setting up stimer clockevents
+	 * hyperv_init() is called before LAPIC is initialized: see
-	 * as we can run with the LAPIC timer as a fallback.
+	 * apic_intr_mode_init() -> x86_platform.apic_post_init() and
+	 * apic_bsp_setup() -> setup_local_APIC(). The direct-mode STIMER
+	 * depends on LAPIC, so hv_stimer_alloc() should be called from
+	 * x86_init.timers.setup_percpu_clockev.
 	 */
-	(void)hv_stimer_alloc();
+	old_setup_percpu_clockev = x86_init.timers.setup_percpu_clockev;
+	x86_init.timers.setup_percpu_clockev = hv_stimer_setup_percpu_clockev;
 	hv_apic_init();
 	register_syscore_ops(&hv_syscore_ops);
+	hyperv_init_cpuhp = cpuhp;
 	return;
 remove_cpuhp_state:

arch/x86/hyperv/mmu.c+9−3

 	if (!hv_hypercall_pg)
 		goto do_native;
-	if (cpumask_empty(cpus))
-		return;
 	local_irq_save(flags);
+	/*
+	 * Only check the mask _after_ interrupt has been disabled to avoid the
+	 * mask changing under our feet.
+	 */
+	if (cpumask_empty(cpus)) {
+		local_irq_restore(flags);
+		return;
+	}
 	flush_pcpu = (struct hv_tlb_flush **)
 		     this_cpu_ptr(hyperv_pcpu_input_arg);

arch/x86/include/asm/kvm_host.h+17−2

@@ -1010,9 +1010,21 @@ struct kvm_arch { · 1009 unmodified lines
1010	*/	1010	*/
1011	bool tdp_mmu_enabled;	1011	bool tdp_mmu_enabled;
1012		1012
1013	/* List of struct tdp_mmu_pages being used as roots */	1013	/*
		1014	* List of struct kvmp_mmu_pages being used as roots.
		1015	* All struct kvm_mmu_pages in the list should have
		1016	* tdp_mmu_page set.
		1017	* All struct kvm_mmu_pages in the list should have a positive
		1018	* root_count except when a thread holds the MMU lock and is removing
		1019	* an entry from the list.
		1020	*/
1014	struct list_head tdp_mmu_roots;	1021	struct list_head tdp_mmu_roots;
1015	/* List of struct tdp_mmu_pages not being used as roots */	1022
		1023	/*
		1024	* List of struct kvmp_mmu_pages not being used as roots.
		1025	* All struct kvm_mmu_pages in the list should have
		1026	* tdp_mmu_page set and a root_count of 0.
		1027	*/
1016	struct list_head tdp_mmu_pages;	1028	struct list_head tdp_mmu_pages;
1017	};	1029	};
1018		1030
@@ -1287,6 +1299,8 @@ struct kvm_x86_ops { · 268 unmodified lines
1287	void (migrate_timers)(struct kvm_vcpu vcpu);	1299	void (migrate_timers)(struct kvm_vcpu vcpu);
1288	void (msr_filter_changed)(struct kvm_vcpu vcpu);	1300	void (msr_filter_changed)(struct kvm_vcpu vcpu);
1289	int (complete_emulated_msr)(struct kvm_vcpu vcpu, int err);	1301	int (complete_emulated_msr)(struct kvm_vcpu vcpu, int err);
		1302
		1303	void (vcpu_deliver_sipi_vector)(struct kvm_vcpu vcpu, u8 vector);
1290	};	1304	};
1291		1305
1292	struct kvm_x86_nested_ops {	1306	struct kvm_x86_nested_ops {
@@ -1468,6 +1482,7 @@ int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in); · 175 unmodified lines
1468	int kvm_emulate_cpuid(struct kvm_vcpu *vcpu);	1482	int kvm_emulate_cpuid(struct kvm_vcpu *vcpu);
1469	int kvm_emulate_halt(struct kvm_vcpu *vcpu);	1483	int kvm_emulate_halt(struct kvm_vcpu *vcpu);
1470	int kvm_vcpu_halt(struct kvm_vcpu *vcpu);	1484	int kvm_vcpu_halt(struct kvm_vcpu *vcpu);
		1485	int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu);
1471	int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu);	1486	int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu);
1472		1487
1473	void kvm_get_segment(struct kvm_vcpu vcpu, struct kvm_segment var, int seg);	1488	void kvm_get_segment(struct kvm_vcpu vcpu, struct kvm_segment var, int seg);

arch/x86/include/asm/local64.h+0−1

@@ -1 +0,0 @@
1	#include <asm-generic/local64.h>

arch/x86/include/asm/mshyperv.h+2−0

@@ -74,6 +74,8 @@ static inline void hv_disable_stimer0_percpu_irq(int irq) {} · 73 unmodified lines
74		74
75		75
76	#if IS_ENABLED(CONFIG_HYPERV)	76	#if IS_ENABLED(CONFIG_HYPERV)
		77	extern int hyperv_init_cpuhp;
		78
77	extern void *hv_hypercall_pg;	79	extern void *hv_hypercall_pg;
78	extern void __percpu **hyperv_pcpu_input_arg;	80	extern void __percpu **hyperv_pcpu_input_arg;
79		81

arch/x86/kernel/cpu/mshyperv.c+18−0

@@ -135,14 +135,32 @@ static void hv_machine_shutdown(void) · 134 unmodified lines
135	{	135	{
136	if (kexec_in_progress && hv_kexec_handler)	136	if (kexec_in_progress && hv_kexec_handler)
137	hv_kexec_handler();	137	hv_kexec_handler();
		138
		139	/*
		140	* Call hv_cpu_die() on all the CPUs, otherwise later the hypervisor
		141	* corrupts the old VP Assist Pages and can crash the kexec kernel.
		142	*/
		143	if (kexec_in_progress && hyperv_init_cpuhp > 0)
		144	cpuhp_remove_state(hyperv_init_cpuhp);
		145
		146	/* The function calls stop_other_cpus(). */
138	native_machine_shutdown();	147	native_machine_shutdown();
		148
		149	/* Disable the hypercall page when there is only 1 active CPU. */
		150	if (kexec_in_progress)
		151	hyperv_cleanup();
139	}	152	}
140		153
141	static void hv_machine_crash_shutdown(struct pt_regs *regs)	154	static void hv_machine_crash_shutdown(struct pt_regs *regs)
142	{	155	{
143	if (hv_crash_handler)	156	if (hv_crash_handler)
144	hv_crash_handler(regs);	157	hv_crash_handler(regs);
		158
		159	/* The function calls crash_smp_send_stop(). */
145	native_machine_crash_shutdown(regs);	160	native_machine_crash_shutdown(regs);
		161
		162	/* Disable the hypercall page when there is only 1 active CPU. */
		163	hyperv_cleanup();
146	}	164	}
147	#endif /* CONFIG_KEXEC_CORE */	165	#endif /* CONFIG_KEXEC_CORE */
148	#endif /* CONFIG_HYPERV */	166	#endif /* CONFIG_HYPERV */

arch/x86/kernel/cpu/mtrr/generic.c+3−3

 	*repeat = 0;
 	*uniform = 1;
-	/* Make end inclusive instead of exclusive */
-	end--;
 	prev_match = MTRR_TYPE_INVALID;
 	for (i = 0; i < num_var_ranges; ++i) {
 		unsigned short start_state, end_state, inclusive;
 	int repeat;
 	u64 partial_end;
+	/* Make end inclusive instead of exclusive */
+	end--;
 	if (!mtrr_state_set)
 		return MTRR_TYPE_INVALID;

arch/x86/kernel/cpu/resctrl/rdtgroup.c+49−68

@@ -525,89 +525,70 @@ static void rdtgroup_remove(struct rdtgroup *rdtgrp) · 524 unmodified lines
525	kfree(rdtgrp);	525	kfree(rdtgrp);
526	}	526	}
527		527
528	struct task_move_callback {	528	static void _update_task_closid_rmid(void *task)
529	struct callback_head work;
530	struct rdtgroup *rdtgrp;
531	};
532
533	static void move_myself(struct callback_head *head)
534	{	529	{
535	struct task_move_callback *callback;
536	struct rdtgroup *rdtgrp;
537
538	callback = container_of(head, struct task_move_callback, work);
539	rdtgrp = callback->rdtgrp;
540
541	/*	530	/*
542	* If resource group was deleted before this task work callback	531	* If the task is still current on this CPU, update PQR_ASSOC MSR.
543	* was invoked, then assign the task to root group and free the	532	* Otherwise, the MSR is updated when the task is scheduled in.
544	* resource group.
545	*/	533	*/
546	if (atomic_dec_and_test(&rdtgrp->waitcount) &&	534	if (task == current)
547	(rdtgrp->flags & RDT_DELETED)) {	535	resctrl_sched_in();
548	current->closid = 0;	536	}
549	current->rmid = 0;
550	rdtgroup_remove(rdtgrp);
551	}
552
553	if (unlikely(current->flags & PF_EXITING))
554	goto out;
555
556	preempt_disable();
557	/* update PQR_ASSOC MSR to make resource group go into effect */
558	resctrl_sched_in();
559	preempt_enable();
560		537
561	out:	538	static void update_task_closid_rmid(struct task_struct *t)
562	kfree(callback);	539	{
		540	if (IS_ENABLED(CONFIG_SMP) && task_curr(t))
		541	smp_call_function_single(task_cpu(t), _update_task_closid_rmid, t, 1);
		542	else
		543	_update_task_closid_rmid(t);
563	}	544	}
564		545
565	static int __rdtgroup_move_task(struct task_struct *tsk,	546	static int __rdtgroup_move_task(struct task_struct *tsk,
566	struct rdtgroup *rdtgrp)	547	struct rdtgroup *rdtgrp)
567	{	548	{
568	struct task_move_callback *callback;	549	/* If the task is already in rdtgrp, no need to move the task. */
569	int ret;	550	if ((rdtgrp->type == RDTCTRL_GROUP && tsk->closid == rdtgrp->closid &&
570		551	tsk->rmid == rdtgrp->mon.rmid) \|\|
571	callback = kzalloc(sizeof(*callback), GFP_KERNEL);	552	(rdtgrp->type == RDTMON_GROUP && tsk->rmid == rdtgrp->mon.rmid &&
572	if (!callback)	553	tsk->closid == rdtgrp->mon.parent->closid))
573	return -ENOMEM;	554	return 0;
574	callback->work.func = move_myself;
575	callback->rdtgrp = rdtgrp;
576		555
577	/*	556	/*
578	* Take a refcount, so rdtgrp cannot be freed before the	557	* Set the task's closid/rmid before the PQR_ASSOC MSR can be
579	* callback has been invoked.	558	* updated by them.
		559	*
		560	* For ctrl_mon groups, move both closid and rmid.
		561	* For monitor groups, can move the tasks only from
		562	* their parent CTRL group.
580	*/	563	*/
581	atomic_inc(&rdtgrp->waitcount);	564
582	ret = task_work_add(tsk, &callback->work, TWA_RESUME);	565	if (rdtgrp->type == RDTCTRL_GROUP) {
583	if (ret) {	566	tsk->closid = rdtgrp->closid;
584	/*	567	tsk->rmid = rdtgrp->mon.rmid;
585	* Task is exiting. Drop the refcount and free the callback.	568	} else if (rdtgrp->type == RDTMON_GROUP) {
586	* No need to check the refcount as the group cannot be	569	if (rdtgrp->mon.parent->closid == tsk->closid) {
587	* deleted before the write function unlocks rdtgroup_mutex.
588	*/
589	atomic_dec(&rdtgrp->waitcount);
590	kfree(callback);
591	rdt_last_cmd_puts("Task exited\n");
592	} else {
593	/*
594	* For ctrl_mon groups move both closid and rmid.
595	* For monitor groups, can move the tasks only from
596	* their parent CTRL group.
597	*/
598	if (rdtgrp->type == RDTCTRL_GROUP) {
599	tsk->closid = rdtgrp->closid;
600	tsk->rmid = rdtgrp->mon.rmid;	570	tsk->rmid = rdtgrp->mon.rmid;
601	} else if (rdtgrp->type == RDTMON_GROUP) {	571	} else {
602	if (rdtgrp->mon.parent->closid == tsk->closid) {	572	rdt_last_cmd_puts("Can't move task to different control group\n");
603	tsk->rmid = rdtgrp->mon.rmid;	573	return -EINVAL;
604	} else {
605	rdt_last_cmd_puts("Can't move task to different control group\n");
606	ret = -EINVAL;
607	}
608	}	574	}
609	}	575	}
610	return ret;	576
		577	/*
		578	* Ensure the task's closid and rmid are written before determining if
		579	* the task is current that will decide if it will be interrupted.
		580	*/
		581	barrier();
		582
		583	/*
		584	* By now, the task's closid and rmid are set. If the task is current
		585	* on a CPU, the PQR_ASSOC MSR needs to be updated to make the resource
		586	* group go into effect. If the task is not current, the MSR will be
		587	* updated when the task is scheduled in.
		588	*/
		589	update_task_closid_rmid(tsk);
		590
		591	return 0;
611	}	592	}
612		593
613	static bool is_closid_match(struct task_struct t, struct rdtgroup r)	594	static bool is_closid_match(struct task_struct t, struct rdtgroup r)

arch/x86/kernel/sev-es-shared.c+2−2

@@ -305,14 +305,14 @@ static enum es_result vc_ioio_exitinfo(struct es_em_ctxt ctxt, u64 exitinfo) · 304 unmodified lines
305	case 0xe4:	305	case 0xe4:
306	case 0xe5:	306	case 0xe5:
307	*exitinfo \|= IOIO_TYPE_IN;	307	*exitinfo \|= IOIO_TYPE_IN;
308	*exitinfo \|= (u64)insn->immediate.value << 16;	308	*exitinfo \|= (u8)insn->immediate.value << 16;
309	break;	309	break;
310		310
311	/* OUT immediate opcodes */	311	/* OUT immediate opcodes */
312	case 0xe6:	312	case 0xe6:
313	case 0xe7:	313	case 0xe7:
314	*exitinfo \|= IOIO_TYPE_OUT;	314	*exitinfo \|= IOIO_TYPE_OUT;
315	*exitinfo \|= (u64)insn->immediate.value << 16;	315	*exitinfo \|= (u8)insn->immediate.value << 16;
316	break;	316	break;
317		317
318	/* IN register opcodes */	318	/* IN register opcodes */

arch/x86/kvm/lapic.c+2−2

@@ -674,7 +674,7 @@ static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu) · 673 unmodified lines
674	(unsigned long long)vcpu->arch.pv_eoi.msr_val);	674	(unsigned long long)vcpu->arch.pv_eoi.msr_val);
675	return false;	675	return false;
676	}	676	}
677	return val & 0x1;	677	return val & KVM_PV_EOI_ENABLED;
678	}	678	}
679		679
680	static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)	680	static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
@@ -2898,7 +2898,7 @@ void kvm_apic_accept_events(struct kvm_vcpu *vcpu) · 2217 unmodified lines
2898	/* evaluate pending_events before reading the vector */	2898	/* evaluate pending_events before reading the vector */
2899	smp_rmb();	2899	smp_rmb();
2900	sipi_vector = apic->sipi_vector;	2900	sipi_vector = apic->sipi_vector;
2901	kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);	2901	kvm_x86_ops.vcpu_deliver_sipi_vector(vcpu, sipi_vector);
2902	vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;	2902	vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2903	}	2903	}
2904	}	2904	}

arch/x86/kvm/mmu.h+1−1

@@ -49,7 +49,7 @@ static inline u64 rsvd_bits(int s, int e) · 48 unmodified lines
49	if (e < s)	49	if (e < s)
50	return 0;	50	return 0;
51		51
52	return ((1ULL << (e - s + 1)) - 1) << s;	52	return ((2ULL << (e - s)) - 1) << s;
53	}	53	}
54		54
55	void kvm_mmu_set_mmio_spte_mask(u64 mmio_value, u64 access_mask);	55	void kvm_mmu_set_mmio_spte_mask(u64 mmio_value, u64 access_mask);

arch/x86/kvm/mmu/mmu.c+30−23

  * Return the level of the lowest level SPTE added to sptes.
  * That SPTE may be non-present.
  */
-static int get_walk(struct kvm_vcpu *vcpu, u64 addr, u64 *sptes)
+static int get_walk(struct kvm_vcpu *vcpu, u64 addr, u64 *sptes, int *root_level)
 {
 	struct kvm_shadow_walk_iterator iterator;
-	int leaf = vcpu->arch.mmu->root_level;
+	int leaf = -1;
 	u64 spte;
 	walk_shadow_page_lockless_begin(vcpu);
-	for (shadow_walk_init(&iterator, vcpu, addr);
+	for (shadow_walk_init(&iterator, vcpu, addr),
+	     *root_level = iterator.level;
 	     shadow_walk_okay(&iterator);
 	     __shadow_walk_next(&iterator, spte)) {
 		leaf = iterator.level;
 		spte = mmu_spte_get_lockless(iterator.sptep);
-		sptes[leaf - 1] = spte;
+		sptes[leaf] = spte;
 		if (!is_shadow_present_pte(spte))
 			break;
 	}
 	walk_shadow_page_lockless_end(vcpu);
 	return leaf;
 }
-/* return true if reserved bit is detected on spte. */
+/* return true if reserved bit(s) are detected on a valid, non-MMIO SPTE. */
 static bool get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep)
 {
-	u64 sptes[PT64_ROOT_MAX_LEVEL];
+	u64 sptes[PT64_ROOT_MAX_LEVEL + 1];
 	struct rsvd_bits_validate *rsvd_check;
-	int root = vcpu->arch.mmu->shadow_root_level;
+	int root, leaf, level;
-	int leaf;
-	int level;
 	bool reserved = false;
 	if (!VALID_PAGE(vcpu->arch.mmu->root_hpa)) {
 	}
 	if (is_tdp_mmu_root(vcpu->kvm, vcpu->arch.mmu->root_hpa))
-		leaf = kvm_tdp_mmu_get_walk(vcpu, addr, sptes);
+		leaf = kvm_tdp_mmu_get_walk(vcpu, addr, sptes, &root);
 	else
-		leaf = get_walk(vcpu, addr, sptes);
+		leaf = get_walk(vcpu, addr, sptes, &root);
+	if (unlikely(leaf < 0)) {
+		*sptep = 0ull;
+		return reserved;
+	}
+	*sptep = sptes[leaf];
+	/*
+	 * Skip reserved bits checks on the terminal leaf if it's not a valid
+	 * SPTE.  Note, this also (intentionally) skips MMIO SPTEs, which, by
+	 * design, always have reserved bits set.  The purpose of the checks is
+	 * to detect reserved bits on non-MMIO SPTEs. i.e. buggy SPTEs.
+	 */
+	if (!is_shadow_present_pte(sptes[leaf]))
+		leaf++;
 	rsvd_check = &vcpu->arch.mmu->shadow_zero_check;
-	for (level = root; level >= leaf; level--) {
+	for (level = root; level >= leaf; level--)
-		if (!is_shadow_present_pte(sptes[level - 1]))
-			break;
 		/*
 		 * Use a bitwise-OR instead of a logical-OR to aggregate the
 		 * reserved bit and EPT's invalid memtype/XWR checks to avoid
 		 * adding a Jcc in the loop.
 		 */
-		reserved |= __is_bad_mt_xwr(rsvd_check, sptes[level - 1]) |
+		reserved |= __is_bad_mt_xwr(rsvd_check, sptes[level]) |
-			    __is_rsvd_bits_set(rsvd_check, sptes[level - 1],
+			    __is_rsvd_bits_set(rsvd_check, sptes[level], level);
-					       level);
-	}
 	if (reserved) {
 		pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n",
 		       __func__, addr);
 		for (level = root; level >= leaf; level--)
 			pr_err("------ spte 0x%llx level %d.\n",
-			       sptes[level - 1], level);
+			       sptes[level], level);
 	}
-	*sptep = sptes[leaf - 1];
 	return reserved;
 }

arch/x86/kvm/mmu/tdp_mmu.c+54−59

 	WARN_ON(!list_empty(&kvm->arch.tdp_mmu_roots));
 }
-#define for_each_tdp_mmu_root(_kvm, _root)			    \
+static void tdp_mmu_put_root(struct kvm *kvm, struct kvm_mmu_page *root)
+{
+	if (kvm_mmu_put_root(kvm, root))
+		kvm_tdp_mmu_free_root(kvm, root);
+}
+static inline bool tdp_mmu_next_root_valid(struct kvm *kvm,
+					   struct kvm_mmu_page *root)
+{
+	lockdep_assert_held(&kvm->mmu_lock);
+	if (list_entry_is_head(root, &kvm->arch.tdp_mmu_roots, link))
+		return false;
+	kvm_mmu_get_root(kvm, root);
+	return true;
+}
+static inline struct kvm_mmu_page *tdp_mmu_next_root(struct kvm *kvm,
+						     struct kvm_mmu_page *root)
+{
+	struct kvm_mmu_page *next_root;
+	next_root = list_next_entry(root, link);
+	tdp_mmu_put_root(kvm, root);
+	return next_root;
+}
+/*
+ * Note: this iterator gets and puts references to the roots it iterates over.
+ * This makes it safe to release the MMU lock and yield within the loop, but
+ * if exiting the loop early, the caller must drop the reference to the most
+ * recent root. (Unless keeping a live reference is desirable.)
+ */
+#define for_each_tdp_mmu_root_yield_safe(_kvm, _root)				\
+	for (_root = list_first_entry(&_kvm->arch.tdp_mmu_roots,	\
+				      typeof(*_root), link);		\
+	     tdp_mmu_next_root_valid(_kvm, _root);			\
+	     _root = tdp_mmu_next_root(_kvm, _root))
+#define for_each_tdp_mmu_root(_kvm, _root)				\
 	list_for_each_entry(_root, &_kvm->arch.tdp_mmu_roots, link)
 bool is_tdp_mmu_root(struct kvm *kvm, hpa_t hpa)
 	struct kvm_mmu_page *root;
 	bool flush = false;
-	for_each_tdp_mmu_root(kvm, root) {
+	for_each_tdp_mmu_root_yield_safe(kvm, root)
-		/*
-		 * Take a reference on the root so that it cannot be freed if
-		 * this thread releases the MMU lock and yields in this loop.
-		 */
-		kvm_mmu_get_root(kvm, root);
 		flush |= zap_gfn_range(kvm, root, start, end, true);
-		kvm_mmu_put_root(kvm, root);
-	}
 	return flush;
 }
 	int ret = 0;
 	int as_id;
-	for_each_tdp_mmu_root(kvm, root) {
+	for_each_tdp_mmu_root_yield_safe(kvm, root) {
-		/*
-		 * Take a reference on the root so that it cannot be freed if
-		 * this thread releases the MMU lock and yields in this loop.
-		 */
-		kvm_mmu_get_root(kvm, root);
 		as_id = kvm_mmu_page_as_id(root);
 		slots = __kvm_memslots(kvm, as_id);
 		kvm_for_each_memslot(memslot, slots) {
 			ret |= handler(kvm, memslot, root, gfn_start,
 				       gfn_end, data);
 		}
-		kvm_mmu_put_root(kvm, root);
 	}
 	return ret;
 	int root_as_id;
 	bool spte_set = false;
-	for_each_tdp_mmu_root(kvm, root) {
+	for_each_tdp_mmu_root_yield_safe(kvm, root) {
 		root_as_id = kvm_mmu_page_as_id(root);
 		if (root_as_id != slot->as_id)
 			continue;
-		/*
-		 * Take a reference on the root so that it cannot be freed if
-		 * this thread releases the MMU lock and yields in this loop.
-		 */
-		kvm_mmu_get_root(kvm, root);
 		spte_set |= wrprot_gfn_range(kvm, root, slot->base_gfn,
 			     slot->base_gfn + slot->npages, min_level);
-		kvm_mmu_put_root(kvm, root);
 	}
 	return spte_set;
 	int root_as_id;
 	bool spte_set = false;
-	for_each_tdp_mmu_root(kvm, root) {
+	for_each_tdp_mmu_root_yield_safe(kvm, root) {
 		root_as_id = kvm_mmu_page_as_id(root);
 		if (root_as_id != slot->as_id)
 			continue;
-		/*
-		 * Take a reference on the root so that it cannot be freed if
-		 * this thread releases the MMU lock and yields in this loop.
-		 */
-		kvm_mmu_get_root(kvm, root);
 		spte_set |= clear_dirty_gfn_range(kvm, root, slot->base_gfn,
 				slot->base_gfn + slot->npages);
-		kvm_mmu_put_root(kvm, root);
 	}
 	return spte_set;
 	int root_as_id;
 	bool spte_set = false;
-	for_each_tdp_mmu_root(kvm, root) {
+	for_each_tdp_mmu_root_yield_safe(kvm, root) {
 		root_as_id = kvm_mmu_page_as_id(root);
 		if (root_as_id != slot->as_id)
 			continue;
-		/*
-		 * Take a reference on the root so that it cannot be freed if
-		 * this thread releases the MMU lock and yields in this loop.
-		 */
-		kvm_mmu_get_root(kvm, root);
 		spte_set |= set_dirty_gfn_range(kvm, root, slot->base_gfn,
 				slot->base_gfn + slot->npages);
-		kvm_mmu_put_root(kvm, root);
 	}
 	return spte_set;
 }
 	struct kvm_mmu_page *root;
 	int root_as_id;
-	for_each_tdp_mmu_root(kvm, root) {
+	for_each_tdp_mmu_root_yield_safe(kvm, root) {
 		root_as_id = kvm_mmu_page_as_id(root);
 		if (root_as_id != slot->as_id)
 			continue;
-		/*
-		 * Take a reference on the root so that it cannot be freed if
-		 * this thread releases the MMU lock and yields in this loop.
-		 */
-		kvm_mmu_get_root(kvm, root);
 		zap_collapsible_spte_range(kvm, root, slot->base_gfn,
 					   slot->base_gfn + slot->npages);
-		kvm_mmu_put_root(kvm, root);
 	}
 }
  * Return the level of the lowest level SPTE added to sptes.
  * That SPTE may be non-present.
  */
-int kvm_tdp_mmu_get_walk(struct kvm_vcpu *vcpu, u64 addr, u64 *sptes)
+int kvm_tdp_mmu_get_walk(struct kvm_vcpu *vcpu, u64 addr, u64 *sptes,
+			 int *root_level)
 {
 	struct tdp_iter iter;
 	struct kvm_mmu *mmu = vcpu->arch.mmu;
-	int leaf = vcpu->arch.mmu->shadow_root_level;
 	gfn_t gfn = addr >> PAGE_SHIFT;
+	int leaf = -1;
+	*root_level = vcpu->arch.mmu->shadow_root_level;
 	tdp_mmu_for_each_pte(iter, mmu, gfn, gfn + 1) {
 		leaf = iter.level;
-		sptes[leaf - 1] = iter.old_spte;
+		sptes[leaf] = iter.old_spte;
 	}
 	return leaf;

arch/x86/kvm/mmu/tdp_mmu.h+3−1

@@ -44,5 +44,7 @@ void kvm_tdp_mmu_zap_collapsible_sptes(struct kvm *kvm, · 43 unmodified lines
44	bool kvm_tdp_mmu_write_protect_gfn(struct kvm *kvm,	44	bool kvm_tdp_mmu_write_protect_gfn(struct kvm *kvm,
45	struct kvm_memory_slot *slot, gfn_t gfn);	45	struct kvm_memory_slot *slot, gfn_t gfn);
46		46
47	int kvm_tdp_mmu_get_walk(struct kvm_vcpu vcpu, u64 addr, u64 sptes);	47	int kvm_tdp_mmu_get_walk(struct kvm_vcpu vcpu, u64 addr, u64 sptes,
		48	int *root_level);
		49
48	#endif /* __KVM_X86_MMU_TDP_MMU_H */	50	#endif /* __KVM_X86_MMU_TDP_MMU_H */

arch/x86/kvm/svm/nested.c+8−0

 static bool svm_get_nested_state_pages(struct kvm_vcpu *vcpu)
 {
 	struct vcpu_svm *svm = to_svm(vcpu);
 	if (!nested_svm_vmrun_msrpm(svm)) {
 		vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
 		vcpu->run->internal.suberror =
 	svm->nested.vmcb12_gpa = 0;
 	WARN_ON_ONCE(svm->nested.nested_run_pending);
+	kvm_clear_request(KVM_REQ_GET_NESTED_STATE_PAGES, &svm->vcpu);
 	/* in case we halted in L2 */
 	svm->vcpu.arch.mp_state = KVM_MP_STATE_RUNNABLE;
 		leave_guest_mode(&svm->vcpu);
 		copy_vmcb_control_area(&vmcb->control, &hsave->control);
 		nested_svm_uninit_mmu_context(&svm->vcpu);
+		vmcb_mark_all_dirty(svm->vmcb);
 	}
 	kvm_clear_request(KVM_REQ_GET_NESTED_STATE_PAGES, &svm->vcpu);
 	 * in the registers, the save area of the nested state instead
 	 * contains saved L1 state.
 	 */
+	svm->nested.nested_run_pending =
+		!!(kvm_state->flags & KVM_STATE_NESTED_RUN_PENDING);
 	copy_vmcb_control_area(&hsave->control, &svm->vmcb->control);
 	hsave->save = *save;

arch/x86/kvm/svm/sev.c+23−1

 			goto vmgexit_err;
 		break;
 	case SVM_VMGEXIT_NMI_COMPLETE:
+	case SVM_VMGEXIT_AP_HLT_LOOP:
 	case SVM_VMGEXIT_AP_JUMP_TABLE:
 	case SVM_VMGEXIT_UNSUPPORTED_EVENT:
 		break;
 	case SVM_VMGEXIT_NMI_COMPLETE:
 		ret = svm_invoke_exit_handler(svm, SVM_EXIT_IRET);
 		break;
+	case SVM_VMGEXIT_AP_HLT_LOOP:
+		ret = kvm_emulate_ap_reset_hold(&svm->vcpu);
+		break;
 	case SVM_VMGEXIT_AP_JUMP_TABLE: {
 		struct kvm_sev_info *sev = &to_kvm_svm(svm->vcpu.kvm)->sev_info;
 	 * of which one step is to perform a VMLOAD. Since hardware does not
 	 * perform a VMSAVE on VMRUN, the host savearea must be updated.
 	 */
-	asm volatile(__ex("vmsave") : : "a" (__sme_page_pa(sd->save_area)) : "memory");
+	asm volatile(__ex("vmsave %0") : : "a" (__sme_page_pa(sd->save_area)) : "memory");
 	/*
 	 * Certain MSRs are restored on VMEXIT, only save ones that aren't
 		wrmsrl(host_save_user_msrs[i].index, svm->host_user_msrs[i]);
 	}
 }
+void sev_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
+{
+	struct vcpu_svm *svm = to_svm(vcpu);
+	/* First SIPI: Use the values as initially set by the VMM */
+	if (!svm->received_first_sipi) {
+		svm->received_first_sipi = true;
+		return;
+	}
+	/*
+	 * Subsequent SIPI: Return from an AP Reset Hold VMGEXIT, where
+	 * the guest will set the CS and RIP. Set SW_EXIT_INFO_2 to a
+	 * non-zero value.
+	 */
+	ghcb_set_sw_exit_info_2(svm->ghcb, 1);
+}

arch/x86/kvm/svm/svm.c+10−2

 	return EXIT_FASTPATH_NONE;
 }
-void __svm_vcpu_run(unsigned long vmcb_pa, unsigned long *regs);
 static noinstr void svm_vcpu_enter_exit(struct kvm_vcpu *vcpu,
 					struct vcpu_svm *svm)
 {
 		   (vmcb_is_intercept(&svm->vmcb->control, INTERCEPT_INIT));
 }
+static void svm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
+{
+	if (!sev_es_guest(vcpu->kvm))
+		return kvm_vcpu_deliver_sipi_vector(vcpu, vector);
+	sev_vcpu_deliver_sipi_vector(vcpu, vector);
+}
 static void svm_vm_destroy(struct kvm *kvm)
 {
 	avic_vm_destroy(kvm);
 	.msr_filter_changed = svm_msr_filter_changed,
 	.complete_emulated_msr = svm_complete_emulated_msr,
+	.vcpu_deliver_sipi_vector = svm_vcpu_deliver_sipi_vector,
 };
 static struct kvm_x86_init_ops svm_init_ops __initdata = {

arch/x86/kvm/svm/svm.h+2−0

 	struct vmcb_save_area *vmsa;
 	struct ghcb *ghcb;
 	struct kvm_host_map ghcb_map;
+	bool received_first_sipi;
 	/* SEV-ES scratch area support */
 	void *ghcb_sa;
 void sev_es_create_vcpu(struct vcpu_svm *svm);
 void sev_es_vcpu_load(struct vcpu_svm *svm, int cpu);
 void sev_es_vcpu_put(struct vcpu_svm *svm);
+void sev_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector);
 /* vmenter.S */

arch/x86/kvm/vmx/nested.c+2−0

@@ -4442,6 +4442,8 @@ void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 vm_exit_reason, · 4441 unmodified lines
4442	/* trying to cancel vmlaunch/vmresume is a bug */	4442	/* trying to cancel vmlaunch/vmresume is a bug */
4443	WARN_ON_ONCE(vmx->nested.nested_run_pending);	4443	WARN_ON_ONCE(vmx->nested.nested_run_pending);
4444		4444
		4445	kvm_clear_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu);
		4446
4445	/* Service the TLB flush request for L2 before switching to L1. */	4447	/* Service the TLB flush request for L2 before switching to L1. */
4446	if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu))	4448	if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu))
4447	kvm_vcpu_flush_tlb_current(vcpu);	4449	kvm_vcpu_flush_tlb_current(vcpu);

arch/x86/kvm/vmx/vmx.c+2−0

@@ -7707,6 +7707,8 @@ static struct kvm_x86_ops vmx_x86_ops __initdata = { · 7706 unmodified lines
7707	.msr_filter_changed = vmx_msr_filter_changed,	7707	.msr_filter_changed = vmx_msr_filter_changed,
7708	.complete_emulated_msr = kvm_complete_insn_gp,	7708	.complete_emulated_msr = kvm_complete_insn_gp,
7709	.cpu_dirty_log_size = vmx_cpu_dirty_log_size,	7709	.cpu_dirty_log_size = vmx_cpu_dirty_log_size,
		7710
		7711	.vcpu_deliver_sipi_vector = kvm_vcpu_deliver_sipi_vector,
7710	};	7712	};
7711		7713
7712	static __init int hardware_setup(void)	7714	static __init int hardware_setup(void)

arch/x86/kvm/x86.c+24−6

 	kmem_cache_destroy(x86_fpu_cache);
 }
-int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
+static int __kvm_vcpu_halt(struct kvm_vcpu *vcpu, int state, int reason)
 {
 	++vcpu->stat.halt_exits;
 	if (lapic_in_kernel(vcpu)) {
-		vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
+		vcpu->arch.mp_state = state;
 		return 1;
 	} else {
-		vcpu->run->exit_reason = KVM_EXIT_HLT;
+		vcpu->run->exit_reason = reason;
 		return 0;
 	}
 }
+int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
+{
+	return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT);
+}
 EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
 }
 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
+int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu)
+{
+	int ret = kvm_skip_emulated_instruction(vcpu);
+	return __kvm_vcpu_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD, KVM_EXIT_AP_RESET_HOLD) && ret;
+}
+EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold);
 #ifdef CONFIG_X86_64
 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
 			        unsigned long clock_type)
 	if (kvm_request_pending(vcpu)) {
 		if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) {
-			if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) {
+			if (WARN_ON_ONCE(!is_guest_mode(vcpu)))
+				;
+			else if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) {
 				r = 0;
 				goto out;
 			}
 	kvm_apic_accept_events(vcpu);
 	switch(vcpu->arch.mp_state) {
 	case KVM_MP_STATE_HALTED:
+	case KVM_MP_STATE_AP_RESET_HOLD:
 		vcpu->arch.pv.pv_unhalted = false;
 		vcpu->arch.mp_state =
 			KVM_MP_STATE_RUNNABLE;
 		kvm_load_guest_fpu(vcpu);
 	kvm_apic_accept_events(vcpu);
-	if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
+	if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED ||
-					vcpu->arch.pv.pv_unhalted)
+	     vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) &&
+	    vcpu->arch.pv.pv_unhalted)
 		mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
 	else
 		mp_state->mp_state = vcpu->arch.mp_state;
 	kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
 	kvm_rip_write(vcpu, 0);
 }
+EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector);
 int kvm_arch_hardware_enable(void)
 {

arch/x86/mm/pgtable.c+2−0

@@ -829,6 +829,8 @@ int pud_free_pmd_page(pud_t *pud, unsigned long addr) · 828 unmodified lines
829	}	829	}
830		830
831	free_page((unsigned long)pmd_sv);	831	free_page((unsigned long)pmd_sv);
		832
		833	pgtable_pmd_page_dtor(virt_to_page(pmd));
832	free_page((unsigned long)pmd);	834	free_page((unsigned long)pmd);
833		835
834	return 1;	836	return 1;

arch/x86/xen/enlighten_hvm.c+12−3

 	else
 		per_cpu(xen_vcpu_id, cpu) = cpu;
 	rc = xen_vcpu_setup(cpu);
-	if (rc)
+	if (rc || !xen_have_vector_callback)
 		return rc;
-	if (xen_have_vector_callback && xen_feature(XENFEAT_hvm_safe_pvclock))
+	if (xen_feature(XENFEAT_hvm_safe_pvclock))
 		xen_setup_timer(cpu);
 	rc = xen_smp_intr_init(cpu);
        return 0;
 }
+static bool no_vector_callback __initdata;
 static void __init xen_hvm_guest_init(void)
 {
 	if (xen_pv_domain())
 	xen_panic_handler_init();
-	if (xen_feature(XENFEAT_hvm_callback_vector))
+	if (!no_vector_callback && xen_feature(XENFEAT_hvm_callback_vector))
 		xen_have_vector_callback = 1;
 	xen_hvm_smp_init();
 }
 early_param("xen_nopv", xen_parse_nopv);
+static __init int xen_parse_no_vector_callback(char *arg)
+{
+	no_vector_callback = true;
+	return 0;
+}
+early_param("xen_no_vector_callback", xen_parse_no_vector_callback);
 bool __init xen_hvm_need_lapic(void)
 {
 	if (xen_pv_domain())

arch/x86/xen/smp_hvm.c+17−10

 	int cpu;
 	native_smp_prepare_cpus(max_cpus);
-	WARN_ON(xen_smp_intr_init(0));
-	xen_init_lock_cpu(0);
+	if (xen_have_vector_callback) {
+		WARN_ON(xen_smp_intr_init(0));
+		xen_init_lock_cpu(0);
+	}
 	for_each_possible_cpu(cpu) {
 		if (cpu == 0)
 static void xen_hvm_cpu_die(unsigned int cpu)
 {
 	if (common_cpu_die(cpu) == 0) {
-		xen_smp_intr_free(cpu);
+		if (xen_have_vector_callback) {
-		xen_uninit_lock_cpu(cpu);
+			xen_smp_intr_free(cpu);
-		xen_teardown_timer(cpu);
+			xen_uninit_lock_cpu(cpu);
+			xen_teardown_timer(cpu);
+		}
 	}
 }
 #else
 void __init xen_hvm_smp_init(void)
 {
-	if (!xen_have_vector_callback)
+	smp_ops.smp_prepare_boot_cpu = xen_hvm_smp_prepare_boot_cpu;
+	smp_ops.smp_prepare_cpus = xen_hvm_smp_prepare_cpus;
+	smp_ops.smp_cpus_done = xen_smp_cpus_done;
+	smp_ops.cpu_die = xen_hvm_cpu_die;
+	if (!xen_have_vector_callback) {
+		nopvspin = true;
 		return;
+	}
-	smp_ops.smp_prepare_cpus = xen_hvm_smp_prepare_cpus;
 	smp_ops.smp_send_reschedule = xen_smp_send_reschedule;
-	smp_ops.cpu_die = xen_hvm_cpu_die;
 	smp_ops.send_call_func_ipi = xen_smp_send_call_function_ipi;
 	smp_ops.send_call_func_single_ipi = xen_smp_send_call_function_single_ipi;
-	smp_ops.smp_prepare_boot_cpu = xen_hvm_smp_prepare_boot_cpu;
-	smp_ops.smp_cpus_done = xen_smp_cpus_done;
 }

arch/xtensa/include/asm/Kbuild+0−1

@@ -2,7 +2,6 @@ · 1 unmodified line
2	generated-y += syscall_table.h	2	generated-y += syscall_table.h
3	generic-y += extable.h	3	generic-y += extable.h
4	generic-y += kvm_para.h	4	generic-y += kvm_para.h
5	generic-y += local64.h
6	generic-y += mcs_spinlock.h	5	generic-y += mcs_spinlock.h
7	generic-y += param.h	6	generic-y += param.h
8	generic-y += qrwlock.h	7	generic-y += qrwlock.h

block/bfq-iosched.c+4−4

@@ -6332,13 +6332,13 @@ static unsigned int bfq_update_depths(struct bfq_data *bfqd, · 6331 unmodified lines
6332	* limit 'something'.	6332	* limit 'something'.
6333	*/	6333	*/
6334	/* no more than 50% of tags for async I/O */	6334	/* no more than 50% of tags for async I/O */
6335	bfqd->word_depths[0][0] = max((1U << bt->sb.shift) >> 1, 1U);	6335	bfqd->word_depths[0][0] = max(bt->sb.depth >> 1, 1U);
6336	/*	6336	/*
6337	* no more than 75% of tags for sync writes (25% extra tags	6337	* no more than 75% of tags for sync writes (25% extra tags
6338	* w.r.t. async I/O, to prevent async I/O from starving sync	6338	* w.r.t. async I/O, to prevent async I/O from starving sync
6339	* writes)	6339	* writes)
6340	*/	6340	*/
6341	bfqd->word_depths[0][1] = max(((1U << bt->sb.shift) * 3) >> 2, 1U);	6341	bfqd->word_depths[0][1] = max((bt->sb.depth * 3) >> 2, 1U);
6342		6342
6343	/*	6343	/*
6344	* In-word depths in case some bfq_queue is being weight-	6344	* In-word depths in case some bfq_queue is being weight-
@@ -6348,9 +6348,9 @@ static unsigned int bfq_update_depths(struct bfq_data *bfqd, · 3 unmodified lines
6348	* shortage.	6348	* shortage.
6349	*/	6349	*/
6350	/* no more than ~18% of tags for async I/O */	6350	/* no more than ~18% of tags for async I/O */
6351	bfqd->word_depths[1][0] = max(((1U << bt->sb.shift) * 3) >> 4, 1U);	6351	bfqd->word_depths[1][0] = max((bt->sb.depth * 3) >> 4, 1U);
6352	/* no more than ~37% of tags for sync writes (~20% extra tags) */	6352	/* no more than ~37% of tags for sync writes (~20% extra tags) */
6353	bfqd->word_depths[1][1] = max(((1U << bt->sb.shift) * 6) >> 4, 1U);	6353	bfqd->word_depths[1][1] = max((bt->sb.depth * 6) >> 4, 1U);
6354		6354
6355	for (i = 0; i < 2; i++)	6355	for (i = 0; i < 2; i++)
6356	for (j = 0; j < 2; j++)	6356	for (j = 0; j < 2; j++)

block/blk-core.c+7−6

 #include <linux/bio.h>
 #include <linux/blkdev.h>
 #include <linux/blk-mq.h>
+#include <linux/blk-pm.h>
 #include <linux/highmem.h>
 #include <linux/mm.h>
 #include <linux/pagemap.h>
 /**
  * blk_queue_enter() - try to increase q->q_usage_counter
  * @q: request queue pointer
- * @flags: BLK_MQ_REQ_NOWAIT and/or BLK_MQ_REQ_PREEMPT
+ * @flags: BLK_MQ_REQ_NOWAIT and/or BLK_MQ_REQ_PM
  */
 int blk_queue_enter(struct request_queue *q, blk_mq_req_flags_t flags)
 {
-	const bool pm = flags & BLK_MQ_REQ_PREEMPT;
+	const bool pm = flags & BLK_MQ_REQ_PM;
 	while (true) {
 		bool success = false;
 			 * responsible for ensuring that that counter is
 			 * globally visible before the queue is unfrozen.
 			 */
-			if (pm || !blk_queue_pm_only(q)) {
+			if ((pm && queue_rpm_status(q) != RPM_SUSPENDED) ||
+			    !blk_queue_pm_only(q)) {
 				success = true;
 			} else {
 				percpu_ref_put(&q->q_usage_counter);
 		wait_event(q->mq_freeze_wq,
 			   (!q->mq_freeze_depth &&
-			    (pm || (blk_pm_request_resume(q),
+			    blk_pm_resume_queue(pm, q)) ||
-				    !blk_queue_pm_only(q)))) ||
 			   blk_queue_dying(q));
 		if (blk_queue_dying(q))
 			return -ENODEV;
 	struct request *req;
 	WARN_ON_ONCE(op & REQ_NOWAIT);
-	WARN_ON_ONCE(flags & ~(BLK_MQ_REQ_NOWAIT | BLK_MQ_REQ_PREEMPT));
+	WARN_ON_ONCE(flags & ~(BLK_MQ_REQ_NOWAIT | BLK_MQ_REQ_PM));
 	req = blk_mq_alloc_request(q, op, flags);
 	if (!IS_ERR(req) && q->mq_ops->initialize_rq_fn)

block/blk-iocost.c+11−5

 	bool use_debt, ioc_locked;
 	unsigned long flags;
-	/* bypass IOs if disabled or for root cgroup */
+	/* bypass IOs if disabled, still initializing, or for root cgroup */
-	if (!ioc->enabled || !iocg->level)
+	if (!ioc->enabled || !iocg || !iocg->level)
 		return;
 	/* calculate the absolute vtime cost */
 			   struct bio *bio)
 {
 	struct ioc_gq *iocg = blkg_to_iocg(bio->bi_blkg);
-	struct ioc *ioc = iocg->ioc;
+	struct ioc *ioc = rqos_to_ioc(rqos);
 	sector_t bio_end = bio_end_sector(bio);
 	struct ioc_now now;
 	u64 vtime, abs_cost, cost;
 	unsigned long flags;
-	/* bypass if disabled or for root cgroup */
+	/* bypass if disabled, still initializing, or for root cgroup */
-	if (!ioc->enabled || !iocg->level)
+	if (!ioc->enabled || !iocg || !iocg->level)
 		return;
 	abs_cost = calc_vtime_cost(bio, iocg, true);
 	ioc_refresh_params(ioc, true);
 	spin_unlock_irq(&ioc->lock);
+	/*
+	 * rqos must be added before activation to allow iocg_pd_init() to
+	 * lookup the ioc from q. This means that the rqos methods may get
+	 * called before policy activation completion, can't assume that the
+	 * target bio has an iocg associated and need to test for NULL iocg.
+	 */
 	rq_qos_add(q, rqos);
 	ret = blkcg_activate_policy(q, &blkcg_policy_iocost);
 	if (ret) {

block/blk-mq-debugfs.c+2−1

 	QUEUE_FLAG_NAME(PCI_P2PDMA),
 	QUEUE_FLAG_NAME(ZONE_RESETALL),
 	QUEUE_FLAG_NAME(RQ_ALLOC_TIME),
+	QUEUE_FLAG_NAME(NOWAIT),
 };
 #undef QUEUE_FLAG_NAME
 	HCTX_FLAG_NAME(BLOCKING),
 	HCTX_FLAG_NAME(NO_SCHED),
 	HCTX_FLAG_NAME(STACKING),
+	HCTX_FLAG_NAME(TAG_HCTX_SHARED),
 };
 #undef HCTX_FLAG_NAME
 	RQF_NAME(MIXED_MERGE),
 	RQF_NAME(MQ_INFLIGHT),
 	RQF_NAME(DONTPREP),
-	RQF_NAME(PREEMPT),
 	RQF_NAME(FAILED),
 	RQF_NAME(QUIET),
 	RQF_NAME(ELVPRIV),

block/blk-mq.c+2−2

@@ -294,8 +294,8 @@ static struct request blk_mq_rq_ctx_init(struct blk_mq_alloc_data data, · 293 unmodified lines
294	rq->mq_hctx = data->hctx;	294	rq->mq_hctx = data->hctx;
295	rq->rq_flags = 0;	295	rq->rq_flags = 0;
296	rq->cmd_flags = data->cmd_flags;	296	rq->cmd_flags = data->cmd_flags;
297	if (data->flags & BLK_MQ_REQ_PREEMPT)	297	if (data->flags & BLK_MQ_REQ_PM)
298	rq->rq_flags \|= RQF_PREEMPT;	298	rq->rq_flags \|= RQF_PM;
299	if (blk_queue_io_stat(data->q))	299	if (blk_queue_io_stat(data->q))
300	rq->rq_flags \|= RQF_IO_STAT;	300	rq->rq_flags \|= RQF_IO_STAT;
301	INIT_LIST_HEAD(&rq->queuelist);	301	INIT_LIST_HEAD(&rq->queuelist);

block/blk-pm.c+9−6

 	WARN_ON_ONCE(q->rpm_status != RPM_ACTIVE);
+	spin_lock_irq(&q->queue_lock);
+	q->rpm_status = RPM_SUSPENDING;
+	spin_unlock_irq(&q->queue_lock);
 	/*
 	 * Increase the pm_only counter before checking whether any
 	 * non-PM blk_queue_enter() calls are in progress to avoid that any
 	/* Switch q_usage_counter back to per-cpu mode. */
 	blk_mq_unfreeze_queue(q);
-	spin_lock_irq(&q->queue_lock);
+	if (ret < 0) {
-	if (ret < 0)
+		spin_lock_irq(&q->queue_lock);
+		q->rpm_status = RPM_ACTIVE;
 		pm_runtime_mark_last_busy(q->dev);
-	else
+		spin_unlock_irq(&q->queue_lock);
-		q->rpm_status = RPM_SUSPENDING;
-	spin_unlock_irq(&q->queue_lock);
-	if (ret)
 		blk_clear_pm_only(q);
+	}
 	return ret;
 }

block/blk-pm.h+9−5

 #include <linux/pm_runtime.h>
 #ifdef CONFIG_PM
-static inline void blk_pm_request_resume(struct request_queue *q)
+static inline int blk_pm_resume_queue(const bool pm, struct request_queue *q)
 {
-	if (q->dev && (q->rpm_status == RPM_SUSPENDED ||
+	if (!q->dev || !blk_queue_pm_only(q))
-		       q->rpm_status == RPM_SUSPENDING))
+		return 1;	/* Nothing to do */
-		pm_request_resume(q->dev);
+	if (pm && q->rpm_status != RPM_SUSPENDED)
+		return 1;	/* Request allowed */
+	pm_request_resume(q->dev);
+	return 0;
 }
 static inline void blk_pm_mark_last_busy(struct request *rq)
 		--rq->q->nr_pending;
 }
 #else
-static inline void blk_pm_request_resume(struct request_queue *q)
+static inline int blk_pm_resume_queue(const bool pm, struct request_queue *q)
 {
+	return 1;
 }
 static inline void blk_pm_mark_last_busy(struct request *rq)

block/genhd.c+7−4

 		part = rcu_dereference(ptbl->part[piter->idx]);
 		if (!part)
 			continue;
+		piter->part = bdgrab(part);
+		if (!piter->part)
+			continue;
 		if (!bdev_nr_sectors(part) &&
 		    !(piter->flags & DISK_PITER_INCL_EMPTY) &&
 		    !(piter->flags & DISK_PITER_INCL_EMPTY_PART0 &&
-		      piter->idx == 0))
+		      piter->idx == 0)) {
+			bdput(piter->part);
+			piter->part = NULL;
 			continue;
+		}
-		piter->part = bdgrab(part);
-		if (!piter->part)
-			continue;
 		piter->idx += inc;
 		break;
 	}

crypto/asymmetric_keys/asym_tpm.c+1−1

@@ -354,7 +354,7 @@ static uint32_t derive_pub_key(const void pub_key, uint32_t len, uint8_t buf) · 353 unmodified lines
354	memcpy(cur, e, sizeof(e));	354	memcpy(cur, e, sizeof(e));
355	cur += sizeof(e);	355	cur += sizeof(e);
356	/* Zero parameters to satisfy set_pub_key ABI. */	356	/* Zero parameters to satisfy set_pub_key ABI. */
357	memset(cur, 0, SETKEY_PARAMS_SIZE);	357	memzero_explicit(cur, SETKEY_PARAMS_SIZE);
358		358
359	return cur - buf;	359	return cur - buf;
360	}	360	}

crypto/ecdh.c+2−1

@@ -39,7 +39,8 @@ static int ecdh_set_secret(struct crypto_kpp tfm, const void buf, · 38 unmodified lines
39	struct ecdh params;	39	struct ecdh params;
40	unsigned int ndigits;	40	unsigned int ndigits;
41		41
42	if (crypto_ecdh_decode_key(buf, len, &params) < 0)	42	if (crypto_ecdh_decode_key(buf, len, &params) < 0 \|\|
		43	params.key_size > sizeof(ctx->private_key))
43	return -EINVAL;	44	return -EINVAL;
44		45
45	ndigits = ecdh_supported_curve(params.curve_id);	46	ndigits = ecdh_supported_curve(params.curve_id);

crypto/xor.c+2−0

@@ -107,6 +107,8 @@ do_xor_speed(struct xor_block_template tmpl, void b1, void *b2) · 106 unmodified lines
107	preempt_enable();	107	preempt_enable();
108		108
109	// bytes/ns == GB/s, multiply by 1000 to get MB/s [not MiB/s]	109	// bytes/ns == GB/s, multiply by 1000 to get MB/s [not MiB/s]
		110	if (!min)
		111	min = 1;
110	speed = (1000 * REPS * BENCH_SIZE) / (unsigned int)ktime_to_ns(min);	112	speed = (1000 * REPS * BENCH_SIZE) / (unsigned int)ktime_to_ns(min);
111	tmpl->speed = speed;	113	tmpl->speed = speed;
112		114

drivers/acpi/Kconfig+0−6

 	  This helps support hotplug of nodes, CPUs, and memory.
-	  To compile this driver as a module, choose M here:
-	  the module will be called container.
 config ACPI_HOTPLUG_MEMORY
 	bool "Memory Hotplug"
 	depends on MEMORY_HOTPLUG
 	  removing memory devices at runtime, you need not enable
 	  this driver.
-	  To compile this driver as a module, choose M here:
-	  the module will be called acpi_memhotplug.
 config ACPI_HOTPLUG_IOAPIC
 	bool
 	depends on PCI

drivers/acpi/internal.h+1−1

@@ -97,7 +97,7 @@ void acpi_scan_table_handler(u32 event, void table, void context); · 96 unmodified lines
97	extern struct list_head acpi_bus_id_list;	97	extern struct list_head acpi_bus_id_list;
98		98
99	struct acpi_device_bus_id {	99	struct acpi_device_bus_id {
100	char bus_id[15];	100	const char *bus_id;
101	unsigned int instance_no;	101	unsigned int instance_no;
102	struct list_head node;	102	struct list_head node;
103	};	103	};

drivers/acpi/scan.c+14−1

 				acpi_device_bus_id->instance_no--;
 			else {
 				list_del(&acpi_device_bus_id->node);
+				kfree_const(acpi_device_bus_id->bus_id);
 				kfree(acpi_device_bus_id);
 			}
 			break;
 	}
 	if (!found) {
 		acpi_device_bus_id = new_bus_id;
-		strcpy(acpi_device_bus_id->bus_id, acpi_device_hid(device));
+		acpi_device_bus_id->bus_id =
+			kstrdup_const(acpi_device_hid(device), GFP_KERNEL);
+		if (!acpi_device_bus_id->bus_id) {
+			pr_err(PREFIX "Memory allocation error for bus id\n");
+			result = -ENOMEM;
+			goto err_free_new_bus_id;
+		}
 		acpi_device_bus_id->instance_no = 0;
 		list_add_tail(&acpi_device_bus_id->node, &acpi_bus_id_list);
 	}
 	if (device->parent)
 		list_del(&device->node);
 	list_del(&device->wakeup_list);
+ err_free_new_bus_id:
+	if (!found)
+		kfree(new_bus_id);
 	mutex_unlock(&acpi_device_lock);
  err_detach:

drivers/acpi/x86/s2idle.c+1−13

 	for (i = 0; i < out_obj->package.count; i++) {
 		union acpi_object *package = &out_obj->package.elements[i];
-		struct lpi_device_info_amd info = { };
-		if (package->type == ACPI_TYPE_INTEGER) {
+		if (package->type == ACPI_TYPE_PACKAGE) {
-			switch (i) {
-			case 0:
-				info.revision = package->integer.value;
-				break;
-			case 1:
-				info.count = package->integer.value;
-				break;
-			}
-		} else if (package->type == ACPI_TYPE_PACKAGE) {
 			lpi_constraints_table = kcalloc(package->package.count,
 							sizeof(*lpi_constraints_table),
 							GFP_KERNEL);
 				for (k = 0; k < info_obj->package.count; ++k) {
 					union acpi_object *obj = &info_obj->package.elements[k];
-					union acpi_object *obj_new;
 					list = &lpi_constraints_table[lpi_constraints_table_size];
 					list->min_dstate = -1;
-					obj_new = &obj[k];
 					switch (k) {
 					case 0:
 						dev_info.enabled = obj->integer.value;

drivers/atm/idt77252.c+1−1

@@ -3607,7 +3607,7 @@ static int idt77252_init_one(struct pci_dev *pcidev, · 3606 unmodified lines
3607		3607
3608	if ((err = dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(32)))) {	3608	if ((err = dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(32)))) {
3609	printk("idt77252: can't enable DMA for PCI device at %s\n", pci_name(pcidev));	3609	printk("idt77252: can't enable DMA for PCI device at %s\n", pci_name(pcidev));
3610	return err;	3610	goto err_out_disable_pdev;
3611	}	3611	}
3612		3612
3613	card = kzalloc(sizeof(struct idt77252_dev), GFP_KERNEL);	3613	card = kzalloc(sizeof(struct idt77252_dev), GFP_KERNEL);

drivers/base/core.c+8−1

  *
  * Set the device's firmware node pointer to @fwnode, but if a secondary
  * firmware node of the device is present, preserve it.
+ *
+ * Valid fwnode cases are:
+ *  - primary --> secondary --> -ENODEV
+ *  - primary --> NULL
+ *  - secondary --> -ENODEV
+ *  - NULL
  */
 void set_primary_fwnode(struct device *dev, struct fwnode_handle *fwnode)
 {
 	} else {
 		if (fwnode_is_primary(fn)) {
 			dev->fwnode = fn->secondary;
+			/* Set fn->secondary = NULL, so fn remains the primary fwnode */
 			if (!(parent && fn == parent->fwnode))
-				fn->secondary = ERR_PTR(-ENODEV);
+				fn->secondary = NULL;
 		} else {
 			dev->fwnode = NULL;
 		}

drivers/base/regmap/regmap-debugfs.c+7−2

 		devname = dev_name(map->dev);
 	if (name) {
-		map->debugfs_name = kasprintf(GFP_KERNEL, "%s-%s",
+		if (!map->debugfs_name) {
+			map->debugfs_name = kasprintf(GFP_KERNEL, "%s-%s",
 					      devname, name);
+			if (!map->debugfs_name)
+				return;
+		}
 		name = map->debugfs_name;
 	} else {
 		name = devname;
 	if (!strcmp(name, "dummy")) {
 		kfree(map->debugfs_name);
 		map->debugfs_name = kasprintf(GFP_KERNEL, "dummy%d",
 						dummy_index);
+		if (!map->debugfs_name)
+				return;
 		name = map->debugfs_name;
 		dummy_index++;
 	}

drivers/block/Kconfig+1−0

@@ -445,6 +445,7 @@ config BLK_DEV_RBD · 444 unmodified lines
445	config BLK_DEV_RSXX	445	config BLK_DEV_RSXX
446	tristate "IBM Flash Adapter 900GB Full Height PCIe Device Driver"	446	tristate "IBM Flash Adapter 900GB Full Height PCIe Device Driver"
447	depends on PCI	447	depends on PCI
		448	select CRC32
448	help	449	help
449	Device driver for IBM's high speed PCIe SSD	450	Device driver for IBM's high speed PCIe SSD
450	storage device: Flash Adapter 900GB Full Height.	451	storage device: Flash Adapter 900GB Full Height.

drivers/block/rnbd/Kconfig+1−0

@@ -7,6 +7,7 @@ config BLK_DEV_RNBD_CLIENT · 6 unmodified lines
7	tristate "RDMA Network Block Device driver client"	7	tristate "RDMA Network Block Device driver client"
8	depends on INFINIBAND_RTRS_CLIENT	8	depends on INFINIBAND_RTRS_CLIENT
9	select BLK_DEV_RNBD	9	select BLK_DEV_RNBD
		10	select SG_POOL
10	help	11	help
11	RNBD client is a network block device driver using rdma transport.	12	RNBD client is a network block device driver using rdma transport.
12		13

drivers/block/rnbd/README+1−0

@@ -90,3 +90,4 @@ Kleber Souza <kleber.souza@profitbricks.com> · 89 unmodified lines
90	Lutz Pogrell <lutz.pogrell@cloud.ionos.com>	90	Lutz Pogrell <lutz.pogrell@cloud.ionos.com>
91	Milind Dumbare <Milind.dumbare@gmail.com>	91	Milind Dumbare <Milind.dumbare@gmail.com>
92	Roman Penyaev <roman.penyaev@profitbricks.com>	92	Roman Penyaev <roman.penyaev@profitbricks.com>
		93	Swapnil Ingle <ingleswapnil@gmail.com>

drivers/block/rnbd/rnbd-clt.c+9−9

 	init_waitqueue_head(&iu->comp.wait);
 	iu->comp.errno = INT_MAX;
+	if (sg_alloc_table(&iu->sgt, 1, GFP_KERNEL)) {
+		rnbd_put_permit(sess, permit);
+		kfree(iu);
+		return NULL;
+	}
 	return iu;
 }
 static void rnbd_put_iu(struct rnbd_clt_session *sess, struct rnbd_iu *iu)
 {
 	if (atomic_dec_and_test(&iu->refcount)) {
+		sg_free_table(&iu->sgt);
 		rnbd_put_permit(sess, iu->permit);
 		kfree(iu);
 	}
 	iu->buf = NULL;
 	iu->dev = dev;
-	sg_alloc_table(&iu->sgt, 1, GFP_KERNEL);
 	msg.hdr.type	= cpu_to_le16(RNBD_MSG_CLOSE);
 	msg.device_id	= cpu_to_le32(device_id);
 		err = errno;
 	}
-	sg_free_table(&iu->sgt);
 	rnbd_put_iu(sess, iu);
 	return err;
 }
 	iu->buf = rsp;
 	iu->dev = dev;
-	sg_alloc_table(&iu->sgt, 1, GFP_KERNEL);
 	sg_init_one(iu->sgt.sgl, rsp, sizeof(*rsp));
 	msg.hdr.type	= cpu_to_le16(RNBD_MSG_OPEN);
 		err = errno;
 	}
-	sg_free_table(&iu->sgt);
 	rnbd_put_iu(sess, iu);
 	return err;
 }
 	iu->buf = rsp;
 	iu->sess = sess;
-	sg_alloc_table(&iu->sgt, 1, GFP_KERNEL);
 	sg_init_one(iu->sgt.sgl, rsp, sizeof(*rsp));
 	msg.hdr.type = cpu_to_le16(RNBD_MSG_SESS_INFO);
 	} else {
 		err = errno;
 	}
-	sg_free_table(&iu->sgt);
 	rnbd_put_iu(sess, iu);
 	return err;
 }
 	 */
 	list_for_each_entry_safe(sess, sn, &sess_list, list) {
-		WARN_ON(!rnbd_clt_get_sess(sess));
+		if (!rnbd_clt_get_sess(sess))
+			continue;
 		close_rtrs(sess);
 		list_for_each_entry_safe(dev, tn, &sess->devs_list, list) {
 			/*

drivers/block/rnbd/rnbd-srv.c+5−3

@@ -338,10 +338,12 @@ static int rnbd_srv_link_ev(struct rtrs_srv *rtrs, · 337 unmodified lines
338		338
339	void rnbd_srv_sess_dev_force_close(struct rnbd_srv_sess_dev *sess_dev)	339	void rnbd_srv_sess_dev_force_close(struct rnbd_srv_sess_dev *sess_dev)
340	{	340	{
341	mutex_lock(&sess_dev->sess->lock);	341	struct rnbd_srv_session *sess = sess_dev->sess;
342	rnbd_srv_destroy_dev_session_sysfs(sess_dev);	342
343	mutex_unlock(&sess_dev->sess->lock);
344	sess_dev->keep_id = true;	343	sess_dev->keep_id = true;
		344	mutex_lock(&sess->lock);
		345	rnbd_srv_destroy_dev_session_sysfs(sess_dev);
		346	mutex_unlock(&sess->lock);
345	}	347	}
346		348
347	static int process_msg_close(struct rtrs_srv *rtrs,	349	static int process_msg_close(struct rtrs_srv *rtrs,

drivers/clk/tegra/clk-tegra30.c+2−0

 	{ TEGRA30_CLK_I2S3_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
 	{ TEGRA30_CLK_I2S4_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
 	{ TEGRA30_CLK_VIMCLK_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
+	{ TEGRA30_CLK_HDA, TEGRA30_CLK_PLL_P, 102000000, 0 },
+	{ TEGRA30_CLK_HDA2CODEC_2X, TEGRA30_CLK_PLL_P, 48000000, 0 },
 	/* must be the last entry */
 	{ TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 },
 };

drivers/cpufreq/intel_pstate.c+3−13

 	return ret;
 }
-static inline int32_t percent_fp(int percent)
-{
-	return div_fp(percent, 100);
-}
 static inline u64 mul_ext_fp(u64 x, u64 y)
 {
 	return (x * y) >> EXT_FRAC_BITS;
 	return div64_u64(x << EXT_FRAC_BITS, y);
 }
-static inline int32_t percent_ext_fp(int percent)
-{
-	return div_ext_fp(percent, 100);
-}
 /**
  * struct sample -	Store performance sample
  * @core_avg_perf:	Ratio of APERF/MPERF which is the actual average
 				      unsigned long capacity)
 {
 	struct cpudata *cpu = all_cpu_data[cpunum];
+	u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached);
 	int old_pstate = cpu->pstate.current_pstate;
 	int cap_pstate, min_pstate, max_pstate, target_pstate;
 	update_turbo_state();
-	cap_pstate = global.turbo_disabled ? cpu->pstate.max_pstate :
+	cap_pstate = global.turbo_disabled ? HWP_GUARANTEED_PERF(hwp_cap) :
-					     cpu->pstate.turbo_pstate;
+					     HWP_HIGHEST_PERF(hwp_cap);
 	/* Optimization: Avoid unnecessary divisions. */
 			intel_pstate.attr = hwp_cpufreq_attrs;
 			intel_cpufreq.attr = hwp_cpufreq_attrs;
 			intel_cpufreq.flags |= CPUFREQ_NEED_UPDATE_LIMITS;
-			intel_cpufreq.fast_switch = NULL;
 			intel_cpufreq.adjust_perf = intel_cpufreq_adjust_perf;
 			if (!default_driver)
 				default_driver = &intel_pstate;

drivers/cpufreq/powernow-k8.c+3−6

 /* Take a frequency, and issue the fid/vid transition command */
 static int transition_frequency_fidvid(struct powernow_k8_data *data,
-		unsigned int index)
+		unsigned int index,
+		struct cpufreq_policy *policy)
 {
-	struct cpufreq_policy *policy;
 	u32 fid = 0;
 	u32 vid = 0;
 	int res;
 	freqs.old = find_khz_freq_from_fid(data->currfid);
 	freqs.new = find_khz_freq_from_fid(fid);
-	policy = cpufreq_cpu_get(smp_processor_id());
-	cpufreq_cpu_put(policy);
 	cpufreq_freq_transition_begin(policy, &freqs);
 	res = transition_fid_vid(data, fid, vid);
 	cpufreq_freq_transition_end(policy, &freqs, res);
 	powernow_k8_acpi_pst_values(data, newstate);
-	ret = transition_frequency_fidvid(data, newstate);
+	ret = transition_frequency_fidvid(data, newstate, pol);
 	if (ret) {
 		pr_err("transition frequency failed\n");

drivers/crypto/Kconfig+1−0

@@ -366,6 +366,7 @@ if CRYPTO_DEV_OMAP · 365 unmodified lines
366	config CRYPTO_DEV_OMAP_SHAM	366	config CRYPTO_DEV_OMAP_SHAM
367	tristate "Support for OMAP MD5/SHA1/SHA2 hw accelerator"	367	tristate "Support for OMAP MD5/SHA1/SHA2 hw accelerator"
368	depends on ARCH_OMAP2PLUS	368	depends on ARCH_OMAP2PLUS
		369	select CRYPTO_ENGINE
369	select CRYPTO_SHA1	370	select CRYPTO_SHA1
370	select CRYPTO_MD5	371	select CRYPTO_MD5
371	select CRYPTO_SHA256	372	select CRYPTO_SHA256

drivers/dma-buf/dma-buf.c+17−4

 	dmabuf->ops->release(dmabuf);
-	mutex_lock(&db_list.lock);
-	list_del(&dmabuf->list_node);
-	mutex_unlock(&db_list.lock);
 	if (dmabuf->resv == (struct dma_resv *)&dmabuf[1])
 		dma_resv_fini(dmabuf->resv);
 	kfree(dmabuf);
 }
+static int dma_buf_file_release(struct inode *inode, struct file *file)
+{
+	struct dma_buf *dmabuf;
+	if (!is_dma_buf_file(file))
+		return -EINVAL;
+	dmabuf = file->private_data;
+	mutex_lock(&db_list.lock);
+	list_del(&dmabuf->list_node);
+	mutex_unlock(&db_list.lock);
+	return 0;
+}
 static const struct dentry_operations dma_buf_dentry_ops = {
 	.d_dname = dmabuffs_dname,
 	.d_release = dma_buf_release,
 }
 static const struct file_operations dma_buf_fops = {
+	.release	= dma_buf_file_release,
 	.mmap		= dma_buf_mmap_internal,
 	.llseek		= dma_buf_llseek,
 	.poll		= dma_buf_poll,

drivers/dma-buf/heaps/cma_heap.c+3−0

 		buffer->vaddr = NULL;
 	}
+	/* free page list */
+	kfree(buffer->pages);
+	/* release memory */
 	cma_release(cma_heap->cma, buffer->cma_pages, buffer->pagecount);
 	kfree(buffer);
 }

drivers/dma/dw-edma/dw-edma-core.c+2−2

 	if (desc->chunk) {
 		/* Create and add new element into the linked list */
-		desc->chunks_alloc++;
-		list_add_tail(&chunk->list, &desc->chunk->list);
 		if (!dw_edma_alloc_burst(chunk)) {
 			kfree(chunk);
 			return NULL;
 		}
+		desc->chunks_alloc++;
+		list_add_tail(&chunk->list, &desc->chunk->list);
 	} else {
 		/* List head */
 		chunk->burst = NULL;

drivers/dma/idxd/sysfs.c+2−2

@@ -434,7 +434,7 @@ int idxd_register_driver(void) · 433 unmodified lines
434	return 0;	434	return 0;
435		435
436	drv_fail:	436	drv_fail:
437	for (; i > 0; i--)	437	while (--i >= 0)
438	driver_unregister(&idxd_drvs[i]->drv);	438	driver_unregister(&idxd_drvs[i]->drv);
439	return rc;	439	return rc;
440	}	440	}
@@ -1840,7 +1840,7 @@ int idxd_register_bus_type(void) · 1399 unmodified lines
1840	return 0;	1840	return 0;
1841		1841
1842	bus_err:	1842	bus_err:
1843	for (; i > 0; i--)	1843	while (--i >= 0)
1844	bus_unregister(idxd_bus_types[i]);	1844	bus_unregister(idxd_bus_types[i]);
1845	return rc;	1845	return rc;
1846	}	1846	}

drivers/dma/mediatek/mtk-hsdma.c+1−0

@@ -1007,6 +1007,7 @@ static int mtk_hsdma_probe(struct platform_device *pdev) · 1006 unmodified lines
1007	return 0;	1007	return 0;
1008		1008
1009	err_free:	1009	err_free:
		1010	mtk_hsdma_hw_deinit(hsdma);
1010	of_dma_controller_free(pdev->dev.of_node);	1011	of_dma_controller_free(pdev->dev.of_node);
1011	err_unregister:	1012	err_unregister:
1012	dma_async_device_unregister(dd);	1013	dma_async_device_unregister(dd);

drivers/dma/milbeaut-xdmac.c+3−1

 	ret = dma_async_device_register(ddev);
 	if (ret)
-		return ret;
+		goto disable_xdmac;
 	ret = of_dma_controller_register(dev->of_node,
 					 of_dma_simple_xlate, mdev);
 unregister_dmac:
 	dma_async_device_unregister(ddev);
+disable_xdmac:
+	disable_xdmac(mdev);
 	return ret;
 }

drivers/dma/qcom/bam_dma.c+1−5

 			     GFP_NOWAIT);
 	if (!async_desc)
-		goto err_out;
+		return NULL;
 	if (flags & DMA_PREP_FENCE)
 		async_desc->flags |= DESC_FLAG_NWD;
 	}
 	return vchan_tx_prep(&bchan->vc, &async_desc->vd, flags);
-err_out:
-	kfree(async_desc);
-	return NULL;
 }
 /**

drivers/dma/qcom/gpi.c+5−5

@@ -1416,7 +1416,7 @@ static int gpi_alloc_ring(struct gpi_ring *ring, u32 elements, · 1415 unmodified lines
1416	len = 1 << bit;	1416	len = 1 << bit;
1417	ring->alloc_size = (len + (len - 1));	1417	ring->alloc_size = (len + (len - 1));
1418	dev_dbg(gpii->gpi_dev->dev,	1418	dev_dbg(gpii->gpi_dev->dev,
1419	"#el:%u el_size:%u len:%u actual_len:%llu alloc_size:%lu\n",	1419	"#el:%u el_size:%u len:%u actual_len:%llu alloc_size:%zu\n",
1420	elements, el_size, (elements * el_size), len,	1420	elements, el_size, (elements * el_size), len,
1421	ring->alloc_size);	1421	ring->alloc_size);
1422		1422
@@ -1424,7 +1424,7 @@ static int gpi_alloc_ring(struct gpi_ring *ring, u32 elements, · 1 unmodified line
1424	ring->alloc_size,	1424	ring->alloc_size,
1425	&ring->dma_handle, GFP_KERNEL);	1425	&ring->dma_handle, GFP_KERNEL);
1426	if (!ring->pre_aligned) {	1426	if (!ring->pre_aligned) {
1427	dev_err(gpii->gpi_dev->dev, "could not alloc size:%lu mem for ring\n",	1427	dev_err(gpii->gpi_dev->dev, "could not alloc size:%zu mem for ring\n",
1428	ring->alloc_size);	1428	ring->alloc_size);
1429	return -ENOMEM;	1429	return -ENOMEM;
1430	}	1430	}
@@ -1444,8 +1444,8 @@ static int gpi_alloc_ring(struct gpi_ring *ring, u32 elements, · 13 unmodified lines
1444	smp_wmb();	1444	smp_wmb();
1445		1445
1446	dev_dbg(gpii->gpi_dev->dev,	1446	dev_dbg(gpii->gpi_dev->dev,
1447	"phy_pre:0x%0llx phy_alig:0x%0llx len:%u el_size:%u elements:%u\n",	1447	"phy_pre:%pad phy_alig:%pa len:%u el_size:%u elements:%u\n",
1448	ring->dma_handle, ring->phys_addr, ring->len,	1448	&ring->dma_handle, &ring->phys_addr, ring->len,
1449	ring->el_size, ring->elements);	1449	ring->el_size, ring->elements);
1450		1450
1451	return 0;	1451	return 0;
@@ -1948,7 +1948,7 @@ static int gpi_ch_init(struct gchan *gchan) · 496 unmodified lines
1948	return ret;	1948	return ret;
1949		1949
1950	error_start_chan:	1950	error_start_chan:
1951	for (i = i - 1; i >= 0; i++) {	1951	for (i = i - 1; i >= 0; i--) {
1952	gpi_stop_chan(&gpii->gchan[i]);	1952	gpi_stop_chan(&gpii->gchan[i]);
1953	gpi_send_cmd(gpii, gchan, GPI_CH_CMD_RESET);	1953	gpi_send_cmd(gpii, gchan, GPI_CH_CMD_RESET);
1954	}	1954	}

drivers/dma/stm32-mdma.c+1−1

@@ -199,7 +199,7 @@ · 198 unmodified lines
199	#define STM32_MDMA_MAX_CHANNELS 63	199	#define STM32_MDMA_MAX_CHANNELS 63
200	#define STM32_MDMA_MAX_REQUESTS 256	200	#define STM32_MDMA_MAX_REQUESTS 256
201	#define STM32_MDMA_MAX_BURST 128	201	#define STM32_MDMA_MAX_BURST 128
202	#define STM32_MDMA_VERY_HIGH_PRIORITY 0x11	202	#define STM32_MDMA_VERY_HIGH_PRIORITY 0x3
203		203
204	enum stm32_mdma_trigger_mode {	204	enum stm32_mdma_trigger_mode {
205	STM32_MDMA_BUFFER,	205	STM32_MDMA_BUFFER,

drivers/dma/ti/k3-udma.c+3−3

@@ -4698,9 +4698,9 @@ static int pktdma_setup_resources(struct udma_dev *ud) · 4697 unmodified lines
4698	ud->tchan_tpl.levels = 1;	4698	ud->tchan_tpl.levels = 1;
4699	}	4699	}
4700		4700
4701	ud->tchan_tpl.levels = ud->tchan_tpl.levels;	4701	ud->rchan_tpl.levels = ud->tchan_tpl.levels;
4702	ud->tchan_tpl.start_idx[0] = ud->tchan_tpl.start_idx[0];	4702	ud->rchan_tpl.start_idx[0] = ud->tchan_tpl.start_idx[0];
4703	ud->tchan_tpl.start_idx[1] = ud->tchan_tpl.start_idx[1];	4703	ud->rchan_tpl.start_idx[1] = ud->tchan_tpl.start_idx[1];
4704		4704
4705	ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt),	4705	ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt),
4706	sizeof(unsigned long), GFP_KERNEL);	4706	sizeof(unsigned long), GFP_KERNEL);

drivers/dma/xilinx/xilinx_dma.c+8−3

 		has_dre = false;
 	if (!has_dre)
-		xdev->common.copy_align = fls(width - 1);
+		xdev->common.copy_align = (enum dmaengine_alignment)fls(width - 1);
 	if (of_device_is_compatible(node, "xlnx,axi-vdma-mm2s-channel") ||
 	    of_device_is_compatible(node, "xlnx,axi-dma-mm2s-channel") ||
 static int xilinx_dma_child_probe(struct xilinx_dma_device *xdev,
 				    struct device_node *node)
 {
-	int ret, i, nr_channels = 1;
+	int ret, i;
+	u32 nr_channels = 1;
 	ret = of_property_read_u32(node, "dma-channels", &nr_channels);
 	if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA && ret < 0)
 	}
 	/* Register the DMA engine with the core */
-	dma_async_device_register(&xdev->common);
+	err = dma_async_device_register(&xdev->common);
+	if (err) {
+		dev_err(xdev->dev, "failed to register the dma device\n");
+		goto error;
+	}
 	err = of_dma_controller_register(node, of_dma_xilinx_xlate,
 					 xdev);

drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c+36−17

 union igp_info {
 	struct atom_integrated_system_info_v1_11 v11;
 	struct atom_integrated_system_info_v1_12 v12;
+	struct atom_integrated_system_info_v2_1 v21;
 };
 union umc_info {
 		if (adev->flags & AMD_IS_APU) {
 			igp_info = (union igp_info *)
 				(mode_info->atom_context->bios + data_offset);
-			switch (crev) {
+			switch (frev) {
-			case 11:
+			case 1:
-				mem_channel_number = igp_info->v11.umachannelnumber;
+				switch (crev) {
-				/* channel width is 64 */
+				case 11:
-				if (vram_width)
+				case 12:
-					*vram_width = mem_channel_number * 64;
+					mem_channel_number = igp_info->v11.umachannelnumber;
-				mem_type = igp_info->v11.memorytype;
+					if (!mem_channel_number)
-				if (vram_type)
+						mem_channel_number = 1;
-					*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
+					/* channel width is 64 */
+					if (vram_width)
+						*vram_width = mem_channel_number * 64;
+					mem_type = igp_info->v11.memorytype;
+					if (vram_type)
+						*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
+					break;
+				default:
+					return -EINVAL;
+				}
 				break;
-			case 12:
+			case 2:
-				mem_channel_number = igp_info->v12.umachannelnumber;
+				switch (crev) {
-				/* channel width is 64 */
+				case 1:
-				if (vram_width)
+				case 2:
-					*vram_width = mem_channel_number * 64;
+					mem_channel_number = igp_info->v21.umachannelnumber;
-				mem_type = igp_info->v12.memorytype;
+					if (!mem_channel_number)
-				if (vram_type)
+						mem_channel_number = 1;
-					*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
+					/* channel width is 64 */
+					if (vram_width)
+						*vram_width = mem_channel_number * 64;
+					mem_type = igp_info->v21.memorytype;
+					if (vram_type)
+						*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
+					break;
+				default:
+					return -EINVAL;
+				}
 				break;
 			default:
 				return -EINVAL;

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c+3−3

 	if (adev->gmc.xgmi.num_physical_nodes > 1)
 		amdgpu_xgmi_remove_device(adev);
-	amdgpu_amdkfd_device_fini(adev);
 	amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
 	amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
+	amdgpu_amdkfd_device_fini(adev);
 	/* need to disable SMC first */
 	for (i = 0; i < adev->num_ip_blocks; i++) {
 		if (!adev->ip_blocks[i].status.hw)
 #endif
 	default:
 		if (amdgpu_dc > 0)
-			DRM_INFO("Display Core has been requested via kernel parameter "
+			DRM_INFO_ONCE("Display Core has been requested via kernel parameter "
 					 "but isn't supported by ASIC, ignoring\n");
 		return false;
 	}

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c+2−0

@@ -1085,6 +1085,8 @@ static const struct pci_device_id pciidlist[] = { · 1084 unmodified lines
1085		1085
1086	/* Renoir */	1086	/* Renoir */
1087	{0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR\|AMD_IS_APU},	1087	{0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR\|AMD_IS_APU},
		1088	{0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR\|AMD_IS_APU},
		1089	{0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR\|AMD_IS_APU},
1088		1090
1089	/* Navi12 */	1091	/* Navi12 */
1090	{0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},	1092	{0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c+17−8

 	 * add workaround to bypass it for sriov now.
 	 * TODO: add version check to make it common
 	 */
-	if (amdgpu_sriov_vf(psp->adev) || !psp->asd_fw)
+	if (amdgpu_sriov_vf(psp->adev) || !psp->asd_ucode_size)
 		return 0;
 	cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 	if (amdgpu_sriov_vf(psp->adev))
 		return 0;
-	if (!psp->hdcp_context.hdcp_initialized)
+	if (!psp->hdcp_context.hdcp_initialized) {
-		return 0;
+		if (psp->hdcp_context.hdcp_shared_buf)
+			goto out;
+		else
+			return 0;
+	}
 	ret = psp_hdcp_unload(psp);
 	if (ret)
 	psp->hdcp_context.hdcp_initialized = false;
+out:
 	/* free hdcp shared memory */
 	amdgpu_bo_free_kernel(&psp->hdcp_context.hdcp_shared_bo,
 			      &psp->hdcp_context.hdcp_shared_mc_addr,
 	if (amdgpu_sriov_vf(psp->adev))
 		return 0;
-	if (!psp->dtm_context.dtm_initialized)
+	if (!psp->dtm_context.dtm_initialized) {
-		return 0;
+		if (psp->dtm_context.dtm_shared_buf)
+			goto out;
+		else
+			return 0;
+	}
 	ret = psp_dtm_unload(psp);
 	if (ret)
 	psp->dtm_context.dtm_initialized = false;
+out:
 	/* free hdcp shared memory */
 	amdgpu_bo_free_kernel(&psp->dtm_context.dtm_shared_bo,
 			      &psp->dtm_context.dtm_shared_mc_addr,
 	switch (desc->fw_type) {
 	case TA_FW_TYPE_PSP_ASD:
-		psp->asd_fw_version	   = le32_to_cpu(desc->fw_version);
+		psp->asd_fw_version        = le32_to_cpu(desc->fw_version);
 		psp->asd_feature_version   = le32_to_cpu(desc->fw_version);
-		psp->asd_ucode_size	   = le32_to_cpu(desc->size_bytes);
+		psp->asd_ucode_size        = le32_to_cpu(desc->size_bytes);
 		psp->asd_start_addr 	   = ucode_start_addr;
-		psp->asd_fw                = psp->ta_fw;
 		break;
 	case TA_FW_TYPE_PSP_XGMI:
 		psp->ta_xgmi_ucode_version = le32_to_cpu(desc->fw_version);

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c+4−4

@@ -1518,7 +1518,7 @@ static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, · 1517 unmodified lines
1518	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);	1518	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1519	struct ras_err_handler_data *data;	1519	struct ras_err_handler_data *data;
1520	int i = 0;	1520	int i = 0;
1521	int ret = 0;	1521	int ret = 0, status;
1522		1522
1523	if (!con \|\| !con->eh_data \|\| !bps \|\| !count)	1523	if (!con \|\| !con->eh_data \|\| !bps \|\| !count)
1524	return -EINVAL;	1524	return -EINVAL;
@@ -1543,12 +1543,12 @@ static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, · 18 unmodified lines
1543	.size = AMDGPU_GPU_PAGE_SIZE,	1543	.size = AMDGPU_GPU_PAGE_SIZE,
1544	.flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED,	1544	.flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED,
1545	};	1545	};
1546	ret = amdgpu_vram_mgr_query_page_status(	1546	status = amdgpu_vram_mgr_query_page_status(
1547	ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM),	1547	ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM),
1548	data->bps[i].retired_page);	1548	data->bps[i].retired_page);
1549	if (ret == -EBUSY)	1549	if (status == -EBUSY)
1550	(*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING;	1550	(*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING;
1551	else if (ret == -ENOENT)	1551	else if (status == -ENOENT)
1552	(*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT;	1552	(*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT;
1553	}	1553	}
1554		1554

drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c+7−1

 #define EEPROM_I2C_TARGET_ADDR_VEGA20		0xA0
 #define EEPROM_I2C_TARGET_ADDR_ARCTURUS		0xA8
 #define EEPROM_I2C_TARGET_ADDR_ARCTURUS_D342	0xA0
+#define EEPROM_I2C_TARGET_ADDR_SIENNA_CICHLID   0xA0
 /*
  * The 2 macros bellow represent the actual size in bytes that
 static bool __is_ras_eeprom_supported(struct amdgpu_device *adev)
 {
 	if ((adev->asic_type == CHIP_VEGA20) ||
-	    (adev->asic_type == CHIP_ARCTURUS))
+	    (adev->asic_type == CHIP_ARCTURUS) ||
+	    (adev->asic_type == CHIP_SIENNA_CICHLID))
 		return true;
 	return false;
 	case CHIP_ARCTURUS:
 		return __get_eeprom_i2c_addr_arct(adev, i2c_addr);
+	case CHIP_SIENNA_CICHLID:
+		*i2c_addr = EEPROM_I2C_TARGET_ADDR_SIENNA_CICHLID;
+		break;
 	default:
 		return false;
 	}

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c+46−2

@@ -99,6 +99,10 @@ · 98 unmodified lines
99	#define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580	99	#define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580
100	#define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0	100	#define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0
101		101
		102	#define mmGOLDEN_TSC_COUNT_UPPER_Vangogh 0x0025
		103	#define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX 1
		104	#define mmGOLDEN_TSC_COUNT_LOWER_Vangogh 0x0026
		105	#define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX 1
102	#define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441	106	#define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441
103	#define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1	107	#define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1
104	#define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261	108	#define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261
@@ -160,6 +164,9 @@ · 55 unmodified lines
160	#define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid 0x15db	164	#define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid 0x15db
161	#define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0	165	#define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
162		166
		167	#define mmGC_THROTTLE_CTRL_Sienna_Cichlid 0x2030
		168	#define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX 0
		169
163	MODULE_FIRMWARE("amdgpu/navi10_ce.bin");	170	MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
164	MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");	171	MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
165	MODULE_FIRMWARE("amdgpu/navi10_me.bin");	172	MODULE_FIRMWARE("amdgpu/navi10_me.bin");
@@ -3324,6 +3331,7 @@ static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); · 3158 unmodified lines
3324	static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);	3331	static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3325	static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);	3332	static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);
3326	static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);	3333	static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);
		3334	static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev);
3327		3335
3328	static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)	3336	static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3329	{	3337	{
@@ -7192,6 +7200,9 @@ static int gfx_v10_0_hw_init(void *handle) · 3862 unmodified lines
7192	if (adev->asic_type == CHIP_SIENNA_CICHLID)	7200	if (adev->asic_type == CHIP_SIENNA_CICHLID)
7193	gfx_v10_3_program_pbb_mode(adev);	7201	gfx_v10_3_program_pbb_mode(adev);
7194		7202
		7203	if (adev->asic_type >= CHIP_SIENNA_CICHLID)
		7204	gfx_v10_3_set_power_brake_sequence(adev);
		7205
7195	return r;	7206	return r;
7196	}	7207	}
7197		7208
@@ -7377,8 +7388,16 @@ static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev) · 179 unmodified lines
7377		7388
7378	amdgpu_gfx_off_ctrl(adev, false);	7389	amdgpu_gfx_off_ctrl(adev, false);
7379	mutex_lock(&adev->gfx.gpu_clock_mutex);	7390	mutex_lock(&adev->gfx.gpu_clock_mutex);
7380	clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) \|	7391	switch (adev->asic_type) {
7381	((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL);	7392	case CHIP_VANGOGH:
		7393	clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh) \|
		7394	((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh) << 32ULL);
		7395	break;
		7396	default:
		7397	clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) \|
		7398	((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL);
		7399	break;
		7400	}
7382	mutex_unlock(&adev->gfx.gpu_clock_mutex);	7401	mutex_unlock(&adev->gfx.gpu_clock_mutex);
7383	amdgpu_gfx_off_ctrl(adev, true);	7402	amdgpu_gfx_off_ctrl(adev, true);
7384	return clock;	7403	return clock;
@@ -9169,6 +9188,31 @@ static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev) · 1784 unmodified lines
9169	}	9188	}
9170	}	9189	}
9171		9190
		9191	static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev)
		9192	{
		9193	WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX,
		9194	(0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) \|
		9195	(0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) \|
		9196	(0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));
		9197
		9198	WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL);
		9199	WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA,
		9200	(0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) \|
		9201	(0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) \|
		9202	(0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) \|
		9203	(0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT));
		9204
		9205	WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid,
		9206	(0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) \|
		9207	(0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) \|
		9208	(0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT));
		9209
		9210	WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL);
		9211
		9212	WREG32_SOC15(GC, 0, mmDIDT_IND_DATA,
		9213	(0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT));
		9214	}
		9215
9172	const struct amdgpu_ip_block_version gfx_v10_0_ip_block =	9216	const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
9173	{	9217	{
9174	.type = AMD_IP_BLOCK_TYPE_GFX,	9218	.type = AMD_IP_BLOCK_TYPE_GFX,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c+1−1

@@ -310,7 +310,7 @@ static void mmhub_v2_3_setup_vmid_config(struct amdgpu_device *adev) · 309 unmodified lines
310	/* Send no-retry XNACK on fault to suppress VM fault storm. */	310	/* Send no-retry XNACK on fault to suppress VM fault storm. */
311	tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,	311	tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
312	RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,	312	RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
313	!amdgpu_noretry);	313	!adev->gmc.noretry);
314	WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL,	314	WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL,
315	i * hub->ctx_distance, tmp);	315	i * hub->ctx_distance, tmp);
316	WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,	316	WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,

drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h+1−1

@@ -47,7 +47,7 @@ enum psp_gfx_crtl_cmd_id · 46 unmodified lines
47	GFX_CTRL_CMD_ID_DISABLE_INT = 0x00060000, /* disable PSP-to-Gfx interrupt */	47	GFX_CTRL_CMD_ID_DISABLE_INT = 0x00060000, /* disable PSP-to-Gfx interrupt */
48	GFX_CTRL_CMD_ID_MODE1_RST = 0x00070000, /* trigger the Mode 1 reset */	48	GFX_CTRL_CMD_ID_MODE1_RST = 0x00070000, /* trigger the Mode 1 reset */
49	GFX_CTRL_CMD_ID_GBR_IH_SET = 0x00080000, /* set Gbr IH_RB_CNTL registers */	49	GFX_CTRL_CMD_ID_GBR_IH_SET = 0x00080000, /* set Gbr IH_RB_CNTL registers */
50	GFX_CTRL_CMD_ID_CONSUME_CMD = 0x000A0000, /* send interrupt to psp for updating write pointer of vf */	50	GFX_CTRL_CMD_ID_CONSUME_CMD = 0x00090000, /* send interrupt to psp for updating write pointer of vf */
51	GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING = 0x000C0000, /* destroy GPCOM ring */	51	GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING = 0x000C0000, /* destroy GPCOM ring */
52		52
53	GFX_CTRL_CMD_ID_MAX = 0x000F0000, /* max command ID */	53	GFX_CTRL_CMD_ID_MAX = 0x000F0000, /* max command ID */

drivers/gpu/drm/amd/amdgpu/soc15.c+2−1

 		break;
 	case CHIP_RENOIR:
 		adev->asic_funcs = &soc15_asic_funcs;
-		if (adev->pdev->device == 0x1636)
+		if ((adev->pdev->device == 0x1636) ||
+		    (adev->pdev->device == 0x164c))
 			adev->apu_flags |= AMD_APU_IS_RENOIR;
 		else
 			adev->apu_flags |= AMD_APU_IS_GREEN_SARDINE;

drivers/gpu/drm/amd/amdkfd/kfd_crat.c+7−4

 				(struct crat_subtype_iolink *)sub_type_hdr);
 		if (ret < 0)
 			return ret;
-		crat_table->length += (sub_type_hdr->length * entries);
-		crat_table->total_entries += entries;
-		sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
+		if (entries) {
-				sub_type_hdr->length * entries);
+			crat_table->length += (sub_type_hdr->length * entries);
+			crat_table->total_entries += entries;
+			sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
+					sub_type_hdr->length * entries);
+		}
 #else
 		pr_info("IO link not available for non x86 platforms\n");
 #endif

drivers/gpu/drm/amd/display/Kconfig+1−1

@@ -6,7 +6,7 @@ config DRM_AMD_DC · 5 unmodified lines
6	bool "AMD DC - Enable new display engine"	6	bool "AMD DC - Enable new display engine"
7	default y	7	default y
8	select SND_HDA_COMPONENT if SND_HDA_CORE	8	select SND_HDA_COMPONENT if SND_HDA_CORE
9	select DRM_AMD_DC_DCN if (X86 \|\| PPC64 \|\| (ARM64 && KERNEL_MODE_NEON)) && !(KCOV_INSTRUMENT_ALL && KCOV_ENABLE_COMPARISONS)	9	select DRM_AMD_DC_DCN if (X86 \|\| PPC64) && !(KCOV_INSTRUMENT_ALL && KCOV_ENABLE_COMPARISONS)
10	help	10	help
11	Choose this option if you want to use the new display engine	11	Choose this option if you want to use the new display engine
12	support for AMDGPU. This adds required support for Vega and	12	support for AMDGPU. This adds required support for Vega and

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c+9−136

@@ -939,41 +939,6 @@ static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_ · 938 unmodified lines
939	}	939	}
940	#endif	940	#endif
941		941
942	#ifdef CONFIG_DEBUG_FS
943	static int create_crtc_crc_properties(struct amdgpu_display_manager *dm)
944	{
945	dm->crc_win_x_start_property =
946	drm_property_create_range(adev_to_drm(dm->adev),
947	DRM_MODE_PROP_ATOMIC,
948	"AMD_CRC_WIN_X_START", 0, U16_MAX);
949	if (!dm->crc_win_x_start_property)
950	return -ENOMEM;
951
952	dm->crc_win_y_start_property =
953	drm_property_create_range(adev_to_drm(dm->adev),
954	DRM_MODE_PROP_ATOMIC,
955	"AMD_CRC_WIN_Y_START", 0, U16_MAX);
956	if (!dm->crc_win_y_start_property)
957	return -ENOMEM;
958
959	dm->crc_win_x_end_property =
960	drm_property_create_range(adev_to_drm(dm->adev),
961	DRM_MODE_PROP_ATOMIC,
962	"AMD_CRC_WIN_X_END", 0, U16_MAX);
963	if (!dm->crc_win_x_end_property)
964	return -ENOMEM;
965
966	dm->crc_win_y_end_property =
967	drm_property_create_range(adev_to_drm(dm->adev),
968	DRM_MODE_PROP_ATOMIC,
969	"AMD_CRC_WIN_Y_END", 0, U16_MAX);
970	if (!dm->crc_win_y_end_property)
971	return -ENOMEM;
972
973	return 0;
974	}
975	#endif
976
977	static int amdgpu_dm_init(struct amdgpu_device *adev)	942	static int amdgpu_dm_init(struct amdgpu_device *adev)
978	{	943	{
979	struct dc_init_data init_data;	944	struct dc_init_data init_data;
@@ -1120,10 +1085,6 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) · 140 unmodified lines
1120		1085
1121	dc_init_callbacks(adev->dm.dc, &init_params);	1086	dc_init_callbacks(adev->dm.dc, &init_params);
1122	}	1087	}
1123	#endif
1124	#ifdef CONFIG_DEBUG_FS
1125	if (create_crtc_crc_properties(&adev->dm))
1126	DRM_ERROR("amdgpu: failed to create crc property.\n");
1127	#endif	1088	#endif
1128	if (amdgpu_dm_initialize_drm_device(adev)) {	1089	if (amdgpu_dm_initialize_drm_device(adev)) {
1129	DRM_ERROR(	1090	DRM_ERROR(
@@ -2386,8 +2347,7 @@ void amdgpu_dm_update_connector_after_detect( · 1256 unmodified lines
2386		2347
2387	drm_connector_update_edid_property(connector,	2348	drm_connector_update_edid_property(connector,
2388	aconnector->edid);	2349	aconnector->edid);
2389	aconnector->num_modes = drm_add_edid_modes(connector, aconnector->edid);	2350	drm_add_edid_modes(connector, aconnector->edid);
2390	drm_connector_list_update(connector);
2391		2351
2392	if (aconnector->dc_link->aux_mode)	2352	if (aconnector->dc_link->aux_mode)
2393	drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,	2353	drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
@@ -5334,64 +5294,12 @@ dm_crtc_duplicate_state(struct drm_crtc *crtc) · 2940 unmodified lines
5334	state->crc_src = cur->crc_src;	5294	state->crc_src = cur->crc_src;
5335	state->cm_has_degamma = cur->cm_has_degamma;	5295	state->cm_has_degamma = cur->cm_has_degamma;
5336	state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;	5296	state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;
5337	#ifdef CONFIG_DEBUG_FS	5297
5338	state->crc_window = cur->crc_window;
5339	#endif
5340	/* TODO Duplicate dc_stream after objects are stream object is flattened */	5298	/* TODO Duplicate dc_stream after objects are stream object is flattened */
5341		5299
5342	return &state->base;	5300	return &state->base;
5343	}	5301	}
5344		5302
5345	#ifdef CONFIG_DEBUG_FS
5346	static int amdgpu_dm_crtc_atomic_set_property(struct drm_crtc *crtc,
5347	struct drm_crtc_state *crtc_state,
5348	struct drm_property *property,
5349	uint64_t val)
5350	{
5351	struct drm_device *dev = crtc->dev;
5352	struct amdgpu_device *adev = drm_to_adev(dev);
5353	struct dm_crtc_state *dm_new_state =
5354	to_dm_crtc_state(crtc_state);
5355
5356	if (property == adev->dm.crc_win_x_start_property)
5357	dm_new_state->crc_window.x_start = val;
5358	else if (property == adev->dm.crc_win_y_start_property)
5359	dm_new_state->crc_window.y_start = val;
5360	else if (property == adev->dm.crc_win_x_end_property)
5361	dm_new_state->crc_window.x_end = val;
5362	else if (property == adev->dm.crc_win_y_end_property)
5363	dm_new_state->crc_window.y_end = val;
5364	else
5365	return -EINVAL;
5366
5367	return 0;
5368	}
5369
5370	static int amdgpu_dm_crtc_atomic_get_property(struct drm_crtc *crtc,
5371	const struct drm_crtc_state *state,
5372	struct drm_property *property,
5373	uint64_t *val)
5374	{
5375	struct drm_device *dev = crtc->dev;
5376	struct amdgpu_device *adev = drm_to_adev(dev);
5377	struct dm_crtc_state *dm_state =
5378	to_dm_crtc_state(state);
5379
5380	if (property == adev->dm.crc_win_x_start_property)
5381	*val = dm_state->crc_window.x_start;
5382	else if (property == adev->dm.crc_win_y_start_property)
5383	*val = dm_state->crc_window.y_start;
5384	else if (property == adev->dm.crc_win_x_end_property)
5385	*val = dm_state->crc_window.x_end;
5386	else if (property == adev->dm.crc_win_y_end_property)
5387	*val = dm_state->crc_window.y_end;
5388	else
5389	return -EINVAL;
5390
5391	return 0;
5392	}
5393	#endif
5394
5395	static inline int dm_set_vupdate_irq(struct drm_crtc *crtc, bool enable)	5303	static inline int dm_set_vupdate_irq(struct drm_crtc *crtc, bool enable)
5396	{	5304	{
5397	enum dc_irq_source irq_source;	5305	enum dc_irq_source irq_source;
@@ -5458,10 +5366,6 @@ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { · 60 unmodified lines
5458	.enable_vblank = dm_enable_vblank,	5366	.enable_vblank = dm_enable_vblank,
5459	.disable_vblank = dm_disable_vblank,	5367	.disable_vblank = dm_disable_vblank,
5460	.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,	5368	.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
5461	#ifdef CONFIG_DEBUG_FS
5462	.atomic_set_property = amdgpu_dm_crtc_atomic_set_property,
5463	.atomic_get_property = amdgpu_dm_crtc_atomic_get_property,
5464	#endif
5465	};	5369	};
5466		5370
5467	static enum drm_connector_status	5371	static enum drm_connector_status
@@ -6663,25 +6567,6 @@ static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, · 1195 unmodified lines
6663	return 0;	6567	return 0;
6664	}	6568	}
6665		6569
6666	#ifdef CONFIG_DEBUG_FS
6667	static void attach_crtc_crc_properties(struct amdgpu_display_manager *dm,
6668	struct amdgpu_crtc *acrtc)
6669	{
6670	drm_object_attach_property(&acrtc->base.base,
6671	dm->crc_win_x_start_property,
6672	0);
6673	drm_object_attach_property(&acrtc->base.base,
6674	dm->crc_win_y_start_property,
6675	0);
6676	drm_object_attach_property(&acrtc->base.base,
6677	dm->crc_win_x_end_property,
6678	0);
6679	drm_object_attach_property(&acrtc->base.base,
6680	dm->crc_win_y_end_property,
6681	0);
6682	}
6683	#endif
6684
6685	static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,	6570	static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
6686	struct drm_plane *plane,	6571	struct drm_plane *plane,
6687	uint32_t crtc_index)	6572	uint32_t crtc_index)
@@ -6729,9 +6614,7 @@ static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, · 41 unmodified lines
6729	drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES,	6614	drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES,
6730	true, MAX_COLOR_LUT_ENTRIES);	6615	true, MAX_COLOR_LUT_ENTRIES);
6731	drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);	6616	drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
6732	#ifdef CONFIG_DEBUG_FS	6617
6733	attach_crtc_crc_properties(dm, acrtc);
6734	#endif
6735	return 0;	6618	return 0;
6736		6619
6737	fail:	6620	fail:
@@ -8368,7 +8251,6 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) · 1630 unmodified lines
8368	*/	8251	*/
8369	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {	8252	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8370	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);	8253	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8371	bool configure_crc = false;
8372		8254
8373	dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);	8255	dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8374		8256
@@ -8378,30 +8260,21 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) · 3 unmodified lines
8378	dc_stream_retain(dm_new_crtc_state->stream);	8260	dc_stream_retain(dm_new_crtc_state->stream);
8379	acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;	8261	acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
8380	manage_dm_interrupts(adev, acrtc, true);	8262	manage_dm_interrupts(adev, acrtc, true);
8381	}	8263
8382	#ifdef CONFIG_DEBUG_FS	8264	#ifdef CONFIG_DEBUG_FS
8383	if (new_crtc_state->active &&
8384	amdgpu_dm_is_valid_crc_source(dm_new_crtc_state->crc_src)) {
8385	/**	8265	/**
8386	* Frontend may have changed so reapply the CRC capture	8266	* Frontend may have changed so reapply the CRC capture
8387	* settings for the stream.	8267	* settings for the stream.
8388	*/	8268	*/
8389	dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);	8269	dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8390	dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8391
8392	if (amdgpu_dm_crc_window_is_default(dm_new_crtc_state)) {
8393	if (!old_crtc_state->active \|\| drm_atomic_crtc_needs_modeset(new_crtc_state))
8394	configure_crc = true;
8395	} else {
8396	if (amdgpu_dm_crc_window_changed(dm_new_crtc_state, dm_old_crtc_state))
8397	configure_crc = true;
8398	}
8399		8270
8400	if (configure_crc)	8271	if (amdgpu_dm_is_valid_crc_source(dm_new_crtc_state->crc_src)) {
8401	amdgpu_dm_crtc_configure_crc_source(	8272	amdgpu_dm_crtc_configure_crc_source(
8402	crtc, dm_new_crtc_state, dm_new_crtc_state->crc_src);	8273	crtc, dm_new_crtc_state,
8403	}	8274	dm_new_crtc_state->crc_src);
		8275	}
8404	#endif	8276	#endif
		8277	}
8405	}	8278	}
8406		8279
8407	for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)	8280	for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h+0−38

@@ -336,32 +336,6 @@ struct amdgpu_display_manager { · 335 unmodified lines
336	*/	336	*/
337	const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;	337	const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
338		338
339	#ifdef CONFIG_DEBUG_FS
340	/**
341	* @crc_win_x_start_property:
342	*
343	* X start of the crc calculation window
344	*/
345	struct drm_property *crc_win_x_start_property;
346	/**
347	* @crc_win_y_start_property:
348	*
349	* Y start of the crc calculation window
350	*/
351	struct drm_property *crc_win_y_start_property;
352	/**
353	* @crc_win_x_end_property:
354	*
355	* X end of the crc calculation window
356	*/
357	struct drm_property *crc_win_x_end_property;
358	/**
359	* @crc_win_y_end_property:
360	*
361	* Y end of the crc calculation window
362	*/
363	struct drm_property *crc_win_y_end_property;
364	#endif
365	/**	339	/**
366	* @mst_encoders:	340	* @mst_encoders:
367	*	341	*
@@ -448,15 +422,6 @@ struct dm_plane_state { · 80 unmodified lines
448	struct dc_plane_state *dc_state;	422	struct dc_plane_state *dc_state;
449	};	423	};
450		424
451	#ifdef CONFIG_DEBUG_FS
452	struct crc_rec {
453	uint16_t x_start;
454	uint16_t y_start;
455	uint16_t x_end;
456	uint16_t y_end;
457	};
458	#endif
459
460	struct dm_crtc_state {	425	struct dm_crtc_state {
461	struct drm_crtc_state base;	426	struct drm_crtc_state base;
462	struct dc_stream_state *stream;	427	struct dc_stream_state *stream;
@@ -479,9 +444,6 @@ struct dm_crtc_state { · 16 unmodified lines
479	struct dc_info_packet vrr_infopacket;	444	struct dc_info_packet vrr_infopacket;
480		445
481	int abm_level;	446	int abm_level;
482	#ifdef CONFIG_DEBUG_FS
483	struct crc_rec crc_window;
484	#endif
485	};	447	};
486		448
487	#define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base)	449	#define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c+1−53

@@ -81,41 +81,6 @@ const char const amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc, · 80 unmodified lines
81	return pipe_crc_sources;	81	return pipe_crc_sources;
82	}	82	}
83		83
84	static void amdgpu_dm_set_crc_window_default(struct dm_crtc_state *dm_crtc_state)
85	{
86	dm_crtc_state->crc_window.x_start = 0;
87	dm_crtc_state->crc_window.y_start = 0;
88	dm_crtc_state->crc_window.x_end = 0;
89	dm_crtc_state->crc_window.y_end = 0;
90	}
91
92	bool amdgpu_dm_crc_window_is_default(struct dm_crtc_state *dm_crtc_state)
93	{
94	bool ret = true;
95
96	if ((dm_crtc_state->crc_window.x_start != 0) \|\|
97	(dm_crtc_state->crc_window.y_start != 0) \|\|
98	(dm_crtc_state->crc_window.x_end != 0) \|\|
99	(dm_crtc_state->crc_window.y_end != 0))
100	ret = false;
101
102	return ret;
103	}
104
105	bool amdgpu_dm_crc_window_changed(struct dm_crtc_state *dm_new_crtc_state,
106	struct dm_crtc_state *dm_old_crtc_state)
107	{
108	bool ret = false;
109
110	if ((dm_new_crtc_state->crc_window.x_start != dm_old_crtc_state->crc_window.x_start) \|\|
111	(dm_new_crtc_state->crc_window.y_start != dm_old_crtc_state->crc_window.y_start) \|\|
112	(dm_new_crtc_state->crc_window.x_end != dm_old_crtc_state->crc_window.x_end) \|\|
113	(dm_new_crtc_state->crc_window.y_end != dm_old_crtc_state->crc_window.y_end))
114	ret = true;
115
116	return ret;
117	}
118
119	int	84	int
120	amdgpu_dm_crtc_verify_crc_source(struct drm_crtc crtc, const char src_name,	85	amdgpu_dm_crtc_verify_crc_source(struct drm_crtc crtc, const char src_name,
121	size_t *values_cnt)	86	size_t *values_cnt)
@@ -140,7 +105,6 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc, · 18 unmodified lines
140	struct dc_stream_state *stream_state = dm_crtc_state->stream;	105	struct dc_stream_state *stream_state = dm_crtc_state->stream;
141	bool enable = amdgpu_dm_is_valid_crc_source(source);	106	bool enable = amdgpu_dm_is_valid_crc_source(source);
142	int ret = 0;	107	int ret = 0;
143	struct crc_params *crc_window = NULL, tmp_window;
144		108
145	/* Configuration will be deferred to stream enable. */	109	/* Configuration will be deferred to stream enable. */
146	if (!stream_state)	110	if (!stream_state)
@@ -150,24 +114,8 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc, · 3 unmodified lines
150		114
151	/* Enable CRTC CRC generation if necessary. */	115	/* Enable CRTC CRC generation if necessary. */
152	if (dm_is_crc_source_crtc(source) \|\| source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE) {	116	if (dm_is_crc_source_crtc(source) \|\| source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE) {
153	if (!enable)
154	amdgpu_dm_set_crc_window_default(dm_crtc_state);
155
156	if (!amdgpu_dm_crc_window_is_default(dm_crtc_state)) {
157	crc_window = &tmp_window;
158
159	tmp_window.windowa_x_start = dm_crtc_state->crc_window.x_start;
160	tmp_window.windowa_y_start = dm_crtc_state->crc_window.y_start;
161	tmp_window.windowa_x_end = dm_crtc_state->crc_window.x_end;
162	tmp_window.windowa_y_end = dm_crtc_state->crc_window.y_end;
163	tmp_window.windowb_x_start = dm_crtc_state->crc_window.x_start;
164	tmp_window.windowb_y_start = dm_crtc_state->crc_window.y_start;
165	tmp_window.windowb_x_end = dm_crtc_state->crc_window.x_end;
166	tmp_window.windowb_y_end = dm_crtc_state->crc_window.y_end;
167	}
168
169	if (!dc_stream_configure_crc(stream_state->ctx->dc,	117	if (!dc_stream_configure_crc(stream_state->ctx->dc,
170	stream_state, crc_window, enable, enable)) {	118	stream_state, NULL, enable, enable)) {
171	ret = -EINVAL;	119	ret = -EINVAL;
172	goto unlock;	120	goto unlock;
173	}	121	}

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h+0−3

 /* amdgpu_dm_crc.c */
 #ifdef CONFIG_DEBUG_FS
-bool amdgpu_dm_crc_window_is_default(struct dm_crtc_state *dm_crtc_state);
-bool amdgpu_dm_crc_window_changed(struct dm_crtc_state *dm_new_crtc_state,
-					struct dm_crtc_state *dm_old_crtc_state);
 int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,
 					struct dm_crtc_state *dm_crtc_state,
 					enum amdgpu_dm_pipe_crc_source source);

drivers/gpu/drm/amd/display/dc/calcs/Makefile+0−4

 calcs_ccflags := -mhard-float -maltivec
 endif
-ifdef CONFIG_ARM64
-calcs_rcflags := -mgeneral-regs-only
-endif
 ifdef CONFIG_CC_IS_GCC
 ifeq ($(call cc-ifversion, -lt, 0701, y), y)
 IS_OLD_GCC = 1

drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile+0−21

@@ -104,13 +104,6 @@ ifdef CONFIG_PPC64 · 103 unmodified lines
104	CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn21/rn_clk_mgr.o := $(call cc-option,-mno-gnu-attribute)	104	CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn21/rn_clk_mgr.o := $(call cc-option,-mno-gnu-attribute)
105	endif	105	endif
106		106
107	# prevent build errors:
108	# ...: '-mgeneral-regs-only' is incompatible with the use of floating-point types
109	# this file is unused on arm64, just like on ppc64
110	ifdef CONFIG_ARM64
111	CFLAGS_REMOVE_$(AMDDALPATH)/dc/clk_mgr/dcn21/rn_clk_mgr.o := -mgeneral-regs-only
112	endif
113
114	AMD_DAL_CLK_MGR_DCN21 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn21/,$(CLK_MGR_DCN21))	107	AMD_DAL_CLK_MGR_DCN21 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn21/,$(CLK_MGR_DCN21))
115		108
116	AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN21)	109	AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN21)
@@ -125,13 +118,6 @@ ifdef CONFIG_PPC64 · 8 unmodified lines
125	CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn30/dcn30_clk_mgr.o := $(call cc-option,-mno-gnu-attribute)	118	CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn30/dcn30_clk_mgr.o := $(call cc-option,-mno-gnu-attribute)
126	endif	119	endif
127		120
128	# prevent build errors:
129	# ...: '-mgeneral-regs-only' is incompatible with the use of floating-point types
130	# this file is unused on arm64, just like on ppc64
131	ifdef CONFIG_ARM64
132	CFLAGS_REMOVE_$(AMDDALPATH)/dc/clk_mgr/dcn30/dcn30_clk_mgr.o := -mgeneral-regs-only
133	endif
134
135	AMD_DAL_CLK_MGR_DCN30 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn30/,$(CLK_MGR_DCN30))	121	AMD_DAL_CLK_MGR_DCN30 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn30/,$(CLK_MGR_DCN30))
136		122
137	AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN30)	123	AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN30)
@@ -146,13 +132,6 @@ ifdef CONFIG_PPC64 · 8 unmodified lines
146	CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn301/vg_clk_mgr.o := $(call cc-option,-mno-gnu-attribute)	132	CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn301/vg_clk_mgr.o := $(call cc-option,-mno-gnu-attribute)
147	endif	133	endif
148		134
149	# prevent build errors:
150	# ...: '-mgeneral-regs-only' is incompatible with the use of floating-point types
151	# this file is unused on arm64, just like on ppc64
152	ifdef CONFIG_ARM64
153	CFLAGS_REMOVE_$(AMDDALPATH)/dc/clk_mgr/dcn301/vg_clk_mgr.o := -mgeneral-regs-only
154	endif
155
156	AMD_DAL_CLK_MGR_DCN301 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn301/,$(CLK_MGR_DCN301))	135	AMD_DAL_CLK_MGR_DCN301 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn301/,$(CLK_MGR_DCN301))
157		136
158	AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN301)	137	AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN301)

drivers/gpu/drm/amd/display/dc/core/dc_link.c+6−1

 static struct abm *get_abm_from_stream_res(const struct dc_link *link)
 {
 	int i;
-	struct dc *dc = link->ctx->dc;
+	struct dc *dc = NULL;
 	struct abm *abm = NULL;
+	if (!link || !link->ctx)
+		return NULL;
+	dc = link->ctx->dc;
 	for (i = 0; i < MAX_PIPES; i++) {
 		struct pipe_ctx pipe_ctx = dc->current_state->res_ctx.pipe_ctx[i];
 		struct dc_stream_state *stream = pipe_ctx.stream;

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c+7−1

 	unsigned int cust_pattern_size)
 {
 	struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
-	struct pipe_ctx *pipe_ctx = &pipes[0];
+	struct pipe_ctx *pipe_ctx = NULL;
 	unsigned int lane;
 	unsigned int i;
 	unsigned char link_qual_pattern[LANE_COUNT_DP_MAX] = {0};
 	memset(&training_pattern, 0, sizeof(training_pattern));
 	for (i = 0; i < MAX_PIPES; i++) {
+		if (pipes[i].stream == NULL)
+			continue;
 		if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) {
 			pipe_ctx = &pipes[i];
 			break;
 		}
 	}
+	if (pipe_ctx == NULL)
+		return false;
 	/* Reset CRTC Test Pattern if it is currently running and request is VideoMode */
 	if (link->test_pattern_enabled && test_pattern ==
 			DP_TEST_PATTERN_VIDEO_MODE) {

drivers/gpu/drm/amd/display/dc/dcn10/Makefile+0−7

@@ -31,11 +31,4 @@ DCN10 = dcn10_init.o dcn10_resource.o dcn10_ipp.o dcn10_hw_sequencer.o \ · 30 unmodified lines
31		31
32	AMD_DAL_DCN10 = $(addprefix $(AMDDALPATH)/dc/dcn10/,$(DCN10))	32	AMD_DAL_DCN10 = $(addprefix $(AMDDALPATH)/dc/dcn10/,$(DCN10))
33		33
34	# fix:
35	# ...: '-mgeneral-regs-only' is incompatible with the use of floating-point types
36	# aarch64 does not support soft-float, so use hard-float and handle this in code
37	ifdef CONFIG_ARM64
38	CFLAGS_REMOVE_$(AMDDALPATH)/dc/dcn10/dcn10_resource.o := -mgeneral-regs-only
39	endif
40
41	AMD_DISPLAY_FILES += $(AMD_DAL_DCN10)	34	AMD_DISPLAY_FILES += $(AMD_DAL_DCN10)

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c+1−1

@@ -470,7 +470,7 @@ void mpc1_cursor_lock(struct mpc *mpc, int opp_id, bool lock) · 469 unmodified lines
470	unsigned int mpc1_get_mpc_out_mux(struct mpc *mpc, int opp_id)	470	unsigned int mpc1_get_mpc_out_mux(struct mpc *mpc, int opp_id)
471	{	471	{
472	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);	472	struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
473	uint32_t val = 0;	473	uint32_t val = 0xf;
474		474
475	if (opp_id < MAX_OPP && REG(MUX[opp_id]))	475	if (opp_id < MAX_OPP && REG(MUX[opp_id]))
476	REG_GET(MUX[opp_id], MPC_OUT_MUX, &val);	476	REG_GET(MUX[opp_id], MPC_OUT_MUX, &val);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c+2−9

 		.disable_pplib_clock_request = false,
 		.disable_pplib_wm_range = false,
 		.pplib_wm_report_mode = WM_REPORT_DEFAULT,
-		.pipe_split_policy = MPC_SPLIT_DYNAMIC,
+		.pipe_split_policy = MPC_SPLIT_AVOID,
-		.force_single_disp_pipe_split = true,
+		.force_single_disp_pipe_split = false,
 		.disable_dcc = DCC_ENABLE,
 		.voltage_align_fclk = true,
 		.disable_stereo_support = true,
 	memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults));
 	memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults));
-#if defined(CONFIG_ARM64)
-	/* Aarch64 does not support -msoft-float/-mfloat-abi=soft */
-	DC_FP_START();
-	dcn10_resource_construct_fp(dc);
-	DC_FP_END();
-#else
 	/* Other architectures we build for build this with soft-float */
 	dcn10_resource_construct_fp(dc);
-#endif
 	pool->base.pp_smu = dcn10_pp_smu_create(ctx);

drivers/gpu/drm/amd/display/dc/dcn20/Makefile+0−4

 CFLAGS_$(AMDDALPATH)/dc/dcn20/dcn20_resource.o := -mhard-float -maltivec
 endif
-ifdef CONFIG_ARM64
-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dcn20/dcn20_resource.o := -mgeneral-regs-only
-endif
 ifdef CONFIG_CC_IS_GCC
 ifeq ($(call cc-ifversion, -lt, 0701, y), y)
 IS_OLD_GCC = 1

drivers/gpu/drm/amd/display/dc/dcn21/Makefile+0−4

 CFLAGS_$(AMDDALPATH)/dc/dcn21/dcn21_resource.o := -mhard-float -maltivec
 endif
-ifdef CONFIG_ARM64
-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dcn21/dcn21_resource.o := -mgeneral-regs-only
-endif
 ifdef CONFIG_CC_IS_GCC
 ifeq ($(call cc-ifversion, -lt, 0701, y), y)
 IS_OLD_GCC = 1

drivers/gpu/drm/amd/display/dc/dcn30/Makefile+0−5

 CFLAGS_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o := -mhard-float -maltivec
 endif
-ifdef CONFIG_ARM64
-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dcn30/dcn30_resource.o := -mgeneral-regs-only
-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dcn30/dcn30_optc.o := -mgeneral-regs-only
-endif
 ifdef CONFIG_CC_IS_GCC
 ifeq ($(call cc-ifversion, -lt, 0701, y), y)
 IS_OLD_GCC = 1

drivers/gpu/drm/amd/display/dc/dcn301/Makefile+0−4

 CFLAGS_$(AMDDALPATH)/dc/dcn301/dcn301_resource.o := -mhard-float -maltivec
 endif
-ifdef CONFIG_ARM64
-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dcn301/dcn301_resource.o := -mgeneral-regs-only
-endif
 ifdef CONFIG_CC_IS_GCC
 ifeq ($(call cc-ifversion, -lt, 0701, y), y)
 IS_OLD_GCC = 1

drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c+1−0

@@ -1731,6 +1731,7 @@ static struct resource_funcs dcn301_res_pool_funcs = { · 1730 unmodified lines
1731	.populate_dml_pipes = dcn30_populate_dml_pipes_from_context,	1731	.populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
1732	.acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,	1732	.acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1733	.add_stream_to_ctx = dcn30_add_stream_to_ctx,	1733	.add_stream_to_ctx = dcn30_add_stream_to_ctx,
		1734	.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1734	.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,	1735	.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1735	.populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,	1736	.populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1736	.set_mcif_arb_params = dcn30_set_mcif_arb_params,	1737	.set_mcif_arb_params = dcn30_set_mcif_arb_params,

drivers/gpu/drm/amd/display/dc/dcn302/Makefile+0−4

 CFLAGS_$(AMDDALPATH)/dc/dcn302/dcn302_resource.o := -mhard-float -maltivec
 endif
-ifdef CONFIG_ARM64
-CFLAGS_REMOVE_$(AMDDALPATH)/dc/dcn302/dcn302_resource.o := -mgeneral-regs-only
-endif
 ifdef CONFIG_CC_IS_GCC
 ifeq ($(call cc-ifversion, -lt, 0701, y), y)
 IS_OLD_GCC = 1

drivers/gpu/drm/amd/display/dc/dml/Makefile+0−4

 dml_ccflags := -mhard-float -maltivec
 endif
-ifdef CONFIG_ARM64
-dml_rcflags := -mgeneral-regs-only
-endif
 ifdef CONFIG_CC_IS_GCC
 ifeq ($(call cc-ifversion, -lt, 0701, y), y)
 IS_OLD_GCC = 1

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c+6−5

 	}
 	if (mode_lib->vba.DRAMClockChangeSupportsVActive &&
-			mode_lib->vba.MinActiveDRAMClockChangeMargin > 60 &&
+			mode_lib->vba.MinActiveDRAMClockChangeMargin > 60) {
-			mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb] == 0) {
 		mode_lib->vba.DRAMClockChangeWatermark += 25;
 		for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-			if (mode_lib->vba.DRAMClockChangeWatermark >
+			if (mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb] == 0) {
-			dml_max(mode_lib->vba.StutterEnterPlusExitWatermark, mode_lib->vba.UrgentWatermark))
+				if (mode_lib->vba.DRAMClockChangeWatermark >
-				mode_lib->vba.MinTTUVBlank[k] += 25;
+				dml_max(mode_lib->vba.StutterEnterPlusExitWatermark, mode_lib->vba.UrgentWatermark))
+					mode_lib->vba.MinTTUVBlank[k] += 25;
+			}
 		}
 		mode_lib->vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive;

drivers/gpu/drm/amd/display/dc/dsc/Makefile+0−4

 dsc_ccflags := -mhard-float -maltivec
 endif
-ifdef CONFIG_ARM64
-dsc_rcflags := -mgeneral-regs-only
-endif
 ifdef CONFIG_CC_IS_GCC
 ifeq ($(call cc-ifversion, -lt, 0701, y), y)
 IS_OLD_GCC = 1

drivers/gpu/drm/amd/display/dc/os_types.h+0−4

 #include <asm/fpu/api.h>
 #define DC_FP_START() kernel_fpu_begin()
 #define DC_FP_END() kernel_fpu_end()
-#elif defined(CONFIG_ARM64)
-#include <asm/neon.h>
-#define DC_FP_START() kernel_neon_begin()
-#define DC_FP_END() kernel_neon_end()
 #elif defined(CONFIG_PPC64)
 #include <asm/switch_to.h>
 #include <asm/cputable.h>

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c+151−15

@@ -251,7 +251,7 @@ static int smu10_set_hard_min_gfxclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t cl · 250 unmodified lines
251	smu10_data->gfx_actual_soft_min_freq = clock;	251	smu10_data->gfx_actual_soft_min_freq = clock;
252	smum_send_msg_to_smc_with_parameter(hwmgr,	252	smum_send_msg_to_smc_with_parameter(hwmgr,
253	PPSMC_MSG_SetHardMinGfxClk,	253	PPSMC_MSG_SetHardMinGfxClk,
254	smu10_data->gfx_actual_soft_min_freq,	254	clock,
255	NULL);	255	NULL);
256	}	256	}
257	return 0;	257	return 0;
@@ -558,7 +558,8 @@ static int smu10_hwmgr_backend_init(struct pp_hwmgr *hwmgr) · 300 unmodified lines
558		558
559	/* enable the pp_od_clk_voltage sysfs file */	559	/* enable the pp_od_clk_voltage sysfs file */
560	hwmgr->od_enabled = 1;	560	hwmgr->od_enabled = 1;
561		561	/* disabled fine grain tuning function by default */
		562	data->fine_grain_enabled = 0;
562	return result;	563	return result;
563	}	564	}
564		565
@@ -597,6 +598,7 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, · 32 unmodified lines
597	uint32_t min_mclk = hwmgr->display_config->min_mem_set_clock/100;	598	uint32_t min_mclk = hwmgr->display_config->min_mem_set_clock/100;
598	uint32_t index_fclk = data->clock_vol_info.vdd_dep_on_fclk->count - 1;	599	uint32_t index_fclk = data->clock_vol_info.vdd_dep_on_fclk->count - 1;
599	uint32_t index_socclk = data->clock_vol_info.vdd_dep_on_socclk->count - 1;	600	uint32_t index_socclk = data->clock_vol_info.vdd_dep_on_socclk->count - 1;
		601	uint32_t fine_grain_min_freq = 0, fine_grain_max_freq = 0;
600		602
601	if (hwmgr->smu_version < 0x1E3700) {	603	if (hwmgr->smu_version < 0x1E3700) {
602	pr_info("smu firmware version too old, can not set dpm level\n");	604	pr_info("smu firmware version too old, can not set dpm level\n");
@@ -613,6 +615,14 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, · 10 unmodified lines
613	switch (level) {	615	switch (level) {
614	case AMD_DPM_FORCED_LEVEL_HIGH:	616	case AMD_DPM_FORCED_LEVEL_HIGH:
615	case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:	617	case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
		618	data->fine_grain_enabled = 0;
		619
		620	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq);
		621	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq);
		622
		623	data->gfx_actual_soft_min_freq = fine_grain_min_freq;
		624	data->gfx_actual_soft_max_freq = fine_grain_max_freq;
		625
616	smum_send_msg_to_smc_with_parameter(hwmgr,	626	smum_send_msg_to_smc_with_parameter(hwmgr,
617	PPSMC_MSG_SetHardMinGfxClk,	627	PPSMC_MSG_SetHardMinGfxClk,
618	data->gfx_max_freq_limit/100,	628	data->gfx_max_freq_limit/100,
@@ -648,6 +658,14 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, · 29 unmodified lines
648	NULL);	658	NULL);
649	break;	659	break;
650	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:	660	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
		661	data->fine_grain_enabled = 0;
		662
		663	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq);
		664	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq);
		665
		666	data->gfx_actual_soft_min_freq = fine_grain_min_freq;
		667	data->gfx_actual_soft_max_freq = fine_grain_max_freq;
		668
651	smum_send_msg_to_smc_with_parameter(hwmgr,	669	smum_send_msg_to_smc_with_parameter(hwmgr,
652	PPSMC_MSG_SetHardMinGfxClk,	670	PPSMC_MSG_SetHardMinGfxClk,
653	min_sclk,	671	min_sclk,
@@ -658,6 +676,14 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, · 4 unmodified lines
658	NULL);	676	NULL);
659	break;	677	break;
660	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:	678	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
		679	data->fine_grain_enabled = 0;
		680
		681	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq);
		682	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq);
		683
		684	data->gfx_actual_soft_min_freq = fine_grain_min_freq;
		685	data->gfx_actual_soft_max_freq = fine_grain_max_freq;
		686
661	smum_send_msg_to_smc_with_parameter(hwmgr,	687	smum_send_msg_to_smc_with_parameter(hwmgr,
662	PPSMC_MSG_SetHardMinFclkByFreq,	688	PPSMC_MSG_SetHardMinFclkByFreq,
663	min_mclk,	689	min_mclk,
@@ -668,6 +694,14 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, · 4 unmodified lines
668	NULL);	694	NULL);
669	break;	695	break;
670	case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:	696	case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
		697	data->fine_grain_enabled = 0;
		698
		699	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq);
		700	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq);
		701
		702	data->gfx_actual_soft_min_freq = fine_grain_min_freq;
		703	data->gfx_actual_soft_max_freq = fine_grain_max_freq;
		704
671	smum_send_msg_to_smc_with_parameter(hwmgr,	705	smum_send_msg_to_smc_with_parameter(hwmgr,
672	PPSMC_MSG_SetHardMinGfxClk,	706	PPSMC_MSG_SetHardMinGfxClk,
673	SMU10_UMD_PSTATE_GFXCLK,	707	SMU10_UMD_PSTATE_GFXCLK,
@@ -703,6 +737,14 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, · 29 unmodified lines
703	NULL);	737	NULL);
704	break;	738	break;
705	case AMD_DPM_FORCED_LEVEL_AUTO:	739	case AMD_DPM_FORCED_LEVEL_AUTO:
		740	data->fine_grain_enabled = 0;
		741
		742	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq);
		743	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq);
		744
		745	data->gfx_actual_soft_min_freq = fine_grain_min_freq;
		746	data->gfx_actual_soft_max_freq = fine_grain_max_freq;
		747
706	smum_send_msg_to_smc_with_parameter(hwmgr,	748	smum_send_msg_to_smc_with_parameter(hwmgr,
707	PPSMC_MSG_SetHardMinGfxClk,	749	PPSMC_MSG_SetHardMinGfxClk,
708	min_sclk,	750	min_sclk,
@@ -741,6 +783,14 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, · 32 unmodified lines
741	NULL);	783	NULL);
742	break;	784	break;
743	case AMD_DPM_FORCED_LEVEL_LOW:	785	case AMD_DPM_FORCED_LEVEL_LOW:
		786	data->fine_grain_enabled = 0;
		787
		788	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq);
		789	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq);
		790
		791	data->gfx_actual_soft_min_freq = fine_grain_min_freq;
		792	data->gfx_actual_soft_max_freq = fine_grain_max_freq;
		793
744	smum_send_msg_to_smc_with_parameter(hwmgr,	794	smum_send_msg_to_smc_with_parameter(hwmgr,
745	PPSMC_MSG_SetHardMinGfxClk,	795	PPSMC_MSG_SetHardMinGfxClk,
746	data->gfx_min_freq_limit/100,	796	data->gfx_min_freq_limit/100,
@@ -759,6 +809,7 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, · 12 unmodified lines
759	NULL);	809	NULL);
760	break;	810	break;
761	case AMD_DPM_FORCED_LEVEL_MANUAL:	811	case AMD_DPM_FORCED_LEVEL_MANUAL:
		812	data->fine_grain_enabled = 1;
762	case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:	813	case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
763	default:	814	default:
764	break;	815	break;
@@ -948,6 +999,8 @@ static int smu10_print_clock_levels(struct pp_hwmgr *hwmgr, · 183 unmodified lines
948	struct smu10_voltage_dependency_table *mclk_table =	999	struct smu10_voltage_dependency_table *mclk_table =
949	data->clock_vol_info.vdd_dep_on_fclk;	1000	data->clock_vol_info.vdd_dep_on_fclk;
950	uint32_t i, now, size = 0;	1001	uint32_t i, now, size = 0;
		1002	uint32_t min_freq, max_freq = 0;
		1003	uint32_t ret = 0;
951		1004
952	switch (type) {	1005	switch (type) {
953	case PP_SCLK:	1006	case PP_SCLK:
@@ -983,18 +1036,28 @@ static int smu10_print_clock_levels(struct pp_hwmgr *hwmgr, · 29 unmodified lines
983	break;	1036	break;
984	case OD_SCLK:	1037	case OD_SCLK:
985	if (hwmgr->od_enabled) {	1038	if (hwmgr->od_enabled) {
986	size = sprintf(buf, "%s:\n", "OD_SCLK");	1039	ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &min_freq);
		1040	if (ret)
		1041	return ret;
		1042	ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &max_freq);
		1043	if (ret)
		1044	return ret;
987		1045
		1046	size = sprintf(buf, "%s:\n", "OD_SCLK");
988	size += sprintf(buf + size, "0: %10uMhz\n",	1047	size += sprintf(buf + size, "0: %10uMhz\n",
989	(data->gfx_actual_soft_min_freq > 0) ? data->gfx_actual_soft_min_freq : data->gfx_min_freq_limit/100);	1048	(data->gfx_actual_soft_min_freq > 0) ? data->gfx_actual_soft_min_freq : min_freq);
990	size += sprintf(buf + size, "1: %10uMhz\n", data->gfx_max_freq_limit/100);	1049	size += sprintf(buf + size, "1: %10uMhz\n",
		1050	(data->gfx_actual_soft_max_freq > 0) ? data->gfx_actual_soft_max_freq : max_freq);
991	}	1051	}
992	break;	1052	break;
993	case OD_RANGE:	1053	case OD_RANGE:
994	if (hwmgr->od_enabled) {	1054	if (hwmgr->od_enabled) {
995	uint32_t min_freq, max_freq = 0;	1055	ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &min_freq);
996	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &min_freq);	1056	if (ret)
997	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &max_freq);	1057	return ret;
		1058	ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &max_freq);
		1059	if (ret)
		1060	return ret;
998		1061
999	size = sprintf(buf, "%s:\n", "OD_RANGE");	1062	size = sprintf(buf, "%s:\n", "OD_RANGE");
1000	size += sprintf(buf + size, "SCLK: %7uMHz %10uMHz\n",	1063	size += sprintf(buf + size, "SCLK: %7uMHz %10uMHz\n",
@@ -1414,23 +1477,96 @@ static int smu10_set_fine_grain_clk_vol(struct pp_hwmgr *hwmgr, · 413 unmodified lines
1414	enum PP_OD_DPM_TABLE_COMMAND type,	1477	enum PP_OD_DPM_TABLE_COMMAND type,
1415	long *input, uint32_t size)	1478	long *input, uint32_t size)
1416	{	1479	{
		1480	uint32_t min_freq, max_freq = 0;
		1481	struct smu10_hwmgr smu10_data = (struct smu10_hwmgr )(hwmgr->backend);
		1482	int ret = 0;
		1483
1417	if (!hwmgr->od_enabled) {	1484	if (!hwmgr->od_enabled) {
1418	pr_err("Fine grain not support\n");	1485	pr_err("Fine grain not support\n");
1419	return -EINVAL;	1486	return -EINVAL;
1420	}	1487	}
1421		1488
1422	if (size != 2) {	1489	if (!smu10_data->fine_grain_enabled) {
1423	pr_err("Input parameter number not correct\n");	1490	pr_err("Fine grain not started\n");
1424	return -EINVAL;	1491	return -EINVAL;
1425	}	1492	}
1426		1493
1427	if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) {	1494	if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) {
1428	if (input[0] == 0)	1495	if (size != 2) {
1429	smu10_set_hard_min_gfxclk_by_freq(hwmgr, input[1]);	1496	pr_err("Input parameter number not correct\n");
1430	else if (input[0] == 1)
1431	smu10_set_soft_max_gfxclk_by_freq(hwmgr, input[1]);
1432	else
1433	return -EINVAL;	1497	return -EINVAL;
		1498	}
		1499
		1500	if (input[0] == 0) {
		1501	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &min_freq);
		1502	if (input[1] < min_freq) {
		1503	pr_err("Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
		1504	input[1], min_freq);
		1505	return -EINVAL;
		1506	}
		1507	smu10_data->gfx_actual_soft_min_freq = input[1];
		1508	} else if (input[0] == 1) {
		1509	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &max_freq);
		1510	if (input[1] > max_freq) {
		1511	pr_err("Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
		1512	input[1], max_freq);
		1513	return -EINVAL;
		1514	}
		1515	smu10_data->gfx_actual_soft_max_freq = input[1];
		1516	} else {
		1517	return -EINVAL;
		1518	}
		1519	} else if (type == PP_OD_RESTORE_DEFAULT_TABLE) {
		1520	if (size != 0) {
		1521	pr_err("Input parameter number not correct\n");
		1522	return -EINVAL;
		1523	}
		1524	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &min_freq);
		1525	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &max_freq);
		1526
		1527	smu10_data->gfx_actual_soft_min_freq = min_freq;
		1528	smu10_data->gfx_actual_soft_max_freq = max_freq;
		1529
		1530	ret = smum_send_msg_to_smc_with_parameter(hwmgr,
		1531	PPSMC_MSG_SetHardMinGfxClk,
		1532	min_freq,
		1533	NULL);
		1534	if (ret)
		1535	return ret;
		1536
		1537	ret = smum_send_msg_to_smc_with_parameter(hwmgr,
		1538	PPSMC_MSG_SetSoftMaxGfxClk,
		1539	max_freq,
		1540	NULL);
		1541	if (ret)
		1542	return ret;
		1543	} else if (type == PP_OD_COMMIT_DPM_TABLE) {
		1544	if (size != 0) {
		1545	pr_err("Input parameter number not correct\n");
		1546	return -EINVAL;
		1547	}
		1548
		1549	if (smu10_data->gfx_actual_soft_min_freq > smu10_data->gfx_actual_soft_max_freq) {
		1550	pr_err("The setting minimun sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
		1551	smu10_data->gfx_actual_soft_min_freq, smu10_data->gfx_actual_soft_max_freq);
		1552	return -EINVAL;
		1553	}
		1554
		1555	ret = smum_send_msg_to_smc_with_parameter(hwmgr,
		1556	PPSMC_MSG_SetHardMinGfxClk,
		1557	smu10_data->gfx_actual_soft_min_freq,
		1558	NULL);
		1559	if (ret)
		1560	return ret;
		1561
		1562	ret = smum_send_msg_to_smc_with_parameter(hwmgr,
		1563	PPSMC_MSG_SetSoftMaxGfxClk,
		1564	smu10_data->gfx_actual_soft_max_freq,
		1565	NULL);
		1566	if (ret)
		1567	return ret;
		1568	} else {
		1569	return -EINVAL;
1434	}	1570	}
1435		1571
1436	return 0;	1572	return 0;

drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h+3−0

 	uint32_t                        vclk_soft_min;
 	uint32_t                        dclk_soft_min;
 	uint32_t                        gfx_actual_soft_min_freq;
+	uint32_t                        gfx_actual_soft_max_freq;
 	uint32_t                        gfx_min_freq_limit;
 	uint32_t                        gfx_max_freq_limit; /* in 10Khz*/
 	bool need_min_deep_sleep_dcefclk;
 	uint32_t                             deep_sleep_dcefclk;
 	uint32_t                             num_active_display;
+	bool							fine_grain_enabled;
 };
 struct pp_hwmgr;

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c+1−1

@@ -2372,7 +2372,7 @@ static void sienna_cichlid_fill_i2c_req(SwI2cRequest_t *req, bool write, · 2371 unmodified lines
2372	{	2372	{
2373	int i;	2373	int i;
2374		2374
2375	req->I2CcontrollerPort = 0;	2375	req->I2CcontrollerPort = 1;
2376	req->I2CSpeed = 2;	2376	req->I2CSpeed = 2;
2377	req->SlaveAddress = address;	2377	req->SlaveAddress = address;
2378	req->NumCmds = numbytes;	2378	req->NumCmds = numbytes;

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c+2−1

 		*value = metrics->UvdActivity;
 		break;
 	case METRICS_AVERAGE_SOCKETPOWER:
-		*value = metrics->CurrentSocketPower;
+		*value = (metrics->CurrentSocketPower << 8) /
+		1000 ;
 		break;
 	case METRICS_TEMPERATURE_EDGE:
 		*value = metrics->GfxTemperature / 100 *

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c+1−0

@@ -188,6 +188,7 @@ static int renoir_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type · 187 unmodified lines
188	return -EINVAL;	188	return -EINVAL;
189	*freq = clk_table->SocClocks[dpm_level].Freq;	189	*freq = clk_table->SocClocks[dpm_level].Freq;
190	break;	190	break;
		191	case SMU_UCLK:
191	case SMU_MCLK:	192	case SMU_MCLK:
192	if (dpm_level >= NUM_FCLK_DPM_LEVELS)	193	if (dpm_level >= NUM_FCLK_DPM_LEVELS)
193	return -EINVAL;	194	return -EINVAL;

drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c+1−0

@@ -225,6 +225,7 @@ int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_ · 224 unmodified lines
225	break;	225	break;
226	case SMU_FCLK:	226	case SMU_FCLK:
227	case SMU_MCLK:	227	case SMU_MCLK:
		228	case SMU_UCLK:
228	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinFclkByFreq, min, NULL);	229	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinFclkByFreq, min, NULL);
229	if (ret)	230	if (ret)
230	return ret;	231	return ret;

drivers/gpu/drm/drm_plane.c+8−1

 	if (ret)
 		goto out;
-	if (old_fb->format != fb->format) {
+	/*
+	 * Only check the FOURCC format code, excluding modifiers. This is
+	 * enough for all legacy drivers. Atomic drivers have their own
+	 * checks in their ->atomic_check implementation, which will
+	 * return -EINVAL if any hw or driver constraint is violated due
+	 * to modifier changes.
+	 */
+	if (old_fb->format->format != fb->format->format) {
 		DRM_DEBUG_KMS("Page flip is not allowed to change frame buffer format.\n");
 		ret = -EINVAL;
 		goto out;

drivers/gpu/drm/i915/Makefile+1−0

@@ -38,6 +38,7 @@ i915-y += i915_drv.o \ · 37 unmodified lines
38	i915_config.o \	38	i915_config.o \
39	i915_irq.o \	39	i915_irq.o \
40	i915_getparam.o \	40	i915_getparam.o \
		41	i915_mitigations.o \
41	i915_params.o \	42	i915_params.o \
42	i915_pci.o \	43	i915_pci.o \
43	i915_scatterlist.o \	44	i915_scatterlist.o \

drivers/gpu/drm/i915/display/icl_dsi.c+0−4

@@ -1616,10 +1616,6 @@ static void gen11_dsi_get_power_domains(struct intel_encoder *encoder, · 1615 unmodified lines
1616		1616
1617	get_dsi_io_power_domains(i915,	1617	get_dsi_io_power_domains(i915,
1618	enc_to_intel_dsi(encoder));	1618	enc_to_intel_dsi(encoder));
1619
1620	if (crtc_state->dsc.compression_enable)
1621	intel_display_power_get(i915,
1622	intel_dsc_power_domain(crtc_state));
1623	}	1619	}
1624		1620
1625	static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,	1621	static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,

drivers/gpu/drm/i915/display/intel_display_types.h+3−0

@@ -1436,6 +1436,9 @@ struct intel_dp { · 1435 unmodified lines
1436	bool ycbcr_444_to_420;	1436	bool ycbcr_444_to_420;
1437	} dfp;	1437	} dfp;
1438		1438
		1439	/* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
		1440	struct pm_qos_request pm_qos;
		1441
1439	/* Display stream compression testing */	1442	/* Display stream compression testing */
1440	bool force_dsc_en;	1443	bool force_dsc_en;
1441		1444

drivers/gpu/drm/i915/display/intel_dp.c+6−2

 	 * lowest possible wakeup latency and so prevent the cpu from going into
 	 * deep sleep states.
 	 */
-	cpu_latency_qos_update_request(&i915->pm_qos, 0);
+	cpu_latency_qos_update_request(&intel_dp->pm_qos, 0);
 	intel_dp_check_edp(intel_dp);
 	ret = recv_bytes;
 out:
-	cpu_latency_qos_update_request(&i915->pm_qos, PM_QOS_DEFAULT_VALUE);
+	cpu_latency_qos_update_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
 	if (vdd)
 		edp_panel_vdd_off(intel_dp, false);
 static void
 intel_dp_aux_fini(struct intel_dp *intel_dp)
 {
+	if (cpu_latency_qos_request_active(&intel_dp->pm_qos))
+		cpu_latency_qos_remove_request(&intel_dp->pm_qos);
 	kfree(intel_dp->aux.name);
 }
 					       encoder->base.name);
 	intel_dp->aux.transfer = intel_dp_aux_transfer;
+	cpu_latency_qos_add_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
 }
 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/display/intel_panel.c+5−4

 		val = pch_get_backlight(connector);
 	else
 		val = lpt_get_backlight(connector);
-	val = intel_panel_compute_brightness(connector, val);
-	panel->backlight.level = clamp(val, panel->backlight.min,
-				       panel->backlight.max);
 	if (cpu_mode) {
 		drm_dbg_kms(&dev_priv->drm,
 			    "CPU backlight register was enabled, switching to PCH override\n");
 		/* Write converted CPU PWM value to PCH override register */
-		lpt_set_backlight(connector->base.state, panel->backlight.level);
+		lpt_set_backlight(connector->base.state, val);
 		intel_de_write(dev_priv, BLC_PWM_PCH_CTL1,
 			       pch_ctl1 | BLM_PCH_OVERRIDE_ENABLE);
 			       cpu_ctl2 & ~BLM_PWM_ENABLE);
 	}
+	val = intel_panel_compute_brightness(connector, val);
+	panel->backlight.level = clamp(val, panel->backlight.min,
+				       panel->backlight.max);
 	return 0;
 }

drivers/gpu/drm/i915/display/vlv_dsi.c+13−3

@@ -812,10 +812,20 @@ static void intel_dsi_pre_enable(struct intel_atomic_state *state, · 811 unmodified lines
812	intel_dsi_prepare(encoder, pipe_config);	812	intel_dsi_prepare(encoder, pipe_config);
813		813
814	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);	814	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
815	intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay);
816		815
817	/* Deassert reset */	816	/*
818	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);	817	* Give the panel time to power-on and then deassert its reset.
		818	* Depending on the VBT MIPI sequences version the deassert-seq
		819	* may contain the necessary delay, intel_dsi_msleep() will skip
		820	* the delay in that case. If there is no deassert-seq, then an
		821	* unconditional msleep is used to give the panel time to power-on.
		822	*/
		823	if (dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET]) {
		824	intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay);
		825	intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
		826	} else {
		827	msleep(intel_dsi->panel_on_delay);
		828	}
819		829
820	if (IS_GEMINILAKE(dev_priv)) {	830	if (IS_GEMINILAKE(dev_priv)) {
821	glk_cold_boot = glk_dsi_enable_io(encoder);	831	glk_cold_boot = glk_dsi_enable_io(encoder);

drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c+3−1

 	GEM_BUG_ON(cache->rq_size >= obj->base.size / sizeof(u32));
 	cache->rq_cmd[cache->rq_size] = MI_BATCH_BUFFER_END;
-	__i915_gem_object_flush_map(obj, 0, sizeof(u32) * (cache->rq_size + 1));
+	i915_gem_object_flush_map(obj);
 	i915_gem_object_unpin_map(obj);
 	intel_gt_chipset_flush(cache->rq->engine->gt);
 		goto err_pool;
 	}
+	memset32(cmd, 0, pool->obj->base.size / sizeof(u32));
 	batch = i915_vma_instance(pool->obj, vma->vm, NULL);
 	if (IS_ERR(batch)) {
 		err = PTR_ERR(batch);

drivers/gpu/drm/i915/gt/gen7_renderclear.c+94−63

@@ -7,8 +7,6 @@ · 6 unmodified lines
7	#include "i915_drv.h"	7	#include "i915_drv.h"
8	#include "intel_gpu_commands.h"	8	#include "intel_gpu_commands.h"
9		9
10	#define MAX_URB_ENTRIES 64
11	#define STATE_SIZE (4 * 1024)
12	#define GT3_INLINE_DATA_DELAYS 0x1E00	10	#define GT3_INLINE_DATA_DELAYS 0x1E00
13	#define batch_advance(Y, CS) GEM_BUG_ON((Y)->end != (CS))	11	#define batch_advance(Y, CS) GEM_BUG_ON((Y)->end != (CS))
14		12
@@ -34,38 +32,59 @@ struct batch_chunk { · 19 unmodified lines
34	};	32	};
35		33
36	struct batch_vals {	34	struct batch_vals {
37	u32 max_primitives;	35	u32 max_threads;
38	u32 max_urb_entries;
39	u32 cmd_size;
40	u32 state_size;
41	u32 state_start;	36	u32 state_start;
42	u32 batch_size;	37	u32 surface_start;
43	u32 surface_height;	38	u32 surface_height;
44	u32 surface_width;	39	u32 surface_width;
45	u32 scratch_size;	40	u32 size;
46	u32 max_size;
47	};	41	};
48		42
		43	static inline int num_primitives(const struct batch_vals *bv)
		44	{
		45	/*
		46	* We need to saturate the GPU with work in order to dispatch
		47	* a shader on every HW thread, and clear the thread-local registers.
		48	* In short, we have to dispatch work faster than the shaders can
		49	* run in order to fill the EU and occupy each HW thread.
		50	*/
		51	return bv->max_threads;
		52	}
		53
49	static void	54	static void
50	batch_get_defaults(struct drm_i915_private i915, struct batch_vals bv)	55	batch_get_defaults(struct drm_i915_private i915, struct batch_vals bv)
51	{	56	{
52	if (IS_HASWELL(i915)) {	57	if (IS_HASWELL(i915)) {
53	bv->max_primitives = 280;	58	switch (INTEL_INFO(i915)->gt) {
54	bv->max_urb_entries = MAX_URB_ENTRIES;	59	default:
		60	case 1:
		61	bv->max_threads = 70;
		62	break;
		63	case 2:
		64	bv->max_threads = 140;
		65	break;
		66	case 3:
		67	bv->max_threads = 280;
		68	break;
		69	}
55	bv->surface_height = 16 * 16;	70	bv->surface_height = 16 * 16;
56	bv->surface_width = 32 * 2 * 16;	71	bv->surface_width = 32 * 2 * 16;
57	} else {	72	} else {
58	bv->max_primitives = 128;	73	switch (INTEL_INFO(i915)->gt) {
59	bv->max_urb_entries = MAX_URB_ENTRIES / 2;	74	default:
		75	case 1: /* including vlv */
		76	bv->max_threads = 36;
		77	break;
		78	case 2:
		79	bv->max_threads = 128;
		80	break;
		81	}
60	bv->surface_height = 16 * 8;	82	bv->surface_height = 16 * 8;
61	bv->surface_width = 32 * 16;	83	bv->surface_width = 32 * 16;
62	}	84	}
63	bv->cmd_size = bv->max_primitives * 4096;	85	bv->state_start = round_up(SZ_1K + num_primitives(bv) * 64, SZ_4K);
64	bv->state_size = STATE_SIZE;	86	bv->surface_start = bv->state_start + SZ_4K;
65	bv->state_start = bv->cmd_size;	87	bv->size = bv->surface_start + bv->surface_height * bv->surface_width;
66	bv->batch_size = bv->cmd_size + bv->state_size;
67	bv->scratch_size = bv->surface_height * bv->surface_width;
68	bv->max_size = bv->batch_size + bv->scratch_size;
69	}	88	}
70		89
71	static void batch_init(struct batch_chunk *bc,	90	static void batch_init(struct batch_chunk *bc,
@@ -155,7 +174,8 @@ static u32 · 83 unmodified lines
155	gen7_fill_binding_table(struct batch_chunk *state,	174	gen7_fill_binding_table(struct batch_chunk *state,
156	const struct batch_vals *bv)	175	const struct batch_vals *bv)
157	{	176	{
158	u32 surface_start = gen7_fill_surface_state(state, bv->batch_size, bv);	177	u32 surface_start =
		178	gen7_fill_surface_state(state, bv->surface_start, bv);
159	u32 *cs = batch_alloc_items(state, 32, 8);	179	u32 *cs = batch_alloc_items(state, 32, 8);
160	u32 offset = batch_offset(state, cs);	180	u32 offset = batch_offset(state, cs);
161		181
@@ -214,9 +234,9 @@ static void · 52 unmodified lines
214	gen7_emit_state_base_address(struct batch_chunk *batch,	234	gen7_emit_state_base_address(struct batch_chunk *batch,
215	u32 surface_state_base)	235	u32 surface_state_base)
216	{	236	{
217	u32 *cs = batch_alloc_items(batch, 0, 12);	237	u32 *cs = batch_alloc_items(batch, 0, 10);
218		238
219	*cs++ = STATE_BASE_ADDRESS \| (12 - 2);	239	*cs++ = STATE_BASE_ADDRESS \| (10 - 2);
220	/* general */	240	/* general */
221	*cs++ = batch_addr(batch) \| BASE_ADDRESS_MODIFY;	241	*cs++ = batch_addr(batch) \| BASE_ADDRESS_MODIFY;
222	/* surface */	242	/* surface */
@@ -233,8 +253,6 @@ gen7_emit_state_base_address(struct batch_chunk *batch, · 10 unmodified lines
233	*cs++ = BASE_ADDRESS_MODIFY;	253	*cs++ = BASE_ADDRESS_MODIFY;
234	*cs++ = 0;	254	*cs++ = 0;
235	*cs++ = BASE_ADDRESS_MODIFY;	255	*cs++ = BASE_ADDRESS_MODIFY;
236	*cs++ = 0;
237	*cs++ = 0;
238	batch_advance(batch, cs);	256	batch_advance(batch, cs);
239	}	257	}
240		258
@@ -244,8 +262,7 @@ gen7_emit_vfe_state(struct batch_chunk *batch, · 3 unmodified lines
244	u32 urb_size, u32 curbe_size,	262	u32 urb_size, u32 curbe_size,
245	u32 mode)	263	u32 mode)
246	{	264	{
247	u32 urb_entries = bv->max_urb_entries;	265	u32 threads = bv->max_threads - 1;
248	u32 threads = bv->max_primitives - 1;
249	u32 *cs = batch_alloc_items(batch, 32, 8);	266	u32 *cs = batch_alloc_items(batch, 32, 8);
250		267
251	*cs++ = MEDIA_VFE_STATE \| (8 - 2);	268	*cs++ = MEDIA_VFE_STATE \| (8 - 2);
@@ -254,7 +271,7 @@ gen7_emit_vfe_state(struct batch_chunk *batch, · 2 unmodified lines
254	*cs++ = 0;	271	*cs++ = 0;
255		272
256	/* number of threads & urb entries for GPGPU vs Media Mode */	273	/* number of threads & urb entries for GPGPU vs Media Mode */
257	*cs++ = threads << 16 \| urb_entries << 8 \| mode << 2;	274	*cs++ = threads << 16 \| 1 << 8 \| mode << 2;
258		275
259	*cs++ = 0;	276	*cs++ = 0;
260		277
@@ -293,17 +310,12 @@ gen7_emit_media_object(struct batch_chunk *batch, · 32 unmodified lines
293	{	310	{
294	unsigned int x_offset = (media_object_index % 16) * 64;	311	unsigned int x_offset = (media_object_index % 16) * 64;
295	unsigned int y_offset = (media_object_index / 16) * 16;	312	unsigned int y_offset = (media_object_index / 16) * 16;
296	unsigned int inline_data_size;	313	unsigned int pkt = 6 + 3;
297	unsigned int media_batch_size;
298	unsigned int i;
299	u32 *cs;	314	u32 *cs;
300		315
301	inline_data_size = 112 * 8;	316	cs = batch_alloc_items(batch, 8, pkt);
302	media_batch_size = inline_data_size + 6;
303
304	cs = batch_alloc_items(batch, 8, media_batch_size);
305		317
306	*cs++ = MEDIA_OBJECT \| (media_batch_size - 2);	318	*cs++ = MEDIA_OBJECT \| (pkt - 2);
307		319
308	/* interface descriptor offset */	320	/* interface descriptor offset */
309	*cs++ = 0;	321	*cs++ = 0;
@@ -317,25 +329,44 @@ gen7_emit_media_object(struct batch_chunk *batch, · 7 unmodified lines
317	*cs++ = 0;	329	*cs++ = 0;
318		330
319	/* inline */	331	/* inline */
320	*cs++ = (y_offset << 16) \| (x_offset);	332	*cs++ = y_offset << 16 \| x_offset;
321	*cs++ = 0;	333	*cs++ = 0;
322	*cs++ = GT3_INLINE_DATA_DELAYS;	334	*cs++ = GT3_INLINE_DATA_DELAYS;
323	for (i = 3; i < inline_data_size; i++)
324	*cs++ = 0;
325		335
326	batch_advance(batch, cs);	336	batch_advance(batch, cs);
327	}	337	}
328		338
329	static void gen7_emit_pipeline_flush(struct batch_chunk *batch)	339	static void gen7_emit_pipeline_flush(struct batch_chunk *batch)
330	{	340	{
331	u32 *cs = batch_alloc_items(batch, 0, 5);	341	u32 *cs = batch_alloc_items(batch, 0, 4);
332		342
333	*cs++ = GFX_OP_PIPE_CONTROL(5);	343	*cs++ = GFX_OP_PIPE_CONTROL(4);
334	*cs++ = PIPE_CONTROL_STATE_CACHE_INVALIDATE \|	344	*cs++ = PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH \|
335	PIPE_CONTROL_GLOBAL_GTT_IVB;	345	PIPE_CONTROL_DEPTH_CACHE_FLUSH \|
		346	PIPE_CONTROL_DC_FLUSH_ENABLE \|
		347	PIPE_CONTROL_CS_STALL;
336	*cs++ = 0;	348	*cs++ = 0;
337	*cs++ = 0;	349	*cs++ = 0;
		350
		351	batch_advance(batch, cs);
		352	}
		353
		354	static void gen7_emit_pipeline_invalidate(struct batch_chunk *batch)
		355	{
		356	u32 *cs = batch_alloc_items(batch, 0, 8);
		357
		358	/* ivb: Stall before STATE_CACHE_INVALIDATE */
		359	*cs++ = GFX_OP_PIPE_CONTROL(4);
		360	*cs++ = PIPE_CONTROL_STALL_AT_SCOREBOARD \|
		361	PIPE_CONTROL_CS_STALL;
		362	*cs++ = 0;
		363	*cs++ = 0;
		364
		365	*cs++ = GFX_OP_PIPE_CONTROL(4);
		366	*cs++ = PIPE_CONTROL_STATE_CACHE_INVALIDATE;
338	*cs++ = 0;	367	*cs++ = 0;
		368	*cs++ = 0;
		369
339	batch_advance(batch, cs);	370	batch_advance(batch, cs);
340	}	371	}
341		372
@@ -344,34 +375,34 @@ static void emit_batch(struct i915_vma * const vma, · 2 unmodified lines
344	const struct batch_vals *bv)	375	const struct batch_vals *bv)
345	{	376	{
346	struct drm_i915_private *i915 = vma->vm->i915;	377	struct drm_i915_private *i915 = vma->vm->i915;
347	unsigned int desc_count = 64;	378	const unsigned int desc_count = 1;
348	const u32 urb_size = 112;	379	const unsigned int urb_size = 1;
349	struct batch_chunk cmds, state;	380	struct batch_chunk cmds, state;
350	u32 interface_descriptor;	381	u32 descriptors;
351	unsigned int i;	382	unsigned int i;
352		383
353	batch_init(&cmds, vma, start, 0, bv->cmd_size);	384	batch_init(&cmds, vma, start, 0, bv->state_start);
354	batch_init(&state, vma, start, bv->state_start, bv->state_size);	385	batch_init(&state, vma, start, bv->state_start, SZ_4K);
355		386
356	interface_descriptor =	387	descriptors = gen7_fill_interface_descriptor(&state, bv,
357	gen7_fill_interface_descriptor(&state, bv,	388	IS_HASWELL(i915) ?
358	IS_HASWELL(i915) ?	389	&cb_kernel_hsw :
359	&cb_kernel_hsw :	390	&cb_kernel_ivb,
360	&cb_kernel_ivb,	391	desc_count);
361	desc_count);	392
362	gen7_emit_pipeline_flush(&cmds);	393	gen7_emit_pipeline_invalidate(&cmds);
363	batch_add(&cmds, PIPELINE_SELECT \| PIPELINE_SELECT_MEDIA);	394	batch_add(&cmds, PIPELINE_SELECT \| PIPELINE_SELECT_MEDIA);
364	batch_add(&cmds, MI_NOOP);	395	batch_add(&cmds, MI_NOOP);
365	gen7_emit_state_base_address(&cmds, interface_descriptor);	396	gen7_emit_pipeline_invalidate(&cmds);
		397
366	gen7_emit_pipeline_flush(&cmds);	398	gen7_emit_pipeline_flush(&cmds);
		399	gen7_emit_state_base_address(&cmds, descriptors);
		400	gen7_emit_pipeline_invalidate(&cmds);
367		401
368	gen7_emit_vfe_state(&cmds, bv, urb_size - 1, 0, 0);	402	gen7_emit_vfe_state(&cmds, bv, urb_size - 1, 0, 0);
		403	gen7_emit_interface_descriptor_load(&cmds, descriptors, desc_count);
369		404
370	gen7_emit_interface_descriptor_load(&cmds,	405	for (i = 0; i < num_primitives(bv); i++)
371	interface_descriptor,
372	desc_count);
373
374	for (i = 0; i < bv->max_primitives; i++)
375	gen7_emit_media_object(&cmds, i);	406	gen7_emit_media_object(&cmds, i);
376		407
377	batch_add(&cmds, MI_BATCH_BUFFER_END);	408	batch_add(&cmds, MI_BATCH_BUFFER_END);
@@ -385,15 +416,15 @@ int gen7_setup_clear_gpr_bb(struct intel_engine_cs * const engine, · 7 unmodified lines
385		416
386	batch_get_defaults(engine->i915, &bv);	417	batch_get_defaults(engine->i915, &bv);
387	if (!vma)	418	if (!vma)
388	return bv.max_size;	419	return bv.size;
389		420
390	GEM_BUG_ON(vma->obj->base.size < bv.max_size);	421	GEM_BUG_ON(vma->obj->base.size < bv.size);
391		422
392	batch = i915_gem_object_pin_map(vma->obj, I915_MAP_WC);	423	batch = i915_gem_object_pin_map(vma->obj, I915_MAP_WC);
393	if (IS_ERR(batch))	424	if (IS_ERR(batch))
394	return PTR_ERR(batch);	425	return PTR_ERR(batch);
395		426
396	emit_batch(vma, memset(batch, 0, bv.max_size), &bv);	427	emit_batch(vma, memset(batch, 0, bv.size), &bv);
397		428
398	i915_gem_object_flush_map(vma->obj);	429	i915_gem_object_flush_map(vma->obj);
399	__i915_gem_object_release_map(vma->obj);	430	__i915_gem_object_release_map(vma->obj);

drivers/gpu/drm/i915/gt/intel_ring_submission.c+4−2

 #include "gen6_ppgtt.h"
 #include "gen7_renderclear.h"
 #include "i915_drv.h"
+#include "i915_mitigations.h"
 #include "intel_breadcrumbs.h"
 #include "intel_context.h"
 #include "intel_gt.h"
 	GEM_BUG_ON(HAS_EXECLISTS(engine->i915));
 	if (engine->wa_ctx.vma && ce != engine->kernel_context) {
-		if (engine->wa_ctx.vma->private != ce) {
+		if (engine->wa_ctx.vma->private != ce &&
+		    i915_mitigate_clear_residuals()) {
 			ret = clear_residuals(rq);
 			if (ret)
 				return ret;
 	GEM_BUG_ON(timeline->hwsp_ggtt != engine->status_page.vma);
-	if (IS_HASWELL(engine->i915) && engine->class == RENDER_CLASS) {
+	if (IS_GEN(engine->i915, 7) && engine->class == RENDER_CLASS) {
 		err = gen7_ctx_switch_bb_init(engine);
 		if (err)
 			goto err_ring_unpin;

drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c+1−0

@@ -53,6 +53,7 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw, · 52 unmodified lines
53	fw_def(ELKHARTLAKE, 0, guc_def(ehl, 49, 0, 1), huc_def(ehl, 9, 0, 0)) \	53	fw_def(ELKHARTLAKE, 0, guc_def(ehl, 49, 0, 1), huc_def(ehl, 9, 0, 0)) \
54	fw_def(ICELAKE, 0, guc_def(icl, 49, 0, 1), huc_def(icl, 9, 0, 0)) \	54	fw_def(ICELAKE, 0, guc_def(icl, 49, 0, 1), huc_def(icl, 9, 0, 0)) \
55	fw_def(COMETLAKE, 5, guc_def(cml, 49, 0, 1), huc_def(cml, 4, 0, 0)) \	55	fw_def(COMETLAKE, 5, guc_def(cml, 49, 0, 1), huc_def(cml, 4, 0, 0)) \
		56	fw_def(COMETLAKE, 0, guc_def(kbl, 49, 0, 1), huc_def(kbl, 4, 0, 0)) \
56	fw_def(COFFEELAKE, 0, guc_def(kbl, 49, 0, 1), huc_def(kbl, 4, 0, 0)) \	57	fw_def(COFFEELAKE, 0, guc_def(kbl, 49, 0, 1), huc_def(kbl, 4, 0, 0)) \
57	fw_def(GEMINILAKE, 0, guc_def(glk, 49, 0, 1), huc_def(glk, 4, 0, 0)) \	58	fw_def(GEMINILAKE, 0, guc_def(glk, 49, 0, 1), huc_def(glk, 4, 0, 0)) \
58	fw_def(KABYLAKE, 0, guc_def(kbl, 49, 0, 1), huc_def(kbl, 4, 0, 0)) \	59	fw_def(KABYLAKE, 0, guc_def(kbl, 49, 0, 1), huc_def(kbl, 4, 0, 0)) \

drivers/gpu/drm/i915/gvt/display.c+57−24

 				  DDI_BUF_CTL_ENABLE);
 			vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) |= DDI_BUF_IS_IDLE;
 		}
+		vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
+			~(PORTA_HOTPLUG_ENABLE | PORTA_HOTPLUG_STATUS_MASK);
+		vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
+			~(PORTB_HOTPLUG_ENABLE | PORTB_HOTPLUG_STATUS_MASK);
+		vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
+			~(PORTC_HOTPLUG_ENABLE | PORTC_HOTPLUG_STATUS_MASK);
+		/* No hpd_invert set in vgpu vbt, need to clear invert mask */
+		vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= ~BXT_DDI_HPD_INVERT_MASK;
+		vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~BXT_DE_PORT_HOTPLUG_MASK;
 		vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= ~(BIT(0) | BIT(1));
 		vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=
 			vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)) |=
 				(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
 				 TRANS_DDI_FUNC_ENABLE);
+			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
+				PORTA_HOTPLUG_ENABLE;
 			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
 				GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
 		}
 				(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
 				 (PORT_B << TRANS_DDI_PORT_SHIFT) |
 				 TRANS_DDI_FUNC_ENABLE);
+			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
+				PORTB_HOTPLUG_ENABLE;
 			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
 				GEN8_DE_PORT_HOTPLUG(HPD_PORT_B);
 		}
 				(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
 				 (PORT_B << TRANS_DDI_PORT_SHIFT) |
 				 TRANS_DDI_FUNC_ENABLE);
+			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
+				PORTC_HOTPLUG_ENABLE;
 			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
 				GEN8_DE_PORT_HOTPLUG(HPD_PORT_C);
 		}
 				PORTD_HOTPLUG_STATUS_MASK;
 		intel_vgpu_trigger_virtual_event(vgpu, DP_D_HOTPLUG);
 	} else if (IS_BROXTON(i915)) {
-		if (connected) {
+		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
-			if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
+			if (connected) {
 				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
 					GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
+			} else {
+				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
+					~GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
 			}
-			if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
+			vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=
-				vgpu_vreg_t(vgpu, SFUSE_STRAP) |=
+				GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
-					SFUSE_STRAP_DDIB_DETECTED;
+			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
+				~PORTA_HOTPLUG_STATUS_MASK;
+			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
+				PORTA_HOTPLUG_LONG_DETECT;
+			intel_vgpu_trigger_virtual_event(vgpu, DP_A_HOTPLUG);
+		}
+		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
+			if (connected) {
 				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
 					GEN8_DE_PORT_HOTPLUG(HPD_PORT_B);
-			}
-			if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
 				vgpu_vreg_t(vgpu, SFUSE_STRAP) |=
-					SFUSE_STRAP_DDIC_DETECTED;
+					SFUSE_STRAP_DDIB_DETECTED;
-				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
+			} else {
-					GEN8_DE_PORT_HOTPLUG(HPD_PORT_C);
-			}
-		} else {
-			if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
 				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
-					~GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
+					~GEN8_DE_PORT_HOTPLUG(HPD_PORT_B);
-			}
-			if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
 				vgpu_vreg_t(vgpu, SFUSE_STRAP) &=
 					~SFUSE_STRAP_DDIB_DETECTED;
-				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
-					~GEN8_DE_PORT_HOTPLUG(HPD_PORT_B);
 			}
-			if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
+			vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=
-				vgpu_vreg_t(vgpu, SFUSE_STRAP) &=
+				GEN8_DE_PORT_HOTPLUG(HPD_PORT_B);
-					~SFUSE_STRAP_DDIC_DETECTED;
+			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
+				~PORTB_HOTPLUG_STATUS_MASK;
+			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
+				PORTB_HOTPLUG_LONG_DETECT;
+			intel_vgpu_trigger_virtual_event(vgpu, DP_B_HOTPLUG);
+		}
+		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
+			if (connected) {
+				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
+					GEN8_DE_PORT_HOTPLUG(HPD_PORT_C);
+				vgpu_vreg_t(vgpu, SFUSE_STRAP) |=
+					SFUSE_STRAP_DDIC_DETECTED;
+			} else {
 				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
 					~GEN8_DE_PORT_HOTPLUG(HPD_PORT_C);
+				vgpu_vreg_t(vgpu, SFUSE_STRAP) &=
+					~SFUSE_STRAP_DDIC_DETECTED;
 			}
+			vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=
+				GEN8_DE_PORT_HOTPLUG(HPD_PORT_C);
+			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
+				~PORTC_HOTPLUG_STATUS_MASK;
+			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
+				PORTC_HOTPLUG_LONG_DETECT;
+			intel_vgpu_trigger_virtual_event(vgpu, DP_C_HOTPLUG);
 		}
-		vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
-			PORTB_HOTPLUG_STATUS_MASK;
-		intel_vgpu_trigger_virtual_event(vgpu, DP_B_HOTPLUG);
 	}
 }

drivers/gpu/drm/i915/gvt/vgpu.c+2−3

 	if (ret)
 		goto out_clean_sched_policy;
-	if (IS_BROADWELL(dev_priv))
+	if (IS_BROADWELL(dev_priv) || IS_BROXTON(dev_priv))
 		ret = intel_gvt_hypervisor_set_edid(vgpu, PORT_B);
-	/* FixMe: Re-enable APL/BXT once vfio_edid enabled */
+	else
-	else if (!IS_BROXTON(dev_priv))
 		ret = intel_gvt_hypervisor_set_edid(vgpu, PORT_D);
 	if (ret)
 		goto out_clean_sched_policy;

drivers/gpu/drm/i915/i915_cmd_parser.c+9−18

 		}
 	}
 	if (IS_ERR(src)) {
-		unsigned long x, n;
+		unsigned long x, n, remain;
 		void *ptr;
 		/*
 		 * We don't care about copying too much here as we only
 		 * validate up to the end of the batch.
 		 */
+		remain = length;
 		if (!(dst_obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ))
-			length = round_up(length,
+			remain = round_up(remain,
 					  boot_cpu_data.x86_clflush_size);
 		ptr = dst;
 		x = offset_in_page(offset);
-		for (n = offset >> PAGE_SHIFT; length; n++) {
+		for (n = offset >> PAGE_SHIFT; remain; n++) {
-			int len = min(length, PAGE_SIZE - x);
+			int len = min(remain, PAGE_SIZE - x);
 			src = kmap_atomic(i915_gem_object_get_page(src_obj, n));
 			if (needs_clflush)
 			kunmap_atomic(src);
 			ptr += len;
-			length -= len;
+			remain -= len;
 			x = 0;
 		}
 	}
 	i915_gem_object_unpin_pages(src_obj);
+	memset32(dst + length, 0, (dst_obj->base.size - length) / sizeof(u32));
 	/* dst_obj is returned with vmap pinned */
 	return dst;
 }
 #define LENGTH_BIAS 2
-static bool shadow_needs_clflush(struct drm_i915_gem_object *obj)
-{
-	return !(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE);
-}
 /**
  * intel_engine_cmd_parser() - parse a batch buffer for privilege violations
  * @engine: the engine on which the batch is to execute
 				ret = 0; /* allow execution */
 			}
 		}
-		if (shadow_needs_clflush(shadow->obj))
-			drm_clflush_virt_range(batch_end, 8);
 	}
-	if (shadow_needs_clflush(shadow->obj)) {
+	i915_gem_object_flush_map(shadow->obj);
-		void *ptr = page_mask_bits(shadow->obj->mm.mapping);
-		drm_clflush_virt_range(ptr, (void *)(cmd + 1) - ptr);
-	}
 	if (!IS_ERR_OR_NULL(jump_whitelist))
 		kfree(jump_whitelist);

drivers/gpu/drm/i915/i915_drv.c+4−5

 	pci_set_master(pdev);
-	cpu_latency_qos_add_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 	intel_gt_init_workarounds(dev_priv);
 	/* On the 945G/GM, the chipset reports the MSI capability on the
 err_msi:
 	if (pdev->msi_enabled)
 		pci_disable_msi(pdev);
-	cpu_latency_qos_remove_request(&dev_priv->pm_qos);
 err_mem_regions:
 	intel_memory_regions_driver_release(dev_priv);
 err_ggtt:
 	if (pdev->msi_enabled)
 		pci_disable_msi(pdev);
-	cpu_latency_qos_remove_request(&dev_priv->pm_qos);
 }
 /**
 void i915_driver_shutdown(struct drm_i915_private *i915)
 {
+	disable_rpm_wakeref_asserts(&i915->runtime_pm);
 	i915_gem_suspend(i915);
 	drm_kms_helper_poll_disable(&i915->drm);
 	intel_suspend_encoders(i915);
 	intel_shutdown_encoders(i915);
+	enable_rpm_wakeref_asserts(&i915->runtime_pm);
 }
 static bool suspend_to_idle(struct drm_i915_private *dev_priv)

drivers/gpu/drm/i915/i915_drv.h+0−3

@@ -891,9 +891,6 @@ struct drm_i915_private { · 890 unmodified lines
891		891
892	bool display_irqs_enabled;	892	bool display_irqs_enabled;
893		893
894	/* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
895	struct pm_qos_request pm_qos;
896
897	/* Sideband mailbox protection */	894	/* Sideband mailbox protection */
898	struct mutex sb_lock;	895	struct mutex sb_lock;
899	struct pm_qos_request sb_qos;	896	struct pm_qos_request sb_qos;

drivers/gpu/drm/i915/i915_mitigations.c+146−0

@@ -0,0 +1,146 @@
	1	// SPDX-License-Identifier: MIT
	2	/*
	3	* Copyright © 2021 Intel Corporation
	4	*/
	5
	6	#include <linux/kernel.h>
	7	#include <linux/moduleparam.h>
	8	#include <linux/slab.h>
	9	#include <linux/string.h>
	10
	11	#include "i915_drv.h"
	12	#include "i915_mitigations.h"
	13
	14	static unsigned long mitigations __read_mostly = ~0UL;
	15
	16	enum {
	17	CLEAR_RESIDUALS = 0,
	18	};
	19
	20	static const char * const names[] = {
	21	[CLEAR_RESIDUALS] = "residuals",
	22	};
	23
	24	bool i915_mitigate_clear_residuals(void)
	25	{
	26	return READ_ONCE(mitigations) & BIT(CLEAR_RESIDUALS);
	27	}
	28
	29	static int mitigations_set(const char val, const struct kernel_param kp)
	30	{
	31	unsigned long new = ~0UL;
	32	char str, sep, *tok;
	33	bool first = true;
	34	int err = 0;
	35
	36	BUILD_BUG_ON(ARRAY_SIZE(names) >= BITS_PER_TYPE(mitigations));
	37
	38	str = kstrdup(val, GFP_KERNEL);
	39	if (!str)
	40	return -ENOMEM;
	41
	42	for (sep = str; (tok = strsep(&sep, ","));) {
	43	bool enable = true;
	44	int i;
	45
	46	/* Be tolerant of leading/trailing whitespace */
	47	tok = strim(tok);
	48
	49	if (first) {
	50	first = false;
	51
	52	if (!strcmp(tok, "auto"))
	53	continue;
	54
	55	new = 0;
	56	if (!strcmp(tok, "off"))
	57	continue;
	58	}
	59
	60	if (*tok == '!') {
	61	enable = !enable;
	62	tok++;
	63	}
	64
	65	if (!strncmp(tok, "no", 2)) {
	66	enable = !enable;
	67	tok += 2;
	68	}
	69
	70	if (*tok == '\0')
	71	continue;
	72
	73	for (i = 0; i < ARRAY_SIZE(names); i++) {
	74	if (!strcmp(tok, names[i])) {
	75	if (enable)
	76	new \|= BIT(i);
	77	else
	78	new &= ~BIT(i);
	79	break;
	80	}
	81	}
	82	if (i == ARRAY_SIZE(names)) {
	83	pr_err("Bad \"%s.mitigations=%s\", '%s' is unknown\n",
	84	DRIVER_NAME, val, tok);
	85	err = -EINVAL;
	86	break;
	87	}
	88	}
	89	kfree(str);
	90	if (err)
	91	return err;
	92
	93	WRITE_ONCE(mitigations, new);
	94	return 0;
	95	}
	96
	97	static int mitigations_get(char buffer, const struct kernel_param kp)
	98	{
	99	unsigned long local = READ_ONCE(mitigations);
	100	int count, i;
	101	bool enable;
	102
	103	if (!local)
	104	return scnprintf(buffer, PAGE_SIZE, "%s\n", "off");
	105
	106	if (local & BIT(BITS_PER_LONG - 1)) {
	107	count = scnprintf(buffer, PAGE_SIZE, "%s,", "auto");
	108	enable = false;
	109	} else {
	110	enable = true;
	111	count = 0;
	112	}
	113
	114	for (i = 0; i < ARRAY_SIZE(names); i++) {
	115	if ((local & BIT(i)) != enable)
	116	continue;
	117
	118	count += scnprintf(buffer + count, PAGE_SIZE - count,
	119	"%s%s,", enable ? "" : "!", names[i]);
	120	}
	121
	122	buffer[count - 1] = '\n';
	123	return count;
	124	}
	125
	126	static const struct kernel_param_ops ops = {
	127	.set = mitigations_set,
	128	.get = mitigations_get,
	129	};
	130
	131	module_param_cb_unsafe(mitigations, &ops, NULL, 0600);
	132	MODULE_PARM_DESC(mitigations,
	133	"Selectively enable security mitigations for all Intel® GPUs in the system.\n"
	134	"\n"
	135	" auto -- enables all mitigations required for the platform [default]\n"
	136	" off -- disables all mitigations\n"
	137	"\n"
	138	"Individual mitigations can be enabled by passing a comma-separated string,\n"
	139	"e.g. mitigations=residuals to enable only clearing residuals or\n"
	140	"mitigations=auto,noresiduals to disable only the clear residual mitigation.\n"
	141	"Either '!' or 'no' may be used to switch from enabling the mitigation to\n"
	142	"disabling it.\n"
	143	"\n"
	144	"Active mitigations for Ivybridge, Baytrail, Haswell:\n"
	145	" residuals -- clear all thread-local registers between contexts"
	146	);

drivers/gpu/drm/i915/i915_mitigations.h+13−0

@@ -0,0 +1,13 @@
	1	/* SPDX-License-Identifier: MIT */
	2	/*
	3	* Copyright © 2021 Intel Corporation
	4	*/
	5
	6	#ifndef __I915_MITIGATIONS_H__
	7	#define __I915_MITIGATIONS_H__
	8
	9	#include <linux/types.h>
	10
	11	bool i915_mitigate_clear_residuals(void);
	12
	13	#endif /* __I915_MITIGATIONS_H__ */

drivers/gpu/drm/msm/adreno/a2xx_gpu.c+4−2

 	if (!gpu->aspace) {
 		dev_err(dev->dev, "No memory protection without MMU\n");
-		ret = -ENXIO;
+		if (!allow_vram_carveout) {
-		goto fail;
+			ret = -ENXIO;
+			goto fail;
+		}
 	}
 	return gpu;

drivers/gpu/drm/msm/adreno/a3xx_gpu.c+4−2

 		 * implement a cmdstream validator.
 		 */
 		DRM_DEV_ERROR(dev->dev, "No memory protection without IOMMU\n");
-		ret = -ENXIO;
+		if (!allow_vram_carveout) {
-		goto fail;
+			ret = -ENXIO;
+			goto fail;
+		}
 	}
 	icc_path = devm_of_icc_get(&pdev->dev, "gfx-mem");

drivers/gpu/drm/msm/adreno/a4xx_gpu.c+4−2

 		 * implement a cmdstream validator.
 		 */
 		DRM_DEV_ERROR(dev->dev, "No memory protection without IOMMU\n");
-		ret = -ENXIO;
+		if (!allow_vram_carveout) {
-		goto fail;
+			ret = -ENXIO;
+			goto fail;
+		}
 	}
 	icc_path = devm_of_icc_get(&pdev->dev, "gfx-mem");

drivers/gpu/drm/msm/adreno/adreno_device.c+4−0

 MODULE_PARM_DESC(snapshot_debugbus, "Include debugbus sections in GPU devcoredump (if not fused off)");
 module_param_named(snapshot_debugbus, snapshot_debugbus, bool, 0600);
+bool allow_vram_carveout = false;
+MODULE_PARM_DESC(allow_vram_carveout, "Allow using VRAM Carveout, in place of IOMMU");
+module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600);
 static const struct adreno_info gpulist[] = {
 	{
 		.rev   = ADRENO_REV(2, 0, 0, 0),

drivers/gpu/drm/msm/adreno/adreno_gpu.c+12−9

@@ -191,8 +191,6 @@ adreno_iommu_create_address_space(struct msm_gpu *gpu, · 190 unmodified lines
191	struct platform_device *pdev)	191	struct platform_device *pdev)
192	{	192	{
193	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);	193	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
194	struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
195	struct io_pgtable_domain_attr pgtbl_cfg;
196	struct iommu_domain *iommu;	194	struct iommu_domain *iommu;
197	struct msm_mmu *mmu;	195	struct msm_mmu *mmu;
198	struct msm_gem_address_space *aspace;	196	struct msm_gem_address_space *aspace;
@@ -202,13 +200,18 @@ adreno_iommu_create_address_space(struct msm_gpu *gpu, · 3 unmodified lines
202	if (!iommu)	200	if (!iommu)
203	return NULL;	201	return NULL;
204		202
205	/*	203
206	* This allows GPU to set the bus attributes required to use system	204	if (adreno_is_a6xx(adreno_gpu)) {
207	* cache on behalf of the iommu page table walker.	205	struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
208	*/	206	struct io_pgtable_domain_attr pgtbl_cfg;
209	if (!IS_ERR(a6xx_gpu->htw_llc_slice)) {	207	/*
210	pgtbl_cfg.quirks = IO_PGTABLE_QUIRK_ARM_OUTER_WBWA;	208	* This allows GPU to set the bus attributes required to use system
211	iommu_domain_set_attr(iommu, DOMAIN_ATTR_IO_PGTABLE_CFG, &pgtbl_cfg);	209	* cache on behalf of the iommu page table walker.
		210	*/
		211	if (!IS_ERR(a6xx_gpu->htw_llc_slice)) {
		212	pgtbl_cfg.quirks = IO_PGTABLE_QUIRK_ARM_OUTER_WBWA;
		213	iommu_domain_set_attr(iommu, DOMAIN_ATTR_IO_PGTABLE_CFG, &pgtbl_cfg);
		214	}
212	}	215	}
213		216
214	mmu = msm_iommu_new(&pdev->dev, iommu);	217	mmu = msm_iommu_new(&pdev->dev, iommu);

drivers/gpu/drm/msm/adreno/adreno_gpu.h+6−0

 #include "adreno_pm4.xml.h"
 extern bool snapshot_debugbus;
+extern bool allow_vram_carveout;
 enum {
 	ADRENO_FW_PM4 = 0,
 	return gpu->revn == 540;
 }
+static inline bool adreno_is_a6xx(struct adreno_gpu *gpu)
+{
+	return ((gpu->revn < 700 && gpu->revn > 599));
+}
 static inline int adreno_is_a618(struct adreno_gpu *gpu)
 {
        return gpu->revn == 618;

drivers/gpu/drm/msm/dp/dp_display.c+7−0

@@ -693,6 +693,13 @@ static int dp_irq_hpd_handle(struct dp_display_private *dp, u32 data) · 692 unmodified lines
693	return 0;	693	return 0;
694	}	694	}
695		695
		696	if (state == ST_CONNECT_PENDING) {
		697	/* wait until ST_CONNECTED */
		698	dp_add_event(dp, EV_IRQ_HPD_INT, 0, 1); /* delay = 1 */
		699	mutex_unlock(&dp->event_mutex);
		700	return 0;
		701	}
		702
696	ret = dp_display_usbpd_attention_cb(&dp->pdev->dev);	703	ret = dp_display_usbpd_attention_cb(&dp->pdev->dev);
697	if (ret == -ECONNRESET) { /* cable unplugged */	704	if (ret == -ECONNRESET) { /* cable unplugged */
698	dp->core_initialized = false;	705	dp->core_initialized = false;

drivers/gpu/drm/msm/dp/dp_panel.c+9−3

 	panel = container_of(dp_panel, struct dp_panel_private, dp_panel);
 	rc = dp_panel_read_dpcd(dp_panel);
+	if (rc) {
+		DRM_ERROR("read dpcd failed %d\n", rc);
+		return rc;
+	}
 	bw_code = drm_dp_link_rate_to_bw_code(dp_panel->link_info.rate);
-	if (rc || !is_link_rate_valid(bw_code) ||
+	if (!is_link_rate_valid(bw_code) ||
 			!is_lane_count_valid(dp_panel->link_info.num_lanes) ||
 			(bw_code > dp_panel->max_bw_code)) {
-		DRM_ERROR("read dpcd failed %d\n", rc);
+		DRM_ERROR("Illegal link rate=%d lane=%d\n", dp_panel->link_info.rate,
-		return rc;
+				dp_panel->link_info.num_lanes);
+		return -EINVAL;
 	}
 	if (dp_panel->dfp_present) {

drivers/gpu/drm/msm/msm_drv.c+4−4

 	drm_mode_config_init(ddev);
-	/* Bind all our sub-components: */
+	ret = msm_init_vram(ddev);
-	ret = component_bind_all(dev, ddev);
 	if (ret)
 		goto err_destroy_mdss;
-	ret = msm_init_vram(ddev);
+	/* Bind all our sub-components: */
+	ret = component_bind_all(dev, ddev);
 	if (ret)
-		goto err_msm_uninit;
+		goto err_destroy_mdss;
 	dma_set_max_seg_size(dev, UINT_MAX);

drivers/gpu/drm/msm/msm_gem.c+9−4

 {
 	struct msm_gem_object *msm_obj = to_msm_bo(obj);
+	WARN_ON(!msm_gem_is_locked(obj));
 	if (!msm_obj->pages) {
 		struct drm_device *dev = obj->dev;
 		struct page **p;
 		if (msm_obj->pages)
 			kvfree(msm_obj->pages);
+		put_iova_vmas(obj);
 		/* dma_buf_detach() grabs resv lock, so we need to unlock
 		 * prior to drm_prime_gem_destroy
 		 */
 	} else {
 		msm_gem_vunmap(obj);
 		put_pages(obj);
+		put_iova_vmas(obj);
 		msm_gem_unlock(obj);
 	}
-	put_iova_vmas(obj);
 	drm_gem_object_release(obj);
 	kfree(msm_obj);
 		struct msm_gem_vma *vma;
 		struct page **pages;
+		drm_gem_private_object_init(dev, obj, size);
 		msm_gem_lock(obj);
 		vma = add_vma(obj, NULL);
 		to_msm_bo(obj)->vram_node = &vma->node;
-		drm_gem_private_object_init(dev, obj, size);
+		msm_gem_lock(obj);
 		pages = get_pages(obj);
+		msm_gem_unlock(obj);
 		if (IS_ERR(pages)) {
 			ret = PTR_ERR(pages);
 			goto fail;

drivers/gpu/drm/nouveau/dispnv50/Kbuild+1−0

@@ -37,6 +37,7 @@ nouveau-y += dispnv50/wimmc37b.o · 36 unmodified lines
37	nouveau-y += dispnv50/wndw.o	37	nouveau-y += dispnv50/wndw.o
38	nouveau-y += dispnv50/wndwc37e.o	38	nouveau-y += dispnv50/wndwc37e.o
39	nouveau-y += dispnv50/wndwc57e.o	39	nouveau-y += dispnv50/wndwc57e.o
		40	nouveau-y += dispnv50/wndwc67e.o
40		41
41	nouveau-y += dispnv50/base.o	42	nouveau-y += dispnv50/base.o
42	nouveau-y += dispnv50/base507c.o	43	nouveau-y += dispnv50/base507c.o

drivers/gpu/drm/nouveau/dispnv50/core.c+1−0

@@ -42,6 +42,7 @@ nv50_core_new(struct nouveau_drm drm, struct nv50_core *pcore) · 41 unmodified lines
42	int version;	42	int version;
43	int (new)(struct nouveau_drm , s32, struct nv50_core **);	43	int (new)(struct nouveau_drm , s32, struct nv50_core **);
44	} cores[] = {	44	} cores[] = {
		45	{ GA102_DISP_CORE_CHANNEL_DMA, 0, corec57d_new },
45	{ TU102_DISP_CORE_CHANNEL_DMA, 0, corec57d_new },	46	{ TU102_DISP_CORE_CHANNEL_DMA, 0, corec57d_new },
46	{ GV100_DISP_CORE_CHANNEL_DMA, 0, corec37d_new },	47	{ GV100_DISP_CORE_CHANNEL_DMA, 0, corec37d_new },
47	{ GP102_DISP_CORE_CHANNEL_DMA, 0, core917d_new },	48	{ GP102_DISP_CORE_CHANNEL_DMA, 0, core917d_new },

drivers/gpu/drm/nouveau/dispnv50/curs.c+1−0

@@ -31,6 +31,7 @@ nv50_curs_new(struct nouveau_drm drm, int head, struct nv50_wndw *pwndw) · 30 unmodified lines
31	int version;	31	int version;
32	int (new)(struct nouveau_drm , int, s32, struct nv50_wndw **);	32	int (new)(struct nouveau_drm , int, s32, struct nv50_wndw **);
33	} curses[] = {	33	} curses[] = {
		34	{ GA102_DISP_CURSOR, 0, cursc37a_new },
34	{ TU102_DISP_CURSOR, 0, cursc37a_new },	35	{ TU102_DISP_CURSOR, 0, cursc37a_new },
35	{ GV100_DISP_CURSOR, 0, cursc37a_new },	36	{ GV100_DISP_CURSOR, 0, cursc37a_new },
36	{ GK104_DISP_CURSOR, 0, curs907a_new },	37	{ GK104_DISP_CURSOR, 0, curs907a_new },

drivers/gpu/drm/nouveau/dispnv50/disp.c+2−2

@@ -222,7 +222,7 @@ nv50_dmac_wait(struct nvif_push *push, u32 size) · 221 unmodified lines
222		222
223	int	223	int
224	nv50_dmac_create(struct nvif_device device, struct nvif_object disp,	224	nv50_dmac_create(struct nvif_device device, struct nvif_object disp,
225	const s32 oclass, u8 head, void data, u32 size, u64 syncbuf,	225	const s32 oclass, u8 head, void data, u32 size, s64 syncbuf,
226	struct nv50_dmac *dmac)	226	struct nv50_dmac *dmac)
227	{	227	{
228	struct nouveau_cli cli = (void )device->object.client;	228	struct nouveau_cli cli = (void )device->object.client;
@@ -271,7 +271,7 @@ nv50_dmac_create(struct nvif_device device, struct nvif_object disp, · 42 unmodified lines
271	if (ret)	271	if (ret)
272	return ret;	272	return ret;
273		273
274	if (!syncbuf)	274	if (syncbuf < 0)
275	return 0;	275	return 0;
276		276
277	ret = nvif_object_ctor(&dmac->base.user, "kmsSyncCtxDma", NV50_DISP_HANDLE_SYNCBUF,	277	ret = nvif_object_ctor(&dmac->base.user, "kmsSyncCtxDma", NV50_DISP_HANDLE_SYNCBUF,

drivers/gpu/drm/nouveau/dispnv50/disp.h+1−1

@@ -95,7 +95,7 @@ struct nv50_outp_atom { · 94 unmodified lines
95		95
96	int nv50_dmac_create(struct nvif_device device, struct nvif_object disp,	96	int nv50_dmac_create(struct nvif_device device, struct nvif_object disp,
97	const s32 oclass, u8 head, void data, u32 size,	97	const s32 oclass, u8 head, void data, u32 size,
98	u64 syncbuf, struct nv50_dmac *dmac);	98	s64 syncbuf, struct nv50_dmac *dmac);
99	void nv50_dmac_destroy(struct nv50_dmac *);	99	void nv50_dmac_destroy(struct nv50_dmac *);
100		100
101	/*	101	/*

drivers/gpu/drm/nouveau/dispnv50/wimm.c+1−0

@@ -31,6 +31,7 @@ nv50_wimm_init(struct nouveau_drm drm, struct nv50_wndw wndw) · 30 unmodified lines
31	int version;	31	int version;
32	int (init)(struct nouveau_drm , s32, struct nv50_wndw *);	32	int (init)(struct nouveau_drm , s32, struct nv50_wndw *);
33	} wimms[] = {	33	} wimms[] = {
		34	{ GA102_DISP_WINDOW_IMM_CHANNEL_DMA, 0, wimmc37b_init },
34	{ TU102_DISP_WINDOW_IMM_CHANNEL_DMA, 0, wimmc37b_init },	35	{ TU102_DISP_WINDOW_IMM_CHANNEL_DMA, 0, wimmc37b_init },
35	{ GV100_DISP_WINDOW_IMM_CHANNEL_DMA, 0, wimmc37b_init },	36	{ GV100_DISP_WINDOW_IMM_CHANNEL_DMA, 0, wimmc37b_init },
36	{}	37	{}

drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c+1−1

@@ -76,7 +76,7 @@ wimmc37b_init_(const struct nv50_wimm_func func, struct nouveau_drm drm, · 75 unmodified lines
76	int ret;	76	int ret;
77		77
78	ret = nv50_dmac_create(&drm->client.device, &disp->disp->object,	78	ret = nv50_dmac_create(&drm->client.device, &disp->disp->object,
79	&oclass, 0, &args, sizeof(args), 0,	79	&oclass, 0, &args, sizeof(args), -1,
80	&wndw->wimm);	80	&wndw->wimm);
81	if (ret) {	81	if (ret) {
82	NV_ERROR(drm, "wimm%04x allocation failed: %d\n", oclass, ret);	82	NV_ERROR(drm, "wimm%04x allocation failed: %d\n", oclass, ret);

drivers/gpu/drm/nouveau/dispnv50/wndw.c+1−0

@@ -784,6 +784,7 @@ nv50_wndw_new(struct nouveau_drm *drm, enum drm_plane_type type, int index, · 783 unmodified lines
784	int (new)(struct nouveau_drm , enum drm_plane_type,	784	int (new)(struct nouveau_drm , enum drm_plane_type,
785	int, s32, struct nv50_wndw **);	785	int, s32, struct nv50_wndw **);
786	} wndws[] = {	786	} wndws[] = {
		787	{ GA102_DISP_WINDOW_CHANNEL_DMA, 0, wndwc67e_new },
787	{ TU102_DISP_WINDOW_CHANNEL_DMA, 0, wndwc57e_new },	788	{ TU102_DISP_WINDOW_CHANNEL_DMA, 0, wndwc57e_new },
788	{ GV100_DISP_WINDOW_CHANNEL_DMA, 0, wndwc37e_new },	789	{ GV100_DISP_WINDOW_CHANNEL_DMA, 0, wndwc37e_new },
789	{}	790	{}

drivers/gpu/drm/nouveau/dispnv50/wndw.h+8−0

@@ -129,6 +129,14 @@ int wndwc37e_update(struct nv50_wndw , u32 ); · 128 unmodified lines
129		129
130	int wndwc57e_new(struct nouveau_drm *, enum drm_plane_type, int, s32,	130	int wndwc57e_new(struct nouveau_drm *, enum drm_plane_type, int, s32,
131	struct nv50_wndw **);	131	struct nv50_wndw **);
		132	bool wndwc57e_ilut(struct nv50_wndw , struct nv50_wndw_atom , int);
		133	int wndwc57e_ilut_set(struct nv50_wndw , struct nv50_wndw_atom );
		134	int wndwc57e_ilut_clr(struct nv50_wndw *);
		135	int wndwc57e_csc_set(struct nv50_wndw , struct nv50_wndw_atom );
		136	int wndwc57e_csc_clr(struct nv50_wndw *);
		137
		138	int wndwc67e_new(struct nouveau_drm *, enum drm_plane_type, int, s32,
		139	struct nv50_wndw **);
132		140
133	int nv50_wndw_new(struct nouveau_drm *, enum drm_plane_type, int index,	141	int nv50_wndw_new(struct nouveau_drm *, enum drm_plane_type, int index,
134	struct nv50_wndw **);	142	struct nv50_wndw **);

drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c+5−5

@@ -80,7 +80,7 @@ wndwc57e_image_set(struct nv50_wndw wndw, struct nv50_wndw_atom asyw) · 79 unmodified lines
80	return 0;	80	return 0;
81	}	81	}
82		82
83	static int	83	int
84	wndwc57e_csc_clr(struct nv50_wndw *wndw)	84	wndwc57e_csc_clr(struct nv50_wndw *wndw)
85	{	85	{
86	struct nvif_push *push = wndw->wndw.push;	86	struct nvif_push *push = wndw->wndw.push;
@@ -98,7 +98,7 @@ wndwc57e_csc_clr(struct nv50_wndw *wndw) · 11 unmodified lines
98	return 0;	98	return 0;
99	}	99	}
100		100
101	static int	101	int
102	wndwc57e_csc_set(struct nv50_wndw wndw, struct nv50_wndw_atom asyw)	102	wndwc57e_csc_set(struct nv50_wndw wndw, struct nv50_wndw_atom asyw)
103	{	103	{
104	struct nvif_push *push = wndw->wndw.push;	104	struct nvif_push *push = wndw->wndw.push;
@@ -111,7 +111,7 @@ wndwc57e_csc_set(struct nv50_wndw wndw, struct nv50_wndw_atom asyw) · 6 unmodified lines
111	return 0;	111	return 0;
112	}	112	}
113		113
114	static int	114	int
115	wndwc57e_ilut_clr(struct nv50_wndw *wndw)	115	wndwc57e_ilut_clr(struct nv50_wndw *wndw)
116	{	116	{
117	struct nvif_push *push = wndw->wndw.push;	117	struct nvif_push *push = wndw->wndw.push;
@@ -124,7 +124,7 @@ wndwc57e_ilut_clr(struct nv50_wndw *wndw) · 6 unmodified lines
124	return 0;	124	return 0;
125	}	125	}
126		126
127	static int	127	int
128	wndwc57e_ilut_set(struct nv50_wndw wndw, struct nv50_wndw_atom asyw)	128	wndwc57e_ilut_set(struct nv50_wndw wndw, struct nv50_wndw_atom asyw)
129	{	129	{
130	struct nvif_push *push = wndw->wndw.push;	130	struct nvif_push *push = wndw->wndw.push;
@@ -179,7 +179,7 @@ wndwc57e_ilut_load(struct drm_color_lut in, int size, void __iomem mem) · 48 unmodified lines
179	writew(readw(mem - 4), mem + 4);	179	writew(readw(mem - 4), mem + 4);
180	}	180	}
181		181
182	static bool	182	bool
183	wndwc57e_ilut(struct nv50_wndw wndw, struct nv50_wndw_atom asyw, int size)	183	wndwc57e_ilut(struct nv50_wndw wndw, struct nv50_wndw_atom asyw, int size)
184	{	184	{
185	if (size = size ? size : 1024, size != 256 && size != 1024)	185	if (size = size ? size : 1024, size != 256 && size != 1024)

drivers/gpu/drm/nouveau/dispnv50/wndwc67e.c+106−0

@@ -0,0 +1,106 @@
	1	/*
	2	* Copyright 2021 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*/
	22	#include "wndw.h"
	23	#include "atom.h"
	24
	25	#include <nvif/pushc37b.h>
	26
	27	#include <nvhw/class/clc57e.h>
	28
	29	static int
	30	wndwc67e_image_set(struct nv50_wndw wndw, struct nv50_wndw_atom asyw)
	31	{
	32	struct nvif_push *push = wndw->wndw.push;
	33	int ret;
	34
	35	if ((ret = PUSH_WAIT(push, 17)))
	36	return ret;
	37
	38	PUSH_MTHD(push, NVC57E, SET_PRESENT_CONTROL,
	39	NVVAL(NVC57E, SET_PRESENT_CONTROL, MIN_PRESENT_INTERVAL, asyw->image.interval) \|
	40	NVVAL(NVC57E, SET_PRESENT_CONTROL, BEGIN_MODE, asyw->image.mode) \|
	41	NVDEF(NVC57E, SET_PRESENT_CONTROL, TIMESTAMP_MODE, DISABLE));
	42
	43	PUSH_MTHD(push, NVC57E, SET_SIZE,
	44	NVVAL(NVC57E, SET_SIZE, WIDTH, asyw->image.w) \|
	45	NVVAL(NVC57E, SET_SIZE, HEIGHT, asyw->image.h),
	46
	47	SET_STORAGE,
	48	NVVAL(NVC57E, SET_STORAGE, BLOCK_HEIGHT, asyw->image.blockh),
	49
	50	SET_PARAMS,
	51	NVVAL(NVC57E, SET_PARAMS, FORMAT, asyw->image.format) \|
	52	NVDEF(NVC57E, SET_PARAMS, CLAMP_BEFORE_BLEND, DISABLE) \|
	53	NVDEF(NVC57E, SET_PARAMS, SWAP_UV, DISABLE) \|
	54	NVDEF(NVC57E, SET_PARAMS, FMT_ROUNDING_MODE, ROUND_TO_NEAREST),
	55
	56	SET_PLANAR_STORAGE(0),
	57	NVVAL(NVC57E, SET_PLANAR_STORAGE, PITCH, asyw->image.blocks[0]) \|
	58	NVVAL(NVC57E, SET_PLANAR_STORAGE, PITCH, asyw->image.pitch[0] >> 6));
	59
	60	PUSH_MTHD(push, NVC57E, SET_CONTEXT_DMA_ISO(0), asyw->image.handle, 1);
	61	PUSH_MTHD(push, NVC57E, SET_OFFSET(0), asyw->image.offset[0] >> 8);
	62
	63	PUSH_MTHD(push, NVC57E, SET_POINT_IN(0),
	64	NVVAL(NVC57E, SET_POINT_IN, X, asyw->state.src_x >> 16) \|
	65	NVVAL(NVC57E, SET_POINT_IN, Y, asyw->state.src_y >> 16));
	66
	67	PUSH_MTHD(push, NVC57E, SET_SIZE_IN,
	68	NVVAL(NVC57E, SET_SIZE_IN, WIDTH, asyw->state.src_w >> 16) \|
	69	NVVAL(NVC57E, SET_SIZE_IN, HEIGHT, asyw->state.src_h >> 16));
	70
	71	PUSH_MTHD(push, NVC57E, SET_SIZE_OUT,
	72	NVVAL(NVC57E, SET_SIZE_OUT, WIDTH, asyw->state.crtc_w) \|
	73	NVVAL(NVC57E, SET_SIZE_OUT, HEIGHT, asyw->state.crtc_h));
	74	return 0;
	75	}
	76
	77	static const struct nv50_wndw_func
	78	wndwc67e = {
	79	.acquire = wndwc37e_acquire,
	80	.release = wndwc37e_release,
	81	.sema_set = wndwc37e_sema_set,
	82	.sema_clr = wndwc37e_sema_clr,
	83	.ntfy_set = wndwc37e_ntfy_set,
	84	.ntfy_clr = wndwc37e_ntfy_clr,
	85	.ntfy_reset = corec37d_ntfy_init,
	86	.ntfy_wait_begun = base507c_ntfy_wait_begun,
	87	.ilut = wndwc57e_ilut,
	88	.ilut_identity = true,
	89	.ilut_size = 1024,
	90	.xlut_set = wndwc57e_ilut_set,
	91	.xlut_clr = wndwc57e_ilut_clr,
	92	.csc = base907c_csc,
	93	.csc_set = wndwc57e_csc_set,
	94	.csc_clr = wndwc57e_csc_clr,
	95	.image_set = wndwc67e_image_set,
	96	.image_clr = wndwc37e_image_clr,
	97	.blend_set = wndwc37e_blend_set,
	98	.update = wndwc37e_update,
	99	};
	100
	101	int
	102	wndwc67e_new(struct nouveau_drm *drm, enum drm_plane_type type, int index,
	103	s32 oclass, struct nv50_wndw **pwndw)
	104	{
	105	return wndwc37e_new_(&wndwc67e, drm, type, index, oclass, BIT(index >> 1), pwndw);
	106	}

drivers/gpu/drm/nouveau/include/nvif/cl0080.h+1−0

@@ -33,6 +33,7 @@ struct nv_device_info_v0 { · 32 unmodified lines
33	#define NV_DEVICE_INFO_V0_PASCAL 0x0a	33	#define NV_DEVICE_INFO_V0_PASCAL 0x0a
34	#define NV_DEVICE_INFO_V0_VOLTA 0x0b	34	#define NV_DEVICE_INFO_V0_VOLTA 0x0b
35	#define NV_DEVICE_INFO_V0_TURING 0x0c	35	#define NV_DEVICE_INFO_V0_TURING 0x0c
		36	#define NV_DEVICE_INFO_V0_AMPERE 0x0d
36	__u8 family;	37	__u8 family;
37	__u8 pad06[2];	38	__u8 pad06[2];
38	__u64 ram_size;	39	__u64 ram_size;

drivers/gpu/drm/nouveau/include/nvif/class.h+5−0

 #define GP102_DISP                                    /* cl5070.h */ 0x00009870
 #define GV100_DISP                                    /* cl5070.h */ 0x0000c370
 #define TU102_DISP                                    /* cl5070.h */ 0x0000c570
+#define GA102_DISP                                    /* cl5070.h */ 0x0000c670
 #define GV100_DISP_CAPS                                              0x0000c373
 #define GK104_DISP_CURSOR                             /* cl507a.h */ 0x0000917a
 #define GV100_DISP_CURSOR                             /* cl507a.h */ 0x0000c37a
 #define TU102_DISP_CURSOR                             /* cl507a.h */ 0x0000c57a
+#define GA102_DISP_CURSOR                             /* cl507a.h */ 0x0000c67a
 #define NV50_DISP_OVERLAY                             /* cl507b.h */ 0x0000507b
 #define G82_DISP_OVERLAY                              /* cl507b.h */ 0x0000827b
 #define GV100_DISP_WINDOW_IMM_CHANNEL_DMA             /* clc37b.h */ 0x0000c37b
 #define TU102_DISP_WINDOW_IMM_CHANNEL_DMA             /* clc37b.h */ 0x0000c57b
+#define GA102_DISP_WINDOW_IMM_CHANNEL_DMA             /* clc37b.h */ 0x0000c67b
 #define NV50_DISP_BASE_CHANNEL_DMA                    /* cl507c.h */ 0x0000507c
 #define G82_DISP_BASE_CHANNEL_DMA                     /* cl507c.h */ 0x0000827c
 #define GP102_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000987d
 #define GV100_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000c37d
 #define TU102_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000c57d
+#define GA102_DISP_CORE_CHANNEL_DMA                   /* cl507d.h */ 0x0000c67d
 #define NV50_DISP_OVERLAY_CHANNEL_DMA                 /* cl507e.h */ 0x0000507e
 #define G82_DISP_OVERLAY_CHANNEL_DMA                  /* cl507e.h */ 0x0000827e
 #define GV100_DISP_WINDOW_CHANNEL_DMA                 /* clc37e.h */ 0x0000c37e
 #define TU102_DISP_WINDOW_CHANNEL_DMA                 /* clc37e.h */ 0x0000c57e
+#define GA102_DISP_WINDOW_CHANNEL_DMA                 /* clc37e.h */ 0x0000c67e
 #define NV50_TESLA                                                   0x00005097
 #define G82_TESLA                                                    0x00008297

drivers/gpu/drm/nouveau/include/nvkm/core/device.h+1−0

@@ -120,6 +120,7 @@ struct nvkm_device { · 119 unmodified lines
120	GP100 = 0x130,	120	GP100 = 0x130,
121	GV100 = 0x140,	121	GV100 = 0x140,
122	TU100 = 0x160,	122	TU100 = 0x160,
		123	GA100 = 0x170,
123	} card_type;	124	} card_type;
124	u32 chipset;	125	u32 chipset;
125	u8 chiprev;	126	u8 chiprev;

drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h+1−0

@@ -37,4 +37,5 @@ int gp100_disp_new(struct nvkm_device , int, struct nvkm_disp *); · 36 unmodified lines
37	int gp102_disp_new(struct nvkm_device , int, struct nvkm_disp *);	37	int gp102_disp_new(struct nvkm_device , int, struct nvkm_disp *);
38	int gv100_disp_new(struct nvkm_device , int, struct nvkm_disp *);	38	int gv100_disp_new(struct nvkm_device , int, struct nvkm_disp *);
39	int tu102_disp_new(struct nvkm_device , int, struct nvkm_disp *);	39	int tu102_disp_new(struct nvkm_device , int, struct nvkm_disp *);
		40	int ga102_disp_new(struct nvkm_device , int, struct nvkm_disp *);
40	#endif	41	#endif

drivers/gpu/drm/nouveau/include/nvkm/subdev/devinit.h+1−0

@@ -32,4 +32,5 @@ int gm107_devinit_new(struct nvkm_device , int, struct nvkm_devinit *); · 31 unmodified lines
32	int gm200_devinit_new(struct nvkm_device , int, struct nvkm_devinit *);	32	int gm200_devinit_new(struct nvkm_device , int, struct nvkm_devinit *);
33	int gv100_devinit_new(struct nvkm_device , int, struct nvkm_devinit *);	33	int gv100_devinit_new(struct nvkm_device , int, struct nvkm_devinit *);
34	int tu102_devinit_new(struct nvkm_device , int, struct nvkm_devinit *);	34	int tu102_devinit_new(struct nvkm_device , int, struct nvkm_devinit *);
		35	int ga100_devinit_new(struct nvkm_device , int, struct nvkm_devinit *);
35	#endif	36	#endif

drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h+2−0

@@ -86,6 +86,8 @@ int gp100_fb_new(struct nvkm_device , int, struct nvkm_fb *); · 85 unmodified lines
86	int gp102_fb_new(struct nvkm_device , int, struct nvkm_fb *);	86	int gp102_fb_new(struct nvkm_device , int, struct nvkm_fb *);
87	int gp10b_fb_new(struct nvkm_device , int, struct nvkm_fb *);	87	int gp10b_fb_new(struct nvkm_device , int, struct nvkm_fb *);
88	int gv100_fb_new(struct nvkm_device , int, struct nvkm_fb *);	88	int gv100_fb_new(struct nvkm_device , int, struct nvkm_fb *);
		89	int ga100_fb_new(struct nvkm_device , int, struct nvkm_fb *);
		90	int ga102_fb_new(struct nvkm_device , int, struct nvkm_fb *);
89		91
90	#include <subdev/bios.h>	92	#include <subdev/bios.h>
91	#include <subdev/bios/ramcfg.h>	93	#include <subdev/bios/ramcfg.h>

drivers/gpu/drm/nouveau/include/nvkm/subdev/gpio.h+1−0

@@ -37,4 +37,5 @@ int nv50_gpio_new(struct nvkm_device , int, struct nvkm_gpio *); · 36 unmodified lines
37	int g94_gpio_new(struct nvkm_device , int, struct nvkm_gpio *);	37	int g94_gpio_new(struct nvkm_device , int, struct nvkm_gpio *);
38	int gf119_gpio_new(struct nvkm_device , int, struct nvkm_gpio *);	38	int gf119_gpio_new(struct nvkm_device , int, struct nvkm_gpio *);
39	int gk104_gpio_new(struct nvkm_device , int, struct nvkm_gpio *);	39	int gk104_gpio_new(struct nvkm_device , int, struct nvkm_gpio *);
		40	int ga102_gpio_new(struct nvkm_device , int, struct nvkm_gpio *);
40	#endif	41	#endif

drivers/gpu/drm/nouveau/include/nvkm/subdev/i2c.h+1−0

@@ -92,6 +92,7 @@ int g94_i2c_new(struct nvkm_device , int, struct nvkm_i2c *); · 91 unmodified lines
92	int gf117_i2c_new(struct nvkm_device , int, struct nvkm_i2c *);	92	int gf117_i2c_new(struct nvkm_device , int, struct nvkm_i2c *);
93	int gf119_i2c_new(struct nvkm_device , int, struct nvkm_i2c *);	93	int gf119_i2c_new(struct nvkm_device , int, struct nvkm_i2c *);
94	int gk104_i2c_new(struct nvkm_device , int, struct nvkm_i2c *);	94	int gk104_i2c_new(struct nvkm_device , int, struct nvkm_i2c *);
		95	int gk110_i2c_new(struct nvkm_device , int, struct nvkm_i2c *);
95	int gm200_i2c_new(struct nvkm_device , int, struct nvkm_i2c *);	96	int gm200_i2c_new(struct nvkm_device , int, struct nvkm_i2c *);
96		97
97	static inline int	98	static inline int

drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h+1−0

@@ -32,4 +32,5 @@ int gk20a_mc_new(struct nvkm_device , int, struct nvkm_mc *); · 31 unmodified lines
32	int gp100_mc_new(struct nvkm_device , int, struct nvkm_mc *);	32	int gp100_mc_new(struct nvkm_device , int, struct nvkm_mc *);
33	int gp10b_mc_new(struct nvkm_device , int, struct nvkm_mc *);	33	int gp10b_mc_new(struct nvkm_device , int, struct nvkm_mc *);
34	int tu102_mc_new(struct nvkm_device , int, struct nvkm_mc *);	34	int tu102_mc_new(struct nvkm_device , int, struct nvkm_mc *);
		35	int ga100_mc_new(struct nvkm_device , int, struct nvkm_mc *);
35	#endif	36	#endif

drivers/gpu/drm/nouveau/nouveau_backlight.c+1−0

@@ -256,6 +256,7 @@ nouveau_backlight_init(struct drm_connector *connector) · 255 unmodified lines
256	case NV_DEVICE_INFO_V0_PASCAL:	256	case NV_DEVICE_INFO_V0_PASCAL:
257	case NV_DEVICE_INFO_V0_VOLTA:	257	case NV_DEVICE_INFO_V0_VOLTA:
258	case NV_DEVICE_INFO_V0_TURING:	258	case NV_DEVICE_INFO_V0_TURING:
		259	case NV_DEVICE_INFO_V0_AMPERE: //XXX: not confirmed
259	ret = nv50_backlight_init(nv_encoder, &props, &ops);	260	ret = nv50_backlight_init(nv_encoder, &props, &ops);
260	break;	261	break;
261	default:	262	default:

drivers/gpu/drm/nouveau/nvif/disp.c+1−0

@@ -35,6 +35,7 @@ nvif_disp_ctor(struct nvif_device device, const char name, s32 oclass, · 34 unmodified lines
35	struct nvif_disp *disp)	35	struct nvif_disp *disp)
36	{	36	{
37	static const struct nvif_mclass disps[] = {	37	static const struct nvif_mclass disps[] = {
		38	{ GA102_DISP, -1 },
38	{ TU102_DISP, -1 },	39	{ TU102_DISP, -1 },
39	{ GV100_DISP, -1 },	40	{ GV100_DISP, -1 },
40	{ GP102_DISP, -1 },	41	{ GP102_DISP, -1 },

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c+78−9

@@ -1815,7 +1815,7 @@ nvf0_chipset = { · 1814 unmodified lines
1815	.fb = gk110_fb_new,	1815	.fb = gk110_fb_new,
1816	.fuse = gf100_fuse_new,	1816	.fuse = gf100_fuse_new,
1817	.gpio = gk104_gpio_new,	1817	.gpio = gk104_gpio_new,
1818	.i2c = gk104_i2c_new,	1818	.i2c = gk110_i2c_new,
1819	.ibus = gk104_ibus_new,	1819	.ibus = gk104_ibus_new,
1820	.iccsense = gf100_iccsense_new,	1820	.iccsense = gf100_iccsense_new,
1821	.imem = nv50_instmem_new,	1821	.imem = nv50_instmem_new,
@@ -1853,7 +1853,7 @@ nvf1_chipset = { · 31 unmodified lines
1853	.fb = gk110_fb_new,	1853	.fb = gk110_fb_new,
1854	.fuse = gf100_fuse_new,	1854	.fuse = gf100_fuse_new,
1855	.gpio = gk104_gpio_new,	1855	.gpio = gk104_gpio_new,
1856	.i2c = gk104_i2c_new,	1856	.i2c = gk110_i2c_new,
1857	.ibus = gk104_ibus_new,	1857	.ibus = gk104_ibus_new,
1858	.iccsense = gf100_iccsense_new,	1858	.iccsense = gf100_iccsense_new,
1859	.imem = nv50_instmem_new,	1859	.imem = nv50_instmem_new,
@@ -1891,7 +1891,7 @@ nv106_chipset = { · 31 unmodified lines
1891	.fb = gk110_fb_new,	1891	.fb = gk110_fb_new,
1892	.fuse = gf100_fuse_new,	1892	.fuse = gf100_fuse_new,
1893	.gpio = gk104_gpio_new,	1893	.gpio = gk104_gpio_new,
1894	.i2c = gk104_i2c_new,	1894	.i2c = gk110_i2c_new,
1895	.ibus = gk104_ibus_new,	1895	.ibus = gk104_ibus_new,
1896	.iccsense = gf100_iccsense_new,	1896	.iccsense = gf100_iccsense_new,
1897	.imem = nv50_instmem_new,	1897	.imem = nv50_instmem_new,
@@ -1929,7 +1929,7 @@ nv108_chipset = { · 31 unmodified lines
1929	.fb = gk110_fb_new,	1929	.fb = gk110_fb_new,
1930	.fuse = gf100_fuse_new,	1930	.fuse = gf100_fuse_new,
1931	.gpio = gk104_gpio_new,	1931	.gpio = gk104_gpio_new,
1932	.i2c = gk104_i2c_new,	1932	.i2c = gk110_i2c_new,
1933	.ibus = gk104_ibus_new,	1933	.ibus = gk104_ibus_new,
1934	.iccsense = gf100_iccsense_new,	1934	.iccsense = gf100_iccsense_new,
1935	.imem = nv50_instmem_new,	1935	.imem = nv50_instmem_new,
@@ -1967,7 +1967,7 @@ nv117_chipset = { · 31 unmodified lines
1967	.fb = gm107_fb_new,	1967	.fb = gm107_fb_new,
1968	.fuse = gm107_fuse_new,	1968	.fuse = gm107_fuse_new,
1969	.gpio = gk104_gpio_new,	1969	.gpio = gk104_gpio_new,
1970	.i2c = gk104_i2c_new,	1970	.i2c = gk110_i2c_new,
1971	.ibus = gk104_ibus_new,	1971	.ibus = gk104_ibus_new,
1972	.iccsense = gf100_iccsense_new,	1972	.iccsense = gf100_iccsense_new,
1973	.imem = nv50_instmem_new,	1973	.imem = nv50_instmem_new,
@@ -2003,7 +2003,7 @@ nv118_chipset = { · 29 unmodified lines
2003	.fb = gm107_fb_new,	2003	.fb = gm107_fb_new,
2004	.fuse = gm107_fuse_new,	2004	.fuse = gm107_fuse_new,
2005	.gpio = gk104_gpio_new,	2005	.gpio = gk104_gpio_new,
2006	.i2c = gk104_i2c_new,	2006	.i2c = gk110_i2c_new,
2007	.ibus = gk104_ibus_new,	2007	.ibus = gk104_ibus_new,
2008	.iccsense = gf100_iccsense_new,	2008	.iccsense = gf100_iccsense_new,
2009	.imem = nv50_instmem_new,	2009	.imem = nv50_instmem_new,
@@ -2652,6 +2652,61 @@ nv168_chipset = { · 642 unmodified lines
2652	.sec2 = tu102_sec2_new,	2652	.sec2 = tu102_sec2_new,
2653	};	2653	};
2654		2654
		2655	static const struct nvkm_device_chip
		2656	nv170_chipset = {
		2657	.name = "GA100",
		2658	.bar = tu102_bar_new,
		2659	.bios = nvkm_bios_new,
		2660	.devinit = ga100_devinit_new,
		2661	.fb = ga100_fb_new,
		2662	.gpio = gk104_gpio_new,
		2663	.i2c = gm200_i2c_new,
		2664	.ibus = gm200_ibus_new,
		2665	.imem = nv50_instmem_new,
		2666	.mc = ga100_mc_new,
		2667	.mmu = tu102_mmu_new,
		2668	.pci = gp100_pci_new,
		2669	.timer = gk20a_timer_new,
		2670	};
		2671
		2672	static const struct nvkm_device_chip
		2673	nv172_chipset = {
		2674	.name = "GA102",
		2675	.bar = tu102_bar_new,
		2676	.bios = nvkm_bios_new,
		2677	.devinit = ga100_devinit_new,
		2678	.fb = ga102_fb_new,
		2679	.gpio = ga102_gpio_new,
		2680	.i2c = gm200_i2c_new,
		2681	.ibus = gm200_ibus_new,
		2682	.imem = nv50_instmem_new,
		2683	.mc = ga100_mc_new,
		2684	.mmu = tu102_mmu_new,
		2685	.pci = gp100_pci_new,
		2686	.timer = gk20a_timer_new,
		2687	.disp = ga102_disp_new,
		2688	.dma = gv100_dma_new,
		2689	};
		2690
		2691	static const struct nvkm_device_chip
		2692	nv174_chipset = {
		2693	.name = "GA104",
		2694	.bar = tu102_bar_new,
		2695	.bios = nvkm_bios_new,
		2696	.devinit = ga100_devinit_new,
		2697	.fb = ga102_fb_new,
		2698	.gpio = ga102_gpio_new,
		2699	.i2c = gm200_i2c_new,
		2700	.ibus = gm200_ibus_new,
		2701	.imem = nv50_instmem_new,
		2702	.mc = ga100_mc_new,
		2703	.mmu = tu102_mmu_new,
		2704	.pci = gp100_pci_new,
		2705	.timer = gk20a_timer_new,
		2706	.disp = ga102_disp_new,
		2707	.dma = gv100_dma_new,
		2708	};
		2709
2655	static int	2710	static int
2656	nvkm_device_event_ctor(struct nvkm_object object, void data, u32 size,	2711	nvkm_device_event_ctor(struct nvkm_object object, void data, u32 size,
2657	struct nvkm_notify *notify)	2712	struct nvkm_notify *notify)
@@ -3063,6 +3118,7 @@ nvkm_device_ctor(const struct nvkm_device_func *func, · 405 unmodified lines
3063	case 0x130: device->card_type = GP100; break;	3118	case 0x130: device->card_type = GP100; break;
3064	case 0x140: device->card_type = GV100; break;	3119	case 0x140: device->card_type = GV100; break;
3065	case 0x160: device->card_type = TU100; break;	3120	case 0x160: device->card_type = TU100; break;
		3121	case 0x170: device->card_type = GA100; break;
3066	default:	3122	default:
3067	break;	3123	break;
3068	}	3124	}
@@ -3160,10 +3216,23 @@ nvkm_device_ctor(const struct nvkm_device_func *func, · 91 unmodified lines
3160	case 0x166: device->chip = &nv166_chipset; break;	3216	case 0x166: device->chip = &nv166_chipset; break;
3161	case 0x167: device->chip = &nv167_chipset; break;	3217	case 0x167: device->chip = &nv167_chipset; break;
3162	case 0x168: device->chip = &nv168_chipset; break;	3218	case 0x168: device->chip = &nv168_chipset; break;
		3219	case 0x172: device->chip = &nv172_chipset; break;
		3220	case 0x174: device->chip = &nv174_chipset; break;
3163	default:	3221	default:
3164	nvdev_error(device, "unknown chipset (%08x)\n", boot0);	3222	if (nvkm_boolopt(device->cfgopt, "NvEnableUnsupportedChipsets", false)) {
3165	ret = -ENODEV;	3223	switch (device->chipset) {
3166	goto done;	3224	case 0x170: device->chip = &nv170_chipset; break;
		3225	default:
		3226	break;
		3227	}
		3228	}
		3229
		3230	if (!device->chip) {
		3231	nvdev_error(device, "unknown chipset (%08x)\n", boot0);
		3232	ret = -ENODEV;
		3233	goto done;
		3234	}
		3235	break;
3167	}	3236	}
3168		3237
3169	nvdev_info(device, "NVIDIA %s (%08x)\n",	3238	nvdev_info(device, "NVIDIA %s (%08x)\n",

drivers/gpu/drm/nouveau/nvkm/engine/device/user.c+1−0

@@ -176,6 +176,7 @@ nvkm_udevice_info(struct nvkm_udevice udev, void data, u32 size) · 175 unmodified lines
176	case GP100: args->v0.family = NV_DEVICE_INFO_V0_PASCAL; break;	176	case GP100: args->v0.family = NV_DEVICE_INFO_V0_PASCAL; break;
177	case GV100: args->v0.family = NV_DEVICE_INFO_V0_VOLTA; break;	177	case GV100: args->v0.family = NV_DEVICE_INFO_V0_VOLTA; break;
178	case TU100: args->v0.family = NV_DEVICE_INFO_V0_TURING; break;	178	case TU100: args->v0.family = NV_DEVICE_INFO_V0_TURING; break;
		179	case GA100: args->v0.family = NV_DEVICE_INFO_V0_AMPERE; break;
179	default:	180	default:
180	args->v0.family = 0;	181	args->v0.family = 0;
181	break;	182	break;

drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild+3−0

 nvkm-y += nvkm/engine/disp/gp102.o
 nvkm-y += nvkm/engine/disp/gv100.o
 nvkm-y += nvkm/engine/disp/tu102.o
+nvkm-y += nvkm/engine/disp/ga102.o
 nvkm-y += nvkm/engine/disp/vga.o
 nvkm-y += nvkm/engine/disp/head.o
 nvkm-y += nvkm/engine/disp/sorgp100.o
 nvkm-y += nvkm/engine/disp/sorgv100.o
 nvkm-y += nvkm/engine/disp/sortu102.o
+nvkm-y += nvkm/engine/disp/sorga102.o
 nvkm-y += nvkm/engine/disp/outp.o
 nvkm-y += nvkm/engine/disp/dp.o
 nvkm-y += nvkm/engine/disp/rootgp102.o
 nvkm-y += nvkm/engine/disp/rootgv100.o
 nvkm-y += nvkm/engine/disp/roottu102.o
+nvkm-y += nvkm/engine/disp/rootga102.o
 nvkm-y += nvkm/engine/disp/capsgv100.o

drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c+27−6

 #include <nvif/event.h>
+/* IED scripts are no longer used by UEFI/RM from Ampere, but have been updated for
+ * the x86 option ROM.  However, the relevant VBIOS table versions weren't modified,
+ * so we're unable to detect this in a nice way.
+ */
+#define AMPERE_IED_HACK(disp) ((disp)->engine.subdev.device->card_type >= GA100)
 struct lt_state {
 	struct nvkm_dp *dp;
 	u8  stat[6];
 		dp->dpcd[DPCD_RC02] &= ~DPCD_RC02_TPS3_SUPPORTED;
 	lt.pc2 = dp->dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED;
+	if (AMPERE_IED_HACK(disp) && (lnkcmp = lt.dp->info.script[0])) {
+		/* Execute BeforeLinkTraining script from DP Info table. */
+		while (ior->dp.bw < nvbios_rd08(bios, lnkcmp))
+			lnkcmp += 3;
+		lnkcmp = nvbios_rd16(bios, lnkcmp + 1);
+		nvbios_init(&dp->outp.disp->engine.subdev, lnkcmp,
+			init.outp = &dp->outp.info;
+			init.or   = ior->id;
+			init.link = ior->asy.link;
+		);
+	}
 	/* Set desired link configuration on the source. */
 	if ((lnkcmp = lt.dp->info.lnkcmp)) {
 		if (dp->version < 0x30) {
 		);
 	}
-	/* Execute BeforeLinkTraining script from DP Info table. */
+	if (!AMPERE_IED_HACK(dp->outp.disp)) {
-	nvbios_init(&dp->outp.disp->engine.subdev, dp->info.script[0],
+		/* Execute BeforeLinkTraining script from DP Info table. */
-		init.outp = &dp->outp.info;
+		nvbios_init(&dp->outp.disp->engine.subdev, dp->info.script[0],
-		init.or   = dp->outp.ior->id;
+			init.outp = &dp->outp.info;
-		init.link = dp->outp.ior->asy.link;
+			init.or   = dp->outp.ior->id;
-	);
+			init.link = dp->outp.ior->asy.link;
+		);
+	}
 }
 static const struct dp_rates {

drivers/gpu/drm/nouveau/nvkm/engine/disp/ga102.c+46−0

@@ -0,0 +1,46 @@
	1	/*
	2	* Copyright 2021 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*/
	22	#include "nv50.h"
	23	#include "head.h"
	24	#include "ior.h"
	25	#include "channv50.h"
	26	#include "rootnv50.h"
	27
	28	static const struct nv50_disp_func
	29	ga102_disp = {
	30	.init = tu102_disp_init,
	31	.fini = gv100_disp_fini,
	32	.intr = gv100_disp_intr,
	33	.uevent = &gv100_disp_chan_uevent,
	34	.super = gv100_disp_super,
	35	.root = &ga102_disp_root_oclass,
	36	.wndw = { .cnt = gv100_disp_wndw_cnt },
	37	.head = { .cnt = gv100_head_cnt, .new = gv100_head_new },
	38	.sor = { .cnt = gv100_sor_cnt, .new = ga102_sor_new },
	39	.ramht_size = 0x2000,
	40	};
	41
	42	int
	43	ga102_disp_new(struct nvkm_device device, int index, struct nvkm_disp *pdisp)
	44	{
	45	return nv50_disp_new_(&ga102_disp, device, index, pdisp);
	46	}

drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h+4−0

 void gv100_sor_dp_audio_sym(struct nvkm_ior *, int, u16, u32);
 void gv100_sor_dp_watermark(struct nvkm_ior *, int, u8);
+void tu102_sor_dp_vcpi(struct nvkm_ior *, int, u8, u8, u16, u16);
 void g84_hdmi_ctrl(struct nvkm_ior *, int, bool, u8, u8, u8 *, u8 , u8 *, u8);
 void gt215_hdmi_ctrl(struct nvkm_ior *, int, bool, u8, u8, u8 *, u8 , u8 *, u8);
 void gf119_hdmi_ctrl(struct nvkm_ior *, int, bool, u8, u8, u8 *, u8 , u8 *, u8);
 int gv100_sor_new(struct nvkm_disp *, int);
 int tu102_sor_new(struct nvkm_disp *, int);
+int ga102_sor_new(struct nvkm_disp *, int);
 #endif

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h+2−0

@@ -86,6 +86,8 @@ void gv100_disp_intr(struct nv50_disp *); · 85 unmodified lines
86	void gv100_disp_super(struct work_struct *);	86	void gv100_disp_super(struct work_struct *);
87	int gv100_disp_wndw_cnt(struct nvkm_disp , unsigned long );	87	int gv100_disp_wndw_cnt(struct nvkm_disp , unsigned long );
88		88
		89	int tu102_disp_init(struct nv50_disp *);
		90
89	void nv50_disp_dptmds_war_2(struct nv50_disp , struct dcb_output );	91	void nv50_disp_dptmds_war_2(struct nv50_disp , struct dcb_output );
90	void nv50_disp_dptmds_war_3(struct nv50_disp , struct dcb_output );	92	void nv50_disp_dptmds_war_3(struct nv50_disp , struct dcb_output );
91	void nv50_disp_update_sppll1(struct nv50_disp *);	93	void nv50_disp_update_sppll1(struct nv50_disp *);

drivers/gpu/drm/nouveau/nvkm/engine/disp/rootga102.c+52−0

@@ -0,0 +1,52 @@
	1	/*
	2	* Copyright 2021 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*/
	22	#include "rootnv50.h"
	23	#include "channv50.h"
	24
	25	#include <nvif/class.h>
	26
	27	static const struct nv50_disp_root_func
	28	ga102_disp_root = {
	29	.user = {
	30	{{-1,-1,GV100_DISP_CAPS }, gv100_disp_caps_new },
	31	{{0,0,GA102_DISP_CURSOR }, gv100_disp_curs_new },
	32	{{0,0,GA102_DISP_WINDOW_IMM_CHANNEL_DMA}, gv100_disp_wimm_new },
	33	{{0,0,GA102_DISP_CORE_CHANNEL_DMA }, gv100_disp_core_new },
	34	{{0,0,GA102_DISP_WINDOW_CHANNEL_DMA }, gv100_disp_wndw_new },
	35	{}
	36	},
	37	};
	38
	39	static int
	40	ga102_disp_root_new(struct nvkm_disp disp, const struct nvkm_oclass oclass,
	41	void data, u32 size, struct nvkm_object *pobject)
	42	{
	43	return nv50_disp_root_new_(&ga102_disp_root, disp, oclass, data, size, pobject);
	44	}
	45
	46	const struct nvkm_disp_oclass
	47	ga102_disp_root_oclass = {
	48	.base.oclass = GA102_DISP,
	49	.base.minver = -1,
	50	.base.maxver = -1,
	51	.ctor = ga102_disp_root_new,
	52	};

drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.h+1−0

@@ -41,4 +41,5 @@ extern const struct nvkm_disp_oclass gp100_disp_root_oclass; · 40 unmodified lines
41	extern const struct nvkm_disp_oclass gp102_disp_root_oclass;	41	extern const struct nvkm_disp_oclass gp102_disp_root_oclass;
42	extern const struct nvkm_disp_oclass gv100_disp_root_oclass;	42	extern const struct nvkm_disp_oclass gv100_disp_root_oclass;
43	extern const struct nvkm_disp_oclass tu102_disp_root_oclass;	43	extern const struct nvkm_disp_oclass tu102_disp_root_oclass;
		44	extern const struct nvkm_disp_oclass ga102_disp_root_oclass;
44	#endif	45	#endif

drivers/gpu/drm/nouveau/nvkm/engine/disp/sorga102.c+140−0

@@ -0,0 +1,140 @@
	1	/*
	2	* Copyright 2021 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*/
	22	#include "ior.h"
	23
	24	#include <subdev/timer.h>
	25
	26	static int
	27	ga102_sor_dp_links(struct nvkm_ior sor, struct nvkm_i2c_aux aux)
	28	{
	29	struct nvkm_device *device = sor->disp->engine.subdev.device;
	30	const u32 soff = nv50_ior_base(sor);
	31	const u32 loff = nv50_sor_link(sor);
	32	u32 dpctrl = 0x00000000;
	33	u32 clksor = 0x00000000;
	34
	35	switch (sor->dp.bw) {
	36	case 0x06: clksor \|= 0x00000000; break;
	37	case 0x0a: clksor \|= 0x00040000; break;
	38	case 0x14: clksor \|= 0x00080000; break;
	39	case 0x1e: clksor \|= 0x000c0000; break;
	40	default:
	41	WARN_ON(1);
	42	return -EINVAL;
	43	}
	44
	45	dpctrl \|= ((1 << sor->dp.nr) - 1) << 16;
	46	if (sor->dp.mst)
	47	dpctrl \|= 0x40000000;
	48	if (sor->dp.ef)
	49	dpctrl \|= 0x00004000;
	50
	51	nvkm_mask(device, 0x612300 + soff, 0x007c0000, clksor);
	52
	53	/XXX/
	54	nvkm_msec(device, 40, NVKM_DELAY);
	55	nvkm_mask(device, 0x612300 + soff, 0x00030000, 0x00010000);
	56	nvkm_mask(device, 0x61c10c + loff, 0x00000003, 0x00000001);
	57
	58	nvkm_mask(device, 0x61c10c + loff, 0x401f4000, dpctrl);
	59	return 0;
	60	}
	61
	62	static void
	63	ga102_sor_clock(struct nvkm_ior *sor)
	64	{
	65	struct nvkm_device *device = sor->disp->engine.subdev.device;
	66	u32 div2 = 0;
	67	if (sor->asy.proto == TMDS) {
	68	if (sor->tmds.high_speed)
	69	div2 = 1;
	70	}
	71	nvkm_wr32(device, 0x00ec08 + (sor->id * 0x10), 0x00000000);
	72	nvkm_wr32(device, 0x00ec04 + (sor->id * 0x10), div2);
	73	}
	74
	75	static const struct nvkm_ior_func
	76	ga102_sor_hda = {
	77	.route = {
	78	.get = gm200_sor_route_get,
	79	.set = gm200_sor_route_set,
	80	},
	81	.state = gv100_sor_state,
	82	.power = nv50_sor_power,
	83	.clock = ga102_sor_clock,
	84	.hdmi = {
	85	.ctrl = gv100_hdmi_ctrl,
	86	.scdc = gm200_hdmi_scdc,
	87	},
	88	.dp = {
	89	.lanes = { 0, 1, 2, 3 },
	90	.links = ga102_sor_dp_links,
	91	.power = g94_sor_dp_power,
	92	.pattern = gm107_sor_dp_pattern,
	93	.drive = gm200_sor_dp_drive,
	94	.vcpi = tu102_sor_dp_vcpi,
	95	.audio = gv100_sor_dp_audio,
	96	.audio_sym = gv100_sor_dp_audio_sym,
	97	.watermark = gv100_sor_dp_watermark,
	98	},
	99	.hda = {
	100	.hpd = gf119_hda_hpd,
	101	.eld = gf119_hda_eld,
	102	.device_entry = gv100_hda_device_entry,
	103	},
	104	};
	105
	106	static const struct nvkm_ior_func
	107	ga102_sor = {
	108	.route = {
	109	.get = gm200_sor_route_get,
	110	.set = gm200_sor_route_set,
	111	},
	112	.state = gv100_sor_state,
	113	.power = nv50_sor_power,
	114	.clock = ga102_sor_clock,
	115	.hdmi = {
	116	.ctrl = gv100_hdmi_ctrl,
	117	.scdc = gm200_hdmi_scdc,
	118	},
	119	.dp = {
	120	.lanes = { 0, 1, 2, 3 },
	121	.links = ga102_sor_dp_links,
	122	.power = g94_sor_dp_power,
	123	.pattern = gm107_sor_dp_pattern,
	124	.drive = gm200_sor_dp_drive,
	125	.vcpi = tu102_sor_dp_vcpi,
	126	.audio = gv100_sor_dp_audio,
	127	.audio_sym = gv100_sor_dp_audio_sym,
	128	.watermark = gv100_sor_dp_watermark,
	129	},
	130	};
	131
	132	int
	133	ga102_sor_new(struct nvkm_disp *disp, int id)
	134	{
	135	struct nvkm_device *device = disp->engine.subdev.device;
	136	u32 hda = nvkm_rd32(device, 0x08a15c);
	137	if (hda & BIT(id))
	138	return nvkm_ior_new_(&ga102_sor_hda, disp, SOR, id);
	139	return nvkm_ior_new_(&ga102_sor, disp, SOR, id);
	140	}

drivers/gpu/drm/nouveau/nvkm/engine/disp/sortu102.c+1−1

@@ -23,7 +23,7 @@ · 22 unmodified lines
23		23
24	#include <subdev/timer.h>	24	#include <subdev/timer.h>
25		25
26	static void	26	void
27	tu102_sor_dp_vcpi(struct nvkm_ior *sor, int head,	27	tu102_sor_dp_vcpi(struct nvkm_ior *sor, int head,
28	u8 slot, u8 slot_nr, u16 pbn, u16 aligned)	28	u8 slot, u8 slot_nr, u16 pbn, u16 aligned)
29	{	29	{

drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.c+1−1

@@ -28,7 +28,7 @@ · 27 unmodified lines
28	#include <core/gpuobj.h>	28	#include <core/gpuobj.h>
29	#include <subdev/timer.h>	29	#include <subdev/timer.h>
30		30
31	static int	31	int
32	tu102_disp_init(struct nv50_disp *disp)	32	tu102_disp_init(struct nv50_disp *disp)
33	{	33	{
34	struct nvkm_device *device = disp->base.engine.subdev.device;	34	struct nvkm_device *device = disp->base.engine.subdev.device;

drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c+1−1

@@ -75,7 +75,7 @@ shadow_image(struct nvkm_bios bios, int idx, u32 offset, struct shadow mthd) · 74 unmodified lines
75	nvkm_debug(subdev, "%08x: type %02x, %d bytes\n",	75	nvkm_debug(subdev, "%08x: type %02x, %d bytes\n",
76	image.base, image.type, image.size);	76	image.base, image.type, image.size);
77		77
78	if (!shadow_fetch(bios, mthd, image.size)) {	78	if (!shadow_fetch(bios, mthd, image.base + image.size)) {
79	nvkm_debug(subdev, "%08x: fetch failed\n", image.base);	79	nvkm_debug(subdev, "%08x: fetch failed\n", image.base);
80	return 0;	80	return 0;
81	}	81	}

drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowramin.c+3−0

 		return NULL;
 	/* we can't get the bios image pointer without PDISP */
+	if (device->card_type >= GA100)
+		addr = device->chipset == 0x170; /*XXX: find the fuse reg for this */
+	else
 	if (device->card_type >= GM100)
 		addr = nvkm_rd32(device, 0x021c04);
 	else

drivers/gpu/drm/nouveau/nvkm/subdev/devinit/Kbuild+1−0

@@ -15,3 +15,4 @@ nvkm-y += nvkm/subdev/devinit/gm107.o · 14 unmodified lines
15	nvkm-y += nvkm/subdev/devinit/gm200.o	15	nvkm-y += nvkm/subdev/devinit/gm200.o
16	nvkm-y += nvkm/subdev/devinit/gv100.o	16	nvkm-y += nvkm/subdev/devinit/gv100.o
17	nvkm-y += nvkm/subdev/devinit/tu102.o	17	nvkm-y += nvkm/subdev/devinit/tu102.o
		18	nvkm-y += nvkm/subdev/devinit/ga100.o

drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ga100.c+76−0

@@ -0,0 +1,76 @@
	1	/*
	2	* Copyright 2021 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*/
	22	#include "nv50.h"
	23
	24	#include <subdev/bios.h>
	25	#include <subdev/bios/pll.h>
	26	#include <subdev/clk/pll.h>
	27
	28	static int
	29	ga100_devinit_pll_set(struct nvkm_devinit *init, u32 type, u32 freq)
	30	{
	31	struct nvkm_subdev *subdev = &init->subdev;
	32	struct nvkm_device *device = subdev->device;
	33	struct nvbios_pll info;
	34	int head = type - PLL_VPLL0;
	35	int N, fN, M, P;
	36	int ret;
	37
	38	ret = nvbios_pll_parse(device->bios, type, &info);
	39	if (ret)
	40	return ret;
	41
	42	ret = gt215_pll_calc(subdev, &info, freq, &N, &fN, &M, &P);
	43	if (ret < 0)
	44	return ret;
	45
	46	switch (info.type) {
	47	case PLL_VPLL0:
	48	case PLL_VPLL1:
	49	case PLL_VPLL2:
	50	case PLL_VPLL3:
	51	nvkm_wr32(device, 0x00ef00 + (head * 0x40), 0x02080004);
	52	nvkm_wr32(device, 0x00ef18 + (head * 0x40), (N << 16) \| fN);
	53	nvkm_wr32(device, 0x00ef04 + (head * 0x40), (P << 16) \| M);
	54	nvkm_wr32(device, 0x00e9c0 + (head * 0x04), 0x00000001);
	55	break;
	56	default:
	57	nvkm_warn(subdev, "%08x/%dKhz unimplemented\n", type, freq);
	58	ret = -EINVAL;
	59	break;
	60	}
	61
	62	return ret;
	63	}
	64
	65	static const struct nvkm_devinit_func
	66	ga100_devinit = {
	67	.init = nv50_devinit_init,
	68	.post = tu102_devinit_post,
	69	.pll_set = ga100_devinit_pll_set,
	70	};
	71
	72	int
	73	ga100_devinit_new(struct nvkm_device device, int index, struct nvkm_devinit *pinit)
	74	{
	75	return nv50_devinit_new_(&ga100_devinit, device, index, pinit);
	76	}

drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h+1−0

@@ -19,4 +19,5 @@ void nvkm_devinit_ctor(const struct nvkm_devinit_func , struct nvkm_device , · 18 unmodified lines
19	int index, struct nvkm_devinit *);	19	int index, struct nvkm_devinit *);
20		20
21	int nv04_devinit_post(struct nvkm_devinit *, bool);	21	int nv04_devinit_post(struct nvkm_devinit *, bool);
		22	int tu102_devinit_post(struct nvkm_devinit *, bool);
22	#endif	23	#endif

drivers/gpu/drm/nouveau/nvkm/subdev/devinit/tu102.c+1−1

@@ -65,7 +65,7 @@ tu102_devinit_pll_set(struct nvkm_devinit *init, u32 type, u32 freq) · 64 unmodified lines
65	return ret;	65	return ret;
66	}	66	}
67		67
68	static int	68	int
69	tu102_devinit_post(struct nvkm_devinit *base, bool post)	69	tu102_devinit_post(struct nvkm_devinit *base, bool post)
70	{	70	{
71	struct nv50_devinit *init = nv50_devinit(base);	71	struct nv50_devinit *init = nv50_devinit(base);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/Kbuild+3−0

 nvkm-y += nvkm/subdev/fb/gp102.o
 nvkm-y += nvkm/subdev/fb/gp10b.o
 nvkm-y += nvkm/subdev/fb/gv100.o
+nvkm-y += nvkm/subdev/fb/ga100.o
+nvkm-y += nvkm/subdev/fb/ga102.o
 nvkm-y += nvkm/subdev/fb/ram.o
 nvkm-y += nvkm/subdev/fb/ramnv04.o
 nvkm-y += nvkm/subdev/fb/ramgm107.o
 nvkm-y += nvkm/subdev/fb/ramgm200.o
 nvkm-y += nvkm/subdev/fb/ramgp100.o
+nvkm-y += nvkm/subdev/fb/ramga102.o
 nvkm-y += nvkm/subdev/fb/sddr2.o
 nvkm-y += nvkm/subdev/fb/sddr3.o
 nvkm-y += nvkm/subdev/fb/gddr3.o

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ga100.c+40−0

@@ -0,0 +1,40 @@
	1	/*
	2	* Copyright 2021 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*/
	22	#include "gf100.h"
	23	#include "ram.h"
	24
	25	static const struct nvkm_fb_func
	26	ga100_fb = {
	27	.dtor = gf100_fb_dtor,
	28	.oneinit = gf100_fb_oneinit,
	29	.init = gp100_fb_init,
	30	.init_page = gv100_fb_init_page,
	31	.init_unkn = gp100_fb_init_unkn,
	32	.ram_new = gp100_ram_new,
	33	.default_bigpage = 16,
	34	};
	35
	36	int
	37	ga100_fb_new(struct nvkm_device device, int index, struct nvkm_fb *pfb)
	38	{
	39	return gp102_fb_new_(&ga100_fb, device, index, pfb);
	40	}

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ga102.c+40−0

@@ -0,0 +1,40 @@
	1	/*
	2	* Copyright 2021 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*/
	22	#include "gf100.h"
	23	#include "ram.h"
	24
	25	static const struct nvkm_fb_func
	26	ga102_fb = {
	27	.dtor = gf100_fb_dtor,
	28	.oneinit = gf100_fb_oneinit,
	29	.init = gp100_fb_init,
	30	.init_page = gv100_fb_init_page,
	31	.init_unkn = gp100_fb_init_unkn,
	32	.ram_new = ga102_ram_new,
	33	.default_bigpage = 16,
	34	};
	35
	36	int
	37	ga102_fb_new(struct nvkm_device device, int index, struct nvkm_fb *pfb)
	38	{
	39	return gp102_fb_new_(&ga102_fb, device, index, pfb);
	40	}

drivers/gpu/drm/nouveau/nvkm/subdev/fb/gv100.c+1−1

@@ -22,7 +22,7 @@ · 21 unmodified lines
22	#include "gf100.h"	22	#include "gf100.h"
23	#include "ram.h"	23	#include "ram.h"
24		24
25	static int	25	int
26	gv100_fb_init_page(struct nvkm_fb *fb)	26	gv100_fb_init_page(struct nvkm_fb *fb)
27	{	27	{
28	return (fb->page == 16) ? 0 : -EINVAL;	28	return (fb->page == 16) ? 0 : -EINVAL;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h+2−0

@@ -82,4 +82,6 @@ int gp102_fb_new_(const struct nvkm_fb_func , struct nvkm_device , int, · 81 unmodified lines
82	struct nvkm_fb **);	82	struct nvkm_fb **);
83	bool gp102_fb_vpr_scrub_required(struct nvkm_fb *);	83	bool gp102_fb_vpr_scrub_required(struct nvkm_fb *);
84	int gp102_fb_vpr_scrub(struct nvkm_fb *);	84	int gp102_fb_vpr_scrub(struct nvkm_fb *);
		85
		86	int gv100_fb_init_page(struct nvkm_fb *);
85	#endif	87	#endif

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.h+1−0

@@ -70,4 +70,5 @@ int gk104_ram_new(struct nvkm_fb , struct nvkm_ram *); · 69 unmodified lines
70	int gm107_ram_new(struct nvkm_fb , struct nvkm_ram *);	70	int gm107_ram_new(struct nvkm_fb , struct nvkm_ram *);
71	int gm200_ram_new(struct nvkm_fb , struct nvkm_ram *);	71	int gm200_ram_new(struct nvkm_fb , struct nvkm_ram *);
72	int gp100_ram_new(struct nvkm_fb , struct nvkm_ram *);	72	int gp100_ram_new(struct nvkm_fb , struct nvkm_ram *);
		73	int ga102_ram_new(struct nvkm_fb , struct nvkm_ram *);
73	#endif	74	#endif

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramga102.c+40−0

@@ -0,0 +1,40 @@
	1	/*
	2	* Copyright 2021 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*/
	22	#include "ram.h"
	23
	24	#include <subdev/bios.h>
	25	#include <subdev/bios/init.h>
	26	#include <subdev/bios/rammap.h>
	27
	28	static const struct nvkm_ram_func
	29	ga102_ram = {
	30	};
	31
	32	int
	33	ga102_ram_new(struct nvkm_fb fb, struct nvkm_ram *pram)
	34	{
	35	struct nvkm_device *device = fb->subdev.device;
	36	enum nvkm_ram_type type = nvkm_fb_bios_memtype(device->bios);
	37	u32 size = nvkm_rd32(device, 0x1183a4);
	38
	39	return nvkm_ram_new_(&ga102_ram, fb, type, (u64)size << 20, pram);
	40	}

drivers/gpu/drm/nouveau/nvkm/subdev/gpio/Kbuild+1−0

@@ -5,3 +5,4 @@ nvkm-y += nvkm/subdev/gpio/nv50.o · 4 unmodified lines
5	nvkm-y += nvkm/subdev/gpio/g94.o	5	nvkm-y += nvkm/subdev/gpio/g94.o
6	nvkm-y += nvkm/subdev/gpio/gf119.o	6	nvkm-y += nvkm/subdev/gpio/gf119.o
7	nvkm-y += nvkm/subdev/gpio/gk104.o	7	nvkm-y += nvkm/subdev/gpio/gk104.o
		8	nvkm-y += nvkm/subdev/gpio/ga102.o

drivers/gpu/drm/nouveau/nvkm/subdev/gpio/ga102.c+118−0

@@ -0,0 +1,118 @@
	1	/*
	2	* Copyright 2021 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*/
	22	#include "priv.h"
	23
	24	static void
	25	ga102_gpio_reset(struct nvkm_gpio *gpio, u8 match)
	26	{
	27	struct nvkm_device *device = gpio->subdev.device;
	28	struct nvkm_bios *bios = device->bios;
	29	u8 ver, len;
	30	u16 entry;
	31	int ent = -1;
	32
	33	while ((entry = dcb_gpio_entry(bios, 0, ++ent, &ver, &len))) {
	34	u32 data = nvbios_rd32(bios, entry);
	35	u8 line = (data & 0x0000003f);
	36	u8 defs = !!(data & 0x00000080);
	37	u8 func = (data & 0x0000ff00) >> 8;
	38	u8 unk0 = (data & 0x00ff0000) >> 16;
	39	u8 unk1 = (data & 0x1f000000) >> 24;
	40
	41	if ( func == DCB_GPIO_UNUSED \|\|
	42	(match != DCB_GPIO_UNUSED && match != func))
	43	continue;
	44
	45	nvkm_gpio_set(gpio, 0, func, line, defs);
	46
	47	nvkm_mask(device, 0x021200 + (line * 4), 0xff, unk0);
	48	if (unk1--)
	49	nvkm_mask(device, 0x00d740 + (unk1 * 4), 0xff, line);
	50	}
	51	}
	52
	53	static int
	54	ga102_gpio_drive(struct nvkm_gpio *gpio, int line, int dir, int out)
	55	{
	56	struct nvkm_device *device = gpio->subdev.device;
	57	u32 data = ((dir ^ 1) << 13) \| (out << 12);
	58	nvkm_mask(device, 0x021200 + (line * 4), 0x00003000, data);
	59	nvkm_mask(device, 0x00d604, 0x00000001, 0x00000001); /* update? */
	60	return 0;
	61	}
	62
	63	static int
	64	ga102_gpio_sense(struct nvkm_gpio *gpio, int line)
	65	{
	66	struct nvkm_device *device = gpio->subdev.device;
	67	return !!(nvkm_rd32(device, 0x021200 + (line * 4)) & 0x00004000);
	68	}
	69
	70	static void
	71	ga102_gpio_intr_stat(struct nvkm_gpio gpio, u32 hi, u32 *lo)
	72	{
	73	struct nvkm_device *device = gpio->subdev.device;
	74	u32 intr0 = nvkm_rd32(device, 0x021640);
	75	u32 intr1 = nvkm_rd32(device, 0x02164c);
	76	u32 stat0 = nvkm_rd32(device, 0x021648) & intr0;
	77	u32 stat1 = nvkm_rd32(device, 0x021654) & intr1;
	78	*lo = (stat1 & 0xffff0000) \| (stat0 >> 16);
	79	*hi = (stat1 << 16) \| (stat0 & 0x0000ffff);
	80	nvkm_wr32(device, 0x021640, intr0);
	81	nvkm_wr32(device, 0x02164c, intr1);
	82	}
	83
	84	static void
	85	ga102_gpio_intr_mask(struct nvkm_gpio *gpio, u32 type, u32 mask, u32 data)
	86	{
	87	struct nvkm_device *device = gpio->subdev.device;
	88	u32 inte0 = nvkm_rd32(device, 0x021648);
	89	u32 inte1 = nvkm_rd32(device, 0x021654);
	90	if (type & NVKM_GPIO_LO)
	91	inte0 = (inte0 & ~(mask << 16)) \| (data << 16);
	92	if (type & NVKM_GPIO_HI)
	93	inte0 = (inte0 & ~(mask & 0xffff)) \| (data & 0xffff);
	94	mask >>= 16;
	95	data >>= 16;
	96	if (type & NVKM_GPIO_LO)
	97	inte1 = (inte1 & ~(mask << 16)) \| (data << 16);
	98	if (type & NVKM_GPIO_HI)
	99	inte1 = (inte1 & ~mask) \| data;
	100	nvkm_wr32(device, 0x021648, inte0);
	101	nvkm_wr32(device, 0x021654, inte1);
	102	}
	103
	104	static const struct nvkm_gpio_func
	105	ga102_gpio = {
	106	.lines = 32,
	107	.intr_stat = ga102_gpio_intr_stat,
	108	.intr_mask = ga102_gpio_intr_mask,
	109	.drive = ga102_gpio_drive,
	110	.sense = ga102_gpio_sense,
	111	.reset = ga102_gpio_reset,
	112	};
	113
	114	int
	115	ga102_gpio_new(struct nvkm_device device, int index, struct nvkm_gpio *pgpio)
	116	{
	117	return nvkm_gpio_new_(&ga102_gpio, device, index, pgpio);
	118	}

drivers/gpu/drm/nouveau/nvkm/subdev/i2c/Kbuild+1−0

@@ -7,6 +7,7 @@ nvkm-y += nvkm/subdev/i2c/g94.o · 6 unmodified lines
7	nvkm-y += nvkm/subdev/i2c/gf117.o	7	nvkm-y += nvkm/subdev/i2c/gf117.o
8	nvkm-y += nvkm/subdev/i2c/gf119.o	8	nvkm-y += nvkm/subdev/i2c/gf119.o
9	nvkm-y += nvkm/subdev/i2c/gk104.o	9	nvkm-y += nvkm/subdev/i2c/gk104.o
		10	nvkm-y += nvkm/subdev/i2c/gk110.o
10	nvkm-y += nvkm/subdev/i2c/gm200.o	11	nvkm-y += nvkm/subdev/i2c/gm200.o
11		12
12	nvkm-y += nvkm/subdev/i2c/pad.o	13	nvkm-y += nvkm/subdev/i2c/pad.o

drivers/gpu/drm/nouveau/nvkm/subdev/i2c/aux.h+7−0

@@ -3,6 +3,13 @@ · 2 unmodified lines
3	#define __NVKM_I2C_AUX_H__	3	#define __NVKM_I2C_AUX_H__
4	#include "pad.h"	4	#include "pad.h"
5		5
		6	static inline void
		7	nvkm_i2c_aux_autodpcd(struct nvkm_i2c *i2c, int aux, bool enable)
		8	{
		9	if (i2c->func->aux_autodpcd)
		10	i2c->func->aux_autodpcd(i2c, aux, false);
		11	}
		12
6	struct nvkm_i2c_aux_func {	13	struct nvkm_i2c_aux_func {
7	bool address_only;	14	bool address_only;
8	int (xfer)(struct nvkm_i2c_aux , bool retry, u8 type,	15	int (xfer)(struct nvkm_i2c_aux , bool retry, u8 type,

drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.c+7−3

@@ -77,7 +77,8 @@ g94_i2c_aux_xfer(struct nvkm_i2c_aux *obj, bool retry, · 76 unmodified lines
77	u8 type, u32 addr, u8 data, u8 size)	77	u8 type, u32 addr, u8 data, u8 size)
78	{	78	{
79	struct g94_i2c_aux *aux = g94_i2c_aux(obj);	79	struct g94_i2c_aux *aux = g94_i2c_aux(obj);
80	struct nvkm_device *device = aux->base.pad->i2c->subdev.device;	80	struct nvkm_i2c *i2c = aux->base.pad->i2c;
		81	struct nvkm_device *device = i2c->subdev.device;
81	const u32 base = aux->ch * 0x50;	82	const u32 base = aux->ch * 0x50;
82	u32 ctrl, stat, timeout, retries = 0;	83	u32 ctrl, stat, timeout, retries = 0;
83	u32 xbuf[4] = {};	84	u32 xbuf[4] = {};
@@ -96,6 +97,8 @@ g94_i2c_aux_xfer(struct nvkm_i2c_aux *obj, bool retry, · 12 unmodified lines
96	goto out;	97	goto out;
97	}	98	}
98		99
		100	nvkm_i2c_aux_autodpcd(i2c, aux->ch, false);
		101
99	if (!(type & 1)) {	102	if (!(type & 1)) {
100	memcpy(xbuf, data, *size);	103	memcpy(xbuf, data, *size);
101	for (i = 0; i < 16; i += 4) {	104	for (i = 0; i < 16; i += 4) {
@@ -128,7 +131,7 @@ g94_i2c_aux_xfer(struct nvkm_i2c_aux *obj, bool retry, · 26 unmodified lines
128	if (!timeout--) {	131	if (!timeout--) {
129	AUX_ERR(&aux->base, "timeout %08x", ctrl);	132	AUX_ERR(&aux->base, "timeout %08x", ctrl);
130	ret = -EIO;	133	ret = -EIO;
131	goto out;	134	goto out_err;
132	}	135	}
133	} while (ctrl & 0x00010000);	136	} while (ctrl & 0x00010000);
134	ret = 0;	137	ret = 0;
@@ -154,7 +157,8 @@ g94_i2c_aux_xfer(struct nvkm_i2c_aux *obj, bool retry, · 19 unmodified lines
154	memcpy(data, xbuf, *size);	157	memcpy(data, xbuf, *size);
155	*size = stat & 0x0000001f;	158	*size = stat & 0x0000001f;
156	}	159	}
157		160	out_err:
		161	nvkm_i2c_aux_autodpcd(i2c, aux->ch, true);
158	out:	162	out:
159	g94_i2c_aux_fini(aux);	163	g94_i2c_aux_fini(aux);
160	return ret < 0 ? ret : (stat & 0x000f0000) >> 16;	164	return ret < 0 ? ret : (stat & 0x000f0000) >> 16;

drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm200.c+11−6

 gm200_i2c_aux_fini(struct gm200_i2c_aux *aux)
 {
 	struct nvkm_device *device = aux->base.pad->i2c->subdev.device;
-	nvkm_mask(device, 0x00d954 + (aux->ch * 0x50), 0x00310000, 0x00000000);
+	nvkm_mask(device, 0x00d954 + (aux->ch * 0x50), 0x00710000, 0x00000000);
 }
 static int
 			AUX_ERR(&aux->base, "begin idle timeout %08x", ctrl);
 			return -EBUSY;
 		}
-	} while (ctrl & 0x03010000);
+	} while (ctrl & 0x07010000);
 	/* set some magic, and wait up to 1ms for it to appear */
-	nvkm_mask(device, 0x00d954 + (aux->ch * 0x50), 0x00300000, ureq);
+	nvkm_mask(device, 0x00d954 + (aux->ch * 0x50), 0x00700000, ureq);
 	timeout = 1000;
 	do {
 		ctrl = nvkm_rd32(device, 0x00d954 + (aux->ch * 0x50));
 			gm200_i2c_aux_fini(aux);
 			return -EBUSY;
 		}
-	} while ((ctrl & 0x03000000) != urep);
+	} while ((ctrl & 0x07000000) != urep);
 	return 0;
 }
 		   u8 type, u32 addr, u8 *data, u8 *size)
 {
 	struct gm200_i2c_aux *aux = gm200_i2c_aux(obj);
-	struct nvkm_device *device = aux->base.pad->i2c->subdev.device;
+	struct nvkm_i2c *i2c = aux->base.pad->i2c;
+	struct nvkm_device *device = i2c->subdev.device;
 	const u32 base = aux->ch * 0x50;
 	u32 ctrl, stat, timeout, retries = 0;
 	u32 xbuf[4] = {};
 		goto out;
 	}
+	nvkm_i2c_aux_autodpcd(i2c, aux->ch, false);
 	if (!(type & 1)) {
 		memcpy(xbuf, data, *size);
 		for (i = 0; i < 16; i += 4) {
 			if (!timeout--) {
 				AUX_ERR(&aux->base, "timeout %08x", ctrl);
 				ret = -EIO;
-				goto out;
+				goto out_err;
 			}
 		} while (ctrl & 0x00010000);
 		ret = 0;
 		*size = stat & 0x0000001f;
 	}
+out_err:
+	nvkm_i2c_aux_autodpcd(i2c, aux->ch, true);
 out:
 	gm200_i2c_aux_fini(aux);
 	return ret < 0 ? ret : (stat & 0x000f0000) >> 16;

drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk110.c+45−0

@@ -0,0 +1,45 @@
	1	/*
	2	* Copyright 2021 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*/
	22	#include "priv.h"
	23	#include "pad.h"
	24
	25	static void
	26	gk110_aux_autodpcd(struct nvkm_i2c *i2c, int aux, bool enable)
	27	{
	28	nvkm_mask(i2c->subdev.device, 0x00e4f8 + (aux * 0x50), 0x00010000, enable << 16);
	29	}
	30
	31	static const struct nvkm_i2c_func
	32	gk110_i2c = {
	33	.pad_x_new = gf119_i2c_pad_x_new,
	34	.pad_s_new = gf119_i2c_pad_s_new,
	35	.aux = 4,
	36	.aux_stat = gk104_aux_stat,
	37	.aux_mask = gk104_aux_mask,
	38	.aux_autodpcd = gk110_aux_autodpcd,
	39	};
	40
	41	int
	42	gk110_i2c_new(struct nvkm_device device, int index, struct nvkm_i2c *pi2c)
	43	{
	44	return nvkm_i2c_new_(&gk110_i2c, device, index, pi2c);
	45	}

drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gm200.c+7−0

 #include "priv.h"
 #include "pad.h"
+static void
+gm200_aux_autodpcd(struct nvkm_i2c *i2c, int aux, bool enable)
+{
+	nvkm_mask(i2c->subdev.device, 0x00d968 + (aux * 0x50), 0x00010000, enable << 16);
+}
 static const struct nvkm_i2c_func
 gm200_i2c = {
 	.pad_x_new = gf119_i2c_pad_x_new,
 	.aux = 8,
 	.aux_stat = gk104_aux_stat,
 	.aux_mask = gk104_aux_mask,
+	.aux_autodpcd = gm200_aux_autodpcd,
 };
 int

drivers/gpu/drm/nouveau/nvkm/subdev/i2c/pad.h+1−1

@@ -1,7 +1,7 @@
1	/* SPDX-License-Identifier: MIT */	1	/* SPDX-License-Identifier: MIT */
2	#ifndef __NVKM_I2C_PAD_H__	2	#ifndef __NVKM_I2C_PAD_H__
3	#define __NVKM_I2C_PAD_H__	3	#define __NVKM_I2C_PAD_H__
4	#include <subdev/i2c.h>	4	#include "priv.h"
5		5
6	struct nvkm_i2c_pad {	6	struct nvkm_i2c_pad {
7	const struct nvkm_i2c_pad_func *func;	7	const struct nvkm_i2c_pad_func *func;

drivers/gpu/drm/nouveau/nvkm/subdev/i2c/priv.h+4−0

 	/* mask on/off interrupt types for a given set of auxch
 	 */
 	void (*aux_mask)(struct nvkm_i2c *, u32, u32, u32);
+	/* enable/disable HW-initiated DPCD reads
+	 */
+	void (*aux_autodpcd)(struct nvkm_i2c *, int aux, bool enable);
 };
 void g94_aux_stat(struct nvkm_i2c *, u32 *, u32 *, u32 *, u32 *);

drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gf100.c+7−3

  * Authors: Ben Skeggs
  */
 #include "priv.h"
+#include <subdev/timer.h>
 static void
 gf100_ibus_intr_hub(struct nvkm_subdev *ibus, int i)
 	u32 data = nvkm_rd32(device, 0x122124 + (i * 0x0400));
 	u32 stat = nvkm_rd32(device, 0x122128 + (i * 0x0400));
 	nvkm_debug(ibus, "HUB%d: %06x %08x (%08x)\n", i, addr, data, stat);
-	nvkm_mask(device, 0x122128 + (i * 0x0400), 0x00000200, 0x00000000);
 }
 static void
 	u32 data = nvkm_rd32(device, 0x124124 + (i * 0x0400));
 	u32 stat = nvkm_rd32(device, 0x124128 + (i * 0x0400));
 	nvkm_debug(ibus, "ROP%d: %06x %08x (%08x)\n", i, addr, data, stat);
-	nvkm_mask(device, 0x124128 + (i * 0x0400), 0x00000200, 0x00000000);
 }
 static void
 	u32 data = nvkm_rd32(device, 0x128124 + (i * 0x0400));
 	u32 stat = nvkm_rd32(device, 0x128128 + (i * 0x0400));
 	nvkm_debug(ibus, "GPC%d: %06x %08x (%08x)\n", i, addr, data, stat);
-	nvkm_mask(device, 0x128128 + (i * 0x0400), 0x00000200, 0x00000000);
 }
 void
 			intr1 &= ~stat;
 		}
 	}
+	nvkm_mask(device, 0x121c4c, 0x0000003f, 0x00000002);
+	nvkm_msec(device, 2000,
+		if (!(nvkm_rd32(device, 0x121c4c) & 0x0000003f))
+			break;
+	);
 }
 static int

drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gk104.c+7−3

  * Authors: Ben Skeggs
  */
 #include "priv.h"
+#include <subdev/timer.h>
 static void
 gk104_ibus_intr_hub(struct nvkm_subdev *ibus, int i)
 	u32 data = nvkm_rd32(device, 0x122124 + (i * 0x0800));
 	u32 stat = nvkm_rd32(device, 0x122128 + (i * 0x0800));
 	nvkm_debug(ibus, "HUB%d: %06x %08x (%08x)\n", i, addr, data, stat);
-	nvkm_mask(device, 0x122128 + (i * 0x0800), 0x00000200, 0x00000000);
 }
 static void
 	u32 data = nvkm_rd32(device, 0x124124 + (i * 0x0800));
 	u32 stat = nvkm_rd32(device, 0x124128 + (i * 0x0800));
 	nvkm_debug(ibus, "ROP%d: %06x %08x (%08x)\n", i, addr, data, stat);
-	nvkm_mask(device, 0x124128 + (i * 0x0800), 0x00000200, 0x00000000);
 }
 static void
 	u32 data = nvkm_rd32(device, 0x128124 + (i * 0x0800));
 	u32 stat = nvkm_rd32(device, 0x128128 + (i * 0x0800));
 	nvkm_debug(ibus, "GPC%d: %06x %08x (%08x)\n", i, addr, data, stat);
-	nvkm_mask(device, 0x128128 + (i * 0x0800), 0x00000200, 0x00000000);
 }
 void
 			intr1 &= ~stat;
 		}
 	}
+	nvkm_mask(device, 0x12004c, 0x0000003f, 0x00000002);
+	nvkm_msec(device, 2000,
+		if (!(nvkm_rd32(device, 0x12004c) & 0x0000003f))
+			break;
+	);
 }
 static int

drivers/gpu/drm/nouveau/nvkm/subdev/mc/Kbuild+1−0

@@ -14,3 +14,4 @@ nvkm-y += nvkm/subdev/mc/gk20a.o · 13 unmodified lines
14	nvkm-y += nvkm/subdev/mc/gp100.o	14	nvkm-y += nvkm/subdev/mc/gp100.o
15	nvkm-y += nvkm/subdev/mc/gp10b.o	15	nvkm-y += nvkm/subdev/mc/gp10b.o
16	nvkm-y += nvkm/subdev/mc/tu102.o	16	nvkm-y += nvkm/subdev/mc/tu102.o
		17	nvkm-y += nvkm/subdev/mc/ga100.o

drivers/gpu/drm/nouveau/nvkm/subdev/mc/ga100.c+74−0

@@ -0,0 +1,74 @@
	1	/*
	2	* Copyright 2021 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*/
	22	#include "priv.h"
	23
	24	static void
	25	ga100_mc_intr_unarm(struct nvkm_mc *mc)
	26	{
	27	nvkm_wr32(mc->subdev.device, 0xb81610, 0x00000004);
	28	}
	29
	30	static void
	31	ga100_mc_intr_rearm(struct nvkm_mc *mc)
	32	{
	33	nvkm_wr32(mc->subdev.device, 0xb81608, 0x00000004);
	34	}
	35
	36	static void
	37	ga100_mc_intr_mask(struct nvkm_mc *mc, u32 mask, u32 intr)
	38	{
	39	nvkm_wr32(mc->subdev.device, 0xb81210, mask & intr );
	40	nvkm_wr32(mc->subdev.device, 0xb81410, mask & ~(mask & intr));
	41	}
	42
	43	static u32
	44	ga100_mc_intr_stat(struct nvkm_mc *mc)
	45	{
	46	u32 intr_top = nvkm_rd32(mc->subdev.device, 0xb81600), intr = 0x00000000;
	47	if (intr_top & 0x00000004)
	48	intr = nvkm_mask(mc->subdev.device, 0xb81010, 0x00000000, 0x00000000);
	49	return intr;
	50	}
	51
	52	static void
	53	ga100_mc_init(struct nvkm_mc *mc)
	54	{
	55	nv50_mc_init(mc);
	56	nvkm_wr32(mc->subdev.device, 0xb81210, 0xffffffff);
	57	}
	58
	59	static const struct nvkm_mc_func
	60	ga100_mc = {
	61	.init = ga100_mc_init,
	62	.intr = gp100_mc_intr,
	63	.intr_unarm = ga100_mc_intr_unarm,
	64	.intr_rearm = ga100_mc_intr_rearm,
	65	.intr_mask = ga100_mc_intr_mask,
	66	.intr_stat = ga100_mc_intr_stat,
	67	.reset = gk104_mc_reset,
	68	};
	69
	70	int
	71	ga100_mc_new(struct nvkm_device device, int index, struct nvkm_mc *pmc)
	72	{
	73	return nvkm_mc_new_(&ga100_mc, device, index, pmc);
	74	}

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c+3−3

@@ -316,9 +316,9 @@ nvkm_mmu_vram(struct nvkm_mmu *mmu) · 315 unmodified lines
316	{	316	{
317	struct nvkm_device *device = mmu->subdev.device;	317	struct nvkm_device *device = mmu->subdev.device;
318	struct nvkm_mm *mm = &device->fb->ram->vram;	318	struct nvkm_mm *mm = &device->fb->ram->vram;
319	const u32 sizeN = nvkm_mm_heap_size(mm, NVKM_RAM_MM_NORMAL);	319	const u64 sizeN = nvkm_mm_heap_size(mm, NVKM_RAM_MM_NORMAL);
320	const u32 sizeU = nvkm_mm_heap_size(mm, NVKM_RAM_MM_NOMAP);	320	const u64 sizeU = nvkm_mm_heap_size(mm, NVKM_RAM_MM_NOMAP);
321	const u32 sizeM = nvkm_mm_heap_size(mm, NVKM_RAM_MM_MIXED);	321	const u64 sizeM = nvkm_mm_heap_size(mm, NVKM_RAM_MM_MIXED);
322	u8 type = NVKM_MEM_KIND * !!mmu->func->kind;	322	u8 type = NVKM_MEM_KIND * !!mmu->func->kind;
323	u8 heap = NVKM_MEM_VRAM;	323	u8 heap = NVKM_MEM_VRAM;
324	int heapM, heapN, heapU;	324	int heapM, heapN, heapU;

drivers/gpu/drm/radeon/radeon_ttm.c+0−3

@@ -730,9 +730,6 @@ int radeon_ttm_init(struct radeon_device *rdev) · 729 unmodified lines
730	}	730	}
731	rdev->mman.initialized = true;	731	rdev->mman.initialized = true;
732		732
733	ttm_pool_init(&rdev->mman.bdev.pool, rdev->dev, rdev->need_swiotlb,
734	dma_addressing_limited(&rdev->pdev->dev));
735
736	r = radeon_ttm_init_vram(rdev);	733	r = radeon_ttm_init_vram(rdev);
737	if (r) {	734	if (r) {
738	DRM_ERROR("Failed initializing VRAM heap.\n");	735	DRM_ERROR("Failed initializing VRAM heap.\n");

drivers/gpu/drm/ttm/ttm_pool.c+11−13

 static struct ttm_pool_type global_dma32_write_combined[MAX_ORDER];
 static struct ttm_pool_type global_dma32_uncached[MAX_ORDER];
-static spinlock_t shrinker_lock;
+static struct mutex shrinker_lock;
 static struct list_head shrinker_list;
 static struct shrinker mm_shrinker;
 		size_t size = (1ULL << order) * PAGE_SIZE;
 		addr = dma_map_page(pool->dev, p, 0, size, DMA_BIDIRECTIONAL);
-		if (dma_mapping_error(pool->dev, **dma_addr))
+		if (dma_mapping_error(pool->dev, addr))
 			return -EFAULT;
 	}
 	spin_lock_init(&pt->lock);
 	INIT_LIST_HEAD(&pt->pages);
-	spin_lock(&shrinker_lock);
+	mutex_lock(&shrinker_lock);
 	list_add_tail(&pt->shrinker_list, &shrinker_list);
-	spin_unlock(&shrinker_lock);
+	mutex_unlock(&shrinker_lock);
 }
 /* Remove a pool_type from the global shrinker list and free all pages */
 {
 	struct page *p, *tmp;
-	spin_lock(&shrinker_lock);
+	mutex_lock(&shrinker_lock);
 	list_del(&pt->shrinker_list);
-	spin_unlock(&shrinker_lock);
+	mutex_unlock(&shrinker_lock);
 	list_for_each_entry_safe(p, tmp, &pt->pages, lru)
 		ttm_pool_free_page(pt->pool, pt->caching, pt->order, p);
 	unsigned int num_freed;
 	struct page *p;
-	spin_lock(&shrinker_lock);
+	mutex_lock(&shrinker_lock);
 	pt = list_first_entry(&shrinker_list, typeof(*pt), shrinker_list);
 	p = ttm_pool_type_take(pt);
 	}
 	list_move_tail(&pt->shrinker_list, &shrinker_list);
-	spin_unlock(&shrinker_lock);
+	mutex_unlock(&shrinker_lock);
 	return num_freed;
 }
 			ttm_pool_type_init(&pool->caching[i].orders[j],
 					   pool, i, j);
 }
-EXPORT_SYMBOL(ttm_pool_init);
 /**
  * ttm_pool_fini - Cleanup a pool
 		for (j = 0; j < MAX_ORDER; ++j)
 			ttm_pool_type_fini(&pool->caching[i].orders[j]);
 }
-EXPORT_SYMBOL(ttm_pool_fini);
 #ifdef CONFIG_DEBUG_FS
 /* Count the number of pages available in a pool_type */
 {
 	unsigned int i;
-	spin_lock(&shrinker_lock);
+	mutex_lock(&shrinker_lock);
 	seq_puts(m, "\t ");
 	for (i = 0; i < MAX_ORDER; ++i)
 	seq_printf(m, "\ntotal\t: %8lu of %8lu\n",
 		   atomic_long_read(&allocated_pages), page_pool_size);
-	spin_unlock(&shrinker_lock);
+	mutex_unlock(&shrinker_lock);
 	return 0;
 }
 	if (!page_pool_size)
 		page_pool_size = num_pages;
-	spin_lock_init(&shrinker_lock);
+	mutex_init(&shrinker_lock);
 	INIT_LIST_HEAD(&shrinker_list);
 	for (i = 0; i < MAX_ORDER; ++i) {

drivers/hid/Kconfig+1−0

@@ -899,6 +899,7 @@ config HID_SONY · 898 unmodified lines
899	depends on NEW_LEDS	899	depends on NEW_LEDS
900	depends on LEDS_CLASS	900	depends on LEDS_CLASS
901	select POWER_SUPPLY	901	select POWER_SUPPLY
		902	select CRC32
902	help	903	help
903	Support for	904	Support for
904		905

drivers/hid/amd-sfh-hid/amd_sfh_client.c+4−4

@@ -154,7 +154,7 @@ int amd_sfh_hid_client_init(struct amd_mp2_dev *privdata) · 153 unmodified lines
154		154
155	for (i = 0; i < cl_data->num_hid_devices; i++) {	155	for (i = 0; i < cl_data->num_hid_devices; i++) {
156	cl_data->sensor_virt_addr[i] = dma_alloc_coherent(dev, sizeof(int) * 8,	156	cl_data->sensor_virt_addr[i] = dma_alloc_coherent(dev, sizeof(int) * 8,
157	&cl_data->sensor_phys_addr[i],	157	&cl_data->sensor_dma_addr[i],
158	GFP_KERNEL);	158	GFP_KERNEL);
159	cl_data->sensor_sts[i] = 0;	159	cl_data->sensor_sts[i] = 0;
160	cl_data->sensor_requested_cnt[i] = 0;	160	cl_data->sensor_requested_cnt[i] = 0;
@@ -187,7 +187,7 @@ int amd_sfh_hid_client_init(struct amd_mp2_dev *privdata) · 26 unmodified lines
187	}	187	}
188	info.period = msecs_to_jiffies(AMD_SFH_IDLE_LOOP);	188	info.period = msecs_to_jiffies(AMD_SFH_IDLE_LOOP);
189	info.sensor_idx = cl_idx;	189	info.sensor_idx = cl_idx;
190	info.phys_address = cl_data->sensor_phys_addr[i];	190	info.dma_address = cl_data->sensor_dma_addr[i];
191		191
192	cl_data->report_descr[i] = kzalloc(cl_data->report_descr_sz[i], GFP_KERNEL);	192	cl_data->report_descr[i] = kzalloc(cl_data->report_descr_sz[i], GFP_KERNEL);
193	if (!cl_data->report_descr[i]) {	193	if (!cl_data->report_descr[i]) {
@@ -212,7 +212,7 @@ cleanup: · 18 unmodified lines
212	if (cl_data->sensor_virt_addr[i]) {	212	if (cl_data->sensor_virt_addr[i]) {
213	dma_free_coherent(&privdata->pdev->dev, 8 * sizeof(int),	213	dma_free_coherent(&privdata->pdev->dev, 8 * sizeof(int),
214	cl_data->sensor_virt_addr[i],	214	cl_data->sensor_virt_addr[i],
215	cl_data->sensor_phys_addr[i]);	215	cl_data->sensor_dma_addr[i]);
216	}	216	}
217	kfree(cl_data->feature_report[i]);	217	kfree(cl_data->feature_report[i]);
218	kfree(cl_data->input_report[i]);	218	kfree(cl_data->input_report[i]);
@@ -238,7 +238,7 @@ int amd_sfh_hid_client_deinit(struct amd_mp2_dev *privdata) · 19 unmodified lines
238	if (cl_data->sensor_virt_addr[i]) {	238	if (cl_data->sensor_virt_addr[i]) {
239	dma_free_coherent(&privdata->pdev->dev, 8 * sizeof(int),	239	dma_free_coherent(&privdata->pdev->dev, 8 * sizeof(int),
240	cl_data->sensor_virt_addr[i],	240	cl_data->sensor_virt_addr[i],
241	cl_data->sensor_phys_addr[i]);	241	cl_data->sensor_dma_addr[i]);
242	}	242	}
243	}	243	}
244	kfree(cl_data);	244	kfree(cl_data);

drivers/hid/amd-sfh-hid/amd_sfh_hid.h+1−1

@@ -27,7 +27,7 @@ struct amdtp_cl_data { · 26 unmodified lines
27	int hid_descr_size[MAX_HID_DEVICES];	27	int hid_descr_size[MAX_HID_DEVICES];
28	phys_addr_t phys_addr_base;	28	phys_addr_t phys_addr_base;
29	u32 *sensor_virt_addr[MAX_HID_DEVICES];	29	u32 *sensor_virt_addr[MAX_HID_DEVICES];
30	phys_addr_t sensor_phys_addr[MAX_HID_DEVICES];	30	dma_addr_t sensor_dma_addr[MAX_HID_DEVICES];
31	u32 sensor_sts[MAX_HID_DEVICES];	31	u32 sensor_sts[MAX_HID_DEVICES];
32	u32 sensor_requested_cnt[MAX_HID_DEVICES];	32	u32 sensor_requested_cnt[MAX_HID_DEVICES];
33	u8 report_type[MAX_HID_DEVICES];	33	u8 report_type[MAX_HID_DEVICES];

drivers/hid/amd-sfh-hid/amd_sfh_pcie.c+1−1

@@ -41,7 +41,7 @@ void amd_start_sensor(struct amd_mp2_dev *privdata, struct amd_mp2_sensor_info i · 40 unmodified lines
41	cmd_param.s.buf_layout = 1;	41	cmd_param.s.buf_layout = 1;
42	cmd_param.s.buf_length = 16;	42	cmd_param.s.buf_length = 16;
43		43
44	writeq(info.phys_address, privdata->mmio + AMD_C2P_MSG2);	44	writeq(info.dma_address, privdata->mmio + AMD_C2P_MSG2);
45	writel(cmd_param.ul, privdata->mmio + AMD_C2P_MSG1);	45	writel(cmd_param.ul, privdata->mmio + AMD_C2P_MSG1);
46	writel(cmd_base.ul, privdata->mmio + AMD_C2P_MSG0);	46	writel(cmd_base.ul, privdata->mmio + AMD_C2P_MSG0);
47	}	47	}

drivers/hid/amd-sfh-hid/amd_sfh_pcie.h+1−1

@@ -67,7 +67,7 @@ struct amd_mp2_dev { · 66 unmodified lines
67	struct amd_mp2_sensor_info {	67	struct amd_mp2_sensor_info {
68	u8 sensor_idx;	68	u8 sensor_idx;
69	u32 period;	69	u32 period;
70	phys_addr_t phys_address;	70	dma_addr_t dma_address;
71	};	71	};
72		72
73	void amd_start_sensor(struct amd_mp2_dev *privdata, struct amd_mp2_sensor_info info);	73	void amd_start_sensor(struct amd_mp2_dev *privdata, struct amd_mp2_sensor_info info);

drivers/hid/hid-ids.h+1−0

@@ -389,6 +389,7 @@ · 388 unmodified lines
389	#define USB_DEVICE_ID_TOSHIBA_CLICK_L9W 0x0401	389	#define USB_DEVICE_ID_TOSHIBA_CLICK_L9W 0x0401
390	#define USB_DEVICE_ID_HP_X2 0x074d	390	#define USB_DEVICE_ID_HP_X2 0x074d
391	#define USB_DEVICE_ID_HP_X2_10_COVER 0x0755	391	#define USB_DEVICE_ID_HP_X2_10_COVER 0x0755
		392	#define USB_DEVICE_ID_ASUS_UX550_TOUCHSCREEN 0x2706
392		393
393	#define USB_VENDOR_ID_ELECOM 0x056e	394	#define USB_VENDOR_ID_ELECOM 0x056e
394	#define USB_DEVICE_ID_ELECOM_BM084 0x0061	395	#define USB_DEVICE_ID_ELECOM_BM084 0x0061

drivers/hid/hid-input.c+2−0

@@ -322,6 +322,8 @@ static const struct hid_device_id hid_battery_quirks[] = { · 321 unmodified lines
322	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_LOGITECH,	322	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_LOGITECH,
323	USB_DEVICE_ID_LOGITECH_DINOVO_EDGE_KBD),	323	USB_DEVICE_ID_LOGITECH_DINOVO_EDGE_KBD),
324	HID_BATTERY_QUIRK_IGNORE },	324	HID_BATTERY_QUIRK_IGNORE },
		325	{ HID_USB_DEVICE(USB_VENDOR_ID_ELAN, USB_DEVICE_ID_ASUS_UX550_TOUCHSCREEN),
		326	HID_BATTERY_QUIRK_IGNORE },
325	{}	327	{}
326	};	328	};
327		329

drivers/hid/hid-logitech-dj.c+4−0

 	  HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH,
 		0xc531),
 	 .driver_data = recvr_type_gaming_hidpp},
+	{ /* Logitech G602 receiver (0xc537) */
+	  HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH,
+		0xc537),
+	 .driver_data = recvr_type_gaming_hidpp},
 	{ /* Logitech lightspeed receiver (0xc539) */
 	  HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH,
 		USB_DEVICE_ID_LOGITECH_NANO_RECEIVER_LIGHTSPEED_1),

drivers/hid/hid-logitech-hidpp.c+2−0

 	{ /* MX Master mouse over Bluetooth */
 	  HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_LOGITECH, 0xb012),
 	  .driver_data = HIDPP_QUIRK_HI_RES_SCROLL_X2121 },
+	{ /* MX Ergo trackball over Bluetooth */
+	  HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_LOGITECH, 0xb01d) },
 	{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_LOGITECH, 0xb01e),
 	  .driver_data = HIDPP_QUIRK_HI_RES_SCROLL_X2121 },
 	{ /* MX Master 3 mouse over Bluetooth */

drivers/hid/hid-multitouch.c+4−0

 		HID_DEVICE(BUS_I2C, HID_GROUP_MULTITOUCH_WIN_8,
 			USB_VENDOR_ID_SYNAPTICS, 0xce08) },
+	{ .driver_data = MT_CLS_WIN_8_FORCE_MULTI_INPUT,
+		HID_DEVICE(BUS_I2C, HID_GROUP_MULTITOUCH_WIN_8,
+			USB_VENDOR_ID_SYNAPTICS, 0xce09) },
 	/* TopSeed panels */
 	{ .driver_data = MT_CLS_TOPSEED,
 		MT_USB_DEVICE(USB_VENDOR_ID_TOPSEED2,

drivers/hid/hid-uclogic-params.c+1−1

@@ -90,7 +90,7 @@ static int uclogic_params_get_str_desc(__u8 *pbuf, struct hid_device hdev, · 89 unmodified lines
90	goto cleanup;	90	goto cleanup;
91	} else if (rc < 0) {	91	} else if (rc < 0) {
92	hid_err(hdev,	92	hid_err(hdev,
93	"failed retrieving string descriptor #%hhu: %d\n",	93	"failed retrieving string descriptor #%u: %d\n",
94	idx, rc);	94	idx, rc);
95	goto cleanup;	95	goto cleanup;
96	}	96	}

drivers/hid/hid-wiimote-core.c+1−1

@@ -1482,7 +1482,7 @@ static void handler_return(struct wiimote_data wdata, const __u8 payload) · 1481 unmodified lines
1482	wdata->state.cmd_err = err;	1482	wdata->state.cmd_err = err;
1483	wiimote_cmd_complete(wdata);	1483	wiimote_cmd_complete(wdata);
1484	} else if (err) {	1484	} else if (err) {
1485	hid_warn(wdata->hdev, "Remote error %hhu on req %hhu\n", err,	1485	hid_warn(wdata->hdev, "Remote error %u on req %u\n", err,
1486	cmd);	1486	cmd);
1487	}	1487	}
1488	}	1488	}

drivers/hid/wacom_sys.c+32−3

@@ -1270,6 +1270,37 @@ static int wacom_devm_sysfs_create_group(struct wacom *wacom, · 1269 unmodified lines
1270	group);	1270	group);
1271	}	1271	}
1272		1272
		1273	static void wacom_devm_kfifo_release(struct device dev, void res)
		1274	{
		1275	struct kfifo_rec_ptr_2 *devres = res;
		1276
		1277	kfifo_free(devres);
		1278	}
		1279
		1280	static int wacom_devm_kfifo_alloc(struct wacom *wacom)
		1281	{
		1282	struct wacom_wac *wacom_wac = &wacom->wacom_wac;
		1283	struct kfifo_rec_ptr_2 *pen_fifo = &wacom_wac->pen_fifo;
		1284	int error;
		1285
		1286	pen_fifo = devres_alloc(wacom_devm_kfifo_release,
		1287	sizeof(struct kfifo_rec_ptr_2),
		1288	GFP_KERNEL);
		1289
		1290	if (!pen_fifo)
		1291	return -ENOMEM;
		1292
		1293	error = kfifo_alloc(pen_fifo, WACOM_PKGLEN_MAX, GFP_KERNEL);
		1294	if (error) {
		1295	devres_free(pen_fifo);
		1296	return error;
		1297	}
		1298
		1299	devres_add(&wacom->hdev->dev, pen_fifo);
		1300
		1301	return 0;
		1302	}
		1303
1273	enum led_brightness wacom_leds_brightness_get(struct wacom_led *led)	1304	enum led_brightness wacom_leds_brightness_get(struct wacom_led *led)
1274	{	1305	{
1275	struct wacom *wacom = led->wacom;	1306	struct wacom *wacom = led->wacom;
@@ -2724,7 +2755,7 @@ static int wacom_probe(struct hid_device *hdev, · 1448 unmodified lines
2724	if (features->check_for_hid_type && features->hid_type != hdev->type)	2755	if (features->check_for_hid_type && features->hid_type != hdev->type)
2725	return -ENODEV;	2756	return -ENODEV;
2726		2757
2727	error = kfifo_alloc(&wacom_wac->pen_fifo, WACOM_PKGLEN_MAX, GFP_KERNEL);	2758	error = wacom_devm_kfifo_alloc(wacom);
2728	if (error)	2759	if (error)
2729	return error;	2760	return error;
2730		2761
@@ -2786,8 +2817,6 @@ static void wacom_remove(struct hid_device *hdev) · 55 unmodified lines
2786		2817
2787	if (wacom->wacom_wac.features.type != REMOTE)	2818	if (wacom->wacom_wac.features.type != REMOTE)
2788	wacom_release_resources(wacom);	2819	wacom_release_resources(wacom);
2789
2790	kfifo_free(&wacom_wac->pen_fifo);
2791	}	2820	}
2792		2821
2793	#ifdef CONFIG_PM	2822	#ifdef CONFIG_PM

drivers/hv/vmbus_drv.c+0−2

 	/* Make sure conn_state is set as hv_synic_cleanup checks for it */
 	mb();
 	cpuhp_remove_state(hyperv_cpuhp_online);
-	hyperv_cleanup();
 };
 static void hv_crash_handler(struct pt_regs *regs)
 	cpu = smp_processor_id();
 	hv_stimer_cleanup(cpu);
 	hv_synic_disable_regs(cpu);
-	hyperv_cleanup();
 };
 static int hv_synic_suspend(void)

drivers/hwmon/amd_energy.c+2−1

 	 */
 	cpus = num_present_cpus() / num_siblings;
-	s_config = devm_kcalloc(dev, cpus + sockets,
+	s_config = devm_kcalloc(dev, cpus + sockets + 1,
 				sizeof(u32), GFP_KERNEL);
 	if (!s_config)
 		return -ENOMEM;
 			scnprintf(label_l[i], 10, "Esocket%u", (i - cpus));
 	}
+	s_config[i] = 0;
 	return 0;
 }

drivers/hwmon/pwm-fan.c+11−1

@@ -334,8 +334,18 @@ static int pwm_fan_probe(struct platform_device *pdev) · 333 unmodified lines
334		334
335	ctx->pwm_value = MAX_PWM;	335	ctx->pwm_value = MAX_PWM;
336		336
337	/* Set duty cycle to maximum allowed and enable PWM output */
338	pwm_init_state(ctx->pwm, &state);	337	pwm_init_state(ctx->pwm, &state);
		338	/*
		339	* __set_pwm assumes that MAX_PWM * (period - 1) fits into an unsigned
		340	* long. Check this here to prevent the fan running at a too low
		341	* frequency.
		342	*/
		343	if (state.period > ULONG_MAX / MAX_PWM + 1) {
		344	dev_err(dev, "Configured period too big\n");
		345	return -EINVAL;
		346	}
		347
		348	/* Set duty cycle to maximum allowed and enable PWM output */
339	state.duty_cycle = ctx->pwm->args.period - 1;	349	state.duty_cycle = ctx->pwm->args.period - 1;
340	state.enabled = true;	350	state.enabled = true;
341		351

drivers/i2c/busses/i2c-i801.c+1−1

@@ -1449,7 +1449,7 @@ static int i801_add_mux(struct i801_priv *priv) · 1448 unmodified lines
1449		1449
1450	/* Register GPIO descriptor lookup table */	1450	/* Register GPIO descriptor lookup table */
1451	lookup = devm_kzalloc(dev,	1451	lookup = devm_kzalloc(dev,
1452	struct_size(lookup, table, mux_config->n_gpios),	1452	struct_size(lookup, table, mux_config->n_gpios + 1),
1453	GFP_KERNEL);	1453	GFP_KERNEL);
1454	if (!lookup)	1454	if (!lookup)
1455	return -ENOMEM;	1455	return -ENOMEM;

drivers/i2c/busses/i2c-mt65xx.c+22−5

@@ -38,6 +38,7 @@ · 37 unmodified lines
38	#define I2C_IO_CONFIG_OPEN_DRAIN 0x0003	38	#define I2C_IO_CONFIG_OPEN_DRAIN 0x0003
39	#define I2C_IO_CONFIG_PUSH_PULL 0x0000	39	#define I2C_IO_CONFIG_PUSH_PULL 0x0000
40	#define I2C_SOFT_RST 0x0001	40	#define I2C_SOFT_RST 0x0001
		41	#define I2C_HANDSHAKE_RST 0x0020
41	#define I2C_FIFO_ADDR_CLR 0x0001	42	#define I2C_FIFO_ADDR_CLR 0x0001
42	#define I2C_DELAY_LEN 0x0002	43	#define I2C_DELAY_LEN 0x0002
43	#define I2C_TIME_CLR_VALUE 0x0000	44	#define I2C_TIME_CLR_VALUE 0x0000
@@ -45,6 +46,7 @@ · 1 unmodified line
45	#define I2C_WRRD_TRANAC_VALUE 0x0002	46	#define I2C_WRRD_TRANAC_VALUE 0x0002
46	#define I2C_RD_TRANAC_VALUE 0x0001	47	#define I2C_RD_TRANAC_VALUE 0x0001
47	#define I2C_SCL_MIS_COMP_VALUE 0x0000	48	#define I2C_SCL_MIS_COMP_VALUE 0x0000
		49	#define I2C_CHN_CLR_FLAG 0x0000
48		50
49	#define I2C_DMA_CON_TX 0x0000	51	#define I2C_DMA_CON_TX 0x0000
50	#define I2C_DMA_CON_RX 0x0001	52	#define I2C_DMA_CON_RX 0x0001
@@ -54,7 +56,9 @@ · 3 unmodified lines
54	#define I2C_DMA_START_EN 0x0001	56	#define I2C_DMA_START_EN 0x0001
55	#define I2C_DMA_INT_FLAG_NONE 0x0000	57	#define I2C_DMA_INT_FLAG_NONE 0x0000
56	#define I2C_DMA_CLR_FLAG 0x0000	58	#define I2C_DMA_CLR_FLAG 0x0000
		59	#define I2C_DMA_WARM_RST 0x0001
57	#define I2C_DMA_HARD_RST 0x0002	60	#define I2C_DMA_HARD_RST 0x0002
		61	#define I2C_DMA_HANDSHAKE_RST 0x0004
58		62
59	#define MAX_SAMPLE_CNT_DIV 8	63	#define MAX_SAMPLE_CNT_DIV 8
60	#define MAX_STEP_CNT_DIV 64	64	#define MAX_STEP_CNT_DIV 64
@@ -475,11 +479,24 @@ static void mtk_i2c_init_hw(struct mtk_i2c *i2c) · 414 unmodified lines
475	{	479	{
476	u16 control_reg;	480	u16 control_reg;
477		481
478	writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST);	482	if (i2c->dev_comp->dma_sync) {
479	udelay(50);	483	writel(I2C_DMA_WARM_RST, i2c->pdmabase + OFFSET_RST);
480	writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);	484	udelay(10);
481		485	writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
482	mtk_i2c_writew(i2c, I2C_SOFT_RST, OFFSET_SOFTRESET);	486	udelay(10);
		487	writel(I2C_DMA_HANDSHAKE_RST \| I2C_DMA_HARD_RST,
		488	i2c->pdmabase + OFFSET_RST);
		489	mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST \| I2C_SOFT_RST,
		490	OFFSET_SOFTRESET);
		491	udelay(10);
		492	writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
		493	mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_SOFTRESET);
		494	} else {
		495	writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST);
		496	udelay(50);
		497	writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
		498	mtk_i2c_writew(i2c, I2C_SOFT_RST, OFFSET_SOFTRESET);
		499	}
483		500
484	/* Set ioconfig */	501	/* Set ioconfig */
485	if (i2c->use_push_pull)	502	if (i2c->use_push_pull)

drivers/i2c/busses/i2c-sprd.c+7−1

 /* timeout (ms) for pm runtime autosuspend */
 #define SPRD_I2C_PM_TIMEOUT	1000
+/* timeout (ms) for transfer message */
+#define I2C_XFER_TIMEOUT	1000
 /* SPRD i2c data structure */
 struct sprd_i2c {
 			       struct i2c_msg *msg, bool is_last_msg)
 {
 	struct sprd_i2c *i2c_dev = i2c_adap->algo_data;
+	unsigned long time_left;
 	i2c_dev->msg = msg;
 	i2c_dev->buf = msg->buf;
 	sprd_i2c_opt_start(i2c_dev);
-	wait_for_completion(&i2c_dev->complete);
+	time_left = wait_for_completion_timeout(&i2c_dev->complete,
+				msecs_to_jiffies(I2C_XFER_TIMEOUT));
+	if (!time_left)
+		return -ETIMEDOUT;
 	return i2c_dev->err;
 }

drivers/ide/ide-atapi.c+0−1

@@ -223,7 +223,6 @@ void ide_prep_sense(ide_drive_t drive, struct request rq) · 222 unmodified lines
223	sense_rq->rq_disk = rq->rq_disk;	223	sense_rq->rq_disk = rq->rq_disk;
224	sense_rq->cmd_flags = REQ_OP_DRV_IN;	224	sense_rq->cmd_flags = REQ_OP_DRV_IN;
225	ide_req(sense_rq)->type = ATA_PRIV_SENSE;	225	ide_req(sense_rq)->type = ATA_PRIV_SENSE;
226	sense_rq->rq_flags \|= RQF_PREEMPT;
227		226
228	req->cmd[0] = GPCMD_REQUEST_SENSE;	227	req->cmd[0] = GPCMD_REQUEST_SENSE;
229	req->cmd[4] = cmd_len;	228	req->cmd[4] = cmd_len;

drivers/ide/ide-io.c+1−6

 		 * above to return us whatever is in the queue. Since we call
 		 * ide_do_request() ourselves, we end up taking requests while
 		 * the queue is blocked...
-		 *
-		 * We let requests forced at head of queue with ide-preempt
-		 * though. I hope that doesn't happen too much, hopefully not
-		 * unless the subdriver triggers such a thing in its own PM
-		 * state machine.
 		 */
 		if ((drive->dev_flags & IDE_DFLAG_BLOCKED) &&
 		    ata_pm_request(rq) == 0 &&
-		    (rq->rq_flags & RQF_PREEMPT) == 0) {
+		    (rq->rq_flags & RQF_PM) == 0) {
 			/* there should be no pending command at this point */
 			ide_unlock_port(hwif);
 			goto plug_device;

drivers/ide/ide-pm.c+1−1

@@ -77,7 +77,7 @@ int generic_ide_resume(struct device *dev) · 76 unmodified lines
77	}	77	}
78		78
79	memset(&rqpm, 0, sizeof(rqpm));	79	memset(&rqpm, 0, sizeof(rqpm));
80	rq = blk_get_request(drive->queue, REQ_OP_DRV_IN, BLK_MQ_REQ_PREEMPT);	80	rq = blk_get_request(drive->queue, REQ_OP_DRV_IN, BLK_MQ_REQ_PM);
81	ide_req(rq)->type = ATA_PRIV_PM_RESUME;	81	ide_req(rq)->type = ATA_PRIV_PM_RESUME;
82	ide_req(rq)->special = &rqpm;	82	ide_req(rq)->special = &rqpm;
83	rqpm.pm_step = IDE_PM_START_RESUME;	83	rqpm.pm_step = IDE_PM_START_RESUME;

drivers/idle/intel_idle.c+40−1

@@ -963,6 +963,39 @@ static struct cpuidle_state dnv_cstates[] __initdata = { · 962 unmodified lines
963	.enter = NULL }	963	.enter = NULL }
964	};	964	};
965		965
		966	/*
		967	* Note, depending on HW and FW revision, SnowRidge SoC may or may not support
		968	* C6, and this is indicated in the CPUID mwait leaf.
		969	*/
		970	static struct cpuidle_state snr_cstates[] __initdata = {
		971	{
		972	.name = "C1",
		973	.desc = "MWAIT 0x00",
		974	.flags = MWAIT2flg(0x00),
		975	.exit_latency = 2,
		976	.target_residency = 2,
		977	.enter = &intel_idle,
		978	.enter_s2idle = intel_idle_s2idle, },
		979	{
		980	.name = "C1E",
		981	.desc = "MWAIT 0x01",
		982	.flags = MWAIT2flg(0x01) \| CPUIDLE_FLAG_ALWAYS_ENABLE,
		983	.exit_latency = 15,
		984	.target_residency = 25,
		985	.enter = &intel_idle,
		986	.enter_s2idle = intel_idle_s2idle, },
		987	{
		988	.name = "C6",
		989	.desc = "MWAIT 0x20",
		990	.flags = MWAIT2flg(0x20) \| CPUIDLE_FLAG_TLB_FLUSHED,
		991	.exit_latency = 130,
		992	.target_residency = 500,
		993	.enter = &intel_idle,
		994	.enter_s2idle = intel_idle_s2idle, },
		995	{
		996	.enter = NULL }
		997	};
		998
966	static const struct idle_cpu idle_cpu_nehalem __initconst = {	999	static const struct idle_cpu idle_cpu_nehalem __initconst = {
967	.state_table = nehalem_cstates,	1000	.state_table = nehalem_cstates,
968	.auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE \| NHM_C3_AUTO_DEMOTE,	1001	.auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE \| NHM_C3_AUTO_DEMOTE,
@@ -1084,6 +1117,12 @@ static const struct idle_cpu idle_cpu_dnv __initconst = { · 115 unmodified lines
1084	.use_acpi = true,	1117	.use_acpi = true,
1085	};	1118	};
1086		1119
		1120	static const struct idle_cpu idle_cpu_snr __initconst = {
		1121	.state_table = snr_cstates,
		1122	.disable_promotion_to_c1e = true,
		1123	.use_acpi = true,
		1124	};
		1125
1087	static const struct x86_cpu_id intel_idle_ids[] __initconst = {	1126	static const struct x86_cpu_id intel_idle_ids[] __initconst = {
1088	X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_EP, &idle_cpu_nhx),	1127	X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_EP, &idle_cpu_nhx),
1089	X86_MATCH_INTEL_FAM6_MODEL(NEHALEM, &idle_cpu_nehalem),	1128	X86_MATCH_INTEL_FAM6_MODEL(NEHALEM, &idle_cpu_nehalem),
@@ -1122,7 +1161,7 @@ static const struct x86_cpu_id intel_idle_ids[] __initconst = { · 32 unmodified lines
1122	X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT, &idle_cpu_bxt),	1161	X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT, &idle_cpu_bxt),
1123	X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_PLUS, &idle_cpu_bxt),	1162	X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_PLUS, &idle_cpu_bxt),
1124	X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_D, &idle_cpu_dnv),	1163	X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_D, &idle_cpu_dnv),
1125	X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, &idle_cpu_dnv),	1164	X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, &idle_cpu_snr),
1126	{}	1165	{}
1127	};	1166	};
1128		1167

drivers/infiniband/core/cma_configfs.c+3−1

@@ -131,8 +131,10 @@ static ssize_t default_roce_mode_store(struct config_item *item, · 130 unmodified lines
131	return ret;	131	return ret;
132		132
133	gid_type = ib_cache_gid_parse_type_str(buf);	133	gid_type = ib_cache_gid_parse_type_str(buf);
134	if (gid_type < 0)	134	if (gid_type < 0) {
		135	cma_configfs_params_put(cma_dev);
135	return -EINVAL;	136	return -EINVAL;
		137	}
136		138
137	ret = cma_set_default_gid_type(cma_dev, group->port_num, gid_type);	139	ret = cma_set_default_gid_type(cma_dev, group->port_num, gid_type);
138		140

drivers/infiniband/core/restrack.c+1−0

@@ -254,6 +254,7 @@ void rdma_restrack_add(struct rdma_restrack_entry *res) · 253 unmodified lines
254	} else {	254	} else {
255	ret = xa_alloc_cyclic(&rt->xa, &res->id, res, xa_limit_32b,	255	ret = xa_alloc_cyclic(&rt->xa, &res->id, res, xa_limit_32b,
256	&rt->next_id, GFP_KERNEL);	256	&rt->next_id, GFP_KERNEL);
		257	ret = (ret < 0) ? ret : 0;
257	}	258	}
258		259
259	out:	260	out:

drivers/infiniband/core/ucma.c+72−63

@@ -95,8 +95,6 @@ struct ucma_context { · 94 unmodified lines
95	u64 uid;	95	u64 uid;
96		96
97	struct list_head list;	97	struct list_head list;
98	/* sync between removal event and id destroy, protected by file mut */
99	int destroying;
100	struct work_struct close_work;	98	struct work_struct close_work;
101	};	99	};
102		100
@@ -122,7 +120,7 @@ static DEFINE_XARRAY_ALLOC(ctx_table); · 19 unmodified lines
122	static DEFINE_XARRAY_ALLOC(multicast_table);	120	static DEFINE_XARRAY_ALLOC(multicast_table);
123		121
124	static const struct file_operations ucma_fops;	122	static const struct file_operations ucma_fops;
125	static int __destroy_id(struct ucma_context *ctx);	123	static int ucma_destroy_private_ctx(struct ucma_context *ctx);
126		124
127	static inline struct ucma_context *_ucma_find_context(int id,	125	static inline struct ucma_context *_ucma_find_context(int id,
128	struct ucma_file *file)	126	struct ucma_file *file)
@@ -179,19 +177,14 @@ static void ucma_close_id(struct work_struct *work) · 50 unmodified lines
179		177
180	/* once all inflight tasks are finished, we close all underlying	178	/* once all inflight tasks are finished, we close all underlying
181	* resources. The context is still alive till its explicit destryoing	179	* resources. The context is still alive till its explicit destryoing
182	* by its creator.	180	* by its creator. This puts back the xarray's reference.
183	*/	181	*/
184	ucma_put_ctx(ctx);	182	ucma_put_ctx(ctx);
185	wait_for_completion(&ctx->comp);	183	wait_for_completion(&ctx->comp);
186	/* No new events will be generated after destroying the id. */	184	/* No new events will be generated after destroying the id. */
187	rdma_destroy_id(ctx->cm_id);	185	rdma_destroy_id(ctx->cm_id);
188		186
189	/*	187	/* Reading the cm_id without holding a positive ref is not allowed */
190	* At this point ctx->ref is zero so the only place the ctx can be is in
191	* a uevent or in __destroy_id(). Since the former doesn't touch
192	* ctx->cm_id and the latter sync cancels this, there is no races with
193	* this store.
194	*/
195	ctx->cm_id = NULL;	188	ctx->cm_id = NULL;
196	}	189	}
197		190
@@ -204,7 +197,6 @@ static struct ucma_context ucma_alloc_ctx(struct ucma_file file) · 6 unmodified lines
204	return NULL;	197	return NULL;
205		198
206	INIT_WORK(&ctx->close_work, ucma_close_id);	199	INIT_WORK(&ctx->close_work, ucma_close_id);
207	refcount_set(&ctx->ref, 1);
208	init_completion(&ctx->comp);	200	init_completion(&ctx->comp);
209	/* So list_del() will work if we don't do ucma_finish_ctx() */	201	/* So list_del() will work if we don't do ucma_finish_ctx() */
210	INIT_LIST_HEAD(&ctx->list);	202	INIT_LIST_HEAD(&ctx->list);
@@ -218,6 +210,13 @@ static struct ucma_context ucma_alloc_ctx(struct ucma_file file) · 7 unmodified lines
218	return ctx;	210	return ctx;
219	}	211	}
220		212
		213	static void ucma_set_ctx_cm_id(struct ucma_context *ctx,
		214	struct rdma_cm_id *cm_id)
		215	{
		216	refcount_set(&ctx->ref, 1);
		217	ctx->cm_id = cm_id;
		218	}
		219
221	static void ucma_finish_ctx(struct ucma_context *ctx)	220	static void ucma_finish_ctx(struct ucma_context *ctx)
222	{	221	{
223	lockdep_assert_held(&ctx->file->mut);	222	lockdep_assert_held(&ctx->file->mut);
@@ -303,7 +302,7 @@ static int ucma_connect_event_handler(struct rdma_cm_id *cm_id, · 79 unmodified lines
303	ctx = ucma_alloc_ctx(listen_ctx->file);	302	ctx = ucma_alloc_ctx(listen_ctx->file);
304	if (!ctx)	303	if (!ctx)
305	goto err_backlog;	304	goto err_backlog;
306	ctx->cm_id = cm_id;	305	ucma_set_ctx_cm_id(ctx, cm_id);
307		306
308	uevent = ucma_create_uevent(listen_ctx, event);	307	uevent = ucma_create_uevent(listen_ctx, event);
309	if (!uevent)	308	if (!uevent)
@@ -321,8 +320,7 @@ static int ucma_connect_event_handler(struct rdma_cm_id *cm_id, · 11 unmodified lines
321	return 0;	320	return 0;
322		321
323	err_alloc:	322	err_alloc:
324	xa_erase(&ctx_table, ctx->id);	323	ucma_destroy_private_ctx(ctx);
325	kfree(ctx);
326	err_backlog:	324	err_backlog:
327	atomic_inc(&listen_ctx->backlog);	325	atomic_inc(&listen_ctx->backlog);
328	/* Returning error causes the new ID to be destroyed */	326	/* Returning error causes the new ID to be destroyed */
@@ -356,8 +354,12 @@ static int ucma_event_handler(struct rdma_cm_id *cm_id, · 27 unmodified lines
356	wake_up_interruptible(&ctx->file->poll_wait);	354	wake_up_interruptible(&ctx->file->poll_wait);
357	}	355	}
358		356
359	if (event->event == RDMA_CM_EVENT_DEVICE_REMOVAL && !ctx->destroying)	357	if (event->event == RDMA_CM_EVENT_DEVICE_REMOVAL) {
360	queue_work(system_unbound_wq, &ctx->close_work);	358	xa_lock(&ctx_table);
		359	if (xa_load(&ctx_table, ctx->id) == ctx)
		360	queue_work(system_unbound_wq, &ctx->close_work);
		361	xa_unlock(&ctx_table);
		362	}
361	return 0;	363	return 0;
362	}	364	}
363		365
@@ -461,13 +463,12 @@ static ssize_t ucma_create_id(struct ucma_file file, const char __user inbuf, · 97 unmodified lines
461	ret = PTR_ERR(cm_id);	463	ret = PTR_ERR(cm_id);
462	goto err1;	464	goto err1;
463	}	465	}
464	ctx->cm_id = cm_id;	466	ucma_set_ctx_cm_id(ctx, cm_id);
465		467
466	resp.id = ctx->id;	468	resp.id = ctx->id;
467	if (copy_to_user(u64_to_user_ptr(cmd.response),	469	if (copy_to_user(u64_to_user_ptr(cmd.response),
468	&resp, sizeof(resp))) {	470	&resp, sizeof(resp))) {
469	xa_erase(&ctx_table, ctx->id);	471	ucma_destroy_private_ctx(ctx);
470	__destroy_id(ctx);
471	return -EFAULT;	472	return -EFAULT;
472	}	473	}
473		474
@@ -477,8 +478,7 @@ static ssize_t ucma_create_id(struct ucma_file file, const char __user inbuf, · 3 unmodified lines
477	return 0;	478	return 0;
478		479
479	err1:	480	err1:
480	xa_erase(&ctx_table, ctx->id);	481	ucma_destroy_private_ctx(ctx);
481	kfree(ctx);
482	return ret;	482	return ret;
483	}	483	}
484		484
@@ -516,68 +516,73 @@ static void ucma_cleanup_mc_events(struct ucma_multicast *mc) · 31 unmodified lines
516	rdma_unlock_handler(mc->ctx->cm_id);	516	rdma_unlock_handler(mc->ctx->cm_id);
517	}	517	}
518		518
519	/*	519	static int ucma_cleanup_ctx_events(struct ucma_context *ctx)
520	* ucma_free_ctx is called after the underlying rdma CM-ID is destroyed. At
521	* this point, no new events will be reported from the hardware. However, we
522	* still need to cleanup the UCMA context for this ID. Specifically, there
523	* might be events that have not yet been consumed by the user space software.
524	* mutex. After that we release them as needed.
525	*/
526	static int ucma_free_ctx(struct ucma_context *ctx)
527	{	520	{
528	int events_reported;	521	int events_reported;
529	struct ucma_event uevent, tmp;	522	struct ucma_event uevent, tmp;
530	LIST_HEAD(list);	523	LIST_HEAD(list);
531		524
532	ucma_cleanup_multicast(ctx);	525	/* Cleanup events not yet reported to the user.*/
533
534	/* Cleanup events not yet reported to the user. */
535	mutex_lock(&ctx->file->mut);	526	mutex_lock(&ctx->file->mut);
536	list_for_each_entry_safe(uevent, tmp, &ctx->file->event_list, list) {	527	list_for_each_entry_safe(uevent, tmp, &ctx->file->event_list, list) {
537	if (uevent->ctx == ctx \|\| uevent->conn_req_ctx == ctx)	528	if (uevent->ctx != ctx)
		529	continue;
		530
		531	if (uevent->resp.event == RDMA_CM_EVENT_CONNECT_REQUEST &&
		532	xa_cmpxchg(&ctx_table, uevent->conn_req_ctx->id,
		533	uevent->conn_req_ctx, XA_ZERO_ENTRY,
		534	GFP_KERNEL) == uevent->conn_req_ctx) {
538	list_move_tail(&uevent->list, &list);	535	list_move_tail(&uevent->list, &list);
		536	continue;
		537	}
		538	list_del(&uevent->list);
		539	kfree(uevent);
539	}	540	}
540	list_del(&ctx->list);	541	list_del(&ctx->list);
541	events_reported = ctx->events_reported;	542	events_reported = ctx->events_reported;
542	mutex_unlock(&ctx->file->mut);	543	mutex_unlock(&ctx->file->mut);
543		544
544	/*	545	/*
545	* If this was a listening ID then any connections spawned from it	546	* If this was a listening ID then any connections spawned from it that
546	* that have not been delivered to userspace are cleaned up too.	547	* have not been delivered to userspace are cleaned up too. Must be done
547	* Must be done outside any locks.	548	* outside any locks.
548	*/	549	*/
549	list_for_each_entry_safe(uevent, tmp, &list, list) {	550	list_for_each_entry_safe(uevent, tmp, &list, list) {
550	list_del(&uevent->list);	551	ucma_destroy_private_ctx(uevent->conn_req_ctx);
551	if (uevent->resp.event == RDMA_CM_EVENT_CONNECT_REQUEST &&
552	uevent->conn_req_ctx != ctx)
553	__destroy_id(uevent->conn_req_ctx);
554	kfree(uevent);	552	kfree(uevent);
555	}	553	}
556
557	mutex_destroy(&ctx->mutex);
558	kfree(ctx);
559	return events_reported;	554	return events_reported;
560	}	555	}
561		556
562	static int __destroy_id(struct ucma_context *ctx)	557	/*
		558	* When this is called the xarray must have a XA_ZERO_ENTRY in the ctx->id (ie
		559	* the ctx is not public to the user). This either because:
		560	* - ucma_finish_ctx() hasn't been called
		561	* - xa_cmpxchg() succeed to remove the entry (only one thread can succeed)
		562	*/
		563	static int ucma_destroy_private_ctx(struct ucma_context *ctx)
563	{	564	{
		565	int events_reported;
		566
564	/*	567	/*
565	* If the refcount is already 0 then ucma_close_id() has already	568	* Destroy the underlying cm_id. New work queuing is prevented now by
566	* destroyed the cm_id, otherwise holding the refcount keeps cm_id	569	* the removal from the xarray. Once the work is cancled ref will either
567	* valid. Prevent queue_work() from being called.	570	* be 0 because the work ran to completion and consumed the ref from the
		571	* xarray, or it will be positive because we still have the ref from the
		572	* xarray. This can also be 0 in cases where cm_id was never set
568	*/	573	*/
569	if (refcount_inc_not_zero(&ctx->ref)) {
570	rdma_lock_handler(ctx->cm_id);
571	ctx->destroying = 1;
572	rdma_unlock_handler(ctx->cm_id);
573	ucma_put_ctx(ctx);
574	}
575
576	cancel_work_sync(&ctx->close_work);	574	cancel_work_sync(&ctx->close_work);
577	/* At this point it's guaranteed that there is no inflight closing task */	575	if (refcount_read(&ctx->ref))
578	if (ctx->cm_id)
579	ucma_close_id(&ctx->close_work);	576	ucma_close_id(&ctx->close_work);
580	return ucma_free_ctx(ctx);	577
		578	events_reported = ucma_cleanup_ctx_events(ctx);
		579	ucma_cleanup_multicast(ctx);
		580
		581	WARN_ON(xa_cmpxchg(&ctx_table, ctx->id, XA_ZERO_ENTRY, NULL,
		582	GFP_KERNEL) != NULL);
		583	mutex_destroy(&ctx->mutex);
		584	kfree(ctx);
		585	return events_reported;
581	}	586	}
582		587
583	static ssize_t ucma_destroy_id(struct ucma_file file, const char __user inbuf,	588	static ssize_t ucma_destroy_id(struct ucma_file file, const char __user inbuf,
@@ -596,14 +601,17 @@ static ssize_t ucma_destroy_id(struct ucma_file file, const char __user inbuf, · 12 unmodified lines
596		601
597	xa_lock(&ctx_table);	602	xa_lock(&ctx_table);
598	ctx = _ucma_find_context(cmd.id, file);	603	ctx = _ucma_find_context(cmd.id, file);
599	if (!IS_ERR(ctx))	604	if (!IS_ERR(ctx)) {
600	__xa_erase(&ctx_table, ctx->id);	605	if (__xa_cmpxchg(&ctx_table, ctx->id, ctx, XA_ZERO_ENTRY,
		606	GFP_KERNEL) != ctx)
		607	ctx = ERR_PTR(-ENOENT);
		608	}
601	xa_unlock(&ctx_table);	609	xa_unlock(&ctx_table);
602		610
603	if (IS_ERR(ctx))	611	if (IS_ERR(ctx))
604	return PTR_ERR(ctx);	612	return PTR_ERR(ctx);
605		613
606	resp.events_reported = __destroy_id(ctx);	614	resp.events_reported = ucma_destroy_private_ctx(ctx);
607	if (copy_to_user(u64_to_user_ptr(cmd.response),	615	if (copy_to_user(u64_to_user_ptr(cmd.response),
608	&resp, sizeof(resp)))	616	&resp, sizeof(resp)))
609	ret = -EFAULT;	617	ret = -EFAULT;
@@ -1777,15 +1785,16 @@ static int ucma_close(struct inode inode, struct file filp) · 1167 unmodified lines
1777	* prevented by this being a FD release function. The list_add_tail() in	1785	* prevented by this being a FD release function. The list_add_tail() in
1778	* ucma_connect_event_handler() can run concurrently, however it only	1786	* ucma_connect_event_handler() can run concurrently, however it only
1779	* adds to the list after a listening ID. By only reading the first of	1787	* adds to the list after a listening ID. By only reading the first of
1780	* the list, and relying on __destroy_id() to block	1788	* the list, and relying on ucma_destroy_private_ctx() to block
1781	* ucma_connect_event_handler(), no additional locking is needed.	1789	* ucma_connect_event_handler(), no additional locking is needed.
1782	*/	1790	*/
1783	while (!list_empty(&file->ctx_list)) {	1791	while (!list_empty(&file->ctx_list)) {
1784	struct ucma_context *ctx = list_first_entry(	1792	struct ucma_context *ctx = list_first_entry(
1785	&file->ctx_list, struct ucma_context, list);	1793	&file->ctx_list, struct ucma_context, list);
1786		1794
1787	xa_erase(&ctx_table, ctx->id);	1795	WARN_ON(xa_cmpxchg(&ctx_table, ctx->id, ctx, XA_ZERO_ENTRY,
1788	__destroy_id(ctx);	1796	GFP_KERNEL) != ctx);
		1797	ucma_destroy_private_ctx(ctx);
1789	}	1798	}
1790	kfree(file);	1799	kfree(file);
1791	return 0;	1800	return 0;

drivers/infiniband/core/umem.c+1−1

@@ -135,7 +135,7 @@ unsigned long ib_umem_find_best_pgsz(struct ib_umem *umem, · 134 unmodified lines
135	*/	135	*/
136	if (mask)	136	if (mask)
137	pgsz_bitmap &= GENMASK(count_trailing_zeros(mask), 0);	137	pgsz_bitmap &= GENMASK(count_trailing_zeros(mask), 0);
138	return rounddown_pow_of_two(pgsz_bitmap);	138	return pgsz_bitmap ? rounddown_pow_of_two(pgsz_bitmap) : 0;
139	}	139	}
140	EXPORT_SYMBOL(ib_umem_find_best_pgsz);	140	EXPORT_SYMBOL(ib_umem_find_best_pgsz);
141		141

drivers/infiniband/hw/mlx5/main.c+2−2

@@ -3956,7 +3956,7 @@ static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev) · 3955 unmodified lines
3956		3956
3957	err = set_has_smi_cap(dev);	3957	err = set_has_smi_cap(dev);
3958	if (err)	3958	if (err)
3959	return err;	3959	goto err_mp;
3960		3960
3961	if (!mlx5_core_mp_enabled(mdev)) {	3961	if (!mlx5_core_mp_enabled(mdev)) {
3962	for (i = 1; i <= dev->num_ports; i++) {	3962	for (i = 1; i <= dev->num_ports; i++) {
@@ -4319,7 +4319,7 @@ static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev) · 356 unmodified lines
4319		4319
4320	err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);	4320	err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
4321	if (err)	4321	if (err)
4322	mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);	4322	mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4323		4323
4324	return err;	4324	return err;
4325	}	4325	}

drivers/infiniband/hw/ocrdma/ocrdma_verbs.c+1−1

 		pr_err("%s(%d) Freeing in use pdid=0x%x.\n",
 		       __func__, dev->id, pd->id);
 	}
-	kfree(uctx->cntxt_pd);
 	uctx->cntxt_pd = NULL;
 	_ocrdma_dealloc_pd(dev, pd);
+	kfree(pd);
 }
 static struct ocrdma_pd *ocrdma_get_ucontext_pd(struct ocrdma_ucontext *uctx)

drivers/infiniband/hw/usnic/usnic_ib_verbs.c+3−0

 		}
 		usnic_uiom_free_dev_list(dev_list);
+		dev_list = NULL;
 	}
 	/* Try to find resources on an unused vf */
 qp_grp_check:
 	if (IS_ERR_OR_NULL(qp_grp)) {
 		usnic_err("Failed to allocate qp_grp\n");
+		if (usnic_ib_share_vf)
+			usnic_uiom_free_dev_list(dev_list);
 		return ERR_PTR(qp_grp ? PTR_ERR(qp_grp) : -ENOMEM);
 	}
 	return qp_grp;

drivers/interconnect/imx/imx.c+2−1

 			return -ENODEV;
 		}
 		/* Allow scaling to be disabled on a per-node basis */
-		if (!dn || !of_device_is_available(dn)) {
+		if (!of_device_is_available(dn)) {
 			dev_warn(dev, "Missing property %s, skip scaling %s\n",
 				 adj->phandle_name, node->name);
+			of_node_put(dn);
 			return 0;
 		}

drivers/interconnect/imx/imx8mq.c+2−0

 #include <linux/module.h>
 #include <linux/platform_device.h>
+#include <linux/interconnect-provider.h>
 #include <dt-bindings/interconnect/imx8mq.h>
 #include "imx.h"
 	.remove = imx8mq_icc_remove,
 	.driver = {
 		.name = "imx8mq-interconnect",
+		.sync_state = icc_sync_state,
 	},
 };

drivers/interconnect/qcom/Kconfig+15−8

 	  This is a driver for the Qualcomm Network-on-Chip on qcs404-based
 	  platforms.
+config INTERCONNECT_QCOM_RPMH_POSSIBLE
+	tristate
+	default INTERCONNECT_QCOM
+	depends on QCOM_RPMH || (COMPILE_TEST && !QCOM_RPMH)
+	depends on QCOM_COMMAND_DB || (COMPILE_TEST && !QCOM_COMMAND_DB)
+	depends on OF || COMPILE_TEST
+	help
+	  Compile-testing RPMH drivers is possible on other platforms,
+	  but in order to avoid link failures, drivers must not be built-in
+	  when QCOM_RPMH or QCOM_COMMAND_DB are loadable modules
 config INTERCONNECT_QCOM_RPMH
 	tristate
 config INTERCONNECT_QCOM_SC7180
 	tristate "Qualcomm SC7180 interconnect driver"
-	depends on INTERCONNECT_QCOM
+	depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
-	depends on (QCOM_RPMH && QCOM_COMMAND_DB && OF) || COMPILE_TEST
 	select INTERCONNECT_QCOM_RPMH
 	select INTERCONNECT_QCOM_BCM_VOTER
 	help
 config INTERCONNECT_QCOM_SDM845
 	tristate "Qualcomm SDM845 interconnect driver"
-	depends on INTERCONNECT_QCOM
+	depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
-	depends on (QCOM_RPMH && QCOM_COMMAND_DB && OF) || COMPILE_TEST
 	select INTERCONNECT_QCOM_RPMH
 	select INTERCONNECT_QCOM_BCM_VOTER
 	help
 config INTERCONNECT_QCOM_SM8150
 	tristate "Qualcomm SM8150 interconnect driver"
-	depends on INTERCONNECT_QCOM
+	depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
-	depends on (QCOM_RPMH && QCOM_COMMAND_DB && OF) || COMPILE_TEST
 	select INTERCONNECT_QCOM_RPMH
 	select INTERCONNECT_QCOM_BCM_VOTER
 	help
 config INTERCONNECT_QCOM_SM8250
 	tristate "Qualcomm SM8250 interconnect driver"
-	depends on INTERCONNECT_QCOM
+	depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
-	depends on (QCOM_RPMH && QCOM_COMMAND_DB && OF) || COMPILE_TEST
 	select INTERCONNECT_QCOM_RPMH
 	select INTERCONNECT_QCOM_BCM_VOTER
 	help

drivers/iommu/amd/init.c+1−2

 		return r;
 	}
-	iommu->int_enabled = true;
 	return 0;
 }
 	if (ret)
 		return ret;
+	iommu->int_enabled = true;
 enable_faults:
 	iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);

drivers/iommu/amd/iommu.c+3−0

@@ -3854,6 +3854,9 @@ static int irq_remapping_select(struct irq_domain d, struct irq_fwspec fwspec, · 3853 unmodified lines
3854	struct amd_iommu *iommu;	3854	struct amd_iommu *iommu;
3855	int devid = -1;	3855	int devid = -1;
3856		3856
		3857	if (!amd_iommu_irq_remap)
		3858	return 0;
		3859
3857	if (x86_fwspec_is_ioapic(fwspec))	3860	if (x86_fwspec_is_ioapic(fwspec))
3858	devid = get_ioapic_devid(fwspec->param[0]);	3861	devid = get_ioapic_devid(fwspec->param[0]);
3859	else if (x86_fwspec_is_hpet(fwspec))	3862	else if (x86_fwspec_is_hpet(fwspec))

drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c+4−0

 		set_bit(qsmmu->bypass_cbndx, smmu->context_map);
+		arm_smmu_cb_write(smmu, qsmmu->bypass_cbndx, ARM_SMMU_CB_SCTLR, 0);
 		reg = FIELD_PREP(ARM_SMMU_CBAR_TYPE, CBAR_TYPE_S1_TRANS_S2_BYPASS);
 		arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBAR(qsmmu->bypass_cbndx), reg);
 	}
 }
 static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
+	{ .compatible = "qcom,msm8998-smmu-v2" },
 	{ .compatible = "qcom,sc7180-smmu-500" },
+	{ .compatible = "qcom,sdm630-smmu-v2" },
 	{ .compatible = "qcom,sdm845-smmu-500" },
 	{ .compatible = "qcom,sm8150-smmu-500" },
 	{ .compatible = "qcom,sm8250-smmu-500" },

drivers/iommu/dma-iommu.c+0−27

@@ -863,33 +863,6 @@ static int __finalise_sg(struct device dev, struct scatterlist sg, int nents, · 862 unmodified lines
863	unsigned int cur_len = 0, max_len = dma_get_max_seg_size(dev);	863	unsigned int cur_len = 0, max_len = dma_get_max_seg_size(dev);
864	int i, count = 0;	864	int i, count = 0;
865		865
866	/*
867	* The Intel graphic driver is used to assume that the returned
868	* sg list is not combound. This blocks the efforts of converting
869	* Intel IOMMU driver to dma-iommu api's. Add this quirk to make the
870	* device driver work and should be removed once it's fixed in i915
871	* driver.
872	*/
873	if (IS_ENABLED(CONFIG_DRM_I915) && dev_is_pci(dev) &&
874	to_pci_dev(dev)->vendor == PCI_VENDOR_ID_INTEL &&
875	(to_pci_dev(dev)->class >> 16) == PCI_BASE_CLASS_DISPLAY) {
876	for_each_sg(sg, s, nents, i) {
877	unsigned int s_iova_off = sg_dma_address(s);
878	unsigned int s_length = sg_dma_len(s);
879	unsigned int s_iova_len = s->length;
880
881	s->offset += s_iova_off;
882	s->length = s_length;
883	sg_dma_address(s) = dma_addr + s_iova_off;
884	sg_dma_len(s) = s_length;
885	dma_addr += s_iova_len;
886
887	pr_info_once("sg combining disabled due to i915 driver\n");
888	}
889
890	return nents;
891	}
892
893	for_each_sg(sg, s, nents, i) {	866	for_each_sg(sg, s, nents, i) {
894	/* Restore this segment's original unaligned fields first */	867	/* Restore this segment's original unaligned fields first */
895	unsigned int s_iova_off = sg_dma_address(s);	868	unsigned int s_iova_off = sg_dma_address(s);

drivers/iommu/intel/dmar.c+2−2

@@ -1461,8 +1461,8 @@ void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr, · 1460 unmodified lines
1461	int mask = ilog2(__roundup_pow_of_two(npages));	1461	int mask = ilog2(__roundup_pow_of_two(npages));
1462	unsigned long align = (1ULL << (VTD_PAGE_SHIFT + mask));	1462	unsigned long align = (1ULL << (VTD_PAGE_SHIFT + mask));
1463		1463
1464	if (WARN_ON_ONCE(!ALIGN(addr, align)))	1464	if (WARN_ON_ONCE(!IS_ALIGNED(addr, align)))
1465	addr &= ~(align - 1);	1465	addr = ALIGN_DOWN(addr, align);
1466		1466
1467	desc.qw0 = QI_EIOTLB_PASID(pasid) \|	1467	desc.qw0 = QI_EIOTLB_PASID(pasid) \|
1468	QI_EIOTLB_DID(did) \|	1468	QI_EIOTLB_DID(did) \|

drivers/iommu/intel/iommu.c+108−41

@@ -38,7 +38,6 @@ · 37 unmodified lines
38	#include <linux/dmi.h>	38	#include <linux/dmi.h>
39	#include <linux/pci-ats.h>	39	#include <linux/pci-ats.h>
40	#include <linux/memblock.h>	40	#include <linux/memblock.h>
41	#include <linux/dma-map-ops.h>
42	#include <linux/dma-direct.h>	41	#include <linux/dma-direct.h>
43	#include <linux/crash_dump.h>	42	#include <linux/crash_dump.h>
44	#include <linux/numa.h>	43	#include <linux/numa.h>
@@ -719,6 +718,8 @@ static int domain_update_device_node(struct dmar_domain *domain) · 674 unmodified lines
719	return nid;	718	return nid;
720	}	719	}
721		720
		721	static void domain_update_iotlb(struct dmar_domain *domain);
		722
722	/* Some capabilities may be different across iommus */	723	/* Some capabilities may be different across iommus */
723	static void domain_update_iommu_cap(struct dmar_domain *domain)	724	static void domain_update_iommu_cap(struct dmar_domain *domain)
724	{	725	{
@@ -744,6 +745,8 @@ static void domain_update_iommu_cap(struct dmar_domain *domain) · 19 unmodified lines
744	domain->domain.geometry.aperture_end = __DOMAIN_MAX_ADDR(domain->gaw - 1);	745	domain->domain.geometry.aperture_end = __DOMAIN_MAX_ADDR(domain->gaw - 1);
745	else	746	else
746	domain->domain.geometry.aperture_end = __DOMAIN_MAX_ADDR(domain->gaw);	747	domain->domain.geometry.aperture_end = __DOMAIN_MAX_ADDR(domain->gaw);
		748
		749	domain_update_iotlb(domain);
747	}	750	}
748		751
749	struct context_entry iommu_context_addr(struct intel_iommu iommu, u8 bus,	752	struct context_entry iommu_context_addr(struct intel_iommu iommu, u8 bus,
@@ -1464,17 +1467,22 @@ static void domain_update_iotlb(struct dmar_domain *domain) · 714 unmodified lines
1464		1467
1465	assert_spin_locked(&device_domain_lock);	1468	assert_spin_locked(&device_domain_lock);
1466		1469
1467	list_for_each_entry(info, &domain->devices, link) {	1470	list_for_each_entry(info, &domain->devices, link)
1468	struct pci_dev *pdev;	1471	if (info->ats_enabled) {
1469
1470	if (!info->dev \|\| !dev_is_pci(info->dev))
1471	continue;
1472
1473	pdev = to_pci_dev(info->dev);
1474	if (pdev->ats_enabled) {
1475	has_iotlb_device = true;	1472	has_iotlb_device = true;
1476	break;	1473	break;
1477	}	1474	}
		1475
		1476	if (!has_iotlb_device) {
		1477	struct subdev_domain_info *sinfo;
		1478
		1479	list_for_each_entry(sinfo, &domain->subdevices, link_domain) {
		1480	info = get_domain_info(sinfo->pdev);
		1481	if (info && info->ats_enabled) {
		1482	has_iotlb_device = true;
		1483	break;
		1484	}
		1485	}
1478	}	1486	}
1479		1487
1480	domain->has_iotlb_device = has_iotlb_device;	1488	domain->has_iotlb_device = has_iotlb_device;
@@ -1555,25 +1563,37 @@ static void iommu_disable_dev_iotlb(struct device_domain_info *info) · 74 unmodified lines
1555	#endif	1563	#endif
1556	}	1564	}
1557		1565
		1566	static void __iommu_flush_dev_iotlb(struct device_domain_info *info,
		1567	u64 addr, unsigned int mask)
		1568	{
		1569	u16 sid, qdep;
		1570
		1571	if (!info \|\| !info->ats_enabled)
		1572	return;
		1573
		1574	sid = info->bus << 8 \| info->devfn;
		1575	qdep = info->ats_qdep;
		1576	qi_flush_dev_iotlb(info->iommu, sid, info->pfsid,
		1577	qdep, addr, mask);
		1578	}
		1579
1558	static void iommu_flush_dev_iotlb(struct dmar_domain *domain,	1580	static void iommu_flush_dev_iotlb(struct dmar_domain *domain,
1559	u64 addr, unsigned mask)	1581	u64 addr, unsigned mask)
1560	{	1582	{
1561	u16 sid, qdep;
1562	unsigned long flags;	1583	unsigned long flags;
1563	struct device_domain_info *info;	1584	struct device_domain_info *info;
		1585	struct subdev_domain_info *sinfo;
1564		1586
1565	if (!domain->has_iotlb_device)	1587	if (!domain->has_iotlb_device)
1566	return;	1588	return;
1567		1589
1568	spin_lock_irqsave(&device_domain_lock, flags);	1590	spin_lock_irqsave(&device_domain_lock, flags);
1569	list_for_each_entry(info, &domain->devices, link) {	1591	list_for_each_entry(info, &domain->devices, link)
1570	if (!info->ats_enabled)	1592	__iommu_flush_dev_iotlb(info, addr, mask);
1571	continue;
1572		1593
1573	sid = info->bus << 8 \| info->devfn;	1594	list_for_each_entry(sinfo, &domain->subdevices, link_domain) {
1574	qdep = info->ats_qdep;	1595	info = get_domain_info(sinfo->pdev);
1575	qi_flush_dev_iotlb(info->iommu, sid, info->pfsid,	1596	__iommu_flush_dev_iotlb(info, addr, mask);
1576	qdep, addr, mask);
1577	}	1597	}
1578	spin_unlock_irqrestore(&device_domain_lock, flags);	1598	spin_unlock_irqrestore(&device_domain_lock, flags);
1579	}	1599	}
@@ -1877,6 +1897,7 @@ static struct dmar_domain *alloc_domain(int flags) · 297 unmodified lines
1877	domain->flags \|= DOMAIN_FLAG_USE_FIRST_LEVEL;	1897	domain->flags \|= DOMAIN_FLAG_USE_FIRST_LEVEL;
1878	domain->has_iotlb_device = false;	1898	domain->has_iotlb_device = false;
1879	INIT_LIST_HEAD(&domain->devices);	1899	INIT_LIST_HEAD(&domain->devices);
		1900	INIT_LIST_HEAD(&domain->subdevices);
1880		1901
1881	return domain;	1902	return domain;
1882	}	1903	}
@@ -2547,7 +2568,7 @@ static struct dmar_domain dmar_insert_one_dev_info(struct intel_iommu iommu, · 664 unmodified lines
2547	info->iommu = iommu;	2568	info->iommu = iommu;
2548	info->pasid_table = NULL;	2569	info->pasid_table = NULL;
2549	info->auxd_enabled = 0;	2570	info->auxd_enabled = 0;
2550	INIT_LIST_HEAD(&info->auxiliary_domains);	2571	INIT_LIST_HEAD(&info->subdevices);
2551		2572
2552	if (dev && dev_is_pci(dev)) {	2573	if (dev && dev_is_pci(dev)) {
2553	struct pci_dev *pdev = to_pci_dev(info->dev);	2574	struct pci_dev *pdev = to_pci_dev(info->dev);
@@ -4475,33 +4496,61 @@ is_aux_domain(struct device dev, struct iommu_domain domain) · 1921 unmodified lines
4475	domain->type == IOMMU_DOMAIN_UNMANAGED;	4496	domain->type == IOMMU_DOMAIN_UNMANAGED;
4476	}	4497	}
4477		4498
4478	static void auxiliary_link_device(struct dmar_domain *domain,	4499	static inline struct subdev_domain_info *
4479	struct device *dev)	4500	lookup_subdev_info(struct dmar_domain domain, struct device dev)
		4501	{
		4502	struct subdev_domain_info *sinfo;
		4503
		4504	if (!list_empty(&domain->subdevices)) {
		4505	list_for_each_entry(sinfo, &domain->subdevices, link_domain) {
		4506	if (sinfo->pdev == dev)
		4507	return sinfo;
		4508	}
		4509	}
		4510
		4511	return NULL;
		4512	}
		4513
		4514	static int auxiliary_link_device(struct dmar_domain *domain,
		4515	struct device *dev)
4480	{	4516	{
4481	struct device_domain_info *info = get_domain_info(dev);	4517	struct device_domain_info *info = get_domain_info(dev);
		4518	struct subdev_domain_info *sinfo = lookup_subdev_info(domain, dev);
4482		4519
4483	assert_spin_locked(&device_domain_lock);	4520	assert_spin_locked(&device_domain_lock);
4484	if (WARN_ON(!info))	4521	if (WARN_ON(!info))
4485	return;	4522	return -EINVAL;
4486		4523
4487	domain->auxd_refcnt++;	4524	if (!sinfo) {
4488	list_add(&domain->auxd, &info->auxiliary_domains);	4525	sinfo = kzalloc(sizeof(*sinfo), GFP_ATOMIC);
		4526	sinfo->domain = domain;
		4527	sinfo->pdev = dev;
		4528	list_add(&sinfo->link_phys, &info->subdevices);
		4529	list_add(&sinfo->link_domain, &domain->subdevices);
		4530	}
		4531
		4532	return ++sinfo->users;
4489	}	4533	}
4490		4534
4491	static void auxiliary_unlink_device(struct dmar_domain *domain,	4535	static int auxiliary_unlink_device(struct dmar_domain *domain,
4492	struct device *dev)	4536	struct device *dev)
4493	{	4537	{
4494	struct device_domain_info *info = get_domain_info(dev);	4538	struct device_domain_info *info = get_domain_info(dev);
		4539	struct subdev_domain_info *sinfo = lookup_subdev_info(domain, dev);
		4540	int ret;
4495		4541
4496	assert_spin_locked(&device_domain_lock);	4542	assert_spin_locked(&device_domain_lock);
4497	if (WARN_ON(!info))	4543	if (WARN_ON(!info \|\| !sinfo \|\| sinfo->users <= 0))
4498	return;	4544	return -EINVAL;
4499		4545
4500	list_del(&domain->auxd);	4546	ret = --sinfo->users;
4501	domain->auxd_refcnt--;	4547	if (!ret) {
		4548	list_del(&sinfo->link_phys);
		4549	list_del(&sinfo->link_domain);
		4550	kfree(sinfo);
		4551	}
4502		4552
4503	if (!domain->auxd_refcnt && domain->default_pasid > 0)	4553	return ret;
4504	ioasid_put(domain->default_pasid);
4505	}	4554	}
4506		4555
4507	static int aux_domain_add_dev(struct dmar_domain *domain,	4556	static int aux_domain_add_dev(struct dmar_domain *domain,
@@ -4530,6 +4579,19 @@ static int aux_domain_add_dev(struct dmar_domain *domain, · 22 unmodified lines
4530	}	4579	}
4531		4580
4532	spin_lock_irqsave(&device_domain_lock, flags);	4581	spin_lock_irqsave(&device_domain_lock, flags);
		4582	ret = auxiliary_link_device(domain, dev);
		4583	if (ret <= 0)
		4584	goto link_failed;
		4585
		4586	/*
		4587	* Subdevices from the same physical device can be attached to the
		4588	* same domain. For such cases, only the first subdevice attachment
		4589	* needs to go through the full steps in this function. So if ret >
		4590	* 1, just goto out.
		4591	*/
		4592	if (ret > 1)
		4593	goto out;
		4594
4533	/*	4595	/*
4534	* iommu->lock must be held to attach domain to iommu and setup the	4596	* iommu->lock must be held to attach domain to iommu and setup the
4535	* pasid entry for second level translation.	4597	* pasid entry for second level translation.
@@ -4548,10 +4610,9 @@ static int aux_domain_add_dev(struct dmar_domain *domain, · 12 unmodified lines
4548	domain->default_pasid);	4610	domain->default_pasid);
4549	if (ret)	4611	if (ret)
4550	goto table_failed;	4612	goto table_failed;
4551	spin_unlock(&iommu->lock);
4552
4553	auxiliary_link_device(domain, dev);
4554		4613
		4614	spin_unlock(&iommu->lock);
		4615	out:
4555	spin_unlock_irqrestore(&device_domain_lock, flags);	4616	spin_unlock_irqrestore(&device_domain_lock, flags);
4556		4617
4557	return 0;	4618	return 0;
@@ -4560,8 +4621,10 @@ table_failed: · 2 unmodified lines
4560	domain_detach_iommu(domain, iommu);	4621	domain_detach_iommu(domain, iommu);
4561	attach_failed:	4622	attach_failed:
4562	spin_unlock(&iommu->lock);	4623	spin_unlock(&iommu->lock);
		4624	auxiliary_unlink_device(domain, dev);
		4625	link_failed:
4563	spin_unlock_irqrestore(&device_domain_lock, flags);	4626	spin_unlock_irqrestore(&device_domain_lock, flags);
4564	if (!domain->auxd_refcnt && domain->default_pasid > 0)	4627	if (list_empty(&domain->subdevices) && domain->default_pasid > 0)
4565	ioasid_put(domain->default_pasid);	4628	ioasid_put(domain->default_pasid);
4566		4629
4567	return ret;	4630	return ret;
@@ -4581,14 +4644,18 @@ static void aux_domain_remove_dev(struct dmar_domain *domain, · 13 unmodified lines
4581	info = get_domain_info(dev);	4644	info = get_domain_info(dev);
4582	iommu = info->iommu;	4645	iommu = info->iommu;
4583		4646
4584	auxiliary_unlink_device(domain, dev);	4647	if (!auxiliary_unlink_device(domain, dev)) {
4585		4648	spin_lock(&iommu->lock);
4586	spin_lock(&iommu->lock);	4649	intel_pasid_tear_down_entry(iommu, dev,
4587	intel_pasid_tear_down_entry(iommu, dev, domain->default_pasid, false);	4650	domain->default_pasid, false);
4588	domain_detach_iommu(domain, iommu);	4651	domain_detach_iommu(domain, iommu);
4589	spin_unlock(&iommu->lock);	4652	spin_unlock(&iommu->lock);
		4653	}
4590		4654
4591	spin_unlock_irqrestore(&device_domain_lock, flags);	4655	spin_unlock_irqrestore(&device_domain_lock, flags);
		4656
		4657	if (list_empty(&domain->subdevices) && domain->default_pasid > 0)
		4658	ioasid_put(domain->default_pasid);
4592	}	4659	}
4593		4660
4594	static int prepare_domain_attach_device(struct iommu_domain *domain,	4661	static int prepare_domain_attach_device(struct iommu_domain *domain,

drivers/iommu/intel/irq_remapping.c+2−0

 		irq_data = irq_domain_get_irq_data(domain, virq + i);
 		irq_cfg = irqd_cfg(irq_data);
 		if (!irq_data || !irq_cfg) {
+			if (!i)
+				kfree(data);
 			ret = -EINVAL;
 			goto out_free_data;
 		}

drivers/iommu/intel/svm.c+33−12

 	iommu->flags |= VTD_FLAG_SVM_CAPABLE;
 }
-static void intel_flush_svm_range_dev (struct intel_svm *svm, struct intel_svm_dev *sdev,
+static void __flush_svm_range_dev(struct intel_svm *svm,
-				unsigned long address, unsigned long pages, int ih)
+				  struct intel_svm_dev *sdev,
+				  unsigned long address,
+				  unsigned long pages, int ih)
 {
 	struct qi_desc desc;
 	}
 	desc.qw2 = 0;
 	desc.qw3 = 0;
-	qi_submit_sync(svm->iommu, &desc, 1, 0);
+	qi_submit_sync(sdev->iommu, &desc, 1, 0);
 	if (sdev->dev_iotlb) {
 		desc.qw0 = QI_DEV_EIOTLB_PASID(svm->pasid) |
 		}
 		desc.qw2 = 0;
 		desc.qw3 = 0;
-		qi_submit_sync(svm->iommu, &desc, 1, 0);
+		qi_submit_sync(sdev->iommu, &desc, 1, 0);
+	}
+}
+static void intel_flush_svm_range_dev(struct intel_svm *svm,
+				      struct intel_svm_dev *sdev,
+				      unsigned long address,
+				      unsigned long pages, int ih)
+{
+	unsigned long shift = ilog2(__roundup_pow_of_two(pages));
+	unsigned long align = (1ULL << (VTD_PAGE_SHIFT + shift));
+	unsigned long start = ALIGN_DOWN(address, align);
+	unsigned long end = ALIGN(address + (pages << VTD_PAGE_SHIFT), align);
+	while (start < end) {
+		__flush_svm_range_dev(svm, sdev, start, align >> VTD_PAGE_SHIFT, ih);
+		start += align;
 	}
 }
 	 */
 	rcu_read_lock();
 	list_for_each_entry_rcu(sdev, &svm->devs, list)
-		intel_pasid_tear_down_entry(svm->iommu, sdev->dev,
+		intel_pasid_tear_down_entry(sdev->iommu, sdev->dev,
 					    svm->pasid, true);
 	rcu_read_unlock();
 	struct dmar_domain *dmar_domain;
 	struct device_domain_info *info;
 	struct intel_svm *svm = NULL;
+	unsigned long iflags;
 	int ret = 0;
 	if (WARN_ON(!iommu) || !data)
 	}
 	sdev->dev = dev;
 	sdev->sid = PCI_DEVID(info->bus, info->devfn);
+	sdev->iommu = iommu;
 	/* Only count users if device has aux domains */
 	if (iommu_dev_feature_enabled(dev, IOMMU_DEV_FEAT_AUX))
 	 * each bind of a new device even with an existing PASID, we need to
 	 * call the nested mode setup function here.
 	 */
-	spin_lock(&iommu->lock);
+	spin_lock_irqsave(&iommu->lock, iflags);
 	ret = intel_pasid_setup_nested(iommu, dev,
 				       (pgd_t *)(uintptr_t)data->gpgd,
 				       data->hpasid, &data->vendor.vtd, dmar_domain,
 				       data->addr_width);
-	spin_unlock(&iommu->lock);
+	spin_unlock_irqrestore(&iommu->lock, iflags);
 	if (ret) {
 		dev_err_ratelimited(dev, "Failed to set up PASID %llu in nested mode, Err %d\n",
 				    data->hpasid, ret);
 	struct device_domain_info *info;
 	struct intel_svm_dev *sdev;
 	struct intel_svm *svm = NULL;
+	unsigned long iflags;
 	int pasid_max;
 	int ret;
 		goto out;
 	}
 	sdev->dev = dev;
+	sdev->iommu = iommu;
 	ret = intel_iommu_enable_pasid(iommu, dev);
 	if (ret) {
 			kfree(sdev);
 			goto out;
 		}
-		svm->iommu = iommu;
 		if (pasid_max > intel_pasid_max_id)
 			pasid_max = intel_pasid_max_id;
 			}
 		}
-		spin_lock(&iommu->lock);
+		spin_lock_irqsave(&iommu->lock, iflags);
 		ret = intel_pasid_setup_first_level(iommu, dev,
 				mm ? mm->pgd : init_mm.pgd,
 				svm->pasid, FLPT_DEFAULT_DID,
 				(mm ? 0 : PASID_FLAG_SUPERVISOR_MODE) |
 				(cpu_feature_enabled(X86_FEATURE_LA57) ?
 				 PASID_FLAG_FL5LP : 0));
-		spin_unlock(&iommu->lock);
+		spin_unlock_irqrestore(&iommu->lock, iflags);
 		if (ret) {
 			if (mm)
 				mmu_notifier_unregister(&svm->notifier, mm);
 		 * Binding a new device with existing PASID, need to setup
 		 * the PASID entry.
 		 */
-		spin_lock(&iommu->lock);
+		spin_lock_irqsave(&iommu->lock, iflags);
 		ret = intel_pasid_setup_first_level(iommu, dev,
 						mm ? mm->pgd : init_mm.pgd,
 						svm->pasid, FLPT_DEFAULT_DID,
 						(mm ? 0 : PASID_FLAG_SUPERVISOR_MODE) |
 						(cpu_feature_enabled(X86_FEATURE_LA57) ?
 						PASID_FLAG_FL5LP : 0));
-		spin_unlock(&iommu->lock);
+		spin_unlock_irqrestore(&iommu->lock, iflags);
 		if (ret) {
 			kfree(sdev);
 			goto out;

drivers/iommu/iova.c+4−4

@@ -358,7 +358,7 @@ static void private_free_iova(struct iova_domain iovad, struct iova iova) · 357 unmodified lines
358	* @iovad: - iova domain in question.	358	* @iovad: - iova domain in question.
359	* @pfn: - page frame number	359	* @pfn: - page frame number
360	* This function finds and returns an iova belonging to the	360	* This function finds and returns an iova belonging to the
361	* given doamin which matches the given pfn.	361	* given domain which matches the given pfn.
362	*/	362	*/
363	struct iova find_iova(struct iova_domain iovad, unsigned long pfn)	363	struct iova find_iova(struct iova_domain iovad, unsigned long pfn)
364	{	364	{
@@ -601,7 +601,7 @@ void queue_iova(struct iova_domain *iovad, · 236 unmodified lines
601	EXPORT_SYMBOL_GPL(queue_iova);	601	EXPORT_SYMBOL_GPL(queue_iova);
602		602
603	/**	603	/**
604	* put_iova_domain - destroys the iova doamin	604	* put_iova_domain - destroys the iova domain
605	* @iovad: - iova domain in question.	605	* @iovad: - iova domain in question.
606	* All the iova's in that domain are destroyed.	606	* All the iova's in that domain are destroyed.
607	*/	607	*/
@@ -712,9 +712,9 @@ EXPORT_SYMBOL_GPL(reserve_iova); · 104 unmodified lines
712		712
713	/**	713	/**
714	* copy_reserved_iova - copies the reserved between domains	714	* copy_reserved_iova - copies the reserved between domains
715	* @from: - source doamin from where to copy	715	* @from: - source domain from where to copy
716	* @to: - destination domin where to copy	716	* @to: - destination domin where to copy
717	* This function copies reserved iova's from one doamin to	717	* This function copies reserved iova's from one domain to
718	* other.	718	* other.
719	*/	719	*/
720	void	720	void

drivers/isdn/mISDN/Kconfig+1−0

@@ -13,6 +13,7 @@ if MISDN != n · 12 unmodified lines
13	config MISDN_DSP	13	config MISDN_DSP
14	tristate "Digital Audio Processing of transparent data"	14	tristate "Digital Audio Processing of transparent data"
15	depends on MISDN	15	depends on MISDN
		16	select BITREVERSE
16	help	17	help
17	Enable support for digital audio processing capability.	18	Enable support for digital audio processing capability.
18		19

drivers/lightnvm/Kconfig+1−0

@@ -19,6 +19,7 @@ if NVM · 18 unmodified lines
19		19
20	config NVM_PBLK	20	config NVM_PBLK
21	tristate "Physical Block Device Open-Channel SSD target"	21	tristate "Physical Block Device Open-Channel SSD target"
		22	select CRC32
22	help	23	help
23	Allows an open-channel SSD to be exposed as a block device to the	24	Allows an open-channel SSD to be exposed as a block device to the
24	host. The target assumes the device exposes raw flash and must be	25	host. The target assumes the device exposes raw flash and must be

drivers/md/Kconfig+2−0

 	select BLK_DEV_INTEGRITY
 	select DM_BUFIO
 	select CRYPTO
+	select CRYPTO_SKCIPHER
 	select ASYNC_XOR
 	help
 	  This device-mapper target emulates a block device that has
 	tristate "Drive-managed zoned block device target support"
 	depends on BLK_DEV_DM
 	depends on BLK_DEV_ZONED
+	select CRC32
 	help
 	  This device-mapper target takes a host-managed or host-aware zoned
 	  block device and exposes most of its capacity as a regular block

drivers/md/bcache/features.c+1−1

@@ -17,7 +17,7 @@ struct feature { · 16 unmodified lines
17	};	17	};
18		18
19	static struct feature feature_list[] = {	19	static struct feature feature_list[] = {
20	{BCH_FEATURE_INCOMPAT, BCH_FEATURE_INCOMPAT_LARGE_BUCKET,	20	{BCH_FEATURE_INCOMPAT, BCH_FEATURE_INCOMPAT_LOG_LARGE_BUCKET_SIZE,
21	"large_bucket"},	21	"large_bucket"},
22	{0, 0, 0 },	22	{0, 0, 0 },
23	};	23	};

drivers/md/bcache/features.h+25−5

@@ -13,11 +13,15 @@ · 12 unmodified lines
13		13
14	/* Feature set definition */	14	/* Feature set definition */
15	/* Incompat feature set */	15	/* Incompat feature set */
16	#define BCH_FEATURE_INCOMPAT_LARGE_BUCKET 0x0001 /* 32bit bucket size */	16	/* 32bit bucket size, obsoleted */
		17	#define BCH_FEATURE_INCOMPAT_OBSO_LARGE_BUCKET 0x0001
		18	/* real bucket size is (1 << bucket_size) */
		19	#define BCH_FEATURE_INCOMPAT_LOG_LARGE_BUCKET_SIZE 0x0002
17		20
18	#define BCH_FEATURE_COMPAT_SUUP 0	21	#define BCH_FEATURE_COMPAT_SUPP 0
19	#define BCH_FEATURE_RO_COMPAT_SUUP 0	22	#define BCH_FEATURE_RO_COMPAT_SUPP 0
20	#define BCH_FEATURE_INCOMPAT_SUUP BCH_FEATURE_INCOMPAT_LARGE_BUCKET	23	#define BCH_FEATURE_INCOMPAT_SUPP (BCH_FEATURE_INCOMPAT_OBSO_LARGE_BUCKET\| \
		24	BCH_FEATURE_INCOMPAT_LOG_LARGE_BUCKET_SIZE)
21		25
22	#define BCH_HAS_COMPAT_FEATURE(sb, mask) \	26	#define BCH_HAS_COMPAT_FEATURE(sb, mask) \
23	((sb)->feature_compat & (mask))	27	((sb)->feature_compat & (mask))
@@ -77,7 +81,23 @@ static inline void bch_clear_feature_##name(struct cache_sb *sb) \ · 53 unmodified lines
77	~BCH##_FEATURE_INCOMPAT_##flagname; \	81	~BCH##_FEATURE_INCOMPAT_##flagname; \
78	}	82	}
79		83
80	BCH_FEATURE_INCOMPAT_FUNCS(large_bucket, LARGE_BUCKET);	84	BCH_FEATURE_INCOMPAT_FUNCS(obso_large_bucket, OBSO_LARGE_BUCKET);
		85	BCH_FEATURE_INCOMPAT_FUNCS(large_bucket, LOG_LARGE_BUCKET_SIZE);
		86
		87	static inline bool bch_has_unknown_compat_features(struct cache_sb *sb)
		88	{
		89	return ((sb->feature_compat & ~BCH_FEATURE_COMPAT_SUPP) != 0);
		90	}
		91
		92	static inline bool bch_has_unknown_ro_compat_features(struct cache_sb *sb)
		93	{
		94	return ((sb->feature_ro_compat & ~BCH_FEATURE_RO_COMPAT_SUPP) != 0);
		95	}
		96
		97	static inline bool bch_has_unknown_incompat_features(struct cache_sb *sb)
		98	{
		99	return ((sb->feature_incompat & ~BCH_FEATURE_INCOMPAT_SUPP) != 0);
		100	}
81		101
82	int bch_print_cache_set_feature_compat(struct cache_set c, char buf, int size);	102	int bch_print_cache_set_feature_compat(struct cache_set c, char buf, int size);
83	int bch_print_cache_set_feature_ro_compat(struct cache_set c, char buf, int size);	103	int bch_print_cache_set_feature_ro_compat(struct cache_set c, char buf, int size);

drivers/md/bcache/super.c+49−4

@@ -64,9 +64,25 @@ static unsigned int get_bucket_size(struct cache_sb sb, struct cache_sb_disk s · 63 unmodified lines
64	{	64	{
65	unsigned int bucket_size = le16_to_cpu(s->bucket_size);	65	unsigned int bucket_size = le16_to_cpu(s->bucket_size);
66		66
67	if (sb->version >= BCACHE_SB_VERSION_CDEV_WITH_FEATURES &&	67	if (sb->version >= BCACHE_SB_VERSION_CDEV_WITH_FEATURES) {
68	bch_has_feature_large_bucket(sb))	68	if (bch_has_feature_large_bucket(sb)) {
69	bucket_size \|= le16_to_cpu(s->bucket_size_hi) << 16;	69	unsigned int max, order;
		70
		71	max = sizeof(unsigned int) * BITS_PER_BYTE - 1;
		72	order = le16_to_cpu(s->bucket_size);
		73	/*
		74	* bcache tool will make sure the overflow won't
		75	* happen, an error message here is enough.
		76	*/
		77	if (order > max)
		78	pr_err("Bucket size (1 << %u) overflows\n",
		79	order);
		80	bucket_size = 1 << order;
		81	} else if (bch_has_feature_obso_large_bucket(sb)) {
		82	bucket_size +=
		83	le16_to_cpu(s->obso_bucket_size_hi) << 16;
		84	}
		85	}
70		86
71	return bucket_size;	87	return bucket_size;
72	}	88	}
@@ -228,6 +244,20 @@ static const char read_super(struct cache_sb sb, struct block_device *bdev, · 155 unmodified lines
228	sb->feature_compat = le64_to_cpu(s->feature_compat);	244	sb->feature_compat = le64_to_cpu(s->feature_compat);
229	sb->feature_incompat = le64_to_cpu(s->feature_incompat);	245	sb->feature_incompat = le64_to_cpu(s->feature_incompat);
230	sb->feature_ro_compat = le64_to_cpu(s->feature_ro_compat);	246	sb->feature_ro_compat = le64_to_cpu(s->feature_ro_compat);
		247
		248	/* Check incompatible features */
		249	err = "Unsupported compatible feature found";
		250	if (bch_has_unknown_compat_features(sb))
		251	goto err;
		252
		253	err = "Unsupported read-only compatible feature found";
		254	if (bch_has_unknown_ro_compat_features(sb))
		255	goto err;
		256
		257	err = "Unsupported incompatible feature found";
		258	if (bch_has_unknown_incompat_features(sb))
		259	goto err;
		260
231	err = read_super_common(sb, bdev, s);	261	err = read_super_common(sb, bdev, s);
232	if (err)	262	if (err)
233	goto err;	263	goto err;
@@ -1302,6 +1332,12 @@ int bch_cached_dev_attach(struct cached_dev dc, struct cache_set c, · 1068 unmodified lines
1302	bcache_device_link(&dc->disk, c, "bdev");	1332	bcache_device_link(&dc->disk, c, "bdev");
1303	atomic_inc(&c->attached_dev_nr);	1333	atomic_inc(&c->attached_dev_nr);
1304		1334
		1335	if (bch_has_feature_obso_large_bucket(&(c->cache->sb))) {
		1336	pr_err("The obsoleted large bucket layout is unsupported, set the bcache device into read-only\n");
		1337	pr_err("Please update to the latest bcache-tools to create the cache device\n");
		1338	set_disk_ro(dc->disk.disk, 1);
		1339	}
		1340
1305	/* Allow the writeback thread to proceed */	1341	/* Allow the writeback thread to proceed */
1306	up_write(&dc->writeback_lock);	1342	up_write(&dc->writeback_lock);
1307		1343
@@ -1524,6 +1560,12 @@ static int flash_dev_run(struct cache_set c, struct uuid_entry u) · 216 unmodified lines
1524		1560
1525	bcache_device_link(d, c, "volume");	1561	bcache_device_link(d, c, "volume");
1526		1562
		1563	if (bch_has_feature_obso_large_bucket(&c->cache->sb)) {
		1564	pr_err("The obsoleted large bucket layout is unsupported, set the bcache device into read-only\n");
		1565	pr_err("Please update to the latest bcache-tools to create the cache device\n");
		1566	set_disk_ro(d->disk, 1);
		1567	}
		1568
1527	return 0;	1569	return 0;
1528	err:	1570	err:
1529	kobject_put(&d->kobj);	1571	kobject_put(&d->kobj);
@@ -2083,6 +2125,9 @@ static int run_cache_set(struct cache_set *c) · 553 unmodified lines
2083	c->cache->sb.last_mount = (u32)ktime_get_real_seconds();	2125	c->cache->sb.last_mount = (u32)ktime_get_real_seconds();
2084	bcache_write_super(c);	2126	bcache_write_super(c);
2085		2127
		2128	if (bch_has_feature_obso_large_bucket(&c->cache->sb))
		2129	pr_err("Detect obsoleted large bucket layout, all attached bcache device will be read-only\n");
		2130
2086	list_for_each_entry_safe(dc, t, &uncached_devices, list)	2131	list_for_each_entry_safe(dc, t, &uncached_devices, list)
2087	bch_cached_dev_attach(dc, c, NULL);	2132	bch_cached_dev_attach(dc, c, NULL);
2088		2133
@@ -2644,8 +2689,8 @@ static ssize_t bch_pending_bdevs_cleanup(struct kobject *k, · 555 unmodified lines
2644	}	2689	}
2645		2690
2646	list_for_each_entry_safe(pdev, tpdev, &pending_devs, list) {	2691	list_for_each_entry_safe(pdev, tpdev, &pending_devs, list) {
		2692	char *pdev_set_uuid = pdev->dc->sb.set_uuid;
2647	list_for_each_entry_safe(c, tc, &bch_cache_sets, list) {	2693	list_for_each_entry_safe(c, tc, &bch_cache_sets, list) {
2648	char *pdev_set_uuid = pdev->dc->sb.set_uuid;
2649	char *set_uuid = c->set_uuid;	2694	char *set_uuid = c->set_uuid;
2650		2695
2651	if (!memcmp(pdev_set_uuid, set_uuid, 16)) {	2696	if (!memcmp(pdev_set_uuid, set_uuid, 16)) {

drivers/md/dm-bufio.c+6−0

 }
 EXPORT_SYMBOL_GPL(dm_bufio_get_device_size);
+struct dm_io_client *dm_bufio_get_dm_io_client(struct dm_bufio_client *c)
+{
+	return c->dm_io;
+}
+EXPORT_SYMBOL_GPL(dm_bufio_get_dm_io_client);
 sector_t dm_bufio_get_block_number(struct dm_buffer *b)
 {
 	return b->block;

drivers/md/dm-crypt.c+155−22

@@ -1454,13 +1454,16 @@ static int crypt_convert_block_skcipher(struct crypt_config *cc, · 1453 unmodified lines
1454	static void kcryptd_async_done(struct crypto_async_request *async_req,	1454	static void kcryptd_async_done(struct crypto_async_request *async_req,
1455	int error);	1455	int error);
1456		1456
1457	static void crypt_alloc_req_skcipher(struct crypt_config *cc,	1457	static int crypt_alloc_req_skcipher(struct crypt_config *cc,
1458	struct convert_context *ctx)	1458	struct convert_context *ctx)
1459	{	1459	{
1460	unsigned key_index = ctx->cc_sector & (cc->tfms_count - 1);	1460	unsigned key_index = ctx->cc_sector & (cc->tfms_count - 1);
1461		1461
1462	if (!ctx->r.req)	1462	if (!ctx->r.req) {
1463	ctx->r.req = mempool_alloc(&cc->req_pool, GFP_NOIO);	1463	ctx->r.req = mempool_alloc(&cc->req_pool, in_interrupt() ? GFP_ATOMIC : GFP_NOIO);
		1464	if (!ctx->r.req)
		1465	return -ENOMEM;
		1466	}
1464		1467
1465	skcipher_request_set_tfm(ctx->r.req, cc->cipher_tfm.tfms[key_index]);	1468	skcipher_request_set_tfm(ctx->r.req, cc->cipher_tfm.tfms[key_index]);
1466		1469
@@ -1471,13 +1474,18 @@ static void crypt_alloc_req_skcipher(struct crypt_config *cc, · 4 unmodified lines
1471	skcipher_request_set_callback(ctx->r.req,	1474	skcipher_request_set_callback(ctx->r.req,
1472	CRYPTO_TFM_REQ_MAY_BACKLOG,	1475	CRYPTO_TFM_REQ_MAY_BACKLOG,
1473	kcryptd_async_done, dmreq_of_req(cc, ctx->r.req));	1476	kcryptd_async_done, dmreq_of_req(cc, ctx->r.req));
		1477
		1478	return 0;
1474	}	1479	}
1475		1480
1476	static void crypt_alloc_req_aead(struct crypt_config *cc,	1481	static int crypt_alloc_req_aead(struct crypt_config *cc,
1477	struct convert_context *ctx)	1482	struct convert_context *ctx)
1478	{	1483	{
1479	if (!ctx->r.req_aead)	1484	if (!ctx->r.req) {
1480	ctx->r.req_aead = mempool_alloc(&cc->req_pool, GFP_NOIO);	1485	ctx->r.req = mempool_alloc(&cc->req_pool, in_interrupt() ? GFP_ATOMIC : GFP_NOIO);
		1486	if (!ctx->r.req)
		1487	return -ENOMEM;
		1488	}
1481		1489
1482	aead_request_set_tfm(ctx->r.req_aead, cc->cipher_tfm.tfms_aead[0]);	1490	aead_request_set_tfm(ctx->r.req_aead, cc->cipher_tfm.tfms_aead[0]);
1483		1491
@@ -1488,15 +1496,17 @@ static void crypt_alloc_req_aead(struct crypt_config *cc, · 4 unmodified lines
1488	aead_request_set_callback(ctx->r.req_aead,	1496	aead_request_set_callback(ctx->r.req_aead,
1489	CRYPTO_TFM_REQ_MAY_BACKLOG,	1497	CRYPTO_TFM_REQ_MAY_BACKLOG,
1490	kcryptd_async_done, dmreq_of_req(cc, ctx->r.req_aead));	1498	kcryptd_async_done, dmreq_of_req(cc, ctx->r.req_aead));
		1499
		1500	return 0;
1491	}	1501	}
1492		1502
1493	static void crypt_alloc_req(struct crypt_config *cc,	1503	static int crypt_alloc_req(struct crypt_config *cc,
1494	struct convert_context *ctx)	1504	struct convert_context *ctx)
1495	{	1505	{
1496	if (crypt_integrity_aead(cc))	1506	if (crypt_integrity_aead(cc))
1497	crypt_alloc_req_aead(cc, ctx);	1507	return crypt_alloc_req_aead(cc, ctx);
1498	else	1508	else
1499	crypt_alloc_req_skcipher(cc, ctx);	1509	return crypt_alloc_req_skcipher(cc, ctx);
1500	}	1510	}
1501		1511
1502	static void crypt_free_req_skcipher(struct crypt_config *cc,	1512	static void crypt_free_req_skcipher(struct crypt_config *cc,
@@ -1529,17 +1539,28 @@ static void crypt_free_req(struct crypt_config cc, void req, struct bio *base_ · 26 unmodified lines
1529	* Encrypt / decrypt data from one bio to another one (can be the same one)	1539	* Encrypt / decrypt data from one bio to another one (can be the same one)
1530	*/	1540	*/
1531	static blk_status_t crypt_convert(struct crypt_config *cc,	1541	static blk_status_t crypt_convert(struct crypt_config *cc,
1532	struct convert_context *ctx, bool atomic)	1542	struct convert_context *ctx, bool atomic, bool reset_pending)
1533	{	1543	{
1534	unsigned int tag_offset = 0;	1544	unsigned int tag_offset = 0;
1535	unsigned int sector_step = cc->sector_size >> SECTOR_SHIFT;	1545	unsigned int sector_step = cc->sector_size >> SECTOR_SHIFT;
1536	int r;	1546	int r;
1537		1547
1538	atomic_set(&ctx->cc_pending, 1);	1548	/*
		1549	* if reset_pending is set we are dealing with the bio for the first time,
		1550	* else we're continuing to work on the previous bio, so don't mess with
		1551	* the cc_pending counter
		1552	*/
		1553	if (reset_pending)
		1554	atomic_set(&ctx->cc_pending, 1);
1539		1555
1540	while (ctx->iter_in.bi_size && ctx->iter_out.bi_size) {	1556	while (ctx->iter_in.bi_size && ctx->iter_out.bi_size) {
1541		1557
1542	crypt_alloc_req(cc, ctx);	1558	r = crypt_alloc_req(cc, ctx);
		1559	if (r) {
		1560	complete(&ctx->restart);
		1561	return BLK_STS_DEV_RESOURCE;
		1562	}
		1563
1543	atomic_inc(&ctx->cc_pending);	1564	atomic_inc(&ctx->cc_pending);
1544		1565
1545	if (crypt_integrity_aead(cc))	1566	if (crypt_integrity_aead(cc))
@@ -1553,7 +1574,25 @@ static blk_status_t crypt_convert(struct crypt_config *cc, · 7 unmodified lines
1553	* but the driver request queue is full, let's wait.	1574	* but the driver request queue is full, let's wait.
1554	*/	1575	*/
1555	case -EBUSY:	1576	case -EBUSY:
1556	wait_for_completion(&ctx->restart);	1577	if (in_interrupt()) {
		1578	if (try_wait_for_completion(&ctx->restart)) {
		1579	/*
		1580	* we don't have to block to wait for completion,
		1581	* so proceed
		1582	*/
		1583	} else {
		1584	/*
		1585	* we can't wait for completion without blocking
		1586	* exit and continue processing in a workqueue
		1587	*/
		1588	ctx->r.req = NULL;
		1589	ctx->cc_sector += sector_step;
		1590	tag_offset++;
		1591	return BLK_STS_DEV_RESOURCE;
		1592	}
		1593	} else {
		1594	wait_for_completion(&ctx->restart);
		1595	}
1557	reinit_completion(&ctx->restart);	1596	reinit_completion(&ctx->restart);
1558	fallthrough;	1597	fallthrough;
1559	/*	1598	/*
@@ -1691,6 +1730,12 @@ static void crypt_inc_pending(struct dm_crypt_io *io) · 131 unmodified lines
1691	atomic_inc(&io->io_pending);	1730	atomic_inc(&io->io_pending);
1692	}	1731	}
1693		1732
		1733	static void kcryptd_io_bio_endio(struct work_struct *work)
		1734	{
		1735	struct dm_crypt_io *io = container_of(work, struct dm_crypt_io, work);
		1736	bio_endio(io->base_bio);
		1737	}
		1738
1694	/*	1739	/*
1695	* One of the bios was finished. Check for completion of	1740	* One of the bios was finished. Check for completion of
1696	* the whole request and correctly clean up the buffer.	1741	* the whole request and correctly clean up the buffer.
@@ -1713,7 +1758,23 @@ static void crypt_dec_pending(struct dm_crypt_io *io) · 16 unmodified lines
1713	kfree(io->integrity_metadata);	1758	kfree(io->integrity_metadata);
1714		1759
1715	base_bio->bi_status = error;	1760	base_bio->bi_status = error;
1716	bio_endio(base_bio);	1761
		1762	/*
		1763	* If we are running this function from our tasklet,
		1764	* we can't call bio_endio() here, because it will call
		1765	* clone_endio() from dm.c, which in turn will
		1766	* free the current struct dm_crypt_io structure with
		1767	* our tasklet. In this case we need to delay bio_endio()
		1768	* execution to after the tasklet is done and dequeued.
		1769	*/
		1770	if (tasklet_trylock(&io->tasklet)) {
		1771	tasklet_unlock(&io->tasklet);
		1772	bio_endio(base_bio);
		1773	return;
		1774	}
		1775
		1776	INIT_WORK(&io->work, kcryptd_io_bio_endio);
		1777	queue_work(cc->io_queue, &io->work);
1717	}	1778	}
1718		1779
1719	/*	1780	/*
@@ -1945,6 +2006,37 @@ static bool kcryptd_crypt_write_inline(struct crypt_config *cc, · 225 unmodified lines
1945	}	2006	}
1946	}	2007	}
1947		2008
		2009	static void kcryptd_crypt_write_continue(struct work_struct *work)
		2010	{
		2011	struct dm_crypt_io *io = container_of(work, struct dm_crypt_io, work);
		2012	struct crypt_config *cc = io->cc;
		2013	struct convert_context *ctx = &io->ctx;
		2014	int crypt_finished;
		2015	sector_t sector = io->sector;
		2016	blk_status_t r;
		2017
		2018	wait_for_completion(&ctx->restart);
		2019	reinit_completion(&ctx->restart);
		2020
		2021	r = crypt_convert(cc, &io->ctx, true, false);
		2022	if (r)
		2023	io->error = r;
		2024	crypt_finished = atomic_dec_and_test(&ctx->cc_pending);
		2025	if (!crypt_finished && kcryptd_crypt_write_inline(cc, ctx)) {
		2026	/* Wait for completion signaled by kcryptd_async_done() */
		2027	wait_for_completion(&ctx->restart);
		2028	crypt_finished = 1;
		2029	}
		2030
		2031	/* Encryption was already finished, submit io now */
		2032	if (crypt_finished) {
		2033	kcryptd_crypt_write_io_submit(io, 0);
		2034	io->sector = sector;
		2035	}
		2036
		2037	crypt_dec_pending(io);
		2038	}
		2039
1948	static void kcryptd_crypt_write_convert(struct dm_crypt_io *io)	2040	static void kcryptd_crypt_write_convert(struct dm_crypt_io *io)
1949	{	2041	{
1950	struct crypt_config *cc = io->cc;	2042	struct crypt_config *cc = io->cc;
@@ -1973,7 +2065,17 @@ static void kcryptd_crypt_write_convert(struct dm_crypt_io *io) · 22 unmodified lines
1973		2065
1974	crypt_inc_pending(io);	2066	crypt_inc_pending(io);
1975	r = crypt_convert(cc, ctx,	2067	r = crypt_convert(cc, ctx,
1976	test_bit(DM_CRYPT_NO_WRITE_WORKQUEUE, &cc->flags));	2068	test_bit(DM_CRYPT_NO_WRITE_WORKQUEUE, &cc->flags), true);
		2069	/*
		2070	* Crypto API backlogged the request, because its queue was full
		2071	* and we're in softirq context, so continue from a workqueue
		2072	* (TODO: is it actually possible to be in softirq in the write path?)
		2073	*/
		2074	if (r == BLK_STS_DEV_RESOURCE) {
		2075	INIT_WORK(&io->work, kcryptd_crypt_write_continue);
		2076	queue_work(cc->crypt_queue, &io->work);
		2077	return;
		2078	}
1977	if (r)	2079	if (r)
1978	io->error = r;	2080	io->error = r;
1979	crypt_finished = atomic_dec_and_test(&ctx->cc_pending);	2081	crypt_finished = atomic_dec_and_test(&ctx->cc_pending);
@@ -1998,6 +2100,25 @@ static void kcryptd_crypt_read_done(struct dm_crypt_io *io) · 18 unmodified lines
1998	crypt_dec_pending(io);	2100	crypt_dec_pending(io);
1999	}	2101	}
2000		2102
		2103	static void kcryptd_crypt_read_continue(struct work_struct *work)
		2104	{
		2105	struct dm_crypt_io *io = container_of(work, struct dm_crypt_io, work);
		2106	struct crypt_config *cc = io->cc;
		2107	blk_status_t r;
		2108
		2109	wait_for_completion(&io->ctx.restart);
		2110	reinit_completion(&io->ctx.restart);
		2111
		2112	r = crypt_convert(cc, &io->ctx, true, false);
		2113	if (r)
		2114	io->error = r;
		2115
		2116	if (atomic_dec_and_test(&io->ctx.cc_pending))
		2117	kcryptd_crypt_read_done(io);
		2118
		2119	crypt_dec_pending(io);
		2120	}
		2121
2001	static void kcryptd_crypt_read_convert(struct dm_crypt_io *io)	2122	static void kcryptd_crypt_read_convert(struct dm_crypt_io *io)
2002	{	2123	{
2003	struct crypt_config *cc = io->cc;	2124	struct crypt_config *cc = io->cc;
@@ -2009,7 +2130,16 @@ static void kcryptd_crypt_read_convert(struct dm_crypt_io *io) · 5 unmodified lines
2009	io->sector);	2130	io->sector);
2010		2131
2011	r = crypt_convert(cc, &io->ctx,	2132	r = crypt_convert(cc, &io->ctx,
2012	test_bit(DM_CRYPT_NO_READ_WORKQUEUE, &cc->flags));	2133	test_bit(DM_CRYPT_NO_READ_WORKQUEUE, &cc->flags), true);
		2134	/*
		2135	* Crypto API backlogged the request, because its queue was full
		2136	* and we're in softirq context, so continue from a workqueue
		2137	*/
		2138	if (r == BLK_STS_DEV_RESOURCE) {
		2139	INIT_WORK(&io->work, kcryptd_crypt_read_continue);
		2140	queue_work(cc->crypt_queue, &io->work);
		2141	return;
		2142	}
2013	if (r)	2143	if (r)
2014	io->error = r;	2144	io->error = r;
2015		2145
@@ -2091,8 +2221,12 @@ static void kcryptd_queue_crypt(struct dm_crypt_io *io) · 75 unmodified lines
2091		2221
2092	if ((bio_data_dir(io->base_bio) == READ && test_bit(DM_CRYPT_NO_READ_WORKQUEUE, &cc->flags)) \|\|	2222	if ((bio_data_dir(io->base_bio) == READ && test_bit(DM_CRYPT_NO_READ_WORKQUEUE, &cc->flags)) \|\|
2093	(bio_data_dir(io->base_bio) == WRITE && test_bit(DM_CRYPT_NO_WRITE_WORKQUEUE, &cc->flags))) {	2223	(bio_data_dir(io->base_bio) == WRITE && test_bit(DM_CRYPT_NO_WRITE_WORKQUEUE, &cc->flags))) {
2094	if (in_irq()) {	2224	/*
2095	/* Crypto API's "skcipher_walk_first() refuses to work in hard IRQ context */	2225	* in_irq(): Crypto API's skcipher_walk_first() refuses to work in hard IRQ context.
		2226	* irqs_disabled(): the kernel may run some IO completion from the idle thread, but
		2227	* it is being executed with irqs disabled.
		2228	*/
		2229	if (in_irq() \|\| irqs_disabled()) {
2096	tasklet_init(&io->tasklet, kcryptd_crypt_tasklet, (unsigned long)&io->work);	2230	tasklet_init(&io->tasklet, kcryptd_crypt_tasklet, (unsigned long)&io->work);
2097	tasklet_schedule(&io->tasklet);	2231	tasklet_schedule(&io->tasklet);
2098	return;	2232	return;
@@ -3166,12 +3300,11 @@ static int crypt_ctr(struct dm_target ti, unsigned int argc, char *argv) · 1067 unmodified lines
3166	}	3300	}
3167		3301
3168	if (test_bit(DM_CRYPT_SAME_CPU, &cc->flags))	3302	if (test_bit(DM_CRYPT_SAME_CPU, &cc->flags))
3169	cc->crypt_queue = alloc_workqueue("kcryptd-%s", WQ_CPU_INTENSIVE \| WQ_MEM_RECLAIM,	3303	cc->crypt_queue = alloc_workqueue("kcryptd/%s", WQ_CPU_INTENSIVE \| WQ_MEM_RECLAIM,
3170	1, devname);	3304	1, devname);
3171	else	3305	else
3172	cc->crypt_queue = alloc_workqueue("kcryptd-%s",	3306	cc->crypt_queue = alloc_workqueue("kcryptd/%s",
3173	WQ_CPU_INTENSIVE \| WQ_MEM_RECLAIM \|	3307	WQ_CPU_INTENSIVE \| WQ_MEM_RECLAIM \| WQ_UNBOUND,
3174	WQ_UNBOUND \| WQ_SYSFS,
3175	num_online_cpus(), devname);	3308	num_online_cpus(), devname);
3176	if (!cc->crypt_queue) {	3309	if (!cc->crypt_queue) {
3177	ti->error = "Couldn't create kcryptd queue";	3310	ti->error = "Couldn't create kcryptd queue";

drivers/md/dm-integrity.c+50−12

 #undef MAY_BE_HASH
 }
-static void dm_integrity_flush_buffers(struct dm_integrity_c *ic)
+struct flush_request {
+	struct dm_io_request io_req;
+	struct dm_io_region io_reg;
+	struct dm_integrity_c *ic;
+	struct completion comp;
+};
+static void flush_notify(unsigned long error, void *fr_)
+{
+	struct flush_request *fr = fr_;
+	if (unlikely(error != 0))
+		dm_integrity_io_error(fr->ic, "flusing disk cache", -EIO);
+	complete(&fr->comp);
+}
+static void dm_integrity_flush_buffers(struct dm_integrity_c *ic, bool flush_data)
 {
 	int r;
+	struct flush_request fr;
+	if (!ic->meta_dev)
+		flush_data = false;
+	if (flush_data) {
+		fr.io_req.bi_op = REQ_OP_WRITE,
+		fr.io_req.bi_op_flags = REQ_PREFLUSH | REQ_SYNC,
+		fr.io_req.mem.type = DM_IO_KMEM,
+		fr.io_req.mem.ptr.addr = NULL,
+		fr.io_req.notify.fn = flush_notify,
+		fr.io_req.notify.context = &fr;
+		fr.io_req.client = dm_bufio_get_dm_io_client(ic->bufio),
+		fr.io_reg.bdev = ic->dev->bdev,
+		fr.io_reg.sector = 0,
+		fr.io_reg.count = 0,
+		fr.ic = ic;
+		init_completion(&fr.comp);
+		r = dm_io(&fr.io_req, 1, &fr.io_reg, NULL);
+		BUG_ON(r);
+	}
 	r = dm_bufio_write_dirty_buffers(ic->bufio);
 	if (unlikely(r))
 		dm_integrity_io_error(ic, "writing tags", r);
+	if (flush_data)
+		wait_for_completion(&fr.comp);
 }
 static void sleep_on_endio_wait(struct dm_integrity_c *ic)
 	if (unlikely(dio->op == REQ_OP_DISCARD) && likely(ic->mode != 'D')) {
 		integrity_metadata(&dio->work);
-		dm_integrity_flush_buffers(ic);
+		dm_integrity_flush_buffers(ic, false);
 		dio->in_flight = (atomic_t)ATOMIC_INIT(1);
 		dio->completion = NULL;
 	flushes = bio_list_get(&ic->flush_bio_list);
 	if (unlikely(ic->mode != 'J')) {
 		spin_unlock_irq(&ic->endio_wait.lock);
-		dm_integrity_flush_buffers(ic);
+		dm_integrity_flush_buffers(ic, true);
 		goto release_flush_bios;
 	}
 	complete_journal_op(&comp);
 	wait_for_completion_io(&comp.comp);
-	dm_integrity_flush_buffers(ic);
+	dm_integrity_flush_buffers(ic, true);
 }
 static void integrity_writer(struct work_struct *w)
 {
 	int r;
-	dm_integrity_flush_buffers(ic);
+	dm_integrity_flush_buffers(ic, false);
 	if (dm_integrity_failed(ic))
 		return;
 	unsigned long limit;
 	struct bio *bio;
-	dm_integrity_flush_buffers(ic);
+	dm_integrity_flush_buffers(ic, false);
 	range.logical_sector = 0;
 	range.n_sectors = ic->provided_data_sectors;
 	add_new_range_and_wait(ic, &range);
 	spin_unlock_irq(&ic->endio_wait.lock);
-	dm_integrity_flush_buffers(ic);
+	dm_integrity_flush_buffers(ic, true);
-	if (ic->meta_dev)
-		blkdev_issue_flush(ic->dev->bdev, GFP_NOIO);
 	limit = ic->provided_data_sectors;
 	if (ic->sb->flags & cpu_to_le32(SB_FLAG_RECALCULATING)) {
 		if (ic->meta_dev)
 			queue_work(ic->writer_wq, &ic->writer_work);
 		drain_workqueue(ic->writer_wq);
-		dm_integrity_flush_buffers(ic);
+		dm_integrity_flush_buffers(ic, true);
 	}
 	if (ic->mode == 'B') {
-		dm_integrity_flush_buffers(ic);
+		dm_integrity_flush_buffers(ic, true);
 #if 1
 		/* set to 0 to test bitmap replay code */
 		init_journal(ic, 0, ic->journal_sections, 0);
 	unsigned extra_args;
 	struct dm_arg_set as;
 	static const struct dm_arg _args[] = {
-		{0, 9, "Invalid number of feature args"},
+		{0, 15, "Invalid number of feature args"},
 	};
 	unsigned journal_sectors, interleave_sectors, buffer_sectors, journal_watermark, sync_msec;
 	bool should_write_sb;

drivers/md/dm-raid.c+3−3

@@ -3729,10 +3729,10 @@ static void raid_io_hints(struct dm_target ti, struct queue_limits limits) · 3728 unmodified lines
3729	blk_limits_io_opt(limits, chunk_size_bytes * mddev_data_stripes(rs));	3729	blk_limits_io_opt(limits, chunk_size_bytes * mddev_data_stripes(rs));
3730		3730
3731	/*	3731	/*
3732	* RAID1 and RAID10 personalities require bio splitting,	3732	* RAID0 and RAID10 personalities require bio splitting,
3733	* RAID0/4/5/6 don't and process large discard bios properly.	3733	* RAID1/4/5/6 don't and process large discard bios properly.
3734	*/	3734	*/
3735	if (rs_is_raid1(rs) \|\| rs_is_raid10(rs)) {	3735	if (rs_is_raid0(rs) \|\| rs_is_raid10(rs)) {
3736	limits->discard_granularity = chunk_size_bytes;	3736	limits->discard_granularity = chunk_size_bytes;
3737	limits->max_discard_sectors = rs->md.chunk_sectors;	3737	limits->max_discard_sectors = rs->md.chunk_sectors;
3738	}	3738	}

drivers/md/dm-snap.c+24−0

 	 * for them to be committed.
 	 */
 	struct bio_list bios_queued_during_merge;
+	/*
+	 * Flush data after merge.
+	 */
+	struct bio flush_bio;
 };
 /*
 static void error_bios(struct bio *bio);
+static int flush_data(struct dm_snapshot *s)
+{
+	struct bio *flush_bio = &s->flush_bio;
+	bio_reset(flush_bio);
+	bio_set_dev(flush_bio, s->origin->bdev);
+	flush_bio->bi_opf = REQ_OP_WRITE | REQ_PREFLUSH;
+	return submit_bio_wait(flush_bio);
+}
 static void merge_callback(int read_err, unsigned long write_err, void *context)
 {
 	struct dm_snapshot *s = context;
 		goto shut;
 	}
+	if (flush_data(s) < 0) {
+		DMERR("Flush after merge failed: shutting down merge");
+		goto shut;
+	}
 	if (s->store->type->commit_merge(s->store,
 					 s->num_merging_chunks) < 0) {
 		DMERR("Write error in exception store: shutting down merge");
 	s->first_merging_chunk = 0;
 	s->num_merging_chunks = 0;
 	bio_list_init(&s->bios_queued_during_merge);
+	bio_init(&s->flush_bio, NULL, 0);
 	/* Allocate hash table for COW data */
 	if (init_hash_tables(s)) {
 	dm_exception_store_destroy(s->store);
+	bio_uninit(&s->flush_bio);
 	dm_put_device(ti, s->cow);
 	dm_put_device(ti, s->origin);

drivers/md/dm.c+1−1

@@ -562,7 +562,7 @@ static int dm_blk_ioctl(struct block_device *bdev, fmode_t mode, · 561 unmodified lines
562	* subset of the parent bdev; require extra privileges.	562	* subset of the parent bdev; require extra privileges.
563	*/	563	*/
564	if (!capable(CAP_SYS_RAWIO)) {	564	if (!capable(CAP_SYS_RAWIO)) {
565	DMWARN_LIMIT(	565	DMDEBUG_LIMIT(
566	"%s: sending ioctl %x to DM device without required privilege.",	566	"%s: sending ioctl %x to DM device without required privilege.",
567	current->comm, cmd);	567	current->comm, cmd);
568	r = -ENOIOCTLCMD;	568	r = -ENOIOCTLCMD;

drivers/misc/habanalabs/common/command_submission.c+58−19

 	cntr = &hdev->aggregated_cs_counters;
 	cs = kzalloc(sizeof(*cs), GFP_ATOMIC);
-	if (!cs)
+	if (!cs) {
+		atomic64_inc(&ctx->cs_counters.out_of_mem_drop_cnt);
+		atomic64_inc(&cntr->out_of_mem_drop_cnt);
 		return -ENOMEM;
+	}
 	cs->ctx = ctx;
 	cs->submitted = false;
 	cs_cmpl = kmalloc(sizeof(*cs_cmpl), GFP_ATOMIC);
 	if (!cs_cmpl) {
+		atomic64_inc(&ctx->cs_counters.out_of_mem_drop_cnt);
+		atomic64_inc(&cntr->out_of_mem_drop_cnt);
 		rc = -ENOMEM;
 		goto free_cs;
 	}
 	cs->jobs_in_queue_cnt = kcalloc(hdev->asic_prop.max_queues,
 			sizeof(*cs->jobs_in_queue_cnt), GFP_ATOMIC);
 	if (!cs->jobs_in_queue_cnt) {
+		atomic64_inc(&ctx->cs_counters.out_of_mem_drop_cnt);
+		atomic64_inc(&cntr->out_of_mem_drop_cnt);
 		rc = -ENOMEM;
 		goto free_fence;
 	}
 	for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++)
 		flush_workqueue(hdev->cq_wq[i]);
-	/* Make sure we don't have leftovers in the H/W queues mirror list */
+	/* Make sure we don't have leftovers in the CS mirror list */
 	list_for_each_entry_safe(cs, tmp, &hdev->cs_mirror_list, mirror_node) {
 		cs_get(cs);
 		cs->aborted = true;
 static int hl_cs_copy_chunk_array(struct hl_device *hdev,
 					struct hl_cs_chunk **cs_chunk_array,
-					void __user *chunks, u32 num_chunks)
+					void __user *chunks, u32 num_chunks,
+					struct hl_ctx *ctx)
 {
 	u32 size_to_copy;
 	if (num_chunks > HL_MAX_JOBS_PER_CS) {
+		atomic64_inc(&ctx->cs_counters.validation_drop_cnt);
+		atomic64_inc(&hdev->aggregated_cs_counters.validation_drop_cnt);
 		dev_err(hdev->dev,
 			"Number of chunks can NOT be larger than %d\n",
 			HL_MAX_JOBS_PER_CS);
 	*cs_chunk_array = kmalloc_array(num_chunks, sizeof(**cs_chunk_array),
 					GFP_ATOMIC);
-	if (!*cs_chunk_array)
+	if (!*cs_chunk_array) {
+		atomic64_inc(&ctx->cs_counters.out_of_mem_drop_cnt);
+		atomic64_inc(&hdev->aggregated_cs_counters.out_of_mem_drop_cnt);
 		return -ENOMEM;
+	}
 	size_to_copy = num_chunks * sizeof(struct hl_cs_chunk);
 	if (copy_from_user(*cs_chunk_array, chunks, size_to_copy)) {
+		atomic64_inc(&ctx->cs_counters.validation_drop_cnt);
+		atomic64_inc(&hdev->aggregated_cs_counters.validation_drop_cnt);
 		dev_err(hdev->dev, "Failed to copy cs chunk array from user\n");
 		kfree(*cs_chunk_array);
 		return -EFAULT;
 	struct hl_device *hdev = hpriv->hdev;
 	struct hl_cs_chunk *cs_chunk_array;
 	struct hl_cs_counters_atomic *cntr;
+	struct hl_ctx *ctx = hpriv->ctx;
 	struct hl_cs_job *job;
 	struct hl_cs *cs;
 	struct hl_cb *cb;
 	cntr = &hdev->aggregated_cs_counters;
 	*cs_seq = ULLONG_MAX;
-	rc = hl_cs_copy_chunk_array(hdev, &cs_chunk_array, chunks, num_chunks);
+	rc = hl_cs_copy_chunk_array(hdev, &cs_chunk_array, chunks, num_chunks,
+			hpriv->ctx);
 	if (rc)
 		goto out;
 		rc = validate_queue_index(hdev, chunk, &queue_type,
 						&is_kernel_allocated_cb);
 		if (rc) {
-			atomic64_inc(&hpriv->ctx->cs_counters.parsing_drop_cnt);
+			atomic64_inc(&ctx->cs_counters.validation_drop_cnt);
-			atomic64_inc(&cntr->parsing_drop_cnt);
+			atomic64_inc(&cntr->validation_drop_cnt);
 			goto free_cs_object;
 		}
 			cb = get_cb_from_cs_chunk(hdev, &hpriv->cb_mgr, chunk);
 			if (!cb) {
 				atomic64_inc(
-				&hpriv->ctx->cs_counters.parsing_drop_cnt);
+					&ctx->cs_counters.validation_drop_cnt);
-				atomic64_inc(&cntr->parsing_drop_cnt);
+				atomic64_inc(&cntr->validation_drop_cnt);
 				rc = -EINVAL;
 				goto free_cs_object;
 			}
 		job = hl_cs_allocate_job(hdev, queue_type,
 						is_kernel_allocated_cb);
 		if (!job) {
-			atomic64_inc(
+			atomic64_inc(&ctx->cs_counters.out_of_mem_drop_cnt);
-			&hpriv->ctx->cs_counters.out_of_mem_drop_cnt);
 			atomic64_inc(&cntr->out_of_mem_drop_cnt);
 			dev_err(hdev->dev, "Failed to allocate a new job\n");
 			rc = -ENOMEM;
 		rc = cs_parser(hpriv, job);
 		if (rc) {
-			atomic64_inc(&hpriv->ctx->cs_counters.parsing_drop_cnt);
+			atomic64_inc(&ctx->cs_counters.parsing_drop_cnt);
 			atomic64_inc(&cntr->parsing_drop_cnt);
 			dev_err(hdev->dev,
 				"Failed to parse JOB %d.%llu.%d, err %d, rejecting the CS\n",
 	}
 	if (int_queues_only) {
-		atomic64_inc(&hpriv->ctx->cs_counters.parsing_drop_cnt);
+		atomic64_inc(&ctx->cs_counters.validation_drop_cnt);
-		atomic64_inc(&cntr->parsing_drop_cnt);
+		atomic64_inc(&cntr->validation_drop_cnt);
 		dev_err(hdev->dev,
 			"Reject CS %d.%llu because only internal queues jobs are present\n",
 			cs->ctx->asid, cs->sequence);
 }
 static int cs_ioctl_extract_signal_seq(struct hl_device *hdev,
-		struct hl_cs_chunk *chunk, u64 *signal_seq)
+		struct hl_cs_chunk *chunk, u64 *signal_seq, struct hl_ctx *ctx)
 {
 	u64 *signal_seq_arr = NULL;
 	u32 size_to_copy, signal_seq_arr_len;
 	/* currently only one signal seq is supported */
 	if (signal_seq_arr_len != 1) {
+		atomic64_inc(&ctx->cs_counters.validation_drop_cnt);
+		atomic64_inc(&hdev->aggregated_cs_counters.validation_drop_cnt);
 		dev_err(hdev->dev,
 			"Wait for signal CS supports only one signal CS seq\n");
 		return -EINVAL;
 	signal_seq_arr = kmalloc_array(signal_seq_arr_len,
 					sizeof(*signal_seq_arr),
 					GFP_ATOMIC);
-	if (!signal_seq_arr)
+	if (!signal_seq_arr) {
+		atomic64_inc(&ctx->cs_counters.out_of_mem_drop_cnt);
+		atomic64_inc(&hdev->aggregated_cs_counters.out_of_mem_drop_cnt);
 		return -ENOMEM;
+	}
 	size_to_copy = chunk->num_signal_seq_arr * sizeof(*signal_seq_arr);
 	if (copy_from_user(signal_seq_arr,
 				u64_to_user_ptr(chunk->signal_seq_arr),
 				size_to_copy)) {
+		atomic64_inc(&ctx->cs_counters.validation_drop_cnt);
+		atomic64_inc(&hdev->aggregated_cs_counters.validation_drop_cnt);
 		dev_err(hdev->dev,
 			"Failed to copy signal seq array from user\n");
 		rc = -EFAULT;
 	struct hl_device *hdev = hpriv->hdev;
 	struct hl_cs_compl *sig_waitcs_cmpl;
 	u32 q_idx, collective_engine_id = 0;
+	struct hl_cs_counters_atomic *cntr;
 	struct hl_fence *sig_fence = NULL;
 	struct hl_ctx *ctx = hpriv->ctx;
 	enum hl_queue_type q_type;
 	u64 signal_seq;
 	int rc;
+	cntr = &hdev->aggregated_cs_counters;
 	*cs_seq = ULLONG_MAX;
-	rc = hl_cs_copy_chunk_array(hdev, &cs_chunk_array, chunks, num_chunks);
+	rc = hl_cs_copy_chunk_array(hdev, &cs_chunk_array, chunks, num_chunks,
+			ctx);
 	if (rc)
 		goto out;
 	chunk = &cs_chunk_array[0];
 	if (chunk->queue_index >= hdev->asic_prop.max_queues) {
+		atomic64_inc(&ctx->cs_counters.validation_drop_cnt);
+		atomic64_inc(&cntr->validation_drop_cnt);
 		dev_err(hdev->dev, "Queue index %d is invalid\n",
 			chunk->queue_index);
 		rc = -EINVAL;
 	q_type = hw_queue_prop->type;
 	if (!hw_queue_prop->supports_sync_stream) {
+		atomic64_inc(&ctx->cs_counters.validation_drop_cnt);
+		atomic64_inc(&cntr->validation_drop_cnt);
 		dev_err(hdev->dev,
 			"Queue index %d does not support sync stream operations\n",
 			q_idx);
 	if (cs_type == CS_TYPE_COLLECTIVE_WAIT) {
 		if (!(hw_queue_prop->collective_mode == HL_COLLECTIVE_MASTER)) {
+			atomic64_inc(&ctx->cs_counters.validation_drop_cnt);
+			atomic64_inc(&cntr->validation_drop_cnt);
 			dev_err(hdev->dev,
 				"Queue index %d is invalid\n", q_idx);
 			rc = -EINVAL;
 	}
 	if (cs_type == CS_TYPE_WAIT || cs_type == CS_TYPE_COLLECTIVE_WAIT) {
-		rc = cs_ioctl_extract_signal_seq(hdev, chunk, &signal_seq);
+		rc = cs_ioctl_extract_signal_seq(hdev, chunk, &signal_seq, ctx);
 		if (rc)
 			goto free_cs_chunk_array;
 		sig_fence = hl_ctx_get_fence(ctx, signal_seq);
 		if (IS_ERR(sig_fence)) {
+			atomic64_inc(&ctx->cs_counters.validation_drop_cnt);
+			atomic64_inc(&cntr->validation_drop_cnt);
 			dev_err(hdev->dev,
 				"Failed to get signal CS with seq 0x%llx\n",
 				signal_seq);
 			container_of(sig_fence, struct hl_cs_compl, base_fence);
 		if (sig_waitcs_cmpl->type != CS_TYPE_SIGNAL) {
+			atomic64_inc(&ctx->cs_counters.validation_drop_cnt);
+			atomic64_inc(&cntr->validation_drop_cnt);
 			dev_err(hdev->dev,
 				"CS seq 0x%llx is not of a signal CS\n",
 				signal_seq);
 	else if (cs_type == CS_TYPE_COLLECTIVE_WAIT)
 		rc = hdev->asic_funcs->collective_wait_create_jobs(hdev, ctx,
 				cs, q_idx, collective_engine_id);
-	else
+	else {
+		atomic64_inc(&ctx->cs_counters.validation_drop_cnt);
+		atomic64_inc(&cntr->validation_drop_cnt);
 		rc = -EINVAL;
+	}
 	if (rc)
 		goto free_cs_object;

drivers/misc/habanalabs/common/device.c+5−3

 {
 	enum hl_device_status status;
-	if (hdev->disabled)
+	if (atomic_read(&hdev->in_reset))
-		status = HL_DEVICE_STATUS_MALFUNCTION;
-	else if (atomic_read(&hdev->in_reset))
 		status = HL_DEVICE_STATUS_IN_RESET;
 	else if (hdev->needs_reset)
 		status = HL_DEVICE_STATUS_NEEDS_RESET;
+	else if (hdev->disabled)
+		status = HL_DEVICE_STATUS_MALFUNCTION;
 	else
 		status = HL_DEVICE_STATUS_OPERATIONAL;
 						GFP_KERNEL);
 		if (!hdev->kernel_ctx) {
 			rc = -ENOMEM;
+			hl_mmu_fini(hdev);
 			goto out_err;
 		}
 				"failed to init kernel ctx in hard reset\n");
 			kfree(hdev->kernel_ctx);
 			hdev->kernel_ctx = NULL;
+			hl_mmu_fini(hdev);
 			goto out_err;
 		}
 	}

drivers/misc/habanalabs/common/firmware_if.c+44−16

@@ -627,25 +627,38 @@ int hl_fw_read_preboot_status(struct hl_device *hdev, u32 cpu_boot_status_reg, · 626 unmodified lines
627	security_status = RREG32(cpu_security_boot_status_reg);	627	security_status = RREG32(cpu_security_boot_status_reg);
628		628
629	/* We read security status multiple times during boot:	629	/* We read security status multiple times during boot:
630	* 1. preboot - we check if fw security feature is supported	630	* 1. preboot - a. Check whether the security status bits are valid
631	* 2. boot cpu - we get boot cpu security status	631	* b. Check whether fw security is enabled
632	* 3. FW application - we get FW application security status	632	* c. Check whether hard reset is done by preboot
		633	* 2. boot cpu - a. Fetch boot cpu security status
		634	* b. Check whether hard reset is done by boot cpu
		635	* 3. FW application - a. Fetch fw application security status
		636	* b. Check whether hard reset is done by fw app
633	*	637	*
634	* Preboot:	638	* Preboot:
635	* Check security status bit (CPU_BOOT_DEV_STS0_ENABLED), if it is set	639	* Check security status bit (CPU_BOOT_DEV_STS0_ENABLED), if it is set
636	* check security enabled bit (CPU_BOOT_DEV_STS0_SECURITY_EN)	640	* check security enabled bit (CPU_BOOT_DEV_STS0_SECURITY_EN)
637	*/	641	*/
638	if (security_status & CPU_BOOT_DEV_STS0_ENABLED) {	642	if (security_status & CPU_BOOT_DEV_STS0_ENABLED) {
639	hdev->asic_prop.fw_security_status_valid = 1;	643	prop->fw_security_status_valid = 1;
640	prop->fw_security_disabled =	644
641	!(security_status & CPU_BOOT_DEV_STS0_SECURITY_EN);	645	if (security_status & CPU_BOOT_DEV_STS0_SECURITY_EN)
		646	prop->fw_security_disabled = false;
		647	else
		648	prop->fw_security_disabled = true;
		649
		650	if (security_status & CPU_BOOT_DEV_STS0_FW_HARD_RST_EN)
		651	prop->hard_reset_done_by_fw = true;
642	} else {	652	} else {
643	hdev->asic_prop.fw_security_status_valid = 0;	653	prop->fw_security_status_valid = 0;
644	prop->fw_security_disabled = true;	654	prop->fw_security_disabled = true;
645	}	655	}
646		656
		657	dev_dbg(hdev->dev, "Firmware preboot hard-reset is %s\n",
		658	prop->hard_reset_done_by_fw ? "enabled" : "disabled");
		659
647	dev_info(hdev->dev, "firmware-level security is %s\n",	660	dev_info(hdev->dev, "firmware-level security is %s\n",
648	prop->fw_security_disabled ? "disabled" : "enabled");	661	prop->fw_security_disabled ? "disabled" : "enabled");
649		662
650	return 0;	663	return 0;
651	}	664	}
@@ -655,6 +668,7 @@ int hl_fw_init_cpu(struct hl_device *hdev, u32 cpu_boot_status_reg, · 3 unmodified lines
655	u32 cpu_security_boot_status_reg, u32 boot_err0_reg,	668	u32 cpu_security_boot_status_reg, u32 boot_err0_reg,
656	bool skip_bmc, u32 cpu_timeout, u32 boot_fit_timeout)	669	bool skip_bmc, u32 cpu_timeout, u32 boot_fit_timeout)
657	{	670	{
		671	struct asic_fixed_properties *prop = &hdev->asic_prop;
658	u32 status;	672	u32 status;
659	int rc;	673	int rc;
660		674
@@ -723,11 +737,22 @@ int hl_fw_init_cpu(struct hl_device *hdev, u32 cpu_boot_status_reg, · 62 unmodified lines
723	/* Read U-Boot version now in case we will later fail */	737	/* Read U-Boot version now in case we will later fail */
724	hdev->asic_funcs->read_device_fw_version(hdev, FW_COMP_UBOOT);	738	hdev->asic_funcs->read_device_fw_version(hdev, FW_COMP_UBOOT);
725		739
		740	/* Clear reset status since we need to read it again from boot CPU */
		741	prop->hard_reset_done_by_fw = false;
		742
726	/* Read boot_cpu security bits */	743	/* Read boot_cpu security bits */
727	if (hdev->asic_prop.fw_security_status_valid)	744	if (prop->fw_security_status_valid) {
728	hdev->asic_prop.fw_boot_cpu_security_map =	745	prop->fw_boot_cpu_security_map =
729	RREG32(cpu_security_boot_status_reg);	746	RREG32(cpu_security_boot_status_reg);
730		747
		748	if (prop->fw_boot_cpu_security_map &
		749	CPU_BOOT_DEV_STS0_FW_HARD_RST_EN)
		750	prop->hard_reset_done_by_fw = true;
		751	}
		752
		753	dev_dbg(hdev->dev, "Firmware boot CPU hard-reset is %s\n",
		754	prop->hard_reset_done_by_fw ? "enabled" : "disabled");
		755
731	if (rc) {	756	if (rc) {
732	detect_cpu_boot_status(hdev, status);	757	detect_cpu_boot_status(hdev, status);
733	rc = -EIO;	758	rc = -EIO;
@@ -796,18 +821,21 @@ int hl_fw_init_cpu(struct hl_device *hdev, u32 cpu_boot_status_reg, · 62 unmodified lines
796	goto out;	821	goto out;
797	}	822	}
798		823
		824	/* Clear reset status since we need to read again from app */
		825	prop->hard_reset_done_by_fw = false;
		826
799	/* Read FW application security bits */	827	/* Read FW application security bits */
800	if (hdev->asic_prop.fw_security_status_valid) {	828	if (prop->fw_security_status_valid) {
801	hdev->asic_prop.fw_app_security_map =	829	prop->fw_app_security_map =
802	RREG32(cpu_security_boot_status_reg);	830	RREG32(cpu_security_boot_status_reg);
803		831
804	if (hdev->asic_prop.fw_app_security_map &	832	if (prop->fw_app_security_map &
805	CPU_BOOT_DEV_STS0_FW_HARD_RST_EN)	833	CPU_BOOT_DEV_STS0_FW_HARD_RST_EN)
806	hdev->asic_prop.hard_reset_done_by_fw = true;	834	prop->hard_reset_done_by_fw = true;
807	}	835	}
808		836
809	dev_dbg(hdev->dev, "Firmware hard-reset is %s\n",	837	dev_dbg(hdev->dev, "Firmware application CPU hard-reset is %s\n",
810	hdev->asic_prop.hard_reset_done_by_fw ? "enabled" : "disabled");	838	prop->hard_reset_done_by_fw ? "enabled" : "disabled");
811		839
812	dev_info(hdev->dev, "Successfully loaded firmware to device\n");	840	dev_info(hdev->dev, "Successfully loaded firmware to device\n");
813		841

drivers/misc/habanalabs/common/habanalabs.h+3−1

 	u32 (*get_signal_cb_size)(struct hl_device *hdev);
 	u32 (*get_wait_cb_size)(struct hl_device *hdev);
 	u32 (*gen_signal_cb)(struct hl_device *hdev, void *data, u16 sob_id,
-			u32 size);
+			u32 size, bool eb);
 	u32 (*gen_wait_cb)(struct hl_device *hdev,
 			struct hl_gen_wait_properties *prop);
 	void (*reset_sob)(struct hl_device *hdev, void *data);
  * @queue_full_drop_cnt: dropped due to queue full
  * @device_in_reset_drop_cnt: dropped due to device in reset
  * @max_cs_in_flight_drop_cnt: dropped due to maximum CS in-flight
+ * @validation_drop_cnt: dropped due to error in validation
  */
 struct hl_cs_counters_atomic {
 	atomic64_t out_of_mem_drop_cnt;
 	atomic64_t queue_full_drop_cnt;
 	atomic64_t device_in_reset_drop_cnt;
 	atomic64_t max_cs_in_flight_drop_cnt;
+	atomic64_t validation_drop_cnt;
 };
 /**

drivers/misc/habanalabs/common/habanalabs_drv.c+1−0

@@ -544,6 +544,7 @@ static struct pci_driver hl_pci_driver = { · 543 unmodified lines
544	.id_table = ids,	544	.id_table = ids,
545	.probe = hl_pci_probe,	545	.probe = hl_pci_probe,
546	.remove = hl_pci_remove,	546	.remove = hl_pci_remove,
		547	.shutdown = hl_pci_remove,
547	.driver.pm = &hl_pm_ops,	548	.driver.pm = &hl_pm_ops,
548	.err_handler = &hl_pci_err_handler,	549	.err_handler = &hl_pci_err_handler,
549	};	550	};

drivers/misc/habanalabs/common/habanalabs_ioctl.c+6−1

 			atomic64_read(&cntr->device_in_reset_drop_cnt);
 	cs_counters.total_max_cs_in_flight_drop_cnt =
 			atomic64_read(&cntr->max_cs_in_flight_drop_cnt);
+	cs_counters.total_validation_drop_cnt =
+			atomic64_read(&cntr->validation_drop_cnt);
 	if (hpriv->ctx) {
 		cs_counters.ctx_out_of_mem_drop_cnt =
 		cs_counters.ctx_max_cs_in_flight_drop_cnt =
 				atomic64_read(
 			&hpriv->ctx->cs_counters.max_cs_in_flight_drop_cnt);
+		cs_counters.ctx_validation_drop_cnt =
+				atomic64_read(
+				&hpriv->ctx->cs_counters.validation_drop_cnt);
 	}
 	return copy_to_user(out, &cs_counters,
 static int pll_frequency_info(struct hl_fpriv *hpriv, struct hl_info_args *args)
 {
 	struct hl_device *hdev = hpriv->hdev;
-	struct hl_pll_frequency_info freq_info = {0};
+	struct hl_pll_frequency_info freq_info = { {0} };
 	u32 max_size = args->return_size;
 	void __user *out = (void __user *) (uintptr_t) args->return_pointer;
 	int rc;

drivers/misc/habanalabs/common/hw_queue.c+4−1

 		"generate signal CB, sob_id: %d, sob val: 0x%x, q_idx: %d\n",
 		cs_cmpl->hw_sob->sob_id, cs_cmpl->sob_val, q_idx);
+	/* we set an EB since we must make sure all oeprations are done
+	 * when sending the signal
+	 */
 	hdev->asic_funcs->gen_signal_cb(hdev, job->patched_cb,
-				cs_cmpl->hw_sob->sob_id, 0);
+				cs_cmpl->hw_sob->sob_id, 0, true);
 	kref_get(&hw_sob->kref);

drivers/misc/habanalabs/common/pci.c+17−11

 	if ((val & PCI_CONFIG_ELBI_STS_MASK) == PCI_CONFIG_ELBI_STS_DONE)
 		return 0;
-	if (val & PCI_CONFIG_ELBI_STS_ERR) {
+	if (val & PCI_CONFIG_ELBI_STS_ERR)
-		dev_err(hdev->dev, "Error writing to ELBI\n");
 		return -EIO;
-	}
 	if (!(val & PCI_CONFIG_ELBI_STS_MASK)) {
 		dev_err(hdev->dev, "ELBI write didn't finish in time\n");
 	dbi_offset = addr & 0xFFF;
-	rc = hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr, 0x00300000);
+	/* Ignore result of writing to pcie_aux_dbi_reg_addr as it could fail
-	rc |= hl_pci_elbi_write(hdev, prop->pcie_dbi_base_address + dbi_offset,
+	 * in case the firmware security is enabled
+	 */
+	hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr, 0x00300000);
+	rc = hl_pci_elbi_write(hdev, prop->pcie_dbi_base_address + dbi_offset,
 				data);
 	if (rc)
 	rc |= hl_pci_iatu_write(hdev, offset + 0x4, ctrl_reg_val);
-	/* Return the DBI window to the default location */
+	/* Return the DBI window to the default location
-	rc |= hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr, 0);
+	 * Ignore result of writing to pcie_aux_dbi_reg_addr as it could fail
-	rc |= hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr + 4, 0);
+	 * in case the firmware security is enabled
+	 */
+	hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr, 0);
 	if (rc)
 		dev_err(hdev->dev, "failed to map bar %u to 0x%08llx\n",
 	/* Enable */
 	rc |= hl_pci_iatu_write(hdev, 0x004, 0x80000000);
-	/* Return the DBI window to the default location */
+	/* Return the DBI window to the default location
-	rc |= hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr, 0);
+	 * Ignore result of writing to pcie_aux_dbi_reg_addr as it could fail
-	rc |= hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr + 4, 0);
+	 * in case the firmware security is enabled
+	 */
+	hl_pci_elbi_write(hdev, prop->pcie_aux_dbi_reg_addr, 0);
 	return rc;
 }

drivers/misc/habanalabs/gaudi/gaudi.c+83−108

@@ -151,19 +151,6 @@ static const u16 gaudi_packet_sizes[MAX_PACKET_ID] = { · 150 unmodified lines
151	[PACKET_LOAD_AND_EXE] = sizeof(struct packet_load_and_exe)	151	[PACKET_LOAD_AND_EXE] = sizeof(struct packet_load_and_exe)
152	};	152	};
153		153
154	static const u32 gaudi_pll_base_addresses[GAUDI_PLL_MAX] = {
155	[CPU_PLL] = mmPSOC_CPU_PLL_NR,
156	[PCI_PLL] = mmPSOC_PCI_PLL_NR,
157	[SRAM_PLL] = mmSRAM_W_PLL_NR,
158	[HBM_PLL] = mmPSOC_HBM_PLL_NR,
159	[NIC_PLL] = mmNIC0_PLL_NR,
160	[DMA_PLL] = mmDMA_W_PLL_NR,
161	[MESH_PLL] = mmMESH_W_PLL_NR,
162	[MME_PLL] = mmPSOC_MME_PLL_NR,
163	[TPC_PLL] = mmPSOC_TPC_PLL_NR,
164	[IF_PLL] = mmIF_W_PLL_NR
165	};
166
167	static inline bool validate_packet_id(enum packet_id id)	154	static inline bool validate_packet_id(enum packet_id id)
168	{	155	{
169	switch (id) {	156	switch (id) {
@@ -374,7 +361,7 @@ static int gaudi_cpucp_info_get(struct hl_device *hdev); · 204 unmodified lines
374	static void gaudi_disable_clock_gating(struct hl_device *hdev);	361	static void gaudi_disable_clock_gating(struct hl_device *hdev);
375	static void gaudi_mmu_prepare(struct hl_device *hdev, u32 asid);	362	static void gaudi_mmu_prepare(struct hl_device *hdev, u32 asid);
376	static u32 gaudi_gen_signal_cb(struct hl_device hdev, void data, u16 sob_id,	363	static u32 gaudi_gen_signal_cb(struct hl_device hdev, void data, u16 sob_id,
377	u32 size);	364	u32 size, bool eb);
378	static u32 gaudi_gen_wait_cb(struct hl_device *hdev,	365	static u32 gaudi_gen_wait_cb(struct hl_device *hdev,
379	struct hl_gen_wait_properties *prop);	366	struct hl_gen_wait_properties *prop);
380		367
@@ -667,12 +654,6 @@ static int gaudi_early_init(struct hl_device *hdev) · 286 unmodified lines
667	if (rc)	654	if (rc)
668	goto free_queue_props;	655	goto free_queue_props;
669		656
670	if (gaudi_get_hw_state(hdev) == HL_DEVICE_HW_STATE_DIRTY) {
671	dev_info(hdev->dev,
672	"H/W state is dirty, must reset before initializing\n");
673	hdev->asic_funcs->hw_fini(hdev, true);
674	}
675
676	/* Before continuing in the initialization, we need to read the preboot	657	/* Before continuing in the initialization, we need to read the preboot
677	* version to determine whether we run with a security-enabled firmware	658	* version to determine whether we run with a security-enabled firmware
678	*/	659	*/
@@ -685,6 +666,12 @@ static int gaudi_early_init(struct hl_device *hdev) · 6 unmodified lines
685	goto pci_fini;	666	goto pci_fini;
686	}	667	}
687		668
		669	if (gaudi_get_hw_state(hdev) == HL_DEVICE_HW_STATE_DIRTY) {
		670	dev_info(hdev->dev,
		671	"H/W state is dirty, must reset before initializing\n");
		672	hdev->asic_funcs->hw_fini(hdev, true);
		673	}
		674
688	return 0;	675	return 0;
689		676
690	pci_fini:	677	pci_fini:
@@ -703,93 +690,60 @@ static int gaudi_early_fini(struct hl_device *hdev) · 12 unmodified lines
703	}	690	}
704		691
705	/**	692	/**
706	* gaudi_fetch_pll_frequency - Fetch PLL frequency values	693	* gaudi_fetch_psoc_frequency - Fetch PSOC frequency values
707	*	694	*
708	* @hdev: pointer to hl_device structure	695	* @hdev: pointer to hl_device structure
709	* @pll_index: index of the pll to fetch frequency from
710	* @pll_freq: pointer to store the pll frequency in MHz in each of the available
711	* outputs. if a certain output is not available a 0 will be set
712	*	696	*
713	*/	697	*/
714	static int gaudi_fetch_pll_frequency(struct hl_device *hdev,	698	static int gaudi_fetch_psoc_frequency(struct hl_device *hdev)
715	enum gaudi_pll_index pll_index,
716	u16 *pll_freq_arr)
717	{	699	{
718	u32 nr = 0, nf = 0, od = 0, pll_clk = 0, div_fctr, div_sel,	700	struct asic_fixed_properties *prop = &hdev->asic_prop;
719	pll_base_addr = gaudi_pll_base_addresses[pll_index];	701	u32 nr = 0, nf = 0, od = 0, div_fctr = 0, pll_clk, div_sel;
720	u16 freq = 0;	702	u16 pll_freq_arr[HL_PLL_NUM_OUTPUTS], freq;
721	int i, rc;	703	int rc;
722
723	if (hdev->asic_prop.fw_security_status_valid &&
724	(hdev->asic_prop.fw_app_security_map &
725	CPU_BOOT_DEV_STS0_PLL_INFO_EN)) {
726	rc = hl_fw_cpucp_pll_info_get(hdev, pll_index, pll_freq_arr);
727		704
728	if (rc)	705	if (hdev->asic_prop.fw_security_disabled) {
729	return rc;
730	} else if (hdev->asic_prop.fw_security_disabled) {
731	/* Backward compatibility */	706	/* Backward compatibility */
732	nr = RREG32(pll_base_addr + PLL_NR_OFFSET);	707	div_fctr = RREG32(mmPSOC_CPU_PLL_DIV_FACTOR_2);
733	nf = RREG32(pll_base_addr + PLL_NF_OFFSET);	708	div_sel = RREG32(mmPSOC_CPU_PLL_DIV_SEL_2);
734	od = RREG32(pll_base_addr + PLL_OD_OFFSET);	709	nr = RREG32(mmPSOC_CPU_PLL_NR);
735		710	nf = RREG32(mmPSOC_CPU_PLL_NF);
736	for (i = 0; i < HL_PLL_NUM_OUTPUTS; i++) {	711	od = RREG32(mmPSOC_CPU_PLL_OD);
737	div_fctr = RREG32(pll_base_addr +
738	PLL_DIV_FACTOR_0_OFFSET + i * 4);
739	div_sel = RREG32(pll_base_addr +
740	PLL_DIV_SEL_0_OFFSET + i * 4);
741		712
742	if (div_sel == DIV_SEL_REF_CLK \|\|	713	if (div_sel == DIV_SEL_REF_CLK \|\|
743	div_sel == DIV_SEL_DIVIDED_REF) {	714	div_sel == DIV_SEL_DIVIDED_REF) {
744	if (div_sel == DIV_SEL_REF_CLK)	715	if (div_sel == DIV_SEL_REF_CLK)
745	freq = PLL_REF_CLK;	716	freq = PLL_REF_CLK;
746	else	717	else
747	freq = PLL_REF_CLK / (div_fctr + 1);	718	freq = PLL_REF_CLK / (div_fctr + 1);
748	} else if (div_sel == DIV_SEL_PLL_CLK \|\|	719	} else if (div_sel == DIV_SEL_PLL_CLK \|\|
749	div_sel == DIV_SEL_DIVIDED_PLL) {	720	div_sel == DIV_SEL_DIVIDED_PLL) {
750	pll_clk = PLL_REF_CLK * (nf + 1) /	721	pll_clk = PLL_REF_CLK * (nf + 1) /
751	((nr + 1) * (od + 1));	722	((nr + 1) * (od + 1));
752	if (div_sel == DIV_SEL_PLL_CLK)	723	if (div_sel == DIV_SEL_PLL_CLK)
753	freq = pll_clk;	724	freq = pll_clk;
754	else	725	else
755	freq = pll_clk / (div_fctr + 1);	726	freq = pll_clk / (div_fctr + 1);
756	} else {	727	} else {
757	dev_warn(hdev->dev,	728	dev_warn(hdev->dev,
758	"Received invalid div select value: %d",	729	"Received invalid div select value: %d",
759	div_sel);	730	div_sel);
760	}	731	freq = 0;
761
762	pll_freq_arr[i] = freq;
763	}	732	}
764	} else {	733	} else {
765	dev_err(hdev->dev, "Failed to fetch PLL frequency values\n");	734	rc = hl_fw_cpucp_pll_info_get(hdev, CPU_PLL, pll_freq_arr);
766	return -EIO;
767	}
768		735
769	return 0;	736	if (rc)
770	}	737	return rc;
771
772	/**
773	* gaudi_fetch_psoc_frequency - Fetch PSOC frequency values
774	*
775	* @hdev: pointer to hl_device structure
776	*
777	*/
778	static int gaudi_fetch_psoc_frequency(struct hl_device *hdev)
779	{
780	struct asic_fixed_properties *prop = &hdev->asic_prop;
781	u16 pll_freq[HL_PLL_NUM_OUTPUTS];
782	int rc;
783		738
784	rc = gaudi_fetch_pll_frequency(hdev, CPU_PLL, pll_freq);	739	freq = pll_freq_arr[2];
785	if (rc)	740	}
786	return rc;
787		741
788	prop->psoc_timestamp_frequency = pll_freq[2];	742	prop->psoc_timestamp_frequency = freq;
789	prop->psoc_pci_pll_nr = 0;	743	prop->psoc_pci_pll_nr = nr;
790	prop->psoc_pci_pll_nf = 0;	744	prop->psoc_pci_pll_nf = nf;
791	prop->psoc_pci_pll_od = 0;	745	prop->psoc_pci_pll_od = od;
792	prop->psoc_pci_pll_div_factor = 0;	746	prop->psoc_pci_pll_div_factor = div_fctr;
793		747
794	return 0;	748	return 0;
795	}	749	}
@@ -884,11 +838,17 @@ static int gaudi_init_tpc_mem(struct hl_device *hdev) · 88 unmodified lines
884	size_t fw_size;	838	size_t fw_size;
885	void *cpu_addr;	839	void *cpu_addr;
886	dma_addr_t dma_handle;	840	dma_addr_t dma_handle;
887	int rc;	841	int rc, count = 5;
888		842
		843	again:
889	rc = request_firmware(&fw, GAUDI_TPC_FW_FILE, hdev->dev);	844	rc = request_firmware(&fw, GAUDI_TPC_FW_FILE, hdev->dev);
		845	if (rc == -EINTR && count-- > 0) {
		846	msleep(50);
		847	goto again;
		848	}
		849
890	if (rc) {	850	if (rc) {
891	dev_err(hdev->dev, "Firmware file %s is not found!\n",	851	dev_err(hdev->dev, "Failed to load firmware file %s\n",
892	GAUDI_TPC_FW_FILE);	852	GAUDI_TPC_FW_FILE);
893	goto out;	853	goto out;
894	}	854	}
@@ -1110,7 +1070,7 @@ static void gaudi_collective_slave_init_job(struct hl_device *hdev, · 215 unmodified lines
1110	prop->collective_sob_id, queue_id);	1070	prop->collective_sob_id, queue_id);
1111		1071
1112	cb_size += gaudi_gen_signal_cb(hdev, job->user_cb,	1072	cb_size += gaudi_gen_signal_cb(hdev, job->user_cb,
1113	prop->collective_sob_id, cb_size);	1073	prop->collective_sob_id, cb_size, false);
1114	}	1074	}
1115		1075
1116	static void gaudi_collective_wait_init_cs(struct hl_cs *cs)	1076	static void gaudi_collective_wait_init_cs(struct hl_cs *cs)
@@ -2449,8 +2409,6 @@ static void gaudi_init_golden_registers(struct hl_device *hdev) · 1332 unmodified lines
2449	gaudi_init_e2e(hdev);	2409	gaudi_init_e2e(hdev);
2450	gaudi_init_hbm_cred(hdev);	2410	gaudi_init_hbm_cred(hdev);
2451		2411
2452	hdev->asic_funcs->disable_clock_gating(hdev);
2453
2454	for (tpc_id = 0, tpc_offset = 0;	2412	for (tpc_id = 0, tpc_offset = 0;
2455	tpc_id < TPC_NUMBER_OF_ENGINES;	2413	tpc_id < TPC_NUMBER_OF_ENGINES;
2456	tpc_id++, tpc_offset += TPC_CFG_OFFSET) {	2414	tpc_id++, tpc_offset += TPC_CFG_OFFSET) {
@@ -3462,6 +3420,9 @@ static void gaudi_set_clock_gating(struct hl_device *hdev) · 1005 unmodified lines
3462	if (hdev->in_debug)	3420	if (hdev->in_debug)
3463	return;	3421	return;
3464		3422
		3423	if (!hdev->asic_prop.fw_security_disabled)
		3424	return;
		3425
3465	for (i = GAUDI_PCI_DMA_1, qman_offset = 0 ; i < GAUDI_HBM_DMA_1 ; i++) {	3426	for (i = GAUDI_PCI_DMA_1, qman_offset = 0 ; i < GAUDI_HBM_DMA_1 ; i++) {
3466	enable = !!(hdev->clock_gating_mask &	3427	enable = !!(hdev->clock_gating_mask &
3467	(BIT_ULL(gaudi_dma_assignment[i])));	3428	(BIT_ULL(gaudi_dma_assignment[i])));
@@ -3513,7 +3474,7 @@ static void gaudi_disable_clock_gating(struct hl_device *hdev) · 45 unmodified lines
3513	u32 qman_offset;	3474	u32 qman_offset;
3514	int i;	3475	int i;
3515		3476
3516	if (!(gaudi->hw_cap_initialized & HW_CAP_CLK_GATE))	3477	if (!hdev->asic_prop.fw_security_disabled)
3517	return;	3478	return;
3518		3479
3519	for (i = 0, qman_offset = 0 ; i < DMA_NUMBER_OF_CHANNELS ; i++) {	3480	for (i = 0, qman_offset = 0 ; i < DMA_NUMBER_OF_CHANNELS ; i++) {
@@ -3806,7 +3767,7 @@ static int gaudi_init_cpu_queues(struct hl_device *hdev, u32 cpu_timeout) · 286 unmodified lines
3806	static void gaudi_pre_hw_init(struct hl_device *hdev)	3767	static void gaudi_pre_hw_init(struct hl_device *hdev)
3807	{	3768	{
3808	/* Perform read from the device to make sure device is up */	3769	/* Perform read from the device to make sure device is up */
3809	RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG);	3770	RREG32(mmHW_STATE);
3810		3771
3811	if (hdev->asic_prop.fw_security_disabled) {	3772	if (hdev->asic_prop.fw_security_disabled) {
3812	/* Set the access through PCI bars (Linux driver only) as	3773	/* Set the access through PCI bars (Linux driver only) as
@@ -3847,6 +3808,13 @@ static int gaudi_hw_init(struct hl_device *hdev) · 34 unmodified lines
3847	return rc;	3808	return rc;
3848	}	3809	}
3849		3810
		3811	/* In case the clock gating was enabled in preboot we need to disable
		3812	* it here before touching the MME/TPC registers.
		3813	* There is no need to take clk gating mutex because when this function
		3814	* runs, no other relevant code can run
		3815	*/
		3816	hdev->asic_funcs->disable_clock_gating(hdev);
		3817
3850	/* SRAM scrambler must be initialized after CPU is running from HBM */	3818	/* SRAM scrambler must be initialized after CPU is running from HBM */
3851	gaudi_init_scrambler_sram(hdev);	3819	gaudi_init_scrambler_sram(hdev);
3852		3820
@@ -3885,7 +3853,7 @@ static int gaudi_hw_init(struct hl_device *hdev) · 32 unmodified lines
3885	}	3853	}
3886		3854
3887	/* Perform read from the device to flush all configuration */	3855	/* Perform read from the device to flush all configuration */
3888	RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG);	3856	RREG32(mmHW_STATE);
3889		3857
3890	return 0;	3858	return 0;
3891		3859
@@ -3927,7 +3895,10 @@ static void gaudi_hw_fini(struct hl_device *hdev, bool hard_reset) · 35 unmodified lines
3927	/* I don't know what is the state of the CPU so make sure it is	3895	/* I don't know what is the state of the CPU so make sure it is
3928	* stopped in any means necessary	3896	* stopped in any means necessary
3929	*/	3897	*/
3930	WREG32(mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU, KMD_MSG_GOTO_WFE);	3898	if (hdev->asic_prop.hard_reset_done_by_fw)
		3899	WREG32(mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU, KMD_MSG_RST_DEV);
		3900	else
		3901	WREG32(mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU, KMD_MSG_GOTO_WFE);
3931		3902
3932	WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR, GAUDI_EVENT_HALT_MACHINE);	3903	WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR, GAUDI_EVENT_HALT_MACHINE);
3933		3904
@@ -3971,11 +3942,15 @@ static void gaudi_hw_fini(struct hl_device *hdev, bool hard_reset) · 37 unmodified lines
3971		3942
3972	WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST,	3943	WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST,
3973	1 << PSOC_GLOBAL_CONF_SW_ALL_RST_IND_SHIFT);	3944	1 << PSOC_GLOBAL_CONF_SW_ALL_RST_IND_SHIFT);
3974	}
3975		3945
3976	dev_info(hdev->dev,	3946	dev_info(hdev->dev,
3977	"Issued HARD reset command, going to wait %dms\n",	3947	"Issued HARD reset command, going to wait %dms\n",
3978	reset_timeout_ms);	3948	reset_timeout_ms);
		3949	} else {
		3950	dev_info(hdev->dev,
		3951	"Firmware performs HARD reset, going to wait %dms\n",
		3952	reset_timeout_ms);
		3953	}
3979		3954
3980	/*	3955	/*
3981	* After hard reset, we can't poll the BTM_FSM register because the PSOC	3956	* After hard reset, we can't poll the BTM_FSM register because the PSOC
@@ -7936,7 +7911,7 @@ static u32 gaudi_get_wait_cb_size(struct hl_device *hdev) · 3954 unmodified lines
7936	}	7911	}
7937		7912
7938	static u32 gaudi_gen_signal_cb(struct hl_device hdev, void data, u16 sob_id,	7913	static u32 gaudi_gen_signal_cb(struct hl_device hdev, void data, u16 sob_id,
7939	u32 size)	7914	u32 size, bool eb)
7940	{	7915	{
7941	struct hl_cb cb = (struct hl_cb ) data;	7916	struct hl_cb cb = (struct hl_cb ) data;
7942	struct packet_msg_short *pkt;	7917	struct packet_msg_short *pkt;
@@ -7953,7 +7928,7 @@ static u32 gaudi_gen_signal_cb(struct hl_device hdev, void data, u16 sob_id, · 10 unmodified lines
7953	ctl \|= FIELD_PREP(GAUDI_PKT_SHORT_CTL_OP_MASK, 0); /* write the value */	7928	ctl \|= FIELD_PREP(GAUDI_PKT_SHORT_CTL_OP_MASK, 0); /* write the value */
7954	ctl \|= FIELD_PREP(GAUDI_PKT_SHORT_CTL_BASE_MASK, 3); /* W_S SOB base */	7929	ctl \|= FIELD_PREP(GAUDI_PKT_SHORT_CTL_BASE_MASK, 3); /* W_S SOB base */
7955	ctl \|= FIELD_PREP(GAUDI_PKT_SHORT_CTL_OPCODE_MASK, PACKET_MSG_SHORT);	7930	ctl \|= FIELD_PREP(GAUDI_PKT_SHORT_CTL_OPCODE_MASK, PACKET_MSG_SHORT);
7956	ctl \|= FIELD_PREP(GAUDI_PKT_SHORT_CTL_EB_MASK, 1);	7931	ctl \|= FIELD_PREP(GAUDI_PKT_SHORT_CTL_EB_MASK, eb);
7957	ctl \|= FIELD_PREP(GAUDI_PKT_SHORT_CTL_RB_MASK, 1);	7932	ctl \|= FIELD_PREP(GAUDI_PKT_SHORT_CTL_RB_MASK, 1);
7958	ctl \|= FIELD_PREP(GAUDI_PKT_SHORT_CTL_MB_MASK, 1);	7933	ctl \|= FIELD_PREP(GAUDI_PKT_SHORT_CTL_MB_MASK, 1);
7959		7934

drivers/misc/habanalabs/gaudi/gaudiP.h+0−7

@@ -105,13 +105,6 @@ · 104 unmodified lines
105	#define MME_ACC_OFFSET (mmMME1_ACC_BASE - mmMME0_ACC_BASE)	105	#define MME_ACC_OFFSET (mmMME1_ACC_BASE - mmMME0_ACC_BASE)
106	#define SRAM_BANK_OFFSET (mmSRAM_Y0_X1_RTR_BASE - mmSRAM_Y0_X0_RTR_BASE)	106	#define SRAM_BANK_OFFSET (mmSRAM_Y0_X1_RTR_BASE - mmSRAM_Y0_X0_RTR_BASE)
107		107
108	#define PLL_NR_OFFSET 0
109	#define PLL_NF_OFFSET (mmPSOC_CPU_PLL_NF - mmPSOC_CPU_PLL_NR)
110	#define PLL_OD_OFFSET (mmPSOC_CPU_PLL_OD - mmPSOC_CPU_PLL_NR)
111	#define PLL_DIV_FACTOR_0_OFFSET (mmPSOC_CPU_PLL_DIV_FACTOR_0 - \
112	mmPSOC_CPU_PLL_NR)
113	#define PLL_DIV_SEL_0_OFFSET (mmPSOC_CPU_PLL_DIV_SEL_0 - mmPSOC_CPU_PLL_NR)
114
115	#define NUM_OF_SOB_IN_BLOCK \	108	#define NUM_OF_SOB_IN_BLOCK \
116	(((mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_2047 - \	109	(((mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_2047 - \
117	mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0) + 4) >> 2)	110	mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0) + 4) >> 2)

drivers/misc/habanalabs/gaudi/gaudi_coresight.c+2−1

 #include "../include/gaudi/gaudi_coresight.h"
 #include "../include/gaudi/asic_reg/gaudi_regs.h"
 #include "../include/gaudi/gaudi_masks.h"
+#include "../include/gaudi/gaudi_reg_map.h"
 #include <uapi/misc/habanalabs.h>
 #define SPMU_SECTION_SIZE		MME0_ACC_SPMU_MAX_OFFSET
 	}
 	/* Perform read from the device to flush all configuration */
-	RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG);
+	RREG32(mmHW_STATE);
 	return rc;
 }

drivers/misc/habanalabs/goya/goya.c+45−30

@@ -613,12 +613,6 @@ static int goya_early_init(struct hl_device *hdev) · 612 unmodified lines
613	if (rc)	613	if (rc)
614	goto free_queue_props;	614	goto free_queue_props;
615		615
616	if (goya_get_hw_state(hdev) == HL_DEVICE_HW_STATE_DIRTY) {
617	dev_info(hdev->dev,
618	"H/W state is dirty, must reset before initializing\n");
619	hdev->asic_funcs->hw_fini(hdev, true);
620	}
621
622	/* Before continuing in the initialization, we need to read the preboot	616	/* Before continuing in the initialization, we need to read the preboot
623	* version to determine whether we run with a security-enabled firmware	617	* version to determine whether we run with a security-enabled firmware
624	*/	618	*/
@@ -631,6 +625,12 @@ static int goya_early_init(struct hl_device *hdev) · 6 unmodified lines
631	goto pci_fini;	625	goto pci_fini;
632	}	626	}
633		627
		628	if (goya_get_hw_state(hdev) == HL_DEVICE_HW_STATE_DIRTY) {
		629	dev_info(hdev->dev,
		630	"H/W state is dirty, must reset before initializing\n");
		631	hdev->asic_funcs->hw_fini(hdev, true);
		632	}
		633
634	if (!hdev->pldm) {	634	if (!hdev->pldm) {
635	val = RREG32(mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS);	635	val = RREG32(mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS);
636	if (val & PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_SRIOV_EN_MASK)	636	if (val & PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_SRIOV_EN_MASK)
@@ -694,32 +694,47 @@ static void goya_qman0_set_security(struct hl_device *hdev, bool secure) · 57 unmodified lines
694	static void goya_fetch_psoc_frequency(struct hl_device *hdev)	694	static void goya_fetch_psoc_frequency(struct hl_device *hdev)
695	{	695	{
696	struct asic_fixed_properties *prop = &hdev->asic_prop;	696	struct asic_fixed_properties *prop = &hdev->asic_prop;
697	u32 trace_freq = 0;	697	u32 nr = 0, nf = 0, od = 0, div_fctr = 0, pll_clk, div_sel;
698	u32 pll_clk = 0;	698	u16 pll_freq_arr[HL_PLL_NUM_OUTPUTS], freq;
699	u32 div_fctr = RREG32(mmPSOC_PCI_PLL_DIV_FACTOR_1);	699	int rc;
700	u32 div_sel = RREG32(mmPSOC_PCI_PLL_DIV_SEL_1);	700
701	u32 nr = RREG32(mmPSOC_PCI_PLL_NR);	701	if (hdev->asic_prop.fw_security_disabled) {
702	u32 nf = RREG32(mmPSOC_PCI_PLL_NF);	702	div_fctr = RREG32(mmPSOC_PCI_PLL_DIV_FACTOR_1);
703	u32 od = RREG32(mmPSOC_PCI_PLL_OD);	703	div_sel = RREG32(mmPSOC_PCI_PLL_DIV_SEL_1);
704		704	nr = RREG32(mmPSOC_PCI_PLL_NR);
705	if (div_sel == DIV_SEL_REF_CLK \|\| div_sel == DIV_SEL_DIVIDED_REF) {	705	nf = RREG32(mmPSOC_PCI_PLL_NF);
706	if (div_sel == DIV_SEL_REF_CLK)	706	od = RREG32(mmPSOC_PCI_PLL_OD);
707	trace_freq = PLL_REF_CLK;	707
708	else	708	if (div_sel == DIV_SEL_REF_CLK \|\|
709	trace_freq = PLL_REF_CLK / (div_fctr + 1);	709	div_sel == DIV_SEL_DIVIDED_REF) {
710	} else if (div_sel == DIV_SEL_PLL_CLK \|\|	710	if (div_sel == DIV_SEL_REF_CLK)
711	div_sel == DIV_SEL_DIVIDED_PLL) {	711	freq = PLL_REF_CLK;
712	pll_clk = PLL_REF_CLK * (nf + 1) / ((nr + 1) * (od + 1));	712	else
713	if (div_sel == DIV_SEL_PLL_CLK)	713	freq = PLL_REF_CLK / (div_fctr + 1);
714	trace_freq = pll_clk;	714	} else if (div_sel == DIV_SEL_PLL_CLK \|\|
715	else	715	div_sel == DIV_SEL_DIVIDED_PLL) {
716	trace_freq = pll_clk / (div_fctr + 1);	716	pll_clk = PLL_REF_CLK * (nf + 1) /
		717	((nr + 1) * (od + 1));
		718	if (div_sel == DIV_SEL_PLL_CLK)
		719	freq = pll_clk;
		720	else
		721	freq = pll_clk / (div_fctr + 1);
		722	} else {
		723	dev_warn(hdev->dev,
		724	"Received invalid div select value: %d",
		725	div_sel);
		726	freq = 0;
		727	}
717	} else {	728	} else {
718	dev_warn(hdev->dev,	729	rc = hl_fw_cpucp_pll_info_get(hdev, PCI_PLL, pll_freq_arr);
719	"Received invalid div select value: %d", div_sel);	730
		731	if (rc)
		732	return;
		733
		734	freq = pll_freq_arr[1];
720	}	735	}
721		736
722	prop->psoc_timestamp_frequency = trace_freq;	737	prop->psoc_timestamp_frequency = freq;
723	prop->psoc_pci_pll_nr = nr;	738	prop->psoc_pci_pll_nr = nr;
724	prop->psoc_pci_pll_nf = nf;	739	prop->psoc_pci_pll_nf = nf;
725	prop->psoc_pci_pll_od = od;	740	prop->psoc_pci_pll_od = od;
@@ -5324,7 +5339,7 @@ static u32 goya_get_wait_cb_size(struct hl_device *hdev) · 4598 unmodified lines
5324	}	5339	}
5325		5340
5326	static u32 goya_gen_signal_cb(struct hl_device hdev, void data, u16 sob_id,	5341	static u32 goya_gen_signal_cb(struct hl_device hdev, void data, u16 sob_id,
5327	u32 size)	5342	u32 size, bool eb)
5328	{	5343	{
5329	return 0;	5344	return 0;
5330	}	5345	}

drivers/misc/habanalabs/include/common/hl_boot_if.h+8−1

  *					implemented. This means that FW will
  *					perform hard reset procedure on
  *					receiving the halt-machine event.
- *					Initialized in: linux
+ *					Initialized in: preboot, u-boot, linux
  *
  * CPU_BOOT_DEV_STS0_PLL_INFO_EN	FW retrieval of PLL info is enabled.
  *					Initialized in: linux
  *
+ * CPU_BOOT_DEV_STS0_CLK_GATE_EN	Clock Gating enabled.
+ *					FW initialized Clock Gating.
+ *					Initialized in: preboot
+ *
  * CPU_BOOT_DEV_STS0_ENABLED		Device status register enabled.
  *					This is a main indication that the
  *					running FW populates the device status
 #define CPU_BOOT_DEV_STS0_DRAM_SCR_EN			(1 << 9)
 #define CPU_BOOT_DEV_STS0_FW_HARD_RST_EN		(1 << 10)
 #define CPU_BOOT_DEV_STS0_PLL_INFO_EN			(1 << 11)
+#define CPU_BOOT_DEV_STS0_CLK_GATE_EN			(1 << 13)
 #define CPU_BOOT_DEV_STS0_ENABLED			(1 << 31)
 enum cpu_boot_status {
 	KMD_MSG_GOTO_WFE,
 	KMD_MSG_FIT_RDY,
 	KMD_MSG_SKIP_BMC,
+	RESERVED,
+	KMD_MSG_RST_DEV,
 };
 enum cpu_msg_status {

drivers/misc/pvpanic.c+15−4

 	struct resource *res;
 	res = platform_get_mem_or_io(pdev, 0);
-	if (res && resource_type(res) == IORESOURCE_IO)
+	if (!res)
+		return -EINVAL;
+	switch (resource_type(res)) {
+	case IORESOURCE_IO:
 		base = devm_ioport_map(dev, res->start, resource_size(res));
-	else
+		if (!base)
+			return -ENOMEM;
+		break;
+	case IORESOURCE_MEM:
 		base = devm_ioremap_resource(dev, res);
-	if (IS_ERR(base))
+		if (IS_ERR(base))
-		return PTR_ERR(base);
+			return PTR_ERR(base);
+		break;
+	default:
+		return -EINVAL;
+	}
 	atomic_notifier_chain_register(&panic_notifier_list,
 				       &pvpanic_panic_nb);

drivers/net/bareudp.c+16−9

 		goto free_dst;
 	min_headroom = LL_RESERVED_SPACE(dst->dev) + dst->header_len +
-		BAREUDP_BASE_HLEN + info->options_len + sizeof(struct iphdr);
+		BAREUDP_BASE_HLEN + info->options_len + sizeof(struct ipv6hdr);
 	err = skb_cow_head(skb, min_headroom);
 	if (unlikely(err))
 	SET_NETDEV_DEVTYPE(dev, &bareudp_type);
 	dev->features    |= NETIF_F_SG | NETIF_F_HW_CSUM;
 	dev->features    |= NETIF_F_RXCSUM;
+	dev->features    |= NETIF_F_LLTX;
 	dev->features    |= NETIF_F_GSO_SOFTWARE;
 	dev->hw_features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
 	dev->hw_features |= NETIF_F_GSO_SOFTWARE;
 	return 0;
 }
+static void bareudp_dellink(struct net_device *dev, struct list_head *head)
+{
+	struct bareudp_dev *bareudp = netdev_priv(dev);
+	list_del(&bareudp->next);
+	unregister_netdevice_queue(dev, head);
+}
 static int bareudp_newlink(struct net *net, struct net_device *dev,
 			   struct nlattr *tb[], struct nlattr *data[],
 			   struct netlink_ext_ack *extack)
 {
 	struct bareudp_conf conf;
+	LIST_HEAD(list_kill);
 	int err;
 	err = bareudp2info(data, &conf, extack);
 	err = bareudp_link_config(dev, tb);
 	if (err)
-		return err;
+		goto err_unconfig;
 	return 0;
-}
-static void bareudp_dellink(struct net_device *dev, struct list_head *head)
-{
-	struct bareudp_dev *bareudp = netdev_priv(dev);
-	list_del(&bareudp->next);
+err_unconfig:
-	unregister_netdevice_queue(dev, head);
+	bareudp_dellink(dev, &list_kill);
+	unregister_netdevice_many(&list_kill);
+	return err;
 }
 static size_t bareudp_get_size(const struct net_device *dev)

drivers/net/can/Kconfig+1−0

@@ -123,6 +123,7 @@ config CAN_JANZ_ICAN3 · 122 unmodified lines
123	config CAN_KVASER_PCIEFD	123	config CAN_KVASER_PCIEFD
124	depends on PCI	124	depends on PCI
125	tristate "Kvaser PCIe FD cards"	125	tristate "Kvaser PCIe FD cards"
		126	select CRC32
126	help	127	help
127	This is a driver for the Kvaser PCI Express CAN FD family.	128	This is a driver for the Kvaser PCI Express CAN FD family.
128		129

drivers/net/can/m_can/m_can.c+0−2

@@ -1852,8 +1852,6 @@ EXPORT_SYMBOL_GPL(m_can_class_register); · 1851 unmodified lines
1852	void m_can_class_unregister(struct m_can_classdev *cdev)	1852	void m_can_class_unregister(struct m_can_classdev *cdev)
1853	{	1853	{
1854	unregister_candev(cdev->net);	1854	unregister_candev(cdev->net);
1855
1856	m_can_clk_stop(cdev);
1857	}	1855	}
1858	EXPORT_SYMBOL_GPL(m_can_class_unregister);	1856	EXPORT_SYMBOL_GPL(m_can_class_unregister);
1859		1857

drivers/net/can/m_can/tcan4x5x.c+0−26

@@ -131,30 +131,6 @@ static inline struct tcan4x5x_priv cdev_to_priv(struct m_can_classdev cdev) · 130 unmodified lines
131		131
132	}	132	}
133		133
134	static struct can_bittiming_const tcan4x5x_bittiming_const = {
135	.name = DEVICE_NAME,
136	.tseg1_min = 2,
137	.tseg1_max = 31,
138	.tseg2_min = 2,
139	.tseg2_max = 16,
140	.sjw_max = 16,
141	.brp_min = 1,
142	.brp_max = 32,
143	.brp_inc = 1,
144	};
145
146	static struct can_bittiming_const tcan4x5x_data_bittiming_const = {
147	.name = DEVICE_NAME,
148	.tseg1_min = 1,
149	.tseg1_max = 32,
150	.tseg2_min = 1,
151	.tseg2_max = 16,
152	.sjw_max = 16,
153	.brp_min = 1,
154	.brp_max = 32,
155	.brp_inc = 1,
156	};
157
158	static void tcan4x5x_check_wake(struct tcan4x5x_priv *priv)	134	static void tcan4x5x_check_wake(struct tcan4x5x_priv *priv)
159	{	135	{
160	int wake_state = 0;	136	int wake_state = 0;
@@ -469,8 +445,6 @@ static int tcan4x5x_can_probe(struct spi_device *spi) · 308 unmodified lines
469	mcan_class->dev = &spi->dev;	445	mcan_class->dev = &spi->dev;
470	mcan_class->ops = &tcan4x5x_ops;	446	mcan_class->ops = &tcan4x5x_ops;
471	mcan_class->is_peripheral = true;	447	mcan_class->is_peripheral = true;
472	mcan_class->bit_timing = &tcan4x5x_bittiming_const;
473	mcan_class->data_timing = &tcan4x5x_data_bittiming_const;
474	mcan_class->net->irq = spi->irq;	448	mcan_class->net->irq = spi->irq;
475		449
476	spi_set_drvdata(spi, priv);	450	spi_set_drvdata(spi, priv);

drivers/net/can/rcar/Kconfig+2−2

@@ -1,10 +1,10 @@
1	# SPDX-License-Identifier: GPL-2.0	1	# SPDX-License-Identifier: GPL-2.0
2	config CAN_RCAR	2	config CAN_RCAR
3	tristate "Renesas R-Car CAN controller"	3	tristate "Renesas R-Car and RZ/G CAN controller"
4	depends on ARCH_RENESAS \|\| ARM	4	depends on ARCH_RENESAS \|\| ARM
5	help	5	help
6	Say Y here if you want to use CAN controller found on Renesas R-Car	6	Say Y here if you want to use CAN controller found on Renesas R-Car
7	SoCs.	7	or RZ/G SoCs.
8		8
9	To compile this driver as a module, choose M here: the module will	9	To compile this driver as a module, choose M here: the module will
10	be called rcar_can.	10	be called rcar_can.

drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c+9−10

@@ -1368,13 +1368,10 @@ static int mcp251xfd_handle_tefif(struct mcp251xfd_priv *priv) · 1367 unmodified lines
1368	struct mcp251xfd_tx_ring *tx_ring = priv->tx;	1368	struct mcp251xfd_tx_ring *tx_ring = priv->tx;
1369	struct spi_transfer *last_xfer;	1369	struct spi_transfer *last_xfer;
1370		1370
1371	tx_ring->tail += len;
1372
1373	/* Increment the TEF FIFO tail pointer 'len' times in	1371	/* Increment the TEF FIFO tail pointer 'len' times in
1374	* a single SPI message.	1372	* a single SPI message.
1375	*/	1373	*
1376		1374	* Note:
1377	/* Note:
1378	*	1375	*
1379	* "cs_change == 1" on the last transfer results in an	1376	* "cs_change == 1" on the last transfer results in an
1380	* active chip select after the complete SPI	1377	* active chip select after the complete SPI
@@ -1391,6 +1388,8 @@ static int mcp251xfd_handle_tefif(struct mcp251xfd_priv *priv) · 10 unmodified lines
1391	if (err)	1388	if (err)
1392	return err;	1389	return err;
1393		1390
		1391	tx_ring->tail += len;
		1392
1394	err = mcp251xfd_check_tef_tail(priv);	1393	err = mcp251xfd_check_tef_tail(priv);
1395	if (err)	1394	if (err)
1396	return err;	1395	return err;
@@ -1492,7 +1491,7 @@ mcp251xfd_handle_rxif_one(struct mcp251xfd_priv *priv, · 95 unmodified lines
1492	else	1491	else
1493	skb = alloc_can_skb(priv->ndev, (struct can_frame **)&cfd);	1492	skb = alloc_can_skb(priv->ndev, (struct can_frame **)&cfd);
1494		1493
1495	if (!cfd) {	1494	if (!skb) {
1496	stats->rx_dropped++;	1495	stats->rx_dropped++;
1497	return 0;	1496	return 0;
1498	}	1497	}
@@ -1553,10 +1552,8 @@ mcp251xfd_handle_rxif_ring(struct mcp251xfd_priv *priv, · 54 unmodified lines
1553		1552
1554	/* Increment the RX FIFO tail pointer 'len' times in a	1553	/* Increment the RX FIFO tail pointer 'len' times in a
1555	* single SPI message.	1554	* single SPI message.
1556	*/	1555	*
1557	ring->tail += len;	1556	* Note:
1558
1559	/* Note:
1560	*	1557	*
1561	* "cs_change == 1" on the last transfer results in an	1558	* "cs_change == 1" on the last transfer results in an
1562	* active chip select after the complete SPI	1559	* active chip select after the complete SPI
@@ -1572,6 +1569,8 @@ mcp251xfd_handle_rxif_ring(struct mcp251xfd_priv *priv, · 9 unmodified lines
1572	last_xfer->cs_change = 1;	1569	last_xfer->cs_change = 1;
1573	if (err)	1570	if (err)
1574	return err;	1571	return err;
		1572
		1573	ring->tail += len;
1575	}	1574	}
1576		1575
1577	return 0;	1576	return 0;

drivers/net/dsa/hirschmann/Kconfig+1−0

@@ -4,6 +4,7 @@ config NET_DSA_HIRSCHMANN_HELLCREEK · 3 unmodified lines
4	depends on HAS_IOMEM	4	depends on HAS_IOMEM
5	depends on NET_DSA	5	depends on NET_DSA
6	depends on PTP_1588_CLOCK	6	depends on PTP_1588_CLOCK
		7	depends on LEDS_CLASS
7	select NET_DSA_TAG_HELLCREEK	8	select NET_DSA_TAG_HELLCREEK
8	help	9	help
9	This driver adds support for Hirschmann Hellcreek TSN switches.	10	This driver adds support for Hirschmann Hellcreek TSN switches.

drivers/net/dsa/lantiq_gswip.c+11−23

 					 GSWIP_MDIO_PHY_FDUP_MASK)
 /* GSWIP MII Registers */
-#define GSWIP_MII_CFG0			0x00
+#define GSWIP_MII_CFGp(p)		(0x2 * (p))
-#define GSWIP_MII_CFG1			0x02
-#define GSWIP_MII_CFG5			0x04
 #define  GSWIP_MII_CFG_EN		BIT(14)
 #define  GSWIP_MII_CFG_LDCLKDIS		BIT(12)
 #define  GSWIP_MII_CFG_MODE_MIIP	0x0
 static void gswip_mii_mask_cfg(struct gswip_priv *priv, u32 clear, u32 set,
 			       int port)
 {
-	switch (port) {
+	/* There's no MII_CFG register for the CPU port */
-	case 0:
+	if (!dsa_is_cpu_port(priv->ds, port))
-		gswip_mii_mask(priv, clear, set, GSWIP_MII_CFG0);
+		gswip_mii_mask(priv, clear, set, GSWIP_MII_CFGp(port));
-		break;
-	case 1:
-		gswip_mii_mask(priv, clear, set, GSWIP_MII_CFG1);
-		break;
-	case 5:
-		gswip_mii_mask(priv, clear, set, GSWIP_MII_CFG5);
-		break;
-	}
 }
 static void gswip_mii_mask_pcdu(struct gswip_priv *priv, u32 clear, u32 set,
 	gswip_mdio_mask(priv, 0xff, 0x09, GSWIP_MDIO_MDC_CFG1);
 	/* Disable the xMII link */
-	gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, 0);
+	for (i = 0; i < priv->hw_info->max_ports; i++)
-	gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, 1);
+		gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, i);
-	gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, 5);
 	/* enable special tag insertion on cpu port */
 	gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_STEN,
 	phylink_set(mask, Pause);
 	phylink_set(mask, Asym_Pause);
-	/* With the exclusion of MII and Reverse MII, we support Gigabit,
+	/* With the exclusion of MII, Reverse MII and Reduced MII, we
-	 * including Half duplex
+	 * support Gigabit, including Half duplex
 	 */
 	if (state->interface != PHY_INTERFACE_MODE_MII &&
-	    state->interface != PHY_INTERFACE_MODE_REVMII) {
+	    state->interface != PHY_INTERFACE_MODE_REVMII &&
+	    state->interface != PHY_INTERFACE_MODE_RMII) {
 		phylink_set(mask, 1000baseT_Full);
 		phylink_set(mask, 1000baseT_Half);
 	}
 {
 	struct gswip_priv *priv = ds->priv;
-	/* Enable the xMII interface only for the external PHY */
+	gswip_mii_mask_cfg(priv, 0, GSWIP_MII_CFG_EN, port);
-	if (interface != PHY_INTERFACE_MODE_INTERNAL)
-		gswip_mii_mask_cfg(priv, 0, GSWIP_MII_CFG_EN, port);
 }
 static void gswip_get_strings(struct dsa_switch *ds, int port, u32 stringset,

drivers/net/ethernet/aquantia/Kconfig+0−1

@@ -19,7 +19,6 @@ if NET_VENDOR_AQUANTIA · 18 unmodified lines
19	config AQTION	19	config AQTION
20	tristate "aQuantia AQtion(tm) Support"	20	tristate "aQuantia AQtion(tm) Support"
21	depends on PCI	21	depends on PCI
22	depends on X86_64 \|\| ARM64 \|\| COMPILE_TEST
23	depends on MACSEC \|\| MACSEC=n	22	depends on MACSEC \|\| MACSEC=n
24	help	23	help
25	This enables the support for the aQuantia AQtion(tm) Ethernet card.	24	This enables the support for the aQuantia AQtion(tm) Ethernet card.

drivers/net/ethernet/broadcom/bcmsysport.c+1−0

@@ -2577,6 +2577,7 @@ static int bcm_sysport_probe(struct platform_device *pdev) · 2576 unmodified lines
2577	NETIF_F_HW_VLAN_CTAG_TX;	2577	NETIF_F_HW_VLAN_CTAG_TX;
2578	dev->hw_features \|= dev->features;	2578	dev->hw_features \|= dev->features;
2579	dev->vlan_features \|= dev->features;	2579	dev->vlan_features \|= dev->features;
		2580	dev->max_mtu = UMAC_MAX_MTU_SIZE;
2580		2581
2581	/* Request the WOL interrupt and advertise suspend if available */	2582	/* Request the WOL interrupt and advertise suspend if available */
2582	priv->wol_irq_disabled = 1;	2583	priv->wol_irq_disabled = 1;

drivers/net/ethernet/broadcom/bnxt/bnxt.c+19−19

 		ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
 		if (!ctx->tqm_fp_rings_count)
 			ctx->tqm_fp_rings_count = bp->max_q;
+		else if (ctx->tqm_fp_rings_count > BNXT_MAX_TQM_FP_RINGS)
+			ctx->tqm_fp_rings_count = BNXT_MAX_TQM_FP_RINGS;
-		tqm_rings = ctx->tqm_fp_rings_count + 1;
+		tqm_rings = ctx->tqm_fp_rings_count + BNXT_MAX_TQM_SP_RINGS;
 		ctx_pg = kcalloc(tqm_rings, sizeof(*ctx_pg), GFP_KERNEL);
 		if (!ctx_pg) {
 			kfree(ctx);
 	     pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl,
 	     pg_dir = &req.tqm_sp_page_dir,
 	     ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP;
-	     i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
+	     i < BNXT_MAX_TQM_RINGS;
+	     i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
 		if (!(enables & ena))
 			continue;
  */
 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
 {
+	pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
 	struct net_device *netdev = pci_get_drvdata(pdev);
 	struct bnxt *bp = netdev_priv(netdev);
 	int err = 0, off;
-	pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
 	netdev_info(bp->dev, "PCI Slot Reset\n");
 		pci_save_state(pdev);
 		err = bnxt_hwrm_func_reset(bp);
-		if (!err) {
+		if (!err)
-			err = bnxt_hwrm_func_qcaps(bp);
-			if (!err && netif_running(netdev))
-				err = bnxt_open(netdev);
-		}
-		bnxt_ulp_start(bp, err);
-		if (!err) {
-			bnxt_reenable_sriov(bp);
 			result = PCI_ERS_RESULT_RECOVERED;
-		}
-	}
-	if (result != PCI_ERS_RESULT_RECOVERED) {
-		if (netif_running(netdev))
-			dev_close(netdev);
-		pci_disable_device(pdev);
 	}
 	rtnl_unlock();
 static void bnxt_io_resume(struct pci_dev *pdev)
 {
 	struct net_device *netdev = pci_get_drvdata(pdev);
+	struct bnxt *bp = netdev_priv(netdev);
+	int err;
+	netdev_info(bp->dev, "PCI Slot Resume\n");
 	rtnl_lock();
-	netif_device_attach(netdev);
+	err = bnxt_hwrm_func_qcaps(bp);
+	if (!err && netif_running(netdev))
+		err = bnxt_open(netdev);
+	bnxt_ulp_start(bp, err);
+	if (!err) {
+		bnxt_reenable_sriov(bp);
+		netif_device_attach(netdev);
+	}
 	rtnl_unlock();
 }

drivers/net/ethernet/broadcom/bnxt/bnxt.h+6−1

 	struct bnxt_ctx_pg_info **ctx_pg_tbl;
 };
+#define BNXT_MAX_TQM_SP_RINGS		1
+#define BNXT_MAX_TQM_FP_RINGS		8
+#define BNXT_MAX_TQM_RINGS		\
+	(BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_RINGS)
 struct bnxt_ctx_mem_info {
 	u32	qp_max_entries;
 	u16	qp_min_qp1_entries;
 	struct bnxt_ctx_pg_info stat_mem;
 	struct bnxt_ctx_pg_info mrav_mem;
 	struct bnxt_ctx_pg_info tim_mem;
-	struct bnxt_ctx_pg_info *tqm_mem[9];
+	struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TQM_RINGS];
 };
 struct bnxt_fw_health {

drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c+2−1

 		if (rc && ((struct hwrm_err_output *)&resp)->cmd_err ==
 		    NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR) {
-			install.flags |=
+			install.flags =
 				cpu_to_le16(NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG);
 			rc = _hwrm_send_message_silent(bp, &install,
 				 * UPDATE directory and try the flash again
 				 */
 				defrag_attempted = true;
+				install.flags = 0;
 				rc = __bnxt_flash_nvram(bp->dev,
 							BNX_DIR_TYPE_UPDATE,
 							BNX_DIR_ORDINAL_FIRST,

drivers/net/ethernet/broadcom/bnxt/bnxt_ulp.c+6−2

 int bnxt_get_ulp_stat_ctxs(struct bnxt *bp)
 {
-	if (bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP))
+	if (bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP)) {
-		return BNXT_MIN_ROCE_STAT_CTXS;
+		struct bnxt_en_dev *edev = bp->edev;
+		if (edev->ulp_tbl[BNXT_ROCE_ULP].msix_requested)
+			return BNXT_MIN_ROCE_STAT_CTXS;
+	}
 	return 0;
 }

drivers/net/ethernet/cadence/macb_main.c+1−1

@@ -467,7 +467,7 @@ static void macb_set_tx_clk(struct macb *bp, int speed) · 466 unmodified lines
467	{	467	{
468	long ferr, rate, rate_rounded;	468	long ferr, rate, rate_rounded;
469		469
470	if (!bp->tx_clk \|\| !(bp->caps & MACB_CAPS_CLK_HW_CHG))	470	if (!bp->tx_clk \|\| (bp->caps & MACB_CAPS_CLK_HW_CHG))
471	return;	471	return;
472		472
473	switch (speed) {	473	switch (speed) {

drivers/net/ethernet/chelsio/cxgb4/t4_tcb.h+7−0

@@ -40,6 +40,13 @@ · 39 unmodified lines
40	#define TCB_L2T_IX_M 0xfffULL	40	#define TCB_L2T_IX_M 0xfffULL
41	#define TCB_L2T_IX_V(x) ((x) << TCB_L2T_IX_S)	41	#define TCB_L2T_IX_V(x) ((x) << TCB_L2T_IX_S)
42		42
		43	#define TCB_T_FLAGS_W 1
		44	#define TCB_T_FLAGS_S 0
		45	#define TCB_T_FLAGS_M 0xffffffffffffffffULL
		46	#define TCB_T_FLAGS_V(x) ((__u64)(x) << TCB_T_FLAGS_S)
		47
		48	#define TCB_FIELD_COOKIE_TFLAG 1
		49
43	#define TCB_SMAC_SEL_W 0	50	#define TCB_SMAC_SEL_W 0
44	#define TCB_SMAC_SEL_S 24	51	#define TCB_SMAC_SEL_S 24
45	#define TCB_SMAC_SEL_M 0xffULL	52	#define TCB_SMAC_SEL_M 0xffULL

drivers/net/ethernet/chelsio/inline_crypto/chtls/chtls.h+4−0

 void chtls_tcp_push(struct sock *sk, int flags);
 int chtls_push_frames(struct chtls_sock *csk, int comp);
 int chtls_set_tcb_tflag(struct sock *sk, unsigned int bit_pos, int val);
+void chtls_set_tcb_field_rpl_skb(struct sock *sk, u16 word,
+				 u64 mask, u64 val, u8 cookie,
+				 int through_l2t);
 int chtls_setkey(struct chtls_sock *csk, u32 keylen, u32 mode, int cipher_type);
+void chtls_set_quiesce_ctrl(struct sock *sk, int val);
 void skb_entail(struct sock *sk, struct sk_buff *skb, int flags);
 unsigned int keyid_to_addr(int start_addr, int keyid);
 void free_tls_keyid(struct sock *sk);

drivers/net/ethernet/chelsio/inline_crypto/chtls/chtls_cm.c+54−49

 #include "chtls.h"
 #include "chtls_cm.h"
 #include "clip_tbl.h"
+#include "t4_tcb.h"
 /*
  * State transitions and actions for close.  Note that if we are in SYN_SENT
 	if (sk->sk_state != TCP_SYN_RECV)
 		chtls_send_abort(sk, mode, skb);
 	else
-		goto out;
+		chtls_set_tcb_field_rpl_skb(sk, TCB_T_FLAGS_W,
+					    TCB_T_FLAGS_V(TCB_T_FLAGS_M), 0,
+					    TCB_FIELD_COOKIE_TFLAG, 1);
 	return;
 out:
 	while (!skb_queue_empty(&listen_ctx->synq)) {
 		struct chtls_sock *csk =
-			container_of((struct synq *)__skb_dequeue
+			container_of((struct synq *)skb_peek
 				(&listen_ctx->synq), struct chtls_sock, synq);
 		struct sock *child = csk->sk;
 				    const struct cpl_pass_accept_req *req,
 				    struct chtls_dev *cdev)
 {
+	struct adapter *adap = pci_get_drvdata(cdev->pdev);
 	struct neighbour *n = NULL;
 	struct inet_sock *newinet;
 	const struct iphdr *iph;
 	struct dst_entry *dst;
 	struct tcp_sock *tp;
 	struct sock *newsk;
+	bool found = false;
 	u16 port_id;
 	int rxq_idx;
-	int step;
+	int step, i;
 	iph = (const struct iphdr *)network_hdr;
 	newsk = tcp_create_openreq_child(lsk, oreq, cdev->askb);
 		n = dst_neigh_lookup(dst, &ip6h->saddr);
 #endif
 	}
-	if (!n)
+	if (!n || !n->dev)
 		goto free_sk;
 	ndev = n->dev;
 	if (is_vlan_dev(ndev))
 		ndev = vlan_dev_real_dev(ndev);
+	for_each_port(adap, i)
+		if (cdev->ports[i] == ndev)
+			found = true;
+	if (!found)
+		goto free_dst;
 	port_id = cxgb4_port_idx(ndev);
 	csk = chtls_sock_create(cdev);
 free_csk:
 	chtls_sock_release(&csk->kref);
 free_dst:
+	neigh_release(n);
 	dst_release(dst);
 free_sk:
 	inet_csk_prepare_forced_close(newsk);
 	newsk = chtls_recv_sock(sk, oreq, network_hdr, req, cdev);
 	if (!newsk)
-		goto free_oreq;
+		goto reject;
 	if (chtls_get_module(newsk))
 		goto reject;
 	kfree_skb(skb);
 	return;
-free_oreq:
-	chtls_reqsk_free(oreq);
 reject:
 	mk_tid_release(reply_skb, 0, tid);
 	cxgb4_ofld_send(cdev->lldi->ports[0], reply_skb);
 			sk_wake_async(sk, 0, POLL_OUT);
 		data = lookup_stid(cdev->tids, stid);
+		if (!data) {
+			/* listening server close */
+			kfree_skb(skb);
+			goto unlock;
+		}
 		lsk = ((struct listen_ctx *)data)->lsk;
 		bh_lock_sock(lsk);
 		else if (tcp_sk(sk)->linger2 < 0 &&
 			 !csk_flag_nochk(csk, CSK_ABORT_SHUTDOWN))
 			chtls_abort_conn(sk, skb);
+		else if (csk_flag_nochk(csk, CSK_TX_DATA_SENT))
+			chtls_set_quiesce_ctrl(sk, 0);
 		break;
 	default:
 		pr_info("close_con_rpl in bad state %d\n", sk->sk_state);
 	spin_unlock_bh(&cdev->deferq.lock);
 }
-static void send_abort_rpl(struct sock *sk, struct sk_buff *skb,
-			   struct chtls_dev *cdev, int status, int queue)
-{
-	struct cpl_abort_req_rss *req = cplhdr(skb);
-	struct sk_buff *reply_skb;
-	struct chtls_sock *csk;
-	csk = rcu_dereference_sk_user_data(sk);
-	reply_skb = alloc_skb(sizeof(struct cpl_abort_rpl),
-			      GFP_KERNEL);
-	if (!reply_skb) {
-		req->status = (queue << 1);
-		t4_defer_reply(skb, cdev, send_defer_abort_rpl);
-		return;
-	}
-	set_abort_rpl_wr(reply_skb, GET_TID(req), status);
-	kfree_skb(skb);
-	set_wr_txq(reply_skb, CPL_PRIORITY_DATA, queue);
-	if (csk_conn_inline(csk)) {
-		struct l2t_entry *e = csk->l2t_entry;
-		if (e && sk->sk_state != TCP_SYN_RECV) {
-			cxgb4_l2t_send(csk->egress_dev, reply_skb, e);
-			return;
-		}
-	}
-	cxgb4_ofld_send(cdev->lldi->ports[0], reply_skb);
-}
 static void chtls_send_abort_rpl(struct sock *sk, struct sk_buff *skb,
 				 struct chtls_dev *cdev,
 				 int status, int queue)
 	queue = csk->txq_idx;
 	skb->sk	= NULL;
+	chtls_send_abort_rpl(child, skb, BLOG_SKB_CB(skb)->cdev,
+			     CPL_ABORT_NO_RST, queue);
 	do_abort_syn_rcv(child, lsk);
-	send_abort_rpl(child, skb, BLOG_SKB_CB(skb)->cdev,
-		       CPL_ABORT_NO_RST, queue);
 }
 static int abort_syn_rcv(struct sock *sk, struct sk_buff *skb)
 	if (!sock_owned_by_user(psk)) {
 		int queue = csk->txq_idx;
+		chtls_send_abort_rpl(sk, skb, cdev, CPL_ABORT_NO_RST, queue);
 		do_abort_syn_rcv(sk, psk);
-		send_abort_rpl(sk, skb, cdev, CPL_ABORT_NO_RST, queue);
 	} else {
 		skb->sk = sk;
 		BLOG_SKB_CB(skb)->backlog_rcv = bl_abort_syn_rcv;
 	int queue = csk->txq_idx;
 	if (is_neg_adv(req->status)) {
-		if (sk->sk_state == TCP_SYN_RECV)
-			chtls_set_tcb_tflag(sk, 0, 0);
 		kfree_skb(skb);
 		return;
 	}
 		if (sk->sk_state == TCP_SYN_RECV && !abort_syn_rcv(sk, skb))
 			return;
-		chtls_release_resources(sk);
-		chtls_conn_done(sk);
 	}
 	chtls_send_abort_rpl(sk, skb, BLOG_SKB_CB(skb)->cdev,
 			     rst_status, queue);
+	chtls_release_resources(sk);
+	chtls_conn_done(sk);
 }
 static void chtls_abort_rpl_rss(struct sock *sk, struct sk_buff *skb)
 	return 0;
 }
+static int chtls_set_tcb_rpl(struct chtls_dev *cdev, struct sk_buff *skb)
+{
+	struct cpl_set_tcb_rpl *rpl = cplhdr(skb) + RSS_HDR;
+	unsigned int hwtid = GET_TID(rpl);
+	struct sock *sk;
+	sk = lookup_tid(cdev->tids, hwtid);
+	/* return EINVAL if socket doesn't exist */
+	if (!sk)
+		return -EINVAL;
+	/* Reusing the skb as size of cpl_set_tcb_field structure
+	 * is greater than cpl_abort_req
+	 */
+	if (TCB_COOKIE_G(rpl->cookie) == TCB_FIELD_COOKIE_TFLAG)
+		chtls_send_abort(sk, CPL_ABORT_SEND_RST, NULL);
+	kfree_skb(skb);
+	return 0;
+}
 chtls_handler_func chtls_handlers[NUM_CPL_CMDS] = {
 	[CPL_PASS_OPEN_RPL]     = chtls_pass_open_rpl,
 	[CPL_CLOSE_LISTSRV_RPL] = chtls_close_listsrv_rpl,
 	[CPL_CLOSE_CON_RPL]     = chtls_conn_cpl,
 	[CPL_ABORT_REQ_RSS]     = chtls_conn_cpl,
 	[CPL_ABORT_RPL_RSS]     = chtls_conn_cpl,
-	[CPL_FW4_ACK]           = chtls_wr_ack,
+	[CPL_FW4_ACK]		= chtls_wr_ack,
+	[CPL_SET_TCB_RPL]	= chtls_set_tcb_rpl,
 };

drivers/net/ethernet/chelsio/inline_crypto/chtls/chtls_hw.c+41−0

@@ -88,6 +88,24 @@ static int chtls_set_tcb_field(struct sock *sk, u16 word, u64 mask, u64 val) · 87 unmodified lines
88	return ret < 0 ? ret : 0;	88	return ret < 0 ? ret : 0;
89	}	89	}
90		90
		91	void chtls_set_tcb_field_rpl_skb(struct sock *sk, u16 word,
		92	u64 mask, u64 val, u8 cookie,
		93	int through_l2t)
		94	{
		95	struct sk_buff *skb;
		96	unsigned int wrlen;
		97
		98	wrlen = sizeof(struct cpl_set_tcb_field) + sizeof(struct ulptx_idata);
		99	wrlen = roundup(wrlen, 16);
		100
		101	skb = alloc_skb(wrlen, GFP_KERNEL \| __GFP_NOFAIL);
		102	if (!skb)
		103	return;
		104
		105	__set_tcb_field(sk, skb, word, mask, val, cookie, 0);
		106	send_or_defer(sk, tcp_sk(sk), skb, through_l2t);
		107	}
		108
91	/*	109	/*
92	* Set one of the t_flags bits in the TCB.	110	* Set one of the t_flags bits in the TCB.
93	*/	111	*/
@@ -113,6 +131,29 @@ static int chtls_set_tcb_quiesce(struct sock *sk, int val) · 19 unmodified lines
113	TF_RX_QUIESCE_V(val));	131	TF_RX_QUIESCE_V(val));
114	}	132	}
115		133
		134	void chtls_set_quiesce_ctrl(struct sock *sk, int val)
		135	{
		136	struct chtls_sock *csk;
		137	struct sk_buff *skb;
		138	unsigned int wrlen;
		139	int ret;
		140
		141	wrlen = sizeof(struct cpl_set_tcb_field) + sizeof(struct ulptx_idata);
		142	wrlen = roundup(wrlen, 16);
		143
		144	skb = alloc_skb(wrlen, GFP_ATOMIC);
		145	if (!skb)
		146	return;
		147
		148	csk = rcu_dereference_sk_user_data(sk);
		149
		150	__set_tcb_field(sk, skb, 1, TF_RX_QUIESCE_V(1), 0, 0, 1);
		151	set_wr_txq(skb, CPL_PRIORITY_CONTROL, csk->port_id);
		152	ret = cxgb4_ofld_send(csk->egress_dev, skb);
		153	if (ret < 0)
		154	kfree_skb(skb);
		155	}
		156
116	/* TLS Key bitmap processing */	157	/* TLS Key bitmap processing */
117	int chtls_init_kmap(struct chtls_dev cdev, struct cxgb4_lld_info lldi)	158	int chtls_init_kmap(struct chtls_dev cdev, struct cxgb4_lld_info lldi)
118	{	159	{

drivers/net/ethernet/ethoc.c+2−1

 	ret = mdiobus_register(priv->mdio);
 	if (ret) {
 		dev_err(&netdev->dev, "failed to register MDIO bus\n");
-		goto free2;
+		goto free3;
 	}
 	ret = ethoc_mdio_probe(netdev);
 	netif_napi_del(&priv->napi);
 error:
 	mdiobus_unregister(priv->mdio);
+free3:
 	mdiobus_free(priv->mdio);
 free2:
 	clk_disable_unprepare(priv->clk);

drivers/net/ethernet/freescale/fs_enet/mii-bitbang.c+1−0

@@ -223,3 +223,4 @@ static struct platform_driver fs_enet_bb_mdio_driver = { · 222 unmodified lines
223	};	223	};
224		224
225	module_platform_driver(fs_enet_bb_mdio_driver);	225	module_platform_driver(fs_enet_bb_mdio_driver);
		226	MODULE_LICENSE("GPL");

drivers/net/ethernet/freescale/fs_enet/mii-fec.c+1−0

@@ -224,3 +224,4 @@ static struct platform_driver fs_enet_fec_mdio_driver = { · 223 unmodified lines
224	};	224	};
225		225
226	module_platform_driver(fs_enet_fec_mdio_driver);	226	module_platform_driver(fs_enet_fec_mdio_driver);
		227	MODULE_LICENSE("GPL");

drivers/net/ethernet/freescale/ucc_geth.c+2−1

 	INIT_WORK(&ugeth->timeout_work, ucc_geth_timeout_work);
 	netif_napi_add(dev, &ugeth->napi, ucc_geth_poll, 64);
 	dev->mtu = 1500;
+	dev->max_mtu = 1518;
 	ugeth->msg_enable = netif_msg_init(debug.msg_enable, UGETH_MSG_DEFAULT);
 	ugeth->phy_interface = phy_interface;
 	struct device_node *np = ofdev->dev.of_node;
 	unregister_netdev(dev);
-	free_netdev(dev);
 	ucc_geth_memclean(ugeth);
 	if (of_phy_is_fixed_link(np))
 		of_phy_deregister_fixed_link(np);
 	of_node_put(ugeth->ug_info->tbi_node);
 	of_node_put(ugeth->ug_info->phy_node);
+	free_netdev(dev);
 	return 0;
 }

drivers/net/ethernet/freescale/ucc_geth.h+8−1

 	u32 vtagtable[0x8];	/* 8 4-byte VLAN tags */
 	u32 tqptr;		/* a base pointer to the Tx Queues Memory
 				   Region */
-	u8 res2[0x80 - 0x74];
+	u8 res2[0x78 - 0x74];
+	u64 snums_en;
+	u32 l2l3baseptr;	/* top byte consists of a few other bit fields */
+	u16 mtu[8];
+	u8 res3[0xa8 - 0x94];
+	u32 wrrtablebase;	/* top byte is reserved */
+	u8 res4[0xc0 - 0xac];
 } __packed;
 /* structure representing Extended Filtering Global Parameters in PRAM */

drivers/net/ethernet/hisilicon/hns/hns_ethtool.c+4−0

 	/* for mutl buffer*/
 	new_skb = skb_copy(skb, GFP_ATOMIC);
 	dev_kfree_skb_any(skb);
+	if (!new_skb) {
+		netdev_err(ndev, "skb alloc failed\n");
+		return;
+	}
 	skb = new_skb;
 	check_ok = 0;

drivers/net/ethernet/hisilicon/hns3/hclge_mbx.h+2−2

@@ -169,7 +169,7 @@ struct hclgevf_mbx_arq_ring { · 168 unmodified lines
169	#define hclge_mbx_ring_ptr_move_crq(crq) \	169	#define hclge_mbx_ring_ptr_move_crq(crq) \
170	(crq->next_to_use = (crq->next_to_use + 1) % crq->desc_num)	170	(crq->next_to_use = (crq->next_to_use + 1) % crq->desc_num)
171	#define hclge_mbx_tail_ptr_move_arq(arq) \	171	#define hclge_mbx_tail_ptr_move_arq(arq) \
172	(arq.tail = (arq.tail + 1) % HCLGE_MBX_MAX_ARQ_MSG_SIZE)	172	(arq.tail = (arq.tail + 1) % HCLGE_MBX_MAX_ARQ_MSG_NUM)
173	#define hclge_mbx_head_ptr_move_arq(arq) \	173	#define hclge_mbx_head_ptr_move_arq(arq) \
174	(arq.head = (arq.head + 1) % HCLGE_MBX_MAX_ARQ_MSG_SIZE)	174	(arq.head = (arq.head + 1) % HCLGE_MBX_MAX_ARQ_MSG_NUM)
175	#endif	175	#endif

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c+6−3

 		handle->flags |= HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK;
 		handle->flags |= HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK;
-		if (hdev->hw.mac.phydev) {
+		if (hdev->hw.mac.phydev && hdev->hw.mac.phydev->drv &&
+		    hdev->hw.mac.phydev->drv->set_loopback) {
 			count += 1;
 			handle->flags |= HNAE3_SUPPORT_PHY_LOOPBACK;
 		}
 		req->ipv4_sctp_en = tuple_sets;
 		break;
 	case SCTP_V6_FLOW:
-		if ((nfc->data & RXH_L4_B_0_1) ||
+		if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 &&
-		    (nfc->data & RXH_L4_B_2_3))
+		    (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)))
 			return -EINVAL;
 		req->ipv6_sctp_en = tuple_sets;
 		vport[i].rss_tuple_sets.ipv6_udp_en =
 			HCLGE_RSS_INPUT_TUPLE_OTHER;
 		vport[i].rss_tuple_sets.ipv6_sctp_en =
+			hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 ?
+			HCLGE_RSS_INPUT_TUPLE_SCTP_NO_PORT :
 			HCLGE_RSS_INPUT_TUPLE_SCTP;
 		vport[i].rss_tuple_sets.ipv6_fragment_en =
 			HCLGE_RSS_INPUT_TUPLE_OTHER;

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h+2−0

@@ -107,6 +107,8 @@ · 106 unmodified lines
107	#define HCLGE_D_IP_BIT BIT(2)	107	#define HCLGE_D_IP_BIT BIT(2)
108	#define HCLGE_S_IP_BIT BIT(3)	108	#define HCLGE_S_IP_BIT BIT(3)
109	#define HCLGE_V_TAG_BIT BIT(4)	109	#define HCLGE_V_TAG_BIT BIT(4)
		110	#define HCLGE_RSS_INPUT_TUPLE_SCTP_NO_PORT \
		111	(HCLGE_D_IP_BIT \| HCLGE_S_IP_BIT \| HCLGE_V_TAG_BIT)
110		112
111	#define HCLGE_RSS_TC_SIZE_0 1	113	#define HCLGE_RSS_TC_SIZE_0 1
112	#define HCLGE_RSS_TC_SIZE_1 2	114	#define HCLGE_RSS_TC_SIZE_1 2

drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c+6−3

 		req->ipv4_sctp_en = tuple_sets;
 		break;
 	case SCTP_V6_FLOW:
-		if ((nfc->data & RXH_L4_B_0_1) ||
+		if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 &&
-		    (nfc->data & RXH_L4_B_2_3))
+		    (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)))
 			return -EINVAL;
 		req->ipv6_sctp_en = tuple_sets;
 		tuple_sets->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
 		tuple_sets->ipv6_tcp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
 		tuple_sets->ipv6_udp_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
-		tuple_sets->ipv6_sctp_en = HCLGEVF_RSS_INPUT_TUPLE_SCTP;
+		tuple_sets->ipv6_sctp_en =
+			hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 ?
+					HCLGEVF_RSS_INPUT_TUPLE_SCTP_NO_PORT :
+					HCLGEVF_RSS_INPUT_TUPLE_SCTP;
 		tuple_sets->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
 	}

drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h+2−0

@@ -122,6 +122,8 @@ · 121 unmodified lines
122	#define HCLGEVF_D_IP_BIT BIT(2)	122	#define HCLGEVF_D_IP_BIT BIT(2)
123	#define HCLGEVF_S_IP_BIT BIT(3)	123	#define HCLGEVF_S_IP_BIT BIT(3)
124	#define HCLGEVF_V_TAG_BIT BIT(4)	124	#define HCLGEVF_V_TAG_BIT BIT(4)
		125	#define HCLGEVF_RSS_INPUT_TUPLE_SCTP_NO_PORT \
		126	(HCLGEVF_D_IP_BIT \| HCLGEVF_S_IP_BIT \| HCLGEVF_V_TAG_BIT)
125		127
126	#define HCLGEVF_STATS_TIMER_INTERVAL 36U	128	#define HCLGEVF_STATS_TIMER_INTERVAL 36U
127		129

drivers/net/ethernet/ibm/ibmvnic.c+5−5

 	release_rx_pools(adapter);
 	release_napi(adapter);
+	release_login_buffer(adapter);
 	release_login_rsp_buffer(adapter);
 }
 				set_current_state(TASK_UNINTERRUPTIBLE);
 				schedule_timeout(60 * HZ);
 			}
-		} else if (!(rwi->reset_reason == VNIC_RESET_FATAL &&
+		} else {
-				adapter->from_passive_init)) {
 			rc = do_reset(adapter, rwi, reset_state);
 		}
 		kfree(rwi);
 	int rc;
 	if (!scrq) {
-		netdev_dbg(adapter->netdev,
+		netdev_dbg(adapter->netdev, "Invalid scrq reset.\n");
-			   "Invalid scrq reset. irq (%d) or msgs (%p).\n",
-			   scrq->irq, scrq->msgs);
 		return -EINVAL;
 	}
 		return -1;
 	}
+	release_login_buffer(adapter);
 	release_login_rsp_buffer(adapter);
 	client_data_len = vnic_client_data_len(adapter);
 	buffer_size =

drivers/net/ethernet/intel/e1000e/e1000.h+1−0

@@ -436,6 +436,7 @@ s32 e1000e_get_base_timinca(struct e1000_adapter adapter, u32 timinca); · 435 unmodified lines
436	#define FLAG2_DFLT_CRC_STRIPPING BIT(12)	436	#define FLAG2_DFLT_CRC_STRIPPING BIT(12)
437	#define FLAG2_CHECK_RX_HWTSTAMP BIT(13)	437	#define FLAG2_CHECK_RX_HWTSTAMP BIT(13)
438	#define FLAG2_CHECK_SYSTIM_OVERFLOW BIT(14)	438	#define FLAG2_CHECK_SYSTIM_OVERFLOW BIT(14)
		439	#define FLAG2_ENABLE_S0IX_FLOWS BIT(15)
439		440
440	#define E1000_RX_DESC_PS(R, i) \	441	#define E1000_RX_DESC_PS(R, i) \
441	(&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))	442	(&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))

drivers/net/ethernet/intel/e1000e/ethtool.c+46−0

@@ -23,6 +23,13 @@ struct e1000_stats { · 22 unmodified lines
23	int stat_offset;	23	int stat_offset;
24	};	24	};
25		25
		26	static const char e1000e_priv_flags_strings[][ETH_GSTRING_LEN] = {
		27	#define E1000E_PRIV_FLAGS_S0IX_ENABLED BIT(0)
		28	"s0ix-enabled",
		29	};
		30
		31	#define E1000E_PRIV_FLAGS_STR_LEN ARRAY_SIZE(e1000e_priv_flags_strings)
		32
26	#define E1000_STAT(str, m) { \	33	#define E1000_STAT(str, m) { \
27	.stat_string = str, \	34	.stat_string = str, \
28	.type = E1000_STATS, \	35	.type = E1000_STATS, \
@@ -1776,6 +1783,8 @@ static int e1000e_get_sset_count(struct net_device __always_unused *netdev, · 1747 unmodified lines
1776	return E1000_TEST_LEN;	1783	return E1000_TEST_LEN;
1777	case ETH_SS_STATS:	1784	case ETH_SS_STATS:
1778	return E1000_STATS_LEN;	1785	return E1000_STATS_LEN;
		1786	case ETH_SS_PRIV_FLAGS:
		1787	return E1000E_PRIV_FLAGS_STR_LEN;
1779	default:	1788	default:
1780	return -EOPNOTSUPP;	1789	return -EOPNOTSUPP;
1781	}	1790	}
@@ -2097,6 +2106,10 @@ static void e1000_get_strings(struct net_device __always_unused *netdev, · 315 unmodified lines
2097	p += ETH_GSTRING_LEN;	2106	p += ETH_GSTRING_LEN;
2098	}	2107	}
2099	break;	2108	break;
		2109	case ETH_SS_PRIV_FLAGS:
		2110	memcpy(data, e1000e_priv_flags_strings,
		2111	E1000E_PRIV_FLAGS_STR_LEN * ETH_GSTRING_LEN);
		2112	break;
2100	}	2113	}
2101	}	2114	}
2102		2115
@@ -2305,6 +2318,37 @@ static int e1000e_get_ts_info(struct net_device *netdev, · 202 unmodified lines
2305	return 0;	2318	return 0;
2306	}	2319	}
2307		2320
		2321	static u32 e1000e_get_priv_flags(struct net_device *netdev)
		2322	{
		2323	struct e1000_adapter *adapter = netdev_priv(netdev);
		2324	u32 priv_flags = 0;
		2325
		2326	if (adapter->flags2 & FLAG2_ENABLE_S0IX_FLOWS)
		2327	priv_flags \|= E1000E_PRIV_FLAGS_S0IX_ENABLED;
		2328
		2329	return priv_flags;
		2330	}
		2331
		2332	static int e1000e_set_priv_flags(struct net_device *netdev, u32 priv_flags)
		2333	{
		2334	struct e1000_adapter *adapter = netdev_priv(netdev);
		2335	unsigned int flags2 = adapter->flags2;
		2336
		2337	flags2 &= ~FLAG2_ENABLE_S0IX_FLOWS;
		2338	if (priv_flags & E1000E_PRIV_FLAGS_S0IX_ENABLED) {
		2339	struct e1000_hw *hw = &adapter->hw;
		2340
		2341	if (hw->mac.type < e1000_pch_cnp)
		2342	return -EINVAL;
		2343	flags2 \|= FLAG2_ENABLE_S0IX_FLOWS;
		2344	}
		2345
		2346	if (flags2 != adapter->flags2)
		2347	adapter->flags2 = flags2;
		2348
		2349	return 0;
		2350	}
		2351
2308	static const struct ethtool_ops e1000_ethtool_ops = {	2352	static const struct ethtool_ops e1000_ethtool_ops = {
2309	.supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS,	2353	.supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS,
2310	.get_drvinfo = e1000_get_drvinfo,	2354	.get_drvinfo = e1000_get_drvinfo,
@@ -2336,6 +2380,8 @@ static const struct ethtool_ops e1000_ethtool_ops = { · 25 unmodified lines
2336	.set_eee = e1000e_set_eee,	2380	.set_eee = e1000e_set_eee,
2337	.get_link_ksettings = e1000_get_link_ksettings,	2381	.get_link_ksettings = e1000_get_link_ksettings,
2338	.set_link_ksettings = e1000_set_link_ksettings,	2382	.set_link_ksettings = e1000_set_link_ksettings,
		2383	.get_priv_flags = e1000e_get_priv_flags,
		2384	.set_priv_flags = e1000e_set_priv_flags,
2339	};	2385	};
2340		2386
2341	void e1000e_set_ethtool_ops(struct net_device *netdev)	2387	void e1000e_set_ethtool_ops(struct net_device *netdev)

drivers/net/ethernet/intel/e1000e/ich8lan.c+14−3

 		return 0;
 	if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
+		struct e1000_adapter *adapter = hw->adapter;
+		bool firmware_bug = false;
 		if (force) {
 			/* Request ME un-configure ULP mode in the PHY */
 			mac_reg = er32(H2ME);
 			ew32(H2ME, mac_reg);
 		}
-		/* Poll up to 300msec for ME to clear ULP_CFG_DONE. */
+		/* Poll up to 2.5 seconds for ME to clear ULP_CFG_DONE.
+		 * If this takes more than 1 second, show a warning indicating a
+		 * firmware bug
+		 */
 		while (er32(FWSM) & E1000_FWSM_ULP_CFG_DONE) {
-			if (i++ == 30) {
+			if (i++ == 250) {
 				ret_val = -E1000_ERR_PHY;
 				goto out;
 			}
+			if (i > 100 && !firmware_bug)
+				firmware_bug = true;
 			usleep_range(10000, 11000);
 		}
-		e_dbg("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
+		if (firmware_bug)
+			e_warn("ULP_CONFIG_DONE took %dmsec.  This is a firmware bug\n", i * 10);
+		else
+			e_dbg("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
 		if (force) {
 			mac_reg = er32(H2ME);

drivers/net/ethernet/intel/e1000e/netdev.c+10−49

@@ -103,45 +103,6 @@ static const struct e1000_reg_info e1000_reg_info_tbl[] = { · 102 unmodified lines
103	{0, NULL}	103	{0, NULL}
104	};	104	};
105		105
106	struct e1000e_me_supported {
107	u16 device_id; /* supported device ID */
108	};
109
110	static const struct e1000e_me_supported me_supported[] = {
111	{E1000_DEV_ID_PCH_LPT_I217_LM},
112	{E1000_DEV_ID_PCH_LPTLP_I218_LM},
113	{E1000_DEV_ID_PCH_I218_LM2},
114	{E1000_DEV_ID_PCH_I218_LM3},
115	{E1000_DEV_ID_PCH_SPT_I219_LM},
116	{E1000_DEV_ID_PCH_SPT_I219_LM2},
117	{E1000_DEV_ID_PCH_LBG_I219_LM3},
118	{E1000_DEV_ID_PCH_SPT_I219_LM4},
119	{E1000_DEV_ID_PCH_SPT_I219_LM5},
120	{E1000_DEV_ID_PCH_CNP_I219_LM6},
121	{E1000_DEV_ID_PCH_CNP_I219_LM7},
122	{E1000_DEV_ID_PCH_ICP_I219_LM8},
123	{E1000_DEV_ID_PCH_ICP_I219_LM9},
124	{E1000_DEV_ID_PCH_CMP_I219_LM10},
125	{E1000_DEV_ID_PCH_CMP_I219_LM11},
126	{E1000_DEV_ID_PCH_CMP_I219_LM12},
127	{E1000_DEV_ID_PCH_TGP_I219_LM13},
128	{E1000_DEV_ID_PCH_TGP_I219_LM14},
129	{E1000_DEV_ID_PCH_TGP_I219_LM15},
130	{0}
131	};
132
133	static bool e1000e_check_me(u16 device_id)
134	{
135	struct e1000e_me_supported *id;
136
137	for (id = (struct e1000e_me_supported *)me_supported;
138	id->device_id; id++)
139	if (device_id == id->device_id)
140	return true;
141
142	return false;
143	}
144
145	/**	106	/**
146	* __ew32_prepare - prepare to write to MAC CSR register on certain parts	107	* __ew32_prepare - prepare to write to MAC CSR register on certain parts
147	* @hw: pointer to the HW structure	108	* @hw: pointer to the HW structure
@@ -6962,7 +6923,6 @@ static __maybe_unused int e1000e_pm_suspend(struct device *dev) · 6814 unmodified lines
6962	struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));	6923	struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
6963	struct e1000_adapter *adapter = netdev_priv(netdev);	6924	struct e1000_adapter *adapter = netdev_priv(netdev);
6964	struct pci_dev *pdev = to_pci_dev(dev);	6925	struct pci_dev *pdev = to_pci_dev(dev);
6965	struct e1000_hw *hw = &adapter->hw;
6966	int rc;	6926	int rc;
6967		6927
6968	e1000e_flush_lpic(pdev);	6928	e1000e_flush_lpic(pdev);
@@ -6970,13 +6930,13 @@ static __maybe_unused int e1000e_pm_suspend(struct device *dev) · 1 unmodified line
6970	e1000e_pm_freeze(dev);	6930	e1000e_pm_freeze(dev);
6971		6931
6972	rc = __e1000_shutdown(pdev, false);	6932	rc = __e1000_shutdown(pdev, false);
6973	if (rc)	6933	if (rc) {
6974	e1000e_pm_thaw(dev);	6934	e1000e_pm_thaw(dev);
6975		6935	} else {
6976	/* Introduce S0ix implementation */	6936	/* Introduce S0ix implementation */
6977	if (hw->mac.type >= e1000_pch_cnp &&	6937	if (adapter->flags2 & FLAG2_ENABLE_S0IX_FLOWS)
6978	!e1000e_check_me(hw->adapter->pdev->device))	6938	e1000e_s0ix_entry_flow(adapter);
6979	e1000e_s0ix_entry_flow(adapter);	6939	}
6980		6940
6981	return rc;	6941	return rc;
6982	}	6942	}
@@ -6986,12 +6946,10 @@ static __maybe_unused int e1000e_pm_resume(struct device *dev) · 3 unmodified lines
6986	struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));	6946	struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
6987	struct e1000_adapter *adapter = netdev_priv(netdev);	6947	struct e1000_adapter *adapter = netdev_priv(netdev);
6988	struct pci_dev *pdev = to_pci_dev(dev);	6948	struct pci_dev *pdev = to_pci_dev(dev);
6989	struct e1000_hw *hw = &adapter->hw;
6990	int rc;	6949	int rc;
6991		6950
6992	/* Introduce S0ix implementation */	6951	/* Introduce S0ix implementation */
6993	if (hw->mac.type >= e1000_pch_cnp &&	6952	if (adapter->flags2 & FLAG2_ENABLE_S0IX_FLOWS)
6994	!e1000e_check_me(hw->adapter->pdev->device))
6995	e1000e_s0ix_exit_flow(adapter);	6953	e1000e_s0ix_exit_flow(adapter);
6996		6954
6997	rc = __e1000_resume(pdev);	6955	rc = __e1000_resume(pdev);
@@ -7655,6 +7613,9 @@ static int e1000_probe(struct pci_dev pdev, const struct pci_device_id ent) · 657 unmodified lines
7655	if (!(adapter->flags & FLAG_HAS_AMT))	7613	if (!(adapter->flags & FLAG_HAS_AMT))
7656	e1000e_get_hw_control(adapter);	7614	e1000e_get_hw_control(adapter);
7657		7615
		7616	if (hw->mac.type >= e1000_pch_cnp)
		7617	adapter->flags2 \|= FLAG2_ENABLE_S0IX_FLOWS;
		7618
7658	strlcpy(netdev->name, "eth%d", sizeof(netdev->name));	7619	strlcpy(netdev->name, "eth%d", sizeof(netdev->name));
7659	err = register_netdev(netdev);	7620	err = register_netdev(netdev);
7660	if (err)	7621	if (err)

drivers/net/ethernet/intel/i40e/i40e.h+3−0

 	__I40E_RESET_INTR_RECEIVED,
 	__I40E_REINIT_REQUESTED,
 	__I40E_PF_RESET_REQUESTED,
+	__I40E_PF_RESET_AND_REBUILD_REQUESTED,
 	__I40E_CORE_RESET_REQUESTED,
 	__I40E_GLOBAL_RESET_REQUESTED,
 	__I40E_EMP_RESET_INTR_RECEIVED,
 };
 #define I40E_PF_RESET_FLAG	BIT_ULL(__I40E_PF_RESET_REQUESTED)
+#define I40E_PF_RESET_AND_REBUILD_FLAG	\
+	BIT_ULL(__I40E_PF_RESET_AND_REBUILD_REQUESTED)
 /* VSI state flags */
 enum i40e_vsi_state_t {

drivers/net/ethernet/intel/i40e/i40e_main.c+10−0

 static void i40e_determine_queue_usage(struct i40e_pf *pf);
 static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
 static void i40e_prep_for_reset(struct i40e_pf *pf, bool lock_acquired);
+static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit,
+				   bool lock_acquired);
 static int i40e_reset(struct i40e_pf *pf);
 static void i40e_rebuild(struct i40e_pf *pf, bool reinit, bool lock_acquired);
 static int i40e_setup_misc_vector_for_recovery_mode(struct i40e_pf *pf);
 			 "FW LLDP is disabled\n" :
 			 "FW LLDP is enabled\n");
+	} else if (reset_flags & I40E_PF_RESET_AND_REBUILD_FLAG) {
+		/* Request a PF Reset
+		 *
+		 * Resets PF and reinitializes PFs VSI.
+		 */
+		i40e_prep_for_reset(pf, lock_acquired);
+		i40e_reset_and_rebuild(pf, true, lock_acquired);
 	} else if (reset_flags & BIT_ULL(__I40E_REINIT_REQUESTED)) {
 		int v;

drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c+2−2

@@ -1772,7 +1772,7 @@ int i40e_pci_sriov_configure(struct pci_dev *pdev, int num_vfs) · 1771 unmodified lines
1772	if (num_vfs) {	1772	if (num_vfs) {
1773	if (!(pf->flags & I40E_FLAG_VEB_MODE_ENABLED)) {	1773	if (!(pf->flags & I40E_FLAG_VEB_MODE_ENABLED)) {
1774	pf->flags \|= I40E_FLAG_VEB_MODE_ENABLED;	1774	pf->flags \|= I40E_FLAG_VEB_MODE_ENABLED;
1775	i40e_do_reset_safe(pf, I40E_PF_RESET_FLAG);	1775	i40e_do_reset_safe(pf, I40E_PF_RESET_AND_REBUILD_FLAG);
1776	}	1776	}
1777	ret = i40e_pci_sriov_enable(pdev, num_vfs);	1777	ret = i40e_pci_sriov_enable(pdev, num_vfs);
1778	goto sriov_configure_out;	1778	goto sriov_configure_out;
@@ -1781,7 +1781,7 @@ int i40e_pci_sriov_configure(struct pci_dev *pdev, int num_vfs) · 2 unmodified lines
1781	if (!pci_vfs_assigned(pf->pdev)) {	1781	if (!pci_vfs_assigned(pf->pdev)) {
1782	i40e_free_vfs(pf);	1782	i40e_free_vfs(pf);
1783	pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;	1783	pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
1784	i40e_do_reset_safe(pf, I40E_PF_RESET_FLAG);	1784	i40e_do_reset_safe(pf, I40E_PF_RESET_AND_REBUILD_FLAG);
1785	} else {	1785	} else {
1786	dev_warn(&pdev->dev, "Unable to free VFs because some are assigned to VMs.\n");	1786	dev_warn(&pdev->dev, "Unable to free VFs because some are assigned to VMs.\n");
1787	ret = -EINVAL;	1787	ret = -EINVAL;

drivers/net/ethernet/intel/i40e/i40e_xsk.c+1−1

 		 * SBP is *not* set in PRT_SBPVSI (default not set).
 		 */
 		skb = i40e_construct_skb_zc(rx_ring, *bi);
-		*bi = NULL;
 		if (!skb) {
 			rx_ring->rx_stats.alloc_buff_failed++;
 			break;
 		}
+		*bi = NULL;
 		cleaned_count++;
 		i40e_inc_ntc(rx_ring);

drivers/net/ethernet/intel/iavf/iavf_main.c+1−3

 	netif_tx_stop_all_queues(netdev);
 	if (CLIENT_ALLOWED(adapter)) {
 		err = iavf_lan_add_device(adapter);
-		if (err) {
+		if (err)
-			rtnl_unlock();
 			dev_info(&pdev->dev, "Failed to add VF to client API service list: %d\n",
 				 err);
-		}
 	}
 	dev_info(&pdev->dev, "MAC address: %pM\n", adapter->hw.mac.addr);
 	if (netdev->features & NETIF_F_GRO)

drivers/net/ethernet/marvell/mvneta.c+2−2

@@ -4432,7 +4432,7 @@ static int mvneta_xdp_setup(struct net_device dev, struct bpf_prog prog, · 4431 unmodified lines
4432	struct bpf_prog *old_prog;	4432	struct bpf_prog *old_prog;
4433		4433
4434	if (prog && dev->mtu > MVNETA_MAX_RX_BUF_SIZE) {	4434	if (prog && dev->mtu > MVNETA_MAX_RX_BUF_SIZE) {
4435	NL_SET_ERR_MSG_MOD(extack, "Jumbo frames not supported on XDP");	4435	NL_SET_ERR_MSG_MOD(extack, "MTU too large for XDP");
4436	return -EOPNOTSUPP;	4436	return -EOPNOTSUPP;
4437	}	4437	}
4438		4438
@@ -5255,7 +5255,7 @@ static int mvneta_probe(struct platform_device *pdev) · 816 unmodified lines
5255	err = mvneta_port_power_up(pp, pp->phy_interface);	5255	err = mvneta_port_power_up(pp, pp->phy_interface);
5256	if (err < 0) {	5256	if (err < 0) {
5257	dev_err(&pdev->dev, "can't power up port\n");	5257	dev_err(&pdev->dev, "can't power up port\n");
5258	return err;	5258	goto err_netdev;
5259	}	5259	}
5260		5260
5261	/* Armada3700 network controller does not support per-cpu	5261	/* Armada3700 network controller does not support per-cpu

drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c+20−9

@@ -1231,7 +1231,7 @@ static void mvpp22_gop_init_rgmii(struct mvpp2_port *port) · 1230 unmodified lines
1231		1231
1232	regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val);	1232	regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val);
1233	if (port->gop_id == 2)	1233	if (port->gop_id == 2)
1234	val \|= GENCONF_CTRL0_PORT0_RGMII \| GENCONF_CTRL0_PORT1_RGMII;	1234	val \|= GENCONF_CTRL0_PORT0_RGMII;
1235	else if (port->gop_id == 3)	1235	else if (port->gop_id == 3)
1236	val \|= GENCONF_CTRL0_PORT1_RGMII_MII;	1236	val \|= GENCONF_CTRL0_PORT1_RGMII_MII;
1237	regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val);	1237	regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val);
@@ -2370,17 +2370,18 @@ static void mvpp2_rx_pkts_coal_set(struct mvpp2_port *port, · 1132 unmodified lines
2370	static void mvpp2_tx_pkts_coal_set(struct mvpp2_port *port,	2370	static void mvpp2_tx_pkts_coal_set(struct mvpp2_port *port,
2371	struct mvpp2_tx_queue *txq)	2371	struct mvpp2_tx_queue *txq)
2372	{	2372	{
2373	unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu());	2373	unsigned int thread;
2374	u32 val;	2374	u32 val;
2375		2375
2376	if (txq->done_pkts_coal > MVPP2_TXQ_THRESH_MASK)	2376	if (txq->done_pkts_coal > MVPP2_TXQ_THRESH_MASK)
2377	txq->done_pkts_coal = MVPP2_TXQ_THRESH_MASK;	2377	txq->done_pkts_coal = MVPP2_TXQ_THRESH_MASK;
2378		2378
2379	val = (txq->done_pkts_coal << MVPP2_TXQ_THRESH_OFFSET);	2379	val = (txq->done_pkts_coal << MVPP2_TXQ_THRESH_OFFSET);
2380	mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);	2380	/* PKT-coalescing registers are per-queue + per-thread */
2381	mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_THRESH_REG, val);	2381	for (thread = 0; thread < MVPP2_MAX_THREADS; thread++) {
2382		2382	mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
2383	put_cpu();	2383	mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_THRESH_REG, val);
		2384	}
2384	}	2385	}
2385		2386
2386	static u32 mvpp2_usec_to_cycles(u32 usec, unsigned long clk_hz)	2387	static u32 mvpp2_usec_to_cycles(u32 usec, unsigned long clk_hz)
@@ -5487,7 +5488,7 @@ static int mvpp2_port_init(struct mvpp2_port *port) · 3100 unmodified lines
5487	struct mvpp2 *priv = port->priv;	5488	struct mvpp2 *priv = port->priv;
5488	struct mvpp2_txq_pcpu *txq_pcpu;	5489	struct mvpp2_txq_pcpu *txq_pcpu;
5489	unsigned int thread;	5490	unsigned int thread;
5490	int queue, err;	5491	int queue, err, val;
5491		5492
5492	/* Checks for hardware constraints */	5493	/* Checks for hardware constraints */
5493	if (port->first_rxq + port->nrxqs >	5494	if (port->first_rxq + port->nrxqs >
@@ -5501,6 +5502,18 @@ static int mvpp2_port_init(struct mvpp2_port *port) · 7 unmodified lines
5501	mvpp2_egress_disable(port);	5502	mvpp2_egress_disable(port);
5502	mvpp2_port_disable(port);	5503	mvpp2_port_disable(port);
5503		5504
		5505	if (mvpp2_is_xlg(port->phy_interface)) {
		5506	val = readl(port->base + MVPP22_XLG_CTRL0_REG);
		5507	val &= ~MVPP22_XLG_CTRL0_FORCE_LINK_PASS;
		5508	val \|= MVPP22_XLG_CTRL0_FORCE_LINK_DOWN;
		5509	writel(val, port->base + MVPP22_XLG_CTRL0_REG);
		5510	} else {
		5511	val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
		5512	val &= ~MVPP2_GMAC_FORCE_LINK_PASS;
		5513	val \|= MVPP2_GMAC_FORCE_LINK_DOWN;
		5514	writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
		5515	}
		5516
5504	port->tx_time_coal = MVPP2_TXDONE_COAL_USEC;	5517	port->tx_time_coal = MVPP2_TXDONE_COAL_USEC;
5505		5518
5506	port->txqs = devm_kcalloc(dev, port->ntxqs, sizeof(*port->txqs),	5519	port->txqs = devm_kcalloc(dev, port->ntxqs, sizeof(*port->txqs),
@@ -5869,8 +5882,6 @@ static void mvpp2_phylink_validate(struct phylink_config *config, · 362 unmodified lines
5869		5882
5870	phylink_set(mask, Autoneg);	5883	phylink_set(mask, Autoneg);
5871	phylink_set_port_modes(mask);	5884	phylink_set_port_modes(mask);
5872	phylink_set(mask, Pause);
5873	phylink_set(mask, Asym_Pause);
5874		5885
5875	switch (state->interface) {	5886	switch (state->interface) {
5876	case PHY_INTERFACE_MODE_10GBASER:	5887	case PHY_INTERFACE_MODE_10GBASER:

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c+36−2

@@ -405,6 +405,38 @@ static int mvpp2_prs_tcam_first_free(struct mvpp2 *priv, unsigned char start, · 404 unmodified lines
405	return -EINVAL;	405	return -EINVAL;
406	}	406	}
407		407
		408	/* Drop flow control pause frames */
		409	static void mvpp2_prs_drop_fc(struct mvpp2 *priv)
		410	{
		411	unsigned char da[ETH_ALEN] = { 0x01, 0x80, 0xC2, 0x00, 0x00, 0x01 };
		412	struct mvpp2_prs_entry pe;
		413	unsigned int len;
		414
		415	memset(&pe, 0, sizeof(pe));
		416
		417	/* For all ports - drop flow control frames */
		418	pe.index = MVPP2_PE_FC_DROP;
		419	mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
		420
		421	/* Set match on DA */
		422	len = ETH_ALEN;
		423	while (len--)
		424	mvpp2_prs_tcam_data_byte_set(&pe, len, da[len], 0xff);
		425
		426	mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
		427	MVPP2_PRS_RI_DROP_MASK);
		428
		429	mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
		430	mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
		431
		432	/* Mask all ports */
		433	mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
		434
		435	/* Update shadow table and hw entry */
		436	mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
		437	mvpp2_prs_hw_write(priv, &pe);
		438	}
		439
408	/* Enable/disable dropping all mac da's */	440	/* Enable/disable dropping all mac da's */
409	static void mvpp2_prs_mac_drop_all_set(struct mvpp2 *priv, int port, bool add)	441	static void mvpp2_prs_mac_drop_all_set(struct mvpp2 *priv, int port, bool add)
410	{	442	{
@@ -1162,6 +1194,7 @@ static void mvpp2_prs_mac_init(struct mvpp2 *priv) · 751 unmodified lines
1162	mvpp2_prs_hw_write(priv, &pe);	1194	mvpp2_prs_hw_write(priv, &pe);
1163		1195
1164	/* Create dummy entries for drop all and promiscuous modes */	1196	/* Create dummy entries for drop all and promiscuous modes */
		1197	mvpp2_prs_drop_fc(priv);
1165	mvpp2_prs_mac_drop_all_set(priv, 0, false);	1198	mvpp2_prs_mac_drop_all_set(priv, 0, false);
1166	mvpp2_prs_mac_promisc_set(priv, 0, MVPP2_PRS_L2_UNI_CAST, false);	1199	mvpp2_prs_mac_promisc_set(priv, 0, MVPP2_PRS_L2_UNI_CAST, false);
1167	mvpp2_prs_mac_promisc_set(priv, 0, MVPP2_PRS_L2_MULTI_CAST, false);	1200	mvpp2_prs_mac_promisc_set(priv, 0, MVPP2_PRS_L2_MULTI_CAST, false);
@@ -1647,8 +1680,9 @@ static int mvpp2_prs_pppoe_init(struct mvpp2 *priv) · 479 unmodified lines
1647	mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);	1680	mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);
1648	mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6,	1681	mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6,
1649	MVPP2_PRS_RI_L3_PROTO_MASK);	1682	MVPP2_PRS_RI_L3_PROTO_MASK);
1650	/* Skip eth_type + 4 bytes of IPv6 header */	1683	/* Jump to DIP of IPV6 header */
1651	mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4,	1684	mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 +
		1685	MVPP2_MAX_L3_ADDR_SIZE,
1652	MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);	1686	MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
1653	/* Set L3 offset */	1687	/* Set L3 offset */
1654	mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,	1688	mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,

drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.h+1−1

@@ -129,7 +129,7 @@ · 128 unmodified lines
129	#define MVPP2_PE_VID_EDSA_FLTR_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 7)	129	#define MVPP2_PE_VID_EDSA_FLTR_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 7)
130	#define MVPP2_PE_VLAN_DBL (MVPP2_PRS_TCAM_SRAM_SIZE - 6)	130	#define MVPP2_PE_VLAN_DBL (MVPP2_PRS_TCAM_SRAM_SIZE - 6)
131	#define MVPP2_PE_VLAN_NONE (MVPP2_PRS_TCAM_SRAM_SIZE - 5)	131	#define MVPP2_PE_VLAN_NONE (MVPP2_PRS_TCAM_SRAM_SIZE - 5)
132	/* reserved */	132	#define MVPP2_PE_FC_DROP (MVPP2_PRS_TCAM_SRAM_SIZE - 4)
133	#define MVPP2_PE_MAC_MC_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 3)	133	#define MVPP2_PE_MAC_MC_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 3)
134	#define MVPP2_PE_MAC_UC_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 2)	134	#define MVPP2_PE_MAC_UC_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 2)
135	#define MVPP2_PE_MAC_NON_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 1)	135	#define MVPP2_PE_MAC_NON_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 1)

drivers/net/ethernet/marvell/octeontx2/af/cgx.c+11−3

 		if (!lmac)
 			return -ENOMEM;
 		lmac->name = kcalloc(1, sizeof("cgx_fwi_xxx_yyy"), GFP_KERNEL);
-		if (!lmac->name)
+		if (!lmac->name) {
-			return -ENOMEM;
+			err = -ENOMEM;
+			goto err_lmac_free;
+		}
 		sprintf(lmac->name, "cgx_fwi_%d_%d", cgx->cgx_id, i);
 		lmac->lmac_id = i;
 		lmac->cgx = cgx;
 						 CGX_LMAC_FWI + i * 9),
 				   cgx_fwi_event_handler, 0, lmac->name, lmac);
 		if (err)
-			return err;
+			goto err_irq;
 		/* Enable interrupt */
 		cgx_write(cgx, lmac->lmac_id, CGXX_CMRX_INT_ENA_W1S,
 	}
 	return cgx_lmac_verify_fwi_version(cgx);
+err_irq:
+	kfree(lmac->name);
+err_lmac_free:
+	kfree(lmac);
+	return err;
 }
 static int cgx_lmac_exit(struct cgx *cgx)

drivers/net/ethernet/mellanox/mlx5/core/en/rep/tc.c+5−0

 	if (!reg_c0)
 		return true;
+	/* If reg_c0 is not equal to the default flow tag then skb->mark
+	 * is not supported and must be reset back to 0.
+	 */
+	skb->mark = 0;
 	priv = netdev_priv(skb->dev);
 	esw = priv->mdev->priv.eswitch;

drivers/net/ethernet/mellanox/mlx5/core/en/tc_ct.c+49−28

 	u16 zone;
 };
-struct mlx5_ct_shared_counter {
+struct mlx5_ct_counter {
 	struct mlx5_fc *counter;
 	refcount_t refcount;
+	bool is_shared;
 };
 struct mlx5_ct_entry {
 	struct rhash_head node;
 	struct rhash_head tuple_node;
 	struct rhash_head tuple_nat_node;
-	struct mlx5_ct_shared_counter *shared_counter;
+	struct mlx5_ct_counter *counter;
 	unsigned long cookie;
 	unsigned long restore_cookie;
 	struct mlx5_ct_tuple tuple;
 }
 static void
-mlx5_tc_ct_shared_counter_put(struct mlx5_tc_ct_priv *ct_priv, struct mlx5_ct_entry *entry)
+mlx5_tc_ct_counter_put(struct mlx5_tc_ct_priv *ct_priv, struct mlx5_ct_entry *entry)
 {
-	if (!refcount_dec_and_test(&entry->shared_counter->refcount))
+	if (entry->counter->is_shared &&
+	    !refcount_dec_and_test(&entry->counter->refcount))
 		return;
-	mlx5_fc_destroy(ct_priv->dev, entry->shared_counter->counter);
+	mlx5_fc_destroy(ct_priv->dev, entry->counter->counter);
-	kfree(entry->shared_counter);
+	kfree(entry->counter);
 }
 static void
 	attr->dest_ft = ct_priv->post_ct;
 	attr->ft = nat ? ct_priv->ct_nat : ct_priv->ct;
 	attr->outer_match_level = MLX5_MATCH_L4;
-	attr->counter = entry->shared_counter->counter;
+	attr->counter = entry->counter->counter;
 	attr->flags |= MLX5_ESW_ATTR_FLAG_NO_IN_PORT;
 	mlx5_tc_ct_set_tuple_match(netdev_priv(ct_priv->netdev), spec, flow_rule);
 	return err;
 }
-static struct mlx5_ct_shared_counter *
+static struct mlx5_ct_counter *
+mlx5_tc_ct_counter_create(struct mlx5_tc_ct_priv *ct_priv)
+{
+	struct mlx5_ct_counter *counter;
+	int ret;
+	counter = kzalloc(sizeof(*counter), GFP_KERNEL);
+	if (!counter)
+		return ERR_PTR(-ENOMEM);
+	counter->is_shared = false;
+	counter->counter = mlx5_fc_create(ct_priv->dev, true);
+	if (IS_ERR(counter->counter)) {
+		ct_dbg("Failed to create counter for ct entry");
+		ret = PTR_ERR(counter->counter);
+		kfree(counter);
+		return ERR_PTR(ret);
+	}
+	return counter;
+}
+static struct mlx5_ct_counter *
 mlx5_tc_ct_shared_counter_get(struct mlx5_tc_ct_priv *ct_priv,
 			      struct mlx5_ct_entry *entry)
 {
 	struct mlx5_ct_tuple rev_tuple = entry->tuple;
-	struct mlx5_ct_shared_counter *shared_counter;
+	struct mlx5_ct_counter *shared_counter;
-	struct mlx5_core_dev *dev = ct_priv->dev;
 	struct mlx5_ct_entry *rev_entry;
 	__be16 tmp_port;
 	int ret;
 	rev_entry = rhashtable_lookup_fast(&ct_priv->ct_tuples_ht, &rev_tuple,
 					   tuples_ht_params);
 	if (rev_entry) {
-		if (refcount_inc_not_zero(&rev_entry->shared_counter->refcount)) {
+		if (refcount_inc_not_zero(&rev_entry->counter->refcount)) {
 			mutex_unlock(&ct_priv->shared_counter_lock);
-			return rev_entry->shared_counter;
+			return rev_entry->counter;
 		}
 	}
 	mutex_unlock(&ct_priv->shared_counter_lock);
-	shared_counter = kzalloc(sizeof(*shared_counter), GFP_KERNEL);
+	shared_counter = mlx5_tc_ct_counter_create(ct_priv);
-	if (!shared_counter)
+	if (IS_ERR(shared_counter)) {
-		return ERR_PTR(-ENOMEM);
+		ret = PTR_ERR(shared_counter);
-	shared_counter->counter = mlx5_fc_create(dev, true);
-	if (IS_ERR(shared_counter->counter)) {
-		ct_dbg("Failed to create counter for ct entry");
-		ret = PTR_ERR(shared_counter->counter);
-		kfree(shared_counter);
 		return ERR_PTR(ret);
 	}
+	shared_counter->is_shared = true;
 	refcount_set(&shared_counter->refcount, 1);
 	return shared_counter;
 }
 {
 	int err;
-	entry->shared_counter = mlx5_tc_ct_shared_counter_get(ct_priv, entry);
+	if (nf_ct_acct_enabled(dev_net(ct_priv->netdev)))
-	if (IS_ERR(entry->shared_counter)) {
+		entry->counter = mlx5_tc_ct_counter_create(ct_priv);
-		err = PTR_ERR(entry->shared_counter);
+	else
-		ct_dbg("Failed to create counter for ct entry");
+		entry->counter = mlx5_tc_ct_shared_counter_get(ct_priv, entry);
+	if (IS_ERR(entry->counter)) {
+		err = PTR_ERR(entry->counter);
 		return err;
 	}
 err_nat:
 	mlx5_tc_ct_entry_del_rule(ct_priv, entry, false);
 err_orig:
-	mlx5_tc_ct_shared_counter_put(ct_priv, entry);
+	mlx5_tc_ct_counter_put(ct_priv, entry);
 	return err;
 }
 	rhashtable_remove_fast(&ct_priv->ct_tuples_ht, &entry->tuple_node,
 			       tuples_ht_params);
 	mutex_unlock(&ct_priv->shared_counter_lock);
-	mlx5_tc_ct_shared_counter_put(ct_priv, entry);
+	mlx5_tc_ct_counter_put(ct_priv, entry);
 }
 	if (!entry)
 		return -ENOENT;
-	mlx5_fc_query_cached(entry->shared_counter->counter, &bytes, &packets, &lastuse);
+	mlx5_fc_query_cached(entry->counter->counter, &bytes, &packets, &lastuse);
 	flow_stats_update(&f->stats, bytes, packets, 0, lastuse,
 			  FLOW_ACTION_HW_STATS_DELAYED);

drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h+9−0

@@ -371,6 +371,15 @@ struct mlx5e_swp_spec { · 370 unmodified lines
371	u8 tun_l4_proto;	371	u8 tun_l4_proto;
372	};	372	};
373		373
		374	static inline void mlx5e_eseg_swp_offsets_add_vlan(struct mlx5_wqe_eth_seg *eseg)
		375	{
		376	/* SWP offsets are in 2-bytes words */
		377	eseg->swp_outer_l3_offset += VLAN_HLEN / 2;
		378	eseg->swp_outer_l4_offset += VLAN_HLEN / 2;
		379	eseg->swp_inner_l3_offset += VLAN_HLEN / 2;
		380	eseg->swp_inner_l4_offset += VLAN_HLEN / 2;
		381	}
		382
374	static inline void	383	static inline void
375	mlx5e_set_eseg_swp(struct sk_buff skb, struct mlx5_wqe_eth_seg eseg,	384	mlx5e_set_eseg_swp(struct sk_buff skb, struct mlx5_wqe_eth_seg eseg,
376	struct mlx5e_swp_spec *swp_spec)	385	struct mlx5e_swp_spec *swp_spec)

drivers/net/ethernet/mellanox/mlx5/core/en_accel/en_accel.h+5−3

 }
 static inline void
-mlx5e_tx_tunnel_accel(struct sk_buff *skb, struct mlx5_wqe_eth_seg *eseg)
+mlx5e_tx_tunnel_accel(struct sk_buff *skb, struct mlx5_wqe_eth_seg *eseg, u16 ihs)
 {
 	struct mlx5e_swp_spec swp_spec = {};
 	unsigned int offset = 0;
 	}
 	mlx5e_set_eseg_swp(skb, eseg, &swp_spec);
+	if (skb_vlan_tag_present(skb) &&  ihs)
+		mlx5e_eseg_swp_offsets_add_vlan(eseg);
 }
 #else
 static inline bool mlx5e_accel_tx_eseg(struct mlx5e_priv *priv,
 				       struct sk_buff *skb,
-				       struct mlx5_wqe_eth_seg *eseg)
+				       struct mlx5_wqe_eth_seg *eseg, u16 ihs)
 {
 #ifdef CONFIG_MLX5_EN_IPSEC
 	if (xfrm_offload(skb))
 #if IS_ENABLED(CONFIG_GENEVE)
 	if (skb->encapsulation)
-		mlx5e_tx_tunnel_accel(skb, eseg);
+		mlx5e_tx_tunnel_accel(skb, eseg, ihs);
 #endif
 	return true;

drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c+18−6

 	return mlx5e_ethtool_get_link_ksettings(priv, link_ksettings);
 }
+static int mlx5e_speed_validate(struct net_device *netdev, bool ext,
+				const unsigned long link_modes, u8 autoneg)
+{
+	/* Extended link-mode has no speed limitations. */
+	if (ext)
+		return 0;
+	if ((link_modes & MLX5E_PROT_MASK(MLX5E_56GBASE_R4)) &&
+	    autoneg != AUTONEG_ENABLE) {
+		netdev_err(netdev, "%s: 56G link speed requires autoneg enabled\n",
+			   __func__);
+		return -EINVAL;
+	}
+	return 0;
+}
 static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes)
 {
 	u32 i, ptys_modes = 0;
 	link_modes = autoneg == AUTONEG_ENABLE ? ethtool2ptys_adver_func(adver) :
 		mlx5e_port_speed2linkmodes(mdev, speed, !ext);
-	if ((link_modes & MLX5E_PROT_MASK(MLX5E_56GBASE_R4)) &&
+	err = mlx5e_speed_validate(priv->netdev, ext, link_modes, autoneg);
-	    autoneg != AUTONEG_ENABLE) {
+	if (err)
-		netdev_err(priv->netdev, "%s: 56G link speed requires autoneg enabled\n",
-			   __func__);
-		err = -EINVAL;
 		goto out;
-	}
 	link_modes = link_modes & eproto.cap;
 	if (!link_modes) {

drivers/net/ethernet/mellanox/mlx5/core/en_fs.c+3−0

 	in = kvzalloc(inlen, GFP_KERNEL);
 	if (!in) {
 		kfree(ft->g);
+		ft->g = NULL;
 		return -ENOMEM;
 	}
 	in = kvzalloc(inlen, GFP_KERNEL);
 	if (!in) {
 		kfree(ft->g);
+		ft->g = NULL;
 		return -ENOMEM;
 	}
 	ft->g[ft->num_groups] = NULL;
 	mlx5e_destroy_groups(ft);
 	kvfree(in);
+	kfree(ft->g);
 	return err;
 }

drivers/net/ethernet/mellanox/mlx5/core/en_main.c+2−1

@@ -3161,7 +3161,8 @@ static void mlx5e_modify_admin_state(struct mlx5_core_dev *mdev, · 3160 unmodified lines
3161		3161
3162	mlx5_set_port_admin_status(mdev, state);	3162	mlx5_set_port_admin_status(mdev, state);
3163		3163
3164	if (mlx5_eswitch_mode(mdev) != MLX5_ESWITCH_LEGACY)	3164	if (mlx5_eswitch_mode(mdev) == MLX5_ESWITCH_OFFLOADS \|\|
		3165	!MLX5_CAP_GEN(mdev, uplink_follow))
3165	return;	3166	return;
3166		3167
3167	if (state == MLX5_PORT_UP)	3168	if (state == MLX5_PORT_UP)

drivers/net/ethernet/mellanox/mlx5/core/en_tx.c+5−4

 static bool mlx5e_txwqe_build_eseg(struct mlx5e_priv *priv, struct mlx5e_txqsq *sq,
 				   struct sk_buff *skb, struct mlx5e_accel_tx_state *accel,
-				   struct mlx5_wqe_eth_seg *eseg)
+				   struct mlx5_wqe_eth_seg *eseg, u16 ihs)
 {
-	if (unlikely(!mlx5e_accel_tx_eseg(priv, skb, eseg)))
+	if (unlikely(!mlx5e_accel_tx_eseg(priv, skb, eseg, ihs)))
 		return false;
 	mlx5e_txwqe_build_eseg_csum(sq, skb, accel, eseg);
 		if (mlx5e_tx_skb_supports_mpwqe(skb, &attr)) {
 			struct mlx5_wqe_eth_seg eseg = {};
-			if (unlikely(!mlx5e_txwqe_build_eseg(priv, sq, skb, &accel, &eseg)))
+			if (unlikely(!mlx5e_txwqe_build_eseg(priv, sq, skb, &accel, &eseg,
+							     attr.ihs)))
 				return NETDEV_TX_OK;
 			mlx5e_sq_xmit_mpwqe(sq, skb, &eseg, netdev_xmit_more());
 	/* May update the WQE, but may not post other WQEs. */
 	mlx5e_accel_tx_finish(sq, wqe, &accel,
 			      (struct mlx5_wqe_inline_seg *)(wqe->data + wqe_attr.ds_cnt_inl));
-	if (unlikely(!mlx5e_txwqe_build_eseg(priv, sq, skb, &accel, &wqe->eth)))
+	if (unlikely(!mlx5e_txwqe_build_eseg(priv, sq, skb, &accel, &wqe->eth, attr.ihs)))
 		return NETDEV_TX_OK;
 	mlx5e_sq_xmit_wqe(sq, skb, &attr, &wqe_attr, wqe, pi, netdev_xmit_more());

drivers/net/ethernet/mellanox/mlx5/core/esw/acl/egress_lgcy.c+13−14

@@ -95,22 +95,21 @@ int esw_acl_egress_lgcy_setup(struct mlx5_eswitch *esw, · 94 unmodified lines
95	return 0;	95	return 0;
96	}	96	}
97		97
98	if (!IS_ERR_OR_NULL(vport->egress.acl))	98	if (!vport->egress.acl) {
99	return 0;	99	vport->egress.acl = esw_acl_table_create(esw, vport->vport,
100		100	MLX5_FLOW_NAMESPACE_ESW_EGRESS,
101	vport->egress.acl = esw_acl_table_create(esw, vport->vport,	101	table_size);
102	MLX5_FLOW_NAMESPACE_ESW_EGRESS,	102	if (IS_ERR(vport->egress.acl)) {
103	table_size);	103	err = PTR_ERR(vport->egress.acl);
104	if (IS_ERR(vport->egress.acl)) {	104	vport->egress.acl = NULL;
105	err = PTR_ERR(vport->egress.acl);	105	goto out;
106	vport->egress.acl = NULL;	106	}
107	goto out;	107
		108	err = esw_acl_egress_lgcy_groups_create(esw, vport);
		109	if (err)
		110	goto out;
108	}	111	}
109		112
110	err = esw_acl_egress_lgcy_groups_create(esw, vport);
111	if (err)
112	goto out;
113
114	esw_debug(esw->dev,	113	esw_debug(esw->dev,
115	"vport[%d] configure egress rules, vlan(%d) qos(%d)\n",	114	"vport[%d] configure egress rules, vlan(%d) qos(%d)\n",
116	vport->vport, vport->info.vlan, vport->info.qos);	115	vport->vport, vport->info.vlan, vport->info.qos);

drivers/net/ethernet/mellanox/mlx5/core/lag.c+5−6

 	struct mlx5_core_dev *tmp_dev;
 	int i, err;
-	if (!MLX5_CAP_GEN(dev, vport_group_manager))
+	if (!MLX5_CAP_GEN(dev, vport_group_manager) ||
+	    !MLX5_CAP_GEN(dev, lag_master) ||
+	    MLX5_CAP_GEN(dev, num_lag_ports) != MLX5_MAX_PORTS)
 		return;
 	tmp_dev = mlx5_get_next_phys_dev(dev);
 	if (mlx5_lag_dev_add_pf(ldev, dev, netdev) < 0)
 		return;
-	for (i = 0; i < MLX5_MAX_PORTS; i++) {
+	for (i = 0; i < MLX5_MAX_PORTS; i++)
-		tmp_dev = ldev->pf[i].dev;
+		if (!ldev->pf[i].dev)
-		if (!tmp_dev || !MLX5_CAP_GEN(tmp_dev, lag_master) ||
-		    MLX5_CAP_GEN(tmp_dev, num_lag_ports) != MLX5_MAX_PORTS)
 			break;
-	}
 	if (i >= MLX5_MAX_PORTS)
 		ldev->flags |= MLX5_LAG_FLAG_READY;

drivers/net/ethernet/mellanox/mlx5/core/main.c+5−2

 			 MLX5_COREDEV_VF : MLX5_COREDEV_PF;
 	dev->priv.adev_idx = mlx5_adev_idx_alloc();
-	if (dev->priv.adev_idx < 0)
+	if (dev->priv.adev_idx < 0) {
-		return dev->priv.adev_idx;
+		err = dev->priv.adev_idx;
+		goto adev_init_err;
+	}
 	err = mlx5_mdev_init(dev, prof_sel);
 	if (err)
 	mlx5_mdev_uninit(dev);
 mdev_init_err:
 	mlx5_adev_idx_free(dev->priv.adev_idx);
+adev_init_err:
 	mlx5_devlink_free(devlink);
 	return err;

drivers/net/ethernet/mellanox/mlx5/core/rdma.c+1−1

@@ -116,7 +116,7 @@ free: · 115 unmodified lines
116	static void mlx5_rdma_del_roce_addr(struct mlx5_core_dev *dev)	116	static void mlx5_rdma_del_roce_addr(struct mlx5_core_dev *dev)
117	{	117	{
118	mlx5_core_roce_gid_set(dev, 0, 0, 0,	118	mlx5_core_roce_gid_set(dev, 0, 0, 0,
119	NULL, NULL, false, 0, 0);	119	NULL, NULL, false, 0, 1);
120	}	120	}
121		121
122	static void mlx5_rdma_make_default_gid(struct mlx5_core_dev dev, union ib_gid gid)	122	static void mlx5_rdma_make_default_gid(struct mlx5_core_dev dev, union ib_gid gid)

drivers/net/ethernet/mellanox/mlxsw/core_thermal.c+8−5

 #define MLXSW_THERMAL_ASIC_TEMP_NORM	75000	/* 75C */
 #define MLXSW_THERMAL_ASIC_TEMP_HIGH	85000	/* 85C */
 #define MLXSW_THERMAL_ASIC_TEMP_HOT	105000	/* 105C */
-#define MLXSW_THERMAL_ASIC_TEMP_CRIT	110000	/* 110C */
+#define MLXSW_THERMAL_ASIC_TEMP_CRIT	140000	/* 140C */
 #define MLXSW_THERMAL_HYSTERESIS_TEMP	5000	/* 5C */
 #define MLXSW_THERMAL_MODULE_TEMP_SHIFT	(MLXSW_THERMAL_HYSTERESIS_TEMP * 2)
 #define MLXSW_THERMAL_ZONE_MAX_NAME	16
 	if (err)
 		return err;
+	if (crit_temp > emerg_temp) {
+		dev_warn(dev, "%s : Critical threshold %d is above emergency threshold %d\n",
+			 tz->tzdev->type, crit_temp, emerg_temp);
+		return 0;
+	}
 	/* According to the system thermal requirements, the thermal zones are
 	 * defined with four trip points. The critical and emergency
 	 * temperature thresholds, provided by QSFP module are set as "active"
 		tz->trips[MLXSW_THERMAL_TEMP_TRIP_NORM].temp = crit_temp;
 	tz->trips[MLXSW_THERMAL_TEMP_TRIP_HIGH].temp = crit_temp;
 	tz->trips[MLXSW_THERMAL_TEMP_TRIP_HOT].temp = emerg_temp;
-	if (emerg_temp > crit_temp)
+	tz->trips[MLXSW_THERMAL_TEMP_TRIP_CRIT].temp = emerg_temp +
-		tz->trips[MLXSW_THERMAL_TEMP_TRIP_CRIT].temp = emerg_temp +
 					MLXSW_THERMAL_MODULE_TEMP_SHIFT;
-	else
-		tz->trips[MLXSW_THERMAL_TEMP_TRIP_CRIT].temp = emerg_temp;
 	return 0;
 }

drivers/net/ethernet/natsemi/macsonic.c+10−2

 	err = register_netdev(dev);
 	if (err)
-		goto out;
+		goto undo_probe;
 	return 0;
+undo_probe:
+	dma_free_coherent(lp->device,
+			  SIZEOF_SONIC_DESC * SONIC_BUS_SCALE(lp->dma_bitmode),
+			  lp->descriptors, lp->descriptors_laddr);
 out:
 	free_netdev(dev);
 	err = register_netdev(ndev);
 	if (err)
-		goto out;
+		goto undo_probe;
 	nubus_set_drvdata(board, ndev);
 	return 0;
+undo_probe:
+	dma_free_coherent(lp->device,
+			  SIZEOF_SONIC_DESC * SONIC_BUS_SCALE(lp->dma_bitmode),
+			  lp->descriptors, lp->descriptors_laddr);
 out:
 	free_netdev(ndev);
 	return err;

drivers/net/ethernet/natsemi/xtsonic.c+5−2

 	sonic_msg_init(dev);
 	if ((err = register_netdev(dev)))
-		goto out1;
+		goto undo_probe1;
 	return 0;
-out1:
+undo_probe1:
+	dma_free_coherent(lp->device,
+			  SIZEOF_SONIC_DESC * SONIC_BUS_SCALE(lp->dma_bitmode),
+			  lp->descriptors, lp->descriptors_laddr);
 	release_region(dev->base_addr, SONIC_MEM_SIZE);
 out:
 	free_netdev(dev);

drivers/net/ethernet/pensando/ionic/ionic_txrx.c+1−1

@@ -337,7 +337,7 @@ void ionic_rx_fill(struct ionic_queue *q) · 336 unmodified lines
337	unsigned int i, j;	337	unsigned int i, j;
338	unsigned int len;	338	unsigned int len;
339		339
340	len = netdev->mtu + ETH_HLEN;	340	len = netdev->mtu + ETH_HLEN + VLAN_HLEN;
341	nfrags = round_up(len, PAGE_SIZE) / PAGE_SIZE;	341	nfrags = round_up(len, PAGE_SIZE) / PAGE_SIZE;
342		342
343	for (i = ionic_q_space_avail(q); i; i--) {	343	for (i = ionic_q_space_avail(q); i; i--) {

drivers/net/ethernet/qlogic/Kconfig+1−0

@@ -78,6 +78,7 @@ config QED · 77 unmodified lines
78	depends on PCI	78	depends on PCI
79	select ZLIB_INFLATE	79	select ZLIB_INFLATE
80	select CRC8	80	select CRC8
		81	select CRC32
81	select NET_DEVLINK	82	select NET_DEVLINK
82	help	83	help
83	This enables the support for Marvell FastLinQ adapters family.	84	This enables the support for Marvell FastLinQ adapters family.

drivers/net/ethernet/qlogic/netxen/netxen_nic_main.c+1−6

 	.ndo_set_features = netxen_set_features,
 };
-static inline bool netxen_function_zero(struct pci_dev *pdev)
-{
-	return (PCI_FUNC(pdev->devfn) == 0) ? true : false;
-}
 static inline void netxen_set_interrupt_mode(struct netxen_adapter *adapter,
 					     u32 mode)
 {
 	netxen_initialize_interrupt_registers(adapter);
 	netxen_set_msix_bit(pdev, 0);
-	if (netxen_function_zero(pdev)) {
+	if (adapter->portnum == 0) {
 		if (!netxen_setup_msi_interrupts(adapter, num_msix))
 			netxen_set_interrupt_mode(adapter, NETXEN_MSI_MODE);
 		else

drivers/net/ethernet/qlogic/qede/qede_fp.c+5−0

 			      ntohs(udp_hdr(skb)->dest) != gnv_port))
 				return features & ~(NETIF_F_CSUM_MASK |
 						    NETIF_F_GSO_MASK);
+		} else if (l4_proto == IPPROTO_IPIP) {
+			/* IPIP tunnels are unknown to the device or at least unsupported natively,
+			 * offloads for them can't be done trivially, so disable them for such skb.
+			 */
+			return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
 		}
 	}

drivers/net/ethernet/realtek/r8169_main.c+4−2

 	}
 	switch (tp->mac_version) {
-	case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
+	case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26:
+	case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_33:
 	case RTL_GIGA_MAC_VER_37:
 	case RTL_GIGA_MAC_VER_39:
 	case RTL_GIGA_MAC_VER_43:
 static void rtl_pll_power_up(struct rtl8169_private *tp)
 {
 	switch (tp->mac_version) {
-	case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
+	case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26:
+	case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_33:
 	case RTL_GIGA_MAC_VER_37:
 	case RTL_GIGA_MAC_VER_39:
 	case RTL_GIGA_MAC_VER_43:

drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c+4−0

 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G_ID		0x4bb0
 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G_ID		0x4bb1
 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5_ID	0x4bb2
+#define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_0_ID		0x43ac
+#define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_1_ID		0x43a2
 #define PCI_DEVICE_ID_INTEL_TGL_SGMII1G_ID		0xa0ac
 static const struct pci_device_id intel_eth_pci_id_table[] = {
 	{ PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII1G_ID, &ehl_pse1_sgmii1g_info) },
 	{ PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII2G5_ID, &ehl_pse1_sgmii1g_info) },
 	{ PCI_DEVICE_DATA(INTEL, TGL_SGMII1G_ID, &tgl_sgmii1g_info) },
+	{ PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_0_ID, &tgl_sgmii1g_info) },
+	{ PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_1_ID, &tgl_sgmii1g_info) },
 	{}
 };
 MODULE_DEVICE_TABLE(pci, intel_eth_pci_id_table);

drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c+1−1

@@ -135,7 +135,7 @@ static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac) · 134 unmodified lines
135	struct device *dev = dwmac->dev;	135	struct device *dev = dwmac->dev;
136	static const struct clk_parent_data mux_parents[] = {	136	static const struct clk_parent_data mux_parents[] = {
137	{ .fw_name = "clkin0", },	137	{ .fw_name = "clkin0", },
138	{ .fw_name = "clkin1", },	138	{ .index = -1, },
139	};	139	};
140	static const struct clk_div_table div_table[] = {	140	static const struct clk_div_table div_table[] = {
141	{ .div = 2, .val = 2, },	141	{ .div = 2, .val = 2, },

drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c+82−47

@@ -64,6 +64,7 @@ struct emac_variant { · 63 unmodified lines
64	* @variant: reference to the current board variant	64	* @variant: reference to the current board variant
65	* @regmap: regmap for using the syscon	65	* @regmap: regmap for using the syscon
66	* @internal_phy_powered: Does the internal PHY is enabled	66	* @internal_phy_powered: Does the internal PHY is enabled
		67	* @use_internal_phy: Is the internal PHY selected for use
67	* @mux_handle: Internal pointer used by mdio-mux lib	68	* @mux_handle: Internal pointer used by mdio-mux lib
68	*/	69	*/
69	struct sunxi_priv_data {	70	struct sunxi_priv_data {
@@ -74,6 +75,7 @@ struct sunxi_priv_data { · 4 unmodified lines
74	const struct emac_variant *variant;	75	const struct emac_variant *variant;
75	struct regmap_field *regmap_field;	76	struct regmap_field *regmap_field;
76	bool internal_phy_powered;	77	bool internal_phy_powered;
		78	bool use_internal_phy;
77	void *mux_handle;	79	void *mux_handle;
78	};	80	};
79		81
@@ -539,8 +541,11 @@ static const struct stmmac_dma_ops sun8i_dwmac_dma_ops = { · 459 unmodified lines
539	.dma_interrupt = sun8i_dwmac_dma_interrupt,	541	.dma_interrupt = sun8i_dwmac_dma_interrupt,
540	};	542	};
541		543
		544	static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv);
		545
542	static int sun8i_dwmac_init(struct platform_device pdev, void priv)	546	static int sun8i_dwmac_init(struct platform_device pdev, void priv)
543	{	547	{
		548	struct net_device *ndev = platform_get_drvdata(pdev);
544	struct sunxi_priv_data *gmac = priv;	549	struct sunxi_priv_data *gmac = priv;
545	int ret;	550	int ret;
546		551
@@ -554,13 +559,25 @@ static int sun8i_dwmac_init(struct platform_device pdev, void priv) · 7 unmodified lines
554		559
555	ret = clk_prepare_enable(gmac->tx_clk);	560	ret = clk_prepare_enable(gmac->tx_clk);
556	if (ret) {	561	if (ret) {
557	if (gmac->regulator)
558	regulator_disable(gmac->regulator);
559	dev_err(&pdev->dev, "Could not enable AHB clock\n");	562	dev_err(&pdev->dev, "Could not enable AHB clock\n");
560	return ret;	563	goto err_disable_regulator;
		564	}
		565
		566	if (gmac->use_internal_phy) {
		567	ret = sun8i_dwmac_power_internal_phy(netdev_priv(ndev));
		568	if (ret)
		569	goto err_disable_clk;
561	}	570	}
562		571
563	return 0;	572	return 0;
		573
		574	err_disable_clk:
		575	clk_disable_unprepare(gmac->tx_clk);
		576	err_disable_regulator:
		577	if (gmac->regulator)
		578	regulator_disable(gmac->regulator);
		579
		580	return ret;
564	}	581	}
565		582
566	static void sun8i_dwmac_core_init(struct mac_device_info *hw,	583	static void sun8i_dwmac_core_init(struct mac_device_info *hw,
@@ -831,7 +848,6 @@ static int mdio_mux_syscon_switch_fn(int current_child, int desired_child, · 264 unmodified lines
831	struct sunxi_priv_data *gmac = priv->plat->bsp_priv;	848	struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
832	u32 reg, val;	849	u32 reg, val;
833	int ret = 0;	850	int ret = 0;
834	bool need_power_ephy = false;
835		851
836	if (current_child ^ desired_child) {	852	if (current_child ^ desired_child) {
837	regmap_field_read(gmac->regmap_field, &reg);	853	regmap_field_read(gmac->regmap_field, &reg);
@@ -839,13 +855,12 @@ static int mdio_mux_syscon_switch_fn(int current_child, int desired_child, · 1 unmodified line
839	case DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID:	855	case DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID:
840	dev_info(priv->device, "Switch mux to internal PHY");	856	dev_info(priv->device, "Switch mux to internal PHY");
841	val = (reg & ~H3_EPHY_MUX_MASK) \| H3_EPHY_SELECT;	857	val = (reg & ~H3_EPHY_MUX_MASK) \| H3_EPHY_SELECT;
842		858	gmac->use_internal_phy = true;
843	need_power_ephy = true;
844	break;	859	break;
845	case DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID:	860	case DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID:
846	dev_info(priv->device, "Switch mux to external PHY");	861	dev_info(priv->device, "Switch mux to external PHY");
847	val = (reg & ~H3_EPHY_MUX_MASK) \| H3_EPHY_SHUTDOWN;	862	val = (reg & ~H3_EPHY_MUX_MASK) \| H3_EPHY_SHUTDOWN;
848	need_power_ephy = false;	863	gmac->use_internal_phy = false;
849	break;	864	break;
850	default:	865	default:
851	dev_err(priv->device, "Invalid child ID %x\n",	866	dev_err(priv->device, "Invalid child ID %x\n",
@@ -853,7 +868,7 @@ static int mdio_mux_syscon_switch_fn(int current_child, int desired_child, · 1 unmodified line
853	return -EINVAL;	868	return -EINVAL;
854	}	869	}
855	regmap_field_write(gmac->regmap_field, val);	870	regmap_field_write(gmac->regmap_field, val);
856	if (need_power_ephy) {	871	if (gmac->use_internal_phy) {
857	ret = sun8i_dwmac_power_internal_phy(priv);	872	ret = sun8i_dwmac_power_internal_phy(priv);
858	if (ret)	873	if (ret)
859	return ret;	874	return ret;
@@ -883,22 +898,23 @@ static int sun8i_dwmac_register_mdio_mux(struct stmmac_priv *priv) · 23 unmodified lines
883	return ret;	898	return ret;
884	}	899	}
885		900
886	static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv)	901	static int sun8i_dwmac_set_syscon(struct device *dev,
		902	struct plat_stmmacenet_data *plat)
887	{	903	{
888	struct sunxi_priv_data *gmac = priv->plat->bsp_priv;	904	struct sunxi_priv_data *gmac = plat->bsp_priv;
889	struct device_node *node = priv->device->of_node;	905	struct device_node *node = dev->of_node;
890	int ret;	906	int ret;
891	u32 reg, val;	907	u32 reg, val;
892		908
893	ret = regmap_field_read(gmac->regmap_field, &val);	909	ret = regmap_field_read(gmac->regmap_field, &val);
894	if (ret) {	910	if (ret) {
895	dev_err(priv->device, "Fail to read from regmap field.\n");	911	dev_err(dev, "Fail to read from regmap field.\n");
896	return ret;	912	return ret;
897	}	913	}
898		914
899	reg = gmac->variant->default_syscon_value;	915	reg = gmac->variant->default_syscon_value;
900	if (reg != val)	916	if (reg != val)
901	dev_warn(priv->device,	917	dev_warn(dev,
902	"Current syscon value is not the default %x (expect %x)\n",	918	"Current syscon value is not the default %x (expect %x)\n",
903	val, reg);	919	val, reg);
904		920
@@ -911,9 +927,9 @@ static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv) · 6 unmodified lines
911	/* Force EPHY xtal frequency to 24MHz. */	927	/* Force EPHY xtal frequency to 24MHz. */
912	reg \|= H3_EPHY_CLK_SEL;	928	reg \|= H3_EPHY_CLK_SEL;
913		929
914	ret = of_mdio_parse_addr(priv->device, priv->plat->phy_node);	930	ret = of_mdio_parse_addr(dev, plat->phy_node);
915	if (ret < 0) {	931	if (ret < 0) {
916	dev_err(priv->device, "Could not parse MDIO addr\n");	932	dev_err(dev, "Could not parse MDIO addr\n");
917	return ret;	933	return ret;
918	}	934	}
919	/* of_mdio_parse_addr returns a valid (0 ~ 31) PHY	935	/* of_mdio_parse_addr returns a valid (0 ~ 31) PHY
@@ -929,17 +945,17 @@ static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv) · 9 unmodified lines
929		945
930	if (!of_property_read_u32(node, "allwinner,tx-delay-ps", &val)) {	946	if (!of_property_read_u32(node, "allwinner,tx-delay-ps", &val)) {
931	if (val % 100) {	947	if (val % 100) {
932	dev_err(priv->device, "tx-delay must be a multiple of 100\n");	948	dev_err(dev, "tx-delay must be a multiple of 100\n");
933	return -EINVAL;	949	return -EINVAL;
934	}	950	}
935	val /= 100;	951	val /= 100;
936	dev_dbg(priv->device, "set tx-delay to %x\n", val);	952	dev_dbg(dev, "set tx-delay to %x\n", val);
937	if (val <= gmac->variant->tx_delay_max) {	953	if (val <= gmac->variant->tx_delay_max) {
938	reg &= ~(gmac->variant->tx_delay_max <<	954	reg &= ~(gmac->variant->tx_delay_max <<
939	SYSCON_ETXDC_SHIFT);	955	SYSCON_ETXDC_SHIFT);
940	reg \|= (val << SYSCON_ETXDC_SHIFT);	956	reg \|= (val << SYSCON_ETXDC_SHIFT);
941	} else {	957	} else {
942	dev_err(priv->device, "Invalid TX clock delay: %d\n",	958	dev_err(dev, "Invalid TX clock delay: %d\n",
943	val);	959	val);
944	return -EINVAL;	960	return -EINVAL;
945	}	961	}
@@ -947,17 +963,17 @@ static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv) · 1 unmodified line
947		963
948	if (!of_property_read_u32(node, "allwinner,rx-delay-ps", &val)) {	964	if (!of_property_read_u32(node, "allwinner,rx-delay-ps", &val)) {
949	if (val % 100) {	965	if (val % 100) {
950	dev_err(priv->device, "rx-delay must be a multiple of 100\n");	966	dev_err(dev, "rx-delay must be a multiple of 100\n");
951	return -EINVAL;	967	return -EINVAL;
952	}	968	}
953	val /= 100;	969	val /= 100;
954	dev_dbg(priv->device, "set rx-delay to %x\n", val);	970	dev_dbg(dev, "set rx-delay to %x\n", val);
955	if (val <= gmac->variant->rx_delay_max) {	971	if (val <= gmac->variant->rx_delay_max) {
956	reg &= ~(gmac->variant->rx_delay_max <<	972	reg &= ~(gmac->variant->rx_delay_max <<
957	SYSCON_ERXDC_SHIFT);	973	SYSCON_ERXDC_SHIFT);
958	reg \|= (val << SYSCON_ERXDC_SHIFT);	974	reg \|= (val << SYSCON_ERXDC_SHIFT);
959	} else {	975	} else {
960	dev_err(priv->device, "Invalid RX clock delay: %d\n",	976	dev_err(dev, "Invalid RX clock delay: %d\n",
961	val);	977	val);
962	return -EINVAL;	978	return -EINVAL;
963	}	979	}
@@ -968,7 +984,7 @@ static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv) · 4 unmodified lines
968	if (gmac->variant->support_rmii)	984	if (gmac->variant->support_rmii)
969	reg &= ~SYSCON_RMII_EN;	985	reg &= ~SYSCON_RMII_EN;
970		986
971	switch (priv->plat->interface) {	987	switch (plat->interface) {
972	case PHY_INTERFACE_MODE_MII:	988	case PHY_INTERFACE_MODE_MII:
973	/* default */	989	/* default */
974	break;	990	break;
@@ -982,8 +998,8 @@ static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv) · 7 unmodified lines
982	reg \|= SYSCON_RMII_EN \| SYSCON_ETCS_EXT_GMII;	998	reg \|= SYSCON_RMII_EN \| SYSCON_ETCS_EXT_GMII;
983	break;	999	break;
984	default:	1000	default:
985	dev_err(priv->device, "Unsupported interface mode: %s",	1001	dev_err(dev, "Unsupported interface mode: %s",
986	phy_modes(priv->plat->interface));	1002	phy_modes(plat->interface));
987	return -EINVAL;	1003	return -EINVAL;
988	}	1004	}
989		1005
@@ -1004,17 +1020,10 @@ static void sun8i_dwmac_exit(struct platform_device pdev, void priv) · 14 unmodified lines
1004	struct sunxi_priv_data *gmac = priv;	1020	struct sunxi_priv_data *gmac = priv;
1005		1021
1006	if (gmac->variant->soc_has_internal_phy) {	1022	if (gmac->variant->soc_has_internal_phy) {
1007	/* sun8i_dwmac_exit could be called with mdiomux uninit */
1008	if (gmac->mux_handle)
1009	mdio_mux_uninit(gmac->mux_handle);
1010	if (gmac->internal_phy_powered)	1023	if (gmac->internal_phy_powered)
1011	sun8i_dwmac_unpower_internal_phy(gmac);	1024	sun8i_dwmac_unpower_internal_phy(gmac);
1012	}	1025	}
1013		1026
1014	sun8i_dwmac_unset_syscon(gmac);
1015
1016	reset_control_put(gmac->rst_ephy);
1017
1018	clk_disable_unprepare(gmac->tx_clk);	1027	clk_disable_unprepare(gmac->tx_clk);
1019		1028
1020	if (gmac->regulator)	1029	if (gmac->regulator)
@@ -1049,16 +1058,11 @@ static struct mac_device_info sun8i_dwmac_setup(void ppriv) · 28 unmodified lines
1049	{	1058	{
1050	struct mac_device_info *mac;	1059	struct mac_device_info *mac;
1051	struct stmmac_priv *priv = ppriv;	1060	struct stmmac_priv *priv = ppriv;
1052	int ret;
1053		1061
1054	mac = devm_kzalloc(priv->device, sizeof(*mac), GFP_KERNEL);	1062	mac = devm_kzalloc(priv->device, sizeof(*mac), GFP_KERNEL);
1055	if (!mac)	1063	if (!mac)
1056	return NULL;	1064	return NULL;
1057		1065
1058	ret = sun8i_dwmac_set_syscon(priv);
1059	if (ret)
1060	return NULL;
1061
1062	mac->pcsr = priv->ioaddr;	1066	mac->pcsr = priv->ioaddr;
1063	mac->mac = &sun8i_dwmac_ops;	1067	mac->mac = &sun8i_dwmac_ops;
1064	mac->dma = &sun8i_dwmac_dma_ops;	1068	mac->dma = &sun8i_dwmac_dma_ops;
@@ -1134,10 +1138,6 @@ static int sun8i_dwmac_probe(struct platform_device *pdev) · 69 unmodified lines
1134	if (ret)	1138	if (ret)
1135	return ret;	1139	return ret;
1136		1140
1137	plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
1138	if (IS_ERR(plat_dat))
1139	return PTR_ERR(plat_dat);
1140
1141	gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL);	1141	gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL);
1142	if (!gmac)	1142	if (!gmac)
1143	return -ENOMEM;	1143	return -ENOMEM;
@@ -1201,11 +1201,15 @@ static int sun8i_dwmac_probe(struct platform_device *pdev) · 57 unmodified lines
1201	ret = of_get_phy_mode(dev->of_node, &interface);	1201	ret = of_get_phy_mode(dev->of_node, &interface);
1202	if (ret)	1202	if (ret)
1203	return -EINVAL;	1203	return -EINVAL;
1204	plat_dat->interface = interface;	1204
		1205	plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
		1206	if (IS_ERR(plat_dat))
		1207	return PTR_ERR(plat_dat);
1205		1208
1206	/* platform data specifying hardware features and callbacks.	1209	/* platform data specifying hardware features and callbacks.
1207	* hardware features were copied from Allwinner drivers.	1210	* hardware features were copied from Allwinner drivers.
1208	*/	1211	*/
		1212	plat_dat->interface = interface;
1209	plat_dat->rx_coe = STMMAC_RX_COE_TYPE2;	1213	plat_dat->rx_coe = STMMAC_RX_COE_TYPE2;
1210	plat_dat->tx_coe = 1;	1214	plat_dat->tx_coe = 1;
1211	plat_dat->has_sun8i = true;	1215	plat_dat->has_sun8i = true;
@@ -1214,9 +1218,13 @@ static int sun8i_dwmac_probe(struct platform_device *pdev) · 2 unmodified lines
1214	plat_dat->exit = sun8i_dwmac_exit;	1218	plat_dat->exit = sun8i_dwmac_exit;
1215	plat_dat->setup = sun8i_dwmac_setup;	1219	plat_dat->setup = sun8i_dwmac_setup;
1216		1220
		1221	ret = sun8i_dwmac_set_syscon(&pdev->dev, plat_dat);
		1222	if (ret)
		1223	goto dwmac_deconfig;
		1224
1217	ret = sun8i_dwmac_init(pdev, plat_dat->bsp_priv);	1225	ret = sun8i_dwmac_init(pdev, plat_dat->bsp_priv);
1218	if (ret)	1226	if (ret)
1219	return ret;	1227	goto dwmac_syscon;
1220		1228
1221	ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);	1229	ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
1222	if (ret)	1230	if (ret)
@@ -1230,7 +1238,7 @@ static int sun8i_dwmac_probe(struct platform_device *pdev) · 7 unmodified lines
1230	if (gmac->variant->soc_has_internal_phy) {	1238	if (gmac->variant->soc_has_internal_phy) {
1231	ret = get_ephy_nodes(priv);	1239	ret = get_ephy_nodes(priv);
1232	if (ret)	1240	if (ret)
1233	goto dwmac_exit;	1241	goto dwmac_remove;
1234	ret = sun8i_dwmac_register_mdio_mux(priv);	1242	ret = sun8i_dwmac_register_mdio_mux(priv);
1235	if (ret) {	1243	if (ret) {
1236	dev_err(&pdev->dev, "Failed to register mux\n");	1244	dev_err(&pdev->dev, "Failed to register mux\n");
@@ -1239,15 +1247,42 @@ static int sun8i_dwmac_probe(struct platform_device *pdev) · 2 unmodified lines
1239	} else {	1247	} else {
1240	ret = sun8i_dwmac_reset(priv);	1248	ret = sun8i_dwmac_reset(priv);
1241	if (ret)	1249	if (ret)
1242	goto dwmac_exit;	1250	goto dwmac_remove;
1243	}	1251	}
1244		1252
1245	return ret;	1253	return ret;
1246	dwmac_mux:	1254	dwmac_mux:
1247	sun8i_dwmac_unset_syscon(gmac);	1255	reset_control_put(gmac->rst_ephy);
		1256	clk_put(gmac->ephy_clk);
		1257	dwmac_remove:
		1258	stmmac_dvr_remove(&pdev->dev);
1248	dwmac_exit:	1259	dwmac_exit:
		1260	sun8i_dwmac_exit(pdev, gmac);
		1261	dwmac_syscon:
		1262	sun8i_dwmac_unset_syscon(gmac);
		1263	dwmac_deconfig:
		1264	stmmac_remove_config_dt(pdev, plat_dat);
		1265
		1266	return ret;
		1267	}
		1268
		1269	static int sun8i_dwmac_remove(struct platform_device *pdev)
		1270	{
		1271	struct net_device *ndev = platform_get_drvdata(pdev);
		1272	struct stmmac_priv *priv = netdev_priv(ndev);
		1273	struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
		1274
		1275	if (gmac->variant->soc_has_internal_phy) {
		1276	mdio_mux_uninit(gmac->mux_handle);
		1277	sun8i_dwmac_unpower_internal_phy(gmac);
		1278	reset_control_put(gmac->rst_ephy);
		1279	clk_put(gmac->ephy_clk);
		1280	}
		1281
1249	stmmac_pltfr_remove(pdev);	1282	stmmac_pltfr_remove(pdev);
1250	return ret;	1283	sun8i_dwmac_unset_syscon(gmac);
		1284
		1285	return 0;
1251	}	1286	}
1252		1287
1253	static const struct of_device_id sun8i_dwmac_match[] = {	1288	static const struct of_device_id sun8i_dwmac_match[] = {
@@ -1269,7 +1304,7 @@ MODULE_DEVICE_TABLE(of, sun8i_dwmac_match); · 15 unmodified lines
1269		1304
1270	static struct platform_driver sun8i_dwmac_driver = {	1305	static struct platform_driver sun8i_dwmac_driver = {
1271	.probe = sun8i_dwmac_probe,	1306	.probe = sun8i_dwmac_probe,
1272	.remove = stmmac_pltfr_remove,	1307	.remove = sun8i_dwmac_remove,
1273	.driver = {	1308	.driver = {
1274	.name = "dwmac-sun8i",	1309	.name = "dwmac-sun8i",
1275	.pm = &stmmac_pltfr_pm_ops,	1310	.pm = &stmmac_pltfr_pm_ops,

drivers/net/ethernet/stmicro/stmmac/dwmac5.c+4−48

@@ -568,68 +568,24 @@ static int dwmac5_est_write(void __iomem *ioaddr, u32 reg, u32 val, bool gcl) · 567 unmodified lines
568	int dwmac5_est_configure(void __iomem ioaddr, struct stmmac_est cfg,	568	int dwmac5_est_configure(void __iomem ioaddr, struct stmmac_est cfg,
569	unsigned int ptp_rate)	569	unsigned int ptp_rate)
570	{	570	{
571	u32 speed, total_offset, offset, ctrl, ctr_low;
572	u32 extcfg = readl(ioaddr + GMAC_EXT_CONFIG);
573	u32 mac_cfg = readl(ioaddr + GMAC_CONFIG);
574	int i, ret = 0x0;	571	int i, ret = 0x0;
575	u64 total_ctr;	572	u32 ctrl;
576
577	if (extcfg & GMAC_CONFIG_EIPG_EN) {
578	offset = (extcfg & GMAC_CONFIG_EIPG) >> GMAC_CONFIG_EIPG_SHIFT;
579	offset = 104 + (offset * 8);
580	} else {
581	offset = (mac_cfg & GMAC_CONFIG_IPG) >> GMAC_CONFIG_IPG_SHIFT;
582	offset = 96 - (offset * 8);
583	}
584
585	speed = mac_cfg & (GMAC_CONFIG_PS \| GMAC_CONFIG_FES);
586	speed = speed >> GMAC_CONFIG_FES_SHIFT;
587
588	switch (speed) {
589	case 0x0:
590	offset = offset * 1000; /* 1G */
591	break;
592	case 0x1:
593	offset = offset * 400; /* 2.5G */
594	break;
595	case 0x2:
596	offset = offset * 100000; /* 10M */
597	break;
598	case 0x3:
599	offset = offset * 10000; /* 100M */
600	break;
601	default:
602	return -EINVAL;
603	}
604
605	offset = offset / 1000;
606		573
607	ret \|= dwmac5_est_write(ioaddr, BTR_LOW, cfg->btr[0], false);	574	ret \|= dwmac5_est_write(ioaddr, BTR_LOW, cfg->btr[0], false);
608	ret \|= dwmac5_est_write(ioaddr, BTR_HIGH, cfg->btr[1], false);	575	ret \|= dwmac5_est_write(ioaddr, BTR_HIGH, cfg->btr[1], false);
609	ret \|= dwmac5_est_write(ioaddr, TER, cfg->ter, false);	576	ret \|= dwmac5_est_write(ioaddr, TER, cfg->ter, false);
610	ret \|= dwmac5_est_write(ioaddr, LLR, cfg->gcl_size, false);	577	ret \|= dwmac5_est_write(ioaddr, LLR, cfg->gcl_size, false);
		578	ret \|= dwmac5_est_write(ioaddr, CTR_LOW, cfg->ctr[0], false);
		579	ret \|= dwmac5_est_write(ioaddr, CTR_HIGH, cfg->ctr[1], false);
611	if (ret)	580	if (ret)
612	return ret;	581	return ret;
613		582
614	total_offset = 0;
615	for (i = 0; i < cfg->gcl_size; i++) {	583	for (i = 0; i < cfg->gcl_size; i++) {
616	ret = dwmac5_est_write(ioaddr, i, cfg->gcl[i] + offset, true);	584	ret = dwmac5_est_write(ioaddr, i, cfg->gcl[i], true);
617	if (ret)	585	if (ret)
618	return ret;	586	return ret;
619
620	total_offset += offset;
621	}	587	}
622		588
623	total_ctr = cfg->ctr[0] + cfg->ctr[1] * 1000000000ULL;
624	total_ctr += total_offset;
625
626	ctr_low = do_div(total_ctr, 1000000000);
627
628	ret \|= dwmac5_est_write(ioaddr, CTR_LOW, ctr_low, false);
629	ret \|= dwmac5_est_write(ioaddr, CTR_HIGH, total_ctr, false);
630	if (ret)
631	return ret;
632
633	ctrl = readl(ioaddr + MTL_EST_CONTROL);	589	ctrl = readl(ioaddr + MTL_EST_CONTROL);
634	ctrl &= ~PTOV;	590	ctrl &= ~PTOV;
635	ctrl \|= ((1000000000 / ptp_rate) * 6) << PTOV_SHIFT;	591	ctrl \|= ((1000000000 / ptp_rate) * 6) << PTOV_SHIFT;

drivers/net/ethernet/stmicro/stmmac/stmmac_main.c+4−3

 			spin_lock_irqsave(&ch->lock, flags);
 			stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 0);
 			spin_unlock_irqrestore(&ch->lock, flags);
-			__napi_schedule_irqoff(&ch->rx_napi);
+			__napi_schedule(&ch->rx_napi);
 		}
 	}
 			spin_lock_irqsave(&ch->lock, flags);
 			stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 0, 1);
 			spin_unlock_irqrestore(&ch->lock, flags);
-			__napi_schedule_irqoff(&ch->tx_napi);
+			__napi_schedule(&ch->tx_napi);
 		}
 	}
 {
 	struct stmmac_priv *priv = netdev_priv(dev);
 	int txfifosz = priv->plat->tx_fifo_size;
+	const int mtu = new_mtu;
 	if (txfifosz == 0)
 		txfifosz = priv->dma_cap.tx_fifo_size;
 	if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB))
 		return -EINVAL;
-	dev->mtu = new_mtu;
+	dev->mtu = mtu;
 	netdev_update_features(dev);

drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c+18−2

@@ -599,7 +599,8 @@ static int tc_setup_taprio(struct stmmac_priv *priv, · 598 unmodified lines
599	{	599	{
600	u32 size, wid = priv->dma_cap.estwid, dep = priv->dma_cap.estdep;	600	u32 size, wid = priv->dma_cap.estwid, dep = priv->dma_cap.estdep;
601	struct plat_stmmacenet_data *plat = priv->plat;	601	struct plat_stmmacenet_data *plat = priv->plat;
602	struct timespec64 time;	602	struct timespec64 time, current_time;
		603	ktime_t current_time_ns;
603	bool fpe = false;	604	bool fpe = false;
604	int i, ret = 0;	605	int i, ret = 0;
605	u64 ctr;	606	u64 ctr;
@@ -694,7 +695,22 @@ static int tc_setup_taprio(struct stmmac_priv *priv, · 88 unmodified lines
694	}	695	}
695		696
696	/* Adjust for real system time */	697	/* Adjust for real system time */
697	time = ktime_to_timespec64(qopt->base_time);	698	priv->ptp_clock_ops.gettime64(&priv->ptp_clock_ops, &current_time);
		699	current_time_ns = timespec64_to_ktime(current_time);
		700	if (ktime_after(qopt->base_time, current_time_ns)) {
		701	time = ktime_to_timespec64(qopt->base_time);
		702	} else {
		703	ktime_t base_time;
		704	s64 n;
		705
		706	n = div64_s64(ktime_sub_ns(current_time_ns, qopt->base_time),
		707	qopt->cycle_time);
		708	base_time = ktime_add_ns(qopt->base_time,
		709	(n + 1) * qopt->cycle_time);
		710
		711	time = ktime_to_timespec64(base_time);
		712	}
		713
698	priv->plat->est->btr[0] = (u32)time.tv_nsec;	714	priv->plat->est->btr[0] = (u32)time.tv_nsec;
699	priv->plat->est->btr[1] = (u32)time.tv_sec;	715	priv->plat->est->btr[1] = (u32)time.tv_sec;
700		716

drivers/net/ethernet/ti/cpts.c+2−0

 	ptp_clock_unregister(cpts->clock);
 	cpts->clock = NULL;
+	cpts->phc_index = -1;
 	cpts_write32(cpts, 0, int_enable);
 	cpts_write32(cpts, 0, control);
 	cpts->cc.read = cpts_systim_read;
 	cpts->cc.mask = CLOCKSOURCE_MASK(32);
 	cpts->info = cpts_info;
+	cpts->phc_index = -1;
 	if (n_ext_ts)
 		cpts->info.n_ext_ts = n_ext_ts;

drivers/net/ipa/gsi.c+69−58

@@ -326,8 +326,8 @@ gsi_evt_ring_state(struct gsi *gsi, u32 evt_ring_id) · 325 unmodified lines
326	}	326	}
327		327
328	/* Issue an event ring command and wait for it to complete */	328	/* Issue an event ring command and wait for it to complete */
329	static int evt_ring_command(struct gsi *gsi, u32 evt_ring_id,	329	static void evt_ring_command(struct gsi *gsi, u32 evt_ring_id,
330	enum gsi_evt_cmd_opcode opcode)	330	enum gsi_evt_cmd_opcode opcode)
331	{	331	{
332	struct gsi_evt_ring *evt_ring = &gsi->evt_ring[evt_ring_id];	332	struct gsi_evt_ring *evt_ring = &gsi->evt_ring[evt_ring_id];
333	struct completion *completion = &evt_ring->completion;	333	struct completion *completion = &evt_ring->completion;
@@ -340,7 +340,13 @@ static int evt_ring_command(struct gsi *gsi, u32 evt_ring_id, · 6 unmodified lines
340	* is issued here. Only permit this event ring to trigger	340	* is issued here. Only permit this event ring to trigger
341	* an interrupt, and only enable the event control IRQ type	341	* an interrupt, and only enable the event control IRQ type
342	* when we expect it to occur.	342	* when we expect it to occur.
		343	*
		344	* There's a small chance that a previous command completed
		345	* after the interrupt was disabled, so make sure we have no
		346	* pending interrupts before we enable them.
343	*/	347	*/
		348	iowrite32(~0, gsi->virt + GSI_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET);
		349
344	val = BIT(evt_ring_id);	350	val = BIT(evt_ring_id);
345	iowrite32(val, gsi->virt + GSI_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET);	351	iowrite32(val, gsi->virt + GSI_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET);
346	gsi_irq_type_enable(gsi, GSI_EV_CTRL);	352	gsi_irq_type_enable(gsi, GSI_EV_CTRL);
@@ -355,19 +361,16 @@ static int evt_ring_command(struct gsi *gsi, u32 evt_ring_id, · 8 unmodified lines
355	iowrite32(0, gsi->virt + GSI_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET);	361	iowrite32(0, gsi->virt + GSI_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET);
356		362
357	if (success)	363	if (success)
358	return 0;	364	return;
359		365
360	dev_err(dev, "GSI command %u for event ring %u timed out, state %u\n",	366	dev_err(dev, "GSI command %u for event ring %u timed out, state %u\n",
361	opcode, evt_ring_id, evt_ring->state);	367	opcode, evt_ring_id, evt_ring->state);
362
363	return -ETIMEDOUT;
364	}	368	}
365		369
366	/* Allocate an event ring in NOT_ALLOCATED state */	370	/* Allocate an event ring in NOT_ALLOCATED state */
367	static int gsi_evt_ring_alloc_command(struct gsi *gsi, u32 evt_ring_id)	371	static int gsi_evt_ring_alloc_command(struct gsi *gsi, u32 evt_ring_id)
368	{	372	{
369	struct gsi_evt_ring *evt_ring = &gsi->evt_ring[evt_ring_id];	373	struct gsi_evt_ring *evt_ring = &gsi->evt_ring[evt_ring_id];
370	int ret;
371		374
372	/* Get initial event ring state */	375	/* Get initial event ring state */
373	evt_ring->state = gsi_evt_ring_state(gsi, evt_ring_id);	376	evt_ring->state = gsi_evt_ring_state(gsi, evt_ring_id);
@@ -377,14 +380,16 @@ static int gsi_evt_ring_alloc_command(struct gsi *gsi, u32 evt_ring_id) · 3 unmodified lines
377	return -EINVAL;	380	return -EINVAL;
378	}	381	}
379		382
380	ret = evt_ring_command(gsi, evt_ring_id, GSI_EVT_ALLOCATE);	383	evt_ring_command(gsi, evt_ring_id, GSI_EVT_ALLOCATE);
381	if (!ret && evt_ring->state != GSI_EVT_RING_STATE_ALLOCATED) {
382	dev_err(gsi->dev, "event ring %u bad state %u after alloc\n",
383	evt_ring_id, evt_ring->state);
384	ret = -EIO;
385	}
386		384
387	return ret;	385	/* If successful the event ring state will have changed */
		386	if (evt_ring->state == GSI_EVT_RING_STATE_ALLOCATED)
		387	return 0;
		388
		389	dev_err(gsi->dev, "event ring %u bad state %u after alloc\n",
		390	evt_ring_id, evt_ring->state);
		391
		392	return -EIO;
388	}	393	}
389		394
390	/* Reset a GSI event ring in ALLOCATED or ERROR state. */	395	/* Reset a GSI event ring in ALLOCATED or ERROR state. */
@@ -392,7 +397,6 @@ static void gsi_evt_ring_reset_command(struct gsi *gsi, u32 evt_ring_id) · 1 unmodified line
392	{	397	{
393	struct gsi_evt_ring *evt_ring = &gsi->evt_ring[evt_ring_id];	398	struct gsi_evt_ring *evt_ring = &gsi->evt_ring[evt_ring_id];
394	enum gsi_evt_ring_state state = evt_ring->state;	399	enum gsi_evt_ring_state state = evt_ring->state;
395	int ret;
396		400
397	if (state != GSI_EVT_RING_STATE_ALLOCATED &&	401	if (state != GSI_EVT_RING_STATE_ALLOCATED &&
398	state != GSI_EVT_RING_STATE_ERROR) {	402	state != GSI_EVT_RING_STATE_ERROR) {
@@ -401,17 +405,20 @@ static void gsi_evt_ring_reset_command(struct gsi *gsi, u32 evt_ring_id) · 2 unmodified lines
401	return;	405	return;
402	}	406	}
403		407
404	ret = evt_ring_command(gsi, evt_ring_id, GSI_EVT_RESET);	408	evt_ring_command(gsi, evt_ring_id, GSI_EVT_RESET);
405	if (!ret && evt_ring->state != GSI_EVT_RING_STATE_ALLOCATED)	409
406	dev_err(gsi->dev, "event ring %u bad state %u after reset\n",	410	/* If successful the event ring state will have changed */
407	evt_ring_id, evt_ring->state);	411	if (evt_ring->state == GSI_EVT_RING_STATE_ALLOCATED)
		412	return;
		413
		414	dev_err(gsi->dev, "event ring %u bad state %u after reset\n",
		415	evt_ring_id, evt_ring->state);
408	}	416	}
409		417
410	/* Issue a hardware de-allocation request for an allocated event ring */	418	/* Issue a hardware de-allocation request for an allocated event ring */
411	static void gsi_evt_ring_de_alloc_command(struct gsi *gsi, u32 evt_ring_id)	419	static void gsi_evt_ring_de_alloc_command(struct gsi *gsi, u32 evt_ring_id)
412	{	420	{
413	struct gsi_evt_ring *evt_ring = &gsi->evt_ring[evt_ring_id];	421	struct gsi_evt_ring *evt_ring = &gsi->evt_ring[evt_ring_id];
414	int ret;
415		422
416	if (evt_ring->state != GSI_EVT_RING_STATE_ALLOCATED) {	423	if (evt_ring->state != GSI_EVT_RING_STATE_ALLOCATED) {
417	dev_err(gsi->dev, "event ring %u state %u before dealloc\n",	424	dev_err(gsi->dev, "event ring %u state %u before dealloc\n",
@@ -419,10 +426,14 @@ static void gsi_evt_ring_de_alloc_command(struct gsi *gsi, u32 evt_ring_id) · 1 unmodified line
419	return;	426	return;
420	}	427	}
421		428
422	ret = evt_ring_command(gsi, evt_ring_id, GSI_EVT_DE_ALLOC);	429	evt_ring_command(gsi, evt_ring_id, GSI_EVT_DE_ALLOC);
423	if (!ret && evt_ring->state != GSI_EVT_RING_STATE_NOT_ALLOCATED)	430
424	dev_err(gsi->dev, "event ring %u bad state %u after dealloc\n",	431	/* If successful the event ring state will have changed */
425	evt_ring_id, evt_ring->state);	432	if (evt_ring->state == GSI_EVT_RING_STATE_NOT_ALLOCATED)
		433	return;
		434
		435	dev_err(gsi->dev, "event ring %u bad state %u after dealloc\n",
		436	evt_ring_id, evt_ring->state);
426	}	437	}
427		438
428	/* Fetch the current state of a channel from hardware */	439	/* Fetch the current state of a channel from hardware */
@@ -438,7 +449,7 @@ static enum gsi_channel_state gsi_channel_state(struct gsi_channel *channel) · 9 unmodified lines
438	}	449	}
439		450
440	/* Issue a channel command and wait for it to complete */	451	/* Issue a channel command and wait for it to complete */
441	static int	452	static void
442	gsi_channel_command(struct gsi_channel *channel, enum gsi_ch_cmd_opcode opcode)	453	gsi_channel_command(struct gsi_channel *channel, enum gsi_ch_cmd_opcode opcode)
443	{	454	{
444	struct completion *completion = &channel->completion;	455	struct completion *completion = &channel->completion;
@@ -453,7 +464,13 @@ gsi_channel_command(struct gsi_channel *channel, enum gsi_ch_cmd_opcode opcode) · 8 unmodified lines
453	* issued here. So we only permit this channel to trigger	464	* issued here. So we only permit this channel to trigger
454	* an interrupt and only enable the channel control IRQ type	465	* an interrupt and only enable the channel control IRQ type
455	* when we expect it to occur.	466	* when we expect it to occur.
		467	*
		468	* There's a small chance that a previous command completed
		469	* after the interrupt was disabled, so make sure we have no
		470	* pending interrupts before we enable them.
456	*/	471	*/
		472	iowrite32(~0, gsi->virt + GSI_CNTXT_SRC_CH_IRQ_CLR_OFFSET);
		473
457	val = BIT(channel_id);	474	val = BIT(channel_id);
458	iowrite32(val, gsi->virt + GSI_CNTXT_SRC_CH_IRQ_MSK_OFFSET);	475	iowrite32(val, gsi->virt + GSI_CNTXT_SRC_CH_IRQ_MSK_OFFSET);
459	gsi_irq_type_enable(gsi, GSI_CH_CTRL);	476	gsi_irq_type_enable(gsi, GSI_CH_CTRL);
@@ -467,12 +484,10 @@ gsi_channel_command(struct gsi_channel *channel, enum gsi_ch_cmd_opcode opcode) · 7 unmodified lines
467	iowrite32(0, gsi->virt + GSI_CNTXT_SRC_CH_IRQ_MSK_OFFSET);	484	iowrite32(0, gsi->virt + GSI_CNTXT_SRC_CH_IRQ_MSK_OFFSET);
468		485
469	if (success)	486	if (success)
470	return 0;	487	return;
471		488
472	dev_err(dev, "GSI command %u for channel %u timed out, state %u\n",	489	dev_err(dev, "GSI command %u for channel %u timed out, state %u\n",
473	opcode, channel_id, gsi_channel_state(channel));	490	opcode, channel_id, gsi_channel_state(channel));
474
475	return -ETIMEDOUT;
476	}	491	}
477		492
478	/* Allocate GSI channel in NOT_ALLOCATED state */	493	/* Allocate GSI channel in NOT_ALLOCATED state */
@@ -481,7 +496,6 @@ static int gsi_channel_alloc_command(struct gsi *gsi, u32 channel_id) · 2 unmodified lines
481	struct gsi_channel *channel = &gsi->channel[channel_id];	496	struct gsi_channel *channel = &gsi->channel[channel_id];
482	struct device *dev = gsi->dev;	497	struct device *dev = gsi->dev;
483	enum gsi_channel_state state;	498	enum gsi_channel_state state;
484	int ret;
485		499
486	/* Get initial channel state */	500	/* Get initial channel state */
487	state = gsi_channel_state(channel);	501	state = gsi_channel_state(channel);
@@ -491,17 +505,17 @@ static int gsi_channel_alloc_command(struct gsi *gsi, u32 channel_id) · 3 unmodified lines
491	return -EINVAL;	505	return -EINVAL;
492	}	506	}
493		507
494	ret = gsi_channel_command(channel, GSI_CH_ALLOCATE);	508	gsi_channel_command(channel, GSI_CH_ALLOCATE);
495		509
496	/* Channel state will normally have been updated */	510	/* If successful the channel state will have changed */
497	state = gsi_channel_state(channel);	511	state = gsi_channel_state(channel);
498	if (!ret && state != GSI_CHANNEL_STATE_ALLOCATED) {	512	if (state == GSI_CHANNEL_STATE_ALLOCATED)
499	dev_err(dev, "channel %u bad state %u after alloc\n",	513	return 0;
500	channel_id, state);
501	ret = -EIO;
502	}
503		514
504	return ret;	515	dev_err(dev, "channel %u bad state %u after alloc\n",
		516	channel_id, state);
		517
		518	return -EIO;
505	}	519	}
506		520
507	/* Start an ALLOCATED channel */	521	/* Start an ALLOCATED channel */
@@ -509,7 +523,6 @@ static int gsi_channel_start_command(struct gsi_channel *channel) · 1 unmodified line
509	{	523	{
510	struct device *dev = channel->gsi->dev;	524	struct device *dev = channel->gsi->dev;
511	enum gsi_channel_state state;	525	enum gsi_channel_state state;
512	int ret;
513		526
514	state = gsi_channel_state(channel);	527	state = gsi_channel_state(channel);
515	if (state != GSI_CHANNEL_STATE_ALLOCATED &&	528	if (state != GSI_CHANNEL_STATE_ALLOCATED &&
@@ -519,17 +532,17 @@ static int gsi_channel_start_command(struct gsi_channel *channel) · 3 unmodified lines
519	return -EINVAL;	532	return -EINVAL;
520	}	533	}
521		534
522	ret = gsi_channel_command(channel, GSI_CH_START);	535	gsi_channel_command(channel, GSI_CH_START);
523		536
524	/* Channel state will normally have been updated */	537	/* If successful the channel state will have changed */
525	state = gsi_channel_state(channel);	538	state = gsi_channel_state(channel);
526	if (!ret && state != GSI_CHANNEL_STATE_STARTED) {	539	if (state == GSI_CHANNEL_STATE_STARTED)
527	dev_err(dev, "channel %u bad state %u after start\n",	540	return 0;
528	gsi_channel_id(channel), state);
529	ret = -EIO;
530	}
531		541
532	return ret;	542	dev_err(dev, "channel %u bad state %u after start\n",
		543	gsi_channel_id(channel), state);
		544
		545	return -EIO;
533	}	546	}
534		547
535	/* Stop a GSI channel in STARTED state */	548	/* Stop a GSI channel in STARTED state */
@@ -537,7 +550,6 @@ static int gsi_channel_stop_command(struct gsi_channel *channel) · 1 unmodified line
537	{	550	{
538	struct device *dev = channel->gsi->dev;	551	struct device *dev = channel->gsi->dev;
539	enum gsi_channel_state state;	552	enum gsi_channel_state state;
540	int ret;
541		553
542	state = gsi_channel_state(channel);	554	state = gsi_channel_state(channel);
543		555
@@ -554,12 +566,12 @@ static int gsi_channel_stop_command(struct gsi_channel *channel) · 10 unmodified lines
554	return -EINVAL;	566	return -EINVAL;
555	}	567	}
556		568
557	ret = gsi_channel_command(channel, GSI_CH_STOP);	569	gsi_channel_command(channel, GSI_CH_STOP);
558		570
559	/* Channel state will normally have been updated */	571	/* If successful the channel state will have changed */
560	state = gsi_channel_state(channel);	572	state = gsi_channel_state(channel);
561	if (ret \|\| state == GSI_CHANNEL_STATE_STOPPED)	573	if (state == GSI_CHANNEL_STATE_STOPPED)
562	return ret;	574	return 0;
563		575
564	/* We may have to try again if stop is in progress */	576	/* We may have to try again if stop is in progress */
565	if (state == GSI_CHANNEL_STATE_STOP_IN_PROC)	577	if (state == GSI_CHANNEL_STATE_STOP_IN_PROC)
@@ -576,7 +588,6 @@ static void gsi_channel_reset_command(struct gsi_channel *channel) · 10 unmodified lines
576	{	588	{
577	struct device *dev = channel->gsi->dev;	589	struct device *dev = channel->gsi->dev;
578	enum gsi_channel_state state;	590	enum gsi_channel_state state;
579	int ret;
580		591
581	msleep(1); /* A short delay is required before a RESET command */	592	msleep(1); /* A short delay is required before a RESET command */
582		593
@@ -590,11 +601,11 @@ static void gsi_channel_reset_command(struct gsi_channel *channel) · 7 unmodified lines
590	return;	601	return;
591	}	602	}
592		603
593	ret = gsi_channel_command(channel, GSI_CH_RESET);	604	gsi_channel_command(channel, GSI_CH_RESET);
594		605
595	/* Channel state will normally have been updated */	606	/* If successful the channel state will have changed */
596	state = gsi_channel_state(channel);	607	state = gsi_channel_state(channel);
597	if (!ret && state != GSI_CHANNEL_STATE_ALLOCATED)	608	if (state != GSI_CHANNEL_STATE_ALLOCATED)
598	dev_err(dev, "channel %u bad state %u after reset\n",	609	dev_err(dev, "channel %u bad state %u after reset\n",
599	gsi_channel_id(channel), state);	610	gsi_channel_id(channel), state);
600	}	611	}
@@ -605,7 +616,6 @@ static void gsi_channel_de_alloc_command(struct gsi *gsi, u32 channel_id) · 4 unmodified lines
605	struct gsi_channel *channel = &gsi->channel[channel_id];	616	struct gsi_channel *channel = &gsi->channel[channel_id];
606	struct device *dev = gsi->dev;	617	struct device *dev = gsi->dev;
607	enum gsi_channel_state state;	618	enum gsi_channel_state state;
608	int ret;
609		619
610	state = gsi_channel_state(channel);	620	state = gsi_channel_state(channel);
611	if (state != GSI_CHANNEL_STATE_ALLOCATED) {	621	if (state != GSI_CHANNEL_STATE_ALLOCATED) {
@@ -614,11 +624,12 @@ static void gsi_channel_de_alloc_command(struct gsi *gsi, u32 channel_id) · 2 unmodified lines
614	return;	624	return;
615	}	625	}
616		626
617	ret = gsi_channel_command(channel, GSI_CH_DE_ALLOC);	627	gsi_channel_command(channel, GSI_CH_DE_ALLOC);
618		628
619	/* Channel state will normally have been updated */	629	/* If successful the channel state will have changed */
620	state = gsi_channel_state(channel);	630	state = gsi_channel_state(channel);
621	if (!ret && state != GSI_CHANNEL_STATE_NOT_ALLOCATED)	631
		632	if (state != GSI_CHANNEL_STATE_NOT_ALLOCATED)
622	dev_err(dev, "channel %u bad state %u after dealloc\n",	633	dev_err(dev, "channel %u bad state %u after dealloc\n",
623	channel_id, state);	634	channel_id, state);
624	}	635	}

drivers/net/ipa/ipa_clock.c+2−2

@@ -115,13 +115,13 @@ static int ipa_interconnect_enable(struct ipa *ipa) · 114 unmodified lines
115	return ret;	115	return ret;
116		116
117	data = &clock->interconnect_data[IPA_INTERCONNECT_IMEM];	117	data = &clock->interconnect_data[IPA_INTERCONNECT_IMEM];
118	ret = icc_set_bw(clock->memory_path, data->average_rate,	118	ret = icc_set_bw(clock->imem_path, data->average_rate,
119	data->peak_rate);	119	data->peak_rate);
120	if (ret)	120	if (ret)
121	goto err_memory_path_disable;	121	goto err_memory_path_disable;
122		122
123	data = &clock->interconnect_data[IPA_INTERCONNECT_CONFIG];	123	data = &clock->interconnect_data[IPA_INTERCONNECT_CONFIG];
124	ret = icc_set_bw(clock->memory_path, data->average_rate,	124	ret = icc_set_bw(clock->config_path, data->average_rate,
125	data->peak_rate);	125	data->peak_rate);
126	if (ret)	126	if (ret)
127	goto err_imem_path_disable;	127	goto err_imem_path_disable;

drivers/net/ipa/ipa_modem.c+1−0

@@ -216,6 +216,7 @@ int ipa_modem_start(struct ipa *ipa) · 215 unmodified lines
216	ipa->name_map[IPA_ENDPOINT_AP_MODEM_TX]->netdev = netdev;	216	ipa->name_map[IPA_ENDPOINT_AP_MODEM_TX]->netdev = netdev;
217	ipa->name_map[IPA_ENDPOINT_AP_MODEM_RX]->netdev = netdev;	217	ipa->name_map[IPA_ENDPOINT_AP_MODEM_RX]->netdev = netdev;
218		218
		219	SET_NETDEV_DEV(netdev, &ipa->pdev->dev);
219	priv = netdev_priv(netdev);	220	priv = netdev_priv(netdev);
220	priv->ipa = ipa;	221	priv->ipa = ipa;
221		222

drivers/net/phy/smsc.c+2−1

@@ -317,7 +317,8 @@ static int smsc_phy_probe(struct phy_device *phydev) · 316 unmodified lines
317	/* Make clk optional to keep DTB backward compatibility. */	317	/* Make clk optional to keep DTB backward compatibility. */
318	priv->refclk = clk_get_optional(dev, NULL);	318	priv->refclk = clk_get_optional(dev, NULL);
319	if (IS_ERR(priv->refclk))	319	if (IS_ERR(priv->refclk))
320	dev_err_probe(dev, PTR_ERR(priv->refclk), "Failed to request clock\n");	320	return dev_err_probe(dev, PTR_ERR(priv->refclk),
		321	"Failed to request clock\n");
321		322
322	ret = clk_prepare_enable(priv->refclk);	323	ret = clk_prepare_enable(priv->refclk);
323	if (ret)	324	if (ret)

drivers/net/ppp/ppp_generic.c+9−3

 		write_unlock_bh(&pch->upl);
 		return -EALREADY;
 	}
+	refcount_inc(&pchb->file.refcnt);
 	rcu_assign_pointer(pch->bridge, pchb);
 	write_unlock_bh(&pch->upl);
 		write_unlock_bh(&pchb->upl);
 		goto err_unset;
 	}
+	refcount_inc(&pch->file.refcnt);
 	rcu_assign_pointer(pchb->bridge, pch);
 	write_unlock_bh(&pchb->upl);
-	refcount_inc(&pch->file.refcnt);
-	refcount_inc(&pchb->file.refcnt);
 	return 0;
 err_unset:
 	write_lock_bh(&pch->upl);
+	/* Re-read pch->bridge with upl held in case it was modified concurrently */
+	pchb = rcu_dereference_protected(pch->bridge, lockdep_is_held(&pch->upl));
 	RCU_INIT_POINTER(pch->bridge, NULL);
 	write_unlock_bh(&pch->upl);
 	synchronize_rcu();
+	if (pchb)
+		if (refcount_dec_and_test(&pchb->file.refcnt))
+			ppp_destroy_channel(pchb);
 	return -EALREADY;
 }

drivers/net/tun.c+1−1

@@ -1365,7 +1365,7 @@ static struct sk_buff tun_napi_alloc_frags(struct tun_file tfile, · 1364 unmodified lines
1365	int i;	1365	int i;
1366		1366
1367	if (it->nr_segs > MAX_SKB_FRAGS + 1)	1367	if (it->nr_segs > MAX_SKB_FRAGS + 1)
1368	return ERR_PTR(-ENOMEM);	1368	return ERR_PTR(-EMSGSIZE);
1369		1369
1370	local_bh_disable();	1370	local_bh_disable();
1371	skb = napi_get_frags(&tfile->napi);	1371	skb = napi_get_frags(&tfile->napi);

drivers/net/usb/Kconfig+0−1

@@ -631,7 +631,6 @@ config USB_NET_AQC111 · 630 unmodified lines
631	config USB_RTL8153_ECM	631	config USB_RTL8153_ECM
632	tristate "RTL8153 ECM support"	632	tristate "RTL8153 ECM support"
633	depends on USB_NET_CDCETHER && (USB_RTL8152 \|\| USB_RTL8152=n)	633	depends on USB_NET_CDCETHER && (USB_RTL8152 \|\| USB_RTL8152=n)
634	default y
635	help	634	help
636	This option supports ECM mode for RTL8153 ethernet adapter, when	635	This option supports ECM mode for RTL8153 ethernet adapter, when
637	CONFIG_USB_RTL8152 is not set, or the RTL8153 device is not	636	CONFIG_USB_RTL8152 is not set, or the RTL8153 device is not

drivers/net/usb/cdc_ether.c+7−0

@@ -793,6 +793,13 @@ static const struct usb_device_id products[] = { · 792 unmodified lines
793	.driver_info = 0,	793	.driver_info = 0,
794	},	794	},
795		795
		796	/* Lenovo Powered USB-C Travel Hub (4X90S92381, based on Realtek RTL8153) */
		797	{
		798	USB_DEVICE_AND_INTERFACE_INFO(LENOVO_VENDOR_ID, 0x721e, USB_CLASS_COMM,
		799	USB_CDC_SUBCLASS_ETHERNET, USB_CDC_PROTO_NONE),
		800	.driver_info = 0,
		801	},
		802
796	/* ThinkPad USB-C Dock Gen 2 (based on Realtek RTL8153) */	803	/* ThinkPad USB-C Dock Gen 2 (based on Realtek RTL8153) */
797	{	804	{
798	USB_DEVICE_AND_INTERFACE_INFO(LENOVO_VENDOR_ID, 0xa387, USB_CLASS_COMM,	805	USB_DEVICE_AND_INTERFACE_INFO(LENOVO_VENDOR_ID, 0xa387, USB_CLASS_COMM,

drivers/net/usb/cdc_ncm.c+6−5

 	 * accordingly. Otherwise, we should check here.
 	 */
 	if (ctx->drvflags & CDC_NCM_FLAG_NDP_TO_END)
-		delayed_ndp_size = ALIGN(ctx->max_ndp_size, ctx->tx_ndp_modulus);
+		delayed_ndp_size = ctx->max_ndp_size +
+			max_t(u32,
+			      ctx->tx_ndp_modulus,
+			      ctx->tx_modulus + ctx->tx_remainder) - 1;
 	else
 		delayed_ndp_size = 0;
 	if (!(dev->driver_info->flags & FLAG_SEND_ZLP) &&
 	    skb_out->len > ctx->min_tx_pkt) {
 		padding_count = ctx->tx_curr_size - skb_out->len;
-		skb_put_zero(skb_out, padding_count);
+		if (!WARN_ON(padding_count > ctx->tx_curr_size))
+			skb_put_zero(skb_out, padding_count);
 	} else if (skb_out->len < ctx->tx_curr_size &&
 		   (skb_out->len % dev->maxpacket) == 0) {
 		skb_put_u8(skb_out, 0);	/* force short packet */
 		 * USB_CDC_NOTIFY_NETWORK_CONNECTION notification shall be
 		 * sent by device after USB_CDC_NOTIFY_SPEED_CHANGE.
 		 */
-		netif_info(dev, link, dev->net,
-			   "network connection: %sconnected\n",
-			   !!event->wValue ? "" : "dis");
 		usbnet_link_change(dev, !!event->wValue, 0);
 		break;

drivers/net/usb/qmi_wwan.c+1−0

@@ -1013,6 +1013,7 @@ static const struct usb_device_id products[] = { · 1012 unmodified lines
1013	{QMI_MATCH_FF_FF_FF(0x2c7c, 0x0125)}, /* Quectel EC25, EC20 R2.0 Mini PCIe */	1013	{QMI_MATCH_FF_FF_FF(0x2c7c, 0x0125)}, /* Quectel EC25, EC20 R2.0 Mini PCIe */
1014	{QMI_MATCH_FF_FF_FF(0x2c7c, 0x0306)}, /* Quectel EP06/EG06/EM06 */	1014	{QMI_MATCH_FF_FF_FF(0x2c7c, 0x0306)}, /* Quectel EP06/EG06/EM06 */
1015	{QMI_MATCH_FF_FF_FF(0x2c7c, 0x0512)}, /* Quectel EG12/EM12 */	1015	{QMI_MATCH_FF_FF_FF(0x2c7c, 0x0512)}, /* Quectel EG12/EM12 */
		1016	{QMI_MATCH_FF_FF_FF(0x2c7c, 0x0620)}, /* Quectel EM160R-GL */
1016	{QMI_MATCH_FF_FF_FF(0x2c7c, 0x0800)}, /* Quectel RM500Q-GL */	1017	{QMI_MATCH_FF_FF_FF(0x2c7c, 0x0800)}, /* Quectel RM500Q-GL */
1017		1018
1018	/* 3. Combined interface devices matching on interface number */	1019	/* 3. Combined interface devices matching on interface number */

drivers/net/usb/r8152.c+1−0

@@ -6877,6 +6877,7 @@ static const struct usb_device_id rtl8152_table[] = { · 6876 unmodified lines
6877	{REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)},	6877	{REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)},
6878	{REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c)},	6878	{REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c)},
6879	{REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214)},	6879	{REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214)},
		6880	{REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x721e)},
6880	{REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0xa387)},	6881	{REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0xa387)},
6881	{REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)},	6882	{REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)},
6882	{REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)},	6883	{REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)},

drivers/net/usb/r8153_ecm.c+8−0

 };
 static const struct usb_device_id products[] = {
+/* Realtek RTL8153 Based USB 3.0 Ethernet Adapters */
 {
 	USB_DEVICE_AND_INTERFACE_INFO(VENDOR_ID_REALTEK, 0x8153, USB_CLASS_COMM,
 				      USB_CDC_SUBCLASS_ETHERNET, USB_CDC_PROTO_NONE),
 	.driver_info = (unsigned long)&r8153_info,
 },
+/* Lenovo Powered USB-C Travel Hub (4X90S92381, based on Realtek RTL8153) */
+{
+	USB_DEVICE_AND_INTERFACE_INFO(VENDOR_ID_LENOVO, 0x721e, USB_CLASS_COMM,
+				      USB_CDC_SUBCLASS_ETHERNET, USB_CDC_PROTO_NONE),
+	.driver_info = (unsigned long)&r8153_info,
+},
 	{ },		/* END */
 };
 MODULE_DEVICE_TABLE(usb, products);

drivers/net/usb/rndis_host.c+1−1

@@ -387,7 +387,7 @@ generic_rndis_bind(struct usbnet dev, struct usb_interface intf, int flags) · 386 unmodified lines
387	reply_len = sizeof *phym;	387	reply_len = sizeof *phym;
388	retval = rndis_query(dev, intf, u.buf,	388	retval = rndis_query(dev, intf, u.buf,
389	RNDIS_OID_GEN_PHYSICAL_MEDIUM,	389	RNDIS_OID_GEN_PHYSICAL_MEDIUM,
390	0, (void **) &phym, &reply_len);	390	reply_len, (void **)&phym, &reply_len);
391	if (retval != 0 \|\| !phym) {	391	if (retval != 0 \|\| !phym) {
392	/* OID is optional so don't fail here. */	392	/* OID is optional so don't fail here. */
393	phym_unspec = cpu_to_le32(RNDIS_PHYSICAL_MEDIUM_UNSPECIFIED);	393	phym_unspec = cpu_to_le32(RNDIS_PHYSICAL_MEDIUM_UNSPECIFIED);

drivers/net/virtio_net.c+7−5

 	get_online_cpus();
 	err = _virtnet_set_queues(vi, queue_pairs);
-	if (!err) {
+	if (err) {
-		netif_set_real_num_tx_queues(dev, queue_pairs);
+		put_online_cpus();
-		netif_set_real_num_rx_queues(dev, queue_pairs);
+		goto err;
-		virtnet_set_affinity(vi);
 	}
+	virtnet_set_affinity(vi);
 	put_online_cpus();
+	netif_set_real_num_tx_queues(dev, queue_pairs);
+	netif_set_real_num_rx_queues(dev, queue_pairs);
+ err:
 	return err;
 }

drivers/net/wan/Kconfig+1−0

@@ -282,6 +282,7 @@ config SLIC_DS26522 · 281 unmodified lines
282	tristate "Slic Maxim ds26522 card support"	282	tristate "Slic Maxim ds26522 card support"
283	depends on SPI	283	depends on SPI
284	depends on FSL_SOC \|\| ARCH_MXC \|\| ARCH_LAYERSCAPE \|\| COMPILE_TEST	284	depends on FSL_SOC \|\| ARCH_MXC \|\| ARCH_LAYERSCAPE \|\| COMPILE_TEST
		285	select BITREVERSE
285	help	286	help
286	This module initializes and configures the slic maxim card	287	This module initializes and configures the slic maxim card
287	in T1 or E1 mode.	288	in T1 or E1 mode.

drivers/net/wan/hdlc_ppp.c+7−0

@@ -569,6 +569,13 @@ static void ppp_timer(struct timer_list *t) · 568 unmodified lines
569	unsigned long flags;	569	unsigned long flags;
570		570
571	spin_lock_irqsave(&ppp->lock, flags);	571	spin_lock_irqsave(&ppp->lock, flags);
		572	/* mod_timer could be called after we entered this function but
		573	* before we got the lock.
		574	*/
		575	if (timer_pending(&proto->timer)) {
		576	spin_unlock_irqrestore(&ppp->lock, flags);
		577	return;
		578	}
572	switch (proto->state) {	579	switch (proto->state) {
573	case STOPPING:	580	case STOPPING:
574	case REQ_SENT:	581	case REQ_SENT:

drivers/net/wireless/ath/ath11k/core.c+1−1

@@ -185,7 +185,7 @@ int ath11k_core_suspend(struct ath11k_base *ab) · 184 unmodified lines
185	ath11k_hif_ce_irq_disable(ab);	185	ath11k_hif_ce_irq_disable(ab);
186		186
187	ret = ath11k_hif_suspend(ab);	187	ret = ath11k_hif_suspend(ab);
188	if (!ret) {	188	if (ret) {
189	ath11k_warn(ab, "failed to suspend hif: %d\n", ret);	189	ath11k_warn(ab, "failed to suspend hif: %d\n", ret);
190	return ret;	190	return ret;
191	}	191	}

drivers/net/wireless/ath/ath11k/dp_rx.c+7−3

 {
 	u8 channel_num;
 	u32 center_freq;
+	struct ieee80211_channel *channel;
 	rx_status->freq = 0;
 	rx_status->rate_idx = 0;
 		rx_status->band = NL80211_BAND_5GHZ;
 	} else {
 		spin_lock_bh(&ar->data_lock);
-		rx_status->band = ar->rx_channel->band;
+		channel = ar->rx_channel;
-		channel_num =
+		if (channel) {
-			ieee80211_frequency_to_channel(ar->rx_channel->center_freq);
+			rx_status->band = channel->band;
+			channel_num =
+				ieee80211_frequency_to_channel(channel->center_freq);
+		}
 		spin_unlock_bh(&ar->data_lock);
 		ath11k_dbg_dump(ar->ab, ATH11K_DBG_DATA, NULL, "rx_desc: ",
 				rx_desc, sizeof(struct hal_rx_desc));

drivers/net/wireless/ath/ath11k/mac.c+6−2

 	}
 	if (ab->hw_params.vdev_start_delay &&
+	    !arvif->is_started &&
 	    arvif->vdev_type != WMI_VDEV_TYPE_AP) {
 		ret = ath11k_start_vdev_delay(ar->hw, vif);
 		if (ret) {
 	/* for QCA6390 bss peer must be created before vdev_start */
 	if (ab->hw_params.vdev_start_delay &&
 	    arvif->vdev_type != WMI_VDEV_TYPE_AP &&
-	    arvif->vdev_type != WMI_VDEV_TYPE_MONITOR) {
+	    arvif->vdev_type != WMI_VDEV_TYPE_MONITOR &&
+	    !ath11k_peer_find_by_vdev_id(ab, arvif->vdev_id)) {
 		memcpy(&arvif->chanctx, ctx, sizeof(*ctx));
 		ret = 0;
 		goto out;
 		goto out;
 	}
-	if (ab->hw_params.vdev_start_delay) {
+	if (ab->hw_params.vdev_start_delay &&
+	    (arvif->vdev_type == WMI_VDEV_TYPE_AP ||
+	    arvif->vdev_type == WMI_VDEV_TYPE_MONITOR)) {
 		param.vdev_id = arvif->vdev_id;
 		param.peer_type = WMI_PEER_TYPE_DEFAULT;
 		param.peer_addr = ar->mac_addr;

drivers/net/wireless/ath/ath11k/pci.c+40−4

 				      PCIE_QSERDES_COM_SYSCLK_EN_SEL_REG,
 				      PCIE_QSERDES_COM_SYSCLK_EN_SEL_VAL,
 				      PCIE_QSERDES_COM_SYSCLK_EN_SEL_MSK);
-	if (!ret) {
+	if (ret) {
 		ath11k_warn(ab, "failed to set sysclk: %d\n", ret);
 		return ret;
 	}
 				      PCIE_USB3_PCS_MISC_OSC_DTCT_CONFIG1_REG,
 				      PCIE_USB3_PCS_MISC_OSC_DTCT_CONFIG1_VAL,
 				      PCIE_USB3_PCS_MISC_OSC_DTCT_CONFIG_MSK);
-	if (!ret) {
+	if (ret) {
 		ath11k_warn(ab, "failed to set dtct config1 error: %d\n", ret);
 		return ret;
 	}
 				      PCIE_USB3_PCS_MISC_OSC_DTCT_CONFIG2_REG,
 				      PCIE_USB3_PCS_MISC_OSC_DTCT_CONFIG2_VAL,
 				      PCIE_USB3_PCS_MISC_OSC_DTCT_CONFIG_MSK);
-	if (!ret) {
+	if (ret) {
 		ath11k_warn(ab, "failed to set dtct config2: %d\n", ret);
 		return ret;
 	}
 				      PCIE_USB3_PCS_MISC_OSC_DTCT_CONFIG4_REG,
 				      PCIE_USB3_PCS_MISC_OSC_DTCT_CONFIG4_VAL,
 				      PCIE_USB3_PCS_MISC_OSC_DTCT_CONFIG_MSK);
-	if (!ret) {
+	if (ret) {
 		ath11k_warn(ab, "failed to set dtct config4: %d\n", ret);
 		return ret;
 	}
 		pci_disable_device(pci_dev);
 }
+static void ath11k_pci_aspm_disable(struct ath11k_pci *ab_pci)
+{
+	struct ath11k_base *ab = ab_pci->ab;
+	pcie_capability_read_word(ab_pci->pdev, PCI_EXP_LNKCTL,
+				  &ab_pci->link_ctl);
+	ath11k_dbg(ab, ATH11K_DBG_PCI, "pci link_ctl 0x%04x L0s %d L1 %d\n",
+		   ab_pci->link_ctl,
+		   u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L0S),
+		   u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L1));
+	/* disable L0s and L1 */
+	pcie_capability_write_word(ab_pci->pdev, PCI_EXP_LNKCTL,
+				   ab_pci->link_ctl & ~PCI_EXP_LNKCTL_ASPMC);
+	set_bit(ATH11K_PCI_ASPM_RESTORE, &ab_pci->flags);
+}
+static void ath11k_pci_aspm_restore(struct ath11k_pci *ab_pci)
+{
+	if (test_and_clear_bit(ATH11K_PCI_ASPM_RESTORE, &ab_pci->flags))
+		pcie_capability_write_word(ab_pci->pdev, PCI_EXP_LNKCTL,
+					   ab_pci->link_ctl);
+}
 static int ath11k_pci_power_up(struct ath11k_base *ab)
 {
 	struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
 	clear_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags);
 	ath11k_pci_sw_reset(ab_pci->ab, true);
+	/* Disable ASPM during firmware download due to problems switching
+	 * to AMSS state.
+	 */
+	ath11k_pci_aspm_disable(ab_pci);
 	ret = ath11k_mhi_start(ab_pci);
 	if (ret) {
 		ath11k_err(ab, "failed to start mhi: %d\n", ret);
 {
 	struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
+	/* restore aspm in case firmware bootup fails */
+	ath11k_pci_aspm_restore(ab_pci);
 	ath11k_pci_force_wake(ab_pci->ab);
 	ath11k_mhi_stop(ab_pci);
 	clear_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags);
 	set_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags);
+	ath11k_pci_aspm_restore(ab_pci);
 	ath11k_pci_ce_irqs_enable(ab);
 	ath11k_ce_rx_post_buf(ab);

drivers/net/wireless/ath/ath11k/pci.h+2−0

 enum ath11k_pci_flags {
 	ATH11K_PCI_FLAG_INIT_DONE,
 	ATH11K_PCI_FLAG_IS_MSI_64,
+	ATH11K_PCI_ASPM_RESTORE,
 };
 struct ath11k_pci {
 	/* enum ath11k_pci_flags */
 	unsigned long flags;
+	u16 link_ctl;
 };
 static inline struct ath11k_pci *ath11k_pci_priv(struct ath11k_base *ab)

drivers/net/wireless/ath/ath11k/peer.c+17−0

@@ -76,6 +76,23 @@ struct ath11k_peer ath11k_peer_find_by_id(struct ath11k_base ab, · 75 unmodified lines
76	return NULL;	76	return NULL;
77	}	77	}
78		78
		79	struct ath11k_peer ath11k_peer_find_by_vdev_id(struct ath11k_base ab,
		80	int vdev_id)
		81	{
		82	struct ath11k_peer *peer;
		83
		84	spin_lock_bh(&ab->base_lock);
		85
		86	list_for_each_entry(peer, &ab->peers, list) {
		87	if (vdev_id == peer->vdev_id) {
		88	spin_unlock_bh(&ab->base_lock);
		89	return peer;
		90	}
		91	}
		92	spin_unlock_bh(&ab->base_lock);
		93	return NULL;
		94	}
		95
79	void ath11k_peer_unmap_event(struct ath11k_base *ab, u16 peer_id)	96	void ath11k_peer_unmap_event(struct ath11k_base *ab, u16 peer_id)
80	{	97	{
81	struct ath11k_peer *peer;	98	struct ath11k_peer *peer;

drivers/net/wireless/ath/ath11k/peer.h+2−0

@@ -43,5 +43,7 @@ int ath11k_peer_create(struct ath11k ar, struct ath11k_vif arvif, · 42 unmodified lines
43	struct ieee80211_sta sta, struct peer_create_params param);	43	struct ieee80211_sta sta, struct peer_create_params param);
44	int ath11k_wait_for_peer_delete_done(struct ath11k *ar, u32 vdev_id,	44	int ath11k_wait_for_peer_delete_done(struct ath11k *ar, u32 vdev_id,
45	const u8 *addr);	45	const u8 *addr);
		46	struct ath11k_peer ath11k_peer_find_by_vdev_id(struct ath11k_base ab,
		47	int vdev_id);
46		48
47	#endif /* _PEER_H_ */	49	#endif /* _PEER_H_ */

drivers/net/wireless/ath/ath11k/qmi.c+22−2

 	struct qmi_wlanfw_respond_mem_resp_msg_v01 resp;
 	struct qmi_txn txn = {};
 	int ret = 0, i;
+	bool delayed;
 	req = kzalloc(sizeof(*req), GFP_KERNEL);
 	if (!req)
 	 * failure to FW and FW will then request mulitple blocks of small
 	 * chunk size memory.
 	 */
-	if (!ab->bus_params.fixed_mem_region && ab->qmi.mem_seg_count <= 2) {
+	if (!ab->bus_params.fixed_mem_region && ab->qmi.target_mem_delayed) {
+		delayed = true;
 		ath11k_dbg(ab, ATH11K_DBG_QMI, "qmi delays mem_request %d\n",
 			   ab->qmi.mem_seg_count);
 		memset(req, 0, sizeof(*req));
 	} else {
+		delayed = false;
 		req->mem_seg_len = ab->qmi.mem_seg_count;
 		for (i = 0; i < req->mem_seg_len ; i++) {
 	}
 	if (resp.resp.result != QMI_RESULT_SUCCESS_V01) {
+		/* the error response is expected when
+		 * target_mem_delayed is true.
+		 */
+		if (delayed && resp.resp.error == 0)
+			goto out;
 		ath11k_warn(ab, "Respond mem req failed, result: %d, err: %d\n",
 			    resp.resp.result, resp.resp.error);
 		ret = -EINVAL;
 	int i;
 	struct target_mem_chunk *chunk;
+	ab->qmi.target_mem_delayed = false;
 	for (i = 0; i < ab->qmi.mem_seg_count; i++) {
 		chunk = &ab->qmi.target_mem[i];
 		chunk->vaddr = dma_alloc_coherent(ab->dev,
 						  &chunk->paddr,
 						  GFP_KERNEL);
 		if (!chunk->vaddr) {
+			if (ab->qmi.mem_seg_count <= 2) {
+				ath11k_dbg(ab, ATH11K_DBG_QMI,
+					   "qmi dma allocation failed (%d B type %u), will try later with small size\n",
+					    chunk->size,
+					    chunk->type);
+				ath11k_qmi_free_target_mem_chunk(ab);
+				ab->qmi.target_mem_delayed = true;
+				return 0;
+			}
 			ath11k_err(ab, "failed to alloc memory, size: 0x%x, type: %u\n",
 				   chunk->size,
 				   chunk->type);
 				    ret);
 			return;
 		}
-	} else if (msg->mem_seg_len > 2) {
+	} else {
 		ret = ath11k_qmi_alloc_target_mem_chunk(ab);
 		if (ret) {
 			ath11k_warn(ab, "qmi failed to alloc target memory: %d\n",

drivers/net/wireless/ath/ath11k/qmi.h+1−0

@@ -125,6 +125,7 @@ struct ath11k_qmi { · 124 unmodified lines
125	struct target_mem_chunk target_mem[ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01];	125	struct target_mem_chunk target_mem[ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01];
126	u32 mem_seg_count;	126	u32 mem_seg_count;
127	u32 target_mem_mode;	127	u32 target_mem_mode;
		128	bool target_mem_delayed;
128	u8 cal_done;	129	u8 cal_done;
129	struct target_info target;	130	struct target_info target;
130	struct m3_mem_region m3_mem;	131	struct m3_mem_region m3_mem;

drivers/net/wireless/ath/ath11k/wmi.c+3−0

@@ -3460,6 +3460,9 @@ int ath11k_wmi_set_hw_mode(struct ath11k_base *ab, · 3459 unmodified lines
3460	len = sizeof(*cmd);	3460	len = sizeof(*cmd);
3461		3461
3462	skb = ath11k_wmi_alloc_skb(wmi_ab, len);	3462	skb = ath11k_wmi_alloc_skb(wmi_ab, len);
		3463	if (!skb)
		3464	return -ENOMEM;
		3465
3463	cmd = (struct wmi_pdev_set_hw_mode_cmd_param *)skb->data;	3466	cmd = (struct wmi_pdev_set_hw_mode_cmd_param *)skb->data;
3464		3467
3465	cmd->tlv_header = FIELD_PREP(WMI_TLV_TAG, WMI_TAG_PDEV_SET_HW_MODE_CMD) \|	3468	cmd->tlv_header = FIELD_PREP(WMI_TLV_TAG, WMI_TAG_PDEV_SET_HW_MODE_CMD) \|

drivers/net/wireless/ath/wil6210/Kconfig+1−0

@@ -2,6 +2,7 @@ · 1 unmodified line
2	config WIL6210	2	config WIL6210
3	tristate "Wilocity 60g WiFi card wil6210 support"	3	tristate "Wilocity 60g WiFi card wil6210 support"
4	select WANT_DEV_COREDUMP	4	select WANT_DEV_COREDUMP
		5	select CRC32
5	depends on CFG80211	6	depends on CFG80211
6	depends on PCI	7	depends on PCI
7	default n	8	default n

drivers/net/wireless/mediatek/mt76/mt7915/init.c+2−2

@@ -40,9 +40,9 @@ static const struct ieee80211_iface_limit if_limits[] = { · 39 unmodified lines
40	.types = BIT(NL80211_IFTYPE_ADHOC)	40	.types = BIT(NL80211_IFTYPE_ADHOC)
41	}, {	41	}, {
42	.max = 16,	42	.max = 16,
43	.types = BIT(NL80211_IFTYPE_AP) \|	43	.types = BIT(NL80211_IFTYPE_AP)
44	#ifdef CONFIG_MAC80211_MESH	44	#ifdef CONFIG_MAC80211_MESH
45	BIT(NL80211_IFTYPE_MESH_POINT)	45	\| BIT(NL80211_IFTYPE_MESH_POINT)
46	#endif	46	#endif
47	}, {	47	}, {
48	.max = MT7915_MAX_INTERFACES,	48	.max = MT7915_MAX_INTERFACES,

drivers/net/wireless/mediatek/mt76/sdio.c+7−12

 static int mt76s_process_tx_queue(struct mt76_dev *dev, struct mt76_queue *q)
 {
-	bool wake, mcu = q == dev->q_mcu[MT_MCUQ_WM];
 	struct mt76_queue_entry entry;
 	int nframes = 0;
+	bool mcu;
+	if (!q)
+		return 0;
+	mcu = q == dev->q_mcu[MT_MCUQ_WM];
 	while (q->queued > 0) {
 		if (!q->entry[q->tail].done)
 			break;
 		nframes++;
 	}
-	wake = q->stopped && q->queued < q->ndesc - 8;
-	if (wake)
-		q->stopped = false;
 	if (!q->queued)
 		wake_up(&dev->tx_wait);
-	if (mcu)
+	if (!mcu)
-		goto out;
+		mt76_txq_schedule(&dev->phy, q->qid);
-	mt76_txq_schedule(&dev->phy, q->qid);
-	if (wake)
-		ieee80211_wake_queue(dev->hw, q->qid);
-out:
 	return nframes;
 }

drivers/net/wireless/mediatek/mt76/usb.c+2−7

 	struct mt76_dev *dev = container_of(usb, struct mt76_dev, usb);
 	struct mt76_queue_entry entry;
 	struct mt76_queue *q;
-	bool wake;
 	int i;
 	for (i = 0; i < IEEE80211_NUM_ACS; i++) {
 		q = dev->phy.q_tx[i];
+		if (!q)
+			continue;
 		while (q->queued > 0) {
 			if (!q->entry[q->tail].done)
 			mt76_queue_tx_complete(dev, q, &entry);
 		}
-		wake = q->stopped && q->queued < q->ndesc - 8;
-		if (wake)
-			q->stopped = false;
 		if (!q->queued)
 			wake_up(&dev->tx_wait);
 		if (dev->drv->tx_status_data &&
 		    !test_and_set_bit(MT76_READING_STATS, &dev->phy.state))
 			queue_work(dev->wq, &dev->usb.stat_work);
-		if (wake)
-			ieee80211_wake_queue(dev->hw, i);
 	}
 }

drivers/net/wireless/realtek/rtlwifi/core.c+5−3

 	rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
 		"Firmware callback routine entered!\n");
-	complete(&rtlpriv->firmware_loading_complete);
 	if (!firmware) {
 		if (rtlpriv->cfg->alt_fw_name) {
 			err = request_firmware(&firmware,
 		}
 		pr_err("Selected firmware is not available\n");
 		rtlpriv->max_fw_size = 0;
-		return;
+		goto exit;
 	}
 found_alt:
 	if (firmware->size > rtlpriv->max_fw_size) {
 		pr_err("Firmware is too big!\n");
 		release_firmware(firmware);
-		return;
+		goto exit;
 	}
 	if (!is_wow) {
 		memcpy(rtlpriv->rtlhal.pfirmware, firmware->data,
 		rtlpriv->rtlhal.wowlan_fwsize = firmware->size;
 	}
 	release_firmware(firmware);
+exit:
+	complete(&rtlpriv->firmware_loading_complete);
 }
 void rtl_fw_cb(const struct firmware *firmware, void *context)

drivers/nvme/host/core.c+11−8

 }
 EXPORT_SYMBOL_GPL(nvme_reset_ctrl);
-int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl)
+static int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl)
 {
 	int ret;
 	return ret;
 }
-EXPORT_SYMBOL_GPL(nvme_reset_ctrl_sync);
 static void nvme_do_delete_ctrl(struct nvme_ctrl *ctrl)
 {
 		req->__sector = nvme_lba_to_sect(req->q->queuedata,
 			le64_to_cpu(nvme_req(req)->result.u64));
-	nvme_trace_bio_complete(req, status);
+	nvme_trace_bio_complete(req);
 	blk_mq_end_request(req, status);
 }
 }
 EXPORT_SYMBOL_GPL(nvme_alloc_request);
-struct request *nvme_alloc_request_qid(struct request_queue *q,
+static struct request *nvme_alloc_request_qid(struct request_queue *q,
 		struct nvme_command *cmd, blk_mq_req_flags_t flags, int qid)
 {
 	struct request *req;
 		nvme_init_request(req, cmd);
 	return req;
 }
-EXPORT_SYMBOL_GPL(nvme_alloc_request_qid);
 static int nvme_toggle_streams(struct nvme_ctrl *ctrl, bool enable)
 {
 	NULL,
 };
+static inline bool nvme_discovery_ctrl(struct nvme_ctrl *ctrl)
+{
+	return ctrl->opts && ctrl->opts->discovery_nqn;
+}
 static bool nvme_validate_cntlid(struct nvme_subsystem *subsys,
 		struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id)
 {
 		}
 		if ((id->cmic & NVME_CTRL_CMIC_MULTI_CTRL) ||
-		    (ctrl->opts && ctrl->opts->discovery_nqn))
+		    nvme_discovery_ctrl(ctrl))
 			continue;
 		dev_err(ctrl->device,
 			goto out_free;
 		}
-		if (!ctrl->opts->discovery_nqn && !ctrl->kas) {
+		if (!nvme_discovery_ctrl(ctrl) && !ctrl->kas) {
 			dev_err(ctrl->device,
 				"keep-alive support is mandatory for fabrics\n");
 			ret = -EINVAL;
 	if (ret < 0)
 		return ret;
-	if (!ctrl->identified) {
+	if (!ctrl->identified && !nvme_discovery_ctrl(ctrl)) {
 		ret = nvme_hwmon_init(ctrl);
 		if (ret < 0)
 			return ret;

drivers/nvme/host/fc.c+14−1

 	struct blk_mq_tag_set	admin_tag_set;
 	struct blk_mq_tag_set	tag_set;
+	struct work_struct	ioerr_work;
 	struct delayed_work	connect_work;
 	struct kref		ref;
 	}
 }
+static void
+nvme_fc_ctrl_ioerr_work(struct work_struct *work)
+{
+	struct nvme_fc_ctrl *ctrl =
+			container_of(work, struct nvme_fc_ctrl, ioerr_work);
+	nvme_fc_error_recovery(ctrl, "transport detected io error");
+}
 static void
 nvme_fc_fcpio_done(struct nvmefc_fcp_req *req)
 {
 check_error:
 	if (terminate_assoc)
-		nvme_fc_error_recovery(ctrl, "transport detected io error");
+		queue_work(nvme_reset_wq, &ctrl->ioerr_work);
 }
 static int
 {
 	struct nvme_fc_ctrl *ctrl = to_fc_ctrl(nctrl);
+	cancel_work_sync(&ctrl->ioerr_work);
 	cancel_delayed_work_sync(&ctrl->connect_work);
 	/*
 	 * kill the association on the link side.  this will block
 	INIT_WORK(&ctrl->ctrl.reset_work, nvme_fc_reset_ctrl_work);
 	INIT_DELAYED_WORK(&ctrl->connect_work, nvme_fc_connect_ctrl_work);
+	INIT_WORK(&ctrl->ioerr_work, nvme_fc_ctrl_ioerr_work);
 	spin_lock_init(&ctrl->lock);
 	/* io queue count */
 fail_ctrl:
 	nvme_change_ctrl_state(&ctrl->ctrl, NVME_CTRL_DELETING);
+	cancel_work_sync(&ctrl->ioerr_work);
 	cancel_work_sync(&ctrl->ctrl.reset_work);
 	cancel_delayed_work_sync(&ctrl->connect_work);

drivers/nvme/host/nvme.h+2−7

 #define NVME_QID_ANY -1
 struct request *nvme_alloc_request(struct request_queue *q,
 		struct nvme_command *cmd, blk_mq_req_flags_t flags);
-struct request *nvme_alloc_request_qid(struct request_queue *q,
-		struct nvme_command *cmd, blk_mq_req_flags_t flags, int qid);
 void nvme_cleanup_cmd(struct request *req);
 blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req,
 		struct nvme_command *cmd);
 int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count);
 void nvme_stop_keep_alive(struct nvme_ctrl *ctrl);
 int nvme_reset_ctrl(struct nvme_ctrl *ctrl);
-int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl);
 int nvme_try_sched_reset(struct nvme_ctrl *ctrl);
 int nvme_delete_ctrl(struct nvme_ctrl *ctrl);
 		kblockd_schedule_work(&head->requeue_work);
 }
-static inline void nvme_trace_bio_complete(struct request *req,
+static inline void nvme_trace_bio_complete(struct request *req)
-        blk_status_t status)
 {
 	struct nvme_ns *ns = req->q->queuedata;
 static inline void nvme_mpath_check_last_path(struct nvme_ns *ns)
 {
 }
-static inline void nvme_trace_bio_complete(struct request *req,
+static inline void nvme_trace_bio_complete(struct request *req)
-        blk_status_t status)
 {
 }
 static inline int nvme_mpath_init(struct nvme_ctrl *ctrl,

drivers/nvme/host/pci.c+6−4

 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
 {
 	struct nvme_completion *cqe = &nvmeq->cqes[idx];
+	__u16 command_id = READ_ONCE(cqe->command_id);
 	struct request *req;
 	/*
 	 * aborts.  We don't even bother to allocate a struct request
 	 * for them but rather special case them here.
 	 */
-	if (unlikely(nvme_is_aen_req(nvmeq->qid, cqe->command_id))) {
+	if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
 		nvme_complete_async_event(&nvmeq->dev->ctrl,
 				cqe->status, &cqe->result);
 		return;
 	}
-	req = blk_mq_tag_to_rq(nvme_queue_tagset(nvmeq), cqe->command_id);
+	req = blk_mq_tag_to_rq(nvme_queue_tagset(nvmeq), command_id);
 	if (unlikely(!req)) {
 		dev_warn(nvmeq->dev->ctrl.device,
 			"invalid id %d completed on queue %d\n",
-			cqe->command_id, le16_to_cpu(cqe->sq_id));
+			command_id, le16_to_cpu(cqe->sq_id));
 		return;
 	}
 	{ PCI_DEVICE(0x144d, 0xa821),   /* Samsung PM1725 */
 		.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
 	{ PCI_DEVICE(0x144d, 0xa822),   /* Samsung PM1725a */
-		.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
+		.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
+				NVME_QUIRK_IGNORE_DEV_SUBNQN, },
 	{ PCI_DEVICE(0x1d1d, 0x1f1f),	/* LighNVM qemu device */
 		.driver_data = NVME_QUIRK_LIGHTNVM, },
 	{ PCI_DEVICE(0x1d1d, 0x2807),	/* CNEX WL */

drivers/nvme/host/tcp.c+13−3

 static inline size_t nvme_tcp_req_cur_length(struct nvme_tcp_request *req)
 {
-	return min_t(size_t, req->iter.bvec->bv_len - req->iter.iov_offset,
+	return min_t(size_t, iov_iter_single_seg_count(&req->iter),
 			req->pdu_len - req->pdu_sent);
 }
 	}
 }
+static inline void nvme_tcp_send_all(struct nvme_tcp_queue *queue)
+{
+	int ret;
+	/* drain the send queue as much as we can... */
+	do {
+		ret = nvme_tcp_try_send(queue);
+	} while (ret > 0);
+}
 static inline void nvme_tcp_queue_request(struct nvme_tcp_request *req,
 		bool sync, bool last)
 {
 	 * directly, otherwise queue io_work. Also, only do that if we
 	 * are on the same cpu, so we don't introduce contention.
 	 */
-	if (queue->io_cpu == smp_processor_id() &&
+	if (queue->io_cpu == __smp_processor_id() &&
 	    sync && empty && mutex_trylock(&queue->send_mutex)) {
 		queue->more_requests = !last;
-		nvme_tcp_try_send(queue);
+		nvme_tcp_send_all(queue);
 		queue->more_requests = false;
 		mutex_unlock(&queue->send_mutex);
 	} else if (last) {

drivers/nvme/target/fcloop.c+4−3

 fcloop_set_cmd_drop(struct device *dev, struct device_attribute *attr,
 		const char *buf, size_t count)
 {
-	int opcode, starting, amount;
+	unsigned int opcode;
+	int starting, amount;
 	if (sscanf(buf, "%x:%d:%d", &opcode, &starting, &amount) != 3)
 		return -EBADRQC;
 static void __exit fcloop_exit(void)
 {
-	struct fcloop_lport *lport;
+	struct fcloop_lport *lport = NULL;
-	struct fcloop_nport *nport;
+	struct fcloop_nport *nport = NULL;
 	struct fcloop_tport *tport;
 	struct fcloop_rport *rport;
 	unsigned long flags;

drivers/nvme/target/rdma.c+18−8

 	}
 	ndev->inline_data_size = nport->inline_data_size;
 	ndev->inline_page_count = inline_page_count;
+	if (nport->pi_enable && !(cm_id->device->attrs.device_cap_flags &
+				  IB_DEVICE_INTEGRITY_HANDOVER)) {
+		pr_warn("T10-PI is not supported by device %s. Disabling it\n",
+			cm_id->device->name);
+		nport->pi_enable = false;
+	}
 	ndev->device = cm_id->device;
 	kref_init(&ndev->ref);
 	spin_lock_irqsave(&queue->state_lock, flags);
 	switch (queue->state) {
 	case NVMET_RDMA_Q_CONNECTING:
+		while (!list_empty(&queue->rsp_wait_list)) {
+			struct nvmet_rdma_rsp *rsp;
+			rsp = list_first_entry(&queue->rsp_wait_list,
+					       struct nvmet_rdma_rsp,
+					       wait_list);
+			list_del(&rsp->wait_list);
+			nvmet_rdma_put_rsp(rsp);
+		}
+		fallthrough;
 	case NVMET_RDMA_Q_LIVE:
 		queue->state = NVMET_RDMA_Q_DISCONNECTING;
 		disconnect = true;
 		goto out_destroy_id;
 	}
-	if (port->nport->pi_enable &&
-	    !(cm_id->device->attrs.device_cap_flags &
-	      IB_DEVICE_INTEGRITY_HANDOVER)) {
-		pr_err("T10-PI is not supported for %pISpcs\n", addr);
-		ret = -EINVAL;
-		goto out_destroy_id;
-	}
 	port->cm_id = cm_id;
 	return 0;

drivers/opp/core.c+7−2

 	if (IS_ERR(opp_table->clk)) {
 		ret = PTR_ERR(opp_table->clk);
 		if (ret == -EPROBE_DEFER)
-			goto err;
+			goto remove_opp_dev;
 		dev_dbg(dev, "%s: Couldn't find clock: %d\n", __func__, ret);
 	}
 	ret = dev_pm_opp_of_find_icc_paths(dev, opp_table);
 	if (ret) {
 		if (ret == -EPROBE_DEFER)
-			goto err;
+			goto put_clk;
 		dev_warn(dev, "%s: Error finding interconnect paths: %d\n",
 			 __func__, ret);
 	return opp_table;
+put_clk:
+	if (!IS_ERR(opp_table->clk))
+		clk_put(opp_table->clk);
+remove_opp_dev:
+	_remove_opp_dev(opp_dev, opp_table);
 err:
 	kfree(opp_table);
 	return ERR_PTR(ret);

drivers/perf/arm_pmu.c+0−5

 	return per_cpu(hw_events->irq, cpu);
 }
-bool arm_pmu_irq_is_nmi(void)
-{
-	return has_nmi;
-}
 /*
  * PMU hardware loses all context when a CPU goes offline.
  * When a CPU is hotplugged back in, since some hardware registers are

drivers/ptp/Kconfig+2−0

 	depends on NETWORK_PHY_TIMESTAMPING
 	depends on PHYLIB
 	depends on PTP_1588_CLOCK
+	select CRC32
 	help
 	  Supports the DP83640 PHYTER with IEEE 1588 features.
 config PTP_1588_CLOCK_INES
 	tristate "ZHAW InES PTP time stamping IP core"
 	depends on NETWORK_PHY_TIMESTAMPING
+	depends on HAS_IOMEM
 	depends on PHYLIB
 	depends on PTP_1588_CLOCK
 	help

drivers/regulator/Kconfig+1−0

@@ -881,6 +881,7 @@ config REGULATOR_QCOM_RPM · 880 unmodified lines
881	config REGULATOR_QCOM_RPMH	881	config REGULATOR_QCOM_RPMH
882	tristate "Qualcomm Technologies, Inc. RPMh regulator driver"	882	tristate "Qualcomm Technologies, Inc. RPMh regulator driver"
883	depends on QCOM_RPMH \|\| (QCOM_RPMH=n && COMPILE_TEST)	883	depends on QCOM_RPMH \|\| (QCOM_RPMH=n && COMPILE_TEST)
		884	depends on QCOM_COMMAND_DB \|\| (QCOM_COMMAND_DB=n && COMPILE_TEST)
884	help	885	help
885	This driver supports control of PMIC regulators via the RPMh hardware	886	This driver supports control of PMIC regulators via the RPMh hardware
886	block found on Qualcomm Technologies Inc. SoCs. RPMh regulator	887	block found on Qualcomm Technologies Inc. SoCs. RPMh regulator

drivers/regulator/bd718x7-regulator.c+57−0

 #include <linux/regulator/of_regulator.h>
 #include <linux/slab.h>
+/* Typical regulator startup times as per data sheet in uS */
+#define BD71847_BUCK1_STARTUP_TIME 144
+#define BD71847_BUCK2_STARTUP_TIME 162
+#define BD71847_BUCK3_STARTUP_TIME 162
+#define BD71847_BUCK4_STARTUP_TIME 240
+#define BD71847_BUCK5_STARTUP_TIME 270
+#define BD71847_BUCK6_STARTUP_TIME 200
+#define BD71847_LDO1_STARTUP_TIME  440
+#define BD71847_LDO2_STARTUP_TIME  370
+#define BD71847_LDO3_STARTUP_TIME  310
+#define BD71847_LDO4_STARTUP_TIME  400
+#define BD71847_LDO5_STARTUP_TIME  530
+#define BD71847_LDO6_STARTUP_TIME  400
+#define BD71837_BUCK1_STARTUP_TIME 160
+#define BD71837_BUCK2_STARTUP_TIME 180
+#define BD71837_BUCK3_STARTUP_TIME 180
+#define BD71837_BUCK4_STARTUP_TIME 180
+#define BD71837_BUCK5_STARTUP_TIME 160
+#define BD71837_BUCK6_STARTUP_TIME 240
+#define BD71837_BUCK7_STARTUP_TIME 220
+#define BD71837_BUCK8_STARTUP_TIME 200
+#define BD71837_LDO1_STARTUP_TIME  440
+#define BD71837_LDO2_STARTUP_TIME  370
+#define BD71837_LDO3_STARTUP_TIME  310
+#define BD71837_LDO4_STARTUP_TIME  400
+#define BD71837_LDO5_STARTUP_TIME  310
+#define BD71837_LDO6_STARTUP_TIME  400
+#define BD71837_LDO7_STARTUP_TIME  530
 /*
  * BD718(37/47/50) have two "enable control modes". ON/OFF can either be
  * controlled by software - or by PMIC internal HW state machine. Whether
 			.vsel_mask = DVS_BUCK_RUN_MASK,
 			.enable_reg = BD718XX_REG_BUCK1_CTRL,
 			.enable_mask = BD718XX_BUCK_EN,
+			.enable_time = BD71847_BUCK1_STARTUP_TIME,
 			.owner = THIS_MODULE,
 			.of_parse_cb = buck_set_hw_dvs_levels,
 		},
 			.vsel_mask = DVS_BUCK_RUN_MASK,
 			.enable_reg = BD718XX_REG_BUCK2_CTRL,
 			.enable_mask = BD718XX_BUCK_EN,
+			.enable_time = BD71847_BUCK2_STARTUP_TIME,
 			.owner = THIS_MODULE,
 			.of_parse_cb = buck_set_hw_dvs_levels,
 		},
 			.linear_range_selectors = bd71847_buck3_volt_range_sel,
 			.enable_reg = BD718XX_REG_1ST_NODVS_BUCK_CTRL,
 			.enable_mask = BD718XX_BUCK_EN,
+			.enable_time = BD71847_BUCK3_STARTUP_TIME,
 			.owner = THIS_MODULE,
 		},
 		.init = {
 			.vsel_range_mask = BD71847_BUCK4_RANGE_MASK,
 			.linear_range_selectors = bd71847_buck4_volt_range_sel,
 			.enable_mask = BD718XX_BUCK_EN,
+			.enable_time = BD71847_BUCK4_STARTUP_TIME,
 			.owner = THIS_MODULE,
 		},
 		.init = {
 			.vsel_mask = BD718XX_3RD_NODVS_BUCK_MASK,
 			.enable_reg = BD718XX_REG_3RD_NODVS_BUCK_CTRL,
 			.enable_mask = BD718XX_BUCK_EN,
+			.enable_time = BD71847_BUCK5_STARTUP_TIME,
 			.owner = THIS_MODULE,
 		},
 		.init = {
 			.vsel_mask = BD718XX_4TH_NODVS_BUCK_MASK,
 			.enable_reg = BD718XX_REG_4TH_NODVS_BUCK_CTRL,
 			.enable_mask = BD718XX_BUCK_EN,
+			.enable_time = BD71847_BUCK6_STARTUP_TIME,
 			.owner = THIS_MODULE,
 		},
 		.init = {
 			.linear_range_selectors = bd718xx_ldo1_volt_range_sel,
 			.enable_reg = BD718XX_REG_LDO1_VOLT,
 			.enable_mask = BD718XX_LDO_EN,
+			.enable_time = BD71847_LDO1_STARTUP_TIME,
 			.owner = THIS_MODULE,
 		},
 		.init = {
 			.n_voltages = ARRAY_SIZE(ldo_2_volts),
 			.enable_reg = BD718XX_REG_LDO2_VOLT,
 			.enable_mask = BD718XX_LDO_EN,
+			.enable_time = BD71847_LDO2_STARTUP_TIME,
 			.owner = THIS_MODULE,
 		},
 		.init = {
 			.vsel_mask = BD718XX_LDO3_MASK,
 			.enable_reg = BD718XX_REG_LDO3_VOLT,
 			.enable_mask = BD718XX_LDO_EN,
+			.enable_time = BD71847_LDO3_STARTUP_TIME,
 			.owner = THIS_MODULE,
 		},
 		.init = {
 			.vsel_mask = BD718XX_LDO4_MASK,
 			.enable_reg = BD718XX_REG_LDO4_VOLT,
 			.enable_mask = BD718XX_LDO_EN,
+			.enable_time = BD71847_LDO4_STARTUP_TIME,
 			.owner = THIS_MODULE,
 		},
 		.init = {
 			.linear_range_selectors = bd71847_ldo5_volt_range_sel,
 			.enable_reg = BD718XX_REG_LDO5_VOLT,
 			.enable_mask = BD718XX_LDO_EN,
+			.enable_time = BD71847_LDO5_STARTUP_TIME,
 			.owner = THIS_MODULE,
 		},
 		.init = {
 			.vsel_mask = BD718XX_LDO6_MASK,
 			.enable_reg = BD718XX_REG_LDO6_VOLT,
 			.enable_mask = BD718XX_LDO_EN,
+			.enable_time = BD71847_LDO6_STARTUP_TIME,
 			.owner = THIS_MODULE,
 		},
 		.init = {
 			.vsel_mask = DVS_BUCK_RUN_MASK,
 			.enable_reg = BD718XX_REG_BUCK1_CTRL,
 			.enable_mask = BD718XX_BUCK_EN,
+			.enable_time = BD71837_BUCK1_STARTUP_TIME,
 			.owner = THIS_MODULE,
 			.of_parse_cb = buck_set_hw_dvs_levels,
 		},
 			.vsel_mask = DVS_BUCK_RUN_MASK,
 			.enable_reg = BD718XX_REG_BUCK2_CTRL,
 			.enable_mask = BD718XX_BUCK_EN,
+			.enable_time = BD71837_BUCK2_STARTUP_TIME,
 			.owner = THIS_MODULE,
 			.of_parse_cb = buck_set_hw_dvs_levels,
 		},
 			.vsel_mask = DVS_BUCK_RUN_MASK,
 			.enable_reg = BD71837_REG_BUCK3_CTRL,
 			.enable_mask = BD718XX_BUCK_EN,
+			.enable_time = BD71837_BUCK3_STARTUP_TIME,
 			.owner = THIS_MODULE,
 			.of_parse_cb = buck_set_hw_dvs_levels,
 		},
 			.vsel_mask = DVS_BUCK_RUN_MASK,
 			.enable_reg = BD71837_REG_BUCK4_CTRL,
 			.enable_mask = BD718XX_BUCK_EN,
+			.enable_time = BD71837_BUCK4_STARTUP_TIME,
 			.owner = THIS_MODULE,
 			.of_parse_cb = buck_set_hw_dvs_levels,
 		},
 			.linear_range_selectors = bd71837_buck5_volt_range_sel,
 			.enable_reg = BD718XX_REG_1ST_NODVS_BUCK_CTRL,
 			.enable_mask = BD718XX_BUCK_EN,
+			.enable_time = BD71837_BUCK5_STARTUP_TIME,
 			.owner = THIS_MODULE,
 		},
 		.init = {
 			.vsel_mask = BD71837_BUCK6_MASK,
 			.enable_reg = BD718XX_REG_2ND_NODVS_BUCK_CTRL,
 			.enable_mask = BD718XX_BUCK_EN,
+			.enable_time = BD71837_BUCK6_STARTUP_TIME,
 			.owner = THIS_MODULE,
 		},
 		.init = {
 			.vsel_mask = BD718XX_3RD_NODVS_BUCK_MASK,
 			.enable_reg = BD718XX_REG_3RD_NODVS_BUCK_CTRL,
 			.enable_mask = BD718XX_BUCK_EN,
+			.enable_time = BD71837_BUCK7_STARTUP_TIME,
 			.owner = THIS_MODULE,
 		},
 		.init = {
 			.vsel_mask = BD718XX_4TH_NODVS_BUCK_MASK,
 			.enable_reg = BD718XX_REG_4TH_NODVS_BUCK_CTRL,
 			.enable_mask = BD718XX_BUCK_EN,
+			.enable_time = BD71837_BUCK8_STARTUP_TIME,
 			.owner = THIS_MODULE,
 		},
 		.init = {
 			.linear_range_selectors = bd718xx_ldo1_volt_range_sel,
 			.enable_reg = BD718XX_REG_LDO1_VOLT,
 			.enable_mask = BD718XX_LDO_EN,
+			.enable_time = BD71837_LDO1_STARTUP_TIME,
 			.owner = THIS_MODULE,
 		},
 		.init = {
 			.n_voltages = ARRAY_SIZE(ldo_2_volts),
 			.enable_reg = BD718XX_REG_LDO2_VOLT,
 			.enable_mask = BD718XX_LDO_EN,
+			.enable_time = BD71837_LDO2_STARTUP_TIME,
 			.owner = THIS_MODULE,
 		},
 		.init = {
 			.vsel_mask = BD718XX_LDO3_MASK,
 			.enable_reg = BD718XX_REG_LDO3_VOLT,
 			.enable_mask = BD718XX_LDO_EN,
+			.enable_time = BD71837_LDO3_STARTUP_TIME,
 			.owner = THIS_MODULE,
 		},
 		.init = {
 			.vsel_mask = BD718XX_LDO4_MASK,
 			.enable_reg = BD718XX_REG_LDO4_VOLT,
 			.enable_mask = BD718XX_LDO_EN,
+			.enable_time = BD71837_LDO4_STARTUP_TIME,
 			.owner = THIS_MODULE,
 		},
 		.init = {
 			.vsel_mask = BD71837_LDO5_MASK,
 			.enable_reg = BD718XX_REG_LDO5_VOLT,
 			.enable_mask = BD718XX_LDO_EN,
+			.enable_time = BD71837_LDO5_STARTUP_TIME,
 			.owner = THIS_MODULE,
 		},
 		.init = {
 			.vsel_mask = BD718XX_LDO6_MASK,
 			.enable_reg = BD718XX_REG_LDO6_VOLT,
 			.enable_mask = BD718XX_LDO_EN,
+			.enable_time = BD71837_LDO6_STARTUP_TIME,
 			.owner = THIS_MODULE,
 		},
 		.init = {
 			.vsel_mask = BD71837_LDO7_MASK,
 			.enable_reg = BD71837_REG_LDO7_VOLT,
 			.enable_mask = BD718XX_LDO_EN,
+			.enable_time = BD71837_LDO7_STARTUP_TIME,
 			.owner = THIS_MODULE,
 		},
 		.init = {

drivers/regulator/pf8x00-regulator.c+6−2

 }
 static const struct of_device_id pf8x00_dt_ids[] = {
-	{ .compatible = "nxp,pf8x00",},
+	{ .compatible = "nxp,pf8100",},
+	{ .compatible = "nxp,pf8121a",},
+	{ .compatible = "nxp,pf8200",},
 	{ }
 };
 MODULE_DEVICE_TABLE(of, pf8x00_dt_ids);
 static const struct i2c_device_id pf8x00_i2c_id[] = {
-	{ "pf8x00", 0 },
+	{ "pf8100", 0 },
+	{ "pf8121a", 0 },
+	{ "pf8200", 0 },
 	{},
 };
 MODULE_DEVICE_TABLE(i2c, pf8x00_i2c_id);

drivers/regulator/qcom-rpmh-regulator.c+1−1

@@ -726,7 +726,7 @@ static const struct rpmh_vreg_hw_data pmic5_ftsmps510 = { · 725 unmodified lines
726	static const struct rpmh_vreg_hw_data pmic5_hfsmps515 = {	726	static const struct rpmh_vreg_hw_data pmic5_hfsmps515 = {
727	.regulator_type = VRM,	727	.regulator_type = VRM,
728	.ops = &rpmh_regulator_vrm_ops,	728	.ops = &rpmh_regulator_vrm_ops,
729	.voltage_range = REGULATOR_LINEAR_RANGE(2800000, 0, 4, 1600),	729	.voltage_range = REGULATOR_LINEAR_RANGE(2800000, 0, 4, 16000),
730	.n_voltages = 5,	730	.n_voltages = 5,
731	.pmic_mode_map = pmic_mode_map_pmic5_smps,	731	.pmic_mode_map = pmic_mode_map_pmic5_smps,
732	.of_map_mode = rpmh_regulator_pmic4_smps_of_map_mode,	732	.of_map_mode = rpmh_regulator_pmic4_smps_of_map_mode,

drivers/s390/net/qeth_core.h+2−1

@@ -1079,7 +1079,8 @@ struct qeth_card qeth_get_card_by_busid(char bus_id); · 1078 unmodified lines
1079	void qeth_set_allowed_threads(struct qeth_card *card, unsigned long threads,	1079	void qeth_set_allowed_threads(struct qeth_card *card, unsigned long threads,
1080	int clear_start_mask);	1080	int clear_start_mask);
1081	int qeth_threads_running(struct qeth_card *, unsigned long);	1081	int qeth_threads_running(struct qeth_card *, unsigned long);
1082	int qeth_set_offline(struct qeth_card *card, bool resetting);	1082	int qeth_set_offline(struct qeth_card card, const struct qeth_discipline disc,
		1083	bool resetting);
1083		1084
1084	int qeth_send_ipa_cmd(struct qeth_card , struct qeth_cmd_buffer ,	1085	int qeth_send_ipa_cmd(struct qeth_card , struct qeth_cmd_buffer ,
1085	int (*reply_cb)	1086	int (*reply_cb)

drivers/s390/net/qeth_core_main.c+25−13

 	return rc;
 }
-static int qeth_set_online(struct qeth_card *card)
+static int qeth_set_online(struct qeth_card *card,
+			   const struct qeth_discipline *disc)
 {
 	bool carrier_ok;
 	int rc;
-	mutex_lock(&card->discipline_mutex);
 	mutex_lock(&card->conf_mutex);
 	QETH_CARD_TEXT(card, 2, "setonlin");
 		/* no need for locking / error handling at this early stage: */
 		qeth_set_real_num_tx_queues(card, qeth_tx_actual_queues(card));
-	rc = card->discipline->set_online(card, carrier_ok);
+	rc = disc->set_online(card, carrier_ok);
 	if (rc)
 		goto err_online;
 	kobject_uevent(&card->gdev->dev.kobj, KOBJ_CHANGE);
 	mutex_unlock(&card->conf_mutex);
-	mutex_unlock(&card->discipline_mutex);
 	return 0;
 err_online:
 	qdio_free(CARD_DDEV(card));
 	mutex_unlock(&card->conf_mutex);
-	mutex_unlock(&card->discipline_mutex);
 	return rc;
 }
-int qeth_set_offline(struct qeth_card *card, bool resetting)
+int qeth_set_offline(struct qeth_card *card, const struct qeth_discipline *disc,
+		     bool resetting)
 {
 	int rc, rc2, rc3;
-	mutex_lock(&card->discipline_mutex);
 	mutex_lock(&card->conf_mutex);
 	QETH_CARD_TEXT(card, 3, "setoffl");
 	cancel_work_sync(&card->rx_mode_work);
-	card->discipline->set_offline(card);
+	disc->set_offline(card);
 	qeth_qdio_clear_card(card, 0);
 	qeth_drain_output_queues(card);
 	kobject_uevent(&card->gdev->dev.kobj, KOBJ_CHANGE);
 	mutex_unlock(&card->conf_mutex);
-	mutex_unlock(&card->discipline_mutex);
 	return 0;
 }
 EXPORT_SYMBOL_GPL(qeth_set_offline);
 static int qeth_do_reset(void *data)
 {
+	const struct qeth_discipline *disc;
 	struct qeth_card *card = data;
 	int rc;
+	/* Lock-free, other users will block until we are done. */
+	disc = card->discipline;
 	QETH_CARD_TEXT(card, 2, "recover1");
 	if (!qeth_do_run_thread(card, QETH_RECOVER_THREAD))
 		return 0;
 	dev_warn(&card->gdev->dev,
 		 "A recovery process has been started for the device\n");
-	qeth_set_offline(card, true);
+	qeth_set_offline(card, disc, true);
-	rc = qeth_set_online(card);
+	rc = qeth_set_online(card, disc);
 	if (!rc) {
 		dev_info(&card->gdev->dev,
 			 "Device successfully recovered!\n");
 		break;
 	default:
 		card->info.layer_enforced = true;
+		/* It's so early that we don't need the discipline_mutex yet. */
 		rc = qeth_core_load_discipline(card, enforced_disc);
 		if (rc)
 			goto err_load;
 	QETH_CARD_TEXT(card, 2, "removedv");
+	mutex_lock(&card->discipline_mutex);
 	if (card->discipline) {
 		card->discipline->remove(gdev);
 		qeth_core_free_discipline(card);
 	}
+	mutex_unlock(&card->discipline_mutex);
 	qeth_free_qdio_queues(card);
 	int rc = 0;
 	enum qeth_discipline_id def_discipline;
+	mutex_lock(&card->discipline_mutex);
 	if (!card->discipline) {
 		def_discipline = IS_IQD(card) ? QETH_DISCIPLINE_LAYER3 :
 						QETH_DISCIPLINE_LAYER2;
 		}
 	}
-	rc = qeth_set_online(card);
+	rc = qeth_set_online(card, card->discipline);
 err:
+	mutex_unlock(&card->discipline_mutex);
 	return rc;
 }
 static int qeth_core_set_offline(struct ccwgroup_device *gdev)
 {
 	struct qeth_card *card = dev_get_drvdata(&gdev->dev);
+	int rc;
-	return qeth_set_offline(card, false);
+	mutex_lock(&card->discipline_mutex);
+	rc = qeth_set_offline(card, card->discipline, false);
+	mutex_unlock(&card->discipline_mutex);
+	return rc;
 }
 static void qeth_core_shutdown(struct ccwgroup_device *gdev)

drivers/s390/net/qeth_l2_main.c+1−1

@@ -2208,7 +2208,7 @@ static void qeth_l2_remove_device(struct ccwgroup_device *gdev) · 2207 unmodified lines
2208	wait_event(card->wait_q, qeth_threads_running(card, 0xffffffff) == 0);	2208	wait_event(card->wait_q, qeth_threads_running(card, 0xffffffff) == 0);
2209		2209
2210	if (gdev->state == CCWGROUP_ONLINE)	2210	if (gdev->state == CCWGROUP_ONLINE)
2211	qeth_set_offline(card, false);	2211	qeth_set_offline(card, card->discipline, false);
2212		2212
2213	cancel_work_sync(&card->close_dev_work);	2213	cancel_work_sync(&card->close_dev_work);
2214	if (card->dev->reg_state == NETREG_REGISTERED)	2214	if (card->dev->reg_state == NETREG_REGISTERED)

drivers/s390/net/qeth_l3_main.c+2−2

@@ -1813,7 +1813,7 @@ static netdev_features_t qeth_l3_osa_features_check(struct sk_buff *skb, · 1812 unmodified lines
1813	struct net_device *dev,	1813	struct net_device *dev,
1814	netdev_features_t features)	1814	netdev_features_t features)
1815	{	1815	{
1816	if (qeth_get_ip_version(skb) != 4)	1816	if (vlan_get_protocol(skb) != htons(ETH_P_IP))
1817	features &= ~NETIF_F_HW_VLAN_CTAG_TX;	1817	features &= ~NETIF_F_HW_VLAN_CTAG_TX;
1818	return qeth_features_check(skb, dev, features);	1818	return qeth_features_check(skb, dev, features);
1819	}	1819	}
@@ -1971,7 +1971,7 @@ static void qeth_l3_remove_device(struct ccwgroup_device *cgdev) · 151 unmodified lines
1971	wait_event(card->wait_q, qeth_threads_running(card, 0xffffffff) == 0);	1971	wait_event(card->wait_q, qeth_threads_running(card, 0xffffffff) == 0);
1972		1972
1973	if (cgdev->state == CCWGROUP_ONLINE)	1973	if (cgdev->state == CCWGROUP_ONLINE)
1974	qeth_set_offline(card, false);	1974	qeth_set_offline(card, card->discipline, false);
1975		1975
1976	cancel_work_sync(&card->close_dev_work);	1976	cancel_work_sync(&card->close_dev_work);
1977	if (card->dev->reg_state == NETREG_REGISTERED)	1977	if (card->dev->reg_state == NETREG_REGISTERED)

drivers/scsi/cxgbi/cxgb4i/Kconfig+1−0

@@ -4,6 +4,7 @@ config SCSI_CXGB4_ISCSI · 3 unmodified lines
4	depends on PCI && INET && (IPV6 \|\| IPV6=n)	4	depends on PCI && INET && (IPV6 \|\| IPV6=n)
5	depends on THERMAL \|\| !THERMAL	5	depends on THERMAL \|\| !THERMAL
6	depends on ETHERNET	6	depends on ETHERNET
		7	depends on TLS \|\| TLS=n
7	select NET_VENDOR_CHELSIO	8	select NET_VENDOR_CHELSIO
8	select CHELSIO_T4	9	select CHELSIO_T4
9	select CHELSIO_LIB	10	select CHELSIO_LIB

drivers/scsi/hisi_sas/hisi_sas.h+4−0

 #include <linux/debugfs.h>
 #include <linux/dmapool.h>
 #include <linux/iopoll.h>
+#include <linux/irq.h>
 #include <linux/lcm.h>
 #include <linux/libata.h>
 #include <linux/mfd/syscon.h>
 struct hisi_sas_hw {
 	int (*hw_init)(struct hisi_hba *hisi_hba);
+	int (*interrupt_preinit)(struct hisi_hba *hisi_hba);
 	void (*setup_itct)(struct hisi_hba *hisi_hba,
 			   struct hisi_sas_device *device);
 	int (*slot_index_alloc)(struct hisi_hba *hisi_hba,
 	u32 refclk_frequency_mhz;
 	u8 sas_addr[SAS_ADDR_SIZE];
+	int *irq_map; /* v2 hw */
 	int n_phy;
 	spinlock_t lock;
 	struct semaphore sem;

drivers/scsi/hisi_sas/hisi_sas_main.c+11−0

 	return NULL;
 }
+static int hisi_sas_interrupt_preinit(struct hisi_hba *hisi_hba)
+{
+	if (hisi_hba->hw->interrupt_preinit)
+		return hisi_hba->hw->interrupt_preinit(hisi_hba);
+	return 0;
+}
 int hisi_sas_probe(struct platform_device *pdev,
 		   const struct hisi_sas_hw *hw)
 {
 		sha->sas_port[i] = &hisi_hba->port[i].sas_port;
 	}
+	rc = hisi_sas_interrupt_preinit(hisi_hba);
+	if (rc)
+		goto err_out_ha;
 	rc = scsi_add_host(shost, &pdev->dev);
 	if (rc)
 		goto err_out_ha;

drivers/scsi/hisi_sas/hisi_sas_v2_hw.c+53−13

 	fatal_axi_int_v2_hw
 };
+#define CQ0_IRQ_INDEX (96)
+static int hisi_sas_v2_interrupt_preinit(struct hisi_hba *hisi_hba)
+{
+	struct platform_device *pdev = hisi_hba->platform_dev;
+	struct Scsi_Host *shost = hisi_hba->shost;
+	struct irq_affinity desc = {
+		.pre_vectors = CQ0_IRQ_INDEX,
+		.post_vectors = 16,
+	};
+	int resv = desc.pre_vectors + desc.post_vectors, minvec = resv + 1, nvec;
+	nvec = devm_platform_get_irqs_affinity(pdev, &desc, minvec, 128,
+					       &hisi_hba->irq_map);
+	if (nvec < 0)
+		return nvec;
+	shost->nr_hw_queues = hisi_hba->cq_nvecs = nvec - resv;
+	return 0;
+}
 /*
  * There is a limitation in the hip06 chipset that we need
  * to map in all mbigen interrupts, even if they are not used.
 {
 	struct platform_device *pdev = hisi_hba->platform_dev;
 	struct device *dev = &pdev->dev;
-	int irq, rc = 0, irq_map[128];
+	int irq, rc = 0;
 	int i, phy_no, fatal_no, queue_no;
-	for (i = 0; i < 128; i++)
-		irq_map[i] = platform_get_irq(pdev, i);
 	for (i = 0; i < HISI_SAS_PHY_INT_NR; i++) {
-		irq = irq_map[i + 1]; /* Phy up/down is irq1 */
+		irq = hisi_hba->irq_map[i + 1]; /* Phy up/down is irq1 */
 		rc = devm_request_irq(dev, irq, phy_interrupts[i], 0,
 				      DRV_NAME " phy", hisi_hba);
 		if (rc) {
 	for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
 		struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
-		irq = irq_map[phy_no + 72];
+		irq = hisi_hba->irq_map[phy_no + 72];
 		rc = devm_request_irq(dev, irq, sata_int_v2_hw, 0,
 				      DRV_NAME " sata", phy);
 		if (rc) {
 	}
 	for (fatal_no = 0; fatal_no < HISI_SAS_FATAL_INT_NR; fatal_no++) {
-		irq = irq_map[fatal_no + 81];
+		irq = hisi_hba->irq_map[fatal_no + 81];
 		rc = devm_request_irq(dev, irq, fatal_interrupts[fatal_no], 0,
 				      DRV_NAME " fatal", hisi_hba);
 		if (rc) {
 		}
 	}
-	for (queue_no = 0; queue_no < hisi_hba->queue_count; queue_no++) {
+	for (queue_no = 0; queue_no < hisi_hba->cq_nvecs; queue_no++) {
 		struct hisi_sas_cq *cq = &hisi_hba->cq[queue_no];
-		cq->irq_no = irq_map[queue_no + 96];
+		cq->irq_no = hisi_hba->irq_map[queue_no + 96];
 		rc = devm_request_threaded_irq(dev, cq->irq_no,
 					       cq_interrupt_v2_hw,
 					       cq_thread_v2_hw, IRQF_ONESHOT,
 					       DRV_NAME " cq", cq);
 		if (rc) {
 			dev_err(dev, "irq init: could not request cq interrupt %d, rc=%d\n",
-				irq, rc);
+					cq->irq_no, rc);
 			rc = -ENOENT;
 			goto err_out;
 		}
+		cq->irq_mask = irq_get_affinity_mask(cq->irq_no);
 	}
-	hisi_hba->cq_nvecs = hisi_hba->queue_count;
 err_out:
 	return rc;
 }
 	NULL
 };
+static int map_queues_v2_hw(struct Scsi_Host *shost)
+{
+	struct hisi_hba *hisi_hba = shost_priv(shost);
+	struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT];
+	const struct cpumask *mask;
+	unsigned int queue, cpu;
+	for (queue = 0; queue < qmap->nr_queues; queue++) {
+		mask = irq_get_affinity_mask(hisi_hba->irq_map[96 + queue]);
+		if (!mask)
+			continue;
+		for_each_cpu(cpu, mask)
+			qmap->mq_map[cpu] = qmap->queue_offset + queue;
+	}
+	return 0;
+}
 static struct scsi_host_template sht_v2_hw = {
 	.name			= DRV_NAME,
 	.proc_name		= DRV_NAME,
 #endif
 	.shost_attrs		= host_attrs_v2_hw,
 	.host_reset		= hisi_sas_host_reset,
+	.map_queues		= map_queues_v2_hw,
+	.host_tagset		= 1,
 };
 static const struct hisi_sas_hw hisi_sas_v2_hw = {
 	.hw_init = hisi_sas_v2_init,
+	.interrupt_preinit = hisi_sas_v2_interrupt_preinit,
 	.setup_itct = setup_itct_v2_hw,
 	.slot_index_alloc = slot_index_alloc_quirk_v2_hw,
 	.alloc_dev = alloc_dev_quirk_v2_hw,

drivers/scsi/megaraid/megaraid_sas_base.c+39−0

@@ -37,6 +37,7 @@ · 36 unmodified lines
37	#include <linux/poll.h>	37	#include <linux/poll.h>
38	#include <linux/vmalloc.h>	38	#include <linux/vmalloc.h>
39	#include <linux/irq_poll.h>	39	#include <linux/irq_poll.h>
		40	#include <linux/blk-mq-pci.h>
40		41
41	#include <scsi/scsi.h>	42	#include <scsi/scsi.h>
42	#include <scsi/scsi_cmnd.h>	43	#include <scsi/scsi_cmnd.h>
@@ -113,6 +114,10 @@ unsigned int enable_sdev_max_qd; · 70 unmodified lines
113	module_param(enable_sdev_max_qd, int, 0444);	114	module_param(enable_sdev_max_qd, int, 0444);
114	MODULE_PARM_DESC(enable_sdev_max_qd, "Enable sdev max qd as can_queue. Default: 0");	115	MODULE_PARM_DESC(enable_sdev_max_qd, "Enable sdev max qd as can_queue. Default: 0");
115		116
		117	int host_tagset_enable = 1;
		118	module_param(host_tagset_enable, int, 0444);
		119	MODULE_PARM_DESC(host_tagset_enable, "Shared host tagset enable/disable Default: enable(1)");
		120
116	MODULE_LICENSE("GPL");	121	MODULE_LICENSE("GPL");
117	MODULE_VERSION(MEGASAS_VERSION);	122	MODULE_VERSION(MEGASAS_VERSION);
118	MODULE_AUTHOR("megaraidlinux.pdl@broadcom.com");	123	MODULE_AUTHOR("megaraidlinux.pdl@broadcom.com");
@@ -3119,6 +3124,19 @@ megasas_bios_param(struct scsi_device sdev, struct block_device bdev, · 3000 unmodified lines
3119	return 0;	3124	return 0;
3120	}	3125	}
3121		3126
		3127	static int megasas_map_queues(struct Scsi_Host *shost)
		3128	{
		3129	struct megasas_instance *instance;
		3130
		3131	instance = (struct megasas_instance *)shost->hostdata;
		3132
		3133	if (shost->nr_hw_queues == 1)
		3134	return 0;
		3135
		3136	return blk_mq_pci_map_queues(&shost->tag_set.map[HCTX_TYPE_DEFAULT],
		3137	instance->pdev, instance->low_latency_index_start);
		3138	}
		3139
3122	static void megasas_aen_polling(struct work_struct *work);	3140	static void megasas_aen_polling(struct work_struct *work);
3123		3141
3124	/**	3142	/**
@@ -3427,6 +3445,7 @@ static struct scsi_host_template megasas_template = { · 302 unmodified lines
3427	.eh_timed_out = megasas_reset_timer,	3445	.eh_timed_out = megasas_reset_timer,
3428	.shost_attrs = megaraid_host_attrs,	3446	.shost_attrs = megaraid_host_attrs,
3429	.bios_param = megasas_bios_param,	3447	.bios_param = megasas_bios_param,
		3448	.map_queues = megasas_map_queues,
3430	.change_queue_depth = scsi_change_queue_depth,	3449	.change_queue_depth = scsi_change_queue_depth,
3431	.max_segment_size = 0xffffffff,	3450	.max_segment_size = 0xffffffff,
3432	};	3451	};
@@ -6808,6 +6827,26 @@ static int megasas_io_attach(struct megasas_instance *instance) · 3375 unmodified lines
6808	host->max_lun = MEGASAS_MAX_LUN;	6827	host->max_lun = MEGASAS_MAX_LUN;
6809	host->max_cmd_len = 16;	6828	host->max_cmd_len = 16;
6810		6829
		6830	/* Use shared host tagset only for fusion adaptors
		6831	* if there are managed interrupts (smp affinity enabled case).
		6832	* Single msix_vectors in kdump, so shared host tag is also disabled.
		6833	*/
		6834
		6835	host->host_tagset = 0;
		6836	host->nr_hw_queues = 1;
		6837
		6838	if ((instance->adapter_type != MFI_SERIES) &&
		6839	(instance->msix_vectors > instance->low_latency_index_start) &&
		6840	host_tagset_enable &&
		6841	instance->smp_affinity_enable) {
		6842	host->host_tagset = 1;
		6843	host->nr_hw_queues = instance->msix_vectors -
		6844	instance->low_latency_index_start;
		6845	}
		6846
		6847	dev_info(&instance->pdev->dev,
		6848	"Max firmware commands: %d shared with nr_hw_queues = %d\n",
		6849	instance->max_fw_cmds, host->nr_hw_queues);
6811	/*	6850	/*
6812	* Notify the mid-layer about the new controller	6851	* Notify the mid-layer about the new controller
6813	*/	6852	*/

drivers/scsi/megaraid/megaraid_sas_fusion.c+16−13

@@ -359,24 +359,29 @@ megasas_get_msix_index(struct megasas_instance *instance, · 358 unmodified lines
359	{	359	{
360	int sdev_busy;	360	int sdev_busy;
361		361
362	/* nr_hw_queue = 1 for MegaRAID */	362	/* TBD - if sml remove device_busy in future, driver
363	struct blk_mq_hw_ctx *hctx =	363	* should track counter in internal structure.
364	scmd->device->request_queue->queue_hw_ctx[0];	364	*/
365		365	sdev_busy = atomic_read(&scmd->device->device_busy);
366	sdev_busy = atomic_read(&hctx->nr_active);
367		366
368	if (instance->perf_mode == MR_BALANCED_PERF_MODE &&	367	if (instance->perf_mode == MR_BALANCED_PERF_MODE &&
369	sdev_busy > (data_arms * MR_DEVICE_HIGH_IOPS_DEPTH))	368	sdev_busy > (data_arms * MR_DEVICE_HIGH_IOPS_DEPTH)) {
370	cmd->request_desc->SCSIIO.MSIxIndex =	369	cmd->request_desc->SCSIIO.MSIxIndex =
371	mega_mod64((atomic64_add_return(1, &instance->high_iops_outstanding) /	370	mega_mod64((atomic64_add_return(1, &instance->high_iops_outstanding) /
372	MR_HIGH_IOPS_BATCH_COUNT), instance->low_latency_index_start);	371	MR_HIGH_IOPS_BATCH_COUNT), instance->low_latency_index_start);
373	else if (instance->msix_load_balance)	372	} else if (instance->msix_load_balance) {
374	cmd->request_desc->SCSIIO.MSIxIndex =	373	cmd->request_desc->SCSIIO.MSIxIndex =
375	(mega_mod64(atomic64_add_return(1, &instance->total_io_count),	374	(mega_mod64(atomic64_add_return(1, &instance->total_io_count),
376	instance->msix_vectors));	375	instance->msix_vectors));
377	else	376	} else if (instance->host->nr_hw_queues > 1) {
		377	u32 tag = blk_mq_unique_tag(scmd->request);
		378
		379	cmd->request_desc->SCSIIO.MSIxIndex = blk_mq_unique_tag_to_hwq(tag) +
		380	instance->low_latency_index_start;
		381	} else {
378	cmd->request_desc->SCSIIO.MSIxIndex =	382	cmd->request_desc->SCSIIO.MSIxIndex =
379	instance->reply_map[raw_smp_processor_id()];	383	instance->reply_map[raw_smp_processor_id()];
		384	}
380	}	385	}
381		386
382	/**	387	/**
@@ -956,9 +961,6 @@ megasas_alloc_cmds_fusion(struct megasas_instance *instance) · 573 unmodified lines
956	if (megasas_alloc_cmdlist_fusion(instance))	961	if (megasas_alloc_cmdlist_fusion(instance))
957	goto fail_exit;	962	goto fail_exit;
958		963
959	dev_info(&instance->pdev->dev, "Configured max firmware commands: %d\n",
960	instance->max_fw_cmds);
961
962	/* The first 256 bytes (SMID 0) is not used. Don't add to the cmd list */	964	/* The first 256 bytes (SMID 0) is not used. Don't add to the cmd list */
963	io_req_base = fusion->io_request_frames + MEGA_MPI2_RAID_DEFAULT_IO_FRAME_SIZE;	965	io_req_base = fusion->io_request_frames + MEGA_MPI2_RAID_DEFAULT_IO_FRAME_SIZE;
964	io_req_base_phys = fusion->io_request_frames_phys + MEGA_MPI2_RAID_DEFAULT_IO_FRAME_SIZE;	966	io_req_base_phys = fusion->io_request_frames_phys + MEGA_MPI2_RAID_DEFAULT_IO_FRAME_SIZE;
@@ -1102,8 +1104,9 @@ megasas_ioc_init_fusion(struct megasas_instance *instance) · 137 unmodified lines
1102	MR_HIGH_IOPS_QUEUE_COUNT) && cur_intr_coalescing)	1104	MR_HIGH_IOPS_QUEUE_COUNT) && cur_intr_coalescing)
1103	instance->perf_mode = MR_BALANCED_PERF_MODE;	1105	instance->perf_mode = MR_BALANCED_PERF_MODE;
1104		1106
1105	dev_info(&instance->pdev->dev, "Performance mode :%s\n",	1107	dev_info(&instance->pdev->dev, "Performance mode :%s (latency index = %d)\n",
1106	MEGASAS_PERF_MODE_2STR(instance->perf_mode));	1108	MEGASAS_PERF_MODE_2STR(instance->perf_mode),
		1109	instance->low_latency_index_start);
1107		1110
1108	instance->fw_sync_cache_support = (scratch_pad_1 &	1111	instance->fw_sync_cache_support = (scratch_pad_1 &
1109	MR_CAN_HANDLE_SYNC_CACHE_OFFSET) ? 1 : 0;	1112	MR_CAN_HANDLE_SYNC_CACHE_OFFSET) ? 1 : 0;

drivers/scsi/mpt3sas/Kconfig+1−1

@@ -79,5 +79,5 @@ config SCSI_MPT2SAS · 78 unmodified lines
79	select SCSI_MPT3SAS	79	select SCSI_MPT3SAS
80	depends on PCI && SCSI	80	depends on PCI && SCSI
81	help	81	help
82	Dummy config option for backwards compatiblity: configure the MPT3SAS	82	Dummy config option for backwards compatibility: configure the MPT3SAS
83	driver instead.	83	driver instead.

drivers/scsi/mpt3sas/mpt3sas_base.c+1−1

@@ -5034,7 +5034,7 @@ _base_check_for_trigger_pages_support(struct MPT3SAS_ADAPTER *ioc) · 5033 unmodified lines
5034	static void	5034	static void
5035	_base_get_diag_triggers(struct MPT3SAS_ADAPTER *ioc)	5035	_base_get_diag_triggers(struct MPT3SAS_ADAPTER *ioc)
5036	{	5036	{
5037	u16 trigger_flags;	5037	int trigger_flags;
5038		5038
5039	/*	5039	/*
5040	* Default setting of master trigger.	5040	* Default setting of master trigger.

drivers/scsi/qedi/qedi_main.c+2−2

@@ -2245,7 +2245,7 @@ qedi_show_boot_tgt_info(struct qedi_ctx *qedi, int type, · 2244 unmodified lines
2245	chap_name);	2245	chap_name);
2246	break;	2246	break;
2247	case ISCSI_BOOT_TGT_CHAP_SECRET:	2247	case ISCSI_BOOT_TGT_CHAP_SECRET:
2248	rc = sprintf(buf, "%.*s\n", NVM_ISCSI_CFG_CHAP_NAME_MAX_LEN,	2248	rc = sprintf(buf, "%.*s\n", NVM_ISCSI_CFG_CHAP_PWD_MAX_LEN,
2249	chap_secret);	2249	chap_secret);
2250	break;	2250	break;
2251	case ISCSI_BOOT_TGT_REV_CHAP_NAME:	2251	case ISCSI_BOOT_TGT_REV_CHAP_NAME:
@@ -2253,7 +2253,7 @@ qedi_show_boot_tgt_info(struct qedi_ctx *qedi, int type, · 1 unmodified line
2253	mchap_name);	2253	mchap_name);
2254	break;	2254	break;
2255	case ISCSI_BOOT_TGT_REV_CHAP_SECRET:	2255	case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
2256	rc = sprintf(buf, "%.*s\n", NVM_ISCSI_CFG_CHAP_NAME_MAX_LEN,	2256	rc = sprintf(buf, "%.*s\n", NVM_ISCSI_CFG_CHAP_PWD_MAX_LEN,
2257	mchap_secret);	2257	mchap_secret);
2258	break;	2258	break;
2259	case ISCSI_BOOT_TGT_FLAGS:	2259	case ISCSI_BOOT_TGT_FLAGS:

drivers/scsi/scsi_debug.c+3−2

 		k = sdeb_zbc_model_str(sdeb_zbc_model_s);
 		if (k < 0) {
 			ret = k;
-			goto free_vm;
+			goto free_q_arr;
 		}
 		sdeb_zbc_model = k;
 		switch (sdeb_zbc_model) {
 			break;
 		default:
 			pr_err("Invalid ZBC model\n");
-			return -EINVAL;
+			ret = -EINVAL;
+			goto free_q_arr;
 		}
 	}
 	if (sdeb_zbc_model != BLK_ZONED_NONE) {

drivers/scsi/scsi_lib.c+14−13

 	req = blk_get_request(sdev->request_queue,
 			data_direction == DMA_TO_DEVICE ?
-			REQ_OP_SCSI_OUT : REQ_OP_SCSI_IN, BLK_MQ_REQ_PREEMPT);
+			REQ_OP_SCSI_OUT : REQ_OP_SCSI_IN,
+			rq_flags & RQF_PM ? BLK_MQ_REQ_PM : 0);
 	if (IS_ERR(req))
 		return ret;
 	rq = scsi_req(req);
 scsi_device_state_check(struct scsi_device *sdev, struct request *req)
 {
 	switch (sdev->sdev_state) {
+	case SDEV_CREATED:
+		return BLK_STS_OK;
 	case SDEV_OFFLINE:
 	case SDEV_TRANSPORT_OFFLINE:
 		/*
 		return BLK_STS_RESOURCE;
 	case SDEV_QUIESCE:
 		/*
-		 * If the devices is blocked we defer normal commands.
+		 * If the device is blocked we only accept power management
+		 * commands.
 		 */
-		if (req && !(req->rq_flags & RQF_PREEMPT))
+		if (req && WARN_ON_ONCE(!(req->rq_flags & RQF_PM)))
 			return BLK_STS_RESOURCE;
 		return BLK_STS_OK;
 	default:
 		/*
 		 * For any other not fully online state we only allow
-		 * special commands.  In particular any user initiated
+		 * power management commands.
-		 * command is not allowed.
 		 */
-		if (req && !(req->rq_flags & RQF_PREEMPT))
+		if (req && !(req->rq_flags & RQF_PM))
 			return BLK_STS_IOERR;
 		return BLK_STS_OK;
 	}
 EXPORT_SYMBOL_GPL(sdev_evt_send_simple);
 /**
- *	scsi_device_quiesce - Block user issued commands.
+ *	scsi_device_quiesce - Block all commands except power management.
  *	@sdev:	scsi device to quiesce.
  *
  *	This works by trying to transition to the SDEV_QUIESCE state
  *	(which must be a legal transition).  When the device is in this
- *	state, only special requests will be accepted, all others will
+ *	state, only power management requests will be accepted, all others will
- *	be deferred.  Since special requests may also be requeued requests,
+ *	be deferred.
- *	a successful return doesn't guarantee the device will be
- *	totally quiescent.
  *
  *	Must be called with user context, may sleep.
  *
 	 * device deleted during suspend)
 	 */
 	mutex_lock(&sdev->state_mutex);
+	if (sdev->sdev_state == SDEV_QUIESCE)
+		scsi_device_set_state(sdev, SDEV_RUNNING);
 	if (sdev->quiesced_by) {
 		sdev->quiesced_by = NULL;
 		blk_clear_pm_only(sdev->request_queue);
 	}
-	if (sdev->sdev_state == SDEV_QUIESCE)
-		scsi_device_set_state(sdev, SDEV_RUNNING);
 	mutex_unlock(&sdev->state_mutex);
 }
 EXPORT_SYMBOL(scsi_device_resume);

drivers/scsi/scsi_transport_spi.c+19−8

@@ -117,12 +117,16 @@ static int spi_execute(struct scsi_device sdev, const void cmd, · 116 unmodified lines
117	sshdr = &sshdr_tmp;	117	sshdr = &sshdr_tmp;
118		118
119	for(i = 0; i < DV_RETRIES; i++) {	119	for(i = 0; i < DV_RETRIES; i++) {
		120	/*
		121	* The purpose of the RQF_PM flag below is to bypass the
		122	* SDEV_QUIESCE state.
		123	*/
120	result = scsi_execute(sdev, cmd, dir, buffer, bufflen, sense,	124	result = scsi_execute(sdev, cmd, dir, buffer, bufflen, sense,
121	sshdr, DV_TIMEOUT, /* retries */ 1,	125	sshdr, DV_TIMEOUT, /* retries */ 1,
122	REQ_FAILFAST_DEV \|	126	REQ_FAILFAST_DEV \|
123	REQ_FAILFAST_TRANSPORT \|	127	REQ_FAILFAST_TRANSPORT \|
124	REQ_FAILFAST_DRIVER,	128	REQ_FAILFAST_DRIVER,
125	0, NULL);	129	RQF_PM, NULL);
126	if (driver_byte(result) != DRIVER_SENSE \|\|	130	if (driver_byte(result) != DRIVER_SENSE \|\|
127	sshdr->sense_key != UNIT_ATTENTION)	131	sshdr->sense_key != UNIT_ATTENTION)
128	break;	132	break;
@@ -1005,23 +1009,26 @@ spi_dv_device(struct scsi_device *sdev) · 876 unmodified lines
1005	*/	1009	*/
1006	lock_system_sleep();	1010	lock_system_sleep();
1007		1011
		1012	if (scsi_autopm_get_device(sdev))
		1013	goto unlock_system_sleep;
		1014
1008	if (unlikely(spi_dv_in_progress(starget)))	1015	if (unlikely(spi_dv_in_progress(starget)))
1009	goto unlock;	1016	goto put_autopm;
1010		1017
1011	if (unlikely(scsi_device_get(sdev)))	1018	if (unlikely(scsi_device_get(sdev)))
1012	goto unlock;	1019	goto put_autopm;
1013		1020
1014	spi_dv_in_progress(starget) = 1;	1021	spi_dv_in_progress(starget) = 1;
1015		1022
1016	buffer = kzalloc(len, GFP_KERNEL);	1023	buffer = kzalloc(len, GFP_KERNEL);
1017		1024
1018	if (unlikely(!buffer))	1025	if (unlikely(!buffer))
1019	goto out_put;	1026	goto put_sdev;
1020		1027
1021	/* We need to verify that the actual device will quiesce; the	1028	/* We need to verify that the actual device will quiesce; the
1022	* later target quiesce is just a nice to have */	1029	* later target quiesce is just a nice to have */
1023	if (unlikely(scsi_device_quiesce(sdev)))	1030	if (unlikely(scsi_device_quiesce(sdev)))
1024	goto out_free;	1031	goto free_buffer;
1025		1032
1026	scsi_target_quiesce(starget);	1033	scsi_target_quiesce(starget);
1027		1034
@@ -1041,12 +1048,16 @@ spi_dv_device(struct scsi_device *sdev) · 13 unmodified lines
1041		1048
1042	spi_initial_dv(starget) = 1;	1049	spi_initial_dv(starget) = 1;
1043		1050
1044	out_free:	1051	free_buffer:
1045	kfree(buffer);	1052	kfree(buffer);
1046	out_put:	1053
		1054	put_sdev:
1047	spi_dv_in_progress(starget) = 0;	1055	spi_dv_in_progress(starget) = 0;
1048	scsi_device_put(sdev);	1056	scsi_device_put(sdev);
1049	unlock:	1057	put_autopm:
		1058	scsi_autopm_put_device(sdev);
		1059
		1060	unlock_system_sleep:
1050	unlock_system_sleep();	1061	unlock_system_sleep();
1051	}	1062	}
1052	EXPORT_SYMBOL(spi_dv_device);	1063	EXPORT_SYMBOL(spi_dv_device);

drivers/scsi/sd.c+3−3

 		}
 	}
-	if (sdp->no_write_same)
+	if (sdp->no_write_same) {
+		rq->rq_flags |= RQF_QUIET;
 		return BLK_STS_TARGET;
+	}
 	if (sdkp->ws16 || lba > 0xffffffff || nr_blocks > 0xffff)
 		return sd_setup_write_same16_cmnd(cmd, false);
 static int sd_remove(struct device *dev)
 {
 	struct scsi_disk *sdkp;
-	dev_t devt;
 	sdkp = dev_get_drvdata(dev);
-	devt = disk_devt(sdkp->disk);
 	scsi_autopm_get_device(sdkp->device);
 	async_synchronize_full_domain(&scsi_sd_pm_domain);

drivers/scsi/ufs/ufs-mediatek-trace.h+1−1

@@ -31,6 +31,6 @@ TRACE_EVENT(ufs_mtk_event, · 30 unmodified lines
31		31
32	#undef TRACE_INCLUDE_PATH	32	#undef TRACE_INCLUDE_PATH
33	#undef TRACE_INCLUDE_FILE	33	#undef TRACE_INCLUDE_FILE
34	#define TRACE_INCLUDE_PATH .	34	#define TRACE_INCLUDE_PATH ../../drivers/scsi/ufs/
35	#define TRACE_INCLUDE_FILE ufs-mediatek-trace	35	#define TRACE_INCLUDE_FILE ufs-mediatek-trace
36	#include <trace/define_trace.h>	36	#include <trace/define_trace.h>

drivers/scsi/ufs/ufs-mediatek.c+21−0

@@ -70,6 +70,13 @@ static bool ufs_mtk_is_va09_supported(struct ufs_hba *hba) · 69 unmodified lines
70	return !!(host->caps & UFS_MTK_CAP_VA09_PWR_CTRL);	70	return !!(host->caps & UFS_MTK_CAP_VA09_PWR_CTRL);
71	}	71	}
72		72
		73	static bool ufs_mtk_is_broken_vcc(struct ufs_hba *hba)
		74	{
		75	struct ufs_mtk_host *host = ufshcd_get_variant(hba);
		76
		77	return !!(host->caps & UFS_MTK_CAP_BROKEN_VCC);
		78	}
		79
73	static void ufs_mtk_cfg_unipro_cg(struct ufs_hba *hba, bool enable)	80	static void ufs_mtk_cfg_unipro_cg(struct ufs_hba *hba, bool enable)
74	{	81	{
75	u32 tmp;	82	u32 tmp;
@@ -514,6 +521,9 @@ static void ufs_mtk_init_host_caps(struct ufs_hba *hba) · 438 unmodified lines
514	if (of_property_read_bool(np, "mediatek,ufs-disable-ah8"))	521	if (of_property_read_bool(np, "mediatek,ufs-disable-ah8"))
515	host->caps \|= UFS_MTK_CAP_DISABLE_AH8;	522	host->caps \|= UFS_MTK_CAP_DISABLE_AH8;
516		523
		524	if (of_property_read_bool(np, "mediatek,ufs-broken-vcc"))
		525	host->caps \|= UFS_MTK_CAP_BROKEN_VCC;
		526
517	dev_info(hba->dev, "caps: 0x%x", host->caps);	527	dev_info(hba->dev, "caps: 0x%x", host->caps);
518	}	528	}
519		529
@@ -1003,6 +1013,17 @@ static int ufs_mtk_apply_dev_quirks(struct ufs_hba *hba) · 483 unmodified lines
1003	static void ufs_mtk_fixup_dev_quirks(struct ufs_hba *hba)	1013	static void ufs_mtk_fixup_dev_quirks(struct ufs_hba *hba)
1004	{	1014	{
1005	ufshcd_fixup_dev_quirks(hba, ufs_mtk_dev_fixups);	1015	ufshcd_fixup_dev_quirks(hba, ufs_mtk_dev_fixups);
		1016
		1017	if (ufs_mtk_is_broken_vcc(hba) && hba->vreg_info.vcc &&
		1018	(hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_AFTER_LPM)) {
		1019	hba->vreg_info.vcc->always_on = true;
		1020	/*
		1021	* VCC will be kept always-on thus we don't
		1022	* need any delay during regulator operations
		1023	*/
		1024	hba->dev_quirks &= ~(UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM \|
		1025	UFS_DEVICE_QUIRK_DELAY_AFTER_LPM);
		1026	}
1006	}	1027	}
1007		1028
1008	static void ufs_mtk_event_notify(struct ufs_hba *hba,	1029	static void ufs_mtk_event_notify(struct ufs_hba *hba,

drivers/scsi/ufs/ufs-mediatek.h+1−0

@@ -81,6 +81,7 @@ enum ufs_mtk_host_caps { · 80 unmodified lines
81	UFS_MTK_CAP_BOOST_CRYPT_ENGINE = 1 << 0,	81	UFS_MTK_CAP_BOOST_CRYPT_ENGINE = 1 << 0,
82	UFS_MTK_CAP_VA09_PWR_CTRL = 1 << 1,	82	UFS_MTK_CAP_VA09_PWR_CTRL = 1 << 1,
83	UFS_MTK_CAP_DISABLE_AH8 = 1 << 2,	83	UFS_MTK_CAP_DISABLE_AH8 = 1 << 2,
		84	UFS_MTK_CAP_BROKEN_VCC = 1 << 3,
84	};	85	};
85		86
86	struct ufs_mtk_crypt_cfg {	87	struct ufs_mtk_crypt_cfg {

drivers/scsi/ufs/ufs.h+1−1

 	UFS_DEV_WRITE_BOOSTER_SUP	= BIT(8),
 };
-#define POWER_DESC_MAX_SIZE			0x62
 #define POWER_DESC_MAX_ACTV_ICC_LVLS		16
 /* Attribute  bActiveICCLevel parameter bit masks definitions */
 struct ufs_vreg {
 	struct regulator *reg;
 	const char *name;
+	bool always_on;
 	bool enabled;
 	int min_uV;
 	int max_uV;

drivers/scsi/ufs/ufshcd-pci.c+71−2

@@ -148,6 +148,8 @@ static int ufs_intel_common_init(struct ufs_hba *hba) · 147 unmodified lines
148	{	148	{
149	struct intel_host *host;	149	struct intel_host *host;
150		150
		151	hba->caps \|= UFSHCD_CAP_RPM_AUTOSUSPEND;
		152
151	host = devm_kzalloc(hba->dev, sizeof(*host), GFP_KERNEL);	153	host = devm_kzalloc(hba->dev, sizeof(*host), GFP_KERNEL);
152	if (!host)	154	if (!host)
153	return -ENOMEM;	155	return -ENOMEM;
@@ -163,6 +165,41 @@ static void ufs_intel_common_exit(struct ufs_hba *hba) · 9 unmodified lines
163	intel_ltr_hide(hba->dev);	165	intel_ltr_hide(hba->dev);
164	}	166	}
165		167
		168	static int ufs_intel_resume(struct ufs_hba *hba, enum ufs_pm_op op)
		169	{
		170	/*
		171	* To support S4 (suspend-to-disk) with spm_lvl other than 5, the base
		172	* address registers must be restored because the restore kernel can
		173	* have used different addresses.
		174	*/
		175	ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
		176	REG_UTP_TRANSFER_REQ_LIST_BASE_L);
		177	ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
		178	REG_UTP_TRANSFER_REQ_LIST_BASE_H);
		179	ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
		180	REG_UTP_TASK_REQ_LIST_BASE_L);
		181	ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
		182	REG_UTP_TASK_REQ_LIST_BASE_H);
		183
		184	if (ufshcd_is_link_hibern8(hba)) {
		185	int ret = ufshcd_uic_hibern8_exit(hba);
		186
		187	if (!ret) {
		188	ufshcd_set_link_active(hba);
		189	} else {
		190	dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
		191	__func__, ret);
		192	/*
		193	* Force reset and restore. Any other actions can lead
		194	* to an unrecoverable state.
		195	*/
		196	ufshcd_set_link_off(hba);
		197	}
		198	}
		199
		200	return 0;
		201	}
		202
166	static int ufs_intel_ehl_init(struct ufs_hba *hba)	203	static int ufs_intel_ehl_init(struct ufs_hba *hba)
167	{	204	{
168	hba->quirks \|= UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8;	205	hba->quirks \|= UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8;
@@ -174,6 +211,7 @@ static struct ufs_hba_variant_ops ufs_intel_cnl_hba_vops = { · 5 unmodified lines
174	.init = ufs_intel_common_init,	211	.init = ufs_intel_common_init,
175	.exit = ufs_intel_common_exit,	212	.exit = ufs_intel_common_exit,
176	.link_startup_notify = ufs_intel_link_startup_notify,	213	.link_startup_notify = ufs_intel_link_startup_notify,
		214	.resume = ufs_intel_resume,
177	};	215	};
178		216
179	static struct ufs_hba_variant_ops ufs_intel_ehl_hba_vops = {	217	static struct ufs_hba_variant_ops ufs_intel_ehl_hba_vops = {
@@ -181,6 +219,7 @@ static struct ufs_hba_variant_ops ufs_intel_ehl_hba_vops = { · 1 unmodified line
181	.init = ufs_intel_ehl_init,	219	.init = ufs_intel_ehl_init,
182	.exit = ufs_intel_common_exit,	220	.exit = ufs_intel_common_exit,
183	.link_startup_notify = ufs_intel_link_startup_notify,	221	.link_startup_notify = ufs_intel_link_startup_notify,
		222	.resume = ufs_intel_resume,
184	};	223	};
185		224
186	#ifdef CONFIG_PM_SLEEP	225	#ifdef CONFIG_PM_SLEEP
@@ -207,6 +246,30 @@ static int ufshcd_pci_resume(struct device *dev) · 20 unmodified lines
207	{	246	{
208	return ufshcd_system_resume(dev_get_drvdata(dev));	247	return ufshcd_system_resume(dev_get_drvdata(dev));
209	}	248	}
		249
		250	/**
		251	* ufshcd_pci_poweroff - suspend-to-disk poweroff function
		252	* @dev: pointer to PCI device handle
		253	*
		254	* Returns 0 if successful
		255	* Returns non-zero otherwise
		256	*/
		257	static int ufshcd_pci_poweroff(struct device *dev)
		258	{
		259	struct ufs_hba *hba = dev_get_drvdata(dev);
		260	int spm_lvl = hba->spm_lvl;
		261	int ret;
		262
		263	/*
		264	* For poweroff we need to set the UFS device to PowerDown mode.
		265	* Force spm_lvl to ensure that.
		266	*/
		267	hba->spm_lvl = 5;
		268	ret = ufshcd_system_suspend(hba);
		269	hba->spm_lvl = spm_lvl;
		270	return ret;
		271	}
		272
210	#endif /* !CONFIG_PM_SLEEP */	273	#endif /* !CONFIG_PM_SLEEP */
211		274
212	#ifdef CONFIG_PM	275	#ifdef CONFIG_PM
@@ -302,8 +365,14 @@ ufshcd_pci_probe(struct pci_dev pdev, const struct pci_device_id id) · 89 unmodified lines
302	}	365	}
303		366
304	static const struct dev_pm_ops ufshcd_pci_pm_ops = {	367	static const struct dev_pm_ops ufshcd_pci_pm_ops = {
305	SET_SYSTEM_SLEEP_PM_OPS(ufshcd_pci_suspend,	368	#ifdef CONFIG_PM_SLEEP
306	ufshcd_pci_resume)	369	.suspend = ufshcd_pci_suspend,
		370	.resume = ufshcd_pci_resume,
		371	.freeze = ufshcd_pci_suspend,
		372	.thaw = ufshcd_pci_resume,
		373	.poweroff = ufshcd_pci_poweroff,
		374	.restore = ufshcd_pci_resume,
		375	#endif
307	SET_RUNTIME_PM_OPS(ufshcd_pci_runtime_suspend,	376	SET_RUNTIME_PM_OPS(ufshcd_pci_runtime_suspend,
308	ufshcd_pci_runtime_resume,	377	ufshcd_pci_runtime_resume,
309	ufshcd_pci_runtime_idle)	378	ufshcd_pci_runtime_idle)

drivers/scsi/ufs/ufshcd.c+39−30

@@ -225,6 +225,7 @@ static int ufshcd_reset_and_restore(struct ufs_hba *hba); · 224 unmodified lines
225	static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd);	225	static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd);
226	static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);	226	static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
227	static void ufshcd_hba_exit(struct ufs_hba *hba);	227	static void ufshcd_hba_exit(struct ufs_hba *hba);
		228	static int ufshcd_clear_ua_wluns(struct ufs_hba *hba);
228	static int ufshcd_probe_hba(struct ufs_hba *hba, bool async);	229	static int ufshcd_probe_hba(struct ufs_hba *hba, bool async);
229	static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);	230	static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
230	static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);	231	static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
@@ -288,7 +289,8 @@ static inline void ufshcd_wb_config(struct ufs_hba *hba) · 57 unmodified lines
288	if (ret)	289	if (ret)
289	dev_err(hba->dev, "%s: En WB flush during H8: failed: %d\n",	290	dev_err(hba->dev, "%s: En WB flush during H8: failed: %d\n",
290	__func__, ret);	291	__func__, ret);
291	ufshcd_wb_toggle_flush(hba, true);	292	if (!(hba->quirks & UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL))
		293	ufshcd_wb_toggle_flush(hba, true);
292	}	294	}
293		295
294	static void ufshcd_scsi_unblock_requests(struct ufs_hba *hba)	296	static void ufshcd_scsi_unblock_requests(struct ufs_hba *hba)
@@ -580,6 +582,23 @@ static void ufshcd_print_pwr_info(struct ufs_hba *hba) · 285 unmodified lines
580	hba->pwr_info.hs_rate);	582	hba->pwr_info.hs_rate);
581	}	583	}
582		584
		585	static void ufshcd_device_reset(struct ufs_hba *hba)
		586	{
		587	int err;
		588
		589	err = ufshcd_vops_device_reset(hba);
		590
		591	if (!err) {
		592	ufshcd_set_ufs_dev_active(hba);
		593	if (ufshcd_is_wb_allowed(hba)) {
		594	hba->wb_enabled = false;
		595	hba->wb_buf_flush_enabled = false;
		596	}
		597	}
		598	if (err != -EOPNOTSUPP)
		599	ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, err);
		600	}
		601
583	void ufshcd_delay_us(unsigned long us, unsigned long tolerance)	602	void ufshcd_delay_us(unsigned long us, unsigned long tolerance)
584	{	603	{
585	if (!us)	604	if (!us)
@@ -3665,7 +3684,7 @@ static int ufshcd_dme_enable(struct ufs_hba *hba) · 3079 unmodified lines
3665	ret = ufshcd_send_uic_cmd(hba, &uic_cmd);	3684	ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3666	if (ret)	3685	if (ret)
3667	dev_err(hba->dev,	3686	dev_err(hba->dev,
3668	"dme-reset: error code %d\n", ret);	3687	"dme-enable: error code %d\n", ret);
3669		3688
3670	return ret;	3689	return ret;
3671	}	3690	}
@@ -3964,7 +3983,7 @@ int ufshcd_link_recovery(struct ufs_hba *hba) · 292 unmodified lines
3964	spin_unlock_irqrestore(hba->host->host_lock, flags);	3983	spin_unlock_irqrestore(hba->host->host_lock, flags);
3965		3984
3966	/* Reset the attached device */	3985	/* Reset the attached device */
3967	ufshcd_vops_device_reset(hba);	3986	ufshcd_device_reset(hba);
3968		3987
3969	ret = ufshcd_host_reset_and_restore(hba);	3988	ret = ufshcd_host_reset_and_restore(hba);
3970		3989
@@ -5418,9 +5437,6 @@ static int ufshcd_wb_toggle_flush_during_h8(struct ufs_hba *hba, bool set) · 1447 unmodified lines
5418		5437
5419	static inline void ufshcd_wb_toggle_flush(struct ufs_hba *hba, bool enable)	5438	static inline void ufshcd_wb_toggle_flush(struct ufs_hba *hba, bool enable)
5420	{	5439	{
5421	if (hba->quirks & UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL)
5422	return;
5423
5424	if (enable)	5440	if (enable)
5425	ufshcd_wb_buf_flush_enable(hba);	5441	ufshcd_wb_buf_flush_enable(hba);
5426	else	5442	else
@@ -6643,19 +6659,16 @@ static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd) · 1216 unmodified lines
6643	{	6659	{
6644	struct Scsi_Host *host;	6660	struct Scsi_Host *host;
6645	struct ufs_hba *hba;	6661	struct ufs_hba *hba;
6646	unsigned int tag;
6647	u32 pos;	6662	u32 pos;
6648	int err;	6663	int err;
6649	u8 resp = 0xF;	6664	u8 resp = 0xF, lun;
6650	struct ufshcd_lrb *lrbp;
6651	unsigned long flags;	6665	unsigned long flags;
6652		6666
6653	host = cmd->device->host;	6667	host = cmd->device->host;
6654	hba = shost_priv(host);	6668	hba = shost_priv(host);
6655	tag = cmd->request->tag;
6656		6669
6657	lrbp = &hba->lrb[tag];	6670	lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
6658	err = ufshcd_issue_tm_cmd(hba, lrbp->lun, 0, UFS_LOGICAL_RESET, &resp);	6671	err = ufshcd_issue_tm_cmd(hba, lun, 0, UFS_LOGICAL_RESET, &resp);
6659	if (err \|\| resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {	6672	if (err \|\| resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
6660	if (!err)	6673	if (!err)
6661	err = resp;	6674	err = resp;
@@ -6664,7 +6677,7 @@ static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd) · 2 unmodified lines
6664		6677
6665	/* clear the commands that were pending for corresponding LUN */	6678	/* clear the commands that were pending for corresponding LUN */
6666	for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {	6679	for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {
6667	if (hba->lrb[pos].lun == lrbp->lun) {	6680	if (hba->lrb[pos].lun == lun) {
6668	err = ufshcd_clear_cmd(hba, pos);	6681	err = ufshcd_clear_cmd(hba, pos);
6669	if (err)	6682	if (err)
6670	break;	6683	break;
@@ -6930,7 +6943,8 @@ static int ufshcd_host_reset_and_restore(struct ufs_hba *hba) · 259 unmodified lines
6930		6943
6931	/* Establish the link again and restore the device */	6944	/* Establish the link again and restore the device */
6932	err = ufshcd_probe_hba(hba, false);	6945	err = ufshcd_probe_hba(hba, false);
6933		6946	if (!err)
		6947	ufshcd_clear_ua_wluns(hba);
6934	out:	6948	out:
6935	if (err)	6949	if (err)
6936	dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);	6950	dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
@@ -6968,7 +6982,7 @@ static int ufshcd_reset_and_restore(struct ufs_hba *hba) · 31 unmodified lines
6968		6982
6969	do {	6983	do {
6970	/* Reset the attached device */	6984	/* Reset the attached device */
6971	ufshcd_vops_device_reset(hba);	6985	ufshcd_device_reset(hba);
6972		6986
6973	err = ufshcd_host_reset_and_restore(hba);	6987	err = ufshcd_host_reset_and_restore(hba);
6974	} while (err && --retries);	6988	} while (err && --retries);
@@ -8045,7 +8059,7 @@ static int ufshcd_disable_vreg(struct device dev, struct ufs_vreg vreg) · 1070 unmodified lines
8045	{	8059	{
8046	int ret = 0;	8060	int ret = 0;
8047		8061
8048	if (!vreg \|\| !vreg->enabled)	8062	if (!vreg \|\| !vreg->enabled \|\| vreg->always_on)
8049	goto out;	8063	goto out;
8050		8064
8051	ret = regulator_disable(vreg->reg);	8065	ret = regulator_disable(vreg->reg);
@@ -8414,13 +8428,7 @@ static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba, · 362 unmodified lines
8414	* handling context.	8428	* handling context.
8415	*/	8429	*/
8416	hba->host->eh_noresume = 1;	8430	hba->host->eh_noresume = 1;
8417	if (hba->wlun_dev_clr_ua) {	8431	ufshcd_clear_ua_wluns(hba);
8418	ret = ufshcd_send_request_sense(hba, sdp);
8419	if (ret)
8420	goto out;
8421	/* Unit attention condition is cleared now */
8422	hba->wlun_dev_clr_ua = false;
8423	}
8424		8432
8425	cmd[4] = pwr_mode << 4;	8433	cmd[4] = pwr_mode << 4;
8426		8434
@@ -8441,7 +8449,7 @@ static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba, · 14 unmodified lines
8441		8449
8442	if (!ret)	8450	if (!ret)
8443	hba->curr_dev_pwr_mode = pwr_mode;	8451	hba->curr_dev_pwr_mode = pwr_mode;
8444	out:	8452
8445	scsi_device_put(sdp);	8453	scsi_device_put(sdp);
8446	hba->host->eh_noresume = 0;	8454	hba->host->eh_noresume = 0;
8447	return ret;	8455	return ret;
@@ -8685,6 +8693,8 @@ static int ufshcd_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op) · 237 unmodified lines
8685	ufshcd_wb_need_flush(hba));	8693	ufshcd_wb_need_flush(hba));
8686	}	8694	}
8687		8695
		8696	flush_work(&hba->eeh_work);
		8697
8688	if (req_dev_pwr_mode != hba->curr_dev_pwr_mode) {	8698	if (req_dev_pwr_mode != hba->curr_dev_pwr_mode) {
8689	if (!ufshcd_is_runtime_pm(pm_op))	8699	if (!ufshcd_is_runtime_pm(pm_op))
8690	/* ensure that bkops is disabled */	8700	/* ensure that bkops is disabled */
@@ -8697,8 +8707,6 @@ static int ufshcd_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op) · 6 unmodified lines
8697	}	8707	}
8698	}	8708	}
8699		8709
8700	flush_work(&hba->eeh_work);
8701
8702	/*	8710	/*
8703	* In the case of DeepSleep, the device is expected to remain powered	8711	* In the case of DeepSleep, the device is expected to remain powered
8704	* with the link off, so do not check for bkops.	8712	* with the link off, so do not check for bkops.
@@ -8747,7 +8755,7 @@ set_link_active: · 42 unmodified lines
8747	* further below.	8755	* further below.
8748	*/	8756	*/
8749	if (ufshcd_is_ufs_dev_deepsleep(hba)) {	8757	if (ufshcd_is_ufs_dev_deepsleep(hba)) {
8750	ufshcd_vops_device_reset(hba);	8758	ufshcd_device_reset(hba);
8751	WARN_ON(!ufshcd_is_link_off(hba));	8759	WARN_ON(!ufshcd_is_link_off(hba));
8752	}	8760	}
8753	if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))	8761	if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
@@ -8757,7 +8765,7 @@ set_link_active: · 3 unmodified lines
8757	set_dev_active:	8765	set_dev_active:
8758	/* Can also get here needing to exit DeepSleep */	8766	/* Can also get here needing to exit DeepSleep */
8759	if (ufshcd_is_ufs_dev_deepsleep(hba)) {	8767	if (ufshcd_is_ufs_dev_deepsleep(hba)) {
8760	ufshcd_vops_device_reset(hba);	8768	ufshcd_device_reset(hba);
8761	ufshcd_host_reset_and_restore(hba);	8769	ufshcd_host_reset_and_restore(hba);
8762	}	8770	}
8763	if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))	8771	if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
@@ -8925,7 +8933,8 @@ int ufshcd_system_suspend(struct ufs_hba *hba) · 161 unmodified lines
8925	if ((ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl) ==	8933	if ((ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl) ==
8926	hba->curr_dev_pwr_mode) &&	8934	hba->curr_dev_pwr_mode) &&
8927	(ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl) ==	8935	(ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl) ==
8928	hba->uic_link_state))	8936	hba->uic_link_state) &&
		8937	!hba->dev_info.b_rpm_dev_flush_capable)
8929	goto out;	8938	goto out;
8930		8939
8931	if (pm_runtime_suspended(hba->dev)) {	8940	if (pm_runtime_suspended(hba->dev)) {
@@ -9353,7 +9362,7 @@ int ufshcd_init(struct ufs_hba hba, void __iomem mmio_base, unsigned int irq) · 421 unmodified lines
9353	}	9362	}
9354		9363
9355	/* Reset the attached device */	9364	/* Reset the attached device */
9356	ufshcd_vops_device_reset(hba);	9365	ufshcd_device_reset(hba);
9357		9366
9358	ufshcd_init_crypto(hba);	9367	ufshcd_init_crypto(hba);
9359		9368

drivers/scsi/ufs/ufshcd.h+5−9

 		hba->vops->dbg_register_dump(hba);
 }
-static inline void ufshcd_vops_device_reset(struct ufs_hba *hba)
+static inline int ufshcd_vops_device_reset(struct ufs_hba *hba)
 {
-	if (hba->vops && hba->vops->device_reset) {
+	if (hba->vops && hba->vops->device_reset)
-		int err = hba->vops->device_reset(hba);
+		return hba->vops->device_reset(hba);
-		if (!err)
+	return -EOPNOTSUPP;
-			ufshcd_set_ufs_dev_active(hba);
-		if (err != -EOPNOTSUPP)
-			ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, err);
-	}
 }
 static inline void ufshcd_vops_config_scaling_param(struct ufs_hba *hba,

drivers/spi/spi-altera.c+14−12

@@ -189,24 +189,26 @@ static int altera_spi_txrx(struct spi_master *master, · 188 unmodified lines
189		189
190	/* send the first byte */	190	/* send the first byte */
191	altera_spi_tx_word(hw);	191	altera_spi_tx_word(hw);
192	} else {
193	while (hw->count < hw->len) {
194	altera_spi_tx_word(hw);
195		192
196	for (;;) {	193	return 1;
197	altr_spi_readl(hw, ALTERA_SPI_STATUS, &val);	194	}
198	if (val & ALTERA_SPI_STATUS_RRDY_MSK)	195
199	break;	196	while (hw->count < hw->len) {
		197	altera_spi_tx_word(hw);
200		198
201	cpu_relax();	199	for (;;) {
202	}	200	altr_spi_readl(hw, ALTERA_SPI_STATUS, &val);
		201	if (val & ALTERA_SPI_STATUS_RRDY_MSK)
		202	break;
203		203
204	altera_spi_rx_word(hw);	204	cpu_relax();
205	}	205	}
206	spi_finalize_current_transfer(master);	206
		207	altera_spi_rx_word(hw);
207	}	208	}
		209	spi_finalize_current_transfer(master);
208		210
209	return t->len;	211	return 0;
210	}	212	}
211		213
212	static irqreturn_t altera_spi_irq(int irq, void *dev)	214	static irqreturn_t altera_spi_irq(int irq, void *dev)

drivers/spi/spi-cadence.c+4−2

 	void __iomem *regs;
 	struct clk *ref_clk;
 	struct clk *pclk;
+	unsigned int clk_rate;
 	u32 speed_hz;
 	const u8 *txbuf;
 	u8 *rxbuf;
 	u32 ctrl_reg, baud_rate_val;
 	unsigned long frequency;
-	frequency = clk_get_rate(xspi->ref_clk);
+	frequency = xspi->clk_rate;
 	ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
 	master->auto_runtime_pm = true;
 	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
+	xspi->clk_rate = clk_get_rate(xspi->ref_clk);
 	/* Set to default valid value */
-	master->max_speed_hz = clk_get_rate(xspi->ref_clk) / 4;
+	master->max_speed_hz = xspi->clk_rate / 4;
 	xspi->speed_hz = master->max_speed_hz;
 	master->bits_per_word_mask = SPI_BPW_MASK(8);

drivers/spi/spi-fsl-spi.c+2−3

 {
 	struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
 	struct fsl_spi_platform_data *pdata;
-	bool pol = spi->mode & SPI_CS_HIGH;
 	struct spi_mpc8xxx_cs	*cs = spi->controller_state;
 	pdata = spi->dev.parent->parent->platform_data;
 	if (value == BITBANG_CS_INACTIVE) {
 		if (pdata->cs_control)
-			pdata->cs_control(spi, !pol);
+			pdata->cs_control(spi, false);
 	}
 	if (value == BITBANG_CS_ACTIVE) {
 		fsl_spi_change_mode(spi);
 		if (pdata->cs_control)
-			pdata->cs_control(spi, pol);
+			pdata->cs_control(spi, true);
 	}
 }

drivers/spi/spi-geni-qcom.c+80−4

@@ -83,6 +83,7 @@ struct spi_geni_master { · 82 unmodified lines
83	spinlock_t lock;	83	spinlock_t lock;
84	int irq;	84	int irq;
85	bool cs_flag;	85	bool cs_flag;
		86	bool abort_failed;
86	};	87	};
87		88
88	static int get_spi_clk_cfg(unsigned int speed_hz,	89	static int get_spi_clk_cfg(unsigned int speed_hz,
@@ -141,8 +142,49 @@ static void handle_fifo_timeout(struct spi_master *spi, · 52 unmodified lines
141	spin_unlock_irq(&mas->lock);	142	spin_unlock_irq(&mas->lock);
142		143
143	time_left = wait_for_completion_timeout(&mas->abort_done, HZ);	144	time_left = wait_for_completion_timeout(&mas->abort_done, HZ);
144	if (!time_left)	145	if (!time_left) {
145	dev_err(mas->dev, "Failed to cancel/abort m_cmd\n");	146	dev_err(mas->dev, "Failed to cancel/abort m_cmd\n");
		147
		148	/*
		149	* No need for a lock since SPI core has a lock and we never
		150	* access this from an interrupt.
		151	*/
		152	mas->abort_failed = true;
		153	}
		154	}
		155
		156	static bool spi_geni_is_abort_still_pending(struct spi_geni_master *mas)
		157	{
		158	struct geni_se *se = &mas->se;
		159	u32 m_irq, m_irq_en;
		160
		161	if (!mas->abort_failed)
		162	return false;
		163
		164	/*
		165	* The only known case where a transfer times out and then a cancel
		166	* times out then an abort times out is if something is blocking our
		167	* interrupt handler from running. Avoid starting any new transfers
		168	* until that sorts itself out.
		169	*/
		170	spin_lock_irq(&mas->lock);
		171	m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS);
		172	m_irq_en = readl(se->base + SE_GENI_M_IRQ_EN);
		173	spin_unlock_irq(&mas->lock);
		174
		175	if (m_irq & m_irq_en) {
		176	dev_err(mas->dev, "Interrupts pending after abort: %#010x\n",
		177	m_irq & m_irq_en);
		178	return true;
		179	}
		180
		181	/*
		182	* If we're here the problem resolved itself so no need to check more
		183	* on future transfers.
		184	*/
		185	mas->abort_failed = false;
		186
		187	return false;
146	}	188	}
147		189
148	static void spi_geni_set_cs(struct spi_device *slv, bool set_flag)	190	static void spi_geni_set_cs(struct spi_device *slv, bool set_flag)
@@ -158,10 +200,21 @@ static void spi_geni_set_cs(struct spi_device *slv, bool set_flag) · 9 unmodified lines
158	if (set_flag == mas->cs_flag)	200	if (set_flag == mas->cs_flag)
159	return;	201	return;
160		202
161	mas->cs_flag = set_flag;
162
163	pm_runtime_get_sync(mas->dev);	203	pm_runtime_get_sync(mas->dev);
		204
		205	if (spi_geni_is_abort_still_pending(mas)) {
		206	dev_err(mas->dev, "Can't set chip select\n");
		207	goto exit;
		208	}
		209
164	spin_lock_irq(&mas->lock);	210	spin_lock_irq(&mas->lock);
		211	if (mas->cur_xfer) {
		212	dev_err(mas->dev, "Can't set CS when prev xfer running\n");
		213	spin_unlock_irq(&mas->lock);
		214	goto exit;
		215	}
		216
		217	mas->cs_flag = set_flag;
165	reinit_completion(&mas->cs_done);	218	reinit_completion(&mas->cs_done);
166	if (set_flag)	219	if (set_flag)
167	geni_se_setup_m_cmd(se, SPI_CS_ASSERT, 0);	220	geni_se_setup_m_cmd(se, SPI_CS_ASSERT, 0);
@@ -170,9 +223,12 @@ static void spi_geni_set_cs(struct spi_device *slv, bool set_flag) · 2 unmodified lines
170	spin_unlock_irq(&mas->lock);	223	spin_unlock_irq(&mas->lock);
171		224
172	time_left = wait_for_completion_timeout(&mas->cs_done, HZ);	225	time_left = wait_for_completion_timeout(&mas->cs_done, HZ);
173	if (!time_left)	226	if (!time_left) {
		227	dev_warn(mas->dev, "Timeout setting chip select\n");
174	handle_fifo_timeout(spi, NULL);	228	handle_fifo_timeout(spi, NULL);
		229	}
175		230
		231	exit:
176	pm_runtime_put(mas->dev);	232	pm_runtime_put(mas->dev);
177	}	233	}
178		234
@@ -280,6 +336,9 @@ static int spi_geni_prepare_message(struct spi_master *spi, · 101 unmodified lines
280	int ret;	336	int ret;
281	struct spi_geni_master *mas = spi_master_get_devdata(spi);	337	struct spi_geni_master *mas = spi_master_get_devdata(spi);
282		338
		339	if (spi_geni_is_abort_still_pending(mas))
		340	return -EBUSY;
		341
283	ret = setup_fifo_params(spi_msg->spi, spi);	342	ret = setup_fifo_params(spi_msg->spi, spi);
284	if (ret)	343	if (ret)
285	dev_err(mas->dev, "Couldn't select mode %d\n", ret);	344	dev_err(mas->dev, "Couldn't select mode %d\n", ret);
@@ -354,6 +413,12 @@ static bool geni_spi_handle_tx(struct spi_geni_master *mas) · 68 unmodified lines
354	unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas);	413	unsigned int bytes_per_fifo_word = geni_byte_per_fifo_word(mas);
355	unsigned int i = 0;	414	unsigned int i = 0;
356		415
		416	/* Stop the watermark IRQ if nothing to send */
		417	if (!mas->cur_xfer) {
		418	writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
		419	return false;
		420	}
		421
357	max_bytes = (mas->tx_fifo_depth - mas->tx_wm) * bytes_per_fifo_word;	422	max_bytes = (mas->tx_fifo_depth - mas->tx_wm) * bytes_per_fifo_word;
358	if (mas->tx_rem_bytes < max_bytes)	423	if (mas->tx_rem_bytes < max_bytes)
359	max_bytes = mas->tx_rem_bytes;	424	max_bytes = mas->tx_rem_bytes;
@@ -396,6 +461,14 @@ static void geni_spi_handle_rx(struct spi_geni_master *mas) · 36 unmodified lines
396	if (rx_last_byte_valid && rx_last_byte_valid < 4)	461	if (rx_last_byte_valid && rx_last_byte_valid < 4)
397	rx_bytes -= bytes_per_fifo_word - rx_last_byte_valid;	462	rx_bytes -= bytes_per_fifo_word - rx_last_byte_valid;
398	}	463	}
		464
		465	/* Clear out the FIFO and bail if nowhere to put it */
		466	if (!mas->cur_xfer) {
		467	for (i = 0; i < DIV_ROUND_UP(rx_bytes, bytes_per_fifo_word); i++)
		468	readl(se->base + SE_GENI_RX_FIFOn);
		469	return;
		470	}
		471
399	if (mas->rx_rem_bytes < rx_bytes)	472	if (mas->rx_rem_bytes < rx_bytes)
400	rx_bytes = mas->rx_rem_bytes;	473	rx_bytes = mas->rx_rem_bytes;
401		474
@@ -495,6 +568,9 @@ static int spi_geni_transfer_one(struct spi_master *spi, · 93 unmodified lines
495	{	568	{
496	struct spi_geni_master *mas = spi_master_get_devdata(spi);	569	struct spi_geni_master *mas = spi_master_get_devdata(spi);
497		570
		571	if (spi_geni_is_abort_still_pending(mas))
		572	return -EBUSY;
		573
498	/* Terminate and return success for 0 byte length transfer */	574	/* Terminate and return success for 0 byte length transfer */
499	if (!xfer->len)	575	if (!xfer->len)
500	return 0;	576	return 0;

drivers/spi/spi-stm32.c+2−2

@@ -493,9 +493,9 @@ static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi, u32 xfer_len) · 492 unmodified lines
493		493
494	/* align packet size with data registers access */	494	/* align packet size with data registers access */
495	if (spi->cur_bpw > 8)	495	if (spi->cur_bpw > 8)
496	fthlv -= (fthlv % 2); /* multiple of 2 */	496	fthlv += (fthlv % 2) ? 1 : 0;
497	else	497	else
498	fthlv -= (fthlv % 4); /* multiple of 4 */	498	fthlv += (fthlv % 4) ? (4 - (fthlv % 4)) : 0;
499		499
500	if (!fthlv)	500	if (!fthlv)
501	fthlv = 1;	501	fthlv = 1;

drivers/spi/spi.c+8−3

 {
 	struct spi_statistics *statm = &ctlr->statistics;
 	struct spi_statistics *stats = &msg->spi->statistics;
+	u32 speed_hz = xfer->speed_hz;
 	unsigned long long ms;
 	if (spi_controller_is_slave(ctlr)) {
 			return -EINTR;
 		}
 	} else {
+		if (!speed_hz)
+			speed_hz = 100000;
 		ms = 8LL * 1000LL * xfer->len;
-		do_div(ms, xfer->speed_hz);
+		do_div(ms, speed_hz);
 		ms += ms + 200; /* some tolerance */
 		if (ms > UINT_MAX)
 	if (status)
 		return status;
-	if (!spi->max_speed_hz ||
+	if (spi->controller->max_speed_hz &&
-	    spi->max_speed_hz > spi->controller->max_speed_hz)
+	    (!spi->max_speed_hz ||
+	     spi->max_speed_hz > spi->controller->max_speed_hz))
 		spi->max_speed_hz = spi->controller->max_speed_hz;
 	mutex_lock(&spi->controller->io_mutex);

drivers/staging/comedi/comedi_fops.c+3−1

 	v32.chanlist_len = cmd->chanlist_len;
 	v32.data = ptr_to_compat(cmd->data);
 	v32.data_len = cmd->data_len;
-	return copy_to_user(cmd32, &v32, sizeof(v32));
+	if (copy_to_user(cmd32, &v32, sizeof(v32)))
+		return -EFAULT;
+	return 0;
 }
 /* Handle 32-bit COMEDI_CMD ioctl. */

drivers/staging/hikey9xx/hisi-spmi-controller.c+15−6

 	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!iores) {
 		dev_err(&pdev->dev, "can not get resource!\n");
-		return -EINVAL;
+		ret = -EINVAL;
+		goto err_put_controller;
 	}
 	spmi_controller->base = devm_ioremap(&pdev->dev, iores->start,
 					     resource_size(iores));
 	if (!spmi_controller->base) {
 		dev_err(&pdev->dev, "can not remap base addr!\n");
-		return -EADDRNOTAVAIL;
+		ret = -EADDRNOTAVAIL;
+		goto err_put_controller;
 	}
 	ret = of_property_read_u32(pdev->dev.of_node, "spmi-channel",
 				   &spmi_controller->channel);
 	if (ret) {
 		dev_err(&pdev->dev, "can not get channel\n");
-		return -ENODEV;
+		ret = -ENODEV;
+		goto err_put_controller;
 	}
 	platform_set_drvdata(pdev, spmi_controller);
 	ctrl->write_cmd = spmi_write_cmd;
 	ret = spmi_controller_add(ctrl);
-	if (ret)
+	if (ret) {
-		dev_err(&pdev->dev, "spmi_add_controller failed with error %d!\n", ret);
+		dev_err(&pdev->dev, "spmi_controller_add failed with error %d!\n", ret);
+		goto err_put_controller;
+	}
+	return 0;
+err_put_controller:
+	spmi_controller_put(ctrl);
 	return ret;
 }
 	struct spmi_controller *ctrl = platform_get_drvdata(pdev);
 	spmi_controller_remove(ctrl);
-	kfree(ctrl);
+	spmi_controller_put(ctrl);
 	return 0;
 }

drivers/staging/media/atomisp/pci/atomisp_subdev.c+0−20

@@ -1062,26 +1062,6 @@ static const struct v4l2_ctrl_config ctrl_select_isp_version = { · 1061 unmodified lines
1062	.def = 0,	1062	.def = 0,
1063	};	1063	};
1064		1064
1065	#if 0 /* #ifdef CONFIG_ION */
1066	/*
1067	* Control for ISP ion device fd
1068	*
1069	* userspace will open ion device and pass the fd to kernel.
1070	* this fd will be used to map shared fd to buffer.
1071	*/
1072	/* V4L2_CID_ATOMISP_ION_DEVICE_FD is not defined */
1073	static const struct v4l2_ctrl_config ctrl_ion_dev_fd = {
1074	.ops = &ctrl_ops,
1075	.id = V4L2_CID_ATOMISP_ION_DEVICE_FD,
1076	.type = V4L2_CTRL_TYPE_INTEGER,
1077	.name = "Ion Device Fd",
1078	.min = -1,
1079	.max = 1024,
1080	.step = 1,
1081	.def = ION_FD_UNSET
1082	};
1083	#endif
1084
1085	static void atomisp_init_subdev_pipe(struct atomisp_sub_device *asd,	1065	static void atomisp_init_subdev_pipe(struct atomisp_sub_device *asd,
1086	struct atomisp_video_pipe *pipe, enum v4l2_buf_type buf_type)	1066	struct atomisp_video_pipe *pipe, enum v4l2_buf_type buf_type)
1087	{	1067	{

drivers/staging/mt7621-dma/mtk-hsdma.c+3−1

 	ret = dma_async_device_register(dd);
 	if (ret) {
 		dev_err(&pdev->dev, "failed to register dma device\n");
-		return ret;
+		goto err_uninit_hsdma;
 	}
 	ret = of_dma_controller_register(pdev->dev.of_node,
 err_unregister:
 	dma_async_device_unregister(dd);
+err_uninit_hsdma:
+	mtk_hsdma_uninit(hsdma);
 	return ret;
 }

drivers/target/target_core_xcopy.c+70−49

@@ -46,60 +46,83 @@ static int target_xcopy_gen_naa_ieee(struct se_device dev, unsigned char buf) · 45 unmodified lines
46	return 0;	46	return 0;
47	}	47	}
48		48
49	struct xcopy_dev_search_info {	49	/**
50	const unsigned char *dev_wwn;	50	* target_xcopy_locate_se_dev_e4_iter - compare XCOPY NAA device identifiers
51	struct se_device *found_dev;	51	*
52	};	52	* @se_dev: device being considered for match
53		53	* @dev_wwn: XCOPY requested NAA dev_wwn
		54	* @return: 1 on match, 0 on no-match
		55	*/
54	static int target_xcopy_locate_se_dev_e4_iter(struct se_device *se_dev,	56	static int target_xcopy_locate_se_dev_e4_iter(struct se_device *se_dev,
55	void *data)	57	const unsigned char *dev_wwn)
56	{	58	{
57	struct xcopy_dev_search_info *info = data;
58	unsigned char tmp_dev_wwn[XCOPY_NAA_IEEE_REGEX_LEN];	59	unsigned char tmp_dev_wwn[XCOPY_NAA_IEEE_REGEX_LEN];
59	int rc;	60	int rc;
60		61
61	if (!se_dev->dev_attrib.emulate_3pc)	62	if (!se_dev->dev_attrib.emulate_3pc) {
		63	pr_debug("XCOPY: emulate_3pc disabled on se_dev %p\n", se_dev);
62	return 0;	64	return 0;
		65	}
63		66
64	memset(&tmp_dev_wwn[0], 0, XCOPY_NAA_IEEE_REGEX_LEN);	67	memset(&tmp_dev_wwn[0], 0, XCOPY_NAA_IEEE_REGEX_LEN);
65	target_xcopy_gen_naa_ieee(se_dev, &tmp_dev_wwn[0]);	68	target_xcopy_gen_naa_ieee(se_dev, &tmp_dev_wwn[0]);
66		69
67	rc = memcmp(&tmp_dev_wwn[0], info->dev_wwn, XCOPY_NAA_IEEE_REGEX_LEN);	70	rc = memcmp(&tmp_dev_wwn[0], dev_wwn, XCOPY_NAA_IEEE_REGEX_LEN);
68	if (rc != 0)
69	return 0;
70
71	info->found_dev = se_dev;
72	pr_debug("XCOPY 0xe4: located se_dev: %p\n", se_dev);
73
74	rc = target_depend_item(&se_dev->dev_group.cg_item);
75	if (rc != 0) {	71	if (rc != 0) {
76	pr_err("configfs_depend_item attempt failed: %d for se_dev: %p\n",	72	pr_debug("XCOPY: skip non-matching: %*ph\n",
77	rc, se_dev);	73	XCOPY_NAA_IEEE_REGEX_LEN, tmp_dev_wwn);
78	return rc;	74	return 0;
79	}	75	}
		76	pr_debug("XCOPY 0xe4: located se_dev: %p\n", se_dev);
80		77
81	pr_debug("Called configfs_depend_item for se_dev: %p se_dev->se_dev_group: %p\n",
82	se_dev, &se_dev->dev_group);
83	return 1;	78	return 1;
84	}	79	}
85		80
86	static int target_xcopy_locate_se_dev_e4(const unsigned char *dev_wwn,	81	static int target_xcopy_locate_se_dev_e4(struct se_session *sess,
87	struct se_device **found_dev)	82	const unsigned char *dev_wwn,
		83	struct se_device **_found_dev,
		84	struct percpu_ref **_found_lun_ref)
88	{	85	{
89	struct xcopy_dev_search_info info;	86	struct se_dev_entry *deve;
90	int ret;	87	struct se_node_acl *nacl;
91		88	struct se_lun *this_lun = NULL;
92	memset(&info, 0, sizeof(info));	89	struct se_device *found_dev = NULL;
93	info.dev_wwn = dev_wwn;	90
94		91	/* cmd with NULL sess indicates no associated $FABRIC_MOD */
95	ret = target_for_each_device(target_xcopy_locate_se_dev_e4_iter, &info);	92	if (!sess)
96	if (ret == 1) {	93	goto err_out;
97	*found_dev = info.found_dev;	94
98	return 0;	95	pr_debug("XCOPY 0xe4: searching for: %*ph\n",
99	} else {	96	XCOPY_NAA_IEEE_REGEX_LEN, dev_wwn);
100	pr_debug_ratelimited("Unable to locate 0xe4 descriptor for EXTENDED_COPY\n");	97
101	return -EINVAL;	98	nacl = sess->se_node_acl;
		99	rcu_read_lock();
		100	hlist_for_each_entry_rcu(deve, &nacl->lun_entry_hlist, link) {
		101	struct se_device *this_dev;
		102	int rc;
		103
		104	this_lun = rcu_dereference(deve->se_lun);
		105	this_dev = rcu_dereference_raw(this_lun->lun_se_dev);
		106
		107	rc = target_xcopy_locate_se_dev_e4_iter(this_dev, dev_wwn);
		108	if (rc) {
		109	if (percpu_ref_tryget_live(&this_lun->lun_ref))
		110	found_dev = this_dev;
		111	break;
		112	}
102	}	113	}
		114	rcu_read_unlock();
		115	if (found_dev == NULL)
		116	goto err_out;
		117
		118	pr_debug("lun_ref held for se_dev: %p se_dev->se_dev_group: %p\n",
		119	found_dev, &found_dev->dev_group);
		120	*_found_dev = found_dev;
		121	*_found_lun_ref = &this_lun->lun_ref;
		122	return 0;
		123	err_out:
		124	pr_debug_ratelimited("Unable to locate 0xe4 descriptor for EXTENDED_COPY\n");
		125	return -EINVAL;
103	}	126	}
104		127
105	static int target_xcopy_parse_tiddesc_e4(struct se_cmd se_cmd, struct xcopy_op xop,	128	static int target_xcopy_parse_tiddesc_e4(struct se_cmd se_cmd, struct xcopy_op xop,
@@ -246,12 +269,16 @@ static int target_xcopy_parse_target_descriptors(struct se_cmd *se_cmd, · 140 unmodified lines
246		269
247	switch (xop->op_origin) {	270	switch (xop->op_origin) {
248	case XCOL_SOURCE_RECV_OP:	271	case XCOL_SOURCE_RECV_OP:
249	rc = target_xcopy_locate_se_dev_e4(xop->dst_tid_wwn,	272	rc = target_xcopy_locate_se_dev_e4(se_cmd->se_sess,
250	&xop->dst_dev);	273	xop->dst_tid_wwn,
		274	&xop->dst_dev,
		275	&xop->remote_lun_ref);
251	break;	276	break;
252	case XCOL_DEST_RECV_OP:	277	case XCOL_DEST_RECV_OP:
253	rc = target_xcopy_locate_se_dev_e4(xop->src_tid_wwn,	278	rc = target_xcopy_locate_se_dev_e4(se_cmd->se_sess,
254	&xop->src_dev);	279	xop->src_tid_wwn,
		280	&xop->src_dev,
		281	&xop->remote_lun_ref);
255	break;	282	break;
256	default:	283	default:
257	pr_err("XCOPY CSCD descriptor IDs not found in CSCD list - "	284	pr_err("XCOPY CSCD descriptor IDs not found in CSCD list - "
@@ -391,18 +418,12 @@ static int xcopy_pt_get_cmd_state(struct se_cmd *se_cmd) · 133 unmodified lines
391		418
392	static void xcopy_pt_undepend_remotedev(struct xcopy_op *xop)	419	static void xcopy_pt_undepend_remotedev(struct xcopy_op *xop)
393	{	420	{
394	struct se_device *remote_dev;
395
396	if (xop->op_origin == XCOL_SOURCE_RECV_OP)	421	if (xop->op_origin == XCOL_SOURCE_RECV_OP)
397	remote_dev = xop->dst_dev;	422	pr_debug("putting dst lun_ref for %p\n", xop->dst_dev);
398	else	423	else
399	remote_dev = xop->src_dev;	424	pr_debug("putting src lun_ref for %p\n", xop->src_dev);
400
401	pr_debug("Calling configfs_undepend_item for"
402	" remote_dev: %p remote_dev->dev_group: %p\n",
403	remote_dev, &remote_dev->dev_group.cg_item);
404		425
405	target_undepend_item(&remote_dev->dev_group.cg_item);	426	percpu_ref_put(xop->remote_lun_ref);
406	}	427	}
407		428
408	static void xcopy_pt_release_cmd(struct se_cmd *se_cmd)	429	static void xcopy_pt_release_cmd(struct se_cmd *se_cmd)

drivers/target/target_core_xcopy.h+1−0

@@ -27,6 +27,7 @@ struct xcopy_op { · 26 unmodified lines
27	struct se_device *dst_dev;	27	struct se_device *dst_dev;
28	unsigned char dst_tid_wwn[XCOPY_NAA_IEEE_REGEX_LEN];	28	unsigned char dst_tid_wwn[XCOPY_NAA_IEEE_REGEX_LEN];
29	unsigned char local_dev_wwn[XCOPY_NAA_IEEE_REGEX_LEN];	29	unsigned char local_dev_wwn[XCOPY_NAA_IEEE_REGEX_LEN];
		30	struct percpu_ref *remote_lun_ref;
30		31
31	sector_t src_lba;	32	sector_t src_lba;
32	sector_t dst_lba;	33	sector_t dst_lba;

drivers/tty/Kconfig+14−0

@@ -401,6 +401,20 @@ config MIPS_EJTAG_FDC_KGDB_CHAN · 400 unmodified lines
401	help	401	help
402	FDC channel number to use for KGDB.	402	FDC channel number to use for KGDB.
403		403
		404	config NULL_TTY
		405	tristate "NULL TTY driver"
		406	help
		407	Say Y here if you want a NULL TTY which simply discards messages.
		408
		409	This is useful to allow userspace applications which expect a console
		410	device to work without modifications even when no console is
		411	available or desired.
		412
		413	In order to use this driver, you should redirect the console to this
		414	TTY, or boot the kernel with console=ttynull.
		415
		416	If unsure, say N.
		417
404	config TRACE_ROUTER	418	config TRACE_ROUTER
405	tristate "Trace data router for MIPI P1149.7 cJTAG standard"	419	tristate "Trace data router for MIPI P1149.7 cJTAG standard"
406	depends on TRACE_SINK	420	depends on TRACE_SINK

drivers/tty/Makefile+2−1

 obj-$(CONFIG_TTY)		+= tty_io.o n_tty.o tty_ioctl.o tty_ldisc.o \
 				   tty_buffer.o tty_port.o tty_mutex.o \
 				   tty_ldsem.o tty_baudrate.o tty_jobctrl.o \
-				   n_null.o ttynull.o
+				   n_null.o
 obj-$(CONFIG_LEGACY_PTYS)	+= pty.o
 obj-$(CONFIG_UNIX98_PTYS)	+= pty.o
 obj-$(CONFIG_AUDIT)		+= tty_audit.o
 obj-$(CONFIG_MOXA_INTELLIO)	+= moxa.o
 obj-$(CONFIG_MOXA_SMARTIO)	+= mxser.o
 obj-$(CONFIG_NOZOMI)		+= nozomi.o
+obj-$(CONFIG_NULL_TTY)	        += ttynull.o
 obj-$(CONFIG_ROCKETPORT)	+= rocket.o
 obj-$(CONFIG_SYNCLINK_GT)	+= synclink_gt.o
 obj-$(CONFIG_PPC_EPAPR_HV_BYTECHAN) += ehv_bytechan.o

drivers/tty/serial/sifive.c+1−0

@@ -1000,6 +1000,7 @@ static int sifive_serial_probe(struct platform_device *pdev) · 999 unmodified lines
1000	/* Set up clock divider */	1000	/* Set up clock divider */
1001	ssp->clkin_rate = clk_get_rate(ssp->clk);	1001	ssp->clkin_rate = clk_get_rate(ssp->clk);
1002	ssp->baud_rate = SIFIVE_DEFAULT_BAUD_RATE;	1002	ssp->baud_rate = SIFIVE_DEFAULT_BAUD_RATE;
		1003	ssp->port.uartclk = ssp->baud_rate * 16;
1003	__ssp_update_div(ssp);	1004	__ssp_update_div(ssp);
1004		1005
1005	platform_set_drvdata(pdev, ssp);	1006	platform_set_drvdata(pdev, ssp);

drivers/tty/ttynull.c+0−18

@@ -2,13 +2,6 @@ · 1 unmodified line
2	/*	2	/*
3	* Copyright (C) 2019 Axis Communications AB	3	* Copyright (C) 2019 Axis Communications AB
4	*	4	*
5	* The console is useful for userspace applications which expect a console
6	* device to work without modifications even when no console is available
7	* or desired.
8	*
9	* In order to use this driver, you should redirect the console to this
10	* TTY, or boot the kernel with console=ttynull.
11	*
12	* Based on ttyprintk.c:	5	* Based on ttyprintk.c:
13	* Copyright (C) 2010 Samo Pogacnik	6	* Copyright (C) 2010 Samo Pogacnik
14	*/	7	*/
@@ -66,17 +59,6 @@ static struct console ttynull_console = { · 51 unmodified lines
66	.device = ttynull_device,	59	.device = ttynull_device,
67	};	60	};
68		61
69	void __init register_ttynull_console(void)
70	{
71	if (!ttynull_driver)
72	return;
73
74	if (add_preferred_console(ttynull_console.name, 0, NULL))
75	return;
76
77	register_console(&ttynull_console);
78	}
79
80	static int __init ttynull_init(void)	62	static int __init ttynull_init(void)
81	{	63	{
82	struct tty_driver *driver;	64	struct tty_driver *driver;

drivers/usb/chipidea/ci_hdrc_imx.c+5−1

 	misc_pdev = of_find_device_by_node(args.np);
 	of_node_put(args.np);
-	if (!misc_pdev || !platform_get_drvdata(misc_pdev))
+	if (!misc_pdev)
 		return ERR_PTR(-EPROBE_DEFER);
+	if (!platform_get_drvdata(misc_pdev)) {
+		put_device(&misc_pdev->dev);
+		return ERR_PTR(-EPROBE_DEFER);
+	}
 	data->dev = &misc_pdev->dev;
 	/*

drivers/usb/class/cdc-acm.c+4−0

 	{ USB_DEVICE(0x04d8, 0xfd08),
 	.driver_info = IGNORE_DEVICE,
 	},
+	{ USB_DEVICE(0x04d8, 0xf58b),
+	.driver_info = IGNORE_DEVICE,
+	},
 #endif
 	/*Samsung phone in firmware update mode */

drivers/usb/class/cdc-wdm.c+13−3

 	if (!desc->resp_count || !--desc->resp_count)
 		goto out;
+	if (test_bit(WDM_DISCONNECTING, &desc->flags)) {
+		rv = -ENODEV;
+		goto out;
+	}
+	if (test_bit(WDM_RESETTING, &desc->flags)) {
+		rv = -EIO;
+		goto out;
+	}
 	set_bit(WDM_RESPONDING, &desc->flags);
 	spin_unlock_irq(&desc->iuspin);
 	rv = usb_submit_urb(desc->response, GFP_KERNEL);
 	spin_lock_irq(&desc->iuspin);
 	if (rv) {
-		dev_err(&desc->intf->dev,
+		if (!test_bit(WDM_DISCONNECTING, &desc->flags))
-			"usb_submit_urb failed with result %d\n", rv);
+			dev_err(&desc->intf->dev,
+				"usb_submit_urb failed with result %d\n", rv);
 		/* make sure the next notification trigger a submit */
 		clear_bit(WDM_RESPONDING, &desc->flags);
 	wake_up_all(&desc->wait);
 	mutex_lock(&desc->rlock);
 	mutex_lock(&desc->wlock);
-	kill_urbs(desc);
 	cancel_work_sync(&desc->rxwork);
 	cancel_work_sync(&desc->service_outs_intr);
+	kill_urbs(desc);
 	mutex_unlock(&desc->wlock);
 	mutex_unlock(&desc->rlock);

drivers/usb/class/usblp.c+19−2

@@ -274,8 +274,25 @@ static int usblp_ctrl_msg(struct usblp *usblp, int request, int type, int dir, i · 273 unmodified lines
274	#define usblp_reset(usblp)\	274	#define usblp_reset(usblp)\
275	usblp_ctrl_msg(usblp, USBLP_REQ_RESET, USB_TYPE_CLASS, USB_DIR_OUT, USB_RECIP_OTHER, 0, NULL, 0)	275	usblp_ctrl_msg(usblp, USBLP_REQ_RESET, USB_TYPE_CLASS, USB_DIR_OUT, USB_RECIP_OTHER, 0, NULL, 0)
276		276
277	#define usblp_hp_channel_change_request(usblp, channel, buffer) \	277	static int usblp_hp_channel_change_request(struct usblp usblp, int channel, u8 new_channel)
278	usblp_ctrl_msg(usblp, USBLP_REQ_HP_CHANNEL_CHANGE_REQUEST, USB_TYPE_VENDOR, USB_DIR_IN, USB_RECIP_INTERFACE, channel, buffer, 1)	278	{
		279	u8 *buf;
		280	int ret;
		281
		282	buf = kzalloc(1, GFP_KERNEL);
		283	if (!buf)
		284	return -ENOMEM;
		285
		286	ret = usblp_ctrl_msg(usblp, USBLP_REQ_HP_CHANNEL_CHANGE_REQUEST,
		287	USB_TYPE_VENDOR, USB_DIR_IN, USB_RECIP_INTERFACE,
		288	channel, buf, 1);
		289	if (ret == 0)
		290	*new_channel = buf[0];
		291
		292	kfree(buf);
		293
		294	return ret;
		295	}
279		296
280	/*	297	/*
281	* See the description for usblp_select_alts() below for the usage	298	* See the description for usblp_select_alts() below for the usage

drivers/usb/core/hcd.c+3−5

 	urb->status = status;
 	/*
 	 * This function can be called in task context inside another remote
-	 * coverage collection section, but KCOV doesn't support that kind of
+	 * coverage collection section, but kcov doesn't support that kind of
 	 * recursion yet. Only collect coverage in softirq context for now.
 	 */
-	if (in_serving_softirq())
+	kcov_remote_start_usb_softirq((u64)urb->dev->bus->busnum);
-		kcov_remote_start_usb((u64)urb->dev->bus->busnum);
 	urb->complete(urb);
-	if (in_serving_softirq())
+	kcov_remote_stop_softirq();
-		kcov_remote_stop();
 	usb_anchor_resume_wakeups(anchor);
 	atomic_dec(&urb->use_count);

drivers/usb/dwc3/core.h+1−0

@@ -285,6 +285,7 @@ · 284 unmodified lines
285		285
286	/* Global USB2 PHY Vendor Control Register */	286	/* Global USB2 PHY Vendor Control Register */
287	#define DWC3_GUSB2PHYACC_NEWREGREQ BIT(25)	287	#define DWC3_GUSB2PHYACC_NEWREGREQ BIT(25)
		288	#define DWC3_GUSB2PHYACC_DONE BIT(24)
288	#define DWC3_GUSB2PHYACC_BUSY BIT(23)	289	#define DWC3_GUSB2PHYACC_BUSY BIT(23)
289	#define DWC3_GUSB2PHYACC_WRITE BIT(22)	290	#define DWC3_GUSB2PHYACC_WRITE BIT(22)
290	#define DWC3_GUSB2PHYACC_ADDR(n) (n << 16)	291	#define DWC3_GUSB2PHYACC_ADDR(n) (n << 16)

drivers/usb/dwc3/dwc3-meson-g12a.c+1−1

@@ -754,7 +754,7 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev) · 753 unmodified lines
754		754
755	ret = priv->drvdata->setup_regmaps(priv, base);	755	ret = priv->drvdata->setup_regmaps(priv, base);
756	if (ret)	756	if (ret)
757	return ret;	757	goto err_disable_clks;
758		758
759	if (priv->vbus) {	759	if (priv->vbus) {
760	ret = regulator_enable(priv->vbus);	760	ret = regulator_enable(priv->vbus);

drivers/usb/dwc3/gadget.c+5−11

 			list_for_each_entry_safe(r, t, &dep->started_list, list)
 				dwc3_gadget_move_cancelled_request(r);
+			dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE;
 			goto out;
 		}
 	}
 static void dwc3_gadget_disable_irq(struct dwc3 *dwc);
 static void __dwc3_gadget_stop(struct dwc3 *dwc);
+static int __dwc3_gadget_start(struct dwc3 *dwc);
 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
 {
 			dwc->ev_buf->lpos = (dwc->ev_buf->lpos + count) %
 						dwc->ev_buf->length;
 		}
+	} else {
+		__dwc3_gadget_start(dwc);
 	}
 	ret = dwc3_gadget_run_stop(dwc, is_on, false);
 	}
 	dwc->gadget_driver	= driver;
-	if (pm_runtime_active(dwc->dev))
-		__dwc3_gadget_start(dwc);
 	spin_unlock_irqrestore(&dwc->lock, flags);
 	return 0;
 	unsigned long		flags;
 	spin_lock_irqsave(&dwc->lock, flags);
-	if (pm_runtime_suspended(dwc->dev))
-		goto out;
-	__dwc3_gadget_stop(dwc);
-out:
 	dwc->gadget_driver	= NULL;
 	spin_unlock_irqrestore(&dwc->lock, flags);

drivers/usb/dwc3/ulpi.c+21−17

  * Author: Heikki Krogerus <heikki.krogerus@linux.intel.com>
  */
+#include <linux/delay.h>
+#include <linux/time64.h>
 #include <linux/ulpi/regs.h>
 #include "core.h"
 		DWC3_GUSB2PHYACC_ADDR(ULPI_ACCESS_EXTENDED) | \
 		DWC3_GUSB2PHYACC_EXTEND_ADDR(a) : DWC3_GUSB2PHYACC_ADDR(a))
-static int dwc3_ulpi_busyloop(struct dwc3 *dwc)
+#define DWC3_ULPI_BASE_DELAY	DIV_ROUND_UP(NSEC_PER_SEC, 60000000L)
+static int dwc3_ulpi_busyloop(struct dwc3 *dwc, u8 addr, bool read)
 {
-	unsigned int count = 1000;
+	unsigned long ns = 5L * DWC3_ULPI_BASE_DELAY;
+	unsigned int count = 10000;
 	u32 reg;
+	if (addr >= ULPI_EXT_VENDOR_SPECIFIC)
+		ns += DWC3_ULPI_BASE_DELAY;
+	if (read)
+		ns += DWC3_ULPI_BASE_DELAY;
+	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
+	if (reg & DWC3_GUSB2PHYCFG_SUSPHY)
+		usleep_range(1000, 1200);
 	while (count--) {
+		ndelay(ns);
 		reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYACC(0));
-		if (!(reg & DWC3_GUSB2PHYACC_BUSY))
+		if (reg & DWC3_GUSB2PHYACC_DONE)
 			return 0;
 		cpu_relax();
 	}
 	u32 reg;
 	int ret;
-	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
-	if (reg & DWC3_GUSB2PHYCFG_SUSPHY) {
-		reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
-		dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
-	}
 	reg = DWC3_GUSB2PHYACC_NEWREGREQ | DWC3_ULPI_ADDR(addr);
 	dwc3_writel(dwc->regs, DWC3_GUSB2PHYACC(0), reg);
-	ret = dwc3_ulpi_busyloop(dwc);
+	ret = dwc3_ulpi_busyloop(dwc, addr, true);
 	if (ret)
 		return ret;
 	struct dwc3 *dwc = dev_get_drvdata(dev);
 	u32 reg;
-	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
-	if (reg & DWC3_GUSB2PHYCFG_SUSPHY) {
-		reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
-		dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
-	}
 	reg = DWC3_GUSB2PHYACC_NEWREGREQ | DWC3_ULPI_ADDR(addr);
 	reg |= DWC3_GUSB2PHYACC_WRITE | val;
 	dwc3_writel(dwc->regs, DWC3_GUSB2PHYACC(0), reg);
-	return dwc3_ulpi_busyloop(dwc);
+	return dwc3_ulpi_busyloop(dwc, addr, false);
 }
 static const struct ulpi_ops dwc3_ulpi_ops = {

drivers/usb/gadget/Kconfig+2−0

 	depends on NET
 	select USB_U_ETHER
 	select USB_F_NCM
+	select CRC32
 	help
 	  NCM is an advanced protocol for Ethernet encapsulation, allows
 	  grouping of several ethernet frames into one USB transfer and
 	depends on NET
 	select USB_U_ETHER
 	select USB_F_EEM
+	select CRC32
 	help
 	  CDC EEM is a newer USB standard that is somewhat simpler than CDC ECM
 	  and therefore can be supported by more hardware.  Technically ECM and

drivers/usb/gadget/composite.c+8−2

 	spin_lock_irqsave(&cdev->lock, flags);
-	if (cdev->deactivations == 0)
+	if (cdev->deactivations == 0) {
+		spin_unlock_irqrestore(&cdev->lock, flags);
 		status = usb_gadget_deactivate(cdev->gadget);
+		spin_lock_irqsave(&cdev->lock, flags);
+	}
 	if (status == 0)
 		cdev->deactivations++;
 		status = -EINVAL;
 	else {
 		cdev->deactivations--;
-		if (cdev->deactivations == 0)
+		if (cdev->deactivations == 0) {
+			spin_unlock_irqrestore(&cdev->lock, flags);
 			status = usb_gadget_activate(cdev->gadget);
+			spin_lock_irqsave(&cdev->lock, flags);
+		}
 	}
 	spin_unlock_irqrestore(&cdev->lock, flags);

drivers/usb/gadget/configfs.c+13−6

 static ssize_t gadget_dev_desc_UDC_show(struct config_item *item, char *page)
 {
-	char *udc_name = to_gadget_info(item)->composite.gadget_driver.udc_name;
+	struct gadget_info *gi = to_gadget_info(item);
+	char *udc_name;
+	int ret;
+	mutex_lock(&gi->lock);
+	udc_name = gi->composite.gadget_driver.udc_name;
+	ret = sprintf(page, "%s\n", udc_name ?: "");
+	mutex_unlock(&gi->lock);
-	return sprintf(page, "%s\n", udc_name ?: "");
+	return ret;
 }
 static int unregister_gadget(struct gadget_info *gi)
 		cfg = container_of(c, struct config_usb_cfg, c);
-		list_for_each_entry_safe(f, tmp, &c->functions, list) {
+		list_for_each_entry_safe_reverse(f, tmp, &c->functions, list) {
-			list_move_tail(&f->list, &cfg->func_list);
+			list_move(&f->list, &cfg->func_list);
 			if (f->unbind) {
 				dev_dbg(&gi->cdev.gadget->dev,
 					"unbind function '%s'/%p\n",
 	.suspend	= configfs_composite_suspend,
 	.resume		= configfs_composite_resume,
-	.max_speed	= USB_SPEED_SUPER,
+	.max_speed	= USB_SPEED_SUPER_PLUS,
 	.driver = {
 		.owner          = THIS_MODULE,
 		.name		= "configfs-gadget",
 	gi->composite.unbind = configfs_do_nothing;
 	gi->composite.suspend = NULL;
 	gi->composite.resume = NULL;
-	gi->composite.max_speed = USB_SPEED_SUPER;
+	gi->composite.max_speed = USB_SPEED_SUPER_PLUS;
 	spin_lock_init(&gi->spinlock);
 	mutex_init(&gi->lock);

drivers/usb/gadget/function/f_printer.c+1−0

@@ -1162,6 +1162,7 @@ fail_tx_reqs: · 1161 unmodified lines
1162	printer_req_free(dev->in_ep, req);	1162	printer_req_free(dev->in_ep, req);
1163	}	1163	}
1164		1164
		1165	usb_free_all_descriptors(f);
1165	return ret;	1166	return ret;
1166		1167
1167	}	1168	}

drivers/usb/gadget/function/f_uac2.c+55−14

 	.bEndpointAddress = USB_DIR_OUT,
 	.bmAttributes = USB_ENDPOINT_XFER_ISOC | USB_ENDPOINT_SYNC_ASYNC,
-	.wMaxPacketSize = cpu_to_le16(1023),
+	/* .wMaxPacketSize = DYNAMIC */
 	.bInterval = 1,
 };
 	.bDescriptorType = USB_DT_ENDPOINT,
 	.bmAttributes = USB_ENDPOINT_XFER_ISOC | USB_ENDPOINT_SYNC_ASYNC,
-	.wMaxPacketSize = cpu_to_le16(1024),
+	/* .wMaxPacketSize = DYNAMIC */
 	.bInterval = 4,
 };
 	.bEndpointAddress = USB_DIR_IN,
 	.bmAttributes = USB_ENDPOINT_XFER_ISOC | USB_ENDPOINT_SYNC_ASYNC,
-	.wMaxPacketSize = cpu_to_le16(1023),
+	/* .wMaxPacketSize = DYNAMIC */
 	.bInterval = 1,
 };
 	.bDescriptorType = USB_DT_ENDPOINT,
 	.bmAttributes = USB_ENDPOINT_XFER_ISOC | USB_ENDPOINT_SYNC_ASYNC,
-	.wMaxPacketSize = cpu_to_le16(1024),
+	/* .wMaxPacketSize = DYNAMIC */
 	.bInterval = 4,
 };
 	__le32	dRES;
 } __packed;
-static void set_ep_max_packet_size(const struct f_uac2_opts *uac2_opts,
+static int set_ep_max_packet_size(const struct f_uac2_opts *uac2_opts,
 	struct usb_endpoint_descriptor *ep_desc,
-	unsigned int factor, bool is_playback)
+	enum usb_device_speed speed, bool is_playback)
 {
 	int chmask, srate, ssize;
-	u16 max_packet_size;
+	u16 max_size_bw, max_size_ep;
+	unsigned int factor;
+	switch (speed) {
+	case USB_SPEED_FULL:
+		max_size_ep = 1023;
+		factor = 1000;
+		break;
+	case USB_SPEED_HIGH:
+		max_size_ep = 1024;
+		factor = 8000;
+		break;
+	default:
+		return -EINVAL;
+	}
 	if (is_playback) {
 		chmask = uac2_opts->p_chmask;
 		ssize = uac2_opts->c_ssize;
 	}
-	max_packet_size = num_channels(chmask) * ssize *
+	max_size_bw = num_channels(chmask) * ssize *
 		DIV_ROUND_UP(srate, factor / (1 << (ep_desc->bInterval - 1)));
-	ep_desc->wMaxPacketSize = cpu_to_le16(min_t(u16, max_packet_size,
+	ep_desc->wMaxPacketSize = cpu_to_le16(min_t(u16, max_size_bw,
-				le16_to_cpu(ep_desc->wMaxPacketSize)));
+						    max_size_ep));
+	return 0;
 }
 /* Use macro to overcome line length limitation */
 	}
 	/* Calculate wMaxPacketSize according to audio bandwidth */
-	set_ep_max_packet_size(uac2_opts, &fs_epin_desc, 1000, true);
+	ret = set_ep_max_packet_size(uac2_opts, &fs_epin_desc, USB_SPEED_FULL,
-	set_ep_max_packet_size(uac2_opts, &fs_epout_desc, 1000, false);
+				     true);
-	set_ep_max_packet_size(uac2_opts, &hs_epin_desc, 8000, true);
+	if (ret < 0) {
-	set_ep_max_packet_size(uac2_opts, &hs_epout_desc, 8000, false);
+		dev_err(dev, "%s:%d Error!\n", __func__, __LINE__);
+		return ret;
+	}
+	ret = set_ep_max_packet_size(uac2_opts, &fs_epout_desc, USB_SPEED_FULL,
+				     false);
+	if (ret < 0) {
+		dev_err(dev, "%s:%d Error!\n", __func__, __LINE__);
+		return ret;
+	}
+	ret = set_ep_max_packet_size(uac2_opts, &hs_epin_desc, USB_SPEED_HIGH,
+				     true);
+	if (ret < 0) {
+		dev_err(dev, "%s:%d Error!\n", __func__, __LINE__);
+		return ret;
+	}
+	ret = set_ep_max_packet_size(uac2_opts, &hs_epout_desc, USB_SPEED_HIGH,
+				     false);
+	if (ret < 0) {
+		dev_err(dev, "%s:%d Error!\n", __func__, __LINE__);
+		return ret;
+	}
 	if (EPOUT_EN(uac2_opts)) {
 		agdev->out_ep = usb_ep_autoconfig(gadget, &fs_epout_desc);

drivers/usb/gadget/function/u_ether.c+5−4

 #define UETH__VERSION	"29-May-2008"
 /* Experiments show that both Linux and Windows hosts allow up to 16k
- * frame sizes. Set the max size to 15k+52 to prevent allocating 32k
+ * frame sizes. Set the max MTU size to 15k+52 to prevent allocating 32k
  * blocks and still have efficient handling. */
-#define GETHER_MAX_ETH_FRAME_LEN 15412
+#define GETHER_MAX_MTU_SIZE 15412
+#define GETHER_MAX_ETH_FRAME_LEN (GETHER_MAX_MTU_SIZE + ETH_HLEN)
 struct eth_dev {
 	/* lock is held while accessing port_usb
 	/* MTU range: 14 - 15412 */
 	net->min_mtu = ETH_HLEN;
-	net->max_mtu = GETHER_MAX_ETH_FRAME_LEN;
+	net->max_mtu = GETHER_MAX_MTU_SIZE;
 	dev->gadget = g;
 	SET_NETDEV_DEV(net, &g->dev);
 	/* MTU range: 14 - 15412 */
 	net->min_mtu = ETH_HLEN;
-	net->max_mtu = GETHER_MAX_ETH_FRAME_LEN;
+	net->max_mtu = GETHER_MAX_MTU_SIZE;
 	return net;
 }

drivers/usb/gadget/legacy/acm_ms.c+3−1

 		struct usb_descriptor_header *usb_desc;
 		usb_desc = usb_otg_descriptor_alloc(gadget);
-		if (!usb_desc)
+		if (!usb_desc) {
+			status = -ENOMEM;
 			goto fail_string_ids;
+		}
 		usb_otg_descriptor_init(gadget, usb_desc);
 		otg_desc[0] = usb_desc;
 		otg_desc[1] = NULL;

drivers/usb/gadget/udc/Kconfig+1−1

@@ -90,7 +90,7 @@ config USB_BCM63XX_UDC · 89 unmodified lines
90		90
91	config USB_FSL_USB2	91	config USB_FSL_USB2
92	tristate "Freescale Highspeed USB DR Peripheral Controller"	92	tristate "Freescale Highspeed USB DR Peripheral Controller"
93	depends on FSL_SOC \|\| ARCH_MXC	93	depends on FSL_SOC
94	help	94	help
95	Some of Freescale PowerPC and i.MX processors have a High Speed	95	Some of Freescale PowerPC and i.MX processors have a High Speed
96	Dual-Role(DR) USB controller, which supports device mode.	96	Dual-Role(DR) USB controller, which supports device mode.

drivers/usb/gadget/udc/Makefile+0−1

@@ -23,7 +23,6 @@ obj-$(CONFIG_USB_ATMEL_USBA) += atmel_usba_udc.o · 22 unmodified lines
23	obj-$(CONFIG_USB_BCM63XX_UDC) += bcm63xx_udc.o	23	obj-$(CONFIG_USB_BCM63XX_UDC) += bcm63xx_udc.o
24	obj-$(CONFIG_USB_FSL_USB2) += fsl_usb2_udc.o	24	obj-$(CONFIG_USB_FSL_USB2) += fsl_usb2_udc.o
25	fsl_usb2_udc-y := fsl_udc_core.o	25	fsl_usb2_udc-y := fsl_udc_core.o
26	fsl_usb2_udc-$(CONFIG_ARCH_MXC) += fsl_mxc_udc.o
27	obj-$(CONFIG_USB_TEGRA_XUDC) += tegra-xudc.o	26	obj-$(CONFIG_USB_TEGRA_XUDC) += tegra-xudc.o
28	obj-$(CONFIG_USB_M66592) += m66592-udc.o	27	obj-$(CONFIG_USB_M66592) += m66592-udc.o
29	obj-$(CONFIG_USB_R8A66597) += r8a66597-udc.o	28	obj-$(CONFIG_USB_R8A66597) += r8a66597-udc.o

drivers/usb/gadget/udc/core.c+1−2

  *
  * Enables the D+ (or potentially D-) pullup.  The host will start
  * enumerating this gadget when the pullup is active and a VBUS session
- * is active (the link is powered).  This pullup is always enabled unless
+ * is active (the link is powered).
- * usb_gadget_disconnect() has been used to disable it.
  *
  * Returns zero on success, else negative errno.
  */

drivers/usb/gadget/udc/dummy_hcd.c+23−12

 				dum_hcd->port_status &= ~USB_PORT_STAT_POWER;
 			set_link_state(dum_hcd);
 			break;
-		default:
+		case USB_PORT_FEAT_ENABLE:
+		case USB_PORT_FEAT_C_ENABLE:
+		case USB_PORT_FEAT_C_SUSPEND:
+			/* Not allowed for USB-3 */
+			if (hcd->speed == HCD_USB3)
+				goto error;
+			fallthrough;
+		case USB_PORT_FEAT_C_CONNECTION:
+		case USB_PORT_FEAT_C_RESET:
 			dum_hcd->port_status &= ~(1 << wValue);
 			set_link_state(dum_hcd);
+			break;
+		default:
+		/* Disallow INDICATOR and C_OVER_CURRENT */
+			goto error;
 		}
 		break;
 	case GetHubDescriptor:
 			 */
 			dum_hcd->re_timeout = jiffies + msecs_to_jiffies(50);
 			fallthrough;
+		case USB_PORT_FEAT_C_CONNECTION:
+		case USB_PORT_FEAT_C_RESET:
+		case USB_PORT_FEAT_C_ENABLE:
+		case USB_PORT_FEAT_C_SUSPEND:
+			/* Not allowed for USB-3, and ignored for USB-2 */
+			if (hcd->speed == HCD_USB3)
+				goto error;
+			break;
 		default:
-			if (hcd->speed == HCD_USB3) {
+		/* Disallow TEST, INDICATOR, and C_OVER_CURRENT */
-				if ((dum_hcd->port_status &
+			goto error;
-				     USB_SS_PORT_STAT_POWER) != 0) {
-					dum_hcd->port_status |= (1 << wValue);
-				}
-			} else
-				if ((dum_hcd->port_status &
-				     USB_PORT_STAT_POWER) != 0) {
-					dum_hcd->port_status |= (1 << wValue);
-				}
-			set_link_state(dum_hcd);
 		}
 		break;
 	case GetPortErrorCount:

drivers/usb/gadget/udc/fsl_mxc_udc.c+0−122

@@ -1,122 +0,0 @@
1	// SPDX-License-Identifier: GPL-2.0+
2	/*
3	* Copyright (C) 2009
4	* Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
5	*
6	* Description:
7	* Helper routines for i.MX3x SoCs from Freescale, needed by the fsl_usb2_udc.c
8	* driver to function correctly on these systems.
9	*/
10	#include <linux/clk.h>
11	#include <linux/delay.h>
12	#include <linux/err.h>
13	#include <linux/fsl_devices.h>
14	#include <linux/mod_devicetable.h>
15	#include <linux/platform_device.h>
16	#include <linux/io.h>
17
18	#include "fsl_usb2_udc.h"
19
20	static struct clk *mxc_ahb_clk;
21	static struct clk *mxc_per_clk;
22	static struct clk *mxc_ipg_clk;
23
24	/* workaround ENGcm09152 for i.MX35 */
25	#define MX35_USBPHYCTRL_OFFSET 0x600
26	#define USBPHYCTRL_OTGBASE_OFFSET 0x8
27	#define USBPHYCTRL_EVDO (1 << 23)
28
29	int fsl_udc_clk_init(struct platform_device *pdev)
30	{
31	struct fsl_usb2_platform_data *pdata;
32	unsigned long freq;
33	int ret;
34
35	pdata = dev_get_platdata(&pdev->dev);
36
37	mxc_ipg_clk = devm_clk_get(&pdev->dev, "ipg");
38	if (IS_ERR(mxc_ipg_clk)) {
39	dev_err(&pdev->dev, "clk_get(\"ipg\") failed\n");
40	return PTR_ERR(mxc_ipg_clk);
41	}
42
43	mxc_ahb_clk = devm_clk_get(&pdev->dev, "ahb");
44	if (IS_ERR(mxc_ahb_clk)) {
45	dev_err(&pdev->dev, "clk_get(\"ahb\") failed\n");
46	return PTR_ERR(mxc_ahb_clk);
47	}
48
49	mxc_per_clk = devm_clk_get(&pdev->dev, "per");
50	if (IS_ERR(mxc_per_clk)) {
51	dev_err(&pdev->dev, "clk_get(\"per\") failed\n");
52	return PTR_ERR(mxc_per_clk);
53	}
54
55	clk_prepare_enable(mxc_ipg_clk);
56	clk_prepare_enable(mxc_ahb_clk);
57	clk_prepare_enable(mxc_per_clk);
58
59	/* make sure USB_CLK is running at 60 MHz +/- 1000 Hz */
60	if (!strcmp(pdev->id_entry->name, "imx-udc-mx27")) {
61	freq = clk_get_rate(mxc_per_clk);
62	if (pdata->phy_mode != FSL_USB2_PHY_ULPI &&
63	(freq < 59999000 \|\| freq > 60001000)) {
64	dev_err(&pdev->dev, "USB_CLK=%lu, should be 60MHz\n", freq);
65	ret = -EINVAL;
66	goto eclkrate;
67	}
68	}
69
70	return 0;
71
72	eclkrate:
73	clk_disable_unprepare(mxc_ipg_clk);
74	clk_disable_unprepare(mxc_ahb_clk);
75	clk_disable_unprepare(mxc_per_clk);
76	mxc_per_clk = NULL;
77	return ret;
78	}
79
80	int fsl_udc_clk_finalize(struct platform_device *pdev)
81	{
82	struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev);
83	int ret = 0;
84
85	/* workaround ENGcm09152 for i.MX35 */
86	if (pdata->workaround & FLS_USB2_WORKAROUND_ENGCM09152) {
87	unsigned int v;
88	struct resource *res = platform_get_resource
89	(pdev, IORESOURCE_MEM, 0);
90	void __iomem *phy_regs = ioremap(res->start +
91	MX35_USBPHYCTRL_OFFSET, 512);
92	if (!phy_regs) {
93	dev_err(&pdev->dev, "ioremap for phy address fails\n");
94	ret = -EINVAL;
95	goto ioremap_err;
96	}
97
98	v = readl(phy_regs + USBPHYCTRL_OTGBASE_OFFSET);
99	writel(v \| USBPHYCTRL_EVDO,
100	phy_regs + USBPHYCTRL_OTGBASE_OFFSET);
101
102	iounmap(phy_regs);
103	}
104
105
106	ioremap_err:
107	/* ULPI transceivers don't need usbpll */
108	if (pdata->phy_mode == FSL_USB2_PHY_ULPI) {
109	clk_disable_unprepare(mxc_per_clk);
110	mxc_per_clk = NULL;
111	}
112
113	return ret;
114	}
115
116	void fsl_udc_clk_release(void)
117	{
118	if (mxc_per_clk)
119	clk_disable_unprepare(mxc_per_clk);
120	clk_disable_unprepare(mxc_ahb_clk);
121	clk_disable_unprepare(mxc_ipg_clk);
122	}

drivers/usb/host/xhci.c+12−12

 {
 	unsigned long long timeout_ns;
+	if (xhci->quirks & XHCI_INTEL_HOST)
+		timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
+	else
+		timeout_ns = udev->u1_params.sel;
 	/* Prevent U1 if service interval is shorter than U1 exit latency */
 	if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
-		if (xhci_service_interval_to_ns(desc) <= udev->u1_params.mel) {
+		if (xhci_service_interval_to_ns(desc) <= timeout_ns) {
 			dev_dbg(&udev->dev, "Disable U1, ESIT shorter than exit latency\n");
 			return USB3_LPM_DISABLED;
 		}
 	}
-	if (xhci->quirks & XHCI_INTEL_HOST)
-		timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
-	else
-		timeout_ns = udev->u1_params.sel;
 	/* The U1 timeout is encoded in 1us intervals.
 	 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
 	 */
 {
 	unsigned long long timeout_ns;
+	if (xhci->quirks & XHCI_INTEL_HOST)
+		timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
+	else
+		timeout_ns = udev->u2_params.sel;
 	/* Prevent U2 if service interval is shorter than U2 exit latency */
 	if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
-		if (xhci_service_interval_to_ns(desc) <= udev->u2_params.mel) {
+		if (xhci_service_interval_to_ns(desc) <= timeout_ns) {
 			dev_dbg(&udev->dev, "Disable U2, ESIT shorter than exit latency\n");
 			return USB3_LPM_DISABLED;
 		}
 	}
-	if (xhci->quirks & XHCI_INTEL_HOST)
-		timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
-	else
-		timeout_ns = udev->u2_params.sel;
 	/* The U2 timeout is encoded in 256us intervals */
 	timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
 	/* If the necessary timeout value is bigger than what we can set in the

drivers/usb/misc/yurex.c+3−0

@@ -496,6 +496,9 @@ static ssize_t yurex_write(struct file file, const char __user user_buffer, · 495 unmodified lines
496	timeout = schedule_timeout(YUREX_WRITE_TIMEOUT);	496	timeout = schedule_timeout(YUREX_WRITE_TIMEOUT);
497	finish_wait(&dev->waitq, &wait);	497	finish_wait(&dev->waitq, &wait);
498		498
		499	/* make sure URB is idle after timeout or (spurious) CMD_ACK */
		500	usb_kill_urb(dev->cntl_urb);
		501
499	mutex_unlock(&dev->io_mutex);	502	mutex_unlock(&dev->io_mutex);
500		503
501	if (retval < 0) {	504	if (retval < 0) {

drivers/usb/serial/iuu_phoenix.c+15−5

 	struct device *dev = &port->dev;
 	int i;
 	int status;
-	u8 rxcmd = IUU_UART_RX;
+	u8 *rxcmd;
 	struct iuu_private *priv = usb_get_serial_port_data(port);
 	if (iuu_led(port, 0xF000, 0, 0, 0xFF) < 0)
 		return -EIO;
+	rxcmd = kmalloc(1, GFP_KERNEL);
+	if (!rxcmd)
+		return -ENOMEM;
+	rxcmd[0] = IUU_UART_RX;
 	for (i = 0; i < 2; i++) {
-		status = bulk_immediate(port, &rxcmd, 1);
+		status = bulk_immediate(port, rxcmd, 1);
 		if (status != IUU_OPERATION_OK) {
 			dev_dbg(dev, "%s - uart_flush_write error\n", __func__);
-			return status;
+			goto out_free;
 		}
 		status = read_immediate(port, &priv->len, 1);
 		if (status != IUU_OPERATION_OK) {
 			dev_dbg(dev, "%s - uart_flush_read error\n", __func__);
-			return status;
+			goto out_free;
 		}
 		if (priv->len > 0) {
 			status = read_immediate(port, priv->buf, priv->len);
 			if (status != IUU_OPERATION_OK) {
 				dev_dbg(dev, "%s - uart_flush_read error\n", __func__);
-				return status;
+				goto out_free;
 			}
 		}
 	}
 	dev_dbg(dev, "%s - uart_flush_read OK!\n", __func__);
 	iuu_led(port, 0, 0xF000, 0, 0xFF);
+out_free:
+	kfree(rxcmd);
 	return status;
 }

drivers/usb/serial/option.c+3−0

 	{ USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM12, 0xff, 0xff, 0xff),
 	  .driver_info = RSVD(1) | RSVD(2) | RSVD(3) | RSVD(4) | NUMEP2 },
 	{ USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM12, 0xff, 0, 0) },
+	{ USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, 0x0620, 0xff, 0xff, 0x30) },	/* EM160R-GL */
+	{ USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, 0x0620, 0xff, 0, 0) },
 	{ USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_RM500Q, 0xff, 0xff, 0x30) },
 	{ USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_RM500Q, 0xff, 0, 0) },
 	{ USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_RM500Q, 0xff, 0xff, 0x10),
 	{ USB_DEVICE_INTERFACE_CLASS(0x2cb7, 0x0105, 0xff),			/* Fibocom NL678 series */
 	  .driver_info = RSVD(6) },
 	{ USB_DEVICE_INTERFACE_CLASS(0x2cb7, 0x01a0, 0xff) },			/* Fibocom NL668-AM/NL652-EU (laptop MBIM) */
+	{ USB_DEVICE_INTERFACE_CLASS(0x2df3, 0x9d03, 0xff) },			/* LongSung M5710 */
 	{ USB_DEVICE_INTERFACE_CLASS(0x305a, 0x1404, 0xff) },			/* GosunCn GM500 RNDIS */
 	{ USB_DEVICE_INTERFACE_CLASS(0x305a, 0x1405, 0xff) },			/* GosunCn GM500 MBIM */
 	{ USB_DEVICE_INTERFACE_CLASS(0x305a, 0x1406, 0xff) },			/* GosunCn GM500 ECM/NCM */

drivers/usb/storage/unusual_uas.h+7−0

@@ -90,6 +90,13 @@ UNUSUAL_DEV(0x152d, 0x0578, 0x0000, 0x9999, · 89 unmodified lines
90	USB_SC_DEVICE, USB_PR_DEVICE, NULL,	90	USB_SC_DEVICE, USB_PR_DEVICE, NULL,
91	US_FL_BROKEN_FUA),	91	US_FL_BROKEN_FUA),
92		92
		93	/* Reported-by: Thinh Nguyen <thinhn@synopsys.com> */
		94	UNUSUAL_DEV(0x154b, 0xf00b, 0x0000, 0x9999,
		95	"PNY",
		96	"Pro Elite SSD",
		97	USB_SC_DEVICE, USB_PR_DEVICE, NULL,
		98	US_FL_NO_ATA_1X),
		99
93	/* Reported-by: Thinh Nguyen <thinhn@synopsys.com> */	100	/* Reported-by: Thinh Nguyen <thinhn@synopsys.com> */
94	UNUSUAL_DEV(0x154b, 0xf00d, 0x0000, 0x9999,	101	UNUSUAL_DEV(0x154b, 0xf00d, 0x0000, 0x9999,
95	"PNY",	102	"PNY",

drivers/usb/typec/altmodes/Kconfig+1−1

@@ -20,6 +20,6 @@ config TYPEC_NVIDIA_ALTMODE · 19 unmodified lines
20	to enable support for VirtualLink devices with NVIDIA GPUs.	20	to enable support for VirtualLink devices with NVIDIA GPUs.
21		21
22	To compile this driver as a module, choose M here: the	22	To compile this driver as a module, choose M here: the
23	module will be called typec_displayport.	23	module will be called typec_nvidia.
24		24
25	endmenu	25	endmenu

drivers/usb/typec/class.c+2−0

 		return ret;
 	sysfs_notify(&partner->dev.kobj, NULL, "number_of_alternate_modes");
+	kobject_uevent(&partner->dev.kobj, KOBJ_CHANGE);
 	return 0;
 }
 		return ret;
 	sysfs_notify(&plug->dev.kobj, NULL, "number_of_alternate_modes");
+	kobject_uevent(&plug->dev.kobj, KOBJ_CHANGE);
 	return 0;
 }

drivers/usb/typec/mux/intel_pmc_mux.c+11−0

@@ -207,10 +207,21 @@ static int · 206 unmodified lines
207	pmc_usb_mux_dp_hpd(struct pmc_usb_port port, struct typec_displayport_data dp)	207	pmc_usb_mux_dp_hpd(struct pmc_usb_port port, struct typec_displayport_data dp)
208	{	208	{
209	u8 msg[2] = { };	209	u8 msg[2] = { };
		210	int ret;
210		211
211	msg[0] = PMC_USB_DP_HPD;	212	msg[0] = PMC_USB_DP_HPD;
212	msg[0] \|= port->usb3_port << PMC_USB_MSG_USB3_PORT_SHIFT;	213	msg[0] \|= port->usb3_port << PMC_USB_MSG_USB3_PORT_SHIFT;
213		214
		215	/* Configure HPD first if HPD,IRQ comes together */
		216	if (!IOM_PORT_HPD_ASSERTED(port->iom_status) &&
		217	dp->status & DP_STATUS_IRQ_HPD &&
		218	dp->status & DP_STATUS_HPD_STATE) {
		219	msg[1] = PMC_USB_DP_HPD_LVL;
		220	ret = pmc_usb_command(port, msg, sizeof(msg));
		221	if (ret)
		222	return ret;
		223	}
		224
214	if (dp->status & DP_STATUS_IRQ_HPD)	225	if (dp->status & DP_STATUS_IRQ_HPD)
215	msg[1] = PMC_USB_DP_HPD_IRQ;	226	msg[1] = PMC_USB_DP_HPD_IRQ;
216		227

drivers/usb/usbip/vhci_hcd.c+2−0

 		default:
 			usbip_dbg_vhci_rh(" ClearPortFeature: default %x\n",
 					  wValue);
+			if (wValue >= 32)
+				goto error;
 			vhci_hcd->port_status[rhport] &= ~(1 << wValue);
 			break;
 		}

drivers/vhost/net.c+3−3

@@ -863,6 +863,7 @@ static void handle_tx_zerocopy(struct vhost_net net, struct socket sock) · 862 unmodified lines
863	size_t len, total_len = 0;	863	size_t len, total_len = 0;
864	int err;	864	int err;
865	struct vhost_net_ubuf_ref *ubufs;	865	struct vhost_net_ubuf_ref *ubufs;
		866	struct ubuf_info *ubuf;
866	bool zcopy_used;	867	bool zcopy_used;

22 more lines aren’t shown here.

drivers/vhost/vsock.c+65−3

This diff is large: its 124 lines aren’t shown here.

drivers/xen/events/events_base.c+0−10

This diff is large: its 17 lines aren’t shown here.

drivers/xen/platform-pci.c+7−1

This diff is large: its 22 lines aren’t shown here.

drivers/xen/privcmd.c+19−6

This diff is large: its 52 lines aren’t shown here.

drivers/xen/xenbus/xenbus.h+1−0

This diff is large: its 8 lines aren’t shown here.

drivers/xen/xenbus/xenbus_comms.c+0−8

This diff is large: its 17 lines aren’t shown here.

drivers/xen/xenbus/xenbus_probe.c+67−14

This diff is large: its 109 lines aren’t shown here.

fs/afs/dir.c+26−23

This diff is large: its 84 lines aren’t shown here.

fs/afs/dir_edit.c+2−4

This diff is large: its 20 lines aren’t shown here.

fs/afs/xdr_fs.h+21−4

This diff is large: its 37 lines aren’t shown here.

fs/block_dev.c+6−3

This diff is large: its 52 lines aren’t shown here.

fs/btrfs/btrfs_inode.h+9−0

This diff is large: its 16 lines aren’t shown here.

fs/btrfs/ctree.c+22−2

This diff is large: its 38 lines aren’t shown here.

fs/btrfs/ctree.h+27−2

This diff is large: its 60 lines aren’t shown here.

fs/btrfs/dev-replace.c+1−1

This diff is large: its 9 lines aren’t shown here.

fs/btrfs/discard.c+36−34

This diff is large: its 143 lines aren’t shown here.

fs/btrfs/disk-io.c+9−6

This diff is large: its 57 lines aren’t shown here.

fs/btrfs/extent-tree.c+2−0

This diff is large: its 16 lines aren’t shown here.

fs/btrfs/extent_io.c+1−3

This diff is large: its 11 lines aren’t shown here.

fs/btrfs/file-item.c+2−0

This diff is large: its 11 lines aren’t shown here.

fs/btrfs/inode.c+51−18

This diff is large: its 127 lines aren’t shown here.

fs/btrfs/ioctl.c+1−1

This diff is large: its 9 lines aren’t shown here.

fs/btrfs/print-tree.c+5−5

This diff is large: its 28 lines aren’t shown here.

fs/btrfs/print-tree.h+1−1

This diff is large: its 8 lines aren’t shown here.

fs/btrfs/qgroup.c+30−13

This diff is large: its 92 lines aren’t shown here.

fs/btrfs/reflink.c+15−0

This diff is large: its 29 lines aren’t shown here.

fs/btrfs/relocation.c+6−1

This diff is large: its 18 lines aren’t shown here.

fs/btrfs/send.c+31−18

This diff is large: its 182 lines aren’t shown here.

fs/btrfs/space-info.c+3−1

This diff is large: its 11 lines aren’t shown here.

fs/btrfs/super.c+37−3

This diff is large: its 79 lines aren’t shown here.

fs/btrfs/tests/btrfs-tests.c+8−2

This diff is large: its 17 lines aren’t shown here.

fs/btrfs/tests/inode-tests.c+0−9

This diff is large: its 23 lines aren’t shown here.

fs/btrfs/tree-checker.c+7−0

This diff is large: its 21 lines aren’t shown here.

fs/btrfs/volumes.c+2−2

This diff is large: its 18 lines aren’t shown here.

fs/ceph/mds_client.c+22−31

This diff is large: its 98 lines aren’t shown here.

fs/cifs/connect.c+1−1

This diff is large: its 9 lines aren’t shown here.

fs/cifs/dfs_cache.c+2−1

This diff is large: its 10 lines aren’t shown here.

fs/cifs/fs_context.c+1−3

This diff is large: its 18 lines aren’t shown here.

fs/cifs/smb2pdu.c+1−1

This diff is large: its 9 lines aren’t shown here.

fs/cifs/smb2pdu.h+1−1

This diff is large: its 9 lines aren’t shown here.

fs/ext4/ext4_jbd2.c+0−17

This diff is large: its 21 lines aren’t shown here.

fs/ext4/ext4_jbd2.h+0−5

This diff is large: its 19 lines aren’t shown here.

fs/ext4/fast_commit.c+18−17

This diff is large: its 146 lines aren’t shown here.

fs/ext4/file.c+5−2

This diff is large: its 15 lines aren’t shown here.

fs/ext4/inode.c+5−1

This diff is large: its 15 lines aren’t shown here.

fs/ext4/ioctl.c+3−0

This diff is large: its 11 lines aren’t shown here.

fs/ext4/namei.c+17−10

This diff is large: its 83 lines aren’t shown here.

fs/ext4/resize.c+16−4

This diff is large: its 76 lines aren’t shown here.

fs/ext4/super.c+118−72

This diff is large: its 375 lines aren’t shown here.

fs/ext4/xattr.c+4−1

This diff is large: its 13 lines aren’t shown here.

fs/file.c+0−2

This diff is large: its 16 lines aren’t shown here.

fs/io_uring.c+248−112

This diff is large: its 769 lines aren’t shown here.

fs/namespace.c+5−2

This diff is large: its 28 lines aren’t shown here.

fs/nfs/delegation.c+7−5

This diff is large: its 30 lines aren’t shown here.

fs/nfs/internal.h+30−8

This diff is large: its 53 lines aren’t shown here.

fs/nfs/nfs4proc.c+11−17

This diff is large: its 71 lines aren’t shown here.

fs/nfs/nfs4super.c+2−2

This diff is large: its 18 lines aren’t shown here.

fs/nfs/pnfs.c+35−32

This diff is large: its 129 lines aren’t shown here.

fs/nfs/pnfs.h+3−5

This diff is large: its 22 lines aren’t shown here.

fs/nfs/pnfs_nfs.c+10−12

This diff is large: its 55 lines aren’t shown here.

fs/nfsd/nfs3xdr.c+6−1

This diff is large: its 16 lines aren’t shown here.

fs/nfsd/nfs4proc.c+5−0

This diff is large: its 12 lines aren’t shown here.

fs/nfsd/nfs4xdr.c+36−20

This diff is large: its 153 lines aren’t shown here.

fs/nfsd/nfssvc.c+0−6

This diff is large: its 13 lines aren’t shown here.

fs/nfsd/xdr4.h+0−1

This diff is large: its 8 lines aren’t shown here.

fs/notify/fanotify/fanotify_user.c+7−10

This diff is large: its 34 lines aren’t shown here.

fs/proc/task_mmu.c+30−23

This diff is large: its 94 lines aren’t shown here.

fs/select.c+11−3

This diff is large: its 33 lines aren’t shown here.

fs/zonefs/Kconfig+1−0

This diff is large: its 8 lines aren’t shown here.

include/asm-generic/Kbuild+1−0

This diff is large: its 8 lines aren’t shown here.

include/asm-generic/bitops/atomic.h+3−3

This diff is large: its 23 lines aren’t shown here.

include/kvm/arm_pmu.h+1−1

This diff is large: its 9 lines aren’t shown here.

include/linux/acpi.h+7−0

This diff is large: its 14 lines aren’t shown here.

include/linux/blk-mq.h+2−2

This diff is large: its 11 lines aren’t shown here.

include/linux/blkdev.h+13−5

This diff is large: its 39 lines aren’t shown here.

include/linux/build_bug.h+0−5

This diff is large: its 10 lines aren’t shown here.

include/linux/ceph/msgr.h+2−2

This diff is large: its 11 lines aren’t shown here.

include/linux/compiler-gcc.h+6−0

This diff is large: its 13 lines aren’t shown here.

include/linux/compiler_attributes.h+6−0

This diff is large: its 13 lines aren’t shown here.

include/linux/compiler_types.h+0−6

This diff is large: its 13 lines aren’t shown here.

include/linux/console.h+0−3

This diff is large: its 13 lines aren’t shown here.

include/linux/dm-bufio.h+1−0

This diff is large: its 8 lines aren’t shown here.

include/linux/intel-iommu.h+12−6

This diff is large: its 54 lines aren’t shown here.

include/linux/kasan.h+5−1

This diff is large: its 14 lines aren’t shown here.

include/linux/kcov.h+21−0

This diff is large: its 35 lines aren’t shown here.

include/linux/kdev_t.h+11−11

This diff is large: its 73 lines aren’t shown here.

include/linux/memcontrol.h+1−1

This diff is large: its 9 lines aren’t shown here.

include/linux/mlx5/mlx5_ifc.h+2−1

This diff is large: its 10 lines aren’t shown here.

include/linux/mm.h+10−2

This diff is large: its 26 lines aren’t shown here.

include/linux/perf/arm_pmu.h+0−2

This diff is large: its 9 lines aren’t shown here.

include/linux/rcupdate.h+6−0

This diff is large: its 13 lines aren’t shown here.

include/linux/sizes.h+3−0

This diff is large: its 10 lines aren’t shown here.

include/linux/skbuff.h+2−1

This diff is large: its 17 lines aren’t shown here.

include/linux/syscalls.h+24−0

This diff is large: its 31 lines aren’t shown here.

include/net/red.h+3−1

This diff is large: its 16 lines aren’t shown here.

include/net/xdp_sock.h+0−4

This diff is large: its 11 lines aren’t shown here.

include/net/xsk_buff_pool.h+5−0

This diff is large: its 12 lines aren’t shown here.

include/soc/nps/common.h+0−172

This diff is large: its 173 lines aren’t shown here.

include/soc/nps/mtm.h+0−59

This diff is large: its 60 lines aren’t shown here.

include/trace/events/afs.h+2−0

This diff is large: its 16 lines aren’t shown here.

include/trace/events/sunrpc.h+53−6

This diff is large: its 88 lines aren’t shown here.

include/uapi/linux/bcache.h+1−1

This diff is large: its 9 lines aren’t shown here.

include/uapi/linux/if_link.h+3−2

This diff is large: its 12 lines aren’t shown here.

include/uapi/linux/kvm.h+2−0

This diff is large: its 16 lines aren’t shown here.

include/uapi/linux/netfilter/nf_tables.h+3−0

This diff is large: its 24 lines aren’t shown here.

include/uapi/linux/ppp-ioctl.h+1−1

This diff is large: its 9 lines aren’t shown here.

include/uapi/misc/habanalabs.h+5−0

This diff is large: its 26 lines aren’t shown here.

include/xen/xenbus.h+1−1

This diff is large: its 9 lines aren’t shown here.

init/main.c+3−8

This diff is large: its 25 lines aren’t shown here.

kernel/bpf/hashtab.c+1−0

This diff is large: its 8 lines aren’t shown here.

kernel/bpf/syscall.c+0−1

This diff is large: its 8 lines aren’t shown here.

kernel/bpf/task_iter.c+9−8

This diff is large: its 31 lines aren’t shown here.

kernel/cgroup/cgroup-v1.c+2−0

This diff is large: its 9 lines aren’t shown here.

kernel/cgroup/cgroup.c+15−15

This diff is large: its 135 lines aren’t shown here.

kernel/configs/android-recommended.config+0−1

This diff is large: its 8 lines aren’t shown here.

kernel/exit.c+2−0

This diff is large: its 16 lines aren’t shown here.

kernel/rcu/tasks.h+21−4

This diff is large: its 67 lines aren’t shown here.

kernel/signal.c+3−0

This diff is large: its 10 lines aren’t shown here.

kernel/trace/Kconfig+1−1

This diff is large: its 9 lines aren’t shown here.

kernel/trace/trace_kprobe.c+1−1

This diff is large: its 9 lines aren’t shown here.

kernel/workqueue.c+10−3

This diff is large: its 28 lines aren’t shown here.

lib/Kconfig.debug+0−8

This diff is large: its 15 lines aren’t shown here.

lib/fonts/font_ter16x32.c+3−3

This diff is large: its 20 lines aren’t shown here.

lib/genalloc.c+13−12

This diff is large: its 84 lines aren’t shown here.

lib/iov_iter.c+1−1

This diff is large: its 9 lines aren’t shown here.

lib/raid6/Makefile+1−1

This diff is large: its 9 lines aren’t shown here.

lib/zlib_dfltcc/Makefile+1−1

This diff is large: its 6 lines aren’t shown here.

lib/zlib_dfltcc/dfltcc.c+5−1

This diff is large: its 17 lines aren’t shown here.

lib/zlib_dfltcc/dfltcc_deflate.c+3−0

This diff is large: its 21 lines aren’t shown here.

lib/zlib_dfltcc/dfltcc_inflate.c+2−2

This diff is large: its 18 lines aren’t shown here.

lib/zlib_dfltcc/dfltcc_syms.c+0−17

This diff is large: its 18 lines aren’t shown here.

mm/hugetlb.c+22−2

This diff is large: its 41 lines aren’t shown here.

mm/kasan/generic.c+2−0

This diff is large: its 9 lines aren’t shown here.

mm/kasan/init.c+2−1

This diff is large: its 10 lines aren’t shown here.

mm/memory-failure.c+1−1

This diff is large: its 9 lines aren’t shown here.

mm/memory.c+5−3

This diff is large: its 17 lines aren’t shown here.

mm/memory_hotplug.c+1−1

This diff is large: its 9 lines aren’t shown here.

mm/mempolicy.c+1−1

This diff is large: its 9 lines aren’t shown here.

mm/mremap.c+3−1

This diff is large: its 11 lines aren’t shown here.

mm/page-writeback.c+1−1

This diff is large: its 9 lines aren’t shown here.

mm/page_alloc.c+21−18

This diff is large: its 82 lines aren’t shown here.

mm/process_vm_access.c+1−0

This diff is large: its 8 lines aren’t shown here.

mm/slub.c+3−4

This diff is large: its 28 lines aren’t shown here.

mm/vmalloc.c+3−1

This diff is large: its 12 lines aren’t shown here.

mm/vmscan.c+2−0

This diff is large: its 9 lines aren’t shown here.

net/8021q/vlan.c+1−2

This diff is large: its 10 lines aren’t shown here.

net/can/isotp.c+1−0

This diff is large: its 8 lines aren’t shown here.

net/ceph/messenger_v2.c+12−3

This diff is large: its 31 lines aren’t shown here.

net/core/dev.c+24−13

This diff is large: its 59 lines aren’t shown here.

net/core/neighbour.c+2−4

This diff is large: its 13 lines aren’t shown here.

net/core/net-sysfs.c+53−12

This diff is large: its 148 lines aren’t shown here.

net/core/rtnetlink.c+6−17

This diff is large: its 33 lines aren’t shown here.

net/core/skbuff.c+49−8

This diff is large: its 121 lines aren’t shown here.

net/core/sock_reuseport.c+1−1

This diff is large: its 9 lines aren’t shown here.

net/dcb/dcbnl.c+2−0

This diff is large: its 9 lines aren’t shown here.

net/dsa/dsa2.c+4−0

This diff is large: its 14 lines aren’t shown here.

net/dsa/master.c+10−0

This diff is large: its 19 lines aren’t shown here.

net/ipv4/esp4.c+1−6

This diff is large: its 24 lines aren’t shown here.

net/ipv4/fib_frontend.c+1−1

This diff is large: its 9 lines aren’t shown here.

net/ipv4/gre_demux.c+1−1

This diff is large: its 9 lines aren’t shown here.

net/ipv4/ip_output.c+1−1

This diff is large: its 9 lines aren’t shown here.

net/ipv4/ip_tunnel.c+5−6

This diff is large: its 25 lines aren’t shown here.

net/ipv4/netfilter/arp_tables.c+1−1

This diff is large: its 9 lines aren’t shown here.

net/ipv4/netfilter/ip_tables.c+1−1

This diff is large: its 9 lines aren’t shown here.

net/ipv4/nexthop.c+4−2

This diff is large: its 21 lines aren’t shown here.

net/ipv6/esp6.c+1−6

This diff is large: its 24 lines aren’t shown here.

net/ipv6/ip6_fib.c+2−3

This diff is large: its 19 lines aren’t shown here.

net/ipv6/ip6_output.c+40−1

This diff is large: its 57 lines aren’t shown here.

net/ipv6/netfilter/ip6_tables.c+1−1

This diff is large: its 9 lines aren’t shown here.

net/ipv6/sit.c+4−1

This diff is large: its 13 lines aren’t shown here.

net/lapb/lapb_iface.c+1−0

This diff is large: its 8 lines aren’t shown here.

net/mptcp/protocol.c+27−47

This diff is large: its 137 lines aren’t shown here.

net/ncsi/ncsi-rsp.c+1−1

This diff is large: its 9 lines aren’t shown here.

net/netfilter/ipset/ip_set_hash_gen.h+18−24

This diff is large: its 77 lines aren’t shown here.

net/netfilter/nf_conntrack_standalone.c+3−0

This diff is large: its 10 lines aren’t shown here.

net/netfilter/nf_nat_core.c+1−0

This diff is large: its 8 lines aren’t shown here.

net/netfilter/nf_tables_api.c+7−3

This diff is large: its 31 lines aren’t shown here.

net/netfilter/nft_dynset.c+10−5

This diff is large: its 52 lines aren’t shown here.

net/netfilter/xt_RATEEST.c+3−0

This diff is large: its 10 lines aren’t shown here.

net/packet/af_packet.c+3−1

This diff is large: its 11 lines aren’t shown here.

net/qrtr/ns.c+4−3

This diff is large: its 33 lines aren’t shown here.

net/qrtr/qrtr.c+11−5

This diff is large: its 25 lines aren’t shown here.

net/qrtr/qrtr.h+1−1

This diff is large: its 9 lines aren’t shown here.

net/rxrpc/input.c+1−1

This diff is large: its 9 lines aren’t shown here.

net/rxrpc/key.c+4−2

This diff is large: its 20 lines aren’t shown here.

net/sched/sch_choke.c+1−1

This diff is large: its 9 lines aren’t shown here.

net/sched/sch_gred.c+1−1

This diff is large: its 9 lines aren’t shown here.

net/sched/sch_red.c+1−1

This diff is large: its 9 lines aren’t shown here.

net/sched/sch_sfq.c+1−1

This diff is large: its 9 lines aren’t shown here.

net/sched/sch_taprio.c+4−3

This diff is large: its 21 lines aren’t shown here.

net/smc/smc_core.c+13−7

This diff is large: its 64 lines aren’t shown here.

net/smc/smc_ib.c+3−3

This diff is large: its 20 lines aren’t shown here.

net/smc/smc_ism.c+2−1

This diff is large: its 10 lines aren’t shown here.

net/sunrpc/addr.c+1−1

This diff is large: its 9 lines aren’t shown here.

net/sunrpc/svc_xprt.c+2−2

This diff is large: its 25 lines aren’t shown here.

net/sunrpc/svcsock.c+85−1

This diff is large: its 100 lines aren’t shown here.

net/tipc/link.c+8−3

This diff is large: its 45 lines aren’t shown here.

net/tipc/node.c+1−1

This diff is large: its 9 lines aren’t shown here.

net/wireless/Kconfig+1−0

This diff is large: its 8 lines aren’t shown here.

net/xdp/xsk.c+13−3

This diff is large: its 63 lines aren’t shown here.

net/xdp/xsk_buff_pool.c+1−2

This diff is large: its 14 lines aren’t shown here.

net/xdp/xsk_queue.h+5−0

This diff is large: its 12 lines aren’t shown here.

scripts/checkpatch.pl+6−0

This diff is large: its 13 lines aren’t shown here.

scripts/config+1−0

This diff is large: its 8 lines aren’t shown here.

scripts/depmod.sh+2−0

This diff is large: its 9 lines aren’t shown here.

scripts/gcc-plugins/Makefile+2−2

This diff is large: its 12 lines aren’t shown here.

scripts/kconfig/Makefile+0−10

This diff is large: its 17 lines aren’t shown here.

scripts/kconfig/mconf-cfg.sh+3−1

This diff is large: its 11 lines aren’t shown here.

security/lsm_audit.c+5−2

This diff is large: its 22 lines aren’t shown here.

sound/firewire/fireface/ff-transaction.c+1−1

This diff is large: its 9 lines aren’t shown here.

sound/firewire/tascam/tascam-transaction.c+1−1

This diff is large: its 9 lines aren’t shown here.

sound/pci/hda/hda_intel.c+6−5

This diff is large: its 33 lines aren’t shown here.

sound/pci/hda/hda_tegra.c+1−1

This diff is large: its 9 lines aren’t shown here.

sound/pci/hda/patch_conexant.c+1−0

This diff is large: its 8 lines aren’t shown here.

sound/pci/hda/patch_hdmi.c+1−1

This diff is large: its 9 lines aren’t shown here.

sound/pci/hda/patch_realtek.c+15−1

This diff is large: its 63 lines aren’t shown here.

sound/pci/hda/patch_via.c+13−0

This diff is large: its 39 lines aren’t shown here.

sound/soc/amd/raven/pci-acp3x.c+3−13

This diff is large: its 50 lines aren’t shown here.

sound/soc/amd/renoir/rn-pci-acp3x.c+14−0

This diff is large: its 21 lines aren’t shown here.

sound/soc/atmel/Kconfig+2−2

This diff is large: its 16 lines aren’t shown here.

sound/soc/codecs/Kconfig+1−1

This diff is large: its 9 lines aren’t shown here.

sound/soc/codecs/max98373-i2c.c+20−0

This diff is large: its 48 lines aren’t shown here.

sound/soc/codecs/max98373-sdw.c+20−0

This diff is large: its 48 lines aren’t shown here.

sound/soc/codecs/max98373.c+31−3

This diff is large: its 55 lines aren’t shown here.

sound/soc/codecs/max98373.h+8−0

This diff is large: its 22 lines aren’t shown here.

sound/soc/codecs/rt711.c+6−0

This diff is large: its 30 lines aren’t shown here.

sound/soc/fsl/imx-hdmi.c+1−0

This diff is large: its 8 lines aren’t shown here.

sound/soc/intel/boards/haswell.c+1−0

This diff is large: its 8 lines aren’t shown here.

sound/soc/intel/skylake/cnl-sst.c+1−0

This diff is large: its 8 lines aren’t shown here.

sound/soc/meson/axg-tdm-interface.c+13−1

This diff is large: its 22 lines aren’t shown here.

sound/soc/meson/axg-tdmin.c+2−11

This diff is large: its 29 lines aren’t shown here.

sound/soc/qcom/lpass-cpu.c+2−18

This diff is large: its 42 lines aren’t shown here.

sound/soc/qcom/lpass-platform.c+35−15

This diff is large: its 107 lines aren’t shown here.

sound/soc/sh/rcar/adg.c+10−8

This diff is large: its 36 lines aren’t shown here.

sound/soc/soc-dapm.c+1−0

This diff is large: its 8 lines aren’t shown here.

sound/soc/sof/Kconfig+1−1

This diff is large: its 9 lines aren’t shown here.

sound/usb/card.c+2−3

This diff is large: its 20 lines aren’t shown here.

sound/usb/card.h+3−0

This diff is large: its 24 lines aren’t shown here.

sound/usb/endpoint.c+72−12

This diff is large: its 176 lines aren’t shown here.

sound/usb/endpoint.h+1−1

This diff is large: its 9 lines aren’t shown here.

sound/usb/implicit.c+46−15

This diff is large: its 165 lines aren’t shown here.

sound/usb/midi.c+4−0

This diff is large: its 18 lines aren’t shown here.

sound/usb/quirks-table.h+6−0

This diff is large: its 48 lines aren’t shown here.

sound/usb/quirks.c+46−12

This diff is large: its 108 lines aren’t shown here.

sound/usb/usbaudio.h+1−0

This diff is large: its 8 lines aren’t shown here.

tools/bootconfig/scripts/bconf2ftrace.sh+1−0

This diff is large: its 8 lines aren’t shown here.

tools/bootconfig/scripts/ftrace2bconf.sh+4−0

This diff is large: its 11 lines aren’t shown here.

tools/bpf/bpftool/net.c+0−1

This diff is large: its 8 lines aren’t shown here.

tools/bpf/resolve_btfids/main.c+12−5

This diff is large: its 49 lines aren’t shown here.

tools/include/linux/build_bug.h+0−5

This diff is large: its 10 lines aren’t shown here.

tools/include/uapi/linux/kvm.h+2−0

This diff is large: its 16 lines aren’t shown here.

tools/lib/perf/tests/test-cpumap.c+1−1

This diff is large: its 7 lines aren’t shown here.

tools/lib/perf/tests/test-evlist.c+4−3

This diff is large: its 39 lines aren’t shown here.

tools/lib/perf/tests/test-evsel.c+1−1

This diff is large: its 7 lines aren’t shown here.

tools/lib/perf/tests/test-threadmap.c+1−1

This diff is large: its 7 lines aren’t shown here.

tools/perf/examples/bpf/5sec.c+1−1

This diff is large: its 9 lines aren’t shown here.

tools/perf/tests/shell/stat+shadow_stat.sh+14−16

This diff is large: its 79 lines aren’t shown here.

tools/perf/util/header.c+8−0

This diff is large: its 15 lines aren’t shown here.

tools/perf/util/machine.c+2−2

This diff is large: its 18 lines aren’t shown here.

tools/perf/util/session.c+1−1

This diff is large: its 9 lines aren’t shown here.

tools/perf/util/stat-shadow.c+189−177

This diff is large: its 840 lines aren’t shown here.

tools/testing/kunit/kunit_kernel.py+1−1

This diff is large: its 9 lines aren’t shown here.

tools/testing/selftests/Makefile+4−2

This diff is large: its 13 lines aren’t shown here.

tools/testing/selftests/arm64/fp/fpsimd-test.S+1−1

This diff is large: its 9 lines aren’t shown here.

tools/testing/selftests/arm64/fp/sve-test.S+1−1

This diff is large: its 9 lines aren’t shown here.

tools/testing/selftests/bpf/Makefile+3−0

This diff is large: its 10 lines aren’t shown here.

tools/testing/selftests/bpf/progs/bprm_opts.c+1−1

This diff is large: its 9 lines aren’t shown here.

tools/testing/selftests/bpf/test_maps.c+42−6

This diff is large: its 65 lines aren’t shown here.

tools/testing/selftests/bpf/xdpxceiver.c+2−2

This diff is large: its 18 lines aren’t shown here.

tools/testing/selftests/drivers/net/mlxsw/qos_pfc.sh+1−1

This diff is large: its 9 lines aren’t shown here.

tools/testing/selftests/kvm/Makefile+1−1

This diff is large: its 9 lines aren’t shown here.

tools/testing/selftests/kvm/demand_paging_test.c+32−86

This diff is large: its 226 lines aren’t shown here.

tools/testing/selftests/kvm/dirty_log_perf_test.c+46−99

This diff is large: its 295 lines aren’t shown here.

tools/testing/selftests/kvm/dirty_log_test.c+37−88

This diff is large: its 219 lines aren’t shown here.

tools/testing/selftests/kvm/include/guest_modes.h+21−0

This diff is large: its 22 lines aren’t shown here.

tools/testing/selftests/kvm/include/kvm_util.h+9−0

This diff is large: its 23 lines aren’t shown here.

tools/testing/selftests/kvm/include/perf_test_util.h+12−155

This diff is large: its 193 lines aren’t shown here.

tools/testing/selftests/kvm/lib/guest_modes.c+70−0

This diff is large: its 71 lines aren’t shown here.

tools/testing/selftests/kvm/lib/kvm_util.c+1−8

This diff is large: its 16 lines aren’t shown here.

tools/testing/selftests/kvm/lib/perf_test_util.c+134−0

This diff is large: its 135 lines aren’t shown here.

tools/testing/selftests/net/fib_nexthops.sh+1−1

This diff is large: its 9 lines aren’t shown here.

tools/testing/selftests/net/pmtu.sh+69−2

This diff is large: its 92 lines aren’t shown here.

tools/testing/selftests/net/tls.c+2−2

This diff is large: its 11 lines aren’t shown here.

tools/testing/selftests/net/udpgro.sh+34−0

This diff is large: its 107 lines aren’t shown here.

tools/testing/selftests/netfilter/Makefile+2−1

This diff is large: its 10 lines aren’t shown here.

tools/testing/selftests/netfilter/ipip-conntrack-mtu.sh+206−0

This diff is large: its 207 lines aren’t shown here.

tools/testing/selftests/netfilter/nft_conntrack_helper.sh+9−3

This diff is large: its 35 lines aren’t shown here.

tools/testing/selftests/vDSO/.gitignore+3−0

This diff is large: its 9 lines aren’t shown here.

tools/testing/selftests/vDSO/vdso_test_correctness.c+1−1

This diff is large: its 9 lines aren’t shown here.

tools/testing/selftests/vm/Makefile+5−5

This diff is large: its 43 lines aren’t shown here.

tools/testing/selftests/wireguard/qemu/debug.config+0−1

This diff is large: its 6 lines aren’t shown here.

virt/kvm/kvm_main.c+1−2

This diff is large: its 11 lines aren’t shown here.

@@ -45,7 +45,7 @@ requirements: · 44 unmodified lines
45	#. `Other RCU Flavors`_	45	#. `Other RCU Flavors`_
46	#. `Possible Future Changes`_	46	#. `Possible Future Changes`_
47		47
48	This is followed by a `summary <#Summary>`__, however, the answers to	48	This is followed by a summary_, however, the answers to
49	each quick quiz immediately follows the quiz. Select the big white space	49	each quick quiz immediately follows the quiz. Select the big white space
50	with your mouse to see the answer.	50	with your mouse to see the answer.
51		51
@@ -1096,7 +1096,7 @@ memory barriers. · 1044 unmodified lines
1096	\| case, voluntary context switch) within an RCU read-side critical \|	1096	\| case, voluntary context switch) within an RCU read-side critical \|
1097	\| section. However, sleeping locks may be used within userspace RCU \|	1097	\| section. However, sleeping locks may be used within userspace RCU \|
1098	\| read-side critical sections, and also within Linux-kernel sleepable \|	1098	\| read-side critical sections, and also within Linux-kernel sleepable \|
1099	\| RCU `(SRCU) <#Sleepable%20RCU>`__ read-side critical sections. In \|	1099	\| RCU `(SRCU) <Sleepable RCU_>`__ read-side critical sections. In \|
1100	\| addition, the -rt patchset turns spinlocks into a sleeping locks so \|	1100	\| addition, the -rt patchset turns spinlocks into a sleeping locks so \|
1101	\| that the corresponding critical sections can be preempted, which also \|	1101	\| that the corresponding critical sections can be preempted, which also \|
1102	\| means that these sleeplockified spinlocks (but not other sleeping \|	1102	\| means that these sleeplockified spinlocks (but not other sleeping \|
@@ -1186,7 +1186,7 @@ non-preemptible (``CONFIG_PREEMPT=n``) kernels, and thus `tiny · 83 unmodified lines
1186	RCU <https://lkml.kernel.org/g/20090113221724.GA15307@linux.vnet.ibm.com>`__	1186	RCU <https://lkml.kernel.org/g/20090113221724.GA15307@linux.vnet.ibm.com>`__
1187	was born. Josh Triplett has since taken over the small-memory banner	1187	was born. Josh Triplett has since taken over the small-memory banner
1188	with his `Linux kernel tinification <https://tiny.wiki.kernel.org/>`__	1188	with his `Linux kernel tinification <https://tiny.wiki.kernel.org/>`__
1189	project, which resulted in `SRCU <#Sleepable%20RCU>`__ becoming optional	1189	project, which resulted in `SRCU <Sleepable RCU_>`__ becoming optional
1190	for those kernels not needing it.	1190	for those kernels not needing it.
1191		1191
1192	The remaining performance requirements are, for the most part,	1192	The remaining performance requirements are, for the most part,
@@ -1457,8 +1457,8 @@ will vary as the value of ``HZ`` varies, and can also be changed using · 264 unmodified lines
1457	the relevant Kconfig options and kernel boot parameters. RCU currently	1457	the relevant Kconfig options and kernel boot parameters. RCU currently
1458	does not do much sanity checking of these parameters, so please use	1458	does not do much sanity checking of these parameters, so please use
1459	caution when changing them. Note that these forward-progress measures	1459	caution when changing them. Note that these forward-progress measures
1460	are provided only for RCU, not for `SRCU <#Sleepable%20RCU>`__ or `Tasks	1460	are provided only for RCU, not for `SRCU <Sleepable RCU_>`__ or `Tasks
1461	RCU <#Tasks%20RCU>`__.	1461	RCU`_.
1462		1462
1463	RCU takes the following steps in ``call_rcu()`` to encourage timely	1463	RCU takes the following steps in ``call_rcu()`` to encourage timely
1464	invocation of callbacks when any given non-\ ``rcu_nocbs`` CPU has	1464	invocation of callbacks when any given non-\ ``rcu_nocbs`` CPU has
@@ -1477,8 +1477,8 @@ encouragement was provided: · 12 unmodified lines
1477		1477
1478	Again, these are default values when running at ``HZ=1000``, and can be	1478	Again, these are default values when running at ``HZ=1000``, and can be
1479	overridden. Again, these forward-progress measures are provided only for	1479	overridden. Again, these forward-progress measures are provided only for
1480	RCU, not for `SRCU <#Sleepable%20RCU>`__ or `Tasks	1480	RCU, not for `SRCU <Sleepable RCU_>`__ or `Tasks
1481	RCU <#Tasks%20RCU>`__. Even for RCU, callback-invocation forward	1481	RCU`_. Even for RCU, callback-invocation forward
1482	progress for ``rcu_nocbs`` CPUs is much less well-developed, in part	1482	progress for ``rcu_nocbs`` CPUs is much less well-developed, in part
1483	because workloads benefiting from ``rcu_nocbs`` CPUs tend to invoke	1483	because workloads benefiting from ``rcu_nocbs`` CPUs tend to invoke
1484	``call_rcu()`` relatively infrequently. If workloads emerge that need	1484	``call_rcu()`` relatively infrequently. If workloads emerge that need
@@ -1920,7 +1920,7 @@ Hotplug CPU · 435 unmodified lines
1920		1920
1921	The Linux kernel supports CPU hotplug, which means that CPUs can come	1921	The Linux kernel supports CPU hotplug, which means that CPUs can come
1922	and go. It is of course illegal to use any RCU API member from an	1922	and go. It is of course illegal to use any RCU API member from an
1923	offline CPU, with the exception of `SRCU <#Sleepable%20RCU>`__ read-side	1923	offline CPU, with the exception of `SRCU <Sleepable RCU_>`__ read-side
1924	critical sections. This requirement was present from day one in	1924	critical sections. This requirement was present from day one in
1925	DYNIX/ptx, but on the other hand, the Linux kernel's CPU-hotplug	1925	DYNIX/ptx, but on the other hand, the Linux kernel's CPU-hotplug
1926	implementation is “interesting.”	1926	implementation is “interesting.”
@@ -2177,7 +2177,7 @@ handles these states differently: · 250 unmodified lines
2177	However, RCU must be reliably informed as to whether any given CPU is	2177	However, RCU must be reliably informed as to whether any given CPU is
2178	currently in the idle loop, and, for ``NO_HZ_FULL``, also whether that	2178	currently in the idle loop, and, for ``NO_HZ_FULL``, also whether that
2179	CPU is executing in usermode, as discussed	2179	CPU is executing in usermode, as discussed
2180	`earlier <#Energy%20Efficiency>`__. It also requires that the	2180	`earlier <Energy Efficiency_>`__. It also requires that the
2181	scheduling-clock interrupt be enabled when RCU needs it to be:	2181	scheduling-clock interrupt be enabled when RCU needs it to be:
2182		2182
2183	#. If a CPU is either idle or executing in usermode, and RCU believes it	2183	#. If a CPU is either idle or executing in usermode, and RCU believes it
@@ -2294,7 +2294,7 @@ Performance, Scalability, Response Time, and Reliability · 110 unmodified lines
2294	~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~	2294	~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2295		2295
2296	Expanding on the `earlier	2296	Expanding on the `earlier
2297	discussion <#Performance%20and%20Scalability>`__, RCU is used heavily by	2297	discussion <Performance and Scalability_>`__, RCU is used heavily by
2298	hot code paths in performance-critical portions of the Linux kernel's	2298	hot code paths in performance-critical portions of the Linux kernel's
2299	networking, security, virtualization, and scheduling code paths. RCU	2299	networking, security, virtualization, and scheduling code paths. RCU
2300	must therefore use efficient implementations, especially in its	2300	must therefore use efficient implementations, especially in its

@@ -23,7 +23,7 @@ Here is what the fields mean: · 22 unmodified lines
23		23
24	- ``name``	24	- ``name``
25	is an identifier string. A new /proc file will be created with this	25	is an identifier string. A new /proc file will be created with this
26	``name below /proc/sys/fs/binfmt_misc``; cannot contain slashes ``/`` for	26	name below ``/proc/sys/fs/binfmt_misc``; cannot contain slashes ``/`` for
27	obvious reasons.	27	obvious reasons.
28	- ``type``	28	- ``type``
29	is the type of recognition. Give ``M`` for magic and ``E`` for extension.	29	is the type of recognition. Give ``M`` for magic and ``E`` for extension.
@@ -83,7 +83,7 @@ Here is what the fields mean: · 53 unmodified lines
83	``F`` - fix binary	83	``F`` - fix binary
84	The usual behaviour of binfmt_misc is to spawn the	84	The usual behaviour of binfmt_misc is to spawn the
85	binary lazily when the misc format file is invoked. However,	85	binary lazily when the misc format file is invoked. However,
86	this doesn``t work very well in the face of mount namespaces and	86	this doesn't work very well in the face of mount namespaces and
87	changeroots, so the ``F`` mode opens the binary as soon as the	87	changeroots, so the ``F`` mode opens the binary as soon as the
88	emulation is installed and uses the opened image to spawn the	88	emulation is installed and uses the opened image to spawn the
89	emulator, meaning it is always available once installed,	89	emulator, meaning it is always available once installed,

@@ -118,11 +118,11 @@ spinlock, but you may block holding a mutex. If you can't lock a mutex, · 117 unmodified lines
118	your task will suspend itself, and be woken up when the mutex is	118	your task will suspend itself, and be woken up when the mutex is
119	released. This means the CPU can do something else while you are	119	released. This means the CPU can do something else while you are
120	waiting. There are many cases when you simply can't sleep (see	120	waiting. There are many cases when you simply can't sleep (see
121	`What Functions Are Safe To Call From Interrupts? <#sleeping-things>`__),	121	`What Functions Are Safe To Call From Interrupts?`_),
122	and so have to use a spinlock instead.	122	and so have to use a spinlock instead.
123		123
124	Neither type of lock is recursive: see	124	Neither type of lock is recursive: see
125	`Deadlock: Simple and Advanced <#deadlock>`__.	125	`Deadlock: Simple and Advanced`_.
126		126
127	Locks and Uniprocessor Kernels	127	Locks and Uniprocessor Kernels
128	------------------------------	128	------------------------------
@@ -179,7 +179,7 @@ perfect world). · 50 unmodified lines
179		179
180	Note that you can also use spin_lock_irq() or	180	Note that you can also use spin_lock_irq() or
181	spin_lock_irqsave() here, which stop hardware interrupts	181	spin_lock_irqsave() here, which stop hardware interrupts
182	as well: see `Hard IRQ Context <#hard-irq-context>`__.	182	as well: see `Hard IRQ Context`_.
183		183
184	This works perfectly for UP as well: the spin lock vanishes, and this	184	This works perfectly for UP as well: the spin lock vanishes, and this
185	macro simply becomes local_bh_disable()	185	macro simply becomes local_bh_disable()
@@ -230,7 +230,7 @@ The Same Softirq · 44 unmodified lines
230	~~~~~~~~~~~~~~~~	230	~~~~~~~~~~~~~~~~
231		231
232	The same softirq can run on the other CPUs: you can use a per-CPU array	232	The same softirq can run on the other CPUs: you can use a per-CPU array
233	(see `Per-CPU Data <#per-cpu-data>`__) for better performance. If you're	233	(see `Per-CPU Data`_) for better performance. If you're
234	going so far as to use a softirq, you probably care about scalable	234	going so far as to use a softirq, you probably care about scalable
235	performance enough to justify the extra complexity.	235	performance enough to justify the extra complexity.
236		236

@@ -6,9 +6,9 @@ · 5 unmodified lines
6	netdev FAQ	6	netdev FAQ
7	==========	7	==========
8		8
9	Q: What is netdev?	9	What is netdev?
10	------------------	10	---------------
11	A: It is a mailing list for all network-related Linux stuff. This	11	It is a mailing list for all network-related Linux stuff. This
12	includes anything found under net/ (i.e. core code like IPv6) and	12	includes anything found under net/ (i.e. core code like IPv6) and
13	drivers/net (i.e. hardware specific drivers) in the Linux source tree.	13	drivers/net (i.e. hardware specific drivers) in the Linux source tree.
14		14
@@ -25,9 +25,9 @@ Aside from subsystems like that mentioned above, all network-related · 10 unmodified lines
25	Linux development (i.e. RFC, review, comments, etc.) takes place on	25	Linux development (i.e. RFC, review, comments, etc.) takes place on
26	netdev.	26	netdev.
27		27
28	Q: How do the changes posted to netdev make their way into Linux?	28	How do the changes posted to netdev make their way into Linux?
29	-----------------------------------------------------------------	29	--------------------------------------------------------------
30	A: There are always two trees (git repositories) in play. Both are	30	There are always two trees (git repositories) in play. Both are
31	driven by David Miller, the main network maintainer. There is the	31	driven by David Miller, the main network maintainer. There is the
32	``net`` tree, and the ``net-next`` tree. As you can probably guess from	32	``net`` tree, and the ``net-next`` tree. As you can probably guess from
33	the names, the ``net`` tree is for fixes to existing code already in the	33	the names, the ``net`` tree is for fixes to existing code already in the
@@ -37,9 +37,9 @@ for the future release. You can find the trees here: · 3 unmodified lines
37	- https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net.git	37	- https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net.git
38	- https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git	38	- https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git
39		39
40	Q: How often do changes from these trees make it to the mainline Linus tree?	40	How often do changes from these trees make it to the mainline Linus tree?
41	----------------------------------------------------------------------------	41	-------------------------------------------------------------------------
42	A: To understand this, you need to know a bit of background information on	42	To understand this, you need to know a bit of background information on
43	the cadence of Linux development. Each new release starts off with a	43	the cadence of Linux development. Each new release starts off with a
44	two week "merge window" where the main maintainers feed their new stuff	44	two week "merge window" where the main maintainers feed their new stuff
45	to Linus for merging into the mainline tree. After the two weeks, the	45	to Linus for merging into the mainline tree. After the two weeks, the
@@ -81,7 +81,8 @@ focus for ``net`` is on stabilization and bug fixes. · 35 unmodified lines
81		81
82	Finally, the vX.Y gets released, and the whole cycle starts over.	82	Finally, the vX.Y gets released, and the whole cycle starts over.
83		83
84	Q: So where are we now in this cycle?	84	So where are we now in this cycle?
		85	----------------------------------
85		86
86	Load the mainline (Linus) page here:	87	Load the mainline (Linus) page here:
87		88
@@ -91,9 +92,9 @@ and note the top of the "tags" section. If it is rc1, it is early in · 3 unmodified lines
91	the dev cycle. If it was tagged rc7 a week ago, then a release is	92	the dev cycle. If it was tagged rc7 a week ago, then a release is
92	probably imminent.	93	probably imminent.
93		94
94	Q: How do I indicate which tree (net vs. net-next) my patch should be in?	95	How do I indicate which tree (net vs. net-next) my patch should be in?
95	-------------------------------------------------------------------------	96	----------------------------------------------------------------------
96	A: Firstly, think whether you have a bug fix or new "next-like" content.	97	Firstly, think whether you have a bug fix or new "next-like" content.
97	Then once decided, assuming that you use git, use the prefix flag, i.e.	98	Then once decided, assuming that you use git, use the prefix flag, i.e.
98	::	99	::
99		100
@@ -105,48 +106,45 @@ in the above is just the subject text of the outgoing e-mail, and you · 5 unmodified lines
105	can manually change it yourself with whatever MUA you are comfortable	106	can manually change it yourself with whatever MUA you are comfortable
106	with.	107	with.
107		108
108	Q: I sent a patch and I'm wondering what happened to it?	109	I sent a patch and I'm wondering what happened to it - how can I tell whether it got merged?
109	--------------------------------------------------------	110	--------------------------------------------------------------------------------------------
110	Q: How can I tell whether it got merged?	111	Start by looking at the main patchworks queue for netdev:
111	A: Start by looking at the main patchworks queue for netdev:
112		112
113	https://patchwork.kernel.org/project/netdevbpf/list/	113	https://patchwork.kernel.org/project/netdevbpf/list/
114		114
115	The "State" field will tell you exactly where things are at with your	115	The "State" field will tell you exactly where things are at with your
116	patch.	116	patch.
117		117
118	Q: The above only says "Under Review". How can I find out more?	118	The above only says "Under Review". How can I find out more?
119	----------------------------------------------------------------	119	-------------------------------------------------------------
120	A: Generally speaking, the patches get triaged quickly (in less than	120	Generally speaking, the patches get triaged quickly (in less than
121	48h). So be patient. Asking the maintainer for status updates on your	121	48h). So be patient. Asking the maintainer for status updates on your
122	patch is a good way to ensure your patch is ignored or pushed to the	122	patch is a good way to ensure your patch is ignored or pushed to the
123	bottom of the priority list.	123	bottom of the priority list.
124		124
125	Q: I submitted multiple versions of the patch series	125	I submitted multiple versions of the patch series. Should I directly update patchwork for the previous versions of these patch series?
126	----------------------------------------------------	126	--------------------------------------------------------------------------------------------------------------------------------------
127	Q: should I directly update patchwork for the previous versions of these	127	No, please don't interfere with the patch status on patchwork, leave
128	patch series?
129	A: No, please don't interfere with the patch status on patchwork, leave
130	it to the maintainer to figure out what is the most recent and current	128	it to the maintainer to figure out what is the most recent and current
131	version that should be applied. If there is any doubt, the maintainer	129	version that should be applied. If there is any doubt, the maintainer
132	will reply and ask what should be done.	130	will reply and ask what should be done.
133		131
134	Q: I made changes to only a few patches in a patch series should I resend only those changed?	132	I made changes to only a few patches in a patch series should I resend only those changed?
135	---------------------------------------------------------------------------------------------	133	------------------------------------------------------------------------------------------
136	A: No, please resend the entire patch series and make sure you do number your	134	No, please resend the entire patch series and make sure you do number your
137	patches such that it is clear this is the latest and greatest set of patches	135	patches such that it is clear this is the latest and greatest set of patches
138	that can be applied.	136	that can be applied.
139		137
140	Q: I submitted multiple versions of a patch series and it looks like a version other than the last one has been accepted, what should I do?	138	I submitted multiple versions of a patch series and it looks like a version other than the last one has been accepted, what should I do?
141	-------------------------------------------------------------------------------------------------------------------------------------------	139	----------------------------------------------------------------------------------------------------------------------------------------
142	A: There is no revert possible, once it is pushed out, it stays like that.	140	There is no revert possible, once it is pushed out, it stays like that.
143	Please send incremental versions on top of what has been merged in order to fix	141	Please send incremental versions on top of what has been merged in order to fix
144	the patches the way they would look like if your latest patch series was to be	142	the patches the way they would look like if your latest patch series was to be
145	merged.	143	merged.
146		144
147	Q: How can I tell what patches are queued up for backporting to the various stable releases?	145	How can I tell what patches are queued up for backporting to the various stable releases?
148	--------------------------------------------------------------------------------------------	146	-----------------------------------------------------------------------------------------
149	A: Normally Greg Kroah-Hartman collects stable commits himself, but for	147	Normally Greg Kroah-Hartman collects stable commits himself, but for
150	networking, Dave collects up patches he deems critical for the	148	networking, Dave collects up patches he deems critical for the
151	networking subsystem, and then hands them off to Greg.	149	networking subsystem, and then hands them off to Greg.
152		150
@@ -169,11 +167,9 @@ simply clone the repo, and then git grep the mainline commit ID, e.g. · 16 unmodified lines
169	releases/3.9.8/ipv6-fix-possible-crashes-in-ip6_cork_release.patch	167	releases/3.9.8/ipv6-fix-possible-crashes-in-ip6_cork_release.patch
170	stable/stable-queue$	168	stable/stable-queue$
171		169
172	Q: I see a network patch and I think it should be backported to stable.	170	I see a network patch and I think it should be backported to stable. Should I request it via stable@vger.kernel.org like the references in the kernel's Documentation/process/stable-kernel-rules.rst file say?
173	-----------------------------------------------------------------------	171	---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
174	Q: Should I request it via stable@vger.kernel.org like the references in	172	No, not for networking. Check the stable queues as per above first
175	the kernel's Documentation/process/stable-kernel-rules.rst file say?
176	A: No, not for networking. Check the stable queues as per above first
177	to see if it is already queued. If not, then send a mail to netdev,	173	to see if it is already queued. If not, then send a mail to netdev,
178	listing the upstream commit ID and why you think it should be a stable	174	listing the upstream commit ID and why you think it should be a stable
179	candidate.	175	candidate.
@@ -190,11 +186,9 @@ mainline, the better the odds that it is an OK candidate for stable. So · 10 unmodified lines
190	scrambling to request a commit be added the day after it appears should	186	scrambling to request a commit be added the day after it appears should
191	be avoided.	187	be avoided.
192		188
193	Q: I have created a network patch and I think it should be backported to stable.	189	I have created a network patch and I think it should be backported to stable. Should I add a Cc: stable@vger.kernel.org like the references in the kernel's Documentation/ directory say?
194	--------------------------------------------------------------------------------	190	-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
195	Q: Should I add a Cc: stable@vger.kernel.org like the references in the	191	No. See above answer. In short, if you think it really belongs in
196	kernel's Documentation/ directory say?
197	A: No. See above answer. In short, if you think it really belongs in
198	stable, then ensure you write a decent commit log that describes who	192	stable, then ensure you write a decent commit log that describes who
199	gets impacted by the bug fix and how it manifests itself, and when the	193	gets impacted by the bug fix and how it manifests itself, and when the
200	bug was introduced. If you do that properly, then the commit will get	194	bug was introduced. If you do that properly, then the commit will get
@@ -207,18 +201,18 @@ marker line as described in · 6 unmodified lines
207	:ref:`Documentation/process/submitting-patches.rst <the_canonical_patch_format>`	201	:ref:`Documentation/process/submitting-patches.rst <the_canonical_patch_format>`
208	to temporarily embed that information into the patch that you send.	202	to temporarily embed that information into the patch that you send.
209		203
210	Q: Are all networking bug fixes backported to all stable releases?	204	Are all networking bug fixes backported to all stable releases?
211	------------------------------------------------------------------	205	---------------------------------------------------------------
212	A: Due to capacity, Dave could only take care of the backports for the	206	Due to capacity, Dave could only take care of the backports for the
213	last two stable releases. For earlier stable releases, each stable	207	last two stable releases. For earlier stable releases, each stable
214	branch maintainer is supposed to take care of them. If you find any	208	branch maintainer is supposed to take care of them. If you find any
215	patch is missing from an earlier stable branch, please notify	209	patch is missing from an earlier stable branch, please notify
216	stable@vger.kernel.org with either a commit ID or a formal patch	210	stable@vger.kernel.org with either a commit ID or a formal patch
217	backported, and CC Dave and other relevant networking developers.	211	backported, and CC Dave and other relevant networking developers.
218		212
219	Q: Is the comment style convention different for the networking content?	213	Is the comment style convention different for the networking content?
220	------------------------------------------------------------------------	214	---------------------------------------------------------------------
221	A: Yes, in a largely trivial way. Instead of this::	215	Yes, in a largely trivial way. Instead of this::
222		216
223	/*	217	/*
224	* foobar blah blah blah	218	* foobar blah blah blah
@@ -231,32 +225,30 @@ it is requested that you make it look like this:: · 6 unmodified lines
231	* another line of text	225	* another line of text
232	*/	226	*/
233		227
234	Q: I am working in existing code that has the former comment style and not the latter.	228	I am working in existing code that has the former comment style and not the latter. Should I submit new code in the former style or the latter?
235	--------------------------------------------------------------------------------------	229	-----------------------------------------------------------------------------------------------------------------------------------------------
236	Q: Should I submit new code in the former style or the latter?	230	Make it the latter style, so that eventually all code in the domain
237	A: Make it the latter style, so that eventually all code in the domain
238	of netdev is of this format.	231	of netdev is of this format.
239		232
240	Q: I found a bug that might have possible security implications or similar.	233	I found a bug that might have possible security implications or similar. Should I mail the main netdev maintainer off-list?
241	---------------------------------------------------------------------------	234	---------------------------------------------------------------------------------------------------------------------------
242	Q: Should I mail the main netdev maintainer off-list?**	235	No. The current netdev maintainer has consistently requested that
243	A: No. The current netdev maintainer has consistently requested that
244	people use the mailing lists and not reach out directly. If you aren't	236	people use the mailing lists and not reach out directly. If you aren't
245	OK with that, then perhaps consider mailing security@kernel.org or	237	OK with that, then perhaps consider mailing security@kernel.org or
246	reading about http://oss-security.openwall.org/wiki/mailing-lists/distros	238	reading about http://oss-security.openwall.org/wiki/mailing-lists/distros
247	as possible alternative mechanisms.	239	as possible alternative mechanisms.
248		240
249	Q: What level of testing is expected before I submit my change?	241	What level of testing is expected before I submit my change?
250	---------------------------------------------------------------	242	------------------------------------------------------------
251	A: If your changes are against ``net-next``, the expectation is that you	243	If your changes are against ``net-next``, the expectation is that you
252	have tested by layering your changes on top of ``net-next``. Ideally	244	have tested by layering your changes on top of ``net-next``. Ideally
253	you will have done run-time testing specific to your change, but at a	245	you will have done run-time testing specific to your change, but at a
254	minimum, your changes should survive an ``allyesconfig`` and an	246	minimum, your changes should survive an ``allyesconfig`` and an
255	``allmodconfig`` build without new warnings or failures.	247	``allmodconfig`` build without new warnings or failures.
256		248
257	Q: How do I post corresponding changes to user space components?	249	How do I post corresponding changes to user space components?
258	----------------------------------------------------------------	250	-------------------------------------------------------------
259	A: User space code exercising kernel features should be posted	251	User space code exercising kernel features should be posted
260	alongside kernel patches. This gives reviewers a chance to see	252	alongside kernel patches. This gives reviewers a chance to see
261	how any new interface is used and how well it works.	253	how any new interface is used and how well it works.
262		254
@@ -280,9 +272,9 @@ to the mailing list, e.g.:: · 17 unmodified lines
280	Posting as one thread is discouraged because it confuses patchwork	272	Posting as one thread is discouraged because it confuses patchwork
281	(as of patchwork 2.2.2).	273	(as of patchwork 2.2.2).
282		274
283	Q: Any other tips to help ensure my net/net-next patch gets OK'd?	275	Any other tips to help ensure my net/net-next patch gets OK'd?
284	-----------------------------------------------------------------	276	--------------------------------------------------------------
285	A: Attention to detail. Re-read your own work as if you were the	277	Attention to detail. Re-read your own work as if you were the
286	reviewer. You can start with using ``checkpatch.pl``, perhaps even with	278	reviewer. You can start with using ``checkpatch.pl``, perhaps even with
287	the ``--strict`` flag. But do not be mindlessly robotic in doing so.	279	the ``--strict`` flag. But do not be mindlessly robotic in doing so.
288	If your change is a bug fix, make sure your commit log indicates the	280	If your change is a bug fix, make sure your commit log indicates the