History

Merge tag 'drm-intel-next-2013-02-01' of git://people.freedesktop.org/~danvet/drm-intel into drm-next

Daniel writes: "Probably the last feature pull for 3.9, there's some fixes outstanding thought that I'd like to sneak in. And maybe 3.8 takes a bit longer ... Anyway, highlights of this pull: - Kill the horrible IS_DISPLAYREG hack to handle the mmio offset movements on vlv, big thanks to Ville. - Dynamic power well support for Haswell, shaves away a bit when only using the eDP port on pipe A (Paulo). Plus unclaimed register fixes uncovered by this. - Clarifications of the gpu hang/reset state transitions, hopefully fixing a few spurious -EIO deaths in userspace. - Haswell ELD fixes. - Some more (pp)gtt cleanups from Ben. - A few smaller things all over. Plus all the stuff from the previous rather small pull request: - Broadcast RBG improvements and reduced color range fixes from Ville. - Ben is on a "kill legacy gtt code for good" spree, first pile of patches included. - No-relocs and bo lut improvements for faster execbuf from Chris. - Some refactorings from Imre." * tag 'drm-intel-next-2013-02-01' of git://people.freedesktop.org/~danvet/drm-intel: (101 commits) GPU/i915: Fix acpi_bus_get_device() check in drivers/gpu/drm/i915/intel_opregion.c drm/i915: Set the SR01 "screen off" bit in i915_redisable_vga() too drm/i915: Kill IS_DISPLAYREG() drm/i915: Introduce i915_vgacntrl_reg() drm/i915: gen6_gmch_remove can be static drm/i915: dynamic Haswell display power well support drm/i915: check the power down well on assert_pipe() drm/i915: don't send DP "idle" pattern before "normal" on HSW PORT_A drm/i915: don't run hsw power well code on !hsw drm/i915: kill cargo-culted locking from power well code drm/i915: Only run idle processing from i915_gem_retire_requests_worker drm/i915: Fix CAGF for HSW drm/i915: Reclaim GTT space for failed PPGTT drm/i915: remove intel_gtt structure drm/i915: Add probe and remove to the gtt ops drm/i915: extract hw ppgtt setup/cleanup code drm/i915: pte_encode is gen6+ drm/i915: vfuncs for ppgtt drm/i915: vfuncs for gtt_clear_range/insert_entries drm/i915: Error state should print /sys/kernel/debug ...

Dave Airlie committed 13 years ago

Commit cd17ef42 parents 67c9640 7d37bea34 files · +2255 −1732Browse files

Unified · Split

34 files
  1. drivers/char/agp/intel-gtt.c +35 −52
  2. drivers/gpu/drm/drm_edid.c +33 −0
  3. drivers/gpu/drm/i915/Makefile +1 −0
  4. drivers/gpu/drm/i915/i915_debugfs.c +120 −11
  5. drivers/gpu/drm/i915/i915_dma.c +24 −19
  6. drivers/gpu/drm/i915/i915_drv.c +9 −107
  7. drivers/gpu/drm/i915/i915_drv.h +239 −142
  8. drivers/gpu/drm/i915/i915_gem.c +140 −145
  9. drivers/gpu/drm/i915/i915_gem_evict.c +1 −1
  10. drivers/gpu/drm/i915/i915_gem_execbuffer.c +163 −117
  11. drivers/gpu/drm/i915/i915_gem_gtt.c +324 −266
  12. drivers/gpu/drm/i915/i915_gem_stolen.c +4 −4
  13. drivers/gpu/drm/i915/i915_gem_tiling.c +5 −16
  14. drivers/gpu/drm/i915/i915_irq.c +88 −42
  15. drivers/gpu/drm/i915/i915_reg.h +150 −136
  16. drivers/gpu/drm/i915/i915_suspend.c +29 −511
  17. drivers/gpu/drm/i915/i915_ums.c +503 −0
  18. drivers/gpu/drm/i915/intel_crt.c +15 −14
  19. drivers/gpu/drm/i915/intel_ddi.c +28 −1
  20. drivers/gpu/drm/i915/intel_display.c +91 −53
  21. drivers/gpu/drm/i915/intel_dp.c +49 −15
  22. drivers/gpu/drm/i915/intel_drv.h +15 −3
  23. drivers/gpu/drm/i915/intel_fb.c +4 −4
  24. drivers/gpu/drm/i915/intel_hdmi.c +56 −16
  25. drivers/gpu/drm/i915/intel_i2c.c +2 −0
  26. drivers/gpu/drm/i915/intel_modes.c +3 −2
  27. drivers/gpu/drm/i915/intel_opregion.c +1 −1
  28. drivers/gpu/drm/i915/intel_overlay.c +2 −2
  29. drivers/gpu/drm/i915/intel_pm.c +44 −18
  30. drivers/gpu/drm/i915/intel_ringbuffer.c +6 −6
  31. drivers/gpu/drm/i915/intel_sdvo.c +49 −10
  32. include/drm/drm_crtc.h +1 −0
  33. include/drm/intel-gtt.h +1 −18
  34. include/uapi/drm/i915_drm.h +20 −0
drivers/char/agp/intel-gtt.c+35−52
@@ -60,7 +60,6 @@ struct intel_gtt_driver { · 59 unmodified lines
6060 };
6161
6262 static struct _intel_private {
63− struct intel_gtt base;
6463 const struct intel_gtt_driver *driver;
6564 struct pci_dev *pcidev; /* device one */
6665 struct pci_dev *bridge_dev;
@@ -75,7 +74,18 @@ static struct _intel_private { · 8 unmodified lines
7574 struct resource ifp_resource;
7675 int resource_valid;
7776 struct page *scratch_page;
77+ phys_addr_t scratch_page_dma;
7878 int refcount;
79+ /* Whether i915 needs to use the dmar apis or not. */
80+ unsigned int needs_dmar : 1;
81+ phys_addr_t gma_bus_addr;
82+ /* Size of memory reserved for graphics by the BIOS */
83+ unsigned int stolen_size;
84+ /* Total number of gtt entries. */
85+ unsigned int gtt_total_entries;
86+ /* Part of the gtt that is mappable by the cpu, for those chips where
87+ * this is not the full gtt. */
88+ unsigned int gtt_mappable_entries;
7989 } intel_private;
8090
8191 #define INTEL_GTT_GEN intel_private.driver->gen
@@ -291,15 +301,15 @@ static int intel_gtt_setup_scratch_page(void) · 209 unmodified lines
291301 get_page(page);
292302 set_pages_uc(page, 1);
293303
294− if (intel_private.base.needs_dmar) {
304+ if (intel_private.needs_dmar) {
295305 dma_addr = pci_map_page(intel_private.pcidev, page, 0,
296306 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
297307 if (pci_dma_mapping_error(intel_private.pcidev, dma_addr))
298308 return -EINVAL;
299309
300− intel_private.base.scratch_page_dma = dma_addr;
310+ intel_private.scratch_page_dma = dma_addr;
301311 } else
302− intel_private.base.scratch_page_dma = page_to_phys(page);
312+ intel_private.scratch_page_dma = page_to_phys(page);
303313
304314 intel_private.scratch_page = page;
305315
@@ -506,7 +516,7 @@ static unsigned int intel_gtt_total_entries(void) · 200 unmodified lines
506516 /* On previous hardware, the GTT size was just what was
507517 * required to map the aperture.
508518 */
509− return intel_private.base.gtt_mappable_entries;
519+ return intel_private.gtt_mappable_entries;
510520 }
511521 }
512522
@@ -546,7 +556,7 @@ static unsigned int intel_gtt_mappable_entries(void) · 33 unmodified lines
546556 static void intel_gtt_teardown_scratch_page(void)
547557 {
548558 set_pages_wb(intel_private.scratch_page, 1);
549− pci_unmap_page(intel_private.pcidev, intel_private.base.scratch_page_dma,
559+ pci_unmap_page(intel_private.pcidev, intel_private.scratch_page_dma,
550560 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
551561 put_page(intel_private.scratch_page);
552562 __free_page(intel_private.scratch_page);
@@ -572,8 +582,8 @@ static int intel_gtt_init(void) · 19 unmodified lines
572582 if (ret != 0)
573583 return ret;
574584
575− intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries();
576− intel_private.base.gtt_total_entries = intel_gtt_total_entries();
585+ intel_private.gtt_mappable_entries = intel_gtt_mappable_entries();
586+ intel_private.gtt_total_entries = intel_gtt_total_entries();
577587
578588 /* save the PGETBL reg for resume */
579589 intel_private.PGETBL_save =
@@ -585,10 +595,10 @@ static int intel_gtt_init(void) · 5 unmodified lines
585595
586596 dev_info(&intel_private.bridge_dev->dev,
587597 "detected gtt size: %dK total, %dK mappable\n",
588− intel_private.base.gtt_total_entries * 4,
589− intel_private.base.gtt_mappable_entries * 4);
598+ intel_private.gtt_total_entries * 4,
599+ intel_private.gtt_mappable_entries * 4);
590600
591− gtt_map_size = intel_private.base.gtt_total_entries * 4;
601+ gtt_map_size = intel_private.gtt_total_entries * 4;
592602
593603 intel_private.gtt = NULL;
594604 if (INTEL_GTT_GEN < 6 && INTEL_GTT_GEN > 2)
@@ -605,9 +615,9 @@ static int intel_gtt_init(void) · 10 unmodified lines
605615
606616 global_cache_flush(); /* FIXME: ? */
607617
608− intel_private.base.stolen_size = intel_gtt_stolen_size();
618+ intel_private.stolen_size = intel_gtt_stolen_size();
609619
610− intel_private.base.needs_dmar = USE_PCI_DMA_API && INTEL_GTT_GEN > 2;
620+ intel_private.needs_dmar = USE_PCI_DMA_API && INTEL_GTT_GEN > 2;
611621
612622 ret = intel_gtt_setup_scratch_page();
613623 if (ret != 0) {
@@ -622,7 +632,7 @@ static int intel_gtt_init(void) · 8 unmodified lines
622632 pci_read_config_dword(intel_private.pcidev, I915_GMADDR,
623633 &gma_addr);
624634
625− intel_private.base.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK);
635+ intel_private.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK);
626636
627637 return 0;
628638 }
@@ -633,8 +643,7 @@ static int intel_fake_agp_fetch_size(void) · 4 unmodified lines
633643 unsigned int aper_size;
634644 int i;
635645
636− aper_size = (intel_private.base.gtt_mappable_entries << PAGE_SHIFT)
637− / MB(1);
646+ aper_size = (intel_private.gtt_mappable_entries << PAGE_SHIFT) / MB(1);
638647
639648 for (i = 0; i < num_sizes; i++) {
640649 if (aper_size == intel_fake_agp_sizes[i].size) {
@@ -778,7 +787,7 @@ static int intel_fake_agp_configure(void) · 137 unmodified lines
778787 return -EIO;
779788
780789 intel_private.clear_fake_agp = true;
781− agp_bridge->gart_bus_addr = intel_private.base.gma_bus_addr;
790+ agp_bridge->gart_bus_addr = intel_private.gma_bus_addr;
782791
783792 return 0;
784793 }
@@ -840,12 +849,9 @@ static int intel_fake_agp_insert_entries(struct agp_memory *mem, · 55 unmodified lines
840849 {
841850 int ret = -EINVAL;
842851
843− if (intel_private.base.do_idle_maps)
844− return -ENODEV;
845−
846852 if (intel_private.clear_fake_agp) {
847− int start = intel_private.base.stolen_size / PAGE_SIZE;
848− int end = intel_private.base.gtt_mappable_entries;
853+ int start = intel_private.stolen_size / PAGE_SIZE;
854+ int end = intel_private.gtt_mappable_entries;
849855 intel_gtt_clear_range(start, end - start);
850856 intel_private.clear_fake_agp = false;
851857 }
@@ -856,7 +862,7 @@ static int intel_fake_agp_insert_entries(struct agp_memory *mem, · 4 unmodified lines
856862 if (mem->page_count == 0)
857863 goto out;
858864
859− if (pg_start + mem->page_count > intel_private.base.gtt_total_entries)
865+ if (pg_start + mem->page_count > intel_private.gtt_total_entries)
860866 goto out_err;
861867
862868 if (type != mem->type)
@@ -868,7 +874,7 @@ static int intel_fake_agp_insert_entries(struct agp_memory *mem, · 5 unmodified lines
868874 if (!mem->is_flushed)
869875 global_cache_flush();
870876
871− if (intel_private.base.needs_dmar) {
877+ if (intel_private.needs_dmar) {
872878 struct sg_table st;
873879
874880 ret = intel_gtt_map_memory(mem->pages, mem->page_count, &st);
@@ -894,7 +900,7 @@ void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries) · 19 unmodified lines
894900 unsigned int i;
895901
896902 for (i = first_entry; i < (first_entry + num_entries); i++) {
897− intel_private.driver->write_entry(intel_private.base.scratch_page_dma,
903+ intel_private.driver->write_entry(intel_private.scratch_page_dma,
898904 i, 0);
899905 }
900906 readl(intel_private.gtt+i-1);
@@ -907,12 +913,9 @@ static int intel_fake_agp_remove_entries(struct agp_memory *mem, · 6 unmodified lines
907913 if (mem->page_count == 0)
908914 return 0;
909915
910− if (intel_private.base.do_idle_maps)
911− return -ENODEV;
912−
913916 intel_gtt_clear_range(pg_start, mem->page_count);
914917
915− if (intel_private.base.needs_dmar) {
918+ if (intel_private.needs_dmar) {
916919 intel_gtt_unmap_memory(mem->sg_list, mem->num_sg);
917920 mem->sg_list = NULL;
918921 mem->num_sg = 0;
@@ -1069,24 +1072,6 @@ static void i965_write_entry(dma_addr_t addr, · 150 unmodified lines
10691072 writel(addr | pte_flags, intel_private.gtt + entry);
10701073 }
10711074
1072−/* Certain Gen5 chipsets require require idling the GPU before
1073− * unmapping anything from the GTT when VT-d is enabled.
1074− */
1075−static inline int needs_idle_maps(void)
1076−{
1077−#ifdef CONFIG_INTEL_IOMMU
1078− const unsigned short gpu_devid = intel_private.pcidev->device;
1079−
1080− /* Query intel_iommu to see if we need the workaround. Presumably that
1081− * was loaded first.
1082− */
1083− if ((gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB ||
1084− gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG) &&
1085− intel_iommu_gfx_mapped)
1086− return 1;
1087−#endif
1088− return 0;
1089−}
10901075
10911076 static int i9xx_setup(void)
10921077 {
@@ -1115,9 +1100,6 @@ static int i9xx_setup(void) · 22 unmodified lines
11151100 break;
11161101 }
11171102
1118− if (needs_idle_maps())
1119− intel_private.base.do_idle_maps = 1;
1120−
11211103 intel_i9xx_setup_flush();
11221104
11231105 return 0;
@@ -1389,9 +1371,10 @@ int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev, · 265 unmodified lines
13891371 }
13901372 EXPORT_SYMBOL(intel_gmch_probe);
13911373
1392−struct intel_gtt *intel_gtt_get(void)
1374+void intel_gtt_get(size_t *gtt_total, size_t *stolen_size)
13931375 {
1394− return &intel_private.base;
1376+ *gtt_total = intel_private.gtt_total_entries << PAGE_SHIFT;
1377+ *stolen_size = intel_private.stolen_size;
13951378 }
13961379 EXPORT_SYMBOL(intel_gtt_get);
13971380
drivers/gpu/drm/drm_edid.c+33−0
@@ -1483,9 +1483,11 @@ add_detailed_modes(struct drm_connector *connector, struct edid *edid, · 1482 unmodified lines
14831483 #define VIDEO_BLOCK 0x02
14841484 #define VENDOR_BLOCK 0x03
14851485 #define SPEAKER_BLOCK 0x04
1486+#define VIDEO_CAPABILITY_BLOCK 0x07
14861487 #define EDID_BASIC_AUDIO (1 << 6)
14871488 #define EDID_CEA_YCRCB444 (1 << 5)
14881489 #define EDID_CEA_YCRCB422 (1 << 4)
1490+#define EDID_CEA_VCDB_QS (1 << 6)
14891491
14901492 /**
14911493 * Search EDID for CEA extension block.
@@ -1901,6 +1903,37 @@ end: · 409 unmodified lines
19011903 }
19021904 EXPORT_SYMBOL(drm_detect_monitor_audio);
19031905
1906+/**
1907+ * drm_rgb_quant_range_selectable - is RGB quantization range selectable?
1908+ *
1909+ * Check whether the monitor reports the RGB quantization range selection
1910+ * as supported. The AVI infoframe can then be used to inform the monitor
1911+ * which quantization range (full or limited) is used.
1912+ */
1913+bool drm_rgb_quant_range_selectable(struct edid *edid)
1914+{
1915+ u8 *edid_ext;
1916+ int i, start, end;
1917+
1918+ edid_ext = drm_find_cea_extension(edid);
1919+ if (!edid_ext)
1920+ return false;
1921+
1922+ if (cea_db_offsets(edid_ext, &start, &end))
1923+ return false;
1924+
1925+ for_each_cea_db(edid_ext, i, start, end) {
1926+ if (cea_db_tag(&edid_ext[i]) == VIDEO_CAPABILITY_BLOCK &&
1927+ cea_db_payload_len(&edid_ext[i]) == 2) {
1928+ DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]);
1929+ return edid_ext[i + 2] & EDID_CEA_VCDB_QS;
1930+ }
1931+ }
1932+
1933+ return false;
1934+}
1935+EXPORT_SYMBOL(drm_rgb_quant_range_selectable);
1936+
19041937 /**
19051938 * drm_add_display_info - pull display info out if present
19061939 * @edid: EDID data
drivers/gpu/drm/i915/Makefile+1−0
@@ -16,6 +16,7 @@ i915-y := i915_drv.o i915_dma.o i915_irq.o \ · 15 unmodified lines
1616 i915_gem_tiling.o \
1717 i915_sysfs.o \
1818 i915_trace_points.o \
19+ i915_ums.o \
1920 intel_display.o \
2021 intel_crt.o \
2122 intel_lvds.o \
drivers/gpu/drm/i915/i915_debugfs.c+120−11
@@ -258,8 +258,9 @@ static int i915_gem_object_info(struct seq_file *m, void* data) · 257 unmodified lines
258258 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
259259 count, size);
260260
261− seq_printf(m, "%zu [%zu] gtt total\n",
262− dev_priv->mm.gtt_total, dev_priv->mm.mappable_gtt_total);
261+ seq_printf(m, "%zu [%lu] gtt total\n",
262+ dev_priv->gtt.total,
263+ dev_priv->gtt.mappable_end - dev_priv->gtt.start);
263264
264265 mutex_unlock(&dev->struct_mutex);
265266
@@ -813,11 +814,11 @@ static int i915_error_state_open(struct inode *inode, struct file *file) · 547 unmodified lines
813814
814815 error_priv->dev = dev;
815816
816− spin_lock_irqsave(&dev_priv->error_lock, flags);
817− error_priv->error = dev_priv->first_error;
817+ spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
818+ error_priv->error = dev_priv->gpu_error.first_error;
818819 if (error_priv->error)
819820 kref_get(&error_priv->error->ref);
820− spin_unlock_irqrestore(&dev_priv->error_lock, flags);
821+ spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
821822
822823 return single_open(file, i915_error_state, error_priv);
823824 }
@@ -956,7 +957,7 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused) · 132 unmodified lines
956957 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
957958 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
958959 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
959− u32 rpstat;
960+ u32 rpstat, cagf;
960961 u32 rpupei, rpcurup, rpprevup;
961962 u32 rpdownei, rpcurdown, rpprevdown;
962963 int max_freq;
@@ -975,6 +976,11 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused) · 12 unmodified lines
975976 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
976977 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
977978 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
979+ if (IS_HASWELL(dev))
980+ cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
981+ else
982+ cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
983+ cagf *= GT_FREQUENCY_MULTIPLIER;
978984
979985 gen6_gt_force_wake_put(dev_priv);
980986 mutex_unlock(&dev->struct_mutex);
@@ -987,8 +993,7 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused) · 6 unmodified lines
987993 gt_perf_status & 0xff);
988994 seq_printf(m, "Render p-state limit: %d\n",
989995 rp_state_limits & 0xff);
990− seq_printf(m, "CAGF: %dMHz\n", ((rpstat & GEN6_CAGF_MASK) >>
991− GEN6_CAGF_SHIFT) * GT_FREQUENCY_MULTIPLIER);
996+ seq_printf(m, "CAGF: %dMHz\n", cagf);
992997 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
993998 GEN6_CURICONT_MASK);
994999 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
@@ -1674,7 +1679,7 @@ i915_wedged_read(struct file *filp, · 679 unmodified lines
16741679
16751680 len = snprintf(buf, sizeof(buf),
16761681 "wedged : %d\n",
1677− atomic_read(&dev_priv->mm.wedged));
1682+ atomic_read(&dev_priv->gpu_error.reset_counter));
16781683
16791684 if (len > sizeof(buf))
16801685 len = sizeof(buf);
@@ -1729,7 +1734,7 @@ i915_ring_stop_read(struct file *filp, · 48 unmodified lines
17291734 int len;
17301735
17311736 len = snprintf(buf, sizeof(buf),
1732− "0x%08x\n", dev_priv->stop_rings);
1737+ "0x%08x\n", dev_priv->gpu_error.stop_rings);
17331738
17341739 if (len > sizeof(buf))
17351740 len = sizeof(buf);
@@ -1765,7 +1770,7 @@ i915_ring_stop_write(struct file *filp, · 29 unmodified lines
17651770 if (ret)
17661771 return ret;
17671772
1768− dev_priv->stop_rings = val;
1773+ dev_priv->gpu_error.stop_rings = val;
17691774 mutex_unlock(&dev->struct_mutex);
17701775
17711776 return cnt;
@@ -1779,6 +1784,102 @@ static const struct file_operations i915_ring_stop_fops = { · 7 unmodified lines
17791784 .llseek = default_llseek,
17801785 };
17811786
1787+#define DROP_UNBOUND 0x1
1788+#define DROP_BOUND 0x2
1789+#define DROP_RETIRE 0x4
1790+#define DROP_ACTIVE 0x8
1791+#define DROP_ALL (DROP_UNBOUND | \
1792+ DROP_BOUND | \
1793+ DROP_RETIRE | \
1794+ DROP_ACTIVE)
1795+static ssize_t
1796+i915_drop_caches_read(struct file *filp,
1797+ char __user *ubuf,
1798+ size_t max,
1799+ loff_t *ppos)
1800+{
1801+ char buf[20];
1802+ int len;
1803+
1804+ len = snprintf(buf, sizeof(buf), "0x%08x\n", DROP_ALL);
1805+ if (len > sizeof(buf))
1806+ len = sizeof(buf);
1807+
1808+ return simple_read_from_buffer(ubuf, max, ppos, buf, len);
1809+}
1810+
1811+static ssize_t
1812+i915_drop_caches_write(struct file *filp,
1813+ const char __user *ubuf,
1814+ size_t cnt,
1815+ loff_t *ppos)
1816+{
1817+ struct drm_device *dev = filp->private_data;
1818+ struct drm_i915_private *dev_priv = dev->dev_private;
1819+ struct drm_i915_gem_object *obj, *next;
1820+ char buf[20];
1821+ int val = 0, ret;
1822+
1823+ if (cnt > 0) {
1824+ if (cnt > sizeof(buf) - 1)
1825+ return -EINVAL;
1826+
1827+ if (copy_from_user(buf, ubuf, cnt))
1828+ return -EFAULT;
1829+ buf[cnt] = 0;
1830+
1831+ val = simple_strtoul(buf, NULL, 0);
1832+ }
1833+
1834+ DRM_DEBUG_DRIVER("Dropping caches: 0x%08x\n", val);
1835+
1836+ /* No need to check and wait for gpu resets, only libdrm auto-restarts
1837+ * on ioctls on -EAGAIN. */
1838+ ret = mutex_lock_interruptible(&dev->struct_mutex);
1839+ if (ret)
1840+ return ret;
1841+
1842+ if (val & DROP_ACTIVE) {
1843+ ret = i915_gpu_idle(dev);
1844+ if (ret)
1845+ goto unlock;
1846+ }
1847+
1848+ if (val & (DROP_RETIRE | DROP_ACTIVE))
1849+ i915_gem_retire_requests(dev);
1850+
1851+ if (val & DROP_BOUND) {
1852+ list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list, mm_list)
1853+ if (obj->pin_count == 0) {
1854+ ret = i915_gem_object_unbind(obj);
1855+ if (ret)
1856+ goto unlock;
1857+ }
1858+ }
1859+
1860+ if (val & DROP_UNBOUND) {
1861+ list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, gtt_list)
1862+ if (obj->pages_pin_count == 0) {
1863+ ret = i915_gem_object_put_pages(obj);
1864+ if (ret)
1865+ goto unlock;
1866+ }
1867+ }
1868+
1869+unlock:
1870+ mutex_unlock(&dev->struct_mutex);
1871+
1872+ return ret ?: cnt;
1873+}
1874+
1875+static const struct file_operations i915_drop_caches_fops = {
1876+ .owner = THIS_MODULE,
1877+ .open = simple_open,
1878+ .read = i915_drop_caches_read,
1879+ .write = i915_drop_caches_write,
1880+ .llseek = default_llseek,
1881+};
1882+
17821883 static ssize_t
17831884 i915_max_freq_read(struct file *filp,
17841885 char __user *ubuf,
@@ -2175,6 +2276,12 @@ int i915_debugfs_init(struct drm_minor *minor) · 390 unmodified lines
21752276 if (ret)
21762277 return ret;
21772278
2279+ ret = i915_debugfs_create(minor->debugfs_root, minor,
2280+ "i915_gem_drop_caches",
2281+ &i915_drop_caches_fops);
2282+ if (ret)
2283+ return ret;
2284+
21782285 ret = i915_debugfs_create(minor->debugfs_root, minor,
21792286 "i915_error_state",
21802287 &i915_error_state_fops);
@@ -2206,6 +2313,8 @@ void i915_debugfs_cleanup(struct drm_minor *minor) · 25 unmodified lines
22062313 1, minor);
22072314 drm_debugfs_remove_files((struct drm_info_list *) &i915_cache_sharing_fops,
22082315 1, minor);
2316+ drm_debugfs_remove_files((struct drm_info_list *) &i915_drop_caches_fops,
2317+ 1, minor);
22092318 drm_debugfs_remove_files((struct drm_info_list *) &i915_ring_stop_fops,
22102319 1, minor);
22112320 drm_debugfs_remove_files((struct drm_info_list *) &i915_error_state_fops,
drivers/gpu/drm/i915/i915_dma.c+24−19
@@ -992,6 +992,12 @@ static int i915_getparam(struct drm_device *dev, void *data, · 991 unmodified lines
992992 case I915_PARAM_HAS_PINNED_BATCHES:
993993 value = 1;
994994 break;
995+ case I915_PARAM_HAS_EXEC_NO_RELOC:
996+ value = 1;
997+ break;
998+ case I915_PARAM_HAS_EXEC_HANDLE_LUT:
999+ value = 1;
1000+ break;
9951001 default:
9961002 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
9971003 param->param);
@@ -1070,7 +1076,7 @@ static int i915_set_status_page(struct drm_device *dev, void *data, · 72 unmodified lines
10701076 ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
10711077
10721078 dev_priv->dri1.gfx_hws_cpu_addr =
1073− ioremap_wc(dev_priv->mm.gtt_base_addr + hws->addr, 4096);
1079+ ioremap_wc(dev_priv->gtt.mappable_base + hws->addr, 4096);
10741080 if (dev_priv->dri1.gfx_hws_cpu_addr == NULL) {
10751081 i915_dma_cleanup(dev);
10761082 ring->status_page.gfx_addr = 0;
@@ -1420,9 +1426,9 @@ static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv) · 343 unmodified lines
14201426 if (!ap)
14211427 return;
14221428
1423− ap->ranges[0].base = dev_priv->mm.gtt->gma_bus_addr;
1424− ap->ranges[0].size =
1425− dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1429+ ap->ranges[0].base = dev_priv->gtt.mappable_base;
1430+ ap->ranges[0].size = dev_priv->gtt.mappable_end - dev_priv->gtt.start;
1431+
14261432 primary =
14271433 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
14281434
@@ -1536,18 +1542,17 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) · 107 unmodified lines
15361542 goto put_gmch;
15371543 }
15381544
1539− aperture_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1540− dev_priv->mm.gtt_base_addr = dev_priv->mm.gtt->gma_bus_addr;
1545+ aperture_size = dev_priv->gtt.mappable_end;
15411546
1542− dev_priv->mm.gtt_mapping =
1543− io_mapping_create_wc(dev_priv->mm.gtt_base_addr,
1547+ dev_priv->gtt.mappable =
1548+ io_mapping_create_wc(dev_priv->gtt.mappable_base,
15441549 aperture_size);
1545− if (dev_priv->mm.gtt_mapping == NULL) {
1550+ if (dev_priv->gtt.mappable == NULL) {
15461551 ret = -EIO;
15471552 goto out_rmmap;
15481553 }
15491554
1550− i915_mtrr_setup(dev_priv, dev_priv->mm.gtt_base_addr,
1555+ i915_mtrr_setup(dev_priv, dev_priv->gtt.mappable_base,
15511556 aperture_size);
15521557
15531558 /* The i915 workqueue is primarily used for batched retirement of
@@ -1600,7 +1605,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) · 46 unmodified lines
16001605 pci_enable_msi(dev->pdev);
16011606
16021607 spin_lock_init(&dev_priv->irq_lock);
1603− spin_lock_init(&dev_priv->error_lock);
1608+ spin_lock_init(&dev_priv->gpu_error.lock);
16041609 spin_lock_init(&dev_priv->rps.lock);
16051610 mutex_init(&dev_priv->dpio_lock);
16061611
@@ -1652,15 +1657,15 @@ out_gem_unload: · 45 unmodified lines
16521657 out_mtrrfree:
16531658 if (dev_priv->mm.gtt_mtrr >= 0) {
16541659 mtrr_del(dev_priv->mm.gtt_mtrr,
1655− dev_priv->mm.gtt_base_addr,
1660+ dev_priv->gtt.mappable_base,
16561661 aperture_size);
16571662 dev_priv->mm.gtt_mtrr = -1;
16581663 }
1659− io_mapping_free(dev_priv->mm.gtt_mapping);
1664+ io_mapping_free(dev_priv->gtt.mappable);
16601665 out_rmmap:
16611666 pci_iounmap(dev->pdev, dev_priv->regs);
16621667 put_gmch:
1663− i915_gem_gtt_fini(dev);
1668+ dev_priv->gtt.gtt_remove(dev);
16641669 put_bridge:
16651670 pci_dev_put(dev_priv->bridge_dev);
16661671 free_priv:
@@ -1690,11 +1695,11 @@ int i915_driver_unload(struct drm_device *dev) · 23 unmodified lines
16901695 /* Cancel the retire work handler, which should be idle now. */
16911696 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
16921697
1693− io_mapping_free(dev_priv->mm.gtt_mapping);
1698+ io_mapping_free(dev_priv->gtt.mappable);
16941699 if (dev_priv->mm.gtt_mtrr >= 0) {
16951700 mtrr_del(dev_priv->mm.gtt_mtrr,
1696− dev_priv->mm.gtt_base_addr,
1697− dev_priv->mm.gtt->gtt_mappable_entries * PAGE_SIZE);
1701+ dev_priv->gtt.mappable_base,
1702+ dev_priv->gtt.mappable_end);
16981703 dev_priv->mm.gtt_mtrr = -1;
16991704 }
17001705
@@ -1720,8 +1725,8 @@ int i915_driver_unload(struct drm_device *dev) · 19 unmodified lines
17201725 }
17211726
17221727 /* Free error state after interrupts are fully disabled. */
1723− del_timer_sync(&dev_priv->hangcheck_timer);
1724− cancel_work_sync(&dev_priv->error_work);
1728+ del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
1729+ cancel_work_sync(&dev_priv->gpu_error.work);
17251730 i915_destroy_error_state(dev);
17261731
17271732 if (dev->pdev->msi_enabled)
drivers/gpu/drm/i915/i915_drv.c+9−107
@@ -276,6 +276,7 @@ static const struct intel_device_info intel_valleyview_m_info = { · 275 unmodified lines
276276 .has_bsd_ring = 1,
277277 .has_blt_ring = 1,
278278 .is_valleyview = 1,
279+ .display_mmio_offset = VLV_DISPLAY_BASE,
279280 };
280281
281282 static const struct intel_device_info intel_valleyview_d_info = {
@@ -285,6 +286,7 @@ static const struct intel_device_info intel_valleyview_d_info = { · 3 unmodified lines
285286 .has_bsd_ring = 1,
286287 .has_blt_ring = 1,
287288 .is_valleyview = 1,
289+ .display_mmio_offset = VLV_DISPLAY_BASE,
288290 };
289291
290292 static const struct intel_device_info intel_haswell_d_info = {
@@ -468,6 +470,8 @@ static int i915_drm_freeze(struct drm_device *dev) · 177 unmodified lines
468470 {
469471 struct drm_i915_private *dev_priv = dev->dev_private;
470472
473+ intel_set_power_well(dev, true);
474+
471475 drm_kms_helper_poll_disable(dev);
472476
473477 pci_save_state(dev->pdev);
@@ -779,9 +783,9 @@ int intel_gpu_reset(struct drm_device *dev) · 305 unmodified lines
779783 }
780784
781785 /* Also reset the gpu hangman. */
782− if (dev_priv->stop_rings) {
786+ if (dev_priv->gpu_error.stop_rings) {
783787 DRM_DEBUG("Simulated gpu hang, resetting stop_rings\n");
784− dev_priv->stop_rings = 0;
788+ dev_priv->gpu_error.stop_rings = 0;
785789 if (ret == -ENODEV) {
786790 DRM_ERROR("Reset not implemented, but ignoring "
787791 "error for simulated gpu hangs\n");
@@ -820,12 +824,12 @@ int i915_reset(struct drm_device *dev) · 32 unmodified lines
820824 i915_gem_reset(dev);
821825
822826 ret = -ENODEV;
823− if (get_seconds() - dev_priv->last_gpu_reset < 5)
827+ if (get_seconds() - dev_priv->gpu_error.last_reset < 5)
824828 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
825829 else
826830 ret = intel_gpu_reset(dev);
827831
828− dev_priv->last_gpu_reset = get_seconds();
832+ dev_priv->gpu_error.last_reset = get_seconds();
829833 if (ret) {
830834 DRM_ERROR("Failed to reset chip.\n");
831835 mutex_unlock(&dev->struct_mutex);
@@ -1115,102 +1119,6 @@ MODULE_LICENSE("GPL and additional rights"); · 283 unmodified lines
11151119 ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
11161120 ((reg) < 0x40000) && \
11171121 ((reg) != FORCEWAKE))
1118−
1119−static bool IS_DISPLAYREG(u32 reg)
1120−{
1121− /*
1122− * This should make it easier to transition modules over to the
1123− * new register block scheme, since we can do it incrementally.
1124− */
1125− if (reg >= VLV_DISPLAY_BASE)
1126− return false;
1127−
1128− if (reg >= RENDER_RING_BASE &&
1129− reg < RENDER_RING_BASE + 0xff)
1130− return false;
1131− if (reg >= GEN6_BSD_RING_BASE &&
1132− reg < GEN6_BSD_RING_BASE + 0xff)
1133− return false;
1134− if (reg >= BLT_RING_BASE &&
1135− reg < BLT_RING_BASE + 0xff)
1136− return false;
1137−
1138− if (reg == PGTBL_ER)
1139− return false;
1140−
1141− if (reg >= IPEIR_I965 &&
1142− reg < HWSTAM)
1143− return false;
1144−
1145− if (reg == MI_MODE)
1146− return false;
1147−
1148− if (reg == GFX_MODE_GEN7)
1149− return false;
1150−
1151− if (reg == RENDER_HWS_PGA_GEN7 ||
1152− reg == BSD_HWS_PGA_GEN7 ||
1153− reg == BLT_HWS_PGA_GEN7)
1154− return false;
1155−
1156− if (reg == GEN6_BSD_SLEEP_PSMI_CONTROL ||
1157− reg == GEN6_BSD_RNCID)
1158− return false;
1159−
1160− if (reg == GEN6_BLITTER_ECOSKPD)
1161− return false;
1162−
1163− if (reg >= 0x4000c &&
1164− reg <= 0x4002c)
1165− return false;
1166−
1167− if (reg >= 0x4f000 &&
1168− reg <= 0x4f08f)
1169− return false;
1170−
1171− if (reg >= 0x4f100 &&
1172− reg <= 0x4f11f)
1173− return false;
1174−
1175− if (reg >= VLV_MASTER_IER &&
1176− reg <= GEN6_PMIER)
1177− return false;
1178−
1179− if (reg >= FENCE_REG_SANDYBRIDGE_0 &&
1180− reg < (FENCE_REG_SANDYBRIDGE_0 + (16*8)))
1181− return false;
1182−
1183− if (reg >= VLV_IIR_RW &&
1184− reg <= VLV_ISR)
1185− return false;
1186−
1187− if (reg == FORCEWAKE_VLV ||
1188− reg == FORCEWAKE_ACK_VLV)
1189− return false;
1190−
1191− if (reg == GEN6_GDRST)
1192− return false;
1193−
1194− switch (reg) {
1195− case _3D_CHICKEN3:
1196− case IVB_CHICKEN3:
1197− case GEN7_COMMON_SLICE_CHICKEN1:
1198− case GEN7_L3CNTLREG1:
1199− case GEN7_L3_CHICKEN_MODE_REGISTER:
1200− case GEN7_ROW_CHICKEN2:
1201− case GEN7_L3SQCREG4:
1202− case GEN7_SQ_CHICKEN_MBCUNIT_CONFIG:
1203− case GEN7_HALF_SLICE_CHICKEN1:
1204− case GEN6_MBCTL:
1205− case GEN6_UCGCTL2:
1206− return false;
1207− default:
1208− break;
1209− }
1210−
1211− return true;
1212−}
1213−
12141122 static void
12151123 ilk_dummy_write(struct drm_i915_private *dev_priv)
12161124 {
@@ -1234,8 +1142,6 @@ u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ · 17 unmodified lines
12341142 if (dev_priv->forcewake_count == 0) \
12351143 dev_priv->gt.force_wake_put(dev_priv); \
12361144 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
1237− } else if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
1238− val = read##y(dev_priv->regs + reg + 0x180000); \
12391145 } else { \
12401146 val = read##y(dev_priv->regs + reg); \
12411147 } \
@@ -1262,11 +1168,7 @@ void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ · 20 unmodified lines
12621168 DRM_ERROR("Unknown unclaimed register before writing to %x\n", reg); \
12631169 I915_WRITE_NOTRACE(GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); \
12641170 } \
1265− if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
1266− write##y(val, dev_priv->regs + reg + 0x180000); \
1267− } else { \
1268− write##y(val, dev_priv->regs + reg); \
1269− } \
1171+ write##y(val, dev_priv->regs + reg); \
12701172 if (unlikely(__fifo_ret)) { \
12711173 gen6_gt_check_fifodbg(dev_priv); \
12721174 } \
drivers/gpu/drm/i915/i915_drv.h+239−142
@@ -337,6 +337,7 @@ struct drm_i915_gt_funcs { · 336 unmodified lines
337337 DEV_INFO_FLAG(has_llc)
338338
339339 struct intel_device_info {
340+ u32 display_mmio_offset;
340341 u8 gen;
341342 u8 is_mobile:1;
342343 u8 is_i85x:1;
@@ -364,6 +365,49 @@ struct intel_device_info { · 21 unmodified lines
364365 u8 has_llc:1;
365366 };
366367
368+enum i915_cache_level {
369+ I915_CACHE_NONE = 0,
370+ I915_CACHE_LLC,
371+ I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */
372+};
373+
374+/* The Graphics Translation Table is the way in which GEN hardware translates a
375+ * Graphics Virtual Address into a Physical Address. In addition to the normal
376+ * collateral associated with any va->pa translations GEN hardware also has a
377+ * portion of the GTT which can be mapped by the CPU and remain both coherent
378+ * and correct (in cases like swizzling). That region is referred to as GMADR in
379+ * the spec.
380+ */
381+struct i915_gtt {
382+ unsigned long start; /* Start offset of used GTT */
383+ size_t total; /* Total size GTT can map */
384+ size_t stolen_size; /* Total size of stolen memory */
385+
386+ unsigned long mappable_end; /* End offset that we can CPU map */
387+ struct io_mapping *mappable; /* Mapping to our CPU mappable region */
388+ phys_addr_t mappable_base; /* PA of our GMADR */
389+
390+ /** "Graphics Stolen Memory" holds the global PTEs */
391+ void __iomem *gsm;
392+
393+ bool do_idle_maps;
394+ dma_addr_t scratch_page_dma;
395+ struct page *scratch_page;
396+
397+ /* global gtt ops */
398+ int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total,
399+ size_t *stolen);
400+ void (*gtt_remove)(struct drm_device *dev);
401+ void (*gtt_clear_range)(struct drm_device *dev,
402+ unsigned int first_entry,
403+ unsigned int num_entries);
404+ void (*gtt_insert_entries)(struct drm_device *dev,
405+ struct sg_table *st,
406+ unsigned int pg_start,
407+ enum i915_cache_level cache_level);
408+};
409+#define gtt_total_entries(gtt) ((gtt).total >> PAGE_SHIFT)
410+
367411 #define I915_PPGTT_PD_ENTRIES 512
368412 #define I915_PPGTT_PT_ENTRIES 1024
369413 struct i915_hw_ppgtt {
@@ -373,6 +417,16 @@ struct i915_hw_ppgtt { · 3 unmodified lines
373417 uint32_t pd_offset;
374418 dma_addr_t *pt_dma_addr;
375419 dma_addr_t scratch_page_dma_addr;
420+
421+ /* pte functions, mirroring the interface of the global gtt. */
422+ void (*clear_range)(struct i915_hw_ppgtt *ppgtt,
423+ unsigned int first_entry,
424+ unsigned int num_entries);
425+ void (*insert_entries)(struct i915_hw_ppgtt *ppgtt,
426+ struct sg_table *st,
427+ unsigned int pg_start,
428+ enum i915_cache_level cache_level);
429+ void (*cleanup)(struct i915_hw_ppgtt *ppgtt);
376430 };
377431
378432
@@ -642,6 +696,153 @@ struct intel_l3_parity { · 263 unmodified lines
642696 struct work_struct error_work;
643697 };
644698
699+struct i915_gem_mm {
700+ /** Memory allocator for GTT stolen memory */
701+ struct drm_mm stolen;
702+ /** Memory allocator for GTT */
703+ struct drm_mm gtt_space;
704+ /** List of all objects in gtt_space. Used to restore gtt
705+ * mappings on resume */
706+ struct list_head bound_list;
707+ /**
708+ * List of objects which are not bound to the GTT (thus
709+ * are idle and not used by the GPU) but still have
710+ * (presumably uncached) pages still attached.
711+ */
712+ struct list_head unbound_list;
713+
714+ /** Usable portion of the GTT for GEM */
715+ unsigned long stolen_base; /* limited to low memory (32-bit) */
716+
717+ int gtt_mtrr;
718+
719+ /** PPGTT used for aliasing the PPGTT with the GTT */
720+ struct i915_hw_ppgtt *aliasing_ppgtt;
721+
722+ struct shrinker inactive_shrinker;
723+ bool shrinker_no_lock_stealing;
724+
725+ /**
726+ * List of objects currently involved in rendering.
727+ *
728+ * Includes buffers having the contents of their GPU caches
729+ * flushed, not necessarily primitives. last_rendering_seqno
730+ * represents when the rendering involved will be completed.
731+ *
732+ * A reference is held on the buffer while on this list.
733+ */
734+ struct list_head active_list;
735+
736+ /**
737+ * LRU list of objects which are not in the ringbuffer and
738+ * are ready to unbind, but are still in the GTT.
739+ *
740+ * last_rendering_seqno is 0 while an object is in this list.
741+ *
742+ * A reference is not held on the buffer while on this list,
743+ * as merely being GTT-bound shouldn't prevent its being
744+ * freed, and we'll pull it off the list in the free path.
745+ */
746+ struct list_head inactive_list;
747+
748+ /** LRU list of objects with fence regs on them. */
749+ struct list_head fence_list;
750+
751+ /**
752+ * We leave the user IRQ off as much as possible,
753+ * but this means that requests will finish and never
754+ * be retired once the system goes idle. Set a timer to
755+ * fire periodically while the ring is running. When it
756+ * fires, go retire requests.
757+ */
758+ struct delayed_work retire_work;
759+
760+ /**
761+ * Are we in a non-interruptible section of code like
762+ * modesetting?
763+ */
764+ bool interruptible;
765+
766+ /**
767+ * Flag if the X Server, and thus DRM, is not currently in
768+ * control of the device.
769+ *
770+ * This is set between LeaveVT and EnterVT. It needs to be
771+ * replaced with a semaphore. It also needs to be
772+ * transitioned away from for kernel modesetting.
773+ */
774+ int suspended;
775+
776+ /** Bit 6 swizzling required for X tiling */
777+ uint32_t bit_6_swizzle_x;
778+ /** Bit 6 swizzling required for Y tiling */
779+ uint32_t bit_6_swizzle_y;
780+
781+ /* storage for physical objects */
782+ struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
783+
784+ /* accounting, useful for userland debugging */
785+ size_t object_memory;
786+ u32 object_count;
787+};
788+
789+struct i915_gpu_error {
790+ /* For hangcheck timer */
791+#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
792+#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
793+ struct timer_list hangcheck_timer;
794+ int hangcheck_count;
795+ uint32_t last_acthd[I915_NUM_RINGS];
796+ uint32_t prev_instdone[I915_NUM_INSTDONE_REG];
797+
798+ /* For reset and error_state handling. */
799+ spinlock_t lock;
800+ /* Protected by the above dev->gpu_error.lock. */
801+ struct drm_i915_error_state *first_error;
802+ struct work_struct work;
803+
804+ unsigned long last_reset;
805+
806+ /**
807+ * State variable and reset counter controlling the reset flow
808+ *
809+ * Upper bits are for the reset counter. This counter is used by the
810+ * wait_seqno code to race-free noticed that a reset event happened and
811+ * that it needs to restart the entire ioctl (since most likely the
812+ * seqno it waited for won't ever signal anytime soon).
813+ *
814+ * This is important for lock-free wait paths, where no contended lock
815+ * naturally enforces the correct ordering between the bail-out of the
816+ * waiter and the gpu reset work code.
817+ *
818+ * Lowest bit controls the reset state machine: Set means a reset is in
819+ * progress. This state will (presuming we don't have any bugs) decay
820+ * into either unset (successful reset) or the special WEDGED value (hw
821+ * terminally sour). All waiters on the reset_queue will be woken when
822+ * that happens.
823+ */
824+ atomic_t reset_counter;
825+
826+ /**
827+ * Special values/flags for reset_counter
828+ *
829+ * Note that the code relies on
830+ * I915_WEDGED & I915_RESET_IN_PROGRESS_FLAG
831+ * being true.
832+ */
833+#define I915_RESET_IN_PROGRESS_FLAG 1
834+#define I915_WEDGED 0xffffffff
835+
836+ /**
837+ * Waitqueue to signal when the reset has completed. Used by clients
838+ * that wait for dev_priv->mm.wedged to settle.
839+ */
840+ wait_queue_head_t reset_queue;
841+
842+ /* For gpu hang simulation. */
843+ unsigned int stop_rings;
844+};
845+
645846 typedef struct drm_i915_private {
646847 struct drm_device *dev;
647848 struct kmem_cache *slab;
@@ -697,7 +898,6 @@ typedef struct drm_i915_private { · 49 unmodified lines
697898 u32 pipestat[2];
698899 u32 irq_mask;
699900 u32 gt_irq_mask;
700− u32 pch_irq_mask;
701901
702902 u32 hotplug_supported_mask;
703903 struct work_struct hotplug_work;
@@ -706,16 +906,6 @@ typedef struct drm_i915_private { · 2 unmodified lines
706906 int num_pipe;
707907 int num_pch_pll;
708908
709− /* For hangcheck timer */
710−#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
711−#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
712− struct timer_list hangcheck_timer;
713− int hangcheck_count;
714− uint32_t last_acthd[I915_NUM_RINGS];
715− uint32_t prev_instdone[I915_NUM_INSTDONE_REG];
716−
717− unsigned int stop_rings;
718−
719909 unsigned long cfb_size;
720910 unsigned int cfb_fb;
721911 enum plane cfb_plane;
@@ -763,11 +953,6 @@ typedef struct drm_i915_private { · 41 unmodified lines
763953
764954 unsigned int fsb_freq, mem_freq, is_ddr3;
765955
766− spinlock_t error_lock;
767− /* Protected by dev->error_lock. */
768− struct drm_i915_error_state *first_error;
769− struct work_struct error_work;
770− struct completion error_completion;
771956 struct workqueue_struct *wq;
772957
773958 /* Display functions */
@@ -782,116 +967,9 @@ typedef struct drm_i915_private { · 8 unmodified lines
782967 /* Register state */
783968 bool modeset_on_lid;
784969
785− struct {
786− /** Bridge to intel-gtt-ko */
787− struct intel_gtt *gtt;
788− /** Memory allocator for GTT stolen memory */
789− struct drm_mm stolen;
790− /** Memory allocator for GTT */
791− struct drm_mm gtt_space;
792− /** List of all objects in gtt_space. Used to restore gtt
793− * mappings on resume */
794− struct list_head bound_list;
795− /**
796− * List of objects which are not bound to the GTT (thus
797− * are idle and not used by the GPU) but still have
798− * (presumably uncached) pages still attached.
799− */
800− struct list_head unbound_list;
801−
802− /** Usable portion of the GTT for GEM */
803− unsigned long gtt_start;
804− unsigned long gtt_mappable_end;
805− unsigned long gtt_end;
806− unsigned long stolen_base; /* limited to low memory (32-bit) */
807−
808− /** "Graphics Stolen Memory" holds the global PTEs */
809− void __iomem *gsm;
810−
811− struct io_mapping *gtt_mapping;
812− phys_addr_t gtt_base_addr;
813− int gtt_mtrr;
814−
815− /** PPGTT used for aliasing the PPGTT with the GTT */
816− struct i915_hw_ppgtt *aliasing_ppgtt;
817−
818− struct shrinker inactive_shrinker;
819− bool shrinker_no_lock_stealing;
820−
821− /**
822− * List of objects currently involved in rendering.
823− *
824− * Includes buffers having the contents of their GPU caches
825− * flushed, not necessarily primitives. last_rendering_seqno
826− * represents when the rendering involved will be completed.
827− *
828− * A reference is held on the buffer while on this list.
829− */
830− struct list_head active_list;
831−
832− /**
833− * LRU list of objects which are not in the ringbuffer and
834− * are ready to unbind, but are still in the GTT.
835− *
836− * last_rendering_seqno is 0 while an object is in this list.
837− *
838− * A reference is not held on the buffer while on this list,
839− * as merely being GTT-bound shouldn't prevent its being
840− * freed, and we'll pull it off the list in the free path.
841− */
842− struct list_head inactive_list;
843−
844− /** LRU list of objects with fence regs on them. */
845− struct list_head fence_list;
846−
847− /**
848− * We leave the user IRQ off as much as possible,
849− * but this means that requests will finish and never
850− * be retired once the system goes idle. Set a timer to
851− * fire periodically while the ring is running. When it
852− * fires, go retire requests.
853− */
854− struct delayed_work retire_work;
855−
856− /**
857− * Are we in a non-interruptible section of code like
858− * modesetting?
859− */
860− bool interruptible;
861−
862− /**
863− * Flag if the X Server, and thus DRM, is not currently in
864− * control of the device.
865− *
866− * This is set between LeaveVT and EnterVT. It needs to be
867− * replaced with a semaphore. It also needs to be
868− * transitioned away from for kernel modesetting.
869− */
870− int suspended;
871−
872− /**
873− * Flag if the hardware appears to be wedged.
874− *
875− * This is set when attempts to idle the device timeout.
876− * It prevents command submission from occurring and makes
877− * every pending request fail
878− */
879− atomic_t wedged;
880−
881− /** Bit 6 swizzling required for X tiling */
882− uint32_t bit_6_swizzle_x;
883− /** Bit 6 swizzling required for Y tiling */
884− uint32_t bit_6_swizzle_y;
885−
886− /* storage for physical objects */
887− struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
888−
889− /* accounting, useful for userland debugging */
890− size_t gtt_total;
891− size_t mappable_gtt_total;
892− size_t object_memory;
893− u32 object_count;
894− } mm;
970+ struct i915_gtt gtt;
971+
972+ struct i915_gem_mm mm;
895973
896974 /* Kernel Modesetting */
897975
@@ -933,7 +1011,7 @@ typedef struct drm_i915_private { · 35 unmodified lines
9331011 struct drm_mm_node *compressed_fb;
9341012 struct drm_mm_node *compressed_llb;
9351013
936− unsigned long last_gpu_reset;
1014+ struct i915_gpu_error gpu_error;
9371015
9381016 /* list of fbdev register on this device */
9391017 struct intel_fbdev *fbdev;
@@ -973,12 +1051,6 @@ enum hdmi_force_audio { · 33 unmodified lines
9731051 HDMI_AUDIO_ON, /* force turn on HDMI audio */
9741052 };
9751053
976−enum i915_cache_level {
977− I915_CACHE_NONE = 0,
978− I915_CACHE_LLC,
979− I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */
980−};
981−
9821054 #define I915_GTT_RESERVED ((struct drm_mm_node *)0x1)
9831055
9841056 struct drm_i915_gem_object_ops {
@@ -1446,6 +1518,7 @@ int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, · 461 unmodified lines
14461518 bool nonblocking);
14471519 void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
14481520 int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1521+int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
14491522 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
14501523 void i915_gem_lastclose(struct drm_device *dev);
14511524
@@ -1524,8 +1597,18 @@ i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) · 72 unmodified lines
15241597
15251598 void i915_gem_retire_requests(struct drm_device *dev);
15261599 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
1527−int __must_check i915_gem_check_wedge(struct drm_i915_private *dev_priv,
1600+int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
15281601 bool interruptible);
1602+static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
1603+{
1604+ return unlikely(atomic_read(&error->reset_counter)
1605+ & I915_RESET_IN_PROGRESS_FLAG);
1606+}
1607+
1608+static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
1609+{
1610+ return atomic_read(&error->reset_counter) == I915_WEDGED;
1611+}
15291612
15301613 void i915_gem_reset(struct drm_device *dev);
15311614 void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
@@ -1566,9 +1649,10 @@ void i915_gem_free_all_phys_object(struct drm_device *dev); · 34 unmodified lines
15661649 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
15671650
15681651 uint32_t
1569−i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1570− uint32_t size,
1571− int tiling_mode);
1652+i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
1653+uint32_t
1654+i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1655+ int tiling_mode, bool fenced);
15721656
15731657 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
15741658 enum i915_cache_level cache_level);
@@ -1591,7 +1675,6 @@ int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, · 16 unmodified lines
15911675 struct drm_file *file);
15921676
15931677 /* i915_gem_gtt.c */
1594−int __must_check i915_gem_init_aliasing_ppgtt(struct drm_device *dev);
15951678 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
15961679 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
15971680 struct drm_i915_gem_object *obj,
@@ -1609,7 +1692,6 @@ void i915_gem_init_global_gtt(struct drm_device *dev); · 11 unmodified lines
16091692 void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start,
16101693 unsigned long mappable_end, unsigned long end);
16111694 int i915_gem_gtt_init(struct drm_device *dev);
1612−void i915_gem_gtt_fini(struct drm_device *dev);
16131695 static inline void i915_gem_chipset_flush(struct drm_device *dev)
16141696 {
16151697 if (INTEL_INFO(dev)->gen < 6)
@@ -1668,9 +1750,9 @@ void i915_debugfs_cleanup(struct drm_minor *minor); · 52 unmodified lines
16681750 extern int i915_save_state(struct drm_device *dev);
16691751 extern int i915_restore_state(struct drm_device *dev);
16701752
1671−/* i915_suspend.c */
1672−extern int i915_save_state(struct drm_device *dev);
1673−extern int i915_restore_state(struct drm_device *dev);
1753+/* i915_ums.c */
1754+void i915_save_display_reg(struct drm_device *dev);
1755+void i915_restore_display_reg(struct drm_device *dev);
16741756
16751757 /* i915_sysfs.c */
16761758 void i915_setup_sysfs(struct drm_device *dev_priv);
@@ -1727,6 +1809,7 @@ extern void intel_modeset_cleanup(struct drm_device *dev); · 50 unmodified lines
17271809 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
17281810 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
17291811 bool force_restore);
1812+extern void i915_redisable_vga(struct drm_device *dev);
17301813 extern bool intel_fbc_enabled(struct drm_device *dev);
17311814 extern void intel_disable_fbc(struct drm_device *dev);
17321815 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
@@ -1799,5 +1882,19 @@ __i915_write(64, q) · 66 unmodified lines
17991882 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
18001883 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
18011884
1885+/* "Broadcast RGB" property */
1886+#define INTEL_BROADCAST_RGB_AUTO 0
1887+#define INTEL_BROADCAST_RGB_FULL 1
1888+#define INTEL_BROADCAST_RGB_LIMITED 2
1889+
1890+static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
1891+{
1892+ if (HAS_PCH_SPLIT(dev))
1893+ return CPU_VGACNTRL;
1894+ else if (IS_VALLEYVIEW(dev))
1895+ return VLV_VGACNTRL;
1896+ else
1897+ return VGACNTRL;
1898+}
18021899
18031900 #endif
drivers/gpu/drm/i915/i915_gem.c+140−145
@@ -87,47 +87,43 @@ static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, · 86 unmodified lines
8787 }
8888
8989 static int
90−i915_gem_wait_for_error(struct drm_device *dev)
90+i915_gem_wait_for_error(struct i915_gpu_error *error)
9191 {
92− struct drm_i915_private *dev_priv = dev->dev_private;
93− struct completion *x = &dev_priv->error_completion;
94− unsigned long flags;
9592 int ret;
9693
97− if (!atomic_read(&dev_priv->mm.wedged))
94+#define EXIT_COND (!i915_reset_in_progress(error))
95+ if (EXIT_COND)
9896 return 0;
9997
98+ /* GPU is already declared terminally dead, give up. */
99+ if (i915_terminally_wedged(error))
100+ return -EIO;
101+
100102 /*
101103 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
102104 * userspace. If it takes that long something really bad is going on and
103105 * we should simply try to bail out and fail as gracefully as possible.
104106 */
105− ret = wait_for_completion_interruptible_timeout(x, 10*HZ);
107+ ret = wait_event_interruptible_timeout(error->reset_queue,
108+ EXIT_COND,
109+ 10*HZ);
106110 if (ret == 0) {
107111 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
108112 return -EIO;
109113 } else if (ret < 0) {
110114 return ret;
111115 }
116+#undef EXIT_COND
112117
113− if (atomic_read(&dev_priv->mm.wedged)) {
114− /* GPU is hung, bump the completion count to account for
115− * the token we just consumed so that we never hit zero and
116− * end up waiting upon a subsequent completion event that
117− * will never happen.
118− */
119− spin_lock_irqsave(&x->wait.lock, flags);
120− x->done++;
121− spin_unlock_irqrestore(&x->wait.lock, flags);
122− }
123118 return 0;
124119 }
125120
126121 int i915_mutex_lock_interruptible(struct drm_device *dev)
127122 {
123+ struct drm_i915_private *dev_priv = dev->dev_private;
128124 int ret;
129125
130− ret = i915_gem_wait_for_error(dev);
126+ ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
131127 if (ret)
132128 return ret;
133129
@@ -149,6 +145,7 @@ int · 15 unmodified lines
149145 i915_gem_init_ioctl(struct drm_device *dev, void *data,
150146 struct drm_file *file)
151147 {
148+ struct drm_i915_private *dev_priv = dev->dev_private;
152149 struct drm_i915_gem_init *args = data;
153150
154151 if (drm_core_check_feature(dev, DRIVER_MODESET))
@@ -165,6 +162,7 @@ i915_gem_init_ioctl(struct drm_device *dev, void *data, · 10 unmodified lines
165162 mutex_lock(&dev->struct_mutex);
166163 i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
167164 args->gtt_end);
165+ dev_priv->gtt.mappable_end = args->gtt_end;
168166 mutex_unlock(&dev->struct_mutex);
169167
170168 return 0;
@@ -186,7 +184,7 @@ i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, · 15 unmodified lines
186184 pinned += obj->gtt_space->size;
187185 mutex_unlock(&dev->struct_mutex);
188186
189− args->aper_size = dev_priv->mm.gtt_total;
187+ args->aper_size = dev_priv->gtt.total;
190188 args->aper_available_size = args->aper_size - pinned;
191189
192190 return 0;
@@ -637,7 +635,7 @@ i915_gem_gtt_pwrite_fast(struct drm_device *dev, · 444 unmodified lines
637635 * source page isn't available. Return the error and we'll
638636 * retry in the slow path.
639637 */
640− if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
638+ if (fast_user_write(dev_priv->gtt.mappable, page_base,
641639 page_offset, user_data, page_length)) {
642640 ret = -EFAULT;
643641 goto out_unpin;
@@ -937,26 +935,17 @@ unlock: · 293 unmodified lines
937935 }
938936
939937 int
940−i915_gem_check_wedge(struct drm_i915_private *dev_priv,
938+i915_gem_check_wedge(struct i915_gpu_error *error,
941939 bool interruptible)
942940 {
943− if (atomic_read(&dev_priv->mm.wedged)) {
944− struct completion *x = &dev_priv->error_completion;
945− bool recovery_complete;
946− unsigned long flags;
947−
948− /* Give the error handler a chance to run. */
949− spin_lock_irqsave(&x->wait.lock, flags);
950− recovery_complete = x->done > 0;
951− spin_unlock_irqrestore(&x->wait.lock, flags);
952−
941+ if (i915_reset_in_progress(error)) {
953942 /* Non-interruptible callers can't handle -EAGAIN, hence return
954943 * -EIO unconditionally for these. */
955944 if (!interruptible)
956945 return -EIO;
957946
958− /* Recovery complete, but still wedged means reset failure. */
959− if (recovery_complete)
947+ /* Recovery complete, but the reset failed ... */
948+ if (i915_terminally_wedged(error))
960949 return -EIO;
961950
962951 return -EAGAIN;
@@ -987,13 +976,22 @@ i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno) · 24 unmodified lines
987976 * __wait_seqno - wait until execution of seqno has finished
988977 * @ring: the ring expected to report seqno
989978 * @seqno: duh!
979+ * @reset_counter: reset sequence associated with the given seqno
990980 * @interruptible: do an interruptible wait (normally yes)
991981 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
992982 *
983+ * Note: It is of utmost importance that the passed in seqno and reset_counter
984+ * values have been read by the caller in an smp safe manner. Where read-side
985+ * locks are involved, it is sufficient to read the reset_counter before
986+ * unlocking the lock that protects the seqno. For lockless tricks, the
987+ * reset_counter _must_ be read before, and an appropriate smp_rmb must be
988+ * inserted.
989+ *
993990 * Returns 0 if the seqno was found within the alloted time. Else returns the
994991 * errno with remaining time filled in timeout argument.
995992 */
996993 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
994+ unsigned reset_counter,
997995 bool interruptible, struct timespec *timeout)
998996 {
999997 drm_i915_private_t *dev_priv = ring->dev->dev_private;
@@ -1023,7 +1021,8 @@ static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, · 23 unmodified lines
10231021
10241022 #define EXIT_COND \
10251023 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1026− atomic_read(&dev_priv->mm.wedged))
1024+ i915_reset_in_progress(&dev_priv->gpu_error) || \
1025+ reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10271026 do {
10281027 if (interruptible)
10291028 end = wait_event_interruptible_timeout(ring->irq_queue,
@@ -1033,7 +1032,14 @@ static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, · 3 unmodified lines
10331032 end = wait_event_timeout(ring->irq_queue, EXIT_COND,
10341033 timeout_jiffies);
10351034
1036− ret = i915_gem_check_wedge(dev_priv, interruptible);
1035+ /* We need to check whether any gpu reset happened in between
1036+ * the caller grabbing the seqno and now ... */
1037+ if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1038+ end = -EAGAIN;
1039+
1040+ /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely
1041+ * gone. */
1042+ ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
10371043 if (ret)
10381044 end = ret;
10391045 } while (end == 0 && wait_forever);
@@ -1079,7 +1085,7 @@ i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno) · 39 unmodified lines
10791085 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
10801086 BUG_ON(seqno == 0);
10811087
1082− ret = i915_gem_check_wedge(dev_priv, interruptible);
1088+ ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
10831089 if (ret)
10841090 return ret;
10851091
@@ -1087,7 +1093,9 @@ i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno) · 1 unmodified line
10871093 if (ret)
10881094 return ret;
10891095
1090− return __wait_seqno(ring, seqno, interruptible, NULL);
1096+ return __wait_seqno(ring, seqno,
1097+ atomic_read(&dev_priv->gpu_error.reset_counter),
1098+ interruptible, NULL);
10911099 }
10921100
10931101 /**
@@ -1134,6 +1142,7 @@ i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, · 40 unmodified lines
11341142 struct drm_device *dev = obj->base.dev;
11351143 struct drm_i915_private *dev_priv = dev->dev_private;
11361144 struct intel_ring_buffer *ring = obj->ring;
1145+ unsigned reset_counter;
11371146 u32 seqno;
11381147 int ret;
11391148
@@ -1144,7 +1153,7 @@ i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, · 4 unmodified lines
11441153 if (seqno == 0)
11451154 return 0;
11461155
1147− ret = i915_gem_check_wedge(dev_priv, true);
1156+ ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
11481157 if (ret)
11491158 return ret;
11501159
@@ -1152,8 +1161,9 @@ i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, · 1 unmodified line
11521161 if (ret)
11531162 return ret;
11541163
1164+ reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11551165 mutex_unlock(&dev->struct_mutex);
1156− ret = __wait_seqno(ring, seqno, true, NULL);
1166+ ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
11571167 mutex_lock(&dev->struct_mutex);
11581168
11591169 i915_gem_retire_requests_ring(ring);
@@ -1362,7 +1372,7 @@ int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) · 202 unmodified lines
13621372
13631373 obj->fault_mappable = true;
13641374
1365− pfn = ((dev_priv->mm.gtt_base_addr + obj->gtt_offset) >> PAGE_SHIFT) +
1375+ pfn = ((dev_priv->gtt.mappable_base + obj->gtt_offset) >> PAGE_SHIFT) +
13661376 page_offset;
13671377
13681378 /* Finally, remap it using the new GTT offset */
@@ -1377,7 +1387,7 @@ out: · 8 unmodified lines
13771387 /* If this -EIO is due to a gpu hang, give the reset code a
13781388 * chance to clean up the mess. Otherwise return the proper
13791389 * SIGBUS. */
1380− if (!atomic_read(&dev_priv->mm.wedged))
1390+ if (i915_terminally_wedged(&dev_priv->gpu_error))
13811391 return VM_FAULT_SIGBUS;
13821392 case -EAGAIN:
13831393 /* Give the error handler a chance to run and move the
@@ -1435,7 +1445,7 @@ i915_gem_release_mmap(struct drm_i915_gem_object *obj) · 51 unmodified lines
14351445 obj->fault_mappable = false;
14361446 }
14371447
1438−static uint32_t
1448+uint32_t
14391449 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
14401450 {
14411451 uint32_t gtt_size;
@@ -1463,16 +1473,15 @@ i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) · 21 unmodified lines
14631473 * Return the required GTT alignment for an object, taking into account
14641474 * potential fence register mapping.
14651475 */
1466−static uint32_t
1467−i915_gem_get_gtt_alignment(struct drm_device *dev,
1468− uint32_t size,
1469− int tiling_mode)
1476+uint32_t
1477+i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1478+ int tiling_mode, bool fenced)
14701479 {
14711480 /*
14721481 * Minimum alignment is 4k (GTT page size), but might be greater
14731482 * if a fence register is needed for the object.
14741483 */
1475− if (INTEL_INFO(dev)->gen >= 4 ||
1484+ if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
14761485 tiling_mode == I915_TILING_NONE)
14771486 return 4096;
14781487
@@ -1483,35 +1492,6 @@ i915_gem_get_gtt_alignment(struct drm_device *dev, · 4 unmodified lines
14831492 return i915_gem_get_gtt_size(dev, size, tiling_mode);
14841493 }
14851494
1486−/**
1487− * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1488− * unfenced object
1489− * @dev: the device
1490− * @size: size of the object
1491− * @tiling_mode: tiling mode of the object
1492− *
1493− * Return the required GTT alignment for an object, only taking into account
1494− * unfenced tiled surface requirements.
1495− */
1496−uint32_t
1497−i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1498− uint32_t size,
1499− int tiling_mode)
1500−{
1501− /*
1502− * Minimum alignment is 4k (GTT page size) for sane hw.
1503− */
1504− if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
1505− tiling_mode == I915_TILING_NONE)
1506− return 4096;
1507−
1508− /* Previous hardware however needs to be aligned to a power-of-two
1509− * tile height. The simplest method for determining this is to reuse
1510− * the power-of-tile object size.
1511− */
1512− return i915_gem_get_gtt_size(dev, size, tiling_mode);
1513−}
1514−
15151495 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
15161496 {
15171497 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
@@ -1574,7 +1554,7 @@ i915_gem_mmap_gtt(struct drm_file *file, · 56 unmodified lines
15741554 goto unlock;
15751555 }
15761556
1577− if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
1557+ if (obj->base.size > dev_priv->gtt.mappable_end) {
15781558 ret = -E2BIG;
15791559 goto out;
15801560 }
@@ -1692,7 +1672,7 @@ i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) · 111 unmodified lines
16921672 kfree(obj->pages);
16931673 }
16941674
1695−static int
1675+int
16961676 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
16971677 {
16981678 const struct drm_i915_gem_object_ops *ops = obj->ops;
@@ -1865,6 +1845,11 @@ i915_gem_object_get_pages(struct drm_i915_gem_object *obj) · 166 unmodified lines
18651845 if (obj->pages)
18661846 return 0;
18671847
1848+ if (obj->madv != I915_MADV_WILLNEED) {
1849+ DRM_ERROR("Attempting to obtain a purgeable object\n");
1850+ return -EINVAL;
1851+ }
1852+
18681853 BUG_ON(obj->pages_pin_count);
18691854
18701855 ret = ops->get_pages(obj);
@@ -1921,9 +1906,6 @@ i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) · 50 unmodified lines
19211906 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
19221907 BUG_ON(!obj->active);
19231908
1924− if (obj->pin_count) /* are we a framebuffer? */
1925− intel_mark_fb_idle(obj);
1926−
19271909 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
19281910
19291911 list_del_init(&obj->ring_list);
@@ -2075,7 +2057,7 @@ i915_add_request(struct intel_ring_buffer *ring, · 145 unmodified lines
20752057
20762058 if (!dev_priv->mm.suspended) {
20772059 if (i915_enable_hangcheck) {
2078− mod_timer(&dev_priv->hangcheck_timer,
2060+ mod_timer(&dev_priv->gpu_error.hangcheck_timer,
20792061 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
20802062 }
20812063 if (was_empty) {
@@ -2340,10 +2322,12 @@ i915_gem_object_flush_active(struct drm_i915_gem_object *obj) · 258 unmodified lines
23402322 int
23412323 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
23422324 {
2325+ drm_i915_private_t *dev_priv = dev->dev_private;
23432326 struct drm_i915_gem_wait *args = data;
23442327 struct drm_i915_gem_object *obj;
23452328 struct intel_ring_buffer *ring = NULL;
23462329 struct timespec timeout_stack, *timeout = NULL;
2330+ unsigned reset_counter;
23472331 u32 seqno = 0;
23482332 int ret = 0;
23492333
@@ -2384,9 +2368,10 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) · 34 unmodified lines
23842368 }
23852369
23862370 drm_gem_object_unreference(&obj->base);
2371+ reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
23872372 mutex_unlock(&dev->struct_mutex);
23882373
2389− ret = __wait_seqno(ring, seqno, true, timeout);
2374+ ret = __wait_seqno(ring, seqno, reset_counter, true, timeout);
23902375 if (timeout) {
23912376 WARN_ON(!timespec_valid(timeout));
23922377 args->timeout_ns = timespec_to_ns(timeout);
@@ -2450,15 +2435,15 @@ static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) · 57 unmodified lines
24502435 {
24512436 u32 old_write_domain, old_read_domains;
24522437
2453− /* Act a barrier for all accesses through the GTT */
2454− mb();
2455−
24562438 /* Force a pagefault for domain tracking on next user access */
24572439 i915_gem_release_mmap(obj);
24582440
24592441 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
24602442 return;
24612443
2444+ /* Wait for any direct GTT access to complete */
2445+ mb();
2446+
24622447 old_read_domains = obj->base.read_domains;
24632448 old_write_domain = obj->base.write_domain;
24642449
@@ -2477,7 +2462,7 @@ int · 12 unmodified lines
24772462 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
24782463 {
24792464 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2480− int ret = 0;
2465+ int ret;
24812466
24822467 if (obj->gtt_space == NULL)
24832468 return 0;
@@ -2544,52 +2529,38 @@ int i915_gpu_idle(struct drm_device *dev) · 60 unmodified lines
25442529 return 0;
25452530 }
25462531
2547−static void sandybridge_write_fence_reg(struct drm_device *dev, int reg,
2548− struct drm_i915_gem_object *obj)
2549−{
2550− drm_i915_private_t *dev_priv = dev->dev_private;
2551− uint64_t val;
2552−
2553− if (obj) {
2554− u32 size = obj->gtt_space->size;
2555−
2556− val = (uint64_t)((obj->gtt_offset + size - 4096) &
2557− 0xfffff000) << 32;
2558− val |= obj->gtt_offset & 0xfffff000;
2559− val |= (uint64_t)((obj->stride / 128) - 1) <<
2560− SANDYBRIDGE_FENCE_PITCH_SHIFT;
2561−
2562− if (obj->tiling_mode == I915_TILING_Y)
2563− val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2564− val |= I965_FENCE_REG_VALID;
2565− } else
2566− val = 0;
2567−
2568− I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val);
2569− POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8);
2570−}
2571−
25722532 static void i965_write_fence_reg(struct drm_device *dev, int reg,
25732533 struct drm_i915_gem_object *obj)
25742534 {
25752535 drm_i915_private_t *dev_priv = dev->dev_private;
2536+ int fence_reg;
2537+ int fence_pitch_shift;
25762538 uint64_t val;
25772539
2540+ if (INTEL_INFO(dev)->gen >= 6) {
2541+ fence_reg = FENCE_REG_SANDYBRIDGE_0;
2542+ fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
2543+ } else {
2544+ fence_reg = FENCE_REG_965_0;
2545+ fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
2546+ }
2547+
25782548 if (obj) {
25792549 u32 size = obj->gtt_space->size;
25802550
25812551 val = (uint64_t)((obj->gtt_offset + size - 4096) &
25822552 0xfffff000) << 32;
25832553 val |= obj->gtt_offset & 0xfffff000;
2584− val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2554+ val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
25852555 if (obj->tiling_mode == I915_TILING_Y)
25862556 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
25872557 val |= I965_FENCE_REG_VALID;
25882558 } else
25892559 val = 0;
25902560
2591− I915_WRITE64(FENCE_REG_965_0 + reg * 8, val);
2592− POSTING_READ(FENCE_REG_965_0 + reg * 8);
2561+ fence_reg += reg * 8;
2562+ I915_WRITE64(fence_reg, val);
2563+ POSTING_READ(fence_reg);
25932564 }
25942565
25952566 static void i915_write_fence_reg(struct drm_device *dev, int reg,
@@ -2668,18 +2639,37 @@ static void i830_write_fence_reg(struct drm_device *dev, int reg, · 72 unmodified lines
26682639 POSTING_READ(FENCE_REG_830_0 + reg * 4);
26692640 }
26702641
2642+inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
2643+{
2644+ return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
2645+}
2646+
26712647 static void i915_gem_write_fence(struct drm_device *dev, int reg,
26722648 struct drm_i915_gem_object *obj)
26732649 {
2650+ struct drm_i915_private *dev_priv = dev->dev_private;
2651+
2652+ /* Ensure that all CPU reads are completed before installing a fence
2653+ * and all writes before removing the fence.
2654+ */
2655+ if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
2656+ mb();
2657+
26742658 switch (INTEL_INFO(dev)->gen) {
26752659 case 7:
2676− case 6: sandybridge_write_fence_reg(dev, reg, obj); break;
2660+ case 6:
26772661 case 5:
26782662 case 4: i965_write_fence_reg(dev, reg, obj); break;
26792663 case 3: i915_write_fence_reg(dev, reg, obj); break;
26802664 case 2: i830_write_fence_reg(dev, reg, obj); break;
26812665 default: BUG();
26822666 }
2667+
2668+ /* And similarly be paranoid that no direct access to this region
2669+ * is reordered to before the fence is installed.
2670+ */
2671+ if (i915_gem_object_needs_mb(obj))
2672+ mb();
26832673 }
26842674
26852675 static inline int fence_number(struct drm_i915_private *dev_priv,
@@ -2709,7 +2699,7 @@ static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, · 23 unmodified lines
27092699 }
27102700
27112701 static int
2712−i915_gem_object_flush_fence(struct drm_i915_gem_object *obj)
2702+i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
27132703 {
27142704 if (obj->last_fenced_seqno) {
27152705 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
@@ -2719,12 +2709,6 @@ i915_gem_object_flush_fence(struct drm_i915_gem_object *obj) · 3 unmodified lines
27192709 obj->last_fenced_seqno = 0;
27202710 }
27212711
2722− /* Ensure that all CPU reads are completed before installing a fence
2723− * and all writes before removing the fence.
2724− */
2725− if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
2726− mb();
2727−
27282712 obj->fenced_gpu_access = false;
27292713 return 0;
27302714 }
@@ -2735,7 +2719,7 @@ i915_gem_object_put_fence(struct drm_i915_gem_object *obj) · 4 unmodified lines
27352719 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
27362720 int ret;
27372721
2738− ret = i915_gem_object_flush_fence(obj);
2722+ ret = i915_gem_object_wait_fence(obj);
27392723 if (ret)
27402724 return ret;
27412725
@@ -2809,7 +2793,7 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj) · 67 unmodified lines
28092793 * will need to serialise the write to the associated fence register?
28102794 */
28112795 if (obj->fence_dirty) {
2812− ret = i915_gem_object_flush_fence(obj);
2796+ ret = i915_gem_object_wait_fence(obj);
28132797 if (ret)
28142798 return ret;
28152799 }
@@ -2830,7 +2814,7 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj) · 14 unmodified lines
28302814 if (reg->obj) {
28312815 struct drm_i915_gem_object *old = reg->obj;
28322816
2833− ret = i915_gem_object_flush_fence(old);
2817+ ret = i915_gem_object_wait_fence(old);
28342818 if (ret)
28352819 return ret;
28362820
@@ -2931,21 +2915,16 @@ i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, · 94 unmodified lines
29312915 bool mappable, fenceable;
29322916 int ret;
29332917
2934− if (obj->madv != I915_MADV_WILLNEED) {
2935− DRM_ERROR("Attempting to bind a purgeable object\n");
2936− return -EINVAL;
2937− }
2938−
29392918 fence_size = i915_gem_get_gtt_size(dev,
29402919 obj->base.size,
29412920 obj->tiling_mode);
29422921 fence_alignment = i915_gem_get_gtt_alignment(dev,
29432922 obj->base.size,
2944− obj->tiling_mode);
2923+ obj->tiling_mode, true);
29452924 unfenced_alignment =
2946− i915_gem_get_unfenced_gtt_alignment(dev,
2925+ i915_gem_get_gtt_alignment(dev,
29472926 obj->base.size,
2948− obj->tiling_mode);
2927+ obj->tiling_mode, false);
29492928
29502929 if (alignment == 0)
29512930 alignment = map_and_fenceable ? fence_alignment :
@@ -2961,7 +2940,7 @@ i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, · 9 unmodified lines
29612940 * before evicting everything in a vain attempt to find space.
29622941 */
29632942 if (obj->base.size >
2964− (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2943+ (map_and_fenceable ? dev_priv->gtt.mappable_end : dev_priv->gtt.total)) {
29652944 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
29662945 return -E2BIG;
29672946 }
@@ -2982,7 +2961,7 @@ i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, · 14 unmodified lines
29822961 if (map_and_fenceable)
29832962 ret = drm_mm_insert_node_in_range_generic(&dev_priv->mm.gtt_space, node,
29842963 size, alignment, obj->cache_level,
2985− 0, dev_priv->mm.gtt_mappable_end);
2964+ 0, dev_priv->gtt.mappable_end);
29862965 else
29872966 ret = drm_mm_insert_node_generic(&dev_priv->mm.gtt_space, node,
29882967 size, alignment, obj->cache_level);
@@ -3022,7 +3001,7 @@ i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, · 33 unmodified lines
30223001 (node->start & (fence_alignment - 1)) == 0;
30233002
30243003 mappable =
3025− obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
3004+ obj->gtt_offset + obj->base.size <= dev_priv->gtt.mappable_end;
30263005
30273006 obj->map_and_fenceable = mappable && fenceable;
30283007
@@ -3130,6 +3109,13 @@ i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) · 101 unmodified lines
31303109
31313110 i915_gem_object_flush_cpu_write_domain(obj);
31323111
3112+ /* Serialise direct access to this object with the barriers for
3113+ * coherent writes from the GPU, by effectively invalidating the
3114+ * GTT domain upon first access.
3115+ */
3116+ if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3117+ mb();
3118+
31333119 old_write_domain = obj->base.write_domain;
31343120 old_read_domains = obj->base.read_domains;
31353121
@@ -3436,11 +3422,17 @@ i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) · 300 unmodified lines
34363422 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
34373423 struct drm_i915_gem_request *request;
34383424 struct intel_ring_buffer *ring = NULL;
3425+ unsigned reset_counter;
34393426 u32 seqno = 0;
34403427 int ret;
34413428
3442− if (atomic_read(&dev_priv->mm.wedged))
3443− return -EIO;
3429+ ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
3430+ if (ret)
3431+ return ret;
3432+
3433+ ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
3434+ if (ret)
3435+ return ret;
34443436
34453437 spin_lock(&file_priv->mm.lock);
34463438 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
@@ -3450,12 +3442,13 @@ i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) · 3 unmodified lines
34503442 ring = request->ring;
34513443 seqno = request->seqno;
34523444 }
3445+ reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
34533446 spin_unlock(&file_priv->mm.lock);
34543447
34553448 if (seqno == 0)
34563449 return 0;
34573450
3458− ret = __wait_seqno(ring, seqno, true, NULL);
3451+ ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
34593452 if (ret == 0)
34603453 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
34613454
@@ -3853,7 +3846,7 @@ i915_gem_idle(struct drm_device *dev) · 391 unmodified lines
38533846 * And not confound mm.suspended!
38543847 */
38553848 dev_priv->mm.suspended = 1;
3856− del_timer_sync(&dev_priv->hangcheck_timer);
3849+ del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
38573850
38583851 i915_kernel_lost_context(dev);
38593852 i915_gem_cleanup_ringbuffer(dev);
@@ -3953,8 +3946,6 @@ i915_gem_init_hw(struct drm_device *dev) · 93 unmodified lines
39533946
39543947 i915_gem_init_swizzling(dev);
39553948
3956− dev_priv->next_seqno = dev_priv->last_seqno = (u32)~0 - 0x1000;
3957−
39583949 ret = intel_init_render_ring_buffer(dev);
39593950 if (ret)
39603951 return ret;
@@ -3971,6 +3962,10 @@ i915_gem_init_hw(struct drm_device *dev) · 10 unmodified lines
39713962 goto cleanup_bsd_ring;
39723963 }
39733964
3965+ ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
3966+ if (ret)
3967+ return ret;
3968+
39743969 /*
39753970 * XXX: There was some w/a described somewhere suggesting loading
39763971 * contexts before PPGTT.
@@ -4028,9 +4023,9 @@ i915_gem_entervt_ioctl(struct drm_device *dev, void *data, · 51 unmodified lines
40284023 if (drm_core_check_feature(dev, DRIVER_MODESET))
40294024 return 0;
40304025
4031− if (atomic_read(&dev_priv->mm.wedged)) {
4026+ if (i915_reset_in_progress(&dev_priv->gpu_error)) {
40324027 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4033− atomic_set(&dev_priv->mm.wedged, 0);
4028+ atomic_set(&dev_priv->gpu_error.reset_counter, 0);
40344029 }
40354030
40364031 mutex_lock(&dev->struct_mutex);
@@ -4114,7 +4109,7 @@ i915_gem_load(struct drm_device *dev) · 77 unmodified lines
41144109 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
41154110 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
41164111 i915_gem_retire_work_handler);
4117− init_completion(&dev_priv->error_completion);
4112+ init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
41184113
41194114 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
41204115 if (IS_GEN3(dev)) {
drivers/gpu/drm/i915/i915_gem_evict.c+1−1
@@ -80,7 +80,7 @@ i915_gem_evict_something(struct drm_device *dev, int min_size, · 79 unmodified lines
8080 if (mappable)
8181 drm_mm_init_scan_with_range(&dev_priv->mm.gtt_space,
8282 min_size, alignment, cache_level,
83− 0, dev_priv->mm.gtt_mappable_end);
83+ 0, dev_priv->gtt.mappable_end);
8484 else
8585 drm_mm_init_scan(&dev_priv->mm.gtt_space,
8686 min_size, alignment, cache_level);
drivers/gpu/drm/i915/i915_gem_execbuffer.c+163−117
@@ -34,61 +34,133 @@ · 33 unmodified lines
3434 #include <linux/dma_remapping.h>
3535
3636 struct eb_objects {
37+ struct list_head objects;
3738 int and;
38− struct hlist_head buckets[0];
39+ union {
40+ struct drm_i915_gem_object *lut[0];
41+ struct hlist_head buckets[0];
42+ };
3943 };
4044
4145 static struct eb_objects *
42−eb_create(int size)
46+eb_create(struct drm_i915_gem_execbuffer2 *args)
4347 {
44− struct eb_objects *eb;
45− int count = PAGE_SIZE / sizeof(struct hlist_head) / 2;
46− BUILD_BUG_ON(!is_power_of_2(PAGE_SIZE / sizeof(struct hlist_head)));
47− while (count > size)
48− count >>= 1;
49− eb = kzalloc(count*sizeof(struct hlist_head) +
50− sizeof(struct eb_objects),
51− GFP_KERNEL);
52− if (eb == NULL)
53− return eb;
54−
55− eb->and = count - 1;
48+ struct eb_objects *eb = NULL;
49+
50+ if (args->flags & I915_EXEC_HANDLE_LUT) {
51+ int size = args->buffer_count;
52+ size *= sizeof(struct drm_i915_gem_object *);
53+ size += sizeof(struct eb_objects);
54+ eb = kmalloc(size, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY);
55+ }
56+
57+ if (eb == NULL) {
58+ int size = args->buffer_count;
59+ int count = PAGE_SIZE / sizeof(struct hlist_head) / 2;
60+ BUILD_BUG_ON(!is_power_of_2(PAGE_SIZE / sizeof(struct hlist_head)));
61+ while (count > 2*size)
62+ count >>= 1;
63+ eb = kzalloc(count*sizeof(struct hlist_head) +
64+ sizeof(struct eb_objects),
65+ GFP_TEMPORARY);
66+ if (eb == NULL)
67+ return eb;
68+
69+ eb->and = count - 1;
70+ } else
71+ eb->and = -args->buffer_count;
72+
73+ INIT_LIST_HEAD(&eb->objects);
5674 return eb;
5775 }
5876
5977 static void
6078 eb_reset(struct eb_objects *eb)
6179 {
62− memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head));
80+ if (eb->and >= 0)
81+ memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head));
6382 }
6483
65−static void
66−eb_add_object(struct eb_objects *eb, struct drm_i915_gem_object *obj)
84+static int
85+eb_lookup_objects(struct eb_objects *eb,
86+ struct drm_i915_gem_exec_object2 *exec,
87+ const struct drm_i915_gem_execbuffer2 *args,
88+ struct drm_file *file)
6789 {
68− hlist_add_head(&obj->exec_node,
69− &eb->buckets[obj->exec_handle & eb->and]);
90+ int i;
91+
92+ spin_lock(&file->table_lock);
93+ for (i = 0; i < args->buffer_count; i++) {
94+ struct drm_i915_gem_object *obj;
95+
96+ obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle));
97+ if (obj == NULL) {
98+ spin_unlock(&file->table_lock);
99+ DRM_DEBUG("Invalid object handle %d at index %d\n",
100+ exec[i].handle, i);
101+ return -ENOENT;
102+ }
103+
104+ if (!list_empty(&obj->exec_list)) {
105+ spin_unlock(&file->table_lock);
106+ DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
107+ obj, exec[i].handle, i);
108+ return -EINVAL;
109+ }
110+
111+ drm_gem_object_reference(&obj->base);
112+ list_add_tail(&obj->exec_list, &eb->objects);
113+
114+ obj->exec_entry = &exec[i];
115+ if (eb->and < 0) {
116+ eb->lut[i] = obj;
117+ } else {
118+ uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle;
119+ obj->exec_handle = handle;
120+ hlist_add_head(&obj->exec_node,
121+ &eb->buckets[handle & eb->and]);
122+ }
123+ }
124+ spin_unlock(&file->table_lock);
125+
126+ return 0;
70127 }
71128
72129 static struct drm_i915_gem_object *
73130 eb_get_object(struct eb_objects *eb, unsigned long handle)
74131 {
75− struct hlist_head *head;
76− struct hlist_node *node;
77− struct drm_i915_gem_object *obj;
132+ if (eb->and < 0) {
133+ if (handle >= -eb->and)
134+ return NULL;
135+ return eb->lut[handle];
136+ } else {
137+ struct hlist_head *head;
138+ struct hlist_node *node;
78139
79− head = &eb->buckets[handle & eb->and];
80− hlist_for_each(node, head) {
81− obj = hlist_entry(node, struct drm_i915_gem_object, exec_node);
82− if (obj->exec_handle == handle)
83− return obj;
84− }
140+ head = &eb->buckets[handle & eb->and];
141+ hlist_for_each(node, head) {
142+ struct drm_i915_gem_object *obj;
85143
86− return NULL;
144+ obj = hlist_entry(node, struct drm_i915_gem_object, exec_node);
145+ if (obj->exec_handle == handle)
146+ return obj;
147+ }
148+ return NULL;
149+ }
87150 }
88151
89152 static void
90153 eb_destroy(struct eb_objects *eb)
91154 {
155+ while (!list_empty(&eb->objects)) {
156+ struct drm_i915_gem_object *obj;
157+
158+ obj = list_first_entry(&eb->objects,
159+ struct drm_i915_gem_object,
160+ exec_list);
161+ list_del_init(&obj->exec_list);
162+ drm_gem_object_unreference(&obj->base);
163+ }
92164 kfree(eb);
93165 }
94166
@@ -209,7 +281,7 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, · 114 unmodified lines
209281
210282 /* Map the page containing the relocation we're going to perform. */
211283 reloc->offset += obj->gtt_offset;
212− reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
284+ reloc_page = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
213285 reloc->offset & PAGE_MASK);
214286 reloc_entry = (uint32_t __iomem *)
215287 (reloc_page + (reloc->offset & ~PAGE_MASK));
@@ -288,8 +360,7 @@ i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object *obj, · 72 unmodified lines
288360
289361 static int
290362 i915_gem_execbuffer_relocate(struct drm_device *dev,
291− struct eb_objects *eb,
292− struct list_head *objects)
363+ struct eb_objects *eb)
293364 {
294365 struct drm_i915_gem_object *obj;
295366 int ret = 0;
@@ -302,7 +373,7 @@ i915_gem_execbuffer_relocate(struct drm_device *dev, · 6 unmodified lines
302373 * lockdep complains vehemently.
303374 */
304375 pagefault_disable();
305− list_for_each_entry(obj, objects, exec_list) {
376+ list_for_each_entry(obj, &eb->objects, exec_list) {
306377 ret = i915_gem_execbuffer_relocate_object(obj, eb);
307378 if (ret)
308379 break;
@@ -324,7 +395,8 @@ need_reloc_mappable(struct drm_i915_gem_object *obj) · 15 unmodified lines
324395
325396 static int
326397 i915_gem_execbuffer_reserve_object(struct drm_i915_gem_object *obj,
327− struct intel_ring_buffer *ring)
398+ struct intel_ring_buffer *ring,
399+ bool *need_reloc)
328400 {
329401 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
330402 struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
@@ -365,7 +437,20 @@ i915_gem_execbuffer_reserve_object(struct drm_i915_gem_object *obj, · 34 unmodified lines
365437 obj->has_aliasing_ppgtt_mapping = 1;
366438 }
367439
368− entry->offset = obj->gtt_offset;
440+ if (entry->offset != obj->gtt_offset) {
441+ entry->offset = obj->gtt_offset;
442+ *need_reloc = true;
443+ }
444+
445+ if (entry->flags & EXEC_OBJECT_WRITE) {
446+ obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER;
447+ obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER;
448+ }
449+
450+ if (entry->flags & EXEC_OBJECT_NEEDS_GTT &&
451+ !obj->has_global_gtt_mapping)
452+ i915_gem_gtt_bind_object(obj, obj->cache_level);
453+
369454 return 0;
370455 }
371456
@@ -391,7 +476,8 @@ i915_gem_execbuffer_unreserve_object(struct drm_i915_gem_object *obj) · 19 unmodified lines
391476 static int
392477 i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring,
393478 struct drm_file *file,
394− struct list_head *objects)
479+ struct list_head *objects,
480+ bool *need_relocs)
395481 {
396482 struct drm_i915_gem_object *obj;
397483 struct list_head ordered_objects;
@@ -419,7 +505,7 @@ i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring, · 21 unmodified lines
419505 else
420506 list_move_tail(&obj->exec_list, &ordered_objects);
421507
422− obj->base.pending_read_domains = 0;
508+ obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND;
423509 obj->base.pending_write_domain = 0;
424510 obj->pending_fenced_gpu_access = false;
425511 }
@@ -459,7 +545,7 @@ i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring, · 33 unmodified lines
459545 (need_mappable && !obj->map_and_fenceable))
460546 ret = i915_gem_object_unbind(obj);
461547 else
462− ret = i915_gem_execbuffer_reserve_object(obj, ring);
548+ ret = i915_gem_execbuffer_reserve_object(obj, ring, need_relocs);
463549 if (ret)
464550 goto err;
465551 }
@@ -469,7 +555,7 @@ i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring, · 3 unmodified lines
469555 if (obj->gtt_space)
470556 continue;
471557
472− ret = i915_gem_execbuffer_reserve_object(obj, ring);
558+ ret = i915_gem_execbuffer_reserve_object(obj, ring, need_relocs);
473559 if (ret)
474560 goto err;
475561 }
@@ -489,21 +575,22 @@ err: /* Decrement pin count for bound objects */ · 13 unmodified lines
489575
490576 static int
491577 i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
578+ struct drm_i915_gem_execbuffer2 *args,
492579 struct drm_file *file,
493580 struct intel_ring_buffer *ring,
494− struct list_head *objects,
495581 struct eb_objects *eb,
496− struct drm_i915_gem_exec_object2 *exec,
497− int count)
582+ struct drm_i915_gem_exec_object2 *exec)
498583 {
499584 struct drm_i915_gem_relocation_entry *reloc;
500585 struct drm_i915_gem_object *obj;
586+ bool need_relocs;
501587 int *reloc_offset;
502588 int i, total, ret;
589+ int count = args->buffer_count;
503590
504591 /* We may process another execbuffer during the unlock... */
505− while (!list_empty(objects)) {
506− obj = list_first_entry(objects,
592+ while (!list_empty(&eb->objects)) {
593+ obj = list_first_entry(&eb->objects,
507594 struct drm_i915_gem_object,
508595 exec_list);
509596 list_del_init(&obj->exec_list);
@@ -550,27 +637,16 @@ i915_gem_execbuffer_relocate_slow(struct drm_device *dev, · 40 unmodified lines
550637
551638 /* reacquire the objects */
552639 eb_reset(eb);
553− for (i = 0; i < count; i++) {
554− obj = to_intel_bo(drm_gem_object_lookup(dev, file,
555− exec[i].handle));
556− if (&obj->base == NULL) {
557− DRM_DEBUG("Invalid object handle %d at index %d\n",
558− exec[i].handle, i);
559− ret = -ENOENT;
560− goto err;
561− }
562−
563− list_add_tail(&obj->exec_list, objects);
564− obj->exec_handle = exec[i].handle;
565− obj->exec_entry = &exec[i];
566− eb_add_object(eb, obj);
567− }
640+ ret = eb_lookup_objects(eb, exec, args, file);
641+ if (ret)
642+ goto err;
568643
569− ret = i915_gem_execbuffer_reserve(ring, file, objects);
644+ need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
645+ ret = i915_gem_execbuffer_reserve(ring, file, &eb->objects, &need_relocs);
570646 if (ret)
571647 goto err;
572648
573− list_for_each_entry(obj, objects, exec_list) {
649+ list_for_each_entry(obj, &eb->objects, exec_list) {
574650 int offset = obj->exec_entry - exec;
575651 ret = i915_gem_execbuffer_relocate_object_slow(obj, eb,
576652 reloc + reloc_offset[offset]);
@@ -624,6 +700,9 @@ i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring, · 47 unmodified lines
624700 static bool
625701 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
626702 {
703+ if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS)
704+ return false;
705+
627706 return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0;
628707 }
629708
@@ -637,6 +716,9 @@ validate_exec_list(struct drm_i915_gem_exec_object2 *exec, · 7 unmodified lines
637716 char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr;
638717 int length; /* limited by fault_in_pages_readable() */
639718
719+ if (exec[i].flags & __EXEC_OBJECT_UNKNOWN_FLAGS)
720+ return -EINVAL;
721+
640722 /* First check for malicious input causing overflow */
641723 if (exec[i].relocation_count >
642724 INT_MAX / sizeof(struct drm_i915_gem_relocation_entry))
@@ -644,9 +726,6 @@ validate_exec_list(struct drm_i915_gem_exec_object2 *exec, · 1 unmodified line
644726
645727 length = exec[i].relocation_count *
646728 sizeof(struct drm_i915_gem_relocation_entry);
647− if (!access_ok(VERIFY_READ, ptr, length))
648− return -EFAULT;
649−
650729 /* we may also need to update the presumed offsets */
651730 if (!access_ok(VERIFY_WRITE, ptr, length))
652731 return -EFAULT;
@@ -668,8 +747,10 @@ i915_gem_execbuffer_move_to_active(struct list_head *objects, · 15 unmodified lines
668747 u32 old_read = obj->base.read_domains;
669748 u32 old_write = obj->base.write_domain;
670749
671− obj->base.read_domains = obj->base.pending_read_domains;
672750 obj->base.write_domain = obj->base.pending_write_domain;
751+ if (obj->base.write_domain == 0)
752+ obj->base.pending_read_domains |= obj->base.read_domains;
753+ obj->base.read_domains = obj->base.pending_read_domains;
673754 obj->fenced_gpu_access = obj->pending_fenced_gpu_access;
674755
675756 i915_gem_object_move_to_active(obj, ring);
@@ -728,21 +809,18 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data, · 52 unmodified lines
728809 struct drm_i915_gem_exec_object2 *exec)
729810 {
730811 drm_i915_private_t *dev_priv = dev->dev_private;
731− struct list_head objects;
732812 struct eb_objects *eb;
733813 struct drm_i915_gem_object *batch_obj;
734814 struct drm_clip_rect *cliprects = NULL;
735815 struct intel_ring_buffer *ring;
736816 u32 ctx_id = i915_execbuffer2_get_context_id(*args);
737817 u32 exec_start, exec_len;
738− u32 mask;
739− u32 flags;
818+ u32 mask, flags;
740819 int ret, mode, i;
820+ bool need_relocs;
741821
742− if (!i915_gem_check_execbuffer(args)) {
743− DRM_DEBUG("execbuf with invalid offset/length\n");
822+ if (!i915_gem_check_execbuffer(args))
744823 return -EINVAL;
745− }
746824
747825 ret = validate_exec_list(exec, args->buffer_count);
748826 if (ret)
@@ -863,7 +941,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data, · 114 unmodified lines
863941 goto pre_mutex_err;
864942 }
865943
866− eb = eb_create(args->buffer_count);
944+ eb = eb_create(args);
867945 if (eb == NULL) {
868946 mutex_unlock(&dev->struct_mutex);
869947 ret = -ENOMEM;
@@ -871,51 +949,28 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data, · 1 unmodified line
871949 }
872950
873951 /* Look up object handles */
874− INIT_LIST_HEAD(&objects);
875− for (i = 0; i < args->buffer_count; i++) {
876− struct drm_i915_gem_object *obj;
877−
878− obj = to_intel_bo(drm_gem_object_lookup(dev, file,
879− exec[i].handle));
880− if (&obj->base == NULL) {
881− DRM_DEBUG("Invalid object handle %d at index %d\n",
882− exec[i].handle, i);
883− /* prevent error path from reading uninitialized data */
884− ret = -ENOENT;
885− goto err;
886− }
887−
888− if (!list_empty(&obj->exec_list)) {
889− DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
890− obj, exec[i].handle, i);
891− ret = -EINVAL;
892− goto err;
893− }
894−
895− list_add_tail(&obj->exec_list, &objects);
896− obj->exec_handle = exec[i].handle;
897− obj->exec_entry = &exec[i];
898− eb_add_object(eb, obj);
899− }
952+ ret = eb_lookup_objects(eb, exec, args, file);
953+ if (ret)
954+ goto err;
900955
901956 /* take note of the batch buffer before we might reorder the lists */
902− batch_obj = list_entry(objects.prev,
957+ batch_obj = list_entry(eb->objects.prev,
903958 struct drm_i915_gem_object,
904959 exec_list);
905960
906961 /* Move the objects en-masse into the GTT, evicting if necessary. */
907− ret = i915_gem_execbuffer_reserve(ring, file, &objects);
962+ need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
963+ ret = i915_gem_execbuffer_reserve(ring, file, &eb->objects, &need_relocs);
908964 if (ret)
909965 goto err;
910966
911967 /* The objects are in their final locations, apply the relocations. */
912− ret = i915_gem_execbuffer_relocate(dev, eb, &objects);
968+ if (need_relocs)
969+ ret = i915_gem_execbuffer_relocate(dev, eb);
913970 if (ret) {
914971 if (ret == -EFAULT) {
915− ret = i915_gem_execbuffer_relocate_slow(dev, file, ring,
916− &objects, eb,
917− exec,
918− args->buffer_count);
972+ ret = i915_gem_execbuffer_relocate_slow(dev, args, file, ring,
973+ eb, exec);
919974 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
920975 }
921976 if (ret)
@@ -937,7 +992,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data, · 15 unmodified lines
937992 if (flags & I915_DISPATCH_SECURE && !batch_obj->has_global_gtt_mapping)
938993 i915_gem_gtt_bind_object(batch_obj, batch_obj->cache_level);
939994
940− ret = i915_gem_execbuffer_move_to_gpu(ring, &objects);
995+ ret = i915_gem_execbuffer_move_to_gpu(ring, &eb->objects);
941996 if (ret)
942997 goto err;
943998
@@ -991,20 +1046,11 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data, · 47 unmodified lines
9911046
9921047 trace_i915_gem_ring_dispatch(ring, intel_ring_get_seqno(ring), flags);
9931048
994− i915_gem_execbuffer_move_to_active(&objects, ring);
1049+ i915_gem_execbuffer_move_to_active(&eb->objects, ring);
9951050 i915_gem_execbuffer_retire_commands(dev, file, ring);
9961051
9971052 err:
9981053 eb_destroy(eb);
999− while (!list_empty(&objects)) {
1000− struct drm_i915_gem_object *obj;
1001−
1002− obj = list_first_entry(&objects,
1003− struct drm_i915_gem_object,
1004− exec_list);
1005− list_del_init(&obj->exec_list);
1006− drm_gem_object_unreference(&obj->base);
1007− }
10081054
10091055 mutex_unlock(&dev->struct_mutex);
10101056
@@ -1113,7 +1159,7 @@ i915_gem_execbuffer2(struct drm_device *dev, void *data, · 102 unmodified lines
11131159 }
11141160
11151161 exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count,
1116− GFP_KERNEL | __GFP_NOWARN | __GFP_NORETRY);
1162+ GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY);
11171163 if (exec2_list == NULL)
11181164 exec2_list = drm_malloc_ab(sizeof(*exec2_list),
11191165 args->buffer_count);
drivers/gpu/drm/i915/i915_gem_gtt.c+324−266
@@ -44,9 +44,9 @@ typedef uint32_t gtt_pte_t; · 43 unmodified lines
4444 #define GEN6_PTE_CACHE_LLC_MLC (3 << 1)
4545 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
4646
47−static inline gtt_pte_t pte_encode(struct drm_device *dev,
48− dma_addr_t addr,
49− enum i915_cache_level level)
47+static inline gtt_pte_t gen6_pte_encode(struct drm_device *dev,
48+ dma_addr_t addr,
49+ enum i915_cache_level level)
5050 {
5151 gtt_pte_t pte = GEN6_PTE_VALID;
5252 pte |= GEN6_PTE_ADDR_ENCODE(addr);
@@ -77,7 +77,7 @@ static inline gtt_pte_t pte_encode(struct drm_device *dev, · 24 unmodified lines
7777 }
7878
7979 /* PPGTT support for Sandybdrige/Gen6 and later */
80−static void i915_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt,
80+static void gen6_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt,
8181 unsigned first_entry,
8282 unsigned num_entries)
8383 {
@@ -87,8 +87,9 @@ static void i915_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt, · 3 unmodified lines
8787 unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
8888 unsigned last_pte, i;
8989
90− scratch_pte = pte_encode(ppgtt->dev, ppgtt->scratch_page_dma_addr,
91− I915_CACHE_LLC);
90+ scratch_pte = gen6_pte_encode(ppgtt->dev,
91+ ppgtt->scratch_page_dma_addr,
92+ I915_CACHE_LLC);
9293
9394 while (num_entries) {
9495 last_pte = first_pte + num_entries;
@@ -108,10 +109,72 @@ static void i915_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt, · 13 unmodified lines
108109 }
109110 }
110111
111−int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
112+static void gen6_ppgtt_insert_entries(struct i915_hw_ppgtt *ppgtt,
113+ struct sg_table *pages,
114+ unsigned first_entry,
115+ enum i915_cache_level cache_level)
112116 {
117+ gtt_pte_t *pt_vaddr;
118+ unsigned act_pd = first_entry / I915_PPGTT_PT_ENTRIES;
119+ unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
120+ unsigned i, j, m, segment_len;
121+ dma_addr_t page_addr;
122+ struct scatterlist *sg;
123+
124+ /* init sg walking */
125+ sg = pages->sgl;
126+ i = 0;
127+ segment_len = sg_dma_len(sg) >> PAGE_SHIFT;
128+ m = 0;
129+
130+ while (i < pages->nents) {
131+ pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pd]);
132+
133+ for (j = first_pte; j < I915_PPGTT_PT_ENTRIES; j++) {
134+ page_addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
135+ pt_vaddr[j] = gen6_pte_encode(ppgtt->dev, page_addr,
136+ cache_level);
137+
138+ /* grab the next page */
139+ if (++m == segment_len) {
140+ if (++i == pages->nents)
141+ break;
142+
143+ sg = sg_next(sg);
144+ segment_len = sg_dma_len(sg) >> PAGE_SHIFT;
145+ m = 0;
146+ }
147+ }
148+
149+ kunmap_atomic(pt_vaddr);
150+
151+ first_pte = 0;
152+ act_pd++;
153+ }
154+}
155+
156+static void gen6_ppgtt_cleanup(struct i915_hw_ppgtt *ppgtt)
157+{
158+ int i;
159+
160+ if (ppgtt->pt_dma_addr) {
161+ for (i = 0; i < ppgtt->num_pd_entries; i++)
162+ pci_unmap_page(ppgtt->dev->pdev,
163+ ppgtt->pt_dma_addr[i],
164+ 4096, PCI_DMA_BIDIRECTIONAL);
165+ }
166+
167+ kfree(ppgtt->pt_dma_addr);
168+ for (i = 0; i < ppgtt->num_pd_entries; i++)
169+ __free_page(ppgtt->pt_pages[i]);
170+ kfree(ppgtt->pt_pages);
171+ kfree(ppgtt);
172+}
173+
174+static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
175+{
176+ struct drm_device *dev = ppgtt->dev;
113177 struct drm_i915_private *dev_priv = dev->dev_private;
114− struct i915_hw_ppgtt *ppgtt;
115178 unsigned first_pd_entry_in_global_pt;
116179 int i;
117180 int ret = -ENOMEM;
@@ -119,18 +182,17 @@ int i915_gem_init_aliasing_ppgtt(struct drm_device *dev) · 1 unmodified line
119182 /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024
120183 * entries. For aliasing ppgtt support we just steal them at the end for
121184 * now. */
122− first_pd_entry_in_global_pt = dev_priv->mm.gtt->gtt_total_entries - I915_PPGTT_PD_ENTRIES;
185+ first_pd_entry_in_global_pt =
186+ gtt_total_entries(dev_priv->gtt) - I915_PPGTT_PD_ENTRIES;
123187
124− ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
125− if (!ppgtt)
126− return ret;
127−
128− ppgtt->dev = dev;
129188 ppgtt->num_pd_entries = I915_PPGTT_PD_ENTRIES;
189+ ppgtt->clear_range = gen6_ppgtt_clear_range;
190+ ppgtt->insert_entries = gen6_ppgtt_insert_entries;
191+ ppgtt->cleanup = gen6_ppgtt_cleanup;
130192 ppgtt->pt_pages = kzalloc(sizeof(struct page *)*ppgtt->num_pd_entries,
131193 GFP_KERNEL);
132194 if (!ppgtt->pt_pages)
133− goto err_ppgtt;
195+ return -ENOMEM;
134196
135197 for (i = 0; i < ppgtt->num_pd_entries; i++) {
136198 ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
@@ -138,39 +200,32 @@ int i915_gem_init_aliasing_ppgtt(struct drm_device *dev) · 1 unmodified line
138200 goto err_pt_alloc;
139201 }
140202
141− if (dev_priv->mm.gtt->needs_dmar) {
142− ppgtt->pt_dma_addr = kzalloc(sizeof(dma_addr_t)
143− *ppgtt->num_pd_entries,
144− GFP_KERNEL);
145− if (!ppgtt->pt_dma_addr)
146− goto err_pt_alloc;
203+ ppgtt->pt_dma_addr = kzalloc(sizeof(dma_addr_t) *ppgtt->num_pd_entries,
204+ GFP_KERNEL);
205+ if (!ppgtt->pt_dma_addr)
206+ goto err_pt_alloc;
147207
148− for (i = 0; i < ppgtt->num_pd_entries; i++) {
149− dma_addr_t pt_addr;
208+ for (i = 0; i < ppgtt->num_pd_entries; i++) {
209+ dma_addr_t pt_addr;
150210
151− pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i],
152− 0, 4096,
153− PCI_DMA_BIDIRECTIONAL);
211+ pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096,
212+ PCI_DMA_BIDIRECTIONAL);
154213
155− if (pci_dma_mapping_error(dev->pdev,
156− pt_addr)) {
157− ret = -EIO;
158− goto err_pd_pin;
214+ if (pci_dma_mapping_error(dev->pdev, pt_addr)) {
215+ ret = -EIO;
216+ goto err_pd_pin;
159217
160− }
161− ppgtt->pt_dma_addr[i] = pt_addr;
162218 }
219+ ppgtt->pt_dma_addr[i] = pt_addr;
163220 }
164221
165− ppgtt->scratch_page_dma_addr = dev_priv->mm.gtt->scratch_page_dma;
222+ ppgtt->scratch_page_dma_addr = dev_priv->gtt.scratch_page_dma;
166223
167− i915_ppgtt_clear_range(ppgtt, 0,
168− ppgtt->num_pd_entries*I915_PPGTT_PT_ENTRIES);
224+ ppgtt->clear_range(ppgtt, 0,
225+ ppgtt->num_pd_entries*I915_PPGTT_PT_ENTRIES);
169226
170227 ppgtt->pd_offset = (first_pd_entry_in_global_pt)*sizeof(gtt_pte_t);
171228
172− dev_priv->mm.aliasing_ppgtt = ppgtt;
173−
174229 return 0;
175230
176231 err_pd_pin:
@@ -186,94 +241,57 @@ err_pt_alloc: · 9 unmodified lines
186241 __free_page(ppgtt->pt_pages[i]);
187242 }
188243 kfree(ppgtt->pt_pages);
189−err_ppgtt:
190− kfree(ppgtt);
191244
192245 return ret;
193246 }
194247
195−void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev)
248+static int i915_gem_init_aliasing_ppgtt(struct drm_device *dev)
196249 {
197250 struct drm_i915_private *dev_priv = dev->dev_private;
198− struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
199− int i;
251+ struct i915_hw_ppgtt *ppgtt;
252+ int ret;
200253
254+ ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
201255 if (!ppgtt)
202− return;
256+ return -ENOMEM;
203257
204− if (ppgtt->pt_dma_addr) {
205− for (i = 0; i < ppgtt->num_pd_entries; i++)
206− pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i],
207− 4096, PCI_DMA_BIDIRECTIONAL);
208− }
258+ ppgtt->dev = dev;
209259
210− kfree(ppgtt->pt_dma_addr);
211− for (i = 0; i < ppgtt->num_pd_entries; i++)
212− __free_page(ppgtt->pt_pages[i]);
213− kfree(ppgtt->pt_pages);
214− kfree(ppgtt);
260+ ret = gen6_ppgtt_init(ppgtt);
261+ if (ret)
262+ kfree(ppgtt);
263+ else
264+ dev_priv->mm.aliasing_ppgtt = ppgtt;
265+
266+ return ret;
215267 }
216268
217−static void i915_ppgtt_insert_sg_entries(struct i915_hw_ppgtt *ppgtt,
218− const struct sg_table *pages,
219− unsigned first_entry,
220− enum i915_cache_level cache_level)
269+void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev)
221270 {
222− gtt_pte_t *pt_vaddr;
223− unsigned act_pd = first_entry / I915_PPGTT_PT_ENTRIES;
224− unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
225− unsigned i, j, m, segment_len;
226− dma_addr_t page_addr;
227− struct scatterlist *sg;
228−
229− /* init sg walking */
230− sg = pages->sgl;
231− i = 0;
232− segment_len = sg_dma_len(sg) >> PAGE_SHIFT;
233− m = 0;
234−
235− while (i < pages->nents) {
236− pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pd]);
237−
238− for (j = first_pte; j < I915_PPGTT_PT_ENTRIES; j++) {
239− page_addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
240− pt_vaddr[j] = pte_encode(ppgtt->dev, page_addr,
241− cache_level);
242−
243− /* grab the next page */
244− if (++m == segment_len) {
245− if (++i == pages->nents)
246− break;
247−
248− sg = sg_next(sg);
249− segment_len = sg_dma_len(sg) >> PAGE_SHIFT;
250− m = 0;
251− }
252− }
271+ struct drm_i915_private *dev_priv = dev->dev_private;
272+ struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
253273
254− kunmap_atomic(pt_vaddr);
274+ if (!ppgtt)
275+ return;
255276
256− first_pte = 0;
257− act_pd++;
258− }
277+ ppgtt->cleanup(ppgtt);
259278 }
260279
261280 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
262281 struct drm_i915_gem_object *obj,
263282 enum i915_cache_level cache_level)
264283 {
265− i915_ppgtt_insert_sg_entries(ppgtt,
266− obj->pages,
267− obj->gtt_space->start >> PAGE_SHIFT,
268− cache_level);
284+ ppgtt->insert_entries(ppgtt, obj->pages,
285+ obj->gtt_space->start >> PAGE_SHIFT,
286+ cache_level);
269287 }
270288
271289 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
272290 struct drm_i915_gem_object *obj)
273291 {
274− i915_ppgtt_clear_range(ppgtt,
275− obj->gtt_space->start >> PAGE_SHIFT,
276− obj->base.size >> PAGE_SHIFT);
292+ ppgtt->clear_range(ppgtt,
293+ obj->gtt_space->start >> PAGE_SHIFT,
294+ obj->base.size >> PAGE_SHIFT);
277295 }
278296
279297 void i915_gem_init_ppgtt(struct drm_device *dev)
@@ -290,15 +308,11 @@ void i915_gem_init_ppgtt(struct drm_device *dev) · 10 unmodified lines
290308 return;
291309
292310
293− pd_addr = (gtt_pte_t __iomem*)dev_priv->mm.gsm + ppgtt->pd_offset/sizeof(gtt_pte_t);
311+ pd_addr = (gtt_pte_t __iomem*)dev_priv->gtt.gsm + ppgtt->pd_offset/sizeof(gtt_pte_t);
294312 for (i = 0; i < ppgtt->num_pd_entries; i++) {
295313 dma_addr_t pt_addr;
296314
297− if (dev_priv->mm.gtt->needs_dmar)
298− pt_addr = ppgtt->pt_dma_addr[i];
299− else
300− pt_addr = page_to_phys(ppgtt->pt_pages[i]);
301−
315+ pt_addr = ppgtt->pt_dma_addr[i];
302316 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
303317 pd_entry |= GEN6_PDE_VALID;
304318
@@ -338,11 +352,27 @@ void i915_gem_init_ppgtt(struct drm_device *dev) · 33 unmodified lines
338352 }
339353 }
340354
355+extern int intel_iommu_gfx_mapped;
356+/* Certain Gen5 chipsets require require idling the GPU before
357+ * unmapping anything from the GTT when VT-d is enabled.
358+ */
359+static inline bool needs_idle_maps(struct drm_device *dev)
360+{
361+#ifdef CONFIG_INTEL_IOMMU
362+ /* Query intel_iommu to see if we need the workaround. Presumably that
363+ * was loaded first.
364+ */
365+ if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
366+ return true;
367+#endif
368+ return false;
369+}
370+
341371 static bool do_idling(struct drm_i915_private *dev_priv)
342372 {
343373 bool ret = dev_priv->mm.interruptible;
344374
345− if (unlikely(dev_priv->mm.gtt->do_idle_maps)) {
375+ if (unlikely(dev_priv->gtt.do_idle_maps)) {
346376 dev_priv->mm.interruptible = false;
347377 if (i915_gpu_idle(dev_priv->dev)) {
348378 DRM_ERROR("Couldn't idle GPU\n");
@@ -356,45 +386,18 @@ static bool do_idling(struct drm_i915_private *dev_priv) · 7 unmodified lines
356386
357387 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
358388 {
359− if (unlikely(dev_priv->mm.gtt->do_idle_maps))
389+ if (unlikely(dev_priv->gtt.do_idle_maps))
360390 dev_priv->mm.interruptible = interruptible;
361391 }
362392
363−
364−static void i915_ggtt_clear_range(struct drm_device *dev,
365− unsigned first_entry,
366− unsigned num_entries)
367−{
368− struct drm_i915_private *dev_priv = dev->dev_private;
369− gtt_pte_t scratch_pte;
370− gtt_pte_t __iomem *gtt_base = (gtt_pte_t __iomem *) dev_priv->mm.gsm + first_entry;
371− const int max_entries = dev_priv->mm.gtt->gtt_total_entries - first_entry;
372− int i;
373−
374− if (INTEL_INFO(dev)->gen < 6) {
375− intel_gtt_clear_range(first_entry, num_entries);
376− return;
377− }
378−
379− if (WARN(num_entries > max_entries,
380− "First entry = %d; Num entries = %d (max=%d)\n",
381− first_entry, num_entries, max_entries))
382− num_entries = max_entries;
383−
384− scratch_pte = pte_encode(dev, dev_priv->mm.gtt->scratch_page_dma, I915_CACHE_LLC);
385− for (i = 0; i < num_entries; i++)
386− iowrite32(scratch_pte, &gtt_base[i]);
387− readl(gtt_base);
388−}
389−
390393 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
391394 {
392395 struct drm_i915_private *dev_priv = dev->dev_private;
393396 struct drm_i915_gem_object *obj;
394397
395398 /* First fill our portion of the GTT with scratch pages */
396− i915_ggtt_clear_range(dev, dev_priv->mm.gtt_start / PAGE_SIZE,
397− (dev_priv->mm.gtt_end - dev_priv->mm.gtt_start) / PAGE_SIZE);
399+ dev_priv->gtt.gtt_clear_range(dev, dev_priv->gtt.start / PAGE_SIZE,
400+ dev_priv->gtt.total / PAGE_SIZE);
398401
399402 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
400403 i915_gem_clflush_object(obj);
@@ -423,17 +426,15 @@ int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) · 22 unmodified lines
423426 * within the global GTT as well as accessible by the GPU through the GMADR
424427 * mapped BAR (dev_priv->mm.gtt->gtt).
425428 */
426−static void gen6_ggtt_bind_object(struct drm_i915_gem_object *obj,
427− enum i915_cache_level level)
429+static void gen6_ggtt_insert_entries(struct drm_device *dev,
430+ struct sg_table *st,
431+ unsigned int first_entry,
432+ enum i915_cache_level level)
428433 {
429− struct drm_device *dev = obj->base.dev;
430434 struct drm_i915_private *dev_priv = dev->dev_private;
431− struct sg_table *st = obj->pages;
432435 struct scatterlist *sg = st->sgl;
433− const int first_entry = obj->gtt_space->start >> PAGE_SHIFT;
434− const int max_entries = dev_priv->mm.gtt->gtt_total_entries - first_entry;
435436 gtt_pte_t __iomem *gtt_entries =
436− (gtt_pte_t __iomem *)dev_priv->mm.gsm + first_entry;
437+ (gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
437438 int unused, i = 0;
438439 unsigned int len, m = 0;
439440 dma_addr_t addr;
@@ -442,14 +443,12 @@ static void gen6_ggtt_bind_object(struct drm_i915_gem_object *obj, · 2 unmodified lines
442443 len = sg_dma_len(sg) >> PAGE_SHIFT;
443444 for (m = 0; m < len; m++) {
444445 addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
445− iowrite32(pte_encode(dev, addr, level), &gtt_entries[i]);
446+ iowrite32(gen6_pte_encode(dev, addr, level),
447+ &gtt_entries[i]);
446448 i++;
447449 }
448450 }
449451
450− BUG_ON(i > max_entries);
451− BUG_ON(i != obj->base.size / PAGE_SIZE);
452−
453452 /* XXX: This serves as a posting read to make sure that the PTE has
454453 * actually been updated. There is some concern that even though
455454 * registers and PTEs are within the same BAR that they are potentially
@@ -457,7 +456,8 @@ static void gen6_ggtt_bind_object(struct drm_i915_gem_object *obj, · 1 unmodified line
457456 * hardware should work, we must keep this posting read for paranoia.
458457 */
459458 if (i != 0)
460− WARN_ON(readl(&gtt_entries[i-1]) != pte_encode(dev, addr, level));
459+ WARN_ON(readl(&gtt_entries[i-1])
460+ != gen6_pte_encode(dev, addr, level));
461461
462462 /* This next bit makes the above posting read even more important. We
463463 * want to flush the TLBs only after we're certain all the PTE updates
@@ -467,28 +467,70 @@ static void gen6_ggtt_bind_object(struct drm_i915_gem_object *obj, · 3 unmodified lines
467467 POSTING_READ(GFX_FLSH_CNTL_GEN6);
468468 }
469469
470+static void gen6_ggtt_clear_range(struct drm_device *dev,
471+ unsigned int first_entry,
472+ unsigned int num_entries)
473+{
474+ struct drm_i915_private *dev_priv = dev->dev_private;
475+ gtt_pte_t scratch_pte;
476+ gtt_pte_t __iomem *gtt_base = (gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
477+ const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
478+ int i;
479+
480+ if (WARN(num_entries > max_entries,
481+ "First entry = %d; Num entries = %d (max=%d)\n",
482+ first_entry, num_entries, max_entries))
483+ num_entries = max_entries;
484+
485+ scratch_pte = gen6_pte_encode(dev, dev_priv->gtt.scratch_page_dma,
486+ I915_CACHE_LLC);
487+ for (i = 0; i < num_entries; i++)
488+ iowrite32(scratch_pte, &gtt_base[i]);
489+ readl(gtt_base);
490+}
491+
492+
493+static void i915_ggtt_insert_entries(struct drm_device *dev,
494+ struct sg_table *st,
495+ unsigned int pg_start,
496+ enum i915_cache_level cache_level)
497+{
498+ unsigned int flags = (cache_level == I915_CACHE_NONE) ?
499+ AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
500+
501+ intel_gtt_insert_sg_entries(st, pg_start, flags);
502+
503+}
504+
505+static void i915_ggtt_clear_range(struct drm_device *dev,
506+ unsigned int first_entry,
507+ unsigned int num_entries)
508+{
509+ intel_gtt_clear_range(first_entry, num_entries);
510+}
511+
512+
470513 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
471514 enum i915_cache_level cache_level)
472515 {
473516 struct drm_device *dev = obj->base.dev;
474− if (INTEL_INFO(dev)->gen < 6) {
475− unsigned int flags = (cache_level == I915_CACHE_NONE) ?
476− AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
477− intel_gtt_insert_sg_entries(obj->pages,
478− obj->gtt_space->start >> PAGE_SHIFT,
479− flags);
480− } else {
481− gen6_ggtt_bind_object(obj, cache_level);
482− }
517+ struct drm_i915_private *dev_priv = dev->dev_private;
518+
519+ dev_priv->gtt.gtt_insert_entries(dev, obj->pages,
520+ obj->gtt_space->start >> PAGE_SHIFT,
521+ cache_level);
483522
484523 obj->has_global_gtt_mapping = 1;
485524 }
486525
487526 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj)
488527 {
489− i915_ggtt_clear_range(obj->base.dev,
490− obj->gtt_space->start >> PAGE_SHIFT,
491− obj->base.size >> PAGE_SHIFT);
528+ struct drm_device *dev = obj->base.dev;
529+ struct drm_i915_private *dev_priv = dev->dev_private;
530+
531+ dev_priv->gtt.gtt_clear_range(obj->base.dev,
532+ obj->gtt_space->start >> PAGE_SHIFT,
533+ obj->base.size >> PAGE_SHIFT);
492534
493535 obj->has_global_gtt_mapping = 0;
494536 }
@@ -525,17 +567,27 @@ static void i915_gtt_color_adjust(struct drm_mm_node *node, · 30 unmodified lines
525567 *end -= 4096;
526568 }
527569 }
528−
529570 void i915_gem_setup_global_gtt(struct drm_device *dev,
530571 unsigned long start,
531572 unsigned long mappable_end,
532573 unsigned long end)
533574 {
575+ /* Let GEM Manage all of the aperture.
576+ *
577+ * However, leave one page at the end still bound to the scratch page.
578+ * There are a number of places where the hardware apparently prefetches
579+ * past the end of the object, and we've seen multiple hangs with the
580+ * GPU head pointer stuck in a batchbuffer bound at the last page of the
581+ * aperture. One page should be enough to keep any prefetching inside
582+ * of the aperture.
583+ */
534584 drm_i915_private_t *dev_priv = dev->dev_private;
535585 struct drm_mm_node *entry;
536586 struct drm_i915_gem_object *obj;
537587 unsigned long hole_start, hole_end;
538588
589+ BUG_ON(mappable_end > end);
590+
539591 /* Subtract the guard page ... */
540592 drm_mm_init(&dev_priv->mm.gtt_space, start, end - start - PAGE_SIZE);
541593 if (!HAS_LLC(dev))
@@ -554,24 +606,20 @@ void i915_gem_setup_global_gtt(struct drm_device *dev, · 12 unmodified lines
554606 obj->has_global_gtt_mapping = 1;
555607 }
556608
557− dev_priv->mm.gtt_start = start;
558− dev_priv->mm.gtt_mappable_end = mappable_end;
559− dev_priv->mm.gtt_end = end;
560− dev_priv->mm.gtt_total = end - start;
561− dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start;
609+ dev_priv->gtt.start = start;
610+ dev_priv->gtt.total = end - start;
562611
563612 /* Clear any non-preallocated blocks */
564613 drm_mm_for_each_hole(entry, &dev_priv->mm.gtt_space,
565614 hole_start, hole_end) {
566615 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
567616 hole_start, hole_end);
568− i915_ggtt_clear_range(dev,
569− hole_start / PAGE_SIZE,
570− (hole_end-hole_start) / PAGE_SIZE);
617+ dev_priv->gtt.gtt_clear_range(dev, hole_start / PAGE_SIZE,
618+ (hole_end-hole_start) / PAGE_SIZE);
571619 }
572620
573621 /* And finally clear the reserved guard page */
574− i915_ggtt_clear_range(dev, end / PAGE_SIZE - 1, 1);
622+ dev_priv->gtt.gtt_clear_range(dev, end / PAGE_SIZE - 1, 1);
575623 }
576624
577625 static bool
@@ -593,12 +641,12 @@ void i915_gem_init_global_gtt(struct drm_device *dev) · 15 unmodified lines
593641 {
594642 struct drm_i915_private *dev_priv = dev->dev_private;
595643 unsigned long gtt_size, mappable_size;
596− int ret;
597644
598− gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
599− mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
645+ gtt_size = dev_priv->gtt.total;
646+ mappable_size = dev_priv->gtt.mappable_end;
600647
601648 if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
649+ int ret;
602650 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
603651 * aperture accordingly when using aliasing ppgtt. */
604652 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
@@ -606,23 +654,14 @@ void i915_gem_init_global_gtt(struct drm_device *dev) · 1 unmodified line
606654 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
607655
608656 ret = i915_gem_init_aliasing_ppgtt(dev);
609− if (ret) {
610− mutex_unlock(&dev->struct_mutex);
657+ if (!ret)
611658 return;
612− }
613− } else {
614− /* Let GEM Manage all of the aperture.
615− *
616− * However, leave one page at the end still bound to the scratch
617− * page. There are a number of places where the hardware
618− * apparently prefetches past the end of the object, and we've
619− * seen multiple hangs with the GPU head pointer stuck in a
620− * batchbuffer bound at the last page of the aperture. One page
621− * should be enough to keep any prefetching inside of the
622− * aperture.
623− */
624− i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
659+
660+ DRM_ERROR("Aliased PPGTT setup failed %d\n", ret);
661+ drm_mm_takedown(&dev_priv->mm.gtt_space);
662+ gtt_size += I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
625663 }
664+ i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
626665 }
627666
628667 static int setup_scratch_page(struct drm_device *dev)
@@ -645,8 +684,8 @@ static int setup_scratch_page(struct drm_device *dev) · 16 unmodified lines
645684 #else
646685 dma_addr = page_to_phys(page);
647686 #endif
648− dev_priv->mm.gtt->scratch_page = page;
649− dev_priv->mm.gtt->scratch_page_dma = dma_addr;
687+ dev_priv->gtt.scratch_page = page;
688+ dev_priv->gtt.scratch_page_dma = dma_addr;
650689
651690 return 0;
652691 }
@@ -654,11 +693,11 @@ static int setup_scratch_page(struct drm_device *dev) · 1 unmodified line
654693 static void teardown_scratch_page(struct drm_device *dev)
655694 {
656695 struct drm_i915_private *dev_priv = dev->dev_private;
657− set_pages_wb(dev_priv->mm.gtt->scratch_page, 1);
658− pci_unmap_page(dev->pdev, dev_priv->mm.gtt->scratch_page_dma,
696+ set_pages_wb(dev_priv->gtt.scratch_page, 1);
697+ pci_unmap_page(dev->pdev, dev_priv->gtt.scratch_page_dma,
659698 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
660− put_page(dev_priv->mm.gtt->scratch_page);
661− __free_page(dev_priv->mm.gtt->scratch_page);
699+ put_page(dev_priv->gtt.scratch_page);
700+ __free_page(dev_priv->gtt.scratch_page);
662701 }
663702
664703 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
@@ -668,14 +707,14 @@ static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) · 3 unmodified lines
668707 return snb_gmch_ctl << 20;
669708 }
670709
671−static inline unsigned int gen6_get_stolen_size(u16 snb_gmch_ctl)
710+static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
672711 {
673712 snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
674713 snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
675714 return snb_gmch_ctl << 25; /* 32 MB units */
676715 }
677716
678−static inline unsigned int gen7_get_stolen_size(u16 snb_gmch_ctl)
717+static inline size_t gen7_get_stolen_size(u16 snb_gmch_ctl)
679718 {
680719 static const int stolen_decoder[] = {
681720 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352};
@@ -684,103 +723,122 @@ static inline unsigned int gen7_get_stolen_size(u16 snb_gmch_ctl) · 2 unmodified lines
684723 return stolen_decoder[snb_gmch_ctl] << 20;
685724 }
686725
687−int i915_gem_gtt_init(struct drm_device *dev)
726+static int gen6_gmch_probe(struct drm_device *dev,
727+ size_t *gtt_total,
728+ size_t *stolen)
688729 {
689730 struct drm_i915_private *dev_priv = dev->dev_private;
690731 phys_addr_t gtt_bus_addr;
732+ unsigned int gtt_size;
691733 u16 snb_gmch_ctl;
692734 int ret;
693735
694− /* On modern platforms we need not worry ourself with the legacy
695− * hostbridge query stuff. Skip it entirely
736+ /* 64/512MB is the current min/max we actually know of, but this is just
737+ * a coarse sanity check.
696738 */
697− if (INTEL_INFO(dev)->gen < 6) {
698− ret = intel_gmch_probe(dev_priv->bridge_dev, dev->pdev, NULL);
699− if (!ret) {
700− DRM_ERROR("failed to set up gmch\n");
701− return -EIO;
702− }
703−
704− dev_priv->mm.gtt = intel_gtt_get();
705− if (!dev_priv->mm.gtt) {
706− DRM_ERROR("Failed to initialize GTT\n");
707− intel_gmch_remove();
708− return -ENODEV;
709− }
710− return 0;
739+ if ((dev_priv->gtt.mappable_end < (64<<20) ||
740+ (dev_priv->gtt.mappable_end > (512<<20)))) {
741+ DRM_ERROR("Unknown GMADR size (%lx)\n",
742+ dev_priv->gtt.mappable_end);
743+ return -ENXIO;
711744 }
712745
713− dev_priv->mm.gtt = kzalloc(sizeof(*dev_priv->mm.gtt), GFP_KERNEL);
714− if (!dev_priv->mm.gtt)
715− return -ENOMEM;
716−
717746 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
718747 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
748+ pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
749+ gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
719750
720−#ifdef CONFIG_INTEL_IOMMU
721− dev_priv->mm.gtt->needs_dmar = 1;
722−#endif
751+ if (IS_GEN7(dev))
752+ *stolen = gen7_get_stolen_size(snb_gmch_ctl);
753+ else
754+ *stolen = gen6_get_stolen_size(snb_gmch_ctl);
755+
756+ *gtt_total = (gtt_size / sizeof(gtt_pte_t)) << PAGE_SHIFT;
723757
724758 /* For GEN6+ the PTEs for the ggtt live at 2MB + BAR0 */
725759 gtt_bus_addr = pci_resource_start(dev->pdev, 0) + (2<<20);
726− dev_priv->mm.gtt->gma_bus_addr = pci_resource_start(dev->pdev, 2);
727−
728− /* i9xx_setup */
729− pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
730− dev_priv->mm.gtt->gtt_total_entries =
731− gen6_get_total_gtt_size(snb_gmch_ctl) / sizeof(gtt_pte_t);
732− if (INTEL_INFO(dev)->gen < 7)
733− dev_priv->mm.gtt->stolen_size = gen6_get_stolen_size(snb_gmch_ctl);
734− else
735− dev_priv->mm.gtt->stolen_size = gen7_get_stolen_size(snb_gmch_ctl);
736−
737− dev_priv->mm.gtt->gtt_mappable_entries = pci_resource_len(dev->pdev, 2) >> PAGE_SHIFT;
738− /* 64/512MB is the current min/max we actually know of, but this is just a
739− * coarse sanity check.
740− */
741− if ((dev_priv->mm.gtt->gtt_mappable_entries >> 8) < 64 ||
742− dev_priv->mm.gtt->gtt_mappable_entries > dev_priv->mm.gtt->gtt_total_entries) {
743− DRM_ERROR("Unknown GMADR entries (%d)\n",
744− dev_priv->mm.gtt->gtt_mappable_entries);
745− ret = -ENXIO;
746− goto err_out;
760+ dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size);
761+ if (!dev_priv->gtt.gsm) {
762+ DRM_ERROR("Failed to map the gtt page table\n");
763+ return -ENOMEM;
747764 }
748765
749766 ret = setup_scratch_page(dev);
750− if (ret) {
767+ if (ret)
751768 DRM_ERROR("Scratch setup failed\n");
752− goto err_out;
753− }
754769
755− dev_priv->mm.gsm = ioremap_wc(gtt_bus_addr,
756− dev_priv->mm.gtt->gtt_total_entries * sizeof(gtt_pte_t));
757− if (!dev_priv->mm.gsm) {
758− DRM_ERROR("Failed to map the gtt page table\n");
759− teardown_scratch_page(dev);
760− ret = -ENOMEM;
761− goto err_out;
770+ dev_priv->gtt.gtt_clear_range = gen6_ggtt_clear_range;
771+ dev_priv->gtt.gtt_insert_entries = gen6_ggtt_insert_entries;
772+
773+ return ret;
774+}
775+
776+static void gen6_gmch_remove(struct drm_device *dev)
777+{
778+ struct drm_i915_private *dev_priv = dev->dev_private;
779+ iounmap(dev_priv->gtt.gsm);
780+ teardown_scratch_page(dev_priv->dev);
781+}
782+
783+static int i915_gmch_probe(struct drm_device *dev,
784+ size_t *gtt_total,
785+ size_t *stolen)
786+{
787+ struct drm_i915_private *dev_priv = dev->dev_private;
788+ int ret;
789+
790+ ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
791+ if (!ret) {
792+ DRM_ERROR("failed to set up gmch\n");
793+ return -EIO;
762794 }
763795
764− /* GMADR is the PCI aperture used by SW to access tiled GFX surfaces in a linear fashion. */
765− DRM_INFO("Memory usable by graphics device = %dM\n", dev_priv->mm.gtt->gtt_total_entries >> 8);
766− DRM_DEBUG_DRIVER("GMADR size = %dM\n", dev_priv->mm.gtt->gtt_mappable_entries >> 8);
767− DRM_DEBUG_DRIVER("GTT stolen size = %dM\n", dev_priv->mm.gtt->stolen_size >> 20);
796+ intel_gtt_get(gtt_total, stolen);
797+
798+ dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
799+ dev_priv->gtt.gtt_clear_range = i915_ggtt_clear_range;
800+ dev_priv->gtt.gtt_insert_entries = i915_ggtt_insert_entries;
768801
769802 return 0;
803+}
770804
771−err_out:
772− kfree(dev_priv->mm.gtt);
773− if (INTEL_INFO(dev)->gen < 6)
774− intel_gmch_remove();
775− return ret;
805+static void i915_gmch_remove(struct drm_device *dev)
806+{
807+ intel_gmch_remove();
776808 }
777809
778−void i915_gem_gtt_fini(struct drm_device *dev)
810+int i915_gem_gtt_init(struct drm_device *dev)
779811 {
780812 struct drm_i915_private *dev_priv = dev->dev_private;
781− iounmap(dev_priv->mm.gsm);
782− teardown_scratch_page(dev);
783− if (INTEL_INFO(dev)->gen < 6)
784− intel_gmch_remove();
785− kfree(dev_priv->mm.gtt);
813+ struct i915_gtt *gtt = &dev_priv->gtt;
814+ unsigned long gtt_size;
815+ int ret;
816+
817+ gtt->mappable_base = pci_resource_start(dev->pdev, 2);
818+ gtt->mappable_end = pci_resource_len(dev->pdev, 2);
819+
820+ if (INTEL_INFO(dev)->gen <= 5) {
821+ dev_priv->gtt.gtt_probe = i915_gmch_probe;
822+ dev_priv->gtt.gtt_remove = i915_gmch_remove;
823+ } else {
824+ dev_priv->gtt.gtt_probe = gen6_gmch_probe;
825+ dev_priv->gtt.gtt_remove = gen6_gmch_remove;
826+ }
827+
828+ ret = dev_priv->gtt.gtt_probe(dev, &dev_priv->gtt.total,
829+ &dev_priv->gtt.stolen_size);
830+ if (ret)
831+ return ret;
832+
833+ gtt_size = (dev_priv->gtt.total >> PAGE_SHIFT) * sizeof(gtt_pte_t);
834+
835+ /* GMADR is the PCI mmio aperture into the global GTT. */
836+ DRM_INFO("Memory usable by graphics device = %zdM\n",
837+ dev_priv->gtt.total >> 20);
838+ DRM_DEBUG_DRIVER("GMADR size = %ldM\n",
839+ dev_priv->gtt.mappable_end >> 20);
840+ DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n",
841+ dev_priv->gtt.stolen_size >> 20);
842+
843+ return 0;
786844 }
drivers/gpu/drm/i915/i915_gem_stolen.c+4−4
@@ -187,11 +187,11 @@ int i915_gem_init_stolen(struct drm_device *dev) · 186 unmodified lines
187187 if (dev_priv->mm.stolen_base == 0)
188188 return 0;
189189
190− DRM_DEBUG_KMS("found %d bytes of stolen memory at %08lx\n",
191− dev_priv->mm.gtt->stolen_size, dev_priv->mm.stolen_base);
190+ DRM_DEBUG_KMS("found %zd bytes of stolen memory at %08lx\n",
191+ dev_priv->gtt.stolen_size, dev_priv->mm.stolen_base);
192192
193193 /* Basic memrange allocator for stolen space */
194− drm_mm_init(&dev_priv->mm.stolen, 0, dev_priv->mm.gtt->stolen_size);
194+ drm_mm_init(&dev_priv->mm.stolen, 0, dev_priv->gtt.stolen_size);
195195
196196 return 0;
197197 }
@@ -205,7 +205,7 @@ i915_pages_create_for_stolen(struct drm_device *dev, · 7 unmodified lines
205205 struct scatterlist *sg;
206206
207207 DRM_DEBUG_DRIVER("offset=0x%x, size=%d\n", offset, size);
208− BUG_ON(offset > dev_priv->mm.gtt->stolen_size - size);
208+ BUG_ON(offset > dev_priv->gtt.stolen_size - size);
209209
210210 /* We hide that we have no struct page backing our stolen object
211211 * by wrapping the contiguous physical allocation with a fake
drivers/gpu/drm/i915/i915_gem_tiling.c+5−16
@@ -272,18 +272,7 @@ i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode) · 271 unmodified lines
272272 return false;
273273 }
274274
275− /*
276− * Previous chips need to be aligned to the size of the smallest
277− * fence register that can contain the object.
278− */
279− if (INTEL_INFO(obj->base.dev)->gen == 3)
280− size = 1024*1024;
281− else
282− size = 512*1024;
283−
284− while (size < obj->base.size)
285− size <<= 1;
286−
275+ size = i915_gem_get_gtt_size(obj->base.dev, obj->base.size, tiling_mode);
287276 if (obj->gtt_space->size != size)
288277 return false;
289278
@@ -368,15 +357,15 @@ i915_gem_set_tiling(struct drm_device *dev, void *data, · 78 unmodified lines
368357
369358 obj->map_and_fenceable =
370359 obj->gtt_space == NULL ||
371− (obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end &&
360+ (obj->gtt_offset + obj->base.size <= dev_priv->gtt.mappable_end &&
372361 i915_gem_object_fence_ok(obj, args->tiling_mode));
373362
374363 /* Rebind if we need a change of alignment */
375364 if (!obj->map_and_fenceable) {
376365 u32 unfenced_alignment =
377− i915_gem_get_unfenced_gtt_alignment(dev,
378− obj->base.size,
379− args->tiling_mode);
366+ i915_gem_get_gtt_alignment(dev, obj->base.size,
367+ args->tiling_mode,
368+ false);
380369 if (obj->gtt_offset & (unfenced_alignment - 1))
381370 ret = i915_gem_object_unbind(obj);
382371 }
drivers/gpu/drm/i915/i915_irq.c+88−42
@@ -356,8 +356,8 @@ static void notify_ring(struct drm_device *dev, · 355 unmodified lines
356356
357357 wake_up_all(&ring->irq_queue);
358358 if (i915_enable_hangcheck) {
359− dev_priv->hangcheck_count = 0;
360− mod_timer(&dev_priv->hangcheck_timer,
359+ dev_priv->gpu_error.hangcheck_count = 0;
360+ mod_timer(&dev_priv->gpu_error.hangcheck_timer,
361361 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
362362 }
363363 }
@@ -862,23 +862,60 @@ done: · 498 unmodified lines
862862 */
863863 static void i915_error_work_func(struct work_struct *work)
864864 {
865− drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
866− error_work);
865+ struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
866+ work);
867+ drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
868+ gpu_error);
867869 struct drm_device *dev = dev_priv->dev;
870+ struct intel_ring_buffer *ring;
868871 char *error_event[] = { "ERROR=1", NULL };
869872 char *reset_event[] = { "RESET=1", NULL };
870873 char *reset_done_event[] = { "ERROR=0", NULL };
874+ int i, ret;
871875
872876 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
873877
874− if (atomic_read(&dev_priv->mm.wedged)) {
878+ /*
879+ * Note that there's only one work item which does gpu resets, so we
880+ * need not worry about concurrent gpu resets potentially incrementing
881+ * error->reset_counter twice. We only need to take care of another
882+ * racing irq/hangcheck declaring the gpu dead for a second time. A
883+ * quick check for that is good enough: schedule_work ensures the
884+ * correct ordering between hang detection and this work item, and since
885+ * the reset in-progress bit is only ever set by code outside of this
886+ * work we don't need to worry about any other races.
887+ */
888+ if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
875889 DRM_DEBUG_DRIVER("resetting chip\n");
876− kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
877− if (!i915_reset(dev)) {
878− atomic_set(&dev_priv->mm.wedged, 0);
879− kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
890+ kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
891+ reset_event);
892+
893+ ret = i915_reset(dev);
894+
895+ if (ret == 0) {
896+ /*
897+ * After all the gem state is reset, increment the reset
898+ * counter and wake up everyone waiting for the reset to
899+ * complete.
900+ *
901+ * Since unlock operations are a one-sided barrier only,
902+ * we need to insert a barrier here to order any seqno
903+ * updates before
904+ * the counter increment.
905+ */
906+ smp_mb__before_atomic_inc();
907+ atomic_inc(&dev_priv->gpu_error.reset_counter);
908+
909+ kobject_uevent_env(&dev->primary->kdev.kobj,
910+ KOBJ_CHANGE, reset_done_event);
911+ } else {
912+ atomic_set(&error->reset_counter, I915_WEDGED);
880913 }
881− complete_all(&dev_priv->error_completion);
914+
915+ for_each_ring(ring, dev_priv, i)
916+ wake_up_all(&ring->irq_queue);
917+
918+ wake_up_all(&dev_priv->gpu_error.reset_queue);
882919 }
883920 }
884921
@@ -939,7 +976,7 @@ i915_error_object_create(struct drm_i915_private *dev_priv, · 54 unmodified lines
939976 goto unwind;
940977
941978 local_irq_save(flags);
942− if (reloc_offset < dev_priv->mm.gtt_mappable_end &&
979+ if (reloc_offset < dev_priv->gtt.mappable_end &&
943980 src->has_global_gtt_mapping) {
944981 void __iomem *s;
945982
@@ -948,7 +985,7 @@ i915_error_object_create(struct drm_i915_private *dev_priv, · 2 unmodified lines
948985 * captures what the GPU read.
949986 */
950987
951− s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
988+ s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
952989 reloc_offset);
953990 memcpy_fromio(d, s, PAGE_SIZE);
954991 io_mapping_unmap_atomic(s);
@@ -1255,9 +1292,9 @@ static void i915_capture_error_state(struct drm_device *dev) · 300 unmodified lines
12551292 unsigned long flags;
12561293 int i, pipe;
12571294
1258− spin_lock_irqsave(&dev_priv->error_lock, flags);
1259− error = dev_priv->first_error;
1260− spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1295+ spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1296+ error = dev_priv->gpu_error.first_error;
1297+ spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
12611298 if (error)
12621299 return;
12631300
@@ -1268,7 +1305,8 @@ static void i915_capture_error_state(struct drm_device *dev) · 4 unmodified lines
12681305 return;
12691306 }
12701307
1271− DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
1308+ DRM_INFO("capturing error event; look for more information in"
1309+ "/sys/kernel/debug/dri/%d/i915_error_state\n",
12721310 dev->primary->index);
12731311
12741312 kref_init(&error->ref);
@@ -1341,12 +1379,12 @@ static void i915_capture_error_state(struct drm_device *dev) · 66 unmodified lines
13411379 error->overlay = intel_overlay_capture_error_state(dev);
13421380 error->display = intel_display_capture_error_state(dev);
13431381
1344− spin_lock_irqsave(&dev_priv->error_lock, flags);
1345− if (dev_priv->first_error == NULL) {
1346− dev_priv->first_error = error;
1382+ spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1383+ if (dev_priv->gpu_error.first_error == NULL) {
1384+ dev_priv->gpu_error.first_error = error;
13471385 error = NULL;
13481386 }
1349− spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1387+ spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
13501388
13511389 if (error)
13521390 i915_error_state_free(&error->ref);
@@ -1358,10 +1396,10 @@ void i915_destroy_error_state(struct drm_device *dev) · 5 unmodified lines
13581396 struct drm_i915_error_state *error;
13591397 unsigned long flags;
13601398
1361− spin_lock_irqsave(&dev_priv->error_lock, flags);
1362− error = dev_priv->first_error;
1363− dev_priv->first_error = NULL;
1364− spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1399+ spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1400+ error = dev_priv->gpu_error.first_error;
1401+ dev_priv->gpu_error.first_error = NULL;
1402+ spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
13651403
13661404 if (error)
13671405 kref_put(&error->ref, i915_error_state_free);
@@ -1482,17 +1520,18 @@ void i915_handle_error(struct drm_device *dev, bool wedged) · 114 unmodified lines
14821520 i915_report_and_clear_eir(dev);
14831521
14841522 if (wedged) {
1485− INIT_COMPLETION(dev_priv->error_completion);
1486− atomic_set(&dev_priv->mm.wedged, 1);
1523+ atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
1524+ &dev_priv->gpu_error.reset_counter);
14871525
14881526 /*
1489− * Wakeup waiting processes so they don't hang
1527+ * Wakeup waiting processes so that the reset work item
1528+ * doesn't deadlock trying to grab various locks.
14901529 */
14911530 for_each_ring(ring, dev_priv, i)
14921531 wake_up_all(&ring->irq_queue);
14931532 }
14941533
1495− queue_work(dev_priv->wq, &dev_priv->error_work);
1534+ queue_work(dev_priv->wq, &dev_priv->gpu_error.work);
14961535 }
14971536
14981537 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
@@ -1723,7 +1762,7 @@ static bool i915_hangcheck_hung(struct drm_device *dev) · 224 unmodified lines
17231762 {
17241763 drm_i915_private_t *dev_priv = dev->dev_private;
17251764
1726− if (dev_priv->hangcheck_count++ > 1) {
1765+ if (dev_priv->gpu_error.hangcheck_count++ > 1) {
17271766 bool hung = true;
17281767
17291768 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
@@ -1782,25 +1821,29 @@ void i915_hangcheck_elapsed(unsigned long data) · 52 unmodified lines
17821821 goto repeat;
17831822 }
17841823
1785− dev_priv->hangcheck_count = 0;
1824+ dev_priv->gpu_error.hangcheck_count = 0;
17861825 return;
17871826 }
17881827
17891828 i915_get_extra_instdone(dev, instdone);
1790− if (memcmp(dev_priv->last_acthd, acthd, sizeof(acthd)) == 0 &&
1791− memcmp(dev_priv->prev_instdone, instdone, sizeof(instdone)) == 0) {
1829+ if (memcmp(dev_priv->gpu_error.last_acthd, acthd,
1830+ sizeof(acthd)) == 0 &&
1831+ memcmp(dev_priv->gpu_error.prev_instdone, instdone,
1832+ sizeof(instdone)) == 0) {
17921833 if (i915_hangcheck_hung(dev))
17931834 return;
17941835 } else {
1795− dev_priv->hangcheck_count = 0;
1836+ dev_priv->gpu_error.hangcheck_count = 0;
17961837
1797− memcpy(dev_priv->last_acthd, acthd, sizeof(acthd));
1798− memcpy(dev_priv->prev_instdone, instdone, sizeof(instdone));
1838+ memcpy(dev_priv->gpu_error.last_acthd, acthd,
1839+ sizeof(acthd));
1840+ memcpy(dev_priv->gpu_error.prev_instdone, instdone,
1841+ sizeof(instdone));
17991842 }
18001843
18011844 repeat:
18021845 /* Reset timer case chip hangs without another request being added */
1803− mod_timer(&dev_priv->hangcheck_timer,
1846+ mod_timer(&dev_priv->gpu_error.hangcheck_timer,
18041847 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
18051848 }
18061849
@@ -1892,6 +1935,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev) · 85 unmodified lines
18921935 DE_AUX_CHANNEL_A;
18931936 u32 render_irqs;
18941937 u32 hotplug_mask;
1938+ u32 pch_irq_mask;
18951939
18961940 dev_priv->irq_mask = ~display_mask;
18971941
@@ -1935,10 +1979,10 @@ static int ironlake_irq_postinstall(struct drm_device *dev) · 37 unmodified lines
19351979 SDE_AUX_MASK);
19361980 }
19371981
1938− dev_priv->pch_irq_mask = ~hotplug_mask;
1982+ pch_irq_mask = ~hotplug_mask;
19391983
19401984 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1941− I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1985+ I915_WRITE(SDEIMR, pch_irq_mask);
19421986 I915_WRITE(SDEIER, hotplug_mask);
19431987 POSTING_READ(SDEIER);
19441988
@@ -1966,6 +2010,7 @@ static int ivybridge_irq_postinstall(struct drm_device *dev) · 21 unmodified lines
19662010 DE_AUX_CHANNEL_A_IVB;
19672011 u32 render_irqs;
19682012 u32 hotplug_mask;
2013+ u32 pch_irq_mask;
19692014
19702015 dev_priv->irq_mask = ~display_mask;
19712016
@@ -1995,10 +2040,10 @@ static int ivybridge_irq_postinstall(struct drm_device *dev) · 23 unmodified lines
19952040 SDE_PORTD_HOTPLUG_CPT |
19962041 SDE_GMBUS_CPT |
19972042 SDE_AUX_MASK_CPT);
1998− dev_priv->pch_irq_mask = ~hotplug_mask;
2043+ pch_irq_mask = ~hotplug_mask;
19992044
20002045 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2001− I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
2046+ I915_WRITE(SDEIMR, pch_irq_mask);
20022047 I915_WRITE(SDEIER, hotplug_mask);
20032048 POSTING_READ(SDEIER);
20042049
@@ -2767,11 +2812,12 @@ void intel_irq_init(struct drm_device *dev) · 762 unmodified lines
27672812 struct drm_i915_private *dev_priv = dev->dev_private;
27682813
27692814 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
2770− INIT_WORK(&dev_priv->error_work, i915_error_work_func);
2815+ INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
27712816 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
27722817 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
27732818
2774− setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
2819+ setup_timer(&dev_priv->gpu_error.hangcheck_timer,
2820+ i915_hangcheck_elapsed,
27752821 (unsigned long) dev);
27762822
27772823 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
drivers/gpu/drm/i915/i915_reg.h+150−136
@@ -141,9 +141,15 @@ · 140 unmodified lines
141141 #define VGA_MSR_MEM_EN (1<<1)
142142 #define VGA_MSR_CGA_MODE (1<<0)
143143
144−#define VGA_SR_INDEX 0x3c4
144+/*
145+ * SR01 is the only VGA register touched on non-UMS setups.
146+ * VLV doesn't do UMS, so the sequencer index/data registers
147+ * are the only VGA registers which need to include
148+ * display_mmio_offset.
149+ */
150+#define VGA_SR_INDEX (dev_priv->info->display_mmio_offset + 0x3c4)
145151 #define SR01 1
146−#define VGA_SR_DATA 0x3c5
152+#define VGA_SR_DATA (dev_priv->info->display_mmio_offset + 0x3c5)
147153
148154 #define VGA_AR_INDEX 0x3c0
149155 #define VGA_AR_VID_EN (1<<5)
@@ -336,17 +342,19 @@ · 186 unmodified lines
336342 * 0x801c/3c: core clock bits
337343 * 0x8048/68: low pass filter coefficients
338344 * 0x8100: fast clock controls
345+ *
346+ * DPIO is VLV only.
339347 */
340−#define DPIO_PKT 0x2100
348+#define DPIO_PKT (VLV_DISPLAY_BASE + 0x2100)
341349 #define DPIO_RID (0<<24)
342350 #define DPIO_OP_WRITE (1<<16)
343351 #define DPIO_OP_READ (0<<16)
344352 #define DPIO_PORTID (0x12<<8)
345353 #define DPIO_BYTE (0xf<<4)
346354 #define DPIO_BUSY (1<<0) /* status only */
347−#define DPIO_DATA 0x2104
348−#define DPIO_REG 0x2108
349−#define DPIO_CTL 0x2110
355+#define DPIO_DATA (VLV_DISPLAY_BASE + 0x2104)
356+#define DPIO_REG (VLV_DISPLAY_BASE + 0x2108)
357+#define DPIO_CTL (VLV_DISPLAY_BASE + 0x2110)
350358 #define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */
351359 #define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */
352360 #define DPIO_SFR_BYPASS (1<<1)
@@ -554,13 +562,13 @@ · 201 unmodified lines
554562 #define IIR 0x020a4
555563 #define IMR 0x020a8
556564 #define ISR 0x020ac
557−#define VLV_GUNIT_CLOCK_GATE 0x182060
565+#define VLV_GUNIT_CLOCK_GATE (VLV_DISPLAY_BASE + 0x2060)
558566 #define GCFG_DIS (1<<8)
559−#define VLV_IIR_RW 0x182084
560−#define VLV_IER 0x1820a0
561−#define VLV_IIR 0x1820a4
562−#define VLV_IMR 0x1820a8
563−#define VLV_ISR 0x1820ac
567+#define VLV_IIR_RW (VLV_DISPLAY_BASE + 0x2084)
568+#define VLV_IER (VLV_DISPLAY_BASE + 0x20a0)
569+#define VLV_IIR (VLV_DISPLAY_BASE + 0x20a4)
570+#define VLV_IMR (VLV_DISPLAY_BASE + 0x20a8)
571+#define VLV_ISR (VLV_DISPLAY_BASE + 0x20ac)
564572 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
565573 #define I915_DISPLAY_PORT_INTERRUPT (1<<17)
566574 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
@@ -733,6 +741,7 @@ · 166 unmodified lines
733741 #define GEN7_FF_TS_SCHED_HS0 (0x3<<16)
734742 #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16)
735743 #define GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */
744+#define GEN7_FF_VS_REF_CNT_FFME (1 << 15)
736745 #define GEN7_FF_VS_SCHED_HS1 (0x5<<12)
737746 #define GEN7_FF_VS_SCHED_HS0 (0x3<<12)
738747 #define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */
@@ -919,8 +928,8 @@ · 180 unmodified lines
919928 #define VGA1_PD_P1_DIV_2 (1 << 13)
920929 #define VGA1_PD_P1_SHIFT 8
921930 #define VGA1_PD_P1_MASK (0x1f << 8)
922−#define _DPLL_A 0x06014
923−#define _DPLL_B 0x06018
931+#define _DPLL_A (dev_priv->info->display_mmio_offset + 0x6014)
932+#define _DPLL_B (dev_priv->info->display_mmio_offset + 0x6018)
924933 #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
925934 #define DPLL_VCO_ENABLE (1 << 31)
926935 #define DPLL_DVO_HIGH_SPEED (1 << 30)
@@ -979,7 +988,7 @@ · 52 unmodified lines
979988 #define SDVO_MULTIPLIER_MASK 0x000000ff
980989 #define SDVO_MULTIPLIER_SHIFT_HIRES 4
981990 #define SDVO_MULTIPLIER_SHIFT_VGA 0
982−#define _DPLL_A_MD 0x0601c /* 965+ only */
991+#define _DPLL_A_MD (dev_priv->info->display_mmio_offset + 0x601c) /* 965+ only */
983992 /*
984993 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
985994 *
@@ -1016,7 +1025,7 @@ · 30 unmodified lines
10161025 */
10171026 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
10181027 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
1019−#define _DPLL_B_MD 0x06020 /* 965+ only */
1028+#define _DPLL_B_MD (dev_priv->info->display_mmio_offset + 0x6020) /* 965+ only */
10201029 #define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD)
10211030
10221031 #define _FPA0 0x06040
@@ -1159,15 +1168,15 @@ · 136 unmodified lines
11591168 #define RAMCLK_GATE_D 0x6210 /* CRL only */
11601169 #define DEUC 0x6214 /* CRL only */
11611170
1162−#define FW_BLC_SELF_VLV 0x6500
1171+#define FW_BLC_SELF_VLV (VLV_DISPLAY_BASE + 0x6500)
11631172 #define FW_CSPWRDWNEN (1<<15)
11641173
11651174 /*
11661175 * Palette regs
11671176 */
11681177
1169−#define _PALETTE_A 0x0a000
1170−#define _PALETTE_B 0x0a800
1178+#define _PALETTE_A (dev_priv->info->display_mmio_offset + 0xa000)
1179+#define _PALETTE_B (dev_priv->info->display_mmio_offset + 0xa800)
11711180 #define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B)
11721181
11731182 /* MCH MMIO space */
@@ -1532,26 +1541,26 @@ · 358 unmodified lines
15321541 */
15331542
15341543 /* Pipe A timing regs */
1535−#define _HTOTAL_A 0x60000
1536−#define _HBLANK_A 0x60004
1537−#define _HSYNC_A 0x60008
1538−#define _VTOTAL_A 0x6000c
1539−#define _VBLANK_A 0x60010
1540−#define _VSYNC_A 0x60014
1541−#define _PIPEASRC 0x6001c
1542−#define _BCLRPAT_A 0x60020
1543−#define _VSYNCSHIFT_A 0x60028
1544+#define _HTOTAL_A (dev_priv->info->display_mmio_offset + 0x60000)
1545+#define _HBLANK_A (dev_priv->info->display_mmio_offset + 0x60004)
1546+#define _HSYNC_A (dev_priv->info->display_mmio_offset + 0x60008)
1547+#define _VTOTAL_A (dev_priv->info->display_mmio_offset + 0x6000c)
1548+#define _VBLANK_A (dev_priv->info->display_mmio_offset + 0x60010)
1549+#define _VSYNC_A (dev_priv->info->display_mmio_offset + 0x60014)
1550+#define _PIPEASRC (dev_priv->info->display_mmio_offset + 0x6001c)
1551+#define _BCLRPAT_A (dev_priv->info->display_mmio_offset + 0x60020)
1552+#define _VSYNCSHIFT_A (dev_priv->info->display_mmio_offset + 0x60028)
15441553
15451554 /* Pipe B timing regs */
1546−#define _HTOTAL_B 0x61000
1547−#define _HBLANK_B 0x61004
1548−#define _HSYNC_B 0x61008
1549−#define _VTOTAL_B 0x6100c
1550−#define _VBLANK_B 0x61010
1551−#define _VSYNC_B 0x61014
1552−#define _PIPEBSRC 0x6101c
1553−#define _BCLRPAT_B 0x61020
1554−#define _VSYNCSHIFT_B 0x61028
1555+#define _HTOTAL_B (dev_priv->info->display_mmio_offset + 0x61000)
1556+#define _HBLANK_B (dev_priv->info->display_mmio_offset + 0x61004)
1557+#define _HSYNC_B (dev_priv->info->display_mmio_offset + 0x61008)
1558+#define _VTOTAL_B (dev_priv->info->display_mmio_offset + 0x6100c)
1559+#define _VBLANK_B (dev_priv->info->display_mmio_offset + 0x61010)
1560+#define _VSYNC_B (dev_priv->info->display_mmio_offset + 0x61014)
1561+#define _PIPEBSRC (dev_priv->info->display_mmio_offset + 0x6101c)
1562+#define _BCLRPAT_B (dev_priv->info->display_mmio_offset + 0x61020)
1563+#define _VSYNCSHIFT_B (dev_priv->info->display_mmio_offset + 0x61028)
15551564
15561565
15571566 #define HTOTAL(trans) _TRANSCODER(trans, _HTOTAL_A, _HTOTAL_B)
@@ -1612,7 +1621,7 @@ · 54 unmodified lines
16121621
16131622
16141623 /* Hotplug control (945+ only) */
1615−#define PORT_HOTPLUG_EN 0x61110
1624+#define PORT_HOTPLUG_EN (dev_priv->info->display_mmio_offset + 0x61110)
16161625 #define HDMIB_HOTPLUG_INT_EN (1 << 29)
16171626 #define DPB_HOTPLUG_INT_EN (1 << 29)
16181627 #define HDMIC_HOTPLUG_INT_EN (1 << 28)
@@ -1639,7 +1648,7 @@ · 20 unmodified lines
16391648 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
16401649 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
16411650
1642−#define PORT_HOTPLUG_STAT 0x61114
1651+#define PORT_HOTPLUG_STAT (dev_priv->info->display_mmio_offset + 0x61114)
16431652 /* HDMI/DP bits are gen4+ */
16441653 #define DPB_HOTPLUG_LIVE_STATUS (1 << 29)
16451654 #define DPC_HOTPLUG_LIVE_STATUS (1 << 28)
@@ -1858,7 +1867,7 @@ · 212 unmodified lines
18581867 #define PP_DIVISOR 0x61210
18591868
18601869 /* Panel fitting */
1861−#define PFIT_CONTROL 0x61230
1870+#define PFIT_CONTROL (dev_priv->info->display_mmio_offset + 0x61230)
18621871 #define PFIT_ENABLE (1 << 31)
18631872 #define PFIT_PIPE_MASK (3 << 29)
18641873 #define PFIT_PIPE_SHIFT 29
@@ -1876,7 +1885,7 @@ · 11 unmodified lines
18761885 #define PFIT_SCALING_PROGRAMMED (1 << 26)
18771886 #define PFIT_SCALING_PILLAR (2 << 26)
18781887 #define PFIT_SCALING_LETTER (3 << 26)
1879−#define PFIT_PGM_RATIOS 0x61234
1888+#define PFIT_PGM_RATIOS (dev_priv->info->display_mmio_offset + 0x61234)
18801889 /* Pre-965 */
18811890 #define PFIT_VERT_SCALE_SHIFT 20
18821891 #define PFIT_VERT_SCALE_MASK 0xfff00000
@@ -1888,7 +1897,7 @@ · 5 unmodified lines
18881897 #define PFIT_HORIZ_SCALE_SHIFT_965 0
18891898 #define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
18901899
1891−#define PFIT_AUTO_RATIOS 0x61238
1900+#define PFIT_AUTO_RATIOS (dev_priv->info->display_mmio_offset + 0x61238)
18921901
18931902 /* Backlight control */
18941903 #define BLC_PWM_CTL2 0x61250 /* 965+ only */
@@ -2618,10 +2627,10 @@ · 723 unmodified lines
26182627 /* Display & cursor control */
26192628
26202629 /* Pipe A */
2621−#define _PIPEADSL 0x70000
2630+#define _PIPEADSL (dev_priv->info->display_mmio_offset + 0x70000)
26222631 #define DSL_LINEMASK_GEN2 0x00000fff
26232632 #define DSL_LINEMASK_GEN3 0x00001fff
2624−#define _PIPEACONF 0x70008
2633+#define _PIPEACONF (dev_priv->info->display_mmio_offset + 0x70008)
26252634 #define PIPECONF_ENABLE (1<<31)
26262635 #define PIPECONF_DISABLE 0
26272636 #define PIPECONF_DOUBLE_WIDE (1<<30)
@@ -2650,6 +2659,7 @@ · 22 unmodified lines
26502659 #define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */
26512660 #define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */
26522661 #define PIPECONF_CXSR_DOWNCLOCK (1<<16)
2662+#define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
26532663 #define PIPECONF_BPC_MASK (0x7 << 5)
26542664 #define PIPECONF_8BPC (0<<5)
26552665 #define PIPECONF_10BPC (1<<5)
@@ -2661,7 +2671,7 @@ · 5 unmodified lines
26612671 #define PIPECONF_DITHER_TYPE_ST1 (1<<2)
26622672 #define PIPECONF_DITHER_TYPE_ST2 (2<<2)
26632673 #define PIPECONF_DITHER_TYPE_TEMP (3<<2)
2664−#define _PIPEASTAT 0x70024
2674+#define _PIPEASTAT (dev_priv->info->display_mmio_offset + 0x70024)
26652675 #define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
26662676 #define SPRITE1_FLIPDONE_INT_EN_VLV (1UL<<30)
26672677 #define PIPE_CRC_ERROR_ENABLE (1UL<<29)
@@ -2672,7 +2682,7 @@ · 4 unmodified lines
26722682 #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
26732683 #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
26742684 #define PIPE_DPST_EVENT_ENABLE (1UL<<23)
2675−#define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<26)
2685+#define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<22)
26762686 #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
26772687 #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
26782688 #define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
@@ -2682,7 +2692,7 @@ · 3 unmodified lines
26822692 #define PIPEA_HBLANK_INT_EN_VLV (1UL<<16)
26832693 #define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
26842694 #define SPRITE1_FLIPDONE_INT_STATUS_VLV (1UL<<15)
2685−#define SPRITE0_FLIPDONE_INT_STATUS_VLV (1UL<<15)
2695+#define SPRITE0_FLIPDONE_INT_STATUS_VLV (1UL<<14)
26862696 #define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
26872697 #define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
26882698 #define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
@@ -2706,7 +2716,7 @@ · 17 unmodified lines
27062716 #define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
27072717 #define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)
27082718
2709−#define VLV_DPFLIPSTAT 0x70028
2719+#define VLV_DPFLIPSTAT (VLV_DISPLAY_BASE + 0x70028)
27102720 #define PIPEB_LINE_COMPARE_INT_EN (1<<29)
27112721 #define PIPEB_HLINE_INT_EN (1<<28)
27122722 #define PIPEB_VBLANK_INT_EN (1<<27)
@@ -2720,7 +2730,7 @@ · 7 unmodified lines
27202730 #define SPRITEA_FLIPDONE_INT_EN (1<<17)
27212731 #define PLANEA_FLIPDONE_INT_EN (1<<16)
27222732
2723−#define DPINVGTT 0x7002c /* VLV only */
2733+#define DPINVGTT (VLV_DISPLAY_BASE + 0x7002c) /* VLV only */
27242734 #define CURSORB_INVALID_GTT_INT_EN (1<<23)
27252735 #define CURSORA_INVALID_GTT_INT_EN (1<<22)
27262736 #define SPRITED_INVALID_GTT_INT_EN (1<<21)
@@ -2748,7 +2758,7 @@ · 21 unmodified lines
27482758 #define DSPARB_BEND_SHIFT 9 /* on 855 */
27492759 #define DSPARB_AEND_SHIFT 0
27502760
2751−#define DSPFW1 0x70034
2761+#define DSPFW1 (dev_priv->info->display_mmio_offset + 0x70034)
27522762 #define DSPFW_SR_SHIFT 23
27532763 #define DSPFW_SR_MASK (0x1ff<<23)
27542764 #define DSPFW_CURSORB_SHIFT 16
@@ -2756,11 +2766,11 @@ · 1 unmodified line
27562766 #define DSPFW_PLANEB_SHIFT 8
27572767 #define DSPFW_PLANEB_MASK (0x7f<<8)
27582768 #define DSPFW_PLANEA_MASK (0x7f)
2759−#define DSPFW2 0x70038
2769+#define DSPFW2 (dev_priv->info->display_mmio_offset + 0x70038)
27602770 #define DSPFW_CURSORA_MASK 0x00003f00
27612771 #define DSPFW_CURSORA_SHIFT 8
27622772 #define DSPFW_PLANEC_MASK (0x7f)
2763−#define DSPFW3 0x7003c
2773+#define DSPFW3 (dev_priv->info->display_mmio_offset + 0x7003c)
27642774 #define DSPFW_HPLL_SR_EN (1<<31)
27652775 #define DSPFW_CURSOR_SR_SHIFT 24
27662776 #define PINEVIEW_SELF_REFRESH_EN (1<<30)
@@ -2772,13 +2782,13 @@ · 5 unmodified lines
27722782 /* drain latency register values*/
27732783 #define DRAIN_LATENCY_PRECISION_32 32
27742784 #define DRAIN_LATENCY_PRECISION_16 16
2775−#define VLV_DDL1 0x70050
2785+#define VLV_DDL1 (VLV_DISPLAY_BASE + 0x70050)
27762786 #define DDL_CURSORA_PRECISION_32 (1<<31)
27772787 #define DDL_CURSORA_PRECISION_16 (0<<31)
27782788 #define DDL_CURSORA_SHIFT 24
27792789 #define DDL_PLANEA_PRECISION_32 (1<<7)
27802790 #define DDL_PLANEA_PRECISION_16 (0<<7)
2781−#define VLV_DDL2 0x70054
2791+#define VLV_DDL2 (VLV_DISPLAY_BASE + 0x70054)
27822792 #define DDL_CURSORB_PRECISION_32 (1<<31)
27832793 #define DDL_CURSORB_PRECISION_16 (0<<31)
27842794 #define DDL_CURSORB_SHIFT 24
@@ -2922,10 +2932,10 @@ · 137 unmodified lines
29222932 * } while (high1 != high2);
29232933 * frame = (high1 << 8) | low1;
29242934 */
2925−#define _PIPEAFRAMEHIGH 0x70040
2935+#define _PIPEAFRAMEHIGH (dev_priv->info->display_mmio_offset + 0x70040)
29262936 #define PIPE_FRAME_HIGH_MASK 0x0000ffff
29272937 #define PIPE_FRAME_HIGH_SHIFT 0
2928−#define _PIPEAFRAMEPIXEL 0x70044
2938+#define _PIPEAFRAMEPIXEL (dev_priv->info->display_mmio_offset + 0x70044)
29292939 #define PIPE_FRAME_LOW_MASK 0xff000000
29302940 #define PIPE_FRAME_LOW_SHIFT 24
29312941 #define PIPE_PIXEL_MASK 0x00ffffff
@@ -2936,7 +2946,7 @@ · 4 unmodified lines
29362946 #define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45)
29372947
29382948 /* Cursor A & B regs */
2939−#define _CURACNTR 0x70080
2949+#define _CURACNTR (dev_priv->info->display_mmio_offset + 0x70080)
29402950 /* Old style CUR*CNTR flags (desktop 8xx) */
29412951 #define CURSOR_ENABLE 0x80000000
29422952 #define CURSOR_GAMMA_ENABLE 0x40000000
@@ -2957,16 +2967,16 @@ · 14 unmodified lines
29572967 #define MCURSOR_PIPE_A 0x00
29582968 #define MCURSOR_PIPE_B (1 << 28)
29592969 #define MCURSOR_GAMMA_ENABLE (1 << 26)
2960−#define _CURABASE 0x70084
2961−#define _CURAPOS 0x70088
2970+#define _CURABASE (dev_priv->info->display_mmio_offset + 0x70084)
2971+#define _CURAPOS (dev_priv->info->display_mmio_offset + 0x70088)
29622972 #define CURSOR_POS_MASK 0x007FF
29632973 #define CURSOR_POS_SIGN 0x8000
29642974 #define CURSOR_X_SHIFT 0
29652975 #define CURSOR_Y_SHIFT 16
29662976 #define CURSIZE 0x700a0
2967−#define _CURBCNTR 0x700c0
2968−#define _CURBBASE 0x700c4
2969−#define _CURBPOS 0x700c8
2977+#define _CURBCNTR (dev_priv->info->display_mmio_offset + 0x700c0)
2978+#define _CURBBASE (dev_priv->info->display_mmio_offset + 0x700c4)
2979+#define _CURBPOS (dev_priv->info->display_mmio_offset + 0x700c8)
29702980
29712981 #define _CURBCNTR_IVB 0x71080
29722982 #define _CURBBASE_IVB 0x71084
@@ -2981,7 +2991,7 @@ · 8 unmodified lines
29812991 #define CURPOS_IVB(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS_IVB)
29822992
29832993 /* Display A control */
2984−#define _DSPACNTR 0x70180
2994+#define _DSPACNTR (dev_priv->info->display_mmio_offset + 0x70180)
29852995 #define DISPLAY_PLANE_ENABLE (1<<31)
29862996 #define DISPLAY_PLANE_DISABLE 0
29872997 #define DISPPLANE_GAMMA_ENABLE (1<<30)
@@ -3014,14 +3024,14 @@ · 26 unmodified lines
30143024 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
30153025 #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
30163026 #define DISPPLANE_TILED (1<<10)
3017−#define _DSPAADDR 0x70184
3018−#define _DSPASTRIDE 0x70188
3019−#define _DSPAPOS 0x7018C /* reserved */
3020−#define _DSPASIZE 0x70190
3021−#define _DSPASURF 0x7019C /* 965+ only */
3022−#define _DSPATILEOFF 0x701A4 /* 965+ only */
3023−#define _DSPAOFFSET 0x701A4 /* HSW */
3024−#define _DSPASURFLIVE 0x701AC
3027+#define _DSPAADDR (dev_priv->info->display_mmio_offset + 0x70184)
3028+#define _DSPASTRIDE (dev_priv->info->display_mmio_offset + 0x70188)
3029+#define _DSPAPOS (dev_priv->info->display_mmio_offset + 0x7018C) /* reserved */
3030+#define _DSPASIZE (dev_priv->info->display_mmio_offset + 0x70190)
3031+#define _DSPASURF (dev_priv->info->display_mmio_offset + 0x7019C) /* 965+ only */
3032+#define _DSPATILEOFF (dev_priv->info->display_mmio_offset + 0x701A4) /* 965+ only */
3033+#define _DSPAOFFSET (dev_priv->info->display_mmio_offset + 0x701A4) /* HSW */
3034+#define _DSPASURFLIVE (dev_priv->info->display_mmio_offset + 0x701AC)
30253035
30263036 #define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR)
30273037 #define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR)
@@ -3042,44 +3052,44 @@ · 14 unmodified lines
30423052 (I915_WRITE((reg), (gfx_addr) | I915_LO_DISPBASE(I915_READ(reg))))
30433053
30443054 /* VBIOS flags */
3045−#define SWF00 0x71410
3046−#define SWF01 0x71414
3047−#define SWF02 0x71418
3048−#define SWF03 0x7141c
3049−#define SWF04 0x71420
3050−#define SWF05 0x71424
3051−#define SWF06 0x71428
3052−#define SWF10 0x70410
3053−#define SWF11 0x70414
3054−#define SWF14 0x71420
3055−#define SWF30 0x72414
3056−#define SWF31 0x72418
3057−#define SWF32 0x7241c
3055+#define SWF00 (dev_priv->info->display_mmio_offset + 0x71410)
3056+#define SWF01 (dev_priv->info->display_mmio_offset + 0x71414)
3057+#define SWF02 (dev_priv->info->display_mmio_offset + 0x71418)
3058+#define SWF03 (dev_priv->info->display_mmio_offset + 0x7141c)
3059+#define SWF04 (dev_priv->info->display_mmio_offset + 0x71420)
3060+#define SWF05 (dev_priv->info->display_mmio_offset + 0x71424)
3061+#define SWF06 (dev_priv->info->display_mmio_offset + 0x71428)
3062+#define SWF10 (dev_priv->info->display_mmio_offset + 0x70410)
3063+#define SWF11 (dev_priv->info->display_mmio_offset + 0x70414)
3064+#define SWF14 (dev_priv->info->display_mmio_offset + 0x71420)
3065+#define SWF30 (dev_priv->info->display_mmio_offset + 0x72414)
3066+#define SWF31 (dev_priv->info->display_mmio_offset + 0x72418)
3067+#define SWF32 (dev_priv->info->display_mmio_offset + 0x7241c)
30583068
30593069 /* Pipe B */
3060−#define _PIPEBDSL 0x71000
3061−#define _PIPEBCONF 0x71008
3062−#define _PIPEBSTAT 0x71024
3063−#define _PIPEBFRAMEHIGH 0x71040
3064−#define _PIPEBFRAMEPIXEL 0x71044
3070+#define _PIPEBDSL (dev_priv->info->display_mmio_offset + 0x71000)
3071+#define _PIPEBCONF (dev_priv->info->display_mmio_offset + 0x71008)
3072+#define _PIPEBSTAT (dev_priv->info->display_mmio_offset + 0x71024)
3073+#define _PIPEBFRAMEHIGH (dev_priv->info->display_mmio_offset + 0x71040)
3074+#define _PIPEBFRAMEPIXEL (dev_priv->info->display_mmio_offset + 0x71044)
30653075 #define _PIPEB_FRMCOUNT_GM45 0x71040
30663076 #define _PIPEB_FLIPCOUNT_GM45 0x71044
30673077
30683078
30693079 /* Display B control */
3070−#define _DSPBCNTR 0x71180
3080+#define _DSPBCNTR (dev_priv->info->display_mmio_offset + 0x71180)
30713081 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
30723082 #define DISPPLANE_ALPHA_TRANS_DISABLE 0
30733083 #define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
30743084 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
3075−#define _DSPBADDR 0x71184
3076−#define _DSPBSTRIDE 0x71188
3077−#define _DSPBPOS 0x7118C
3078−#define _DSPBSIZE 0x71190
3079−#define _DSPBSURF 0x7119C
3080−#define _DSPBTILEOFF 0x711A4
3081−#define _DSPBOFFSET 0x711A4
3082−#define _DSPBSURFLIVE 0x711AC
3085+#define _DSPBADDR (dev_priv->info->display_mmio_offset + 0x71184)
3086+#define _DSPBSTRIDE (dev_priv->info->display_mmio_offset + 0x71188)
3087+#define _DSPBPOS (dev_priv->info->display_mmio_offset + 0x7118C)
3088+#define _DSPBSIZE (dev_priv->info->display_mmio_offset + 0x71190)
3089+#define _DSPBSURF (dev_priv->info->display_mmio_offset + 0x7119C)
3090+#define _DSPBTILEOFF (dev_priv->info->display_mmio_offset + 0x711A4)
3091+#define _DSPBOFFSET (dev_priv->info->display_mmio_offset + 0x711A4)
3092+#define _DSPBSURFLIVE (dev_priv->info->display_mmio_offset + 0x711AC)
30833093
30843094 /* Sprite A control */
30853095 #define _DVSACNTR 0x72180
@@ -3228,6 +3238,8 @@ · 142 unmodified lines
32283238 # define VGA_2X_MODE (1 << 30)
32293239 # define VGA_PIPE_B_SELECT (1 << 29)
32303240
3241+#define VLV_VGACNTRL (VLV_DISPLAY_BASE + 0x71400)
3242+
32313243 /* Ironlake */
32323244
32333245 #define CPU_VGACNTRL 0x41000
@@ -3268,41 +3280,41 @@ · 34 unmodified lines
32683280 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
32693281
32703282
3271−#define _PIPEA_DATA_M1 0x60030
3283+#define _PIPEA_DATA_M1 (dev_priv->info->display_mmio_offset + 0x60030)
32723284 #define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
32733285 #define TU_SIZE_MASK 0x7e000000
32743286 #define PIPE_DATA_M1_OFFSET 0
3275−#define _PIPEA_DATA_N1 0x60034
3287+#define _PIPEA_DATA_N1 (dev_priv->info->display_mmio_offset + 0x60034)
32763288 #define PIPE_DATA_N1_OFFSET 0
32773289
3278−#define _PIPEA_DATA_M2 0x60038
3290+#define _PIPEA_DATA_M2 (dev_priv->info->display_mmio_offset + 0x60038)
32793291 #define PIPE_DATA_M2_OFFSET 0
3280−#define _PIPEA_DATA_N2 0x6003c
3292+#define _PIPEA_DATA_N2 (dev_priv->info->display_mmio_offset + 0x6003c)
32813293 #define PIPE_DATA_N2_OFFSET 0
32823294
3283−#define _PIPEA_LINK_M1 0x60040
3295+#define _PIPEA_LINK_M1 (dev_priv->info->display_mmio_offset + 0x60040)
32843296 #define PIPE_LINK_M1_OFFSET 0
3285−#define _PIPEA_LINK_N1 0x60044
3297+#define _PIPEA_LINK_N1 (dev_priv->info->display_mmio_offset + 0x60044)
32863298 #define PIPE_LINK_N1_OFFSET 0
32873299
3288−#define _PIPEA_LINK_M2 0x60048
3300+#define _PIPEA_LINK_M2 (dev_priv->info->display_mmio_offset + 0x60048)
32893301 #define PIPE_LINK_M2_OFFSET 0
3290−#define _PIPEA_LINK_N2 0x6004c
3302+#define _PIPEA_LINK_N2 (dev_priv->info->display_mmio_offset + 0x6004c)
32913303 #define PIPE_LINK_N2_OFFSET 0
32923304
32933305 /* PIPEB timing regs are same start from 0x61000 */
32943306
3295−#define _PIPEB_DATA_M1 0x61030
3296−#define _PIPEB_DATA_N1 0x61034
3307+#define _PIPEB_DATA_M1 (dev_priv->info->display_mmio_offset + 0x61030)
3308+#define _PIPEB_DATA_N1 (dev_priv->info->display_mmio_offset + 0x61034)
32973309
3298−#define _PIPEB_DATA_M2 0x61038
3299−#define _PIPEB_DATA_N2 0x6103c
3310+#define _PIPEB_DATA_M2 (dev_priv->info->display_mmio_offset + 0x61038)
3311+#define _PIPEB_DATA_N2 (dev_priv->info->display_mmio_offset + 0x6103c)
33003312
3301−#define _PIPEB_LINK_M1 0x61040
3302−#define _PIPEB_LINK_N1 0x61044
3313+#define _PIPEB_LINK_M1 (dev_priv->info->display_mmio_offset + 0x61040)
3314+#define _PIPEB_LINK_N1 (dev_priv->info->display_mmio_offset + 0x61044)
33033315
3304−#define _PIPEB_LINK_M2 0x61048
3305−#define _PIPEB_LINK_N2 0x6104c
3316+#define _PIPEB_LINK_M2 (dev_priv->info->display_mmio_offset + 0x61048)
3317+#define _PIPEB_LINK_N2 (dev_priv->info->display_mmio_offset + 0x6104c)
33063318
33073319 #define PIPE_DATA_M1(tran) _TRANSCODER(tran, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
33083320 #define PIPE_DATA_N1(tran) _TRANSCODER(tran, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
@@ -3699,13 +3711,13 @@ · 390 unmodified lines
36993711 #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
37003712 #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
37013713
3702−#define VLV_VIDEO_DIP_CTL_A 0x60200
3703−#define VLV_VIDEO_DIP_DATA_A 0x60208
3704−#define VLV_VIDEO_DIP_GDCP_PAYLOAD_A 0x60210
3714+#define VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200)
3715+#define VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208)
3716+#define VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210)
37053717
3706−#define VLV_VIDEO_DIP_CTL_B 0x61170
3707−#define VLV_VIDEO_DIP_DATA_B 0x61174
3708−#define VLV_VIDEO_DIP_GDCP_PAYLOAD_B 0x61178
3718+#define VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170)
3719+#define VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174)
3720+#define VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178)
37093721
37103722 #define VLV_TVIDEO_DIP_CTL(pipe) \
37113723 _PIPE(pipe, VLV_VIDEO_DIP_CTL_A, VLV_VIDEO_DIP_CTL_B)
@@ -3995,17 +4007,17 @@ · 283 unmodified lines
39954007 #define LVDS_DETECTED (1 << 1)
39964008
39974009 /* vlv has 2 sets of panel control regs. */
3998−#define PIPEA_PP_STATUS 0x61200
3999−#define PIPEA_PP_CONTROL 0x61204
4000−#define PIPEA_PP_ON_DELAYS 0x61208
4001−#define PIPEA_PP_OFF_DELAYS 0x6120c
4002−#define PIPEA_PP_DIVISOR 0x61210
4003−
4004−#define PIPEB_PP_STATUS 0x61300
4005−#define PIPEB_PP_CONTROL 0x61304
4006−#define PIPEB_PP_ON_DELAYS 0x61308
4007−#define PIPEB_PP_OFF_DELAYS 0x6130c
4008−#define PIPEB_PP_DIVISOR 0x61310
4010+#define PIPEA_PP_STATUS (VLV_DISPLAY_BASE + 0x61200)
4011+#define PIPEA_PP_CONTROL (VLV_DISPLAY_BASE + 0x61204)
4012+#define PIPEA_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61208)
4013+#define PIPEA_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6120c)
4014+#define PIPEA_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61210)
4015+
4016+#define PIPEB_PP_STATUS (VLV_DISPLAY_BASE + 0x61300)
4017+#define PIPEB_PP_CONTROL (VLV_DISPLAY_BASE + 0x61304)
4018+#define PIPEB_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61308)
4019+#define PIPEB_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6130c)
4020+#define PIPEB_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61310)
40094021
40104022 #define PCH_PP_STATUS 0xc7200
40114023 #define PCH_PP_CONTROL 0xc7204
@@ -4186,7 +4198,9 @@ · 174 unmodified lines
41864198 #define GEN6_RP_INTERRUPT_LIMITS 0xA014
41874199 #define GEN6_RPSTAT1 0xA01C
41884200 #define GEN6_CAGF_SHIFT 8
4201+#define HSW_CAGF_SHIFT 7
41894202 #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
4203+#define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT)
41904204 #define GEN6_RP_CONTROL 0xA024
41914205 #define GEN6_RP_MEDIA_TURBO (1<<11)
41924206 #define GEN6_RP_MEDIA_MODE_MASK (3<<9)
@@ -4297,7 +4311,7 @@ · 104 unmodified lines
42974311 #define GEN7_ROW_CHICKEN2_GT2 0xf4f4
42984312 #define DOP_CLOCK_GATING_DISABLE (1<<0)
42994313
4300−#define G4X_AUD_VID_DID 0x62020
4314+#define G4X_AUD_VID_DID (dev_priv->info->display_mmio_offset + 0x62020)
43014315 #define INTEL_AUDIO_DEVCL 0x808629FB
43024316 #define INTEL_AUDIO_DEVBLC 0x80862801
43034317 #define INTEL_AUDIO_DEVCTG 0x80862802
@@ -4413,10 +4427,10 @@ · 109 unmodified lines
44134427 #define AUDIO_CP_READY_C (1<<9)
44144428
44154429 /* HSW Power Wells */
4416−#define HSW_PWR_WELL_CTL1 0x45400 /* BIOS */
4417−#define HSW_PWR_WELL_CTL2 0x45404 /* Driver */
4418−#define HSW_PWR_WELL_CTL3 0x45408 /* KVMR */
4419−#define HSW_PWR_WELL_CTL4 0x4540C /* Debug */
4430+#define HSW_PWR_WELL_BIOS 0x45400 /* CTL1 */
4431+#define HSW_PWR_WELL_DRIVER 0x45404 /* CTL2 */
4432+#define HSW_PWR_WELL_KVMR 0x45408 /* CTL3 */
4433+#define HSW_PWR_WELL_DEBUG 0x4540C /* CTL4 */
44204434 #define HSW_PWR_WELL_ENABLE (1<<31)
44214435 #define HSW_PWR_WELL_STATE (1<<30)
44224436 #define HSW_PWR_WELL_CTL5 0x45410
drivers/gpu/drm/i915/i915_suspend.c+29−511
@@ -29,67 +29,6 @@ · 28 unmodified lines
2929 #include "intel_drv.h"
3030 #include "i915_reg.h"
3131
32−static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
33−{
34− struct drm_i915_private *dev_priv = dev->dev_private;
35− u32 dpll_reg;
36−
37− /* On IVB, 3rd pipe shares PLL with another one */
38− if (pipe > 1)
39− return false;
40−
41− if (HAS_PCH_SPLIT(dev))
42− dpll_reg = _PCH_DPLL(pipe);
43− else
44− dpll_reg = (pipe == PIPE_A) ? _DPLL_A : _DPLL_B;
45−
46− return (I915_READ(dpll_reg) & DPLL_VCO_ENABLE);
47−}
48−
49−static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
50−{
51− struct drm_i915_private *dev_priv = dev->dev_private;
52− unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B);
53− u32 *array;
54− int i;
55−
56− if (!i915_pipe_enabled(dev, pipe))
57− return;
58−
59− if (HAS_PCH_SPLIT(dev))
60− reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B;
61−
62− if (pipe == PIPE_A)
63− array = dev_priv->regfile.save_palette_a;
64− else
65− array = dev_priv->regfile.save_palette_b;
66−
67− for (i = 0; i < 256; i++)
68− array[i] = I915_READ(reg + (i << 2));
69−}
70−
71−static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
72−{
73− struct drm_i915_private *dev_priv = dev->dev_private;
74− unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B);
75− u32 *array;
76− int i;
77−
78− if (!i915_pipe_enabled(dev, pipe))
79− return;
80−
81− if (HAS_PCH_SPLIT(dev))
82− reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B;
83−
84− if (pipe == PIPE_A)
85− array = dev_priv->regfile.save_palette_a;
86− else
87− array = dev_priv->regfile.save_palette_b;
88−
89− for (i = 0; i < 256; i++)
90− I915_WRITE(reg + (i << 2), array[i]);
91−}
92−
9332 static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg)
9433 {
9534 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -130,6 +69,12 @@ static void i915_save_vga(struct drm_device *dev) · 34 unmodified lines
13069 int i;
13170 u16 cr_index, cr_data, st01;
13271
72+ /* VGA state */
73+ dev_priv->regfile.saveVGA0 = I915_READ(VGA0);
74+ dev_priv->regfile.saveVGA1 = I915_READ(VGA1);
75+ dev_priv->regfile.saveVGA_PD = I915_READ(VGA_PD);
76+ dev_priv->regfile.saveVGACNTRL = I915_READ(i915_vgacntrl_reg(dev));
77+
13378 /* VGA color palette registers */
13479 dev_priv->regfile.saveDACMASK = I915_READ8(VGA_DACMASK);
13580
@@ -188,6 +133,15 @@ static void i915_restore_vga(struct drm_device *dev) · 52 unmodified lines
188133 int i;
189134 u16 cr_index, cr_data, st01;
190135
136+ /* VGA state */
137+ I915_WRITE(i915_vgacntrl_reg(dev), dev_priv->regfile.saveVGACNTRL);
138+
139+ I915_WRITE(VGA0, dev_priv->regfile.saveVGA0);
140+ I915_WRITE(VGA1, dev_priv->regfile.saveVGA1);
141+ I915_WRITE(VGA_PD, dev_priv->regfile.saveVGA_PD);
142+ POSTING_READ(VGA_PD);
143+ udelay(150);
144+
191145 /* MSR bits */
192146 I915_WRITE8(VGA_MSR_WRITE, dev_priv->regfile.saveMSR);
193147 if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) {
@@ -235,396 +189,18 @@ static void i915_restore_vga(struct drm_device *dev) · 41 unmodified lines
235189 I915_WRITE8(VGA_DACMASK, dev_priv->regfile.saveDACMASK);
236190 }
237191
238−static void i915_save_modeset_reg(struct drm_device *dev)
239−{
240− struct drm_i915_private *dev_priv = dev->dev_private;
241− int i;
242−
243− if (drm_core_check_feature(dev, DRIVER_MODESET))
244− return;
245−
246− /* Cursor state */
247− dev_priv->regfile.saveCURACNTR = I915_READ(_CURACNTR);
248− dev_priv->regfile.saveCURAPOS = I915_READ(_CURAPOS);
249− dev_priv->regfile.saveCURABASE = I915_READ(_CURABASE);
250− dev_priv->regfile.saveCURBCNTR = I915_READ(_CURBCNTR);
251− dev_priv->regfile.saveCURBPOS = I915_READ(_CURBPOS);
252− dev_priv->regfile.saveCURBBASE = I915_READ(_CURBBASE);
253− if (IS_GEN2(dev))
254− dev_priv->regfile.saveCURSIZE = I915_READ(CURSIZE);
255−
256− if (HAS_PCH_SPLIT(dev)) {
257− dev_priv->regfile.savePCH_DREF_CONTROL = I915_READ(PCH_DREF_CONTROL);
258− dev_priv->regfile.saveDISP_ARB_CTL = I915_READ(DISP_ARB_CTL);
259− }
260−
261− /* Pipe & plane A info */
262− dev_priv->regfile.savePIPEACONF = I915_READ(_PIPEACONF);
263− dev_priv->regfile.savePIPEASRC = I915_READ(_PIPEASRC);
264− if (HAS_PCH_SPLIT(dev)) {
265− dev_priv->regfile.saveFPA0 = I915_READ(_PCH_FPA0);
266− dev_priv->regfile.saveFPA1 = I915_READ(_PCH_FPA1);
267− dev_priv->regfile.saveDPLL_A = I915_READ(_PCH_DPLL_A);
268− } else {
269− dev_priv->regfile.saveFPA0 = I915_READ(_FPA0);
270− dev_priv->regfile.saveFPA1 = I915_READ(_FPA1);
271− dev_priv->regfile.saveDPLL_A = I915_READ(_DPLL_A);
272− }
273− if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
274− dev_priv->regfile.saveDPLL_A_MD = I915_READ(_DPLL_A_MD);
275− dev_priv->regfile.saveHTOTAL_A = I915_READ(_HTOTAL_A);
276− dev_priv->regfile.saveHBLANK_A = I915_READ(_HBLANK_A);
277− dev_priv->regfile.saveHSYNC_A = I915_READ(_HSYNC_A);
278− dev_priv->regfile.saveVTOTAL_A = I915_READ(_VTOTAL_A);
279− dev_priv->regfile.saveVBLANK_A = I915_READ(_VBLANK_A);
280− dev_priv->regfile.saveVSYNC_A = I915_READ(_VSYNC_A);
281− if (!HAS_PCH_SPLIT(dev))
282− dev_priv->regfile.saveBCLRPAT_A = I915_READ(_BCLRPAT_A);
283−
284− if (HAS_PCH_SPLIT(dev)) {
285− dev_priv->regfile.savePIPEA_DATA_M1 = I915_READ(_PIPEA_DATA_M1);
286− dev_priv->regfile.savePIPEA_DATA_N1 = I915_READ(_PIPEA_DATA_N1);
287− dev_priv->regfile.savePIPEA_LINK_M1 = I915_READ(_PIPEA_LINK_M1);
288− dev_priv->regfile.savePIPEA_LINK_N1 = I915_READ(_PIPEA_LINK_N1);
289−
290− dev_priv->regfile.saveFDI_TXA_CTL = I915_READ(_FDI_TXA_CTL);
291− dev_priv->regfile.saveFDI_RXA_CTL = I915_READ(_FDI_RXA_CTL);
292−
293− dev_priv->regfile.savePFA_CTL_1 = I915_READ(_PFA_CTL_1);
294− dev_priv->regfile.savePFA_WIN_SZ = I915_READ(_PFA_WIN_SZ);
295− dev_priv->regfile.savePFA_WIN_POS = I915_READ(_PFA_WIN_POS);
296−
297− dev_priv->regfile.saveTRANSACONF = I915_READ(_TRANSACONF);
298− dev_priv->regfile.saveTRANS_HTOTAL_A = I915_READ(_TRANS_HTOTAL_A);
299− dev_priv->regfile.saveTRANS_HBLANK_A = I915_READ(_TRANS_HBLANK_A);
300− dev_priv->regfile.saveTRANS_HSYNC_A = I915_READ(_TRANS_HSYNC_A);
301− dev_priv->regfile.saveTRANS_VTOTAL_A = I915_READ(_TRANS_VTOTAL_A);
302− dev_priv->regfile.saveTRANS_VBLANK_A = I915_READ(_TRANS_VBLANK_A);
303− dev_priv->regfile.saveTRANS_VSYNC_A = I915_READ(_TRANS_VSYNC_A);
304− }
305−
306− dev_priv->regfile.saveDSPACNTR = I915_READ(_DSPACNTR);
307− dev_priv->regfile.saveDSPASTRIDE = I915_READ(_DSPASTRIDE);
308− dev_priv->regfile.saveDSPASIZE = I915_READ(_DSPASIZE);
309− dev_priv->regfile.saveDSPAPOS = I915_READ(_DSPAPOS);
310− dev_priv->regfile.saveDSPAADDR = I915_READ(_DSPAADDR);
311− if (INTEL_INFO(dev)->gen >= 4) {
312− dev_priv->regfile.saveDSPASURF = I915_READ(_DSPASURF);
313− dev_priv->regfile.saveDSPATILEOFF = I915_READ(_DSPATILEOFF);
314− }
315− i915_save_palette(dev, PIPE_A);
316− dev_priv->regfile.savePIPEASTAT = I915_READ(_PIPEASTAT);
317−
318− /* Pipe & plane B info */
319− dev_priv->regfile.savePIPEBCONF = I915_READ(_PIPEBCONF);
320− dev_priv->regfile.savePIPEBSRC = I915_READ(_PIPEBSRC);
321− if (HAS_PCH_SPLIT(dev)) {
322− dev_priv->regfile.saveFPB0 = I915_READ(_PCH_FPB0);
323− dev_priv->regfile.saveFPB1 = I915_READ(_PCH_FPB1);
324− dev_priv->regfile.saveDPLL_B = I915_READ(_PCH_DPLL_B);
325− } else {
326− dev_priv->regfile.saveFPB0 = I915_READ(_FPB0);
327− dev_priv->regfile.saveFPB1 = I915_READ(_FPB1);
328− dev_priv->regfile.saveDPLL_B = I915_READ(_DPLL_B);
329− }
330− if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
331− dev_priv->regfile.saveDPLL_B_MD = I915_READ(_DPLL_B_MD);
332− dev_priv->regfile.saveHTOTAL_B = I915_READ(_HTOTAL_B);
333− dev_priv->regfile.saveHBLANK_B = I915_READ(_HBLANK_B);
334− dev_priv->regfile.saveHSYNC_B = I915_READ(_HSYNC_B);
335− dev_priv->regfile.saveVTOTAL_B = I915_READ(_VTOTAL_B);
336− dev_priv->regfile.saveVBLANK_B = I915_READ(_VBLANK_B);
337− dev_priv->regfile.saveVSYNC_B = I915_READ(_VSYNC_B);
338− if (!HAS_PCH_SPLIT(dev))
339− dev_priv->regfile.saveBCLRPAT_B = I915_READ(_BCLRPAT_B);
340−
341− if (HAS_PCH_SPLIT(dev)) {
342− dev_priv->regfile.savePIPEB_DATA_M1 = I915_READ(_PIPEB_DATA_M1);
343− dev_priv->regfile.savePIPEB_DATA_N1 = I915_READ(_PIPEB_DATA_N1);
344− dev_priv->regfile.savePIPEB_LINK_M1 = I915_READ(_PIPEB_LINK_M1);
345− dev_priv->regfile.savePIPEB_LINK_N1 = I915_READ(_PIPEB_LINK_N1);
346−
347− dev_priv->regfile.saveFDI_TXB_CTL = I915_READ(_FDI_TXB_CTL);
348− dev_priv->regfile.saveFDI_RXB_CTL = I915_READ(_FDI_RXB_CTL);
349−
350− dev_priv->regfile.savePFB_CTL_1 = I915_READ(_PFB_CTL_1);
351− dev_priv->regfile.savePFB_WIN_SZ = I915_READ(_PFB_WIN_SZ);
352− dev_priv->regfile.savePFB_WIN_POS = I915_READ(_PFB_WIN_POS);
353−
354− dev_priv->regfile.saveTRANSBCONF = I915_READ(_TRANSBCONF);
355− dev_priv->regfile.saveTRANS_HTOTAL_B = I915_READ(_TRANS_HTOTAL_B);
356− dev_priv->regfile.saveTRANS_HBLANK_B = I915_READ(_TRANS_HBLANK_B);
357− dev_priv->regfile.saveTRANS_HSYNC_B = I915_READ(_TRANS_HSYNC_B);
358− dev_priv->regfile.saveTRANS_VTOTAL_B = I915_READ(_TRANS_VTOTAL_B);
359− dev_priv->regfile.saveTRANS_VBLANK_B = I915_READ(_TRANS_VBLANK_B);
360− dev_priv->regfile.saveTRANS_VSYNC_B = I915_READ(_TRANS_VSYNC_B);
361− }
362−
363− dev_priv->regfile.saveDSPBCNTR = I915_READ(_DSPBCNTR);
364− dev_priv->regfile.saveDSPBSTRIDE = I915_READ(_DSPBSTRIDE);
365− dev_priv->regfile.saveDSPBSIZE = I915_READ(_DSPBSIZE);
366− dev_priv->regfile.saveDSPBPOS = I915_READ(_DSPBPOS);
367− dev_priv->regfile.saveDSPBADDR = I915_READ(_DSPBADDR);
368− if (INTEL_INFO(dev)->gen >= 4) {
369− dev_priv->regfile.saveDSPBSURF = I915_READ(_DSPBSURF);
370− dev_priv->regfile.saveDSPBTILEOFF = I915_READ(_DSPBTILEOFF);
371− }
372− i915_save_palette(dev, PIPE_B);
373− dev_priv->regfile.savePIPEBSTAT = I915_READ(_PIPEBSTAT);
374−
375− /* Fences */
376− switch (INTEL_INFO(dev)->gen) {
377− case 7:
378− case 6:
379− for (i = 0; i < 16; i++)
380− dev_priv->regfile.saveFENCE[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
381− break;
382− case 5:
383− case 4:
384− for (i = 0; i < 16; i++)
385− dev_priv->regfile.saveFENCE[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
386− break;
387− case 3:
388− if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
389− for (i = 0; i < 8; i++)
390− dev_priv->regfile.saveFENCE[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
391− case 2:
392− for (i = 0; i < 8; i++)
393− dev_priv->regfile.saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
394− break;
395− }
396−
397− /* CRT state */
398− if (HAS_PCH_SPLIT(dev))
399− dev_priv->regfile.saveADPA = I915_READ(PCH_ADPA);
400− else
401− dev_priv->regfile.saveADPA = I915_READ(ADPA);
402−
403− return;
404−}
405−
406−static void i915_restore_modeset_reg(struct drm_device *dev)
407−{
408− struct drm_i915_private *dev_priv = dev->dev_private;
409− int dpll_a_reg, fpa0_reg, fpa1_reg;
410− int dpll_b_reg, fpb0_reg, fpb1_reg;
411− int i;
412−
413− if (drm_core_check_feature(dev, DRIVER_MODESET))
414− return;
415−
416− /* Fences */
417− switch (INTEL_INFO(dev)->gen) {
418− case 7:
419− case 6:
420− for (i = 0; i < 16; i++)
421− I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), dev_priv->regfile.saveFENCE[i]);
422− break;
423− case 5:
424− case 4:
425− for (i = 0; i < 16; i++)
426− I915_WRITE64(FENCE_REG_965_0 + (i * 8), dev_priv->regfile.saveFENCE[i]);
427− break;
428− case 3:
429− case 2:
430− if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
431− for (i = 0; i < 8; i++)
432− I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->regfile.saveFENCE[i+8]);
433− for (i = 0; i < 8; i++)
434− I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->regfile.saveFENCE[i]);
435− break;
436− }
437−
438−
439− if (HAS_PCH_SPLIT(dev)) {
440− dpll_a_reg = _PCH_DPLL_A;
441− dpll_b_reg = _PCH_DPLL_B;
442− fpa0_reg = _PCH_FPA0;
443− fpb0_reg = _PCH_FPB0;
444− fpa1_reg = _PCH_FPA1;
445− fpb1_reg = _PCH_FPB1;
446− } else {
447− dpll_a_reg = _DPLL_A;
448− dpll_b_reg = _DPLL_B;
449− fpa0_reg = _FPA0;
450− fpb0_reg = _FPB0;
451− fpa1_reg = _FPA1;
452− fpb1_reg = _FPB1;
453− }
454−
455− if (HAS_PCH_SPLIT(dev)) {
456− I915_WRITE(PCH_DREF_CONTROL, dev_priv->regfile.savePCH_DREF_CONTROL);
457− I915_WRITE(DISP_ARB_CTL, dev_priv->regfile.saveDISP_ARB_CTL);
458− }
459−
460− /* Pipe & plane A info */
461− /* Prime the clock */
462− if (dev_priv->regfile.saveDPLL_A & DPLL_VCO_ENABLE) {
463− I915_WRITE(dpll_a_reg, dev_priv->regfile.saveDPLL_A &
464− ~DPLL_VCO_ENABLE);
465− POSTING_READ(dpll_a_reg);
466− udelay(150);
467− }
468− I915_WRITE(fpa0_reg, dev_priv->regfile.saveFPA0);
469− I915_WRITE(fpa1_reg, dev_priv->regfile.saveFPA1);
470− /* Actually enable it */
471− I915_WRITE(dpll_a_reg, dev_priv->regfile.saveDPLL_A);
472− POSTING_READ(dpll_a_reg);
473− udelay(150);
474− if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
475− I915_WRITE(_DPLL_A_MD, dev_priv->regfile.saveDPLL_A_MD);
476− POSTING_READ(_DPLL_A_MD);
477− }
478− udelay(150);
479−
480− /* Restore mode */
481− I915_WRITE(_HTOTAL_A, dev_priv->regfile.saveHTOTAL_A);
482− I915_WRITE(_HBLANK_A, dev_priv->regfile.saveHBLANK_A);
483− I915_WRITE(_HSYNC_A, dev_priv->regfile.saveHSYNC_A);
484− I915_WRITE(_VTOTAL_A, dev_priv->regfile.saveVTOTAL_A);
485− I915_WRITE(_VBLANK_A, dev_priv->regfile.saveVBLANK_A);
486− I915_WRITE(_VSYNC_A, dev_priv->regfile.saveVSYNC_A);
487− if (!HAS_PCH_SPLIT(dev))
488− I915_WRITE(_BCLRPAT_A, dev_priv->regfile.saveBCLRPAT_A);
489−
490− if (HAS_PCH_SPLIT(dev)) {
491− I915_WRITE(_PIPEA_DATA_M1, dev_priv->regfile.savePIPEA_DATA_M1);
492− I915_WRITE(_PIPEA_DATA_N1, dev_priv->regfile.savePIPEA_DATA_N1);
493− I915_WRITE(_PIPEA_LINK_M1, dev_priv->regfile.savePIPEA_LINK_M1);
494− I915_WRITE(_PIPEA_LINK_N1, dev_priv->regfile.savePIPEA_LINK_N1);
495−
496− I915_WRITE(_FDI_RXA_CTL, dev_priv->regfile.saveFDI_RXA_CTL);
497− I915_WRITE(_FDI_TXA_CTL, dev_priv->regfile.saveFDI_TXA_CTL);
498−
499− I915_WRITE(_PFA_CTL_1, dev_priv->regfile.savePFA_CTL_1);
500− I915_WRITE(_PFA_WIN_SZ, dev_priv->regfile.savePFA_WIN_SZ);
501− I915_WRITE(_PFA_WIN_POS, dev_priv->regfile.savePFA_WIN_POS);
502−
503− I915_WRITE(_TRANSACONF, dev_priv->regfile.saveTRANSACONF);
504− I915_WRITE(_TRANS_HTOTAL_A, dev_priv->regfile.saveTRANS_HTOTAL_A);
505− I915_WRITE(_TRANS_HBLANK_A, dev_priv->regfile.saveTRANS_HBLANK_A);
506− I915_WRITE(_TRANS_HSYNC_A, dev_priv->regfile.saveTRANS_HSYNC_A);
507− I915_WRITE(_TRANS_VTOTAL_A, dev_priv->regfile.saveTRANS_VTOTAL_A);
508− I915_WRITE(_TRANS_VBLANK_A, dev_priv->regfile.saveTRANS_VBLANK_A);
509− I915_WRITE(_TRANS_VSYNC_A, dev_priv->regfile.saveTRANS_VSYNC_A);
510− }
511−
512− /* Restore plane info */
513− I915_WRITE(_DSPASIZE, dev_priv->regfile.saveDSPASIZE);
514− I915_WRITE(_DSPAPOS, dev_priv->regfile.saveDSPAPOS);
515− I915_WRITE(_PIPEASRC, dev_priv->regfile.savePIPEASRC);
516− I915_WRITE(_DSPAADDR, dev_priv->regfile.saveDSPAADDR);
517− I915_WRITE(_DSPASTRIDE, dev_priv->regfile.saveDSPASTRIDE);
518− if (INTEL_INFO(dev)->gen >= 4) {
519− I915_WRITE(_DSPASURF, dev_priv->regfile.saveDSPASURF);
520− I915_WRITE(_DSPATILEOFF, dev_priv->regfile.saveDSPATILEOFF);
521− }
522−
523− I915_WRITE(_PIPEACONF, dev_priv->regfile.savePIPEACONF);
524−
525− i915_restore_palette(dev, PIPE_A);
526− /* Enable the plane */
527− I915_WRITE(_DSPACNTR, dev_priv->regfile.saveDSPACNTR);
528− I915_WRITE(_DSPAADDR, I915_READ(_DSPAADDR));
529−
530− /* Pipe & plane B info */
531− if (dev_priv->regfile.saveDPLL_B & DPLL_VCO_ENABLE) {
532− I915_WRITE(dpll_b_reg, dev_priv->regfile.saveDPLL_B &
533− ~DPLL_VCO_ENABLE);
534− POSTING_READ(dpll_b_reg);
535− udelay(150);
536− }
537− I915_WRITE(fpb0_reg, dev_priv->regfile.saveFPB0);
538− I915_WRITE(fpb1_reg, dev_priv->regfile.saveFPB1);
539− /* Actually enable it */
540− I915_WRITE(dpll_b_reg, dev_priv->regfile.saveDPLL_B);
541− POSTING_READ(dpll_b_reg);
542− udelay(150);
543− if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
544− I915_WRITE(_DPLL_B_MD, dev_priv->regfile.saveDPLL_B_MD);
545− POSTING_READ(_DPLL_B_MD);
546− }
547− udelay(150);
548−
549− /* Restore mode */
550− I915_WRITE(_HTOTAL_B, dev_priv->regfile.saveHTOTAL_B);
551− I915_WRITE(_HBLANK_B, dev_priv->regfile.saveHBLANK_B);
552− I915_WRITE(_HSYNC_B, dev_priv->regfile.saveHSYNC_B);
553− I915_WRITE(_VTOTAL_B, dev_priv->regfile.saveVTOTAL_B);
554− I915_WRITE(_VBLANK_B, dev_priv->regfile.saveVBLANK_B);
555− I915_WRITE(_VSYNC_B, dev_priv->regfile.saveVSYNC_B);
556− if (!HAS_PCH_SPLIT(dev))
557− I915_WRITE(_BCLRPAT_B, dev_priv->regfile.saveBCLRPAT_B);
558−
559− if (HAS_PCH_SPLIT(dev)) {
560− I915_WRITE(_PIPEB_DATA_M1, dev_priv->regfile.savePIPEB_DATA_M1);
561− I915_WRITE(_PIPEB_DATA_N1, dev_priv->regfile.savePIPEB_DATA_N1);
562− I915_WRITE(_PIPEB_LINK_M1, dev_priv->regfile.savePIPEB_LINK_M1);
563− I915_WRITE(_PIPEB_LINK_N1, dev_priv->regfile.savePIPEB_LINK_N1);
564−
565− I915_WRITE(_FDI_RXB_CTL, dev_priv->regfile.saveFDI_RXB_CTL);
566− I915_WRITE(_FDI_TXB_CTL, dev_priv->regfile.saveFDI_TXB_CTL);
567−
568− I915_WRITE(_PFB_CTL_1, dev_priv->regfile.savePFB_CTL_1);
569− I915_WRITE(_PFB_WIN_SZ, dev_priv->regfile.savePFB_WIN_SZ);
570− I915_WRITE(_PFB_WIN_POS, dev_priv->regfile.savePFB_WIN_POS);
571−
572− I915_WRITE(_TRANSBCONF, dev_priv->regfile.saveTRANSBCONF);
573− I915_WRITE(_TRANS_HTOTAL_B, dev_priv->regfile.saveTRANS_HTOTAL_B);
574− I915_WRITE(_TRANS_HBLANK_B, dev_priv->regfile.saveTRANS_HBLANK_B);
575− I915_WRITE(_TRANS_HSYNC_B, dev_priv->regfile.saveTRANS_HSYNC_B);
576− I915_WRITE(_TRANS_VTOTAL_B, dev_priv->regfile.saveTRANS_VTOTAL_B);
577− I915_WRITE(_TRANS_VBLANK_B, dev_priv->regfile.saveTRANS_VBLANK_B);
578− I915_WRITE(_TRANS_VSYNC_B, dev_priv->regfile.saveTRANS_VSYNC_B);
579− }
580−
581− /* Restore plane info */
582− I915_WRITE(_DSPBSIZE, dev_priv->regfile.saveDSPBSIZE);
583− I915_WRITE(_DSPBPOS, dev_priv->regfile.saveDSPBPOS);
584− I915_WRITE(_PIPEBSRC, dev_priv->regfile.savePIPEBSRC);
585− I915_WRITE(_DSPBADDR, dev_priv->regfile.saveDSPBADDR);
586− I915_WRITE(_DSPBSTRIDE, dev_priv->regfile.saveDSPBSTRIDE);
587− if (INTEL_INFO(dev)->gen >= 4) {
588− I915_WRITE(_DSPBSURF, dev_priv->regfile.saveDSPBSURF);
589− I915_WRITE(_DSPBTILEOFF, dev_priv->regfile.saveDSPBTILEOFF);
590− }
591−
592− I915_WRITE(_PIPEBCONF, dev_priv->regfile.savePIPEBCONF);
593−
594− i915_restore_palette(dev, PIPE_B);
595− /* Enable the plane */
596− I915_WRITE(_DSPBCNTR, dev_priv->regfile.saveDSPBCNTR);
597− I915_WRITE(_DSPBADDR, I915_READ(_DSPBADDR));
598−
599− /* Cursor state */
600− I915_WRITE(_CURAPOS, dev_priv->regfile.saveCURAPOS);
601− I915_WRITE(_CURACNTR, dev_priv->regfile.saveCURACNTR);
602− I915_WRITE(_CURABASE, dev_priv->regfile.saveCURABASE);
603− I915_WRITE(_CURBPOS, dev_priv->regfile.saveCURBPOS);
604− I915_WRITE(_CURBCNTR, dev_priv->regfile.saveCURBCNTR);
605− I915_WRITE(_CURBBASE, dev_priv->regfile.saveCURBBASE);
606− if (IS_GEN2(dev))
607− I915_WRITE(CURSIZE, dev_priv->regfile.saveCURSIZE);
608−
609− /* CRT state */
610− if (HAS_PCH_SPLIT(dev))
611− I915_WRITE(PCH_ADPA, dev_priv->regfile.saveADPA);
612− else
613− I915_WRITE(ADPA, dev_priv->regfile.saveADPA);
614−
615− return;
616−}
617−
618192 static void i915_save_display(struct drm_device *dev)
619193 {
620194 struct drm_i915_private *dev_priv = dev->dev_private;
621195
622196 /* Display arbitration control */
623− dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
197+ if (INTEL_INFO(dev)->gen <= 4)
198+ dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
624199
625200 /* This is only meaningful in non-KMS mode */
626201 /* Don't regfile.save them in KMS mode */
627− i915_save_modeset_reg(dev);
202+ if (!drm_core_check_feature(dev, DRIVER_MODESET))
203+ i915_save_display_reg(dev);
628204
629205 /* LVDS state */
630206 if (HAS_PCH_SPLIT(dev)) {
@@ -658,24 +234,6 @@ static void i915_save_display(struct drm_device *dev) · 27 unmodified lines
658234 dev_priv->regfile.savePP_DIVISOR = I915_READ(PP_DIVISOR);
659235 }
660236
661− if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
662− /* Display Port state */
663− if (SUPPORTS_INTEGRATED_DP(dev)) {
664− dev_priv->regfile.saveDP_B = I915_READ(DP_B);
665− dev_priv->regfile.saveDP_C = I915_READ(DP_C);
666− dev_priv->regfile.saveDP_D = I915_READ(DP_D);
667− dev_priv->regfile.savePIPEA_GMCH_DATA_M = I915_READ(_PIPEA_GMCH_DATA_M);
668− dev_priv->regfile.savePIPEB_GMCH_DATA_M = I915_READ(_PIPEB_GMCH_DATA_M);
669− dev_priv->regfile.savePIPEA_GMCH_DATA_N = I915_READ(_PIPEA_GMCH_DATA_N);
670− dev_priv->regfile.savePIPEB_GMCH_DATA_N = I915_READ(_PIPEB_GMCH_DATA_N);
671− dev_priv->regfile.savePIPEA_DP_LINK_M = I915_READ(_PIPEA_DP_LINK_M);
672− dev_priv->regfile.savePIPEB_DP_LINK_M = I915_READ(_PIPEB_DP_LINK_M);
673− dev_priv->regfile.savePIPEA_DP_LINK_N = I915_READ(_PIPEA_DP_LINK_N);
674− dev_priv->regfile.savePIPEB_DP_LINK_N = I915_READ(_PIPEB_DP_LINK_N);
675− }
676− /* FIXME: regfile.save TV & SDVO state */
677− }
678−
679237 /* Only regfile.save FBC state on the platform that supports FBC */
680238 if (I915_HAS_FBC(dev)) {
681239 if (HAS_PCH_SPLIT(dev)) {
@@ -690,16 +248,8 @@ static void i915_save_display(struct drm_device *dev) · 8 unmodified lines
690248 }
691249 }
692250
693− /* VGA state */
694− dev_priv->regfile.saveVGA0 = I915_READ(VGA0);
695− dev_priv->regfile.saveVGA1 = I915_READ(VGA1);
696− dev_priv->regfile.saveVGA_PD = I915_READ(VGA_PD);
697− if (HAS_PCH_SPLIT(dev))
698− dev_priv->regfile.saveVGACNTRL = I915_READ(CPU_VGACNTRL);
699− else
700− dev_priv->regfile.saveVGACNTRL = I915_READ(VGACNTRL);
701−
702− i915_save_vga(dev);
251+ if (!drm_core_check_feature(dev, DRIVER_MODESET))
252+ i915_save_vga(dev);
703253 }
704254
705255 static void i915_restore_display(struct drm_device *dev)
@@ -707,25 +257,11 @@ static void i915_restore_display(struct drm_device *dev) · 1 unmodified line
707257 struct drm_i915_private *dev_priv = dev->dev_private;
708258
709259 /* Display arbitration */
710− I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
260+ if (INTEL_INFO(dev)->gen <= 4)
261+ I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
711262
712− if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
713− /* Display port ratios (must be done before clock is set) */
714− if (SUPPORTS_INTEGRATED_DP(dev)) {
715− I915_WRITE(_PIPEA_GMCH_DATA_M, dev_priv->regfile.savePIPEA_GMCH_DATA_M);
716− I915_WRITE(_PIPEB_GMCH_DATA_M, dev_priv->regfile.savePIPEB_GMCH_DATA_M);
717− I915_WRITE(_PIPEA_GMCH_DATA_N, dev_priv->regfile.savePIPEA_GMCH_DATA_N);
718− I915_WRITE(_PIPEB_GMCH_DATA_N, dev_priv->regfile.savePIPEB_GMCH_DATA_N);
719− I915_WRITE(_PIPEA_DP_LINK_M, dev_priv->regfile.savePIPEA_DP_LINK_M);
720− I915_WRITE(_PIPEB_DP_LINK_M, dev_priv->regfile.savePIPEB_DP_LINK_M);
721− I915_WRITE(_PIPEA_DP_LINK_N, dev_priv->regfile.savePIPEA_DP_LINK_N);
722− I915_WRITE(_PIPEB_DP_LINK_N, dev_priv->regfile.savePIPEB_DP_LINK_N);
723− }
724− }
725−
726− /* This is only meaningful in non-KMS mode */
727− /* Don't restore them in KMS mode */
728− i915_restore_modeset_reg(dev);
263+ if (!drm_core_check_feature(dev, DRIVER_MODESET))
264+ i915_restore_display_reg(dev);
729265
730266 /* LVDS state */
731267 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
@@ -763,16 +299,6 @@ static void i915_restore_display(struct drm_device *dev) · 31 unmodified lines
763299 I915_WRITE(PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
764300 }
765301
766− if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
767− /* Display Port state */
768− if (SUPPORTS_INTEGRATED_DP(dev)) {
769− I915_WRITE(DP_B, dev_priv->regfile.saveDP_B);
770− I915_WRITE(DP_C, dev_priv->regfile.saveDP_C);
771− I915_WRITE(DP_D, dev_priv->regfile.saveDP_D);
772− }
773− /* FIXME: restore TV & SDVO state */
774− }
775−
776302 /* only restore FBC info on the platform that supports FBC*/
777303 intel_disable_fbc(dev);
778304 if (I915_HAS_FBC(dev)) {
@@ -787,19 +313,11 @@ static void i915_restore_display(struct drm_device *dev) · 8 unmodified lines
787313 I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
788314 }
789315 }
790− /* VGA state */
791− if (HAS_PCH_SPLIT(dev))
792− I915_WRITE(CPU_VGACNTRL, dev_priv->regfile.saveVGACNTRL);
793− else
794− I915_WRITE(VGACNTRL, dev_priv->regfile.saveVGACNTRL);
795316
796− I915_WRITE(VGA0, dev_priv->regfile.saveVGA0);
797− I915_WRITE(VGA1, dev_priv->regfile.saveVGA1);
798− I915_WRITE(VGA_PD, dev_priv->regfile.saveVGA_PD);
799− POSTING_READ(VGA_PD);
800− udelay(150);
801−
802− i915_restore_vga(dev);
317+ if (!drm_core_check_feature(dev, DRIVER_MODESET))
318+ i915_restore_vga(dev);
319+ else
320+ i915_redisable_vga(dev);
803321 }
804322
805323 int i915_save_state(struct drm_device *dev)
drivers/gpu/drm/i915/i915_ums.c+503−0
@@ -0,0 +1,503 @@
1+/*
2+ *
3+ * Copyright 2008 (c) Intel Corporation
4+ * Jesse Barnes <jbarnes@virtuousgeek.org>
5+ * Copyright 2013 (c) Intel Corporation
6+ * Daniel Vetter <daniel.vetter@ffwll.ch>
7+ *
8+ * Permission is hereby granted, free of charge, to any person obtaining a
9+ * copy of this software and associated documentation files (the
10+ * "Software"), to deal in the Software without restriction, including
11+ * without limitation the rights to use, copy, modify, merge, publish,
12+ * distribute, sub license, and/or sell copies of the Software, and to
13+ * permit persons to whom the Software is furnished to do so, subject to
14+ * the following conditions:
15+ *
16+ * The above copyright notice and this permission notice (including the
17+ * next paragraph) shall be included in all copies or substantial portions
18+ * of the Software.
19+ *
20+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23+ * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27+ */
28+
29+#include <drm/drmP.h>
30+#include <drm/i915_drm.h>
31+#include "intel_drv.h"
32+#include "i915_reg.h"
33+
34+static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
35+{
36+ struct drm_i915_private *dev_priv = dev->dev_private;
37+ u32 dpll_reg;
38+
39+ /* On IVB, 3rd pipe shares PLL with another one */
40+ if (pipe > 1)
41+ return false;
42+
43+ if (HAS_PCH_SPLIT(dev))
44+ dpll_reg = _PCH_DPLL(pipe);
45+ else
46+ dpll_reg = (pipe == PIPE_A) ? _DPLL_A : _DPLL_B;
47+
48+ return (I915_READ(dpll_reg) & DPLL_VCO_ENABLE);
49+}
50+
51+static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
52+{
53+ struct drm_i915_private *dev_priv = dev->dev_private;
54+ unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B);
55+ u32 *array;
56+ int i;
57+
58+ if (!i915_pipe_enabled(dev, pipe))
59+ return;
60+
61+ if (HAS_PCH_SPLIT(dev))
62+ reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B;
63+
64+ if (pipe == PIPE_A)
65+ array = dev_priv->regfile.save_palette_a;
66+ else
67+ array = dev_priv->regfile.save_palette_b;
68+
69+ for (i = 0; i < 256; i++)
70+ array[i] = I915_READ(reg + (i << 2));
71+}
72+
73+static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
74+{
75+ struct drm_i915_private *dev_priv = dev->dev_private;
76+ unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B);
77+ u32 *array;
78+ int i;
79+
80+ if (!i915_pipe_enabled(dev, pipe))
81+ return;
82+
83+ if (HAS_PCH_SPLIT(dev))
84+ reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B;
85+
86+ if (pipe == PIPE_A)
87+ array = dev_priv->regfile.save_palette_a;
88+ else
89+ array = dev_priv->regfile.save_palette_b;
90+
91+ for (i = 0; i < 256; i++)
92+ I915_WRITE(reg + (i << 2), array[i]);
93+}
94+
95+void i915_save_display_reg(struct drm_device *dev)
96+{
97+ struct drm_i915_private *dev_priv = dev->dev_private;
98+ int i;
99+
100+ /* Cursor state */
101+ dev_priv->regfile.saveCURACNTR = I915_READ(_CURACNTR);
102+ dev_priv->regfile.saveCURAPOS = I915_READ(_CURAPOS);
103+ dev_priv->regfile.saveCURABASE = I915_READ(_CURABASE);
104+ dev_priv->regfile.saveCURBCNTR = I915_READ(_CURBCNTR);
105+ dev_priv->regfile.saveCURBPOS = I915_READ(_CURBPOS);
106+ dev_priv->regfile.saveCURBBASE = I915_READ(_CURBBASE);
107+ if (IS_GEN2(dev))
108+ dev_priv->regfile.saveCURSIZE = I915_READ(CURSIZE);
109+
110+ if (HAS_PCH_SPLIT(dev)) {
111+ dev_priv->regfile.savePCH_DREF_CONTROL = I915_READ(PCH_DREF_CONTROL);
112+ dev_priv->regfile.saveDISP_ARB_CTL = I915_READ(DISP_ARB_CTL);
113+ }
114+
115+ /* Pipe & plane A info */
116+ dev_priv->regfile.savePIPEACONF = I915_READ(_PIPEACONF);
117+ dev_priv->regfile.savePIPEASRC = I915_READ(_PIPEASRC);
118+ if (HAS_PCH_SPLIT(dev)) {
119+ dev_priv->regfile.saveFPA0 = I915_READ(_PCH_FPA0);
120+ dev_priv->regfile.saveFPA1 = I915_READ(_PCH_FPA1);
121+ dev_priv->regfile.saveDPLL_A = I915_READ(_PCH_DPLL_A);
122+ } else {
123+ dev_priv->regfile.saveFPA0 = I915_READ(_FPA0);
124+ dev_priv->regfile.saveFPA1 = I915_READ(_FPA1);
125+ dev_priv->regfile.saveDPLL_A = I915_READ(_DPLL_A);
126+ }
127+ if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
128+ dev_priv->regfile.saveDPLL_A_MD = I915_READ(_DPLL_A_MD);
129+ dev_priv->regfile.saveHTOTAL_A = I915_READ(_HTOTAL_A);
130+ dev_priv->regfile.saveHBLANK_A = I915_READ(_HBLANK_A);
131+ dev_priv->regfile.saveHSYNC_A = I915_READ(_HSYNC_A);
132+ dev_priv->regfile.saveVTOTAL_A = I915_READ(_VTOTAL_A);
133+ dev_priv->regfile.saveVBLANK_A = I915_READ(_VBLANK_A);
134+ dev_priv->regfile.saveVSYNC_A = I915_READ(_VSYNC_A);
135+ if (!HAS_PCH_SPLIT(dev))
136+ dev_priv->regfile.saveBCLRPAT_A = I915_READ(_BCLRPAT_A);
137+
138+ if (HAS_PCH_SPLIT(dev)) {
139+ dev_priv->regfile.savePIPEA_DATA_M1 = I915_READ(_PIPEA_DATA_M1);
140+ dev_priv->regfile.savePIPEA_DATA_N1 = I915_READ(_PIPEA_DATA_N1);
141+ dev_priv->regfile.savePIPEA_LINK_M1 = I915_READ(_PIPEA_LINK_M1);
142+ dev_priv->regfile.savePIPEA_LINK_N1 = I915_READ(_PIPEA_LINK_N1);
143+
144+ dev_priv->regfile.saveFDI_TXA_CTL = I915_READ(_FDI_TXA_CTL);
145+ dev_priv->regfile.saveFDI_RXA_CTL = I915_READ(_FDI_RXA_CTL);
146+
147+ dev_priv->regfile.savePFA_CTL_1 = I915_READ(_PFA_CTL_1);
148+ dev_priv->regfile.savePFA_WIN_SZ = I915_READ(_PFA_WIN_SZ);
149+ dev_priv->regfile.savePFA_WIN_POS = I915_READ(_PFA_WIN_POS);
150+
151+ dev_priv->regfile.saveTRANSACONF = I915_READ(_TRANSACONF);
152+ dev_priv->regfile.saveTRANS_HTOTAL_A = I915_READ(_TRANS_HTOTAL_A);
153+ dev_priv->regfile.saveTRANS_HBLANK_A = I915_READ(_TRANS_HBLANK_A);
154+ dev_priv->regfile.saveTRANS_HSYNC_A = I915_READ(_TRANS_HSYNC_A);
155+ dev_priv->regfile.saveTRANS_VTOTAL_A = I915_READ(_TRANS_VTOTAL_A);
156+ dev_priv->regfile.saveTRANS_VBLANK_A = I915_READ(_TRANS_VBLANK_A);
157+ dev_priv->regfile.saveTRANS_VSYNC_A = I915_READ(_TRANS_VSYNC_A);
158+ }
159+
160+ dev_priv->regfile.saveDSPACNTR = I915_READ(_DSPACNTR);
161+ dev_priv->regfile.saveDSPASTRIDE = I915_READ(_DSPASTRIDE);
162+ dev_priv->regfile.saveDSPASIZE = I915_READ(_DSPASIZE);
163+ dev_priv->regfile.saveDSPAPOS = I915_READ(_DSPAPOS);
164+ dev_priv->regfile.saveDSPAADDR = I915_READ(_DSPAADDR);
165+ if (INTEL_INFO(dev)->gen >= 4) {
166+ dev_priv->regfile.saveDSPASURF = I915_READ(_DSPASURF);
167+ dev_priv->regfile.saveDSPATILEOFF = I915_READ(_DSPATILEOFF);
168+ }
169+ i915_save_palette(dev, PIPE_A);
170+ dev_priv->regfile.savePIPEASTAT = I915_READ(_PIPEASTAT);
171+
172+ /* Pipe & plane B info */
173+ dev_priv->regfile.savePIPEBCONF = I915_READ(_PIPEBCONF);
174+ dev_priv->regfile.savePIPEBSRC = I915_READ(_PIPEBSRC);
175+ if (HAS_PCH_SPLIT(dev)) {
176+ dev_priv->regfile.saveFPB0 = I915_READ(_PCH_FPB0);
177+ dev_priv->regfile.saveFPB1 = I915_READ(_PCH_FPB1);
178+ dev_priv->regfile.saveDPLL_B = I915_READ(_PCH_DPLL_B);
179+ } else {
180+ dev_priv->regfile.saveFPB0 = I915_READ(_FPB0);
181+ dev_priv->regfile.saveFPB1 = I915_READ(_FPB1);
182+ dev_priv->regfile.saveDPLL_B = I915_READ(_DPLL_B);
183+ }
184+ if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
185+ dev_priv->regfile.saveDPLL_B_MD = I915_READ(_DPLL_B_MD);
186+ dev_priv->regfile.saveHTOTAL_B = I915_READ(_HTOTAL_B);
187+ dev_priv->regfile.saveHBLANK_B = I915_READ(_HBLANK_B);
188+ dev_priv->regfile.saveHSYNC_B = I915_READ(_HSYNC_B);
189+ dev_priv->regfile.saveVTOTAL_B = I915_READ(_VTOTAL_B);
190+ dev_priv->regfile.saveVBLANK_B = I915_READ(_VBLANK_B);
191+ dev_priv->regfile.saveVSYNC_B = I915_READ(_VSYNC_B);
192+ if (!HAS_PCH_SPLIT(dev))
193+ dev_priv->regfile.saveBCLRPAT_B = I915_READ(_BCLRPAT_B);
194+
195+ if (HAS_PCH_SPLIT(dev)) {
196+ dev_priv->regfile.savePIPEB_DATA_M1 = I915_READ(_PIPEB_DATA_M1);
197+ dev_priv->regfile.savePIPEB_DATA_N1 = I915_READ(_PIPEB_DATA_N1);
198+ dev_priv->regfile.savePIPEB_LINK_M1 = I915_READ(_PIPEB_LINK_M1);
199+ dev_priv->regfile.savePIPEB_LINK_N1 = I915_READ(_PIPEB_LINK_N1);
200+
201+ dev_priv->regfile.saveFDI_TXB_CTL = I915_READ(_FDI_TXB_CTL);
202+ dev_priv->regfile.saveFDI_RXB_CTL = I915_READ(_FDI_RXB_CTL);
203+
204+ dev_priv->regfile.savePFB_CTL_1 = I915_READ(_PFB_CTL_1);
205+ dev_priv->regfile.savePFB_WIN_SZ = I915_READ(_PFB_WIN_SZ);
206+ dev_priv->regfile.savePFB_WIN_POS = I915_READ(_PFB_WIN_POS);
207+
208+ dev_priv->regfile.saveTRANSBCONF = I915_READ(_TRANSBCONF);
209+ dev_priv->regfile.saveTRANS_HTOTAL_B = I915_READ(_TRANS_HTOTAL_B);
210+ dev_priv->regfile.saveTRANS_HBLANK_B = I915_READ(_TRANS_HBLANK_B);
211+ dev_priv->regfile.saveTRANS_HSYNC_B = I915_READ(_TRANS_HSYNC_B);
212+ dev_priv->regfile.saveTRANS_VTOTAL_B = I915_READ(_TRANS_VTOTAL_B);
213+ dev_priv->regfile.saveTRANS_VBLANK_B = I915_READ(_TRANS_VBLANK_B);
214+ dev_priv->regfile.saveTRANS_VSYNC_B = I915_READ(_TRANS_VSYNC_B);
215+ }
216+
217+ dev_priv->regfile.saveDSPBCNTR = I915_READ(_DSPBCNTR);
218+ dev_priv->regfile.saveDSPBSTRIDE = I915_READ(_DSPBSTRIDE);
219+ dev_priv->regfile.saveDSPBSIZE = I915_READ(_DSPBSIZE);
220+ dev_priv->regfile.saveDSPBPOS = I915_READ(_DSPBPOS);
221+ dev_priv->regfile.saveDSPBADDR = I915_READ(_DSPBADDR);
222+ if (INTEL_INFO(dev)->gen >= 4) {
223+ dev_priv->regfile.saveDSPBSURF = I915_READ(_DSPBSURF);
224+ dev_priv->regfile.saveDSPBTILEOFF = I915_READ(_DSPBTILEOFF);
225+ }
226+ i915_save_palette(dev, PIPE_B);
227+ dev_priv->regfile.savePIPEBSTAT = I915_READ(_PIPEBSTAT);
228+
229+ /* Fences */
230+ switch (INTEL_INFO(dev)->gen) {
231+ case 7:
232+ case 6:
233+ for (i = 0; i < 16; i++)
234+ dev_priv->regfile.saveFENCE[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
235+ break;
236+ case 5:
237+ case 4:
238+ for (i = 0; i < 16; i++)
239+ dev_priv->regfile.saveFENCE[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
240+ break;
241+ case 3:
242+ if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
243+ for (i = 0; i < 8; i++)
244+ dev_priv->regfile.saveFENCE[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
245+ case 2:
246+ for (i = 0; i < 8; i++)
247+ dev_priv->regfile.saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
248+ break;
249+ }
250+
251+ /* CRT state */
252+ if (HAS_PCH_SPLIT(dev))
253+ dev_priv->regfile.saveADPA = I915_READ(PCH_ADPA);
254+ else
255+ dev_priv->regfile.saveADPA = I915_READ(ADPA);
256+
257+ /* Display Port state */
258+ if (SUPPORTS_INTEGRATED_DP(dev)) {
259+ dev_priv->regfile.saveDP_B = I915_READ(DP_B);
260+ dev_priv->regfile.saveDP_C = I915_READ(DP_C);
261+ dev_priv->regfile.saveDP_D = I915_READ(DP_D);
262+ dev_priv->regfile.savePIPEA_GMCH_DATA_M = I915_READ(_PIPEA_GMCH_DATA_M);
263+ dev_priv->regfile.savePIPEB_GMCH_DATA_M = I915_READ(_PIPEB_GMCH_DATA_M);
264+ dev_priv->regfile.savePIPEA_GMCH_DATA_N = I915_READ(_PIPEA_GMCH_DATA_N);
265+ dev_priv->regfile.savePIPEB_GMCH_DATA_N = I915_READ(_PIPEB_GMCH_DATA_N);
266+ dev_priv->regfile.savePIPEA_DP_LINK_M = I915_READ(_PIPEA_DP_LINK_M);
267+ dev_priv->regfile.savePIPEB_DP_LINK_M = I915_READ(_PIPEB_DP_LINK_M);
268+ dev_priv->regfile.savePIPEA_DP_LINK_N = I915_READ(_PIPEA_DP_LINK_N);
269+ dev_priv->regfile.savePIPEB_DP_LINK_N = I915_READ(_PIPEB_DP_LINK_N);
270+ }
271+ /* FIXME: regfile.save TV & SDVO state */
272+
273+ return;
274+}
275+
276+void i915_restore_display_reg(struct drm_device *dev)
277+{
278+ struct drm_i915_private *dev_priv = dev->dev_private;
279+ int dpll_a_reg, fpa0_reg, fpa1_reg;
280+ int dpll_b_reg, fpb0_reg, fpb1_reg;
281+ int i;
282+
283+ /* Display port ratios (must be done before clock is set) */
284+ if (SUPPORTS_INTEGRATED_DP(dev)) {
285+ I915_WRITE(_PIPEA_GMCH_DATA_M, dev_priv->regfile.savePIPEA_GMCH_DATA_M);
286+ I915_WRITE(_PIPEB_GMCH_DATA_M, dev_priv->regfile.savePIPEB_GMCH_DATA_M);
287+ I915_WRITE(_PIPEA_GMCH_DATA_N, dev_priv->regfile.savePIPEA_GMCH_DATA_N);
288+ I915_WRITE(_PIPEB_GMCH_DATA_N, dev_priv->regfile.savePIPEB_GMCH_DATA_N);
289+ I915_WRITE(_PIPEA_DP_LINK_M, dev_priv->regfile.savePIPEA_DP_LINK_M);
290+ I915_WRITE(_PIPEB_DP_LINK_M, dev_priv->regfile.savePIPEB_DP_LINK_M);
291+ I915_WRITE(_PIPEA_DP_LINK_N, dev_priv->regfile.savePIPEA_DP_LINK_N);
292+ I915_WRITE(_PIPEB_DP_LINK_N, dev_priv->regfile.savePIPEB_DP_LINK_N);
293+ }
294+
295+ /* Fences */
296+ switch (INTEL_INFO(dev)->gen) {
297+ case 7:
298+ case 6:
299+ for (i = 0; i < 16; i++)
300+ I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), dev_priv->regfile.saveFENCE[i]);
301+ break;
302+ case 5:
303+ case 4:
304+ for (i = 0; i < 16; i++)
305+ I915_WRITE64(FENCE_REG_965_0 + (i * 8), dev_priv->regfile.saveFENCE[i]);
306+ break;
307+ case 3:
308+ case 2:
309+ if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
310+ for (i = 0; i < 8; i++)
311+ I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->regfile.saveFENCE[i+8]);
312+ for (i = 0; i < 8; i++)
313+ I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->regfile.saveFENCE[i]);
314+ break;
315+ }
316+
317+
318+ if (HAS_PCH_SPLIT(dev)) {
319+ dpll_a_reg = _PCH_DPLL_A;
320+ dpll_b_reg = _PCH_DPLL_B;
321+ fpa0_reg = _PCH_FPA0;
322+ fpb0_reg = _PCH_FPB0;
323+ fpa1_reg = _PCH_FPA1;
324+ fpb1_reg = _PCH_FPB1;
325+ } else {
326+ dpll_a_reg = _DPLL_A;
327+ dpll_b_reg = _DPLL_B;
328+ fpa0_reg = _FPA0;
329+ fpb0_reg = _FPB0;
330+ fpa1_reg = _FPA1;
331+ fpb1_reg = _FPB1;
332+ }
333+
334+ if (HAS_PCH_SPLIT(dev)) {
335+ I915_WRITE(PCH_DREF_CONTROL, dev_priv->regfile.savePCH_DREF_CONTROL);
336+ I915_WRITE(DISP_ARB_CTL, dev_priv->regfile.saveDISP_ARB_CTL);
337+ }
338+
339+ /* Pipe & plane A info */
340+ /* Prime the clock */
341+ if (dev_priv->regfile.saveDPLL_A & DPLL_VCO_ENABLE) {
342+ I915_WRITE(dpll_a_reg, dev_priv->regfile.saveDPLL_A &
343+ ~DPLL_VCO_ENABLE);
344+ POSTING_READ(dpll_a_reg);
345+ udelay(150);
346+ }
347+ I915_WRITE(fpa0_reg, dev_priv->regfile.saveFPA0);
348+ I915_WRITE(fpa1_reg, dev_priv->regfile.saveFPA1);
349+ /* Actually enable it */
350+ I915_WRITE(dpll_a_reg, dev_priv->regfile.saveDPLL_A);
351+ POSTING_READ(dpll_a_reg);
352+ udelay(150);
353+ if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
354+ I915_WRITE(_DPLL_A_MD, dev_priv->regfile.saveDPLL_A_MD);
355+ POSTING_READ(_DPLL_A_MD);
356+ }
357+ udelay(150);
358+
359+ /* Restore mode */
360+ I915_WRITE(_HTOTAL_A, dev_priv->regfile.saveHTOTAL_A);
361+ I915_WRITE(_HBLANK_A, dev_priv->regfile.saveHBLANK_A);
362+ I915_WRITE(_HSYNC_A, dev_priv->regfile.saveHSYNC_A);
363+ I915_WRITE(_VTOTAL_A, dev_priv->regfile.saveVTOTAL_A);
364+ I915_WRITE(_VBLANK_A, dev_priv->regfile.saveVBLANK_A);
365+ I915_WRITE(_VSYNC_A, dev_priv->regfile.saveVSYNC_A);
366+ if (!HAS_PCH_SPLIT(dev))
367+ I915_WRITE(_BCLRPAT_A, dev_priv->regfile.saveBCLRPAT_A);
368+
369+ if (HAS_PCH_SPLIT(dev)) {
370+ I915_WRITE(_PIPEA_DATA_M1, dev_priv->regfile.savePIPEA_DATA_M1);
371+ I915_WRITE(_PIPEA_DATA_N1, dev_priv->regfile.savePIPEA_DATA_N1);
372+ I915_WRITE(_PIPEA_LINK_M1, dev_priv->regfile.savePIPEA_LINK_M1);
373+ I915_WRITE(_PIPEA_LINK_N1, dev_priv->regfile.savePIPEA_LINK_N1);
374+
375+ I915_WRITE(_FDI_RXA_CTL, dev_priv->regfile.saveFDI_RXA_CTL);
376+ I915_WRITE(_FDI_TXA_CTL, dev_priv->regfile.saveFDI_TXA_CTL);
377+
378+ I915_WRITE(_PFA_CTL_1, dev_priv->regfile.savePFA_CTL_1);
379+ I915_WRITE(_PFA_WIN_SZ, dev_priv->regfile.savePFA_WIN_SZ);
380+ I915_WRITE(_PFA_WIN_POS, dev_priv->regfile.savePFA_WIN_POS);
381+
382+ I915_WRITE(_TRANSACONF, dev_priv->regfile.saveTRANSACONF);
383+ I915_WRITE(_TRANS_HTOTAL_A, dev_priv->regfile.saveTRANS_HTOTAL_A);
384+ I915_WRITE(_TRANS_HBLANK_A, dev_priv->regfile.saveTRANS_HBLANK_A);
385+ I915_WRITE(_TRANS_HSYNC_A, dev_priv->regfile.saveTRANS_HSYNC_A);
386+ I915_WRITE(_TRANS_VTOTAL_A, dev_priv->regfile.saveTRANS_VTOTAL_A);
387+ I915_WRITE(_TRANS_VBLANK_A, dev_priv->regfile.saveTRANS_VBLANK_A);
388+ I915_WRITE(_TRANS_VSYNC_A, dev_priv->regfile.saveTRANS_VSYNC_A);
389+ }
390+
391+ /* Restore plane info */
392+ I915_WRITE(_DSPASIZE, dev_priv->regfile.saveDSPASIZE);
393+ I915_WRITE(_DSPAPOS, dev_priv->regfile.saveDSPAPOS);
394+ I915_WRITE(_PIPEASRC, dev_priv->regfile.savePIPEASRC);
395+ I915_WRITE(_DSPAADDR, dev_priv->regfile.saveDSPAADDR);
396+ I915_WRITE(_DSPASTRIDE, dev_priv->regfile.saveDSPASTRIDE);
397+ if (INTEL_INFO(dev)->gen >= 4) {
398+ I915_WRITE(_DSPASURF, dev_priv->regfile.saveDSPASURF);
399+ I915_WRITE(_DSPATILEOFF, dev_priv->regfile.saveDSPATILEOFF);
400+ }
401+
402+ I915_WRITE(_PIPEACONF, dev_priv->regfile.savePIPEACONF);
403+
404+ i915_restore_palette(dev, PIPE_A);
405+ /* Enable the plane */
406+ I915_WRITE(_DSPACNTR, dev_priv->regfile.saveDSPACNTR);
407+ I915_WRITE(_DSPAADDR, I915_READ(_DSPAADDR));
408+
409+ /* Pipe & plane B info */
410+ if (dev_priv->regfile.saveDPLL_B & DPLL_VCO_ENABLE) {
411+ I915_WRITE(dpll_b_reg, dev_priv->regfile.saveDPLL_B &
412+ ~DPLL_VCO_ENABLE);
413+ POSTING_READ(dpll_b_reg);
414+ udelay(150);
415+ }
416+ I915_WRITE(fpb0_reg, dev_priv->regfile.saveFPB0);
417+ I915_WRITE(fpb1_reg, dev_priv->regfile.saveFPB1);
418+ /* Actually enable it */
419+ I915_WRITE(dpll_b_reg, dev_priv->regfile.saveDPLL_B);
420+ POSTING_READ(dpll_b_reg);
421+ udelay(150);
422+ if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
423+ I915_WRITE(_DPLL_B_MD, dev_priv->regfile.saveDPLL_B_MD);
424+ POSTING_READ(_DPLL_B_MD);
425+ }
426+ udelay(150);
427+
428+ /* Restore mode */
429+ I915_WRITE(_HTOTAL_B, dev_priv->regfile.saveHTOTAL_B);
430+ I915_WRITE(_HBLANK_B, dev_priv->regfile.saveHBLANK_B);
431+ I915_WRITE(_HSYNC_B, dev_priv->regfile.saveHSYNC_B);
432+ I915_WRITE(_VTOTAL_B, dev_priv->regfile.saveVTOTAL_B);
433+ I915_WRITE(_VBLANK_B, dev_priv->regfile.saveVBLANK_B);
434+ I915_WRITE(_VSYNC_B, dev_priv->regfile.saveVSYNC_B);
435+ if (!HAS_PCH_SPLIT(dev))
436+ I915_WRITE(_BCLRPAT_B, dev_priv->regfile.saveBCLRPAT_B);
437+
438+ if (HAS_PCH_SPLIT(dev)) {
439+ I915_WRITE(_PIPEB_DATA_M1, dev_priv->regfile.savePIPEB_DATA_M1);
440+ I915_WRITE(_PIPEB_DATA_N1, dev_priv->regfile.savePIPEB_DATA_N1);
441+ I915_WRITE(_PIPEB_LINK_M1, dev_priv->regfile.savePIPEB_LINK_M1);
442+ I915_WRITE(_PIPEB_LINK_N1, dev_priv->regfile.savePIPEB_LINK_N1);
443+
444+ I915_WRITE(_FDI_RXB_CTL, dev_priv->regfile.saveFDI_RXB_CTL);
445+ I915_WRITE(_FDI_TXB_CTL, dev_priv->regfile.saveFDI_TXB_CTL);
446+
447+ I915_WRITE(_PFB_CTL_1, dev_priv->regfile.savePFB_CTL_1);
448+ I915_WRITE(_PFB_WIN_SZ, dev_priv->regfile.savePFB_WIN_SZ);
449+ I915_WRITE(_PFB_WIN_POS, dev_priv->regfile.savePFB_WIN_POS);
450+
451+ I915_WRITE(_TRANSBCONF, dev_priv->regfile.saveTRANSBCONF);
452+ I915_WRITE(_TRANS_HTOTAL_B, dev_priv->regfile.saveTRANS_HTOTAL_B);
453+ I915_WRITE(_TRANS_HBLANK_B, dev_priv->regfile.saveTRANS_HBLANK_B);
454+ I915_WRITE(_TRANS_HSYNC_B, dev_priv->regfile.saveTRANS_HSYNC_B);
455+ I915_WRITE(_TRANS_VTOTAL_B, dev_priv->regfile.saveTRANS_VTOTAL_B);
456+ I915_WRITE(_TRANS_VBLANK_B, dev_priv->regfile.saveTRANS_VBLANK_B);
457+ I915_WRITE(_TRANS_VSYNC_B, dev_priv->regfile.saveTRANS_VSYNC_B);
458+ }
459+
460+ /* Restore plane info */
461+ I915_WRITE(_DSPBSIZE, dev_priv->regfile.saveDSPBSIZE);
462+ I915_WRITE(_DSPBPOS, dev_priv->regfile.saveDSPBPOS);
463+ I915_WRITE(_PIPEBSRC, dev_priv->regfile.savePIPEBSRC);
464+ I915_WRITE(_DSPBADDR, dev_priv->regfile.saveDSPBADDR);
465+ I915_WRITE(_DSPBSTRIDE, dev_priv->regfile.saveDSPBSTRIDE);
466+ if (INTEL_INFO(dev)->gen >= 4) {
467+ I915_WRITE(_DSPBSURF, dev_priv->regfile.saveDSPBSURF);
468+ I915_WRITE(_DSPBTILEOFF, dev_priv->regfile.saveDSPBTILEOFF);
469+ }
470+
471+ I915_WRITE(_PIPEBCONF, dev_priv->regfile.savePIPEBCONF);
472+
473+ i915_restore_palette(dev, PIPE_B);
474+ /* Enable the plane */
475+ I915_WRITE(_DSPBCNTR, dev_priv->regfile.saveDSPBCNTR);
476+ I915_WRITE(_DSPBADDR, I915_READ(_DSPBADDR));
477+
478+ /* Cursor state */
479+ I915_WRITE(_CURAPOS, dev_priv->regfile.saveCURAPOS);
480+ I915_WRITE(_CURACNTR, dev_priv->regfile.saveCURACNTR);
481+ I915_WRITE(_CURABASE, dev_priv->regfile.saveCURABASE);
482+ I915_WRITE(_CURBPOS, dev_priv->regfile.saveCURBPOS);
483+ I915_WRITE(_CURBCNTR, dev_priv->regfile.saveCURBCNTR);
484+ I915_WRITE(_CURBBASE, dev_priv->regfile.saveCURBBASE);
485+ if (IS_GEN2(dev))
486+ I915_WRITE(CURSIZE, dev_priv->regfile.saveCURSIZE);
487+
488+ /* CRT state */
489+ if (HAS_PCH_SPLIT(dev))
490+ I915_WRITE(PCH_ADPA, dev_priv->regfile.saveADPA);
491+ else
492+ I915_WRITE(ADPA, dev_priv->regfile.saveADPA);
493+
494+ /* Display Port state */
495+ if (SUPPORTS_INTEGRATED_DP(dev)) {
496+ I915_WRITE(DP_B, dev_priv->regfile.saveDP_B);
497+ I915_WRITE(DP_C, dev_priv->regfile.saveDP_C);
498+ I915_WRITE(DP_D, dev_priv->regfile.saveDP_D);
499+ }
500+ /* FIXME: restore TV & SDVO state */
501+
502+ return;
503+}
drivers/gpu/drm/i915/intel_crt.c+15−14
@@ -267,27 +267,27 @@ static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) · 266 unmodified lines
267267
268268 crt->force_hotplug_required = 0;
269269
270− save_adpa = adpa = I915_READ(PCH_ADPA);
270+ save_adpa = adpa = I915_READ(crt->adpa_reg);
271271 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
272272
273273 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
274274 if (turn_off_dac)
275275 adpa &= ~ADPA_DAC_ENABLE;
276276
277− I915_WRITE(PCH_ADPA, adpa);
277+ I915_WRITE(crt->adpa_reg, adpa);
278278
279− if (wait_for((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
279+ if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
280280 1000))
281281 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
282282
283283 if (turn_off_dac) {
284− I915_WRITE(PCH_ADPA, save_adpa);
285− POSTING_READ(PCH_ADPA);
284+ I915_WRITE(crt->adpa_reg, save_adpa);
285+ POSTING_READ(crt->adpa_reg);
286286 }
287287 }
288288
289289 /* Check the status to see if both blue and green are on now */
290− adpa = I915_READ(PCH_ADPA);
290+ adpa = I915_READ(crt->adpa_reg);
291291 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
292292 ret = true;
293293 else
@@ -300,26 +300,27 @@ static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) · 6 unmodified lines
300300 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
301301 {
302302 struct drm_device *dev = connector->dev;
303+ struct intel_crt *crt = intel_attached_crt(connector);
303304 struct drm_i915_private *dev_priv = dev->dev_private;
304305 u32 adpa;
305306 bool ret;
306307 u32 save_adpa;
307308
308− save_adpa = adpa = I915_READ(ADPA);
309+ save_adpa = adpa = I915_READ(crt->adpa_reg);
309310 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
310311
311312 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
312313
313− I915_WRITE(ADPA, adpa);
314+ I915_WRITE(crt->adpa_reg, adpa);
314315
315− if (wait_for((I915_READ(ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
316+ if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
316317 1000)) {
317318 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
318− I915_WRITE(ADPA, save_adpa);
319+ I915_WRITE(crt->adpa_reg, save_adpa);
319320 }
320321
321322 /* Check the status to see if both blue and green are on now */
322− adpa = I915_READ(ADPA);
323+ adpa = I915_READ(crt->adpa_reg);
323324 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
324325 ret = true;
325326 else
@@ -665,11 +666,11 @@ static void intel_crt_reset(struct drm_connector *connector) · 339 unmodified lines
665666 if (HAS_PCH_SPLIT(dev)) {
666667 u32 adpa;
667668
668− adpa = I915_READ(PCH_ADPA);
669+ adpa = I915_READ(crt->adpa_reg);
669670 adpa &= ~ADPA_CRT_HOTPLUG_MASK;
670671 adpa |= ADPA_HOTPLUG_BITS;
671− I915_WRITE(PCH_ADPA, adpa);
672− POSTING_READ(PCH_ADPA);
672+ I915_WRITE(crt->adpa_reg, adpa);
673+ POSTING_READ(crt->adpa_reg);
673674
674675 DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa);
675676 crt->force_hotplug_required = 1;
drivers/gpu/drm/i915/intel_ddi.c+28−1
@@ -677,6 +677,7 @@ static void intel_ddi_mode_set(struct drm_encoder *encoder, · 676 unmodified lines
677677 DRM_DEBUG_KMS("Preparing DDI mode for Haswell on port %c, pipe %c\n",
678678 port_name(port), pipe_name(pipe));
679679
680+ intel_crtc->eld_vld = false;
680681 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
681682 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
682683
@@ -987,7 +988,13 @@ void intel_ddi_enable_pipe_func(struct drm_crtc *crtc) · 304 unmodified lines
987988 if (cpu_transcoder == TRANSCODER_EDP) {
988989 switch (pipe) {
989990 case PIPE_A:
990− temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
991+ /* Can only use the always-on power well for eDP when
992+ * not using the panel fitter, and when not using motion
993+ * blur mitigation (which we don't support). */
994+ if (dev_priv->pch_pf_size)
995+ temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
996+ else
997+ temp |= TRANS_DDI_EDP_INPUT_A_ON;
991998 break;
992999 case PIPE_B:
9931000 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
@@ -1287,10 +1294,14 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder) · 293 unmodified lines
12871294 static void intel_enable_ddi(struct intel_encoder *intel_encoder)
12881295 {
12891296 struct drm_encoder *encoder = &intel_encoder->base;
1297+ struct drm_crtc *crtc = encoder->crtc;
1298+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1299+ int pipe = intel_crtc->pipe;
12901300 struct drm_device *dev = encoder->dev;
12911301 struct drm_i915_private *dev_priv = dev->dev_private;
12921302 enum port port = intel_ddi_get_encoder_port(intel_encoder);
12931303 int type = intel_encoder->type;
1304+ uint32_t tmp;
12941305
12951306 if (type == INTEL_OUTPUT_HDMI) {
12961307 /* In HDMI/DVI mode, the port width, and swing/emphasis values
@@ -1303,18 +1314,34 @@ static void intel_enable_ddi(struct intel_encoder *intel_encoder) · 6 unmodified lines
13031314
13041315 ironlake_edp_backlight_on(intel_dp);
13051316 }
1317+
1318+ if (intel_crtc->eld_vld) {
1319+ tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1320+ tmp |= ((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4));
1321+ I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
1322+ }
13061323 }
13071324
13081325 static void intel_disable_ddi(struct intel_encoder *intel_encoder)
13091326 {
13101327 struct drm_encoder *encoder = &intel_encoder->base;
1328+ struct drm_crtc *crtc = encoder->crtc;
1329+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1330+ int pipe = intel_crtc->pipe;
13111331 int type = intel_encoder->type;
1332+ struct drm_device *dev = encoder->dev;
1333+ struct drm_i915_private *dev_priv = dev->dev_private;
1334+ uint32_t tmp;
13121335
13131336 if (type == INTEL_OUTPUT_EDP) {
13141337 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
13151338
13161339 ironlake_edp_backlight_off(intel_dp);
13171340 }
1341+
1342+ tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1343+ tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4));
1344+ I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
13181345 }
13191346
13201347 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
drivers/gpu/drm/i915/intel_display.c+91−53
@@ -1214,9 +1214,15 @@ void assert_pipe(struct drm_i915_private *dev_priv, · 1213 unmodified lines
12141214 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
12151215 state = true;
12161216
1217− reg = PIPECONF(cpu_transcoder);
1218− val = I915_READ(reg);
1219− cur_state = !!(val & PIPECONF_ENABLE);
1217+ if (IS_HASWELL(dev_priv->dev) && cpu_transcoder != TRANSCODER_EDP &&
1218+ !(I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_ENABLE)) {
1219+ cur_state = false;
1220+ } else {
1221+ reg = PIPECONF(cpu_transcoder);
1222+ val = I915_READ(reg);
1223+ cur_state = !!(val & PIPECONF_ENABLE);
1224+ }
1225+
12201226 WARN(cur_state != state,
12211227 "pipe %c assertion failure (expected %s, current %s)\n",
12221228 pipe_name(pipe), state_string(state), state_string(cur_state));
@@ -2220,8 +2226,10 @@ intel_finish_fb(struct drm_framebuffer *old_fb) · 997 unmodified lines
22202226 bool was_interruptible = dev_priv->mm.interruptible;
22212227 int ret;
22222228
2229+ WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2230+
22232231 wait_event(dev_priv->pending_flip_queue,
2224− atomic_read(&dev_priv->mm.wedged) ||
2232+ i915_reset_in_progress(&dev_priv->gpu_error) ||
22252233 atomic_read(&obj->pending_flip) == 0);
22262234
22272235 /* Big Hammer, we also need to ensure that any pending
@@ -2869,7 +2877,7 @@ static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) · 641 unmodified lines
28692877 unsigned long flags;
28702878 bool pending;
28712879
2872− if (atomic_read(&dev_priv->mm.wedged))
2880+ if (i915_reset_in_progress(&dev_priv->gpu_error))
28732881 return false;
28742882
28752883 spin_lock_irqsave(&dev->event_lock, flags);
@@ -2887,6 +2895,8 @@ static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) · 11 unmodified lines
28872895 if (crtc->fb == NULL)
28882896 return;
28892897
2898+ WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2899+
28902900 wait_event(dev_priv->pending_flip_queue,
28912901 !intel_crtc_has_pending_flip(crtc));
28922902
@@ -3717,10 +3727,12 @@ static void intel_crtc_disable(struct drm_crtc *crtc) · 824 unmodified lines
37173727 struct drm_device *dev = crtc->dev;
37183728 struct drm_connector *connector;
37193729 struct drm_i915_private *dev_priv = dev->dev_private;
3730+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
37203731
37213732 /* crtc should still be enabled when we disable it. */
37223733 WARN_ON(!crtc->enabled);
37233734
3735+ intel_crtc->eld_vld = false;
37243736 dev_priv->display.crtc_disable(crtc);
37253737 intel_crtc_update_sarea(crtc, false);
37263738 dev_priv->display.off(crtc);
@@ -4867,6 +4879,8 @@ static void lpt_init_pch_refclk(struct drm_device *dev) · 1140 unmodified lines
48674879 if (!has_vga)
48684880 return;
48694881
4882+ mutex_lock(&dev_priv->dpio_lock);
4883+
48704884 /* XXX: Rip out SDV support once Haswell ships for real. */
48714885 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
48724886 is_sdv = true;
@@ -5009,6 +5023,8 @@ static void lpt_init_pch_refclk(struct drm_device *dev) · 136 unmodified lines
50095023 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
50105024 tmp |= SBI_DBUFF0_ENABLE;
50115025 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5026+
5027+ mutex_unlock(&dev_priv->dpio_lock);
50125028 }
50135029
50145030 /*
@@ -5092,6 +5108,11 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc, · 77 unmodified lines
50925108 else
50935109 val |= PIPECONF_PROGRESSIVE;
50945110
5111+ if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5112+ val |= PIPECONF_COLOR_RANGE_SELECT;
5113+ else
5114+ val &= ~PIPECONF_COLOR_RANGE_SELECT;
5115+
50955116 I915_WRITE(PIPECONF(pipe), val);
50965117 POSTING_READ(PIPECONF(pipe));
50975118 }
@@ -5586,6 +5607,35 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, · 488 unmodified lines
55865607 return fdi_config_ok ? ret : -EINVAL;
55875608 }
55885609
5610+static void haswell_modeset_global_resources(struct drm_device *dev)
5611+{
5612+ struct drm_i915_private *dev_priv = dev->dev_private;
5613+ bool enable = false;
5614+ struct intel_crtc *crtc;
5615+ struct intel_encoder *encoder;
5616+
5617+ list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5618+ if (crtc->pipe != PIPE_A && crtc->base.enabled)
5619+ enable = true;
5620+ /* XXX: Should check for edp transcoder here, but thanks to init
5621+ * sequence that's not yet available. Just in case desktop eDP
5622+ * on PORT D is possible on haswell, too. */
5623+ }
5624+
5625+ list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5626+ base.head) {
5627+ if (encoder->type != INTEL_OUTPUT_EDP &&
5628+ encoder->connectors_active)
5629+ enable = true;
5630+ }
5631+
5632+ /* Even the eDP panel fitter is outside the always-on well. */
5633+ if (dev_priv->pch_pf_size)
5634+ enable = true;
5635+
5636+ intel_set_power_well(dev, enable);
5637+}
5638+
55895639 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
55905640 struct drm_display_mode *mode,
55915641 struct drm_display_mode *adjusted_mode,
@@ -5618,11 +5668,6 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc, · 26 unmodified lines
56185668 num_connectors++;
56195669 }
56205670
5621− if (is_cpu_edp)
5622− intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5623− else
5624− intel_crtc->cpu_transcoder = pipe;
5625−
56265671 /* We are not sure yet this won't happen. */
56275672 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
56285673 INTEL_PCH_TYPE(dev));
@@ -5687,6 +5732,11 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, · 58 unmodified lines
56875732 int pipe = intel_crtc->pipe;
56885733 int ret;
56895734
5735+ if (IS_HASWELL(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5736+ intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5737+ else
5738+ intel_crtc->cpu_transcoder = pipe;
5739+
56905740 drm_vblank_pre_modeset(dev, pipe);
56915741
56925742 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
@@ -5783,6 +5833,7 @@ static void haswell_write_eld(struct drm_connector *connector, · 90 unmodified lines
57835833 struct drm_i915_private *dev_priv = connector->dev->dev_private;
57845834 uint8_t *eld = connector->eld;
57855835 struct drm_device *dev = crtc->dev;
5836+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
57865837 uint32_t eldv;
57875838 uint32_t i;
57885839 int len;
@@ -5824,6 +5875,7 @@ static void haswell_write_eld(struct drm_connector *connector, · 35 unmodified lines
58245875 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
58255876
58265877 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5878+ intel_crtc->eld_vld = true;
58275879
58285880 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
58295881 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
@@ -6717,11 +6769,6 @@ void intel_mark_busy(struct drm_device *dev) · 887 unmodified lines
67176769
67186770 void intel_mark_idle(struct drm_device *dev)
67196771 {
6720−}
6721−
6722−void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6723−{
6724− struct drm_device *dev = obj->base.dev;
67256772 struct drm_crtc *crtc;
67266773
67276774 if (!i915_powersave)
@@ -6731,12 +6778,11 @@ void intel_mark_fb_busy(struct drm_i915_gem_object *obj) · 3 unmodified lines
67316778 if (!crtc->fb)
67326779 continue;
67336780
6734− if (to_intel_framebuffer(crtc->fb)->obj == obj)
6735− intel_increase_pllclock(crtc);
6781+ intel_decrease_pllclock(crtc);
67366782 }
67376783 }
67386784
6739−void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6785+void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
67406786 {
67416787 struct drm_device *dev = obj->base.dev;
67426788 struct drm_crtc *crtc;
@@ -6749,7 +6795,7 @@ void intel_mark_fb_idle(struct drm_i915_gem_object *obj) · 6 unmodified lines
67496795 continue;
67506796
67516797 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6752− intel_decrease_pllclock(crtc);
6798+ intel_increase_pllclock(crtc);
67536799 }
67546800 }
67556801
@@ -6833,7 +6879,7 @@ static void do_intel_finish_page_flip(struct drm_device *dev, · 77 unmodified lines
68336879
68346880 obj = work->old_fb_obj;
68356881
6836− wake_up(&dev_priv->pending_flip_queue);
6882+ wake_up_all(&dev_priv->pending_flip_queue);
68376883
68386884 queue_work(dev_priv->wq, &work->work);
68396885
@@ -8219,23 +8265,18 @@ static void intel_setup_outputs(struct drm_device *dev) · 1379 unmodified lines
82198265 if (I915_READ(PCH_DP_D) & DP_DETECTED)
82208266 intel_dp_init(dev, PCH_DP_D, PORT_D);
82218267 } else if (IS_VALLEYVIEW(dev)) {
8222− int found;
8223−
82248268 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8225− if (I915_READ(DP_C) & DP_DETECTED)
8226− intel_dp_init(dev, DP_C, PORT_C);
8269+ if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8270+ intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
82278271
8228− if (I915_READ(SDVOB) & PORT_DETECTED) {
8229− /* SDVOB multiplex with HDMIB */
8230− found = intel_sdvo_init(dev, SDVOB, true);
8231− if (!found)
8232− intel_hdmi_init(dev, SDVOB, PORT_B);
8233− if (!found && (I915_READ(DP_B) & DP_DETECTED))
8234− intel_dp_init(dev, DP_B, PORT_B);
8272+ if (I915_READ(VLV_DISPLAY_BASE + SDVOB) & PORT_DETECTED) {
8273+ intel_hdmi_init(dev, VLV_DISPLAY_BASE + SDVOB, PORT_B);
8274+ if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8275+ intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
82358276 }
82368277
8237− if (I915_READ(SDVOC) & PORT_DETECTED)
8238− intel_hdmi_init(dev, SDVOC, PORT_C);
8278+ if (I915_READ(VLV_DISPLAY_BASE + SDVOC) & PORT_DETECTED)
8279+ intel_hdmi_init(dev, VLV_DISPLAY_BASE + SDVOC, PORT_C);
82398280
82408281 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
82418282 bool found = false;
@@ -8495,6 +8536,8 @@ static void intel_init_display(struct drm_device *dev) · 253 unmodified lines
84958536 } else if (IS_HASWELL(dev)) {
84968537 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
84978538 dev_priv->display.write_eld = haswell_write_eld;
8539+ dev_priv->display.modeset_global_resources =
8540+ haswell_modeset_global_resources;
84988541 }
84998542 } else if (IS_G4X(dev)) {
85008543 dev_priv->display.write_eld = g4x_write_eld;
@@ -8617,6 +8660,15 @@ static struct intel_quirk intel_quirks[] = { · 116 unmodified lines
86178660
86188661 /* Acer Aspire 5734Z must invert backlight brightness */
86198662 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8663+
8664+ /* Acer/eMachines G725 */
8665+ { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
8666+
8667+ /* Acer/eMachines e725 */
8668+ { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
8669+
8670+ /* Acer/Packard Bell NCL20 */
8671+ { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
86208672 };
86218673
86228674 static void intel_init_quirks(struct drm_device *dev)
@@ -8645,12 +8697,7 @@ static void i915_disable_vga(struct drm_device *dev) · 22 unmodified lines
86458697 {
86468698 struct drm_i915_private *dev_priv = dev->dev_private;
86478699 u8 sr1;
8648− u32 vga_reg;
8649−
8650− if (HAS_PCH_SPLIT(dev))
8651− vga_reg = CPU_VGACNTRL;
8652− else
8653− vga_reg = VGACNTRL;
8700+ u32 vga_reg = i915_vgacntrl_reg(dev);
86548701
86558702 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
86568703 outb(SR01, VGA_SR_INDEX);
@@ -8665,10 +8712,7 @@ static void i915_disable_vga(struct drm_device *dev) · 8 unmodified lines
86658712
86668713 void intel_modeset_init_hw(struct drm_device *dev)
86678714 {
8668− /* We attempt to init the necessary power wells early in the initialization
8669− * time, so the subsystems that expect power to be enabled can work.
8670− */
8671− intel_init_power_wells(dev);
8715+ intel_init_power_well(dev);
86728716
86738717 intel_prepare_ddi(dev);
86748718
@@ -8710,7 +8754,7 @@ void intel_modeset_init(struct drm_device *dev) · 35 unmodified lines
87108754 dev->mode_config.max_width = 8192;
87118755 dev->mode_config.max_height = 8192;
87128756 }
8713− dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
8757+ dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
87148758
87158759 DRM_DEBUG_KMS("%d display pipe%s available.\n",
87168760 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
@@ -8912,20 +8956,14 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder) · 195 unmodified lines
89128956 * the crtc fixup. */
89138957 }
89148958
8915−static void i915_redisable_vga(struct drm_device *dev)
8959+void i915_redisable_vga(struct drm_device *dev)
89168960 {
89178961 struct drm_i915_private *dev_priv = dev->dev_private;
8918− u32 vga_reg;
8919−
8920− if (HAS_PCH_SPLIT(dev))
8921− vga_reg = CPU_VGACNTRL;
8922− else
8923− vga_reg = VGACNTRL;
8962+ u32 vga_reg = i915_vgacntrl_reg(dev);
89248963
89258964 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
89268965 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
8927− I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8928− POSTING_READ(vga_reg);
8966+ i915_disable_vga(dev);
89298967 }
89308968 }
89318969
drivers/gpu/drm/i915/intel_dp.c+49−15
@@ -763,6 +763,22 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, · 762 unmodified lines
763763 return false;
764764
765765 bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
766+
767+ if (intel_dp->color_range_auto) {
768+ /*
769+ * See:
770+ * CEA-861-E - 5.1 Default Encoding Parameters
771+ * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
772+ */
773+ if (bpp != 18 && drm_mode_cea_vic(adjusted_mode) > 1)
774+ intel_dp->color_range = DP_COLOR_RANGE_16_235;
775+ else
776+ intel_dp->color_range = 0;
777+ }
778+
779+ if (intel_dp->color_range)
780+ adjusted_mode->private_flags |= INTEL_MODE_LIMITED_COLOR_RANGE;
781+
766782 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
767783
768784 for (clock = 0; clock <= max_clock; clock++) {
@@ -967,7 +983,8 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, · 198 unmodified lines
967983 else
968984 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
969985 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
970− intel_dp->DP |= intel_dp->color_range;
986+ if (!HAS_PCH_SPLIT(dev))
987+ intel_dp->DP |= intel_dp->color_range;
971988
972989 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
973990 intel_dp->DP |= DP_SYNC_HS_HIGH;
@@ -1770,14 +1787,18 @@ intel_dp_set_link_train(struct intel_dp *intel_dp, · 796 unmodified lines
17701787 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
17711788 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
17721789 case DP_TRAINING_PATTERN_DISABLE:
1773− temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
1774− I915_WRITE(DP_TP_CTL(port), temp);
17751790
1776− if (wait_for((I915_READ(DP_TP_STATUS(port)) &
1777− DP_TP_STATUS_IDLE_DONE), 1))
1778− DRM_ERROR("Timed out waiting for DP idle patterns\n");
1791+ if (port != PORT_A) {
1792+ temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
1793+ I915_WRITE(DP_TP_CTL(port), temp);
1794+
1795+ if (wait_for((I915_READ(DP_TP_STATUS(port)) &
1796+ DP_TP_STATUS_IDLE_DONE), 1))
1797+ DRM_ERROR("Timed out waiting for DP idle patterns\n");
1798+
1799+ temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1800+ }
17791801
1780− temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
17811802 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
17821803
17831804 break;
@@ -2276,16 +2297,17 @@ g4x_dp_detect(struct intel_dp *intel_dp) · 492 unmodified lines
22762297 {
22772298 struct drm_device *dev = intel_dp_to_dev(intel_dp);
22782299 struct drm_i915_private *dev_priv = dev->dev_private;
2300+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
22792301 uint32_t bit;
22802302
2281− switch (intel_dp->output_reg) {
2282− case DP_B:
2303+ switch (intel_dig_port->port) {
2304+ case PORT_B:
22832305 bit = DPB_HOTPLUG_LIVE_STATUS;
22842306 break;
2285− case DP_C:
2307+ case PORT_C:
22862308 bit = DPC_HOTPLUG_LIVE_STATUS;
22872309 break;
2288− case DP_D:
2310+ case PORT_D:
22892311 bit = DPD_HOTPLUG_LIVE_STATUS;
22902312 break;
22912313 default:
@@ -2459,10 +2481,21 @@ intel_dp_set_property(struct drm_connector *connector, · 167 unmodified lines
24592481 }
24602482
24612483 if (property == dev_priv->broadcast_rgb_property) {
2462− if (val == !!intel_dp->color_range)
2463− return 0;
2464−
2465− intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2484+ switch (val) {
2485+ case INTEL_BROADCAST_RGB_AUTO:
2486+ intel_dp->color_range_auto = true;
2487+ break;
2488+ case INTEL_BROADCAST_RGB_FULL:
2489+ intel_dp->color_range_auto = false;
2490+ intel_dp->color_range = 0;
2491+ break;
2492+ case INTEL_BROADCAST_RGB_LIMITED:
2493+ intel_dp->color_range_auto = false;
2494+ intel_dp->color_range = DP_COLOR_RANGE_16_235;
2495+ break;
2496+ default:
2497+ return -EINVAL;
2498+ }
24662499 goto done;
24672500 }
24682501
@@ -2603,6 +2636,7 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connect · 134 unmodified lines
26032636
26042637 intel_attach_force_audio_property(connector);
26052638 intel_attach_broadcast_rgb_property(connector);
2639+ intel_dp->color_range_auto = true;
26062640
26072641 if (is_edp(intel_dp)) {
26082642 drm_mode_create_scaling_mode_property(connector->dev);
drivers/gpu/drm/i915/intel_drv.h+15−3
@@ -109,6 +109,11 @@ · 108 unmodified lines
109109 * timings in the mode to prevent the crtc fixup from overwriting them.
110110 * Currently only lvds needs that. */
111111 #define INTEL_MODE_CRTC_TIMINGS_SET (0x20)
112+/*
113+ * Set when limited 16-235 (as opposed to full 0-255) RGB color range is
114+ * to be used.
115+ */
116+#define INTEL_MODE_LIMITED_COLOR_RANGE (0x40)
112117
113118 static inline void
114119 intel_mode_set_pixel_multiplier(struct drm_display_mode *mode,
@@ -206,6 +211,7 @@ struct intel_crtc { · 91 unmodified lines
206211 * some outputs connected to this crtc.
207212 */
208213 bool active;
214+ bool eld_vld;
209215 bool primary_disabled; /* is the crtc obscured by a plane? */
210216 bool lowfreq_avail;
211217 struct intel_overlay *overlay;
@@ -284,6 +290,9 @@ struct cxsr_latency { · 72 unmodified lines
284290 #define DIP_LEN_AVI 13
285291 #define DIP_AVI_PR_1 0
286292 #define DIP_AVI_PR_2 1
293+#define DIP_AVI_RGB_QUANT_RANGE_DEFAULT (0 << 2)
294+#define DIP_AVI_RGB_QUANT_RANGE_LIMITED (1 << 2)
295+#define DIP_AVI_RGB_QUANT_RANGE_FULL (2 << 2)
287296
288297 #define DIP_TYPE_SPD 0x83
289298 #define DIP_VERSION_SPD 0x1
@@ -338,9 +347,11 @@ struct intel_hdmi { · 48 unmodified lines
338347 u32 sdvox_reg;
339348 int ddc_bus;
340349 uint32_t color_range;
350+ bool color_range_auto;
341351 bool has_hdmi_sink;
342352 bool has_audio;
343353 enum hdmi_force_audio force_audio;
354+ bool rgb_quant_range_selectable;
344355 void (*write_infoframe)(struct drm_encoder *encoder,
345356 struct dip_infoframe *frame);
346357 void (*set_infoframes)(struct drm_encoder *encoder,
@@ -357,6 +368,7 @@ struct intel_dp { · 10 unmodified lines
357368 bool has_audio;
358369 enum hdmi_force_audio force_audio;
359370 uint32_t color_range;
371+ bool color_range_auto;
360372 uint8_t link_bw;
361373 uint8_t lane_count;
362374 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
@@ -440,9 +452,8 @@ extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, · 77 unmodified lines
440452 extern void intel_dvo_init(struct drm_device *dev);
441453 extern void intel_tv_init(struct drm_device *dev);
442454 extern void intel_mark_busy(struct drm_device *dev);
443−extern void intel_mark_idle(struct drm_device *dev);
444455 extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj);
445−extern void intel_mark_fb_idle(struct drm_i915_gem_object *obj);
456+extern void intel_mark_idle(struct drm_device *dev);
446457 extern bool intel_lvds_init(struct drm_device *dev);
447458 extern bool intel_is_dual_link_lvds(struct drm_device *dev);
448459 extern void intel_dp_init(struct drm_device *dev, int output_reg,
@@ -655,7 +666,8 @@ extern void intel_update_fbc(struct drm_device *dev); · 206 unmodified lines
655666 extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
656667 extern void intel_gpu_ips_teardown(void);
657668
658−extern void intel_init_power_wells(struct drm_device *dev);
669+extern void intel_init_power_well(struct drm_device *dev);
670+extern void intel_set_power_well(struct drm_device *dev, bool enable);
659671 extern void intel_enable_gt_powersave(struct drm_device *dev);
660672 extern void intel_disable_gt_powersave(struct drm_device *dev);
661673 extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv);
drivers/gpu/drm/i915/intel_fb.c+4−4
@@ -135,14 +135,13 @@ static int intelfb_create(struct intel_fbdev *ifbdev, · 134 unmodified lines
135135 goto out_unpin;
136136 }
137137 info->apertures->ranges[0].base = dev->mode_config.fb_base;
138− info->apertures->ranges[0].size =
139− dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
138+ info->apertures->ranges[0].size = dev_priv->gtt.mappable_end;
140139
141140 info->fix.smem_start = dev->mode_config.fb_base + obj->gtt_offset;
142141 info->fix.smem_len = size;
143142
144143 info->screen_base =
145− ioremap_wc(dev_priv->mm.gtt_base_addr + obj->gtt_offset,
144+ ioremap_wc(dev_priv->gtt.mappable_base + obj->gtt_offset,
146145 size);
147146 if (!info->screen_base) {
148147 ret = -ENOSPC;
@@ -306,7 +305,8 @@ void intel_fb_restore_mode(struct drm_device *dev) · 157 unmodified lines
306305
307306 /* Be sure to shut off any planes that may be active */
308307 list_for_each_entry(plane, &config->plane_list, head)
309− plane->funcs->disable_plane(plane);
308+ if (plane->enabled)
309+ plane->funcs->disable_plane(plane);
310310
311311 drm_modeset_unlock_all(dev);
312312 }
drivers/gpu/drm/i915/intel_hdmi.c+56−16
@@ -331,6 +331,7 @@ static void intel_set_infoframe(struct drm_encoder *encoder, · 330 unmodified lines
331331 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
332332 struct drm_display_mode *adjusted_mode)
333333 {
334+ struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
334335 struct dip_infoframe avi_if = {
335336 .type = DIP_TYPE_AVI,
336337 .ver = DIP_VERSION_AVI,
@@ -340,6 +341,13 @@ static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, · 3 unmodified lines
340341 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
341342 avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2;
342343
344+ if (intel_hdmi->rgb_quant_range_selectable) {
345+ if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
346+ avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_LIMITED;
347+ else
348+ avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_FULL;
349+ }
350+
343351 avi_if.body.avi.VIC = drm_mode_cea_vic(adjusted_mode);
344352
345353 intel_set_infoframe(encoder, &avi_if);
@@ -364,7 +372,8 @@ static void g4x_set_infoframes(struct drm_encoder *encoder, · 18 unmodified lines
364372 struct drm_display_mode *adjusted_mode)
365373 {
366374 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
367− struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
375+ struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
376+ struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
368377 u32 reg = VIDEO_DIP_CTL;
369378 u32 val = I915_READ(reg);
370379 u32 port;
@@ -391,11 +400,11 @@ static void g4x_set_infoframes(struct drm_encoder *encoder, · 20 unmodified lines
391400 return;
392401 }
393402
394− switch (intel_hdmi->sdvox_reg) {
395− case SDVOB:
403+ switch (intel_dig_port->port) {
404+ case PORT_B:
396405 port = VIDEO_DIP_PORT_B;
397406 break;
398− case SDVOC:
407+ case PORT_C:
399408 port = VIDEO_DIP_PORT_C;
400409 break;
401410 default:
@@ -428,7 +437,8 @@ static void ibx_set_infoframes(struct drm_encoder *encoder, · 26 unmodified lines
428437 {
429438 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
430439 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
431− struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
440+ struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
441+ struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
432442 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
433443 u32 val = I915_READ(reg);
434444 u32 port;
@@ -447,14 +457,14 @@ static void ibx_set_infoframes(struct drm_encoder *encoder, · 12 unmodified lines
447457 return;
448458 }
449459
450− switch (intel_hdmi->sdvox_reg) {
451− case HDMIB:
460+ switch (intel_dig_port->port) {
461+ case PORT_B:
452462 port = VIDEO_DIP_PORT_B;
453463 break;
454− case HDMIC:
464+ case PORT_C:
455465 port = VIDEO_DIP_PORT_C;
456466 break;
457− case HDMID:
467+ case PORT_D:
458468 port = VIDEO_DIP_PORT_D;
459469 break;
460470 default:
@@ -766,6 +776,20 @@ bool intel_hdmi_mode_fixup(struct drm_encoder *encoder, · 305 unmodified lines
766776 const struct drm_display_mode *mode,
767777 struct drm_display_mode *adjusted_mode)
768778 {
779+ struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
780+
781+ if (intel_hdmi->color_range_auto) {
782+ /* See CEA-861-E - 5.1 Default Encoding Parameters */
783+ if (intel_hdmi->has_hdmi_sink &&
784+ drm_mode_cea_vic(adjusted_mode) > 1)
785+ intel_hdmi->color_range = SDVO_COLOR_RANGE_16_235;
786+ else
787+ intel_hdmi->color_range = 0;
788+ }
789+
790+ if (intel_hdmi->color_range)
791+ adjusted_mode->private_flags |= INTEL_MODE_LIMITED_COLOR_RANGE;
792+
769793 return true;
770794 }
771795
@@ -773,13 +797,14 @@ static bool g4x_hdmi_connected(struct intel_hdmi *intel_hdmi) · 1 unmodified line
773797 {
774798 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
775799 struct drm_i915_private *dev_priv = dev->dev_private;
800+ struct intel_digital_port *intel_dig_port = hdmi_to_dig_port(intel_hdmi);
776801 uint32_t bit;
777802
778− switch (intel_hdmi->sdvox_reg) {
779− case SDVOB:
803+ switch (intel_dig_port->port) {
804+ case PORT_B:
780805 bit = HDMIB_HOTPLUG_LIVE_STATUS;
781806 break;
782− case SDVOC:
807+ case PORT_C:
783808 bit = HDMIC_HOTPLUG_LIVE_STATUS;
784809 break;
785810 default:
@@ -811,6 +836,7 @@ intel_hdmi_detect(struct drm_connector *connector, bool force) · 25 unmodified lines
811836
812837 intel_hdmi->has_hdmi_sink = false;
813838 intel_hdmi->has_audio = false;
839+ intel_hdmi->rgb_quant_range_selectable = false;
814840 edid = drm_get_edid(connector,
815841 intel_gmbus_get_adapter(dev_priv,
816842 intel_hdmi->ddc_bus));
@@ -822,6 +848,8 @@ intel_hdmi_detect(struct drm_connector *connector, bool force) · 5 unmodified lines
822848 intel_hdmi->has_hdmi_sink =
823849 drm_detect_hdmi_monitor(edid);
824850 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
851+ intel_hdmi->rgb_quant_range_selectable =
852+ drm_rgb_quant_range_selectable(edid);
825853 }
826854 kfree(edid);
827855 }
@@ -907,10 +935,21 @@ intel_hdmi_set_property(struct drm_connector *connector, · 79 unmodified lines
907935 }
908936
909937 if (property == dev_priv->broadcast_rgb_property) {
910− if (val == !!intel_hdmi->color_range)
911− return 0;
912−
913− intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
938+ switch (val) {
939+ case INTEL_BROADCAST_RGB_AUTO:
940+ intel_hdmi->color_range_auto = true;
941+ break;
942+ case INTEL_BROADCAST_RGB_FULL:
943+ intel_hdmi->color_range_auto = false;
944+ intel_hdmi->color_range = 0;
945+ break;
946+ case INTEL_BROADCAST_RGB_LIMITED:
947+ intel_hdmi->color_range_auto = false;
948+ intel_hdmi->color_range = SDVO_COLOR_RANGE_16_235;
949+ break;
950+ default:
951+ return -EINVAL;
952+ }
914953 goto done;
915954 }
916955
@@ -959,6 +998,7 @@ intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *c · 42 unmodified lines
959998 {
960999 intel_attach_force_audio_property(connector);
9611000 intel_attach_broadcast_rgb_property(connector);
1001+ intel_hdmi->color_range_auto = true;
9621002 }
9631003
9641004 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
drivers/gpu/drm/i915/intel_i2c.c+2−0
@@ -515,6 +515,8 @@ int intel_setup_gmbus(struct drm_device *dev) · 514 unmodified lines
515515
516516 if (HAS_PCH_SPLIT(dev))
517517 dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;
518+ else if (IS_VALLEYVIEW(dev))
519+ dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
518520 else
519521 dev_priv->gpio_mmio_base = 0;
520522
drivers/gpu/drm/i915/intel_modes.c+3−2
@@ -100,8 +100,9 @@ intel_attach_force_audio_property(struct drm_connector *connector) · 99 unmodified lines
100100 }
101101
102102 static const struct drm_prop_enum_list broadcast_rgb_names[] = {
103− { 0, "Full" },
104− { 1, "Limited 16:235" },
103+ { INTEL_BROADCAST_RGB_AUTO, "Automatic" },
104+ { INTEL_BROADCAST_RGB_FULL, "Full" },
105+ { INTEL_BROADCAST_RGB_LIMITED, "Limited 16:235" },
105106 };
106107
107108 void
drivers/gpu/drm/i915/intel_opregion.c+1−1
@@ -347,7 +347,7 @@ static void intel_didl_outputs(struct drm_device *dev) · 346 unmodified lines
347347 int i = 0;
348348
349349 handle = DEVICE_ACPI_HANDLE(&dev->pdev->dev);
350− if (!handle || ACPI_FAILURE(acpi_bus_get_device(handle, &acpi_dev)))
350+ if (!handle || acpi_bus_get_device(handle, &acpi_dev))
351351 return;
352352
353353 if (acpi_is_video_device(acpi_dev))
drivers/gpu/drm/i915/intel_overlay.c+2−2
@@ -195,7 +195,7 @@ intel_overlay_map_regs(struct intel_overlay *overlay) · 194 unmodified lines
195195 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
196196 regs = (struct overlay_registers __iomem *)overlay->reg_bo->phys_obj->handle->vaddr;
197197 else
198− regs = io_mapping_map_wc(dev_priv->mm.gtt_mapping,
198+ regs = io_mapping_map_wc(dev_priv->gtt.mappable,
199199 overlay->reg_bo->gtt_offset);
200200
201201 return regs;
@@ -1434,7 +1434,7 @@ intel_overlay_map_regs_atomic(struct intel_overlay *overlay) · 1232 unmodified lines
14341434 regs = (struct overlay_registers __iomem *)
14351435 overlay->reg_bo->phys_obj->handle->vaddr;
14361436 else
1437− regs = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
1437+ regs = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
14381438 overlay->reg_bo->gtt_offset);
14391439
14401440 return regs;
drivers/gpu/drm/i915/intel_pm.c+44−18
@@ -3687,6 +3687,10 @@ static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) · 3686 unmodified lines
36873687 reg |= GEN7_FF_VS_SCHED_HW;
36883688 reg |= GEN7_FF_DS_SCHED_HW;
36893689
3690+ /* WaVSRefCountFullforceMissDisable */
3691+ if (IS_HASWELL(dev_priv->dev))
3692+ reg &= ~GEN7_FF_VS_REF_CNT_FFME;
3693+
36903694 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
36913695 }
36923696
@@ -4050,35 +4054,57 @@ void intel_init_clock_gating(struct drm_device *dev) · 357 unmodified lines
40504054 dev_priv->display.init_clock_gating(dev);
40514055 }
40524056
4053−/* Starting with Haswell, we have different power wells for
4054− * different parts of the GPU. This attempts to enable them all.
4055− */
4056−void intel_init_power_wells(struct drm_device *dev)
4057+void intel_set_power_well(struct drm_device *dev, bool enable)
40574058 {
40584059 struct drm_i915_private *dev_priv = dev->dev_private;
4059− unsigned long power_wells[] = {
4060− HSW_PWR_WELL_CTL1,
4061− HSW_PWR_WELL_CTL2,
4062− HSW_PWR_WELL_CTL4
4063− };
4064− int i;
4060+ bool is_enabled, enable_requested;
4061+ uint32_t tmp;
40654062
40664063 if (!IS_HASWELL(dev))
40674064 return;
40684065
4069− mutex_lock(&dev->struct_mutex);
4066+ tmp = I915_READ(HSW_PWR_WELL_DRIVER);
4067+ is_enabled = tmp & HSW_PWR_WELL_STATE;
4068+ enable_requested = tmp & HSW_PWR_WELL_ENABLE;
40704069
4071− for (i = 0; i < ARRAY_SIZE(power_wells); i++) {
4072− int well = I915_READ(power_wells[i]);
4070+ if (enable) {
4071+ if (!enable_requested)
4072+ I915_WRITE(HSW_PWR_WELL_DRIVER, HSW_PWR_WELL_ENABLE);
40734073
4074− if ((well & HSW_PWR_WELL_STATE) == 0) {
4075− I915_WRITE(power_wells[i], well & HSW_PWR_WELL_ENABLE);
4076− if (wait_for((I915_READ(power_wells[i]) & HSW_PWR_WELL_STATE), 20))
4077− DRM_ERROR("Error enabling power well %lx\n", power_wells[i]);
4074+ if (!is_enabled) {
4075+ DRM_DEBUG_KMS("Enabling power well\n");
4076+ if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
4077+ HSW_PWR_WELL_STATE), 20))
4078+ DRM_ERROR("Timeout enabling power well\n");
4079+ }
4080+ } else {
4081+ if (enable_requested) {
4082+ I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
4083+ DRM_DEBUG_KMS("Requesting to disable the power well\n");
40784084 }
40794085 }
4086+}
40804087
4081− mutex_unlock(&dev->struct_mutex);
4088+/*
4089+ * Starting with Haswell, we have a "Power Down Well" that can be turned off
4090+ * when not needed anymore. We have 4 registers that can request the power well
4091+ * to be enabled, and it will only be disabled if none of the registers is
4092+ * requesting it to be enabled.
4093+ */
4094+void intel_init_power_well(struct drm_device *dev)
4095+{
4096+ struct drm_i915_private *dev_priv = dev->dev_private;
4097+
4098+ if (!IS_HASWELL(dev))
4099+ return;
4100+
4101+ /* For now, we need the power well to be always enabled. */
4102+ intel_set_power_well(dev, true);
4103+
4104+ /* We're taking over the BIOS, so clear any requests made by it since
4105+ * the driver is in charge now. */
4106+ if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE)
4107+ I915_WRITE(HSW_PWR_WELL_BIOS, 0);
40824108 }
40834109
40844110 /* Set up chip specific power management-related functions */
drivers/gpu/drm/i915/intel_ringbuffer.c+6−6
@@ -1203,7 +1203,7 @@ static int intel_init_ring_buffer(struct drm_device *dev, · 1202 unmodified lines
12031203 goto err_unpin;
12041204
12051205 ring->virtual_start =
1206− ioremap_wc(dev_priv->mm.gtt->gma_bus_addr + obj->gtt_offset,
1206+ ioremap_wc(dev_priv->gtt.mappable_base + obj->gtt_offset,
12071207 ring->size);
12081208 if (ring->virtual_start == NULL) {
12091209 DRM_ERROR("Failed to map ringbuffer.\n");
@@ -1223,8 +1223,6 @@ static int intel_init_ring_buffer(struct drm_device *dev, · 13 unmodified lines
12231223 if (IS_I830(ring->dev) || IS_845G(ring->dev))
12241224 ring->effective_size -= 128;
12251225
1226− intel_ring_init_seqno(ring, dev_priv->last_seqno);
1227−
12281226 return 0;
12291227
12301228 err_unmap:
@@ -1371,7 +1369,8 @@ static int ring_wait_for_space(struct intel_ring_buffer *ring, int n) · 140 unmodified lines
13711369
13721370 msleep(1);
13731371
1374− ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible);
1372+ ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1373+ dev_priv->mm.interruptible);
13751374 if (ret)
13761375 return ret;
13771376 } while (!time_after(jiffies, end));
@@ -1460,7 +1459,8 @@ int intel_ring_begin(struct intel_ring_buffer *ring, · 82 unmodified lines
14601459 drm_i915_private_t *dev_priv = ring->dev->dev_private;
14611460 int ret;
14621461
1463− ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible);
1462+ ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1463+ dev_priv->mm.interruptible);
14641464 if (ret)
14651465 return ret;
14661466
@@ -1491,7 +1491,7 @@ void intel_ring_advance(struct intel_ring_buffer *ring) · 24 unmodified lines
14911491 struct drm_i915_private *dev_priv = ring->dev->dev_private;
14921492
14931493 ring->tail &= ring->size - 1;
1494− if (dev_priv->stop_rings & intel_ring_flag(ring))
1494+ if (dev_priv->gpu_error.stop_rings & intel_ring_flag(ring))
14951495 return;
14961496 ring->write_tail(ring, ring->tail);
14971497 }
drivers/gpu/drm/i915/intel_sdvo.c+49−10
@@ -103,6 +103,7 @@ struct intel_sdvo { · 102 unmodified lines
103103 * It is only valid when using TMDS encoding and 8 bit per color mode.
104104 */
105105 uint32_t color_range;
106+ bool color_range_auto;
106107
107108 /**
108109 * This is set if we're going to treat the device as TV-out.
@@ -125,6 +126,7 @@ struct intel_sdvo { · 16 unmodified lines
125126 bool is_hdmi;
126127 bool has_hdmi_monitor;
127128 bool has_hdmi_audio;
129+ bool rgb_quant_range_selectable;
128130
129131 /**
130132 * This is set if we detect output of sdvo device as LVDS and
@@ -946,7 +948,8 @@ static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo, · 815 unmodified lines
946948 &tx_rate, 1);
947949 }
948950
949−static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo)
951+static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
952+ const struct drm_display_mode *adjusted_mode)
950953 {
951954 struct dip_infoframe avi_if = {
952955 .type = DIP_TYPE_AVI,
@@ -955,6 +958,13 @@ static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo) · 2 unmodified lines
955958 };
956959 uint8_t sdvo_data[4 + sizeof(avi_if.body.avi)];
957960
961+ if (intel_sdvo->rgb_quant_range_selectable) {
962+ if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
963+ avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_LIMITED;
964+ else
965+ avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_FULL;
966+ }
967+
958968 intel_dip_infoframe_csum(&avi_if);
959969
960970 /* sdvo spec says that the ecc is handled by the hw, and it looks like
@@ -1064,6 +1074,18 @@ static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder, · 103 unmodified lines
10641074 multiplier = intel_sdvo_get_pixel_multiplier(adjusted_mode);
10651075 intel_mode_set_pixel_multiplier(adjusted_mode, multiplier);
10661076
1077+ if (intel_sdvo->color_range_auto) {
1078+ /* See CEA-861-E - 5.1 Default Encoding Parameters */
1079+ if (intel_sdvo->has_hdmi_monitor &&
1080+ drm_mode_cea_vic(adjusted_mode) > 1)
1081+ intel_sdvo->color_range = SDVO_COLOR_RANGE_16_235;
1082+ else
1083+ intel_sdvo->color_range = 0;
1084+ }
1085+
1086+ if (intel_sdvo->color_range)
1087+ adjusted_mode->private_flags |= INTEL_MODE_LIMITED_COLOR_RANGE;
1088+
10671089 return true;
10681090 }
10691091
@@ -1121,7 +1143,7 @@ static void intel_sdvo_mode_set(struct drm_encoder *encoder, · 51 unmodified lines
11211143 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
11221144 intel_sdvo_set_colorimetry(intel_sdvo,
11231145 SDVO_COLORIMETRY_RGB256);
1124− intel_sdvo_set_avi_infoframe(intel_sdvo);
1146+ intel_sdvo_set_avi_infoframe(intel_sdvo, adjusted_mode);
11251147 } else
11261148 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
11271149
@@ -1153,7 +1175,7 @@ static void intel_sdvo_mode_set(struct drm_encoder *encoder, · 25 unmodified lines
11531175 /* The real mode polarity is set by the SDVO commands, using
11541176 * struct intel_sdvo_dtd. */
11551177 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
1156− if (intel_sdvo->is_hdmi)
1178+ if (!HAS_PCH_SPLIT(dev) && intel_sdvo->is_hdmi)
11571179 sdvox |= intel_sdvo->color_range;
11581180 if (INTEL_INFO(dev)->gen < 5)
11591181 sdvox |= SDVO_BORDER_ENABLE;
@@ -1513,6 +1535,8 @@ intel_sdvo_tmds_sink_detect(struct drm_connector *connector) · 353 unmodified lines
15131535 if (intel_sdvo->is_hdmi) {
15141536 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
15151537 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
1538+ intel_sdvo->rgb_quant_range_selectable =
1539+ drm_rgb_quant_range_selectable(edid);
15161540 }
15171541 } else
15181542 status = connector_status_disconnected;
@@ -1564,6 +1588,7 @@ intel_sdvo_detect(struct drm_connector *connector, bool force) · 45 unmodified lines
15641588
15651589 intel_sdvo->has_hdmi_monitor = false;
15661590 intel_sdvo->has_hdmi_audio = false;
1591+ intel_sdvo->rgb_quant_range_selectable = false;
15671592
15681593 if ((intel_sdvo_connector->output_flag & response) == 0)
15691594 ret = connector_status_disconnected;
@@ -1897,10 +1922,21 @@ intel_sdvo_set_property(struct drm_connector *connector, · 327 unmodified lines
18971922 }
18981923
18991924 if (property == dev_priv->broadcast_rgb_property) {
1900− if (val == !!intel_sdvo->color_range)
1901− return 0;
1902−
1903− intel_sdvo->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
1925+ switch (val) {
1926+ case INTEL_BROADCAST_RGB_AUTO:
1927+ intel_sdvo->color_range_auto = true;
1928+ break;
1929+ case INTEL_BROADCAST_RGB_FULL:
1930+ intel_sdvo->color_range_auto = false;
1931+ intel_sdvo->color_range = 0;
1932+ break;
1933+ case INTEL_BROADCAST_RGB_LIMITED:
1934+ intel_sdvo->color_range_auto = false;
1935+ intel_sdvo->color_range = SDVO_COLOR_RANGE_16_235;
1936+ break;
1937+ default:
1938+ return -EINVAL;
1939+ }
19041940 goto done;
19051941 }
19061942
@@ -2197,13 +2233,16 @@ intel_sdvo_connector_init(struct intel_sdvo_connector *connector, · 290 unmodified lines
21972233 }
21982234
21992235 static void
2200−intel_sdvo_add_hdmi_properties(struct intel_sdvo_connector *connector)
2236+intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
2237+ struct intel_sdvo_connector *connector)
22012238 {
22022239 struct drm_device *dev = connector->base.base.dev;
22032240
22042241 intel_attach_force_audio_property(&connector->base.base);
2205− if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev))
2242+ if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) {
22062243 intel_attach_broadcast_rgb_property(&connector->base.base);
2244+ intel_sdvo->color_range_auto = true;
2245+ }
22072246 }
22082247
22092248 static bool
@@ -2251,7 +2290,7 @@ intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device) · 41 unmodified lines
22512290
22522291 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
22532292 if (intel_sdvo->is_hdmi)
2254− intel_sdvo_add_hdmi_properties(intel_sdvo_connector);
2293+ intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector);
22552294
22562295 return true;
22572296 }
include/drm/drm_crtc.h+1−0
@@ -1063,6 +1063,7 @@ extern u8 *drm_find_cea_extension(struct edid *edid); · 1062 unmodified lines
10631063 extern u8 drm_match_cea_mode(struct drm_display_mode *to_match);
10641064 extern bool drm_detect_hdmi_monitor(struct edid *edid);
10651065 extern bool drm_detect_monitor_audio(struct edid *edid);
1066+extern bool drm_rgb_quant_range_selectable(struct edid *edid);
10661067 extern int drm_mode_page_flip_ioctl(struct drm_device *dev,
10671068 void *data, struct drm_file *file_priv);
10681069 extern struct drm_display_mode *drm_cvt_mode(struct drm_device *dev,
include/drm/intel-gtt.h+1−18
@@ -3,24 +3,7 @@ · 2 unmodified lines
33 #ifndef _DRM_INTEL_GTT_H
44 #define _DRM_INTEL_GTT_H
55
6−struct intel_gtt {
7− /* Size of memory reserved for graphics by the BIOS */
8− unsigned int stolen_size;
9− /* Total number of gtt entries. */
10− unsigned int gtt_total_entries;
11− /* Part of the gtt that is mappable by the cpu, for those chips where
12− * this is not the full gtt. */
13− unsigned int gtt_mappable_entries;
14− /* Whether i915 needs to use the dmar apis or not. */
15− unsigned int needs_dmar : 1;
16− /* Whether we idle the gpu before mapping/unmapping */
17− unsigned int do_idle_maps : 1;
18− /* Share the scratch page dma with ppgtts. */
19− dma_addr_t scratch_page_dma;
20− struct page *scratch_page;
21− /* needed for ioremap in drm/i915 */
22− phys_addr_t gma_bus_addr;
23−} *intel_gtt_get(void);
6+void intel_gtt_get(size_t *gtt_total, size_t *stolen_size);
247
258 int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev,
269 struct agp_bridge_data *bridge);
include/uapi/drm/i915_drm.h+20−0
@@ -308,6 +308,8 @@ typedef struct drm_i915_irq_wait { · 307 unmodified lines
308308 #define I915_PARAM_RSVD_FOR_FUTURE_USE 22
309309 #define I915_PARAM_HAS_SECURE_BATCHES 23
310310 #define I915_PARAM_HAS_PINNED_BATCHES 24
311+#define I915_PARAM_HAS_EXEC_NO_RELOC 25
312+#define I915_PARAM_HAS_EXEC_HANDLE_LUT 26
311313
312314 typedef struct drm_i915_getparam {
313315 int param;
@@ -628,7 +630,11 @@ struct drm_i915_gem_exec_object2 { · 314 unmodified lines
628630 __u64 offset;
629631
630632 #define EXEC_OBJECT_NEEDS_FENCE (1<<0)
633+#define EXEC_OBJECT_NEEDS_GTT (1<<1)
634+#define EXEC_OBJECT_WRITE (1<<2)
635+#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_WRITE<<1)
631636 __u64 flags;
637+
632638 __u64 rsvd1;
633639 __u64 rsvd2;
634640 };
@@ -687,6 +693,20 @@ struct drm_i915_gem_execbuffer2 { · 52 unmodified lines
687693 */
688694 #define I915_EXEC_IS_PINNED (1<<10)
689695
696+/** Provide a hint to the kernel that the command stream and auxilliary
697+ * state buffers already holds the correct presumed addresses and so the
698+ * relocation process may be skipped if no buffers need to be moved in
699+ * preparation for the execbuffer.
700+ */
701+#define I915_EXEC_NO_RELOC (1<<11)
702+
703+/** Use the reloc.handle as an index into the exec object array rather
704+ * than as the per-file handle.
705+ */
706+#define I915_EXEC_HANDLE_LUT (1<<12)
707+
708+#define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_HANDLE_LUT<<1)
709+
690710 #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
691711 #define i915_execbuffer2_set_context_id(eb2, context) \
692712 (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK