History

Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux

Pull drm fixes from Dave Airlie: "All over the map.. - nouveau: disable MSI, needs more work, will try again next merge window - radeon: audio + uvd regression fixes, dpm fixes, reset fixes - i915: the dpms fix might fix your haswell And one pain in the ass revert, so we have VGA arbitration that when implemented 4-5 years ago really hoped that GPUs could remove themselves from arbitration completely once they had a kernel driver. It seems Intel hw designers decided that was too nice a facility to allow us to have so they removed it when they went on-die (so since Ironlake at least). Now Alex Williamson added support for VGA arbitration for newer GPUs however this now exposes itself to userspace as requireing arbitration of GPU VGA regions and the X server gets involved and disables things that it can't handle when VGA access is possibly required around every operation. So in order to not break userspace we just reverted things back to the old known broken status so maybe we can try and design out way out. Ville also had a patch to use stop machine for the two times Intel needs to access VGA space, that might be acceptable with some rework, but for now myself and Daniel agreed to just go back" * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: (23 commits) Revert "i915: Update VGA arbiter support for newer devices" Revert "drm/i915: Delay disabling of VGA memory until vgacon->fbcon handoff is done" drm/radeon: re-enable sw ACR support on pre-DCE4 drm/radeon/dpm: disable bapm on TN asics drm/radeon: improve soft reset on CIK drm/radeon: improve soft reset on SI drm/radeon/dpm: off by one in si_set_mc_special_registers() drm/radeon/dpm/btc: off by one in btc_set_mc_special_registers() drm/radeon: forever loop on error in radeon_do_test_moves() drm/radeon: fix hw contexts for SUMO2 asics drm/radeon: fix typo in CP DMA register headers drm/radeon/dpm: disable multiple UVD states drm/radeon: use hw generated CTS/N values for audio drm/radeon: fix N/CTS clock matching for audio drm/radeon: use 64-bit math to calculate CTS values for audio (v2) drm/edid: catch kmalloc failure in drm_edid_to_speaker_allocation Revert "drm/fb-helper: don't sleep for screen unblank when an oops is in progress" drm/gma500: fix things after get/put page helpers drm/nouveau/mc: disable msi support by default, it's busted in tons of places drm/i915: Only apply DPMS to the encoder if enabled ...

Linus Torvalds committed 13 years ago

Commit cd4edf72 parents 2fe80d3 ebff5fa25 files · +74 −93Browse files

Unified · Split

25 files
  1. drivers/gpu/drm/drm_edid.c +2 −0
  2. drivers/gpu/drm/drm_fb_helper.c +0 −8
  3. drivers/gpu/drm/gma500/gtt.c +1 −0
  4. drivers/gpu/drm/i915/i915_dma.c +3 −12
  5. drivers/gpu/drm/i915/i915_reg.h +6 −0
  6. drivers/gpu/drm/i915/intel_display.c +2 −36
  7. drivers/gpu/drm/i915/intel_dp.c +1 −1
  8. drivers/gpu/drm/i915/intel_drv.h +0 −1
  9. drivers/gpu/drm/i915/intel_pm.c +7 −2
  10. drivers/gpu/drm/nouveau/core/subdev/mc/base.c +1 −1
  11. drivers/gpu/drm/radeon/btc_dpm.c +3 −3
  12. drivers/gpu/drm/radeon/cik.c +6 −0
  13. drivers/gpu/drm/radeon/evergreen.c +1 −1
  14. drivers/gpu/drm/radeon/evergreen_hdmi.c +1 −2
  15. drivers/gpu/drm/radeon/evergreend.h +2 −2
  16. drivers/gpu/drm/radeon/r600_hdmi.c +14 −7
  17. drivers/gpu/drm/radeon/r600d.h +1 −1
  18. drivers/gpu/drm/radeon/radeon_pm.c +3 −0
  19. drivers/gpu/drm/radeon/radeon_test.c +2 −2
  20. drivers/gpu/drm/radeon/radeon_uvd.c +2 −1
  21. drivers/gpu/drm/radeon/si.c +10 −0
  22. drivers/gpu/drm/radeon/si_dpm.c +3 −3
  23. drivers/gpu/drm/radeon/sid.h +2 −2
  24. drivers/gpu/drm/radeon/trinity_dpm.c +1 −1
  25. include/linux/vgaarb.h +0 −7
drivers/gpu/drm/drm_edid.c+2−0
@@ -2925,6 +2925,8 @@ int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) · 2924 unmodified lines
29252925 /* Speaker Allocation Data Block */
29262926 if (dbl == 3) {
29272927 *sadb = kmalloc(dbl, GFP_KERNEL);
2928+ if (!*sadb)
2929+ return -ENOMEM;
29282930 memcpy(*sadb, &db[1], dbl);
29292931 count = dbl;
29302932 break;
drivers/gpu/drm/drm_fb_helper.c+0−8
@@ -407,14 +407,6 @@ static void drm_fb_helper_dpms(struct fb_info *info, int dpms_mode) · 406 unmodified lines
407407 struct drm_connector *connector;
408408 int i, j;
409409
410− /*
411− * fbdev->blank can be called from irq context in case of a panic.
412− * Since we already have our own special panic handler which will
413− * restore the fbdev console mode completely, just bail out early.
414− */
415− if (oops_in_progress)
416− return;
417−
418410 /*
419411 * fbdev->blank can be called from irq context in case of a panic.
420412 * Since we already have our own special panic handler which will
drivers/gpu/drm/gma500/gtt.c+1−0
@@ -204,6 +204,7 @@ static int psb_gtt_attach_pages(struct gtt_range *gt) · 203 unmodified lines
204204 if (IS_ERR(pages))
205205 return PTR_ERR(pages);
206206
207+ gt->npage = gt->gem.size / PAGE_SIZE;
207208 gt->pages = pages;
208209
209210 return 0;
drivers/gpu/drm/i915/i915_dma.c+3−12
@@ -1290,12 +1290,9 @@ static int i915_load_modeset_init(struct drm_device *dev) · 1289 unmodified lines
12901290 * then we do not take part in VGA arbitration and the
12911291 * vga_client_register() fails with -ENODEV.
12921292 */
1293− if (!HAS_PCH_SPLIT(dev)) {
1294− ret = vga_client_register(dev->pdev, dev, NULL,
1295− i915_vga_set_decode);
1296− if (ret && ret != -ENODEV)
1297− goto out;
1298− }
1293+ ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1294+ if (ret && ret != -ENODEV)
1295+ goto out;
12991296
13001297 intel_register_dsm_handler();
13011298
@@ -1351,12 +1348,6 @@ static int i915_load_modeset_init(struct drm_device *dev) · 49 unmodified lines
13511348 */
13521349 intel_fbdev_initial_config(dev);
13531350
1354− /*
1355− * Must do this after fbcon init so that
1356− * vgacon_save_screen() works during the handover.
1357− */
1358− i915_disable_vga_mem(dev);
1359−
13601351 /* Only enable hotplug handling once the fbdev is fully set up. */
13611352 dev_priv->enable_hotplug_processing = true;
13621353
drivers/gpu/drm/i915/i915_reg.h+6−0
@@ -3881,6 +3881,9 @@ · 3880 unmodified lines
38813881 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030
38823882 #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11)
38833883
3884+#define HSW_SCRATCH1 0xb038
3885+#define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1<<27)
3886+
38843887 #define HSW_FUSE_STRAP 0x42014
38853888 #define HSW_CDCLK_LIMIT (1 << 24)
38863889
@@ -4728,6 +4731,9 @@ · 841 unmodified lines
47284731 #define GEN7_ROW_CHICKEN2_GT2 0xf4f4
47294732 #define DOP_CLOCK_GATING_DISABLE (1<<0)
47304733
4734+#define HSW_ROW_CHICKEN3 0xe49c
4735+#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
4736+
47314737 #define G4X_AUD_VID_DID (dev_priv->info->display_mmio_offset + 0x62020)
47324738 #define INTEL_AUDIO_DEVCL 0x808629FB
47334739 #define INTEL_AUDIO_DEVBLC 0x80862801
drivers/gpu/drm/i915/intel_display.c+2−36
@@ -3941,8 +3941,6 @@ static void intel_connector_check_state(struct intel_connector *connector) · 3940 unmodified lines
39413941 * consider. */
39423942 void intel_connector_dpms(struct drm_connector *connector, int mode)
39433943 {
3944− struct intel_encoder *encoder = intel_attached_encoder(connector);
3945−
39463944 /* All the simple cases only support two dpms states. */
39473945 if (mode != DRM_MODE_DPMS_ON)
39483946 mode = DRM_MODE_DPMS_OFF;
@@ -3953,10 +3951,8 @@ void intel_connector_dpms(struct drm_connector *connector, int mode) · 4 unmodified lines
39533951 connector->dpms = mode;
39543952
39553953 /* Only need to change hw state when actually enabled */
3956− if (encoder->base.crtc)
3957− intel_encoder_dpms(encoder, mode);
3958− else
3959− WARN_ON(encoder->connectors_active != false);
3954+ if (connector->encoder)
3955+ intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
39603956
39613957 intel_modeset_check_state(connector->dev);
39623958 }
@@ -10049,33 +10045,6 @@ static void i915_disable_vga(struct drm_device *dev) · 6086 unmodified lines
1004910045 POSTING_READ(vga_reg);
1005010046 }
1005110047
10052−static void i915_enable_vga_mem(struct drm_device *dev)
10053−{
10054− /* Enable VGA memory on Intel HD */
10055− if (HAS_PCH_SPLIT(dev)) {
10056− vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10057− outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10058− vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10059− VGA_RSRC_LEGACY_MEM |
10060− VGA_RSRC_NORMAL_IO |
10061− VGA_RSRC_NORMAL_MEM);
10062− vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10063− }
10064−}
10065−
10066−void i915_disable_vga_mem(struct drm_device *dev)
10067−{
10068− /* Disable VGA memory on Intel HD */
10069− if (HAS_PCH_SPLIT(dev)) {
10070− vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10071− outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10072− vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10073− VGA_RSRC_NORMAL_IO |
10074− VGA_RSRC_NORMAL_MEM);
10075− vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10076− }
10077−}
10078−
1007910048 void intel_modeset_init_hw(struct drm_device *dev)
1008010049 {
1008110050 intel_init_power_well(dev);
@@ -10354,7 +10323,6 @@ void i915_redisable_vga(struct drm_device *dev) · 272 unmodified lines
1035410323 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
1035510324 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
1035610325 i915_disable_vga(dev);
10357− i915_disable_vga_mem(dev);
1035810326 }
1035910327 }
1036010328
@@ -10568,8 +10536,6 @@ void intel_modeset_cleanup(struct drm_device *dev) · 207 unmodified lines
1056810536
1056910537 intel_disable_fbc(dev);
1057010538
10571− i915_enable_vga_mem(dev);
10572−
1057310539 intel_disable_gt_powersave(dev);
1057410540
1057510541 ironlake_teardown_rc6(dev);
drivers/gpu/drm/i915/intel_dp.c+1−1
@@ -1467,7 +1467,7 @@ static void intel_edp_psr_setup(struct intel_dp *intel_dp) · 1466 unmodified lines
14671467
14681468 /* Avoid continuous PSR exit by masking memup and hpd */
14691469 I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP |
1470− EDP_PSR_DEBUG_MASK_HPD);
1470+ EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
14711471
14721472 intel_dp->psr_setup_done = true;
14731473 }
drivers/gpu/drm/i915/intel_drv.h+0−1
@@ -793,6 +793,5 @@ extern void hsw_pc8_disable_interrupts(struct drm_device *dev); · 792 unmodified lines
793793 extern void hsw_pc8_restore_interrupts(struct drm_device *dev);
794794 extern void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
795795 extern void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
796−extern void i915_disable_vga_mem(struct drm_device *dev);
797796
798797 #endif /* __INTEL_DRV_H__ */
drivers/gpu/drm/i915/intel_pm.c+7−2
@@ -3864,8 +3864,6 @@ static void valleyview_enable_rps(struct drm_device *dev) · 3863 unmodified lines
38643864 dev_priv->rps.rpe_delay),
38653865 dev_priv->rps.rpe_delay);
38663866
3867− INIT_DELAYED_WORK(&dev_priv->rps.vlv_work, vlv_rps_timer_work);
3868−
38693867 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
38703868
38713869 gen6_enable_rps_interrupts(dev);
@@ -4955,6 +4953,11 @@ static void haswell_init_clock_gating(struct drm_device *dev) · 1083 unmodified lines
49554953 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
49564954 GEN7_WA_L3_CHICKEN_MODE);
49574955
4956+ /* L3 caching of data atomics doesn't work -- disable it. */
4957+ I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
4958+ I915_WRITE(HSW_ROW_CHICKEN3,
4959+ _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
4960+
49584961 /* This is required by WaCatErrorRejectionIssue:hsw */
49594962 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
49604963 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
@@ -5681,5 +5684,7 @@ void intel_pm_init(struct drm_device *dev) · 720 unmodified lines
56815684
56825685 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
56835686 intel_gen6_powersave_work);
5687+
5688+ INIT_DELAYED_WORK(&dev_priv->rps.vlv_work, vlv_rps_timer_work);
56845689 }
56855690
drivers/gpu/drm/nouveau/core/subdev/mc/base.c+1−1
@@ -113,7 +113,7 @@ nouveau_mc_create_(struct nouveau_object *parent, struct nouveau_object *engine, · 112 unmodified lines
113113 pmc->use_msi = false;
114114 break;
115115 default:
116− pmc->use_msi = nouveau_boolopt(device->cfgopt, "NvMSI", true);
116+ pmc->use_msi = nouveau_boolopt(device->cfgopt, "NvMSI", false);
117117 if (pmc->use_msi) {
118118 pmc->use_msi = pci_enable_msi(device->pdev) == 0;
119119 if (pmc->use_msi) {
drivers/gpu/drm/radeon/btc_dpm.c+3−3
@@ -1930,7 +1930,7 @@ static int btc_set_mc_special_registers(struct radeon_device *rdev, · 1929 unmodified lines
19301930 }
19311931 j++;
19321932
1933− if (j > SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE)
1933+ if (j >= SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE)
19341934 return -EINVAL;
19351935
19361936 tmp = RREG32(MC_PMG_CMD_MRS);
@@ -1945,7 +1945,7 @@ static int btc_set_mc_special_registers(struct radeon_device *rdev, · 8 unmodified lines
19451945 }
19461946 j++;
19471947
1948− if (j > SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE)
1948+ if (j >= SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE)
19491949 return -EINVAL;
19501950 break;
19511951 case MC_SEQ_RESERVE_M >> 2:
@@ -1959,7 +1959,7 @@ static int btc_set_mc_special_registers(struct radeon_device *rdev, · 7 unmodified lines
19591959 }
19601960 j++;
19611961
1962− if (j > SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE)
1962+ if (j >= SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE)
19631963 return -EINVAL;
19641964 break;
19651965 default:
drivers/gpu/drm/radeon/cik.c+6−0
@@ -77,6 +77,8 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev); · 76 unmodified lines
7777 static void cik_program_aspm(struct radeon_device *rdev);
7878 static void cik_init_pg(struct radeon_device *rdev);
7979 static void cik_init_cg(struct radeon_device *rdev);
80+static void cik_fini_pg(struct radeon_device *rdev);
81+static void cik_fini_cg(struct radeon_device *rdev);
8082 static void cik_enable_gui_idle_interrupt(struct radeon_device *rdev,
8183 bool enable);
8284
@@ -4185,6 +4187,10 @@ static void cik_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) · 4102 unmodified lines
41854187 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
41864188 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
41874189
4190+ /* disable CG/PG */
4191+ cik_fini_pg(rdev);
4192+ cik_fini_cg(rdev);
4193+
41884194 /* stop the rlc */
41894195 cik_rlc_stop(rdev);
41904196
drivers/gpu/drm/radeon/evergreen.c+1−1
@@ -3131,7 +3131,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev) · 3130 unmodified lines
31313131 rdev->config.evergreen.sx_max_export_size = 256;
31323132 rdev->config.evergreen.sx_max_export_pos_size = 64;
31333133 rdev->config.evergreen.sx_max_export_smx_size = 192;
3134− rdev->config.evergreen.max_hw_contexts = 8;
3134+ rdev->config.evergreen.max_hw_contexts = 4;
31353135 rdev->config.evergreen.sq_num_cf_insts = 2;
31363136
31373137 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
drivers/gpu/drm/radeon/evergreen_hdmi.c+1−2
@@ -288,8 +288,7 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode · 287 unmodified lines
288288 /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
289289
290290 WREG32(HDMI_ACR_PACKET_CONTROL + offset,
291− HDMI_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */
292− HDMI_ACR_SOURCE); /* select SW CTS value */
291+ HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
293292
294293 evergreen_hdmi_update_ACR(encoder, mode->clock);
295294
drivers/gpu/drm/radeon/evergreend.h+2−2
@@ -1501,7 +1501,7 @@ · 1500 unmodified lines
15011501 * 6. COMMAND [29:22] | BYTE_COUNT [20:0]
15021502 */
15031503 # define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20)
1504− /* 0 - SRC_ADDR
1504+ /* 0 - DST_ADDR
15051505 * 1 - GDS
15061506 */
15071507 # define PACKET3_CP_DMA_ENGINE(x) ((x) << 27)
@@ -1516,7 +1516,7 @@ · 8 unmodified lines
15161516 # define PACKET3_CP_DMA_CP_SYNC (1 << 31)
15171517 /* COMMAND */
15181518 # define PACKET3_CP_DMA_DIS_WC (1 << 21)
1519−# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23)
1519+# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22)
15201520 /* 0 - none
15211521 * 1 - 8 in 16
15221522 * 2 - 8 in 32
drivers/gpu/drm/radeon/r600_hdmi.c+14−7
@@ -57,15 +57,15 @@ enum r600_hdmi_iec_status_bits { · 56 unmodified lines
5757 static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = {
5858 /* 32kHz 44.1kHz 48kHz */
5959 /* Clock N CTS N CTS N CTS */
60− { 25174, 4576, 28125, 7007, 31250, 6864, 28125 }, /* 25,20/1.001 MHz */
60+ { 25175, 4576, 28125, 7007, 31250, 6864, 28125 }, /* 25,20/1.001 MHz */
6161 { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */
6262 { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */
6363 { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */
6464 { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */
6565 { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */
66− { 74175, 11648, 210937, 17836, 234375, 11648, 140625 }, /* 74.25/1.001 MHz */
66+ { 74176, 11648, 210937, 17836, 234375, 11648, 140625 }, /* 74.25/1.001 MHz */
6767 { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */
68− { 148351, 11648, 421875, 8918, 234375, 5824, 140625 }, /* 148.50/1.001 MHz */
68+ { 148352, 11648, 421875, 8918, 234375, 5824, 140625 }, /* 148.50/1.001 MHz */
6969 { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */
7070 { 0, 4096, 0, 6272, 0, 6144, 0 } /* Other */
7171 };
@@ -75,8 +75,15 @@ static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = { · 3 unmodified lines
7575 */
7676 static void r600_hdmi_calc_cts(uint32_t clock, int *CTS, int N, int freq)
7777 {
78− if (*CTS == 0)
79− *CTS = clock * N / (128 * freq) * 1000;
78+ u64 n;
79+ u32 d;
80+
81+ if (*CTS == 0) {
82+ n = (u64)clock * (u64)N * 1000ULL;
83+ d = 128 * freq;
84+ do_div(n, d);
85+ *CTS = n;
86+ }
8087 DRM_DEBUG("Using ACR timing N=%d CTS=%d for frequency %d\n",
8188 N, *CTS, freq);
8289 }
@@ -444,8 +451,8 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod · 361 unmodified lines
444451 }
445452
446453 WREG32(HDMI0_ACR_PACKET_CONTROL + offset,
447− HDMI0_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */
448− HDMI0_ACR_SOURCE); /* select SW CTS value */
454+ HDMI0_ACR_SOURCE | /* select SW CTS value - XXX verify that hw CTS works on all families */
455+ HDMI0_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
449456
450457 WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
451458 HDMI0_NULL_SEND | /* send null packets when required */
drivers/gpu/drm/radeon/r600d.h+1−1
@@ -1523,7 +1523,7 @@ · 1522 unmodified lines
15231523 */
15241524 # define PACKET3_CP_DMA_CP_SYNC (1 << 31)
15251525 /* COMMAND */
1526−# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23)
1526+# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22)
15271527 /* 0 - none
15281528 * 1 - 8 in 16
15291529 * 2 - 8 in 32
drivers/gpu/drm/radeon/radeon_pm.c+3−0
@@ -945,6 +945,8 @@ void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable) · 944 unmodified lines
945945 if (enable) {
946946 mutex_lock(&rdev->pm.mutex);
947947 rdev->pm.dpm.uvd_active = true;
948+ /* disable this for now */
949+#if 0
948950 if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0))
949951 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_SD;
950952 else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0))
@@ -954,6 +956,7 @@ void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable) · 3 unmodified lines
954956 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2))
955957 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD2;
956958 else
959+#endif
957960 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD;
958961 rdev->pm.dpm.state = dpm_state;
959962 mutex_unlock(&rdev->pm.mutex);
drivers/gpu/drm/radeon/radeon_test.c+2−2
@@ -36,8 +36,8 @@ static void radeon_do_test_moves(struct radeon_device *rdev, int flag) · 35 unmodified lines
3636 struct radeon_bo *vram_obj = NULL;
3737 struct radeon_bo **gtt_obj = NULL;
3838 uint64_t gtt_addr, vram_addr;
39− unsigned i, n, size;
40− int r, ring;
39+ unsigned n, size;
40+ int i, r, ring;
4141
4242 switch (flag) {
4343 case RADEON_TEST_COPY_DMA:
drivers/gpu/drm/radeon/radeon_uvd.c+2−1
@@ -798,7 +798,8 @@ void radeon_uvd_note_usage(struct radeon_device *rdev) · 797 unmodified lines
798798 (rdev->pm.dpm.hd != hd)) {
799799 rdev->pm.dpm.sd = sd;
800800 rdev->pm.dpm.hd = hd;
801− streams_changed = true;
801+ /* disable this for now */
802+ /*streams_changed = true;*/
802803 }
803804 }
804805
drivers/gpu/drm/radeon/si.c+10−0
@@ -85,6 +85,9 @@ extern void si_dma_vm_set_page(struct radeon_device *rdev, · 84 unmodified lines
8585 uint32_t incr, uint32_t flags);
8686 static void si_enable_gui_idle_interrupt(struct radeon_device *rdev,
8787 bool enable);
88+static void si_fini_pg(struct radeon_device *rdev);
89+static void si_fini_cg(struct radeon_device *rdev);
90+static void si_rlc_stop(struct radeon_device *rdev);
8891
8992 static const u32 verde_rlc_save_restore_register_list[] =
9093 {
@@ -3608,6 +3611,13 @@ static void si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) · 3517 unmodified lines
36083611 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
36093612 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
36103613
3614+ /* disable PG/CG */
3615+ si_fini_pg(rdev);
3616+ si_fini_cg(rdev);
3617+
3618+ /* stop the rlc */
3619+ si_rlc_stop(rdev);
3620+
36113621 /* Disable CP parsing/prefetching */
36123622 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
36133623
drivers/gpu/drm/radeon/si_dpm.c+3−3
@@ -5208,7 +5208,7 @@ static int si_set_mc_special_registers(struct radeon_device *rdev, · 5207 unmodified lines
52085208 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
52095209 }
52105210 j++;
5211− if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5211+ if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
52125212 return -EINVAL;
52135213
52145214 if (!pi->mem_gddr5) {
@@ -5218,7 +5218,7 @@ static int si_set_mc_special_registers(struct radeon_device *rdev, · 3 unmodified lines
52185218 table->mc_reg_table_entry[k].mc_data[j] =
52195219 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
52205220 j++;
5221− if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5221+ if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
52225222 return -EINVAL;
52235223 }
52245224 break;
@@ -5231,7 +5231,7 @@ static int si_set_mc_special_registers(struct radeon_device *rdev, · 6 unmodified lines
52315231 (temp_reg & 0xffff0000) |
52325232 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
52335233 j++;
5234− if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5234+ if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
52355235 return -EINVAL;
52365236 break;
52375237 default:
drivers/gpu/drm/radeon/sid.h+2−2
@@ -1553,7 +1553,7 @@ · 1552 unmodified lines
15531553 * 6. COMMAND [30:21] | BYTE_COUNT [20:0]
15541554 */
15551555 # define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20)
1556− /* 0 - SRC_ADDR
1556+ /* 0 - DST_ADDR
15571557 * 1 - GDS
15581558 */
15591559 # define PACKET3_CP_DMA_ENGINE(x) ((x) << 27)
@@ -1568,7 +1568,7 @@ · 8 unmodified lines
15681568 # define PACKET3_CP_DMA_CP_SYNC (1 << 31)
15691569 /* COMMAND */
15701570 # define PACKET3_CP_DMA_DIS_WC (1 << 21)
1571−# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23)
1571+# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22)
15721572 /* 0 - none
15731573 * 1 - 8 in 16
15741574 * 2 - 8 in 32
drivers/gpu/drm/radeon/trinity_dpm.c+1−1
@@ -1868,7 +1868,7 @@ int trinity_dpm_init(struct radeon_device *rdev) · 1867 unmodified lines
18681868 for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++)
18691869 pi->at[i] = TRINITY_AT_DFLT;
18701870
1871− pi->enable_bapm = true;
1871+ pi->enable_bapm = false;
18721872 pi->enable_nbps_policy = true;
18731873 pi->enable_sclk_ds = true;
18741874 pi->enable_gfx_power_gating = true;
include/linux/vgaarb.h+0−7
@@ -65,15 +65,8 @@ struct pci_dev; · 64 unmodified lines
6565 * out of the arbitration process (and can be safe to take
6666 * interrupts at any time.
6767 */
68−#if defined(CONFIG_VGA_ARB)
6968 extern void vga_set_legacy_decoding(struct pci_dev *pdev,
7069 unsigned int decodes);
71−#else
72−static inline void vga_set_legacy_decoding(struct pci_dev *pdev,
73− unsigned int decodes)
74−{
75−}
76−#endif
7770
7871 /**
7972 * vga_get - acquire & locks VGA resources

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