History

Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

* 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (45 commits) ARM: ux500: update defconfig ARM: u300: update defconfig ARM: at91: enable additional boards in existing soc defconfig files ARM: at91: refresh soc defconfig files for 3.2 ARM: at91: rename defconfig files appropriately ARM: OMAP2+: Fix Compilation error when omap_l3_noc built as module ARM: OMAP2+: Remove empty io.h ARM: OMAP2: select ARM_AMBA if OMAP3_EMU is defined ARM: OMAP: smartreflex: fix IRQ handling bug ARM: OMAP: PM: only register TWL with voltage layer when device is present ARM: OMAP: hwmod: Fix the addr space, irq, dma count APIs arm: mx28: fix bit operation in clock setting ARM: imx: export imx_ioremap ARM: imx/mm-imx3: conditionally compile i.MX31 and i.MX35 code ARM: mx5: Fix checkpatch warnings in cpu-imx5.c MAINTAINERS: Add missing directory ARM: imx: drop 'ARCH_MX31' and 'ARCH_MX35' ARM: imx6q: move clock register map to machine_desc.map_io ARM: pxa168/gplugd: add the correct SSP device ARM: Update mach-types to fix mxs build breakage ...

Linus Torvalds committed 14 years ago

Commit cd5b49b2 parents 8cd7920 98014be71 files · +517 −270Browse files

Unified · Split

71 files
  1. MAINTAINERS +8 −0
  2. arch/arm/configs/at91cap9_defconfig +0 −7
  3. arch/arm/configs/at91rm9200_defconfig +14 −33
  4. arch/arm/configs/at91sam9260_defconfig +12 −4
  5. arch/arm/configs/at91sam9g20_defconfig +12 −11
  6. arch/arm/configs/at91sam9g45_defconfig +2 −5
  7. arch/arm/configs/at91sam9rl_defconfig +0 −5
  8. arch/arm/configs/ezx_defconfig +1 −1
  9. arch/arm/configs/imote2_defconfig +1 −1
  10. arch/arm/configs/magician_defconfig +1 −1
  11. arch/arm/configs/omap1_defconfig +0 −1
  12. arch/arm/configs/u300_defconfig +6 −7
  13. arch/arm/configs/u8500_defconfig +5 −9
  14. arch/arm/configs/zeus_defconfig +1 −1
  15. arch/arm/mach-exynos/cpuidle.c +2 −0
  16. arch/arm/mach-highbank/highbank.c +4 −0
  17. arch/arm/mach-imx/Kconfig +0 −13
  18. arch/arm/mach-imx/clock-imx6q.c +5 −2
  19. arch/arm/mach-imx/mach-imx6q.c +1 −0
  20. arch/arm/mach-imx/mm-imx3.c +58 −51
  21. arch/arm/mach-imx/src.c +7 −0
  22. arch/arm/mach-mmp/gplugd.c +1 −1
  23. arch/arm/mach-mmp/include/mach/gpio-pxa.h +1 −1
  24. arch/arm/mach-mx5/cpu.c +3 −2
  25. arch/arm/mach-mx5/mm.c +4 −2
  26. arch/arm/mach-mxs/clock-mx28.c +1 −1
  27. arch/arm/mach-omap1/Kconfig +0 −8
  28. arch/arm/mach-omap1/board-ams-delta.c +7 −3
  29. arch/arm/mach-omap1/clock.h +2 −1
  30. arch/arm/mach-omap1/clock_data.c +34 −19
  31. arch/arm/mach-omap1/devices.c +3 −0
  32. arch/arm/mach-omap2/Kconfig +1 −0
  33. arch/arm/mach-omap2/Makefile +1 −4
  34. arch/arm/mach-omap2/cpuidle34xx.c +1 −0
  35. arch/arm/mach-omap2/display.c +159 −0
  36. arch/arm/mach-omap2/display.h +29 −0
  37. arch/arm/mach-omap2/io.h +0 −0
  38. arch/arm/mach-omap2/omap_hwmod.c +3 −3
  39. arch/arm/mach-omap2/omap_hwmod_2420_data.c +14 −3
  40. arch/arm/mach-omap2/omap_hwmod_2430_data.c +14 −3
  41. arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c +4 −1
  42. arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +32 −5
  43. arch/arm/mach-omap2/omap_hwmod_44xx_data.c +12 −12
  44. arch/arm/mach-omap2/omap_hwmod_common_data.c +4 −0
  45. arch/arm/mach-omap2/omap_hwmod_common_data.h +4 −0
  46. arch/arm/mach-omap2/omap_l3_noc.c +1 −1
  47. arch/arm/mach-omap2/pm.c +2 −4
  48. arch/arm/mach-omap2/smartreflex.c +1 −1
  49. arch/arm/mach-omap2/twl-common.c +11 −0
  50. arch/arm/mach-omap2/twl-common.h +3 −0
  51. arch/arm/mach-pxa/balloon3.c +1 −1
  52. arch/arm/mach-pxa/colibri-pxa320.c +1 −1
  53. arch/arm/mach-pxa/gumstix.c +1 −1
  54. arch/arm/mach-pxa/include/mach/palm27x.h +2 −2
  55. arch/arm/mach-pxa/palm27x.c +2 −2
  56. arch/arm/mach-pxa/palmtc.c +1 −1
  57. arch/arm/mach-pxa/vpac270.c +1 −1
  58. arch/arm/mach-s3c64xx/mach-crag6410-module.c +1 −1
  59. arch/arm/plat-mxc/include/mach/common.h +1 −1
  60. arch/arm/plat-mxc/include/mach/mxc.h +0 −14
  61. arch/arm/plat-mxc/include/mach/system.h +1 −6
  62. arch/arm/plat-mxc/system.c +2 −1
  63. arch/arm/plat-omap/include/plat/clock.h +1 −1
  64. arch/arm/plat-omap/include/plat/common.h +3 −0
  65. arch/arm/plat-s3c24xx/cpu-freq-debugfs.c +1 −1
  66. arch/arm/plat-s5p/sysmmu.c +1 −0
  67. arch/arm/plat-samsung/include/plat/gpio-cfg.h +2 −0
  68. arch/arm/plat-samsung/pd.c +1 −1
  69. arch/arm/plat-samsung/pwm.c +1 −1
  70. arch/arm/tools/mach-types +1 −0
  71. include/video/omapdss.h +0 −7
MAINTAINERS+8−0
@@ -789,6 +789,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) · 788 unmodified lines
789S: Maintained789S: Maintained
790T: git git://git.pengutronix.de/git/imx/linux-2.6.git790T: git git://git.pengutronix.de/git/imx/linux-2.6.git
791F: arch/arm/mach-mx*/791F: arch/arm/mach-mx*/
792F: arch/arm/mach-imx/
792F: arch/arm/plat-mxc/793F: arch/arm/plat-mxc/
793 794
794ARM/FREESCALE IMX51795ARM/FREESCALE IMX51
@@ -804,6 +805,13 @@ S: Maintained · 9 unmodified lines
804T: git git://git.linaro.org/people/shawnguo/linux-2.6.git805T: git git://git.linaro.org/people/shawnguo/linux-2.6.git
805F: arch/arm/mach-imx/*imx6*806F: arch/arm/mach-imx/*imx6*
806 807
808ARM/FREESCALE MXS ARM ARCHITECTURE
809M: Shawn Guo <shawn.guo@linaro.org>
810L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
811S: Maintained
812T: git git://git.linaro.org/people/shawnguo/linux-2.6.git
813F: arch/arm/mach-mxs/
814
807ARM/GLOMATION GESBC9312SX MACHINE SUPPORT815ARM/GLOMATION GESBC9312SX MACHINE SUPPORT
808M: Lennert Buytenhek <kernel@wantstofly.org>816M: Lennert Buytenhek <kernel@wantstofly.org>
809L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)817L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
arch/arm/configs/at91cap9_defconfigrenamed from arch/arm/configs/at91cap9adk_defconfig+0−7
@@ -38,7 +38,6 @@ CONFIG_IP_PNP_RARP=y · 37 unmodified lines
38# CONFIG_IPV6 is not set38# CONFIG_IPV6 is not set
39CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"39CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
40CONFIG_MTD=y40CONFIG_MTD=y
41CONFIG_MTD_PARTITIONS=y
42CONFIG_MTD_CMDLINE_PARTS=y41CONFIG_MTD_CMDLINE_PARTS=y
43CONFIG_MTD_CHAR=y42CONFIG_MTD_CHAR=y
44CONFIG_MTD_BLOCK=y43CONFIG_MTD_BLOCK=y
@@ -52,16 +51,12 @@ CONFIG_MTD_NAND_ATMEL=y · 7 unmodified lines
52CONFIG_BLK_DEV_LOOP=y51CONFIG_BLK_DEV_LOOP=y
53CONFIG_BLK_DEV_RAM=y52CONFIG_BLK_DEV_RAM=y
54CONFIG_BLK_DEV_RAM_SIZE=819253CONFIG_BLK_DEV_RAM_SIZE=8192
55CONFIG_ATMEL_SSC=y
56CONFIG_SCSI=y54CONFIG_SCSI=y
57CONFIG_BLK_DEV_SD=y55CONFIG_BLK_DEV_SD=y
58CONFIG_SCSI_MULTI_LUN=y56CONFIG_SCSI_MULTI_LUN=y
59CONFIG_NETDEVICES=y57CONFIG_NETDEVICES=y
60CONFIG_NET_ETHERNET=y
61CONFIG_MII=y58CONFIG_MII=y
62CONFIG_MACB=y59CONFIG_MACB=y
63# CONFIG_NETDEV_1000 is not set
64# CONFIG_NETDEV_10000 is not set
65# CONFIG_INPUT_MOUSEDEV_PSAUX is not set60# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
66CONFIG_INPUT_EVDEV=y61CONFIG_INPUT_EVDEV=y
67# CONFIG_INPUT_KEYBOARD is not set62# CONFIG_INPUT_KEYBOARD is not set
@@ -81,7 +76,6 @@ CONFIG_WATCHDOG=y · 13 unmodified lines
81CONFIG_WATCHDOG_NOWAYOUT=y76CONFIG_WATCHDOG_NOWAYOUT=y
82CONFIG_FB=y77CONFIG_FB=y
83CONFIG_FB_ATMEL=y78CONFIG_FB_ATMEL=y
84# CONFIG_VGA_CONSOLE is not set
85CONFIG_LOGO=y79CONFIG_LOGO=y
86# CONFIG_LOGO_LINUX_MONO is not set80# CONFIG_LOGO_LINUX_MONO is not set
87# CONFIG_LOGO_LINUX_CLUT224 is not set81# CONFIG_LOGO_LINUX_CLUT224 is not set
@@ -99,7 +93,6 @@ CONFIG_MMC_AT91=m · 11 unmodified lines
99CONFIG_RTC_CLASS=y93CONFIG_RTC_CLASS=y
100CONFIG_RTC_DRV_AT91SAM9=y94CONFIG_RTC_DRV_AT91SAM9=y
101CONFIG_EXT2_FS=y95CONFIG_EXT2_FS=y
102CONFIG_INOTIFY=y
103CONFIG_VFAT_FS=y96CONFIG_VFAT_FS=y
104CONFIG_TMPFS=y97CONFIG_TMPFS=y
105CONFIG_JFFS2_FS=y98CONFIG_JFFS2_FS=y
arch/arm/configs/at91rm9200_defconfig+14−33
@@ -5,7 +5,6 @@ CONFIG_SYSVIPC=y · 4 unmodified lines
5CONFIG_IKCONFIG=y5CONFIG_IKCONFIG=y
6CONFIG_IKCONFIG_PROC=y6CONFIG_IKCONFIG_PROC=y
7CONFIG_LOG_BUF_SHIFT=147CONFIG_LOG_BUF_SHIFT=14
8CONFIG_SYSFS_DEPRECATED_V2=y
9CONFIG_BLK_DEV_INITRD=y8CONFIG_BLK_DEV_INITRD=y
10CONFIG_MODULES=y9CONFIG_MODULES=y
11CONFIG_MODULE_FORCE_LOAD=y10CONFIG_MODULE_FORCE_LOAD=y
@@ -56,7 +55,6 @@ CONFIG_IP_PNP=y · 44 unmodified lines
56CONFIG_IP_PNP_DHCP=y55CONFIG_IP_PNP_DHCP=y
57CONFIG_IP_PNP_BOOTP=y56CONFIG_IP_PNP_BOOTP=y
58CONFIG_NET_IPIP=m57CONFIG_NET_IPIP=m
59CONFIG_NET_IPGRE=m
60CONFIG_INET_AH=m58CONFIG_INET_AH=m
61CONFIG_INET_ESP=m59CONFIG_INET_ESP=m
62CONFIG_INET_IPCOMP=m60CONFIG_INET_IPCOMP=m
@@ -75,18 +73,8 @@ CONFIG_IPV6_TUNNEL=m · 12 unmodified lines
75CONFIG_BRIDGE=m73CONFIG_BRIDGE=m
76CONFIG_VLAN_8021Q=m74CONFIG_VLAN_8021Q=m
77CONFIG_BT=m75CONFIG_BT=m
78CONFIG_BT_L2CAP=m
79CONFIG_BT_SCO=m
80CONFIG_BT_RFCOMM=m
81CONFIG_BT_RFCOMM_TTY=y
82CONFIG_BT_BNEP=m
83CONFIG_BT_BNEP_MC_FILTER=y
84CONFIG_BT_BNEP_PROTO_FILTER=y
85CONFIG_BT_HIDP=m
86CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"76CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
87CONFIG_MTD=y77CONFIG_MTD=y
88CONFIG_MTD_CONCAT=y
89CONFIG_MTD_PARTITIONS=y
90CONFIG_MTD_CMDLINE_PARTS=y78CONFIG_MTD_CMDLINE_PARTS=y
91CONFIG_MTD_AFS_PARTS=y79CONFIG_MTD_AFS_PARTS=y
92CONFIG_MTD_CHAR=y80CONFIG_MTD_CHAR=y
@@ -108,8 +96,6 @@ CONFIG_BLK_DEV_LOOP=y · 15 unmodified lines
108CONFIG_BLK_DEV_NBD=y96CONFIG_BLK_DEV_NBD=y
109CONFIG_BLK_DEV_RAM=y97CONFIG_BLK_DEV_RAM=y
110CONFIG_BLK_DEV_RAM_SIZE=819298CONFIG_BLK_DEV_RAM_SIZE=8192
111CONFIG_ATMEL_TCLIB=y
112CONFIG_EEPROM_LEGACY=m
113CONFIG_SCSI=y99CONFIG_SCSI=y
114CONFIG_BLK_DEV_SD=y100CONFIG_BLK_DEV_SD=y
115CONFIG_BLK_DEV_SR=m101CONFIG_BLK_DEV_SR=m
@@ -119,14 +105,23 @@ CONFIG_SCSI_MULTI_LUN=y · 3 unmodified lines
119# CONFIG_SCSI_LOWLEVEL is not set105# CONFIG_SCSI_LOWLEVEL is not set
120CONFIG_NETDEVICES=y106CONFIG_NETDEVICES=y
121CONFIG_TUN=m107CONFIG_TUN=m
108CONFIG_ARM_AT91_ETHER=y
122CONFIG_PHYLIB=y109CONFIG_PHYLIB=y
123CONFIG_DAVICOM_PHY=y110CONFIG_DAVICOM_PHY=y
124CONFIG_SMSC_PHY=y111CONFIG_SMSC_PHY=y
125CONFIG_MICREL_PHY=y112CONFIG_MICREL_PHY=y
126CONFIG_NET_ETHERNET=y113CONFIG_PPP=y
127CONFIG_ARM_AT91_ETHER=y114CONFIG_PPP_BSDCOMP=y
128# CONFIG_NETDEV_1000 is not set115CONFIG_PPP_DEFLATE=y
129# CONFIG_NETDEV_10000 is not set116CONFIG_PPP_FILTER=y
117CONFIG_PPP_MPPE=m
118CONFIG_PPP_MULTILINK=y
119CONFIG_PPPOE=m
120CONFIG_PPP_ASYNC=y
121CONFIG_SLIP=m
122CONFIG_SLIP_COMPRESSED=y
123CONFIG_SLIP_SMART=y
124CONFIG_SLIP_MODE_SLIP6=y
130CONFIG_USB_CATC=m125CONFIG_USB_CATC=m
131CONFIG_USB_KAWETH=m126CONFIG_USB_KAWETH=m
132CONFIG_USB_PEGASUS=m127CONFIG_USB_PEGASUS=m
@@ -139,18 +134,6 @@ CONFIG_USB_NET_RNDIS_HOST=m · 6 unmodified lines
139CONFIG_USB_ALI_M5632=y134CONFIG_USB_ALI_M5632=y
140CONFIG_USB_AN2720=y135CONFIG_USB_AN2720=y
141CONFIG_USB_EPSON2888=y136CONFIG_USB_EPSON2888=y
142CONFIG_PPP=y
143CONFIG_PPP_MULTILINK=y
144CONFIG_PPP_FILTER=y
145CONFIG_PPP_ASYNC=y
146CONFIG_PPP_DEFLATE=y
147CONFIG_PPP_BSDCOMP=y
148CONFIG_PPP_MPPE=m
149CONFIG_PPPOE=m
150CONFIG_SLIP=m
151CONFIG_SLIP_COMPRESSED=y
152CONFIG_SLIP_SMART=y
153CONFIG_SLIP_MODE_SLIP6=y
154# CONFIG_INPUT_MOUSEDEV_PSAUX is not set137# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
155CONFIG_INPUT_MOUSEDEV_SCREEN_X=640138CONFIG_INPUT_MOUSEDEV_SCREEN_X=640
156CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480139CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480
@@ -158,9 +141,9 @@ CONFIG_INPUT_EVDEV=y · 1 unmodified line
158CONFIG_KEYBOARD_GPIO=y141CONFIG_KEYBOARD_GPIO=y
159# CONFIG_INPUT_MOUSE is not set142# CONFIG_INPUT_MOUSE is not set
160CONFIG_INPUT_TOUCHSCREEN=y143CONFIG_INPUT_TOUCHSCREEN=y
144CONFIG_LEGACY_PTY_COUNT=32
161CONFIG_SERIAL_ATMEL=y145CONFIG_SERIAL_ATMEL=y
162CONFIG_SERIAL_ATMEL_CONSOLE=y146CONFIG_SERIAL_ATMEL_CONSOLE=y
163CONFIG_LEGACY_PTY_COUNT=32
164CONFIG_HW_RANDOM=y147CONFIG_HW_RANDOM=y
165CONFIG_I2C=y148CONFIG_I2C=y
166CONFIG_I2C_CHARDEV=y149CONFIG_I2C_CHARDEV=y
@@ -290,7 +273,6 @@ CONFIG_NFS_V3_ACL=y · 123 unmodified lines
290CONFIG_NFS_V4=y273CONFIG_NFS_V4=y
291CONFIG_ROOT_NFS=y274CONFIG_ROOT_NFS=y
292CONFIG_NFSD=y275CONFIG_NFSD=y
293CONFIG_SMB_FS=m
294CONFIG_CIFS=m276CONFIG_CIFS=m
295CONFIG_PARTITION_ADVANCED=y277CONFIG_PARTITION_ADVANCED=y
296CONFIG_MAC_PARTITION=y278CONFIG_MAC_PARTITION=y
@@ -335,7 +317,6 @@ CONFIG_NLS_UTF8=y · 38 unmodified lines
335CONFIG_MAGIC_SYSRQ=y317CONFIG_MAGIC_SYSRQ=y
336CONFIG_DEBUG_FS=y318CONFIG_DEBUG_FS=y
337CONFIG_DEBUG_KERNEL=y319CONFIG_DEBUG_KERNEL=y
338# CONFIG_RCU_CPU_STALL_DETECTOR is not set
339# CONFIG_FTRACE is not set320# CONFIG_FTRACE is not set
340CONFIG_CRYPTO_PCBC=y321CONFIG_CRYPTO_PCBC=y
341CONFIG_CRYPTO_SHA1=y322CONFIG_CRYPTO_SHA1=y
arch/arm/configs/at91sam9260_defconfigrenamed from arch/arm/configs/at91sam9260ek_defconfig+12−4
@@ -12,11 +12,23 @@ CONFIG_MODULE_UNLOAD=y · 11 unmodified lines
12# CONFIG_IOSCHED_CFQ is not set12# CONFIG_IOSCHED_CFQ is not set
13CONFIG_ARCH_AT91=y13CONFIG_ARCH_AT91=y
14CONFIG_ARCH_AT91SAM9260=y14CONFIG_ARCH_AT91SAM9260=y
15CONFIG_ARCH_AT91SAM9260_SAM9XE=y
15CONFIG_MACH_AT91SAM9260EK=y16CONFIG_MACH_AT91SAM9260EK=y
17CONFIG_MACH_CAM60=y
18CONFIG_MACH_SAM9_L9260=y
19CONFIG_MACH_AFEB9260=y
20CONFIG_MACH_USB_A9260=y
21CONFIG_MACH_QIL_A9260=y
22CONFIG_MACH_CPU9260=y
23CONFIG_MACH_FLEXIBITY=y
24CONFIG_MACH_SNAPPER_9260=y
25CONFIG_MACH_AT91SAM_DT=y
16CONFIG_AT91_PROGRAMMABLE_CLOCKS=y26CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
17# CONFIG_ARM_THUMB is not set27# CONFIG_ARM_THUMB is not set
18CONFIG_ZBOOT_ROM_TEXT=0x028CONFIG_ZBOOT_ROM_TEXT=0x0
19CONFIG_ZBOOT_ROM_BSS=0x029CONFIG_ZBOOT_ROM_BSS=0x0
30CONFIG_ARM_APPENDED_DTB=y
31CONFIG_ARM_ATAG_DTB_COMPAT=y
20CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"32CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
21CONFIG_FPE_NWFPE=y33CONFIG_FPE_NWFPE=y
22CONFIG_NET=y34CONFIG_NET=y
@@ -33,12 +45,10 @@ CONFIG_IP_PNP_BOOTP=y · 10 unmodified lines
33CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"45CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
34CONFIG_BLK_DEV_RAM=y46CONFIG_BLK_DEV_RAM=y
35CONFIG_BLK_DEV_RAM_SIZE=819247CONFIG_BLK_DEV_RAM_SIZE=8192
36CONFIG_ATMEL_SSC=y
37CONFIG_SCSI=y48CONFIG_SCSI=y
38CONFIG_BLK_DEV_SD=y49CONFIG_BLK_DEV_SD=y
39CONFIG_SCSI_MULTI_LUN=y50CONFIG_SCSI_MULTI_LUN=y
40CONFIG_NETDEVICES=y51CONFIG_NETDEVICES=y
41CONFIG_NET_ETHERNET=y
42CONFIG_MII=y52CONFIG_MII=y
43CONFIG_MACB=y53CONFIG_MACB=y
44# CONFIG_INPUT_MOUSEDEV_PSAUX is not set54# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
@@ -55,7 +65,6 @@ CONFIG_I2C_GPIO=y · 10 unmodified lines
55CONFIG_WATCHDOG=y65CONFIG_WATCHDOG=y
56CONFIG_WATCHDOG_NOWAYOUT=y66CONFIG_WATCHDOG_NOWAYOUT=y
57CONFIG_AT91SAM9X_WATCHDOG=y67CONFIG_AT91SAM9X_WATCHDOG=y
58# CONFIG_VGA_CONSOLE is not set
59# CONFIG_USB_HID is not set68# CONFIG_USB_HID is not set
60CONFIG_USB=y69CONFIG_USB=y
61CONFIG_USB_DEVICEFS=y70CONFIG_USB_DEVICEFS=y
@@ -71,7 +80,6 @@ CONFIG_USB_G_SERIAL=m · 9 unmodified lines
71CONFIG_RTC_CLASS=y80CONFIG_RTC_CLASS=y
72CONFIG_RTC_DRV_AT91SAM9=y81CONFIG_RTC_DRV_AT91SAM9=y
73CONFIG_EXT2_FS=y82CONFIG_EXT2_FS=y
74CONFIG_INOTIFY=y
75CONFIG_VFAT_FS=y83CONFIG_VFAT_FS=y
76CONFIG_TMPFS=y84CONFIG_TMPFS=y
77CONFIG_CRAMFS=y85CONFIG_CRAMFS=y
arch/arm/configs/at91sam9g20_defconfigrenamed from arch/arm/configs/at91sam9g20ek_defconfig+12−11
@@ -14,6 +14,15 @@ CONFIG_ARCH_AT91=y · 13 unmodified lines
14CONFIG_ARCH_AT91SAM9G20=y14CONFIG_ARCH_AT91SAM9G20=y
15CONFIG_MACH_AT91SAM9G20EK=y15CONFIG_MACH_AT91SAM9G20EK=y
16CONFIG_MACH_AT91SAM9G20EK_2MMC=y16CONFIG_MACH_AT91SAM9G20EK_2MMC=y
17CONFIG_MACH_CPU9G20=y
18CONFIG_MACH_ACMENETUSFOXG20=y
19CONFIG_MACH_PORTUXG20=y
20CONFIG_MACH_STAMP9G20=y
21CONFIG_MACH_PCONTROL_G20=y
22CONFIG_MACH_GSIA18S=y
23CONFIG_MACH_USB_A9G20=y
24CONFIG_MACH_SNAPPER_9260=y
25CONFIG_MACH_AT91SAM_DT=y
17CONFIG_AT91_PROGRAMMABLE_CLOCKS=y26CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
18# CONFIG_ARM_THUMB is not set27# CONFIG_ARM_THUMB is not set
19CONFIG_AEABI=y28CONFIG_AEABI=y
@@ -21,9 +30,10 @@ CONFIG_LEDS=y · 1 unmodified line
21CONFIG_LEDS_CPU=y30CONFIG_LEDS_CPU=y
22CONFIG_ZBOOT_ROM_TEXT=0x031CONFIG_ZBOOT_ROM_TEXT=0x0
23CONFIG_ZBOOT_ROM_BSS=0x032CONFIG_ZBOOT_ROM_BSS=0x0
33CONFIG_ARM_APPENDED_DTB=y
34CONFIG_ARM_ATAG_DTB_COMPAT=y
24CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"35CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
25CONFIG_FPE_NWFPE=y36CONFIG_FPE_NWFPE=y
26CONFIG_PM=y
27CONFIG_NET=y37CONFIG_NET=y
28CONFIG_PACKET=y38CONFIG_PACKET=y
29CONFIG_UNIX=y39CONFIG_UNIX=y
@@ -37,8 +47,6 @@ CONFIG_IP_PNP_BOOTP=y · 7 unmodified lines
37# CONFIG_IPV6 is not set47# CONFIG_IPV6 is not set
38CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"48CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
39CONFIG_MTD=y49CONFIG_MTD=y
40CONFIG_MTD_CONCAT=y
41CONFIG_MTD_PARTITIONS=y
42CONFIG_MTD_CMDLINE_PARTS=y50CONFIG_MTD_CMDLINE_PARTS=y
43CONFIG_MTD_CHAR=y51CONFIG_MTD_CHAR=y
44CONFIG_MTD_BLOCK=y52CONFIG_MTD_BLOCK=y
@@ -48,17 +56,13 @@ CONFIG_MTD_NAND_ATMEL=y · 3 unmodified lines
48CONFIG_BLK_DEV_LOOP=y56CONFIG_BLK_DEV_LOOP=y
49CONFIG_BLK_DEV_RAM=y57CONFIG_BLK_DEV_RAM=y
50CONFIG_BLK_DEV_RAM_SIZE=819258CONFIG_BLK_DEV_RAM_SIZE=8192
51CONFIG_ATMEL_SSC=y
52CONFIG_SCSI=y59CONFIG_SCSI=y
53CONFIG_BLK_DEV_SD=y60CONFIG_BLK_DEV_SD=y
54CONFIG_SCSI_MULTI_LUN=y61CONFIG_SCSI_MULTI_LUN=y
55# CONFIG_SCSI_LOWLEVEL is not set62# CONFIG_SCSI_LOWLEVEL is not set
56CONFIG_NETDEVICES=y63CONFIG_NETDEVICES=y
57CONFIG_NET_ETHERNET=y
58CONFIG_MII=y64CONFIG_MII=y
59CONFIG_MACB=y65CONFIG_MACB=y
60# CONFIG_NETDEV_1000 is not set
61# CONFIG_NETDEV_10000 is not set
62# CONFIG_INPUT_MOUSEDEV_PSAUX is not set66# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
63CONFIG_INPUT_MOUSEDEV_SCREEN_X=32067CONFIG_INPUT_MOUSEDEV_SCREEN_X=320
64CONFIG_INPUT_MOUSEDEV_SCREEN_Y=24068CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240
@@ -66,15 +70,14 @@ CONFIG_INPUT_EVDEV=y · 1 unmodified line
66# CONFIG_KEYBOARD_ATKBD is not set70# CONFIG_KEYBOARD_ATKBD is not set
67CONFIG_KEYBOARD_GPIO=y71CONFIG_KEYBOARD_GPIO=y
68# CONFIG_INPUT_MOUSE is not set72# CONFIG_INPUT_MOUSE is not set
73CONFIG_LEGACY_PTY_COUNT=16
69CONFIG_SERIAL_ATMEL=y74CONFIG_SERIAL_ATMEL=y
70CONFIG_SERIAL_ATMEL_CONSOLE=y75CONFIG_SERIAL_ATMEL_CONSOLE=y
71CONFIG_LEGACY_PTY_COUNT=16
72CONFIG_HW_RANDOM=y76CONFIG_HW_RANDOM=y
73CONFIG_SPI=y77CONFIG_SPI=y
74CONFIG_SPI_ATMEL=y78CONFIG_SPI_ATMEL=y
75CONFIG_SPI_SPIDEV=y79CONFIG_SPI_SPIDEV=y
76# CONFIG_HWMON is not set80# CONFIG_HWMON is not set
77# CONFIG_VGA_CONSOLE is not set
78CONFIG_SOUND=y81CONFIG_SOUND=y
79CONFIG_SND=y82CONFIG_SND=y
80CONFIG_SND_SEQUENCER=y83CONFIG_SND_SEQUENCER=y
@@ -82,7 +85,6 @@ CONFIG_SND_MIXER_OSS=y · 1 unmodified line
82CONFIG_SND_PCM_OSS=y85CONFIG_SND_PCM_OSS=y
83CONFIG_SND_SEQUENCER_OSS=y86CONFIG_SND_SEQUENCER_OSS=y
84# CONFIG_SND_VERBOSE_PROCFS is not set87# CONFIG_SND_VERBOSE_PROCFS is not set
85CONFIG_SND_AT73C213=y
86CONFIG_USB=y88CONFIG_USB=y
87CONFIG_USB_DEVICEFS=y89CONFIG_USB_DEVICEFS=y
88# CONFIG_USB_DEVICE_CLASS is not set90# CONFIG_USB_DEVICE_CLASS is not set
@@ -105,7 +107,6 @@ CONFIG_LEDS_TRIGGER_HEARTBEAT=y · 16 unmodified lines
105CONFIG_RTC_CLASS=y107CONFIG_RTC_CLASS=y
106CONFIG_RTC_DRV_AT91SAM9=y108CONFIG_RTC_DRV_AT91SAM9=y
107CONFIG_EXT2_FS=y109CONFIG_EXT2_FS=y
108CONFIG_INOTIFY=y
109CONFIG_MSDOS_FS=y110CONFIG_MSDOS_FS=y
110CONFIG_VFAT_FS=y111CONFIG_VFAT_FS=y
111CONFIG_TMPFS=y112CONFIG_TMPFS=y
arch/arm/configs/at91sam9g45_defconfig+2−5
@@ -18,6 +18,7 @@ CONFIG_MODULE_UNLOAD=y · 17 unmodified lines
18CONFIG_ARCH_AT91=y18CONFIG_ARCH_AT91=y
19CONFIG_ARCH_AT91SAM9G45=y19CONFIG_ARCH_AT91SAM9G45=y
20CONFIG_MACH_AT91SAM9M10G45EK=y20CONFIG_MACH_AT91SAM9M10G45EK=y
21CONFIG_MACH_AT91SAM_DT=y
21CONFIG_AT91_PROGRAMMABLE_CLOCKS=y22CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
22CONFIG_AT91_SLOW_CLOCK=y23CONFIG_AT91_SLOW_CLOCK=y
23CONFIG_AEABI=y24CONFIG_AEABI=y
@@ -73,11 +74,8 @@ CONFIG_SCSI_MULTI_LUN=y · 49 unmodified lines
73# CONFIG_SCSI_LOWLEVEL is not set74# CONFIG_SCSI_LOWLEVEL is not set
74CONFIG_NETDEVICES=y75CONFIG_NETDEVICES=y
75CONFIG_MII=y76CONFIG_MII=y
76CONFIG_DAVICOM_PHY=y
77CONFIG_NET_ETHERNET=y
78CONFIG_MACB=y77CONFIG_MACB=y
79# CONFIG_NETDEV_1000 is not set78CONFIG_DAVICOM_PHY=y
80# CONFIG_NETDEV_10000 is not set
81CONFIG_LIBERTAS_THINFIRM=m79CONFIG_LIBERTAS_THINFIRM=m
82CONFIG_LIBERTAS_THINFIRM_USB=m80CONFIG_LIBERTAS_THINFIRM_USB=m
83CONFIG_AT76C50X_USB=m81CONFIG_AT76C50X_USB=m
@@ -131,7 +129,6 @@ CONFIG_I2C_GPIO=y · 47 unmodified lines
131CONFIG_SPI=y129CONFIG_SPI=y
132CONFIG_SPI_ATMEL=y130CONFIG_SPI_ATMEL=y
133# CONFIG_HWMON is not set131# CONFIG_HWMON is not set
134# CONFIG_MFD_SUPPORT is not set
135CONFIG_FB=y132CONFIG_FB=y
136CONFIG_FB_ATMEL=y133CONFIG_FB_ATMEL=y
137CONFIG_FB_UDL=m134CONFIG_FB_UDL=m
arch/arm/configs/at91sam9rl_defconfigrenamed from arch/arm/configs/at91sam9rlek_defconfig+0−5
@@ -23,8 +23,6 @@ CONFIG_NET=y · 22 unmodified lines
23CONFIG_UNIX=y23CONFIG_UNIX=y
24CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"24CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
25CONFIG_MTD=y25CONFIG_MTD=y
26CONFIG_MTD_CONCAT=y
27CONFIG_MTD_PARTITIONS=y
28CONFIG_MTD_CMDLINE_PARTS=y26CONFIG_MTD_CMDLINE_PARTS=y
29CONFIG_MTD_CHAR=y27CONFIG_MTD_CHAR=y
30CONFIG_MTD_BLOCK=y28CONFIG_MTD_BLOCK=y
@@ -35,7 +33,6 @@ CONFIG_BLK_DEV_LOOP=y · 4 unmodified lines
35CONFIG_BLK_DEV_RAM=y33CONFIG_BLK_DEV_RAM=y
36CONFIG_BLK_DEV_RAM_COUNT=434CONFIG_BLK_DEV_RAM_COUNT=4
37CONFIG_BLK_DEV_RAM_SIZE=2457635CONFIG_BLK_DEV_RAM_SIZE=24576
38CONFIG_ATMEL_SSC=y
39CONFIG_SCSI=y36CONFIG_SCSI=y
40CONFIG_BLK_DEV_SD=y37CONFIG_BLK_DEV_SD=y
41CONFIG_SCSI_MULTI_LUN=y38CONFIG_SCSI_MULTI_LUN=y
@@ -62,13 +59,11 @@ CONFIG_WATCHDOG_NOWAYOUT=y · 20 unmodified lines
62CONFIG_AT91SAM9X_WATCHDOG=y59CONFIG_AT91SAM9X_WATCHDOG=y
63CONFIG_FB=y60CONFIG_FB=y
64CONFIG_FB_ATMEL=y61CONFIG_FB_ATMEL=y
65# CONFIG_VGA_CONSOLE is not set
66CONFIG_MMC=y62CONFIG_MMC=y
67CONFIG_MMC_AT91=m63CONFIG_MMC_AT91=m
68CONFIG_RTC_CLASS=y64CONFIG_RTC_CLASS=y
69CONFIG_RTC_DRV_AT91SAM9=y65CONFIG_RTC_DRV_AT91SAM9=y
70CONFIG_EXT2_FS=y66CONFIG_EXT2_FS=y
71CONFIG_INOTIFY=y
72CONFIG_MSDOS_FS=y67CONFIG_MSDOS_FS=y
73CONFIG_VFAT_FS=y68CONFIG_VFAT_FS=y
74CONFIG_TMPFS=y69CONFIG_TMPFS=y
arch/arm/configs/ezx_defconfig+1−1
@@ -287,7 +287,7 @@ CONFIG_USB=y · 286 unmodified lines
287# CONFIG_USB_DEVICE_CLASS is not set287# CONFIG_USB_DEVICE_CLASS is not set
288CONFIG_USB_OHCI_HCD=y288CONFIG_USB_OHCI_HCD=y
289CONFIG_USB_GADGET=y289CONFIG_USB_GADGET=y
290CONFIG_USB_GADGET_PXA27X=y290CONFIG_USB_PXA27X=y
291CONFIG_USB_ETH=m291CONFIG_USB_ETH=m
292# CONFIG_USB_ETH_RNDIS is not set292# CONFIG_USB_ETH_RNDIS is not set
293CONFIG_MMC=y293CONFIG_MMC=y
arch/arm/configs/imote2_defconfig+1−1
@@ -263,7 +263,7 @@ CONFIG_USB=y · 262 unmodified lines
263# CONFIG_USB_DEVICE_CLASS is not set263# CONFIG_USB_DEVICE_CLASS is not set
264CONFIG_USB_OHCI_HCD=y264CONFIG_USB_OHCI_HCD=y
265CONFIG_USB_GADGET=y265CONFIG_USB_GADGET=y
266CONFIG_USB_GADGET_PXA27X=y266CONFIG_USB_PXA27X=y
267CONFIG_USB_ETH=m267CONFIG_USB_ETH=m
268# CONFIG_USB_ETH_RNDIS is not set268# CONFIG_USB_ETH_RNDIS is not set
269CONFIG_MMC=y269CONFIG_MMC=y
arch/arm/configs/magician_defconfig+1−1
@@ -132,7 +132,7 @@ CONFIG_USB_MON=m · 131 unmodified lines
132CONFIG_USB_OHCI_HCD=y132CONFIG_USB_OHCI_HCD=y
133CONFIG_USB_GADGET=y133CONFIG_USB_GADGET=y
134CONFIG_USB_GADGET_VBUS_DRAW=500134CONFIG_USB_GADGET_VBUS_DRAW=500
135CONFIG_USB_GADGET_PXA27X=y135CONFIG_USB_PXA27X=y
136CONFIG_USB_ETH=m136CONFIG_USB_ETH=m
137# CONFIG_USB_ETH_RNDIS is not set137# CONFIG_USB_ETH_RNDIS is not set
138CONFIG_USB_GADGETFS=m138CONFIG_USB_GADGETFS=m
arch/arm/configs/omap1_defconfig+0−1
@@ -48,7 +48,6 @@ CONFIG_MACH_SX1=y · 47 unmodified lines
48CONFIG_MACH_NOKIA770=y48CONFIG_MACH_NOKIA770=y
49CONFIG_MACH_AMS_DELTA=y49CONFIG_MACH_AMS_DELTA=y
50CONFIG_MACH_OMAP_GENERIC=y50CONFIG_MACH_OMAP_GENERIC=y
51CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER=y
52CONFIG_OMAP_ARM_216MHZ=y51CONFIG_OMAP_ARM_216MHZ=y
53CONFIG_OMAP_ARM_195MHZ=y52CONFIG_OMAP_ARM_195MHZ=y
54CONFIG_OMAP_ARM_192MHZ=y53CONFIG_OMAP_ARM_192MHZ=y
arch/arm/configs/u300_defconfig+6−7
@@ -14,8 +14,6 @@ CONFIG_MODULE_UNLOAD=y · 13 unmodified lines
14CONFIG_ARCH_U300=y14CONFIG_ARCH_U300=y
15CONFIG_MACH_U300=y15CONFIG_MACH_U300=y
16CONFIG_MACH_U300_BS335=y16CONFIG_MACH_U300_BS335=y
17CONFIG_MACH_U300_DUAL_RAM=y
18CONFIG_U300_DEBUG=y
19CONFIG_MACH_U300_SPIDUMMY=y17CONFIG_MACH_U300_SPIDUMMY=y
20CONFIG_NO_HZ=y18CONFIG_NO_HZ=y
21CONFIG_HIGH_RES_TIMERS=y19CONFIG_HIGH_RES_TIMERS=y
@@ -26,19 +24,21 @@ CONFIG_ZBOOT_ROM_BSS=0x0 · 4 unmodified lines
26CONFIG_CMDLINE="root=/dev/ram0 rw rootfstype=rootfs console=ttyAMA0,115200n8 lpj=515072"24CONFIG_CMDLINE="root=/dev/ram0 rw rootfstype=rootfs console=ttyAMA0,115200n8 lpj=515072"
27CONFIG_CPU_IDLE=y25CONFIG_CPU_IDLE=y
28CONFIG_FPE_NWFPE=y26CONFIG_FPE_NWFPE=y
29CONFIG_PM=y
30# CONFIG_SUSPEND is not set27# CONFIG_SUSPEND is not set
31CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"28CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
32# CONFIG_PREVENT_FIRMWARE_BUILD is not set29# CONFIG_PREVENT_FIRMWARE_BUILD is not set
33# CONFIG_MISC_DEVICES is not set30CONFIG_MTD=y
31CONFIG_MTD_CMDLINE_PARTS=y
32CONFIG_MTD_NAND=y
33CONFIG_MTD_NAND_FSMC=y
34# CONFIG_INPUT_MOUSEDEV is not set34# CONFIG_INPUT_MOUSEDEV is not set
35CONFIG_INPUT_EVDEV=y35CONFIG_INPUT_EVDEV=y
36# CONFIG_KEYBOARD_ATKBD is not set36# CONFIG_KEYBOARD_ATKBD is not set
37# CONFIG_INPUT_MOUSE is not set37# CONFIG_INPUT_MOUSE is not set
38# CONFIG_SERIO is not set38# CONFIG_SERIO is not set
39CONFIG_LEGACY_PTY_COUNT=16
39CONFIG_SERIAL_AMBA_PL011=y40CONFIG_SERIAL_AMBA_PL011=y
40CONFIG_SERIAL_AMBA_PL011_CONSOLE=y41CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
41CONFIG_LEGACY_PTY_COUNT=16
42# CONFIG_HW_RANDOM is not set42# CONFIG_HW_RANDOM is not set
43CONFIG_I2C=y43CONFIG_I2C=y
44# CONFIG_HWMON is not set44# CONFIG_HWMON is not set
@@ -51,6 +51,7 @@ CONFIG_BACKLIGHT_CLASS_DEVICE=y · 6 unmodified lines
51# CONFIG_HID_SUPPORT is not set51# CONFIG_HID_SUPPORT is not set
52# CONFIG_USB_SUPPORT is not set52# CONFIG_USB_SUPPORT is not set
53CONFIG_MMC=y53CONFIG_MMC=y
54CONFIG_MMC_CLKGATE=y
54CONFIG_MMC_ARMMMCI=y55CONFIG_MMC_ARMMMCI=y
55CONFIG_RTC_CLASS=y56CONFIG_RTC_CLASS=y
56# CONFIG_RTC_HCTOSYS is not set57# CONFIG_RTC_HCTOSYS is not set
@@ -65,10 +66,8 @@ CONFIG_NLS_CODEPAGE_437=y · 8 unmodified lines
65CONFIG_NLS_ISO8859_1=y66CONFIG_NLS_ISO8859_1=y
66CONFIG_PRINTK_TIME=y67CONFIG_PRINTK_TIME=y
67CONFIG_DEBUG_FS=y68CONFIG_DEBUG_FS=y
68CONFIG_DEBUG_KERNEL=y
69# CONFIG_SCHED_DEBUG is not set69# CONFIG_SCHED_DEBUG is not set
70CONFIG_TIMER_STATS=y70CONFIG_TIMER_STATS=y
71# CONFIG_DEBUG_PREEMPT is not set71# CONFIG_DEBUG_PREEMPT is not set
72CONFIG_DEBUG_INFO=y72CONFIG_DEBUG_INFO=y
73# CONFIG_RCU_CPU_STALL_DETECTOR is not set
74# CONFIG_CRC32 is not set73# CONFIG_CRC32 is not set
arch/arm/configs/u8500_defconfig+5−9
@@ -10,7 +10,7 @@ CONFIG_MODULE_UNLOAD=y · 9 unmodified lines
10CONFIG_ARCH_U8500=y10CONFIG_ARCH_U8500=y
11CONFIG_UX500_SOC_DB5500=y11CONFIG_UX500_SOC_DB5500=y
12CONFIG_UX500_SOC_DB8500=y12CONFIG_UX500_SOC_DB8500=y
13CONFIG_MACH_U8500=y13CONFIG_MACH_HREFV60=y
14CONFIG_MACH_SNOWBALL=y14CONFIG_MACH_SNOWBALL=y
15CONFIG_MACH_U5500=y15CONFIG_MACH_U5500=y
16CONFIG_NO_HZ=y16CONFIG_NO_HZ=y
@@ -24,6 +24,7 @@ CONFIG_CPU_FREQ=y · 7 unmodified lines
24CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y24CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
25CONFIG_VFP=y25CONFIG_VFP=y
26CONFIG_NEON=y26CONFIG_NEON=y
27CONFIG_PM_RUNTIME=y
27CONFIG_NET=y28CONFIG_NET=y
28CONFIG_PACKET=y29CONFIG_PACKET=y
29CONFIG_UNIX=y30CONFIG_UNIX=y
@@ -41,11 +42,8 @@ CONFIG_MISC_DEVICES=y · 11 unmodified lines
41CONFIG_AB8500_PWM=y42CONFIG_AB8500_PWM=y
42CONFIG_SENSORS_BH1780=y43CONFIG_SENSORS_BH1780=y
43CONFIG_NETDEVICES=y44CONFIG_NETDEVICES=y
44CONFIG_SMSC_PHY=y
45CONFIG_NET_ETHERNET=y
46CONFIG_SMSC911X=y45CONFIG_SMSC911X=y
47# CONFIG_NETDEV_1000 is not set46CONFIG_SMSC_PHY=y
48# CONFIG_NETDEV_10000 is not set
49# CONFIG_WLAN is not set47# CONFIG_WLAN is not set
50# CONFIG_INPUT_MOUSEDEV_PSAUX is not set48# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
51CONFIG_INPUT_EVDEV=y49CONFIG_INPUT_EVDEV=y
@@ -72,15 +70,12 @@ CONFIG_SPI=y · 20 unmodified lines
72CONFIG_SPI_PL022=y70CONFIG_SPI_PL022=y
73CONFIG_GPIO_STMPE=y71CONFIG_GPIO_STMPE=y
74CONFIG_GPIO_TC3589X=y72CONFIG_GPIO_TC3589X=y
75# CONFIG_HWMON is not set
76CONFIG_MFD_STMPE=y73CONFIG_MFD_STMPE=y
77CONFIG_MFD_TC3589X=y74CONFIG_MFD_TC3589X=y
75CONFIG_AB5500_CORE=y
78CONFIG_AB8500_CORE=y76CONFIG_AB8500_CORE=y
79CONFIG_REGULATOR_AB8500=y77CONFIG_REGULATOR_AB8500=y
80# CONFIG_HID_SUPPORT is not set78# CONFIG_HID_SUPPORT is not set
81CONFIG_USB_MUSB_HDRC=y
82CONFIG_USB_GADGET_MUSB_HDRC=y
83CONFIG_MUSB_PIO_ONLY=y
84CONFIG_USB_GADGET=y79CONFIG_USB_GADGET=y
85CONFIG_AB8500_USB=y80CONFIG_AB8500_USB=y
86CONFIG_MMC=y81CONFIG_MMC=y
@@ -97,6 +92,7 @@ CONFIG_DMADEVICES=y · 10 unmodified lines
97CONFIG_STE_DMA40=y92CONFIG_STE_DMA40=y
98CONFIG_STAGING=y93CONFIG_STAGING=y
99CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4=y94CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4=y
95CONFIG_HSEM_U8500=y
100CONFIG_EXT2_FS=y96CONFIG_EXT2_FS=y
101CONFIG_EXT2_FS_XATTR=y97CONFIG_EXT2_FS_XATTR=y
102CONFIG_EXT2_FS_POSIX_ACL=y98CONFIG_EXT2_FS_POSIX_ACL=y
arch/arm/configs/zeus_defconfig+1−1
@@ -140,7 +140,7 @@ CONFIG_USB_SERIAL=m · 139 unmodified lines
140CONFIG_USB_SERIAL_GENERIC=y140CONFIG_USB_SERIAL_GENERIC=y
141CONFIG_USB_SERIAL_MCT_U232=m141CONFIG_USB_SERIAL_MCT_U232=m
142CONFIG_USB_GADGET=m142CONFIG_USB_GADGET=m
143CONFIG_USB_GADGET_PXA27X=y143CONFIG_USB_PXA27X=y
144CONFIG_USB_ETH=m144CONFIG_USB_ETH=m
145CONFIG_USB_GADGETFS=m145CONFIG_USB_GADGETFS=m
146CONFIG_USB_FILE_STORAGE=m146CONFIG_USB_FILE_STORAGE=m
arch/arm/mach-exynos/cpuidle.c+2−0
@@ -12,6 +12,8 @@ · 11 unmodified lines
12#include <linux/init.h>12#include <linux/init.h>
13#include <linux/cpuidle.h>13#include <linux/cpuidle.h>
14#include <linux/io.h>14#include <linux/io.h>
15#include <linux/export.h>
16#include <linux/time.h>
15 17
16#include <asm/proc-fns.h>18#include <asm/proc-fns.h>
17 19
arch/arm/mach-highbank/highbank.c+4−0
@@ -22,6 +22,7 @@ · 21 unmodified lines
22#include <linux/of_irq.h>22#include <linux/of_irq.h>
23#include <linux/of_platform.h>23#include <linux/of_platform.h>
24#include <linux/of_address.h>24#include <linux/of_address.h>
25#include <linux/smp.h>
25 26
26#include <asm/cacheflush.h>27#include <asm/cacheflush.h>
27#include <asm/unified.h>28#include <asm/unified.h>
@@ -72,6 +73,9 @@ static void __init highbank_map_io(void) · 44 unmodified lines
72 73
73void highbank_set_cpu_jump(int cpu, void *jump_addr)74void highbank_set_cpu_jump(int cpu, void *jump_addr)
74{75{
76#ifdef CONFIG_SMP
77 cpu = cpu_logical_map(cpu);
78#endif
75 writel(BSYM(virt_to_phys(jump_addr)), HB_JUMP_TABLE_VIRT(cpu));79 writel(BSYM(virt_to_phys(jump_addr)), HB_JUMP_TABLE_VIRT(cpu));
76 __cpuc_flush_dcache_area(HB_JUMP_TABLE_VIRT(cpu), 16);80 __cpuc_flush_dcache_area(HB_JUMP_TABLE_VIRT(cpu), 16);
77 outer_clean_range(HB_JUMP_TABLE_PHYS(cpu),81 outer_clean_range(HB_JUMP_TABLE_PHYS(cpu),
arch/arm/mach-imx/Kconfig+0−13
@@ -10,11 +10,6 @@ config HAVE_IMX_MMDC · 9 unmodified lines
10config HAVE_IMX_SRC10config HAVE_IMX_SRC
11 bool11 bool
12 12
13#
14# ARCH_MX31 and ARCH_MX35 are left for compatibility
15# Some usages assume that having one of them implies not having (e.g.) ARCH_MX2.
16# To easily distinguish good and reviewed from unreviewed usages new (and IMHO
17# more sensible) names are used: SOC_IMX31 and SOC_IMX35
18config ARCH_MX113config ARCH_MX1
19 bool14 bool
20 15
@@ -27,12 +22,6 @@ config ARCH_MX25 · 6 unmodified lines
27config MACH_MX2722config MACH_MX27
28 bool23 bool
29 24
30config ARCH_MX31
31 bool
32
33config ARCH_MX35
34 bool
35
36config SOC_IMX125config SOC_IMX1
37 bool26 bool
38 select ARCH_MX127 select ARCH_MX1
@@ -72,7 +61,6 @@ config SOC_IMX31 · 33 unmodified lines
72 select CPU_V661 select CPU_V6
73 select IMX_HAVE_PLATFORM_MXC_RNGA62 select IMX_HAVE_PLATFORM_MXC_RNGA
74 select ARCH_MXC_AUDMUX_V263 select ARCH_MXC_AUDMUX_V2
75 select ARCH_MX31
76 select MXC_AVIC64 select MXC_AVIC
77 select SMP_ON_UP if SMP65 select SMP_ON_UP if SMP
78 66
@@ -82,7 +70,6 @@ config SOC_IMX35 · 3 unmodified lines
82 select ARCH_MXC_IOMUX_V370 select ARCH_MXC_IOMUX_V3
83 select ARCH_MXC_AUDMUX_V271 select ARCH_MXC_AUDMUX_V2
84 select HAVE_EPIT72 select HAVE_EPIT
85 select ARCH_MX35
86 select MXC_AVIC73 select MXC_AVIC
87 select SMP_ON_UP if SMP74 select SMP_ON_UP if SMP
88 75
arch/arm/mach-imx/clock-imx6q.c+5−2
@@ -1953,14 +1953,17 @@ static struct map_desc imx6q_clock_desc[] = { · 1952 unmodified lines
1953 imx_map_entry(MX6Q, ANATOP, MT_DEVICE),1953 imx_map_entry(MX6Q, ANATOP, MT_DEVICE),
1954};1954};
1955 1955
1956void __init imx6q_clock_map_io(void)
1957{
1958 iotable_init(imx6q_clock_desc, ARRAY_SIZE(imx6q_clock_desc));
1959}
1960
1956int __init mx6q_clocks_init(void)1961int __init mx6q_clocks_init(void)
1957{1962{
1958 struct device_node *np;1963 struct device_node *np;
1959 void __iomem *base;1964 void __iomem *base;
1960 int i, irq;1965 int i, irq;
1961 1966
1962 iotable_init(imx6q_clock_desc, ARRAY_SIZE(imx6q_clock_desc));
1963
1964 /* retrieve the freqency of fixed clocks from device tree */1967 /* retrieve the freqency of fixed clocks from device tree */
1965 for_each_compatible_node(np, NULL, "fixed-clock") {1968 for_each_compatible_node(np, NULL, "fixed-clock") {
1966 u32 rate;1969 u32 rate;
arch/arm/mach-imx/mach-imx6q.c+1−0
@@ -34,6 +34,7 @@ static void __init imx6q_map_io(void) · 33 unmodified lines
34{34{
35 imx_lluart_map_io();35 imx_lluart_map_io();
36 imx_scu_map_io();36 imx_scu_map_io();
37 imx6q_clock_map_io();
37}38}
38 39
39static void __init imx6q_gpio_add_irq_domain(struct device_node *np,40static void __init imx6q_gpio_add_irq_domain(struct device_node *np,
arch/arm/mach-imx/mm-imx3.c+58−51
@@ -33,29 +33,32 @@ · 32 unmodified lines
33static void imx3_idle(void)33static void imx3_idle(void)
34{34{
35 unsigned long reg = 0;35 unsigned long reg = 0;
36 __asm__ __volatile__(36
37 /* disable I and D cache */37 if (!need_resched())
38 "mrc p15, 0, %0, c1, c0, 0\n"38 __asm__ __volatile__(
39 "bic %0, %0, #0x00001000\n"39 /* disable I and D cache */
40 "bic %0, %0, #0x00000004\n"40 "mrc p15, 0, %0, c1, c0, 0\n"
41 "mcr p15, 0, %0, c1, c0, 0\n"41 "bic %0, %0, #0x00001000\n"
42 /* invalidate I cache */42 "bic %0, %0, #0x00000004\n"
43 "mov %0, #0\n"43 "mcr p15, 0, %0, c1, c0, 0\n"
44 "mcr p15, 0, %0, c7, c5, 0\n"44 /* invalidate I cache */
45 /* clear and invalidate D cache */45 "mov %0, #0\n"
46 "mov %0, #0\n"46 "mcr p15, 0, %0, c7, c5, 0\n"
47 "mcr p15, 0, %0, c7, c14, 0\n"47 /* clear and invalidate D cache */
48 /* WFI */48 "mov %0, #0\n"
49 "mov %0, #0\n"49 "mcr p15, 0, %0, c7, c14, 0\n"
50 "mcr p15, 0, %0, c7, c0, 4\n"50 /* WFI */
51 "nop\n" "nop\n" "nop\n" "nop\n"51 "mov %0, #0\n"
52 "nop\n" "nop\n" "nop\n"52 "mcr p15, 0, %0, c7, c0, 4\n"
53 /* enable I and D cache */53 "nop\n" "nop\n" "nop\n" "nop\n"
54 "mrc p15, 0, %0, c1, c0, 0\n"54 "nop\n" "nop\n" "nop\n"
55 "orr %0, %0, #0x00001000\n"55 /* enable I and D cache */
56 "orr %0, %0, #0x00000004\n"56 "mrc p15, 0, %0, c1, c0, 0\n"
57 "mcr p15, 0, %0, c1, c0, 0\n"57 "orr %0, %0, #0x00001000\n"
58 : "=r" (reg));58 "orr %0, %0, #0x00000004\n"
59 "mcr p15, 0, %0, c1, c0, 0\n"
60 : "=r" (reg));
61 local_irq_enable();
59}62}
60 63
61static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size,64static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size,
@@ -108,6 +111,7 @@ void imx3_init_l2x0(void) · 46 unmodified lines
108 l2x0_init(l2x0_base, 0x00030024, 0x00000000);111 l2x0_init(l2x0_base, 0x00030024, 0x00000000);
109}112}
110 113
114#ifdef CONFIG_SOC_IMX31
111static struct map_desc mx31_io_desc[] __initdata = {115static struct map_desc mx31_io_desc[] __initdata = {
112 imx_map_entry(MX31, X_MEMC, MT_DEVICE),116 imx_map_entry(MX31, X_MEMC, MT_DEVICE),
113 imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),117 imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
@@ -126,33 +130,11 @@ void __init mx31_map_io(void) · 12 unmodified lines
126 iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));130 iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
127}131}
128 132
129static struct map_desc mx35_io_desc[] __initdata = {
130 imx_map_entry(MX35, X_MEMC, MT_DEVICE),
131 imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
132 imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
133 imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
134 imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
135};
136
137void __init mx35_map_io(void)
138{
139 iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
140}
141
142void __init imx31_init_early(void)133void __init imx31_init_early(void)
143{134{
144 mxc_set_cpu_type(MXC_CPU_MX31);135 mxc_set_cpu_type(MXC_CPU_MX31);
145 mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));136 mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
146 imx_idle = imx3_idle;137 pm_idle = imx3_idle;
147 imx_ioremap = imx3_ioremap;
148}
149
150void __init imx35_init_early(void)
151{
152 mxc_set_cpu_type(MXC_CPU_MX35);
153 mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
154 mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
155 imx_idle = imx3_idle;
156 imx_ioremap = imx3_ioremap;138 imx_ioremap = imx3_ioremap;
157}139}
158 140
@@ -161,11 +143,6 @@ void __init mx31_init_irq(void) · 2 unmodified lines
161 mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));143 mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
162}144}
163 145
164void __init mx35_init_irq(void)
165{
166 mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
167}
168
169static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = {146static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = {
170 .per_2_per_addr = 1677,147 .per_2_per_addr = 1677,
171};148};
@@ -199,6 +176,35 @@ void __init imx31_soc_init(void) · 27 unmodified lines
199 176
200 imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);177 imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);
201}178}
179#endif /* ifdef CONFIG_SOC_IMX31 */
180
181#ifdef CONFIG_SOC_IMX35
182static struct map_desc mx35_io_desc[] __initdata = {
183 imx_map_entry(MX35, X_MEMC, MT_DEVICE),
184 imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
185 imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
186 imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
187 imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
188};
189
190void __init mx35_map_io(void)
191{
192 iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
193}
194
195void __init imx35_init_early(void)
196{
197 mxc_set_cpu_type(MXC_CPU_MX35);
198 mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
199 mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
200 pm_idle = imx3_idle;
201 imx_ioremap = imx3_ioremap;
202}
203
204void __init mx35_init_irq(void)
205{
206 mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
207}
202 208
203static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = {209static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = {
204 .ap_2_ap_addr = 642,210 .ap_2_ap_addr = 642,
@@ -254,3 +260,4 @@ void __init imx35_soc_init(void) · 49 unmodified lines
254 260
255 imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata);261 imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata);
256}262}
263#endif /* ifdef CONFIG_SOC_IMX35 */
arch/arm/mach-imx/src.c+7−0
@@ -14,6 +14,7 @@ · 13 unmodified lines
14#include <linux/io.h>14#include <linux/io.h>
15#include <linux/of.h>15#include <linux/of.h>
16#include <linux/of_address.h>16#include <linux/of_address.h>
17#include <linux/smp.h>
17#include <asm/unified.h>18#include <asm/unified.h>
18 19
19#define SRC_SCR 0x00020#define SRC_SCR 0x000
@@ -23,10 +24,15 @@ · 3 unmodified lines
23 24
24static void __iomem *src_base;25static void __iomem *src_base;
25 26
27#ifndef CONFIG_SMP
28#define cpu_logical_map(cpu) 0
29#endif
30
26void imx_enable_cpu(int cpu, bool enable)31void imx_enable_cpu(int cpu, bool enable)
27{32{
28 u32 mask, val;33 u32 mask, val;
29 34
35 cpu = cpu_logical_map(cpu);
30 mask = 1 << (BP_SRC_SCR_CORE1_ENABLE + cpu - 1);36 mask = 1 << (BP_SRC_SCR_CORE1_ENABLE + cpu - 1);
31 val = readl_relaxed(src_base + SRC_SCR);37 val = readl_relaxed(src_base + SRC_SCR);
32 val = enable ? val | mask : val & ~mask;38 val = enable ? val | mask : val & ~mask;
@@ -35,6 +41,7 @@ void imx_enable_cpu(int cpu, bool enable) · 2 unmodified lines
35 41
36void imx_set_cpu_jump(int cpu, void *jump_addr)42void imx_set_cpu_jump(int cpu, void *jump_addr)
37{43{
44 cpu = cpu_logical_map(cpu);
38 writel_relaxed(BSYM(virt_to_phys(jump_addr)),45 writel_relaxed(BSYM(virt_to_phys(jump_addr)),
39 src_base + SRC_GPR1 + cpu * 8);46 src_base + SRC_GPR1 + cpu * 8);
40}47}
arch/arm/mach-mmp/gplugd.c+1−1
@@ -182,7 +182,7 @@ static void __init gplugd_init(void) · 181 unmodified lines
182 182
183 /* on-chip devices */183 /* on-chip devices */
184 pxa168_add_uart(3);184 pxa168_add_uart(3);
185 pxa168_add_ssp(0);185 pxa168_add_ssp(1);
186 pxa168_add_twsi(0, NULL, ARRAY_AND_SIZE(gplugd_i2c_board_info));186 pxa168_add_twsi(0, NULL, ARRAY_AND_SIZE(gplugd_i2c_board_info));
187 187
188 pxa168_add_eth(&gplugd_eth_platform_data);188 pxa168_add_eth(&gplugd_eth_platform_data);
arch/arm/mach-mmp/include/mach/gpio-pxa.h+1−1
@@ -7,7 +7,7 @@ · 6 unmodified lines
7#define GPIO_REGS_VIRT (APB_VIRT_BASE + 0x19000)7#define GPIO_REGS_VIRT (APB_VIRT_BASE + 0x19000)
8 8
9#define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))9#define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
10#define GPIO_REG(x) (GPIO_REGS_VIRT + (x))10#define GPIO_REG(x) (*(volatile u32 *)(GPIO_REGS_VIRT + (x)))
11 11
12#define NR_BUILTIN_GPIO IRQ_GPIO_NUM12#define NR_BUILTIN_GPIO IRQ_GPIO_NUM
13 13
arch/arm/mach-mx5/cpu.c+3−2
@@ -16,7 +16,7 @@ · 15 unmodified lines
16#include <linux/init.h>16#include <linux/init.h>
17#include <linux/module.h>17#include <linux/module.h>
18#include <mach/hardware.h>18#include <mach/hardware.h>
19#include <asm/io.h>19#include <linux/io.h>
20 20
21static int mx5_cpu_rev = -1;21static int mx5_cpu_rev = -1;
22 22
@@ -67,7 +67,8 @@ static int __init mx51_neon_fixup(void) · 44 unmodified lines
67 if (!cpu_is_mx51())67 if (!cpu_is_mx51())
68 return 0;68 return 0;
69 69
70 if (mx51_revision() < IMX_CHIP_REVISION_3_0 && (elf_hwcap & HWCAP_NEON)) {70 if (mx51_revision() < IMX_CHIP_REVISION_3_0 &&
71 (elf_hwcap & HWCAP_NEON)) {
71 elf_hwcap &= ~HWCAP_NEON;72 elf_hwcap &= ~HWCAP_NEON;
72 pr_info("Turning off NEON support, detected broken NEON implementation\n");73 pr_info("Turning off NEON support, detected broken NEON implementation\n");
73 }74 }
arch/arm/mach-mx5/mm.c+4−2
@@ -23,7 +23,9 @@ · 22 unmodified lines
23 23
24static void imx5_idle(void)24static void imx5_idle(void)
25{25{
26 mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);26 if (!need_resched())
27 mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
28 local_irq_enable();
27}29}
28 30
29/*31/*
@@ -89,7 +91,7 @@ void __init imx51_init_early(void) · 59 unmodified lines
89 mxc_set_cpu_type(MXC_CPU_MX51);91 mxc_set_cpu_type(MXC_CPU_MX51);
90 mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));92 mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
91 mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));93 mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
92 imx_idle = imx5_idle;94 pm_idle = imx5_idle;
93}95}
94 96
95void __init imx53_init_early(void)97void __init imx53_init_early(void)
arch/arm/mach-mxs/clock-mx28.c+1−1
@@ -404,7 +404,7 @@ static int name##_set_rate(struct clk *clk, unsigned long rate) \ · 403 unmodified lines
404 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \404 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \
405 reg &= ~BM_CLKCTRL_##dr##_DIV; \405 reg &= ~BM_CLKCTRL_##dr##_DIV; \
406 reg |= div << BP_CLKCTRL_##dr##_DIV; \406 reg |= div << BP_CLKCTRL_##dr##_DIV; \
407 if (reg | (1 << clk->enable_shift)) { \407 if (reg & (1 << clk->enable_shift)) { \
408 pr_err("%s: clock is gated\n", __func__); \408 pr_err("%s: clock is gated\n", __func__); \
409 return -EINVAL; \409 return -EINVAL; \
410 } \410 } \
arch/arm/mach-omap1/Kconfig+0−8
@@ -171,14 +171,6 @@ config MACH_OMAP_GENERIC · 170 unmodified lines
171comment "OMAP CPU Speed"171comment "OMAP CPU Speed"
172 depends on ARCH_OMAP1172 depends on ARCH_OMAP1
173 173
174config OMAP_CLOCKS_SET_BY_BOOTLOADER
175 bool "OMAP clocks set by bootloader"
176 depends on ARCH_OMAP1
177 help
178 Enable this option to prevent the kernel from overriding the clock
179 frequencies programmed by bootloader for MPU, DSP, MMUs, TC,
180 internal LCD controller and MPU peripherals.
181
182config OMAP_ARM_216MHZ174config OMAP_ARM_216MHZ
183 bool "OMAP ARM 216 MHz CPU (1710 only)"175 bool "OMAP ARM 216 MHz CPU (1710 only)"
184 depends on ARCH_OMAP1 && ARCH_OMAP16XX176 depends on ARCH_OMAP1 && ARCH_OMAP16XX
arch/arm/mach-omap1/board-ams-delta.c+7−3
@@ -302,8 +302,6 @@ static void __init ams_delta_init(void) · 301 unmodified lines
302 omap_cfg_reg(J19_1610_CAM_D6);302 omap_cfg_reg(J19_1610_CAM_D6);
303 omap_cfg_reg(J18_1610_CAM_D7);303 omap_cfg_reg(J18_1610_CAM_D7);
304 304
305 iotable_init(ams_delta_io_desc, ARRAY_SIZE(ams_delta_io_desc));
306
307 omap_board_config = ams_delta_config;305 omap_board_config = ams_delta_config;
308 omap_board_config_size = ARRAY_SIZE(ams_delta_config);306 omap_board_config_size = ARRAY_SIZE(ams_delta_config);
309 omap_serial_init();307 omap_serial_init();
@@ -373,10 +371,16 @@ static int __init ams_delta_modem_init(void) · 63 unmodified lines
373}371}
374arch_initcall(ams_delta_modem_init);372arch_initcall(ams_delta_modem_init);
375 373
374static void __init ams_delta_map_io(void)
375{
376 omap15xx_map_io();
377 iotable_init(ams_delta_io_desc, ARRAY_SIZE(ams_delta_io_desc));
378}
379
376MACHINE_START(AMS_DELTA, "Amstrad E3 (Delta)")380MACHINE_START(AMS_DELTA, "Amstrad E3 (Delta)")
377 /* Maintainer: Jonathan McDowell <noodles@earth.li> */381 /* Maintainer: Jonathan McDowell <noodles@earth.li> */
378 .atag_offset = 0x100,382 .atag_offset = 0x100,
379 .map_io = omap15xx_map_io,383 .map_io = ams_delta_map_io,
380 .init_early = omap1_init_early,384 .init_early = omap1_init_early,
381 .reserve = omap_reserve,385 .reserve = omap_reserve,
382 .init_irq = omap1_init_irq,386 .init_irq = omap1_init_irq,
arch/arm/mach-omap1/clock.h+2−1
@@ -17,7 +17,8 @@ · 16 unmodified lines
17 17
18#include <plat/clock.h>18#include <plat/clock.h>
19 19
20extern int __init omap1_clk_init(void);20int omap1_clk_init(void);
21void omap1_clk_late_init(void);
21extern int omap1_clk_enable(struct clk *clk);22extern int omap1_clk_enable(struct clk *clk);
22extern void omap1_clk_disable(struct clk *clk);23extern void omap1_clk_disable(struct clk *clk);
23extern long omap1_clk_round_rate(struct clk *clk, unsigned long rate);24extern long omap1_clk_round_rate(struct clk *clk, unsigned long rate);
arch/arm/mach-omap1/clock_data.c+34−19
@@ -767,6 +767,15 @@ static struct clk_functions omap1_clk_functions = { · 766 unmodified lines
767 .clk_disable_unused = omap1_clk_disable_unused,767 .clk_disable_unused = omap1_clk_disable_unused,
768};768};
769 769
770static void __init omap1_show_rates(void)
771{
772 pr_notice("Clocking rate (xtal/DPLL1/MPU): "
773 "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
774 ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
775 ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
776 arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
777}
778
770int __init omap1_clk_init(void)779int __init omap1_clk_init(void)
771{780{
772 struct omap_clk *c;781 struct omap_clk *c;
@@ -835,9 +844,12 @@ int __init omap1_clk_init(void) · 62 unmodified lines
835 /* We want to be in syncronous scalable mode */844 /* We want to be in syncronous scalable mode */
836 omap_writew(0x1000, ARM_SYSST);845 omap_writew(0x1000, ARM_SYSST);
837 846
838#ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER847
839 /* Use values set by bootloader. Determine PLL rate and recalculate848 /*
840 * dependent clocks as if kernel had changed PLL or divisors.849 * Initially use the values set by bootloader. Determine PLL rate and
850 * recalculate dependent clocks as if kernel had changed PLL or
851 * divisors. See also omap1_clk_late_init() that can reprogram dpll1
852 * after the SRAM is initialized.
841 */853 */
842 {854 {
843 unsigned pll_ctl_val = omap_readw(DPLL_CTL);855 unsigned pll_ctl_val = omap_readw(DPLL_CTL);
@@ -862,25 +874,10 @@ int __init omap1_clk_init(void) · 18 unmodified lines
862 }874 }
863 }875 }
864 }876 }
865#else
866 /* Find the highest supported frequency and enable it */
867 if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
868 printk(KERN_ERR "System frequencies not set. Check your config.\n");
869 /* Guess sane values (60MHz) */
870 omap_writew(0x2290, DPLL_CTL);
871 omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL);
872 ck_dpll1.rate = 60000000;
873 }
874#endif
875 propagate_rate(&ck_dpll1);877 propagate_rate(&ck_dpll1);
876 /* Cache rates for clocks connected to ck_ref (not dpll1) */878 /* Cache rates for clocks connected to ck_ref (not dpll1) */
877 propagate_rate(&ck_ref);879 propagate_rate(&ck_ref);
878 printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): "880 omap1_show_rates();
879 "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
880 ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
881 ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
882 arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
883
884 if (machine_is_omap_perseus2() || machine_is_omap_fsample()) {881 if (machine_is_omap_perseus2() || machine_is_omap_fsample()) {
885 /* Select slicer output as OMAP input clock */882 /* Select slicer output as OMAP input clock */
886 omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1,883 omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1,
@@ -925,3 +922,21 @@ int __init omap1_clk_init(void) · 38 unmodified lines
925 922
926 return 0;923 return 0;
927}924}
925
926#define OMAP1_DPLL1_SANE_VALUE 60000000
927
928void __init omap1_clk_late_init(void)
929{
930 if (ck_dpll1.rate >= OMAP1_DPLL1_SANE_VALUE)
931 return;
932
933 /* Find the highest supported frequency and enable it */
934 if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
935 pr_err("System frequencies not set, using default. Check your config.\n");
936 omap_writew(0x2290, DPLL_CTL);
937 omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL);
938 ck_dpll1.rate = OMAP1_DPLL1_SANE_VALUE;
939 }
940 propagate_rate(&ck_dpll1);
941 omap1_show_rates();
942}
arch/arm/mach-omap1/devices.c+3−0
@@ -30,6 +30,8 @@ · 29 unmodified lines
30#include <plat/omap7xx.h>30#include <plat/omap7xx.h>
31#include <plat/mcbsp.h>31#include <plat/mcbsp.h>
32 32
33#include "clock.h"
34
33/*-------------------------------------------------------------------------*/35/*-------------------------------------------------------------------------*/
34 36
35#if defined(CONFIG_RTC_DRV_OMAP) || defined(CONFIG_RTC_DRV_OMAP_MODULE)37#if defined(CONFIG_RTC_DRV_OMAP) || defined(CONFIG_RTC_DRV_OMAP_MODULE)
@@ -293,6 +295,7 @@ static int __init omap1_init_devices(void) · 257 unmodified lines
293 return -ENODEV;295 return -ENODEV;
294 296
295 omap_sram_init();297 omap_sram_init();
298 omap1_clk_late_init();
296 299
297 /* please keep these calls, and their implementations above,300 /* please keep these calls, and their implementations above,
298 * in alphabetical order so they're easier to sort through.301 * in alphabetical order so they're easier to sort through.
arch/arm/mach-omap2/Kconfig+1−0
@@ -334,6 +334,7 @@ config MACH_OMAP4_PANDA · 333 unmodified lines
334config OMAP3_EMU334config OMAP3_EMU
335 bool "OMAP3 debugging peripherals"335 bool "OMAP3 debugging peripherals"
336 depends on ARCH_OMAP3336 depends on ARCH_OMAP3
337 select ARM_AMBA
337 select OC_ETM338 select OC_ETM
338 help339 help
339 Say Y here to enable debugging hardware of omap3340 Say Y here to enable debugging hardware of omap3
arch/arm/mach-omap2/Makefile+1−4
@@ -4,7 +4,7 @@ · 3 unmodified lines
4 4
5# Common support5# Common support
6obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \6obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \
7 common.o gpio.o dma.o wd_timer.o7 common.o gpio.o dma.o wd_timer.o display.o
8 8
9omap-2-3-common = irq.o sdrc.o9omap-2-3-common = irq.o sdrc.o
10hwmod-common = omap_hwmod.o \10hwmod-common = omap_hwmod.o \
@@ -264,7 +264,4 @@ smsc911x-$(CONFIG_SMSC911X) := gpmc-smsc911x.o · 253 unmodified lines
264obj-y += $(smsc911x-m) $(smsc911x-y)264obj-y += $(smsc911x-m) $(smsc911x-y)
265obj-$(CONFIG_ARCH_OMAP4) += hwspinlock.o265obj-$(CONFIG_ARCH_OMAP4) += hwspinlock.o
266 266
267disp-$(CONFIG_OMAP2_DSS) := display.o
268obj-y += $(disp-m) $(disp-y)
269
270obj-y += common-board-devices.o twl-common.o267obj-y += common-board-devices.o twl-common.o
arch/arm/mach-omap2/cpuidle34xx.c+1−0
@@ -24,6 +24,7 @@ · 23 unmodified lines
24 24
25#include <linux/sched.h>25#include <linux/sched.h>
26#include <linux/cpuidle.h>26#include <linux/cpuidle.h>
27#include <linux/export.h>
27 28
28#include <plat/prcm.h>29#include <plat/prcm.h>
29#include <plat/irqs.h>30#include <plat/irqs.h>
arch/arm/mach-omap2/display.c+159−0
@@ -27,8 +27,35 @@ · 26 unmodified lines
27#include <plat/omap_hwmod.h>27#include <plat/omap_hwmod.h>
28#include <plat/omap_device.h>28#include <plat/omap_device.h>
29#include <plat/omap-pm.h>29#include <plat/omap-pm.h>
30#include <plat/common.h>
30 31
31#include "control.h"32#include "control.h"
33#include "display.h"
34
35#define DISPC_CONTROL 0x0040
36#define DISPC_CONTROL2 0x0238
37#define DISPC_IRQSTATUS 0x0018
38
39#define DSS_SYSCONFIG 0x10
40#define DSS_SYSSTATUS 0x14
41#define DSS_CONTROL 0x40
42#define DSS_SDI_CONTROL 0x44
43#define DSS_PLL_CONTROL 0x48
44
45#define LCD_EN_MASK (0x1 << 0)
46#define DIGIT_EN_MASK (0x1 << 1)
47
48#define FRAMEDONE_IRQ_SHIFT 0
49#define EVSYNC_EVEN_IRQ_SHIFT 2
50#define EVSYNC_ODD_IRQ_SHIFT 3
51#define FRAMEDONE2_IRQ_SHIFT 22
52#define FRAMEDONETV_IRQ_SHIFT 24
53
54/*
55 * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
56 * reset before deciding that something has gone wrong
57 */
58#define FRAMEDONE_IRQ_TIMEOUT 100
32 59
33static struct platform_device omap_display_device = {60static struct platform_device omap_display_device = {
34 .name = "omapdss",61 .name = "omapdss",
@@ -172,3 +199,135 @@ int __init omap_display_init(struct omap_dss_board_info *board_data) · 137 unmodified lines
172 199
173 return r;200 return r;
174}201}
202
203static void dispc_disable_outputs(void)
204{
205 u32 v, irq_mask = 0;
206 bool lcd_en, digit_en, lcd2_en = false;
207 int i;
208 struct omap_dss_dispc_dev_attr *da;
209 struct omap_hwmod *oh;
210
211 oh = omap_hwmod_lookup("dss_dispc");
212 if (!oh) {
213 WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
214 return;
215 }
216
217 if (!oh->dev_attr) {
218 pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
219 return;
220 }
221
222 da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;
223
224 /* store value of LCDENABLE and DIGITENABLE bits */
225 v = omap_hwmod_read(oh, DISPC_CONTROL);
226 lcd_en = v & LCD_EN_MASK;
227 digit_en = v & DIGIT_EN_MASK;
228
229 /* store value of LCDENABLE for LCD2 */
230 if (da->manager_count > 2) {
231 v = omap_hwmod_read(oh, DISPC_CONTROL2);
232 lcd2_en = v & LCD_EN_MASK;
233 }
234
235 if (!(lcd_en | digit_en | lcd2_en))
236 return; /* no managers currently enabled */
237
238 /*
239 * If any manager was enabled, we need to disable it before
240 * DSS clocks are disabled or DISPC module is reset
241 */
242 if (lcd_en)
243 irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT;
244
245 if (digit_en) {
246 if (da->has_framedonetv_irq) {
247 irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT;
248 } else {
249 irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT |
250 1 << EVSYNC_ODD_IRQ_SHIFT;
251 }
252 }
253
254 if (lcd2_en)
255 irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT;
256
257 /*
258 * clear any previous FRAMEDONE, FRAMEDONETV,
259 * EVSYNC_EVEN/ODD or FRAMEDONE2 interrupts
260 */
261 omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);
262
263 /* disable LCD and TV managers */
264 v = omap_hwmod_read(oh, DISPC_CONTROL);
265 v &= ~(LCD_EN_MASK | DIGIT_EN_MASK);
266 omap_hwmod_write(v, oh, DISPC_CONTROL);
267
268 /* disable LCD2 manager */
269 if (da->manager_count > 2) {
270 v = omap_hwmod_read(oh, DISPC_CONTROL2);
271 v &= ~LCD_EN_MASK;
272 omap_hwmod_write(v, oh, DISPC_CONTROL2);
273 }
274
275 i = 0;
276 while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
277 irq_mask) {
278 i++;
279 if (i > FRAMEDONE_IRQ_TIMEOUT) {
280 pr_err("didn't get FRAMEDONE1/2 or TV interrupt\n");
281 break;
282 }
283 mdelay(1);
284 }
285}
286
287#define MAX_MODULE_SOFTRESET_WAIT 10000
288int omap_dss_reset(struct omap_hwmod *oh)
289{
290 struct omap_hwmod_opt_clk *oc;
291 int c = 0;
292 int i, r;
293
294 if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
295 pr_err("dss_core: hwmod data doesn't contain reset data\n");
296 return -EINVAL;
297 }
298
299 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
300 if (oc->_clk)
301 clk_enable(oc->_clk);
302
303 dispc_disable_outputs();
304
305 /* clear SDI registers */
306 if (cpu_is_omap3430()) {
307 omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
308 omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
309 }
310
311 /*
312 * clear DSS_CONTROL register to switch DSS clock sources to
313 * PRCM clock, if any
314 */
315 omap_hwmod_write(0x0, oh, DSS_CONTROL);
316
317 omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
318 & SYSS_RESETDONE_MASK),
319 MAX_MODULE_SOFTRESET_WAIT, c);
320
321 if (c == MAX_MODULE_SOFTRESET_WAIT)
322 pr_warning("dss_core: waiting for reset to finish failed\n");
323 else
324 pr_debug("dss_core: softreset done\n");
325
326 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
327 if (oc->_clk)
328 clk_disable(oc->_clk);
329
330 r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
331
332 return r;
333}
arch/arm/mach-omap2/display.h+29−0
@@ -0,0 +1,29 @@
1/*
2 * display.h - OMAP2+ integration-specific DSS header
3 *
4 * Copyright (C) 2011 Texas Instruments, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by
8 * the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#ifndef __ARCH_ARM_MACH_OMAP2_DISPLAY_H
20#define __ARCH_ARM_MACH_OMAP2_DISPLAY_H
21
22#include <linux/kernel.h>
23
24struct omap_dss_dispc_dev_attr {
25 u8 manager_count;
26 bool has_framedonetv_irq;
27};
28
29#endif
arch/arm/mach-omap2/io.h+0−0

Empty file deleted.

arch/arm/mach-omap2/omap_hwmod.c+3−3
@@ -749,7 +749,7 @@ static int _count_mpu_irqs(struct omap_hwmod *oh) · 748 unmodified lines
749 ohii = &oh->mpu_irqs[i++];749 ohii = &oh->mpu_irqs[i++];
750 } while (ohii->irq != -1);750 } while (ohii->irq != -1);
751 751
752 return i;752 return i-1;
753}753}
754 754
755/**755/**
@@ -772,7 +772,7 @@ static int _count_sdma_reqs(struct omap_hwmod *oh) · 16 unmodified lines
772 ohdi = &oh->sdma_reqs[i++];772 ohdi = &oh->sdma_reqs[i++];
773 } while (ohdi->dma_req != -1);773 } while (ohdi->dma_req != -1);
774 774
775 return i;775 return i-1;
776}776}
777 777
778/**778/**
@@ -795,7 +795,7 @@ static int _count_ocp_if_addr_spaces(struct omap_hwmod_ocp_if *os) · 16 unmodified lines
795 mem = &os->addr[i++];795 mem = &os->addr[i++];
796 } while (mem->pa_start != mem->pa_end);796 } while (mem->pa_start != mem->pa_end);
797 797
798 return i;798 return i-1;
799}799}
800 800
801/**801/**
arch/arm/mach-omap2/omap_hwmod_2420_data.c+14−3
@@ -875,6 +875,10 @@ static struct omap_hwmod_ocp_if *omap2420_dss_slaves[] = { · 874 unmodified lines
875};875};
876 876
877static struct omap_hwmod_opt_clk dss_opt_clks[] = {877static struct omap_hwmod_opt_clk dss_opt_clks[] = {
878 /*
879 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
880 * driver does not use these clocks.
881 */
878 { .role = "tv_clk", .clk = "dss_54m_fck" },882 { .role = "tv_clk", .clk = "dss_54m_fck" },
879 { .role = "sys_clk", .clk = "dss2_fck" },883 { .role = "sys_clk", .clk = "dss2_fck" },
880};884};
@@ -899,7 +903,7 @@ static struct omap_hwmod omap2420_dss_core_hwmod = { · 18 unmodified lines
899 .slaves_cnt = ARRAY_SIZE(omap2420_dss_slaves),903 .slaves_cnt = ARRAY_SIZE(omap2420_dss_slaves),
900 .masters = omap2420_dss_masters,904 .masters = omap2420_dss_masters,
901 .masters_cnt = ARRAY_SIZE(omap2420_dss_masters),905 .masters_cnt = ARRAY_SIZE(omap2420_dss_masters),
902 .flags = HWMOD_NO_IDLEST,906 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
903};907};
904 908
905/* l4_core -> dss_dispc */909/* l4_core -> dss_dispc */
@@ -939,6 +943,7 @@ static struct omap_hwmod omap2420_dss_dispc_hwmod = { · 33 unmodified lines
939 .slaves = omap2420_dss_dispc_slaves,943 .slaves = omap2420_dss_dispc_slaves,
940 .slaves_cnt = ARRAY_SIZE(omap2420_dss_dispc_slaves),944 .slaves_cnt = ARRAY_SIZE(omap2420_dss_dispc_slaves),
941 .flags = HWMOD_NO_IDLEST,945 .flags = HWMOD_NO_IDLEST,
946 .dev_attr = &omap2_3_dss_dispc_dev_attr
942};947};
943 948
944/* l4_core -> dss_rfbi */949/* l4_core -> dss_rfbi */
@@ -961,6 +966,10 @@ static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = { · 16 unmodified lines
961 &omap2420_l4_core__dss_rfbi,966 &omap2420_l4_core__dss_rfbi,
962};967};
963 968
969static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
970 { .role = "ick", .clk = "dss_ick" },
971};
972
964static struct omap_hwmod omap2420_dss_rfbi_hwmod = {973static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
965 .name = "dss_rfbi",974 .name = "dss_rfbi",
966 .class = &omap2_rfbi_hwmod_class,975 .class = &omap2_rfbi_hwmod_class,
@@ -972,6 +981,8 @@ static struct omap_hwmod omap2420_dss_rfbi_hwmod = { · 5 unmodified lines
972 .module_offs = CORE_MOD,981 .module_offs = CORE_MOD,
973 },982 },
974 },983 },
984 .opt_clks = dss_rfbi_opt_clks,
985 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
975 .slaves = omap2420_dss_rfbi_slaves,986 .slaves = omap2420_dss_rfbi_slaves,
976 .slaves_cnt = ARRAY_SIZE(omap2420_dss_rfbi_slaves),987 .slaves_cnt = ARRAY_SIZE(omap2420_dss_rfbi_slaves),
977 .flags = HWMOD_NO_IDLEST,988 .flags = HWMOD_NO_IDLEST,
@@ -981,7 +992,7 @@ static struct omap_hwmod omap2420_dss_rfbi_hwmod = { · 3 unmodified lines
981static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {992static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
982 .master = &omap2420_l4_core_hwmod,993 .master = &omap2420_l4_core_hwmod,
983 .slave = &omap2420_dss_venc_hwmod,994 .slave = &omap2420_dss_venc_hwmod,
984 .clk = "dss_54m_fck",995 .clk = "dss_ick",
985 .addr = omap2_dss_venc_addrs,996 .addr = omap2_dss_venc_addrs,
986 .fw = {997 .fw = {
987 .omap2 = {998 .omap2 = {
@@ -1001,7 +1012,7 @@ static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = { · 13 unmodified lines
1001static struct omap_hwmod omap2420_dss_venc_hwmod = {1012static struct omap_hwmod omap2420_dss_venc_hwmod = {
1002 .name = "dss_venc",1013 .name = "dss_venc",
1003 .class = &omap2_venc_hwmod_class,1014 .class = &omap2_venc_hwmod_class,
1004 .main_clk = "dss1_fck",1015 .main_clk = "dss_54m_fck",
1005 .prcm = {1016 .prcm = {
1006 .omap2 = {1017 .omap2 = {
1007 .prcm_reg_id = 1,1018 .prcm_reg_id = 1,
arch/arm/mach-omap2/omap_hwmod_2430_data.c+14−3
@@ -942,6 +942,10 @@ static struct omap_hwmod_ocp_if *omap2430_dss_slaves[] = { · 941 unmodified lines
942};942};
943 943
944static struct omap_hwmod_opt_clk dss_opt_clks[] = {944static struct omap_hwmod_opt_clk dss_opt_clks[] = {
945 /*
946 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
947 * driver does not use these clocks.
948 */
945 { .role = "tv_clk", .clk = "dss_54m_fck" },949 { .role = "tv_clk", .clk = "dss_54m_fck" },
946 { .role = "sys_clk", .clk = "dss2_fck" },950 { .role = "sys_clk", .clk = "dss2_fck" },
947};951};
@@ -966,7 +970,7 @@ static struct omap_hwmod omap2430_dss_core_hwmod = { · 18 unmodified lines
966 .slaves_cnt = ARRAY_SIZE(omap2430_dss_slaves),970 .slaves_cnt = ARRAY_SIZE(omap2430_dss_slaves),
967 .masters = omap2430_dss_masters,971 .masters = omap2430_dss_masters,
968 .masters_cnt = ARRAY_SIZE(omap2430_dss_masters),972 .masters_cnt = ARRAY_SIZE(omap2430_dss_masters),
969 .flags = HWMOD_NO_IDLEST,973 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
970};974};
971 975
972/* l4_core -> dss_dispc */976/* l4_core -> dss_dispc */
@@ -1000,6 +1004,7 @@ static struct omap_hwmod omap2430_dss_dispc_hwmod = { · 27 unmodified lines
1000 .slaves = omap2430_dss_dispc_slaves,1004 .slaves = omap2430_dss_dispc_slaves,
1001 .slaves_cnt = ARRAY_SIZE(omap2430_dss_dispc_slaves),1005 .slaves_cnt = ARRAY_SIZE(omap2430_dss_dispc_slaves),
1002 .flags = HWMOD_NO_IDLEST,1006 .flags = HWMOD_NO_IDLEST,
1007 .dev_attr = &omap2_3_dss_dispc_dev_attr
1003};1008};
1004 1009
1005/* l4_core -> dss_rfbi */1010/* l4_core -> dss_rfbi */
@@ -1016,6 +1021,10 @@ static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = { · 10 unmodified lines
1016 &omap2430_l4_core__dss_rfbi,1021 &omap2430_l4_core__dss_rfbi,
1017};1022};
1018 1023
1024static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1025 { .role = "ick", .clk = "dss_ick" },
1026};
1027
1019static struct omap_hwmod omap2430_dss_rfbi_hwmod = {1028static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
1020 .name = "dss_rfbi",1029 .name = "dss_rfbi",
1021 .class = &omap2_rfbi_hwmod_class,1030 .class = &omap2_rfbi_hwmod_class,
@@ -1027,6 +1036,8 @@ static struct omap_hwmod omap2430_dss_rfbi_hwmod = { · 5 unmodified lines
1027 .module_offs = CORE_MOD,1036 .module_offs = CORE_MOD,
1028 },1037 },
1029 },1038 },
1039 .opt_clks = dss_rfbi_opt_clks,
1040 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
1030 .slaves = omap2430_dss_rfbi_slaves,1041 .slaves = omap2430_dss_rfbi_slaves,
1031 .slaves_cnt = ARRAY_SIZE(omap2430_dss_rfbi_slaves),1042 .slaves_cnt = ARRAY_SIZE(omap2430_dss_rfbi_slaves),
1032 .flags = HWMOD_NO_IDLEST,1043 .flags = HWMOD_NO_IDLEST,
@@ -1036,7 +1047,7 @@ static struct omap_hwmod omap2430_dss_rfbi_hwmod = { · 3 unmodified lines
1036static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {1047static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
1037 .master = &omap2430_l4_core_hwmod,1048 .master = &omap2430_l4_core_hwmod,
1038 .slave = &omap2430_dss_venc_hwmod,1049 .slave = &omap2430_dss_venc_hwmod,
1039 .clk = "dss_54m_fck",1050 .clk = "dss_ick",
1040 .addr = omap2_dss_venc_addrs,1051 .addr = omap2_dss_venc_addrs,
1041 .flags = OCPIF_SWSUP_IDLE,1052 .flags = OCPIF_SWSUP_IDLE,
1042 .user = OCP_USER_MPU | OCP_USER_SDMA,1053 .user = OCP_USER_MPU | OCP_USER_SDMA,
@@ -1050,7 +1061,7 @@ static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = { · 7 unmodified lines
1050static struct omap_hwmod omap2430_dss_venc_hwmod = {1061static struct omap_hwmod omap2430_dss_venc_hwmod = {
1051 .name = "dss_venc",1062 .name = "dss_venc",
1052 .class = &omap2_venc_hwmod_class,1063 .class = &omap2_venc_hwmod_class,
1053 .main_clk = "dss1_fck",1064 .main_clk = "dss_54m_fck",
1054 .prcm = {1065 .prcm = {
1055 .omap2 = {1066 .omap2 = {
1056 .prcm_reg_id = 1,1067 .prcm_reg_id = 1,
arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c+4−1
@@ -11,6 +11,7 @@ · 10 unmodified lines
11#include <plat/omap_hwmod.h>11#include <plat/omap_hwmod.h>
12#include <plat/serial.h>12#include <plat/serial.h>
13#include <plat/dma.h>13#include <plat/dma.h>
14#include <plat/common.h>
14 15
15#include <mach/irqs.h>16#include <mach/irqs.h>
16 17
@@ -43,13 +44,15 @@ static struct omap_hwmod_class_sysconfig omap2_dss_sysc = { · 26 unmodified lines
43 .rev_offs = 0x0000,44 .rev_offs = 0x0000,
44 .sysc_offs = 0x0010,45 .sysc_offs = 0x0010,
45 .syss_offs = 0x0014,46 .syss_offs = 0x0014,
46 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),47 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
48 SYSS_HAS_RESET_STATUS),
47 .sysc_fields = &omap_hwmod_sysc_type1,49 .sysc_fields = &omap_hwmod_sysc_type1,
48};50};
49 51
50struct omap_hwmod_class omap2_dss_hwmod_class = {52struct omap_hwmod_class omap2_dss_hwmod_class = {
51 .name = "dss",53 .name = "dss",
52 .sysc = &omap2_dss_sysc,54 .sysc = &omap2_dss_sysc,
55 .reset = omap_dss_reset,
53};56};
54 57
55/*58/*
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c+32−5
@@ -1369,9 +1369,14 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = { · 1368 unmodified lines
1369};1369};
1370 1370
1371static struct omap_hwmod_opt_clk dss_opt_clks[] = {1371static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1372 { .role = "tv_clk", .clk = "dss_tv_fck" },1372 /*
1373 { .role = "video_clk", .clk = "dss_96m_fck" },1373 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
1374 * driver does not use these clocks.
1375 */
1374 { .role = "sys_clk", .clk = "dss2_alwon_fck" },1376 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1377 { .role = "tv_clk", .clk = "dss_tv_fck" },
1378 /* required only on OMAP3430 */
1379 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
1375};1380};
1376 1381
1377static struct omap_hwmod omap3430es1_dss_core_hwmod = {1382static struct omap_hwmod omap3430es1_dss_core_hwmod = {
@@ -1394,11 +1399,12 @@ static struct omap_hwmod omap3430es1_dss_core_hwmod = { · 16 unmodified lines
1394 .slaves_cnt = ARRAY_SIZE(omap3430es1_dss_slaves),1399 .slaves_cnt = ARRAY_SIZE(omap3430es1_dss_slaves),
1395 .masters = omap3xxx_dss_masters,1400 .masters = omap3xxx_dss_masters,
1396 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),1401 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
1397 .flags = HWMOD_NO_IDLEST,1402 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1398};1403};
1399 1404
1400static struct omap_hwmod omap3xxx_dss_core_hwmod = {1405static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1401 .name = "dss_core",1406 .name = "dss_core",
1407 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1402 .class = &omap2_dss_hwmod_class,1408 .class = &omap2_dss_hwmod_class,
1403 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */1409 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
1404 .sdma_reqs = omap3xxx_dss_sdma_chs,1410 .sdma_reqs = omap3xxx_dss_sdma_chs,
@@ -1456,6 +1462,7 @@ static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { · 51 unmodified lines
1456 .slaves = omap3xxx_dss_dispc_slaves,1462 .slaves = omap3xxx_dss_dispc_slaves,
1457 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),1463 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
1458 .flags = HWMOD_NO_IDLEST,1464 .flags = HWMOD_NO_IDLEST,
1465 .dev_attr = &omap2_3_dss_dispc_dev_attr
1459};1466};
1460 1467
1461/*1468/*
@@ -1486,6 +1493,7 @@ static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = { · 24 unmodified lines
1486static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {1493static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1487 .master = &omap3xxx_l4_core_hwmod,1494 .master = &omap3xxx_l4_core_hwmod,
1488 .slave = &omap3xxx_dss_dsi1_hwmod,1495 .slave = &omap3xxx_dss_dsi1_hwmod,
1496 .clk = "dss_ick",
1489 .addr = omap3xxx_dss_dsi1_addrs,1497 .addr = omap3xxx_dss_dsi1_addrs,
1490 .fw = {1498 .fw = {
1491 .omap2 = {1499 .omap2 = {
@@ -1502,6 +1510,10 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = { · 10 unmodified lines
1502 &omap3xxx_l4_core__dss_dsi1,1510 &omap3xxx_l4_core__dss_dsi1,
1503};1511};
1504 1512
1513static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1514 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1515};
1516
1505static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {1517static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1506 .name = "dss_dsi1",1518 .name = "dss_dsi1",
1507 .class = &omap3xxx_dsi_hwmod_class,1519 .class = &omap3xxx_dsi_hwmod_class,
@@ -1514,6 +1526,8 @@ static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = { · 6 unmodified lines
1514 .module_offs = OMAP3430_DSS_MOD,1526 .module_offs = OMAP3430_DSS_MOD,
1515 },1527 },
1516 },1528 },
1529 .opt_clks = dss_dsi1_opt_clks,
1530 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
1517 .slaves = omap3xxx_dss_dsi1_slaves,1531 .slaves = omap3xxx_dss_dsi1_slaves,
1518 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),1532 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
1519 .flags = HWMOD_NO_IDLEST,1533 .flags = HWMOD_NO_IDLEST,
@@ -1540,6 +1554,10 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = { · 20 unmodified lines
1540 &omap3xxx_l4_core__dss_rfbi,1554 &omap3xxx_l4_core__dss_rfbi,
1541};1555};
1542 1556
1557static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1558 { .role = "ick", .clk = "dss_ick" },
1559};
1560
1543static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {1561static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1544 .name = "dss_rfbi",1562 .name = "dss_rfbi",
1545 .class = &omap2_rfbi_hwmod_class,1563 .class = &omap2_rfbi_hwmod_class,
@@ -1551,6 +1569,8 @@ static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = { · 5 unmodified lines
1551 .module_offs = OMAP3430_DSS_MOD,1569 .module_offs = OMAP3430_DSS_MOD,
1552 },1570 },
1553 },1571 },
1572 .opt_clks = dss_rfbi_opt_clks,
1573 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
1554 .slaves = omap3xxx_dss_rfbi_slaves,1574 .slaves = omap3xxx_dss_rfbi_slaves,
1555 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),1575 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
1556 .flags = HWMOD_NO_IDLEST,1576 .flags = HWMOD_NO_IDLEST,
@@ -1560,7 +1580,7 @@ static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = { · 3 unmodified lines
1560static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {1580static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1561 .master = &omap3xxx_l4_core_hwmod,1581 .master = &omap3xxx_l4_core_hwmod,
1562 .slave = &omap3xxx_dss_venc_hwmod,1582 .slave = &omap3xxx_dss_venc_hwmod,
1563 .clk = "dss_tv_fck",1583 .clk = "dss_ick",
1564 .addr = omap2_dss_venc_addrs,1584 .addr = omap2_dss_venc_addrs,
1565 .fw = {1585 .fw = {
1566 .omap2 = {1586 .omap2 = {
@@ -1578,10 +1598,15 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = { · 11 unmodified lines
1578 &omap3xxx_l4_core__dss_venc,1598 &omap3xxx_l4_core__dss_venc,
1579};1599};
1580 1600
1601static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
1602 /* required only on OMAP3430 */
1603 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
1604};
1605
1581static struct omap_hwmod omap3xxx_dss_venc_hwmod = {1606static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1582 .name = "dss_venc",1607 .name = "dss_venc",
1583 .class = &omap2_venc_hwmod_class,1608 .class = &omap2_venc_hwmod_class,
1584 .main_clk = "dss1_alwon_fck",1609 .main_clk = "dss_tv_fck",
1585 .prcm = {1610 .prcm = {
1586 .omap2 = {1611 .omap2 = {
1587 .prcm_reg_id = 1,1612 .prcm_reg_id = 1,
@@ -1589,6 +1614,8 @@ static struct omap_hwmod omap3xxx_dss_venc_hwmod = { · 1 unmodified line
1589 .module_offs = OMAP3430_DSS_MOD,1614 .module_offs = OMAP3430_DSS_MOD,
1590 },1615 },
1591 },1616 },
1617 .opt_clks = dss_venc_opt_clks,
1618 .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks),
1592 .slaves = omap3xxx_dss_venc_slaves,1619 .slaves = omap3xxx_dss_venc_slaves,
1593 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_venc_slaves),1620 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
1594 .flags = HWMOD_NO_IDLEST,1621 .flags = HWMOD_NO_IDLEST,
arch/arm/mach-omap2/omap_hwmod_44xx_data.c+12−12
@@ -30,6 +30,7 @@ · 29 unmodified lines
30#include <plat/mmc.h>30#include <plat/mmc.h>
31#include <plat/i2c.h>31#include <plat/i2c.h>
32#include <plat/dmtimer.h>32#include <plat/dmtimer.h>
33#include <plat/common.h>
33 34
34#include "omap_hwmod_common_data.h"35#include "omap_hwmod_common_data.h"
35 36
@@ -1187,6 +1188,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = { · 1151 unmodified lines
1187static struct omap_hwmod_class omap44xx_dss_hwmod_class = {1188static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
1188 .name = "dss",1189 .name = "dss",
1189 .sysc = &omap44xx_dss_sysc,1190 .sysc = &omap44xx_dss_sysc,
1191 .reset = omap_dss_reset,
1190};1192};
1191 1193
1192/* dss */1194/* dss */
@@ -1240,12 +1242,12 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = { · 47 unmodified lines
1240static struct omap_hwmod_opt_clk dss_opt_clks[] = {1242static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1241 { .role = "sys_clk", .clk = "dss_sys_clk" },1243 { .role = "sys_clk", .clk = "dss_sys_clk" },
1242 { .role = "tv_clk", .clk = "dss_tv_clk" },1244 { .role = "tv_clk", .clk = "dss_tv_clk" },
1243 { .role = "dss_clk", .clk = "dss_dss_clk" },1245 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
1244 { .role = "video_clk", .clk = "dss_48mhz_clk" },
1245};1246};
1246 1247
1247static struct omap_hwmod omap44xx_dss_hwmod = {1248static struct omap_hwmod omap44xx_dss_hwmod = {
1248 .name = "dss_core",1249 .name = "dss_core",
1250 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1249 .class = &omap44xx_dss_hwmod_class,1251 .class = &omap44xx_dss_hwmod_class,
1250 .clkdm_name = "l3_dss_clkdm",1252 .clkdm_name = "l3_dss_clkdm",
1251 .main_clk = "dss_dss_clk",1253 .main_clk = "dss_dss_clk",
@@ -1325,6 +1327,11 @@ static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = { · 73 unmodified lines
1325 { }1327 { }
1326};1328};
1327 1329
1330static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
1331 .manager_count = 3,
1332 .has_framedonetv_irq = 1
1333};
1334
1328/* l4_per -> dss_dispc */1335/* l4_per -> dss_dispc */
1329static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {1336static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
1330 .master = &omap44xx_l4_per_hwmod,1337 .master = &omap44xx_l4_per_hwmod,
@@ -1340,12 +1347,6 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = { · 9 unmodified lines
1340 &omap44xx_l4_per__dss_dispc,1347 &omap44xx_l4_per__dss_dispc,
1341};1348};
1342 1349
1343static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
1344 { .role = "sys_clk", .clk = "dss_sys_clk" },
1345 { .role = "tv_clk", .clk = "dss_tv_clk" },
1346 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
1347};
1348
1349static struct omap_hwmod omap44xx_dss_dispc_hwmod = {1350static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
1350 .name = "dss_dispc",1351 .name = "dss_dispc",
1351 .class = &omap44xx_dispc_hwmod_class,1352 .class = &omap44xx_dispc_hwmod_class,
@@ -1359,10 +1360,9 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = { · 7 unmodified lines
1359 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,1360 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1360 },1361 },
1361 },1362 },
1362 .opt_clks = dss_dispc_opt_clks,
1363 .opt_clks_cnt = ARRAY_SIZE(dss_dispc_opt_clks),
1364 .slaves = omap44xx_dss_dispc_slaves,1363 .slaves = omap44xx_dss_dispc_slaves,
1365 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves),1364 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
1365 .dev_attr = &omap44xx_dss_dispc_dev_attr
1366};1366};
1367 1367
1368/*1368/*
@@ -1624,7 +1624,7 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = { · 255 unmodified lines
1624 .clkdm_name = "l3_dss_clkdm",1624 .clkdm_name = "l3_dss_clkdm",
1625 .mpu_irqs = omap44xx_dss_hdmi_irqs,1625 .mpu_irqs = omap44xx_dss_hdmi_irqs,
1626 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,1626 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
1627 .main_clk = "dss_dss_clk",1627 .main_clk = "dss_48mhz_clk",
1628 .prcm = {1628 .prcm = {
1629 .omap4 = {1629 .omap4 = {
1630 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,1630 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
@@ -1785,7 +1785,7 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = { · 154 unmodified lines
1785 .name = "dss_venc",1785 .name = "dss_venc",
1786 .class = &omap44xx_venc_hwmod_class,1786 .class = &omap44xx_venc_hwmod_class,
1787 .clkdm_name = "l3_dss_clkdm",1787 .clkdm_name = "l3_dss_clkdm",
1788 .main_clk = "dss_dss_clk",1788 .main_clk = "dss_tv_clk",
1789 .prcm = {1789 .prcm = {
1790 .omap4 = {1790 .omap4 = {
1791 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,1791 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
arch/arm/mach-omap2/omap_hwmod_common_data.c+4−0
@@ -49,3 +49,7 @@ struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2 = { · 48 unmodified lines
49 .srst_shift = SYSC_TYPE2_SOFTRESET_SHIFT,49 .srst_shift = SYSC_TYPE2_SOFTRESET_SHIFT,
50};50};
51 51
52struct omap_dss_dispc_dev_attr omap2_3_dss_dispc_dev_attr = {
53 .manager_count = 2,
54 .has_framedonetv_irq = 0
55};
arch/arm/mach-omap2/omap_hwmod_common_data.h+4−0
@@ -16,6 +16,8 @@ · 15 unmodified lines
16 16
17#include <plat/omap_hwmod.h>17#include <plat/omap_hwmod.h>
18 18
19#include "display.h"
20
19/* Common address space across OMAP2xxx */21/* Common address space across OMAP2xxx */
20extern struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[];22extern struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[];
21extern struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[];23extern struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[];
@@ -111,4 +113,6 @@ extern struct omap_hwmod_class omap2xxx_dma_hwmod_class; · 89 unmodified lines
111extern struct omap_hwmod_class omap2xxx_mailbox_hwmod_class;113extern struct omap_hwmod_class omap2xxx_mailbox_hwmod_class;
112extern struct omap_hwmod_class omap2xxx_mcspi_class;114extern struct omap_hwmod_class omap2xxx_mcspi_class;
113 115
116extern struct omap_dss_dispc_dev_attr omap2_3_dss_dispc_dev_attr;
117
114#endif118#endif
arch/arm/mach-omap2/omap_l3_noc.c+1−1
@@ -237,7 +237,7 @@ static int __devexit omap4_l3_remove(struct platform_device *pdev) · 236 unmodified lines
237static const struct of_device_id l3_noc_match[] = {237static const struct of_device_id l3_noc_match[] = {
238 {.compatible = "ti,omap4-l3-noc", },238 {.compatible = "ti,omap4-l3-noc", },
239 {},239 {},
240}240};
241MODULE_DEVICE_TABLE(of, l3_noc_match);241MODULE_DEVICE_TABLE(of, l3_noc_match);
242#else242#else
243#define l3_noc_match NULL243#define l3_noc_match NULL
arch/arm/mach-omap2/pm.c+2−4
@@ -24,6 +24,7 @@ · 23 unmodified lines
24#include "powerdomain.h"24#include "powerdomain.h"
25#include "clockdomain.h"25#include "clockdomain.h"
26#include "pm.h"26#include "pm.h"
27#include "twl-common.h"
27 28
28static struct omap_device_pm_latency *pm_lats;29static struct omap_device_pm_latency *pm_lats;
29 30
@@ -226,11 +227,8 @@ postcore_initcall(omap2_common_pm_init); · 196 unmodified lines
226 227
227static int __init omap2_common_pm_late_init(void)228static int __init omap2_common_pm_late_init(void)
228{229{
229 /* Init the OMAP TWL parameters */
230 omap3_twl_init();
231 omap4_twl_init();
232
233 /* Init the voltage layer */230 /* Init the voltage layer */
231 omap_pmic_late_init();
234 omap_voltage_late_init();232 omap_voltage_late_init();
235 233
236 /* Initialize the voltages */234 /* Initialize the voltages */
arch/arm/mach-omap2/smartreflex.c+1−1
@@ -139,7 +139,7 @@ static irqreturn_t sr_interrupt(int irq, void *data) · 138 unmodified lines
139 sr_write_reg(sr_info, ERRCONFIG_V1, status);139 sr_write_reg(sr_info, ERRCONFIG_V1, status);
140 } else if (sr_info->ip_type == SR_TYPE_V2) {140 } else if (sr_info->ip_type == SR_TYPE_V2) {
141 /* Read the status bits */141 /* Read the status bits */
142 sr_read_reg(sr_info, IRQSTATUS);142 status = sr_read_reg(sr_info, IRQSTATUS);
143 143
144 /* Clear them by writing back */144 /* Clear them by writing back */
145 sr_write_reg(sr_info, IRQSTATUS, status);145 sr_write_reg(sr_info, IRQSTATUS, status);
arch/arm/mach-omap2/twl-common.c+11−0
@@ -30,6 +30,7 @@ · 29 unmodified lines
30#include <plat/usb.h>30#include <plat/usb.h>
31 31
32#include "twl-common.h"32#include "twl-common.h"
33#include "pm.h"
33 34
34static struct i2c_board_info __initdata pmic_i2c_board_info = {35static struct i2c_board_info __initdata pmic_i2c_board_info = {
35 .addr = 0x48,36 .addr = 0x48,
@@ -48,6 +49,16 @@ void __init omap_pmic_init(int bus, u32 clkrate, · 12 unmodified lines
48 omap_register_i2c_bus(bus, clkrate, &pmic_i2c_board_info, 1);49 omap_register_i2c_bus(bus, clkrate, &pmic_i2c_board_info, 1);
49}50}
50 51
52void __init omap_pmic_late_init(void)
53{
54 /* Init the OMAP TWL parameters (if PMIC has been registerd) */
55 if (!pmic_i2c_board_info.irq)
56 return;
57
58 omap3_twl_init();
59 omap4_twl_init();
60}
61
51#if defined(CONFIG_ARCH_OMAP3)62#if defined(CONFIG_ARCH_OMAP3)
52static struct twl4030_usb_data omap3_usb_pdata = {63static struct twl4030_usb_data omap3_usb_pdata = {
53 .usb_mode = T2_USB_MODE_ULPI,64 .usb_mode = T2_USB_MODE_ULPI,
arch/arm/mach-omap2/twl-common.h+3−0
@@ -1,6 +1,8 @@
1#ifndef __OMAP_PMIC_COMMON__1#ifndef __OMAP_PMIC_COMMON__
2#define __OMAP_PMIC_COMMON__2#define __OMAP_PMIC_COMMON__
3 3
4#include <plat/irqs.h>
5
4#define TWL_COMMON_PDATA_USB (1 << 0)6#define TWL_COMMON_PDATA_USB (1 << 0)
5#define TWL_COMMON_PDATA_BCI (1 << 1)7#define TWL_COMMON_PDATA_BCI (1 << 1)
6#define TWL_COMMON_PDATA_MADC (1 << 2)8#define TWL_COMMON_PDATA_MADC (1 << 2)
@@ -30,6 +32,7 @@ struct twl4030_platform_data; · 23 unmodified lines
30 32
31void omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq,33void omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq,
32 struct twl4030_platform_data *pmic_data);34 struct twl4030_platform_data *pmic_data);
35void omap_pmic_late_init(void);
33 36
34static inline void omap2_pmic_init(const char *pmic_type,37static inline void omap2_pmic_init(const char *pmic_type,
35 struct twl4030_platform_data *pmic_data)38 struct twl4030_platform_data *pmic_data)
arch/arm/mach-pxa/balloon3.c+1−1
@@ -307,7 +307,7 @@ static inline void balloon3_mmc_init(void) {} · 306 unmodified lines
307/******************************************************************************307/******************************************************************************
308 * USB Gadget308 * USB Gadget
309 ******************************************************************************/309 ******************************************************************************/
310#if defined(CONFIG_USB_GADGET_PXA27X)||defined(CONFIG_USB_GADGET_PXA27X_MODULE)310#if defined(CONFIG_USB_PXA27X)||defined(CONFIG_USB_PXA27X_MODULE)
311static void balloon3_udc_command(int cmd)311static void balloon3_udc_command(int cmd)
312{312{
313 if (cmd == PXA2XX_UDC_CMD_CONNECT)313 if (cmd == PXA2XX_UDC_CMD_CONNECT)
arch/arm/mach-pxa/colibri-pxa320.c+1−1
@@ -146,7 +146,7 @@ static void __init colibri_pxa320_init_eth(void) · 145 unmodified lines
146static inline void __init colibri_pxa320_init_eth(void) {}146static inline void __init colibri_pxa320_init_eth(void) {}
147#endif /* CONFIG_AX88796 */147#endif /* CONFIG_AX88796 */
148 148
149#if defined(CONFIG_USB_GADGET_PXA27X)||defined(CONFIG_USB_GADGET_PXA27X_MODULE)149#if defined(CONFIG_USB_PXA27X)||defined(CONFIG_USB_PXA27X_MODULE)
150static struct gpio_vbus_mach_info colibri_pxa320_gpio_vbus_info = {150static struct gpio_vbus_mach_info colibri_pxa320_gpio_vbus_info = {
151 .gpio_vbus = mfp_to_gpio(MFP_PIN_GPIO96),151 .gpio_vbus = mfp_to_gpio(MFP_PIN_GPIO96),
152 .gpio_pullup = -1,152 .gpio_pullup = -1,
arch/arm/mach-pxa/gumstix.c+1−1
@@ -106,7 +106,7 @@ static void __init gumstix_mmc_init(void) · 105 unmodified lines
106}106}
107#endif107#endif
108 108
109#ifdef CONFIG_USB_GADGET_PXA25X109#ifdef CONFIG_USB_PXA25X
110static struct gpio_vbus_mach_info gumstix_udc_info = {110static struct gpio_vbus_mach_info gumstix_udc_info = {
111 .gpio_vbus = GPIO_GUMSTIX_USB_GPIOn,111 .gpio_vbus = GPIO_GUMSTIX_USB_GPIOn,
112 .gpio_pullup = GPIO_GUMSTIX_USB_GPIOx,112 .gpio_pullup = GPIO_GUMSTIX_USB_GPIOx,
arch/arm/mach-pxa/include/mach/palm27x.h+2−2
@@ -37,8 +37,8 @@ extern void __init palm27x_lcd_init(int power, · 36 unmodified lines
37#define palm27x_lcd_init(power, mode) do {} while (0)37#define palm27x_lcd_init(power, mode) do {} while (0)
38#endif38#endif
39 39
40#if defined(CONFIG_USB_GADGET_PXA27X) || \40#if defined(CONFIG_USB_PXA27X) || \
41 defined(CONFIG_USB_GADGET_PXA27X_MODULE)41 defined(CONFIG_USB_PXA27X_MODULE)
42extern void __init palm27x_udc_init(int vbus, int pullup,42extern void __init palm27x_udc_init(int vbus, int pullup,
43 int vbus_inverted);43 int vbus_inverted);
44#else44#else
arch/arm/mach-pxa/palm27x.c+2−2
@@ -164,8 +164,8 @@ void __init palm27x_lcd_init(int power, struct pxafb_mode_info *mode) · 163 unmodified lines
164/******************************************************************************164/******************************************************************************
165 * USB Gadget165 * USB Gadget
166 ******************************************************************************/166 ******************************************************************************/
167#if defined(CONFIG_USB_GADGET_PXA27X) || \167#if defined(CONFIG_USB_PXA27X) || \
168 defined(CONFIG_USB_GADGET_PXA27X_MODULE)168 defined(CONFIG_USB_PXA27X_MODULE)
169static struct gpio_vbus_mach_info palm27x_udc_info = {169static struct gpio_vbus_mach_info palm27x_udc_info = {
170 .gpio_vbus_inverted = 1,170 .gpio_vbus_inverted = 1,
171};171};
arch/arm/mach-pxa/palmtc.c+1−1
@@ -338,7 +338,7 @@ static inline void palmtc_mkp_init(void) {} · 337 unmodified lines
338/******************************************************************************338/******************************************************************************
339 * UDC339 * UDC
340 ******************************************************************************/340 ******************************************************************************/
341#if defined(CONFIG_USB_GADGET_PXA25X)||defined(CONFIG_USB_GADGET_PXA25X_MODULE)341#if defined(CONFIG_USB_PXA25X)||defined(CONFIG_USB_PXA25X_MODULE)
342static struct gpio_vbus_mach_info palmtc_udc_info = {342static struct gpio_vbus_mach_info palmtc_udc_info = {
343 .gpio_vbus = GPIO_NR_PALMTC_USB_DETECT_N,343 .gpio_vbus = GPIO_NR_PALMTC_USB_DETECT_N,
344 .gpio_vbus_inverted = 1,344 .gpio_vbus_inverted = 1,
arch/arm/mach-pxa/vpac270.c+1−1
@@ -343,7 +343,7 @@ static inline void vpac270_uhc_init(void) {} · 342 unmodified lines
343/******************************************************************************343/******************************************************************************
344 * USB Gadget344 * USB Gadget
345 ******************************************************************************/345 ******************************************************************************/
346#if defined(CONFIG_USB_GADGET_PXA27X)||defined(CONFIG_USB_GADGET_PXA27X_MODULE)346#if defined(CONFIG_USB_PXA27X)||defined(CONFIG_USB_PXA27X_MODULE)
347static struct gpio_vbus_mach_info vpac270_gpio_vbus_info = {347static struct gpio_vbus_mach_info vpac270_gpio_vbus_info = {
348 .gpio_vbus = GPIO41_VPAC270_UDC_DETECT,348 .gpio_vbus = GPIO41_VPAC270_UDC_DETECT,
349 .gpio_pullup = -1,349 .gpio_pullup = -1,
arch/arm/mach-s3c64xx/mach-crag6410-module.c+1−1
@@ -8,7 +8,7 @@ · 7 unmodified lines
8 * published by the Free Software Foundation.8 * published by the Free Software Foundation.
9 */9 */
10 10
11#include <linux/module.h>11#include <linux/export.h>
12#include <linux/interrupt.h>12#include <linux/interrupt.h>
13#include <linux/i2c.h>13#include <linux/i2c.h>
14 14
arch/arm/plat-mxc/include/mach/common.h+1−1
@@ -85,7 +85,6 @@ enum mxc_cpu_pwr_mode { · 84 unmodified lines
85};85};
86 86
87extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode);87extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode);
88extern void (*imx_idle)(void);
89extern void imx_print_silicon_rev(const char *cpu, int srev);88extern void imx_print_silicon_rev(const char *cpu, int srev);
90 89
91void avic_handle_irq(struct pt_regs *);90void avic_handle_irq(struct pt_regs *);
@@ -133,4 +132,5 @@ extern void imx53_qsb_common_init(void); · 41 unmodified lines
133extern void imx53_smd_common_init(void);132extern void imx53_smd_common_init(void);
134extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);133extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
135extern void imx6q_pm_init(void);134extern void imx6q_pm_init(void);
135extern void imx6q_clock_map_io(void);
136#endif136#endif
arch/arm/plat-mxc/include/mach/mxc.h+0−14
@@ -50,20 +50,6 @@ · 49 unmodified lines
50#define IMX_CHIP_REVISION_3_3 0x3350#define IMX_CHIP_REVISION_3_3 0x33
51#define IMX_CHIP_REVISION_UNKNOWN 0xff51#define IMX_CHIP_REVISION_UNKNOWN 0xff
52 52
53#define IMX_CHIP_REVISION_1_0_STRING "1.0"
54#define IMX_CHIP_REVISION_1_1_STRING "1.1"
55#define IMX_CHIP_REVISION_1_2_STRING "1.2"
56#define IMX_CHIP_REVISION_1_3_STRING "1.3"
57#define IMX_CHIP_REVISION_2_0_STRING "2.0"
58#define IMX_CHIP_REVISION_2_1_STRING "2.1"
59#define IMX_CHIP_REVISION_2_2_STRING "2.2"
60#define IMX_CHIP_REVISION_2_3_STRING "2.3"
61#define IMX_CHIP_REVISION_3_0_STRING "3.0"
62#define IMX_CHIP_REVISION_3_1_STRING "3.1"
63#define IMX_CHIP_REVISION_3_2_STRING "3.2"
64#define IMX_CHIP_REVISION_3_3_STRING "3.3"
65#define IMX_CHIP_REVISION_UNKNOWN_STRING "unknown"
66
67#ifndef __ASSEMBLY__53#ifndef __ASSEMBLY__
68extern unsigned int __mxc_cpu_type;54extern unsigned int __mxc_cpu_type;
69#endif55#endif
arch/arm/plat-mxc/include/mach/system.h+1−6
@@ -17,14 +17,9 @@ · 16 unmodified lines
17#ifndef __ASM_ARCH_MXC_SYSTEM_H__17#ifndef __ASM_ARCH_MXC_SYSTEM_H__
18#define __ASM_ARCH_MXC_SYSTEM_H__18#define __ASM_ARCH_MXC_SYSTEM_H__
19 19
20extern void (*imx_idle)(void);
21
22static inline void arch_idle(void)20static inline void arch_idle(void)
23{21{
24 if (imx_idle != NULL)22 cpu_do_idle();
25 (imx_idle)();
26 else
27 cpu_do_idle();
28}23}
29 24
30void arch_reset(char mode, const char *cmd);25void arch_reset(char mode, const char *cmd);
arch/arm/plat-mxc/system.c+2−1
@@ -21,6 +21,7 @@ · 20 unmodified lines
21#include <linux/io.h>21#include <linux/io.h>
22#include <linux/err.h>22#include <linux/err.h>
23#include <linux/delay.h>23#include <linux/delay.h>
24#include <linux/module.h>
24 25
25#include <mach/hardware.h>26#include <mach/hardware.h>
26#include <mach/common.h>27#include <mach/common.h>
@@ -28,8 +29,8 @@ · 1 unmodified line
28#include <asm/system.h>29#include <asm/system.h>
29#include <asm/mach-types.h>30#include <asm/mach-types.h>
30 31
31void (*imx_idle)(void) = NULL;
32void __iomem *(*imx_ioremap)(unsigned long, size_t, unsigned int) = NULL;32void __iomem *(*imx_ioremap)(unsigned long, size_t, unsigned int) = NULL;
33EXPORT_SYMBOL_GPL(imx_ioremap);
33 34
34static void __iomem *wdog_base;35static void __iomem *wdog_base;
35 36
arch/arm/plat-omap/include/plat/clock.h+1−1
@@ -165,8 +165,8 @@ struct dpll_data { · 164 unmodified lines
165 u8 auto_recal_bit;165 u8 auto_recal_bit;
166 u8 recal_en_bit;166 u8 recal_en_bit;
167 u8 recal_st_bit;167 u8 recal_st_bit;
168 u8 flags;
169# endif168# endif
169 u8 flags;
170};170};
171 171
172#endif172#endif
arch/arm/plat-omap/include/plat/common.h+3−0
@@ -30,6 +30,7 @@ · 29 unmodified lines
30#include <linux/delay.h>30#include <linux/delay.h>
31 31
32#include <plat/i2c.h>32#include <plat/i2c.h>
33#include <plat/omap_hwmod.h>
33 34
34struct sys_timer;35struct sys_timer;
35 36
@@ -55,6 +56,8 @@ void am35xx_init_early(void); · 19 unmodified lines
55void ti816x_init_early(void);56void ti816x_init_early(void);
56void omap4430_init_early(void);57void omap4430_init_early(void);
57 58
59extern int omap_dss_reset(struct omap_hwmod *);
60
58void omap_sram_init(void);61void omap_sram_init(void);
59 62
60/*63/*
arch/arm/plat-s3c24xx/cpu-freq-debugfs.c+1−1
@@ -12,7 +12,7 @@ · 11 unmodified lines
12*/12*/
13 13
14#include <linux/init.h>14#include <linux/init.h>
15#include <linux/module.h>15#include <linux/export.h>
16#include <linux/interrupt.h>16#include <linux/interrupt.h>
17#include <linux/ioport.h>17#include <linux/ioport.h>
18#include <linux/cpufreq.h>18#include <linux/cpufreq.h>
arch/arm/plat-s5p/sysmmu.c+1−0
@@ -11,6 +11,7 @@ · 10 unmodified lines
11#include <linux/io.h>11#include <linux/io.h>
12#include <linux/interrupt.h>12#include <linux/interrupt.h>
13#include <linux/platform_device.h>13#include <linux/platform_device.h>
14#include <linux/export.h>
14 15
15#include <asm/pgtable.h>16#include <asm/pgtable.h>
16 17
arch/arm/plat-samsung/include/plat/gpio-cfg.h+2−0
@@ -24,6 +24,8 @@ · 23 unmodified lines
24#ifndef __PLAT_GPIO_CFG_H24#ifndef __PLAT_GPIO_CFG_H
25#define __PLAT_GPIO_CFG_H __FILE__25#define __PLAT_GPIO_CFG_H __FILE__
26 26
27#include<linux/types.h>
28
27typedef unsigned int __bitwise__ samsung_gpio_pull_t;29typedef unsigned int __bitwise__ samsung_gpio_pull_t;
28typedef unsigned int __bitwise__ s5p_gpio_drvstr_t;30typedef unsigned int __bitwise__ s5p_gpio_drvstr_t;
29 31
arch/arm/plat-samsung/pd.c+1−1
@@ -11,7 +11,7 @@ · 10 unmodified lines
11*/11*/
12 12
13#include <linux/init.h>13#include <linux/init.h>
14#include <linux/module.h>14#include <linux/export.h>
15#include <linux/platform_device.h>15#include <linux/platform_device.h>
16#include <linux/err.h>16#include <linux/err.h>
17#include <linux/pm_runtime.h>17#include <linux/pm_runtime.h>
arch/arm/plat-samsung/pwm.c+1−1
@@ -11,7 +11,7 @@ · 10 unmodified lines
11 * the Free Software Foundation; either version 2 of the License.11 * the Free Software Foundation; either version 2 of the License.
12*/12*/
13 13
14#include <linux/module.h>14#include <linux/export.h>
15#include <linux/kernel.h>15#include <linux/kernel.h>
16#include <linux/platform_device.h>16#include <linux/platform_device.h>
17#include <linux/slab.h>17#include <linux/slab.h>
arch/arm/tools/mach-types+1−0
@@ -1123,5 +1123,6 @@ blissc MACH_BLISSC BLISSC 3491 · 1122 unmodified lines
1123thales_adc MACH_THALES_ADC THALES_ADC 34921123thales_adc MACH_THALES_ADC THALES_ADC 3492
1124ubisys_p9d_evp MACH_UBISYS_P9D_EVP UBISYS_P9D_EVP 34931124ubisys_p9d_evp MACH_UBISYS_P9D_EVP UBISYS_P9D_EVP 3493
1125atdgp318 MACH_ATDGP318 ATDGP318 34941125atdgp318 MACH_ATDGP318 ATDGP318 3494
1126m28evk MACH_M28EVK M28EVK 3613
1126smdk4212 MACH_SMDK4212 SMDK4212 36381127smdk4212 MACH_SMDK4212 SMDK4212 3638
1127smdk4412 MACH_SMDK4412 SMDK4412 37651128smdk4412 MACH_SMDK4412 SMDK4412 3765
include/video/omapdss.h+0−7
@@ -307,15 +307,8 @@ struct omap_dss_board_info { · 306 unmodified lines
307 void (*dsi_disable_pads)(int dsi_id, unsigned lane_mask);307 void (*dsi_disable_pads)(int dsi_id, unsigned lane_mask);
308};308};
309 309
310#if defined(CONFIG_OMAP2_DSS_MODULE) || defined(CONFIG_OMAP2_DSS)
311/* Init with the board info */310/* Init with the board info */
312extern int omap_display_init(struct omap_dss_board_info *board_data);311extern int omap_display_init(struct omap_dss_board_info *board_data);
313#else
314static inline int omap_display_init(struct omap_dss_board_info *board_data)
315{
316 return 0;
317}
318#endif
319 312
320struct omap_display_platform_data {313struct omap_display_platform_data {
321 struct omap_dss_board_info *board_data;314 struct omap_dss_board_info *board_data;