Merge tag 'mailbox-v5.19' of git://git.linaro.org/landing-teams/working/fujitsu/integration

Pull mailbox updates from Jassi Brar: "api: - hrtimer fix qcom: - log pending irq during resume - minor cosmetic changes omap: - use pm_runtime_resume_and_get imx: - use pm_runtime_resume_and_get - remove redundant initializer mtk: - added GCE header for MT8186 - enable support for MT8186 tegra: - remove redundant NULL check - added hsp_sm_ops for send/recv api - support shared mailboxes stm: - remove unsupported "wakeup" irq pcc: - sanitize mbox allocated memory before use misc: - documentation fixes for arm_mhu and qcom-ipcc" * tag 'mailbox-v5.19' of git://git.linaro.org/landing-teams/working/fujitsu/integration: mailbox: qcom-ipcc: Fix -Wunused-function with CONFIG_PM_SLEEP=n mailbox: forward the hrtimer if not queued and under a lock mailbox: qcom-ipcc: Log the pending interrupt during resume mailbox: pcc: Fix an invalid-load caught by the address sanitizer dt-bindings: mailbox: remove the IPCC "wakeup" IRQ mailbox: correct kerneldoc mailbox: omap: using pm_runtime_resume_and_get to simplify the code mailbox:imx: using pm_runtime_resume_and_get mailbox: mediatek: support mt8186 adsp mailbox dt-bindings: mailbox: mtk,adsp-mbox: add mt8186 compatible name mailbox: tegra-hsp: Add 128-bit shared mailbox support dt-bindings: tegra186-hsp: add type for shared mailboxes mailbox: tegra-hsp: Add tegra_hsp_sm_ops dt-bindings: gce: add the GCE header file for MT8186 mailbox: remove an unneeded NULL check on list iterator mailbox: imx: remove redundant initializer dt-bindings: mailbox: qcom-ipcc: simplify the example

Linus Torvalds committed 4 years ago

Commit cdeffe82 parents 7182e89 79f9fbe16 files · +628 −79Browse files

Unified · Split

16 files

Documentation/devicetree/bindings/mailbox/mtk,adsp-mbox.yaml +4 −3
Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml +9 −0
Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml +10 −19
Documentation/devicetree/bindings/mailbox/st,stm32-ipcc.yaml +3 −8
drivers/mailbox/arm_mhu_db.c +1 −1
drivers/mailbox/arm_mhuv2.c +2 −1
drivers/mailbox/imx-mailbox.c +2 −5
drivers/mailbox/mailbox.c +13 −6
drivers/mailbox/mtk-adsp-mailbox.c +8 −0
drivers/mailbox/omap-mailbox.c +2 −4
drivers/mailbox/pcc.c +1 −1
drivers/mailbox/qcom-ipcc.c +25 −1
drivers/mailbox/tegra-hsp.c +121 −30
include/dt-bindings/gce/mt8186-gce.h +421 −0
include/dt-bindings/mailbox/tegra186-hsp.h +5 −0
include/linux/mailbox_controller.h +1 −0

Documentation/devicetree/bindings/mailbox/mtk,adsp-mbox.yaml+4−3

@@ -11,14 +11,15 @@ maintainers: · 10 unmodified lines
11	11
12	12	description: \|
13	13	The MTK ADSP mailbox Inter-Processor Communication (IPC) enables the SoC
14		− to ommunicate with ADSP by passing messages through two mailbox channels.
	14	+ to communicate with ADSP by passing messages through two mailbox channels.
15	15	The MTK ADSP mailbox IPC also provides the ability for one processor to
16	16	signal the other processor using interrupts.
17	17
18	18	properties:
19	19	compatible:
20		− items:
21		− - const: mediatek,mt8195-adsp-mbox
	20	+ enum:
	21	+ - mediatek,mt8195-adsp-mbox
	22	+ - mediatek,mt8186-adsp-mbox
22	23
23	24	"#mbox-cells":
24	25	const: 0

Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml+9−0

@@ -26,6 +26,15 @@ description: \| · 25 unmodified lines
26	26	second cell is used to identify the mailbox that the client is going
27	27	to use.
28	28
	29	+ For shared mailboxes, the first cell composed of two fields:
	30	+ - bits 15..8:
	31	+ A bit mask of flags that further specifies the type of shared
	32	+ mailbox to be used (based on the data size). If no flag is
	33	+ specified then, 32-bit shared mailbox is used.
	34	+ - bits 7..0:
	35	+ Defines the type of the mailbox to be used. This field should be
	36	+ TEGRA_HSP_MBOX_TYPE_SM for shared mailboxes.
	37	+
29	38	For doorbells, the second cell specifies the index of the doorbell to
30	39	use.
31	40

Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml+10−19

@@ -62,23 +62,14 @@ additionalProperties: false · 61 unmodified lines
62	62
63	63	examples:
64	64	- \|
65		− #include <dt-bindings/interrupt-controller/arm-gic.h>
66		− #include <dt-bindings/mailbox/qcom-ipcc.h>
	65	+ #include <dt-bindings/interrupt-controller/arm-gic.h>
	66	+ #include <dt-bindings/mailbox/qcom-ipcc.h>
67	67
68		− mailbox@408000 {
69		− compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
70		− reg = <0x408000 0x1000>;
71		− interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
72		− interrupt-controller;
73		− #interrupt-cells = <3>;
74		− #mbox-cells = <2>;
75		− };
76		−
77		− smp2p-modem {
78		− compatible = "qcom,smp2p";
79		− interrupts-extended = <&ipcc_mproc IPCC_CLIENT_MPSS
80		− IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_EDGE_RISING>;
81		− mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>;
82		−
83		− /* Other SMP2P fields */
84		− };
	68	+ mailbox@408000 {
	69	+ compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
	70	+ reg = <0x408000 0x1000>;
	71	+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
	72	+ interrupt-controller;
	73	+ #interrupt-cells = <3>;
	74	+ #mbox-cells = <2>;
	75	+ };

Documentation/devicetree/bindings/mailbox/st,stm32-ipcc.yaml+3−8

@@ -30,15 +30,11 @@ properties: · 29 unmodified lines
30	30	items:
31	31	- description: rx channel occupied
32	32	- description: tx channel free
33		− - description: wakeup source
34		− minItems: 2
35	33
36	34	interrupt-names:
37	35	items:
38	36	- const: rx
39	37	- const: tx
40		− - const: wakeup
41		− minItems: 2
42	38
43	39	wakeup-source: true
44	40
@@ -70,10 +66,9 @@ examples: · 25 unmodified lines
70	66	#mbox-cells = <1>;
71	67	reg = <0x4c001000 0x400>;
72	68	st,proc-id = <0>;
73		− interrupts-extended = <&intc GIC_SPI 100 IRQ_TYPE_NONE>,
74		− <&intc GIC_SPI 101 IRQ_TYPE_NONE>,
75		− <&aiec 62 1>;
76		− interrupt-names = "rx", "tx", "wakeup";
	69	+ interrupts-extended = <&exti 61 1>,
	70	+ <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
	71	+ interrupt-names = "rx", "tx";
77	72	clocks = <&rcc_clk IPCC>;
78	73	wakeup-source;
79	74	};

drivers/mailbox/arm_mhu_db.c+1−1

@@ -44,7 +44,7 @@ struct arm_mhu { · 43 unmodified lines
44	44	};
45	45
46	46	/**
47		− * ARM MHU Mailbox allocated channel information
	47	+ * struct mhu_db_channel - ARM MHU Mailbox allocated channel information
48	48	*
49	49	* @mhu: Pointer to parent mailbox device
50	50	* @pchan: Physical channel within which this doorbell resides in

drivers/mailbox/arm_mhuv2.c+2−1

@@ -160,7 +160,8 @@ enum mhuv2_frame { · 159 unmodified lines
160	160	* struct mhuv2 - MHUv2 mailbox controller data
161	161	*
162	162	* @mbox: Mailbox controller belonging to the MHU frame.
163		− * @send/recv: Base address of the register mapping region.
	163	+ * @send: Base address of the register mapping region.
	164	+ * @recv: Base address of the register mapping region.
164	165	* @frame: Frame type: RECEIVER_FRAME or SENDER_FRAME.
165	166	* @irq: Interrupt.
166	167	* @windows: Channel windows implemented by the platform.

drivers/mailbox/imx-mailbox.c+2−5

@@ -830,11 +830,9 @@ static int imx_mu_probe(struct platform_device *pdev) · 829 unmodified lines
830	830
831	831	pm_runtime_enable(dev);
832	832
833		− ret = pm_runtime_get_sync(dev);
834		− if (ret < 0) {
835		− pm_runtime_put_noidle(dev);
	833	+ ret = pm_runtime_resume_and_get(dev);
	834	+ if (ret < 0)
836	835	goto disable_runtime_pm;
837		− }
838	836
839	837	ret = pm_runtime_put_sync(dev);
840	838	if (ret < 0)
@@ -886,7 +884,6 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp = { · 45 unmodified lines
886	884	.rx = imx_mu_generic_rx,
887	885	.rxdb = imx_mu_generic_rxdb,
888	886	.init = imx_mu_init_generic,
889		− .rxdb = imx_mu_generic_rxdb,
890	887	.type = IMX_MU_V2,
891	888	.xTR = 0x200,
892	889	.xRR = 0x280,

drivers/mailbox/mailbox.c+13−6

@@ -82,11 +82,11 @@ static void msg_submit(struct mbox_chan *chan) · 81 unmodified lines
82	82	exit:
83	83	spin_unlock_irqrestore(&chan->lock, flags);
84	84
85		− /* kick start the timer immediately to avoid delays */
86	85	if (!err && (chan->txdone_method & TXDONE_BY_POLL)) {
87		− /* but only if not already active */
88		− if (!hrtimer_active(&chan->mbox->poll_hrt))
89		− hrtimer_start(&chan->mbox->poll_hrt, 0, HRTIMER_MODE_REL);
	86	+ /* kick start the timer immediately to avoid delays */
	87	+ spin_lock_irqsave(&chan->mbox->poll_hrt_lock, flags);
	88	+ hrtimer_start(&chan->mbox->poll_hrt, 0, HRTIMER_MODE_REL);
	89	+ spin_unlock_irqrestore(&chan->mbox->poll_hrt_lock, flags);
90	90	}
91	91	}
92	92
@@ -120,20 +120,26 @@ static enum hrtimer_restart txdone_hrtimer(struct hrtimer *hrtimer) · 27 unmodified lines
120	120	container_of(hrtimer, struct mbox_controller, poll_hrt);
121	121	bool txdone, resched = false;
122	122	int i;
	123	+ unsigned long flags;
123	124
124	125	for (i = 0; i < mbox->num_chans; i++) {
125	126	struct mbox_chan *chan = &mbox->chans[i];
126	127
127	128	if (chan->active_req && chan->cl) {
128		− resched = true;
129	129	txdone = chan->mbox->ops->last_tx_done(chan);
130	130	if (txdone)
131	131	tx_tick(chan, 0);
	132	+ else
	133	+ resched = true;
132	134	}
133	135	}
134	136
135	137	if (resched) {
136		− hrtimer_forward_now(hrtimer, ms_to_ktime(mbox->txpoll_period));
	138	+ spin_lock_irqsave(&mbox->poll_hrt_lock, flags);
	139	+ if (!hrtimer_is_queued(hrtimer))
	140	+ hrtimer_forward_now(hrtimer, ms_to_ktime(mbox->txpoll_period));
	141	+ spin_unlock_irqrestore(&mbox->poll_hrt_lock, flags);
	142	+
137	143	return HRTIMER_RESTART;
138	144	}
139	145	return HRTIMER_NORESTART;
@@ -500,6 +506,7 @@ int mbox_controller_register(struct mbox_controller *mbox) · 360 unmodified lines
500	506	hrtimer_init(&mbox->poll_hrt, CLOCK_MONOTONIC,
501	507	HRTIMER_MODE_REL);
502	508	mbox->poll_hrt.function = txdone_hrtimer;
	509	+ spin_lock_init(&mbox->poll_hrt_lock);
503	510	}
504	511
505	512	for (i = 0; i < mbox->num_chans; i++) {

drivers/mailbox/mtk-adsp-mailbox.c+8−0

@@ -149,6 +149,13 @@ static int mtk_adsp_mbox_probe(struct platform_device *pdev) · 148 unmodified lines
149	149	return devm_mbox_controller_register(dev, &priv->mbox);
150	150	}
151	151
	152	+static const struct mtk_adsp_mbox_cfg mt8186_adsp_mbox_cfg = {
	153	+ .set_in = 0x00,
	154	+ .set_out = 0x04,
	155	+ .clr_in = 0x08,
	156	+ .clr_out = 0x0C,
	157	+};
	158	+
152	159	static const struct mtk_adsp_mbox_cfg mt8195_adsp_mbox_cfg = {
153	160	.set_in = 0x00,
154	161	.set_out = 0x1c,
@@ -157,6 +164,7 @@ static const struct mtk_adsp_mbox_cfg mt8195_adsp_mbox_cfg = { · 2 unmodified lines
157	164	};
158	165
159	166	static const struct of_device_id mtk_adsp_mbox_of_match[] = {
	167	+ { .compatible = "mediatek,mt8186-adsp-mbox", .data = &mt8186_adsp_mbox_cfg },
160	168	{ .compatible = "mediatek,mt8195-adsp-mbox", .data = &mt8195_adsp_mbox_cfg },
161	169	{},
162	170	};

drivers/mailbox/omap-mailbox.c+2−4

@@ -856,11 +856,9 @@ static int omap_mbox_probe(struct platform_device *pdev) · 855 unmodified lines
856	856	platform_set_drvdata(pdev, mdev);
857	857	pm_runtime_enable(mdev->dev);
858	858
859		− ret = pm_runtime_get_sync(mdev->dev);
860		− if (ret < 0) {
861		− pm_runtime_put_noidle(mdev->dev);
	859	+ ret = pm_runtime_resume_and_get(mdev->dev);
	860	+ if (ret < 0)
862	861	goto unregister;
863		− }
864	862
865	863	/*
866	864	* just print the raw revision register, the format is not

drivers/mailbox/pcc.c+1−1

@@ -654,7 +654,7 @@ static int pcc_mbox_probe(struct platform_device *pdev) · 653 unmodified lines
654	654	goto err;
655	655	}
656	656
657		− pcc_mbox_ctrl = devm_kmalloc(dev, sizeof(*pcc_mbox_ctrl), GFP_KERNEL);
	657	+ pcc_mbox_ctrl = devm_kzalloc(dev, sizeof(*pcc_mbox_ctrl), GFP_KERNEL);
658	658	if (!pcc_mbox_ctrl) {
659	659	rc = -ENOMEM;
660	660	goto err;

drivers/mailbox/qcom-ipcc.c+25−1

@@ -41,9 +41,10 @@ struct qcom_ipcc_chan_info { · 40 unmodified lines
41	41	* @dev: Device associated with this instance
42	42	* @base: Base address of the IPCC frame associated to APSS
43	43	* @irq_domain: The irq_domain associated with this instance
44		− * @chan: The mailbox channels array
	44	+ * @chans: The mailbox channels array
45	45	* @mchan: The per-mailbox channel info array
46	46	* @mbox: The mailbox controller
	47	+ * @num_chans: Number of @chans elements
47	48	* @irq: Summary irq
48	49	*/
49	50	struct qcom_ipcc {
@@ -254,6 +255,24 @@ static int qcom_ipcc_setup_mbox(struct qcom_ipcc *ipcc, · 204 unmodified lines
254	255	return devm_mbox_controller_register(dev, mbox);
255	256	}
256	257
	258	+static int qcom_ipcc_pm_resume(struct device *dev)
	259	+{
	260	+ struct qcom_ipcc *ipcc = dev_get_drvdata(dev);
	261	+ u32 hwirq;
	262	+ int virq;
	263	+
	264	+ hwirq = readl(ipcc->base + IPCC_REG_RECV_ID);
	265	+ if (hwirq == IPCC_NO_PENDING_IRQ)
	266	+ return 0;
	267	+
	268	+ virq = irq_find_mapping(ipcc->irq_domain, hwirq);
	269	+
	270	+ dev_dbg(dev, "virq: %d triggered client-id: %ld; signal-id: %ld\n", virq,
	271	+ FIELD_GET(IPCC_CLIENT_ID_MASK, hwirq), FIELD_GET(IPCC_SIGNAL_ID_MASK, hwirq));
	272	+
	273	+ return 0;
	274	+}
	275	+
257	276	static int qcom_ipcc_probe(struct platform_device *pdev)
258	277	{
259	278	struct qcom_ipcc *ipcc;
@@ -324,6 +343,10 @@ static const struct of_device_id qcom_ipcc_of_match[] = { · 64 unmodified lines
324	343	};
325	344	MODULE_DEVICE_TABLE(of, qcom_ipcc_of_match);
326	345
	346	+static const struct dev_pm_ops qcom_ipcc_dev_pm_ops = {
	347	+ NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, qcom_ipcc_pm_resume)
	348	+};
	349	+
327	350	static struct platform_driver qcom_ipcc_driver = {
328	351	.probe = qcom_ipcc_probe,
329	352	.remove = qcom_ipcc_remove,
@@ -331,6 +354,7 @@ static struct platform_driver qcom_ipcc_driver = { · 1 unmodified line
331	354	.name = "qcom-ipcc",
332	355	.of_match_table = qcom_ipcc_of_match,
333	356	.suppress_bind_attrs = true,
	357	+ .pm = pm_sleep_ptr(&qcom_ipcc_dev_pm_ops),
334	358	},
335	359	};
336	360

drivers/mailbox/tegra-hsp.c+121−30

@@ -46,10 +46,18 @@ · 45 unmodified lines
46	46	#define HSP_SM_SHRD_MBOX_FULL_INT_IE 0x04
47	47	#define HSP_SM_SHRD_MBOX_EMPTY_INT_IE 0x08
48	48
	49	+#define HSP_SHRD_MBOX_TYPE1_TAG 0x40
	50	+#define HSP_SHRD_MBOX_TYPE1_DATA0 0x48
	51	+#define HSP_SHRD_MBOX_TYPE1_DATA1 0x4c
	52	+#define HSP_SHRD_MBOX_TYPE1_DATA2 0x50
	53	+#define HSP_SHRD_MBOX_TYPE1_DATA3 0x54
	54	+
49	55	#define HSP_DB_CCPLEX 1
50	56	#define HSP_DB_BPMP 3
51	57	#define HSP_DB_MAX 7
52	58
	59	+#define HSP_MBOX_TYPE_MASK 0xff
	60	+
53	61	struct tegra_hsp_channel;
54	62	struct tegra_hsp;
55	63
@@ -67,8 +75,14 @@ struct tegra_hsp_doorbell { · 11 unmodified lines
67	75	unsigned int index;
68	76	};
69	77
	78	+struct tegra_hsp_sm_ops {
	79	+ void (send)(struct tegra_hsp_channel channel, void *data);
	80	+ void (recv)(struct tegra_hsp_channel channel);
	81	+};
	82	+
70	83	struct tegra_hsp_mailbox {
71	84	struct tegra_hsp_channel channel;
	85	+ const struct tegra_hsp_sm_ops *ops;
72	86	unsigned int index;
73	87	bool producer;
74	88	};
@@ -82,6 +96,7 @@ struct tegra_hsp_db_map { · 7 unmodified lines
82	96	struct tegra_hsp_soc {
83	97	const struct tegra_hsp_db_map *map;
84	98	bool has_per_mb_ie;
	99	+ bool has_128_bit_mb;
85	100	};
86	101
87	102	struct tegra_hsp {
@@ -208,8 +223,7 @@ static irqreturn_t tegra_hsp_shared_irq(int irq, void *data) · 120 unmodified lines
208	223	{
209	224	struct tegra_hsp *hsp = data;
210	225	unsigned long bit, mask;
211		− u32 status, value;
212		− void *msg;
	226	+ u32 status;
213	227
214	228	status = tegra_hsp_readl(hsp, HSP_INT_IR) & hsp->mask;
215	229
@@ -245,25 +259,8 @@ static irqreturn_t tegra_hsp_shared_irq(int irq, void *data) · 29 unmodified lines
245	259	for_each_set_bit(bit, &mask, hsp->num_sm) {
246	260	struct tegra_hsp_mailbox *mb = &hsp->mailboxes[bit];
247	261
248		− if (!mb->producer) {
249		− value = tegra_hsp_channel_readl(&mb->channel,
250		− HSP_SM_SHRD_MBOX);
251		− value &= ~HSP_SM_SHRD_MBOX_FULL;
252		− msg = (void *)(unsigned long)value;
253		− mbox_chan_received_data(mb->channel.chan, msg);
254		−
255		− /*
256		− * Need to clear all bits here since some producers,
257		− * such as TCU, depend on fields in the register
258		− * getting cleared by the consumer.
259		− *
260		− * The mailbox API doesn't give the consumers a way
261		− * of doing that explicitly, so we have to make sure
262		− * we cover all possible cases.
263		− */
264		− tegra_hsp_channel_writel(&mb->channel, 0x0,
265		− HSP_SM_SHRD_MBOX);
266		− }
	262	+ if (!mb->producer)
	263	+ mb->ops->recv(&mb->channel);
267	264	}
268	265
269	266	return IRQ_HANDLED;
@@ -372,21 +369,97 @@ static const struct mbox_chan_ops tegra_hsp_db_ops = { · 102 unmodified lines
372	369	.shutdown = tegra_hsp_doorbell_shutdown,
373	370	};
374	371
	372	+static void tegra_hsp_sm_send32(struct tegra_hsp_channel channel, void data)
	373	+{
	374	+ u32 value;
	375	+
	376	+ /* copy data and mark mailbox full */
	377	+ value = (u32)(unsigned long)data;
	378	+ value \|= HSP_SM_SHRD_MBOX_FULL;
	379	+
	380	+ tegra_hsp_channel_writel(channel, value, HSP_SM_SHRD_MBOX);
	381	+}
	382	+
	383	+static void tegra_hsp_sm_recv32(struct tegra_hsp_channel *channel)
	384	+{
	385	+ u32 value;
	386	+ void *msg;
	387	+
	388	+ value = tegra_hsp_channel_readl(channel, HSP_SM_SHRD_MBOX);
	389	+ value &= ~HSP_SM_SHRD_MBOX_FULL;
	390	+ msg = (void *)(unsigned long)value;
	391	+ mbox_chan_received_data(channel->chan, msg);
	392	+
	393	+ /*
	394	+ * Need to clear all bits here since some producers, such as TCU, depend
	395	+ * on fields in the register getting cleared by the consumer.
	396	+ *
	397	+ * The mailbox API doesn't give the consumers a way of doing that
	398	+ * explicitly, so we have to make sure we cover all possible cases.
	399	+ */
	400	+ tegra_hsp_channel_writel(channel, 0x0, HSP_SM_SHRD_MBOX);
	401	+}
	402	+
	403	+static const struct tegra_hsp_sm_ops tegra_hsp_sm_32bit_ops = {
	404	+ .send = tegra_hsp_sm_send32,
	405	+ .recv = tegra_hsp_sm_recv32,
	406	+};
	407	+
	408	+static void tegra_hsp_sm_send128(struct tegra_hsp_channel channel, void data)
	409	+{
	410	+ u32 value[4];
	411	+
	412	+ memcpy(value, data, sizeof(value));
	413	+
	414	+ /* Copy data */
	415	+ tegra_hsp_channel_writel(channel, value[0], HSP_SHRD_MBOX_TYPE1_DATA0);
	416	+ tegra_hsp_channel_writel(channel, value[1], HSP_SHRD_MBOX_TYPE1_DATA1);
	417	+ tegra_hsp_channel_writel(channel, value[2], HSP_SHRD_MBOX_TYPE1_DATA2);
	418	+ tegra_hsp_channel_writel(channel, value[3], HSP_SHRD_MBOX_TYPE1_DATA3);
	419	+
	420	+ /* Update tag to mark mailbox full */
	421	+ tegra_hsp_channel_writel(channel, HSP_SM_SHRD_MBOX_FULL,
	422	+ HSP_SHRD_MBOX_TYPE1_TAG);
	423	+}
	424	+
	425	+static void tegra_hsp_sm_recv128(struct tegra_hsp_channel *channel)
	426	+{
	427	+ u32 value[4];
	428	+ void *msg;
	429	+
	430	+ value[0] = tegra_hsp_channel_readl(channel, HSP_SHRD_MBOX_TYPE1_DATA0);
	431	+ value[1] = tegra_hsp_channel_readl(channel, HSP_SHRD_MBOX_TYPE1_DATA1);
	432	+ value[2] = tegra_hsp_channel_readl(channel, HSP_SHRD_MBOX_TYPE1_DATA2);
	433	+ value[3] = tegra_hsp_channel_readl(channel, HSP_SHRD_MBOX_TYPE1_DATA3);
	434	+
	435	+ msg = (void *)(unsigned long)value;
	436	+ mbox_chan_received_data(channel->chan, msg);
	437	+
	438	+ /*
	439	+ * Clear data registers and tag.
	440	+ */
	441	+ tegra_hsp_channel_writel(channel, 0x0, HSP_SHRD_MBOX_TYPE1_DATA0);
	442	+ tegra_hsp_channel_writel(channel, 0x0, HSP_SHRD_MBOX_TYPE1_DATA1);
	443	+ tegra_hsp_channel_writel(channel, 0x0, HSP_SHRD_MBOX_TYPE1_DATA2);
	444	+ tegra_hsp_channel_writel(channel, 0x0, HSP_SHRD_MBOX_TYPE1_DATA3);
	445	+ tegra_hsp_channel_writel(channel, 0x0, HSP_SHRD_MBOX_TYPE1_TAG);
	446	+}
	447	+
	448	+static const struct tegra_hsp_sm_ops tegra_hsp_sm_128bit_ops = {
	449	+ .send = tegra_hsp_sm_send128,
	450	+ .recv = tegra_hsp_sm_recv128,
	451	+};
	452	+
375	453	static int tegra_hsp_mailbox_send_data(struct mbox_chan chan, void data)
376	454	{
377	455	struct tegra_hsp_mailbox *mb = chan->con_priv;
378	456	struct tegra_hsp *hsp = mb->channel.hsp;
379	457	unsigned long flags;
380		− u32 value;
381	458
382	459	if (WARN_ON(!mb->producer))
383	460	return -EPERM;
384	461
385		− /* copy data and mark mailbox full */
386		− value = (u32)(unsigned long)data;
387		− value \|= HSP_SM_SHRD_MBOX_FULL;
388		−
389		− tegra_hsp_channel_writel(&mb->channel, value, HSP_SM_SHRD_MBOX);
	462	+ mb->ops->send(&mb->channel, data);
390	463
391	464	/* enable EMPTY interrupt for the shared mailbox */
392	465	spin_lock_irqsave(&hsp->lock, flags);
@@ -552,12 +625,21 @@ static struct mbox_chan tegra_hsp_sm_xlate(struct mbox_controller mbox, · 159 unmodified lines
552	625
553	626	index = args->args[1] & TEGRA_HSP_SM_MASK;
554	627
555		− if (type != TEGRA_HSP_MBOX_TYPE_SM \|\| !hsp->shared_irqs \|\|
556		− index >= hsp->num_sm)
	628	+ if ((type & HSP_MBOX_TYPE_MASK) != TEGRA_HSP_MBOX_TYPE_SM \|\|
	629	+ !hsp->shared_irqs \|\| index >= hsp->num_sm)
557	630	return ERR_PTR(-ENODEV);
558	631
559	632	mb = &hsp->mailboxes[index];
560	633
	634	+ if (type & TEGRA_HSP_MBOX_TYPE_SM_128BIT) {
	635	+ if (!hsp->soc->has_128_bit_mb)
	636	+ return ERR_PTR(-ENODEV);
	637	+
	638	+ mb->ops = &tegra_hsp_sm_128bit_ops;
	639	+ } else {
	640	+ mb->ops = &tegra_hsp_sm_32bit_ops;
	641	+ }
	642	+
561	643	if ((args->args[1] & TEGRA_HSP_SM_FLAG_TX) == 0)
562	644	mb->producer = false;
563	645	else
@@ -804,7 +886,7 @@ static int __maybe_unused tegra_hsp_resume(struct device *dev) · 240 unmodified lines
804	886	struct tegra_hsp_doorbell *db;
805	887
806	888	list_for_each_entry(db, &hsp->doorbells, list) {
807		− if (db && db->channel.chan)
	889	+ if (db->channel.chan)
808	890	tegra_hsp_doorbell_startup(db->channel.chan);
809	891	}
810	892
@@ -833,16 +915,25 @@ static const struct tegra_hsp_db_map tegra186_hsp_db_map[] = { · 22 unmodified lines
833	915	static const struct tegra_hsp_soc tegra186_hsp_soc = {
834	916	.map = tegra186_hsp_db_map,
835	917	.has_per_mb_ie = false,
	918	+ .has_128_bit_mb = false,
836	919	};
837	920
838	921	static const struct tegra_hsp_soc tegra194_hsp_soc = {
839	922	.map = tegra186_hsp_db_map,
840	923	.has_per_mb_ie = true,
	924	+ .has_128_bit_mb = false,
	925	+};
	926	+
	927	+static const struct tegra_hsp_soc tegra234_hsp_soc = {
	928	+ .map = tegra186_hsp_db_map,
	929	+ .has_per_mb_ie = false,
	930	+ .has_128_bit_mb = true,
841	931	};
842	932
843	933	static const struct of_device_id tegra_hsp_match[] = {
844	934	{ .compatible = "nvidia,tegra186-hsp", .data = &tegra186_hsp_soc },
845	935	{ .compatible = "nvidia,tegra194-hsp", .data = &tegra194_hsp_soc },
	936	+ { .compatible = "nvidia,tegra234-hsp", .data = &tegra234_hsp_soc },
846	937	{ }
847	938	};
848	939

include/dt-bindings/gce/mt8186-gce.h+421−0

@@ -0,0 +1,421 @@
	1	+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
	2	+/*
	3	+ * Copyright (C) 2022 MediaTek Inc.
	4	+ * Author: Yongqiang Niu <yongqiang.niu@mediatek.com>
	5	+ */
	6	+
	7	+#ifndef _DT_BINDINGS_GCE_MT8186_H
	8	+#define _DT_BINDINGS_GCE_MT8186_H
	9	+
	10	+/* assign timeout 0 also means default */
	11	+#define CMDQ_NO_TIMEOUT 0xffffffff
	12	+#define CMDQ_TIMEOUT_DEFAULT 1000
	13	+
	14	+/* GCE thread priority */
	15	+#define CMDQ_THR_PRIO_LOWEST 0
	16	+#define CMDQ_THR_PRIO_1 1
	17	+#define CMDQ_THR_PRIO_2 2
	18	+#define CMDQ_THR_PRIO_3 3
	19	+#define CMDQ_THR_PRIO_4 4
	20	+#define CMDQ_THR_PRIO_5 5
	21	+#define CMDQ_THR_PRIO_6 6
	22	+#define CMDQ_THR_PRIO_HIGHEST 7
	23	+
	24	+/* CPR count in 32bit register */
	25	+#define GCE_CPR_COUNT 1312
	26	+
	27	+/* GCE subsys table */
	28	+#define SUBSYS_1300XXXX 0
	29	+#define SUBSYS_1400XXXX 1
	30	+#define SUBSYS_1401XXXX 2
	31	+#define SUBSYS_1402XXXX 3
	32	+#define SUBSYS_1502XXXX 4
	33	+#define SUBSYS_1582XXXX 5
	34	+#define SUBSYS_1B00XXXX 6
	35	+#define SUBSYS_1C00XXXX 7
	36	+#define SUBSYS_1C10XXXX 8
	37	+#define SUBSYS_1000XXXX 9
	38	+#define SUBSYS_1001XXXX 10
	39	+#define SUBSYS_1020XXXX 11
	40	+#define SUBSYS_1021XXXX 12
	41	+#define SUBSYS_1022XXXX 13
	42	+#define SUBSYS_1023XXXX 14
	43	+#define SUBSYS_1060XXXX 15
	44	+#define SUBSYS_1602XXXX 16
	45	+#define SUBSYS_1608XXXX 17
	46	+#define SUBSYS_1700XXXX 18
	47	+#define SUBSYS_1701XXXX 19
	48	+#define SUBSYS_1702XXXX 20
	49	+#define SUBSYS_1703XXXX 21
	50	+#define SUBSYS_1706XXXX 22
	51	+#define SUBSYS_1A00XXXX 23
	52	+#define SUBSYS_1A01XXXX 24
	53	+#define SUBSYS_1A02XXXX 25
	54	+#define SUBSYS_1A03XXXX 26
	55	+#define SUBSYS_1A04XXXX 27
	56	+#define SUBSYS_1A05XXXX 28
	57	+#define SUBSYS_1A06XXXX 29
	58	+#define SUBSYS_NO_SUPPORT 99
	59	+
	60	+/* GCE General Purpose Register (GPR) support
	61	+ * Leave note for scenario usage here
	62	+ */
	63	+/* GCE: write mask */
	64	+#define GCE_GPR_R00 0x00
	65	+#define GCE_GPR_R01 0x01
	66	+/* MDP: P1: JPEG dest */
	67	+#define GCE_GPR_R02 0x02
	68	+#define GCE_GPR_R03 0x03
	69	+/* MDP: PQ color */
	70	+#define GCE_GPR_R04 0x04
	71	+/* MDP: 2D sharpness */
	72	+#define GCE_GPR_R05 0x05
	73	+/* DISP: poll esd */
	74	+#define GCE_GPR_R06 0x06
	75	+#define GCE_GPR_R07 0x07
	76	+/* MDP: P4: 2D sharpness dst */
	77	+#define GCE_GPR_R08 0x08
	78	+#define GCE_GPR_R09 0x09
	79	+/* VCU: poll with timeout for GPR timer */
	80	+#define GCE_GPR_R10 0x0A
	81	+#define GCE_GPR_R11 0x0B
	82	+/* CMDQ: debug */
	83	+#define GCE_GPR_R12 0x0C
	84	+#define GCE_GPR_R13 0x0D
	85	+/* CMDQ: P7: debug */
	86	+#define GCE_GPR_R14 0x0E
	87	+#define GCE_GPR_R15 0x0F
	88	+
	89	+/* GCE hardware events */
	90	+/* VDEC */
	91	+#define CMDQ_EVENT_LINE_COUNT_THRESHOLD_INTERRUPT 0
	92	+#define CMDQ_EVENT_VDEC_INT 1
	93	+#define CMDQ_EVENT_VDEC_PAUSE 2
	94	+#define CMDQ_EVENT_VDEC_DEC_ERROR 3
	95	+#define CMDQ_EVENT_MDEC_TIMEOUT 4
	96	+#define CMDQ_EVENT_DRAM_ACCESS_DONE 5
	97	+#define CMDQ_EVENT_INI_FETCH_RDY 6
	98	+#define CMDQ_EVENT_PROCESS_FLAG 7
	99	+#define CMDQ_EVENT_SEARCH_START_CODE_DONE 8
	100	+#define CMDQ_EVENT_REF_REORDER_DONE 9
	101	+#define CMDQ_EVENT_WP_TBLE_DONE 10
	102	+#define CMDQ_EVENT_COUNT_SRAM_CLR_DONE 11
	103	+#define CMDQ_EVENT_GCE_CNT_OP_THRESHOLD 15
	104	+#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_0 16
	105	+#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_1 17
	106	+#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_2 18
	107	+#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_3 19
	108	+#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_4 20
	109	+#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_5 21
	110	+#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_6 22
	111	+#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_7 23
	112	+#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_8 24
	113	+#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_9 25
	114	+#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_10 26
	115	+#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_11 27
	116	+#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_12 28
	117	+#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_13 29
	118	+#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_14 30
	119	+#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_15 31
	120	+#define CMDQ_EVENT_WPE_GCE_FRAME_DONE 32
	121	+
	122	+/* CAM */
	123	+#define CMDQ_EVENT_ISP_FRAME_DONE_A 65
	124	+#define CMDQ_EVENT_ISP_FRAME_DONE_B 66
	125	+#define CMDQ_EVENT_CAMSV1_PASS1_DONE 70
	126	+#define CMDQ_EVENT_CAMSV2_PASS1_DONE 71
	127	+#define CMDQ_EVENT_CAMSV3_PASS1_DONE 72
	128	+#define CMDQ_EVENT_MRAW_0_PASS1_DONE 73
	129	+#define CMDQ_EVENT_SENINF_CAM0_FIFO_FULL 75
	130	+#define CMDQ_EVENT_SENINF_CAM1_FIFO_FULL 76
	131	+#define CMDQ_EVENT_SENINF_CAM2_FIFO_FULL 77
	132	+#define CMDQ_EVENT_SENINF_CAM3_FIFO_FULL 78
	133	+#define CMDQ_EVENT_SENINF_CAM4_FIFO_FULL 79
	134	+#define CMDQ_EVENT_SENINF_CAM5_FIFO_FULL 80
	135	+#define CMDQ_EVENT_SENINF_CAM6_FIFO_FULL 81
	136	+#define CMDQ_EVENT_SENINF_CAM7_FIFO_FULL 82
	137	+#define CMDQ_EVENT_SENINF_CAM8_FIFO_FULL 83
	138	+#define CMDQ_EVENT_SENINF_CAM9_FIFO_FULL 84
	139	+#define CMDQ_EVENT_SENINF_CAM10_FIFO_FULL 85
	140	+#define CMDQ_EVENT_SENINF_CAM11_FIFO_FULL 86
	141	+#define CMDQ_EVENT_SENINF_CAM12_FIFO_FULL 87
	142	+#define CMDQ_EVENT_TG_OVRUN_A_INT 88
	143	+#define CMDQ_EVENT_DMA_R1_ERROR_A_INT 89
	144	+#define CMDQ_EVENT_TG_OVRUN_B_INT 90
	145	+#define CMDQ_EVENT_DMA_R1_ERROR_B_INT 91
	146	+#define CMDQ_EVENT_TG_OVRUN_M0_INT 94
	147	+#define CMDQ_EVENT_R1_ERROR_M0_INT 95
	148	+#define CMDQ_EVENT_TG_GRABERR_M0_INT 96
	149	+#define CMDQ_EVENT_TG_GRABERR_A_INT 98
	150	+#define CMDQ_EVENT_CQ_VR_SNAP_A_INT 99
	151	+#define CMDQ_EVENT_TG_GRABERR_B_INT 100
	152	+#define CMDQ_EVENT_CQ_VR_SNAP_B_INT 101
	153	+/* VENC */
	154	+#define CMDQ_EVENT_VENC_CMDQ_FRAME_DONE 129
	155	+#define CMDQ_EVENT_VENC_CMDQ_PAUSE_DONE 130
	156	+#define CMDQ_EVENT_JPGENC_CMDQ_DONE 131
	157	+#define CMDQ_EVENT_VENC_CMDQ_MB_DONE 132
	158	+#define CMDQ_EVENT_VENC_CMDQ_128BYTE_CNT_DONE 133
	159	+#define CMDQ_EVENT_VENC_CMDQ_PPS_DONE 136
	160	+#define CMDQ_EVENT_VENC_CMDQ_SPS_DONE 137
	161	+#define CMDQ_EVENT_VENC_CMDQ_VPS_DONE 138
	162	+/* IPE */
	163	+#define CMDQ_EVENT_FDVT_DONE 161
	164	+#define CMDQ_EVENT_FE_DONE 162
	165	+#define CMDQ_EVENT_RSC_DONE 163
	166	+#define CMDQ_EVENT_DVS_DONE_ASYNC_SHOT 164
	167	+#define CMDQ_EVENT_DVP_DONE_ASYNC_SHOT 165
	168	+/* IMG2 */
	169	+#define CMDQ_EVENT_GCE_IMG2_EVENT0 193
	170	+#define CMDQ_EVENT_GCE_IMG2_EVENT1 194
	171	+#define CMDQ_EVENT_GCE_IMG2_EVENT2 195
	172	+#define CMDQ_EVENT_GCE_IMG2_EVENT3 196
	173	+#define CMDQ_EVENT_GCE_IMG2_EVENT4 197
	174	+#define CMDQ_EVENT_GCE_IMG2_EVENT5 198
	175	+#define CMDQ_EVENT_GCE_IMG2_EVENT6 199
	176	+#define CMDQ_EVENT_GCE_IMG2_EVENT7 200
	177	+#define CMDQ_EVENT_GCE_IMG2_EVENT8 201
	178	+#define CMDQ_EVENT_GCE_IMG2_EVENT9 202
	179	+#define CMDQ_EVENT_GCE_IMG2_EVENT10 203
	180	+#define CMDQ_EVENT_GCE_IMG2_EVENT11 204
	181	+#define CMDQ_EVENT_GCE_IMG2_EVENT12 205
	182	+#define CMDQ_EVENT_GCE_IMG2_EVENT13 206
	183	+#define CMDQ_EVENT_GCE_IMG2_EVENT14 207
	184	+#define CMDQ_EVENT_GCE_IMG2_EVENT15 208
	185	+#define CMDQ_EVENT_GCE_IMG2_EVENT16 209
	186	+#define CMDQ_EVENT_GCE_IMG2_EVENT17 210
	187	+#define CMDQ_EVENT_GCE_IMG2_EVENT18 211
	188	+#define CMDQ_EVENT_GCE_IMG2_EVENT19 212
	189	+#define CMDQ_EVENT_GCE_IMG2_EVENT20 213
	190	+#define CMDQ_EVENT_GCE_IMG2_EVENT21 214
	191	+#define CMDQ_EVENT_GCE_IMG2_EVENT22 215
	192	+#define CMDQ_EVENT_GCE_IMG2_EVENT23 216
	193	+/* IMG1 */
	194	+#define CMDQ_EVENT_GCE_IMG1_EVENT0 225
	195	+#define CMDQ_EVENT_GCE_IMG1_EVENT1 226
	196	+#define CMDQ_EVENT_GCE_IMG1_EVENT2 227
	197	+#define CMDQ_EVENT_GCE_IMG1_EVENT3 228
	198	+#define CMDQ_EVENT_GCE_IMG1_EVENT4 229
	199	+#define CMDQ_EVENT_GCE_IMG1_EVENT5 230
	200	+#define CMDQ_EVENT_GCE_IMG1_EVENT6 231
	201	+#define CMDQ_EVENT_GCE_IMG1_EVENT7 232
	202	+#define CMDQ_EVENT_GCE_IMG1_EVENT8 233
	203	+#define CMDQ_EVENT_GCE_IMG1_EVENT9 234
	204	+#define CMDQ_EVENT_GCE_IMG1_EVENT10 235
	205	+#define CMDQ_EVENT_GCE_IMG1_EVENT11 236
	206	+#define CMDQ_EVENT_GCE_IMG1_EVENT12 237
	207	+#define CMDQ_EVENT_GCE_IMG1_EVENT13 238
	208	+#define CMDQ_EVENT_GCE_IMG1_EVENT14 239
	209	+#define CMDQ_EVENT_GCE_IMG1_EVENT15 240
	210	+#define CMDQ_EVENT_GCE_IMG1_EVENT16 241
	211	+#define CMDQ_EVENT_GCE_IMG1_EVENT17 242
	212	+#define CMDQ_EVENT_GCE_IMG1_EVENT18 243
	213	+#define CMDQ_EVENT_GCE_IMG1_EVENT19 244
	214	+#define CMDQ_EVENT_GCE_IMG1_EVENT20 245
	215	+#define CMDQ_EVENT_GCE_IMG1_EVENT21 246
	216	+#define CMDQ_EVENT_GCE_IMG1_EVENT22 247
	217	+#define CMDQ_EVENT_GCE_IMG1_EVENT23 248
	218	+/* MDP */
	219	+#define CMDQ_EVENT_MDP_RDMA0_SOF 256
	220	+#define CMDQ_EVENT_MDP_RDMA1_SOF 257
	221	+#define CMDQ_EVENT_MDP_AAL0_SOF 258
	222	+#define CMDQ_EVENT_MDP_AAL1_SOF 259
	223	+#define CMDQ_EVENT_MDP_HDR0_SOF 260
	224	+#define CMDQ_EVENT_MDP_RSZ0_SOF 261
	225	+#define CMDQ_EVENT_MDP_RSZ1_SOF 262
	226	+#define CMDQ_EVENT_MDP_WROT0_SOF 263
	227	+#define CMDQ_EVENT_MDP_WROT1_SOF 264
	228	+#define CMDQ_EVENT_MDP_TDSHP0_SOF 265
	229	+#define CMDQ_EVENT_MDP_TDSHP1_SOF 266
	230	+#define CMDQ_EVENT_IMG_DL_RELAY0_SOF 267
	231	+#define CMDQ_EVENT_IMG_DL_RELAY1_SOF 268
	232	+#define CMDQ_EVENT_MDP_COLOR0_SOF 269
	233	+#define CMDQ_EVENT_MDP_WROT3_FRAME_DONE 288
	234	+#define CMDQ_EVENT_MDP_WROT2_FRAME_DONE 289
	235	+#define CMDQ_EVENT_MDP_WROT1_FRAME_DONE 290
	236	+#define CMDQ_EVENT_MDP_WROT0_FRAME_DONE 291
	237	+#define CMDQ_EVENT_MDP_TDSHP3_FRAME_DONE 292
	238	+#define CMDQ_EVENT_MDP_TDSHP2_FRAME_DONE 293
	239	+#define CMDQ_EVENT_MDP_TDSHP1_FRAME_DONE 294
	240	+#define CMDQ_EVENT_MDP_TDSHP0_FRAME_DONE 295
	241	+#define CMDQ_EVENT_MDP_RSZ3_FRAME_DONE 296
	242	+#define CMDQ_EVENT_MDP_RSZ2_FRAME_DONE 297
	243	+#define CMDQ_EVENT_MDP_RSZ1_FRAME_DONE 298
	244	+#define CMDQ_EVENT_MDP_RSZ0_FRAME_DONE 299
	245	+#define CMDQ_EVENT_MDP_RDMA3_FRAME_DONE 300
	246	+#define CMDQ_EVENT_MDP_RDMA2_FRAME_DONE 301
	247	+#define CMDQ_EVENT_MDP_RDMA1_FRAME_DONE 302
	248	+#define CMDQ_EVENT_MDP_RDMA0_FRAME_DONE 303
	249	+#define CMDQ_EVENT_MDP_HDR1_FRAME_DONE 304
	250	+#define CMDQ_EVENT_MDP_HDR0_FRAME_DONE 305
	251	+#define CMDQ_EVENT_MDP_COLOR0_FRAME_DONE 306
	252	+#define CMDQ_EVENT_MDP_AAL3_FRAME_DONE 307
	253	+#define CMDQ_EVENT_MDP_AAL2_FRAME_DONE 308
	254	+#define CMDQ_EVENT_MDP_AAL1_FRAME_DONE 309
	255	+#define CMDQ_EVENT_MDP_AAL0_FRAME_DONE 310
	256	+#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_0 320
	257	+#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_1 321
	258	+#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_2 322
	259	+#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_3 323
	260	+#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_4 324
	261	+#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_5 325
	262	+#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_6 326
	263	+#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_7 327
	264	+#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_8 328
	265	+#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_9 329
	266	+#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_10 330
	267	+#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_11 331
	268	+#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_12 332
	269	+#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_13 333
	270	+#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_14 334
	271	+#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_15 335
	272	+#define CMDQ_EVENT_MDP_WROT3_SW_RST_DONE_ENG_EVENT 336
	273	+#define CMDQ_EVENT_MDP_WROT2_SW_RST_DONE_ENG_EVENT 337
	274	+#define CMDQ_EVENT_MDP_WROT1_SW_RST_DONE_ENG_EVENT 338
	275	+#define CMDQ_EVENT_MDP_WROT0_SW_RST_DONE_ENG_EVENT 339
	276	+#define CMDQ_EVENT_MDP_RDMA3_SW_RST_DONE_ENG_EVENT 340
	277	+#define CMDQ_EVENT_MDP_RDMA2_SW_RST_DONE_ENG_EVENT 341
	278	+#define CMDQ_EVENT_MDP_RDMA1_SW_RST_DONE_ENG_EVENT 342
	279	+#define CMDQ_EVENT_MDP_RDMA0_SW_RST_DONE_ENG_EVENT 343
	280	+/* DISP */
	281	+#define CMDQ_EVENT_DISP_OVL0_SOF 384
	282	+#define CMDQ_EVENT_DISP_OVL0_2L_SOF 385
	283	+#define CMDQ_EVENT_DISP_RDMA0_SOF 386
	284	+#define CMDQ_EVENT_DISP_RSZ0_SOF 387
	285	+#define CMDQ_EVENT_DISP_COLOR0_SOF 388
	286	+#define CMDQ_EVENT_DISP_CCORR0_SOF 389
	287	+#define CMDQ_EVENT_DISP_CCORR1_SOF 390
	288	+#define CMDQ_EVENT_DISP_AAL0_SOF 391
	289	+#define CMDQ_EVENT_DISP_GAMMA0_SOF 392
	290	+#define CMDQ_EVENT_DISP_POSTMASK0_SOF 393
	291	+#define CMDQ_EVENT_DISP_DITHER0_SOF 394
	292	+#define CMDQ_EVENT_DISP_CM0_SOF 395
	293	+#define CMDQ_EVENT_DISP_SPR0_SOF 396
	294	+#define CMDQ_EVENT_DISP_DSC_WRAP0_SOF 397
	295	+#define CMDQ_EVENT_DSI0_SOF 398
	296	+#define CMDQ_EVENT_DISP_WDMA0_SOF 399
	297	+#define CMDQ_EVENT_DISP_PWM0_SOF 400
	298	+#define CMDQ_EVENT_DSI0_FRAME_DONE 410
	299	+#define CMDQ_EVENT_DISP_WDMA0_FRAME_DONE 411
	300	+#define CMDQ_EVENT_DISP_SPR0_FRAME_DONE 412
	301	+#define CMDQ_EVENT_DISP_RSZ0_FRAME_DONE 413
	302	+#define CMDQ_EVENT_DISP_RDMA0_FRAME_DONE 414
	303	+#define CMDQ_EVENT_DISP_POSTMASK0_FRAME_DONE 415
	304	+#define CMDQ_EVENT_DISP_OVL0_FRAME_DONE 416
	305	+#define CMDQ_EVENT_DISP_OVL0_2L_FRAME_DONE 417
	306	+#define CMDQ_EVENT_DISP_GAMMA0_FRAME_DONE 418
	307	+#define CMDQ_EVENT_DISP_DSC_WRAP0_CORE0_FRAME_DONE 420
	308	+#define CMDQ_EVENT_DISP_DITHER0_FRAME_DONE 421
	309	+#define CMDQ_EVENT_DISP_COLOR0_FRAME_DONE 422
	310	+#define CMDQ_EVENT_DISP_CM0_FRAME_DONE 423
	311	+#define CMDQ_EVENT_DISP_CCORR1_FRAME_DONE 424
	312	+#define CMDQ_EVENT_DISP_CCORR0_FRAME_DONE 425
	313	+#define CMDQ_EVENT_DISP_AAL0_FRAME_DONE 426
	314	+#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0 434
	315	+#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1 435
	316	+#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_2 436
	317	+#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_3 437
	318	+#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_4 438
	319	+#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_5 439
	320	+#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_6 440
	321	+#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_7 441
	322	+#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_8 442
	323	+#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_9 443
	324	+#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_10 444
	325	+#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_11 445
	326	+#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_12 446
	327	+#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_13 447
	328	+#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_14 448
	329	+#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_15 449
	330	+#define CMDQ_EVENT_DSI0_TE_ENG_EVENT 450
	331	+#define CMDQ_EVENT_DSI0_IRQ_ENG_EVENT 451
	332	+#define CMDQ_EVENT_DSI0_DONE_ENG_EVENT 452
	333	+#define CMDQ_EVENT_DISP_WDMA0_SW_RST_DONE_ENG_EVENT 453
	334	+#define CMDQ_EVENT_DISP_SMIASSERT_ENG_EVENT 454
	335	+#define CMDQ_EVENT_DISP_POSTMASK0_RST_DONE_ENG_EVENT 455
	336	+#define CMDQ_EVENT_DISP_OVL0_RST_DONE_ENG_EVENT 456
	337	+#define CMDQ_EVENT_DISP_OVL0_2L_RST_DONE_ENG_EVENT 457
	338	+#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_0 458
	339	+#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_1 459
	340	+#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_2 460
	341	+#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_3 461
	342	+#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_4 462
	343	+#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_5 463
	344	+#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_6 464
	345	+#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_7 465
	346	+#define CMDQ_EVENT_OUT_EVENT_0 898
	347	+
	348	+/* CMDQ sw tokens
	349	+ * Following definitions are gce sw token which may use by clients
	350	+ * event operation API.
	351	+ * Note that token 512 to 639 may set secure
	352	+ */
	353	+
	354	+/* end of hw event and begin of sw token */
	355	+#define CMDQ_MAX_HW_EVENT 512
	356	+
	357	+/* Config thread notify trigger thread */
	358	+#define CMDQ_SYNC_TOKEN_CONFIG_DIRTY 640
	359	+/* Trigger thread notify config thread */
	360	+#define CMDQ_SYNC_TOKEN_STREAM_EOF 641
	361	+/* Block Trigger thread until the ESD check finishes. */
	362	+#define CMDQ_SYNC_TOKEN_ESD_EOF 642
	363	+#define CMDQ_SYNC_TOKEN_STREAM_BLOCK 643
	364	+/* check CABC setup finish */
	365	+#define CMDQ_SYNC_TOKEN_CABC_EOF 644
	366	+
	367	+/* Notify normal CMDQ there are some secure task done
	368	+ * MUST NOT CHANGE, this token sync with secure world
	369	+ */
	370	+#define CMDQ_SYNC_SECURE_THR_EOF 647
	371	+
	372	+/* CMDQ use sw token */
	373	+#define CMDQ_SYNC_TOKEN_USER_0 649
	374	+#define CMDQ_SYNC_TOKEN_USER_1 650
	375	+#define CMDQ_SYNC_TOKEN_POLL_MONITOR 651
	376	+#define CMDQ_SYNC_TOKEN_TPR_LOCK 652
	377	+
	378	+/* ISP sw token */
	379	+#define CMDQ_SYNC_TOKEN_MSS 665
	380	+#define CMDQ_SYNC_TOKEN_MSF 666
	381	+
	382	+/* DISP sw token */
	383	+#define CMDQ_SYNC_TOKEN_SODI 671
	384	+
	385	+/* GPR access tokens (for register backup)
	386	+ * There are 15 32-bit GPR, 3 GPR form a set
	387	+ * (64-bit for address, 32-bit for value)
	388	+ * MUST NOT CHANGE, these tokens sync with MDP
	389	+ */
	390	+#define CMDQ_SYNC_TOKEN_GPR_SET_0 700
	391	+#define CMDQ_SYNC_TOKEN_GPR_SET_1 701
	392	+#define CMDQ_SYNC_TOKEN_GPR_SET_2 702
	393	+#define CMDQ_SYNC_TOKEN_GPR_SET_3 703
	394	+#define CMDQ_SYNC_TOKEN_GPR_SET_4 704
	395	+
	396	+/* Resource lock event to control resource in GCE thread */
	397	+#define CMDQ_SYNC_RESOURCE_WROT0 710
	398	+#define CMDQ_SYNC_RESOURCE_WROT1 711
	399	+
	400	+/* event for gpr timer, used in sleep and poll with timeout */
	401	+#define CMDQ_TOKEN_GPR_TIMER_R0 994
	402	+#define CMDQ_TOKEN_GPR_TIMER_R1 995
	403	+#define CMDQ_TOKEN_GPR_TIMER_R2 996
	404	+#define CMDQ_TOKEN_GPR_TIMER_R3 997
	405	+#define CMDQ_TOKEN_GPR_TIMER_R4 998
	406	+#define CMDQ_TOKEN_GPR_TIMER_R5 999
	407	+#define CMDQ_TOKEN_GPR_TIMER_R6 1000
	408	+#define CMDQ_TOKEN_GPR_TIMER_R7 1001
	409	+#define CMDQ_TOKEN_GPR_TIMER_R8 1002
	410	+#define CMDQ_TOKEN_GPR_TIMER_R9 1003
	411	+#define CMDQ_TOKEN_GPR_TIMER_R10 1004
	412	+#define CMDQ_TOKEN_GPR_TIMER_R11 1005
	413	+#define CMDQ_TOKEN_GPR_TIMER_R12 1006
	414	+#define CMDQ_TOKEN_GPR_TIMER_R13 1007
	415	+#define CMDQ_TOKEN_GPR_TIMER_R14 1008
	416	+#define CMDQ_TOKEN_GPR_TIMER_R15 1009
	417	+
	418	+#define CMDQ_EVENT_MAX 0x3FF
	419	+/* CMDQ sw tokens END */
	420	+
	421	+#endif

include/dt-bindings/mailbox/tegra186-hsp.h+5−0

@@ -15,6 +15,11 @@ · 14 unmodified lines
15	15	#define TEGRA_HSP_MBOX_TYPE_SS 0x2
16	16	#define TEGRA_HSP_MBOX_TYPE_AS 0x3
17	17
	18	+/*
	19	+ * These define the types of shared mailbox supported based on data size.
	20	+ */
	21	+#define TEGRA_HSP_MBOX_TYPE_SM_128BIT (1 << 8)
	22	+
18	23	/*
19	24	* These defines represent the bit associated with the given master ID in the
20	25	* doorbell registers.

include/linux/mailbox_controller.h+1−0

@@ -83,6 +83,7 @@ struct mbox_controller { · 82 unmodified lines
83	83	const struct of_phandle_args *sp);
84	84	/* Internal to API */
85	85	struct hrtimer poll_hrt;
	86	+ spinlock_t poll_hrt_lock;
86	87	struct list_head node;
87	88	};
88	89