History

Merge tag 'drm-fixes-2024-05-11' of https://gitlab.freedesktop.org/drm/kernel

Pull drm fixes from Dave Airlie: "This should be the last set of fixes for 6.9, i915, xe and amdgpu are the bulk here, one of the previous nouveau fixes turned up an issue, so reverting it, otherwise one core and a couple of meson fixes. core: - fix connector debugging output i915: - Automate CCS Mode setting during engine resets - Fix audio time stamp programming for DP - Fix parsing backlight BDB data xe: - Fix use zero-length element array - Move more from system wq to ordered private wq - Do not ignore return for drmm_mutex_init amdgpu: - DCN 3.5 fix - MST DSC fixes - S0i3 fix - S4 fix - HDP MMIO mapping fix - Fix a regression in visible vram handling amdkfd: - Spatial partition fix meson: - dw-hdmi: power-up fixes - dw-hdmi: add badngap setting for g12 nouveau: - revert SG_DEBUG fix that has a side effect" * tag 'drm-fixes-2024-05-11' of https://gitlab.freedesktop.org/drm/kernel: Revert "drm/nouveau/firmware: Fix SG_DEBUG error with nvkm_firmware_ctor()" drm/amdgpu: Fix comparison in amdgpu_res_cpu_visible drm/amdkfd: don't allow mapping the MMIO HDP page with large pages drm/xe: Use ordered WQ for G2H handler drm/xe/guc: Check error code when initializing the CT mutex drm/xe/ads: Use flexible-array Revert "drm/amdkfd: Add partition id field to location_id" dm/amd/pm: Fix problems with reboot/shutdown for some SMU 13.0.4/13.0.11 users drm/amd/display: MST DSC check for older devices drm/amd/display: Fix idle optimization checks for multi-display and dual eDP drm/amd/display: Fix DSC-re-computing drm/amd/display: Enable urgent latency adjustments for DCN35 drm/connector: Add \n to message about demoting connector force-probes drm/i915/bios: Fix parsing backlight BDB data drm/i915/audio: Fix audio time stamp programming for DP drm/i915/gt: Automate CCS Mode setting during engine resets drm/meson: dw-hdmi: add bandgap setting for g12 drm/meson: dw-hdmi: power up phy on device init

Linus Torvalds committed 2 years ago

Commit cf87f462 parents c22c3e0 a222a6420 files · +122 −203Browse files

Unified · Split

20 files
  1. drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +1 −1
  2. drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +5 −2
  3. drivers/gpu/drm/amd/amdkfd/kfd_topology.c +2 −3
  4. drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +13 −3
  5. drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c +2 −2
  6. drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c +27 −6
  7. drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c +1 −1
  8. drivers/gpu/drm/drm_connector.c +1 −1
  9. drivers/gpu/drm/i915/display/intel_audio.c +8 −105
  10. drivers/gpu/drm/i915/display/intel_bios.c +4 −15
  11. drivers/gpu/drm/i915/display/intel_vbt_defs.h +0 −5
  12. drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c +3 −3
  13. drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h +1 −1
  14. drivers/gpu/drm/i915/gt/intel_workarounds.c +3 −1
  15. drivers/gpu/drm/meson/meson_dw_hdmi.c +31 −39
  16. drivers/gpu/drm/nouveau/nvkm/core/firmware.c +7 −12
  17. drivers/gpu/drm/xe/xe_guc_ads.c +1 −1
  18. drivers/gpu/drm/xe/xe_guc_ct.c +9 −1
  19. drivers/gpu/drm/xe/xe_guc_ct.h +1 −1
  20. drivers/gpu/drm/xe/xe_guc_ct_types.h +2 −0
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c+1−1
@@ -427,7 +427,7 @@ bool amdgpu_res_cpu_visible(struct amdgpu_device *adev, · 426 unmodified lines
427 427
428 amdgpu_res_first(res, 0, res->size, &cursor);428 amdgpu_res_first(res, 0, res->size, &cursor);
429 while (cursor.remaining) {429 while (cursor.remaining) {
430 if ((cursor.start + cursor.size) >= adev->gmc.visible_vram_size)430 if ((cursor.start + cursor.size) > adev->gmc.visible_vram_size)
431 return false;431 return false;
432 amdgpu_res_next(&cursor, cursor.size);432 amdgpu_res_next(&cursor, cursor.size);
433 }433 }
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c+5−2
@@ -1139,7 +1139,7 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, · 1138 unmodified lines
1139 goto err_unlock;1139 goto err_unlock;
1140 }1140 }
1141 offset = dev->adev->rmmio_remap.bus_addr;1141 offset = dev->adev->rmmio_remap.bus_addr;
1142 if (!offset) {1142 if (!offset || (PAGE_SIZE > 4096)) {
1143 err = -ENOMEM;1143 err = -ENOMEM;
1144 goto err_unlock;1144 goto err_unlock;
1145 }1145 }
@@ -2307,7 +2307,7 @@ static int criu_restore_memory_of_gpu(struct kfd_process_device *pdd, · 1161 unmodified lines
2307 return -EINVAL;2307 return -EINVAL;
2308 }2308 }
2309 offset = pdd->dev->adev->rmmio_remap.bus_addr;2309 offset = pdd->dev->adev->rmmio_remap.bus_addr;
2310 if (!offset) {2310 if (!offset || (PAGE_SIZE > 4096)) {
2311 pr_err("amdgpu_amdkfd_get_mmio_remap_phys_addr failed\n");2311 pr_err("amdgpu_amdkfd_get_mmio_remap_phys_addr failed\n");
2312 return -ENOMEM;2312 return -ENOMEM;
2313 }2313 }
@@ -3349,6 +3349,9 @@ static int kfd_mmio_mmap(struct kfd_node *dev, struct kfd_process *process, · 1035 unmodified lines
3349 if (vma->vm_end - vma->vm_start != PAGE_SIZE)3349 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
3350 return -EINVAL;3350 return -EINVAL;
3351 3351
3352 if (PAGE_SIZE > 4096)
3353 return -EINVAL;
3354
3352 address = dev->adev->rmmio_remap.bus_addr;3355 address = dev->adev->rmmio_remap.bus_addr;
3353 3356
3354 vm_flags_set(vma, VM_IO | VM_DONTCOPY | VM_DONTEXPAND | VM_NORESERVE |3357 vm_flags_set(vma, VM_IO | VM_DONTCOPY | VM_DONTEXPAND | VM_NORESERVE |
drivers/gpu/drm/amd/amdkfd/kfd_topology.c+2−3
@@ -1997,9 +1997,8 @@ int kfd_topology_add_device(struct kfd_node *gpu) · 1996 unmodified lines
1997 HSA_CAP_ASIC_REVISION_MASK);1997 HSA_CAP_ASIC_REVISION_MASK);
1998 1998
1999 dev->node_props.location_id = pci_dev_id(gpu->adev->pdev);1999 dev->node_props.location_id = pci_dev_id(gpu->adev->pdev);
2000 /* On multi-partition nodes, node id = location_id[31:28] */2000 if (KFD_GC_VERSION(dev->gpu->kfd) == IP_VERSION(9, 4, 3))
2001 if (gpu->kfd->num_nodes > 1)2001 dev->node_props.location_id |= dev->gpu->node_id;
2002 dev->node_props.location_id |= (dev->gpu->node_id << 28);
2003 2002
2004 dev->node_props.domain = pci_domain_nr(gpu->adev->pdev->bus);2003 dev->node_props.domain = pci_domain_nr(gpu->adev->pdev->bus);
2005 dev->node_props.max_engine_clk_fcompute =2004 dev->node_props.max_engine_clk_fcompute =
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c+13−3
@@ -1219,8 +1219,10 @@ static bool is_dsc_need_re_compute( · 1218 unmodified lines
1219 if (dc_link->type != dc_connection_mst_branch)1219 if (dc_link->type != dc_connection_mst_branch)
1220 return false;1220 return false;
1221 1221
1222 if (!(dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT ||1222 /* add a check for older MST DSC with no virtual DPCDs */
1223 dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT))1223 if (needs_dsc_aux_workaround(dc_link) &&
1224 (!(dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT ||
1225 dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT)))
1224 return false;1226 return false;
1225 1227
1226 for (i = 0; i < MAX_PIPES; i++)1228 for (i = 0; i < MAX_PIPES; i++)
@@ -1240,7 +1242,15 @@ static bool is_dsc_need_re_compute( · 13 unmodified lines
1240 continue;1242 continue;
1241 1243
1242 aconnector = (struct amdgpu_dm_connector *) stream->dm_stream_context;1244 aconnector = (struct amdgpu_dm_connector *) stream->dm_stream_context;
1243 if (!aconnector)1245 if (!aconnector || !aconnector->dsc_aux)
1246 continue;
1247
1248 /*
1249 * check if cached virtual MST DSC caps are available and DSC is supported
1250 * as per specifications in their Virtual DPCD registers.
1251 */
1252 if (!(aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported ||
1253 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT))
1244 continue;1254 continue;
1245 1255
1246 stream_on_link[new_stream_on_link_num] = aconnector;1256 stream_on_link[new_stream_on_link_num] = aconnector;
drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c+2−2
@@ -195,9 +195,9 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_5_soc = { · 194 unmodified lines
195 .dcn_downspread_percent = 0.5,195 .dcn_downspread_percent = 0.5,
196 .gpuvm_min_page_size_bytes = 4096,196 .gpuvm_min_page_size_bytes = 4096,
197 .hostvm_min_page_size_bytes = 4096,197 .hostvm_min_page_size_bytes = 4096,
198 .do_urgent_latency_adjustment = 0,198 .do_urgent_latency_adjustment = 1,
199 .urgent_latency_adjustment_fabric_clock_component_us = 0,199 .urgent_latency_adjustment_fabric_clock_component_us = 0,
200 .urgent_latency_adjustment_fabric_clock_reference_mhz = 0,200 .urgent_latency_adjustment_fabric_clock_reference_mhz = 3000,
201};201};
202 202
203void dcn35_build_wm_range_table_fpu(struct clk_mgr *clk_mgr)203void dcn35_build_wm_range_table_fpu(struct clk_mgr *clk_mgr)
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c+27−6
@@ -638,22 +638,43 @@ void dcn35_power_down_on_boot(struct dc *dc) · 637 unmodified lines
638 638
639bool dcn35_apply_idle_power_optimizations(struct dc *dc, bool enable)639bool dcn35_apply_idle_power_optimizations(struct dc *dc, bool enable)
640{640{
641 struct dc_link *edp_links[MAX_NUM_EDP];
642 int i, edp_num;
643 if (dc->debug.dmcub_emulation)641 if (dc->debug.dmcub_emulation)
644 return true;642 return true;
645 643
646 if (enable) {644 if (enable) {
647 dc_get_edp_links(dc, edp_links, &edp_num);645 uint32_t num_active_edp = 0;
648 if (edp_num == 0 || edp_num > 1)646 int i;
649 return false;
650 647
651 for (i = 0; i < dc->current_state->stream_count; ++i) {648 for (i = 0; i < dc->current_state->stream_count; ++i) {
652 struct dc_stream_state *stream = dc->current_state->streams[i];649 struct dc_stream_state *stream = dc->current_state->streams[i];
650 struct dc_link *link = stream->link;
651 bool is_psr = link && !link->panel_config.psr.disable_psr &&
652 (link->psr_settings.psr_version == DC_PSR_VERSION_1 ||
653 link->psr_settings.psr_version == DC_PSR_VERSION_SU_1);
654 bool is_replay = link && link->replay_settings.replay_feature_enabled;
655
656 /* Ignore streams that disabled. */
657 if (stream->dpms_off)
658 continue;
659
660 /* Active external displays block idle optimizations. */
661 if (!dc_is_embedded_signal(stream->signal))
662 return false;
663
664 /* If not PWRSEQ0 can't enter idle optimizations */
665 if (link && link->link_index != 0)
666 return false;
653 667
654 if (!stream->dpms_off && !dc_is_embedded_signal(stream->signal))668 /* Check for panel power features required for idle optimizations. */
669 if (!is_psr && !is_replay)
655 return false;670 return false;
671
672 num_active_edp += 1;
656 }673 }
674
675 /* If more than one active eDP then disallow. */
676 if (num_active_edp > 1)
677 return false;
657 }678 }
658 679
659 // TODO: review other cases when idle optimization is allowed680 // TODO: review other cases when idle optimization is allowed
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c+1−1
@@ -226,7 +226,7 @@ static int smu_v13_0_4_system_features_control(struct smu_context *smu, bool en) · 225 unmodified lines
226 struct amdgpu_device *adev = smu->adev;226 struct amdgpu_device *adev = smu->adev;
227 int ret = 0;227 int ret = 0;
228 228
229 if (!en && !adev->in_s0ix) {229 if (!en && adev->in_s4) {
230 /* Adds a GFX reset as workaround just before sending the230 /* Adds a GFX reset as workaround just before sending the
231 * MP1_UNLOAD message to prevent GC/RLC/PMFW from entering231 * MP1_UNLOAD message to prevent GC/RLC/PMFW from entering
232 * an invalid state.232 * an invalid state.
drivers/gpu/drm/drm_connector.c+1−1
@@ -2940,7 +2940,7 @@ int drm_mode_getconnector(struct drm_device *dev, void *data, · 2939 unmodified lines
2940 dev->mode_config.max_width,2940 dev->mode_config.max_width,
2941 dev->mode_config.max_height);2941 dev->mode_config.max_height);
2942 else2942 else
2943 drm_dbg_kms(dev, "User-space requested a forced probe on [CONNECTOR:%d:%s] but is not the DRM master, demoting to read-only probe",2943 drm_dbg_kms(dev, "User-space requested a forced probe on [CONNECTOR:%d:%s] but is not the DRM master, demoting to read-only probe\n",
2944 connector->base.id, connector->name);2944 connector->base.id, connector->name);
2945 }2945 }
2946 2946
drivers/gpu/drm/i915/display/intel_audio.c+8−105
@@ -76,19 +76,6 @@ struct intel_audio_funcs { · 75 unmodified lines
76 struct intel_crtc_state *crtc_state);76 struct intel_crtc_state *crtc_state);
77};77};
78 78
79/* DP N/M table */
80#define LC_810M 810000
81#define LC_540M 540000
82#define LC_270M 270000
83#define LC_162M 162000
84
85struct dp_aud_n_m {
86 int sample_rate;
87 int clock;
88 u16 m;
89 u16 n;
90};
91
92struct hdmi_aud_ncts {79struct hdmi_aud_ncts {
93 int sample_rate;80 int sample_rate;
94 int clock;81 int clock;
@@ -96,60 +83,6 @@ struct hdmi_aud_ncts { · 1 unmodified line
96 int cts;83 int cts;
97};84};
98 85
99/* Values according to DP 1.4 Table 2-104 */
100static const struct dp_aud_n_m dp_aud_n_m[] = {
101 { 32000, LC_162M, 1024, 10125 },
102 { 44100, LC_162M, 784, 5625 },
103 { 48000, LC_162M, 512, 3375 },
104 { 64000, LC_162M, 2048, 10125 },
105 { 88200, LC_162M, 1568, 5625 },
106 { 96000, LC_162M, 1024, 3375 },
107 { 128000, LC_162M, 4096, 10125 },
108 { 176400, LC_162M, 3136, 5625 },
109 { 192000, LC_162M, 2048, 3375 },
110 { 32000, LC_270M, 1024, 16875 },
111 { 44100, LC_270M, 784, 9375 },
112 { 48000, LC_270M, 512, 5625 },
113 { 64000, LC_270M, 2048, 16875 },
114 { 88200, LC_270M, 1568, 9375 },
115 { 96000, LC_270M, 1024, 5625 },
116 { 128000, LC_270M, 4096, 16875 },
117 { 176400, LC_270M, 3136, 9375 },
118 { 192000, LC_270M, 2048, 5625 },
119 { 32000, LC_540M, 1024, 33750 },
120 { 44100, LC_540M, 784, 18750 },
121 { 48000, LC_540M, 512, 11250 },
122 { 64000, LC_540M, 2048, 33750 },
123 { 88200, LC_540M, 1568, 18750 },
124 { 96000, LC_540M, 1024, 11250 },
125 { 128000, LC_540M, 4096, 33750 },
126 { 176400, LC_540M, 3136, 18750 },
127 { 192000, LC_540M, 2048, 11250 },
128 { 32000, LC_810M, 1024, 50625 },
129 { 44100, LC_810M, 784, 28125 },
130 { 48000, LC_810M, 512, 16875 },
131 { 64000, LC_810M, 2048, 50625 },
132 { 88200, LC_810M, 1568, 28125 },
133 { 96000, LC_810M, 1024, 16875 },
134 { 128000, LC_810M, 4096, 50625 },
135 { 176400, LC_810M, 3136, 28125 },
136 { 192000, LC_810M, 2048, 16875 },
137};
138
139static const struct dp_aud_n_m *
140audio_config_dp_get_n_m(const struct intel_crtc_state *crtc_state, int rate)
141{
142 int i;
143
144 for (i = 0; i < ARRAY_SIZE(dp_aud_n_m); i++) {
145 if (rate == dp_aud_n_m[i].sample_rate &&
146 crtc_state->port_clock == dp_aud_n_m[i].clock)
147 return &dp_aud_n_m[i];
148 }
149
150 return NULL;
151}
152
153static const struct {86static const struct {
154 int clock;87 int clock;
155 u32 config;88 u32 config;
@@ -387,47 +320,17 @@ hsw_dp_audio_config_update(struct intel_encoder *encoder, · 231 unmodified lines
387 const struct intel_crtc_state *crtc_state)320 const struct intel_crtc_state *crtc_state)
388{321{
389 struct drm_i915_private *i915 = to_i915(encoder->base.dev);322 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
390 struct i915_audio_component *acomp = i915->display.audio.component;
391 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;323 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
392 enum port port = encoder->port;
393 const struct dp_aud_n_m *nm;
394 int rate;
395 u32 tmp;
396
397 rate = acomp ? acomp->aud_sample_rate[port] : 0;
398 nm = audio_config_dp_get_n_m(crtc_state, rate);
399 if (nm)
400 drm_dbg_kms(&i915->drm, "using Maud %u, Naud %u\n", nm->m,
401 nm->n);
402 else
403 drm_dbg_kms(&i915->drm, "using automatic Maud, Naud\n");
404
405 tmp = intel_de_read(i915, HSW_AUD_CFG(cpu_transcoder));
406 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
407 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
408 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
409 tmp |= AUD_CONFIG_N_VALUE_INDEX;
410 324
411 if (nm) {325 /* Enable time stamps. Let HW calculate Maud/Naud values */
412 tmp &= ~AUD_CONFIG_N_MASK;326 intel_de_rmw(i915, HSW_AUD_CFG(cpu_transcoder),
413 tmp |= AUD_CONFIG_N(nm->n);327 AUD_CONFIG_N_VALUE_INDEX |
414 tmp |= AUD_CONFIG_N_PROG_ENABLE;328 AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK |
415 }329 AUD_CONFIG_UPPER_N_MASK |
416 330 AUD_CONFIG_LOWER_N_MASK |
417 intel_de_write(i915, HSW_AUD_CFG(cpu_transcoder), tmp);331 AUD_CONFIG_N_PROG_ENABLE,
418 332 AUD_CONFIG_N_VALUE_INDEX);
419 tmp = intel_de_read(i915, HSW_AUD_M_CTS_ENABLE(cpu_transcoder));
420 tmp &= ~AUD_CONFIG_M_MASK;
421 tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
422 tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
423
424 if (nm) {
425 tmp |= nm->m;
426 tmp |= AUD_M_CTS_M_VALUE_INDEX;
427 tmp |= AUD_M_CTS_M_PROG_ENABLE;
428 }
429 333
430 intel_de_write(i915, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp);
431}334}
432 335
433static void336static void
drivers/gpu/drm/i915/display/intel_bios.c+4−15
@@ -1042,22 +1042,11 @@ parse_lfp_backlight(struct drm_i915_private *i915, · 1041 unmodified lines
1042 panel->vbt.backlight.type = INTEL_BACKLIGHT_DISPLAY_DDI;1042 panel->vbt.backlight.type = INTEL_BACKLIGHT_DISPLAY_DDI;
1043 panel->vbt.backlight.controller = 0;1043 panel->vbt.backlight.controller = 0;
1044 if (i915->display.vbt.version >= 191) {1044 if (i915->display.vbt.version >= 191) {
1045 size_t exp_size;1045 const struct lfp_backlight_control_method *method;
1046 1046
1047 if (i915->display.vbt.version >= 236)1047 method = &backlight_data->backlight_control[panel_type];
1048 exp_size = sizeof(struct bdb_lfp_backlight_data);1048 panel->vbt.backlight.type = method->type;
1049 else if (i915->display.vbt.version >= 234)1049 panel->vbt.backlight.controller = method->controller;
1050 exp_size = EXP_BDB_LFP_BL_DATA_SIZE_REV_234;
1051 else
1052 exp_size = EXP_BDB_LFP_BL_DATA_SIZE_REV_191;
1053
1054 if (get_blocksize(backlight_data) >= exp_size) {
1055 const struct lfp_backlight_control_method *method;
1056
1057 method = &backlight_data->backlight_control[panel_type];
1058 panel->vbt.backlight.type = method->type;
1059 panel->vbt.backlight.controller = method->controller;
1060 }
1061 }1050 }
1062 1051
1063 panel->vbt.backlight.pwm_freq_hz = entry->pwm_freq_hz;1052 panel->vbt.backlight.pwm_freq_hz = entry->pwm_freq_hz;
drivers/gpu/drm/i915/display/intel_vbt_defs.h+0−5
@@ -897,11 +897,6 @@ struct lfp_brightness_level { · 896 unmodified lines
897 u16 reserved;897 u16 reserved;
898} __packed;898} __packed;
899 899
900#define EXP_BDB_LFP_BL_DATA_SIZE_REV_191 \
901 offsetof(struct bdb_lfp_backlight_data, brightness_level)
902#define EXP_BDB_LFP_BL_DATA_SIZE_REV_234 \
903 offsetof(struct bdb_lfp_backlight_data, brightness_precision_bits)
904
905struct bdb_lfp_backlight_data {900struct bdb_lfp_backlight_data {
906 u8 entry_size;901 u8 entry_size;
907 struct lfp_backlight_data_entry data[16];902 struct lfp_backlight_data_entry data[16];
drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c+3−3
@@ -8,14 +8,14 @@ · 7 unmodified lines
8#include "intel_gt_ccs_mode.h"8#include "intel_gt_ccs_mode.h"
9#include "intel_gt_regs.h"9#include "intel_gt_regs.h"
10 10
11void intel_gt_apply_ccs_mode(struct intel_gt *gt)11unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt)
12{12{
13 int cslice;13 int cslice;
14 u32 mode = 0;14 u32 mode = 0;
15 int first_ccs = __ffs(CCS_MASK(gt));15 int first_ccs = __ffs(CCS_MASK(gt));
16 16
17 if (!IS_DG2(gt->i915))17 if (!IS_DG2(gt->i915))
18 return;18 return 0;
19 19
20 /* Build the value for the fixed CCS load balancing */20 /* Build the value for the fixed CCS load balancing */
21 for (cslice = 0; cslice < I915_MAX_CCS; cslice++) {21 for (cslice = 0; cslice < I915_MAX_CCS; cslice++) {
@@ -35,5 +35,5 @@ void intel_gt_apply_ccs_mode(struct intel_gt *gt) · 13 unmodified lines
35 XEHP_CCS_MODE_CSLICE_MASK);35 XEHP_CCS_MODE_CSLICE_MASK);
36 }36 }
37 37
38 intel_uncore_write(gt->uncore, XEHP_CCS_MODE, mode);38 return mode;
39}39}
drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h+1−1
@@ -8,6 +8,6 @@ · 7 unmodified lines
8 8
9struct intel_gt;9struct intel_gt;
10 10
11void intel_gt_apply_ccs_mode(struct intel_gt *gt);11unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt);
12 12
13#endif /* __INTEL_GT_CCS_MODE_H__ */13#endif /* __INTEL_GT_CCS_MODE_H__ */
drivers/gpu/drm/i915/gt/intel_workarounds.c+3−1
@@ -2859,6 +2859,7 @@ add_render_compute_tuning_settings(struct intel_gt *gt, · 2858 unmodified lines
2859static void ccs_engine_wa_mode(struct intel_engine_cs *engine, struct i915_wa_list *wal)2859static void ccs_engine_wa_mode(struct intel_engine_cs *engine, struct i915_wa_list *wal)
2860{2860{
2861 struct intel_gt *gt = engine->gt;2861 struct intel_gt *gt = engine->gt;
2862 u32 mode;
2862 2863
2863 if (!IS_DG2(gt->i915))2864 if (!IS_DG2(gt->i915))
2864 return;2865 return;
@@ -2875,7 +2876,8 @@ static void ccs_engine_wa_mode(struct intel_engine_cs *engine, struct i915_wa_li · 10 unmodified lines
2875 * After having disabled automatic load balancing we need to2876 * After having disabled automatic load balancing we need to
2876 * assign all slices to a single CCS. We will call it CCS mode 12877 * assign all slices to a single CCS. We will call it CCS mode 1
2877 */2878 */
2878 intel_gt_apply_ccs_mode(gt);2879 mode = intel_gt_apply_ccs_mode(gt);
2880 wa_masked_en(wal, XEHP_CCS_MODE, mode);
2879}2881}
2880 2882
2881/*2883/*
drivers/gpu/drm/meson/meson_dw_hdmi.c+31−39
@@ -106,6 +106,8 @@ · 105 unmodified lines
106#define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 */106#define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 */
107#define HHI_HDMI_PHY_CNTL0 0x3a0 /* 0xe8 */107#define HHI_HDMI_PHY_CNTL0 0x3a0 /* 0xe8 */
108#define HHI_HDMI_PHY_CNTL1 0x3a4 /* 0xe9 */108#define HHI_HDMI_PHY_CNTL1 0x3a4 /* 0xe9 */
109#define PHY_CNTL1_INIT 0x03900000
110#define PHY_INVERT BIT(17)
109#define HHI_HDMI_PHY_CNTL2 0x3a8 /* 0xea */111#define HHI_HDMI_PHY_CNTL2 0x3a8 /* 0xea */
110#define HHI_HDMI_PHY_CNTL3 0x3ac /* 0xeb */112#define HHI_HDMI_PHY_CNTL3 0x3ac /* 0xeb */
111#define HHI_HDMI_PHY_CNTL4 0x3b0 /* 0xec */113#define HHI_HDMI_PHY_CNTL4 0x3b0 /* 0xec */
@@ -130,6 +132,8 @@ struct meson_dw_hdmi_data { · 18 unmodified lines
130 unsigned int addr);132 unsigned int addr);
131 void (*dwc_write)(struct meson_dw_hdmi *dw_hdmi,133 void (*dwc_write)(struct meson_dw_hdmi *dw_hdmi,
132 unsigned int addr, unsigned int data);134 unsigned int addr, unsigned int data);
135 u32 cntl0_init;
136 u32 cntl1_init;
133};137};
134 138
135struct meson_dw_hdmi {139struct meson_dw_hdmi {
@@ -384,26 +388,6 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, · 248 unmodified lines
384 dw_hdmi_bus_fmt_is_420(hdmi))388 dw_hdmi_bus_fmt_is_420(hdmi))
385 mode_is_420 = true;389 mode_is_420 = true;
386 390
387 /* Enable clocks */
388 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, 0xffff, 0x100);
389
390 /* Bring HDMITX MEM output of power down */
391 regmap_update_bits(priv->hhi, HHI_MEM_PD_REG0, 0xff << 8, 0);
392
393 /* Bring out of reset */
394 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_SW_RESET, 0);
395
396 /* Enable internal pixclk, tmds_clk, spdif_clk, i2s_clk, cecclk */
397 dw_hdmi_top_write_bits(dw_hdmi, HDMITX_TOP_CLK_CNTL,
398 0x3, 0x3);
399
400 /* Enable cec_clk and hdcp22_tmdsclk_en */
401 dw_hdmi_top_write_bits(dw_hdmi, HDMITX_TOP_CLK_CNTL,
402 0x3 << 4, 0x3 << 4);
403
404 /* Enable normal output to PHY */
405 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_BIST_CNTL, BIT(12));
406
407 /* TMDS pattern setup */391 /* TMDS pattern setup */
408 if (mode->clock > 340000 && !mode_is_420) {392 if (mode->clock > 340000 && !mode_is_420) {
409 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01,393 dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01,
@@ -425,20 +409,6 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, · 15 unmodified lines
425 /* Setup PHY parameters */409 /* Setup PHY parameters */
426 meson_hdmi_phy_setup_mode(dw_hdmi, mode, mode_is_420);410 meson_hdmi_phy_setup_mode(dw_hdmi, mode, mode_is_420);
427 411
428 /* Setup PHY */
429 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1,
430 0xffff << 16, 0x0390 << 16);
431
432 /* BIT_INVERT */
433 if (dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxl-dw-hdmi") ||
434 dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxm-dw-hdmi") ||
435 dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-g12a-dw-hdmi"))
436 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1,
437 BIT(17), 0);
438 else
439 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1,
440 BIT(17), BIT(17));
441
442 /* Disable clock, fifo, fifo_wr */412 /* Disable clock, fifo, fifo_wr */
443 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0);413 regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0);
444 414
@@ -492,7 +462,9 @@ static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, · 47 unmodified lines
492 462
493 DRM_DEBUG_DRIVER("\n");463 DRM_DEBUG_DRIVER("\n");
494 464
495 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0);465 /* Fallback to init mode */
466 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL1, dw_hdmi->data->cntl1_init);
467 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, dw_hdmi->data->cntl0_init);
496}468}
497 469
498static enum drm_connector_status dw_hdmi_read_hpd(struct dw_hdmi *hdmi,470static enum drm_connector_status dw_hdmi_read_hpd(struct dw_hdmi *hdmi,
@@ -610,11 +582,22 @@ static const struct regmap_config meson_dw_hdmi_regmap_config = { · 111 unmodified lines
610 .fast_io = true,582 .fast_io = true,
611};583};
612 584
613static const struct meson_dw_hdmi_data meson_dw_hdmi_gx_data = {585static const struct meson_dw_hdmi_data meson_dw_hdmi_gxbb_data = {
614 .top_read = dw_hdmi_top_read,586 .top_read = dw_hdmi_top_read,
615 .top_write = dw_hdmi_top_write,587 .top_write = dw_hdmi_top_write,
616 .dwc_read = dw_hdmi_dwc_read,588 .dwc_read = dw_hdmi_dwc_read,
617 .dwc_write = dw_hdmi_dwc_write,589 .dwc_write = dw_hdmi_dwc_write,
590 .cntl0_init = 0x0,
591 .cntl1_init = PHY_CNTL1_INIT | PHY_INVERT,
592};
593
594static const struct meson_dw_hdmi_data meson_dw_hdmi_gxl_data = {
595 .top_read = dw_hdmi_top_read,
596 .top_write = dw_hdmi_top_write,
597 .dwc_read = dw_hdmi_dwc_read,
598 .dwc_write = dw_hdmi_dwc_write,
599 .cntl0_init = 0x0,
600 .cntl1_init = PHY_CNTL1_INIT,
618};601};
619 602
620static const struct meson_dw_hdmi_data meson_dw_hdmi_g12a_data = {603static const struct meson_dw_hdmi_data meson_dw_hdmi_g12a_data = {
@@ -622,6 +605,8 @@ static const struct meson_dw_hdmi_data meson_dw_hdmi_g12a_data = { · 1 unmodified line
622 .top_write = dw_hdmi_g12a_top_write,605 .top_write = dw_hdmi_g12a_top_write,
623 .dwc_read = dw_hdmi_g12a_dwc_read,606 .dwc_read = dw_hdmi_g12a_dwc_read,
624 .dwc_write = dw_hdmi_g12a_dwc_write,607 .dwc_write = dw_hdmi_g12a_dwc_write,
608 .cntl0_init = 0x000b4242, /* Bandgap */
609 .cntl1_init = PHY_CNTL1_INIT,
625};610};
626 611
627static void meson_dw_hdmi_init(struct meson_dw_hdmi *meson_dw_hdmi)612static void meson_dw_hdmi_init(struct meson_dw_hdmi *meson_dw_hdmi)
@@ -656,6 +641,13 @@ static void meson_dw_hdmi_init(struct meson_dw_hdmi *meson_dw_hdmi) · 28 unmodified lines
656 meson_dw_hdmi->data->top_write(meson_dw_hdmi,641 meson_dw_hdmi->data->top_write(meson_dw_hdmi,
657 HDMITX_TOP_CLK_CNTL, 0xff);642 HDMITX_TOP_CLK_CNTL, 0xff);
658 643
644 /* Enable normal output to PHY */
645 meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_BIST_CNTL, BIT(12));
646
647 /* Setup PHY */
648 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL1, meson_dw_hdmi->data->cntl1_init);
649 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, meson_dw_hdmi->data->cntl0_init);
650
659 /* Enable HDMI-TX Interrupt */651 /* Enable HDMI-TX Interrupt */
660 meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_INTR_STAT_CLR,652 meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_INTR_STAT_CLR,
661 HDMITX_TOP_INTR_CORE);653 HDMITX_TOP_INTR_CORE);
@@ -865,11 +857,11 @@ static const struct dev_pm_ops meson_dw_hdmi_pm_ops = { · 203 unmodified lines
865 857
866static const struct of_device_id meson_dw_hdmi_of_table[] = {858static const struct of_device_id meson_dw_hdmi_of_table[] = {
867 { .compatible = "amlogic,meson-gxbb-dw-hdmi",859 { .compatible = "amlogic,meson-gxbb-dw-hdmi",
868 .data = &meson_dw_hdmi_gx_data },860 .data = &meson_dw_hdmi_gxbb_data },
869 { .compatible = "amlogic,meson-gxl-dw-hdmi",861 { .compatible = "amlogic,meson-gxl-dw-hdmi",
870 .data = &meson_dw_hdmi_gx_data },862 .data = &meson_dw_hdmi_gxl_data },
871 { .compatible = "amlogic,meson-gxm-dw-hdmi",863 { .compatible = "amlogic,meson-gxm-dw-hdmi",
872 .data = &meson_dw_hdmi_gx_data },864 .data = &meson_dw_hdmi_gxl_data },
873 { .compatible = "amlogic,meson-g12a-dw-hdmi",865 { .compatible = "amlogic,meson-g12a-dw-hdmi",
874 .data = &meson_dw_hdmi_g12a_data },866 .data = &meson_dw_hdmi_g12a_data },
875 { }867 { }
drivers/gpu/drm/nouveau/nvkm/core/firmware.c+7−12
@@ -205,9 +205,7 @@ nvkm_firmware_dtor(struct nvkm_firmware *fw) · 204 unmodified lines
205 break;205 break;
206 case NVKM_FIRMWARE_IMG_DMA:206 case NVKM_FIRMWARE_IMG_DMA:
207 nvkm_memory_unref(&memory);207 nvkm_memory_unref(&memory);
208 dma_unmap_single(fw->device->dev, fw->phys, sg_dma_len(&fw->mem.sgl),208 dma_free_coherent(fw->device->dev, sg_dma_len(&fw->mem.sgl), fw->img, fw->phys);
209 DMA_TO_DEVICE);
210 kfree(fw->img);
211 break;209 break;
212 case NVKM_FIRMWARE_IMG_SGT:210 case NVKM_FIRMWARE_IMG_SGT:
213 nvkm_memory_unref(&memory);211 nvkm_memory_unref(&memory);
@@ -237,17 +235,14 @@ nvkm_firmware_ctor(const struct nvkm_firmware_func *func, const char *name, · 23 unmodified lines
237 fw->img = kmemdup(src, fw->len, GFP_KERNEL);235 fw->img = kmemdup(src, fw->len, GFP_KERNEL);
238 break;236 break;
239 case NVKM_FIRMWARE_IMG_DMA: {237 case NVKM_FIRMWARE_IMG_DMA: {
240 len = ALIGN(fw->len, PAGE_SIZE);238 dma_addr_t addr;
241 239
242 fw->img = kmalloc(len, GFP_KERNEL);240 len = ALIGN(fw->len, PAGE_SIZE);
243 if (!fw->img)
244 return -ENOMEM;
245 241
246 memcpy(fw->img, src, fw->len);242 fw->img = dma_alloc_coherent(fw->device->dev, len, &addr, GFP_KERNEL);
247 fw->phys = dma_map_single(fw->device->dev, fw->img, len, DMA_TO_DEVICE);243 if (fw->img) {
248 if (dma_mapping_error(fw->device->dev, fw->phys)) {244 memcpy(fw->img, src, fw->len);
249 kfree(fw->img);245 fw->phys = addr;
250 return -EFAULT;
251 }246 }
252 247
253 sg_init_one(&fw->mem.sgl, fw->img, len);248 sg_init_one(&fw->mem.sgl, fw->img, len);
drivers/gpu/drm/xe/xe_guc_ads.c+1−1
@@ -100,7 +100,7 @@ struct __guc_ads_blob { · 99 unmodified lines
100 struct guc_engine_usage engine_usage;100 struct guc_engine_usage engine_usage;
101 struct guc_um_init_params um_init_params;101 struct guc_um_init_params um_init_params;
102 /* From here on, location is dynamic! Refer to above diagram. */102 /* From here on, location is dynamic! Refer to above diagram. */
103 struct guc_mmio_reg regset[0];103 struct guc_mmio_reg regset[];
104} __packed;104} __packed;
105 105
106#define ads_blob_read(ads_, field_) \106#define ads_blob_read(ads_, field_) \
drivers/gpu/drm/xe/xe_guc_ct.c+9−1
@@ -120,6 +120,7 @@ static void guc_ct_fini(struct drm_device *drm, void *arg) · 119 unmodified lines
120{120{
121 struct xe_guc_ct *ct = arg;121 struct xe_guc_ct *ct = arg;
122 122
123 destroy_workqueue(ct->g2h_wq);
123 xa_destroy(&ct->fence_lookup);124 xa_destroy(&ct->fence_lookup);
124}125}
125 126
@@ -145,13 +146,20 @@ int xe_guc_ct_init(struct xe_guc_ct *ct) · 19 unmodified lines
145 146
146 xe_assert(xe, !(guc_ct_size() % PAGE_SIZE));147 xe_assert(xe, !(guc_ct_size() % PAGE_SIZE));
147 148
148 drmm_mutex_init(&xe->drm, &ct->lock);149 ct->g2h_wq = alloc_ordered_workqueue("xe-g2h-wq", 0);
150 if (!ct->g2h_wq)
151 return -ENOMEM;
152
149 spin_lock_init(&ct->fast_lock);153 spin_lock_init(&ct->fast_lock);
150 xa_init(&ct->fence_lookup);154 xa_init(&ct->fence_lookup);
151 INIT_WORK(&ct->g2h_worker, g2h_worker_func);155 INIT_WORK(&ct->g2h_worker, g2h_worker_func);
152 init_waitqueue_head(&ct->wq);156 init_waitqueue_head(&ct->wq);
153 init_waitqueue_head(&ct->g2h_fence_wq);157 init_waitqueue_head(&ct->g2h_fence_wq);
154 158
159 err = drmm_mutex_init(&xe->drm, &ct->lock);
160 if (err)
161 return err;
162
155 primelockdep(ct);163 primelockdep(ct);
156 164
157 bo = xe_managed_bo_create_pin_map(xe, tile, guc_ct_size(),165 bo = xe_managed_bo_create_pin_map(xe, tile, guc_ct_size(),
drivers/gpu/drm/xe/xe_guc_ct.h+1−1
@@ -34,7 +34,7 @@ static inline void xe_guc_ct_irq_handler(struct xe_guc_ct *ct) · 33 unmodified lines
34 return;34 return;
35 35
36 wake_up_all(&ct->wq);36 wake_up_all(&ct->wq);
37 queue_work(system_unbound_wq, &ct->g2h_worker);37 queue_work(ct->g2h_wq, &ct->g2h_worker);
38 xe_guc_ct_fast_path(ct);38 xe_guc_ct_fast_path(ct);
39}39}
40 40
drivers/gpu/drm/xe/xe_guc_ct_types.h+2−0
@@ -120,6 +120,8 @@ struct xe_guc_ct { · 119 unmodified lines
120 wait_queue_head_t wq;120 wait_queue_head_t wq;
121 /** @g2h_fence_wq: wait queue used for G2H fencing */121 /** @g2h_fence_wq: wait queue used for G2H fencing */
122 wait_queue_head_t g2h_fence_wq;122 wait_queue_head_t g2h_fence_wq;
123 /** @g2h_wq: used to process G2H */
124 struct workqueue_struct *g2h_wq;
123 /** @msg: Message buffer */125 /** @msg: Message buffer */
124 u32 msg[GUC_CTB_MSG_MAX_LEN];126 u32 msg[GUC_CTB_MSG_MAX_LEN];
125 /** @fast_msg: Message buffer */127 /** @fast_msg: Message buffer */