Add register definitions used in several Exar PCI/PCIe UARTs
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| @@ -368,10 +368,22 @@ · 367 unmodified lines | |||
| 368 | #define UART_OMAP_MDR1_DISABLE 0x07 /* Disable (default state) */ | 368 | #define UART_OMAP_MDR1_DISABLE 0x07 /* Disable (default state) */ |
| 369 | 369 | ||
| 370 | /* | 370 | /* |
| 371 | * These are definitions for the XR17V35X and XR17D15X | 371 | * These are definitions for the Exar XR17V35X and XR17(C|D)15X |
| 372 | */ | 372 | */ |
| 373 | #define UART_EXAR_8XMODE 0x88 /* 8X sampling rate select */ | ||
| 373 | #define UART_EXAR_SLEEP 0x8b /* Sleep mode */ | 374 | #define UART_EXAR_SLEEP 0x8b /* Sleep mode */ |
| 374 | #define UART_EXAR_DVID 0x8d /* Device identification */ | 375 | #define UART_EXAR_DVID 0x8d /* Device identification */ |
| 375 | 376 | ||
| 377 | #define UART_EXAR_FCTR 0x08 /* Feature Control Register */ | ||
| 378 | #define UART_FCTR_EXAR_IRDA 0x08 /* IrDa data encode select */ | ||
| 379 | #define UART_FCTR_EXAR_485 0x10 /* Auto 485 half duplex dir ctl */ | ||
| 380 | #define UART_FCTR_EXAR_TRGA 0x00 /* FIFO trigger table A */ | ||
| 381 | #define UART_FCTR_EXAR_TRGB 0x60 /* FIFO trigger table B */ | ||
| 382 | #define UART_FCTR_EXAR_TRGC 0x80 /* FIFO trigger table C */ | ||
| 383 | #define UART_FCTR_EXAR_TRGD 0xc0 /* FIFO trigger table D programmable */ | ||
| 384 | |||
| 385 | #define UART_EXAR_TXTRG 0x0a /* Tx FIFO trigger level write-only */ | ||
| 386 | #define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */ | ||
| 387 | |||
| 376 | #endif /* _LINUX_SERIAL_REG_H */ | 388 | #endif /* _LINUX_SERIAL_REG_H */ |
| 377 | 389 | ||