Pull ARM SoC fixes from Arnd Bergmann: "Most of the changes this time are for incorrect device nodes in various ways, on on imx, berlin, exynos, ux500, uniphier, omap and meson. Chen-Yu Tsai now co-maintains mach-sunxi (Allwinner). Other bug fixes include - a partial revert of a broken tegra gpio patch - irq affinity for arm ccn - suspend on one Armada 385 machine - enable ZONE_DMA to avoid an OMAP crash for over 2GB RAM - turning on a regulator on beagleboard-x15 for HDMI - making the omap gpmc debug code visible - setup of orion network switch - a rare build regression for pxa" * tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (22 commits) ARM: OMAP2+: Fix imprecise external abort caused by bogus SRAM init thermal: exynos: Fix register read in TMU ARM: OMAP2+: Fix oops with LPAE and more than 2GB of memory ARM: tegra: Comment out gpio-ranges properties ARM: dts: uniphier: fix IRQ number for devices on PH1-LD6b ref board drivers/perf: arm_pmu: avoid CPU device_node reference leak bus: arm-ccn: Fix irq affinity setting on CPU migration bus: arm-ccn: Handle correctly no-more-cpus case ARM: mvebu: correct a385-db-ap compatible string ARM: meson6: DTS: Fix wrong reg mapping and IRQ numbers MAINTAINERS: Update Allwinner entry and add new maintainer ARM: ux500: modify initial levelshifter status ARM: pxa: fix pxa3xx DFI lockup hack Documentation: ARM: List new omap MMC requirements memory: omap-gpmc: dump "before" state before first modification memory: omap-gpmc: Fix unselectable debug option for GPMC ARM: dts: am57xx-beagle-x15: set VDD_SD to always-on ARM: dts: Fix audio card detection on Peach boards ARM: EXYNOS: Fix double of_node_put() when parsing child power domains ARM: orion: Fix DSA platform device after mvmdio conversion ...
Unified · Split
| @@ -0,0 +1,7 @@ | ||
| 1 | +This file contains documentation for running mainline | |
| 2 | +kernel on omaps. | |
| 3 | + | |
| 4 | +KERNEL NEW DEPENDENCIES | |
| 5 | +v4.3+ Update is needed for custom .config files to make sure | |
| 6 | + CONFIG_REGULATOR_PBIAS is enabled for MMC1 to work | |
| 7 | + properly. | |
| @@ -894,11 +894,12 @@ M: Lennert Buytenhek <kernel@wantstofly.org> · 893 unmodified lines | ||
| 894 | 894 | L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) |
| 895 | 895 | S: Maintained |
| 896 | 896 | |
| 897 | −ARM/Allwinner A1X SoC support | |
| 897 | +ARM/Allwinner sunXi SoC support | |
| 898 | 898 | M: Maxime Ripard <maxime.ripard@free-electrons.com> |
| 899 | +M: Chen-Yu Tsai <wens@csie.org> | |
| 899 | 900 | L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) |
| 900 | 901 | S: Maintained |
| 901 | −N: sun[x4567]i | |
| 902 | +N: sun[x456789]i | |
| 902 | 903 | |
| 903 | 904 | ARM/Allwinner SoC Clock Support |
| 904 | 905 | M: Emilio López <emilio@elopez.com.ar> |
| @@ -402,11 +402,12 @@ · 401 unmodified lines | ||
| 402 | 402 | /* SMPS9 unused */ |
| 403 | 403 | |
| 404 | 404 | ldo1_reg: ldo1 { |
| 405 | − /* VDD_SD */ | |
| 405 | + /* VDD_SD / VDDSHV8 */ | |
| 406 | 406 | regulator-name = "ldo1"; |
| 407 | 407 | regulator-min-microvolt = <1800000>; |
| 408 | 408 | regulator-max-microvolt = <3300000>; |
| 409 | 409 | regulator-boot-on; |
| 410 | + regulator-always-on; | |
| 410 | 411 | }; |
| 411 | 412 | |
| 412 | 413 | ldo2_reg: ldo2 { |
| @@ -46,7 +46,7 @@ · 45 unmodified lines | ||
| 46 | 46 | |
| 47 | 47 | / { |
| 48 | 48 | model = "Marvell Armada 385 Access Point Development Board"; |
| 49 | − compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada38x"; | |
| 49 | + compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada380"; | |
| 50 | 50 | |
| 51 | 51 | chosen { |
| 52 | 52 | stdout-path = "serial1:115200n8"; |
| @@ -152,7 +152,7 @@ · 151 unmodified lines | ||
| 152 | 152 | }; |
| 153 | 153 | |
| 154 | 154 | usb_phy2: phy@a2f400 { |
| 155 | − compatible = "marvell,berlin2-usb-phy"; | |
| 155 | + compatible = "marvell,berlin2cd-usb-phy"; | |
| 156 | 156 | reg = <0xa2f400 0x128>; |
| 157 | 157 | #phy-cells = <0>; |
| 158 | 158 | resets = <&chip_rst 0x104 14>; |
| @@ -170,7 +170,7 @@ · 11 unmodified lines | ||
| 170 | 170 | }; |
| 171 | 171 | |
| 172 | 172 | usb_phy0: phy@b74000 { |
| 173 | − compatible = "marvell,berlin2-usb-phy"; | |
| 173 | + compatible = "marvell,berlin2cd-usb-phy"; | |
| 174 | 174 | reg = <0xb74000 0x128>; |
| 175 | 175 | #phy-cells = <0>; |
| 176 | 176 | resets = <&chip_rst 0x104 12>; |
| @@ -178,7 +178,7 @@ · 1 unmodified line | ||
| 178 | 178 | }; |
| 179 | 179 | |
| 180 | 180 | usb_phy1: phy@b78000 { |
| 181 | − compatible = "marvell,berlin2-usb-phy"; | |
| 181 | + compatible = "marvell,berlin2cd-usb-phy"; | |
| 182 | 182 | reg = <0xb78000 0x128>; |
| 183 | 183 | #phy-cells = <0>; |
| 184 | 184 | resets = <&chip_rst 0x104 13>; |
| @@ -915,6 +915,11 @@ · 914 unmodified lines | ||
| 915 | 915 | }; |
| 916 | 916 | }; |
| 917 | 917 | |
| 918 | +&pmu_system_controller { | |
| 919 | + assigned-clocks = <&pmu_system_controller 0>; | |
| 920 | + assigned-clock-parents = <&clock CLK_FIN_PLL>; | |
| 921 | +}; | |
| 922 | + | |
| 918 | 923 | &rtc { |
| 919 | 924 | status = "okay"; |
| 920 | 925 | clocks = <&clock CLK_RTC>, <&max77802 MAX77802_CLK_32K_AP>; |
| @@ -878,6 +878,11 @@ · 877 unmodified lines | ||
| 878 | 878 | }; |
| 879 | 879 | }; |
| 880 | 880 | |
| 881 | +&pmu_system_controller { | |
| 882 | + assigned-clocks = <&pmu_system_controller 0>; | |
| 883 | + assigned-clock-parents = <&clock CLK_FIN_PLL>; | |
| 884 | +}; | |
| 885 | + | |
| 881 | 886 | &rtc { |
| 882 | 887 | status = "okay"; |
| 883 | 888 | clocks = <&clock CLK_RTC>, <&max77802 MAX77802_CLK_32K_AP>; |
| @@ -588,10 +588,10 @@ · 587 unmodified lines | ||
| 588 | 588 | status = "disabled"; |
| 589 | 589 | }; |
| 590 | 590 | |
| 591 | − uart2: serial@30870000 { | |
| 591 | + uart2: serial@30890000 { | |
| 592 | 592 | compatible = "fsl,imx7d-uart", |
| 593 | 593 | "fsl,imx6q-uart"; |
| 594 | − reg = <0x30870000 0x10000>; | |
| 594 | + reg = <0x30890000 0x10000>; | |
| 595 | 595 | interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; |
| 596 | 596 | clocks = <&clks IMX7D_UART2_ROOT_CLK>, |
| 597 | 597 | <&clks IMX7D_UART2_ROOT_CLK>; |
| @@ -12,7 +12,7 @@ · 11 unmodified lines | ||
| 12 | 12 | |
| 13 | 13 | / { |
| 14 | 14 | model = "LogicPD Zoom DM3730 Torpedo Development Kit"; |
| 15 | − compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap36xx"; | |
| 15 | + compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap3630", "ti,omap3"; | |
| 16 | 16 | |
| 17 | 17 | gpio_keys { |
| 18 | 18 | compatible = "gpio-keys"; |
| @@ -67,7 +67,7 @@ · 66 unmodified lines | ||
| 67 | 67 | |
| 68 | 68 | timer@c1109940 { |
| 69 | 69 | compatible = "amlogic,meson6-timer"; |
| 70 | − reg = <0xc1109940 0x14>; | |
| 70 | + reg = <0xc1109940 0x18>; | |
| 71 | 71 | interrupts = <0 10 1>; |
| 72 | 72 | }; |
| 73 | 73 | |
| @@ -80,36 +80,37 @@ · 6 unmodified lines | ||
| 80 | 80 | wdt: watchdog@c1109900 { |
| 81 | 81 | compatible = "amlogic,meson6-wdt"; |
| 82 | 82 | reg = <0xc1109900 0x8>; |
| 83 | + interrupts = <0 0 1>; | |
| 83 | 84 | }; |
| 84 | 85 | |
| 85 | 86 | uart_AO: serial@c81004c0 { |
| 86 | 87 | compatible = "amlogic,meson-uart"; |
| 87 | − reg = <0xc81004c0 0x14>; | |
| 88 | + reg = <0xc81004c0 0x18>; | |
| 88 | 89 | interrupts = <0 90 1>; |
| 89 | 90 | clocks = <&clk81>; |
| 90 | 91 | status = "disabled"; |
| 91 | 92 | }; |
| 92 | 93 | |
| 93 | − uart_A: serial@c81084c0 { | |
| 94 | + uart_A: serial@c11084c0 { | |
| 94 | 95 | compatible = "amlogic,meson-uart"; |
| 95 | − reg = <0xc81084c0 0x14>; | |
| 96 | − interrupts = <0 90 1>; | |
| 96 | + reg = <0xc11084c0 0x18>; | |
| 97 | + interrupts = <0 26 1>; | |
| 97 | 98 | clocks = <&clk81>; |
| 98 | 99 | status = "disabled"; |
| 99 | 100 | }; |
| 100 | 101 | |
| 101 | − uart_B: serial@c81084dc { | |
| 102 | + uart_B: serial@c11084dc { | |
| 102 | 103 | compatible = "amlogic,meson-uart"; |
| 103 | − reg = <0xc81084dc 0x14>; | |
| 104 | − interrupts = <0 90 1>; | |
| 104 | + reg = <0xc11084dc 0x18>; | |
| 105 | + interrupts = <0 75 1>; | |
| 105 | 106 | clocks = <&clk81>; |
| 106 | 107 | status = "disabled"; |
| 107 | 108 | }; |
| 108 | 109 | |
| 109 | − uart_C: serial@c8108700 { | |
| 110 | + uart_C: serial@c1108700 { | |
| 110 | 111 | compatible = "amlogic,meson-uart"; |
| 111 | − reg = <0xc8108700 0x14>; | |
| 112 | − interrupts = <0 90 1>; | |
| 112 | + reg = <0xc1108700 0x18>; | |
| 113 | + interrupts = <0 93 1>; | |
| 113 | 114 | clocks = <&clk81>; |
| 114 | 115 | status = "disabled"; |
| 115 | 116 | }; |
| @@ -13,7 +13,7 @@ · 12 unmodified lines | ||
| 13 | 13 | |
| 14 | 14 | / { |
| 15 | 15 | model = "TI OMAP37XX EVM (TMDSEVM3730)"; |
| 16 | − compatible = "ti,omap3-evm-37xx", "ti,omap36xx"; | |
| 16 | + compatible = "ti,omap3-evm-37xx", "ti,omap3630", "ti,omap3"; | |
| 17 | 17 | |
| 18 | 18 | memory { |
| 19 | 19 | device_type = "memory"; |
| @@ -56,7 +56,7 @@ · 55 unmodified lines | ||
| 56 | 56 | /* VMMCI level-shifter enable */ |
| 57 | 57 | default_hrefv60_cfg2 { |
| 58 | 58 | pins = "GPIO169_D22"; |
| 59 | − ste,config = <&gpio_out_lo>; | |
| 59 | + ste,config = <&gpio_out_hi>; | |
| 60 | 60 | }; |
| 61 | 61 | /* VMMCI level-shifter voltage select */ |
| 62 | 62 | default_hrefv60_cfg3 { |
| @@ -234,7 +234,9 @@ · 233 unmodified lines | ||
| 234 | 234 | gpio-controller; |
| 235 | 235 | #interrupt-cells = <2>; |
| 236 | 236 | interrupt-controller; |
| 237 | + /* | |
| 237 | 238 | gpio-ranges = <&pinmux 0 0 246>; |
| 239 | + */ | |
| 238 | 240 | }; |
| 239 | 241 | |
| 240 | 242 | apbmisc@70000800 { |
| @@ -258,7 +258,9 @@ · 257 unmodified lines | ||
| 258 | 258 | gpio-controller; |
| 259 | 259 | #interrupt-cells = <2>; |
| 260 | 260 | interrupt-controller; |
| 261 | + /* | |
| 261 | 262 | gpio-ranges = <&pinmux 0 0 251>; |
| 263 | + */ | |
| 262 | 264 | }; |
| 263 | 265 | |
| 264 | 266 | apbdma: dma@0,60020000 { |
| @@ -244,7 +244,9 @@ · 243 unmodified lines | ||
| 244 | 244 | gpio-controller; |
| 245 | 245 | #interrupt-cells = <2>; |
| 246 | 246 | interrupt-controller; |
| 247 | + /* | |
| 247 | 248 | gpio-ranges = <&pinmux 0 0 224>; |
| 249 | + */ | |
| 248 | 250 | }; |
| 249 | 251 | |
| 250 | 252 | apbmisc@70000800 { |
| @@ -349,7 +349,9 @@ · 348 unmodified lines | ||
| 349 | 349 | gpio-controller; |
| 350 | 350 | #interrupt-cells = <2>; |
| 351 | 351 | interrupt-controller; |
| 352 | + /* | |
| 352 | 353 | gpio-ranges = <&pinmux 0 0 248>; |
| 354 | + */ | |
| 353 | 355 | }; |
| 354 | 356 | |
| 355 | 357 | apbmisc@70000800 { |
| @@ -85,7 +85,7 @@ · 84 unmodified lines | ||
| 85 | 85 | }; |
| 86 | 86 | |
| 87 | 87 | ðsc { |
| 88 | − interrupts = <0 50 4>; | |
| 88 | + interrupts = <0 52 4>; | |
| 89 | 89 | }; |
| 90 | 90 | |
| 91 | 91 | &serial0 { |
| @@ -200,15 +200,15 @@ no_clk: · 199 unmodified lines | ||
| 200 | 200 | args.args_count = 0; |
| 201 | 201 | child_domain = of_genpd_get_from_provider(&args); |
| 202 | 202 | if (IS_ERR(child_domain)) |
| 203 | − goto next_pd; | |
| 203 | + continue; | |
| 204 | 204 | |
| 205 | 205 | if (of_parse_phandle_with_args(np, "power-domains", |
| 206 | 206 | "#power-domain-cells", 0, &args) != 0) |
| 207 | − goto next_pd; | |
| 207 | + continue; | |
| 208 | 208 | |
| 209 | 209 | parent_domain = of_genpd_get_from_provider(&args); |
| 210 | 210 | if (IS_ERR(parent_domain)) |
| 211 | − goto next_pd; | |
| 211 | + continue; | |
| 212 | 212 | |
| 213 | 213 | if (pm_genpd_add_subdomain(parent_domain, child_domain)) |
| 214 | 214 | pr_warn("%s failed to add subdomain: %s\n", |
| @@ -216,8 +216,6 @@ no_clk: · 1 unmodified line | ||
| 216 | 216 | else |
| 217 | 217 | pr_info("%s has as child subdomain: %s.\n", |
| 218 | 218 | parent_domain->name, child_domain->name); |
| 219 | −next_pd: | |
| 220 | − of_node_put(np); | |
| 221 | 219 | } |
| 222 | 220 | |
| 223 | 221 | return 0; |
| @@ -49,6 +49,7 @@ config SOC_OMAP5 · 48 unmodified lines | ||
| 49 | 49 | select OMAP_INTERCONNECT |
| 50 | 50 | select OMAP_INTERCONNECT_BARRIER |
| 51 | 51 | select PM_OPP if PM |
| 52 | + select ZONE_DMA if ARM_LPAE | |
| 52 | 53 | |
| 53 | 54 | config SOC_AM33XX |
| 54 | 55 | bool "TI AM33XX" |
| @@ -78,6 +79,7 @@ config SOC_DRA7XX · 23 unmodified lines | ||
| 78 | 79 | select OMAP_INTERCONNECT |
| 79 | 80 | select OMAP_INTERCONNECT_BARRIER |
| 80 | 81 | select PM_OPP if PM |
| 82 | + select ZONE_DMA if ARM_LPAE | |
| 81 | 83 | |
| 82 | 84 | config ARCH_OMAP2PLUS |
| 83 | 85 | bool |
| @@ -106,6 +106,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)") · 105 unmodified lines | ||
| 106 | 106 | MACHINE_END |
| 107 | 107 | |
| 108 | 108 | static const char *const omap36xx_boards_compat[] __initconst = { |
| 109 | + "ti,omap3630", | |
| 109 | 110 | "ti,omap36xx", |
| 110 | 111 | NULL, |
| 111 | 112 | }; |
| @@ -243,6 +244,9 @@ static const char *const omap5_boards_compat[] __initconst = { · 131 unmodified lines | ||
| 243 | 244 | }; |
| 244 | 245 | |
| 245 | 246 | DT_MACHINE_START(OMAP5_DT, "Generic OMAP5 (Flattened Device Tree)") |
| 247 | +#if defined(CONFIG_ZONE_DMA) && defined(CONFIG_ARM_LPAE) | |
| 248 | + .dma_zone_size = SZ_2G, | |
| 249 | +#endif | |
| 246 | 250 | .reserve = omap_reserve, |
| 247 | 251 | .smp = smp_ops(omap4_smp_ops), |
| 248 | 252 | .map_io = omap5_map_io, |
| @@ -288,6 +292,9 @@ static const char *const dra74x_boards_compat[] __initconst = { · 39 unmodified lines | ||
| 288 | 292 | }; |
| 289 | 293 | |
| 290 | 294 | DT_MACHINE_START(DRA74X_DT, "Generic DRA74X (Flattened Device Tree)") |
| 295 | +#if defined(CONFIG_ZONE_DMA) && defined(CONFIG_ARM_LPAE) | |
| 296 | + .dma_zone_size = SZ_2G, | |
| 297 | +#endif | |
| 291 | 298 | .reserve = omap_reserve, |
| 292 | 299 | .smp = smp_ops(omap4_smp_ops), |
| 293 | 300 | .map_io = dra7xx_map_io, |
| @@ -308,6 +315,9 @@ static const char *const dra72x_boards_compat[] __initconst = { · 14 unmodified lines | ||
| 308 | 315 | }; |
| 309 | 316 | |
| 310 | 317 | DT_MACHINE_START(DRA72X_DT, "Generic DRA72X (Flattened Device Tree)") |
| 318 | +#if defined(CONFIG_ZONE_DMA) && defined(CONFIG_ARM_LPAE) | |
| 319 | + .dma_zone_size = SZ_2G, | |
| 320 | +#endif | |
| 311 | 321 | .reserve = omap_reserve, |
| 312 | 322 | .map_io = dra7xx_map_io, |
| 313 | 323 | .init_early = dra7xx_init_early, |
| @@ -559,7 +559,14 @@ static void pdata_quirks_check(struct pdata_init *quirks) · 558 unmodified lines | ||
| 559 | 559 | |
| 560 | 560 | void __init pdata_quirks_init(const struct of_device_id *omap_dt_match_table) |
| 561 | 561 | { |
| 562 | − omap_sdrc_init(NULL, NULL); | |
| 562 | + /* | |
| 563 | + * We still need this for omap2420 and omap3 PM to work, others are | |
| 564 | + * using drivers/misc/sram.c already. | |
| 565 | + */ | |
| 566 | + if (of_machine_is_compatible("ti,omap2420") || | |
| 567 | + of_machine_is_compatible("ti,omap3")) | |
| 568 | + omap_sdrc_init(NULL, NULL); | |
| 569 | + | |
| 563 | 570 | pdata_quirks_check(auxdata_quirks); |
| 564 | 571 | of_platform_populate(NULL, omap_dt_match_table, |
| 565 | 572 | omap_auxdata_lookup, NULL); |
| @@ -42,10 +42,6 @@ · 41 unmodified lines | ||
| 42 | 42 | #define PECR_IS(n) ((1 << ((n) * 2)) << 29) |
| 43 | 43 | |
| 44 | 44 | extern void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int)); |
| 45 | −#ifdef CONFIG_PM | |
| 46 | − | |
| 47 | −#define ISRAM_START 0x5c000000 | |
| 48 | −#define ISRAM_SIZE SZ_256K | |
| 49 | 45 | |
| 50 | 46 | /* |
| 51 | 47 | * NAND NFC: DFI bus arbitration subset |
| @@ -54,6 +50,11 @@ extern void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int)); · 2 unmodified lines | ||
| 54 | 50 | #define NDCR_ND_ARB_EN (1 << 12) |
| 55 | 51 | #define NDCR_ND_ARB_CNTL (1 << 19) |
| 56 | 52 | |
| 53 | +#ifdef CONFIG_PM | |
| 54 | + | |
| 55 | +#define ISRAM_START 0x5c000000 | |
| 56 | +#define ISRAM_SIZE SZ_256K | |
| 57 | + | |
| 57 | 58 | static void __iomem *sram; |
| 58 | 59 | static unsigned long wakeup_src; |
| 59 | 60 | |
| @@ -495,7 +495,7 @@ void __init orion_ge00_switch_init(struct dsa_platform_data *d, int irq) · 494 unmodified lines | ||
| 495 | 495 | |
| 496 | 496 | d->netdev = &orion_ge00.dev; |
| 497 | 497 | for (i = 0; i < d->nr_chips; i++) |
| 498 | − d->chip[i].host_dev = &orion_ge00_shared.dev; | |
| 498 | + d->chip[i].host_dev = &orion_ge_mvmdio.dev; | |
| 499 | 499 | orion_switch_device.dev.platform_data = d; |
| 500 | 500 | |
| 501 | 501 | platform_device_register(&orion_switch_device); |
| @@ -1184,11 +1184,12 @@ static int arm_ccn_pmu_cpu_notifier(struct notifier_block *nb, · 1183 unmodified lines | ||
| 1184 | 1184 | if (!cpumask_test_and_clear_cpu(cpu, &dt->cpu)) |
| 1185 | 1185 | break; |
| 1186 | 1186 | target = cpumask_any_but(cpu_online_mask, cpu); |
| 1187 | − if (target < 0) | |
| 1187 | + if (target >= nr_cpu_ids) | |
| 1188 | 1188 | break; |
| 1189 | 1189 | perf_pmu_migrate_context(&dt->pmu, cpu, target); |
| 1190 | 1190 | cpumask_set_cpu(target, &dt->cpu); |
| 1191 | − WARN_ON(irq_set_affinity(ccn->irq, &dt->cpu) != 0); | |
| 1191 | + if (ccn->irq) | |
| 1192 | + WARN_ON(irq_set_affinity(ccn->irq, &dt->cpu) != 0); | |
| 1192 | 1193 | default: |
| 1193 | 1194 | break; |
| 1194 | 1195 | } |
| @@ -58,12 +58,18 @@ config OMAP_GPMC · 57 unmodified lines | ||
| 58 | 58 | memory drives like NOR, NAND, OneNAND, SRAM. |
| 59 | 59 | |
| 60 | 60 | config OMAP_GPMC_DEBUG |
| 61 | − bool | |
| 61 | + bool "Enable GPMC debug output and skip reset of GPMC during init" | |
| 62 | 62 | depends on OMAP_GPMC |
| 63 | 63 | help |
| 64 | 64 | Enables verbose debugging mostly to decode the bootloader provided |
| 65 | − timings. Enable this during development to configure devices | |
| 66 | − connected to the GPMC bus. | |
| 65 | + timings. To preserve the bootloader provided timings, the reset | |
| 66 | + of GPMC is skipped during init. Enable this during development to | |
| 67 | + configure devices connected to the GPMC bus. | |
| 68 | + | |
| 69 | + NOTE: In addition to matching the register setup with the bootloader | |
| 70 | + you also need to match the GPMC FCLK frequency used by the | |
| 71 | + bootloader or else the GPMC timings won't be identical with the | |
| 72 | + bootloader timings. | |
| 67 | 73 | |
| 68 | 74 | config MVEBU_DEVBUS |
| 69 | 75 | bool "Marvell EBU Device Bus Controller" |
| @@ -696,7 +696,6 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t, · 695 unmodified lines | ||
| 696 | 696 | int div; |
| 697 | 697 | u32 l; |
| 698 | 698 | |
| 699 | − gpmc_cs_show_timings(cs, "before gpmc_cs_set_timings"); | |
| 700 | 699 | div = gpmc_calc_divider(t->sync_clk); |
| 701 | 700 | if (div < 0) |
| 702 | 701 | return div; |
| @@ -1988,6 +1987,7 @@ static int gpmc_probe_generic_child(struct platform_device *pdev, · 1285 unmodified lines | ||
| 1988 | 1987 | if (ret < 0) |
| 1989 | 1988 | goto err; |
| 1990 | 1989 | |
| 1990 | + gpmc_cs_show_timings(cs, "before gpmc_cs_program_settings"); | |
| 1991 | 1991 | ret = gpmc_cs_program_settings(cs, &gpmc_s); |
| 1992 | 1992 | if (ret < 0) |
| 1993 | 1993 | goto err; |
| @@ -823,9 +823,15 @@ static int of_pmu_irq_cfg(struct arm_pmu *pmu) · 822 unmodified lines | ||
| 823 | 823 | } |
| 824 | 824 | |
| 825 | 825 | /* Now look up the logical CPU number */ |
| 826 | − for_each_possible_cpu(cpu) | |
| 827 | − if (dn == of_cpu_device_node_get(cpu)) | |
| 826 | + for_each_possible_cpu(cpu) { | |
| 827 | + struct device_node *cpu_dn; | |
| 828 | + | |
| 829 | + cpu_dn = of_cpu_device_node_get(cpu); | |
| 830 | + of_node_put(cpu_dn); | |
| 831 | + | |
| 832 | + if (dn == cpu_dn) | |
| 828 | 833 | break; |
| 834 | + } | |
| 829 | 835 | |
| 830 | 836 | if (cpu >= nr_cpu_ids) { |
| 831 | 837 | pr_warn("Failed to find logical CPU for %s\n", |
| @@ -932,7 +932,7 @@ static void exynos4412_tmu_set_emulation(struct exynos_tmu_data *data, · 931 unmodified lines | ||
| 932 | 932 | |
| 933 | 933 | if (data->soc == SOC_ARCH_EXYNOS5260) |
| 934 | 934 | emul_con = EXYNOS5260_EMUL_CON; |
| 935 | − if (data->soc == SOC_ARCH_EXYNOS5433) | |
| 935 | + else if (data->soc == SOC_ARCH_EXYNOS5433) | |
| 936 | 936 | emul_con = EXYNOS5433_TMU_EMUL_CON; |
| 937 | 937 | else if (data->soc == SOC_ARCH_EXYNOS7) |
| 938 | 938 | emul_con = EXYNOS7_TMU_REG_EMUL_CON; |