History

Merge tag 'v5.9-rc4' into patchwork

Linux 5.9-rc4 * tag 'v5.9-rc4': (1001 commits) Linux 5.9-rc4 io_uring: fix linked deferred ->files cancellation io_uring: fix cancel of deferred reqs with ->files include/linux/log2.h: add missing () around n in roundup_pow_of_two() mm/khugepaged.c: fix khugepaged's request size in collapse_file mm/hugetlb: fix a race between hugetlb sysctl handlers mm/hugetlb: try preferred node first when alloc gigantic page from cma mm/migrate: preserve soft dirty in remove_migration_pte() mm/migrate: remove unnecessary is_zone_device_page() check mm/rmap: fixup copying of soft dirty and uffd ptes mm/migrate: fixup setting UFFD_WP flag mm: madvise: fix vma user-after-free checkpatch: fix the usage of capture group ( ... ) fork: adjust sysctl_max_threads definition to match prototype ipc: adjust proc_ipc_sem_dointvec definition to match prototype mm: track page table modifications in __apply_to_page_range() MAINTAINERS: IA64: mark Status as Odd Fixes only MAINTAINERS: add LLVM maintainers MAINTAINERS: update Cavium/Marvell entries mm: slub: fix conversion of freelist_corrupted() ...

Mauro Carvalho Chehab committed 6 years ago

Commit d13ee582 parents 72a9ff3 f4d51df2050 files · +13420 −8275Browse files

Unified · Split

2050 files
  1. .clang-format +12 −0
  2. .mailmap +61 −57
  3. Documentation/ABI/testing/sysfs-bus-event_source-devices-hv_24x7 +1 −1
  4. Documentation/RCU/lockdep.rst +1 −1
  5. Documentation/admin-guide/devices.txt +1 −1
  6. Documentation/admin-guide/ext4.rst +13 −10
  7. Documentation/admin-guide/kernel-parameters.txt +1 −4
  8. Documentation/admin-guide/laptops/thinkpad-acpi.rst +1 −1
  9. Documentation/admin-guide/pm/intel_pstate.rst +5 −3
  10. Documentation/bpf/index.rst +7 −0
  11. Documentation/devicetree/bindings/clock/imx23-clock.yaml +1 −1
  12. Documentation/devicetree/bindings/clock/imx28-clock.yaml +1 −1
  13. Documentation/devicetree/bindings/gpio/gpio-mxs.yaml +1 −1
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  15. Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.txt +0 −66
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  17. Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.txt +0 −82
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  39. Documentation/driver-api/iio/core.rst +8 −8
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  120. arch/arm64/kvm/arm.c +4 −0
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  122. arch/arm64/kvm/hyp/entry.S +9 −6
  123. arch/arm64/kvm/hyp/hyp-entry.S +41 −24
  124. arch/arm64/kvm/hyp/include/hyp/debug-sr.h +30 −30
  125. arch/arm64/kvm/hyp/include/hyp/switch.h +35 −4
  126. arch/arm64/kvm/hyp/nvhe/switch.c +5 −0
  127. arch/arm64/kvm/hyp/vgic-v3-sr.c +8 −8
  128. arch/arm64/kvm/hyp/vhe/switch.c +5 −0
  129. arch/arm64/kvm/mmu.c +14 −5
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  210. arch/riscv/include/asm/clint.h +0 −39
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  1729. mm/memory.c +45 −55
  1730. mm/memremap.c +1 −1
  1731. mm/migrate.c +18 −11
  1732. mm/page_alloc.c +6 −1
  1733. mm/rmap.c +7 −2
  1734. mm/rodata_test.c +1 −0
  1735. mm/slub.c +6 −6
  1736. mm/vmalloc.c +2 −0
  1737. mm/vmscan.c +8 −0
  1738. mm/vmstat.c +1 −0
  1739. net/8021q/vlan_dev.c +1 −1
  1740. net/9p/trans_xen.c +1 −1
  1741. net/atm/common.c +2 −2
  1742. net/atm/lec.c +1 −1
  1743. net/atm/resources.c +4 −4
  1744. net/batman-adv/bat_v_ogm.c +6 −5
  1745. net/batman-adv/bridge_loop_avoidance.c +4 −1
  1746. net/batman-adv/gateway_client.c +4 −2
  1747. net/bpf/test_run.c +1 −1
  1748. net/bridge/netfilter/ebtables.c +4 −0
  1749. net/bridge/netfilter/nf_conntrack_bridge.c +6 −2
  1750. net/caif/cfrfml.c +2 −2
  1751. net/can/j1939/socket.c +15 −1
  1752. net/can/j1939/transport.c +94 −30
  1753. net/ceph/ceph_hash.c +10 −10
  1754. net/ceph/crush/mapper.c +1 −1
  1755. net/ceph/messenger.c +2 −2
  1756. net/ceph/mon_client.c +1 −1
  1757. net/ceph/osd_client.c +2 −2
  1758. net/core/dev.c +16 −13
  1759. net/core/dev_ioctl.c +3 −3
  1760. net/core/devlink.c +3 −3
  1761. net/core/drop_monitor.c +1 −1
  1762. net/core/filter.c +63 −14
  1763. net/core/netpoll.c +1 −1
  1764. net/core/pktgen.c +2 −2
  1765. net/core/skbuff.c +11 −5
  1766. net/core/skmsg.c +0 −1
  1767. net/core/sock.c +2 −2
  1768. net/dccp/ccids/ccid3.c +1 −1
  1769. net/dccp/feat.c +2 −1
  1770. net/dccp/input.c +5 −5
  1771. net/dccp/options.c +1 −1
  1772. net/dccp/output.c +4 −4
  1773. net/dccp/proto.c +4 −4
  1774. net/decnet/af_decnet.c +3 −3
  1775. net/decnet/dn_nsp_in.c +1 −1
  1776. net/decnet/dn_table.c +1 −1
  1777. net/decnet/sysctl_net_decnet.c +1 −1
  1778. net/dsa/slave.c +1 −1
  1779. net/ethtool/features.c +10 −9
  1780. net/ieee802154/6lowpan/reassembly.c +1 −1
  1781. net/ieee802154/6lowpan/rx.c +2 −2
  1782. net/ipv4/Kconfig +7 −7
  1783. net/ipv4/fib_trie.c +2 −1
  1784. net/ipv4/netfilter/nf_nat_pptp.c +1 −1
  1785. net/ipv4/nexthop.c +4 −1
  1786. net/ipv4/raw.c +1 −1
  1787. net/ipv6/addrconf.c +23 −37
  1788. net/ipv6/ip6_tunnel.c +9 −1
  1789. net/ipv6/netfilter.c +0 −3
  1790. net/ipv6/sysctl_net_ipv6.c +2 −1
  1791. net/iucv/af_iucv.c +5 −5
  1792. net/l3mdev/l3mdev.c +1 −1
  1793. net/mac80211/airtime.c +146 −56
  1794. net/mac80211/sta_info.h +3 −2
  1795. net/mac80211/status.c +23 −20
  1796. net/mpls/af_mpls.c +1 −1
  1797. net/mptcp/protocol.c +12 −8
  1798. net/ncsi/ncsi-manage.c +2 −2
  1799. net/netfilter/ipvs/ip_vs_proto_tcp.c +1 −1
  1800. net/netfilter/ipvs/ip_vs_proto_udp.c +1 −1
  1801. net/netfilter/nf_conntrack_pptp.c +1 −1
  1802. net/netfilter/nf_conntrack_proto_sctp.c +35 −4
  1803. net/netfilter/nf_conntrack_proto_tcp.c +1 −1
  1804. net/netfilter/nf_conntrack_proto_udp.c +10 −16
  1805. net/netfilter/nf_tables_api.c +35 −35
  1806. net/netfilter/nfnetlink.c +8 −3
  1807. net/netfilter/nfnetlink_log.c +1 −2
  1808. net/netfilter/nfnetlink_queue.c +1 −1
  1809. net/netfilter/nft_compat.c +14 −23
  1810. net/netfilter/nft_exthdr.c +2 −2
  1811. net/netfilter/nft_flow_offload.c +1 −1
  1812. net/netfilter/nft_payload.c +3 −1
  1813. net/netfilter/nft_set_rbtree.c +47 −10
  1814. net/netfilter/xt_recent.c +1 −1
  1815. net/netlabel/netlabel_domainhash.c +30 −29
  1816. net/netlink/af_netlink.c +1 −1
  1817. net/netlink/policy.c +4 −1
  1818. net/netrom/nr_in.c +1 −1
  1819. net/netrom/nr_route.c +4 −4
  1820. net/openvswitch/conntrack.c +2 −2
  1821. net/openvswitch/flow.c +1 −1
  1822. net/packet/af_packet.c +7 −2
  1823. net/phonet/pep.c +5 −5
  1824. net/qrtr/qrtr.c +11 −9
  1825. net/rds/send.c +1 −1
  1826. net/rose/rose_in.c +1 −1
  1827. net/rose/rose_route.c +2 −2
  1828. net/rxrpc/af_rxrpc.c +3 −3
  1829. net/rxrpc/ar-internal.h +8 −5
  1830. net/rxrpc/call_accept.c +1 −1
  1831. net/rxrpc/call_object.c +1 −0
  1832. net/rxrpc/conn_client.c +1 −1
  1833. net/rxrpc/input.c +73 −56
  1834. net/rxrpc/local_object.c +1 −1
  1835. net/rxrpc/output.c +61 −21
  1836. net/rxrpc/peer_event.c +1 −1
  1837. net/rxrpc/peer_object.c +13 −3
  1838. net/rxrpc/recvmsg.c +1 −1
  1839. net/rxrpc/rtt.c +2 −1
  1840. net/rxrpc/rxkad.c +2 −1
  1841. net/rxrpc/sendmsg.c +3 −3
  1842. net/sched/act_ct.c +1 −1
  1843. net/sched/sch_cake.c +1 −1
  1844. net/sched/sch_red.c +4 −16
  1845. net/sched/sch_taprio.c +24 −6
  1846. net/sctp/ipv6.c +1 −1
  1847. net/sctp/outqueue.c +3 −3
  1848. net/sctp/sm_make_chunk.c +1 −1
  1849. net/sctp/sm_sideeffect.c +1 −1
  1850. net/sctp/sm_statefuns.c +1 −1
  1851. net/sctp/socket.c +6 −10
  1852. net/sctp/stream.c +4 −2
  1853. net/smc/smc_close.c +9 −8
  1854. net/smc/smc_core.c +3 −0
  1855. net/smc/smc_diag.c +9 −7
  1856. net/smc/smc_llc.c +14 −1
  1857. net/socket.c +2 −2
  1858. net/sunrpc/auth_gss/gss_krb5_wrap.c +1 −1
  1859. net/sunrpc/auth_gss/trace.c +0 −1
  1860. net/sunrpc/clnt.c +11 −11
  1861. net/sunrpc/xprt.c +1 −1
  1862. net/sunrpc/xprtrdma/verbs.c +1 −1
  1863. net/sunrpc/xprtsock.c +4 −4
  1864. net/tipc/Kconfig +1 −0
  1865. net/tipc/bearer.c +1 −1
  1866. net/tipc/crypto.c +11 −3
  1867. net/tipc/group.c +1 −1
  1868. net/tipc/link.c +1 −1
  1869. net/tipc/netlink_compat.c +11 −1
  1870. net/tipc/socket.c +8 −5
  1871. net/tipc/udp_media.c +3 −5
  1872. net/unix/af_unix.c +1 −1
  1873. net/wireless/chan.c +13 −6
  1874. net/wireless/mlme.c +1 −1
  1875. net/wireless/nl80211.c +11 −11
  1876. net/wireless/reg.c +3 −0
  1877. net/wireless/scan.c +1 −1
  1878. net/wireless/sme.c +2 −2
  1879. net/wireless/util.c +7 −5
  1880. net/wireless/wext-compat.c +2 −2
  1881. net/x25/x25_facilities.c +1 −1
  1882. net/x25/x25_in.c +1 −1
  1883. net/xfrm/xfrm_policy.c +1 −1
  1884. samples/bpf/hbm.c +1 −1
  1885. scripts/Makefile.extrawarn +1 −1
  1886. scripts/checkpatch.pl +2 −2
  1887. scripts/extract-cert.c +1 −1
  1888. scripts/genksyms/keywords.c +2 −2
  1889. scripts/kconfig/nconf.c +0 −1
  1890. scripts/kconfig/qconf.cc +77 −79
  1891. scripts/kconfig/qconf.h +3 −3
  1892. scripts/kconfig/streamline_config.pl +4 −1
  1893. security/apparmor/domain.c +1 −1
  1894. security/apparmor/lib.c +2 −2
  1895. security/integrity/ima/ima_appraise.c +2 −2
  1896. security/integrity/ima/ima_policy.c +4 −4
  1897. security/integrity/ima/ima_template_lib.c +1 −1
  1898. security/keys/process_keys.c +3 −3
  1899. security/keys/request_key.c +4 −4
  1900. security/selinux/hooks.c +1 −7
  1901. security/selinux/ss/mls.c +1 −3
  1902. security/smack/smack_lsm.c +1 −1
  1903. security/tomoyo/common.c +9 −9
  1904. security/tomoyo/file.c +1 −1
  1905. sound/core/oss/mulaw.c +2 −2
  1906. sound/core/timer.c +3 −4
  1907. sound/firewire/amdtp-stream.c +4 −4
  1908. sound/firewire/digi00x/digi00x.c +5 −0
  1909. sound/firewire/tascam/tascam.c +29 −4
  1910. sound/hda/hdac_bus.c +12 −0
  1911. sound/hda/hdac_controller.c +0 −11
  1912. sound/hda/hdac_device.c +2 −0
  1913. sound/hda/intel-dsp-config.c +5 −5
  1914. sound/isa/sscape.c +3 −3
  1915. sound/pci/asihpi/asihpi.c +4 −5
  1916. sound/pci/ca0106/ca0106_main.c +2 −1
  1917. sound/pci/hda/hda_intel.c +3 −4
  1918. sound/pci/hda/hda_tegra.c +7 −0
  1919. sound/pci/hda/patch_hdmi.c +7 −0
  1920. sound/pci/hda/patch_realtek.c +46 −1
  1921. sound/pci/riptide/riptide.c +3 −3
  1922. sound/pci/rme9652/hdsp.c +3 −3
  1923. sound/pci/rme9652/hdspm.c +3 −4
  1924. sound/ppc/snd_ps3.c +2 −2
  1925. sound/soc/amd/acp3x-rt5682-max9836.c +1 −1
  1926. sound/soc/amd/renoir/acp3x-pdm-dma.c +9 −20
  1927. sound/soc/atmel/mchp-i2s-mcc.c +1 −1
  1928. sound/soc/codecs/jz4770.c +1 −1
  1929. sound/soc/codecs/msm8916-wcd-analog.c +2 −2
  1930. sound/soc/codecs/pcm186x.c +1 −1
  1931. sound/soc/codecs/wm8958-dsp2.c +4 −0
  1932. sound/soc/codecs/wm8962.c +1 −1
  1933. sound/soc/codecs/wm8994.c +44 −16
  1934. sound/soc/fsl/fsl-asoc-card.c +70 −84
  1935. sound/soc/fsl/fsl_esai.c +3 −4
  1936. sound/soc/fsl/fsl_ssi.c +1 −1
  1937. sound/soc/fsl/mpc5200_dma.c +0 −1
  1938. sound/soc/hisilicon/hi6210-i2s.c +2 −2
  1939. sound/soc/intel/atom/sst-mfld-platform-pcm.c +3 −2
  1940. sound/soc/intel/baytrail/sst-baytrail-pcm.c +1 −1
  1941. sound/soc/intel/boards/bytcht_es8316.c +1 −1
  1942. sound/soc/intel/boards/bytcr_rt5651.c +2 −2
  1943. sound/soc/intel/skylake/skl-pcm.c +1 −1
  1944. sound/soc/meson/axg-tdm-interface.c +5 −5
  1945. sound/soc/pxa/pxa-ssp.c +1 −1
  1946. sound/soc/qcom/qdsp6/q6afe-dai.c +105 −105
  1947. sound/soc/qcom/qdsp6/q6routing.c +16 −0
  1948. sound/soc/rockchip/rockchip_pdm.c +3 −3
  1949. sound/soc/samsung/i2s.c +1 −1
  1950. sound/soc/sh/siu_pcm.c +4 −6
  1951. sound/soc/soc-component.c +1 −1
  1952. sound/soc/soc-core.c +1 −1
  1953. sound/soc/soc-topology.c +2 −2
  1954. sound/soc/sof/intel/hda-dai.c +2 −2
  1955. sound/soc/sof/pcm.c +2 −2
  1956. sound/soc/tegra/tegra186_dspk.c +2 −2
  1957. sound/soc/tegra/tegra210_admaif.c +2 −2
  1958. sound/soc/tegra/tegra210_ahub.c +2 −2
  1959. sound/soc/tegra/tegra210_dmic.c +2 −2
  1960. sound/soc/tegra/tegra210_i2s.c +2 −2
  1961. sound/soc/ti/davinci-i2s.c +1 −1
  1962. sound/soc/ti/n810.c +1 −1
  1963. sound/soc/ti/omap-dmic.c +2 −2
  1964. sound/soc/ti/omap-mcpdm.c +4 −4
  1965. sound/soc/ti/rx51.c +1 −1
  1966. sound/soc/txx9/txx9aclc.c +3 −4
  1967. sound/soc/zte/zx-i2s.c +2 −2
  1968. sound/soc/zte/zx-spdif.c +1 −1
  1969. sound/usb/midi.c +3 −4
  1970. sound/usb/misc/ua101.c +3 −4
  1971. sound/usb/mixer.c +7 −1
  1972. sound/usb/pcm.c +2 −0
  1973. sound/usb/quirks-table.h +99 −13
  1974. sound/usb/quirks.c +11 −0
  1975. sound/usb/usbaudio.h +1 −0
  1976. sound/x86/Kconfig +1 −1
  1977. tools/bpf/bpftool/btf_dumper.c +1 −1
  1978. tools/bpf/bpftool/gen.c +18 −4
  1979. tools/bpf/bpftool/link.c +2 −2
  1980. tools/bpf/bpftool/main.h +9 −1
  1981. tools/bpf/bpftool/pids.c +2 −0
  1982. tools/bpf/bpftool/prog.c +8 −8
  1983. tools/bpf/resolve_btfids/main.c +36 −0
  1984. tools/include/uapi/linux/bpf.h +5 −5
  1985. tools/include/uapi/linux/perf_event.h +1 −1
  1986. tools/lib/bpf/bpf_helpers.h +1 −1
  1987. tools/lib/bpf/btf.c +80 −3
  1988. tools/lib/bpf/btf.h +2 −0
  1989. tools/lib/bpf/btf_dump.c +37 −2
  1990. tools/lib/bpf/libbpf.c +22 −12
  1991. tools/lib/bpf/libbpf.map +2 −0
  1992. tools/lib/traceevent/event-parse.c +1 −1
  1993. tools/perf/Documentation/perf-record.txt +4 −0
  1994. tools/perf/Documentation/perf-stat.txt +7 −0
  1995. tools/perf/bench/synthesize.c +2 −2
  1996. tools/perf/builtin-record.c +1 −1
  1997. tools/perf/builtin-report.c +3 −0
  1998. tools/perf/builtin-sched.c +5 −1
  1999. tools/perf/builtin-stat.c +5 −3
  2000. tools/perf/builtin-top.c +2 −0
  2001. tools/perf/pmu-events/jevents.c +1 −1
  2002. tools/perf/tests/bpf.c +1 −1
  2003. tools/perf/tests/parse-events.c +2 −2
  2004. tools/perf/tests/parse-metric.c +3 −0
  2005. tools/perf/ui/browsers/hists.c +2 −1
  2006. tools/perf/util/arm-spe-decoder/arm-spe-decoder.c +3 −3
  2007. tools/perf/util/cs-etm.c +8 −1
  2008. tools/perf/util/intel-pt.c +8 −1
  2009. tools/perf/util/machine.c +0 −6
  2010. tools/perf/util/map.c +16 −0
  2011. tools/perf/util/map.h +8 −1
  2012. tools/perf/util/parse-events.c +19 −12
  2013. tools/perf/util/parse-events.y +4 −4
  2014. tools/perf/util/session.c +1 −1
  2015. tools/perf/util/stat-display.c +1 −1
  2016. tools/perf/util/stat.h +1 −0
  2017. tools/perf/util/symbol.c +1 −0
  2018. tools/perf/util/zstd.c +1 −1
  2019. tools/testing/selftests/bpf/.gitignore +0 −1
  2020. tools/testing/selftests/bpf/Makefile +1 −1
  2021. tools/testing/selftests/bpf/prog_tests/bpf_obj_id.c +4 −4
  2022. tools/testing/selftests/bpf/prog_tests/btf_dump.c +20 −7
  2023. tools/testing/selftests/bpf/prog_tests/core_extern.c +2 −2
  2024. tools/testing/selftests/bpf/prog_tests/core_reloc.c +10 −10
  2025. tools/testing/selftests/bpf/prog_tests/fexit_bpf2bpf.c +3 −3
  2026. tools/testing/selftests/bpf/prog_tests/flow_dissector.c +1 −1
  2027. tools/testing/selftests/bpf/prog_tests/global_data.c +3 −3
  2028. tools/testing/selftests/bpf/prog_tests/mmap.c +13 −6
  2029. tools/testing/selftests/bpf/prog_tests/prog_run_xattr.c +1 −1
  2030. tools/testing/selftests/bpf/prog_tests/sk_lookup.c +1 −0
  2031. tools/testing/selftests/bpf/prog_tests/skb_ctx.c +1 −1
  2032. tools/testing/selftests/bpf/prog_tests/test_global_funcs.c +1 −1
  2033. tools/testing/selftests/bpf/prog_tests/varlen.c +4 −4
  2034. tools/testing/selftests/bpf/progs/core_reloc_types.h +37 −32
  2035. tools/testing/selftests/bpf/progs/test_tcpbpf_kern.c +41 −0
  2036. tools/testing/selftests/bpf/progs/test_varlen.c +3 −3
  2037. tools/testing/selftests/bpf/test_btf.c +4 −4
  2038. tools/testing/selftests/bpf/test_maps.c +2 −0
  2039. tools/testing/selftests/bpf/test_progs.c +3 −1
  2040. tools/testing/selftests/bpf/test_progs.h +5 −0
  2041. tools/testing/selftests/kvm/x86_64/debug_regs.c +2 −2
  2042. tools/testing/selftests/net/icmp_redirect.sh +2 −0
  2043. tools/testing/selftests/netfilter/nft_flowtable.sh +75 −55
  2044. tools/testing/selftests/powerpc/mm/.gitignore +1 −0
  2045. tools/testing/selftests/powerpc/mm/Makefile +3 −1
  2046. tools/testing/selftests/powerpc/mm/prot_sao.c +43 −0
  2047. tools/testing/selftests/x86/test_vsyscall.c +20 −2
  2048. tools/usb/Build +2 −0
  2049. tools/usb/Makefile +45 −8
  2050. virt/kvm/kvm_main.c +2 −1
.clang-format+12−0
@@ -111,6 +111,7 @@ ForEachMacros: · 110 unmodified lines
111 - 'css_for_each_descendant_pre'111 - 'css_for_each_descendant_pre'
112 - 'device_for_each_child_node'112 - 'device_for_each_child_node'
113 - 'dma_fence_chain_for_each'113 - 'dma_fence_chain_for_each'
114 - 'do_for_each_ftrace_op'
114 - 'drm_atomic_crtc_for_each_plane'115 - 'drm_atomic_crtc_for_each_plane'
115 - 'drm_atomic_crtc_state_for_each_plane'116 - 'drm_atomic_crtc_state_for_each_plane'
116 - 'drm_atomic_crtc_state_for_each_plane_state'117 - 'drm_atomic_crtc_state_for_each_plane_state'
@@ -136,6 +137,7 @@ ForEachMacros: · 19 unmodified lines
136 - 'for_each_active_dev_scope'137 - 'for_each_active_dev_scope'
137 - 'for_each_active_drhd_unit'138 - 'for_each_active_drhd_unit'
138 - 'for_each_active_iommu'139 - 'for_each_active_iommu'
140 - 'for_each_aggr_pgid'
139 - 'for_each_available_child_of_node'141 - 'for_each_available_child_of_node'
140 - 'for_each_bio'142 - 'for_each_bio'
141 - 'for_each_board_func_rsrc'143 - 'for_each_board_func_rsrc'
@@ -234,6 +236,7 @@ ForEachMacros: · 92 unmodified lines
234 - 'for_each_node_state'236 - 'for_each_node_state'
235 - 'for_each_node_with_cpus'237 - 'for_each_node_with_cpus'
236 - 'for_each_node_with_property'238 - 'for_each_node_with_property'
239 - 'for_each_nonreserved_multicast_dest_pgid'
237 - 'for_each_of_allnodes'240 - 'for_each_of_allnodes'
238 - 'for_each_of_allnodes_from'241 - 'for_each_of_allnodes_from'
239 - 'for_each_of_cpu_node'242 - 'for_each_of_cpu_node'
@@ -256,6 +259,7 @@ ForEachMacros: · 16 unmodified lines
256 - 'for_each_pci_dev'259 - 'for_each_pci_dev'
257 - 'for_each_pci_msi_entry'260 - 'for_each_pci_msi_entry'
258 - 'for_each_pcm_streams'261 - 'for_each_pcm_streams'
262 - 'for_each_physmem_range'
259 - 'for_each_populated_zone'263 - 'for_each_populated_zone'
260 - 'for_each_possible_cpu'264 - 'for_each_possible_cpu'
261 - 'for_each_present_cpu'265 - 'for_each_present_cpu'
@@ -265,6 +269,8 @@ ForEachMacros: · 3 unmodified lines
265 - 'for_each_process_thread'269 - 'for_each_process_thread'
266 - 'for_each_property_of_node'270 - 'for_each_property_of_node'
267 - 'for_each_registered_fb'271 - 'for_each_registered_fb'
272 - 'for_each_requested_gpio'
273 - 'for_each_requested_gpio_in_range'
268 - 'for_each_reserved_mem_region'274 - 'for_each_reserved_mem_region'
269 - 'for_each_rtd_codec_dais'275 - 'for_each_rtd_codec_dais'
270 - 'for_each_rtd_codec_dais_rollback'276 - 'for_each_rtd_codec_dais_rollback'
@@ -278,12 +284,17 @@ ForEachMacros: · 7 unmodified lines
278 - 'for_each_sg'284 - 'for_each_sg'
279 - 'for_each_sg_dma_page'285 - 'for_each_sg_dma_page'
280 - 'for_each_sg_page'286 - 'for_each_sg_page'
287 - 'for_each_sgtable_dma_page'
288 - 'for_each_sgtable_dma_sg'
289 - 'for_each_sgtable_page'
290 - 'for_each_sgtable_sg'
281 - 'for_each_sibling_event'291 - 'for_each_sibling_event'
282 - 'for_each_subelement'292 - 'for_each_subelement'
283 - 'for_each_subelement_extid'293 - 'for_each_subelement_extid'
284 - 'for_each_subelement_id'294 - 'for_each_subelement_id'
285 - '__for_each_thread'295 - '__for_each_thread'
286 - 'for_each_thread'296 - 'for_each_thread'
297 - 'for_each_unicast_dest_pgid'
287 - 'for_each_wakeup_source'298 - 'for_each_wakeup_source'
288 - 'for_each_zone'299 - 'for_each_zone'
289 - 'for_each_zone_zonelist'300 - 'for_each_zone_zonelist'
@@ -464,6 +475,7 @@ ForEachMacros: · 174 unmodified lines
464 - 'v4l2_m2m_for_each_src_buf'475 - 'v4l2_m2m_for_each_src_buf'
465 - 'v4l2_m2m_for_each_src_buf_safe'476 - 'v4l2_m2m_for_each_src_buf_safe'
466 - 'virtio_device_for_each_vq'477 - 'virtio_device_for_each_vq'
478 - 'while_for_each_ftrace_op'
467 - 'xa_for_each'479 - 'xa_for_each'
468 - 'xa_for_each_marked'480 - 'xa_for_each_marked'
469 - 'xa_for_each_range'481 - 'xa_for_each_range'
.mailmap+61−57
@@ -15,30 +15,31 @@ · 14 unmodified lines
15Aaron Durbin <adurbin@google.com>15Aaron Durbin <adurbin@google.com>
16Adam Oldham <oldhamca@gmail.com>16Adam Oldham <oldhamca@gmail.com>
17Adam Radford <aradford@gmail.com>17Adam Radford <aradford@gmail.com>
18Adrian Bunk <bunk@stusta.de>
19Adriana Reus <adi.reus@gmail.com> <adriana.reus@intel.com>18Adriana Reus <adi.reus@gmail.com> <adriana.reus@intel.com>
19Adrian Bunk <bunk@stusta.de>
20Alan Cox <alan@lxorguk.ukuu.org.uk>20Alan Cox <alan@lxorguk.ukuu.org.uk>
21Alan Cox <root@hraefn.swansea.linux.org.uk>21Alan Cox <root@hraefn.swansea.linux.org.uk>
22Aleksey Gorelov <aleksey_gorelov@phoenix.com>
23Aleksandar Markovic <aleksandar.markovic@mips.com> <aleksandar.markovic@imgtec.com>22Aleksandar Markovic <aleksandar.markovic@mips.com> <aleksandar.markovic@imgtec.com>
24Alex Shi <alex.shi@linux.alibaba.com> <alex.shi@intel.com>23Aleksey Gorelov <aleksey_gorelov@phoenix.com>
25Alex Shi <alex.shi@linux.alibaba.com> <alex.shi@linaro.org>
26Alexander Lobakin <alobakin@pm.me> <alobakin@dlink.ru>24Alexander Lobakin <alobakin@pm.me> <alobakin@dlink.ru>
27Alexander Lobakin <alobakin@pm.me> <alobakin@marvell.com>25Alexander Lobakin <alobakin@pm.me> <alobakin@marvell.com>
28Alexander Lobakin <alobakin@pm.me> <bloodyreaper@yandex.ru>26Alexander Lobakin <alobakin@pm.me> <bloodyreaper@yandex.ru>
29Alexandre Belloni <alexandre.belloni@bootlin.com> <alexandre.belloni@free-electrons.com>27Alexandre Belloni <alexandre.belloni@bootlin.com> <alexandre.belloni@free-electrons.com>
30Alexei Starovoitov <ast@kernel.org> <ast@plumgrid.com>
31Alexei Starovoitov <ast@kernel.org> <alexei.starovoitov@gmail.com>28Alexei Starovoitov <ast@kernel.org> <alexei.starovoitov@gmail.com>
32Alexei Starovoitov <ast@kernel.org> <ast@fb.com>29Alexei Starovoitov <ast@kernel.org> <ast@fb.com>
30Alexei Starovoitov <ast@kernel.org> <ast@plumgrid.com>
31Alex Shi <alex.shi@linux.alibaba.com> <alex.shi@intel.com>
32Alex Shi <alex.shi@linux.alibaba.com> <alex.shi@linaro.org>
33Al Viro <viro@ftp.linux.org.uk>33Al Viro <viro@ftp.linux.org.uk>
34Al Viro <viro@zenIV.linux.org.uk>34Al Viro <viro@zenIV.linux.org.uk>
35Andi Kleen <ak@linux.intel.com> <ak@suse.de>
35Andi Shyti <andi@etezian.org> <andi.shyti@samsung.com>36Andi Shyti <andi@etezian.org> <andi.shyti@samsung.com>
36Andreas Herrmann <aherrman@de.ibm.com>37Andreas Herrmann <aherrman@de.ibm.com>
37Andrey Ryabinin <ryabinin.a.a@gmail.com> <a.ryabinin@samsung.com>
38Andrew Morton <akpm@linux-foundation.org>38Andrew Morton <akpm@linux-foundation.org>
39Andrew Murray <amurray@thegoodpenguin.co.uk> <andrew.murray@arm.com>
40Andrew Murray <amurray@thegoodpenguin.co.uk> <amurray@embedded-bits.co.uk>39Andrew Murray <amurray@thegoodpenguin.co.uk> <amurray@embedded-bits.co.uk>
40Andrew Murray <amurray@thegoodpenguin.co.uk> <andrew.murray@arm.com>
41Andrew Vasquez <andrew.vasquez@qlogic.com>41Andrew Vasquez <andrew.vasquez@qlogic.com>
42Andrey Ryabinin <ryabinin.a.a@gmail.com> <a.ryabinin@samsung.com>
42Andy Adamson <andros@citi.umich.edu>43Andy Adamson <andros@citi.umich.edu>
43Antoine Tenart <antoine.tenart@free-electrons.com>44Antoine Tenart <antoine.tenart@free-electrons.com>
44Antonio Ospite <ao2@ao2.it> <ao2@amarulasolutions.com>45Antonio Ospite <ao2@ao2.it> <ao2@amarulasolutions.com>
@@ -48,40 +49,42 @@ Arnaud Patard <arnaud.patard@rtp-net.org> · 3 unmodified lines
48Arnd Bergmann <arnd@arndb.de>49Arnd Bergmann <arnd@arndb.de>
49Axel Dyks <xl@xlsigned.net>50Axel Dyks <xl@xlsigned.net>
50Axel Lin <axel.lin@gmail.com>51Axel Lin <axel.lin@gmail.com>
51Bart Van Assche <bvanassche@acm.org> <bart.vanassche@wdc.com>
52Bart Van Assche <bvanassche@acm.org> <bart.vanassche@sandisk.com>52Bart Van Assche <bvanassche@acm.org> <bart.vanassche@sandisk.com>
53Bart Van Assche <bvanassche@acm.org> <bart.vanassche@wdc.com>
53Ben Gardner <bgardner@wabtec.com>54Ben Gardner <bgardner@wabtec.com>
54Ben M Cahill <ben.m.cahill@intel.com>55Ben M Cahill <ben.m.cahill@intel.com>
55Björn Steinbrink <B.Steinbrink@gmx.de>56Björn Steinbrink <B.Steinbrink@gmx.de>
56Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@bootlin.com>
57Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@free-electrons.com>
58Boris Brezillon <bbrezillon@kernel.org> <b.brezillon.dev@gmail.com>57Boris Brezillon <bbrezillon@kernel.org> <b.brezillon.dev@gmail.com>
59Boris Brezillon <bbrezillon@kernel.org> <b.brezillon@overkiz.com>58Boris Brezillon <bbrezillon@kernel.org> <b.brezillon@overkiz.com>
59Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@bootlin.com>
60Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@free-electrons.com>
60Brian Avery <b.avery@hp.com>61Brian Avery <b.avery@hp.com>
61Brian King <brking@us.ibm.com>62Brian King <brking@us.ibm.com>
63Changbin Du <changbin.du@intel.com> <changbin.du@gmail.com>
64Changbin Du <changbin.du@intel.com> <changbin.du@intel.com>
62Chao Yu <chao@kernel.org> <chao2.yu@samsung.com>65Chao Yu <chao@kernel.org> <chao2.yu@samsung.com>
63Chao Yu <chao@kernel.org> <yuchao0@huawei.com>66Chao Yu <chao@kernel.org> <yuchao0@huawei.com>
64Christoph Hellwig <hch@lst.de>
65Christophe Ricard <christophe.ricard@gmail.com>67Christophe Ricard <christophe.ricard@gmail.com>
68Christoph Hellwig <hch@lst.de>
66Corey Minyard <minyard@acm.org>69Corey Minyard <minyard@acm.org>
67Damian Hobson-Garcia <dhobsong@igel.co.jp>70Damian Hobson-Garcia <dhobsong@igel.co.jp>
68Daniel Borkmann <daniel@iogearbox.net> <dborkman@redhat.com>71Daniel Borkmann <daniel@iogearbox.net> <danborkmann@googlemail.com>
69Daniel Borkmann <daniel@iogearbox.net> <dborkmann@redhat.com>
70Daniel Borkmann <daniel@iogearbox.net> <danborkmann@iogearbox.net>72Daniel Borkmann <daniel@iogearbox.net> <danborkmann@iogearbox.net>
71Daniel Borkmann <daniel@iogearbox.net> <daniel.borkmann@tik.ee.ethz.ch>73Daniel Borkmann <daniel@iogearbox.net> <daniel.borkmann@tik.ee.ethz.ch>
72Daniel Borkmann <daniel@iogearbox.net> <danborkmann@googlemail.com>74Daniel Borkmann <daniel@iogearbox.net> <dborkmann@redhat.com>
75Daniel Borkmann <daniel@iogearbox.net> <dborkman@redhat.com>
73Daniel Borkmann <daniel@iogearbox.net> <dxchgb@gmail.com>76Daniel Borkmann <daniel@iogearbox.net> <dxchgb@gmail.com>
74David Brownell <david-b@pacbell.net>77David Brownell <david-b@pacbell.net>
75David Woodhouse <dwmw2@shinybook.infradead.org>78David Woodhouse <dwmw2@shinybook.infradead.org>
76Dengcheng Zhu <dzhu@wavecomp.com> <dengcheng.zhu@mips.com>
77Dengcheng Zhu <dzhu@wavecomp.com> <dengcheng.zhu@imgtec.com>
78Dengcheng Zhu <dzhu@wavecomp.com> <dczhu@mips.com>79Dengcheng Zhu <dzhu@wavecomp.com> <dczhu@mips.com>
79Dengcheng Zhu <dzhu@wavecomp.com> <dengcheng.zhu@gmail.com>80Dengcheng Zhu <dzhu@wavecomp.com> <dengcheng.zhu@gmail.com>
81Dengcheng Zhu <dzhu@wavecomp.com> <dengcheng.zhu@imgtec.com>
82Dengcheng Zhu <dzhu@wavecomp.com> <dengcheng.zhu@mips.com>
80<dev.kurt@vandijck-laurijssen.be> <kurt.van.dijck@eia.be>83<dev.kurt@vandijck-laurijssen.be> <kurt.van.dijck@eia.be>
81Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>84Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
82Dmitry Safonov <0x7f454c46@gmail.com> <dsafonov@virtuozzo.com>
83Dmitry Safonov <0x7f454c46@gmail.com> <d.safonov@partner.samsung.com>
84Dmitry Safonov <0x7f454c46@gmail.com> <dima@arista.com>85Dmitry Safonov <0x7f454c46@gmail.com> <dima@arista.com>
86Dmitry Safonov <0x7f454c46@gmail.com> <d.safonov@partner.samsung.com>
87Dmitry Safonov <0x7f454c46@gmail.com> <dsafonov@virtuozzo.com>
85Domen Puncer <domen@coderock.org>88Domen Puncer <domen@coderock.org>
86Douglas Gilbert <dougg@torque.net>89Douglas Gilbert <dougg@torque.net>
87Ed L. Cashin <ecashin@coraid.com>90Ed L. Cashin <ecashin@coraid.com>
@@ -92,20 +95,22 @@ Felix Kuhling <fxkuehl@gmx.de> · 4 unmodified lines
92Felix Moeller <felix@derklecks.de>95Felix Moeller <felix@derklecks.de>
93Filipe Lautert <filipe@icewall.org>96Filipe Lautert <filipe@icewall.org>
94Franck Bui-Huu <vagabon.xyz@gmail.com>97Franck Bui-Huu <vagabon.xyz@gmail.com>
95Frank Rowand <frowand.list@gmail.com> <frowand@mvista.com>
96Frank Rowand <frowand.list@gmail.com> <frank.rowand@am.sony.com>98Frank Rowand <frowand.list@gmail.com> <frank.rowand@am.sony.com>
97Frank Rowand <frowand.list@gmail.com> <frank.rowand@sonymobile.com>99Frank Rowand <frowand.list@gmail.com> <frank.rowand@sonymobile.com>
100Frank Rowand <frowand.list@gmail.com> <frowand@mvista.com>
98Frank Zago <fzago@systemfabricworks.com>101Frank Zago <fzago@systemfabricworks.com>
99Gao Xiang <xiang@kernel.org> <gaoxiang25@huawei.com>102Gao Xiang <xiang@kernel.org> <gaoxiang25@huawei.com>
100Gao Xiang <xiang@kernel.org> <hsiangkao@aol.com>103Gao Xiang <xiang@kernel.org> <hsiangkao@aol.com>
101Gerald Schaefer <gerald.schaefer@linux.ibm.com> <gerald.schaefer@de.ibm.com>
102Gerald Schaefer <gerald.schaefer@linux.ibm.com> <geraldsc@de.ibm.com>104Gerald Schaefer <gerald.schaefer@linux.ibm.com> <geraldsc@de.ibm.com>
105Gerald Schaefer <gerald.schaefer@linux.ibm.com> <gerald.schaefer@de.ibm.com>
103Gerald Schaefer <gerald.schaefer@linux.ibm.com> <geraldsc@linux.vnet.ibm.com>106Gerald Schaefer <gerald.schaefer@linux.ibm.com> <geraldsc@linux.vnet.ibm.com>
104Greg Kroah-Hartman <greg@echidna.(none)>107Greg Kroah-Hartman <greg@echidna.(none)>
105Greg Kroah-Hartman <gregkh@suse.de>108Greg Kroah-Hartman <gregkh@suse.de>
106Greg Kroah-Hartman <greg@kroah.com>109Greg Kroah-Hartman <greg@kroah.com>
107Greg Kurz <groug@kaod.org> <gkurz@linux.vnet.ibm.com>110Greg Kurz <groug@kaod.org> <gkurz@linux.vnet.ibm.com>
108Gregory CLEMENT <gregory.clement@bootlin.com> <gregory.clement@free-electrons.com>111Gregory CLEMENT <gregory.clement@bootlin.com> <gregory.clement@free-electrons.com>
112Gustavo Padovan <gustavo@las.ic.unicamp.br>
113Gustavo Padovan <padovan@profusion.mobi>
109Hanjun Guo <guohanjun@huawei.com> <hanjun.guo@linaro.org>114Hanjun Guo <guohanjun@huawei.com> <hanjun.guo@linaro.org>
110Heiko Carstens <hca@linux.ibm.com> <h.carstens@de.ibm.com>115Heiko Carstens <hca@linux.ibm.com> <h.carstens@de.ibm.com>
111Heiko Carstens <hca@linux.ibm.com> <heiko.carstens@de.ibm.com>116Heiko Carstens <hca@linux.ibm.com> <heiko.carstens@de.ibm.com>
@@ -115,32 +120,33 @@ Henrik Rydberg <rydberg@bitmath.org> · 3 unmodified lines
115Herbert Xu <herbert@gondor.apana.org.au>120Herbert Xu <herbert@gondor.apana.org.au>
116Jacob Shin <Jacob.Shin@amd.com>121Jacob Shin <Jacob.Shin@amd.com>
117Jaegeuk Kim <jaegeuk@kernel.org> <jaegeuk@google.com>122Jaegeuk Kim <jaegeuk@kernel.org> <jaegeuk@google.com>
118Jaegeuk Kim <jaegeuk@kernel.org> <jaegeuk@motorola.com>
119Jaegeuk Kim <jaegeuk@kernel.org> <jaegeuk.kim@samsung.com>123Jaegeuk Kim <jaegeuk@kernel.org> <jaegeuk.kim@samsung.com>
124Jaegeuk Kim <jaegeuk@kernel.org> <jaegeuk@motorola.com>
120Jakub Kicinski <kuba@kernel.org> <jakub.kicinski@netronome.com>125Jakub Kicinski <kuba@kernel.org> <jakub.kicinski@netronome.com>
121James Bottomley <jejb@mulgrave.(none)>126James Bottomley <jejb@mulgrave.(none)>
122James Bottomley <jejb@titanic.il.steeleye.com>127James Bottomley <jejb@titanic.il.steeleye.com>
123James E Wilson <wilson@specifix.com>128James E Wilson <wilson@specifix.com>
124James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
125James Hogan <jhogan@kernel.org> <james@albanarts.com>129James Hogan <jhogan@kernel.org> <james@albanarts.com>
130James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
126James Ketrenos <jketreno@io.(none)>131James Ketrenos <jketreno@io.(none)>
127Jan Glauber <jan.glauber@gmail.com> <jang@de.ibm.com>132Jan Glauber <jan.glauber@gmail.com> <jang@de.ibm.com>
128Jan Glauber <jan.glauber@gmail.com> <jang@linux.vnet.ibm.com>133Jan Glauber <jan.glauber@gmail.com> <jang@linux.vnet.ibm.com>
129Jan Glauber <jan.glauber@gmail.com> <jglauber@cavium.com>134Jan Glauber <jan.glauber@gmail.com> <jglauber@cavium.com>
130Jason Gunthorpe <jgg@ziepe.ca> <jgg@mellanox.com>135Jason Gunthorpe <jgg@ziepe.ca> <jgg@mellanox.com>
136Jason Gunthorpe <jgg@ziepe.ca> <jgg@nvidia.com>
131Jason Gunthorpe <jgg@ziepe.ca> <jgunthorpe@obsidianresearch.com>137Jason Gunthorpe <jgg@ziepe.ca> <jgunthorpe@obsidianresearch.com>
132Javi Merino <javi.merino@kernel.org> <javi.merino@arm.com>
133<javier@osg.samsung.com> <javier.martinez@collabora.co.uk>138<javier@osg.samsung.com> <javier.martinez@collabora.co.uk>
139Javi Merino <javi.merino@kernel.org> <javi.merino@arm.com>
134Jayachandran C <c.jayachandran@gmail.com> <jayachandranc@netlogicmicro.com>140Jayachandran C <c.jayachandran@gmail.com> <jayachandranc@netlogicmicro.com>
135Jayachandran C <c.jayachandran@gmail.com> <jchandra@broadcom.com>141Jayachandran C <c.jayachandran@gmail.com> <jchandra@broadcom.com>
136Jayachandran C <c.jayachandran@gmail.com> <jchandra@digeo.com>142Jayachandran C <c.jayachandran@gmail.com> <jchandra@digeo.com>
137Jayachandran C <c.jayachandran@gmail.com> <jnair@caviumnetworks.com>143Jayachandran C <c.jayachandran@gmail.com> <jnair@caviumnetworks.com>
138Jean Tourrilhes <jt@hpl.hp.com>
139<jean-philippe@linaro.org> <jean-philippe.brucker@arm.com>144<jean-philippe@linaro.org> <jean-philippe.brucker@arm.com>
145Jean Tourrilhes <jt@hpl.hp.com>
140Jeff Garzik <jgarzik@pretzel.yyz.us>146Jeff Garzik <jgarzik@pretzel.yyz.us>
141Jeff Layton <jlayton@kernel.org> <jlayton@redhat.com>
142Jeff Layton <jlayton@kernel.org> <jlayton@poochiereds.net>147Jeff Layton <jlayton@kernel.org> <jlayton@poochiereds.net>
143Jeff Layton <jlayton@kernel.org> <jlayton@primarydata.com>148Jeff Layton <jlayton@kernel.org> <jlayton@primarydata.com>
149Jeff Layton <jlayton@kernel.org> <jlayton@redhat.com>
144Jens Axboe <axboe@suse.de>150Jens Axboe <axboe@suse.de>
145Jens Osterkamp <Jens.Osterkamp@de.ibm.com>151Jens Osterkamp <Jens.Osterkamp@de.ibm.com>
146Jiri Slaby <jirislaby@kernel.org> <jirislaby@gmail.com>152Jiri Slaby <jirislaby@kernel.org> <jirislaby@gmail.com>
@@ -164,30 +170,31 @@ Julien Thierry <julien.thierry.kdev@gmail.com> <julien.thierry@arm.com> · 17 unmodified lines
164Kamil Konieczny <k.konieczny@samsung.com> <k.konieczny@partner.samsung.com>170Kamil Konieczny <k.konieczny@samsung.com> <k.konieczny@partner.samsung.com>
165Kay Sievers <kay.sievers@vrfy.org>171Kay Sievers <kay.sievers@vrfy.org>
166Kenneth W Chen <kenneth.w.chen@intel.com>172Kenneth W Chen <kenneth.w.chen@intel.com>
167Konstantin Khlebnikov <koct9i@gmail.com> <k.khlebnikov@samsung.com>
168Konstantin Khlebnikov <koct9i@gmail.com> <khlebnikov@yandex-team.ru>173Konstantin Khlebnikov <koct9i@gmail.com> <khlebnikov@yandex-team.ru>
174Konstantin Khlebnikov <koct9i@gmail.com> <k.khlebnikov@samsung.com>
169Koushik <raghavendra.koushik@neterion.com>175Koushik <raghavendra.koushik@neterion.com>
170Krzysztof Kozlowski <krzk@kernel.org> <k.kozlowski@samsung.com>
171Krzysztof Kozlowski <krzk@kernel.org> <k.kozlowski.k@gmail.com>176Krzysztof Kozlowski <krzk@kernel.org> <k.kozlowski.k@gmail.com>
177Krzysztof Kozlowski <krzk@kernel.org> <k.kozlowski@samsung.com>
172Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>178Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
173Leon Romanovsky <leon@kernel.org> <leon@leon.nu>
174Leon Romanovsky <leon@kernel.org> <leonro@mellanox.com>
175Leonardo Bras <leobras.c@gmail.com> <leonardo@linux.ibm.com>179Leonardo Bras <leobras.c@gmail.com> <leonardo@linux.ibm.com>
176Leonid I Ananiev <leonid.i.ananiev@intel.com>180Leonid I Ananiev <leonid.i.ananiev@intel.com>
181Leon Romanovsky <leon@kernel.org> <leon@leon.nu>
182Leon Romanovsky <leon@kernel.org> <leonro@mellanox.com>
183Leon Romanovsky <leon@kernel.org> <leonro@nvidia.com>
177Linas Vepstas <linas@austin.ibm.com>184Linas Vepstas <linas@austin.ibm.com>
178Linus Lüssing <linus.luessing@c0d3.blue> <linus.luessing@web.de>
179Linus Lüssing <linus.luessing@c0d3.blue> <linus.luessing@ascom.ch>185Linus Lüssing <linus.luessing@c0d3.blue> <linus.luessing@ascom.ch>
180Li Yang <leoyang.li@nxp.com> <leo@zh-kernel.org>186Linus Lüssing <linus.luessing@c0d3.blue> <linus.luessing@web.de>
181Li Yang <leoyang.li@nxp.com> <leoli@freescale.com>187Li Yang <leoyang.li@nxp.com> <leoli@freescale.com>
188Li Yang <leoyang.li@nxp.com> <leo@zh-kernel.org>
182Lukasz Luba <lukasz.luba@arm.com> <l.luba@partner.samsung.com>189Lukasz Luba <lukasz.luba@arm.com> <l.luba@partner.samsung.com>
183Maciej W. Rozycki <macro@mips.com> <macro@imgtec.com>190Maciej W. Rozycki <macro@mips.com> <macro@imgtec.com>
184Marc Zyngier <maz@kernel.org> <marc.zyngier@arm.com>
185Marcin Nowakowski <marcin.nowakowski@mips.com> <marcin.nowakowski@imgtec.com>191Marcin Nowakowski <marcin.nowakowski@mips.com> <marcin.nowakowski@imgtec.com>
192Marc Zyngier <maz@kernel.org> <marc.zyngier@arm.com>
186Mark Brown <broonie@sirena.org.uk>193Mark Brown <broonie@sirena.org.uk>
187Mark Yao <markyao0591@gmail.com> <mark.yao@rock-chips.com>194Mark Yao <markyao0591@gmail.com> <mark.yao@rock-chips.com>
188Martin Kepplinger <martink@posteo.de> <martin.kepplinger@theobroma-systems.com>
189Martin Kepplinger <martink@posteo.de> <martin.kepplinger@ginzinger.com>195Martin Kepplinger <martink@posteo.de> <martin.kepplinger@ginzinger.com>
190Martin Kepplinger <martink@posteo.de> <martin.kepplinger@puri.sm>196Martin Kepplinger <martink@posteo.de> <martin.kepplinger@puri.sm>
197Martin Kepplinger <martink@posteo.de> <martin.kepplinger@theobroma-systems.com>
191Mathieu Othacehe <m.othacehe@gmail.com>198Mathieu Othacehe <m.othacehe@gmail.com>
192Matthew Wilcox <willy@infradead.org> <matthew.r.wilcox@intel.com>199Matthew Wilcox <willy@infradead.org> <matthew.r.wilcox@intel.com>
193Matthew Wilcox <willy@infradead.org> <matthew@wil.cx>200Matthew Wilcox <willy@infradead.org> <matthew@wil.cx>
@@ -197,17 +204,17 @@ Matthew Wilcox <willy@infradead.org> <willy@debian.org> · 3 unmodified lines
197Matthew Wilcox <willy@infradead.org> <willy@linux.intel.com>204Matthew Wilcox <willy@infradead.org> <willy@linux.intel.com>
198Matthew Wilcox <willy@infradead.org> <willy@parisc-linux.org>205Matthew Wilcox <willy@infradead.org> <willy@parisc-linux.org>
199Matthieu CASTET <castet.matthieu@free.fr>206Matthieu CASTET <castet.matthieu@free.fr>
200Mauro Carvalho Chehab <mchehab@kernel.org> <mchehab@brturbo.com.br>207Matt Ranostay <matt.ranostay@konsulko.com> <matt@ranostay.consulting>
208Matt Ranostay <mranostay@gmail.com> Matthew Ranostay <mranostay@embeddedalley.com>
209Matt Ranostay <mranostay@gmail.com> <matt.ranostay@intel.com>
210Matt Redfearn <matt.redfearn@mips.com> <matt.redfearn@imgtec.com>
201Mauro Carvalho Chehab <mchehab@kernel.org> <maurochehab@gmail.com>211Mauro Carvalho Chehab <mchehab@kernel.org> <maurochehab@gmail.com>
212Mauro Carvalho Chehab <mchehab@kernel.org> <mchehab@brturbo.com.br>
202Mauro Carvalho Chehab <mchehab@kernel.org> <mchehab@infradead.org>213Mauro Carvalho Chehab <mchehab@kernel.org> <mchehab@infradead.org>
214Mauro Carvalho Chehab <mchehab@kernel.org> <mchehab@osg.samsung.com>
203Mauro Carvalho Chehab <mchehab@kernel.org> <mchehab@redhat.com>215Mauro Carvalho Chehab <mchehab@kernel.org> <mchehab@redhat.com>
204Mauro Carvalho Chehab <mchehab@kernel.org> <m.chehab@samsung.com>216Mauro Carvalho Chehab <mchehab@kernel.org> <m.chehab@samsung.com>
205Mauro Carvalho Chehab <mchehab@kernel.org> <mchehab@osg.samsung.com>
206Mauro Carvalho Chehab <mchehab@kernel.org> <mchehab@s-opensource.com>217Mauro Carvalho Chehab <mchehab@kernel.org> <mchehab@s-opensource.com>
207Matt Ranostay <mranostay@gmail.com> Matthew Ranostay <mranostay@embeddedalley.com>
208Matt Ranostay <mranostay@gmail.com> <matt.ranostay@intel.com>
209Matt Ranostay <matt.ranostay@konsulko.com> <matt@ranostay.consulting>
210Matt Redfearn <matt.redfearn@mips.com> <matt.redfearn@imgtec.com>
211Maxime Ripard <mripard@kernel.org> <maxime.ripard@bootlin.com>218Maxime Ripard <mripard@kernel.org> <maxime.ripard@bootlin.com>
212Maxime Ripard <mripard@kernel.org> <maxime.ripard@free-electrons.com>219Maxime Ripard <mripard@kernel.org> <maxime.ripard@free-electrons.com>
213Mayuresh Janorkar <mayur@ti.com>220Mayuresh Janorkar <mayur@ti.com>
@@ -239,13 +246,13 @@ Paolo 'Blaisorblade' Giarrusso <blaisorblade@yahoo.it> · 25 unmodified lines
239Patrick Mochel <mochel@digitalimplant.org>246Patrick Mochel <mochel@digitalimplant.org>
240Paul Burton <paulburton@kernel.org> <paul.burton@imgtec.com>247Paul Burton <paulburton@kernel.org> <paul.burton@imgtec.com>
241Paul Burton <paulburton@kernel.org> <paul.burton@mips.com>248Paul Burton <paulburton@kernel.org> <paul.burton@mips.com>
249Paul E. McKenney <paulmck@kernel.org> <paul.mckenney@linaro.org>
242Paul E. McKenney <paulmck@kernel.org> <paulmck@linux.ibm.com>250Paul E. McKenney <paulmck@kernel.org> <paulmck@linux.ibm.com>
243Paul E. McKenney <paulmck@kernel.org> <paulmck@linux.vnet.ibm.com>251Paul E. McKenney <paulmck@kernel.org> <paulmck@linux.vnet.ibm.com>
244Paul E. McKenney <paulmck@kernel.org> <paul.mckenney@linaro.org>
245Paul E. McKenney <paulmck@kernel.org> <paulmck@us.ibm.com>252Paul E. McKenney <paulmck@kernel.org> <paulmck@us.ibm.com>
246Peter A Jonsson <pj@ludd.ltu.se>253Peter A Jonsson <pj@ludd.ltu.se>
247Peter Oruba <peter@oruba.de>
248Peter Oruba <peter.oruba@amd.com>254Peter Oruba <peter.oruba@amd.com>
255Peter Oruba <peter@oruba.de>
249Pratyush Anand <pratyush.anand@gmail.com> <pratyush.anand@st.com>256Pratyush Anand <pratyush.anand@gmail.com> <pratyush.anand@st.com>
250Praveen BP <praveenbp@ti.com>257Praveen BP <praveenbp@ti.com>
251Punit Agrawal <punitagrawal@gmail.com> <punit.agrawal@arm.com>258Punit Agrawal <punitagrawal@gmail.com> <punit.agrawal@arm.com>
@@ -258,23 +265,23 @@ Ralf Baechle <ralf@linux-mips.org> · 6 unmodified lines
258Ralf Wildenhues <Ralf.Wildenhues@gmx.de>265Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
259Randy Dunlap <rdunlap@infradead.org> <rdunlap@xenotime.net>266Randy Dunlap <rdunlap@infradead.org> <rdunlap@xenotime.net>
260Rémi Denis-Courmont <rdenis@simphalempin.com>267Rémi Denis-Courmont <rdenis@simphalempin.com>
261Ricardo Ribalda <ribalda@kernel.org> <ricardo.ribalda@gmail.com>
262Ricardo Ribalda <ribalda@kernel.org> <ricardo@ribalda.com>268Ricardo Ribalda <ribalda@kernel.org> <ricardo@ribalda.com>
263Ricardo Ribalda <ribalda@kernel.org> Ricardo Ribalda Delgado <ribalda@kernel.org>269Ricardo Ribalda <ribalda@kernel.org> Ricardo Ribalda Delgado <ribalda@kernel.org>
270Ricardo Ribalda <ribalda@kernel.org> <ricardo.ribalda@gmail.com>
264Ross Zwisler <zwisler@kernel.org> <ross.zwisler@linux.intel.com>271Ross Zwisler <zwisler@kernel.org> <ross.zwisler@linux.intel.com>
265Rudolf Marek <R.Marek@sh.cvut.cz>272Rudolf Marek <R.Marek@sh.cvut.cz>
266Rui Saraiva <rmps@joel.ist.utl.pt>273Rui Saraiva <rmps@joel.ist.utl.pt>
267Sachin P Sant <ssant@in.ibm.com>274Sachin P Sant <ssant@in.ibm.com>
268Sarangdhar Joshi <spjoshi@codeaurora.org>275Sakari Ailus <sakari.ailus@linux.intel.com> <sakari.ailus@iki.fi>
269Sam Ravnborg <sam@mars.ravnborg.org>276Sam Ravnborg <sam@mars.ravnborg.org>
270Santosh Shilimkar <ssantosh@kernel.org>
271Santosh Shilimkar <santosh.shilimkar@oracle.org>277Santosh Shilimkar <santosh.shilimkar@oracle.org>
278Santosh Shilimkar <ssantosh@kernel.org>
279Sarangdhar Joshi <spjoshi@codeaurora.org>
272Sascha Hauer <s.hauer@pengutronix.de>280Sascha Hauer <s.hauer@pengutronix.de>
273S.Çağlar Onur <caglar@pardus.org.tr>281S.Çağlar Onur <caglar@pardus.org.tr>
274Sakari Ailus <sakari.ailus@linux.intel.com> <sakari.ailus@iki.fi>
275Sean Nyekjaer <sean@geanix.com> <sean.nyekjaer@prevas.dk>282Sean Nyekjaer <sean@geanix.com> <sean.nyekjaer@prevas.dk>
276Sebastian Reichel <sre@kernel.org> <sre@debian.org>
277Sebastian Reichel <sre@kernel.org> <sebastian.reichel@collabora.co.uk>283Sebastian Reichel <sre@kernel.org> <sebastian.reichel@collabora.co.uk>
284Sebastian Reichel <sre@kernel.org> <sre@debian.org>
278Sedat Dilek <sedat.dilek@gmail.com> <sedat.dilek@credativ.de>285Sedat Dilek <sedat.dilek@gmail.com> <sedat.dilek@credativ.de>
279Shiraz Hashim <shiraz.linux.kernel@gmail.com> <shiraz.hashim@st.com>286Shiraz Hashim <shiraz.linux.kernel@gmail.com> <shiraz.hashim@st.com>
280Shuah Khan <shuah@kernel.org> <shuahkhan@gmail.com>287Shuah Khan <shuah@kernel.org> <shuahkhan@gmail.com>
@@ -285,18 +292,21 @@ Simon Arlott <simon@octiron.net> <simon@fire.lp0.eu> · 4 unmodified lines
285Simon Kelley <simon@thekelleys.org.uk>292Simon Kelley <simon@thekelleys.org.uk>
286Stéphane Witzmann <stephane.witzmann@ubpmes.univ-bpclermont.fr>293Stéphane Witzmann <stephane.witzmann@ubpmes.univ-bpclermont.fr>
287Stephen Hemminger <shemminger@osdl.org>294Stephen Hemminger <shemminger@osdl.org>
295Steve Wise <larrystevenwise@gmail.com> <swise@chelsio.com>
296Steve Wise <larrystevenwise@gmail.com> <swise@opengridcomputing.com>
288Subash Abhinov Kasiviswanathan <subashab@codeaurora.org>297Subash Abhinov Kasiviswanathan <subashab@codeaurora.org>
289Subhash Jadavani <subhashj@codeaurora.org>298Subhash Jadavani <subhashj@codeaurora.org>
290Sudeep Holla <sudeep.holla@arm.com> Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>299Sudeep Holla <sudeep.holla@arm.com> Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
291Sumit Semwal <sumit.semwal@ti.com>300Sumit Semwal <sumit.semwal@ti.com>
301Takashi YOSHII <takashi.yoshii.zj@renesas.com>
292Tejun Heo <htejun@gmail.com>302Tejun Heo <htejun@gmail.com>
293Thomas Graf <tgraf@suug.ch>303Thomas Graf <tgraf@suug.ch>
294Thomas Pedersen <twp@codeaurora.org>304Thomas Pedersen <twp@codeaurora.org>
295Tiezhu Yang <yangtiezhu@loongson.cn> <kernelpatch@126.com>305Tiezhu Yang <yangtiezhu@loongson.cn> <kernelpatch@126.com>
296Todor Tomov <todor.too@gmail.com> <todor.tomov@linaro.org>306Todor Tomov <todor.too@gmail.com> <todor.tomov@linaro.org>
297Tony Luck <tony.luck@intel.com>307Tony Luck <tony.luck@intel.com>
298TripleX Chung <xxx.phy@gmail.com> <zhongyu@18mail.cn>
299TripleX Chung <xxx.phy@gmail.com> <triplex@zh-kernel.org>308TripleX Chung <xxx.phy@gmail.com> <triplex@zh-kernel.org>
309TripleX Chung <xxx.phy@gmail.com> <zhongyu@18mail.cn>
300Tsuneo Yoshioka <Tsuneo.Yoshioka@f-secure.com>310Tsuneo Yoshioka <Tsuneo.Yoshioka@f-secure.com>
301Uwe Kleine-König <ukleinek@informatik.uni-freiburg.de>311Uwe Kleine-König <ukleinek@informatik.uni-freiburg.de>
302Uwe Kleine-König <ukl@pengutronix.de>312Uwe Kleine-König <ukl@pengutronix.de>
@@ -305,22 +315,16 @@ Valdis Kletnieks <Valdis.Kletnieks@vt.edu> · 2 unmodified lines
305Vinod Koul <vkoul@kernel.org> <vinod.koul@intel.com>315Vinod Koul <vkoul@kernel.org> <vinod.koul@intel.com>
306Vinod Koul <vkoul@kernel.org> <vinod.koul@linux.intel.com>316Vinod Koul <vkoul@kernel.org> <vinod.koul@linux.intel.com>
307Vinod Koul <vkoul@kernel.org> <vkoul@infradead.org>317Vinod Koul <vkoul@kernel.org> <vkoul@infradead.org>
318Viresh Kumar <vireshk@kernel.org> <viresh.kumar2@arm.com>
308Viresh Kumar <vireshk@kernel.org> <viresh.kumar@st.com>319Viresh Kumar <vireshk@kernel.org> <viresh.kumar@st.com>
309Viresh Kumar <vireshk@kernel.org> <viresh.linux@gmail.com>320Viresh Kumar <vireshk@kernel.org> <viresh.linux@gmail.com>
310Viresh Kumar <vireshk@kernel.org> <viresh.kumar2@arm.com>
311Vivien Didelot <vivien.didelot@gmail.com> <vivien.didelot@savoirfairelinux.com>321Vivien Didelot <vivien.didelot@gmail.com> <vivien.didelot@savoirfairelinux.com>
312Vlad Dogaru <ddvlad@gmail.com> <vlad.dogaru@intel.com>322Vlad Dogaru <ddvlad@gmail.com> <vlad.dogaru@intel.com>
313Vladimir Davydov <vdavydov.dev@gmail.com> <vdavydov@virtuozzo.com>
314Vladimir Davydov <vdavydov.dev@gmail.com> <vdavydov@parallels.com>323Vladimir Davydov <vdavydov.dev@gmail.com> <vdavydov@parallels.com>
315Takashi YOSHII <takashi.yoshii.zj@renesas.com>324Vladimir Davydov <vdavydov.dev@gmail.com> <vdavydov@virtuozzo.com>
325WeiXiong Liao <gmpy.liaowx@gmail.com> <liaoweixiong@allwinnertech.com>
316Will Deacon <will@kernel.org> <will.deacon@arm.com>326Will Deacon <will@kernel.org> <will.deacon@arm.com>
317Wolfram Sang <wsa@kernel.org> <wsa@the-dreams.de>
318Wolfram Sang <wsa@kernel.org> <w.sang@pengutronix.de>327Wolfram Sang <wsa@kernel.org> <w.sang@pengutronix.de>
328Wolfram Sang <wsa@kernel.org> <wsa@the-dreams.de>
319Yakir Yang <kuankuan.y@gmail.com> <ykk@rock-chips.com>329Yakir Yang <kuankuan.y@gmail.com> <ykk@rock-chips.com>
320Yusuke Goda <goda.yusuke@renesas.com>330Yusuke Goda <goda.yusuke@renesas.com>
321Gustavo Padovan <gustavo@las.ic.unicamp.br>
322Gustavo Padovan <padovan@profusion.mobi>
323Changbin Du <changbin.du@intel.com> <changbin.du@intel.com>
324Changbin Du <changbin.du@intel.com> <changbin.du@gmail.com>
325Steve Wise <larrystevenwise@gmail.com> <swise@chelsio.com>
326Steve Wise <larrystevenwise@gmail.com> <swise@opengridcomputing.com>
Documentation/ABI/testing/sysfs-bus-event_source-devices-hv_24x7+1−1
@@ -43,7 +43,7 @@ Description: read only · 42 unmodified lines
43 This sysfs interface exposes the number of cores per chip43 This sysfs interface exposes the number of cores per chip
44 present in the system.44 present in the system.
45 45
46What: /sys/devices/hv_24x7/interface/cpumask46What: /sys/devices/hv_24x7/cpumask
47Date: July 202047Date: July 2020
48Contact: Linux on PowerPC Developer List <linuxppc-dev@lists.ozlabs.org>48Contact: Linux on PowerPC Developer List <linuxppc-dev@lists.ozlabs.org>
49Description: read only49Description: read only
Documentation/RCU/lockdep.rst+1−1
@@ -49,7 +49,7 @@ checking of rcu_dereference() primitives: · 48 unmodified lines
49 is invoked by both RCU-sched readers and updaters.49 is invoked by both RCU-sched readers and updaters.
50 srcu_dereference_check(p, c):50 srcu_dereference_check(p, c):
51 Use explicit check expression "c" along with51 Use explicit check expression "c" along with
52 srcu_read_lock_held()(). This is useful in code that52 srcu_read_lock_held(). This is useful in code that
53 is invoked by both SRCU readers and updaters.53 is invoked by both SRCU readers and updaters.
54 rcu_dereference_raw(p):54 rcu_dereference_raw(p):
55 Don't check. (Use sparingly, if at all.)55 Don't check. (Use sparingly, if at all.)
Documentation/admin-guide/devices.txt+1−1
@@ -1662,7 +1662,7 @@ · 1661 unmodified lines
1662 1662
1663 98 block User-mode virtual block device1663 98 block User-mode virtual block device
1664 0 = /dev/ubda First user-mode block device1664 0 = /dev/ubda First user-mode block device
1665 16 = /dev/udbb Second user-mode block device1665 16 = /dev/ubdb Second user-mode block device
1666 ...1666 ...
1667 1667
1668 Partitions are handled in the same way as for IDE1668 Partitions are handled in the same way as for IDE
Documentation/admin-guide/ext4.rst+13−10
@@ -489,6 +489,9 @@ Files in /sys/fs/ext4/<devname>: · 488 unmodified lines
489 multiple of this tuning parameter if the stripe size is not set in the489 multiple of this tuning parameter if the stripe size is not set in the
490 ext4 superblock490 ext4 superblock
491 491
492 mb_max_inode_prealloc
493 The maximum length of per-inode ext4_prealloc_space list.
494
492 mb_max_to_scan495 mb_max_to_scan
493 The maximum number of extents the multiblock allocator will search to496 The maximum number of extents the multiblock allocator will search to
494 find the best extent.497 find the best extent.
@@ -529,21 +532,21 @@ Files in /sys/fs/ext4/<devname>: · 34 unmodified lines
529Ioctls532Ioctls
530======533======
531 534
532There is some Ext4 specific functionality which can be accessed by applications535Ext4 implements various ioctls which can be used by applications to access
533through the system call interfaces. The list of all Ext4 specific ioctls are536ext4-specific functionality. An incomplete list of these ioctls is shown in the
534shown in the table below.537table below. This list includes truly ext4-specific ioctls (``EXT4_IOC_*``) as
538well as ioctls that may have been ext4-specific originally but are now supported
539by some other filesystem(s) too (``FS_IOC_*``).
535 540
536Table of Ext4 specific ioctls541Table of Ext4 ioctls
537 542
538 EXT4_IOC_GETFLAGS543 FS_IOC_GETFLAGS
539 Get additional attributes associated with inode. The ioctl argument is544 Get additional attributes associated with inode. The ioctl argument is
540 an integer bitfield, with bit values described in ext4.h. This ioctl is545 an integer bitfield, with bit values described in ext4.h.
541 an alias for FS_IOC_GETFLAGS.
542 546
543 EXT4_IOC_SETFLAGS547 FS_IOC_SETFLAGS
544 Set additional attributes associated with inode. The ioctl argument is548 Set additional attributes associated with inode. The ioctl argument is
545 an integer bitfield, with bit values described in ext4.h. This ioctl is549 an integer bitfield, with bit values described in ext4.h.
546 an alias for FS_IOC_SETFLAGS.
547 550
548 EXT4_IOC_GETVERSION, EXT4_IOC_GETVERSION_OLD551 EXT4_IOC_GETVERSION, EXT4_IOC_GETVERSION_OLD
549 Get the inode i_generation number stored for each inode. The552 Get the inode i_generation number stored for each inode. The
Documentation/admin-guide/kernel-parameters.txt+1−4
@@ -1233,8 +1233,7 @@ · 1232 unmodified lines
1233 efi= [EFI]1233 efi= [EFI]
1234 Format: { "debug", "disable_early_pci_dma",1234 Format: { "debug", "disable_early_pci_dma",
1235 "nochunk", "noruntime", "nosoftreserve",1235 "nochunk", "noruntime", "nosoftreserve",
1236 "novamap", "no_disable_early_pci_dma",1236 "novamap", "no_disable_early_pci_dma" }
1237 "old_map" }
1238 debug: enable misc debug output.1237 debug: enable misc debug output.
1239 disable_early_pci_dma: disable the busmaster bit on all1238 disable_early_pci_dma: disable the busmaster bit on all
1240 PCI bridges while in the EFI boot stub.1239 PCI bridges while in the EFI boot stub.
@@ -1251,8 +1250,6 @@ · 10 unmodified lines
1251 novamap: do not call SetVirtualAddressMap().1250 novamap: do not call SetVirtualAddressMap().
1252 no_disable_early_pci_dma: Leave the busmaster bit set1251 no_disable_early_pci_dma: Leave the busmaster bit set
1253 on all PCI bridges while in the EFI boot stub1252 on all PCI bridges while in the EFI boot stub
1254 old_map [X86-64]: switch to the old ioremap-based EFI
1255 runtime services mapping. [Needs CONFIG_X86_UV=y]
1256 1253
1257 efi_no_storage_paranoia [EFI; X86]1254 efi_no_storage_paranoia [EFI; X86]
1258 Using this parameter you can use more than 50% of1255 Using this parameter you can use more than 50% of
Documentation/admin-guide/laptops/thinkpad-acpi.rst+1−1
@@ -1434,7 +1434,7 @@ on the feature, restricting the viewing angles. · 1433 unmodified lines
1434 1434
1435 1435
1436DYTC Lapmode sensor1436DYTC Lapmode sensor
1437------------------1437-------------------
1438 1438
1439sysfs: dytc_lapmode1439sysfs: dytc_lapmode
1440 1440
Documentation/admin-guide/pm/intel_pstate.rst+5−3
@@ -123,7 +123,9 @@ Energy-Performance Bias (EPB) knob (otherwise), which means that the processor's · 122 unmodified lines
123internal P-state selection logic is expected to focus entirely on performance.123internal P-state selection logic is expected to focus entirely on performance.
124 124
125This will override the EPP/EPB setting coming from the ``sysfs`` interface125This will override the EPP/EPB setting coming from the ``sysfs`` interface
126(see `Energy vs Performance Hints`_ below).126(see `Energy vs Performance Hints`_ below). Moreover, any attempts to change
127the EPP/EPB to a value different from 0 ("performance") via ``sysfs`` in this
128configuration will be rejected.
127 129
128Also, in this configuration the range of P-states available to the processor's130Also, in this configuration the range of P-states available to the processor's
129internal P-state selection logic is always restricted to the upper boundary131internal P-state selection logic is always restricted to the upper boundary
@@ -564,8 +566,8 @@ Energy-Performance Preference (EPP) knob (if supported) or its · 434 unmodified lines
564Energy-Performance Bias (EPB) knob. It is also possible to write a positive566Energy-Performance Bias (EPB) knob. It is also possible to write a positive
565integer value between 0 to 255, if the EPP feature is present. If the EPP567integer value between 0 to 255, if the EPP feature is present. If the EPP
566feature is not present, writing integer value to this attribute is not568feature is not present, writing integer value to this attribute is not
567supported. In this case, user can use569supported. In this case, user can use the
568 "/sys/devices/system/cpu/cpu*/power/energy_perf_bias" interface.570"/sys/devices/system/cpu/cpu*/power/energy_perf_bias" interface.
569 571
570[Note that tasks may by migrated from one CPU to another by the scheduler's572[Note that tasks may by migrated from one CPU to another by the scheduler's
571load-balancing algorithm and if different energy vs performance hints are573load-balancing algorithm and if different energy vs performance hints are
Documentation/bpf/index.rst+7−0
@@ -36,6 +36,12 @@ Two sets of Questions and Answers (Q&A) are maintained. · 35 unmodified lines
36 bpf_devel_QA36 bpf_devel_QA
37 37
38 38
39Helper functions
40================
41
42* `bpf-helpers(7)`_ maintains a list of helpers available to eBPF programs.
43
44
39Program types45Program types
40=============46=============
41 47
@@ -79,4 +85,5 @@ Other · 37 unmodified lines
79.. _networking-filter: ../networking/filter.rst85.. _networking-filter: ../networking/filter.rst
80.. _man-pages: https://www.kernel.org/doc/man-pages/86.. _man-pages: https://www.kernel.org/doc/man-pages/
81.. _bpf(2): https://man7.org/linux/man-pages/man2/bpf.2.html87.. _bpf(2): https://man7.org/linux/man-pages/man2/bpf.2.html
88.. _bpf-helpers(7): https://man7.org/linux/man-pages/man7/bpf-helpers.7.html
82.. _BPF and XDP Reference Guide: https://docs.cilium.io/en/latest/bpf/89.. _BPF and XDP Reference Guide: https://docs.cilium.io/en/latest/bpf/
Documentation/devicetree/bindings/clock/imx23-clock.yaml+1−1
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# · 6 unmodified lines
7title: Clock bindings for Freescale i.MX237title: Clock bindings for Freescale i.MX23
8 8
9maintainers:9maintainers:
10 - Shawn Guo <shawn.guo@linaro.org>10 - Shawn Guo <shawnguo@kernel.org>
11 11
12description: |12description: |
13 The clock consumer should specify the desired clock by having the clock13 The clock consumer should specify the desired clock by having the clock
Documentation/devicetree/bindings/clock/imx28-clock.yaml+1−1
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# · 6 unmodified lines
7title: Clock bindings for Freescale i.MX287title: Clock bindings for Freescale i.MX28
8 8
9maintainers:9maintainers:
10 - Shawn Guo <shawn.guo@linaro.org>10 - Shawn Guo <shawnguo@kernel.org>
11 11
12description: |12description: |
13 The clock consumer should specify the desired clock by having the clock13 The clock consumer should specify the desired clock by having the clock
Documentation/devicetree/bindings/gpio/gpio-mxs.yaml+1−1
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# · 6 unmodified lines
7title: Freescale MXS GPIO controller7title: Freescale MXS GPIO controller
8 8
9maintainers:9maintainers:
10 - Shawn Guo <shawn.guo@linaro.org>10 - Shawn Guo <shawnguo@kernel.org>
11 - Anson Huang <Anson.Huang@nxp.com>11 - Anson Huang <Anson.Huang@nxp.com>
12 12
13description: |13description: |
Documentation/devicetree/bindings/i2c/i2c-mxs.yaml+1−1
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# · 6 unmodified lines
7title: Freescale MXS Inter IC (I2C) Controller7title: Freescale MXS Inter IC (I2C) Controller
8 8
9maintainers:9maintainers:
10 - Shawn Guo <shawn.guo@linaro.org>10 - Shawn Guo <shawnguo@kernel.org>
11 11
12properties:12properties:
13 compatible:13 compatible:
Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.txt+0−66
@@ -1,66 +0,0 @@
1Texas Instruments K3 Interrupt Aggregator
2=========================================
3
4The Interrupt Aggregator (INTA) provides a centralized machine
5which handles the termination of system events to that they can
6be coherently processed by the host(s) in the system. A maximum
7of 64 events can be mapped to a single interrupt.
8
9
10 Interrupt Aggregator
11 +-----------------------------------------+
12 | Intmap VINT |
13 | +--------------+ +------------+ |
14 m ------>| | vint | bit | | 0 |.....|63| vint0 |
15 . | +--------------+ +------------+ | +------+
16 . | . . | | HOST |
17Globalevents ------>| . . |------>| IRQ |
18 . | . . | | CTRL |
19 . | . . | +------+
20 n ------>| +--------------+ +------------+ |
21 | | vint | bit | | 0 |.....|63| vintx |
22 | +--------------+ +------------+ |
23 | |
24 +-----------------------------------------+
25
26Configuration of these Intmap registers that maps global events to vint is done
27by a system controller (like the Device Memory and Security Controller on K3
28AM654 SoC). Driver should request the system controller to get the range
29of global events and vints assigned to the requesting host. Management
30of these requested resources should be handled by driver and requests
31system controller to map specific global event to vint, bit pair.
32
33Communication between the host processor running an OS and the system
34controller happens through a protocol called TI System Control Interface
35(TISCI protocol). For more details refer:
36Documentation/devicetree/bindings/arm/keystone/ti,sci.txt
37
38TISCI Interrupt Aggregator Node:
39-------------------------------
40- compatible: Must be "ti,sci-inta".
41- reg: Should contain registers location and length.
42- interrupt-controller: Identifies the node as an interrupt controller
43- msi-controller: Identifies the node as an MSI controller.
44- interrupt-parent: phandle of irq parent.
45- ti,sci: Phandle to TI-SCI compatible System controller node.
46- ti,sci-dev-id: TISCI device ID of the Interrupt Aggregator.
47- ti,sci-rm-range-vint: Array of TISCI subtype ids representing vints(inta
48 outputs) range within this INTA, assigned to the
49 requesting host context.
50- ti,sci-rm-range-global-event: Array of TISCI subtype ids representing the
51 global events range reaching this IA and are assigned
52 to the requesting host context.
53
54Example:
55--------
56main_udmass_inta: interrupt-controller@33d00000 {
57 compatible = "ti,sci-inta";
58 reg = <0x0 0x33d00000 0x0 0x100000>;
59 interrupt-controller;
60 msi-controller;
61 interrupt-parent = <&main_navss_intr>;
62 ti,sci = <&dmsc>;
63 ti,sci-dev-id = <179>;
64 ti,sci-rm-range-vint = <0x0>;
65 ti,sci-rm-range-global-event = <0x1>;
66};
Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.yaml+98−0
@@ -0,0 +1,98 @@
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/interrupt-controller/ti,sci-inta.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Texas Instruments K3 Interrupt Aggregator
8
9maintainers:
10 - Lokesh Vutla <lokeshvutla@ti.com>
11
12allOf:
13 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
14
15description: |
16 The Interrupt Aggregator (INTA) provides a centralized machine
17 which handles the termination of system events to that they can
18 be coherently processed by the host(s) in the system. A maximum
19 of 64 events can be mapped to a single interrupt.
20
21 Interrupt Aggregator
22 +-----------------------------------------+
23 | Intmap VINT |
24 | +--------------+ +------------+ |
25 m ------>| | vint | bit | | 0 |.....|63| vint0 |
26 . | +--------------+ +------------+ | +------+
27 . | . . | | HOST |
28 Globalevents ------>| . . |----->| IRQ |
29 . | . . | | CTRL |
30 . | . . | +------+
31 n ------>| +--------------+ +------------+ |
32 | | vint | bit | | 0 |.....|63| vintx |
33 | +--------------+ +------------+ |
34 | |
35 +-----------------------------------------+
36
37 Configuration of these Intmap registers that maps global events to vint is
38 done by a system controller (like the Device Memory and Security Controller
39 on AM654 SoC). Driver should request the system controller to get the range
40 of global events and vints assigned to the requesting host. Management
41 of these requested resources should be handled by driver and requests
42 system controller to map specific global event to vint, bit pair.
43
44 Communication between the host processor running an OS and the system
45 controller happens through a protocol called TI System Control Interface
46 (TISCI protocol).
47
48properties:
49 compatible:
50 const: ti,sci-inta
51
52 reg:
53 maxItems: 1
54
55 interrupt-controller: true
56
57 msi-controller: true
58
59 ti,interrupt-ranges:
60 $ref: /schemas/types.yaml#/definitions/uint32-matrix
61 description: |
62 Interrupt ranges that converts the INTA output hw irq numbers
63 to parents's input interrupt numbers.
64 items:
65 items:
66 - description: |
67 "output_irq" specifies the base for inta output irq
68 - description: |
69 "parent's input irq" specifies the base for parent irq
70 - description: |
71 "limit" specifies the limit for translation
72
73required:
74 - compatible
75 - reg
76 - interrupt-controller
77 - msi-controller
78 - ti,sci
79 - ti,sci-dev-id
80 - ti,interrupt-ranges
81
82examples:
83 - |
84 bus {
85 #address-cells = <2>;
86 #size-cells = <2>;
87
88 main_udmass_inta: msi-controller@33d00000 {
89 compatible = "ti,sci-inta";
90 reg = <0x0 0x33d00000 0x0 0x100000>;
91 interrupt-controller;
92 msi-controller;
93 interrupt-parent = <&main_navss_intr>;
94 ti,sci = <&dmsc>;
95 ti,sci-dev-id = <179>;
96 ti,interrupt-ranges = <0 0 256>;
97 };
98 };
Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.txt+0−82
@@ -1,82 +0,0 @@
1Texas Instruments K3 Interrupt Router
2=====================================
3
4The Interrupt Router (INTR) module provides a mechanism to mux M
5interrupt inputs to N interrupt outputs, where all M inputs are selectable
6to be driven per N output. An Interrupt Router can either handle edge triggered
7or level triggered interrupts and that is fixed in hardware.
8
9 Interrupt Router
10 +----------------------+
11 | Inputs Outputs |
12 +-------+ | +------+ +-----+ |
13 | GPIO |----------->| | irq0 | | 0 | | Host IRQ
14 +-------+ | +------+ +-----+ | controller
15 | . . | +-------+
16 +-------+ | . . |----->| IRQ |
17 | INTA |----------->| . . | +-------+
18 +-------+ | . +-----+ |
19 | +------+ | N | |
20 | | irqM | +-----+ |
21 | +------+ |
22 | |
23 +----------------------+
24
25There is one register per output (MUXCNTL_N) that controls the selection.
26Configuration of these MUXCNTL_N registers is done by a system controller
27(like the Device Memory and Security Controller on K3 AM654 SoC). System
28controller will keep track of the used and unused registers within the Router.
29Driver should request the system controller to get the range of GIC IRQs
30assigned to the requesting hosts. It is the drivers responsibility to keep
31track of Host IRQs.
32
33Communication between the host processor running an OS and the system
34controller happens through a protocol called TI System Control Interface
35(TISCI protocol). For more details refer:
36Documentation/devicetree/bindings/arm/keystone/ti,sci.txt
37
38TISCI Interrupt Router Node:
39----------------------------
40Required Properties:
41- compatible: Must be "ti,sci-intr".
42- ti,intr-trigger-type: Should be one of the following:
43 1: If intr supports edge triggered interrupts.
44 4: If intr supports level triggered interrupts.
45- interrupt-controller: Identifies the node as an interrupt controller
46- #interrupt-cells: Specifies the number of cells needed to encode an
47 interrupt source. The value should be 2.
48 First cell should contain the TISCI device ID of source
49 Second cell should contain the interrupt source offset
50 within the device.
51- ti,sci: Phandle to TI-SCI compatible System controller node.
52- ti,sci-dst-id: TISCI device ID of the destination IRQ controller.
53- ti,sci-rm-range-girq: Array of TISCI subtype ids representing the host irqs
54 assigned to this interrupt router. Each subtype id
55 corresponds to a range of host irqs.
56
57For more details on TISCI IRQ resource management refer:
58https://downloads.ti.com/tisci/esd/latest/2_tisci_msgs/rm/rm_irq.html
59
60Example:
61--------
62The following example demonstrates both interrupt router node and the consumer
63node(main gpio) on the AM654 SoC:
64
65main_intr: interrupt-controller0 {
66 compatible = "ti,sci-intr";
67 ti,intr-trigger-type = <1>;
68 interrupt-controller;
69 interrupt-parent = <&gic500>;
70 #interrupt-cells = <2>;
71 ti,sci = <&dmsc>;
72 ti,sci-dst-id = <56>;
73 ti,sci-rm-range-girq = <0x1>;
74};
75
76main_gpio0: gpio@600000 {
77 ...
78 interrupt-parent = <&main_intr>;
79 interrupts = <57 256>, <57 257>, <57 258>,
80 <57 259>, <57 260>, <57 261>;
81 ...
82};
Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.yaml+102−0
@@ -0,0 +1,102 @@
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/interrupt-controller/ti,sci-intr.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Texas Instruments K3 Interrupt Router
8
9maintainers:
10 - Lokesh Vutla <lokeshvutla@ti.com>
11
12allOf:
13 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
14
15description: |
16 The Interrupt Router (INTR) module provides a mechanism to mux M
17 interrupt inputs to N interrupt outputs, where all M inputs are selectable
18 to be driven per N output. An Interrupt Router can either handle edge
19 triggered or level triggered interrupts and that is fixed in hardware.
20
21 Interrupt Router
22 +----------------------+
23 | Inputs Outputs |
24 +-------+ | +------+ +-----+ |
25 | GPIO |----------->| | irq0 | | 0 | | Host IRQ
26 +-------+ | +------+ +-----+ | controller
27 | . . | +-------+
28 +-------+ | . . |----->| IRQ |
29 | INTA |----------->| . . | +-------+
30 +-------+ | . +-----+ |
31 | +------+ | N | |
32 | | irqM | +-----+ |
33 | +------+ |
34 | |
35 +----------------------+
36
37 There is one register per output (MUXCNTL_N) that controls the selection.
38 Configuration of these MUXCNTL_N registers is done by a system controller
39 (like the Device Memory and Security Controller on K3 AM654 SoC). System
40 controller will keep track of the used and unused registers within the Router.
41 Driver should request the system controller to get the range of GIC IRQs
42 assigned to the requesting hosts. It is the drivers responsibility to keep
43 track of Host IRQs.
44
45 Communication between the host processor running an OS and the system
46 controller happens through a protocol called TI System Control Interface
47 (TISCI protocol).
48
49properties:
50 compatible:
51 const: ti,sci-intr
52
53 ti,intr-trigger-type:
54 $ref: /schemas/types.yaml#/definitions/uint32
55 enum: [1, 4]
56 description: |
57 Should be one of the following.
58 1 = If intr supports edge triggered interrupts.
59 4 = If intr supports level triggered interrupts.
60
61 interrupt-controller: true
62
63 '#interrupt-cells':
64 const: 1
65 description: |
66 The 1st cell should contain interrupt router input hw number.
67
68 ti,interrupt-ranges:
69 $ref: /schemas/types.yaml#/definitions/uint32-matrix
70 description: |
71 Interrupt ranges that converts the INTR output hw irq numbers
72 to parents's input interrupt numbers.
73 items:
74 items:
75 - description: |
76 "output_irq" specifies the base for intr output irq
77 - description: |
78 "parent's input irq" specifies the base for parent irq
79 - description: |
80 "limit" specifies the limit for translation
81
82required:
83 - compatible
84 - ti,intr-trigger-type
85 - interrupt-controller
86 - '#interrupt-cells'
87 - ti,sci
88 - ti,sci-dev-id
89 - ti,interrupt-ranges
90
91examples:
92 - |
93 main_gpio_intr: interrupt-controller0 {
94 compatible = "ti,sci-intr";
95 ti,intr-trigger-type = <1>;
96 interrupt-controller;
97 interrupt-parent = <&gic500>;
98 #interrupt-cells = <1>;
99 ti,sci = <&dmsc>;
100 ti,sci-dev-id = <131>;
101 ti,interrupt-ranges = <0 360 32>;
102 };
Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml+7−3
@@ -30,9 +30,13 @@ allOf: · 29 unmodified lines
30 then:30 then:
31 properties:31 properties:
32 clock-output-names:32 clock-output-names:
33 items:33 oneOf:
34 - const: clk_out_sd034 - items:
35 - const: clk_in_sd035 - const: clk_out_sd0
36 - const: clk_in_sd0
37 - items:
38 - const: clk_out_sd1
39 - const: clk_in_sd1
36 40
37properties:41properties:
38 compatible:42 compatible:
Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml+1−1
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# · 6 unmodified lines
7title: Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX7title: Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX
8 8
9maintainers:9maintainers:
10 - Shawn Guo <shawn.guo@linaro.org>10 - Shawn Guo <shawnguo@kernel.org>
11 11
12allOf:12allOf:
13 - $ref: "mmc-controller.yaml"13 - $ref: "mmc-controller.yaml"
Documentation/devicetree/bindings/mmc/mtk-sd.txt+2−0
@@ -50,6 +50,8 @@ Optional properties: · 49 unmodified lines
50 error caused by stop clock(fifo full)50 error caused by stop clock(fifo full)
51 Valid range = [0:0x7]. if not present, default value is 0.51 Valid range = [0:0x7]. if not present, default value is 0.
52 applied to compatible "mediatek,mt2701-mmc".52 applied to compatible "mediatek,mt2701-mmc".
53- resets: Phandle and reset specifier pair to softreset line of MSDC IP.
54- reset-names: Should be "hrst".
53 55
54Examples:56Examples:
55mmc0: mmc@11230000 {57mmc0: mmc@11230000 {
Documentation/devicetree/bindings/mmc/mxs-mmc.yaml+1−1
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# · 6 unmodified lines
7title: Freescale MXS MMC controller7title: Freescale MXS MMC controller
8 8
9maintainers:9maintainers:
10 - Shawn Guo <shawn.guo@linaro.org>10 - Shawn Guo <shawnguo@kernel.org>
11 11
12description: |12description: |
13 The Freescale MXS Synchronous Serial Ports (SSP) can act as a MMC controller13 The Freescale MXS Synchronous Serial Ports (SSP) can act as a MMC controller
Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt+29−3
@@ -15,8 +15,15 @@ Required properties: · 14 unmodified lines
15 - "nvidia,tegra210-sdhci": for Tegra21015 - "nvidia,tegra210-sdhci": for Tegra210
16 - "nvidia,tegra186-sdhci": for Tegra18616 - "nvidia,tegra186-sdhci": for Tegra186
17 - "nvidia,tegra194-sdhci": for Tegra19417 - "nvidia,tegra194-sdhci": for Tegra194
18- clocks : Must contain one entry, for the module clock.18- clocks: For Tegra210, Tegra186 and Tegra194 must contain two entries.
19 See ../clocks/clock-bindings.txt for details.19 One for the module clock and one for the timeout clock.
20 For all other Tegra devices, must contain a single entry for
21 the module clock. See ../clocks/clock-bindings.txt for details.
22- clock-names: For Tegra210, Tegra186 and Tegra194 must contain the
23 strings 'sdhci' and 'tmclk' to represent the module and
24 the timeout clocks, respectively.
25 For all other Tegra devices must contain the string 'sdhci'
26 to represent the module clock.
20- resets : Must contain an entry for each entry in reset-names.27- resets : Must contain an entry for each entry in reset-names.
21 See ../reset/reset.txt for details.28 See ../reset/reset.txt for details.
22- reset-names : Must include the following entries:29- reset-names : Must include the following entries:
@@ -99,7 +106,7 @@ Optional properties for Tegra210, Tegra186 and Tegra194: · 76 unmodified lines
99 106
100Example:107Example:
101sdhci@700b0000 {108sdhci@700b0000 {
102 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";109 compatible = "nvidia,tegra124-sdhci";
103 reg = <0x0 0x700b0000 0x0 0x200>;110 reg = <0x0 0x700b0000 0x0 0x200>;
104 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;111 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
105 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>;112 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>;
@@ -115,3 +122,22 @@ sdhci@700b0000 { · 9 unmodified lines
115 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;122 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
116 status = "disabled";123 status = "disabled";
117};124};
125
126sdhci@700b0000 {
127 compatible = "nvidia,tegra210-sdhci";
128 reg = <0x0 0x700b0000 0x0 0x200>;
129 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
130 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>,
131 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
132 clock-names = "sdhci", "tmclk";
133 resets = <&tegra_car 14>;
134 reset-names = "sdhci";
135 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
136 pinctrl-0 = <&sdmmc1_3v3>;
137 pinctrl-1 = <&sdmmc1_1v8>;
138 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
139 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
140 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
141 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
142 status = "disabled";
143};
Documentation/devicetree/bindings/net/dsa/dsa.txt+1−1
@@ -1,4 +1,4 @@
1Distributed Switch Architecture Device Tree Bindings1Distributed Switch Architecture Device Tree Bindings
2----------------------------------------------------2----------------------------------------------------
3 3
4See Documentation/devicetree/bindings/net/dsa/dsa.yaml for the documenation.4See Documentation/devicetree/bindings/net/dsa/dsa.yaml for the documentation.
Documentation/devicetree/bindings/net/ethernet-controller.yaml+2−1
@@ -54,7 +54,8 @@ properties: · 53 unmodified lines
54 54
55 phy-connection-type:55 phy-connection-type:
56 description:56 description:
57 Operation mode of the PHY interface57 Specifies interface type between the Ethernet device and a physical
58 layer (PHY) device.
58 enum:59 enum:
59 # There is not a standard bus between the MAC and the PHY,60 # There is not a standard bus between the MAC and the PHY,
60 # something proprietary is being used to embed the PHY in the61 # something proprietary is being used to embed the PHY in the
Documentation/devicetree/bindings/net/renesas,ether.yaml+15−7
@@ -59,9 +59,15 @@ properties: · 58 unmodified lines
59 clocks:59 clocks:
60 maxItems: 160 maxItems: 1
61 61
62 pinctrl-0: true62 power-domains:
63 maxItems: 1
64
65 resets:
66 maxItems: 1
63 67
64 pinctrl-names: true68 phy-mode: true
69
70 phy-handle: true
65 71
66 renesas,no-ether-link:72 renesas,no-ether-link:
67 type: boolean73 type: boolean
@@ -74,6 +80,11 @@ properties: · 6 unmodified lines
74 specify when the Ether LINK signal is active-low instead of normal80 specify when the Ether LINK signal is active-low instead of normal
75 active-high81 active-high
76 82
83patternProperties:
84 "^ethernet-phy@[0-9a-f]$":
85 type: object
86 $ref: ethernet-phy.yaml#
87
77required:88required:
78 - compatible89 - compatible
79 - reg90 - reg
@@ -83,7 +94,8 @@ required: · 3 unmodified lines
83 - '#address-cells'94 - '#address-cells'
84 - '#size-cells'95 - '#size-cells'
85 - clocks96 - clocks
86 - pinctrl-097
98additionalProperties: false
87 99
88examples:100examples:
89 # Lager board101 # Lager board
@@ -99,8 +111,6 @@ examples: · 9 unmodified lines
99 clocks = <&mstp8_clks R8A7790_CLK_ETHER>;111 clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
100 phy-mode = "rmii";112 phy-mode = "rmii";
101 phy-handle = <&phy1>;113 phy-handle = <&phy1>;
102 pinctrl-0 = <&ether_pins>;
103 pinctrl-names = "default";
104 renesas,ether-link-active-low;114 renesas,ether-link-active-low;
105 #address-cells = <1>;115 #address-cells = <1>;
106 #size-cells = <0>;116 #size-cells = <0>;
@@ -109,7 +119,5 @@ examples: · 2 unmodified lines
109 reg = <1>;119 reg = <1>;
110 interrupt-parent = <&irqc0>;120 interrupt-parent = <&irqc0>;
111 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;121 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
112 pinctrl-0 = <&phy1_pins>;
113 pinctrl-names = "default";
114 };122 };
115 };123 };
Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml+8−0
@@ -9,6 +9,14 @@ title: PCIe RC controller on Intel Gateway SoCs · 8 unmodified lines
9maintainers:9maintainers:
10 - Dilip Kota <eswara.kota@linux.intel.com>10 - Dilip Kota <eswara.kota@linux.intel.com>
11 11
12select:
13 properties:
14 compatible:
15 contains:
16 const: intel,lgm-pcie
17 required:
18 - compatible
19
12properties:20properties:
13 compatible:21 compatible:
14 items:22 items:
Documentation/devicetree/bindings/pwm/mxs-pwm.yaml+1−1
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# · 6 unmodified lines
7title: Freescale MXS PWM controller7title: Freescale MXS PWM controller
8 8
9maintainers:9maintainers:
10 - Shawn Guo <shawn.guo@linaro.org>10 - Shawn Guo <shawnguo@kernel.org>
11 - Anson Huang <anson.huang@nxp.com>11 - Anson Huang <anson.huang@nxp.com>
12 12
13properties:13properties:
Documentation/devicetree/bindings/spi/fsl-imx-cspi.yaml+1−1
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# · 6 unmodified lines
7title: Freescale (Enhanced) Configurable Serial Peripheral Interface (CSPI/eCSPI) for i.MX7title: Freescale (Enhanced) Configurable Serial Peripheral Interface (CSPI/eCSPI) for i.MX
8 8
9maintainers:9maintainers:
10 - Shawn Guo <shawn.guo@linaro.org>10 - Shawn Guo <shawnguo@kernel.org>
11 11
12allOf:12allOf:
13 - $ref: "/schemas/spi/spi-controller.yaml#"13 - $ref: "/schemas/spi/spi-controller.yaml#"
Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml+1−0
@@ -39,6 +39,7 @@ properties: · 38 unmodified lines
39 spi common code does not support use of CS signals discontinuously.39 spi common code does not support use of CS signals discontinuously.
40 i.MX8DXL-EVK board only uses CS1 without using CS0. Therefore, add40 i.MX8DXL-EVK board only uses CS1 without using CS0. Therefore, add
41 this property to re-config the chipselect value in the LPSPI driver.41 this property to re-config the chipselect value in the LPSPI driver.
42 type: boolean
42 43
43required:44required:
44 - compatible45 - compatible
Documentation/devicetree/bindings/thermal/imx-thermal.yaml+1−1
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# · 6 unmodified lines
7title: NXP i.MX Thermal Binding7title: NXP i.MX Thermal Binding
8 8
9maintainers:9maintainers:
10 - Shawn Guo <shawn.guo@linaro.org>10 - Shawn Guo <shawnguo@kernel.org>
11 - Anson Huang <Anson.Huang@nxp.com>11 - Anson Huang <Anson.Huang@nxp.com>
12 12
13properties:13properties:
Documentation/devicetree/bindings/timer/sifive,clint.yaml+60−0
@@ -0,0 +1,60 @@
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/timer/sifive,clint.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: SiFive Core Local Interruptor
8
9maintainers:
10 - Palmer Dabbelt <palmer@dabbelt.com>
11 - Anup Patel <anup.patel@wdc.com>
12
13description:
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16 interrupts. It directly connects to the timer and inter-processor interrupt
17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
18 interrupt controller is the parent interrupt controller for CLINT device.
19 The clock frequency of CLINT is specified via "timebase-frequency" DT
20 property of "/cpus" DT node. The "timebase-frequency" DT property is
21 described in Documentation/devicetree/bindings/riscv/cpus.yaml
22
23properties:
24 compatible:
25 items:
26 - const: sifive,fu540-c000-clint
27 - const: sifive,clint0
28
29 description:
30 Should be "sifive,<chip>-clint" and "sifive,clint<version>".
31 Supported compatible strings are -
32 "sifive,fu540-c000-clint" for the SiFive CLINT v0 as integrated
33 onto the SiFive FU540 chip, and "sifive,clint0" for the SiFive
34 CLINT v0 IP block with no chip integration tweaks.
35 Please refer to sifive-blocks-ip-versioning.txt for details
36
37 reg:
38 maxItems: 1
39
40 interrupts-extended:
41 minItems: 1
42
43additionalProperties: false
44
45required:
46 - compatible
47 - reg
48 - interrupts-extended
49
50examples:
51 - |
52 timer@2000000 {
53 compatible = "sifive,fu540-c000-clint", "sifive,clint0";
54 interrupts-extended = <&cpu1intc 3 &cpu1intc 7
55 &cpu2intc 3 &cpu2intc 7
56 &cpu3intc 3 &cpu3intc 7
57 &cpu4intc 3 &cpu4intc 7>;
58 reg = <0x2000000 0x10000>;
59 };
60...
Documentation/devicetree/bindings/vendor-prefixes.yaml+1−1
@@ -993,7 +993,7 @@ patternProperties: · 992 unmodified lines
993 "^sst,.*":993 "^sst,.*":
994 description: Silicon Storage Technology, Inc.994 description: Silicon Storage Technology, Inc.
995 "^sstar,.*":995 "^sstar,.*":
996 description: Xiamen Xingchen(SigmaStar) Technology Co., Ltd. 996 description: Xiamen Xingchen(SigmaStar) Technology Co., Ltd.
997 (formerly part of MStar Semiconductor, Inc.)997 (formerly part of MStar Semiconductor, Inc.)
998 "^st,.*":998 "^st,.*":
999 description: STMicroelectronics999 description: STMicroelectronics
Documentation/devicetree/writing-schema.rst+2−2
@@ -5,7 +5,7 @@ Writing DeviceTree Bindings in json-schema · 4 unmodified lines
5 5
6Devicetree bindings are written using json-schema vocabulary. Schema files are6Devicetree bindings are written using json-schema vocabulary. Schema files are
7written in a JSON compatible subset of YAML. YAML is used instead of JSON as it7written in a JSON compatible subset of YAML. YAML is used instead of JSON as it
8considered more human readable and has some advantages such as allowing8is considered more human readable and has some advantages such as allowing
9comments (Prefixed with '#').9comments (Prefixed with '#').
10 10
11Schema Contents11Schema Contents
@@ -19,7 +19,7 @@ $id · 7 unmodified lines
19 A json-schema unique identifier string. The string must be a valid19 A json-schema unique identifier string. The string must be a valid
20 URI typically containing the binding's filename and path. For DT schema, it must20 URI typically containing the binding's filename and path. For DT schema, it must
21 begin with "http://devicetree.org/schemas/". The URL is used in constructing21 begin with "http://devicetree.org/schemas/". The URL is used in constructing
22 references to other files specified in schema "$ref" properties. A $ref values22 references to other files specified in schema "$ref" properties. A $ref value
23 with a leading '/' will have the hostname prepended. A $ref value a relative23 with a leading '/' will have the hostname prepended. A $ref value a relative
24 path or filename only will be prepended with the hostname and path components24 path or filename only will be prepended with the hostname and path components
25 of the current schema file's '$id' value. A URL is used even for local files,25 of the current schema file's '$id' value. A URL is used even for local files,
Documentation/driver-api/fpga/fpga-bridge.rst+3−3
@@ -6,9 +6,9 @@ API to implement a new FPGA bridge · 5 unmodified lines
6 6
7* struct :c:type:`fpga_bridge` — The FPGA Bridge structure7* struct :c:type:`fpga_bridge` — The FPGA Bridge structure
8* struct :c:type:`fpga_bridge_ops` — Low level Bridge driver ops8* struct :c:type:`fpga_bridge_ops` — Low level Bridge driver ops
9* :c:func:`devm_fpga_bridge_create()` — Allocate and init a bridge struct9* devm_fpga_bridge_create() — Allocate and init a bridge struct
10* :c:func:`fpga_bridge_register()` — Register a bridge10* fpga_bridge_register() — Register a bridge
11* :c:func:`fpga_bridge_unregister()` — Unregister a bridge11* fpga_bridge_unregister() — Unregister a bridge
12 12
13.. kernel-doc:: include/linux/fpga/fpga-bridge.h13.. kernel-doc:: include/linux/fpga/fpga-bridge.h
14 :functions: fpga_bridge14 :functions: fpga_bridge
Documentation/driver-api/fpga/fpga-mgr.rst+3−3
@@ -104,9 +104,9 @@ API for implementing a new FPGA Manager driver · 103 unmodified lines
104* ``fpga_mgr_states`` — Values for :c:member:`fpga_manager->state`.104* ``fpga_mgr_states`` — Values for :c:member:`fpga_manager->state`.
105* struct :c:type:`fpga_manager` — the FPGA manager struct105* struct :c:type:`fpga_manager` — the FPGA manager struct
106* struct :c:type:`fpga_manager_ops` — Low level FPGA manager driver ops106* struct :c:type:`fpga_manager_ops` — Low level FPGA manager driver ops
107* :c:func:`devm_fpga_mgr_create` — Allocate and init a manager struct107* devm_fpga_mgr_create() — Allocate and init a manager struct
108* :c:func:`fpga_mgr_register` — Register an FPGA manager108* fpga_mgr_register() — Register an FPGA manager
109* :c:func:`fpga_mgr_unregister` — Unregister an FPGA manager109* fpga_mgr_unregister() — Unregister an FPGA manager
110 110
111.. kernel-doc:: include/linux/fpga/fpga-mgr.h111.. kernel-doc:: include/linux/fpga/fpga-mgr.h
112 :functions: fpga_mgr_states112 :functions: fpga_mgr_states
Documentation/driver-api/fpga/fpga-programming.rst+8−8
@@ -6,9 +6,9 @@ Overview · 5 unmodified lines
6 6
7The in-kernel API for FPGA programming is a combination of APIs from7The in-kernel API for FPGA programming is a combination of APIs from
8FPGA manager, bridge, and regions. The actual function used to8FPGA manager, bridge, and regions. The actual function used to
9trigger FPGA programming is :c:func:`fpga_region_program_fpga()`.9trigger FPGA programming is fpga_region_program_fpga().
10 10
11:c:func:`fpga_region_program_fpga()` uses functionality supplied by11fpga_region_program_fpga() uses functionality supplied by
12the FPGA manager and bridges. It will:12the FPGA manager and bridges. It will:
13 13
14 * lock the region's mutex14 * lock the region's mutex
@@ -20,8 +20,8 @@ the FPGA manager and bridges. It will: · 5 unmodified lines
20 * release the locks20 * release the locks
21 21
22The struct fpga_image_info specifies what FPGA image to program. It is22The struct fpga_image_info specifies what FPGA image to program. It is
23allocated/freed by :c:func:`fpga_image_info_alloc()` and freed with23allocated/freed by fpga_image_info_alloc() and freed with
24:c:func:`fpga_image_info_free()`24fpga_image_info_free()
25 25
26How to program an FPGA using a region26How to program an FPGA using a region
27-------------------------------------27-------------------------------------
@@ -84,10 +84,10 @@ will generate that list. Here's some sample code of what to do next:: · 56 unmodified lines
84API for programming an FPGA84API for programming an FPGA
85---------------------------85---------------------------
86 86
87* :c:func:`fpga_region_program_fpga` — Program an FPGA87* fpga_region_program_fpga() — Program an FPGA
88* :c:type:`fpga_image_info` — Specifies what FPGA image to program88* fpga_image_info() — Specifies what FPGA image to program
89* :c:func:`fpga_image_info_alloc()` — Allocate an FPGA image info struct89* fpga_image_info_alloc() — Allocate an FPGA image info struct
90* :c:func:`fpga_image_info_free()` — Free an FPGA image info struct90* fpga_image_info_free() — Free an FPGA image info struct
91 91
92.. kernel-doc:: drivers/fpga/fpga-region.c92.. kernel-doc:: drivers/fpga/fpga-region.c
93 :functions: fpga_region_program_fpga93 :functions: fpga_region_program_fpga
Documentation/driver-api/fpga/fpga-region.rst+9−9
@@ -46,18 +46,18 @@ API to add a new FPGA region · 45 unmodified lines
46----------------------------46----------------------------
47 47
48* struct :c:type:`fpga_region` — The FPGA region struct48* struct :c:type:`fpga_region` — The FPGA region struct
49* :c:func:`devm_fpga_region_create` — Allocate and init a region struct49* devm_fpga_region_create() — Allocate and init a region struct
50* :c:func:`fpga_region_register` — Register an FPGA region50* fpga_region_register() — Register an FPGA region
51* :c:func:`fpga_region_unregister` — Unregister an FPGA region51* fpga_region_unregister() — Unregister an FPGA region
52 52
53The FPGA region's probe function will need to get a reference to the FPGA53The FPGA region's probe function will need to get a reference to the FPGA
54Manager it will be using to do the programming. This usually would happen54Manager it will be using to do the programming. This usually would happen
55during the region's probe function.55during the region's probe function.
56 56
57* :c:func:`fpga_mgr_get` — Get a reference to an FPGA manager, raise ref count57* fpga_mgr_get() — Get a reference to an FPGA manager, raise ref count
58* :c:func:`of_fpga_mgr_get` — Get a reference to an FPGA manager, raise ref count,58* of_fpga_mgr_get() — Get a reference to an FPGA manager, raise ref count,
59 given a device node.59 given a device node.
60* :c:func:`fpga_mgr_put` — Put an FPGA manager60* fpga_mgr_put() — Put an FPGA manager
61 61
62The FPGA region will need to specify which bridges to control while programming62The FPGA region will need to specify which bridges to control while programming
63the FPGA. The region driver can build a list of bridges during probe time63the FPGA. The region driver can build a list of bridges during probe time
@@ -66,11 +66,11 @@ the list of bridges to program just before programming · 2 unmodified lines
66(:c:member:`fpga_region->get_bridges`). The FPGA bridge framework supplies the66(:c:member:`fpga_region->get_bridges`). The FPGA bridge framework supplies the
67following APIs to handle building or tearing down that list.67following APIs to handle building or tearing down that list.
68 68
69* :c:func:`fpga_bridge_get_to_list` — Get a ref of an FPGA bridge, add it to a69* fpga_bridge_get_to_list() — Get a ref of an FPGA bridge, add it to a
70 list70 list
71* :c:func:`of_fpga_bridge_get_to_list` — Get a ref of an FPGA bridge, add it to a71* of_fpga_bridge_get_to_list() — Get a ref of an FPGA bridge, add it to a
72 list, given a device node72 list, given a device node
73* :c:func:`fpga_bridges_put` — Given a list of bridges, put them73* fpga_bridges_put() — Given a list of bridges, put them
74 74
75.. kernel-doc:: include/linux/fpga/fpga-region.h75.. kernel-doc:: include/linux/fpga/fpga-region.h
76 :functions: fpga_region76 :functions: fpga_region
Documentation/driver-api/iio/core.rst+8−8
@@ -11,10 +11,10 @@ Industrial I/O Devices · 10 unmodified lines
11----------------------11----------------------
12 12
13* struct :c:type:`iio_dev` - industrial I/O device13* struct :c:type:`iio_dev` - industrial I/O device
14* :c:func:`iio_device_alloc()` - allocate an :c:type:`iio_dev` from a driver14* iio_device_alloc() - allocate an :c:type:`iio_dev` from a driver
15* :c:func:`iio_device_free()` - free an :c:type:`iio_dev` from a driver15* iio_device_free() - free an :c:type:`iio_dev` from a driver
16* :c:func:`iio_device_register()` - register a device with the IIO subsystem16* iio_device_register() - register a device with the IIO subsystem
17* :c:func:`iio_device_unregister()` - unregister a device from the IIO17* iio_device_unregister() - unregister a device from the IIO
18 subsystem18 subsystem
19 19
20An IIO device usually corresponds to a single hardware sensor and it20An IIO device usually corresponds to a single hardware sensor and it
@@ -34,17 +34,17 @@ A typical IIO driver will register itself as an :doc:`I2C <../i2c>` or · 13 unmodified lines
34 34
35At probe:35At probe:
36 36
371. Call :c:func:`iio_device_alloc()`, which allocates memory for an IIO device.371. Call iio_device_alloc(), which allocates memory for an IIO device.
382. Initialize IIO device fields with driver specific information (e.g.382. Initialize IIO device fields with driver specific information (e.g.
39 device name, device channels).39 device name, device channels).
403. Call :c:func:`iio_device_register()`, this registers the device with the403. Call iio_device_register(), this registers the device with the
41 IIO core. After this call the device is ready to accept requests from user41 IIO core. After this call the device is ready to accept requests from user
42 space applications.42 space applications.
43 43
44At remove, we free the resources allocated in probe in reverse order:44At remove, we free the resources allocated in probe in reverse order:
45 45
461. :c:func:`iio_device_unregister()`, unregister the device from the IIO core.461. iio_device_unregister(), unregister the device from the IIO core.
472. :c:func:`iio_device_free()`, free the memory allocated for the IIO device.472. iio_device_free(), free the memory allocated for the IIO device.
48 48
49IIO device sysfs interface49IIO device sysfs interface
50==========================50==========================
Documentation/fault-injection/nvme-fault-injection.rst+1−1
@@ -3,7 +3,7 @@ NVMe Fault Injection · 2 unmodified lines
3Linux's fault injection framework provides a systematic way to support3Linux's fault injection framework provides a systematic way to support
4error injection via debugfs in the /sys/kernel/debug directory. When4error injection via debugfs in the /sys/kernel/debug directory. When
5enabled, the default NVME_SC_INVALID_OPCODE with no retry will be5enabled, the default NVME_SC_INVALID_OPCODE with no retry will be
6injected into the nvme_end_request. Users can change the default status6injected into the nvme_try_complete_req. Users can change the default status
7code and no retry flag via the debugfs. The list of Generic Command7code and no retry flag via the debugfs. The list of Generic Command
8Status can be found in include/linux/nvme.h8Status can be found in include/linux/nvme.h
9 9
Documentation/filesystems/affs.rst+10−6
@@ -110,13 +110,15 @@ The Amiga protection flags RWEDRWEDHSPARWED are handled as follows: · 109 unmodified lines
110 110
111 - R maps to r for user, group and others. On directories, R implies x.111 - R maps to r for user, group and others. On directories, R implies x.
112 112
113 - If both W and D are allowed, w will be set.113 - W maps to w.
114 114
115 - E maps to x.115 - E maps to x.
116 116
117 - H and P are always retained and ignored under Linux.117 - D is ignored.
118 118
119 - A is always reset when a file is written to.119 - H, S and P are always retained and ignored under Linux.
120
121 - A is cleared when a file is written to.
120 122
121User id and group id will be used unless set[gu]id are given as mount123User id and group id will be used unless set[gu]id are given as mount
122options. Since most of the Amiga file systems are single user systems124options. Since most of the Amiga file systems are single user systems
@@ -128,11 +130,13 @@ Linux -> Amiga: · 5 unmodified lines
128 130
129The Linux rwxrwxrwx file mode is handled as follows:131The Linux rwxrwxrwx file mode is handled as follows:
130 132
131 - r permission will set R for user, group and others.133 - r permission will allow R for user, group and others.
134
135 - w permission will allow W for user, group and others.
132 136
133 - w permission will set W and D for user, group and others.137 - x permission of the user will allow E for plain files.
134 138
135 - x permission of the user will set E for plain files.139 - D will be allowed for user, group and others.
136 140
137 - All other flags (suid, sgid, ...) are ignored and will141 - All other flags (suid, sgid, ...) are ignored and will
138 not be retained.142 not be retained.
Documentation/filesystems/ext4/about.rst+1−1
@@ -39,6 +39,6 @@ entry. · 38 unmodified lines
39Other References39Other References
40----------------40----------------
41 41
42Also see http://www.nongnu.org/ext2-doc/ for quite a collection of42Also see https://www.nongnu.org/ext2-doc/ for quite a collection of
43information about ext2/3. Here's another old reference:43information about ext2/3. Here's another old reference:
44http://wiki.osdev.org/Ext244http://wiki.osdev.org/Ext2
Documentation/hwmon/abituguru-datasheet.rst+3−3
@@ -68,7 +68,7 @@ See below for all known bank addresses, numbers of sensors in that bank, · 67 unmodified lines
68number of bytes data per sensor and contents/meaning of those bytes.68number of bytes data per sensor and contents/meaning of those bytes.
69 69
70Although both this document and the kernel driver have kept the sensor70Although both this document and the kernel driver have kept the sensor
71terminoligy for the addressing within a bank this is not 100% correct, in71terminology for the addressing within a bank this is not 100% correct, in
72bank 0x24 for example the addressing within the bank selects a PWM output not72bank 0x24 for example the addressing within the bank selects a PWM output not
73a sensor.73a sensor.
74 74
@@ -155,7 +155,7 @@ After wider testing of the Linux kernel driver some variants of the uGuru have · 80 unmodified lines
155turned up which do not hold 0x08 at DATA within 250 reads after writing the155turned up which do not hold 0x08 at DATA within 250 reads after writing the
156bank address. With these versions this happens quite frequent, using larger156bank address. With these versions this happens quite frequent, using larger
157timeouts doesn't help, they just go offline for a second or 2, doing some157timeouts doesn't help, they just go offline for a second or 2, doing some
158internal callibration or whatever. Your code should be prepared to handle158internal calibration or whatever. Your code should be prepared to handle
159this and in case of no response in this specific case just goto sleep for a159this and in case of no response in this specific case just goto sleep for a
160while and then retry.160while and then retry.
161 161
@@ -331,6 +331,6 @@ the voltage / clock programming out, I tried reading and only reading banks · 169 unmodified lines
3310-0x30 with the reading code used for the sensor banks (0x20-0x28) and this3310-0x30 with the reading code used for the sensor banks (0x20-0x28) and this
332resulted in a _permanent_ reprogramming of the voltages, luckily I had the332resulted in a _permanent_ reprogramming of the voltages, luckily I had the
333sensors part configured so that it would shutdown my system on any out of spec333sensors part configured so that it would shutdown my system on any out of spec
334voltages which proprably safed my computer (after a reboot I managed to334voltages which probably safed my computer (after a reboot I managed to
335immediately enter the bios and reload the defaults). This probably means that335immediately enter the bios and reload the defaults). This probably means that
336the read/write cycle for the non sensor part is different from the sensor part.336the read/write cycle for the non sensor part is different from the sensor part.
Documentation/hwmon/abituguru.rst+2−2
@@ -17,7 +17,7 @@ Supported chips: · 16 unmodified lines
17 Note:17 Note:
18 The uGuru is a microcontroller with onboard firmware which programs18 The uGuru is a microcontroller with onboard firmware which programs
19 it to behave as a hwmon IC. There are many different revisions of the19 it to behave as a hwmon IC. There are many different revisions of the
20 firmware and thus effectivly many different revisions of the uGuru.20 firmware and thus effectively many different revisions of the uGuru.
21 Below is an incomplete list with which revisions are used for which21 Below is an incomplete list with which revisions are used for which
22 Motherboards:22 Motherboards:
23 23
@@ -33,7 +33,7 @@ Supported chips: · 9 unmodified lines
33 sensortype (Volt or Temp) for bank1 sensors, for revision 1 uGuru's33 sensortype (Volt or Temp) for bank1 sensors, for revision 1 uGuru's
34 this does not always work. For these uGuru's the autodetection can34 this does not always work. For these uGuru's the autodetection can
35 be overridden with the bank1_types module param. For all 3 known35 be overridden with the bank1_types module param. For all 3 known
36 revison 1 motherboards the correct use of this param is:36 revision 1 motherboards the correct use of this param is:
37 bank1_types=1,1,0,0,0,0,0,2,0,0,0,0,2,0,0,137 bank1_types=1,1,0,0,0,0,0,2,0,0,0,0,2,0,0,1
38 You may also need to specify the fan_sensors option for these boards38 You may also need to specify the fan_sensors option for these boards
39 fan_sensors=539 fan_sensors=5
Documentation/hwmon/abituguru3.rst+2−2
@@ -13,7 +13,7 @@ Supported chips: · 12 unmodified lines
13 Note:13 Note:
14 The uGuru is a microcontroller with onboard firmware which programs14 The uGuru is a microcontroller with onboard firmware which programs
15 it to behave as a hwmon IC. There are many different revisions of the15 it to behave as a hwmon IC. There are many different revisions of the
16 firmware and thus effectivly many different revisions of the uGuru.16 firmware and thus effectively many different revisions of the uGuru.
17 Below is an incomplete list with which revisions are used for which17 Below is an incomplete list with which revisions are used for which
18 Motherboards:18 Motherboards:
19 19
@@ -24,7 +24,7 @@ Supported chips: · 4 unmodified lines
24 - uGuru 3.0.0.0 ~ 3.0.x.x (AW8, AL8, AT8, NI8 SLI, AT8 32X, AN8 32X,24 - uGuru 3.0.0.0 ~ 3.0.x.x (AW8, AL8, AT8, NI8 SLI, AT8 32X, AN8 32X,
25 AW9D-MAX)25 AW9D-MAX)
26 26
27 The abituguru3 driver is only for revison 3.0.x.x motherboards,27 The abituguru3 driver is only for revision 3.0.x.x motherboards,
28 this driver will not work on older motherboards. For older28 this driver will not work on older motherboards. For older
29 motherboards use the abituguru (without the 3 !) driver.29 motherboards use the abituguru (without the 3 !) driver.
30 30
Documentation/kbuild/llvm.rst+13−13
@@ -23,8 +23,8 @@ supports C and the GNU C extensions required by the kernel, and is pronounced · 22 unmodified lines
23Clang23Clang
24-----24-----
25 25
26The compiler used can be swapped out via `CC=` command line argument to `make`.26The compiler used can be swapped out via ``CC=`` command line argument to ``make``.
27`CC=` should be set when selecting a config and during a build.27``CC=`` should be set when selecting a config and during a build. ::
28 28
29 make CC=clang defconfig29 make CC=clang defconfig
30 30
@@ -34,33 +34,33 @@ Cross Compiling · 3 unmodified lines
34---------------34---------------
35 35
36A single Clang compiler binary will typically contain all supported backends,36A single Clang compiler binary will typically contain all supported backends,
37which can help simplify cross compiling.37which can help simplify cross compiling. ::
38 38
39 ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- make CC=clang39 ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- make CC=clang
40 40
41`CROSS_COMPILE` is not used to prefix the Clang compiler binary, instead41``CROSS_COMPILE`` is not used to prefix the Clang compiler binary, instead
42`CROSS_COMPILE` is used to set a command line flag: `--target <triple>`. For42``CROSS_COMPILE`` is used to set a command line flag: ``--target <triple>``. For
43example:43example: ::
44 44
45 clang --target aarch64-linux-gnu foo.c45 clang --target aarch64-linux-gnu foo.c
46 46
47LLVM Utilities47LLVM Utilities
48--------------48--------------
49 49
50LLVM has substitutes for GNU binutils utilities. Kbuild supports `LLVM=1`50LLVM has substitutes for GNU binutils utilities. Kbuild supports ``LLVM=1``
51to enable them.51to enable them. ::
52 52
53 make LLVM=153 make LLVM=1
54 54
55They can be enabled individually. The full list of the parameters:55They can be enabled individually. The full list of the parameters: ::
56 56
57 make CC=clang LD=ld.lld AR=llvm-ar NM=llvm-nm STRIP=llvm-strip \\57 make CC=clang LD=ld.lld AR=llvm-ar NM=llvm-nm STRIP=llvm-strip \
58 OBJCOPY=llvm-objcopy OBJDUMP=llvm-objdump OBJSIZE=llvm-size \\58 OBJCOPY=llvm-objcopy OBJDUMP=llvm-objdump OBJSIZE=llvm-size \
59 READELF=llvm-readelf HOSTCC=clang HOSTCXX=clang++ HOSTAR=llvm-ar \\59 READELF=llvm-readelf HOSTCC=clang HOSTCXX=clang++ HOSTAR=llvm-ar \
60 HOSTLD=ld.lld60 HOSTLD=ld.lld
61 61
62Currently, the integrated assembler is disabled by default. You can pass62Currently, the integrated assembler is disabled by default. You can pass
63`LLVM_IAS=1` to enable it.63``LLVM_IAS=1`` to enable it.
64 64
65Getting Help65Getting Help
66------------66------------
Documentation/kbuild/makefiles.rst+9−9
@@ -16,7 +16,7 @@ This document describes the Linux kernel Makefiles. · 15 unmodified lines
16 --- 3.5 Library file goals - lib-y16 --- 3.5 Library file goals - lib-y
17 --- 3.6 Descending down in directories17 --- 3.6 Descending down in directories
18 --- 3.7 Compilation flags18 --- 3.7 Compilation flags
19 --- 3.8 Command line dependency19 --- 3.8 <deleted>
20 --- 3.9 Dependency tracking20 --- 3.9 Dependency tracking
21 --- 3.10 Special Rules21 --- 3.10 Special Rules
22 --- 3.11 $(CC) support functions22 --- 3.11 $(CC) support functions
@@ -39,8 +39,8 @@ This document describes the Linux kernel Makefiles. · 16 unmodified lines
39 39
40 === 7 Architecture Makefiles40 === 7 Architecture Makefiles
41 --- 7.1 Set variables to tweak the build to the architecture41 --- 7.1 Set variables to tweak the build to the architecture
42 --- 7.2 Add prerequisites to archheaders:42 --- 7.2 Add prerequisites to archheaders
43 --- 7.3 Add prerequisites to archprepare:43 --- 7.3 Add prerequisites to archprepare
44 --- 7.4 List directories to visit when descending44 --- 7.4 List directories to visit when descending
45 --- 7.5 Architecture-specific boot images45 --- 7.5 Architecture-specific boot images
46 --- 7.6 Building non-kbuild targets46 --- 7.6 Building non-kbuild targets
@@ -129,7 +129,7 @@ The preferred name for the kbuild files are 'Makefile' but 'Kbuild' can · 82 unmodified lines
129be used and if both a 'Makefile' and a 'Kbuild' file exists, then the 'Kbuild'129be used and if both a 'Makefile' and a 'Kbuild' file exists, then the 'Kbuild'
130file will be used.130file will be used.
131 131
132Section 3.1 "Goal definitions" is a quick intro, further chapters provide132Section 3.1 "Goal definitions" is a quick intro; further chapters provide
133more details, with real examples.133more details, with real examples.
134 134
1353.1 Goal definitions1353.1 Goal definitions
@@ -965,7 +965,7 @@ When kbuild executes, the following steps are followed (roughly): · 829 unmodified lines
965 KBUILD_LDFLAGS := -m elf_s390965 KBUILD_LDFLAGS := -m elf_s390
966 966
967 Note: ldflags-y can be used to further customise967 Note: ldflags-y can be used to further customise
968 the flags used. See chapter 3.7.968 the flags used. See section 3.7.
969 969
970 LDFLAGS_vmlinux970 LDFLAGS_vmlinux
971 Options for $(LD) when linking vmlinux971 Options for $(LD) when linking vmlinux
@@ -1121,7 +1121,7 @@ When kbuild executes, the following steps are followed (roughly): · 149 unmodified lines
1121 1121
1122 In this example, the file target maketools will be processed1122 In this example, the file target maketools will be processed
1123 before descending down in the subdirectories.1123 before descending down in the subdirectories.
1124 See also chapter XXX-TODO that describe how kbuild supports1124 See also chapter XXX-TODO that describes how kbuild supports
1125 generating offset header files.1125 generating offset header files.
1126 1126
1127 1127
@@ -1261,7 +1261,7 @@ When kbuild executes, the following steps are followed (roughly): · 133 unmodified lines
1261 always be built.1261 always be built.
1262 Assignments to $(targets) are without $(obj)/ prefix.1262 Assignments to $(targets) are without $(obj)/ prefix.
1263 if_changed may be used in conjunction with custom commands as1263 if_changed may be used in conjunction with custom commands as
1264 defined in 6.8 "Custom kbuild commands".1264 defined in 7.8 "Custom kbuild commands".
1265 1265
1266 Note: It is a typical mistake to forget the FORCE prerequisite.1266 Note: It is a typical mistake to forget the FORCE prerequisite.
1267 Another common pitfall is that whitespace is sometimes1267 Another common pitfall is that whitespace is sometimes
@@ -1411,7 +1411,7 @@ When kbuild executes, the following steps are followed (roughly): · 143 unmodified lines
1411 that may be shared between individual architectures.1411 that may be shared between individual architectures.
1412 The recommended approach how to use a generic header file is1412 The recommended approach how to use a generic header file is
1413 to list the file in the Kbuild file.1413 to list the file in the Kbuild file.
1414 See "7.2 generic-y" for further info on syntax etc.1414 See "8.2 generic-y" for further info on syntax etc.
1415 1415
14167.11 Post-link pass14167.11 Post-link pass
1417-------------------1417-------------------
@@ -1601,4 +1601,4 @@ is the right choice. · 183 unmodified lines
1601 1601
1602- Describe how kbuild supports shipped files with _shipped.1602- Describe how kbuild supports shipped files with _shipped.
1603- Generating offset header files.1603- Generating offset header files.
1604- Add more variables to section 7?1604- Add more variables to chapters 7 or 9?
Documentation/locking/locktypes.rst+12−12
@@ -164,14 +164,14 @@ by disabling preemption or interrupts. · 163 unmodified lines
164On non-PREEMPT_RT kernels local_lock operations map to the preemption and164On non-PREEMPT_RT kernels local_lock operations map to the preemption and
165interrupt disabling and enabling primitives:165interrupt disabling and enabling primitives:
166 166
167 =========================== ======================167 =============================== ======================
168 local_lock(&llock) preempt_disable()168 local_lock(&llock) preempt_disable()
169 local_unlock(&llock) preempt_enable()169 local_unlock(&llock) preempt_enable()
170 local_lock_irq(&llock) local_irq_disable()170 local_lock_irq(&llock) local_irq_disable()
171 local_unlock_irq(&llock) local_irq_enable()171 local_unlock_irq(&llock) local_irq_enable()
172 local_lock_save(&llock) local_irq_save()172 local_lock_irqsave(&llock) local_irq_save()
173 local_lock_restore(&llock) local_irq_save()173 local_unlock_irqrestore(&llock) local_irq_restore()
174 =========================== ======================174 =============================== ======================
175 175
176The named scope of local_lock has two advantages over the regular176The named scope of local_lock has two advantages over the regular
177primitives:177primitives:
@@ -353,14 +353,14 @@ protection scope. So the following substitution is wrong:: · 175 unmodified lines
353 {353 {
354 local_irq_save(flags); -> local_lock_irqsave(&local_lock_1, flags);354 local_irq_save(flags); -> local_lock_irqsave(&local_lock_1, flags);
355 func3();355 func3();
356 local_irq_restore(flags); -> local_lock_irqrestore(&local_lock_1, flags);356 local_irq_restore(flags); -> local_unlock_irqrestore(&local_lock_1, flags);
357 }357 }
358 358
359 func2()359 func2()
360 {360 {
361 local_irq_save(flags); -> local_lock_irqsave(&local_lock_2, flags);361 local_irq_save(flags); -> local_lock_irqsave(&local_lock_2, flags);
362 func3();362 func3();
363 local_irq_restore(flags); -> local_lock_irqrestore(&local_lock_2, flags);363 local_irq_restore(flags); -> local_unlock_irqrestore(&local_lock_2, flags);
364 }364 }
365 365
366 func3()366 func3()
@@ -379,14 +379,14 @@ PREEMPT_RT-specific semantics of spinlock_t. The correct substitution is:: · 12 unmodified lines
379 {379 {
380 local_irq_save(flags); -> local_lock_irqsave(&local_lock, flags);380 local_irq_save(flags); -> local_lock_irqsave(&local_lock, flags);
381 func3();381 func3();
382 local_irq_restore(flags); -> local_lock_irqrestore(&local_lock, flags);382 local_irq_restore(flags); -> local_unlock_irqrestore(&local_lock, flags);
383 }383 }
384 384
385 func2()385 func2()
386 {386 {
387 local_irq_save(flags); -> local_lock_irqsave(&local_lock, flags);387 local_irq_save(flags); -> local_lock_irqsave(&local_lock, flags);
388 func3();388 func3();
389 local_irq_restore(flags); -> local_lock_irqrestore(&local_lock, flags);389 local_irq_restore(flags); -> local_unlock_irqrestore(&local_lock, flags);
390 }390 }
391 391
392 func3()392 func3()
Documentation/maintainer/maintainer-entry-profile.rst+1−0
@@ -101,3 +101,4 @@ to do something different in the near future. · 100 unmodified lines
101 101
102 ../doc-guide/maintainer-profile102 ../doc-guide/maintainer-profile
103 ../nvdimm/maintainer-entry-profile103 ../nvdimm/maintainer-entry-profile
104 ../riscv/patch-acceptance
Documentation/networking/bonding.rst+0−18
@@ -2860,17 +2860,6 @@ version of the linux kernel, found on http://kernel.org · 2859 unmodified lines
2860The latest version of this document can be found in the latest kernel2860The latest version of this document can be found in the latest kernel
2861source (named Documentation/networking/bonding.rst).2861source (named Documentation/networking/bonding.rst).
2862 2862
2863Discussions regarding the usage of the bonding driver take place on the
2864bonding-devel mailing list, hosted at sourceforge.net. If you have questions or
2865problems, post them to the list. The list address is:
2866
2867bonding-devel@lists.sourceforge.net
2868
2869The administrative interface (to subscribe or unsubscribe) can
2870be found at:
2871
2872https://lists.sourceforge.net/lists/listinfo/bonding-devel
2873
2874Discussions regarding the development of the bonding driver take place2863Discussions regarding the development of the bonding driver take place
2875on the main Linux network mailing list, hosted at vger.kernel.org. The list2864on the main Linux network mailing list, hosted at vger.kernel.org. The list
2876address is:2865address is:
@@ -2881,10 +2870,3 @@ The administrative interface (to subscribe or unsubscribe) can · 4 unmodified lines
2881be found at:2870be found at:
2882 2871
2883http://vger.kernel.org/vger-lists.html#netdev2872http://vger.kernel.org/vger-lists.html#netdev
2884
2885Donald Becker's Ethernet Drivers and diag programs may be found at :
2886
2887 - http://web.archive.org/web/%2E/http://www.scyld.com/network/
2888
2889You will also find a lot of information regarding Ethernet, NWay, MII,
2890etc. at www.scyld.com.
Documentation/networking/dsa/configuration.rst+1−1
@@ -180,7 +180,7 @@ The configuration can only be set up via VLAN tagging and bridge setup. · 179 unmodified lines
180 180
181 # bring up the slave interfaces181 # bring up the slave interfaces
182 ip link set lan1 up182 ip link set lan1 up
183 ip link set lan1 up183 ip link set lan2 up
184 ip link set lan3 up184 ip link set lan3 up
185 185
186 # create bridge186 # create bridge
Documentation/powerpc/syscall64-abi.rst+3−1
@@ -49,16 +49,18 @@ Register preservation rules · 48 unmodified lines
49Register preservation rules match the ELF ABI calling sequence with the49Register preservation rules match the ELF ABI calling sequence with the
50following differences:50following differences:
51 51
52=========== ============= ========================================
53--- For the sc instruction, differences with the ELF ABI ---52--- For the sc instruction, differences with the ELF ABI ---
53=========== ============= ========================================
54r0 Volatile (System call number.)54r0 Volatile (System call number.)
55r3 Volatile (Parameter 1, and return value.)55r3 Volatile (Parameter 1, and return value.)
56r4-r8 Volatile (Parameters 2-6.)56r4-r8 Volatile (Parameters 2-6.)
57cr0 Volatile (cr0.SO is the return error condition.)57cr0 Volatile (cr0.SO is the return error condition.)
58cr1, cr5-7 Nonvolatile58cr1, cr5-7 Nonvolatile
59lr Nonvolatile59lr Nonvolatile
60=========== ============= ========================================
60 61
61--- For the scv 0 instruction, differences with the ELF ABI ---62--- For the scv 0 instruction, differences with the ELF ABI ---
63=========== ============= ========================================
62r0 Volatile (System call number.)64r0 Volatile (System call number.)
63r3 Volatile (Parameter 1, and return value.)65r3 Volatile (Parameter 1, and return value.)
64r4-r8 Volatile (Parameters 2-6.)66r4-r8 Volatile (Parameters 2-6.)
Documentation/process/deprecated.rst+1−1
@@ -142,7 +142,7 @@ only NUL-terminated strings. The safe replacement is strscpy(). · 141 unmodified lines
142(Users of strscpy() still needing NUL-padding should instead142(Users of strscpy() still needing NUL-padding should instead
143use strscpy_pad().)143use strscpy_pad().)
144 144
145If a caller is using non-NUL-terminated strings, strncpy()() can145If a caller is using non-NUL-terminated strings, strncpy() can
146still be used, but destinations should be marked with the `__nonstring146still be used, but destinations should be marked with the `__nonstring
147<https://gcc.gnu.org/onlinedocs/gcc/Common-Variable-Attributes.html>`_147<https://gcc.gnu.org/onlinedocs/gcc/Common-Variable-Attributes.html>`_
148attribute to avoid future compiler warnings.148attribute to avoid future compiler warnings.
Documentation/sound/cards/audigy-mixer.rst+1−1
@@ -332,7 +332,7 @@ WO 9901953 (A1) · 331 unmodified lines
332 332
333 333
334US Patents (https://www.uspto.gov/)334US Patents (https://www.uspto.gov/)
335----------------------------------335-----------------------------------
336 336
337US 5925841337US 5925841
338 Digital Sampling Instrument employing cache memory (Jul. 20, 1999)338 Digital Sampling Instrument employing cache memory (Jul. 20, 1999)
Documentation/sound/cards/sb-live-mixer.rst+1−1
@@ -337,7 +337,7 @@ WO 9901953 (A1) · 336 unmodified lines
337 337
338 338
339US Patents (https://www.uspto.gov/)339US Patents (https://www.uspto.gov/)
340----------------------------------340-----------------------------------
341 341
342US 5925841342US 5925841
343 Digital Sampling Instrument employing cache memory (Jul. 20, 1999)343 Digital Sampling Instrument employing cache memory (Jul. 20, 1999)
Documentation/sound/designs/timestamping.rst+1−1
@@ -143,7 +143,7 @@ timestamp shows when the information is put together by the driver · 142 unmodified lines
143before returning from the ``STATUS`` and ``STATUS_EXT`` ioctl. in most cases143before returning from the ``STATUS`` and ``STATUS_EXT`` ioctl. in most cases
144this driver_timestamp will be identical to the regular system tstamp.144this driver_timestamp will be identical to the regular system tstamp.
145 145
146Examples of typestamping with HDaudio:146Examples of timestamping with HDAudio:
147 147
1481. DMA timestamp, no compensation for DMA+analog delay1481. DMA timestamp, no compensation for DMA+analog delay
149::149::
Documentation/translations/it_IT/process/deprecated.rst+1−1
@@ -130,7 +130,7 @@ chi usa solo stringe terminate. La versione sicura da usare è · 129 unmodified lines
130strscpy(). (chi usa strscpy() e necessita di estendere la130strscpy(). (chi usa strscpy() e necessita di estendere la
131terminazione con NUL deve aggiungere una chiamata a memset())131terminazione con NUL deve aggiungere una chiamata a memset())
132 132
133Se il chiamate no usa stringhe terminate con NUL, allore strncpy()()133Se il chiamate no usa stringhe terminate con NUL, allore strncpy()
134può continuare ad essere usata, ma i buffer di destinazione devono essere134può continuare ad essere usata, ma i buffer di destinazione devono essere
135marchiati con l'attributo `__nonstring <https://gcc.gnu.org/onlinedocs/gcc/Common-Variable-Attributes.html>`_135marchiati con l'attributo `__nonstring <https://gcc.gnu.org/onlinedocs/gcc/Common-Variable-Attributes.html>`_
136per evitare avvisi durante la compilazione.136per evitare avvisi durante la compilazione.
MAINTAINERS+82−50
@@ -1694,7 +1694,6 @@ F: arch/arm/mach-cns3xxx/ · 1693 unmodified lines
1694 1694
1695ARM/CAVIUM THUNDER NETWORK DRIVER1695ARM/CAVIUM THUNDER NETWORK DRIVER
1696M: Sunil Goutham <sgoutham@marvell.com>1696M: Sunil Goutham <sgoutham@marvell.com>
1697M: Robert Richter <rrichter@marvell.com>
1698L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)1697L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
1699S: Supported1698S: Supported
1700F: drivers/net/ethernet/cavium/thunder/1699F: drivers/net/ethernet/cavium/thunder/
@@ -3205,6 +3204,7 @@ S: Maintained · 1504 unmodified lines
3205T: git git://git.kernel.org/pub/scm/linux/kernel/git/axboe/linux-block.git3204T: git git://git.kernel.org/pub/scm/linux/kernel/git/axboe/linux-block.git
3206F: block/3205F: block/
3207F: drivers/block/3206F: drivers/block/
3207F: include/linux/blk*
3208F: kernel/trace/blktrace.c3208F: kernel/trace/blktrace.c
3209F: lib/sbitmap.c3209F: lib/sbitmap.c
3210 3210
@@ -3388,6 +3388,7 @@ M: Florian Fainelli <f.fainelli@gmail.com> · 177 unmodified lines
3388L: netdev@vger.kernel.org3388L: netdev@vger.kernel.org
3389L: openwrt-devel@lists.openwrt.org (subscribers-only)3389L: openwrt-devel@lists.openwrt.org (subscribers-only)
3390S: Supported3390S: Supported
3391F: Documentation/devicetree/bindings/net/dsa/b53.txt
3391F: drivers/net/dsa/b53/*3392F: drivers/net/dsa/b53/*
3392F: include/linux/platform_data/b53.h3393F: include/linux/platform_data/b53.h
3393 3394
@@ -3573,13 +3574,28 @@ L: bcm-kernel-feedback-list@broadcom.com · 179 unmodified lines
3573S: Maintained3574S: Maintained
3574F: drivers/phy/broadcom/phy-brcm-usb*3575F: drivers/phy/broadcom/phy-brcm-usb*
3575 3576
3577BROADCOM ETHERNET PHY DRIVERS
3578M: Florian Fainelli <f.fainelli@gmail.com>
3579L: bcm-kernel-feedback-list@broadcom.com
3580L: netdev@vger.kernel.org
3581S: Supported
3582F: Documentation/devicetree/bindings/net/broadcom-bcm87xx.txt
3583F: drivers/net/phy/bcm*.[ch]
3584F: drivers/net/phy/broadcom.c
3585F: include/linux/brcmphy.h
3586
3576BROADCOM GENET ETHERNET DRIVER3587BROADCOM GENET ETHERNET DRIVER
3577M: Doug Berger <opendmb@gmail.com>3588M: Doug Berger <opendmb@gmail.com>
3578M: Florian Fainelli <f.fainelli@gmail.com>3589M: Florian Fainelli <f.fainelli@gmail.com>
3579L: bcm-kernel-feedback-list@broadcom.com3590L: bcm-kernel-feedback-list@broadcom.com
3580L: netdev@vger.kernel.org3591L: netdev@vger.kernel.org
3581S: Supported3592S: Supported
3593F: Documentation/devicetree/bindings/net/brcm,bcmgenet.txt
3594F: Documentation/devicetree/bindings/net/brcm,unimac-mdio.txt
3582F: drivers/net/ethernet/broadcom/genet/3595F: drivers/net/ethernet/broadcom/genet/
3596F: drivers/net/mdio/mdio-bcm-unimac.c
3597F: include/linux/platform_data/bcmgenet.h
3598F: include/linux/platform_data/mdio-bcm-unimac.h
3583 3599
3584BROADCOM IPROC ARM ARCHITECTURE3600BROADCOM IPROC ARM ARCHITECTURE
3585M: Ray Jui <rjui@broadcom.com>3601M: Ray Jui <rjui@broadcom.com>
@@ -3931,8 +3947,8 @@ W: https://wireless.wiki.kernel.org/en/users/Drivers/carl9170 · 345 unmodified lines
3931F: drivers/net/wireless/ath/carl9170/3947F: drivers/net/wireless/ath/carl9170/
3932 3948
3933CAVIUM I2C DRIVER3949CAVIUM I2C DRIVER
3934M: Robert Richter <rrichter@marvell.com>3950M: Robert Richter <rric@kernel.org>
3935S: Supported3951S: Odd Fixes
3936W: http://www.marvell.com3952W: http://www.marvell.com
3937F: drivers/i2c/busses/i2c-octeon*3953F: drivers/i2c/busses/i2c-octeon*
3938F: drivers/i2c/busses/i2c-thunderx*3954F: drivers/i2c/busses/i2c-thunderx*
@@ -3947,8 +3963,8 @@ W: http://www.marvell.com · 8 unmodified lines
3947F: drivers/net/ethernet/cavium/liquidio/3963F: drivers/net/ethernet/cavium/liquidio/
3948 3964
3949CAVIUM MMC DRIVER3965CAVIUM MMC DRIVER
3950M: Robert Richter <rrichter@marvell.com>3966M: Robert Richter <rric@kernel.org>
3951S: Supported3967S: Odd Fixes
3952W: http://www.marvell.com3968W: http://www.marvell.com
3953F: drivers/mmc/host/cavium*3969F: drivers/mmc/host/cavium*
3954 3970
@@ -3960,9 +3976,9 @@ W: http://www.marvell.com · 5 unmodified lines
3960F: drivers/crypto/cavium/cpt/3976F: drivers/crypto/cavium/cpt/
3961 3977
3962CAVIUM THUNDERX2 ARM64 SOC3978CAVIUM THUNDERX2 ARM64 SOC
3963M: Robert Richter <rrichter@marvell.com>3979M: Robert Richter <rric@kernel.org>
3964L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)3980L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
3965S: Maintained3981S: Odd Fixes
3966F: Documentation/devicetree/bindings/arm/cavium-thunder2.txt3982F: Documentation/devicetree/bindings/arm/cavium-thunder2.txt
3967F: arch/arm64/boot/dts/cavium/thunder2-99xx*3983F: arch/arm64/boot/dts/cavium/thunder2-99xx*
3968 3984
@@ -4241,6 +4257,8 @@ S: Maintained · 272 unmodified lines
4241F: .clang-format4257F: .clang-format
4242 4258
4243CLANG/LLVM BUILD SUPPORT4259CLANG/LLVM BUILD SUPPORT
4260M: Nathan Chancellor <natechancellor@gmail.com>
4261M: Nick Desaulniers <ndesaulniers@google.com>
4244L: clang-built-linux@googlegroups.com4262L: clang-built-linux@googlegroups.com
4245S: Supported4263S: Supported
4246W: https://clangbuiltlinux.github.io/4264W: https://clangbuiltlinux.github.io/
@@ -5050,7 +5068,7 @@ F: include/linux/dm-*.h · 803 unmodified lines
5050F: include/uapi/linux/dm-*.h5068F: include/uapi/linux/dm-*.h
5051 5069
5052DEVLINK5070DEVLINK
5053M: Jiri Pirko <jiri@mellanox.com>5071M: Jiri Pirko <jiri@nvidia.com>
5054L: netdev@vger.kernel.org5072L: netdev@vger.kernel.org
5055S: Supported5073S: Supported
5056F: Documentation/networking/devlink5074F: Documentation/networking/devlink
@@ -5239,6 +5257,7 @@ DOCUMENTATION · 182 unmodified lines
5239M: Jonathan Corbet <corbet@lwn.net>5257M: Jonathan Corbet <corbet@lwn.net>
5240L: linux-doc@vger.kernel.org5258L: linux-doc@vger.kernel.org
5241S: Maintained5259S: Maintained
5260P: Documentation/doc-guide/maintainer-profile.rst
5242T: git git://git.lwn.net/linux.git docs-next5261T: git git://git.lwn.net/linux.git docs-next
5243F: Documentation/5262F: Documentation/
5244F: scripts/documentation-file-ref-check5263F: scripts/documentation-file-ref-check
@@ -6081,7 +6100,7 @@ F: include/linux/dynamic_debug.h · 836 unmodified lines
6081F: lib/dynamic_debug.c6100F: lib/dynamic_debug.c
6082 6101
6083DYNAMIC INTERRUPT MODERATION6102DYNAMIC INTERRUPT MODERATION
6084M: Tal Gilboa <talgi@mellanox.com>6103M: Tal Gilboa <talgi@nvidia.com>
6085S: Maintained6104S: Maintained
6086F: Documentation/networking/net_dim.rst6105F: Documentation/networking/net_dim.rst
6087F: include/linux/dim.h6106F: include/linux/dim.h
@@ -6161,7 +6180,7 @@ F: Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt · 73 unmodified lines
6161F: drivers/edac/aspeed_edac.c6180F: drivers/edac/aspeed_edac.c
6162 6181
6163EDAC-BLUEFIELD6182EDAC-BLUEFIELD
6164M: Shravan Kumar Ramani <sramani@mellanox.com>6183M: Shravan Kumar Ramani <sramani@nvidia.com>
6165S: Supported6184S: Supported
6166F: drivers/edac/bluefield_edac.c6185F: drivers/edac/bluefield_edac.c
6167 6186
@@ -6173,16 +6192,15 @@ F: drivers/edac/highbank* · 5 unmodified lines
6173 6192
6174EDAC-CAVIUM OCTEON6193EDAC-CAVIUM OCTEON
6175M: Ralf Baechle <ralf@linux-mips.org>6194M: Ralf Baechle <ralf@linux-mips.org>
6176M: Robert Richter <rrichter@marvell.com>
6177L: linux-edac@vger.kernel.org6195L: linux-edac@vger.kernel.org
6178L: linux-mips@vger.kernel.org6196L: linux-mips@vger.kernel.org
6179S: Supported6197S: Supported
6180F: drivers/edac/octeon_edac*6198F: drivers/edac/octeon_edac*
6181 6199
6182EDAC-CAVIUM THUNDERX6200EDAC-CAVIUM THUNDERX
6183M: Robert Richter <rrichter@marvell.com>6201M: Robert Richter <rric@kernel.org>
6184L: linux-edac@vger.kernel.org6202L: linux-edac@vger.kernel.org
6185S: Supported6203S: Odd Fixes
6186F: drivers/edac/thunderx_edac*6204F: drivers/edac/thunderx_edac*
6187 6205
6188EDAC-CORE6206EDAC-CORE
@@ -6190,7 +6208,7 @@ M: Borislav Petkov <bp@alien8.de> · 1 unmodified line
6190M: Mauro Carvalho Chehab <mchehab@kernel.org>6208M: Mauro Carvalho Chehab <mchehab@kernel.org>
6191M: Tony Luck <tony.luck@intel.com>6209M: Tony Luck <tony.luck@intel.com>
6192R: James Morse <james.morse@arm.com>6210R: James Morse <james.morse@arm.com>
6193R: Robert Richter <rrichter@marvell.com>6211R: Robert Richter <rric@kernel.org>
6194L: linux-edac@vger.kernel.org6212L: linux-edac@vger.kernel.org
6195S: Supported6213S: Supported
6196T: git git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras.git edac-for-next6214T: git git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras.git edac-for-next
@@ -6483,8 +6501,8 @@ S: Odd Fixes · 286 unmodified lines
6483F: drivers/net/ethernet/agere/6501F: drivers/net/ethernet/agere/
6484 6502
6485ETHERNET BRIDGE6503ETHERNET BRIDGE
6486M: Roopa Prabhu <roopa@cumulusnetworks.com>6504M: Roopa Prabhu <roopa@nvidia.com>
6487M: Nikolay Aleksandrov <nikolay@cumulusnetworks.com>6505M: Nikolay Aleksandrov <nikolay@nvidia.com>
6488L: bridge@lists.linux-foundation.org (moderated for non-subscribers)6506L: bridge@lists.linux-foundation.org (moderated for non-subscribers)
6489L: netdev@vger.kernel.org6507L: netdev@vger.kernel.org
6490S: Maintained6508S: Maintained
@@ -6494,7 +6512,6 @@ F: net/bridge/ · 3 unmodified lines
6494 6512
6495ETHERNET PHY LIBRARY6513ETHERNET PHY LIBRARY
6496M: Andrew Lunn <andrew@lunn.ch>6514M: Andrew Lunn <andrew@lunn.ch>
6497M: Florian Fainelli <f.fainelli@gmail.com>
6498M: Heiner Kallweit <hkallweit1@gmail.com>6515M: Heiner Kallweit <hkallweit1@gmail.com>
6499R: Russell King <linux@armlinux.org.uk>6516R: Russell King <linux@armlinux.org.uk>
6500L: netdev@vger.kernel.org6517L: netdev@vger.kernel.org
@@ -6599,7 +6616,7 @@ F: drivers/iommu/exynos-iommu.c · 98 unmodified lines
6599 6616
6600EZchip NPS platform support6617EZchip NPS platform support
6601M: Vineet Gupta <vgupta@synopsys.com>6618M: Vineet Gupta <vgupta@synopsys.com>
6602M: Ofer Levi <oferle@mellanox.com>6619M: Ofer Levi <oferle@nvidia.com>
6603S: Supported6620S: Supported
6604F: arch/arc/boot/dts/eznps.dts6621F: arch/arc/boot/dts/eznps.dts
6605F: arch/arc/plat-eznps6622F: arch/arc/plat-eznps
@@ -8255,7 +8272,7 @@ IA64 (Itanium) PLATFORM · 1649 unmodified lines
8255M: Tony Luck <tony.luck@intel.com>8272M: Tony Luck <tony.luck@intel.com>
8256M: Fenghua Yu <fenghua.yu@intel.com>8273M: Fenghua Yu <fenghua.yu@intel.com>
8257L: linux-ia64@vger.kernel.org8274L: linux-ia64@vger.kernel.org
8258S: Maintained8275S: Odd Fixes
8259T: git git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux.git8276T: git git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux.git
8260F: Documentation/ia64/8277F: Documentation/ia64/
8261F: arch/ia64/8278F: arch/ia64/
@@ -8563,7 +8580,7 @@ F: drivers/iio/pressure/dps310.c · 301 unmodified lines
8563 8580
8564INFINIBAND SUBSYSTEM8581INFINIBAND SUBSYSTEM
8565M: Doug Ledford <dledford@redhat.com>8582M: Doug Ledford <dledford@redhat.com>
8566M: Jason Gunthorpe <jgg@mellanox.com>8583M: Jason Gunthorpe <jgg@nvidia.com>
8567L: linux-rdma@vger.kernel.org8584L: linux-rdma@vger.kernel.org
8568S: Supported8585S: Supported
8569W: https://github.com/linux-rdma/rdma-core8586W: https://github.com/linux-rdma/rdma-core
@@ -9226,7 +9243,7 @@ F: drivers/firmware/iscsi_ibft* · 656 unmodified lines
9226 9243
9227ISCSI EXTENSIONS FOR RDMA (ISER) INITIATOR9244ISCSI EXTENSIONS FOR RDMA (ISER) INITIATOR
9228M: Sagi Grimberg <sagi@grimberg.me>9245M: Sagi Grimberg <sagi@grimberg.me>
9229M: Max Gurtovoy <maxg@mellanox.com>9246M: Max Gurtovoy <maxg@nvidia.com>
9230L: linux-rdma@vger.kernel.org9247L: linux-rdma@vger.kernel.org
9231S: Supported9248S: Supported
9232W: http://www.openfabrics.org9249W: http://www.openfabrics.org
@@ -11072,7 +11089,7 @@ F: Documentation/devicetree/bindings/input/touchscreen/melfas_mip4.txt · 1839 unmodified lines
11072F: drivers/input/touchscreen/melfas_mip4.c11089F: drivers/input/touchscreen/melfas_mip4.c
11073 11090
11074MELLANOX ETHERNET DRIVER (mlx4_en)11091MELLANOX ETHERNET DRIVER (mlx4_en)
11075M: Tariq Toukan <tariqt@mellanox.com>11092M: Tariq Toukan <tariqt@nvidia.com>
11076L: netdev@vger.kernel.org11093L: netdev@vger.kernel.org
11077S: Supported11094S: Supported
11078W: http://www.mellanox.com11095W: http://www.mellanox.com
@@ -11080,7 +11097,7 @@ Q: http://patchwork.ozlabs.org/project/netdev/list/ · 1 unmodified line
11080F: drivers/net/ethernet/mellanox/mlx4/en_*11097F: drivers/net/ethernet/mellanox/mlx4/en_*
11081 11098
11082MELLANOX ETHERNET DRIVER (mlx5e)11099MELLANOX ETHERNET DRIVER (mlx5e)
11083M: Saeed Mahameed <saeedm@mellanox.com>11100M: Saeed Mahameed <saeedm@nvidia.com>
11084L: netdev@vger.kernel.org11101L: netdev@vger.kernel.org
11085S: Supported11102S: Supported
11086W: http://www.mellanox.com11103W: http://www.mellanox.com
@@ -11088,7 +11105,7 @@ Q: http://patchwork.ozlabs.org/project/netdev/list/ · 1 unmodified line
11088F: drivers/net/ethernet/mellanox/mlx5/core/en_*11105F: drivers/net/ethernet/mellanox/mlx5/core/en_*
11089 11106
11090MELLANOX ETHERNET INNOVA DRIVERS11107MELLANOX ETHERNET INNOVA DRIVERS
11091R: Boris Pismenny <borisp@mellanox.com>11108R: Boris Pismenny <borisp@nvidia.com>
11092L: netdev@vger.kernel.org11109L: netdev@vger.kernel.org
11093S: Supported11110S: Supported
11094W: http://www.mellanox.com11111W: http://www.mellanox.com
@@ -11099,8 +11116,8 @@ F: drivers/net/ethernet/mellanox/mlx5/core/fpga/* · 4 unmodified lines
11099F: include/linux/mlx5/mlx5_ifc_fpga.h11116F: include/linux/mlx5/mlx5_ifc_fpga.h
11100 11117
11101MELLANOX ETHERNET SWITCH DRIVERS11118MELLANOX ETHERNET SWITCH DRIVERS
11102M: Jiri Pirko <jiri@mellanox.com>11119M: Jiri Pirko <jiri@nvidia.com>
11103M: Ido Schimmel <idosch@mellanox.com>11120M: Ido Schimmel <idosch@nvidia.com>
11104L: netdev@vger.kernel.org11121L: netdev@vger.kernel.org
11105S: Supported11122S: Supported
11106W: http://www.mellanox.com11123W: http://www.mellanox.com
@@ -11109,7 +11126,7 @@ F: drivers/net/ethernet/mellanox/mlxsw/ · 2 unmodified lines
11109F: tools/testing/selftests/drivers/net/mlxsw/11126F: tools/testing/selftests/drivers/net/mlxsw/
11110 11127
11111MELLANOX FIRMWARE FLASH LIBRARY (mlxfw)11128MELLANOX FIRMWARE FLASH LIBRARY (mlxfw)
11112M: mlxsw@mellanox.com11129M: mlxsw@nvidia.com
11113L: netdev@vger.kernel.org11130L: netdev@vger.kernel.org
11114S: Supported11131S: Supported
11115W: http://www.mellanox.com11132W: http://www.mellanox.com
@@ -11119,7 +11136,7 @@ F: drivers/net/ethernet/mellanox/mlxfw/ · 3 unmodified lines
11119MELLANOX HARDWARE PLATFORM SUPPORT11136MELLANOX HARDWARE PLATFORM SUPPORT
11120M: Andy Shevchenko <andy@infradead.org>11137M: Andy Shevchenko <andy@infradead.org>
11121M: Darren Hart <dvhart@infradead.org>11138M: Darren Hart <dvhart@infradead.org>
11122M: Vadim Pasternak <vadimp@mellanox.com>11139M: Vadim Pasternak <vadimp@nvidia.com>
11123L: platform-driver-x86@vger.kernel.org11140L: platform-driver-x86@vger.kernel.org
11124S: Supported11141S: Supported
11125F: Documentation/ABI/testing/sysfs-platform-mellanox-bootctl11142F: Documentation/ABI/testing/sysfs-platform-mellanox-bootctl
@@ -11127,7 +11144,7 @@ F: drivers/platform/mellanox/ · 1 unmodified line
11127F: include/linux/platform_data/mlxreg.h11144F: include/linux/platform_data/mlxreg.h
11128 11145
11129MELLANOX MLX4 core VPI driver11146MELLANOX MLX4 core VPI driver
11130M: Tariq Toukan <tariqt@mellanox.com>11147M: Tariq Toukan <tariqt@nvidia.com>
11131L: netdev@vger.kernel.org11148L: netdev@vger.kernel.org
11132L: linux-rdma@vger.kernel.org11149L: linux-rdma@vger.kernel.org
11133S: Supported11150S: Supported
@@ -11137,7 +11154,7 @@ F: drivers/net/ethernet/mellanox/mlx4/ · 3 unmodified lines
11137F: include/linux/mlx4/11154F: include/linux/mlx4/
11138 11155
11139MELLANOX MLX4 IB driver11156MELLANOX MLX4 IB driver
11140M: Yishai Hadas <yishaih@mellanox.com>11157M: Yishai Hadas <yishaih@nvidia.com>
11141L: linux-rdma@vger.kernel.org11158L: linux-rdma@vger.kernel.org
11142S: Supported11159S: Supported
11143W: http://www.mellanox.com11160W: http://www.mellanox.com
@@ -11147,8 +11164,8 @@ F: include/linux/mlx4/ · 3 unmodified lines
11147F: include/uapi/rdma/mlx4-abi.h11164F: include/uapi/rdma/mlx4-abi.h
11148 11165
11149MELLANOX MLX5 core VPI driver11166MELLANOX MLX5 core VPI driver
11150M: Saeed Mahameed <saeedm@mellanox.com>11167M: Saeed Mahameed <saeedm@nvidia.com>
11151M: Leon Romanovsky <leonro@mellanox.com>11168M: Leon Romanovsky <leonro@nvidia.com>
11152L: netdev@vger.kernel.org11169L: netdev@vger.kernel.org
11153L: linux-rdma@vger.kernel.org11170L: linux-rdma@vger.kernel.org
11154S: Supported11171S: Supported
@@ -11159,7 +11176,7 @@ F: drivers/net/ethernet/mellanox/mlx5/core/ · 4 unmodified lines
11159F: include/linux/mlx5/11176F: include/linux/mlx5/
11160 11177
11161MELLANOX MLX5 IB driver11178MELLANOX MLX5 IB driver
11162M: Leon Romanovsky <leonro@mellanox.com>11179M: Leon Romanovsky <leonro@nvidia.com>
11163L: linux-rdma@vger.kernel.org11180L: linux-rdma@vger.kernel.org
11164S: Supported11181S: Supported
11165W: http://www.mellanox.com11182W: http://www.mellanox.com
@@ -11169,8 +11186,8 @@ F: include/linux/mlx5/ · 3 unmodified lines
11169F: include/uapi/rdma/mlx5-abi.h11186F: include/uapi/rdma/mlx5-abi.h
11170 11187
11171MELLANOX MLXCPLD I2C AND MUX DRIVER11188MELLANOX MLXCPLD I2C AND MUX DRIVER
11172M: Vadim Pasternak <vadimp@mellanox.com>11189M: Vadim Pasternak <vadimp@nvidia.com>
11173M: Michael Shych <michaelsh@mellanox.com>11190M: Michael Shych <michaelsh@nvidia.com>
11174L: linux-i2c@vger.kernel.org11191L: linux-i2c@vger.kernel.org
11175S: Supported11192S: Supported
11176F: Documentation/i2c/busses/i2c-mlxcpld.rst11193F: Documentation/i2c/busses/i2c-mlxcpld.rst
@@ -11178,7 +11195,7 @@ F: drivers/i2c/busses/i2c-mlxcpld.c · 1 unmodified line
11178F: drivers/i2c/muxes/i2c-mux-mlxcpld.c11195F: drivers/i2c/muxes/i2c-mux-mlxcpld.c
11179 11196
11180MELLANOX MLXCPLD LED DRIVER11197MELLANOX MLXCPLD LED DRIVER
11181M: Vadim Pasternak <vadimp@mellanox.com>11198M: Vadim Pasternak <vadimp@nvidia.com>
11182L: linux-leds@vger.kernel.org11199L: linux-leds@vger.kernel.org
11183S: Supported11200S: Supported
11184F: Documentation/leds/leds-mlxcpld.rst11201F: Documentation/leds/leds-mlxcpld.rst
@@ -11186,7 +11203,7 @@ F: drivers/leds/leds-mlxcpld.c · 1 unmodified line
11186F: drivers/leds/leds-mlxreg.c11203F: drivers/leds/leds-mlxreg.c
11187 11204
11188MELLANOX PLATFORM DRIVER11205MELLANOX PLATFORM DRIVER
11189M: Vadim Pasternak <vadimp@mellanox.com>11206M: Vadim Pasternak <vadimp@nvidia.com>
11190L: platform-driver-x86@vger.kernel.org11207L: platform-driver-x86@vger.kernel.org
11191S: Supported11208S: Supported
11192F: drivers/platform/x86/mlx-platform.c11209F: drivers/platform/x86/mlx-platform.c
@@ -12167,8 +12184,8 @@ F: net/ipv6/syncookies.c · 974 unmodified lines
12167F: net/ipv6/tcp*.c12184F: net/ipv6/tcp*.c
12168 12185
12169NETWORKING [TLS]12186NETWORKING [TLS]
12170M: Boris Pismenny <borisp@mellanox.com>12187M: Boris Pismenny <borisp@nvidia.com>
12171M: Aviad Yehezkel <aviadye@mellanox.com>12188M: Aviad Yehezkel <aviadye@nvidia.com>
12172M: John Fastabend <john.fastabend@gmail.com>12189M: John Fastabend <john.fastabend@gmail.com>
12173M: Daniel Borkmann <daniel@iogearbox.net>12190M: Daniel Borkmann <daniel@iogearbox.net>
12174M: Jakub Kicinski <kuba@kernel.org>12191M: Jakub Kicinski <kuba@kernel.org>
@@ -12468,7 +12485,7 @@ S: Supported · 293 unmodified lines
12468F: drivers/nfc/nxp-nci12485F: drivers/nfc/nxp-nci
12469 12486
12470OBJAGG12487OBJAGG
12471M: Jiri Pirko <jiri@mellanox.com>12488M: Jiri Pirko <jiri@nvidia.com>
12472L: netdev@vger.kernel.org12489L: netdev@vger.kernel.org
12473S: Supported12490S: Supported
12474F: include/linux/objagg.h12491F: include/linux/objagg.h
@@ -13112,7 +13129,7 @@ F: drivers/video/logo/logo_parisc* · 637 unmodified lines
13112F: include/linux/hp_sdc.h13129F: include/linux/hp_sdc.h
13113 13130
13114PARMAN13131PARMAN
13115M: Jiri Pirko <jiri@mellanox.com>13132M: Jiri Pirko <jiri@nvidia.com>
13116L: netdev@vger.kernel.org13133L: netdev@vger.kernel.org
13117S: Supported13134S: Supported
13118F: include/linux/parman.h13135F: include/linux/parman.h
@@ -13431,10 +13448,10 @@ F: Documentation/devicetree/bindings/pci/axis,artpec* · 312 unmodified lines
13431F: drivers/pci/controller/dwc/*artpec*13448F: drivers/pci/controller/dwc/*artpec*
13432 13449
13433PCIE DRIVER FOR CAVIUM THUNDERX13450PCIE DRIVER FOR CAVIUM THUNDERX
13434M: Robert Richter <rrichter@marvell.com>13451M: Robert Richter <rric@kernel.org>
13435L: linux-pci@vger.kernel.org13452L: linux-pci@vger.kernel.org
13436L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)13453L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
13437S: Supported13454S: Odd Fixes
13438F: drivers/pci/controller/pci-thunder-*13455F: drivers/pci/controller/pci-thunder-*
13439 13456
13440PCIE DRIVER FOR HISILICON13457PCIE DRIVER FOR HISILICON
@@ -13571,12 +13588,18 @@ F: kernel/events/* · 130 unmodified lines
13571F: tools/lib/perf/13588F: tools/lib/perf/
13572F: tools/perf/13589F: tools/perf/
13573 13590
13574PERFORMANCE EVENTS SUBSYSTEM ARM64 PMU EVENTS13591PERFORMANCE EVENTS TOOLING ARM64
13575R: John Garry <john.garry@huawei.com>13592R: John Garry <john.garry@huawei.com>
13576R: Will Deacon <will@kernel.org>13593R: Will Deacon <will@kernel.org>
13594R: Mathieu Poirier <mathieu.poirier@linaro.org>
13595R: Leo Yan <leo.yan@linaro.org>
13577L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)13596L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
13578S: Supported13597S: Supported
13598F: tools/build/feature/test-libopencsd.c
13599F: tools/perf/arch/arm*/
13579F: tools/perf/pmu-events/arch/arm64/13600F: tools/perf/pmu-events/arch/arm64/
13601F: tools/perf/util/arm-spe*
13602F: tools/perf/util/cs-etm*
13580 13603
13581PERSONALITY HANDLING13604PERSONALITY HANDLING
13582M: Christoph Hellwig <hch@infradead.org>13605M: Christoph Hellwig <hch@infradead.org>
@@ -14367,7 +14390,7 @@ M: Rob Clark <robdclark@gmail.com> · 784 unmodified lines
14367L: iommu@lists.linux-foundation.org14390L: iommu@lists.linux-foundation.org
14368L: linux-arm-msm@vger.kernel.org14391L: linux-arm-msm@vger.kernel.org
14369S: Maintained14392S: Maintained
14370F: drivers/iommu/qcom_iommu.c14393F: drivers/iommu/arm/arm-smmu/qcom_iommu.c
14371 14394
14372QUALCOMM IPCC MAILBOX DRIVER14395QUALCOMM IPCC MAILBOX DRIVER
14373M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>14396M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
@@ -16037,7 +16060,7 @@ F: drivers/infiniband/sw/siw/ · 1663 unmodified lines
16037F: include/uapi/rdma/siw-abi.h16060F: include/uapi/rdma/siw-abi.h
16038 16061
16039SOFT-ROCE DRIVER (rxe)16062SOFT-ROCE DRIVER (rxe)
16040M: Zhu Yanjun <yanjunz@mellanox.com>16063M: Zhu Yanjun <yanjunz@nvidia.com>
16041L: linux-rdma@vger.kernel.org16064L: linux-rdma@vger.kernel.org
16042S: Supported16065S: Supported
16043F: drivers/infiniband/sw/rxe/16066F: drivers/infiniband/sw/rxe/
@@ -17118,8 +17141,8 @@ S: Maintained · 1074 unmodified lines
17118F: Documentation/devicetree/bindings/arm/keystone/ti,k3-sci-common.yaml17141F: Documentation/devicetree/bindings/arm/keystone/ti,k3-sci-common.yaml
17119F: Documentation/devicetree/bindings/arm/keystone/ti,sci.txt17142F: Documentation/devicetree/bindings/arm/keystone/ti,sci.txt
17120F: Documentation/devicetree/bindings/clock/ti,sci-clk.txt17143F: Documentation/devicetree/bindings/clock/ti,sci-clk.txt
17121F: Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.txt17144F: Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.yaml
17122F: Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.txt17145F: Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.yaml
17123F: Documentation/devicetree/bindings/reset/ti,sci-reset.txt17146F: Documentation/devicetree/bindings/reset/ti,sci-reset.txt
17124F: Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt17147F: Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
17125F: drivers/clk/keystone/sci-clk.c17148F: drivers/clk/keystone/sci-clk.c
@@ -17216,8 +17239,8 @@ S: Maintained · 90 unmodified lines
17216F: drivers/net/thunderbolt.c17239F: drivers/net/thunderbolt.c
17217 17240
17218THUNDERX GPIO DRIVER17241THUNDERX GPIO DRIVER
17219M: Robert Richter <rrichter@marvell.com>17242M: Robert Richter <rric@kernel.org>
17220S: Maintained17243S: Odd Fixes
17221F: drivers/gpio/gpio-thunderx.c17244F: drivers/gpio/gpio-thunderx.c
17222 17245
17223TI AM437X VPFE DRIVER17246TI AM437X VPFE DRIVER
@@ -18874,6 +18897,15 @@ S: Maintained · 1650 unmodified lines
18874T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86/core18897T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86/core
18875F: arch/x86/platform18898F: arch/x86/platform
18876 18899
18900X86 PLATFORM UV HPE SUPERDOME FLEX
18901M: Steve Wahl <steve.wahl@hpe.com>
18902R: Dimitri Sivanich <dimitri.sivanich@hpe.com>
18903R: Russ Anderson <russ.anderson@hpe.com>
18904S: Supported
18905F: arch/x86/include/asm/uv/
18906F: arch/x86/kernel/apic/x2apic_uv_x.c
18907F: arch/x86/platform/uv/
18908
18877X86 VDSO18909X86 VDSO
18878M: Andy Lutomirski <luto@kernel.org>18910M: Andy Lutomirski <luto@kernel.org>
18879L: linux-kernel@vger.kernel.org18911L: linux-kernel@vger.kernel.org
Makefile+3−4
@@ -2,7 +2,7 @@ · 1 unmodified line
2VERSION = 52VERSION = 5
3PATCHLEVEL = 93PATCHLEVEL = 9
4SUBLEVEL = 04SUBLEVEL = 0
5EXTRAVERSION = -rc15EXTRAVERSION = -rc4
6NAME = Kleptomaniac Octopus6NAME = Kleptomaniac Octopus
7 7
8# *DOCUMENTATION*8# *DOCUMENTATION*
@@ -265,8 +265,7 @@ no-dot-config-targets := $(clean-targets) \ · 256 unmodified lines
265 $(version_h) headers headers_% archheaders archscripts \265 $(version_h) headers headers_% archheaders archscripts \
266 %asm-generic kernelversion %src-pkg dt_binding_check \266 %asm-generic kernelversion %src-pkg dt_binding_check \
267 outputmakefile267 outputmakefile
268no-sync-config-targets := $(no-dot-config-targets) install %install \268no-sync-config-targets := $(no-dot-config-targets) %install kernelrelease
269 kernelrelease
270single-targets := %.a %.i %.ko %.lds %.ll %.lst %.mod %.o %.s %.symtypes %/269single-targets := %.a %.i %.ko %.lds %.ll %.lst %.mod %.o %.s %.symtypes %/
271 270
272config-build :=271config-build :=
@@ -292,7 +291,7 @@ ifneq ($(KBUILD_EXTMOD),) · 19 unmodified lines
292endif291endif
293 292
294ifeq ($(KBUILD_EXTMOD),)293ifeq ($(KBUILD_EXTMOD),)
295 ifneq ($(filter config %config,$(MAKECMDGOALS)),)294 ifneq ($(filter %config,$(MAKECMDGOALS)),)
296 config-build := 1295 config-build := 1
297 ifneq ($(words $(MAKECMDGOALS)),1)296 ifneq ($(words $(MAKECMDGOALS)),1)
298 mixed-build := 1297 mixed-build := 1
arch/alpha/kernel/module.c+1−1
@@ -212,7 +212,7 @@ apply_relocate_add(Elf64_Shdr *sechdrs, const char *strtab, · 211 unmodified lines
212 STO_ALPHA_STD_GPLOAD)212 STO_ALPHA_STD_GPLOAD)
213 /* Omit the prologue. */213 /* Omit the prologue. */
214 value += 8;214 value += 8;
215 /* FALLTHRU */215 fallthrough;
216 case R_ALPHA_BRADDR:216 case R_ALPHA_BRADDR:
217 value -= (u64)location + 4;217 value -= (u64)location + 4;
218 if (value & 3)218 if (value & 3)
arch/alpha/kernel/signal.c+1−1
@@ -453,7 +453,7 @@ syscall_restart(unsigned long r0, unsigned long r19, · 452 unmodified lines
453 regs->r0 = EINTR;453 regs->r0 = EINTR;
454 break;454 break;
455 }455 }
456 /* fallthrough */456 fallthrough;
457 case ERESTARTNOINTR:457 case ERESTARTNOINTR:
458 regs->r0 = r0; /* reset v0 and a3 and replay syscall */458 regs->r0 = r0; /* reset v0 and a3 and replay syscall */
459 regs->r19 = r19;459 regs->r19 = r19;
arch/alpha/kernel/traps.c+2−2
@@ -883,7 +883,7 @@ do_entUnaUser(void __user * va, unsigned long opcode, · 882 unmodified lines
883 883
884 case 0x26: /* sts */884 case 0x26: /* sts */
885 fake_reg = s_reg_to_mem(alpha_read_fp_reg(reg));885 fake_reg = s_reg_to_mem(alpha_read_fp_reg(reg));
886 /* FALLTHRU */886 fallthrough;
887 887
888 case 0x2c: /* stl */888 case 0x2c: /* stl */
889 __asm__ __volatile__(889 __asm__ __volatile__(
@@ -911,7 +911,7 @@ do_entUnaUser(void __user * va, unsigned long opcode, · 21 unmodified lines
911 911
912 case 0x27: /* stt */912 case 0x27: /* stt */
913 fake_reg = alpha_read_fp_reg(reg);913 fake_reg = alpha_read_fp_reg(reg);
914 /* FALLTHRU */914 fallthrough;
915 915
916 case 0x2d: /* stq */916 case 0x2d: /* stq */
917 __asm__ __volatile__(917 __asm__ __volatile__(
arch/arc/boot/dts/hsdk.dts+4−2
@@ -88,6 +88,8 @@ · 87 unmodified lines
88 88
89 arcpct: pct {89 arcpct: pct {
90 compatible = "snps,archs-pct";90 compatible = "snps,archs-pct";
91 interrupt-parent = <&cpu_intc>;
92 interrupts = <20>;
91 };93 };
92 94
93 /* TIMER0 with interrupt for clockevent */95 /* TIMER0 with interrupt for clockevent */
@@ -208,7 +210,7 @@ · 114 unmodified lines
208 reg = <0x8000 0x2000>;210 reg = <0x8000 0x2000>;
209 interrupts = <10>;211 interrupts = <10>;
210 interrupt-names = "macirq";212 interrupt-names = "macirq";
211 phy-mode = "rgmii";213 phy-mode = "rgmii-id";
212 snps,pbl = <32>;214 snps,pbl = <32>;
213 snps,multicast-filter-bins = <256>;215 snps,multicast-filter-bins = <256>;
214 clocks = <&gmacclk>;216 clocks = <&gmacclk>;
@@ -226,7 +228,7 @@ · 11 unmodified lines
226 #address-cells = <1>;228 #address-cells = <1>;
227 #size-cells = <0>;229 #size-cells = <0>;
228 compatible = "snps,dwmac-mdio";230 compatible = "snps,dwmac-mdio";
229 phy0: ethernet-phy@0 {231 phy0: ethernet-phy@0 { /* Micrel KSZ9031 */
230 reg = <0>;232 reg = <0>;
231 };233 };
232 };234 };
arch/arc/include/asm/pgalloc.h+2−2
@@ -18,10 +18,10 @@ · 17 unmodified lines
18 * vineetg: April 201018 * vineetg: April 2010
19 * -Switched pgtable_t from being struct page * to unsigned long19 * -Switched pgtable_t from being struct page * to unsigned long
20 * =Needed so that Page Table allocator (pte_alloc_one) is not forced to20 * =Needed so that Page Table allocator (pte_alloc_one) is not forced to
21 * to deal with struct page. Thay way in future we can make it allocate21 * deal with struct page. That way in future we can make it allocate
22 * multiple PG Tbls in one Page Frame22 * multiple PG Tbls in one Page Frame
23 * =sweet side effect is avoiding calls to ugly page_address( ) from the23 * =sweet side effect is avoiding calls to ugly page_address( ) from the
24 * pg-tlb allocator sub-sys (pte_alloc_one, ptr_free, pmd_populate24 * pg-tlb allocator sub-sys (pte_alloc_one, ptr_free, pmd_populate)
25 *25 *
26 * Amit Bhor, Sameer Dhavale: Codito Technologies 200426 * Amit Bhor, Sameer Dhavale: Codito Technologies 2004
27 */27 */
arch/arc/kernel/disasm.c+1−1
@@ -339,7 +339,7 @@ void __kprobes disasm_instr(unsigned long addr, struct disasm_state *state, · 338 unmodified lines
339 339
340 case op_LDWX_S: /* LDWX_S c, [b, u6] */340 case op_LDWX_S: /* LDWX_S c, [b, u6] */
341 state->x = 1;341 state->x = 1;
342 /* intentional fall-through */342 fallthrough;
343 343
344 case op_LDW_S: /* LDW_S c, [b, u6] */344 case op_LDW_S: /* LDW_S c, [b, u6] */
345 state->zz = 2;345 state->zz = 2;
arch/arc/kernel/perf_event.c+4−10
@@ -562,7 +562,7 @@ static int arc_pmu_device_probe(struct platform_device *pdev) · 561 unmodified lines
562{562{
563 struct arc_reg_pct_build pct_bcr;563 struct arc_reg_pct_build pct_bcr;
564 struct arc_reg_cc_build cc_bcr;564 struct arc_reg_cc_build cc_bcr;
565 int i, has_interrupts;565 int i, has_interrupts, irq;
566 int counter_size; /* in bits */566 int counter_size; /* in bits */
567 567
568 union cc_name {568 union cc_name {
@@ -637,13 +637,7 @@ static int arc_pmu_device_probe(struct platform_device *pdev) · 68 unmodified lines
637 .attr_groups = arc_pmu->attr_groups,637 .attr_groups = arc_pmu->attr_groups,
638 };638 };
639 639
640 if (has_interrupts) {640 if (has_interrupts && (irq = platform_get_irq(pdev, 0) >= 0)) {
641 int irq = platform_get_irq(pdev, 0);
642
643 if (irq < 0) {
644 pr_err("Cannot get IRQ number for the platform\n");
645 return -ENODEV;
646 }
647 641
648 arc_pmu->irq = irq;642 arc_pmu->irq = irq;
649 643
@@ -652,9 +646,9 @@ static int arc_pmu_device_probe(struct platform_device *pdev) · 2 unmodified lines
652 this_cpu_ptr(&arc_pmu_cpu));646 this_cpu_ptr(&arc_pmu_cpu));
653 647
654 on_each_cpu(arc_cpu_pmu_irq_init, &irq, 1);648 on_each_cpu(arc_cpu_pmu_irq_init, &irq, 1);
655 649 } else {
656 } else
657 arc_pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;650 arc_pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
651 }
658 652
659 /*653 /*
660 * perf parser doesn't really like '-' symbol in events name, so let's654 * perf parser doesn't really like '-' symbol in events name, so let's
arch/arc/kernel/signal.c+1−1
@@ -321,7 +321,7 @@ static void arc_restart_syscall(struct k_sigaction *ka, struct pt_regs *regs) · 320 unmodified lines
321 regs->r0 = -EINTR;321 regs->r0 = -EINTR;
322 break;322 break;
323 }323 }
324 /* fallthrough */324 fallthrough;
325 325
326 case -ERESTARTNOINTR:326 case -ERESTARTNOINTR:
327 /*327 /*
arch/arc/kernel/troubleshoot.c+30−47
@@ -18,44 +18,37 @@ · 17 unmodified lines
18 18
19#define ARC_PATH_MAX 25619#define ARC_PATH_MAX 256
20 20
21/*21static noinline void print_regs_scratch(struct pt_regs *regs)
22 * Common routine to print scratch regs (r0-r12) or callee regs (r13-r25)
23 * -Prints 3 regs per line and a CR.
24 * -To continue, callee regs right after scratch, special handling of CR
25 */
26static noinline void print_reg_file(long *reg_rev, int start_num)
27{22{
28 unsigned int i;23 pr_cont("BTA: 0x%08lx\n SP: 0x%08lx FP: 0x%08lx BLK: %pS\n",
29 char buf[512];24 regs->bta, regs->sp, regs->fp, (void *)regs->blink);
30 int n = 0, len = sizeof(buf);25 pr_cont("LPS: 0x%08lx\tLPE: 0x%08lx\tLPC: 0x%08lx\n",
31 26 regs->lp_start, regs->lp_end, regs->lp_count);
32 for (i = start_num; i < start_num + 13; i++) {
33 n += scnprintf(buf + n, len - n, "r%02u: 0x%08lx\t",
34 i, (unsigned long)*reg_rev);
35
36 if (((i + 1) % 3) == 0)
37 n += scnprintf(buf + n, len - n, "\n");
38
39 /* because pt_regs has regs reversed: r12..r0, r25..r13 */
40 if (is_isa_arcv2() && start_num == 0)
41 reg_rev++;
42 else
43 reg_rev--;
44 }
45
46 if (start_num != 0)
47 n += scnprintf(buf + n, len - n, "\n\n");
48 27
49 /* To continue printing callee regs on same line as scratch regs */28 pr_info("r00: 0x%08lx\tr01: 0x%08lx\tr02: 0x%08lx\n" \
50 if (start_num == 0)29 "r03: 0x%08lx\tr04: 0x%08lx\tr05: 0x%08lx\n" \
51 pr_info("%s", buf);30 "r06: 0x%08lx\tr07: 0x%08lx\tr08: 0x%08lx\n" \
52 else31 "r09: 0x%08lx\tr10: 0x%08lx\tr11: 0x%08lx\n" \
53 pr_cont("%s\n", buf);32 "r12: 0x%08lx\t",
33 regs->r0, regs->r1, regs->r2,
34 regs->r3, regs->r4, regs->r5,
35 regs->r6, regs->r7, regs->r8,
36 regs->r9, regs->r10, regs->r11,
37 regs->r12);
54}38}
55 39
56static void show_callee_regs(struct callee_regs *cregs)40static void print_regs_callee(struct callee_regs *regs)
57{41{
58 print_reg_file(&(cregs->r13), 13);42 pr_cont("r13: 0x%08lx\tr14: 0x%08lx\n" \
43 "r15: 0x%08lx\tr16: 0x%08lx\tr17: 0x%08lx\n" \
44 "r18: 0x%08lx\tr19: 0x%08lx\tr20: 0x%08lx\n" \
45 "r21: 0x%08lx\tr22: 0x%08lx\tr23: 0x%08lx\n" \
46 "r24: 0x%08lx\tr25: 0x%08lx\n",
47 regs->r13, regs->r14,
48 regs->r15, regs->r16, regs->r17,
49 regs->r18, regs->r19, regs->r20,
50 regs->r21, regs->r22, regs->r23,
51 regs->r24, regs->r25);
59}52}
60 53
61static void print_task_path_n_nm(struct task_struct *tsk)54static void print_task_path_n_nm(struct task_struct *tsk)
@@ -175,7 +168,7 @@ static void show_ecr_verbose(struct pt_regs *regs) · 113 unmodified lines
175void show_regs(struct pt_regs *regs)168void show_regs(struct pt_regs *regs)
176{169{
177 struct task_struct *tsk = current;170 struct task_struct *tsk = current;
178 struct callee_regs *cregs;171 struct callee_regs *cregs = (struct callee_regs *)tsk->thread.callee_reg;
179 172
180 /*173 /*
181 * generic code calls us with preemption disabled, but some calls174 * generic code calls us with preemption disabled, but some calls
@@ -204,25 +197,15 @@ void show_regs(struct pt_regs *regs) · 22 unmodified lines
204 STS_BIT(regs, A2), STS_BIT(regs, A1),197 STS_BIT(regs, A2), STS_BIT(regs, A1),
205 STS_BIT(regs, E2), STS_BIT(regs, E1));198 STS_BIT(regs, E2), STS_BIT(regs, E1));
206#else199#else
207 pr_cont(" [%2s%2s%2s%2s]",200 pr_cont(" [%2s%2s%2s%2s] ",
208 STS_BIT(regs, IE),201 STS_BIT(regs, IE),
209 (regs->status32 & STATUS_U_MASK) ? "U " : "K ",202 (regs->status32 & STATUS_U_MASK) ? "U " : "K ",
210 STS_BIT(regs, DE), STS_BIT(regs, AE));203 STS_BIT(regs, DE), STS_BIT(regs, AE));
211#endif204#endif
212 pr_cont(" BTA: 0x%08lx\n SP: 0x%08lx FP: 0x%08lx BLK: %pS\n",
213 regs->bta, regs->sp, regs->fp, (void *)regs->blink);
214 pr_info("LPS: 0x%08lx\tLPE: 0x%08lx\tLPC: 0x%08lx\n",
215 regs->lp_start, regs->lp_end, regs->lp_count);
216
217 /* print regs->r0 thru regs->r12
218 * Sequential printing was generating horrible code
219 */
220 print_reg_file(&(regs->r0), 0);
221 205
222 /* If Callee regs were saved, display them too */206 print_regs_scratch(regs);
223 cregs = (struct callee_regs *)current->thread.callee_reg;
224 if (cregs)207 if (cregs)
225 show_callee_regs(cregs);208 print_regs_callee(cregs);
226 209
227 preempt_disable();210 preempt_disable();
228}211}
arch/arc/kernel/unwind.c+3−3
@@ -572,7 +572,7 @@ static unsigned long read_pointer(const u8 **pLoc, const void *end, · 571 unmodified lines
572#else572#else
573 BUILD_BUG_ON(sizeof(u32) != sizeof(value));573 BUILD_BUG_ON(sizeof(u32) != sizeof(value));
574#endif574#endif
575 /* Fall through */575 fallthrough;
576 case DW_EH_PE_native:576 case DW_EH_PE_native:
577 if (end < (const void *)(ptr.pul + 1))577 if (end < (const void *)(ptr.pul + 1))
578 return 0;578 return 0;
@@ -827,7 +827,7 @@ static int processCFI(const u8 *start, const u8 *end, unsigned long targetLoc, · 248 unmodified lines
827 case DW_CFA_def_cfa:827 case DW_CFA_def_cfa:
828 state->cfa.reg = get_uleb128(&ptr.p8, end);828 state->cfa.reg = get_uleb128(&ptr.p8, end);
829 unw_debug("cfa_def_cfa: r%lu ", state->cfa.reg);829 unw_debug("cfa_def_cfa: r%lu ", state->cfa.reg);
830 /* fall through */830 fallthrough;
831 case DW_CFA_def_cfa_offset:831 case DW_CFA_def_cfa_offset:
832 state->cfa.offs = get_uleb128(&ptr.p8, end);832 state->cfa.offs = get_uleb128(&ptr.p8, end);
833 unw_debug("cfa_def_cfa_offset: 0x%lx ",833 unw_debug("cfa_def_cfa_offset: 0x%lx ",
@@ -835,7 +835,7 @@ static int processCFI(const u8 *start, const u8 *end, unsigned long targetLoc, · 1 unmodified line
835 break;835 break;
836 case DW_CFA_def_cfa_sf:836 case DW_CFA_def_cfa_sf:
837 state->cfa.reg = get_uleb128(&ptr.p8, end);837 state->cfa.reg = get_uleb128(&ptr.p8, end);
838 /* fall through */838 fallthrough;
839 case DW_CFA_def_cfa_offset_sf:839 case DW_CFA_def_cfa_offset_sf:
840 state->cfa.offs = get_sleb128(&ptr.p8, end)840 state->cfa.offs = get_sleb128(&ptr.p8, end)
841 * state->dataAlign;841 * state->dataAlign;
arch/arc/mm/init.c+16−11
@@ -26,8 +26,8 @@ static unsigned long low_mem_sz; · 25 unmodified lines
26 26
27#ifdef CONFIG_HIGHMEM27#ifdef CONFIG_HIGHMEM
28static unsigned long min_high_pfn, max_high_pfn;28static unsigned long min_high_pfn, max_high_pfn;
29static u64 high_mem_start;29static phys_addr_t high_mem_start;
30static u64 high_mem_sz;30static phys_addr_t high_mem_sz;
31#endif31#endif
32 32
33#ifdef CONFIG_DISCONTIGMEM33#ifdef CONFIG_DISCONTIGMEM
@@ -69,6 +69,7 @@ void __init early_init_dt_add_memory_arch(u64 base, u64 size) · 35 unmodified lines
69 high_mem_sz = size;69 high_mem_sz = size;
70 in_use = 1;70 in_use = 1;
71 memblock_add_node(base, size, 1);71 memblock_add_node(base, size, 1);
72 memblock_reserve(base, size);
72#endif73#endif
73 }74 }
74 75
@@ -157,7 +158,7 @@ void __init setup_arch_memory(void) · 82 unmodified lines
157 min_high_pfn = PFN_DOWN(high_mem_start);158 min_high_pfn = PFN_DOWN(high_mem_start);
158 max_high_pfn = PFN_DOWN(high_mem_start + high_mem_sz);159 max_high_pfn = PFN_DOWN(high_mem_start + high_mem_sz);
159 160
160 max_zone_pfn[ZONE_HIGHMEM] = max_high_pfn;161 max_zone_pfn[ZONE_HIGHMEM] = min_low_pfn;
161 162
162 high_memory = (void *)(min_high_pfn << PAGE_SHIFT);163 high_memory = (void *)(min_high_pfn << PAGE_SHIFT);
163 kmap_init();164 kmap_init();
@@ -166,22 +167,26 @@ void __init setup_arch_memory(void) · 2 unmodified lines
166 free_area_init(max_zone_pfn);167 free_area_init(max_zone_pfn);
167}168}
168 169
169/*170static void __init highmem_init(void)
170 * mem_init - initializes memory
171 *
172 * Frees up bootmem
173 * Calculates and displays memory available/used
174 */
175void __init mem_init(void)
176{171{
177#ifdef CONFIG_HIGHMEM172#ifdef CONFIG_HIGHMEM
178 unsigned long tmp;173 unsigned long tmp;
179 174
180 reset_all_zones_managed_pages();175 memblock_free(high_mem_start, high_mem_sz);
181 for (tmp = min_high_pfn; tmp < max_high_pfn; tmp++)176 for (tmp = min_high_pfn; tmp < max_high_pfn; tmp++)
182 free_highmem_page(pfn_to_page(tmp));177 free_highmem_page(pfn_to_page(tmp));
183#endif178#endif
179}
184 180
181/*
182 * mem_init - initializes memory
183 *
184 * Frees up bootmem
185 * Calculates and displays memory available/used
186 */
187void __init mem_init(void)
188{
185 memblock_free_all();189 memblock_free_all();
190 highmem_init();
186 mem_init_print_info(NULL);191 mem_init_print_info(NULL);
187}192}
arch/arc/plat-eznps/include/plat/ctop.h+0−1
@@ -33,7 +33,6 @@ · 32 unmodified lines
33#define CTOP_AUX_DPC (CTOP_AUX_BASE + 0x02C)33#define CTOP_AUX_DPC (CTOP_AUX_BASE + 0x02C)
34#define CTOP_AUX_LPC (CTOP_AUX_BASE + 0x030)34#define CTOP_AUX_LPC (CTOP_AUX_BASE + 0x030)
35#define CTOP_AUX_EFLAGS (CTOP_AUX_BASE + 0x080)35#define CTOP_AUX_EFLAGS (CTOP_AUX_BASE + 0x080)
36#define CTOP_AUX_IACK (CTOP_AUX_BASE + 0x088)
37#define CTOP_AUX_GPA1 (CTOP_AUX_BASE + 0x08C)36#define CTOP_AUX_GPA1 (CTOP_AUX_BASE + 0x08C)
38#define CTOP_AUX_UDMC (CTOP_AUX_BASE + 0x300)37#define CTOP_AUX_UDMC (CTOP_AUX_BASE + 0x300)
39 38
arch/arm/kernel/hw_breakpoint.c+5−5
@@ -547,7 +547,7 @@ static int arch_build_bp_info(struct perf_event *bp, · 546 unmodified lines
547 if ((hw->ctrl.type != ARM_BREAKPOINT_EXECUTE)547 if ((hw->ctrl.type != ARM_BREAKPOINT_EXECUTE)
548 && max_watchpoint_len >= 8)548 && max_watchpoint_len >= 8)
549 break;549 break;
550 /* Else, fall through */550 fallthrough;
551 default:551 default:
552 return -EINVAL;552 return -EINVAL;
553 }553 }
@@ -612,12 +612,12 @@ int hw_breakpoint_arch_parse(struct perf_event *bp, · 58 unmodified lines
612 /* Allow halfword watchpoints and breakpoints. */612 /* Allow halfword watchpoints and breakpoints. */
613 if (hw->ctrl.len == ARM_BREAKPOINT_LEN_2)613 if (hw->ctrl.len == ARM_BREAKPOINT_LEN_2)
614 break;614 break;
615 /* Else, fall through */615 fallthrough;
616 case 3:616 case 3:
617 /* Allow single byte watchpoint. */617 /* Allow single byte watchpoint. */
618 if (hw->ctrl.len == ARM_BREAKPOINT_LEN_1)618 if (hw->ctrl.len == ARM_BREAKPOINT_LEN_1)
619 break;619 break;
620 /* Else, fall through */620 fallthrough;
621 default:621 default:
622 ret = -EINVAL;622 ret = -EINVAL;
623 goto out;623 goto out;
@@ -884,7 +884,7 @@ static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr, · 260 unmodified lines
884 break;884 break;
885 case ARM_ENTRY_ASYNC_WATCHPOINT:885 case ARM_ENTRY_ASYNC_WATCHPOINT:
886 WARN(1, "Asynchronous watchpoint exception taken. Debugging results may be unreliable\n");886 WARN(1, "Asynchronous watchpoint exception taken. Debugging results may be unreliable\n");
887 /* Fall through */887 fallthrough;
888 case ARM_ENTRY_SYNC_WATCHPOINT:888 case ARM_ENTRY_SYNC_WATCHPOINT:
889 watchpoint_handler(addr, fsr, regs);889 watchpoint_handler(addr, fsr, regs);
890 break;890 break;
@@ -933,7 +933,7 @@ static bool core_has_os_save_restore(void) · 42 unmodified lines
933 ARM_DBG_READ(c1, c1, 4, oslsr);933 ARM_DBG_READ(c1, c1, 4, oslsr);
934 if (oslsr & ARM_OSLSR_OSLM0)934 if (oslsr & ARM_OSLSR_OSLM0)
935 return true;935 return true;
936 /* Else, fall through */936 fallthrough;
937 default:937 default:
938 return false;938 return false;
939 }939 }
arch/arm/kernel/signal.c+1−1
@@ -596,7 +596,7 @@ static int do_signal(struct pt_regs *regs, int syscall) · 595 unmodified lines
596 switch (retval) {596 switch (retval) {
597 case -ERESTART_RESTARTBLOCK:597 case -ERESTART_RESTARTBLOCK:
598 restart -= 2;598 restart -= 2;
599 /* Fall through */599 fallthrough;
600 case -ERESTARTNOHAND:600 case -ERESTARTNOHAND:
601 case -ERESTARTSYS:601 case -ERESTARTSYS:
602 case -ERESTARTNOINTR:602 case -ERESTARTNOINTR:
arch/arm/mach-ep93xx/crunch.c+1−1
@@ -49,7 +49,7 @@ static int crunch_do(struct notifier_block *self, unsigned long cmd, void *t) · 48 unmodified lines
49 * FALLTHROUGH: Ensure we don't try to overwrite our newly49 * FALLTHROUGH: Ensure we don't try to overwrite our newly
50 * initialised state information on the first fault.50 * initialised state information on the first fault.
51 */51 */
52 /* Fall through */52 fallthrough;
53 53
54 case THREAD_NOTIFY_EXIT:54 case THREAD_NOTIFY_EXIT:
55 crunch_task_release(thread);55 crunch_task_release(thread);
arch/arm/mach-mmp/pm-mmp2.c+4−4
@@ -123,19 +123,19 @@ void mmp2_pm_enter_lowpower_mode(int state) · 122 unmodified lines
123 case POWER_MODE_SYS_SLEEP:123 case POWER_MODE_SYS_SLEEP:
124 apcr |= MPMU_PCR_PJ_SLPEN; /* set the SLPEN bit */124 apcr |= MPMU_PCR_PJ_SLPEN; /* set the SLPEN bit */
125 apcr |= MPMU_PCR_PJ_VCTCXOSD; /* set VCTCXOSD */125 apcr |= MPMU_PCR_PJ_VCTCXOSD; /* set VCTCXOSD */
126 /* fall through */126 fallthrough;
127 case POWER_MODE_CHIP_SLEEP:127 case POWER_MODE_CHIP_SLEEP:
128 apcr |= MPMU_PCR_PJ_SLPEN;128 apcr |= MPMU_PCR_PJ_SLPEN;
129 /* fall through */129 fallthrough;
130 case POWER_MODE_APPS_SLEEP:130 case POWER_MODE_APPS_SLEEP:
131 apcr |= MPMU_PCR_PJ_APBSD; /* set APBSD */131 apcr |= MPMU_PCR_PJ_APBSD; /* set APBSD */
132 /* fall through */132 fallthrough;
133 case POWER_MODE_APPS_IDLE:133 case POWER_MODE_APPS_IDLE:
134 apcr |= MPMU_PCR_PJ_AXISD; /* set AXISDD bit */134 apcr |= MPMU_PCR_PJ_AXISD; /* set AXISDD bit */
135 apcr |= MPMU_PCR_PJ_DDRCORSD; /* set DDRCORSD bit */135 apcr |= MPMU_PCR_PJ_DDRCORSD; /* set DDRCORSD bit */
136 idle_cfg |= APMU_PJ_IDLE_CFG_PJ_PWRDWN; /* PJ power down */136 idle_cfg |= APMU_PJ_IDLE_CFG_PJ_PWRDWN; /* PJ power down */
137 apcr |= MPMU_PCR_PJ_SPSD;137 apcr |= MPMU_PCR_PJ_SPSD;
138 /* fall through */138 fallthrough;
139 case POWER_MODE_CORE_EXTIDLE:139 case POWER_MODE_CORE_EXTIDLE:
140 idle_cfg |= APMU_PJ_IDLE_CFG_PJ_IDLE; /* set the IDLE bit */140 idle_cfg |= APMU_PJ_IDLE_CFG_PJ_IDLE; /* set the IDLE bit */
141 idle_cfg &= ~APMU_PJ_IDLE_CFG_ISO_MODE_CNTRL_MASK;141 idle_cfg &= ~APMU_PJ_IDLE_CFG_ISO_MODE_CNTRL_MASK;
arch/arm/mach-mmp/pm-pxa910.c+5−5
@@ -145,23 +145,23 @@ void pxa910_pm_enter_lowpower_mode(int state) · 144 unmodified lines
145 case POWER_MODE_UDR:145 case POWER_MODE_UDR:
146 /* only shutdown APB in UDR */146 /* only shutdown APB in UDR */
147 apcr |= MPMU_APCR_STBYEN | MPMU_APCR_APBSD;147 apcr |= MPMU_APCR_STBYEN | MPMU_APCR_APBSD;
148 /* fall through */148 fallthrough;
149 case POWER_MODE_SYS_SLEEP:149 case POWER_MODE_SYS_SLEEP:
150 apcr |= MPMU_APCR_SLPEN; /* set the SLPEN bit */150 apcr |= MPMU_APCR_SLPEN; /* set the SLPEN bit */
151 apcr |= MPMU_APCR_VCTCXOSD; /* set VCTCXOSD */151 apcr |= MPMU_APCR_VCTCXOSD; /* set VCTCXOSD */
152 /* fall through */152 fallthrough;
153 case POWER_MODE_APPS_SLEEP:153 case POWER_MODE_APPS_SLEEP:
154 apcr |= MPMU_APCR_DDRCORSD; /* set DDRCORSD */154 apcr |= MPMU_APCR_DDRCORSD; /* set DDRCORSD */
155 /* fall through */155 fallthrough;
156 case POWER_MODE_APPS_IDLE:156 case POWER_MODE_APPS_IDLE:
157 apcr |= MPMU_APCR_AXISD; /* set AXISDD bit */157 apcr |= MPMU_APCR_AXISD; /* set AXISDD bit */
158 /* fall through */158 fallthrough;
159 case POWER_MODE_CORE_EXTIDLE:159 case POWER_MODE_CORE_EXTIDLE:
160 idle_cfg |= APMU_MOH_IDLE_CFG_MOH_IDLE;160 idle_cfg |= APMU_MOH_IDLE_CFG_MOH_IDLE;
161 idle_cfg |= APMU_MOH_IDLE_CFG_MOH_PWRDWN;161 idle_cfg |= APMU_MOH_IDLE_CFG_MOH_PWRDWN;
162 idle_cfg |= APMU_MOH_IDLE_CFG_MOH_PWR_SW(3)162 idle_cfg |= APMU_MOH_IDLE_CFG_MOH_PWR_SW(3)
163 | APMU_MOH_IDLE_CFG_MOH_L2_PWR_SW(3);163 | APMU_MOH_IDLE_CFG_MOH_L2_PWR_SW(3);
164 /* fall through */164 fallthrough;
165 case POWER_MODE_CORE_INTIDLE:165 case POWER_MODE_CORE_INTIDLE:
166 break;166 break;
167 }167 }
arch/arm/mach-omap2/id.c+0−8
@@ -396,7 +396,6 @@ void __init omap3xxx_check_revision(void) · 395 unmodified lines
396 cpu_rev = "3.1";396 cpu_rev = "3.1";
397 break;397 break;
398 case 7:398 case 7:
399 /* FALLTHROUGH */
400 default:399 default:
401 /* Use the latest known revision as default */400 /* Use the latest known revision as default */
402 omap_revision = OMAP3430_REV_ES3_1_2;401 omap_revision = OMAP3430_REV_ES3_1_2;
@@ -416,7 +415,6 @@ void __init omap3xxx_check_revision(void) · 13 unmodified lines
416 cpu_rev = "1.0";415 cpu_rev = "1.0";
417 break;416 break;
418 case 1:417 case 1:
419 /* FALLTHROUGH */
420 default:418 default:
421 omap_revision = AM35XX_REV_ES1_1;419 omap_revision = AM35XX_REV_ES1_1;
422 cpu_rev = "1.1";420 cpu_rev = "1.1";
@@ -435,7 +433,6 @@ void __init omap3xxx_check_revision(void) · 12 unmodified lines
435 cpu_rev = "1.1";433 cpu_rev = "1.1";
436 break;434 break;
437 case 2:435 case 2:
438 /* FALLTHROUGH */
439 default:436 default:
440 omap_revision = OMAP3630_REV_ES1_2;437 omap_revision = OMAP3630_REV_ES1_2;
441 cpu_rev = "1.2";438 cpu_rev = "1.2";
@@ -456,7 +453,6 @@ void __init omap3xxx_check_revision(void) · 14 unmodified lines
456 cpu_rev = "2.0";453 cpu_rev = "2.0";
457 break;454 break;
458 case 3:455 case 3:
459 /* FALLTHROUGH */
460 default:456 default:
461 omap_revision = TI8168_REV_ES2_1;457 omap_revision = TI8168_REV_ES2_1;
462 cpu_rev = "2.1";458 cpu_rev = "2.1";
@@ -473,7 +469,6 @@ void __init omap3xxx_check_revision(void) · 10 unmodified lines
473 cpu_rev = "2.0";469 cpu_rev = "2.0";
474 break;470 break;
475 case 2:471 case 2:
476 /* FALLTHROUGH */
477 default:472 default:
478 omap_revision = AM335X_REV_ES2_1;473 omap_revision = AM335X_REV_ES2_1;
479 cpu_rev = "2.1";474 cpu_rev = "2.1";
@@ -491,7 +486,6 @@ void __init omap3xxx_check_revision(void) · 11 unmodified lines
491 cpu_rev = "1.1";486 cpu_rev = "1.1";
492 break;487 break;
493 case 2:488 case 2:
494 /* FALLTHROUGH */
495 default:489 default:
496 omap_revision = AM437X_REV_ES1_2;490 omap_revision = AM437X_REV_ES1_2;
497 cpu_rev = "1.2";491 cpu_rev = "1.2";
@@ -502,7 +496,6 @@ void __init omap3xxx_check_revision(void) · 4 unmodified lines
502 case 0xb968:496 case 0xb968:
503 switch (rev) {497 switch (rev) {
504 case 0:498 case 0:
505 /* FALLTHROUGH */
506 case 1:499 case 1:
507 omap_revision = TI8148_REV_ES1_0;500 omap_revision = TI8148_REV_ES1_0;
508 cpu_rev = "1.0";501 cpu_rev = "1.0";
@@ -512,7 +505,6 @@ void __init omap3xxx_check_revision(void) · 3 unmodified lines
512 cpu_rev = "2.0";505 cpu_rev = "2.0";
513 break;506 break;
514 case 3:507 case 3:
515 /* FALLTHROUGH */
516 default:508 default:
517 omap_revision = TI8148_REV_ES2_1;509 omap_revision = TI8148_REV_ES2_1;
518 cpu_rev = "2.1";510 cpu_rev = "2.1";
arch/arm/mach-omap2/omap_device.c+1−1
@@ -240,7 +240,7 @@ static int _omap_device_notifier_call(struct notifier_block *nb, · 239 unmodified lines
240 if (pdev->dev.of_node)240 if (pdev->dev.of_node)
241 omap_device_build_from_dt(pdev);241 omap_device_build_from_dt(pdev);
242 omap_auxdata_legacy_init(dev);242 omap_auxdata_legacy_init(dev);
243 /* fall through */243 fallthrough;
244 default:244 default:
245 od = to_omap_device(pdev);245 od = to_omap_device(pdev);
246 if (od)246 if (od)
arch/arm/mach-omap2/pm34xx.c+0−4
@@ -298,11 +298,7 @@ static void omap3_pm_idle(void) · 297 unmodified lines
298 if (omap_irq_pending())298 if (omap_irq_pending())
299 return;299 return;
300 300
301 trace_cpu_idle_rcuidle(1, smp_processor_id());
302
303 omap_sram_idle();301 omap_sram_idle();
304
305 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
306}302}
307 303
308#ifdef CONFIG_SUSPEND304#ifdef CONFIG_SUSPEND
arch/arm/mach-orion5x/dns323-setup.c+1−1
@@ -624,7 +624,7 @@ static void __init dns323_init(void) · 623 unmodified lines
624 dns323ab_leds[0].active_low = 1;624 dns323ab_leds[0].active_low = 1;
625 gpio_request(DNS323_GPIO_LED_POWER1, "Power Led Enable");625 gpio_request(DNS323_GPIO_LED_POWER1, "Power Led Enable");
626 gpio_direction_output(DNS323_GPIO_LED_POWER1, 0);626 gpio_direction_output(DNS323_GPIO_LED_POWER1, 0);
627 /* Fall through */627 fallthrough;
628 case DNS323_REV_B1:628 case DNS323_REV_B1:
629 i2c_register_board_info(0, dns323ab_i2c_devices,629 i2c_register_board_info(0, dns323ab_i2c_devices,
630 ARRAY_SIZE(dns323ab_i2c_devices));630 ARRAY_SIZE(dns323ab_i2c_devices));
arch/arm/mach-rpc/riscpc.c+1−1
@@ -46,7 +46,7 @@ static int __init parse_tag_acorn(const struct tag *tag) · 45 unmodified lines
46 switch (tag->u.acorn.vram_pages) {46 switch (tag->u.acorn.vram_pages) {
47 case 512:47 case 512:
48 vram_size += PAGE_SIZE * 256;48 vram_size += PAGE_SIZE * 256;
49 /* Fall through - ??? */49 fallthrough; /* ??? */
50 case 256:50 case 256:
51 vram_size += PAGE_SIZE * 256;51 vram_size += PAGE_SIZE * 256;
52 default:52 default:
arch/arm/mach-tegra/reset.c+1−1
@@ -70,7 +70,7 @@ static void __init tegra_cpu_reset_handler_enable(void) · 69 unmodified lines
70 switch (err) {70 switch (err) {
71 case -ENOSYS:71 case -ENOSYS:
72 tegra_cpu_reset_handler_set(reset_address);72 tegra_cpu_reset_handler_set(reset_address);
73 /* fall through */73 fallthrough;
74 case 0:74 case 0:
75 is_enabled = true;75 is_enabled = true;
76 break;76 break;
arch/arm/mm/alignment.c+2−2
@@ -694,7 +694,7 @@ thumb2arm(u16 tinstr) · 693 unmodified lines
694 return subset[(L<<1) | ((tinstr & (1<<8)) >> 8)] |694 return subset[(L<<1) | ((tinstr & (1<<8)) >> 8)] |
695 (tinstr & 255); /* register_list */695 (tinstr & 255); /* register_list */
696 }696 }
697 /* Else, fall through - for illegal instruction case */697 fallthrough; /* for illegal instruction case */
698 698
699 default:699 default:
700 return BAD_INSTR;700 return BAD_INSTR;
@@ -750,7 +750,7 @@ do_alignment_t32_to_handler(u32 *pinstr, struct pt_regs *regs, · 49 unmodified lines
750 case 0xe8e0:750 case 0xe8e0:
751 case 0xe9e0:751 case 0xe9e0:
752 poffset->un = (tinst2 & 0xff) << 2;752 poffset->un = (tinst2 & 0xff) << 2;
753 /* Fall through */753 fallthrough;
754 754
755 case 0xe940:755 case 0xe940:
756 case 0xe9c0:756 case 0xe9c0:
arch/arm/mm/proc-v7-bugs.c+1−1
@@ -71,7 +71,7 @@ static void cpu_v7_spectre_init(void) · 70 unmodified lines
71 /* Other ARM CPUs require no workaround */71 /* Other ARM CPUs require no workaround */
72 if (read_cpuid_implementor() == ARM_CPU_IMP_ARM)72 if (read_cpuid_implementor() == ARM_CPU_IMP_ARM)
73 break;73 break;
74 /* fallthrough */74 fallthrough;
75 /* Cortex A57/A72 require firmware workaround */75 /* Cortex A57/A72 require firmware workaround */
76 case ARM_CPU_PART_CORTEX_A57:76 case ARM_CPU_PART_CORTEX_A57:
77 case ARM_CPU_PART_CORTEX_A72: {77 case ARM_CPU_PART_CORTEX_A72: {
arch/arm/plat-omap/dma.c+3−3
@@ -309,14 +309,14 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) · 308 unmodified lines
309 * not supported by current hardware on OMAP1309 * not supported by current hardware on OMAP1
310 * w |= (0x03 << 7);310 * w |= (0x03 << 7);
311 */311 */
312 /* fall through */312 fallthrough;
313 case OMAP_DMA_DATA_BURST_16:313 case OMAP_DMA_DATA_BURST_16:
314 if (dma_omap2plus()) {314 if (dma_omap2plus()) {
315 burst = 0x3;315 burst = 0x3;
316 break;316 break;
317 }317 }
318 /* OMAP1 don't support burst 16 */318 /* OMAP1 don't support burst 16 */
319 /* fall through */319 fallthrough;
320 default:320 default:
321 BUG();321 BUG();
322 }322 }
@@ -393,7 +393,7 @@ void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) · 70 unmodified lines
393 break;393 break;
394 }394 }
395 /* OMAP1 don't support burst 16 */395 /* OMAP1 don't support burst 16 */
396 /* fall through */396 fallthrough;
397 default:397 default:
398 printk(KERN_ERR "Invalid DMA burst mode\n");398 printk(KERN_ERR "Invalid DMA burst mode\n");
399 BUG();399 BUG();
arch/arm/probes/decode.c+1−1
@@ -307,7 +307,7 @@ static bool __kprobes decode_regs(probes_opcode_t *pinsn, u32 regs, bool modify) · 306 unmodified lines
307 case REG_TYPE_NOPCWB:307 case REG_TYPE_NOPCWB:
308 if (!is_writeback(insn))308 if (!is_writeback(insn))
309 break; /* No writeback, so any register is OK */309 break; /* No writeback, so any register is OK */
310 /* fall through... */310 fallthrough;
311 case REG_TYPE_NOPC:311 case REG_TYPE_NOPC:
312 case REG_TYPE_NOPCX:312 case REG_TYPE_NOPCX:
313 /* Reject PC (R15) */313 /* Reject PC (R15) */
arch/arm/probes/kprobes/core.c+1−1
@@ -280,7 +280,7 @@ void __kprobes kprobe_handler(struct pt_regs *regs) · 279 unmodified lines
280 /* A nested probe was hit in FIQ, it is a BUG */280 /* A nested probe was hit in FIQ, it is a BUG */
281 pr_warn("Unrecoverable kprobe detected.\n");281 pr_warn("Unrecoverable kprobe detected.\n");
282 dump_kprobe(p);282 dump_kprobe(p);
283 /* fall through */283 fallthrough;
284 default:284 default:
285 /* impossible cases */285 /* impossible cases */
286 BUG();286 BUG();
arch/arm64/Makefile+10−3
@@ -82,8 +82,8 @@ endif · 81 unmodified lines
82# compiler to generate them and consequently to break the single image contract82# compiler to generate them and consequently to break the single image contract
83# we pass it only to the assembler. This option is utilized only in case of non83# we pass it only to the assembler. This option is utilized only in case of non
84# integrated assemblers.84# integrated assemblers.
85ifneq ($(CONFIG_AS_HAS_ARMV8_4), y)85ifeq ($(CONFIG_AS_HAS_PAC), y)
86branch-prot-flags-$(CONFIG_AS_HAS_PAC) += -Wa,-march=armv8.3-a86asm-arch := armv8.3-a
87endif87endif
88endif88endif
89 89
@@ -91,7 +91,12 @@ KBUILD_CFLAGS += $(branch-prot-flags-y) · 1 unmodified line
91 91
92ifeq ($(CONFIG_AS_HAS_ARMV8_4), y)92ifeq ($(CONFIG_AS_HAS_ARMV8_4), y)
93# make sure to pass the newest target architecture to -march.93# make sure to pass the newest target architecture to -march.
94KBUILD_CFLAGS += -Wa,-march=armv8.4-a94asm-arch := armv8.4-a
95endif
96
97ifdef asm-arch
98KBUILD_CFLAGS += -Wa,-march=$(asm-arch) \
99 -DARM64_ASM_ARCH='"$(asm-arch)"'
95endif100endif
96 101
97ifeq ($(CONFIG_SHADOW_CALL_STACK), y)102ifeq ($(CONFIG_SHADOW_CALL_STACK), y)
@@ -165,6 +170,8 @@ zinstall install: · 67 unmodified lines
165PHONY += vdso_install170PHONY += vdso_install
166vdso_install:171vdso_install:
167 $(Q)$(MAKE) $(build)=arch/arm64/kernel/vdso $@172 $(Q)$(MAKE) $(build)=arch/arm64/kernel/vdso $@
173 $(if $(CONFIG_COMPAT_VDSO), \
174 $(Q)$(MAKE) $(build)=arch/arm64/kernel/vdso32 $@)
168 175
169# We use MRPROPER_FILES and CLEAN_FILES now176# We use MRPROPER_FILES and CLEAN_FILES now
170archclean:177archclean:
arch/arm64/boot/dts/mediatek/mt7622.dtsi+2−0
@@ -686,6 +686,8 @@ · 685 unmodified lines
686 clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,686 clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,
687 <&topckgen CLK_TOP_MSDC50_0_SEL>;687 <&topckgen CLK_TOP_MSDC50_0_SEL>;
688 clock-names = "source", "hclk";688 clock-names = "source", "hclk";
689 resets = <&pericfg MT7622_PERI_MSDC0_SW_RST>;
690 reset-names = "hrst";
689 status = "disabled";691 status = "disabled";
690 };692 };
691 693
arch/arm64/boot/dts/nvidia/tegra186.dtsi+12−8
@@ -337,8 +337,9 @@ · 336 unmodified lines
337 compatible = "nvidia,tegra186-sdhci";337 compatible = "nvidia,tegra186-sdhci";
338 reg = <0x0 0x03400000 0x0 0x10000>;338 reg = <0x0 0x03400000 0x0 0x10000>;
339 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;339 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
340 clocks = <&bpmp TEGRA186_CLK_SDMMC1>;340 clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
341 clock-names = "sdhci";341 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
342 clock-names = "sdhci", "tmclk";
342 resets = <&bpmp TEGRA186_RESET_SDMMC1>;343 resets = <&bpmp TEGRA186_RESET_SDMMC1>;
343 reset-names = "sdhci";344 reset-names = "sdhci";
344 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>,345 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>,
@@ -366,8 +367,9 @@ · 21 unmodified lines
366 compatible = "nvidia,tegra186-sdhci";367 compatible = "nvidia,tegra186-sdhci";
367 reg = <0x0 0x03420000 0x0 0x10000>;368 reg = <0x0 0x03420000 0x0 0x10000>;
368 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;369 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
369 clocks = <&bpmp TEGRA186_CLK_SDMMC2>;370 clocks = <&bpmp TEGRA186_CLK_SDMMC2>,
370 clock-names = "sdhci";371 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
372 clock-names = "sdhci", "tmclk";
371 resets = <&bpmp TEGRA186_RESET_SDMMC2>;373 resets = <&bpmp TEGRA186_RESET_SDMMC2>;
372 reset-names = "sdhci";374 reset-names = "sdhci";
373 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>,375 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>,
@@ -390,8 +392,9 @@ · 16 unmodified lines
390 compatible = "nvidia,tegra186-sdhci";392 compatible = "nvidia,tegra186-sdhci";
391 reg = <0x0 0x03440000 0x0 0x10000>;393 reg = <0x0 0x03440000 0x0 0x10000>;
392 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;394 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&bpmp TEGRA186_CLK_SDMMC3>;395 clocks = <&bpmp TEGRA186_CLK_SDMMC3>,
394 clock-names = "sdhci";396 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
397 clock-names = "sdhci", "tmclk";
395 resets = <&bpmp TEGRA186_RESET_SDMMC3>;398 resets = <&bpmp TEGRA186_RESET_SDMMC3>;
396 reset-names = "sdhci";399 reset-names = "sdhci";
397 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>,400 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>,
@@ -416,8 +419,9 @@ · 18 unmodified lines
416 compatible = "nvidia,tegra186-sdhci";419 compatible = "nvidia,tegra186-sdhci";
417 reg = <0x0 0x03460000 0x0 0x10000>;420 reg = <0x0 0x03460000 0x0 0x10000>;
418 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;421 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
419 clocks = <&bpmp TEGRA186_CLK_SDMMC4>;422 clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
420 clock-names = "sdhci";423 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
424 clock-names = "sdhci", "tmclk";
421 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>,425 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
422 <&bpmp TEGRA186_CLK_PLLC4_VCO>;426 <&bpmp TEGRA186_CLK_PLLC4_VCO>;
423 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>;427 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>;
arch/arm64/boot/dts/nvidia/tegra194.dtsi+9−6
@@ -460,8 +460,9 @@ · 459 unmodified lines
460 compatible = "nvidia,tegra194-sdhci";460 compatible = "nvidia,tegra194-sdhci";
461 reg = <0x03400000 0x10000>;461 reg = <0x03400000 0x10000>;
462 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;462 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
463 clocks = <&bpmp TEGRA194_CLK_SDMMC1>;463 clocks = <&bpmp TEGRA194_CLK_SDMMC1>,
464 clock-names = "sdhci";464 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
465 clock-names = "sdhci", "tmclk";
465 resets = <&bpmp TEGRA194_RESET_SDMMC1>;466 resets = <&bpmp TEGRA194_RESET_SDMMC1>;
466 reset-names = "sdhci";467 reset-names = "sdhci";
467 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>,468 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>,
@@ -485,8 +486,9 @@ · 17 unmodified lines
485 compatible = "nvidia,tegra194-sdhci";486 compatible = "nvidia,tegra194-sdhci";
486 reg = <0x03440000 0x10000>;487 reg = <0x03440000 0x10000>;
487 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;488 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
488 clocks = <&bpmp TEGRA194_CLK_SDMMC3>;489 clocks = <&bpmp TEGRA194_CLK_SDMMC3>,
489 clock-names = "sdhci";490 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
491 clock-names = "sdhci", "tmclk";
490 resets = <&bpmp TEGRA194_RESET_SDMMC3>;492 resets = <&bpmp TEGRA194_RESET_SDMMC3>;
491 reset-names = "sdhci";493 reset-names = "sdhci";
492 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>,494 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>,
@@ -511,8 +513,9 @@ · 18 unmodified lines
511 compatible = "nvidia,tegra194-sdhci";513 compatible = "nvidia,tegra194-sdhci";
512 reg = <0x03460000 0x10000>;514 reg = <0x03460000 0x10000>;
513 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;515 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
514 clocks = <&bpmp TEGRA194_CLK_SDMMC4>;516 clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
515 clock-names = "sdhci";517 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
518 clock-names = "sdhci", "tmclk";
516 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>,519 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
517 <&bpmp TEGRA194_CLK_PLLC4>;520 <&bpmp TEGRA194_CLK_PLLC4>;
518 assigned-clock-parents =521 assigned-clock-parents =
arch/arm64/boot/dts/nvidia/tegra210.dtsi+12−8
@@ -1194,8 +1194,9 @@ · 1193 unmodified lines
1194 compatible = "nvidia,tegra210-sdhci";1194 compatible = "nvidia,tegra210-sdhci";
1195 reg = <0x0 0x700b0000 0x0 0x200>;1195 reg = <0x0 0x700b0000 0x0 0x200>;
1196 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;1196 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1197 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>;1197 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>,
1198 clock-names = "sdhci";1198 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
1199 clock-names = "sdhci", "tmclk";
1199 resets = <&tegra_car 14>;1200 resets = <&tegra_car 14>;
1200 reset-names = "sdhci";1201 reset-names = "sdhci";
1201 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",1202 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
@@ -1222,8 +1223,9 @@ · 20 unmodified lines
1222 compatible = "nvidia,tegra210-sdhci";1223 compatible = "nvidia,tegra210-sdhci";
1223 reg = <0x0 0x700b0200 0x0 0x200>;1224 reg = <0x0 0x700b0200 0x0 0x200>;
1224 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;1225 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1225 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>;1226 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>,
1226 clock-names = "sdhci";1227 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
1228 clock-names = "sdhci", "tmclk";
1227 resets = <&tegra_car 9>;1229 resets = <&tegra_car 9>;
1228 reset-names = "sdhci";1230 reset-names = "sdhci";
1229 pinctrl-names = "sdmmc-1v8-drv";1231 pinctrl-names = "sdmmc-1v8-drv";
@@ -1239,8 +1241,9 @@ · 9 unmodified lines
1239 compatible = "nvidia,tegra210-sdhci";1241 compatible = "nvidia,tegra210-sdhci";
1240 reg = <0x0 0x700b0400 0x0 0x200>;1242 reg = <0x0 0x700b0400 0x0 0x200>;
1241 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;1243 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1242 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>;1244 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>,
1243 clock-names = "sdhci";1245 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
1246 clock-names = "sdhci", "tmclk";
1244 resets = <&tegra_car 69>;1247 resets = <&tegra_car 69>;
1245 reset-names = "sdhci";1248 reset-names = "sdhci";
1246 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",1249 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
@@ -1262,8 +1265,9 @@ · 15 unmodified lines
1262 compatible = "nvidia,tegra210-sdhci";1265 compatible = "nvidia,tegra210-sdhci";
1263 reg = <0x0 0x700b0600 0x0 0x200>;1266 reg = <0x0 0x700b0600 0x0 0x200>;
1264 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;1267 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1265 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>;1268 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
1266 clock-names = "sdhci";1269 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
1270 clock-names = "sdhci", "tmclk";
1267 resets = <&tegra_car 15>;1271 resets = <&tegra_car 15>;
1268 reset-names = "sdhci";1272 reset-names = "sdhci";
1269 pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv";1273 pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv";
arch/arm64/boot/dts/ti/k3-am65-main.dtsi+17−19
@@ -417,10 +417,10 @@ · 416 unmodified lines
417 ti,intr-trigger-type = <1>;417 ti,intr-trigger-type = <1>;
418 interrupt-controller;418 interrupt-controller;
419 interrupt-parent = <&gic500>;419 interrupt-parent = <&gic500>;
420 #interrupt-cells = <2>;420 #interrupt-cells = <1>;
421 ti,sci = <&dmsc>;421 ti,sci = <&dmsc>;
422 ti,sci-dst-id = <56>;422 ti,sci-dev-id = <100>;
423 ti,sci-rm-range-girq = <0x1>;423 ti,interrupt-ranges = <0 392 32>;
424 };424 };
425 425
426 main_navss {426 main_navss {
@@ -438,10 +438,11 @@ · 11 unmodified lines
438 ti,intr-trigger-type = <4>;438 ti,intr-trigger-type = <4>;
439 interrupt-controller;439 interrupt-controller;
440 interrupt-parent = <&gic500>;440 interrupt-parent = <&gic500>;
441 #interrupt-cells = <2>;441 #interrupt-cells = <1>;
442 ti,sci = <&dmsc>;442 ti,sci = <&dmsc>;
443 ti,sci-dst-id = <56>;443 ti,sci-dev-id = <182>;
444 ti,sci-rm-range-girq = <0x0>, <0x2>;444 ti,interrupt-ranges = <0 64 64>,
445 <64 448 64>;
445 };446 };
446 447
447 inta_main_udmass: interrupt-controller@33d00000 {448 inta_main_udmass: interrupt-controller@33d00000 {
@@ -452,8 +453,7 @@ · 4 unmodified lines
452 msi-controller;453 msi-controller;
453 ti,sci = <&dmsc>;454 ti,sci = <&dmsc>;
454 ti,sci-dev-id = <179>;455 ti,sci-dev-id = <179>;
455 ti,sci-rm-range-vint = <0x0>;456 ti,interrupt-ranges = <0 0 256>;
456 ti,sci-rm-range-global-event = <0x1>;
457 };457 };
458 458
459 secure_proxy_main: mailbox@32c00000 {459 secure_proxy_main: mailbox@32c00000 {
@@ -589,7 +589,7 @@ · 129 unmodified lines
589 <0x0 0x33000000 0x0 0x40000>;589 <0x0 0x33000000 0x0 0x40000>;
590 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";590 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
591 ti,num-rings = <818>;591 ti,num-rings = <818>;
592 ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */592 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
593 ti,dma-ring-reset-quirk;593 ti,dma-ring-reset-quirk;
594 ti,sci = <&dmsc>;594 ti,sci = <&dmsc>;
595 ti,sci-dev-id = <187>;595 ti,sci-dev-id = <187>;
@@ -609,11 +609,11 @@ · 13 unmodified lines
609 ti,sci-dev-id = <188>;609 ti,sci-dev-id = <188>;
610 ti,ringacc = <&ringacc>;610 ti,ringacc = <&ringacc>;
611 611
612 ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */612 ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
613 <0x2>; /* TX_CHAN */613 <0xd>; /* TX_CHAN */
614 ti,sci-rm-range-rchan = <0x4>, /* RX_HCHAN */614 ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
615 <0x5>; /* RX_CHAN */615 <0xa>; /* RX_CHAN */
616 ti,sci-rm-range-rflow = <0x6>; /* GP RFLOW */616 ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
617 };617 };
618 618
619 cpts@310d0000 {619 cpts@310d0000 {
@@ -622,7 +622,7 @@ · 2 unmodified lines
622 reg-names = "cpts";622 reg-names = "cpts";
623 clocks = <&main_cpts_mux>;623 clocks = <&main_cpts_mux>;
624 clock-names = "cpts";624 clock-names = "cpts";
625 interrupts-extended = <&intr_main_navss 163 0>;625 interrupts-extended = <&intr_main_navss 391>;
626 interrupt-names = "cpts";626 interrupt-names = "cpts";
627 ti,cpts-periodic-outputs = <6>;627 ti,cpts-periodic-outputs = <6>;
628 ti,cpts-ext-ts-inputs = <8>;628 ti,cpts-ext-ts-inputs = <8>;
@@ -645,8 +645,7 @@ · 16 unmodified lines
645 gpio-controller;645 gpio-controller;
646 #gpio-cells = <2>;646 #gpio-cells = <2>;
647 interrupt-parent = <&intr_main_gpio>;647 interrupt-parent = <&intr_main_gpio>;
648 interrupts = <57 256>, <57 257>, <57 258>, <57 259>, <57 260>,648 interrupts = <192>, <193>, <194>, <195>, <196>, <197>;
649 <57 261>;
650 interrupt-controller;649 interrupt-controller;
651 #interrupt-cells = <2>;650 #interrupt-cells = <2>;
652 ti,ngpio = <96>;651 ti,ngpio = <96>;
@@ -661,8 +660,7 @@ · 8 unmodified lines
661 gpio-controller;660 gpio-controller;
662 #gpio-cells = <2>;661 #gpio-cells = <2>;
663 interrupt-parent = <&intr_main_gpio>;662 interrupt-parent = <&intr_main_gpio>;
664 interrupts = <58 256>, <58 257>, <58 258>, <58 259>, <58 260>,663 interrupts = <200>, <201>, <202>, <203>, <204>, <205>;
665 <58 261>;
666 interrupt-controller;664 interrupt-controller;
667 #interrupt-cells = <2>;665 #interrupt-cells = <2>;
668 ti,ngpio = <90>;666 ti,ngpio = <90>;
arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi+6−6
@@ -134,7 +134,7 @@ · 133 unmodified lines
134 <0x0 0x2a500000 0x0 0x40000>;134 <0x0 0x2a500000 0x0 0x40000>;
135 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";135 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
136 ti,num-rings = <286>;136 ti,num-rings = <286>;
137 ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */137 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
138 ti,dma-ring-reset-quirk;138 ti,dma-ring-reset-quirk;
139 ti,sci = <&dmsc>;139 ti,sci = <&dmsc>;
140 ti,sci-dev-id = <195>;140 ti,sci-dev-id = <195>;
@@ -154,11 +154,11 @@ · 13 unmodified lines
154 ti,sci-dev-id = <194>;154 ti,sci-dev-id = <194>;
155 ti,ringacc = <&mcu_ringacc>;155 ti,ringacc = <&mcu_ringacc>;
156 156
157 ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */157 ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
158 <0x2>; /* TX_CHAN */158 <0xd>; /* TX_CHAN */
159 ti,sci-rm-range-rchan = <0x3>, /* RX_HCHAN */159 ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
160 <0x4>; /* RX_CHAN */160 <0xa>; /* RX_CHAN */
161 ti,sci-rm-range-rflow = <0x5>; /* GP RFLOW */161 ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
162 };162 };
163 };163 };
164 164
arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi+4−4
@@ -74,10 +74,10 @@ · 73 unmodified lines
74 ti,intr-trigger-type = <1>;74 ti,intr-trigger-type = <1>;
75 interrupt-controller;75 interrupt-controller;
76 interrupt-parent = <&gic500>;76 interrupt-parent = <&gic500>;
77 #interrupt-cells = <2>;77 #interrupt-cells = <1>;
78 ti,sci = <&dmsc>;78 ti,sci = <&dmsc>;
79 ti,sci-dst-id = <56>;79 ti,sci-dev-id = <156>;
80 ti,sci-rm-range-girq = <0x4>;80 ti,interrupt-ranges = <0 712 16>;
81 };81 };
82 82
83 wkup_gpio0: wkup_gpio0@42110000 {83 wkup_gpio0: wkup_gpio0@42110000 {
@@ -86,7 +86,7 @@ · 2 unmodified lines
86 gpio-controller;86 gpio-controller;
87 #gpio-cells = <2>;87 #gpio-cells = <2>;
88 interrupt-parent = <&intr_wkup_gpio>;88 interrupt-parent = <&intr_wkup_gpio>;
89 interrupts = <59 128>, <59 129>, <59 130>, <59 131>;89 interrupts = <60>, <61>, <62>, <63>;
90 interrupt-controller;90 interrupt-controller;
91 #interrupt-cells = <2>;91 #interrupt-cells = <2>;
92 ti,ngpio = <56>;92 ti,ngpio = <56>;
arch/arm64/boot/dts/ti/k3-am654-base-board.dts+2−2
@@ -384,7 +384,7 @@ · 383 unmodified lines
384};384};
385 385
386&mailbox0_cluster0 {386&mailbox0_cluster0 {
387 interrupts = <164 0>;387 interrupts = <436>;
388 388
389 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {389 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
390 ti,mbox-tx = <1 0 0>;390 ti,mbox-tx = <1 0 0>;
@@ -393,7 +393,7 @@ · 2 unmodified lines
393};393};
394 394
395&mailbox0_cluster1 {395&mailbox0_cluster1 {
396 interrupts = <165 0>;396 interrupts = <432>;
397 397
398 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {398 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
399 ti,mbox-tx = <1 0 0>;399 ti,mbox-tx = <1 0 0>;
arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts+5−5
@@ -287,7 +287,7 @@ · 286 unmodified lines
287};287};
288 288
289&mailbox0_cluster0 {289&mailbox0_cluster0 {
290 interrupts = <214 0>;290 interrupts = <436>;
291 291
292 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {292 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
293 ti,mbox-rx = <0 0 0>;293 ti,mbox-rx = <0 0 0>;
@@ -301,7 +301,7 @@ · 7 unmodified lines
301};301};
302 302
303&mailbox0_cluster1 {303&mailbox0_cluster1 {
304 interrupts = <215 0>;304 interrupts = <432>;
305 305
306 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {306 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
307 ti,mbox-rx = <0 0 0>;307 ti,mbox-rx = <0 0 0>;
@@ -315,7 +315,7 @@ · 7 unmodified lines
315};315};
316 316
317&mailbox0_cluster2 {317&mailbox0_cluster2 {
318 interrupts = <216 0>;318 interrupts = <428>;
319 319
320 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {320 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
321 ti,mbox-rx = <0 0 0>;321 ti,mbox-rx = <0 0 0>;
@@ -329,7 +329,7 @@ · 7 unmodified lines
329};329};
330 330
331&mailbox0_cluster3 {331&mailbox0_cluster3 {
332 interrupts = <217 0>;332 interrupts = <424>;
333 333
334 mbox_c66_0: mbox-c66-0 {334 mbox_c66_0: mbox-c66-0 {
335 ti,mbox-rx = <0 0 0>;335 ti,mbox-rx = <0 0 0>;
@@ -343,7 +343,7 @@ · 7 unmodified lines
343};343};
344 344
345&mailbox0_cluster4 {345&mailbox0_cluster4 {
346 interrupts = <218 0>;346 interrupts = <420>;
347 347
348 mbox_c71_0: mbox-c71-0 {348 mbox_c71_0: mbox-c71-0 {
349 ti,mbox-rx = <0 0 0>;349 ti,mbox-rx = <0 0 0>;
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi+22−21
@@ -80,10 +80,10 @@ · 79 unmodified lines
80 ti,intr-trigger-type = <1>;80 ti,intr-trigger-type = <1>;
81 interrupt-controller;81 interrupt-controller;
82 interrupt-parent = <&gic500>;82 interrupt-parent = <&gic500>;
83 #interrupt-cells = <2>;83 #interrupt-cells = <1>;
84 ti,sci = <&dmsc>;84 ti,sci = <&dmsc>;
85 ti,sci-dst-id = <14>;85 ti,sci-dev-id = <131>;
86 ti,sci-rm-range-girq = <0x1>;86 ti,interrupt-ranges = <8 392 56>;
87 };87 };
88 88
89 main_navss {89 main_navss {
@@ -101,10 +101,12 @@ · 11 unmodified lines
101 ti,intr-trigger-type = <4>;101 ti,intr-trigger-type = <4>;
102 interrupt-controller;102 interrupt-controller;
103 interrupt-parent = <&gic500>;103 interrupt-parent = <&gic500>;
104 #interrupt-cells = <2>;104 #interrupt-cells = <1>;
105 ti,sci = <&dmsc>;105 ti,sci = <&dmsc>;
106 ti,sci-dst-id = <14>;106 ti,sci-dev-id = <213>;
107 ti,sci-rm-range-girq = <0>, <2>;107 ti,interrupt-ranges = <0 64 64>,
108 <64 448 64>,
109 <128 672 64>;
108 };110 };
109 111
110 main_udmass_inta: interrupt-controller@33d00000 {112 main_udmass_inta: interrupt-controller@33d00000 {
@@ -115,8 +117,7 @@ · 4 unmodified lines
115 msi-controller;117 msi-controller;
116 ti,sci = <&dmsc>;118 ti,sci = <&dmsc>;
117 ti,sci-dev-id = <209>;119 ti,sci-dev-id = <209>;
118 ti,sci-rm-range-vint = <0xa>;120 ti,interrupt-ranges = <0 0 256>;
119 ti,sci-rm-range-global-event = <0xd>;
120 };121 };
121 122
122 secure_proxy_main: mailbox@32c00000 {123 secure_proxy_main: mailbox@32c00000 {
@@ -296,7 +297,7 @@ · 173 unmodified lines
296 reg-names = "cpts";297 reg-names = "cpts";
297 clocks = <&k3_clks 201 1>;298 clocks = <&k3_clks 201 1>;
298 clock-names = "cpts";299 clock-names = "cpts";
299 interrupts-extended = <&main_navss_intr 201 0>;300 interrupts-extended = <&main_navss_intr 391>;
300 interrupt-names = "cpts";301 interrupt-names = "cpts";
301 ti,cpts-periodic-outputs = <6>;302 ti,cpts-periodic-outputs = <6>;
302 ti,cpts-ext-ts-inputs = <8>;303 ti,cpts-ext-ts-inputs = <8>;
@@ -688,8 +689,8 @@ · 385 unmodified lines
688 gpio-controller;689 gpio-controller;
689 #gpio-cells = <2>;690 #gpio-cells = <2>;
690 interrupt-parent = <&main_gpio_intr>;691 interrupt-parent = <&main_gpio_intr>;
691 interrupts = <105 0>, <105 1>, <105 2>, <105 3>,692 interrupts = <256>, <257>, <258>, <259>,
692 <105 4>, <105 5>, <105 6>, <105 7>;693 <260>, <261>, <262>, <263>;
693 interrupt-controller;694 interrupt-controller;
694 #interrupt-cells = <2>;695 #interrupt-cells = <2>;
695 ti,ngpio = <128>;696 ti,ngpio = <128>;
@@ -705,7 +706,7 @@ · 9 unmodified lines
705 gpio-controller;706 gpio-controller;
706 #gpio-cells = <2>;707 #gpio-cells = <2>;
707 interrupt-parent = <&main_gpio_intr>;708 interrupt-parent = <&main_gpio_intr>;
708 interrupts = <106 0>, <106 1>, <106 2>;709 interrupts = <288>, <289>, <290>;
709 interrupt-controller;710 interrupt-controller;
710 #interrupt-cells = <2>;711 #interrupt-cells = <2>;
711 ti,ngpio = <36>;712 ti,ngpio = <36>;
@@ -721,8 +722,8 @@ · 9 unmodified lines
721 gpio-controller;722 gpio-controller;
722 #gpio-cells = <2>;723 #gpio-cells = <2>;
723 interrupt-parent = <&main_gpio_intr>;724 interrupt-parent = <&main_gpio_intr>;
724 interrupts = <107 0>, <107 1>, <107 2>, <107 3>,725 interrupts = <264>, <265>, <266>, <267>,
725 <107 4>, <107 5>, <107 6>, <107 7>;726 <268>, <269>, <270>, <271>;
726 interrupt-controller;727 interrupt-controller;
727 #interrupt-cells = <2>;728 #interrupt-cells = <2>;
728 ti,ngpio = <128>;729 ti,ngpio = <128>;
@@ -738,7 +739,7 @@ · 9 unmodified lines
738 gpio-controller;739 gpio-controller;
739 #gpio-cells = <2>;740 #gpio-cells = <2>;
740 interrupt-parent = <&main_gpio_intr>;741 interrupt-parent = <&main_gpio_intr>;
741 interrupts = <108 0>, <108 1>, <108 2>;742 interrupts = <292>, <293>, <294>;
742 interrupt-controller;743 interrupt-controller;
743 #interrupt-cells = <2>;744 #interrupt-cells = <2>;
744 ti,ngpio = <36>;745 ti,ngpio = <36>;
@@ -754,8 +755,8 @@ · 9 unmodified lines
754 gpio-controller;755 gpio-controller;
755 #gpio-cells = <2>;756 #gpio-cells = <2>;
756 interrupt-parent = <&main_gpio_intr>;757 interrupt-parent = <&main_gpio_intr>;
757 interrupts = <109 0>, <109 1>, <109 2>, <109 3>,758 interrupts = <272>, <273>, <274>, <275>,
758 <109 4>, <109 5>, <109 6>, <109 7>;759 <276>, <277>, <278>, <279>;
759 interrupt-controller;760 interrupt-controller;
760 #interrupt-cells = <2>;761 #interrupt-cells = <2>;
761 ti,ngpio = <128>;762 ti,ngpio = <128>;
@@ -771,7 +772,7 @@ · 9 unmodified lines
771 gpio-controller;772 gpio-controller;
772 #gpio-cells = <2>;773 #gpio-cells = <2>;
773 interrupt-parent = <&main_gpio_intr>;774 interrupt-parent = <&main_gpio_intr>;
774 interrupts = <110 0>, <110 1>, <110 2>;775 interrupts = <296>, <297>, <298>;
775 interrupt-controller;776 interrupt-controller;
776 #interrupt-cells = <2>;777 #interrupt-cells = <2>;
777 ti,ngpio = <36>;778 ti,ngpio = <36>;
@@ -787,8 +788,8 @@ · 9 unmodified lines
787 gpio-controller;788 gpio-controller;
788 #gpio-cells = <2>;789 #gpio-cells = <2>;
789 interrupt-parent = <&main_gpio_intr>;790 interrupt-parent = <&main_gpio_intr>;
790 interrupts = <111 0>, <111 1>, <111 2>, <111 3>,791 interrupts = <280>, <281>, <282>, <283>,
791 <111 4>, <111 5>, <111 6>, <111 7>;792 <284>, <285>, <286>, <287>;
792 interrupt-controller;793 interrupt-controller;
793 #interrupt-cells = <2>;794 #interrupt-cells = <2>;
794 ti,ngpio = <128>;795 ti,ngpio = <128>;
@@ -804,7 +805,7 @@ · 9 unmodified lines
804 gpio-controller;805 gpio-controller;
805 #gpio-cells = <2>;806 #gpio-cells = <2>;
806 interrupt-parent = <&main_gpio_intr>;807 interrupt-parent = <&main_gpio_intr>;
807 interrupts = <112 0>, <112 1>, <112 2>;808 interrupts = <300>, <301>, <302>;
808 interrupt-controller;809 interrupt-controller;
809 #interrupt-cells = <2>;810 #interrupt-cells = <2>;
810 ti,ngpio = <36>;811 ti,ngpio = <36>;
arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi+5−7
@@ -101,10 +101,10 @@ · 100 unmodified lines
101 ti,intr-trigger-type = <1>;101 ti,intr-trigger-type = <1>;
102 interrupt-controller;102 interrupt-controller;
103 interrupt-parent = <&gic500>;103 interrupt-parent = <&gic500>;
104 #interrupt-cells = <2>;104 #interrupt-cells = <1>;
105 ti,sci = <&dmsc>;105 ti,sci = <&dmsc>;
106 ti,sci-dst-id = <14>;106 ti,sci-dev-id = <137>;
107 ti,sci-rm-range-girq = <0x5>;107 ti,interrupt-ranges = <16 960 16>;
108 };108 };
109 109
110 wkup_gpio0: gpio@42110000 {110 wkup_gpio0: gpio@42110000 {
@@ -113,8 +113,7 @@ · 2 unmodified lines
113 gpio-controller;113 gpio-controller;
114 #gpio-cells = <2>;114 #gpio-cells = <2>;
115 interrupt-parent = <&wkup_gpio_intr>;115 interrupt-parent = <&wkup_gpio_intr>;
116 interrupts = <113 0>, <113 1>, <113 2>,116 interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
117 <113 3>, <113 4>, <113 5>;
118 interrupt-controller;117 interrupt-controller;
119 #interrupt-cells = <2>;118 #interrupt-cells = <2>;
120 ti,ngpio = <84>;119 ti,ngpio = <84>;
@@ -130,8 +129,7 @@ · 9 unmodified lines
130 gpio-controller;129 gpio-controller;
131 #gpio-cells = <2>;130 #gpio-cells = <2>;
132 interrupt-parent = <&wkup_gpio_intr>;131 interrupt-parent = <&wkup_gpio_intr>;
133 interrupts = <114 0>, <114 1>, <114 2>,132 interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
134 <114 3>, <114 4>, <114 5>;
135 interrupt-controller;133 interrupt-controller;
136 #interrupt-cells = <2>;134 #interrupt-cells = <2>;
137 ti,ngpio = <84>;135 ti,ngpio = <84>;
arch/arm64/include/asm/compiler.h+6−0
@@ -2,6 +2,12 @@ · 1 unmodified line
2#ifndef __ASM_COMPILER_H2#ifndef __ASM_COMPILER_H
3#define __ASM_COMPILER_H3#define __ASM_COMPILER_H
4 4
5#ifdef ARM64_ASM_ARCH
6#define ARM64_ASM_PREAMBLE ".arch " ARM64_ASM_ARCH "\n"
7#else
8#define ARM64_ASM_PREAMBLE
9#endif
10
5/*11/*
6 * The EL0/EL1 pointer bits used by a pointer authentication code.12 * The EL0/EL1 pointer bits used by a pointer authentication code.
7 * This is dependent on TBI0/TBI1 being enabled, or bits 63:56 would also apply.13 * This is dependent on TBI0/TBI1 being enabled, or bits 63:56 would also apply.
arch/arm64/include/asm/irqflags.h+5−0
@@ -95,6 +95,11 @@ static inline int arch_irqs_disabled_flags(unsigned long flags) · 94 unmodified lines
95 return res;95 return res;
96}96}
97 97
98static inline int arch_irqs_disabled(void)
99{
100 return arch_irqs_disabled_flags(arch_local_save_flags());
101}
102
98static inline unsigned long arch_local_irq_save(void)103static inline unsigned long arch_local_irq_save(void)
99{104{
100 unsigned long flags;105 unsigned long flags;
arch/arm64/include/asm/kvm_arm.h+2−1
@@ -71,11 +71,12 @@ · 70 unmodified lines
71 * IMO: Override CPSR.I and enable signaling with VI71 * IMO: Override CPSR.I and enable signaling with VI
72 * FMO: Override CPSR.F and enable signaling with VF72 * FMO: Override CPSR.F and enable signaling with VF
73 * SWIO: Turn set/way invalidates into set/way clean+invalidate73 * SWIO: Turn set/way invalidates into set/way clean+invalidate
74 * PTW: Take a stage2 fault if a stage1 walk steps in device memory
74 */75 */
75#define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \76#define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \
76 HCR_BSU_IS | HCR_FB | HCR_TAC | \77 HCR_BSU_IS | HCR_FB | HCR_TAC | \
77 HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW | HCR_TLOR | \78 HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW | HCR_TLOR | \
78 HCR_FMO | HCR_IMO)79 HCR_FMO | HCR_IMO | HCR_PTW )
79#define HCR_VIRT_EXCP_MASK (HCR_VSE | HCR_VI | HCR_VF)80#define HCR_VIRT_EXCP_MASK (HCR_VSE | HCR_VI | HCR_VF)
80#define HCR_HOST_NVHE_FLAGS (HCR_RW | HCR_API | HCR_APK)81#define HCR_HOST_NVHE_FLAGS (HCR_RW | HCR_API | HCR_APK)
81#define HCR_HOST_VHE_FLAGS (HCR_RW | HCR_TGE | HCR_E2H)82#define HCR_HOST_VHE_FLAGS (HCR_RW | HCR_TGE | HCR_E2H)
arch/arm64/include/asm/kvm_asm.h+43−0
@@ -169,6 +169,34 @@ extern char __smccc_workaround_1_smc[__SMCCC_WORKAROUND_1_SMC_SZ]; · 168 unmodified lines
169 *__hyp_this_cpu_ptr(sym); \169 *__hyp_this_cpu_ptr(sym); \
170 })170 })
171 171
172#define __KVM_EXTABLE(from, to) \
173 " .pushsection __kvm_ex_table, \"a\"\n" \
174 " .align 3\n" \
175 " .long (" #from " - .), (" #to " - .)\n" \
176 " .popsection\n"
177
178
179#define __kvm_at(at_op, addr) \
180( { \
181 int __kvm_at_err = 0; \
182 u64 spsr, elr; \
183 asm volatile( \
184 " mrs %1, spsr_el2\n" \
185 " mrs %2, elr_el2\n" \
186 "1: at "at_op", %3\n" \
187 " isb\n" \
188 " b 9f\n" \
189 "2: msr spsr_el2, %1\n" \
190 " msr elr_el2, %2\n" \
191 " mov %w0, %4\n" \
192 "9:\n" \
193 __KVM_EXTABLE(1b, 2b) \
194 : "+r" (__kvm_at_err), "=&r" (spsr), "=&r" (elr) \
195 : "r" (addr), "i" (-EFAULT)); \
196 __kvm_at_err; \
197} )
198
199
172#else /* __ASSEMBLY__ */200#else /* __ASSEMBLY__ */
173 201
174.macro hyp_adr_this_cpu reg, sym, tmp202.macro hyp_adr_this_cpu reg, sym, tmp
@@ -193,6 +221,21 @@ extern char __smccc_workaround_1_smc[__SMCCC_WORKAROUND_1_SMC_SZ]; · 18 unmodified lines
193 ldr \vcpu, [\ctxt, #HOST_CONTEXT_VCPU]221 ldr \vcpu, [\ctxt, #HOST_CONTEXT_VCPU]
194.endm222.endm
195 223
224/*
225 * KVM extable for unexpected exceptions.
226 * In the same format _asm_extable, but output to a different section so that
227 * it can be mapped to EL2. The KVM version is not sorted. The caller must
228 * ensure:
229 * x18 has the hypervisor value to allow any Shadow-Call-Stack instrumented
230 * code to write to it, and that SPSR_EL2 and ELR_EL2 are restored by the fixup.
231 */
232.macro _kvm_extable, from, to
233 .pushsection __kvm_ex_table, "a"
234 .align 3
235 .long (\from - .), (\to - .)
236 .popsection
237.endm
238
196#endif239#endif
197 240
198#endif /* __ARM_KVM_ASM_H__ */241#endif /* __ARM_KVM_ASM_H__ */
arch/arm64/include/asm/kvm_host.h+1−1
@@ -473,7 +473,7 @@ int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu, · 472 unmodified lines
473 473
474#define KVM_ARCH_WANT_MMU_NOTIFIER474#define KVM_ARCH_WANT_MMU_NOTIFIER
475int kvm_unmap_hva_range(struct kvm *kvm,475int kvm_unmap_hva_range(struct kvm *kvm,
476 unsigned long start, unsigned long end);476 unsigned long start, unsigned long end, unsigned flags);
477int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);477int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
478int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end);478int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end);
479int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);479int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);
arch/arm64/include/asm/tlbflush.h+4−2
@@ -28,14 +28,16 @@ · 27 unmodified lines
28 * not. The macros handles invoking the asm with or without the28 * not. The macros handles invoking the asm with or without the
29 * register argument as appropriate.29 * register argument as appropriate.
30 */30 */
31#define __TLBI_0(op, arg) asm ("tlbi " #op "\n" \31#define __TLBI_0(op, arg) asm (ARM64_ASM_PREAMBLE \
32 "tlbi " #op "\n" \
32 ALTERNATIVE("nop\n nop", \33 ALTERNATIVE("nop\n nop", \
33 "dsb ish\n tlbi " #op, \34 "dsb ish\n tlbi " #op, \
34 ARM64_WORKAROUND_REPEAT_TLBI, \35 ARM64_WORKAROUND_REPEAT_TLBI, \
35 CONFIG_ARM64_WORKAROUND_REPEAT_TLBI) \36 CONFIG_ARM64_WORKAROUND_REPEAT_TLBI) \
36 : : )37 : : )
37 38
38#define __TLBI_1(op, arg) asm ("tlbi " #op ", %0\n" \39#define __TLBI_1(op, arg) asm (ARM64_ASM_PREAMBLE \
40 "tlbi " #op ", %0\n" \
39 ALTERNATIVE("nop\n nop", \41 ALTERNATIVE("nop\n nop", \
40 "dsb ish\n tlbi " #op ", %0", \42 "dsb ish\n tlbi " #op ", %0", \
41 ARM64_WORKAROUND_REPEAT_TLBI, \43 ARM64_WORKAROUND_REPEAT_TLBI, \
arch/arm64/kernel/acpi.c+1−1
@@ -322,7 +322,7 @@ void __iomem *acpi_os_ioremap(acpi_physical_address phys, acpi_size size) · 321 unmodified lines
322 */322 */
323 if (memblock_is_map_memory(phys))323 if (memblock_is_map_memory(phys))
324 return (void __iomem *)__phys_to_virt(phys);324 return (void __iomem *)__phys_to_virt(phys);
325 /* fall through */325 fallthrough;
326 326
327 default:327 default:
328 if (region->attribute & EFI_MEMORY_WB)328 if (region->attribute & EFI_MEMORY_WB)
arch/arm64/kernel/cpu_errata.c+2−0
@@ -910,6 +910,8 @@ const struct arm64_cpu_capabilities arm64_errata[] = { · 909 unmodified lines
910 .desc = "ARM erratum 1418040",910 .desc = "ARM erratum 1418040",
911 .capability = ARM64_WORKAROUND_1418040,911 .capability = ARM64_WORKAROUND_1418040,
912 ERRATA_MIDR_RANGE_LIST(erratum_1418040_list),912 ERRATA_MIDR_RANGE_LIST(erratum_1418040_list),
913 .type = (ARM64_CPUCAP_SCOPE_LOCAL_CPU |
914 ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU),
913 },915 },
914#endif916#endif
915#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT917#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT
arch/arm64/kernel/cpufeature.c+1−1
@@ -686,7 +686,7 @@ static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, · 685 unmodified lines
686 case FTR_HIGHER_OR_ZERO_SAFE:686 case FTR_HIGHER_OR_ZERO_SAFE:
687 if (!cur || !new)687 if (!cur || !new)
688 break;688 break;
689 /* Fallthrough */689 fallthrough;
690 case FTR_HIGHER_SAFE:690 case FTR_HIGHER_SAFE:
691 ret = new > cur ? new : cur;691 ret = new > cur ? new : cur;
692 break;692 break;
arch/arm64/kernel/cpuinfo.c+0−1
@@ -327,7 +327,6 @@ static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info) · 326 unmodified lines
327 set_bit(ICACHEF_VPIPT, &__icache_flags);327 set_bit(ICACHEF_VPIPT, &__icache_flags);
328 break;328 break;
329 default:329 default:
330 /* Fallthrough */
331 case ICACHE_POLICY_VIPT:330 case ICACHE_POLICY_VIPT:
332 /* Assume aliasing */331 /* Assume aliasing */
333 set_bit(ICACHEF_ALIASING, &__icache_flags);332 set_bit(ICACHEF_ALIASING, &__icache_flags);
arch/arm64/kernel/entry.S+0−21
@@ -170,19 +170,6 @@ alternative_cb_end · 169 unmodified lines
170 stp x28, x29, [sp, #16 * 14]170 stp x28, x29, [sp, #16 * 14]
171 171
172 .if \el == 0172 .if \el == 0
173 .if \regsize == 32
174 /*
175 * If we're returning from a 32-bit task on a system affected by
176 * 1418040 then re-enable userspace access to the virtual counter.
177 */
178#ifdef CONFIG_ARM64_ERRATUM_1418040
179alternative_if ARM64_WORKAROUND_1418040
180 mrs x0, cntkctl_el1
181 orr x0, x0, #2 // ARCH_TIMER_USR_VCT_ACCESS_EN
182 msr cntkctl_el1, x0
183alternative_else_nop_endif
184#endif
185 .endif
186 clear_gp_regs173 clear_gp_regs
187 mrs x21, sp_el0174 mrs x21, sp_el0
188 ldr_this_cpu tsk, __entry_task, x20175 ldr_this_cpu tsk, __entry_task, x20
@@ -294,14 +281,6 @@ alternative_else_nop_endif · 105 unmodified lines
294 tst x22, #PSR_MODE32_BIT // native task?281 tst x22, #PSR_MODE32_BIT // native task?
295 b.eq 3f282 b.eq 3f
296 283
297#ifdef CONFIG_ARM64_ERRATUM_1418040
298alternative_if ARM64_WORKAROUND_1418040
299 mrs x0, cntkctl_el1
300 bic x0, x0, #2 // ARCH_TIMER_USR_VCT_ACCESS_EN
301 msr cntkctl_el1, x0
302alternative_else_nop_endif
303#endif
304
305#ifdef CONFIG_ARM64_ERRATUM_845719284#ifdef CONFIG_ARM64_ERRATUM_845719
306alternative_if ARM64_WORKAROUND_845719285alternative_if ARM64_WORKAROUND_845719
307#ifdef CONFIG_PID_IN_CONTEXTIDR286#ifdef CONFIG_PID_IN_CONTEXTIDR
arch/arm64/kernel/hw_breakpoint.c+3−3
@@ -257,7 +257,7 @@ static int hw_breakpoint_control(struct perf_event *bp, · 256 unmodified lines
257 * level.257 * level.
258 */258 */
259 enable_debug_monitors(dbg_el);259 enable_debug_monitors(dbg_el);
260 /* Fall through */260 fallthrough;
261 case HW_BREAKPOINT_RESTORE:261 case HW_BREAKPOINT_RESTORE:
262 /* Setup the address register. */262 /* Setup the address register. */
263 write_wb_reg(val_reg, i, info->address);263 write_wb_reg(val_reg, i, info->address);
@@ -541,13 +541,13 @@ int hw_breakpoint_arch_parse(struct perf_event *bp, · 277 unmodified lines
541 if (hw->ctrl.len == ARM_BREAKPOINT_LEN_2)541 if (hw->ctrl.len == ARM_BREAKPOINT_LEN_2)
542 break;542 break;
543 543
544 /* Fallthrough */544 fallthrough;
545 case 3:545 case 3:
546 /* Allow single byte watchpoint. */546 /* Allow single byte watchpoint. */
547 if (hw->ctrl.len == ARM_BREAKPOINT_LEN_1)547 if (hw->ctrl.len == ARM_BREAKPOINT_LEN_1)
548 break;548 break;
549 549
550 /* Fallthrough */550 fallthrough;
551 default:551 default:
552 return -EINVAL;552 return -EINVAL;
553 }553 }
arch/arm64/kernel/image-vars.h+4−0
@@ -103,6 +103,10 @@ KVM_NVHE_ALIAS(vgic_v3_cpuif_trap); · 102 unmodified lines
103KVM_NVHE_ALIAS(gic_pmr_sync);103KVM_NVHE_ALIAS(gic_pmr_sync);
104#endif104#endif
105 105
106/* EL2 exception handling */
107KVM_NVHE_ALIAS(__start___kvm_ex_table);
108KVM_NVHE_ALIAS(__stop___kvm_ex_table);
109
106#endif /* CONFIG_KVM */110#endif /* CONFIG_KVM */
107 111
108#endif /* __ARM64_KERNEL_IMAGE_VARS_H */112#endif /* __ARM64_KERNEL_IMAGE_VARS_H */
arch/arm64/kernel/module-plts.c+1−2
@@ -305,8 +305,7 @@ int module_frob_arch_sections(Elf_Ehdr *ehdr, Elf_Shdr *sechdrs, · 304 unmodified lines
305 mod->arch.core.plt_shndx = i;305 mod->arch.core.plt_shndx = i;
306 else if (!strcmp(secstrings + sechdrs[i].sh_name, ".init.plt"))306 else if (!strcmp(secstrings + sechdrs[i].sh_name, ".init.plt"))
307 mod->arch.init.plt_shndx = i;307 mod->arch.init.plt_shndx = i;
308 else if (IS_ENABLED(CONFIG_DYNAMIC_FTRACE) &&308 else if (!strcmp(secstrings + sechdrs[i].sh_name,
309 !strcmp(secstrings + sechdrs[i].sh_name,
310 ".text.ftrace_trampoline"))309 ".text.ftrace_trampoline"))
311 tramp = sechdrs + i;310 tramp = sechdrs + i;
312 else if (sechdrs[i].sh_type == SHT_SYMTAB)311 else if (sechdrs[i].sh_type == SHT_SYMTAB)
arch/arm64/kernel/module.c+4−4
@@ -315,21 +315,21 @@ int apply_relocate_add(Elf64_Shdr *sechdrs, · 314 unmodified lines
315 /* MOVW instruction relocations. */315 /* MOVW instruction relocations. */
316 case R_AARCH64_MOVW_UABS_G0_NC:316 case R_AARCH64_MOVW_UABS_G0_NC:
317 overflow_check = false;317 overflow_check = false;
318 /* Fall through */318 fallthrough;
319 case R_AARCH64_MOVW_UABS_G0:319 case R_AARCH64_MOVW_UABS_G0:
320 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0,320 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0,
321 AARCH64_INSN_IMM_MOVKZ);321 AARCH64_INSN_IMM_MOVKZ);
322 break;322 break;
323 case R_AARCH64_MOVW_UABS_G1_NC:323 case R_AARCH64_MOVW_UABS_G1_NC:
324 overflow_check = false;324 overflow_check = false;
325 /* Fall through */325 fallthrough;
326 case R_AARCH64_MOVW_UABS_G1:326 case R_AARCH64_MOVW_UABS_G1:
327 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16,327 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16,
328 AARCH64_INSN_IMM_MOVKZ);328 AARCH64_INSN_IMM_MOVKZ);
329 break;329 break;
330 case R_AARCH64_MOVW_UABS_G2_NC:330 case R_AARCH64_MOVW_UABS_G2_NC:
331 overflow_check = false;331 overflow_check = false;
332 /* Fall through */332 fallthrough;
333 case R_AARCH64_MOVW_UABS_G2:333 case R_AARCH64_MOVW_UABS_G2:
334 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32,334 ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32,
335 AARCH64_INSN_IMM_MOVKZ);335 AARCH64_INSN_IMM_MOVKZ);
@@ -397,7 +397,7 @@ int apply_relocate_add(Elf64_Shdr *sechdrs, · 61 unmodified lines
397 break;397 break;
398 case R_AARCH64_ADR_PREL_PG_HI21_NC:398 case R_AARCH64_ADR_PREL_PG_HI21_NC:
399 overflow_check = false;399 overflow_check = false;
400 /* Fall through */400 fallthrough;
401 case R_AARCH64_ADR_PREL_PG_HI21:401 case R_AARCH64_ADR_PREL_PG_HI21:
402 ovf = reloc_insn_adrp(me, sechdrs, loc, val);402 ovf = reloc_insn_adrp(me, sechdrs, loc, val);
403 if (ovf && ovf != -ERANGE)403 if (ovf && ovf != -ERANGE)
arch/arm64/kernel/process.c+34−2
@@ -123,10 +123,8 @@ void arch_cpu_idle(void) · 122 unmodified lines
123 * This should do all the clock switching and wait for interrupt123 * This should do all the clock switching and wait for interrupt
124 * tricks124 * tricks
125 */125 */
126 trace_cpu_idle_rcuidle(1, smp_processor_id());
127 cpu_do_idle();126 cpu_do_idle();
128 local_irq_enable();127 local_irq_enable();
129 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
130}128}
131 129
132#ifdef CONFIG_HOTPLUG_CPU130#ifdef CONFIG_HOTPLUG_CPU
@@ -515,6 +513,39 @@ static void entry_task_switch(struct task_struct *next) · 382 unmodified lines
515 __this_cpu_write(__entry_task, next);513 __this_cpu_write(__entry_task, next);
516}514}
517 515
516/*
517 * ARM erratum 1418040 handling, affecting the 32bit view of CNTVCT.
518 * Assuming the virtual counter is enabled at the beginning of times:
519 *
520 * - disable access when switching from a 64bit task to a 32bit task
521 * - enable access when switching from a 32bit task to a 64bit task
522 */
523static void erratum_1418040_thread_switch(struct task_struct *prev,
524 struct task_struct *next)
525{
526 bool prev32, next32;
527 u64 val;
528
529 if (!(IS_ENABLED(CONFIG_ARM64_ERRATUM_1418040) &&
530 cpus_have_const_cap(ARM64_WORKAROUND_1418040)))
531 return;
532
533 prev32 = is_compat_thread(task_thread_info(prev));
534 next32 = is_compat_thread(task_thread_info(next));
535
536 if (prev32 == next32)
537 return;
538
539 val = read_sysreg(cntkctl_el1);
540
541 if (!next32)
542 val |= ARCH_TIMER_USR_VCT_ACCESS_EN;
543 else
544 val &= ~ARCH_TIMER_USR_VCT_ACCESS_EN;
545
546 write_sysreg(val, cntkctl_el1);
547}
548
518/*549/*
519 * Thread switching.550 * Thread switching.
520 */551 */
@@ -530,6 +561,7 @@ __notrace_funcgraph struct task_struct *__switch_to(struct task_struct *prev, · 9 unmodified lines
530 entry_task_switch(next);561 entry_task_switch(next);
531 uao_thread_switch(next);562 uao_thread_switch(next);
532 ssbs_thread_switch(next);563 ssbs_thread_switch(next);
564 erratum_1418040_thread_switch(prev, next);
533 565
534 /*566 /*
535 * Complete any pending TLB or cache maintenance on this CPU in case567 * Complete any pending TLB or cache maintenance on this CPU in case
arch/arm64/kernel/setup.c+0−1
@@ -280,7 +280,6 @@ u64 cpu_logical_map(int cpu) · 279 unmodified lines
280{280{
281 return __cpu_logical_map[cpu];281 return __cpu_logical_map[cpu];
282}282}
283EXPORT_SYMBOL_GPL(cpu_logical_map);
284 283
285void __init __no_sanitize_address setup_arch(char **cmdline_p)284void __init __no_sanitize_address setup_arch(char **cmdline_p)
286{285{
arch/arm64/kernel/smp.c+1−1
@@ -151,7 +151,7 @@ int __cpu_up(unsigned int cpu, struct task_struct *idle) · 150 unmodified lines
151 break;151 break;
152 }152 }
153 pr_crit("CPU%u: may not have shut down cleanly\n", cpu);153 pr_crit("CPU%u: may not have shut down cleanly\n", cpu);
154 /* Fall through */154 fallthrough;
155 case CPU_STUCK_IN_KERNEL:155 case CPU_STUCK_IN_KERNEL:
156 pr_crit("CPU%u: is stuck in kernel\n", cpu);156 pr_crit("CPU%u: is stuck in kernel\n", cpu);
157 if (status & CPU_STUCK_REASON_52_BIT_VA)157 if (status & CPU_STUCK_REASON_52_BIT_VA)
arch/arm64/kernel/vdso32/Makefile+1−1
@@ -208,7 +208,7 @@ quiet_cmd_vdsosym = VDSOSYM $@ · 207 unmodified lines
208 cmd_vdsosym = $(NM) $< | $(gen-vdsosym) | LC_ALL=C sort > $@208 cmd_vdsosym = $(NM) $< | $(gen-vdsosym) | LC_ALL=C sort > $@
209 209
210# Install commands for the unstripped file210# Install commands for the unstripped file
211quiet_cmd_vdso_install = INSTALL $@211quiet_cmd_vdso_install = INSTALL32 $@
212 cmd_vdso_install = cp $(obj)/$@.dbg $(MODLIB)/vdso/vdso32.so212 cmd_vdso_install = cp $(obj)/$@.dbg $(MODLIB)/vdso/vdso32.so
213 213
214vdso.so: $(obj)/vdso.so.dbg214vdso.so: $(obj)/vdso.so.dbg
arch/arm64/kernel/vmlinux.lds.S+8−0
@@ -20,6 +20,13 @@ ENTRY(_text) · 19 unmodified lines
20 20
21jiffies = jiffies_64;21jiffies = jiffies_64;
22 22
23
24#define HYPERVISOR_EXTABLE \
25 . = ALIGN(SZ_8); \
26 __start___kvm_ex_table = .; \
27 *(__kvm_ex_table) \
28 __stop___kvm_ex_table = .;
29
23#define HYPERVISOR_TEXT \30#define HYPERVISOR_TEXT \
24 /* \31 /* \
25 * Align to 4 KB so that \32 * Align to 4 KB so that \
@@ -35,6 +42,7 @@ jiffies = jiffies_64; · 9 unmodified lines
35 __hyp_idmap_text_end = .; \42 __hyp_idmap_text_end = .; \
36 __hyp_text_start = .; \43 __hyp_text_start = .; \
37 *(.hyp.text) \44 *(.hyp.text) \
45 HYPERVISOR_EXTABLE \
38 __hyp_text_end = .;46 __hyp_text_end = .;
39 47
40#define IDMAP_TEXT \48#define IDMAP_TEXT \
arch/arm64/kvm/arm.c+4−0
@@ -1640,6 +1640,10 @@ int kvm_arch_init(void *opaque) · 1639 unmodified lines
1640 return -ENODEV;1640 return -ENODEV;
1641 }1641 }
1642 1642
1643 if (cpus_have_final_cap(ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE))
1644 kvm_info("Guests without required CPU erratum workarounds can deadlock system!\n" \
1645 "Only trusted guests should be used on this system.\n");
1646
1643 for_each_online_cpu(cpu) {1647 for_each_online_cpu(cpu) {
1644 smp_call_function_single(cpu, check_kvm_target_cpu, &ret, 1);1648 smp_call_function_single(cpu, check_kvm_target_cpu, &ret, 1);
1645 if (ret < 0) {1649 if (ret < 0) {
arch/arm64/kvm/handle_exit.c+1−1
@@ -128,7 +128,7 @@ static int kvm_handle_guest_debug(struct kvm_vcpu *vcpu) · 127 unmodified lines
128 switch (ESR_ELx_EC(esr)) {128 switch (ESR_ELx_EC(esr)) {
129 case ESR_ELx_EC_WATCHPT_LOW:129 case ESR_ELx_EC_WATCHPT_LOW:
130 run->debug.arch.far = vcpu->arch.fault.far_el2;130 run->debug.arch.far = vcpu->arch.fault.far_el2;
131 /* fall through */131 fallthrough;
132 case ESR_ELx_EC_SOFTSTP_LOW:132 case ESR_ELx_EC_SOFTSTP_LOW:
133 case ESR_ELx_EC_BREAKPT_LOW:133 case ESR_ELx_EC_BREAKPT_LOW:
134 case ESR_ELx_EC_BKPT32:134 case ESR_ELx_EC_BKPT32:
arch/arm64/kvm/hyp/entry.S+9−6
@@ -196,20 +196,23 @@ alternative_endif · 195 unmodified lines
196 // This is our single instruction exception window. A pending196 // This is our single instruction exception window. A pending
197 // SError is guaranteed to occur at the earliest when we unmask197 // SError is guaranteed to occur at the earliest when we unmask
198 // it, and at the latest just after the ISB.198 // it, and at the latest just after the ISB.
199 .global abort_guest_exit_start
200abort_guest_exit_start:199abort_guest_exit_start:
201 200
202 isb201 isb
203 202
204 .global abort_guest_exit_end
205abort_guest_exit_end:203abort_guest_exit_end:
206 204
207 msr daifset, #4 // Mask aborts205 msr daifset, #4 // Mask aborts
206 ret
207
208 _kvm_extable abort_guest_exit_start, 9997f
209 _kvm_extable abort_guest_exit_end, 9997f
2109997:
211 msr daifset, #4 // Mask aborts
212 mov x0, #(1 << ARM_EXIT_WITH_SERROR_BIT)
208 213
209 // If the exception took place, restore the EL1 exception214 // restore the EL1 exception context so that we can report some
210 // context so that we can report some information.215 // information. Merge the exception code with the SError pending bit.
211 // Merge the exception code with the SError pending bit.
212 tbz x0, #ARM_EXIT_WITH_SERROR_BIT, 1f
213 msr elr_el2, x2216 msr elr_el2, x2
214 msr esr_el2, x3217 msr esr_el2, x3
215 msr spsr_el2, x4218 msr spsr_el2, x4
arch/arm64/kvm/hyp/hyp-entry.S+41−24
@@ -15,6 +15,30 @@ · 14 unmodified lines
15#include <asm/kvm_mmu.h>15#include <asm/kvm_mmu.h>
16#include <asm/mmu.h>16#include <asm/mmu.h>
17 17
18.macro save_caller_saved_regs_vect
19 /* x0 and x1 were saved in the vector entry */
20 stp x2, x3, [sp, #-16]!
21 stp x4, x5, [sp, #-16]!
22 stp x6, x7, [sp, #-16]!
23 stp x8, x9, [sp, #-16]!
24 stp x10, x11, [sp, #-16]!
25 stp x12, x13, [sp, #-16]!
26 stp x14, x15, [sp, #-16]!
27 stp x16, x17, [sp, #-16]!
28.endm
29
30.macro restore_caller_saved_regs_vect
31 ldp x16, x17, [sp], #16
32 ldp x14, x15, [sp], #16
33 ldp x12, x13, [sp], #16
34 ldp x10, x11, [sp], #16
35 ldp x8, x9, [sp], #16
36 ldp x6, x7, [sp], #16
37 ldp x4, x5, [sp], #16
38 ldp x2, x3, [sp], #16
39 ldp x0, x1, [sp], #16
40.endm
41
18 .text42 .text
19 43
20.macro do_el2_call44.macro do_el2_call
@@ -143,13 +167,19 @@ el1_error: · 122 unmodified lines
143 b __guest_exit167 b __guest_exit
144 168
145el2_sync:169el2_sync:
146 /* Check for illegal exception return, otherwise panic */170 /* Check for illegal exception return */
147 mrs x0, spsr_el2171 mrs x0, spsr_el2
172 tbnz x0, #20, 1f
148 173
149 /* if this was something else, then panic! */174 save_caller_saved_regs_vect
150 tst x0, #PSR_IL_BIT175 stp x29, x30, [sp, #-16]!
151 b.eq __hyp_panic176 bl kvm_unexpected_el2_exception
177 ldp x29, x30, [sp], #16
178 restore_caller_saved_regs_vect
152 179
180 eret
181
1821:
153 /* Let's attempt a recovery from the illegal exception return */183 /* Let's attempt a recovery from the illegal exception return */
154 get_vcpu_ptr x1, x0184 get_vcpu_ptr x1, x0
155 mov x0, #ARM_EXCEPTION_IL185 mov x0, #ARM_EXCEPTION_IL
@@ -157,27 +187,14 @@ el2_sync: · 1 unmodified line
157 187
158 188
159el2_error:189el2_error:
160 ldp x0, x1, [sp], #16190 save_caller_saved_regs_vect
191 stp x29, x30, [sp, #-16]!
192
193 bl kvm_unexpected_el2_exception
194
195 ldp x29, x30, [sp], #16
196 restore_caller_saved_regs_vect
161 197
162 /*
163 * Only two possibilities:
164 * 1) Either we come from the exit path, having just unmasked
165 * PSTATE.A: change the return code to an EL2 fault, and
166 * carry on, as we're already in a sane state to handle it.
167 * 2) Or we come from anywhere else, and that's a bug: we panic.
168 *
169 * For (1), x0 contains the original return code and x1 doesn't
170 * contain anything meaningful at that stage. We can reuse them
171 * as temp registers.
172 * For (2), who cares?
173 */
174 mrs x0, elr_el2
175 adr x1, abort_guest_exit_start
176 cmp x0, x1
177 adr x1, abort_guest_exit_end
178 ccmp x0, x1, #4, ne
179 b.ne __hyp_panic
180 mov x0, #(1 << ARM_EXIT_WITH_SERROR_BIT)
181 eret198 eret
182 sb199 sb
183 200
arch/arm64/kvm/hyp/include/hyp/debug-sr.h+30−30
@@ -21,70 +21,70 @@ · 20 unmodified lines
21#define save_debug(ptr,reg,nr) \21#define save_debug(ptr,reg,nr) \
22 switch (nr) { \22 switch (nr) { \
23 case 15: ptr[15] = read_debug(reg, 15); \23 case 15: ptr[15] = read_debug(reg, 15); \
24 /* Fall through */ \24 fallthrough; \
25 case 14: ptr[14] = read_debug(reg, 14); \25 case 14: ptr[14] = read_debug(reg, 14); \
26 /* Fall through */ \26 fallthrough; \
27 case 13: ptr[13] = read_debug(reg, 13); \27 case 13: ptr[13] = read_debug(reg, 13); \
28 /* Fall through */ \28 fallthrough; \
29 case 12: ptr[12] = read_debug(reg, 12); \29 case 12: ptr[12] = read_debug(reg, 12); \
30 /* Fall through */ \30 fallthrough; \
31 case 11: ptr[11] = read_debug(reg, 11); \31 case 11: ptr[11] = read_debug(reg, 11); \
32 /* Fall through */ \32 fallthrough; \
33 case 10: ptr[10] = read_debug(reg, 10); \33 case 10: ptr[10] = read_debug(reg, 10); \
34 /* Fall through */ \34 fallthrough; \
35 case 9: ptr[9] = read_debug(reg, 9); \35 case 9: ptr[9] = read_debug(reg, 9); \
36 /* Fall through */ \36 fallthrough; \
37 case 8: ptr[8] = read_debug(reg, 8); \37 case 8: ptr[8] = read_debug(reg, 8); \
38 /* Fall through */ \38 fallthrough; \
39 case 7: ptr[7] = read_debug(reg, 7); \39 case 7: ptr[7] = read_debug(reg, 7); \
40 /* Fall through */ \40 fallthrough; \
41 case 6: ptr[6] = read_debug(reg, 6); \41 case 6: ptr[6] = read_debug(reg, 6); \
42 /* Fall through */ \42 fallthrough; \
43 case 5: ptr[5] = read_debug(reg, 5); \43 case 5: ptr[5] = read_debug(reg, 5); \
44 /* Fall through */ \44 fallthrough; \
45 case 4: ptr[4] = read_debug(reg, 4); \45 case 4: ptr[4] = read_debug(reg, 4); \
46 /* Fall through */ \46 fallthrough; \
47 case 3: ptr[3] = read_debug(reg, 3); \47 case 3: ptr[3] = read_debug(reg, 3); \
48 /* Fall through */ \48 fallthrough; \
49 case 2: ptr[2] = read_debug(reg, 2); \49 case 2: ptr[2] = read_debug(reg, 2); \
50 /* Fall through */ \50 fallthrough; \
51 case 1: ptr[1] = read_debug(reg, 1); \51 case 1: ptr[1] = read_debug(reg, 1); \
52 /* Fall through */ \52 fallthrough; \
53 default: ptr[0] = read_debug(reg, 0); \53 default: ptr[0] = read_debug(reg, 0); \
54 }54 }
55 55
56#define restore_debug(ptr,reg,nr) \56#define restore_debug(ptr,reg,nr) \
57 switch (nr) { \57 switch (nr) { \
58 case 15: write_debug(ptr[15], reg, 15); \58 case 15: write_debug(ptr[15], reg, 15); \
59 /* Fall through */ \59 fallthrough; \
60 case 14: write_debug(ptr[14], reg, 14); \60 case 14: write_debug(ptr[14], reg, 14); \
61 /* Fall through */ \61 fallthrough; \
62 case 13: write_debug(ptr[13], reg, 13); \62 case 13: write_debug(ptr[13], reg, 13); \
63 /* Fall through */ \63 fallthrough; \
64 case 12: write_debug(ptr[12], reg, 12); \64 case 12: write_debug(ptr[12], reg, 12); \
65 /* Fall through */ \65 fallthrough; \
66 case 11: write_debug(ptr[11], reg, 11); \66 case 11: write_debug(ptr[11], reg, 11); \
67 /* Fall through */ \67 fallthrough; \
68 case 10: write_debug(ptr[10], reg, 10); \68 case 10: write_debug(ptr[10], reg, 10); \
69 /* Fall through */ \69 fallthrough; \
70 case 9: write_debug(ptr[9], reg, 9); \70 case 9: write_debug(ptr[9], reg, 9); \
71 /* Fall through */ \71 fallthrough; \
72 case 8: write_debug(ptr[8], reg, 8); \72 case 8: write_debug(ptr[8], reg, 8); \
73 /* Fall through */ \73 fallthrough; \
74 case 7: write_debug(ptr[7], reg, 7); \74 case 7: write_debug(ptr[7], reg, 7); \
75 /* Fall through */ \75 fallthrough; \
76 case 6: write_debug(ptr[6], reg, 6); \76 case 6: write_debug(ptr[6], reg, 6); \
77 /* Fall through */ \77 fallthrough; \
78 case 5: write_debug(ptr[5], reg, 5); \78 case 5: write_debug(ptr[5], reg, 5); \
79 /* Fall through */ \79 fallthrough; \
80 case 4: write_debug(ptr[4], reg, 4); \80 case 4: write_debug(ptr[4], reg, 4); \
81 /* Fall through */ \81 fallthrough; \
82 case 3: write_debug(ptr[3], reg, 3); \82 case 3: write_debug(ptr[3], reg, 3); \
83 /* Fall through */ \83 fallthrough; \
84 case 2: write_debug(ptr[2], reg, 2); \84 case 2: write_debug(ptr[2], reg, 2); \
85 /* Fall through */ \85 fallthrough; \
86 case 1: write_debug(ptr[1], reg, 1); \86 case 1: write_debug(ptr[1], reg, 1); \
87 /* Fall through */ \87 fallthrough; \
88 default: write_debug(ptr[0], reg, 0); \88 default: write_debug(ptr[0], reg, 0); \
89 }89 }
90 90
arch/arm64/kvm/hyp/include/hyp/switch.h+35−4
@@ -17,6 +17,7 @@ · 16 unmodified lines
17 17
18#include <asm/barrier.h>18#include <asm/barrier.h>
19#include <asm/cpufeature.h>19#include <asm/cpufeature.h>
20#include <asm/extable.h>
20#include <asm/kprobes.h>21#include <asm/kprobes.h>
21#include <asm/kvm_asm.h>22#include <asm/kvm_asm.h>
22#include <asm/kvm_emulate.h>23#include <asm/kvm_emulate.h>
@@ -29,6 +30,9 @@ · 6 unmodified lines
29 30
30extern const char __hyp_panic_string[];31extern const char __hyp_panic_string[];
31 32
33extern struct exception_table_entry __start___kvm_ex_table;
34extern struct exception_table_entry __stop___kvm_ex_table;
35
32/* Check whether the FP regs were dirtied while in the host-side run loop: */36/* Check whether the FP regs were dirtied while in the host-side run loop: */
33static inline bool update_fp_enabled(struct kvm_vcpu *vcpu)37static inline bool update_fp_enabled(struct kvm_vcpu *vcpu)
34{38{
@@ -142,10 +146,10 @@ static inline bool __translate_far_to_hpfar(u64 far, u64 *hpfar) · 107 unmodified lines
142 * saved the guest context yet, and we may return early...146 * saved the guest context yet, and we may return early...
143 */147 */
144 par = read_sysreg(par_el1);148 par = read_sysreg(par_el1);
145 asm volatile("at s1e1r, %0" : : "r" (far));149 if (!__kvm_at("s1e1r", far))
146 isb();150 tmp = read_sysreg(par_el1);
147 151 else
148 tmp = read_sysreg(par_el1);152 tmp = SYS_PAR_EL1_F; /* back to the guest */
149 write_sysreg(par, par_el1);153 write_sysreg(par, par_el1);
150 154
151 if (unlikely(tmp & SYS_PAR_EL1_F))155 if (unlikely(tmp & SYS_PAR_EL1_F))
@@ -508,4 +512,31 @@ static inline void __set_host_arch_workaround_state(struct kvm_vcpu *vcpu) · 356 unmodified lines
508#endif512#endif
509}513}
510 514
515static inline void __kvm_unexpected_el2_exception(void)
516{
517 unsigned long addr, fixup;
518 struct kvm_cpu_context *host_ctxt;
519 struct exception_table_entry *entry, *end;
520 unsigned long elr_el2 = read_sysreg(elr_el2);
521
522 entry = hyp_symbol_addr(__start___kvm_ex_table);
523 end = hyp_symbol_addr(__stop___kvm_ex_table);
524 host_ctxt = &__hyp_this_cpu_ptr(kvm_host_data)->host_ctxt;
525
526 while (entry < end) {
527 addr = (unsigned long)&entry->insn + entry->insn;
528 fixup = (unsigned long)&entry->fixup + entry->fixup;
529
530 if (addr != elr_el2) {
531 entry++;
532 continue;
533 }
534
535 write_sysreg(fixup, elr_el2);
536 return;
537 }
538
539 hyp_panic(host_ctxt);
540}
541
511#endif /* __ARM64_KVM_HYP_SWITCH_H__ */542#endif /* __ARM64_KVM_HYP_SWITCH_H__ */
arch/arm64/kvm/hyp/nvhe/switch.c+5−0
@@ -270,3 +270,8 @@ void __noreturn hyp_panic(struct kvm_cpu_context *host_ctxt) · 269 unmodified lines
270 read_sysreg(hpfar_el2), par, vcpu);270 read_sysreg(hpfar_el2), par, vcpu);
271 unreachable();271 unreachable();
272}272}
273
274asmlinkage void kvm_unexpected_el2_exception(void)
275{
276 return __kvm_unexpected_el2_exception();
277}
arch/arm64/kvm/hyp/vgic-v3-sr.c+8−8
@@ -340,10 +340,10 @@ void __vgic_v3_save_aprs(struct vgic_v3_cpu_if *cpu_if) · 339 unmodified lines
340 case 7:340 case 7:
341 cpu_if->vgic_ap0r[3] = __vgic_v3_read_ap0rn(3);341 cpu_if->vgic_ap0r[3] = __vgic_v3_read_ap0rn(3);
342 cpu_if->vgic_ap0r[2] = __vgic_v3_read_ap0rn(2);342 cpu_if->vgic_ap0r[2] = __vgic_v3_read_ap0rn(2);
343 /* Fall through */343 fallthrough;
344 case 6:344 case 6:
345 cpu_if->vgic_ap0r[1] = __vgic_v3_read_ap0rn(1);345 cpu_if->vgic_ap0r[1] = __vgic_v3_read_ap0rn(1);
346 /* Fall through */346 fallthrough;
347 default:347 default:
348 cpu_if->vgic_ap0r[0] = __vgic_v3_read_ap0rn(0);348 cpu_if->vgic_ap0r[0] = __vgic_v3_read_ap0rn(0);
349 }349 }
@@ -352,10 +352,10 @@ void __vgic_v3_save_aprs(struct vgic_v3_cpu_if *cpu_if) · 2 unmodified lines
352 case 7:352 case 7:
353 cpu_if->vgic_ap1r[3] = __vgic_v3_read_ap1rn(3);353 cpu_if->vgic_ap1r[3] = __vgic_v3_read_ap1rn(3);
354 cpu_if->vgic_ap1r[2] = __vgic_v3_read_ap1rn(2);354 cpu_if->vgic_ap1r[2] = __vgic_v3_read_ap1rn(2);
355 /* Fall through */355 fallthrough;
356 case 6:356 case 6:
357 cpu_if->vgic_ap1r[1] = __vgic_v3_read_ap1rn(1);357 cpu_if->vgic_ap1r[1] = __vgic_v3_read_ap1rn(1);
358 /* Fall through */358 fallthrough;
359 default:359 default:
360 cpu_if->vgic_ap1r[0] = __vgic_v3_read_ap1rn(0);360 cpu_if->vgic_ap1r[0] = __vgic_v3_read_ap1rn(0);
361 }361 }
@@ -373,10 +373,10 @@ void __vgic_v3_restore_aprs(struct vgic_v3_cpu_if *cpu_if) · 11 unmodified lines
373 case 7:373 case 7:
374 __vgic_v3_write_ap0rn(cpu_if->vgic_ap0r[3], 3);374 __vgic_v3_write_ap0rn(cpu_if->vgic_ap0r[3], 3);
375 __vgic_v3_write_ap0rn(cpu_if->vgic_ap0r[2], 2);375 __vgic_v3_write_ap0rn(cpu_if->vgic_ap0r[2], 2);
376 /* Fall through */376 fallthrough;
377 case 6:377 case 6:
378 __vgic_v3_write_ap0rn(cpu_if->vgic_ap0r[1], 1);378 __vgic_v3_write_ap0rn(cpu_if->vgic_ap0r[1], 1);
379 /* Fall through */379 fallthrough;
380 default:380 default:
381 __vgic_v3_write_ap0rn(cpu_if->vgic_ap0r[0], 0);381 __vgic_v3_write_ap0rn(cpu_if->vgic_ap0r[0], 0);
382 }382 }
@@ -385,10 +385,10 @@ void __vgic_v3_restore_aprs(struct vgic_v3_cpu_if *cpu_if) · 2 unmodified lines
385 case 7:385 case 7:
386 __vgic_v3_write_ap1rn(cpu_if->vgic_ap1r[3], 3);386 __vgic_v3_write_ap1rn(cpu_if->vgic_ap1r[3], 3);
387 __vgic_v3_write_ap1rn(cpu_if->vgic_ap1r[2], 2);387 __vgic_v3_write_ap1rn(cpu_if->vgic_ap1r[2], 2);
388 /* Fall through */388 fallthrough;
389 case 6:389 case 6:
390 __vgic_v3_write_ap1rn(cpu_if->vgic_ap1r[1], 1);390 __vgic_v3_write_ap1rn(cpu_if->vgic_ap1r[1], 1);
391 /* Fall through */391 fallthrough;
392 default:392 default:
393 __vgic_v3_write_ap1rn(cpu_if->vgic_ap1r[0], 0);393 __vgic_v3_write_ap1rn(cpu_if->vgic_ap1r[0], 0);
394 }394 }
arch/arm64/kvm/hyp/vhe/switch.c+5−0
@@ -217,3 +217,8 @@ void __noreturn hyp_panic(struct kvm_cpu_context *host_ctxt) · 216 unmodified lines
217 __hyp_call_panic(spsr, elr, par, host_ctxt);217 __hyp_call_panic(spsr, elr, par, host_ctxt);
218 unreachable();218 unreachable();
219}219}
220
221asmlinkage void kvm_unexpected_el2_exception(void)
222{
223 return __kvm_unexpected_el2_exception();
224}
arch/arm64/kvm/mmu.c+14−5
@@ -343,7 +343,8 @@ static void unmap_stage2_p4ds(struct kvm_s2_mmu *mmu, pgd_t *pgd, · 342 unmodified lines
343 * destroying the VM), otherwise another faulting VCPU may come in and mess343 * destroying the VM), otherwise another faulting VCPU may come in and mess
344 * with things behind our backs.344 * with things behind our backs.
345 */345 */
346static void unmap_stage2_range(struct kvm_s2_mmu *mmu, phys_addr_t start, u64 size)346static void __unmap_stage2_range(struct kvm_s2_mmu *mmu, phys_addr_t start, u64 size,
347 bool may_block)
347{348{
348 struct kvm *kvm = mmu->kvm;349 struct kvm *kvm = mmu->kvm;
349 pgd_t *pgd;350 pgd_t *pgd;
@@ -369,11 +370,16 @@ static void unmap_stage2_range(struct kvm_s2_mmu *mmu, phys_addr_t start, u64 si · 19 unmodified lines
369 * If the range is too large, release the kvm->mmu_lock370 * If the range is too large, release the kvm->mmu_lock
370 * to prevent starvation and lockup detector warnings.371 * to prevent starvation and lockup detector warnings.
371 */372 */
372 if (next != end)373 if (may_block && next != end)
373 cond_resched_lock(&kvm->mmu_lock);374 cond_resched_lock(&kvm->mmu_lock);
374 } while (pgd++, addr = next, addr != end);375 } while (pgd++, addr = next, addr != end);
375}376}
376 377
378static void unmap_stage2_range(struct kvm_s2_mmu *mmu, phys_addr_t start, u64 size)
379{
380 __unmap_stage2_range(mmu, start, size, true);
381}
382
377static void stage2_flush_ptes(struct kvm_s2_mmu *mmu, pmd_t *pmd,383static void stage2_flush_ptes(struct kvm_s2_mmu *mmu, pmd_t *pmd,
378 phys_addr_t addr, phys_addr_t end)384 phys_addr_t addr, phys_addr_t end)
379{385{
@@ -2208,18 +2214,21 @@ static int handle_hva_to_gpa(struct kvm *kvm, · 1828 unmodified lines
2208 2214
2209static int kvm_unmap_hva_handler(struct kvm *kvm, gpa_t gpa, u64 size, void *data)2215static int kvm_unmap_hva_handler(struct kvm *kvm, gpa_t gpa, u64 size, void *data)
2210{2216{
2211 unmap_stage2_range(&kvm->arch.mmu, gpa, size);2217 unsigned flags = *(unsigned *)data;
2218 bool may_block = flags & MMU_NOTIFIER_RANGE_BLOCKABLE;
2219
2220 __unmap_stage2_range(&kvm->arch.mmu, gpa, size, may_block);
2212 return 0;2221 return 0;
2213}2222}
2214 2223
2215int kvm_unmap_hva_range(struct kvm *kvm,2224int kvm_unmap_hva_range(struct kvm *kvm,
2216 unsigned long start, unsigned long end)2225 unsigned long start, unsigned long end, unsigned flags)
2217{2226{
2218 if (!kvm->arch.mmu.pgd)2227 if (!kvm->arch.mmu.pgd)
2219 return 0;2228 return 0;
2220 2229
2221 trace_kvm_unmap_hva_range(start, end);2230 trace_kvm_unmap_hva_range(start, end);
2222 handle_hva_to_gpa(kvm, start, end, &kvm_unmap_hva_handler, NULL);2231 handle_hva_to_gpa(kvm, start, end, &kvm_unmap_hva_handler, &flags);
2223 return 0;2232 return 0;
2224}2233}
2225 2234
arch/arm64/mm/context.c+1−1
@@ -45,7 +45,7 @@ static u32 get_cpu_asid_bits(void) · 44 unmodified lines
45 default:45 default:
46 pr_warn("CPU%d: Unknown ASID size (%d); assuming 8-bit\n",46 pr_warn("CPU%d: Unknown ASID size (%d); assuming 8-bit\n",
47 smp_processor_id(), fld);47 smp_processor_id(), fld);
48 /* Fallthrough */48 fallthrough;
49 case 0:49 case 0:
50 asid = 8;50 asid = 8;
51 break;51 break;
arch/c6x/kernel/signal.c+2−2
@@ -220,7 +220,7 @@ handle_restart(struct pt_regs *regs, struct k_sigaction *ka, int has_handler) · 219 unmodified lines
220 regs->a4 = -EINTR;220 regs->a4 = -EINTR;
221 break;221 break;
222 }222 }
223 /* fallthrough */223 fallthrough;
224 case -ERESTARTNOINTR:224 case -ERESTARTNOINTR:
225do_restart:225do_restart:
226 regs->a4 = regs->orig_a4;226 regs->a4 = regs->orig_a4;
@@ -252,7 +252,7 @@ static void handle_signal(struct ksignal *ksig, struct pt_regs *regs, · 25 unmodified lines
252 break;252 break;
253 }253 }
254 254
255 /* fallthrough */255 fallthrough;
256 case -ERESTARTNOINTR:256 case -ERESTARTNOINTR:
257 regs->a4 = regs->orig_a4;257 regs->a4 = regs->orig_a4;
258 regs->pc -= 4;258 regs->pc -= 4;
arch/csky/kernel/signal.c+1−1
@@ -194,7 +194,7 @@ static void handle_signal(struct ksignal *ksig, struct pt_regs *regs) · 193 unmodified lines
194 regs->a0 = -EINTR;194 regs->a0 = -EINTR;
195 break;195 break;
196 }196 }
197 /* fallthrough */197 fallthrough;
198 case -ERESTARTNOINTR:198 case -ERESTARTNOINTR:
199 regs->a0 = regs->orig_a0;199 regs->a0 = regs->orig_a0;
200 regs->pc -= TRAP0_SIZE;200 regs->pc -= TRAP0_SIZE;
arch/h8300/kernel/signal.c+1−1
@@ -227,7 +227,7 @@ handle_restart(struct pt_regs *regs, struct k_sigaction *ka) · 226 unmodified lines
227 regs->er0 = -EINTR;227 regs->er0 = -EINTR;
228 break;228 break;
229 }229 }
230 /* fallthrough */230 fallthrough;
231 case -ERESTARTNOINTR:231 case -ERESTARTNOINTR:
232do_restart:232do_restart:
233 regs->er0 = regs->orig_er0;233 regs->er0 = regs->orig_er0;
arch/hexagon/kernel/module.c+1−1
@@ -120,7 +120,7 @@ int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab, · 119 unmodified lines
120 }120 }
121 case R_HEXAGON_HI16:121 case R_HEXAGON_HI16:
122 value = (value>>16) & 0xffff;122 value = (value>>16) & 0xffff;
123 /* fallthrough */123 fallthrough;
124 case R_HEXAGON_LO16:124 case R_HEXAGON_LO16:
125 *location &= ~0x00c03fff;125 *location &= ~0x00c03fff;
126 *location |= value & 0x3fff;126 *location |= value & 0x3fff;
arch/hexagon/kernel/signal.c+1−1
@@ -155,7 +155,7 @@ static void handle_signal(struct ksignal *ksig, struct pt_regs *regs) · 154 unmodified lines
155 regs->r00 = -EINTR;155 regs->r00 = -EINTR;
156 break;156 break;
157 }157 }
158 /* Fall through */158 fallthrough;
159 case -ERESTARTNOINTR:159 case -ERESTARTNOINTR:
160 regs->r06 = regs->syscall_nr;160 regs->r06 = regs->syscall_nr;
161 pt_set_elr(regs, pt_elr(regs) - 4);161 pt_set_elr(regs, pt_elr(regs) - 4);
arch/ia64/include/asm/pgtable.h+9−0
@@ -366,6 +366,15 @@ pgd_index (unsigned long address) · 365 unmodified lines
366}366}
367#define pgd_index pgd_index367#define pgd_index pgd_index
368 368
369/*
370 * In the kernel's mapped region we know everything is in region number 5, so
371 * as an optimisation its PGD already points to the area for that region.
372 * However, this also means that we cannot use pgd_index() and we must
373 * never add the region here.
374 */
375#define pgd_offset_k(addr) \
376 (init_mm.pgd + (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)))
377
369/* Look up a pgd entry in the gate area. On IA-64, the gate-area378/* Look up a pgd entry in the gate area. On IA-64, the gate-area
370 resides in the kernel-mapped segment, hence we use pgd_offset_k()379 resides in the kernel-mapped segment, hence we use pgd_offset_k()
371 here. */380 here. */
arch/ia64/kernel/crash.c+1−1
@@ -163,7 +163,7 @@ kdump_init_notifier(struct notifier_block *self, unsigned long val, void *data) · 162 unmodified lines
163 case DIE_INIT_MONARCH_LEAVE:163 case DIE_INIT_MONARCH_LEAVE:
164 if (!kdump_freeze_monarch)164 if (!kdump_freeze_monarch)
165 break;165 break;
166 /* fall through */166 fallthrough;
167 case DIE_INIT_SLAVE_LEAVE:167 case DIE_INIT_SLAVE_LEAVE:
168 case DIE_INIT_MONARCH_ENTER:168 case DIE_INIT_MONARCH_ENTER:
169 case DIE_MCA_RENDZVOUS_LEAVE:169 case DIE_MCA_RENDZVOUS_LEAVE:
arch/ia64/kernel/ia64_ksyms.c+1−1
@@ -3,7 +3,7 @@ · 2 unmodified lines
3 * Architecture-specific kernel symbols3 * Architecture-specific kernel symbols
4 */4 */
5 5
6#ifdef CONFIG_VIRTUAL_MEM_MAP6#if defined(CONFIG_VIRTUAL_MEM_MAP) || defined(CONFIG_DISCONTIGMEM)
7#include <linux/compiler.h>7#include <linux/compiler.h>
8#include <linux/export.h>8#include <linux/export.h>
9#include <linux/memblock.h>9#include <linux/memblock.h>
arch/ia64/kernel/module.c+1−1
@@ -654,7 +654,7 @@ do_reloc (struct module *mod, uint8_t r_type, Elf64_Sym *sym, uint64_t addend, · 653 unmodified lines
654 }654 }
655 } else if (!is_internal(mod, val))655 } else if (!is_internal(mod, val))
656 val = get_plt(mod, location, val, &ok);656 val = get_plt(mod, location, val, &ok);
657 /* FALL THROUGH */657 fallthrough;
658 default:658 default:
659 val -= bundle(location);659 val -= bundle(location);
660 break;660 break;
arch/ia64/kernel/perfmon.c+1−1
@@ -3472,7 +3472,7 @@ pfm_restart(pfm_context_t *ctx, void *arg, int count, struct pt_regs *regs) · 3471 unmodified lines
3472 break;3472 break;
3473 case PFM_CTX_LOADED: 3473 case PFM_CTX_LOADED:
3474 if (CTX_HAS_SMPL(ctx) && fmt->fmt_restart_active) break;3474 if (CTX_HAS_SMPL(ctx) && fmt->fmt_restart_active) break;
3475 /* fall through */3475 fallthrough;
3476 case PFM_CTX_UNLOADED:3476 case PFM_CTX_UNLOADED:
3477 case PFM_CTX_ZOMBIE:3477 case PFM_CTX_ZOMBIE:
3478 DPRINT(("invalid state=%d\n", state));3478 DPRINT(("invalid state=%d\n", state));
arch/ia64/kernel/signal.c+1−1
@@ -374,7 +374,7 @@ ia64_do_signal (struct sigscratch *scr, long in_syscall) · 373 unmodified lines
374 /* note: scr->pt.r10 is already -1 */374 /* note: scr->pt.r10 is already -1 */
375 break;375 break;
376 }376 }
377 /*FALLTHRU*/377 fallthrough;
378 case ERESTARTNOINTR:378 case ERESTARTNOINTR:
379 ia64_decrement_ip(&scr->pt);379 ia64_decrement_ip(&scr->pt);
380 restart = 0; /* don't restart twice if handle_signal() fails... */380 restart = 0; /* don't restart twice if handle_signal() fails... */
arch/ia64/kernel/unaligned.c+3−3
@@ -1431,7 +1431,7 @@ ia64_handle_unaligned (unsigned long ifa, struct pt_regs *regs) · 1430 unmodified lines
1431 if (u.insn.x)1431 if (u.insn.x)
1432 /* oops, really a semaphore op (cmpxchg, etc) */1432 /* oops, really a semaphore op (cmpxchg, etc) */
1433 goto failure;1433 goto failure;
1434 /*FALLTHRU*/1434 fallthrough;
1435 case LDS_IMM_OP:1435 case LDS_IMM_OP:
1436 case LDSA_IMM_OP:1436 case LDSA_IMM_OP:
1437 case LDFS_OP:1437 case LDFS_OP:
@@ -1459,7 +1459,7 @@ ia64_handle_unaligned (unsigned long ifa, struct pt_regs *regs) · 21 unmodified lines
1459 if (u.insn.x)1459 if (u.insn.x)
1460 /* oops, really a semaphore op (cmpxchg, etc) */1460 /* oops, really a semaphore op (cmpxchg, etc) */
1461 goto failure;1461 goto failure;
1462 /*FALLTHRU*/1462 fallthrough;
1463 case LD_IMM_OP:1463 case LD_IMM_OP:
1464 case LDA_IMM_OP:1464 case LDA_IMM_OP:
1465 case LDBIAS_IMM_OP:1465 case LDBIAS_IMM_OP:
@@ -1475,7 +1475,7 @@ ia64_handle_unaligned (unsigned long ifa, struct pt_regs *regs) · 9 unmodified lines
1475 if (u.insn.x)1475 if (u.insn.x)
1476 /* oops, really a semaphore op (cmpxchg, etc) */1476 /* oops, really a semaphore op (cmpxchg, etc) */
1477 goto failure;1477 goto failure;
1478 /*FALLTHRU*/1478 fallthrough;
1479 case ST_IMM_OP:1479 case ST_IMM_OP:
1480 case STREL_IMM_OP:1480 case STREL_IMM_OP:
1481 ret = emulate_store_int(ifa, u.insn, regs);1481 ret = emulate_store_int(ifa, u.insn, regs);
arch/ia64/kernel/unwind.c+1−1
@@ -324,7 +324,7 @@ unw_access_gr (struct unw_frame_info *info, int regnum, unsigned long *val, char · 323 unmodified lines
324 return 0;324 return 0;
325 }325 }
326 }326 }
327 /* fall through */327 fallthrough;
328 case UNW_NAT_NONE:328 case UNW_NAT_NONE:
329 dummy_nat = 0;329 dummy_nat = 0;
330 nat_addr = &dummy_nat;330 nat_addr = &dummy_nat;
arch/m68k/atari/atakeyb.c+1−1
@@ -207,7 +207,7 @@ repeat: · 206 unmodified lines
207 self_test_last_rcv = jiffies;207 self_test_last_rcv = jiffies;
208 break;208 break;
209 }209 }
210 /* FALL THROUGH */210 fallthrough;
211 211
212 default:212 default:
213 break_flag = scancode & BREAK_MASK;213 break_flag = scancode & BREAK_MASK;
arch/m68k/kernel/signal.c+1−1
@@ -1067,7 +1067,7 @@ handle_restart(struct pt_regs *regs, struct k_sigaction *ka, int has_handler) · 1066 unmodified lines
1067 regs->d0 = -EINTR;1067 regs->d0 = -EINTR;
1068 break;1068 break;
1069 }1069 }
1070 /* fallthrough */1070 fallthrough;
1071 case -ERESTARTNOINTR:1071 case -ERESTARTNOINTR:
1072 do_restart:1072 do_restart:
1073 regs->d0 = regs->orig_d0;1073 regs->d0 = regs->orig_d0;
arch/m68k/mac/config.c+1−1
@@ -1018,7 +1018,7 @@ int __init mac_platform_init(void) · 1017 unmodified lines
1018 */1018 */
1019 platform_device_register_simple("mac_scsi", 1,1019 platform_device_register_simple("mac_scsi", 1,
1020 mac_scsi_duo_rsrc, ARRAY_SIZE(mac_scsi_duo_rsrc));1020 mac_scsi_duo_rsrc, ARRAY_SIZE(mac_scsi_duo_rsrc));
1021 /* fall through */1021 fallthrough;
1022 case MAC_SCSI_OLD:1022 case MAC_SCSI_OLD:
1023 /* Addresses from Developer Notes for Duo System,1023 /* Addresses from Developer Notes for Duo System,
1024 * PowerBook 180 & 160, 140 & 170, Macintosh IIsi1024 * PowerBook 180 & 160, 140 & 170, Macintosh IIsi
arch/m68k/mac/via.c+1−1
@@ -370,7 +370,7 @@ void via_nubus_irq_startup(int irq) · 369 unmodified lines
370 /* Allow NuBus slots 9 through F. */370 /* Allow NuBus slots 9 through F. */
371 via2[vDirA] &= 0x80 | ~(1 << irq_idx);371 via2[vDirA] &= 0x80 | ~(1 << irq_idx);
372 }372 }
373 /* fall through */373 fallthrough;
374 case MAC_VIA_IICI:374 case MAC_VIA_IICI:
375 via_irq_enable(irq);375 via_irq_enable(irq);
376 break;376 break;
arch/m68k/mm/fault.c+1−1
@@ -118,7 +118,7 @@ good_area: · 117 unmodified lines
118 pr_debug("do_page_fault: good_area\n");118 pr_debug("do_page_fault: good_area\n");
119 switch (error_code & 3) {119 switch (error_code & 3) {
120 default: /* 3: write, present */120 default: /* 3: write, present */
121 /* fall through */121 fallthrough;
122 case 2: /* write, not present */122 case 2: /* write, not present */
123 if (!(vma->vm_flags & VM_WRITE))123 if (!(vma->vm_flags & VM_WRITE))
124 goto acc_err;124 goto acc_err;
arch/microblaze/kernel/signal.c+1−1
@@ -249,7 +249,7 @@ handle_restart(struct pt_regs *regs, struct k_sigaction *ka, int has_handler) · 248 unmodified lines
249 regs->r3 = -EINTR;249 regs->r3 = -EINTR;
250 break;250 break;
251 }251 }
252 /* fallthrough */252 fallthrough;
253 case -ERESTARTNOINTR:253 case -ERESTARTNOINTR:
254do_restart:254do_restart:
255 /* offset of 4 bytes to re-execute trap (brki) instruction */255 /* offset of 4 bytes to re-execute trap (brki) instruction */
arch/microblaze/mm/init.c+3−0
@@ -46,6 +46,9 @@ unsigned long memory_size; · 45 unmodified lines
46EXPORT_SYMBOL(memory_size);46EXPORT_SYMBOL(memory_size);
47unsigned long lowmem_size;47unsigned long lowmem_size;
48 48
49EXPORT_SYMBOL(min_low_pfn);
50EXPORT_SYMBOL(max_low_pfn);
51
49#ifdef CONFIG_HIGHMEM52#ifdef CONFIG_HIGHMEM
50pte_t *kmap_pte;53pte_t *kmap_pte;
51EXPORT_SYMBOL(kmap_pte);54EXPORT_SYMBOL(kmap_pte);
arch/mips/include/asm/irqflags.h+5−0
@@ -137,6 +137,11 @@ static inline int arch_irqs_disabled_flags(unsigned long flags) · 136 unmodified lines
137 return !(flags & 1);137 return !(flags & 1);
138}138}
139 139
140static inline int arch_irqs_disabled(void)
141{
142 return arch_irqs_disabled_flags(arch_local_save_flags());
143}
144
140#endif /* #ifndef __ASSEMBLY__ */145#endif /* #ifndef __ASSEMBLY__ */
141 146
142/*147/*
arch/mips/include/asm/kvm_host.h+1−1
@@ -969,7 +969,7 @@ enum kvm_mips_fault_result kvm_trap_emul_gva_fault(struct kvm_vcpu *vcpu, · 968 unmodified lines
969 969
970#define KVM_ARCH_WANT_MMU_NOTIFIER970#define KVM_ARCH_WANT_MMU_NOTIFIER
971int kvm_unmap_hva_range(struct kvm *kvm,971int kvm_unmap_hva_range(struct kvm *kvm,
972 unsigned long start, unsigned long end);972 unsigned long start, unsigned long end, unsigned flags);
973int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);973int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
974int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end);974int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end);
975int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);975int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);
arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h+0−2
@@ -26,7 +26,6 @@ · 25 unmodified lines
26#define cpu_has_counter 126#define cpu_has_counter 1
27#define cpu_has_dc_aliases (PAGE_SIZE < 0x4000)27#define cpu_has_dc_aliases (PAGE_SIZE < 0x4000)
28#define cpu_has_divec 028#define cpu_has_divec 0
29#define cpu_has_ejtag 0
30#define cpu_has_inclusive_pcaches 129#define cpu_has_inclusive_pcaches 1
31#define cpu_has_llsc 130#define cpu_has_llsc 1
32#define cpu_has_mcheck 031#define cpu_has_mcheck 0
@@ -42,7 +41,6 @@ · 9 unmodified lines
42#define cpu_has_veic 041#define cpu_has_veic 0
43#define cpu_has_vint 042#define cpu_has_vint 0
44#define cpu_has_vtag_icache 043#define cpu_has_vtag_icache 0
45#define cpu_has_watch 1
46#define cpu_has_wsbh 144#define cpu_has_wsbh 1
47#define cpu_has_ic_fills_f_dc 145#define cpu_has_ic_fills_f_dc 1
48#define cpu_hwrena_impl_bits 0xc000000046#define cpu_hwrena_impl_bits 0xc0000000
arch/mips/include/asm/mach-loongson64/irq.h+0−2
@@ -2,8 +2,6 @@ · 1 unmodified line
2#ifndef __ASM_MACH_LOONGSON64_IRQ_H_2#ifndef __ASM_MACH_LOONGSON64_IRQ_H_
3#define __ASM_MACH_LOONGSON64_IRQ_H_3#define __ASM_MACH_LOONGSON64_IRQ_H_
4 4
5#include <boot_param.h>
6
7/* cpu core interrupt numbers */5/* cpu core interrupt numbers */
8#define NR_IRQS_LEGACY 166#define NR_IRQS_LEGACY 16
9#define NR_MIPS_CPU_IRQS 87#define NR_MIPS_CPU_IRQS 8
arch/mips/include/asm/mach-loongson64/mmzone.h+0−1
@@ -9,7 +9,6 @@ · 8 unmodified lines
9#ifndef _ASM_MACH_LOONGSON64_MMZONE_H9#ifndef _ASM_MACH_LOONGSON64_MMZONE_H
10#define _ASM_MACH_LOONGSON64_MMZONE_H10#define _ASM_MACH_LOONGSON64_MMZONE_H
11 11
12#include <boot_param.h>
13#define NODE_ADDRSPACE_SHIFT 4412#define NODE_ADDRSPACE_SHIFT 44
14#define NODE0_ADDRSPACE_OFFSET 0x000000000000UL13#define NODE0_ADDRSPACE_OFFSET 0x000000000000UL
15#define NODE1_ADDRSPACE_OFFSET 0x100000000000UL14#define NODE1_ADDRSPACE_OFFSET 0x100000000000UL
arch/mips/include/asm/unroll.h+32−32
@@ -28,38 +28,38 @@ · 27 unmodified lines
28 BUILD_BUG_ON(!__builtin_constant_p(times)); \28 BUILD_BUG_ON(!__builtin_constant_p(times)); \
29 \29 \
30 switch (times) { \30 switch (times) { \
31 case 32: fn(__VA_ARGS__); /* fall through */ \31 case 32: fn(__VA_ARGS__); fallthrough; \
32 case 31: fn(__VA_ARGS__); /* fall through */ \32 case 31: fn(__VA_ARGS__); fallthrough; \
33 case 30: fn(__VA_ARGS__); /* fall through */ \33 case 30: fn(__VA_ARGS__); fallthrough; \
34 case 29: fn(__VA_ARGS__); /* fall through */ \34 case 29: fn(__VA_ARGS__); fallthrough; \
35 case 28: fn(__VA_ARGS__); /* fall through */ \35 case 28: fn(__VA_ARGS__); fallthrough; \
36 case 27: fn(__VA_ARGS__); /* fall through */ \36 case 27: fn(__VA_ARGS__); fallthrough; \
37 case 26: fn(__VA_ARGS__); /* fall through */ \37 case 26: fn(__VA_ARGS__); fallthrough; \
38 case 25: fn(__VA_ARGS__); /* fall through */ \38 case 25: fn(__VA_ARGS__); fallthrough; \
39 case 24: fn(__VA_ARGS__); /* fall through */ \39 case 24: fn(__VA_ARGS__); fallthrough; \
40 case 23: fn(__VA_ARGS__); /* fall through */ \40 case 23: fn(__VA_ARGS__); fallthrough; \
41 case 22: fn(__VA_ARGS__); /* fall through */ \41 case 22: fn(__VA_ARGS__); fallthrough; \
42 case 21: fn(__VA_ARGS__); /* fall through */ \42 case 21: fn(__VA_ARGS__); fallthrough; \
43 case 20: fn(__VA_ARGS__); /* fall through */ \43 case 20: fn(__VA_ARGS__); fallthrough; \
44 case 19: fn(__VA_ARGS__); /* fall through */ \44 case 19: fn(__VA_ARGS__); fallthrough; \
45 case 18: fn(__VA_ARGS__); /* fall through */ \45 case 18: fn(__VA_ARGS__); fallthrough; \
46 case 17: fn(__VA_ARGS__); /* fall through */ \46 case 17: fn(__VA_ARGS__); fallthrough; \
47 case 16: fn(__VA_ARGS__); /* fall through */ \47 case 16: fn(__VA_ARGS__); fallthrough; \
48 case 15: fn(__VA_ARGS__); /* fall through */ \48 case 15: fn(__VA_ARGS__); fallthrough; \
49 case 14: fn(__VA_ARGS__); /* fall through */ \49 case 14: fn(__VA_ARGS__); fallthrough; \
50 case 13: fn(__VA_ARGS__); /* fall through */ \50 case 13: fn(__VA_ARGS__); fallthrough; \
51 case 12: fn(__VA_ARGS__); /* fall through */ \51 case 12: fn(__VA_ARGS__); fallthrough; \
52 case 11: fn(__VA_ARGS__); /* fall through */ \52 case 11: fn(__VA_ARGS__); fallthrough; \
53 case 10: fn(__VA_ARGS__); /* fall through */ \53 case 10: fn(__VA_ARGS__); fallthrough; \
54 case 9: fn(__VA_ARGS__); /* fall through */ \54 case 9: fn(__VA_ARGS__); fallthrough; \
55 case 8: fn(__VA_ARGS__); /* fall through */ \55 case 8: fn(__VA_ARGS__); fallthrough; \
56 case 7: fn(__VA_ARGS__); /* fall through */ \56 case 7: fn(__VA_ARGS__); fallthrough; \
57 case 6: fn(__VA_ARGS__); /* fall through */ \57 case 6: fn(__VA_ARGS__); fallthrough; \
58 case 5: fn(__VA_ARGS__); /* fall through */ \58 case 5: fn(__VA_ARGS__); fallthrough; \
59 case 4: fn(__VA_ARGS__); /* fall through */ \59 case 4: fn(__VA_ARGS__); fallthrough; \
60 case 3: fn(__VA_ARGS__); /* fall through */ \60 case 3: fn(__VA_ARGS__); fallthrough; \
61 case 2: fn(__VA_ARGS__); /* fall through */ \61 case 2: fn(__VA_ARGS__); fallthrough; \
62 case 1: fn(__VA_ARGS__); /* fall through */ \62 case 1: fn(__VA_ARGS__); fallthrough; \
63 case 0: break; \63 case 0: break; \
64 \64 \
65 default: \65 default: \
arch/mips/kernel/perf_event_mipsxx.c+2−2
@@ -1898,8 +1898,8 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config) · 1897 unmodified lines
1898 (base_id >= 64 && base_id < 90) ||1898 (base_id >= 64 && base_id < 90) ||
1899 (base_id >= 128 && base_id < 164) ||1899 (base_id >= 128 && base_id < 164) ||
1900 (base_id >= 192 && base_id < 200) ||1900 (base_id >= 192 && base_id < 200) ||
1901 (base_id >= 256 && base_id < 274) ||1901 (base_id >= 256 && base_id < 275) ||
1902 (base_id >= 320 && base_id < 358) ||1902 (base_id >= 320 && base_id < 361) ||
1903 (base_id >= 384 && base_id < 574))1903 (base_id >= 384 && base_id < 574))
1904 break;1904 break;
1905 1905
arch/mips/kernel/smp-bmips.c+2−0
@@ -239,6 +239,8 @@ static int bmips_boot_secondary(int cpu, struct task_struct *idle) · 238 unmodified lines
239 */239 */
240static void bmips_init_secondary(void)240static void bmips_init_secondary(void)
241{241{
242 bmips_cpu_setup();
243
242 switch (current_cpu_type()) {244 switch (current_cpu_type()) {
243 case CPU_BMIPS4350:245 case CPU_BMIPS4350:
244 case CPU_BMIPS4380:246 case CPU_BMIPS4380:
arch/mips/kernel/traps.c+12−0
@@ -1287,6 +1287,18 @@ static int enable_restore_fp_context(int msa) · 1286 unmodified lines
1287 err = own_fpu_inatomic(1);1287 err = own_fpu_inatomic(1);
1288 if (msa && !err) {1288 if (msa && !err) {
1289 enable_msa();1289 enable_msa();
1290 /*
1291 * with MSA enabled, userspace can see MSACSR
1292 * and MSA regs, but the values in them are from
1293 * other task before current task, restore them
1294 * from saved fp/msa context
1295 */
1296 write_msa_csr(current->thread.fpu.msacsr);
1297 /*
1298 * own_fpu_inatomic(1) just restore low 64bit,
1299 * fix the high 64bit
1300 */
1301 init_msa_upper();
1290 set_thread_flag(TIF_USEDMSA);1302 set_thread_flag(TIF_USEDMSA);
1291 set_thread_flag(TIF_MSA_CTX_LIVE);1303 set_thread_flag(TIF_MSA_CTX_LIVE);
1292 }1304 }
arch/mips/kvm/mmu.c+2−1
@@ -486,7 +486,8 @@ static int kvm_unmap_hva_handler(struct kvm *kvm, gfn_t gfn, gfn_t gfn_end, · 485 unmodified lines
486 return 1;486 return 1;
487}487}
488 488
489int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end)489int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end,
490 unsigned flags)
490{491{
491 handle_hva_to_gpa(kvm, start, end, &kvm_unmap_hva_handler, NULL);492 handle_hva_to_gpa(kvm, start, end, &kvm_unmap_hva_handler, NULL);
492 493
arch/mips/mm/c-r4k.c+4−0
@@ -1712,7 +1712,11 @@ static void setup_scache(void) · 1711 unmodified lines
1712 printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",1712 printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
1713 scache_size >> 10,1713 scache_size >> 10,
1714 way_string[c->scache.ways], c->scache.linesz);1714 way_string[c->scache.ways], c->scache.linesz);
1715
1716 if (current_cpu_type() == CPU_BMIPS5000)
1717 c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1715 }1718 }
1719
1716#else1720#else
1717 if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))1721 if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
1718 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");1722 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
arch/mips/oprofile/op_model_mipsxx.c+3−1
@@ -245,7 +245,6 @@ static int mipsxx_perfcount_handler(void) · 244 unmodified lines
245 245
246 switch (counters) {246 switch (counters) {
247#define HANDLE_COUNTER(n) \247#define HANDLE_COUNTER(n) \
248 fallthrough; \
249 case n + 1: \248 case n + 1: \
250 control = r_c0_perfctrl ## n(); \249 control = r_c0_perfctrl ## n(); \
251 counter = r_c0_perfcntr ## n(); \250 counter = r_c0_perfcntr ## n(); \
@@ -256,8 +255,11 @@ static int mipsxx_perfcount_handler(void) · 4 unmodified lines
256 handled = IRQ_HANDLED; \255 handled = IRQ_HANDLED; \
257 }256 }
258 HANDLE_COUNTER(3)257 HANDLE_COUNTER(3)
258 fallthrough;
259 HANDLE_COUNTER(2)259 HANDLE_COUNTER(2)
260 fallthrough;
260 HANDLE_COUNTER(1)261 HANDLE_COUNTER(1)
262 fallthrough;
261 HANDLE_COUNTER(0)263 HANDLE_COUNTER(0)
262 }264 }
263 265
arch/mips/sni/a20r.c+2−2
@@ -222,8 +222,8 @@ void __init sni_a20r_irq_init(void) · 221 unmodified lines
222 irq_set_chip_and_handler(i, &a20r_irq_type, handle_level_irq);222 irq_set_chip_and_handler(i, &a20r_irq_type, handle_level_irq);
223 sni_hwint = a20r_hwint;223 sni_hwint = a20r_hwint;
224 change_c0_status(ST0_IM, IE_IRQ0);224 change_c0_status(ST0_IM, IE_IRQ0);
225 if (request_irq(SNI_A20R_IRQ_BASE + 3, sni_isa_irq_handler, 0, "ISA",225 if (request_irq(SNI_A20R_IRQ_BASE + 3, sni_isa_irq_handler,
226 NULL))226 IRQF_SHARED, "ISA", sni_isa_irq_handler))
227 pr_err("Failed to register ISA interrupt\n");227 pr_err("Failed to register ISA interrupt\n");
228}228}
229 229
arch/nds32/include/asm/irqflags.h+5−0
@@ -34,3 +34,8 @@ static inline int arch_irqs_disabled_flags(unsigned long flags) · 33 unmodified lines
34{34{
35 return !flags;35 return !flags;
36}36}
37
38static inline int arch_irqs_disabled(void)
39{
40 return arch_irqs_disabled_flags(arch_local_save_flags());
41}
arch/nds32/kernel/fpu.c+6−6
@@ -45,7 +45,7 @@ void save_fpu(struct task_struct *tsk) · 44 unmodified lines
45 : /* no output */45 : /* no output */
46 : "r" (&tsk->thread.fpu)46 : "r" (&tsk->thread.fpu)
47 : "memory");47 : "memory");
48 /* fall through */48 fallthrough;
49 case SP32_DP16_reg:49 case SP32_DP16_reg:
50 asm volatile ("fsdi $fd15, [%0+0x78]\n\t"50 asm volatile ("fsdi $fd15, [%0+0x78]\n\t"
51 "fsdi $fd14, [%0+0x70]\n\t"51 "fsdi $fd14, [%0+0x70]\n\t"
@@ -58,7 +58,7 @@ void save_fpu(struct task_struct *tsk) · 6 unmodified lines
58 : /* no output */58 : /* no output */
59 : "r" (&tsk->thread.fpu)59 : "r" (&tsk->thread.fpu)
60 : "memory");60 : "memory");
61 /* fall through */61 fallthrough;
62 case SP16_DP8_reg:62 case SP16_DP8_reg:
63 asm volatile ("fsdi $fd7, [%0+0x38]\n\t"63 asm volatile ("fsdi $fd7, [%0+0x38]\n\t"
64 "fsdi $fd6, [%0+0x30]\n\t"64 "fsdi $fd6, [%0+0x30]\n\t"
@@ -67,7 +67,7 @@ void save_fpu(struct task_struct *tsk) · 2 unmodified lines
67 : /* no output */67 : /* no output */
68 : "r" (&tsk->thread.fpu)68 : "r" (&tsk->thread.fpu)
69 : "memory");69 : "memory");
70 /* fall through */70 fallthrough;
71 case SP8_DP4_reg:71 case SP8_DP4_reg:
72 asm volatile ("fsdi $fd3, [%1+0x18]\n\t"72 asm volatile ("fsdi $fd3, [%1+0x18]\n\t"
73 "fsdi $fd2, [%1+0x10]\n\t"73 "fsdi $fd2, [%1+0x10]\n\t"
@@ -108,7 +108,7 @@ void load_fpu(const struct fpu_struct *fpregs) · 34 unmodified lines
108 "fldi $fd16, [%0+0x80]\n\t"108 "fldi $fd16, [%0+0x80]\n\t"
109 : /* no output */109 : /* no output */
110 : "r" (fpregs));110 : "r" (fpregs));
111 /* fall through */111 fallthrough;
112 case SP32_DP16_reg:112 case SP32_DP16_reg:
113 asm volatile ("fldi $fd15, [%0+0x78]\n\t"113 asm volatile ("fldi $fd15, [%0+0x78]\n\t"
114 "fldi $fd14, [%0+0x70]\n\t"114 "fldi $fd14, [%0+0x70]\n\t"
@@ -120,7 +120,7 @@ void load_fpu(const struct fpu_struct *fpregs) · 5 unmodified lines
120 "fldi $fd8, [%0+0x40]\n\t"120 "fldi $fd8, [%0+0x40]\n\t"
121 : /* no output */121 : /* no output */
122 : "r" (fpregs));122 : "r" (fpregs));
123 /* fall through */123 fallthrough;
124 case SP16_DP8_reg:124 case SP16_DP8_reg:
125 asm volatile ("fldi $fd7, [%0+0x38]\n\t"125 asm volatile ("fldi $fd7, [%0+0x38]\n\t"
126 "fldi $fd6, [%0+0x30]\n\t"126 "fldi $fd6, [%0+0x30]\n\t"
@@ -128,7 +128,7 @@ void load_fpu(const struct fpu_struct *fpregs) · 1 unmodified line
128 "fldi $fd4, [%0+0x20]\n\t"128 "fldi $fd4, [%0+0x20]\n\t"
129 : /* no output */129 : /* no output */
130 : "r" (fpregs));130 : "r" (fpregs));
131 /* fall through */131 fallthrough;
132 case SP8_DP4_reg:132 case SP8_DP4_reg:
133 asm volatile ("fldi $fd3, [%1+0x18]\n\t"133 asm volatile ("fldi $fd3, [%1+0x18]\n\t"
134 "fldi $fd2, [%1+0x10]\n\t"134 "fldi $fd2, [%1+0x10]\n\t"
arch/nds32/kernel/signal.c+2−2
@@ -316,7 +316,7 @@ static void handle_signal(struct ksignal *ksig, struct pt_regs *regs) · 315 unmodified lines
316 regs->uregs[0] = -EINTR;316 regs->uregs[0] = -EINTR;
317 break;317 break;
318 }318 }
319 /* Else, fall through */319 fallthrough;
320 case -ERESTARTNOINTR:320 case -ERESTARTNOINTR:
321 regs->uregs[0] = regs->orig_r0;321 regs->uregs[0] = regs->orig_r0;
322 regs->ipc -= 4;322 regs->ipc -= 4;
@@ -361,7 +361,7 @@ static void do_signal(struct pt_regs *regs) · 38 unmodified lines
361 switch (regs->uregs[0]) {361 switch (regs->uregs[0]) {
362 case -ERESTART_RESTARTBLOCK:362 case -ERESTART_RESTARTBLOCK:
363 regs->uregs[15] = __NR_restart_syscall;363 regs->uregs[15] = __NR_restart_syscall;
364 /* Fall through */364 fallthrough;
365 case -ERESTARTNOHAND:365 case -ERESTARTNOHAND:
366 case -ERESTARTSYS:366 case -ERESTARTSYS:
367 case -ERESTARTNOINTR:367 case -ERESTARTNOINTR:
arch/openrisc/kernel/signal.c+1−1
@@ -244,7 +244,7 @@ int do_signal(struct pt_regs *regs, int syscall) · 243 unmodified lines
244 switch (retval) {244 switch (retval) {
245 case -ERESTART_RESTARTBLOCK:245 case -ERESTART_RESTARTBLOCK:
246 restart = -2;246 restart = -2;
247 /* Fall through */247 fallthrough;
248 case -ERESTARTNOHAND:248 case -ERESTARTNOHAND:
249 case -ERESTARTSYS:249 case -ERESTARTSYS:
250 case -ERESTARTNOINTR:250 case -ERESTARTNOINTR:
arch/parisc/kernel/signal.c+1−1
@@ -502,7 +502,7 @@ syscall_restart(struct pt_regs *regs, struct k_sigaction *ka) · 501 unmodified lines
502 regs->gr[28] = -EINTR;502 regs->gr[28] = -EINTR;
503 break;503 break;
504 }504 }
505 /* fallthrough */505 fallthrough;
506 case -ERESTARTNOINTR:506 case -ERESTARTNOINTR:
507 check_syscallno_in_delay_branch(regs);507 check_syscallno_in_delay_branch(regs);
508 break;508 break;
arch/parisc/kernel/traps.c+5−6
@@ -437,7 +437,6 @@ void parisc_terminate(char *msg, struct pt_regs *regs, int code, unsigned long o · 436 unmodified lines
437 break;437 break;
438 438
439 default:439 default:
440 /* Fall through */
441 break;440 break;
442 441
443 }442 }
@@ -644,12 +643,12 @@ void notrace handle_interruption(int code, struct pt_regs *regs) · 200 unmodified lines
644 643
645 case 15:644 case 15:
646 /* Data TLB miss fault/Data page fault */645 /* Data TLB miss fault/Data page fault */
647 /* Fall through */646 fallthrough;
648 case 16:647 case 16:
649 /* Non-access instruction TLB miss fault */648 /* Non-access instruction TLB miss fault */
650 /* The instruction TLB entry needed for the target address of the FIC649 /* The instruction TLB entry needed for the target address of the FIC
651 is absent, and hardware can't find it, so we get to cleanup */650 is absent, and hardware can't find it, so we get to cleanup */
652 /* Fall through */651 fallthrough;
653 case 17:652 case 17:
654 /* Non-access data TLB miss fault/Non-access data page fault */653 /* Non-access data TLB miss fault/Non-access data page fault */
655 /* FIXME: 654 /* FIXME:
@@ -673,7 +672,7 @@ void notrace handle_interruption(int code, struct pt_regs *regs) · 17 unmodified lines
673 handle_unaligned(regs);672 handle_unaligned(regs);
674 return;673 return;
675 }674 }
676 /* Fall Through */675 fallthrough;
677 case 26: 676 case 26:
678 /* PCXL: Data memory access rights trap */677 /* PCXL: Data memory access rights trap */
679 fault_address = regs->ior;678 fault_address = regs->ior;
@@ -683,7 +682,7 @@ void notrace handle_interruption(int code, struct pt_regs *regs) · 3 unmodified lines
683 case 19:682 case 19:
684 /* Data memory break trap */683 /* Data memory break trap */
685 regs->gr[0] |= PSW_X; /* So we can single-step over the trap */684 regs->gr[0] |= PSW_X; /* So we can single-step over the trap */
686 /* fall thru */685 fallthrough;
687 case 21:686 case 21:
688 /* Page reference trap */687 /* Page reference trap */
689 handle_gdb_break(regs, TRAP_HWBKPT);688 handle_gdb_break(regs, TRAP_HWBKPT);
@@ -730,7 +729,7 @@ void notrace handle_interruption(int code, struct pt_regs *regs) · 40 unmodified lines
730 }729 }
731 mmap_read_unlock(current->mm);730 mmap_read_unlock(current->mm);
732 }731 }
733 /* Fall Through */732 fallthrough;
734 case 27: 733 case 27:
735 /* Data memory protection ID trap */734 /* Data memory protection ID trap */
736 if (code == 27 && !user_mode(regs) &&735 if (code == 27 && !user_mode(regs) &&
arch/parisc/mm/fault.c+2−2
@@ -67,7 +67,7 @@ parisc_acctyp(unsigned long code, unsigned int inst) · 66 unmodified lines
67 case 0x30000000: /* coproc2 */67 case 0x30000000: /* coproc2 */
68 if (bit22set(inst))68 if (bit22set(inst))
69 return VM_WRITE;69 return VM_WRITE;
70 /* fall through */70 fallthrough;
71 71
72 case 0x0: /* indexed/memory management */72 case 0x0: /* indexed/memory management */
73 if (bit22set(inst)) {73 if (bit22set(inst)) {
@@ -370,7 +370,7 @@ bad_area: · 296 unmodified lines
370 }370 }
371 371
372 /* probably address is outside of mapped file */372 /* probably address is outside of mapped file */
373 /* fall through */373 fallthrough;
374 case 17: /* NA data TLB miss / page fault */374 case 17: /* NA data TLB miss / page fault */
375 case 18: /* Unaligned access - PCXS only */375 case 18: /* Unaligned access - PCXS only */
376 signo = SIGBUS;376 signo = SIGBUS;
arch/powerpc/Kconfig+12−0
@@ -860,6 +860,18 @@ config PPC_SUBPAGE_PROT · 859 unmodified lines
860 860
861 If unsure, say N here.861 If unsure, say N here.
862 862
863config PPC_PROT_SAO_LPAR
864 bool "Support PROT_SAO mappings in LPARs"
865 depends on PPC_BOOK3S_64
866 help
867 This option adds support for PROT_SAO mappings from userspace
868 inside LPARs on supported CPUs.
869
870 This may cause issues when performing guest migration from
871 a CPU that supports SAO to one that does not.
872
873 If unsure, say N here.
874
863config PPC_COPRO_BASE875config PPC_COPRO_BASE
864 bool876 bool
865 877
arch/powerpc/include/asm/book3s/64/pgtable.h+3−5
@@ -20,13 +20,9 @@ · 19 unmodified lines
20#define _PAGE_RW (_PAGE_READ | _PAGE_WRITE)20#define _PAGE_RW (_PAGE_READ | _PAGE_WRITE)
21#define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC)21#define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC)
22#define _PAGE_PRIVILEGED 0x00008 /* kernel access only */22#define _PAGE_PRIVILEGED 0x00008 /* kernel access only */
23 23#define _PAGE_SAO 0x00010 /* Strong access order */
24#define _PAGE_CACHE_CTL 0x00030 /* Bits for the folowing cache modes */
25 /* No bits set is normal cacheable memory */
26 /* 0x00010 unused, is SAO bit on radix POWER9 */
27#define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */24#define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */
28#define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */25#define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */
29
30#define _PAGE_DIRTY 0x00080 /* C: page changed */26#define _PAGE_DIRTY 0x00080 /* C: page changed */
31#define _PAGE_ACCESSED 0x00100 /* R: page referenced */27#define _PAGE_ACCESSED 0x00100 /* R: page referenced */
32/*28/*
@@ -828,6 +824,8 @@ static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, · 795 unmodified lines
828 return hash__set_pte_at(mm, addr, ptep, pte, percpu);824 return hash__set_pte_at(mm, addr, ptep, pte, percpu);
829}825}
830 826
827#define _PAGE_CACHE_CTL (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT)
828
831#define pgprot_noncached pgprot_noncached829#define pgprot_noncached pgprot_noncached
832static inline pgprot_t pgprot_noncached(pgprot_t prot)830static inline pgprot_t pgprot_noncached(pgprot_t prot)
833{831{
arch/powerpc/include/asm/cputable.h+10−5
@@ -9,6 +9,11 @@ · 8 unmodified lines
9 9
10#ifndef __ASSEMBLY__10#ifndef __ASSEMBLY__
11 11
12/*
13 * Added to include __machine_check_early_realmode_* functions
14 */
15#include <asm/mce.h>
16
12/* This structure can grow, it's real size is used by head.S code17/* This structure can grow, it's real size is used by head.S code
13 * via the mkdefs mechanism.18 * via the mkdefs mechanism.
14 */19 */
@@ -191,7 +196,7 @@ static inline void cpu_feature_keys_init(void) { } · 176 unmodified lines
191#define CPU_FTR_SPURR LONG_ASM_CONST(0x0000000001000000)196#define CPU_FTR_SPURR LONG_ASM_CONST(0x0000000001000000)
192#define CPU_FTR_DSCR LONG_ASM_CONST(0x0000000002000000)197#define CPU_FTR_DSCR LONG_ASM_CONST(0x0000000002000000)
193#define CPU_FTR_VSX LONG_ASM_CONST(0x0000000004000000)198#define CPU_FTR_VSX LONG_ASM_CONST(0x0000000004000000)
194// Free LONG_ASM_CONST(0x0000000008000000)199#define CPU_FTR_SAO LONG_ASM_CONST(0x0000000008000000)
195#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0000000010000000)200#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0000000010000000)
196#define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0000000020000000)201#define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0000000020000000)
197#define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0000000040000000)202#define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0000000040000000)
@@ -436,7 +441,7 @@ static inline void cpu_feature_keys_init(void) { } · 238 unmodified lines
436 CPU_FTR_MMCRA | CPU_FTR_SMT | \441 CPU_FTR_MMCRA | CPU_FTR_SMT | \
437 CPU_FTR_COHERENT_ICACHE | \442 CPU_FTR_COHERENT_ICACHE | \
438 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \443 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
439 CPU_FTR_DSCR | CPU_FTR_ASYM_SMT | \444 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
440 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \445 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
441 CPU_FTR_CFAR | CPU_FTR_HVMODE | \446 CPU_FTR_CFAR | CPU_FTR_HVMODE | \
442 CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX )447 CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX )
@@ -445,7 +450,7 @@ static inline void cpu_feature_keys_init(void) { } · 2 unmodified lines
445 CPU_FTR_MMCRA | CPU_FTR_SMT | \450 CPU_FTR_MMCRA | CPU_FTR_SMT | \
446 CPU_FTR_COHERENT_ICACHE | \451 CPU_FTR_COHERENT_ICACHE | \
447 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \452 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
448 CPU_FTR_DSCR | \453 CPU_FTR_DSCR | CPU_FTR_SAO | \
449 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \454 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
450 CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \455 CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
451 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \456 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
@@ -456,7 +461,7 @@ static inline void cpu_feature_keys_init(void) { } · 4 unmodified lines
456 CPU_FTR_MMCRA | CPU_FTR_SMT | \461 CPU_FTR_MMCRA | CPU_FTR_SMT | \
457 CPU_FTR_COHERENT_ICACHE | \462 CPU_FTR_COHERENT_ICACHE | \
458 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \463 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
459 CPU_FTR_DSCR | \464 CPU_FTR_DSCR | CPU_FTR_SAO | \
460 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \465 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
461 CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \466 CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
462 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \467 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \
@@ -474,7 +479,7 @@ static inline void cpu_feature_keys_init(void) { } · 11 unmodified lines
474 CPU_FTR_MMCRA | CPU_FTR_SMT | \479 CPU_FTR_MMCRA | CPU_FTR_SMT | \
475 CPU_FTR_COHERENT_ICACHE | \480 CPU_FTR_COHERENT_ICACHE | \
476 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \481 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
477 CPU_FTR_DSCR | \482 CPU_FTR_DSCR | CPU_FTR_SAO | \
478 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \483 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
479 CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \484 CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
480 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \485 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \
arch/powerpc/include/asm/fixmap.h+1−1
@@ -52,7 +52,7 @@ enum fixed_addresses { · 51 unmodified lines
52 FIX_HOLE,52 FIX_HOLE,
53 /* reserve the top 128K for early debugging purposes */53 /* reserve the top 128K for early debugging purposes */
54 FIX_EARLY_DEBUG_TOP = FIX_HOLE,54 FIX_EARLY_DEBUG_TOP = FIX_HOLE,
55 FIX_EARLY_DEBUG_BASE = FIX_EARLY_DEBUG_TOP+(ALIGN(SZ_128, PAGE_SIZE)/PAGE_SIZE)-1,55 FIX_EARLY_DEBUG_BASE = FIX_EARLY_DEBUG_TOP+(ALIGN(SZ_128K, PAGE_SIZE)/PAGE_SIZE)-1,
56#ifdef CONFIG_HIGHMEM56#ifdef CONFIG_HIGHMEM
57 FIX_KMAP_BEGIN, /* reserved pte's for temporary kernel mappings */57 FIX_KMAP_BEGIN, /* reserved pte's for temporary kernel mappings */
58 FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1,58 FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1,
arch/powerpc/include/asm/hw_irq.h+4−7
@@ -200,17 +200,14 @@ static inline bool arch_irqs_disabled(void) · 199 unmodified lines
200#define powerpc_local_irq_pmu_save(flags) \200#define powerpc_local_irq_pmu_save(flags) \
201 do { \201 do { \
202 raw_local_irq_pmu_save(flags); \202 raw_local_irq_pmu_save(flags); \
203 trace_hardirqs_off(); \203 if (!raw_irqs_disabled_flags(flags)) \
204 trace_hardirqs_off(); \
204 } while(0)205 } while(0)
205#define powerpc_local_irq_pmu_restore(flags) \206#define powerpc_local_irq_pmu_restore(flags) \
206 do { \207 do { \
207 if (raw_irqs_disabled_flags(flags)) { \208 if (!raw_irqs_disabled_flags(flags)) \
208 raw_local_irq_pmu_restore(flags); \
209 trace_hardirqs_off(); \
210 } else { \
211 trace_hardirqs_on(); \209 trace_hardirqs_on(); \
212 raw_local_irq_pmu_restore(flags); \210 raw_local_irq_pmu_restore(flags); \
213 } \
214 } while(0)211 } while(0)
215#else212#else
216#define powerpc_local_irq_pmu_save(flags) \213#define powerpc_local_irq_pmu_save(flags) \
arch/powerpc/include/asm/kasan.h+8−1
@@ -15,11 +15,18 @@ · 14 unmodified lines
15#ifndef __ASSEMBLY__15#ifndef __ASSEMBLY__
16 16
17#include <asm/page.h>17#include <asm/page.h>
18#include <linux/sizes.h>
18 19
19#define KASAN_SHADOW_SCALE_SHIFT 320#define KASAN_SHADOW_SCALE_SHIFT 3
20 21
22#if defined(CONFIG_PPC_BOOK3S_32) && defined(CONFIG_MODULES) && defined(CONFIG_STRICT_KERNEL_RWX)
23#define KASAN_KERN_START ALIGN_DOWN(PAGE_OFFSET - SZ_256M, SZ_256M)
24#else
25#define KASAN_KERN_START PAGE_OFFSET
26#endif
27
21#define KASAN_SHADOW_START (KASAN_SHADOW_OFFSET + \28#define KASAN_SHADOW_START (KASAN_SHADOW_OFFSET + \
22 (PAGE_OFFSET >> KASAN_SHADOW_SCALE_SHIFT))29 (KASAN_KERN_START >> KASAN_SHADOW_SCALE_SHIFT))
23 30
24#define KASAN_SHADOW_OFFSET ASM_CONST(CONFIG_KASAN_SHADOW_OFFSET)31#define KASAN_SHADOW_OFFSET ASM_CONST(CONFIG_KASAN_SHADOW_OFFSET)
25 32
arch/powerpc/include/asm/kvm_host.h+2−1
@@ -58,7 +58,8 @@ · 57 unmodified lines
58#define KVM_ARCH_WANT_MMU_NOTIFIER58#define KVM_ARCH_WANT_MMU_NOTIFIER
59 59
60extern int kvm_unmap_hva_range(struct kvm *kvm,60extern int kvm_unmap_hva_range(struct kvm *kvm,
61 unsigned long start, unsigned long end);61 unsigned long start, unsigned long end,
62 unsigned flags);
62extern int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end);63extern int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end);
63extern int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);64extern int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);
64extern int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);65extern int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
arch/powerpc/include/asm/mce.h+7−0
@@ -210,6 +210,9 @@ struct mce_error_info { · 209 unmodified lines
210#define MCE_EVENT_RELEASE true210#define MCE_EVENT_RELEASE true
211#define MCE_EVENT_DONTRELEASE false211#define MCE_EVENT_DONTRELEASE false
212 212
213struct pt_regs;
214struct notifier_block;
215
213extern void save_mce_event(struct pt_regs *regs, long handled,216extern void save_mce_event(struct pt_regs *regs, long handled,
214 struct mce_error_info *mce_err, uint64_t nip,217 struct mce_error_info *mce_err, uint64_t nip,
215 uint64_t addr, uint64_t phys_addr);218 uint64_t addr, uint64_t phys_addr);
@@ -225,5 +228,9 @@ int mce_register_notifier(struct notifier_block *nb); · 9 unmodified lines
225int mce_unregister_notifier(struct notifier_block *nb);228int mce_unregister_notifier(struct notifier_block *nb);
226#ifdef CONFIG_PPC_BOOK3S_64229#ifdef CONFIG_PPC_BOOK3S_64
227void flush_and_reload_slb(void);230void flush_and_reload_slb(void);
231long __machine_check_early_realmode_p7(struct pt_regs *regs);
232long __machine_check_early_realmode_p8(struct pt_regs *regs);
233long __machine_check_early_realmode_p9(struct pt_regs *regs);
234long __machine_check_early_realmode_p10(struct pt_regs *regs);
228#endif /* CONFIG_PPC_BOOK3S_64 */235#endif /* CONFIG_PPC_BOOK3S_64 */
229#endif /* __ASM_PPC64_MCE_H__ */236#endif /* __ASM_PPC64_MCE_H__ */
arch/powerpc/include/asm/mman.h+27−4
@@ -13,20 +13,43 @@ · 12 unmodified lines
13#include <linux/pkeys.h>13#include <linux/pkeys.h>
14#include <asm/cpu_has_feature.h>14#include <asm/cpu_has_feature.h>
15 15
16#ifdef CONFIG_PPC_MEM_KEYS
17static inline unsigned long arch_calc_vm_prot_bits(unsigned long prot,16static inline unsigned long arch_calc_vm_prot_bits(unsigned long prot,
18 unsigned long pkey)17 unsigned long pkey)
19{18{
20 return pkey_to_vmflag_bits(pkey);19#ifdef CONFIG_PPC_MEM_KEYS
20 return (((prot & PROT_SAO) ? VM_SAO : 0) | pkey_to_vmflag_bits(pkey));
21#else
22 return ((prot & PROT_SAO) ? VM_SAO : 0);
23#endif
21}24}
22#define arch_calc_vm_prot_bits(prot, pkey) arch_calc_vm_prot_bits(prot, pkey)25#define arch_calc_vm_prot_bits(prot, pkey) arch_calc_vm_prot_bits(prot, pkey)
23 26
24static inline pgprot_t arch_vm_get_page_prot(unsigned long vm_flags)27static inline pgprot_t arch_vm_get_page_prot(unsigned long vm_flags)
25{28{
26 return __pgprot(vmflag_to_pte_pkey_bits(vm_flags));29#ifdef CONFIG_PPC_MEM_KEYS
30 return (vm_flags & VM_SAO) ?
31 __pgprot(_PAGE_SAO | vmflag_to_pte_pkey_bits(vm_flags)) :
32 __pgprot(0 | vmflag_to_pte_pkey_bits(vm_flags));
33#else
34 return (vm_flags & VM_SAO) ? __pgprot(_PAGE_SAO) : __pgprot(0);
35#endif
27}36}
28#define arch_vm_get_page_prot(vm_flags) arch_vm_get_page_prot(vm_flags)37#define arch_vm_get_page_prot(vm_flags) arch_vm_get_page_prot(vm_flags)
29#endif38
39static inline bool arch_validate_prot(unsigned long prot, unsigned long addr)
40{
41 if (prot & ~(PROT_READ | PROT_WRITE | PROT_EXEC | PROT_SEM | PROT_SAO))
42 return false;
43 if (prot & PROT_SAO) {
44 if (!cpu_has_feature(CPU_FTR_SAO))
45 return false;
46 if (firmware_has_feature(FW_FEATURE_LPAR) &&
47 !IS_ENABLED(CONFIG_PPC_PROT_SAO_LPAR))
48 return false;
49 }
50 return true;
51}
52#define arch_validate_prot arch_validate_prot
30 53
31#endif /* CONFIG_PPC64 */54#endif /* CONFIG_PPC64 */
32#endif /* _ASM_POWERPC_MMAN_H */55#endif /* _ASM_POWERPC_MMAN_H */
arch/powerpc/include/asm/nohash/64/pgtable.h+2−0
@@ -82,6 +82,8 @@ · 81 unmodified lines
82 */82 */
83#include <asm/nohash/pte-book3e.h>83#include <asm/nohash/pte-book3e.h>
84 84
85#define _PAGE_SAO 0
86
85#define PTE_RPN_MASK (~((1UL << PTE_RPN_SHIFT) - 1))87#define PTE_RPN_MASK (~((1UL << PTE_RPN_SHIFT) - 1))
86 88
87/*89/*
arch/powerpc/include/asm/perf_event.h+3−0
@@ -40,4 +40,7 @@ static inline bool is_sier_available(void) { return false; } · 39 unmodified lines
40 40
41/* To support perf_regs sier update */41/* To support perf_regs sier update */
42extern bool is_sier_available(void);42extern bool is_sier_available(void);
43/* To define perf extended regs mask value */
44extern u64 PERF_REG_EXTENDED_MASK;
45#define PERF_REG_EXTENDED_MASK PERF_REG_EXTENDED_MASK
43#endif46#endif
arch/powerpc/include/asm/perf_event_server.h+5−0
@@ -62,6 +62,11 @@ struct power_pmu { · 61 unmodified lines
62 int *blacklist_ev;62 int *blacklist_ev;
63 /* BHRB entries in the PMU */63 /* BHRB entries in the PMU */
64 int bhrb_nr;64 int bhrb_nr;
65 /*
66 * set this flag with `PERF_PMU_CAP_EXTENDED_REGS` if
67 * the pmu supports extended perf regs capability
68 */
69 int capabilities;
65};70};
66 71
67/*72/*
arch/powerpc/include/uapi/asm/mman.h+1−1
@@ -11,7 +11,7 @@ · 10 unmodified lines
11#include <asm-generic/mman-common.h>11#include <asm-generic/mman-common.h>
12 12
13 13
14#define PROT_SAO 0x10 /* Unsupported since v5.9 */14#define PROT_SAO 0x10 /* Strong Access Ordering */
15 15
16#define MAP_RENAME MAP_ANONYMOUS /* In SunOS terminology */16#define MAP_RENAME MAP_ANONYMOUS /* In SunOS terminology */
17#define MAP_NORESERVE 0x40 /* don't reserve swap pages */17#define MAP_NORESERVE 0x40 /* don't reserve swap pages */
arch/powerpc/include/uapi/asm/perf_regs.h+19−1
@@ -48,6 +48,24 @@ enum perf_event_powerpc_regs { · 47 unmodified lines
48 PERF_REG_POWERPC_DSISR,48 PERF_REG_POWERPC_DSISR,
49 PERF_REG_POWERPC_SIER,49 PERF_REG_POWERPC_SIER,
50 PERF_REG_POWERPC_MMCRA,50 PERF_REG_POWERPC_MMCRA,
51 PERF_REG_POWERPC_MAX,51 /* Extended registers */
52 PERF_REG_POWERPC_MMCR0,
53 PERF_REG_POWERPC_MMCR1,
54 PERF_REG_POWERPC_MMCR2,
55 PERF_REG_POWERPC_MMCR3,
56 PERF_REG_POWERPC_SIER2,
57 PERF_REG_POWERPC_SIER3,
58 /* Max regs without the extended regs */
59 PERF_REG_POWERPC_MAX = PERF_REG_POWERPC_MMCRA + 1,
52};60};
61
62#define PERF_REG_PMU_MASK ((1ULL << PERF_REG_POWERPC_MAX) - 1)
63
64/* PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_300 */
65#define PERF_REG_PMU_MASK_300 (((1ULL << (PERF_REG_POWERPC_MMCR2 + 1)) - 1) - PERF_REG_PMU_MASK)
66/* PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_31 */
67#define PERF_REG_PMU_MASK_31 (((1ULL << (PERF_REG_POWERPC_SIER3 + 1)) - 1) - PERF_REG_PMU_MASK)
68
69#define PERF_REG_MAX_ISA_300 (PERF_REG_POWERPC_MMCR2 + 1)
70#define PERF_REG_MAX_ISA_31 (PERF_REG_POWERPC_SIER3 + 1)
53#endif /* _UAPI_ASM_POWERPC_PERF_REGS_H */71#endif /* _UAPI_ASM_POWERPC_PERF_REGS_H */
arch/powerpc/kernel/cputable.c+19−3
@@ -72,9 +72,6 @@ extern void __setup_cpu_power9(unsigned long offset, struct cpu_spec* spec); · 71 unmodified lines
72extern void __restore_cpu_power9(void);72extern void __restore_cpu_power9(void);
73extern void __setup_cpu_power10(unsigned long offset, struct cpu_spec* spec);73extern void __setup_cpu_power10(unsigned long offset, struct cpu_spec* spec);
74extern void __restore_cpu_power10(void);74extern void __restore_cpu_power10(void);
75extern long __machine_check_early_realmode_p7(struct pt_regs *regs);
76extern long __machine_check_early_realmode_p8(struct pt_regs *regs);
77extern long __machine_check_early_realmode_p9(struct pt_regs *regs);
78#endif /* CONFIG_PPC64 */75#endif /* CONFIG_PPC64 */
79#if defined(CONFIG_E500)76#if defined(CONFIG_E500)
80extern void __setup_cpu_e5500(unsigned long offset, struct cpu_spec* spec);77extern void __setup_cpu_e5500(unsigned long offset, struct cpu_spec* spec);
@@ -542,6 +539,25 @@ static struct cpu_spec __initdata cpu_specs[] = { · 461 unmodified lines
542 .machine_check_early = __machine_check_early_realmode_p9,539 .machine_check_early = __machine_check_early_realmode_p9,
543 .platform = "power9",540 .platform = "power9",
544 },541 },
542 { /* Power10 */
543 .pvr_mask = 0xffff0000,
544 .pvr_value = 0x00800000,
545 .cpu_name = "POWER10 (raw)",
546 .cpu_features = CPU_FTRS_POWER10,
547 .cpu_user_features = COMMON_USER_POWER10,
548 .cpu_user_features2 = COMMON_USER2_POWER10,
549 .mmu_features = MMU_FTRS_POWER10,
550 .icache_bsize = 128,
551 .dcache_bsize = 128,
552 .num_pmcs = 6,
553 .pmc_type = PPC_PMC_IBM,
554 .oprofile_cpu_type = "ppc64/power10",
555 .oprofile_type = PPC_OPROFILE_INVALID,
556 .cpu_setup = __setup_cpu_power10,
557 .cpu_restore = __restore_cpu_power10,
558 .machine_check_early = __machine_check_early_realmode_p10,
559 .platform = "power10",
560 },
545 { /* Cell Broadband Engine */561 { /* Cell Broadband Engine */
546 .pvr_mask = 0xffff0000,562 .pvr_mask = 0xffff0000,
547 .pvr_value = 0x00700000,563 .pvr_value = 0x00700000,
arch/powerpc/kernel/dt_cpu_ftrs.c+1−5
@@ -64,10 +64,6 @@ struct dt_cpu_feature { · 63 unmodified lines
64 * Set up the base CPU64 * Set up the base CPU
65 */65 */
66 66
67extern long __machine_check_early_realmode_p8(struct pt_regs *regs);
68extern long __machine_check_early_realmode_p9(struct pt_regs *regs);
69extern long __machine_check_early_realmode_p10(struct pt_regs *regs);
70
71static int hv_mode;67static int hv_mode;
72 68
73static struct {69static struct {
@@ -657,7 +653,7 @@ static struct dt_cpu_feature_match __initdata · 583 unmodified lines
657 {"processor-control-facility-v3", feat_enable_dbell, CPU_FTR_DBELL},653 {"processor-control-facility-v3", feat_enable_dbell, CPU_FTR_DBELL},
658 {"processor-utilization-of-resources-register", feat_enable_purr, 0},654 {"processor-utilization-of-resources-register", feat_enable_purr, 0},
659 {"no-execute", feat_enable, 0},655 {"no-execute", feat_enable, 0},
660 /* strong-access-ordering is unused */656 {"strong-access-ordering", feat_enable, CPU_FTR_SAO},
661 {"cache-inhibited-large-page", feat_enable_large_ci, 0},657 {"cache-inhibited-large-page", feat_enable_large_ci, 0},
662 {"coprocessor-icswx", feat_enable, 0},658 {"coprocessor-icswx", feat_enable, 0},
663 {"hypervisor-virtualization-interrupt", feat_enable_hvi, 0},659 {"hypervisor-virtualization-interrupt", feat_enable_hvi, 0},
arch/powerpc/kernel/entry_64.S+4−0
@@ -113,6 +113,10 @@ END_FTR_SECTION_IFSET(CPU_FTR_TM) · 112 unmodified lines
113 ld r11,exception_marker@toc(r2)113 ld r11,exception_marker@toc(r2)
114 std r11,-16(r10) /* "regshere" marker */114 std r11,-16(r10) /* "regshere" marker */
115 115
116BEGIN_FTR_SECTION
117 HMT_MEDIUM
118END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
119
116 /*120 /*
117 * RECONCILE_IRQ_STATE without calling trace_hardirqs_off(), which121 * RECONCILE_IRQ_STATE without calling trace_hardirqs_off(), which
118 * would clobber syscall parameters. Also we always enter with IRQs122 * would clobber syscall parameters. Also we always enter with IRQs
arch/powerpc/kernel/process.c+9−3
@@ -548,7 +548,7 @@ void notrace restore_math(struct pt_regs *regs) · 547 unmodified lines
548 * are live for the user thread).548 * are live for the user thread).
549 */549 */
550 if ((!(msr & MSR_FP)) && should_restore_fp())550 if ((!(msr & MSR_FP)) && should_restore_fp())
551 new_msr |= MSR_FP | current->thread.fpexc_mode;551 new_msr |= MSR_FP;
552 552
553 if ((!(msr & MSR_VEC)) && should_restore_altivec())553 if ((!(msr & MSR_VEC)) && should_restore_altivec())
554 new_msr |= MSR_VEC;554 new_msr |= MSR_VEC;
@@ -559,11 +559,17 @@ void notrace restore_math(struct pt_regs *regs) · 4 unmodified lines
559 }559 }
560 560
561 if (new_msr) {561 if (new_msr) {
562 unsigned long fpexc_mode = 0;
563
562 msr_check_and_set(new_msr);564 msr_check_and_set(new_msr);
563 565
564 if (new_msr & MSR_FP)566 if (new_msr & MSR_FP) {
565 do_restore_fp();567 do_restore_fp();
566 568
569 // This also covers VSX, because VSX implies FP
570 fpexc_mode = current->thread.fpexc_mode;
571 }
572
567 if (new_msr & MSR_VEC)573 if (new_msr & MSR_VEC)
568 do_restore_altivec();574 do_restore_altivec();
569 575
@@ -572,7 +578,7 @@ void notrace restore_math(struct pt_regs *regs) · 2 unmodified lines
572 578
573 msr_check_and_clear(new_msr);579 msr_check_and_clear(new_msr);
574 580
575 regs->msr |= new_msr;581 regs->msr |= new_msr | fpexc_mode;
576 }582 }
577}583}
578#endif584#endif
arch/powerpc/kernel/setup-common.c+1−0
@@ -311,6 +311,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) · 310 unmodified lines
311 min = pvr & 0xFF;311 min = pvr & 0xFF;
312 break;312 break;
313 case 0x004e: /* POWER9 bits 12-15 give chip type */313 case 0x004e: /* POWER9 bits 12-15 give chip type */
314 case 0x0080: /* POWER10 bit 12 gives SMT8/4 */
314 maj = (pvr >> 8) & 0x0F;315 maj = (pvr >> 8) & 0x0F;
315 min = pvr & 0xFF;316 min = pvr & 0xFF;
316 break;317 break;
arch/powerpc/kvm/book3s.c+2−1
@@ -834,7 +834,8 @@ void kvmppc_core_commit_memory_region(struct kvm *kvm, · 833 unmodified lines
834 kvm->arch.kvm_ops->commit_memory_region(kvm, mem, old, new, change);834 kvm->arch.kvm_ops->commit_memory_region(kvm, mem, old, new, change);
835}835}
836 836
837int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end)837int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end,
838 unsigned flags)
838{839{
839 return kvm->arch.kvm_ops->unmap_hva_range(kvm, start, end);840 return kvm->arch.kvm_ops->unmap_hva_range(kvm, start, end);
840}841}
arch/powerpc/kvm/e500_mmu_host.c+2−1
@@ -734,7 +734,8 @@ static int kvm_unmap_hva(struct kvm *kvm, unsigned long hva) · 733 unmodified lines
734 return 0;734 return 0;
735}735}
736 736
737int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end)737int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end,
738 unsigned flags)
738{739{
739 /* kvm_unmap_hva flushes everything anyways */740 /* kvm_unmap_hva flushes everything anyways */
740 kvm_unmap_hva(kvm, start);741 kvm_unmap_hva(kvm, start);
arch/powerpc/mm/book3s32/mmu.c+8−1
@@ -191,10 +191,17 @@ static bool is_module_segment(unsigned long addr) · 190 unmodified lines
191{191{
192 if (!IS_ENABLED(CONFIG_MODULES))192 if (!IS_ENABLED(CONFIG_MODULES))
193 return false;193 return false;
194#ifdef MODULES_VADDR
195 if (addr < ALIGN_DOWN(MODULES_VADDR, SZ_256M))
196 return false;
197 if (addr > ALIGN(MODULES_END, SZ_256M) - 1)
198 return false;
199#else
194 if (addr < ALIGN_DOWN(VMALLOC_START, SZ_256M))200 if (addr < ALIGN_DOWN(VMALLOC_START, SZ_256M))
195 return false;201 return false;
196 if (addr >= ALIGN(VMALLOC_END, SZ_256M))202 if (addr > ALIGN(VMALLOC_END, SZ_256M) - 1)
197 return false;203 return false;
204#endif
198 return true;205 return true;
199}206}
200 207
arch/powerpc/mm/book3s64/hash_utils.c+5−1
@@ -232,6 +232,8 @@ unsigned long htab_convert_pte_flags(unsigned long pteflags) · 231 unmodified lines
232 rflags |= HPTE_R_I;232 rflags |= HPTE_R_I;
233 else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT)233 else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT)
234 rflags |= (HPTE_R_I | HPTE_R_G);234 rflags |= (HPTE_R_I | HPTE_R_G);
235 else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_SAO)
236 rflags |= (HPTE_R_W | HPTE_R_I | HPTE_R_M);
235 else237 else
236 /*238 /*
237 * Add memory coherence if cache inhibited is not set239 * Add memory coherence if cache inhibited is not set
@@ -1115,8 +1117,10 @@ void hash__early_init_mmu_secondary(void) · 877 unmodified lines
1115 && cpu_has_feature(CPU_FTR_HVMODE))1117 && cpu_has_feature(CPU_FTR_HVMODE))
1116 tlbiel_all();1118 tlbiel_all();
1117 1119
1118 if (IS_ENABLED(CONFIG_PPC_MEM_KEYS) && mmu_has_feature(MMU_FTR_PKEY))1120#ifdef CONFIG_PPC_MEM_KEYS
1121 if (mmu_has_feature(MMU_FTR_PKEY))
1119 mtspr(SPRN_UAMOR, default_uamor);1122 mtspr(SPRN_UAMOR, default_uamor);
1123#endif
1120}1124}
1121#endif /* CONFIG_SMP */1125#endif /* CONFIG_SMP */
1122 1126
arch/powerpc/net/bpf_jit_comp.c+1−1
@@ -475,7 +475,7 @@ static int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, · 474 unmodified lines
475 case BPF_JMP | BPF_JSET | BPF_K:475 case BPF_JMP | BPF_JSET | BPF_K:
476 case BPF_JMP | BPF_JSET | BPF_X:476 case BPF_JMP | BPF_JSET | BPF_X:
477 true_cond = COND_NE;477 true_cond = COND_NE;
478 /* Fall through */478 fallthrough;
479 cond_branch:479 cond_branch:
480 /* same targets, can avoid doing the test :) */480 /* same targets, can avoid doing the test :) */
481 if (filter[i].jt == filter[i].jf) {481 if (filter[i].jt == filter[i].jf) {
arch/powerpc/perf/core-book3s.c+19−5
@@ -1557,9 +1557,16 @@ nocheck: · 1556 unmodified lines
1557 ret = 0;1557 ret = 0;
1558 out:1558 out:
1559 if (has_branch_stack(event)) {1559 if (has_branch_stack(event)) {
1560 power_pmu_bhrb_enable(event);1560 u64 bhrb_filter = -1;
1561 cpuhw->bhrb_filter = ppmu->bhrb_filter_map(1561
1562 event->attr.branch_sample_type);1562 if (ppmu->bhrb_filter_map)
1563 bhrb_filter = ppmu->bhrb_filter_map(
1564 event->attr.branch_sample_type);
1565
1566 if (bhrb_filter != -1) {
1567 cpuhw->bhrb_filter = bhrb_filter;
1568 power_pmu_bhrb_enable(event);
1569 }
1563 }1570 }
1564 1571
1565 perf_pmu_enable(event->pmu);1572 perf_pmu_enable(event->pmu);
@@ -1881,7 +1888,6 @@ static int power_pmu_event_init(struct perf_event *event) · 315 unmodified lines
1881 int n;1888 int n;
1882 int err;1889 int err;
1883 struct cpu_hw_events *cpuhw;1890 struct cpu_hw_events *cpuhw;
1884 u64 bhrb_filter;
1885 1891
1886 if (!ppmu)1892 if (!ppmu)
1887 return -ENOENT;1893 return -ENOENT;
@@ -1987,7 +1993,10 @@ static int power_pmu_event_init(struct perf_event *event) · 99 unmodified lines
1987 err = power_check_constraints(cpuhw, events, cflags, n + 1);1993 err = power_check_constraints(cpuhw, events, cflags, n + 1);
1988 1994
1989 if (has_branch_stack(event)) {1995 if (has_branch_stack(event)) {
1990 bhrb_filter = ppmu->bhrb_filter_map(1996 u64 bhrb_filter = -1;
1997
1998 if (ppmu->bhrb_filter_map)
1999 bhrb_filter = ppmu->bhrb_filter_map(
1991 event->attr.branch_sample_type);2000 event->attr.branch_sample_type);
1992 2001
1993 if (bhrb_filter == -1) {2002 if (bhrb_filter == -1) {
@@ -2141,6 +2150,10 @@ static void record_and_restart(struct perf_event *event, unsigned long val, · 147 unmodified lines
2141 2150
2142 if (perf_event_overflow(event, &data, regs))2151 if (perf_event_overflow(event, &data, regs))
2143 power_pmu_stop(event, 0);2152 power_pmu_stop(event, 0);
2153 } else if (period) {
2154 /* Account for interrupt in case of invalid SIAR */
2155 if (perf_event_account_interrupt(event))
2156 power_pmu_stop(event, 0);
2144 }2157 }
2145}2158}
2146 2159
@@ -2323,6 +2336,7 @@ int register_power_pmu(struct power_pmu *pmu) · 176 unmodified lines
2323 pmu->name);2336 pmu->name);
2324 2337
2325 power_pmu.attr_groups = ppmu->attr_groups;2338 power_pmu.attr_groups = ppmu->attr_groups;
2339 power_pmu.capabilities |= (ppmu->capabilities & PERF_PMU_CAP_EXTENDED_REGS);
2326 2340
2327#ifdef MSR_HV2341#ifdef MSR_HV
2328 /*2342 /*
arch/powerpc/perf/hv-24x7.c+10−1
@@ -1128,6 +1128,15 @@ static struct bin_attribute *if_bin_attrs[] = { · 1127 unmodified lines
1128 NULL,1128 NULL,
1129};1129};
1130 1130
1131static struct attribute *cpumask_attrs[] = {
1132 &dev_attr_cpumask.attr,
1133 NULL,
1134};
1135
1136static struct attribute_group cpumask_attr_group = {
1137 .attrs = cpumask_attrs,
1138};
1139
1131static struct attribute *if_attrs[] = {1140static struct attribute *if_attrs[] = {
1132 &dev_attr_catalog_len.attr,1141 &dev_attr_catalog_len.attr,
1133 &dev_attr_catalog_version.attr,1142 &dev_attr_catalog_version.attr,
@@ -1135,7 +1144,6 @@ static struct attribute *if_attrs[] = { · 1 unmodified line
1135 &dev_attr_sockets.attr,1144 &dev_attr_sockets.attr,
1136 &dev_attr_chipspersocket.attr,1145 &dev_attr_chipspersocket.attr,
1137 &dev_attr_coresperchip.attr,1146 &dev_attr_coresperchip.attr,
1138 &dev_attr_cpumask.attr,
1139 NULL,1147 NULL,
1140};1148};
1141 1149
@@ -1151,6 +1159,7 @@ static const struct attribute_group *attr_groups[] = { · 9 unmodified lines
1151 &event_desc_group,1159 &event_desc_group,
1152 &event_long_desc_group,1160 &event_long_desc_group,
1153 &if_group,1161 &if_group,
1162 &cpumask_attr_group,
1154 NULL,1163 NULL,
1155};1164};
1156 1165
arch/powerpc/perf/imc-pmu.c+2−2
@@ -1289,7 +1289,7 @@ static int trace_imc_prepare_sample(struct trace_imc_data *mem, · 1288 unmodified lines
1289 header->misc = 0;1289 header->misc = 0;
1290 1290
1291 if (cpu_has_feature(CPU_FTR_ARCH_31)) {1291 if (cpu_has_feature(CPU_FTR_ARCH_31)) {
1292 switch (IMC_TRACE_RECORD_VAL_HVPR(mem->val)) {1292 switch (IMC_TRACE_RECORD_VAL_HVPR(be64_to_cpu(READ_ONCE(mem->val)))) {
1293 case 0:/* when MSR HV and PR not set in the trace-record */1293 case 0:/* when MSR HV and PR not set in the trace-record */
1294 header->misc |= PERF_RECORD_MISC_GUEST_KERNEL;1294 header->misc |= PERF_RECORD_MISC_GUEST_KERNEL;
1295 break;1295 break;
@@ -1297,7 +1297,7 @@ static int trace_imc_prepare_sample(struct trace_imc_data *mem, · 1 unmodified line
1297 header->misc |= PERF_RECORD_MISC_GUEST_USER;1297 header->misc |= PERF_RECORD_MISC_GUEST_USER;
1298 break;1298 break;
1299 case 2: /* MSR HV is 1 and PR is 0 */1299 case 2: /* MSR HV is 1 and PR is 0 */
1300 header->misc |= PERF_RECORD_MISC_HYPERVISOR;1300 header->misc |= PERF_RECORD_MISC_KERNEL;
1301 break;1301 break;
1302 case 3: /* MSR HV is 1 and PR is 1 */1302 case 3: /* MSR HV is 1 and PR is 1 */
1303 header->misc |= PERF_RECORD_MISC_USER;1303 header->misc |= PERF_RECORD_MISC_USER;
arch/powerpc/perf/perf_regs.c+41−3
@@ -13,9 +13,11 @@ · 12 unmodified lines
13#include <asm/ptrace.h>13#include <asm/ptrace.h>
14#include <asm/perf_regs.h>14#include <asm/perf_regs.h>
15 15
16u64 PERF_REG_EXTENDED_MASK;
17
16#define PT_REGS_OFFSET(id, r) [id] = offsetof(struct pt_regs, r)18#define PT_REGS_OFFSET(id, r) [id] = offsetof(struct pt_regs, r)
17 19
18#define REG_RESERVED (~((1ULL << PERF_REG_POWERPC_MAX) - 1))20#define REG_RESERVED (~(PERF_REG_EXTENDED_MASK | PERF_REG_PMU_MASK))
19 21
20static unsigned int pt_regs_offset[PERF_REG_POWERPC_MAX] = {22static unsigned int pt_regs_offset[PERF_REG_POWERPC_MAX] = {
21 PT_REGS_OFFSET(PERF_REG_POWERPC_R0, gpr[0]),23 PT_REGS_OFFSET(PERF_REG_POWERPC_R0, gpr[0]),
@@ -69,10 +71,36 @@ static unsigned int pt_regs_offset[PERF_REG_POWERPC_MAX] = { · 47 unmodified lines
69 PT_REGS_OFFSET(PERF_REG_POWERPC_MMCRA, dsisr),71 PT_REGS_OFFSET(PERF_REG_POWERPC_MMCRA, dsisr),
70};72};
71 73
74/* Function to return the extended register values */
75static u64 get_ext_regs_value(int idx)
76{
77 switch (idx) {
78 case PERF_REG_POWERPC_MMCR0:
79 return mfspr(SPRN_MMCR0);
80 case PERF_REG_POWERPC_MMCR1:
81 return mfspr(SPRN_MMCR1);
82 case PERF_REG_POWERPC_MMCR2:
83 return mfspr(SPRN_MMCR2);
84#ifdef CONFIG_PPC64
85 case PERF_REG_POWERPC_MMCR3:
86 return mfspr(SPRN_MMCR3);
87 case PERF_REG_POWERPC_SIER2:
88 return mfspr(SPRN_SIER2);
89 case PERF_REG_POWERPC_SIER3:
90 return mfspr(SPRN_SIER3);
91#endif
92 default: return 0;
93 }
94}
95
72u64 perf_reg_value(struct pt_regs *regs, int idx)96u64 perf_reg_value(struct pt_regs *regs, int idx)
73{97{
74 if (WARN_ON_ONCE(idx >= PERF_REG_POWERPC_MAX))98 u64 perf_reg_extended_max = PERF_REG_POWERPC_MAX;
75 return 0;99
100 if (cpu_has_feature(CPU_FTR_ARCH_31))
101 perf_reg_extended_max = PERF_REG_MAX_ISA_31;
102 else if (cpu_has_feature(CPU_FTR_ARCH_300))
103 perf_reg_extended_max = PERF_REG_MAX_ISA_300;
76 104
77 if (idx == PERF_REG_POWERPC_SIER &&105 if (idx == PERF_REG_POWERPC_SIER &&
78 (IS_ENABLED(CONFIG_FSL_EMB_PERF_EVENT) ||106 (IS_ENABLED(CONFIG_FSL_EMB_PERF_EVENT) ||
@@ -85,6 +113,16 @@ u64 perf_reg_value(struct pt_regs *regs, int idx) · 6 unmodified lines
85 IS_ENABLED(CONFIG_PPC32)))113 IS_ENABLED(CONFIG_PPC32)))
86 return 0;114 return 0;
87 115
116 if (idx >= PERF_REG_POWERPC_MAX && idx < perf_reg_extended_max)
117 return get_ext_regs_value(idx);
118
119 /*
120 * If the idx is referring to value beyond the
121 * supported registers, return 0 with a warning
122 */
123 if (WARN_ON_ONCE(idx >= perf_reg_extended_max))
124 return 0;
125
88 return regs_get_register(regs, pt_regs_offset[idx]);126 return regs_get_register(regs, pt_regs_offset[idx]);
89}127}
90 128
arch/powerpc/perf/power10-pmu.c+6−0
@@ -87,6 +87,8 @@ · 86 unmodified lines
87#define POWER10_MMCRA_IFM3 0x00000000C0000000UL87#define POWER10_MMCRA_IFM3 0x00000000C0000000UL
88#define POWER10_MMCRA_BHRB_MASK 0x00000000C0000000UL88#define POWER10_MMCRA_BHRB_MASK 0x00000000C0000000UL
89 89
90extern u64 PERF_REG_EXTENDED_MASK;
91
90/* Table of alternatives, sorted by column 0 */92/* Table of alternatives, sorted by column 0 */
91static const unsigned int power10_event_alternatives[][MAX_ALT] = {93static const unsigned int power10_event_alternatives[][MAX_ALT] = {
92 { PM_RUN_CYC_ALT, PM_RUN_CYC },94 { PM_RUN_CYC_ALT, PM_RUN_CYC },
@@ -397,6 +399,7 @@ static struct power_pmu power10_pmu = { · 304 unmodified lines
397 .cache_events = &power10_cache_events,399 .cache_events = &power10_cache_events,
398 .attr_groups = power10_pmu_attr_groups,400 .attr_groups = power10_pmu_attr_groups,
399 .bhrb_nr = 32,401 .bhrb_nr = 32,
402 .capabilities = PERF_PMU_CAP_EXTENDED_REGS,
400};403};
401 404
402int init_power10_pmu(void)405int init_power10_pmu(void)
@@ -408,6 +411,9 @@ int init_power10_pmu(void) · 5 unmodified lines
408 strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power10"))411 strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power10"))
409 return -ENODEV;412 return -ENODEV;
410 413
414 /* Set the PERF_REG_EXTENDED_MASK here */
415 PERF_REG_EXTENDED_MASK = PERF_REG_PMU_MASK_31;
416
411 rc = register_power_pmu(&power10_pmu);417 rc = register_power_pmu(&power10_pmu);
412 if (rc)418 if (rc)
413 return rc;419 return rc;
arch/powerpc/perf/power9-pmu.c+6−0
@@ -90,6 +90,8 @@ enum { · 89 unmodified lines
90#define POWER9_MMCRA_IFM3 0x00000000C0000000UL90#define POWER9_MMCRA_IFM3 0x00000000C0000000UL
91#define POWER9_MMCRA_BHRB_MASK 0x00000000C0000000UL91#define POWER9_MMCRA_BHRB_MASK 0x00000000C0000000UL
92 92
93extern u64 PERF_REG_EXTENDED_MASK;
94
93/* Nasty Power9 specific hack */95/* Nasty Power9 specific hack */
94#define PVR_POWER9_CUMULUS 0x0000200096#define PVR_POWER9_CUMULUS 0x00002000
95 97
@@ -434,6 +436,7 @@ static struct power_pmu power9_pmu = { · 338 unmodified lines
434 .cache_events = &power9_cache_events,436 .cache_events = &power9_cache_events,
435 .attr_groups = power9_pmu_attr_groups,437 .attr_groups = power9_pmu_attr_groups,
436 .bhrb_nr = 32,438 .bhrb_nr = 32,
439 .capabilities = PERF_PMU_CAP_EXTENDED_REGS,
437};440};
438 441
439int init_power9_pmu(void)442int init_power9_pmu(void)
@@ -457,6 +460,9 @@ int init_power9_pmu(void) · 17 unmodified lines
457 }460 }
458 }461 }
459 462
463 /* Set the PERF_REG_EXTENDED_MASK here */
464 PERF_REG_EXTENDED_MASK = PERF_REG_PMU_MASK_300;
465
460 rc = register_power_pmu(&power9_pmu);466 rc = register_power_pmu(&power9_pmu);
461 if (rc)467 if (rc)
462 return rc;468 return rc;
arch/powerpc/platforms/Kconfig.cputype+1−1
@@ -36,7 +36,7 @@ config PPC_BOOK3S_6xx · 35 unmodified lines
36 select PPC_HAVE_PMU_SUPPORT36 select PPC_HAVE_PMU_SUPPORT
37 select PPC_HAVE_KUEP37 select PPC_HAVE_KUEP
38 select PPC_HAVE_KUAP38 select PPC_HAVE_KUAP
39 select HAVE_ARCH_VMAP_STACK39 select HAVE_ARCH_VMAP_STACK if !ADB_PMU
40 40
41config PPC_BOOK3S_60141config PPC_BOOK3S_601
42 bool "PowerPC 601"42 bool "PowerPC 601"
arch/powerpc/platforms/powernv/idle.c+1−1
@@ -1223,7 +1223,7 @@ static void __init pnv_probe_idle_states(void) · 1222 unmodified lines
1223 return;1223 return;
1224 }1224 }
1225 1225
1226 if (pvr_version_is(PVR_POWER9))1226 if (cpu_has_feature(CPU_FTR_ARCH_300))
1227 pnv_power9_idle_init();1227 pnv_power9_idle_init();
1228 1228
1229 for (i = 0; i < nr_pnv_idle_states; i++)1229 for (i = 0; i < nr_pnv_idle_states; i++)
arch/powerpc/platforms/powernv/pci-ioda.c+1−1
@@ -2705,7 +2705,7 @@ void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe) · 2704 unmodified lines
2705 struct iommu_table *tbl = pe->table_group.tables[0];2705 struct iommu_table *tbl = pe->table_group.tables[0];
2706 int64_t rc;2706 int64_t rc;
2707 2707
2708 if (pe->dma_setup_done)2708 if (!pe->dma_setup_done)
2709 return;2709 return;
2710 2710
2711 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);2711 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
arch/powerpc/platforms/pseries/hotplug-cpu.c+12−6
@@ -107,22 +107,28 @@ static int pseries_cpu_disable(void) · 106 unmodified lines
107 */107 */
108static void pseries_cpu_die(unsigned int cpu)108static void pseries_cpu_die(unsigned int cpu)
109{109{
110 int tries;
111 int cpu_status = 1;110 int cpu_status = 1;
112 unsigned int pcpu = get_hard_smp_processor_id(cpu);111 unsigned int pcpu = get_hard_smp_processor_id(cpu);
112 unsigned long timeout = jiffies + msecs_to_jiffies(120000);
113 113
114 for (tries = 0; tries < 25; tries++) {114 while (true) {
115 cpu_status = smp_query_cpu_stopped(pcpu);115 cpu_status = smp_query_cpu_stopped(pcpu);
116 if (cpu_status == QCSS_STOPPED ||116 if (cpu_status == QCSS_STOPPED ||
117 cpu_status == QCSS_HARDWARE_ERROR)117 cpu_status == QCSS_HARDWARE_ERROR)
118 break;118 break;
119 cpu_relax();
120 119
120 if (time_after(jiffies, timeout)) {
121 pr_warn("CPU %i (hwid %i) didn't die after 120 seconds\n",
122 cpu, pcpu);
123 timeout = jiffies + msecs_to_jiffies(120000);
124 }
125
126 cond_resched();
121 }127 }
122 128
123 if (cpu_status != 0) {129 if (cpu_status == QCSS_HARDWARE_ERROR) {
124 printk("Querying DEAD? cpu %i (%i) shows %i\n",130 pr_warn("CPU %i (hwid %i) reported error while dying\n",
125 cpu, pcpu, cpu_status);131 cpu, pcpu);
126 }132 }
127 133
128 /* Isolation and deallocation are definitely done by134 /* Isolation and deallocation are definitely done by
arch/powerpc/platforms/pseries/ras.c+0−1
@@ -184,7 +184,6 @@ static void handle_system_shutdown(char event_modifier) · 183 unmodified lines
184 case EPOW_SHUTDOWN_ON_UPS:184 case EPOW_SHUTDOWN_ON_UPS:
185 pr_emerg("Loss of system power detected. System is running on"185 pr_emerg("Loss of system power detected. System is running on"
186 " UPS/battery. Check RTAS error log for details\n");186 " UPS/battery. Check RTAS error log for details\n");
187 orderly_poweroff(true);
188 break;187 break;
189 188
190 case EPOW_SHUTDOWN_LOSS_OF_CRITICAL_FUNCTIONS:189 case EPOW_SHUTDOWN_LOSS_OF_CRITICAL_FUNCTIONS:
arch/riscv/Kconfig+1−1
@@ -81,7 +81,7 @@ config RISCV · 80 unmodified lines
81 select PCI_DOMAINS_GENERIC if PCI81 select PCI_DOMAINS_GENERIC if PCI
82 select PCI_MSI if PCI82 select PCI_MSI if PCI
83 select RISCV_INTC83 select RISCV_INTC
84 select RISCV_TIMER84 select RISCV_TIMER if RISCV_SBI
85 select SPARSEMEM_STATIC if 32BIT85 select SPARSEMEM_STATIC if 32BIT
86 select SPARSE_IRQ86 select SPARSE_IRQ
87 select SYSCTL_EXCEPTION_TRACE87 select SYSCTL_EXCEPTION_TRACE
arch/riscv/Kconfig.socs+2−0
@@ -12,6 +12,7 @@ config SOC_SIFIVE · 11 unmodified lines
12 12
13config SOC_VIRT13config SOC_VIRT
14 bool "QEMU Virt Machine"14 bool "QEMU Virt Machine"
15 select CLINT_TIMER if RISCV_M_MODE
15 select POWER_RESET16 select POWER_RESET
16 select POWER_RESET_SYSCON17 select POWER_RESET_SYSCON
17 select POWER_RESET_SYSCON_POWEROFF18 select POWER_RESET_SYSCON_POWEROFF
@@ -24,6 +25,7 @@ config SOC_VIRT · 6 unmodified lines
24config SOC_KENDRYTE25config SOC_KENDRYTE
25 bool "Kendryte K210 SoC"26 bool "Kendryte K210 SoC"
26 depends on !MMU27 depends on !MMU
28 select CLINT_TIMER if RISCV_M_MODE
27 select SERIAL_SIFIVE if TTY29 select SERIAL_SIFIVE if TTY
28 select SERIAL_SIFIVE_CONSOLE if TTY30 select SERIAL_SIFIVE_CONSOLE if TTY
29 select SIFIVE_PLIC31 select SIFIVE_PLIC
arch/riscv/configs/nommu_virt_defconfig+2−5
@@ -26,6 +26,7 @@ CONFIG_EXPERT=y · 25 unmodified lines
26CONFIG_SLOB=y26CONFIG_SLOB=y
27# CONFIG_SLAB_MERGE_DEFAULT is not set27# CONFIG_SLAB_MERGE_DEFAULT is not set
28# CONFIG_MMU is not set28# CONFIG_MMU is not set
29CONFIG_SOC_VIRT=y
29CONFIG_MAXPHYSMEM_2GB=y30CONFIG_MAXPHYSMEM_2GB=y
30CONFIG_SMP=y31CONFIG_SMP=y
31CONFIG_CMDLINE="root=/dev/vda rw earlycon=uart8250,mmio,0x10000000,115200n8 console=ttyS0"32CONFIG_CMDLINE="root=/dev/vda rw earlycon=uart8250,mmio,0x10000000,115200n8 console=ttyS0"
@@ -49,7 +50,6 @@ CONFIG_VIRTIO_BLK=y · 17 unmodified lines
49# CONFIG_SERIO is not set50# CONFIG_SERIO is not set
50# CONFIG_LEGACY_PTYS is not set51# CONFIG_LEGACY_PTYS is not set
51# CONFIG_LDISC_AUTOLOAD is not set52# CONFIG_LDISC_AUTOLOAD is not set
52# CONFIG_DEVMEM is not set
53CONFIG_SERIAL_8250=y53CONFIG_SERIAL_8250=y
54# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set54# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
55CONFIG_SERIAL_8250_CONSOLE=y55CONFIG_SERIAL_8250_CONSOLE=y
@@ -57,16 +57,13 @@ CONFIG_SERIAL_8250_NR_UARTS=1 · 1 unmodified line
57CONFIG_SERIAL_8250_RUNTIME_UARTS=157CONFIG_SERIAL_8250_RUNTIME_UARTS=1
58CONFIG_SERIAL_OF_PLATFORM=y58CONFIG_SERIAL_OF_PLATFORM=y
59# CONFIG_HW_RANDOM is not set59# CONFIG_HW_RANDOM is not set
60# CONFIG_DEVMEM is not set
60# CONFIG_HWMON is not set61# CONFIG_HWMON is not set
61# CONFIG_LCD_CLASS_DEVICE is not set
62# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
63# CONFIG_VGA_CONSOLE is not set62# CONFIG_VGA_CONSOLE is not set
64# CONFIG_HID is not set63# CONFIG_HID is not set
65# CONFIG_USB_SUPPORT is not set64# CONFIG_USB_SUPPORT is not set
66CONFIG_VIRTIO_MMIO=y65CONFIG_VIRTIO_MMIO=y
67CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y66CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
68CONFIG_SIFIVE_PLIC=y
69# CONFIG_VALIDATE_FS_PARSER is not set
70CONFIG_EXT2_FS=y67CONFIG_EXT2_FS=y
71# CONFIG_DNOTIFY is not set68# CONFIG_DNOTIFY is not set
72# CONFIG_INOTIFY_USER is not set69# CONFIG_INOTIFY_USER is not set
arch/riscv/configs/rv32_defconfig+5−0
@@ -14,6 +14,7 @@ CONFIG_CHECKPOINT_RESTORE=y · 13 unmodified lines
14CONFIG_BLK_DEV_INITRD=y14CONFIG_BLK_DEV_INITRD=y
15CONFIG_EXPERT=y15CONFIG_EXPERT=y
16CONFIG_BPF_SYSCALL=y16CONFIG_BPF_SYSCALL=y
17CONFIG_SOC_SIFIVE=y
17CONFIG_SOC_VIRT=y18CONFIG_SOC_VIRT=y
18CONFIG_ARCH_RV32I=y19CONFIG_ARCH_RV32I=y
19CONFIG_SMP=y20CONFIG_SMP=y
@@ -62,6 +63,8 @@ CONFIG_HVC_RISCV_SBI=y · 42 unmodified lines
62CONFIG_VIRTIO_CONSOLE=y63CONFIG_VIRTIO_CONSOLE=y
63CONFIG_HW_RANDOM=y64CONFIG_HW_RANDOM=y
64CONFIG_HW_RANDOM_VIRTIO=y65CONFIG_HW_RANDOM_VIRTIO=y
66CONFIG_SPI=y
67CONFIG_SPI_SIFIVE=y
65# CONFIG_PTP_1588_CLOCK is not set68# CONFIG_PTP_1588_CLOCK is not set
66CONFIG_POWER_RESET=y69CONFIG_POWER_RESET=y
67CONFIG_DRM=y70CONFIG_DRM=y
@@ -77,6 +80,8 @@ CONFIG_USB_OHCI_HCD=y · 9 unmodified lines
77CONFIG_USB_OHCI_HCD_PLATFORM=y80CONFIG_USB_OHCI_HCD_PLATFORM=y
78CONFIG_USB_STORAGE=y81CONFIG_USB_STORAGE=y
79CONFIG_USB_UAS=y82CONFIG_USB_UAS=y
83CONFIG_MMC=y
84CONFIG_MMC_SPI=y
80CONFIG_RTC_CLASS=y85CONFIG_RTC_CLASS=y
81CONFIG_VIRTIO_PCI=y86CONFIG_VIRTIO_PCI=y
82CONFIG_VIRTIO_BALLOON=y87CONFIG_VIRTIO_BALLOON=y
arch/riscv/include/asm/clint.h+0−39
@@ -1,39 +0,0 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _ASM_RISCV_CLINT_H
3#define _ASM_RISCV_CLINT_H 1
4
5#include <linux/io.h>
6#include <linux/smp.h>
7
8#ifdef CONFIG_RISCV_M_MODE
9extern u32 __iomem *clint_ipi_base;
10
11void clint_init_boot_cpu(void);
12
13static inline void clint_send_ipi_single(unsigned long hartid)
14{
15 writel(1, clint_ipi_base + hartid);
16}
17
18static inline void clint_send_ipi_mask(const struct cpumask *mask)
19{
20 int cpu;
21
22 for_each_cpu(cpu, mask)
23 clint_send_ipi_single(cpuid_to_hartid_map(cpu));
24}
25
26static inline void clint_clear_ipi(unsigned long hartid)
27{
28 writel(0, clint_ipi_base + hartid);
29}
30#else /* CONFIG_RISCV_M_MODE */
31#define clint_init_boot_cpu() do { } while (0)
32
33/* stubs to for code is only reachable under IS_ENABLED(CONFIG_RISCV_M_MODE): */
34void clint_send_ipi_single(unsigned long hartid);
35void clint_send_ipi_mask(const struct cpumask *hartid_mask);
36void clint_clear_ipi(unsigned long hartid);
37#endif /* CONFIG_RISCV_M_MODE */
38
39#endif /* _ASM_RISCV_CLINT_H */
arch/riscv/include/asm/smp.h+19−0
@@ -15,6 +15,11 @@ · 14 unmodified lines
15struct seq_file;15struct seq_file;
16extern unsigned long boot_cpu_hartid;16extern unsigned long boot_cpu_hartid;
17 17
18struct riscv_ipi_ops {
19 void (*ipi_inject)(const struct cpumask *target);
20 void (*ipi_clear)(void);
21};
22
18#ifdef CONFIG_SMP23#ifdef CONFIG_SMP
19/*24/*
20 * Mapping between linux logical cpu index and hartid.25 * Mapping between linux logical cpu index and hartid.
@@ -40,6 +45,12 @@ void arch_send_call_function_single_ipi(int cpu); · 19 unmodified lines
40int riscv_hartid_to_cpuid(int hartid);45int riscv_hartid_to_cpuid(int hartid);
41void riscv_cpuid_to_hartid_mask(const struct cpumask *in, struct cpumask *out);46void riscv_cpuid_to_hartid_mask(const struct cpumask *in, struct cpumask *out);
42 47
48/* Set custom IPI operations */
49void riscv_set_ipi_ops(struct riscv_ipi_ops *ops);
50
51/* Clear IPI for current CPU */
52void riscv_clear_ipi(void);
53
43/* Secondary hart entry */54/* Secondary hart entry */
44asmlinkage void smp_callin(void);55asmlinkage void smp_callin(void);
45 56
@@ -81,6 +92,14 @@ static inline void riscv_cpuid_to_hartid_mask(const struct cpumask *in, · 35 unmodified lines
81 cpumask_set_cpu(boot_cpu_hartid, out);92 cpumask_set_cpu(boot_cpu_hartid, out);
82}93}
83 94
95static inline void riscv_set_ipi_ops(struct riscv_ipi_ops *ops)
96{
97}
98
99static inline void riscv_clear_ipi(void)
100{
101}
102
84#endif /* CONFIG_SMP */103#endif /* CONFIG_SMP */
85 104
86#if defined(CONFIG_HOTPLUG_CPU) && (CONFIG_SMP)105#if defined(CONFIG_HOTPLUG_CPU) && (CONFIG_SMP)
arch/riscv/include/asm/timex.h+7−21
@@ -7,41 +7,27 @@ · 6 unmodified lines
7#define _ASM_RISCV_TIMEX_H7#define _ASM_RISCV_TIMEX_H
8 8
9#include <asm/csr.h>9#include <asm/csr.h>
10#include <asm/mmio.h>
11 10
12typedef unsigned long cycles_t;11typedef unsigned long cycles_t;
13 12
14extern u64 __iomem *riscv_time_val;
15extern u64 __iomem *riscv_time_cmp;
16
17#ifdef CONFIG_64BIT
18#define mmio_get_cycles() readq_relaxed(riscv_time_val)
19#else
20#define mmio_get_cycles() readl_relaxed(riscv_time_val)
21#define mmio_get_cycles_hi() readl_relaxed(((u32 *)riscv_time_val) + 1)
22#endif
23
24static inline cycles_t get_cycles(void)13static inline cycles_t get_cycles(void)
25{14{
26 if (IS_ENABLED(CONFIG_RISCV_SBI))15 return csr_read(CSR_TIME);
27 return csr_read(CSR_TIME);
28 return mmio_get_cycles();
29}16}
30#define get_cycles get_cycles17#define get_cycles get_cycles
31 18
19static inline u32 get_cycles_hi(void)
20{
21 return csr_read(CSR_TIMEH);
22}
23#define get_cycles_hi get_cycles_hi
24
32#ifdef CONFIG_64BIT25#ifdef CONFIG_64BIT
33static inline u64 get_cycles64(void)26static inline u64 get_cycles64(void)
34{27{
35 return get_cycles();28 return get_cycles();
36}29}
37#else /* CONFIG_64BIT */30#else /* CONFIG_64BIT */
38static inline u32 get_cycles_hi(void)
39{
40 if (IS_ENABLED(CONFIG_RISCV_SBI))
41 return csr_read(CSR_TIMEH);
42 return mmio_get_cycles_hi();
43}
44
45static inline u64 get_cycles64(void)31static inline u64 get_cycles64(void)
46{32{
47 u32 hi, lo;33 u32 hi, lo;
arch/riscv/kernel/Makefile+1−1
@@ -31,7 +31,7 @@ obj-y += cacheinfo.o · 30 unmodified lines
31obj-y += patch.o31obj-y += patch.o
32obj-$(CONFIG_MMU) += vdso.o vdso/32obj-$(CONFIG_MMU) += vdso.o vdso/
33 33
34obj-$(CONFIG_RISCV_M_MODE) += clint.o traps_misaligned.o34obj-$(CONFIG_RISCV_M_MODE) += traps_misaligned.o
35obj-$(CONFIG_FPU) += fpu.o35obj-$(CONFIG_FPU) += fpu.o
36obj-$(CONFIG_SMP) += smpboot.o36obj-$(CONFIG_SMP) += smpboot.o
37obj-$(CONFIG_SMP) += smp.o37obj-$(CONFIG_SMP) += smp.o
arch/riscv/kernel/clint.c+0−44
@@ -1,44 +0,0 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2019 Christoph Hellwig.
4 */
5
6#include <linux/io.h>
7#include <linux/of_address.h>
8#include <linux/types.h>
9#include <asm/clint.h>
10#include <asm/csr.h>
11#include <asm/timex.h>
12#include <asm/smp.h>
13
14/*
15 * This is the layout used by the SiFive clint, which is also shared by the qemu
16 * virt platform, and the Kendryte KD210 at least.
17 */
18#define CLINT_IPI_OFF 0
19#define CLINT_TIME_CMP_OFF 0x4000
20#define CLINT_TIME_VAL_OFF 0xbff8
21
22u32 __iomem *clint_ipi_base;
23
24void clint_init_boot_cpu(void)
25{
26 struct device_node *np;
27 void __iomem *base;
28
29 np = of_find_compatible_node(NULL, NULL, "riscv,clint0");
30 if (!np) {
31 panic("clint not found");
32 return;
33 }
34
35 base = of_iomap(np, 0);
36 if (!base)
37 panic("could not map CLINT");
38
39 clint_ipi_base = base + CLINT_IPI_OFF;
40 riscv_time_cmp = base + CLINT_TIME_CMP_OFF;
41 riscv_time_val = base + CLINT_TIME_VAL_OFF;
42
43 clint_clear_ipi(boot_cpu_hartid);
44}
arch/riscv/kernel/sbi.c+14−0
@@ -547,6 +547,18 @@ static inline long sbi_get_firmware_version(void) · 546 unmodified lines
547 return __sbi_base_ecall(SBI_EXT_BASE_GET_IMP_VERSION);547 return __sbi_base_ecall(SBI_EXT_BASE_GET_IMP_VERSION);
548}548}
549 549
550static void sbi_send_cpumask_ipi(const struct cpumask *target)
551{
552 struct cpumask hartid_mask;
553
554 riscv_cpuid_to_hartid_mask(target, &hartid_mask);
555
556 sbi_send_ipi(cpumask_bits(&hartid_mask));
557}
558
559static struct riscv_ipi_ops sbi_ipi_ops = {
560 .ipi_inject = sbi_send_cpumask_ipi
561};
550 562
551int __init sbi_init(void)563int __init sbi_init(void)
552{564{
@@ -587,5 +599,7 @@ int __init sbi_init(void) · 34 unmodified lines
587 __sbi_rfence = __sbi_rfence_v01;599 __sbi_rfence = __sbi_rfence_v01;
588 }600 }
589 601
602 riscv_set_ipi_ops(&sbi_ipi_ops);
603
590 return 0;604 return 0;
591}605}
arch/riscv/kernel/setup.c+0−2
@@ -18,7 +18,6 @@ · 17 unmodified lines
18#include <linux/swiotlb.h>18#include <linux/swiotlb.h>
19#include <linux/smp.h>19#include <linux/smp.h>
20 20
21#include <asm/clint.h>
22#include <asm/cpu_ops.h>21#include <asm/cpu_ops.h>
23#include <asm/setup.h>22#include <asm/setup.h>
24#include <asm/sections.h>23#include <asm/sections.h>
@@ -79,7 +78,6 @@ void __init setup_arch(char **cmdline_p) · 54 unmodified lines
79#else78#else
80 unflatten_device_tree();79 unflatten_device_tree();
81#endif80#endif
82 clint_init_boot_cpu();
83 81
84#ifdef CONFIG_SWIOTLB82#ifdef CONFIG_SWIOTLB
85 swiotlb_init(1);83 swiotlb_init(1);
arch/riscv/kernel/signal.c+1−1
@@ -250,7 +250,7 @@ static void handle_signal(struct ksignal *ksig, struct pt_regs *regs) · 249 unmodified lines
250 regs->a0 = -EINTR;250 regs->a0 = -EINTR;
251 break;251 break;
252 }252 }
253 /* fallthrough */253 fallthrough;
254 case -ERESTARTNOINTR:254 case -ERESTARTNOINTR:
255 regs->a0 = regs->orig_a0;255 regs->a0 = regs->orig_a0;
256 regs->epc -= 0x4;256 regs->epc -= 0x4;
arch/riscv/kernel/smp.c+24−20
@@ -18,7 +18,6 @@ · 17 unmodified lines
18#include <linux/delay.h>18#include <linux/delay.h>
19#include <linux/irq_work.h>19#include <linux/irq_work.h>
20 20
21#include <asm/clint.h>
22#include <asm/sbi.h>21#include <asm/sbi.h>
23#include <asm/tlbflush.h>22#include <asm/tlbflush.h>
24#include <asm/cacheflush.h>23#include <asm/cacheflush.h>
@@ -86,9 +85,25 @@ static void ipi_stop(void) · 61 unmodified lines
86 wait_for_interrupt();85 wait_for_interrupt();
87}86}
88 87
88static struct riscv_ipi_ops *ipi_ops;
89
90void riscv_set_ipi_ops(struct riscv_ipi_ops *ops)
91{
92 ipi_ops = ops;
93}
94EXPORT_SYMBOL_GPL(riscv_set_ipi_ops);
95
96void riscv_clear_ipi(void)
97{
98 if (ipi_ops && ipi_ops->ipi_clear)
99 ipi_ops->ipi_clear();
100
101 csr_clear(CSR_IP, IE_SIE);
102}
103EXPORT_SYMBOL_GPL(riscv_clear_ipi);
104
89static void send_ipi_mask(const struct cpumask *mask, enum ipi_message_type op)105static void send_ipi_mask(const struct cpumask *mask, enum ipi_message_type op)
90{106{
91 struct cpumask hartid_mask;
92 int cpu;107 int cpu;
93 108
94 smp_mb__before_atomic();109 smp_mb__before_atomic();
@@ -96,33 +111,22 @@ static void send_ipi_mask(const struct cpumask *mask, enum ipi_message_type op) · 1 unmodified line
96 set_bit(op, &ipi_data[cpu].bits);111 set_bit(op, &ipi_data[cpu].bits);
97 smp_mb__after_atomic();112 smp_mb__after_atomic();
98 113
99 riscv_cpuid_to_hartid_mask(mask, &hartid_mask);114 if (ipi_ops && ipi_ops->ipi_inject)
100 if (IS_ENABLED(CONFIG_RISCV_SBI))115 ipi_ops->ipi_inject(mask);
101 sbi_send_ipi(cpumask_bits(&hartid_mask));
102 else116 else
103 clint_send_ipi_mask(mask);117 pr_warn("SMP: IPI inject method not available\n");
104}118}
105 119
106static void send_ipi_single(int cpu, enum ipi_message_type op)120static void send_ipi_single(int cpu, enum ipi_message_type op)
107{121{
108 int hartid = cpuid_to_hartid_map(cpu);
109
110 smp_mb__before_atomic();122 smp_mb__before_atomic();
111 set_bit(op, &ipi_data[cpu].bits);123 set_bit(op, &ipi_data[cpu].bits);
112 smp_mb__after_atomic();124 smp_mb__after_atomic();
113 125
114 if (IS_ENABLED(CONFIG_RISCV_SBI))126 if (ipi_ops && ipi_ops->ipi_inject)
115 sbi_send_ipi(cpumask_bits(cpumask_of(hartid)));127 ipi_ops->ipi_inject(cpumask_of(cpu));
116 else
117 clint_send_ipi_single(hartid);
118}
119
120static inline void clear_ipi(void)
121{
122 if (IS_ENABLED(CONFIG_RISCV_SBI))
123 csr_clear(CSR_IP, IE_SIE);
124 else128 else
125 clint_clear_ipi(cpuid_to_hartid_map(smp_processor_id()));129 pr_warn("SMP: IPI inject method not available\n");
126}130}
127 131
128#ifdef CONFIG_IRQ_WORK132#ifdef CONFIG_IRQ_WORK
@@ -140,7 +144,7 @@ void handle_IPI(struct pt_regs *regs) · 11 unmodified lines
140 144
141 irq_enter();145 irq_enter();
142 146
143 clear_ipi();147 riscv_clear_ipi();
144 148
145 while (true) {149 while (true) {
146 unsigned long ops;150 unsigned long ops;
arch/riscv/kernel/smpboot.c+1−3
@@ -24,7 +24,6 @@ · 23 unmodified lines
24#include <linux/of.h>24#include <linux/of.h>
25#include <linux/sched/task_stack.h>25#include <linux/sched/task_stack.h>
26#include <linux/sched/mm.h>26#include <linux/sched/mm.h>
27#include <asm/clint.h>
28#include <asm/cpu_ops.h>27#include <asm/cpu_ops.h>
29#include <asm/irq.h>28#include <asm/irq.h>
30#include <asm/mmu_context.h>29#include <asm/mmu_context.h>
@@ -147,8 +146,7 @@ asmlinkage __visible void smp_callin(void) · 116 unmodified lines
147 struct mm_struct *mm = &init_mm;146 struct mm_struct *mm = &init_mm;
148 unsigned int curr_cpuid = smp_processor_id();147 unsigned int curr_cpuid = smp_processor_id();
149 148
150 if (!IS_ENABLED(CONFIG_RISCV_SBI))149 riscv_clear_ipi();
151 clint_clear_ipi(cpuid_to_hartid_map(smp_processor_id()));
152 150
153 /* All kernel threads share the same mm context. */151 /* All kernel threads share the same mm context. */
154 mmgrab(mm);152 mmgrab(mm);
arch/riscv/net/bpf_jit_comp32.c+2−2
@@ -1020,7 +1020,7 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx, · 1019 unmodified lines
1020 emit_zext64(dst, ctx);1020 emit_zext64(dst, ctx);
1021 break;1021 break;
1022 }1022 }
1023 /* Fallthrough. */1023 fallthrough;
1024 1024
1025 case BPF_ALU | BPF_ADD | BPF_X:1025 case BPF_ALU | BPF_ADD | BPF_X:
1026 case BPF_ALU | BPF_SUB | BPF_X:1026 case BPF_ALU | BPF_SUB | BPF_X:
@@ -1079,7 +1079,7 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx, · 52 unmodified lines
1079 case 16:1079 case 16:
1080 emit(rv_slli(lo(rd), lo(rd), 16), ctx);1080 emit(rv_slli(lo(rd), lo(rd), 16), ctx);
1081 emit(rv_srli(lo(rd), lo(rd), 16), ctx);1081 emit(rv_srli(lo(rd), lo(rd), 16), ctx);
1082 /* Fallthrough. */1082 fallthrough;
1083 case 32:1083 case 32:
1084 if (!ctx->prog->aux->verifier_zext)1084 if (!ctx->prog->aux->verifier_zext)
1085 emit(rv_addi(hi(rd), RV_REG_ZERO, 0), ctx);1085 emit(rv_addi(hi(rd), RV_REG_ZERO, 0), ctx);
arch/s390/Kconfig+1−1
@@ -30,7 +30,7 @@ config GENERIC_BUG_RELATIVE_POINTERS · 29 unmodified lines
30 def_bool y30 def_bool y
31 31
32config GENERIC_LOCKBREAK32config GENERIC_LOCKBREAK
33 def_bool y if PREEMPTTION33 def_bool y if PREEMPTION
34 34
35config PGSTE35config PGSTE
36 def_bool y if KVM36 def_bool y if KVM
arch/s390/configs/debug_defconfig+4−0
@@ -626,6 +626,7 @@ CONFIG_NTFS_RW=y · 625 unmodified lines
626CONFIG_PROC_KCORE=y626CONFIG_PROC_KCORE=y
627CONFIG_TMPFS=y627CONFIG_TMPFS=y
628CONFIG_TMPFS_POSIX_ACL=y628CONFIG_TMPFS_POSIX_ACL=y
629CONFIG_TMPFS_INODE64=y
629CONFIG_HUGETLBFS=y630CONFIG_HUGETLBFS=y
630CONFIG_CONFIGFS_FS=m631CONFIG_CONFIGFS_FS=m
631CONFIG_ECRYPT_FS=m632CONFIG_ECRYPT_FS=m
@@ -807,6 +808,7 @@ CONFIG_DEBUG_NOTIFIERS=y · 175 unmodified lines
807CONFIG_BUG_ON_DATA_CORRUPTION=y808CONFIG_BUG_ON_DATA_CORRUPTION=y
808CONFIG_DEBUG_CREDENTIALS=y809CONFIG_DEBUG_CREDENTIALS=y
809CONFIG_RCU_TORTURE_TEST=m810CONFIG_RCU_TORTURE_TEST=m
811CONFIG_RCU_REF_SCALE_TEST=m
810CONFIG_RCU_CPU_STALL_TIMEOUT=300812CONFIG_RCU_CPU_STALL_TIMEOUT=300
811# CONFIG_RCU_TRACE is not set813# CONFIG_RCU_TRACE is not set
812CONFIG_LATENCYTOP=y814CONFIG_LATENCYTOP=y
@@ -818,6 +820,7 @@ CONFIG_PREEMPT_TRACER=y · 5 unmodified lines
818CONFIG_SCHED_TRACER=y820CONFIG_SCHED_TRACER=y
819CONFIG_FTRACE_SYSCALLS=y821CONFIG_FTRACE_SYSCALLS=y
820CONFIG_BLK_DEV_IO_TRACE=y822CONFIG_BLK_DEV_IO_TRACE=y
823CONFIG_BPF_KPROBE_OVERRIDE=y
821CONFIG_HIST_TRIGGERS=y824CONFIG_HIST_TRIGGERS=y
822CONFIG_S390_PTDUMP=y825CONFIG_S390_PTDUMP=y
823CONFIG_NOTIFIER_ERROR_INJECTION=m826CONFIG_NOTIFIER_ERROR_INJECTION=m
@@ -829,6 +832,7 @@ CONFIG_FAIL_MAKE_REQUEST=y · 5 unmodified lines
829CONFIG_FAIL_IO_TIMEOUT=y832CONFIG_FAIL_IO_TIMEOUT=y
830CONFIG_FAIL_FUTEX=y833CONFIG_FAIL_FUTEX=y
831CONFIG_FAULT_INJECTION_DEBUG_FS=y834CONFIG_FAULT_INJECTION_DEBUG_FS=y
835CONFIG_FAIL_FUNCTION=y
832CONFIG_FAULT_INJECTION_STACKTRACE_FILTER=y836CONFIG_FAULT_INJECTION_STACKTRACE_FILTER=y
833CONFIG_LKDTM=m837CONFIG_LKDTM=m
834CONFIG_TEST_LIST_SORT=y838CONFIG_TEST_LIST_SORT=y
arch/s390/configs/defconfig+3−0
@@ -617,6 +617,7 @@ CONFIG_NTFS_RW=y · 616 unmodified lines
617CONFIG_PROC_KCORE=y617CONFIG_PROC_KCORE=y
618CONFIG_TMPFS=y618CONFIG_TMPFS=y
619CONFIG_TMPFS_POSIX_ACL=y619CONFIG_TMPFS_POSIX_ACL=y
620CONFIG_TMPFS_INODE64=y
620CONFIG_HUGETLBFS=y621CONFIG_HUGETLBFS=y
621CONFIG_CONFIGFS_FS=m622CONFIG_CONFIGFS_FS=m
622CONFIG_ECRYPT_FS=m623CONFIG_ECRYPT_FS=m
@@ -763,6 +764,7 @@ CONFIG_PANIC_ON_OOPS=y · 140 unmodified lines
763CONFIG_TEST_LOCKUP=m764CONFIG_TEST_LOCKUP=m
764CONFIG_BUG_ON_DATA_CORRUPTION=y765CONFIG_BUG_ON_DATA_CORRUPTION=y
765CONFIG_RCU_TORTURE_TEST=m766CONFIG_RCU_TORTURE_TEST=m
767CONFIG_RCU_REF_SCALE_TEST=m
766CONFIG_RCU_CPU_STALL_TIMEOUT=60768CONFIG_RCU_CPU_STALL_TIMEOUT=60
767CONFIG_LATENCYTOP=y769CONFIG_LATENCYTOP=y
768CONFIG_BOOTTIME_TRACING=y770CONFIG_BOOTTIME_TRACING=y
@@ -771,6 +773,7 @@ CONFIG_STACK_TRACER=y · 2 unmodified lines
771CONFIG_SCHED_TRACER=y773CONFIG_SCHED_TRACER=y
772CONFIG_FTRACE_SYSCALLS=y774CONFIG_FTRACE_SYSCALLS=y
773CONFIG_BLK_DEV_IO_TRACE=y775CONFIG_BLK_DEV_IO_TRACE=y
776CONFIG_BPF_KPROBE_OVERRIDE=y
774CONFIG_HIST_TRIGGERS=y777CONFIG_HIST_TRIGGERS=y
775CONFIG_S390_PTDUMP=y778CONFIG_S390_PTDUMP=y
776CONFIG_LKDTM=m779CONFIG_LKDTM=m
arch/s390/configs/zfcpdump_defconfig+1−0
@@ -74,5 +74,6 @@ CONFIG_DEBUG_KERNEL=y · 73 unmodified lines
74CONFIG_PANIC_ON_OOPS=y74CONFIG_PANIC_ON_OOPS=y
75# CONFIG_SCHED_DEBUG is not set75# CONFIG_SCHED_DEBUG is not set
76CONFIG_RCU_CPU_STALL_TIMEOUT=6076CONFIG_RCU_CPU_STALL_TIMEOUT=60
77# CONFIG_RCU_TRACE is not set
77# CONFIG_FTRACE is not set78# CONFIG_FTRACE is not set
78# CONFIG_RUNTIME_TESTING_MENU is not set79# CONFIG_RUNTIME_TESTING_MENU is not set
arch/s390/include/asm/percpu.h+14−14
@@ -29,7 +29,7 @@ · 28 unmodified lines
29 typedef typeof(pcp) pcp_op_T__; \29 typedef typeof(pcp) pcp_op_T__; \
30 pcp_op_T__ old__, new__, prev__; \30 pcp_op_T__ old__, new__, prev__; \
31 pcp_op_T__ *ptr__; \31 pcp_op_T__ *ptr__; \
32 preempt_disable(); \32 preempt_disable_notrace(); \
33 ptr__ = raw_cpu_ptr(&(pcp)); \33 ptr__ = raw_cpu_ptr(&(pcp)); \
34 prev__ = *ptr__; \34 prev__ = *ptr__; \
35 do { \35 do { \
@@ -37,7 +37,7 @@ · 1 unmodified line
37 new__ = old__ op (val); \37 new__ = old__ op (val); \
38 prev__ = cmpxchg(ptr__, old__, new__); \38 prev__ = cmpxchg(ptr__, old__, new__); \
39 } while (prev__ != old__); \39 } while (prev__ != old__); \
40 preempt_enable(); \40 preempt_enable_notrace(); \
41 new__; \41 new__; \
42})42})
43 43
@@ -68,7 +68,7 @@ · 24 unmodified lines
68 typedef typeof(pcp) pcp_op_T__; \68 typedef typeof(pcp) pcp_op_T__; \
69 pcp_op_T__ val__ = (val); \69 pcp_op_T__ val__ = (val); \
70 pcp_op_T__ old__, *ptr__; \70 pcp_op_T__ old__, *ptr__; \
71 preempt_disable(); \71 preempt_disable_notrace(); \
72 ptr__ = raw_cpu_ptr(&(pcp)); \72 ptr__ = raw_cpu_ptr(&(pcp)); \
73 if (__builtin_constant_p(val__) && \73 if (__builtin_constant_p(val__) && \
74 ((szcast)val__ > -129) && ((szcast)val__ < 128)) { \74 ((szcast)val__ > -129) && ((szcast)val__ < 128)) { \
@@ -84,7 +84,7 @@ · 9 unmodified lines
84 : [val__] "d" (val__) \84 : [val__] "d" (val__) \
85 : "cc"); \85 : "cc"); \
86 } \86 } \
87 preempt_enable(); \87 preempt_enable_notrace(); \
88}88}
89 89
90#define this_cpu_add_4(pcp, val) arch_this_cpu_add(pcp, val, "laa", "asi", int)90#define this_cpu_add_4(pcp, val) arch_this_cpu_add(pcp, val, "laa", "asi", int)
@@ -95,14 +95,14 @@ · 4 unmodified lines
95 typedef typeof(pcp) pcp_op_T__; \95 typedef typeof(pcp) pcp_op_T__; \
96 pcp_op_T__ val__ = (val); \96 pcp_op_T__ val__ = (val); \
97 pcp_op_T__ old__, *ptr__; \97 pcp_op_T__ old__, *ptr__; \
98 preempt_disable(); \98 preempt_disable_notrace(); \
99 ptr__ = raw_cpu_ptr(&(pcp)); \99 ptr__ = raw_cpu_ptr(&(pcp)); \
100 asm volatile( \100 asm volatile( \
101 op " %[old__],%[val__],%[ptr__]\n" \101 op " %[old__],%[val__],%[ptr__]\n" \
102 : [old__] "=d" (old__), [ptr__] "+Q" (*ptr__) \102 : [old__] "=d" (old__), [ptr__] "+Q" (*ptr__) \
103 : [val__] "d" (val__) \103 : [val__] "d" (val__) \
104 : "cc"); \104 : "cc"); \
105 preempt_enable(); \105 preempt_enable_notrace(); \
106 old__ + val__; \106 old__ + val__; \
107})107})
108 108
@@ -114,14 +114,14 @@ · 5 unmodified lines
114 typedef typeof(pcp) pcp_op_T__; \114 typedef typeof(pcp) pcp_op_T__; \
115 pcp_op_T__ val__ = (val); \115 pcp_op_T__ val__ = (val); \
116 pcp_op_T__ old__, *ptr__; \116 pcp_op_T__ old__, *ptr__; \
117 preempt_disable(); \117 preempt_disable_notrace(); \
118 ptr__ = raw_cpu_ptr(&(pcp)); \118 ptr__ = raw_cpu_ptr(&(pcp)); \
119 asm volatile( \119 asm volatile( \
120 op " %[old__],%[val__],%[ptr__]\n" \120 op " %[old__],%[val__],%[ptr__]\n" \
121 : [old__] "=d" (old__), [ptr__] "+Q" (*ptr__) \121 : [old__] "=d" (old__), [ptr__] "+Q" (*ptr__) \
122 : [val__] "d" (val__) \122 : [val__] "d" (val__) \
123 : "cc"); \123 : "cc"); \
124 preempt_enable(); \124 preempt_enable_notrace(); \
125}125}
126 126
127#define this_cpu_and_4(pcp, val) arch_this_cpu_to_op(pcp, val, "lan")127#define this_cpu_and_4(pcp, val) arch_this_cpu_to_op(pcp, val, "lan")
@@ -136,10 +136,10 @@ · 8 unmodified lines
136 typedef typeof(pcp) pcp_op_T__; \136 typedef typeof(pcp) pcp_op_T__; \
137 pcp_op_T__ ret__; \137 pcp_op_T__ ret__; \
138 pcp_op_T__ *ptr__; \138 pcp_op_T__ *ptr__; \
139 preempt_disable(); \139 preempt_disable_notrace(); \
140 ptr__ = raw_cpu_ptr(&(pcp)); \140 ptr__ = raw_cpu_ptr(&(pcp)); \
141 ret__ = cmpxchg(ptr__, oval, nval); \141 ret__ = cmpxchg(ptr__, oval, nval); \
142 preempt_enable(); \142 preempt_enable_notrace(); \
143 ret__; \143 ret__; \
144})144})
145 145
@@ -152,10 +152,10 @@ · 6 unmodified lines
152({ \152({ \
153 typeof(pcp) *ptr__; \153 typeof(pcp) *ptr__; \
154 typeof(pcp) ret__; \154 typeof(pcp) ret__; \
155 preempt_disable(); \155 preempt_disable_notrace(); \
156 ptr__ = raw_cpu_ptr(&(pcp)); \156 ptr__ = raw_cpu_ptr(&(pcp)); \
157 ret__ = xchg(ptr__, nval); \157 ret__ = xchg(ptr__, nval); \
158 preempt_enable(); \158 preempt_enable_notrace(); \
159 ret__; \159 ret__; \
160})160})
161 161
@@ -171,11 +171,11 @@ · 9 unmodified lines
171 typeof(pcp1) *p1__; \171 typeof(pcp1) *p1__; \
172 typeof(pcp2) *p2__; \172 typeof(pcp2) *p2__; \
173 int ret__; \173 int ret__; \
174 preempt_disable(); \174 preempt_disable_notrace(); \
175 p1__ = raw_cpu_ptr(&(pcp1)); \175 p1__ = raw_cpu_ptr(&(pcp1)); \
176 p2__ = raw_cpu_ptr(&(pcp2)); \176 p2__ = raw_cpu_ptr(&(pcp2)); \
177 ret__ = __cmpxchg_double(p1__, p2__, o1__, o2__, n1__, n2__); \177 ret__ = __cmpxchg_double(p1__, p2__, o1__, o2__, n1__, n2__); \
178 preempt_enable(); \178 preempt_enable_notrace(); \
179 ret__; \179 ret__; \
180})180})
181 181
arch/s390/kernel/idle.c+1−2
@@ -33,14 +33,13 @@ void enabled_wait(void) · 32 unmodified lines
33 PSW_MASK_IO | PSW_MASK_EXT | PSW_MASK_MCHECK;33 PSW_MASK_IO | PSW_MASK_EXT | PSW_MASK_MCHECK;
34 clear_cpu_flag(CIF_NOHZ_DELAY);34 clear_cpu_flag(CIF_NOHZ_DELAY);
35 35
36 trace_cpu_idle_rcuidle(1, smp_processor_id());
37 local_irq_save(flags);36 local_irq_save(flags);
38 /* Call the assembler magic in entry.S */37 /* Call the assembler magic in entry.S */
39 psw_idle(idle, psw_mask);38 psw_idle(idle, psw_mask);
40 local_irq_restore(flags);39 local_irq_restore(flags);
41 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
42 40
43 /* Account time spent with enabled wait psw loaded as idle time. */41 /* Account time spent with enabled wait psw loaded as idle time. */
42 /* XXX seqcount has tracepoints that require RCU */
44 write_seqcount_begin(&idle->seqcount);43 write_seqcount_begin(&idle->seqcount);
45 idle_time = idle->clock_idle_exit - idle->clock_idle_enter;44 idle_time = idle->clock_idle_exit - idle->clock_idle_enter;
46 idle->clock_idle_enter = idle->clock_idle_exit = 0ULL;45 idle->clock_idle_enter = idle->clock_idle_exit = 0ULL;
arch/s390/kernel/ptrace.c+5−2
@@ -1268,7 +1268,6 @@ static bool is_ri_cb_valid(struct runtime_instr_cb *cb) · 1267 unmodified lines
1268 cb->pc == 1 &&1268 cb->pc == 1 &&
1269 cb->qc == 0 &&1269 cb->qc == 0 &&
1270 cb->reserved2 == 0 &&1270 cb->reserved2 == 0 &&
1271 cb->key == PAGE_DEFAULT_KEY &&
1272 cb->reserved3 == 0 &&1271 cb->reserved3 == 0 &&
1273 cb->reserved4 == 0 &&1272 cb->reserved4 == 0 &&
1274 cb->reserved5 == 0 &&1273 cb->reserved5 == 0 &&
@@ -1330,7 +1329,11 @@ static int s390_runtime_instr_set(struct task_struct *target, · 55 unmodified lines
1330 kfree(data);1329 kfree(data);
1331 return -EINVAL;1330 return -EINVAL;
1332 }1331 }
1333 1332 /*
1333 * Override access key in any case, since user space should
1334 * not be able to set it, nor should it care about it.
1335 */
1336 ri_cb.key = PAGE_DEFAULT_KEY >> 4;
1334 preempt_disable();1337 preempt_disable();
1335 if (!target->thread.ri_cb)1338 if (!target->thread.ri_cb)
1336 target->thread.ri_cb = data;1339 target->thread.ri_cb = data;
arch/s390/kernel/runtime_instr.c+1−1
@@ -57,7 +57,7 @@ static void init_runtime_instr_cb(struct runtime_instr_cb *cb) · 56 unmodified lines
57 cb->k = 1;57 cb->k = 1;
58 cb->ps = 1;58 cb->ps = 1;
59 cb->pc = 1;59 cb->pc = 1;
60 cb->key = PAGE_DEFAULT_KEY;60 cb->key = PAGE_DEFAULT_KEY >> 4;
61 cb->v = 1;61 cb->v = 1;
62}62}
63 63
arch/s390/mm/vmem.c+1−0
@@ -402,6 +402,7 @@ static int modify_p4d_table(pgd_t *pgd, unsigned long addr, unsigned long end, · 401 unmodified lines
402 pud = vmem_crst_alloc(_REGION3_ENTRY_EMPTY);402 pud = vmem_crst_alloc(_REGION3_ENTRY_EMPTY);
403 if (!pud)403 if (!pud)
404 goto out;404 goto out;
405 p4d_populate(&init_mm, p4d, pud);
405 }406 }
406 ret = modify_pud_table(p4d, addr, next, add, direct);407 ret = modify_pud_table(p4d, addr, next, add, direct);
407 if (ret)408 if (ret)
arch/s390/pci/pci.c+15−7
@@ -672,6 +672,19 @@ int zpci_disable_device(struct zpci_dev *zdev) · 671 unmodified lines
672}672}
673EXPORT_SYMBOL_GPL(zpci_disable_device);673EXPORT_SYMBOL_GPL(zpci_disable_device);
674 674
675void zpci_remove_device(struct zpci_dev *zdev)
676{
677 struct zpci_bus *zbus = zdev->zbus;
678 struct pci_dev *pdev;
679
680 pdev = pci_get_slot(zbus->bus, zdev->devfn);
681 if (pdev) {
682 if (pdev->is_virtfn)
683 return zpci_remove_virtfn(pdev, zdev->vfn);
684 pci_stop_and_remove_bus_device_locked(pdev);
685 }
686}
687
675int zpci_create_device(struct zpci_dev *zdev)688int zpci_create_device(struct zpci_dev *zdev)
676{689{
677 int rc;690 int rc;
@@ -716,13 +729,8 @@ void zpci_release_device(struct kref *kref) · 38 unmodified lines
716{729{
717 struct zpci_dev *zdev = container_of(kref, struct zpci_dev, kref);730 struct zpci_dev *zdev = container_of(kref, struct zpci_dev, kref);
718 731
719 if (zdev->zbus->bus) {732 if (zdev->zbus->bus)
720 struct pci_dev *pdev;733 zpci_remove_device(zdev);
721
722 pdev = pci_get_slot(zdev->zbus->bus, zdev->devfn);
723 if (pdev)
724 pci_stop_and_remove_bus_device_locked(pdev);
725 }
726 734
727 switch (zdev->state) {735 switch (zdev->state) {
728 case ZPCI_FN_STATE_ONLINE:736 case ZPCI_FN_STATE_ONLINE:
arch/s390/pci/pci_bus.c+30−22
@@ -132,13 +132,14 @@ static int zpci_bus_link_virtfn(struct pci_dev *pdev, · 131 unmodified lines
132{132{
133 int rc;133 int rc;
134 134
135 virtfn->physfn = pci_dev_get(pdev);
136 rc = pci_iov_sysfs_link(pdev, virtfn, vfid);135 rc = pci_iov_sysfs_link(pdev, virtfn, vfid);
137 if (rc) {136 if (rc)
138 pci_dev_put(pdev);
139 virtfn->physfn = NULL;
140 return rc;137 return rc;
141 }138
139 virtfn->is_virtfn = 1;
140 virtfn->multifunction = 0;
141 virtfn->physfn = pci_dev_get(pdev);
142
142 return 0;143 return 0;
143}144}
144 145
@@ -151,9 +152,9 @@ static int zpci_bus_setup_virtfn(struct zpci_bus *zbus, · 6 unmodified lines
151 int vfid = vfn - 1; /* Linux' vfid's start at 0 vfn at 1*/152 int vfid = vfn - 1; /* Linux' vfid's start at 0 vfn at 1*/
152 int rc = 0;153 int rc = 0;
153 154
154 virtfn->is_virtfn = 1;155 if (!zbus->multifunction)
155 virtfn->multifunction = 0;156 return 0;
156 WARN_ON(vfid < 0);157
157 /* If the parent PF for the given VF is also configured in the158 /* If the parent PF for the given VF is also configured in the
158 * instance, it must be on the same zbus.159 * instance, it must be on the same zbus.
159 * We can then identify the parent PF by checking what160 * We can then identify the parent PF by checking what
@@ -165,11 +166,17 @@ static int zpci_bus_setup_virtfn(struct zpci_bus *zbus, · 5 unmodified lines
165 zdev = zbus->function[i];166 zdev = zbus->function[i];
166 if (zdev && zdev->is_physfn) {167 if (zdev && zdev->is_physfn) {
167 pdev = pci_get_slot(zbus->bus, zdev->devfn);168 pdev = pci_get_slot(zbus->bus, zdev->devfn);
169 if (!pdev)
170 continue;
168 cand_devfn = pci_iov_virtfn_devfn(pdev, vfid);171 cand_devfn = pci_iov_virtfn_devfn(pdev, vfid);
169 if (cand_devfn == virtfn->devfn) {172 if (cand_devfn == virtfn->devfn) {
170 rc = zpci_bus_link_virtfn(pdev, virtfn, vfid);173 rc = zpci_bus_link_virtfn(pdev, virtfn, vfid);
174 /* balance pci_get_slot() */
175 pci_dev_put(pdev);
171 break;176 break;
172 }177 }
178 /* balance pci_get_slot() */
179 pci_dev_put(pdev);
173 }180 }
174 }181 }
175 return rc;182 return rc;
@@ -178,12 +185,23 @@ static int zpci_bus_setup_virtfn(struct zpci_bus *zbus, · 2 unmodified lines
178static inline int zpci_bus_setup_virtfn(struct zpci_bus *zbus,185static inline int zpci_bus_setup_virtfn(struct zpci_bus *zbus,
179 struct pci_dev *virtfn, int vfn)186 struct pci_dev *virtfn, int vfn)
180{187{
181 virtfn->is_virtfn = 1;
182 virtfn->multifunction = 0;
183 return 0;188 return 0;
184}189}
185#endif190#endif
186 191
192void pcibios_bus_add_device(struct pci_dev *pdev)
193{
194 struct zpci_dev *zdev = to_zpci(pdev);
195
196 /*
197 * With pdev->no_vf_scan the common PCI probing code does not
198 * perform PF/VF linking.
199 */
200 if (zdev->vfn)
201 zpci_bus_setup_virtfn(zdev->zbus, pdev, zdev->vfn);
202
203}
204
187static int zpci_bus_add_device(struct zpci_bus *zbus, struct zpci_dev *zdev)205static int zpci_bus_add_device(struct zpci_bus *zbus, struct zpci_dev *zdev)
188{206{
189 struct pci_bus *bus;207 struct pci_bus *bus;
@@ -214,20 +232,10 @@ static int zpci_bus_add_device(struct zpci_bus *zbus, struct zpci_dev *zdev) · 24 unmodified lines
214 }232 }
215 233
216 pdev = pci_scan_single_device(bus, zdev->devfn);234 pdev = pci_scan_single_device(bus, zdev->devfn);
217 if (pdev) {235 if (pdev)
218 if (!zdev->is_physfn) {
219 rc = zpci_bus_setup_virtfn(zbus, pdev, zdev->vfn);
220 if (rc)
221 goto failed_with_pdev;
222 }
223 pci_bus_add_device(pdev);236 pci_bus_add_device(pdev);
224 }
225 return 0;
226 237
227failed_with_pdev:238 return 0;
228 pci_stop_and_remove_bus_device(pdev);
229 pci_dev_put(pdev);
230 return rc;
231}239}
232 240
233static void zpci_bus_add_devices(struct zpci_bus *zbus)241static void zpci_bus_add_devices(struct zpci_bus *zbus)
arch/s390/pci/pci_bus.h+13−0
@@ -29,3 +29,16 @@ static inline struct zpci_dev *get_zdev_by_bus(struct pci_bus *bus, · 28 unmodified lines
29 29
30 return (devfn >= ZPCI_FUNCTIONS_PER_BUS) ? NULL : zbus->function[devfn];30 return (devfn >= ZPCI_FUNCTIONS_PER_BUS) ? NULL : zbus->function[devfn];
31}31}
32
33#ifdef CONFIG_PCI_IOV
34static inline void zpci_remove_virtfn(struct pci_dev *pdev, int vfn)
35{
36
37 pci_lock_rescan_remove();
38 /* Linux' vfid's start at 0 vfn at 1 */
39 pci_iov_remove_virtfn(pdev->physfn, vfn - 1);
40 pci_unlock_rescan_remove();
41}
42#else /* CONFIG_PCI_IOV */
43static inline void zpci_remove_virtfn(struct pci_dev *pdev, int vfn) {}
44#endif /* CONFIG_PCI_IOV */
arch/s390/pci/pci_event.c+5−2
@@ -92,6 +92,9 @@ static void __zpci_event_availability(struct zpci_ccdf_avail *ccdf) · 91 unmodified lines
92 ret = clp_add_pci_device(ccdf->fid, ccdf->fh, 1);92 ret = clp_add_pci_device(ccdf->fid, ccdf->fh, 1);
93 break;93 break;
94 }94 }
95 /* the configuration request may be stale */
96 if (zdev->state != ZPCI_FN_STATE_STANDBY)
97 break;
95 zdev->fh = ccdf->fh;98 zdev->fh = ccdf->fh;
96 zdev->state = ZPCI_FN_STATE_CONFIGURED;99 zdev->state = ZPCI_FN_STATE_CONFIGURED;
97 ret = zpci_enable_device(zdev);100 ret = zpci_enable_device(zdev);
@@ -118,7 +121,7 @@ static void __zpci_event_availability(struct zpci_ccdf_avail *ccdf) · 20 unmodified lines
118 if (!zdev)121 if (!zdev)
119 break;122 break;
120 if (pdev)123 if (pdev)
121 pci_stop_and_remove_bus_device_locked(pdev);124 zpci_remove_device(zdev);
122 125
123 ret = zpci_disable_device(zdev);126 ret = zpci_disable_device(zdev);
124 if (ret)127 if (ret)
@@ -137,7 +140,7 @@ static void __zpci_event_availability(struct zpci_ccdf_avail *ccdf) · 12 unmodified lines
137 /* Give the driver a hint that the function is140 /* Give the driver a hint that the function is
138 * already unusable. */141 * already unusable. */
139 pdev->error_state = pci_channel_io_perm_failure;142 pdev->error_state = pci_channel_io_perm_failure;
140 pci_stop_and_remove_bus_device_locked(pdev);143 zpci_remove_device(zdev);
141 }144 }
142 145
143 zdev->state = ZPCI_FN_STATE_STANDBY;146 zdev->state = ZPCI_FN_STATE_STANDBY;
arch/sh/drivers/platform_early.c+1−1
@@ -246,7 +246,7 @@ static int __init sh_early_platform_driver_probe_id(char *class_str, · 245 unmodified lines
246 case EARLY_PLATFORM_ID_ERROR:246 case EARLY_PLATFORM_ID_ERROR:
247 pr_warn("%s: unable to parse %s parameter\n",247 pr_warn("%s: unable to parse %s parameter\n",
248 class_str, epdrv->pdrv->driver.name);248 class_str, epdrv->pdrv->driver.name);
249 /* fall-through */249 fallthrough;
250 case EARLY_PLATFORM_ID_UNSET:250 case EARLY_PLATFORM_ID_UNSET:
251 match = NULL;251 match = NULL;
252 break;252 break;
arch/sh/kernel/disassemble.c+2−2
@@ -486,7 +486,7 @@ static void print_sh_insn(u32 memaddr, u16 insn) · 485 unmodified lines
486 pr_cont("xd%d", rn & ~1);486 pr_cont("xd%d", rn & ~1);
487 break;487 break;
488 }488 }
489 /* else, fall through */489 fallthrough;
490 case D_REG_N:490 case D_REG_N:
491 pr_cont("dr%d", rn);491 pr_cont("dr%d", rn);
492 break;492 break;
@@ -495,7 +495,7 @@ static void print_sh_insn(u32 memaddr, u16 insn) · 2 unmodified lines
495 pr_cont("xd%d", rm & ~1);495 pr_cont("xd%d", rm & ~1);
496 break;496 break;
497 }497 }
498 /* else, fall through */498 fallthrough;
499 case D_REG_M:499 case D_REG_M:
500 pr_cont("dr%d", rm);500 pr_cont("dr%d", rm);
501 break;501 break;
arch/sh/kernel/kgdb.c+1−1
@@ -266,7 +266,7 @@ int kgdb_arch_handle_exception(int e_vector, int signo, int err_code, · 265 unmodified lines
266 ptr = &remcomInBuffer[1];266 ptr = &remcomInBuffer[1];
267 if (kgdb_hex2long(&ptr, &addr))267 if (kgdb_hex2long(&ptr, &addr))
268 linux_regs->pc = addr;268 linux_regs->pc = addr;
269 /* fallthrough */269 fallthrough;
270 case 'D':270 case 'D':
271 case 'k':271 case 'k':
272 atomic_set(&kgdb_cpu_doing_single_step, -1);272 atomic_set(&kgdb_cpu_doing_single_step, -1);
arch/sh/kernel/signal_32.c+1−1
@@ -418,7 +418,7 @@ handle_syscall_restart(unsigned long save_r0, struct pt_regs *regs, · 417 unmodified lines
418 case -ERESTARTSYS:418 case -ERESTARTSYS:
419 if (!(sa->sa_flags & SA_RESTART))419 if (!(sa->sa_flags & SA_RESTART))
420 goto no_system_call_restart;420 goto no_system_call_restart;
421 /* fallthrough */421 fallthrough;
422 case -ERESTARTNOINTR:422 case -ERESTARTNOINTR:
423 regs->regs[0] = save_r0;423 regs->regs[0] = save_r0;
424 regs->pc -= instruction_size(__raw_readw(regs->pc - 4));424 regs->pc -= instruction_size(__raw_readw(regs->pc - 4));
arch/sparc/kernel/auxio_64.c+0−1
@@ -87,7 +87,6 @@ void auxio_set_lte(int on) · 86 unmodified lines
87 __auxio_sbus_set_lte(on);87 __auxio_sbus_set_lte(on);
88 break;88 break;
89 case AUXIO_TYPE_EBUS:89 case AUXIO_TYPE_EBUS:
90 /* FALL-THROUGH */
91 default:90 default:
92 break;91 break;
93 }92 }
arch/sparc/kernel/central.c+1−1
@@ -55,7 +55,7 @@ static int clock_board_calc_nslots(struct clock_board *p) · 54 unmodified lines
55 else55 else
56 return 5;56 return 5;
57 }57 }
58 /* Fallthrough */58 fallthrough;
59 default:59 default:
60 return 4;60 return 4;
61 }61 }
arch/sparc/kernel/kgdb_32.c+1−1
@@ -122,7 +122,7 @@ int kgdb_arch_handle_exception(int e_vector, int signo, int err_code, · 121 unmodified lines
122 linux_regs->pc = addr;122 linux_regs->pc = addr;
123 linux_regs->npc = addr + 4;123 linux_regs->npc = addr + 4;
124 }124 }
125 /* fall through */125 fallthrough;
126 126
127 case 'D':127 case 'D':
128 case 'k':128 case 'k':
arch/sparc/kernel/kgdb_64.c+1−1
@@ -148,7 +148,7 @@ int kgdb_arch_handle_exception(int e_vector, int signo, int err_code, · 147 unmodified lines
148 linux_regs->tpc = addr;148 linux_regs->tpc = addr;
149 linux_regs->tnpc = addr + 4;149 linux_regs->tnpc = addr + 4;
150 }150 }
151 /* fall through */151 fallthrough;
152 152
153 case 'D':153 case 'D':
154 case 'k':154 case 'k':
arch/sparc/kernel/pcr.c+1−1
@@ -359,7 +359,7 @@ int __init pcr_arch_init(void) · 358 unmodified lines
359 * counter overflow interrupt so we can't make use of359 * counter overflow interrupt so we can't make use of
360 * their hardware currently.360 * their hardware currently.
361 */361 */
362 /* fallthrough */362 fallthrough;
363 default:363 default:
364 err = -ENODEV;364 err = -ENODEV;
365 goto out_unregister;365 goto out_unregister;
arch/sparc/kernel/prom_32.c+1−1
@@ -224,7 +224,7 @@ void __init of_console_init(void) · 223 unmodified lines
224 224
225 case PROMDEV_TTYB:225 case PROMDEV_TTYB:
226 skip = 1;226 skip = 1;
227 /* FALLTHRU */227 fallthrough;
228 228
229 case PROMDEV_TTYA:229 case PROMDEV_TTYA:
230 type = "serial";230 type = "serial";
arch/sparc/kernel/signal32.c+2−2
@@ -646,7 +646,7 @@ static inline void syscall_restart32(unsigned long orig_i0, struct pt_regs *regs · 645 unmodified lines
646 case ERESTARTSYS:646 case ERESTARTSYS:
647 if (!(sa->sa_flags & SA_RESTART))647 if (!(sa->sa_flags & SA_RESTART))
648 goto no_system_call_restart;648 goto no_system_call_restart;
649 /* fallthrough */649 fallthrough;
650 case ERESTARTNOINTR:650 case ERESTARTNOINTR:
651 regs->u_regs[UREG_I0] = orig_i0;651 regs->u_regs[UREG_I0] = orig_i0;
652 regs->tpc -= 4;652 regs->tpc -= 4;
@@ -686,7 +686,7 @@ void do_signal32(struct pt_regs * regs) · 33 unmodified lines
686 regs->tpc -= 4;686 regs->tpc -= 4;
687 regs->tnpc -= 4;687 regs->tnpc -= 4;
688 pt_regs_clear_syscall(regs);688 pt_regs_clear_syscall(regs);
689 /* fall through */689 fallthrough;
690 case ERESTART_RESTARTBLOCK:690 case ERESTART_RESTARTBLOCK:
691 regs->u_regs[UREG_G1] = __NR_restart_syscall;691 regs->u_regs[UREG_G1] = __NR_restart_syscall;
692 regs->tpc -= 4;692 regs->tpc -= 4;
arch/sparc/kernel/signal_32.c+2−2
@@ -440,7 +440,7 @@ static inline void syscall_restart(unsigned long orig_i0, struct pt_regs *regs, · 439 unmodified lines
440 case ERESTARTSYS:440 case ERESTARTSYS:
441 if (!(sa->sa_flags & SA_RESTART))441 if (!(sa->sa_flags & SA_RESTART))
442 goto no_system_call_restart;442 goto no_system_call_restart;
443 /* fallthrough */443 fallthrough;
444 case ERESTARTNOINTR:444 case ERESTARTNOINTR:
445 regs->u_regs[UREG_I0] = orig_i0;445 regs->u_regs[UREG_I0] = orig_i0;
446 regs->pc -= 4;446 regs->pc -= 4;
@@ -506,7 +506,7 @@ static void do_signal(struct pt_regs *regs, unsigned long orig_i0) · 59 unmodified lines
506 regs->pc -= 4;506 regs->pc -= 4;
507 regs->npc -= 4;507 regs->npc -= 4;
508 pt_regs_clear_syscall(regs);508 pt_regs_clear_syscall(regs);
509 /* fall through */509 fallthrough;
510 case ERESTART_RESTARTBLOCK:510 case ERESTART_RESTARTBLOCK:
511 regs->u_regs[UREG_G1] = __NR_restart_syscall;511 regs->u_regs[UREG_G1] = __NR_restart_syscall;
512 regs->pc -= 4;512 regs->pc -= 4;
arch/sparc/kernel/signal_64.c+2−2
@@ -461,7 +461,7 @@ static inline void syscall_restart(unsigned long orig_i0, struct pt_regs *regs, · 460 unmodified lines
461 case ERESTARTSYS:461 case ERESTARTSYS:
462 if (!(sa->sa_flags & SA_RESTART))462 if (!(sa->sa_flags & SA_RESTART))
463 goto no_system_call_restart;463 goto no_system_call_restart;
464 /* fallthrough */464 fallthrough;
465 case ERESTARTNOINTR:465 case ERESTARTNOINTR:
466 regs->u_regs[UREG_I0] = orig_i0;466 regs->u_regs[UREG_I0] = orig_i0;
467 regs->tpc -= 4;467 regs->tpc -= 4;
@@ -532,7 +532,7 @@ static void do_signal(struct pt_regs *regs, unsigned long orig_i0) · 64 unmodified lines
532 regs->tpc -= 4;532 regs->tpc -= 4;
533 regs->tnpc -= 4;533 regs->tnpc -= 4;
534 pt_regs_clear_syscall(regs);534 pt_regs_clear_syscall(regs);
535 /* fall through */535 fallthrough;
536 case ERESTART_RESTARTBLOCK:536 case ERESTART_RESTARTBLOCK:
537 regs->u_regs[UREG_G1] = __NR_restart_syscall;537 regs->u_regs[UREG_G1] = __NR_restart_syscall;
538 regs->tpc -= 4;538 regs->tpc -= 4;
arch/sparc/math-emu/math_32.c+4−4
@@ -359,7 +359,7 @@ static int do_one_mathemu(u32 insn, unsigned long *pfsr, unsigned long *fregs) · 358 unmodified lines
359 *pfsr |= (6 << 14);359 *pfsr |= (6 << 14);
360 return 0; /* simulate invalid_fp_register exception */360 return 0; /* simulate invalid_fp_register exception */
361 }361 }
362 /* fall through */362 fallthrough;
363 case 2:363 case 2:
364 if (freg & 1) { /* doublewords must have bit 5 zeroed */364 if (freg & 1) { /* doublewords must have bit 5 zeroed */
365 *pfsr |= (6 << 14);365 *pfsr |= (6 << 14);
@@ -380,7 +380,7 @@ static int do_one_mathemu(u32 insn, unsigned long *pfsr, unsigned long *fregs) · 14 unmodified lines
380 *pfsr |= (6 << 14);380 *pfsr |= (6 << 14);
381 return 0; /* simulate invalid_fp_register exception */381 return 0; /* simulate invalid_fp_register exception */
382 }382 }
383 /* fall through */383 fallthrough;
384 case 2:384 case 2:
385 if (freg & 1) { /* doublewords must have bit 5 zeroed */385 if (freg & 1) { /* doublewords must have bit 5 zeroed */
386 *pfsr |= (6 << 14);386 *pfsr |= (6 << 14);
@@ -408,13 +408,13 @@ static int do_one_mathemu(u32 insn, unsigned long *pfsr, unsigned long *fregs) · 21 unmodified lines
408 *pfsr |= (6 << 14);408 *pfsr |= (6 << 14);
409 return 0; /* simulate invalid_fp_register exception */409 return 0; /* simulate invalid_fp_register exception */
410 }410 }
411 /* fall through */411 fallthrough;
412 case 2:412 case 2:
413 if (freg & 1) { /* doublewords must have bit 5 zeroed */413 if (freg & 1) { /* doublewords must have bit 5 zeroed */
414 *pfsr |= (6 << 14);414 *pfsr |= (6 << 14);
415 return 0;415 return 0;
416 }416 }
417 /* fall through */417 fallthrough;
418 case 1:418 case 1:
419 rd = (void *)&fregs[freg];419 rd = (void *)&fregs[freg];
420 break;420 break;
arch/sparc/net/bpf_jit_comp_32.c+1−1
@@ -491,7 +491,7 @@ void bpf_jit_compile(struct bpf_prog *fp) · 490 unmodified lines
491 } else {491 } else {
492 emit_loadimm(K, r_A);492 emit_loadimm(K, r_A);
493 }493 }
494 /* Fallthrough */494 fallthrough;
495 case BPF_RET | BPF_A:495 case BPF_RET | BPF_A:
496 if (seen_or_pass0) {496 if (seen_or_pass0) {
497 if (i != flen - 1) {497 if (i != flen - 1) {
arch/um/kernel/signal.c+1−1
@@ -70,7 +70,7 @@ static void handle_signal(struct ksignal *ksig, struct pt_regs *regs) · 69 unmodified lines
70 PT_REGS_SYSCALL_RET(regs) = -EINTR;70 PT_REGS_SYSCALL_RET(regs) = -EINTR;
71 break;71 break;
72 }72 }
73 /* fallthrough */73 fallthrough;
74 case -ERESTARTNOINTR:74 case -ERESTARTNOINTR:
75 PT_REGS_RESTART_SYSCALL(regs);75 PT_REGS_RESTART_SYSCALL(regs);
76 PT_REGS_ORIG_SYSCALL(regs) = PT_REGS_SYSCALL_NR(regs);76 PT_REGS_ORIG_SYSCALL(regs) = PT_REGS_SYSCALL_NR(regs);
arch/x86/boot/cmdline.c+2−2
@@ -54,7 +54,7 @@ int __cmdline_find_option(unsigned long cmdline_ptr, const char *option, char *b · 53 unmodified lines
54 /* else */54 /* else */
55 state = st_wordcmp;55 state = st_wordcmp;
56 opptr = option;56 opptr = option;
57 /* fall through */57 fallthrough;
58 58
59 case st_wordcmp:59 case st_wordcmp:
60 if (c == '=' && !*opptr) {60 if (c == '=' && !*opptr) {
@@ -129,7 +129,7 @@ int __cmdline_find_option_bool(unsigned long cmdline_ptr, const char *option) · 68 unmodified lines
129 state = st_wordcmp;129 state = st_wordcmp;
130 opptr = option;130 opptr = option;
131 wstart = pos;131 wstart = pos;
132 /* fall through */132 fallthrough;
133 133
134 case st_wordcmp:134 case st_wordcmp:
135 if (!*opptr)135 if (!*opptr)
arch/x86/boot/compressed/kaslr.c+1−1
@@ -178,7 +178,7 @@ parse_memmap(char *p, unsigned long long *start, unsigned long long *size, · 177 unmodified lines
178 }178 }
179 *size = 0;179 *size = 0;
180 }180 }
181 /* Fall through */181 fallthrough;
182 default:182 default:
183 /*183 /*
184 * If w/o offset, only size specified, memmap=nn[KMG] has the184 * If w/o offset, only size specified, memmap=nn[KMG] has the
arch/x86/boot/compressed/misc.c+2−5
@@ -30,12 +30,9 @@ · 29 unmodified lines
30#define STATIC static30#define STATIC static
31 31
32/*32/*
33 * Use normal definitions of mem*() from string.c. There are already33 * Provide definitions of memzero and memmove as some of the decompressors will
34 * included header files which expect a definition of memset() and by34 * try to define their own functions if these are not defined as macros.
35 * the time we define memset macro, it is too late.
36 */35 */
37#undef memcpy
38#undef memset
39#define memzero(s, n) memset((s), 0, (n))36#define memzero(s, n) memset((s), 0, (n))
40#define memmove memmove37#define memmove memmove
41 38
arch/x86/boot/string.h+1−4
@@ -11,10 +11,7 @@ void *memcpy(void *dst, const void *src, size_t len); · 10 unmodified lines
11void *memset(void *dst, int c, size_t len);11void *memset(void *dst, int c, size_t len);
12int memcmp(const void *s1, const void *s2, size_t len);12int memcmp(const void *s1, const void *s2, size_t len);
13 13
14/*14/* Access builtin version by default. */
15 * Access builtin version by default. If one needs to use optimized version,
16 * do "undef memcpy" in .c file and link against right string.c
17 */
18#define memcpy(d,s,l) __builtin_memcpy(d,s,l)15#define memcpy(d,s,l) __builtin_memcpy(d,s,l)
19#define memset(d,c,l) __builtin_memset(d,c,l)16#define memset(d,c,l) __builtin_memset(d,c,l)
20#define memcmp __builtin_memcmp17#define memcmp __builtin_memcmp
arch/x86/entry/calling.h+6−4
@@ -374,12 +374,14 @@ For 32-bit we have the following conventions - kernel is built with · 373 unmodified lines
374 * Fetch the per-CPU GSBASE value for this processor and put it in @reg.374 * Fetch the per-CPU GSBASE value for this processor and put it in @reg.
375 * We normally use %gs for accessing per-CPU data, but we are setting up375 * We normally use %gs for accessing per-CPU data, but we are setting up
376 * %gs here and obviously can not use %gs itself to access per-CPU data.376 * %gs here and obviously can not use %gs itself to access per-CPU data.
377 *
378 * Do not use RDPID, because KVM loads guest's TSC_AUX on vm-entry and
379 * may not restore the host's value until the CPU returns to userspace.
380 * Thus the kernel would consume a guest's TSC_AUX if an NMI arrives
381 * while running KVM's run loop.
377 */382 */
378.macro GET_PERCPU_BASE reg:req383.macro GET_PERCPU_BASE reg:req
379 ALTERNATIVE \384 LOAD_CPU_AND_NODE_SEG_LIMIT \reg
380 "LOAD_CPU_AND_NODE_SEG_LIMIT \reg", \
381 "RDPID \reg", \
382 X86_FEATURE_RDPID
383 andq $VDSO_CPUNODE_MASK, \reg385 andq $VDSO_CPUNODE_MASK, \reg
384 movq __per_cpu_offset(, \reg, 8), \reg386 movq __per_cpu_offset(, \reg, 8), \reg
385.endm387.endm
arch/x86/entry/common.c+20−9
@@ -60,16 +60,10 @@ __visible noinstr void do_syscall_64(unsigned long nr, struct pt_regs *regs) · 59 unmodified lines
60#if defined(CONFIG_X86_32) || defined(CONFIG_IA32_EMULATION)60#if defined(CONFIG_X86_32) || defined(CONFIG_IA32_EMULATION)
61static __always_inline unsigned int syscall_32_enter(struct pt_regs *regs)61static __always_inline unsigned int syscall_32_enter(struct pt_regs *regs)
62{62{
63 unsigned int nr = (unsigned int)regs->orig_ax;
64
65 if (IS_ENABLED(CONFIG_IA32_EMULATION))63 if (IS_ENABLED(CONFIG_IA32_EMULATION))
66 current_thread_info()->status |= TS_COMPAT;64 current_thread_info()->status |= TS_COMPAT;
67 /*65
68 * Subtlety here: if ptrace pokes something larger than 2^32-1 into66 return (unsigned int)regs->orig_ax;
69 * orig_ax, the unsigned int return value truncates it. This may
70 * or may not be necessary, but it matches the old asm behavior.
71 */
72 return (unsigned int)syscall_enter_from_user_mode(regs, nr);
73}67}
74 68
75/*69/*
@@ -91,15 +85,29 @@ __visible noinstr void do_int80_syscall_32(struct pt_regs *regs) · 15 unmodified lines
91{85{
92 unsigned int nr = syscall_32_enter(regs);86 unsigned int nr = syscall_32_enter(regs);
93 87
88 /*
89 * Subtlety here: if ptrace pokes something larger than 2^32-1 into
90 * orig_ax, the unsigned int return value truncates it. This may
91 * or may not be necessary, but it matches the old asm behavior.
92 */
93 nr = (unsigned int)syscall_enter_from_user_mode(regs, nr);
94
94 do_syscall_32_irqs_on(regs, nr);95 do_syscall_32_irqs_on(regs, nr);
95 syscall_exit_to_user_mode(regs);96 syscall_exit_to_user_mode(regs);
96}97}
97 98
98static noinstr bool __do_fast_syscall_32(struct pt_regs *regs)99static noinstr bool __do_fast_syscall_32(struct pt_regs *regs)
99{100{
100 unsigned int nr = syscall_32_enter(regs);101 unsigned int nr = syscall_32_enter(regs);
101 int res;102 int res;
102 103
104 /*
105 * This cannot use syscall_enter_from_user_mode() as it has to
106 * fetch EBP before invoking any of the syscall entry work
107 * functions.
108 */
109 syscall_enter_from_user_mode_prepare(regs);
110
103 instrumentation_begin();111 instrumentation_begin();
104 /* Fetch EBP from where the vDSO stashed it. */112 /* Fetch EBP from where the vDSO stashed it. */
105 if (IS_ENABLED(CONFIG_X86_64)) {113 if (IS_ENABLED(CONFIG_X86_64)) {
@@ -122,6 +130,9 @@ static noinstr bool __do_fast_syscall_32(struct pt_regs *regs) · 16 unmodified lines
122 return false;130 return false;
123 }131 }
124 132
133 /* The case truncates any ptrace induced syscall nr > 2^32 -1 */
134 nr = (unsigned int)syscall_enter_from_user_mode_work(regs, nr);
135
125 /* Now this is just like a normal syscall. */136 /* Now this is just like a normal syscall. */
126 do_syscall_32_irqs_on(regs, nr);137 do_syscall_32_irqs_on(regs, nr);
127 syscall_exit_to_user_mode(regs);138 syscall_exit_to_user_mode(regs);
arch/x86/entry/thunk_32.S+0−5
@@ -29,11 +29,6 @@ SYM_CODE_START_NOALIGN(\name) · 28 unmodified lines
29SYM_CODE_END(\name)29SYM_CODE_END(\name)
30 .endm30 .endm
31 31
32#ifdef CONFIG_TRACE_IRQFLAGS
33 THUNK trace_hardirqs_on_thunk,trace_hardirqs_on_caller,1
34 THUNK trace_hardirqs_off_thunk,trace_hardirqs_off_caller,1
35#endif
36
37#ifdef CONFIG_PREEMPTION32#ifdef CONFIG_PREEMPTION
38 THUNK preempt_schedule_thunk, preempt_schedule33 THUNK preempt_schedule_thunk, preempt_schedule
39 THUNK preempt_schedule_notrace_thunk, preempt_schedule_notrace34 THUNK preempt_schedule_notrace_thunk, preempt_schedule_notrace
arch/x86/events/intel/core.c+3−3
@@ -4682,7 +4682,7 @@ __init int intel_pmu_init(void) · 4681 unmodified lines
4682 4682
4683 case INTEL_FAM6_CORE2_MEROM:4683 case INTEL_FAM6_CORE2_MEROM:
4684 x86_add_quirk(intel_clovertown_quirk);4684 x86_add_quirk(intel_clovertown_quirk);
4685 /* fall through */4685 fallthrough;
4686 4686
4687 case INTEL_FAM6_CORE2_MEROM_L:4687 case INTEL_FAM6_CORE2_MEROM_L:
4688 case INTEL_FAM6_CORE2_PENRYN:4688 case INTEL_FAM6_CORE2_PENRYN:
@@ -5062,7 +5062,7 @@ __init int intel_pmu_init(void) · 373 unmodified lines
5062 5062
5063 case INTEL_FAM6_SKYLAKE_X:5063 case INTEL_FAM6_SKYLAKE_X:
5064 pmem = true;5064 pmem = true;
5065 /* fall through */5065 fallthrough;
5066 case INTEL_FAM6_SKYLAKE_L:5066 case INTEL_FAM6_SKYLAKE_L:
5067 case INTEL_FAM6_SKYLAKE:5067 case INTEL_FAM6_SKYLAKE:
5068 case INTEL_FAM6_KABYLAKE_L:5068 case INTEL_FAM6_KABYLAKE_L:
@@ -5114,7 +5114,7 @@ __init int intel_pmu_init(void) · 45 unmodified lines
5114 case INTEL_FAM6_ICELAKE_X:5114 case INTEL_FAM6_ICELAKE_X:
5115 case INTEL_FAM6_ICELAKE_D:5115 case INTEL_FAM6_ICELAKE_D:
5116 pmem = true;5116 pmem = true;
5117 /* fall through */5117 fallthrough;
5118 case INTEL_FAM6_ICELAKE_L:5118 case INTEL_FAM6_ICELAKE_L:
5119 case INTEL_FAM6_ICELAKE:5119 case INTEL_FAM6_ICELAKE:
5120 case INTEL_FAM6_TIGERLAKE_L:5120 case INTEL_FAM6_TIGERLAKE_L:
arch/x86/events/intel/lbr.c+1−1
@@ -1268,7 +1268,7 @@ static int branch_type(unsigned long from, unsigned long to, int abort) · 1267 unmodified lines
1268 ret = X86_BR_ZERO_CALL;1268 ret = X86_BR_ZERO_CALL;
1269 break;1269 break;
1270 }1270 }
1271 /* fall through */1271 fallthrough;
1272 case 0x9a: /* call far absolute */1272 case 0x9a: /* call far absolute */
1273 ret = X86_BR_CALL;1273 ret = X86_BR_CALL;
1274 break;1274 break;
arch/x86/events/intel/uncore_snb.c+49−3
@@ -390,6 +390,18 @@ static struct uncore_event_desc snb_uncore_imc_events[] = { · 389 unmodified lines
390 INTEL_UNCORE_EVENT_DESC(data_writes.scale, "6.103515625e-5"),390 INTEL_UNCORE_EVENT_DESC(data_writes.scale, "6.103515625e-5"),
391 INTEL_UNCORE_EVENT_DESC(data_writes.unit, "MiB"),391 INTEL_UNCORE_EVENT_DESC(data_writes.unit, "MiB"),
392 392
393 INTEL_UNCORE_EVENT_DESC(gt_requests, "event=0x03"),
394 INTEL_UNCORE_EVENT_DESC(gt_requests.scale, "6.103515625e-5"),
395 INTEL_UNCORE_EVENT_DESC(gt_requests.unit, "MiB"),
396
397 INTEL_UNCORE_EVENT_DESC(ia_requests, "event=0x04"),
398 INTEL_UNCORE_EVENT_DESC(ia_requests.scale, "6.103515625e-5"),
399 INTEL_UNCORE_EVENT_DESC(ia_requests.unit, "MiB"),
400
401 INTEL_UNCORE_EVENT_DESC(io_requests, "event=0x05"),
402 INTEL_UNCORE_EVENT_DESC(io_requests.scale, "6.103515625e-5"),
403 INTEL_UNCORE_EVENT_DESC(io_requests.unit, "MiB"),
404
393 { /* end: all zeroes */ },405 { /* end: all zeroes */ },
394};406};
395 407
@@ -405,13 +417,35 @@ static struct uncore_event_desc snb_uncore_imc_events[] = { · 9 unmodified lines
405#define SNB_UNCORE_PCI_IMC_DATA_WRITES_BASE 0x5054417#define SNB_UNCORE_PCI_IMC_DATA_WRITES_BASE 0x5054
406#define SNB_UNCORE_PCI_IMC_CTR_BASE SNB_UNCORE_PCI_IMC_DATA_READS_BASE418#define SNB_UNCORE_PCI_IMC_CTR_BASE SNB_UNCORE_PCI_IMC_DATA_READS_BASE
407 419
420/* BW break down- legacy counters */
421#define SNB_UNCORE_PCI_IMC_GT_REQUESTS 0x3
422#define SNB_UNCORE_PCI_IMC_GT_REQUESTS_BASE 0x5040
423#define SNB_UNCORE_PCI_IMC_IA_REQUESTS 0x4
424#define SNB_UNCORE_PCI_IMC_IA_REQUESTS_BASE 0x5044
425#define SNB_UNCORE_PCI_IMC_IO_REQUESTS 0x5
426#define SNB_UNCORE_PCI_IMC_IO_REQUESTS_BASE 0x5048
427
408enum perf_snb_uncore_imc_freerunning_types {428enum perf_snb_uncore_imc_freerunning_types {
409 SNB_PCI_UNCORE_IMC_DATA = 0,429 SNB_PCI_UNCORE_IMC_DATA_READS = 0,
430 SNB_PCI_UNCORE_IMC_DATA_WRITES,
431 SNB_PCI_UNCORE_IMC_GT_REQUESTS,
432 SNB_PCI_UNCORE_IMC_IA_REQUESTS,
433 SNB_PCI_UNCORE_IMC_IO_REQUESTS,
434
410 SNB_PCI_UNCORE_IMC_FREERUNNING_TYPE_MAX,435 SNB_PCI_UNCORE_IMC_FREERUNNING_TYPE_MAX,
411};436};
412 437
413static struct freerunning_counters snb_uncore_imc_freerunning[] = {438static struct freerunning_counters snb_uncore_imc_freerunning[] = {
414 [SNB_PCI_UNCORE_IMC_DATA] = { SNB_UNCORE_PCI_IMC_DATA_READS_BASE, 0x4, 0x0, 2, 32 },439 [SNB_PCI_UNCORE_IMC_DATA_READS] = { SNB_UNCORE_PCI_IMC_DATA_READS_BASE,
440 0x0, 0x0, 1, 32 },
441 [SNB_PCI_UNCORE_IMC_DATA_READS] = { SNB_UNCORE_PCI_IMC_DATA_WRITES_BASE,
442 0x0, 0x0, 1, 32 },
443 [SNB_PCI_UNCORE_IMC_GT_REQUESTS] = { SNB_UNCORE_PCI_IMC_GT_REQUESTS_BASE,
444 0x0, 0x0, 1, 32 },
445 [SNB_PCI_UNCORE_IMC_IA_REQUESTS] = { SNB_UNCORE_PCI_IMC_IA_REQUESTS_BASE,
446 0x0, 0x0, 1, 32 },
447 [SNB_PCI_UNCORE_IMC_IO_REQUESTS] = { SNB_UNCORE_PCI_IMC_IO_REQUESTS_BASE,
448 0x0, 0x0, 1, 32 },
415};449};
416 450
417static struct attribute *snb_uncore_imc_formats_attr[] = {451static struct attribute *snb_uncore_imc_formats_attr[] = {
@@ -525,6 +559,18 @@ static int snb_uncore_imc_event_init(struct perf_event *event) · 107 unmodified lines
525 base = SNB_UNCORE_PCI_IMC_DATA_WRITES_BASE;559 base = SNB_UNCORE_PCI_IMC_DATA_WRITES_BASE;
526 idx = UNCORE_PMC_IDX_FREERUNNING;560 idx = UNCORE_PMC_IDX_FREERUNNING;
527 break;561 break;
562 case SNB_UNCORE_PCI_IMC_GT_REQUESTS:
563 base = SNB_UNCORE_PCI_IMC_GT_REQUESTS_BASE;
564 idx = UNCORE_PMC_IDX_FREERUNNING;
565 break;
566 case SNB_UNCORE_PCI_IMC_IA_REQUESTS:
567 base = SNB_UNCORE_PCI_IMC_IA_REQUESTS_BASE;
568 idx = UNCORE_PMC_IDX_FREERUNNING;
569 break;
570 case SNB_UNCORE_PCI_IMC_IO_REQUESTS:
571 base = SNB_UNCORE_PCI_IMC_IO_REQUESTS_BASE;
572 idx = UNCORE_PMC_IDX_FREERUNNING;
573 break;
528 default:574 default:
529 return -EINVAL;575 return -EINVAL;
530 }576 }
@@ -598,7 +644,7 @@ static struct intel_uncore_ops snb_uncore_imc_ops = { · 67 unmodified lines
598 644
599static struct intel_uncore_type snb_uncore_imc = {645static struct intel_uncore_type snb_uncore_imc = {
600 .name = "imc",646 .name = "imc",
601 .num_counters = 2,647 .num_counters = 5,
602 .num_boxes = 1,648 .num_boxes = 1,
603 .num_freerunning_types = SNB_PCI_UNCORE_IMC_FREERUNNING_TYPE_MAX,649 .num_freerunning_types = SNB_PCI_UNCORE_IMC_FREERUNNING_TYPE_MAX,
604 .mmio_map_size = SNB_UNCORE_PCI_IMC_MAP_SIZE,650 .mmio_map_size = SNB_UNCORE_PCI_IMC_MAP_SIZE,
arch/x86/include/asm/efi.h+0−10
@@ -81,11 +81,8 @@ extern unsigned long efi_fw_vendor, efi_config_table; · 80 unmodified lines
81 kernel_fpu_end(); \81 kernel_fpu_end(); \
82})82})
83 83
84
85#define arch_efi_call_virt(p, f, args...) p->f(args)84#define arch_efi_call_virt(p, f, args...) p->f(args)
86 85
87#define efi_ioremap(addr, size, type, attr) ioremap_cache(addr, size)
88
89#else /* !CONFIG_X86_32 */86#else /* !CONFIG_X86_32 */
90 87
91#define EFI_LOADER_SIGNATURE "EL64"88#define EFI_LOADER_SIGNATURE "EL64"
@@ -125,9 +122,6 @@ struct efi_scratch { · 33 unmodified lines
125 kernel_fpu_end(); \122 kernel_fpu_end(); \
126})123})
127 124
128extern void __iomem *__init efi_ioremap(unsigned long addr, unsigned long size,
129 u32 type, u64 attribute);
130
131#ifdef CONFIG_KASAN125#ifdef CONFIG_KASAN
132/*126/*
133 * CONFIG_KASAN may redefine memset to __memset. __memset function is present127 * CONFIG_KASAN may redefine memset to __memset. __memset function is present
@@ -143,17 +137,13 @@ extern void __iomem *__init efi_ioremap(unsigned long addr, unsigned long size, · 9 unmodified lines
143#endif /* CONFIG_X86_32 */137#endif /* CONFIG_X86_32 */
144 138
145extern struct efi_scratch efi_scratch;139extern struct efi_scratch efi_scratch;
146extern void __init efi_set_executable(efi_memory_desc_t *md, bool executable);
147extern int __init efi_memblock_x86_reserve_range(void);140extern int __init efi_memblock_x86_reserve_range(void);
148extern void __init efi_print_memmap(void);141extern void __init efi_print_memmap(void);
149extern void __init efi_memory_uc(u64 addr, unsigned long size);
150extern void __init efi_map_region(efi_memory_desc_t *md);142extern void __init efi_map_region(efi_memory_desc_t *md);
151extern void __init efi_map_region_fixed(efi_memory_desc_t *md);143extern void __init efi_map_region_fixed(efi_memory_desc_t *md);
152extern void efi_sync_low_kernel_mappings(void);144extern void efi_sync_low_kernel_mappings(void);
153extern int __init efi_alloc_page_tables(void);145extern int __init efi_alloc_page_tables(void);
154extern int __init efi_setup_page_tables(unsigned long pa_memmap, unsigned num_pages);146extern int __init efi_setup_page_tables(unsigned long pa_memmap, unsigned num_pages);
155extern void __init old_map_region(efi_memory_desc_t *md);
156extern void __init runtime_code_page_mkexec(void);
157extern void __init efi_runtime_update_mappings(void);147extern void __init efi_runtime_update_mappings(void);
158extern void __init efi_dump_pagetable(void);148extern void __init efi_dump_pagetable(void);
159extern void __init efi_apply_memmap_quirks(void);149extern void __init efi_apply_memmap_quirks(void);
arch/x86/include/asm/entry-common.h+10−2
@@ -18,8 +18,16 @@ static __always_inline void arch_check_user_regs(struct pt_regs *regs) · 17 unmodified lines
18 * state, not the interrupt state as imagined by Xen.18 * state, not the interrupt state as imagined by Xen.
19 */19 */
20 unsigned long flags = native_save_fl();20 unsigned long flags = native_save_fl();
21 WARN_ON_ONCE(flags & (X86_EFLAGS_AC | X86_EFLAGS_DF |21 unsigned long mask = X86_EFLAGS_DF | X86_EFLAGS_NT;
22 X86_EFLAGS_NT));22
23 /*
24 * For !SMAP hardware we patch out CLAC on entry.
25 */
26 if (boot_cpu_has(X86_FEATURE_SMAP) ||
27 (IS_ENABLED(CONFIG_64_BIT) && boot_cpu_has(X86_FEATURE_XENPV)))
28 mask |= X86_EFLAGS_AC;
29
30 WARN_ON_ONCE(flags & mask);
23 31
24 /* We think we came from user mode. Make sure pt_regs agrees. */32 /* We think we came from user mode. Make sure pt_regs agrees. */
25 WARN_ON_ONCE(!user_mode(regs));33 WARN_ON_ONCE(!user_mode(regs));
arch/x86/include/asm/kvm_host.h+2−1
@@ -1596,7 +1596,8 @@ asmlinkage void kvm_spurious_fault(void); · 1595 unmodified lines
1596 _ASM_EXTABLE(666b, 667b)1596 _ASM_EXTABLE(666b, 667b)
1597 1597
1598#define KVM_ARCH_WANT_MMU_NOTIFIER1598#define KVM_ARCH_WANT_MMU_NOTIFIER
1599int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end);1599int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end,
1600 unsigned flags);
1600int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end);1601int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end);
1601int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);1602int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);
1602int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);1603int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
arch/x86/include/asm/mmu.h+1−0
@@ -59,5 +59,6 @@ typedef struct { · 58 unmodified lines
59 }59 }
60 60
61void leave_mm(int cpu);61void leave_mm(int cpu);
62#define leave_mm leave_mm
62 63
63#endif /* _ASM_X86_MMU_H */64#endif /* _ASM_X86_MMU_H */
arch/x86/include/asm/ptrace.h+1−1
@@ -327,8 +327,8 @@ static inline unsigned long regs_get_kernel_argument(struct pt_regs *regs, · 326 unmodified lines
327 static const unsigned int argument_offs[] = {327 static const unsigned int argument_offs[] = {
328#ifdef __i386__328#ifdef __i386__
329 offsetof(struct pt_regs, ax),329 offsetof(struct pt_regs, ax),
330 offsetof(struct pt_regs, cx),
331 offsetof(struct pt_regs, dx),330 offsetof(struct pt_regs, dx),
331 offsetof(struct pt_regs, cx),
332#define NR_REG_ARGUMENTS 3332#define NR_REG_ARGUMENTS 3
333#else333#else
334 offsetof(struct pt_regs, di),334 offsetof(struct pt_regs, di),
arch/x86/kernel/alternative.c+1−1
@@ -239,7 +239,7 @@ void __init arch_init_ideal_nops(void) · 238 unmodified lines
239 return;239 return;
240 }240 }
241 241
242 /* fall through */242 fallthrough;
243 243
244 default:244 default:
245#ifdef CONFIG_X86_64245#ifdef CONFIG_X86_64
arch/x86/kernel/apic/io_apic.c+2−2
@@ -800,7 +800,7 @@ static int irq_polarity(int idx) · 799 unmodified lines
800 return IOAPIC_POL_HIGH;800 return IOAPIC_POL_HIGH;
801 case MP_IRQPOL_RESERVED:801 case MP_IRQPOL_RESERVED:
802 pr_warn("IOAPIC: Invalid polarity: 2, defaulting to low\n");802 pr_warn("IOAPIC: Invalid polarity: 2, defaulting to low\n");
803 /* fall through */803 fallthrough;
804 case MP_IRQPOL_ACTIVE_LOW:804 case MP_IRQPOL_ACTIVE_LOW:
805 default: /* Pointless default required due to do gcc stupidity */805 default: /* Pointless default required due to do gcc stupidity */
806 return IOAPIC_POL_LOW;806 return IOAPIC_POL_LOW;
@@ -848,7 +848,7 @@ static int irq_trigger(int idx) · 41 unmodified lines
848 return IOAPIC_EDGE;848 return IOAPIC_EDGE;
849 case MP_IRQTRIG_RESERVED:849 case MP_IRQTRIG_RESERVED:
850 pr_warn("IOAPIC: Invalid trigger mode 2 defaulting to level\n");850 pr_warn("IOAPIC: Invalid trigger mode 2 defaulting to level\n");
851 /* fall through */851 fallthrough;
852 case MP_IRQTRIG_LEVEL:852 case MP_IRQTRIG_LEVEL:
853 default: /* Pointless default required due to do gcc stupidity */853 default: /* Pointless default required due to do gcc stupidity */
854 return IOAPIC_LEVEL;854 return IOAPIC_LEVEL;
arch/x86/kernel/apic/probe_32.c+1−1
@@ -149,7 +149,7 @@ void __init default_setup_apic_routing(void) · 148 unmodified lines
149 break;149 break;
150 }150 }
151 /* P4 and above */151 /* P4 and above */
152 /* fall through */152 fallthrough;
153 case X86_VENDOR_HYGON:153 case X86_VENDOR_HYGON:
154 case X86_VENDOR_AMD:154 case X86_VENDOR_AMD:
155 def_to_bigsmp = 1;155 def_to_bigsmp = 1;
arch/x86/kernel/apic/vector.c+9−7
@@ -161,6 +161,7 @@ static void apic_update_vector(struct irq_data *irqd, unsigned int newvec, · 160 unmodified lines
161 apicd->move_in_progress = true;161 apicd->move_in_progress = true;
162 apicd->prev_vector = apicd->vector;162 apicd->prev_vector = apicd->vector;
163 apicd->prev_cpu = apicd->cpu;163 apicd->prev_cpu = apicd->cpu;
164 WARN_ON_ONCE(apicd->cpu == newcpu);
164 } else {165 } else {
165 irq_matrix_free(vector_matrix, apicd->cpu, apicd->vector,166 irq_matrix_free(vector_matrix, apicd->cpu, apicd->vector,
166 managed);167 managed);
@@ -910,7 +911,7 @@ void send_cleanup_vector(struct irq_cfg *cfg) · 743 unmodified lines
910 __send_cleanup_vector(apicd);911 __send_cleanup_vector(apicd);
911}912}
912 913
913static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector)914void irq_complete_move(struct irq_cfg *cfg)
914{915{
915 struct apic_chip_data *apicd;916 struct apic_chip_data *apicd;
916 917
@@ -918,15 +919,16 @@ static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector) · 1 unmodified line
918 if (likely(!apicd->move_in_progress))919 if (likely(!apicd->move_in_progress))
919 return;920 return;
920 921
921 if (vector == apicd->vector && apicd->cpu == smp_processor_id())922 /*
923 * If the interrupt arrived on the new target CPU, cleanup the
924 * vector on the old target CPU. A vector check is not required
925 * because an interrupt can never move from one vector to another
926 * on the same CPU.
927 */
928 if (apicd->cpu == smp_processor_id())
922 __send_cleanup_vector(apicd);929 __send_cleanup_vector(apicd);
923}930}
924 931
925void irq_complete_move(struct irq_cfg *cfg)
926{
927 __irq_complete_move(cfg, ~get_irq_regs()->orig_ax);
928}
929
930/*932/*
931 * Called from fixup_irqs() with @desc->lock held and interrupts disabled.933 * Called from fixup_irqs() with @desc->lock held and interrupts disabled.
932 */934 */
arch/x86/kernel/cpu/cacheinfo.c+1−1
@@ -248,7 +248,7 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax, · 247 unmodified lines
248 switch (leaf) {248 switch (leaf) {
249 case 1:249 case 1:
250 l1 = &l1i;250 l1 = &l1i;
251 /* fall through */251 fallthrough;
252 case 0:252 case 0:
253 if (!l1->val)253 if (!l1->val)
254 return;254 return;
arch/x86/kernel/cpu/mce/inject.c+1−1
@@ -199,7 +199,7 @@ static int raise_local(void) · 198 unmodified lines
199 * calling irq_enter, but the necessary199 * calling irq_enter, but the necessary
200 * machinery isn't exported currently.200 * machinery isn't exported currently.
201 */201 */
202 /*FALL THROUGH*/202 fallthrough;
203 case MCJ_CTX_PROCESS:203 case MCJ_CTX_PROCESS:
204 raise_exception(m, NULL);204 raise_exception(m, NULL);
205 break;205 break;
arch/x86/kernel/cpu/mce/intel.c+1−1
@@ -193,7 +193,7 @@ unsigned long cmci_intel_adjust_timer(unsigned long interval) · 192 unmodified lines
193 if (!atomic_sub_return(1, &cmci_storm_on_cpus))193 if (!atomic_sub_return(1, &cmci_storm_on_cpus))
194 pr_notice("CMCI storm subsided: switching to interrupt mode\n");194 pr_notice("CMCI storm subsided: switching to interrupt mode\n");
195 195
196 /* FALLTHROUGH */196 fallthrough;
197 197
198 case CMCI_STORM_SUBSIDED:198 case CMCI_STORM_SUBSIDED:
199 /*199 /*
arch/x86/kernel/cpu/mtrr/cyrix.c+1−1
@@ -98,7 +98,7 @@ cyrix_get_free_region(unsigned long base, unsigned long size, int replace_reg) · 97 unmodified lines
98 case 7:98 case 7:
99 if (size < 0x40)99 if (size < 0x40)
100 break;100 break;
101 /* Else, fall through */101 fallthrough;
102 case 6:102 case 6:
103 case 5:103 case 5:
104 case 4:104 case 4:
arch/x86/kernel/hw_breakpoint.c+1−1
@@ -349,7 +349,7 @@ static int arch_build_bp_info(struct perf_event *bp, · 348 unmodified lines
349 hw->len = X86_BREAKPOINT_LEN_X;349 hw->len = X86_BREAKPOINT_LEN_X;
350 return 0;350 return 0;
351 }351 }
352 /* fall through */352 fallthrough;
353 default:353 default:
354 return -EINVAL;354 return -EINVAL;
355 }355 }
arch/x86/kernel/kgdb.c+2−2
@@ -450,7 +450,7 @@ int kgdb_arch_handle_exception(int e_vector, int signo, int err_code, · 449 unmodified lines
450 ptr = &remcomInBuffer[1];450 ptr = &remcomInBuffer[1];
451 if (kgdb_hex2long(&ptr, &addr))451 if (kgdb_hex2long(&ptr, &addr))
452 linux_regs->ip = addr;452 linux_regs->ip = addr;
453 /* fall through */453 fallthrough;
454 case 'D':454 case 'D':
455 case 'k':455 case 'k':
456 /* clear the trace bit */456 /* clear the trace bit */
@@ -539,7 +539,7 @@ static int __kgdb_notify(struct die_args *args, unsigned long cmd) · 82 unmodified lines
539 * a system call which should be ignored539 * a system call which should be ignored
540 */540 */
541 return NOTIFY_DONE;541 return NOTIFY_DONE;
542 /* fall through */542 fallthrough;
543 default:543 default:
544 if (user_mode(regs))544 if (user_mode(regs))
545 return NOTIFY_DONE;545 return NOTIFY_DONE;
arch/x86/kernel/mpparse.c+2−2
@@ -312,7 +312,7 @@ static void __init construct_default_ioirq_mptable(int mpc_default_type) · 311 unmodified lines
312 case 2:312 case 2:
313 if (i == 0 || i == 13)313 if (i == 0 || i == 13)
314 continue; /* IRQ0 & IRQ13 not connected */314 continue; /* IRQ0 & IRQ13 not connected */
315 /* fall through */315 fallthrough;
316 default:316 default:
317 if (i == 2)317 if (i == 2)
318 continue; /* IRQ2 is never connected */318 continue; /* IRQ2 is never connected */
@@ -356,7 +356,7 @@ static void __init construct_ioapic_table(int mpc_default_type) · 37 unmodified lines
356 default:356 default:
357 pr_err("???\nUnknown standard configuration %d\n",357 pr_err("???\nUnknown standard configuration %d\n",
358 mpc_default_type);358 mpc_default_type);
359 /* fall through */359 fallthrough;
360 case 1:360 case 1:
361 case 5:361 case 5:
362 memcpy(bus.bustype, "ISA ", 6);362 memcpy(bus.bustype, "ISA ", 6);
arch/x86/kernel/process.c+0−4
@@ -684,9 +684,7 @@ void arch_cpu_idle(void) · 683 unmodified lines
684 */684 */
685void __cpuidle default_idle(void)685void __cpuidle default_idle(void)
686{686{
687 trace_cpu_idle_rcuidle(1, smp_processor_id());
688 safe_halt();687 safe_halt();
689 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
690}688}
691#if defined(CONFIG_APM_MODULE) || defined(CONFIG_HALTPOLL_CPUIDLE_MODULE)689#if defined(CONFIG_APM_MODULE) || defined(CONFIG_HALTPOLL_CPUIDLE_MODULE)
692EXPORT_SYMBOL(default_idle);690EXPORT_SYMBOL(default_idle);
@@ -792,7 +790,6 @@ static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c) · 99 unmodified lines
792static __cpuidle void mwait_idle(void)790static __cpuidle void mwait_idle(void)
793{791{
794 if (!current_set_polling_and_test()) {792 if (!current_set_polling_and_test()) {
795 trace_cpu_idle_rcuidle(1, smp_processor_id());
796 if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) {793 if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) {
797 mb(); /* quirk */794 mb(); /* quirk */
798 clflush((void *)&current_thread_info()->flags);795 clflush((void *)&current_thread_info()->flags);
@@ -804,7 +801,6 @@ static __cpuidle void mwait_idle(void) · 5 unmodified lines
804 __sti_mwait(0, 0);801 __sti_mwait(0, 0);
805 else802 else
806 local_irq_enable();803 local_irq_enable();
807 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
808 } else {804 } else {
809 local_irq_enable();805 local_irq_enable();
810 }806 }
arch/x86/kernel/ptrace.c+1−1
@@ -204,7 +204,7 @@ static int set_segment_reg(struct task_struct *task, · 203 unmodified lines
204 case offsetof(struct user_regs_struct, ss):204 case offsetof(struct user_regs_struct, ss):
205 if (unlikely(value == 0))205 if (unlikely(value == 0))
206 return -EIO;206 return -EIO;
207 /* Else, fall through */207 fallthrough;
208 208
209 default:209 default:
210 *pt_regs_access(task_pt_regs(task), offset) = value;210 *pt_regs_access(task_pt_regs(task), offset) = value;
arch/x86/kernel/reboot.c+1−1
@@ -654,7 +654,7 @@ static void native_machine_emergency_restart(void) · 653 unmodified lines
654 654
655 case BOOT_CF9_FORCE:655 case BOOT_CF9_FORCE:
656 port_cf9_safe = true;656 port_cf9_safe = true;
657 /* Fall through */657 fallthrough;
658 658
659 case BOOT_CF9_SAFE:659 case BOOT_CF9_SAFE:
660 if (port_cf9_safe) {660 if (port_cf9_safe) {
arch/x86/kernel/signal.c+1−1
@@ -726,7 +726,7 @@ handle_signal(struct ksignal *ksig, struct pt_regs *regs) · 725 unmodified lines
726 regs->ax = -EINTR;726 regs->ax = -EINTR;
727 break;727 break;
728 }728 }
729 /* fallthrough */729 fallthrough;
730 case -ERESTARTNOINTR:730 case -ERESTARTNOINTR:
731 regs->ax = regs->orig_ax;731 regs->ax = regs->orig_ax;
732 regs->ip -= 2;732 regs->ip -= 2;
arch/x86/kernel/smpboot.c+20−6
@@ -1594,14 +1594,28 @@ int native_cpu_disable(void) · 1593 unmodified lines
1594 if (ret)1594 if (ret)
1595 return ret;1595 return ret;
1596 1596
1597 /*
1598 * Disable the local APIC. Otherwise IPI broadcasts will reach
1599 * it. It still responds normally to INIT, NMI, SMI, and SIPI
1600 * messages.
1601 */
1602 apic_soft_disable();
1603 cpu_disable_common();1597 cpu_disable_common();
1604 1598
1599 /*
1600 * Disable the local APIC. Otherwise IPI broadcasts will reach
1601 * it. It still responds normally to INIT, NMI, SMI, and SIPI
1602 * messages.
1603 *
1604 * Disabling the APIC must happen after cpu_disable_common()
1605 * which invokes fixup_irqs().
1606 *
1607 * Disabling the APIC preserves already set bits in IRR, but
1608 * an interrupt arriving after disabling the local APIC does not
1609 * set the corresponding IRR bit.
1610 *
1611 * fixup_irqs() scans IRR for set bits so it can raise a not
1612 * yet handled interrupt on the new destination CPU via an IPI
1613 * but obviously it can't do so for IRR bits which are not set.
1614 * IOW, interrupts arriving after disabling the local APIC will
1615 * be lost.
1616 */
1617 apic_soft_disable();
1618
1605 return 0;1619 return 0;
1606}1620}
1607 1621
arch/x86/kernel/traps.c+31−34
@@ -729,20 +729,9 @@ static bool is_sysenter_singlestep(struct pt_regs *regs) · 728 unmodified lines
729#endif729#endif
730}730}
731 731
732static __always_inline void debug_enter(unsigned long *dr6, unsigned long *dr7)732static __always_inline unsigned long debug_read_clear_dr6(void)
733{733{
734 /*734 unsigned long dr6;
735 * Disable breakpoints during exception handling; recursive exceptions
736 * are exceedingly 'fun'.
737 *
738 * Since this function is NOKPROBE, and that also applies to
739 * HW_BREAKPOINT_X, we can't hit a breakpoint before this (XXX except a
740 * HW_BREAKPOINT_W on our stack)
741 *
742 * Entry text is excluded for HW_BP_X and cpu_entry_area, which
743 * includes the entry stack is excluded for everything.
744 */
745 *dr7 = local_db_save();
746 735
747 /*736 /*
748 * The Intel SDM says:737 * The Intel SDM says:
@@ -755,15 +744,12 @@ static __always_inline void debug_enter(unsigned long *dr6, unsigned long *dr7) · 6 unmodified lines
755 *744 *
756 * Keep it simple: clear DR6 immediately.745 * Keep it simple: clear DR6 immediately.
757 */746 */
758 get_debugreg(*dr6, 6);747 get_debugreg(dr6, 6);
759 set_debugreg(0, 6);748 set_debugreg(0, 6);
760 /* Filter out all the reserved bits which are preset to 1 */749 /* Filter out all the reserved bits which are preset to 1 */
761 *dr6 &= ~DR6_RESERVED;750 dr6 &= ~DR6_RESERVED;
762}
763 751
764static __always_inline void debug_exit(unsigned long dr7)752 return dr6;
765{
766 local_db_restore(dr7);
767}753}
768 754
769/*755/*
@@ -863,6 +849,18 @@ out: · 93 unmodified lines
863static __always_inline void exc_debug_kernel(struct pt_regs *regs,849static __always_inline void exc_debug_kernel(struct pt_regs *regs,
864 unsigned long dr6)850 unsigned long dr6)
865{851{
852 /*
853 * Disable breakpoints during exception handling; recursive exceptions
854 * are exceedingly 'fun'.
855 *
856 * Since this function is NOKPROBE, and that also applies to
857 * HW_BREAKPOINT_X, we can't hit a breakpoint before this (XXX except a
858 * HW_BREAKPOINT_W on our stack)
859 *
860 * Entry text is excluded for HW_BP_X and cpu_entry_area, which
861 * includes the entry stack is excluded for everything.
862 */
863 unsigned long dr7 = local_db_save();
866 bool irq_state = idtentry_enter_nmi(regs);864 bool irq_state = idtentry_enter_nmi(regs);
867 instrumentation_begin();865 instrumentation_begin();
868 866
@@ -883,6 +881,8 @@ static __always_inline void exc_debug_kernel(struct pt_regs *regs, · 14 unmodified lines
883 881
884 instrumentation_end();882 instrumentation_end();
885 idtentry_exit_nmi(regs, irq_state);883 idtentry_exit_nmi(regs, irq_state);
884
885 local_db_restore(dr7);
886}886}
887 887
888static __always_inline void exc_debug_user(struct pt_regs *regs,888static __always_inline void exc_debug_user(struct pt_regs *regs,
@@ -894,6 +894,15 @@ static __always_inline void exc_debug_user(struct pt_regs *regs, · 5 unmodified lines
894 */894 */
895 WARN_ON_ONCE(!user_mode(regs));895 WARN_ON_ONCE(!user_mode(regs));
896 896
897 /*
898 * NB: We can't easily clear DR7 here because
899 * idtentry_exit_to_usermode() can invoke ptrace, schedule, access
900 * user memory, etc. This means that a recursive #DB is possible. If
901 * this happens, that #DB will hit exc_debug_kernel() and clear DR7.
902 * Since we're not on the IST stack right now, everything will be
903 * fine.
904 */
905
897 irqentry_enter_from_user_mode(regs);906 irqentry_enter_from_user_mode(regs);
898 instrumentation_begin();907 instrumentation_begin();
899 908
@@ -907,36 +916,24 @@ static __always_inline void exc_debug_user(struct pt_regs *regs, · 7 unmodified lines
907/* IST stack entry */916/* IST stack entry */
908DEFINE_IDTENTRY_DEBUG(exc_debug)917DEFINE_IDTENTRY_DEBUG(exc_debug)
909{918{
910 unsigned long dr6, dr7;919 exc_debug_kernel(regs, debug_read_clear_dr6());
911
912 debug_enter(&dr6, &dr7);
913 exc_debug_kernel(regs, dr6);
914 debug_exit(dr7);
915}920}
916 921
917/* User entry, runs on regular task stack */922/* User entry, runs on regular task stack */
918DEFINE_IDTENTRY_DEBUG_USER(exc_debug)923DEFINE_IDTENTRY_DEBUG_USER(exc_debug)
919{924{
920 unsigned long dr6, dr7;925 exc_debug_user(regs, debug_read_clear_dr6());
921
922 debug_enter(&dr6, &dr7);
923 exc_debug_user(regs, dr6);
924 debug_exit(dr7);
925}926}
926#else927#else
927/* 32 bit does not have separate entry points. */928/* 32 bit does not have separate entry points. */
928DEFINE_IDTENTRY_RAW(exc_debug)929DEFINE_IDTENTRY_RAW(exc_debug)
929{930{
930 unsigned long dr6, dr7;931 unsigned long dr6 = debug_read_clear_dr6();
931
932 debug_enter(&dr6, &dr7);
933 932
934 if (user_mode(regs))933 if (user_mode(regs))
935 exc_debug_user(regs, dr6);934 exc_debug_user(regs, dr6);
936 else935 else
937 exc_debug_kernel(regs, dr6);936 exc_debug_kernel(regs, dr6);
938
939 debug_exit(dr7);
940}937}
941#endif938#endif
942 939
arch/x86/kernel/uprobes.c+2−2
@@ -735,7 +735,7 @@ static int branch_setup_xol_ops(struct arch_uprobe *auprobe, struct insn *insn) · 734 unmodified lines
735 * OPCODE1() of the "short" jmp which checks the same condition.735 * OPCODE1() of the "short" jmp which checks the same condition.
736 */736 */
737 opc1 = OPCODE2(insn) - 0x10;737 opc1 = OPCODE2(insn) - 0x10;
738 /* fall through */738 fallthrough;
739 default:739 default:
740 if (!is_cond_jmp_opcode(opc1))740 if (!is_cond_jmp_opcode(opc1))
741 return -ENOSYS;741 return -ENOSYS;
@@ -892,7 +892,7 @@ int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, struct mm_struct *mm, · 150 unmodified lines
892 fix_ip_or_call = 0;892 fix_ip_or_call = 0;
893 break;893 break;
894 }894 }
895 /* fall through */895 fallthrough;
896 default:896 default:
897 riprel_analyze(auprobe, &insn);897 riprel_analyze(auprobe, &insn);
898 }898 }
arch/x86/kvm/emulate.c+1−1
@@ -3016,7 +3016,7 @@ static void string_registers_quirk(struct x86_emulate_ctxt *ctxt) · 3015 unmodified lines
3016 case 0xa4: /* movsb */3016 case 0xa4: /* movsb */
3017 case 0xa5: /* movsd/w */3017 case 0xa5: /* movsd/w */
3018 *reg_rmw(ctxt, VCPU_REGS_RSI) &= (u32)-1;3018 *reg_rmw(ctxt, VCPU_REGS_RSI) &= (u32)-1;
3019 /* fall through */3019 fallthrough;
3020 case 0xaa: /* stosb */3020 case 0xaa: /* stosb */
3021 case 0xab: /* stosd/w */3021 case 0xab: /* stosd/w */
3022 *reg_rmw(ctxt, VCPU_REGS_RDI) &= (u32)-1;3022 *reg_rmw(ctxt, VCPU_REGS_RDI) &= (u32)-1;
arch/x86/kvm/hyperv.c+1−1
@@ -1779,7 +1779,7 @@ int kvm_hv_hypercall(struct kvm_vcpu *vcpu) · 1778 unmodified lines
1779 ret = kvm_hvcall_signal_event(vcpu, fast, ingpa);1779 ret = kvm_hvcall_signal_event(vcpu, fast, ingpa);
1780 if (ret != HV_STATUS_INVALID_PORT_ID)1780 if (ret != HV_STATUS_INVALID_PORT_ID)
1781 break;1781 break;
1782 /* fall through - maybe userspace knows this conn_id. */1782 fallthrough; /* maybe userspace knows this conn_id */
1783 case HVCALL_POST_MESSAGE:1783 case HVCALL_POST_MESSAGE:
1784 /* don't bother userspace if it has no way to handle it */1784 /* don't bother userspace if it has no way to handle it */
1785 if (unlikely(rep || !vcpu_to_synic(vcpu)->active)) {1785 if (unlikely(rep || !vcpu_to_synic(vcpu)->active)) {
arch/x86/kvm/irq_comm.c+1−1
@@ -285,7 +285,7 @@ int kvm_set_routing_entry(struct kvm *kvm, · 284 unmodified lines
285 switch (ue->u.irqchip.irqchip) {285 switch (ue->u.irqchip.irqchip) {
286 case KVM_IRQCHIP_PIC_SLAVE:286 case KVM_IRQCHIP_PIC_SLAVE:
287 e->irqchip.pin += PIC_NUM_PINS / 2;287 e->irqchip.pin += PIC_NUM_PINS / 2;
288 /* fall through */288 fallthrough;
289 case KVM_IRQCHIP_PIC_MASTER:289 case KVM_IRQCHIP_PIC_MASTER:
290 if (ue->u.irqchip.pin >= PIC_NUM_PINS / 2)290 if (ue->u.irqchip.pin >= PIC_NUM_PINS / 2)
291 return -EINVAL;291 return -EINVAL;
arch/x86/kvm/lapic.c+3−3
@@ -1053,7 +1053,7 @@ static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode, · 1052 unmodified lines
1053 switch (delivery_mode) {1053 switch (delivery_mode) {
1054 case APIC_DM_LOWEST:1054 case APIC_DM_LOWEST:
1055 vcpu->arch.apic_arb_prio++;1055 vcpu->arch.apic_arb_prio++;
1056 /* fall through */1056 fallthrough;
1057 case APIC_DM_FIXED:1057 case APIC_DM_FIXED:
1058 if (unlikely(trig_mode && !level))1058 if (unlikely(trig_mode && !level))
1059 break;1059 break;
@@ -1341,7 +1341,7 @@ static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset) · 281 unmodified lines
1341 break;1341 break;
1342 case APIC_TASKPRI:1342 case APIC_TASKPRI:
1343 report_tpr_access(apic, false);1343 report_tpr_access(apic, false);
1344 /* fall thru */1344 fallthrough;
1345 default:1345 default:
1346 val = kvm_lapic_get_reg(apic, offset);1346 val = kvm_lapic_get_reg(apic, offset);
1347 break;1347 break;
@@ -2027,7 +2027,7 @@ int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) · 679 unmodified lines
2027 2027
2028 case APIC_LVT0:2028 case APIC_LVT0:
2029 apic_manage_nmi_watchdog(apic, val);2029 apic_manage_nmi_watchdog(apic, val);
2030 /* fall through */2030 fallthrough;
2031 case APIC_LVTTHMR:2031 case APIC_LVTTHMR:
2032 case APIC_LVTPC:2032 case APIC_LVTPC:
2033 case APIC_LVT1:2033 case APIC_LVT1:
arch/x86/kvm/mmu/mmu.c+3−2
@@ -1916,7 +1916,8 @@ static int kvm_handle_hva(struct kvm *kvm, unsigned long hva, · 1915 unmodified lines
1916 return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler);1916 return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler);
1917}1917}
1918 1918
1919int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end)1919int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end,
1920 unsigned flags)
1920{1921{
1921 return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp);1922 return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp);
1922}1923}
@@ -4421,7 +4422,7 @@ __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, · 2498 unmodified lines
4421 rsvd_bits(maxphyaddr, 51);4422 rsvd_bits(maxphyaddr, 51);
4422 rsvd_check->rsvd_bits_mask[1][4] =4423 rsvd_check->rsvd_bits_mask[1][4] =
4423 rsvd_check->rsvd_bits_mask[0][4];4424 rsvd_check->rsvd_bits_mask[0][4];
4424 /* fall through */4425 fallthrough;
4425 case PT64_ROOT_4LEVEL:4426 case PT64_ROOT_4LEVEL:
4426 rsvd_check->rsvd_bits_mask[0][3] = exb_bit_rsvd |4427 rsvd_check->rsvd_bits_mask[0][3] = exb_bit_rsvd |
4427 nonleaf_bit8_rsvd | rsvd_bits(7, 7) |4428 nonleaf_bit8_rsvd | rsvd_bits(7, 7) |
arch/x86/kvm/svm/svm.c+1−1
@@ -2668,7 +2668,7 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) · 2667 unmodified lines
2668 case MSR_IA32_APICBASE:2668 case MSR_IA32_APICBASE:
2669 if (kvm_vcpu_apicv_active(vcpu))2669 if (kvm_vcpu_apicv_active(vcpu))
2670 avic_update_vapic_bar(to_svm(vcpu), data);2670 avic_update_vapic_bar(to_svm(vcpu), data);
2671 /* Fall through */2671 fallthrough;
2672 default:2672 default:
2673 return kvm_set_msr_common(vcpu, msr);2673 return kvm_set_msr_common(vcpu, msr);
2674 }2674 }
arch/x86/kvm/vmx/vmx.c+6−6
@@ -4654,7 +4654,7 @@ static bool rmode_exception(struct kvm_vcpu *vcpu, int vec) · 4653 unmodified lines
4654 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);4654 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4655 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)4655 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4656 return false;4656 return false;
4657 /* fall through */4657 fallthrough;
4658 case DB_VECTOR:4658 case DB_VECTOR:
4659 return !(vcpu->guest_debug &4659 return !(vcpu->guest_debug &
4660 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP));4660 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP));
@@ -4827,7 +4827,7 @@ static int handle_exception_nmi(struct kvm_vcpu *vcpu) · 166 unmodified lines
4827 }4827 }
4828 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;4828 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
4829 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);4829 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4830 /* fall through */4830 fallthrough;
4831 case BP_VECTOR:4831 case BP_VECTOR:
4832 /*4832 /*
4833 * Update instruction length as we may reinject #BP from4833 * Update instruction length as we may reinject #BP from
@@ -5257,7 +5257,7 @@ static int handle_task_switch(struct kvm_vcpu *vcpu) · 423 unmodified lines
5257 error_code =5257 error_code =
5258 vmcs_read32(IDT_VECTORING_ERROR_CODE);5258 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5259 }5259 }
5260 /* fall through */5260 fallthrough;
5261 case INTR_TYPE_SOFT_EXCEPTION:5261 case INTR_TYPE_SOFT_EXCEPTION:
5262 kvm_clear_exception_queue(vcpu);5262 kvm_clear_exception_queue(vcpu);
5263 break;5263 break;
@@ -5610,7 +5610,7 @@ static int handle_invpcid(struct kvm_vcpu *vcpu) · 346 unmodified lines
5610 * keeping track of global entries in shadow page tables.5610 * keeping track of global entries in shadow page tables.
5611 */5611 */
5612 5612
5613 /* fall-through */5613 fallthrough;
5614 case INVPCID_TYPE_ALL_INCL_GLOBAL:5614 case INVPCID_TYPE_ALL_INCL_GLOBAL:
5615 kvm_mmu_unload(vcpu);5615 kvm_mmu_unload(vcpu);
5616 return kvm_skip_emulated_instruction(vcpu);5616 return kvm_skip_emulated_instruction(vcpu);
@@ -6578,7 +6578,7 @@ static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu, · 961 unmodified lines
6578 break;6578 break;
6579 case INTR_TYPE_SOFT_EXCEPTION:6579 case INTR_TYPE_SOFT_EXCEPTION:
6580 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);6580 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6581 /* fall through */6581 fallthrough;
6582 case INTR_TYPE_HARD_EXCEPTION:6582 case INTR_TYPE_HARD_EXCEPTION:
6583 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {6583 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6584 u32 err = vmcs_read32(error_code_field);6584 u32 err = vmcs_read32(error_code_field);
@@ -6588,7 +6588,7 @@ static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu, · 3 unmodified lines
6588 break;6588 break;
6589 case INTR_TYPE_SOFT_INTR:6589 case INTR_TYPE_SOFT_INTR:
6590 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);6590 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
6591 /* fall through */6591 fallthrough;
6592 case INTR_TYPE_EXT_INTR:6592 case INTR_TYPE_EXT_INTR:
6593 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);6593 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
6594 break;6594 break;
arch/x86/kvm/x86.c+8−9
@@ -975,7 +975,7 @@ int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) · 974 unmodified lines
975{975{
976 unsigned long old_cr4 = kvm_read_cr4(vcpu);976 unsigned long old_cr4 = kvm_read_cr4(vcpu);
977 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |977 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
978 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;978 X86_CR4_SMEP;
979 979
980 if (kvm_valid_cr4(vcpu, cr4))980 if (kvm_valid_cr4(vcpu, cr4))
981 return 1;981 return 1;
@@ -1116,14 +1116,12 @@ static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) · 134 unmodified lines
1116 vcpu->arch.eff_db[dr] = val;1116 vcpu->arch.eff_db[dr] = val;
1117 break;1117 break;
1118 case 4:1118 case 4:
1119 /* fall through */
1120 case 6:1119 case 6:
1121 if (!kvm_dr6_valid(val))1120 if (!kvm_dr6_valid(val))
1122 return -1; /* #GP */1121 return -1; /* #GP */
1123 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);1122 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1124 break;1123 break;
1125 case 5:1124 case 5:
1126 /* fall through */
1127 default: /* 7 */1125 default: /* 7 */
1128 if (!kvm_dr7_valid(val))1126 if (!kvm_dr7_valid(val))
1129 return -1; /* #GP */1127 return -1; /* #GP */
@@ -1154,12 +1152,10 @@ int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) · 24 unmodified lines
1154 *val = vcpu->arch.db[array_index_nospec(dr, size)];1152 *val = vcpu->arch.db[array_index_nospec(dr, size)];
1155 break;1153 break;
1156 case 4:1154 case 4:
1157 /* fall through */
1158 case 6:1155 case 6:
1159 *val = vcpu->arch.dr6;1156 *val = vcpu->arch.dr6;
1160 break;1157 break;
1161 case 5:1158 case 5:
1162 /* fall through */
1163 default: /* 7 */1159 default: /* 7 */
1164 *val = vcpu->arch.dr7;1160 *val = vcpu->arch.dr7;
1165 break;1161 break;
@@ -3051,7 +3047,8 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) · 1885 unmodified lines
3051 3047
3052 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:3048 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3053 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:3049 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3054 pr = true; /* fall through */3050 pr = true;
3051 fallthrough;
3055 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:3052 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3056 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:3053 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3057 if (kvm_pmu_is_valid_msr(vcpu, msr))3054 if (kvm_pmu_is_valid_msr(vcpu, msr))
@@ -4359,7 +4356,7 @@ static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, · 1301 unmodified lines
4359 case KVM_CAP_HYPERV_SYNIC2:4356 case KVM_CAP_HYPERV_SYNIC2:
4360 if (cap->args[0])4357 if (cap->args[0])
4361 return -EINVAL;4358 return -EINVAL;
4362 /* fall through */4359 fallthrough;
4363 4360
4364 case KVM_CAP_HYPERV_SYNIC:4361 case KVM_CAP_HYPERV_SYNIC:
4365 if (!irqchip_in_kernel(vcpu->kvm))4362 if (!irqchip_in_kernel(vcpu->kvm))
@@ -8672,7 +8669,7 @@ static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu) · 4306 unmodified lines
8672 vcpu->arch.pv.pv_unhalted = false;8669 vcpu->arch.pv.pv_unhalted = false;
8673 vcpu->arch.mp_state =8670 vcpu->arch.mp_state =
8674 KVM_MP_STATE_RUNNABLE;8671 KVM_MP_STATE_RUNNABLE;
8675 /* fall through */8672 fallthrough;
8676 case KVM_MP_STATE_RUNNABLE:8673 case KVM_MP_STATE_RUNNABLE:
8677 vcpu->arch.apf.halted = false;8674 vcpu->arch.apf.halted = false;
8678 break;8675 break;
@@ -10751,9 +10748,11 @@ EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value); · 2072 unmodified lines
10751void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code)10748void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code)
10752{10749{
10753 struct x86_exception fault;10750 struct x86_exception fault;
10751 u32 access = error_code &
10752 (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK);
10754 10753
10755 if (!(error_code & PFERR_PRESENT_MASK) ||10754 if (!(error_code & PFERR_PRESENT_MASK) ||
10756 vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, error_code, &fault) != UNMAPPED_GVA) {10755 vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, &fault) != UNMAPPED_GVA) {
10757 /*10756 /*
10758 * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page10757 * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page
10759 * tables probably do not match the TLB. Just proceed10758 * tables probably do not match the TLB. Just proceed
arch/x86/lib/Makefile+1−1
@@ -24,7 +24,7 @@ ifdef CONFIG_FUNCTION_TRACER · 23 unmodified lines
24CFLAGS_REMOVE_cmdline.o = -pg24CFLAGS_REMOVE_cmdline.o = -pg
25endif25endif
26 26
27CFLAGS_cmdline.o := -fno-stack-protector27CFLAGS_cmdline.o := -fno-stack-protector -fno-jump-tables
28endif28endif
29 29
30inat_tables_script = $(srctree)/arch/x86/tools/gen-insn-attr-x86.awk30inat_tables_script = $(srctree)/arch/x86/tools/gen-insn-attr-x86.awk
arch/x86/lib/cmdline.c+4−4
@@ -58,7 +58,7 @@ __cmdline_find_option_bool(const char *cmdline, int max_cmdline_size, · 57 unmodified lines
58 state = st_wordcmp;58 state = st_wordcmp;
59 opptr = option;59 opptr = option;
60 wstart = pos;60 wstart = pos;
61 /* fall through */61 fallthrough;
62 62
63 case st_wordcmp:63 case st_wordcmp:
64 if (!*opptr) {64 if (!*opptr) {
@@ -89,7 +89,7 @@ __cmdline_find_option_bool(const char *cmdline, int max_cmdline_size, · 24 unmodified lines
89 break;89 break;
90 }90 }
91 state = st_wordskip;91 state = st_wordskip;
92 /* fall through */92 fallthrough;
93 93
94 case st_wordskip:94 case st_wordskip:
95 if (!c)95 if (!c)
@@ -151,7 +151,7 @@ __cmdline_find_option(const char *cmdline, int max_cmdline_size, · 55 unmodified lines
151 151
152 state = st_wordcmp;152 state = st_wordcmp;
153 opptr = option;153 opptr = option;
154 /* fall through */154 fallthrough;
155 155
156 case st_wordcmp:156 case st_wordcmp:
157 if ((c == '=') && !*opptr) {157 if ((c == '=') && !*opptr) {
@@ -172,7 +172,7 @@ __cmdline_find_option(const char *cmdline, int max_cmdline_size, · 14 unmodified lines
172 break;172 break;
173 }173 }
174 state = st_wordskip;174 state = st_wordskip;
175 /* fall through */175 fallthrough;
176 176
177 case st_wordskip:177 case st_wordskip:
178 if (myisspace(c))178 if (myisspace(c))
arch/x86/lib/insn-eval.c+2−4
@@ -179,7 +179,7 @@ static int resolve_default_seg(struct insn *insn, struct pt_regs *regs, int off) · 178 unmodified lines
179 if (insn->addr_bytes == 2)179 if (insn->addr_bytes == 2)
180 return -EINVAL;180 return -EINVAL;
181 181
182 /* fall through */182 fallthrough;
183 183
184 case -EDOM:184 case -EDOM:
185 case offsetof(struct pt_regs, bx):185 case offsetof(struct pt_regs, bx):
@@ -362,7 +362,6 @@ static short get_segment_selector(struct pt_regs *regs, int seg_reg_idx) · 176 unmodified lines
362 case INAT_SEG_REG_GS:362 case INAT_SEG_REG_GS:
363 return vm86regs->gs;363 return vm86regs->gs;
364 case INAT_SEG_REG_IGNORE:364 case INAT_SEG_REG_IGNORE:
365 /* fall through */
366 default:365 default:
367 return -EINVAL;366 return -EINVAL;
368 }367 }
@@ -386,7 +385,6 @@ static short get_segment_selector(struct pt_regs *regs, int seg_reg_idx) · 17 unmodified lines
386 */385 */
387 return get_user_gs(regs);386 return get_user_gs(regs);
388 case INAT_SEG_REG_IGNORE:387 case INAT_SEG_REG_IGNORE:
389 /* fall through */
390 default:388 default:
391 return -EINVAL;389 return -EINVAL;
392 }390 }
@@ -786,7 +784,7 @@ int insn_get_code_seg_params(struct pt_regs *regs) · 393 unmodified lines
786 */784 */
787 return INSN_CODE_SEG_PARAMS(4, 8);785 return INSN_CODE_SEG_PARAMS(4, 8);
788 case 3: /* Invalid setting. CS.L=1, CS.D=1 */786 case 3: /* Invalid setting. CS.L=1, CS.D=1 */
789 /* fall through */787 fallthrough;
790 default:788 default:
791 return -EINVAL;789 return -EINVAL;
792 }790 }
arch/x86/math-emu/errors.c+1−1
@@ -186,7 +186,7 @@ void FPU_printall(void) · 185 unmodified lines
186 case TAG_Special:186 case TAG_Special:
187 /* Update tagi for the printk below */187 /* Update tagi for the printk below */
188 tagi = FPU_Special(r);188 tagi = FPU_Special(r);
189 /* fall through */189 fallthrough;
190 case TAG_Valid:190 case TAG_Valid:
191 printk("st(%d) %c .%04lx %04lx %04lx %04lx e%+-6d ", i,191 printk("st(%d) %c .%04lx %04lx %04lx %04lx e%+-6d ", i,
192 getsign(r) ? '-' : '+',192 getsign(r) ? '-' : '+',
arch/x86/math-emu/fpu_trig.c+1−1
@@ -1352,7 +1352,7 @@ static void fyl2xp1(FPU_REG *st0_ptr, u_char st0_tag) · 1351 unmodified lines
1352 case TW_Denormal:1352 case TW_Denormal:
1353 if (denormal_operand() < 0)1353 if (denormal_operand() < 0)
1354 return;1354 return;
1355 /* fall through */1355 fallthrough;
1356 case TAG_Zero:1356 case TAG_Zero:
1357 case TAG_Valid:1357 case TAG_Valid:
1358 setsign(st0_ptr, getsign(st0_ptr) ^ getsign(st1_ptr));1358 setsign(st0_ptr, getsign(st0_ptr) ^ getsign(st1_ptr));
arch/x86/mm/fault.c+78−0
@@ -190,6 +190,53 @@ static inline pmd_t *vmalloc_sync_one(pgd_t *pgd, unsigned long address) · 189 unmodified lines
190 return pmd_k;190 return pmd_k;
191}191}
192 192
193/*
194 * Handle a fault on the vmalloc or module mapping area
195 *
196 * This is needed because there is a race condition between the time
197 * when the vmalloc mapping code updates the PMD to the point in time
198 * where it synchronizes this update with the other page-tables in the
199 * system.
200 *
201 * In this race window another thread/CPU can map an area on the same
202 * PMD, finds it already present and does not synchronize it with the
203 * rest of the system yet. As a result v[mz]alloc might return areas
204 * which are not mapped in every page-table in the system, causing an
205 * unhandled page-fault when they are accessed.
206 */
207static noinline int vmalloc_fault(unsigned long address)
208{
209 unsigned long pgd_paddr;
210 pmd_t *pmd_k;
211 pte_t *pte_k;
212
213 /* Make sure we are in vmalloc area: */
214 if (!(address >= VMALLOC_START && address < VMALLOC_END))
215 return -1;
216
217 /*
218 * Synchronize this task's top level page-table
219 * with the 'reference' page table.
220 *
221 * Do _not_ use "current" here. We might be inside
222 * an interrupt in the middle of a task switch..
223 */
224 pgd_paddr = read_cr3_pa();
225 pmd_k = vmalloc_sync_one(__va(pgd_paddr), address);
226 if (!pmd_k)
227 return -1;
228
229 if (pmd_large(*pmd_k))
230 return 0;
231
232 pte_k = pte_offset_kernel(pmd_k, address);
233 if (!pte_present(*pte_k))
234 return -1;
235
236 return 0;
237}
238NOKPROBE_SYMBOL(vmalloc_fault);
239
193void arch_sync_kernel_mappings(unsigned long start, unsigned long end)240void arch_sync_kernel_mappings(unsigned long start, unsigned long end)
194{241{
195 unsigned long addr;242 unsigned long addr;
@@ -1110,6 +1157,37 @@ do_kern_addr_fault(struct pt_regs *regs, unsigned long hw_error_code, · 914 unmodified lines
1110 */1157 */
1111 WARN_ON_ONCE(hw_error_code & X86_PF_PK);1158 WARN_ON_ONCE(hw_error_code & X86_PF_PK);
1112 1159
1160#ifdef CONFIG_X86_32
1161 /*
1162 * We can fault-in kernel-space virtual memory on-demand. The
1163 * 'reference' page table is init_mm.pgd.
1164 *
1165 * NOTE! We MUST NOT take any locks for this case. We may
1166 * be in an interrupt or a critical region, and should
1167 * only copy the information from the master page table,
1168 * nothing more.
1169 *
1170 * Before doing this on-demand faulting, ensure that the
1171 * fault is not any of the following:
1172 * 1. A fault on a PTE with a reserved bit set.
1173 * 2. A fault caused by a user-mode access. (Do not demand-
1174 * fault kernel memory due to user-mode accesses).
1175 * 3. A fault caused by a page-level protection violation.
1176 * (A demand fault would be on a non-present page which
1177 * would have X86_PF_PROT==0).
1178 *
1179 * This is only needed to close a race condition on x86-32 in
1180 * the vmalloc mapping/unmapping code. See the comment above
1181 * vmalloc_fault() for details. On x86-64 the race does not
1182 * exist as the vmalloc mappings don't need to be synchronized
1183 * there.
1184 */
1185 if (!(hw_error_code & (X86_PF_RSVD | X86_PF_USER | X86_PF_PROT))) {
1186 if (vmalloc_fault(address) >= 0)
1187 return;
1188 }
1189#endif
1190
1113 /* Was the fault spurious, caused by lazy TLB invalidation? */1191 /* Was the fault spurious, caused by lazy TLB invalidation? */
1114 if (spurious_kernel_fault(hw_error_code, address))1192 if (spurious_kernel_fault(hw_error_code, address))
1115 return;1193 return;
arch/x86/mm/ioremap.c+1−1
@@ -574,7 +574,7 @@ static bool memremap_should_map_decrypted(resource_size_t phys_addr, · 573 unmodified lines
574 /* For SEV, these areas are encrypted */574 /* For SEV, these areas are encrypted */
575 if (sev_active())575 if (sev_active())
576 break;576 break;
577 /* Fallthrough */577 fallthrough;
578 578
579 case E820_TYPE_PRAM:579 case E820_TYPE_PRAM:
580 return true;580 return true;
arch/x86/mm/numa_emulation.c+1−1
@@ -321,7 +321,7 @@ static int __init split_nodes_size_interleave(struct numa_meminfo *ei, · 320 unmodified lines
321 u64 addr, u64 max_addr, u64 size)321 u64 addr, u64 max_addr, u64 size)
322{322{
323 return split_nodes_size_interleave_uniform(ei, pi, addr, max_addr, size,323 return split_nodes_size_interleave_uniform(ei, pi, addr, max_addr, size,
324 0, NULL, NUMA_NO_NODE);324 0, NULL, 0);
325}325}
326 326
327static int __init setup_emu2phys_nid(int *dfl_phys_nid)327static int __init setup_emu2phys_nid(int *dfl_phys_nid)
arch/x86/mm/tlb.c+2−11
@@ -555,21 +555,12 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next, · 554 unmodified lines
555 this_cpu_write(cpu_tlbstate.ctxs[new_asid].tlb_gen, next_tlb_gen);555 this_cpu_write(cpu_tlbstate.ctxs[new_asid].tlb_gen, next_tlb_gen);
556 load_new_mm_cr3(next->pgd, new_asid, true);556 load_new_mm_cr3(next->pgd, new_asid, true);
557 557
558 /*558 trace_tlb_flush(TLB_FLUSH_ON_TASK_SWITCH, TLB_FLUSH_ALL);
559 * NB: This gets called via leave_mm() in the idle path
560 * where RCU functions differently. Tracing normally
561 * uses RCU, so we need to use the _rcuidle variant.
562 *
563 * (There is no good reason for this. The idle code should
564 * be rearranged to call this before rcu_idle_enter().)
565 */
566 trace_tlb_flush_rcuidle(TLB_FLUSH_ON_TASK_SWITCH, TLB_FLUSH_ALL);
567 } else {559 } else {
568 /* The new ASID is already up to date. */560 /* The new ASID is already up to date. */
569 load_new_mm_cr3(next->pgd, new_asid, false);561 load_new_mm_cr3(next->pgd, new_asid, false);
570 562
571 /* See above wrt _rcuidle. */563 trace_tlb_flush(TLB_FLUSH_ON_TASK_SWITCH, 0);
572 trace_tlb_flush_rcuidle(TLB_FLUSH_ON_TASK_SWITCH, 0);
573 }564 }
574 565
575 /* Make sure we write CR3 before loaded_mm. */566 /* Make sure we write CR3 before loaded_mm. */
arch/x86/pci/xen.c+1−0
@@ -26,6 +26,7 @@ · 25 unmodified lines
26#include <asm/xen/pci.h>26#include <asm/xen/pci.h>
27#include <asm/xen/cpuid.h>27#include <asm/xen/cpuid.h>
28#include <asm/apic.h>28#include <asm/apic.h>
29#include <asm/acpi.h>
29#include <asm/i8259.h>30#include <asm/i8259.h>
30 31
31static int xen_pcifront_enable_irq(struct pci_dev *dev)32static int xen_pcifront_enable_irq(struct pci_dev *dev)
arch/x86/platform/efi/efi.c+0−69
@@ -49,7 +49,6 @@ · 48 unmodified lines
49#include <asm/efi.h>49#include <asm/efi.h>
50#include <asm/e820/api.h>50#include <asm/e820/api.h>
51#include <asm/time.h>51#include <asm/time.h>
52#include <asm/set_memory.h>
53#include <asm/tlbflush.h>52#include <asm/tlbflush.h>
54#include <asm/x86_init.h>53#include <asm/x86_init.h>
55#include <asm/uv/uv.h>54#include <asm/uv/uv.h>
@@ -496,74 +495,6 @@ void __init efi_init(void) · 440 unmodified lines
496 efi_print_memmap();495 efi_print_memmap();
497}496}
498 497
499#if defined(CONFIG_X86_32)
500
501void __init efi_set_executable(efi_memory_desc_t *md, bool executable)
502{
503 u64 addr, npages;
504
505 addr = md->virt_addr;
506 npages = md->num_pages;
507
508 memrange_efi_to_native(&addr, &npages);
509
510 if (executable)
511 set_memory_x(addr, npages);
512 else
513 set_memory_nx(addr, npages);
514}
515
516void __init runtime_code_page_mkexec(void)
517{
518 efi_memory_desc_t *md;
519
520 /* Make EFI runtime service code area executable */
521 for_each_efi_memory_desc(md) {
522 if (md->type != EFI_RUNTIME_SERVICES_CODE)
523 continue;
524
525 efi_set_executable(md, true);
526 }
527}
528
529void __init efi_memory_uc(u64 addr, unsigned long size)
530{
531 unsigned long page_shift = 1UL << EFI_PAGE_SHIFT;
532 u64 npages;
533
534 npages = round_up(size, page_shift) / page_shift;
535 memrange_efi_to_native(&addr, &npages);
536 set_memory_uc(addr, npages);
537}
538
539void __init old_map_region(efi_memory_desc_t *md)
540{
541 u64 start_pfn, end_pfn, end;
542 unsigned long size;
543 void *va;
544
545 start_pfn = PFN_DOWN(md->phys_addr);
546 size = md->num_pages << PAGE_SHIFT;
547 end = md->phys_addr + size;
548 end_pfn = PFN_UP(end);
549
550 if (pfn_range_is_mapped(start_pfn, end_pfn)) {
551 va = __va(md->phys_addr);
552
553 if (!(md->attribute & EFI_MEMORY_WB))
554 efi_memory_uc((u64)(unsigned long)va, size);
555 } else
556 va = efi_ioremap(md->phys_addr, size,
557 md->type, md->attribute);
558
559 md->virt_addr = (u64) (unsigned long) va;
560 if (!va)
561 pr_err("ioremap of 0x%llX failed!\n",
562 (unsigned long long)md->phys_addr);
563}
564
565#endif
566
567/* Merge contiguous regions of the same type and attribute */498/* Merge contiguous regions of the same type and attribute */
568static void __init efi_merge_regions(void)499static void __init efi_merge_regions(void)
569{500{
arch/x86/platform/efi/efi_32.c+37−7
@@ -29,9 +29,35 @@ · 28 unmodified lines
29#include <asm/io.h>29#include <asm/io.h>
30#include <asm/desc.h>30#include <asm/desc.h>
31#include <asm/page.h>31#include <asm/page.h>
32#include <asm/set_memory.h>
32#include <asm/tlbflush.h>33#include <asm/tlbflush.h>
33#include <asm/efi.h>34#include <asm/efi.h>
34 35
36void __init efi_map_region(efi_memory_desc_t *md)
37{
38 u64 start_pfn, end_pfn, end;
39 unsigned long size;
40 void *va;
41
42 start_pfn = PFN_DOWN(md->phys_addr);
43 size = md->num_pages << PAGE_SHIFT;
44 end = md->phys_addr + size;
45 end_pfn = PFN_UP(end);
46
47 if (pfn_range_is_mapped(start_pfn, end_pfn)) {
48 va = __va(md->phys_addr);
49
50 if (!(md->attribute & EFI_MEMORY_WB))
51 set_memory_uc((unsigned long)va, md->num_pages);
52 } else {
53 va = ioremap_cache(md->phys_addr, size);
54 }
55
56 md->virt_addr = (unsigned long)va;
57 if (!va)
58 pr_err("ioremap of 0x%llX failed!\n", md->phys_addr);
59}
60
35/*61/*
36 * To make EFI call EFI runtime service in physical addressing mode we need62 * To make EFI call EFI runtime service in physical addressing mode we need
37 * prolog/epilog before/after the invocation to claim the EFI runtime service63 * prolog/epilog before/after the invocation to claim the EFI runtime service
@@ -58,11 +84,6 @@ int __init efi_setup_page_tables(unsigned long pa_memmap, unsigned num_pages) · 20 unmodified lines
58 return 0;84 return 0;
59}85}
60 86
61void __init efi_map_region(efi_memory_desc_t *md)
62{
63 old_map_region(md);
64}
65
66void __init efi_map_region_fixed(efi_memory_desc_t *md) {}87void __init efi_map_region_fixed(efi_memory_desc_t *md) {}
67void __init parse_efi_setup(u64 phys_addr, u32 data_len) {}88void __init parse_efi_setup(u64 phys_addr, u32 data_len) {}
68 89
@@ -107,6 +128,15 @@ efi_status_t __init efi_set_virtual_address_map(unsigned long memory_map_size, · 38 unmodified lines
107 128
108void __init efi_runtime_update_mappings(void)129void __init efi_runtime_update_mappings(void)
109{130{
110 if (__supported_pte_mask & _PAGE_NX)131 if (__supported_pte_mask & _PAGE_NX) {
111 runtime_code_page_mkexec();132 efi_memory_desc_t *md;
133
134 /* Make EFI runtime service code area executable */
135 for_each_efi_memory_desc(md) {
136 if (md->type != EFI_RUNTIME_SERVICES_CODE)
137 continue;
138
139 set_memory_x(md->virt_addr, md->num_pages);
140 }
141 }
112}142}
arch/x86/platform/efi/efi_64.c+2−0
@@ -259,6 +259,8 @@ int __init efi_setup_page_tables(unsigned long pa_memmap, unsigned num_pages) · 258 unmodified lines
259 npages = (__end_rodata - __start_rodata) >> PAGE_SHIFT;259 npages = (__end_rodata - __start_rodata) >> PAGE_SHIFT;
260 rodata = __pa(__start_rodata);260 rodata = __pa(__start_rodata);
261 pfn = rodata >> PAGE_SHIFT;261 pfn = rodata >> PAGE_SHIFT;
262
263 pf = _PAGE_NX | _PAGE_ENC;
262 if (kernel_map_pages_in_pgd(pgd, pfn, rodata, npages, pf)) {264 if (kernel_map_pages_in_pgd(pgd, pfn, rodata, npages, pf)) {
263 pr_err("Failed to map kernel rodata 1:1\n");265 pr_err("Failed to map kernel rodata 1:1\n");
264 return 1;266 return 1;
arch/xtensa/kernel/signal.c+1−1
@@ -448,7 +448,7 @@ static void do_signal(struct pt_regs *regs) · 447 unmodified lines
448 regs->areg[2] = -EINTR;448 regs->areg[2] = -EINTR;
449 break;449 break;
450 }450 }
451 /* fallthrough */451 fallthrough;
452 case -ERESTARTNOINTR:452 case -ERESTARTNOINTR:
453 regs->areg[2] = regs->syscall;453 regs->areg[2] = regs->syscall;
454 regs->pc -= 3;454 regs->pc -= 3;
block/badblocks.c+1−1
@@ -525,7 +525,7 @@ ssize_t badblocks_store(struct badblocks *bb, const char *page, size_t len, · 524 unmodified lines
525 case 3:525 case 3:
526 if (newline != '\n')526 if (newline != '\n')
527 return -EINVAL;527 return -EINVAL;
528 /* fall through */528 fallthrough;
529 case 2:529 case 2:
530 if (length <= 0)530 if (length <= 0)
531 return -EINVAL;531 return -EINVAL;
block/bfq-cgroup.c+1−1
@@ -332,7 +332,7 @@ static void bfqg_put(struct bfq_group *bfqg) · 331 unmodified lines
332 kfree(bfqg);332 kfree(bfqg);
333}333}
334 334
335void bfqg_and_blkg_get(struct bfq_group *bfqg)335static void bfqg_and_blkg_get(struct bfq_group *bfqg)
336{336{
337 /* see comments in bfq_bic_update_cgroup for why refcounting bfqg */337 /* see comments in bfq_bic_update_cgroup for why refcounting bfqg */
338 bfqg_get(bfqg);338 bfqg_get(bfqg);
block/bfq-iosched.c+2−2
@@ -4980,7 +4980,7 @@ bfq_set_next_ioprio_data(struct bfq_queue *bfqq, struct bfq_io_cq *bic) · 4979 unmodified lines
4980 pr_err("bdi %s: bfq: bad prio class %d\n",4980 pr_err("bdi %s: bfq: bad prio class %d\n",
4981 bdi_dev_name(bfqq->bfqd->queue->backing_dev_info),4981 bdi_dev_name(bfqq->bfqd->queue->backing_dev_info),
4982 ioprio_class);4982 ioprio_class);
4983 /* fall through */4983 fallthrough;
4984 case IOPRIO_CLASS_NONE:4984 case IOPRIO_CLASS_NONE:
4985 /*4985 /*
4986 * No prio set, inherit CPU scheduling settings.4986 * No prio set, inherit CPU scheduling settings.
@@ -5112,7 +5112,7 @@ static struct bfq_queue **bfq_async_queue_prio(struct bfq_data *bfqd, · 125 unmodified lines
5112 return &bfqg->async_bfqq[0][ioprio];5112 return &bfqg->async_bfqq[0][ioprio];
5113 case IOPRIO_CLASS_NONE:5113 case IOPRIO_CLASS_NONE:
5114 ioprio = IOPRIO_NORM;5114 ioprio = IOPRIO_NORM;
5115 /* fall through */5115 fallthrough;
5116 case IOPRIO_CLASS_BE:5116 case IOPRIO_CLASS_BE:
5117 return &bfqg->async_bfqq[1][ioprio];5117 return &bfqg->async_bfqq[1][ioprio];
5118 case IOPRIO_CLASS_IDLE:5118 case IOPRIO_CLASS_IDLE:
block/bfq-iosched.h+0−1
@@ -986,7 +986,6 @@ struct bfq_group *bfq_find_set_group(struct bfq_data *bfqd, · 985 unmodified lines
986struct blkcg_gq *bfqg_to_blkg(struct bfq_group *bfqg);986struct blkcg_gq *bfqg_to_blkg(struct bfq_group *bfqg);
987struct bfq_group *bfqq_group(struct bfq_queue *bfqq);987struct bfq_group *bfqq_group(struct bfq_queue *bfqq);
988struct bfq_group *bfq_create_group_hierarchy(struct bfq_data *bfqd, int node);988struct bfq_group *bfq_create_group_hierarchy(struct bfq_data *bfqd, int node);
989void bfqg_and_blkg_get(struct bfq_group *bfqg);
990void bfqg_and_blkg_put(struct bfq_group *bfqg);989void bfqg_and_blkg_put(struct bfq_group *bfqg);
991 990
992#ifdef CONFIG_BFQ_GROUP_IOSCHED991#ifdef CONFIG_BFQ_GROUP_IOSCHED
block/bfq-wf2q.c+2−10
@@ -533,9 +533,7 @@ static void bfq_get_entity(struct bfq_entity *entity) · 532 unmodified lines
533 bfqq->ref++;533 bfqq->ref++;
534 bfq_log_bfqq(bfqq->bfqd, bfqq, "get_entity: %p %d",534 bfq_log_bfqq(bfqq->bfqd, bfqq, "get_entity: %p %d",
535 bfqq, bfqq->ref);535 bfqq, bfqq->ref);
536 } else536 }
537 bfqg_and_blkg_get(container_of(entity, struct bfq_group,
538 entity));
539}537}
540 538
541/**539/**
@@ -649,14 +647,8 @@ static void bfq_forget_entity(struct bfq_service_tree *st, · 107 unmodified lines
649 647
650 entity->on_st_or_in_serv = false;648 entity->on_st_or_in_serv = false;
651 st->wsum -= entity->weight;649 st->wsum -= entity->weight;
652 if (is_in_service)650 if (bfqq && !is_in_service)
653 return;
654
655 if (bfqq)
656 bfq_put_queue(bfqq);651 bfq_put_queue(bfqq);
657 else
658 bfqg_and_blkg_put(container_of(entity, struct bfq_group,
659 entity));
660}652}
661 653
662/**654/**
block/bio.c+5−5
@@ -740,8 +740,8 @@ static inline bool page_is_mergeable(const struct bio_vec *bv, · 739 unmodified lines
740 struct page *page, unsigned int len, unsigned int off,740 struct page *page, unsigned int len, unsigned int off,
741 bool *same_page)741 bool *same_page)
742{742{
743 phys_addr_t vec_end_addr = page_to_phys(bv->bv_page) +743 size_t bv_end = bv->bv_offset + bv->bv_len;
744 bv->bv_offset + bv->bv_len - 1;744 phys_addr_t vec_end_addr = page_to_phys(bv->bv_page) + bv_end - 1;
745 phys_addr_t page_addr = page_to_phys(page);745 phys_addr_t page_addr = page_to_phys(page);
746 746
747 if (vec_end_addr + 1 != page_addr + off)747 if (vec_end_addr + 1 != page_addr + off)
@@ -750,9 +750,9 @@ static inline bool page_is_mergeable(const struct bio_vec *bv, · 2 unmodified lines
750 return false;750 return false;
751 751
752 *same_page = ((vec_end_addr & PAGE_MASK) == page_addr);752 *same_page = ((vec_end_addr & PAGE_MASK) == page_addr);
753 if (!*same_page && pfn_to_page(PFN_DOWN(vec_end_addr)) + 1 != page)753 if (*same_page)
754 return false;754 return true;
755 return true;755 return (bv->bv_page + bv_end / PAGE_SIZE) == (page + off / PAGE_SIZE);
756}756}
757 757
758/*758/*
block/blk-cgroup.c+5−3
@@ -1152,13 +1152,15 @@ int blkcg_init_queue(struct request_queue *q) · 1151 unmodified lines
1152 if (preloaded)1152 if (preloaded)
1153 radix_tree_preload_end();1153 radix_tree_preload_end();
1154 1154
1155 ret = blk_iolatency_init(q);1155 ret = blk_throtl_init(q);
1156 if (ret)1156 if (ret)
1157 goto err_destroy_all;1157 goto err_destroy_all;
1158 1158
1159 ret = blk_throtl_init(q);1159 ret = blk_iolatency_init(q);
1160 if (ret)1160 if (ret) {
1161 blk_throtl_exit(q);
1161 goto err_destroy_all;1162 goto err_destroy_all;
1163 }
1162 return 0;1164 return 0;
1163 1165
1164err_destroy_all:1166err_destroy_all:
block/blk-core.c+1−0
@@ -539,6 +539,7 @@ struct request_queue *blk_alloc_queue(int node_id) · 538 unmodified lines
539 goto fail_stats;539 goto fail_stats;
540 540
541 q->backing_dev_info->ra_pages = VM_READAHEAD_PAGES;541 q->backing_dev_info->ra_pages = VM_READAHEAD_PAGES;
542 q->backing_dev_info->io_pages = VM_READAHEAD_PAGES;
542 q->backing_dev_info->capabilities = BDI_CAP_CGROUP_WRITEBACK;543 q->backing_dev_info->capabilities = BDI_CAP_CGROUP_WRITEBACK;
543 q->node = node_id;544 q->node = node_id;
544 545
block/blk-iocost.c+3−2
@@ -2092,14 +2092,15 @@ static void ioc_pd_free(struct blkg_policy_data *pd) · 2091 unmodified lines
2092{2092{
2093 struct ioc_gq *iocg = pd_to_iocg(pd);2093 struct ioc_gq *iocg = pd_to_iocg(pd);
2094 struct ioc *ioc = iocg->ioc;2094 struct ioc *ioc = iocg->ioc;
2095 unsigned long flags;
2095 2096
2096 if (ioc) {2097 if (ioc) {
2097 spin_lock(&ioc->lock);2098 spin_lock_irqsave(&ioc->lock, flags);
2098 if (!list_empty(&iocg->active_list)) {2099 if (!list_empty(&iocg->active_list)) {
2099 propagate_active_weight(iocg, 0, 0);2100 propagate_active_weight(iocg, 0, 0);
2100 list_del_init(&iocg->active_list);2101 list_del_init(&iocg->active_list);
2101 }2102 }
2102 spin_unlock(&ioc->lock);2103 spin_unlock_irqrestore(&ioc->lock, flags);
2103 2104
2104 hrtimer_cancel(&iocg->waitq_timer);2105 hrtimer_cancel(&iocg->waitq_timer);
2105 hrtimer_cancel(&iocg->delay_timer);2106 hrtimer_cancel(&iocg->delay_timer);
block/blk-merge.c+10−3
@@ -154,7 +154,7 @@ static inline unsigned get_max_io_size(struct request_queue *q, · 153 unmodified lines
154 if (max_sectors > start_offset)154 if (max_sectors > start_offset)
155 return max_sectors - start_offset;155 return max_sectors - start_offset;
156 156
157 return sectors & (lbs - 1);157 return sectors & ~(lbs - 1);
158}158}
159 159
160static inline unsigned get_max_segment_size(const struct request_queue *q,160static inline unsigned get_max_segment_size(const struct request_queue *q,
@@ -533,10 +533,17 @@ int __blk_rq_map_sg(struct request_queue *q, struct request *rq, · 372 unmodified lines
533}533}
534EXPORT_SYMBOL(__blk_rq_map_sg);534EXPORT_SYMBOL(__blk_rq_map_sg);
535 535
536static inline unsigned int blk_rq_get_max_segments(struct request *rq)
537{
538 if (req_op(rq) == REQ_OP_DISCARD)
539 return queue_max_discard_segments(rq->q);
540 return queue_max_segments(rq->q);
541}
542
536static inline int ll_new_hw_segment(struct request *req, struct bio *bio,543static inline int ll_new_hw_segment(struct request *req, struct bio *bio,
537 unsigned int nr_phys_segs)544 unsigned int nr_phys_segs)
538{545{
539 if (req->nr_phys_segments + nr_phys_segs > queue_max_segments(req->q))546 if (req->nr_phys_segments + nr_phys_segs > blk_rq_get_max_segments(req))
540 goto no_merge;547 goto no_merge;
541 548
542 if (blk_integrity_merge_bio(req->q, req, bio) == false)549 if (blk_integrity_merge_bio(req->q, req, bio) == false)
@@ -624,7 +631,7 @@ static int ll_merge_requests_fn(struct request_queue *q, struct request *req, · 81 unmodified lines
624 return 0;631 return 0;
625 632
626 total_phys_segments = req->nr_phys_segments + next->nr_phys_segments;633 total_phys_segments = req->nr_phys_segments + next->nr_phys_segments;
627 if (total_phys_segments > queue_max_segments(q))634 if (total_phys_segments > blk_rq_get_max_segments(req))
628 return 0;635 return 0;
629 636
630 if (blk_integrity_merge_rq(q, req, next) == false)637 if (blk_integrity_merge_rq(q, req, next) == false)
block/blk-mq-sched.c+9−0
@@ -78,6 +78,15 @@ void blk_mq_sched_restart(struct blk_mq_hw_ctx *hctx) · 77 unmodified lines
78 return;78 return;
79 clear_bit(BLK_MQ_S_SCHED_RESTART, &hctx->state);79 clear_bit(BLK_MQ_S_SCHED_RESTART, &hctx->state);
80 80
81 /*
82 * Order clearing SCHED_RESTART and list_empty_careful(&hctx->dispatch)
83 * in blk_mq_run_hw_queue(). Its pair is the barrier in
84 * blk_mq_dispatch_rq_list(). So dispatch code won't see SCHED_RESTART,
85 * meantime new request added to hctx->dispatch is missed to check in
86 * blk_mq_run_hw_queue().
87 */
88 smp_mb();
89
81 blk_mq_run_hw_queue(hctx, true);90 blk_mq_run_hw_queue(hctx, true);
82}91}
83 92
block/blk-mq.c+12−1
@@ -1437,6 +1437,15 @@ out: · 1436 unmodified lines
1437 list_splice_tail_init(list, &hctx->dispatch);1437 list_splice_tail_init(list, &hctx->dispatch);
1438 spin_unlock(&hctx->lock);1438 spin_unlock(&hctx->lock);
1439 1439
1440 /*
1441 * Order adding requests to hctx->dispatch and checking
1442 * SCHED_RESTART flag. The pair of this smp_mb() is the one
1443 * in blk_mq_sched_restart(). Avoid restart code path to
1444 * miss the new added requests to hctx->dispatch, meantime
1445 * SCHED_RESTART is observed here.
1446 */
1447 smp_mb();
1448
1440 /*1449 /*
1441 * If SCHED_RESTART was set by the caller of this function and1450 * If SCHED_RESTART was set by the caller of this function and
1442 * it is no longer set that means that it was cleared by another1451 * it is no longer set that means that it was cleared by another
@@ -1834,6 +1843,7 @@ void __blk_mq_insert_request(struct blk_mq_hw_ctx *hctx, struct request *rq, · 391 unmodified lines
1834/**1843/**
1835 * blk_mq_request_bypass_insert - Insert a request at dispatch list.1844 * blk_mq_request_bypass_insert - Insert a request at dispatch list.
1836 * @rq: Pointer to request to be inserted.1845 * @rq: Pointer to request to be inserted.
1846 * @at_head: true if the request should be inserted at the head of the list.
1837 * @run_queue: If we should run the hardware queue after inserting the request.1847 * @run_queue: If we should run the hardware queue after inserting the request.
1838 *1848 *
1839 * Should only be used carefully, when the caller knows we want to1849 * Should only be used carefully, when the caller knows we want to
@@ -2016,7 +2026,8 @@ insert: · 176 unmodified lines
2016 if (bypass_insert)2026 if (bypass_insert)
2017 return BLK_STS_RESOURCE;2027 return BLK_STS_RESOURCE;
2018 2028
2019 blk_mq_request_bypass_insert(rq, false, run_queue);2029 blk_mq_sched_insert_request(rq, false, run_queue, false);
2030
2020 return BLK_STS_OK;2031 return BLK_STS_OK;
2021}2032}
2022 2033
block/blk-stat.c+11−6
@@ -137,6 +137,7 @@ void blk_stat_add_callback(struct request_queue *q, · 136 unmodified lines
137 struct blk_stat_callback *cb)137 struct blk_stat_callback *cb)
138{138{
139 unsigned int bucket;139 unsigned int bucket;
140 unsigned long flags;
140 int cpu;141 int cpu;
141 142
142 for_each_possible_cpu(cpu) {143 for_each_possible_cpu(cpu) {
@@ -147,20 +148,22 @@ void blk_stat_add_callback(struct request_queue *q, · 4 unmodified lines
147 blk_rq_stat_init(&cpu_stat[bucket]);148 blk_rq_stat_init(&cpu_stat[bucket]);
148 }149 }
149 150
150 spin_lock(&q->stats->lock);151 spin_lock_irqsave(&q->stats->lock, flags);
151 list_add_tail_rcu(&cb->list, &q->stats->callbacks);152 list_add_tail_rcu(&cb->list, &q->stats->callbacks);
152 blk_queue_flag_set(QUEUE_FLAG_STATS, q);153 blk_queue_flag_set(QUEUE_FLAG_STATS, q);
153 spin_unlock(&q->stats->lock);154 spin_unlock_irqrestore(&q->stats->lock, flags);
154}155}
155 156
156void blk_stat_remove_callback(struct request_queue *q,157void blk_stat_remove_callback(struct request_queue *q,
157 struct blk_stat_callback *cb)158 struct blk_stat_callback *cb)
158{159{
159 spin_lock(&q->stats->lock);160 unsigned long flags;
161
162 spin_lock_irqsave(&q->stats->lock, flags);
160 list_del_rcu(&cb->list);163 list_del_rcu(&cb->list);
161 if (list_empty(&q->stats->callbacks) && !q->stats->enable_accounting)164 if (list_empty(&q->stats->callbacks) && !q->stats->enable_accounting)
162 blk_queue_flag_clear(QUEUE_FLAG_STATS, q);165 blk_queue_flag_clear(QUEUE_FLAG_STATS, q);
163 spin_unlock(&q->stats->lock);166 spin_unlock_irqrestore(&q->stats->lock, flags);
164 167
165 del_timer_sync(&cb->timer);168 del_timer_sync(&cb->timer);
166}169}
@@ -183,10 +186,12 @@ void blk_stat_free_callback(struct blk_stat_callback *cb) · 16 unmodified lines
183 186
184void blk_stat_enable_accounting(struct request_queue *q)187void blk_stat_enable_accounting(struct request_queue *q)
185{188{
186 spin_lock(&q->stats->lock);189 unsigned long flags;
190
191 spin_lock_irqsave(&q->stats->lock, flags);
187 q->stats->enable_accounting = true;192 q->stats->enable_accounting = true;
188 blk_queue_flag_set(QUEUE_FLAG_STATS, q);193 blk_queue_flag_set(QUEUE_FLAG_STATS, q);
189 spin_unlock(&q->stats->lock);194 spin_unlock_irqrestore(&q->stats->lock, flags);
190}195}
191EXPORT_SYMBOL_GPL(blk_stat_enable_accounting);196EXPORT_SYMBOL_GPL(blk_stat_enable_accounting);
192 197
block/blk-wbt.c+1−1
@@ -528,7 +528,7 @@ static inline bool wbt_should_throttle(struct rq_wb *rwb, struct bio *bio) · 527 unmodified lines
528 if ((bio->bi_opf & (REQ_SYNC | REQ_IDLE)) ==528 if ((bio->bi_opf & (REQ_SYNC | REQ_IDLE)) ==
529 (REQ_SYNC | REQ_IDLE))529 (REQ_SYNC | REQ_IDLE))
530 return false;530 return false;
531 /* fallthrough */531 fallthrough;
532 case REQ_OP_DISCARD:532 case REQ_OP_DISCARD:
533 return true;533 return true;
534 default:534 default:
block/bsg-lib.c+1−1
@@ -378,7 +378,7 @@ struct request_queue *bsg_setup_queue(struct device *dev, const char *name, · 377 unmodified lines
378 bset->timeout_fn = timeout;378 bset->timeout_fn = timeout;
379 379
380 set = &bset->tag_set;380 set = &bset->tag_set;
381 set->ops = &bsg_mq_ops,381 set->ops = &bsg_mq_ops;
382 set->nr_hw_queues = 1;382 set->nr_hw_queues = 1;
383 set->queue_depth = 128;383 set->queue_depth = 128;
384 set->numa_node = NUMA_NO_NODE;384 set->numa_node = NUMA_NO_NODE;
block/ioprio.c+1−1
@@ -71,7 +71,7 @@ int ioprio_check_cap(int ioprio) · 70 unmodified lines
71 case IOPRIO_CLASS_RT:71 case IOPRIO_CLASS_RT:
72 if (!capable(CAP_SYS_ADMIN))72 if (!capable(CAP_SYS_ADMIN))
73 return -EPERM;73 return -EPERM;
74 /* fall through */74 fallthrough;
75 /* rt has prio field too */75 /* rt has prio field too */
76 case IOPRIO_CLASS_BE:76 case IOPRIO_CLASS_BE:
77 if (data >= IOPRIO_BE_NR || data < 0)77 if (data >= IOPRIO_BE_NR || data < 0)
block/partitions/core.c+22−15
@@ -278,6 +278,15 @@ static void hd_struct_free_work(struct work_struct *work) · 277 unmodified lines
278{278{
279 struct hd_struct *part =279 struct hd_struct *part =
280 container_of(to_rcu_work(work), struct hd_struct, rcu_work);280 container_of(to_rcu_work(work), struct hd_struct, rcu_work);
281 struct gendisk *disk = part_to_disk(part);
282
283 /*
284 * Release the disk reference acquired in delete_partition here.
285 * We can't release it in hd_struct_free because the final put_device
286 * needs process context and thus can't be run directly from a
287 * percpu_ref ->release handler.
288 */
289 put_device(disk_to_dev(disk));
281 290
282 part->start_sect = 0;291 part->start_sect = 0;
283 part->nr_sects = 0;292 part->nr_sects = 0;
@@ -293,7 +302,6 @@ static void hd_struct_free(struct percpu_ref *ref) · 9 unmodified lines
293 rcu_dereference_protected(disk->part_tbl, 1);302 rcu_dereference_protected(disk->part_tbl, 1);
294 303
295 rcu_assign_pointer(ptbl->last_lookup, NULL);304 rcu_assign_pointer(ptbl->last_lookup, NULL);
296 put_device(disk_to_dev(disk));
297 305
298 INIT_RCU_WORK(&part->rcu_work, hd_struct_free_work);306 INIT_RCU_WORK(&part->rcu_work, hd_struct_free_work);
299 queue_rcu_work(system_wq, &part->rcu_work);307 queue_rcu_work(system_wq, &part->rcu_work);
@@ -524,19 +532,20 @@ int bdev_add_partition(struct block_device *bdev, int partno, · 224 unmodified lines
524int bdev_del_partition(struct block_device *bdev, int partno)532int bdev_del_partition(struct block_device *bdev, int partno)
525{533{
526 struct block_device *bdevp;534 struct block_device *bdevp;
527 struct hd_struct *part;535 struct hd_struct *part = NULL;
528 int ret = 0;536 int ret;
529 537
530 part = disk_get_part(bdev->bd_disk, partno);538 bdevp = bdget_disk(bdev->bd_disk, partno);
531 if (!part)
532 return -ENXIO;
533
534 ret = -ENOMEM;
535 bdevp = bdget(part_devt(part));
536 if (!bdevp)539 if (!bdevp)
537 goto out_put_part;540 return -ENOMEM;
538 541
539 mutex_lock(&bdevp->bd_mutex);542 mutex_lock(&bdevp->bd_mutex);
543 mutex_lock_nested(&bdev->bd_mutex, 1);
544
545 ret = -ENXIO;
546 part = disk_get_part(bdev->bd_disk, partno);
547 if (!part)
548 goto out_unlock;
540 549
541 ret = -EBUSY;550 ret = -EBUSY;
542 if (bdevp->bd_openers)551 if (bdevp->bd_openers)
@@ -545,16 +554,14 @@ int bdev_del_partition(struct block_device *bdev, int partno) · 2 unmodified lines
545 sync_blockdev(bdevp);554 sync_blockdev(bdevp);
546 invalidate_bdev(bdevp);555 invalidate_bdev(bdevp);
547 556
548 mutex_lock_nested(&bdev->bd_mutex, 1);
549 delete_partition(bdev->bd_disk, part);557 delete_partition(bdev->bd_disk, part);
550 mutex_unlock(&bdev->bd_mutex);
551
552 ret = 0;558 ret = 0;
553out_unlock:559out_unlock:
560 mutex_unlock(&bdev->bd_mutex);
554 mutex_unlock(&bdevp->bd_mutex);561 mutex_unlock(&bdevp->bd_mutex);
555 bdput(bdevp);562 bdput(bdevp);
556out_put_part:563 if (part)
557 disk_put_part(part);564 disk_put_part(part);
558 return ret;565 return ret;
559}566}
560 567
crypto/af_alg.c+10−3
@@ -16,6 +16,7 @@ · 15 unmodified lines
16#include <linux/module.h>16#include <linux/module.h>
17#include <linux/net.h>17#include <linux/net.h>
18#include <linux/rwsem.h>18#include <linux/rwsem.h>
19#include <linux/sched.h>
19#include <linux/sched/signal.h>20#include <linux/sched/signal.h>
20#include <linux/security.h>21#include <linux/security.h>
21 22
@@ -845,9 +846,15 @@ int af_alg_sendmsg(struct socket *sock, struct msghdr *msg, size_t size, · 823 unmodified lines
845 }846 }
846 847
847 lock_sock(sk);848 lock_sock(sk);
848 if (ctx->init && (init || !ctx->more)) {849 if (ctx->init && !ctx->more) {
849 err = -EINVAL;850 if (ctx->used) {
850 goto unlock;851 err = -EINVAL;
852 goto unlock;
853 }
854
855 pr_info_once(
856 "%s sent an empty control message without MSG_MORE.\n",
857 current->comm);
851 }858 }
852 ctx->init = true;859 ctx->init = true;
853 860
crypto/drbg.c+1−1
@@ -1521,7 +1521,7 @@ static int drbg_prepare_hrng(struct drbg_state *drbg) · 1520 unmodified lines
1521 1521
1522 case -EALREADY:1522 case -EALREADY:
1523 err = 0;1523 err = 0;
1524 /* fall through */1524 fallthrough;
1525 1525
1526 default:1526 default:
1527 drbg->random_ready.func = NULL;1527 drbg->random_ready.func = NULL;
crypto/tcrypt.c+57−57
@@ -2348,121 +2348,121 @@ static int do_test(const char *alg, u32 type, u32 mask, int m, u32 num_mb) · 2347 unmodified lines
2348 test_hash_speed(alg, sec, generic_hash_speed_template);2348 test_hash_speed(alg, sec, generic_hash_speed_template);
2349 break;2349 break;
2350 }2350 }
2351 /* fall through */2351 fallthrough;
2352 case 301:2352 case 301:
2353 test_hash_speed("md4", sec, generic_hash_speed_template);2353 test_hash_speed("md4", sec, generic_hash_speed_template);
2354 if (mode > 300 && mode < 400) break;2354 if (mode > 300 && mode < 400) break;
2355 /* fall through */2355 fallthrough;
2356 case 302:2356 case 302:
2357 test_hash_speed("md5", sec, generic_hash_speed_template);2357 test_hash_speed("md5", sec, generic_hash_speed_template);
2358 if (mode > 300 && mode < 400) break;2358 if (mode > 300 && mode < 400) break;
2359 /* fall through */2359 fallthrough;
2360 case 303:2360 case 303:
2361 test_hash_speed("sha1", sec, generic_hash_speed_template);2361 test_hash_speed("sha1", sec, generic_hash_speed_template);
2362 if (mode > 300 && mode < 400) break;2362 if (mode > 300 && mode < 400) break;
2363 /* fall through */2363 fallthrough;
2364 case 304:2364 case 304:
2365 test_hash_speed("sha256", sec, generic_hash_speed_template);2365 test_hash_speed("sha256", sec, generic_hash_speed_template);
2366 if (mode > 300 && mode < 400) break;2366 if (mode > 300 && mode < 400) break;
2367 /* fall through */2367 fallthrough;
2368 case 305:2368 case 305:
2369 test_hash_speed("sha384", sec, generic_hash_speed_template);2369 test_hash_speed("sha384", sec, generic_hash_speed_template);
2370 if (mode > 300 && mode < 400) break;2370 if (mode > 300 && mode < 400) break;
2371 /* fall through */2371 fallthrough;
2372 case 306:2372 case 306:
2373 test_hash_speed("sha512", sec, generic_hash_speed_template);2373 test_hash_speed("sha512", sec, generic_hash_speed_template);
2374 if (mode > 300 && mode < 400) break;2374 if (mode > 300 && mode < 400) break;
2375 /* fall through */2375 fallthrough;
2376 case 307:2376 case 307:
2377 test_hash_speed("wp256", sec, generic_hash_speed_template);2377 test_hash_speed("wp256", sec, generic_hash_speed_template);
2378 if (mode > 300 && mode < 400) break;2378 if (mode > 300 && mode < 400) break;
2379 /* fall through */2379 fallthrough;
2380 case 308:2380 case 308:
2381 test_hash_speed("wp384", sec, generic_hash_speed_template);2381 test_hash_speed("wp384", sec, generic_hash_speed_template);
2382 if (mode > 300 && mode < 400) break;2382 if (mode > 300 && mode < 400) break;
2383 /* fall through */2383 fallthrough;
2384 case 309:2384 case 309:
2385 test_hash_speed("wp512", sec, generic_hash_speed_template);2385 test_hash_speed("wp512", sec, generic_hash_speed_template);
2386 if (mode > 300 && mode < 400) break;2386 if (mode > 300 && mode < 400) break;
2387 /* fall through */2387 fallthrough;
2388 case 310:2388 case 310:
2389 test_hash_speed("tgr128", sec, generic_hash_speed_template);2389 test_hash_speed("tgr128", sec, generic_hash_speed_template);
2390 if (mode > 300 && mode < 400) break;2390 if (mode > 300 && mode < 400) break;
2391 /* fall through */2391 fallthrough;
2392 case 311:2392 case 311:
2393 test_hash_speed("tgr160", sec, generic_hash_speed_template);2393 test_hash_speed("tgr160", sec, generic_hash_speed_template);
2394 if (mode > 300 && mode < 400) break;2394 if (mode > 300 && mode < 400) break;
2395 /* fall through */2395 fallthrough;
2396 case 312:2396 case 312:
2397 test_hash_speed("tgr192", sec, generic_hash_speed_template);2397 test_hash_speed("tgr192", sec, generic_hash_speed_template);
2398 if (mode > 300 && mode < 400) break;2398 if (mode > 300 && mode < 400) break;
2399 /* fall through */2399 fallthrough;
2400 case 313:2400 case 313:
2401 test_hash_speed("sha224", sec, generic_hash_speed_template);2401 test_hash_speed("sha224", sec, generic_hash_speed_template);
2402 if (mode > 300 && mode < 400) break;2402 if (mode > 300 && mode < 400) break;
2403 /* fall through */2403 fallthrough;
2404 case 314:2404 case 314:
2405 test_hash_speed("rmd128", sec, generic_hash_speed_template);2405 test_hash_speed("rmd128", sec, generic_hash_speed_template);
2406 if (mode > 300 && mode < 400) break;2406 if (mode > 300 && mode < 400) break;
2407 /* fall through */2407 fallthrough;
2408 case 315:2408 case 315:
2409 test_hash_speed("rmd160", sec, generic_hash_speed_template);2409 test_hash_speed("rmd160", sec, generic_hash_speed_template);
2410 if (mode > 300 && mode < 400) break;2410 if (mode > 300 && mode < 400) break;
2411 /* fall through */2411 fallthrough;
2412 case 316:2412 case 316:
2413 test_hash_speed("rmd256", sec, generic_hash_speed_template);2413 test_hash_speed("rmd256", sec, generic_hash_speed_template);
2414 if (mode > 300 && mode < 400) break;2414 if (mode > 300 && mode < 400) break;
2415 /* fall through */2415 fallthrough;
2416 case 317:2416 case 317:
2417 test_hash_speed("rmd320", sec, generic_hash_speed_template);2417 test_hash_speed("rmd320", sec, generic_hash_speed_template);
2418 if (mode > 300 && mode < 400) break;2418 if (mode > 300 && mode < 400) break;
2419 /* fall through */2419 fallthrough;
2420 case 318:2420 case 318:
2421 test_hash_speed("ghash-generic", sec, hash_speed_template_16);2421 test_hash_speed("ghash-generic", sec, hash_speed_template_16);
2422 if (mode > 300 && mode < 400) break;2422 if (mode > 300 && mode < 400) break;
2423 /* fall through */2423 fallthrough;
2424 case 319:2424 case 319:
2425 test_hash_speed("crc32c", sec, generic_hash_speed_template);2425 test_hash_speed("crc32c", sec, generic_hash_speed_template);
2426 if (mode > 300 && mode < 400) break;2426 if (mode > 300 && mode < 400) break;
2427 /* fall through */2427 fallthrough;
2428 case 320:2428 case 320:
2429 test_hash_speed("crct10dif", sec, generic_hash_speed_template);2429 test_hash_speed("crct10dif", sec, generic_hash_speed_template);
2430 if (mode > 300 && mode < 400) break;2430 if (mode > 300 && mode < 400) break;
2431 /* fall through */2431 fallthrough;
2432 case 321:2432 case 321:
2433 test_hash_speed("poly1305", sec, poly1305_speed_template);2433 test_hash_speed("poly1305", sec, poly1305_speed_template);
2434 if (mode > 300 && mode < 400) break;2434 if (mode > 300 && mode < 400) break;
2435 /* fall through */2435 fallthrough;
2436 case 322:2436 case 322:
2437 test_hash_speed("sha3-224", sec, generic_hash_speed_template);2437 test_hash_speed("sha3-224", sec, generic_hash_speed_template);
2438 if (mode > 300 && mode < 400) break;2438 if (mode > 300 && mode < 400) break;
2439 /* fall through */2439 fallthrough;
2440 case 323:2440 case 323:
2441 test_hash_speed("sha3-256", sec, generic_hash_speed_template);2441 test_hash_speed("sha3-256", sec, generic_hash_speed_template);
2442 if (mode > 300 && mode < 400) break;2442 if (mode > 300 && mode < 400) break;
2443 /* fall through */2443 fallthrough;
2444 case 324:2444 case 324:
2445 test_hash_speed("sha3-384", sec, generic_hash_speed_template);2445 test_hash_speed("sha3-384", sec, generic_hash_speed_template);
2446 if (mode > 300 && mode < 400) break;2446 if (mode > 300 && mode < 400) break;
2447 /* fall through */2447 fallthrough;
2448 case 325:2448 case 325:
2449 test_hash_speed("sha3-512", sec, generic_hash_speed_template);2449 test_hash_speed("sha3-512", sec, generic_hash_speed_template);
2450 if (mode > 300 && mode < 400) break;2450 if (mode > 300 && mode < 400) break;
2451 /* fall through */2451 fallthrough;
2452 case 326:2452 case 326:
2453 test_hash_speed("sm3", sec, generic_hash_speed_template);2453 test_hash_speed("sm3", sec, generic_hash_speed_template);
2454 if (mode > 300 && mode < 400) break;2454 if (mode > 300 && mode < 400) break;
2455 /* fall through */2455 fallthrough;
2456 case 327:2456 case 327:
2457 test_hash_speed("streebog256", sec,2457 test_hash_speed("streebog256", sec,
2458 generic_hash_speed_template);2458 generic_hash_speed_template);
2459 if (mode > 300 && mode < 400) break;2459 if (mode > 300 && mode < 400) break;
2460 /* fall through */2460 fallthrough;
2461 case 328:2461 case 328:
2462 test_hash_speed("streebog512", sec,2462 test_hash_speed("streebog512", sec,
2463 generic_hash_speed_template);2463 generic_hash_speed_template);
2464 if (mode > 300 && mode < 400) break;2464 if (mode > 300 && mode < 400) break;
2465 /* fall through */2465 fallthrough;
2466 case 399:2466 case 399:
2467 break;2467 break;
2468 2468
@@ -2471,121 +2471,121 @@ static int do_test(const char *alg, u32 type, u32 mask, int m, u32 num_mb) · 2 unmodified lines
2471 test_ahash_speed(alg, sec, generic_hash_speed_template);2471 test_ahash_speed(alg, sec, generic_hash_speed_template);
2472 break;2472 break;
2473 }2473 }
2474 /* fall through */2474 fallthrough;
2475 case 401:2475 case 401:
2476 test_ahash_speed("md4", sec, generic_hash_speed_template);2476 test_ahash_speed("md4", sec, generic_hash_speed_template);
2477 if (mode > 400 && mode < 500) break;2477 if (mode > 400 && mode < 500) break;
2478 /* fall through */2478 fallthrough;
2479 case 402:2479 case 402:
2480 test_ahash_speed("md5", sec, generic_hash_speed_template);2480 test_ahash_speed("md5", sec, generic_hash_speed_template);
2481 if (mode > 400 && mode < 500) break;2481 if (mode > 400 && mode < 500) break;
2482 /* fall through */2482 fallthrough;
2483 case 403:2483 case 403:
2484 test_ahash_speed("sha1", sec, generic_hash_speed_template);2484 test_ahash_speed("sha1", sec, generic_hash_speed_template);
2485 if (mode > 400 && mode < 500) break;2485 if (mode > 400 && mode < 500) break;
2486 /* fall through */2486 fallthrough;
2487 case 404:2487 case 404:
2488 test_ahash_speed("sha256", sec, generic_hash_speed_template);2488 test_ahash_speed("sha256", sec, generic_hash_speed_template);
2489 if (mode > 400 && mode < 500) break;2489 if (mode > 400 && mode < 500) break;
2490 /* fall through */2490 fallthrough;
2491 case 405:2491 case 405:
2492 test_ahash_speed("sha384", sec, generic_hash_speed_template);2492 test_ahash_speed("sha384", sec, generic_hash_speed_template);
2493 if (mode > 400 && mode < 500) break;2493 if (mode > 400 && mode < 500) break;
2494 /* fall through */2494 fallthrough;
2495 case 406:2495 case 406:
2496 test_ahash_speed("sha512", sec, generic_hash_speed_template);2496 test_ahash_speed("sha512", sec, generic_hash_speed_template);
2497 if (mode > 400 && mode < 500) break;2497 if (mode > 400 && mode < 500) break;
2498 /* fall through */2498 fallthrough;
2499 case 407:2499 case 407:
2500 test_ahash_speed("wp256", sec, generic_hash_speed_template);2500 test_ahash_speed("wp256", sec, generic_hash_speed_template);
2501 if (mode > 400 && mode < 500) break;2501 if (mode > 400 && mode < 500) break;
2502 /* fall through */2502 fallthrough;
2503 case 408:2503 case 408:
2504 test_ahash_speed("wp384", sec, generic_hash_speed_template);2504 test_ahash_speed("wp384", sec, generic_hash_speed_template);
2505 if (mode > 400 && mode < 500) break;2505 if (mode > 400 && mode < 500) break;
2506 /* fall through */2506 fallthrough;
2507 case 409:2507 case 409:
2508 test_ahash_speed("wp512", sec, generic_hash_speed_template);2508 test_ahash_speed("wp512", sec, generic_hash_speed_template);
2509 if (mode > 400 && mode < 500) break;2509 if (mode > 400 && mode < 500) break;
2510 /* fall through */2510 fallthrough;
2511 case 410:2511 case 410:
2512 test_ahash_speed("tgr128", sec, generic_hash_speed_template);2512 test_ahash_speed("tgr128", sec, generic_hash_speed_template);
2513 if (mode > 400 && mode < 500) break;2513 if (mode > 400 && mode < 500) break;
2514 /* fall through */2514 fallthrough;
2515 case 411:2515 case 411:
2516 test_ahash_speed("tgr160", sec, generic_hash_speed_template);2516 test_ahash_speed("tgr160", sec, generic_hash_speed_template);
2517 if (mode > 400 && mode < 500) break;2517 if (mode > 400 && mode < 500) break;
2518 /* fall through */2518 fallthrough;
2519 case 412:2519 case 412:
2520 test_ahash_speed("tgr192", sec, generic_hash_speed_template);2520 test_ahash_speed("tgr192", sec, generic_hash_speed_template);
2521 if (mode > 400 && mode < 500) break;2521 if (mode > 400 && mode < 500) break;
2522 /* fall through */2522 fallthrough;
2523 case 413:2523 case 413:
2524 test_ahash_speed("sha224", sec, generic_hash_speed_template);2524 test_ahash_speed("sha224", sec, generic_hash_speed_template);
2525 if (mode > 400 && mode < 500) break;2525 if (mode > 400 && mode < 500) break;
2526 /* fall through */2526 fallthrough;
2527 case 414:2527 case 414:
2528 test_ahash_speed("rmd128", sec, generic_hash_speed_template);2528 test_ahash_speed("rmd128", sec, generic_hash_speed_template);
2529 if (mode > 400 && mode < 500) break;2529 if (mode > 400 && mode < 500) break;
2530 /* fall through */2530 fallthrough;
2531 case 415:2531 case 415:
2532 test_ahash_speed("rmd160", sec, generic_hash_speed_template);2532 test_ahash_speed("rmd160", sec, generic_hash_speed_template);
2533 if (mode > 400 && mode < 500) break;2533 if (mode > 400 && mode < 500) break;
2534 /* fall through */2534 fallthrough;
2535 case 416:2535 case 416:
2536 test_ahash_speed("rmd256", sec, generic_hash_speed_template);2536 test_ahash_speed("rmd256", sec, generic_hash_speed_template);
2537 if (mode > 400 && mode < 500) break;2537 if (mode > 400 && mode < 500) break;
2538 /* fall through */2538 fallthrough;
2539 case 417:2539 case 417:
2540 test_ahash_speed("rmd320", sec, generic_hash_speed_template);2540 test_ahash_speed("rmd320", sec, generic_hash_speed_template);
2541 if (mode > 400 && mode < 500) break;2541 if (mode > 400 && mode < 500) break;
2542 /* fall through */2542 fallthrough;
2543 case 418:2543 case 418:
2544 test_ahash_speed("sha3-224", sec, generic_hash_speed_template);2544 test_ahash_speed("sha3-224", sec, generic_hash_speed_template);
2545 if (mode > 400 && mode < 500) break;2545 if (mode > 400 && mode < 500) break;
2546 /* fall through */2546 fallthrough;
2547 case 419:2547 case 419:
2548 test_ahash_speed("sha3-256", sec, generic_hash_speed_template);2548 test_ahash_speed("sha3-256", sec, generic_hash_speed_template);
2549 if (mode > 400 && mode < 500) break;2549 if (mode > 400 && mode < 500) break;
2550 /* fall through */2550 fallthrough;
2551 case 420:2551 case 420:
2552 test_ahash_speed("sha3-384", sec, generic_hash_speed_template);2552 test_ahash_speed("sha3-384", sec, generic_hash_speed_template);
2553 if (mode > 400 && mode < 500) break;2553 if (mode > 400 && mode < 500) break;
2554 /* fall through */2554 fallthrough;
2555 case 421:2555 case 421:
2556 test_ahash_speed("sha3-512", sec, generic_hash_speed_template);2556 test_ahash_speed("sha3-512", sec, generic_hash_speed_template);
2557 if (mode > 400 && mode < 500) break;2557 if (mode > 400 && mode < 500) break;
2558 /* fall through */2558 fallthrough;
2559 case 422:2559 case 422:
2560 test_mb_ahash_speed("sha1", sec, generic_hash_speed_template,2560 test_mb_ahash_speed("sha1", sec, generic_hash_speed_template,
2561 num_mb);2561 num_mb);
2562 if (mode > 400 && mode < 500) break;2562 if (mode > 400 && mode < 500) break;
2563 /* fall through */2563 fallthrough;
2564 case 423:2564 case 423:
2565 test_mb_ahash_speed("sha256", sec, generic_hash_speed_template,2565 test_mb_ahash_speed("sha256", sec, generic_hash_speed_template,
2566 num_mb);2566 num_mb);
2567 if (mode > 400 && mode < 500) break;2567 if (mode > 400 && mode < 500) break;
2568 /* fall through */2568 fallthrough;
2569 case 424:2569 case 424:
2570 test_mb_ahash_speed("sha512", sec, generic_hash_speed_template,2570 test_mb_ahash_speed("sha512", sec, generic_hash_speed_template,
2571 num_mb);2571 num_mb);
2572 if (mode > 400 && mode < 500) break;2572 if (mode > 400 && mode < 500) break;
2573 /* fall through */2573 fallthrough;
2574 case 425:2574 case 425:
2575 test_mb_ahash_speed("sm3", sec, generic_hash_speed_template,2575 test_mb_ahash_speed("sm3", sec, generic_hash_speed_template,
2576 num_mb);2576 num_mb);
2577 if (mode > 400 && mode < 500) break;2577 if (mode > 400 && mode < 500) break;
2578 /* fall through */2578 fallthrough;
2579 case 426:2579 case 426:
2580 test_mb_ahash_speed("streebog256", sec,2580 test_mb_ahash_speed("streebog256", sec,
2581 generic_hash_speed_template, num_mb);2581 generic_hash_speed_template, num_mb);
2582 if (mode > 400 && mode < 500) break;2582 if (mode > 400 && mode < 500) break;
2583 /* fall through */2583 fallthrough;
2584 case 427:2584 case 427:
2585 test_mb_ahash_speed("streebog512", sec,2585 test_mb_ahash_speed("streebog512", sec,
2586 generic_hash_speed_template, num_mb);2586 generic_hash_speed_template, num_mb);
2587 if (mode > 400 && mode < 500) break;2587 if (mode > 400 && mode < 500) break;
2588 /* fall through */2588 fallthrough;
2589 case 499:2589 case 499:
2590 break;2590 break;
2591 2591
drivers/accessibility/braille/braille_console.c+1−1
@@ -290,7 +290,7 @@ static int vt_notifier_call(struct notifier_block *blk, · 289 unmodified lines
290 break;290 break;
291 case '\t':291 case '\t':
292 c = ' ';292 c = ' ';
293 /* Fallthrough */293 fallthrough;
294 default:294 default:
295 if (c < 32)295 if (c < 32)
296 /* Ignore other control sequences */296 /* Ignore other control sequences */
drivers/accessibility/speakup/Kconfig+9−4
@@ -42,6 +42,11 @@ config SPEAKUP · 41 unmodified lines
42 one of the listed synthesizers, you should say n.42 one of the listed synthesizers, you should say n.
43 43
44if SPEAKUP44if SPEAKUP
45
46config SPEAKUP_SERIALIO
47 def_bool y
48 depends on ISA || COMPILE_TEST
49
45config SPEAKUP_SYNTH_ACNTSA50config SPEAKUP_SYNTH_ACNTSA
46 tristate "Accent SA synthesizer support"51 tristate "Accent SA synthesizer support"
47 help52 help
@@ -52,7 +57,7 @@ config SPEAKUP_SYNTH_ACNTSA · 4 unmodified lines
52 57
53config SPEAKUP_SYNTH_ACNTPC58config SPEAKUP_SYNTH_ACNTPC
54 tristate "Accent PC synthesizer support"59 tristate "Accent PC synthesizer support"
55 depends on ISA || COMPILE_TEST60 depends on SPEAKUP_SERIALIO
56 help61 help
57 This is the Speakup driver for the accent pc62 This is the Speakup driver for the accent pc
58 synthesizer. You can say y to build it into the kernel,63 synthesizer. You can say y to build it into the kernel,
@@ -104,7 +109,7 @@ config SPEAKUP_SYNTH_DECEXT · 45 unmodified lines
104 109
105config SPEAKUP_SYNTH_DECPC110config SPEAKUP_SYNTH_DECPC
106 depends on m111 depends on m
107 depends on ISA || COMPILE_TEST112 depends on SPEAKUP_SERIALIO
108 tristate "DECtalk PC (big ISA card) synthesizer support"113 tristate "DECtalk PC (big ISA card) synthesizer support"
109 help114 help
110 115
@@ -127,7 +132,7 @@ config SPEAKUP_SYNTH_DECPC · 16 unmodified lines
127 132
128config SPEAKUP_SYNTH_DTLK133config SPEAKUP_SYNTH_DTLK
129 tristate "DoubleTalk PC synthesizer support"134 tristate "DoubleTalk PC synthesizer support"
130 depends on ISA || COMPILE_TEST135 depends on SPEAKUP_SERIALIO
131 help136 help
132 137
133 This is the Speakup driver for the internal DoubleTalk138 This is the Speakup driver for the internal DoubleTalk
@@ -138,7 +143,7 @@ config SPEAKUP_SYNTH_DTLK · 4 unmodified lines
138 143
139config SPEAKUP_SYNTH_KEYPC144config SPEAKUP_SYNTH_KEYPC
140 tristate "Keynote Gold PC synthesizer support"145 tristate "Keynote Gold PC synthesizer support"
141 depends on ISA || COMPILE_TEST146 depends on SPEAKUP_SERIALIO
142 help147 help
143 148
144 This is the Speakup driver for the Keynote Gold149 This is the Speakup driver for the Keynote Gold
drivers/accessibility/speakup/Makefile+1−1
@@ -25,8 +25,8 @@ speakup-y := \ · 24 unmodified lines
25 keyhelp.o \25 keyhelp.o \
26 kobjects.o \26 kobjects.o \
27 selection.o \27 selection.o \
28 serialio.o \
29 spk_ttyio.o \28 spk_ttyio.o \
30 synth.o \29 synth.o \
31 thread.o \30 thread.o \
32 varhandlers.o31 varhandlers.o
32speakup-$(CONFIG_SPEAKUP_SERIALIO) += serialio.o
drivers/accessibility/speakup/serialio.c+5−3
@@ -32,6 +32,7 @@ static void spk_serial_tiocmset(unsigned int set, unsigned int clear); · 31 unmodified lines
32static unsigned char spk_serial_in(void);32static unsigned char spk_serial_in(void);
33static unsigned char spk_serial_in_nowait(void);33static unsigned char spk_serial_in_nowait(void);
34static void spk_serial_flush_buffer(void);34static void spk_serial_flush_buffer(void);
35static int spk_serial_wait_for_xmitr(struct spk_synth *in_synth);
35 36
36struct spk_io_ops spk_serial_io_ops = {37struct spk_io_ops spk_serial_io_ops = {
37 .synth_out = spk_serial_out,38 .synth_out = spk_serial_out,
@@ -40,6 +41,7 @@ struct spk_io_ops spk_serial_io_ops = { · 2 unmodified lines
40 .synth_in = spk_serial_in,41 .synth_in = spk_serial_in,
41 .synth_in_nowait = spk_serial_in_nowait,42 .synth_in_nowait = spk_serial_in_nowait,
42 .flush_buffer = spk_serial_flush_buffer,43 .flush_buffer = spk_serial_flush_buffer,
44 .wait_for_xmitr = spk_serial_wait_for_xmitr,
43};45};
44EXPORT_SYMBOL_GPL(spk_serial_io_ops);46EXPORT_SYMBOL_GPL(spk_serial_io_ops);
45 47
@@ -211,7 +213,7 @@ void spk_stop_serial_interrupt(void) · 165 unmodified lines
211}213}
212EXPORT_SYMBOL_GPL(spk_stop_serial_interrupt);214EXPORT_SYMBOL_GPL(spk_stop_serial_interrupt);
213 215
214int spk_wait_for_xmitr(struct spk_synth *in_synth)216static int spk_serial_wait_for_xmitr(struct spk_synth *in_synth)
215{217{
216 int tmout = SPK_XMITR_TIMEOUT;218 int tmout = SPK_XMITR_TIMEOUT;
217 219
@@ -280,7 +282,7 @@ static void spk_serial_flush_buffer(void) · 62 unmodified lines
280 282
281static int spk_serial_out(struct spk_synth *in_synth, const char ch)283static int spk_serial_out(struct spk_synth *in_synth, const char ch)
282{284{
283 if (in_synth->alive && spk_wait_for_xmitr(in_synth)) {285 if (in_synth->alive && spk_serial_wait_for_xmitr(in_synth)) {
284 outb_p(ch, speakup_info.port_tts);286 outb_p(ch, speakup_info.port_tts);
285 return 1;287 return 1;
286 }288 }
@@ -295,7 +297,7 @@ const char *spk_serial_synth_immediate(struct spk_synth *synth, · 8 unmodified lines
295 while ((ch = *buff)) {297 while ((ch = *buff)) {
296 if (ch == '\n')298 if (ch == '\n')
297 ch = synth->procspeech;299 ch = synth->procspeech;
298 if (spk_wait_for_xmitr(synth))300 if (spk_serial_wait_for_xmitr(synth))
299 outb(ch, speakup_info.port_tts);301 outb(ch, speakup_info.port_tts);
300 else302 else
301 return buff;303 return buff;
drivers/accessibility/speakup/spk_priv.h+0−1
@@ -34,7 +34,6 @@ · 33 unmodified lines
34 34
35const struct old_serial_port *spk_serial_init(int index);35const struct old_serial_port *spk_serial_init(int index);
36void spk_stop_serial_interrupt(void);36void spk_stop_serial_interrupt(void);
37int spk_wait_for_xmitr(struct spk_synth *in_synth);
38void spk_serial_release(void);37void spk_serial_release(void);
39void spk_ttyio_release(void);38void spk_ttyio_release(void);
40void spk_ttyio_register_ldisc(void);39void spk_ttyio_register_ldisc(void);
drivers/accessibility/speakup/spk_ttyio.c+7−0
@@ -116,6 +116,7 @@ static void spk_ttyio_tiocmset(unsigned int set, unsigned int clear); · 115 unmodified lines
116static unsigned char spk_ttyio_in(void);116static unsigned char spk_ttyio_in(void);
117static unsigned char spk_ttyio_in_nowait(void);117static unsigned char spk_ttyio_in_nowait(void);
118static void spk_ttyio_flush_buffer(void);118static void spk_ttyio_flush_buffer(void);
119static int spk_ttyio_wait_for_xmitr(struct spk_synth *in_synth);
119 120
120struct spk_io_ops spk_ttyio_ops = {121struct spk_io_ops spk_ttyio_ops = {
121 .synth_out = spk_ttyio_out,122 .synth_out = spk_ttyio_out,
@@ -125,6 +126,7 @@ struct spk_io_ops spk_ttyio_ops = { · 3 unmodified lines
125 .synth_in = spk_ttyio_in,126 .synth_in = spk_ttyio_in,
126 .synth_in_nowait = spk_ttyio_in_nowait,127 .synth_in_nowait = spk_ttyio_in_nowait,
127 .flush_buffer = spk_ttyio_flush_buffer,128 .flush_buffer = spk_ttyio_flush_buffer,
129 .wait_for_xmitr = spk_ttyio_wait_for_xmitr,
128};130};
129EXPORT_SYMBOL_GPL(spk_ttyio_ops);131EXPORT_SYMBOL_GPL(spk_ttyio_ops);
130 132
@@ -286,6 +288,11 @@ static void spk_ttyio_tiocmset(unsigned int set, unsigned int clear) · 155 unmodified lines
286 mutex_unlock(&speakup_tty_mutex);288 mutex_unlock(&speakup_tty_mutex);
287}289}
288 290
291static int spk_ttyio_wait_for_xmitr(struct spk_synth *in_synth)
292{
293 return 1;
294}
295
289static unsigned char ttyio_in(int timeout)296static unsigned char ttyio_in(int timeout)
290{297{
291 struct spk_ldisc_data *ldisc_data = speakup_tty->disc_data;298 struct spk_ldisc_data *ldisc_data = speakup_tty->disc_data;
drivers/accessibility/speakup/spk_types.h+1−0
@@ -158,6 +158,7 @@ struct spk_io_ops { · 157 unmodified lines
158 unsigned char (*synth_in)(void);158 unsigned char (*synth_in)(void);
159 unsigned char (*synth_in_nowait)(void);159 unsigned char (*synth_in_nowait)(void);
160 void (*flush_buffer)(void);160 void (*flush_buffer)(void);
161 int (*wait_for_xmitr)(struct spk_synth *synth);
161};162};
162 163
163struct spk_synth {164struct spk_synth {
drivers/accessibility/speakup/synth.c+1−1
@@ -159,7 +159,7 @@ int spk_synth_is_alive_restart(struct spk_synth *synth) · 158 unmodified lines
159{159{
160 if (synth->alive)160 if (synth->alive)
161 return 1;161 return 1;
162 if (spk_wait_for_xmitr(synth) > 0) {162 if (synth->io_ops->wait_for_xmitr(synth) > 0) {
163 /* restart */163 /* restart */
164 synth->alive = 1;164 synth->alive = 1;
165 synth_printf("%s", synth->init);165 synth_printf("%s", synth->init);
drivers/acpi/acpi_apd.c+2−2
@@ -99,8 +99,8 @@ static int fch_misc_setup(struct apd_private_data *pdata) · 98 unmodified lines
99 if (ret < 0)99 if (ret < 0)
100 return -ENOENT;100 return -ENOENT;
101 101
102 acpi_dev_get_property(adev, "is-rv", ACPI_TYPE_INTEGER, &obj);102 if (!acpi_dev_get_property(adev, "is-rv", ACPI_TYPE_INTEGER, &obj))
103 clk_data->is_rv = obj->integer.value;103 clk_data->is_rv = obj->integer.value;
104 104
105 list_for_each_entry(rentry, &resource_list, node) {105 list_for_each_entry(rentry, &resource_list, node) {
106 clk_data->base = devm_ioremap(&adev->dev, rentry->res->start,106 clk_data->base = devm_ioremap(&adev->dev, rentry->res->start,
drivers/acpi/osl.c+19−4
@@ -350,7 +350,7 @@ void __iomem __ref · 349 unmodified lines
350 350
351 pg_off = round_down(phys, PAGE_SIZE);351 pg_off = round_down(phys, PAGE_SIZE);
352 pg_sz = round_up(phys + size, PAGE_SIZE) - pg_off;352 pg_sz = round_up(phys + size, PAGE_SIZE) - pg_off;
353 virt = acpi_map(pg_off, pg_sz);353 virt = acpi_map(phys, size);
354 if (!virt) {354 if (!virt) {
355 mutex_unlock(&acpi_ioremap_lock);355 mutex_unlock(&acpi_ioremap_lock);
356 kfree(map);356 kfree(map);
@@ -358,7 +358,7 @@ void __iomem __ref · 1 unmodified line
358 }358 }
359 359
360 INIT_LIST_HEAD(&map->list);360 INIT_LIST_HEAD(&map->list);
361 map->virt = virt;361 map->virt = (void __iomem __force *)((unsigned long)virt & PAGE_MASK);
362 map->phys = pg_off;362 map->phys = pg_off;
363 map->size = pg_sz;363 map->size = pg_sz;
364 map->track.refcount = 1;364 map->track.refcount = 1;
@@ -1575,11 +1575,26 @@ static acpi_status acpi_deactivate_mem_region(acpi_handle handle, u32 level, · 1210 unmodified lines
1575acpi_status acpi_release_memory(acpi_handle handle, struct resource *res,1575acpi_status acpi_release_memory(acpi_handle handle, struct resource *res,
1576 u32 level)1576 u32 level)
1577{1577{
1578 acpi_status status;
1579
1578 if (!(res->flags & IORESOURCE_MEM))1580 if (!(res->flags & IORESOURCE_MEM))
1579 return AE_TYPE;1581 return AE_TYPE;
1580 1582
1581 return acpi_walk_namespace(ACPI_TYPE_REGION, handle, level,1583 status = acpi_walk_namespace(ACPI_TYPE_REGION, handle, level,
1582 acpi_deactivate_mem_region, NULL, res, NULL);1584 acpi_deactivate_mem_region, NULL,
1585 res, NULL);
1586 if (ACPI_FAILURE(status))
1587 return status;
1588
1589 /*
1590 * Wait for all of the mappings queued up for removal by
1591 * acpi_deactivate_mem_region() to actually go away.
1592 */
1593 synchronize_rcu();
1594 rcu_barrier();
1595 flush_scheduled_work();
1596
1597 return AE_OK;
1583}1598}
1584EXPORT_SYMBOL_GPL(acpi_release_memory);1599EXPORT_SYMBOL_GPL(acpi_release_memory);
1585 1600
drivers/ata/ahci.c+1−2
@@ -807,8 +807,7 @@ static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class, · 806 unmodified lines
807 (sstatus & 0xf) != 1)807 (sstatus & 0xf) != 1)
808 break;808 break;
809 809
810 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n",810 ata_link_info(link, "avn bounce port%d\n", port);
811 port);
812 811
813 pci_read_config_word(pdev, 0x92, &val);812 pci_read_config_word(pdev, 0x92, &val);
814 val &= ~(1 << port);813 val &= ~(1 << port);
drivers/ata/ahci_brcm.c+1−1
@@ -470,7 +470,7 @@ static int brcm_ahci_probe(struct platform_device *pdev) · 469 unmodified lines
470 switch (priv->version) {470 switch (priv->version) {
471 case BRCM_SATA_BCM7425:471 case BRCM_SATA_BCM7425:
472 hpriv->flags |= AHCI_HFLAG_DELAY_ENGINE;472 hpriv->flags |= AHCI_HFLAG_DELAY_ENGINE;
473 /* fall through */473 fallthrough;
474 case BRCM_SATA_NSP:474 case BRCM_SATA_NSP:
475 hpriv->flags |= AHCI_HFLAG_NO_NCQ;475 hpriv->flags |= AHCI_HFLAG_NO_NCQ;
476 priv->quirks |= BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE;476 priv->quirks |= BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE;
drivers/ata/libahci_platform.c+1−1
@@ -326,7 +326,7 @@ static int ahci_platform_get_phy(struct ahci_host_priv *hpriv, u32 port, · 325 unmodified lines
326 node);326 node);
327 break;327 break;
328 }328 }
329 /* fall through */329 fallthrough;
330 case -ENODEV:330 case -ENODEV:
331 /* continue normally */331 /* continue normally */
332 hpriv->phys[port] = NULL;332 hpriv->phys[port] = NULL;
drivers/ata/libata-core.c+10−11
@@ -190,7 +190,7 @@ struct ata_link *ata_link_next(struct ata_link *link, struct ata_port *ap, · 189 unmodified lines
190 case ATA_LITER_PMP_FIRST:190 case ATA_LITER_PMP_FIRST:
191 if (sata_pmp_attached(ap))191 if (sata_pmp_attached(ap))
192 return ap->pmp_link;192 return ap->pmp_link;
193 /* fall through */193 fallthrough;
194 case ATA_LITER_HOST_FIRST:194 case ATA_LITER_HOST_FIRST:
195 return &ap->link;195 return &ap->link;
196 }196 }
@@ -201,11 +201,11 @@ struct ata_link *ata_link_next(struct ata_link *link, struct ata_port *ap, · 4 unmodified lines
201 case ATA_LITER_HOST_FIRST:201 case ATA_LITER_HOST_FIRST:
202 if (sata_pmp_attached(ap))202 if (sata_pmp_attached(ap))
203 return ap->pmp_link;203 return ap->pmp_link;
204 /* fall through */204 fallthrough;
205 case ATA_LITER_PMP_FIRST:205 case ATA_LITER_PMP_FIRST:
206 if (unlikely(ap->slave_link))206 if (unlikely(ap->slave_link))
207 return ap->slave_link;207 return ap->slave_link;
208 /* fall through */208 fallthrough;
209 case ATA_LITER_EDGE:209 case ATA_LITER_EDGE:
210 return NULL;210 return NULL;
211 }211 }
@@ -523,7 +523,7 @@ int atapi_cmd_type(u8 opcode) · 311 unmodified lines
523 case ATA_12:523 case ATA_12:
524 if (atapi_passthru16)524 if (atapi_passthru16)
525 return ATAPI_PASS_THRU;525 return ATAPI_PASS_THRU;
526 /* fall thru */526 fallthrough;
527 default:527 default:
528 return ATAPI_MISC;528 return ATAPI_MISC;
529 }529 }
@@ -1800,7 +1800,7 @@ retry: · 1270 unmodified lines
1800 switch (class) {1800 switch (class) {
1801 case ATA_DEV_SEMB:1801 case ATA_DEV_SEMB:
1802 class = ATA_DEV_ATA; /* some hard drives report SEMB sig */1802 class = ATA_DEV_ATA; /* some hard drives report SEMB sig */
1803 /* fall through */1803 fallthrough;
1804 case ATA_DEV_ATA:1804 case ATA_DEV_ATA:
1805 case ATA_DEV_ZAC:1805 case ATA_DEV_ZAC:
1806 tf.command = ATA_CMD_ID_ATA;1806 tf.command = ATA_CMD_ID_ATA;
@@ -2907,7 +2907,7 @@ int ata_bus_probe(struct ata_port *ap) · 1100 unmodified lines
2907 case -ENODEV:2907 case -ENODEV:
2908 /* give it just one more chance */2908 /* give it just one more chance */
2909 tries[dev->devno] = min(tries[dev->devno], 1);2909 tries[dev->devno] = min(tries[dev->devno], 1);
2910 /* fall through */2910 fallthrough;
2911 case -EIO:2911 case -EIO:
2912 if (tries[dev->devno] == 1) {2912 if (tries[dev->devno] == 1) {
2913 /* This is the last chance, better to slow2913 /* This is the last chance, better to slow
@@ -3158,7 +3158,7 @@ int ata_down_xfermask_limit(struct ata_device *dev, unsigned int sel) · 244 unmodified lines
3158 3158
3159 case ATA_DNXFER_FORCE_PIO0:3159 case ATA_DNXFER_FORCE_PIO0:
3160 pio_mask &= 1;3160 pio_mask &= 1;
3161 /* fall through */3161 fallthrough;
3162 case ATA_DNXFER_FORCE_PIO:3162 case ATA_DNXFER_FORCE_PIO:
3163 mwdma_mask = 0;3163 mwdma_mask = 0;
3164 udma_mask = 0;3164 udma_mask = 0;
@@ -3868,9 +3868,8 @@ static const struct ata_blacklist_entry ata_device_blacklist [] = { · 703 unmodified lines
3868 /* https://bugzilla.kernel.org/show_bug.cgi?id=15573 */3868 /* https://bugzilla.kernel.org/show_bug.cgi?id=15573 */
3869 { "C300-CTFDDAC128MAG", "0001", ATA_HORKAGE_NONCQ, },3869 { "C300-CTFDDAC128MAG", "0001", ATA_HORKAGE_NONCQ, },
3870 3870
3871 /* Some Sandisk SSDs lock up hard with NCQ enabled. Reported on3871 /* Sandisk SD7/8/9s lock up hard on large trims */
3872 SD7SN6S256G and SD8SN8U256G */3872 { "SanDisk SD[789]*", NULL, ATA_HORKAGE_MAX_TRIM_128M, },
3873 { "SanDisk SD[78]SN*G", NULL, ATA_HORKAGE_NONCQ, },
3874 3873
3875 /* devices which puke on READ_NATIVE_MAX */3874 /* devices which puke on READ_NATIVE_MAX */
3876 { "HDS724040KLSA80", "KFAOA20N", ATA_HORKAGE_BROKEN_HPA, },3875 { "HDS724040KLSA80", "KFAOA20N", ATA_HORKAGE_BROKEN_HPA, },
@@ -4694,7 +4693,7 @@ void ata_qc_complete(struct ata_queued_cmd *qc) · 817 unmodified lines
4694 qc->tf.feature != SETFEATURES_RA_ON &&4693 qc->tf.feature != SETFEATURES_RA_ON &&
4695 qc->tf.feature != SETFEATURES_RA_OFF)4694 qc->tf.feature != SETFEATURES_RA_OFF)
4696 break;4695 break;
4697 /* fall through */4696 fallthrough;
4698 case ATA_CMD_INIT_DEV_PARAMS: /* CHS translation changed */4697 case ATA_CMD_INIT_DEV_PARAMS: /* CHS translation changed */
4699 case ATA_CMD_SET_MULTI: /* multi_count changed */4698 case ATA_CMD_SET_MULTI: /* multi_count changed */
4700 /* revalidate device */4699 /* revalidate device */
drivers/ata/libata-eh.c+3−3
@@ -1576,7 +1576,7 @@ static unsigned int ata_eh_analyze_tf(struct ata_queued_cmd *qc, · 1575 unmodified lines
1576 case ATA_DEV_ZAC:1576 case ATA_DEV_ZAC:
1577 if (stat & ATA_SENSE)1577 if (stat & ATA_SENSE)
1578 ata_eh_request_sense(qc, qc->scsicmd);1578 ata_eh_request_sense(qc, qc->scsicmd);
1579 /* fall through */1579 fallthrough;
1580 case ATA_DEV_ATA:1580 case ATA_DEV_ATA:
1581 if (err & ATA_ICRC)1581 if (err & ATA_ICRC)
1582 qc->err_mask |= AC_ERR_ATA_BUS;1582 qc->err_mask |= AC_ERR_ATA_BUS;
@@ -3473,11 +3473,11 @@ static int ata_eh_handle_dev_fail(struct ata_device *dev, int err) · 1890 unmodified lines
3473 case -ENODEV:3473 case -ENODEV:
3474 /* device missing or wrong IDENTIFY data, schedule probing */3474 /* device missing or wrong IDENTIFY data, schedule probing */
3475 ehc->i.probe_mask |= (1 << dev->devno);3475 ehc->i.probe_mask |= (1 << dev->devno);
3476 /* fall through */3476 fallthrough;
3477 case -EINVAL:3477 case -EINVAL:
3478 /* give it just one more chance */3478 /* give it just one more chance */
3479 ehc->tries[dev->devno] = min(ehc->tries[dev->devno], 1);3479 ehc->tries[dev->devno] = min(ehc->tries[dev->devno], 1);
3480 /* fall through */3480 fallthrough;
3481 case -EIO:3481 case -EIO:
3482 if (ehc->tries[dev->devno] == 1) {3482 if (ehc->tries[dev->devno] == 1) {
3483 /* This is the last chance, better to slow3483 /* This is the last chance, better to slow
drivers/ata/libata-scsi.c+9−3
@@ -2080,6 +2080,7 @@ static unsigned int ata_scsiop_inq_89(struct ata_scsi_args *args, u8 *rbuf) · 2079 unmodified lines
2080 2080
2081static unsigned int ata_scsiop_inq_b0(struct ata_scsi_args *args, u8 *rbuf)2081static unsigned int ata_scsiop_inq_b0(struct ata_scsi_args *args, u8 *rbuf)
2082{2082{
2083 struct ata_device *dev = args->dev;
2083 u16 min_io_sectors;2084 u16 min_io_sectors;
2084 2085
2085 rbuf[1] = 0xb0;2086 rbuf[1] = 0xb0;
@@ -2105,7 +2106,12 @@ static unsigned int ata_scsiop_inq_b0(struct ata_scsi_args *args, u8 *rbuf) · 19 unmodified lines
2105 * with the unmap bit set.2106 * with the unmap bit set.
2106 */2107 */
2107 if (ata_id_has_trim(args->id)) {2108 if (ata_id_has_trim(args->id)) {
2108 put_unaligned_be64(65535 * ATA_MAX_TRIM_RNUM, &rbuf[36]);2109 u64 max_blocks = 65535 * ATA_MAX_TRIM_RNUM;
2110
2111 if (dev->horkage & ATA_HORKAGE_MAX_TRIM_128M)
2112 max_blocks = 128 << (20 - SECTOR_SHIFT);
2113
2114 put_unaligned_be64(max_blocks, &rbuf[36]);
2109 put_unaligned_be32(1, &rbuf[28]);2115 put_unaligned_be32(1, &rbuf[28]);
2110 }2116 }
2111 2117
@@ -4162,7 +4168,7 @@ void ata_scsi_simulate(struct ata_device *dev, struct scsi_cmnd *cmd) · 2050 unmodified lines
4162 ata_scsi_rbuf_fill(&args, ata_scsiop_inq_b6);4168 ata_scsi_rbuf_fill(&args, ata_scsiop_inq_b6);
4163 break;4169 break;
4164 }4170 }
4165 /* Fallthrough */4171 fallthrough;
4166 default:4172 default:
4167 ata_scsi_set_invalid_field(dev, cmd, 2, 0xff);4173 ata_scsi_set_invalid_field(dev, cmd, 2, 0xff);
4168 break;4174 break;
@@ -4198,7 +4204,7 @@ void ata_scsi_simulate(struct ata_device *dev, struct scsi_cmnd *cmd) · 29 unmodified lines
4198 * turning this into a no-op.4204 * turning this into a no-op.
4199 */4205 */
4200 case SYNCHRONIZE_CACHE:4206 case SYNCHRONIZE_CACHE:
4201 /* fall through */4207 fallthrough;
4202 4208
4203 /* no-op's, complete with success */4209 /* no-op's, complete with success */
4204 case REZERO_UNIT:4210 case REZERO_UNIT:
drivers/ata/pata_atp867x.c+2−2
@@ -157,7 +157,7 @@ static int atp867x_get_active_clocks_shifted(struct ata_port *ap, · 156 unmodified lines
157 default:157 default:
158 printk(KERN_WARNING "ATP867X: active %dclk is invalid. "158 printk(KERN_WARNING "ATP867X: active %dclk is invalid. "
159 "Using 12clk.\n", clk);159 "Using 12clk.\n", clk);
160 /* fall through */160 fallthrough;
161 case 9 ... 12:161 case 9 ... 12:
162 clocks = 7; /* 12 clk */162 clocks = 7; /* 12 clk */
163 break;163 break;
@@ -190,7 +190,7 @@ static int atp867x_get_recover_clocks_shifted(unsigned int clk) · 26 unmodified lines
190 default:190 default:
191 printk(KERN_WARNING "ATP867X: recover %dclk is invalid. "191 printk(KERN_WARNING "ATP867X: recover %dclk is invalid. "
192 "Using default 12clk.\n", clk);192 "Using default 12clk.\n", clk);
193 /* fall through */193 fallthrough;
194 case 12: /* default 12 clk */194 case 12: /* default 12 clk */
195 clocks = 0;195 clocks = 0;
196 break;196 break;
drivers/ata/pata_serverworks.c+1−1
@@ -369,7 +369,7 @@ static int serverworks_fixup(struct pci_dev *pdev) · 368 unmodified lines
369 break;369 break;
370 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:370 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
371 ata_pci_bmdma_clear_simplex(pdev);371 ata_pci_bmdma_clear_simplex(pdev);
372 /* fall through */372 fallthrough;
373 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:373 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
374 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:374 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
375 rc = serverworks_fixup_csb(pdev);375 rc = serverworks_fixup_csb(pdev);
drivers/ata/sata_mv.c+6−6
@@ -2010,7 +2010,7 @@ static void mv_rw_multi_errata_sata24(struct ata_queued_cmd *qc) · 2009 unmodified lines
2010 break;2010 break;
2011 case ATA_CMD_WRITE_MULTI_FUA_EXT:2011 case ATA_CMD_WRITE_MULTI_FUA_EXT:
2012 tf->flags &= ~ATA_TFLAG_FUA; /* ugh */2012 tf->flags &= ~ATA_TFLAG_FUA; /* ugh */
2013 /* fall through */2013 fallthrough;
2014 case ATA_CMD_WRITE_MULTI_EXT:2014 case ATA_CMD_WRITE_MULTI_EXT:
2015 tf->command = ATA_CMD_PIO_WRITE_EXT;2015 tf->command = ATA_CMD_PIO_WRITE_EXT;
2016 break;2016 break;
@@ -2044,7 +2044,7 @@ static enum ata_completion_errors mv_qc_prep(struct ata_queued_cmd *qc) · 27 unmodified lines
2044 case ATA_PROT_DMA:2044 case ATA_PROT_DMA:
2045 if (tf->command == ATA_CMD_DSM)2045 if (tf->command == ATA_CMD_DSM)
2046 return AC_ERR_OK;2046 return AC_ERR_OK;
2047 /* fall-thru */2047 fallthrough;
2048 case ATA_PROT_NCQ:2048 case ATA_PROT_NCQ:
2049 break; /* continue below */2049 break; /* continue below */
2050 case ATA_PROT_PIO:2050 case ATA_PROT_PIO:
@@ -2296,7 +2296,7 @@ static unsigned int mv_qc_issue_fis(struct ata_queued_cmd *qc) · 245 unmodified lines
2296 switch (qc->tf.protocol) {2296 switch (qc->tf.protocol) {
2297 case ATAPI_PROT_PIO:2297 case ATAPI_PROT_PIO:
2298 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;2298 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
2299 /* fall through */2299 fallthrough;
2300 case ATAPI_PROT_NODATA:2300 case ATAPI_PROT_NODATA:
2301 ap->hsm_task_state = HSM_ST_FIRST;2301 ap->hsm_task_state = HSM_ST_FIRST;
2302 break;2302 break;
@@ -2347,7 +2347,7 @@ static unsigned int mv_qc_issue(struct ata_queued_cmd *qc) · 44 unmodified lines
2347 return AC_ERR_OTHER;2347 return AC_ERR_OTHER;
2348 break; /* use bmdma for this */2348 break; /* use bmdma for this */
2349 }2349 }
2350 /* fall thru */2350 fallthrough;
2351 case ATA_PROT_NCQ:2351 case ATA_PROT_NCQ:
2352 mv_start_edma(ap, port_mmio, pp, qc->tf.protocol);2352 mv_start_edma(ap, port_mmio, pp, qc->tf.protocol);
2353 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;2353 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
@@ -2376,7 +2376,7 @@ static unsigned int mv_qc_issue(struct ata_queued_cmd *qc) · 22 unmodified lines
2376 ": attempting PIO w/multiple DRQ: "2376 ": attempting PIO w/multiple DRQ: "
2377 "this may fail due to h/w errata\n");2377 "this may fail due to h/w errata\n");
2378 }2378 }
2379 /* fall through */2379 fallthrough;
2380 case ATA_PROT_NODATA:2380 case ATA_PROT_NODATA:
2381 case ATAPI_PROT_PIO:2381 case ATAPI_PROT_PIO:
2382 case ATAPI_PROT_NODATA:2382 case ATAPI_PROT_NODATA:
@@ -3864,7 +3864,7 @@ static int mv_chip_id(struct ata_host *host, unsigned int board_idx) · 1481 unmodified lines
3864 " and avoid the final two gigabytes on"3864 " and avoid the final two gigabytes on"
3865 " all RocketRAID BIOS initialized drives.\n");3865 " all RocketRAID BIOS initialized drives.\n");
3866 }3866 }
3867 /* fall through */3867 fallthrough;
3868 case chip_6042:3868 case chip_6042:
3869 hpriv->ops = &mv6xxx_ops;3869 hpriv->ops = &mv6xxx_ops;
3870 hp_flags |= MV_HP_GEN_IIE;3870 hp_flags |= MV_HP_GEN_IIE;
drivers/ata/sata_promise.c+4−4
@@ -637,7 +637,7 @@ static enum ata_completion_errors pdc_qc_prep(struct ata_queued_cmd *qc) · 636 unmodified lines
637 switch (qc->tf.protocol) {637 switch (qc->tf.protocol) {
638 case ATA_PROT_DMA:638 case ATA_PROT_DMA:
639 pdc_fill_sg(qc);639 pdc_fill_sg(qc);
640 /*FALLTHROUGH*/640 fallthrough;
641 case ATA_PROT_NODATA:641 case ATA_PROT_NODATA:
642 i = pdc_pkt_header(&qc->tf, qc->ap->bmdma_prd_dma,642 i = pdc_pkt_header(&qc->tf, qc->ap->bmdma_prd_dma,
643 qc->dev->devno, pp->pkt);643 qc->dev->devno, pp->pkt);
@@ -652,7 +652,7 @@ static enum ata_completion_errors pdc_qc_prep(struct ata_queued_cmd *qc) · 8 unmodified lines
652 break;652 break;
653 case ATAPI_PROT_DMA:653 case ATAPI_PROT_DMA:
654 pdc_fill_sg(qc);654 pdc_fill_sg(qc);
655 /*FALLTHROUGH*/655 fallthrough;
656 case ATAPI_PROT_NODATA:656 case ATAPI_PROT_NODATA:
657 pdc_atapi_pkt(qc);657 pdc_atapi_pkt(qc);
658 break;658 break;
@@ -1022,11 +1022,11 @@ static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc) · 363 unmodified lines
1022 case ATAPI_PROT_NODATA:1022 case ATAPI_PROT_NODATA:
1023 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)1023 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
1024 break;1024 break;
1025 /*FALLTHROUGH*/1025 fallthrough;
1026 case ATA_PROT_NODATA:1026 case ATA_PROT_NODATA:
1027 if (qc->tf.flags & ATA_TFLAG_POLLING)1027 if (qc->tf.flags & ATA_TFLAG_POLLING)
1028 break;1028 break;
1029 /*FALLTHROUGH*/1029 fallthrough;
1030 case ATAPI_PROT_DMA:1030 case ATAPI_PROT_DMA:
1031 case ATA_PROT_DMA:1031 case ATA_PROT_DMA:
1032 pdc_packet_start(qc);1032 pdc_packet_start(qc);
drivers/ata/sata_sx4.c+1−1
@@ -669,7 +669,7 @@ static unsigned int pdc20621_qc_issue(struct ata_queued_cmd *qc) · 668 unmodified lines
669 case ATA_PROT_NODATA:669 case ATA_PROT_NODATA:
670 if (qc->tf.flags & ATA_TFLAG_POLLING)670 if (qc->tf.flags & ATA_TFLAG_POLLING)
671 break;671 break;
672 /*FALLTHROUGH*/672 fallthrough;
673 case ATA_PROT_DMA:673 case ATA_PROT_DMA:
674 pdc20621_packet_start(qc);674 pdc20621_packet_start(qc);
675 return 0;675 return 0;
drivers/atm/firestream.c+2−1
@@ -711,7 +711,7 @@ static void process_txdone_queue (struct fs_dev *dev, struct queue *q) · 710 unmodified lines
711 711
712 switch (STATUS_CODE (qe)) {712 switch (STATUS_CODE (qe)) {
713 case 0x01: /* This is for AAL0 where we put the chip in streaming mode */713 case 0x01: /* This is for AAL0 where we put the chip in streaming mode */
714 /* Fall through */714 fallthrough;
715 case 0x02:715 case 0x02:
716 /* Process a real txdone entry. */716 /* Process a real txdone entry. */
717 tmp = qe->p0;717 tmp = qe->p0;
@@ -998,6 +998,7 @@ static int fs_open(struct atm_vcc *atm_vcc) · 280 unmodified lines
998 error = make_rate (pcr, r, &tmc0, NULL);998 error = make_rate (pcr, r, &tmc0, NULL);
999 if (error) {999 if (error) {
1000 kfree(tc);1000 kfree(tc);
1001 kfree(vcc);
1001 return error;1002 return error;
1002 }1003 }
1003 }1004 }
drivers/atm/fore200e.c+8−8
@@ -376,33 +376,33 @@ fore200e_shutdown(struct fore200e* fore200e) · 375 unmodified lines
376 case FORE200E_STATE_COMPLETE:376 case FORE200E_STATE_COMPLETE:
377 kfree(fore200e->stats);377 kfree(fore200e->stats);
378 378
379 /* fall through */379 fallthrough;
380 case FORE200E_STATE_IRQ:380 case FORE200E_STATE_IRQ:
381 free_irq(fore200e->irq, fore200e->atm_dev);381 free_irq(fore200e->irq, fore200e->atm_dev);
382 382
383 /* fall through */383 fallthrough;
384 case FORE200E_STATE_ALLOC_BUF:384 case FORE200E_STATE_ALLOC_BUF:
385 fore200e_free_rx_buf(fore200e);385 fore200e_free_rx_buf(fore200e);
386 386
387 /* fall through */387 fallthrough;
388 case FORE200E_STATE_INIT_BSQ:388 case FORE200E_STATE_INIT_BSQ:
389 fore200e_uninit_bs_queue(fore200e);389 fore200e_uninit_bs_queue(fore200e);
390 390
391 /* fall through */391 fallthrough;
392 case FORE200E_STATE_INIT_RXQ:392 case FORE200E_STATE_INIT_RXQ:
393 fore200e_dma_chunk_free(fore200e, &fore200e->host_rxq.status);393 fore200e_dma_chunk_free(fore200e, &fore200e->host_rxq.status);
394 fore200e_dma_chunk_free(fore200e, &fore200e->host_rxq.rpd);394 fore200e_dma_chunk_free(fore200e, &fore200e->host_rxq.rpd);
395 395
396 /* fall through */396 fallthrough;
397 case FORE200E_STATE_INIT_TXQ:397 case FORE200E_STATE_INIT_TXQ:
398 fore200e_dma_chunk_free(fore200e, &fore200e->host_txq.status);398 fore200e_dma_chunk_free(fore200e, &fore200e->host_txq.status);
399 fore200e_dma_chunk_free(fore200e, &fore200e->host_txq.tpd);399 fore200e_dma_chunk_free(fore200e, &fore200e->host_txq.tpd);
400 400
401 /* fall through */401 fallthrough;
402 case FORE200E_STATE_INIT_CMDQ:402 case FORE200E_STATE_INIT_CMDQ:
403 fore200e_dma_chunk_free(fore200e, &fore200e->host_cmdq.status);403 fore200e_dma_chunk_free(fore200e, &fore200e->host_cmdq.status);
404 404
405 /* fall through */405 fallthrough;
406 case FORE200E_STATE_INITIALIZE:406 case FORE200E_STATE_INITIALIZE:
407 /* nothing to do for that state */407 /* nothing to do for that state */
408 408
@@ -415,7 +415,7 @@ fore200e_shutdown(struct fore200e* fore200e) · 6 unmodified lines
415 case FORE200E_STATE_MAP:415 case FORE200E_STATE_MAP:
416 fore200e->bus->unmap(fore200e);416 fore200e->bus->unmap(fore200e);
417 417
418 /* fall through */418 fallthrough;
419 case FORE200E_STATE_CONFIGURE:419 case FORE200E_STATE_CONFIGURE:
420 /* nothing to do for that state */420 /* nothing to do for that state */
421 421
drivers/atm/he.c+2−2
@@ -1944,14 +1944,14 @@ he_tasklet(unsigned long data) · 1943 unmodified lines
1944 switch (type) {1944 switch (type) {
1945 case ITYPE_RBRQ_THRESH:1945 case ITYPE_RBRQ_THRESH:
1946 HPRINTK("rbrq%d threshold\n", group);1946 HPRINTK("rbrq%d threshold\n", group);
1947 /* fall through */1947 fallthrough;
1948 case ITYPE_RBRQ_TIMER:1948 case ITYPE_RBRQ_TIMER:
1949 if (he_service_rbrq(he_dev, group))1949 if (he_service_rbrq(he_dev, group))
1950 he_service_rbpl(he_dev, group);1950 he_service_rbpl(he_dev, group);
1951 break;1951 break;
1952 case ITYPE_TBRQ_THRESH:1952 case ITYPE_TBRQ_THRESH:
1953 HPRINTK("tbrq%d threshold\n", group);1953 HPRINTK("tbrq%d threshold\n", group);
1954 /* fall through */1954 fallthrough;
1955 case ITYPE_TPD_COMPLETE:1955 case ITYPE_TPD_COMPLETE:
1956 he_service_tbrq(he_dev, group);1956 he_service_tbrq(he_dev, group);
1957 break;1957 break;
drivers/atm/idt77105.c+1−1
@@ -192,7 +192,7 @@ static int idt77105_ioctl(struct atm_dev *dev,unsigned int cmd,void __user *arg) · 191 unmodified lines
192 switch (cmd) {192 switch (cmd) {
193 case IDT77105_GETSTATZ:193 case IDT77105_GETSTATZ:
194 if (!capable(CAP_NET_ADMIN)) return -EPERM;194 if (!capable(CAP_NET_ADMIN)) return -EPERM;
195 /* fall through */195 fallthrough;
196 case IDT77105_GETSTAT:196 case IDT77105_GETSTAT:
197 return fetch_stats(dev, arg, cmd == IDT77105_GETSTATZ);197 return fetch_stats(dev, arg, cmd == IDT77105_GETSTATZ);
198 case ATM_SETLOOP:198 case ATM_SETLOOP:
drivers/atm/lanai.c+1−1
@@ -2019,7 +2019,7 @@ static int lanai_normalize_ci(struct lanai_dev *lanai, · 2018 unmodified lines
2019 switch (*vpip) {2019 switch (*vpip) {
2020 case ATM_VPI_ANY:2020 case ATM_VPI_ANY:
2021 *vpip = 0;2021 *vpip = 0;
2022 /* FALLTHROUGH */2022 fallthrough;
2023 case 0:2023 case 0:
2024 break;2024 break;
2025 default:2025 default:
drivers/atm/zatm.c+1−1
@@ -1447,7 +1447,7 @@ static int zatm_ioctl(struct atm_dev *dev,unsigned int cmd,void __user *arg) · 1446 unmodified lines
1447 switch (cmd) {1447 switch (cmd) {
1448 case ZATM_GETPOOLZ:1448 case ZATM_GETPOOLZ:
1449 if (!capable(CAP_NET_ADMIN)) return -EPERM;1449 if (!capable(CAP_NET_ADMIN)) return -EPERM;
1450 /* fall through */1450 fallthrough;
1451 case ZATM_GETPOOL:1451 case ZATM_GETPOOL:
1452 {1452 {
1453 struct zatm_pool_info info;1453 struct zatm_pool_info info;
drivers/auxdisplay/arm-charlcd.c+1−1
@@ -2,7 +2,7 @@ · 1 unmodified line
2/*2/*
3 * Driver for the on-board character LCD found on some ARM reference boards3 * Driver for the on-board character LCD found on some ARM reference boards
4 * This is basically an Hitachi HD44780 LCD with a custom IP block to drive it4 * This is basically an Hitachi HD44780 LCD with a custom IP block to drive it
5 * http://en.wikipedia.org/wiki/HD44780_Character_LCD5 * https://en.wikipedia.org/wiki/HD44780_Character_LCD
6 * Currently it will just display the text "ARM Linux" and the linux version6 * Currently it will just display the text "ARM Linux" and the linux version
7 *7 *
8 * Author: Linus Walleij <triad@df.lth.se>8 * Author: Linus Walleij <triad@df.lth.se>
drivers/auxdisplay/panel.c+3−3
@@ -1365,7 +1365,7 @@ static void panel_process_inputs(void) · 1364 unmodified lines
1365 break;1365 break;
1366 input->rise_timer = 0;1366 input->rise_timer = 0;
1367 input->state = INPUT_ST_RISING;1367 input->state = INPUT_ST_RISING;
1368 /* fall through */1368 fallthrough;
1369 case INPUT_ST_RISING:1369 case INPUT_ST_RISING:
1370 if ((phys_curr & input->mask) != input->value) {1370 if ((phys_curr & input->mask) != input->value) {
1371 input->state = INPUT_ST_LOW;1371 input->state = INPUT_ST_LOW;
@@ -1378,11 +1378,11 @@ static void panel_process_inputs(void) · 6 unmodified lines
1378 }1378 }
1379 input->high_timer = 0;1379 input->high_timer = 0;
1380 input->state = INPUT_ST_HIGH;1380 input->state = INPUT_ST_HIGH;
1381 /* fall through */1381 fallthrough;
1382 case INPUT_ST_HIGH:1382 case INPUT_ST_HIGH:
1383 if (input_state_high(input))1383 if (input_state_high(input))
1384 break;1384 break;
1385 /* fall through */1385 fallthrough;
1386 case INPUT_ST_FALLING:1386 case INPUT_ST_FALLING:
1387 input_state_falling(input);1387 input_state_falling(input);
1388 }1388 }
drivers/base/core.c+8−4
@@ -4264,9 +4264,9 @@ static inline bool fwnode_is_primary(struct fwnode_handle *fwnode) · 4263 unmodified lines
4264 */4264 */
4265void set_primary_fwnode(struct device *dev, struct fwnode_handle *fwnode)4265void set_primary_fwnode(struct device *dev, struct fwnode_handle *fwnode)
4266{4266{
4267 if (fwnode) {4267 struct fwnode_handle *fn = dev->fwnode;
4268 struct fwnode_handle *fn = dev->fwnode;
4269 4268
4269 if (fwnode) {
4270 if (fwnode_is_primary(fn))4270 if (fwnode_is_primary(fn))
4271 fn = fn->secondary;4271 fn = fn->secondary;
4272 4272
@@ -4276,8 +4276,12 @@ void set_primary_fwnode(struct device *dev, struct fwnode_handle *fwnode) · 3 unmodified lines
4276 }4276 }
4277 dev->fwnode = fwnode;4277 dev->fwnode = fwnode;
4278 } else {4278 } else {
4279 dev->fwnode = fwnode_is_primary(dev->fwnode) ?4279 if (fwnode_is_primary(fn)) {
4280 dev->fwnode->secondary : NULL;4280 dev->fwnode = fn->secondary;
4281 fn->secondary = NULL;
4282 } else {
4283 dev->fwnode = NULL;
4284 }
4281 }4285 }
4282}4286}
4283EXPORT_SYMBOL_GPL(set_primary_fwnode);4287EXPORT_SYMBOL_GPL(set_primary_fwnode);
drivers/base/firmware_loader/fallback.c+2−2
@@ -289,10 +289,10 @@ static ssize_t firmware_loading_store(struct device *dev, · 288 unmodified lines
289 }289 }
290 break;290 break;
291 }291 }
292 /* fallthrough */292 fallthrough;
293 default:293 default:
294 dev_err(dev, "%s: unexpected value (%d)\n", __func__, loading);294 dev_err(dev, "%s: unexpected value (%d)\n", __func__, loading);
295 /* fallthrough */295 fallthrough;
296 case -1:296 case -1:
297 fw_load_abort(fw_sysfs);297 fw_load_abort(fw_sysfs);
298 break;298 break;
drivers/base/power/main.c+10−6
@@ -1606,13 +1606,17 @@ static int __device_suspend(struct device *dev, pm_message_t state, bool async) · 1605 unmodified lines
1606 }1606 }
1607 1607
1608 /*1608 /*
1609 * If a device configured to wake up the system from sleep states1609 * Wait for possible runtime PM transitions of the device in progress
1610 * has been suspended at run time and there's a resume request pending1610 * to complete and if there's a runtime resume request pending for it,
1611 * for it, this is equivalent to the device signaling wakeup, so the1611 * resume it before proceeding with invoking the system-wide suspend
1612 * system suspend operation should be aborted.1612 * callbacks for it.
1613 *
1614 * If the system-wide suspend callbacks below change the configuration
1615 * of the device, they must disable runtime PM for it or otherwise
1616 * ensure that its runtime-resume callbacks will not be confused by that
1617 * change in case they are invoked going forward.
1613 */1618 */
1614 if (pm_runtime_barrier(dev) && device_may_wakeup(dev))1619 pm_runtime_barrier(dev);
1615 pm_wakeup_event(dev, 0);
1616 1620
1617 if (pm_wakeup_pending()) {1621 if (pm_wakeup_pending()) {
1618 dev->power.direct_complete = false;1622 dev->power.direct_complete = false;
drivers/block/aoe/aoecmd.c+1−1
@@ -1135,7 +1135,7 @@ noskb: if (buf) · 1134 unmodified lines
1135 break;1135 break;
1136 }1136 }
1137 bvcpy(skb, f->buf->bio, f->iter, n);1137 bvcpy(skb, f->buf->bio, f->iter, n);
1138 /* fall through */1138 fallthrough;
1139 case ATA_CMD_PIO_WRITE:1139 case ATA_CMD_PIO_WRITE:
1140 case ATA_CMD_PIO_WRITE_EXT:1140 case ATA_CMD_PIO_WRITE_EXT:
1141 spin_lock_irq(&d->lock);1141 spin_lock_irq(&d->lock);
drivers/block/ataflop.c+1−1
@@ -1726,7 +1726,7 @@ static int fd_locked_ioctl(struct block_device *bdev, fmode_t mode, · 1725 unmodified lines
1726 /* MSch: invalidate default_params */1726 /* MSch: invalidate default_params */
1727 default_params[drive].blocks = 0;1727 default_params[drive].blocks = 0;
1728 set_capacity(floppy->disk, MAX_DISK_SIZE * 2);1728 set_capacity(floppy->disk, MAX_DISK_SIZE * 2);
1729 /* Fall through */1729 fallthrough;
1730 case FDFMTEND:1730 case FDFMTEND:
1731 case FDFLUSH:1731 case FDFLUSH:
1732 /* invalidate the buffer track to force a reread */1732 /* invalidate the buffer track to force a reread */
drivers/block/drbd/drbd_int.h+1−1
@@ -1733,7 +1733,7 @@ static inline void __drbd_chk_io_error_(struct drbd_device *device, · 1732 unmodified lines
1733 _drbd_set_state(_NS(device, disk, D_INCONSISTENT), CS_HARD, NULL);1733 _drbd_set_state(_NS(device, disk, D_INCONSISTENT), CS_HARD, NULL);
1734 break;1734 break;
1735 }1735 }
1736 /* fall through - for DRBD_META_IO_ERROR or DRBD_FORCE_DETACH */1736 fallthrough; /* for DRBD_META_IO_ERROR or DRBD_FORCE_DETACH */
1737 case EP_DETACH:1737 case EP_DETACH:
1738 case EP_CALL_HELPER:1738 case EP_CALL_HELPER:
1739 /* Remember whether we saw a READ or WRITE error.1739 /* Remember whether we saw a READ or WRITE error.
drivers/block/drbd/drbd_main.c+1−1
@@ -430,7 +430,7 @@ int drbd_thread_start(struct drbd_thread *thi) · 429 unmodified lines
430 thi->t_state = RESTARTING;430 thi->t_state = RESTARTING;
431 drbd_info(resource, "Restarting %s thread (from %s [%d])\n",431 drbd_info(resource, "Restarting %s thread (from %s [%d])\n",
432 thi->name, current->comm, current->pid);432 thi->name, current->comm, current->pid);
433 /* fall through */433 fallthrough;
434 case RUNNING:434 case RUNNING:
435 case RESTARTING:435 case RESTARTING:
436 default:436 default:
drivers/block/drbd/drbd_nl.c+1−1
@@ -3883,7 +3883,7 @@ static int nla_put_status_info(struct sk_buff *skb, struct drbd_device *device, · 3882 unmodified lines
3883 if (nla_put_u32(skb, T_helper_exit_code,3883 if (nla_put_u32(skb, T_helper_exit_code,
3884 sib->helper_exit_code))3884 sib->helper_exit_code))
3885 goto nla_put_failure;3885 goto nla_put_failure;
3886 /* fall through */3886 fallthrough;
3887 case SIB_HELPER_PRE:3887 case SIB_HELPER_PRE:
3888 if (nla_put_string(skb, T_helper, sib->helper_name))3888 if (nla_put_string(skb, T_helper, sib->helper_name))
3889 goto nla_put_failure;3889 goto nla_put_failure;
drivers/block/drbd/drbd_receiver.c+6−6
@@ -1797,7 +1797,7 @@ static int receive_Barrier(struct drbd_connection *connection, struct packet_inf · 1796 unmodified lines
1797 break;1797 break;
1798 else1798 else
1799 drbd_warn(connection, "Allocation of an epoch failed, slowing down\n");1799 drbd_warn(connection, "Allocation of an epoch failed, slowing down\n");
1800 /* Fall through */1800 fallthrough;
1801 1801
1802 case WO_BDEV_FLUSH:1802 case WO_BDEV_FLUSH:
1803 case WO_DRAIN_IO:1803 case WO_DRAIN_IO:
@@ -2917,7 +2917,7 @@ static int receive_DataRequest(struct drbd_connection *connection, struct packet · 1113 unmodified lines
2917 then we would do something smarter here than reading2917 then we would do something smarter here than reading
2918 the block... */2918 the block... */
2919 peer_req->flags |= EE_RS_THIN_REQ;2919 peer_req->flags |= EE_RS_THIN_REQ;
2920 /* fall through */2920 fallthrough;
2921 case P_RS_DATA_REQUEST:2921 case P_RS_DATA_REQUEST:
2922 peer_req->w.cb = w_e_end_rsdata_req;2922 peer_req->w.cb = w_e_end_rsdata_req;
2923 fault_type = DRBD_FAULT_RS_RD;2923 fault_type = DRBD_FAULT_RS_RD;
@@ -3083,7 +3083,7 @@ static int drbd_asb_recover_0p(struct drbd_peer_device *peer_device) __must_hold · 159 unmodified lines
3083 rv = 1;3083 rv = 1;
3084 break;3084 break;
3085 }3085 }
3086 /* Else fall through - to one of the other strategies... */3086 fallthrough; /* to one of the other strategies */
3087 case ASB_DISCARD_OLDER_PRI:3087 case ASB_DISCARD_OLDER_PRI:
3088 if (self == 0 && peer == 1) {3088 if (self == 0 && peer == 1) {
3089 rv = 1;3089 rv = 1;
@@ -3096,7 +3096,7 @@ static int drbd_asb_recover_0p(struct drbd_peer_device *peer_device) __must_hold · 6 unmodified lines
3096 /* Else fall through to one of the other strategies... */3096 /* Else fall through to one of the other strategies... */
3097 drbd_warn(device, "Discard younger/older primary did not find a decision\n"3097 drbd_warn(device, "Discard younger/older primary did not find a decision\n"
3098 "Using discard-least-changes instead\n");3098 "Using discard-least-changes instead\n");
3099 /* fall through */3099 fallthrough;
3100 case ASB_DISCARD_ZERO_CHG:3100 case ASB_DISCARD_ZERO_CHG:
3101 if (ch_peer == 0 && ch_self == 0) {3101 if (ch_peer == 0 && ch_self == 0) {
3102 rv = test_bit(RESOLVE_CONFLICTS, &peer_device->connection->flags)3102 rv = test_bit(RESOLVE_CONFLICTS, &peer_device->connection->flags)
@@ -3108,7 +3108,7 @@ static int drbd_asb_recover_0p(struct drbd_peer_device *peer_device) __must_hold · 5 unmodified lines
3108 }3108 }
3109 if (after_sb_0p == ASB_DISCARD_ZERO_CHG)3109 if (after_sb_0p == ASB_DISCARD_ZERO_CHG)
3110 break;3110 break;
3111 /* else, fall through */3111 fallthrough;
3112 case ASB_DISCARD_LEAST_CHG:3112 case ASB_DISCARD_LEAST_CHG:
3113 if (ch_self < ch_peer)3113 if (ch_self < ch_peer)
3114 rv = -1;3114 rv = -1;
@@ -3608,7 +3608,7 @@ static enum drbd_conns drbd_sync_handshake(struct drbd_peer_device *peer_device, · 493 unmodified lines
3608 switch (rr_conflict) {3608 switch (rr_conflict) {
3609 case ASB_CALL_HELPER:3609 case ASB_CALL_HELPER:
3610 drbd_khelper(device, "pri-lost");3610 drbd_khelper(device, "pri-lost");
3611 /* fall through */3611 fallthrough;
3612 case ASB_DISCONNECT:3612 case ASB_DISCONNECT:
3613 drbd_err(device, "I shall become SyncTarget, but I am primary!\n");3613 drbd_err(device, "I shall become SyncTarget, but I am primary!\n");
3614 return C_MASK;3614 return C_MASK;
drivers/block/drbd/drbd_req.c+2−2
@@ -611,7 +611,7 @@ int __req_mod(struct drbd_request *req, enum drbd_req_event what, · 610 unmodified lines
611 drbd_set_out_of_sync(device, req->i.sector, req->i.size);611 drbd_set_out_of_sync(device, req->i.sector, req->i.size);
612 drbd_report_io_error(device, req);612 drbd_report_io_error(device, req);
613 __drbd_chk_io_error(device, DRBD_READ_ERROR);613 __drbd_chk_io_error(device, DRBD_READ_ERROR);
614 /* fall through. */614 fallthrough;
615 case READ_AHEAD_COMPLETED_WITH_ERROR:615 case READ_AHEAD_COMPLETED_WITH_ERROR:
616 /* it is legal to fail read-ahead, no __drbd_chk_io_error in that case. */616 /* it is legal to fail read-ahead, no __drbd_chk_io_error in that case. */
617 mod_rq_state(req, m, RQ_LOCAL_PENDING, RQ_LOCAL_COMPLETED);617 mod_rq_state(req, m, RQ_LOCAL_PENDING, RQ_LOCAL_COMPLETED);
@@ -836,7 +836,7 @@ int __req_mod(struct drbd_request *req, enum drbd_req_event what, · 218 unmodified lines
836 } /* else: FIXME can this happen? */836 } /* else: FIXME can this happen? */
837 break;837 break;
838 }838 }
839 /* else, fall through - to BARRIER_ACKED */839 fallthrough; /* to BARRIER_ACKED */
840 840
841 case BARRIER_ACKED:841 case BARRIER_ACKED:
842 /* barrier ack for READ requests does not make sense */842 /* barrier ack for READ requests does not make sense */
drivers/block/floppy.c+2−2
@@ -1680,7 +1680,7 @@ static void recal_interrupt(void) · 1679 unmodified lines
1680 clear_bit(FD_DISK_NEWCHANGE_BIT,1680 clear_bit(FD_DISK_NEWCHANGE_BIT,
1681 &drive_state[current_drive].flags);1681 &drive_state[current_drive].flags);
1682 drive_state[current_drive].select_date = jiffies;1682 drive_state[current_drive].select_date = jiffies;
1683 /* fall through */1683 fallthrough;
1684 default:1684 default:
1685 debugt(__func__, "default");1685 debugt(__func__, "default");
1686 /* Recalibrate moves the head by at1686 /* Recalibrate moves the head by at
@@ -3592,7 +3592,7 @@ static int fd_locked_ioctl(struct block_device *bdev, fmode_t mode, unsigned int · 1905 unmodified lines
3592 if (poll_drive(true, FD_RAW_NEED_DISK) == -EINTR)3592 if (poll_drive(true, FD_RAW_NEED_DISK) == -EINTR)
3593 return -EINTR;3593 return -EINTR;
3594 process_fd_request();3594 process_fd_request();
3595 /* fall through */3595 fallthrough;
3596 case FDGETDRVSTAT:3596 case FDGETDRVSTAT:
3597 outparam = &drive_state[drive];3597 outparam = &drive_state[drive];
3598 break;3598 break;
drivers/block/loop.c+22−19
@@ -878,6 +878,7 @@ static void loop_config_discard(struct loop_device *lo) · 877 unmodified lines
878 struct file *file = lo->lo_backing_file;878 struct file *file = lo->lo_backing_file;
879 struct inode *inode = file->f_mapping->host;879 struct inode *inode = file->f_mapping->host;
880 struct request_queue *q = lo->lo_queue;880 struct request_queue *q = lo->lo_queue;
881 u32 granularity, max_discard_sectors;
881 882
882 /*883 /*
883 * If the backing device is a block device, mirror its zeroing884 * If the backing device is a block device, mirror its zeroing
@@ -890,11 +891,10 @@ static void loop_config_discard(struct loop_device *lo) · 6 unmodified lines
890 struct request_queue *backingq;891 struct request_queue *backingq;
891 892
892 backingq = bdev_get_queue(inode->i_bdev);893 backingq = bdev_get_queue(inode->i_bdev);
893 blk_queue_max_discard_sectors(q,
894 backingq->limits.max_write_zeroes_sectors);
895 894
896 blk_queue_max_write_zeroes_sectors(q,895 max_discard_sectors = backingq->limits.max_write_zeroes_sectors;
897 backingq->limits.max_write_zeroes_sectors);896 granularity = backingq->limits.discard_granularity ?:
897 queue_physical_block_size(backingq);
898 898
899 /*899 /*
900 * We use punch hole to reclaim the free space used by the900 * We use punch hole to reclaim the free space used by the
@@ -903,23 +903,26 @@ static void loop_config_discard(struct loop_device *lo) · 2 unmodified lines
903 * useful information.903 * useful information.
904 */904 */
905 } else if (!file->f_op->fallocate || lo->lo_encrypt_key_size) {905 } else if (!file->f_op->fallocate || lo->lo_encrypt_key_size) {
906 q->limits.discard_granularity = 0;906 max_discard_sectors = 0;
907 q->limits.discard_alignment = 0;907 granularity = 0;
908 blk_queue_max_discard_sectors(q, 0);
909 blk_queue_max_write_zeroes_sectors(q, 0);
910 908
911 } else {909 } else {
912 q->limits.discard_granularity = inode->i_sb->s_blocksize;910 max_discard_sectors = UINT_MAX >> 9;
913 q->limits.discard_alignment = 0;911 granularity = inode->i_sb->s_blocksize;
914
915 blk_queue_max_discard_sectors(q, UINT_MAX >> 9);
916 blk_queue_max_write_zeroes_sectors(q, UINT_MAX >> 9);
917 }912 }
918 913
919 if (q->limits.max_write_zeroes_sectors)914 if (max_discard_sectors) {
915 q->limits.discard_granularity = granularity;
916 blk_queue_max_discard_sectors(q, max_discard_sectors);
917 blk_queue_max_write_zeroes_sectors(q, max_discard_sectors);
920 blk_queue_flag_set(QUEUE_FLAG_DISCARD, q);918 blk_queue_flag_set(QUEUE_FLAG_DISCARD, q);
921 else919 } else {
920 q->limits.discard_granularity = 0;
921 blk_queue_max_discard_sectors(q, 0);
922 blk_queue_max_write_zeroes_sectors(q, 0);
922 blk_queue_flag_clear(QUEUE_FLAG_DISCARD, q);923 blk_queue_flag_clear(QUEUE_FLAG_DISCARD, q);
924 }
925 q->limits.discard_alignment = 0;
923}926}
924 927
925static void loop_unprepare_queue(struct loop_device *lo)928static void loop_unprepare_queue(struct loop_device *lo)
@@ -1111,8 +1114,6 @@ static int loop_configure(struct loop_device *lo, fmode_t mode, · 185 unmodified lines
1111 mapping = file->f_mapping;1114 mapping = file->f_mapping;
1112 inode = mapping->host;1115 inode = mapping->host;
1113 1116
1114 size = get_loop_size(lo, file);
1115
1116 if ((config->info.lo_flags & ~LOOP_CONFIGURE_SETTABLE_FLAGS) != 0) {1117 if ((config->info.lo_flags & ~LOOP_CONFIGURE_SETTABLE_FLAGS) != 0) {
1117 error = -EINVAL;1118 error = -EINVAL;
1118 goto out_unlock;1119 goto out_unlock;
@@ -1162,6 +1163,8 @@ static int loop_configure(struct loop_device *lo, fmode_t mode, · 43 unmodified lines
1162 loop_update_rotational(lo);1163 loop_update_rotational(lo);
1163 loop_update_dio(lo);1164 loop_update_dio(lo);
1164 loop_sysfs_init(lo);1165 loop_sysfs_init(lo);
1166
1167 size = get_loop_size(lo, file);
1165 loop_set_size(lo, size);1168 loop_set_size(lo, size);
1166 1169
1167 set_blocksize(bdev, S_ISBLK(inode->i_mode) ?1170 set_blocksize(bdev, S_ISBLK(inode->i_mode) ?
@@ -1719,7 +1722,7 @@ static int lo_ioctl(struct block_device *bdev, fmode_t mode, · 551 unmodified lines
1719 case LOOP_SET_BLOCK_SIZE:1722 case LOOP_SET_BLOCK_SIZE:
1720 if (!(mode & FMODE_WRITE) && !capable(CAP_SYS_ADMIN))1723 if (!(mode & FMODE_WRITE) && !capable(CAP_SYS_ADMIN))
1721 return -EPERM;1724 return -EPERM;
1722 /* Fall through */1725 fallthrough;
1723 default:1726 default:
1724 err = lo_simple_ioctl(lo, cmd, arg);1727 err = lo_simple_ioctl(lo, cmd, arg);
1725 break;1728 break;
@@ -1867,7 +1870,7 @@ static int lo_compat_ioctl(struct block_device *bdev, fmode_t mode, · 141 unmodified lines
1867 case LOOP_SET_STATUS64:1870 case LOOP_SET_STATUS64:
1868 case LOOP_CONFIGURE:1871 case LOOP_CONFIGURE:
1869 arg = (unsigned long) compat_ptr(arg);1872 arg = (unsigned long) compat_ptr(arg);
1870 /* fall through */1873 fallthrough;
1871 case LOOP_SET_FD:1874 case LOOP_SET_FD:
1872 case LOOP_CHANGE_FD:1875 case LOOP_CHANGE_FD:
1873 case LOOP_SET_BLOCK_SIZE:1876 case LOOP_SET_BLOCK_SIZE:
drivers/block/nbd.c+2−0
@@ -1363,6 +1363,8 @@ static void nbd_set_cmd_timeout(struct nbd_device *nbd, u64 timeout) · 1362 unmodified lines
1363 nbd->tag_set.timeout = timeout * HZ;1363 nbd->tag_set.timeout = timeout * HZ;
1364 if (timeout)1364 if (timeout)
1365 blk_queue_rq_timeout(nbd->disk->queue, timeout * HZ);1365 blk_queue_rq_timeout(nbd->disk->queue, timeout * HZ);
1366 else
1367 blk_queue_rq_timeout(nbd->disk->queue, 30 * HZ);
1366}1368}
1367 1369
1368/* Must be called with config_lock held */1370/* Must be called with config_lock held */
drivers/block/null_blk_main.c+1−1
@@ -1147,7 +1147,7 @@ static int null_handle_rq(struct nullb_cmd *cmd) · 1146 unmodified lines
1147 len = bvec.bv_len;1147 len = bvec.bv_len;
1148 err = null_transfer(nullb, bvec.bv_page, len, bvec.bv_offset,1148 err = null_transfer(nullb, bvec.bv_page, len, bvec.bv_offset,
1149 op_is_write(req_op(rq)), sector,1149 op_is_write(req_op(rq)), sector,
1150 req_op(rq) & REQ_FUA);1150 rq->cmd_flags & REQ_FUA);
1151 if (err) {1151 if (err) {
1152 spin_unlock_irq(&nullb->lock);1152 spin_unlock_irq(&nullb->lock);
1153 return err;1153 return err;
drivers/block/paride/pd.c+2−2
@@ -440,7 +440,7 @@ static void run_fsm(void) · 439 unmodified lines
440 pd_claimed = 1;440 pd_claimed = 1;
441 if (!pi_schedule_claimed(pi_current, run_fsm))441 if (!pi_schedule_claimed(pi_current, run_fsm))
442 return;442 return;
443 /* fall through */443 fallthrough;
444 case 1:444 case 1:
445 pd_claimed = 2;445 pd_claimed = 2;
446 pi_current->proto->connect(pi_current);446 pi_current->proto->connect(pi_current);
@@ -465,7 +465,7 @@ static void run_fsm(void) · 18 unmodified lines
465 if (stop)465 if (stop)
466 return;466 return;
467 }467 }
468 /* fall through */468 fallthrough;
469 case Hold:469 case Hold:
470 schedule_fsm();470 schedule_fsm();
471 return;471 return;
drivers/block/pktcdvd.c+1−1
@@ -2641,7 +2641,7 @@ static int pkt_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, · 2640 unmodified lines
2641 */2641 */
2642 if (pd->refcnt == 1)2642 if (pd->refcnt == 1)
2643 pkt_lock_door(pd, 0);2643 pkt_lock_door(pd, 0);
2644 /* fall through */2644 fallthrough;
2645 /*2645 /*
2646 * forward selected CDROM ioctls to CD-ROM, for UDF2646 * forward selected CDROM ioctls to CD-ROM, for UDF
2647 */2647 */
drivers/block/rbd.c+4−4
@@ -3293,7 +3293,7 @@ again: · 3292 unmodified lines
3293 case __RBD_OBJ_COPYUP_OBJECT_MAPS:3293 case __RBD_OBJ_COPYUP_OBJECT_MAPS:
3294 if (!pending_result_dec(&obj_req->pending, result))3294 if (!pending_result_dec(&obj_req->pending, result))
3295 return false;3295 return false;
3296 /* fall through */3296 fallthrough;
3297 case RBD_OBJ_COPYUP_OBJECT_MAPS:3297 case RBD_OBJ_COPYUP_OBJECT_MAPS:
3298 if (*result) {3298 if (*result) {
3299 rbd_warn(rbd_dev, "snap object map update failed: %d",3299 rbd_warn(rbd_dev, "snap object map update failed: %d",
@@ -3312,7 +3312,7 @@ again: · 12 unmodified lines
3312 case __RBD_OBJ_COPYUP_WRITE_OBJECT:3312 case __RBD_OBJ_COPYUP_WRITE_OBJECT:
3313 if (!pending_result_dec(&obj_req->pending, result))3313 if (!pending_result_dec(&obj_req->pending, result))
3314 return false;3314 return false;
3315 /* fall through */3315 fallthrough;
3316 case RBD_OBJ_COPYUP_WRITE_OBJECT:3316 case RBD_OBJ_COPYUP_WRITE_OBJECT:
3317 return true;3317 return true;
3318 default:3318 default:
@@ -3399,7 +3399,7 @@ again: · 80 unmodified lines
3399 case __RBD_OBJ_WRITE_COPYUP:3399 case __RBD_OBJ_WRITE_COPYUP:
3400 if (!rbd_obj_advance_copyup(obj_req, result))3400 if (!rbd_obj_advance_copyup(obj_req, result))
3401 return false;3401 return false;
3402 /* fall through */3402 fallthrough;
3403 case RBD_OBJ_WRITE_COPYUP:3403 case RBD_OBJ_WRITE_COPYUP:
3404 if (*result) {3404 if (*result) {
3405 rbd_warn(rbd_dev, "copyup failed: %d", *result);3405 rbd_warn(rbd_dev, "copyup failed: %d", *result);
@@ -3592,7 +3592,7 @@ again: · 186 unmodified lines
3592 case __RBD_IMG_OBJECT_REQUESTS:3592 case __RBD_IMG_OBJECT_REQUESTS:
3593 if (!pending_result_dec(&img_req->pending, result))3593 if (!pending_result_dec(&img_req->pending, result))
3594 return false;3594 return false;
3595 /* fall through */3595 fallthrough;
3596 case RBD_IMG_OBJECT_REQUESTS:3596 case RBD_IMG_OBJECT_REQUESTS:
3597 return true;3597 return true;
3598 default:3598 default:
drivers/block/rnbd/rnbd-srv.c+2−1
@@ -148,7 +148,8 @@ static int process_rdma(struct rtrs_srv *sess, · 147 unmodified lines
148 /* Generate bio with pages pointing to the rdma buffer */148 /* Generate bio with pages pointing to the rdma buffer */
149 bio = rnbd_bio_map_kern(data, sess_dev->rnbd_dev->ibd_bio_set, datalen, GFP_KERNEL);149 bio = rnbd_bio_map_kern(data, sess_dev->rnbd_dev->ibd_bio_set, datalen, GFP_KERNEL);
150 if (IS_ERR(bio)) {150 if (IS_ERR(bio)) {
151 rnbd_srv_err(sess_dev, "Failed to generate bio, err: %ld\n", PTR_ERR(bio));151 err = PTR_ERR(bio);
152 rnbd_srv_err(sess_dev, "Failed to generate bio, err: %d\n", err);
152 goto sess_dev_put;153 goto sess_dev_put;
153 }154 }
154 155
drivers/block/rsxx/core.c+1−1
@@ -425,7 +425,7 @@ static void card_state_change(struct rsxx_cardinfo *card, · 424 unmodified lines
425 * Fall through so the DMA devices can be attached and425 * Fall through so the DMA devices can be attached and
426 * the user can attempt to pull off their data.426 * the user can attempt to pull off their data.
427 */427 */
428 /* fall through */428 fallthrough;
429 case CARD_STATE_GOOD:429 case CARD_STATE_GOOD:
430 st = rsxx_get_card_size8(card, &card->size8);430 st = rsxx_get_card_size8(card, &card->size8);
431 if (st)431 if (st)
drivers/block/skd_main.c+1−1
@@ -1436,7 +1436,7 @@ static void skd_resolve_req_exception(struct skd_device *skdev, · 1435 unmodified lines
1436 blk_mq_requeue_request(req, true);1436 blk_mq_requeue_request(req, true);
1437 break;1437 break;
1438 }1438 }
1439 /* fall through */1439 fallthrough;
1440 1440
1441 case SKD_CHECK_STATUS_REPORT_ERROR:1441 case SKD_CHECK_STATUS_REPORT_ERROR:
1442 default:1442 default:
drivers/block/virtio_blk.c+23−8
@@ -126,16 +126,31 @@ static int virtblk_setup_discard_write_zeroes(struct request *req, bool unmap) · 125 unmodified lines
126 if (!range)126 if (!range)
127 return -ENOMEM;127 return -ENOMEM;
128 128
129 __rq_for_each_bio(bio, req) {129 /*
130 u64 sector = bio->bi_iter.bi_sector;130 * Single max discard segment means multi-range discard isn't
131 u32 num_sectors = bio->bi_iter.bi_size >> SECTOR_SHIFT;131 * supported, and block layer only runs contiguity merge like
132 132 * normal RW request. So we can't reply on bio for retrieving
133 range[n].flags = cpu_to_le32(flags);133 * each range info.
134 range[n].num_sectors = cpu_to_le32(num_sectors);134 */
135 range[n].sector = cpu_to_le64(sector);135 if (queue_max_discard_segments(req->q) == 1) {
136 n++;136 range[0].flags = cpu_to_le32(flags);
137 range[0].num_sectors = cpu_to_le32(blk_rq_sectors(req));
138 range[0].sector = cpu_to_le64(blk_rq_pos(req));
139 n = 1;
140 } else {
141 __rq_for_each_bio(bio, req) {
142 u64 sector = bio->bi_iter.bi_sector;
143 u32 num_sectors = bio->bi_iter.bi_size >> SECTOR_SHIFT;
144
145 range[n].flags = cpu_to_le32(flags);
146 range[n].num_sectors = cpu_to_le32(num_sectors);
147 range[n].sector = cpu_to_le64(sector);
148 n++;
149 }
137 }150 }
138 151
152 WARN_ON_ONCE(n != segments);
153
139 req->special_vec.bv_page = virt_to_page(range);154 req->special_vec.bv_page = virt_to_page(range);
140 req->special_vec.bv_offset = offset_in_page(range);155 req->special_vec.bv_offset = offset_in_page(range);
141 req->special_vec.bv_len = sizeof(*range) * segments;156 req->special_vec.bv_len = sizeof(*range) * segments;
drivers/block/xen-blkback/blkback.c+1−1
@@ -1260,7 +1260,7 @@ static int dispatch_rw_block_io(struct xen_blkif_ring *ring, · 1259 unmodified lines
1260 break;1260 break;
1261 case BLKIF_OP_WRITE_BARRIER:1261 case BLKIF_OP_WRITE_BARRIER:
1262 drain = true;1262 drain = true;
1263 /* fall through */1263 fallthrough;
1264 case BLKIF_OP_FLUSH_DISKCACHE:1264 case BLKIF_OP_FLUSH_DISKCACHE:
1265 ring->st_f_req++;1265 ring->st_f_req++;
1266 operation = REQ_OP_WRITE;1266 operation = REQ_OP_WRITE;
drivers/block/xen-blkback/xenbus.c+1−1
@@ -843,7 +843,7 @@ static void frontend_changed(struct xenbus_device *dev, · 842 unmodified lines
843 xenbus_switch_state(dev, XenbusStateClosed);843 xenbus_switch_state(dev, XenbusStateClosed);
844 if (xenbus_dev_is_online(dev))844 if (xenbus_dev_is_online(dev))
845 break;845 break;
846 /* fall through */846 fallthrough;
847 /* if not online */847 /* if not online */
848 case XenbusStateUnknown:848 case XenbusStateUnknown:
849 /* implies xen_blkif_disconnect() via xen_blkbk_remove() */849 /* implies xen_blkif_disconnect() via xen_blkbk_remove() */
drivers/block/xen-blkfront.c+2−3
@@ -1403,7 +1403,6 @@ static enum blk_req_status blkif_rsp_to_req_status(int rsp) · 1402 unmodified lines
1403 case BLKIF_RSP_EOPNOTSUPP:1403 case BLKIF_RSP_EOPNOTSUPP:
1404 return REQ_EOPNOTSUPP;1404 return REQ_EOPNOTSUPP;
1405 case BLKIF_RSP_ERROR:1405 case BLKIF_RSP_ERROR:
1406 /* Fallthrough. */
1407 default:1406 default:
1408 return REQ_ERROR;1407 return REQ_ERROR;
1409 }1408 }
@@ -1643,7 +1642,7 @@ static irqreturn_t blkif_interrupt(int irq, void *dev_id) · 233 unmodified lines
1643 info->feature_flush = 0;1642 info->feature_flush = 0;
1644 xlvbd_flush(info);1643 xlvbd_flush(info);
1645 }1644 }
1646 /* fall through */1645 fallthrough;
1647 case BLKIF_OP_READ:1646 case BLKIF_OP_READ:
1648 case BLKIF_OP_WRITE:1647 case BLKIF_OP_WRITE:
1649 if (unlikely(bret->status != BLKIF_RSP_OKAY))1648 if (unlikely(bret->status != BLKIF_RSP_OKAY))
@@ -2484,7 +2483,7 @@ static void blkback_changed(struct xenbus_device *dev, · 834 unmodified lines
2484 case XenbusStateClosed:2483 case XenbusStateClosed:
2485 if (dev->state == XenbusStateClosed)2484 if (dev->state == XenbusStateClosed)
2486 break;2485 break;
2487 /* fall through */2486 fallthrough;
2488 case XenbusStateClosing:2487 case XenbusStateClosing:
2489 if (info)2488 if (info)
2490 blkfront_closing(info);2489 blkfront_closing(info);
drivers/bus/ti-sysc.c+1−1
@@ -1849,7 +1849,7 @@ static int sysc_clockdomain_init(struct sysc *ddata) · 1848 unmodified lines
1849 switch (ddata->nr_clocks) {1849 switch (ddata->nr_clocks) {
1850 case 2:1850 case 2:
1851 ick = ddata->clocks[SYSC_ICK];1851 ick = ddata->clocks[SYSC_ICK];
1852 /* fallthrough */1852 fallthrough;
1853 case 1:1853 case 1:
1854 fck = ddata->clocks[SYSC_FCK];1854 fck = ddata->clocks[SYSC_FCK];
1855 break;1855 break;
drivers/char/agp/ali-agp.c+1−1
@@ -357,7 +357,7 @@ found: · 356 unmodified lines
357 default:357 default:
358 break;358 break;
359 }359 }
360 /*FALLTHROUGH*/360 fallthrough;
361 default:361 default:
362 bridge->driver = &ali_generic_bridge;362 bridge->driver = &ali_generic_bridge;
363 }363 }
drivers/char/hw_random/ingenic-rng.c+2−7
@@ -92,8 +92,7 @@ static int ingenic_rng_probe(struct platform_device *pdev) · 91 unmodified lines
92 priv->base = devm_platform_ioremap_resource(pdev, 0);92 priv->base = devm_platform_ioremap_resource(pdev, 0);
93 if (IS_ERR(priv->base)) {93 if (IS_ERR(priv->base)) {
94 pr_err("%s: Failed to map RNG registers\n", __func__);94 pr_err("%s: Failed to map RNG registers\n", __func__);
95 ret = PTR_ERR(priv->base);95 return PTR_ERR(priv->base);
96 goto err_free_rng;
97 }96 }
98 97
99 priv->version = (enum ingenic_rng_version)of_device_get_match_data(&pdev->dev);98 priv->version = (enum ingenic_rng_version)of_device_get_match_data(&pdev->dev);
@@ -106,17 +105,13 @@ static int ingenic_rng_probe(struct platform_device *pdev) · 6 unmodified lines
106 ret = hwrng_register(&priv->rng);105 ret = hwrng_register(&priv->rng);
107 if (ret) {106 if (ret) {
108 dev_err(&pdev->dev, "Failed to register hwrng\n");107 dev_err(&pdev->dev, "Failed to register hwrng\n");
109 goto err_free_rng;108 return ret;
110 }109 }
111 110
112 platform_set_drvdata(pdev, priv);111 platform_set_drvdata(pdev, priv);
113 112
114 dev_info(&pdev->dev, "Ingenic RNG driver registered\n");113 dev_info(&pdev->dev, "Ingenic RNG driver registered\n");
115 return 0;114 return 0;
116
117err_free_rng:
118 kfree(priv);
119 return ret;
120}115}
121 116
122static int ingenic_rng_remove(struct platform_device *pdev)117static int ingenic_rng_remove(struct platform_device *pdev)
drivers/char/ipmi/kcs_bmc.c+1−1
@@ -99,7 +99,7 @@ static void kcs_bmc_handle_data(struct kcs_bmc *kcs_bmc) · 98 unmodified lines
99 switch (kcs_bmc->phase) {99 switch (kcs_bmc->phase) {
100 case KCS_PHASE_WRITE_START:100 case KCS_PHASE_WRITE_START:
101 kcs_bmc->phase = KCS_PHASE_WRITE_DATA;101 kcs_bmc->phase = KCS_PHASE_WRITE_DATA;
102 /* fall through */102 fallthrough;
103 103
104 case KCS_PHASE_WRITE_DATA:104 case KCS_PHASE_WRITE_DATA:
105 if (kcs_bmc->data_in_idx < KCS_MSG_BUFSIZ) {105 if (kcs_bmc->data_in_idx < KCS_MSG_BUFSIZ) {
drivers/char/lp.c+2−2
@@ -734,7 +734,7 @@ static long lp_ioctl(struct file *file, unsigned int cmd, · 733 unmodified lines
734 ret = lp_set_timeout32(minor, (void __user *)arg);734 ret = lp_set_timeout32(minor, (void __user *)arg);
735 break;735 break;
736 }736 }
737 /* fall through - for 64-bit */737 fallthrough; /* for 64-bit */
738 case LPSETTIMEOUT_NEW:738 case LPSETTIMEOUT_NEW:
739 ret = lp_set_timeout64(minor, (void __user *)arg);739 ret = lp_set_timeout64(minor, (void __user *)arg);
740 break;740 break;
@@ -762,7 +762,7 @@ static long lp_compat_ioctl(struct file *file, unsigned int cmd, · 21 unmodified lines
762 ret = lp_set_timeout32(minor, (void __user *)arg);762 ret = lp_set_timeout32(minor, (void __user *)arg);
763 break;763 break;
764 }764 }
765 /* fall through - for x32 mode */765 fallthrough; /* for x32 mode */
766 case LPSETTIMEOUT_NEW:766 case LPSETTIMEOUT_NEW:
767 ret = lp_set_timeout64(minor, (void __user *)arg);767 ret = lp_set_timeout64(minor, (void __user *)arg);
768 break;768 break;
drivers/char/mem.c+1−1
@@ -791,7 +791,7 @@ static loff_t memory_lseek(struct file *file, loff_t offset, int orig) · 790 unmodified lines
791 switch (orig) {791 switch (orig) {
792 case SEEK_CUR:792 case SEEK_CUR:
793 offset += file->f_pos;793 offset += file->f_pos;
794 /* fall through */794 fallthrough;
795 case SEEK_SET:795 case SEEK_SET:
796 /* to avoid userland mistaking f_pos=-9 as -EBADF=-9 */796 /* to avoid userland mistaking f_pos=-9 as -EBADF=-9 */
797 if ((unsigned long long)offset >= -MAX_ERRNO) {797 if ((unsigned long long)offset >= -MAX_ERRNO) {
drivers/char/nvram.c+1−1
@@ -286,7 +286,7 @@ static long nvram_misc_ioctl(struct file *file, unsigned int cmd, · 285 unmodified lines
286#ifdef CONFIG_PPC286#ifdef CONFIG_PPC
287 case OBSOLETE_PMAC_NVRAM_GET_OFFSET:287 case OBSOLETE_PMAC_NVRAM_GET_OFFSET:
288 pr_warn("nvram: Using obsolete PMAC_NVRAM_GET_OFFSET ioctl\n");288 pr_warn("nvram: Using obsolete PMAC_NVRAM_GET_OFFSET ioctl\n");
289 /* fall through */289 fallthrough;
290 case IOC_NVRAM_GET_OFFSET:290 case IOC_NVRAM_GET_OFFSET:
291 ret = -EINVAL;291 ret = -EINVAL;
292#ifdef CONFIG_PPC_PMAC292#ifdef CONFIG_PPC_PMAC
drivers/clocksource/Kconfig+10−2
@@ -653,9 +653,8 @@ config ATCPIT100_TIMER · 652 unmodified lines
653 This option enables support for the Andestech ATCPIT100 timers.653 This option enables support for the Andestech ATCPIT100 timers.
654 654
655config RISCV_TIMER655config RISCV_TIMER
656 bool "Timer for the RISC-V platform"656 bool "Timer for the RISC-V platform" if COMPILE_TEST
657 depends on GENERIC_SCHED_CLOCK && RISCV657 depends on GENERIC_SCHED_CLOCK && RISCV
658 default y
659 select TIMER_PROBE658 select TIMER_PROBE
660 select TIMER_OF659 select TIMER_OF
661 help660 help
@@ -663,6 +662,15 @@ config RISCV_TIMER · 1 unmodified line
663 is accessed via both the SBI and the rdcycle instruction. This is662 is accessed via both the SBI and the rdcycle instruction. This is
664 required for all RISC-V systems.663 required for all RISC-V systems.
665 664
665config CLINT_TIMER
666 bool "CLINT Timer for the RISC-V platform" if COMPILE_TEST
667 depends on GENERIC_SCHED_CLOCK && RISCV
668 select TIMER_PROBE
669 select TIMER_OF
670 help
671 This option enables the CLINT timer for RISC-V systems. The CLINT
672 driver is usually used for NoMMU RISC-V systems.
673
666config CSKY_MP_TIMER674config CSKY_MP_TIMER
667 bool "SMP Timer for the C-SKY platform" if COMPILE_TEST675 bool "SMP Timer for the C-SKY platform" if COMPILE_TEST
668 depends on CSKY676 depends on CSKY
drivers/clocksource/Makefile+1−0
@@ -89,6 +89,7 @@ obj-$(CONFIG_CLKSRC_ST_LPC) += clksrc_st_lpc.o · 88 unmodified lines
89obj-$(CONFIG_X86_NUMACHIP) += numachip.o89obj-$(CONFIG_X86_NUMACHIP) += numachip.o
90obj-$(CONFIG_ATCPIT100_TIMER) += timer-atcpit100.o90obj-$(CONFIG_ATCPIT100_TIMER) += timer-atcpit100.o
91obj-$(CONFIG_RISCV_TIMER) += timer-riscv.o91obj-$(CONFIG_RISCV_TIMER) += timer-riscv.o
92obj-$(CONFIG_CLINT_TIMER) += timer-clint.o
92obj-$(CONFIG_CSKY_MP_TIMER) += timer-mp-csky.o93obj-$(CONFIG_CSKY_MP_TIMER) += timer-mp-csky.o
93obj-$(CONFIG_GX6605S_TIMER) += timer-gx6605s.o94obj-$(CONFIG_GX6605S_TIMER) += timer-gx6605s.o
94obj-$(CONFIG_HYPERV_TIMER) += hyperv_timer.o95obj-$(CONFIG_HYPERV_TIMER) += hyperv_timer.o
drivers/clocksource/timer-cadence-ttc.c+2−2
@@ -309,7 +309,7 @@ static int ttc_rate_change_clocksource_cb(struct notifier_block *nb, · 308 unmodified lines
309 /* restore original register value */309 /* restore original register value */
310 writel_relaxed(ttccs->scale_clk_ctrl_reg_old,310 writel_relaxed(ttccs->scale_clk_ctrl_reg_old,
311 ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);311 ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
312 /* fall through */312 fallthrough;
313 default:313 default:
314 return NOTIFY_DONE;314 return NOTIFY_DONE;
315 }315 }
@@ -392,7 +392,7 @@ static int ttc_rate_change_clockevent_cb(struct notifier_block *nb, · 76 unmodified lines
392 392
393 clockevents_update_freq(&ttcce->ce, ndata->new_rate / PRESCALE);393 clockevents_update_freq(&ttcce->ce, ndata->new_rate / PRESCALE);
394 394
395 /* fall through */395 fallthrough;
396 case PRE_RATE_CHANGE:396 case PRE_RATE_CHANGE:
397 case ABORT_RATE_CHANGE:397 case ABORT_RATE_CHANGE:
398 default:398 default:
drivers/clocksource/timer-clint.c+226−0
@@ -0,0 +1,226 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2020 Western Digital Corporation or its affiliates.
4 *
5 * Most of the M-mode (i.e. NoMMU) RISC-V systems usually have a
6 * CLINT MMIO timer device.
7 */
8
9#define pr_fmt(fmt) "clint: " fmt
10#include <linux/bitops.h>
11#include <linux/clocksource.h>
12#include <linux/clockchips.h>
13#include <linux/cpu.h>
14#include <linux/delay.h>
15#include <linux/module.h>
16#include <linux/of_address.h>
17#include <linux/sched_clock.h>
18#include <linux/io-64-nonatomic-lo-hi.h>
19#include <linux/interrupt.h>
20#include <linux/of_irq.h>
21#include <linux/smp.h>
22
23#define CLINT_IPI_OFF 0
24#define CLINT_TIMER_CMP_OFF 0x4000
25#define CLINT_TIMER_VAL_OFF 0xbff8
26
27/* CLINT manages IPI and Timer for RISC-V M-mode */
28static u32 __iomem *clint_ipi_base;
29static u64 __iomem *clint_timer_cmp;
30static u64 __iomem *clint_timer_val;
31static unsigned long clint_timer_freq;
32static unsigned int clint_timer_irq;
33
34static void clint_send_ipi(const struct cpumask *target)
35{
36 unsigned int cpu;
37
38 for_each_cpu(cpu, target)
39 writel(1, clint_ipi_base + cpuid_to_hartid_map(cpu));
40}
41
42static void clint_clear_ipi(void)
43{
44 writel(0, clint_ipi_base + cpuid_to_hartid_map(smp_processor_id()));
45}
46
47static struct riscv_ipi_ops clint_ipi_ops = {
48 .ipi_inject = clint_send_ipi,
49 .ipi_clear = clint_clear_ipi,
50};
51
52#ifdef CONFIG_64BIT
53#define clint_get_cycles() readq_relaxed(clint_timer_val)
54#else
55#define clint_get_cycles() readl_relaxed(clint_timer_val)
56#define clint_get_cycles_hi() readl_relaxed(((u32 *)clint_timer_val) + 1)
57#endif
58
59#ifdef CONFIG_64BIT
60static u64 notrace clint_get_cycles64(void)
61{
62 return clint_get_cycles();
63}
64#else /* CONFIG_64BIT */
65static u64 notrace clint_get_cycles64(void)
66{
67 u32 hi, lo;
68
69 do {
70 hi = clint_get_cycles_hi();
71 lo = clint_get_cycles();
72 } while (hi != clint_get_cycles_hi());
73
74 return ((u64)hi << 32) | lo;
75}
76#endif /* CONFIG_64BIT */
77
78static u64 clint_rdtime(struct clocksource *cs)
79{
80 return clint_get_cycles64();
81}
82
83static struct clocksource clint_clocksource = {
84 .name = "clint_clocksource",
85 .rating = 300,
86 .mask = CLOCKSOURCE_MASK(64),
87 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
88 .read = clint_rdtime,
89};
90
91static int clint_clock_next_event(unsigned long delta,
92 struct clock_event_device *ce)
93{
94 void __iomem *r = clint_timer_cmp +
95 cpuid_to_hartid_map(smp_processor_id());
96
97 csr_set(CSR_IE, IE_TIE);
98 writeq_relaxed(clint_get_cycles64() + delta, r);
99 return 0;
100}
101
102static DEFINE_PER_CPU(struct clock_event_device, clint_clock_event) = {
103 .name = "clint_clockevent",
104 .features = CLOCK_EVT_FEAT_ONESHOT,
105 .rating = 100,
106 .set_next_event = clint_clock_next_event,
107};
108
109static int clint_timer_starting_cpu(unsigned int cpu)
110{
111 struct clock_event_device *ce = per_cpu_ptr(&clint_clock_event, cpu);
112
113 ce->cpumask = cpumask_of(cpu);
114 clockevents_config_and_register(ce, clint_timer_freq, 100, 0x7fffffff);
115
116 enable_percpu_irq(clint_timer_irq,
117 irq_get_trigger_type(clint_timer_irq));
118 return 0;
119}
120
121static int clint_timer_dying_cpu(unsigned int cpu)
122{
123 disable_percpu_irq(clint_timer_irq);
124 return 0;
125}
126
127static irqreturn_t clint_timer_interrupt(int irq, void *dev_id)
128{
129 struct clock_event_device *evdev = this_cpu_ptr(&clint_clock_event);
130
131 csr_clear(CSR_IE, IE_TIE);
132 evdev->event_handler(evdev);
133
134 return IRQ_HANDLED;
135}
136
137static int __init clint_timer_init_dt(struct device_node *np)
138{
139 int rc;
140 u32 i, nr_irqs;
141 void __iomem *base;
142 struct of_phandle_args oirq;
143
144 /*
145 * Ensure that CLINT device interrupts are either RV_IRQ_TIMER or
146 * RV_IRQ_SOFT. If it's anything else then we ignore the device.
147 */
148 nr_irqs = of_irq_count(np);
149 for (i = 0; i < nr_irqs; i++) {
150 if (of_irq_parse_one(np, i, &oirq)) {
151 pr_err("%pOFP: failed to parse irq %d.\n", np, i);
152 continue;
153 }
154
155 if ((oirq.args_count != 1) ||
156 (oirq.args[0] != RV_IRQ_TIMER &&
157 oirq.args[0] != RV_IRQ_SOFT)) {
158 pr_err("%pOFP: invalid irq %d (hwirq %d)\n",
159 np, i, oirq.args[0]);
160 return -ENODEV;
161 }
162
163 /* Find parent irq domain and map timer irq */
164 if (!clint_timer_irq &&
165 oirq.args[0] == RV_IRQ_TIMER &&
166 irq_find_host(oirq.np))
167 clint_timer_irq = irq_of_parse_and_map(np, i);
168 }
169
170 /* If CLINT timer irq not found then fail */
171 if (!clint_timer_irq) {
172 pr_err("%pOFP: timer irq not found\n", np);
173 return -ENODEV;
174 }
175
176 base = of_iomap(np, 0);
177 if (!base) {
178 pr_err("%pOFP: could not map registers\n", np);
179 return -ENODEV;
180 }
181
182 clint_ipi_base = base + CLINT_IPI_OFF;
183 clint_timer_cmp = base + CLINT_TIMER_CMP_OFF;
184 clint_timer_val = base + CLINT_TIMER_VAL_OFF;
185 clint_timer_freq = riscv_timebase;
186
187 pr_info("%pOFP: timer running at %ld Hz\n", np, clint_timer_freq);
188
189 rc = clocksource_register_hz(&clint_clocksource, clint_timer_freq);
190 if (rc) {
191 pr_err("%pOFP: clocksource register failed [%d]\n", np, rc);
192 goto fail_iounmap;
193 }
194
195 sched_clock_register(clint_get_cycles64, 64, clint_timer_freq);
196
197 rc = request_percpu_irq(clint_timer_irq, clint_timer_interrupt,
198 "clint-timer", &clint_clock_event);
199 if (rc) {
200 pr_err("registering percpu irq failed [%d]\n", rc);
201 goto fail_iounmap;
202 }
203
204 rc = cpuhp_setup_state(CPUHP_AP_CLINT_TIMER_STARTING,
205 "clockevents/clint/timer:starting",
206 clint_timer_starting_cpu,
207 clint_timer_dying_cpu);
208 if (rc) {
209 pr_err("%pOFP: cpuhp setup state failed [%d]\n", np, rc);
210 goto fail_free_irq;
211 }
212
213 riscv_set_ipi_ops(&clint_ipi_ops);
214 clint_clear_ipi();
215
216 return 0;
217
218fail_free_irq:
219 free_irq(clint_timer_irq, &clint_clock_event);
220fail_iounmap:
221 iounmap(base);
222 return rc;
223}
224
225TIMER_OF_DECLARE(clint_timer, "riscv,clint0", clint_timer_init_dt);
226TIMER_OF_DECLARE(clint_timer1, "sifive,clint0", clint_timer_init_dt);
drivers/clocksource/timer-riscv.c+2−15
@@ -19,26 +19,13 @@ · 18 unmodified lines
19#include <linux/of_irq.h>19#include <linux/of_irq.h>
20#include <asm/smp.h>20#include <asm/smp.h>
21#include <asm/sbi.h>21#include <asm/sbi.h>
22 22#include <asm/timex.h>
23u64 __iomem *riscv_time_cmp;
24u64 __iomem *riscv_time_val;
25
26static inline void mmio_set_timer(u64 val)
27{
28 void __iomem *r;
29
30 r = riscv_time_cmp + cpuid_to_hartid_map(smp_processor_id());
31 writeq_relaxed(val, r);
32}
33 23
34static int riscv_clock_next_event(unsigned long delta,24static int riscv_clock_next_event(unsigned long delta,
35 struct clock_event_device *ce)25 struct clock_event_device *ce)
36{26{
37 csr_set(CSR_IE, IE_TIE);27 csr_set(CSR_IE, IE_TIE);
38 if (IS_ENABLED(CONFIG_RISCV_SBI))28 sbi_set_timer(get_cycles64() + delta);
39 sbi_set_timer(get_cycles64() + delta);
40 else
41 mmio_set_timer(get_cycles64() + delta);
42 return 0;29 return 0;
43}30}
44 31
drivers/cpufreq/cpufreq.c+1−2
@@ -703,8 +703,7 @@ static ssize_t show_scaling_cur_freq(struct cpufreq_policy *policy, char *buf) · 702 unmodified lines
703 freq = arch_freq_get_on_cpu(policy->cpu);703 freq = arch_freq_get_on_cpu(policy->cpu);
704 if (freq)704 if (freq)
705 ret = sprintf(buf, "%u\n", freq);705 ret = sprintf(buf, "%u\n", freq);
706 else if (cpufreq_driver && cpufreq_driver->setpolicy &&706 else if (cpufreq_driver->setpolicy && cpufreq_driver->get)
707 cpufreq_driver->get)
708 ret = sprintf(buf, "%u\n", cpufreq_driver->get(policy->cpu));707 ret = sprintf(buf, "%u\n", cpufreq_driver->get(policy->cpu));
709 else708 else
710 ret = sprintf(buf, "%u\n", policy->cur);709 ret = sprintf(buf, "%u\n", policy->cur);
drivers/cpufreq/intel_pstate.c+148−88
@@ -219,14 +219,13 @@ struct global_params { · 218 unmodified lines
219 * @epp_policy: Last saved policy used to set EPP/EPB219 * @epp_policy: Last saved policy used to set EPP/EPB
220 * @epp_default: Power on default HWP energy performance220 * @epp_default: Power on default HWP energy performance
221 * preference/bias221 * preference/bias
222 * @epp_saved: Saved EPP/EPB during system suspend or CPU offline
223 * operation
224 * @epp_cached Cached HWP energy-performance preference value222 * @epp_cached Cached HWP energy-performance preference value
225 * @hwp_req_cached: Cached value of the last HWP Request MSR223 * @hwp_req_cached: Cached value of the last HWP Request MSR
226 * @hwp_cap_cached: Cached value of the last HWP Capabilities MSR224 * @hwp_cap_cached: Cached value of the last HWP Capabilities MSR
227 * @last_io_update: Last time when IO wake flag was set225 * @last_io_update: Last time when IO wake flag was set
228 * @sched_flags: Store scheduler flags for possible cross CPU update226 * @sched_flags: Store scheduler flags for possible cross CPU update
229 * @hwp_boost_min: Last HWP boosted min performance227 * @hwp_boost_min: Last HWP boosted min performance
228 * @suspended: Whether or not the driver has been suspended.
230 *229 *
231 * This structure stores per CPU instance data for all CPUs.230 * This structure stores per CPU instance data for all CPUs.
232 */231 */
@@ -258,13 +257,13 @@ struct cpudata { · 25 unmodified lines
258 s16 epp_powersave;257 s16 epp_powersave;
259 s16 epp_policy;258 s16 epp_policy;
260 s16 epp_default;259 s16 epp_default;
261 s16 epp_saved;
262 s16 epp_cached;260 s16 epp_cached;
263 u64 hwp_req_cached;261 u64 hwp_req_cached;
264 u64 hwp_cap_cached;262 u64 hwp_cap_cached;
265 u64 last_io_update;263 u64 last_io_update;
266 unsigned int sched_flags;264 unsigned int sched_flags;
267 u32 hwp_boost_min;265 u32 hwp_boost_min;
266 bool suspended;
268};267};
269 268
270static struct cpudata **all_cpu_data;269static struct cpudata **all_cpu_data;
@@ -644,6 +643,8 @@ static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data, int *raw · 373 unmodified lines
644 643
645static int intel_pstate_set_epp(struct cpudata *cpu, u32 epp)644static int intel_pstate_set_epp(struct cpudata *cpu, u32 epp)
646{645{
646 int ret;
647
647 /*648 /*
648 * Use the cached HWP Request MSR value, because in the active mode the649 * Use the cached HWP Request MSR value, because in the active mode the
649 * register itself may be updated by intel_pstate_hwp_boost_up() or650 * register itself may be updated by intel_pstate_hwp_boost_up() or
@@ -659,7 +660,11 @@ static int intel_pstate_set_epp(struct cpudata *cpu, u32 epp) · 9 unmodified lines
659 * function, so it cannot run in parallel with the update below.660 * function, so it cannot run in parallel with the update below.
660 */661 */
661 WRITE_ONCE(cpu->hwp_req_cached, value);662 WRITE_ONCE(cpu->hwp_req_cached, value);
662 return wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);663 ret = wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
664 if (!ret)
665 cpu->epp_cached = epp;
666
667 return ret;
663}668}
664 669
665static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,670static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
@@ -678,6 +683,14 @@ static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data, · 12 unmodified lines
678 else if (epp == -EINVAL)683 else if (epp == -EINVAL)
679 epp = epp_values[pref_index - 1];684 epp = epp_values[pref_index - 1];
680 685
686 /*
687 * To avoid confusion, refuse to set EPP to any values different
688 * from 0 (performance) if the current policy is "performance",
689 * because those values would be overridden.
690 */
691 if (epp > 0 && cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
692 return -EBUSY;
693
681 ret = intel_pstate_set_epp(cpu_data, epp);694 ret = intel_pstate_set_epp(cpu_data, epp);
682 } else {695 } else {
683 if (epp == -EINVAL)696 if (epp == -EINVAL)
@@ -762,10 +775,8 @@ static ssize_t store_energy_performance_preference( · 78 unmodified lines
762 cpufreq_stop_governor(policy);775 cpufreq_stop_governor(policy);
763 ret = intel_pstate_set_epp(cpu, epp);776 ret = intel_pstate_set_epp(cpu, epp);
764 err = cpufreq_start_governor(policy);777 err = cpufreq_start_governor(policy);
765 if (!ret) {778 if (!ret)
766 cpu->epp_cached = epp;
767 ret = err;779 ret = err;
768 }
769 }780 }
770 }781 }
771 782
@@ -825,7 +836,7 @@ static void intel_pstate_get_hwp_max(unsigned int cpu, int *phy_max, · 53 unmodified lines
825 836
826 rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap);837 rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap);
827 WRITE_ONCE(all_cpu_data[cpu]->hwp_cap_cached, cap);838 WRITE_ONCE(all_cpu_data[cpu]->hwp_cap_cached, cap);
828 if (global.no_turbo)839 if (global.no_turbo || global.turbo_disabled)
829 *current_max = HWP_GUARANTEED_PERF(cap);840 *current_max = HWP_GUARANTEED_PERF(cap);
830 else841 else
831 *current_max = HWP_HIGHEST_PERF(cap);842 *current_max = HWP_HIGHEST_PERF(cap);
@@ -859,12 +870,6 @@ static void intel_pstate_hwp_set(unsigned int cpu) · 27 unmodified lines
859 870
860 cpu_data->epp_policy = cpu_data->policy;871 cpu_data->epp_policy = cpu_data->policy;
861 872
862 if (cpu_data->epp_saved >= 0) {
863 epp = cpu_data->epp_saved;
864 cpu_data->epp_saved = -EINVAL;
865 goto update_epp;
866 }
867
868 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {873 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
869 epp = intel_pstate_get_epp(cpu_data, value);874 epp = intel_pstate_get_epp(cpu_data, value);
870 cpu_data->epp_powersave = epp;875 cpu_data->epp_powersave = epp;
@@ -891,7 +896,6 @@ static void intel_pstate_hwp_set(unsigned int cpu) · 20 unmodified lines
891 896
892 epp = cpu_data->epp_powersave;897 epp = cpu_data->epp_powersave;
893 }898 }
894update_epp:
895 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {899 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
896 value &= ~GENMASK_ULL(31, 24);900 value &= ~GENMASK_ULL(31, 24);
897 value |= (u64)epp << 24;901 value |= (u64)epp << 24;
@@ -903,14 +907,24 @@ skip_epp: · 5 unmodified lines
903 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);907 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
904}908}
905 909
906static void intel_pstate_hwp_force_min_perf(int cpu)910static void intel_pstate_hwp_offline(struct cpudata *cpu)
907{911{
908 u64 value;912 u64 value = READ_ONCE(cpu->hwp_req_cached);
909 int min_perf;913 int min_perf;
910 914
911 value = all_cpu_data[cpu]->hwp_req_cached;915 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
916 /*
917 * In case the EPP has been set to "performance" by the
918 * active mode "performance" scaling algorithm, replace that
919 * temporary value with the cached EPP one.
920 */
921 value &= ~GENMASK_ULL(31, 24);
922 value |= HWP_ENERGY_PERF_PREFERENCE(cpu->epp_cached);
923 WRITE_ONCE(cpu->hwp_req_cached, value);
924 }
925
912 value &= ~GENMASK_ULL(31, 0);926 value &= ~GENMASK_ULL(31, 0);
913 min_perf = HWP_LOWEST_PERF(all_cpu_data[cpu]->hwp_cap_cached);927 min_perf = HWP_LOWEST_PERF(cpu->hwp_cap_cached);
914 928
915 /* Set hwp_max = hwp_min */929 /* Set hwp_max = hwp_min */
916 value |= HWP_MAX_PERF(min_perf);930 value |= HWP_MAX_PERF(min_perf);
@@ -920,19 +934,7 @@ static void intel_pstate_hwp_force_min_perf(int cpu) · 3 unmodified lines
920 if (boot_cpu_has(X86_FEATURE_HWP_EPP))934 if (boot_cpu_has(X86_FEATURE_HWP_EPP))
921 value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE);935 value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE);
922 936
923 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);937 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
924}
925
926static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy)
927{
928 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
929
930 if (!hwp_active)
931 return 0;
932
933 cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0);
934
935 return 0;
936}938}
937 939
938#define POWER_CTL_EE_ENABLE 1940#define POWER_CTL_EE_ENABLE 1
@@ -959,8 +961,28 @@ static void set_power_ctl_ee_state(bool input) · 20 unmodified lines
959 961
960static void intel_pstate_hwp_enable(struct cpudata *cpudata);962static void intel_pstate_hwp_enable(struct cpudata *cpudata);
961 963
964static void intel_pstate_hwp_reenable(struct cpudata *cpu)
965{
966 intel_pstate_hwp_enable(cpu);
967 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, READ_ONCE(cpu->hwp_req_cached));
968}
969
970static int intel_pstate_suspend(struct cpufreq_policy *policy)
971{
972 struct cpudata *cpu = all_cpu_data[policy->cpu];
973
974 pr_debug("CPU %d suspending\n", cpu->cpu);
975
976 cpu->suspended = true;
977
978 return 0;
979}
980
962static int intel_pstate_resume(struct cpufreq_policy *policy)981static int intel_pstate_resume(struct cpufreq_policy *policy)
963{982{
983 struct cpudata *cpu = all_cpu_data[policy->cpu];
984
985 pr_debug("CPU %d resuming\n", cpu->cpu);
964 986
965 /* Only restore if the system default is changed */987 /* Only restore if the system default is changed */
966 if (power_ctl_ee_state == POWER_CTL_EE_ENABLE)988 if (power_ctl_ee_state == POWER_CTL_EE_ENABLE)
@@ -968,18 +990,16 @@ static int intel_pstate_resume(struct cpufreq_policy *policy) · 1 unmodified line
968 else if (power_ctl_ee_state == POWER_CTL_EE_DISABLE)990 else if (power_ctl_ee_state == POWER_CTL_EE_DISABLE)
969 set_power_ctl_ee_state(false);991 set_power_ctl_ee_state(false);
970 992
971 if (!hwp_active)993 if (cpu->suspended && hwp_active) {
972 return 0;994 mutex_lock(&intel_pstate_limits_lock);
973 995
974 mutex_lock(&intel_pstate_limits_lock);996 /* Re-enable HWP, because "online" has not done that. */
997 intel_pstate_hwp_reenable(cpu);
975 998
976 if (policy->cpu == 0)999 mutex_unlock(&intel_pstate_limits_lock);
977 intel_pstate_hwp_enable(all_cpu_data[policy->cpu]);1000 }
978 1001
979 all_cpu_data[policy->cpu]->epp_policy = 0;1002 cpu->suspended = false;
980 intel_pstate_hwp_set(policy->cpu);
981
982 mutex_unlock(&intel_pstate_limits_lock);
983 1003
984 return 0;1004 return 0;
985}1005}
@@ -1428,7 +1448,6 @@ static void intel_pstate_hwp_enable(struct cpudata *cpudata) · 442 unmodified lines
1428 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);1448 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1429 1449
1430 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);1450 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1431 cpudata->epp_policy = 0;
1432 if (cpudata->epp_default == -EINVAL)1451 if (cpudata->epp_default == -EINVAL)
1433 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);1452 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1434}1453}
@@ -2097,25 +2116,31 @@ static int intel_pstate_init_cpu(unsigned int cpunum) · 662 unmodified lines
2097 2116
2098 all_cpu_data[cpunum] = cpu;2117 all_cpu_data[cpunum] = cpu;
2099 2118
2100 cpu->epp_default = -EINVAL;2119 cpu->cpu = cpunum;
2101 cpu->epp_powersave = -EINVAL;
2102 cpu->epp_saved = -EINVAL;
2103 }
2104
2105 cpu = all_cpu_data[cpunum];
2106 2120
2107 cpu->cpu = cpunum;2121 cpu->epp_default = -EINVAL;
2108 2122
2109 if (hwp_active) {2123 if (hwp_active) {
2110 const struct x86_cpu_id *id;2124 const struct x86_cpu_id *id;
2111 2125
2112 intel_pstate_hwp_enable(cpu);2126 intel_pstate_hwp_enable(cpu);
2113 2127
2114 id = x86_match_cpu(intel_pstate_hwp_boost_ids);2128 id = x86_match_cpu(intel_pstate_hwp_boost_ids);
2115 if (id && intel_pstate_acpi_pm_profile_server())2129 if (id && intel_pstate_acpi_pm_profile_server())
2116 hwp_boost = true;2130 hwp_boost = true;
2131 }
2132 } else if (hwp_active) {
2133 /*
2134 * Re-enable HWP in case this happens after a resume from ACPI
2135 * S3 if the CPU was offline during the whole system/resume
2136 * cycle.
2137 */
2138 intel_pstate_hwp_reenable(cpu);
2117 }2139 }
2118 2140
2141 cpu->epp_powersave = -EINVAL;
2142 cpu->epp_policy = 0;
2143
2119 intel_pstate_get_cpu_pstates(cpu);2144 intel_pstate_get_cpu_pstates(cpu);
2120 2145
2121 pr_debug("controlling: cpu %d\n", cpunum);2146 pr_debug("controlling: cpu %d\n", cpunum);
@@ -2296,28 +2321,61 @@ static int intel_pstate_verify_policy(struct cpufreq_policy_data *policy) · 174 unmodified lines
2296 return 0;2321 return 0;
2297}2322}
2298 2323
2299static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy)2324static int intel_pstate_cpu_offline(struct cpufreq_policy *policy)
2300{2325{
2326 struct cpudata *cpu = all_cpu_data[policy->cpu];
2327
2328 pr_debug("CPU %d going offline\n", cpu->cpu);
2329
2330 if (cpu->suspended)
2331 return 0;
2332
2333 /*
2334 * If the CPU is an SMT thread and it goes offline with the performance
2335 * settings different from the minimum, it will prevent its sibling
2336 * from getting to lower performance levels, so force the minimum
2337 * performance on CPU offline to prevent that from happening.
2338 */
2301 if (hwp_active)2339 if (hwp_active)
2302 intel_pstate_hwp_force_min_perf(policy->cpu);2340 intel_pstate_hwp_offline(cpu);
2303 else2341 else
2304 intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]);2342 intel_pstate_set_min_pstate(cpu);
2343
2344 intel_pstate_exit_perf_limits(policy);
2345
2346 return 0;
2347}
2348
2349static int intel_pstate_cpu_online(struct cpufreq_policy *policy)
2350{
2351 struct cpudata *cpu = all_cpu_data[policy->cpu];
2352
2353 pr_debug("CPU %d going online\n", cpu->cpu);
2354
2355 intel_pstate_init_acpi_perf_limits(policy);
2356
2357 if (hwp_active) {
2358 /*
2359 * Re-enable HWP and clear the "suspended" flag to let "resume"
2360 * know that it need not do that.
2361 */
2362 intel_pstate_hwp_reenable(cpu);
2363 cpu->suspended = false;
2364 }
2365
2366 return 0;
2305}2367}
2306 2368
2307static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)2369static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
2308{2370{
2309 pr_debug("CPU %d exiting\n", policy->cpu);2371 pr_debug("CPU %d stopping\n", policy->cpu);
2310 2372
2311 intel_pstate_clear_update_util_hook(policy->cpu);2373 intel_pstate_clear_update_util_hook(policy->cpu);
2312 if (hwp_active)
2313 intel_pstate_hwp_save_state(policy);
2314
2315 intel_cpufreq_stop_cpu(policy);
2316}2374}
2317 2375
2318static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)2376static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2319{2377{
2320 intel_pstate_exit_perf_limits(policy);2378 pr_debug("CPU %d exiting\n", policy->cpu);
2321 2379
2322 policy->fast_switch_possible = false;2380 policy->fast_switch_possible = false;
2323 2381
@@ -2378,6 +2436,12 @@ static int intel_pstate_cpu_init(struct cpufreq_policy *policy) · 54 unmodified lines
2378 */2436 */
2379 policy->policy = CPUFREQ_POLICY_POWERSAVE;2437 policy->policy = CPUFREQ_POLICY_POWERSAVE;
2380 2438
2439 if (hwp_active) {
2440 struct cpudata *cpu = all_cpu_data[policy->cpu];
2441
2442 cpu->epp_cached = intel_pstate_get_epp(cpu, 0);
2443 }
2444
2381 return 0;2445 return 0;
2382}2446}
2383 2447
@@ -2385,11 +2449,13 @@ static struct cpufreq_driver intel_pstate = { · 1 unmodified line
2385 .flags = CPUFREQ_CONST_LOOPS,2449 .flags = CPUFREQ_CONST_LOOPS,
2386 .verify = intel_pstate_verify_policy,2450 .verify = intel_pstate_verify_policy,
2387 .setpolicy = intel_pstate_set_policy,2451 .setpolicy = intel_pstate_set_policy,
2388 .suspend = intel_pstate_hwp_save_state,2452 .suspend = intel_pstate_suspend,
2389 .resume = intel_pstate_resume,2453 .resume = intel_pstate_resume,
2390 .init = intel_pstate_cpu_init,2454 .init = intel_pstate_cpu_init,
2391 .exit = intel_pstate_cpu_exit,2455 .exit = intel_pstate_cpu_exit,
2392 .stop_cpu = intel_pstate_stop_cpu,2456 .stop_cpu = intel_pstate_stop_cpu,
2457 .offline = intel_pstate_cpu_offline,
2458 .online = intel_pstate_cpu_online,
2393 .update_limits = intel_pstate_update_limits,2459 .update_limits = intel_pstate_update_limits,
2394 .name = "intel_pstate",2460 .name = "intel_pstate",
2395};2461};
@@ -2585,7 +2651,7 @@ static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy) · 189 unmodified lines
2585 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY_HWP;2651 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY_HWP;
2586 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, &value);2652 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, &value);
2587 WRITE_ONCE(cpu->hwp_req_cached, value);2653 WRITE_ONCE(cpu->hwp_req_cached, value);
2588 cpu->epp_cached = (value & GENMASK_ULL(31, 24)) >> 24;2654 cpu->epp_cached = intel_pstate_get_epp(cpu, value);
2589 } else {2655 } else {
2590 turbo_max = cpu->pstate.turbo_pstate;2656 turbo_max = cpu->pstate.turbo_pstate;
2591 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY;2657 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY;
@@ -2644,7 +2710,10 @@ static struct cpufreq_driver intel_cpufreq = { · 52 unmodified lines
2644 .fast_switch = intel_cpufreq_fast_switch,2710 .fast_switch = intel_cpufreq_fast_switch,
2645 .init = intel_cpufreq_cpu_init,2711 .init = intel_cpufreq_cpu_init,
2646 .exit = intel_cpufreq_cpu_exit,2712 .exit = intel_cpufreq_cpu_exit,
2647 .stop_cpu = intel_cpufreq_stop_cpu,2713 .offline = intel_pstate_cpu_offline,
2714 .online = intel_pstate_cpu_online,
2715 .suspend = intel_pstate_suspend,
2716 .resume = intel_pstate_resume,
2648 .update_limits = intel_pstate_update_limits,2717 .update_limits = intel_pstate_update_limits,
2649 .name = "intel_cpufreq",2718 .name = "intel_cpufreq",
2650};2719};
@@ -2667,9 +2736,6 @@ static void intel_pstate_driver_cleanup(void) · 16 unmodified lines
2667 }2736 }
2668 put_online_cpus();2737 put_online_cpus();
2669 2738
2670 if (intel_pstate_driver == &intel_pstate)
2671 intel_pstate_sysfs_hide_hwp_dynamic_boost();
2672
2673 intel_pstate_driver = NULL;2739 intel_pstate_driver = NULL;
2674}2740}
2675 2741
@@ -2695,14 +2761,6 @@ static int intel_pstate_register_driver(struct cpufreq_driver *driver) · 19 unmodified lines
2695 return 0;2761 return 0;
2696}2762}
2697 2763
2698static int intel_pstate_unregister_driver(void)
2699{
2700 cpufreq_unregister_driver(intel_pstate_driver);
2701 intel_pstate_driver_cleanup();
2702
2703 return 0;
2704}
2705
2706static ssize_t intel_pstate_show_status(char *buf)2764static ssize_t intel_pstate_show_status(char *buf)
2707{2765{
2708 if (!intel_pstate_driver)2766 if (!intel_pstate_driver)
@@ -2714,20 +2772,23 @@ static ssize_t intel_pstate_show_status(char *buf) · 5 unmodified lines
2714 2772
2715static int intel_pstate_update_status(const char *buf, size_t size)2773static int intel_pstate_update_status(const char *buf, size_t size)
2716{2774{
2717 int ret;2775 if (size == 3 && !strncmp(buf, "off", size)) {
2776 if (!intel_pstate_driver)
2777 return -EINVAL;
2778
2779 if (hwp_active)
2780 return -EBUSY;
2718 2781
2719 if (size == 3 && !strncmp(buf, "off", size))2782 cpufreq_unregister_driver(intel_pstate_driver);
2720 return intel_pstate_driver ?2783 intel_pstate_driver_cleanup();
2721 intel_pstate_unregister_driver() : -EINVAL;2784 }
2722 2785
2723 if (size == 6 && !strncmp(buf, "active", size)) {2786 if (size == 6 && !strncmp(buf, "active", size)) {
2724 if (intel_pstate_driver) {2787 if (intel_pstate_driver) {
2725 if (intel_pstate_driver == &intel_pstate)2788 if (intel_pstate_driver == &intel_pstate)
2726 return 0;2789 return 0;
2727 2790
2728 ret = intel_pstate_unregister_driver();2791 cpufreq_unregister_driver(intel_pstate_driver);
2729 if (ret)
2730 return ret;
2731 }2792 }
2732 2793
2733 return intel_pstate_register_driver(&intel_pstate);2794 return intel_pstate_register_driver(&intel_pstate);
@@ -2738,9 +2799,8 @@ static int intel_pstate_update_status(const char *buf, size_t size) · 4 unmodified lines
2738 if (intel_pstate_driver == &intel_cpufreq)2799 if (intel_pstate_driver == &intel_cpufreq)
2739 return 0;2800 return 0;
2740 2801
2741 ret = intel_pstate_unregister_driver();2802 cpufreq_unregister_driver(intel_pstate_driver);
2742 if (ret)2803 intel_pstate_sysfs_hide_hwp_dynamic_boost();
2743 return ret;
2744 }2804 }
2745 2805
2746 return intel_pstate_register_driver(&intel_cpufreq);2806 return intel_pstate_register_driver(&intel_cpufreq);
drivers/cpufreq/p4-clockmod.c+1−1
@@ -129,7 +129,7 @@ static unsigned int cpufreq_p4_get_frequency(struct cpuinfo_x86 *c) · 128 unmodified lines
129 return speedstep_get_frequency(SPEEDSTEP_CPU_PCORE);129 return speedstep_get_frequency(SPEEDSTEP_CPU_PCORE);
130 case 0x0D: /* Pentium M (Dothan) */130 case 0x0D: /* Pentium M (Dothan) */
131 p4clockmod_driver.flags |= CPUFREQ_CONST_LOOPS;131 p4clockmod_driver.flags |= CPUFREQ_CONST_LOOPS;
132 /* fall through */132 fallthrough;
133 case 0x09: /* Pentium M (Banias) */133 case 0x09: /* Pentium M (Banias) */
134 return speedstep_get_frequency(SPEEDSTEP_CPU_PM);134 return speedstep_get_frequency(SPEEDSTEP_CPU_PM);
135 }135 }
drivers/cpufreq/speedstep-lib.c+1−1
@@ -366,7 +366,7 @@ enum speedstep_processor speedstep_detect_processor(void) · 365 unmodified lines
366 } else366 } else
367 return SPEEDSTEP_CPU_PIII_C;367 return SPEEDSTEP_CPU_PIII_C;
368 }368 }
369 /* fall through */369 fallthrough;
370 default:370 default:
371 return 0;371 return 0;
372 }372 }
drivers/cpufreq/tegra194-cpufreq.c+7−3
@@ -56,9 +56,11 @@ struct read_counters_work { · 55 unmodified lines
56 56
57static struct workqueue_struct *read_counters_wq;57static struct workqueue_struct *read_counters_wq;
58 58
59static enum cluster get_cpu_cluster(u8 cpu)59static void get_cpu_cluster(void *cluster)
60{60{
61 return MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 1);61 u64 mpidr = read_cpuid_mpidr() & MPIDR_HWID_BITMASK;
62
63 *((uint32_t *)cluster) = MPIDR_AFFINITY_LEVEL(mpidr, 1);
62}64}
63 65
64/*66/*
@@ -186,8 +188,10 @@ static unsigned int tegra194_get_speed(u32 cpu) · 121 unmodified lines
186static int tegra194_cpufreq_init(struct cpufreq_policy *policy)188static int tegra194_cpufreq_init(struct cpufreq_policy *policy)
187{189{
188 struct tegra194_cpufreq_data *data = cpufreq_get_driver_data();190 struct tegra194_cpufreq_data *data = cpufreq_get_driver_data();
189 int cl = get_cpu_cluster(policy->cpu);
190 u32 cpu;191 u32 cpu;
192 u32 cl;
193
194 smp_call_function_single(policy->cpu, get_cpu_cluster, &cl, true);
191 195
192 if (cl >= data->num_clusters)196 if (cl >= data->num_clusters)
193 return -EINVAL;197 return -EINVAL;
drivers/cpufreq/ti-cpufreq.c+2−2
@@ -86,11 +86,11 @@ static unsigned long dra7_efuse_xlate(struct ti_cpufreq_data *opp_data, · 85 unmodified lines
86 case DRA76_EFUSE_HAS_PLUS_MPU_OPP:86 case DRA76_EFUSE_HAS_PLUS_MPU_OPP:
87 case DRA76_EFUSE_HAS_ALL_MPU_OPP:87 case DRA76_EFUSE_HAS_ALL_MPU_OPP:
88 calculated_efuse |= DRA76_EFUSE_PLUS_MPU_OPP;88 calculated_efuse |= DRA76_EFUSE_PLUS_MPU_OPP;
89 /* Fall through */89 fallthrough;
90 case DRA7_EFUSE_HAS_ALL_MPU_OPP:90 case DRA7_EFUSE_HAS_ALL_MPU_OPP:
91 case DRA7_EFUSE_HAS_HIGH_MPU_OPP:91 case DRA7_EFUSE_HAS_HIGH_MPU_OPP:
92 calculated_efuse |= DRA7_EFUSE_HIGH_MPU_OPP;92 calculated_efuse |= DRA7_EFUSE_HIGH_MPU_OPP;
93 /* Fall through */93 fallthrough;
94 case DRA7_EFUSE_HAS_OD_MPU_OPP:94 case DRA7_EFUSE_HAS_OD_MPU_OPP:
95 calculated_efuse |= DRA7_EFUSE_OD_MPU_OPP;95 calculated_efuse |= DRA7_EFUSE_OD_MPU_OPP;
96 }96 }
drivers/cpuidle/cpuidle.c+14−5
@@ -22,6 +22,7 @@ · 21 unmodified lines
22#include <linux/module.h>22#include <linux/module.h>
23#include <linux/suspend.h>23#include <linux/suspend.h>
24#include <linux/tick.h>24#include <linux/tick.h>
25#include <linux/mmu_context.h>
25#include <trace/events/power.h>26#include <trace/events/power.h>
26 27
27#include "cpuidle.h"28#include "cpuidle.h"
@@ -145,21 +146,24 @@ static void enter_s2idle_proper(struct cpuidle_driver *drv, · 117 unmodified lines
145 * executing it contains RCU usage regarded as invalid in the idle146 * executing it contains RCU usage regarded as invalid in the idle
146 * context, so tell RCU about that.147 * context, so tell RCU about that.
147 */148 */
148 RCU_NONIDLE(tick_freeze());149 tick_freeze();
149 /*150 /*
150 * The state used here cannot be a "coupled" one, because the "coupled"151 * The state used here cannot be a "coupled" one, because the "coupled"
151 * cpuidle mechanism enables interrupts and doing that with timekeeping152 * cpuidle mechanism enables interrupts and doing that with timekeeping
152 * suspended is generally unsafe.153 * suspended is generally unsafe.
153 */154 */
154 stop_critical_timings();155 stop_critical_timings();
156 rcu_idle_enter();
155 drv->states[index].enter_s2idle(dev, drv, index);157 drv->states[index].enter_s2idle(dev, drv, index);
156 WARN_ON(!irqs_disabled());158 if (WARN_ON_ONCE(!irqs_disabled()))
159 local_irq_disable();
157 /*160 /*
158 * timekeeping_resume() that will be called by tick_unfreeze() for the161 * timekeeping_resume() that will be called by tick_unfreeze() for the
159 * first CPU executing it calls functions containing RCU read-side162 * first CPU executing it calls functions containing RCU read-side
160 * critical sections, so tell RCU about that.163 * critical sections, so tell RCU about that.
161 */164 */
162 RCU_NONIDLE(tick_unfreeze());165 rcu_idle_exit();
166 tick_unfreeze();
163 start_critical_timings();167 start_critical_timings();
164 168
165 time_end = ns_to_ktime(local_clock());169 time_end = ns_to_ktime(local_clock());
@@ -225,19 +229,24 @@ int cpuidle_enter_state(struct cpuidle_device *dev, struct cpuidle_driver *drv, · 59 unmodified lines
225 broadcast = false;229 broadcast = false;
226 }230 }
227 231
232 if (target_state->flags & CPUIDLE_FLAG_TLB_FLUSHED)
233 leave_mm(dev->cpu);
234
228 /* Take note of the planned idle state. */235 /* Take note of the planned idle state. */
229 sched_idle_set_state(target_state);236 sched_idle_set_state(target_state);
230 237
231 trace_cpu_idle_rcuidle(index, dev->cpu);238 trace_cpu_idle(index, dev->cpu);
232 time_start = ns_to_ktime(local_clock());239 time_start = ns_to_ktime(local_clock());
233 240
234 stop_critical_timings();241 stop_critical_timings();
242 rcu_idle_enter();
235 entered_state = target_state->enter(dev, drv, index);243 entered_state = target_state->enter(dev, drv, index);
244 rcu_idle_exit();
236 start_critical_timings();245 start_critical_timings();
237 246
238 sched_clock_idle_wakeup_event();247 sched_clock_idle_wakeup_event();
239 time_end = ns_to_ktime(local_clock());248 time_end = ns_to_ktime(local_clock());
240 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, dev->cpu);249 trace_cpu_idle(PWR_EVENT_EXIT, dev->cpu);
241 250
242 /* The cpu is no longer idle or about to enter idle. */251 /* The cpu is no longer idle or about to enter idle. */
243 sched_idle_set_state(NULL);252 sched_idle_set_state(NULL);
drivers/crypto/Kconfig+3−0
@@ -873,6 +873,9 @@ config CRYPTO_DEV_SA2UL · 872 unmodified lines
873 select CRYPTO_AES873 select CRYPTO_AES
874 select CRYPTO_AES_ARM64874 select CRYPTO_AES_ARM64
875 select CRYPTO_ALGAPI875 select CRYPTO_ALGAPI
876 select CRYPTO_SHA1
877 select CRYPTO_SHA256
878 select CRYPTO_SHA512
876 select HW_RANDOM879 select HW_RANDOM
877 select SG_SPLIT880 select SG_SPLIT
878 help881 help
drivers/crypto/axis/artpec6_crypto.c+1−1
@@ -2310,7 +2310,7 @@ static int artpec6_crypto_prepare_submit_hash(struct ahash_request *req) · 2309 unmodified lines
2310 2310
2311 case ARTPEC6_CRYPTO_PREPARE_HASH_NO_START:2311 case ARTPEC6_CRYPTO_PREPARE_HASH_NO_START:
2312 ret = 0;2312 ret = 0;
2313 /* Fallthrough */2313 fallthrough;
2314 2314
2315 default:2315 default:
2316 artpec6_crypto_common_destroy(&req_ctx->common);2316 artpec6_crypto_common_destroy(&req_ctx->common);
drivers/crypto/cavium/cpt/cptvf_reqmanager.c+2−2
@@ -90,11 +90,11 @@ static int setup_sgio_components(struct cpt_vf *cptvf, struct buf_ptr *list, · 89 unmodified lines
90 case 3:90 case 3:
91 sg_ptr->u.s.len2 = cpu_to_be16(list[i * 4 + 2].size);91 sg_ptr->u.s.len2 = cpu_to_be16(list[i * 4 + 2].size);
92 sg_ptr->ptr2 = cpu_to_be64(list[i * 4 + 2].dma_addr);92 sg_ptr->ptr2 = cpu_to_be64(list[i * 4 + 2].dma_addr);
93 /* Fall through */93 fallthrough;
94 case 2:94 case 2:
95 sg_ptr->u.s.len1 = cpu_to_be16(list[i * 4 + 1].size);95 sg_ptr->u.s.len1 = cpu_to_be16(list[i * 4 + 1].size);
96 sg_ptr->ptr1 = cpu_to_be64(list[i * 4 + 1].dma_addr);96 sg_ptr->ptr1 = cpu_to_be64(list[i * 4 + 1].dma_addr);
97 /* Fall through */97 fallthrough;
98 case 1:98 case 1:
99 sg_ptr->u.s.len0 = cpu_to_be16(list[i * 4 + 0].size);99 sg_ptr->u.s.len0 = cpu_to_be16(list[i * 4 + 0].size);
100 sg_ptr->ptr0 = cpu_to_be64(list[i * 4 + 0].dma_addr);100 sg_ptr->ptr0 = cpu_to_be64(list[i * 4 + 0].dma_addr);
drivers/crypto/chelsio/chcr_ktls.c+2−2
@@ -135,7 +135,7 @@ static int chcr_ktls_update_connection_state(struct chcr_ktls_info *tx_info, · 134 unmodified lines
135 break;135 break;
136 /* update to the next state and also initialize TCB */136 /* update to the next state and also initialize TCB */
137 tx_info->connection_state = new_state;137 tx_info->connection_state = new_state;
138 /* FALLTHRU */138 fallthrough;
139 case KTLS_CONN_ACT_OPEN_RPL:139 case KTLS_CONN_ACT_OPEN_RPL:
140 /* if we are stuck in this state, means tcb init might not140 /* if we are stuck in this state, means tcb init might not
141 * received by HW, try sending it again.141 * received by HW, try sending it again.
@@ -150,7 +150,7 @@ static int chcr_ktls_update_connection_state(struct chcr_ktls_info *tx_info, · 8 unmodified lines
150 break;150 break;
151 /* update to the next state and check if l2t_state is valid */151 /* update to the next state and check if l2t_state is valid */
152 tx_info->connection_state = new_state;152 tx_info->connection_state = new_state;
153 /* FALLTHRU */153 fallthrough;
154 case KTLS_CONN_SET_TCB_RPL:154 case KTLS_CONN_SET_TCB_RPL:
155 /* Check if l2t state is valid, then move to ready state. */155 /* Check if l2t state is valid, then move to ready state. */
156 if (cxgb4_check_l2t_valid(tx_info->l2te)) {156 if (cxgb4_check_l2t_valid(tx_info->l2te)) {
drivers/crypto/marvell/octeontx/otx_cptvf_reqmgr.c+2−2
@@ -140,11 +140,11 @@ static inline int setup_sgio_components(struct pci_dev *pdev, · 139 unmodified lines
140 case 3:140 case 3:
141 sg_ptr->u.s.len2 = cpu_to_be16(list[i * 4 + 2].size);141 sg_ptr->u.s.len2 = cpu_to_be16(list[i * 4 + 2].size);
142 sg_ptr->ptr2 = cpu_to_be64(list[i * 4 + 2].dma_addr);142 sg_ptr->ptr2 = cpu_to_be64(list[i * 4 + 2].dma_addr);
143 /* Fall through */143 fallthrough;
144 case 2:144 case 2:
145 sg_ptr->u.s.len1 = cpu_to_be16(list[i * 4 + 1].size);145 sg_ptr->u.s.len1 = cpu_to_be16(list[i * 4 + 1].size);
146 sg_ptr->ptr1 = cpu_to_be64(list[i * 4 + 1].dma_addr);146 sg_ptr->ptr1 = cpu_to_be64(list[i * 4 + 1].dma_addr);
147 /* Fall through */147 fallthrough;
148 case 1:148 case 1:
149 sg_ptr->u.s.len0 = cpu_to_be16(list[i * 4 + 0].size);149 sg_ptr->u.s.len0 = cpu_to_be16(list[i * 4 + 0].size);
150 sg_ptr->ptr0 = cpu_to_be64(list[i * 4 + 0].dma_addr);150 sg_ptr->ptr0 = cpu_to_be64(list[i * 4 + 0].dma_addr);
drivers/crypto/qat/qat_common/adf_admin.c+4−3
@@ -131,9 +131,10 @@ static int adf_put_admin_msg_sync(struct adf_accel_dev *accel_dev, u32 ae, · 130 unmodified lines
131 memcpy(admin->virt_addr + offset, in, ADF_ADMINMSG_LEN);131 memcpy(admin->virt_addr + offset, in, ADF_ADMINMSG_LEN);
132 ADF_CSR_WR(mailbox, mb_offset, 1);132 ADF_CSR_WR(mailbox, mb_offset, 1);
133 133
134 ret = readl_poll_timeout(mailbox + mb_offset, status,134 ret = read_poll_timeout(ADF_CSR_RD, status, status == 0,
135 status == 0, ADF_ADMIN_POLL_DELAY_US,135 ADF_ADMIN_POLL_DELAY_US,
136 ADF_ADMIN_POLL_TIMEOUT_US);136 ADF_ADMIN_POLL_TIMEOUT_US, true,
137 mailbox, mb_offset);
137 if (ret < 0) {138 if (ret < 0) {
138 /* Response timeout */139 /* Response timeout */
139 dev_err(&GET_DEV(accel_dev),140 dev_err(&GET_DEV(accel_dev),
drivers/crypto/qat/qat_common/adf_pf2vf_msg.c+1−1
@@ -340,7 +340,7 @@ static int adf_vf2pf_request_version(struct adf_accel_dev *accel_dev) · 339 unmodified lines
340 /* VF is newer than PF and decides whether it is compatible */340 /* VF is newer than PF and decides whether it is compatible */
341 if (accel_dev->vf.pf_version >= hw_data->min_iov_compat_ver)341 if (accel_dev->vf.pf_version >= hw_data->min_iov_compat_ver)
342 break;342 break;
343 /* fall through */343 fallthrough;
344 case ADF_PF2VF_VF_INCOMPATIBLE:344 case ADF_PF2VF_VF_INCOMPATIBLE:
345 dev_err(&GET_DEV(accel_dev),345 dev_err(&GET_DEV(accel_dev),
346 "PF (vers %d) and VF (vers %d) are not compatible\n",346 "PF (vers %d) and VF (vers %d) are not compatible\n",
drivers/crypto/qat/qat_common/qat_uclo.c+3−3
@@ -752,7 +752,7 @@ static int qat_uclo_init_reg(struct icp_qat_fw_loader_handle *handle, · 751 unmodified lines
752 case ICP_GPA_ABS:752 case ICP_GPA_ABS:
753 case ICP_GPB_ABS:753 case ICP_GPB_ABS:
754 ctx_mask = 0;754 ctx_mask = 0;
755 /* fall through */755 fallthrough;
756 case ICP_GPA_REL:756 case ICP_GPA_REL:
757 case ICP_GPB_REL:757 case ICP_GPB_REL:
758 return qat_hal_init_gpr(handle, ae, ctx_mask, reg_type,758 return qat_hal_init_gpr(handle, ae, ctx_mask, reg_type,
@@ -762,7 +762,7 @@ static int qat_uclo_init_reg(struct icp_qat_fw_loader_handle *handle, · 3 unmodified lines
762 case ICP_SR_RD_ABS:762 case ICP_SR_RD_ABS:
763 case ICP_DR_RD_ABS:763 case ICP_DR_RD_ABS:
764 ctx_mask = 0;764 ctx_mask = 0;
765 /* fall through */765 fallthrough;
766 case ICP_SR_REL:766 case ICP_SR_REL:
767 case ICP_DR_REL:767 case ICP_DR_REL:
768 case ICP_SR_RD_REL:768 case ICP_SR_RD_REL:
@@ -772,7 +772,7 @@ static int qat_uclo_init_reg(struct icp_qat_fw_loader_handle *handle, · 3 unmodified lines
772 case ICP_SR_WR_ABS:772 case ICP_SR_WR_ABS:
773 case ICP_DR_WR_ABS:773 case ICP_DR_WR_ABS:
774 ctx_mask = 0;774 ctx_mask = 0;
775 /* fall through */775 fallthrough;
776 case ICP_SR_WR_REL:776 case ICP_SR_WR_REL:
777 case ICP_DR_WR_REL:777 case ICP_DR_WR_REL:
778 return qat_hal_init_wr_xfer(handle, ae, ctx_mask, reg_type,778 return qat_hal_init_wr_xfer(handle, ae, ctx_mask, reg_type,
drivers/crypto/ux500/cryp/cryp.c+6−6
@@ -314,17 +314,17 @@ void cryp_save_device_context(struct cryp_device_data *device_data, · 313 unmodified lines
314 case CRYP_KEY_SIZE_256:314 case CRYP_KEY_SIZE_256:
315 ctx->key_4_l = readl_relaxed(&src_reg->key_4_l);315 ctx->key_4_l = readl_relaxed(&src_reg->key_4_l);
316 ctx->key_4_r = readl_relaxed(&src_reg->key_4_r);316 ctx->key_4_r = readl_relaxed(&src_reg->key_4_r);
317 /* Fall through */317 fallthrough;
318 318
319 case CRYP_KEY_SIZE_192:319 case CRYP_KEY_SIZE_192:
320 ctx->key_3_l = readl_relaxed(&src_reg->key_3_l);320 ctx->key_3_l = readl_relaxed(&src_reg->key_3_l);
321 ctx->key_3_r = readl_relaxed(&src_reg->key_3_r);321 ctx->key_3_r = readl_relaxed(&src_reg->key_3_r);
322 /* Fall through */322 fallthrough;
323 323
324 case CRYP_KEY_SIZE_128:324 case CRYP_KEY_SIZE_128:
325 ctx->key_2_l = readl_relaxed(&src_reg->key_2_l);325 ctx->key_2_l = readl_relaxed(&src_reg->key_2_l);
326 ctx->key_2_r = readl_relaxed(&src_reg->key_2_r);326 ctx->key_2_r = readl_relaxed(&src_reg->key_2_r);
327 /* Fall through */327 fallthrough;
328 328
329 default:329 default:
330 ctx->key_1_l = readl_relaxed(&src_reg->key_1_l);330 ctx->key_1_l = readl_relaxed(&src_reg->key_1_l);
@@ -364,17 +364,17 @@ void cryp_restore_device_context(struct cryp_device_data *device_data, · 33 unmodified lines
364 case CRYP_KEY_SIZE_256:364 case CRYP_KEY_SIZE_256:
365 writel_relaxed(ctx->key_4_l, &reg->key_4_l);365 writel_relaxed(ctx->key_4_l, &reg->key_4_l);
366 writel_relaxed(ctx->key_4_r, &reg->key_4_r);366 writel_relaxed(ctx->key_4_r, &reg->key_4_r);
367 /* Fall through */367 fallthrough;
368 368
369 case CRYP_KEY_SIZE_192:369 case CRYP_KEY_SIZE_192:
370 writel_relaxed(ctx->key_3_l, &reg->key_3_l);370 writel_relaxed(ctx->key_3_l, &reg->key_3_l);
371 writel_relaxed(ctx->key_3_r, &reg->key_3_r);371 writel_relaxed(ctx->key_3_r, &reg->key_3_r);
372 /* Fall through */372 fallthrough;
373 373
374 case CRYP_KEY_SIZE_128:374 case CRYP_KEY_SIZE_128:
375 writel_relaxed(ctx->key_2_l, &reg->key_2_l);375 writel_relaxed(ctx->key_2_l, &reg->key_2_l);
376 writel_relaxed(ctx->key_2_r, &reg->key_2_r);376 writel_relaxed(ctx->key_2_r, &reg->key_2_r);
377 /* Fall through */377 fallthrough;
378 378
379 default:379 default:
380 writel_relaxed(ctx->key_1_l, &reg->key_1_l);380 writel_relaxed(ctx->key_1_l, &reg->key_1_l);
drivers/dax/device.c+1−1
@@ -429,7 +429,7 @@ int dev_dax_probe(struct device *dev) · 428 unmodified lines
429 return -EBUSY;429 return -EBUSY;
430 }430 }
431 431
432 dev_dax->pgmap.type = MEMORY_DEVICE_DEVDAX;432 dev_dax->pgmap.type = MEMORY_DEVICE_GENERIC;
433 addr = devm_memremap_pages(dev, &dev_dax->pgmap);433 addr = devm_memremap_pages(dev, &dev_dax->pgmap);
434 if (IS_ERR(addr))434 if (IS_ERR(addr))
435 return PTR_ERR(addr);435 return PTR_ERR(addr);
drivers/dax/super.c+6−0
@@ -100,6 +100,12 @@ bool __generic_fsdax_supported(struct dax_device *dax_dev, · 99 unmodified lines
100 return false;100 return false;
101 }101 }
102 102
103 if (!dax_dev && !bdev_dax_supported(bdev, blocksize)) {
104 pr_debug("%s: error: dax unsupported by block device\n",
105 bdevname(bdev, buf));
106 return false;
107 }
108
103 id = dax_read_lock();109 id = dax_read_lock();
104 len = dax_direct_access(dax_dev, pgoff, 1, &kaddr, &pfn);110 len = dax_direct_access(dax_dev, pgoff, 1, &kaddr, &pfn);
105 len2 = dax_direct_access(dax_dev, pgoff_end, 1, &end_kaddr, &end_pfn);111 len2 = dax_direct_access(dax_dev, pgoff_end, 1, &end_kaddr, &end_pfn);
drivers/dma/acpi-dma.c+3−1
@@ -135,11 +135,13 @@ static void acpi_dma_parse_csrt(struct acpi_device *adev, struct acpi_dma *adma) · 134 unmodified lines
135 if (ret < 0) {135 if (ret < 0) {
136 dev_warn(&adev->dev,136 dev_warn(&adev->dev,
137 "error in parsing resource group\n");137 "error in parsing resource group\n");
138 return;138 break;
139 }139 }
140 140
141 grp = (struct acpi_csrt_group *)((void *)grp + grp->length);141 grp = (struct acpi_csrt_group *)((void *)grp + grp->length);
142 }142 }
143
144 acpi_put_table((struct acpi_table_header *)csrt);
143}145}
144 146
145/**147/**
drivers/dma/amba-pl08x.c+5−5
@@ -1767,7 +1767,7 @@ static u32 pl08x_memcpy_cctl(struct pl08x_driver_data *pl08x) · 1766 unmodified lines
1767 default:1767 default:
1768 dev_err(&pl08x->adev->dev,1768 dev_err(&pl08x->adev->dev,
1769 "illegal burst size for memcpy, set to 1\n");1769 "illegal burst size for memcpy, set to 1\n");
1770 /* Fall through */1770 fallthrough;
1771 case PL08X_BURST_SZ_1:1771 case PL08X_BURST_SZ_1:
1772 cctl |= PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT |1772 cctl |= PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT |
1773 PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT;1773 PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT;
@@ -1806,7 +1806,7 @@ static u32 pl08x_memcpy_cctl(struct pl08x_driver_data *pl08x) · 32 unmodified lines
1806 default:1806 default:
1807 dev_err(&pl08x->adev->dev,1807 dev_err(&pl08x->adev->dev,
1808 "illegal bus width for memcpy, set to 8 bits\n");1808 "illegal bus width for memcpy, set to 8 bits\n");
1809 /* Fall through */1809 fallthrough;
1810 case PL08X_BUS_WIDTH_8_BITS:1810 case PL08X_BUS_WIDTH_8_BITS:
1811 cctl |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT |1811 cctl |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT |
1812 PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT;1812 PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT;
@@ -1850,7 +1850,7 @@ static u32 pl08x_ftdmac020_memcpy_cctl(struct pl08x_driver_data *pl08x) · 37 unmodified lines
1850 default:1850 default:
1851 dev_err(&pl08x->adev->dev,1851 dev_err(&pl08x->adev->dev,
1852 "illegal bus width for memcpy, set to 8 bits\n");1852 "illegal bus width for memcpy, set to 8 bits\n");
1853 /* Fall through */1853 fallthrough;
1854 case PL08X_BUS_WIDTH_8_BITS:1854 case PL08X_BUS_WIDTH_8_BITS:
1855 cctl |= PL080_WIDTH_8BIT << FTDMAC020_LLI_SRC_WIDTH_SHIFT |1855 cctl |= PL080_WIDTH_8BIT << FTDMAC020_LLI_SRC_WIDTH_SHIFT |
1856 PL080_WIDTH_8BIT << FTDMAC020_LLI_DST_WIDTH_SHIFT;1856 PL080_WIDTH_8BIT << FTDMAC020_LLI_DST_WIDTH_SHIFT;
@@ -2612,7 +2612,7 @@ static int pl08x_of_probe(struct amba_device *adev, · 755 unmodified lines
2612 switch (val) {2612 switch (val) {
2613 default:2613 default:
2614 dev_err(&adev->dev, "illegal burst size for memcpy, set to 1\n");2614 dev_err(&adev->dev, "illegal burst size for memcpy, set to 1\n");
2615 /* Fall through */2615 fallthrough;
2616 case 1:2616 case 1:
2617 pd->memcpy_burst_size = PL08X_BURST_SZ_1;2617 pd->memcpy_burst_size = PL08X_BURST_SZ_1;
2618 break;2618 break;
@@ -2647,7 +2647,7 @@ static int pl08x_of_probe(struct amba_device *adev, · 28 unmodified lines
2647 switch (val) {2647 switch (val) {
2648 default:2648 default:
2649 dev_err(&adev->dev, "illegal bus width for memcpy, set to 8 bits\n");2649 dev_err(&adev->dev, "illegal bus width for memcpy, set to 8 bits\n");
2650 /* Fall through */2650 fallthrough;
2651 case 8:2651 case 8:
2652 pd->memcpy_bus_width = PL08X_BUS_WIDTH_8_BITS;2652 pd->memcpy_bus_width = PL08X_BUS_WIDTH_8_BITS;
2653 break;2653 break;
drivers/dma/at_hdmac.c+9−2
@@ -1650,13 +1650,17 @@ static struct dma_chan *at_dma_xlate(struct of_phandle_args *dma_spec, · 1649 unmodified lines
1650 return NULL;1650 return NULL;
1651 1651
1652 dmac_pdev = of_find_device_by_node(dma_spec->np);1652 dmac_pdev = of_find_device_by_node(dma_spec->np);
1653 if (!dmac_pdev)
1654 return NULL;
1653 1655
1654 dma_cap_zero(mask);1656 dma_cap_zero(mask);
1655 dma_cap_set(DMA_SLAVE, mask);1657 dma_cap_set(DMA_SLAVE, mask);
1656 1658
1657 atslave = kmalloc(sizeof(*atslave), GFP_KERNEL);1659 atslave = kmalloc(sizeof(*atslave), GFP_KERNEL);
1658 if (!atslave)1660 if (!atslave) {
1661 put_device(&dmac_pdev->dev);
1659 return NULL;1662 return NULL;
1663 }
1660 1664
1661 atslave->cfg = ATC_DST_H2SEL_HW | ATC_SRC_H2SEL_HW;1665 atslave->cfg = ATC_DST_H2SEL_HW | ATC_SRC_H2SEL_HW;
1662 /*1666 /*
@@ -1685,8 +1689,11 @@ static struct dma_chan *at_dma_xlate(struct of_phandle_args *dma_spec, · 22 unmodified lines
1685 atslave->dma_dev = &dmac_pdev->dev;1689 atslave->dma_dev = &dmac_pdev->dev;
1686 1690
1687 chan = dma_request_channel(mask, at_dma_filter, atslave);1691 chan = dma_request_channel(mask, at_dma_filter, atslave);
1688 if (!chan)1692 if (!chan) {
1693 put_device(&dmac_pdev->dev);
1694 kfree(atslave);
1689 return NULL;1695 return NULL;
1696 }
1690 1697
1691 atchan = to_at_dma_chan(chan);1698 atchan = to_at_dma_chan(chan);
1692 atchan->per_if = dma_spec->args[0] & 0xff;1699 atchan->per_if = dma_spec->args[0] & 0xff;
drivers/dma/dma-jz4780.c+19−19
@@ -879,24 +879,11 @@ static int jz4780_dma_probe(struct platform_device *pdev) · 878 unmodified lines
879 return -EINVAL;879 return -EINVAL;
880 }880 }
881 881
882 ret = platform_get_irq(pdev, 0);
883 if (ret < 0)
884 return ret;
885
886 jzdma->irq = ret;
887
888 ret = request_irq(jzdma->irq, jz4780_dma_irq_handler, 0, dev_name(dev),
889 jzdma);
890 if (ret) {
891 dev_err(dev, "failed to request IRQ %u!\n", jzdma->irq);
892 return ret;
893 }
894
895 jzdma->clk = devm_clk_get(dev, NULL);882 jzdma->clk = devm_clk_get(dev, NULL);
896 if (IS_ERR(jzdma->clk)) {883 if (IS_ERR(jzdma->clk)) {
897 dev_err(dev, "failed to get clock\n");884 dev_err(dev, "failed to get clock\n");
898 ret = PTR_ERR(jzdma->clk);885 ret = PTR_ERR(jzdma->clk);
899 goto err_free_irq;886 return ret;
900 }887 }
901 888
902 clk_prepare_enable(jzdma->clk);889 clk_prepare_enable(jzdma->clk);
@@ -949,10 +936,23 @@ static int jz4780_dma_probe(struct platform_device *pdev) · 46 unmodified lines
949 jzchan->vchan.desc_free = jz4780_dma_desc_free;936 jzchan->vchan.desc_free = jz4780_dma_desc_free;
950 }937 }
951 938
939 ret = platform_get_irq(pdev, 0);
940 if (ret < 0)
941 goto err_disable_clk;
942
943 jzdma->irq = ret;
944
945 ret = request_irq(jzdma->irq, jz4780_dma_irq_handler, 0, dev_name(dev),
946 jzdma);
947 if (ret) {
948 dev_err(dev, "failed to request IRQ %u!\n", jzdma->irq);
949 goto err_disable_clk;
950 }
951
952 ret = dmaenginem_async_device_register(dd);952 ret = dmaenginem_async_device_register(dd);
953 if (ret) {953 if (ret) {
954 dev_err(dev, "failed to register device\n");954 dev_err(dev, "failed to register device\n");
955 goto err_disable_clk;955 goto err_free_irq;
956 }956 }
957 957
958 /* Register with OF DMA helpers. */958 /* Register with OF DMA helpers. */
@@ -960,17 +960,17 @@ static int jz4780_dma_probe(struct platform_device *pdev) · 1 unmodified line
960 jzdma);960 jzdma);
961 if (ret) {961 if (ret) {
962 dev_err(dev, "failed to register OF DMA controller\n");962 dev_err(dev, "failed to register OF DMA controller\n");
963 goto err_disable_clk;963 goto err_free_irq;
964 }964 }
965 965
966 dev_info(dev, "JZ4780 DMA controller initialised\n");966 dev_info(dev, "JZ4780 DMA controller initialised\n");
967 return 0;967 return 0;
968 968
969err_disable_clk:
970 clk_disable_unprepare(jzdma->clk);
971
972err_free_irq:969err_free_irq:
973 free_irq(jzdma->irq, jzdma);970 free_irq(jzdma->irq, jzdma);
971
972err_disable_clk:
973 clk_disable_unprepare(jzdma->clk);
974 return ret;974 return ret;
975}975}
976 976
drivers/dma/dw-edma/dw-edma-core.c+6−5
@@ -405,7 +405,7 @@ dw_edma_device_transfer(struct dw_edma_transfer *xfer) · 404 unmodified lines
405 if (xfer->cyclic) {405 if (xfer->cyclic) {
406 burst->dar = xfer->xfer.cyclic.paddr;406 burst->dar = xfer->xfer.cyclic.paddr;
407 } else {407 } else {
408 burst->dar = sg_dma_address(sg);408 burst->dar = dst_addr;
409 /* Unlike the typical assumption by other409 /* Unlike the typical assumption by other
410 * drivers/IPs the peripheral memory isn't410 * drivers/IPs the peripheral memory isn't
411 * a FIFO memory, in this case, it's a411 * a FIFO memory, in this case, it's a
@@ -413,14 +413,13 @@ dw_edma_device_transfer(struct dw_edma_transfer *xfer) · 1 unmodified line
413 * and destination addresses are increased413 * and destination addresses are increased
414 * by the same portion (data length)414 * by the same portion (data length)
415 */415 */
416 src_addr += sg_dma_len(sg);
417 }416 }
418 } else {417 } else {
419 burst->dar = dst_addr;418 burst->dar = dst_addr;
420 if (xfer->cyclic) {419 if (xfer->cyclic) {
421 burst->sar = xfer->xfer.cyclic.paddr;420 burst->sar = xfer->xfer.cyclic.paddr;
422 } else {421 } else {
423 burst->sar = sg_dma_address(sg);422 burst->sar = src_addr;
424 /* Unlike the typical assumption by other423 /* Unlike the typical assumption by other
425 * drivers/IPs the peripheral memory isn't424 * drivers/IPs the peripheral memory isn't
426 * a FIFO memory, in this case, it's a425 * a FIFO memory, in this case, it's a
@@ -428,12 +427,14 @@ dw_edma_device_transfer(struct dw_edma_transfer *xfer) · 1 unmodified line
428 * and destination addresses are increased427 * and destination addresses are increased
429 * by the same portion (data length)428 * by the same portion (data length)
430 */429 */
431 dst_addr += sg_dma_len(sg);
432 }430 }
433 }431 }
434 432
435 if (!xfer->cyclic)433 if (!xfer->cyclic) {
434 src_addr += sg_dma_len(sg);
435 dst_addr += sg_dma_len(sg);
436 sg = sg_next(sg);436 sg = sg_next(sg);
437 }
437 }438 }
438 439
439 return vchan_tx_prep(&chan->vc, &desc->vd, xfer->flags);440 return vchan_tx_prep(&chan->vc, &desc->vd, xfer->flags);
drivers/dma/fsldma.c+1−1
@@ -1163,7 +1163,7 @@ static int fsl_dma_chan_probe(struct fsldma_device *fdev, · 1162 unmodified lines
1163 switch (chan->feature & FSL_DMA_IP_MASK) {1163 switch (chan->feature & FSL_DMA_IP_MASK) {
1164 case FSL_DMA_IP_85XX:1164 case FSL_DMA_IP_85XX:
1165 chan->toggle_ext_pause = fsl_chan_toggle_ext_pause;1165 chan->toggle_ext_pause = fsl_chan_toggle_ext_pause;
1166 /* Fall through */1166 fallthrough;
1167 case FSL_DMA_IP_83XX:1167 case FSL_DMA_IP_83XX:
1168 chan->toggle_ext_start = fsl_chan_toggle_ext_start;1168 chan->toggle_ext_start = fsl_chan_toggle_ext_start;
1169 chan->set_src_loop_size = fsl_chan_set_src_loop_size;1169 chan->set_src_loop_size = fsl_chan_set_src_loop_size;
drivers/dma/fsldma.h+6−6
@@ -205,10 +205,10 @@ struct fsldma_chan { · 204 unmodified lines
205#else205#else
206static u64 fsl_ioread64(const u64 __iomem *addr)206static u64 fsl_ioread64(const u64 __iomem *addr)
207{207{
208 u32 fsl_addr = lower_32_bits(addr);208 u32 val_lo = in_le32((u32 __iomem *)addr);
209 u64 fsl_addr_hi = (u64)in_le32((u32 *)(fsl_addr + 1)) << 32;209 u32 val_hi = in_le32((u32 __iomem *)addr + 1);
210 210
211 return fsl_addr_hi | in_le32((u32 *)fsl_addr);211 return ((u64)val_hi << 32) + val_lo;
212}212}
213 213
214static void fsl_iowrite64(u64 val, u64 __iomem *addr)214static void fsl_iowrite64(u64 val, u64 __iomem *addr)
@@ -219,10 +219,10 @@ static void fsl_iowrite64(u64 val, u64 __iomem *addr) · 4 unmodified lines
219 219
220static u64 fsl_ioread64be(const u64 __iomem *addr)220static u64 fsl_ioread64be(const u64 __iomem *addr)
221{221{
222 u32 fsl_addr = lower_32_bits(addr);222 u32 val_hi = in_be32((u32 __iomem *)addr);
223 u64 fsl_addr_hi = (u64)in_be32((u32 *)fsl_addr) << 32;223 u32 val_lo = in_be32((u32 __iomem *)addr + 1);
224 224
225 return fsl_addr_hi | in_be32((u32 *)(fsl_addr + 1));225 return ((u64)val_hi << 32) + val_lo;
226}226}
227 227
228static void fsl_iowrite64be(u64 val, u64 __iomem *addr)228static void fsl_iowrite64be(u64 val, u64 __iomem *addr)
drivers/dma/idxd/device.c+26−0
@@ -410,10 +410,27 @@ int idxd_device_enable(struct idxd_device *idxd) · 409 unmodified lines
410 return 0;410 return 0;
411}411}
412 412
413void idxd_device_wqs_clear_state(struct idxd_device *idxd)
414{
415 int i;
416
417 lockdep_assert_held(&idxd->dev_lock);
418
419 for (i = 0; i < idxd->max_wqs; i++) {
420 struct idxd_wq *wq = &idxd->wqs[i];
421
422 if (wq->state == IDXD_WQ_ENABLED) {
423 idxd_wq_disable_cleanup(wq);
424 wq->state = IDXD_WQ_DISABLED;
425 }
426 }
427}
428
413int idxd_device_disable(struct idxd_device *idxd)429int idxd_device_disable(struct idxd_device *idxd)
414{430{
415 struct device *dev = &idxd->pdev->dev;431 struct device *dev = &idxd->pdev->dev;
416 u32 status;432 u32 status;
433 unsigned long flags;
417 434
418 if (!idxd_is_enabled(idxd)) {435 if (!idxd_is_enabled(idxd)) {
419 dev_dbg(dev, "Device is not enabled\n");436 dev_dbg(dev, "Device is not enabled\n");
@@ -429,13 +446,22 @@ int idxd_device_disable(struct idxd_device *idxd) · 9 unmodified lines
429 return -ENXIO;446 return -ENXIO;
430 }447 }
431 448
449 spin_lock_irqsave(&idxd->dev_lock, flags);
450 idxd_device_wqs_clear_state(idxd);
432 idxd->state = IDXD_DEV_CONF_READY;451 idxd->state = IDXD_DEV_CONF_READY;
452 spin_unlock_irqrestore(&idxd->dev_lock, flags);
433 return 0;453 return 0;
434}454}
435 455
436void idxd_device_reset(struct idxd_device *idxd)456void idxd_device_reset(struct idxd_device *idxd)
437{457{
458 unsigned long flags;
459
438 idxd_cmd_exec(idxd, IDXD_CMD_RESET_DEVICE, 0, NULL);460 idxd_cmd_exec(idxd, IDXD_CMD_RESET_DEVICE, 0, NULL);
461 spin_lock_irqsave(&idxd->dev_lock, flags);
462 idxd_device_wqs_clear_state(idxd);
463 idxd->state = IDXD_DEV_CONF_READY;
464 spin_unlock_irqrestore(&idxd->dev_lock, flags);
439}465}
440 466
441/* Device configuration bits */467/* Device configuration bits */
drivers/dma/idxd/irq.c+0−12
@@ -11,18 +11,6 @@ · 10 unmodified lines
11#include "idxd.h"11#include "idxd.h"
12#include "registers.h"12#include "registers.h"
13 13
14void idxd_device_wqs_clear_state(struct idxd_device *idxd)
15{
16 int i;
17
18 lockdep_assert_held(&idxd->dev_lock);
19 for (i = 0; i < idxd->max_wqs; i++) {
20 struct idxd_wq *wq = &idxd->wqs[i];
21
22 wq->state = IDXD_WQ_DISABLED;
23 }
24}
25
26static void idxd_device_reinit(struct work_struct *work)14static void idxd_device_reinit(struct work_struct *work)
27{15{
28 struct idxd_device *idxd = container_of(work, struct idxd_device, work);16 struct idxd_device *idxd = container_of(work, struct idxd_device, work);
drivers/dma/imx-dma.c+1−1
@@ -556,7 +556,7 @@ static int imxdma_xfer_desc(struct imxdma_desc *d) · 555 unmodified lines
556 * We fall-through here intentionally, since a 2D transfer is556 * We fall-through here intentionally, since a 2D transfer is
557 * similar to MEMCPY just adding the 2D slot configuration.557 * similar to MEMCPY just adding the 2D slot configuration.
558 */558 */
559 /* Fall through */559 fallthrough;
560 case IMXDMA_DESC_MEMCPY:560 case IMXDMA_DESC_MEMCPY:
561 imx_dmav1_writel(imxdma, d->src, DMA_SAR(imxdmac->channel));561 imx_dmav1_writel(imxdma, d->src, DMA_SAR(imxdmac->channel));
562 imx_dmav1_writel(imxdma, d->dest, DMA_DAR(imxdmac->channel));562 imx_dmav1_writel(imxdma, d->dest, DMA_DAR(imxdmac->channel));
drivers/dma/iop-adma.h+6−6
@@ -496,7 +496,7 @@ iop3xx_desc_init_xor(struct iop3xx_desc_aau *hw_desc, int src_cnt, · 495 unmodified lines
496 }496 }
497 hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = edcr;497 hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = edcr;
498 src_cnt = 24;498 src_cnt = 24;
499 /* fall through */499 fallthrough;
500 case 17 ... 24:500 case 17 ... 24:
501 if (!u_desc_ctrl.field.blk_ctrl) {501 if (!u_desc_ctrl.field.blk_ctrl) {
502 hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = 0;502 hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = 0;
@@ -510,7 +510,7 @@ iop3xx_desc_init_xor(struct iop3xx_desc_aau *hw_desc, int src_cnt, · 7 unmodified lines
510 }510 }
511 hw_desc->src_edc[AAU_EDCR1_IDX].e_desc_ctrl = edcr;511 hw_desc->src_edc[AAU_EDCR1_IDX].e_desc_ctrl = edcr;
512 src_cnt = 16;512 src_cnt = 16;
513 /* fall through */513 fallthrough;
514 case 9 ... 16:514 case 9 ... 16:
515 if (!u_desc_ctrl.field.blk_ctrl)515 if (!u_desc_ctrl.field.blk_ctrl)
516 u_desc_ctrl.field.blk_ctrl = 0x2; /* use EDCR0 */516 u_desc_ctrl.field.blk_ctrl = 0x2; /* use EDCR0 */
@@ -522,7 +522,7 @@ iop3xx_desc_init_xor(struct iop3xx_desc_aau *hw_desc, int src_cnt, · 5 unmodified lines
522 }522 }
523 hw_desc->src_edc[AAU_EDCR0_IDX].e_desc_ctrl = edcr;523 hw_desc->src_edc[AAU_EDCR0_IDX].e_desc_ctrl = edcr;
524 src_cnt = 8;524 src_cnt = 8;
525 /* fall through */525 fallthrough;
526 case 2 ... 8:526 case 2 ... 8:
527 shift = 1;527 shift = 1;
528 for (i = 0; i < src_cnt; i++) {528 for (i = 0; i < src_cnt; i++) {
@@ -602,19 +602,19 @@ iop_desc_init_null_xor(struct iop_adma_desc_slot *desc, int src_cnt, · 73 unmodified lines
602 case 25 ... 32:602 case 25 ... 32:
603 u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */603 u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */
604 hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = 0;604 hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = 0;
605 /* fall through */605 fallthrough;
606 case 17 ... 24:606 case 17 ... 24:
607 if (!u_desc_ctrl.field.blk_ctrl) {607 if (!u_desc_ctrl.field.blk_ctrl) {
608 hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = 0;608 hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = 0;
609 u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */609 u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */
610 }610 }
611 hw_desc->src_edc[AAU_EDCR1_IDX].e_desc_ctrl = 0;611 hw_desc->src_edc[AAU_EDCR1_IDX].e_desc_ctrl = 0;
612 /* fall through */612 fallthrough;
613 case 9 ... 16:613 case 9 ... 16:
614 if (!u_desc_ctrl.field.blk_ctrl)614 if (!u_desc_ctrl.field.blk_ctrl)
615 u_desc_ctrl.field.blk_ctrl = 0x2; /* use EDCR0 */615 u_desc_ctrl.field.blk_ctrl = 0x2; /* use EDCR0 */
616 hw_desc->src_edc[AAU_EDCR0_IDX].e_desc_ctrl = 0;616 hw_desc->src_edc[AAU_EDCR0_IDX].e_desc_ctrl = 0;
617 /* fall through */617 fallthrough;
618 case 1 ... 8:618 case 1 ... 8:
619 if (!u_desc_ctrl.field.blk_ctrl && src_cnt > 4)619 if (!u_desc_ctrl.field.blk_ctrl && src_cnt > 4)
620 u_desc_ctrl.field.blk_ctrl = 0x1; /* use mini-desc */620 u_desc_ctrl.field.blk_ctrl = 0x1; /* use mini-desc */
drivers/dma/nbpfaxi.c+1−1
@@ -483,7 +483,7 @@ static size_t nbpf_xfer_size(struct nbpf_device *nbpf, · 482 unmodified lines
483 483
484 default:484 default:
485 pr_warn("%s(): invalid bus width %u\n", __func__, width);485 pr_warn("%s(): invalid bus width %u\n", __func__, width);
486 /* fall through */486 fallthrough;
487 case DMA_SLAVE_BUSWIDTH_1_BYTE:487 case DMA_SLAVE_BUSWIDTH_1_BYTE:
488 size = burst;488 size = burst;
489 }489 }
drivers/dma/of-dma.c+4−4
@@ -71,12 +71,12 @@ static struct dma_chan *of_dma_router_xlate(struct of_phandle_args *dma_spec, · 70 unmodified lines
71 return NULL;71 return NULL;
72 72
73 chan = ofdma_target->of_dma_xlate(&dma_spec_target, ofdma_target);73 chan = ofdma_target->of_dma_xlate(&dma_spec_target, ofdma_target);
74 if (chan) {74 if (IS_ERR_OR_NULL(chan)) {
75 chan->router = ofdma->dma_router;
76 chan->route_data = route_data;
77 } else {
78 ofdma->dma_router->route_free(ofdma->dma_router->dev,75 ofdma->dma_router->route_free(ofdma->dma_router->dev,
79 route_data);76 route_data);
77 } else {
78 chan->router = ofdma->dma_router;
79 chan->route_data = route_data;
80 }80 }
81 81
82 /*82 /*
drivers/dma/pl330.c+4−8
@@ -1061,16 +1061,16 @@ static bool _start(struct pl330_thread *thrd) · 1060 unmodified lines
1061 1061
1062 if (_state(thrd) == PL330_STATE_KILLING)1062 if (_state(thrd) == PL330_STATE_KILLING)
1063 UNTIL(thrd, PL330_STATE_STOPPED)1063 UNTIL(thrd, PL330_STATE_STOPPED)
1064 /* fall through */1064 fallthrough;
1065 1065
1066 case PL330_STATE_FAULTING:1066 case PL330_STATE_FAULTING:
1067 _stop(thrd);1067 _stop(thrd);
1068 /* fall through */1068 fallthrough;
1069 1069
1070 case PL330_STATE_KILLING:1070 case PL330_STATE_KILLING:
1071 case PL330_STATE_COMPLETING:1071 case PL330_STATE_COMPLETING:
1072 UNTIL(thrd, PL330_STATE_STOPPED)1072 UNTIL(thrd, PL330_STATE_STOPPED)
1073 /* fall through */1073 fallthrough;
1074 1074
1075 case PL330_STATE_STOPPED:1075 case PL330_STATE_STOPPED:
1076 return _trigger(thrd);1076 return _trigger(thrd);
@@ -1121,7 +1121,6 @@ static u32 _emit_load(unsigned int dry_run, u8 buf[], · 44 unmodified lines
1121 1121
1122 switch (direction) {1122 switch (direction) {
1123 case DMA_MEM_TO_MEM:1123 case DMA_MEM_TO_MEM:
1124 /* fall through */
1125 case DMA_MEM_TO_DEV:1124 case DMA_MEM_TO_DEV:
1126 off += _emit_LD(dry_run, &buf[off], cond);1125 off += _emit_LD(dry_run, &buf[off], cond);
1127 break;1126 break;
@@ -1155,7 +1154,6 @@ static inline u32 _emit_store(unsigned int dry_run, u8 buf[], · 27 unmodified lines
1155 1154
1156 switch (direction) {1155 switch (direction) {
1157 case DMA_MEM_TO_MEM:1156 case DMA_MEM_TO_MEM:
1158 /* fall through */
1159 case DMA_DEV_TO_MEM:1157 case DMA_DEV_TO_MEM:
1160 off += _emit_ST(dry_run, &buf[off], cond);1158 off += _emit_ST(dry_run, &buf[off], cond);
1161 break;1159 break;
@@ -1216,7 +1214,6 @@ static int _bursts(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[], · 54 unmodified lines
1216 1214
1217 switch (pxs->desc->rqtype) {1215 switch (pxs->desc->rqtype) {
1218 case DMA_MEM_TO_DEV:1216 case DMA_MEM_TO_DEV:
1219 /* fall through */
1220 case DMA_DEV_TO_MEM:1217 case DMA_DEV_TO_MEM:
1221 off += _ldst_peripheral(pl330, dry_run, &buf[off], pxs, cyc,1218 off += _ldst_peripheral(pl330, dry_run, &buf[off], pxs, cyc,
1222 cond);1219 cond);
@@ -1266,7 +1263,6 @@ static int _dregs(struct pl330_dmac *pl330, unsigned int dry_run, u8 buf[], · 43 unmodified lines
1266 1263
1267 switch (pxs->desc->rqtype) {1264 switch (pxs->desc->rqtype) {
1268 case DMA_MEM_TO_DEV:1265 case DMA_MEM_TO_DEV:
1269 /* fall through */
1270 case DMA_DEV_TO_MEM:1266 case DMA_DEV_TO_MEM:
1271 off += _emit_MOV(dry_run, &buf[off], CCR, dregs_ccr);1267 off += _emit_MOV(dry_run, &buf[off], CCR, dregs_ccr);
1272 off += _ldst_peripheral(pl330, dry_run, &buf[off], pxs, 1,1268 off += _ldst_peripheral(pl330, dry_run, &buf[off], pxs, 1,
@@ -2801,6 +2797,7 @@ pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst, · 1528 unmodified lines
2801 while (burst != (1 << desc->rqcfg.brst_size))2797 while (burst != (1 << desc->rqcfg.brst_size))
2802 desc->rqcfg.brst_size++;2798 desc->rqcfg.brst_size++;
2803 2799
2800 desc->rqcfg.brst_len = get_burst_len(desc, len);
2804 /*2801 /*
2805 * If burst size is smaller than bus width then make sure we only2802 * If burst size is smaller than bus width then make sure we only
2806 * transfer one at a time to avoid a burst stradling an MFIFO entry.2803 * transfer one at a time to avoid a burst stradling an MFIFO entry.
@@ -2808,7 +2805,6 @@ pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst, · 1 unmodified line
2808 if (desc->rqcfg.brst_size * 8 < pl330->pcfg.data_bus_width)2805 if (desc->rqcfg.brst_size * 8 < pl330->pcfg.data_bus_width)
2809 desc->rqcfg.brst_len = 1;2806 desc->rqcfg.brst_len = 1;
2810 2807
2811 desc->rqcfg.brst_len = get_burst_len(desc, len);
2812 desc->bytes_requested = len;2808 desc->bytes_requested = len;
2813 2809
2814 desc->txd.flags = flags;2810 desc->txd.flags = flags;
drivers/dma/sh/shdma-base.c+1−1
@@ -383,7 +383,7 @@ static dma_async_tx_callback __ld_cleanup(struct shdma_chan *schan, bool all) · 382 unmodified lines
383 switch (desc->mark) {383 switch (desc->mark) {
384 case DESC_COMPLETED:384 case DESC_COMPLETED:
385 desc->mark = DESC_WAITING;385 desc->mark = DESC_WAITING;
386 /* Fall through */386 fallthrough;
387 case DESC_WAITING:387 case DESC_WAITING:
388 if (head_acked)388 if (head_acked)
389 async_tx_ack(&desc->async_tx);389 async_tx_ack(&desc->async_tx);
drivers/dma/ti/k3-udma.c+5−5
@@ -2059,9 +2059,9 @@ udma_prep_slave_sg_tr(struct udma_chan *uc, struct scatterlist *sgl, · 2058 unmodified lines
2059 return NULL;2059 return NULL;
2060 }2060 }
2061 2061
2062 cppi5_tr_init(&tr_req[i].flags, CPPI5_TR_TYPE1, false, false,2062 cppi5_tr_init(&tr_req[tr_idx].flags, CPPI5_TR_TYPE1, false,
2063 CPPI5_TR_EVENT_SIZE_COMPLETION, 0);2063 false, CPPI5_TR_EVENT_SIZE_COMPLETION, 0);
2064 cppi5_tr_csf_set(&tr_req[i].flags, CPPI5_TR_CSF_SUPR_EVT);2064 cppi5_tr_csf_set(&tr_req[tr_idx].flags, CPPI5_TR_CSF_SUPR_EVT);
2065 2065
2066 tr_req[tr_idx].addr = sg_addr;2066 tr_req[tr_idx].addr = sg_addr;
2067 tr_req[tr_idx].icnt0 = tr0_cnt0;2067 tr_req[tr_idx].icnt0 = tr0_cnt0;
@@ -3101,14 +3101,14 @@ static struct udma_match_data am654_main_data = { · 1033 unmodified lines
3101 .psil_base = 0x1000,3101 .psil_base = 0x1000,
3102 .enable_memcpy_support = true,3102 .enable_memcpy_support = true,
3103 .statictr_z_mask = GENMASK(11, 0),3103 .statictr_z_mask = GENMASK(11, 0),
3104 .rchan_oes_offset = 0x2000,3104 .rchan_oes_offset = 0x200,
3105};3105};
3106 3106
3107static struct udma_match_data am654_mcu_data = {3107static struct udma_match_data am654_mcu_data = {
3108 .psil_base = 0x6000,3108 .psil_base = 0x6000,
3109 .enable_memcpy_support = false,3109 .enable_memcpy_support = false,
3110 .statictr_z_mask = GENMASK(11, 0),3110 .statictr_z_mask = GENMASK(11, 0),
3111 .rchan_oes_offset = 0x2000,3111 .rchan_oes_offset = 0x200,
3112};3112};
3113 3113
3114static struct udma_match_data j721e_main_data = {3114static struct udma_match_data j721e_main_data = {
drivers/edac/amd64_edac.c+1−1
@@ -3375,7 +3375,7 @@ static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt) · 3374 unmodified lines
3375 pvt->ops = &family_types[F17_M70H_CPUS].ops;3375 pvt->ops = &family_types[F17_M70H_CPUS].ops;
3376 break;3376 break;
3377 }3377 }
3378 /* fall through */3378 fallthrough;
3379 case 0x18:3379 case 0x18:
3380 fam_type = &family_types[F17_CPUS];3380 fam_type = &family_types[F17_CPUS];
3381 pvt->ops = &family_types[F17_CPUS].ops;3381 pvt->ops = &family_types[F17_CPUS].ops;
drivers/edac/ghes_edac.c+6−4
@@ -55,6 +55,8 @@ static DEFINE_SPINLOCK(ghes_lock); · 54 unmodified lines
55static bool __read_mostly force_load;55static bool __read_mostly force_load;
56module_param(force_load, bool, 0);56module_param(force_load, bool, 0);
57 57
58static bool system_scanned;
59
58/* Memory Device - Type 17 of SMBIOS spec */60/* Memory Device - Type 17 of SMBIOS spec */
59struct memdev_dmi_entry {61struct memdev_dmi_entry {
60 u8 type;62 u8 type;
@@ -225,14 +227,12 @@ static void enumerate_dimms(const struct dmi_header *dh, void *arg) · 164 unmodified lines
225 227
226static void ghes_scan_system(void)228static void ghes_scan_system(void)
227{229{
228 static bool scanned;230 if (system_scanned)
229
230 if (scanned)
231 return;231 return;
232 232
233 dmi_walk(enumerate_dimms, &ghes_hw);233 dmi_walk(enumerate_dimms, &ghes_hw);
234 234
235 scanned = true;235 system_scanned = true;
236}236}
237 237
238void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err)238void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err)
@@ -631,6 +631,8 @@ void ghes_edac_unregister(struct ghes *ghes) · 392 unmodified lines
631 631
632 mutex_lock(&ghes_reg_mutex);632 mutex_lock(&ghes_reg_mutex);
633 633
634 system_scanned = false;
635
634 if (!refcount_dec_and_test(&ghes_refcount))636 if (!refcount_dec_and_test(&ghes_refcount))
635 goto unlock;637 goto unlock;
636 638
drivers/edac/i7core_edac.c+2−2
@@ -1710,9 +1710,9 @@ static void i7core_mce_output_error(struct mem_ctl_info *mci, · 1709 unmodified lines
1710 if (uncorrected_error) {1710 if (uncorrected_error) {
1711 core_err_cnt = 1;1711 core_err_cnt = 1;
1712 if (ripv)1712 if (ripv)
1713 tp_event = HW_EVENT_ERR_FATAL;
1714 else
1715 tp_event = HW_EVENT_ERR_UNCORRECTED;1713 tp_event = HW_EVENT_ERR_UNCORRECTED;
1714 else
1715 tp_event = HW_EVENT_ERR_FATAL;
1716 } else {1716 } else {
1717 tp_event = HW_EVENT_ERR_CORRECTED;1717 tp_event = HW_EVENT_ERR_CORRECTED;
1718 }1718 }
drivers/edac/pnd2_edac.c+2−2
@@ -198,7 +198,7 @@ static int apl_rd_reg(int port, int off, int op, void *data, size_t sz, char *na · 197 unmodified lines
198 switch (sz) {198 switch (sz) {
199 case 8:199 case 8:
200 ret = _apl_rd_reg(port, off + 4, op, (u32 *)(data + 4));200 ret = _apl_rd_reg(port, off + 4, op, (u32 *)(data + 4));
201 /* fall through */201 fallthrough;
202 case 4:202 case 4:
203 ret |= _apl_rd_reg(port, off, op, (u32 *)data);203 ret |= _apl_rd_reg(port, off, op, (u32 *)data);
204 pnd2_printk(KERN_DEBUG, "%s=%x%08x ret=%d\n", name,204 pnd2_printk(KERN_DEBUG, "%s=%x%08x ret=%d\n", name,
@@ -1155,7 +1155,7 @@ static void pnd2_mce_output_error(struct mem_ctl_info *mci, const struct mce *m, · 950 unmodified lines
1155 u32 optypenum = GET_BITFIELD(m->status, 4, 6);1155 u32 optypenum = GET_BITFIELD(m->status, 4, 6);
1156 int rc;1156 int rc;
1157 1157
1158 tp_event = uc_err ? (ripv ? HW_EVENT_ERR_FATAL : HW_EVENT_ERR_UNCORRECTED) :1158 tp_event = uc_err ? (ripv ? HW_EVENT_ERR_UNCORRECTED : HW_EVENT_ERR_FATAL) :
1159 HW_EVENT_ERR_CORRECTED;1159 HW_EVENT_ERR_CORRECTED;
1160 1160
1161 /*1161 /*
drivers/edac/sb_edac.c+2−2
@@ -2982,9 +2982,9 @@ static void sbridge_mce_output_error(struct mem_ctl_info *mci, · 2981 unmodified lines
2982 if (uncorrected_error) {2982 if (uncorrected_error) {
2983 core_err_cnt = 1;2983 core_err_cnt = 1;
2984 if (ripv) {2984 if (ripv) {
2985 tp_event = HW_EVENT_ERR_FATAL;
2986 } else {
2987 tp_event = HW_EVENT_ERR_UNCORRECTED;2985 tp_event = HW_EVENT_ERR_UNCORRECTED;
2986 } else {
2987 tp_event = HW_EVENT_ERR_FATAL;
2988 }2988 }
2989 } else {2989 } else {
2990 tp_event = HW_EVENT_ERR_CORRECTED;2990 tp_event = HW_EVENT_ERR_CORRECTED;
drivers/edac/skx_common.c+2−2
@@ -493,9 +493,9 @@ static void skx_mce_output_error(struct mem_ctl_info *mci, · 492 unmodified lines
493 if (uncorrected_error) {493 if (uncorrected_error) {
494 core_err_cnt = 1;494 core_err_cnt = 1;
495 if (ripv) {495 if (ripv) {
496 tp_event = HW_EVENT_ERR_FATAL;
497 } else {
498 tp_event = HW_EVENT_ERR_UNCORRECTED;496 tp_event = HW_EVENT_ERR_UNCORRECTED;
497 } else {
498 tp_event = HW_EVENT_ERR_FATAL;
499 }499 }
500 } else {500 } else {
501 tp_event = HW_EVENT_ERR_CORRECTED;501 tp_event = HW_EVENT_ERR_CORRECTED;
drivers/firewire/core-device.c+1−1
@@ -957,7 +957,7 @@ static void set_broadcast_channel(struct fw_device *device, int generation) · 956 unmodified lines
957 device->bc_implemented = BC_IMPLEMENTED;957 device->bc_implemented = BC_IMPLEMENTED;
958 break;958 break;
959 }959 }
960 /* else, fall through - to case address error */960 fallthrough; /* to case address error */
961 case RCODE_ADDRESS_ERROR:961 case RCODE_ADDRESS_ERROR:
962 device->bc_implemented = BC_UNIMPLEMENTED;962 device->bc_implemented = BC_UNIMPLEMENTED;
963 }963 }
drivers/firewire/core-iso.c+1−1
@@ -277,7 +277,7 @@ static int manage_channel(struct fw_card *card, int irm_id, int generation, · 276 unmodified lines
277 if ((data[0] & bit) == (data[1] & bit))277 if ((data[0] & bit) == (data[1] & bit))
278 continue;278 continue;
279 279
280 /* fall through - It's a 1394-1995 IRM, retry. */280 fallthrough; /* It's a 1394-1995 IRM, retry */
281 default:281 default:
282 if (retry) {282 if (retry) {
283 retry--;283 retry--;
drivers/firewire/core-topology.c+1−1
@@ -54,7 +54,7 @@ static u32 *count_ports(u32 *sid, int *total_port_count, int *child_port_count) · 53 unmodified lines
54 switch (port_type) {54 switch (port_type) {
55 case SELFID_PORT_CHILD:55 case SELFID_PORT_CHILD:
56 (*child_port_count)++;56 (*child_port_count)++;
57 /* fall through */57 fallthrough;
58 case SELFID_PORT_PARENT:58 case SELFID_PORT_PARENT:
59 case SELFID_PORT_NCONN:59 case SELFID_PORT_NCONN:
60 (*total_port_count)++;60 (*total_port_count)++;
drivers/firewire/core-transaction.c+2−2
@@ -1097,14 +1097,14 @@ static void handle_registers(struct fw_card *card, struct fw_request *request, · 1096 unmodified lines
1097 rcode = RCODE_ADDRESS_ERROR;1097 rcode = RCODE_ADDRESS_ERROR;
1098 break;1098 break;
1099 }1099 }
1100 /* else fall through */1100 fallthrough;
1101 1101
1102 case CSR_NODE_IDS:1102 case CSR_NODE_IDS:
1103 /*1103 /*
1104 * per IEEE 1394-2008 8.3.22.3, not IEEE 1394.1-2004 3.2.81104 * per IEEE 1394-2008 8.3.22.3, not IEEE 1394.1-2004 3.2.8
1105 * and 9.6, but interoperable with IEEE 1394.1-2004 bridges1105 * and 9.6, but interoperable with IEEE 1394.1-2004 bridges
1106 */1106 */
1107 /* fall through */1107 fallthrough;
1108 1108
1109 case CSR_STATE_CLEAR:1109 case CSR_STATE_CLEAR:
1110 case CSR_STATE_SET:1110 case CSR_STATE_SET:
drivers/firewire/ohci.c+2−2
@@ -1495,7 +1495,7 @@ static int handle_at_packet(struct context *context, · 1494 unmodified lines
1495 packet->ack = RCODE_GENERATION;1495 packet->ack = RCODE_GENERATION;
1496 break;1496 break;
1497 }1497 }
1498 /* fall through */1498 fallthrough;
1499 1499
1500 default:1500 default:
1501 packet->ack = RCODE_SEND_ERROR;1501 packet->ack = RCODE_SEND_ERROR;
@@ -3054,7 +3054,7 @@ static int ohci_start_iso(struct fw_iso_context *base, · 1552 unmodified lines
3054 3054
3055 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:3055 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3056 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;3056 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
3057 /* fall through */3057 fallthrough;
3058 case FW_ISO_CONTEXT_RECEIVE:3058 case FW_ISO_CONTEXT_RECEIVE:
3059 index = ctx - ohci->ir_context_list;3059 index = ctx - ohci->ir_context_list;
3060 match = (tags << 28) | (sync << 8) | ctx->base.channel;3060 match = (tags << 28) | (sync << 8) | ctx->base.channel;
drivers/firmware/efi/efi.c+2−0
@@ -381,6 +381,7 @@ static int __init efisubsys_init(void) · 380 unmodified lines
381 efi_kobj = kobject_create_and_add("efi", firmware_kobj);381 efi_kobj = kobject_create_and_add("efi", firmware_kobj);
382 if (!efi_kobj) {382 if (!efi_kobj) {
383 pr_err("efi: Firmware registration failed.\n");383 pr_err("efi: Firmware registration failed.\n");
384 destroy_workqueue(efi_rts_wq);
384 return -ENOMEM;385 return -ENOMEM;
385 }386 }
386 387
@@ -424,6 +425,7 @@ err_unregister: · 37 unmodified lines
424 generic_ops_unregister();425 generic_ops_unregister();
425err_put:426err_put:
426 kobject_put(efi_kobj);427 kobject_put(efi_kobj);
428 destroy_workqueue(efi_rts_wq);
427 return error;429 return error;
428}430}
429 431
drivers/firmware/efi/libstub/efi-stub-helper.c+10−2
@@ -187,20 +187,28 @@ int efi_printk(const char *fmt, ...) · 186 unmodified lines
187 */187 */
188efi_status_t efi_parse_options(char const *cmdline)188efi_status_t efi_parse_options(char const *cmdline)
189{189{
190 size_t len = strlen(cmdline) + 1;190 size_t len;
191 efi_status_t status;191 efi_status_t status;
192 char *str, *buf;192 char *str, *buf;
193 193
194 if (!cmdline)
195 return EFI_SUCCESS;
196
197 len = strnlen(cmdline, COMMAND_LINE_SIZE - 1) + 1;
194 status = efi_bs_call(allocate_pool, EFI_LOADER_DATA, len, (void **)&buf);198 status = efi_bs_call(allocate_pool, EFI_LOADER_DATA, len, (void **)&buf);
195 if (status != EFI_SUCCESS)199 if (status != EFI_SUCCESS)
196 return status;200 return status;
197 201
198 str = skip_spaces(memcpy(buf, cmdline, len));202 memcpy(buf, cmdline, len - 1);
203 buf[len - 1] = '\0';
204 str = skip_spaces(buf);
199 205
200 while (*str) {206 while (*str) {
201 char *param, *val;207 char *param, *val;
202 208
203 str = next_arg(str, &param, &val);209 str = next_arg(str, &param, &val);
210 if (!val && !strcmp(param, "--"))
211 break;
204 212
205 if (!strcmp(param, "nokaslr")) {213 if (!strcmp(param, "nokaslr")) {
206 efi_nokaslr = true;214 efi_nokaslr = true;
drivers/firmware/ti_sci.c+68−87
@@ -64,22 +64,6 @@ struct ti_sci_xfers_info { · 63 unmodified lines
64 spinlock_t xfer_lock;64 spinlock_t xfer_lock;
65};65};
66 66
67/**
68 * struct ti_sci_rm_type_map - Structure representing TISCI Resource
69 * management representation of dev_ids.
70 * @dev_id: TISCI device ID
71 * @type: Corresponding id as identified by TISCI RM.
72 *
73 * Note: This is used only as a work around for using RM range apis
74 * for AM654 SoC. For future SoCs dev_id will be used as type
75 * for RM range APIs. In order to maintain ABI backward compatibility
76 * type is not being changed for AM654 SoC.
77 */
78struct ti_sci_rm_type_map {
79 u32 dev_id;
80 u16 type;
81};
82
83/**67/**
84 * struct ti_sci_desc - Description of SoC integration68 * struct ti_sci_desc - Description of SoC integration
85 * @default_host_id: Host identifier representing the compute entity69 * @default_host_id: Host identifier representing the compute entity
@@ -87,14 +71,12 @@ struct ti_sci_rm_type_map { · 1 unmodified line
87 * @max_msgs: Maximum number of messages that can be pending71 * @max_msgs: Maximum number of messages that can be pending
88 * simultaneously in the system72 * simultaneously in the system
89 * @max_msg_size: Maximum size of data per message that can be handled.73 * @max_msg_size: Maximum size of data per message that can be handled.
90 * @rm_type_map: RM resource type mapping structure.
91 */74 */
92struct ti_sci_desc {75struct ti_sci_desc {
93 u8 default_host_id;76 u8 default_host_id;
94 int max_rx_timeout_ms;77 int max_rx_timeout_ms;
95 int max_msgs;78 int max_msgs;
96 int max_msg_size;79 int max_msg_size;
97 struct ti_sci_rm_type_map *rm_type_map;
98};80};
99 81
100/**82/**
@@ -1710,33 +1692,6 @@ fail: · 1609 unmodified lines
1710 return ret;1692 return ret;
1711}1693}
1712 1694
1713static int ti_sci_get_resource_type(struct ti_sci_info *info, u16 dev_id,
1714 u16 *type)
1715{
1716 struct ti_sci_rm_type_map *rm_type_map = info->desc->rm_type_map;
1717 bool found = false;
1718 int i;
1719
1720 /* If map is not provided then assume dev_id is used as type */
1721 if (!rm_type_map) {
1722 *type = dev_id;
1723 return 0;
1724 }
1725
1726 for (i = 0; rm_type_map[i].dev_id; i++) {
1727 if (rm_type_map[i].dev_id == dev_id) {
1728 *type = rm_type_map[i].type;
1729 found = true;
1730 break;
1731 }
1732 }
1733
1734 if (!found)
1735 return -EINVAL;
1736
1737 return 0;
1738}
1739
1740/**1695/**
1741 * ti_sci_get_resource_range - Helper to get a range of resources assigned1696 * ti_sci_get_resource_range - Helper to get a range of resources assigned
1742 * to a host. Resource is uniquely identified by1697 * to a host. Resource is uniquely identified by
@@ -1760,7 +1715,6 @@ static int ti_sci_get_resource_range(const struct ti_sci_handle *handle, · 17 unmodified lines
1760 struct ti_sci_xfer *xfer;1715 struct ti_sci_xfer *xfer;
1761 struct ti_sci_info *info;1716 struct ti_sci_info *info;
1762 struct device *dev;1717 struct device *dev;
1763 u16 type;
1764 int ret = 0;1718 int ret = 0;
1765 1719
1766 if (IS_ERR(handle))1720 if (IS_ERR(handle))
@@ -1780,15 +1734,9 @@ static int ti_sci_get_resource_range(const struct ti_sci_handle *handle, · 13 unmodified lines
1780 return ret;1734 return ret;
1781 }1735 }
1782 1736
1783 ret = ti_sci_get_resource_type(info, dev_id, &type);
1784 if (ret) {
1785 dev_err(dev, "rm type lookup failed for %u\n", dev_id);
1786 goto fail;
1787 }
1788
1789 req = (struct ti_sci_msg_req_get_resource_range *)xfer->xfer_buf;1737 req = (struct ti_sci_msg_req_get_resource_range *)xfer->xfer_buf;
1790 req->secondary_host = s_host;1738 req->secondary_host = s_host;
1791 req->type = type & MSG_RM_RESOURCE_TYPE_MASK;1739 req->type = dev_id & MSG_RM_RESOURCE_TYPE_MASK;
1792 req->subtype = subtype & MSG_RM_RESOURCE_SUBTYPE_MASK;1740 req->subtype = subtype & MSG_RM_RESOURCE_SUBTYPE_MASK;
1793 1741
1794 ret = ti_sci_do_xfer(info, xfer);1742 ret = ti_sci_do_xfer(info, xfer);
@@ -3260,61 +3208,50 @@ u32 ti_sci_get_num_resources(struct ti_sci_resource *res) · 1465 unmodified lines
3260EXPORT_SYMBOL_GPL(ti_sci_get_num_resources);3208EXPORT_SYMBOL_GPL(ti_sci_get_num_resources);
3261 3209
3262/**3210/**
3263 * devm_ti_sci_get_of_resource() - Get a TISCI resource assigned to a device3211 * devm_ti_sci_get_resource_sets() - Get a TISCI resources assigned to a device
3264 * @handle: TISCI handle3212 * @handle: TISCI handle
3265 * @dev: Device pointer to which the resource is assigned3213 * @dev: Device pointer to which the resource is assigned
3266 * @dev_id: TISCI device id to which the resource is assigned3214 * @dev_id: TISCI device id to which the resource is assigned
3267 * @of_prop: property name by which the resource are represented3215 * @sub_types: Array of sub_types assigned corresponding to device
3216 * @sets: Number of sub_types
3268 *3217 *
3269 * Return: Pointer to ti_sci_resource if all went well else appropriate3218 * Return: Pointer to ti_sci_resource if all went well else appropriate
3270 * error pointer.3219 * error pointer.
3271 */3220 */
3272struct ti_sci_resource *3221static struct ti_sci_resource *
3273devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,3222devm_ti_sci_get_resource_sets(const struct ti_sci_handle *handle,
3274 struct device *dev, u32 dev_id, char *of_prop)3223 struct device *dev, u32 dev_id, u32 *sub_types,
3224 u32 sets)
3275{3225{
3276 struct ti_sci_resource *res;3226 struct ti_sci_resource *res;
3277 bool valid_set = false;3227 bool valid_set = false;
3278 u32 resource_subtype;
3279 int i, ret;3228 int i, ret;
3280 3229
3281 res = devm_kzalloc(dev, sizeof(*res), GFP_KERNEL);3230 res = devm_kzalloc(dev, sizeof(*res), GFP_KERNEL);
3282 if (!res)3231 if (!res)
3283 return ERR_PTR(-ENOMEM);3232 return ERR_PTR(-ENOMEM);
3284 3233
3285 ret = of_property_count_elems_of_size(dev_of_node(dev), of_prop,3234 res->sets = sets;
3286 sizeof(u32));
3287 if (ret < 0) {
3288 dev_err(dev, "%s resource type ids not available\n", of_prop);
3289 return ERR_PTR(ret);
3290 }
3291 res->sets = ret;
3292
3293 res->desc = devm_kcalloc(dev, res->sets, sizeof(*res->desc),3235 res->desc = devm_kcalloc(dev, res->sets, sizeof(*res->desc),
3294 GFP_KERNEL);3236 GFP_KERNEL);
3295 if (!res->desc)3237 if (!res->desc)
3296 return ERR_PTR(-ENOMEM);3238 return ERR_PTR(-ENOMEM);
3297 3239
3298 for (i = 0; i < res->sets; i++) {3240 for (i = 0; i < res->sets; i++) {
3299 ret = of_property_read_u32_index(dev_of_node(dev), of_prop, i,
3300 &resource_subtype);
3301 if (ret)
3302 return ERR_PTR(-EINVAL);
3303
3304 ret = handle->ops.rm_core_ops.get_range(handle, dev_id,3241 ret = handle->ops.rm_core_ops.get_range(handle, dev_id,
3305 resource_subtype,3242 sub_types[i],
3306 &res->desc[i].start,3243 &res->desc[i].start,
3307 &res->desc[i].num);3244 &res->desc[i].num);
3308 if (ret) {3245 if (ret) {
3309 dev_dbg(dev, "dev = %d subtype %d not allocated for this host\n",3246 dev_dbg(dev, "dev = %d subtype %d not allocated for this host\n",
3310 dev_id, resource_subtype);3247 dev_id, sub_types[i]);
3311 res->desc[i].start = 0;3248 res->desc[i].start = 0;
3312 res->desc[i].num = 0;3249 res->desc[i].num = 0;
3313 continue;3250 continue;
3314 }3251 }
3315 3252
3316 dev_dbg(dev, "dev = %d, subtype = %d, start = %d, num = %d\n",3253 dev_dbg(dev, "dev = %d, subtype = %d, start = %d, num = %d\n",
3317 dev_id, resource_subtype, res->desc[i].start,3254 dev_id, sub_types[i], res->desc[i].start,
3318 res->desc[i].num);3255 res->desc[i].num);
3319 3256
3320 valid_set = true;3257 valid_set = true;
@@ -3332,6 +3269,62 @@ devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle, · 11 unmodified lines
3332 return ERR_PTR(-EINVAL);3269 return ERR_PTR(-EINVAL);
3333}3270}
3334 3271
3272/**
3273 * devm_ti_sci_get_of_resource() - Get a TISCI resource assigned to a device
3274 * @handle: TISCI handle
3275 * @dev: Device pointer to which the resource is assigned
3276 * @dev_id: TISCI device id to which the resource is assigned
3277 * @of_prop: property name by which the resource are represented
3278 *
3279 * Return: Pointer to ti_sci_resource if all went well else appropriate
3280 * error pointer.
3281 */
3282struct ti_sci_resource *
3283devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
3284 struct device *dev, u32 dev_id, char *of_prop)
3285{
3286 struct ti_sci_resource *res;
3287 u32 *sub_types;
3288 int sets;
3289
3290 sets = of_property_count_elems_of_size(dev_of_node(dev), of_prop,
3291 sizeof(u32));
3292 if (sets < 0) {
3293 dev_err(dev, "%s resource type ids not available\n", of_prop);
3294 return ERR_PTR(sets);
3295 }
3296
3297 sub_types = kcalloc(sets, sizeof(*sub_types), GFP_KERNEL);
3298 if (!sub_types)
3299 return ERR_PTR(-ENOMEM);
3300
3301 of_property_read_u32_array(dev_of_node(dev), of_prop, sub_types, sets);
3302 res = devm_ti_sci_get_resource_sets(handle, dev, dev_id, sub_types,
3303 sets);
3304
3305 kfree(sub_types);
3306 return res;
3307}
3308EXPORT_SYMBOL_GPL(devm_ti_sci_get_of_resource);
3309
3310/**
3311 * devm_ti_sci_get_resource() - Get a resource range assigned to the device
3312 * @handle: TISCI handle
3313 * @dev: Device pointer to which the resource is assigned
3314 * @dev_id: TISCI device id to which the resource is assigned
3315 * @suub_type: TISCI resource subytpe representing the resource.
3316 *
3317 * Return: Pointer to ti_sci_resource if all went well else appropriate
3318 * error pointer.
3319 */
3320struct ti_sci_resource *
3321devm_ti_sci_get_resource(const struct ti_sci_handle *handle, struct device *dev,
3322 u32 dev_id, u32 sub_type)
3323{
3324 return devm_ti_sci_get_resource_sets(handle, dev, dev_id, &sub_type, 1);
3325}
3326EXPORT_SYMBOL_GPL(devm_ti_sci_get_resource);
3327
3335static int tisci_reboot_handler(struct notifier_block *nb, unsigned long mode,3328static int tisci_reboot_handler(struct notifier_block *nb, unsigned long mode,
3336 void *cmd)3329 void *cmd)
3337{3330{
@@ -3352,17 +3345,6 @@ static const struct ti_sci_desc ti_sci_pmmc_k2g_desc = { · 14 unmodified lines
3352 /* Limited by MBOX_TX_QUEUE_LEN. K2G can handle upto 128 messages! */3345 /* Limited by MBOX_TX_QUEUE_LEN. K2G can handle upto 128 messages! */
3353 .max_msgs = 20,3346 .max_msgs = 20,
3354 .max_msg_size = 64,3347 .max_msg_size = 64,
3355 .rm_type_map = NULL,
3356};
3357
3358static struct ti_sci_rm_type_map ti_sci_am654_rm_type_map[] = {
3359 {.dev_id = 56, .type = 0x00b}, /* GIC_IRQ */
3360 {.dev_id = 179, .type = 0x000}, /* MAIN_NAV_UDMASS_IA0 */
3361 {.dev_id = 187, .type = 0x009}, /* MAIN_NAV_RA */
3362 {.dev_id = 188, .type = 0x006}, /* MAIN_NAV_UDMAP */
3363 {.dev_id = 194, .type = 0x007}, /* MCU_NAV_UDMAP */
3364 {.dev_id = 195, .type = 0x00a}, /* MCU_NAV_RA */
3365 {.dev_id = 0, .type = 0x000}, /* end of table */
3366};3348};
3367 3349
3368/* Description for AM654 */3350/* Description for AM654 */
@@ -3373,7 +3355,6 @@ static const struct ti_sci_desc ti_sci_pmmc_am654_desc = { · 4 unmodified lines
3373 /* Limited by MBOX_TX_QUEUE_LEN. K2G can handle upto 128 messages! */3355 /* Limited by MBOX_TX_QUEUE_LEN. K2G can handle upto 128 messages! */
3374 .max_msgs = 20,3356 .max_msgs = 20,
3375 .max_msg_size = 60,3357 .max_msg_size = 60,
3376 .rm_type_map = ti_sci_am654_rm_type_map,
3377};3358};
3378 3359
3379static const struct of_device_id ti_sci_of_match[] = {3360static const struct of_device_id ti_sci_of_match[] = {
drivers/gpio/gpio-aspeed-sgpio.c+3−3
@@ -303,16 +303,16 @@ static int aspeed_sgpio_set_type(struct irq_data *d, unsigned int type) · 302 unmodified lines
303 switch (type & IRQ_TYPE_SENSE_MASK) {303 switch (type & IRQ_TYPE_SENSE_MASK) {
304 case IRQ_TYPE_EDGE_BOTH:304 case IRQ_TYPE_EDGE_BOTH:
305 type2 |= bit;305 type2 |= bit;
306 /* fall through */306 fallthrough;
307 case IRQ_TYPE_EDGE_RISING:307 case IRQ_TYPE_EDGE_RISING:
308 type0 |= bit;308 type0 |= bit;
309 /* fall through */309 fallthrough;
310 case IRQ_TYPE_EDGE_FALLING:310 case IRQ_TYPE_EDGE_FALLING:
311 handler = handle_edge_irq;311 handler = handle_edge_irq;
312 break;312 break;
313 case IRQ_TYPE_LEVEL_HIGH:313 case IRQ_TYPE_LEVEL_HIGH:
314 type0 |= bit;314 type0 |= bit;
315 /* fall through */315 fallthrough;
316 case IRQ_TYPE_LEVEL_LOW:316 case IRQ_TYPE_LEVEL_LOW:
317 type1 |= bit;317 type1 |= bit;
318 handler = handle_level_irq;318 handler = handle_level_irq;
drivers/gpio/gpio-aspeed.c+3−3
@@ -611,16 +611,16 @@ static int aspeed_gpio_set_type(struct irq_data *d, unsigned int type) · 610 unmodified lines
611 switch (type & IRQ_TYPE_SENSE_MASK) {611 switch (type & IRQ_TYPE_SENSE_MASK) {
612 case IRQ_TYPE_EDGE_BOTH:612 case IRQ_TYPE_EDGE_BOTH:
613 type2 |= bit;613 type2 |= bit;
614 /* fall through */614 fallthrough;
615 case IRQ_TYPE_EDGE_RISING:615 case IRQ_TYPE_EDGE_RISING:
616 type0 |= bit;616 type0 |= bit;
617 /* fall through */617 fallthrough;
618 case IRQ_TYPE_EDGE_FALLING:618 case IRQ_TYPE_EDGE_FALLING:
619 handler = handle_edge_irq;619 handler = handle_edge_irq;
620 break;620 break;
621 case IRQ_TYPE_LEVEL_HIGH:621 case IRQ_TYPE_LEVEL_HIGH:
622 type0 |= bit;622 type0 |= bit;
623 /* fall through */623 fallthrough;
624 case IRQ_TYPE_LEVEL_LOW:624 case IRQ_TYPE_LEVEL_LOW:
625 type1 |= bit;625 type1 |= bit;
626 handler = handle_level_irq;626 handler = handle_level_irq;
drivers/gpio/gpio-ath79.c+1−1
@@ -129,7 +129,7 @@ static int ath79_gpio_irq_set_type(struct irq_data *data, · 128 unmodified lines
129 129
130 case IRQ_TYPE_LEVEL_HIGH:130 case IRQ_TYPE_LEVEL_HIGH:
131 polarity |= mask;131 polarity |= mask;
132 /* fall through */132 fallthrough;
133 case IRQ_TYPE_LEVEL_LOW:133 case IRQ_TYPE_LEVEL_LOW:
134 type |= mask;134 type |= mask;
135 break;135 break;
drivers/gpio/gpio-eic-sprd.c+1−3
@@ -617,14 +617,12 @@ static int sprd_eic_probe(struct platform_device *pdev) · 616 unmodified lines
617 sprd_eic->chip.free = sprd_eic_free;617 sprd_eic->chip.free = sprd_eic_free;
618 sprd_eic->chip.set_config = sprd_eic_set_config;618 sprd_eic->chip.set_config = sprd_eic_set_config;
619 sprd_eic->chip.set = sprd_eic_set;619 sprd_eic->chip.set = sprd_eic_set;
620 /* fall-through */620 fallthrough;
621 case SPRD_EIC_ASYNC:621 case SPRD_EIC_ASYNC:
622 /* fall-through */
623 case SPRD_EIC_SYNC:622 case SPRD_EIC_SYNC:
624 sprd_eic->chip.get = sprd_eic_get;623 sprd_eic->chip.get = sprd_eic_get;
625 break;624 break;
626 case SPRD_EIC_LATCH:625 case SPRD_EIC_LATCH:
627 /* fall-through */
628 default:626 default:
629 break;627 break;
630 }628 }
drivers/gpio/gpio-stmpe.c+2−2
@@ -308,7 +308,7 @@ static void stmpe_dbg_show_one(struct seq_file *s, · 307 unmodified lines
308 if (ret < 0)308 if (ret < 0)
309 return;309 return;
310 edge_det = !!(ret & mask);310 edge_det = !!(ret & mask);
311 /* fall through */311 fallthrough;
312 case STMPE1801:312 case STMPE1801:
313 rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB + bank];313 rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB + bank];
314 fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB + bank];314 fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB + bank];
@@ -321,7 +321,7 @@ static void stmpe_dbg_show_one(struct seq_file *s, · 6 unmodified lines
321 if (ret < 0)321 if (ret < 0)
322 return;322 return;
323 fall = !!(ret & mask);323 fall = !!(ret & mask);
324 /* fall through */324 fallthrough;
325 case STMPE801:325 case STMPE801:
326 case STMPE1600:326 case STMPE1600:
327 irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB + bank];327 irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB + bank];
drivers/gpio/gpiolib-acpi.c+1−1
@@ -1264,7 +1264,7 @@ static int acpi_gpio_package_count(const union acpi_object *obj) · 1263 unmodified lines
1264 switch (element->type) {1264 switch (element->type) {
1265 case ACPI_TYPE_LOCAL_REFERENCE:1265 case ACPI_TYPE_LOCAL_REFERENCE:
1266 element += 3;1266 element += 3;
1267 /* Fallthrough */1267 fallthrough;
1268 case ACPI_TYPE_INTEGER:1268 case ACPI_TYPE_INTEGER:
1269 element++;1269 element++;
1270 count++;1270 count++;
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c+1−1
@@ -152,7 +152,7 @@ static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev, · 151 unmodified lines
152 dev_warn(adev->dev,152 dev_warn(adev->dev,
153 "Invalid sdma engine id (%d), using engine id 0\n",153 "Invalid sdma engine id (%d), using engine id 0\n",
154 engine_id);154 engine_id);
155 /* fall through */155 fallthrough;
156 case 0:156 case 0:
157 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,157 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
158 mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;158 mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c+22−9
@@ -195,19 +195,32 @@ static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev, · 194 unmodified lines
195 unsigned int engine_id,195 unsigned int engine_id,
196 unsigned int queue_id)196 unsigned int queue_id)
197{197{
198 uint32_t sdma_engine_reg_base[2] = {198 uint32_t sdma_engine_reg_base = 0;
199 SOC15_REG_OFFSET(SDMA0, 0,199 uint32_t sdma_rlc_reg_offset;
200 mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL,200
201 SOC15_REG_OFFSET(SDMA1, 0,201 switch (engine_id) {
202 mmSDMA1_RLC0_RB_CNTL) - mmSDMA1_RLC0_RB_CNTL202 default:
203 };203 dev_warn(adev->dev,
204 uint32_t retval = sdma_engine_reg_base[engine_id]204 "Invalid sdma engine id (%d), using engine id 0\n",
205 engine_id);
206 fallthrough;
207 case 0:
208 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
209 mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
210 break;
211 case 1:
212 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA1, 0,
213 mmSDMA1_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
214 break;
215 }
216
217 sdma_rlc_reg_offset = sdma_engine_reg_base
205 + queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL);218 + queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL);
206 219
207 pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id,220 pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id,
208 queue_id, retval);221 queue_id, sdma_rlc_reg_offset);
209 222
210 return retval;223 return sdma_rlc_reg_offset;
211}224}
212 225
213static inline struct v9_mqd *get_mqd(void *mqd)226static inline struct v9_mqd *get_mqd(void *mqd)
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c+5−0
@@ -179,6 +179,7 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) · 178 unmodified lines
179 case CHIP_VEGA20:179 case CHIP_VEGA20:
180 case CHIP_ARCTURUS:180 case CHIP_ARCTURUS:
181 case CHIP_SIENNA_CICHLID:181 case CHIP_SIENNA_CICHLID:
182 case CHIP_NAVY_FLOUNDER:
182 /* enable runpm if runpm=1 */183 /* enable runpm if runpm=1 */
183 if (amdgpu_runtime_pm > 0)184 if (amdgpu_runtime_pm > 0)
184 adev->runpm = true;185 adev->runpm = true;
@@ -678,8 +679,12 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file · 493 unmodified lines
678 * in the bitfields */679 * in the bitfields */
679 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)680 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
680 se_num = 0xffffffff;681 se_num = 0xffffffff;
682 else if (se_num >= AMDGPU_GFX_MAX_SE)
683 return -EINVAL;
681 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)684 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
682 sh_num = 0xffffffff;685 sh_num = 0xffffffff;
686 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE)
687 return -EINVAL;
683 688
684 if (info->read_mmr_reg.count > 128)689 if (info->read_mmr_reg.count > 128)
685 return -EINVAL;690 return -EINVAL;
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c+1−2
@@ -522,8 +522,7 @@ static int psp_asd_load(struct psp_context *psp) · 521 unmodified lines
522 * add workaround to bypass it for sriov now.522 * add workaround to bypass it for sriov now.
523 * TODO: add version check to make it common523 * TODO: add version check to make it common
524 */524 */
525 if (amdgpu_sriov_vf(psp->adev) ||525 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_fw)
526 (psp->adev->asic_type == CHIP_NAVY_FLOUNDER))
527 return 0;526 return 0;
528 527
529 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);528 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c+0−2
@@ -1243,7 +1243,6 @@ void amdgpu_ras_debugfs_remove(struct amdgpu_device *adev, · 1242 unmodified lines
1243 if (!obj || !obj->ent)1243 if (!obj || !obj->ent)
1244 return;1244 return;
1245 1245
1246 debugfs_remove(obj->ent);
1247 obj->ent = NULL;1246 obj->ent = NULL;
1248 put_obj(obj);1247 put_obj(obj);
1249}1248}
@@ -1257,7 +1256,6 @@ static void amdgpu_ras_debugfs_remove_all(struct amdgpu_device *adev) · 7 unmodified lines
1257 amdgpu_ras_debugfs_remove(adev, &obj->head);1256 amdgpu_ras_debugfs_remove(adev, &obj->head);
1258 }1257 }
1259 1258
1260 debugfs_remove_recursive(con->dir);
1261 con->dir = NULL;1259 con->dir = NULL;
1262}1260}
1263/* debugfs end */1261/* debugfs end */
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c+1−1
@@ -462,7 +462,7 @@ int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev, · 461 unmodified lines
462 unsigned int pages;462 unsigned int pages;
463 int i, r;463 int i, r;
464 464
465 *sgt = kmalloc(sizeof(*sg), GFP_KERNEL);465 *sgt = kmalloc(sizeof(**sgt), GFP_KERNEL);
466 if (!*sgt)466 if (!*sgt)
467 return -ENOMEM;467 return -ENOMEM;
468 468
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c+2−4
@@ -7263,10 +7263,8 @@ static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade · 7262 unmodified lines
7263 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);7263 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7264 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |7264 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7265 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |7265 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7266 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);7266 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7267 7267 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7268 /* only for Vega10 & Raven1 */
7269 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
7270 7268
7271 if (def != data)7269 if (def != data)
7272 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);7270 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c+1−1
@@ -3250,7 +3250,7 @@ static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev) · 3249 unmodified lines
3250 dev_warn(adev->dev,3250 dev_warn(adev->dev,
3251 "Unknown chip type (%d) in function gfx_v8_0_tiling_mode_table_init() falling through to CHIP_CARRIZO\n",3251 "Unknown chip type (%d) in function gfx_v8_0_tiling_mode_table_init() falling through to CHIP_CARRIZO\n",
3252 adev->asic_type);3252 adev->asic_type);
3253 /* fall through */3253 fallthrough;
3254 3254
3255 case CHIP_CARRIZO:3255 case CHIP_CARRIZO:
3256 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |3256 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c+1−0
@@ -691,6 +691,7 @@ static const struct soc15_reg_golden golden_settings_gc_9_4_1_arct[] = · 690 unmodified lines
691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_5_ARCT, 0x3ff, 0x135),691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_5_ARCT, 0x3ff, 0x135),
692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xffffffff, 0x011A0000),692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xffffffff, 0x011A0000),
693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_FIFO_SIZES, 0xffffffff, 0x00000f00),693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_FIFO_SIZES, 0xffffffff, 0x00000f00),
694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_UTCL1_CNTL1, 0x30000000, 0x30000000)
694};695};
695 696
696static const struct soc15_reg_rlcg rlcg_access_gc_9_0[] = {697static const struct soc15_reg_rlcg rlcg_access_gc_9_0[] = {
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c+19−0
@@ -135,6 +135,12 @@ static void gfxhub_v2_1_init_cache_regs(struct amdgpu_device *adev) · 134 unmodified lines
135{135{
136 uint32_t tmp;136 uint32_t tmp;
137 137
138 /* These registers are not accessible to VF-SRIOV.
139 * The PF will program them instead.
140 */
141 if (amdgpu_sriov_vf(adev))
142 return;
143
138 /* Setup L2 cache */144 /* Setup L2 cache */
139 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);145 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);
140 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);146 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);
@@ -190,6 +196,12 @@ static void gfxhub_v2_1_enable_system_domain(struct amdgpu_device *adev) · 49 unmodified lines
190 196
191static void gfxhub_v2_1_disable_identity_aperture(struct amdgpu_device *adev)197static void gfxhub_v2_1_disable_identity_aperture(struct amdgpu_device *adev)
192{198{
199 /* These registers are not accessible to VF-SRIOV.
200 * The PF will program them instead.
201 */
202 if (amdgpu_sriov_vf(adev))
203 return;
204
193 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,205 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
194 0xFFFFFFFF);206 0xFFFFFFFF);
195 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,207 WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
@@ -326,6 +338,13 @@ void gfxhub_v2_1_set_fault_enable_default(struct amdgpu_device *adev, · 130 unmodified lines
326 bool value)338 bool value)
327{339{
328 u32 tmp;340 u32 tmp;
341
342 /* These registers are not accessible to VF-SRIOV.
343 * The PF will program them instead.
344 */
345 if (amdgpu_sriov_vf(adev))
346 return;
347
329 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);348 tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);
330 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,349 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
331 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);350 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c+1−1
@@ -1297,7 +1297,7 @@ static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) · 1296 unmodified lines
1297 case CHIP_VEGA10:1297 case CHIP_VEGA10:
1298 if (amdgpu_sriov_vf(adev))1298 if (amdgpu_sriov_vf(adev))
1299 break;1299 break;
1300 /* fall through */1300 fallthrough;
1301 case CHIP_VEGA20:1301 case CHIP_VEGA20:
1302 soc15_program_register_sequence(adev,1302 soc15_program_register_sequence(adev,
1303 golden_settings_mmhub_1_0_0,1303 golden_settings_mmhub_1_0_0,
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c+19−0
@@ -134,6 +134,12 @@ static void mmhub_v2_0_init_cache_regs(struct amdgpu_device *adev) · 133 unmodified lines
134{134{
135 uint32_t tmp;135 uint32_t tmp;
136 136
137 /* These registers are not accessible to VF-SRIOV.
138 * The PF will program them instead.
139 */
140 if (amdgpu_sriov_vf(adev))
141 return;
142
137 /* Setup L2 cache */143 /* Setup L2 cache */
138 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);144 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);
139 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);145 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);
@@ -189,6 +195,12 @@ static void mmhub_v2_0_enable_system_domain(struct amdgpu_device *adev) · 49 unmodified lines
189 195
190static void mmhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev)196static void mmhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev)
191{197{
198 /* These registers are not accessible to VF-SRIOV.
199 * The PF will program them instead.
200 */
201 if (amdgpu_sriov_vf(adev))
202 return;
203
192 WREG32_SOC15(MMHUB, 0,204 WREG32_SOC15(MMHUB, 0,
193 mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,205 mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
194 0xFFFFFFFF);206 0xFFFFFFFF);
@@ -318,6 +330,13 @@ void mmhub_v2_0_gart_disable(struct amdgpu_device *adev) · 123 unmodified lines
318void mmhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)330void mmhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
319{331{
320 u32 tmp;332 u32 tmp;
333
334 /* These registers are not accessible to VF-SRIOV.
335 * The PF will program them instead.
336 */
337 if (amdgpu_sriov_vf(adev))
338 return;
339
321 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);340 tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);
322 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,341 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
323 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);342 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
drivers/gpu/drm/amd/amdgpu/nv.c+1−0
@@ -364,6 +364,7 @@ nv_asic_reset_method(struct amdgpu_device *adev) · 363 unmodified lines
364 364
365 switch (adev->asic_type) {365 switch (adev->asic_type) {
366 case CHIP_SIENNA_CICHLID:366 case CHIP_SIENNA_CICHLID:
367 case CHIP_NAVY_FLOUNDER:
367 return AMD_RESET_METHOD_MODE1;368 return AMD_RESET_METHOD_MODE1;
368 default:369 default:
369 if (smu_baco_is_support(smu))370 if (smu_baco_is_support(smu))
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c+1−2
@@ -179,12 +179,11 @@ static int psp_v11_0_init_microcode(struct psp_context *psp) · 178 unmodified lines
179 }179 }
180 break;180 break;
181 case CHIP_SIENNA_CICHLID:181 case CHIP_SIENNA_CICHLID:
182 case CHIP_NAVY_FLOUNDER:
182 err = psp_init_ta_microcode(&adev->psp, chip_name);183 err = psp_init_ta_microcode(&adev->psp, chip_name);
183 if (err)184 if (err)
184 return err;185 return err;
185 break;186 break;
186 case CHIP_NAVY_FLOUNDER:
187 break;
188 default:187 default:
189 BUG();188 BUG();
190 }189 }
drivers/gpu/drm/amd/amdgpu/si_dpm.c+1−1
@@ -6196,7 +6196,7 @@ static void si_request_link_speed_change_before_state_change(struct amdgpu_devic · 6195 unmodified lines
6196 si_pi->force_pcie_gen = AMDGPU_PCIE_GEN2;6196 si_pi->force_pcie_gen = AMDGPU_PCIE_GEN2;
6197 if (current_link_speed == AMDGPU_PCIE_GEN2)6197 if (current_link_speed == AMDGPU_PCIE_GEN2)
6198 break;6198 break;
6199 /* fall through */6199 fallthrough;
6200 case AMDGPU_PCIE_GEN2:6200 case AMDGPU_PCIE_GEN2:
6201 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)6201 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
6202 break;6202 break;
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c+51−43
@@ -2196,6 +2196,7 @@ void amdgpu_dm_update_connector_after_detect( · 2195 unmodified lines
2196 2196
2197 drm_connector_update_edid_property(connector,2197 drm_connector_update_edid_property(connector,
2198 aconnector->edid);2198 aconnector->edid);
2199 drm_add_edid_modes(connector, aconnector->edid);
2199 2200
2200 if (aconnector->dc_link->aux_mode)2201 if (aconnector->dc_link->aux_mode)
2201 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,2202 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
@@ -2833,12 +2834,18 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) · 631 unmodified lines
2833 &dm_atomic_state_funcs);2834 &dm_atomic_state_funcs);
2834 2835
2835 r = amdgpu_display_modeset_create_props(adev);2836 r = amdgpu_display_modeset_create_props(adev);
2836 if (r)2837 if (r) {
2838 dc_release_state(state->context);
2839 kfree(state);
2837 return r;2840 return r;
2841 }
2838 2842
2839 r = amdgpu_dm_audio_init(adev);2843 r = amdgpu_dm_audio_init(adev);
2840 if (r)2844 if (r) {
2845 dc_release_state(state->context);
2846 kfree(state);
2841 return r;2847 return r;
2848 }
2842 2849
2843 return 0;2850 return 0;
2844}2851}
@@ -2855,6 +2862,8 @@ static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm) · 10 unmodified lines
2855#if defined(CONFIG_ACPI)2862#if defined(CONFIG_ACPI)
2856 struct amdgpu_dm_backlight_caps caps;2863 struct amdgpu_dm_backlight_caps caps;
2857 2864
2865 memset(&caps, 0, sizeof(caps));
2866
2858 if (dm->backlight_caps.caps_valid)2867 if (dm->backlight_caps.caps_valid)
2859 return;2868 return;
2860 2869
@@ -2893,51 +2902,50 @@ static int set_backlight_via_aux(struct dc_link *link, uint32_t brightness) · 32 unmodified lines
2893 return rc ? 0 : 1;2902 return rc ? 0 : 1;
2894}2903}
2895 2904
2896static u32 convert_brightness(const struct amdgpu_dm_backlight_caps *caps,2905static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,
2897 const uint32_t user_brightness)2906 unsigned *min, unsigned *max)
2898{2907{
2899 u32 min, max, conversion_pace;
2900 u32 brightness = user_brightness;
2901
2902 if (!caps)2908 if (!caps)
2903 goto out;2909 return 0;
2904 2910
2905 if (!caps->aux_support) {2911 if (caps->aux_support) {
2906 max = caps->max_input_signal;2912 // Firmware limits are in nits, DC API wants millinits.
2907 min = caps->min_input_signal;2913 *max = 1000 * caps->aux_max_input_signal;
2908 /*2914 *min = 1000 * caps->aux_min_input_signal;
2909 * The brightness input is in the range 0-255
2910 * It needs to be rescaled to be between the
2911 * requested min and max input signal
2912 * It also needs to be scaled up by 0x101 to
2913 * match the DC interface which has a range of
2914 * 0 to 0xffff
2915 */
2916 conversion_pace = 0x101;
2917 brightness =
2918 user_brightness
2919 * conversion_pace
2920 * (max - min)
2921 / AMDGPU_MAX_BL_LEVEL
2922 + min * conversion_pace;
2923 } else {2915 } else {
2924 /* TODO2916 // Firmware limits are 8-bit, PWM control is 16-bit.
2925 * We are doing a linear interpolation here, which is OK but2917 *max = 0x101 * caps->max_input_signal;
2926 * does not provide the optimal result. We probably want2918 *min = 0x101 * caps->min_input_signal;
2927 * something close to the Perceptual Quantizer (PQ) curve.
2928 */
2929 max = caps->aux_max_input_signal;
2930 min = caps->aux_min_input_signal;
2931
2932 brightness = (AMDGPU_MAX_BL_LEVEL - user_brightness) * min
2933 + user_brightness * max;
2934 // Multiple the value by 1000 since we use millinits
2935 brightness *= 1000;
2936 brightness = DIV_ROUND_CLOSEST(brightness, AMDGPU_MAX_BL_LEVEL);
2937 }2919 }
2920 return 1;
2921}
2938 2922
2939out:2923static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,
2940 return brightness;2924 uint32_t brightness)
2925{
2926 unsigned min, max;
2927
2928 if (!get_brightness_range(caps, &min, &max))
2929 return brightness;
2930
2931 // Rescale 0..255 to min..max
2932 return min + DIV_ROUND_CLOSEST((max - min) * brightness,
2933 AMDGPU_MAX_BL_LEVEL);
2934}
2935
2936static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,
2937 uint32_t brightness)
2938{
2939 unsigned min, max;
2940
2941 if (!get_brightness_range(caps, &min, &max))
2942 return brightness;
2943
2944 if (brightness < min)
2945 return 0;
2946 // Rescale min..max to 0..255
2947 return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min),
2948 max - min);
2941}2949}
2942 2950
2943static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)2951static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
@@ -2953,7 +2961,7 @@ static int amdgpu_dm_backlight_update_status(struct backlight_device *bd) · 9 unmodified lines
2953 2961
2954 link = (struct dc_link *)dm->backlight_link;2962 link = (struct dc_link *)dm->backlight_link;
2955 2963
2956 brightness = convert_brightness(&caps, bd->props.brightness);2964 brightness = convert_brightness_from_user(&caps, bd->props.brightness);
2957 // Change brightness based on AUX property2965 // Change brightness based on AUX property
2958 if (caps.aux_support)2966 if (caps.aux_support)
2959 return set_backlight_via_aux(link, brightness);2967 return set_backlight_via_aux(link, brightness);
@@ -2970,7 +2978,7 @@ static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd) · 10 unmodified lines
2970 2978
2971 if (ret == DC_ERROR_UNEXPECTED)2979 if (ret == DC_ERROR_UNEXPECTED)
2972 return bd->props.brightness;2980 return bd->props.brightness;
2973 return ret;2981 return convert_brightness_to_user(&dm->backlight_caps, ret);
2974}2982}
2975 2983
2976static const struct backlight_ops amdgpu_dm_backlight_ops = {2984static const struct backlight_ops amdgpu_dm_backlight_ops = {
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c+1−1
@@ -67,7 +67,7 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux, · 66 unmodified lines
67 result = dc_link_aux_transfer_raw(TO_DM_AUX(aux)->ddc_service, &payload,67 result = dc_link_aux_transfer_raw(TO_DM_AUX(aux)->ddc_service, &payload,
68 &operation_result);68 &operation_result);
69 69
70 if (payload.write)70 if (payload.write && result >= 0)
71 result = msg->size;71 result = msg->size;
72 72
73 if (result < 0)73 if (result < 0)
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c+15−1
@@ -1108,6 +1108,18 @@ static enum bp_result bios_parser_enable_disp_power_gating( · 1107 unmodified lines
1108 action);1108 action);
1109}1109}
1110 1110
1111static enum bp_result bios_parser_enable_lvtma_control(
1112 struct dc_bios *dcb,
1113 uint8_t uc_pwr_on)
1114{
1115 struct bios_parser *bp = BP_FROM_DCB(dcb);
1116
1117 if (!bp->cmd_tbl.enable_lvtma_control)
1118 return BP_RESULT_FAILURE;
1119
1120 return bp->cmd_tbl.enable_lvtma_control(bp, uc_pwr_on);
1121}
1122
1111static bool bios_parser_is_accelerated_mode(1123static bool bios_parser_is_accelerated_mode(
1112 struct dc_bios *dcb)1124 struct dc_bios *dcb)
1113{1125{
@@ -2208,7 +2220,9 @@ static const struct dc_vbios_funcs vbios_funcs = { · 1094 unmodified lines
2208 .get_board_layout_info = bios_get_board_layout_info,2220 .get_board_layout_info = bios_get_board_layout_info,
2209 .pack_data_tables = bios_parser_pack_data_tables,2221 .pack_data_tables = bios_parser_pack_data_tables,
2210 2222
2211 .get_atom_dc_golden_table = bios_get_atom_dc_golden_table2223 .get_atom_dc_golden_table = bios_get_atom_dc_golden_table,
2224
2225 .enable_lvtma_control = bios_parser_enable_lvtma_control
2212};2226};
2213 2227
2214static bool bios_parser2_construct(2228static bool bios_parser2_construct(
drivers/gpu/drm/amd/display/dc/bios/command_table2.c+28−0
@@ -904,6 +904,33 @@ static unsigned int get_smu_clock_info_v3_1(struct bios_parser *bp, uint8_t id) · 903 unmodified lines
904 return 0;904 return 0;
905}905}
906 906
907/******************************************************************************
908 ******************************************************************************
909 **
910 ** LVTMA CONTROL
911 **
912 ******************************************************************************
913 *****************************************************************************/
914
915static enum bp_result enable_lvtma_control(
916 struct bios_parser *bp,
917 uint8_t uc_pwr_on);
918
919static void init_enable_lvtma_control(struct bios_parser *bp)
920{
921 /* TODO add switch for table vrsion */
922 bp->cmd_tbl.enable_lvtma_control = enable_lvtma_control;
923
924}
925
926static enum bp_result enable_lvtma_control(
927 struct bios_parser *bp,
928 uint8_t uc_pwr_on)
929{
930 enum bp_result result = BP_RESULT_FAILURE;
931 return result;
932}
933
907void dal_firmware_parser_init_cmd_tbl(struct bios_parser *bp)934void dal_firmware_parser_init_cmd_tbl(struct bios_parser *bp)
908{935{
909 init_dig_encoder_control(bp);936 init_dig_encoder_control(bp);
@@ -919,4 +946,5 @@ void dal_firmware_parser_init_cmd_tbl(struct bios_parser *bp) · 9 unmodified lines
919 init_set_dce_clock(bp);946 init_set_dce_clock(bp);
920 init_get_smu_clock_info(bp);947 init_get_smu_clock_info(bp);
921 948
949 init_enable_lvtma_control(bp);
922}950}
drivers/gpu/drm/amd/display/dc/bios/command_table2.h+2−1
@@ -94,7 +94,8 @@ struct cmd_tbl { · 93 unmodified lines
94 struct bp_set_dce_clock_parameters *bp_params);94 struct bp_set_dce_clock_parameters *bp_params);
95 unsigned int (*get_smu_clock_info)(95 unsigned int (*get_smu_clock_info)(
96 struct bios_parser *bp, uint8_t id);96 struct bios_parser *bp, uint8_t id);
97 97 enum bp_result (*enable_lvtma_control)(struct bios_parser *bp,
98 uint8_t uc_pwr_on);
98};99};
99 100
100void dal_firmware_parser_init_cmd_tbl(struct bios_parser *bp);101void dal_firmware_parser_init_cmd_tbl(struct bios_parser *bp);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c+10−0
@@ -94,6 +94,15 @@ int rn_get_active_display_cnt_wa( · 93 unmodified lines
94 return display_count;94 return display_count;
95}95}
96 96
97void rn_set_low_power_state(struct clk_mgr *clk_mgr_base)
98{
99 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
100
101 rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_LOW_POWER);
102 /* update power state */
103 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
104}
105
97void rn_update_clocks(struct clk_mgr *clk_mgr_base,106void rn_update_clocks(struct clk_mgr *clk_mgr_base,
98 struct dc_state *context,107 struct dc_state *context,
99 bool safe_to_lower)108 bool safe_to_lower)
@@ -516,6 +525,7 @@ static struct clk_mgr_funcs dcn21_funcs = { · 416 unmodified lines
516 .init_clocks = rn_init_clocks,525 .init_clocks = rn_init_clocks,
517 .enable_pme_wa = rn_enable_pme_wa,526 .enable_pme_wa = rn_enable_pme_wa,
518 .are_clock_states_equal = rn_are_clock_states_equal,527 .are_clock_states_equal = rn_are_clock_states_equal,
528 .set_low_power_state = rn_set_low_power_state,
519 .notify_wm_ranges = rn_notify_wm_ranges,529 .notify_wm_ranges = rn_notify_wm_ranges,
520 .notify_link_rate_change = rn_notify_link_rate_change,530 .notify_link_rate_change = rn_notify_link_rate_change,
521};531};
drivers/gpu/drm/amd/display/dc/core/dc_link.c+1−1
@@ -763,6 +763,7 @@ static bool detect_dp(struct dc_link *link, · 762 unmodified lines
763 sink_caps->signal = dp_passive_dongle_detection(link->ddc,763 sink_caps->signal = dp_passive_dongle_detection(link->ddc,
764 sink_caps,764 sink_caps,
765 audio_support);765 audio_support);
766 link->dpcd_caps.dongle_type = sink_caps->dongle_type;
766 }767 }
767 768
768 return true;769 return true;
@@ -3289,7 +3290,6 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx) · 2520 unmodified lines
3289#if defined(CONFIG_DRM_AMD_DC_HDCP)3290#if defined(CONFIG_DRM_AMD_DC_HDCP)
3290 update_psp_stream_config(pipe_ctx, true);3291 update_psp_stream_config(pipe_ctx, true);
3291#endif3292#endif
3292
3293 dc->hwss.blank_stream(pipe_ctx);3293 dc->hwss.blank_stream(pipe_ctx);
3294 3294
3295 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)3295 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c+4−4
@@ -4409,9 +4409,9 @@ bool dc_link_get_backlight_level_nits(struct dc_link *link, · 4408 unmodified lines
4409 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))4409 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4410 return false;4410 return false;
4411 4411
4412 if (!core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_CURRENT_PEAK,4412 if (core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_CURRENT_PEAK,
4413 dpcd_backlight_get.raw,4413 dpcd_backlight_get.raw,
4414 sizeof(union dpcd_source_backlight_get)))4414 sizeof(union dpcd_source_backlight_get)) != DC_OK)
4415 return false;4415 return false;
4416 4416
4417 *backlight_millinits_avg =4417 *backlight_millinits_avg =
@@ -4450,9 +4450,9 @@ bool dc_link_read_default_bl_aux(struct dc_link *link, uint32_t *backlight_milli · 32 unmodified lines
4450 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))4450 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4451 return false;4451 return false;
4452 4452
4453 if (!core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,4453 if (core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
4454 (uint8_t *) backlight_millinits,4454 (uint8_t *) backlight_millinits,
4455 sizeof(uint32_t)))4455 sizeof(uint32_t)) != DC_OK)
4456 return false;4456 return false;
4457 4457
4458 return true;4458 return true;
drivers/gpu/drm/amd/display/dc/dc_bios_types.h+4−0
@@ -136,6 +136,10 @@ struct dc_vbios_funcs { · 135 unmodified lines
136 136
137 enum bp_result (*get_atom_dc_golden_table)(137 enum bp_result (*get_atom_dc_golden_table)(
138 struct dc_bios *dcb);138 struct dc_bios *dcb);
139
140 enum bp_result (*enable_lvtma_control)(
141 struct dc_bios *bios,
142 uint8_t uc_pwr_on);
139};143};
140 144
141struct bios_registers {145struct bios_registers {
drivers/gpu/drm/amd/display/dc/dc_stream.h+1−1
@@ -233,7 +233,7 @@ struct dc_stream_state { · 232 unmodified lines
233 union stream_update_flags update_flags;233 union stream_update_flags update_flags;
234};234};
235 235
236#define ABM_LEVEL_IMMEDIATE_DISABLE 0xFFFFFFFF236#define ABM_LEVEL_IMMEDIATE_DISABLE 255
237 237
238struct dc_stream_update {238struct dc_stream_update {
239 struct dc_stream_state *stream;239 struct dc_stream_state *stream;
drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h+1−1
@@ -49,7 +49,7 @@ · 48 unmodified lines
49#define DCN_PANEL_CNTL_REG_LIST()\49#define DCN_PANEL_CNTL_REG_LIST()\
50 DCN_PANEL_CNTL_SR(PWRSEQ_CNTL, LVTMA), \50 DCN_PANEL_CNTL_SR(PWRSEQ_CNTL, LVTMA), \
51 DCN_PANEL_CNTL_SR(PWRSEQ_STATE, LVTMA), \51 DCN_PANEL_CNTL_SR(PWRSEQ_STATE, LVTMA), \
52 DCE_PANEL_CNTL_SR(PWRSEQ_REF_DIV, LVTMA), \52 DCN_PANEL_CNTL_SR(PWRSEQ_REF_DIV, LVTMA), \
53 SR(BL_PWM_CNTL), \53 SR(BL_PWM_CNTL), \
54 SR(BL_PWM_CNTL2), \54 SR(BL_PWM_CNTL2), \
55 SR(BL_PWM_PERIOD_CNTL), \55 SR(BL_PWM_PERIOD_CNTL), \
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c+24−0
@@ -842,6 +842,17 @@ void dce110_edp_power_control( · 841 unmodified lines
842 cntl.coherent = false;842 cntl.coherent = false;
843 cntl.lanes_number = LANE_COUNT_FOUR;843 cntl.lanes_number = LANE_COUNT_FOUR;
844 cntl.hpd_sel = link->link_enc->hpd_source;844 cntl.hpd_sel = link->link_enc->hpd_source;
845
846 if (ctx->dc->ctx->dmub_srv &&
847 ctx->dc->debug.dmub_command_table) {
848 if (cntl.action == TRANSMITTER_CONTROL_POWER_ON)
849 bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
850 LVTMA_CONTROL_POWER_ON);
851 else
852 bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
853 LVTMA_CONTROL_POWER_OFF);
854 }
855
845 bp_result = link_transmitter_control(ctx->dc_bios, &cntl);856 bp_result = link_transmitter_control(ctx->dc_bios, &cntl);
846 857
847 if (!power_up)858 if (!power_up)
@@ -919,8 +930,21 @@ void dce110_edp_backlight_control( · 71 unmodified lines
919 /*edp 1.2*/930 /*edp 1.2*/
920 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON)931 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON)
921 edp_receiver_ready_T7(link);932 edp_receiver_ready_T7(link);
933
934 if (ctx->dc->ctx->dmub_srv &&
935 ctx->dc->debug.dmub_command_table) {
936 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON)
937 ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
938 LVTMA_CONTROL_LCD_BLON);
939 else
940 ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
941 LVTMA_CONTROL_LCD_BLOFF);
942 }
943
922 link_transmitter_control(ctx->dc_bios, &cntl);944 link_transmitter_control(ctx->dc_bios, &cntl);
923 945
946
947
924 if (enable && link->dpcd_sink_ext_caps.bits.oled)948 if (enable && link->dpcd_sink_ext_caps.bits.oled)
925 msleep(OLED_POST_T7_DELAY);949 msleep(OLED_POST_T7_DELAY);
926 950
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c+31−22
@@ -1450,33 +1450,42 @@ void dcn10_init_hw(struct dc *dc) · 1449 unmodified lines
1450void dcn10_power_down_on_boot(struct dc *dc)1450void dcn10_power_down_on_boot(struct dc *dc)
1451{1451{
1452 int i = 0;1452 int i = 0;
1453 struct dc_link *edp_link;
1453 1454
1454 if (dc->config.power_down_display_on_boot) {1455 if (!dc->config.power_down_display_on_boot)
1455 struct dc_link *edp_link = get_edp_link(dc);1456 return;
1456 1457
1457 if (edp_link &&1458 edp_link = get_edp_link(dc);
1458 edp_link->link_enc->funcs->is_dig_enabled &&1459 if (edp_link &&
1459 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&1460 edp_link->link_enc->funcs->is_dig_enabled &&
1460 dc->hwseq->funcs.edp_backlight_control &&1461 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&
1461 dc->hwss.power_down &&1462 dc->hwseq->funcs.edp_backlight_control &&
1462 dc->hwss.edp_power_control) {1463 dc->hwss.power_down &&
1463 dc->hwseq->funcs.edp_backlight_control(edp_link, false);1464 dc->hwss.edp_power_control) {
1464 dc->hwss.power_down(dc);1465 dc->hwseq->funcs.edp_backlight_control(edp_link, false);
1465 dc->hwss.edp_power_control(edp_link, false);1466 dc->hwss.power_down(dc);
1466 } else {1467 dc->hwss.edp_power_control(edp_link, false);
1467 for (i = 0; i < dc->link_count; i++) {1468 } else {
1468 struct dc_link *link = dc->links[i];1469 for (i = 0; i < dc->link_count; i++) {
1469 1470 struct dc_link *link = dc->links[i];
1470 if (link->link_enc->funcs->is_dig_enabled &&
1471 link->link_enc->funcs->is_dig_enabled(link->link_enc) &&
1472 dc->hwss.power_down) {
1473 dc->hwss.power_down(dc);
1474 break;
1475 }
1476 1471
1472 if (link->link_enc->funcs->is_dig_enabled &&
1473 link->link_enc->funcs->is_dig_enabled(link->link_enc) &&
1474 dc->hwss.power_down) {
1475 dc->hwss.power_down(dc);
1476 break;
1477 }1477 }
1478
1478 }1479 }
1479 }1480 }
1481
1482 /*
1483 * Call update_clocks with empty context
1484 * to send DISPLAY_OFF
1485 * Otherwise DISPLAY_OFF may not be asserted
1486 */
1487 if (dc->clk_mgr->funcs->set_low_power_state)
1488 dc->clk_mgr->funcs->set_low_power_state(dc->clk_mgr);
1480}1489}
1481 1490
1482void dcn10_reset_hw_ctx_wrap(1491void dcn10_reset_hw_ctx_wrap(
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c+8−0
@@ -1213,6 +1213,7 @@ static enum dc_status dcn10_validate_global(struct dc *dc, struct dc_state *cont · 1212 unmodified lines
1213 bool video_large = false;1213 bool video_large = false;
1214 bool desktop_large = false;1214 bool desktop_large = false;
1215 bool dcc_disabled = false;1215 bool dcc_disabled = false;
1216 bool mpo_enabled = false;
1216 1217
1217 for (i = 0; i < context->stream_count; i++) {1218 for (i = 0; i < context->stream_count; i++) {
1218 if (context->stream_status[i].plane_count == 0)1219 if (context->stream_status[i].plane_count == 0)
@@ -1221,6 +1222,9 @@ static enum dc_status dcn10_validate_global(struct dc *dc, struct dc_state *cont · 2 unmodified lines
1221 if (context->stream_status[i].plane_count > 2)1222 if (context->stream_status[i].plane_count > 2)
1222 return DC_FAIL_UNSUPPORTED_1;1223 return DC_FAIL_UNSUPPORTED_1;
1223 1224
1225 if (context->stream_status[i].plane_count > 1)
1226 mpo_enabled = true;
1227
1224 for (j = 0; j < context->stream_status[i].plane_count; j++) {1228 for (j = 0; j < context->stream_status[i].plane_count; j++) {
1225 struct dc_plane_state *plane =1229 struct dc_plane_state *plane =
1226 context->stream_status[i].plane_states[j];1230 context->stream_status[i].plane_states[j];
@@ -1244,6 +1248,10 @@ static enum dc_status dcn10_validate_global(struct dc *dc, struct dc_state *cont · 17 unmodified lines
1244 }1248 }
1245 }1249 }
1246 1250
1251 /* Disable MPO in multi-display configurations. */
1252 if (context->stream_count > 1 && mpo_enabled)
1253 return DC_FAIL_UNSUPPORTED_1;
1254
1247 /*1255 /*
1248 * Workaround: On DCN10 there is UMC issue that causes underflow when1256 * Workaround: On DCN10 there is UMC issue that causes underflow when
1249 * playing 4k video on 4k desktop with video downscaled and single channel1257 * playing 4k video on 4k desktop with video downscaled and single channel
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c+8−8
@@ -121,35 +121,35 @@ void enc1_update_generic_info_packet( · 120 unmodified lines
121 switch (packet_index) {121 switch (packet_index) {
122 case 0:122 case 0:
123 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,123 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
124 AFMT_GENERIC0_FRAME_UPDATE, 1);124 AFMT_GENERIC0_IMMEDIATE_UPDATE, 1);
125 break;125 break;
126 case 1:126 case 1:
127 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,127 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
128 AFMT_GENERIC1_FRAME_UPDATE, 1);128 AFMT_GENERIC1_IMMEDIATE_UPDATE, 1);
129 break;129 break;
130 case 2:130 case 2:
131 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,131 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
132 AFMT_GENERIC2_FRAME_UPDATE, 1);132 AFMT_GENERIC2_IMMEDIATE_UPDATE, 1);
133 break;133 break;
134 case 3:134 case 3:
135 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,135 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
136 AFMT_GENERIC3_FRAME_UPDATE, 1);136 AFMT_GENERIC3_IMMEDIATE_UPDATE, 1);
137 break;137 break;
138 case 4:138 case 4:
139 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,139 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
140 AFMT_GENERIC4_FRAME_UPDATE, 1);140 AFMT_GENERIC4_IMMEDIATE_UPDATE, 1);
141 break;141 break;
142 case 5:142 case 5:
143 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,143 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
144 AFMT_GENERIC5_FRAME_UPDATE, 1);144 AFMT_GENERIC5_IMMEDIATE_UPDATE, 1);
145 break;145 break;
146 case 6:146 case 6:
147 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,147 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
148 AFMT_GENERIC6_FRAME_UPDATE, 1);148 AFMT_GENERIC6_IMMEDIATE_UPDATE, 1);
149 break;149 break;
150 case 7:150 case 7:
151 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,151 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
152 AFMT_GENERIC7_FRAME_UPDATE, 1);152 AFMT_GENERIC7_IMMEDIATE_UPDATE, 1);
153 break;153 break;
154 default:154 default:
155 break;155 break;
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h+14−0
@@ -281,7 +281,14 @@ struct dcn10_stream_enc_registers { · 280 unmodified lines
281 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE, mask_sh),\281 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE, mask_sh),\
282 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE, mask_sh),\282 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE, mask_sh),\
283 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE, mask_sh),\283 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE, mask_sh),\
284 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_IMMEDIATE_UPDATE, mask_sh),\
285 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_IMMEDIATE_UPDATE, mask_sh),\
286 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_IMMEDIATE_UPDATE, mask_sh),\
287 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_IMMEDIATE_UPDATE, mask_sh),\
284 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_IMMEDIATE_UPDATE, mask_sh),\288 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_IMMEDIATE_UPDATE, mask_sh),\
289 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_IMMEDIATE_UPDATE, mask_sh),\
290 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_IMMEDIATE_UPDATE, mask_sh),\
291 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_IMMEDIATE_UPDATE, mask_sh),\
285 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE, mask_sh),\292 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE, mask_sh),\
286 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE, mask_sh),\293 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE, mask_sh),\
287 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE, mask_sh),\294 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE, mask_sh),\
@@ -345,7 +352,14 @@ struct dcn10_stream_enc_registers { · 57 unmodified lines
345 type AFMT_GENERIC2_FRAME_UPDATE;\352 type AFMT_GENERIC2_FRAME_UPDATE;\
346 type AFMT_GENERIC3_FRAME_UPDATE;\353 type AFMT_GENERIC3_FRAME_UPDATE;\
347 type AFMT_GENERIC4_FRAME_UPDATE;\354 type AFMT_GENERIC4_FRAME_UPDATE;\
355 type AFMT_GENERIC0_IMMEDIATE_UPDATE;\
356 type AFMT_GENERIC1_IMMEDIATE_UPDATE;\
357 type AFMT_GENERIC2_IMMEDIATE_UPDATE;\
358 type AFMT_GENERIC3_IMMEDIATE_UPDATE;\
348 type AFMT_GENERIC4_IMMEDIATE_UPDATE;\359 type AFMT_GENERIC4_IMMEDIATE_UPDATE;\
360 type AFMT_GENERIC5_IMMEDIATE_UPDATE;\
361 type AFMT_GENERIC6_IMMEDIATE_UPDATE;\
362 type AFMT_GENERIC7_IMMEDIATE_UPDATE;\
349 type AFMT_GENERIC5_FRAME_UPDATE;\363 type AFMT_GENERIC5_FRAME_UPDATE;\
350 type AFMT_GENERIC6_FRAME_UPDATE;\364 type AFMT_GENERIC6_FRAME_UPDATE;\
351 type AFMT_GENERIC7_FRAME_UPDATE;\365 type AFMT_GENERIC7_FRAME_UPDATE;\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c+2−2
@@ -1457,8 +1457,8 @@ static void dcn20_update_dchubp_dpp( · 1456 unmodified lines
1457 1457
1458 /* Any updates are handled in dc interface, just need to apply existing for plane enable */1458 /* Any updates are handled in dc interface, just need to apply existing for plane enable */
1459 if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed ||1459 if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed ||
1460 pipe_ctx->update_flags.bits.scaler || pipe_ctx->update_flags.bits.viewport)1460 pipe_ctx->update_flags.bits.scaler || viewport_changed == true) &&
1461 && pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {1461 pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {
1462 dc->hwss.set_cursor_position(pipe_ctx);1462 dc->hwss.set_cursor_position(pipe_ctx);
1463 dc->hwss.set_cursor_attribute(pipe_ctx);1463 dc->hwss.set_cursor_attribute(pipe_ctx);
1464 1464
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h+3−1
@@ -167,7 +167,9 @@ · 166 unmodified lines
167 LE_SF(DCIO_SOFT_RESET, UNIPHYB_SOFT_RESET, mask_sh),\167 LE_SF(DCIO_SOFT_RESET, UNIPHYB_SOFT_RESET, mask_sh),\
168 LE_SF(DCIO_SOFT_RESET, UNIPHYC_SOFT_RESET, mask_sh),\168 LE_SF(DCIO_SOFT_RESET, UNIPHYC_SOFT_RESET, mask_sh),\
169 LE_SF(DCIO_SOFT_RESET, UNIPHYD_SOFT_RESET, mask_sh),\169 LE_SF(DCIO_SOFT_RESET, UNIPHYD_SOFT_RESET, mask_sh),\
170 LE_SF(DCIO_SOFT_RESET, UNIPHYE_SOFT_RESET, mask_sh)170 LE_SF(DCIO_SOFT_RESET, UNIPHYE_SOFT_RESET, mask_sh),\
171 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, mask_sh),\
172 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, mask_sh)
171 173
172#define LINK_ENCODER_MASK_SH_LIST_DCN20(mask_sh)\174#define LINK_ENCODER_MASK_SH_LIST_DCN20(mask_sh)\
173 LINK_ENCODER_MASK_SH_LIST_DCN10(mask_sh),\175 LINK_ENCODER_MASK_SH_LIST_DCN10(mask_sh),\
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c+1−1
@@ -3141,7 +3141,7 @@ static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *co · 3140 unmodified lines
3141 int vlevel = 0;3141 int vlevel = 0;
3142 int pipe_split_from[MAX_PIPES];3142 int pipe_split_from[MAX_PIPES];
3143 int pipe_cnt = 0;3143 int pipe_cnt = 0;
3144 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);3144 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC);
3145 DC_LOGGER_INIT(dc->ctx->logger);3145 DC_LOGGER_INIT(dc->ctx->logger);
3146 3146
3147 BW_VAL_TRACE_COUNT();3147 BW_VAL_TRACE_COUNT();
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_link_encoder.h+4−1
@@ -61,7 +61,10 @@ · 60 unmodified lines
61 DPCS_DCN2_MASK_SH_LIST(mask_sh),\61 DPCS_DCN2_MASK_SH_LIST(mask_sh),\
62 LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_DATA_ORDER_INVERT_18_BIT, mask_sh),\62 LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_DATA_ORDER_INVERT_18_BIT, mask_sh),\
63 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_TX_VBOOST_LVL, mask_sh),\63 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_TX_VBOOST_LVL, mask_sh),\
64 LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_TX_CLK_EN, mask_sh)64 LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_TX_CLK_EN, mask_sh),\
65 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, mask_sh),\
66 LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, mask_sh)
67
65 68
66void dcn30_link_encoder_construct(69void dcn30_link_encoder_construct(
67 struct dcn20_link_encoder *enc20,70 struct dcn20_link_encoder *enc20,
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c+1−0
@@ -491,6 +491,7 @@ static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { · 490 unmodified lines
491[id] = {\491[id] = {\
492 LE_DCN3_REG_LIST(id), \492 LE_DCN3_REG_LIST(id), \
493 UNIPHY_DCN2_REG_LIST(phyid), \493 UNIPHY_DCN2_REG_LIST(phyid), \
494 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
494}495}
495 496
496static const struct dce110_aux_registers_shift aux_shift = {497static const struct dce110_aux_registers_shift aux_shift = {
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c+4−0
@@ -63,6 +63,7 @@ typedef struct { · 62 unmodified lines
63 63
64#define BPP_INVALID 064#define BPP_INVALID 0
65#define BPP_BLENDED_PIPE 0xffffffff65#define BPP_BLENDED_PIPE 0xffffffff
66#define DCN30_MAX_DSC_IMAGE_WIDTH 5184
66 67
67static void DisplayPipeConfiguration(struct display_mode_lib *mode_lib);68static void DisplayPipeConfiguration(struct display_mode_lib *mode_lib);
68static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(69static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(
@@ -3984,6 +3985,9 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l · 3915 unmodified lines
3984 } else if (v->PlaneRequiredDISPCLKWithoutODMCombine > v->MaxDispclkRoundedDownToDFSGranularity) {3985 } else if (v->PlaneRequiredDISPCLKWithoutODMCombine > v->MaxDispclkRoundedDownToDFSGranularity) {
3985 v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;3986 v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
3986 v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1;3987 v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1;
3988 } else if (v->DSCEnabled[k] && (v->HActive[k] > DCN30_MAX_DSC_IMAGE_WIDTH)) {
3989 v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
3990 v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1;
3987 } else {3991 } else {
3988 v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;3992 v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
3989 v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithoutODMCombine;3993 v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithoutODMCombine;
drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h+2−0
@@ -230,6 +230,8 @@ struct clk_mgr_funcs { · 229 unmodified lines
230 230
231 int (*get_dp_ref_clk_frequency)(struct clk_mgr *clk_mgr);231 int (*get_dp_ref_clk_frequency)(struct clk_mgr *clk_mgr);
232 232
233 void (*set_low_power_state)(struct clk_mgr *clk_mgr);
234
233 void (*init_clocks)(struct clk_mgr *clk_mgr);235 void (*init_clocks)(struct clk_mgr *clk_mgr);
234 236
235 void (*enable_pme_wa) (struct clk_mgr *clk_mgr);237 void (*enable_pme_wa) (struct clk_mgr *clk_mgr);
drivers/gpu/drm/amd/display/include/bios_parser_types.h+7−0
@@ -101,6 +101,13 @@ enum bp_pipe_control_action { · 100 unmodified lines
101 ASIC_PIPE_INIT101 ASIC_PIPE_INIT
102};102};
103 103
104enum bp_lvtma_control_action {
105 LVTMA_CONTROL_LCD_BLOFF = 2,
106 LVTMA_CONTROL_LCD_BLON = 3,
107 LVTMA_CONTROL_POWER_ON = 12,
108 LVTMA_CONTROL_POWER_OFF = 13
109};
110
104struct bp_encoder_control {111struct bp_encoder_control {
105 enum bp_encoder_control_action action;112 enum bp_encoder_control_action action;
106 enum engine_id engine_id;113 enum engine_id engine_id;
drivers/gpu/drm/amd/display/include/fixed31_32.h+3−0
@@ -431,6 +431,9 @@ struct fixed31_32 dc_fixpt_log(struct fixed31_32 arg); · 430 unmodified lines
431 */431 */
432static inline struct fixed31_32 dc_fixpt_pow(struct fixed31_32 arg1, struct fixed31_32 arg2)432static inline struct fixed31_32 dc_fixpt_pow(struct fixed31_32 arg1, struct fixed31_32 arg2)
433{433{
434 if (arg1.value == 0)
435 return arg2.value == 0 ? dc_fixpt_one : dc_fixpt_zero;
436
434 return dc_fixpt_exp(437 return dc_fixpt_exp(
435 dc_fixpt_mul(438 dc_fixpt_mul(
436 dc_fixpt_log(arg1),439 dc_fixpt_log(arg1),
drivers/gpu/drm/amd/display/modules/freesync/freesync.c+29−7
@@ -324,22 +324,44 @@ static void apply_below_the_range(struct core_freesync *core_freesync, · 323 unmodified lines
324 324
325 /* Choose number of frames to insert based on how close it325 /* Choose number of frames to insert based on how close it
326 * can get to the mid point of the variable range.326 * can get to the mid point of the variable range.
327 * - Delta for CEIL: delta_from_mid_point_in_us_1
328 * - Delta for FLOOR: delta_from_mid_point_in_us_2
327 */329 */
328 if ((frame_time_in_us / mid_point_frames_ceil) > in_out_vrr->min_duration_in_us &&330 if ((last_render_time_in_us / mid_point_frames_ceil) < in_out_vrr->min_duration_in_us) {
329 (delta_from_mid_point_in_us_1 < delta_from_mid_point_in_us_2 ||331 /* Check for out of range.
330 mid_point_frames_floor < 2)) {332 * If using CEIL produces a value that is out of range,
333 * then we are forced to use FLOOR.
334 */
335 frames_to_insert = mid_point_frames_floor;
336 } else if (mid_point_frames_floor < 2) {
337 /* Check if FLOOR would result in non-LFC. In this case
338 * choose to use CEIL
339 */
340 frames_to_insert = mid_point_frames_ceil;
341 } else if (delta_from_mid_point_in_us_1 < delta_from_mid_point_in_us_2) {
342 /* If choosing CEIL results in a frame duration that is
343 * closer to the mid point of the range.
344 * Choose CEIL
345 */
331 frames_to_insert = mid_point_frames_ceil;346 frames_to_insert = mid_point_frames_ceil;
332 delta_from_mid_point_delta_in_us = delta_from_mid_point_in_us_2 -
333 delta_from_mid_point_in_us_1;
334 } else {347 } else {
348 /* If choosing FLOOR results in a frame duration that is
349 * closer to the mid point of the range.
350 * Choose FLOOR
351 */
335 frames_to_insert = mid_point_frames_floor;352 frames_to_insert = mid_point_frames_floor;
336 delta_from_mid_point_delta_in_us = delta_from_mid_point_in_us_1 -
337 delta_from_mid_point_in_us_2;
338 }353 }
339 354
340 /* Prefer current frame multiplier when BTR is enabled unless it drifts355 /* Prefer current frame multiplier when BTR is enabled unless it drifts
341 * too far from the midpoint356 * too far from the midpoint
342 */357 */
358 if (delta_from_mid_point_in_us_1 < delta_from_mid_point_in_us_2) {
359 delta_from_mid_point_delta_in_us = delta_from_mid_point_in_us_2 -
360 delta_from_mid_point_in_us_1;
361 } else {
362 delta_from_mid_point_delta_in_us = delta_from_mid_point_in_us_1 -
363 delta_from_mid_point_in_us_2;
364 }
343 if (in_out_vrr->btr.frames_to_insert != 0 &&365 if (in_out_vrr->btr.frames_to_insert != 0 &&
344 delta_from_mid_point_delta_in_us < BTR_DRIFT_MARGIN) {366 delta_from_mid_point_delta_in_us < BTR_DRIFT_MARGIN) {
345 if (((last_render_time_in_us / in_out_vrr->btr.frames_to_insert) <367 if (((last_render_time_in_us / in_out_vrr->btr.frames_to_insert) <
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c+13−6
@@ -1840,10 +1840,14 @@ static bool arcturus_is_dpm_running(struct smu_context *smu) · 1839 unmodified lines
1840{1840{
1841 int ret = 0;1841 int ret = 0;
1842 uint32_t feature_mask[2];1842 uint32_t feature_mask[2];
1843 unsigned long feature_enabled;1843 uint64_t feature_enabled;
1844
1844 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);1845 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
1845 feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |1846 if (ret)
1846 ((uint64_t)feature_mask[1] << 32));1847 return false;
1848
1849 feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
1850
1847 return !!(feature_enabled & SMC_DPM_FEATURE);1851 return !!(feature_enabled & SMC_DPM_FEATURE);
1848}1852}
1849 1853
@@ -2204,14 +2208,17 @@ static const struct throttling_logging_label { · 354 unmodified lines
2204};2208};
2205static void arcturus_log_thermal_throttling_event(struct smu_context *smu)2209static void arcturus_log_thermal_throttling_event(struct smu_context *smu)
2206{2210{
2211 int ret;
2207 int throttler_idx, throtting_events = 0, buf_idx = 0;2212 int throttler_idx, throtting_events = 0, buf_idx = 0;
2208 struct amdgpu_device *adev = smu->adev;2213 struct amdgpu_device *adev = smu->adev;
2209 uint32_t throttler_status;2214 uint32_t throttler_status;
2210 char log_buf[256];2215 char log_buf[256];
2211 2216
2212 arcturus_get_smu_metrics_data(smu,2217 ret = arcturus_get_smu_metrics_data(smu,
2213 METRICS_THROTTLER_STATUS,2218 METRICS_THROTTLER_STATUS,
2214 &throttler_status);2219 &throttler_status);
2220 if (ret)
2221 return;
2215 2222
2216 memset(log_buf, 0, sizeof(log_buf));2223 memset(log_buf, 0, sizeof(log_buf));
2217 for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label);2224 for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label);
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c+3−6
@@ -204,8 +204,7 @@ static int smu10_set_min_deep_sleep_dcefclk(struct pp_hwmgr *hwmgr, uint32_t clo · 203 unmodified lines
204{204{
205 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);205 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
206 206
207 if (smu10_data->need_min_deep_sleep_dcefclk &&207 if (clock && smu10_data->deep_sleep_dcefclk != clock) {
208 smu10_data->deep_sleep_dcefclk != clock) {
209 smu10_data->deep_sleep_dcefclk = clock;208 smu10_data->deep_sleep_dcefclk = clock;
210 smum_send_msg_to_smc_with_parameter(hwmgr,209 smum_send_msg_to_smc_with_parameter(hwmgr,
211 PPSMC_MSG_SetMinDeepSleepDcefclk,210 PPSMC_MSG_SetMinDeepSleepDcefclk,
@@ -219,8 +218,7 @@ static int smu10_set_hard_min_dcefclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t c · 7 unmodified lines
219{218{
220 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);219 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
221 220
222 if (smu10_data->dcf_actual_hard_min_freq &&221 if (clock && smu10_data->dcf_actual_hard_min_freq != clock) {
223 smu10_data->dcf_actual_hard_min_freq != clock) {
224 smu10_data->dcf_actual_hard_min_freq = clock;222 smu10_data->dcf_actual_hard_min_freq = clock;
225 smum_send_msg_to_smc_with_parameter(hwmgr,223 smum_send_msg_to_smc_with_parameter(hwmgr,
226 PPSMC_MSG_SetHardMinDcefclkByFreq,224 PPSMC_MSG_SetHardMinDcefclkByFreq,
@@ -234,8 +232,7 @@ static int smu10_set_hard_min_fclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t cloc · 7 unmodified lines
234{232{
235 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);233 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
236 234
237 if (smu10_data->f_actual_hard_min_freq &&235 if (clock && smu10_data->f_actual_hard_min_freq != clock) {
238 smu10_data->f_actual_hard_min_freq != clock) {
239 smu10_data->f_actual_hard_min_freq = clock;236 smu10_data->f_actual_hard_min_freq = clock;
240 smum_send_msg_to_smc_with_parameter(hwmgr,237 smum_send_msg_to_smc_with_parameter(hwmgr,
241 PPSMC_MSG_SetHardMinFclkByFreq,238 PPSMC_MSG_SetHardMinFclkByFreq,
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c+2−1
@@ -3581,7 +3581,8 @@ static int smu7_read_sensor(struct pp_hwmgr *hwmgr, int idx, · 3580 unmodified lines
3581 case AMDGPU_PP_SENSOR_GPU_POWER:3581 case AMDGPU_PP_SENSOR_GPU_POWER:
3582 return smu7_get_gpu_power(hwmgr, (uint32_t *)value);3582 return smu7_get_gpu_power(hwmgr, (uint32_t *)value);
3583 case AMDGPU_PP_SENSOR_VDDGFX:3583 case AMDGPU_PP_SENSOR_VDDGFX:
3584 if ((data->vr_config & 0xff) == 0x2)3584 if ((data->vr_config & VRCONF_VDDGFX_MASK) ==
3585 (VR_SVI2_PLANE_2 << VRCONF_VDDGFX_SHIFT))
3585 val_vid = PHM_READ_INDIRECT_FIELD(hwmgr->device,3586 val_vid = PHM_READ_INDIRECT_FIELD(hwmgr->device,
3586 CGS_IND_REG__SMC, PWR_SVI2_STATUS, PLANE2_VID);3587 CGS_IND_REG__SMC, PWR_SVI2_STATUS, PLANE2_VID);
3587 else3588 else
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c+22−10
@@ -363,17 +363,29 @@ int vega10_thermal_get_temperature(struct pp_hwmgr *hwmgr) · 362 unmodified lines
363static int vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,363static int vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
364 struct PP_TemperatureRange *range)364 struct PP_TemperatureRange *range)
365{365{
366 struct phm_ppt_v2_information *pp_table_info =
367 (struct phm_ppt_v2_information *)(hwmgr->pptable);
368 struct phm_tdp_table *tdp_table = pp_table_info->tdp_table;
366 struct amdgpu_device *adev = hwmgr->adev;369 struct amdgpu_device *adev = hwmgr->adev;
367 int low = VEGA10_THERMAL_MINIMUM_ALERT_TEMP *370 int low = VEGA10_THERMAL_MINIMUM_ALERT_TEMP;
368 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;371 int high = VEGA10_THERMAL_MAXIMUM_ALERT_TEMP;
369 int high = VEGA10_THERMAL_MAXIMUM_ALERT_TEMP *
370 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
371 uint32_t val;372 uint32_t val;
372 373
373 if (low < range->min)374 /* compare them in unit celsius degree */
374 low = range->min;375 if (low < range->min / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)
375 if (high > range->max)376 low = range->min / PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
376 high = range->max;377
378 /*
379 * As a common sense, usSoftwareShutdownTemp should be bigger
380 * than ThotspotLimit. For any invalid usSoftwareShutdownTemp,
381 * we will just use the max possible setting VEGA10_THERMAL_MAXIMUM_ALERT_TEMP
382 * to avoid false alarms.
383 */
384 if ((tdp_table->usSoftwareShutdownTemp >
385 range->hotspot_crit_max / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)) {
386 if (high > tdp_table->usSoftwareShutdownTemp)
387 high = tdp_table->usSoftwareShutdownTemp;
388 }
377 389
378 if (low > high)390 if (low > high)
379 return -EINVAL;391 return -EINVAL;
@@ -382,8 +394,8 @@ static int vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, · 2 unmodified lines
382 394
383 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);395 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
384 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);396 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
385 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));397 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, high);
386 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));398 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, low);
387 val &= (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK) &399 val &= (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK) &
388 (~THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK) &400 (~THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK) &
389 (~THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK);401 (~THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK);
drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c+11−10
@@ -170,17 +170,18 @@ int vega12_thermal_get_temperature(struct pp_hwmgr *hwmgr) · 169 unmodified lines
170static int vega12_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,170static int vega12_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
171 struct PP_TemperatureRange *range)171 struct PP_TemperatureRange *range)
172{172{
173 struct phm_ppt_v3_information *pptable_information =
174 (struct phm_ppt_v3_information *)hwmgr->pptable;
173 struct amdgpu_device *adev = hwmgr->adev;175 struct amdgpu_device *adev = hwmgr->adev;
174 int low = VEGA12_THERMAL_MINIMUM_ALERT_TEMP *176 int low = VEGA12_THERMAL_MINIMUM_ALERT_TEMP;
175 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;177 int high = VEGA12_THERMAL_MAXIMUM_ALERT_TEMP;
176 int high = VEGA12_THERMAL_MAXIMUM_ALERT_TEMP *
177 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
178 uint32_t val;178 uint32_t val;
179 179
180 if (low < range->min)180 /* compare them in unit celsius degree */
181 low = range->min;181 if (low < range->min / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)
182 if (high > range->max)182 low = range->min / PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
183 high = range->max;183 if (high > pptable_information->us_software_shutdown_temp)
184 high = pptable_information->us_software_shutdown_temp;
184 185
185 if (low > high)186 if (low > high)
186 return -EINVAL;187 return -EINVAL;
@@ -189,8 +190,8 @@ static int vega12_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, · 2 unmodified lines
189 190
190 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);191 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
191 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);192 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
192 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));193 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, high);
193 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));194 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, low);
194 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);195 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
195 196
196 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);197 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c+19−25
@@ -979,10 +979,7 @@ static int vega20_disable_all_smu_features(struct pp_hwmgr *hwmgr) · 978 unmodified lines
979{979{
980 struct vega20_hwmgr *data =980 struct vega20_hwmgr *data =
981 (struct vega20_hwmgr *)(hwmgr->backend);981 (struct vega20_hwmgr *)(hwmgr->backend);
982 uint64_t features_enabled;982 int i, ret = 0;
983 int i;
984 bool enabled;
985 int ret = 0;
986 983
987 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,984 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,
988 PPSMC_MSG_DisableAllSmuFeatures,985 PPSMC_MSG_DisableAllSmuFeatures,
@@ -990,17 +987,8 @@ static int vega20_disable_all_smu_features(struct pp_hwmgr *hwmgr) · 1 unmodified line
990 "[DisableAllSMUFeatures] Failed to disable all smu features!",987 "[DisableAllSMUFeatures] Failed to disable all smu features!",
991 return ret);988 return ret);
992 989
993 ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);990 for (i = 0; i < GNLD_FEATURES_MAX; i++)
994 PP_ASSERT_WITH_CODE(!ret,991 data->smu_features[i].enabled = 0;
995 "[DisableAllSMUFeatures] Failed to get enabled smc features!",
996 return ret);
997
998 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
999 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ?
1000 true : false;
1001 data->smu_features[i].enabled = enabled;
1002 data->smu_features[i].supported = enabled;
1003 }
1004 992
1005 return 0;993 return 0;
1006}994}
@@ -1652,12 +1640,6 @@ static void vega20_init_powergate_state(struct pp_hwmgr *hwmgr) · 645 unmodified lines
1652 1640
1653 data->uvd_power_gated = true;1641 data->uvd_power_gated = true;
1654 data->vce_power_gated = true;1642 data->vce_power_gated = true;
1655
1656 if (data->smu_features[GNLD_DPM_UVD].enabled)
1657 data->uvd_power_gated = false;
1658
1659 if (data->smu_features[GNLD_DPM_VCE].enabled)
1660 data->vce_power_gated = false;
1661}1643}
1662 1644
1663static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr)1645static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
@@ -3230,10 +3212,11 @@ static int vega20_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf) · 1566 unmodified lines
3230 3212
3231static int vega20_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfeature_masks)3213static int vega20_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfeature_masks)
3232{3214{
3233 uint64_t features_enabled;3215 struct vega20_hwmgr *data =
3234 uint64_t features_to_enable;3216 (struct vega20_hwmgr *)(hwmgr->backend);
3235 uint64_t features_to_disable;3217 uint64_t features_enabled, features_to_enable, features_to_disable;
3236 int ret = 0;3218 int i, ret = 0;
3219 bool enabled;
3237 3220
3238 if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX))3221 if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX))
3239 return -EINVAL;3222 return -EINVAL;
@@ -3262,6 +3245,17 @@ static int vega20_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfe · 22 unmodified lines
3262 return ret;3245 return ret;
3263 }3246 }
3264 3247
3248 /* Update the cached feature enablement state */
3249 ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
3250 if (ret)
3251 return ret;
3252
3253 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
3254 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ?
3255 true : false;
3256 data->smu_features[i].enabled = enabled;
3257 }
3258
3265 return 0;3259 return 0;
3266}3260}
3267 3261
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c+11−10
@@ -240,17 +240,18 @@ int vega20_thermal_get_temperature(struct pp_hwmgr *hwmgr) · 239 unmodified lines
240static int vega20_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,240static int vega20_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
241 struct PP_TemperatureRange *range)241 struct PP_TemperatureRange *range)
242{242{
243 struct phm_ppt_v3_information *pptable_information =
244 (struct phm_ppt_v3_information *)hwmgr->pptable;
243 struct amdgpu_device *adev = hwmgr->adev;245 struct amdgpu_device *adev = hwmgr->adev;
244 int low = VEGA20_THERMAL_MINIMUM_ALERT_TEMP *246 int low = VEGA20_THERMAL_MINIMUM_ALERT_TEMP;
245 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;247 int high = VEGA20_THERMAL_MAXIMUM_ALERT_TEMP;
246 int high = VEGA20_THERMAL_MAXIMUM_ALERT_TEMP *
247 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
248 uint32_t val;248 uint32_t val;
249 249
250 if (low < range->min)250 /* compare them in unit celsius degree */
251 low = range->min;251 if (low < range->min / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)
252 if (high > range->max)252 low = range->min / PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
253 high = range->max;253 if (high > pptable_information->us_software_shutdown_temp)
254 high = pptable_information->us_software_shutdown_temp;
254 255
255 if (low > high)256 if (low > high)
256 return -EINVAL;257 return -EINVAL;
@@ -259,8 +260,8 @@ static int vega20_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, · 2 unmodified lines
259 260
260 val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);261 val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
261 val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);262 val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
262 val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));263 val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, high);
263 val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES));264 val = CGS_REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, low);
264 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);265 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
265 266
266 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);267 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
drivers/gpu/drm/amd/powerplay/navi10_ppt.c+7−3
@@ -1331,10 +1331,14 @@ static bool navi10_is_dpm_running(struct smu_context *smu) · 1330 unmodified lines
1331{1331{
1332 int ret = 0;1332 int ret = 0;
1333 uint32_t feature_mask[2];1333 uint32_t feature_mask[2];
1334 unsigned long feature_enabled;1334 uint64_t feature_enabled;
1335
1335 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);1336 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
1336 feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |1337 if (ret)
1337 ((uint64_t)feature_mask[1] << 32));1338 return false;
1339
1340 feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
1341
1338 return !!(feature_enabled & SMC_DPM_FEATURE);1342 return !!(feature_enabled & SMC_DPM_FEATURE);
1339}1343}
1340 1344
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c+19−6
@@ -68,7 +68,8 @@ · 67 unmodified lines
68 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \68 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
69 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \69 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
70 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \70 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
71 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))71 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT) | \
72 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
72 73
73#define SMU_11_0_7_GFX_BUSY_THRESHOLD 1574#define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
74 75
@@ -95,6 +96,7 @@ static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] · 20 unmodified lines
95 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 0),96 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 0),
96 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),97 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
97 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),98 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
99 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0),
98 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),100 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
99 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0),101 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0),
100 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 0),102 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 0),
@@ -228,6 +230,7 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu, · 127 unmodified lines
228 230
229 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)231 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
230 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)232 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
233 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
231 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)234 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
232 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)235 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
233 | FEATURE_MASK(FEATURE_DS_FCLK_BIT)236 | FEATURE_MASK(FEATURE_DS_FCLK_BIT)
@@ -775,7 +778,7 @@ static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enabl · 541 unmodified lines
775 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);778 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
776 if (ret)779 if (ret)
777 return ret;780 return ret;
778 if (adev->asic_type == CHIP_SIENNA_CICHLID) {781 if (adev->vcn.num_vcn_inst > 1) {
779 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn,782 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn,
780 0x10000, NULL);783 0x10000, NULL);
781 if (ret)784 if (ret)
@@ -787,7 +790,7 @@ static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enabl · 5 unmodified lines
787 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL);790 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL);
788 if (ret)791 if (ret)
789 return ret;792 return ret;
790 if (adev->asic_type == CHIP_SIENNA_CICHLID) {793 if (adev->vcn.num_vcn_inst > 1) {
791 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn,794 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn,
792 0x10000, NULL);795 0x10000, NULL);
793 if (ret)796 if (ret)
@@ -1146,10 +1149,14 @@ static bool sienna_cichlid_is_dpm_running(struct smu_context *smu) · 352 unmodified lines
1146{1149{
1147 int ret = 0;1150 int ret = 0;
1148 uint32_t feature_mask[2];1151 uint32_t feature_mask[2];
1149 unsigned long feature_enabled;1152 uint64_t feature_enabled;
1153
1150 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);1154 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
1151 feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |1155 if (ret)
1152 ((uint64_t)feature_mask[1] << 32));1156 return false;
1157
1158 feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
1159
1153 return !!(feature_enabled & SMC_DPM_FEATURE);1160 return !!(feature_enabled & SMC_DPM_FEATURE);
1154}1161}
1155 1162
@@ -1732,6 +1739,11 @@ static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu, · 576 unmodified lines
1732 return ret;1739 return ret;
1733}1740}
1734 1741
1742static int sienna_cichlid_run_btc(struct smu_context *smu)
1743{
1744 return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
1745}
1746
1735static bool sienna_cichlid_is_baco_supported(struct smu_context *smu)1747static bool sienna_cichlid_is_baco_supported(struct smu_context *smu)
1736{1748{
1737 struct amdgpu_device *adev = smu->adev;1749 struct amdgpu_device *adev = smu->adev;
@@ -2719,6 +2731,7 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = { · 981 unmodified lines
2719 .mode1_reset = smu_v11_0_mode1_reset,2731 .mode1_reset = smu_v11_0_mode1_reset,
2720 .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,2732 .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
2721 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,2733 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2734 .run_btc = sienna_cichlid_run_btc,
2722 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,2735 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2723 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,2736 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
2724};2737};
drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c+2−0
@@ -37,6 +37,7 @@ · 36 unmodified lines
37#include "cgs_common.h"37#include "cgs_common.h"
38#include "atombios.h"38#include "atombios.h"
39#include "pppcielanes.h"39#include "pppcielanes.h"
40#include "smu7_smumgr.h"
40 41
41#include "smu/smu_7_0_1_d.h"42#include "smu/smu_7_0_1_d.h"
42#include "smu/smu_7_0_1_sh_mask.h"43#include "smu/smu_7_0_1_sh_mask.h"
@@ -2948,6 +2949,7 @@ const struct pp_smumgr_func ci_smu_funcs = { · 2905 unmodified lines
2948 .request_smu_load_specific_fw = NULL,2949 .request_smu_load_specific_fw = NULL,
2949 .send_msg_to_smc = ci_send_msg_to_smc,2950 .send_msg_to_smc = ci_send_msg_to_smc,
2950 .send_msg_to_smc_with_parameter = ci_send_msg_to_smc_with_parameter,2951 .send_msg_to_smc_with_parameter = ci_send_msg_to_smc_with_parameter,
2952 .get_argument = smu7_get_argument,
2951 .download_pptable_settings = NULL,2953 .download_pptable_settings = NULL,
2952 .upload_pptable_settings = NULL,2954 .upload_pptable_settings = NULL,
2953 .get_offsetof = ci_get_offsetof,2955 .get_offsetof = ci_get_offsetof,
drivers/gpu/drm/arm/malidp_hw.c+3−3
@@ -532,7 +532,7 @@ static int malidp500_enable_memwrite(struct malidp_hw_device *hwdev, · 531 unmodified lines
532 malidp_hw_write(hwdev, lower_32_bits(addrs[1]), base + MALIDP_MW_P2_PTR_LOW);532 malidp_hw_write(hwdev, lower_32_bits(addrs[1]), base + MALIDP_MW_P2_PTR_LOW);
533 malidp_hw_write(hwdev, upper_32_bits(addrs[1]), base + MALIDP_MW_P2_PTR_HIGH);533 malidp_hw_write(hwdev, upper_32_bits(addrs[1]), base + MALIDP_MW_P2_PTR_HIGH);
534 malidp_hw_write(hwdev, pitches[1], base + MALIDP_MW_P2_STRIDE);534 malidp_hw_write(hwdev, pitches[1], base + MALIDP_MW_P2_STRIDE);
535 /* fall through */535 fallthrough;
536 case 1:536 case 1:
537 malidp_hw_write(hwdev, lower_32_bits(addrs[0]), base + MALIDP_MW_P1_PTR_LOW);537 malidp_hw_write(hwdev, lower_32_bits(addrs[0]), base + MALIDP_MW_P1_PTR_LOW);
538 malidp_hw_write(hwdev, upper_32_bits(addrs[0]), base + MALIDP_MW_P1_PTR_HIGH);538 malidp_hw_write(hwdev, upper_32_bits(addrs[0]), base + MALIDP_MW_P1_PTR_HIGH);
@@ -869,7 +869,7 @@ static int malidp550_enable_memwrite(struct malidp_hw_device *hwdev, · 330 unmodified lines
869 malidp_hw_write(hwdev, lower_32_bits(addrs[1]), base + MALIDP_MW_P2_PTR_LOW);869 malidp_hw_write(hwdev, lower_32_bits(addrs[1]), base + MALIDP_MW_P2_PTR_LOW);
870 malidp_hw_write(hwdev, upper_32_bits(addrs[1]), base + MALIDP_MW_P2_PTR_HIGH);870 malidp_hw_write(hwdev, upper_32_bits(addrs[1]), base + MALIDP_MW_P2_PTR_HIGH);
871 malidp_hw_write(hwdev, pitches[1], base + MALIDP_MW_P2_STRIDE);871 malidp_hw_write(hwdev, pitches[1], base + MALIDP_MW_P2_STRIDE);
872 /* fall through */872 fallthrough;
873 case 1:873 case 1:
874 malidp_hw_write(hwdev, lower_32_bits(addrs[0]), base + MALIDP_MW_P1_PTR_LOW);874 malidp_hw_write(hwdev, lower_32_bits(addrs[0]), base + MALIDP_MW_P1_PTR_LOW);
875 malidp_hw_write(hwdev, upper_32_bits(addrs[0]), base + MALIDP_MW_P1_PTR_HIGH);875 malidp_hw_write(hwdev, upper_32_bits(addrs[0]), base + MALIDP_MW_P1_PTR_HIGH);
@@ -1324,7 +1324,7 @@ static irqreturn_t malidp_se_irq(int irq, void *arg) · 448 unmodified lines
1324 break;1324 break;
1325 case MW_RESTART:1325 case MW_RESTART:
1326 drm_writeback_signal_completion(&malidp->mw_connector, 0);1326 drm_writeback_signal_completion(&malidp->mw_connector, 0);
1327 /* fall through - to a new start */1327 fallthrough; /* to a new start */
1328 case MW_START:1328 case MW_START:
1329 /* writeback started, need to emulate one-shot mode */1329 /* writeback started, need to emulate one-shot mode */
1330 hw->disable_memwrite(hwdev);1330 hw->disable_memwrite(hwdev);
drivers/gpu/drm/ast/ast_main.c+1−1
@@ -238,7 +238,7 @@ static int ast_detect_chip(struct drm_device *dev, bool *need_post) · 237 unmodified lines
238 ast->dp501_fw_addr = NULL;238 ast->dp501_fw_addr = NULL;
239 }239 }
240 }240 }
241 /* fallthrough */241 fallthrough;
242 case 0x0c:242 case 0x0c:
243 ast->tx_chip_type = AST_TX_DP501;243 ast->tx_chip_type = AST_TX_DP501;
244 }244 }
drivers/gpu/drm/bridge/nwl-dsi.c+0−2
@@ -409,7 +409,6 @@ static bool nwl_dsi_read_packet(struct nwl_dsi *dsi, u32 status) · 408 unmodified lines
409 409
410 switch (data_type) {410 switch (data_type) {
411 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:411 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
412 fallthrough;
413 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:412 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
414 if (xfer->msg->rx_len > 1) {413 if (xfer->msg->rx_len > 1) {
415 /* read second byte */414 /* read second byte */
@@ -418,7 +417,6 @@ static bool nwl_dsi_read_packet(struct nwl_dsi *dsi, u32 status) · 2 unmodified lines
418 }417 }
419 fallthrough;418 fallthrough;
420 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:419 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
421 fallthrough;
422 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:420 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
423 if (xfer->msg->rx_len > 0) {421 if (xfer->msg->rx_len > 0) {
424 /* read first byte */422 /* read first byte */
drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c+2−2
@@ -61,10 +61,10 @@ static int dw_hdmi_i2s_hw_params(struct device *dev, void *data, · 60 unmodified lines
61 switch (hparms->channels) {61 switch (hparms->channels) {
62 case 7 ... 8:62 case 7 ... 8:
63 conf0 |= HDMI_AUD_CONF0_I2S_EN3;63 conf0 |= HDMI_AUD_CONF0_I2S_EN3;
64 /* Fall-thru */64 fallthrough;
65 case 5 ... 6:65 case 5 ... 6:
66 conf0 |= HDMI_AUD_CONF0_I2S_EN2;66 conf0 |= HDMI_AUD_CONF0_I2S_EN2;
67 /* Fall-thru */67 fallthrough;
68 case 3 ... 4:68 case 3 ... 4:
69 conf0 |= HDMI_AUD_CONF0_I2S_EN1;69 conf0 |= HDMI_AUD_CONF0_I2S_EN1;
70 /* Fall-thru */70 /* Fall-thru */
drivers/gpu/drm/bridge/ti-sn65dsi86.c+3−3
@@ -604,13 +604,13 @@ static void ti_sn_bridge_read_valid_rates(struct ti_sn_bridge *pdata, · 603 unmodified lines
604 DRM_DEV_ERROR(pdata->dev,604 DRM_DEV_ERROR(pdata->dev,
605 "Unexpected max rate (%#x); assuming 5.4 GHz\n",605 "Unexpected max rate (%#x); assuming 5.4 GHz\n",
606 (int)dpcd_val);606 (int)dpcd_val);
607 /* fall through */607 fallthrough;
608 case DP_LINK_BW_5_4:608 case DP_LINK_BW_5_4:
609 rate_valid[7] = 1;609 rate_valid[7] = 1;
610 /* fall through */610 fallthrough;
611 case DP_LINK_BW_2_7:611 case DP_LINK_BW_2_7:
612 rate_valid[4] = 1;612 rate_valid[4] = 1;
613 /* fall through */613 fallthrough;
614 case DP_LINK_BW_1_62:614 case DP_LINK_BW_1_62:
615 rate_valid[1] = 1;615 rate_valid[1] = 1;
616 break;616 break;
drivers/gpu/drm/drm_atomic_helper.c+4−3
@@ -34,6 +34,7 @@ · 33 unmodified lines
34#include <drm/drm_bridge.h>34#include <drm/drm_bridge.h>
35#include <drm/drm_damage_helper.h>35#include <drm/drm_damage_helper.h>
36#include <drm/drm_device.h>36#include <drm/drm_device.h>
37#include <drm/drm_drv.h>
37#include <drm/drm_plane_helper.h>38#include <drm/drm_plane_helper.h>
38#include <drm/drm_print.h>39#include <drm/drm_print.h>
39#include <drm/drm_self_refresh_helper.h>40#include <drm/drm_self_refresh_helper.h>
@@ -3106,7 +3107,7 @@ void drm_atomic_helper_shutdown(struct drm_device *dev) · 3066 unmodified lines
3106 if (ret)3107 if (ret)
3107 DRM_ERROR("Disabling all crtc's during unload failed with %i\n", ret);3108 DRM_ERROR("Disabling all crtc's during unload failed with %i\n", ret);
3108 3109
3109 DRM_MODESET_LOCK_ALL_END(ctx, ret);3110 DRM_MODESET_LOCK_ALL_END(dev, ctx, ret);
3110}3111}
3111EXPORT_SYMBOL(drm_atomic_helper_shutdown);3112EXPORT_SYMBOL(drm_atomic_helper_shutdown);
3112 3113
@@ -3246,7 +3247,7 @@ struct drm_atomic_state *drm_atomic_helper_suspend(struct drm_device *dev) · 133 unmodified lines
3246 }3247 }
3247 3248
3248unlock:3249unlock:
3249 DRM_MODESET_LOCK_ALL_END(ctx, err);3250 DRM_MODESET_LOCK_ALL_END(dev, ctx, err);
3250 if (err)3251 if (err)
3251 return ERR_PTR(err);3252 return ERR_PTR(err);
3252 3253
@@ -3327,7 +3328,7 @@ int drm_atomic_helper_resume(struct drm_device *dev, · 74 unmodified lines
3327 3328
3328 err = drm_atomic_helper_commit_duplicated_state(state, &ctx);3329 err = drm_atomic_helper_commit_duplicated_state(state, &ctx);
3329 3330
3330 DRM_MODESET_LOCK_ALL_END(ctx, err);3331 DRM_MODESET_LOCK_ALL_END(dev, ctx, err);
3331 drm_atomic_state_put(state);3332 drm_atomic_state_put(state);
3332 3333
3333 return err;3334 return err;
drivers/gpu/drm/drm_bufs.c+1−1
@@ -537,7 +537,7 @@ int drm_legacy_rmmap_locked(struct drm_device *dev, struct drm_local_map *map) · 536 unmodified lines
537 switch (map->type) {537 switch (map->type) {
538 case _DRM_REGISTERS:538 case _DRM_REGISTERS:
539 iounmap(map->handle);539 iounmap(map->handle);
540 /* FALLTHROUGH */540 fallthrough;
541 case _DRM_FRAME_BUFFER:541 case _DRM_FRAME_BUFFER:
542 arch_phys_wc_del(map->mtrr);542 arch_phys_wc_del(map->mtrr);
543 break;543 break;
drivers/gpu/drm/drm_color_mgmt.c+1−1
@@ -294,7 +294,7 @@ int drm_mode_gamma_set_ioctl(struct drm_device *dev, · 293 unmodified lines
294 crtc->gamma_size, &ctx);294 crtc->gamma_size, &ctx);
295 295
296out:296out:
297 DRM_MODESET_LOCK_ALL_END(ctx, ret);297 DRM_MODESET_LOCK_ALL_END(dev, ctx, ret);
298 return ret;298 return ret;
299 299
300}300}
drivers/gpu/drm/drm_crtc.c+1−3
@@ -588,7 +588,6 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data, · 587 unmodified lines
588 if (crtc_req->mode_valid && !drm_lease_held(file_priv, plane->base.id))588 if (crtc_req->mode_valid && !drm_lease_held(file_priv, plane->base.id))
589 return -EACCES;589 return -EACCES;
590 590
591 mutex_lock(&crtc->dev->mode_config.mutex);
592 DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx,591 DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx,
593 DRM_MODESET_ACQUIRE_INTERRUPTIBLE, ret);592 DRM_MODESET_ACQUIRE_INTERRUPTIBLE, ret);
594 593
@@ -756,8 +755,7 @@ out: · 161 unmodified lines
756 fb = NULL;755 fb = NULL;
757 mode = NULL;756 mode = NULL;
758 757
759 DRM_MODESET_LOCK_ALL_END(ctx, ret);758 DRM_MODESET_LOCK_ALL_END(dev, ctx, ret);
760 mutex_unlock(&crtc->dev->mode_config.mutex);
761 759
762 return ret;760 return ret;
763}761}
drivers/gpu/drm/drm_dp_helper.c+1−1
@@ -492,7 +492,7 @@ int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], · 491 unmodified lines
492 case DP_DS_16BPC:492 case DP_DS_16BPC:
493 return 16;493 return 16;
494 }494 }
495 /* fall through */495 fallthrough;
496 default:496 default:
497 return 0;497 return 0;
498 }498 }
drivers/gpu/drm/drm_dp_mst_topology.c+2−2
@@ -5040,8 +5040,8 @@ int drm_dp_mst_add_affected_dsc_crtcs(struct drm_atomic_state *state, struct drm · 5039 unmodified lines
5040 5040
5041 crtc = conn_state->crtc;5041 crtc = conn_state->crtc;
5042 5042
5043 if (WARN_ON(!crtc))5043 if (!crtc)
5044 return -EINVAL;5044 continue;
5045 5045
5046 if (!drm_dp_mst_dsc_aux_for_port(pos->port))5046 if (!drm_dp_mst_dsc_aux_for_port(pos->port))
5047 continue;5047 continue;
drivers/gpu/drm/drm_mode_object.c+2−2
@@ -428,7 +428,7 @@ int drm_mode_obj_get_properties_ioctl(struct drm_device *dev, void *data, · 427 unmodified lines
428out_unref:428out_unref:
429 drm_mode_object_put(obj);429 drm_mode_object_put(obj);
430out:430out:
431 DRM_MODESET_LOCK_ALL_END(ctx, ret);431 DRM_MODESET_LOCK_ALL_END(dev, ctx, ret);
432 return ret;432 return ret;
433}433}
434 434
@@ -470,7 +470,7 @@ static int set_property_legacy(struct drm_mode_object *obj, · 35 unmodified lines
470 break;470 break;
471 }471 }
472 drm_property_change_valid_put(prop, ref);472 drm_property_change_valid_put(prop, ref);
473 DRM_MODESET_LOCK_ALL_END(ctx, ret);473 DRM_MODESET_LOCK_ALL_END(dev, ctx, ret);
474 474
475 return ret;475 return ret;
476}476}
drivers/gpu/drm/drm_modes.c+1−1
@@ -1930,7 +1930,7 @@ void drm_mode_convert_to_umode(struct drm_mode_modeinfo *out, · 1929 unmodified lines
1930 default:1930 default:
1931 WARN(1, "Invalid aspect ratio (0%x) on mode\n",1931 WARN(1, "Invalid aspect ratio (0%x) on mode\n",
1932 in->picture_aspect_ratio);1932 in->picture_aspect_ratio);
1933 /* fall through */1933 fallthrough;
1934 case HDMI_PICTURE_ASPECT_NONE:1934 case HDMI_PICTURE_ASPECT_NONE:
1935 out->flags |= DRM_MODE_FLAG_PIC_AR_NONE;1935 out->flags |= DRM_MODE_FLAG_PIC_AR_NONE;
1936 break;1936 break;
drivers/gpu/drm/drm_plane.c+1−1
@@ -792,7 +792,7 @@ static int setplane_internal(struct drm_plane *plane, · 791 unmodified lines
792 crtc_x, crtc_y, crtc_w, crtc_h,792 crtc_x, crtc_y, crtc_w, crtc_h,
793 src_x, src_y, src_w, src_h, &ctx);793 src_x, src_y, src_w, src_h, &ctx);
794 794
795 DRM_MODESET_LOCK_ALL_END(ctx, ret);795 DRM_MODESET_LOCK_ALL_END(plane->dev, ctx, ret);
796 796
797 return ret;797 return ret;
798}798}
drivers/gpu/drm/etnaviv/etnaviv_gpu.c+9−2
@@ -337,9 +337,16 @@ static void etnaviv_hw_identify(struct etnaviv_gpu *gpu) · 336 unmodified lines
337 337
338 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL);338 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL);
339 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV);339 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV);
340 gpu->identity.product_id = gpu_read(gpu, VIVS_HI_CHIP_PRODUCT_ID);
341 gpu->identity.customer_id = gpu_read(gpu, VIVS_HI_CHIP_CUSTOMER_ID);340 gpu->identity.customer_id = gpu_read(gpu, VIVS_HI_CHIP_CUSTOMER_ID);
342 gpu->identity.eco_id = gpu_read(gpu, VIVS_HI_CHIP_ECO_ID);341
342 /*
343 * Reading these two registers on GC600 rev 0x19 result in a
344 * unhandled fault: external abort on non-linefetch
345 */
346 if (!etnaviv_is_model_rev(gpu, GC600, 0x19)) {
347 gpu->identity.product_id = gpu_read(gpu, VIVS_HI_CHIP_PRODUCT_ID);
348 gpu->identity.eco_id = gpu_read(gpu, VIVS_HI_CHIP_ECO_ID);
349 }
343 350
344 /*351 /*
345 * !!!! HACK ALERT !!!!352 * !!!! HACK ALERT !!!!
drivers/gpu/drm/etnaviv/etnaviv_sched.c+6−5
@@ -89,12 +89,15 @@ static void etnaviv_sched_timedout_job(struct drm_sched_job *sched_job) · 88 unmodified lines
89 u32 dma_addr;89 u32 dma_addr;
90 int change;90 int change;
91 91
92 /* block scheduler */
93 drm_sched_stop(&gpu->sched, sched_job);
94
92 /*95 /*
93 * If the GPU managed to complete this jobs fence, the timout is96 * If the GPU managed to complete this jobs fence, the timout is
94 * spurious. Bail out.97 * spurious. Bail out.
95 */98 */
96 if (dma_fence_is_signaled(submit->out_fence))99 if (dma_fence_is_signaled(submit->out_fence))
97 return;100 goto out_no_timeout;
98 101
99 /*102 /*
100 * If the GPU is still making forward progress on the front-end (which103 * If the GPU is still making forward progress on the front-end (which
@@ -105,12 +108,9 @@ static void etnaviv_sched_timedout_job(struct drm_sched_job *sched_job) · 4 unmodified lines
105 change = dma_addr - gpu->hangcheck_dma_addr;108 change = dma_addr - gpu->hangcheck_dma_addr;
106 if (change < 0 || change > 16) {109 if (change < 0 || change > 16) {
107 gpu->hangcheck_dma_addr = dma_addr;110 gpu->hangcheck_dma_addr = dma_addr;
108 return;111 goto out_no_timeout;
109 }112 }
110 113
111 /* block scheduler */
112 drm_sched_stop(&gpu->sched, sched_job);
113
114 if(sched_job)114 if(sched_job)
115 drm_sched_increase_karma(sched_job);115 drm_sched_increase_karma(sched_job);
116 116
@@ -120,6 +120,7 @@ static void etnaviv_sched_timedout_job(struct drm_sched_job *sched_job) · 3 unmodified lines
120 120
121 drm_sched_resubmit_jobs(&gpu->sched);121 drm_sched_resubmit_jobs(&gpu->sched);
122 122
123out_no_timeout:
123 /* restart scheduler after GPU is usable again */124 /* restart scheduler after GPU is usable again */
124 drm_sched_start(&gpu->sched, true);125 drm_sched_start(&gpu->sched, true);
125}126}
drivers/gpu/drm/exynos/exynos_drm_dsi.c+5−5
@@ -987,10 +987,10 @@ static void exynos_dsi_send_to_fifo(struct exynos_dsi *dsi, · 986 unmodified lines
987 switch (length) {987 switch (length) {
988 case 3:988 case 3:
989 reg |= payload[2] << 16;989 reg |= payload[2] << 16;
990 /* Fall through */990 fallthrough;
991 case 2:991 case 2:
992 reg |= payload[1] << 8;992 reg |= payload[1] << 8;
993 /* Fall through */993 fallthrough;
994 case 1:994 case 1:
995 reg |= payload[0];995 reg |= payload[0];
996 exynos_dsi_write(dsi, DSIM_PAYLOAD_REG, reg);996 exynos_dsi_write(dsi, DSIM_PAYLOAD_REG, reg);
@@ -1038,7 +1038,7 @@ static void exynos_dsi_read_from_fifo(struct exynos_dsi *dsi, · 41 unmodified lines
1038 payload[1] = reg >> 16;1038 payload[1] = reg >> 16;
1039 ++xfer->rx_done;1039 ++xfer->rx_done;
1040 }1040 }
1041 /* Fall through */1041 fallthrough;
1042 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:1042 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
1043 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:1043 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
1044 payload[0] = reg >> 8;1044 payload[0] = reg >> 8;
@@ -1082,10 +1082,10 @@ static void exynos_dsi_read_from_fifo(struct exynos_dsi *dsi, · 37 unmodified lines
1082 switch (length) {1082 switch (length) {
1083 case 3:1083 case 3:
1084 payload[2] = (reg >> 16) & 0xff;1084 payload[2] = (reg >> 16) & 0xff;
1085 /* Fall through */1085 fallthrough;
1086 case 2:1086 case 2:
1087 payload[1] = (reg >> 8) & 0xff;1087 payload[1] = (reg >> 8) & 0xff;
1088 /* Fall through */1088 fallthrough;
1089 case 1:1089 case 1:
1090 payload[0] = reg & 0xff;1090 payload[0] = reg & 0xff;
1091 }1091 }
drivers/gpu/drm/exynos/exynos_drm_fbdev.c+1−1
@@ -92,7 +92,7 @@ static int exynos_drm_fbdev_update(struct drm_fb_helper *helper, · 91 unmodified lines
92 offset = fbi->var.xoffset * fb->format->cpp[0];92 offset = fbi->var.xoffset * fb->format->cpp[0];
93 offset += fbi->var.yoffset * fb->pitches[0];93 offset += fbi->var.yoffset * fb->pitches[0];
94 94
95 fbi->screen_base = exynos_gem->kvaddr + offset;95 fbi->screen_buffer = exynos_gem->kvaddr + offset;
96 fbi->screen_size = size;96 fbi->screen_size = size;
97 fbi->fix.smem_len = size;97 fbi->fix.smem_len = size;
98 98
drivers/gpu/drm/exynos/exynos_drm_gem.h+1−1
@@ -40,7 +40,7 @@ struct exynos_drm_gem { · 39 unmodified lines
40 unsigned int flags;40 unsigned int flags;
41 unsigned long size;41 unsigned long size;
42 void *cookie;42 void *cookie;
43 void __iomem *kvaddr;43 void *kvaddr;
44 dma_addr_t dma_addr;44 dma_addr_t dma_addr;
45 unsigned long dma_attrs;45 unsigned long dma_attrs;
46 struct sg_table *sgt;46 struct sg_table *sgt;
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c+3−3
@@ -101,19 +101,19 @@ static void fsl_dcu_drm_plane_atomic_update(struct drm_plane *plane, · 100 unmodified lines
101 break;101 break;
102 case DRM_FORMAT_ARGB8888:102 case DRM_FORMAT_ARGB8888:
103 alpha = DCU_LAYER_AB_WHOLE_FRAME;103 alpha = DCU_LAYER_AB_WHOLE_FRAME;
104 /* fall-through */104 fallthrough;
105 case DRM_FORMAT_XRGB8888:105 case DRM_FORMAT_XRGB8888:
106 bpp = FSL_DCU_ARGB8888;106 bpp = FSL_DCU_ARGB8888;
107 break;107 break;
108 case DRM_FORMAT_ARGB4444:108 case DRM_FORMAT_ARGB4444:
109 alpha = DCU_LAYER_AB_WHOLE_FRAME;109 alpha = DCU_LAYER_AB_WHOLE_FRAME;
110 /* fall-through */110 fallthrough;
111 case DRM_FORMAT_XRGB4444:111 case DRM_FORMAT_XRGB4444:
112 bpp = FSL_DCU_ARGB4444;112 bpp = FSL_DCU_ARGB4444;
113 break;113 break;
114 case DRM_FORMAT_ARGB1555:114 case DRM_FORMAT_ARGB1555:
115 alpha = DCU_LAYER_AB_WHOLE_FRAME;115 alpha = DCU_LAYER_AB_WHOLE_FRAME;
116 /* fall-through */116 fallthrough;
117 case DRM_FORMAT_XRGB1555:117 case DRM_FORMAT_XRGB1555:
118 bpp = FSL_DCU_ARGB1555;118 bpp = FSL_DCU_ARGB1555;
119 break;119 break;
drivers/gpu/drm/i915/display/icl_dsi.c+3−3
@@ -712,7 +712,7 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder, · 711 unmodified lines
712 switch (intel_dsi->pixel_format) {712 switch (intel_dsi->pixel_format) {
713 default:713 default:
714 MISSING_CASE(intel_dsi->pixel_format);714 MISSING_CASE(intel_dsi->pixel_format);
715 /* fallthrough */715 fallthrough;
716 case MIPI_DSI_FMT_RGB565:716 case MIPI_DSI_FMT_RGB565:
717 tmp |= PIX_FMT_RGB565;717 tmp |= PIX_FMT_RGB565;
718 break;718 break;
@@ -739,7 +739,7 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder, · 20 unmodified lines
739 switch (intel_dsi->video_mode_format) {739 switch (intel_dsi->video_mode_format) {
740 default:740 default:
741 MISSING_CASE(intel_dsi->video_mode_format);741 MISSING_CASE(intel_dsi->video_mode_format);
742 /* fallthrough */742 fallthrough;
743 case VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS:743 case VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS:
744 tmp |= VIDEO_MODE_SYNC_EVENT;744 tmp |= VIDEO_MODE_SYNC_EVENT;
745 break;745 break;
@@ -792,7 +792,7 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder, · 46 unmodified lines
792 switch (pipe) {792 switch (pipe) {
793 default:793 default:
794 MISSING_CASE(pipe);794 MISSING_CASE(pipe);
795 /* fallthrough */795 fallthrough;
796 case PIPE_A:796 case PIPE_A:
797 tmp |= TRANS_DDI_EDP_INPUT_A_ON;797 tmp |= TRANS_DDI_EDP_INPUT_A_ON;
798 break;798 break;
drivers/gpu/drm/i915/display/intel_bios.c+3−3
@@ -905,7 +905,7 @@ parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb) · 904 unmodified lines
905 drm_dbg_kms(&dev_priv->drm,905 drm_dbg_kms(&dev_priv->drm,
906 "VBT tp1 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",906 "VBT tp1 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
907 psr_table->tp1_wakeup_time);907 psr_table->tp1_wakeup_time);
908 /* fallthrough */908 fallthrough;
909 case 2:909 case 2:
910 dev_priv->vbt.psr.tp1_wakeup_time_us = 2500;910 dev_priv->vbt.psr.tp1_wakeup_time_us = 2500;
911 break;911 break;
@@ -925,7 +925,7 @@ parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb) · 13 unmodified lines
925 drm_dbg_kms(&dev_priv->drm,925 drm_dbg_kms(&dev_priv->drm,
926 "VBT tp2_tp3 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",926 "VBT tp2_tp3 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
927 psr_table->tp2_tp3_wakeup_time);927 psr_table->tp2_tp3_wakeup_time);
928 /* fallthrough */928 fallthrough;
929 case 2:929 case 2:
930 dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 2500;930 dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 2500;
931 break;931 break;
@@ -1775,7 +1775,7 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv, · 843 unmodified lines
1775 switch (child->hdmi_max_data_rate) {1775 switch (child->hdmi_max_data_rate) {
1776 default:1776 default:
1777 MISSING_CASE(child->hdmi_max_data_rate);1777 MISSING_CASE(child->hdmi_max_data_rate);
1778 /* fall through */1778 fallthrough;
1779 case HDMI_MAX_DATA_RATE_PLATFORM:1779 case HDMI_MAX_DATA_RATE_PLATFORM:
1780 max_tmds_clock = 0;1780 max_tmds_clock = 0;
1781 break;1781 break;
drivers/gpu/drm/i915/display/intel_cdclk.c+5−5
@@ -326,7 +326,7 @@ static void pnv_get_cdclk(struct drm_i915_private *dev_priv, · 325 unmodified lines
326 default:326 default:
327 drm_err(&dev_priv->drm,327 drm_err(&dev_priv->drm,
328 "Unknown pnv display core clock 0x%04x\n", gcfgc);328 "Unknown pnv display core clock 0x%04x\n", gcfgc);
329 /* fall through */329 fallthrough;
330 case GC_DISPLAY_CLOCK_133_MHZ_PNV:330 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
331 cdclk_config->cdclk = 133333;331 cdclk_config->cdclk = 133333;
332 break;332 break;
@@ -766,7 +766,7 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv, · 433 unmodified lines
766 switch (cdclk) {766 switch (cdclk) {
767 default:767 default:
768 MISSING_CASE(cdclk);768 MISSING_CASE(cdclk);
769 /* fall through */769 fallthrough;
770 case 337500:770 case 337500:
771 val |= LCPLL_CLK_FREQ_337_5_BDW;771 val |= LCPLL_CLK_FREQ_337_5_BDW;
772 break;772 break;
@@ -1042,7 +1042,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, · 269 unmodified lines
1042 drm_WARN_ON(&dev_priv->drm,1042 drm_WARN_ON(&dev_priv->drm,
1043 cdclk != dev_priv->cdclk.hw.bypass);1043 cdclk != dev_priv->cdclk.hw.bypass);
1044 drm_WARN_ON(&dev_priv->drm, vco != 0);1044 drm_WARN_ON(&dev_priv->drm, vco != 0);
1045 /* fall through */1045 fallthrough;
1046 case 308571:1046 case 308571:
1047 case 337500:1047 case 337500:
1048 freq_select = CDCLK_FREQ_337_308;1048 freq_select = CDCLK_FREQ_337_308;
@@ -1333,7 +1333,7 @@ static void icl_readout_refclk(struct drm_i915_private *dev_priv, · 284 unmodified lines
1333 switch (dssm) {1333 switch (dssm) {
1334 default:1334 default:
1335 MISSING_CASE(dssm);1335 MISSING_CASE(dssm);
1336 /* fall through */1336 fallthrough;
1337 case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:1337 case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:
1338 cdclk_config->ref = 24000;1338 cdclk_config->ref = 24000;
1339 break;1339 break;
@@ -1561,7 +1561,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, · 221 unmodified lines
1561 drm_WARN_ON(&dev_priv->drm,1561 drm_WARN_ON(&dev_priv->drm,
1562 cdclk != dev_priv->cdclk.hw.bypass);1562 cdclk != dev_priv->cdclk.hw.bypass);
1563 drm_WARN_ON(&dev_priv->drm, vco != 0);1563 drm_WARN_ON(&dev_priv->drm, vco != 0);
1564 /* fall through */1564 fallthrough;
1565 case 2:1565 case 2:
1566 divider = BXT_CDCLK_CD2X_DIV_SEL_1;1566 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1567 break;1567 break;
drivers/gpu/drm/i915/display/intel_combo_phy.c+5−5
@@ -52,7 +52,7 @@ cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy) · 51 unmodified lines
52 switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) {52 switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) {
53 default:53 default:
54 MISSING_CASE(val);54 MISSING_CASE(val);
55 /* fall through */55 fallthrough;
56 case VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0:56 case VOLTAGE_INFO_0_85V | PROCESS_INFO_DOT_0:
57 procmon = &cnl_procmon_values[PROCMON_0_85V_DOT_0];57 procmon = &cnl_procmon_values[PROCMON_0_85V_DOT_0];
58 break;58 break;
@@ -258,7 +258,7 @@ static bool phy_is_master(struct drm_i915_private *dev_priv, enum phy phy) · 199 unmodified lines
258static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,258static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
259 enum phy phy)259 enum phy phy)
260{260{
261 bool ret;261 bool ret = true;
262 u32 expected_val = 0;262 u32 expected_val = 0;
263 263
264 if (!icl_combo_phy_enabled(dev_priv, phy))264 if (!icl_combo_phy_enabled(dev_priv, phy))
@@ -276,7 +276,7 @@ static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv, · 11 unmodified lines
276 DCC_MODE_SELECT_CONTINUOSLY);276 DCC_MODE_SELECT_CONTINUOSLY);
277 }277 }
278 278
279 ret = cnl_verify_procmon_ref_values(dev_priv, phy);279 ret &= cnl_verify_procmon_ref_values(dev_priv, phy);
280 280
281 if (phy_is_master(dev_priv, phy)) {281 if (phy_is_master(dev_priv, phy)) {
282 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy),282 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy),
@@ -320,7 +320,7 @@ void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv, · 37 unmodified lines
320 break;320 break;
321 default:321 default:
322 MISSING_CASE(lane_count);322 MISSING_CASE(lane_count);
323 /* fall-through */323 fallthrough;
324 case 4:324 case 4:
325 lane_mask = PWR_UP_ALL_LANES;325 lane_mask = PWR_UP_ALL_LANES;
326 break;326 break;
@@ -337,7 +337,7 @@ void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv, · 10 unmodified lines
337 break;337 break;
338 default:338 default:
339 MISSING_CASE(lane_count);339 MISSING_CASE(lane_count);
340 /* fall-through */340 fallthrough;
341 case 4:341 case 4:
342 lane_mask = PWR_UP_ALL_LANES;342 lane_mask = PWR_UP_ALL_LANES;
343 break;343 break;
drivers/gpu/drm/i915/display/intel_ddi.c+2−2
@@ -1888,7 +1888,7 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, · 1887 unmodified lines
1888 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {1888 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1889 default:1889 default:
1890 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);1890 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
1891 /* fallthrough */1891 fallthrough;
1892 case TRANS_DDI_EDP_INPUT_A_ON:1892 case TRANS_DDI_EDP_INPUT_A_ON:
1893 case TRANS_DDI_EDP_INPUT_A_ONOFF:1893 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1894 *pipe_mask = BIT(PIPE_A);1894 *pipe_mask = BIT(PIPE_A);
@@ -4268,7 +4268,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder, · 2373 unmodified lines
4268 pipe_config->hdmi_scrambling = true;4268 pipe_config->hdmi_scrambling = true;
4269 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)4269 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
4270 pipe_config->hdmi_high_tmds_clock_ratio = true;4270 pipe_config->hdmi_high_tmds_clock_ratio = true;
4271 /* fall through */4271 fallthrough;
4272 case TRANS_DDI_MODE_SELECT_DVI:4272 case TRANS_DDI_MODE_SELECT_DVI:
4273 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);4273 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
4274 pipe_config->lane_count = 4;4274 pipe_config->lane_count = 4;
drivers/gpu/drm/i915/display/intel_display.c+11−11
@@ -2029,12 +2029,12 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane) · 2028 unmodified lines
2029 case I915_FORMAT_MOD_Y_TILED_CCS:2029 case I915_FORMAT_MOD_Y_TILED_CCS:
2030 if (is_ccs_plane(fb, color_plane))2030 if (is_ccs_plane(fb, color_plane))
2031 return 128;2031 return 128;
2032 /* fall through */2032 fallthrough;
2033 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:2033 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
2034 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:2034 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2035 if (is_ccs_plane(fb, color_plane))2035 if (is_ccs_plane(fb, color_plane))
2036 return 64;2036 return 64;
2037 /* fall through */2037 fallthrough;
2038 case I915_FORMAT_MOD_Y_TILED:2038 case I915_FORMAT_MOD_Y_TILED:
2039 if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))2039 if (IS_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv))
2040 return 128;2040 return 128;
@@ -2043,7 +2043,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane) · 2 unmodified lines
2043 case I915_FORMAT_MOD_Yf_TILED_CCS:2043 case I915_FORMAT_MOD_Yf_TILED_CCS:
2044 if (is_ccs_plane(fb, color_plane))2044 if (is_ccs_plane(fb, color_plane))
2045 return 128;2045 return 128;
2046 /* fall through */2046 fallthrough;
2047 case I915_FORMAT_MOD_Yf_TILED:2047 case I915_FORMAT_MOD_Yf_TILED:
2048 switch (cpp) {2048 switch (cpp) {
2049 case 1:2049 case 1:
@@ -2185,7 +2185,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb, · 135 unmodified lines
2185 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:2185 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2186 if (is_semiplanar_uv_plane(fb, color_plane))2186 if (is_semiplanar_uv_plane(fb, color_plane))
2187 return intel_tile_row_size(fb, color_plane);2187 return intel_tile_row_size(fb, color_plane);
2188 /* Fall-through */2188 fallthrough;
2189 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:2189 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
2190 return 16 * 1024;2190 return 16 * 1024;
2191 case I915_FORMAT_MOD_Y_TILED_CCS:2191 case I915_FORMAT_MOD_Y_TILED_CCS:
@@ -2194,7 +2194,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb, · 2 unmodified lines
2194 if (INTEL_GEN(dev_priv) >= 12 &&2194 if (INTEL_GEN(dev_priv) >= 12 &&
2195 is_semiplanar_uv_plane(fb, color_plane))2195 is_semiplanar_uv_plane(fb, color_plane))
2196 return intel_tile_row_size(fb, color_plane);2196 return intel_tile_row_size(fb, color_plane);
2197 /* Fall-through */2197 fallthrough;
2198 case I915_FORMAT_MOD_Yf_TILED:2198 case I915_FORMAT_MOD_Yf_TILED:
2199 return 1 * 1024 * 1024;2199 return 1 * 1024 * 1024;
2200 default:2200 default:
@@ -6211,7 +6211,7 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, · 4010 unmodified lines
6211 case DRM_FORMAT_ARGB16161616F:6211 case DRM_FORMAT_ARGB16161616F:
6212 if (INTEL_GEN(dev_priv) >= 11)6212 if (INTEL_GEN(dev_priv) >= 11)
6213 break;6213 break;
6214 /* fall through */6214 fallthrough;
6215 default:6215 default:
6216 drm_dbg_kms(&dev_priv->drm,6216 drm_dbg_kms(&dev_priv->drm,
6217 "[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",6217 "[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
@@ -10896,7 +10896,7 @@ static void hsw_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port, · 4678 unmodified lines
10896 break;10896 break;
10897 default:10897 default:
10898 MISSING_CASE(ddi_pll_sel);10898 MISSING_CASE(ddi_pll_sel);
10899 /* fall through */10899 fallthrough;
10900 case PORT_CLK_SEL_NONE:10900 case PORT_CLK_SEL_NONE:
10901 return;10901 return;
10902 }10902 }
@@ -10956,10 +10956,10 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc, · 53 unmodified lines
10956 drm_WARN(dev, 1,10956 drm_WARN(dev, 1,
10957 "unknown pipe linked to transcoder %s\n",10957 "unknown pipe linked to transcoder %s\n",
10958 transcoder_name(panel_transcoder));10958 transcoder_name(panel_transcoder));
10959 /* fall through */10959 fallthrough;
10960 case TRANS_DDI_EDP_INPUT_A_ONOFF:10960 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10961 force_thru = true;10961 force_thru = true;
10962 /* fall through */10962 fallthrough;
10963 case TRANS_DDI_EDP_INPUT_A_ON:10963 case TRANS_DDI_EDP_INPUT_A_ON:
10964 trans_pipe = PIPE_A;10964 trans_pipe = PIPE_A;
10965 break;10965 break;
@@ -13183,7 +13183,7 @@ static bool check_digital_port_conflicts(struct intel_atomic_state *state) · 2217 unmodified lines
13183 case INTEL_OUTPUT_DDI:13183 case INTEL_OUTPUT_DDI:
13184 if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev))))13184 if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev))))
13185 break;13185 break;
13186 /* else, fall through */13186 fallthrough;
13187 case INTEL_OUTPUT_DP:13187 case INTEL_OUTPUT_DP:
13188 case INTEL_OUTPUT_HDMI:13188 case INTEL_OUTPUT_HDMI:
13189 case INTEL_OUTPUT_EDP:13189 case INTEL_OUTPUT_EDP:
@@ -14930,7 +14930,7 @@ static int intel_atomic_check(struct drm_device *dev, · 1740 unmodified lines
14930 if (any_ms && !check_digital_port_conflicts(state)) {14930 if (any_ms && !check_digital_port_conflicts(state)) {
14931 drm_dbg_kms(&dev_priv->drm,14931 drm_dbg_kms(&dev_priv->drm,
14932 "rejecting conflicting digital port configuration\n");14932 "rejecting conflicting digital port configuration\n");
14933 ret = EINVAL;14933 ret = -EINVAL;
14934 goto fail;14934 goto fail;
14935 }14935 }
14936 14936
drivers/gpu/drm/i915/display/intel_display_debugfs.c+5−2
@@ -2044,9 +2044,12 @@ DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability); · 2043 unmodified lines
2044static int i915_lpsp_capability_show(struct seq_file *m, void *data)2044static int i915_lpsp_capability_show(struct seq_file *m, void *data)
2045{2045{
2046 struct drm_connector *connector = m->private;2046 struct drm_connector *connector = m->private;
2047 struct intel_encoder *encoder =
2048 intel_attached_encoder(to_intel_connector(connector));
2049 struct drm_i915_private *i915 = to_i915(connector->dev);2047 struct drm_i915_private *i915 = to_i915(connector->dev);
2048 struct intel_encoder *encoder;
2049
2050 encoder = intel_attached_encoder(to_intel_connector(connector));
2051 if (!encoder)
2052 return -ENODEV;
2050 2053
2051 if (connector->status != connector_status_connected)2054 if (connector->status != connector_status_connected)
2052 return -ENODEV;2055 return -ENODEV;
drivers/gpu/drm/i915/display/intel_display_power.c+7−7
@@ -4146,6 +4146,12 @@ static const struct i915_power_well_desc tgl_power_wells[] = { · 4145 unmodified lines
4146 .hsw.idx = TGL_PW_CTL_IDX_DDI_TC6,4146 .hsw.idx = TGL_PW_CTL_IDX_DDI_TC6,
4147 },4147 },
4148 },4148 },
4149 {
4150 .name = "TC cold off",
4151 .domains = TGL_TC_COLD_OFF_POWER_DOMAINS,
4152 .ops = &tgl_tc_cold_off_ops,
4153 .id = DISP_PW_ID_NONE,
4154 },
4149 {4155 {
4150 .name = "AUX A",4156 .name = "AUX A",
4151 .domains = TGL_AUX_A_IO_POWER_DOMAINS,4157 .domains = TGL_AUX_A_IO_POWER_DOMAINS,
@@ -4332,12 +4338,6 @@ static const struct i915_power_well_desc tgl_power_wells[] = { · 180 unmodified lines
4332 .hsw.irq_pipe_mask = BIT(PIPE_D),4338 .hsw.irq_pipe_mask = BIT(PIPE_D),
4333 },4339 },
4334 },4340 },
4335 {
4336 .name = "TC cold off",
4337 .domains = TGL_TC_COLD_OFF_POWER_DOMAINS,
4338 .ops = &tgl_tc_cold_off_ops,
4339 .id = DISP_PW_ID_NONE,
4340 },
4341};4341};
4342 4342
4343static const struct i915_power_well_desc rkl_power_wells[] = {4343static const struct i915_power_well_desc rkl_power_wells[] = {
@@ -5240,10 +5240,10 @@ struct buddy_page_mask { · 896 unmodified lines
5240};5240};
5241 5241
5242static const struct buddy_page_mask tgl_buddy_page_masks[] = {5242static const struct buddy_page_mask tgl_buddy_page_masks[] = {
5243 { .num_channels = 1, .type = INTEL_DRAM_LPDDR4, .page_mask = 0xE },
5244 { .num_channels = 1, .type = INTEL_DRAM_DDR4, .page_mask = 0xF },5243 { .num_channels = 1, .type = INTEL_DRAM_DDR4, .page_mask = 0xF },
5245 { .num_channels = 2, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x1C },5244 { .num_channels = 2, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x1C },
5246 { .num_channels = 2, .type = INTEL_DRAM_DDR4, .page_mask = 0x1F },5245 { .num_channels = 2, .type = INTEL_DRAM_DDR4, .page_mask = 0x1F },
5246 { .num_channels = 4, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x38 },
5247 {}5247 {}
5248};5248};
5249 5249
drivers/gpu/drm/i915/display/intel_dpll_mgr.c+4−4
@@ -892,7 +892,7 @@ static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv, · 891 unmodified lines
892 refclk = dev_priv->dpll.ref_clks.nssc;892 refclk = dev_priv->dpll.ref_clks.nssc;
893 break;893 break;
894 }894 }
895 /* fall through */895 fallthrough;
896 case WRPLL_REF_PCH_SSC:896 case WRPLL_REF_PCH_SSC:
897 /*897 /*
898 * We could calculate spread here, but our checking898 * We could calculate spread here, but our checking
@@ -2977,7 +2977,7 @@ static bool icl_calc_tbt_pll(struct intel_crtc_state *crtc_state, · 2078 unmodified lines
2977 switch (dev_priv->dpll.ref_clks.nssc) {2977 switch (dev_priv->dpll.ref_clks.nssc) {
2978 default:2978 default:
2979 MISSING_CASE(dev_priv->dpll.ref_clks.nssc);2979 MISSING_CASE(dev_priv->dpll.ref_clks.nssc);
2980 /* fall-through */2980 fallthrough;
2981 case 19200:2981 case 19200:
2982 *pll_params = tgl_tbt_pll_19_2MHz_values;2982 *pll_params = tgl_tbt_pll_19_2MHz_values;
2983 break;2983 break;
@@ -2992,7 +2992,7 @@ static bool icl_calc_tbt_pll(struct intel_crtc_state *crtc_state, · 8 unmodified lines
2992 switch (dev_priv->dpll.ref_clks.nssc) {2992 switch (dev_priv->dpll.ref_clks.nssc) {
2993 default:2993 default:
2994 MISSING_CASE(dev_priv->dpll.ref_clks.nssc);2994 MISSING_CASE(dev_priv->dpll.ref_clks.nssc);
2995 /* fall-through */2995 fallthrough;
2996 case 19200:2996 case 19200:
2997 case 38400:2997 case 38400:
2998 *pll_params = icl_tbt_pll_19_2MHz_values;2998 *pll_params = icl_tbt_pll_19_2MHz_values;
@@ -3120,7 +3120,7 @@ static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc, · 121 unmodified lines
3120 switch (div1) {3120 switch (div1) {
3121 default:3121 default:
3122 MISSING_CASE(div1);3122 MISSING_CASE(div1);
3123 /* fall through */3123 fallthrough;
3124 case 2:3124 case 2:
3125 hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2;3125 hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2;
3126 break;3126 break;
drivers/gpu/drm/i915/display/intel_hdcp.c+26−6
@@ -336,8 +336,10 @@ int intel_hdcp_validate_v_prime(struct intel_connector *connector, · 335 unmodified lines
336 336
337 /* Fill up the empty slots in sha_text and write it out */337 /* Fill up the empty slots in sha_text and write it out */
338 sha_empty = sizeof(sha_text) - sha_leftovers;338 sha_empty = sizeof(sha_text) - sha_leftovers;
339 for (j = 0; j < sha_empty; j++)339 for (j = 0; j < sha_empty; j++) {
340 sha_text |= ksv[j] << ((sizeof(sha_text) - j - 1) * 8);340 u8 off = ((sizeof(sha_text) - j - 1 - sha_leftovers) * 8);
341 sha_text |= ksv[j] << off;
342 }
341 343
342 ret = intel_write_sha_text(dev_priv, sha_text);344 ret = intel_write_sha_text(dev_priv, sha_text);
343 if (ret < 0)345 if (ret < 0)
@@ -435,7 +437,7 @@ int intel_hdcp_validate_v_prime(struct intel_connector *connector, · 91 unmodified lines
435 /* Write 32 bits of text */437 /* Write 32 bits of text */
436 intel_de_write(dev_priv, HDCP_REP_CTL,438 intel_de_write(dev_priv, HDCP_REP_CTL,
437 rep_ctl | HDCP_SHA1_TEXT_32);439 rep_ctl | HDCP_SHA1_TEXT_32);
438 sha_text |= bstatus[0] << 24 | bstatus[1] << 16;440 sha_text |= bstatus[0] << 8 | bstatus[1];
439 ret = intel_write_sha_text(dev_priv, sha_text);441 ret = intel_write_sha_text(dev_priv, sha_text);
440 if (ret < 0)442 if (ret < 0)
441 return ret;443 return ret;
@@ -450,17 +452,29 @@ int intel_hdcp_validate_v_prime(struct intel_connector *connector, · 8 unmodified lines
450 return ret;452 return ret;
451 sha_idx += sizeof(sha_text);453 sha_idx += sizeof(sha_text);
452 }454 }
455
456 /*
457 * Terminate the SHA-1 stream by hand. For the other leftover
458 * cases this is appended by the hardware.
459 */
460 intel_de_write(dev_priv, HDCP_REP_CTL,
461 rep_ctl | HDCP_SHA1_TEXT_32);
462 sha_text = DRM_HDCP_SHA1_TERMINATOR << 24;
463 ret = intel_write_sha_text(dev_priv, sha_text);
464 if (ret < 0)
465 return ret;
466 sha_idx += sizeof(sha_text);
453 } else if (sha_leftovers == 3) {467 } else if (sha_leftovers == 3) {
454 /* Write 32 bits of text */468 /* Write 32 bits of text (filled from LSB) */
455 intel_de_write(dev_priv, HDCP_REP_CTL,469 intel_de_write(dev_priv, HDCP_REP_CTL,
456 rep_ctl | HDCP_SHA1_TEXT_32);470 rep_ctl | HDCP_SHA1_TEXT_32);
457 sha_text |= bstatus[0] << 24;471 sha_text |= bstatus[0];
458 ret = intel_write_sha_text(dev_priv, sha_text);472 ret = intel_write_sha_text(dev_priv, sha_text);
459 if (ret < 0)473 if (ret < 0)
460 return ret;474 return ret;
461 sha_idx += sizeof(sha_text);475 sha_idx += sizeof(sha_text);
462 476
463 /* Write 8 bits of text, 24 bits of M0 */477 /* Write 8 bits of text (filled from LSB), 24 bits of M0 */
464 intel_de_write(dev_priv, HDCP_REP_CTL,478 intel_de_write(dev_priv, HDCP_REP_CTL,
465 rep_ctl | HDCP_SHA1_TEXT_8);479 rep_ctl | HDCP_SHA1_TEXT_8);
466 ret = intel_write_sha_text(dev_priv, bstatus[1]);480 ret = intel_write_sha_text(dev_priv, bstatus[1]);
@@ -781,6 +795,7 @@ static int _intel_hdcp_disable(struct intel_connector *connector) · 314 unmodified lines
781 struct intel_hdcp *hdcp = &connector->hdcp;795 struct intel_hdcp *hdcp = &connector->hdcp;
782 enum port port = dig_port->base.port;796 enum port port = dig_port->base.port;
783 enum transcoder cpu_transcoder = hdcp->cpu_transcoder;797 enum transcoder cpu_transcoder = hdcp->cpu_transcoder;
798 u32 repeater_ctl;
784 int ret;799 int ret;
785 800
786 drm_dbg_kms(&dev_priv->drm, "[%s:%d] HDCP is being disabled...\n",801 drm_dbg_kms(&dev_priv->drm, "[%s:%d] HDCP is being disabled...\n",
@@ -796,6 +811,11 @@ static int _intel_hdcp_disable(struct intel_connector *connector) · 9 unmodified lines
796 return -ETIMEDOUT;811 return -ETIMEDOUT;
797 }812 }
798 813
814 repeater_ctl = intel_hdcp_get_repeater_ctl(dev_priv, cpu_transcoder,
815 port);
816 intel_de_write(dev_priv, HDCP_REP_CTL,
817 intel_de_read(dev_priv, HDCP_REP_CTL) & ~repeater_ctl);
818
799 ret = hdcp->shim->toggle_signalling(dig_port, false);819 ret = hdcp->shim->toggle_signalling(dig_port, false);
800 if (ret) {820 if (ret) {
801 drm_err(&dev_priv->drm, "Failed to disable HDCP signalling\n");821 drm_err(&dev_priv->drm, "Failed to disable HDCP signalling\n");
drivers/gpu/drm/i915/display/intel_panel.c+1−1
@@ -229,7 +229,7 @@ int intel_pch_panel_fitting(struct intel_crtc_state *crtc_state, · 228 unmodified lines
229 case DRM_MODE_SCALE_NONE:229 case DRM_MODE_SCALE_NONE:
230 WARN_ON(adjusted_mode->crtc_hdisplay != crtc_state->pipe_src_w);230 WARN_ON(adjusted_mode->crtc_hdisplay != crtc_state->pipe_src_w);
231 WARN_ON(adjusted_mode->crtc_vdisplay != crtc_state->pipe_src_h);231 WARN_ON(adjusted_mode->crtc_vdisplay != crtc_state->pipe_src_h);
232 /* fall through */232 fallthrough;
233 case DRM_MODE_SCALE_FULLSCREEN:233 case DRM_MODE_SCALE_FULLSCREEN:
234 x = y = 0;234 x = y = 0;
235 width = adjusted_mode->crtc_hdisplay;235 width = adjusted_mode->crtc_hdisplay;
drivers/gpu/drm/i915/display/intel_sdvo.c+6−6
@@ -1531,7 +1531,7 @@ static void intel_sdvo_pre_enable(struct intel_atomic_state *state, · 1530 unmodified lines
1531 default:1531 default:
1532 drm_WARN(&dev_priv->drm, 1,1532 drm_WARN(&dev_priv->drm, 1,
1533 "unknown pixel multiplier specified\n");1533 "unknown pixel multiplier specified\n");
1534 /* fall through */1534 fallthrough;
1535 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;1535 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1536 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;1536 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1537 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;1537 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
@@ -2549,19 +2549,19 @@ intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo) · 1011 unmodified lines
2549 switch (sdvo->controlled_output) {2549 switch (sdvo->controlled_output) {
2550 case SDVO_OUTPUT_LVDS1:2550 case SDVO_OUTPUT_LVDS1:
2551 mask |= SDVO_OUTPUT_LVDS1;2551 mask |= SDVO_OUTPUT_LVDS1;
2552 /* fall through */2552 fallthrough;
2553 case SDVO_OUTPUT_LVDS0:2553 case SDVO_OUTPUT_LVDS0:
2554 mask |= SDVO_OUTPUT_LVDS0;2554 mask |= SDVO_OUTPUT_LVDS0;
2555 /* fall through */2555 fallthrough;
2556 case SDVO_OUTPUT_TMDS1:2556 case SDVO_OUTPUT_TMDS1:
2557 mask |= SDVO_OUTPUT_TMDS1;2557 mask |= SDVO_OUTPUT_TMDS1;
2558 /* fall through */2558 fallthrough;
2559 case SDVO_OUTPUT_TMDS0:2559 case SDVO_OUTPUT_TMDS0:
2560 mask |= SDVO_OUTPUT_TMDS0;2560 mask |= SDVO_OUTPUT_TMDS0;
2561 /* fall through */2561 fallthrough;
2562 case SDVO_OUTPUT_RGB1:2562 case SDVO_OUTPUT_RGB1:
2563 mask |= SDVO_OUTPUT_RGB1;2563 mask |= SDVO_OUTPUT_RGB1;
2564 /* fall through */2564 fallthrough;
2565 case SDVO_OUTPUT_RGB0:2565 case SDVO_OUTPUT_RGB0:
2566 mask |= SDVO_OUTPUT_RGB0;2566 mask |= SDVO_OUTPUT_RGB0;
2567 break;2567 break;
drivers/gpu/drm/i915/display/intel_sprite.c+11−11
@@ -2147,7 +2147,7 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, · 2146 unmodified lines
2147 case DRM_FORMAT_RGB565:2147 case DRM_FORMAT_RGB565:
2148 if (INTEL_GEN(dev_priv) >= 11)2148 if (INTEL_GEN(dev_priv) >= 11)
2149 break;2149 break;
2150 /* fall through */2150 fallthrough;
2151 case DRM_FORMAT_C8:2151 case DRM_FORMAT_C8:
2152 case DRM_FORMAT_XRGB16161616F:2152 case DRM_FORMAT_XRGB16161616F:
2153 case DRM_FORMAT_XBGR16161616F:2153 case DRM_FORMAT_XBGR16161616F:
@@ -2702,7 +2702,7 @@ static bool g4x_sprite_format_mod_supported(struct drm_plane *_plane, · 548 unmodified lines
2702 if (modifier == DRM_FORMAT_MOD_LINEAR ||2702 if (modifier == DRM_FORMAT_MOD_LINEAR ||
2703 modifier == I915_FORMAT_MOD_X_TILED)2703 modifier == I915_FORMAT_MOD_X_TILED)
2704 return true;2704 return true;
2705 /* fall through */2705 fallthrough;
2706 default:2706 default:
2707 return false;2707 return false;
2708 }2708 }
@@ -2733,7 +2733,7 @@ static bool snb_sprite_format_mod_supported(struct drm_plane *_plane, · 24 unmodified lines
2733 if (modifier == DRM_FORMAT_MOD_LINEAR ||2733 if (modifier == DRM_FORMAT_MOD_LINEAR ||
2734 modifier == I915_FORMAT_MOD_X_TILED)2734 modifier == I915_FORMAT_MOD_X_TILED)
2735 return true;2735 return true;
2736 /* fall through */2736 fallthrough;
2737 default:2737 default:
2738 return false;2738 return false;
2739 }2739 }
@@ -2768,7 +2768,7 @@ static bool vlv_sprite_format_mod_supported(struct drm_plane *_plane, · 28 unmodified lines
2768 if (modifier == DRM_FORMAT_MOD_LINEAR ||2768 if (modifier == DRM_FORMAT_MOD_LINEAR ||
2769 modifier == I915_FORMAT_MOD_X_TILED)2769 modifier == I915_FORMAT_MOD_X_TILED)
2770 return true;2770 return true;
2771 /* fall through */2771 fallthrough;
2772 default:2772 default:
2773 return false;2773 return false;
2774 }2774 }
@@ -2801,7 +2801,7 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane, · 26 unmodified lines
2801 case DRM_FORMAT_ABGR8888:2801 case DRM_FORMAT_ABGR8888:
2802 if (is_ccs_modifier(modifier))2802 if (is_ccs_modifier(modifier))
2803 return true;2803 return true;
2804 /* fall through */2804 fallthrough;
2805 case DRM_FORMAT_RGB565:2805 case DRM_FORMAT_RGB565:
2806 case DRM_FORMAT_XRGB2101010:2806 case DRM_FORMAT_XRGB2101010:
2807 case DRM_FORMAT_XBGR2101010:2807 case DRM_FORMAT_XBGR2101010:
@@ -2819,7 +2819,7 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane, · 11 unmodified lines
2819 case DRM_FORMAT_XVYU2101010:2819 case DRM_FORMAT_XVYU2101010:
2820 if (modifier == I915_FORMAT_MOD_Yf_TILED)2820 if (modifier == I915_FORMAT_MOD_Yf_TILED)
2821 return true;2821 return true;
2822 /* fall through */2822 fallthrough;
2823 case DRM_FORMAT_C8:2823 case DRM_FORMAT_C8:
2824 case DRM_FORMAT_XBGR16161616F:2824 case DRM_FORMAT_XBGR16161616F:
2825 case DRM_FORMAT_ABGR16161616F:2825 case DRM_FORMAT_ABGR16161616F:
@@ -2834,7 +2834,7 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane, · 8 unmodified lines
2834 modifier == I915_FORMAT_MOD_X_TILED ||2834 modifier == I915_FORMAT_MOD_X_TILED ||
2835 modifier == I915_FORMAT_MOD_Y_TILED)2835 modifier == I915_FORMAT_MOD_Y_TILED)
2836 return true;2836 return true;
2837 /* fall through */2837 fallthrough;
2838 default:2838 default:
2839 return false;2839 return false;
2840 }2840 }
@@ -2860,7 +2860,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane, · 19 unmodified lines
2860 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:2860 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
2861 if (!gen12_plane_supports_mc_ccs(dev_priv, plane->id))2861 if (!gen12_plane_supports_mc_ccs(dev_priv, plane->id))
2862 return false;2862 return false;
2863 /* fall through */2863 fallthrough;
2864 case DRM_FORMAT_MOD_LINEAR:2864 case DRM_FORMAT_MOD_LINEAR:
2865 case I915_FORMAT_MOD_X_TILED:2865 case I915_FORMAT_MOD_X_TILED:
2866 case I915_FORMAT_MOD_Y_TILED:2866 case I915_FORMAT_MOD_Y_TILED:
@@ -2877,7 +2877,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane, · 10 unmodified lines
2877 case DRM_FORMAT_ABGR8888:2877 case DRM_FORMAT_ABGR8888:
2878 if (is_ccs_modifier(modifier))2878 if (is_ccs_modifier(modifier))
2879 return true;2879 return true;
2880 /* fall through */2880 fallthrough;
2881 case DRM_FORMAT_YUYV:2881 case DRM_FORMAT_YUYV:
2882 case DRM_FORMAT_YVYU:2882 case DRM_FORMAT_YVYU:
2883 case DRM_FORMAT_UYVY:2883 case DRM_FORMAT_UYVY:
@@ -2889,7 +2889,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane, · 5 unmodified lines
2889 case DRM_FORMAT_P016:2889 case DRM_FORMAT_P016:
2890 if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)2890 if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)
2891 return true;2891 return true;
2892 /* fall through */2892 fallthrough;
2893 case DRM_FORMAT_RGB565:2893 case DRM_FORMAT_RGB565:
2894 case DRM_FORMAT_XRGB2101010:2894 case DRM_FORMAT_XRGB2101010:
2895 case DRM_FORMAT_XBGR2101010:2895 case DRM_FORMAT_XBGR2101010:
@@ -2910,7 +2910,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane, · 14 unmodified lines
2910 modifier == I915_FORMAT_MOD_X_TILED ||2910 modifier == I915_FORMAT_MOD_X_TILED ||
2911 modifier == I915_FORMAT_MOD_Y_TILED)2911 modifier == I915_FORMAT_MOD_Y_TILED)
2912 return true;2912 return true;
2913 /* fall through */2913 fallthrough;
2914 default:2914 default:
2915 return false;2915 return false;
2916 }2916 }
drivers/gpu/drm/i915/display/intel_tc.c+1−1
@@ -159,7 +159,7 @@ int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port) · 158 unmodified lines
159 switch (lane_mask) {159 switch (lane_mask) {
160 default:160 default:
161 MISSING_CASE(lane_mask);161 MISSING_CASE(lane_mask);
162 /* fall-through */162 fallthrough;
163 case 0x1:163 case 0x1:
164 case 0x2:164 case 0x2:
165 case 0x4:165 case 0x4:
drivers/gpu/drm/i915/gem/i915_gem_mman.c+1−1
@@ -209,7 +209,7 @@ static vm_fault_t i915_error_to_vmf_fault(int err) · 208 unmodified lines
209 switch (err) {209 switch (err) {
210 default:210 default:
211 WARN_ONCE(err, "unhandled error in %s: %i\n", __func__, err);211 WARN_ONCE(err, "unhandled error in %s: %i\n", __func__, err);
212 /* fallthrough */212 fallthrough;
213 case -EIO: /* shmemfs failure from swap device */213 case -EIO: /* shmemfs failure from swap device */
214 case -EFAULT: /* purged object */214 case -EFAULT: /* purged object */
215 case -ENODEV: /* bad object, how did you get here! */215 case -ENODEV: /* bad object, how did you get here! */
drivers/gpu/drm/i915/gem/i915_gem_pages.c+1−1
@@ -276,7 +276,7 @@ static void *i915_gem_object_map(struct drm_i915_gem_object *obj, · 275 unmodified lines
276 switch (type) {276 switch (type) {
277 default:277 default:
278 MISSING_CASE(type);278 MISSING_CASE(type);
279 /* fallthrough - to use PAGE_KERNEL anyway */279 fallthrough; /* to use PAGE_KERNEL anyway */
280 case I915_MAP_WB:280 case I915_MAP_WB:
281 pgprot = PAGE_KERNEL;281 pgprot = PAGE_KERNEL;
282 break;282 break;
drivers/gpu/drm/i915/gem/i915_gem_stolen.c+3−3
@@ -249,7 +249,7 @@ static void vlv_get_stolen_reserved(struct drm_i915_private *i915, · 248 unmodified lines
249 switch (reg_val & GEN7_STOLEN_RESERVED_SIZE_MASK) {249 switch (reg_val & GEN7_STOLEN_RESERVED_SIZE_MASK) {
250 default:250 default:
251 MISSING_CASE(reg_val & GEN7_STOLEN_RESERVED_SIZE_MASK);251 MISSING_CASE(reg_val & GEN7_STOLEN_RESERVED_SIZE_MASK);
252 /* fall through */252 fallthrough;
253 case GEN7_STOLEN_RESERVED_1M:253 case GEN7_STOLEN_RESERVED_1M:
254 *size = 1024 * 1024;254 *size = 1024 * 1024;
255 break;255 break;
@@ -416,7 +416,7 @@ static int i915_gem_init_stolen(struct drm_i915_private *i915) · 160 unmodified lines
416 case 4:416 case 4:
417 if (!IS_G4X(i915))417 if (!IS_G4X(i915))
418 break;418 break;
419 /* fall through */419 fallthrough;
420 case 5:420 case 5:
421 g4x_get_stolen_reserved(i915, uncore,421 g4x_get_stolen_reserved(i915, uncore,
422 &reserved_base, &reserved_size);422 &reserved_base, &reserved_size);
@@ -445,7 +445,7 @@ static int i915_gem_init_stolen(struct drm_i915_private *i915) · 22 unmodified lines
445 break;445 break;
446 default:446 default:
447 MISSING_CASE(INTEL_GEN(i915));447 MISSING_CASE(INTEL_GEN(i915));
448 /* fall-through */448 fallthrough;
449 case 11:449 case 11:
450 case 12:450 case 12:
451 icl_get_stolen_reserved(i915, uncore,451 icl_get_stolen_reserved(i915, uncore,
drivers/gpu/drm/i915/gem/i915_gem_userptr.c+0−8
@@ -596,14 +596,6 @@ static int i915_gem_userptr_get_pages(struct drm_i915_gem_object *obj) · 595 unmodified lines
596 GFP_KERNEL |596 GFP_KERNEL |
597 __GFP_NORETRY |597 __GFP_NORETRY |
598 __GFP_NOWARN);598 __GFP_NOWARN);
599 /*
600 * Using __get_user_pages_fast() with a read-only
601 * access is questionable. A read-only page may be
602 * COW-broken, and then this might end up giving
603 * the wrong side of the COW..
604 *
605 * We may or may not care.
606 */
607 if (pvec) {599 if (pvec) {
608 /* defer to worker if malloc fails */600 /* defer to worker if malloc fails */
609 if (!i915_gem_object_is_readonly(obj))601 if (!i915_gem_object_is_readonly(obj))
drivers/gpu/drm/i915/gt/intel_engine_cs.c+1−1
@@ -213,7 +213,7 @@ u32 intel_engine_context_size(struct intel_gt *gt, u8 class) · 212 unmodified lines
213 break;213 break;
214 default:214 default:
215 MISSING_CASE(class);215 MISSING_CASE(class);
216 /* fall through */216 fallthrough;
217 case VIDEO_DECODE_CLASS:217 case VIDEO_DECODE_CLASS:
218 case VIDEO_ENHANCEMENT_CLASS:218 case VIDEO_ENHANCEMENT_CLASS:
219 case COPY_ENGINE_CLASS:219 case COPY_ENGINE_CLASS:
drivers/gpu/drm/i915/gt/intel_ggtt.c+1−1
@@ -1437,7 +1437,7 @@ i915_get_ggtt_vma_pages(struct i915_vma *vma) · 1436 unmodified lines
1437 switch (vma->ggtt_view.type) {1437 switch (vma->ggtt_view.type) {
1438 default:1438 default:
1439 GEM_BUG_ON(vma->ggtt_view.type);1439 GEM_BUG_ON(vma->ggtt_view.type);
1440 /* fall through */1440 fallthrough;
1441 case I915_GGTT_VIEW_NORMAL:1441 case I915_GGTT_VIEW_NORMAL:
1442 vma->pages = vma->obj->mm.pages;1442 vma->pages = vma->obj->mm.pages;
1443 return 0;1443 return 0;
drivers/gpu/drm/i915/gt/intel_ring_submission.c+1−1
@@ -100,7 +100,7 @@ static void set_hwsp(struct intel_engine_cs *engine, u32 offset) · 99 unmodified lines
100 */100 */
101 default:101 default:
102 GEM_BUG_ON(engine->id);102 GEM_BUG_ON(engine->id);
103 /* fallthrough */103 fallthrough;
104 case RCS0:104 case RCS0:
105 hwsp = RENDER_HWS_PGA_GEN7;105 hwsp = RENDER_HWS_PGA_GEN7;
106 break;106 break;
drivers/gpu/drm/i915/gvt/cfg_space.c+24−0
@@ -70,6 +70,7 @@ static void vgpu_pci_cfg_mem_write(struct intel_vgpu *vgpu, unsigned int off, · 69 unmodified lines
70{70{
71 u8 *cfg_base = vgpu_cfg_space(vgpu);71 u8 *cfg_base = vgpu_cfg_space(vgpu);
72 u8 mask, new, old;72 u8 mask, new, old;
73 pci_power_t pwr;
73 int i = 0;74 int i = 0;
74 75
75 for (; i < bytes && (off + i < sizeof(pci_cfg_space_rw_bmp)); i++) {76 for (; i < bytes && (off + i < sizeof(pci_cfg_space_rw_bmp)); i++) {
@@ -91,6 +92,15 @@ static void vgpu_pci_cfg_mem_write(struct intel_vgpu *vgpu, unsigned int off, · 15 unmodified lines
91 /* For other configuration space directly copy as it is. */92 /* For other configuration space directly copy as it is. */
92 if (i < bytes)93 if (i < bytes)
93 memcpy(cfg_base + off + i, src + i, bytes - i);94 memcpy(cfg_base + off + i, src + i, bytes - i);
95
96 if (off == vgpu->cfg_space.pmcsr_off && vgpu->cfg_space.pmcsr_off) {
97 pwr = (pci_power_t __force)(*(u16*)(&vgpu_cfg_space(vgpu)[off])
98 & PCI_PM_CTRL_STATE_MASK);
99 if (pwr == PCI_D3hot)
100 vgpu->d3_entered = true;
101 gvt_dbg_core("vgpu-%d power status changed to %d\n",
102 vgpu->id, pwr);
103 }
94}104}
95 105
96/**106/**
@@ -366,6 +376,7 @@ void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu, · 269 unmodified lines
366 struct intel_gvt *gvt = vgpu->gvt;376 struct intel_gvt *gvt = vgpu->gvt;
367 const struct intel_gvt_device_info *info = &gvt->device_info;377 const struct intel_gvt_device_info *info = &gvt->device_info;
368 u16 *gmch_ctl;378 u16 *gmch_ctl;
379 u8 next;
369 380
370 memcpy(vgpu_cfg_space(vgpu), gvt->firmware.cfg_space,381 memcpy(vgpu_cfg_space(vgpu), gvt->firmware.cfg_space,
371 info->cfg_space_size);382 info->cfg_space_size);
@@ -401,6 +412,19 @@ void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu, · 29 unmodified lines
401 pci_resource_len(gvt->gt->i915->drm.pdev, 2);412 pci_resource_len(gvt->gt->i915->drm.pdev, 2);
402 413
403 memset(vgpu_cfg_space(vgpu) + PCI_ROM_ADDRESS, 0, 4);414 memset(vgpu_cfg_space(vgpu) + PCI_ROM_ADDRESS, 0, 4);
415
416 /* PM Support */
417 vgpu->cfg_space.pmcsr_off = 0;
418 if (vgpu_cfg_space(vgpu)[PCI_STATUS] & PCI_STATUS_CAP_LIST) {
419 next = vgpu_cfg_space(vgpu)[PCI_CAPABILITY_LIST];
420 do {
421 if (vgpu_cfg_space(vgpu)[next + PCI_CAP_LIST_ID] == PCI_CAP_ID_PM) {
422 vgpu->cfg_space.pmcsr_off = next + PCI_PM_CTRL;
423 break;
424 }
425 next = vgpu_cfg_space(vgpu)[next + PCI_CAP_LIST_NEXT];
426 } while (next);
427 }
404}428}
405 429
406/**430/**
drivers/gpu/drm/i915/gvt/gtt.c+1−1
@@ -2501,7 +2501,7 @@ int intel_vgpu_init_gtt(struct intel_vgpu *vgpu) · 2500 unmodified lines
2501 return create_scratch_page_tree(vgpu);2501 return create_scratch_page_tree(vgpu);
2502}2502}
2503 2503
2504static void intel_vgpu_destroy_all_ppgtt_mm(struct intel_vgpu *vgpu)2504void intel_vgpu_destroy_all_ppgtt_mm(struct intel_vgpu *vgpu)
2505{2505{
2506 struct list_head *pos, *n;2506 struct list_head *pos, *n;
2507 struct intel_vgpu_mm *mm;2507 struct intel_vgpu_mm *mm;
drivers/gpu/drm/i915/gvt/gtt.h+2−0
@@ -279,4 +279,6 @@ int intel_vgpu_emulate_ggtt_mmio_read(struct intel_vgpu *vgpu, · 278 unmodified lines
279int intel_vgpu_emulate_ggtt_mmio_write(struct intel_vgpu *vgpu,279int intel_vgpu_emulate_ggtt_mmio_write(struct intel_vgpu *vgpu,
280 unsigned int off, void *p_data, unsigned int bytes);280 unsigned int off, void *p_data, unsigned int bytes);
281 281
282void intel_vgpu_destroy_all_ppgtt_mm(struct intel_vgpu *vgpu);
283
282#endif /* _GVT_GTT_H_ */284#endif /* _GVT_GTT_H_ */
drivers/gpu/drm/i915/gvt/gvt.h+3−0
@@ -106,6 +106,7 @@ struct intel_vgpu_pci_bar { · 105 unmodified lines
106struct intel_vgpu_cfg_space {106struct intel_vgpu_cfg_space {
107 unsigned char virtual_cfg_space[PCI_CFG_SPACE_EXP_SIZE];107 unsigned char virtual_cfg_space[PCI_CFG_SPACE_EXP_SIZE];
108 struct intel_vgpu_pci_bar bar[INTEL_GVT_MAX_BAR_NUM];108 struct intel_vgpu_pci_bar bar[INTEL_GVT_MAX_BAR_NUM];
109 u32 pmcsr_off;
109};110};
110 111
111#define vgpu_cfg_space(vgpu) ((vgpu)->cfg_space.virtual_cfg_space)112#define vgpu_cfg_space(vgpu) ((vgpu)->cfg_space.virtual_cfg_space)
@@ -198,6 +199,8 @@ struct intel_vgpu { · 86 unmodified lines
198 struct intel_vgpu_submission submission;199 struct intel_vgpu_submission submission;
199 struct radix_tree_root page_track_tree;200 struct radix_tree_root page_track_tree;
200 u32 hws_pga[I915_NUM_ENGINES];201 u32 hws_pga[I915_NUM_ENGINES];
202 /* Set on PCI_D3, reset on DMLR, not reflecting the actual PM state */
203 bool d3_entered;
201 204
202 struct dentry *debugfs;205 struct dentry *debugfs;
203 206
drivers/gpu/drm/i915/gvt/handlers.c+1−1
@@ -1226,7 +1226,7 @@ static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification) · 1225 unmodified lines
1226 switch (notification) {1226 switch (notification) {
1227 case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE:1227 case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE:
1228 root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY;1228 root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY;
1229 /* fall through */1229 fallthrough;
1230 case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE:1230 case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE:
1231 mm = intel_vgpu_get_ppgtt_mm(vgpu, root_entry_type, pdps);1231 mm = intel_vgpu_get_ppgtt_mm(vgpu, root_entry_type, pdps);
1232 return PTR_ERR_OR_ZERO(mm);1232 return PTR_ERR_OR_ZERO(mm);
drivers/gpu/drm/i915/gvt/vgpu.c+17−3
@@ -257,6 +257,7 @@ void intel_gvt_release_vgpu(struct intel_vgpu *vgpu) · 256 unmodified lines
257 intel_gvt_deactivate_vgpu(vgpu);257 intel_gvt_deactivate_vgpu(vgpu);
258 258
259 mutex_lock(&vgpu->vgpu_lock);259 mutex_lock(&vgpu->vgpu_lock);
260 vgpu->d3_entered = false;
260 intel_vgpu_clean_workloads(vgpu, ALL_ENGINES);261 intel_vgpu_clean_workloads(vgpu, ALL_ENGINES);
261 intel_vgpu_dmabuf_cleanup(vgpu);262 intel_vgpu_dmabuf_cleanup(vgpu);
262 mutex_unlock(&vgpu->vgpu_lock);263 mutex_unlock(&vgpu->vgpu_lock);
@@ -393,6 +394,7 @@ static struct intel_vgpu *__intel_gvt_create_vgpu(struct intel_gvt *gvt, · 130 unmodified lines
393 INIT_RADIX_TREE(&vgpu->page_track_tree, GFP_KERNEL);394 INIT_RADIX_TREE(&vgpu->page_track_tree, GFP_KERNEL);
394 idr_init(&vgpu->object_idr);395 idr_init(&vgpu->object_idr);
395 intel_vgpu_init_cfg_space(vgpu, param->primary);396 intel_vgpu_init_cfg_space(vgpu, param->primary);
397 vgpu->d3_entered = false;
396 398
397 ret = intel_vgpu_init_mmio(vgpu);399 ret = intel_vgpu_init_mmio(vgpu);
398 if (ret)400 if (ret)
@@ -557,10 +559,15 @@ void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr, · 158 unmodified lines
557 /* full GPU reset or device model level reset */559 /* full GPU reset or device model level reset */
558 if (engine_mask == ALL_ENGINES || dmlr) {560 if (engine_mask == ALL_ENGINES || dmlr) {
559 intel_vgpu_select_submission_ops(vgpu, ALL_ENGINES, 0);561 intel_vgpu_select_submission_ops(vgpu, ALL_ENGINES, 0);
560 intel_vgpu_invalidate_ppgtt(vgpu);562 if (engine_mask == ALL_ENGINES)
563 intel_vgpu_invalidate_ppgtt(vgpu);
561 /*fence will not be reset during virtual reset */564 /*fence will not be reset during virtual reset */
562 if (dmlr) {565 if (dmlr) {
563 intel_vgpu_reset_gtt(vgpu);566 if(!vgpu->d3_entered) {
567 intel_vgpu_invalidate_ppgtt(vgpu);
568 intel_vgpu_destroy_all_ppgtt_mm(vgpu);
569 }
570 intel_vgpu_reset_ggtt(vgpu, true);
564 intel_vgpu_reset_resource(vgpu);571 intel_vgpu_reset_resource(vgpu);
565 }572 }
566 573
@@ -572,7 +579,14 @@ void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr, · 5 unmodified lines
572 intel_vgpu_reset_cfg_space(vgpu);579 intel_vgpu_reset_cfg_space(vgpu);
573 /* only reset the failsafe mode when dmlr reset */580 /* only reset the failsafe mode when dmlr reset */
574 vgpu->failsafe = false;581 vgpu->failsafe = false;
575 vgpu->pv_notified = false;582 /*
583 * PCI_D0 is set before dmlr, so reset d3_entered here
584 * after done using.
585 */
586 if(vgpu->d3_entered)
587 vgpu->d3_entered = false;
588 else
589 vgpu->pv_notified = false;
576 }590 }
577 }591 }
578 592
drivers/gpu/drm/i915/i915_cmd_parser.c+10−4
@@ -1204,6 +1204,12 @@ static u32 *copy_batch(struct drm_i915_gem_object *dst_obj, · 1203 unmodified lines
1204 return dst;1204 return dst;
1205}1205}
1206 1206
1207static inline bool cmd_desc_is(const struct drm_i915_cmd_descriptor * const desc,
1208 const u32 cmd)
1209{
1210 return desc->cmd.value == (cmd & desc->cmd.mask);
1211}
1212
1207static bool check_cmd(const struct intel_engine_cs *engine,1213static bool check_cmd(const struct intel_engine_cs *engine,
1208 const struct drm_i915_cmd_descriptor *desc,1214 const struct drm_i915_cmd_descriptor *desc,
1209 const u32 *cmd, u32 length)1215 const u32 *cmd, u32 length)
@@ -1242,19 +1248,19 @@ static bool check_cmd(const struct intel_engine_cs *engine, · 32 unmodified lines
1242 * allowed mask/value pair given in the whitelist entry.1248 * allowed mask/value pair given in the whitelist entry.
1243 */1249 */
1244 if (reg->mask) {1250 if (reg->mask) {
1245 if (desc->cmd.value == MI_LOAD_REGISTER_MEM) {1251 if (cmd_desc_is(desc, MI_LOAD_REGISTER_MEM)) {
1246 DRM_DEBUG("CMD: Rejected LRM to masked register 0x%08X\n",1252 DRM_DEBUG("CMD: Rejected LRM to masked register 0x%08X\n",
1247 reg_addr);1253 reg_addr);
1248 return false;1254 return false;
1249 }1255 }
1250 1256
1251 if (desc->cmd.value == MI_LOAD_REGISTER_REG) {1257 if (cmd_desc_is(desc, MI_LOAD_REGISTER_REG)) {
1252 DRM_DEBUG("CMD: Rejected LRR to masked register 0x%08X\n",1258 DRM_DEBUG("CMD: Rejected LRR to masked register 0x%08X\n",
1253 reg_addr);1259 reg_addr);
1254 return false;1260 return false;
1255 }1261 }
1256 1262
1257 if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1) &&1263 if (cmd_desc_is(desc, MI_LOAD_REGISTER_IMM(1)) &&
1258 (offset + 2 > length ||1264 (offset + 2 > length ||
1259 (cmd[offset + 1] & reg->mask) != reg->value)) {1265 (cmd[offset + 1] & reg->mask) != reg->value)) {
1260 DRM_DEBUG("CMD: Rejected LRI to masked register 0x%08X\n",1266 DRM_DEBUG("CMD: Rejected LRI to masked register 0x%08X\n",
@@ -1478,7 +1484,7 @@ int intel_engine_cmd_parser(struct intel_engine_cs *engine, · 217 unmodified lines
1478 break;1484 break;
1479 }1485 }
1480 1486
1481 if (desc->cmd.value == MI_BATCH_BUFFER_START) {1487 if (cmd_desc_is(desc, MI_BATCH_BUFFER_START)) {
1482 ret = check_bbstart(cmd, offset, length, batch_length,1488 ret = check_bbstart(cmd, offset, length, batch_length,
1483 batch_addr, shadow_addr,1489 batch_addr, shadow_addr,
1484 jump_whitelist);1490 jump_whitelist);
drivers/gpu/drm/i915/i915_gpu_error.c+1−1
@@ -1159,7 +1159,7 @@ static void engine_record_registers(struct intel_engine_coredump *ee) · 1158 unmodified lines
1159 switch (engine->id) {1159 switch (engine->id) {
1160 default:1160 default:
1161 MISSING_CASE(engine->id);1161 MISSING_CASE(engine->id);
1162 /* fall through */1162 fallthrough;
1163 case RCS0:1163 case RCS0:
1164 mmio = RENDER_HWS_PGA_GEN7;1164 mmio = RENDER_HWS_PGA_GEN7;
1165 break;1165 break;
drivers/gpu/drm/i915/i915_pmu.c+3−6
@@ -445,8 +445,6 @@ static void i915_pmu_event_destroy(struct perf_event *event) · 444 unmodified lines
445 container_of(event->pmu, typeof(*i915), pmu.base);445 container_of(event->pmu, typeof(*i915), pmu.base);
446 446
447 drm_WARN_ON(&i915->drm, event->parent);447 drm_WARN_ON(&i915->drm, event->parent);
448
449 module_put(THIS_MODULE);
450}448}
451 449
452static int450static int
@@ -476,7 +474,7 @@ config_status(struct drm_i915_private *i915, u64 config) · 23 unmodified lines
476 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))474 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
477 /* Requires a mutex for sampling! */475 /* Requires a mutex for sampling! */
478 return -ENODEV;476 return -ENODEV;
479 /* Fall-through. */477 fallthrough;
480 case I915_PMU_REQUESTED_FREQUENCY:478 case I915_PMU_REQUESTED_FREQUENCY:
481 if (INTEL_GEN(i915) < 6)479 if (INTEL_GEN(i915) < 6)
482 return -ENODEV;480 return -ENODEV;
@@ -538,10 +536,8 @@ static int i915_pmu_event_init(struct perf_event *event) · 55 unmodified lines
538 if (ret)536 if (ret)
539 return ret;537 return ret;
540 538
541 if (!event->parent) {539 if (!event->parent)
542 __module_get(THIS_MODULE);
543 event->destroy = i915_pmu_event_destroy;540 event->destroy = i915_pmu_event_destroy;
544 }
545 541
546 return 0;542 return 0;
547}543}
@@ -1130,6 +1126,7 @@ void i915_pmu_register(struct drm_i915_private *i915) · 582 unmodified lines
1130 if (!pmu->base.attr_groups)1126 if (!pmu->base.attr_groups)
1131 goto err_attr;1127 goto err_attr;
1132 1128
1129 pmu->base.module = THIS_MODULE;
1133 pmu->base.task_ctx_nr = perf_invalid_context;1130 pmu->base.task_ctx_nr = perf_invalid_context;
1134 pmu->base.event_init = i915_pmu_event_init;1131 pmu->base.event_init = i915_pmu_event_init;
1135 pmu->base.add = i915_pmu_event_add;1132 pmu->base.add = i915_pmu_event_add;
drivers/gpu/drm/i915/selftests/i915_buddy.c+10−8
@@ -8,8 +8,6 @@ · 7 unmodified lines
8#include "../i915_selftest.h"8#include "../i915_selftest.h"
9#include "i915_random.h"9#include "i915_random.h"
10 10
11#define SZ_8G (1ULL << 33)
12
13static void __igt_dump_block(struct i915_buddy_mm *mm,11static void __igt_dump_block(struct i915_buddy_mm *mm,
14 struct i915_buddy_block *block,12 struct i915_buddy_block *block,
15 bool buddy)13 bool buddy)
@@ -281,18 +279,22 @@ static int igt_check_mm(struct i915_buddy_mm *mm) · 265 unmodified lines
281static void igt_mm_config(u64 *size, u64 *chunk_size)279static void igt_mm_config(u64 *size, u64 *chunk_size)
282{280{
283 I915_RND_STATE(prng);281 I915_RND_STATE(prng);
284 u64 s, ms;282 u32 s, ms;
285 283
286 /* Nothing fancy, just try to get an interesting bit pattern */284 /* Nothing fancy, just try to get an interesting bit pattern */
287 285
288 prandom_seed_state(&prng, i915_selftest.random_seed);286 prandom_seed_state(&prng, i915_selftest.random_seed);
289 287
290 s = i915_prandom_u64_state(&prng) & (SZ_8G - 1);288 /* Let size be a random number of pages up to 8 GB (2M pages) */
291 ms = BIT_ULL(12 + (prandom_u32_state(&prng) % ilog2(s >> 12)));289 s = 1 + i915_prandom_u32_max_state((BIT(33 - 12)) - 1, &prng);
292 s = max(s & -ms, ms);290 /* Let the chunk size be a random power of 2 less than size */
291 ms = BIT(i915_prandom_u32_max_state(ilog2(s), &prng));
292 /* Round size down to the chunk size */
293 s &= -ms;
293 294
294 *chunk_size = ms;295 /* Convert from pages to bytes */
295 *size = s;296 *chunk_size = (u64)ms << 12;
297 *size = (u64)s << 12;
296}298}
297 299
298static int igt_buddy_alloc_smoke(void *arg)300static int igt_buddy_alloc_smoke(void *arg)
drivers/gpu/drm/i915/selftests/mock_gem_device.c+3−0
@@ -78,6 +78,7 @@ static void mock_device_release(struct drm_device *dev) · 77 unmodified lines
78 drm_mode_config_cleanup(&i915->drm);78 drm_mode_config_cleanup(&i915->drm);
79 79
80out:80out:
81 i915_params_free(&i915->params);
81 put_device(&i915->drm.pdev->dev);82 put_device(&i915->drm.pdev->dev);
82 i915->drm.pdev = NULL;83 i915->drm.pdev = NULL;
83}84}
@@ -165,6 +166,8 @@ struct drm_i915_private *mock_gem_device(void) · 81 unmodified lines
165 i915->drm.pdev = pdev;166 i915->drm.pdev = pdev;
166 drmm_add_final_kfree(&i915->drm, i915);167 drmm_add_final_kfree(&i915->drm, i915);
167 168
169 i915_params_copy(&i915->params, &i915_modparams);
170
168 intel_runtime_pm_init_early(&i915->runtime_pm);171 intel_runtime_pm_init_early(&i915->runtime_pm);
169 172
170 /* Using the global GTT may ask questions about KMS users, so prepare */173 /* Using the global GTT may ask questions about KMS users, so prepare */
drivers/gpu/drm/imx/ipuv3-plane.c+1−1
@@ -447,7 +447,7 @@ static int ipu_plane_atomic_check(struct drm_plane *plane, · 446 unmodified lines
447 if (fb->pitches[1] != fb->pitches[2])447 if (fb->pitches[1] != fb->pitches[2])
448 return -EINVAL;448 return -EINVAL;
449 449
450 /* fall-through */450 fallthrough;
451 case DRM_FORMAT_NV12:451 case DRM_FORMAT_NV12:
452 case DRM_FORMAT_NV16:452 case DRM_FORMAT_NV16:
453 ubo = drm_plane_state_to_ubo(state);453 ubo = drm_plane_state_to_ubo(state);
drivers/gpu/drm/meson/meson_osd_afbcd.c+1−1
@@ -205,7 +205,7 @@ static int meson_g12a_afbcd_pixel_fmt(u64 modifier, uint32_t format) · 204 unmodified lines
205 /* YTR is forbidden for non XBGR formats */205 /* YTR is forbidden for non XBGR formats */
206 if (modifier & AFBC_FORMAT_MOD_YTR)206 if (modifier & AFBC_FORMAT_MOD_YTR)
207 return -EINVAL;207 return -EINVAL;
208 /* fall through */208 fallthrough;
209 case DRM_FORMAT_XBGR8888:209 case DRM_FORMAT_XBGR8888:
210 case DRM_FORMAT_ABGR8888:210 case DRM_FORMAT_ABGR8888:
211 return MAFBC_FMT_RGBA8888;211 return MAFBC_FMT_RGBA8888;
drivers/gpu/drm/meson/meson_overlay.c+2−2
@@ -654,7 +654,7 @@ static void meson_overlay_atomic_update(struct drm_plane *plane, · 653 unmodified lines
654 priv->viu.vd1_addr2,654 priv->viu.vd1_addr2,
655 priv->viu.vd1_stride2,655 priv->viu.vd1_stride2,
656 priv->viu.vd1_height2);656 priv->viu.vd1_height2);
657 /* fallthrough */657 fallthrough;
658 case 2:658 case 2:
659 gem = drm_fb_cma_get_gem_obj(fb, 1);659 gem = drm_fb_cma_get_gem_obj(fb, 1);
660 priv->viu.vd1_addr1 = gem->paddr + fb->offsets[1];660 priv->viu.vd1_addr1 = gem->paddr + fb->offsets[1];
@@ -666,7 +666,7 @@ static void meson_overlay_atomic_update(struct drm_plane *plane, · 5 unmodified lines
666 priv->viu.vd1_addr1,666 priv->viu.vd1_addr1,
667 priv->viu.vd1_stride1,667 priv->viu.vd1_stride1,
668 priv->viu.vd1_height1);668 priv->viu.vd1_height1);
669 /* fallthrough */669 fallthrough;
670 case 1:670 case 1:
671 gem = drm_fb_cma_get_gem_obj(fb, 0);671 gem = drm_fb_cma_get_gem_obj(fb, 0);
672 priv->viu.vd1_addr0 = gem->paddr + fb->offsets[0];672 priv->viu.vd1_addr0 = gem->paddr + fb->offsets[0];
drivers/gpu/drm/msm/adreno/a5xx_gpu.c+2−2
@@ -59,7 +59,7 @@ static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct msm_gem_submit *submit · 58 unmodified lines
59 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:59 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:
60 if (priv->lastctx == ctx)60 if (priv->lastctx == ctx)
61 break;61 break;
62 /* fall-thru */62 fallthrough;
63 case MSM_SUBMIT_CMD_BUF:63 case MSM_SUBMIT_CMD_BUF:
64 /* copy commands into RB: */64 /* copy commands into RB: */
65 obj = submit->bos[submit->cmd[i].idx].obj;65 obj = submit->bos[submit->cmd[i].idx].obj;
@@ -150,7 +150,7 @@ static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, · 84 unmodified lines
150 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:150 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:
151 if (priv->lastctx == ctx)151 if (priv->lastctx == ctx)
152 break;152 break;
153 /* fall-thru */153 fallthrough;
154 case MSM_SUBMIT_CMD_BUF:154 case MSM_SUBMIT_CMD_BUF:
155 OUT_PKT7(ring, CP_INDIRECT_BUFFER_PFE, 3);155 OUT_PKT7(ring, CP_INDIRECT_BUFFER_PFE, 3);
156 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova));156 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova));
drivers/gpu/drm/msm/adreno/a6xx_gmu.c+30−10
@@ -133,7 +133,7 @@ void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp) · 132 unmodified lines
133 133
134 if (!gmu->legacy) {134 if (!gmu->legacy) {
135 a6xx_hfi_set_freq(gmu, perf_index);135 a6xx_hfi_set_freq(gmu, perf_index);
136 icc_set_bw(gpu->icc_path, 0, MBps_to_icc(7216));136 dev_pm_opp_set_bw(&gpu->pdev->dev, opp);
137 pm_runtime_put(gmu->dev);137 pm_runtime_put(gmu->dev);
138 return;138 return;
139 }139 }
@@ -157,11 +157,7 @@ void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp) · 17 unmodified lines
157 if (ret)157 if (ret)
158 dev_err(gmu->dev, "GMU set GPU frequency error: %d\n", ret);158 dev_err(gmu->dev, "GMU set GPU frequency error: %d\n", ret);
159 159
160 /*160 dev_pm_opp_set_bw(&gpu->pdev->dev, opp);
161 * Eventually we will want to scale the path vote with the frequency but
162 * for now leave it at max so that the performance is nominal.
163 */
164 icc_set_bw(gpu->icc_path, 0, MBps_to_icc(7216));
165 pm_runtime_put(gmu->dev);161 pm_runtime_put(gmu->dev);
166}162}
167 163
@@ -204,6 +200,16 @@ static int a6xx_gmu_start(struct a6xx_gmu *gmu) · 36 unmodified lines
204{200{
205 int ret;201 int ret;
206 u32 val;202 u32 val;
203 u32 mask, reset_val;
204
205 val = gmu_read(gmu, REG_A6XX_GMU_CM3_DTCM_START + 0xff8);
206 if (val <= 0x20010004) {
207 mask = 0xffffffff;
208 reset_val = 0xbabeface;
209 } else {
210 mask = 0x1ff;
211 reset_val = 0x100;
212 }
207 213
208 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1);214 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1);
209 215
@@ -215,7 +221,7 @@ static int a6xx_gmu_start(struct a6xx_gmu *gmu) · 5 unmodified lines
215 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 0);221 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 0);
216 222
217 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, val,223 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, val,
218 val == 0xbabeface, 100, 10000);224 (val & mask) == reset_val, 100, 10000);
219 225
220 if (ret)226 if (ret)
221 DRM_DEV_ERROR(gmu->dev, "GMU firmware initialization timed out\n");227 DRM_DEV_ERROR(gmu->dev, "GMU firmware initialization timed out\n");
@@ -602,7 +608,7 @@ static void a6xx_gmu_power_config(struct a6xx_gmu *gmu) · 380 unmodified lines
602 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0,608 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0,
603 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE |609 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE |
604 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_HM_POWER_COLLAPSE_ENABLE);610 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_HM_POWER_COLLAPSE_ENABLE);
605 /* Fall through */611 fallthrough;
606 case GMU_IDLE_STATE_SPTP:612 case GMU_IDLE_STATE_SPTP:
607 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_SPTPRAC_HYST,613 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_SPTPRAC_HYST,
608 GMU_PWR_COL_HYST);614 GMU_PWR_COL_HYST);
@@ -845,10 +851,24 @@ static void a6xx_gmu_set_initial_freq(struct msm_gpu *gpu, struct a6xx_gmu *gmu) · 236 unmodified lines
845 if (IS_ERR_OR_NULL(gpu_opp))851 if (IS_ERR_OR_NULL(gpu_opp))
846 return;852 return;
847 853
854 gmu->freq = 0; /* so a6xx_gmu_set_freq() doesn't exit early */
848 a6xx_gmu_set_freq(gpu, gpu_opp);855 a6xx_gmu_set_freq(gpu, gpu_opp);
849 dev_pm_opp_put(gpu_opp);856 dev_pm_opp_put(gpu_opp);
850}857}
851 858
859static void a6xx_gmu_set_initial_bw(struct msm_gpu *gpu, struct a6xx_gmu *gmu)
860{
861 struct dev_pm_opp *gpu_opp;
862 unsigned long gpu_freq = gmu->gpu_freqs[gmu->current_perf_index];
863
864 gpu_opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, gpu_freq, true);
865 if (IS_ERR_OR_NULL(gpu_opp))
866 return;
867
868 dev_pm_opp_set_bw(&gpu->pdev->dev, gpu_opp);
869 dev_pm_opp_put(gpu_opp);
870}
871
852int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu)872int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu)
853{873{
854 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;874 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
@@ -882,7 +902,7 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) · 27 unmodified lines
882 }902 }
883 903
884 /* Set the bus quota to a reasonable value for boot */904 /* Set the bus quota to a reasonable value for boot */
885 icc_set_bw(gpu->icc_path, 0, MBps_to_icc(3072));905 a6xx_gmu_set_initial_bw(gpu, gmu);
886 906
887 /* Enable the GMU interrupt */907 /* Enable the GMU interrupt */
888 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, ~0);908 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, ~0);
@@ -1051,7 +1071,7 @@ int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu) · 162 unmodified lines
1051 a6xx_gmu_shutdown(gmu);1071 a6xx_gmu_shutdown(gmu);
1052 1072
1053 /* Remove the bus vote */1073 /* Remove the bus vote */
1054 icc_set_bw(gpu->icc_path, 0, 0);1074 dev_pm_opp_set_bw(&gpu->pdev->dev, NULL);
1055 1075
1056 /*1076 /*
1057 * Make sure the GX domain is off before turning off the GMU (CX)1077 * Make sure the GX domain is off before turning off the GMU (CX)
drivers/gpu/drm/msm/adreno/a6xx_gpu.c+1−1
@@ -117,7 +117,7 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, · 116 unmodified lines
117 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:117 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:
118 if (priv->lastctx == ctx)118 if (priv->lastctx == ctx)
119 break;119 break;
120 /* fall-thru */120 fallthrough;
121 case MSM_SUBMIT_CMD_BUF:121 case MSM_SUBMIT_CMD_BUF:
122 OUT_PKT7(ring, CP_INDIRECT_BUFFER_PFE, 3);122 OUT_PKT7(ring, CP_INDIRECT_BUFFER_PFE, 3);
123 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova));123 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova));
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c+2−1
@@ -938,7 +938,8 @@ struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu) · 937 unmodified lines
938 msm_gem_kernel_put(dumper.bo, gpu->aspace, true);938 msm_gem_kernel_put(dumper.bo, gpu->aspace, true);
939 }939 }
940 940
941 a6xx_get_debugbus(gpu, a6xx_state);941 if (snapshot_debugbus)
942 a6xx_get_debugbus(gpu, a6xx_state);
942 943
943 return &a6xx_state->base;944 return &a6xx_state->base;
944}945}
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h+1−1
@@ -372,7 +372,7 @@ static const struct a6xx_indexed_registers { · 371 unmodified lines
372 u32 data;372 u32 data;
373 u32 count;373 u32 count;
374} a6xx_indexed_reglist[] = {374} a6xx_indexed_reglist[] = {
375 { "CP_SEQ_STAT", REG_A6XX_CP_SQE_STAT_ADDR,375 { "CP_SQE_STAT", REG_A6XX_CP_SQE_STAT_ADDR,
376 REG_A6XX_CP_SQE_STAT_DATA, 0x33 },376 REG_A6XX_CP_SQE_STAT_DATA, 0x33 },
377 { "CP_DRAW_STATE", REG_A6XX_CP_DRAW_STATE_ADDR,377 { "CP_DRAW_STATE", REG_A6XX_CP_DRAW_STATE_ADDR,
378 REG_A6XX_CP_DRAW_STATE_DATA, 0x100 },378 REG_A6XX_CP_DRAW_STATE_DATA, 0x100 },
drivers/gpu/drm/msm/adreno/adreno_device.c+4−0
@@ -14,6 +14,10 @@ bool hang_debug = false; · 13 unmodified lines
14MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)");14MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)");
15module_param_named(hang_debug, hang_debug, bool, 0600);15module_param_named(hang_debug, hang_debug, bool, 0600);
16 16
17bool snapshot_debugbus = false;
18MODULE_PARM_DESC(snapshot_debugbus, "Include debugbus sections in GPU devcoredump (if not fused off)");
19module_param_named(snapshot_debugbus, snapshot_debugbus, bool, 0600);
20
17static const struct adreno_info gpulist[] = {21static const struct adreno_info gpulist[] = {
18 {22 {
19 .rev = ADRENO_REV(2, 0, 0, 0),23 .rev = ADRENO_REV(2, 0, 0, 0),
drivers/gpu/drm/msm/adreno/adreno_gpu.c+2−2
@@ -396,7 +396,7 @@ int adreno_hw_init(struct msm_gpu *gpu) · 395 unmodified lines
396 ring->next = ring->start;396 ring->next = ring->start;
397 397
398 /* reset completed fence seqno: */398 /* reset completed fence seqno: */
399 ring->memptrs->fence = ring->seqno;399 ring->memptrs->fence = ring->fctx->completed_fence;
400 ring->memptrs->rptr = 0;400 ring->memptrs->rptr = 0;
401 }401 }
402 402
@@ -474,7 +474,7 @@ void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, · 71 unmodified lines
474 /* ignore if there has not been a ctx switch: */474 /* ignore if there has not been a ctx switch: */
475 if (priv->lastctx == ctx)475 if (priv->lastctx == ctx)
476 break;476 break;
477 /* fall-thru */477 fallthrough;
478 case MSM_SUBMIT_CMD_BUF:478 case MSM_SUBMIT_CMD_BUF:
479 OUT_PKT3(ring, adreno_is_a4xx(adreno_gpu) ?479 OUT_PKT3(ring, adreno_is_a4xx(adreno_gpu) ?
480 CP_INDIRECT_BUFFER_PFE : CP_INDIRECT_BUFFER_PFD, 2);480 CP_INDIRECT_BUFFER_PFE : CP_INDIRECT_BUFFER_PFD, 2);
drivers/gpu/drm/msm/adreno/adreno_gpu.h+2−0
@@ -21,6 +21,8 @@ · 20 unmodified lines
21#define REG_SKIP ~021#define REG_SKIP ~0
22#define REG_ADRENO_SKIP(_offset) [_offset] = REG_SKIP22#define REG_ADRENO_SKIP(_offset) [_offset] = REG_SKIP
23 23
24extern bool snapshot_debugbus;
25
24/**26/**
25 * adreno_regs: List of registers that are used in across all27 * adreno_regs: List of registers that are used in across all
26 * 3D devices. Each device type has different offset value for the same28 * 3D devices. Each device type has different offset value for the same
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c+1−1
@@ -827,7 +827,7 @@ static void dpu_crtc_enable(struct drm_crtc *crtc, · 826 unmodified lines
827{827{
828 struct dpu_crtc *dpu_crtc;828 struct dpu_crtc *dpu_crtc;
829 struct drm_encoder *encoder;829 struct drm_encoder *encoder;
830 bool request_bandwidth;830 bool request_bandwidth = false;
831 831
832 if (!crtc) {832 if (!crtc) {
833 DPU_ERROR("invalid crtc\n");833 DPU_ERROR("invalid crtc\n");
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c+11−9
@@ -599,7 +599,10 @@ static int dpu_encoder_virt_atomic_check( · 598 unmodified lines
599 dpu_kms = to_dpu_kms(priv->kms);599 dpu_kms = to_dpu_kms(priv->kms);
600 mode = &crtc_state->mode;600 mode = &crtc_state->mode;
601 adj_mode = &crtc_state->adjusted_mode;601 adj_mode = &crtc_state->adjusted_mode;
602 global_state = dpu_kms_get_existing_global_state(dpu_kms);602 global_state = dpu_kms_get_global_state(crtc_state->state);
603 if (IS_ERR(global_state))
604 return PTR_ERR(global_state);
605
603 trace_dpu_enc_atomic_check(DRMID(drm_enc));606 trace_dpu_enc_atomic_check(DRMID(drm_enc));
604 607
605 /* perform atomic check on the first physical encoder (master) */608 /* perform atomic check on the first physical encoder (master) */
@@ -625,12 +628,15 @@ static int dpu_encoder_virt_atomic_check( · 19 unmodified lines
625 /* Reserve dynamic resources now. */628 /* Reserve dynamic resources now. */
626 if (!ret) {629 if (!ret) {
627 /*630 /*
628 * Avoid reserving resources when mode set is pending. Topology631 * Release and Allocate resources on every modeset
629 * info may not be available to complete reservation.632 * Dont allocate when active is false.
630 */633 */
631 if (drm_atomic_crtc_needs_modeset(crtc_state)) {634 if (drm_atomic_crtc_needs_modeset(crtc_state)) {
632 ret = dpu_rm_reserve(&dpu_kms->rm, global_state,635 dpu_rm_release(global_state, drm_enc);
633 drm_enc, crtc_state, topology);636
637 if (!crtc_state->active_changed || crtc_state->active)
638 ret = dpu_rm_reserve(&dpu_kms->rm, global_state,
639 drm_enc, crtc_state, topology);
634 }640 }
635 }641 }
636 642
@@ -1181,7 +1187,6 @@ static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc) · 544 unmodified lines
1181 struct dpu_encoder_virt *dpu_enc = NULL;1187 struct dpu_encoder_virt *dpu_enc = NULL;
1182 struct msm_drm_private *priv;1188 struct msm_drm_private *priv;
1183 struct dpu_kms *dpu_kms;1189 struct dpu_kms *dpu_kms;
1184 struct dpu_global_state *global_state;
1185 int i = 0;1190 int i = 0;
1186 1191
1187 if (!drm_enc) {1192 if (!drm_enc) {
@@ -1200,7 +1205,6 @@ static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc) · 12 unmodified lines
1200 1205
1201 priv = drm_enc->dev->dev_private;1206 priv = drm_enc->dev->dev_private;
1202 dpu_kms = to_dpu_kms(priv->kms);1207 dpu_kms = to_dpu_kms(priv->kms);
1203 global_state = dpu_kms_get_existing_global_state(dpu_kms);
1204 1208
1205 trace_dpu_enc_disable(DRMID(drm_enc));1209 trace_dpu_enc_disable(DRMID(drm_enc));
1206 1210
@@ -1230,8 +1234,6 @@ static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc) · 23 unmodified lines
1230 1234
1231 DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n");1235 DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n");
1232 1236
1233 dpu_rm_release(global_state, drm_enc);
1234
1235 mutex_unlock(&dpu_enc->enc_lock);1237 mutex_unlock(&dpu_enc->enc_lock);
1236}1238}
1237 1239
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c+2−2
@@ -866,9 +866,9 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, · 865 unmodified lines
866 crtc_state = drm_atomic_get_new_crtc_state(state->state,866 crtc_state = drm_atomic_get_new_crtc_state(state->state,
867 state->crtc);867 state->crtc);
868 868
869 min_scale = FRAC_16_16(1, pdpu->pipe_sblk->maxdwnscale);869 min_scale = FRAC_16_16(1, pdpu->pipe_sblk->maxupscale);
870 ret = drm_atomic_helper_check_plane_state(state, crtc_state, min_scale,870 ret = drm_atomic_helper_check_plane_state(state, crtc_state, min_scale,
871 pdpu->pipe_sblk->maxupscale << 16,871 pdpu->pipe_sblk->maxdwnscale << 16,
872 true, true);872 true, true);
873 if (ret) {873 if (ret) {
874 DPU_DEBUG_PLANE(pdpu, "Check plane state failed (%d)\n", ret);874 DPU_DEBUG_PLANE(pdpu, "Check plane state failed (%d)\n", ret);
drivers/gpu/drm/msm/msm_atomic.c+36−0
@@ -27,6 +27,34 @@ int msm_atomic_prepare_fb(struct drm_plane *plane, · 26 unmodified lines
27 return msm_framebuffer_prepare(new_state->fb, kms->aspace);27 return msm_framebuffer_prepare(new_state->fb, kms->aspace);
28}28}
29 29
30/*
31 * Helpers to control vblanks while we flush.. basically just to ensure
32 * that vblank accounting is switched on, so we get valid seqn/timestamp
33 * on pageflip events (if requested)
34 */
35
36static void vblank_get(struct msm_kms *kms, unsigned crtc_mask)
37{
38 struct drm_crtc *crtc;
39
40 for_each_crtc_mask(kms->dev, crtc, crtc_mask) {
41 if (!crtc->state->active)
42 continue;
43 drm_crtc_vblank_get(crtc);
44 }
45}
46
47static void vblank_put(struct msm_kms *kms, unsigned crtc_mask)
48{
49 struct drm_crtc *crtc;
50
51 for_each_crtc_mask(kms->dev, crtc, crtc_mask) {
52 if (!crtc->state->active)
53 continue;
54 drm_crtc_vblank_put(crtc);
55 }
56}
57
30static void msm_atomic_async_commit(struct msm_kms *kms, int crtc_idx)58static void msm_atomic_async_commit(struct msm_kms *kms, int crtc_idx)
31{59{
32 unsigned crtc_mask = BIT(crtc_idx);60 unsigned crtc_mask = BIT(crtc_idx);
@@ -44,6 +72,8 @@ static void msm_atomic_async_commit(struct msm_kms *kms, int crtc_idx) · 11 unmodified lines
44 72
45 kms->funcs->enable_commit(kms);73 kms->funcs->enable_commit(kms);
46 74
75 vblank_get(kms, crtc_mask);
76
47 /*77 /*
48 * Flush hardware updates:78 * Flush hardware updates:
49 */79 */
@@ -58,6 +88,8 @@ static void msm_atomic_async_commit(struct msm_kms *kms, int crtc_idx) · 8 unmodified lines
58 kms->funcs->wait_flush(kms, crtc_mask);88 kms->funcs->wait_flush(kms, crtc_mask);
59 trace_msm_atomic_wait_flush_finish(crtc_mask);89 trace_msm_atomic_wait_flush_finish(crtc_mask);
60 90
91 vblank_put(kms, crtc_mask);
92
61 mutex_lock(&kms->commit_lock);93 mutex_lock(&kms->commit_lock);
62 kms->funcs->complete_commit(kms, crtc_mask);94 kms->funcs->complete_commit(kms, crtc_mask);
63 mutex_unlock(&kms->commit_lock);95 mutex_unlock(&kms->commit_lock);
@@ -221,6 +253,8 @@ void msm_atomic_commit_tail(struct drm_atomic_state *state) · 157 unmodified lines
221 */253 */
222 kms->pending_crtc_mask &= ~crtc_mask;254 kms->pending_crtc_mask &= ~crtc_mask;
223 255
256 vblank_get(kms, crtc_mask);
257
224 /*258 /*
225 * Flush hardware updates:259 * Flush hardware updates:
226 */260 */
@@ -235,6 +269,8 @@ void msm_atomic_commit_tail(struct drm_atomic_state *state) · 8 unmodified lines
235 kms->funcs->wait_flush(kms, crtc_mask);269 kms->funcs->wait_flush(kms, crtc_mask);
236 trace_msm_atomic_wait_flush_finish(crtc_mask);270 trace_msm_atomic_wait_flush_finish(crtc_mask);
237 271
272 vblank_put(kms, crtc_mask);
273
238 mutex_lock(&kms->commit_lock);274 mutex_lock(&kms->commit_lock);
239 kms->funcs->complete_commit(kms, crtc_mask);275 kms->funcs->complete_commit(kms, crtc_mask);
240 mutex_unlock(&kms->commit_lock);276 mutex_unlock(&kms->commit_lock);
drivers/gpu/drm/msm/msm_drv.c+8−0
@@ -1320,6 +1320,13 @@ static int msm_pdev_remove(struct platform_device *pdev) · 1319 unmodified lines
1320 return 0;1320 return 0;
1321}1321}
1322 1322
1323static void msm_pdev_shutdown(struct platform_device *pdev)
1324{
1325 struct drm_device *drm = platform_get_drvdata(pdev);
1326
1327 drm_atomic_helper_shutdown(drm);
1328}
1329
1323static const struct of_device_id dt_match[] = {1330static const struct of_device_id dt_match[] = {
1324 { .compatible = "qcom,mdp4", .data = (void *)KMS_MDP4 },1331 { .compatible = "qcom,mdp4", .data = (void *)KMS_MDP4 },
1325 { .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 },1332 { .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 },
@@ -1332,6 +1339,7 @@ MODULE_DEVICE_TABLE(of, dt_match); · 6 unmodified lines
1332static struct platform_driver msm_platform_driver = {1339static struct platform_driver msm_platform_driver = {
1333 .probe = msm_pdev_probe,1340 .probe = msm_pdev_probe,
1334 .remove = msm_pdev_remove,1341 .remove = msm_pdev_remove,
1342 .shutdown = msm_pdev_shutdown,
1335 .driver = {1343 .driver = {
1336 .name = "msm",1344 .name = "msm",
1337 .of_match_table = dt_match,1345 .of_match_table = dt_match,
drivers/gpu/drm/msm/msm_ringbuffer.c+2−1
@@ -27,7 +27,8 @@ struct msm_ringbuffer *msm_ringbuffer_new(struct msm_gpu *gpu, int id, · 26 unmodified lines
27 ring->id = id;27 ring->id = id;
28 28
29 ring->start = msm_gem_kernel_new(gpu->dev, MSM_GPU_RINGBUFFER_SZ,29 ring->start = msm_gem_kernel_new(gpu->dev, MSM_GPU_RINGBUFFER_SZ,
30 MSM_BO_WC, gpu->aspace, &ring->bo, &ring->iova);30 MSM_BO_WC | MSM_BO_GPU_READONLY, gpu->aspace, &ring->bo,
31 &ring->iova);
31 32
32 if (IS_ERR(ring->start)) {33 if (IS_ERR(ring->start)) {
33 ret = PTR_ERR(ring->start);34 ret = PTR_ERR(ring->start);
drivers/gpu/drm/nouveau/dispnv50/core507d.c+4−1
@@ -50,7 +50,10 @@ core507d_update(struct nv50_core *core, u32 *interlock, bool ntfy) · 49 unmodified lines
50 interlock[NV50_DISP_INTERLOCK_OVLY] |50 interlock[NV50_DISP_INTERLOCK_OVLY] |
51 NVDEF(NV507D, UPDATE, NOT_DRIVER_FRIENDLY, FALSE) |51 NVDEF(NV507D, UPDATE, NOT_DRIVER_FRIENDLY, FALSE) |
52 NVDEF(NV507D, UPDATE, NOT_DRIVER_UNFRIENDLY, FALSE) |52 NVDEF(NV507D, UPDATE, NOT_DRIVER_UNFRIENDLY, FALSE) |
53 NVDEF(NV507D, UPDATE, INHIBIT_INTERRUPTS, FALSE));53 NVDEF(NV507D, UPDATE, INHIBIT_INTERRUPTS, FALSE),
54
55 SET_NOTIFIER_CONTROL,
56 NVDEF(NV507D, SET_NOTIFIER_CONTROL, NOTIFY, DISABLE));
54 57
55 return PUSH_KICK(push);58 return PUSH_KICK(push);
56}59}
drivers/gpu/drm/nouveau/dispnv50/crcc37d.c+1−1
@@ -6,7 +6,7 @@ · 5 unmodified lines
6#include "disp.h"6#include "disp.h"
7#include "head.h"7#include "head.h"
8 8
9#include <nvif/push507c.h>9#include <nvif/pushc37b.h>
10 10
11#include <nvhw/class/clc37d.h>11#include <nvhw/class/clc37d.h>
12 12
drivers/gpu/drm/nouveau/dispnv50/disp.c+6−0
@@ -257,6 +257,12 @@ nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp, · 256 unmodified lines
257 dmac->push->end = dmac->push->bgn;257 dmac->push->end = dmac->push->bgn;
258 dmac->max = 0x1000/4 - 1;258 dmac->max = 0x1000/4 - 1;
259 259
260 /* EVO channels are affected by a HW bug where the last 12 DWORDs
261 * of the push buffer aren't able to be used safely.
262 */
263 if (disp->oclass < GV100_DISP)
264 dmac->max -= 12;
265
260 args->pushbuf = nvif_handle(&dmac->_push.mem.object);266 args->pushbuf = nvif_handle(&dmac->_push.mem.object);
261 267
262 ret = nv50_chan_create(device, disp, oclass, head, data, size,268 ret = nv50_chan_create(device, disp, oclass, head, data, size,
drivers/gpu/drm/nouveau/include/nvif/push507c.h+1−1
@@ -20,6 +20,6 @@ · 19 unmodified lines
20 PUSH_ASSERT(!((o) & ~DRF_SMASK(NV507C_DMA_JUMP_OFFSET)), "offset"); \20 PUSH_ASSERT(!((o) & ~DRF_SMASK(NV507C_DMA_JUMP_OFFSET)), "offset"); \
21 PUSH_DATA__((p), NVDEF(NV507C, DMA, OPCODE, JUMP) | \21 PUSH_DATA__((p), NVDEF(NV507C, DMA, OPCODE, JUMP) | \
22 NVVAL(NV507C, DMA, JUMP_OFFSET, (o) >> 2), \22 NVVAL(NV507C, DMA, JUMP_OFFSET, (o) >> 2), \
23 "jump 0x%08x - %s", (u32)(o), __func__); \23 " jump 0x%08x - %s", (u32)(o), __func__); \
24} while(0)24} while(0)
25#endif25#endif
drivers/gpu/drm/omapdrm/dss/venc.c+1−1
@@ -597,7 +597,7 @@ static void venc_bridge_mode_set(struct drm_bridge *bridge, · 596 unmodified lines
597 switch (venc_mode) {597 switch (venc_mode) {
598 default:598 default:
599 WARN_ON_ONCE(1);599 WARN_ON_ONCE(1);
600 /* Fall-through */600 fallthrough;
601 case VENC_MODE_PAL:601 case VENC_MODE_PAL:
602 venc->config = &venc_config_pal_trm;602 venc->config = &venc_config_pal_trm;
603 break;603 break;
drivers/gpu/drm/omapdrm/omap_crtc.c+2−1
@@ -451,11 +451,12 @@ static void omap_crtc_atomic_enable(struct drm_crtc *crtc, · 450 unmodified lines
451 if (omap_state->manually_updated)451 if (omap_state->manually_updated)
452 return;452 return;
453 453
454 spin_lock_irq(&crtc->dev->event_lock);
455 drm_crtc_vblank_on(crtc);454 drm_crtc_vblank_on(crtc);
455
456 ret = drm_crtc_vblank_get(crtc);456 ret = drm_crtc_vblank_get(crtc);
457 WARN_ON(ret != 0);457 WARN_ON(ret != 0);
458 458
459 spin_lock_irq(&crtc->dev->event_lock);
459 omap_crtc_arm_event(crtc);460 omap_crtc_arm_event(crtc);
460 spin_unlock_irq(&crtc->dev->event_lock);461 spin_unlock_irq(&crtc->dev->event_lock);
461}462}
drivers/gpu/drm/radeon/ci_dpm.c+1−1
@@ -4856,7 +4856,7 @@ static void ci_request_link_speed_change_before_state_change(struct radeon_devic · 4855 unmodified lines
4856 pi->force_pcie_gen = RADEON_PCIE_GEN2;4856 pi->force_pcie_gen = RADEON_PCIE_GEN2;
4857 if (current_link_speed == RADEON_PCIE_GEN2)4857 if (current_link_speed == RADEON_PCIE_GEN2)
4858 break;4858 break;
4859 /* fall through */4859 fallthrough;
4860 case RADEON_PCIE_GEN2:4860 case RADEON_PCIE_GEN2:
4861 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)4861 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
4862 break;4862 break;
drivers/gpu/drm/radeon/r300.c+2−2
@@ -820,7 +820,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p, · 819 unmodified lines
820 ((idx_value >> 21) & 0xF));820 ((idx_value >> 21) & 0xF));
821 return -EINVAL;821 return -EINVAL;
822 }822 }
823 /* Fall through. */823 fallthrough;
824 case 6:824 case 6:
825 track->cb[i].cpp = 4;825 track->cb[i].cpp = 4;
826 break;826 break;
@@ -971,7 +971,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p, · 144 unmodified lines
971 return -EINVAL;971 return -EINVAL;
972 }972 }
973 /* The same rules apply as for DXT3/5. */973 /* The same rules apply as for DXT3/5. */
974 /* Fall through. */974 fallthrough;
975 case R300_TX_FORMAT_DXT3:975 case R300_TX_FORMAT_DXT3:
976 case R300_TX_FORMAT_DXT5:976 case R300_TX_FORMAT_DXT5:
977 track->textures[i].cpp = 1;977 track->textures[i].cpp = 1;
drivers/gpu/drm/radeon/r420.c+1−1
@@ -115,7 +115,7 @@ void r420_pipes_init(struct radeon_device *rdev) · 114 unmodified lines
115 default:115 default:
116 /* force to 1 pipe */116 /* force to 1 pipe */
117 num_pipes = 1;117 num_pipes = 1;
118 /* fall through */118 fallthrough;
119 case 1:119 case 1:
120 tmp = (0 << 1);120 tmp = (0 << 1);
121 break;121 break;
drivers/gpu/drm/radeon/r600_cs.c+2−2
@@ -487,7 +487,7 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i) · 486 unmodified lines
487 return -EINVAL;487 return -EINVAL;
488 }488 }
489 }489 }
490 /* fall through */490 fallthrough;
491 case V_0280A0_CLEAR_ENABLE:491 case V_0280A0_CLEAR_ENABLE:
492 {492 {
493 uint32_t block_max = G_028100_CMASK_BLOCK_MAX(track->cb_color_mask[i]);493 uint32_t block_max = G_028100_CMASK_BLOCK_MAX(track->cb_color_mask[i]);
@@ -1535,7 +1535,7 @@ static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx, · 1041 unmodified lines
1535 break;1535 break;
1536 case V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA:1536 case V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA:
1537 is_array = true;1537 is_array = true;
1538 /* fall through */1538 fallthrough;
1539 case V_038000_SQ_TEX_DIM_2D_MSAA:1539 case V_038000_SQ_TEX_DIM_2D_MSAA:
1540 array_check.nsamples = 1 << llevel;1540 array_check.nsamples = 1 << llevel;
1541 llevel = 0;1541 llevel = 0;
drivers/gpu/drm/radeon/radeon_display.c+1−1
@@ -933,7 +933,7 @@ static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div, · 932 unmodified lines
933 933
934 /* get matching reference and feedback divider */934 /* get matching reference and feedback divider */
935 *ref_div = min(max(den/post_div, 1u), ref_div_max);935 *ref_div = min(max(den/post_div, 1u), ref_div_max);
936 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);936 *fb_div = max(nom * *ref_div * post_div / den, 1u);
937 937
938 /* limit fb divider to its maximum */938 /* limit fb divider to its maximum */
939 if (*fb_div > fb_div_max) {939 if (*fb_div > fb_div_max) {
drivers/gpu/drm/radeon/radeon_uvd.c+1−1
@@ -454,7 +454,7 @@ static int radeon_uvd_validate_codec(struct radeon_cs_parser *p, · 453 unmodified lines
454 if (p->rdev->family >= CHIP_PALM)454 if (p->rdev->family >= CHIP_PALM)
455 return 0;455 return 0;
456 456
457 /* fall through */457 fallthrough;
458 default:458 default:
459 DRM_ERROR("UVD codec not supported by hardware %d!\n",459 DRM_ERROR("UVD codec not supported by hardware %d!\n",
460 stream_type);460 stream_type);
drivers/gpu/drm/radeon/si_dpm.c+1−1
@@ -5744,7 +5744,7 @@ static void si_request_link_speed_change_before_state_change(struct radeon_devic · 5743 unmodified lines
5744 si_pi->force_pcie_gen = RADEON_PCIE_GEN2;5744 si_pi->force_pcie_gen = RADEON_PCIE_GEN2;
5745 if (current_link_speed == RADEON_PCIE_GEN2)5745 if (current_link_speed == RADEON_PCIE_GEN2)
5746 break;5746 break;
5747 /* fall through */5747 fallthrough;
5748 case RADEON_PCIE_GEN2:5748 case RADEON_PCIE_GEN2:
5749 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)5749 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
5750 break;5750 break;
drivers/gpu/drm/radeon/uvd_v1_0.c+1−1
@@ -219,7 +219,7 @@ done: · 218 unmodified lines
219 WREG32(RS_DQ_RD_RET_CONF, 0x3f);219 WREG32(RS_DQ_RD_RET_CONF, 0x3f);
220 WREG32(MC_CONFIG, 0x1f);220 WREG32(MC_CONFIG, 0x1f);
221 221
222 /* fall through */222 fallthrough;
223 case CHIP_RV670:223 case CHIP_RV670:
224 case CHIP_RV635:224 case CHIP_RV635:
225 225
drivers/gpu/drm/savage/savage_state.c+5−5
@@ -306,7 +306,7 @@ static int savage_dispatch_dma_prim(drm_savage_private_t * dev_priv, · 305 unmodified lines
306 case SAVAGE_PRIM_TRILIST_201:306 case SAVAGE_PRIM_TRILIST_201:
307 reorder = 1;307 reorder = 1;
308 prim = SAVAGE_PRIM_TRILIST;308 prim = SAVAGE_PRIM_TRILIST;
309 /* fall through */309 fallthrough;
310 case SAVAGE_PRIM_TRILIST:310 case SAVAGE_PRIM_TRILIST:
311 if (n % 3 != 0) {311 if (n % 3 != 0) {
312 DRM_ERROR("wrong number of vertices %u in TRILIST\n",312 DRM_ERROR("wrong number of vertices %u in TRILIST\n",
@@ -444,7 +444,7 @@ static int savage_dispatch_vb_prim(drm_savage_private_t * dev_priv, · 131 unmodified lines
444 case SAVAGE_PRIM_TRILIST_201:444 case SAVAGE_PRIM_TRILIST_201:
445 reorder = 1;445 reorder = 1;
446 prim = SAVAGE_PRIM_TRILIST;446 prim = SAVAGE_PRIM_TRILIST;
447 /* fall through */447 fallthrough;
448 case SAVAGE_PRIM_TRILIST:448 case SAVAGE_PRIM_TRILIST:
449 if (n % 3 != 0) {449 if (n % 3 != 0) {
450 DRM_ERROR("wrong number of vertices %u in TRILIST\n",450 DRM_ERROR("wrong number of vertices %u in TRILIST\n",
@@ -566,7 +566,7 @@ static int savage_dispatch_dma_idx(drm_savage_private_t * dev_priv, · 115 unmodified lines
566 case SAVAGE_PRIM_TRILIST_201:566 case SAVAGE_PRIM_TRILIST_201:
567 reorder = 1;567 reorder = 1;
568 prim = SAVAGE_PRIM_TRILIST;568 prim = SAVAGE_PRIM_TRILIST;
569 /* fall through */569 fallthrough;
570 case SAVAGE_PRIM_TRILIST:570 case SAVAGE_PRIM_TRILIST:
571 if (n % 3 != 0) {571 if (n % 3 != 0) {
572 DRM_ERROR("wrong number of indices %u in TRILIST\n", n);572 DRM_ERROR("wrong number of indices %u in TRILIST\n", n);
@@ -705,7 +705,7 @@ static int savage_dispatch_vb_idx(drm_savage_private_t * dev_priv, · 132 unmodified lines
705 case SAVAGE_PRIM_TRILIST_201:705 case SAVAGE_PRIM_TRILIST_201:
706 reorder = 1;706 reorder = 1;
707 prim = SAVAGE_PRIM_TRILIST;707 prim = SAVAGE_PRIM_TRILIST;
708 /* fall through */708 fallthrough;
709 case SAVAGE_PRIM_TRILIST:709 case SAVAGE_PRIM_TRILIST:
710 if (n % 3 != 0) {710 if (n % 3 != 0) {
711 DRM_ERROR("wrong number of indices %u in TRILIST\n", n);711 DRM_ERROR("wrong number of indices %u in TRILIST\n", n);
@@ -1066,7 +1066,7 @@ int savage_bci_cmdbuf(struct drm_device *dev, void *data, struct drm_file *file_ · 354 unmodified lines
1066 ret = -EINVAL;1066 ret = -EINVAL;
1067 goto done;1067 goto done;
1068 }1068 }
1069 /* fall through */1069 fallthrough;
1070 case SAVAGE_CMD_DMA_PRIM:1070 case SAVAGE_CMD_DMA_PRIM:
1071 case SAVAGE_CMD_VB_PRIM:1071 case SAVAGE_CMD_VB_PRIM:
1072 if (!first_draw_cmd)1072 if (!first_draw_cmd)
drivers/gpu/drm/sti/sti_hdmi.c+3−3
@@ -850,13 +850,13 @@ static int hdmi_audio_configure(struct sti_hdmi *hdmi) · 849 unmodified lines
850 switch (info->channels) {850 switch (info->channels) {
851 case 8:851 case 8:
852 audio_cfg |= HDMI_AUD_CFG_CH78_VALID;852 audio_cfg |= HDMI_AUD_CFG_CH78_VALID;
853 /* fall through */853 fallthrough;
854 case 6:854 case 6:
855 audio_cfg |= HDMI_AUD_CFG_CH56_VALID;855 audio_cfg |= HDMI_AUD_CFG_CH56_VALID;
856 /* fall through */856 fallthrough;
857 case 4:857 case 4:
858 audio_cfg |= HDMI_AUD_CFG_CH34_VALID | HDMI_AUD_CFG_8CH;858 audio_cfg |= HDMI_AUD_CFG_CH34_VALID | HDMI_AUD_CFG_8CH;
859 /* fall through */859 fallthrough;
860 case 2:860 case 2:
861 audio_cfg |= HDMI_AUD_CFG_CH12_VALID;861 audio_cfg |= HDMI_AUD_CFG_CH12_VALID;
862 break;862 break;
drivers/gpu/drm/sun4i/sun4i_tcon.c+2−2
@@ -195,7 +195,7 @@ void sun4i_tcon_set_status(struct sun4i_tcon *tcon, · 194 unmodified lines
195 switch (encoder->encoder_type) {195 switch (encoder->encoder_type) {
196 case DRM_MODE_ENCODER_LVDS:196 case DRM_MODE_ENCODER_LVDS:
197 is_lvds = true;197 is_lvds = true;
198 /* Fallthrough */198 fallthrough;
199 case DRM_MODE_ENCODER_DSI:199 case DRM_MODE_ENCODER_DSI:
200 case DRM_MODE_ENCODER_NONE:200 case DRM_MODE_ENCODER_NONE:
201 channel = 0;201 channel = 0;
@@ -342,7 +342,7 @@ static void sun4i_tcon0_mode_set_dithering(struct sun4i_tcon *tcon, · 140 unmodified lines
342 /* R and B components are only 5 bits deep */342 /* R and B components are only 5 bits deep */
343 val |= SUN4I_TCON0_FRM_CTL_MODE_R;343 val |= SUN4I_TCON0_FRM_CTL_MODE_R;
344 val |= SUN4I_TCON0_FRM_CTL_MODE_B;344 val |= SUN4I_TCON0_FRM_CTL_MODE_B;
345 /* Fall through */345 fallthrough;
346 case MEDIA_BUS_FMT_RGB666_1X18:346 case MEDIA_BUS_FMT_RGB666_1X18:
347 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:347 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
348 /* Fall through: enable dithering */348 /* Fall through: enable dithering */
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c+1−1
@@ -1027,7 +1027,7 @@ static ssize_t sun6i_dsi_transfer(struct mipi_dsi_host *host, · 1026 unmodified lines
1027 ret = sun6i_dsi_dcs_read(dsi, msg);1027 ret = sun6i_dsi_dcs_read(dsi, msg);
1028 break;1028 break;
1029 }1029 }
1030 /* Else, fall through */1030 fallthrough;
1031 1031
1032 default:1032 default:
1033 ret = -EINVAL;1033 ret = -EINVAL;
drivers/gpu/drm/tegra/dc.c+1−1
@@ -135,7 +135,7 @@ static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v, · 134 unmodified lines
135 135
136 default:136 default:
137 WARN_ON_ONCE(1);137 WARN_ON_ONCE(1);
138 /* fallthrough */138 fallthrough;
139 case 4:139 case 4:
140 max = 4;140 max = 4;
141 break;141 break;
drivers/gpu/drm/tilcdc/tilcdc_crtc.c+1−1
@@ -386,7 +386,7 @@ static void tilcdc_crtc_set_mode(struct drm_crtc *crtc) · 385 unmodified lines
386 case DRM_FORMAT_XBGR8888:386 case DRM_FORMAT_XBGR8888:
387 case DRM_FORMAT_XRGB8888:387 case DRM_FORMAT_XRGB8888:
388 reg |= LCDC_V2_TFT_24BPP_UNPACK;388 reg |= LCDC_V2_TFT_24BPP_UNPACK;
389 /* fallthrough */389 fallthrough;
390 case DRM_FORMAT_BGR888:390 case DRM_FORMAT_BGR888:
391 case DRM_FORMAT_RGB888:391 case DRM_FORMAT_RGB888:
392 reg |= LCDC_V2_TFT_24BPP_MODE;392 reg |= LCDC_V2_TFT_24BPP_MODE;
drivers/gpu/drm/ttm/ttm_bo_vm.c+1−1
@@ -525,7 +525,7 @@ int ttm_bo_vm_access(struct vm_area_struct *vma, unsigned long addr, · 524 unmodified lines
525 if (unlikely(ret != 0))525 if (unlikely(ret != 0))
526 return ret;526 return ret;
527 }527 }
528 /* fall through */528 fallthrough;
529 case TTM_PL_TT:529 case TTM_PL_TT:
530 ret = ttm_bo_vm_access_kmap(bo, offset, buf, len, write);530 ret = ttm_bo_vm_access_kmap(bo, offset, buf, len, write);
531 break;531 break;
drivers/gpu/drm/via/via_dmablit.c+4−4
@@ -179,21 +179,21 @@ via_free_sg_info(struct pci_dev *pdev, drm_via_sg_info_t *vsg) · 178 unmodified lines
179 switch (vsg->state) {179 switch (vsg->state) {
180 case dr_via_device_mapped:180 case dr_via_device_mapped:
181 via_unmap_blit_from_device(pdev, vsg);181 via_unmap_blit_from_device(pdev, vsg);
182 /* fall through */182 fallthrough;
183 case dr_via_desc_pages_alloc:183 case dr_via_desc_pages_alloc:
184 for (i = 0; i < vsg->num_desc_pages; ++i) {184 for (i = 0; i < vsg->num_desc_pages; ++i) {
185 if (vsg->desc_pages[i] != NULL)185 if (vsg->desc_pages[i] != NULL)
186 free_page((unsigned long)vsg->desc_pages[i]);186 free_page((unsigned long)vsg->desc_pages[i]);
187 }187 }
188 kfree(vsg->desc_pages);188 kfree(vsg->desc_pages);
189 /* fall through */189 fallthrough;
190 case dr_via_pages_locked:190 case dr_via_pages_locked:
191 unpin_user_pages_dirty_lock(vsg->pages, vsg->num_pages,191 unpin_user_pages_dirty_lock(vsg->pages, vsg->num_pages,
192 (vsg->direction == DMA_FROM_DEVICE));192 (vsg->direction == DMA_FROM_DEVICE));
193 /* fall through */193 fallthrough;
194 case dr_via_pages_alloc:194 case dr_via_pages_alloc:
195 vfree(vsg->pages);195 vfree(vsg->pages);
196 /* fall through */196 fallthrough;
197 default:197 default:
198 vsg->state = dr_via_sg_init;198 vsg->state = dr_via_sg_init;
199 }199 }
drivers/gpu/drm/virtio/virtgpu_ioctl.c+1−0
@@ -179,6 +179,7 @@ static int virtio_gpu_execbuffer_ioctl(struct drm_device *dev, void *data, · 178 unmodified lines
179 179
180 virtio_gpu_cmd_submit(vgdev, buf, exbuf->size,180 virtio_gpu_cmd_submit(vgdev, buf, exbuf->size,
181 vfpriv->ctx_id, buflist, out_fence);181 vfpriv->ctx_id, buflist, out_fence);
182 dma_fence_put(&out_fence->f);
182 virtio_gpu_notify(vgdev);183 virtio_gpu_notify(vgdev);
183 return 0;184 return 0;
184 185
drivers/gpu/drm/virtio/virtgpu_object.c+1−0
@@ -79,6 +79,7 @@ void virtio_gpu_cleanup_object(struct virtio_gpu_object *bo) · 78 unmodified lines
79 }79 }
80 80
81 sg_free_table(shmem->pages);81 sg_free_table(shmem->pages);
82 kfree(shmem->pages);
82 shmem->pages = NULL;83 shmem->pages = NULL;
83 drm_gem_shmem_unpin(&bo->base.base);84 drm_gem_shmem_unpin(&bo->base.base);
84 }85 }
drivers/gpu/drm/xen/xen_drm_front.c+0−3
@@ -649,9 +649,7 @@ static void displback_changed(struct xenbus_device *xb_dev, · 648 unmodified lines
649 649
650 switch (backend_state) {650 switch (backend_state) {
651 case XenbusStateReconfiguring:651 case XenbusStateReconfiguring:
652 /* fall through */
653 case XenbusStateReconfigured:652 case XenbusStateReconfigured:
654 /* fall through */
655 case XenbusStateInitialised:653 case XenbusStateInitialised:
656 break;654 break;
657 655
@@ -701,7 +699,6 @@ static void displback_changed(struct xenbus_device *xb_dev, · 43 unmodified lines
701 break;699 break;
702 700
703 case XenbusStateUnknown:701 case XenbusStateUnknown:
704 /* fall through */
705 case XenbusStateClosed:702 case XenbusStateClosed:
706 if (xb_dev->state == XenbusStateClosed)703 if (xb_dev->state == XenbusStateClosed)
707 break;704 break;
drivers/gpu/drm/xen/xen_drm_front_gem.c+5−4
@@ -18,6 +18,7 @@ · 17 unmodified lines
18#include <drm/drm_probe_helper.h>18#include <drm/drm_probe_helper.h>
19 19
20#include <xen/balloon.h>20#include <xen/balloon.h>
21#include <xen/xen.h>
21 22
22#include "xen_drm_front.h"23#include "xen_drm_front.h"
23#include "xen_drm_front_gem.h"24#include "xen_drm_front_gem.h"
@@ -99,8 +100,8 @@ static struct xen_gem_object *gem_create(struct drm_device *dev, size_t size) · 75 unmodified lines
99 * allocate ballooned pages which will be used to map100 * allocate ballooned pages which will be used to map
100 * grant references provided by the backend101 * grant references provided by the backend
101 */102 */
102 ret = alloc_xenballooned_pages(xen_obj->num_pages,103 ret = xen_alloc_unpopulated_pages(xen_obj->num_pages,
103 xen_obj->pages);104 xen_obj->pages);
104 if (ret < 0) {105 if (ret < 0) {
105 DRM_ERROR("Cannot allocate %zu ballooned pages: %d\n",106 DRM_ERROR("Cannot allocate %zu ballooned pages: %d\n",
106 xen_obj->num_pages, ret);107 xen_obj->num_pages, ret);
@@ -152,8 +153,8 @@ void xen_drm_front_gem_free_object_unlocked(struct drm_gem_object *gem_obj) · 45 unmodified lines
152 } else {153 } else {
153 if (xen_obj->pages) {154 if (xen_obj->pages) {
154 if (xen_obj->be_alloc) {155 if (xen_obj->be_alloc) {
155 free_xenballooned_pages(xen_obj->num_pages,156 xen_free_unpopulated_pages(xen_obj->num_pages,
156 xen_obj->pages);157 xen_obj->pages);
157 gem_free_pages_array(xen_obj);158 gem_free_pages_array(xen_obj);
158 } else {159 } else {
159 drm_gem_put_pages(&xen_obj->base,160 drm_gem_put_pages(&xen_obj->base,
drivers/gpu/ipu-v3/ipu-dc.c+1−1
@@ -141,7 +141,7 @@ static int ipu_bus_format_to_map(u32 fmt) · 140 unmodified lines
141 switch (fmt) {141 switch (fmt) {
142 default:142 default:
143 WARN_ON(1);143 WARN_ON(1);
144 /* fall-through */144 fallthrough;
145 case MEDIA_BUS_FMT_RGB888_1X24:145 case MEDIA_BUS_FMT_RGB888_1X24:
146 return IPU_DC_MAP_RGB24;146 return IPU_DC_MAP_RGB24;
147 case MEDIA_BUS_FMT_RGB565_1X16:147 case MEDIA_BUS_FMT_RGB565_1X16:
drivers/hid/hid-core.c+13−2
@@ -1597,6 +1597,17 @@ static void hid_output_field(const struct hid_device *hid, · 1596 unmodified lines
1597 }1597 }
1598}1598}
1599 1599
1600/*
1601 * Compute the size of a report.
1602 */
1603static size_t hid_compute_report_size(struct hid_report *report)
1604{
1605 if (report->size)
1606 return ((report->size - 1) >> 3) + 1;
1607
1608 return 0;
1609}
1610
1600/*1611/*
1601 * Create a report. 'data' has to be allocated using1612 * Create a report. 'data' has to be allocated using
1602 * hid_alloc_report_buf() so that it has proper size.1613 * hid_alloc_report_buf() so that it has proper size.
@@ -1609,7 +1620,7 @@ void hid_output_report(struct hid_report *report, __u8 *data) · 6 unmodified lines
1609 if (report->id > 0)1620 if (report->id > 0)
1610 *data++ = report->id;1621 *data++ = report->id;
1611 1622
1612 memset(data, 0, ((report->size - 1) >> 3) + 1);1623 memset(data, 0, hid_compute_report_size(report));
1613 for (n = 0; n < report->maxfield; n++)1624 for (n = 0; n < report->maxfield; n++)
1614 hid_output_field(report->device, report->field[n], data);1625 hid_output_field(report->device, report->field[n], data);
1615}1626}
@@ -1739,7 +1750,7 @@ int hid_report_raw_event(struct hid_device *hid, int type, u8 *data, u32 size, · 123 unmodified lines
1739 csize--;1750 csize--;
1740 }1751 }
1741 1752
1742 rsize = ((report->size - 1) >> 3) + 1;1753 rsize = hid_compute_report_size(report);
1743 1754
1744 if (report_enum->numbered && rsize >= HID_MAX_BUFFER_SIZE)1755 if (report_enum->numbered && rsize >= HID_MAX_BUFFER_SIZE)
1745 rsize = HID_MAX_BUFFER_SIZE - 1;1756 rsize = HID_MAX_BUFFER_SIZE - 1;
drivers/hid/hid-cougar.c+1−1
@@ -321,7 +321,7 @@ static const struct kernel_param_ops cougar_g6_is_space_ops = { · 320 unmodified lines
321};321};
322module_param_cb(g6_is_space, &cougar_g6_is_space_ops, &g6_is_space, 0644);322module_param_cb(g6_is_space, &cougar_g6_is_space_ops, &g6_is_space, 0644);
323 323
324static struct hid_device_id cougar_id_table[] = {324static const struct hid_device_id cougar_id_table[] = {
325 { HID_USB_DEVICE(USB_VENDOR_ID_SOLID_YEAR,325 { HID_USB_DEVICE(USB_VENDOR_ID_SOLID_YEAR,
326 USB_DEVICE_ID_COUGAR_500K_GAMING_KEYBOARD) },326 USB_DEVICE_ID_COUGAR_500K_GAMING_KEYBOARD) },
327 { HID_USB_DEVICE(USB_VENDOR_ID_SOLID_YEAR,327 { HID_USB_DEVICE(USB_VENDOR_ID_SOLID_YEAR,
drivers/hid/hid-elan.c+2−0
@@ -188,6 +188,7 @@ static int elan_input_configured(struct hid_device *hdev, struct hid_input *hi) · 187 unmodified lines
188 ret = input_mt_init_slots(input, ELAN_MAX_FINGERS, INPUT_MT_POINTER);188 ret = input_mt_init_slots(input, ELAN_MAX_FINGERS, INPUT_MT_POINTER);
189 if (ret) {189 if (ret) {
190 hid_err(hdev, "Failed to init elan MT slots: %d\n", ret);190 hid_err(hdev, "Failed to init elan MT slots: %d\n", ret);
191 input_free_device(input);
191 return ret;192 return ret;
192 }193 }
193 194
@@ -198,6 +199,7 @@ static int elan_input_configured(struct hid_device *hdev, struct hid_input *hi) · 4 unmodified lines
198 if (ret) {199 if (ret) {
199 hid_err(hdev, "Failed to register elan input device: %d\n",200 hid_err(hdev, "Failed to register elan input device: %d\n",
200 ret);201 ret);
202 input_mt_destroy_slots(input);
201 input_free_device(input);203 input_free_device(input);
202 return ret;204 return ret;
203 }205 }
drivers/hid/hid-ids.h+6−0
@@ -728,6 +728,9 @@ · 727 unmodified lines
728#define USB_DEVICE_ID_LENOVO_TPPRODOCK 0x6067728#define USB_DEVICE_ID_LENOVO_TPPRODOCK 0x6067
729#define USB_DEVICE_ID_LENOVO_X1_COVER 0x6085729#define USB_DEVICE_ID_LENOVO_X1_COVER 0x6085
730#define USB_DEVICE_ID_LENOVO_PIXART_USB_MOUSE_608D 0x608d730#define USB_DEVICE_ID_LENOVO_PIXART_USB_MOUSE_608D 0x608d
731#define USB_DEVICE_ID_LENOVO_PIXART_USB_MOUSE_6019 0x6019
732#define USB_DEVICE_ID_LENOVO_PIXART_USB_MOUSE_602E 0x602e
733#define USB_DEVICE_ID_LENOVO_PIXART_USB_MOUSE_6093 0x6093
731 734
732#define USB_VENDOR_ID_LG 0x1fd2735#define USB_VENDOR_ID_LG 0x1fd2
733#define USB_DEVICE_ID_LG_MULTITOUCH 0x0064736#define USB_DEVICE_ID_LG_MULTITOUCH 0x0064
@@ -847,6 +850,7 @@ · 113 unmodified lines
847#define USB_DEVICE_ID_MS_POWER_COVER 0x07da850#define USB_DEVICE_ID_MS_POWER_COVER 0x07da
848#define USB_DEVICE_ID_MS_XBOX_ONE_S_CONTROLLER 0x02fd851#define USB_DEVICE_ID_MS_XBOX_ONE_S_CONTROLLER 0x02fd
849#define USB_DEVICE_ID_MS_PIXART_MOUSE 0x00cb852#define USB_DEVICE_ID_MS_PIXART_MOUSE 0x00cb
853#define USB_DEVICE_ID_8BITDO_SN30_PRO_PLUS 0x02e0
850 854
851#define USB_VENDOR_ID_MOJO 0x8282855#define USB_VENDOR_ID_MOJO 0x8282
852#define USB_DEVICE_ID_RETRO_ADAPTER 0x3201856#define USB_DEVICE_ID_RETRO_ADAPTER 0x3201
@@ -1012,6 +1016,8 @@ · 159 unmodified lines
1012#define USB_DEVICE_ID_SAITEK_RAT9 0x0cfa1016#define USB_DEVICE_ID_SAITEK_RAT9 0x0cfa
1013#define USB_DEVICE_ID_SAITEK_MMO7 0x0cd01017#define USB_DEVICE_ID_SAITEK_MMO7 0x0cd0
1014#define USB_DEVICE_ID_SAITEK_X52 0x075c1018#define USB_DEVICE_ID_SAITEK_X52 0x075c
1019#define USB_DEVICE_ID_SAITEK_X52_2 0x0255
1020#define USB_DEVICE_ID_SAITEK_X52_PRO 0x0762
1015 1021
1016#define USB_VENDOR_ID_SAMSUNG 0x04191022#define USB_VENDOR_ID_SAMSUNG 0x0419
1017#define USB_DEVICE_ID_SAMSUNG_IR_REMOTE 0x00011023#define USB_DEVICE_ID_SAMSUNG_IR_REMOTE 0x0001
drivers/hid/hid-input.c+4−0
@@ -1132,6 +1132,10 @@ static void hidinput_configure_usage(struct hid_input *hidinput, struct hid_fiel · 1131 unmodified lines
1132 }1132 }
1133 1133
1134mapped:1134mapped:
1135 /* Mapping failed, bail out */
1136 if (!bit)
1137 return;
1138
1135 if (device->driver->input_mapped &&1139 if (device->driver->input_mapped &&
1136 device->driver->input_mapped(device, hidinput, field, usage,1140 device->driver->input_mapped(device, hidinput, field, usage,
1137 &bit, &max) < 0) {1141 &bit, &max) < 0) {
drivers/hid/hid-lg-g15.c+1−1
@@ -680,7 +680,7 @@ static int lg_g15_register_led(struct lg_g15_data *g15, int i) · 679 unmodified lines
680 * but it does have a separate power-on (reset) value.680 * but it does have a separate power-on (reset) value.
681 */681 */
682 g15->leds[i].cdev.name = "g15::power_on_backlight_val";682 g15->leds[i].cdev.name = "g15::power_on_backlight_val";
683 /* fall through */683 fallthrough;
684 case LG_G15_KBD_BRIGHTNESS:684 case LG_G15_KBD_BRIGHTNESS:
685 g15->leds[i].cdev.brightness_set_blocking =685 g15->leds[i].cdev.brightness_set_blocking =
686 lg_g510_kbd_led_set;686 lg_g510_kbd_led_set;
drivers/hid/hid-logitech-dj.c+1−1
@@ -844,7 +844,7 @@ static void logi_dj_recv_queue_notification(struct dj_receiver_dev *djrcv_dev, · 843 unmodified lines
844 workitem.type = WORKITEM_TYPE_EMPTY;844 workitem.type = WORKITEM_TYPE_EMPTY;
845 break;845 break;
846 }846 }
847 /* fall-through */847 fallthrough;
848 case REPORT_TYPE_NOTIF_DEVICE_UNPAIRED:848 case REPORT_TYPE_NOTIF_DEVICE_UNPAIRED:
849 workitem.quad_id_msb =849 workitem.quad_id_msb =
850 dj_report->report_params[DEVICE_PAIRED_PARAM_EQUAD_ID_MSB];850 dj_report->report_params[DEVICE_PAIRED_PARAM_EQUAD_ID_MSB];
drivers/hid/hid-macally.c+1−1
@@ -29,7 +29,7 @@ static __u8 *macally_report_fixup(struct hid_device *hdev, __u8 *rdesc, · 28 unmodified lines
29 return rdesc;29 return rdesc;
30}30}
31 31
32static struct hid_device_id macally_id_table[] = {32static const struct hid_device_id macally_id_table[] = {
33 { HID_USB_DEVICE(USB_VENDOR_ID_SOLID_YEAR,33 { HID_USB_DEVICE(USB_VENDOR_ID_SOLID_YEAR,
34 USB_DEVICE_ID_MACALLY_IKEY_KEYBOARD) },34 USB_DEVICE_ID_MACALLY_IKEY_KEYBOARD) },
35 { }35 { }
drivers/hid/hid-microsoft.c+2−3
@@ -163,16 +163,13 @@ static int ms_surface_dial_quirk(struct hid_input *hi, struct hid_field *field, · 162 unmodified lines
163{163{
164 switch (usage->hid & HID_USAGE_PAGE) {164 switch (usage->hid & HID_USAGE_PAGE) {
165 case 0xff070000:165 case 0xff070000:
166 /* fall-through */
167 case HID_UP_DIGITIZER:166 case HID_UP_DIGITIZER:
168 /* ignore those axis */167 /* ignore those axis */
169 return -1;168 return -1;
170 case HID_UP_GENDESK:169 case HID_UP_GENDESK:
171 switch (usage->hid) {170 switch (usage->hid) {
172 case HID_GD_X:171 case HID_GD_X:
173 /* fall-through */
174 case HID_GD_Y:172 case HID_GD_Y:
175 /* fall-through */
176 case HID_GD_RFKILL_BTN:173 case HID_GD_RFKILL_BTN:
177 /* ignore those axis */174 /* ignore those axis */
178 return -1;175 return -1;
@@ -451,6 +448,8 @@ static const struct hid_device_id ms_devices[] = { · 272 unmodified lines
451 .driver_data = MS_SURFACE_DIAL },448 .driver_data = MS_SURFACE_DIAL },
452 { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_XBOX_ONE_S_CONTROLLER),449 { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_XBOX_ONE_S_CONTROLLER),
453 .driver_data = MS_QUIRK_FF },450 .driver_data = MS_QUIRK_FF },
451 { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_8BITDO_SN30_PRO_PLUS),
452 .driver_data = MS_QUIRK_FF },
454 { }453 { }
455};454};
456MODULE_DEVICE_TABLE(hid, ms_devices);455MODULE_DEVICE_TABLE(hid, ms_devices);
drivers/hid/hid-multitouch.c+2−0
@@ -856,6 +856,8 @@ static int mt_touch_input_mapping(struct hid_device *hdev, struct hid_input *hi, · 855 unmodified lines
856 code = BTN_0 + ((usage->hid - 1) & HID_USAGE);856 code = BTN_0 + ((usage->hid - 1) & HID_USAGE);
857 857
858 hid_map_usage(hi, usage, bit, max, EV_KEY, code);858 hid_map_usage(hi, usage, bit, max, EV_KEY, code);
859 if (!*bit)
860 return -1;
859 input_set_capability(hi->input, EV_KEY, code);861 input_set_capability(hi->input, EV_KEY, code);
860 return 1;862 return 1;
861 863
drivers/hid/hid-quirks.c+5−0
@@ -105,6 +105,9 @@ static const struct hid_device_id hid_quirks[] = { · 104 unmodified lines
105 { HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_EASYPEN_M406XE), HID_QUIRK_MULTI_INPUT },105 { HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_EASYPEN_M406XE), HID_QUIRK_MULTI_INPUT },
106 { HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_PIXART_USB_OPTICAL_MOUSE_ID2), HID_QUIRK_ALWAYS_POLL },106 { HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_PIXART_USB_OPTICAL_MOUSE_ID2), HID_QUIRK_ALWAYS_POLL },
107 { HID_USB_DEVICE(USB_VENDOR_ID_LENOVO, USB_DEVICE_ID_LENOVO_PIXART_USB_MOUSE_608D), HID_QUIRK_ALWAYS_POLL },107 { HID_USB_DEVICE(USB_VENDOR_ID_LENOVO, USB_DEVICE_ID_LENOVO_PIXART_USB_MOUSE_608D), HID_QUIRK_ALWAYS_POLL },
108 { HID_USB_DEVICE(USB_VENDOR_ID_LENOVO, USB_DEVICE_ID_LENOVO_PIXART_USB_MOUSE_6019), HID_QUIRK_ALWAYS_POLL },
109 { HID_USB_DEVICE(USB_VENDOR_ID_LENOVO, USB_DEVICE_ID_LENOVO_PIXART_USB_MOUSE_602E), HID_QUIRK_ALWAYS_POLL },
110 { HID_USB_DEVICE(USB_VENDOR_ID_LENOVO, USB_DEVICE_ID_LENOVO_PIXART_USB_MOUSE_6093), HID_QUIRK_ALWAYS_POLL },
108 { HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_C007), HID_QUIRK_ALWAYS_POLL },111 { HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_C007), HID_QUIRK_ALWAYS_POLL },
109 { HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_C077), HID_QUIRK_ALWAYS_POLL },112 { HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_C077), HID_QUIRK_ALWAYS_POLL },
110 { HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_KEYBOARD_G710_PLUS), HID_QUIRK_NOGET },113 { HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_KEYBOARD_G710_PLUS), HID_QUIRK_NOGET },
@@ -147,6 +150,8 @@ static const struct hid_device_id hid_quirks[] = { · 36 unmodified lines
147 { HID_USB_DEVICE(USB_VENDOR_ID_RETROUSB, USB_DEVICE_ID_RETROUSB_SNES_RETROPORT), HID_QUIRK_INCREMENT_USAGE_ON_DUPLICATE },150 { HID_USB_DEVICE(USB_VENDOR_ID_RETROUSB, USB_DEVICE_ID_RETROUSB_SNES_RETROPORT), HID_QUIRK_INCREMENT_USAGE_ON_DUPLICATE },
148 { HID_USB_DEVICE(USB_VENDOR_ID_SAITEK, USB_DEVICE_ID_SAITEK_RUMBLEPAD), HID_QUIRK_BADPAD },151 { HID_USB_DEVICE(USB_VENDOR_ID_SAITEK, USB_DEVICE_ID_SAITEK_RUMBLEPAD), HID_QUIRK_BADPAD },
149 { HID_USB_DEVICE(USB_VENDOR_ID_SAITEK, USB_DEVICE_ID_SAITEK_X52), HID_QUIRK_INCREMENT_USAGE_ON_DUPLICATE },152 { HID_USB_DEVICE(USB_VENDOR_ID_SAITEK, USB_DEVICE_ID_SAITEK_X52), HID_QUIRK_INCREMENT_USAGE_ON_DUPLICATE },
153 { HID_USB_DEVICE(USB_VENDOR_ID_SAITEK, USB_DEVICE_ID_SAITEK_X52_2), HID_QUIRK_INCREMENT_USAGE_ON_DUPLICATE },
154 { HID_USB_DEVICE(USB_VENDOR_ID_SAITEK, USB_DEVICE_ID_SAITEK_X52_PRO), HID_QUIRK_INCREMENT_USAGE_ON_DUPLICATE },
150 { HID_USB_DEVICE(USB_VENDOR_ID_SEMICO, USB_DEVICE_ID_SEMICO_USB_KEYKOARD2), HID_QUIRK_NO_INIT_REPORTS },155 { HID_USB_DEVICE(USB_VENDOR_ID_SEMICO, USB_DEVICE_ID_SEMICO_USB_KEYKOARD2), HID_QUIRK_NO_INIT_REPORTS },
151 { HID_USB_DEVICE(USB_VENDOR_ID_SEMICO, USB_DEVICE_ID_SEMICO_USB_KEYKOARD), HID_QUIRK_NO_INIT_REPORTS },156 { HID_USB_DEVICE(USB_VENDOR_ID_SEMICO, USB_DEVICE_ID_SEMICO_USB_KEYKOARD), HID_QUIRK_NO_INIT_REPORTS },
152 { HID_USB_DEVICE(USB_VENDOR_ID_SENNHEISER, USB_DEVICE_ID_SENNHEISER_BTD500USB), HID_QUIRK_NOGET },157 { HID_USB_DEVICE(USB_VENDOR_ID_SENNHEISER, USB_DEVICE_ID_SENNHEISER_BTD500USB), HID_QUIRK_NOGET },
drivers/hid/hid-rmi.c+0−1
@@ -428,7 +428,6 @@ static void rmi_report(struct hid_device *hid, struct hid_report *report) · 427 unmodified lines
428 428
429 switch (report->id) {429 switch (report->id) {
430 case RMI_READ_DATA_REPORT_ID:430 case RMI_READ_DATA_REPORT_ID:
431 /* fall-through */
432 case RMI_ATTN_REPORT_ID:431 case RMI_ATTN_REPORT_ID:
433 return;432 return;
434 }433 }
drivers/hid/hid-roccat-kone.c+1−1
@@ -780,7 +780,7 @@ static void kone_keep_values_up_to_date(struct kone_device *kone, · 779 unmodified lines
780 case kone_mouse_event_switch_profile:780 case kone_mouse_event_switch_profile:
781 kone->actual_dpi = kone->profiles[event->value - 1].781 kone->actual_dpi = kone->profiles[event->value - 1].
782 startup_dpi;782 startup_dpi;
783 /* fall through */783 fallthrough;
784 case kone_mouse_event_osd_profile:784 case kone_mouse_event_osd_profile:
785 kone->actual_profile = event->value;785 kone->actual_profile = event->value;
786 break;786 break;
drivers/hid/hid-uclogic-params.c+1−1
@@ -974,7 +974,7 @@ int uclogic_params_init(struct uclogic_params *params, · 973 unmodified lines
974 }974 }
975 break;975 break;
976 }976 }
977 /* FALL THROUGH */977 fallthrough;
978 case VID_PID(USB_VENDOR_ID_HUION,978 case VID_PID(USB_VENDOR_ID_HUION,
979 USB_DEVICE_ID_HUION_TABLET):979 USB_DEVICE_ID_HUION_TABLET):
980 case VID_PID(USB_VENDOR_ID_HUION,980 case VID_PID(USB_VENDOR_ID_HUION,
drivers/hid/hid-wiimote-core.c+0−2
@@ -1672,7 +1672,6 @@ static ssize_t wiimote_ext_show(struct device *dev, · 1671 unmodified lines
1672 case WIIMOTE_EXT_GUITAR:1672 case WIIMOTE_EXT_GUITAR:
1673 return sprintf(buf, "guitar\n");1673 return sprintf(buf, "guitar\n");
1674 case WIIMOTE_EXT_UNKNOWN:1674 case WIIMOTE_EXT_UNKNOWN:
1675 /* fallthrough */
1676 default:1675 default:
1677 return sprintf(buf, "unknown\n");1676 return sprintf(buf, "unknown\n");
1678 }1677 }
@@ -1722,7 +1721,6 @@ static ssize_t wiimote_dev_show(struct device *dev, · 43 unmodified lines
1722 case WIIMOTE_DEV_PENDING:1721 case WIIMOTE_DEV_PENDING:
1723 return sprintf(buf, "pending\n");1722 return sprintf(buf, "pending\n");
1724 case WIIMOTE_DEV_UNKNOWN:1723 case WIIMOTE_DEV_UNKNOWN:
1725 /* fallthrough */
1726 default:1724 default:
1727 return sprintf(buf, "unknown\n");1725 return sprintf(buf, "unknown\n");
1728 }1726 }
drivers/hid/i2c-hid/i2c-hid-core.c+13−9
@@ -420,6 +420,19 @@ static int i2c_hid_set_power(struct i2c_client *client, int power_state) · 419 unmodified lines
420 dev_err(&client->dev, "failed to change power setting.\n");420 dev_err(&client->dev, "failed to change power setting.\n");
421 421
422set_pwr_exit:422set_pwr_exit:
423
424 /*
425 * The HID over I2C specification states that if a DEVICE needs time
426 * after the PWR_ON request, it should utilise CLOCK stretching.
427 * However, it has been observered that the Windows driver provides a
428 * 1ms sleep between the PWR_ON and RESET requests.
429 * According to Goodix Windows even waits 60 ms after (other?)
430 * PWR_ON requests. Testing has confirmed that several devices
431 * will not work properly without a delay after a PWR_ON request.
432 */
433 if (!ret && power_state == I2C_HID_PWR_ON)
434 msleep(60);
435
423 return ret;436 return ret;
424}437}
425 438
@@ -441,15 +454,6 @@ static int i2c_hid_hwreset(struct i2c_client *client) · 15 unmodified lines
441 if (ret)454 if (ret)
442 goto out_unlock;455 goto out_unlock;
443 456
444 /*
445 * The HID over I2C specification states that if a DEVICE needs time
446 * after the PWR_ON request, it should utilise CLOCK stretching.
447 * However, it has been observered that the Windows driver provides a
448 * 1ms sleep between the PWR_ON and RESET requests and that some devices
449 * rely on this.
450 */
451 usleep_range(1000, 5000);
452
453 i2c_hid_dbg(ihid, "resetting...\n");457 i2c_hid_dbg(ihid, "resetting...\n");
454 458
455 ret = i2c_hid_command(client, &hid_reset_cmd, NULL, 0);459 ret = i2c_hid_command(client, &hid_reset_cmd, NULL, 0);
drivers/hid/usbhid/hid-core.c+24−29
@@ -26,7 +26,6 @@ · 25 unmodified lines
26#include <linux/wait.h>26#include <linux/wait.h>
27#include <linux/workqueue.h>27#include <linux/workqueue.h>
28#include <linux/string.h>28#include <linux/string.h>
29#include <linux/timekeeping.h>
30 29
31#include <linux/usb.h>30#include <linux/usb.h>
32 31
@@ -96,18 +95,6 @@ static int hid_start_in(struct hid_device *hid) · 63 unmodified lines
96 set_bit(HID_NO_BANDWIDTH, &usbhid->iofl);95 set_bit(HID_NO_BANDWIDTH, &usbhid->iofl);
97 } else {96 } else {
98 clear_bit(HID_NO_BANDWIDTH, &usbhid->iofl);97 clear_bit(HID_NO_BANDWIDTH, &usbhid->iofl);
99
100 if (test_bit(HID_RESUME_RUNNING, &usbhid->iofl)) {
101 /*
102 * In case events are generated while nobody was
103 * listening, some are released when the device
104 * is re-opened. Wait 50 msec for the queue to
105 * empty before allowing events to go through
106 * hid.
107 */
108 usbhid->input_start_time =
109 ktime_add_ms(ktime_get_coarse(), 50);
110 }
111 }98 }
112 }99 }
113 spin_unlock_irqrestore(&usbhid->lock, flags);100 spin_unlock_irqrestore(&usbhid->lock, flags);
@@ -293,23 +280,20 @@ static void hid_irq_in(struct urb *urb) · 179 unmodified lines
293 if (!test_bit(HID_OPENED, &usbhid->iofl))280 if (!test_bit(HID_OPENED, &usbhid->iofl))
294 break;281 break;
295 usbhid_mark_busy(usbhid);282 usbhid_mark_busy(usbhid);
296 if (test_bit(HID_RESUME_RUNNING, &usbhid->iofl)) {283 if (!test_bit(HID_RESUME_RUNNING, &usbhid->iofl)) {
297 if (ktime_before(ktime_get_coarse(),284 hid_input_report(urb->context, HID_INPUT_REPORT,
298 usbhid->input_start_time))285 urb->transfer_buffer,
299 break;286 urb->actual_length, 1);
300 clear_bit(HID_RESUME_RUNNING, &usbhid->iofl);287 /*
288 * autosuspend refused while keys are pressed
289 * because most keyboards don't wake up when
290 * a key is released
291 */
292 if (hid_check_keys_pressed(hid))
293 set_bit(HID_KEYS_PRESSED, &usbhid->iofl);
294 else
295 clear_bit(HID_KEYS_PRESSED, &usbhid->iofl);
301 }296 }
302 hid_input_report(urb->context, HID_INPUT_REPORT,
303 urb->transfer_buffer, urb->actual_length, 1);
304 /*
305 * autosuspend refused while keys are pressed
306 * because most keyboards don't wake up when
307 * a key is released
308 */
309 if (hid_check_keys_pressed(hid))
310 set_bit(HID_KEYS_PRESSED, &usbhid->iofl);
311 else
312 clear_bit(HID_KEYS_PRESSED, &usbhid->iofl);
313 break;297 break;
314 case -EPIPE: /* stall */298 case -EPIPE: /* stall */
315 usbhid_mark_busy(usbhid);299 usbhid_mark_busy(usbhid);
@@ -736,6 +720,17 @@ static int usbhid_open(struct hid_device *hid) · 420 unmodified lines
736 720
737 usb_autopm_put_interface(usbhid->intf);721 usb_autopm_put_interface(usbhid->intf);
738 722
723 /*
724 * In case events are generated while nobody was listening,
725 * some are released when the device is re-opened.
726 * Wait 50 msec for the queue to empty before allowing events
727 * to go through hid.
728 */
729 if (res == 0)
730 msleep(50);
731
732 clear_bit(HID_RESUME_RUNNING, &usbhid->iofl);
733
739 Done:734 Done:
740 mutex_unlock(&usbhid->mutex);735 mutex_unlock(&usbhid->mutex);
741 return res;736 return res;
drivers/hid/usbhid/hiddev.c+4−1
@@ -519,12 +519,16 @@ static noinline int hiddev_ioctl_usage(struct hiddev *hiddev, unsigned int cmd, · 518 unmodified lines
519 519
520 switch (cmd) {520 switch (cmd) {
521 case HIDIOCGUSAGE:521 case HIDIOCGUSAGE:
522 if (uref->usage_index >= field->report_count)
523 goto inval;
522 uref->value = field->value[uref->usage_index];524 uref->value = field->value[uref->usage_index];
523 if (copy_to_user(user_arg, uref, sizeof(*uref)))525 if (copy_to_user(user_arg, uref, sizeof(*uref)))
524 goto fault;526 goto fault;
525 goto goodreturn;527 goto goodreturn;
526 528
527 case HIDIOCSUSAGE:529 case HIDIOCSUSAGE:
530 if (uref->usage_index >= field->report_count)
531 goto inval;
528 field->value[uref->usage_index] = uref->value;532 field->value[uref->usage_index] = uref->value;
529 goto goodreturn;533 goto goodreturn;
530 534
@@ -781,7 +785,6 @@ static long hiddev_ioctl(struct file *file, unsigned int cmd, unsigned long arg) · 250 unmodified lines
781 break;785 break;
782 786
783 case HIDIOCGUCODE:787 case HIDIOCGUCODE:
784 /* fall through */
785 case HIDIOCGUSAGE:788 case HIDIOCGUSAGE:
786 case HIDIOCSUSAGE:789 case HIDIOCSUSAGE:
787 case HIDIOCGUSAGES:790 case HIDIOCGUSAGES:
drivers/hid/usbhid/usbhid.h+0−2
@@ -13,7 +13,6 @@ · 12 unmodified lines
13 13
14#include <linux/types.h>14#include <linux/types.h>
15#include <linux/slab.h>15#include <linux/slab.h>
16#include <linux/ktime.h>
17#include <linux/list.h>16#include <linux/list.h>
18#include <linux/mutex.h>17#include <linux/mutex.h>
19#include <linux/timer.h>18#include <linux/timer.h>
@@ -84,7 +83,6 @@ struct usbhid_device { · 64 unmodified lines
84 struct mutex mutex; /* start/stop/open/close */83 struct mutex mutex; /* start/stop/open/close */
85 spinlock_t lock; /* fifo spinlock */84 spinlock_t lock; /* fifo spinlock */
86 unsigned long iofl; /* I/O flags (CTRL_RUNNING, OUT_RUNNING) */85 unsigned long iofl; /* I/O flags (CTRL_RUNNING, OUT_RUNNING) */
87 ktime_t input_start_time; /* When to start handling input */
88 struct timer_list io_retry; /* Retry timer */86 struct timer_list io_retry; /* Retry timer */
89 unsigned long stop_retry; /* Time to give up, in jiffies */87 unsigned long stop_retry; /* Time to give up, in jiffies */
90 unsigned int retry_delay; /* Delay length in ms */88 unsigned int retry_delay; /* Delay length in ms */
drivers/hid/wacom_wac.c+16−16
@@ -341,7 +341,7 @@ static int wacom_graphire_irq(struct wacom_wac *wacom) · 340 unmodified lines
341 341
342 case 2: /* Mouse with wheel */342 case 2: /* Mouse with wheel */
343 input_report_key(input, BTN_MIDDLE, data[1] & 0x04);343 input_report_key(input, BTN_MIDDLE, data[1] & 0x04);
344 /* fall through */344 fallthrough;
345 345
346 case 3: /* Mouse without wheel */346 case 3: /* Mouse without wheel */
347 wacom->tool[0] = BTN_TOOL_MOUSE;347 wacom->tool[0] = BTN_TOOL_MOUSE;
@@ -1201,7 +1201,7 @@ static int wacom_intuos_bt_irq(struct wacom_wac *wacom, size_t len) · 853 unmodified lines
1201 case 0x04:1201 case 0x04:
1202 wacom_intuos_bt_process_data(wacom, data + i);1202 wacom_intuos_bt_process_data(wacom, data + i);
1203 i += 10;1203 i += 10;
1204 /* fall through */1204 fallthrough;
1205 case 0x03:1205 case 0x03:
1206 wacom_intuos_bt_process_data(wacom, data + i);1206 wacom_intuos_bt_process_data(wacom, data + i);
1207 i += 10;1207 i += 10;
@@ -2148,7 +2148,7 @@ static void wacom_wac_pad_event(struct hid_device *hdev, struct hid_field *field · 940 unmodified lines
2148 for (i = 0; i < wacom->led.count; i++)2148 for (i = 0; i < wacom->led.count; i++)
2149 wacom_update_led(wacom, features->numbered_buttons,2149 wacom_update_led(wacom, features->numbered_buttons,
2150 value, i);2150 value, i);
2151 /* fall through*/2151 fallthrough;
2152 default:2152 default:
2153 do_report = true;2153 do_report = true;
2154 break;2154 break;
@@ -3602,14 +3602,14 @@ int wacom_setup_pen_input_capabilities(struct input_dev *input_dev, · 1447 unmodified lines
3602 switch (features->type) {3602 switch (features->type) {
3603 case GRAPHIRE_BT:3603 case GRAPHIRE_BT:
3604 __clear_bit(ABS_MISC, input_dev->absbit);3604 __clear_bit(ABS_MISC, input_dev->absbit);
3605 /* fall through */3605 fallthrough;
3606 3606
3607 case WACOM_MO:3607 case WACOM_MO:
3608 case WACOM_G4:3608 case WACOM_G4:
3609 input_set_abs_params(input_dev, ABS_DISTANCE, 0,3609 input_set_abs_params(input_dev, ABS_DISTANCE, 0,
3610 features->distance_max,3610 features->distance_max,
3611 features->distance_fuzz, 0);3611 features->distance_fuzz, 0);
3612 /* fall through */3612 fallthrough;
3613 3613
3614 case GRAPHIRE:3614 case GRAPHIRE:
3615 input_set_capability(input_dev, EV_REL, REL_WHEEL);3615 input_set_capability(input_dev, EV_REL, REL_WHEEL);
@@ -3649,7 +3649,7 @@ int wacom_setup_pen_input_capabilities(struct input_dev *input_dev, · 33 unmodified lines
3649 case INTUOS4S:3649 case INTUOS4S:
3650 input_set_abs_params(input_dev, ABS_Z, -900, 899, 0, 0);3650 input_set_abs_params(input_dev, ABS_Z, -900, 899, 0, 0);
3651 input_abs_set_res(input_dev, ABS_Z, 287);3651 input_abs_set_res(input_dev, ABS_Z, 287);
3652 /* fall through */3652 fallthrough;
3653 3653
3654 case INTUOS:3654 case INTUOS:
3655 wacom_setup_intuos(wacom_wac);3655 wacom_setup_intuos(wacom_wac);
@@ -3682,7 +3682,7 @@ int wacom_setup_pen_input_capabilities(struct input_dev *input_dev, · 26 unmodified lines
3682 case TABLETPC:3682 case TABLETPC:
3683 case TABLETPCE:3683 case TABLETPCE:
3684 __clear_bit(ABS_MISC, input_dev->absbit);3684 __clear_bit(ABS_MISC, input_dev->absbit);
3685 /* fall through */3685 fallthrough;
3686 3686
3687 case DTUS:3687 case DTUS:
3688 case DTUSX:3688 case DTUSX:
@@ -3696,7 +3696,7 @@ int wacom_setup_pen_input_capabilities(struct input_dev *input_dev, · 7 unmodified lines
3696 3696
3697 case PTU:3697 case PTU:
3698 __set_bit(BTN_STYLUS2, input_dev->keybit);3698 __set_bit(BTN_STYLUS2, input_dev->keybit);
3699 /* fall through */3699 fallthrough;
3700 3700
3701 case PENPARTNER:3701 case PENPARTNER:
3702 __set_bit(BTN_TOOL_PEN, input_dev->keybit);3702 __set_bit(BTN_TOOL_PEN, input_dev->keybit);
@@ -3799,7 +3799,7 @@ int wacom_setup_touch_input_capabilities(struct input_dev *input_dev, · 96 unmodified lines
3799 input_abs_set_res(input_dev, ABS_MT_POSITION_X, 40);3799 input_abs_set_res(input_dev, ABS_MT_POSITION_X, 40);
3800 input_abs_set_res(input_dev, ABS_MT_POSITION_Y, 40);3800 input_abs_set_res(input_dev, ABS_MT_POSITION_Y, 40);
3801 3801
3802 /* fall through */3802 fallthrough;
3803 3803
3804 case INTUOS5:3804 case INTUOS5:
3805 case INTUOS5L:3805 case INTUOS5L:
@@ -3817,7 +3817,7 @@ int wacom_setup_touch_input_capabilities(struct input_dev *input_dev, · 11 unmodified lines
3817 input_set_abs_params(input_dev, ABS_MT_WIDTH_MAJOR, 0, features->x_max, 0, 0);3817 input_set_abs_params(input_dev, ABS_MT_WIDTH_MAJOR, 0, features->x_max, 0, 0);
3818 input_set_abs_params(input_dev, ABS_MT_WIDTH_MINOR, 0, features->y_max, 0, 0);3818 input_set_abs_params(input_dev, ABS_MT_WIDTH_MINOR, 0, features->y_max, 0, 0);
3819 input_set_abs_params(input_dev, ABS_MT_ORIENTATION, 0, 1, 0, 0);3819 input_set_abs_params(input_dev, ABS_MT_ORIENTATION, 0, 1, 0, 0);
3820 /* fall through */3820 fallthrough;
3821 3821
3822 case WACOM_27QHDT:3822 case WACOM_27QHDT:
3823 if (wacom_wac->shared->touch->product == 0x32C ||3823 if (wacom_wac->shared->touch->product == 0x32C ||
@@ -3826,14 +3826,14 @@ int wacom_setup_touch_input_capabilities(struct input_dev *input_dev, · 2 unmodified lines
3826 __set_bit(SW_MUTE_DEVICE, input_dev->swbit);3826 __set_bit(SW_MUTE_DEVICE, input_dev->swbit);
3827 wacom_wac->shared->has_mute_touch_switch = true;3827 wacom_wac->shared->has_mute_touch_switch = true;
3828 }3828 }
3829 /* fall through */3829 fallthrough;
3830 3830
3831 case MTSCREEN:3831 case MTSCREEN:
3832 case MTTPC:3832 case MTTPC:
3833 case MTTPC_B:3833 case MTTPC_B:
3834 case TABLETPC2FG:3834 case TABLETPC2FG:
3835 input_mt_init_slots(input_dev, features->touch_max, INPUT_MT_DIRECT);3835 input_mt_init_slots(input_dev, features->touch_max, INPUT_MT_DIRECT);
3836 /*fall through */3836 fallthrough;
3837 3837
3838 case TABLETPC:3838 case TABLETPC:
3839 case TABLETPCE:3839 case TABLETPCE:
@@ -3843,7 +3843,7 @@ int wacom_setup_touch_input_capabilities(struct input_dev *input_dev, · 3 unmodified lines
3843 case INTUOSHT2:3843 case INTUOSHT2:
3844 input_dev->evbit[0] |= BIT_MASK(EV_SW);3844 input_dev->evbit[0] |= BIT_MASK(EV_SW);
3845 __set_bit(SW_MUTE_DEVICE, input_dev->swbit);3845 __set_bit(SW_MUTE_DEVICE, input_dev->swbit);
3846 /* fall through */3846 fallthrough;
3847 3847
3848 case BAMBOO_PT:3848 case BAMBOO_PT:
3849 case BAMBOO_TOUCH:3849 case BAMBOO_TOUCH:
@@ -4099,7 +4099,7 @@ int wacom_setup_pad_input_capabilities(struct input_dev *input_dev, · 249 unmodified lines
4099 4099
4100 __set_bit(KEY_BUTTONCONFIG, input_dev->keybit);4100 __set_bit(KEY_BUTTONCONFIG, input_dev->keybit);
4101 __set_bit(KEY_INFO, input_dev->keybit);4101 __set_bit(KEY_INFO, input_dev->keybit);
4102 /* fall through */4102 fallthrough;
4103 4103
4104 case WACOM_21UX2:4104 case WACOM_21UX2:
4105 case WACOM_BEE:4105 case WACOM_BEE:
@@ -4115,7 +4115,7 @@ int wacom_setup_pad_input_capabilities(struct input_dev *input_dev, · 9 unmodified lines
4115 case INTUOS3:4115 case INTUOS3:
4116 case INTUOS3L:4116 case INTUOS3L:
4117 input_set_abs_params(input_dev, ABS_RY, 0, 4096, 0, 0);4117 input_set_abs_params(input_dev, ABS_RY, 0, 4096, 0, 0);
4118 /* fall through */4118 fallthrough;
4119 4119
4120 case INTUOS3S:4120 case INTUOS3S:
4121 input_set_abs_params(input_dev, ABS_RX, 0, 4096, 0, 0);4121 input_set_abs_params(input_dev, ABS_RX, 0, 4096, 0, 0);
@@ -4139,7 +4139,7 @@ int wacom_setup_pad_input_capabilities(struct input_dev *input_dev, · 17 unmodified lines
4139 * ID_INPUT_TABLET to be set.4139 * ID_INPUT_TABLET to be set.
4140 */4140 */
4141 __set_bit(BTN_STYLUS, input_dev->keybit);4141 __set_bit(BTN_STYLUS, input_dev->keybit);
4142 /* fall through */4142 fallthrough;
4143 4143
4144 case INTUOS4:4144 case INTUOS4:
4145 case INTUOS4L:4145 case INTUOS4L:
drivers/hsi/clients/ssi_protocol.c+3−3
@@ -291,7 +291,7 @@ static void ssip_set_rxstate(struct ssi_protocol *ssi, unsigned int state) · 290 unmodified lines
291 /* CMT speech workaround */291 /* CMT speech workaround */
292 if (atomic_read(&ssi->tx_usecnt))292 if (atomic_read(&ssi->tx_usecnt))
293 break;293 break;
294 /* Else, fall through */294 fallthrough;
295 case RECEIVING:295 case RECEIVING:
296 mod_timer(&ssi->keep_alive, jiffies +296 mod_timer(&ssi->keep_alive, jiffies +
297 msecs_to_jiffies(SSIP_KATOUT));297 msecs_to_jiffies(SSIP_KATOUT));
@@ -466,7 +466,7 @@ static void ssip_keep_alive(struct timer_list *t) · 168 unmodified lines
466 case SEND_READY:466 case SEND_READY:
467 if (atomic_read(&ssi->tx_usecnt) == 0)467 if (atomic_read(&ssi->tx_usecnt) == 0)
468 break;468 break;
469 /* Fall through */469 fallthrough;
470 /*470 /*
471 * Workaround for cmt-speech in that case471 * Workaround for cmt-speech in that case
472 * we relay on audio timers.472 * we relay on audio timers.
@@ -668,7 +668,7 @@ static void ssip_rx_bootinforeq(struct hsi_client *cl, u32 cmd) · 195 unmodified lines
668 case ACTIVE:668 case ACTIVE:
669 dev_err(&cl->device, "Boot info req on active state\n");669 dev_err(&cl->device, "Boot info req on active state\n");
670 ssip_error(cl);670 ssip_error(cl);
671 /* Fall through */671 fallthrough;
672 case INIT:672 case INIT:
673 case HANDSHAKE:673 case HANDSHAKE:
674 spin_lock_bh(&ssi->lock);674 spin_lock_bh(&ssi->lock);
drivers/hsi/controllers/omap_ssi_core.c+1−1
@@ -296,7 +296,7 @@ static int ssi_clk_event(struct notifier_block *nb, unsigned long event, · 295 unmodified lines
296 break;296 break;
297 case ABORT_RATE_CHANGE:297 case ABORT_RATE_CHANGE:
298 dev_dbg(&ssi->device, "abort rate change\n");298 dev_dbg(&ssi->device, "abort rate change\n");
299 /* Fall through */299 fallthrough;
300 case POST_RATE_CHANGE:300 case POST_RATE_CHANGE:
301 dev_dbg(&ssi->device, "post rate change (%lu -> %lu)\n",301 dev_dbg(&ssi->device, "post rate change (%lu -> %lu)\n",
302 clk_data->old_rate, clk_data->new_rate);302 clk_data->old_rate, clk_data->new_rate);
drivers/hv/hv_kvp.c+1−1
@@ -354,7 +354,7 @@ static void process_ib_ipinfo(void *in_msg, void *out_msg, int op) · 353 unmodified lines
354 354
355 out->body.kvp_ip_val.dhcp_enabled = in->kvp_ip_val.dhcp_enabled;355 out->body.kvp_ip_val.dhcp_enabled = in->kvp_ip_val.dhcp_enabled;
356 356
357 /* fallthrough */357 fallthrough;
358 358
359 case KVP_OP_GET_IP_INFO:359 case KVP_OP_GET_IP_INFO:
360 utf16s_to_utf8s((wchar_t *)in->kvp_ip_val.adapter_id,360 utf16s_to_utf8s((wchar_t *)in->kvp_ip_val.adapter_id,
drivers/hv/hv_util.c+51−14
@@ -282,26 +282,52 @@ static struct { · 281 unmodified lines
282 spinlock_t lock;282 spinlock_t lock;
283} host_ts;283} host_ts;
284 284
285static struct timespec64 hv_get_adj_host_time(void)285static inline u64 reftime_to_ns(u64 reftime)
286{286{
287 struct timespec64 ts;287 return (reftime - WLTIMEDELTA) * 100;
288 u64 newtime, reftime;288}
289
290/*
291 * Hard coded threshold for host timesync delay: 600 seconds
292 */
293static const u64 HOST_TIMESYNC_DELAY_THRESH = 600 * (u64)NSEC_PER_SEC;
294
295static int hv_get_adj_host_time(struct timespec64 *ts)
296{
297 u64 newtime, reftime, timediff_adj;
289 unsigned long flags;298 unsigned long flags;
299 int ret = 0;
290 300
291 spin_lock_irqsave(&host_ts.lock, flags);301 spin_lock_irqsave(&host_ts.lock, flags);
292 reftime = hv_read_reference_counter();302 reftime = hv_read_reference_counter();
293 newtime = host_ts.host_time + (reftime - host_ts.ref_time);303
294 ts = ns_to_timespec64((newtime - WLTIMEDELTA) * 100);304 /*
305 * We need to let the caller know that last update from host
306 * is older than the max allowable threshold. clock_gettime()
307 * and PTP ioctl do not have a documented error that we could
308 * return for this specific case. Use ESTALE to report this.
309 */
310 timediff_adj = reftime - host_ts.ref_time;
311 if (timediff_adj * 100 > HOST_TIMESYNC_DELAY_THRESH) {
312 pr_warn_once("TIMESYNC IC: Stale time stamp, %llu nsecs old\n",
313 (timediff_adj * 100));
314 ret = -ESTALE;
315 }
316
317 newtime = host_ts.host_time + timediff_adj;
318 *ts = ns_to_timespec64(reftime_to_ns(newtime));
295 spin_unlock_irqrestore(&host_ts.lock, flags);319 spin_unlock_irqrestore(&host_ts.lock, flags);
296 320
297 return ts;321 return ret;
298}322}
299 323
300static void hv_set_host_time(struct work_struct *work)324static void hv_set_host_time(struct work_struct *work)
301{325{
302 struct timespec64 ts = hv_get_adj_host_time();
303 326
304 do_settimeofday64(&ts);327 struct timespec64 ts;
328
329 if (!hv_get_adj_host_time(&ts))
330 do_settimeofday64(&ts);
305}331}
306 332
307/*333/*
@@ -361,10 +387,23 @@ static void timesync_onchannelcallback(void *context) · 53 unmodified lines
361 struct ictimesync_ref_data *refdata;387 struct ictimesync_ref_data *refdata;
362 u8 *time_txf_buf = util_timesynch.recv_buffer;388 u8 *time_txf_buf = util_timesynch.recv_buffer;
363 389
364 vmbus_recvpacket(channel, time_txf_buf,390 /*
365 HV_HYP_PAGE_SIZE, &recvlen, &requestid);391 * Drain the ring buffer and use the last packet to update
392 * host_ts
393 */
394 while (1) {
395 int ret = vmbus_recvpacket(channel, time_txf_buf,
396 HV_HYP_PAGE_SIZE, &recvlen,
397 &requestid);
398 if (ret) {
399 pr_warn_once("TimeSync IC pkt recv failed (Err: %d)\n",
400 ret);
401 break;
402 }
403
404 if (!recvlen)
405 break;
366 406
367 if (recvlen > 0) {
368 icmsghdrp = (struct icmsg_hdr *)&time_txf_buf[407 icmsghdrp = (struct icmsg_hdr *)&time_txf_buf[
369 sizeof(struct vmbuspipe_hdr)];408 sizeof(struct vmbuspipe_hdr)];
370 409
@@ -622,9 +661,7 @@ static int hv_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) · 251 unmodified lines
622 661
623static int hv_ptp_gettime(struct ptp_clock_info *info, struct timespec64 *ts)662static int hv_ptp_gettime(struct ptp_clock_info *info, struct timespec64 *ts)
624{663{
625 *ts = hv_get_adj_host_time();664 return hv_get_adj_host_time(ts);
626
627 return 0;
628}665}
629 666
630static struct ptp_clock_info ptp_hyperv_info = {667static struct ptp_clock_info ptp_hyperv_info = {
drivers/hwmon/adt7462.c+4−4
@@ -435,7 +435,7 @@ static const char *voltage_label(struct adt7462_data *data, int which) · 434 unmodified lines
435 case 3:435 case 3:
436 return "+1.5V";436 return "+1.5V";
437 }437 }
438 /* fall through */438 fallthrough;
439 case 2:439 case 2:
440 if (!(data->pin_cfg[1] & ADT7462_PIN22_INPUT))440 if (!(data->pin_cfg[1] & ADT7462_PIN22_INPUT))
441 return "+12V3";441 return "+12V3";
@@ -493,7 +493,7 @@ static const char *voltage_label(struct adt7462_data *data, int which) · 51 unmodified lines
493 case 3:493 case 3:
494 return "+1.5";494 return "+1.5";
495 }495 }
496 /* fall through */496 fallthrough;
497 case 11:497 case 11:
498 if (data->pin_cfg[3] >> ADT7462_PIN28_SHIFT ==498 if (data->pin_cfg[3] >> ADT7462_PIN28_SHIFT ==
499 ADT7462_PIN28_VOLT &&499 ADT7462_PIN28_VOLT &&
@@ -531,7 +531,7 @@ static int voltage_multiplier(struct adt7462_data *data, int which) · 31 unmodified lines
531 case 3:531 case 3:
532 return 7800;532 return 7800;
533 }533 }
534 /* fall through */534 fallthrough;
535 case 2:535 case 2:
536 if (!(data->pin_cfg[1] & ADT7462_PIN22_INPUT))536 if (!(data->pin_cfg[1] & ADT7462_PIN22_INPUT))
537 return 62500;537 return 62500;
@@ -589,7 +589,7 @@ static int voltage_multiplier(struct adt7462_data *data, int which) · 51 unmodified lines
589 case 3:589 case 3:
590 return 7800;590 return 7800;
591 }591 }
592 /* fall through */592 fallthrough;
593 case 11:593 case 11:
594 case 12:594 case 12:
595 if (data->pin_cfg[3] >> ADT7462_PIN28_SHIFT ==595 if (data->pin_cfg[3] >> ADT7462_PIN28_SHIFT ==
drivers/hwmon/applesmc.c+16−15
@@ -753,15 +753,18 @@ static ssize_t applesmc_light_show(struct device *dev, · 752 unmodified lines
753 }753 }
754 754
755 ret = applesmc_read_key(LIGHT_SENSOR_LEFT_KEY, buffer, data_length);755 ret = applesmc_read_key(LIGHT_SENSOR_LEFT_KEY, buffer, data_length);
756 if (ret)
757 goto out;
756 /* newer macbooks report a single 10-bit bigendian value */758 /* newer macbooks report a single 10-bit bigendian value */
757 if (data_length == 10) {759 if (data_length == 10) {
758 left = be16_to_cpu(*(__be16 *)(buffer + 6)) >> 2;760 left = be16_to_cpu(*(__be16 *)(buffer + 6)) >> 2;
759 goto out;761 goto out;
760 }762 }
761 left = buffer[2];763 left = buffer[2];
764
765 ret = applesmc_read_key(LIGHT_SENSOR_RIGHT_KEY, buffer, data_length);
762 if (ret)766 if (ret)
763 goto out;767 goto out;
764 ret = applesmc_read_key(LIGHT_SENSOR_RIGHT_KEY, buffer, data_length);
765 right = buffer[2];768 right = buffer[2];
766 769
767out:770out:
@@ -810,12 +813,11 @@ static ssize_t applesmc_show_fan_speed(struct device *dev, · 42 unmodified lines
810 to_index(attr));813 to_index(attr));
811 814
812 ret = applesmc_read_key(newkey, buffer, 2);815 ret = applesmc_read_key(newkey, buffer, 2);
813 speed = ((buffer[0] << 8 | buffer[1]) >> 2);
814
815 if (ret)816 if (ret)
816 return ret;817 return ret;
817 else818
818 return snprintf(sysfsbuf, PAGE_SIZE, "%u\n", speed);819 speed = ((buffer[0] << 8 | buffer[1]) >> 2);
820 return snprintf(sysfsbuf, PAGE_SIZE, "%u\n", speed);
819}821}
820 822
821static ssize_t applesmc_store_fan_speed(struct device *dev,823static ssize_t applesmc_store_fan_speed(struct device *dev,
@@ -851,12 +853,11 @@ static ssize_t applesmc_show_fan_manual(struct device *dev, · 29 unmodified lines
851 u8 buffer[2];853 u8 buffer[2];
852 854
853 ret = applesmc_read_key(FANS_MANUAL, buffer, 2);855 ret = applesmc_read_key(FANS_MANUAL, buffer, 2);
854 manual = ((buffer[0] << 8 | buffer[1]) >> to_index(attr)) & 0x01;
855
856 if (ret)856 if (ret)
857 return ret;857 return ret;
858 else858
859 return snprintf(sysfsbuf, PAGE_SIZE, "%d\n", manual);859 manual = ((buffer[0] << 8 | buffer[1]) >> to_index(attr)) & 0x01;
860 return snprintf(sysfsbuf, PAGE_SIZE, "%d\n", manual);
860}861}
861 862
862static ssize_t applesmc_store_fan_manual(struct device *dev,863static ssize_t applesmc_store_fan_manual(struct device *dev,
@@ -872,10 +873,11 @@ static ssize_t applesmc_store_fan_manual(struct device *dev, · 9 unmodified lines
872 return -EINVAL;873 return -EINVAL;
873 874
874 ret = applesmc_read_key(FANS_MANUAL, buffer, 2);875 ret = applesmc_read_key(FANS_MANUAL, buffer, 2);
875 val = (buffer[0] << 8 | buffer[1]);
876 if (ret)876 if (ret)
877 goto out;877 goto out;
878 878
879 val = (buffer[0] << 8 | buffer[1]);
880
879 if (input)881 if (input)
880 val = val | (0x01 << to_index(attr));882 val = val | (0x01 << to_index(attr));
881 else883 else
@@ -951,13 +953,12 @@ static ssize_t applesmc_key_count_show(struct device *dev, · 69 unmodified lines
951 u32 count;953 u32 count;
952 954
953 ret = applesmc_read_key(KEY_COUNT_KEY, buffer, 4);955 ret = applesmc_read_key(KEY_COUNT_KEY, buffer, 4);
954 count = ((u32)buffer[0]<<24) + ((u32)buffer[1]<<16) +
955 ((u32)buffer[2]<<8) + buffer[3];
956
957 if (ret)956 if (ret)
958 return ret;957 return ret;
959 else958
960 return snprintf(sysfsbuf, PAGE_SIZE, "%d\n", count);959 count = ((u32)buffer[0]<<24) + ((u32)buffer[1]<<16) +
960 ((u32)buffer[2]<<8) + buffer[3];
961 return snprintf(sysfsbuf, PAGE_SIZE, "%d\n", count);
961}962}
962 963
963static ssize_t applesmc_key_at_index_read_show(struct device *dev,964static ssize_t applesmc_key_at_index_read_show(struct device *dev,
drivers/hwmon/emc1403.c+2−2
@@ -406,10 +406,10 @@ static int emc1403_probe(struct i2c_client *client, · 405 unmodified lines
406 switch (id->driver_data) {406 switch (id->driver_data) {
407 case emc1404:407 case emc1404:
408 data->groups[2] = &emc1404_group;408 data->groups[2] = &emc1404_group;
409 /* fall through */409 fallthrough;
410 case emc1403:410 case emc1403:
411 data->groups[1] = &emc1403_group;411 data->groups[1] = &emc1403_group;
412 /* fall through */412 fallthrough;
413 case emc1402:413 case emc1402:
414 data->groups[0] = &emc1402_group;414 data->groups[0] = &emc1402_group;
415 }415 }
drivers/hwmon/f71882fg.c+2−2
@@ -1285,7 +1285,7 @@ static struct f71882fg_data *f71882fg_update_device(struct device *dev) · 1284 unmodified lines
1285 data->pwm_auto_point_pwm[nr][0] =1285 data->pwm_auto_point_pwm[nr][0] =
1286 f71882fg_read8(data,1286 f71882fg_read8(data,
1287 F71882FG_REG_POINT_PWM(nr, 0));1287 F71882FG_REG_POINT_PWM(nr, 0));
1288 /* Fall through */1288 fallthrough;
1289 case f71862fg:1289 case f71862fg:
1290 data->pwm_auto_point_pwm[nr][1] =1290 data->pwm_auto_point_pwm[nr][1] =
1291 f71882fg_read8(data,1291 f71882fg_read8(data,
@@ -2442,7 +2442,7 @@ static int f71882fg_probe(struct platform_device *pdev) · 1150 unmodified lines
2442 case f71869a:2442 case f71869a:
2443 /* These always have signed auto point temps */2443 /* These always have signed auto point temps */
2444 data->auto_point_temp_signed = 1;2444 data->auto_point_temp_signed = 1;
2445 /* Fall through - to select correct fan/pwm reg bank! */2445 fallthrough; /* to select correct fan/pwm reg bank! */
2446 case f71889fg:2446 case f71889fg:
2447 case f71889ed:2447 case f71889ed:
2448 case f71889a:2448 case f71889a:
drivers/hwmon/gsc-hwmon.c+1−0
@@ -172,6 +172,7 @@ gsc_hwmon_read(struct device *dev, enum hwmon_sensor_types type, u32 attr, · 171 unmodified lines
172 case mode_temperature:172 case mode_temperature:
173 if (tmp > 0x8000)173 if (tmp > 0x8000)
174 tmp -= 0xffff;174 tmp -= 0xffff;
175 tmp *= 100; /* convert to millidegrees celsius */
175 break;176 break;
176 case mode_voltage_raw:177 case mode_voltage_raw:
177 tmp = clamp_val(tmp, 0, BIT(GSC_HWMON_RESOLUTION));178 tmp = clamp_val(tmp, 0, BIT(GSC_HWMON_RESOLUTION));
drivers/hwmon/hwmon-vid.c+2−2
@@ -96,7 +96,7 @@ int vid_from_reg(int val, u8 vrm) · 95 unmodified lines
96 val &= 0x1f;96 val &= 0x1f;
97 if (val == 0x1f)97 if (val == 0x1f)
98 return 0;98 return 0;
99 /* fall through */99 fallthrough;
100 case 25: /* AMD NPT 0Fh */100 case 25: /* AMD NPT 0Fh */
101 val &= 0x3f;101 val &= 0x3f;
102 return (val < 32) ? 1550 - 25 * val102 return (val < 32) ? 1550 - 25 * val
@@ -122,7 +122,7 @@ int vid_from_reg(int val, u8 vrm) · 19 unmodified lines
122 122
123 case 84: /* VRM 8.4 */123 case 84: /* VRM 8.4 */
124 val &= 0x0f;124 val &= 0x0f;
125 /* fall through */125 fallthrough;
126 case 82: /* VRM 8.2 */126 case 82: /* VRM 8.2 */
127 val &= 0x1f;127 val &= 0x1f;
128 return val == 0x1f ? 0 :128 return val == 0x1f ? 0 :
drivers/hwmon/ina3221.c+1−1
@@ -352,7 +352,7 @@ static int ina3221_read_curr(struct device *dev, u32 attr, · 351 unmodified lines
352 if (ret)352 if (ret)
353 return ret;353 return ret;
354 354
355 /* fall through */355 fallthrough;
356 case hwmon_curr_crit:356 case hwmon_curr_crit:
357 case hwmon_curr_max:357 case hwmon_curr_max:
358 if (!resistance_uo)358 if (!resistance_uo)
drivers/hwmon/nct6775.c+1−1
@@ -2669,7 +2669,7 @@ static void pwm_update_registers(struct nct6775_data *data, int nr) · 2668 unmodified lines
2669 case thermal_cruise:2669 case thermal_cruise:
2670 nct6775_write_value(data, data->REG_TARGET[nr],2670 nct6775_write_value(data, data->REG_TARGET[nr],
2671 data->target_temp[nr]);2671 data->target_temp[nr]);
2672 /* fall through */2672 fallthrough;
2673 default:2673 default:
2674 reg = nct6775_read_value(data, data->REG_FAN_MODE[nr]);2674 reg = nct6775_read_value(data, data->REG_FAN_MODE[nr]);
2675 reg = (reg & ~data->tolerance_mask) |2675 reg = (reg & ~data->tolerance_mask) |
drivers/hwmon/nct7904.c+2−2
@@ -231,7 +231,7 @@ static int nct7904_read_fan(struct device *dev, u32 attr, int channel, · 230 unmodified lines
231 if (ret < 0)231 if (ret < 0)
232 return ret;232 return ret;
233 cnt = ((ret & 0xff00) >> 3) | (ret & 0x1f);233 cnt = ((ret & 0xff00) >> 3) | (ret & 0x1f);
234 if (cnt == 0x1fff)234 if (cnt == 0 || cnt == 0x1fff)
235 rpm = 0;235 rpm = 0;
236 else236 else
237 rpm = 1350000 / cnt;237 rpm = 1350000 / cnt;
@@ -243,7 +243,7 @@ static int nct7904_read_fan(struct device *dev, u32 attr, int channel, · 5 unmodified lines
243 if (ret < 0)243 if (ret < 0)
244 return ret;244 return ret;
245 cnt = ((ret & 0xff00) >> 3) | (ret & 0x1f);245 cnt = ((ret & 0xff00) >> 3) | (ret & 0x1f);
246 if (cnt == 0x1fff)246 if (cnt == 0 || cnt == 0x1fff)
247 rpm = 0;247 rpm = 0;
248 else248 else
249 rpm = 1350000 / cnt;249 rpm = 1350000 / cnt;
drivers/hwmon/occ/common.c+3−3
@@ -752,7 +752,7 @@ static int occ_setup_sensor_attrs(struct occ *occ) · 751 unmodified lines
752 switch (sensors->freq.version) {752 switch (sensors->freq.version) {
753 case 2:753 case 2:
754 show_freq = occ_show_freq_2;754 show_freq = occ_show_freq_2;
755 /* fall through */755 fallthrough;
756 case 1:756 case 1:
757 num_attrs += (sensors->freq.num_sensors * 2);757 num_attrs += (sensors->freq.num_sensors * 2);
758 break;758 break;
@@ -763,7 +763,7 @@ static int occ_setup_sensor_attrs(struct occ *occ) · 4 unmodified lines
763 switch (sensors->power.version) {763 switch (sensors->power.version) {
764 case 2:764 case 2:
765 show_power = occ_show_power_2;765 show_power = occ_show_power_2;
766 /* fall through */766 fallthrough;
767 case 1:767 case 1:
768 num_attrs += (sensors->power.num_sensors * 4);768 num_attrs += (sensors->power.num_sensors * 4);
769 break;769 break;
@@ -781,7 +781,7 @@ static int occ_setup_sensor_attrs(struct occ *occ) · 11 unmodified lines
781 break;781 break;
782 case 3:782 case 3:
783 show_caps = occ_show_caps_3;783 show_caps = occ_show_caps_3;
784 /* fall through */784 fallthrough;
785 case 2:785 case 2:
786 num_attrs += (sensors->caps.num_sensors * 8);786 num_attrs += (sensors->caps.num_sensors * 8);
787 break;787 break;
drivers/hwmon/pmbus/isl68137.c+6−1
@@ -67,6 +67,7 @@ enum variants { · 66 unmodified lines
67 raa_dmpvr1_2rail,67 raa_dmpvr1_2rail,
68 raa_dmpvr2_1rail,68 raa_dmpvr2_1rail,
69 raa_dmpvr2_2rail,69 raa_dmpvr2_2rail,
70 raa_dmpvr2_2rail_nontc,
70 raa_dmpvr2_3rail,71 raa_dmpvr2_3rail,
71 raa_dmpvr2_hv,72 raa_dmpvr2_hv,
72};73};
@@ -241,6 +242,10 @@ static int isl68137_probe(struct i2c_client *client, · 168 unmodified lines
241 info->pages = 1;242 info->pages = 1;
242 info->read_word_data = raa_dmpvr2_read_word_data;243 info->read_word_data = raa_dmpvr2_read_word_data;
243 break;244 break;
245 case raa_dmpvr2_2rail_nontc:
246 info->func[0] &= ~PMBUS_HAVE_TEMP;
247 info->func[1] &= ~PMBUS_HAVE_TEMP;
248 fallthrough;
244 case raa_dmpvr2_2rail:249 case raa_dmpvr2_2rail:
245 info->pages = 2;250 info->pages = 2;
246 info->read_word_data = raa_dmpvr2_read_word_data;251 info->read_word_data = raa_dmpvr2_read_word_data;
@@ -304,7 +309,7 @@ static const struct i2c_device_id raa_dmpvr_id[] = { · 57 unmodified lines
304 {"raa228000", raa_dmpvr2_hv},309 {"raa228000", raa_dmpvr2_hv},
305 {"raa228004", raa_dmpvr2_hv},310 {"raa228004", raa_dmpvr2_hv},
306 {"raa228006", raa_dmpvr2_hv},311 {"raa228006", raa_dmpvr2_hv},
307 {"raa228228", raa_dmpvr2_2rail},312 {"raa228228", raa_dmpvr2_2rail_nontc},
308 {"raa229001", raa_dmpvr2_2rail},313 {"raa229001", raa_dmpvr2_2rail},
309 {"raa229004", raa_dmpvr2_2rail},314 {"raa229004", raa_dmpvr2_2rail},
310 {}315 {}
drivers/hwmon/w83627hf.c+1−1
@@ -1213,7 +1213,7 @@ temp_type_store(struct device *dev, struct device_attribute *devattr, · 1212 unmodified lines
1213 case W83781D_DEFAULT_BETA:1213 case W83781D_DEFAULT_BETA:
1214 dev_warn(dev, "Sensor type %d is deprecated, please use 4 "1214 dev_warn(dev, "Sensor type %d is deprecated, please use 4 "
1215 "instead\n", W83781D_DEFAULT_BETA);1215 "instead\n", W83781D_DEFAULT_BETA);
1216 /* fall through */1216 fallthrough;
1217 case 4: /* thermistor */1217 case 4: /* thermistor */
1218 tmp = w83627hf_read_value(data, W83781D_REG_SCFG1);1218 tmp = w83627hf_read_value(data, W83781D_REG_SCFG1);
1219 w83627hf_write_value(data, W83781D_REG_SCFG1,1219 w83627hf_write_value(data, W83781D_REG_SCFG1,
drivers/hwmon/w83781d.c+1−1
@@ -814,7 +814,7 @@ store_sensor(struct device *dev, struct device_attribute *da, · 813 unmodified lines
814 dev_warn(dev,814 dev_warn(dev,
815 "Sensor type %d is deprecated, please use 4 instead\n",815 "Sensor type %d is deprecated, please use 4 instead\n",
816 W83781D_DEFAULT_BETA);816 W83781D_DEFAULT_BETA);
817 /* fall through */817 fallthrough;
818 case 4: /* thermistor */818 case 4: /* thermistor */
819 tmp = w83781d_read_value(data, W83781D_REG_SCFG1);819 tmp = w83781d_read_value(data, W83781D_REG_SCFG1);
820 w83781d_write_value(data, W83781D_REG_SCFG1,820 w83781d_write_value(data, W83781D_REG_SCFG1,
drivers/hwmon/w83795.c+1−1
@@ -2127,7 +2127,7 @@ static void w83795_apply_temp_config(struct w83795_data *data, u8 config, · 2126 unmodified lines
2127 if (temp_chan >= 4)2127 if (temp_chan >= 4)
2128 break;2128 break;
2129 data->temp_mode |= 1 << temp_chan;2129 data->temp_mode |= 1 << temp_chan;
2130 /* fall through */2130 fallthrough;
2131 case 0x3: /* Thermistor */2131 case 0x3: /* Thermistor */
2132 data->has_temp |= 1 << temp_chan;2132 data->has_temp |= 1 << temp_chan;
2133 break;2133 break;
drivers/hwtracing/coresight/coresight-cpu-debug.c+2−2
@@ -346,10 +346,10 @@ static void debug_init_arch_data(void *info) · 345 unmodified lines
346 switch (mode) {346 switch (mode) {
347 case EDDEVID_IMPL_FULL:347 case EDDEVID_IMPL_FULL:
348 drvdata->edvidsr_present = true;348 drvdata->edvidsr_present = true;
349 /* Fall through */349 fallthrough;
350 case EDDEVID_IMPL_EDPCSR_EDCIDSR:350 case EDDEVID_IMPL_EDPCSR_EDCIDSR:
351 drvdata->edcidsr_present = true;351 drvdata->edcidsr_present = true;
352 /* Fall through */352 fallthrough;
353 case EDDEVID_IMPL_EDPCSR:353 case EDDEVID_IMPL_EDPCSR:
354 /*354 /*
355 * In ARM DDI 0487A.k, the EDDEVID1.PCSROffset is used to355 * In ARM DDI 0487A.k, the EDDEVID1.PCSROffset is used to
drivers/hwtracing/coresight/coresight-etm4x.c+0−1
@@ -1382,7 +1382,6 @@ static int etm4_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd, · 1381 unmodified lines
1382 return NOTIFY_BAD;1382 return NOTIFY_BAD;
1383 break;1383 break;
1384 case CPU_PM_EXIT:1384 case CPU_PM_EXIT:
1385 /* fallthrough */
1386 case CPU_PM_ENTER_FAILED:1385 case CPU_PM_ENTER_FAILED:
1387 if (drvdata->state_needs_restore)1386 if (drvdata->state_needs_restore)
1388 etm4_cpu_restore(drvdata);1387 etm4_cpu_restore(drvdata);
drivers/hwtracing/coresight/coresight-tmc.c+0−2
@@ -84,9 +84,7 @@ u32 tmc_get_memwidth_mask(struct tmc_drvdata *drvdata) · 83 unmodified lines
84 */84 */
85 switch (drvdata->memwidth) {85 switch (drvdata->memwidth) {
86 case TMC_MEM_INTF_WIDTH_32BITS:86 case TMC_MEM_INTF_WIDTH_32BITS:
87 /* fallthrough */
88 case TMC_MEM_INTF_WIDTH_64BITS:87 case TMC_MEM_INTF_WIDTH_64BITS:
89 /* fallthrough */
90 case TMC_MEM_INTF_WIDTH_128BITS:88 case TMC_MEM_INTF_WIDTH_128BITS:
91 mask = GENMASK(31, 4);89 mask = GENMASK(31, 4);
92 break;90 break;
drivers/hwtracing/intel_th/sth.c+2−2
@@ -84,11 +84,11 @@ static ssize_t notrace sth_stm_packet(struct stm_data *stm_data, · 83 unmodified lines
84 /* Global packets (GERR, XSYNC, TRIG) are sent with register writes */84 /* Global packets (GERR, XSYNC, TRIG) are sent with register writes */
85 case STP_PACKET_GERR:85 case STP_PACKET_GERR:
86 reg += 4;86 reg += 4;
87 /* fall through */87 fallthrough;
88 88
89 case STP_PACKET_XSYNC:89 case STP_PACKET_XSYNC:
90 reg += 8;90 reg += 8;
91 /* fall through */91 fallthrough;
92 92
93 case STP_PACKET_TRIG:93 case STP_PACKET_TRIG:
94 if (flags & STP_PACKET_TIMESTAMPED)94 if (flags & STP_PACKET_TIMESTAMPED)
drivers/i2c/busses/i2c-bcm-iproc.c+2−2
@@ -720,7 +720,7 @@ static int bcm_iproc_i2c_xfer_internal(struct bcm_iproc_i2c_dev *iproc_i2c, · 719 unmodified lines
720 720
721 /* mark the last byte */721 /* mark the last byte */
722 if (!process_call && (i == msg->len - 1))722 if (!process_call && (i == msg->len - 1))
723 val |= 1 << M_TX_WR_STATUS_SHIFT;723 val |= BIT(M_TX_WR_STATUS_SHIFT);
724 724
725 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);725 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
726 }726 }
@@ -738,7 +738,7 @@ static int bcm_iproc_i2c_xfer_internal(struct bcm_iproc_i2c_dev *iproc_i2c, · 11 unmodified lines
738 */738 */
739 addr = i2c_8bit_addr_from_msg(msg);739 addr = i2c_8bit_addr_from_msg(msg);
740 /* mark it the last byte out */740 /* mark it the last byte out */
741 val = addr | (1 << M_TX_WR_STATUS_SHIFT);741 val = addr | BIT(M_TX_WR_STATUS_SHIFT);
742 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);742 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
743 }743 }
744 744
drivers/i2c/busses/i2c-omap.c+0−1
@@ -1425,7 +1425,6 @@ omap_i2c_probe(struct platform_device *pdev) · 1424 unmodified lines
1425 major = OMAP_I2C_REV_SCHEME_0_MAJOR(omap->rev);1425 major = OMAP_I2C_REV_SCHEME_0_MAJOR(omap->rev);
1426 break;1426 break;
1427 case OMAP_I2C_SCHEME_1:1427 case OMAP_I2C_SCHEME_1:
1428 /* FALLTHROUGH */
1429 default:1428 default:
1430 omap->regs = (u8 *)reg_map_ip_v2;1429 omap->regs = (u8 *)reg_map_ip_v2;
1431 rev = (rev << 16) |1430 rev = (rev << 16) |
drivers/i2c/busses/i2c-opal.c+1−1
@@ -125,7 +125,7 @@ static int i2c_opal_smbus_xfer(struct i2c_adapter *adap, u16 addr, · 124 unmodified lines
125 case I2C_SMBUS_BYTE:125 case I2C_SMBUS_BYTE:
126 req.buffer_ra = cpu_to_be64(__pa(&data->byte));126 req.buffer_ra = cpu_to_be64(__pa(&data->byte));
127 req.size = cpu_to_be32(1);127 req.size = cpu_to_be32(1);
128 /* Fall through */128 fallthrough;
129 case I2C_SMBUS_QUICK:129 case I2C_SMBUS_QUICK:
130 req.type = (read_write == I2C_SMBUS_READ) ?130 req.type = (read_write == I2C_SMBUS_READ) ?
131 OPAL_I2C_RAW_READ : OPAL_I2C_RAW_WRITE;131 OPAL_I2C_RAW_READ : OPAL_I2C_RAW_WRITE;
drivers/i2c/busses/i2c-rcar.c+1−0
@@ -590,6 +590,7 @@ static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv) · 589 unmodified lines
590 /* master sent stop */590 /* master sent stop */
591 if (ssr_filtered & SSR) {591 if (ssr_filtered & SSR) {
592 i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value);592 i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value);
593 rcar_i2c_write(priv, ICSCR, SIE | SDBS); /* clear our NACK */
593 rcar_i2c_write(priv, ICSIER, SAR);594 rcar_i2c_write(priv, ICSIER, SAR);
594 rcar_i2c_write(priv, ICSSR, ~SSR & 0xff);595 rcar_i2c_write(priv, ICSSR, ~SSR & 0xff);
595 }596 }
drivers/i2c/i2c-core-acpi.c+0−10
@@ -276,16 +276,6 @@ void i2c_acpi_register_devices(struct i2c_adapter *adap) · 275 unmodified lines
276 dev_warn(&adap->dev, "failed to enumerate I2C slaves\n");276 dev_warn(&adap->dev, "failed to enumerate I2C slaves\n");
277}277}
278 278
279const struct acpi_device_id *
280i2c_acpi_match_device(const struct acpi_device_id *matches,
281 struct i2c_client *client)
282{
283 if (!(client && matches))
284 return NULL;
285
286 return acpi_match_device(matches, &client->dev);
287}
288
289static const struct acpi_device_id i2c_acpi_force_400khz_device_ids[] = {279static const struct acpi_device_id i2c_acpi_force_400khz_device_ids[] = {
290 /*280 /*
291 * These Silead touchscreen controllers only work at 400KHz, for281 * These Silead touchscreen controllers only work at 400KHz, for
drivers/i2c/i2c-core-base.c+1−1
@@ -480,7 +480,7 @@ static int i2c_device_probe(struct device *dev) · 479 unmodified lines
480 * or ACPI ID table is supplied for the probing device.480 * or ACPI ID table is supplied for the probing device.
481 */481 */
482 if (!driver->id_table &&482 if (!driver->id_table &&
483 !i2c_acpi_match_device(dev->driver->acpi_match_table, client) &&483 !acpi_driver_match_device(dev, dev->driver) &&
484 !i2c_of_match_device(dev->driver->of_match_table, client)) {484 !i2c_of_match_device(dev->driver->of_match_table, client)) {
485 status = -ENODEV;485 status = -ENODEV;
486 goto put_sync_adapter;486 goto put_sync_adapter;
drivers/i2c/i2c-core.h+0−9
@@ -59,20 +59,11 @@ static inline int __i2c_check_suspended(struct i2c_adapter *adap) · 58 unmodified lines
59}59}
60 60
61#ifdef CONFIG_ACPI61#ifdef CONFIG_ACPI
62const struct acpi_device_id *
63i2c_acpi_match_device(const struct acpi_device_id *matches,
64 struct i2c_client *client);
65void i2c_acpi_register_devices(struct i2c_adapter *adap);62void i2c_acpi_register_devices(struct i2c_adapter *adap);
66 63
67int i2c_acpi_get_irq(struct i2c_client *client);64int i2c_acpi_get_irq(struct i2c_client *client);
68#else /* CONFIG_ACPI */65#else /* CONFIG_ACPI */
69static inline void i2c_acpi_register_devices(struct i2c_adapter *adap) { }66static inline void i2c_acpi_register_devices(struct i2c_adapter *adap) { }
70static inline const struct acpi_device_id *
71i2c_acpi_match_device(const struct acpi_device_id *matches,
72 struct i2c_client *client)
73{
74 return NULL;
75}
76 67
77static inline int i2c_acpi_get_irq(struct i2c_client *client)68static inline int i2c_acpi_get_irq(struct i2c_client *client)
78{69{
drivers/i3c/master/dw-i3c-master.c+1−1
@@ -603,7 +603,7 @@ static int dw_i3c_master_bus_init(struct i3c_master_controller *m) · 602 unmodified lines
603 ret = dw_i2c_clk_cfg(master);603 ret = dw_i2c_clk_cfg(master);
604 if (ret)604 if (ret)
605 return ret;605 return ret;
606 /* fall through */606 fallthrough;
607 case I3C_BUS_MODE_PURE:607 case I3C_BUS_MODE_PURE:
608 ret = dw_i3c_clk_cfg(master);608 ret = dw_i3c_clk_cfg(master);
609 if (ret)609 if (ret)
drivers/ide/hpt366.c+3−3
@@ -575,14 +575,14 @@ static u8 hpt3xx_udma_filter(ide_drive_t *drive) · 574 unmodified lines
575 if (!HPT370_ALLOW_ATA100_5 ||575 if (!HPT370_ALLOW_ATA100_5 ||
576 check_in_drive_list(drive, bad_ata100_5))576 check_in_drive_list(drive, bad_ata100_5))
577 return ATA_UDMA4;577 return ATA_UDMA4;
578 /* fall through */578 fallthrough;
579 case HPT372 :579 case HPT372 :
580 case HPT372A:580 case HPT372A:
581 case HPT372N:581 case HPT372N:
582 case HPT374 :582 case HPT374 :
583 if (ata_id_is_sata(drive->id))583 if (ata_id_is_sata(drive->id))
584 mask &= ~0x0e;584 mask &= ~0x0e;
585 /* fall through */585 fallthrough;
586 default:586 default:
587 return mask;587 return mask;
588 }588 }
@@ -602,7 +602,7 @@ static u8 hpt3xx_mdma_filter(ide_drive_t *drive) · 13 unmodified lines
602 case HPT374 :602 case HPT374 :
603 if (ata_id_is_sata(drive->id))603 if (ata_id_is_sata(drive->id))
604 return 0x00;604 return 0x00;
605 /* fall through */605 fallthrough;
606 default:606 default:
607 return 0x07;607 return 0x07;
608 }608 }
drivers/ide/ide-cd.c+2−2
@@ -350,7 +350,7 @@ static int cdrom_decode_status(ide_drive_t *drive, u8 stat) · 349 unmodified lines
350 */350 */
351 if (scsi_req(rq)->cmd[0] == GPCMD_START_STOP_UNIT)351 if (scsi_req(rq)->cmd[0] == GPCMD_START_STOP_UNIT)
352 break;352 break;
353 /* fall-through */353 fallthrough;
354 case DATA_PROTECT:354 case DATA_PROTECT:
355 /*355 /*
356 * No point in retrying after an illegal request or data356 * No point in retrying after an illegal request or data
@@ -750,7 +750,7 @@ static ide_startstop_t cdrom_newpc_intr(ide_drive_t *drive) · 393 unmodified lines
750 case REQ_OP_DRV_IN:750 case REQ_OP_DRV_IN:
751 case REQ_OP_DRV_OUT:751 case REQ_OP_DRV_OUT:
752 expiry = ide_cd_expiry;752 expiry = ide_cd_expiry;
753 /*FALLTHRU*/753 fallthrough;
754 default:754 default:
755 timeout = ATAPI_WAIT_PC;755 timeout = ATAPI_WAIT_PC;
756 break;756 break;
drivers/ide/ide-floppy.c+1−1
@@ -428,7 +428,7 @@ static int ide_floppy_get_capacity(ide_drive_t *drive) · 427 unmodified lines
428 * (maintains previous driver behaviour)428 * (maintains previous driver behaviour)
429 */429 */
430 break;430 break;
431 /* fall through */431 fallthrough;
432 case CAPACITY_CURRENT:432 case CAPACITY_CURRENT:
433 /* Normal Zip/LS-120 disks */433 /* Normal Zip/LS-120 disks */
434 if (memcmp(cap_desc, &floppy->cap_desc, 8))434 if (memcmp(cap_desc, &floppy->cap_desc, 8))
drivers/ide/ide-probe.c+1−1
@@ -143,7 +143,7 @@ static void ide_classify_atapi_dev(ide_drive_t *drive) · 142 unmodified lines
143 }143 }
144 /* Early cdrom models used zero */144 /* Early cdrom models used zero */
145 type = ide_cdrom;145 type = ide_cdrom;
146 /* fall through */146 fallthrough;
147 case ide_cdrom:147 case ide_cdrom:
148 drive->dev_flags |= IDE_DFLAG_REMOVABLE;148 drive->dev_flags |= IDE_DFLAG_REMOVABLE;
149#ifdef CONFIG_PPC149#ifdef CONFIG_PPC
drivers/ide/ide-taskfile.c+6−6
@@ -129,7 +129,7 @@ ide_startstop_t do_rw_taskfile(ide_drive_t *drive, struct ide_cmd *orig_cmd) · 128 unmodified lines
129 return pre_task_out_intr(drive, cmd);129 return pre_task_out_intr(drive, cmd);
130 }130 }
131 handler = task_pio_intr;131 handler = task_pio_intr;
132 /* fall through */132 fallthrough;
133 case ATA_PROT_NODATA:133 case ATA_PROT_NODATA:
134 if (handler == NULL)134 if (handler == NULL)
135 handler = task_no_data_intr;135 handler = task_no_data_intr;
@@ -141,7 +141,7 @@ ide_startstop_t do_rw_taskfile(ide_drive_t *drive, struct ide_cmd *orig_cmd) · 5 unmodified lines
141 hwif->expiry = dma_ops->dma_timer_expiry;141 hwif->expiry = dma_ops->dma_timer_expiry;
142 ide_execute_command(drive, cmd, ide_dma_intr, 2 * WAIT_CMD);142 ide_execute_command(drive, cmd, ide_dma_intr, 2 * WAIT_CMD);
143 dma_ops->dma_start(drive);143 dma_ops->dma_start(drive);
144 /* fall through */144 fallthrough;
145 default:145 default:
146 return ide_started;146 return ide_started;
147 }147 }
@@ -579,10 +579,10 @@ int ide_taskfile_ioctl(ide_drive_t *drive, unsigned long arg) · 431 unmodified lines
579 goto abort;579 goto abort;
580 }580 }
581 cmd.tf_flags |= IDE_TFLAG_MULTI_PIO;581 cmd.tf_flags |= IDE_TFLAG_MULTI_PIO;
582 /* fall through */582 fallthrough;
583 case TASKFILE_OUT:583 case TASKFILE_OUT:
584 cmd.protocol = ATA_PROT_PIO;584 cmd.protocol = ATA_PROT_PIO;
585 /* fall through */585 fallthrough;
586 case TASKFILE_OUT_DMAQ:586 case TASKFILE_OUT_DMAQ:
587 case TASKFILE_OUT_DMA:587 case TASKFILE_OUT_DMA:
588 cmd.tf_flags |= IDE_TFLAG_WRITE;588 cmd.tf_flags |= IDE_TFLAG_WRITE;
@@ -598,10 +598,10 @@ int ide_taskfile_ioctl(ide_drive_t *drive, unsigned long arg) · 9 unmodified lines
598 goto abort;598 goto abort;
599 }599 }
600 cmd.tf_flags |= IDE_TFLAG_MULTI_PIO;600 cmd.tf_flags |= IDE_TFLAG_MULTI_PIO;
601 /* fall through */601 fallthrough;
602 case TASKFILE_IN:602 case TASKFILE_IN:
603 cmd.protocol = ATA_PROT_PIO;603 cmd.protocol = ATA_PROT_PIO;
604 /* fall through */604 fallthrough;
605 case TASKFILE_IN_DMAQ:605 case TASKFILE_IN_DMAQ:
606 case TASKFILE_IN_DMA:606 case TASKFILE_IN_DMA:
607 nsect = taskin / SECTOR_SIZE;607 nsect = taskin / SECTOR_SIZE;
drivers/ide/sis5513.c+1−1
@@ -494,7 +494,7 @@ static int init_chipset_sis5513(struct pci_dev *dev) · 493 unmodified lines
494 pci_read_config_byte(dev, 0x09, &reg);494 pci_read_config_byte(dev, 0x09, &reg);
495 if ((reg & 0x0f) != 0x00)495 if ((reg & 0x0f) != 0x00)
496 pci_write_config_byte(dev, 0x09, reg&0xf0);496 pci_write_config_byte(dev, 0x09, reg&0xf0);
497 /* fall through */497 fallthrough;
498 case ATA_16:498 case ATA_16:
499 /* force per drive recovery and active timings499 /* force per drive recovery and active timings
500 needed on ATA_33 and below chips */500 needed on ATA_33 and below chips */
drivers/idle/intel_idle.c+0−16
@@ -89,14 +89,6 @@ static unsigned int mwait_substates __initdata; · 88 unmodified lines
89 */89 */
90#define CPUIDLE_FLAG_ALWAYS_ENABLE BIT(15)90#define CPUIDLE_FLAG_ALWAYS_ENABLE BIT(15)
91 91
92/*
93 * Set this flag for states where the HW flushes the TLB for us
94 * and so we don't need cross-calls to keep it consistent.
95 * If this flag is set, SW flushes the TLB, so even if the
96 * HW doesn't do the flushing, this flag is safe to use.
97 */
98#define CPUIDLE_FLAG_TLB_FLUSHED BIT(16)
99
100/*92/*
101 * MWAIT takes an 8-bit "hint" in EAX "suggesting"93 * MWAIT takes an 8-bit "hint" in EAX "suggesting"
102 * the C-state (top nibble) and sub-state (bottom nibble)94 * the C-state (top nibble) and sub-state (bottom nibble)
@@ -131,14 +123,6 @@ static __cpuidle int intel_idle(struct cpuidle_device *dev, · 28 unmodified lines
131 unsigned long eax = flg2MWAIT(state->flags);123 unsigned long eax = flg2MWAIT(state->flags);
132 unsigned long ecx = 1; /* break on interrupt flag */124 unsigned long ecx = 1; /* break on interrupt flag */
133 bool tick;125 bool tick;
134 int cpu = smp_processor_id();
135
136 /*
137 * leave_mm() to avoid costly and often unnecessary wakeups
138 * for flushing the user TLB's associated with the active mm.
139 */
140 if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED)
141 leave_mm(cpu);
142 126
143 if (!static_cpu_has(X86_FEATURE_ARAT)) {127 if (!static_cpu_has(X86_FEATURE_ARAT)) {
144 /*128 /*
drivers/iio/accel/mma8452.c+1−1
@@ -1580,7 +1580,7 @@ static int mma8452_probe(struct i2c_client *client, · 1579 unmodified lines
1580 case FXLS8471_DEVICE_ID:1580 case FXLS8471_DEVICE_ID:
1581 if (ret == data->chip_info->chip_id)1581 if (ret == data->chip_info->chip_id)
1582 break;1582 break;
1583 /* fall through */1583 fallthrough;
1584 default:1584 default:
1585 ret = -ENODEV;1585 ret = -ENODEV;
1586 goto disable_regulators;1586 goto disable_regulators;
drivers/iio/adc/ab8500-gpadc.c+1−1
@@ -484,7 +484,7 @@ static int ab8500_gpadc_read(struct ab8500_gpadc *gpadc, · 483 unmodified lines
484 delay_max = 10000; /* large range optimises sleepmode */484 delay_max = 10000; /* large range optimises sleepmode */
485 break;485 break;
486 }486 }
487 /* Fall through */487 fallthrough;
488 default:488 default:
489 ctrl1 |= AB8500_GPADC_CTRL1_BUF_ENA;489 ctrl1 |= AB8500_GPADC_CTRL1_BUF_ENA;
490 break;490 break;
drivers/iio/adc/cpcap-adc.c+1−1
@@ -690,7 +690,7 @@ static void cpcap_adc_phase(struct cpcap_adc_request *req) · 689 unmodified lines
690 break;690 break;
691 case CPCAP_ADC_BATTI_PI17:691 case CPCAP_ADC_BATTI_PI17:
692 index = req->bank_index;692 index = req->bank_index;
693 /* fallthrough */693 fallthrough;
694 default:694 default:
695 req->result += conv_tbl[index].cal_offset;695 req->result += conv_tbl[index].cal_offset;
696 req->result += conv_tbl[index].align_offset;696 req->result += conv_tbl[index].align_offset;
drivers/iio/chemical/sps30.c+1−1
@@ -118,7 +118,7 @@ static int sps30_do_cmd(struct sps30_state *state, u16 cmd, u8 *data, int size) · 117 unmodified lines
118 case SPS30_READ_AUTO_CLEANING_PERIOD:118 case SPS30_READ_AUTO_CLEANING_PERIOD:
119 buf[0] = SPS30_AUTO_CLEANING_PERIOD >> 8;119 buf[0] = SPS30_AUTO_CLEANING_PERIOD >> 8;
120 buf[1] = (u8)(SPS30_AUTO_CLEANING_PERIOD & 0xff);120 buf[1] = (u8)(SPS30_AUTO_CLEANING_PERIOD & 0xff);
121 /* fall through */121 fallthrough;
122 case SPS30_READ_DATA_READY_FLAG:122 case SPS30_READ_DATA_READY_FLAG:
123 case SPS30_READ_DATA:123 case SPS30_READ_DATA:
124 case SPS30_READ_SERIAL:124 case SPS30_READ_SERIAL:
drivers/iio/dac/ad5592r-base.c+0−2
@@ -220,7 +220,6 @@ static int ad5592r_set_channel_modes(struct ad5592r_state *st) · 219 unmodified lines
220 break;220 break;
221 221
222 case CH_MODE_UNUSED:222 case CH_MODE_UNUSED:
223 /* fall-through */
224 default:223 default:
225 switch (st->channel_offstate[i]) {224 switch (st->channel_offstate[i]) {
226 case CH_OFFSTATE_OUT_TRISTATE:225 case CH_OFFSTATE_OUT_TRISTATE:
@@ -237,7 +236,6 @@ static int ad5592r_set_channel_modes(struct ad5592r_state *st) · 10 unmodified lines
237 break;236 break;
238 237
239 case CH_OFFSTATE_PULLDOWN:238 case CH_OFFSTATE_PULLDOWN:
240 /* fall-through */
241 default:239 default:
242 pulldown |= BIT(i);240 pulldown |= BIT(i);
243 break;241 break;
drivers/iio/dac/dpot-dac.c+3−2
@@ -74,11 +74,12 @@ static int dpot_dac_read_raw(struct iio_dev *indio_dev, · 73 unmodified lines
74 case IIO_VAL_INT:74 case IIO_VAL_INT:
75 /*75 /*
76 * Convert integer scale to fractional scale by76 * Convert integer scale to fractional scale by
77 * setting the denominator (val2) to one, and...77 * setting the denominator (val2) to one...
78 */78 */
79 *val2 = 1;79 *val2 = 1;
80 ret = IIO_VAL_FRACTIONAL;80 ret = IIO_VAL_FRACTIONAL;
81 /* fall through */81 /* ...and fall through. Say it again for GCC. */
82 fallthrough;
82 case IIO_VAL_FRACTIONAL:83 case IIO_VAL_FRACTIONAL:
83 *val *= regulator_get_voltage(dac->vref) / 1000;84 *val *= regulator_get_voltage(dac->vref) / 1000;
84 *val2 *= dac->max_ohms;85 *val2 *= dac->max_ohms;
drivers/iio/health/max30102.c+2−2
@@ -273,10 +273,10 @@ static int max30102_read_measurement(struct max30102_data *data, · 272 unmodified lines
273 switch (measurements) {273 switch (measurements) {
274 case 3:274 case 3:
275 MAX30102_COPY_DATA(2);275 MAX30102_COPY_DATA(2);
276 /* fall through */276 fallthrough;
277 case 2:277 case 2:
278 MAX30102_COPY_DATA(1);278 MAX30102_COPY_DATA(1);
279 /* fall through */279 fallthrough;
280 case 1:280 case 1:
281 MAX30102_COPY_DATA(0);281 MAX30102_COPY_DATA(0);
282 break;282 break;
drivers/iio/imu/adis.c+3−3
@@ -97,11 +97,11 @@ int __adis_write_reg(struct adis *adis, unsigned int reg, · 96 unmodified lines
97 adis->tx[9] = (value >> 24) & 0xff;97 adis->tx[9] = (value >> 24) & 0xff;
98 adis->tx[6] = ADIS_WRITE_REG(reg + 2);98 adis->tx[6] = ADIS_WRITE_REG(reg + 2);
99 adis->tx[7] = (value >> 16) & 0xff;99 adis->tx[7] = (value >> 16) & 0xff;
100 /* fall through */100 fallthrough;
101 case 2:101 case 2:
102 adis->tx[4] = ADIS_WRITE_REG(reg + 1);102 adis->tx[4] = ADIS_WRITE_REG(reg + 1);
103 adis->tx[5] = (value >> 8) & 0xff;103 adis->tx[5] = (value >> 8) & 0xff;
104 /* fall through */104 fallthrough;
105 case 1:105 case 1:
106 adis->tx[2] = ADIS_WRITE_REG(reg);106 adis->tx[2] = ADIS_WRITE_REG(reg);
107 adis->tx[3] = value & 0xff;107 adis->tx[3] = value & 0xff;
@@ -191,7 +191,7 @@ int __adis_read_reg(struct adis *adis, unsigned int reg, · 83 unmodified lines
191 adis->tx[2] = ADIS_READ_REG(reg + 2);191 adis->tx[2] = ADIS_READ_REG(reg + 2);
192 adis->tx[3] = 0;192 adis->tx[3] = 0;
193 spi_message_add_tail(&xfers[1], &msg);193 spi_message_add_tail(&xfers[1], &msg);
194 /* fall through */194 fallthrough;
195 case 2:195 case 2:
196 adis->tx[4] = ADIS_READ_REG(reg);196 adis->tx[4] = ADIS_READ_REG(reg);
197 adis->tx[5] = 0;197 adis->tx[5] = 0;
drivers/iio/industrialio-core.c+2−2
@@ -599,7 +599,7 @@ static ssize_t __iio_format_value(char *buf, size_t len, unsigned int type, · 598 unmodified lines
599 return scnprintf(buf, len, "%d", vals[0]);599 return scnprintf(buf, len, "%d", vals[0]);
600 case IIO_VAL_INT_PLUS_MICRO_DB:600 case IIO_VAL_INT_PLUS_MICRO_DB:
601 scale_db = true;601 scale_db = true;
602 /* fall through */602 fallthrough;
603 case IIO_VAL_INT_PLUS_MICRO:603 case IIO_VAL_INT_PLUS_MICRO:
604 if (vals[1] < 0)604 if (vals[1] < 0)
605 return scnprintf(buf, len, "-%d.%06u%s", abs(vals[0]),605 return scnprintf(buf, len, "-%d.%06u%s", abs(vals[0]),
@@ -918,7 +918,7 @@ static ssize_t iio_write_channel_info(struct device *dev, · 312 unmodified lines
918 break;918 break;
919 case IIO_VAL_INT_PLUS_MICRO_DB:919 case IIO_VAL_INT_PLUS_MICRO_DB:
920 scale_db = true;920 scale_db = true;
921 /* fall through */921 fallthrough;
922 case IIO_VAL_INT_PLUS_MICRO:922 case IIO_VAL_INT_PLUS_MICRO:
923 fract_mult = 100000;923 fract_mult = 100000;
924 break;924 break;
drivers/iio/light/si1145.c+1−1
@@ -1042,7 +1042,7 @@ static int si1145_initialize(struct si1145_data *data) · 1041 unmodified lines
1042 SI1145_LED_CURRENT_45mA);1042 SI1145_LED_CURRENT_45mA);
1043 if (ret < 0)1043 if (ret < 0)
1044 return ret;1044 return ret;
1045 /* fallthrough */1045 fallthrough;
1046 case 2:1046 case 2:
1047 ret = i2c_smbus_write_byte_data(client,1047 ret = i2c_smbus_write_byte_data(client,
1048 SI1145_REG_PS_LED21,1048 SI1145_REG_PS_LED21,
drivers/iio/magnetometer/ak8974.c+1−1
@@ -499,7 +499,7 @@ static int ak8974_detect(struct ak8974 *ak8974) · 498 unmodified lines
499 switch (whoami) {499 switch (whoami) {
500 case AK8974_WHOAMI_VALUE_AMI306:500 case AK8974_WHOAMI_VALUE_AMI306:
501 name = "ami306";501 name = "ami306";
502 /* fall-through */502 fallthrough;
503 case AK8974_WHOAMI_VALUE_AMI305:503 case AK8974_WHOAMI_VALUE_AMI305:
504 ret = regmap_read(ak8974->map, AMI305_VER, &fw);504 ret = regmap_read(ak8974->map, AMI305_VER, &fw);
505 if (ret)505 if (ret)
drivers/infiniband/core/cm.c+6−6
@@ -3034,7 +3034,7 @@ static int cm_rej_handler(struct cm_work *work) · 3033 unmodified lines
3034 case IB_CM_REP_SENT:3034 case IB_CM_REP_SENT:
3035 case IB_CM_MRA_REP_RCVD:3035 case IB_CM_MRA_REP_RCVD:
3036 ib_cancel_mad(cm_id_priv->av.port->mad_agent, cm_id_priv->msg);3036 ib_cancel_mad(cm_id_priv->av.port->mad_agent, cm_id_priv->msg);
3037 /* fall through */3037 fallthrough;
3038 case IB_CM_REQ_RCVD:3038 case IB_CM_REQ_RCVD:
3039 case IB_CM_MRA_REQ_SENT:3039 case IB_CM_MRA_REQ_SENT:
3040 if (IBA_GET(CM_REJ_REASON, rej_msg) == IB_CM_REJ_STALE_CONN)3040 if (IBA_GET(CM_REJ_REASON, rej_msg) == IB_CM_REJ_STALE_CONN)
@@ -3044,7 +3044,7 @@ static int cm_rej_handler(struct cm_work *work) · 3 unmodified lines
3044 break;3044 break;
3045 case IB_CM_DREQ_SENT:3045 case IB_CM_DREQ_SENT:
3046 ib_cancel_mad(cm_id_priv->av.port->mad_agent, cm_id_priv->msg);3046 ib_cancel_mad(cm_id_priv->av.port->mad_agent, cm_id_priv->msg);
3047 /* fall through */3047 fallthrough;
3048 case IB_CM_REP_RCVD:3048 case IB_CM_REP_RCVD:
3049 case IB_CM_MRA_REP_SENT:3049 case IB_CM_MRA_REP_SENT:
3050 cm_enter_timewait(cm_id_priv);3050 cm_enter_timewait(cm_id_priv);
@@ -3058,7 +3058,7 @@ static int cm_rej_handler(struct cm_work *work) · 7 unmodified lines
3058 cm_enter_timewait(cm_id_priv);3058 cm_enter_timewait(cm_id_priv);
3059 break;3059 break;
3060 }3060 }
3061 /* fall through */3061 fallthrough;
3062 default:3062 default:
3063 pr_debug("%s: local_id %d, cm_id_priv->id.state: %d\n",3063 pr_debug("%s: local_id %d, cm_id_priv->id.state: %d\n",
3064 __func__, be32_to_cpu(cm_id_priv->id.local_id),3064 __func__, be32_to_cpu(cm_id_priv->id.local_id),
@@ -3116,7 +3116,7 @@ int ib_send_cm_mra(struct ib_cm_id *cm_id, · 51 unmodified lines
3116 msg_response = CM_MSG_RESPONSE_OTHER;3116 msg_response = CM_MSG_RESPONSE_OTHER;
3117 break;3117 break;
3118 }3118 }
3119 /* fall through */3119 fallthrough;
3120 default:3120 default:
3121 pr_debug("%s: local_id %d, cm_id_priv->id.state: %d\n",3121 pr_debug("%s: local_id %d, cm_id_priv->id.state: %d\n",
3122 __func__, be32_to_cpu(cm_id_priv->id.local_id),3122 __func__, be32_to_cpu(cm_id_priv->id.local_id),
@@ -3227,7 +3227,7 @@ static int cm_mra_handler(struct cm_work *work) · 104 unmodified lines
3227 case IB_CM_MRA_REP_RCVD:3227 case IB_CM_MRA_REP_RCVD:
3228 atomic_long_inc(&work->port->counter_group[CM_RECV_DUPLICATES].3228 atomic_long_inc(&work->port->counter_group[CM_RECV_DUPLICATES].
3229 counter[CM_MRA_COUNTER]);3229 counter[CM_MRA_COUNTER]);
3230 /* fall through */3230 fallthrough;
3231 default:3231 default:
3232 pr_debug("%s local_id %d, cm_id_priv->id.state: %d\n",3232 pr_debug("%s local_id %d, cm_id_priv->id.state: %d\n",
3233 __func__, be32_to_cpu(cm_id_priv->id.local_id),3233 __func__, be32_to_cpu(cm_id_priv->id.local_id),
@@ -4214,7 +4214,7 @@ static int cm_init_qp_rts_attr(struct cm_id_private *cm_id_priv, · 980 unmodified lines
4214 qp_attr->retry_cnt = cm_id_priv->retry_count;4214 qp_attr->retry_cnt = cm_id_priv->retry_count;
4215 qp_attr->rnr_retry = cm_id_priv->rnr_retry_count;4215 qp_attr->rnr_retry = cm_id_priv->rnr_retry_count;
4216 qp_attr->max_rd_atomic = cm_id_priv->initiator_depth;4216 qp_attr->max_rd_atomic = cm_id_priv->initiator_depth;
4217 /* fall through */4217 fallthrough;
4218 case IB_QPT_XRC_TGT:4218 case IB_QPT_XRC_TGT:
4219 *qp_attr_mask |= IB_QP_TIMEOUT;4219 *qp_attr_mask |= IB_QP_TIMEOUT;
4220 qp_attr->timeout = cm_id_priv->av.timeout;4220 qp_attr->timeout = cm_id_priv->av.timeout;
drivers/infiniband/core/cma.c+2−1
@@ -1985,7 +1985,8 @@ static int cma_ib_handler(struct ib_cm_id *cm_id, · 1984 unmodified lines
1985 event.event = RDMA_CM_EVENT_ESTABLISHED;1985 event.event = RDMA_CM_EVENT_ESTABLISHED;
1986 break;1986 break;
1987 case IB_CM_DREQ_ERROR:1987 case IB_CM_DREQ_ERROR:
1988 event.status = -ETIMEDOUT; /* fall through */1988 event.status = -ETIMEDOUT;
1989 fallthrough;
1989 case IB_CM_DREQ_RECEIVED:1990 case IB_CM_DREQ_RECEIVED:
1990 case IB_CM_DREP_RECEIVED:1991 case IB_CM_DREP_RECEIVED:
1991 if (!cma_comp_exch(id_priv, RDMA_CM_CONNECT,1992 if (!cma_comp_exch(id_priv, RDMA_CM_CONNECT,
drivers/infiniband/core/device.c+1−1
@@ -2751,7 +2751,7 @@ static int __init ib_core_init(void) · 2750 unmodified lines
2751 2751
2752 ret = addr_init();2752 ret = addr_init();
2753 if (ret) {2753 if (ret) {
2754 pr_warn("Could't init IB address resolution\n");2754 pr_warn("Couldn't init IB address resolution\n");
2755 goto err_ibnl;2755 goto err_ibnl;
2756 }2756 }
2757 2757
drivers/infiniband/core/rw.c+0−1
@@ -510,7 +510,6 @@ struct ib_send_wr *rdma_rw_ctx_wrs(struct rdma_rw_ctx *ctx, struct ib_qp *qp, · 509 unmodified lines
510 switch (ctx->type) {510 switch (ctx->type) {
511 case RDMA_RW_SIG_MR:511 case RDMA_RW_SIG_MR:
512 case RDMA_RW_MR:512 case RDMA_RW_MR:
513 /* fallthrough */
514 for (i = 0; i < ctx->nr_ops; i++) {513 for (i = 0; i < ctx->nr_ops; i++) {
515 rdma_rw_update_lkey(&ctx->reg[i],514 rdma_rw_update_lkey(&ctx->reg[i],
516 ctx->reg[i].wr.wr.opcode !=515 ctx->reg[i].wr.wr.opcode !=
drivers/infiniband/core/ucma.c+2−2
@@ -794,7 +794,7 @@ static void ucma_copy_ib_route(struct rdma_ucm_query_route_resp *resp, · 793 unmodified lines
794 case 2:794 case 2:
795 ib_copy_path_rec_to_user(&resp->ib_route[1],795 ib_copy_path_rec_to_user(&resp->ib_route[1],
796 &route->path_rec[1]);796 &route->path_rec[1]);
797 /* fall through */797 fallthrough;
798 case 1:798 case 1:
799 ib_copy_path_rec_to_user(&resp->ib_route[0],799 ib_copy_path_rec_to_user(&resp->ib_route[0],
800 &route->path_rec[0]);800 &route->path_rec[0]);
@@ -820,7 +820,7 @@ static void ucma_copy_iboe_route(struct rdma_ucm_query_route_resp *resp, · 19 unmodified lines
820 case 2:820 case 2:
821 ib_copy_path_rec_to_user(&resp->ib_route[1],821 ib_copy_path_rec_to_user(&resp->ib_route[1],
822 &route->path_rec[1]);822 &route->path_rec[1]);
823 /* fall through */823 fallthrough;
824 case 1:824 case 1:
825 ib_copy_path_rec_to_user(&resp->ib_route[0],825 ib_copy_path_rec_to_user(&resp->ib_route[0],
826 &route->path_rec[0]);826 &route->path_rec[0]);
drivers/infiniband/core/uverbs_ioctl.c+2−2
@@ -259,7 +259,7 @@ static int uverbs_process_attr(struct bundle_priv *pbundle, · 258 unmodified lines
259 return -EOPNOTSUPP;259 return -EOPNOTSUPP;
260 260
261 e->ptr_attr.enum_id = uattr->attr_data.enum_data.elem_id;261 e->ptr_attr.enum_id = uattr->attr_data.enum_data.elem_id;
262 /* fall through */262 fallthrough;
263 case UVERBS_ATTR_TYPE_PTR_IN:263 case UVERBS_ATTR_TYPE_PTR_IN:
264 /* Ensure that any data provided by userspace beyond the known264 /* Ensure that any data provided by userspace beyond the known
265 * struct is zero. Userspace that knows how to use some future265 * struct is zero. Userspace that knows how to use some future
@@ -271,7 +271,7 @@ static int uverbs_process_attr(struct bundle_priv *pbundle, · 5 unmodified lines
271 !uverbs_is_attr_cleared(uattr, val_spec->u.ptr.len))271 !uverbs_is_attr_cleared(uattr, val_spec->u.ptr.len))
272 return -EOPNOTSUPP;272 return -EOPNOTSUPP;
273 273
274 /* fall through */274 fallthrough;
275 case UVERBS_ATTR_TYPE_PTR_OUT:275 case UVERBS_ATTR_TYPE_PTR_OUT:
276 if (uattr->len < val_spec->u.ptr.min_len ||276 if (uattr->len < val_spec->u.ptr.min_len ||
277 (!val_spec->zero_trailing &&277 (!val_spec->zero_trailing &&
drivers/infiniband/hw/bnxt_re/ib_verbs.c+1−1
@@ -2657,7 +2657,7 @@ int bnxt_re_post_send(struct ib_qp *ib_qp, const struct ib_send_wr *wr, · 2656 unmodified lines
2657 default:2657 default:
2658 break;2658 break;
2659 }2659 }
2660 /* fall through */2660 fallthrough;
2661 case IB_WR_SEND_WITH_INV:2661 case IB_WR_SEND_WITH_INV:
2662 rc = bnxt_re_build_send_wqe(qp, wr, &wqe);2662 rc = bnxt_re_build_send_wqe(qp, wr, &wqe);
2663 break;2663 break;
drivers/infiniband/hw/bnxt_re/main.c+2−1
@@ -821,7 +821,8 @@ static int bnxt_re_handle_qp_async_event(struct creq_qp_event *qp_event, · 820 unmodified lines
821 struct ib_event event;821 struct ib_event event;
822 unsigned int flags;822 unsigned int flags;
823 823
824 if (qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR) {824 if (qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR &&
825 rdma_is_kernel_res(&qp->ib_qp.res)) {
825 flags = bnxt_re_lock_cqs(qp);826 flags = bnxt_re_lock_cqs(qp);
826 bnxt_qplib_add_flush_qp(&qp->qplib_qp);827 bnxt_qplib_add_flush_qp(&qp->qplib_qp);
827 bnxt_re_unlock_cqs(qp, flags);828 bnxt_re_unlock_cqs(qp, flags);
drivers/infiniband/hw/bnxt_re/qplib_fp.c+1−1
@@ -1779,7 +1779,7 @@ int bnxt_qplib_post_send(struct bnxt_qplib_qp *qp, · 1778 unmodified lines
1779 1779
1780 break;1780 break;
1781 }1781 }
1782 /* fall thru */1782 fallthrough;
1783 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM:1783 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM:
1784 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV:1784 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV:
1785 {1785 {
drivers/infiniband/hw/cxgb4/cm.c+2−2
@@ -2885,7 +2885,7 @@ static int peer_abort(struct c4iw_dev *dev, struct sk_buff *skb) · 2884 unmodified lines
2885 case MORIBUND:2885 case MORIBUND:
2886 case CLOSING:2886 case CLOSING:
2887 stop_ep_timer(ep);2887 stop_ep_timer(ep);
2888 /*FALLTHROUGH*/2888 fallthrough;
2889 case FPDU_MODE:2889 case FPDU_MODE:
2890 if (ep->com.qp && ep->com.qp->srq) {2890 if (ep->com.qp && ep->com.qp->srq) {
2891 srqidx = ABORT_RSS_SRQIDX_G(2891 srqidx = ABORT_RSS_SRQIDX_G(
@@ -3759,7 +3759,7 @@ static void active_ofld_conn_reply(struct c4iw_dev *dev, struct sk_buff *skb, · 867 unmodified lines
3759 send_fw_act_open_req(ep, atid);3759 send_fw_act_open_req(ep, atid);
3760 return;3760 return;
3761 }3761 }
3762 /* fall through */3762 fallthrough;
3763 case FW_EADDRINUSE:3763 case FW_EADDRINUSE:
3764 set_bit(ACT_RETRY_INUSE, &ep->com.history);3764 set_bit(ACT_RETRY_INUSE, &ep->com.history);
3765 if (ep->retry_count++ < ACT_OPEN_RETRY_COUNT) {3765 if (ep->retry_count++ < ACT_OPEN_RETRY_COUNT) {
drivers/infiniband/hw/cxgb4/qp.c+1−1
@@ -1165,7 +1165,7 @@ int c4iw_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, · 1164 unmodified lines
1165 break;1165 break;
1166 }1166 }
1167 fw_flags |= FW_RI_RDMA_WRITE_WITH_IMMEDIATE;1167 fw_flags |= FW_RI_RDMA_WRITE_WITH_IMMEDIATE;
1168 /*FALLTHROUGH*/1168 fallthrough;
1169 case IB_WR_RDMA_WRITE:1169 case IB_WR_RDMA_WRITE:
1170 fw_opcode = FW_RI_RDMA_WRITE_WR;1170 fw_opcode = FW_RI_RDMA_WRITE_WR;
1171 swsqe->opcode = FW_RI_RDMA_WRITE;1171 swsqe->opcode = FW_RI_RDMA_WRITE;
drivers/infiniband/hw/hfi1/pio_copy.c+0−1
@@ -209,7 +209,6 @@ static inline void jcopy(u8 *dest, const u8 *src, u32 n) · 208 unmodified lines
209 fallthrough;209 fallthrough;
210 case 1:210 case 1:
211 *dest++ = *src++;211 *dest++ = *src++;
212 /* fall through */
213 }212 }
214}213}
215 214
drivers/infiniband/hw/hfi1/tid_rdma.c+1−0
@@ -3215,6 +3215,7 @@ bool hfi1_tid_rdma_wqe_interlock(struct rvt_qp *qp, struct rvt_swqe *wqe) · 3214 unmodified lines
3215 case IB_WR_ATOMIC_CMP_AND_SWP:3215 case IB_WR_ATOMIC_CMP_AND_SWP:
3216 case IB_WR_ATOMIC_FETCH_AND_ADD:3216 case IB_WR_ATOMIC_FETCH_AND_ADD:
3217 case IB_WR_RDMA_WRITE:3217 case IB_WR_RDMA_WRITE:
3218 case IB_WR_RDMA_WRITE_WITH_IMM:
3218 switch (prev->wr.opcode) {3219 switch (prev->wr.opcode) {
3219 case IB_WR_TID_RDMA_WRITE:3220 case IB_WR_TID_RDMA_WRITE:
3220 req = wqe_to_tid_req(prev);3221 req = wqe_to_tid_req(prev);
drivers/infiniband/hw/hns/hns_roce_device.h+0−2
@@ -65,8 +65,6 @@ · 64 unmodified lines
65#define HNS_ROCE_CQE_WCMD_EMPTY_BIT 0x265#define HNS_ROCE_CQE_WCMD_EMPTY_BIT 0x2
66#define HNS_ROCE_MIN_CQE_CNT 1666#define HNS_ROCE_MIN_CQE_CNT 16
67 67
68#define HNS_ROCE_RESERVED_SGE 1
69
70#define HNS_ROCE_MAX_IRQ_NUM 12868#define HNS_ROCE_MAX_IRQ_NUM 128
71 69
72#define HNS_ROCE_SGE_IN_WQE 270#define HNS_ROCE_SGE_IN_WQE 2
drivers/infiniband/hw/hns/hns_roce_hw_v1.c+1−1
@@ -535,7 +535,7 @@ static void hns_roce_set_sdb_ext(struct hns_roce_dev *hr_dev, u32 ext_sdb_alept, · 534 unmodified lines
535 roce_write(hr_dev, ROCEE_EXT_DB_SQ_H_REG, val);535 roce_write(hr_dev, ROCEE_EXT_DB_SQ_H_REG, val);
536 536
537 dev_dbg(dev, "ext SDB depth: 0x%x\n", db->ext_db->esdb_dep);537 dev_dbg(dev, "ext SDB depth: 0x%x\n", db->ext_db->esdb_dep);
538 dev_dbg(dev, "ext SDB threshold: epmty: 0x%x, ful: 0x%x\n",538 dev_dbg(dev, "ext SDB threshold: empty: 0x%x, ful: 0x%x\n",
539 ext_sdb_alept, ext_sdb_alful);539 ext_sdb_alept, ext_sdb_alful);
540}540}
541 541
drivers/infiniband/hw/hns/hns_roce_hw_v2.c+4−5
@@ -633,7 +633,7 @@ static int hns_roce_v2_post_recv(struct ib_qp *ibqp, · 632 unmodified lines
633 633
634 wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1);634 wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1);
635 635
636 if (unlikely(wr->num_sge >= hr_qp->rq.max_gs)) {636 if (unlikely(wr->num_sge > hr_qp->rq.max_gs)) {
637 ibdev_err(ibdev, "rq:num_sge=%d >= qp->sq.max_gs=%d\n",637 ibdev_err(ibdev, "rq:num_sge=%d >= qp->sq.max_gs=%d\n",
638 wr->num_sge, hr_qp->rq.max_gs);638 wr->num_sge, hr_qp->rq.max_gs);
639 ret = -EINVAL;639 ret = -EINVAL;
@@ -653,7 +653,6 @@ static int hns_roce_v2_post_recv(struct ib_qp *ibqp, · 13 unmodified lines
653 if (wr->num_sge < hr_qp->rq.max_gs) {653 if (wr->num_sge < hr_qp->rq.max_gs) {
654 dseg->lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY);654 dseg->lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY);
655 dseg->addr = 0;655 dseg->addr = 0;
656 dseg->len = cpu_to_le32(HNS_ROCE_INVALID_SGE_LENGTH);
657 }656 }
658 657
659 /* rq support inline data */658 /* rq support inline data */
@@ -787,8 +786,8 @@ static int hns_roce_v2_post_srq_recv(struct ib_srq *ibsrq, · 127 unmodified lines
787 }786 }
788 787
789 if (wr->num_sge < srq->max_gs) {788 if (wr->num_sge < srq->max_gs) {
790 dseg[i].len = cpu_to_le32(HNS_ROCE_INVALID_SGE_LENGTH);789 dseg[i].len = 0;
791 dseg[i].lkey = cpu_to_le32(HNS_ROCE_INVALID_LKEY);790 dseg[i].lkey = cpu_to_le32(0x100);
792 dseg[i].addr = 0;791 dseg[i].addr = 0;
793 }792 }
794 793
@@ -5070,7 +5069,7 @@ static int hns_roce_v2_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr) · 4275 unmodified lines
5070 5069
5071 attr->srq_limit = limit_wl;5070 attr->srq_limit = limit_wl;
5072 attr->max_wr = srq->wqe_cnt - 1;5071 attr->max_wr = srq->wqe_cnt - 1;
5073 attr->max_sge = srq->max_gs - HNS_ROCE_RESERVED_SGE;5072 attr->max_sge = srq->max_gs;
5074 5073
5075out:5074out:
5076 hns_roce_free_cmd_mailbox(hr_dev, mailbox);5075 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
drivers/infiniband/hw/hns/hns_roce_hw_v2.h+1−3
@@ -92,9 +92,7 @@ · 91 unmodified lines
92#define HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ PAGE_SIZE92#define HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ PAGE_SIZE
93#define HNS_ROCE_V2_PAGE_SIZE_SUPPORTED 0xFFFFF00093#define HNS_ROCE_V2_PAGE_SIZE_SUPPORTED 0xFFFFF000
94#define HNS_ROCE_V2_MAX_INNER_MTPT_NUM 294#define HNS_ROCE_V2_MAX_INNER_MTPT_NUM 2
95#define HNS_ROCE_INVALID_LKEY 0x095#define HNS_ROCE_INVALID_LKEY 0x100
96#define HNS_ROCE_INVALID_SGE_LENGTH 0x80000000
97
98#define HNS_ROCE_CMQ_TX_TIMEOUT 3000096#define HNS_ROCE_CMQ_TX_TIMEOUT 30000
99#define HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE 297#define HNS_ROCE_V2_UC_RC_SGE_NUM_IN_WQE 2
100#define HNS_ROCE_V2_RSV_QPS 898#define HNS_ROCE_V2_RSV_QPS 8
drivers/infiniband/hw/hns/hns_roce_qp.c+2−3
@@ -386,8 +386,7 @@ static int set_rq_size(struct hns_roce_dev *hr_dev, struct ib_qp_cap *cap, · 385 unmodified lines
386 return -EINVAL;386 return -EINVAL;
387 }387 }
388 388
389 hr_qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge) +389 hr_qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge));
390 HNS_ROCE_RESERVED_SGE);
391 390
392 if (hr_dev->caps.max_rq_sg <= HNS_ROCE_SGE_IN_WQE)391 if (hr_dev->caps.max_rq_sg <= HNS_ROCE_SGE_IN_WQE)
393 hr_qp->rq.wqe_shift = ilog2(hr_dev->caps.max_rq_desc_sz);392 hr_qp->rq.wqe_shift = ilog2(hr_dev->caps.max_rq_desc_sz);
@@ -402,7 +401,7 @@ static int set_rq_size(struct hns_roce_dev *hr_dev, struct ib_qp_cap *cap, · 8 unmodified lines
402 hr_qp->rq_inl_buf.wqe_cnt = 0;401 hr_qp->rq_inl_buf.wqe_cnt = 0;
403 402
404 cap->max_recv_wr = cnt;403 cap->max_recv_wr = cnt;
405 cap->max_recv_sge = hr_qp->rq.max_gs - HNS_ROCE_RESERVED_SGE;404 cap->max_recv_sge = hr_qp->rq.max_gs;
406 405
407 return 0;406 return 0;
408}407}
drivers/infiniband/hw/hns/hns_roce_srq.c+1−1
@@ -297,7 +297,7 @@ int hns_roce_create_srq(struct ib_srq *ib_srq, · 296 unmodified lines
297 spin_lock_init(&srq->lock);297 spin_lock_init(&srq->lock);
298 298
299 srq->wqe_cnt = roundup_pow_of_two(init_attr->attr.max_wr + 1);299 srq->wqe_cnt = roundup_pow_of_two(init_attr->attr.max_wr + 1);
300 srq->max_gs = init_attr->attr.max_sge + HNS_ROCE_RESERVED_SGE;300 srq->max_gs = init_attr->attr.max_sge;
301 301
302 if (udata) {302 if (udata) {
303 ret = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));303 ret = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
drivers/infiniband/hw/i40iw/i40iw_cm.c+1−1
@@ -2443,7 +2443,7 @@ static void i40iw_handle_rst_pkt(struct i40iw_cm_node *cm_node, · 2442 unmodified lines
2443 case I40IW_CM_STATE_FIN_WAIT1:2443 case I40IW_CM_STATE_FIN_WAIT1:
2444 case I40IW_CM_STATE_LAST_ACK:2444 case I40IW_CM_STATE_LAST_ACK:
2445 cm_node->cm_id->rem_ref(cm_node->cm_id);2445 cm_node->cm_id->rem_ref(cm_node->cm_id);
2446 /* fall through */2446 fallthrough;
2447 case I40IW_CM_STATE_TIME_WAIT:2447 case I40IW_CM_STATE_TIME_WAIT:
2448 cm_node->state = I40IW_CM_STATE_CLOSED;2448 cm_node->state = I40IW_CM_STATE_CLOSED;
2449 i40iw_rem_ref_cm_node(cm_node);2449 i40iw_rem_ref_cm_node(cm_node);
drivers/infiniband/hw/i40iw/i40iw_ctrl.c+2−3
@@ -1964,7 +1964,6 @@ static enum i40iw_status_code i40iw_sc_get_next_aeqe(struct i40iw_sc_aeq *aeq, · 1963 unmodified lines
1964 info->out_rdrsp = true;1964 info->out_rdrsp = true;
1965 break;1965 break;
1966 case I40IW_AE_SOURCE_RSVD:1966 case I40IW_AE_SOURCE_RSVD:
1967 /* fallthrough */
1968 default:1967 default:
1969 break;1968 break;
1970 }1969 }
@@ -3762,14 +3761,14 @@ static enum i40iw_status_code cqp_sds_wqe_fill(struct i40iw_sc_cqp *cqp, · 1791 unmodified lines
3762 LS_64(1, I40IW_CQPSQ_UPESD_ENTRY_VALID)));3761 LS_64(1, I40IW_CQPSQ_UPESD_ENTRY_VALID)));
3763 3762
3764 set_64bit_val(wqe, 56, info->entry[2].data);3763 set_64bit_val(wqe, 56, info->entry[2].data);
3765 /* fallthrough */3764 fallthrough;
3766 case 2:3765 case 2:
3767 set_64bit_val(wqe, 32,3766 set_64bit_val(wqe, 32,
3768 (LS_64(info->entry[1].cmd, I40IW_CQPSQ_UPESD_SDCMD) |3767 (LS_64(info->entry[1].cmd, I40IW_CQPSQ_UPESD_SDCMD) |
3769 LS_64(1, I40IW_CQPSQ_UPESD_ENTRY_VALID)));3768 LS_64(1, I40IW_CQPSQ_UPESD_ENTRY_VALID)));
3770 3769
3771 set_64bit_val(wqe, 40, info->entry[1].data);3770 set_64bit_val(wqe, 40, info->entry[1].data);
3772 /* fallthrough */3771 fallthrough;
3773 case 1:3772 case 1:
3774 set_64bit_val(wqe, 0,3773 set_64bit_val(wqe, 0,
3775 LS_64(info->entry[0].cmd, I40IW_CQPSQ_UPESD_SDCMD));3774 LS_64(info->entry[0].cmd, I40IW_CQPSQ_UPESD_SDCMD));
drivers/infiniband/hw/i40iw/i40iw_hw.c+1−2
@@ -353,7 +353,6 @@ void i40iw_process_aeq(struct i40iw_device *iwdev) · 352 unmodified lines
353 i40iw_cm_disconn(iwqp);353 i40iw_cm_disconn(iwqp);
354 break;354 break;
355 case I40IW_AE_BAD_CLOSE:355 case I40IW_AE_BAD_CLOSE:
356 /* fall through */
357 case I40IW_AE_RESET_SENT:356 case I40IW_AE_RESET_SENT:
358 i40iw_next_iw_state(iwqp, I40IW_QP_STATE_ERROR, 1, 0, 0);357 i40iw_next_iw_state(iwqp, I40IW_QP_STATE_ERROR, 1, 0, 0);
359 i40iw_cm_disconn(iwqp);358 i40iw_cm_disconn(iwqp);
@@ -413,7 +412,7 @@ void i40iw_process_aeq(struct i40iw_device *iwdev) · 53 unmodified lines
413 case I40IW_AE_UDA_XMIT_DGRAM_TOO_LONG:412 case I40IW_AE_UDA_XMIT_DGRAM_TOO_LONG:
414 case I40IW_AE_UDA_XMIT_DGRAM_TOO_SHORT:413 case I40IW_AE_UDA_XMIT_DGRAM_TOO_SHORT:
415 ctx_info->err_rq_idx_valid = false;414 ctx_info->err_rq_idx_valid = false;
416 /* fall through */415 fallthrough;
417 default:416 default:
418 if (!info->sq && ctx_info->err_rq_idx_valid) {417 if (!info->sq && ctx_info->err_rq_idx_valid) {
419 ctx_info->err_rq_idx = info->wqe_idx;418 ctx_info->err_rq_idx = info->wqe_idx;
drivers/infiniband/hw/i40iw/i40iw_main.c+10−12
@@ -1489,36 +1489,35 @@ static void i40iw_deinit_device(struct i40iw_device *iwdev) · 1488 unmodified lines
1489 iwdev->iw_status = 0;1489 iwdev->iw_status = 0;
1490 i40iw_port_ibevent(iwdev);1490 i40iw_port_ibevent(iwdev);
1491 i40iw_destroy_rdma_device(iwdev->iwibdev);1491 i40iw_destroy_rdma_device(iwdev->iwibdev);
1492 /* fallthrough */1492 fallthrough;
1493 case IP_ADDR_REGISTERED:1493 case IP_ADDR_REGISTERED:
1494 if (!iwdev->reset)1494 if (!iwdev->reset)
1495 i40iw_del_macip_entry(iwdev, (u8)iwdev->mac_ip_table_idx);1495 i40iw_del_macip_entry(iwdev, (u8)iwdev->mac_ip_table_idx);
1496 /* fallthrough */1496 fallthrough;
1497 /* fallthrough */
1498 case PBLE_CHUNK_MEM:1497 case PBLE_CHUNK_MEM:
1499 i40iw_destroy_pble_pool(dev, iwdev->pble_rsrc);1498 i40iw_destroy_pble_pool(dev, iwdev->pble_rsrc);
1500 /* fallthrough */1499 fallthrough;
1501 case CEQ_CREATED:1500 case CEQ_CREATED:
1502 i40iw_dele_ceqs(iwdev);1501 i40iw_dele_ceqs(iwdev);
1503 /* fallthrough */1502 fallthrough;
1504 case AEQ_CREATED:1503 case AEQ_CREATED:
1505 i40iw_destroy_aeq(iwdev);1504 i40iw_destroy_aeq(iwdev);
1506 /* fallthrough */1505 fallthrough;
1507 case IEQ_CREATED:1506 case IEQ_CREATED:
1508 i40iw_puda_dele_resources(&iwdev->vsi, I40IW_PUDA_RSRC_TYPE_IEQ, iwdev->reset);1507 i40iw_puda_dele_resources(&iwdev->vsi, I40IW_PUDA_RSRC_TYPE_IEQ, iwdev->reset);
1509 /* fallthrough */1508 fallthrough;
1510 case ILQ_CREATED:1509 case ILQ_CREATED:
1511 i40iw_puda_dele_resources(&iwdev->vsi, I40IW_PUDA_RSRC_TYPE_ILQ, iwdev->reset);1510 i40iw_puda_dele_resources(&iwdev->vsi, I40IW_PUDA_RSRC_TYPE_ILQ, iwdev->reset);
1512 /* fallthrough */1511 fallthrough;
1513 case CCQ_CREATED:1512 case CCQ_CREATED:
1514 i40iw_destroy_ccq(iwdev);1513 i40iw_destroy_ccq(iwdev);
1515 /* fallthrough */1514 fallthrough;
1516 case HMC_OBJS_CREATED:1515 case HMC_OBJS_CREATED:
1517 i40iw_del_hmc_objects(dev, dev->hmc_info, true, iwdev->reset);1516 i40iw_del_hmc_objects(dev, dev->hmc_info, true, iwdev->reset);
1518 /* fallthrough */1517 fallthrough;
1519 case CQP_CREATED:1518 case CQP_CREATED:
1520 i40iw_destroy_cqp(iwdev, true);1519 i40iw_destroy_cqp(iwdev, true);
1521 /* fallthrough */1520 fallthrough;
1522 case INITIAL_STATE:1521 case INITIAL_STATE:
1523 i40iw_cleanup_cm_core(&iwdev->cm_core);1522 i40iw_cleanup_cm_core(&iwdev->cm_core);
1524 if (iwdev->vsi.pestat) {1523 if (iwdev->vsi.pestat) {
@@ -1528,7 +1527,6 @@ static void i40iw_deinit_device(struct i40iw_device *iwdev) · 3 unmodified lines
1528 i40iw_del_init_mem(iwdev);1527 i40iw_del_init_mem(iwdev);
1529 break;1528 break;
1530 case INVALID_STATE:1529 case INVALID_STATE:
1531 /* fallthrough */
1532 default:1530 default:
1533 i40iw_pr_err("bad init_state = %d\n", iwdev->init_state);1531 i40iw_pr_err("bad init_state = %d\n", iwdev->init_state);
1534 break;1532 break;
drivers/infiniband/hw/i40iw/i40iw_puda.c+2−2
@@ -814,13 +814,13 @@ void i40iw_puda_dele_resources(struct i40iw_sc_vsi *vsi, · 813 unmodified lines
814 switch (rsrc->completion) {814 switch (rsrc->completion) {
815 case PUDA_HASH_CRC_COMPLETE:815 case PUDA_HASH_CRC_COMPLETE:
816 i40iw_free_hash_desc(rsrc->hash_desc);816 i40iw_free_hash_desc(rsrc->hash_desc);
817 /* fall through */817 fallthrough;
818 case PUDA_QP_CREATED:818 case PUDA_QP_CREATED:
819 if (!reset)819 if (!reset)
820 i40iw_puda_free_qp(rsrc);820 i40iw_puda_free_qp(rsrc);
821 821
822 i40iw_free_dma_mem(dev->hw, &rsrc->qpmem);822 i40iw_free_dma_mem(dev->hw, &rsrc->qpmem);
823 /* fallthrough */823 fallthrough;
824 case PUDA_CQ_CREATED:824 case PUDA_CQ_CREATED:
825 if (!reset)825 if (!reset)
826 i40iw_puda_free_cq(rsrc);826 i40iw_puda_free_cq(rsrc);
drivers/infiniband/hw/i40iw/i40iw_utils.c+3−5
@@ -190,9 +190,8 @@ int i40iw_inetaddr_event(struct notifier_block *notifier, · 189 unmodified lines
190 switch (event) {190 switch (event) {
191 case NETDEV_DOWN:191 case NETDEV_DOWN:
192 action = I40IW_ARP_DELETE;192 action = I40IW_ARP_DELETE;
193 /* Fall through */193 fallthrough;
194 case NETDEV_UP:194 case NETDEV_UP:
195 /* Fall through */
196 case NETDEV_CHANGEADDR:195 case NETDEV_CHANGEADDR:
197 196
198 /* Just skip if no need to handle ARP cache */197 /* Just skip if no need to handle ARP cache */
@@ -247,9 +246,8 @@ int i40iw_inet6addr_event(struct notifier_block *notifier, · 48 unmodified lines
247 switch (event) {246 switch (event) {
248 case NETDEV_DOWN:247 case NETDEV_DOWN:
249 action = I40IW_ARP_DELETE;248 action = I40IW_ARP_DELETE;
250 /* Fall through */249 fallthrough;
251 case NETDEV_UP:250 case NETDEV_UP:
252 /* Fall through */
253 case NETDEV_CHANGEADDR:251 case NETDEV_CHANGEADDR:
254 i40iw_manage_arp_cache(iwdev,252 i40iw_manage_arp_cache(iwdev,
255 netdev->dev_addr,253 netdev->dev_addr,
@@ -344,7 +342,7 @@ int i40iw_netdevice_event(struct notifier_block *notifier, · 88 unmodified lines
344 switch (event) {342 switch (event) {
345 case NETDEV_DOWN:343 case NETDEV_DOWN:
346 iwdev->iw_status = 0;344 iwdev->iw_status = 0;
347 /* Fall through */345 fallthrough;
348 case NETDEV_UP:346 case NETDEV_UP:
349 i40iw_port_ibevent(iwdev);347 i40iw_port_ibevent(iwdev);
350 break;348 break;
drivers/infiniband/hw/i40iw/i40iw_verbs.c+2−3
@@ -810,7 +810,7 @@ void i40iw_hw_modify_qp(struct i40iw_device *iwdev, struct i40iw_qp *iwqp, · 809 unmodified lines
810 case I40IW_QP_STATE_RTS:810 case I40IW_QP_STATE_RTS:
811 if (iwqp->iwarp_state == I40IW_QP_STATE_IDLE)811 if (iwqp->iwarp_state == I40IW_QP_STATE_IDLE)
812 i40iw_send_reset(iwqp->cm_node);812 i40iw_send_reset(iwqp->cm_node);
813 /* fall through */813 fallthrough;
814 case I40IW_QP_STATE_IDLE:814 case I40IW_QP_STATE_IDLE:
815 case I40IW_QP_STATE_TERMINATE:815 case I40IW_QP_STATE_TERMINATE:
816 case I40IW_QP_STATE_CLOSING:816 case I40IW_QP_STATE_CLOSING:
@@ -2144,7 +2144,6 @@ static int i40iw_post_send(struct ib_qp *ibqp, · 1327 unmodified lines
2144 2144
2145 switch (ib_wr->opcode) {2145 switch (ib_wr->opcode) {
2146 case IB_WR_SEND:2146 case IB_WR_SEND:
2147 /* fall-through */
2148 case IB_WR_SEND_WITH_INV:2147 case IB_WR_SEND_WITH_INV:
2149 if (ib_wr->opcode == IB_WR_SEND) {2148 if (ib_wr->opcode == IB_WR_SEND) {
2150 if (ib_wr->send_flags & IB_SEND_SOLICITED)2149 if (ib_wr->send_flags & IB_SEND_SOLICITED)
@@ -2201,7 +2200,7 @@ static int i40iw_post_send(struct ib_qp *ibqp, · 50 unmodified lines
2201 break;2200 break;
2202 case IB_WR_RDMA_READ_WITH_INV:2201 case IB_WR_RDMA_READ_WITH_INV:
2203 inv_stag = true;2202 inv_stag = true;
2204 /* fall-through*/2203 fallthrough;
2205 case IB_WR_RDMA_READ:2204 case IB_WR_RDMA_READ:
2206 if (ib_wr->num_sge > I40IW_MAX_SGE_RD) {2205 if (ib_wr->num_sge > I40IW_MAX_SGE_RD) {
2207 err = -EINVAL;2206 err = -EINVAL;
drivers/infiniband/hw/mlx4/cq.c+2−2
@@ -765,13 +765,13 @@ repoll: · 764 unmodified lines
765 switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) {765 switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) {
766 case MLX4_OPCODE_RDMA_WRITE_IMM:766 case MLX4_OPCODE_RDMA_WRITE_IMM:
767 wc->wc_flags |= IB_WC_WITH_IMM;767 wc->wc_flags |= IB_WC_WITH_IMM;
768 /* fall through */768 fallthrough;
769 case MLX4_OPCODE_RDMA_WRITE:769 case MLX4_OPCODE_RDMA_WRITE:
770 wc->opcode = IB_WC_RDMA_WRITE;770 wc->opcode = IB_WC_RDMA_WRITE;
771 break;771 break;
772 case MLX4_OPCODE_SEND_IMM:772 case MLX4_OPCODE_SEND_IMM:
773 wc->wc_flags |= IB_WC_WITH_IMM;773 wc->wc_flags |= IB_WC_WITH_IMM;
774 /* fall through */774 fallthrough;
775 case MLX4_OPCODE_SEND:775 case MLX4_OPCODE_SEND:
776 case MLX4_OPCODE_SEND_INVAL:776 case MLX4_OPCODE_SEND_INVAL:
777 wc->opcode = IB_WC_SEND;777 wc->opcode = IB_WC_SEND;
drivers/infiniband/hw/mlx4/mcg.c+1−1
@@ -944,7 +944,7 @@ int mlx4_ib_mcg_multiplex_handler(struct ib_device *ibdev, int port, · 943 unmodified lines
944 switch (sa_mad->mad_hdr.method) {944 switch (sa_mad->mad_hdr.method) {
945 case IB_MGMT_METHOD_SET:945 case IB_MGMT_METHOD_SET:
946 may_create = 1;946 may_create = 1;
947 /* fall through */947 fallthrough;
948 case IB_SA_METHOD_DELETE:948 case IB_SA_METHOD_DELETE:
949 req = kzalloc(sizeof *req, GFP_KERNEL);949 req = kzalloc(sizeof *req, GFP_KERNEL);
950 if (!req)950 if (!req)
drivers/infiniband/hw/mlx4/qp.c+3−3
@@ -1578,12 +1578,12 @@ static struct ib_qp *_mlx4_ib_create_qp(struct ib_pd *pd, · 1577 unmodified lines
1578 pd = to_mxrcd(init_attr->xrcd)->pd;1578 pd = to_mxrcd(init_attr->xrcd)->pd;
1579 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;1579 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1580 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;1580 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
1581 /* fall through */1581 fallthrough;
1582 case IB_QPT_XRC_INI:1582 case IB_QPT_XRC_INI:
1583 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))1583 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1584 return ERR_PTR(-ENOSYS);1584 return ERR_PTR(-ENOSYS);
1585 init_attr->recv_cq = init_attr->send_cq;1585 init_attr->recv_cq = init_attr->send_cq;
1586 /* fall through */1586 fallthrough;
1587 case IB_QPT_RC:1587 case IB_QPT_RC:
1588 case IB_QPT_UC:1588 case IB_QPT_UC:
1589 case IB_QPT_RAW_PACKET:1589 case IB_QPT_RAW_PACKET:
@@ -1592,7 +1592,7 @@ static struct ib_qp *_mlx4_ib_create_qp(struct ib_pd *pd, · 2 unmodified lines
1592 return ERR_PTR(-ENOMEM);1592 return ERR_PTR(-ENOMEM);
1593 qp->pri.vid = 0xFFFF;1593 qp->pri.vid = 0xFFFF;
1594 qp->alt.vid = 0xFFFF;1594 qp->alt.vid = 0xFFFF;
1595 /* fall through */1595 fallthrough;
1596 case IB_QPT_UD:1596 case IB_QPT_UD:
1597 {1597 {
1598 err = create_qp_common(pd, init_attr, udata, 0, &qp);1598 err = create_qp_common(pd, init_attr, udata, 0, &qp);
drivers/infiniband/hw/mlx5/cq.c+2−2
@@ -121,13 +121,13 @@ static void handle_good_req(struct ib_wc *wc, struct mlx5_cqe64 *cqe, · 120 unmodified lines
121 switch (be32_to_cpu(cqe->sop_drop_qpn) >> 24) {121 switch (be32_to_cpu(cqe->sop_drop_qpn) >> 24) {
122 case MLX5_OPCODE_RDMA_WRITE_IMM:122 case MLX5_OPCODE_RDMA_WRITE_IMM:
123 wc->wc_flags |= IB_WC_WITH_IMM;123 wc->wc_flags |= IB_WC_WITH_IMM;
124 /* fall through */124 fallthrough;
125 case MLX5_OPCODE_RDMA_WRITE:125 case MLX5_OPCODE_RDMA_WRITE:
126 wc->opcode = IB_WC_RDMA_WRITE;126 wc->opcode = IB_WC_RDMA_WRITE;
127 break;127 break;
128 case MLX5_OPCODE_SEND_IMM:128 case MLX5_OPCODE_SEND_IMM:
129 wc->wc_flags |= IB_WC_WITH_IMM;129 wc->wc_flags |= IB_WC_WITH_IMM;
130 /* fall through */130 fallthrough;
131 case MLX5_OPCODE_SEND:131 case MLX5_OPCODE_SEND:
132 case MLX5_OPCODE_SEND_INVAL:132 case MLX5_OPCODE_SEND_INVAL:
133 wc->opcode = IB_WC_SEND;133 wc->opcode = IB_WC_SEND;
drivers/infiniband/hw/mlx5/mad.c+1−2
@@ -250,9 +250,8 @@ int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num, · 249 unmodified lines
250 if (MLX5_CAP_GEN(dev->mdev, vport_counters) &&250 if (MLX5_CAP_GEN(dev->mdev, vport_counters) &&
251 method == IB_MGMT_METHOD_GET)251 method == IB_MGMT_METHOD_GET)
252 return process_pma_cmd(dev, port_num, in, out);252 return process_pma_cmd(dev, port_num, in, out);
253 /* fallthrough */253 fallthrough;
254 case MLX5_IB_VENDOR_CLASS1:254 case MLX5_IB_VENDOR_CLASS1:
255 /* fallthrough */
256 case MLX5_IB_VENDOR_CLASS2:255 case MLX5_IB_VENDOR_CLASS2:
257 case IB_MGMT_CLASS_CONG_MGMT: {256 case IB_MGMT_CLASS_CONG_MGMT: {
258 if (method != IB_MGMT_METHOD_GET &&257 if (method != IB_MGMT_METHOD_GET &&
drivers/infiniband/hw/mlx5/main.c+1−1
@@ -2872,7 +2872,7 @@ static void mlx5_ib_handle_event(struct work_struct *_work) · 2871 unmodified lines
2872 break;2872 break;
2873 case MLX5_EVENT_TYPE_GENERAL_EVENT:2873 case MLX5_EVENT_TYPE_GENERAL_EVENT:
2874 handle_general_event(ibdev, work->param, &ibev);2874 handle_general_event(ibdev, work->param, &ibev);
2875 /* fall through */2875 fallthrough;
2876 default:2876 default:
2877 goto out;2877 goto out;
2878 }2878 }
drivers/infiniband/hw/mlx5/qp.c+2−2
@@ -416,7 +416,7 @@ static int sq_overhead(struct ib_qp_init_attr *attr) · 415 unmodified lines
416 switch (attr->qp_type) {416 switch (attr->qp_type) {
417 case IB_QPT_XRC_INI:417 case IB_QPT_XRC_INI:
418 size += sizeof(struct mlx5_wqe_xrc_seg);418 size += sizeof(struct mlx5_wqe_xrc_seg);
419 /* fall through */419 fallthrough;
420 case IB_QPT_RC:420 case IB_QPT_RC:
421 size += sizeof(struct mlx5_wqe_ctrl_seg) +421 size += sizeof(struct mlx5_wqe_ctrl_seg) +
422 max(sizeof(struct mlx5_wqe_atomic_seg) +422 max(sizeof(struct mlx5_wqe_atomic_seg) +
@@ -441,7 +441,7 @@ static int sq_overhead(struct ib_qp_init_attr *attr) · 18 unmodified lines
441 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)441 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
442 size += sizeof(struct mlx5_wqe_eth_pad) +442 size += sizeof(struct mlx5_wqe_eth_pad) +
443 sizeof(struct mlx5_wqe_eth_seg);443 sizeof(struct mlx5_wqe_eth_seg);
444 /* fall through */444 fallthrough;
445 case IB_QPT_SMI:445 case IB_QPT_SMI:
446 case MLX5_IB_QPT_HW_GSI:446 case MLX5_IB_QPT_HW_GSI:
447 size += sizeof(struct mlx5_wqe_ctrl_seg) +447 size += sizeof(struct mlx5_wqe_ctrl_seg) +
drivers/infiniband/hw/mthca/mthca_av.c+1−1
@@ -115,7 +115,7 @@ static u8 ib_rate_to_memfree(u8 req_rate, u8 cur_rate) · 114 unmodified lines
115 switch ((cur_rate - 1) / req_rate) {115 switch ((cur_rate - 1) / req_rate) {
116 case 0: return MTHCA_RATE_MEMFREE_FULL;116 case 0: return MTHCA_RATE_MEMFREE_FULL;
117 case 1: return MTHCA_RATE_MEMFREE_HALF;117 case 1: return MTHCA_RATE_MEMFREE_HALF;
118 case 2: /* fall through */118 case 2:
119 case 3: return MTHCA_RATE_MEMFREE_QUARTER;119 case 3: return MTHCA_RATE_MEMFREE_QUARTER;
120 default: return MTHCA_RATE_MEMFREE_EIGHTH;120 default: return MTHCA_RATE_MEMFREE_EIGHTH;
121 }121 }
drivers/infiniband/hw/ocrdma/ocrdma_verbs.c+2−2
@@ -2134,7 +2134,7 @@ int ocrdma_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, · 2133 unmodified lines
2134 case IB_WR_SEND_WITH_IMM:2134 case IB_WR_SEND_WITH_IMM:
2135 hdr->cw |= (OCRDMA_FLAG_IMM << OCRDMA_WQE_FLAGS_SHIFT);2135 hdr->cw |= (OCRDMA_FLAG_IMM << OCRDMA_WQE_FLAGS_SHIFT);
2136 hdr->immdt = ntohl(wr->ex.imm_data);2136 hdr->immdt = ntohl(wr->ex.imm_data);
2137 /* fall through */2137 fallthrough;
2138 case IB_WR_SEND:2138 case IB_WR_SEND:
2139 hdr->cw |= (OCRDMA_SEND << OCRDMA_WQE_OPCODE_SHIFT);2139 hdr->cw |= (OCRDMA_SEND << OCRDMA_WQE_OPCODE_SHIFT);
2140 ocrdma_build_send(qp, hdr, wr);2140 ocrdma_build_send(qp, hdr, wr);
@@ -2148,7 +2148,7 @@ int ocrdma_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, · 7 unmodified lines
2148 case IB_WR_RDMA_WRITE_WITH_IMM:2148 case IB_WR_RDMA_WRITE_WITH_IMM:
2149 hdr->cw |= (OCRDMA_FLAG_IMM << OCRDMA_WQE_FLAGS_SHIFT);2149 hdr->cw |= (OCRDMA_FLAG_IMM << OCRDMA_WQE_FLAGS_SHIFT);
2150 hdr->immdt = ntohl(wr->ex.imm_data);2150 hdr->immdt = ntohl(wr->ex.imm_data);
2151 /* fall through */2151 fallthrough;
2152 case IB_WR_RDMA_WRITE:2152 case IB_WR_RDMA_WRITE:
2153 hdr->cw |= (OCRDMA_WRITE << OCRDMA_WQE_OPCODE_SHIFT);2153 hdr->cw |= (OCRDMA_WRITE << OCRDMA_WQE_OPCODE_SHIFT);
2154 status = ocrdma_build_write(qp, hdr, wr);2154 status = ocrdma_build_write(qp, hdr, wr);
drivers/infiniband/hw/qedr/verbs.c+1−1
@@ -3528,7 +3528,7 @@ static int __qedr_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, · 3527 unmodified lines
3528 break;3528 break;
3529 case IB_WR_RDMA_READ_WITH_INV:3529 case IB_WR_RDMA_READ_WITH_INV:
3530 SET_FIELD2(wqe->flags, RDMA_SQ_RDMA_WQE_1ST_READ_INV_FLG, 1);3530 SET_FIELD2(wqe->flags, RDMA_SQ_RDMA_WQE_1ST_READ_INV_FLG, 1);
3531 /* fallthrough -- same is identical to RDMA READ */3531 fallthrough; /* same is identical to RDMA READ */
3532 3532
3533 case IB_WR_RDMA_READ:3533 case IB_WR_RDMA_READ:
3534 wqe->req_type = RDMA_SQ_REQ_TYPE_RDMA_RD;3534 wqe->req_type = RDMA_SQ_REQ_TYPE_RDMA_RD;
drivers/infiniband/hw/qib/qib_iba6120.c+2−2
@@ -2973,11 +2973,11 @@ static u32 qib_6120_iblink_state(u64 ibcs) · 2972 unmodified lines
2973 state = IB_PORT_ARMED;2973 state = IB_PORT_ARMED;
2974 break;2974 break;
2975 case IB_6120_L_STATE_ACTIVE:2975 case IB_6120_L_STATE_ACTIVE:
2976 /* fall through */
2977 case IB_6120_L_STATE_ACT_DEFER:2976 case IB_6120_L_STATE_ACT_DEFER:
2978 state = IB_PORT_ACTIVE;2977 state = IB_PORT_ACTIVE;
2979 break;2978 break;
2980 default: /* fall through */2979 default:
2980 fallthrough;
2981 case IB_6120_L_STATE_DOWN:2981 case IB_6120_L_STATE_DOWN:
2982 state = IB_PORT_DOWN;2982 state = IB_PORT_DOWN;
2983 break;2983 break;
drivers/infiniband/hw/qib/qib_iba7220.c+2−2
@@ -3586,11 +3586,11 @@ static u32 qib_7220_iblink_state(u64 ibcs) · 3585 unmodified lines
3586 state = IB_PORT_ARMED;3586 state = IB_PORT_ARMED;
3587 break;3587 break;
3588 case IB_7220_L_STATE_ACTIVE:3588 case IB_7220_L_STATE_ACTIVE:
3589 /* fall through */
3590 case IB_7220_L_STATE_ACT_DEFER:3589 case IB_7220_L_STATE_ACT_DEFER:
3591 state = IB_PORT_ACTIVE;3590 state = IB_PORT_ACTIVE;
3592 break;3591 break;
3593 default: /* fall through */3592 default:
3593 fallthrough;
3594 case IB_7220_L_STATE_DOWN:3594 case IB_7220_L_STATE_DOWN:
3595 state = IB_PORT_DOWN;3595 state = IB_PORT_DOWN;
3596 break;3596 break;
drivers/infiniband/hw/qib/qib_iba7322.c+3−3
@@ -5508,11 +5508,11 @@ static u32 qib_7322_iblink_state(u64 ibcs) · 5507 unmodified lines
5508 state = IB_PORT_ARMED;5508 state = IB_PORT_ARMED;
5509 break;5509 break;
5510 case IB_7322_L_STATE_ACTIVE:5510 case IB_7322_L_STATE_ACTIVE:
5511 /* fall through */
5512 case IB_7322_L_STATE_ACT_DEFER:5511 case IB_7322_L_STATE_ACT_DEFER:
5513 state = IB_PORT_ACTIVE;5512 state = IB_PORT_ACTIVE;
5514 break;5513 break;
5515 default: /* fall through */5514 default:
5515 fallthrough;
5516 case IB_7322_L_STATE_DOWN:5516 case IB_7322_L_STATE_DOWN:
5517 state = IB_PORT_DOWN;5517 state = IB_PORT_DOWN;
5518 break;5518 break;
@@ -6533,7 +6533,7 @@ static int qib_init_7322_variables(struct qib_devdata *dd) · 1014 unmodified lines
6533 "Invalid num_vls %u, using 4 VLs\n",6533 "Invalid num_vls %u, using 4 VLs\n",
6534 qib_num_cfg_vls);6534 qib_num_cfg_vls);
6535 qib_num_cfg_vls = 4;6535 qib_num_cfg_vls = 4;
6536 /* fall through */6536 fallthrough;
6537 case 4:6537 case 4:
6538 ppd->vls_supported = IB_VL_VL0_3;6538 ppd->vls_supported = IB_VL_VL0_3;
6539 break;6539 break;
drivers/infiniband/hw/qib/qib_mad.c+6−6
@@ -433,7 +433,7 @@ static int check_mkey(struct qib_ibport *ibp, struct ib_smp *smp, int mad_flags) · 432 unmodified lines
433 /* Bad mkey not a violation below level 2 */433 /* Bad mkey not a violation below level 2 */
434 if (ibp->rvp.mkeyprot < 2)434 if (ibp->rvp.mkeyprot < 2)
435 break;435 break;
436 /* fall through */436 fallthrough;
437 case IB_MGMT_METHOD_SET:437 case IB_MGMT_METHOD_SET:
438 case IB_MGMT_METHOD_TRAP_REPRESS:438 case IB_MGMT_METHOD_TRAP_REPRESS:
439 if (ibp->rvp.mkey_violations != 0xFFFF)439 if (ibp->rvp.mkey_violations != 0xFFFF)
@@ -828,7 +828,7 @@ static int subn_set_portinfo(struct ib_smp *smp, struct ib_device *ibdev, · 388 unmodified lines
828 case IB_PORT_NOP:828 case IB_PORT_NOP:
829 if (lstate == 0)829 if (lstate == 0)
830 break;830 break;
831 /* FALLTHROUGH */831 fallthrough;
832 case IB_PORT_DOWN:832 case IB_PORT_DOWN:
833 if (lstate == 0)833 if (lstate == 0)
834 lstate = QIB_IB_LINKDOWN_ONLY;834 lstate = QIB_IB_LINKDOWN_ONLY;
@@ -1928,7 +1928,7 @@ static int process_subn(struct ib_device *ibdev, int mad_flags, · 1093 unmodified lines
1928 ret = IB_MAD_RESULT_SUCCESS;1928 ret = IB_MAD_RESULT_SUCCESS;
1929 goto bail;1929 goto bail;
1930 }1930 }
1931 /* FALLTHROUGH */1931 fallthrough;
1932 default:1932 default:
1933 smp->status |= IB_SMP_UNSUP_METH_ATTR;1933 smp->status |= IB_SMP_UNSUP_METH_ATTR;
1934 ret = reply(smp);1934 ret = reply(smp);
@@ -1962,7 +1962,7 @@ static int process_subn(struct ib_device *ibdev, int mad_flags, · 27 unmodified lines
1962 ret = IB_MAD_RESULT_SUCCESS;1962 ret = IB_MAD_RESULT_SUCCESS;
1963 goto bail;1963 goto bail;
1964 }1964 }
1965 /* FALLTHROUGH */1965 fallthrough;
1966 default:1966 default:
1967 smp->status |= IB_SMP_UNSUP_METH_ATTR;1967 smp->status |= IB_SMP_UNSUP_METH_ATTR;
1968 ret = reply(smp);1968 ret = reply(smp);
@@ -2322,7 +2322,7 @@ static int process_cc(struct ib_device *ibdev, int mad_flags, · 353 unmodified lines
2322 ret = cc_get_congestion_control_table(ccp, ibdev, port);2322 ret = cc_get_congestion_control_table(ccp, ibdev, port);
2323 goto bail;2323 goto bail;
2324 2324
2325 /* FALLTHROUGH */2325 fallthrough;
2326 default:2326 default:
2327 ccp->status |= IB_SMP_UNSUP_METH_ATTR;2327 ccp->status |= IB_SMP_UNSUP_METH_ATTR;
2328 ret = reply((struct ib_smp *) ccp);2328 ret = reply((struct ib_smp *) ccp);
@@ -2339,7 +2339,7 @@ static int process_cc(struct ib_device *ibdev, int mad_flags, · 10 unmodified lines
2339 ret = cc_set_congestion_control_table(ccp, ibdev, port);2339 ret = cc_set_congestion_control_table(ccp, ibdev, port);
2340 goto bail;2340 goto bail;
2341 2341
2342 /* FALLTHROUGH */2342 fallthrough;
2343 default:2343 default:
2344 ccp->status |= IB_SMP_UNSUP_METH_ATTR;2344 ccp->status |= IB_SMP_UNSUP_METH_ATTR;
2345 ret = reply((struct ib_smp *) ccp);2345 ret = reply((struct ib_smp *) ccp);
drivers/infiniband/hw/qib/qib_rc.c+9−9
@@ -83,7 +83,7 @@ static int qib_make_rc_ack(struct qib_ibdev *dev, struct rvt_qp *qp, · 82 unmodified lines
83 rvt_put_mr(e->rdma_sge.mr);83 rvt_put_mr(e->rdma_sge.mr);
84 e->rdma_sge.mr = NULL;84 e->rdma_sge.mr = NULL;
85 }85 }
86 /* FALLTHROUGH */86 fallthrough;
87 case OP(ATOMIC_ACKNOWLEDGE):87 case OP(ATOMIC_ACKNOWLEDGE):
88 /*88 /*
89 * We can increment the tail pointer now that the last89 * We can increment the tail pointer now that the last
@@ -92,7 +92,7 @@ static int qib_make_rc_ack(struct qib_ibdev *dev, struct rvt_qp *qp, · 2 unmodified lines
92 */92 */
93 if (++qp->s_tail_ack_queue > QIB_MAX_RDMA_ATOMIC)93 if (++qp->s_tail_ack_queue > QIB_MAX_RDMA_ATOMIC)
94 qp->s_tail_ack_queue = 0;94 qp->s_tail_ack_queue = 0;
95 /* FALLTHROUGH */95 fallthrough;
96 case OP(SEND_ONLY):96 case OP(SEND_ONLY):
97 case OP(ACKNOWLEDGE):97 case OP(ACKNOWLEDGE):
98 /* Check for no next entry in the queue. */98 /* Check for no next entry in the queue. */
@@ -149,7 +149,7 @@ static int qib_make_rc_ack(struct qib_ibdev *dev, struct rvt_qp *qp, · 50 unmodified lines
149 149
150 case OP(RDMA_READ_RESPONSE_FIRST):150 case OP(RDMA_READ_RESPONSE_FIRST):
151 qp->s_ack_state = OP(RDMA_READ_RESPONSE_MIDDLE);151 qp->s_ack_state = OP(RDMA_READ_RESPONSE_MIDDLE);
152 /* FALLTHROUGH */152 fallthrough;
153 case OP(RDMA_READ_RESPONSE_MIDDLE):153 case OP(RDMA_READ_RESPONSE_MIDDLE):
154 qp->s_cur_sge = &qp->s_ack_rdma_sge;154 qp->s_cur_sge = &qp->s_ack_rdma_sge;
155 qp->s_rdma_mr = qp->s_ack_rdma_sge.sge.mr;155 qp->s_rdma_mr = qp->s_ack_rdma_sge.sge.mr;
@@ -471,10 +471,10 @@ no_flow_control: · 315 unmodified lines
471 * See qib_restart_rc().471 * See qib_restart_rc().
472 */472 */
473 qp->s_len = restart_sge(&qp->s_sge, wqe, qp->s_psn, pmtu);473 qp->s_len = restart_sge(&qp->s_sge, wqe, qp->s_psn, pmtu);
474 /* FALLTHROUGH */474 fallthrough;
475 case OP(SEND_FIRST):475 case OP(SEND_FIRST):
476 qp->s_state = OP(SEND_MIDDLE);476 qp->s_state = OP(SEND_MIDDLE);
477 /* FALLTHROUGH */477 fallthrough;
478 case OP(SEND_MIDDLE):478 case OP(SEND_MIDDLE):
479 bth2 = qp->s_psn++ & QIB_PSN_MASK;479 bth2 = qp->s_psn++ & QIB_PSN_MASK;
480 ss = &qp->s_sge;480 ss = &qp->s_sge;
@@ -510,10 +510,10 @@ no_flow_control: · 29 unmodified lines
510 * See qib_restart_rc().510 * See qib_restart_rc().
511 */511 */
512 qp->s_len = restart_sge(&qp->s_sge, wqe, qp->s_psn, pmtu);512 qp->s_len = restart_sge(&qp->s_sge, wqe, qp->s_psn, pmtu);
513 /* FALLTHROUGH */513 fallthrough;
514 case OP(RDMA_WRITE_FIRST):514 case OP(RDMA_WRITE_FIRST):
515 qp->s_state = OP(RDMA_WRITE_MIDDLE);515 qp->s_state = OP(RDMA_WRITE_MIDDLE);
516 /* FALLTHROUGH */516 fallthrough;
517 case OP(RDMA_WRITE_MIDDLE):517 case OP(RDMA_WRITE_MIDDLE):
518 bth2 = qp->s_psn++ & QIB_PSN_MASK;518 bth2 = qp->s_psn++ & QIB_PSN_MASK;
519 ss = &qp->s_sge;519 ss = &qp->s_sge;
@@ -1807,7 +1807,7 @@ void qib_rc_rcv(struct qib_ctxtdata *rcd, struct ib_header *hdr, · 1287 unmodified lines
1807 if (!ret)1807 if (!ret)
1808 goto rnr_nak;1808 goto rnr_nak;
1809 qp->r_rcv_len = 0;1809 qp->r_rcv_len = 0;
1810 /* FALLTHROUGH */1810 fallthrough;
1811 case OP(SEND_MIDDLE):1811 case OP(SEND_MIDDLE):
1812 case OP(RDMA_WRITE_MIDDLE):1812 case OP(RDMA_WRITE_MIDDLE):
1813send_middle:1813send_middle:
@@ -1839,7 +1839,7 @@ send_middle: · 25 unmodified lines
1839 qp->r_rcv_len = 0;1839 qp->r_rcv_len = 0;
1840 if (opcode == OP(SEND_ONLY))1840 if (opcode == OP(SEND_ONLY))
1841 goto no_immediate_data;1841 goto no_immediate_data;
1842 /* fall through -- for SEND_ONLY_WITH_IMMEDIATE */1842 fallthrough; /* for SEND_ONLY_WITH_IMMEDIATE */
1843 case OP(SEND_LAST_WITH_IMMEDIATE):1843 case OP(SEND_LAST_WITH_IMMEDIATE):
1844send_last_imm:1844send_last_imm:
1845 wc.ex.imm_data = ohdr->u.imm_data;1845 wc.ex.imm_data = ohdr->u.imm_data;
drivers/infiniband/hw/qib/qib_sdma.c+1−1
@@ -763,7 +763,7 @@ void __qib_sdma_process_event(struct qib_pportdata *ppd, · 762 unmodified lines
763 * bringing the link up with traffic active on763 * bringing the link up with traffic active on
764 * 7220, e.g. */764 * 7220, e.g. */
765 ss->go_s99_running = 1;765 ss->go_s99_running = 1;
766 /* fall through -- and start dma engine */766 fallthrough; /* and start dma engine */
767 case qib_sdma_event_e10_go_hw_start:767 case qib_sdma_event_e10_go_hw_start:
768 /* This reference means the state machine is started */768 /* This reference means the state machine is started */
769 sdma_get(&ppd->sdma_state);769 sdma_get(&ppd->sdma_state);
drivers/infiniband/hw/qib/qib_uc.c+4−4
@@ -161,7 +161,7 @@ int qib_make_uc_req(struct rvt_qp *qp, unsigned long *flags) · 160 unmodified lines
161 161
162 case OP(SEND_FIRST):162 case OP(SEND_FIRST):
163 qp->s_state = OP(SEND_MIDDLE);163 qp->s_state = OP(SEND_MIDDLE);
164 /* FALLTHROUGH */164 fallthrough;
165 case OP(SEND_MIDDLE):165 case OP(SEND_MIDDLE):
166 len = qp->s_len;166 len = qp->s_len;
167 if (len > pmtu) {167 if (len > pmtu) {
@@ -185,7 +185,7 @@ int qib_make_uc_req(struct rvt_qp *qp, unsigned long *flags) · 17 unmodified lines
185 185
186 case OP(RDMA_WRITE_FIRST):186 case OP(RDMA_WRITE_FIRST):
187 qp->s_state = OP(RDMA_WRITE_MIDDLE);187 qp->s_state = OP(RDMA_WRITE_MIDDLE);
188 /* FALLTHROUGH */188 fallthrough;
189 case OP(RDMA_WRITE_MIDDLE):189 case OP(RDMA_WRITE_MIDDLE):
190 len = qp->s_len;190 len = qp->s_len;
191 if (len > pmtu) {191 if (len > pmtu) {
@@ -351,7 +351,7 @@ send_first: · 159 unmodified lines
351 goto no_immediate_data;351 goto no_immediate_data;
352 else if (opcode == OP(SEND_ONLY_WITH_IMMEDIATE))352 else if (opcode == OP(SEND_ONLY_WITH_IMMEDIATE))
353 goto send_last_imm;353 goto send_last_imm;
354 /* FALLTHROUGH */354 fallthrough;
355 case OP(SEND_MIDDLE):355 case OP(SEND_MIDDLE):
356 /* Check for invalid length PMTU or posted rwqe len. */356 /* Check for invalid length PMTU or posted rwqe len. */
357 if (unlikely(tlen != (hdrsize + pmtu + 4)))357 if (unlikely(tlen != (hdrsize + pmtu + 4)))
@@ -440,7 +440,7 @@ rdma_first: · 82 unmodified lines
440 wc.ex.imm_data = ohdr->u.rc.imm_data;440 wc.ex.imm_data = ohdr->u.rc.imm_data;
441 goto rdma_last_imm;441 goto rdma_last_imm;
442 }442 }
443 /* FALLTHROUGH */443 fallthrough;
444 case OP(RDMA_WRITE_MIDDLE):444 case OP(RDMA_WRITE_MIDDLE):
445 /* Check for invalid length PMTU or posted rwqe len. */445 /* Check for invalid length PMTU or posted rwqe len. */
446 if (unlikely(tlen != (hdrsize + pmtu + 4)))446 if (unlikely(tlen != (hdrsize + pmtu + 4)))
drivers/infiniband/hw/qib/qib_verbs.c+1−1
@@ -237,7 +237,7 @@ static void qib_qp_rcv(struct qib_ctxtdata *rcd, struct ib_header *hdr, · 236 unmodified lines
237 case IB_QPT_GSI:237 case IB_QPT_GSI:
238 if (ib_qib_disable_sma)238 if (ib_qib_disable_sma)
239 break;239 break;
240 /* FALLTHROUGH */240 fallthrough;
241 case IB_QPT_UD:241 case IB_QPT_UD:
242 qib_ud_rcv(ibp, hdr, has_grh, data, tlen, qp);242 qib_ud_rcv(ibp, hdr, has_grh, data, tlen, qp);
243 break;243 break;
drivers/infiniband/hw/usnic/usnic_ib_main.c+1−1
@@ -120,7 +120,7 @@ static void usnic_ib_qp_grp_modify_active_to_err(struct usnic_ib_dev *us_ibdev) · 119 unmodified lines
120 IB_QPS_ERR,120 IB_QPS_ERR,
121 NULL);121 NULL);
122 if (status) {122 if (status) {
123 usnic_err("Failed to transistion qp grp %u from %s to %s\n",123 usnic_err("Failed to transition qp grp %u from %s to %s\n",
124 qp_grp->grp_id,124 qp_grp->grp_id,
125 usnic_ib_qp_grp_state_to_string125 usnic_ib_qp_grp_state_to_string
126 (cur_state),126 (cur_state),
drivers/infiniband/hw/vmw_pvrdma/pvrdma_qp.c+1−1
@@ -238,7 +238,7 @@ struct ib_qp *pvrdma_create_qp(struct ib_pd *pd, · 237 unmodified lines
238 ret = -EINVAL;238 ret = -EINVAL;
239 goto err_qp;239 goto err_qp;
240 }240 }
241 /* fall through */241 fallthrough;
242 case IB_QPT_RC:242 case IB_QPT_RC:
243 case IB_QPT_UD:243 case IB_QPT_UD:
244 qp = kzalloc(sizeof(*qp), GFP_KERNEL);244 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
drivers/infiniband/sw/rdmavt/qp.c+1−1
@@ -1111,7 +1111,7 @@ struct ib_qp *rvt_create_qp(struct ib_pd *ibpd, · 1110 unmodified lines
1111 if (init_attr->port_num == 0 ||1111 if (init_attr->port_num == 0 ||
1112 init_attr->port_num > ibpd->device->phys_port_cnt)1112 init_attr->port_num > ibpd->device->phys_port_cnt)
1113 return ERR_PTR(-EINVAL);1113 return ERR_PTR(-EINVAL);
1114 /* fall through */1114 fallthrough;
1115 case IB_QPT_UC:1115 case IB_QPT_UC:
1116 case IB_QPT_RC:1116 case IB_QPT_RC:
1117 case IB_QPT_UD:1117 case IB_QPT_UD:
drivers/infiniband/sw/rxe/rxe_comp.c+1−1
@@ -282,7 +282,7 @@ static inline enum comp_state check_ack(struct rxe_qp *qp, · 281 unmodified lines
282 if ((syn & AETH_TYPE_MASK) != AETH_ACK)282 if ((syn & AETH_TYPE_MASK) != AETH_ACK)
283 return COMPST_ERROR;283 return COMPST_ERROR;
284 284
285 /* fall through */285 fallthrough;
286 /* (IB_OPCODE_RC_RDMA_READ_RESPONSE_MIDDLE doesn't have an AETH)286 /* (IB_OPCODE_RC_RDMA_READ_RESPONSE_MIDDLE doesn't have an AETH)
287 */287 */
288 case IB_OPCODE_RC_RDMA_READ_RESPONSE_MIDDLE:288 case IB_OPCODE_RC_RDMA_READ_RESPONSE_MIDDLE:
drivers/infiniband/sw/rxe/rxe_task.c+1−1
@@ -71,7 +71,7 @@ void rxe_do_task(unsigned long data) · 70 unmodified lines
71 71
72 case TASK_STATE_BUSY:72 case TASK_STATE_BUSY:
73 task->state = TASK_STATE_ARMED;73 task->state = TASK_STATE_ARMED;
74 /* fall through */74 fallthrough;
75 case TASK_STATE_ARMED:75 case TASK_STATE_ARMED:
76 spin_unlock_irqrestore(&task->state_lock, flags);76 spin_unlock_irqrestore(&task->state_lock, flags);
77 return;77 return;
drivers/infiniband/sw/rxe/rxe_verbs.c+1−1
@@ -540,7 +540,7 @@ static void init_send_wr(struct rxe_qp *qp, struct rxe_send_wr *wr, · 539 unmodified lines
540 switch (wr->opcode) {540 switch (wr->opcode) {
541 case IB_WR_RDMA_WRITE_WITH_IMM:541 case IB_WR_RDMA_WRITE_WITH_IMM:
542 wr->ex.imm_data = ibwr->ex.imm_data;542 wr->ex.imm_data = ibwr->ex.imm_data;
543 /* fall through */543 fallthrough;
544 case IB_WR_RDMA_READ:544 case IB_WR_RDMA_READ:
545 case IB_WR_RDMA_WRITE:545 case IB_WR_RDMA_WRITE:
546 wr->wr.rdma.remote_addr = rdma_wr(ibwr)->remote_addr;546 wr->wr.rdma.remote_addr = rdma_wr(ibwr)->remote_addr;
drivers/infiniband/sw/siw/siw_cm.c+0−2
@@ -1224,12 +1224,10 @@ static void siw_cm_llp_data_ready(struct sock *sk) · 1223 unmodified lines
1224 1224
1225 switch (cep->state) {1225 switch (cep->state) {
1226 case SIW_EPSTATE_RDMA_MODE:1226 case SIW_EPSTATE_RDMA_MODE:
1227 /* fall through */
1228 case SIW_EPSTATE_LISTENING:1227 case SIW_EPSTATE_LISTENING:
1229 break;1228 break;
1230 1229
1231 case SIW_EPSTATE_AWAIT_MPAREQ:1230 case SIW_EPSTATE_AWAIT_MPAREQ:
1232 /* fall through */
1233 case SIW_EPSTATE_AWAIT_MPAREP:1231 case SIW_EPSTATE_AWAIT_MPAREP:
1234 siw_cm_queue_work(cep, SIW_CM_WORK_READ_MPAHDR);1232 siw_cm_queue_work(cep, SIW_CM_WORK_READ_MPAHDR);
1235 break;1233 break;
drivers/infiniband/sw/siw/siw_qp_rx.c+2−2
@@ -1215,7 +1215,7 @@ static int siw_rdmap_complete(struct siw_qp *qp, int error) · 1214 unmodified lines
1215 case RDMAP_SEND_SE:1215 case RDMAP_SEND_SE:
1216 case RDMAP_SEND_SE_INVAL:1216 case RDMAP_SEND_SE_INVAL:
1217 wqe->rqe.flags |= SIW_WQE_SOLICITED;1217 wqe->rqe.flags |= SIW_WQE_SOLICITED;
1218 /* Fall through */1218 fallthrough;
1219 1219
1220 case RDMAP_SEND:1220 case RDMAP_SEND:
1221 case RDMAP_SEND_INVAL:1221 case RDMAP_SEND_INVAL:
@@ -1386,7 +1386,7 @@ int siw_tcp_rx_data(read_descriptor_t *rd_desc, struct sk_buff *skb, · 164 unmodified lines
1386 * DDP segment.1386 * DDP segment.
1387 */1387 */
1388 qp->rx_fpdu->first_ddp_seg = 0;1388 qp->rx_fpdu->first_ddp_seg = 0;
1389 /* Fall through */1389 fallthrough;
1390 1390
1391 case SIW_GET_DATA_START:1391 case SIW_GET_DATA_START:
1392 /*1392 /*
drivers/infiniband/sw/siw/siw_qp_tx.c+2−2
@@ -1042,7 +1042,7 @@ next_wqe: · 1041 unmodified lines
1042 case SIW_OP_SEND_REMOTE_INV:1042 case SIW_OP_SEND_REMOTE_INV:
1043 case SIW_OP_WRITE:1043 case SIW_OP_WRITE:
1044 siw_wqe_put_mem(wqe, tx_type);1044 siw_wqe_put_mem(wqe, tx_type);
1045 /* Fall through */1045 fallthrough;
1046 1046
1047 case SIW_OP_INVAL_STAG:1047 case SIW_OP_INVAL_STAG:
1048 case SIW_OP_REG_MR:1048 case SIW_OP_REG_MR:
@@ -1128,7 +1128,7 @@ next_wqe: · 79 unmodified lines
1128 case SIW_OP_READ:1128 case SIW_OP_READ:
1129 case SIW_OP_READ_LOCAL_INV:1129 case SIW_OP_READ_LOCAL_INV:
1130 siw_wqe_put_mem(wqe, tx_type);1130 siw_wqe_put_mem(wqe, tx_type);
1131 /* Fall through */1131 fallthrough;
1132 1132
1133 case SIW_OP_INVAL_STAG:1133 case SIW_OP_INVAL_STAG:
1134 case SIW_OP_REG_MR:1134 case SIW_OP_REG_MR:
drivers/infiniband/ulp/ipoib/ipoib_cm.c+2−2
@@ -512,13 +512,13 @@ static int ipoib_cm_rx_handler(struct ib_cm_id *cm_id, · 511 unmodified lines
512 return ipoib_cm_req_handler(cm_id, event);512 return ipoib_cm_req_handler(cm_id, event);
513 case IB_CM_DREQ_RECEIVED:513 case IB_CM_DREQ_RECEIVED:
514 ib_send_cm_drep(cm_id, NULL, 0);514 ib_send_cm_drep(cm_id, NULL, 0);
515 /* Fall through */515 fallthrough;
516 case IB_CM_REJ_RECEIVED:516 case IB_CM_REJ_RECEIVED:
517 p = cm_id->context;517 p = cm_id->context;
518 priv = ipoib_priv(p->dev);518 priv = ipoib_priv(p->dev);
519 if (ib_modify_qp(p->qp, &ipoib_cm_err_attr, IB_QP_STATE))519 if (ib_modify_qp(p->qp, &ipoib_cm_err_attr, IB_QP_STATE))
520 ipoib_warn(priv, "unable to move qp to error state\n");520 ipoib_warn(priv, "unable to move qp to error state\n");
521 /* Fall through */521 fallthrough;
522 default:522 default:
523 return 0;523 return 0;
524 }524 }
drivers/infiniband/ulp/ipoib/ipoib_main.c+1−1
@@ -502,7 +502,7 @@ static struct net_device *ipoib_get_net_dev_by_params( · 501 unmodified lines
502 default:502 default:
503 dev_warn_ratelimited(&dev->dev,503 dev_warn_ratelimited(&dev->dev,
504 "duplicate IP address detected\n");504 "duplicate IP address detected\n");
505 /* Fall through */505 fallthrough;
506 case 1:506 case 1:
507 return net_dev;507 return net_dev;
508 }508 }
drivers/infiniband/ulp/iser/iser_verbs.c+1−1
@@ -711,7 +711,7 @@ static int iser_cma_handler(struct rdma_cm_id *cma_id, struct rdma_cm_event *eve · 710 unmodified lines
711 case RDMA_CM_EVENT_REJECTED:711 case RDMA_CM_EVENT_REJECTED:
712 iser_info("Connection rejected: %s\n",712 iser_info("Connection rejected: %s\n",
713 rdma_reject_msg(cma_id, event->status));713 rdma_reject_msg(cma_id, event->status));
714 /* FALLTHROUGH */714 fallthrough;
715 case RDMA_CM_EVENT_ADDR_ERROR:715 case RDMA_CM_EVENT_ADDR_ERROR:
716 case RDMA_CM_EVENT_ROUTE_ERROR:716 case RDMA_CM_EVENT_ROUTE_ERROR:
717 case RDMA_CM_EVENT_CONNECT_ERROR:717 case RDMA_CM_EVENT_CONNECT_ERROR:
drivers/infiniband/ulp/isert/ib_isert.c+5−5
@@ -664,8 +664,8 @@ isert_cma_handler(struct rdma_cm_id *cma_id, struct rdma_cm_event *event) · 663 unmodified lines
664 case RDMA_CM_EVENT_ESTABLISHED:664 case RDMA_CM_EVENT_ESTABLISHED:
665 isert_connected_handler(cma_id);665 isert_connected_handler(cma_id);
666 break;666 break;
667 case RDMA_CM_EVENT_ADDR_CHANGE: /* FALLTHRU */667 case RDMA_CM_EVENT_ADDR_CHANGE:
668 case RDMA_CM_EVENT_DISCONNECTED: /* FALLTHRU */668 case RDMA_CM_EVENT_DISCONNECTED:
669 case RDMA_CM_EVENT_TIMEWAIT_EXIT: /* FALLTHRU */669 case RDMA_CM_EVENT_TIMEWAIT_EXIT: /* FALLTHRU */
670 ret = isert_disconnected_handler(cma_id, event->event);670 ret = isert_disconnected_handler(cma_id, event->event);
671 break;671 break;
@@ -684,7 +684,7 @@ isert_cma_handler(struct rdma_cm_id *cma_id, struct rdma_cm_event *event) · 12 unmodified lines
684 case RDMA_CM_EVENT_REJECTED:684 case RDMA_CM_EVENT_REJECTED:
685 isert_info("Connection rejected: %s\n",685 isert_info("Connection rejected: %s\n",
686 rdma_reject_msg(cma_id, event->status));686 rdma_reject_msg(cma_id, event->status));
687 /* fall through */687 fallthrough;
688 case RDMA_CM_EVENT_UNREACHABLE:688 case RDMA_CM_EVENT_UNREACHABLE:
689 case RDMA_CM_EVENT_CONNECT_ERROR:689 case RDMA_CM_EVENT_CONNECT_ERROR:
690 ret = isert_connect_error(cma_id);690 ret = isert_connect_error(cma_id);
@@ -1470,7 +1470,7 @@ isert_put_cmd(struct isert_cmd *isert_cmd, bool comp_err) · 779 unmodified lines
1470 transport_generic_free_cmd(&cmd->se_cmd, 0);1470 transport_generic_free_cmd(&cmd->se_cmd, 0);
1471 break;1471 break;
1472 }1472 }
1473 /* fall through */1473 fallthrough;
1474 default:1474 default:
1475 iscsit_release_cmd(cmd);1475 iscsit_release_cmd(cmd);
1476 break;1476 break;
@@ -1648,7 +1648,7 @@ isert_do_control_comp(struct work_struct *work) · 171 unmodified lines
1648 switch (cmd->i_state) {1648 switch (cmd->i_state) {
1649 case ISTATE_SEND_TASKMGTRSP:1649 case ISTATE_SEND_TASKMGTRSP:
1650 iscsit_tmr_post_handler(cmd, cmd->conn);1650 iscsit_tmr_post_handler(cmd, cmd->conn);
1651 /* fall through */1651 fallthrough;
1652 case ISTATE_SEND_REJECT:1652 case ISTATE_SEND_REJECT:
1653 case ISTATE_SEND_TEXTRSP:1653 case ISTATE_SEND_TEXTRSP:
1654 cmd->i_state = ISTATE_SENT_STATUS;1654 cmd->i_state = ISTATE_SENT_STATUS;
drivers/infiniband/ulp/opa_vnic/opa_vnic_vema.c+0−1
@@ -547,7 +547,6 @@ static void vema_get(struct opa_vnic_vema_port *port, · 546 unmodified lines
547 vema_get_mac_entries(port, recvd_mad, rsp_mad);547 vema_get_mac_entries(port, recvd_mad, rsp_mad);
548 break;548 break;
549 case OPA_EM_ATTR_IFACE_UCAST_MACS:549 case OPA_EM_ATTR_IFACE_UCAST_MACS:
550 /* fall through */
551 case OPA_EM_ATTR_IFACE_MCAST_MACS:550 case OPA_EM_ATTR_IFACE_MCAST_MACS:
552 vema_get_mac_list(port, recvd_mad, rsp_mad, attr_id);551 vema_get_mac_list(port, recvd_mad, rsp_mad, attr_id);
553 break;552 break;
drivers/input/joystick/fsia6b.c+2−2
@@ -102,12 +102,12 @@ static irqreturn_t fsia6b_serio_irq(struct serio *serio, · 101 unmodified lines
102 input_report_key(fsia6b->dev,102 input_report_key(fsia6b->dev,
103 sw_id++,103 sw_id++,
104 sw_state == 0);104 sw_state == 0);
105 /* fall-through */105 fallthrough;
106 case '2':106 case '2':
107 input_report_key(fsia6b->dev,107 input_report_key(fsia6b->dev,
108 sw_id++,108 sw_id++,
109 sw_state == 1);109 sw_state == 1);
110 /* fall-through */110 fallthrough;
111 case '1':111 case '1':
112 input_report_key(fsia6b->dev,112 input_report_key(fsia6b->dev,
113 sw_id++,113 sw_id++,
drivers/input/joystick/gamecon.c+0−1
@@ -885,7 +885,6 @@ static int gc_setup_pad(struct gc *gc, int idx, int pad_type) · 884 unmodified lines
885 885
886 case GC_MULTI:886 case GC_MULTI:
887 input_set_capability(input_dev, EV_KEY, BTN_TRIGGER);887 input_set_capability(input_dev, EV_KEY, BTN_TRIGGER);
888 /* fall through */
889 break;888 break;
890 889
891 case GC_PSX:890 case GC_PSX:
drivers/input/tablet/wacom_serial4.c+1−1
@@ -213,7 +213,7 @@ static void wacom_handle_model_response(struct wacom *wacom) · 212 unmodified lines
213 case 0x3731: /* PL-710 */213 case 0x3731: /* PL-710 */
214 wacom->res_x = 2540;214 wacom->res_x = 2540;
215 wacom->res_y = 2540;215 wacom->res_y = 2540;
216 /* fall through */216 fallthrough;
217 case 0x3535: /* PL-550 */217 case 0x3535: /* PL-550 */
218 case 0x3830: /* PL-800 */218 case 0x3830: /* PL-800 */
219 wacom->extra_z_bits = 2;219 wacom->extra_z_bits = 2;
drivers/input/touchscreen/atmel_mxt_ts.c+1−1
@@ -477,7 +477,7 @@ static int mxt_lookup_bootloader_address(struct mxt_data *data, bool retry) · 476 unmodified lines
477 bootloader = appmode - 0x24;477 bootloader = appmode - 0x24;
478 break;478 break;
479 }479 }
480 /* Fall through - for normal case */480 fallthrough; /* for normal case */
481 case 0x4c:481 case 0x4c:
482 case 0x4d:482 case 0x4d:
483 case 0x5a:483 case 0x5a:
drivers/input/touchscreen/wm831x-ts.c+1−1
@@ -290,7 +290,7 @@ static int wm831x_ts_probe(struct platform_device *pdev) · 289 unmodified lines
290 default:290 default:
291 dev_err(&pdev->dev, "Unsupported ISEL setting: %d\n",291 dev_err(&pdev->dev, "Unsupported ISEL setting: %d\n",
292 pdata->isel);292 pdata->isel);
293 /* Fall through */293 fallthrough;
294 case 200:294 case 200:
295 case 0:295 case 0:
296 wm831x_set_bits(wm831x, WM831X_TOUCH_CONTROL_2,296 wm831x_set_bits(wm831x, WM831X_TOUCH_CONTROL_2,
drivers/iommu/amd/Kconfig+1−1
@@ -10,7 +10,7 @@ config AMD_IOMMU · 9 unmodified lines
10 select IOMMU_API10 select IOMMU_API
11 select IOMMU_IOVA11 select IOMMU_IOVA
12 select IOMMU_DMA12 select IOMMU_DMA
13 depends on X86_64 && PCI && ACPI13 depends on X86_64 && PCI && ACPI && HAVE_CMPXCHG_DOUBLE
14 help14 help
15 With this option you can enable support for AMD IOMMU hardware in15 With this option you can enable support for AMD IOMMU hardware in
16 your system. An IOMMU is a hardware component which provides16 your system. An IOMMU is a hardware component which provides
drivers/iommu/amd/init.c+20−3
@@ -1511,7 +1511,14 @@ static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h) · 1510 unmodified lines
1511 iommu->mmio_phys_end = MMIO_REG_END_OFFSET;1511 iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
1512 else1512 else
1513 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;1513 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
1514 if (((h->efr_attr & (0x1 << IOMMU_FEAT_GASUP_SHIFT)) == 0))1514
1515 /*
1516 * Note: GA (128-bit IRTE) mode requires cmpxchg16b supports.
1517 * GAM also requires GA mode. Therefore, we need to
1518 * check cmpxchg16b support before enabling it.
1519 */
1520 if (!boot_cpu_has(X86_FEATURE_CX16) ||
1521 ((h->efr_attr & (0x1 << IOMMU_FEAT_GASUP_SHIFT)) == 0))
1515 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;1522 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
1516 break;1523 break;
1517 case 0x11:1524 case 0x11:
@@ -1520,8 +1527,18 @@ static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h) · 2 unmodified lines
1520 iommu->mmio_phys_end = MMIO_REG_END_OFFSET;1527 iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
1521 else1528 else
1522 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;1529 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
1523 if (((h->efr_reg & (0x1 << IOMMU_EFR_GASUP_SHIFT)) == 0))1530
1531 /*
1532 * Note: GA (128-bit IRTE) mode requires cmpxchg16b supports.
1533 * XT, GAM also requires GA mode. Therefore, we need to
1534 * check cmpxchg16b support before enabling them.
1535 */
1536 if (!boot_cpu_has(X86_FEATURE_CX16) ||
1537 ((h->efr_reg & (0x1 << IOMMU_EFR_GASUP_SHIFT)) == 0)) {
1524 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;1538 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
1539 break;
1540 }
1541
1525 /*1542 /*
1526 * Note: Since iommu_update_intcapxt() leverages1543 * Note: Since iommu_update_intcapxt() leverages
1527 * the IOMMU MMIO access to MSI capability block registers1544 * the IOMMU MMIO access to MSI capability block registers
@@ -2258,7 +2275,7 @@ static void iommu_enable_ga(struct amd_iommu *iommu) · 730 unmodified lines
2258 switch (amd_iommu_guest_ir) {2275 switch (amd_iommu_guest_ir) {
2259 case AMD_IOMMU_GUEST_IR_VAPIC:2276 case AMD_IOMMU_GUEST_IR_VAPIC:
2260 iommu_feature_enable(iommu, CONTROL_GAM_EN);2277 iommu_feature_enable(iommu, CONTROL_GAM_EN);
2261 /* Fall through */2278 fallthrough;
2262 case AMD_IOMMU_GUEST_IR_LEGACY_GA:2279 case AMD_IOMMU_GUEST_IR_LEGACY_GA:
2263 iommu_feature_enable(iommu, CONTROL_GA_EN);2280 iommu_feature_enable(iommu, CONTROL_GA_EN);
2264 iommu->irte_ops = &irte_128_ops;2281 iommu->irte_ops = &irte_128_ops;
drivers/iommu/amd/iommu.c+21−5
@@ -2659,7 +2659,12 @@ static int amd_iommu_def_domain_type(struct device *dev) · 2658 unmodified lines
2659 if (!dev_data)2659 if (!dev_data)
2660 return 0;2660 return 0;
2661 2661
2662 if (dev_data->iommu_v2)2662 /*
2663 * Do not identity map IOMMUv2 capable devices when memory encryption is
2664 * active, because some of those devices (AMD GPUs) don't have the
2665 * encryption bit in their DMA-mask and require remapping.
2666 */
2667 if (!mem_encrypt_active() && dev_data->iommu_v2)
2663 return IOMMU_DOMAIN_IDENTITY;2668 return IOMMU_DOMAIN_IDENTITY;
2664 2669
2665 return 0;2670 return 0;
@@ -3292,6 +3297,7 @@ out: · 626 unmodified lines
3292static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte,3297static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte,
3293 struct amd_ir_data *data)3298 struct amd_ir_data *data)
3294{3299{
3300 bool ret;
3295 struct irq_remap_table *table;3301 struct irq_remap_table *table;
3296 struct amd_iommu *iommu;3302 struct amd_iommu *iommu;
3297 unsigned long flags;3303 unsigned long flags;
@@ -3309,10 +3315,18 @@ static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte, · 11 unmodified lines
3309 3315
3310 entry = (struct irte_ga *)table->table;3316 entry = (struct irte_ga *)table->table;
3311 entry = &entry[index];3317 entry = &entry[index];
3312 entry->lo.fields_remap.valid = 0;3318
3313 entry->hi.val = irte->hi.val;3319 ret = cmpxchg_double(&entry->lo.val, &entry->hi.val,
3314 entry->lo.val = irte->lo.val;3320 entry->lo.val, entry->hi.val,
3315 entry->lo.fields_remap.valid = 1;3321 irte->lo.val, irte->hi.val);
3322 /*
3323 * We use cmpxchg16 to atomically update the 128-bit IRTE,
3324 * and it cannot be updated by the hardware or other processors
3325 * behind us, so the return value of cmpxchg16 should be the
3326 * same as the old value.
3327 */
3328 WARN_ON(!ret);
3329
3316 if (data)3330 if (data)
3317 data->ref = entry;3331 data->ref = entry;
3318 3332
@@ -3850,6 +3864,7 @@ int amd_iommu_deactivate_guest_mode(void *data) · 531 unmodified lines
3850 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;3864 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
3851 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;3865 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
3852 struct irq_cfg *cfg = ir_data->cfg;3866 struct irq_cfg *cfg = ir_data->cfg;
3867 u64 valid = entry->lo.fields_remap.valid;
3853 3868
3854 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||3869 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
3855 !entry || !entry->lo.fields_vapic.guest_mode)3870 !entry || !entry->lo.fields_vapic.guest_mode)
@@ -3858,6 +3873,7 @@ int amd_iommu_deactivate_guest_mode(void *data) · 2 unmodified lines
3858 entry->lo.val = 0;3873 entry->lo.val = 0;
3859 entry->hi.val = 0;3874 entry->hi.val = 0;
3860 3875
3876 entry->lo.fields_remap.valid = valid;
3861 entry->lo.fields_remap.dm = apic->irq_dest_mode;3877 entry->lo.fields_remap.dm = apic->irq_dest_mode;
3862 entry->lo.fields_remap.int_type = apic->irq_delivery_mode;3878 entry->lo.fields_remap.int_type = apic->irq_delivery_mode;
3863 entry->hi.fields.vector = cfg->vector;3879 entry->hi.fields.vector = cfg->vector;
drivers/iommu/amd/iommu_v2.c+7−0
@@ -737,6 +737,13 @@ int amd_iommu_init_device(struct pci_dev *pdev, int pasids) · 736 unmodified lines
737 737
738 might_sleep();738 might_sleep();
739 739
740 /*
741 * When memory encryption is active the device is likely not in a
742 * direct-mapped domain. Forbid using IOMMUv2 functionality for now.
743 */
744 if (mem_encrypt_active())
745 return -ENODEV;
746
740 if (!amd_iommu_v2_supported())747 if (!amd_iommu_v2_supported())
741 return -ENODEV;748 return -ENODEV;
742 749
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c+5−6
@@ -903,7 +903,7 @@ static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent) · 902 unmodified lines
903 break;903 break;
904 case CMDQ_OP_CFGI_CD:904 case CMDQ_OP_CFGI_CD:
905 cmd[0] |= FIELD_PREP(CMDQ_CFGI_0_SSID, ent->cfgi.ssid);905 cmd[0] |= FIELD_PREP(CMDQ_CFGI_0_SSID, ent->cfgi.ssid);
906 /* Fallthrough */906 fallthrough;
907 case CMDQ_OP_CFGI_STE:907 case CMDQ_OP_CFGI_STE:
908 cmd[0] |= FIELD_PREP(CMDQ_CFGI_0_SID, ent->cfgi.sid);908 cmd[0] |= FIELD_PREP(CMDQ_CFGI_0_SID, ent->cfgi.sid);
909 cmd[1] |= FIELD_PREP(CMDQ_CFGI_1_LEAF, ent->cfgi.leaf);909 cmd[1] |= FIELD_PREP(CMDQ_CFGI_1_LEAF, ent->cfgi.leaf);
@@ -936,7 +936,7 @@ static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent) · 26 unmodified lines
936 break;936 break;
937 case CMDQ_OP_TLBI_NH_ASID:937 case CMDQ_OP_TLBI_NH_ASID:
938 cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_ASID, ent->tlbi.asid);938 cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_ASID, ent->tlbi.asid);
939 /* Fallthrough */939 fallthrough;
940 case CMDQ_OP_TLBI_S12_VMALL:940 case CMDQ_OP_TLBI_S12_VMALL:
941 cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_VMID, ent->tlbi.vmid);941 cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_VMID, ent->tlbi.vmid);
942 break;942 break;
@@ -1036,7 +1036,6 @@ static void arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu) · 93 unmodified lines
1036 */1036 */
1037 return;1037 return;
1038 case CMDQ_ERR_CERROR_ILL_IDX:1038 case CMDQ_ERR_CERROR_ILL_IDX:
1039 /* Fallthrough */
1040 default:1039 default:
1041 break;1040 break;
1042 }1041 }
@@ -3758,7 +3757,7 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu) · 2715 unmodified lines
3758 switch (FIELD_GET(IDR0_STALL_MODEL, reg)) {3757 switch (FIELD_GET(IDR0_STALL_MODEL, reg)) {
3759 case IDR0_STALL_MODEL_FORCE:3758 case IDR0_STALL_MODEL_FORCE:
3760 smmu->features |= ARM_SMMU_FEAT_STALL_FORCE;3759 smmu->features |= ARM_SMMU_FEAT_STALL_FORCE;
3761 /* Fallthrough */3760 fallthrough;
3762 case IDR0_STALL_MODEL_STALL:3761 case IDR0_STALL_MODEL_STALL:
3763 smmu->features |= ARM_SMMU_FEAT_STALLS;3762 smmu->features |= ARM_SMMU_FEAT_STALLS;
3764 }3763 }
@@ -3778,7 +3777,7 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu) · 13 unmodified lines
3778 switch (FIELD_GET(IDR0_TTF, reg)) {3777 switch (FIELD_GET(IDR0_TTF, reg)) {
3779 case IDR0_TTF_AARCH32_64:3778 case IDR0_TTF_AARCH32_64:
3780 smmu->ias = 40;3779 smmu->ias = 40;
3781 /* Fallthrough */3780 fallthrough;
3782 case IDR0_TTF_AARCH64:3781 case IDR0_TTF_AARCH64:
3783 break;3782 break;
3784 default:3783 default:
@@ -3875,7 +3874,7 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu) · 90 unmodified lines
3875 default:3874 default:
3876 dev_info(smmu->dev,3875 dev_info(smmu->dev,
3877 "unknown output address size. Truncating to 48-bit\n");3876 "unknown output address size. Truncating to 48-bit\n");
3878 /* Fallthrough */3877 fallthrough;
3879 case IDR5_OAS_48_BIT:3878 case IDR5_OAS_48_BIT:
3880 smmu->oas = 48;3879 smmu->oas = 48;
3881 }3880 }
drivers/iommu/dma-iommu.c+2−2
@@ -1035,8 +1035,8 @@ static void *iommu_dma_alloc(struct device *dev, size_t size, · 1034 unmodified lines
1035 1035
1036 if (IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&1036 if (IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
1037 !gfpflags_allow_blocking(gfp) && !coherent)1037 !gfpflags_allow_blocking(gfp) && !coherent)
1038 cpu_addr = dma_alloc_from_pool(dev, PAGE_ALIGN(size), &page,1038 page = dma_alloc_from_pool(dev, PAGE_ALIGN(size), &cpu_addr,
1039 gfp);1039 gfp, NULL);
1040 else1040 else
1041 cpu_addr = iommu_dma_alloc_pages(dev, size, &page, gfp, attrs);1041 cpu_addr = iommu_dma_alloc_pages(dev, size, &page, gfp, attrs);
1042 if (!cpu_addr)1042 if (!cpu_addr)
drivers/iommu/intel/iommu.c+62−53
@@ -123,29 +123,29 @@ static inline unsigned int level_to_offset_bits(int level) · 122 unmodified lines
123 return (level - 1) * LEVEL_STRIDE;123 return (level - 1) * LEVEL_STRIDE;
124}124}
125 125
126static inline int pfn_level_offset(unsigned long pfn, int level)126static inline int pfn_level_offset(u64 pfn, int level)
127{127{
128 return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK;128 return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK;
129}129}
130 130
131static inline unsigned long level_mask(int level)131static inline u64 level_mask(int level)
132{132{
133 return -1UL << level_to_offset_bits(level);133 return -1ULL << level_to_offset_bits(level);
134}134}
135 135
136static inline unsigned long level_size(int level)136static inline u64 level_size(int level)
137{137{
138 return 1UL << level_to_offset_bits(level);138 return 1ULL << level_to_offset_bits(level);
139}139}
140 140
141static inline unsigned long align_to_level(unsigned long pfn, int level)141static inline u64 align_to_level(u64 pfn, int level)
142{142{
143 return (pfn + level_size(level) - 1) & level_mask(level);143 return (pfn + level_size(level) - 1) & level_mask(level);
144}144}
145 145
146static inline unsigned long lvl_to_nr_pages(unsigned int lvl)146static inline unsigned long lvl_to_nr_pages(unsigned int lvl)
147{147{
148 return 1 << min_t(int, (lvl - 1) * LEVEL_STRIDE, MAX_AGAW_PFN_WIDTH);148 return 1UL << min_t(int, (lvl - 1) * LEVEL_STRIDE, MAX_AGAW_PFN_WIDTH);
149}149}
150 150
151/* VT-d pages must always be _smaller_ than MM pages. Otherwise things151/* VT-d pages must always be _smaller_ than MM pages. Otherwise things
@@ -364,7 +364,6 @@ static int iommu_skip_te_disable; · 212 unmodified lines
364int intel_iommu_gfx_mapped;364int intel_iommu_gfx_mapped;
365EXPORT_SYMBOL_GPL(intel_iommu_gfx_mapped);365EXPORT_SYMBOL_GPL(intel_iommu_gfx_mapped);
366 366
367#define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
368#define DEFER_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-2))367#define DEFER_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-2))
369struct device_domain_info *get_domain_info(struct device *dev)368struct device_domain_info *get_domain_info(struct device *dev)
370{369{
@@ -374,8 +373,7 @@ struct device_domain_info *get_domain_info(struct device *dev) · 3 unmodified lines
374 return NULL;373 return NULL;
375 374
376 info = dev_iommu_priv_get(dev);375 info = dev_iommu_priv_get(dev);
377 if (unlikely(info == DUMMY_DEVICE_DOMAIN_INFO ||376 if (unlikely(info == DEFER_DEVICE_DOMAIN_INFO))
378 info == DEFER_DEVICE_DOMAIN_INFO))
379 return NULL;377 return NULL;
380 378
381 return info;379 return info;
@@ -742,11 +740,6 @@ struct context_entry *iommu_context_addr(struct intel_iommu *iommu, u8 bus, · 360 unmodified lines
742 return &context[devfn];740 return &context[devfn];
743}741}
744 742
745static int iommu_dummy(struct device *dev)
746{
747 return dev_iommu_priv_get(dev) == DUMMY_DEVICE_DOMAIN_INFO;
748}
749
750static bool attach_deferred(struct device *dev)743static bool attach_deferred(struct device *dev)
751{744{
752 return dev_iommu_priv_get(dev) == DEFER_DEVICE_DOMAIN_INFO;745 return dev_iommu_priv_get(dev) == DEFER_DEVICE_DOMAIN_INFO;
@@ -779,6 +772,53 @@ is_downstream_to_pci_bridge(struct device *dev, struct device *bridge) · 26 unmodified lines
779 return false;772 return false;
780}773}
781 774
775static bool quirk_ioat_snb_local_iommu(struct pci_dev *pdev)
776{
777 struct dmar_drhd_unit *drhd;
778 u32 vtbar;
779 int rc;
780
781 /* We know that this device on this chipset has its own IOMMU.
782 * If we find it under a different IOMMU, then the BIOS is lying
783 * to us. Hope that the IOMMU for this device is actually
784 * disabled, and it needs no translation...
785 */
786 rc = pci_bus_read_config_dword(pdev->bus, PCI_DEVFN(0, 0), 0xb0, &vtbar);
787 if (rc) {
788 /* "can't" happen */
789 dev_info(&pdev->dev, "failed to run vt-d quirk\n");
790 return false;
791 }
792 vtbar &= 0xffff0000;
793
794 /* we know that the this iommu should be at offset 0xa000 from vtbar */
795 drhd = dmar_find_matched_drhd_unit(pdev);
796 if (!drhd || drhd->reg_base_addr - vtbar != 0xa000) {
797 pr_warn_once(FW_BUG "BIOS assigned incorrect VT-d unit for Intel(R) QuickData Technology device\n");
798 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
799 return true;
800 }
801
802 return false;
803}
804
805static bool iommu_is_dummy(struct intel_iommu *iommu, struct device *dev)
806{
807 if (!iommu || iommu->drhd->ignored)
808 return true;
809
810 if (dev_is_pci(dev)) {
811 struct pci_dev *pdev = to_pci_dev(dev);
812
813 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
814 pdev->device == PCI_DEVICE_ID_INTEL_IOAT_SNB &&
815 quirk_ioat_snb_local_iommu(pdev))
816 return true;
817 }
818
819 return false;
820}
821
782struct intel_iommu *device_to_iommu(struct device *dev, u8 *bus, u8 *devfn)822struct intel_iommu *device_to_iommu(struct device *dev, u8 *bus, u8 *devfn)
783{823{
784 struct dmar_drhd_unit *drhd = NULL;824 struct dmar_drhd_unit *drhd = NULL;
@@ -788,7 +828,7 @@ struct intel_iommu *device_to_iommu(struct device *dev, u8 *bus, u8 *devfn) · 3 unmodified lines
788 u16 segment = 0;828 u16 segment = 0;
789 int i;829 int i;
790 830
791 if (!dev || iommu_dummy(dev))831 if (!dev)
792 return NULL;832 return NULL;
793 833
794 if (dev_is_pci(dev)) {834 if (dev_is_pci(dev)) {
@@ -805,7 +845,7 @@ struct intel_iommu *device_to_iommu(struct device *dev, u8 *bus, u8 *devfn) · 10 unmodified lines
805 dev = &ACPI_COMPANION(dev)->dev;845 dev = &ACPI_COMPANION(dev)->dev;
806 846
807 rcu_read_lock();847 rcu_read_lock();
808 for_each_active_iommu(iommu, drhd) {848 for_each_iommu(iommu, drhd) {
809 if (pdev && segment != drhd->segment)849 if (pdev && segment != drhd->segment)
810 continue;850 continue;
811 851
@@ -841,6 +881,9 @@ struct intel_iommu *device_to_iommu(struct device *dev, u8 *bus, u8 *devfn) · 29 unmodified lines
841 }881 }
842 iommu = NULL;882 iommu = NULL;
843 out:883 out:
884 if (iommu_is_dummy(iommu, dev))
885 iommu = NULL;
886
844 rcu_read_unlock();887 rcu_read_unlock();
845 888
846 return iommu;889 return iommu;
@@ -2447,7 +2490,7 @@ struct dmar_domain *find_domain(struct device *dev) · 1600 unmodified lines
2447{2490{
2448 struct device_domain_info *info;2491 struct device_domain_info *info;
2449 2492
2450 if (unlikely(attach_deferred(dev) || iommu_dummy(dev)))2493 if (unlikely(attach_deferred(dev)))
2451 return NULL;2494 return NULL;
2452 2495
2453 /* No lock here, assumes no domain exit in normal case */2496 /* No lock here, assumes no domain exit in normal case */
@@ -3989,35 +4032,6 @@ static void __init iommu_exit_mempool(void) · 1535 unmodified lines
3989 iova_cache_put();4032 iova_cache_put();
3990}4033}
3991 4034
3992static void quirk_ioat_snb_local_iommu(struct pci_dev *pdev)
3993{
3994 struct dmar_drhd_unit *drhd;
3995 u32 vtbar;
3996 int rc;
3997
3998 /* We know that this device on this chipset has its own IOMMU.
3999 * If we find it under a different IOMMU, then the BIOS is lying
4000 * to us. Hope that the IOMMU for this device is actually
4001 * disabled, and it needs no translation...
4002 */
4003 rc = pci_bus_read_config_dword(pdev->bus, PCI_DEVFN(0, 0), 0xb0, &vtbar);
4004 if (rc) {
4005 /* "can't" happen */
4006 dev_info(&pdev->dev, "failed to run vt-d quirk\n");
4007 return;
4008 }
4009 vtbar &= 0xffff0000;
4010
4011 /* we know that the this iommu should be at offset 0xa000 from vtbar */
4012 drhd = dmar_find_matched_drhd_unit(pdev);
4013 if (!drhd || drhd->reg_base_addr - vtbar != 0xa000) {
4014 pr_warn_once(FW_BUG "BIOS assigned incorrect VT-d unit for Intel(R) QuickData Technology device\n");
4015 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
4016 dev_iommu_priv_set(&pdev->dev, DUMMY_DEVICE_DOMAIN_INFO);
4017 }
4018}
4019DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB, quirk_ioat_snb_local_iommu);
4020
4021static void __init init_no_remapping_devices(void)4035static void __init init_no_remapping_devices(void)
4022{4036{
4023 struct dmar_drhd_unit *drhd;4037 struct dmar_drhd_unit *drhd;
@@ -4049,12 +4063,8 @@ static void __init init_no_remapping_devices(void) · 25 unmodified lines
4049 /* This IOMMU has *only* gfx devices. Either bypass it or4063 /* This IOMMU has *only* gfx devices. Either bypass it or
4050 set the gfx_mapped flag, as appropriate */4064 set the gfx_mapped flag, as appropriate */
4051 drhd->gfx_dedicated = 1;4065 drhd->gfx_dedicated = 1;
4052 if (!dmar_map_gfx) {4066 if (!dmar_map_gfx)
4053 drhd->ignored = 1;4067 drhd->ignored = 1;
4054 for_each_active_dev_scope(drhd->devices,
4055 drhd->devices_cnt, i, dev)
4056 dev_iommu_priv_set(dev, DUMMY_DEVICE_DOMAIN_INFO);
4057 }
4058 }4068 }
4059}4069}
4060 4070
@@ -5070,7 +5080,6 @@ static struct iommu_domain *intel_iommu_domain_alloc(unsigned type) · 1009 unmodified lines
5070 5080
5071 switch (type) {5081 switch (type) {
5072 case IOMMU_DOMAIN_DMA:5082 case IOMMU_DOMAIN_DMA:
5073 /* fallthrough */
5074 case IOMMU_DOMAIN_UNMANAGED:5083 case IOMMU_DOMAIN_UNMANAGED:
5075 dmar_domain = alloc_domain(0);5084 dmar_domain = alloc_domain(0);
5076 if (!dmar_domain) {5085 if (!dmar_domain) {
drivers/iommu/intel/irq_remapping.c+8−2
@@ -508,12 +508,18 @@ static void iommu_enable_irq_remapping(struct intel_iommu *iommu) · 507 unmodified lines
508 508
509 /* Enable interrupt-remapping */509 /* Enable interrupt-remapping */
510 iommu->gcmd |= DMA_GCMD_IRE;510 iommu->gcmd |= DMA_GCMD_IRE;
511 iommu->gcmd &= ~DMA_GCMD_CFI; /* Block compatibility-format MSIs */
512 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);511 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
513
514 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,512 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
515 readl, (sts & DMA_GSTS_IRES), sts);513 readl, (sts & DMA_GSTS_IRES), sts);
516 514
515 /* Block compatibility-format MSIs */
516 if (sts & DMA_GSTS_CFIS) {
517 iommu->gcmd &= ~DMA_GCMD_CFI;
518 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
519 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
520 readl, !(sts & DMA_GSTS_CFIS), sts);
521 }
522
517 /*523 /*
518 * With CFI clear in the Global Command register, we should be524 * With CFI clear in the Global Command register, we should be
519 * protected from dangerous (i.e. compatibility) interrupts525 * protected from dangerous (i.e. compatibility) interrupts
drivers/iommu/virtio-iommu.c+1−1
@@ -440,7 +440,7 @@ static int viommu_add_resv_mem(struct viommu_endpoint *vdev, · 439 unmodified lines
440 default:440 default:
441 dev_warn(vdev->dev, "unknown resv mem subtype 0x%x\n",441 dev_warn(vdev->dev, "unknown resv mem subtype 0x%x\n",
442 mem->subtype);442 mem->subtype);
443 /* Fall-through */443 fallthrough;
444 case VIRTIO_IOMMU_RESV_MEM_T_RESERVED:444 case VIRTIO_IOMMU_RESV_MEM_T_RESERVED:
445 region = iommu_alloc_resv_region(start, size, 0,445 region = iommu_alloc_resv_region(start, size, 0,
446 IOMMU_RESV_RESERVED);446 IOMMU_RESV_RESERVED);
drivers/irqchip/Kconfig+1−1
@@ -425,7 +425,7 @@ config GOLDFISH_PIC · 424 unmodified lines
425 for Goldfish based virtual platforms.425 for Goldfish based virtual platforms.
426 426
427config QCOM_PDC427config QCOM_PDC
428 tristate "QCOM PDC"428 bool "QCOM PDC"
429 depends on ARCH_QCOM429 depends on ARCH_QCOM
430 select IRQ_DOMAIN_HIERARCHY430 select IRQ_DOMAIN_HIERARCHY
431 help431 help
drivers/irqchip/irq-gic-v3-its.c+2−2
@@ -2737,7 +2737,7 @@ static bool allocate_vpe_l2_table(int cpu, u32 id) · 2736 unmodified lines
2737 switch (gpsz) {2737 switch (gpsz) {
2738 default:2738 default:
2739 WARN_ON(1);2739 WARN_ON(1);
2740 /* fall through */2740 fallthrough;
2741 case GIC_PAGE_SIZE_4K:2741 case GIC_PAGE_SIZE_4K:
2742 psz = SZ_4K;2742 psz = SZ_4K;
2743 break;2743 break;
@@ -2832,7 +2832,7 @@ static int allocate_vpe_l1_table(void) · 88 unmodified lines
2832 switch (gpsz) {2832 switch (gpsz) {
2833 default:2833 default:
2834 gpsz = GIC_PAGE_SIZE_4K;2834 gpsz = GIC_PAGE_SIZE_4K;
2835 /* fall through */2835 fallthrough;
2836 case GIC_PAGE_SIZE_4K:2836 case GIC_PAGE_SIZE_4K:
2837 psz = SZ_4K;2837 psz = SZ_4K;
2838 break;2838 break;
drivers/irqchip/irq-gic-v3.c+4−4
@@ -965,10 +965,10 @@ static void gic_cpu_sys_reg_init(void) · 964 unmodified lines
965 case 7:965 case 7:
966 write_gicreg(0, ICC_AP0R3_EL1);966 write_gicreg(0, ICC_AP0R3_EL1);
967 write_gicreg(0, ICC_AP0R2_EL1);967 write_gicreg(0, ICC_AP0R2_EL1);
968 /* Fall through */968 fallthrough;
969 case 6:969 case 6:
970 write_gicreg(0, ICC_AP0R1_EL1);970 write_gicreg(0, ICC_AP0R1_EL1);
971 /* Fall through */971 fallthrough;
972 case 5:972 case 5:
973 case 4:973 case 4:
974 write_gicreg(0, ICC_AP0R0_EL1);974 write_gicreg(0, ICC_AP0R0_EL1);
@@ -982,10 +982,10 @@ static void gic_cpu_sys_reg_init(void) · 7 unmodified lines
982 case 7:982 case 7:
983 write_gicreg(0, ICC_AP1R3_EL1);983 write_gicreg(0, ICC_AP1R3_EL1);
984 write_gicreg(0, ICC_AP1R2_EL1);984 write_gicreg(0, ICC_AP1R2_EL1);
985 /* Fall through */985 fallthrough;
986 case 6:986 case 6:
987 write_gicreg(0, ICC_AP1R1_EL1);987 write_gicreg(0, ICC_AP1R1_EL1);
988 /* Fall through */988 fallthrough;
989 case 5:989 case 5:
990 case 4:990 case 4:
991 write_gicreg(0, ICC_AP1R0_EL1);991 write_gicreg(0, ICC_AP1R0_EL1);
drivers/irqchip/irq-imx-gpcv2.c+1−1
@@ -259,7 +259,7 @@ static int __init imx_gpcv2_irqchip_init(struct device_node *node, · 258 unmodified lines
259 case 4:259 case 4:
260 writel_relaxed(~0, reg + GPC_IMR1_CORE2);260 writel_relaxed(~0, reg + GPC_IMR1_CORE2);
261 writel_relaxed(~0, reg + GPC_IMR1_CORE3);261 writel_relaxed(~0, reg + GPC_IMR1_CORE3);
262 /* fall through */262 fallthrough;
263 case 2:263 case 2:
264 writel_relaxed(~0, reg + GPC_IMR1_CORE0);264 writel_relaxed(~0, reg + GPC_IMR1_CORE0);
265 writel_relaxed(~0, reg + GPC_IMR1_CORE1);265 writel_relaxed(~0, reg + GPC_IMR1_CORE1);
drivers/irqchip/irq-ingenic.c+1−1
@@ -125,7 +125,7 @@ static int __init ingenic_intc_of_init(struct device_node *node, · 124 unmodified lines
125 irq_reg_writel(gc, IRQ_MSK(32), JZ_REG_INTC_SET_MASK);125 irq_reg_writel(gc, IRQ_MSK(32), JZ_REG_INTC_SET_MASK);
126 }126 }
127 127
128 if (request_irq(parent_irq, intc_cascade, 0,128 if (request_irq(parent_irq, intc_cascade, IRQF_NO_SUSPEND,
129 "SoC intc cascade interrupt", NULL))129 "SoC intc cascade interrupt", NULL))
130 pr_err("Failed to register SoC intc cascade interrupt\n");130 pr_err("Failed to register SoC intc cascade interrupt\n");
131 return 0;131 return 0;
drivers/irqchip/irq-mips-gic.c+1−1
@@ -480,7 +480,7 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq, · 479 unmodified lines
480 case GIC_LOCAL_INT_TIMER:480 case GIC_LOCAL_INT_TIMER:
481 /* CONFIG_MIPS_CMP workaround (see __gic_init) */481 /* CONFIG_MIPS_CMP workaround (see __gic_init) */
482 map = GIC_MAP_PIN_MAP_TO_PIN | timer_cpu_pin;482 map = GIC_MAP_PIN_MAP_TO_PIN | timer_cpu_pin;
483 /* fall-through */483 fallthrough;
484 case GIC_LOCAL_INT_PERFCTR:484 case GIC_LOCAL_INT_PERFCTR:
485 case GIC_LOCAL_INT_FDC:485 case GIC_LOCAL_INT_FDC:
486 /*486 /*
drivers/irqchip/irq-mtk-cirq.c+1−3
@@ -295,6 +295,4 @@ out_free: · 294 unmodified lines
295 return ret;295 return ret;
296}296}
297 297
298IRQCHIP_PLATFORM_DRIVER_BEGIN(mtk_cirq)298IRQCHIP_DECLARE(mtk_cirq, "mediatek,mtk-cirq", mtk_cirq_of_init);
299IRQCHIP_MATCH("mediatek,mtk-cirq", mtk_cirq_of_init)
300IRQCHIP_PLATFORM_DRIVER_END(mtk_cirq)
drivers/irqchip/irq-mtk-sysirq.c+1−3
@@ -231,6 +231,4 @@ out_free_chip: · 230 unmodified lines
231 kfree(chip_data);231 kfree(chip_data);
232 return ret;232 return ret;
233}233}
234IRQCHIP_PLATFORM_DRIVER_BEGIN(mtk_sysirq)234IRQCHIP_DECLARE(mtk_sysirq, "mediatek,mt6577-sysirq", mtk_sysirq_of_init);
235IRQCHIP_MATCH("mediatek,mt6577-sysirq", mtk_sysirq_of_init)
236IRQCHIP_PLATFORM_DRIVER_END(mtk_sysirq)
drivers/irqchip/irq-stm32-exti.c+12−2
@@ -416,6 +416,16 @@ static void stm32_irq_ack(struct irq_data *d) · 415 unmodified lines
416 irq_gc_unlock(gc);416 irq_gc_unlock(gc);
417}417}
418 418
419/* directly set the target bit without reading first. */
420static inline void stm32_exti_write_bit(struct irq_data *d, u32 reg)
421{
422 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
423 void __iomem *base = chip_data->host_data->base;
424 u32 val = BIT(d->hwirq % IRQS_PER_BANK);
425
426 writel_relaxed(val, base + reg);
427}
428
419static inline u32 stm32_exti_set_bit(struct irq_data *d, u32 reg)429static inline u32 stm32_exti_set_bit(struct irq_data *d, u32 reg)
420{430{
421 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);431 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
@@ -449,9 +459,9 @@ static void stm32_exti_h_eoi(struct irq_data *d) · 27 unmodified lines
449 459
450 raw_spin_lock(&chip_data->rlock);460 raw_spin_lock(&chip_data->rlock);
451 461
452 stm32_exti_set_bit(d, stm32_bank->rpr_ofst);462 stm32_exti_write_bit(d, stm32_bank->rpr_ofst);
453 if (stm32_bank->fpr_ofst != UNDEF_REG)463 if (stm32_bank->fpr_ofst != UNDEF_REG)
454 stm32_exti_set_bit(d, stm32_bank->fpr_ofst);464 stm32_exti_write_bit(d, stm32_bank->fpr_ofst);
455 465
456 raw_spin_unlock(&chip_data->rlock);466 raw_spin_unlock(&chip_data->rlock);
457 467
drivers/irqchip/irq-ti-sci-inta.c+79−16
@@ -8,6 +8,7 @@ · 7 unmodified lines
8 8
9#include <linux/err.h>9#include <linux/err.h>
10#include <linux/io.h>10#include <linux/io.h>
11#include <linux/irq.h>
11#include <linux/irqchip.h>12#include <linux/irqchip.h>
12#include <linux/irqdomain.h>13#include <linux/irqdomain.h>
13#include <linux/interrupt.h>14#include <linux/interrupt.h>
@@ -83,6 +84,7 @@ struct ti_sci_inta_vint_desc { · 69 unmodified lines
83 * @vint_mutex: Mutex to protect vint_list84 * @vint_mutex: Mutex to protect vint_list
84 * @base: Base address of the memory mapped IO registers85 * @base: Base address of the memory mapped IO registers
85 * @pdev: Pointer to platform device.86 * @pdev: Pointer to platform device.
87 * @ti_sci_id: TI-SCI device identifier
86 */88 */
87struct ti_sci_inta_irq_domain {89struct ti_sci_inta_irq_domain {
88 const struct ti_sci_handle *sci;90 const struct ti_sci_handle *sci;
@@ -93,6 +95,7 @@ struct ti_sci_inta_irq_domain { · 4 unmodified lines
93 struct mutex vint_mutex;95 struct mutex vint_mutex;
94 void __iomem *base;96 void __iomem *base;
95 struct platform_device *pdev;97 struct platform_device *pdev;
98 u32 ti_sci_id;
96};99};
97 100
98#define to_vint_desc(e, i) container_of(e, struct ti_sci_inta_vint_desc, \101#define to_vint_desc(e, i) container_of(e, struct ti_sci_inta_vint_desc, \
@@ -128,6 +131,37 @@ static void ti_sci_inta_irq_handler(struct irq_desc *desc) · 29 unmodified lines
128 chained_irq_exit(irq_desc_get_chip(desc), desc);131 chained_irq_exit(irq_desc_get_chip(desc), desc);
129}132}
130 133
134/**
135 * ti_sci_inta_xlate_irq() - Translate hwirq to parent's hwirq.
136 * @inta: IRQ domain corresponding to Interrupt Aggregator
137 * @irq: Hardware irq corresponding to the above irq domain
138 *
139 * Return parent irq number if translation is available else -ENOENT.
140 */
141static int ti_sci_inta_xlate_irq(struct ti_sci_inta_irq_domain *inta,
142 u16 vint_id)
143{
144 struct device_node *np = dev_of_node(&inta->pdev->dev);
145 u32 base, parent_base, size;
146 const __be32 *range;
147 int len;
148
149 range = of_get_property(np, "ti,interrupt-ranges", &len);
150 if (!range)
151 return vint_id;
152
153 for (len /= sizeof(*range); len >= 3; len -= 3) {
154 base = be32_to_cpu(*range++);
155 parent_base = be32_to_cpu(*range++);
156 size = be32_to_cpu(*range++);
157
158 if (base <= vint_id && vint_id < base + size)
159 return vint_id - base + parent_base;
160 }
161
162 return -ENOENT;
163}
164
131/**165/**
132 * ti_sci_inta_alloc_parent_irq() - Allocate parent irq to Interrupt aggregator166 * ti_sci_inta_alloc_parent_irq() - Allocate parent irq to Interrupt aggregator
133 * @domain: IRQ domain corresponding to Interrupt Aggregator167 * @domain: IRQ domain corresponding to Interrupt Aggregator
@@ -139,30 +173,52 @@ static struct ti_sci_inta_vint_desc *ti_sci_inta_alloc_parent_irq(struct irq_dom · 5 unmodified lines
139 struct ti_sci_inta_irq_domain *inta = domain->host_data;173 struct ti_sci_inta_irq_domain *inta = domain->host_data;
140 struct ti_sci_inta_vint_desc *vint_desc;174 struct ti_sci_inta_vint_desc *vint_desc;
141 struct irq_fwspec parent_fwspec;175 struct irq_fwspec parent_fwspec;
176 struct device_node *parent_node;
142 unsigned int parent_virq;177 unsigned int parent_virq;
143 u16 vint_id;178 u16 vint_id, p_hwirq;
179 int ret;
144 180
145 vint_id = ti_sci_get_free_resource(inta->vint);181 vint_id = ti_sci_get_free_resource(inta->vint);
146 if (vint_id == TI_SCI_RESOURCE_NULL)182 if (vint_id == TI_SCI_RESOURCE_NULL)
147 return ERR_PTR(-EINVAL);183 return ERR_PTR(-EINVAL);
148 184
185 p_hwirq = ti_sci_inta_xlate_irq(inta, vint_id);
186 if (p_hwirq < 0) {
187 ret = p_hwirq;
188 goto free_vint;
189 }
190
149 vint_desc = kzalloc(sizeof(*vint_desc), GFP_KERNEL);191 vint_desc = kzalloc(sizeof(*vint_desc), GFP_KERNEL);
150 if (!vint_desc)192 if (!vint_desc) {
151 return ERR_PTR(-ENOMEM);193 ret = -ENOMEM;
194 goto free_vint;
195 }
152 196
153 vint_desc->domain = domain;197 vint_desc->domain = domain;
154 vint_desc->vint_id = vint_id;198 vint_desc->vint_id = vint_id;
155 INIT_LIST_HEAD(&vint_desc->list);199 INIT_LIST_HEAD(&vint_desc->list);
156 200
157 parent_fwspec.fwnode = of_node_to_fwnode(of_irq_find_parent(dev_of_node(&inta->pdev->dev)));201 parent_node = of_irq_find_parent(dev_of_node(&inta->pdev->dev));
158 parent_fwspec.param_count = 2;202 parent_fwspec.fwnode = of_node_to_fwnode(parent_node);
159 parent_fwspec.param[0] = inta->pdev->id;203
160 parent_fwspec.param[1] = vint_desc->vint_id;204 if (of_device_is_compatible(parent_node, "arm,gic-v3")) {
205 /* Parent is GIC */
206 parent_fwspec.param_count = 3;
207 parent_fwspec.param[0] = 0;
208 parent_fwspec.param[1] = p_hwirq - 32;
209 parent_fwspec.param[2] = IRQ_TYPE_LEVEL_HIGH;
210 } else {
211 /* Parent is Interrupt Router */
212 parent_fwspec.param_count = 1;
213 parent_fwspec.param[0] = p_hwirq;
214 }
161 215
162 parent_virq = irq_create_fwspec_mapping(&parent_fwspec);216 parent_virq = irq_create_fwspec_mapping(&parent_fwspec);
163 if (parent_virq == 0) {217 if (parent_virq == 0) {
164 kfree(vint_desc);218 dev_err(&inta->pdev->dev, "Parent IRQ allocation failed\n");
165 return ERR_PTR(-EINVAL);219 ret = -EINVAL;
220 goto free_vint_desc;
221
166 }222 }
167 vint_desc->parent_virq = parent_virq;223 vint_desc->parent_virq = parent_virq;
168 224
@@ -171,6 +227,11 @@ static struct ti_sci_inta_vint_desc *ti_sci_inta_alloc_parent_irq(struct irq_dom · 2 unmodified lines
171 ti_sci_inta_irq_handler, vint_desc);227 ti_sci_inta_irq_handler, vint_desc);
172 228
173 return vint_desc;229 return vint_desc;
230free_vint_desc:
231 kfree(vint_desc);
232free_vint:
233 ti_sci_release_resource(inta->vint, vint_id);
234 return ERR_PTR(ret);
174}235}
175 236
176/**237/**
@@ -202,7 +263,7 @@ static struct ti_sci_inta_event_desc *ti_sci_inta_alloc_event(struct ti_sci_inta · 25 unmodified lines
202 263
203 err = inta->sci->ops.rm_irq_ops.set_event_map(inta->sci,264 err = inta->sci->ops.rm_irq_ops.set_event_map(inta->sci,
204 dev_id, dev_index,265 dev_id, dev_index,
205 inta->pdev->id,266 inta->ti_sci_id,
206 vint_desc->vint_id,267 vint_desc->vint_id,
207 event_desc->global_event,268 event_desc->global_event,
208 free_bit);269 free_bit);
@@ -299,7 +360,7 @@ static void ti_sci_inta_free_irq(struct ti_sci_inta_event_desc *event_desc, · 90 unmodified lines
299 inta->sci->ops.rm_irq_ops.free_event_map(inta->sci,360 inta->sci->ops.rm_irq_ops.free_event_map(inta->sci,
300 HWIRQ_TO_DEVID(hwirq),361 HWIRQ_TO_DEVID(hwirq),
301 HWIRQ_TO_IRQID(hwirq),362 HWIRQ_TO_IRQID(hwirq),
302 inta->pdev->id,363 inta->ti_sci_id,
303 vint_desc->vint_id,364 vint_desc->vint_id,
304 event_desc->global_event,365 event_desc->global_event,
305 event_desc->vint_bit);366 event_desc->vint_bit);
@@ -547,21 +608,21 @@ static int ti_sci_inta_irq_domain_probe(struct platform_device *pdev) · 241 unmodified lines
547 return ret;608 return ret;
548 }609 }
549 610
550 ret = of_property_read_u32(dev->of_node, "ti,sci-dev-id", &pdev->id);611 ret = of_property_read_u32(dev->of_node, "ti,sci-dev-id", &inta->ti_sci_id);
551 if (ret) {612 if (ret) {
552 dev_err(dev, "missing 'ti,sci-dev-id' property\n");613 dev_err(dev, "missing 'ti,sci-dev-id' property\n");
553 return -EINVAL;614 return -EINVAL;
554 }615 }
555 616
556 inta->vint = devm_ti_sci_get_of_resource(inta->sci, dev, pdev->id,617 inta->vint = devm_ti_sci_get_resource(inta->sci, dev, inta->ti_sci_id,
557 "ti,sci-rm-range-vint");618 TI_SCI_RESASG_SUBTYPE_IA_VINT);
558 if (IS_ERR(inta->vint)) {619 if (IS_ERR(inta->vint)) {
559 dev_err(dev, "VINT resource allocation failed\n");620 dev_err(dev, "VINT resource allocation failed\n");
560 return PTR_ERR(inta->vint);621 return PTR_ERR(inta->vint);
561 }622 }
562 623
563 inta->global_event = devm_ti_sci_get_of_resource(inta->sci, dev, pdev->id,624 inta->global_event = devm_ti_sci_get_resource(inta->sci, dev, inta->ti_sci_id,
564 "ti,sci-rm-range-global-event");625 TI_SCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT);
565 if (IS_ERR(inta->global_event)) {626 if (IS_ERR(inta->global_event)) {
566 dev_err(dev, "Global event resource allocation failed\n");627 dev_err(dev, "Global event resource allocation failed\n");
567 return PTR_ERR(inta->global_event);628 return PTR_ERR(inta->global_event);
@@ -592,6 +653,8 @@ static int ti_sci_inta_irq_domain_probe(struct platform_device *pdev) · 24 unmodified lines
592 INIT_LIST_HEAD(&inta->vint_list);653 INIT_LIST_HEAD(&inta->vint_list);
593 mutex_init(&inta->vint_mutex);654 mutex_init(&inta->vint_mutex);
594 655
656 dev_info(dev, "Interrupt Aggregator domain %d created\n", pdev->id);
657
595 return 0;658 return 0;
596}659}
597 660
drivers/irqchip/irq-ti-sci-intr.c+93−59
@@ -17,29 +17,20 @@ · 16 unmodified lines
17#include <linux/of_irq.h>17#include <linux/of_irq.h>
18#include <linux/soc/ti/ti_sci_protocol.h>18#include <linux/soc/ti/ti_sci_protocol.h>
19 19
20#define TI_SCI_DEV_ID_MASK 0xffff
21#define TI_SCI_DEV_ID_SHIFT 16
22#define TI_SCI_IRQ_ID_MASK 0xffff
23#define TI_SCI_IRQ_ID_SHIFT 0
24#define HWIRQ_TO_DEVID(hwirq) (((hwirq) >> (TI_SCI_DEV_ID_SHIFT)) & \
25 (TI_SCI_DEV_ID_MASK))
26#define HWIRQ_TO_IRQID(hwirq) ((hwirq) & (TI_SCI_IRQ_ID_MASK))
27#define TO_HWIRQ(dev, index) ((((dev) & TI_SCI_DEV_ID_MASK) << \
28 TI_SCI_DEV_ID_SHIFT) | \
29 ((index) & TI_SCI_IRQ_ID_MASK))
30
31/**20/**
32 * struct ti_sci_intr_irq_domain - Structure representing a TISCI based21 * struct ti_sci_intr_irq_domain - Structure representing a TISCI based
33 * Interrupt Router IRQ domain.22 * Interrupt Router IRQ domain.
34 * @sci: Pointer to TISCI handle23 * @sci: Pointer to TISCI handle
35 * @dst_irq: TISCI resource pointer representing GIC irq controller.24 * @out_irqs: TISCI resource pointer representing INTR irqs.
36 * @dst_id: TISCI device ID of the GIC irq controller.25 * @dev: Struct device pointer.
26 * @ti_sci_id: TI-SCI device identifier
37 * @type: Specifies the trigger type supported by this Interrupt Router27 * @type: Specifies the trigger type supported by this Interrupt Router
38 */28 */
39struct ti_sci_intr_irq_domain {29struct ti_sci_intr_irq_domain {
40 const struct ti_sci_handle *sci;30 const struct ti_sci_handle *sci;
41 struct ti_sci_resource *dst_irq;31 struct ti_sci_resource *out_irqs;
42 u32 dst_id;32 struct device *dev;
33 u32 ti_sci_id;
43 u32 type;34 u32 type;
44};35};
45 36
@@ -70,15 +61,44 @@ static int ti_sci_intr_irq_domain_translate(struct irq_domain *domain, · 24 unmodified lines
70{61{
71 struct ti_sci_intr_irq_domain *intr = domain->host_data;62 struct ti_sci_intr_irq_domain *intr = domain->host_data;
72 63
73 if (fwspec->param_count != 2)64 if (fwspec->param_count != 1)
74 return -EINVAL;65 return -EINVAL;
75 66
76 *hwirq = TO_HWIRQ(fwspec->param[0], fwspec->param[1]);67 *hwirq = fwspec->param[0];
77 *type = intr->type;68 *type = intr->type;
78 69
79 return 0;70 return 0;
80}71}
81 72
73/**
74 * ti_sci_intr_xlate_irq() - Translate hwirq to parent's hwirq.
75 * @intr: IRQ domain corresponding to Interrupt Router
76 * @irq: Hardware irq corresponding to the above irq domain
77 *
78 * Return parent irq number if translation is available else -ENOENT.
79 */
80static int ti_sci_intr_xlate_irq(struct ti_sci_intr_irq_domain *intr, u32 irq)
81{
82 struct device_node *np = dev_of_node(intr->dev);
83 u32 base, pbase, size, len;
84 const __be32 *range;
85
86 range = of_get_property(np, "ti,interrupt-ranges", &len);
87 if (!range)
88 return irq;
89
90 for (len /= sizeof(*range); len >= 3; len -= 3) {
91 base = be32_to_cpu(*range++);
92 pbase = be32_to_cpu(*range++);
93 size = be32_to_cpu(*range++);
94
95 if (base <= irq && irq < base + size)
96 return irq - base + pbase;
97 }
98
99 return -ENOENT;
100}
101
82/**102/**
83 * ti_sci_intr_irq_domain_free() - Free the specified IRQs from the domain.103 * ti_sci_intr_irq_domain_free() - Free the specified IRQs from the domain.
84 * @domain: Domain to which the irqs belong104 * @domain: Domain to which the irqs belong
@@ -89,66 +109,76 @@ static void ti_sci_intr_irq_domain_free(struct irq_domain *domain, · 4 unmodified lines
89 unsigned int virq, unsigned int nr_irqs)109 unsigned int virq, unsigned int nr_irqs)
90{110{
91 struct ti_sci_intr_irq_domain *intr = domain->host_data;111 struct ti_sci_intr_irq_domain *intr = domain->host_data;
92 struct irq_data *data, *parent_data;112 struct irq_data *data;
93 u16 dev_id, irq_index;113 int out_irq;
94 114
95 parent_data = irq_domain_get_irq_data(domain->parent, virq);
96 data = irq_domain_get_irq_data(domain, virq);115 data = irq_domain_get_irq_data(domain, virq);
97 irq_index = HWIRQ_TO_IRQID(data->hwirq);116 out_irq = (uintptr_t)data->chip_data;
98 dev_id = HWIRQ_TO_DEVID(data->hwirq);
99 117
100 intr->sci->ops.rm_irq_ops.free_irq(intr->sci, dev_id, irq_index,118 intr->sci->ops.rm_irq_ops.free_irq(intr->sci,
101 intr->dst_id, parent_data->hwirq);119 intr->ti_sci_id, data->hwirq,
102 ti_sci_release_resource(intr->dst_irq, parent_data->hwirq);120 intr->ti_sci_id, out_irq);
121 ti_sci_release_resource(intr->out_irqs, out_irq);
103 irq_domain_free_irqs_parent(domain, virq, 1);122 irq_domain_free_irqs_parent(domain, virq, 1);
104 irq_domain_reset_irq_data(data);123 irq_domain_reset_irq_data(data);
105}124}
106 125
107/**126/**
108 * ti_sci_intr_alloc_gic_irq() - Allocate GIC specific IRQ127 * ti_sci_intr_alloc_parent_irq() - Allocate parent IRQ
109 * @domain: Pointer to the interrupt router IRQ domain128 * @domain: Pointer to the interrupt router IRQ domain
110 * @virq: Corresponding Linux virtual IRQ number129 * @virq: Corresponding Linux virtual IRQ number
111 * @hwirq: Corresponding hwirq for the IRQ within this IRQ domain130 * @hwirq: Corresponding hwirq for the IRQ within this IRQ domain
112 *131 *
113 * Returns 0 if all went well else appropriate error pointer.132 * Returns parent irq if all went well else appropriate error pointer.
114 */133 */
115static int ti_sci_intr_alloc_gic_irq(struct irq_domain *domain,134static int ti_sci_intr_alloc_parent_irq(struct irq_domain *domain,
116 unsigned int virq, u32 hwirq)135 unsigned int virq, u32 hwirq)
117{136{
118 struct ti_sci_intr_irq_domain *intr = domain->host_data;137 struct ti_sci_intr_irq_domain *intr = domain->host_data;
138 struct device_node *parent_node;
119 struct irq_fwspec fwspec;139 struct irq_fwspec fwspec;
120 u16 dev_id, irq_index;140 u16 out_irq, p_hwirq;
121 u16 dst_irq;141 int err = 0;
122 int err;
123
124 dev_id = HWIRQ_TO_DEVID(hwirq);
125 irq_index = HWIRQ_TO_IRQID(hwirq);
126 142
127 dst_irq = ti_sci_get_free_resource(intr->dst_irq);143 out_irq = ti_sci_get_free_resource(intr->out_irqs);
128 if (dst_irq == TI_SCI_RESOURCE_NULL)144 if (out_irq == TI_SCI_RESOURCE_NULL)
129 return -EINVAL;145 return -EINVAL;
130 146
131 fwspec.fwnode = domain->parent->fwnode;147 p_hwirq = ti_sci_intr_xlate_irq(intr, out_irq);
132 fwspec.param_count = 3;148 if (p_hwirq < 0)
133 fwspec.param[0] = 0; /* SPI */149 goto err_irqs;
134 fwspec.param[1] = dst_irq - 32; /* SPI offset */150
135 fwspec.param[2] = intr->type;151 parent_node = of_irq_find_parent(dev_of_node(intr->dev));
152 fwspec.fwnode = of_node_to_fwnode(parent_node);
153
154 if (of_device_is_compatible(parent_node, "arm,gic-v3")) {
155 /* Parent is GIC */
156 fwspec.param_count = 3;
157 fwspec.param[0] = 0; /* SPI */
158 fwspec.param[1] = p_hwirq - 32; /* SPI offset */
159 fwspec.param[2] = intr->type;
160 } else {
161 /* Parent is Interrupt Router */
162 fwspec.param_count = 1;
163 fwspec.param[0] = p_hwirq;
164 }
136 165
137 err = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);166 err = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
138 if (err)167 if (err)
139 goto err_irqs;168 goto err_irqs;
140 169
141 err = intr->sci->ops.rm_irq_ops.set_irq(intr->sci, dev_id, irq_index,170 err = intr->sci->ops.rm_irq_ops.set_irq(intr->sci,
142 intr->dst_id, dst_irq);171 intr->ti_sci_id, hwirq,
172 intr->ti_sci_id, out_irq);
143 if (err)173 if (err)
144 goto err_msg;174 goto err_msg;
145 175
146 return 0;176 return p_hwirq;
147 177
148err_msg:178err_msg:
149 irq_domain_free_irqs_parent(domain, virq, 1);179 irq_domain_free_irqs_parent(domain, virq, 1);
150err_irqs:180err_irqs:
151 ti_sci_release_resource(intr->dst_irq, dst_irq);181 ti_sci_release_resource(intr->out_irqs, out_irq);
152 return err;182 return err;
153}183}
154 184
@@ -168,18 +198,19 @@ static int ti_sci_intr_irq_domain_alloc(struct irq_domain *domain, · 13 unmodified lines
168 struct irq_fwspec *fwspec = data;198 struct irq_fwspec *fwspec = data;
169 unsigned long hwirq;199 unsigned long hwirq;
170 unsigned int flags;200 unsigned int flags;
171 int err;201 int err, p_hwirq;
172 202
173 err = ti_sci_intr_irq_domain_translate(domain, fwspec, &hwirq, &flags);203 err = ti_sci_intr_irq_domain_translate(domain, fwspec, &hwirq, &flags);
174 if (err)204 if (err)
175 return err;205 return err;
176 206
177 err = ti_sci_intr_alloc_gic_irq(domain, virq, hwirq);207 p_hwirq = ti_sci_intr_alloc_parent_irq(domain, virq, hwirq);
178 if (err)208 if (p_hwirq < 0)
179 return err;209 return p_hwirq;
180 210
181 irq_domain_set_hwirq_and_chip(domain, virq, hwirq,211 irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
182 &ti_sci_intr_irq_chip, NULL);212 &ti_sci_intr_irq_chip,
213 (void *)(uintptr_t)p_hwirq);
183 214
184 return 0;215 return 0;
185}216}
@@ -214,6 +245,7 @@ static int ti_sci_intr_irq_domain_probe(struct platform_device *pdev) · 28 unmodified lines
214 if (!intr)245 if (!intr)
215 return -ENOMEM;246 return -ENOMEM;
216 247
248 intr->dev = dev;
217 ret = of_property_read_u32(dev_of_node(dev), "ti,intr-trigger-type",249 ret = of_property_read_u32(dev_of_node(dev), "ti,intr-trigger-type",
218 &intr->type);250 &intr->type);
219 if (ret) {251 if (ret) {
@@ -230,19 +262,19 @@ static int ti_sci_intr_irq_domain_probe(struct platform_device *pdev) · 10 unmodified lines
230 return ret;262 return ret;
231 }263 }
232 264
233 ret = of_property_read_u32(dev_of_node(dev), "ti,sci-dst-id",265 ret = of_property_read_u32(dev_of_node(dev), "ti,sci-dev-id",
234 &intr->dst_id);266 &intr->ti_sci_id);
235 if (ret) {267 if (ret) {
236 dev_err(dev, "missing 'ti,sci-dst-id' property\n");268 dev_err(dev, "missing 'ti,sci-dev-id' property\n");
237 return -EINVAL;269 return -EINVAL;
238 }270 }
239 271
240 intr->dst_irq = devm_ti_sci_get_of_resource(intr->sci, dev,272 intr->out_irqs = devm_ti_sci_get_resource(intr->sci, dev,
241 intr->dst_id,273 intr->ti_sci_id,
242 "ti,sci-rm-range-girq");274 TI_SCI_RESASG_SUBTYPE_IR_OUTPUT);
243 if (IS_ERR(intr->dst_irq)) {275 if (IS_ERR(intr->out_irqs)) {
244 dev_err(dev, "Destination irq resource allocation failed\n");276 dev_err(dev, "Destination irq resource allocation failed\n");
245 return PTR_ERR(intr->dst_irq);277 return PTR_ERR(intr->out_irqs);
246 }278 }
247 279
248 domain = irq_domain_add_hierarchy(parent_domain, 0, 0, dev_of_node(dev),280 domain = irq_domain_add_hierarchy(parent_domain, 0, 0, dev_of_node(dev),
@@ -252,6 +284,8 @@ static int ti_sci_intr_irq_domain_probe(struct platform_device *pdev) · 3 unmodified lines
252 return -ENOMEM;284 return -ENOMEM;
253 }285 }
254 286
287 dev_info(dev, "Interrupt Router %d domain created\n", intr->ti_sci_id);
288
255 return 0;289 return 0;
256}290}
257 291
drivers/irqchip/irq-vic.c+1−1
@@ -455,7 +455,7 @@ static void __init __vic_init(void __iomem *base, int parent_irq, int irq_start, · 454 unmodified lines
455 return;455 return;
456 default:456 default:
457 printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n");457 printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n");
458 /* fall through */458 fallthrough;
459 case AMBA_VENDOR_ARM:459 case AMBA_VENDOR_ARM:
460 break;460 break;
461 }461 }
drivers/irqchip/irqchip.c+1−1
@@ -52,7 +52,7 @@ int platform_irqchip_probe(struct platform_device *pdev) · 51 unmodified lines
52 * interrupt controller. The actual initialization callback of this52 * interrupt controller. The actual initialization callback of this
53 * interrupt controller can check for specific domains as necessary.53 * interrupt controller can check for specific domains as necessary.
54 */54 */
55 if (par_np && !irq_find_matching_host(np, DOMAIN_BUS_ANY))55 if (par_np && !irq_find_matching_host(par_np, DOMAIN_BUS_ANY))
56 return -EPROBE_DEFER;56 return -EPROBE_DEFER;
57 57
58 return irq_init_cb(np, par_np);58 return irq_init_cb(np, par_np);
drivers/irqchip/qcom-pdc.c+1−7
@@ -11,11 +11,9 @@ · 10 unmodified lines
11#include <linux/irqdomain.h>11#include <linux/irqdomain.h>
12#include <linux/io.h>12#include <linux/io.h>
13#include <linux/kernel.h>13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/of.h>14#include <linux/of.h>
16#include <linux/of_address.h>15#include <linux/of_address.h>
17#include <linux/of_device.h>16#include <linux/of_device.h>
18#include <linux/of_irq.h>
19#include <linux/soc/qcom/irq.h>17#include <linux/soc/qcom/irq.h>
20#include <linux/spinlock.h>18#include <linux/spinlock.h>
21#include <linux/slab.h>19#include <linux/slab.h>
@@ -432,8 +430,4 @@ fail: · 410 unmodified lines
432 return ret;430 return ret;
433}431}
434 432
435IRQCHIP_PLATFORM_DRIVER_BEGIN(qcom_pdc)433IRQCHIP_DECLARE(qcom_pdc, "qcom,pdc", qcom_pdc_init);
436IRQCHIP_MATCH("qcom,pdc", qcom_pdc_init)
437IRQCHIP_PLATFORM_DRIVER_END(qcom_pdc)
438MODULE_DESCRIPTION("Qualcomm Technologies, Inc. Power Domain Controller");
439MODULE_LICENSE("GPL v2");
drivers/isdn/hardware/mISDN/avmfritz.c+1−1
@@ -348,7 +348,7 @@ modehdlc(struct bchannel *bch, int protocol) · 347 unmodified lines
348 switch (protocol) {348 switch (protocol) {
349 case -1: /* used for init */349 case -1: /* used for init */
350 bch->state = -1;350 bch->state = -1;
351 /* fall through */351 fallthrough;
352 case ISDN_P_NONE:352 case ISDN_P_NONE:
353 if (bch->state == ISDN_P_NONE)353 if (bch->state == ISDN_P_NONE)
354 break;354 break;
drivers/isdn/hardware/mISDN/hfc_multi_8xx.h+0−1
@@ -121,7 +121,6 @@ setup_embedded(struct hfc_multi *hc, struct hm_map *m) · 120 unmodified lines
121 case HFC_IO_MODE_EMBSD:121 case HFC_IO_MODE_EMBSD:
122 test_and_set_bit(HFC_CHIP_EMBSD, &hc->chip);122 test_and_set_bit(HFC_CHIP_EMBSD, &hc->chip);
123 hc->slots = 128; /* required */123 hc->slots = 128; /* required */
124 /* fall through */
125 hc->HFC_outb = HFC_outb_embsd;124 hc->HFC_outb = HFC_outb_embsd;
126 hc->HFC_inb = HFC_inb_embsd;125 hc->HFC_inb = HFC_inb_embsd;
127 hc->HFC_inw = HFC_inw_embsd;126 hc->HFC_inw = HFC_inw_embsd;
drivers/isdn/hardware/mISDN/hfcpci.c+1−1
@@ -1280,7 +1280,7 @@ mode_hfcpci(struct bchannel *bch, int bc, int protocol) · 1279 unmodified lines
1280 case (-1): /* used for init */1280 case (-1): /* used for init */
1281 bch->state = -1;1281 bch->state = -1;
1282 bch->nr = bc;1282 bch->nr = bc;
1283 /* fall through */1283 fallthrough;
1284 case (ISDN_P_NONE):1284 case (ISDN_P_NONE):
1285 if (bch->state == ISDN_P_NONE)1285 if (bch->state == ISDN_P_NONE)
1286 return 0;1286 return 0;
drivers/isdn/hardware/mISDN/hfcsusb.c+1−1
@@ -695,7 +695,7 @@ hfcsusb_setup_bch(struct bchannel *bch, int protocol) · 694 unmodified lines
695 switch (protocol) {695 switch (protocol) {
696 case (-1): /* used for init */696 case (-1): /* used for init */
697 bch->state = -1;697 bch->state = -1;
698 /* fall through */698 fallthrough;
699 case (ISDN_P_NONE):699 case (ISDN_P_NONE):
700 if (bch->state == ISDN_P_NONE)700 if (bch->state == ISDN_P_NONE)
701 return 0; /* already in idle state */701 return 0; /* already in idle state */
drivers/isdn/hardware/mISDN/isdnhdlc.c+1−1
@@ -397,7 +397,7 @@ int isdnhdlc_encode(struct isdnhdlc_vars *hdlc, const u8 *src, u16 slen, · 396 unmodified lines
397 dsize--;397 dsize--;
398 break;398 break;
399 }399 }
400 /* fall through */400 fallthrough;
401 case HDLC_SENDFLAG_ONE:401 case HDLC_SENDFLAG_ONE:
402 if (hdlc->bit_shift == 8) {402 if (hdlc->bit_shift == 8) {
403 hdlc->cbin = hdlc->ffvalue >>403 hdlc->cbin = hdlc->ffvalue >>
drivers/isdn/hardware/mISDN/mISDNinfineon.c+1−1
@@ -875,7 +875,7 @@ release_card(struct inf_hw *card) { · 874 unmodified lines
875 release_card(card->sc[i]);875 release_card(card->sc[i]);
876 card->sc[i] = NULL;876 card->sc[i] = NULL;
877 }877 }
878 /* fall through */878 fallthrough;
879 default:879 default:
880 pci_disable_device(card->pdev);880 pci_disable_device(card->pdev);
881 pci_set_drvdata(card->pdev, NULL);881 pci_set_drvdata(card->pdev, NULL);
drivers/isdn/hardware/mISDN/mISDNisar.c+4−4
@@ -957,7 +957,7 @@ isar_pump_statev_fax(struct isar_ch *ch, u8 devt) { · 956 unmodified lines
957 break;957 break;
958 case PCTRL_CMD_FTM:958 case PCTRL_CMD_FTM:
959 p1 = 2;959 p1 = 2;
960 /* fall through */960 fallthrough;
961 case PCTRL_CMD_FTH:961 case PCTRL_CMD_FTH:
962 send_mbox(ch->is, dps | ISAR_HIS_PUMPCTRL,962 send_mbox(ch->is, dps | ISAR_HIS_PUMPCTRL,
963 PCTRL_CMD_SILON, 1, &p1);963 PCTRL_CMD_SILON, 1, &p1);
@@ -1163,7 +1163,7 @@ setup_pump(struct isar_ch *ch) { · 199 unmodified lines
1163 send_mbox(ch->is, dps | ISAR_HIS_PUMPCFG,1163 send_mbox(ch->is, dps | ISAR_HIS_PUMPCFG,
1164 PMOD_DTMF, 1, param);1164 PMOD_DTMF, 1, param);
1165 }1165 }
1166 /* fall through */1166 fallthrough;
1167 case ISDN_P_B_MODEM_ASYNC:1167 case ISDN_P_B_MODEM_ASYNC:
1168 ctrl = PMOD_DATAMODEM;1168 ctrl = PMOD_DATAMODEM;
1169 if (test_bit(FLG_ORIGIN, &ch->bch.Flags)) {1169 if (test_bit(FLG_ORIGIN, &ch->bch.Flags)) {
@@ -1255,7 +1255,7 @@ setup_iom2(struct isar_ch *ch) { · 85 unmodified lines
1255 case ISDN_P_B_MODEM_ASYNC:1255 case ISDN_P_B_MODEM_ASYNC:
1256 case ISDN_P_B_T30_FAX:1256 case ISDN_P_B_T30_FAX:
1257 cmsb |= IOM_CTRL_RCV;1257 cmsb |= IOM_CTRL_RCV;
1258 /* fall through */1258 fallthrough;
1259 case ISDN_P_B_L2DTMF:1259 case ISDN_P_B_L2DTMF:
1260 if (test_bit(FLG_DTMFSEND, &ch->bch.Flags))1260 if (test_bit(FLG_DTMFSEND, &ch->bch.Flags))
1261 cmsb |= IOM_CTRL_RCV;1261 cmsb |= IOM_CTRL_RCV;
@@ -1548,7 +1548,7 @@ isar_l2l1(struct mISDNchannel *ch, struct sk_buff *skb) · 286 unmodified lines
1548 ich->is->name, hh->id);1548 ich->is->name, hh->id);
1549 ret = -EINVAL;1549 ret = -EINVAL;
1550 }1550 }
1551 /* fall through */1551 fallthrough;
1552 default:1552 default:
1553 pr_info("%s: %s unknown prim(%x,%x)\n",1553 pr_info("%s: %s unknown prim(%x,%x)\n",
1554 ich->is->name, __func__, hh->prim, hh->id);1554 ich->is->name, __func__, hh->prim, hh->id);
drivers/isdn/mISDN/stack.c+1−1
@@ -528,7 +528,7 @@ create_l2entity(struct mISDNdevice *dev, struct mISDNchannel *ch, · 527 unmodified lines
528 rq.protocol = ISDN_P_NT_S0;528 rq.protocol = ISDN_P_NT_S0;
529 if (dev->Dprotocols & (1 << ISDN_P_NT_E1))529 if (dev->Dprotocols & (1 << ISDN_P_NT_E1))
530 rq.protocol = ISDN_P_NT_E1;530 rq.protocol = ISDN_P_NT_E1;
531 /* fall through */531 fallthrough;
532 case ISDN_P_LAPD_TE:532 case ISDN_P_LAPD_TE:
533 ch->recv = mISDN_queue_message;533 ch->recv = mISDN_queue_message;
534 ch->peer = &dev->D.st->own;534 ch->peer = &dev->D.st->own;
drivers/lightnvm/pblk-core.c+1−1
@@ -301,7 +301,7 @@ void pblk_free_rqd(struct pblk *pblk, struct nvm_rq *rqd, int type) · 300 unmodified lines
301 switch (type) {301 switch (type) {
302 case PBLK_WRITE:302 case PBLK_WRITE:
303 kfree(((struct pblk_c_ctx *)nvm_rq_to_pdu(rqd))->lun_bitmap);303 kfree(((struct pblk_c_ctx *)nvm_rq_to_pdu(rqd))->lun_bitmap);
304 /* fall through */304 fallthrough;
305 case PBLK_WRITE_INT:305 case PBLK_WRITE_INT:
306 pool = &pblk->w_rq_pool;306 pool = &pblk->w_rq_pool;
307 break;307 break;
drivers/macintosh/adbhid.c+1−1
@@ -881,7 +881,7 @@ adbhid_input_register(int id, int default_id, int original_handler_id, · 880 unmodified lines
881 }881 }
882 if (hid->name[0])882 if (hid->name[0])
883 break;883 break;
884 /* else fall through */884 fallthrough;
885 885
886 default:886 default:
887 pr_info("Trying to register unknown ADB device to input layer.\n");887 pr_info("Trying to register unknown ADB device to input layer.\n");
drivers/macintosh/smu.c+1−1
@@ -852,7 +852,7 @@ int smu_queue_i2c(struct smu_i2c_cmd *cmd) · 851 unmodified lines
852 break;852 break;
853 case SMU_I2C_TRANSFER_COMBINED:853 case SMU_I2C_TRANSFER_COMBINED:
854 cmd->info.devaddr &= 0xfe;854 cmd->info.devaddr &= 0xfe;
855 /* fall through */855 fallthrough;
856 case SMU_I2C_TRANSFER_STDSUB:856 case SMU_I2C_TRANSFER_STDSUB:
857 if (cmd->info.sublen > 3)857 if (cmd->info.sublen > 3)
858 return -EINVAL;858 return -EINVAL;
drivers/md/bcache/journal.c+1−1
@@ -608,7 +608,7 @@ static void do_journal_discard(struct cache *ca) · 607 unmodified lines
608 ca->sb.njournal_buckets;608 ca->sb.njournal_buckets;
609 609
610 atomic_set(&ja->discard_in_flight, DISCARD_READY);610 atomic_set(&ja->discard_in_flight, DISCARD_READY);
611 /* fallthrough */611 fallthrough;
612 612
613 case DISCARD_READY:613 case DISCARD_READY:
614 if (ja->discard_idx == ja->last_idx)614 if (ja->discard_idx == ja->last_idx)
drivers/md/bcache/util.c+7−7
@@ -33,27 +33,27 @@ int bch_ ## name ## _h(const char *cp, type *res) \ · 32 unmodified lines
33 case 'y': \33 case 'y': \
34 case 'z': \34 case 'z': \
35 u++; \35 u++; \
36 /* fall through */ \36 fallthrough; \
37 case 'e': \37 case 'e': \
38 u++; \38 u++; \
39 /* fall through */ \39 fallthrough; \
40 case 'p': \40 case 'p': \
41 u++; \41 u++; \
42 /* fall through */ \42 fallthrough; \
43 case 't': \43 case 't': \
44 u++; \44 u++; \
45 /* fall through */ \45 fallthrough; \
46 case 'g': \46 case 'g': \
47 u++; \47 u++; \
48 /* fall through */ \48 fallthrough; \
49 case 'm': \49 case 'm': \
50 u++; \50 u++; \
51 /* fall through */ \51 fallthrough; \
52 case 'k': \52 case 'k': \
53 u++; \53 u++; \
54 if (e++ == cp) \54 if (e++ == cp) \
55 return -EINVAL; \55 return -EINVAL; \
56 /* fall through */ \56 fallthrough; \
57 case '\n': \57 case '\n': \
58 case '\0': \58 case '\0': \
59 if (*e == '\n') \59 if (*e == '\n') \
drivers/md/dm-cache-metadata.c+6−2
@@ -537,12 +537,16 @@ static int __create_persistent_data_objects(struct dm_cache_metadata *cmd, · 536 unmodified lines
537 CACHE_MAX_CONCURRENT_LOCKS);537 CACHE_MAX_CONCURRENT_LOCKS);
538 if (IS_ERR(cmd->bm)) {538 if (IS_ERR(cmd->bm)) {
539 DMERR("could not create block manager");539 DMERR("could not create block manager");
540 return PTR_ERR(cmd->bm);540 r = PTR_ERR(cmd->bm);
541 cmd->bm = NULL;
542 return r;
541 }543 }
542 544
543 r = __open_or_format_metadata(cmd, may_format_device);545 r = __open_or_format_metadata(cmd, may_format_device);
544 if (r)546 if (r) {
545 dm_block_manager_destroy(cmd->bm);547 dm_block_manager_destroy(cmd->bm);
548 cmd->bm = NULL;
549 }
546 550
547 return r;551 return r;
548}552}
drivers/md/dm-crypt.c+3−3
@@ -739,7 +739,7 @@ static int crypt_iv_eboiv_gen(struct crypt_config *cc, u8 *iv, · 738 unmodified lines
739 u8 buf[MAX_CIPHER_BLOCKSIZE] __aligned(__alignof__(__le64));739 u8 buf[MAX_CIPHER_BLOCKSIZE] __aligned(__alignof__(__le64));
740 struct skcipher_request *req;740 struct skcipher_request *req;
741 struct scatterlist src, dst;741 struct scatterlist src, dst;
742 struct crypto_wait wait;742 DECLARE_CRYPTO_WAIT(wait);
743 int err;743 int err;
744 744
745 req = skcipher_request_alloc(any_tfm(cc), GFP_NOIO);745 req = skcipher_request_alloc(any_tfm(cc), GFP_NOIO);
@@ -936,7 +936,7 @@ static int crypt_iv_elephant(struct crypt_config *cc, struct dm_crypt_request *d · 190 unmodified lines
936 u8 *es, *ks, *data, *data2, *data_offset;936 u8 *es, *ks, *data, *data2, *data_offset;
937 struct skcipher_request *req;937 struct skcipher_request *req;
938 struct scatterlist *sg, *sg2, src, dst;938 struct scatterlist *sg, *sg2, src, dst;
939 struct crypto_wait wait;939 DECLARE_CRYPTO_WAIT(wait);
940 int i, r;940 int i, r;
941 941
942 req = skcipher_request_alloc(elephant->tfm, GFP_NOIO);942 req = skcipher_request_alloc(elephant->tfm, GFP_NOIO);
@@ -1552,7 +1552,7 @@ static blk_status_t crypt_convert(struct crypt_config *cc, · 609 unmodified lines
1552 case -EBUSY:1552 case -EBUSY:
1553 wait_for_completion(&ctx->restart);1553 wait_for_completion(&ctx->restart);
1554 reinit_completion(&ctx->restart);1554 reinit_completion(&ctx->restart);
1555 /* fall through */1555 fallthrough;
1556 /*1556 /*
1557 * The request is queued and processed asynchronously,1557 * The request is queued and processed asynchronously,
1558 * completion function kcryptd_async_done() will be called.1558 * completion function kcryptd_async_done() will be called.
drivers/md/dm-integrity.c+12−0
@@ -2487,6 +2487,7 @@ next_chunk: · 2486 unmodified lines
2487 range.logical_sector = le64_to_cpu(ic->sb->recalc_sector);2487 range.logical_sector = le64_to_cpu(ic->sb->recalc_sector);
2488 if (unlikely(range.logical_sector >= ic->provided_data_sectors)) {2488 if (unlikely(range.logical_sector >= ic->provided_data_sectors)) {
2489 if (ic->mode == 'B') {2489 if (ic->mode == 'B') {
2490 block_bitmap_op(ic, ic->recalc_bitmap, 0, ic->provided_data_sectors, BITMAP_OP_CLEAR);
2490 DEBUG_print("queue_delayed_work: bitmap_flush_work\n");2491 DEBUG_print("queue_delayed_work: bitmap_flush_work\n");
2491 queue_delayed_work(ic->commit_wq, &ic->bitmap_flush_work, 0);2492 queue_delayed_work(ic->commit_wq, &ic->bitmap_flush_work, 0);
2492 }2493 }
@@ -2564,6 +2565,17 @@ next_chunk: · 71 unmodified lines
2564 goto err;2565 goto err;
2565 }2566 }
2566 2567
2568 if (ic->mode == 'B') {
2569 sector_t start, end;
2570 start = (range.logical_sector >>
2571 (ic->sb->log2_sectors_per_block + ic->log2_blocks_per_bitmap_bit)) <<
2572 (ic->sb->log2_sectors_per_block + ic->log2_blocks_per_bitmap_bit);
2573 end = ((range.logical_sector + range.n_sectors) >>
2574 (ic->sb->log2_sectors_per_block + ic->log2_blocks_per_bitmap_bit)) <<
2575 (ic->sb->log2_sectors_per_block + ic->log2_blocks_per_bitmap_bit);
2576 block_bitmap_op(ic, ic->recalc_bitmap, start, end - start, BITMAP_OP_CLEAR);
2577 }
2578
2567advance_and_next:2579advance_and_next:
2568 cond_resched();2580 cond_resched();
2569 2581
drivers/md/dm-mpath.c+16−8
@@ -1287,17 +1287,25 @@ static void multipath_wait_for_pg_init_completion(struct multipath *m) · 1286 unmodified lines
1287static void flush_multipath_work(struct multipath *m)1287static void flush_multipath_work(struct multipath *m)
1288{1288{
1289 if (m->hw_handler_name) {1289 if (m->hw_handler_name) {
1290 set_bit(MPATHF_PG_INIT_DISABLED, &m->flags);1290 unsigned long flags;
1291 smp_mb__after_atomic();1291
1292 if (!atomic_read(&m->pg_init_in_progress))
1293 goto skip;
1294
1295 spin_lock_irqsave(&m->lock, flags);
1296 if (atomic_read(&m->pg_init_in_progress) &&
1297 !test_and_set_bit(MPATHF_PG_INIT_DISABLED, &m->flags)) {
1298 spin_unlock_irqrestore(&m->lock, flags);
1292 1299
1293 if (atomic_read(&m->pg_init_in_progress))
1294 flush_workqueue(kmpath_handlerd);1300 flush_workqueue(kmpath_handlerd);
1295 multipath_wait_for_pg_init_completion(m);1301 multipath_wait_for_pg_init_completion(m);
1296 1302
1297 clear_bit(MPATHF_PG_INIT_DISABLED, &m->flags);1303 spin_lock_irqsave(&m->lock, flags);
1298 smp_mb__after_atomic();1304 clear_bit(MPATHF_PG_INIT_DISABLED, &m->flags);
1305 }
1306 spin_unlock_irqrestore(&m->lock, flags);
1299 }1307 }
1300 1308skip:
1301 if (m->queue_mode == DM_TYPE_BIO_BASED)1309 if (m->queue_mode == DM_TYPE_BIO_BASED)
1302 flush_work(&m->process_queued_bios);1310 flush_work(&m->process_queued_bios);
1303 flush_work(&m->trigger_event);1311 flush_work(&m->trigger_event);
@@ -1554,7 +1562,7 @@ static void pg_init_done(void *data, int errors) · 250 unmodified lines
1554 case SCSI_DH_RETRY:1562 case SCSI_DH_RETRY:
1555 /* Wait before retrying. */1563 /* Wait before retrying. */
1556 delay_retry = true;1564 delay_retry = true;
1557 /* fall through */1565 fallthrough;
1558 case SCSI_DH_IMM_RETRY:1566 case SCSI_DH_IMM_RETRY:
1559 case SCSI_DH_RES_TEMP_UNAVAIL:1567 case SCSI_DH_RES_TEMP_UNAVAIL:
1560 if (pg_init_limit_reached(m, pgpath))1568 if (pg_init_limit_reached(m, pgpath))
drivers/md/dm-thin-metadata.c+7−3
@@ -739,12 +739,16 @@ static int __create_persistent_data_objects(struct dm_pool_metadata *pmd, bool f · 738 unmodified lines
739 THIN_MAX_CONCURRENT_LOCKS);739 THIN_MAX_CONCURRENT_LOCKS);
740 if (IS_ERR(pmd->bm)) {740 if (IS_ERR(pmd->bm)) {
741 DMERR("could not create block manager");741 DMERR("could not create block manager");
742 return PTR_ERR(pmd->bm);742 r = PTR_ERR(pmd->bm);
743 pmd->bm = NULL;
744 return r;
743 }745 }
744 746
745 r = __open_or_format_metadata(pmd, format_device);747 r = __open_or_format_metadata(pmd, format_device);
746 if (r)748 if (r) {
747 dm_block_manager_destroy(pmd->bm);749 dm_block_manager_destroy(pmd->bm);
750 pmd->bm = NULL;
751 }
748 752
749 return r;753 return r;
750}754}
@@ -954,7 +958,7 @@ int dm_pool_metadata_close(struct dm_pool_metadata *pmd) · 203 unmodified lines
954 }958 }
955 959
956 pmd_write_lock_in_core(pmd);960 pmd_write_lock_in_core(pmd);
957 if (!dm_bm_is_read_only(pmd->bm) && !pmd->fail_io) {961 if (!pmd->fail_io && !dm_bm_is_read_only(pmd->bm)) {
958 r = __commit_transaction(pmd);962 r = __commit_transaction(pmd);
959 if (r < 0)963 if (r < 0)
960 DMWARN("%s: __commit_transaction() failed, error = %d",964 DMWARN("%s: __commit_transaction() failed, error = %d",
drivers/md/dm-writecache.c+10−2
@@ -231,6 +231,7 @@ static int persistent_memory_claim(struct dm_writecache *wc) · 230 unmodified lines
231 pfn_t pfn;231 pfn_t pfn;
232 int id;232 int id;
233 struct page **pages;233 struct page **pages;
234 sector_t offset;
234 235
235 wc->memory_vmapped = false;236 wc->memory_vmapped = false;
236 237
@@ -245,9 +246,16 @@ static int persistent_memory_claim(struct dm_writecache *wc) · 8 unmodified lines
245 goto err1;246 goto err1;
246 }247 }
247 248
249 offset = get_start_sect(wc->ssd_dev->bdev);
250 if (offset & (PAGE_SIZE / 512 - 1)) {
251 r = -EINVAL;
252 goto err1;
253 }
254 offset >>= PAGE_SHIFT - 9;
255
248 id = dax_read_lock();256 id = dax_read_lock();
249 257
250 da = dax_direct_access(wc->ssd_dev->dax_dev, 0, p, &wc->memory_map, &pfn);258 da = dax_direct_access(wc->ssd_dev->dax_dev, offset, p, &wc->memory_map, &pfn);
251 if (da < 0) {259 if (da < 0) {
252 wc->memory_map = NULL;260 wc->memory_map = NULL;
253 r = da;261 r = da;
@@ -269,7 +277,7 @@ static int persistent_memory_claim(struct dm_writecache *wc) · 15 unmodified lines
269 i = 0;277 i = 0;
270 do {278 do {
271 long daa;279 long daa;
272 daa = dax_direct_access(wc->ssd_dev->dax_dev, i, p - i,280 daa = dax_direct_access(wc->ssd_dev->dax_dev, offset + i, p - i,
273 NULL, &pfn);281 NULL, &pfn);
274 if (daa <= 0) {282 if (daa <= 0) {
275 r = daa ? daa : -EINVAL;283 r = daa ? daa : -EINVAL;
drivers/md/dm.c+1−1
@@ -1021,7 +1021,7 @@ static void clone_endio(struct bio *bio) · 1020 unmodified lines
1021 switch (r) {1021 switch (r) {
1022 case DM_ENDIO_REQUEUE:1022 case DM_ENDIO_REQUEUE:
1023 error = BLK_STS_DM_REQUEUE;1023 error = BLK_STS_DM_REQUEUE;
1024 /*FALLTHRU*/1024 fallthrough;
1025 case DM_ENDIO_DONE:1025 case DM_ENDIO_DONE:
1026 break;1026 break;
1027 case DM_ENDIO_INCOMPLETE:1027 case DM_ENDIO_INCOMPLETE:
drivers/md/md-autodetect.c+2−2
@@ -102,10 +102,10 @@ static int __init md_setup(char *str) · 101 unmodified lines
102 pername = "raid0";102 pername = "raid0";
103 break;103 break;
104 }104 }
105 /* FALL THROUGH */105 fallthrough;
106 case 1: /* the first device is numeric */106 case 1: /* the first device is numeric */
107 str = str1;107 str = str1;
108 /* FALL THROUGH */108 fallthrough;
109 case 0:109 case 0:
110 md_setup_args[ent].level = LEVEL_NONE;110 md_setup_args[ent].level = LEVEL_NONE;
111 pername="super-block";111 pername="super-block";
drivers/md/md-bitmap.c+1−1
@@ -1433,7 +1433,7 @@ int md_bitmap_startwrite(struct bitmap *bitmap, sector_t offset, unsigned long s · 1432 unmodified lines
1433 case 0:1433 case 0:
1434 md_bitmap_file_set_bit(bitmap, offset);1434 md_bitmap_file_set_bit(bitmap, offset);
1435 md_bitmap_count_page(&bitmap->counts, offset, 1);1435 md_bitmap_count_page(&bitmap->counts, offset, 1);
1436 /* fall through */1436 fallthrough;
1437 case 1:1437 case 1:
1438 *bmc = 2;1438 *bmc = 2;
1439 }1439 }
drivers/md/persistent-data/dm-block-manager.c+8−6
@@ -493,7 +493,7 @@ int dm_bm_write_lock(struct dm_block_manager *bm, · 492 unmodified lines
493 void *p;493 void *p;
494 int r;494 int r;
495 495
496 if (bm->read_only)496 if (dm_bm_is_read_only(bm))
497 return -EPERM;497 return -EPERM;
498 498
499 p = dm_bufio_read(bm->bufio, b, (struct dm_buffer **) result);499 p = dm_bufio_read(bm->bufio, b, (struct dm_buffer **) result);
@@ -562,7 +562,7 @@ int dm_bm_write_lock_zero(struct dm_block_manager *bm, · 62 unmodified lines
562 struct buffer_aux *aux;562 struct buffer_aux *aux;
563 void *p;563 void *p;
564 564
565 if (bm->read_only)565 if (dm_bm_is_read_only(bm))
566 return -EPERM;566 return -EPERM;
567 567
568 p = dm_bufio_new(bm->bufio, b, (struct dm_buffer **) result);568 p = dm_bufio_new(bm->bufio, b, (struct dm_buffer **) result);
@@ -602,7 +602,7 @@ EXPORT_SYMBOL_GPL(dm_bm_unlock); · 33 unmodified lines
602 602
603int dm_bm_flush(struct dm_block_manager *bm)603int dm_bm_flush(struct dm_block_manager *bm)
604{604{
605 if (bm->read_only)605 if (dm_bm_is_read_only(bm))
606 return -EPERM;606 return -EPERM;
607 607
608 return dm_bufio_write_dirty_buffers(bm->bufio);608 return dm_bufio_write_dirty_buffers(bm->bufio);
@@ -616,19 +616,21 @@ void dm_bm_prefetch(struct dm_block_manager *bm, dm_block_t b) · 7 unmodified lines
616 616
617bool dm_bm_is_read_only(struct dm_block_manager *bm)617bool dm_bm_is_read_only(struct dm_block_manager *bm)
618{618{
619 return bm->read_only;619 return (bm ? bm->read_only : true);
620}620}
621EXPORT_SYMBOL_GPL(dm_bm_is_read_only);621EXPORT_SYMBOL_GPL(dm_bm_is_read_only);
622 622
623void dm_bm_set_read_only(struct dm_block_manager *bm)623void dm_bm_set_read_only(struct dm_block_manager *bm)
624{624{
625 bm->read_only = true;625 if (bm)
626 bm->read_only = true;
626}627}
627EXPORT_SYMBOL_GPL(dm_bm_set_read_only);628EXPORT_SYMBOL_GPL(dm_bm_set_read_only);
628 629
629void dm_bm_set_read_write(struct dm_block_manager *bm)630void dm_bm_set_read_write(struct dm_block_manager *bm)
630{631{
631 bm->read_only = false;632 if (bm)
633 bm->read_only = false;
632}634}
633EXPORT_SYMBOL_GPL(dm_bm_set_read_write);635EXPORT_SYMBOL_GPL(dm_bm_set_read_write);
634 636
drivers/md/raid5.c+7−4
@@ -4083,7 +4083,7 @@ static void handle_parity_checks5(struct r5conf *conf, struct stripe_head *sh, · 4082 unmodified lines
4083 break;4083 break;
4084 }4084 }
4085 dev = &sh->dev[s->failed_num[0]];4085 dev = &sh->dev[s->failed_num[0]];
4086 /* fall through */4086 fallthrough;
4087 case check_state_compute_result:4087 case check_state_compute_result:
4088 sh->check_state = check_state_idle;4088 sh->check_state = check_state_idle;
4089 if (!dev)4089 if (!dev)
@@ -4214,7 +4214,7 @@ static void handle_parity_checks6(struct r5conf *conf, struct stripe_head *sh, · 124 unmodified lines
4214 4214
4215 /* we have 2-disk failure */4215 /* we have 2-disk failure */
4216 BUG_ON(s->failed != 2);4216 BUG_ON(s->failed != 2);
4217 /* fall through */4217 fallthrough;
4218 case check_state_compute_result:4218 case check_state_compute_result:
4219 sh->check_state = check_state_idle;4219 sh->check_state = check_state_idle;
4220 4220
@@ -6514,9 +6514,12 @@ raid5_store_stripe_size(struct mddev *mddev, const char *page, size_t len) · 2293 unmodified lines
6514 6514
6515 /*6515 /*
6516 * The value should not be bigger than PAGE_SIZE. It requires to6516 * The value should not be bigger than PAGE_SIZE. It requires to
6517 * be multiple of DEFAULT_STRIPE_SIZE.6517 * be multiple of DEFAULT_STRIPE_SIZE and the value should be power
6518 * of two.
6518 */6519 */
6519 if (new % DEFAULT_STRIPE_SIZE != 0 || new > PAGE_SIZE || new == 0)6520 if (new % DEFAULT_STRIPE_SIZE != 0 ||
6521 new > PAGE_SIZE || new == 0 ||
6522 new != roundup_pow_of_two(new))
6520 return -EINVAL;6523 return -EINVAL;
6521 6524
6522 err = mddev_lock(mddev);6525 err = mddev_lock(mddev);
drivers/media/common/v4l2-tpg/v4l2-tpg-core.c+18−18
@@ -210,7 +210,7 @@ bool tpg_s_fourcc(struct tpg_data *tpg, u32 fourcc) · 209 unmodified lines
210 tpg->vdownsampling[1] = 1;210 tpg->vdownsampling[1] = 1;
211 tpg->hdownsampling[1] = 1;211 tpg->hdownsampling[1] = 1;
212 tpg->planes = 2;212 tpg->planes = 2;
213 /* fall through */213 fallthrough;
214 case V4L2_PIX_FMT_RGB332:214 case V4L2_PIX_FMT_RGB332:
215 case V4L2_PIX_FMT_RGB565:215 case V4L2_PIX_FMT_RGB565:
216 case V4L2_PIX_FMT_RGB565X:216 case V4L2_PIX_FMT_RGB565X:
@@ -271,7 +271,7 @@ bool tpg_s_fourcc(struct tpg_data *tpg, u32 fourcc) · 54 unmodified lines
271 case V4L2_PIX_FMT_YUV420M:271 case V4L2_PIX_FMT_YUV420M:
272 case V4L2_PIX_FMT_YVU420M:272 case V4L2_PIX_FMT_YVU420M:
273 tpg->buffers = 3;273 tpg->buffers = 3;
274 /* fall through */274 fallthrough;
275 case V4L2_PIX_FMT_YUV420:275 case V4L2_PIX_FMT_YUV420:
276 case V4L2_PIX_FMT_YVU420:276 case V4L2_PIX_FMT_YVU420:
277 tpg->vdownsampling[1] = 2;277 tpg->vdownsampling[1] = 2;
@@ -284,7 +284,7 @@ bool tpg_s_fourcc(struct tpg_data *tpg, u32 fourcc) · 6 unmodified lines
284 case V4L2_PIX_FMT_YUV422M:284 case V4L2_PIX_FMT_YUV422M:
285 case V4L2_PIX_FMT_YVU422M:285 case V4L2_PIX_FMT_YVU422M:
286 tpg->buffers = 3;286 tpg->buffers = 3;
287 /* fall through */287 fallthrough;
288 case V4L2_PIX_FMT_YUV422P:288 case V4L2_PIX_FMT_YUV422P:
289 tpg->vdownsampling[1] = 1;289 tpg->vdownsampling[1] = 1;
290 tpg->vdownsampling[2] = 1;290 tpg->vdownsampling[2] = 1;
@@ -296,7 +296,7 @@ bool tpg_s_fourcc(struct tpg_data *tpg, u32 fourcc) · 5 unmodified lines
296 case V4L2_PIX_FMT_NV16M:296 case V4L2_PIX_FMT_NV16M:
297 case V4L2_PIX_FMT_NV61M:297 case V4L2_PIX_FMT_NV61M:
298 tpg->buffers = 2;298 tpg->buffers = 2;
299 /* fall through */299 fallthrough;
300 case V4L2_PIX_FMT_NV16:300 case V4L2_PIX_FMT_NV16:
301 case V4L2_PIX_FMT_NV61:301 case V4L2_PIX_FMT_NV61:
302 tpg->vdownsampling[1] = 1;302 tpg->vdownsampling[1] = 1;
@@ -308,7 +308,7 @@ bool tpg_s_fourcc(struct tpg_data *tpg, u32 fourcc) · 5 unmodified lines
308 case V4L2_PIX_FMT_NV12M:308 case V4L2_PIX_FMT_NV12M:
309 case V4L2_PIX_FMT_NV21M:309 case V4L2_PIX_FMT_NV21M:
310 tpg->buffers = 2;310 tpg->buffers = 2;
311 /* fall through */311 fallthrough;
312 case V4L2_PIX_FMT_NV12:312 case V4L2_PIX_FMT_NV12:
313 case V4L2_PIX_FMT_NV21:313 case V4L2_PIX_FMT_NV21:
314 tpg->vdownsampling[1] = 2;314 tpg->vdownsampling[1] = 2;
@@ -1275,7 +1275,7 @@ static void gen_twopix(struct tpg_data *tpg, · 960 unmodified lines
1275 case V4L2_PIX_FMT_RGB444:1275 case V4L2_PIX_FMT_RGB444:
1276 case V4L2_PIX_FMT_XRGB444:1276 case V4L2_PIX_FMT_XRGB444:
1277 alpha = 0;1277 alpha = 0;
1278 /* fall through */1278 fallthrough;
1279 case V4L2_PIX_FMT_YUV444:1279 case V4L2_PIX_FMT_YUV444:
1280 case V4L2_PIX_FMT_ARGB444:1280 case V4L2_PIX_FMT_ARGB444:
1281 buf[0][offset] = (g_u_s << 4) | b_v;1281 buf[0][offset] = (g_u_s << 4) | b_v;
@@ -1283,21 +1283,21 @@ static void gen_twopix(struct tpg_data *tpg, · 1 unmodified line
1283 break;1283 break;
1284 case V4L2_PIX_FMT_RGBX444:1284 case V4L2_PIX_FMT_RGBX444:
1285 alpha = 0;1285 alpha = 0;
1286 /* fall through */1286 fallthrough;
1287 case V4L2_PIX_FMT_RGBA444:1287 case V4L2_PIX_FMT_RGBA444:
1288 buf[0][offset] = (b_v << 4) | (alpha >> 4);1288 buf[0][offset] = (b_v << 4) | (alpha >> 4);
1289 buf[0][offset + 1] = (r_y_h << 4) | g_u_s;1289 buf[0][offset + 1] = (r_y_h << 4) | g_u_s;
1290 break;1290 break;
1291 case V4L2_PIX_FMT_XBGR444:1291 case V4L2_PIX_FMT_XBGR444:
1292 alpha = 0;1292 alpha = 0;
1293 /* fall through */1293 fallthrough;
1294 case V4L2_PIX_FMT_ABGR444:1294 case V4L2_PIX_FMT_ABGR444:
1295 buf[0][offset] = (g_u_s << 4) | r_y_h;1295 buf[0][offset] = (g_u_s << 4) | r_y_h;
1296 buf[0][offset + 1] = (alpha & 0xf0) | b_v;1296 buf[0][offset + 1] = (alpha & 0xf0) | b_v;
1297 break;1297 break;
1298 case V4L2_PIX_FMT_BGRX444:1298 case V4L2_PIX_FMT_BGRX444:
1299 alpha = 0;1299 alpha = 0;
1300 /* fall through */1300 fallthrough;
1301 case V4L2_PIX_FMT_BGRA444:1301 case V4L2_PIX_FMT_BGRA444:
1302 buf[0][offset] = (r_y_h << 4) | (alpha >> 4);1302 buf[0][offset] = (r_y_h << 4) | (alpha >> 4);
1303 buf[0][offset + 1] = (b_v << 4) | g_u_s;1303 buf[0][offset + 1] = (b_v << 4) | g_u_s;
@@ -1305,7 +1305,7 @@ static void gen_twopix(struct tpg_data *tpg, · 1 unmodified line
1305 case V4L2_PIX_FMT_RGB555:1305 case V4L2_PIX_FMT_RGB555:
1306 case V4L2_PIX_FMT_XRGB555:1306 case V4L2_PIX_FMT_XRGB555:
1307 alpha = 0;1307 alpha = 0;
1308 /* fall through */1308 fallthrough;
1309 case V4L2_PIX_FMT_YUV555:1309 case V4L2_PIX_FMT_YUV555:
1310 case V4L2_PIX_FMT_ARGB555:1310 case V4L2_PIX_FMT_ARGB555:
1311 buf[0][offset] = (g_u_s << 5) | b_v;1311 buf[0][offset] = (g_u_s << 5) | b_v;
@@ -1314,7 +1314,7 @@ static void gen_twopix(struct tpg_data *tpg, · 2 unmodified lines
1314 break;1314 break;
1315 case V4L2_PIX_FMT_RGBX555:1315 case V4L2_PIX_FMT_RGBX555:
1316 alpha = 0;1316 alpha = 0;
1317 /* fall through */1317 fallthrough;
1318 case V4L2_PIX_FMT_RGBA555:1318 case V4L2_PIX_FMT_RGBA555:
1319 buf[0][offset] = (g_u_s << 6) | (b_v << 1) |1319 buf[0][offset] = (g_u_s << 6) | (b_v << 1) |
1320 ((alpha & 0x80) >> 7);1320 ((alpha & 0x80) >> 7);
@@ -1322,7 +1322,7 @@ static void gen_twopix(struct tpg_data *tpg, · 1 unmodified line
1322 break;1322 break;
1323 case V4L2_PIX_FMT_XBGR555:1323 case V4L2_PIX_FMT_XBGR555:
1324 alpha = 0;1324 alpha = 0;
1325 /* fall through */1325 fallthrough;
1326 case V4L2_PIX_FMT_ABGR555:1326 case V4L2_PIX_FMT_ABGR555:
1327 buf[0][offset] = (g_u_s << 5) | r_y_h;1327 buf[0][offset] = (g_u_s << 5) | r_y_h;
1328 buf[0][offset + 1] = (alpha & 0x80) | (b_v << 2)1328 buf[0][offset + 1] = (alpha & 0x80) | (b_v << 2)
@@ -1330,7 +1330,7 @@ static void gen_twopix(struct tpg_data *tpg, · 1 unmodified line
1330 break;1330 break;
1331 case V4L2_PIX_FMT_BGRX555:1331 case V4L2_PIX_FMT_BGRX555:
1332 alpha = 0;1332 alpha = 0;
1333 /* fall through */1333 fallthrough;
1334 case V4L2_PIX_FMT_BGRA555:1334 case V4L2_PIX_FMT_BGRA555:
1335 buf[0][offset] = (g_u_s << 6) | (r_y_h << 1) |1335 buf[0][offset] = (g_u_s << 6) | (r_y_h << 1) |
1336 ((alpha & 0x80) >> 7);1336 ((alpha & 0x80) >> 7);
@@ -1339,7 +1339,7 @@ static void gen_twopix(struct tpg_data *tpg, · 2 unmodified lines
1339 case V4L2_PIX_FMT_RGB555X:1339 case V4L2_PIX_FMT_RGB555X:
1340 case V4L2_PIX_FMT_XRGB555X:1340 case V4L2_PIX_FMT_XRGB555X:
1341 alpha = 0;1341 alpha = 0;
1342 /* fall through */1342 fallthrough;
1343 case V4L2_PIX_FMT_ARGB555X:1343 case V4L2_PIX_FMT_ARGB555X:
1344 buf[0][offset] = (alpha & 0x80) | (r_y_h << 2) | (g_u_s >> 3);1344 buf[0][offset] = (alpha & 0x80) | (r_y_h << 2) | (g_u_s >> 3);
1345 buf[0][offset + 1] = (g_u_s << 5) | b_v;1345 buf[0][offset + 1] = (g_u_s << 5) | b_v;
@@ -1366,7 +1366,7 @@ static void gen_twopix(struct tpg_data *tpg, · 20 unmodified lines
1366 case V4L2_PIX_FMT_HSV32:1366 case V4L2_PIX_FMT_HSV32:
1367 case V4L2_PIX_FMT_XYUV32:1367 case V4L2_PIX_FMT_XYUV32:
1368 alpha = 0;1368 alpha = 0;
1369 /* fall through */1369 fallthrough;
1370 case V4L2_PIX_FMT_YUV32:1370 case V4L2_PIX_FMT_YUV32:
1371 case V4L2_PIX_FMT_ARGB32:1371 case V4L2_PIX_FMT_ARGB32:
1372 case V4L2_PIX_FMT_AYUV32:1372 case V4L2_PIX_FMT_AYUV32:
@@ -1377,7 +1377,7 @@ static void gen_twopix(struct tpg_data *tpg, · 4 unmodified lines
1377 break;1377 break;
1378 case V4L2_PIX_FMT_RGBX32:1378 case V4L2_PIX_FMT_RGBX32:
1379 alpha = 0;1379 alpha = 0;
1380 /* fall through */1380 fallthrough;
1381 case V4L2_PIX_FMT_RGBA32:1381 case V4L2_PIX_FMT_RGBA32:
1382 buf[0][offset] = r_y_h;1382 buf[0][offset] = r_y_h;
1383 buf[0][offset + 1] = g_u_s;1383 buf[0][offset + 1] = g_u_s;
@@ -1388,7 +1388,7 @@ static void gen_twopix(struct tpg_data *tpg, · 4 unmodified lines
1388 case V4L2_PIX_FMT_XBGR32:1388 case V4L2_PIX_FMT_XBGR32:
1389 case V4L2_PIX_FMT_VUYX32:1389 case V4L2_PIX_FMT_VUYX32:
1390 alpha = 0;1390 alpha = 0;
1391 /* fall through */1391 fallthrough;
1392 case V4L2_PIX_FMT_ABGR32:1392 case V4L2_PIX_FMT_ABGR32:
1393 case V4L2_PIX_FMT_VUYA32:1393 case V4L2_PIX_FMT_VUYA32:
1394 buf[0][offset] = b_v;1394 buf[0][offset] = b_v;
@@ -1398,7 +1398,7 @@ static void gen_twopix(struct tpg_data *tpg, · 3 unmodified lines
1398 break;1398 break;
1399 case V4L2_PIX_FMT_BGRX32:1399 case V4L2_PIX_FMT_BGRX32:
1400 alpha = 0;1400 alpha = 0;
1401 /* fall through */1401 fallthrough;
1402 case V4L2_PIX_FMT_BGRA32:1402 case V4L2_PIX_FMT_BGRA32:
1403 buf[0][offset] = alpha;1403 buf[0][offset] = alpha;
1404 buf[0][offset + 1] = b_v;1404 buf[0][offset + 1] = b_v;
drivers/media/dvb-core/dvb_net.c+1−1
@@ -546,7 +546,7 @@ static int dvb_net_ule_new_payload(struct dvb_net_ule_handle *h) · 545 unmodified lines
546 h->priv->ule_sndu_type_1 = 1;546 h->priv->ule_sndu_type_1 = 1;
547 h->ts_remain -= 1;547 h->ts_remain -= 1;
548 h->from_where += 1;548 h->from_where += 1;
549 /* fallthrough */549 fallthrough;
550 case 0:550 case 0:
551 h->new_ts = 1;551 h->new_ts = 1;
552 h->ts += TS_SZ;552 h->ts += TS_SZ;
drivers/media/dvb-frontends/bcm3510.c+1−1
@@ -773,7 +773,7 @@ static int bcm3510_init(struct dvb_frontend* fe) · 772 unmodified lines
773 deb_info("attempting to download firmware\n");773 deb_info("attempting to download firmware\n");
774 if ((ret = bcm3510_init_cold(st)) < 0)774 if ((ret = bcm3510_init_cold(st)) < 0)
775 return ret;775 return ret;
776 /* fall-through */776 fallthrough;
777 case JDEC_EEPROM_LOAD_WAIT:777 case JDEC_EEPROM_LOAD_WAIT:
778 deb_info("firmware is loaded\n");778 deb_info("firmware is loaded\n");
779 bcm3510_check_firmware_version(st);779 bcm3510_check_firmware_version(st);
drivers/media/dvb-frontends/dib0090.c+1−1
@@ -1693,7 +1693,7 @@ static int dib0090_dc_offset_calibration(struct dib0090_state *state, enum front · 1692 unmodified lines
1693 if (state->identity.p1g)1693 if (state->identity.p1g)
1694 state->dc = dc_p1g_table;1694 state->dc = dc_p1g_table;
1695 1695
1696 /* fall through */1696 fallthrough;
1697 case CT_TUNER_STEP_0:1697 case CT_TUNER_STEP_0:
1698 dprintk("Start/continue DC calibration for %s path\n",1698 dprintk("Start/continue DC calibration for %s path\n",
1699 (state->dc->i == 1) ? "I" : "Q");1699 (state->dc->i == 1) ? "I" : "Q");
drivers/media/dvb-frontends/dib3000mb.c+1−1
@@ -224,7 +224,7 @@ static int dib3000mb_set_frontend(struct dvb_frontend *fe, int tuner) · 223 unmodified lines
224 switch (c->hierarchy) {224 switch (c->hierarchy) {
225 case HIERARCHY_NONE:225 case HIERARCHY_NONE:
226 deb_setf("hierarchy: none\n");226 deb_setf("hierarchy: none\n");
227 /* fall through */227 fallthrough;
228 case HIERARCHY_1:228 case HIERARCHY_1:
229 deb_setf("hierarchy: alpha=1\n");229 deb_setf("hierarchy: alpha=1\n");
230 wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_1);230 wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_1);
drivers/media/dvb-frontends/dib7000p.c+1−1
@@ -276,7 +276,7 @@ static int dib7000p_set_power_mode(struct dib7000p_state *state, enum dib7000p_p · 275 unmodified lines
276 if (state->version != SOC7090)276 if (state->version != SOC7090)
277 reg_1280 &= ~((1 << 11));277 reg_1280 &= ~((1 << 11));
278 reg_1280 &= ~(1 << 6);278 reg_1280 &= ~(1 << 6);
279 /* fall-through */279 fallthrough;
280 case DIB7000P_POWER_INTERFACE_ONLY:280 case DIB7000P_POWER_INTERFACE_ONLY:
281 /* just leave power on the control-interfaces: GPIO and (I2C or SDIO) */281 /* just leave power on the control-interfaces: GPIO and (I2C or SDIO) */
282 /* TODO power up either SDIO or I2C */282 /* TODO power up either SDIO or I2C */
drivers/media/dvb-frontends/drx39xyj/drxj.c+56−47
@@ -2306,7 +2306,7 @@ hi_command(struct i2c_device_addr *dev_addr, const struct drxj_hi_cmd *cmd, u16 · 2305 unmodified lines
2306 pr_err("error %d\n", rc);2306 pr_err("error %d\n", rc);
2307 goto rw_error;2307 goto rw_error;
2308 }2308 }
2309 /* fallthrough */2309 fallthrough;
2310 case SIO_HI_RA_RAM_CMD_BRDCTRL:2310 case SIO_HI_RA_RAM_CMD_BRDCTRL:
2311 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_2__A, cmd->param2, 0);2311 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_2__A, cmd->param2, 0);
2312 if (rc != 0) {2312 if (rc != 0) {
@@ -2318,7 +2318,7 @@ hi_command(struct i2c_device_addr *dev_addr, const struct drxj_hi_cmd *cmd, u16 · 5 unmodified lines
2318 pr_err("error %d\n", rc);2318 pr_err("error %d\n", rc);
2319 goto rw_error;2319 goto rw_error;
2320 }2320 }
2321 /* fallthrough */2321 fallthrough;
2322 case SIO_HI_RA_RAM_CMD_NULL:2322 case SIO_HI_RA_RAM_CMD_NULL:
2323 /* No parameters */2323 /* No parameters */
2324 break;2324 break;
@@ -2841,7 +2841,7 @@ ctrl_set_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_o · 516 unmodified lines
2841 /* coef = 188/204 */2841 /* coef = 188/204 */
2842 max_bit_rate =2842 max_bit_rate =
2843 (ext_attr->curr_symbol_rate / 8) * nr_bits * 188;2843 (ext_attr->curr_symbol_rate / 8) * nr_bits * 188;
2844 /* fall-through - as b/c Annex A/C need following settings */2844 fallthrough; /* as b/c Annex A/C need following settings */
2845 case DRX_STANDARD_ITU_B:2845 case DRX_STANDARD_ITU_B:
2846 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_USAGE__A, FEC_OC_FCT_USAGE__PRE, 0);2846 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_USAGE__A, FEC_OC_FCT_USAGE__PRE, 0);
2847 if (rc != 0) {2847 if (rc != 0) {
@@ -3555,8 +3555,8 @@ static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg · 707 unmodified lines
3555 if (!ext_attr->has_smatx)3555 if (!ext_attr->has_smatx)
3556 return -EIO;3556 return -EIO;
3557 switch (uio_cfg->mode) {3557 switch (uio_cfg->mode) {
3558 case DRX_UIO_MODE_FIRMWARE_SMA: /* fall through */3558 case DRX_UIO_MODE_FIRMWARE_SMA:
3559 case DRX_UIO_MODE_FIRMWARE_SAW: /* fall through */3559 case DRX_UIO_MODE_FIRMWARE_SAW:
3560 case DRX_UIO_MODE_READWRITE:3560 case DRX_UIO_MODE_READWRITE:
3561 ext_attr->uio_sma_tx_mode = uio_cfg->mode;3561 ext_attr->uio_sma_tx_mode = uio_cfg->mode;
3562 break;3562 break;
@@ -3579,7 +3579,7 @@ static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg · 16 unmodified lines
3579 if (!ext_attr->has_smarx)3579 if (!ext_attr->has_smarx)
3580 return -EIO;3580 return -EIO;
3581 switch (uio_cfg->mode) {3581 switch (uio_cfg->mode) {
3582 case DRX_UIO_MODE_FIRMWARE0: /* fall through */3582 case DRX_UIO_MODE_FIRMWARE0:
3583 case DRX_UIO_MODE_READWRITE:3583 case DRX_UIO_MODE_READWRITE:
3584 ext_attr->uio_sma_rx_mode = uio_cfg->mode;3584 ext_attr->uio_sma_rx_mode = uio_cfg->mode;
3585 break;3585 break;
@@ -3603,7 +3603,7 @@ static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg · 17 unmodified lines
3603 if (!ext_attr->has_gpio)3603 if (!ext_attr->has_gpio)
3604 return -EIO;3604 return -EIO;
3605 switch (uio_cfg->mode) {3605 switch (uio_cfg->mode) {
3606 case DRX_UIO_MODE_FIRMWARE0: /* fall through */3606 case DRX_UIO_MODE_FIRMWARE0:
3607 case DRX_UIO_MODE_READWRITE:3607 case DRX_UIO_MODE_READWRITE:
3608 ext_attr->uio_gpio_mode = uio_cfg->mode;3608 ext_attr->uio_gpio_mode = uio_cfg->mode;
3609 break;3609 break;
@@ -3639,7 +3639,7 @@ static int ctrl_set_uio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg · 29 unmodified lines
3639 }3639 }
3640 ext_attr->uio_irqn_mode = uio_cfg->mode;3640 ext_attr->uio_irqn_mode = uio_cfg->mode;
3641 break;3641 break;
3642 case DRX_UIO_MODE_FIRMWARE0: /* fall through */3642 case DRX_UIO_MODE_FIRMWARE0:
3643 default:3643 default:
3644 return -EINVAL;3644 return -EINVAL;
3645 break;3645 break;
@@ -4004,31 +4004,36 @@ static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd · 358 unmodified lines
4004 if (rc != 0) {4004 if (rc != 0) {
4005 pr_err("error %d\n", rc);4005 pr_err("error %d\n", rc);
4006 goto rw_error;4006 goto rw_error;
4007 } /* fallthrough */4007 }
4008 fallthrough;
4008 case 4:4009 case 4:
4009 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_3__A, *(cmd->parameter + 3), 0);4010 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_3__A, *(cmd->parameter + 3), 0);
4010 if (rc != 0) {4011 if (rc != 0) {
4011 pr_err("error %d\n", rc);4012 pr_err("error %d\n", rc);
4012 goto rw_error;4013 goto rw_error;
4013 } /* fallthrough */4014 }
4015 fallthrough;
4014 case 3:4016 case 3:
4015 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_2__A, *(cmd->parameter + 2), 0);4017 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_2__A, *(cmd->parameter + 2), 0);
4016 if (rc != 0) {4018 if (rc != 0) {
4017 pr_err("error %d\n", rc);4019 pr_err("error %d\n", rc);
4018 goto rw_error;4020 goto rw_error;
4019 } /* fallthrough */4021 }
4022 fallthrough;
4020 case 2:4023 case 2:
4021 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_1__A, *(cmd->parameter + 1), 0);4024 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_1__A, *(cmd->parameter + 1), 0);
4022 if (rc != 0) {4025 if (rc != 0) {
4023 pr_err("error %d\n", rc);4026 pr_err("error %d\n", rc);
4024 goto rw_error;4027 goto rw_error;
4025 } /* fallthrough */4028 }
4029 fallthrough;
4026 case 1:4030 case 1:
4027 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_0__A, *(cmd->parameter + 0), 0);4031 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_0__A, *(cmd->parameter + 0), 0);
4028 if (rc != 0) {4032 if (rc != 0) {
4029 pr_err("error %d\n", rc);4033 pr_err("error %d\n", rc);
4030 goto rw_error;4034 goto rw_error;
4031 } /* fallthrough */4035 }
4036 fallthrough;
4032 case 0:4037 case 0:
4033 /* do nothing */4038 /* do nothing */
4034 break;4039 break;
@@ -4068,25 +4073,29 @@ static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd · 33 unmodified lines
4068 if (rc != 0) {4073 if (rc != 0) {
4069 pr_err("error %d\n", rc);4074 pr_err("error %d\n", rc);
4070 goto rw_error;4075 goto rw_error;
4071 } /* fallthrough */4076 }
4077 fallthrough;
4072 case 3:4078 case 3:
4073 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_2__A, cmd->result + 2, 0);4079 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_2__A, cmd->result + 2, 0);
4074 if (rc != 0) {4080 if (rc != 0) {
4075 pr_err("error %d\n", rc);4081 pr_err("error %d\n", rc);
4076 goto rw_error;4082 goto rw_error;
4077 } /* fallthrough */4083 }
4084 fallthrough;
4078 case 2:4085 case 2:
4079 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_1__A, cmd->result + 1, 0);4086 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_1__A, cmd->result + 1, 0);
4080 if (rc != 0) {4087 if (rc != 0) {
4081 pr_err("error %d\n", rc);4088 pr_err("error %d\n", rc);
4082 goto rw_error;4089 goto rw_error;
4083 } /* fallthrough */4090 }
4091 fallthrough;
4084 case 1:4092 case 1:
4085 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_0__A, cmd->result + 0, 0);4093 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_0__A, cmd->result + 0, 0);
4086 if (rc != 0) {4094 if (rc != 0) {
4087 pr_err("error %d\n", rc);4095 pr_err("error %d\n", rc);
4088 goto rw_error;4096 goto rw_error;
4089 } /* fallthrough */4097 }
4098 fallthrough;
4090 case 0:4099 case 0:
4091 /* do nothing */4100 /* do nothing */
4092 break;4101 break;
@@ -4791,7 +4800,7 @@ set_frequency(struct drx_demod_instance *demod, · 698 unmodified lines
4791 Sound carrier is already 3Mhz above centre frequency due4800 Sound carrier is already 3Mhz above centre frequency due
4792 to tuner setting so now add an extra shift of 1MHz... */4801 to tuner setting so now add an extra shift of 1MHz... */
4793 fm_frequency_shift = 1000;4802 fm_frequency_shift = 1000;
4794 /*fall through */4803 fallthrough;
4795 case DRX_STANDARD_ITU_B:4804 case DRX_STANDARD_ITU_B:
4796 case DRX_STANDARD_NTSC:4805 case DRX_STANDARD_NTSC:
4797 case DRX_STANDARD_PAL_SECAM_BG:4806 case DRX_STANDARD_PAL_SECAM_BG:
@@ -10475,11 +10484,11 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) · 5677 unmodified lines
10475 (standard == DRX_STANDARD_NTSC)) {10484 (standard == DRX_STANDARD_NTSC)) {
10476 switch (channel->bandwidth) {10485 switch (channel->bandwidth) {
10477 case DRX_BANDWIDTH_6MHZ:10486 case DRX_BANDWIDTH_6MHZ:
10478 case DRX_BANDWIDTH_UNKNOWN: /* fall through */10487 case DRX_BANDWIDTH_UNKNOWN:
10479 channel->bandwidth = DRX_BANDWIDTH_6MHZ;10488 channel->bandwidth = DRX_BANDWIDTH_6MHZ;
10480 break;10489 break;
10481 case DRX_BANDWIDTH_8MHZ: /* fall through */10490 case DRX_BANDWIDTH_8MHZ:
10482 case DRX_BANDWIDTH_7MHZ: /* fall through */10491 case DRX_BANDWIDTH_7MHZ:
10483 default:10492 default:
10484 return -EINVAL;10493 return -EINVAL;
10485 }10494 }
@@ -10511,10 +10520,10 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) · 25 unmodified lines
10511 }10520 }
10512 10521
10513 switch (channel->constellation) {10522 switch (channel->constellation) {
10514 case DRX_CONSTELLATION_QAM16: /* fall through */10523 case DRX_CONSTELLATION_QAM16:
10515 case DRX_CONSTELLATION_QAM32: /* fall through */10524 case DRX_CONSTELLATION_QAM32:
10516 case DRX_CONSTELLATION_QAM64: /* fall through */10525 case DRX_CONSTELLATION_QAM64:
10517 case DRX_CONSTELLATION_QAM128: /* fall through */10526 case DRX_CONSTELLATION_QAM128:
10518 case DRX_CONSTELLATION_QAM256:10527 case DRX_CONSTELLATION_QAM256:
10519 bandwidth_temp = channel->symbolrate * bw_rolloff_factor;10528 bandwidth_temp = channel->symbolrate * bw_rolloff_factor;
10520 bandwidth = bandwidth_temp / 100;10529 bandwidth = bandwidth_temp / 100;
@@ -10628,8 +10637,8 @@ ctrl_set_channel(struct drx_demod_instance *demod, struct drx_channel *channel) · 107 unmodified lines
10628 }10637 }
10629 break;10638 break;
10630#ifndef DRXJ_VSB_ONLY10639#ifndef DRXJ_VSB_ONLY
10631 case DRX_STANDARD_ITU_A: /* fallthrough */10640 case DRX_STANDARD_ITU_A:
10632 case DRX_STANDARD_ITU_B: /* fallthrough */10641 case DRX_STANDARD_ITU_B:
10633 case DRX_STANDARD_ITU_C:10642 case DRX_STANDARD_ITU_C:
10634 rc = set_qam_channel(demod, channel, tuner_freq_offset);10643 rc = set_qam_channel(demod, channel, tuner_freq_offset);
10635 if (rc != 0) {10644 if (rc != 0) {
@@ -10820,7 +10829,7 @@ ctrl_lock_status(struct drx_demod_instance *demod, enum drx_lock_status *lock_st · 184 unmodified lines
10820 SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK;10829 SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK;
10821 break;10830 break;
10822#endif10831#endif
10823 case DRX_STANDARD_UNKNOWN: /* fallthrough */10832 case DRX_STANDARD_UNKNOWN:
10824 default:10833 default:
10825 return -EIO;10834 return -EIO;
10826 }10835 }
@@ -10888,8 +10897,8 @@ ctrl_set_standard(struct drx_demod_instance *demod, enum drx_standard *standard) · 61 unmodified lines
10888 */10897 */
10889 switch (prev_standard) {10898 switch (prev_standard) {
10890#ifndef DRXJ_VSB_ONLY10899#ifndef DRXJ_VSB_ONLY
10891 case DRX_STANDARD_ITU_A: /* fallthrough */10900 case DRX_STANDARD_ITU_A:
10892 case DRX_STANDARD_ITU_B: /* fallthrough */10901 case DRX_STANDARD_ITU_B:
10893 case DRX_STANDARD_ITU_C:10902 case DRX_STANDARD_ITU_C:
10894 rc = power_down_qam(demod, false);10903 rc = power_down_qam(demod, false);
10895 if (rc != 0) {10904 if (rc != 0) {
@@ -10908,7 +10917,7 @@ ctrl_set_standard(struct drx_demod_instance *demod, enum drx_standard *standard) · 12 unmodified lines
10908 case DRX_STANDARD_UNKNOWN:10917 case DRX_STANDARD_UNKNOWN:
10909 /* Do nothing */10918 /* Do nothing */
10910 break;10919 break;
10911 case DRX_STANDARD_AUTO: /* fallthrough */10920 case DRX_STANDARD_AUTO:
10912 default:10921 default:
10913 return -EINVAL;10922 return -EINVAL;
10914 }10923 }
@@ -10921,8 +10930,8 @@ ctrl_set_standard(struct drx_demod_instance *demod, enum drx_standard *standard) · 6 unmodified lines
10921 10930
10922 switch (*standard) {10931 switch (*standard) {
10923#ifndef DRXJ_VSB_ONLY10932#ifndef DRXJ_VSB_ONLY
10924 case DRX_STANDARD_ITU_A: /* fallthrough */10933 case DRX_STANDARD_ITU_A:
10925 case DRX_STANDARD_ITU_B: /* fallthrough */10934 case DRX_STANDARD_ITU_B:
10926 case DRX_STANDARD_ITU_C:10935 case DRX_STANDARD_ITU_C:
10927 do {10936 do {
10928 u16 dummy;10937 u16 dummy;
@@ -11111,12 +11120,12 @@ ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode) · 182 unmodified lines
11111 goto rw_error;11120 goto rw_error;
11112 }11121 }
11113 break;11122 break;
11114 case DRX_STANDARD_PAL_SECAM_BG: /* fallthrough */11123 case DRX_STANDARD_PAL_SECAM_BG:
11115 case DRX_STANDARD_PAL_SECAM_DK: /* fallthrough */11124 case DRX_STANDARD_PAL_SECAM_DK:
11116 case DRX_STANDARD_PAL_SECAM_I: /* fallthrough */11125 case DRX_STANDARD_PAL_SECAM_I:
11117 case DRX_STANDARD_PAL_SECAM_L: /* fallthrough */11126 case DRX_STANDARD_PAL_SECAM_L:
11118 case DRX_STANDARD_PAL_SECAM_LP: /* fallthrough */11127 case DRX_STANDARD_PAL_SECAM_LP:
11119 case DRX_STANDARD_NTSC: /* fallthrough */11128 case DRX_STANDARD_NTSC:
11120 case DRX_STANDARD_FM:11129 case DRX_STANDARD_FM:
11121 rc = power_down_atv(demod, ext_attr->standard, true);11130 rc = power_down_atv(demod, ext_attr->standard, true);
11122 if (rc != 0) {11131 if (rc != 0) {
@@ -11127,7 +11136,7 @@ ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode) · 4 unmodified lines
11127 case DRX_STANDARD_UNKNOWN:11136 case DRX_STANDARD_UNKNOWN:
11128 /* Do nothing */11137 /* Do nothing */
11129 break;11138 break;
11130 case DRX_STANDARD_AUTO: /* fallthrough */11139 case DRX_STANDARD_AUTO:
11131 default:11140 default:
11132 return -EIO;11141 return -EIO;
11133 }11142 }
@@ -11220,8 +11229,8 @@ ctrl_set_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw * · 86 unmodified lines
11220 ext_attr->vsb_pre_saw_cfg = *pre_saw;11229 ext_attr->vsb_pre_saw_cfg = *pre_saw;
11221 break;11230 break;
11222#ifndef DRXJ_VSB_ONLY11231#ifndef DRXJ_VSB_ONLY
11223 case DRX_STANDARD_ITU_A: /* fallthrough */11232 case DRX_STANDARD_ITU_A:
11224 case DRX_STANDARD_ITU_B: /* fallthrough */11233 case DRX_STANDARD_ITU_B:
11225 case DRX_STANDARD_ITU_C:11234 case DRX_STANDARD_ITU_C:
11226 ext_attr->qam_pre_saw_cfg = *pre_saw;11235 ext_attr->qam_pre_saw_cfg = *pre_saw;
11227 break;11236 break;
@@ -11264,10 +11273,10 @@ ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain · 36 unmodified lines
11264 ext_attr = (struct drxj_data *) demod->my_ext_attr;11273 ext_attr = (struct drxj_data *) demod->my_ext_attr;
11265 11274
11266 switch (afe_gain->standard) {11275 switch (afe_gain->standard) {
11267 case DRX_STANDARD_8VSB: /* fallthrough */11276 case DRX_STANDARD_8VSB: fallthrough;
11268#ifndef DRXJ_VSB_ONLY11277#ifndef DRXJ_VSB_ONLY
11269 case DRX_STANDARD_ITU_A: /* fallthrough */11278 case DRX_STANDARD_ITU_A:
11270 case DRX_STANDARD_ITU_B: /* fallthrough */11279 case DRX_STANDARD_ITU_B:
11271 case DRX_STANDARD_ITU_C:11280 case DRX_STANDARD_ITU_C:
11272#endif11281#endif
11273 /* Do nothing */11282 /* Do nothing */
@@ -11301,8 +11310,8 @@ ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain · 27 unmodified lines
11301 ext_attr->vsb_pga_cfg = gain * 13 + 140;11310 ext_attr->vsb_pga_cfg = gain * 13 + 140;
11302 break;11311 break;
11303#ifndef DRXJ_VSB_ONLY11312#ifndef DRXJ_VSB_ONLY
11304 case DRX_STANDARD_ITU_A: /* fallthrough */11313 case DRX_STANDARD_ITU_A:
11305 case DRX_STANDARD_ITU_B: /* fallthrough */11314 case DRX_STANDARD_ITU_B:

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drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c+13−0

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drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c+2−2

This diff is large: its 11 lines aren’t shown here.

drivers/net/ethernet/arc/emac_mdio.c+1−0

This diff is large: its 8 lines aren’t shown here.

drivers/net/ethernet/broadcom/bcmsysport.c+4−2

This diff is large: its 13 lines aren’t shown here.

drivers/net/ethernet/broadcom/bgmac-bcma.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/broadcom/bgmac-platform.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/broadcom/bnx2.c+7−7

This diff is large: its 56 lines aren’t shown here.

drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c+7−7

This diff is large: its 59 lines aren’t shown here.

drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c+2−2

This diff is large: its 14 lines aren’t shown here.

drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c+2−2

This diff is large: its 18 lines aren’t shown here.

drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c+2−2

This diff is large: its 18 lines aren’t shown here.

drivers/net/ethernet/broadcom/bnxt/bnxt.c+67−39

This diff is large: its 276 lines aren’t shown here.

drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c+8−12

This diff is large: its 60 lines aren’t shown here.

drivers/net/ethernet/broadcom/bnxt/bnxt_xdp.c+2−2

This diff is large: its 13 lines aren’t shown here.

drivers/net/ethernet/broadcom/cnic.c+2−2

This diff is large: its 18 lines aren’t shown here.

drivers/net/ethernet/broadcom/genet/bcmgenet.c+3−3

This diff is large: its 22 lines aren’t shown here.

drivers/net/ethernet/broadcom/genet/bcmmii.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/broadcom/tg3.c+40−31

This diff is large: its 226 lines aren’t shown here.

drivers/net/ethernet/brocade/bna/bfa_ioc.c+3−3

This diff is large: its 27 lines aren’t shown here.

drivers/net/ethernet/brocade/bna/bna_enet.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/brocade/bna/bna_tx_rx.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/cadence/macb_ptp.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/cavium/liquidio/lio_main.c+14−15

This diff is large: its 107 lines aren’t shown here.

drivers/net/ethernet/cavium/liquidio/lio_vf_main.c+12−13

This diff is large: its 86 lines aren’t shown here.

drivers/net/ethernet/cavium/thunder/nicvf_ethtool.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/cavium/thunder/nicvf_main.c+2−2

This diff is large: its 13 lines aren’t shown here.

drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/chelsio/cxgb3/l2t.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/chelsio/cxgb4/cxgb4_thermal.c+6−2

This diff is large: its 29 lines aren’t shown here.

drivers/net/ethernet/chelsio/cxgb4/l2t.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/chelsio/cxgb4/sge.c+7−3

This diff is large: its 34 lines aren’t shown here.

drivers/net/ethernet/chelsio/cxgb4/t4_hw.c+3−3

This diff is large: its 17 lines aren’t shown here.

drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/cisco/enic/enic_main.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/cortina/gemini.c+18−20

This diff is large: its 70 lines aren’t shown here.

drivers/net/ethernet/davicom/dm9000.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/dec/tulip/de4x5.c+3−3

This diff is large: its 27 lines aren’t shown here.

drivers/net/ethernet/dec/tulip/tulip_core.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/dec/tulip/winbond-840.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/emulex/benet/be_ethtool.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/freescale/dpaa/dpaa_eth.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/freescale/dpaa/dpaa_ethtool.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c+2−2

This diff is large: its 13 lines aren’t shown here.

drivers/net/ethernet/freescale/fec_main.c+2−2

This diff is large: its 14 lines aren’t shown here.

drivers/net/ethernet/freescale/fman/fman_memac.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/freescale/fman/fman_port.c+2−2

This diff is large: its 13 lines aren’t shown here.

drivers/net/ethernet/freescale/gianfar.c+3−1

This diff is large: its 12 lines aren’t shown here.

drivers/net/ethernet/freescale/ucc_geth.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/hisilicon/hns/hns_enet.c+6−3

This diff is large: its 23 lines aren’t shown here.

drivers/net/ethernet/hisilicon/hns/hns_ethtool.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/hisilicon/hns3/hns3_enet.c+5−3

This diff is large: its 36 lines aren’t shown here.

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c+1−3

This diff is large: its 22 lines aren’t shown here.

drivers/net/ethernet/ibm/ehea/ehea_main.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/ibm/emac/core.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/ibm/ibmvnic.c+14−1

This diff is large: its 47 lines aren’t shown here.

drivers/net/ethernet/intel/e1000e/netdev.c+0−1

This diff is large: its 8 lines aren’t shown here.

drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/intel/i40e/i40e_common.c+27−8

This diff is large: its 65 lines aren’t shown here.

drivers/net/ethernet/intel/i40e/i40e_main.c+3−0

This diff is large: its 10 lines aren’t shown here.

drivers/net/ethernet/intel/igb/igb_main.c+0−1

This diff is large: its 8 lines aren’t shown here.

drivers/net/ethernet/intel/igc/igc_main.c+2−3

This diff is large: its 19 lines aren’t shown here.

drivers/net/ethernet/intel/igc/igc_ptp.c+0−2

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/intel/ixgbe/ixgbe_fcoe.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/marvell/mvneta.c+2−2

This diff is large: its 13 lines aren’t shown here.

drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c+2−2

This diff is large: its 18 lines aren’t shown here.

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c+2−2

This diff is large: its 11 lines aren’t shown here.

drivers/net/ethernet/marvell/skge.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/marvell/sky2.c+2−2

This diff is large: its 18 lines aren’t shown here.

drivers/net/ethernet/mediatek/mtk_eth_soc.c+3−3

This diff is large: its 23 lines aren’t shown here.

drivers/net/ethernet/mellanox/mlx4/mr.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/mellanox/mlxfw/mlxfw_fsm.c+2−2

This diff is large: its 18 lines aren’t shown here.

drivers/net/ethernet/mellanox/mlxsw/core.c+9−9

This diff is large: its 31 lines aren’t shown here.

drivers/net/ethernet/mellanox/mlxsw/core_env.c+3−3

This diff is large: its 20 lines aren’t shown here.

drivers/net/ethernet/mellanox/mlxsw/core_hwmon.c+2−2

This diff is large: its 11 lines aren’t shown here.

drivers/net/ethernet/mellanox/mlxsw/spectrum.c+2−2

This diff is large: its 11 lines aren’t shown here.

drivers/net/ethernet/mellanox/mlxsw/spectrum.h+5−5

This diff is large: its 17 lines aren’t shown here.

drivers/net/ethernet/mellanox/mlxsw/spectrum_router.c+16−16

This diff is large: its 116 lines aren’t shown here.

drivers/net/ethernet/mellanox/mlxsw/spectrum_span.c+3−3

This diff is large: its 16 lines aren’t shown here.

drivers/net/ethernet/mellanox/mlxsw/spectrum_switchdev.c+6−6

This diff is large: its 40 lines aren’t shown here.

drivers/net/ethernet/microchip/lan743x_ethtool.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/mscc/ocelot.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/natsemi/natsemi.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/neterion/vxge/vxge-config.c+3−3

This diff is large: its 24 lines aren’t shown here.

drivers/net/ethernet/netronome/nfp/crypto/tls.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/netronome/nfp/flower/action.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/netronome/nfp/flower/cmsg.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/netronome/nfp/flower/offload.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/netronome/nfp/flower/tunnel_conf.c+2−0

This diff is large: its 16 lines aren’t shown here.

drivers/net/ethernet/netronome/nfp/nfp_asm.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/netronome/nfp/nfp_net_common.c+2−2

This diff is large: its 13 lines aren’t shown here.

drivers/net/ethernet/netronome/nfp/nfpcore/nfp6000_pcie.c+2−2

This diff is large: its 15 lines aren’t shown here.

drivers/net/ethernet/netronome/nfp/nfpcore/nfp_rtsym.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_param.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/packetengines/yellowfin.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/pensando/ionic/ionic_txrx.c+3−10

This diff is large: its 39 lines aren’t shown here.

drivers/net/ethernet/qlogic/netxen/netxen_nic_ethtool.c+2−2

This diff is large: its 18 lines aren’t shown here.

drivers/net/ethernet/qlogic/qed/qed_cxt.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/qlogic/qed/qed_dev.c+2−2

This diff is large: its 17 lines aren’t shown here.

drivers/net/ethernet/qlogic/qed/qed_main.c+2−2

This diff is large: its 18 lines aren’t shown here.

drivers/net/ethernet/qlogic/qed/qed_mcp.c+5−5

This diff is large: its 45 lines aren’t shown here.

drivers/net/ethernet/qlogic/qla3xxx.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c+2−2

This diff is large: its 18 lines aren’t shown here.

drivers/net/ethernet/realtek/r8169_main.c+2−2

This diff is large: its 18 lines aren’t shown here.

drivers/net/ethernet/renesas/ravb_main.c+55−55

This diff is large: its 166 lines aren’t shown here.

drivers/net/ethernet/rocker/rocker_main.c+4−4

This diff is large: its 36 lines aren’t shown here.

drivers/net/ethernet/samsung/sxgbe/sxgbe_ethtool.c+2−2

This diff is large: its 18 lines aren’t shown here.

drivers/net/ethernet/sfc/ef100.c+4−4

This diff is large: its 36 lines aren’t shown here.

drivers/net/ethernet/sfc/ef100_nic.c+6−4

This diff is large: its 39 lines aren’t shown here.

drivers/net/ethernet/sfc/ef100_rx.c+9−4

This diff is large: its 37 lines aren’t shown here.

drivers/net/ethernet/sfc/ef100_rx.h+1−0

This diff is large: its 8 lines aren’t shown here.

drivers/net/ethernet/sfc/efx.h+8−0

This diff is large: its 15 lines aren’t shown here.

drivers/net/ethernet/sfc/falcon/ethtool.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/sfc/falcon/farch.c+7−7

This diff is large: its 58 lines aren’t shown here.

drivers/net/ethernet/sfc/farch.c+7−7

This diff is large: its 58 lines aren’t shown here.

drivers/net/ethernet/sfc/mcdi_filters.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/sfc/mcdi_port_common.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/sfc/net_driver.h+4−0

This diff is large: its 32 lines aren’t shown here.

drivers/net/ethernet/sfc/nic.c+4−0

This diff is large: its 25 lines aren’t shown here.

drivers/net/ethernet/sfc/rx.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/sfc/rx_common.c+3−1

This diff is large: its 18 lines aren’t shown here.

drivers/net/ethernet/sis/sis900.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/smsc/smc911x.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/socionext/netsec.c+2−2

This diff is large: its 13 lines aren’t shown here.

drivers/net/ethernet/stmicro/stmmac/dwmac-anarion.c+4−3

This diff is large: its 14 lines aren’t shown here.

drivers/net/ethernet/stmicro/stmmac/stmmac_selftests.c+2−2

This diff is large: its 18 lines aren’t shown here.

drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/sun/cassini.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/sun/niu.c+2−2

This diff is large: its 18 lines aren’t shown here.

drivers/net/ethernet/sun/sungem.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/ti/am65-cpsw-nuss.c+2−0

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/ti/cpsw-phy-sel.c+2−2

This diff is large: its 18 lines aren’t shown here.

drivers/net/ethernet/ti/cpsw.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/ti/cpsw_new.c+22−7

This diff is large: its 42 lines aren’t shown here.

drivers/net/ethernet/ti/cpsw_priv.c+2−2

This diff is large: its 13 lines aren’t shown here.

drivers/net/ethernet/ti/tlan.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/toshiba/ps3_gelic_wireless.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/ethernet/toshiba/spider_net.c+14−14

This diff is large: its 63 lines aren’t shown here.

drivers/net/ethernet/xircom/xirc2ps_cs.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/fddi/skfp/cfm.c+2−15

This diff is large: its 48 lines aren’t shown here.

drivers/net/fddi/skfp/fplustm.c+0−4

This diff is large: its 11 lines aren’t shown here.

drivers/net/fddi/skfp/hwmtm.c+0−4

This diff is large: its 11 lines aren’t shown here.

drivers/net/fddi/skfp/pcmplc.c+2−2

This diff is large: its 18 lines aren’t shown here.

drivers/net/fddi/skfp/smt.c+2−5

This diff is large: its 28 lines aren’t shown here.

drivers/net/fjes/fjes_main.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/gtp.c+1−0

This diff is large: its 8 lines aren’t shown here.

drivers/net/hamradio/baycom_epp.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/hamradio/mkiss.c+2−3

This diff is large: its 26 lines aren’t shown here.

drivers/net/hyperv/netvsc_drv.c+2−2

This diff is large: its 18 lines aren’t shown here.

drivers/net/ipvlan/ipvlan_main.c+22−5

This diff is large: its 62 lines aren’t shown here.

drivers/net/macvlan.c+18−5

This diff is large: its 51 lines aren’t shown here.

drivers/net/mii.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/netdevsim/bus.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/netdevsim/fib.c+3−3

This diff is large: its 18 lines aren’t shown here.

drivers/net/phy/adin.c+2−2

This diff is large: its 13 lines aren’t shown here.

drivers/net/phy/dp83640.c+4−4

This diff is large: its 26 lines aren’t shown here.

drivers/net/phy/dp83867.c+2−2

This diff is large: its 12 lines aren’t shown here.

drivers/net/phy/dp83869.c+6−6

This diff is large: its 25 lines aren’t shown here.

drivers/net/phy/fixed_phy.c+2−2

This diff is large: its 16 lines aren’t shown here.

drivers/net/phy/mscc/mscc_main.c+2−2

This diff is large: its 16 lines aren’t shown here.

drivers/net/phy/phy.c+2−2

This diff is large: its 18 lines aren’t shown here.

drivers/net/phy/phy_device.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/phy/phylink.c+2−2

This diff is large: its 18 lines aren’t shown here.

drivers/net/phy/sfp-bus.c+2−2

This diff is large: its 18 lines aren’t shown here.

drivers/net/phy/sfp.c+6−6

This diff is large: its 54 lines aren’t shown here.

drivers/net/plip/plip.c+13−13

This diff is large: its 117 lines aren’t shown here.

drivers/net/tun.c+3−3

This diff is large: its 22 lines aren’t shown here.

drivers/net/usb/Kconfig+1−0

This diff is large: its 8 lines aren’t shown here.

drivers/net/usb/aqc111.c+3−3

This diff is large: its 17 lines aren’t shown here.

drivers/net/usb/asix_common.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/usb/catc.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/usb/cdc-phonet.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/usb/dm9601.c+4−0

This diff is large: its 11 lines aren’t shown here.

drivers/net/usb/lan78xx.c+2−2

This diff is large: its 18 lines aren’t shown here.

drivers/net/usb/pegasus.c+2−2

This diff is large: its 18 lines aren’t shown here.

drivers/net/usb/r8152.c+3−3

This diff is large: its 27 lines aren’t shown here.

drivers/net/usb/rtl8150.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/usb/usbnet.c+3−3

This diff is large: its 27 lines aren’t shown here.

drivers/net/veth.c+4−4

This diff is large: its 26 lines aren’t shown here.

drivers/net/virtio_net.c+3−3

This diff is large: its 22 lines aren’t shown here.

drivers/net/vmxnet3/vmxnet3_ethtool.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/wan/dlci.c+1−2

This diff is large: its 16 lines aren’t shown here.

drivers/net/wan/hdlc.c+2−1

This diff is large: its 10 lines aren’t shown here.

drivers/net/wan/hdlc_cisco.c+1−0

This diff is large: its 8 lines aren’t shown here.

drivers/net/wan/hdlc_x25.c+16−1

This diff is large: its 32 lines aren’t shown here.

drivers/net/wan/lapbether.c+4−1

This diff is large: its 26 lines aren’t shown here.

drivers/net/wan/sdla.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/wan/x25_asy.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/wimax/i2400m/control.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/wimax/i2400m/usb-fw.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/wimax/i2400m/usb-tx.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/wimax/i2400m/usb.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/xen-netback/hash.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/xen-netback/xenbus.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/net/xen-netfront.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/nfc/pn533/pn533.c+2−2

This diff is large: its 18 lines aren’t shown here.

drivers/nfc/st21nfca/dep.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/nfc/st95hf/core.c+1−1

This diff is large: its 9 lines aren’t shown here.

drivers/nfc/trf7970a.c+2−2

This diff is large: its 18 lines aren’t shown here.

drivers/ntb/ntb_transport.c+2−2

This diff is large: its 18 lines aren’t shown here.

drivers/nvdimm/dimm_devs.c+1−0

This diff is large: its 8 lines aren’t shown here.

drivers/nvme/host/core.c+104−48

This diff is large: its 296 lines aren’t shown here.

drivers/nvme/host/fabrics.c+0−1

This diff is large: its 8 lines aren’t shown here.

drivers/nvme/host/fc.c+3−3

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drivers/nvme/host/multipath.c+26−43

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drivers/nvme/host/nvme.h+28−5

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drivers/nvme/host/pci.c+12−11

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drivers/nvme/host/rdma.c+53−19

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drivers/nvme/host/tcp.c+59−26

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drivers/nvme/target/configfs.c+1−0

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drivers/nvme/target/core.c+7−1

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drivers/nvme/target/fc.c+2−2

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drivers/nvme/target/fcloop.c+1−1

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drivers/nvme/target/io-cmd-bdev.c+0−1

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drivers/nvme/target/loop.c+1−1

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drivers/nvme/target/passthru.c+17−8

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drivers/nvme/target/rdma.c+2−2

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drivers/nvme/target/tcp.c+9−1

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drivers/of/address.c+20−1

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drivers/opp/core.c+28−13

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drivers/opp/opp.h+1−1

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drivers/parport/ieee1284.c+3−3

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drivers/parport/parport_pc.c+1−1

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drivers/pci/controller/dwc/pci-imx6.c+3−3

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drivers/pci/controller/pci-rcar-gen2.c+1−1

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drivers/pci/hotplug/ibmphp_res.c+1−1

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drivers/pci/hotplug/pciehp_ctrl.c+2−2

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drivers/pci/hotplug/s390_pci_hpc.c+5−7

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drivers/pci/hotplug/shpchp_ctrl.c+2−2

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drivers/pci/p2pdma.c+6−4

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drivers/pci/pci.c+2−2

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drivers/pci/proc.c+1−1

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drivers/pci/quirks.c+2−2

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drivers/pci/setup-bus.c+1−1

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drivers/pci/xen-pcifront.c+1−1

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drivers/pcmcia/db1xxx_ss.c+4−4

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drivers/perf/arm-ccn.c+1−1

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drivers/perf/arm_spe_pmu.c+2−2

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drivers/phy/qualcomm/phy-qcom-usb-hs.c+1−1

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drivers/phy/rockchip/phy-rockchip-inno-usb2.c+4−4

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drivers/platform/olpc/olpc-xo175-ec.c+1−1

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drivers/platform/x86/acer-wmi.c+4−4

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drivers/platform/x86/dell-laptop.c+2−2

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drivers/platform/x86/surfacepro3_button.c+4−4

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drivers/platform/x86/thinkpad_acpi.c+3−3

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drivers/platform/x86/toshiba_acpi.c+1−1

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drivers/power/supply/ab8500_charger.c+2−2

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drivers/power/supply/ab8500_fg.c+2−2

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drivers/power/supply/abx500_chargalg.c+13−13

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drivers/power/supply/axp20x_usb_power.c+1−1

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drivers/power/supply/cros_usbpd-charger.c+1−1

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drivers/power/supply/max8925_power.c+1−1

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drivers/power/supply/wm831x_power.c+1−1

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drivers/power/supply/wm8350_power.c+1−1

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drivers/ps3/ps3av.c+1−1

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drivers/ps3/ps3av_cmd.c+2−2

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drivers/ptp/ptp_clockmatrix.c+43−13

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drivers/ptp/ptp_clockmatrix.h+2−0

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drivers/rapidio/devices/rio_mport_cdev.c+1−1

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drivers/regulator/axp20x-regulator.c+4−4

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drivers/regulator/core.c+1−1

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drivers/regulator/slg51000-regulator.c+1−1

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drivers/regulator/twl6030-regulator.c+1−1

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drivers/remoteproc/omap_remoteproc.c+0−1

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drivers/reset/reset-imx7.c+7−7

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drivers/rpmsg/qcom_glink_native.c+2−2

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drivers/rtc/rtc-m41t80.c+1−1

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drivers/rtc/rtc-pcf85063.c+1−1

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drivers/rtc/rtc-pcf8523.c+1−1

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drivers/rtc/rtc-stmp3xxx.c+1−1

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drivers/s390/cio/css.c+5−0

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drivers/s390/net/ctcm_fsms.c+1−1

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drivers/s390/net/ctcm_mpc.c+3−3

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drivers/s390/net/qeth_core_main.c+2−2

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drivers/s390/net/qeth_ethtool.c+3−3

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drivers/s390/net/qeth_l2_main.c+1−1

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drivers/s390/net/qeth_l3_main.c+1−1

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drivers/s390/scsi/zfcp_fsf.c+2−2

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drivers/scsi/53c700.c+1−1

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drivers/scsi/BusLogic.c+1−1

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drivers/scsi/FlashPoint.c+6−3

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drivers/scsi/NCR5380.c+1−1

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drivers/scsi/aacraid/aachba.c+4−4

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drivers/scsi/aacraid/commsup.c+1−1

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drivers/scsi/aacraid/linit.c+1−1

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drivers/scsi/aic7xxx/aic79xx_core.c+20−20

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drivers/scsi/aic7xxx/aic79xx_osm.c+1−1

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drivers/scsi/aic7xxx/aic7xxx_core.c+14−14

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drivers/scsi/aic94xx/aic94xx_scb.c+5−5

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drivers/scsi/aic94xx/aic94xx_tmf.c+1−1

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drivers/scsi/arcmsr/arcmsr_hba.c+1−1

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drivers/scsi/arm/fas216.c+6−6

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drivers/scsi/be2iscsi/be_iscsi.c+1−1

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drivers/scsi/be2iscsi/be_main.c+1−1

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drivers/scsi/bfa/bfa_fcpim.c+3−3

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drivers/scsi/bfa/bfa_fcs_lport.c+2−2

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drivers/scsi/bfa/bfa_fcs_rport.c+7−7

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drivers/scsi/bfa/bfa_ioc.c+3−3

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drivers/scsi/bfa/bfa_svc.c+1−1

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drivers/scsi/bnx2fc/bnx2fc_hwi.c+0−1

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drivers/scsi/csiostor/csio_hw.c+1−1

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drivers/scsi/csiostor/csio_lnode.c+0−1

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drivers/scsi/csiostor/csio_wr.c+1−1

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drivers/scsi/cxgbi/cxgb3i/cxgb3i.c+1−1

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drivers/scsi/cxgbi/cxgb4i/cxgb4i.c+1−1

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drivers/scsi/cxgbi/libcxgbi.c+1−1

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drivers/scsi/cxlflash/main.c+14−14

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drivers/scsi/cxlflash/superpipe.c+4−6

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drivers/scsi/device_handler/scsi_dh_hp_sw.c+2−2

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drivers/scsi/esas2r/esas2r_flash.c+1−1

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drivers/scsi/esas2r/esas2r_init.c+2−2

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drivers/scsi/esp_scsi.c+2−2

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drivers/scsi/fcoe/fcoe_ctlr.c+4−4

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drivers/scsi/g_NCR5380.c+1−1

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drivers/scsi/hisi_sas/hisi_sas_main.c+1−1

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drivers/scsi/hpsa.c+5−5

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drivers/scsi/ibmvscsi/ibmvfc.c+3−3

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drivers/scsi/ibmvscsi_tgt/ibmvscsi_tgt.c+3−3

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drivers/scsi/imm.c+7−7

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drivers/scsi/isci/phy.c+1−1

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drivers/scsi/isci/remote_device.c+2−2

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drivers/scsi/isci/remote_node_context.c+3−3

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drivers/scsi/isci/request.c+1−1

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drivers/scsi/libfc/fc_exch.c+2−2

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drivers/scsi/libfc/fc_fcp.c+4−4

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drivers/scsi/libfc/fc_lport.c+1−1

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drivers/scsi/libfc/fc_rport.c+1−1

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drivers/scsi/libiscsi.c+3−3

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drivers/scsi/libiscsi_tcp.c+1−1

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drivers/scsi/libsas/sas_ata.c+1−1

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drivers/scsi/libsas/sas_discover.c+1−1

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drivers/scsi/libsas/sas_expander.c+1−1

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drivers/scsi/libsas/sas_scsi_host.c+1−1

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drivers/scsi/lpfc/lpfc_ct.c+2−2

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drivers/scsi/lpfc/lpfc_els.c+1−1

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drivers/scsi/lpfc/lpfc_hbadisc.c+3−4

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drivers/scsi/lpfc/lpfc_nportdisc.c+1−1

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drivers/scsi/lpfc/lpfc_nvme.c+1−1

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drivers/scsi/lpfc/lpfc_scsi.c+4−4

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drivers/scsi/lpfc/lpfc_sli.c+14−14

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drivers/scsi/megaraid.c+6−6

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drivers/scsi/megaraid/megaraid_mbox.c+1−1

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drivers/scsi/megaraid/megaraid_sas_base.c+1−1

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drivers/scsi/megaraid/megaraid_sas_fusion.c+1−1

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drivers/scsi/mesh.c+1−1

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drivers/scsi/mpt3sas/mpt3sas_base.c+1−1

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drivers/scsi/mpt3sas/mpt3sas_ctl.c+1−1

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drivers/scsi/mpt3sas/mpt3sas_scsih.c+4−4

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drivers/scsi/myrb.c+4−4

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drivers/scsi/ncr53c8xx.c+7−7

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drivers/scsi/pcmcia/nsp_cs.c+1−1

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drivers/scsi/ppa.c+5−5

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drivers/scsi/qedf/qedf_main.c+1−1

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drivers/scsi/qla2xxx/qla_dbg.h+3−0

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drivers/scsi/qla2xxx/qla_def.h+1−0

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drivers/scsi/qla2xxx/qla_gs.c+40−10

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drivers/scsi/qla2xxx/qla_init.c+1−1

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drivers/scsi/qla2xxx/qla_iocb.c+1−1

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drivers/scsi/qla2xxx/qla_isr.c+7−7

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drivers/scsi/qla2xxx/qla_mbx.c+7−15

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drivers/scsi/qla2xxx/qla_nvme.c+14−1

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drivers/scsi/qla2xxx/qla_os.c+5−4

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drivers/scsi/qla2xxx/qla_sup.c+3−3

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drivers/scsi/qla2xxx/qla_target.c+4−4

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drivers/scsi/qla4xxx/ql4_os.c+1−1

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drivers/scsi/qlogicpti.c+10−10

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drivers/scsi/scsi_debug.c+2−2

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drivers/scsi/scsi_error.c+14−14

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drivers/scsi/scsi_ioctl.c+2−2

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drivers/scsi/scsi_lib.c+1−1

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drivers/scsi/smartpqi/smartpqi_init.c+8−9

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drivers/scsi/sr.c+2−2

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drivers/scsi/st.c+4−4

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drivers/scsi/sun3_scsi.c+2−2

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drivers/scsi/sym53c8xx_2/sym_fw.c+1−1

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drivers/scsi/sym53c8xx_2/sym_hipd.c+2−2

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drivers/scsi/sym53c8xx_2/sym_nvram.c+1−1

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drivers/scsi/ufs/ti-j721e-ufs.c+1−0

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drivers/scsi/ufs/ufs-mediatek.c+1−1

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drivers/scsi/ufs/ufs_bsg.c+1−1

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drivers/scsi/ufs/ufshcd-pci.c+14−2

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drivers/scsi/ufs/ufshcd.c+22−17

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drivers/scsi/ufs/ufshcd.h+8−1

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drivers/scsi/virtio_scsi.c+1−1

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drivers/scsi/vmw_pvscsi.c+1−1

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drivers/scsi/wd33c93.c+1−1

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drivers/scsi/xen-scsifront.c+1−1

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drivers/soc/qcom/socinfo.c+11−11

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drivers/soc/tegra/pmc.c+1−1

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drivers/spi/Kconfig+3−0

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drivers/spi/spi-bcm2835aux.c+2−2

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drivers/spi/spi-fsl-cpm.c+2−2

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drivers/spi/spi-sprd-adi.c+1−1

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drivers/spi/spi-stm32.c+62−38

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drivers/spi/spi.c+20−1

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drivers/ssb/driver_chipcommon.c+1−1

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drivers/ssb/driver_mipscore.c+1−1

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drivers/ssb/scan.c+1−1

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drivers/staging/media/atomisp/pci/atomisp_cmd.c+1−1

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drivers/staging/media/atomisp/pci/atomisp_compat_css20.c+4−4

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drivers/staging/media/atomisp/pci/atomisp_ioctl.c+0−1

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drivers/staging/media/atomisp/pci/atomisp_v4l2.c+1−1

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drivers/staging/media/atomisp/pci/hmm/hmm_bo.c+1−1

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drivers/staging/media/atomisp/pci/sh_css.c+1−1

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drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c+1−1

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drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c+1−1

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drivers/staging/media/imx/imx-media-csi.c+1−1

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drivers/staging/media/sunxi/cedrus/cedrus.c+6−1

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drivers/staging/media/usbvision/usbvision-i2c.c+3−3

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drivers/target/iscsi/cxgbit/cxgbit_main.c+1−1

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drivers/target/iscsi/iscsi_target.c+1−1

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drivers/target/target_core_pr.c+2−2

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drivers/target/target_core_sbc.c+1−1

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drivers/target/target_core_transport.c+2−2

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drivers/target/tcm_fc/tfc_cmd.c+1−1

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drivers/thermal/qcom/qcom-spmi-temp-alarm.c+2−2

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drivers/thermal/qcom/tsens-v0_1.c+4−4

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drivers/thermal/qcom/tsens-v1.c+2−2

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drivers/thermal/thermal_core.c+3−2

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drivers/thermal/ti-soc-thermal/omap4-thermal-data.c+12−11

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drivers/thermal/ti-soc-thermal/omap4xxx-bandgap.h+7−3

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drivers/thunderbolt/ctl.c+1−1

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drivers/thunderbolt/switch.c+1−1

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drivers/thunderbolt/tunnel.c+2−2

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drivers/tty/hvc/hvc_xen.c+1−1

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drivers/tty/mips_ejtag_fdc.c+1−1

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drivers/tty/n_r3964.c+0−1

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drivers/tty/serial/8250/8250_em.c+1−1

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drivers/tty/serial/8250/8250_exar.c+21−3

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drivers/tty/serial/8250/8250_fintek.c+1−1

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drivers/tty/serial/8250/8250_pci.c+1−1

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drivers/tty/serial/8250/8250_port.c+7−4

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drivers/tty/serial/8250/8250_uniphier.c+3−3

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drivers/tty/serial/Kconfig+1−0

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drivers/tty/serial/Makefile+1−0

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drivers/tty/serial/amba-pl011.c+9−7

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drivers/tty/serial/atmel_serial.c+1−1

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drivers/tty/serial/omap-serial.c+0−2

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drivers/tty/serial/qcom_geni_serial.c+8−3

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drivers/tty/serial/rda-uart.c+1−1

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drivers/tty/serial/samsung_tty.c+5−3

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drivers/tty/serial/serial-tegra.c+1−1

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drivers/tty/serial/serial_core.c+1−1

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drivers/tty/serial/stm32-usart.c+1−1

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drivers/tty/serial/sunsu.c+1−1

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drivers/tty/serial/sunzilog.c+1−1

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drivers/tty/serial/xilinx_uartps.c+1−1

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drivers/tty/vt/vt_ioctl.c+11−1

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drivers/usb/c67x00/c67x00-sched.c+2−1

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drivers/usb/class/cdc-acm.c+10−12

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drivers/usb/core/driver.c+38−2

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drivers/usb/core/generic.c+3−2

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drivers/usb/core/hcd-pci.c+4−1

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drivers/usb/core/hub.c+1−1

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drivers/usb/core/quirks.c+7−0

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drivers/usb/dwc3/core.c+2−3

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drivers/usb/dwc3/gadget.c+89−18

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drivers/usb/gadget/function/f_mass_storage.c+0−1

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drivers/usb/gadget/function/f_ncm.c+69−12

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drivers/usb/gadget/function/f_tcm.c+4−3

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drivers/usb/gadget/u_f.h+27−11

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drivers/usb/gadget/udc/atmel_usba_udc.c+1−1

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drivers/usb/gadget/udc/fsl_udc_core.c+1−1

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drivers/usb/gadget/udc/pxa25x_udc.c+2−2

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drivers/usb/host/isp116x-hcd.c+3−3

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drivers/usb/host/ohci-exynos.c+2−3

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drivers/usb/host/pci-quirks.c+2−1

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drivers/usb/host/xhci-dbgcap.c+1−1

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drivers/usb/host/xhci-debugfs.c+4−4

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drivers/usb/host/xhci-hub.c+11−10

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drivers/usb/host/xhci-mem.c+2−2

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drivers/usb/host/xhci-pci-renesas.c+1−18

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drivers/usb/host/xhci-ring.c+1−1

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drivers/usb/host/xhci-tegra.c+3−1

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drivers/usb/host/xhci.c+3−2

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drivers/usb/misc/lvstest.c+1−1

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drivers/usb/misc/yurex.c+1−1

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drivers/usb/musb/cppi_dma.c+1−1

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drivers/usb/musb/musb_core.c+6−7

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drivers/usb/musb/musb_dsps.c+3−3

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drivers/usb/musb/musb_gadget_ep0.c+2−2

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drivers/usb/musb/musb_host.c+3−3

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drivers/usb/musb/musb_virthub.c+1−1

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drivers/usb/musb/omap2430.c+1−1

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drivers/usb/musb/tusb6010.c+1−1

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drivers/usb/phy/phy-jz4770.c+1−0

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drivers/usb/storage/sddr55.c+1−1

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drivers/usb/storage/uas.c+1−1

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drivers/usb/storage/unusual_devs.h+1−1

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drivers/usb/storage/unusual_uas.h+14−0

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drivers/usb/typec/tcpm/tcpci.c+1−1

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drivers/usb/typec/tcpm/tcpm.c+25−3

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drivers/usb/typec/ucsi/displayport.c+1−8

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drivers/usb/typec/ucsi/ucsi.c+53−50

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drivers/usb/usbip/stub_dev.c+6−0

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drivers/vdpa/ifcvf/ifcvf_base.h+1−1

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drivers/vdpa/ifcvf/ifcvf_main.c+7−2

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drivers/vdpa/mlx5/net/mlx5_vnet.c+25−25

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drivers/vfio/pci/vfio_pci.c+1−1

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drivers/vfio/pci/vfio_pci_private.h+2−0

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drivers/vfio/pci/vfio_pci_rdwr.c+96−24

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drivers/vfio/vfio_iommu_type1.c+67−6

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drivers/vhost/iotlb.c+2−2

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drivers/vhost/vhost.c+1−1

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drivers/video/backlight/adp8860_bl.c+1−1

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drivers/video/fbdev/acornfb.c+1−1

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drivers/video/fbdev/arcfb.c+1−1

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drivers/video/fbdev/atmel_lcdfb.c+2−2

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drivers/video/fbdev/aty/radeon_pm.c+3−3

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drivers/video/fbdev/cirrusfb.c+2−2

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drivers/video/fbdev/controlfb.c+3−1

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drivers/video/fbdev/core/fbcon.c+23−2

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drivers/video/fbdev/core/fbmem.c+1−1

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drivers/video/fbdev/efifb.c+1−1

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drivers/video/fbdev/fsl-diu-fb.c+2−2

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drivers/video/fbdev/gxt4500.c+1−1

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drivers/video/fbdev/hyperv_fb.c+2−2

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drivers/video/fbdev/i740fb.c+1−1

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drivers/video/fbdev/mmp/fb/mmpfb.c+0−2

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drivers/video/fbdev/nvidia/nv_hw.c+1−1

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drivers/video/fbdev/offb.c+2−2

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drivers/video/fbdev/omap/lcdc.c+2−2

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drivers/video/fbdev/omap/omapfb_main.c+10−10

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drivers/video/fbdev/omap2/omapfb/dss/dispc.c+2−2

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drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c+1−1

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drivers/video/fbdev/omap2/omapfb/omapfb-main.c+1−1

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drivers/video/fbdev/pm2fb.c+2−2

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drivers/video/fbdev/pxa168fb.c+0−4

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drivers/video/fbdev/pxafb.c+1−1

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drivers/video/fbdev/riva/fbdev.c+1−1

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drivers/video/fbdev/s3c-fb.c+3−3

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drivers/video/fbdev/sa1100fb.c+1−1

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drivers/video/fbdev/savage/savagefb_driver.c+1−1

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drivers/video/fbdev/sh_mobile_lcdcfb.c+2−2

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drivers/video/fbdev/sis/sis_main.c+4−4

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drivers/video/fbdev/sm501fb.c+1−1

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drivers/video/fbdev/stifb.c+2−2

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drivers/video/fbdev/tdfxfb.c+1−1

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drivers/video/fbdev/via/lcd.c+1−1

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drivers/video/fbdev/xen-fbfront.c+1−1

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drivers/watchdog/sc1200wdt.c+1−1

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drivers/watchdog/wdrtas.c+1−1

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drivers/xen/Kconfig+10−0

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drivers/xen/Makefile+1−0

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drivers/xen/balloon.c+2−2

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drivers/xen/events/events_base.c+8−8

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drivers/xen/grant-table.c+2−2

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drivers/xen/privcmd.c+2−2

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drivers/xen/pvcalls-front.c+1−1

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drivers/xen/unpopulated-alloc.c+183−0

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drivers/xen/xen-acpi-memhotplug.c+1−1

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drivers/xen/xen-pciback/xenbus.c+1−1

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drivers/xen/xen-scsiback.c+1−1

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drivers/xen/xenbus/xenbus_client.c+11−5

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drivers/xen/xenbus/xenbus_probe_frontend.c+2−2

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drivers/xen/xlate_mmu.c+2−2

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fs/9p/vfs_file.c+1−1

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fs/adfs/dir_f.c+6−6

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fs/affs/amigaffs.c+27−0

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fs/affs/file.c+25−1

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fs/affs/inode.c+1−1

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fs/affs/super.c+3−3

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fs/afs/cmservice.c+8−8

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fs/afs/dynroot.c+11−9

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fs/afs/file.c+1−1

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fs/afs/flock.c+0−1

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fs/afs/fs_operation.c+1−0

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fs/afs/fs_probe.c+2−2

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fs/afs/fsclient.c+21−21

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fs/afs/internal.h+8−6

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fs/afs/misc.c+9−9

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fs/afs/proc.c+5−0

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fs/afs/rotate.c+1−1

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fs/afs/rxrpc.c+3−3

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fs/afs/vl_list.c+1−0

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fs/afs/vl_probe.c+51−31

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fs/afs/vl_rotate.c+6−1

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fs/afs/vlclient.c+12−12

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fs/afs/write.c+1−1

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fs/afs/yfsclient.c+25−25

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fs/aio.c+1−1

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fs/binfmt_flat.c+12−8

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fs/btrfs/block-group.c+3−1

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fs/btrfs/ctree.c+6−2

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fs/btrfs/ctree.h+3−3

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fs/btrfs/disk-io.c+1−0

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fs/btrfs/extent-tree.c+12−7

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fs/btrfs/extent_io.c+4−4

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fs/btrfs/extent_io.h+3−3

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fs/btrfs/file.c+1−1

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fs/btrfs/free-space-cache.c+1−1

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fs/btrfs/free-space-tree.c+4−0

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fs/btrfs/inode.c+14−15

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fs/btrfs/ioctl.c+20−7

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fs/btrfs/scrub.c+70−52

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fs/btrfs/super.c+1−0

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fs/btrfs/tree-checker.c+1−1

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fs/btrfs/tree-log.c+6−4

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fs/btrfs/volumes.c+2−1

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fs/buffer.c+10−1

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fs/ceph/caps.c+7−7

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fs/ceph/dir.c+14−19

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fs/ceph/file.c+4−3

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fs/ceph/inode.c+9−10

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fs/ceph/mds_client.h+1−1

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fs/ceph/quota.c+2−2

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fs/ceph/super.h+38−35

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fs/cifs/cifsglob.h+15−0

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fs/cifs/cifssmb.c+1−1

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fs/cifs/connect.c+6−6

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fs/cifs/sess.c+3−3

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fs/cifs/smb2pdu.c+1−1

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fs/configfs/dir.c+2−2

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fs/dax.c+1−1

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fs/dlm/lock.c+1−1

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fs/erofs/zmap.c+3−3

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fs/eventpoll.c+15−15

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fs/ext2/file.c+4−2

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fs/ext2/inode.c+2−2

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fs/ext2/super.c+1−1

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fs/ext4/Kconfig+1−1

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fs/ext4/balloc.c+12−4

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fs/ext4/block_validity.c+69−90

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fs/ext4/ext4.h+63−28

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fs/ext4/ext4_jbd2.c+25−0

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fs/ext4/extents.c+18−24

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fs/ext4/file.c+7−4

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fs/ext4/hash.c+2−2

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fs/ext4/indirect.c+9−11

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fs/ext4/inline.c+2−2

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fs/ext4/inode.c+16−16

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fs/ext4/ioctl.c+17−17

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fs/ext4/mballoc.c+244−45

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fs/ext4/mballoc.h+4−0

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fs/ext4/move_extent.c+2−2

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fs/ext4/namei.c+39−27

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fs/ext4/readpage.c+2−2

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fs/ext4/super.c+189−79

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fs/ext4/sysfs.c+13−0

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fs/ext4/xattr.c+1−2

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fs/f2fs/f2fs.h+1−1

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fs/f2fs/node.c+2−2

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fs/fcntl.c+2−2

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fs/fs-writeback.c+53−50

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fs/fs_context.c+1−1

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fs/fsopen.c+1−1

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fs/gfs2/bmap.c+2−2

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fs/gfs2/log.c+31−0

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fs/gfs2/quota.c+1−1

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fs/gfs2/trans.c+1−0

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fs/hfsplus/wrapper.c+1−1

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fs/io-wq.c+19−2

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fs/io_uring.c+200−140

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fs/iomap/seek.c+2−2

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fs/jbd2/journal.c+9−7

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fs/jbd2/recovery.c+12−34

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fs/jbd2/transaction.c+27−6

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