Merge tag 'media/v5.8-3' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media into master

Pull media fixes from Mauro Carvalho Chehab: "A series of fixes for the upcoming atomisp driver. They solve issues when probing atomisp on devices with multiple cameras and get rid of warnings when built with W=1. The diffstat is a bit long, as this driver has several abstractions. The patches that solved the issues with W=1 had to get rid of some duplicated code (there used to have 2 versions of the same code, one for ISP2401 and another one for ISP2400). As this driver is not in 5.7, such changes won't cause regressions" * tag 'media/v5.8-3' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media: (38 commits) Revert "media: atomisp: keep the ISP powered on when setting it" media: atomisp: fix mask and shift operation on ISPSSPM0 media: atomisp: move system_local consts into a C file media: atomisp: get rid of version-specific system_local.h media: atomisp: move global stuff into a common header media: atomisp: remove non-used 32-bits consts at system_local media: atomisp: get rid of some unused static vars media: atomisp: Fix error code in ov5693_probe() media: atomisp: Replace trace_printk by pr_info media: atomisp: Fix __func__ style warnings media: atomisp: fix help message for ISP2401 selection media: atomisp: i2c: atomisp-ov2680.c: fixed a brace coding style issue. media: atomisp: make const arrays static, makes object smaller media: atomisp: Clean up non-existing folders from Makefile media: atomisp: Get rid of ACPI specifics in gmin_subdev_add() media: atomisp: Provide Gmin subdev as parameter to gmin_subdev_add() media: atomisp: Use temporary variable for device in gmin_subdev_add() media: atomisp: Refactor PMIC detection to a separate function media: atomisp: Deduplicate return ret in gmin_i2c_write() media: atomisp: Make pointer to PMIC client global ...

Linus Torvalds committed 6 years ago

Commit d15be542 parents 071fb1b 0d6db8530 files · +1280 −1929Browse files

Unified · Split

30 files

arch/x86/include/asm/iosf_mbi.h +1 −0
drivers/staging/media/atomisp/Kconfig +1 −1
drivers/staging/media/atomisp/Makefile +1 −5
drivers/staging/media/atomisp/i2c/atomisp-ov2680.c +3 −3
drivers/staging/media/atomisp/i2c/ov5693/atomisp-ov5693.c +4 −2
drivers/staging/media/atomisp/include/linux/atomisp_platform.h +1 −0
drivers/staging/media/atomisp/pci/atomisp-regs.h +0 −3
drivers/staging/media/atomisp/pci/atomisp_acc.c +2 −2
drivers/staging/media/atomisp/pci/atomisp_cmd.c +32 −27
drivers/staging/media/atomisp/pci/atomisp_cmd.h +2 −2
drivers/staging/media/atomisp/pci/atomisp_compat.h +0 −2
drivers/staging/media/atomisp/pci/atomisp_compat_css20.c +34 −36
drivers/staging/media/atomisp/pci/atomisp_compat_css20.h +1 −1
drivers/staging/media/atomisp/pci/atomisp_drvfs.c +7 −7
drivers/staging/media/atomisp/pci/atomisp_drvfs.h +1 −1
drivers/staging/media/atomisp/pci/atomisp_gmin_platform.c +351 −186
drivers/staging/media/atomisp/pci/atomisp_internal.h +1 −1
drivers/staging/media/atomisp/pci/atomisp_ioctl.c +9 −10
drivers/staging/media/atomisp/pci/atomisp_v4l2.c +127 −158
drivers/staging/media/atomisp/pci/base/refcount/src/refcount.c +14 −14
drivers/staging/media/atomisp/pci/hive_types.h +3 −21
drivers/staging/media/atomisp/pci/hmm/hmm.c +5 −5
drivers/staging/media/atomisp/pci/isp2400_system_global.h +0 −302
drivers/staging/media/atomisp/pci/isp2400_system_local.h +0 −321
drivers/staging/media/atomisp/pci/isp2401_system_global.h +1 −409
drivers/staging/media/atomisp/pci/isp2401_system_local.h +0 −402
drivers/staging/media/atomisp/pci/sh_css.c +7 −2
drivers/staging/media/atomisp/pci/system_global.h +395 −0
drivers/staging/media/atomisp/pci/system_local.c +179 −0
drivers/staging/media/atomisp/pci/system_local.h +98 −6

arch/x86/include/asm/iosf_mbi.h+1−0

@@ -39,6 +39,7 @@ · 38 unmodified lines
39	39	#define BT_MBI_UNIT_PMC 0x04
40	40	#define BT_MBI_UNIT_GFX 0x06
41	41	#define BT_MBI_UNIT_SMI 0x0C
	42	+#define BT_MBI_UNIT_CCK 0x14
42	43	#define BT_MBI_UNIT_USB 0x43
43	44	#define BT_MBI_UNIT_SATA 0xA3
44	45	#define BT_MBI_UNIT_PCIE 0xA6

drivers/staging/media/atomisp/Kconfig+1−1

@@ -22,7 +22,7 @@ config VIDEO_ATOMISP · 21 unmodified lines
22	22	module will be called atomisp
23	23
24	24	config VIDEO_ATOMISP_ISP2401
25		− bool "VIDEO_ATOMISP_ISP2401"
	25	+ bool "Use Intel Atom ISP on Cherrytail/Anniedale (ISP2401)"
26	26	depends on VIDEO_ATOMISP
27	27	help
28	28	Enable support for Atom ISP2401-based boards.

drivers/staging/media/atomisp/Makefile+1−5

@@ -156,6 +156,7 @@ atomisp-objs += \ · 155 unmodified lines
156	156	pci/hive_isp_css_common/host/timed_ctrl.o \
157	157	pci/hive_isp_css_common/host/vmem.o \
158	158	pci/hive_isp_css_shared/host/tag.o \
	159	+ pci/system_local.o \
159	160
160	161	obj-byt = \
161	162	pci/css_2400_system/hive/ia_css_isp_configs.o \
@@ -182,7 +183,6 @@ INCLUDES += \ · 20 unmodified lines
182	183	-I$(atomisp)/include/hmm/ \
183	184	-I$(atomisp)/include/mmu/ \
184	185	-I$(atomisp)/pci/ \
185		− -I$(atomisp)/pci/hrt/ \
186	186	-I$(atomisp)/pci/base/circbuf/interface/ \
187	187	-I$(atomisp)/pci/base/refcount/interface/ \
188	188	-I$(atomisp)/pci/camera/pipe/interface/ \
@@ -192,7 +192,6 @@ INCLUDES += \ · 3 unmodified lines
192	192	-I$(atomisp)/pci/hive_isp_css_include/ \
193	193	-I$(atomisp)/pci/hive_isp_css_include/device_access/ \
194	194	-I$(atomisp)/pci/hive_isp_css_include/host/ \
195		− -I$(atomisp)/pci/hive_isp_css_include/memory_access/ \
196	195	-I$(atomisp)/pci/hive_isp_css_shared/ \
197	196	-I$(atomisp)/pci/hive_isp_css_shared/host/ \
198	197	-I$(atomisp)/pci/isp/kernels/ \
@@ -311,9 +310,7 @@ INCLUDES += \ · 112 unmodified lines
311	310	-I$(atomisp)/pci/runtime/tagger/interface/
312	311
313	312	INCLUDES_byt += \
314		− -I$(atomisp)/pci/css_2400_system/ \
315	313	-I$(atomisp)/pci/css_2400_system/hive/ \
316		− -I$(atomisp)/pci/css_2400_system/hrt/ \
317	314
318	315	INCLUDES_cht += \
319	316	-I$(atomisp)/pci/css_2401_system/ \
@@ -321,7 +318,6 @@ INCLUDES_cht += \ · 1 unmodified line
321	318	-I$(atomisp)/pci/css_2401_system/hive/ \
322	319	-I$(atomisp)/pci/css_2401_system/hrt/ \
323	320
324		−# -I$(atomisp)/pci/css_2401_system/hrt/ \
325	321	# -I$(atomisp)/pci/css_2401_system/hive_isp_css_2401_system_generated/ \
326	322
327	323	DEFINES := -DHRT_HW -DHRT_ISP_CSS_CUSTOM_HOST -DHRT_USE_VIR_ADDRS -D__HOST__

drivers/staging/media/atomisp/i2c/atomisp-ov2680.c+3−3

@@ -495,11 +495,11 @@ static int ov2680_h_flip(struct v4l2_subdev *sd, s32 value) · 494 unmodified lines
495	495	ret = ov2680_read_reg(client, 1, OV2680_MIRROR_REG, &val);
496	496	if (ret)
497	497	return ret;
498		− if (value) {
	498	+ if (value)
499	499	val \|= OV2680_FLIP_MIRROR_BIT_ENABLE;
500		− } else {
	500	+ else
501	501	val &= ~OV2680_FLIP_MIRROR_BIT_ENABLE;
502		− }
	502	+
503	503	ret = ov2680_write_reg(client, 1,
504	504	OV2680_MIRROR_REG, val);
505	505	if (ret)

drivers/staging/media/atomisp/i2c/ov5693/atomisp-ov5693.c+4−2

@@ -1899,7 +1899,7 @@ static int ov5693_probe(struct i2c_client *client) · 1898 unmodified lines
1899	1899	{
1900	1900	struct ov5693_device *dev;
1901	1901	int i2c;
1902		− int ret = 0;
	1902	+ int ret;
1903	1903	void *pdata;
1904	1904	unsigned int i;
1905	1905
@@ -1929,8 +1929,10 @@ static int ov5693_probe(struct i2c_client *client) · 23 unmodified lines
1929	1929	pdata = gmin_camera_platform_data(&dev->sd,
1930	1930	ATOMISP_INPUT_FORMAT_RAW_10,
1931	1931	atomisp_bayer_order_bggr);
1932		− if (!pdata)
	1932	+ if (!pdata) {
	1933	+ ret = -EINVAL;
1933	1934	goto out_free;
	1935	+ }
1934	1936
1935	1937	ret = ov5693_s_config(&dev->sd, client->irq, pdata);
1936	1938	if (ret)

drivers/staging/media/atomisp/include/linux/atomisp_platform.h+1−0

@@ -250,6 +250,7 @@ const struct atomisp_camera_caps *atomisp_get_default_camera_caps(void); · 249 unmodified lines
250	250	#define IS_MFLD __IS_SOC(INTEL_FAM6_ATOM_SALTWELL_MID)
251	251	#define IS_BYT __IS_SOC(INTEL_FAM6_ATOM_SILVERMONT)
252	252	#define IS_CHT __IS_SOC(INTEL_FAM6_ATOM_AIRMONT)
	253	+#define IS_MRFD __IS_SOC(INTEL_FAM6_ATOM_SILVERMONT_MID)
253	254	#define IS_MOFD __IS_SOC(INTEL_FAM6_ATOM_AIRMONT_MID)
254	255
255	256	/* Both CHT and MOFD come with ISP2401 */

drivers/staging/media/atomisp/pci/atomisp-regs.h+0−3

@@ -20,9 +20,6 @@ · 19 unmodified lines
20	20	#define ATOMISP_REGS_H
21	21
22	22	/* common register definitions */
23		−#define PUNIT_PORT 0x04
24		−#define CCK_PORT 0x14
25		−
26	23	#define PCICMDSTS 0x01
27	24	#define INTR 0x0f
28	25	#define MSI_CAPID 0x24

drivers/staging/media/atomisp/pci/atomisp_acc.c+2−2

@@ -355,11 +355,11 @@ int atomisp_acc_map(struct atomisp_sub_device asd, struct atomisp_acc_map map) · 354 unmodified lines
355	355
356	356	pgnr = DIV_ROUND_UP(map->length, PAGE_SIZE);
357	357	if (pgnr < ((PAGE_ALIGN(map->length)) >> PAGE_SHIFT)) {
358		− dev_err(atomisp_dev,
	358	+ dev_err(asd->isp->dev,
359	359	"user space memory size is less than the expected size..\n");
360	360	return -ENOMEM;
361	361	} else if (pgnr > ((PAGE_ALIGN(map->length)) >> PAGE_SHIFT)) {
362		− dev_err(atomisp_dev,
	362	+ dev_err(asd->isp->dev,
363	363	"user space memory size is large than the expected size..\n");
364	364	return -ENOMEM;
365	365	}

drivers/staging/media/atomisp/pci/atomisp_cmd.c+32−27

@@ -21,6 +21,7 @@ · 20 unmodified lines
21	21	#include <linux/firmware.h>
22	22	#include <linux/pci.h>
23	23	#include <linux/interrupt.h>
	24	+#include <linux/io.h>
24	25	#include <linux/kernel.h>
25	26	#include <linux/kfifo.h>
26	27	#include <linux/pm_runtime.h>
@@ -109,7 +110,7 @@ struct atomisp_acc_pipe atomisp_to_acc_pipe(struct video_device dev) · 82 unmodified lines
109	110
110	111	static unsigned short atomisp_get_sensor_fps(struct atomisp_sub_device *asd)
111	112	{
112		− struct v4l2_subdev_frame_interval fi;
	113	+ struct v4l2_subdev_frame_interval fi = { 0 };
113	114	struct atomisp_device *isp = asd->isp;
114	115
115	116	unsigned short fps = 0;
@@ -206,6 +207,7 @@ int atomisp_freq_scaling(struct atomisp_device *isp, · 90 unmodified lines
206	207	enum atomisp_dfs_mode mode,
207	208	bool force)
208	209	{
	210	+ struct pci_dev *pdev = to_pci_dev(isp->dev);
209	211	/* FIXME! Only use subdev[0] status yet */
210	212	struct atomisp_sub_device *asd = &isp->asd[0];
211	213	const struct atomisp_dfs_config *dfs;
@@ -219,7 +221,7 @@ int atomisp_freq_scaling(struct atomisp_device *isp, · 7 unmodified lines
219	221	return -EINVAL;
220	222	}
221	223
222		− if ((isp->pdev->device & ATOMISP_PCI_DEVICE_SOC_MASK) ==
	224	+ if ((pdev->device & ATOMISP_PCI_DEVICE_SOC_MASK) ==
223	225	ATOMISP_PCI_DEVICE_SOC_CHT && ATOMISP_USE_YUVPP(asd))
224	226	isp->dfs = &dfs_config_cht_soc;
225	227
@@ -357,39 +359,41 @@ static void clear_isp_irq(enum hrt_isp_css_irq irq) · 131 unmodified lines
357	359	irq_clear_all(IRQ0_ID);
358	360	}
359	361
360		−void atomisp_msi_irq_init(struct atomisp_device isp, struct pci_dev dev)
	362	+void atomisp_msi_irq_init(struct atomisp_device *isp)
361	363	{
	364	+ struct pci_dev *pdev = to_pci_dev(isp->dev);
362	365	u32 msg32;
363	366	u16 msg16;
364	367
365		− pci_read_config_dword(dev, PCI_MSI_CAPID, &msg32);
	368	+ pci_read_config_dword(pdev, PCI_MSI_CAPID, &msg32);
366	369	msg32 \|= 1 << MSI_ENABLE_BIT;
367		− pci_write_config_dword(dev, PCI_MSI_CAPID, msg32);
	370	+ pci_write_config_dword(pdev, PCI_MSI_CAPID, msg32);
368	371
369	372	msg32 = (1 << INTR_IER) \| (1 << INTR_IIR);
370		− pci_write_config_dword(dev, PCI_INTERRUPT_CTRL, msg32);
	373	+ pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, msg32);
371	374
372		− pci_read_config_word(dev, PCI_COMMAND, &msg16);
	375	+ pci_read_config_word(pdev, PCI_COMMAND, &msg16);
373	376	msg16 \|= (PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER \|
374	377	PCI_COMMAND_INTX_DISABLE);
375		− pci_write_config_word(dev, PCI_COMMAND, msg16);
	378	+ pci_write_config_word(pdev, PCI_COMMAND, msg16);
376	379	}
377	380
378		−void atomisp_msi_irq_uninit(struct atomisp_device isp, struct pci_dev dev)
	381	+void atomisp_msi_irq_uninit(struct atomisp_device *isp)
379	382	{
	383	+ struct pci_dev *pdev = to_pci_dev(isp->dev);
380	384	u32 msg32;
381	385	u16 msg16;
382	386
383		− pci_read_config_dword(dev, PCI_MSI_CAPID, &msg32);
	387	+ pci_read_config_dword(pdev, PCI_MSI_CAPID, &msg32);
384	388	msg32 &= ~(1 << MSI_ENABLE_BIT);
385		− pci_write_config_dword(dev, PCI_MSI_CAPID, msg32);
	389	+ pci_write_config_dword(pdev, PCI_MSI_CAPID, msg32);
386	390
387	391	msg32 = 0x0;
388		− pci_write_config_dword(dev, PCI_INTERRUPT_CTRL, msg32);
	392	+ pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, msg32);
389	393
390		− pci_read_config_word(dev, PCI_COMMAND, &msg16);
	394	+ pci_read_config_word(pdev, PCI_COMMAND, &msg16);
391	395	msg16 &= ~(PCI_COMMAND_MASTER);
392		− pci_write_config_word(dev, PCI_COMMAND, msg16);
	396	+ pci_write_config_word(pdev, PCI_COMMAND, msg16);
393	397	}
394	398
395	399	static void atomisp_sof_event(struct atomisp_sub_device *asd)
@@ -480,11 +484,12 @@ static void print_csi_rx_errors(enum mipi_port_id port, · 84 unmodified lines
480	484	/* Clear irq reg */
481	485	static void clear_irq_reg(struct atomisp_device *isp)
482	486	{
	487	+ struct pci_dev *pdev = to_pci_dev(isp->dev);
483	488	u32 msg_ret;
484	489
485		− pci_read_config_dword(isp->pdev, PCI_INTERRUPT_CTRL, &msg_ret);
	490	+ pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &msg_ret);
486	491	msg_ret \|= 1 << INTR_IIR;
487		− pci_write_config_dword(isp->pdev, PCI_INTERRUPT_CTRL, msg_ret);
	492	+ pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, msg_ret);
488	493	}
489	494
490	495	static struct atomisp_sub_device *
@@ -665,11 +670,10 @@ bool atomisp_buffers_queued_pipe(struct atomisp_video_pipe *pipe) · 174 unmodified lines
665	670	void dump_sp_dmem(struct atomisp_device *isp, unsigned int addr,
666	671	unsigned int size)
667	672	{
668		− u32 __iomem *io_virt_addr;
669	673	unsigned int data = 0;
670	674	unsigned int size32 = DIV_ROUND_UP(size, sizeof(u32));
671	675
672		− dev_dbg(isp->dev, "atomisp_io_base:%p\n", atomisp_io_base);
	676	+ dev_dbg(isp->dev, "atomisp mmio base: %p\n", isp->base);
673	677	dev_dbg(isp->dev, "%s, addr:0x%x, size: %d, size32: %d\n", __func__,
674	678	addr, size, size32);
675	679	if (size32 * 4 + addr > 0x4000) {
@@ -678,13 +682,12 @@ void dump_sp_dmem(struct atomisp_device *isp, unsigned int addr, · 2 unmodified lines
678	682	return;
679	683	}
680	684	addr += SP_DMEM_BASE;
681		− io_virt_addr = atomisp_io_base + (addr & 0x003FFFFF);
	685	+ addr &= 0x003FFFFF;
682	686	do {
683		− data = *io_virt_addr;
	687	+ data = readl(isp->base + addr);
684	688	dev_dbg(isp->dev, "%s, \t [0x%x]:0x%x\n", __func__, addr, data);
685		− io_virt_addr += sizeof(u32);
686		− size32 -= 1;
687		− } while (size32 > 0);
	689	+ addr += sizeof(u32);
	690	+ } while (--size32);
688	691	}
689	692
690	693	static struct videobuf_buffer *atomisp_css_frame_to_vbuf(
@@ -1289,6 +1292,7 @@ void atomisp_delayed_init_work(struct work_struct *work) · 598 unmodified lines
1289	1292
1290	1293	static void __atomisp_css_recover(struct atomisp_device *isp, bool isp_timeout)
1291	1294	{
	1295	+ struct pci_dev *pdev = to_pci_dev(isp->dev);
1292	1296	enum ia_css_pipe_id css_pipe_id;
1293	1297	bool stream_restart[MAX_STREAM_NUM] = {0};
1294	1298	bool depth_mode = false;
@@ -1372,8 +1376,8 @@ static void __atomisp_css_recover(struct atomisp_device *isp, bool isp_timeout) · 77 unmodified lines
1372	1376	clear_isp_irq(hrt_isp_css_irq_sp);
1373	1377
1374	1378	/* Set the SRSE to 3 before resetting */
1375		− pci_write_config_dword(isp->pdev, PCI_I_CONTROL, isp->saved_regs.i_control \|
1376		− MRFLD_PCI_I_CONTROL_SRSE_RESET_MASK);
	1379	+ pci_write_config_dword(pdev, PCI_I_CONTROL,
	1380	+ isp->saved_regs.i_control \| MRFLD_PCI_I_CONTROL_SRSE_RESET_MASK);
1377	1381
1378	1382	/* reset ISP and restore its state */
1379	1383	isp->isp_timeout = true;
@@ -6158,6 +6162,7 @@ out: · 4778 unmodified lines
6158	6162	/Turn off ISP dphy /
6159	6163	int atomisp_ospm_dphy_down(struct atomisp_device *isp)
6160	6164	{
	6165	+ struct pci_dev *pdev = to_pci_dev(isp->dev);
6161	6166	unsigned long flags;
6162	6167	u32 reg;
6163	6168
@@ -6179,9 +6184,9 @@ done: · 15 unmodified lines
6179	6184	* MRFLD HW design need all CSI ports are disabled before
6180	6185	* powering down the IUNIT.
6181	6186	*/
6182		− pci_read_config_dword(isp->pdev, MRFLD_PCI_CSI_CONTROL, &reg);
	6187	+ pci_read_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, &reg);
6183	6188	reg \|= MRFLD_ALL_CSI_PORTS_OFF_MASK;
6184		− pci_write_config_dword(isp->pdev, MRFLD_PCI_CSI_CONTROL, reg);
	6189	+ pci_write_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, reg);
6185	6190	return 0;
6186	6191	}
6187	6192

drivers/staging/media/atomisp/pci/atomisp_cmd.h+2−2

@@ -68,8 +68,8 @@ bool atomisp_buffers_queued_pipe(struct atomisp_video_pipe *pipe); · 67 unmodified lines
68	68	/*
69	69	* Interrupt functions
70	70	*/
71		−void atomisp_msi_irq_init(struct atomisp_device isp, struct pci_dev dev);
72		−void atomisp_msi_irq_uninit(struct atomisp_device isp, struct pci_dev dev);
	71	+void atomisp_msi_irq_init(struct atomisp_device *isp);
	72	+void atomisp_msi_irq_uninit(struct atomisp_device *isp);
73	73	void atomisp_wdt_work(struct work_struct *work);
74	74	void atomisp_wdt(struct timer_list *t);
75	75	void atomisp_setup_flash(struct atomisp_sub_device *asd);

drivers/staging/media/atomisp/pci/atomisp_compat.h+0−2

@@ -29,8 +29,6 @@ struct atomisp_sub_device; · 28 unmodified lines
29	29	struct video_device;
30	30	enum atomisp_input_stream_id;
31	31
32		−extern void __iomem *atomisp_io_base;
33		−
34	32	struct atomisp_metadata_buf {
35	33	struct ia_css_metadata *metadata;
36	34	void *md_vptr;

drivers/staging/media/atomisp/pci/atomisp_compat_css20.c+34−36

@@ -33,13 +33,12 @@ · 32 unmodified lines
33	33	#include "atomisp_ioctl.h"
34	34	#include "atomisp_acc.h"
35	35
36		−#include <asm/intel-mid.h>
37		−
38	36	#include "ia_css_debug.h"
39	37	#include "ia_css_isp_param.h"
40	38	#include "sh_css_hrt.h"
41	39	#include "ia_css_isys.h"
42	40
	41	+#include <linux/io.h>
43	42	#include <linux/pm_runtime.h>
44	43
45	44	/* Assume max number of ACC stages */
@@ -69,92 +68,94 @@ struct bayer_ds_factor { · 23 unmodified lines
69	68
70	69	static void atomisp_css2_hw_store_8(hrt_address addr, uint8_t data)
71	70	{
72		− s8 __iomem *io_virt_addr = atomisp_io_base + (addr & 0x003FFFFF);
	71	+ struct atomisp_device *isp = dev_get_drvdata(atomisp_dev);
73	72	unsigned long flags;
74	73
75	74	spin_lock_irqsave(&mmio_lock, flags);
76		− *io_virt_addr = data;
	75	+ writeb(data, isp->base + (addr & 0x003FFFFF));
77	76	spin_unlock_irqrestore(&mmio_lock, flags);
78	77	}
79	78
80	79	static void atomisp_css2_hw_store_16(hrt_address addr, uint16_t data)
81	80	{
82		− s16 __iomem *io_virt_addr = atomisp_io_base + (addr & 0x003FFFFF);
	81	+ struct atomisp_device *isp = dev_get_drvdata(atomisp_dev);
83	82	unsigned long flags;
84	83
85	84	spin_lock_irqsave(&mmio_lock, flags);
86		− *io_virt_addr = data;
	85	+ writew(data, isp->base + (addr & 0x003FFFFF));
87	86	spin_unlock_irqrestore(&mmio_lock, flags);
88	87	}
89	88
90	89	void atomisp_css2_hw_store_32(hrt_address addr, uint32_t data)
91	90	{
92		− s32 __iomem *io_virt_addr = atomisp_io_base + (addr & 0x003FFFFF);
	91	+ struct atomisp_device *isp = dev_get_drvdata(atomisp_dev);
93	92	unsigned long flags;
94	93
95	94	spin_lock_irqsave(&mmio_lock, flags);
96		− *io_virt_addr = data;
	95	+ writel(data, isp->base + (addr & 0x003FFFFF));
97	96	spin_unlock_irqrestore(&mmio_lock, flags);
98	97	}
99	98
100	99	static uint8_t atomisp_css2_hw_load_8(hrt_address addr)
101	100	{
102		− s8 __iomem *io_virt_addr = atomisp_io_base + (addr & 0x003FFFFF);
	101	+ struct atomisp_device *isp = dev_get_drvdata(atomisp_dev);
103	102	unsigned long flags;
104	103	u8 ret;
105	104
106	105	spin_lock_irqsave(&mmio_lock, flags);
107		− ret = *io_virt_addr;
	106	+ ret = readb(isp->base + (addr & 0x003FFFFF));
108	107	spin_unlock_irqrestore(&mmio_lock, flags);
109	108	return ret;
110	109	}
111	110
112	111	static uint16_t atomisp_css2_hw_load_16(hrt_address addr)
113	112	{
114		− s16 __iomem *io_virt_addr = atomisp_io_base + (addr & 0x003FFFFF);
	113	+ struct atomisp_device *isp = dev_get_drvdata(atomisp_dev);
115	114	unsigned long flags;
116	115	u16 ret;
117	116
118	117	spin_lock_irqsave(&mmio_lock, flags);
119		− ret = *io_virt_addr;
	118	+ ret = readw(isp->base + (addr & 0x003FFFFF));
120	119	spin_unlock_irqrestore(&mmio_lock, flags);
121	120	return ret;
122	121	}
123	122
124	123	static uint32_t atomisp_css2_hw_load_32(hrt_address addr)
125	124	{
126		− s32 __iomem *io_virt_addr = atomisp_io_base + (addr & 0x003FFFFF);
	125	+ struct atomisp_device *isp = dev_get_drvdata(atomisp_dev);
127	126	unsigned long flags;
128	127	u32 ret;
129	128
130	129	spin_lock_irqsave(&mmio_lock, flags);
131		− ret = *io_virt_addr;
	130	+ ret = readl(isp->base + (addr & 0x003FFFFF));
132	131	spin_unlock_irqrestore(&mmio_lock, flags);
133	132	return ret;
134	133	}
135	134
136		−static void atomisp_css2_hw_store(hrt_address addr,
137		− const void *from, uint32_t n)
	135	+static void atomisp_css2_hw_store(hrt_address addr, const void *from, uint32_t n)
138	136	{
139		− s8 __iomem *io_virt_addr = atomisp_io_base + (addr & 0x003FFFFF);
	137	+ struct atomisp_device *isp = dev_get_drvdata(atomisp_dev);
140	138	unsigned long flags;
141	139	unsigned int i;
142	140
	141	+ addr &= 0x003FFFFF;
143	142	spin_lock_irqsave(&mmio_lock, flags);
144		− for (i = 0; i < n; i++, io_virt_addr++, from++)
145		− io_virt_addr = (s8 *)from;
	143	+ for (i = 0; i < n; i++, from++)
	144	+ writeb((s8 )from, isp->base + addr + i);
	145	+
146	146	spin_unlock_irqrestore(&mmio_lock, flags);
147	147	}
148	148
149	149	static void atomisp_css2_hw_load(hrt_address addr, void *to, uint32_t n)
150	150	{
151		− s8 __iomem *io_virt_addr = atomisp_io_base + (addr & 0x003FFFFF);
	151	+ struct atomisp_device *isp = dev_get_drvdata(atomisp_dev);
152	152	unsigned long flags;
153	153	unsigned int i;
154	154
	155	+ addr &= 0x003FFFFF;
155	156	spin_lock_irqsave(&mmio_lock, flags);
156		− for (i = 0; i < n; i++, to++, io_virt_addr++)
157		− (s8 )to = *io_virt_addr;
	157	+ for (i = 0; i < n; i++, to++)
	158	+ (s8 )to = readb(isp->base + addr + i);
158	159	spin_unlock_irqrestore(&mmio_lock, flags);
159	160	}
160	161
@@ -181,10 +182,10 @@ void atomisp_load_uint32(hrt_address addr, uint32_t *data) · 20 unmodified lines
181	182	*data = atomisp_css2_hw_load_32(addr);
182	183	}
183	184
184		−static int hmm_get_mmu_base_addr(unsigned int *mmu_base_addr)
	185	+static int hmm_get_mmu_base_addr(struct device dev, unsigned int mmu_base_addr)
185	186	{
186	187	if (!sh_mmu_mrfld.get_pd_base) {
187		− dev_err(atomisp_dev, "get mmu base address failed.\n");
	188	+ dev_err(dev, "get mmu base address failed.\n");
188	189	return -EINVAL;
189	190	}
190	191
@@ -839,7 +840,7 @@ int atomisp_css_init(struct atomisp_device *isp) · 648 unmodified lines
839	840	int ret;
840	841	int err;
841	842
842		− ret = hmm_get_mmu_base_addr(&mmu_base_addr);
	843	+ ret = hmm_get_mmu_base_addr(isp->dev, &mmu_base_addr);
843	844	if (ret)
844	845	return ret;
845	846
@@ -941,7 +942,7 @@ int atomisp_css_resume(struct atomisp_device *isp) · 95 unmodified lines
941	942	unsigned int mmu_base_addr;
942	943	int ret;
943	944
944		− ret = hmm_get_mmu_base_addr(&mmu_base_addr);
	945	+ ret = hmm_get_mmu_base_addr(isp->dev, &mmu_base_addr);
945	946	if (ret) {
946	947	dev_err(isp->dev, "get base address error.\n");
947	948	return -EINVAL;
@@ -1966,8 +1967,7 @@ void atomisp_css_input_set_mode(struct atomisp_sub_device *asd, · 1018 unmodified lines
1966	1967	true,
1967	1968	0x13000,
1968	1969	&size_mem_words) != 0) {
1969		− if (intel_mid_identify_cpu() ==
1970		− INTEL_MID_CPU_CHIP_TANGIER)
	1970	+ if (IS_MRFD)
1971	1971	size_mem_words = CSS_MIPI_FRAME_BUFFER_SIZE_2;
1972	1972	else
1973	1973	size_mem_words = CSS_MIPI_FRAME_BUFFER_SIZE_1;
@@ -2414,13 +2414,13 @@ static void __configure_preview_pp_input(struct atomisp_sub_device *asd, · 440 unmodified lines
2414	2414	struct ia_css_resolution *effective_res =
2415	2415	&stream_config->input_config.effective_res;
2416	2416
2417		− const struct bayer_ds_factor bds_fct[] = {{2, 1}, {3, 2}, {5, 4} };
	2417	+ static const struct bayer_ds_factor bds_fct[] = {{2, 1}, {3, 2}, {5, 4} };
2418	2418	/*
2419	2419	* BZ201033: YUV decimation factor of 4 causes couple of rightmost
2420	2420	* columns to be shaded. Remove this factor to work around the CSS bug.
2421	2421	* const unsigned int yuv_dec_fct[] = {4, 2};
2422	2422	*/
2423		− const unsigned int yuv_dec_fct[] = { 2 };
	2423	+ static const unsigned int yuv_dec_fct[] = { 2 };
2424	2424	unsigned int i;
2425	2425
2426	2426	if (width == 0 && height == 0)
@@ -2540,7 +2540,7 @@ static void __configure_video_pp_input(struct atomisp_sub_device *asd, · 113 unmodified lines
2540	2540	struct ia_css_resolution *effective_res =
2541	2541	&stream_config->input_config.effective_res;
2542	2542
2543		− const struct bayer_ds_factor bds_factors[] = {
	2543	+ static const struct bayer_ds_factor bds_factors[] = {
2544	2544	{8, 1}, {6, 1}, {4, 1}, {3, 1}, {2, 1}, {3, 2}
2545	2545	};
2546	2546	unsigned int i;
@@ -4337,7 +4337,7 @@ static const char * const fw_acc_type_name[] = { · 1790 unmodified lines
4337	4337	[IA_CSS_ACC_STANDALONE] = "Stand-alone acceleration",
4338	4338	};
4339	4339
4340		−int atomisp_css_dump_blob_infor(void)
	4340	+int atomisp_css_dump_blob_infor(struct atomisp_device *isp)
4341	4341	{
4342	4342	struct ia_css_blob_descr *bd = sh_css_blob_info;
4343	4343	unsigned int i, nm = sh_css_num_binaries;
@@ -4354,8 +4354,7 @@ int atomisp_css_dump_blob_infor(void) · 10 unmodified lines
4354	4354	for (i = 0; i < sh_css_num_binaries - NUM_OF_SPS; i++) {
4355	4355	switch (bd[i].header.type) {
4356	4356	case ia_css_isp_firmware:
4357		− dev_dbg(atomisp_dev,
4358		− "Num%2d type %s (%s), binary id is %2d, name is %s\n",
	4357	+ dev_dbg(isp->dev, "Num%2d type %s (%s), binary id is %2d, name is %s\n",
4359	4358	i + NUM_OF_SPS,
4360	4359	fw_type_name[bd[i].header.type],
4361	4360	fw_acc_type_name[bd[i].header.info.isp.type],
@@ -4363,8 +4362,7 @@ int atomisp_css_dump_blob_infor(void) · 1 unmodified line
4363	4362	bd[i].name);
4364	4363	break;
4365	4364	default:
4366		− dev_dbg(atomisp_dev,
4367		− "Num%2d type %s, name is %s\n",
	4365	+ dev_dbg(isp->dev, "Num%2d type %s, name is %s\n",
4368	4366	i + NUM_OF_SPS, fw_type_name[bd[i].header.type],
4369	4367	bd[i].name);
4370	4368	}

drivers/staging/media/atomisp/pci/atomisp_compat_css20.h+1−1

@@ -153,7 +153,7 @@ int atomisp_css_debug_dump_isp_binary(void); · 152 unmodified lines
153	153
154	154	int atomisp_css_dump_sp_raw_copy_linecount(bool reduced);
155	155
156		−int atomisp_css_dump_blob_infor(void);
	156	+int atomisp_css_dump_blob_infor(struct atomisp_device *isp);
157	157
158	158	void atomisp_css_set_isp_config_id(struct atomisp_sub_device *asd,
159	159	uint32_t isp_config_id);

drivers/staging/media/atomisp/pci/atomisp_drvfs.c+7−7

@@ -62,9 +62,9 @@ static inline int iunit_dump_dbgopt(struct atomisp_device *isp, · 61 unmodified lines
62	62
63	63	if (opt & OPTION_VALID) {
64	64	if (opt & OPTION_BIN_LIST) {
65		− ret = atomisp_css_dump_blob_infor();
	65	+ ret = atomisp_css_dump_blob_infor(isp);
66	66	if (ret) {
67		− dev_err(atomisp_dev, "%s dump blob infor err[ret:%d]\n",
	67	+ dev_err(isp->dev, "%s dump blob infor err[ret:%d]\n",
68	68	__func__, ret);
69	69	goto opt_err;
70	70	}
@@ -76,7 +76,7 @@ static inline int iunit_dump_dbgopt(struct atomisp_device *isp, · 5 unmodified lines
76	76	atomisp_css_debug_dump_isp_binary();
77	77	} else {
78	78	ret = -EPERM;
79		− dev_err(atomisp_dev, "%s dump running bin err[ret:%d]\n",
	79	+ dev_err(isp->dev, "%s dump running bin err[ret:%d]\n",
80	80	__func__, ret);
81	81	goto opt_err;
82	82	}
@@ -86,8 +86,7 @@ static inline int iunit_dump_dbgopt(struct atomisp_device *isp, · 3 unmodified lines
86	86	hmm_show_mem_stat(__func__, __LINE__);
87	87	} else {
88	88	ret = -EINVAL;
89		− dev_err(atomisp_dev, "%s dump nothing[ret=%d]\n", __func__,
90		− ret);
	89	+ dev_err(isp->dev, "%s dump nothing[ret=%d]\n", __func__, ret);
91	90	}
92	91
93	92	opt_err:
@@ -185,8 +184,9 @@ static void iunit_drvfs_remove_files(struct device_driver *drv) · 91 unmodified lines
185	184	driver_remove_file(drv, &iunit_drvfs_attrs[i]);
186	185	}
187	186
188		−int atomisp_drvfs_init(struct device_driver drv, struct atomisp_device isp)
	187	+int atomisp_drvfs_init(struct atomisp_device *isp)
189	188	{
	189	+ struct device_driver *drv = isp->dev->driver;
190	190	int ret;
191	191
192	192	iunit_debug.isp = isp;
@@ -194,7 +194,7 @@ int atomisp_drvfs_init(struct device_driver drv, struct atomisp_device isp) · 1 unmodified line
194	194
195	195	ret = iunit_drvfs_create_files(iunit_debug.drv);
196	196	if (ret) {
197		− dev_err(atomisp_dev, "drvfs_create_files error: %d\n", ret);
	197	+ dev_err(isp->dev, "drvfs_create_files error: %d\n", ret);
198	198	iunit_drvfs_remove_files(iunit_debug.drv);
199	199	}
200	200

drivers/staging/media/atomisp/pci/atomisp_drvfs.h+1−1

@@ -19,7 +19,7 @@ · 18 unmodified lines
19	19	#ifndef __ATOMISP_DRVFS_H__
20	20	#define __ATOMISP_DRVFS_H__
21	21
22		−int atomisp_drvfs_init(struct device_driver drv, struct atomisp_device isp);
	22	+int atomisp_drvfs_init(struct atomisp_device *isp);
23	23	void atomisp_drvfs_exit(void);
24	24
25	25	#endif /* __ATOMISP_DRVFS_H__ */

drivers/staging/media/atomisp/pci/atomisp_gmin_platform.c+351−186

@@ -26,6 +26,9 @@ enum clock_rate { · 25 unmodified lines
26	26	#define CLK_RATE_19_2MHZ 19200000
27	27	#define CLK_RATE_25_0MHZ 25000000
28	28
	29	+/* Valid clock number range from 0 to 5 */
	30	+#define MAX_CLK_COUNT 5
	31	+
29	32	/* X-Powers AXP288 register set */
30	33	#define ALDO1_SEL_REG 0x28
31	34	#define ALDO1_CTRL3_REG 0x13
@@ -61,9 +64,7 @@ enum clock_rate { · 29 unmodified lines
61	64
62	65	struct gmin_subdev {
63	66	struct v4l2_subdev *subdev;
64		− int clock_num;
65	67	enum clock_rate clock_src;
66		− bool clock_on;
67	68	struct clk *pmc_clk;
68	69	struct gpio_desc *gpio0;
69	70	struct gpio_desc *gpio1;
@@ -75,11 +76,16 @@ struct gmin_subdev { · 5 unmodified lines
75	76	unsigned int csi_lanes;
76	77	enum atomisp_input_format csi_fmt;
77	78	enum atomisp_bayer_order csi_bayer;
	79	+
	80	+ bool clock_on;
78	81	bool v1p8_on;
79	82	bool v2p8_on;
80	83	bool v1p2_on;
81	84	bool v2p8_vcm_on;
82	85
	86	+ int v1p8_gpio;
	87	+ int v2p8_gpio;
	88	+
83	89	u8 pwm_i2c_addr;
84	90
85	91	/* For PMIC AXP */
@@ -90,9 +96,9 @@ struct gmin_subdev { · 4 unmodified lines
90	96	static struct gmin_subdev gmin_subdevs[MAX_SUBDEVS];
91	97
92	98	/* ACPI HIDs for the PMICs that could be used by this driver */
93		−#define PMIC_ACPI_AXP "INT33F4:00" /* XPower AXP288 PMIC */
94		−#define PMIC_ACPI_TI "INT33F5:00" /* Dollar Cove TI PMIC */
95		−#define PMIC_ACPI_CRYSTALCOVE "INT33FD:00" /* Crystal Cove PMIC */
	99	+#define PMIC_ACPI_AXP "INT33F4" /* XPower AXP288 PMIC */
	100	+#define PMIC_ACPI_TI "INT33F5" /* Dollar Cove TI PMIC */
	101	+#define PMIC_ACPI_CRYSTALCOVE "INT33FD" /* Crystal Cove PMIC */
96	102
97	103	#define PMIC_PLATFORM_TI "intel_soc_pmic_chtdc_ti"
98	104
@@ -105,7 +111,7 @@ static enum { · 6 unmodified lines
105	111	} pmic_id;
106	112
107	113	static const char *pmic_name[] = {
108		− [PMIC_UNSET] = "unset",
	114	+ [PMIC_UNSET] = "ACPI device PM",
109	115	[PMIC_REGULATOR] = "regulator driver",
110	116	[PMIC_AXP] = "XPower AXP288 PMIC",
111	117	[PMIC_TI] = "Dollar Cove TI PMIC",
@@ -119,24 +125,6 @@ static const struct atomisp_platform_data pdata = { · 7 unmodified lines
119	125	.subdevs = pdata_subdevs,
120	126	};
121	127
122		−/*
123		− * Something of a hack. The ECS E7 board drives camera 2.8v from an
124		− * external regulator instead of the PMIC. There's a gmin_CamV2P8
125		− * config variable that specifies the GPIO to handle this particular
126		− * case, but this needs a broader architecture for handling camera
127		− * power.
128		− */
129		−enum { V2P8_GPIO_UNSET = -2, V2P8_GPIO_NONE = -1 };
130		−static int v2p8_gpio = V2P8_GPIO_UNSET;
131		−
132		−/*
133		− * Something of a hack. The CHT RVP board drives camera 1.8v from an
134		− * external regulator instead of the PMIC just like ECS E7 board, see the
135		− * comments above.
136		− */
137		−enum { V1P8_GPIO_UNSET = -2, V1P8_GPIO_NONE = -1 };
138		−static int v1p8_gpio = V1P8_GPIO_UNSET;
139		−
140	128	static LIST_HEAD(vcm_devices);
141	129	static DEFINE_MUTEX(vcm_lock);
142	130
@@ -199,6 +187,8 @@ int atomisp_register_i2c_module(struct v4l2_subdev *subdev, · 56 unmodified lines
199	187	* gmin_subdev struct is already initialized for us.
200	188	*/
201	189	gs = find_gmin_subdev(subdev);
	190	+ if (!gs)
	191	+ return -ENODEV;
202	192
203	193	pdata.subdevs[i].type = type;
204	194	pdata.subdevs[i].port = gs->csi_port;
@@ -294,6 +284,7 @@ static struct gmin_cfg_var mrd7_vars[] = { · 89 unmodified lines
294	284	{"INT33F8:00_CsiFmt", "13"},
295	285	{"INT33F8:00_CsiBayer", "0"},
296	286	{"INT33F8:00_CamClk", "0"},
	287	+
297	288	{"INT33F9:00_CamType", "1"},
298	289	{"INT33F9:00_CsiPort", "0"},
299	290	{"INT33F9:00_CsiLanes", "1"},
@@ -309,6 +300,7 @@ static struct gmin_cfg_var ecs7_vars[] = { · 9 unmodified lines
309	300	{"INT33BE:00_CsiFmt", "13"},
310	301	{"INT33BE:00_CsiBayer", "2"},
311	302	{"INT33BE:00_CamClk", "0"},
	303	+
312	304	{"INT33F0:00_CsiPort", "0"},
313	305	{"INT33F0:00_CsiLanes", "1"},
314	306	{"INT33F0:00_CsiFmt", "13"},
@@ -322,6 +314,7 @@ static struct gmin_cfg_var i8880_vars[] = { · 7 unmodified lines
322	314	{"XXOV2680:00_CsiPort", "1"},
323	315	{"XXOV2680:00_CsiLanes", "1"},
324	316	{"XXOV2680:00_CamClk", "0"},
	317	+
325	318	{"XXGC0310:00_CsiPort", "0"},
326	319	{"XXGC0310:00_CsiLanes", "1"},
327	320	{"XXGC0310:00_CamClk", "1"},
@@ -381,34 +374,27 @@ static const guid_t atomisp_dsm_guid = GUID_INIT(0xdc2f6c4f, 0x045b, 0x4f1d, · 53 unmodified lines
381	374	#define GMIN_PMC_CLK_NAME 14 /* "pmc_plt_clk_[0..5]" */
382	375	static char gmin_pmc_clk_name[GMIN_PMC_CLK_NAME];
383	376
384		−static int gmin_i2c_match_one(struct device dev, const void data)
385		−{
386		− const char *name = data;
387		− struct i2c_client *client;
388		−
389		− if (dev->type != &i2c_client_type)
390		− return 0;
391		−
392		− client = to_i2c_client(dev);
393		−
394		− return (!strcmp(name, client->name));
395		−}
396		−
397	377	static struct i2c_client gmin_i2c_dev_exists(struct device dev, char *name,
398	378	struct i2c_client **client)
399	379	{
	380	+ struct acpi_device *adev;
400	381	struct device *d;
401	382
402		− while ((d = bus_find_device(&i2c_bus_type, NULL, name,
403		− gmin_i2c_match_one))) {
404		− *client = to_i2c_client(d);
405		− dev_dbg(dev, "found '%s' at address 0x%02x, adapter %d\n",
406		− (client)->name, (client)->addr,
407		− (*client)->adapter->nr);
408		− return *client;
409		− }
	383	+ adev = acpi_dev_get_first_match_dev(name, NULL, -1);
	384	+ if (!adev)
	385	+ return NULL;
410	386
411		− return NULL;
	387	+ d = bus_find_device_by_acpi_dev(&i2c_bus_type, adev);
	388	+ acpi_dev_put(adev);
	389	+ if (!d)
	390	+ return NULL;
	391	+
	392	+ *client = i2c_verify_client(d);
	393	+ put_device(d);
	394	+
	395	+ dev_dbg(dev, "found '%s' at address 0x%02x, adapter %d\n",
	396	+ (client)->name, (client)->addr, (*client)->adapter->nr);
	397	+ return *client;
412	398	}
413	399
414	400	static int gmin_i2c_write(struct device *dev, u16 i2c_addr, u8 reg,
@@ -427,94 +413,222 @@ static int gmin_i2c_write(struct device *dev, u16 i2c_addr, u8 reg, · 12 unmodified lines
427	413	"I2C write, addr: 0x%02x, reg: 0x%02x, value: 0x%02x, mask: 0x%02x\n",
428	414	i2c_addr, reg, value, mask);
429	415
430		− ret = intel_soc_pmic_exec_mipi_pmic_seq_element(i2c_addr, reg,
431		− value, mask);
432		−
433		− if (ret == -EOPNOTSUPP) {
	416	+ ret = intel_soc_pmic_exec_mipi_pmic_seq_element(i2c_addr, reg, value, mask);
	417	+ if (ret == -EOPNOTSUPP)
434	418	dev_err(dev,
435	419	"ACPI didn't mapped the OpRegion needed to access I2C address 0x%02x.\n"
436		− "Need to compile the Kernel using CONFIG_*_PMIC_OPREGION settings\n",
	420	+ "Need to compile the kernel using CONFIG_*_PMIC_OPREGION settings\n",
437	421	i2c_addr);
438		− return ret;
439		− }
440	422
441	423	return ret;
442	424	}
443	425
444		−static struct gmin_subdev gmin_subdev_add(struct v4l2_subdev subdev)
	426	+static int atomisp_get_acpi_power(struct device *dev)
445	427	{
446		− struct i2c_client power = NULL, client = v4l2_get_subdevdata(subdev);
447		− struct acpi_device *adev;
448		− acpi_handle handle;
449		− struct device *dev;
450		− int i, ret;
	428	+ char name[5];
	429	+ struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
	430	+ struct acpi_buffer b_name = { sizeof(name), name };
	431	+ union acpi_object package, element;
	432	+ acpi_handle handle = ACPI_HANDLE(dev);
	433	+ acpi_handle rhandle;
	434	+ acpi_status status;
	435	+ int clock_num = -1;
	436	+ int i;
451	437
452		− if (!client)
453		− return NULL;
	438	+ status = acpi_evaluate_object(handle, "_PR0", NULL, &buffer);
	439	+ if (!ACPI_SUCCESS(status))
	440	+ return -1;
454	441
455		− dev = &client->dev;
	442	+ package = buffer.pointer;
456	443
457		− handle = ACPI_HANDLE(dev);
	444	+ if (!buffer.length \|\| !package
	445	+ \|\| package->type != ACPI_TYPE_PACKAGE
	446	+ \|\| !package->package.count)
	447	+ goto fail;
458	448
459		− // FIXME: may need to release resources allocated by acpi_bus_get_device()
460		− if (!handle \|\| acpi_bus_get_device(handle, &adev)) {
461		− dev_err(dev, "Error could not get ACPI device\n");
462		− return NULL;
463		− }
	449	+ for (i = 0; i < package->package.count; i++) {
	450	+ element = &package->package.elements[i];
464	451
465		− dev_info(&client->dev, "%s: ACPI detected it on bus ID=%s, HID=%s\n",
466		− __func__, acpi_device_bid(adev), acpi_device_hid(adev));
	452	+ if (element->type != ACPI_TYPE_LOCAL_REFERENCE)
	453	+ continue;
467	454
468		− if (!pmic_id) {
469		− if (gmin_i2c_dev_exists(dev, PMIC_ACPI_TI, &power))
470		− pmic_id = PMIC_TI;
471		− else if (gmin_i2c_dev_exists(dev, PMIC_ACPI_AXP, &power))
472		− pmic_id = PMIC_AXP;
473		− else if (gmin_i2c_dev_exists(dev, PMIC_ACPI_CRYSTALCOVE, &power))
474		− pmic_id = PMIC_CRYSTALCOVE;
475		− else
476		− pmic_id = PMIC_REGULATOR;
	455	+ rhandle = element->reference.handle;
	456	+ if (!rhandle)
	457	+ goto fail;
	458	+
	459	+ acpi_get_name(rhandle, ACPI_SINGLE_NAME, &b_name);
	460	+
	461	+ dev_dbg(dev, "Found PM resource '%s'\n", name);
	462	+ if (strlen(name) == 4 && !strncmp(name, "CLK", 3)) {
	463	+ if (name[3] >= '0' && name[3] <= '4')
	464	+ clock_num = name[3] - '0';
	465	+#if 0
	466	+ /*
	467	+ * We could abort here, but let's parse all resources,
	468	+ * as this is helpful for debugging purposes
	469	+ */
	470	+ if (clock_num >= 0)
	471	+ break;
	472	+#endif
	473	+ }
477	474	}
478	475
479		− for (i = 0; i < MAX_SUBDEVS && gmin_subdevs[i].subdev; i++)
480		− ;
481		− if (i >= MAX_SUBDEVS)
482		− return NULL;
	476	+fail:
	477	+ ACPI_FREE(buffer.pointer);
	478	+
	479	+ return clock_num;
	480	+}
	481	+
	482	+static u8 gmin_get_pmic_id_and_addr(struct device *dev)
	483	+{
	484	+ struct i2c_client *power;
	485	+ static u8 pmic_i2c_addr;
	486	+
	487	+ if (pmic_id)
	488	+ return pmic_i2c_addr;
	489	+
	490	+ if (gmin_i2c_dev_exists(dev, PMIC_ACPI_TI, &power))
	491	+ pmic_id = PMIC_TI;
	492	+ else if (gmin_i2c_dev_exists(dev, PMIC_ACPI_AXP, &power))
	493	+ pmic_id = PMIC_AXP;
	494	+ else if (gmin_i2c_dev_exists(dev, PMIC_ACPI_CRYSTALCOVE, &power))
	495	+ pmic_id = PMIC_CRYSTALCOVE;
	496	+ else
	497	+ pmic_id = PMIC_REGULATOR;
	498	+
	499	+ pmic_i2c_addr = power ? power->addr : 0;
	500	+ return pmic_i2c_addr;
	501	+}
	502	+
	503	+static int gmin_detect_pmic(struct v4l2_subdev *subdev)
	504	+{
	505	+ struct i2c_client *client = v4l2_get_subdevdata(subdev);
	506	+ struct device *dev = &client->dev;
	507	+ u8 pmic_i2c_addr;
	508	+
	509	+ pmic_i2c_addr = gmin_get_pmic_id_and_addr(dev);
	510	+ dev_info(dev, "gmin: power management provided via %s (i2c addr 0x%02x)\n",
	511	+ pmic_name[pmic_id], pmic_i2c_addr);
	512	+ return pmic_i2c_addr;
	513	+}
	514	+
	515	+static int gmin_subdev_add(struct gmin_subdev *gs)
	516	+{
	517	+ struct i2c_client *client = v4l2_get_subdevdata(gs->subdev);
	518	+ struct device *dev = &client->dev;
	519	+ struct acpi_device *adev = ACPI_COMPANION(dev);
	520	+ int ret, clock_num = -1;
	521	+
	522	+ dev_info(dev, "%s: ACPI path is %pfw\n", __func__, dev_fwnode(dev));
	523	+
	524	+ /WA:CHT requires XTAL clock as PLL is not stable./
	525	+ gs->clock_src = gmin_get_var_int(dev, false, "ClkSrc",
	526	+ VLV2_CLK_PLL_19P2MHZ);
	527	+
	528	+ gs->csi_port = gmin_get_var_int(dev, false, "CsiPort", 0);
	529	+ gs->csi_lanes = gmin_get_var_int(dev, false, "CsiLanes", 1);
	530	+
	531	+ gs->gpio0 = gpiod_get_index(dev, NULL, 0, GPIOD_OUT_LOW);
	532	+ if (IS_ERR(gs->gpio0))
	533	+ gs->gpio0 = NULL;
	534	+ else
	535	+ dev_info(dev, "will handle gpio0 via ACPI\n");
	536	+
	537	+ gs->gpio1 = gpiod_get_index(dev, NULL, 1, GPIOD_OUT_LOW);
	538	+ if (IS_ERR(gs->gpio1))
	539	+ gs->gpio1 = NULL;
	540	+ else
	541	+ dev_info(dev, "will handle gpio1 via ACPI\n");
	542	+
	543	+ /*
	544	+ * Those are used only when there is an external regulator apart
	545	+ * from the PMIC that would be providing power supply, like on the
	546	+ * two cases below:
	547	+ *
	548	+ * The ECS E7 board drives camera 2.8v from an external regulator
	549	+ * instead of the PMIC. There's a gmin_CamV2P8 config variable
	550	+ * that specifies the GPIO to handle this particular case,
	551	+ * but this needs a broader architecture for handling camera power.
	552	+ *
	553	+ * The CHT RVP board drives camera 1.8v from an* external regulator
	554	+ * instead of the PMIC just like ECS E7 board.
	555	+ */
483	556
484		− if (power) {
485		− gmin_subdevs[i].pwm_i2c_addr = power->addr;
	557	+ gs->v1p8_gpio = gmin_get_var_int(dev, true, "V1P8GPIO", -1);
	558	+ gs->v2p8_gpio = gmin_get_var_int(dev, true, "V2P8GPIO", -1);
	559	+
	560	+ /*
	561	+ * FIXME:
	562	+ *
	563	+ * The ACPI handling code checks for the _PR? tables in order to
	564	+ * know what is required to switch the device from power state
	565	+ * D0 (_PR0) up to D3COLD (_PR3).
	566	+ *
	567	+ * The adev->flags.power_manageable is set to true if the device
	568	+ * has a _PR0 table, which can be checked by calling
	569	+ * acpi_device_power_manageable(adev).
	570	+ *
	571	+ * However, this only says that the device can be set to power off
	572	+ * mode.
	573	+ *
	574	+ * At least on the DSDT tables we've seen so far, there's no _PR3,
	575	+ * nor _PS3 (which would have a somewhat similar effect).
	576	+ * So, using ACPI for power management won't work, except if adding
	577	+ * an ACPI override logic somewhere.
	578	+ *
	579	+ * So, at least for the existing devices we know, the check below
	580	+ * will always be false.
	581	+ */
	582	+ if (acpi_device_can_wakeup(adev) &&
	583	+ acpi_device_can_poweroff(adev)) {
486	584	dev_info(dev,
487		− "gmin: power management provided via %s (i2c addr 0x%02x)\n",
488		− pmic_name[pmic_id], power->addr);
489		− } else {
490		− dev_info(dev, "gmin: power management provided via %s\n",
491		− pmic_name[pmic_id]);
	585	+ "gmin: power management provided via device PM\n");
	586	+ return 0;
492	587	}
493	588
494		− gmin_subdevs[i].subdev = subdev;
495		− gmin_subdevs[i].clock_num = gmin_get_var_int(dev, false, "CamClk", 0);
496		− /WA:CHT requires XTAL clock as PLL is not stable./
497		− gmin_subdevs[i].clock_src = gmin_get_var_int(dev, false, "ClkSrc",
498		− VLV2_CLK_PLL_19P2MHZ);
499		− gmin_subdevs[i].csi_port = gmin_get_var_int(dev, false, "CsiPort", 0);
500		− gmin_subdevs[i].csi_lanes = gmin_get_var_int(dev, false, "CsiLanes", 1);
	589	+ /*
	590	+ * The code below is here due to backward compatibility with devices
	591	+ * whose ACPI BIOS may not contain everything that would be needed
	592	+ * in order to set clocks and do power management.
	593	+ */
	594	+
	595	+ /*
	596	+ * According with :
	597	+ * https://github.com/projectceladon/hardware-intel-kernelflinger/blob/master/doc/fastboot.md
	598	+ *
	599	+ * The "CamClk" EFI var is set via fastboot on some Android devices,
	600	+ * and seems to contain the number of the clock used to feed the
	601	+ * sensor.
	602	+ *
	603	+ * On systems with a proper ACPI table, this is given via the _PR0
	604	+ * power resource table. The logic below should first check if there
	605	+ * is a power resource already, falling back to the EFI vars detection
	606	+ * otherwise.
	607	+ */
501	608
502		− /* get PMC clock with clock framework */
503		− snprintf(gmin_pmc_clk_name,
504		− sizeof(gmin_pmc_clk_name),
505		− "%s_%d", "pmc_plt_clk", gmin_subdevs[i].clock_num);
	609	+ /* Try first to use ACPI to get the clock resource */
	610	+ if (acpi_device_power_manageable(adev))
	611	+ clock_num = atomisp_get_acpi_power(dev);
506	612
507		− gmin_subdevs[i].pmc_clk = devm_clk_get(dev, gmin_pmc_clk_name);
508		− if (IS_ERR(gmin_subdevs[i].pmc_clk)) {
509		− ret = PTR_ERR(gmin_subdevs[i].pmc_clk);
	613	+ /* Fall-back use EFI and/or DMI match */
	614	+ if (clock_num < 0)
	615	+ clock_num = gmin_get_var_int(dev, false, "CamClk", 0);
510	616
511		− dev_err(dev,
512		− "Failed to get clk from %s : %d\n",
513		− gmin_pmc_clk_name,
514		− ret);
	617	+ if (clock_num < 0 \|\| clock_num > MAX_CLK_COUNT) {
	618	+ dev_err(dev, "Invalid clock number\n");
	619	+ return -EINVAL;
	620	+ }
515	621
516		− return NULL;
	622	+ snprintf(gmin_pmc_clk_name, sizeof(gmin_pmc_clk_name),
	623	+ "%s_%d", "pmc_plt_clk", clock_num);
	624	+
	625	+ gs->pmc_clk = devm_clk_get(dev, gmin_pmc_clk_name);
	626	+ if (IS_ERR(gs->pmc_clk)) {
	627	+ ret = PTR_ERR(gs->pmc_clk);
	628	+ dev_err(dev, "Failed to get clk from %s: %d\n", gmin_pmc_clk_name, ret);
	629	+ return ret;
517	630	}
	631	+ dev_info(dev, "Will use CLK%d (%s)\n", clock_num, gmin_pmc_clk_name);
518	632
519	633	/*
520	634	* The firmware might enable the clock at
@@ -526,25 +640,17 @@ static struct gmin_subdev gmin_subdev_add(struct v4l2_subdev subdev) · 5 unmodified lines
526	640	* to disable a clock that has not been enabled,
527	641	* we need to enable the clock first.
528	642	*/
529		− ret = clk_prepare_enable(gmin_subdevs[i].pmc_clk);
	643	+ ret = clk_prepare_enable(gs->pmc_clk);
530	644	if (!ret)
531		− clk_disable_unprepare(gmin_subdevs[i].pmc_clk);
532		−
533		− gmin_subdevs[i].gpio0 = gpiod_get_index(dev, NULL, 0, GPIOD_OUT_LOW);
534		− if (IS_ERR(gmin_subdevs[i].gpio0))
535		− gmin_subdevs[i].gpio0 = NULL;
536		−
537		− gmin_subdevs[i].gpio1 = gpiod_get_index(dev, NULL, 1, GPIOD_OUT_LOW);
538		− if (IS_ERR(gmin_subdevs[i].gpio1))
539		− gmin_subdevs[i].gpio1 = NULL;
	645	+ clk_disable_unprepare(gs->pmc_clk);
540	646
541	647	switch (pmic_id) {
542	648	case PMIC_REGULATOR:
543		− gmin_subdevs[i].v1p8_reg = regulator_get(dev, "V1P8SX");
544		− gmin_subdevs[i].v2p8_reg = regulator_get(dev, "V2P8SX");
	649	+ gs->v1p8_reg = regulator_get(dev, "V1P8SX");
	650	+ gs->v2p8_reg = regulator_get(dev, "V2P8SX");
545	651
546		− gmin_subdevs[i].v1p2_reg = regulator_get(dev, "V1P2A");
547		− gmin_subdevs[i].v2p8_vcm_reg = regulator_get(dev, "VPROG4B");
	652	+ gs->v1p2_reg = regulator_get(dev, "V1P2A");
	653	+ gs->v2p8_vcm_reg = regulator_get(dev, "VPROG4B");
548	654
549	655	/* Note: ideally we would initialize v[12]p8_on to the
550	656	* output of regulator_is_enabled(), but sadly that
@@ -556,32 +662,31 @@ static struct gmin_subdev gmin_subdev_add(struct v4l2_subdev subdev) · 5 unmodified lines
556	662	break;
557	663
558	664	case PMIC_AXP:
559		− gmin_subdevs[i].eldo1_1p8v = gmin_get_var_int(dev, false,
560		− "eldo1_1p8v",
561		− ELDO1_1P8V);
562		− gmin_subdevs[i].eldo1_sel_reg = gmin_get_var_int(dev, false,
563		− "eldo1_sel_reg",
564		− ELDO1_SEL_REG);
565		− gmin_subdevs[i].eldo1_ctrl_shift = gmin_get_var_int(dev, false,
566		− "eldo1_ctrl_shift",
567		− ELDO1_CTRL_SHIFT);
568		− gmin_subdevs[i].eldo2_1p8v = gmin_get_var_int(dev, false,
569		− "eldo2_1p8v",
570		− ELDO2_1P8V);
571		− gmin_subdevs[i].eldo2_sel_reg = gmin_get_var_int(dev, false,
572		− "eldo2_sel_reg",
573		− ELDO2_SEL_REG);
574		− gmin_subdevs[i].eldo2_ctrl_shift = gmin_get_var_int(dev, false,
575		− "eldo2_ctrl_shift",
576		− ELDO2_CTRL_SHIFT);
577		− gmin_subdevs[i].pwm_i2c_addr = power->addr;
	665	+ gs->eldo1_1p8v = gmin_get_var_int(dev, false,
	666	+ "eldo1_1p8v",
	667	+ ELDO1_1P8V);
	668	+ gs->eldo1_sel_reg = gmin_get_var_int(dev, false,
	669	+ "eldo1_sel_reg",
	670	+ ELDO1_SEL_REG);
	671	+ gs->eldo1_ctrl_shift = gmin_get_var_int(dev, false,
	672	+ "eldo1_ctrl_shift",
	673	+ ELDO1_CTRL_SHIFT);
	674	+ gs->eldo2_1p8v = gmin_get_var_int(dev, false,
	675	+ "eldo2_1p8v",
	676	+ ELDO2_1P8V);
	677	+ gs->eldo2_sel_reg = gmin_get_var_int(dev, false,
	678	+ "eldo2_sel_reg",
	679	+ ELDO2_SEL_REG);
	680	+ gs->eldo2_ctrl_shift = gmin_get_var_int(dev, false,
	681	+ "eldo2_ctrl_shift",
	682	+ ELDO2_CTRL_SHIFT);
578	683	break;
579	684
580	685	default:
581	686	break;
582	687	}
583	688
584		− return &gmin_subdevs[i];
	689	+ return 0;
585	690	}
586	691
587	692	static struct gmin_subdev find_gmin_subdev(struct v4l2_subdev subdev)
@@ -591,7 +696,17 @@ static struct gmin_subdev find_gmin_subdev(struct v4l2_subdev subdev) · 3 unmodified lines
591	696	for (i = 0; i < MAX_SUBDEVS; i++)
592	697	if (gmin_subdevs[i].subdev == subdev)
593	698	return &gmin_subdevs[i];
594		− return gmin_subdev_add(subdev);
	699	+ return NULL;
	700	+}
	701	+
	702	+static struct gmin_subdev *find_free_gmin_subdev_slot(void)
	703	+{
	704	+ unsigned int i;
	705	+
	706	+ for (i = 0; i < MAX_SUBDEVS; i++)
	707	+ if (gmin_subdevs[i].subdev == NULL)
	708	+ return &gmin_subdevs[i];
	709	+ return NULL;
595	710	}
596	711
597	712	static int axp_regulator_set(struct device dev, struct gmin_subdev gs,
@@ -700,32 +815,24 @@ static int gmin_v1p8_ctrl(struct v4l2_subdev *subdev, int on) · 102 unmodified lines
700	815	{
701	816	struct gmin_subdev *gs = find_gmin_subdev(subdev);
702	817	int ret;
703		− struct device *dev;
704		− struct i2c_client *client = v4l2_get_subdevdata(subdev);
705	818	int value;
706	819
707		− dev = &client->dev;
708		−
709		− if (v1p8_gpio == V1P8_GPIO_UNSET) {
710		− v1p8_gpio = gmin_get_var_int(dev, true,
711		− "V1P8GPIO", V1P8_GPIO_NONE);
712		− if (v1p8_gpio != V1P8_GPIO_NONE) {
713		− pr_info("atomisp_gmin_platform: 1.8v power on GPIO %d\n",
714		− v1p8_gpio);
715		− ret = gpio_request(v1p8_gpio, "camera_v1p8_en");
716		− if (!ret)
717		− ret = gpio_direction_output(v1p8_gpio, 0);
718		− if (ret)
719		− pr_err("V1P8 GPIO initialization failed\n");
720		− }
	820	+ if (gs->v1p8_gpio >= 0) {
	821	+ pr_info("atomisp_gmin_platform: 1.8v power on GPIO %d\n",
	822	+ gs->v1p8_gpio);
	823	+ ret = gpio_request(gs->v1p8_gpio, "camera_v1p8_en");
	824	+ if (!ret)
	825	+ ret = gpio_direction_output(gs->v1p8_gpio, 0);
	826	+ if (ret)
	827	+ pr_err("V1P8 GPIO initialization failed\n");
721	828	}
722	829
723	830	if (!gs \|\| gs->v1p8_on == on)
724	831	return 0;
725	832	gs->v1p8_on = on;
726	833
727		− if (v1p8_gpio >= 0)
728		− gpio_set_value(v1p8_gpio, on);
	834	+ if (gs->v1p8_gpio >= 0)
	835	+ gpio_set_value(gs->v1p8_gpio, on);
729	836
730	837	if (gs->v1p8_reg) {
731	838	regulator_set_voltage(gs->v1p8_reg, 1800000, 1800000);
@@ -762,32 +869,24 @@ static int gmin_v2p8_ctrl(struct v4l2_subdev *subdev, int on) · 30 unmodified lines
762	869	{
763	870	struct gmin_subdev *gs = find_gmin_subdev(subdev);
764	871	int ret;
765		− struct device *dev;
766		− struct i2c_client *client = v4l2_get_subdevdata(subdev);
767	872	int value;
768	873
769		− dev = &client->dev;
770		−
771		− if (v2p8_gpio == V2P8_GPIO_UNSET) {
772		− v2p8_gpio = gmin_get_var_int(dev, true,
773		− "V2P8GPIO", V2P8_GPIO_NONE);
774		− if (v2p8_gpio != V2P8_GPIO_NONE) {
775		− pr_info("atomisp_gmin_platform: 2.8v power on GPIO %d\n",
776		− v2p8_gpio);
777		− ret = gpio_request(v2p8_gpio, "camera_v2p8");
778		− if (!ret)
779		− ret = gpio_direction_output(v2p8_gpio, 0);
780		− if (ret)
781		− pr_err("V2P8 GPIO initialization failed\n");
782		− }
	874	+ if (gs->v2p8_gpio >= 0) {
	875	+ pr_info("atomisp_gmin_platform: 2.8v power on GPIO %d\n",
	876	+ gs->v2p8_gpio);
	877	+ ret = gpio_request(gs->v2p8_gpio, "camera_v2p8");
	878	+ if (!ret)
	879	+ ret = gpio_direction_output(gs->v2p8_gpio, 0);
	880	+ if (ret)
	881	+ pr_err("V2P8 GPIO initialization failed\n");
783	882	}
784	883
785	884	if (!gs \|\| gs->v2p8_on == on)
786	885	return 0;
787	886	gs->v2p8_on = on;
788	887
789		− if (v2p8_gpio >= 0)
790		− gpio_set_value(v2p8_gpio, on);
	888	+ if (gs->v2p8_gpio >= 0)
	889	+ gpio_set_value(gs->v2p8_gpio, on);
791	890
792	891	if (gs->v2p8_reg) {
793	892	regulator_set_voltage(gs->v2p8_reg, 2900000, 2900000);
@@ -819,6 +918,37 @@ static int gmin_v2p8_ctrl(struct v4l2_subdev *subdev, int on) · 25 unmodified lines
819	918	return -EINVAL;
820	919	}
821	920
	921	+static int gmin_acpi_pm_ctrl(struct v4l2_subdev *subdev, int on)
	922	+{
	923	+ int ret = 0;
	924	+ struct gmin_subdev *gs = find_gmin_subdev(subdev);
	925	+ struct i2c_client *client = v4l2_get_subdevdata(subdev);
	926	+ struct acpi_device *adev = ACPI_COMPANION(&client->dev);
	927	+
	928	+ /* Use the ACPI power management to control it */
	929	+ on = !!on;
	930	+ if (gs->clock_on == on)
	931	+ return 0;
	932	+
	933	+ dev_dbg(subdev->dev, "Setting power state to %s\n",
	934	+ on ? "on" : "off");
	935	+
	936	+ if (on)
	937	+ ret = acpi_device_set_power(adev,
	938	+ ACPI_STATE_D0);
	939	+ else
	940	+ ret = acpi_device_set_power(adev,
	941	+ ACPI_STATE_D3_COLD);
	942	+
	943	+ if (!ret)
	944	+ gs->clock_on = on;
	945	+ else
	946	+ dev_err(subdev->dev, "Couldn't set power state to %s\n",
	947	+ on ? "on" : "off");
	948	+
	949	+ return ret;
	950	+}
	951	+
822	952	static int gmin_flisclk_ctrl(struct v4l2_subdev *subdev, int on)
823	953	{
824	954	int ret = 0;
@@ -884,7 +1014,7 @@ static struct camera_vcm_control gmin_get_vcm_ctrl(struct v4l2_subdev subdev, · 59 unmodified lines
884	1014	return NULL;
885	1015	}
886	1016
887		−static struct camera_sensor_platform_data gmin_plat = {
	1017	+static struct camera_sensor_platform_data pmic_gmin_plat = {
888	1018	.gpio0_ctrl = gmin_gpio0_ctrl,
889	1019	.gpio1_ctrl = gmin_gpio1_ctrl,
890	1020	.v1p8_ctrl = gmin_v1p8_ctrl,
@@ -895,17 +1025,36 @@ static struct camera_sensor_platform_data gmin_plat = { · 4 unmodified lines
895	1025	.get_vcm_ctrl = gmin_get_vcm_ctrl,
896	1026	};
897	1027
	1028	+static struct camera_sensor_platform_data acpi_gmin_plat = {
	1029	+ .gpio0_ctrl = gmin_gpio0_ctrl,
	1030	+ .gpio1_ctrl = gmin_gpio1_ctrl,
	1031	+ .v1p8_ctrl = gmin_acpi_pm_ctrl,
	1032	+ .v2p8_ctrl = gmin_acpi_pm_ctrl,
	1033	+ .v1p2_ctrl = gmin_acpi_pm_ctrl,
	1034	+ .flisclk_ctrl = gmin_acpi_pm_ctrl,
	1035	+ .csi_cfg = gmin_csi_cfg,
	1036	+ .get_vcm_ctrl = gmin_get_vcm_ctrl,
	1037	+};
	1038	+
898	1039	struct camera_sensor_platform_data *gmin_camera_platform_data(
899	1040	struct v4l2_subdev *subdev,
900	1041	enum atomisp_input_format csi_format,
901	1042	enum atomisp_bayer_order csi_bayer)
902	1043	{
903		− struct gmin_subdev *gs = find_gmin_subdev(subdev);
	1044	+ u8 pmic_i2c_addr = gmin_detect_pmic(subdev);
	1045	+ struct gmin_subdev *gs;
904	1046
	1047	+ gs = find_free_gmin_subdev_slot();
	1048	+ gs->subdev = subdev;
905	1049	gs->csi_fmt = csi_format;
906	1050	gs->csi_bayer = csi_bayer;
	1051	+ gs->pwm_i2c_addr = pmic_i2c_addr;
907	1052
908		− return &gmin_plat;
	1053	+ gmin_subdev_add(gs);
	1054	+ if (gs->pmc_clk)
	1055	+ return &pmic_gmin_plat;
	1056	+ else
	1057	+ return &acpi_gmin_plat;
909	1058	}
910	1059	EXPORT_SYMBOL_GPL(gmin_camera_platform_data);
911	1060
@@ -957,12 +1106,28 @@ static int gmin_get_config_dsm_var(struct device *dev, · 45 unmodified lines
957	1106	union acpi_object obj, cur = NULL;
958	1107	int i;
959	1108
	1109	+ /*
	1110	+ * The data reported by "CamClk" seems to be either 0 or 1 at the
	1111	+ * _DSM table.
	1112	+ *
	1113	+ * At the ACPI tables we looked so far, this is not related to the
	1114	+ * actual clock source for the sensor, which is given by the
	1115	+ * _PR0 ACPI table. So, ignore it, as otherwise this will be
	1116	+ * set to a wrong value.
	1117	+ */
	1118	+ if (!strcmp(var, "CamClk"))
	1119	+ return -EINVAL;
	1120	+
960	1121	obj = acpi_evaluate_dsm(handle, &atomisp_dsm_guid, 0, 0, NULL);
961	1122	if (!obj) {
962	1123	dev_info_once(dev, "Didn't find ACPI _DSM table.\n");
963	1124	return -EINVAL;
964	1125	}
965	1126
	1127	+ /* Return on unexpected object type */
	1128	+ if (obj->type != ACPI_TYPE_PACKAGE)
	1129	+ return -EINVAL;
	1130	+
966	1131	#if 0 /* Just for debugging purposes */
967	1132	for (i = 0; i < obj->package.count; i++) {
968	1133	union acpi_object *cur = &obj->package.elements[i];
@@ -1155,10 +1320,10 @@ EXPORT_SYMBOL_GPL(camera_sensor_csi); · 186 unmodified lines
1155	1320	* trying. The driver itself does direct calls to the PUNIT to manage
1156	1321	* ISP power.
1157	1322	*/
1158		−static void isp_pm_cap_fixup(struct pci_dev *dev)
	1323	+static void isp_pm_cap_fixup(struct pci_dev *pdev)
1159	1324	{
1160		− dev_info(&dev->dev, "Disabling PCI power management on camera ISP\n");
1161		− dev->pm_cap = 0;
	1325	+ dev_info(&pdev->dev, "Disabling PCI power management on camera ISP\n");
	1326	+ pdev->pm_cap = 0;
1162	1327	}
1163	1328	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0f38, isp_pm_cap_fixup);
1164	1329

drivers/staging/media/atomisp/pci/atomisp_internal.h+1−1

@@ -216,12 +216,12 @@ struct atomisp_sw_contex { · 215 unmodified lines
216	216	* ci device struct
217	217	*/
218	218	struct atomisp_device {
219		− struct pci_dev *pdev;
220	219	struct device *dev;
221	220	struct v4l2_device v4l2_dev;
222	221	struct media_device media_dev;
223	222	struct atomisp_platform_data *pdata;
224	223	void *mmu_l1_base;
	224	+ void __iomem *base;
225	225	const struct firmware *firmware;
226	226
227	227	struct pm_qos_request pm_qos;

drivers/staging/media/atomisp/pci/atomisp_ioctl.c+9−10

@@ -549,8 +549,7 @@ static int atomisp_querycap(struct file file, void fh, · 548 unmodified lines
549	549
550	550	strscpy(cap->driver, DRIVER, sizeof(cap->driver));
551	551	strscpy(cap->card, CARD, sizeof(cap->card));
552		− snprintf(cap->bus_info, sizeof(cap->bus_info), "PCI:%s",
553		− pci_name(isp->pdev));
	552	+ snprintf(cap->bus_info, sizeof(cap->bus_info), "PCI:%s", dev_name(isp->dev));
554	553
555	554	return 0;
556	555	}
@@ -1635,6 +1634,7 @@ static int atomisp_streamon(struct file file, void fh, · 1078 unmodified lines
1635	1634	struct atomisp_video_pipe *pipe = atomisp_to_video_pipe(vdev);
1636	1635	struct atomisp_sub_device *asd = pipe->asd;
1637	1636	struct atomisp_device *isp = video_get_drvdata(vdev);
	1637	+ struct pci_dev *pdev = to_pci_dev(isp->dev);
1638	1638	enum ia_css_pipe_id css_pipe_id;
1639	1639	unsigned int sensor_start_stream;
1640	1640	unsigned int wdt_duration = ATOMISP_ISP_TIMEOUT_DURATION;
@@ -1844,9 +1844,8 @@ start_sensor: · 203 unmodified lines
1844	1844	/* Enable the CSI interface on ANN B0/K0 */
1845	1845	if (isp->media_dev.hw_revision >= ((ATOMISP_HW_REVISION_ISP2401 <<
1846	1846	ATOMISP_HW_REVISION_SHIFT) \| ATOMISP_HW_STEPPING_B0)) {
1847		− pci_write_config_word(isp->pdev, MRFLD_PCI_CSI_CONTROL,
1848		− isp->saved_regs.csi_control \|
1849		− MRFLD_PCI_CSI_CONTROL_CSI_READY);
	1847	+ pci_write_config_word(pdev, MRFLD_PCI_CSI_CONTROL,
	1848	+ isp->saved_regs.csi_control \| MRFLD_PCI_CSI_CONTROL_CSI_READY);
1850	1849	}
1851	1850
1852	1851	/* stream on the sensor */
@@ -1891,6 +1890,7 @@ int __atomisp_streamoff(struct file file, void fh, enum v4l2_buf_type type) · 38 unmodified lines
1891	1890	{
1892	1891	struct video_device *vdev = video_devdata(file);
1893	1892	struct atomisp_device *isp = video_get_drvdata(vdev);
	1893	+ struct pci_dev *pdev = to_pci_dev(isp->dev);
1894	1894	struct atomisp_video_pipe *pipe = atomisp_to_video_pipe(vdev);
1895	1895	struct atomisp_sub_device *asd = pipe->asd;
1896	1896	struct atomisp_video_pipe *capture_pipe = NULL;
@@ -2076,9 +2076,8 @@ stopsensor: · 179 unmodified lines
2076	2076	/* Disable the CSI interface on ANN B0/K0 */
2077	2077	if (isp->media_dev.hw_revision >= ((ATOMISP_HW_REVISION_ISP2401 <<
2078	2078	ATOMISP_HW_REVISION_SHIFT) \| ATOMISP_HW_STEPPING_B0)) {
2079		− pci_write_config_word(isp->pdev, MRFLD_PCI_CSI_CONTROL,
2080		− isp->saved_regs.csi_control &
2081		− ~MRFLD_PCI_CSI_CONTROL_CSI_READY);
	2079	+ pci_write_config_word(pdev, MRFLD_PCI_CSI_CONTROL,
	2080	+ isp->saved_regs.csi_control & ~MRFLD_PCI_CSI_CONTROL_CSI_READY);
2082	2081	}
2083	2082
2084	2083	if (atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW, false))
@@ -2111,8 +2110,8 @@ stopsensor: · 26 unmodified lines
2111	2110	}
2112	2111
2113	2112	/* disable PUNIT/ISP acknowlede/handshake - SRSE=3 */
2114		− pci_write_config_dword(isp->pdev, PCI_I_CONTROL, isp->saved_regs.i_control \|
2115		− MRFLD_PCI_I_CONTROL_SRSE_RESET_MASK);
	2113	+ pci_write_config_dword(pdev, PCI_I_CONTROL,
	2114	+ isp->saved_regs.i_control \| MRFLD_PCI_I_CONTROL_SRSE_RESET_MASK);
2116	2115	dev_err(isp->dev, "atomisp_reset");
2117	2116	atomisp_reset(isp);
2118	2117	for (i = 0; i < isp->num_of_streams; i++) {

drivers/staging/media/atomisp/pci/atomisp_v4l2.c+127−158

@@ -127,8 +127,6 @@ MODULE_PARM_DESC(pad_h, "extra data for ISP processing"); · 126 unmodified lines
127	127
128	128	struct device *atomisp_dev;
129	129
130		−void __iomem *atomisp_io_base;
131		−
132	130	static const struct atomisp_freq_scaling_rule dfs_rules_merr[] = {
133	131	{
134	132	.width = ISP_FREQ_RULE_ANY,
@@ -512,30 +510,27 @@ void atomisp_acc_unregister(struct atomisp_acc_pipe *video) · 377 unmodified lines
512	510
513	511	static int atomisp_save_iunit_reg(struct atomisp_device *isp)
514	512	{
515		− struct pci_dev *dev = isp->pdev;
	513	+ struct pci_dev *pdev = to_pci_dev(isp->dev);
516	514
517	515	dev_dbg(isp->dev, "%s\n", __func__);
518	516
519		− pci_read_config_word(dev, PCI_COMMAND, &isp->saved_regs.pcicmdsts);
	517	+ pci_read_config_word(pdev, PCI_COMMAND, &isp->saved_regs.pcicmdsts);
520	518	/* isp->saved_regs.ispmmadr is set from the atomisp_pci_probe() */
521		− pci_read_config_dword(dev, PCI_MSI_CAPID, &isp->saved_regs.msicap);
522		− pci_read_config_dword(dev, PCI_MSI_ADDR, &isp->saved_regs.msi_addr);
523		− pci_read_config_word(dev, PCI_MSI_DATA, &isp->saved_regs.msi_data);
524		− pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &isp->saved_regs.intr);
525		− pci_read_config_dword(dev, PCI_INTERRUPT_CTRL,
526		− &isp->saved_regs.interrupt_control);
527		−
528		− pci_read_config_dword(dev, MRFLD_PCI_PMCS,
529		− &isp->saved_regs.pmcs);
	519	+ pci_read_config_dword(pdev, PCI_MSI_CAPID, &isp->saved_regs.msicap);
	520	+ pci_read_config_dword(pdev, PCI_MSI_ADDR, &isp->saved_regs.msi_addr);
	521	+ pci_read_config_word(pdev, PCI_MSI_DATA, &isp->saved_regs.msi_data);
	522	+ pci_read_config_byte(pdev, PCI_INTERRUPT_LINE, &isp->saved_regs.intr);
	523	+ pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &isp->saved_regs.interrupt_control);
	524	+
	525	+ pci_read_config_dword(pdev, MRFLD_PCI_PMCS, &isp->saved_regs.pmcs);
530	526	/* Ensure read/write combining is enabled. */
531		− pci_read_config_dword(dev, PCI_I_CONTROL,
532		− &isp->saved_regs.i_control);
	527	+ pci_read_config_dword(pdev, PCI_I_CONTROL, &isp->saved_regs.i_control);
533	528	isp->saved_regs.i_control \|=
534	529	MRFLD_PCI_I_CONTROL_ENABLE_READ_COMBINING \|
535	530	MRFLD_PCI_I_CONTROL_ENABLE_WRITE_COMBINING;
536		− pci_read_config_dword(dev, MRFLD_PCI_CSI_ACCESS_CTRL_VIOL,
	531	+ pci_read_config_dword(pdev, MRFLD_PCI_CSI_ACCESS_CTRL_VIOL,
537	532	&isp->saved_regs.csi_access_viol);
538		− pci_read_config_dword(dev, MRFLD_PCI_CSI_RCOMP_CONTROL,
	533	+ pci_read_config_dword(pdev, MRFLD_PCI_CSI_RCOMP_CONTROL,
539	534	&isp->saved_regs.csi_rcomp_config);
540	535	/*
541	536	* Hardware bugs require setting CSI_HS_OVR_CLK_GATE_ON_UPDATE.
@@ -545,65 +540,58 @@ static int atomisp_save_iunit_reg(struct atomisp_device *isp) · 3 unmodified lines
545	540	* is missed, and IUNIT can hang.
546	541	* For both issues, setting this bit is a workaround.
547	542	*/
548		− isp->saved_regs.csi_rcomp_config \|=
549		− MRFLD_PCI_CSI_HS_OVR_CLK_GATE_ON_UPDATE;
550		− pci_read_config_dword(dev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL,
	543	+ isp->saved_regs.csi_rcomp_config \|= MRFLD_PCI_CSI_HS_OVR_CLK_GATE_ON_UPDATE;
	544	+ pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL,
551	545	&isp->saved_regs.csi_afe_dly);
552		− pci_read_config_dword(dev, MRFLD_PCI_CSI_CONTROL,
	546	+ pci_read_config_dword(pdev, MRFLD_PCI_CSI_CONTROL,
553	547	&isp->saved_regs.csi_control);
554	548	if (isp->media_dev.hw_revision >=
555	549	(ATOMISP_HW_REVISION_ISP2401 << ATOMISP_HW_REVISION_SHIFT))
556		− isp->saved_regs.csi_control \|=
557		− MRFLD_PCI_CSI_CONTROL_PARPATHEN;
	550	+ isp->saved_regs.csi_control \|= MRFLD_PCI_CSI_CONTROL_PARPATHEN;
558	551	/*
559	552	* On CHT CSI_READY bit should be enabled before stream on
560	553	*/
561	554	if (IS_CHT && (isp->media_dev.hw_revision >= ((ATOMISP_HW_REVISION_ISP2401 <<
562	555	ATOMISP_HW_REVISION_SHIFT) \| ATOMISP_HW_STEPPING_B0)))
563		− isp->saved_regs.csi_control \|=
564		− MRFLD_PCI_CSI_CONTROL_CSI_READY;
565		− pci_read_config_dword(dev, MRFLD_PCI_CSI_AFE_RCOMP_CONTROL,
	556	+ isp->saved_regs.csi_control \|= MRFLD_PCI_CSI_CONTROL_CSI_READY;
	557	+ pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_RCOMP_CONTROL,
566	558	&isp->saved_regs.csi_afe_rcomp_config);
567		− pci_read_config_dword(dev, MRFLD_PCI_CSI_AFE_HS_CONTROL,
	559	+ pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_HS_CONTROL,
568	560	&isp->saved_regs.csi_afe_hs_control);
569		− pci_read_config_dword(dev, MRFLD_PCI_CSI_DEADLINE_CONTROL,
	561	+ pci_read_config_dword(pdev, MRFLD_PCI_CSI_DEADLINE_CONTROL,
570	562	&isp->saved_regs.csi_deadline_control);
571	563	return 0;
572	564	}
573	565
574	566	static int __maybe_unused atomisp_restore_iunit_reg(struct atomisp_device *isp)
575	567	{
576		− struct pci_dev *dev = isp->pdev;
	568	+ struct pci_dev *pdev = to_pci_dev(isp->dev);
577	569
578	570	dev_dbg(isp->dev, "%s\n", __func__);
579	571
580		− pci_write_config_word(dev, PCI_COMMAND, isp->saved_regs.pcicmdsts);
581		− pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
582		− isp->saved_regs.ispmmadr);
583		− pci_write_config_dword(dev, PCI_MSI_CAPID, isp->saved_regs.msicap);
584		− pci_write_config_dword(dev, PCI_MSI_ADDR, isp->saved_regs.msi_addr);
585		− pci_write_config_word(dev, PCI_MSI_DATA, isp->saved_regs.msi_data);
586		− pci_write_config_byte(dev, PCI_INTERRUPT_LINE, isp->saved_regs.intr);
587		− pci_write_config_dword(dev, PCI_INTERRUPT_CTRL,
588		− isp->saved_regs.interrupt_control);
589		− pci_write_config_dword(dev, PCI_I_CONTROL,
590		− isp->saved_regs.i_control);
591		−
592		− pci_write_config_dword(dev, MRFLD_PCI_PMCS,
593		− isp->saved_regs.pmcs);
594		− pci_write_config_dword(dev, MRFLD_PCI_CSI_ACCESS_CTRL_VIOL,
	572	+ pci_write_config_word(pdev, PCI_COMMAND, isp->saved_regs.pcicmdsts);
	573	+ pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, isp->saved_regs.ispmmadr);
	574	+ pci_write_config_dword(pdev, PCI_MSI_CAPID, isp->saved_regs.msicap);
	575	+ pci_write_config_dword(pdev, PCI_MSI_ADDR, isp->saved_regs.msi_addr);
	576	+ pci_write_config_word(pdev, PCI_MSI_DATA, isp->saved_regs.msi_data);
	577	+ pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, isp->saved_regs.intr);
	578	+ pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, isp->saved_regs.interrupt_control);
	579	+ pci_write_config_dword(pdev, PCI_I_CONTROL, isp->saved_regs.i_control);
	580	+
	581	+ pci_write_config_dword(pdev, MRFLD_PCI_PMCS, isp->saved_regs.pmcs);
	582	+ pci_write_config_dword(pdev, MRFLD_PCI_CSI_ACCESS_CTRL_VIOL,
595	583	isp->saved_regs.csi_access_viol);
596		− pci_write_config_dword(dev, MRFLD_PCI_CSI_RCOMP_CONTROL,
	584	+ pci_write_config_dword(pdev, MRFLD_PCI_CSI_RCOMP_CONTROL,
597	585	isp->saved_regs.csi_rcomp_config);
598		− pci_write_config_dword(dev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL,
	586	+ pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL,
599	587	isp->saved_regs.csi_afe_dly);
600		− pci_write_config_dword(dev, MRFLD_PCI_CSI_CONTROL,
	588	+ pci_write_config_dword(pdev, MRFLD_PCI_CSI_CONTROL,
601	589	isp->saved_regs.csi_control);
602		− pci_write_config_dword(dev, MRFLD_PCI_CSI_AFE_RCOMP_CONTROL,
	590	+ pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_RCOMP_CONTROL,
603	591	isp->saved_regs.csi_afe_rcomp_config);
604		− pci_write_config_dword(dev, MRFLD_PCI_CSI_AFE_HS_CONTROL,
	592	+ pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_HS_CONTROL,
605	593	isp->saved_regs.csi_afe_hs_control);
606		− pci_write_config_dword(dev, MRFLD_PCI_CSI_DEADLINE_CONTROL,
	594	+ pci_write_config_dword(pdev, MRFLD_PCI_CSI_DEADLINE_CONTROL,
607	595	isp->saved_regs.csi_deadline_control);
608	596
609	597	/*
@@ -619,7 +607,7 @@ static int __maybe_unused atomisp_restore_iunit_reg(struct atomisp_device *isp) · 9 unmodified lines
619	607
620	608	static int atomisp_mrfld_pre_power_down(struct atomisp_device *isp)
621	609	{
622		− struct pci_dev *dev = isp->pdev;
	610	+ struct pci_dev *pdev = to_pci_dev(isp->dev);
623	611	u32 irq;
624	612	unsigned long flags;
625	613
@@ -635,11 +623,11 @@ static int atomisp_mrfld_pre_power_down(struct atomisp_device *isp) · 9 unmodified lines
635	623	* So, here we need to check if there is any pending
636	624	* IRQ, if so, waiting for it to be served
637	625	*/
638		− pci_read_config_dword(dev, PCI_INTERRUPT_CTRL, &irq);
	626	+ pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
639	627	irq = irq & 1 << INTR_IIR;
640		− pci_write_config_dword(dev, PCI_INTERRUPT_CTRL, irq);
	628	+ pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq);
641	629
642		− pci_read_config_dword(dev, PCI_INTERRUPT_CTRL, &irq);
	630	+ pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
643	631	if (!(irq & (1 << INTR_IIR)))
644	632	goto done;
645	633
@@ -652,11 +640,11 @@ static int atomisp_mrfld_pre_power_down(struct atomisp_device *isp) · 6 unmodified lines
652	640	spin_unlock_irqrestore(&isp->lock, flags);
653	641	return -EAGAIN;
654	642	} else {
655		− pci_read_config_dword(dev, PCI_INTERRUPT_CTRL, &irq);
	643	+ pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
656	644	irq = irq & 1 << INTR_IIR;
657		− pci_write_config_dword(dev, PCI_INTERRUPT_CTRL, irq);
	645	+ pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq);
658	646
659		− pci_read_config_dword(dev, PCI_INTERRUPT_CTRL, &irq);
	647	+ pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
660	648	if (!(irq & (1 << INTR_IIR))) {
661	649	atomisp_css2_hw_store_32(MRFLD_INTR_ENABLE_REG, 0x0);
662	650	goto done;
@@ -675,11 +663,11 @@ done: · 12 unmodified lines
675	663	* to IIR. It could block subsequent interrupt messages.
676	664	* HW sighting:4568410.
677	665	*/
678		− pci_read_config_dword(dev, PCI_INTERRUPT_CTRL, &irq);
	666	+ pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
679	667	irq &= ~(1 << INTR_IER);
680		− pci_write_config_dword(dev, PCI_INTERRUPT_CTRL, irq);
	668	+ pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq);
681	669
682		− atomisp_msi_irq_uninit(isp, dev);
	670	+ atomisp_msi_irq_uninit(isp);
683	671	atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW, true);
684	672	spin_unlock_irqrestore(&isp->lock, flags);
685	673
@@ -755,7 +743,7 @@ static int atomisp_mrfld_power(struct atomisp_device *isp, bool enable) · 69 unmodified lines
755	743
756	744	/* Wait until ISPSSPM0 bit[25:24] shows the right value */
757	745	iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSPM0, &tmp);
758		− tmp = (tmp & MRFLD_ISPSSPM0_ISPSSC_MASK) >> MRFLD_ISPSSPM0_ISPSSS_OFFSET;
	746	+ tmp = (tmp >> MRFLD_ISPSSPM0_ISPSSS_OFFSET) & MRFLD_ISPSSPM0_ISPSSC_MASK;
759	747	if (tmp == val) {
760	748	trace_ipu_cstate(enable);
761	749	return 0;
@@ -778,15 +766,13 @@ static int atomisp_mrfld_power(struct atomisp_device *isp, bool enable) · 16 unmodified lines
778	766	/* Workaround for pmu_nc_set_power_state not ready in MRFLD */
779	767	int atomisp_mrfld_power_down(struct atomisp_device *isp)
780	768	{
781		−// FIXME: at least with ISP2401, enabling this code causes the driver to break
782		− return 0 && atomisp_mrfld_power(isp, false);
	769	+ return atomisp_mrfld_power(isp, false);
783	770	}
784	771
785	772	/* Workaround for pmu_nc_set_power_state not ready in MRFLD */
786	773	int atomisp_mrfld_power_up(struct atomisp_device *isp)
787	774	{
788		−// FIXME: at least with ISP2401, enabling this code causes the driver to break
789		− return 0 && atomisp_mrfld_power(isp, true);
	775	+ return atomisp_mrfld_power(isp, true);
790	776	}
791	777
792	778	int atomisp_runtime_suspend(struct device *dev)
@@ -902,6 +888,7 @@ static int __maybe_unused atomisp_resume(struct device *dev) · 109 unmodified lines
902	888
903	889	int atomisp_csi_lane_config(struct atomisp_device *isp)
904	890	{
	891	+ struct pci_dev *pdev = to_pci_dev(isp->dev);
905	892	static const struct {
906	893	u8 code;
907	894	u8 lanes[MRFLD_PORT_NUM];
@@ -1003,7 +990,7 @@ int atomisp_csi_lane_config(struct atomisp_device *isp) · 95 unmodified lines
1003	990	return -EINVAL;
1004	991	}
1005	992
1006		− pci_read_config_dword(isp->pdev, MRFLD_PCI_CSI_CONTROL, &csi_control);
	993	+ pci_read_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, &csi_control);
1007	994	csi_control &= ~port_config_mask;
1008	995	csi_control \|= (portconfigs[i].code << MRFLD_PORT_CONFIGCODE_SHIFT)
1009	996	\| (portconfigs[i].lanes[0] ? 0 : (1 << MRFLD_PORT1_ENABLE_SHIFT))
@@ -1013,7 +1000,7 @@ int atomisp_csi_lane_config(struct atomisp_device *isp) · 3 unmodified lines
1013	1000	\| (((1 << portconfigs[i].lanes[1]) - 1) << MRFLD_PORT2_LANES_SHIFT)
1014	1001	\| (((1 << portconfigs[i].lanes[2]) - 1) << port3_lanes_shift);
1015	1002
1016		− pci_write_config_dword(isp->pdev, MRFLD_PCI_CSI_CONTROL, csi_control);
	1003	+ pci_write_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, csi_control);
1017	1004
1018	1005	dev_dbg(isp->dev,
1019	1006	"%s: the portconfig is %d-%d-%d, CSI_CONTROL is 0x%08X\n",
@@ -1440,8 +1427,7 @@ atomisp_load_firmware(struct atomisp_device *isp) · 420 unmodified lines
1440	1427	* Check for flags the driver was compiled with against the PCI
1441	1428	* device. Always returns true on other than ISP 2400.
1442	1429	*/
1443		−static bool is_valid_device(struct pci_dev *dev,
1444		− const struct pci_device_id *id)
	1430	+static bool is_valid_device(struct pci_dev pdev, const struct pci_device_id id)
1445	1431	{
1446	1432	unsigned int a0_max_id = 0;
1447	1433	const char *name;
@@ -1465,14 +1451,14 @@ static bool is_valid_device(struct pci_dev *dev, · 17 unmodified lines
1465	1451	name = "Cherrytrail";
1466	1452	break;
1467	1453	default:
1468		− dev_err(&dev->dev, "%s: unknown device ID %x04:%x04\n",
	1454	+ dev_err(&pdev->dev, "%s: unknown device ID %x04:%x04\n",
1469	1455	product, id->vendor, id->device);
1470	1456	return false;
1471	1457	}
1472	1458
1473		− if (dev->revision <= ATOMISP_PCI_REV_BYT_A0_MAX) {
1474		− dev_err(&dev->dev, "%s revision %d is not unsupported\n",
1475		− name, dev->revision);
	1459	+ if (pdev->revision <= ATOMISP_PCI_REV_BYT_A0_MAX) {
	1460	+ dev_err(&pdev->dev, "%s revision %d is not unsupported\n",
	1461	+ name, pdev->revision);
1476	1462	return false;
1477	1463	}
1478	1464
@@ -1483,22 +1469,20 @@ static bool is_valid_device(struct pci_dev *dev, · 4 unmodified lines
1483	1469
1484	1470	#if defined(ISP2400)
1485	1471	if (IS_ISP2401) {
1486		− dev_err(&dev->dev, "Support for %s (ISP2401) was disabled at compile time\n",
	1472	+ dev_err(&pdev->dev, "Support for %s (ISP2401) was disabled at compile time\n",
1487	1473	name);
1488	1474	return false;
1489	1475	}
1490	1476	#else
1491	1477	if (!IS_ISP2401) {
1492		− dev_err(&dev->dev, "Support for %s (ISP2400) was disabled at compile time\n",
	1478	+ dev_err(&pdev->dev, "Support for %s (ISP2400) was disabled at compile time\n",
1493	1479	name);
1494	1480	return false;
1495	1481	}
1496	1482	#endif
1497	1483
1498		− dev_info(&dev->dev, "Detected %s version %d (ISP240%c) on %s\n",
1499		− name, dev->revision,
1500		− IS_ISP2401 ? '1' : '0',
1501		− product);
	1484	+ dev_info(&pdev->dev, "Detected %s version %d (ISP240%c) on %s\n",
	1485	+ name, pdev->revision, IS_ISP2401 ? '1' : '0', product);
1502	1486
1503	1487	return true;
1504	1488	}
@@ -1538,66 +1522,60 @@ alloc_fail: · 33 unmodified lines
1538	1522
1539	1523	#define ATOM_ISP_PCI_BAR 0
1540	1524
1541		−static int atomisp_pci_probe(struct pci_dev *dev,
1542		− const struct pci_device_id *id)
	1525	+static int atomisp_pci_probe(struct pci_dev pdev, const struct pci_device_id id)
1543	1526	{
1544	1527	const struct atomisp_platform_data *pdata;
1545	1528	struct atomisp_device *isp;
1546	1529	unsigned int start;
1547		− void __iomem *base;
1548	1530	int err, val;
1549	1531	u32 irq;
1550	1532
1551		− if (!is_valid_device(dev, id))
	1533	+ if (!is_valid_device(pdev, id))
1552	1534	return -ENODEV;
1553	1535
1554	1536	/* Pointer to struct device. */
1555		− atomisp_dev = &dev->dev;
	1537	+ atomisp_dev = &pdev->dev;
1556	1538
1557	1539	pdata = atomisp_get_platform_data();
1558	1540	if (!pdata)
1559		− dev_warn(&dev->dev, "no platform data available\n");
	1541	+ dev_warn(&pdev->dev, "no platform data available\n");
1560	1542
1561		− err = pcim_enable_device(dev);
	1543	+ err = pcim_enable_device(pdev);
1562	1544	if (err) {
1563		− dev_err(&dev->dev, "Failed to enable CI ISP device (%d)\n",
1564		− err);
	1545	+ dev_err(&pdev->dev, "Failed to enable CI ISP device (%d)\n", err);
1565	1546	return err;
1566	1547	}
1567	1548
1568		− start = pci_resource_start(dev, ATOM_ISP_PCI_BAR);
1569		− dev_dbg(&dev->dev, "start: 0x%x\n", start);
	1549	+ start = pci_resource_start(pdev, ATOM_ISP_PCI_BAR);
	1550	+ dev_dbg(&pdev->dev, "start: 0x%x\n", start);
1570	1551
1571		− err = pcim_iomap_regions(dev, 1 << ATOM_ISP_PCI_BAR, pci_name(dev));
	1552	+ err = pcim_iomap_regions(pdev, 1 << ATOM_ISP_PCI_BAR, pci_name(pdev));
1572	1553	if (err) {
1573		− dev_err(&dev->dev, "Failed to I/O memory remapping (%d)\n",
1574		− err);
	1554	+ dev_err(&pdev->dev, "Failed to I/O memory remapping (%d)\n", err);
1575	1555	goto ioremap_fail;
1576	1556	}
1577	1557
1578		− base = pcim_iomap_table(dev)[ATOM_ISP_PCI_BAR];
1579		− dev_dbg(&dev->dev, "base: %p\n", base);
1580		−
1581		− atomisp_io_base = base;
1582		−
1583		− dev_dbg(&dev->dev, "atomisp_io_base: %p\n", atomisp_io_base);
1584		−
1585		− isp = devm_kzalloc(&dev->dev, sizeof(struct atomisp_device), GFP_KERNEL);
	1558	+ isp = devm_kzalloc(&pdev->dev, sizeof(*isp), GFP_KERNEL);
1586	1559	if (!isp) {
1587	1560	err = -ENOMEM;
1588	1561	goto atomisp_dev_alloc_fail;
1589	1562	}
1590		− isp->pdev = dev;
1591		− isp->dev = &dev->dev;
	1563	+
	1564	+ isp->dev = &pdev->dev;
	1565	+ isp->base = pcim_iomap_table(pdev)[ATOM_ISP_PCI_BAR];
1592	1566	isp->sw_contex.power_state = ATOM_ISP_POWER_UP;
1593	1567	isp->saved_regs.ispmmadr = start;
1594	1568
	1569	+ dev_dbg(&pdev->dev, "atomisp mmio base: %p\n", isp->base);
	1570	+
1595	1571	rt_mutex_init(&isp->mutex);
1596	1572	mutex_init(&isp->streamoff_mutex);
1597	1573	spin_lock_init(&isp->lock);
1598	1574
1599	1575	/* This is not a true PCI device on SoC, so the delay is not needed. */
1600		− isp->pdev->d3_delay = 0;
	1576	+ pdev->d3_delay = 0;
	1577	+
	1578	+ pci_set_drvdata(pdev, isp);
1601	1579
1602	1580	switch (id->device & ATOMISP_PCI_DEVICE_SOC_MASK) {
1603	1581	case ATOMISP_PCI_DEVICE_SOC_MRFLD:
@@ -1648,15 +1626,14 @@ static int atomisp_pci_probe(struct pci_dev *dev, · 44 unmodified lines
1648	1626	* have specs yet for exactly how it varies. Default to
1649	1627	* BYT-CR but let provisioning set it via EFI variable
1650	1628	*/
1651		− isp->hpll_freq = gmin_get_var_int(&dev->dev, false, "HpllFreq",
1652		− HPLL_FREQ_2000MHZ);
	1629	+ isp->hpll_freq = gmin_get_var_int(&pdev->dev, false, "HpllFreq", HPLL_FREQ_2000MHZ);
1653	1630
1654	1631	/*
1655	1632	* for BYT/CHT we are put isp into D3cold to avoid pci registers access
1656	1633	* in power off. Set d3cold_delay to 0 since default 100ms is not
1657	1634	* necessary.
1658	1635	*/
1659		− isp->pdev->d3cold_delay = 0;
	1636	+ pdev->d3cold_delay = 0;
1660	1637	break;
1661	1638	case ATOMISP_PCI_DEVICE_SOC_ANN:
1662	1639	isp->media_dev.hw_revision = (
@@ -1666,7 +1643,7 @@ static int atomisp_pci_probe(struct pci_dev *dev, · 3 unmodified lines
1666	1643	ATOMISP_HW_REVISION_ISP2401_LEGACY
1667	1644	#endif
1668	1645	<< ATOMISP_HW_REVISION_SHIFT);
1669		− isp->media_dev.hw_revision \|= isp->pdev->revision < 2 ?
	1646	+ isp->media_dev.hw_revision \|= pdev->revision < 2 ?
1670	1647	ATOMISP_HW_STEPPING_A0 : ATOMISP_HW_STEPPING_B0;
1671	1648	isp->dfs = &dfs_config_merr;
1672	1649	isp->hpll_freq = HPLL_FREQ_1600MHZ;
@@ -1679,13 +1656,13 @@ static int atomisp_pci_probe(struct pci_dev *dev, · 6 unmodified lines
1679	1656	ATOMISP_HW_REVISION_ISP2401_LEGACY
1680	1657	#endif
1681	1658	<< ATOMISP_HW_REVISION_SHIFT);
1682		− isp->media_dev.hw_revision \|= isp->pdev->revision < 2 ?
	1659	+ isp->media_dev.hw_revision \|= pdev->revision < 2 ?
1683	1660	ATOMISP_HW_STEPPING_A0 : ATOMISP_HW_STEPPING_B0;
1684	1661
1685	1662	isp->dfs = &dfs_config_cht;
1686		− isp->pdev->d3cold_delay = 0;
	1663	+ pdev->d3cold_delay = 0;
1687	1664
1688		− iosf_mbi_read(CCK_PORT, MBI_REG_READ, CCK_FUSE_REG_0, &val);
	1665	+ iosf_mbi_read(BT_MBI_UNIT_CCK, MBI_REG_READ, CCK_FUSE_REG_0, &val);
1689	1666	switch (val & CCK_FUSE_HPLL_FREQ_MASK) {
1690	1667	case 0x00:
1691	1668	isp->hpll_freq = HPLL_FREQ_800MHZ;
@@ -1698,18 +1675,16 @@ static int atomisp_pci_probe(struct pci_dev *dev, · 6 unmodified lines
1698	1675	break;
1699	1676	default:
1700	1677	isp->hpll_freq = HPLL_FREQ_1600MHZ;
1701		− dev_warn(isp->dev,
1702		− "read HPLL from cck failed. Default to 1600 MHz.\n");
	1678	+ dev_warn(&pdev->dev, "read HPLL from cck failed. Default to 1600 MHz.\n");
1703	1679	}
1704	1680	break;
1705	1681	default:
1706		− dev_err(&dev->dev, "un-supported IUNIT device\n");
	1682	+ dev_err(&pdev->dev, "un-supported IUNIT device\n");
1707	1683	err = -ENODEV;
1708	1684	goto atomisp_dev_alloc_fail;
1709	1685	}
1710	1686
1711		− dev_info(&dev->dev, "ISP HPLL frequency base = %d MHz\n",
1712		− isp->hpll_freq);
	1687	+ dev_info(&pdev->dev, "ISP HPLL frequency base = %d MHz\n", isp->hpll_freq);
1713	1688
1714	1689	isp->max_isr_latency = ATOMISP_MAX_ISR_LATENCY;
1715	1690
@@ -1718,30 +1693,28 @@ static int atomisp_pci_probe(struct pci_dev *dev, · 2 unmodified lines
1718	1693	isp->firmware = atomisp_load_firmware(isp);
1719	1694	if (!isp->firmware) {
1720	1695	err = -ENOENT;
1721		− dev_dbg(&dev->dev, "Firmware load failed\n");
	1696	+ dev_dbg(&pdev->dev, "Firmware load failed\n");
1722	1697	goto load_fw_fail;
1723	1698	}
1724	1699
1725		− err = sh_css_check_firmware_version(isp->dev,
1726		− isp->firmware->data);
	1700	+ err = sh_css_check_firmware_version(isp->dev, isp->firmware->data);
1727	1701	if (err) {
1728		− dev_dbg(&dev->dev, "Firmware version check failed\n");
	1702	+ dev_dbg(&pdev->dev, "Firmware version check failed\n");
1729	1703	goto fw_validation_fail;
1730	1704	}
1731	1705	} else {
1732		− dev_info(&dev->dev, "Firmware load will be deferred\n");
	1706	+ dev_info(&pdev->dev, "Firmware load will be deferred\n");
1733	1707	}
1734	1708
1735		− pci_set_master(dev);
1736		− pci_set_drvdata(dev, isp);
	1709	+ pci_set_master(pdev);
1737	1710
1738		− err = pci_enable_msi(dev);
	1711	+ err = pci_enable_msi(pdev);
1739	1712	if (err) {
1740		− dev_err(&dev->dev, "Failed to enable msi (%d)\n", err);
	1713	+ dev_err(&pdev->dev, "Failed to enable msi (%d)\n", err);
1741	1714	goto enable_msi_fail;
1742	1715	}
1743	1716
1744		− atomisp_msi_irq_init(isp, dev);
	1717	+ atomisp_msi_irq_init(isp);
1745	1718
1746	1719	cpu_latency_qos_add_request(&isp->pm_qos, PM_QOS_DEFAULT_VALUE);
1747	1720
@@ -1762,8 +1735,7 @@ static int atomisp_pci_probe(struct pci_dev *dev, · 14 unmodified lines
1762	1735	* Workaround for imbalance data eye issue which is observed
1763	1736	* on TNG B0.
1764	1737	*/
1765		− pci_read_config_dword(dev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL,
1766		− &csi_afe_trim);
	1738	+ pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, &csi_afe_trim);
1767	1739	csi_afe_trim &= ~((MRFLD_PCI_CSI_HSRXCLKTRIM_MASK <<
1768	1740	MRFLD_PCI_CSI1_HSRXCLKTRIM_SHIFT) \|
1769	1741	(MRFLD_PCI_CSI_HSRXCLKTRIM_MASK <<
@@ -1776,20 +1748,18 @@ static int atomisp_pci_probe(struct pci_dev *dev, · 6 unmodified lines
1776	1748	MRFLD_PCI_CSI2_HSRXCLKTRIM_SHIFT) \|
1777	1749	(MRFLD_PCI_CSI3_HSRXCLKTRIM <<
1778	1750	MRFLD_PCI_CSI3_HSRXCLKTRIM_SHIFT);
1779		− pci_write_config_dword(dev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL,
1780		− csi_afe_trim);
	1751	+ pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, csi_afe_trim);
1781	1752	}
1782	1753
1783	1754	err = atomisp_initialize_modules(isp);
1784	1755	if (err < 0) {
1785		− dev_err(&dev->dev, "atomisp_initialize_modules (%d)\n", err);
	1756	+ dev_err(&pdev->dev, "atomisp_initialize_modules (%d)\n", err);
1786	1757	goto initialize_modules_fail;
1787	1758	}
1788	1759
1789	1760	err = atomisp_register_entities(isp);
1790	1761	if (err < 0) {
1791		− dev_err(&dev->dev, "atomisp_register_entities failed (%d)\n",
1792		− err);
	1762	+ dev_err(&pdev->dev, "atomisp_register_entities failed (%d)\n", err);
1793	1763	goto register_entities_fail;
1794	1764	}
1795	1765	err = atomisp_create_pads_links(isp);
@@ -1802,24 +1772,24 @@ static int atomisp_pci_probe(struct pci_dev *dev, · 6 unmodified lines
1802	1772	/* save the iunit context only once after all the values are init'ed. */
1803	1773	atomisp_save_iunit_reg(isp);
1804	1774
1805		− pm_runtime_put_noidle(&dev->dev);
1806		− pm_runtime_allow(&dev->dev);
	1775	+ pm_runtime_put_noidle(&pdev->dev);
	1776	+ pm_runtime_allow(&pdev->dev);
1807	1777
1808	1778	hmm_init_mem_stat(repool_pgnr, dypool_enable, dypool_pgnr);
1809	1779	err = hmm_pool_register(repool_pgnr, HMM_POOL_TYPE_RESERVED);
1810	1780	if (err) {
1811		− dev_err(&dev->dev, "Failed to register reserved memory pool.\n");
	1781	+ dev_err(&pdev->dev, "Failed to register reserved memory pool.\n");
1812	1782	goto hmm_pool_fail;
1813	1783	}
1814	1784
1815	1785	/* Init ISP memory management */
1816	1786	hmm_init();
1817	1787
1818		− err = devm_request_threaded_irq(&dev->dev, dev->irq,
	1788	+ err = devm_request_threaded_irq(&pdev->dev, pdev->irq,
1819	1789	atomisp_isr, atomisp_isr_thread,
1820	1790	IRQF_SHARED, "isp_irq", isp);
1821	1791	if (err) {
1822		− dev_err(&dev->dev, "Failed to request irq (%d)\n", err);
	1792	+ dev_err(&pdev->dev, "Failed to request irq (%d)\n", err);
1823	1793	goto request_irq_fail;
1824	1794	}
1825	1795
@@ -1827,23 +1797,23 @@ static int atomisp_pci_probe(struct pci_dev *dev, · 1 unmodified line
1827	1797	if (!defer_fw_load) {
1828	1798	err = atomisp_css_load_firmware(isp);
1829	1799	if (err) {
1830		− dev_err(&dev->dev, "Failed to init css.\n");
	1800	+ dev_err(&pdev->dev, "Failed to init css.\n");
1831	1801	goto css_init_fail;
1832	1802	}
1833	1803	} else {
1834		− dev_dbg(&dev->dev, "Skip css init.\n");
	1804	+ dev_dbg(&pdev->dev, "Skip css init.\n");
1835	1805	}
1836	1806	/* Clear FW image from memory */
1837	1807	release_firmware(isp->firmware);
1838	1808	isp->firmware = NULL;
1839	1809	isp->css_env.isp_css_fw.data = NULL;
1840	1810
1841		− atomisp_drvfs_init(&dev->driver->driver, isp);
	1811	+ atomisp_drvfs_init(isp);
1842	1812
1843	1813	return 0;
1844	1814
1845	1815	css_init_fail:
1846		− devm_free_irq(&dev->dev, dev->irq, isp);
	1816	+ devm_free_irq(&pdev->dev, pdev->irq, isp);
1847	1817	request_irq_fail:
1848	1818	hmm_cleanup();
1849	1819	hmm_pool_unregister(HMM_POOL_TYPE_RESERVED);
@@ -1856,8 +1826,8 @@ register_entities_fail: · 6 unmodified lines
1856	1826	atomisp_uninitialize_modules(isp);
1857	1827	initialize_modules_fail:
1858	1828	cpu_latency_qos_remove_request(&isp->pm_qos);
1859		− atomisp_msi_irq_uninit(isp, dev);
1860		− pci_disable_msi(dev);
	1829	+ atomisp_msi_irq_uninit(isp);
	1830	+ pci_disable_msi(pdev);
1861	1831	enable_msi_fail:
1862	1832	fw_validation_fail:
1863	1833	release_firmware(isp->firmware);
@@ -1869,35 +1839,34 @@ load_fw_fail: · 5 unmodified lines
1869	1839	* The following lines have been copied from atomisp suspend path
1870	1840	*/
1871	1841
1872		− pci_read_config_dword(dev, PCI_INTERRUPT_CTRL, &irq);
	1842	+ pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
1873	1843	irq = irq & 1 << INTR_IIR;
1874		− pci_write_config_dword(dev, PCI_INTERRUPT_CTRL, irq);
	1844	+ pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq);
1875	1845
1876		− pci_read_config_dword(dev, PCI_INTERRUPT_CTRL, &irq);
	1846	+ pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
1877	1847	irq &= ~(1 << INTR_IER);
1878		− pci_write_config_dword(dev, PCI_INTERRUPT_CTRL, irq);
	1848	+ pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq);
1879	1849
1880		− atomisp_msi_irq_uninit(isp, dev);
	1850	+ atomisp_msi_irq_uninit(isp);
1881	1851
1882	1852	atomisp_ospm_dphy_down(isp);
1883	1853
1884	1854	/* Address later when we worry about the ...field chips */
1885	1855	if (IS_ENABLED(CONFIG_PM) && atomisp_mrfld_power_down(isp))
1886		− dev_err(&dev->dev, "Failed to switch off ISP\n");
	1856	+ dev_err(&pdev->dev, "Failed to switch off ISP\n");
1887	1857
1888	1858	atomisp_dev_alloc_fail:
1889		− pcim_iounmap_regions(dev, 1 << ATOM_ISP_PCI_BAR);
	1859	+ pcim_iounmap_regions(pdev, 1 << ATOM_ISP_PCI_BAR);
1890	1860
1891	1861	ioremap_fail:
1892	1862	return err;
1893	1863	}
1894	1864
1895		−static void atomisp_pci_remove(struct pci_dev *dev)
	1865	+static void atomisp_pci_remove(struct pci_dev *pdev)
1896	1866	{
1897		− struct atomisp_device isp = (struct atomisp_device )
1898		− pci_get_drvdata(dev);
	1867	+ struct atomisp_device *isp = pci_get_drvdata(pdev);
1899	1868
1900		− dev_info(&dev->dev, "Removing atomisp driver\n");
	1869	+ dev_info(&pdev->dev, "Removing atomisp driver\n");
1901	1870
1902	1871	atomisp_drvfs_exit();
1903	1872
@@ -1906,11 +1875,11 @@ static void atomisp_pci_remove(struct pci_dev *dev) · 2 unmodified lines
1906	1875	ia_css_unload_firmware();
1907	1876	hmm_cleanup();
1908	1877
1909		− pm_runtime_forbid(&dev->dev);
1910		− pm_runtime_get_noresume(&dev->dev);
	1878	+ pm_runtime_forbid(&pdev->dev);
	1879	+ pm_runtime_get_noresume(&pdev->dev);
1911	1880	cpu_latency_qos_remove_request(&isp->pm_qos);
1912	1881
1913		− atomisp_msi_irq_uninit(isp, dev);
	1882	+ atomisp_msi_irq_uninit(isp);
1914	1883	atomisp_unregister_entities(isp);
1915	1884
1916	1885	destroy_workqueue(isp->wdt_work_queue);

drivers/staging/media/atomisp/pci/base/refcount/src/refcount.c+14−14

@@ -48,7 +48,7 @@ static struct ia_css_refcount_entry *refcount_find_entry(ia_css_ptr ptr, · 47 unmodified lines
48	48	return NULL;
49	49	if (!myrefcount.items) {
50	50	ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR,
51		− "refcount_find_entry(): Ref count not initialized!\n");
	51	+ "%s(): Ref count not initialized!\n", __func__);
52	52	return NULL;
53	53	}
54	54
@@ -73,12 +73,12 @@ int ia_css_refcount_init(uint32_t size) · 18 unmodified lines
73	73
74	74	if (size == 0) {
75	75	ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
76		− "ia_css_refcount_init(): Size of 0 for Ref count init!\n");
	76	+ "%s(): Size of 0 for Ref count init!\n", __func__);
77	77	return -EINVAL;
78	78	}
79	79	if (myrefcount.items) {
80	80	ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
81		− "ia_css_refcount_init(): Ref count is already initialized\n");
	81	+ "%s(): Ref count is already initialized\n", __func__);
82	82	return -EINVAL;
83	83	}
84	84	myrefcount.items =
@@ -99,7 +99,7 @@ void ia_css_refcount_uninit(void) · 14 unmodified lines
99	99	u32 i;
100	100
101	101	ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
102		− "ia_css_refcount_uninit() entry\n");
	102	+ "%s() entry\n", __func__);
103	103	for (i = 0; i < myrefcount.size; i++) {
104	104	/* driver verifier tool has issues with &arr[i]
105	105	and prefers arr + i; as these are actually equivalent
@@ -120,7 +120,7 @@ void ia_css_refcount_uninit(void) · 14 unmodified lines
120	120	myrefcount.items = NULL;
121	121	myrefcount.size = 0;
122	122	ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
123		− "ia_css_refcount_uninit() leave\n");
	123	+ "%s() leave\n", __func__);
124	124	}
125	125
126	126	ia_css_ptr ia_css_refcount_increment(s32 id, ia_css_ptr ptr)
@@ -133,7 +133,7 @@ ia_css_ptr ia_css_refcount_increment(s32 id, ia_css_ptr ptr) · 6 unmodified lines
133	133	entry = refcount_find_entry(ptr, false);
134	134
135	135	ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
136		− "ia_css_refcount_increment(%x) 0x%x\n", id, ptr);
	136	+ "%s(%x) 0x%x\n", __func__, id, ptr);
137	137
138	138	if (!entry) {
139	139	entry = refcount_find_entry(ptr, true);
@@ -145,7 +145,7 @@ ia_css_ptr ia_css_refcount_increment(s32 id, ia_css_ptr ptr) · 5 unmodified lines
145	145
146	146	if (entry->id != id) {
147	147	ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR,
148		− "ia_css_refcount_increment(): Ref count IDS do not match!\n");
	148	+ "%s(): Ref count IDS do not match!\n", __func__);
149	149	return mmgr_NULL;
150	150	}
151	151
@@ -165,7 +165,7 @@ bool ia_css_refcount_decrement(s32 id, ia_css_ptr ptr) · 13 unmodified lines
165	165	struct ia_css_refcount_entry *entry;
166	166
167	167	ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
168		− "ia_css_refcount_decrement(%x) 0x%x\n", id, ptr);
	168	+ "%s(%x) 0x%x\n", __func__, id, ptr);
169	169
170	170	if (ptr == mmgr_NULL)
171	171	return false;
@@ -175,7 +175,7 @@ bool ia_css_refcount_decrement(s32 id, ia_css_ptr ptr) · 3 unmodified lines
175	175	if (entry) {
176	176	if (entry->id != id) {
177	177	ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR,
178		− "ia_css_refcount_decrement(): Ref count IDS do not match!\n");
	178	+ "%s(): Ref count IDS do not match!\n", __func__);
179	179	return false;
180	180	}
181	181	if (entry->count > 0) {
@@ -225,8 +225,8 @@ void ia_css_refcount_clear(s32 id, clear_func clear_func_ptr) · 43 unmodified lines
225	225	u32 count = 0;
226	226
227	227	assert(clear_func_ptr);
228		− ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_refcount_clear(%x)\n",
229		− id);
	228	+ ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s(%x)\n",
	229	+ __func__, id);
230	230
231	231	for (i = 0; i < myrefcount.size; i++) {
232	232	/* driver verifier tool has issues with &arr[i]
@@ -236,14 +236,14 @@ void ia_css_refcount_clear(s32 id, clear_func clear_func_ptr) · 3 unmodified lines
236	236	entry = myrefcount.items + i;
237	237	if ((entry->data != mmgr_NULL) && (entry->id == id)) {
238	238	ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
239		− "ia_css_refcount_clear: %x: 0x%x\n",
	239	+ "%s: %x: 0x%x\n", __func__,
240	240	id, entry->data);
241	241	if (clear_func_ptr) {
242	242	/* clear using provided function */
243	243	clear_func_ptr(entry->data);
244	244	} else {
245	245	ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
246		− "ia_css_refcount_clear: using hmm_free: no clear_func\n");
	246	+ "%s: using hmm_free: no clear_func\n", __func__);
247	247	hmm_free(entry->data);
248	248	}
249	249
@@ -260,7 +260,7 @@ void ia_css_refcount_clear(s32 id, clear_func clear_func_ptr) · 10 unmodified lines
260	260	}
261	261	}
262	262	ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
263		− "ia_css_refcount_clear(%x): cleared %d\n", id,
	263	+ "%s(%x): cleared %d\n", __func__, id,
264	264	count);
265	265	}
266	266

drivers/staging/media/atomisp/pci/hive_types.h+3−21

@@ -52,32 +52,14 @@ typedef unsigned short hive_uint16; · 51 unmodified lines
52	52	typedef unsigned int hive_uint32;
53	53	typedef unsigned long long hive_uint64;
54	54
55		−/* by default assume 32 bit master port (both data and address) */
56		−#ifndef HRT_DATA_WIDTH
57		−#define HRT_DATA_WIDTH 32
58		−#endif
59		−#ifndef HRT_ADDRESS_WIDTH
60		−#define HRT_ADDRESS_WIDTH 32
61		−#endif
62		−
	55	+#define HRT_DATA_WIDTH 32
	56	+#define HRT_ADDRESS_WIDTH 64
63	57	#define HRT_DATA_BYTES (HRT_DATA_WIDTH / 8)
64	58	#define HRT_ADDRESS_BYTES (HRT_ADDRESS_WIDTH / 8)
	59	+#define SIZEOF_HRT_REG (HRT_DATA_WIDTH >> 3)
65	60
66		−#if HRT_DATA_WIDTH == 64
67		−typedef hive_uint64 hrt_data;
68		−#elif HRT_DATA_WIDTH == 32
69	61	typedef hive_uint32 hrt_data;
70		−#else
71		−#error data width not supported
72		−#endif
73		−
74		−#if HRT_ADDRESS_WIDTH == 64
75	62	typedef hive_uint64 hrt_address;
76		−#elif HRT_ADDRESS_WIDTH == 32
77		−typedef hive_uint32 hrt_address;
78		−#else
79		−#error adddres width not supported
80		−#endif
81	63
82	64	/* use 64 bit addresses in simulation, where possible */
83	65	typedef hive_uint64 hive_sim_address;

drivers/staging/media/atomisp/pci/hmm/hmm.c+5−5

@@ -735,11 +735,11 @@ ia_css_ptr hmm_host_vaddr_to_hrt_vaddr(const void *ptr) · 734 unmodified lines
735	735
736	736	void hmm_show_mem_stat(const char *func, const int line)
737	737	{
738		− trace_printk("tol_cnt=%d usr_size=%d res_size=%d res_cnt=%d sys_size=%d dyc_thr=%d dyc_size=%d.\n",
739		− hmm_mem_stat.tol_cnt,
740		− hmm_mem_stat.usr_size, hmm_mem_stat.res_size,
741		− hmm_mem_stat.res_cnt, hmm_mem_stat.sys_size,
742		− hmm_mem_stat.dyc_thr, hmm_mem_stat.dyc_size);
	738	+ pr_info("tol_cnt=%d usr_size=%d res_size=%d res_cnt=%d sys_size=%d dyc_thr=%d dyc_size=%d.\n",
	739	+ hmm_mem_stat.tol_cnt,
	740	+ hmm_mem_stat.usr_size, hmm_mem_stat.res_size,
	741	+ hmm_mem_stat.res_cnt, hmm_mem_stat.sys_size,
	742	+ hmm_mem_stat.dyc_thr, hmm_mem_stat.dyc_size);
743	743	}
744	744
745	745	void hmm_init_mem_stat(int res_pgnr, int dyc_en, int dyc_pgnr)

drivers/staging/media/atomisp/pci/isp2400_system_global.h+0−302

@@ -13,306 +13,4 @@ · 12 unmodified lines
13	13	* more details.
14	14	*/
15	15
16		−#ifndef __SYSTEM_GLOBAL_H_INCLUDED__
17		−#define __SYSTEM_GLOBAL_H_INCLUDED__
18		−
19		−#include <hive_isp_css_defs.h>
20		−#include <type_support.h>
21		−
22		−/*
23		− * The longest allowed (uninteruptible) bus transfer, does not
24		− * take stalling into account
25		− */
26		−#define HIVE_ISP_MAX_BURST_LENGTH 1024
27		−
28		−/*
29		− * Maximum allowed burst length in words for the ISP DMA
30		− */
31		−#define ISP_DMA_MAX_BURST_LENGTH 128
32		−
33		−/*
34		− * Create a list of HAS and IS properties that defines the system
35		− *
36		− * The configuration assumes the following
37		− * - The system is hetereogeneous; Multiple cells and devices classes
38		− * - The cell and device instances are homogeneous, each device type
39		− * belongs to the same class
40		− * - Device instances supporting a subset of the class capabilities are
41		− * allowed
42		− *
43		− * We could manage different device classes through the enumerated
44		− * lists (C) or the use of classes (C++), but that is presently not
45		− * fully supported
46		− *
47		− * N.B. the 3 input formatters are of 2 different classess
48		− */
49		−
50	16	#define USE_INPUT_SYSTEM_VERSION_2
51		−
52		−#define HAS_MMU_VERSION_2
53		−#define HAS_DMA_VERSION_2
54		−#define HAS_GDC_VERSION_2
55		−#define HAS_VAMEM_VERSION_2
56		−#define HAS_HMEM_VERSION_1
57		−#define HAS_BAMEM_VERSION_2
58		−#define HAS_IRQ_VERSION_2
59		−#define HAS_IRQ_MAP_VERSION_2
60		−#define HAS_INPUT_FORMATTER_VERSION_2
61		−/* 2401: HAS_INPUT_SYSTEM_VERSION_2401 */
62		−#define HAS_INPUT_SYSTEM_VERSION_2
63		−#define HAS_BUFFERED_SENSOR
64		−#define HAS_FIFO_MONITORS_VERSION_2
65		−/* #define HAS_GP_REGS_VERSION_2 */
66		−#define HAS_GP_DEVICE_VERSION_2
67		−#define HAS_GPIO_VERSION_1
68		−#define HAS_TIMED_CTRL_VERSION_1
69		−#define HAS_RX_VERSION_2
70		−
71		−#define DMA_DDR_TO_VAMEM_WORKAROUND
72		−#define DMA_DDR_TO_HMEM_WORKAROUND
73		−
74		−/*
75		− * Semi global. "HRT" is accessible from SP, but the HRT types do not fully apply
76		− */
77		−#define HRT_VADDRESS_WIDTH 32
78		−//#define HRT_ADDRESS_WIDTH 64 /* Surprise, this is a local property*/
79		−#define HRT_DATA_WIDTH 32
80		−
81		−#define SIZEOF_HRT_REG (HRT_DATA_WIDTH >> 3)
82		−#define HIVE_ISP_CTRL_DATA_BYTES (HIVE_ISP_CTRL_DATA_WIDTH / 8)
83		−
84		−/* The main bus connecting all devices */
85		−#define HRT_BUS_WIDTH HIVE_ISP_CTRL_DATA_WIDTH
86		−#define HRT_BUS_BYTES HIVE_ISP_CTRL_DATA_BYTES
87		−
88		−/* per-frame parameter handling support */
89		−#define SH_CSS_ENABLE_PER_FRAME_PARAMS
90		−
91		−typedef u32 hrt_bus_align_t;
92		−
93		−/*
94		− * Enumerate the devices, device access through the API is by ID, through the DLI by address
95		− * The enumerator terminators are used to size the wiring arrays and as an exception value.
96		− */
97		−typedef enum {
98		− DDR0_ID = 0,
99		− N_DDR_ID
100		−} ddr_ID_t;
101		−
102		−typedef enum {
103		− ISP0_ID = 0,
104		− N_ISP_ID
105		−} isp_ID_t;
106		−
107		−typedef enum {
108		− SP0_ID = 0,
109		− N_SP_ID
110		−} sp_ID_t;
111		−
112		−typedef enum {
113		− MMU0_ID = 0,
114		− MMU1_ID,
115		− N_MMU_ID
116		−} mmu_ID_t;
117		−
118		−typedef enum {
119		− DMA0_ID = 0,
120		− N_DMA_ID
121		−} dma_ID_t;
122		−
123		−typedef enum {
124		− GDC0_ID = 0,
125		− GDC1_ID,
126		− N_GDC_ID
127		−} gdc_ID_t;
128		−
129		−#define N_GDC_ID_CPP 2 // this extra define is needed because we want to use it also in the preprocessor, and that doesn't work with enums.
130		−
131		−typedef enum {
132		− VAMEM0_ID = 0,
133		− VAMEM1_ID,
134		− VAMEM2_ID,
135		− N_VAMEM_ID
136		−} vamem_ID_t;
137		−
138		−typedef enum {
139		− BAMEM0_ID = 0,
140		− N_BAMEM_ID
141		−} bamem_ID_t;
142		−
143		−typedef enum {
144		− HMEM0_ID = 0,
145		− N_HMEM_ID
146		−} hmem_ID_t;
147		−
148		−/*
149		−typedef enum {
150		− IRQ0_ID = 0,
151		− N_IRQ_ID
152		−} irq_ID_t;
153		−*/
154		−
155		−typedef enum {
156		− IRQ0_ID = 0, // GP IRQ block
157		− IRQ1_ID, // Input formatter
158		− IRQ2_ID, // input system
159		− IRQ3_ID, // input selector
160		− N_IRQ_ID
161		−} irq_ID_t;
162		−
163		−typedef enum {
164		− FIFO_MONITOR0_ID = 0,
165		− N_FIFO_MONITOR_ID
166		−} fifo_monitor_ID_t;
167		−
168		−/*
169		− * Deprecated: Since all gp_reg instances are different
170		− * and put in the address maps of other devices we cannot
171		− * enumerate them as that assumes the instrances are the
172		− * same.
173		− *
174		− * We define a single GP_DEVICE containing all gp_regs
175		− * w.r.t. a single base address
176		− *
177		−typedef enum {
178		− GP_REGS0_ID = 0,
179		− N_GP_REGS_ID
180		−} gp_regs_ID_t;
181		− */
182		−typedef enum {
183		− GP_DEVICE0_ID = 0,
184		− N_GP_DEVICE_ID
185		−} gp_device_ID_t;
186		−
187		−typedef enum {
188		− GP_TIMER0_ID = 0,
189		− GP_TIMER1_ID,
190		− GP_TIMER2_ID,
191		− GP_TIMER3_ID,
192		− GP_TIMER4_ID,
193		− GP_TIMER5_ID,
194		− GP_TIMER6_ID,
195		− GP_TIMER7_ID,
196		− N_GP_TIMER_ID
197		−} gp_timer_ID_t;
198		−
199		−typedef enum {
200		− GPIO0_ID = 0,
201		− N_GPIO_ID
202		−} gpio_ID_t;
203		−
204		−typedef enum {
205		− TIMED_CTRL0_ID = 0,
206		− N_TIMED_CTRL_ID
207		−} timed_ctrl_ID_t;
208		−
209		−typedef enum {
210		− INPUT_FORMATTER0_ID = 0,
211		− INPUT_FORMATTER1_ID,
212		− INPUT_FORMATTER2_ID,
213		− INPUT_FORMATTER3_ID,
214		− N_INPUT_FORMATTER_ID
215		−} input_formatter_ID_t;
216		−
217		−/* The IF RST is outside the IF */
218		−#define INPUT_FORMATTER0_SRST_OFFSET 0x0824
219		−#define INPUT_FORMATTER1_SRST_OFFSET 0x0624
220		−#define INPUT_FORMATTER2_SRST_OFFSET 0x0424
221		−#define INPUT_FORMATTER3_SRST_OFFSET 0x0224
222		−
223		−#define INPUT_FORMATTER0_SRST_MASK 0x0001
224		−#define INPUT_FORMATTER1_SRST_MASK 0x0002
225		−#define INPUT_FORMATTER2_SRST_MASK 0x0004
226		−#define INPUT_FORMATTER3_SRST_MASK 0x0008
227		−
228		−typedef enum {
229		− INPUT_SYSTEM0_ID = 0,
230		− N_INPUT_SYSTEM_ID
231		−} input_system_ID_t;
232		−
233		−typedef enum {
234		− RX0_ID = 0,
235		− N_RX_ID
236		−} rx_ID_t;
237		−
238		−enum mipi_port_id {
239		− MIPI_PORT0_ID = 0,
240		− MIPI_PORT1_ID,
241		− MIPI_PORT2_ID,
242		− N_MIPI_PORT_ID
243		−};
244		−
245		−#define N_RX_CHANNEL_ID 4
246		−
247		−/* Generic port enumeration with an internal port type ID */
248		−typedef enum {
249		− CSI_PORT0_ID = 0,
250		− CSI_PORT1_ID,
251		− CSI_PORT2_ID,
252		− TPG_PORT0_ID,
253		− PRBS_PORT0_ID,
254		− FIFO_PORT0_ID,
255		− MEMORY_PORT0_ID,
256		− N_INPUT_PORT_ID
257		−} input_port_ID_t;
258		−
259		−typedef enum {
260		− CAPTURE_UNIT0_ID = 0,
261		− CAPTURE_UNIT1_ID,
262		− CAPTURE_UNIT2_ID,
263		− ACQUISITION_UNIT0_ID,
264		− DMA_UNIT0_ID,
265		− CTRL_UNIT0_ID,
266		− GPREGS_UNIT0_ID,
267		− FIFO_UNIT0_ID,
268		− IRQ_UNIT0_ID,
269		− N_SUB_SYSTEM_ID
270		−} sub_system_ID_t;
271		−
272		−#define N_CAPTURE_UNIT_ID 3
273		−#define N_ACQUISITION_UNIT_ID 1
274		−#define N_CTRL_UNIT_ID 1
275		−
276		−enum ia_css_isp_memories {
277		− IA_CSS_ISP_PMEM0 = 0,
278		− IA_CSS_ISP_DMEM0,
279		− IA_CSS_ISP_VMEM0,
280		− IA_CSS_ISP_VAMEM0,
281		− IA_CSS_ISP_VAMEM1,
282		− IA_CSS_ISP_VAMEM2,
283		− IA_CSS_ISP_HMEM0,
284		− IA_CSS_SP_DMEM0,
285		− IA_CSS_DDR,
286		− N_IA_CSS_MEMORIES
287		−};
288		−
289		−#define IA_CSS_NUM_MEMORIES 9
290		−/* For driver compatibility */
291		−#define N_IA_CSS_ISP_MEMORIES IA_CSS_NUM_MEMORIES
292		−#define IA_CSS_NUM_ISP_MEMORIES IA_CSS_NUM_MEMORIES
293		−
294		−#if 0
295		−typedef enum {
296		− dev_chn, /* device channels, external resource */
297		− ext_mem, /* external memories */
298		− int_mem, /* internal memories */
299		− int_chn /* internal channels, user defined */
300		−} resource_type_t;
301		−
302		−/* if this enum is extended with other memory resources, pls also extend the function resource_to_memptr() */
303		−typedef enum {
304		− vied_nci_dev_chn_dma_ext0,
305		− int_mem_vmem0,
306		− int_mem_dmem0
307		−} resource_id_t;
308		−
309		−/* enum listing the different memories within a program group.
310		− This enum is used in the mem_ptr_t type */
311		−typedef enum {
312		− buf_mem_invalid = 0,
313		− buf_mem_vmem_prog0,
314		− buf_mem_dmem_prog0
315		−} buf_mem_t;
316		−
317		−#endif
318		−#endif /* __SYSTEM_GLOBAL_H_INCLUDED__ */

drivers/staging/media/atomisp/pci/isp2400_system_local.h+0−321

@@ -1,321 +0,0 @@
1		−/* SPDX-License-Identifier: GPL-2.0 */
2		−/*
3		− * Support for Intel Camera Imaging ISP subsystem.
4		− * Copyright (c) 2010-2015, Intel Corporation.
5		− *
6		− * This program is free software; you can redistribute it and/or modify it
7		− * under the terms and conditions of the GNU General Public License,
8		− * version 2, as published by the Free Software Foundation.
9		− *
10		− * This program is distributed in the hope it will be useful, but WITHOUT
11		− * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12		− * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13		− * more details.
14		− */
15		−
16		−#ifndef __SYSTEM_LOCAL_H_INCLUDED__
17		−#define __SYSTEM_LOCAL_H_INCLUDED__
18		−
19		−#ifdef HRT_ISP_CSS_CUSTOM_HOST
20		−#ifndef HRT_USE_VIR_ADDRS
21		−#define HRT_USE_VIR_ADDRS
22		−#endif
23		−#endif
24		−
25		−#include "system_global.h"
26		−
27		−/* HRT assumes 32 by default (see Linux/include/hive_types.h), overrule it in case it is different */
28		−#undef HRT_ADDRESS_WIDTH
29		−#define HRT_ADDRESS_WIDTH 64 /* Surprise, this is a local property */
30		−
31		−/* This interface is deprecated */
32		−#include "hive_types.h"
33		−
34		−/*
35		− * Cell specific address maps
36		− */
37		−#if HRT_ADDRESS_WIDTH == 64
38		−
39		−#define GP_FIFO_BASE ((hrt_address)0x0000000000090104) /* This is NOT a base address */
40		−
41		−/* DDR */
42		−static const hrt_address DDR_BASE[N_DDR_ID] = {
43		− (hrt_address)0x0000000120000000ULL
44		−};
45		−
46		−/* ISP */
47		−static const hrt_address ISP_CTRL_BASE[N_ISP_ID] = {
48		− (hrt_address)0x0000000000020000ULL
49		−};
50		−
51		−static const hrt_address ISP_DMEM_BASE[N_ISP_ID] = {
52		− (hrt_address)0x0000000000200000ULL
53		−};
54		−
55		−static const hrt_address ISP_BAMEM_BASE[N_BAMEM_ID] = {
56		− (hrt_address)0x0000000000100000ULL
57		−};
58		−
59		−static const hrt_address ISP_VAMEM_BASE[N_VAMEM_ID] = {
60		− (hrt_address)0x00000000001C0000ULL,
61		− (hrt_address)0x00000000001D0000ULL,
62		− (hrt_address)0x00000000001E0000ULL
63		−};
64		−
65		−static const hrt_address ISP_HMEM_BASE[N_HMEM_ID] = {
66		− (hrt_address)0x00000000001F0000ULL
67		−};
68		−
69		−/* SP */
70		−static const hrt_address SP_CTRL_BASE[N_SP_ID] = {
71		− (hrt_address)0x0000000000010000ULL
72		−};
73		−
74		−static const hrt_address SP_DMEM_BASE[N_SP_ID] = {
75		− (hrt_address)0x0000000000300000ULL
76		−};
77		−
78		−static const hrt_address SP_PMEM_BASE[N_SP_ID] = {
79		− (hrt_address)0x00000000000B0000ULL
80		−};
81		−
82		−/* MMU */
83		−/*
84		− * MMU0_ID: The data MMU
85		− * MMU1_ID: The icache MMU
86		− */
87		−static const hrt_address MMU_BASE[N_MMU_ID] = {
88		− (hrt_address)0x0000000000070000ULL,
89		− (hrt_address)0x00000000000A0000ULL
90		−};
91		−
92		−/* DMA */
93		−static const hrt_address DMA_BASE[N_DMA_ID] = {
94		− (hrt_address)0x0000000000040000ULL
95		−};
96		−
97		−/* IRQ */
98		−static const hrt_address IRQ_BASE[N_IRQ_ID] = {
99		− (hrt_address)0x0000000000000500ULL,
100		− (hrt_address)0x0000000000030A00ULL,
101		− (hrt_address)0x000000000008C000ULL,
102		− (hrt_address)0x0000000000090200ULL
103		−};
104		−
105		−/*
106		− (hrt_address)0x0000000000000500ULL};
107		− */
108		−
109		−/* GDC */
110		−static const hrt_address GDC_BASE[N_GDC_ID] = {
111		− (hrt_address)0x0000000000050000ULL,
112		− (hrt_address)0x0000000000060000ULL
113		−};
114		−
115		−/* FIFO_MONITOR (not a subset of GP_DEVICE) */
116		−static const hrt_address FIFO_MONITOR_BASE[N_FIFO_MONITOR_ID] = {
117		− (hrt_address)0x0000000000000000ULL
118		−};
119		−
120		−/*
121		−static const hrt_address GP_REGS_BASE[N_GP_REGS_ID] = {
122		− (hrt_address)0x0000000000000000ULL};
123		−
124		−static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = {
125		− (hrt_address)0x0000000000090000ULL};
126		−*/
127		−
128		−/* GP_DEVICE (single base for all separate GP_REG instances) */
129		−static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = {
130		− (hrt_address)0x0000000000000000ULL
131		−};
132		−
133		−/*GP TIMER , all timer registers are inter-twined,
134		− * so, having multiple base addresses for
135		− * different timers does not help*/
136		−static const hrt_address GP_TIMER_BASE =
137		− (hrt_address)0x0000000000000600ULL;
138		−/* GPIO */
139		−static const hrt_address GPIO_BASE[N_GPIO_ID] = {
140		− (hrt_address)0x0000000000000400ULL
141		−};
142		−
143		−/* TIMED_CTRL */
144		−static const hrt_address TIMED_CTRL_BASE[N_TIMED_CTRL_ID] = {
145		− (hrt_address)0x0000000000000100ULL
146		−};
147		−
148		−/* INPUT_FORMATTER */
149		−static const hrt_address INPUT_FORMATTER_BASE[N_INPUT_FORMATTER_ID] = {
150		− (hrt_address)0x0000000000030000ULL,
151		− (hrt_address)0x0000000000030200ULL,
152		− (hrt_address)0x0000000000030400ULL,
153		− (hrt_address)0x0000000000030600ULL
154		−}; /* memcpy() */
155		−
156		−/* INPUT_SYSTEM */
157		−static const hrt_address INPUT_SYSTEM_BASE[N_INPUT_SYSTEM_ID] = {
158		− (hrt_address)0x0000000000080000ULL
159		−};
160		−
161		−/* (hrt_address)0x0000000000081000ULL, / / capture A */
162		−/* (hrt_address)0x0000000000082000ULL, / / capture B */
163		−/* (hrt_address)0x0000000000083000ULL, / / capture C */
164		−/* (hrt_address)0x0000000000084000ULL, / / Acquisition */
165		−/* (hrt_address)0x0000000000085000ULL, / / DMA */
166		−/* (hrt_address)0x0000000000089000ULL, / / ctrl */
167		−/* (hrt_address)0x000000000008A000ULL, / / GP regs */
168		−/* (hrt_address)0x000000000008B000ULL, / / FIFO */
169		−/* (hrt_address)0x000000000008C000ULL, / / IRQ */
170		−
171		−/* RX, the MIPI lane control regs start at offset 0 */
172		−static const hrt_address RX_BASE[N_RX_ID] = {
173		− (hrt_address)0x0000000000080100ULL
174		−};
175		−
176		−#elif HRT_ADDRESS_WIDTH == 32
177		−
178		−#define GP_FIFO_BASE ((hrt_address)0x00090104) /* This is NOT a base address */
179		−
180		−/* DDR : Attention, this value not defined in 32-bit */
181		−static const hrt_address DDR_BASE[N_DDR_ID] = {
182		− (hrt_address)0x00000000UL
183		−};
184		−
185		−/* ISP */
186		−static const hrt_address ISP_CTRL_BASE[N_ISP_ID] = {
187		− (hrt_address)0x00020000UL
188		−};
189		−
190		−static const hrt_address ISP_DMEM_BASE[N_ISP_ID] = {
191		− (hrt_address)0x00200000UL
192		−};
193		−
194		−static const hrt_address ISP_BAMEM_BASE[N_BAMEM_ID] = {
195		− (hrt_address)0x100000UL
196		−};
197		−
198		−static const hrt_address ISP_VAMEM_BASE[N_VAMEM_ID] = {
199		− (hrt_address)0xffffffffUL,
200		− (hrt_address)0xffffffffUL,
201		− (hrt_address)0xffffffffUL
202		−};
203		−
204		−static const hrt_address ISP_HMEM_BASE[N_HMEM_ID] = {
205		− (hrt_address)0xffffffffUL
206		−};
207		−
208		−/* SP */
209		−static const hrt_address SP_CTRL_BASE[N_SP_ID] = {
210		− (hrt_address)0x00010000UL
211		−};
212		−
213		−static const hrt_address SP_DMEM_BASE[N_SP_ID] = {
214		− (hrt_address)0x00300000UL
215		−};
216		−
217		−static const hrt_address SP_PMEM_BASE[N_SP_ID] = {
218		− (hrt_address)0x000B0000UL
219		−};
220		−
221		−/* MMU */
222		−/*
223		− * MMU0_ID: The data MMU
224		− * MMU1_ID: The icache MMU
225		− */
226		−static const hrt_address MMU_BASE[N_MMU_ID] = {
227		− (hrt_address)0x00070000UL,
228		− (hrt_address)0x000A0000UL
229		−};
230		−
231		−/* DMA */
232		−static const hrt_address DMA_BASE[N_DMA_ID] = {
233		− (hrt_address)0x00040000UL
234		−};
235		−
236		−/* IRQ */
237		−static const hrt_address IRQ_BASE[N_IRQ_ID] = {
238		− (hrt_address)0x00000500UL,
239		− (hrt_address)0x00030A00UL,
240		− (hrt_address)0x0008C000UL,
241		− (hrt_address)0x00090200UL
242		−};
243		−
244		−/*
245		− (hrt_address)0x00000500UL};
246		− */
247		−
248		−/* GDC */
249		−static const hrt_address GDC_BASE[N_GDC_ID] = {
250		− (hrt_address)0x00050000UL,
251		− (hrt_address)0x00060000UL
252		−};
253		−
254		−/* FIFO_MONITOR (not a subset of GP_DEVICE) */
255		−static const hrt_address FIFO_MONITOR_BASE[N_FIFO_MONITOR_ID] = {
256		− (hrt_address)0x00000000UL
257		−};
258		−
259		−/*
260		−static const hrt_address GP_REGS_BASE[N_GP_REGS_ID] = {
261		− (hrt_address)0x00000000UL};
262		−
263		−static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = {
264		− (hrt_address)0x00090000UL};
265		−*/
266		−
267		−/* GP_DEVICE (single base for all separate GP_REG instances) */
268		−static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = {
269		− (hrt_address)0x00000000UL
270		−};
271		−
272		−/*GP TIMER , all timer registers are inter-twined,
273		− * so, having multiple base addresses for
274		− * different timers does not help*/
275		−static const hrt_address GP_TIMER_BASE =
276		− (hrt_address)0x00000600UL;
277		−
278		−/* GPIO */
279		−static const hrt_address GPIO_BASE[N_GPIO_ID] = {
280		− (hrt_address)0x00000400UL
281		−};
282		−
283		−/* TIMED_CTRL */
284		−static const hrt_address TIMED_CTRL_BASE[N_TIMED_CTRL_ID] = {
285		− (hrt_address)0x00000100UL
286		−};
287		−
288		−/* INPUT_FORMATTER */
289		−static const hrt_address INPUT_FORMATTER_BASE[N_INPUT_FORMATTER_ID] = {
290		− (hrt_address)0x00030000UL,
291		− (hrt_address)0x00030200UL,
292		− (hrt_address)0x00030400UL
293		−};
294		−
295		−/* (hrt_address)0x00030600UL, / / memcpy() */
296		−
297		−/* INPUT_SYSTEM */
298		−static const hrt_address INPUT_SYSTEM_BASE[N_INPUT_SYSTEM_ID] = {
299		− (hrt_address)0x00080000UL
300		−};
301		−
302		−/* (hrt_address)0x00081000UL, / / capture A */
303		−/* (hrt_address)0x00082000UL, / / capture B */
304		−/* (hrt_address)0x00083000UL, / / capture C */
305		−/* (hrt_address)0x00084000UL, / / Acquisition */
306		−/* (hrt_address)0x00085000UL, / / DMA */
307		−/* (hrt_address)0x00089000UL, / / ctrl */
308		−/* (hrt_address)0x0008A000UL, / / GP regs */
309		−/* (hrt_address)0x0008B000UL, / / FIFO */
310		−/* (hrt_address)0x0008C000UL, / / IRQ */
311		−
312		−/* RX, the MIPI lane control regs start at offset 0 */
313		−static const hrt_address RX_BASE[N_RX_ID] = {
314		− (hrt_address)0x00080100UL
315		−};
316		−
317		−#else
318		−#error "system_local.h: HRT_ADDRESS_WIDTH must be one of {32,64}"
319		−#endif
320		−
321		−#endif /* __SYSTEM_LOCAL_H_INCLUDED__ */

drivers/staging/media/atomisp/pci/isp2401_system_global.h+1−409

@@ -13,415 +13,7 @@ · 12 unmodified lines
13	13	* more details.
14	14	*/
15	15
16		−#ifndef __SYSTEM_GLOBAL_H_INCLUDED__
17		−#define __SYSTEM_GLOBAL_H_INCLUDED__
18		−
19		−#include <hive_isp_css_defs.h>
20		−#include <type_support.h>
21		−
22		−/*
23		− * The longest allowed (uninteruptible) bus transfer, does not
24		− * take stalling into account
25		− */
26		−#define HIVE_ISP_MAX_BURST_LENGTH 1024
27		−
28		−/*
29		− * Maximum allowed burst length in words for the ISP DMA
30		− * This value is set to 2 to prevent the ISP DMA from blocking
31		− * the bus for too long; as the input system can only buffer
32		− * 2 lines on Moorefield and Cherrytrail, the input system buffers
33		− * may overflow if blocked for too long (BZ 2726).
34		− */
35		−#define ISP_DMA_MAX_BURST_LENGTH 2
36		−
37		−/*
38		− * Create a list of HAS and IS properties that defines the system
39		− *
40		− * The configuration assumes the following
41		− * - The system is hetereogeneous; Multiple cells and devices classes
42		− * - The cell and device instances are homogeneous, each device type
43		− * belongs to the same class
44		− * - Device instances supporting a subset of the class capabilities are
45		− * allowed
46		− *
47		− * We could manage different device classes through the enumerated
48		− * lists (C) or the use of classes (C++), but that is presently not
49		− * fully supported
50		− *
51		− * N.B. the 3 input formatters are of 2 different classess
52		− */
53		−
	16	+#define HAS_NO_INPUT_FORMATTER
54	17	#define USE_INPUT_SYSTEM_VERSION_2401
55		−
56		−#define HAS_MMU_VERSION_2
57		−#define HAS_DMA_VERSION_2
58		−#define HAS_GDC_VERSION_2
59		−#define HAS_VAMEM_VERSION_2
60		−#define HAS_HMEM_VERSION_1
61		−#define HAS_BAMEM_VERSION_2
62		−#define HAS_IRQ_VERSION_2
63		−#define HAS_IRQ_MAP_VERSION_2
64		−#define HAS_INPUT_FORMATTER_VERSION_2
65		−/* 2401: HAS_INPUT_SYSTEM_VERSION_3 */
66		−/* 2400: HAS_INPUT_SYSTEM_VERSION_2 */
67		−#define HAS_INPUT_SYSTEM_VERSION_2
68	18	#define HAS_INPUT_SYSTEM_VERSION_2401
69		−#define HAS_BUFFERED_SENSOR
70		−#define HAS_FIFO_MONITORS_VERSION_2
71		−/* #define HAS_GP_REGS_VERSION_2 */
72		−#define HAS_GP_DEVICE_VERSION_2
73		−#define HAS_GPIO_VERSION_1
74		−#define HAS_TIMED_CTRL_VERSION_1
75		−#define HAS_RX_VERSION_2
76		−#define HAS_NO_INPUT_FORMATTER
77		−/#define HAS_NO_PACKED_RAW_PIXELS/
78		−/#define HAS_NO_DVS_6AXIS_CONFIG_UPDATE/
79		−
80		−#define DMA_DDR_TO_VAMEM_WORKAROUND
81		−#define DMA_DDR_TO_HMEM_WORKAROUND
82		−
83		−/*
84		− * Semi global. "HRT" is accessible from SP, but
85		− * the HRT types do not fully apply
86		− */
87		−#define HRT_VADDRESS_WIDTH 32
88		−/* Surprise, this is a local property*/
89		−/#define HRT_ADDRESS_WIDTH 64 /
90		−#define HRT_DATA_WIDTH 32
91		−
92		−#define SIZEOF_HRT_REG (HRT_DATA_WIDTH >> 3)
93		−#define HIVE_ISP_CTRL_DATA_BYTES (HIVE_ISP_CTRL_DATA_WIDTH / 8)
94		−
95		−/* The main bus connecting all devices */
96		−#define HRT_BUS_WIDTH HIVE_ISP_CTRL_DATA_WIDTH
97		−#define HRT_BUS_BYTES HIVE_ISP_CTRL_DATA_BYTES
98		−
99	19	#define CSI2P_DISABLE_ISYS2401_ONLINE_MODE
100		−
101		−/* per-frame parameter handling support */
102		−#define SH_CSS_ENABLE_PER_FRAME_PARAMS
103		−
104		−typedef u32 hrt_bus_align_t;
105		−
106		−/*
107		− * Enumerate the devices, device access through the API is by ID,
108		− * through the DLI by address. The enumerator terminators are used
109		− * to size the wiring arrays and as an exception value.
110		− */
111		−typedef enum {
112		− DDR0_ID = 0,
113		− N_DDR_ID
114		−} ddr_ID_t;
115		−
116		−typedef enum {
117		− ISP0_ID = 0,
118		− N_ISP_ID
119		−} isp_ID_t;
120		−
121		−typedef enum {
122		− SP0_ID = 0,
123		− N_SP_ID
124		−} sp_ID_t;
125		−
126		−typedef enum {
127		− MMU0_ID = 0,
128		− MMU1_ID,
129		− N_MMU_ID
130		−} mmu_ID_t;
131		−
132		−typedef enum {
133		− DMA0_ID = 0,
134		− N_DMA_ID
135		−} dma_ID_t;
136		−
137		−typedef enum {
138		− GDC0_ID = 0,
139		− GDC1_ID,
140		− N_GDC_ID
141		−} gdc_ID_t;
142		−
143		−/* this extra define is needed because we want to use it also
144		− in the preprocessor, and that doesn't work with enums.
145		− */
146		−#define N_GDC_ID_CPP 2
147		−
148		−typedef enum {
149		− VAMEM0_ID = 0,
150		− VAMEM1_ID,
151		− VAMEM2_ID,
152		− N_VAMEM_ID
153		−} vamem_ID_t;
154		−
155		−typedef enum {
156		− BAMEM0_ID = 0,
157		− N_BAMEM_ID
158		−} bamem_ID_t;
159		−
160		−typedef enum {
161		− HMEM0_ID = 0,
162		− N_HMEM_ID
163		−} hmem_ID_t;
164		−
165		−typedef enum {
166		− ISYS_IRQ0_ID = 0, /* port a */
167		− ISYS_IRQ1_ID, /* port b */
168		− ISYS_IRQ2_ID, /* port c */
169		− N_ISYS_IRQ_ID
170		−} isys_irq_ID_t;
171		−
172		−typedef enum {
173		− IRQ0_ID = 0, /* GP IRQ block */
174		− IRQ1_ID, /* Input formatter */
175		− IRQ2_ID, /* input system */
176		− IRQ3_ID, /* input selector */
177		− N_IRQ_ID
178		−} irq_ID_t;
179		−
180		−typedef enum {
181		− FIFO_MONITOR0_ID = 0,
182		− N_FIFO_MONITOR_ID
183		−} fifo_monitor_ID_t;
184		−
185		−/*
186		− * Deprecated: Since all gp_reg instances are different
187		− * and put in the address maps of other devices we cannot
188		− * enumerate them as that assumes the instrances are the
189		− * same.
190		− *
191		− * We define a single GP_DEVICE containing all gp_regs
192		− * w.r.t. a single base address
193		− *
194		−typedef enum {
195		− GP_REGS0_ID = 0,
196		− N_GP_REGS_ID
197		−} gp_regs_ID_t;
198		− */
199		−typedef enum {
200		− GP_DEVICE0_ID = 0,
201		− N_GP_DEVICE_ID
202		−} gp_device_ID_t;
203		−
204		−typedef enum {
205		− GP_TIMER0_ID = 0,
206		− GP_TIMER1_ID,
207		− GP_TIMER2_ID,
208		− GP_TIMER3_ID,
209		− GP_TIMER4_ID,
210		− GP_TIMER5_ID,
211		− GP_TIMER6_ID,
212		− GP_TIMER7_ID,
213		− N_GP_TIMER_ID
214		−} gp_timer_ID_t;
215		−
216		−typedef enum {
217		− GPIO0_ID = 0,
218		− N_GPIO_ID
219		−} gpio_ID_t;
220		−
221		−typedef enum {
222		− TIMED_CTRL0_ID = 0,
223		− N_TIMED_CTRL_ID
224		−} timed_ctrl_ID_t;
225		−
226		−typedef enum {
227		− INPUT_FORMATTER0_ID = 0,
228		− INPUT_FORMATTER1_ID,
229		− INPUT_FORMATTER2_ID,
230		− INPUT_FORMATTER3_ID,
231		− N_INPUT_FORMATTER_ID
232		−} input_formatter_ID_t;
233		−
234		−/* The IF RST is outside the IF */
235		−#define INPUT_FORMATTER0_SRST_OFFSET 0x0824
236		−#define INPUT_FORMATTER1_SRST_OFFSET 0x0624
237		−#define INPUT_FORMATTER2_SRST_OFFSET 0x0424
238		−#define INPUT_FORMATTER3_SRST_OFFSET 0x0224
239		−
240		−#define INPUT_FORMATTER0_SRST_MASK 0x0001
241		−#define INPUT_FORMATTER1_SRST_MASK 0x0002
242		−#define INPUT_FORMATTER2_SRST_MASK 0x0004
243		−#define INPUT_FORMATTER3_SRST_MASK 0x0008
244		−
245		−typedef enum {
246		− INPUT_SYSTEM0_ID = 0,
247		− N_INPUT_SYSTEM_ID
248		−} input_system_ID_t;
249		−
250		−typedef enum {
251		− RX0_ID = 0,
252		− N_RX_ID
253		−} rx_ID_t;
254		−
255		−enum mipi_port_id {
256		− MIPI_PORT0_ID = 0,
257		− MIPI_PORT1_ID,
258		− MIPI_PORT2_ID,
259		− N_MIPI_PORT_ID
260		−};
261		−
262		−#define N_RX_CHANNEL_ID 4
263		−
264		−/* Generic port enumeration with an internal port type ID */
265		−typedef enum {
266		− CSI_PORT0_ID = 0,
267		− CSI_PORT1_ID,
268		− CSI_PORT2_ID,
269		− TPG_PORT0_ID,
270		− PRBS_PORT0_ID,
271		− FIFO_PORT0_ID,
272		− MEMORY_PORT0_ID,
273		− N_INPUT_PORT_ID
274		−} input_port_ID_t;
275		−
276		−typedef enum {
277		− CAPTURE_UNIT0_ID = 0,
278		− CAPTURE_UNIT1_ID,
279		− CAPTURE_UNIT2_ID,
280		− ACQUISITION_UNIT0_ID,
281		− DMA_UNIT0_ID,
282		− CTRL_UNIT0_ID,
283		− GPREGS_UNIT0_ID,
284		− FIFO_UNIT0_ID,
285		− IRQ_UNIT0_ID,
286		− N_SUB_SYSTEM_ID
287		−} sub_system_ID_t;
288		−
289		−#define N_CAPTURE_UNIT_ID 3
290		−#define N_ACQUISITION_UNIT_ID 1
291		−#define N_CTRL_UNIT_ID 1
292		−
293		−/*
294		− * Input-buffer Controller.
295		− */
296		−typedef enum {
297		− IBUF_CTRL0_ID = 0, /* map to ISYS2401_IBUF_CNTRL_A */
298		− IBUF_CTRL1_ID, /* map to ISYS2401_IBUF_CNTRL_B */
299		− IBUF_CTRL2_ID, /* map ISYS2401_IBUF_CNTRL_C */
300		− N_IBUF_CTRL_ID
301		−} ibuf_ctrl_ID_t;
302		−/* end of Input-buffer Controller */
303		−
304		−/*
305		− * Stream2MMIO.
306		− */
307		−typedef enum {
308		− STREAM2MMIO0_ID = 0, /* map to ISYS2401_S2M_A */
309		− STREAM2MMIO1_ID, /* map to ISYS2401_S2M_B */
310		− STREAM2MMIO2_ID, /* map to ISYS2401_S2M_C */
311		− N_STREAM2MMIO_ID
312		−} stream2mmio_ID_t;
313		−
314		−typedef enum {
315		− /*
316		− * Stream2MMIO 0 has 8 SIDs that are indexed by
317		− * [STREAM2MMIO_SID0_ID...STREAM2MMIO_SID7_ID].
318		− *
319		− * Stream2MMIO 1 has 4 SIDs that are indexed by
320		− * [STREAM2MMIO_SID0_ID...TREAM2MMIO_SID3_ID].
321		− *
322		− * Stream2MMIO 2 has 4 SIDs that are indexed by
323		− * [STREAM2MMIO_SID0_ID...STREAM2MMIO_SID3_ID].
324		− */
325		− STREAM2MMIO_SID0_ID = 0,
326		− STREAM2MMIO_SID1_ID,
327		− STREAM2MMIO_SID2_ID,
328		− STREAM2MMIO_SID3_ID,
329		− STREAM2MMIO_SID4_ID,
330		− STREAM2MMIO_SID5_ID,
331		− STREAM2MMIO_SID6_ID,
332		− STREAM2MMIO_SID7_ID,
333		− N_STREAM2MMIO_SID_ID
334		−} stream2mmio_sid_ID_t;
335		−/* end of Stream2MMIO */
336		−
337		−/**
338		− * Input System 2401: CSI-MIPI recevier.
339		− */
340		−typedef enum {
341		− CSI_RX_BACKEND0_ID = 0, /* map to ISYS2401_MIPI_BE_A */
342		− CSI_RX_BACKEND1_ID, /* map to ISYS2401_MIPI_BE_B */
343		− CSI_RX_BACKEND2_ID, /* map to ISYS2401_MIPI_BE_C */
344		− N_CSI_RX_BACKEND_ID
345		−} csi_rx_backend_ID_t;
346		−
347		−typedef enum {
348		− CSI_RX_FRONTEND0_ID = 0, /* map to ISYS2401_CSI_RX_A */
349		− CSI_RX_FRONTEND1_ID, /* map to ISYS2401_CSI_RX_B */
350		− CSI_RX_FRONTEND2_ID, /* map to ISYS2401_CSI_RX_C */
351		−#define N_CSI_RX_FRONTEND_ID (CSI_RX_FRONTEND2_ID + 1)
352		−} csi_rx_frontend_ID_t;
353		−
354		−typedef enum {
355		− CSI_RX_DLANE0_ID = 0, /* map to DLANE0 in CSI RX */
356		− CSI_RX_DLANE1_ID, /* map to DLANE1 in CSI RX */
357		− CSI_RX_DLANE2_ID, /* map to DLANE2 in CSI RX */
358		− CSI_RX_DLANE3_ID, /* map to DLANE3 in CSI RX */
359		− N_CSI_RX_DLANE_ID
360		−} csi_rx_fe_dlane_ID_t;
361		−/* end of CSI-MIPI receiver */
362		−
363		−typedef enum {
364		− ISYS2401_DMA0_ID = 0,
365		− N_ISYS2401_DMA_ID
366		−} isys2401_dma_ID_t;
367		−
368		−/**
369		− * Pixel-generator. ("system_global.h")
370		− */
371		−typedef enum {
372		− PIXELGEN0_ID = 0,
373		− PIXELGEN1_ID,
374		− PIXELGEN2_ID,
375		− N_PIXELGEN_ID
376		−} pixelgen_ID_t;
377		−/* end of pixel-generator. ("system_global.h") */
378		−
379		−typedef enum {
380		− INPUT_SYSTEM_CSI_PORT0_ID = 0,
381		− INPUT_SYSTEM_CSI_PORT1_ID,
382		− INPUT_SYSTEM_CSI_PORT2_ID,
383		−
384		− INPUT_SYSTEM_PIXELGEN_PORT0_ID,
385		− INPUT_SYSTEM_PIXELGEN_PORT1_ID,
386		− INPUT_SYSTEM_PIXELGEN_PORT2_ID,
387		−
388		− N_INPUT_SYSTEM_INPUT_PORT_ID
389		−} input_system_input_port_ID_t;
390		−
391		−#define N_INPUT_SYSTEM_CSI_PORT 3
392		−
393		−typedef enum {
394		− ISYS2401_DMA_CHANNEL_0 = 0,
395		− ISYS2401_DMA_CHANNEL_1,
396		− ISYS2401_DMA_CHANNEL_2,
397		− ISYS2401_DMA_CHANNEL_3,
398		− ISYS2401_DMA_CHANNEL_4,
399		− ISYS2401_DMA_CHANNEL_5,
400		− ISYS2401_DMA_CHANNEL_6,
401		− ISYS2401_DMA_CHANNEL_7,
402		− ISYS2401_DMA_CHANNEL_8,
403		− ISYS2401_DMA_CHANNEL_9,
404		− ISYS2401_DMA_CHANNEL_10,
405		− ISYS2401_DMA_CHANNEL_11,
406		− N_ISYS2401_DMA_CHANNEL
407		−} isys2401_dma_channel;
408		−
409		−enum ia_css_isp_memories {
410		− IA_CSS_ISP_PMEM0 = 0,
411		− IA_CSS_ISP_DMEM0,
412		− IA_CSS_ISP_VMEM0,
413		− IA_CSS_ISP_VAMEM0,
414		− IA_CSS_ISP_VAMEM1,
415		− IA_CSS_ISP_VAMEM2,
416		− IA_CSS_ISP_HMEM0,
417		− IA_CSS_SP_DMEM0,
418		− IA_CSS_DDR,
419		− N_IA_CSS_MEMORIES
420		−};
421		−
422		−#define IA_CSS_NUM_MEMORIES 9
423		−/* For driver compatibility */
424		−#define N_IA_CSS_ISP_MEMORIES IA_CSS_NUM_MEMORIES
425		−#define IA_CSS_NUM_ISP_MEMORIES IA_CSS_NUM_MEMORIES
426		−
427		−#endif /* __SYSTEM_GLOBAL_H_INCLUDED__ */

drivers/staging/media/atomisp/pci/isp2401_system_local.h+0−402

@@ -1,402 +0,0 @@
1		−/* SPDX-License-Identifier: GPL-2.0 */
2		−/*
3		− * Support for Intel Camera Imaging ISP subsystem.
4		− * Copyright (c) 2015, Intel Corporation.
5		− *
6		− * This program is free software; you can redistribute it and/or modify it
7		− * under the terms and conditions of the GNU General Public License,
8		− * version 2, as published by the Free Software Foundation.
9		− *
10		− * This program is distributed in the hope it will be useful, but WITHOUT
11		− * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12		− * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13		− * more details.
14		− */
15		−
16		−#ifndef __SYSTEM_LOCAL_H_INCLUDED__
17		−#define __SYSTEM_LOCAL_H_INCLUDED__
18		−
19		−#ifdef HRT_ISP_CSS_CUSTOM_HOST
20		−#ifndef HRT_USE_VIR_ADDRS
21		−#define HRT_USE_VIR_ADDRS
22		−#endif
23		−#endif
24		−
25		−#include "system_global.h"
26		−
27		−#define HRT_ADDRESS_WIDTH 64 /* Surprise, this is a local property */
28		−
29		−/* This interface is deprecated */
30		−#include "hive_types.h"
31		−
32		−/*
33		− * Cell specific address maps
34		− */
35		−#if HRT_ADDRESS_WIDTH == 64
36		−
37		−#define GP_FIFO_BASE ((hrt_address)0x0000000000090104) /* This is NOT a base address */
38		−
39		−/* DDR */
40		−static const hrt_address DDR_BASE[N_DDR_ID] = {
41		− 0x0000000120000000ULL
42		−};
43		−
44		−/* ISP */
45		−static const hrt_address ISP_CTRL_BASE[N_ISP_ID] = {
46		− 0x0000000000020000ULL
47		−};
48		−
49		−static const hrt_address ISP_DMEM_BASE[N_ISP_ID] = {
50		− 0x0000000000200000ULL
51		−};
52		−
53		−static const hrt_address ISP_BAMEM_BASE[N_BAMEM_ID] = {
54		− 0x0000000000100000ULL
55		−};
56		−
57		−static const hrt_address ISP_VAMEM_BASE[N_VAMEM_ID] = {
58		− 0x00000000001C0000ULL,
59		− 0x00000000001D0000ULL,
60		− 0x00000000001E0000ULL
61		−};
62		−
63		−static const hrt_address ISP_HMEM_BASE[N_HMEM_ID] = {
64		− 0x00000000001F0000ULL
65		−};
66		−
67		−/* SP */
68		−static const hrt_address SP_CTRL_BASE[N_SP_ID] = {
69		− 0x0000000000010000ULL
70		−};
71		−
72		−static const hrt_address SP_DMEM_BASE[N_SP_ID] = {
73		− 0x0000000000300000ULL
74		−};
75		−
76		−/* MMU */
77		−/*
78		− * MMU0_ID: The data MMU
79		− * MMU1_ID: The icache MMU
80		− */
81		−static const hrt_address MMU_BASE[N_MMU_ID] = {
82		− 0x0000000000070000ULL,
83		− 0x00000000000A0000ULL
84		−};
85		−
86		−/* DMA */
87		−static const hrt_address DMA_BASE[N_DMA_ID] = {
88		− 0x0000000000040000ULL
89		−};
90		−
91		−static const hrt_address ISYS2401_DMA_BASE[N_ISYS2401_DMA_ID] = {
92		− 0x00000000000CA000ULL
93		−};
94		−
95		−/* IRQ */
96		−static const hrt_address IRQ_BASE[N_IRQ_ID] = {
97		− 0x0000000000000500ULL,
98		− 0x0000000000030A00ULL,
99		− 0x000000000008C000ULL,
100		− 0x0000000000090200ULL
101		−};
102		−
103		−/*
104		− 0x0000000000000500ULL};
105		− */
106		−
107		−/* GDC */
108		−static const hrt_address GDC_BASE[N_GDC_ID] = {
109		− 0x0000000000050000ULL,
110		− 0x0000000000060000ULL
111		−};
112		−
113		−/* FIFO_MONITOR (not a subset of GP_DEVICE) */
114		−static const hrt_address FIFO_MONITOR_BASE[N_FIFO_MONITOR_ID] = {
115		− 0x0000000000000000ULL
116		−};
117		−
118		−/*
119		−static const hrt_address GP_REGS_BASE[N_GP_REGS_ID] = {
120		− 0x0000000000000000ULL};
121		−
122		−static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = {
123		− 0x0000000000090000ULL};
124		−*/
125		−
126		−/* GP_DEVICE (single base for all separate GP_REG instances) */
127		−static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = {
128		− 0x0000000000000000ULL
129		−};
130		−
131		−/*GP TIMER , all timer registers are inter-twined,
132		− * so, having multiple base addresses for
133		− * different timers does not help*/
134		−static const hrt_address GP_TIMER_BASE =
135		− (hrt_address)0x0000000000000600ULL;
136		−
137		−/* GPIO */
138		−static const hrt_address GPIO_BASE[N_GPIO_ID] = {
139		− 0x0000000000000400ULL
140		−};
141		−
142		−/* TIMED_CTRL */
143		−static const hrt_address TIMED_CTRL_BASE[N_TIMED_CTRL_ID] = {
144		− 0x0000000000000100ULL
145		−};
146		−
147		−/* INPUT_FORMATTER */
148		−static const hrt_address INPUT_FORMATTER_BASE[N_INPUT_FORMATTER_ID] = {
149		− 0x0000000000030000ULL,
150		− 0x0000000000030200ULL,
151		− 0x0000000000030400ULL,
152		− 0x0000000000030600ULL
153		−}; /* memcpy() */
154		−
155		−/* INPUT_SYSTEM */
156		−static const hrt_address INPUT_SYSTEM_BASE[N_INPUT_SYSTEM_ID] = {
157		− 0x0000000000080000ULL
158		−};
159		−
160		−/* 0x0000000000081000ULL, / / capture A */
161		−/* 0x0000000000082000ULL, / / capture B */
162		−/* 0x0000000000083000ULL, / / capture C */
163		−/* 0x0000000000084000ULL, / / Acquisition */
164		−/* 0x0000000000085000ULL, / / DMA */
165		−/* 0x0000000000089000ULL, / / ctrl */
166		−/* 0x000000000008A000ULL, / / GP regs */
167		−/* 0x000000000008B000ULL, / / FIFO */
168		−/* 0x000000000008C000ULL, / / IRQ */
169		−
170		−/* RX, the MIPI lane control regs start at offset 0 */
171		−static const hrt_address RX_BASE[N_RX_ID] = {
172		− 0x0000000000080100ULL
173		−};
174		−
175		−/* IBUF_CTRL, part of the Input System 2401 */
176		−static const hrt_address IBUF_CTRL_BASE[N_IBUF_CTRL_ID] = {
177		− 0x00000000000C1800ULL, /* ibuf controller A */
178		− 0x00000000000C3800ULL, /* ibuf controller B */
179		− 0x00000000000C5800ULL /* ibuf controller C */
180		−};
181		−
182		−/* ISYS IRQ Controllers, part of the Input System 2401 */
183		−static const hrt_address ISYS_IRQ_BASE[N_ISYS_IRQ_ID] = {
184		− 0x00000000000C1400ULL, /* port a */
185		− 0x00000000000C3400ULL, /* port b */
186		− 0x00000000000C5400ULL /* port c */
187		−};
188		−
189		−/* CSI FE, part of the Input System 2401 */
190		−static const hrt_address CSI_RX_FE_CTRL_BASE[N_CSI_RX_FRONTEND_ID] = {
191		− 0x00000000000C0400ULL, /* csi fe controller A */
192		− 0x00000000000C2400ULL, /* csi fe controller B */
193		− 0x00000000000C4400ULL /* csi fe controller C */
194		−};
195		−
196		−/* CSI BE, part of the Input System 2401 */
197		−static const hrt_address CSI_RX_BE_CTRL_BASE[N_CSI_RX_BACKEND_ID] = {
198		− 0x00000000000C0800ULL, /* csi be controller A */
199		− 0x00000000000C2800ULL, /* csi be controller B */
200		− 0x00000000000C4800ULL /* csi be controller C */
201		−};
202		−
203		−/* PIXEL Generator, part of the Input System 2401 */
204		−static const hrt_address PIXELGEN_CTRL_BASE[N_PIXELGEN_ID] = {
205		− 0x00000000000C1000ULL, /* pixel gen controller A */
206		− 0x00000000000C3000ULL, /* pixel gen controller B */
207		− 0x00000000000C5000ULL /* pixel gen controller C */
208		−};
209		−
210		−/* Stream2MMIO, part of the Input System 2401 */
211		−static const hrt_address STREAM2MMIO_CTRL_BASE[N_STREAM2MMIO_ID] = {
212		− 0x00000000000C0C00ULL, /* stream2mmio controller A */
213		− 0x00000000000C2C00ULL, /* stream2mmio controller B */
214		− 0x00000000000C4C00ULL /* stream2mmio controller C */
215		−};
216		−#elif HRT_ADDRESS_WIDTH == 32
217		−
218		−#define GP_FIFO_BASE ((hrt_address)0x00090104) /* This is NOT a base address */
219		−
220		−/* DDR : Attention, this value not defined in 32-bit */
221		−static const hrt_address DDR_BASE[N_DDR_ID] = {
222		− 0x00000000UL
223		−};
224		−
225		−/* ISP */
226		−static const hrt_address ISP_CTRL_BASE[N_ISP_ID] = {
227		− 0x00020000UL
228		−};
229		−
230		−static const hrt_address ISP_DMEM_BASE[N_ISP_ID] = {
231		− 0xffffffffUL
232		−};
233		−
234		−static const hrt_address ISP_BAMEM_BASE[N_BAMEM_ID] = {
235		− 0xffffffffUL
236		−};
237		−
238		−static const hrt_address ISP_VAMEM_BASE[N_VAMEM_ID] = {
239		− 0xffffffffUL,
240		− 0xffffffffUL,
241		− 0xffffffffUL
242		−};
243		−
244		−static const hrt_address ISP_HMEM_BASE[N_HMEM_ID] = {
245		− 0xffffffffUL
246		−};
247		−
248		−/* SP */
249		−static const hrt_address SP_CTRL_BASE[N_SP_ID] = {
250		− 0x00010000UL
251		−};
252		−
253		−static const hrt_address SP_DMEM_BASE[N_SP_ID] = {
254		− 0x00300000UL
255		−};
256		−
257		−/* MMU */
258		−/*
259		− * MMU0_ID: The data MMU
260		− * MMU1_ID: The icache MMU
261		− */
262		−static const hrt_address MMU_BASE[N_MMU_ID] = {
263		− 0x00070000UL,
264		− 0x000A0000UL
265		−};
266		−
267		−/* DMA */
268		−static const hrt_address DMA_BASE[N_DMA_ID] = {
269		− 0x00040000UL
270		−};
271		−
272		−static const hrt_address ISYS2401_DMA_BASE[N_ISYS2401_DMA_ID] = {
273		− 0x000CA000UL
274		−};
275		−
276		−/* IRQ */
277		−static const hrt_address IRQ_BASE[N_IRQ_ID] = {
278		− 0x00000500UL,
279		− 0x00030A00UL,
280		− 0x0008C000UL,
281		− 0x00090200UL
282		−};
283		−
284		−/*
285		− 0x00000500UL};
286		− */
287		−
288		−/* GDC */
289		−static const hrt_address GDC_BASE[N_GDC_ID] = {
290		− 0x00050000UL,
291		− 0x00060000UL
292		−};
293		−
294		−/* FIFO_MONITOR (not a subset of GP_DEVICE) */
295		−static const hrt_address FIFO_MONITOR_BASE[N_FIFO_MONITOR_ID] = {
296		− 0x00000000UL
297		−};
298		−
299		−/*
300		−static const hrt_address GP_REGS_BASE[N_GP_REGS_ID] = {
301		− 0x00000000UL};
302		−
303		−static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = {
304		− 0x00090000UL};
305		−*/
306		−
307		−/* GP_DEVICE (single base for all separate GP_REG instances) */
308		−static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = {
309		− 0x00000000UL
310		−};
311		−
312		−/*GP TIMER , all timer registers are inter-twined,
313		− * so, having multiple base addresses for
314		− * different timers does not help*/
315		−static const hrt_address GP_TIMER_BASE =
316		− (hrt_address)0x00000600UL;
317		−/* GPIO */
318		−static const hrt_address GPIO_BASE[N_GPIO_ID] = {
319		− 0x00000400UL
320		−};
321		−
322		−/* TIMED_CTRL */
323		−static const hrt_address TIMED_CTRL_BASE[N_TIMED_CTRL_ID] = {
324		− 0x00000100UL
325		−};
326		−
327		−/* INPUT_FORMATTER */
328		−static const hrt_address INPUT_FORMATTER_BASE[N_INPUT_FORMATTER_ID] = {
329		− 0x00030000UL,
330		− 0x00030200UL,
331		− 0x00030400UL
332		−};
333		−
334		−/* 0x00030600UL, / / memcpy() */
335		−
336		−/* INPUT_SYSTEM */
337		−static const hrt_address INPUT_SYSTEM_BASE[N_INPUT_SYSTEM_ID] = {
338		− 0x00080000UL
339		−};
340		−
341		−/* 0x00081000UL, / / capture A */
342		−/* 0x00082000UL, / / capture B */
343		−/* 0x00083000UL, / / capture C */
344		−/* 0x00084000UL, / / Acquisition */
345		−/* 0x00085000UL, / / DMA */
346		−/* 0x00089000UL, / / ctrl */
347		−/* 0x0008A000UL, / / GP regs */
348		−/* 0x0008B000UL, / / FIFO */
349		−/* 0x0008C000UL, / / IRQ */
350		−
351		−/* RX, the MIPI lane control regs start at offset 0 */
352		−static const hrt_address RX_BASE[N_RX_ID] = {
353		− 0x00080100UL
354		−};
355		−
356		−/* IBUF_CTRL, part of the Input System 2401 */
357		−static const hrt_address IBUF_CTRL_BASE[N_IBUF_CTRL_ID] = {
358		− 0x000C1800UL, /* ibuf controller A */
359		− 0x000C3800UL, /* ibuf controller B */
360		− 0x000C5800UL /* ibuf controller C */
361		−};
362		−
363		−/* ISYS IRQ Controllers, part of the Input System 2401 */
364		−static const hrt_address ISYS_IRQ_BASE[N_ISYS_IRQ_ID] = {
365		− 0x000C1400ULL, /* port a */
366		− 0x000C3400ULL, /* port b */
367		− 0x000C5400ULL /* port c */
368		−};
369		−
370		−/* CSI FE, part of the Input System 2401 */
371		−static const hrt_address CSI_RX_FE_CTRL_BASE[N_CSI_RX_FRONTEND_ID] = {
372		− 0x000C0400UL, /* csi fe controller A */
373		− 0x000C2400UL, /* csi fe controller B */
374		− 0x000C4400UL /* csi fe controller C */
375		−};
376		−
377		−/* CSI BE, part of the Input System 2401 */
378		−static const hrt_address CSI_RX_FE_CTRL_BASE[N_CSI_RX_BACKEND_ID] = {
379		− 0x000C0800UL, /* csi be controller A */
380		− 0x000C2800UL, /* csi be controller B */
381		− 0x000C4800UL /* csi be controller C */
382		−};
383		−
384		−/* PIXEL Generator, part of the Input System 2401 */
385		−static const hrt_address PIXELGEN_CTRL_BASE[N_PIXELGEN_ID] = {
386		− 0x000C1000UL, /* pixel gen controller A */
387		− 0x000C3000UL, /* pixel gen controller B */
388		− 0x000C5000UL /* pixel gen controller C */
389		−};
390		−
391		−/* Stream2MMIO, part of the Input System 2401 */
392		−static const hrt_address STREAM2MMIO_CTRL_BASE[N_STREAM2MMIO_ID] = {
393		− 0x000C0C00UL, /* stream2mmio controller A */
394		− 0x000C2C00UL, /* stream2mmio controller B */
395		− 0x000C4C00UL /* stream2mmio controller C */
396		−};
397		−
398		−#else
399		−#error "system_local.h: HRT_ADDRESS_WIDTH must be one of {32,64}"
400		−#endif
401		−
402		−#endif /* __SYSTEM_LOCAL_H_INCLUDED__ */

drivers/staging/media/atomisp/pci/sh_css.c+7−2

@@ -1841,8 +1841,13 @@ ia_css_init(struct device dev, const struct ia_css_env env, · 1840 unmodified lines
1841	1841	#endif
1842	1842
1843	1843	#if !defined(HAS_NO_INPUT_SYSTEM)
1844		− dma_set_max_burst_size(DMA0_ID, HIVE_DMA_BUS_DDR_CONN,
1845		− ISP_DMA_MAX_BURST_LENGTH);
	1844	+
	1845	+ if (!IS_ISP2401)
	1846	+ dma_set_max_burst_size(DMA0_ID, HIVE_DMA_BUS_DDR_CONN,
	1847	+ ISP2400_DMA_MAX_BURST_LENGTH);
	1848	+ else
	1849	+ dma_set_max_burst_size(DMA0_ID, HIVE_DMA_BUS_DDR_CONN,
	1850	+ ISP2401_DMA_MAX_BURST_LENGTH);
1846	1851
1847	1852	if (ia_css_isys_init() != INPUT_SYSTEM_ERR_NO_ERROR)
1848	1853	err = -EINVAL;

drivers/staging/media/atomisp/pci/system_global.h+395−0

@@ -4,8 +4,403 @@ · 3 unmodified lines
4	4	* (c) 2020 Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
5	5	*/
6	6
	7	+#ifndef __SYSTEM_GLOBAL_H_INCLUDED__
	8	+#define __SYSTEM_GLOBAL_H_INCLUDED__
	9	+
	10	+/*
	11	+ * Create a list of HAS and IS properties that defines the system
	12	+ * Those are common for both ISP2400 and ISP2401
	13	+ *
	14	+ * The configuration assumes the following
	15	+ * - The system is hetereogeneous; Multiple cells and devices classes
	16	+ * - The cell and device instances are homogeneous, each device type
	17	+ * belongs to the same class
	18	+ * - Device instances supporting a subset of the class capabilities are
	19	+ * allowed
	20	+ *
	21	+ * We could manage different device classes through the enumerated
	22	+ * lists (C) or the use of classes (C++), but that is presently not
	23	+ * fully supported
	24	+ *
	25	+ * N.B. the 3 input formatters are of 2 different classess
	26	+ */
	27	+
	28	+#define HAS_MMU_VERSION_2
	29	+#define HAS_DMA_VERSION_2
	30	+#define HAS_GDC_VERSION_2
	31	+#define HAS_VAMEM_VERSION_2
	32	+#define HAS_HMEM_VERSION_1
	33	+#define HAS_BAMEM_VERSION_2
	34	+#define HAS_IRQ_VERSION_2
	35	+#define HAS_IRQ_MAP_VERSION_2
	36	+#define HAS_INPUT_FORMATTER_VERSION_2
	37	+#define HAS_INPUT_SYSTEM_VERSION_2
	38	+#define HAS_BUFFERED_SENSOR
	39	+#define HAS_FIFO_MONITORS_VERSION_2
	40	+#define HAS_GP_DEVICE_VERSION_2
	41	+#define HAS_GPIO_VERSION_1
	42	+#define HAS_TIMED_CTRL_VERSION_1
	43	+#define HAS_RX_VERSION_2
	44	+
	45	+/* per-frame parameter handling support */
	46	+#define SH_CSS_ENABLE_PER_FRAME_PARAMS
	47	+
	48	+#define DMA_DDR_TO_VAMEM_WORKAROUND
	49	+#define DMA_DDR_TO_HMEM_WORKAROUND
	50	+
	51	+/*
	52	+ * The longest allowed (uninteruptible) bus transfer, does not
	53	+ * take stalling into account
	54	+ */
	55	+#define HIVE_ISP_MAX_BURST_LENGTH 1024
	56	+
	57	+/*
	58	+ * Maximum allowed burst length in words for the ISP DMA
	59	+ * This value is set to 2 to prevent the ISP DMA from blocking
	60	+ * the bus for too long; as the input system can only buffer
	61	+ * 2 lines on Moorefield and Cherrytrail, the input system buffers
	62	+ * may overflow if blocked for too long (BZ 2726).
	63	+ */
	64	+#define ISP2400_DMA_MAX_BURST_LENGTH 128
	65	+#define ISP2401_DMA_MAX_BURST_LENGTH 2
	66	+
7	67	#ifdef ISP2401
8	68	# include "isp2401_system_global.h"
9	69	#else
10	70	# include "isp2400_system_global.h"
11	71	#endif
	72	+
	73	+#include <hive_isp_css_defs.h>
	74	+#include <type_support.h>
	75	+
	76	+/* This interface is deprecated */
	77	+#include "hive_types.h"
	78	+
	79	+/*
	80	+ * Semi global. "HRT" is accessible from SP, but the HRT types do not fully apply
	81	+ */
	82	+#define HRT_VADDRESS_WIDTH 32
	83	+
	84	+#define SIZEOF_HRT_REG (HRT_DATA_WIDTH >> 3)
	85	+#define HIVE_ISP_CTRL_DATA_BYTES (HIVE_ISP_CTRL_DATA_WIDTH / 8)
	86	+
	87	+/* The main bus connecting all devices */
	88	+#define HRT_BUS_WIDTH HIVE_ISP_CTRL_DATA_WIDTH
	89	+#define HRT_BUS_BYTES HIVE_ISP_CTRL_DATA_BYTES
	90	+
	91	+typedef u32 hrt_bus_align_t;
	92	+
	93	+/*
	94	+ * Enumerate the devices, device access through the API is by ID,
	95	+ * through the DLI by address. The enumerator terminators are used
	96	+ * to size the wiring arrays and as an exception value.
	97	+ */
	98	+typedef enum {
	99	+ DDR0_ID = 0,
	100	+ N_DDR_ID
	101	+} ddr_ID_t;
	102	+
	103	+typedef enum {
	104	+ ISP0_ID = 0,
	105	+ N_ISP_ID
	106	+} isp_ID_t;
	107	+
	108	+typedef enum {
	109	+ SP0_ID = 0,
	110	+ N_SP_ID
	111	+} sp_ID_t;
	112	+
	113	+typedef enum {
	114	+ MMU0_ID = 0,
	115	+ MMU1_ID,
	116	+ N_MMU_ID
	117	+} mmu_ID_t;
	118	+
	119	+typedef enum {
	120	+ DMA0_ID = 0,
	121	+ N_DMA_ID
	122	+} dma_ID_t;
	123	+
	124	+typedef enum {
	125	+ GDC0_ID = 0,
	126	+ GDC1_ID,
	127	+ N_GDC_ID
	128	+} gdc_ID_t;
	129	+
	130	+/* this extra define is needed because we want to use it also
	131	+ in the preprocessor, and that doesn't work with enums.
	132	+ */
	133	+#define N_GDC_ID_CPP 2
	134	+
	135	+typedef enum {
	136	+ VAMEM0_ID = 0,
	137	+ VAMEM1_ID,
	138	+ VAMEM2_ID,
	139	+ N_VAMEM_ID
	140	+} vamem_ID_t;
	141	+
	142	+typedef enum {
	143	+ BAMEM0_ID = 0,
	144	+ N_BAMEM_ID
	145	+} bamem_ID_t;
	146	+
	147	+typedef enum {
	148	+ HMEM0_ID = 0,
	149	+ N_HMEM_ID
	150	+} hmem_ID_t;
	151	+
	152	+typedef enum {
	153	+ IRQ0_ID = 0, /* GP IRQ block */
	154	+ IRQ1_ID, /* Input formatter */
	155	+ IRQ2_ID, /* input system */
	156	+ IRQ3_ID, /* input selector */
	157	+ N_IRQ_ID
	158	+} irq_ID_t;
	159	+
	160	+typedef enum {
	161	+ FIFO_MONITOR0_ID = 0,
	162	+ N_FIFO_MONITOR_ID
	163	+} fifo_monitor_ID_t;
	164	+
	165	+typedef enum {
	166	+ GP_DEVICE0_ID = 0,
	167	+ N_GP_DEVICE_ID
	168	+} gp_device_ID_t;
	169	+
	170	+typedef enum {
	171	+ GP_TIMER0_ID = 0,
	172	+ GP_TIMER1_ID,
	173	+ GP_TIMER2_ID,
	174	+ GP_TIMER3_ID,
	175	+ GP_TIMER4_ID,
	176	+ GP_TIMER5_ID,
	177	+ GP_TIMER6_ID,
	178	+ GP_TIMER7_ID,
	179	+ N_GP_TIMER_ID
	180	+} gp_timer_ID_t;
	181	+
	182	+typedef enum {
	183	+ GPIO0_ID = 0,
	184	+ N_GPIO_ID
	185	+} gpio_ID_t;
	186	+
	187	+typedef enum {
	188	+ TIMED_CTRL0_ID = 0,
	189	+ N_TIMED_CTRL_ID
	190	+} timed_ctrl_ID_t;
	191	+
	192	+typedef enum {
	193	+ INPUT_FORMATTER0_ID = 0,
	194	+ INPUT_FORMATTER1_ID,
	195	+ INPUT_FORMATTER2_ID,
	196	+ INPUT_FORMATTER3_ID,
	197	+ N_INPUT_FORMATTER_ID
	198	+} input_formatter_ID_t;
	199	+
	200	+/* The IF RST is outside the IF */
	201	+#define INPUT_FORMATTER0_SRST_OFFSET 0x0824
	202	+#define INPUT_FORMATTER1_SRST_OFFSET 0x0624
	203	+#define INPUT_FORMATTER2_SRST_OFFSET 0x0424
	204	+#define INPUT_FORMATTER3_SRST_OFFSET 0x0224
	205	+
	206	+#define INPUT_FORMATTER0_SRST_MASK 0x0001
	207	+#define INPUT_FORMATTER1_SRST_MASK 0x0002
	208	+#define INPUT_FORMATTER2_SRST_MASK 0x0004
	209	+#define INPUT_FORMATTER3_SRST_MASK 0x0008
	210	+
	211	+typedef enum {
	212	+ INPUT_SYSTEM0_ID = 0,
	213	+ N_INPUT_SYSTEM_ID
	214	+} input_system_ID_t;
	215	+
	216	+typedef enum {
	217	+ RX0_ID = 0,
	218	+ N_RX_ID
	219	+} rx_ID_t;
	220	+
	221	+enum mipi_port_id {
	222	+ MIPI_PORT0_ID = 0,
	223	+ MIPI_PORT1_ID,
	224	+ MIPI_PORT2_ID,
	225	+ N_MIPI_PORT_ID
	226	+};
	227	+
	228	+#define N_RX_CHANNEL_ID 4
	229	+
	230	+/* Generic port enumeration with an internal port type ID */
	231	+typedef enum {
	232	+ CSI_PORT0_ID = 0,
	233	+ CSI_PORT1_ID,
	234	+ CSI_PORT2_ID,
	235	+ TPG_PORT0_ID,
	236	+ PRBS_PORT0_ID,
	237	+ FIFO_PORT0_ID,
	238	+ MEMORY_PORT0_ID,
	239	+ N_INPUT_PORT_ID
	240	+} input_port_ID_t;
	241	+
	242	+typedef enum {
	243	+ CAPTURE_UNIT0_ID = 0,
	244	+ CAPTURE_UNIT1_ID,
	245	+ CAPTURE_UNIT2_ID,
	246	+ ACQUISITION_UNIT0_ID,
	247	+ DMA_UNIT0_ID,
	248	+ CTRL_UNIT0_ID,
	249	+ GPREGS_UNIT0_ID,
	250	+ FIFO_UNIT0_ID,
	251	+ IRQ_UNIT0_ID,
	252	+ N_SUB_SYSTEM_ID
	253	+} sub_system_ID_t;
	254	+
	255	+#define N_CAPTURE_UNIT_ID 3
	256	+#define N_ACQUISITION_UNIT_ID 1
	257	+#define N_CTRL_UNIT_ID 1
	258	+
	259	+
	260	+enum ia_css_isp_memories {
	261	+ IA_CSS_ISP_PMEM0 = 0,
	262	+ IA_CSS_ISP_DMEM0,
	263	+ IA_CSS_ISP_VMEM0,
	264	+ IA_CSS_ISP_VAMEM0,
	265	+ IA_CSS_ISP_VAMEM1,
	266	+ IA_CSS_ISP_VAMEM2,
	267	+ IA_CSS_ISP_HMEM0,
	268	+ IA_CSS_SP_DMEM0,
	269	+ IA_CSS_DDR,
	270	+ N_IA_CSS_MEMORIES
	271	+};
	272	+
	273	+#define IA_CSS_NUM_MEMORIES 9
	274	+/* For driver compatibility */
	275	+#define N_IA_CSS_ISP_MEMORIES IA_CSS_NUM_MEMORIES
	276	+#define IA_CSS_NUM_ISP_MEMORIES IA_CSS_NUM_MEMORIES
	277	+
	278	+/*
	279	+ * ISP2401 specific enums
	280	+ */
	281	+
	282	+typedef enum {
	283	+ ISYS_IRQ0_ID = 0, /* port a */
	284	+ ISYS_IRQ1_ID, /* port b */
	285	+ ISYS_IRQ2_ID, /* port c */
	286	+ N_ISYS_IRQ_ID
	287	+} isys_irq_ID_t;
	288	+
	289	+
	290	+/*
	291	+ * Input-buffer Controller.
	292	+ */
	293	+typedef enum {
	294	+ IBUF_CTRL0_ID = 0, /* map to ISYS2401_IBUF_CNTRL_A */
	295	+ IBUF_CTRL1_ID, /* map to ISYS2401_IBUF_CNTRL_B */
	296	+ IBUF_CTRL2_ID, /* map ISYS2401_IBUF_CNTRL_C */
	297	+ N_IBUF_CTRL_ID
	298	+} ibuf_ctrl_ID_t;
	299	+/* end of Input-buffer Controller */
	300	+
	301	+/*
	302	+ * Stream2MMIO.
	303	+ */
	304	+typedef enum {
	305	+ STREAM2MMIO0_ID = 0, /* map to ISYS2401_S2M_A */
	306	+ STREAM2MMIO1_ID, /* map to ISYS2401_S2M_B */
	307	+ STREAM2MMIO2_ID, /* map to ISYS2401_S2M_C */
	308	+ N_STREAM2MMIO_ID
	309	+} stream2mmio_ID_t;
	310	+
	311	+typedef enum {
	312	+ /*
	313	+ * Stream2MMIO 0 has 8 SIDs that are indexed by
	314	+ * [STREAM2MMIO_SID0_ID...STREAM2MMIO_SID7_ID].
	315	+ *
	316	+ * Stream2MMIO 1 has 4 SIDs that are indexed by
	317	+ * [STREAM2MMIO_SID0_ID...TREAM2MMIO_SID3_ID].
	318	+ *
	319	+ * Stream2MMIO 2 has 4 SIDs that are indexed by
	320	+ * [STREAM2MMIO_SID0_ID...STREAM2MMIO_SID3_ID].
	321	+ */
	322	+ STREAM2MMIO_SID0_ID = 0,
	323	+ STREAM2MMIO_SID1_ID,
	324	+ STREAM2MMIO_SID2_ID,
	325	+ STREAM2MMIO_SID3_ID,
	326	+ STREAM2MMIO_SID4_ID,
	327	+ STREAM2MMIO_SID5_ID,
	328	+ STREAM2MMIO_SID6_ID,
	329	+ STREAM2MMIO_SID7_ID,
	330	+ N_STREAM2MMIO_SID_ID
	331	+} stream2mmio_sid_ID_t;
	332	+/* end of Stream2MMIO */
	333	+
	334	+/**
	335	+ * Input System 2401: CSI-MIPI recevier.
	336	+ */
	337	+typedef enum {
	338	+ CSI_RX_BACKEND0_ID = 0, /* map to ISYS2401_MIPI_BE_A */
	339	+ CSI_RX_BACKEND1_ID, /* map to ISYS2401_MIPI_BE_B */
	340	+ CSI_RX_BACKEND2_ID, /* map to ISYS2401_MIPI_BE_C */
	341	+ N_CSI_RX_BACKEND_ID
	342	+} csi_rx_backend_ID_t;
	343	+
	344	+typedef enum {
	345	+ CSI_RX_FRONTEND0_ID = 0, /* map to ISYS2401_CSI_RX_A */
	346	+ CSI_RX_FRONTEND1_ID, /* map to ISYS2401_CSI_RX_B */
	347	+ CSI_RX_FRONTEND2_ID, /* map to ISYS2401_CSI_RX_C */
	348	+#define N_CSI_RX_FRONTEND_ID (CSI_RX_FRONTEND2_ID + 1)
	349	+} csi_rx_frontend_ID_t;
	350	+
	351	+typedef enum {
	352	+ CSI_RX_DLANE0_ID = 0, /* map to DLANE0 in CSI RX */
	353	+ CSI_RX_DLANE1_ID, /* map to DLANE1 in CSI RX */
	354	+ CSI_RX_DLANE2_ID, /* map to DLANE2 in CSI RX */
	355	+ CSI_RX_DLANE3_ID, /* map to DLANE3 in CSI RX */
	356	+ N_CSI_RX_DLANE_ID
	357	+} csi_rx_fe_dlane_ID_t;
	358	+/* end of CSI-MIPI receiver */
	359	+
	360	+typedef enum {
	361	+ ISYS2401_DMA0_ID = 0,
	362	+ N_ISYS2401_DMA_ID
	363	+} isys2401_dma_ID_t;
	364	+
	365	+/**
	366	+ * Pixel-generator. ("system_global.h")
	367	+ */
	368	+typedef enum {
	369	+ PIXELGEN0_ID = 0,
	370	+ PIXELGEN1_ID,
	371	+ PIXELGEN2_ID,
	372	+ N_PIXELGEN_ID
	373	+} pixelgen_ID_t;
	374	+/* end of pixel-generator. ("system_global.h") */
	375	+
	376	+typedef enum {
	377	+ INPUT_SYSTEM_CSI_PORT0_ID = 0,
	378	+ INPUT_SYSTEM_CSI_PORT1_ID,
	379	+ INPUT_SYSTEM_CSI_PORT2_ID,
	380	+
	381	+ INPUT_SYSTEM_PIXELGEN_PORT0_ID,
	382	+ INPUT_SYSTEM_PIXELGEN_PORT1_ID,
	383	+ INPUT_SYSTEM_PIXELGEN_PORT2_ID,
	384	+
	385	+ N_INPUT_SYSTEM_INPUT_PORT_ID
	386	+} input_system_input_port_ID_t;
	387	+
	388	+#define N_INPUT_SYSTEM_CSI_PORT 3
	389	+
	390	+typedef enum {
	391	+ ISYS2401_DMA_CHANNEL_0 = 0,
	392	+ ISYS2401_DMA_CHANNEL_1,
	393	+ ISYS2401_DMA_CHANNEL_2,
	394	+ ISYS2401_DMA_CHANNEL_3,
	395	+ ISYS2401_DMA_CHANNEL_4,
	396	+ ISYS2401_DMA_CHANNEL_5,
	397	+ ISYS2401_DMA_CHANNEL_6,
	398	+ ISYS2401_DMA_CHANNEL_7,
	399	+ ISYS2401_DMA_CHANNEL_8,
	400	+ ISYS2401_DMA_CHANNEL_9,
	401	+ ISYS2401_DMA_CHANNEL_10,
	402	+ ISYS2401_DMA_CHANNEL_11,
	403	+ N_ISYS2401_DMA_CHANNEL
	404	+} isys2401_dma_channel;
	405	+
	406	+#endif /* __SYSTEM_GLOBAL_H_INCLUDED__ */

drivers/staging/media/atomisp/pci/system_local.c+179−0

@@ -0,0 +1,179 @@
	1	+// SPDX-License-Identifier: GPL-2.0
	2	+/*
	3	+ * Support for Intel Camera Imaging ISP subsystem.
	4	+ * Copyright (c) 2015, Intel Corporation.
	5	+ *
	6	+ * This program is free software; you can redistribute it and/or modify it
	7	+ * under the terms and conditions of the GNU General Public License,
	8	+ * version 2, as published by the Free Software Foundation.
	9	+ *
	10	+ * This program is distributed in the hope it will be useful, but WITHOUT
	11	+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	+ * more details.
	14	+ */
	15	+
	16	+#include "system_local.h"
	17	+
	18	+/* ISP */
	19	+const hrt_address ISP_CTRL_BASE[N_ISP_ID] = {
	20	+ 0x0000000000020000ULL
	21	+};
	22	+
	23	+const hrt_address ISP_DMEM_BASE[N_ISP_ID] = {
	24	+ 0x0000000000200000ULL
	25	+};
	26	+
	27	+const hrt_address ISP_BAMEM_BASE[N_BAMEM_ID] = {
	28	+ 0x0000000000100000ULL
	29	+};
	30	+
	31	+/* SP */
	32	+const hrt_address SP_CTRL_BASE[N_SP_ID] = {
	33	+ 0x0000000000010000ULL
	34	+};
	35	+
	36	+const hrt_address SP_DMEM_BASE[N_SP_ID] = {
	37	+ 0x0000000000300000ULL
	38	+};
	39	+
	40	+/* MMU */
	41	+/*
	42	+ * MMU0_ID: The data MMU
	43	+ * MMU1_ID: The icache MMU
	44	+ */
	45	+const hrt_address MMU_BASE[N_MMU_ID] = {
	46	+ 0x0000000000070000ULL,
	47	+ 0x00000000000A0000ULL
	48	+};
	49	+
	50	+/* DMA */
	51	+const hrt_address DMA_BASE[N_DMA_ID] = {
	52	+ 0x0000000000040000ULL
	53	+};
	54	+
	55	+const hrt_address ISYS2401_DMA_BASE[N_ISYS2401_DMA_ID] = {
	56	+ 0x00000000000CA000ULL
	57	+};
	58	+
	59	+/* IRQ */
	60	+const hrt_address IRQ_BASE[N_IRQ_ID] = {
	61	+ 0x0000000000000500ULL,
	62	+ 0x0000000000030A00ULL,
	63	+ 0x000000000008C000ULL,
	64	+ 0x0000000000090200ULL
	65	+};
	66	+
	67	+/*
	68	+ 0x0000000000000500ULL};
	69	+ */
	70	+
	71	+/* GDC */
	72	+const hrt_address GDC_BASE[N_GDC_ID] = {
	73	+ 0x0000000000050000ULL,
	74	+ 0x0000000000060000ULL
	75	+};
	76	+
	77	+/* FIFO_MONITOR (not a subset of GP_DEVICE) */
	78	+const hrt_address FIFO_MONITOR_BASE[N_FIFO_MONITOR_ID] = {
	79	+ 0x0000000000000000ULL
	80	+};
	81	+
	82	+/*
	83	+const hrt_address GP_REGS_BASE[N_GP_REGS_ID] = {
	84	+ 0x0000000000000000ULL};
	85	+
	86	+const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = {
	87	+ 0x0000000000090000ULL};
	88	+*/
	89	+
	90	+/* GP_DEVICE (single base for all separate GP_REG instances) */
	91	+const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = {
	92	+ 0x0000000000000000ULL
	93	+};
	94	+
	95	+/*GP TIMER , all timer registers are inter-twined,
	96	+ * so, having multiple base addresses for
	97	+ * different timers does not help*/
	98	+const hrt_address GP_TIMER_BASE =
	99	+ (hrt_address)0x0000000000000600ULL;
	100	+
	101	+/* GPIO */
	102	+const hrt_address GPIO_BASE[N_GPIO_ID] = {
	103	+ 0x0000000000000400ULL
	104	+};
	105	+
	106	+/* TIMED_CTRL */
	107	+const hrt_address TIMED_CTRL_BASE[N_TIMED_CTRL_ID] = {
	108	+ 0x0000000000000100ULL
	109	+};
	110	+
	111	+/* INPUT_FORMATTER */
	112	+const hrt_address INPUT_FORMATTER_BASE[N_INPUT_FORMATTER_ID] = {
	113	+ 0x0000000000030000ULL,
	114	+ 0x0000000000030200ULL,
	115	+ 0x0000000000030400ULL,
	116	+ 0x0000000000030600ULL
	117	+}; /* memcpy() */
	118	+
	119	+/* INPUT_SYSTEM */
	120	+const hrt_address INPUT_SYSTEM_BASE[N_INPUT_SYSTEM_ID] = {
	121	+ 0x0000000000080000ULL
	122	+};
	123	+
	124	+/* 0x0000000000081000ULL, / / capture A */
	125	+/* 0x0000000000082000ULL, / / capture B */
	126	+/* 0x0000000000083000ULL, / / capture C */
	127	+/* 0x0000000000084000ULL, / / Acquisition */
	128	+/* 0x0000000000085000ULL, / / DMA */
	129	+/* 0x0000000000089000ULL, / / ctrl */
	130	+/* 0x000000000008A000ULL, / / GP regs */
	131	+/* 0x000000000008B000ULL, / / FIFO */
	132	+/* 0x000000000008C000ULL, / / IRQ */
	133	+
	134	+/* RX, the MIPI lane control regs start at offset 0 */
	135	+const hrt_address RX_BASE[N_RX_ID] = {
	136	+ 0x0000000000080100ULL
	137	+};
	138	+
	139	+/* IBUF_CTRL, part of the Input System 2401 */
	140	+const hrt_address IBUF_CTRL_BASE[N_IBUF_CTRL_ID] = {
	141	+ 0x00000000000C1800ULL, /* ibuf controller A */
	142	+ 0x00000000000C3800ULL, /* ibuf controller B */
	143	+ 0x00000000000C5800ULL /* ibuf controller C */
	144	+};
	145	+
	146	+/* ISYS IRQ Controllers, part of the Input System 2401 */
	147	+const hrt_address ISYS_IRQ_BASE[N_ISYS_IRQ_ID] = {
	148	+ 0x00000000000C1400ULL, /* port a */
	149	+ 0x00000000000C3400ULL, /* port b */
	150	+ 0x00000000000C5400ULL /* port c */
	151	+};
	152	+
	153	+/* CSI FE, part of the Input System 2401 */
	154	+const hrt_address CSI_RX_FE_CTRL_BASE[N_CSI_RX_FRONTEND_ID] = {
	155	+ 0x00000000000C0400ULL, /* csi fe controller A */
	156	+ 0x00000000000C2400ULL, /* csi fe controller B */
	157	+ 0x00000000000C4400ULL /* csi fe controller C */
	158	+};
	159	+
	160	+/* CSI BE, part of the Input System 2401 */
	161	+const hrt_address CSI_RX_BE_CTRL_BASE[N_CSI_RX_BACKEND_ID] = {
	162	+ 0x00000000000C0800ULL, /* csi be controller A */
	163	+ 0x00000000000C2800ULL, /* csi be controller B */
	164	+ 0x00000000000C4800ULL /* csi be controller C */
	165	+};
	166	+
	167	+/* PIXEL Generator, part of the Input System 2401 */
	168	+const hrt_address PIXELGEN_CTRL_BASE[N_PIXELGEN_ID] = {
	169	+ 0x00000000000C1000ULL, /* pixel gen controller A */
	170	+ 0x00000000000C3000ULL, /* pixel gen controller B */
	171	+ 0x00000000000C5000ULL /* pixel gen controller C */
	172	+};
	173	+
	174	+/* Stream2MMIO, part of the Input System 2401 */
	175	+const hrt_address STREAM2MMIO_CTRL_BASE[N_STREAM2MMIO_ID] = {
	176	+ 0x00000000000C0C00ULL, /* stream2mmio controller A */
	177	+ 0x00000000000C2C00ULL, /* stream2mmio controller B */
	178	+ 0x00000000000C4C00ULL /* stream2mmio controller C */
	179	+};

drivers/staging/media/atomisp/pci/system_local.h+98−6

@@ -1,11 +1,103 @@
1	1	/* SPDX-License-Identifier: GPL-2.0 */
2		−// SPDX-License-Identifier: GPL-2.0-or-later
3	2	/*
4		− * (c) 2020 Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
	3	+ * Support for Intel Camera Imaging ISP subsystem.
	4	+ * Copyright (c) 2015, Intel Corporation.
	5	+ *
	6	+ * This program is free software; you can redistribute it and/or modify it
	7	+ * under the terms and conditions of the GNU General Public License,
	8	+ * version 2, as published by the Free Software Foundation.
	9	+ *
	10	+ * This program is distributed in the hope it will be useful, but WITHOUT
	11	+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	+ * more details.
5	14	*/
6	15
7		−#ifdef ISP2401
8		−# include "isp2401_system_local.h"
9		−#else
10		−# include "isp2400_system_local.h"
	16	+#ifndef __SYSTEM_LOCAL_H_INCLUDED__
	17	+#define __SYSTEM_LOCAL_H_INCLUDED__
	18	+
	19	+#ifdef HRT_ISP_CSS_CUSTOM_HOST
	20	+#ifndef HRT_USE_VIR_ADDRS
	21	+#define HRT_USE_VIR_ADDRS
	22	+#endif
11	23	#endif
	24	+
	25	+#include "system_global.h"
	26	+
	27	+/* This interface is deprecated */
	28	+#include "hive_types.h"
	29	+
	30	+/*
	31	+ * Cell specific address maps
	32	+ */
	33	+
	34	+#define GP_FIFO_BASE ((hrt_address)0x0000000000090104) /* This is NOT a base address */
	35	+
	36	+/* ISP */
	37	+extern const hrt_address ISP_CTRL_BASE[N_ISP_ID];
	38	+extern const hrt_address ISP_DMEM_BASE[N_ISP_ID];
	39	+extern const hrt_address ISP_BAMEM_BASE[N_BAMEM_ID];
	40	+
	41	+/* SP */
	42	+extern const hrt_address SP_CTRL_BASE[N_SP_ID];
	43	+extern const hrt_address SP_DMEM_BASE[N_SP_ID];
	44	+
	45	+/* MMU */
	46	+
	47	+extern const hrt_address MMU_BASE[N_MMU_ID];
	48	+
	49	+/* DMA */
	50	+extern const hrt_address DMA_BASE[N_DMA_ID];
	51	+extern const hrt_address ISYS2401_DMA_BASE[N_ISYS2401_DMA_ID];
	52	+
	53	+/* IRQ */
	54	+extern const hrt_address IRQ_BASE[N_IRQ_ID];
	55	+
	56	+/* GDC */
	57	+extern const hrt_address GDC_BASE[N_GDC_ID];
	58	+
	59	+/* FIFO_MONITOR (not a subset of GP_DEVICE) */
	60	+extern const hrt_address FIFO_MONITOR_BASE[N_FIFO_MONITOR_ID];
	61	+
	62	+/* GP_DEVICE (single base for all separate GP_REG instances) */
	63	+extern const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID];
	64	+
	65	+/*GP TIMER , all timer registers are inter-twined,
	66	+ * so, having multiple base addresses for
	67	+ * different timers does not help*/
	68	+extern const hrt_address GP_TIMER_BASE;
	69	+
	70	+/* GPIO */
	71	+extern const hrt_address GPIO_BASE[N_GPIO_ID];
	72	+
	73	+/* TIMED_CTRL */
	74	+extern const hrt_address TIMED_CTRL_BASE[N_TIMED_CTRL_ID];
	75	+
	76	+/* INPUT_FORMATTER */
	77	+extern const hrt_address INPUT_FORMATTER_BASE[N_INPUT_FORMATTER_ID];
	78	+
	79	+/* INPUT_SYSTEM */
	80	+extern const hrt_address INPUT_SYSTEM_BASE[N_INPUT_SYSTEM_ID];
	81	+
	82	+/* RX, the MIPI lane control regs start at offset 0 */
	83	+extern const hrt_address RX_BASE[N_RX_ID];
	84	+
	85	+/* IBUF_CTRL, part of the Input System 2401 */
	86	+extern const hrt_address IBUF_CTRL_BASE[N_IBUF_CTRL_ID];
	87	+
	88	+/* ISYS IRQ Controllers, part of the Input System 2401 */
	89	+extern const hrt_address ISYS_IRQ_BASE[N_ISYS_IRQ_ID];
	90	+
	91	+/* CSI FE, part of the Input System 2401 */
	92	+extern const hrt_address CSI_RX_FE_CTRL_BASE[N_CSI_RX_FRONTEND_ID];
	93	+
	94	+/* CSI BE, part of the Input System 2401 */
	95	+extern const hrt_address CSI_RX_BE_CTRL_BASE[N_CSI_RX_BACKEND_ID];
	96	+
	97	+/* PIXEL Generator, part of the Input System 2401 */
	98	+extern const hrt_address PIXELGEN_CTRL_BASE[N_PIXELGEN_ID];
	99	+
	100	+/* Stream2MMIO, part of the Input System 2401 */
	101	+extern const hrt_address STREAM2MMIO_CTRL_BASE[N_STREAM2MMIO_ID];
	102	+
	103	+#endif /* __SYSTEM_LOCAL_H_INCLUDED__ */

Merge tag 'media/v5.8-3' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media into master

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