The AXI HDL cores provided for Analog Devices reference designs all share some common base registers (e.g. version register at address 0x00). To reduce duplication for this, a common header is added to define these registers as well as bitfields & macros to work with these registers.
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| 1 | +/* SPDX-License-Identifier: GPL-2.0 */ | |
| 2 | +/* | |
| 3 | + * Analog Devices AXI common registers & definitions | |
| 4 | + * | |
| 5 | + * Copyright 2019 Analog Devices Inc. | |
| 6 | + * | |
| 7 | + * https://wiki.analog.com/resources/fpga/docs/axi_ip | |
| 8 | + * https://wiki.analog.com/resources/fpga/docs/hdl/regmap | |
| 9 | + */ | |
| 10 | + | |
| 11 | +#ifndef ADI_AXI_COMMON_H_ | |
| 12 | +#define ADI_AXI_COMMON_H_ | |
| 13 | + | |
| 14 | +#define ADI_AXI_REG_VERSION 0x0000 | |
| 15 | + | |
| 16 | +#define ADI_AXI_PCORE_VER(major, minor, patch) \ | |
| 17 | + (((major) << 16) | ((minor) << 8) | (patch)) | |
| 18 | + | |
| 19 | +#endif /* ADI_AXI_COMMON_H_ */ | |