lael-labs/linux

Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon+24−0

@@ -124,3 +124,27 @@ Contact: intel-xe@lists.freedesktop.org · 123 unmodified lines
124	Description: RO. VRAM temperature in millidegree Celsius.	124	Description: RO. VRAM temperature in millidegree Celsius.
125		125
126	Only supported for particular Intel Xe graphics platforms.	126	Only supported for particular Intel Xe graphics platforms.
		127
		128	What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/fan1_input
		129	Date: March 2025
		130	KernelVersion: 6.14
		131	Contact: intel-xe@lists.freedesktop.org
		132	Description: RO. Fan 1 speed in RPM.
		133
		134	Only supported for particular Intel Xe graphics platforms.
		135
		136	What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/fan2_input
		137	Date: March 2025
		138	KernelVersion: 6.14
		139	Contact: intel-xe@lists.freedesktop.org
		140	Description: RO. Fan 2 speed in RPM.
		141
		142	Only supported for particular Intel Xe graphics platforms.
		143
		144	What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/fan3_input
		145	Date: March 2025
		146	KernelVersion: 6.14
		147	Contact: intel-xe@lists.freedesktop.org
		148	Description: RO. Fan 3 speed in RPM.
		149
		150	Only supported for particular Intel Xe graphics platforms.

Documentation/gpu/xe/index.rst+1−0

@@ -25,3 +25,4 @@ DG2, etc is provided to prototype the driver. · 24 unmodified lines
25	xe_debugging	25	xe_debugging
26	xe_devcoredump	26	xe_devcoredump
27	xe-drm-usage-stats.rst	27	xe-drm-usage-stats.rst
		28	xe_configfs

Documentation/gpu/xe/xe_configfs.rst+10−0

@@ -0,0 +1,10 @@
	1	.. SPDX-License-Identifier: GPL-2.0+
	2
	3	.. _xe_configfs:
	4
	5	============
	6	Xe Configfs
	7	============
	8
	9	.. kernel-doc:: drivers/gpu/drm/xe/xe_configfs.c
	10	:doc: Xe Configfs

Documentation/gpu/xe/xe_pcode.rst+7−0

@@ -12,3 +12,10 @@ Internal API · 11 unmodified lines
12		12
13	.. kernel-doc:: drivers/gpu/drm/xe/xe_pcode.c	13	.. kernel-doc:: drivers/gpu/drm/xe/xe_pcode.c
14	:internal:	14	:internal:
		15
		16	==================
		17	Boot Survivability
		18	==================
		19
		20	.. kernel-doc:: drivers/gpu/drm/xe/xe_survivability_mode.c
		21	:doc: Xe Boot Survivability

drivers/gpu/drm/xe/Kconfig+14−2

 	select DRM_TTM_HELPER
 	select DRM_EXEC
 	select DRM_GPUVM
-	select DRM_GPUSVM if !UML && DEVICE_PRIVATE
 	select DRM_SCHED
 	select MMU_NOTIFIER
 	select WANT_DEV_COREDUMP
 	  If in doubt say "Y".
+config DRM_XE_GPUSVM
+	bool "Enable CPU to GPU address mirroring"
+	depends on DRM_XE
+	depends on !UML
+	depends on DEVICE_PRIVATE
+	default y
+	select DRM_GPUSVM
+	help
+	  Enable this option if you want support for CPU to GPU address
+	  mirroring.
+	  If in doubut say "Y".
 config DRM_XE_DEVMEM_MIRROR
 	bool "Enable device memory mirror"
-	depends on DRM_XE
+	depends on DRM_XE_GPUSVM
 	select GET_FREE_REGION
 	default y
 	help

drivers/gpu/drm/xe/Makefile+2−1

 	xe_wopcm.o
 xe-$(CONFIG_HMM_MIRROR) += xe_hmm.o
-xe-$(CONFIG_DRM_GPUSVM) += xe_svm.o
+xe-$(CONFIG_DRM_XE_GPUSVM) += xe_svm.o
 # graphics hardware monitoring (HWMON) support
 xe-$(CONFIG_HWMON) += xe_hwmon.o
 xe-$(CONFIG_PERF_EVENTS) += xe_pmu.o
+xe-$(CONFIG_CONFIGFS_FS) += xe_configfs.o
 # graphics virtualization (SR-IOV) support
 xe-y += \

drivers/gpu/drm/xe/abi/guc_actions_abi.h+1−0

@@ -141,6 +141,7 @@ enum xe_guc_action { · 140 unmodified lines
141	XE_GUC_ACTION_CLIENT_SOFT_RESET = 0x5507,	141	XE_GUC_ACTION_CLIENT_SOFT_RESET = 0x5507,
142	XE_GUC_ACTION_SET_ENG_UTIL_BUFF = 0x550A,	142	XE_GUC_ACTION_SET_ENG_UTIL_BUFF = 0x550A,
143	XE_GUC_ACTION_SET_DEVICE_ENGINE_ACTIVITY_BUFFER = 0x550C,	143	XE_GUC_ACTION_SET_DEVICE_ENGINE_ACTIVITY_BUFFER = 0x550C,
		144	XE_GUC_ACTION_SET_FUNCTION_ENGINE_ACTIVITY_BUFFER = 0x550D,
144	XE_GUC_ACTION_NOTIFY_MEMORY_CAT_ERROR = 0x6000,	145	XE_GUC_ACTION_NOTIFY_MEMORY_CAT_ERROR = 0x6000,
145	XE_GUC_ACTION_REPORT_PAGE_FAULT_REQ_DESC = 0x6002,	146	XE_GUC_ACTION_REPORT_PAGE_FAULT_REQ_DESC = 0x6002,
146	XE_GUC_ACTION_PAGE_FAULT_RES_DESC = 0x6003,	147	XE_GUC_ACTION_PAGE_FAULT_RES_DESC = 0x6003,

drivers/gpu/drm/xe/abi/guc_klvs_abi.h+1−0

@@ -367,6 +367,7 @@ enum xe_guc_klv_ids { · 366 unmodified lines
367	GUC_WA_KLV_NP_RD_WRITE_TO_CLEAR_RCSM_AT_CGP_LATE_RESTORE = 0x9008,	367	GUC_WA_KLV_NP_RD_WRITE_TO_CLEAR_RCSM_AT_CGP_LATE_RESTORE = 0x9008,
368	GUC_WORKAROUND_KLV_ID_BACK_TO_BACK_RCS_ENGINE_RESET = 0x9009,	368	GUC_WORKAROUND_KLV_ID_BACK_TO_BACK_RCS_ENGINE_RESET = 0x9009,
369	GUC_WA_KLV_WAKE_POWER_DOMAINS_FOR_OUTBOUND_MMIO = 0x900a,	369	GUC_WA_KLV_WAKE_POWER_DOMAINS_FOR_OUTBOUND_MMIO = 0x900a,
		370	GUC_WA_KLV_RESET_BB_STACK_PTR_ON_VF_SWITCH = 0x900b,
370	};	371	};
371		372
372	#endif	373	#endif

drivers/gpu/drm/xe/display/intel_fbdev_fb.c+2−2

@@ -45,7 +45,7 @@ struct intel_framebuffer intel_fbdev_fb_alloc(struct drm_fb_helper helper, · 44 unmodified lines
45	NULL, size,	45	NULL, size,
46	ttm_bo_type_kernel, XE_BO_FLAG_SCANOUT \|	46	ttm_bo_type_kernel, XE_BO_FLAG_SCANOUT \|
47	XE_BO_FLAG_STOLEN \|	47	XE_BO_FLAG_STOLEN \|
48	XE_BO_FLAG_GGTT \| XE_BO_FLAG_PINNED);	48	XE_BO_FLAG_GGTT);
49	if (!IS_ERR(obj))	49	if (!IS_ERR(obj))
50	drm_info(&xe->drm, "Allocated fbdev into stolen\n");	50	drm_info(&xe->drm, "Allocated fbdev into stolen\n");
51	else	51	else
@@ -56,7 +56,7 @@ struct intel_framebuffer intel_fbdev_fb_alloc(struct drm_fb_helper helper, · 4 unmodified lines
56	obj = xe_bo_create_pin_map(xe, xe_device_get_root_tile(xe), NULL, size,	56	obj = xe_bo_create_pin_map(xe, xe_device_get_root_tile(xe), NULL, size,
57	ttm_bo_type_kernel, XE_BO_FLAG_SCANOUT \|	57	ttm_bo_type_kernel, XE_BO_FLAG_SCANOUT \|
58	XE_BO_FLAG_VRAM_IF_DGFX(xe_device_get_root_tile(xe)) \|	58	XE_BO_FLAG_VRAM_IF_DGFX(xe_device_get_root_tile(xe)) \|
59	XE_BO_FLAG_GGTT \| XE_BO_FLAG_PINNED);	59	XE_BO_FLAG_GGTT);
60	}	60	}
61		61
62	if (IS_ERR(obj)) {	62	if (IS_ERR(obj)) {

drivers/gpu/drm/xe/display/xe_plane_initial.c+1−1

@@ -83,7 +83,7 @@ initial_plane_bo(struct xe_device *xe, · 82 unmodified lines
83	if (plane_config->size == 0)	83	if (plane_config->size == 0)
84	return NULL;	84	return NULL;
85		85
86	flags = XE_BO_FLAG_PINNED \| XE_BO_FLAG_SCANOUT \| XE_BO_FLAG_GGTT;	86	flags = XE_BO_FLAG_SCANOUT \| XE_BO_FLAG_GGTT;
87		87
88	base = round_down(plane_config->base, page_size);	88	base = round_down(plane_config->base, page_size);
89	if (IS_DGFX(xe)) {	89	if (IS_DGFX(xe)) {

drivers/gpu/drm/xe/instructions/xe_alu_commands.h+79−0

@@ -0,0 +1,79 @@
	1	/* SPDX-License-Identifier: MIT */
	2	/*
	3	* Copyright © 2025 Intel Corporation
	4	*/
	5
	6	#ifndef _XE_ALU_COMMANDS_H_
	7	#define _XE_ALU_COMMANDS_H_
	8
	9	#include "instructions/xe_instr_defs.h"
	10
	11	/* Instruction Opcodes */
	12	#define CS_ALU_OPCODE_NOOP 0x000
	13	#define CS_ALU_OPCODE_FENCE_RD 0x001
	14	#define CS_ALU_OPCODE_FENCE_WR 0x002
	15	#define CS_ALU_OPCODE_LOAD 0x080
	16	#define CS_ALU_OPCODE_LOADINV 0x480
	17	#define CS_ALU_OPCODE_LOAD0 0x081
	18	#define CS_ALU_OPCODE_LOAD1 0x481
	19	#define CS_ALU_OPCODE_LOADIND 0x082
	20	#define CS_ALU_OPCODE_ADD 0x100
	21	#define CS_ALU_OPCODE_SUB 0x101
	22	#define CS_ALU_OPCODE_AND 0x102
	23	#define CS_ALU_OPCODE_OR 0x103
	24	#define CS_ALU_OPCODE_XOR 0x104
	25	#define CS_ALU_OPCODE_SHL 0x105
	26	#define CS_ALU_OPCODE_SHR 0x106
	27	#define CS_ALU_OPCODE_SAR 0x107
	28	#define CS_ALU_OPCODE_STORE 0x180
	29	#define CS_ALU_OPCODE_STOREINV 0x580
	30	#define CS_ALU_OPCODE_STOREIND 0x181
	31
	32	/* Instruction Operands */
	33	#define CS_ALU_OPERAND_REG(n) REG_FIELD_PREP(GENMASK(3, 0), (n))
	34	#define CS_ALU_OPERAND_REG0 0x0
	35	#define CS_ALU_OPERAND_REG1 0x1
	36	#define CS_ALU_OPERAND_REG2 0x2
	37	#define CS_ALU_OPERAND_REG3 0x3
	38	#define CS_ALU_OPERAND_REG4 0x4
	39	#define CS_ALU_OPERAND_REG5 0x5
	40	#define CS_ALU_OPERAND_REG6 0x6
	41	#define CS_ALU_OPERAND_REG7 0x7
	42	#define CS_ALU_OPERAND_REG8 0x8
	43	#define CS_ALU_OPERAND_REG9 0x9
	44	#define CS_ALU_OPERAND_REG10 0xa
	45	#define CS_ALU_OPERAND_REG11 0xb
	46	#define CS_ALU_OPERAND_REG12 0xc
	47	#define CS_ALU_OPERAND_REG13 0xd
	48	#define CS_ALU_OPERAND_REG14 0xe
	49	#define CS_ALU_OPERAND_REG15 0xf
	50	#define CS_ALU_OPERAND_SRCA 0x20
	51	#define CS_ALU_OPERAND_SRCB 0x21
	52	#define CS_ALU_OPERAND_ACCU 0x31
	53	#define CS_ALU_OPERAND_ZF 0x32
	54	#define CS_ALU_OPERAND_CF 0x33
	55	#define CS_ALU_OPERAND_NA 0 /* N/A operand */
	56
	57	/* Command Streamer ALU Instructions */
	58	#define CS_ALU_INSTR(opcode, op1, op2) (REG_FIELD_PREP(GENMASK(31, 20), (opcode)) \| \
	59	REG_FIELD_PREP(GENMASK(19, 10), (op1)) \| \
	60	REG_FIELD_PREP(GENMASK(9, 0), (op2)))
	61
	62	#define __CS_ALU_INSTR(opcode, op1, op2) CS_ALU_INSTR(CS_ALU_OPCODE_##opcode, \
	63	CS_ALU_OPERAND_##op1, \
	64	CS_ALU_OPERAND_##op2)
	65
	66	#define CS_ALU_INSTR_NOOP __CS_ALU_INSTR(NOOP, NA, NA)
	67	#define CS_ALU_INSTR_LOAD(op1, op2) __CS_ALU_INSTR(LOAD, op1, op2)
	68	#define CS_ALU_INSTR_LOADINV(op1, op2) __CS_ALU_INSTR(LOADINV, op1, op2)
	69	#define CS_ALU_INSTR_LOAD0(op1) __CS_ALU_INSTR(LOAD0, op1, NA)
	70	#define CS_ALU_INSTR_LOAD1(op1) __CS_ALU_INSTR(LOAD1, op1, NA)
	71	#define CS_ALU_INSTR_ADD __CS_ALU_INSTR(ADD, NA, NA)
	72	#define CS_ALU_INSTR_SUB __CS_ALU_INSTR(SUB, NA, NA)
	73	#define CS_ALU_INSTR_AND __CS_ALU_INSTR(AND, NA, NA)
	74	#define CS_ALU_INSTR_OR __CS_ALU_INSTR(OR, NA, NA)
	75	#define CS_ALU_INSTR_XOR __CS_ALU_INSTR(XOR, NA, NA)
	76	#define CS_ALU_INSTR_STORE(op1, op2) __CS_ALU_INSTR(STORE, op1, op2)
	77	#define CS_ALU_INSTR_STOREINV(op1, op2) __CS_ALU_INSTR(STOREINV, op1, op2)
	78
	79	#endif

drivers/gpu/drm/xe/instructions/xe_gfxpipe_commands.h+1−0

@@ -137,6 +137,7 @@ · 136 unmodified lines
137	#define CMD_3DSTATE_CLIP_MESH GFXPIPE_3D_CMD(0x0, 0x81)	137	#define CMD_3DSTATE_CLIP_MESH GFXPIPE_3D_CMD(0x0, 0x81)
138	#define CMD_3DSTATE_SBE_MESH GFXPIPE_3D_CMD(0x0, 0x82)	138	#define CMD_3DSTATE_SBE_MESH GFXPIPE_3D_CMD(0x0, 0x82)
139	#define CMD_3DSTATE_CPSIZE_CONTROL_BUFFER GFXPIPE_3D_CMD(0x0, 0x83)	139	#define CMD_3DSTATE_CPSIZE_CONTROL_BUFFER GFXPIPE_3D_CMD(0x0, 0x83)
		140	#define CMD_3DSTATE_COARSE_PIXEL GFXPIPE_3D_CMD(0x0, 0x89)
140		141
141	#define CMD_3DSTATE_DRAWING_RECTANGLE GFXPIPE_3D_CMD(0x1, 0x0)	142	#define CMD_3DSTATE_DRAWING_RECTANGLE GFXPIPE_3D_CMD(0x1, 0x0)
142	#define CMD_3DSTATE_CHROMA_KEY GFXPIPE_3D_CMD(0x1, 0x4)	143	#define CMD_3DSTATE_CHROMA_KEY GFXPIPE_3D_CMD(0x1, 0x4)

drivers/gpu/drm/xe/instructions/xe_mi_commands.h+5−0

 #define MI_BATCH_BUFFER_END		__MI_INSTR(0xA)
 #define MI_TOPOLOGY_FILTER		__MI_INSTR(0xD)
 #define MI_FORCE_WAKEUP			__MI_INSTR(0x1D)
+#define MI_MATH(n)			(__MI_INSTR(0x1A) | XE_INSTR_NUM_DW((n) + 1))
 #define MI_STORE_DATA_IMM		__MI_INSTR(0x20)
 #define   MI_SDI_GGTT			REG_BIT(22)
 #define MI_LOAD_REGISTER_MEM		(__MI_INSTR(0x29) | XE_INSTR_NUM_DW(4))
 #define   MI_LRM_USE_GGTT		REG_BIT(22)
+#define MI_LOAD_REGISTER_REG		(__MI_INSTR(0x2a) | XE_INSTR_NUM_DW(3))
+#define   MI_LRR_DST_CS_MMIO		REG_BIT(19)
+#define   MI_LRR_SRC_CS_MMIO		REG_BIT(18)
 #define MI_COPY_MEM_MEM			(__MI_INSTR(0x2e) | XE_INSTR_NUM_DW(5))
 #define   MI_COPY_MEM_MEM_SRC_GGTT	REG_BIT(22)
 #define   MI_COPY_MEM_MEM_DST_GGTT	REG_BIT(21)

drivers/gpu/drm/xe/regs/xe_engine_regs.h+4−0

@@ -188,6 +188,10 @@ · 187 unmodified lines
188	#define PREEMPT_GPGPU_LEVEL_MASK PREEMPT_GPGPU_LEVEL(1, 1)	188	#define PREEMPT_GPGPU_LEVEL_MASK PREEMPT_GPGPU_LEVEL(1, 1)
189	#define PREEMPT_3D_OBJECT_LEVEL REG_BIT(0)	189	#define PREEMPT_3D_OBJECT_LEVEL REG_BIT(0)
190		190
		191	#define CS_GPR_DATA(base, n) XE_REG((base) + 0x600 + (n) * 4)
		192	#define CS_GPR_REG(base, n) CS_GPR_DATA((base), (n) * 2)
		193	#define CS_GPR_REG_UDW(base, n) CS_GPR_DATA((base), (n) * 2 + 1)
		194
191	#define VDBOX_CGCTL3F08(base) XE_REG((base) + 0x3f08)	195	#define VDBOX_CGCTL3F08(base) XE_REG((base) + 0x3f08)
192	#define CG3DDISHRS_CLKGATE_DIS REG_BIT(5)	196	#define CG3DDISHRS_CLKGATE_DIS REG_BIT(5)
193		197

drivers/gpu/drm/xe/regs/xe_gt_regs.h+12−1

 #define   LE_SSE_MASK				REG_GENMASK(18, 17)
 #define   LE_SSE(value)				REG_FIELD_PREP(LE_SSE_MASK, value)
 #define   LE_COS_MASK				REG_GENMASK(16, 15)
-#define   LE_COS(value)				REG_FIELD_PREP(LE_COS_MASK)
 #define   LE_SCF_MASK				REG_BIT(14)
 #define   LE_SCF(value)				REG_FIELD_PREP(LE_SCF_MASK, value)
 #define   LE_PFM_MASK				REG_GENMASK(13, 11)
 #define XEHP_L3NODEARBCFG			XE_REG_MCR(0xb0b4)
 #define   XEHP_LNESPARE				REG_BIT(19)
+#define LSN_VC_REG2				XE_REG_MCR(0xb0c8)
+#define   LSN_LNI_WGT_MASK			REG_GENMASK(31, 28)
+#define   LSN_LNI_WGT(value)			REG_FIELD_PREP(LSN_LNI_WGT_MASK, value)
+#define   LSN_LNE_WGT_MASK			REG_GENMASK(27, 24)
+#define   LSN_LNE_WGT(value)			REG_FIELD_PREP(LSN_LNE_WGT_MASK, value)
+#define   LSN_DIM_X_WGT_MASK			REG_GENMASK(23, 20)
+#define   LSN_DIM_X_WGT(value)			REG_FIELD_PREP(LSN_DIM_X_WGT_MASK, value)
+#define   LSN_DIM_Y_WGT_MASK			REG_GENMASK(19, 16)
+#define   LSN_DIM_Y_WGT(value)			REG_FIELD_PREP(LSN_DIM_Y_WGT_MASK, value)
+#define   LSN_DIM_Z_WGT_MASK			REG_GENMASK(15, 12)
+#define   LSN_DIM_Z_WGT(value)			REG_FIELD_PREP(LSN_DIM_Z_WGT_MASK, value)
 #define L3SQCREG2				XE_REG_MCR(0xb104)
 #define   COMPMEMRD256BOVRFETCHEN		REG_BIT(20)

drivers/gpu/drm/xe/regs/xe_pcode_regs.h+3−0

 #define BMG_PACKAGE_POWER_SKU			XE_REG(0x138098)
 #define BMG_PACKAGE_POWER_SKU_UNIT		XE_REG(0x1380dc)
 #define BMG_PACKAGE_ENERGY_STATUS		XE_REG(0x138120)
+#define BMG_FAN_1_SPEED				XE_REG(0x138140)
+#define BMG_FAN_2_SPEED				XE_REG(0x138170)
+#define BMG_FAN_3_SPEED				XE_REG(0x1381a0)
 #define BMG_VRAM_TEMPERATURE			XE_REG(0x1382c0)
 #define BMG_PACKAGE_TEMPERATURE			XE_REG(0x138434)
 #define BMG_PACKAGE_RAPL_LIMIT			XE_REG(0x138440)

drivers/gpu/drm/xe/tests/xe_bo.c+2−2

@@ -252,7 +252,7 @@ static int evict_test_run_tile(struct xe_device xe, struct xe_tile tile, struc · 251 unmodified lines
252		252
253	for_each_gt(__gt, xe, id)	253	for_each_gt(__gt, xe, id)
254	xe_gt_sanitize(__gt);	254	xe_gt_sanitize(__gt);
255	err = xe_bo_restore_kernel(xe);	255	err = xe_bo_restore_early(xe);
256	/*	256	/*
257	* Snapshotting the CTB and copying back a potentially old	257	* Snapshotting the CTB and copying back a potentially old
258	* version seems risky, depending on what might have been	258	* version seems risky, depending on what might have been
@@ -273,7 +273,7 @@ static int evict_test_run_tile(struct xe_device xe, struct xe_tile tile, struc · 14 unmodified lines
273	goto cleanup_all;	273	goto cleanup_all;
274	}	274	}
275		275
276	err = xe_bo_restore_user(xe);	276	err = xe_bo_restore_late(xe);
277	if (err) {	277	if (err) {
278	KUNIT_FAIL(test, "restore user err=%pe\n", ERR_PTR(err));	278	KUNIT_FAIL(test, "restore user err=%pe\n", ERR_PTR(err));
279	goto cleanup_all;	279	goto cleanup_all;

drivers/gpu/drm/xe/tests/xe_migrate.c+3−6

 	big = xe_bo_create_pin_map(xe, tile, m->q->vm, SZ_4M,
 				   ttm_bo_type_kernel,
-				   XE_BO_FLAG_VRAM_IF_DGFX(tile) |
+				   XE_BO_FLAG_VRAM_IF_DGFX(tile));
-				   XE_BO_FLAG_PINNED);
 	if (IS_ERR(big)) {
 		KUNIT_FAIL(test, "Failed to allocate bo: %li\n", PTR_ERR(big));
 		goto vunmap;
 	pt = xe_bo_create_pin_map(xe, tile, m->q->vm, XE_PAGE_SIZE,
 				  ttm_bo_type_kernel,
-				  XE_BO_FLAG_VRAM_IF_DGFX(tile) |
+				  XE_BO_FLAG_VRAM_IF_DGFX(tile));
-				  XE_BO_FLAG_PINNED);
 	if (IS_ERR(pt)) {
 		KUNIT_FAIL(test, "Failed to allocate fake pt: %li\n",
 			   PTR_ERR(pt));
 	tiny = xe_bo_create_pin_map(xe, tile, m->q->vm,
 				    2 * SZ_4K,
 				    ttm_bo_type_kernel,
-				    XE_BO_FLAG_VRAM_IF_DGFX(tile) |
+				    XE_BO_FLAG_VRAM_IF_DGFX(tile));
-				    XE_BO_FLAG_PINNED);
 	if (IS_ERR(tiny)) {
 		KUNIT_FAIL(test, "Failed to allocate tiny fake pt: %li\n",
 			   PTR_ERR(tiny));

drivers/gpu/drm/xe/xe_bo.c+239−164

@@ -55,6 +55,8 @@ static struct ttm_placement sys_placement = { · 54 unmodified lines
55	.placement = &sys_placement_flags,	55	.placement = &sys_placement_flags,
56	};	56	};
57		57
		58	static struct ttm_placement purge_placement;
		59
58	static const struct ttm_place tt_placement_flags[] = {	60	static const struct ttm_place tt_placement_flags[] = {
59	{	61	{
60	.fpfn = 0,	62	.fpfn = 0,
@@ -189,11 +191,18 @@ static void try_add_system(struct xe_device xe, struct xe_bo bo, · 128 unmodified lines
189		191
190	static bool force_contiguous(u32 bo_flags)	192	static bool force_contiguous(u32 bo_flags)
191	{	193	{
		194	if (bo_flags & XE_BO_FLAG_STOLEN)
		195	return true; /* users expect this */
		196	else if (bo_flags & XE_BO_FLAG_PINNED &&
		197	!(bo_flags & XE_BO_FLAG_PINNED_LATE_RESTORE))
		198	return true; /* needs vmap */
		199
192	/*	200	/*
193	* For eviction / restore on suspend / resume objects pinned in VRAM	201	* For eviction / restore on suspend / resume objects pinned in VRAM
194	* must be contiguous, also only contiguous BOs support xe_bo_vmap.	202	* must be contiguous, also only contiguous BOs support xe_bo_vmap.
195	*/	203	*/
196	return bo_flags & (XE_BO_FLAG_PINNED \| XE_BO_FLAG_GGTT);	204	return bo_flags & XE_BO_FLAG_NEEDS_CPU_ACCESS &&
		205	bo_flags & XE_BO_FLAG_PINNED;
197	}	206	}
198		207
199	static void add_vram(struct xe_device xe, struct xe_bo bo,	208	static void add_vram(struct xe_device xe, struct xe_bo bo,
@@ -281,6 +290,8 @@ int xe_bo_placement_for_flags(struct xe_device xe, struct xe_bo bo, · 81 unmodified lines
281	static void xe_evict_flags(struct ttm_buffer_object *tbo,	290	static void xe_evict_flags(struct ttm_buffer_object *tbo,
282	struct ttm_placement *placement)	291	struct ttm_placement *placement)
283	{	292	{
		293	struct xe_device xe = container_of(tbo->bdev, typeof(xe), ttm);
		294	bool device_unplugged = drm_dev_is_unplugged(&xe->drm);
284	struct xe_bo *bo;	295	struct xe_bo *bo;
285		296
286	if (!xe_bo_is_xe_bo(tbo)) {	297	if (!xe_bo_is_xe_bo(tbo)) {
@@ -290,7 +301,7 @@ static void xe_evict_flags(struct ttm_buffer_object *tbo, · 3 unmodified lines
290	return;	301	return;
291	}	302	}
292		303
293	*placement = sys_placement;	304	*placement = device_unplugged ? purge_placement : sys_placement;
294	return;	305	return;
295	}	306	}
296		307
@@ -300,6 +311,11 @@ static void xe_evict_flags(struct ttm_buffer_object *tbo, · 3 unmodified lines
300	return;	311	return;
301	}	312	}
302		313
		314	if (device_unplugged && !tbo->base.dma_buf) {
		315	*placement = purge_placement;
		316	return;
		317	}
		318
303	/*	319	/*
304	* For xe, sg bos that are evicted to system just triggers a	320	* For xe, sg bos that are evicted to system just triggers a
305	* rebind of the sg list upon subsequent validation to XE_PL_TT.	321	* rebind of the sg list upon subsequent validation to XE_PL_TT.
@@ -657,11 +673,20 @@ static int xe_bo_move_dmabuf(struct ttm_buffer_object *ttm_bo, · 351 unmodified lines
657	struct xe_ttm_tt *xe_tt = container_of(ttm_bo->ttm, struct xe_ttm_tt,	673	struct xe_ttm_tt *xe_tt = container_of(ttm_bo->ttm, struct xe_ttm_tt,
658	ttm);	674	ttm);
659	struct xe_device *xe = ttm_to_xe_device(ttm_bo->bdev);	675	struct xe_device *xe = ttm_to_xe_device(ttm_bo->bdev);
		676	bool device_unplugged = drm_dev_is_unplugged(&xe->drm);
660	struct sg_table *sg;	677	struct sg_table *sg;
661		678
662	xe_assert(xe, attach);	679	xe_assert(xe, attach);
663	xe_assert(xe, ttm_bo->ttm);	680	xe_assert(xe, ttm_bo->ttm);
664		681
		682	if (device_unplugged && new_res->mem_type == XE_PL_SYSTEM &&
		683	ttm_bo->sg) {
		684	dma_resv_wait_timeout(ttm_bo->base.resv, DMA_RESV_USAGE_BOOKKEEP,
		685	false, MAX_SCHEDULE_TIMEOUT);
		686	dma_buf_unmap_attachment(attach, ttm_bo->sg, DMA_BIDIRECTIONAL);
		687	ttm_bo->sg = NULL;
		688	}
		689
665	if (new_res->mem_type == XE_PL_SYSTEM)	690	if (new_res->mem_type == XE_PL_SYSTEM)
666	goto out;	691	goto out;
667		692
@@ -898,79 +923,44 @@ static int xe_bo_move(struct ttm_buffer_object *ttm_bo, bool evict, · 230 unmodified lines
898	xe_pm_runtime_get_noresume(xe);	923	xe_pm_runtime_get_noresume(xe);
899	}	924	}
900		925
901	if (xe_bo_is_pinned(bo) && !xe_bo_is_user(bo)) {	926	if (move_lacks_source) {
902	/*	927	u32 flags = 0;
903	* Kernel memory that is pinned should only be moved on suspend
904	* / resume, some of the pinned memory is required for the
905	* device to resume / use the GPU to move other evicted memory
906	* (user memory) around. This likely could be optimized a bit
907	* further where we find the minimum set of pinned memory
908	* required for resume but for simplity doing a memcpy for all
909	* pinned memory.
910	*/
911	ret = xe_bo_vmap(bo);
912	if (!ret) {
913	ret = ttm_bo_move_memcpy(ttm_bo, ctx, new_mem);
914
915	/* Create a new VMAP once kernel BO back in VRAM */
916	if (!ret && resource_is_vram(new_mem)) {
917	struct xe_vram_region *vram = res_to_mem_region(new_mem);
918	void __iomem *new_addr = vram->mapping +
919	(new_mem->start << PAGE_SHIFT);
920
921	if (XE_WARN_ON(new_mem->start == XE_BO_INVALID_OFFSET)) {
922	ret = -EINVAL;
923	xe_pm_runtime_put(xe);
924	goto out;
925	}
926		928
927	xe_assert(xe, new_mem->start ==	929	if (mem_type_is_vram(new_mem->mem_type))
928	bo->placements->fpfn);	930	flags \|= XE_MIGRATE_CLEAR_FLAG_FULL;
		931	else if (handle_system_ccs)
		932	flags \|= XE_MIGRATE_CLEAR_FLAG_CCS_DATA;
929		933
930	iosys_map_set_vaddr_iomem(&bo->vmap, new_addr);	934	fence = xe_migrate_clear(migrate, bo, new_mem, flags);
931	}
932	}
933	} else {	935	} else {
934	if (move_lacks_source) {	936	fence = xe_migrate_copy(migrate, bo, bo, old_mem, new_mem,
935	u32 flags = 0;	937	handle_system_ccs);
936		938	}
937	if (mem_type_is_vram(new_mem->mem_type))	939	if (IS_ERR(fence)) {
938	flags \|= XE_MIGRATE_CLEAR_FLAG_FULL;	940	ret = PTR_ERR(fence);
939	else if (handle_system_ccs)	941	xe_pm_runtime_put(xe);
940	flags \|= XE_MIGRATE_CLEAR_FLAG_CCS_DATA;	942	goto out;
941		943	}
942	fence = xe_migrate_clear(migrate, bo, new_mem, flags);	944	if (!move_lacks_source) {
943	}	945	ret = ttm_bo_move_accel_cleanup(ttm_bo, fence, evict, true,
944	else	946	new_mem);
945	fence = xe_migrate_copy(migrate, bo, bo, old_mem,	947	if (ret) {
946	new_mem, handle_system_ccs);	948	dma_fence_wait(fence, false);
947	if (IS_ERR(fence)) {
948	ret = PTR_ERR(fence);
949	xe_pm_runtime_put(xe);
950	goto out;
951	}
952	if (!move_lacks_source) {
953	ret = ttm_bo_move_accel_cleanup(ttm_bo, fence, evict,
954	true, new_mem);
955	if (ret) {
956	dma_fence_wait(fence, false);
957	ttm_bo_move_null(ttm_bo, new_mem);
958	ret = 0;
959	}
960	} else {
961	/*
962	* ttm_bo_move_accel_cleanup() may blow up if
963	* bo->resource == NULL, so just attach the
964	* fence and set the new resource.
965	*/
966	dma_resv_add_fence(ttm_bo->base.resv, fence,
967	DMA_RESV_USAGE_KERNEL);
968	ttm_bo_move_null(ttm_bo, new_mem);	949	ttm_bo_move_null(ttm_bo, new_mem);
		950	ret = 0;
969	}	951	}
970		952	} else {
971	dma_fence_put(fence);	953	/*
		954	* ttm_bo_move_accel_cleanup() may blow up if
		955	* bo->resource == NULL, so just attach the
		956	* fence and set the new resource.
		957	*/
		958	dma_resv_add_fence(ttm_bo->base.resv, fence,
		959	DMA_RESV_USAGE_KERNEL);
		960	ttm_bo_move_null(ttm_bo, new_mem);
972	}	961	}
973		962
		963	dma_fence_put(fence);
974	xe_pm_runtime_put(xe);	964	xe_pm_runtime_put(xe);
975		965
976	out:	966	out:
@@ -1107,59 +1097,93 @@ out_unref: · 130 unmodified lines
1107	*/	1097	*/
1108	int xe_bo_evict_pinned(struct xe_bo *bo)	1098	int xe_bo_evict_pinned(struct xe_bo *bo)
1109	{	1099	{
1110	struct ttm_place place = {	1100	struct xe_device *xe = ttm_to_xe_device(bo->ttm.bdev);
1111	.mem_type = XE_PL_TT,	1101	struct xe_bo *backup;
1112	};	1102	bool unmap = false;
1113	struct ttm_placement placement = {	1103	int ret = 0;
1114	.placement = &place,
1115	.num_placement = 1,
1116	};
1117	struct ttm_operation_ctx ctx = {
1118	.interruptible = false,
1119	.gfp_retry_mayfail = true,
1120	};
1121	struct ttm_resource *new_mem;
1122	int ret;
1123		1104
1124	xe_bo_assert_held(bo);	1105	xe_bo_lock(bo, false);
1125		1106
1126	if (WARN_ON(!bo->ttm.resource))	1107	if (WARN_ON(!bo->ttm.resource)) {
1127	return -EINVAL;	1108	ret = -EINVAL;
		1109	goto out_unlock_bo;
		1110	}
1128		1111
1129	if (WARN_ON(!xe_bo_is_pinned(bo)))	1112	if (WARN_ON(!xe_bo_is_pinned(bo))) {
1130	return -EINVAL;	1113	ret = -EINVAL;
		1114	goto out_unlock_bo;
		1115	}
1131		1116
1132	if (!xe_bo_is_vram(bo))	1117	if (!xe_bo_is_vram(bo))
1133	return 0;	1118	goto out_unlock_bo;
1134		1119
1135	ret = ttm_bo_mem_space(&bo->ttm, &placement, &new_mem, &ctx);	1120	if (bo->flags & XE_BO_FLAG_PINNED_NORESTORE)
1136	if (ret)	1121	goto out_unlock_bo;
1137	return ret;
1138		1122
1139	if (!bo->ttm.ttm) {	1123	backup = xe_bo_create_locked(xe, NULL, NULL, bo->size, ttm_bo_type_kernel,
1140	bo->ttm.ttm = xe_ttm_tt_create(&bo->ttm, 0);	1124	XE_BO_FLAG_SYSTEM \| XE_BO_FLAG_NEEDS_CPU_ACCESS \|
1141	if (!bo->ttm.ttm) {	1125	XE_BO_FLAG_PINNED);
1142	ret = -ENOMEM;	1126	if (IS_ERR(backup)) {
1143	goto err_res_free;	1127	ret = PTR_ERR(backup);
1144	}	1128	goto out_unlock_bo;
1145	}	1129	}
1146		1130
1147	ret = ttm_bo_populate(&bo->ttm, &ctx);	1131	if (xe_bo_is_user(bo) \|\| (bo->flags & XE_BO_FLAG_PINNED_LATE_RESTORE)) {
1148	if (ret)	1132	struct xe_migrate *migrate;
1149	goto err_res_free;	1133	struct dma_fence *fence;
1150		1134
1151	ret = dma_resv_reserve_fences(bo->ttm.base.resv, 1);	1135	if (bo->tile)
1152	if (ret)	1136	migrate = bo->tile->migrate;
1153	goto err_res_free;	1137	else
		1138	migrate = mem_type_to_migrate(xe, bo->ttm.resource->mem_type);
1154		1139
1155	ret = xe_bo_move(&bo->ttm, false, &ctx, new_mem, NULL);	1140	ret = dma_resv_reserve_fences(bo->ttm.base.resv, 1);
1156	if (ret)	1141	if (ret)
1157	goto err_res_free;	1142	goto out_backup;
1158		1143
1159	return 0;	1144	ret = dma_resv_reserve_fences(backup->ttm.base.resv, 1);
		1145	if (ret)
		1146	goto out_backup;
1160		1147
1161	err_res_free:	1148	fence = xe_migrate_copy(migrate, bo, backup, bo->ttm.resource,
1162	ttm_resource_free(&bo->ttm, &new_mem);	1149	backup->ttm.resource, false);
		1150	if (IS_ERR(fence)) {
		1151	ret = PTR_ERR(fence);
		1152	goto out_backup;
		1153	}
		1154
		1155	dma_resv_add_fence(bo->ttm.base.resv, fence,
		1156	DMA_RESV_USAGE_KERNEL);
		1157	dma_resv_add_fence(backup->ttm.base.resv, fence,
		1158	DMA_RESV_USAGE_KERNEL);
		1159	dma_fence_put(fence);
		1160	} else {
		1161	ret = xe_bo_vmap(backup);
		1162	if (ret)
		1163	goto out_backup;
		1164
		1165	if (iosys_map_is_null(&bo->vmap)) {
		1166	ret = xe_bo_vmap(bo);
		1167	if (ret)
		1168	goto out_backup;
		1169	unmap = true;
		1170	}
		1171
		1172	xe_map_memcpy_from(xe, backup->vmap.vaddr, &bo->vmap, 0,
		1173	bo->size);
		1174	}
		1175
		1176	bo->backup_obj = backup;
		1177
		1178	out_backup:
		1179	xe_bo_vunmap(backup);
		1180	xe_bo_unlock(backup);
		1181	if (ret)
		1182	xe_bo_put(backup);
		1183	out_unlock_bo:
		1184	if (unmap)
		1185	xe_bo_vunmap(bo);
		1186	xe_bo_unlock(bo);
1163	return ret;	1187	return ret;
1164	}	1188	}
1165		1189
@@ -1180,50 +1204,110 @@ int xe_bo_restore_pinned(struct xe_bo *bo) · 14 unmodified lines
1180	.interruptible = false,	1204	.interruptible = false,
1181	.gfp_retry_mayfail = false,	1205	.gfp_retry_mayfail = false,
1182	};	1206	};
1183	struct ttm_resource *new_mem;	1207	struct xe_device *xe = ttm_to_xe_device(bo->ttm.bdev);
1184	struct ttm_place *place = &bo->placements[0];	1208	struct xe_bo *backup = bo->backup_obj;
		1209	bool unmap = false;
1185	int ret;	1210	int ret;
1186		1211
1187	xe_bo_assert_held(bo);	1212	if (!backup)
		1213	return 0;
1188		1214
1189	if (WARN_ON(!bo->ttm.resource))	1215	xe_bo_lock(backup, false);
1190	return -EINVAL;
1191		1216
1192	if (WARN_ON(!xe_bo_is_pinned(bo)))	1217	ret = ttm_bo_validate(&backup->ttm, &backup->placement, &ctx);
1193	return -EINVAL;	1218	if (ret)
		1219	goto out_backup;
1194		1220
1195	if (WARN_ON(xe_bo_is_vram(bo)))	1221	if (WARN_ON(!dma_resv_trylock(bo->ttm.base.resv))) {
1196	return -EINVAL;	1222	ret = -EBUSY;
		1223	goto out_backup;
		1224	}
1197		1225
1198	if (WARN_ON(!bo->ttm.ttm && !xe_bo_is_stolen(bo)))	1226	if (xe_bo_is_user(bo) \|\| (bo->flags & XE_BO_FLAG_PINNED_LATE_RESTORE)) {
1199	return -EINVAL;	1227	struct xe_migrate *migrate;
		1228	struct dma_fence *fence;
1200		1229
1201	if (!mem_type_is_vram(place->mem_type))	1230	if (bo->tile)
1202	return 0;	1231	migrate = bo->tile->migrate;
		1232	else
		1233	migrate = mem_type_to_migrate(xe, bo->ttm.resource->mem_type);
1203		1234
1204	ret = ttm_bo_mem_space(&bo->ttm, &bo->placement, &new_mem, &ctx);	1235	ret = dma_resv_reserve_fences(bo->ttm.base.resv, 1);
1205	if (ret)	1236	if (ret)
1206	return ret;	1237	goto out_unlock_bo;
1207		1238
1208	ret = ttm_bo_populate(&bo->ttm, &ctx);	1239	ret = dma_resv_reserve_fences(backup->ttm.base.resv, 1);
1209	if (ret)	1240	if (ret)
1210	goto err_res_free;	1241	goto out_unlock_bo;
1211		1242
1212	ret = dma_resv_reserve_fences(bo->ttm.base.resv, 1);	1243	fence = xe_migrate_copy(migrate, backup, bo,
1213	if (ret)	1244	backup->ttm.resource, bo->ttm.resource,
1214	goto err_res_free;	1245	false);
		1246	if (IS_ERR(fence)) {
		1247	ret = PTR_ERR(fence);
		1248	goto out_unlock_bo;
		1249	}
1215		1250
1216	ret = xe_bo_move(&bo->ttm, false, &ctx, new_mem, NULL);	1251	dma_resv_add_fence(bo->ttm.base.resv, fence,
1217	if (ret)	1252	DMA_RESV_USAGE_KERNEL);
1218	goto err_res_free;	1253	dma_resv_add_fence(backup->ttm.base.resv, fence,
		1254	DMA_RESV_USAGE_KERNEL);
		1255	dma_fence_put(fence);
		1256	} else {
		1257	ret = xe_bo_vmap(backup);
		1258	if (ret)
		1259	goto out_unlock_bo;
1219		1260
1220	return 0;	1261	if (iosys_map_is_null(&bo->vmap)) {
		1262	ret = xe_bo_vmap(bo);
		1263	if (ret)
		1264	goto out_unlock_bo;
		1265	unmap = true;
		1266	}
1221		1267
1222	err_res_free:	1268	xe_map_memcpy_to(xe, &bo->vmap, 0, backup->vmap.vaddr,
1223	ttm_resource_free(&bo->ttm, &new_mem);	1269	bo->size);
		1270	}
		1271
		1272	bo->backup_obj = NULL;
		1273
		1274	out_unlock_bo:
		1275	if (unmap)
		1276	xe_bo_vunmap(bo);
		1277	xe_bo_unlock(bo);
		1278	out_backup:
		1279	xe_bo_vunmap(backup);
		1280	xe_bo_unlock(backup);
		1281	if (!bo->backup_obj)
		1282	xe_bo_put(backup);
1224	return ret;	1283	return ret;
1225	}	1284	}
1226		1285
		1286	int xe_bo_dma_unmap_pinned(struct xe_bo *bo)
		1287	{
		1288	struct ttm_buffer_object *ttm_bo = &bo->ttm;
		1289	struct ttm_tt *tt = ttm_bo->ttm;
		1290
		1291	if (tt) {
		1292	struct xe_ttm_tt xe_tt = container_of(tt, typeof(xe_tt), ttm);
		1293
		1294	if (ttm_bo->type == ttm_bo_type_sg && ttm_bo->sg) {
		1295	dma_buf_unmap_attachment(ttm_bo->base.import_attach,
		1296	ttm_bo->sg,
		1297	DMA_BIDIRECTIONAL);
		1298	ttm_bo->sg = NULL;
		1299	xe_tt->sg = NULL;
		1300	} else if (xe_tt->sg) {
		1301	dma_unmap_sgtable(xe_tt->xe->drm.dev, xe_tt->sg,
		1302	DMA_BIDIRECTIONAL, 0);
		1303	sg_free_table(xe_tt->sg);
		1304	xe_tt->sg = NULL;
		1305	}
		1306	}
		1307
		1308	return 0;
		1309	}
		1310
1227	static unsigned long xe_ttm_io_mem_pfn(struct ttm_buffer_object *ttm_bo,	1311	static unsigned long xe_ttm_io_mem_pfn(struct ttm_buffer_object *ttm_bo,
1228	unsigned long page_offset)	1312	unsigned long page_offset)
1229	{	1313	{
@@ -1947,7 +2031,7 @@ struct xe_bo xe_bo_create_pin_map_at_aligned(struct xe_device xe, · 717 unmodified lines
1947	flags \|= XE_BO_FLAG_GGTT;	2031	flags \|= XE_BO_FLAG_GGTT;
1948		2032
1949	bo = xe_bo_create_locked_range(xe, tile, vm, size, start, end, type,	2033	bo = xe_bo_create_locked_range(xe, tile, vm, size, start, end, type,
1950	flags \| XE_BO_FLAG_NEEDS_CPU_ACCESS,	2034	flags \| XE_BO_FLAG_NEEDS_CPU_ACCESS \| XE_BO_FLAG_PINNED,
1951	alignment);	2035	alignment);
1952	if (IS_ERR(bo))	2036	if (IS_ERR(bo))
1953	return bo;	2037	return bo;
@@ -2049,7 +2133,8 @@ int xe_managed_bo_reinit_in_vram(struct xe_device xe, struct xe_tile tile, str · 95 unmodified lines
2049	struct xe_bo *bo;	2133	struct xe_bo *bo;
2050	u32 dst_flags = XE_BO_FLAG_VRAM_IF_DGFX(tile) \| XE_BO_FLAG_GGTT;	2134	u32 dst_flags = XE_BO_FLAG_VRAM_IF_DGFX(tile) \| XE_BO_FLAG_GGTT;
2051		2135
2052	dst_flags \|= (*src)->flags & XE_BO_FLAG_GGTT_INVALIDATE;	2136	dst_flags \|= (*src)->flags & (XE_BO_FLAG_GGTT_INVALIDATE \|
		2137	XE_BO_FLAG_PINNED_NORESTORE);
2053		2138
2054	xe_assert(xe, IS_DGFX(xe));	2139	xe_assert(xe, IS_DGFX(xe));
2055	xe_assert(xe, !(*src)->vmap.is_iomem);	2140	xe_assert(xe, !(*src)->vmap.is_iomem);
@@ -2073,10 +2158,16 @@ uint64_t vram_region_gpu_offset(struct ttm_resource *res) · 17 unmodified lines
2073	{	2158	{
2074	struct xe_device *xe = ttm_to_xe_device(res->bo->bdev);	2159	struct xe_device *xe = ttm_to_xe_device(res->bo->bdev);
2075		2160
2076	if (res->mem_type == XE_PL_STOLEN)	2161	switch (res->mem_type) {
		2162	case XE_PL_STOLEN:
2077	return xe_ttm_stolen_gpu_offset(xe);	2163	return xe_ttm_stolen_gpu_offset(xe);
2078		2164	case XE_PL_TT:
2079	return res_to_mem_region(res)->dpa_base;	2165	case XE_PL_SYSTEM:
		2166	return 0;
		2167	default:
		2168	return res_to_mem_region(res)->dpa_base;
		2169	}
		2170	return 0;
2080	}	2171	}
2081		2172
2082	/**	2173	/**
@@ -2102,12 +2193,9 @@ int xe_bo_pin_external(struct xe_bo *bo) · 19 unmodified lines
2102	if (err)	2193	if (err)
2103	return err;	2194	return err;
2104		2195
2105	if (xe_bo_is_vram(bo)) {	2196	spin_lock(&xe->pinned.lock);
2106	spin_lock(&xe->pinned.lock);	2197	list_add_tail(&bo->pinned_link, &xe->pinned.late.external);
2107	list_add_tail(&bo->pinned_link,	2198	spin_unlock(&xe->pinned.lock);
2108	&xe->pinned.external_vram);
2109	spin_unlock(&xe->pinned.lock);
2110	}
2111	}	2199	}
2112		2200
2113	ttm_bo_pin(&bo->ttm);	2201	ttm_bo_pin(&bo->ttm);
@@ -2149,25 +2237,12 @@ int xe_bo_pin(struct xe_bo *bo) · 35 unmodified lines
2149	if (err)	2237	if (err)
2150	return err;	2238	return err;
2151		2239
2152	/*
2153	* For pinned objects in on DGFX, which are also in vram, we expect
2154	* these to be in contiguous VRAM memory. Required eviction / restore
2155	* during suspend / resume (force restore to same physical address).
2156	*/
2157	if (IS_DGFX(xe) && !(IS_ENABLED(CONFIG_DRM_XE_DEBUG) &&
2158	bo->flags & XE_BO_FLAG_INTERNAL_TEST)) {
2159	if (mem_type_is_vram(place->mem_type)) {
2160	xe_assert(xe, place->flags & TTM_PL_FLAG_CONTIGUOUS);
2161
2162	place->fpfn = (xe_bo_addr(bo, 0, PAGE_SIZE) -
2163	vram_region_gpu_offset(bo->ttm.resource)) >> PAGE_SHIFT;
2164	place->lpfn = place->fpfn + (bo->size >> PAGE_SHIFT);
2165	}
2166	}
2167
2168	if (mem_type_is_vram(place->mem_type) \|\| bo->flags & XE_BO_FLAG_GGTT) {	2240	if (mem_type_is_vram(place->mem_type) \|\| bo->flags & XE_BO_FLAG_GGTT) {
2169	spin_lock(&xe->pinned.lock);	2241	spin_lock(&xe->pinned.lock);
2170	list_add_tail(&bo->pinned_link, &xe->pinned.kernel_bo_present);	2242	if (bo->flags & XE_BO_FLAG_PINNED_LATE_RESTORE)
		2243	list_add_tail(&bo->pinned_link, &xe->pinned.late.kernel_bo_present);
		2244	else
		2245	list_add_tail(&bo->pinned_link, &xe->pinned.early.kernel_bo_present);
2171	spin_unlock(&xe->pinned.lock);	2246	spin_unlock(&xe->pinned.lock);
2172	}	2247	}
2173		2248

drivers/gpu/drm/xe/xe_bo.h+14−9

 #define XE_BO_FLAG_NEEDS_64K		BIT(15)
 #define XE_BO_FLAG_NEEDS_2M		BIT(16)
 #define XE_BO_FLAG_GGTT_INVALIDATE	BIT(17)
-#define XE_BO_FLAG_GGTT0                BIT(18)
+#define XE_BO_FLAG_PINNED_NORESTORE	BIT(18)
-#define XE_BO_FLAG_GGTT1                BIT(19)
+#define XE_BO_FLAG_PINNED_LATE_RESTORE	BIT(19)
-#define XE_BO_FLAG_GGTT2                BIT(20)
+#define XE_BO_FLAG_GGTT0		BIT(20)
-#define XE_BO_FLAG_GGTT3                BIT(21)
+#define XE_BO_FLAG_GGTT1		BIT(21)
-#define XE_BO_FLAG_GGTT_ALL             (XE_BO_FLAG_GGTT0 | \
+#define XE_BO_FLAG_GGTT2		BIT(22)
-					 XE_BO_FLAG_GGTT1 | \
+#define XE_BO_FLAG_GGTT3		BIT(23)
-					 XE_BO_FLAG_GGTT2 | \
+#define XE_BO_FLAG_CPU_ADDR_MIRROR	BIT(24)
-					 XE_BO_FLAG_GGTT3)
-#define XE_BO_FLAG_CPU_ADDR_MIRROR	BIT(22)
 /* this one is trigger internally only */
 #define XE_BO_FLAG_INTERNAL_TEST	BIT(30)
 #define XE_BO_FLAG_INTERNAL_64K		BIT(31)
+#define XE_BO_FLAG_GGTT_ALL		(XE_BO_FLAG_GGTT0 | \
+					 XE_BO_FLAG_GGTT1 | \
+					 XE_BO_FLAG_GGTT2 | \
+					 XE_BO_FLAG_GGTT3)
 #define XE_BO_FLAG_GGTTx(tile) \
 	(XE_BO_FLAG_GGTT0 << (tile)->id)
 int xe_bo_evict_pinned(struct xe_bo *bo);
 int xe_bo_restore_pinned(struct xe_bo *bo);
+int xe_bo_dma_unmap_pinned(struct xe_bo *bo);
 extern const struct ttm_device_funcs xe_ttm_funcs;
 extern const char *const xe_mem_type_to_name[];

drivers/gpu/drm/xe/xe_bo_evict.c+179−130

@@ -10,6 +10,42 @@ · 9 unmodified lines
10	#include "xe_ggtt.h"	10	#include "xe_ggtt.h"
11	#include "xe_tile.h"	11	#include "xe_tile.h"
12		12
		13	typedef int (xe_pinned_fn)(struct xe_bo bo);
		14
		15	static int xe_bo_apply_to_pinned(struct xe_device *xe,
		16	struct list_head *pinned_list,
		17	struct list_head *new_list,
		18	const xe_pinned_fn pinned_fn)
		19	{
		20	LIST_HEAD(still_in_list);
		21	struct xe_bo *bo;
		22	int ret = 0;
		23
		24	spin_lock(&xe->pinned.lock);
		25	while (!ret) {
		26	bo = list_first_entry_or_null(pinned_list, typeof(*bo),
		27	pinned_link);
		28	if (!bo)
		29	break;
		30	xe_bo_get(bo);
		31	list_move_tail(&bo->pinned_link, &still_in_list);
		32	spin_unlock(&xe->pinned.lock);
		33
		34	ret = pinned_fn(bo);
		35	if (ret && pinned_list != new_list) {
		36	spin_lock(&xe->pinned.lock);
		37	list_move(&bo->pinned_link, pinned_list);
		38	spin_unlock(&xe->pinned.lock);
		39	}
		40	xe_bo_put(bo);
		41	spin_lock(&xe->pinned.lock);
		42	}
		43	list_splice_tail(&still_in_list, new_list);
		44	spin_unlock(&xe->pinned.lock);
		45
		46	return ret;
		47	}
		48
13	/**	49	/**
14	* xe_bo_evict_all - evict all BOs from VRAM	50	* xe_bo_evict_all - evict all BOs from VRAM
15	*	51	*
@@ -27,9 +63,7 @@ · 11 unmodified lines
27	int xe_bo_evict_all(struct xe_device *xe)	63	int xe_bo_evict_all(struct xe_device *xe)
28	{	64	{
29	struct ttm_device *bdev = &xe->ttm;	65	struct ttm_device *bdev = &xe->ttm;
30	struct xe_bo *bo;
31	struct xe_tile *tile;	66	struct xe_tile *tile;
32	struct list_head still_in_list;
33	u32 mem_type;	67	u32 mem_type;
34	u8 id;	68	u8 id;
35	int ret;	69	int ret;
@@ -57,34 +91,13 @@ int xe_bo_evict_all(struct xe_device *xe) · 21 unmodified lines
57	}	91	}
58	}	92	}
59		93
60	/* Pinned user memory in VRAM */	94	ret = xe_bo_apply_to_pinned(xe, &xe->pinned.late.external,
61	INIT_LIST_HEAD(&still_in_list);	95	&xe->pinned.late.external,
62	spin_lock(&xe->pinned.lock);	96	xe_bo_evict_pinned);
63	for (;;) {
64	bo = list_first_entry_or_null(&xe->pinned.external_vram,
65	typeof(*bo), pinned_link);
66	if (!bo)
67	break;
68	xe_bo_get(bo);
69	list_move_tail(&bo->pinned_link, &still_in_list);
70	spin_unlock(&xe->pinned.lock);
71
72	xe_bo_lock(bo, false);
73	ret = xe_bo_evict_pinned(bo);
74	xe_bo_unlock(bo);
75	xe_bo_put(bo);
76	if (ret) {
77	spin_lock(&xe->pinned.lock);
78	list_splice_tail(&still_in_list,
79	&xe->pinned.external_vram);
80	spin_unlock(&xe->pinned.lock);
81	return ret;
82	}
83		97
84	spin_lock(&xe->pinned.lock);	98	if (!ret)
85	}	99	ret = xe_bo_apply_to_pinned(xe, &xe->pinned.late.kernel_bo_present,
86	list_splice_tail(&still_in_list, &xe->pinned.external_vram);	100	&xe->pinned.late.evicted, xe_bo_evict_pinned);
87	spin_unlock(&xe->pinned.lock);
88		101
89	/*	102	/*
90	* Wait for all user BO to be evicted as those evictions depend on the	103	* Wait for all user BO to be evicted as those evictions depend on the
@@ -93,32 +106,49 @@ int xe_bo_evict_all(struct xe_device *xe) · 2 unmodified lines
93	for_each_tile(tile, xe, id)	106	for_each_tile(tile, xe, id)
94	xe_tile_migrate_wait(tile);	107	xe_tile_migrate_wait(tile);
95		108
96	spin_lock(&xe->pinned.lock);	109	if (ret)
97	for (;;) {	110	return ret;
98	bo = list_first_entry_or_null(&xe->pinned.kernel_bo_present,
99	typeof(*bo), pinned_link);
100	if (!bo)
101	break;
102	xe_bo_get(bo);
103	list_move_tail(&bo->pinned_link, &xe->pinned.evicted);
104	spin_unlock(&xe->pinned.lock);
105		111
106	xe_bo_lock(bo, false);	112	return xe_bo_apply_to_pinned(xe, &xe->pinned.early.kernel_bo_present,
107	ret = xe_bo_evict_pinned(bo);	113	&xe->pinned.early.evicted,
108	xe_bo_unlock(bo);	114	xe_bo_evict_pinned);
109	xe_bo_put(bo);	115	}
110	if (ret)
111	return ret;
112		116
113	spin_lock(&xe->pinned.lock);	117	static int xe_bo_restore_and_map_ggtt(struct xe_bo *bo)
		118	{
		119	struct xe_device *xe = xe_bo_device(bo);
		120	int ret;
		121
		122	ret = xe_bo_restore_pinned(bo);
		123	if (ret)
		124	return ret;
		125
		126	if (bo->flags & XE_BO_FLAG_GGTT) {
		127	struct xe_tile *tile;
		128	u8 id;
		129
		130	for_each_tile(tile, xe_bo_device(bo), id) {
		131	if (tile != bo->tile && !(bo->flags & XE_BO_FLAG_GGTTx(tile)))
		132	continue;
		133
		134	mutex_lock(&tile->mem.ggtt->lock);
		135	xe_ggtt_map_bo(tile->mem.ggtt, bo);
		136	mutex_unlock(&tile->mem.ggtt->lock);
		137	}
114	}	138	}
115	spin_unlock(&xe->pinned.lock);	139
		140	/*
		141	* We expect validate to trigger a move VRAM and our move code
		142	* should setup the iosys map.
		143	*/
		144	xe_assert(xe, !(bo->flags & XE_BO_FLAG_PINNED_LATE_RESTORE) \|\|
		145	!iosys_map_is_null(&bo->vmap));
116		146
117	return 0;	147	return 0;
118	}	148	}
119		149
120	/**	150	/**
121	* xe_bo_restore_kernel - restore kernel BOs to VRAM	151	* xe_bo_restore_early - restore early phase kernel BOs to VRAM
122	*	152	*
123	* @xe: xe device	153	* @xe: xe device
124	*	154	*
@@ -128,111 +158,130 @@ int xe_bo_evict_all(struct xe_device *xe) · 3 unmodified lines
128	* This function should be called early, before trying to init the GT, on device	158	* This function should be called early, before trying to init the GT, on device
129	* resume.	159	* resume.
130	*/	160	*/
131	int xe_bo_restore_kernel(struct xe_device *xe)	161	int xe_bo_restore_early(struct xe_device *xe)
132	{	162	{
133	struct xe_bo *bo;	163	return xe_bo_apply_to_pinned(xe, &xe->pinned.early.evicted,
134	int ret;	164	&xe->pinned.early.kernel_bo_present,
		165	xe_bo_restore_and_map_ggtt);
		166	}
135		167
136	spin_lock(&xe->pinned.lock);	168	/**
137	for (;;) {	169	* xe_bo_restore_late - restore pinned late phase BOs
138	bo = list_first_entry_or_null(&xe->pinned.evicted,	170	*
139	typeof(*bo), pinned_link);	171	* @xe: xe device
140	if (!bo)	172	*
141	break;	173	* Move pinned user and kernel BOs which can use blitter from temporary
142	xe_bo_get(bo);	174	* (typically system) memory to VRAM. All moves done via TTM calls.
143	list_move_tail(&bo->pinned_link, &xe->pinned.kernel_bo_present);	175	*
144	spin_unlock(&xe->pinned.lock);	176	* This function should be called late, after GT init, on device resume.
		177	*/
		178	int xe_bo_restore_late(struct xe_device *xe)
		179	{
		180	struct xe_tile *tile;
		181	int ret, id;
145		182
146	xe_bo_lock(bo, false);	183	ret = xe_bo_apply_to_pinned(xe, &xe->pinned.late.evicted,
147	ret = xe_bo_restore_pinned(bo);	184	&xe->pinned.late.kernel_bo_present,
148	xe_bo_unlock(bo);	185	xe_bo_restore_and_map_ggtt);
149	if (ret) {
150	xe_bo_put(bo);
151	return ret;
152	}
153		186
154	if (bo->flags & XE_BO_FLAG_GGTT) {	187	for_each_tile(tile, xe, id)
155	struct xe_tile *tile;	188	xe_tile_migrate_wait(tile);
156	u8 id;
157		189
158	for_each_tile(tile, xe, id) {	190	if (ret)
159	if (tile != bo->tile && !(bo->flags & XE_BO_FLAG_GGTTx(tile)))	191	return ret;
160	continue;
161		192
162	mutex_lock(&tile->mem.ggtt->lock);	193	if (!IS_DGFX(xe))
163	xe_ggtt_map_bo(tile->mem.ggtt, bo);	194	return 0;
164	mutex_unlock(&tile->mem.ggtt->lock);
165	}
166	}
167		195
168	/*	196	/* Pinned user memory in VRAM should be validated on resume */
169	* We expect validate to trigger a move VRAM and our move code	197	ret = xe_bo_apply_to_pinned(xe, &xe->pinned.late.external,
170	* should setup the iosys map.	198	&xe->pinned.late.external,
171	*/	199	xe_bo_restore_pinned);
172	xe_assert(xe, !iosys_map_is_null(&bo->vmap));
173		200
174	xe_bo_put(bo);	201	/* Wait for restore to complete */
		202	for_each_tile(tile, xe, id)
		203	xe_tile_migrate_wait(tile);
175		204
176	spin_lock(&xe->pinned.lock);	205	return ret;
177	}	206	}
178	spin_unlock(&xe->pinned.lock);
179		207
180	return 0;	208	static void xe_bo_pci_dev_remove_pinned(struct xe_device *xe)
		209	{
		210	struct xe_tile *tile;
		211	unsigned int id;
		212
		213	(void)xe_bo_apply_to_pinned(xe, &xe->pinned.late.external,
		214	&xe->pinned.late.external,
		215	xe_bo_dma_unmap_pinned);
		216	for_each_tile(tile, xe, id)
		217	xe_tile_migrate_wait(tile);
181	}	218	}
182		219
183	/**	220	/**
184	* xe_bo_restore_user - restore pinned user BOs to VRAM	221	* xe_bo_pci_dev_remove_all() - Handle bos when the pci_device is about to be removed
185	*	222	* @xe: The xe device.
186	* @xe: xe device
187	*	223	*
188	* Move pinned user BOs from temporary (typically system) memory to VRAM via	224	* On pci_device removal we need to drop all dma mappings and move
189	* CPU. All moves done via TTM calls.	225	* the data of exported bos out to system. This includes SVM bos and
		226	* exported dma-buf bos. This is done by evicting all bos, but
		227	* the evict placement in xe_evict_flags() is chosen such that all
		228	* bos except those mentioned are purged, and thus their memory
		229	* is released.
190	*	230	*
191	* This function should be called late, after GT init, on device resume.	231	* For pinned bos, we're unmapping dma.
192	*/	232	*/
193	int xe_bo_restore_user(struct xe_device *xe)	233	void xe_bo_pci_dev_remove_all(struct xe_device *xe)
194	{	234	{
195	struct xe_bo *bo;	235	unsigned int mem_type;
196	struct xe_tile *tile;
197	struct list_head still_in_list;
198	u8 id;
199	int ret;
200		236
201	if (!IS_DGFX(xe))	237	/*
202	return 0;	238	* Move pagemap bos and exported dma-buf to system, and
		239	* purge everything else.
		240	*/
		241	for (mem_type = XE_PL_VRAM1; mem_type >= XE_PL_TT; --mem_type) {
		242	struct ttm_resource_manager *man =
		243	ttm_manager_type(&xe->ttm, mem_type);
203		244
204	/* Pinned user memory in VRAM should be validated on resume */	245	if (man) {
205	INIT_LIST_HEAD(&still_in_list);	246	int ret = ttm_resource_manager_evict_all(&xe->ttm, man);
206	spin_lock(&xe->pinned.lock);
207	for (;;) {
208	bo = list_first_entry_or_null(&xe->pinned.external_vram,
209	typeof(*bo), pinned_link);
210	if (!bo)
211	break;
212	list_move_tail(&bo->pinned_link, &still_in_list);
213	xe_bo_get(bo);
214	spin_unlock(&xe->pinned.lock);
215		247
216	xe_bo_lock(bo, false);	248	drm_WARN_ON(&xe->drm, ret);
217	ret = xe_bo_restore_pinned(bo);
218	xe_bo_unlock(bo);
219	xe_bo_put(bo);
220	if (ret) {
221	spin_lock(&xe->pinned.lock);
222	list_splice_tail(&still_in_list,
223	&xe->pinned.external_vram);
224	spin_unlock(&xe->pinned.lock);
225	return ret;
226	}	249	}
227
228	spin_lock(&xe->pinned.lock);
229	}	250	}
230	list_splice_tail(&still_in_list, &xe->pinned.external_vram);
231	spin_unlock(&xe->pinned.lock);
232		251
233	/* Wait for restore to complete */	252	xe_bo_pci_dev_remove_pinned(xe);
234	for_each_tile(tile, xe, id)	253	}
235	xe_tile_migrate_wait(tile);
236		254
237	return 0;	255	static void xe_bo_pinned_fini(void *arg)
		256	{
		257	struct xe_device *xe = arg;
		258
		259	(void)xe_bo_apply_to_pinned(xe, &xe->pinned.late.kernel_bo_present,
		260	&xe->pinned.late.kernel_bo_present,
		261	xe_bo_dma_unmap_pinned);
		262	(void)xe_bo_apply_to_pinned(xe, &xe->pinned.early.kernel_bo_present,
		263	&xe->pinned.early.kernel_bo_present,
		264	xe_bo_dma_unmap_pinned);
		265	}
		266
		267	/**
		268	* xe_bo_pinned_init() - Initialize pinned bo tracking
		269	* @xe: The xe device.
		270	*
		271	* Initializes the lists and locks required for pinned bo
		272	* tracking and registers a callback to dma-unmap
		273	* any remaining pinned bos on pci device removal.
		274	*
		275	* Return: %0 on success, negative error code on error.
		276	*/
		277	int xe_bo_pinned_init(struct xe_device *xe)
		278	{
		279	spin_lock_init(&xe->pinned.lock);
		280	INIT_LIST_HEAD(&xe->pinned.early.kernel_bo_present);
		281	INIT_LIST_HEAD(&xe->pinned.early.evicted);
		282	INIT_LIST_HEAD(&xe->pinned.late.kernel_bo_present);
		283	INIT_LIST_HEAD(&xe->pinned.late.evicted);
		284	INIT_LIST_HEAD(&xe->pinned.late.external);
		285
		286	return devm_add_action_or_reset(xe->drm.dev, xe_bo_pinned_fini, xe);
238	}	287	}

drivers/gpu/drm/xe/xe_bo_evict.h+5−2

@@ -9,7 +9,10 @@ · 8 unmodified lines
9	struct xe_device;	9	struct xe_device;
10		10
11	int xe_bo_evict_all(struct xe_device *xe);	11	int xe_bo_evict_all(struct xe_device *xe);
12	int xe_bo_restore_kernel(struct xe_device *xe);	12	int xe_bo_restore_early(struct xe_device *xe);
13	int xe_bo_restore_user(struct xe_device *xe);	13	int xe_bo_restore_late(struct xe_device *xe);
14		14
		15	void xe_bo_pci_dev_remove_all(struct xe_device *xe);
		16
		17	int xe_bo_pinned_init(struct xe_device *xe);
15	#endif	18	#endif

drivers/gpu/drm/xe/xe_bo_types.h+2−0

 struct xe_bo {
 	/** @ttm: TTM base buffer object */
 	struct ttm_buffer_object ttm;
+	/** @backup_obj: The backup object when pinned and suspended (vram only) */
+	struct xe_bo *backup_obj;
 	/** @size: Size of this buffer object */
 	size_t size;
 	/** @flags: flags for this buffer object */

drivers/gpu/drm/xe/xe_configfs.c+250−0

@@ -0,0 +1,250 @@
	1	// SPDX-License-Identifier: MIT
	2	/*
	3	* Copyright © 2025 Intel Corporation
	4	*/
	5
	6	#include <linux/configfs.h>
	7	#include <linux/init.h>
	8	#include <linux/module.h>
	9	#include <linux/pci.h>
	10
	11	#include "xe_configfs.h"
	12	#include "xe_module.h"
	13
	14	/**
	15	* DOC: Xe Configfs
	16	*
	17	* Overview
	18	* =========
	19	*
	20	* Configfs is a filesystem-based manager of kernel objects. XE KMD registers a
	21	* configfs subsystem called ``'xe'`` that creates a directory in the mounted configfs directory
	22	* The user can create devices under this directory and configure them as necessary
	23	* See Documentation/filesystems/configfs.rst for more information about how configfs works.
	24	*
	25	* Create devices
	26	* ===============
	27	*
	28	* In order to create a device, the user has to create a directory inside ``'xe'``::
	29	*
	30	* mkdir /sys/kernel/config/xe/0000:03:00.0/
	31	*
	32	* Every device created is populated by the driver with entries that can be
	33	* used to configure it::
	34	*
	35	* /sys/kernel/config/xe/
	36	* .. 0000:03:00.0/
	37	* ... survivability_mode
	38	*
	39	* Configure Attributes
	40	* ====================
	41	*
	42	* Survivability mode:
	43	* -------------------
	44	*
	45	* Enable survivability mode on supported cards. This setting only takes
	46	* effect when probing the device. Example to enable it::
	47	*
	48	* # echo 1 > /sys/kernel/config/xe/0000:03:00.0/survivability_mode
	49	* # echo 0000:03:00.0 > /sys/bus/pci/drivers/xe/bind (Enters survivability mode if supported)
	50	*
	51	* Remove devices
	52	* ==============
	53	*
	54	* The created device directories can be removed using ``rmdir``::
	55	*
	56	* rmdir /sys/kernel/config/xe/0000:03:00.0/
	57	*/
	58
	59	struct xe_config_device {
	60	struct config_group group;
	61
	62	bool survivability_mode;
	63
	64	/* protects attributes */
	65	struct mutex lock;
	66	};
	67
	68	static struct xe_config_device to_xe_config_device(struct config_item item)
	69	{
	70	return container_of(to_config_group(item), struct xe_config_device, group);
	71	}
	72
	73	static ssize_t survivability_mode_show(struct config_item item, char page)
	74	{
	75	struct xe_config_device *dev = to_xe_config_device(item);
	76
	77	return sprintf(page, "%d\n", dev->survivability_mode);
	78	}
	79
	80	static ssize_t survivability_mode_store(struct config_item item, const char page, size_t len)
	81	{
	82	struct xe_config_device *dev = to_xe_config_device(item);
	83	bool survivability_mode;
	84	int ret;
	85
	86	ret = kstrtobool(page, &survivability_mode);
	87	if (ret)
	88	return ret;
	89
	90	mutex_lock(&dev->lock);
	91	dev->survivability_mode = survivability_mode;
	92	mutex_unlock(&dev->lock);
	93
	94	return len;
	95	}
	96
	97	CONFIGFS_ATTR(, survivability_mode);
	98
	99	static struct configfs_attribute *xe_config_device_attrs[] = {
	100	&attr_survivability_mode,
	101	NULL,
	102	};
	103
	104	static void xe_config_device_release(struct config_item *item)
	105	{
	106	struct xe_config_device *dev = to_xe_config_device(item);
	107
	108	mutex_destroy(&dev->lock);
	109	kfree(dev);
	110	}
	111
	112	static struct configfs_item_operations xe_config_device_ops = {
	113	.release = xe_config_device_release,
	114	};
	115
	116	static const struct config_item_type xe_config_device_type = {
	117	.ct_item_ops = &xe_config_device_ops,
	118	.ct_attrs = xe_config_device_attrs,
	119	.ct_owner = THIS_MODULE,
	120	};
	121
	122	static struct config_group xe_config_make_device_group(struct config_group group,
	123	const char *name)
	124	{
	125	unsigned int domain, bus, slot, function;
	126	struct xe_config_device *dev;
	127	struct pci_dev *pdev;
	128	int ret;
	129
	130	ret = sscanf(name, "%04x:%02x:%02x.%x", &domain, &bus, &slot, &function);
	131	if (ret != 4)
	132	return ERR_PTR(-EINVAL);
	133
	134	pdev = pci_get_domain_bus_and_slot(domain, bus, PCI_DEVFN(slot, function));
	135	if (!pdev)
	136	return ERR_PTR(-EINVAL);
	137
	138	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
	139	if (!dev)
	140	return ERR_PTR(-ENOMEM);
	141
	142	config_group_init_type_name(&dev->group, name, &xe_config_device_type);
	143
	144	mutex_init(&dev->lock);
	145
	146	return &dev->group;
	147	}
	148
	149	static struct configfs_group_operations xe_config_device_group_ops = {
	150	.make_group = xe_config_make_device_group,
	151	};
	152
	153	static const struct config_item_type xe_configfs_type = {
	154	.ct_group_ops = &xe_config_device_group_ops,
	155	.ct_owner = THIS_MODULE,
	156	};
	157
	158	static struct configfs_subsystem xe_configfs = {
	159	.su_group = {
	160	.cg_item = {
	161	.ci_namebuf = "xe",
	162	.ci_type = &xe_configfs_type,
	163	},
	164	},
	165	};
	166
	167	static struct xe_config_device configfs_find_group(struct pci_dev pdev)
	168	{
	169	struct config_item *item;
	170	char name[64];
	171
	172	snprintf(name, sizeof(name), "%04x:%02x:%02x.%x", pci_domain_nr(pdev->bus),
	173	pdev->bus->number, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
	174
	175	mutex_lock(&xe_configfs.su_mutex);
	176	item = config_group_find_item(&xe_configfs.su_group, name);
	177	mutex_unlock(&xe_configfs.su_mutex);
	178
	179	if (!item)
	180	return NULL;
	181
	182	return to_xe_config_device(item);
	183	}
	184
	185	/**
	186	* xe_configfs_get_survivability_mode - get configfs survivability mode attribute
	187	* @pdev: pci device
	188	*
	189	* find the configfs group that belongs to the pci device and return
	190	* the survivability mode attribute
	191	*
	192	* Return: survivability mode if config group is found, false otherwise
	193	*/
	194	bool xe_configfs_get_survivability_mode(struct pci_dev *pdev)
	195	{
	196	struct xe_config_device *dev = configfs_find_group(pdev);
	197	bool mode;
	198
	199	if (!dev)
	200	return false;
	201
	202	mode = dev->survivability_mode;
	203	config_item_put(&dev->group.cg_item);
	204
	205	return mode;
	206	}
	207
	208	/**
	209	* xe_configfs_clear_survivability_mode - clear configfs survivability mode attribute
	210	* @pdev: pci device
	211	*
	212	* find the configfs group that belongs to the pci device and clear survivability
	213	* mode attribute
	214	*/
	215	void xe_configfs_clear_survivability_mode(struct pci_dev *pdev)
	216	{
	217	struct xe_config_device *dev = configfs_find_group(pdev);
	218
	219	if (!dev)
	220	return;
	221
	222	mutex_lock(&dev->lock);
	223	dev->survivability_mode = 0;
	224	mutex_unlock(&dev->lock);
	225
	226	config_item_put(&dev->group.cg_item);
	227	}
	228
	229	int __init xe_configfs_init(void)
	230	{
	231	struct config_group *root = &xe_configfs.su_group;
	232	int ret;
	233
	234	config_group_init(root);
	235	mutex_init(&xe_configfs.su_mutex);
	236	ret = configfs_register_subsystem(&xe_configfs);
	237	if (ret) {
	238	pr_err("Error %d while registering %s subsystem\n",
	239	ret, root->cg_item.ci_namebuf);
	240	return ret;
	241	}
	242
	243	return 0;
	244	}
	245
	246	void __exit xe_configfs_exit(void)
	247	{
	248	configfs_unregister_subsystem(&xe_configfs);
	249	}
	250

drivers/gpu/drm/xe/xe_configfs.h+24−0

@@ -0,0 +1,24 @@
	1	/* SPDX-License-Identifier: MIT */
	2	/*
	3	* Copyright © 2025 Intel Corporation
	4	*/
	5	#ifndef _XE_CONFIGFS_H_
	6	#define _XE_CONFIGFS_H_
	7
	8	#include <linux/types.h>
	9
	10	struct pci_dev;
	11
	12	#if IS_ENABLED(CONFIG_CONFIGFS_FS)
	13	int xe_configfs_init(void);
	14	void xe_configfs_exit(void);
	15	bool xe_configfs_get_survivability_mode(struct pci_dev *pdev);
	16	void xe_configfs_clear_survivability_mode(struct pci_dev *pdev);
	17	#else
	18	static inline int xe_configfs_init(void) { return 0; };
	19	static inline void xe_configfs_exit(void) {};
	20	static inline bool xe_configfs_get_survivability_mode(struct pci_dev *pdev) { return false; };
	21	static inline void xe_configfs_clear_survivability_mode(struct pci_dev *pdev) {};
	22	#endif
	23
	24	#endif

drivers/gpu/drm/xe/xe_device.c+19−10

 #include "regs/xe_gt_regs.h"
 #include "regs/xe_regs.h"
 #include "xe_bo.h"
+#include "xe_bo_evict.h"
 #include "xe_debugfs.h"
 #include "xe_devcoredump.h"
 #include "xe_dma_buf.h"
 			xa_erase(&xe->usm.asid_to_vm, asid);
 	}
-	spin_lock_init(&xe->pinned.lock);
+	err = xe_bo_pinned_init(xe);
-	INIT_LIST_HEAD(&xe->pinned.kernel_bo_present);
+	if (err)
-	INIT_LIST_HEAD(&xe->pinned.external_vram);
+		goto err;
-	INIT_LIST_HEAD(&xe->pinned.evicted);
 	xe->preempt_fence_wq = alloc_ordered_workqueue("xe-preempt-fence-wq",
 						       WQ_MEM_RECLAIM);
 static bool xe_driver_flr_disabled(struct xe_device *xe)
 {
-	return xe_mmio_read32(xe_root_tile_mmio(xe), GU_CNTL_PROTECTED) & DRIVERINT_FLR_DIS;
+	if (IS_SRIOV_VF(xe))
+		return true;
+	if (xe_mmio_read32(xe_root_tile_mmio(xe), GU_CNTL_PROTECTED) & DRIVERINT_FLR_DIS) {
+		drm_info(&xe->drm, "Driver-FLR disabled by BIOS\n");
+		return true;
+	}
+	return false;
 }
 /*
  */
 static void __xe_driver_flr(struct xe_device *xe)
 {
-	const unsigned int flr_timeout = 3 * MICRO; /* specs recommend a 3s wait */
+	const unsigned int flr_timeout = 3 * USEC_PER_SEC; /* specs recommend a 3s wait */
 	struct xe_mmio *mmio = xe_root_tile_mmio(xe);
 	int ret;
 static void xe_driver_flr(struct xe_device *xe)
 {
-	if (xe_driver_flr_disabled(xe)) {
+	if (xe_driver_flr_disabled(xe))
-		drm_info_once(&xe->drm, "BIOS Disabled Driver-FLR\n");
 		return;
-	}
 	__xe_driver_flr(xe);
 }
 	sriov_update_device_info(xe);
 	err = xe_pcode_probe_early(xe);
-	if (err) {
+	if (err || xe_survivability_mode_is_requested(xe)) {
 		int save_err = err;
 		/*
 	return 0;
 }
+ALLOW_ERROR_INJECTION(xe_device_probe_early, ERRNO); /* See xe_pci_probe() */
 static int probe_has_flat_ccs(struct xe_device *xe)
 {
 	xe_display_unregister(xe);
 	drm_dev_unplug(&xe->drm);
+	xe_bo_pci_dev_remove_all(xe);
 }
 void xe_device_shutdown(struct xe_device *xe)

drivers/gpu/drm/xe/xe_device_types.h+24−8

 	resource_size_t actual_physical_size;
 	/** @mapping: pointer to VRAM mappable space */
 	void __iomem *mapping;
+	/** @ttm: VRAM TTM manager */
+	struct xe_ttm_vram_mgr ttm;
+#if IS_ENABLED(CONFIG_DRM_XE_DEVMEM_MIRROR)
 	/** @pagemap: Used to remap device memory as ZONE_DEVICE */
 	struct dev_pagemap pagemap;
 	/**
 	 * This is generated when remap device memory as ZONE_DEVICE
 	 */
 	resource_size_t hpa_base;
-	/** @ttm: VRAM TTM manager */
+#endif
-	struct xe_ttm_vram_mgr ttm;
 };
 /**
 		u8 has_atomic_enable_pte_bit:1;
 		/** @info.has_device_atomics_on_smem: Supports device atomics on SMEM */
 		u8 has_device_atomics_on_smem:1;
+		/** @info.has_fan_control: Device supports fan control */
+		u8 has_fan_control:1;
 		/** @info.has_flat_ccs: Whether flat CCS metadata is used */
 		u8 has_flat_ccs:1;
 		/** @info.has_heci_cscfi: device has heci cscfi */
 		u8 has_usm:1;
 		/** @info.is_dgfx: is discrete device */
 		u8 is_dgfx:1;
+		/** @info.needs_scratch: needs scratch page for oob prefetch to work */
+		u8 needs_scratch:1;
 		/**
 		 * @info.probe_display: Probe display hardware.  If set to
 		 * false, the driver will behave as if there is no display
 	struct {
 		/** @pinned.lock: protected pinned BO list state */
 		spinlock_t lock;
-		/** @pinned.kernel_bo_present: pinned kernel BO that are present */
+		/** @pinned.early: early pinned lists */
-		struct list_head kernel_bo_present;
+		struct {
-		/** @pinned.evicted: pinned BO that have been evicted */
+			/** @pinned.early.kernel_bo_present: pinned kernel BO that are present */
-		struct list_head evicted;
+			struct list_head kernel_bo_present;
-		/** @pinned.external_vram: pinned external BO in vram*/
+			/** @pinned.early.evicted: pinned BO that have been evicted */
-		struct list_head external_vram;
+			struct list_head evicted;
+		} early;
+		/** @pinned.late: late pinned lists */
+		struct {
+			/** @pinned.late.kernel_bo_present: pinned kernel BO that are present */
+			struct list_head kernel_bo_present;
+			/** @pinned.late.evicted: pinned BO that have been evicted */
+			struct list_head evicted;
+			/** @pinned.external: pinned external and dma-buf. */
+			struct list_head external;
+		} late;
 	} pinned;
 	/** @ufence_wq: user fence wait queue */

drivers/gpu/drm/xe/xe_dma_buf.c+1−4

 			     struct sg_table *sgt,
 			     enum dma_data_direction dir)
 {
-	struct dma_buf *dma_buf = attach->dmabuf;
+	if (sg_page(sgt->sgl)) {
-	struct xe_bo *bo = gem_to_xe_bo(dma_buf->priv);
-	if (!xe_bo_is_vram(bo)) {
 		dma_unmap_sgtable(attach->dev, sgt, dir, 0);
 		sg_free_table(sgt);
 		kfree(sgt);

drivers/gpu/drm/xe/xe_force_wake.c+0−6

 	fw->gt = gt;
 	spin_lock_init(&fw->lock);
-	/* Assuming gen11+ so assert this assumption is correct */
-	xe_gt_assert(gt, GRAPHICS_VER(gt_to_xe(gt)) >= 11);
 	if (xe->info.graphics_verx100 >= 1270) {
 		init_domain(fw, XE_FW_DOMAIN_ID_GT,
 			    FORCEWAKE_GT,
 {
 	int i, j;
-	/* Assuming gen11+ so assert this assumption is correct */
-	xe_gt_assert(gt, GRAPHICS_VER(gt_to_xe(gt)) >= 11);
 	if (!xe_gt_is_media_type(gt))
 		init_domain(fw, XE_FW_DOMAIN_ID_RENDER,
 			    FORCEWAKE_RENDER,

drivers/gpu/drm/xe/xe_ggtt.c+1−1

@@ -365,7 +365,7 @@ int xe_ggtt_init(struct xe_ggtt *ggtt) · 364 unmodified lines
365	* scratch entries, rather keep the scratch page in system memory on	365	* scratch entries, rather keep the scratch page in system memory on
366	* platforms where 64K pages are needed for VRAM.	366	* platforms where 64K pages are needed for VRAM.
367	*/	367	*/
368	flags = XE_BO_FLAG_PINNED;	368	flags = 0;
369	if (ggtt->flags & XE_GGTT_FLAGS_64K)	369	if (ggtt->flags & XE_GGTT_FLAGS_64K)
370	flags \|= XE_BO_FLAG_SYSTEM;	370	flags \|= XE_BO_FLAG_SYSTEM;
371	else	371	else

drivers/gpu/drm/xe/xe_gt.c+63−21

 #include <generated/xe_wa_oob.h>
+#include "instructions/xe_alu_commands.h"
 #include "instructions/xe_gfxpipe_commands.h"
 #include "instructions/xe_mi_commands.h"
+#include "regs/xe_engine_regs.h"
 #include "regs/xe_gt_regs.h"
 #include "xe_assert.h"
 #include "xe_bb.h"
 	return 0;
 }
-/*
- * Convert back from encoded value to type-safe, only to be used when reg.mcr
- * is true
- */
-static struct xe_reg_mcr to_xe_reg_mcr(const struct xe_reg reg)
-{
-	return (const struct xe_reg_mcr){.__reg.raw = reg.raw };
-}
 static int emit_wa_job(struct xe_gt *gt, struct xe_exec_queue *q)
 {
 	struct xe_reg_sr *sr = &q->hwe->reg_lrc;
 	struct xe_bb *bb;
 	struct dma_fence *fence;
 	long timeout;
+	int count_rmw = 0;
 	int count = 0;
 	if (q->hwe->class == XE_ENGINE_CLASS_RENDER)
 	if (IS_ERR(bb))
 		return PTR_ERR(bb);
-	xa_for_each(&sr->xa, idx, entry)
+	/* count RMW registers as those will be handled separately */
-		++count;
+	xa_for_each(&sr->xa, idx, entry) {
+		if (entry->reg.masked || entry->clr_bits == ~0)
+			++count;
+		else
+			++count_rmw;
+	}
-	if (count) {
+	if (count || count_rmw)
 		xe_gt_dbg(gt, "LRC WA %s save-restore batch\n", sr->name);
+	if (count) {
+		/* emit single LRI with all non RMW regs */
 		bb->cs[bb->len++] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(count);
 		xa_for_each(&sr->xa, idx, entry) {
 			struct xe_reg reg = entry->reg;
-			struct xe_reg_mcr reg_mcr = to_xe_reg_mcr(reg);
 			u32 val;
-			/*
-			 * Skip reading the register if it's not really needed
-			 */
 			if (reg.masked)
 				val = entry->clr_bits << 16;
-			else if (entry->clr_bits + 1)
+			else if (entry->clr_bits == ~0)
-				val = (reg.mcr ?
-				       xe_gt_mcr_unicast_read_any(gt, reg_mcr) :
-				       xe_mmio_read32(&gt->mmio, reg)) & (~entry->clr_bits);
-			else
 				val = 0;
+			else
+				continue;
 			val |= entry->set_bits;
 		}
 	}
+	if (count_rmw) {
+		/* emit MI_MATH for each RMW reg */
+		xa_for_each(&sr->xa, idx, entry) {
+			if (entry->reg.masked || entry->clr_bits == ~0)
+				continue;
+			bb->cs[bb->len++] = MI_LOAD_REGISTER_REG | MI_LRR_DST_CS_MMIO;
+			bb->cs[bb->len++] = entry->reg.addr;
+			bb->cs[bb->len++] = CS_GPR_REG(0, 0).addr;
+			bb->cs[bb->len++] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(2) |
+					    MI_LRI_LRM_CS_MMIO;
+			bb->cs[bb->len++] = CS_GPR_REG(0, 1).addr;
+			bb->cs[bb->len++] = entry->clr_bits;
+			bb->cs[bb->len++] = CS_GPR_REG(0, 2).addr;
+			bb->cs[bb->len++] = entry->set_bits;
+			bb->cs[bb->len++] = MI_MATH(8);
+			bb->cs[bb->len++] = CS_ALU_INSTR_LOAD(SRCA, REG0);
+			bb->cs[bb->len++] = CS_ALU_INSTR_LOADINV(SRCB, REG1);
+			bb->cs[bb->len++] = CS_ALU_INSTR_AND;
+			bb->cs[bb->len++] = CS_ALU_INSTR_STORE(REG0, ACCU);
+			bb->cs[bb->len++] = CS_ALU_INSTR_LOAD(SRCA, REG0);
+			bb->cs[bb->len++] = CS_ALU_INSTR_LOAD(SRCB, REG2);
+			bb->cs[bb->len++] = CS_ALU_INSTR_OR;
+			bb->cs[bb->len++] = CS_ALU_INSTR_STORE(REG0, ACCU);
+			bb->cs[bb->len++] = MI_LOAD_REGISTER_REG | MI_LRR_SRC_CS_MMIO;
+			bb->cs[bb->len++] = CS_GPR_REG(0, 0).addr;
+			bb->cs[bb->len++] = entry->reg.addr;
+			xe_gt_dbg(gt, "REG[%#x] = ~%#x|%#x\n",
+				  entry->reg.addr, entry->clr_bits, entry->set_bits);
+		}
+		/* reset used GPR */
+		bb->cs[bb->len++] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(3) | MI_LRI_LRM_CS_MMIO;
+		bb->cs[bb->len++] = CS_GPR_REG(0, 0).addr;
+		bb->cs[bb->len++] = 0;
+		bb->cs[bb->len++] = CS_GPR_REG(0, 1).addr;
+		bb->cs[bb->len++] = 0;
+		bb->cs[bb->len++] = CS_GPR_REG(0, 2).addr;
+		bb->cs[bb->len++] = 0;
+	}
 	xe_lrc_emit_hwe_state_instructions(q, bb);
 	job = xe_bb_create_job(q, bb);

drivers/gpu/drm/xe/xe_gt_debugfs.c+22−8

 	return 0;
 }
-static const struct drm_info_list debugfs_list[] = {
+/*
-	{"hw_engines", .show = xe_gt_debugfs_simple_show, .data = hw_engines},
+ * only for GT debugfs files which can be safely used on the VF as well:
+ * - without access to the GT privileged registers
+ * - without access to the PF specific data
+ */
+static const struct drm_info_list vf_safe_debugfs_list[] = {
 	{"force_reset", .show = xe_gt_debugfs_simple_show, .data = force_reset},
 	{"force_reset_sync", .show = xe_gt_debugfs_simple_show, .data = force_reset_sync},
 	{"sa_info", .show = xe_gt_debugfs_simple_show, .data = sa_info},
 	{"topology", .show = xe_gt_debugfs_simple_show, .data = topology},
-	{"steering", .show = xe_gt_debugfs_simple_show, .data = steering},
 	{"ggtt", .show = xe_gt_debugfs_simple_show, .data = ggtt},
-	{"powergate_info", .show = xe_gt_debugfs_simple_show, .data = powergate_info},
 	{"register-save-restore", .show = xe_gt_debugfs_simple_show, .data = register_save_restore},
 	{"workarounds", .show = xe_gt_debugfs_simple_show, .data = workarounds},
 	{"tunings", .show = xe_gt_debugfs_simple_show, .data = tunings},
-	{"pat", .show = xe_gt_debugfs_simple_show, .data = pat},
-	{"mocs", .show = xe_gt_debugfs_simple_show, .data = mocs},
 	{"default_lrc_rcs", .show = xe_gt_debugfs_simple_show, .data = rcs_default_lrc},
 	{"default_lrc_ccs", .show = xe_gt_debugfs_simple_show, .data = ccs_default_lrc},
 	{"default_lrc_bcs", .show = xe_gt_debugfs_simple_show, .data = bcs_default_lrc},
 	{"hwconfig", .show = xe_gt_debugfs_simple_show, .data = hwconfig},
 };
+/* everything else should be added here */
+static const struct drm_info_list pf_only_debugfs_list[] = {
+	{"hw_engines", .show = xe_gt_debugfs_simple_show, .data = hw_engines},
+	{"mocs", .show = xe_gt_debugfs_simple_show, .data = mocs},
+	{"pat", .show = xe_gt_debugfs_simple_show, .data = pat},
+	{"powergate_info", .show = xe_gt_debugfs_simple_show, .data = powergate_info},
+	{"steering", .show = xe_gt_debugfs_simple_show, .data = steering},
+};
 void xe_gt_debugfs_register(struct xe_gt *gt)
 {
 	struct xe_device *xe = gt_to_xe(gt);
 	 */
 	root->d_inode->i_private = gt;
-	drm_debugfs_create_files(debugfs_list,
+	drm_debugfs_create_files(vf_safe_debugfs_list,
-				 ARRAY_SIZE(debugfs_list),
+				 ARRAY_SIZE(vf_safe_debugfs_list),
 				 root, minor);
+	if (!IS_SRIOV_VF(xe))
+		drm_debugfs_create_files(pf_only_debugfs_list,
+					 ARRAY_SIZE(pf_only_debugfs_list),
+					 root, minor);
 	xe_uc_debugfs_register(&gt->uc, root);
 	if (IS_SRIOV_PF(xe))

drivers/gpu/drm/xe/xe_gt_mcr.c+2−1

@@ -345,7 +345,8 @@ fallback: · 344 unmodified lines
345	* Some older platforms don't have tables or don't have complete tables.	345	* Some older platforms don't have tables or don't have complete tables.
346	* Newer platforms should always have the required info.	346	* Newer platforms should always have the required info.
347	*/	347	*/
348	if (GRAPHICS_VERx100(gt_to_xe(gt)) >= 2000)	348	if (GRAPHICS_VERx100(gt_to_xe(gt)) >= 2000 &&
		349	!gt_to_xe(gt)->info.force_execlist)
349	xe_gt_err(gt, "Slice/Subslice counts missing from hwconfig table; using typical fallback values\n");	350	xe_gt_err(gt, "Slice/Subslice counts missing from hwconfig table; using typical fallback values\n");
350		351
351	if (gt_to_xe(gt)->info.platform == XE_PVC)	352	if (gt_to_xe(gt)->info.platform == XE_PVC)

drivers/gpu/drm/xe/xe_gt_pagefault.c+10−3

 	atomic = access_is_atomic(pf->access_type);
 	if (xe_vma_is_cpu_addr_mirror(vma))
-		err = xe_svm_handle_pagefault(vm, vma, gt_to_tile(gt),
+		err = xe_svm_handle_pagefault(vm, vma, gt,
 					      pf->page_addr, atomic);
 	else
 		err = handle_vma_pagefault(gt, vma, atomic);
 	num_eus = bitmap_weight(gt->fuse_topo.eu_mask_per_dss,
 				XE_MAX_EU_FUSE_BITS) * num_dss;
-	/* user can issue separate page faults per EU and per CS */
+	/*
+	 * user can issue separate page faults per EU and per CS
+	 *
+	 * XXX: Multiplier required as compute UMD are getting PF queue errors
+	 * without it. Follow on why this multiplier is required.
+	 */
+#define PF_MULTIPLIER	8
 	pf_queue->num_dw =
-		(num_eus + XE_NUM_HW_ENGINES) * PF_MSG_LEN_DW;
+		(num_eus + XE_NUM_HW_ENGINES) * PF_MSG_LEN_DW * PF_MULTIPLIER;
+#undef PF_MULTIPLIER
 	pf_queue->gt = gt;
 	pf_queue->data = devm_kcalloc(xe->drm.dev, pf_queue->num_dw,

drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c+14−6

 		return 0;
 	xe_gt_assert(gt, pf_get_lmem_alignment(gt) == SZ_2M);
-	bo = xe_bo_create_pin_map(xe, tile, NULL,
+	bo = xe_bo_create_locked(xe, tile, NULL,
-				  ALIGN(size, PAGE_SIZE),
+				 ALIGN(size, PAGE_SIZE),
-				  ttm_bo_type_kernel,
+				 ttm_bo_type_kernel,
-				  XE_BO_FLAG_VRAM_IF_DGFX(tile) |
+				 XE_BO_FLAG_VRAM_IF_DGFX(tile) |
-				  XE_BO_FLAG_NEEDS_2M |
+				 XE_BO_FLAG_NEEDS_2M |
-				  XE_BO_FLAG_PINNED);
+				 XE_BO_FLAG_PINNED |
+				 XE_BO_FLAG_PINNED_LATE_RESTORE);
 	if (IS_ERR(bo))
 		return PTR_ERR(bo);
+	err = xe_bo_pin(bo);
+	xe_bo_unlock(bo);
+	if (unlikely(err)) {
+		xe_bo_put(bo);
+		return err;
+	}
 	config->lmem_obj = bo;
 	if (xe_device_has_lmtt(xe)) {

drivers/gpu/drm/xe/xe_gt_sriov_pf_debugfs.c+49−17

  *      /sys/kernel/debug/dri/0/
  *      ├── gt0
  *      │   ├── pf
- *      │   │   ├── ggtt_available
- *      │   │   ├── ggtt_provisioned
  *      │   │   ├── contexts_provisioned
  *      │   │   ├── doorbells_provisioned
  *      │   │   ├── runtime_registers
  *      │   │   ├── negotiated_versions
  *      │   │   ├── adverse_events
+ *      ├── gt1
+ *      │   ├── pf
+ *      │   │   ├── ...
  */
 static const struct drm_info_list pf_info[] = {
-	{
-		"ggtt_available",
-		.show = xe_gt_debugfs_simple_show,
-		.data = xe_gt_sriov_pf_config_print_available_ggtt,
-	},
-	{
-		"ggtt_provisioned",
-		.show = xe_gt_debugfs_simple_show,
-		.data = xe_gt_sriov_pf_config_print_ggtt,
-	},
 	{
 		"contexts_provisioned",
 		.show = xe_gt_debugfs_simple_show,
 		.show = xe_gt_debugfs_simple_show,
 		.data = xe_gt_sriov_pf_config_print_dbs,
 	},
-	{
-		"lmem_provisioned",
-		.show = xe_gt_debugfs_simple_show,
-		.data = xe_gt_sriov_pf_config_print_lmem,
-	},
 	{
 		"runtime_registers",
 		.show = xe_gt_debugfs_simple_show,
 	},
 };
+/*
+ *      /sys/kernel/debug/dri/0/
+ *      ├── gt0
+ *      │   ├── pf
+ *      │   │   ├── ggtt_available
+ *      │   │   ├── ggtt_provisioned
+ */
+static const struct drm_info_list pf_ggtt_info[] = {
+	{
+		"ggtt_available",
+		.show = xe_gt_debugfs_simple_show,
+		.data = xe_gt_sriov_pf_config_print_available_ggtt,
+	},
+	{
+		"ggtt_provisioned",
+		.show = xe_gt_debugfs_simple_show,
+		.data = xe_gt_sriov_pf_config_print_ggtt,
+	},
+};
+/*
+ *      /sys/kernel/debug/dri/0/
+ *      ├── gt0
+ *      │   ├── pf
+ *      │   │   ├── lmem_provisioned
+ */
+static const struct drm_info_list pf_lmem_info[] = {
+	{
+		"lmem_provisioned",
+		.show = xe_gt_debugfs_simple_show,
+		.data = xe_gt_sriov_pf_config_print_lmem,
+	},
+};
 /*
  *      /sys/kernel/debug/dri/0/
  *      ├── gt0
 	pfdentry->d_inode->i_private = gt;
 	drm_debugfs_create_files(pf_info, ARRAY_SIZE(pf_info), pfdentry, minor);
+	if (!xe_gt_is_media_type(gt)) {
+		drm_debugfs_create_files(pf_ggtt_info,
+					 ARRAY_SIZE(pf_ggtt_info),
+					 pfdentry, minor);
+		if (IS_DGFX(gt_to_xe(gt)))
+			drm_debugfs_create_files(pf_lmem_info,
+						 ARRAY_SIZE(pf_lmem_info),
+						 pfdentry, minor);
+	}
 	pf_add_policy_attrs(gt, pfdentry);
 	pf_add_config_attrs(gt, pfdentry, PFID);

drivers/gpu/drm/xe/xe_gt_sriov_pf_service.c+0−6

 	XELP_GT_SLICE_ENABLE,		/* _MMIO(0x9138) */
 	XELP_GT_GEOMETRY_DSS_ENABLE,	/* _MMIO(0x913c) */
 	GT_VEBOX_VDBOX_DISABLE,		/* _MMIO(0x9140) */
-	CTC_MODE,			/* _MMIO(0xa26c) */
 	HUC_KERNEL_LOAD_INFO,		/* _MMIO(0xc1dc) */
 };
 	XELP_GT_GEOMETRY_DSS_ENABLE,	/* _MMIO(0x913c) */
 	GT_VEBOX_VDBOX_DISABLE,		/* _MMIO(0x9140) */
 	XEHP_GT_COMPUTE_DSS_ENABLE,	/* _MMIO(0x9144) */
-	CTC_MODE,			/* _MMIO(0xa26c) */
 	HUC_KERNEL_LOAD_INFO,		/* _MMIO(0xc1dc) */
 };
 	GT_VEBOX_VDBOX_DISABLE,		/* _MMIO(0x9140) */
 	XEHP_GT_COMPUTE_DSS_ENABLE,	/* _MMIO(0x9144) */
 	XEHPC_GT_COMPUTE_DSS_ENABLE_EXT,/* _MMIO(0x9148) */
-	CTC_MODE,			/* _MMIO(0xA26C) */
 	HUC_KERNEL_LOAD_INFO,		/* _MMIO(0xc1dc) */
 };
 	GT_VEBOX_VDBOX_DISABLE,		/* _MMIO(0x9140) */
 	XEHP_GT_COMPUTE_DSS_ENABLE,	/* _MMIO(0x9144) */
 	XEHPC_GT_COMPUTE_DSS_ENABLE_EXT,/* _MMIO(0x9148) */
-	CTC_MODE,			/* _MMIO(0xa26c) */
 	HUC_KERNEL_LOAD_INFO,		/* _MMIO(0xc1dc) */
 };
 	XE2_GT_COMPUTE_DSS_2,		/* _MMIO(0x914c) */
 	XE2_GT_GEOMETRY_DSS_1,		/* _MMIO(0x9150) */
 	XE2_GT_GEOMETRY_DSS_2,		/* _MMIO(0x9154) */
-	CTC_MODE,			/* _MMIO(0xa26c) */
 	HUC_KERNEL_LOAD_INFO,		/* _MMIO(0xc1dc) */
 };
 	XE2_GT_COMPUTE_DSS_2,		/* _MMIO(0x914c) */
 	XE2_GT_GEOMETRY_DSS_1,		/* _MMIO(0x9150) */
 	XE2_GT_GEOMETRY_DSS_2,		/* _MMIO(0x9154) */
-	CTC_MODE,			/* _MMIO(0xa26c) */
 	HUC_KERNEL_LOAD_INFO,		/* _MMIO(0xc1dc) */
 };

drivers/gpu/drm/xe/xe_gt_stats.c+1−0

@@ -27,6 +27,7 @@ void xe_gt_stats_incr(struct xe_gt *gt, const enum xe_gt_stats_id id, int incr) · 26 unmodified lines
27	}	27	}
28		28
29	static const char *const stat_description[__XE_GT_STATS_NUM_IDS] = {	29	static const char *const stat_description[__XE_GT_STATS_NUM_IDS] = {
		30	"svm_pagefault_count",
30	"tlb_inval_count",	31	"tlb_inval_count",
31	"vma_pagefault_count",	32	"vma_pagefault_count",
32	"vma_pagefault_kb",	33	"vma_pagefault_kb",

drivers/gpu/drm/xe/xe_gt_stats_types.h+1−0

@@ -7,6 +7,7 @@ · 6 unmodified lines
7	#define _XE_GT_STATS_TYPES_H_	7	#define _XE_GT_STATS_TYPES_H_
8		8
9	enum xe_gt_stats_id {	9	enum xe_gt_stats_id {
		10	XE_GT_STATS_ID_SVM_PAGEFAULT_COUNT,
10	XE_GT_STATS_ID_TLB_INVAL,	11	XE_GT_STATS_ID_TLB_INVAL,
11	XE_GT_STATS_ID_VMA_PAGEFAULT_COUNT,	12	XE_GT_STATS_ID_VMA_PAGEFAULT_COUNT,
12	XE_GT_STATS_ID_VMA_PAGEFAULT_KB,	13	XE_GT_STATS_ID_VMA_PAGEFAULT_KB,

drivers/gpu/drm/xe/xe_guc.c+2−1

@@ -483,7 +483,8 @@ static int guc_g2g_alloc(struct xe_guc *guc) · 482 unmodified lines
483	XE_BO_FLAG_VRAM_IF_DGFX(tile) \|	483	XE_BO_FLAG_VRAM_IF_DGFX(tile) \|
484	XE_BO_FLAG_GGTT \|	484	XE_BO_FLAG_GGTT \|
485	XE_BO_FLAG_GGTT_ALL \|	485	XE_BO_FLAG_GGTT_ALL \|
486	XE_BO_FLAG_GGTT_INVALIDATE);	486	XE_BO_FLAG_GGTT_INVALIDATE \|
		487	XE_BO_FLAG_PINNED_NORESTORE);
487	if (IS_ERR(bo))	488	if (IS_ERR(bo))
488	return PTR_ERR(bo);	489	return PTR_ERR(bo);
489		490

drivers/gpu/drm/xe/xe_guc_ads.c+54−33

@@ -376,6 +376,11 @@ static void guc_waklv_init(struct xe_guc_ads *ads) · 375 unmodified lines
376	GUC_WORKAROUND_KLV_ID_BACK_TO_BACK_RCS_ENGINE_RESET,	376	GUC_WORKAROUND_KLV_ID_BACK_TO_BACK_RCS_ENGINE_RESET,
377	&offset, &remain);	377	&offset, &remain);
378		378
		379	if (GUC_FIRMWARE_VER(&gt->uc.guc) >= MAKE_GUC_VER(70, 44, 0) && XE_WA(gt, 16026508708))
		380	guc_waklv_enable_simple(ads,
		381	GUC_WA_KLV_RESET_BB_STACK_PTR_ON_VF_SWITCH,
		382	&offset, &remain);
		383
379	size = guc_ads_waklv_size(ads) - remain;	384	size = guc_ads_waklv_size(ads) - remain;
380	if (!size)	385	if (!size)
381	return;	386	return;
@@ -414,7 +419,8 @@ int xe_guc_ads_init(struct xe_guc_ads *ads) · 32 unmodified lines
414	bo = xe_managed_bo_create_pin_map(xe, tile, guc_ads_size(ads) + MAX_GOLDEN_LRC_SIZE,	419	bo = xe_managed_bo_create_pin_map(xe, tile, guc_ads_size(ads) + MAX_GOLDEN_LRC_SIZE,
415	XE_BO_FLAG_SYSTEM \|	420	XE_BO_FLAG_SYSTEM \|
416	XE_BO_FLAG_GGTT \|	421	XE_BO_FLAG_GGTT \|
417	XE_BO_FLAG_GGTT_INVALIDATE);	422	XE_BO_FLAG_GGTT_INVALIDATE \|
		423	XE_BO_FLAG_PINNED_NORESTORE);
418	if (IS_ERR(bo))	424	if (IS_ERR(bo))
419	return PTR_ERR(bo);	425	return PTR_ERR(bo);
420		426
@@ -490,24 +496,52 @@ static void fill_engine_enable_masks(struct xe_gt *gt, · 69 unmodified lines
490	engine_enable_mask(gt, XE_ENGINE_CLASS_OTHER));	496	engine_enable_mask(gt, XE_ENGINE_CLASS_OTHER));
491	}	497	}
492		498
493	static void guc_prep_golden_lrc_null(struct xe_guc_ads *ads)	499	/*
		500	* Write the offsets corresponding to the golden LRCs. The actual data is
		501	* populated later by guc_golden_lrc_populate()
		502	*/
		503	static void guc_golden_lrc_init(struct xe_guc_ads *ads)
494	{	504	{
495	struct xe_device *xe = ads_to_xe(ads);	505	struct xe_device *xe = ads_to_xe(ads);
		506	struct xe_gt *gt = ads_to_gt(ads);
496	struct iosys_map info_map = IOSYS_MAP_INIT_OFFSET(ads_to_map(ads),	507	struct iosys_map info_map = IOSYS_MAP_INIT_OFFSET(ads_to_map(ads),
497	offsetof(struct __guc_ads_blob, system_info));	508	offsetof(struct __guc_ads_blob, system_info));
498	u8 guc_class;	509	size_t alloc_size, real_size;
		510	u32 addr_ggtt, offset;
		511	int class;
		512
		513	offset = guc_ads_golden_lrc_offset(ads);
		514	addr_ggtt = xe_bo_ggtt_addr(ads->bo) + offset;
		515
		516	for (class = 0; class < XE_ENGINE_CLASS_MAX; ++class) {
		517	u8 guc_class;
		518
		519	guc_class = xe_engine_class_to_guc_class(class);
499		520
500	for (guc_class = 0; guc_class <= GUC_MAX_ENGINE_CLASSES; ++guc_class) {
501	if (!info_map_read(xe, &info_map,	521	if (!info_map_read(xe, &info_map,
502	engine_enabled_masks[guc_class]))	522	engine_enabled_masks[guc_class]))
503	continue;	523	continue;
504		524
		525	real_size = xe_gt_lrc_size(gt, class);
		526	alloc_size = PAGE_ALIGN(real_size);
		527
		528	/*
		529	* This interface is slightly confusing. We need to pass the
		530	* base address of the full golden context and the size of just
		531	* the engine state, which is the section of the context image
		532	* that starts after the execlists LRC registers. This is
		533	* required to allow the GuC to restore just the engine state
		534	* when a watchdog reset occurs.
		535	* We calculate the engine state size by removing the size of
		536	* what comes before it in the context image (which is identical
		537	* on all engines).
		538	*/
505	ads_blob_write(ads, ads.eng_state_size[guc_class],	539	ads_blob_write(ads, ads.eng_state_size[guc_class],
506	guc_ads_golden_lrc_size(ads) -	540	real_size - xe_lrc_skip_size(xe));
507	xe_lrc_skip_size(xe));
508	ads_blob_write(ads, ads.golden_context_lrca[guc_class],	541	ads_blob_write(ads, ads.golden_context_lrca[guc_class],
509	xe_bo_ggtt_addr(ads->bo) +	542	addr_ggtt);
510	guc_ads_golden_lrc_offset(ads));	543
		544	addr_ggtt += alloc_size;
511	}	545	}
512	}	546	}
513		547
@@ -682,8 +716,8 @@ static int guc_capture_prep_lists(struct xe_guc_ads *ads) · 168 unmodified lines
682	}	716	}
683		717
684	if (ads->capture_size != PAGE_ALIGN(total_size))	718	if (ads->capture_size != PAGE_ALIGN(total_size))
685	xe_gt_dbg(gt, "ADS capture alloc size changed from %d to %d\n",	719	xe_gt_dbg(gt, "Updated ADS capture size %d (was %d)\n",
686	ads->capture_size, PAGE_ALIGN(total_size));	720	PAGE_ALIGN(total_size), ads->capture_size);
687	return PAGE_ALIGN(total_size);	721	return PAGE_ALIGN(total_size);
688	}	722	}
689		723
@@ -857,7 +891,7 @@ void xe_guc_ads_populate_minimal(struct xe_guc_ads *ads) · 167 unmodified lines
857		891
858	xe_map_memset(ads_to_xe(ads), ads_to_map(ads), 0, 0, ads->bo->size);	892	xe_map_memset(ads_to_xe(ads), ads_to_map(ads), 0, 0, ads->bo->size);
859	guc_policies_init(ads);	893	guc_policies_init(ads);
860	guc_prep_golden_lrc_null(ads);	894	guc_golden_lrc_init(ads);
861	guc_mapping_table_init_invalid(gt, &info_map);	895	guc_mapping_table_init_invalid(gt, &info_map);
862	guc_doorbell_init(ads);	896	guc_doorbell_init(ads);
863		897
@@ -883,7 +917,7 @@ void xe_guc_ads_populate(struct xe_guc_ads *ads) · 19 unmodified lines
883	guc_policies_init(ads);	917	guc_policies_init(ads);
884	fill_engine_enable_masks(gt, &info_map);	918	fill_engine_enable_masks(gt, &info_map);
885	guc_mmio_reg_state_init(ads);	919	guc_mmio_reg_state_init(ads);
886	guc_prep_golden_lrc_null(ads);	920	guc_golden_lrc_init(ads);
887	guc_mapping_table_init(gt, &info_map);	921	guc_mapping_table_init(gt, &info_map);
888	guc_capture_prep_lists(ads);	922	guc_capture_prep_lists(ads);
889	guc_doorbell_init(ads);	923	guc_doorbell_init(ads);
@@ -903,18 +937,22 @@ void xe_guc_ads_populate(struct xe_guc_ads *ads) · 13 unmodified lines
903	guc_ads_private_data_offset(ads));	937	guc_ads_private_data_offset(ads));
904	}	938	}
905		939
906	static void guc_populate_golden_lrc(struct xe_guc_ads *ads)	940	/*
		941	* After the golden LRC's are recorded for each engine class by the first
		942	* submission, copy them to the ADS, as initialized earlier by
		943	* guc_golden_lrc_init().
		944	*/
		945	static void guc_golden_lrc_populate(struct xe_guc_ads *ads)
907	{	946	{
908	struct xe_device *xe = ads_to_xe(ads);	947	struct xe_device *xe = ads_to_xe(ads);
909	struct xe_gt *gt = ads_to_gt(ads);	948	struct xe_gt *gt = ads_to_gt(ads);
910	struct iosys_map info_map = IOSYS_MAP_INIT_OFFSET(ads_to_map(ads),	949	struct iosys_map info_map = IOSYS_MAP_INIT_OFFSET(ads_to_map(ads),
911	offsetof(struct __guc_ads_blob, system_info));	950	offsetof(struct __guc_ads_blob, system_info));
912	size_t total_size = 0, alloc_size, real_size;	951	size_t total_size = 0, alloc_size, real_size;
913	u32 addr_ggtt, offset;	952	u32 offset;
914	int class;	953	int class;
915		954
916	offset = guc_ads_golden_lrc_offset(ads);	955	offset = guc_ads_golden_lrc_offset(ads);
917	addr_ggtt = xe_bo_ggtt_addr(ads->bo) + offset;
918		956
919	for (class = 0; class < XE_ENGINE_CLASS_MAX; ++class) {	957	for (class = 0; class < XE_ENGINE_CLASS_MAX; ++class) {
920	u8 guc_class;	958	u8 guc_class;
@@ -931,26 +969,9 @@ static void guc_populate_golden_lrc(struct xe_guc_ads *ads) · 10 unmodified lines
931	alloc_size = PAGE_ALIGN(real_size);	969	alloc_size = PAGE_ALIGN(real_size);
932	total_size += alloc_size;	970	total_size += alloc_size;
933		971
934	/*
935	* This interface is slightly confusing. We need to pass the
936	* base address of the full golden context and the size of just
937	* the engine state, which is the section of the context image
938	* that starts after the execlists LRC registers. This is
939	* required to allow the GuC to restore just the engine state
940	* when a watchdog reset occurs.
941	* We calculate the engine state size by removing the size of
942	* what comes before it in the context image (which is identical
943	* on all engines).
944	*/
945	ads_blob_write(ads, ads.eng_state_size[guc_class],
946	real_size - xe_lrc_skip_size(xe));
947	ads_blob_write(ads, ads.golden_context_lrca[guc_class],
948	addr_ggtt);
949
950	xe_map_memcpy_to(xe, ads_to_map(ads), offset,	972	xe_map_memcpy_to(xe, ads_to_map(ads), offset,
951	gt->default_lrc[class], real_size);	973	gt->default_lrc[class], real_size);
952		974
953	addr_ggtt += alloc_size;
954	offset += alloc_size;	975	offset += alloc_size;
955	}	976	}
956		977
@@ -959,7 +980,7 @@ static void guc_populate_golden_lrc(struct xe_guc_ads *ads) · 2 unmodified lines
959		980
960	void xe_guc_ads_populate_post_load(struct xe_guc_ads *ads)	981	void xe_guc_ads_populate_post_load(struct xe_guc_ads *ads)
961	{	982	{
962	guc_populate_golden_lrc(ads);	983	guc_golden_lrc_populate(ads);
963	}	984	}
964		985
965	static int guc_ads_action_update_policies(struct xe_guc_ads *ads, u32 policy_offset)	986	static int guc_ads_action_update_policies(struct xe_guc_ads *ads, u32 policy_offset)

drivers/gpu/drm/xe/xe_guc_ct.c+3−2

 	bo = xe_managed_bo_create_pin_map(xe, tile, guc_ct_size(),
 					  XE_BO_FLAG_SYSTEM |
 					  XE_BO_FLAG_GGTT |
-					  XE_BO_FLAG_GGTT_INVALIDATE);
+					  XE_BO_FLAG_GGTT_INVALIDATE |
+					  XE_BO_FLAG_PINNED_NORESTORE);
 	if (IS_ERR(bo))
 		return PTR_ERR(bo);
 		return;
 	}
-	drm_printf(&lp, "CTB is dead - reason=0x%X\n", dead->reason);
 	/* Can't generate a genuine core dump at this point, so just do the good bits */
 	drm_puts(&lp, "**** Xe Device Coredump ****\n");
+	drm_printf(&lp, "Reason: CTB is dead - 0x%X\n", dead->reason);
 	xe_device_snapshot_print(xe, &lp);
 	drm_printf(&lp, "**** GT #%d ****\n", gt->info.id);

drivers/gpu/drm/xe/xe_guc_debugfs.c+83−65

@@ -17,101 +17,119 @@ · 16 unmodified lines
17	#include "xe_macros.h"	17	#include "xe_macros.h"
18	#include "xe_pm.h"	18	#include "xe_pm.h"
19		19
20	static struct xe_guc node_to_guc(struct drm_info_node node)	20	/*
21	{	21	* guc_debugfs_show - A show callback for struct drm_info_list
22	return node->info_ent->data;	22	* @m: the &seq_file
23	}	23	* @data: data used by the drm debugfs helpers
24		24	*
25	static int guc_info(struct seq_file m, void data)	25	* This callback can be used in struct drm_info_list to describe debugfs
		26	* files that are &xe_guc specific in similar way how we handle &xe_gt
		27	* specific files using &xe_gt_debugfs_simple_show.
		28	*
		29	* It is assumed that those debugfs files will be created on directory entry
		30	* which grandparent struct dentry d_inode->i_private points to &xe_gt.
		31	*
		32	* /sys/kernel/debug/dri/0/
		33	* ├── gt0 # dent->d_parent->d_parent (d_inode->i_private == gt)
		34	* │ ├── uc # dent->d_parent
		35	* │ │ ├── guc_info # dent
		36	* │ │ ├── guc_...
		37	*
		38	* This function assumes that &m->private will be set to the &struct
		39	* drm_info_node corresponding to the instance of the info on a given &struct
		40	* drm_minor (see struct drm_info_list.show for details).
		41	*
		42	* This function also assumes that struct drm_info_list.data will point to the
		43	* function code that will actually print a file content::
		44	*
		45	* int (print)(struct xe_guc , struct drm_printer *)
		46	*
		47	* Example::
		48	*
		49	* int foo(struct xe_guc guc, struct drm_printer p)
		50	* {
		51	* drm_printf(p, "enabled %d\n", guc->submission_state.enabled);
		52	* return 0;
		53	* }
		54	*
		55	* static const struct drm_info_list bar[] = {
		56	* { name = "foo", .show = guc_debugfs_show, .data = foo },
		57	* };
		58	*
		59	* parent = debugfs_create_dir("uc", gtdir);
		60	* drm_debugfs_create_files(bar, ARRAY_SIZE(bar), parent, minor);
		61	*
		62	* Return: 0 on success or a negative error code on failure.
		63	*/
		64	static int guc_debugfs_show(struct seq_file m, void data)
26	{	65	{
27	struct xe_guc *guc = node_to_guc(m->private);
28	struct xe_device *xe = guc_to_xe(guc);
29	struct drm_printer p = drm_seq_file_printer(m);	66	struct drm_printer p = drm_seq_file_printer(m);
		67	struct drm_info_node *node = m->private;
		68	struct dentry *parent = node->dent->d_parent;
		69	struct dentry *grandparent = parent->d_parent;
		70	struct xe_gt *gt = grandparent->d_inode->i_private;
		71	struct xe_device *xe = gt_to_xe(gt);
		72	int (print)(struct xe_guc , struct drm_printer *) = node->info_ent->data;
		73	int ret;
30		74
31	xe_pm_runtime_get(xe);	75	xe_pm_runtime_get(xe);
32	xe_guc_print_info(guc, &p);	76	ret = print(&gt->uc.guc, &p);
33	xe_pm_runtime_put(xe);	77	xe_pm_runtime_put(xe);
34		78
35	return 0;	79	return ret;
36	}	80	}
37		81
38	static int guc_log(struct seq_file m, void data)	82	static int guc_log(struct xe_guc guc, struct drm_printer p)
39	{	83	{
40	struct xe_guc *guc = node_to_guc(m->private);	84	xe_guc_log_print(&guc->log, p);
41	struct xe_device *xe = guc_to_xe(guc);
42	struct drm_printer p = drm_seq_file_printer(m);
43
44	xe_pm_runtime_get(xe);
45	xe_guc_log_print(&guc->log, &p);
46	xe_pm_runtime_put(xe);
47
48	return 0;	85	return 0;
49	}	86	}
50		87
51	static int guc_log_dmesg(struct seq_file m, void data)	88	static int guc_log_dmesg(struct xe_guc guc, struct drm_printer p)
52	{	89	{
53	struct xe_guc *guc = node_to_guc(m->private);
54	struct xe_device *xe = guc_to_xe(guc);
55
56	xe_pm_runtime_get(xe);
57	xe_guc_log_print_dmesg(&guc->log);	90	xe_guc_log_print_dmesg(&guc->log);
58	xe_pm_runtime_put(xe);
59
60	return 0;	91	return 0;
61	}	92	}
62		93
63	static int guc_ctb(struct seq_file m, void data)	94	static int guc_ctb(struct xe_guc guc, struct drm_printer p)
64	{	95	{
65	struct xe_guc *guc = node_to_guc(m->private);	96	xe_guc_ct_print(&guc->ct, p, true);
66	struct xe_device *xe = guc_to_xe(guc);
67	struct drm_printer p = drm_seq_file_printer(m);
68
69	xe_pm_runtime_get(xe);
70	xe_guc_ct_print(&guc->ct, &p, true);
71	xe_pm_runtime_put(xe);
72
73	return 0;	97	return 0;
74	}	98	}
75		99
76	static int guc_pc(struct seq_file m, void data)	100	static int guc_pc(struct xe_guc guc, struct drm_printer p)
77	{	101	{
78	struct xe_guc *guc = node_to_guc(m->private);	102	xe_guc_pc_print(&guc->pc, p);
79	struct xe_device *xe = guc_to_xe(guc);
80	struct drm_printer p = drm_seq_file_printer(m);
81
82	xe_pm_runtime_get(xe);
83	xe_guc_pc_print(&guc->pc, &p);
84	xe_pm_runtime_put(xe);
85
86	return 0;	103	return 0;
87	}	104	}
88		105
89	static const struct drm_info_list debugfs_list[] = {	106	/*
90	{"guc_info", guc_info, 0},	107	* only for GuC debugfs files which can be safely used on the VF as well:
91	{"guc_log", guc_log, 0},	108	* - without access to the GuC privileged registers
92	{"guc_log_dmesg", guc_log_dmesg, 0},	109	* - without access to the PF specific GuC objects
93	{"guc_ctb", guc_ctb, 0},	110	*/
94	{"guc_pc", guc_pc, 0},	111	static const struct drm_info_list vf_safe_debugfs_list[] = {
		112	{ "guc_info", .show = guc_debugfs_show, .data = xe_guc_print_info },
		113	{ "guc_ctb", .show = guc_debugfs_show, .data = guc_ctb },
		114	};
		115
		116	/* everything else should be added here */
		117	static const struct drm_info_list pf_only_debugfs_list[] = {
		118	{ "guc_log", .show = guc_debugfs_show, .data = guc_log },
		119	{ "guc_log_dmesg", .show = guc_debugfs_show, .data = guc_log_dmesg },
		120	{ "guc_pc", .show = guc_debugfs_show, .data = guc_pc },
95	};	121	};
96		122
97	void xe_guc_debugfs_register(struct xe_guc guc, struct dentry parent)	123	void xe_guc_debugfs_register(struct xe_guc guc, struct dentry parent)
98	{	124	{
99	struct drm_minor *minor = guc_to_xe(guc)->drm.primary;	125	struct drm_minor *minor = guc_to_xe(guc)->drm.primary;
100	struct drm_info_list *local;
101	int i;
102		126
103	#define DEBUGFS_SIZE (ARRAY_SIZE(debugfs_list) * sizeof(struct drm_info_list))	127	drm_debugfs_create_files(vf_safe_debugfs_list,
104	local = drmm_kmalloc(&guc_to_xe(guc)->drm, DEBUGFS_SIZE, GFP_KERNEL);	128	ARRAY_SIZE(vf_safe_debugfs_list),
105	if (!local)
106	return;
107
108	memcpy(local, debugfs_list, DEBUGFS_SIZE);
109	#undef DEBUGFS_SIZE
110
111	for (i = 0; i < ARRAY_SIZE(debugfs_list); ++i)
112	local[i].data = guc;
113
114	drm_debugfs_create_files(local,
115	ARRAY_SIZE(debugfs_list),
116	parent, minor);	129	parent, minor);
		130
		131	if (!IS_SRIOV_VF(guc_to_xe(guc)))
		132	drm_debugfs_create_files(pf_only_debugfs_list,
		133	ARRAY_SIZE(pf_only_debugfs_list),
		134	parent, minor);
117	}	135	}

drivers/gpu/drm/xe/xe_guc_engine_activity.c+172−28

 #include "xe_hw_engine.h"
 #include "xe_map.h"
 #include "xe_mmio.h"
+#include "xe_sriov_pf_helpers.h"
 #include "xe_trace_guc.h"
 #define TOTAL_QUANTA 0x8000
-static struct iosys_map engine_activity_map(struct xe_guc *guc, struct xe_hw_engine *hwe)
+static struct iosys_map engine_activity_map(struct xe_guc *guc, struct xe_hw_engine *hwe,
+					    unsigned int index)
 {
 	struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
-	struct engine_activity_buffer *buffer = &engine_activity->device_buffer;
+	struct engine_activity_buffer *buffer;
 	u16 guc_class = xe_engine_class_to_guc_class(hwe->class);
 	size_t offset;
-	offset = offsetof(struct guc_engine_activity_data,
+	if (engine_activity->num_functions) {
+		buffer = &engine_activity->function_buffer;
+		offset = sizeof(struct guc_engine_activity_data) * index;
+	} else {
+		buffer = &engine_activity->device_buffer;
+		offset = 0;
+	}
+	offset += offsetof(struct guc_engine_activity_data,
 			  engine_activity[guc_class][hwe->logical_instance]);
 	return IOSYS_MAP_INIT_OFFSET(&buffer->activity_bo->vmap, offset);
 }
-static struct iosys_map engine_metadata_map(struct xe_guc *guc)
+static struct iosys_map engine_metadata_map(struct xe_guc *guc,
+					    unsigned int index)
 {
 	struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
-	struct engine_activity_buffer *buffer = &engine_activity->device_buffer;
+	struct engine_activity_buffer *buffer;
+	size_t offset;
-	return buffer->metadata_bo->vmap;
+	if (engine_activity->num_functions) {
+		buffer = &engine_activity->function_buffer;
+		offset = sizeof(struct guc_engine_activity_metadata) * index;
+	} else {
+		buffer = &engine_activity->device_buffer;
+		offset = 0;
+	}
+	return IOSYS_MAP_INIT_OFFSET(&buffer->metadata_bo->vmap, offset);
 }
 static int allocate_engine_activity_group(struct xe_guc *guc)
 {
 	struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
 	struct xe_device *xe = guc_to_xe(guc);
-	u32 num_activity_group = 1; /* Will be modified for VF */
+	u32 num_activity_group;
+	/*
+	 * An additional activity group is allocated for PF
+	 */
+	num_activity_group = IS_SRIOV_PF(xe) ? xe_sriov_pf_get_totalvfs(xe) + 1 : 1;
 	engine_activity->eag  = drmm_kcalloc(&xe->drm, num_activity_group,
 					     sizeof(struct engine_activity_group), GFP_KERNEL);
 }
 static int allocate_engine_activity_buffers(struct xe_guc *guc,
-					    struct engine_activity_buffer *buffer)
+					    struct engine_activity_buffer *buffer,
+					    int count)
 {
-	u32 metadata_size = sizeof(struct guc_engine_activity_metadata);
+	u32 metadata_size = sizeof(struct guc_engine_activity_metadata) * count;
-	u32 size = sizeof(struct guc_engine_activity_data);
+	u32 size = sizeof(struct guc_engine_activity_data) * count;
 	struct xe_gt *gt = guc_to_gt(guc);
 	struct xe_tile *tile = gt_to_tile(gt);
 	struct xe_bo *bo, *metadata_bo;
 	return true;
 }
-static struct engine_activity *hw_engine_to_engine_activity(struct xe_hw_engine *hwe)
+static struct engine_activity *hw_engine_to_engine_activity(struct xe_hw_engine *hwe,
+							    unsigned int index)
 {
 	struct xe_guc *guc = &hwe->gt->uc.guc;
-	struct engine_activity_group *eag = &guc->engine_activity.eag[0];
+	struct engine_activity_group *eag = &guc->engine_activity.eag[index];
 	u16 guc_class = xe_engine_class_to_guc_class(hwe->class);
 	return &eag->engine[guc_class][hwe->logical_instance];
 #define read_metadata_record(xe_, map_, field_) \
 	xe_map_rd_field(xe_, map_, 0, struct guc_engine_activity_metadata, field_)
-static u64 get_engine_active_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe)
+static u64 get_engine_active_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe,
+				   unsigned int index)
 {
-	struct engine_activity *ea = hw_engine_to_engine_activity(hwe);
+	struct engine_activity *ea = hw_engine_to_engine_activity(hwe, index);
 	struct guc_engine_activity *cached_activity = &ea->activity;
 	struct guc_engine_activity_metadata *cached_metadata = &ea->metadata;
 	struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
 	u64 active_ticks, gpm_ts;
 	u16 change_num;
-	activity_map = engine_activity_map(guc, hwe);
+	activity_map = engine_activity_map(guc, hwe, index);
-	metadata_map = engine_metadata_map(guc);
+	metadata_map = engine_metadata_map(guc, index);
 	global_change_num = read_metadata_record(xe, &metadata_map, global_change_num);
 	/* GuC has not initialized activity data yet, return 0 */
 	return ea->total + ea->active;
 }
-static u64 get_engine_total_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe)
+static u64 get_engine_total_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe, unsigned int index)
 {
-	struct engine_activity *ea = hw_engine_to_engine_activity(hwe);
+	struct engine_activity *ea = hw_engine_to_engine_activity(hwe, index);
 	struct guc_engine_activity_metadata *cached_metadata = &ea->metadata;
 	struct guc_engine_activity *cached_activity = &ea->activity;
 	struct iosys_map activity_map, metadata_map;
 	u64 numerator;
 	u16 quanta_ratio;
-	activity_map = engine_activity_map(guc, hwe);
+	activity_map = engine_activity_map(guc, hwe, index);
-	metadata_map = engine_metadata_map(guc);
+	metadata_map = engine_metadata_map(guc, index);
 	if (!cached_metadata->guc_tsc_frequency_hz)
 		cached_metadata->guc_tsc_frequency_hz = read_metadata_record(xe, &metadata_map,
 	return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action));
 }
-static void engine_activity_set_cpu_ts(struct xe_guc *guc)
+static int enable_function_engine_activity_stats(struct xe_guc *guc, bool enable)
 {
 	struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
-	struct engine_activity_group *eag = &engine_activity->eag[0];
+	u32 metadata_ggtt_addr = 0, ggtt_addr = 0, num_functions = 0;
+	struct engine_activity_buffer *buffer = &engine_activity->function_buffer;
+	u32 action[6];
+	int len = 0;
+	if (enable) {
+		metadata_ggtt_addr = xe_bo_ggtt_addr(buffer->metadata_bo);
+		ggtt_addr = xe_bo_ggtt_addr(buffer->activity_bo);
+		num_functions = engine_activity->num_functions;
+	}
+	action[len++] = XE_GUC_ACTION_SET_FUNCTION_ENGINE_ACTIVITY_BUFFER;
+	action[len++] = num_functions;
+	action[len++] = metadata_ggtt_addr;
+	action[len++] = 0;
+	action[len++] = ggtt_addr;
+	action[len++] = 0;
+	/* Blocking here to ensure the buffers are ready before reading them */
+	return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action));
+}
+static void engine_activity_set_cpu_ts(struct xe_guc *guc, unsigned int index)
+{
+	struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
+	struct engine_activity_group *eag = &engine_activity->eag[index];
 	int i, j;
 	for (i = 0; i < GUC_MAX_ENGINE_CLASSES; i++)
 	return 3 - REG_FIELD_GET(RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, reg);
 }
+static bool is_function_valid(struct xe_guc *guc, unsigned int fn_id)
+{
+	struct xe_device *xe = guc_to_xe(guc);
+	struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
+	if (!IS_SRIOV_PF(xe) && fn_id)
+		return false;
+	if (engine_activity->num_functions && fn_id >= engine_activity->num_functions)
+		return false;
+	return true;
+}
+static int engine_activity_disable_function_stats(struct xe_guc *guc)
+{
+	struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
+	struct engine_activity_buffer *buffer = &engine_activity->function_buffer;
+	int ret;
+	if (!engine_activity->num_functions)
+		return 0;
+	ret = enable_function_engine_activity_stats(guc, false);
+	if (ret)
+		return ret;
+	free_engine_activity_buffers(buffer);
+	engine_activity->num_functions = 0;
+	return 0;
+}
+static int engine_activity_enable_function_stats(struct xe_guc *guc, int num_vfs)
+{
+	struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
+	struct engine_activity_buffer *buffer = &engine_activity->function_buffer;
+	int ret, i;
+	if (!num_vfs)
+		return 0;
+	/* This includes 1 PF and num_vfs */
+	engine_activity->num_functions = num_vfs + 1;
+	ret = allocate_engine_activity_buffers(guc, buffer, engine_activity->num_functions);
+	if (ret)
+		return ret;
+	ret = enable_function_engine_activity_stats(guc, true);
+	if (ret) {
+		free_engine_activity_buffers(buffer);
+		engine_activity->num_functions = 0;
+		return ret;
+	}
+	for (i = 0; i < engine_activity->num_functions; i++)
+		engine_activity_set_cpu_ts(guc, i + 1);
+	return 0;
+}
 /**
  * xe_guc_engine_activity_active_ticks - Get engine active ticks
  * @guc: The GuC object
  * @hwe: The hw_engine object
+ * @fn_id: function id to report on
  *
  * Return: accumulated ticks @hwe was active since engine activity stats were enabled.
  */
-u64 xe_guc_engine_activity_active_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe)
+u64 xe_guc_engine_activity_active_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe,
+					unsigned int fn_id)
 {
 	if (!xe_guc_engine_activity_supported(guc))
 		return 0;
-	return get_engine_active_ticks(guc, hwe);
+	if (!is_function_valid(guc, fn_id))
+		return 0;
+	return get_engine_active_ticks(guc, hwe, fn_id);
 }
 /**
  * xe_guc_engine_activity_total_ticks - Get engine total ticks
  * @guc: The GuC object
  * @hwe: The hw_engine object
+ * @fn_id: function id to report on
  *
  * Return: accumulated quanta of ticks allocated for the engine
  */
-u64 xe_guc_engine_activity_total_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe)
+u64 xe_guc_engine_activity_total_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe,
+				       unsigned int fn_id)
 {
 	if (!xe_guc_engine_activity_supported(guc))
 		return 0;
-	return get_engine_total_ticks(guc, hwe);
+	if (!is_function_valid(guc, fn_id))
+		return 0;
+	return get_engine_total_ticks(guc, hwe, fn_id);
 }
 /**
 	return engine_activity->supported;
 }
+/**
+ * xe_guc_engine_activity_function_stats - Enable/Disable per-function engine activity stats
+ * @guc: The GuC object
+ * @num_vfs: number of vfs
+ * @enable: true to enable, false otherwise
+ *
+ * Return: 0 on success, negative error code otherwise
+ */
+int xe_guc_engine_activity_function_stats(struct xe_guc *guc, int num_vfs, bool enable)
+{
+	if (!xe_guc_engine_activity_supported(guc))
+		return 0;
+	if (enable)
+		return engine_activity_enable_function_stats(guc, num_vfs);
+	return engine_activity_disable_function_stats(guc);
+}
 /**
  * xe_guc_engine_activity_enable_stats - Enable engine activity stats
  * @guc: The GuC object
 	if (ret)
 		xe_gt_err(guc_to_gt(guc), "failed to enable activity stats%d\n", ret);
 	else
-		engine_activity_set_cpu_ts(guc);
+		engine_activity_set_cpu_ts(guc, 0);
 }
 static void engine_activity_fini(void *arg)
 		return ret;
 	}
-	ret = allocate_engine_activity_buffers(guc, &engine_activity->device_buffer);
+	ret = allocate_engine_activity_buffers(guc, &engine_activity->device_buffer, 1);
 	if (ret) {
 		xe_gt_err(gt, "failed to allocate engine activity buffers (%pe)\n", ERR_PTR(ret));
 		return ret;

drivers/gpu/drm/xe/xe_guc_engine_activity.h+5−2

 int xe_guc_engine_activity_init(struct xe_guc *guc);
 bool xe_guc_engine_activity_supported(struct xe_guc *guc);
 void xe_guc_engine_activity_enable_stats(struct xe_guc *guc);
-u64 xe_guc_engine_activity_active_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe);
+int xe_guc_engine_activity_function_stats(struct xe_guc *guc, int num_vfs, bool enable);
-u64 xe_guc_engine_activity_total_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe);
+u64 xe_guc_engine_activity_active_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe,
+					unsigned int fn_id);
+u64 xe_guc_engine_activity_total_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe,
+				       unsigned int fn_id);
 #endif

drivers/gpu/drm/xe/xe_guc_engine_activity_types.h+11−1

 	/** @num_activity_group: number of activity groups */
 	u32 num_activity_group;
+	/** @num_functions: number of functions */
+	u32 num_functions;
 	/** @supported: indicates support for engine activity stats */
 	bool supported;
-	/** @eag: holds the device level engine activity data */
+	/**
+	 * @eag: holds the device level engine activity data in native mode.
+	 * In SRIOV mode, points to an array with entries which holds the engine
+	 * activity data for PF and VF's
+	 */
 	struct engine_activity_group *eag;
 	/** @device_buffer: buffer object for global engine activity */
 	struct engine_activity_buffer device_buffer;
+	/** @function_buffer: buffer object for per-function engine activity */
+	struct engine_activity_buffer function_buffer;
 };
 #endif

drivers/gpu/drm/xe/xe_guc_log.c+2−1

@@ -260,7 +260,8 @@ int xe_guc_log_init(struct xe_guc_log *log) · 259 unmodified lines
260	bo = xe_managed_bo_create_pin_map(xe, tile, guc_log_size(),	260	bo = xe_managed_bo_create_pin_map(xe, tile, guc_log_size(),
261	XE_BO_FLAG_SYSTEM \|	261	XE_BO_FLAG_SYSTEM \|
262	XE_BO_FLAG_GGTT \|	262	XE_BO_FLAG_GGTT \|
263	XE_BO_FLAG_GGTT_INVALIDATE);	263	XE_BO_FLAG_GGTT_INVALIDATE \|
		264	XE_BO_FLAG_PINNED_NORESTORE);
264	if (IS_ERR(bo))	265	if (IS_ERR(bo))
265	return PTR_ERR(bo);	266	return PTR_ERR(bo);
266		267

drivers/gpu/drm/xe/xe_guc_pc.c+17−1

@@ -461,6 +461,21 @@ static u32 get_cur_freq(struct xe_gt *gt) · 460 unmodified lines
461	return decode_freq(freq);	461	return decode_freq(freq);
462	}	462	}
463		463
		464	/**
		465	* xe_guc_pc_get_cur_freq_fw - With fw held, get requested frequency
		466	* @pc: The GuC PC
		467	*
		468	* Returns: the requested frequency for that GT instance
		469	*/
		470	u32 xe_guc_pc_get_cur_freq_fw(struct xe_guc_pc *pc)
		471	{
		472	struct xe_gt *gt = pc_to_gt(pc);
		473
		474	xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT);
		475
		476	return get_cur_freq(gt);
		477	}
		478
464	/**	479	/**
465	* xe_guc_pc_get_cur_freq - Get Current requested frequency	480	* xe_guc_pc_get_cur_freq - Get Current requested frequency
466	* @pc: The GuC PC	481	* @pc: The GuC PC
@@ -1170,7 +1185,8 @@ int xe_guc_pc_init(struct xe_guc_pc *pc) · 703 unmodified lines
1170	bo = xe_managed_bo_create_pin_map(xe, tile, size,	1185	bo = xe_managed_bo_create_pin_map(xe, tile, size,
1171	XE_BO_FLAG_VRAM_IF_DGFX(tile) \|	1186	XE_BO_FLAG_VRAM_IF_DGFX(tile) \|
1172	XE_BO_FLAG_GGTT \|	1187	XE_BO_FLAG_GGTT \|
1173	XE_BO_FLAG_GGTT_INVALIDATE);	1188	XE_BO_FLAG_GGTT_INVALIDATE \|
		1189	XE_BO_FLAG_PINNED_NORESTORE);
1174	if (IS_ERR(bo))	1190	if (IS_ERR(bo))
1175	return PTR_ERR(bo);	1191	return PTR_ERR(bo);
1176		1192

drivers/gpu/drm/xe/xe_guc_pc.h+1−0

@@ -22,6 +22,7 @@ void xe_guc_pc_print(struct xe_guc_pc pc, struct drm_printer p); · 21 unmodified lines
22		22
23	u32 xe_guc_pc_get_act_freq(struct xe_guc_pc *pc);	23	u32 xe_guc_pc_get_act_freq(struct xe_guc_pc *pc);
24	int xe_guc_pc_get_cur_freq(struct xe_guc_pc pc, u32 freq);	24	int xe_guc_pc_get_cur_freq(struct xe_guc_pc pc, u32 freq);
		25	u32 xe_guc_pc_get_cur_freq_fw(struct xe_guc_pc *pc);
25	u32 xe_guc_pc_get_rp0_freq(struct xe_guc_pc *pc);	26	u32 xe_guc_pc_get_rp0_freq(struct xe_guc_pc *pc);
26	u32 xe_guc_pc_get_rpa_freq(struct xe_guc_pc *pc);	27	u32 xe_guc_pc_get_rpa_freq(struct xe_guc_pc *pc);
27	u32 xe_guc_pc_get_rpe_freq(struct xe_guc_pc *pc);	28	u32 xe_guc_pc_get_rpe_freq(struct xe_guc_pc *pc);

drivers/gpu/drm/xe/xe_guc_submit.c+9−0

 	primelockdep(guc);
+	guc->submission_state.initialized = true;
 	return drmm_add_action_or_reset(&xe->drm, guc_submit_fini, guc);
 }
 	xe_gt_assert(guc_to_gt(guc), guc_to_xe(guc)->wedged.mode);
+	/*
+	 * If device is being wedged even before submission_state is
+	 * initialized, there's nothing to do here.
+	 */
+	if (!guc->submission_state.initialized)
+		return;
 	err = devm_add_action_or_reset(guc_to_xe(guc)->drm.dev,
 				       guc_submit_wedged_fini, guc);
 	if (err) {

drivers/gpu/drm/xe/xe_guc_types.h+5−0

 		struct mutex lock;
 		/** @submission_state.enabled: submission is enabled */
 		bool enabled;
+		/**
+		 * @submission_state.initialized: mark when submission state is
+		 * even initialized - before that not even the lock is valid
+		 */
+		bool initialized;
 		/** @submission_state.fini_wq: submit fini wait queue */
 		wait_queue_head_t fini_wq;
 	} submission_state;

drivers/gpu/drm/xe/xe_hmm.c+0−24

@@ -19,29 +19,6 @@ static u64 xe_npages_in_range(unsigned long start, unsigned long end) · 18 unmodified lines
19	return (end - start) >> PAGE_SHIFT;	19	return (end - start) >> PAGE_SHIFT;
20	}	20	}
21		21
22	/**
23	* xe_mark_range_accessed() - mark a range is accessed, so core mm
24	* have such information for memory eviction or write back to
25	* hard disk
26	* @range: the range to mark
27	* @write: if write to this range, we mark pages in this range
28	* as dirty
29	*/
30	static void xe_mark_range_accessed(struct hmm_range *range, bool write)
31	{
32	struct page *page;
33	u64 i, npages;
34
35	npages = xe_npages_in_range(range->start, range->end);
36	for (i = 0; i < npages; i++) {
37	page = hmm_pfn_to_page(range->hmm_pfns[i]);
38	if (write)
39	set_page_dirty_lock(page);
40
41	mark_page_accessed(page);
42	}
43	}
44
45	static int xe_alloc_sg(struct xe_device xe, struct sg_table st,	22	static int xe_alloc_sg(struct xe_device xe, struct sg_table st,
46	struct hmm_range range, struct rw_semaphore notifier_sem)	23	struct hmm_range range, struct rw_semaphore notifier_sem)
47	{	24	{
@@ -331,7 +308,6 @@ int xe_hmm_userptr_populate_range(struct xe_userptr_vma *uvma, · 283 unmodified lines
331	if (ret)	308	if (ret)
332	goto out_unlock;	309	goto out_unlock;
333		310
334	xe_mark_range_accessed(&hmm_range, write);
335	userptr->sg = &userptr->sgt;	311	userptr->sg = &userptr->sgt;
336	xe_hmm_userptr_set_mapped(uvma);	312	xe_hmm_userptr_set_mapped(uvma);
337	userptr->notifier_seq = hmm_range.notifier_seq;	313	userptr->notifier_seq = hmm_range.notifier_seq;

drivers/gpu/drm/xe/xe_hw_engine_class_sysfs.c+1−0

@@ -605,6 +605,7 @@ err_object: · 604 unmodified lines
605	kobject_put(kobj);	605	kobject_put(kobj);
606	return err;	606	return err;
607	}	607	}
		608	ALLOW_ERROR_INJECTION(xe_add_hw_engine_class_defaults, ERRNO); /* See xe_pci_probe() */
608		609
609		610
610	static void hw_engine_class_sysfs_fini(void *arg)	611	static void hw_engine_class_sysfs_fini(void *arg)

drivers/gpu/drm/xe/xe_hwmon.c+124−1

@@ -5,6 +5,7 @@ · 4 unmodified lines
5		5
6	#include <linux/hwmon-sysfs.h>	6	#include <linux/hwmon-sysfs.h>
7	#include <linux/hwmon.h>	7	#include <linux/hwmon.h>
		8	#include <linux/jiffies.h>
8	#include <linux/types.h>	9	#include <linux/types.h>
9	#include <linux/units.h>	10	#include <linux/units.h>
10		11
@@ -27,6 +28,7 @@ enum xe_hwmon_reg { · 16 unmodified lines
27	REG_PKG_POWER_SKU_UNIT,	28	REG_PKG_POWER_SKU_UNIT,
28	REG_GT_PERF_STATUS,	29	REG_GT_PERF_STATUS,
29	REG_PKG_ENERGY_STATUS,	30	REG_PKG_ENERGY_STATUS,
		31	REG_FAN_SPEED,
30	};	32	};
31		33
32	enum xe_hwmon_reg_operation {	34	enum xe_hwmon_reg_operation {
@@ -42,6 +44,13 @@ enum xe_hwmon_channel { · 9 unmodified lines
42	CHANNEL_MAX,	44	CHANNEL_MAX,
43	};	45	};
44		46
		47	enum xe_fan_channel {
		48	FAN_1,
		49	FAN_2,
		50	FAN_3,
		51	FAN_MAX,
		52	};
		53
45	/*	54	/*
46	* SF_* - scale factors for particular quantities according to hwmon spec.	55	* SF_* - scale factors for particular quantities according to hwmon spec.
47	*/	56	*/
@@ -61,6 +70,16 @@ struct xe_hwmon_energy_info { · 13 unmodified lines
61	long accum_energy;	70	long accum_energy;
62	};	71	};
63		72
		73	/**
		74	* struct xe_hwmon_fan_info - to cache previous fan reading
		75	*/
		76	struct xe_hwmon_fan_info {
		77	/** @reg_val_prev: previous fan reg val */
		78	u32 reg_val_prev;
		79	/** @time_prev: previous timestamp */
		80	u64 time_prev;
		81	};
		82
64	/**	83	/**
65	* struct xe_hwmon - xe hwmon data structure	84	* struct xe_hwmon - xe hwmon data structure
66	*/	85	*/
@@ -79,6 +98,8 @@ struct xe_hwmon { · 12 unmodified lines
79	int scl_shift_time;	98	int scl_shift_time;
80	/** @ei: Energy info for energyN_input */	99	/** @ei: Energy info for energyN_input */
81	struct xe_hwmon_energy_info ei[CHANNEL_MAX];	100	struct xe_hwmon_energy_info ei[CHANNEL_MAX];
		101	/** @fi: Fan info for fanN_input */
		102	struct xe_hwmon_fan_info fi[FAN_MAX];
82	};	103	};
83		104
84	static struct xe_reg xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg,	105	static struct xe_reg xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg,
@@ -144,6 +165,14 @@ static struct xe_reg xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg · 59 unmodified lines
144	return PCU_CR_PACKAGE_ENERGY_STATUS;	165	return PCU_CR_PACKAGE_ENERGY_STATUS;
145	}	166	}
146	break;	167	break;
		168	case REG_FAN_SPEED:
		169	if (channel == FAN_1)
		170	return BMG_FAN_1_SPEED;
		171	else if (channel == FAN_2)
		172	return BMG_FAN_2_SPEED;
		173	else if (channel == FAN_3)
		174	return BMG_FAN_3_SPEED;
		175	break;
147	default:	176	default:
148	drm_warn(&xe->drm, "Unknown xe hwmon reg id: %d\n", hwmon_reg);	177	drm_warn(&xe->drm, "Unknown xe hwmon reg id: %d\n", hwmon_reg);
149	break;	178	break;
@@ -454,6 +483,7 @@ static const struct hwmon_channel_info * const hwmon_info[] = { · 304 unmodified lines
454	HWMON_CHANNEL_INFO(curr, HWMON_C_LABEL, HWMON_C_CRIT \| HWMON_C_LABEL),	483	HWMON_CHANNEL_INFO(curr, HWMON_C_LABEL, HWMON_C_CRIT \| HWMON_C_LABEL),
455	HWMON_CHANNEL_INFO(in, HWMON_I_INPUT \| HWMON_I_LABEL, HWMON_I_INPUT \| HWMON_I_LABEL),	484	HWMON_CHANNEL_INFO(in, HWMON_I_INPUT \| HWMON_I_LABEL, HWMON_I_INPUT \| HWMON_I_LABEL),
456	HWMON_CHANNEL_INFO(energy, HWMON_E_INPUT \| HWMON_E_LABEL, HWMON_E_INPUT \| HWMON_E_LABEL),	485	HWMON_CHANNEL_INFO(energy, HWMON_E_INPUT \| HWMON_E_LABEL, HWMON_E_INPUT \| HWMON_E_LABEL),
		486	HWMON_CHANNEL_INFO(fan, HWMON_F_INPUT, HWMON_F_INPUT, HWMON_F_INPUT),
457	NULL	487	NULL
458	};	488	};
459		489
@@ -480,6 +510,19 @@ static int xe_hwmon_pcode_write_i1(const struct xe_hwmon *hwmon, u32 uval) · 20 unmodified lines
480	(uval & POWER_SETUP_I1_DATA_MASK));	510	(uval & POWER_SETUP_I1_DATA_MASK));
481	}	511	}
482		512
		513	static int xe_hwmon_pcode_read_fan_control(const struct xe_hwmon hwmon, u32 subcmd, u32 uval)
		514	{
		515	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
		516
		517	/* Platforms that don't return correct value */
		518	if (hwmon->xe->info.platform == XE_DG2 && subcmd == FSC_READ_NUM_FANS) {
		519	*uval = 2;
		520	return 0;
		521	}
		522
		523	return xe_pcode_read(root_tile, PCODE_MBOX(FAN_SPEED_CONTROL, subcmd, 0), uval, NULL);
		524	}
		525
483	static int xe_hwmon_power_curr_crit_read(struct xe_hwmon *hwmon, int channel,	526	static int xe_hwmon_power_curr_crit_read(struct xe_hwmon *hwmon, int channel,
484	long *value, u32 scale_factor)	527	long *value, u32 scale_factor)
485	{	528	{
@@ -705,6 +748,75 @@ xe_hwmon_energy_read(struct xe_hwmon hwmon, u32 attr, int channel, long val) · 219 unmodified lines
705	}	748	}
706	}	749	}
707		750
		751	static umode_t
		752	xe_hwmon_fan_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel)
		753	{
		754	u32 uval;
		755
		756	if (!hwmon->xe->info.has_fan_control)
		757	return 0;
		758
		759	switch (attr) {
		760	case hwmon_fan_input:
		761	if (xe_hwmon_pcode_read_fan_control(hwmon, FSC_READ_NUM_FANS, &uval))
		762	return 0;
		763
		764	return channel < uval ? 0444 : 0;
		765	default:
		766	return 0;
		767	}
		768	}
		769
		770	static int
		771	xe_hwmon_fan_input_read(struct xe_hwmon hwmon, int channel, long val)
		772	{
		773	struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
		774	struct xe_hwmon_fan_info *fi = &hwmon->fi[channel];
		775	u64 rotations, time_now, time;
		776	u32 reg_val;
		777	int ret = 0;
		778
		779	mutex_lock(&hwmon->hwmon_lock);
		780
		781	reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_FAN_SPEED, channel));
		782	time_now = get_jiffies_64();
		783
		784	/*
		785	* HW register value is accumulated count of pulses from PWM fan with the scale
		786	* of 2 pulses per rotation.
		787	*/
		788	rotations = (reg_val - fi->reg_val_prev) / 2;
		789
		790	time = jiffies_delta_to_msecs(time_now - fi->time_prev);
		791	if (unlikely(!time)) {
		792	ret = -EAGAIN;
		793	goto unlock;
		794	}
		795
		796	/*
		797	* Calculate fan speed in RPM by time averaging two subsequent readings in minutes.
		798	* RPM = number of rotations * msecs per minute / time in msecs
		799	*/
		800	val = DIV_ROUND_UP_ULL(rotations (MSEC_PER_SEC * 60), time);
		801
		802	fi->reg_val_prev = reg_val;
		803	fi->time_prev = time_now;
		804	unlock:
		805	mutex_unlock(&hwmon->hwmon_lock);
		806	return ret;
		807	}
		808
		809	static int
		810	xe_hwmon_fan_read(struct xe_hwmon hwmon, u32 attr, int channel, long val)
		811	{
		812	switch (attr) {
		813	case hwmon_fan_input:
		814	return xe_hwmon_fan_input_read(hwmon, channel, val);
		815	default:
		816	return -EOPNOTSUPP;
		817	}
		818	}
		819
708	static umode_t	820	static umode_t
709	xe_hwmon_is_visible(const void *drvdata, enum hwmon_sensor_types type,	821	xe_hwmon_is_visible(const void *drvdata, enum hwmon_sensor_types type,
710	u32 attr, int channel)	822	u32 attr, int channel)
@@ -730,6 +842,9 @@ xe_hwmon_is_visible(const void *drvdata, enum hwmon_sensor_types type, · 19 unmodified lines
730	case hwmon_energy:	842	case hwmon_energy:
731	ret = xe_hwmon_energy_is_visible(hwmon, attr, channel);	843	ret = xe_hwmon_energy_is_visible(hwmon, attr, channel);
732	break;	844	break;
		845	case hwmon_fan:
		846	ret = xe_hwmon_fan_is_visible(hwmon, attr, channel);
		847	break;
733	default:	848	default:
734	ret = 0;	849	ret = 0;
735	break;	850	break;
@@ -765,6 +880,9 @@ xe_hwmon_read(struct device *dev, enum hwmon_sensor_types type, u32 attr, · 29 unmodified lines
765	case hwmon_energy:	880	case hwmon_energy:
766	ret = xe_hwmon_energy_read(hwmon, attr, channel, val);	881	ret = xe_hwmon_energy_read(hwmon, attr, channel, val);
767	break;	882	break;
		883	case hwmon_fan:
		884	ret = xe_hwmon_fan_read(hwmon, attr, channel, val);
		885	break;
768	default:	886	default:
769	ret = -EOPNOTSUPP;	887	ret = -EOPNOTSUPP;
770	break;	888	break;
@@ -842,7 +960,7 @@ static void · 71 unmodified lines
842	xe_hwmon_get_preregistration_info(struct xe_hwmon *hwmon)	960	xe_hwmon_get_preregistration_info(struct xe_hwmon *hwmon)
843	{	961	{
844	struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);	962	struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe);
845	long energy;	963	long energy, fan_speed;
846	u64 val_sku_unit = 0;	964	u64 val_sku_unit = 0;
847	int channel;	965	int channel;
848	struct xe_reg pkg_power_sku_unit;	966	struct xe_reg pkg_power_sku_unit;
@@ -866,6 +984,11 @@ xe_hwmon_get_preregistration_info(struct xe_hwmon *hwmon) · 17 unmodified lines
866	for (channel = 0; channel < CHANNEL_MAX; channel++)	984	for (channel = 0; channel < CHANNEL_MAX; channel++)
867	if (xe_hwmon_is_visible(hwmon, hwmon_energy, hwmon_energy_input, channel))	985	if (xe_hwmon_is_visible(hwmon, hwmon_energy, hwmon_energy_input, channel))
868	xe_hwmon_energy_get(hwmon, channel, &energy);	986	xe_hwmon_energy_get(hwmon, channel, &energy);
		987
		988	/* Initialize 'struct xe_hwmon_fan_info' with initial fan register reading. */
		989	for (channel = 0; channel < FAN_MAX; channel++)
		990	if (xe_hwmon_is_visible(hwmon, hwmon_fan, hwmon_fan_input, channel))
		991	xe_hwmon_fan_input_read(hwmon, channel, &fan_speed);
869	}	992	}
870		993
871	static void xe_hwmon_mutex_destroy(void *arg)	994	static void xe_hwmon_mutex_destroy(void *arg)

drivers/gpu/drm/xe/xe_lmtt.c+1−1

@@ -71,7 +71,7 @@ static struct xe_lmtt_pt lmtt_pt_alloc(struct xe_lmtt lmtt, unsigned int level · 70 unmodified lines
71	lmtt->ops->lmtt_pte_num(level)),	71	lmtt->ops->lmtt_pte_num(level)),
72	ttm_bo_type_kernel,	72	ttm_bo_type_kernel,
73	XE_BO_FLAG_VRAM_IF_DGFX(lmtt_to_tile(lmtt)) \|	73	XE_BO_FLAG_VRAM_IF_DGFX(lmtt_to_tile(lmtt)) \|
74	XE_BO_FLAG_NEEDS_64K \| XE_BO_FLAG_PINNED);	74	XE_BO_FLAG_NEEDS_64K);
75	if (IS_ERR(bo)) {	75	if (IS_ERR(bo)) {
76	err = PTR_ERR(bo);	76	err = PTR_ERR(bo);
77	goto out_free_pt;	77	goto out_free_pt;

drivers/gpu/drm/xe/xe_lrc.c+18−10

 #define LRC_ENGINE_CLASS			GENMASK_ULL(63, 61)
 #define LRC_ENGINE_INSTANCE			GENMASK_ULL(53, 48)
+#define LRC_PPHWSP_SIZE				SZ_4K
 #define LRC_INDIRECT_RING_STATE_SIZE		SZ_4K
 static struct xe_device *
 	struct xe_device *xe = gt_to_xe(gt);
 	size_t size;
+	/* Per-process HW status page (PPHWSP) */
+	size = LRC_PPHWSP_SIZE;
+	/* Engine context image */
 	switch (class) {
 	case XE_ENGINE_CLASS_RENDER:
 		if (GRAPHICS_VER(xe) >= 20)
-			size = 4 * SZ_4K;
+			size += 3 * SZ_4K;
 		else
-			size = 14 * SZ_4K;
+			size += 13 * SZ_4K;
 		break;
 	case XE_ENGINE_CLASS_COMPUTE:
-		/* 14 pages since graphics_ver == 11 */
 		if (GRAPHICS_VER(xe) >= 20)
-			size = 3 * SZ_4K;
+			size += 2 * SZ_4K;
 		else
-			size = 14 * SZ_4K;
+			size += 13 * SZ_4K;
 		break;
 	default:
 		WARN(1, "Unknown engine class: %d", class);
 	case XE_ENGINE_CLASS_VIDEO_DECODE:
 	case XE_ENGINE_CLASS_VIDEO_ENHANCE:
 	case XE_ENGINE_CLASS_OTHER:
-		size = 2 * SZ_4K;
+		size += 1 * SZ_4K;
 	}
 	/* Add indirect ring state page */
 #define LRC_START_SEQNO_PPHWSP_OFFSET (LRC_SEQNO_PPHWSP_OFFSET + 8)
 #define LRC_CTX_JOB_TIMESTAMP_OFFSET (LRC_START_SEQNO_PPHWSP_OFFSET + 8)
 #define LRC_PARALLEL_PPHWSP_OFFSET 2048
-#define LRC_PPHWSP_SIZE SZ_4K
 u32 xe_lrc_regs_offset(struct xe_lrc *lrc)
 {
 	void *init_data = NULL;
 	u32 arb_enable;
 	u32 lrc_size;
+	u32 bo_flags;
 	int err;
 	kref_init(&lrc->refcount);
 	if (xe_gt_has_indirect_ring_state(gt))
 		lrc->flags |= XE_LRC_FLAG_INDIRECT_RING_STATE;
+	bo_flags = XE_BO_FLAG_VRAM_IF_DGFX(tile) | XE_BO_FLAG_GGTT |
+		   XE_BO_FLAG_GGTT_INVALIDATE;
+	if (vm && vm->xef) /* userspace */
+		bo_flags |= XE_BO_FLAG_PINNED_LATE_RESTORE;
 	/*
 	 * FIXME: Perma-pinning LRC as we don't yet support moving GGTT address
 	 * via VM bind calls.
 	 */
 	lrc->bo = xe_bo_create_pin_map(xe, tile, vm, lrc_size,
 				       ttm_bo_type_kernel,
-				       XE_BO_FLAG_VRAM_IF_DGFX(tile) |
+				       bo_flags);
-				       XE_BO_FLAG_GGTT |
-				       XE_BO_FLAG_GGTT_INVALIDATE);
 	if (IS_ERR(lrc->bo))
 		return PTR_ERR(lrc->bo);
 	MATCH3D(3DSTATE_CLIP_MESH);
 	MATCH3D(3DSTATE_SBE_MESH);
 	MATCH3D(3DSTATE_CPSIZE_CONTROL_BUFFER);
+	MATCH3D(3DSTATE_COARSE_PIXEL);
 	MATCH3D(3DSTATE_DRAWING_RECTANGLE);
 	MATCH3D(3DSTATE_CHROMA_KEY);

drivers/gpu/drm/xe/xe_memirq.c+1−1

@@ -86,7 +86,7 @@ static const char guc_name(struct xe_guc guc) · 85 unmodified lines
86	* This object needs to be 4KiB aligned.	86	* This object needs to be 4KiB aligned.
87	*	87	*
88	* - _`Interrupt Source Report Page`: this is the equivalent of the	88	* - _`Interrupt Source Report Page`: this is the equivalent of the
89	* GEN11_GT_INTR_DWx registers, with each bit in those registers being	89	* GT_INTR_DWx registers, with each bit in those registers being
90	* mapped to a byte here. The offsets are the same, just bytes instead	90	* mapped to a byte here. The offsets are the same, just bytes instead
91	* of bits. This object needs to be cacheline aligned.	91	* of bits. This object needs to be cacheline aligned.
92	*	92	*

drivers/gpu/drm/xe/xe_migrate.c+15−9

 	return tile->migrate->q;
 }
-static void xe_migrate_fini(struct drm_device *dev, void *arg)
+static void xe_migrate_fini(void *arg)
 {
 	struct xe_migrate *m = arg;
 				  num_entries * XE_PAGE_SIZE,
 				  ttm_bo_type_kernel,
 				  XE_BO_FLAG_VRAM_IF_DGFX(tile) |
-				  XE_BO_FLAG_PINNED |
 				  XE_BO_FLAG_PAGETABLE);
 	if (IS_ERR(bo))
 		return PTR_ERR(bo);
 	struct xe_vm *vm;
 	int err;
-	m = drmm_kzalloc(&xe->drm, sizeof(*m), GFP_KERNEL);
+	m = devm_kzalloc(xe->drm.dev, sizeof(*m), GFP_KERNEL);
 	if (!m)
 		return ERR_PTR(-ENOMEM);
 	might_lock(&m->job_mutex);
 	fs_reclaim_release(GFP_KERNEL);
-	err = drmm_add_action_or_reset(&xe->drm, xe_migrate_fini, m);
+	err = devm_add_action_or_reset(xe->drm.dev, xe_migrate_fini, m);
 	if (err)
 		return ERR_PTR(err);
 	bool dst_is_pltt = dst->mem_type == XE_PL_TT;
 	bool src_is_vram = mem_type_is_vram(src->mem_type);
 	bool dst_is_vram = mem_type_is_vram(dst->mem_type);
+	bool type_device = src_bo->ttm.type == ttm_bo_type_device;
+	bool needs_ccs_emit = type_device && xe_migrate_needs_ccs_emit(xe);
 	bool copy_ccs = xe_device_has_flat_ccs(xe) &&
 		xe_bo_needs_ccs_pages(src_bo) && xe_bo_needs_ccs_pages(dst_bo);
 	bool copy_system_ccs = copy_ccs && (!src_is_vram || !dst_is_vram);
-	bool use_comp_pat = xe_device_has_flat_ccs(xe) &&
+	bool use_comp_pat = type_device && xe_device_has_flat_ccs(xe) &&
 		GRAPHICS_VER(xe) >= 20 && src_is_vram && !dst_is_vram;
 	/* Copying CCS between two different BOs is not supported yet. */
 					      avail_pts, avail_pts);
 		if (copy_system_ccs) {
+			xe_assert(xe, type_device);
 			ccs_size = xe_device_ccs_bytes(xe, src_L0);
 			batch_size += pte_update_size(m, 0, NULL, &ccs_it, &ccs_size,
 						      &ccs_ofs, &ccs_pt, 0,
 		/* Add copy commands size here */
 		batch_size += ((copy_only_ccs) ? 0 : EMIT_COPY_DW) +
-			((xe_migrate_needs_ccs_emit(xe) ? EMIT_COPY_CCS_DW : 0));
+			((needs_ccs_emit ? EMIT_COPY_CCS_DW : 0));
 		bb = xe_bb_new(gt, batch_size, usm);
 		if (IS_ERR(bb)) {
 		if (!copy_only_ccs)
 			emit_copy(gt, bb, src_L0_ofs, dst_L0_ofs, src_L0, XE_PAGE_SIZE);
-		if (xe_migrate_needs_ccs_emit(xe))
+		if (needs_ccs_emit)
 			flush_flags = xe_migrate_ccs_copy(m, bb, src_L0_ofs,
 							  IS_DGFX(xe) ? src_is_vram : src_is_pltt,
 							  dst_L0_ofs,
 		dma_fence_wait(m->fence, false);
 }
+#if IS_ENABLED(CONFIG_DRM_XE_DEVMEM_MIRROR)
 static u32 pte_update_cmd_size(u64 size)
 {
 	u32 num_dword;
 {
 	struct xe_gt *gt = m->tile->primary_gt;
 	struct xe_device *xe = gt_to_xe(gt);
+	bool use_usm_batch = xe->info.has_usm;
 	struct dma_fence *fence = NULL;
 	u32 batch_size = 2;
 	u64 src_L0_ofs, dst_L0_ofs;
 	batch_size += pte_update_cmd_size(round_update_size);
 	batch_size += EMIT_COPY_DW;
-	bb = xe_bb_new(gt, batch_size, true);
+	bb = xe_bb_new(gt, batch_size, use_usm_batch);
 	if (IS_ERR(bb)) {
 		err = PTR_ERR(bb);
 		return ERR_PTR(err);
 		  XE_PAGE_SIZE);
 	job = xe_bb_create_migration_job(m->q, bb,
-					 xe_migrate_batch_base(m, true),
+					 xe_migrate_batch_base(m, use_usm_batch),
 					 update_idx);
 	if (IS_ERR(job)) {
 		err = PTR_ERR(job);
 			       XE_MIGRATE_COPY_TO_SRAM);
 }
+#endif
 #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
 #include "tests/xe_migrate.c"
 #endif

drivers/gpu/drm/xe/xe_mmio.c+7−4

 	return devm_add_action_or_reset(xe->drm.dev, mmio_fini, xe);
 }
+ALLOW_ERROR_INJECTION(xe_mmio_probe_early, ERRNO); /* See xe_pci_probe() */
 /**
  * xe_mmio_init() - Initialize an MMIO instance
 	trace_xe_reg_rw(mmio, true, addr, val, sizeof(val));
-	if (!reg.vf && mmio->sriov_vf_gt)
+	if (!reg.vf && IS_SRIOV_VF(mmio->tile->xe))
-		xe_gt_sriov_vf_write32(mmio->sriov_vf_gt, reg, val);
+		xe_gt_sriov_vf_write32(mmio->sriov_vf_gt ?:
+				       mmio->tile->primary_gt, reg, val);
 	else
 		writel(val, mmio->regs + addr);
 }
 	/* Wa_15015404425 */
 	mmio_flush_pending_writes(mmio);
-	if (!reg.vf && mmio->sriov_vf_gt)
+	if (!reg.vf && IS_SRIOV_VF(mmio->tile->xe))
-		val = xe_gt_sriov_vf_read32(mmio->sriov_vf_gt, reg);
+		val = xe_gt_sriov_vf_read32(mmio->sriov_vf_gt ?:
+					    mmio->tile->primary_gt, reg);
 	else
 		val = readl(mmio->regs + addr);

drivers/gpu/drm/xe/xe_module.c+7−2

 #include <drm/drm_module.h>
 #include "xe_drv.h"
+#include "xe_configfs.h"
 #include "xe_hw_fence.h"
 #include "xe_pci.h"
 #include "xe_pm.h"
 module_param_named(probe_display, xe_modparam.probe_display, bool, 0444);
 MODULE_PARM_DESC(probe_display, "Probe display HW, otherwise it's left untouched (default: true)");
-module_param_named(vram_bar_size, xe_modparam.force_vram_bar_size, uint, 0600);
+module_param_named(vram_bar_size, xe_modparam.force_vram_bar_size, int, 0600);
-MODULE_PARM_DESC(vram_bar_size, "Set the vram bar size(in MiB)");
+MODULE_PARM_DESC(vram_bar_size, "Set the vram bar size (in MiB) - <0=disable-resize, 0=max-needed-size[default], >0=force-size");
 module_param_named(guc_log_level, xe_modparam.guc_log_level, int, 0600);
 MODULE_PARM_DESC(guc_log_level, "GuC firmware logging level (0=disable, 1..5=enable with verbosity min..max)");
 	{
 		.init = xe_check_nomodeset,
 	},
+	{
+		.init = xe_configfs_init,
+		.exit = xe_configfs_exit,
+	},
 	{
 		.init = xe_hw_fence_module_init,
 		.exit = xe_hw_fence_module_exit,

drivers/gpu/drm/xe/xe_oa.c+1−0

@@ -2221,6 +2221,7 @@ addr_err: · 2220 unmodified lines
2221	kfree(oa_regs);	2221	kfree(oa_regs);
2222	return ERR_PTR(err);	2222	return ERR_PTR(err);
2223	}	2223	}
		2224	ALLOW_ERROR_INJECTION(xe_oa_alloc_regs, ERRNO);
2224		2225
2225	static ssize_t show_dynamic_id(struct kobject *kobj,	2226	static ssize_t show_dynamic_id(struct kobject *kobj,
2226	struct kobj_attribute *attr,	2227	struct kobj_attribute *attr,

drivers/gpu/drm/xe/xe_pci.c+19−10

 	u8 is_dgfx:1;
 	u8 has_display:1;
+	u8 has_fan_control:1;
 	u8 has_heci_gscfi:1;
 	u8 has_heci_cscfi:1;
 	u8 has_llc:1;
 	u8 has_pxp:1;
 	u8 has_sriov:1;
+	u8 needs_scratch:1;
 	u8 skip_guc_pc:1;
 	u8 skip_mtcfg:1;
 	u8 skip_pcode:1;
 	DG2_FEATURES,
 	.has_display = true,
+	.has_fan_control = true,
 };
 static const __maybe_unused struct xe_device_desc pvc_desc = {
 	.dma_mask_size = 46,
 	.has_display = true,
 	.has_pxp = true,
+	.needs_scratch = true,
 };
 static const struct xe_device_desc bmg_desc = {
 	PLATFORM(BATTLEMAGE),
 	.dma_mask_size = 46,
 	.has_display = true,
+	.has_fan_control = true,
 	.has_heci_cscfi = 1,
+	.needs_scratch = true,
 };
 static const struct xe_device_desc ptl_desc = {
 	.has_display = true,
 	.has_sriov = true,
 	.require_force_probe = true,
+	.needs_scratch = true,
 };
 #undef PLATFORM
 	xe->info.dma_mask_size = desc->dma_mask_size;
 	xe->info.is_dgfx = desc->is_dgfx;
+	xe->info.has_fan_control = desc->has_fan_control;
 	xe->info.has_heci_gscfi = desc->has_heci_gscfi;
 	xe->info.has_heci_cscfi = desc->has_heci_cscfi;
 	xe->info.has_llc = desc->has_llc;
 	xe->info.skip_guc_pc = desc->skip_guc_pc;
 	xe->info.skip_mtcfg = desc->skip_mtcfg;
 	xe->info.skip_pcode = desc->skip_pcode;
+	xe->info.needs_scratch = desc->needs_scratch;
 	xe->info.probe_display = IS_ENABLED(CONFIG_DRM_XE_DISPLAY) &&
 				 xe_modparam.probe_display &&
 		return err;
 	err = xe_device_probe_early(xe);
-	if (err) {
+	/*
-		/*
+	 * In Boot Survivability mode, no drm card is exposed and driver
-		 * In Boot Survivability mode, no drm card is exposed and driver
+	 * is loaded with bare minimum to allow for firmware to be
-		 * is loaded with bare minimum to allow for firmware to be
+	 * flashed through mei. Return success, if survivability mode
-		 * flashed through mei. If early probe failed, but it managed to
+	 * is enabled due to pcode failure or configfs being set
-		 * enable survivability mode, return success.
+	 */
-		 */
+	if (xe_survivability_mode_is_enabled(xe))
-		if (xe_survivability_mode_is_enabled(xe))
+		return 0;
-			return 0;
+	if (err)
 		return err;
-	}
 	err = xe_info_init(xe, desc);
 	if (err)
 	pci_save_state(pdev);
 	pci_disable_device(pdev);
+	pci_set_power_state(pdev, PCI_D3cold);
 	return 0;
 }

drivers/gpu/drm/xe/xe_pci_sriov.c+20−0

 #include "xe_device.h"
 #include "xe_gt_sriov_pf_config.h"
 #include "xe_gt_sriov_pf_control.h"
+#include "xe_guc_engine_activity.h"
 #include "xe_pci_sriov.h"
 #include "xe_pm.h"
 #include "xe_sriov.h"
 	}
 }
+static void pf_engine_activity_stats(struct xe_device *xe, unsigned int num_vfs, bool enable)
+{
+	struct xe_gt *gt;
+	unsigned int id;
+	int ret = 0;
+	for_each_gt(gt, xe, id) {
+		ret = xe_guc_engine_activity_function_stats(&gt->uc.guc, num_vfs, enable);
+		if (ret)
+			xe_sriov_info(xe, "Failed to %s engine activity function stats (%pe)\n",
+				      str_enable_disable(enable), ERR_PTR(ret));
+	}
+}
 static int pf_enable_vfs(struct xe_device *xe, int num_vfs)
 {
 	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
 	xe_sriov_info(xe, "Enabled %u of %u VF%s\n",
 		      num_vfs, total_vfs, str_plural(total_vfs));
+	pf_engine_activity_stats(xe, num_vfs, true);
 	return num_vfs;
 failed:
 	if (!num_vfs)
 		return 0;
+	pf_engine_activity_stats(xe, num_vfs, false);
 	pci_disable_sriov(pdev);
 	pf_reset_vfs(xe, num_vfs);

drivers/gpu/drm/xe/xe_pcode.c+2−0

 #include <linux/delay.h>
 #include <linux/errno.h>
+#include <linux/error-injection.h>
 #include <drm/drm_managed.h>
 {
 	return xe_pcode_ready(xe, false);
 }
+ALLOW_ERROR_INJECTION(xe_pcode_probe_early, ERRNO); /* See xe_pci_probe */

drivers/gpu/drm/xe/xe_pcode_api.h+3−0

@@ -49,6 +49,9 @@ · 48 unmodified lines
49	/* Domain IDs (param2) */	49	/* Domain IDs (param2) */
50	#define PCODE_MBOX_DOMAIN_HBM 0x2	50	#define PCODE_MBOX_DOMAIN_HBM 0x2
51		51
		52	#define FAN_SPEED_CONTROL 0x7D
		53	#define FSC_READ_NUM_FANS 0x4
		54
52	#define PCODE_SCRATCH(x) XE_REG(0x138320 + ((x) * 4))	55	#define PCODE_SCRATCH(x) XE_REG(0x138320 + ((x) * 4))
53	/* PCODE_SCRATCH0 */	56	/* PCODE_SCRATCH0 */
54	#define AUXINFO_REG_OFFSET REG_GENMASK(17, 15)	57	#define AUXINFO_REG_OFFSET REG_GENMASK(17, 15)

drivers/gpu/drm/xe/xe_pm.c+4−4

@@ -188,7 +188,7 @@ int xe_pm_resume(struct xe_device *xe) · 187 unmodified lines
188	* This only restores pinned memory which is the memory required for the	188	* This only restores pinned memory which is the memory required for the
189	* GT(s) to resume.	189	* GT(s) to resume.
190	*/	190	*/
191	err = xe_bo_restore_kernel(xe);	191	err = xe_bo_restore_early(xe);
192	if (err)	192	if (err)
193	goto err;	193	goto err;
194		194
@@ -199,7 +199,7 @@ int xe_pm_resume(struct xe_device *xe) · 4 unmodified lines
199		199
200	xe_display_pm_resume(xe);	200	xe_display_pm_resume(xe);
201		201
202	err = xe_bo_restore_user(xe);	202	err = xe_bo_restore_late(xe);
203	if (err)	203	if (err)
204	goto err;	204	goto err;
205		205
@@ -484,7 +484,7 @@ int xe_pm_runtime_resume(struct xe_device *xe) · 278 unmodified lines
484	* This only restores pinned memory which is the memory	484	* This only restores pinned memory which is the memory
485	* required for the GT(s) to resume.	485	* required for the GT(s) to resume.
486	*/	486	*/
487	err = xe_bo_restore_kernel(xe);	487	err = xe_bo_restore_early(xe);
488	if (err)	488	if (err)
489	goto out;	489	goto out;
490	}	490	}
@@ -497,7 +497,7 @@ int xe_pm_runtime_resume(struct xe_device *xe) · 6 unmodified lines
497	xe_display_pm_runtime_resume(xe);	497	xe_display_pm_runtime_resume(xe);
498		498
499	if (xe->d3cold.allowed) {	499	if (xe->d3cold.allowed) {
500	err = xe_bo_restore_user(xe);	500	err = xe_bo_restore_late(xe);
501	if (err)	501	if (err)
502	goto out;	502	goto out;
503	}	503	}

drivers/gpu/drm/xe/xe_pmu.c+67−10

 #include "xe_force_wake.h"
 #include "xe_gt_idle.h"
 #include "xe_guc_engine_activity.h"
+#include "xe_guc_pc.h"
 #include "xe_hw_engine.h"
 #include "xe_pm.h"
 #include "xe_pmu.h"
+#include "xe_sriov_pf_helpers.h"
 /**
  * DOC: Xe PMU (Performance Monitoring Unit)
  *	gt[60:63]		Selects gt for the event
  *	engine_class[20:27]	Selects engine-class for event
  *	engine_instance[12:19]	Selects the engine-instance for the event
+ *	function[44:59]		Selects the function of the event (SRIOV enabled)
  *
  * For engine specific events (engine-*), gt, engine_class and engine_instance parameters must be
- * set as populated by DRM_XE_DEVICE_QUERY_ENGINES.
+ * set as populated by DRM_XE_DEVICE_QUERY_ENGINES and function if SRIOV is enabled.
  *
  * For gt specific events (gt-*) gt parameter must be passed. All other parameters will be 0.
  *
  */
 #define XE_PMU_EVENT_GT_MASK			GENMASK_ULL(63, 60)
+#define XE_PMU_EVENT_FUNCTION_MASK		GENMASK_ULL(59, 44)
 #define XE_PMU_EVENT_ENGINE_CLASS_MASK		GENMASK_ULL(27, 20)
 #define XE_PMU_EVENT_ENGINE_INSTANCE_MASK	GENMASK_ULL(19, 12)
 #define XE_PMU_EVENT_ID_MASK			GENMASK_ULL(11, 0)
 	return FIELD_GET(XE_PMU_EVENT_ID_MASK, config);
 }
+static unsigned int config_to_function_id(u64 config)
+{
+	return FIELD_GET(XE_PMU_EVENT_FUNCTION_MASK, config);
+}
 static unsigned int config_to_engine_class(u64 config)
 {
 	return FIELD_GET(XE_PMU_EVENT_ENGINE_CLASS_MASK, config);
 #define XE_PMU_EVENT_GT_C6_RESIDENCY		0x01
 #define XE_PMU_EVENT_ENGINE_ACTIVE_TICKS	0x02
 #define XE_PMU_EVENT_ENGINE_TOTAL_TICKS		0x03
+#define XE_PMU_EVENT_GT_ACTUAL_FREQUENCY	0x04
+#define XE_PMU_EVENT_GT_REQUESTED_FREQUENCY	0x05
 static struct xe_gt *event_to_gt(struct perf_event *event)
 {
 		event_id == XE_PMU_EVENT_ENGINE_ACTIVE_TICKS);
 }
+static bool is_gt_frequency_event(struct perf_event *event)
+{
+	u32 id = config_to_event_id(event->attr.config);
+	return id == XE_PMU_EVENT_GT_ACTUAL_FREQUENCY ||
+	       id == XE_PMU_EVENT_GT_REQUESTED_FREQUENCY;
+}
 static bool event_gt_forcewake(struct perf_event *event)
 {
 	struct xe_device *xe = container_of(event->pmu, typeof(*xe), pmu.base);
 	struct xe_gt *gt;
 	unsigned int *fw_ref;
-	if (!is_engine_event(config))
+	if (!is_engine_event(config) && !is_gt_frequency_event(event))
 		return true;
 	gt = xe_device_get_gt(xe, config_to_gt_id(config));
 static bool event_param_valid(struct perf_event *event)
 {
 	struct xe_device *xe = container_of(event->pmu, typeof(*xe), pmu.base);
-	unsigned int engine_class, engine_instance;
+	unsigned int engine_class, engine_instance, function_id;
 	u64 config = event->attr.config;
 	struct xe_gt *gt;
 	engine_class = config_to_engine_class(config);
 	engine_instance = config_to_engine_instance(config);
+	function_id = config_to_function_id(config);
 	switch (config_to_event_id(config)) {
 	case XE_PMU_EVENT_GT_C6_RESIDENCY:
-		if (engine_class || engine_instance)
+	case XE_PMU_EVENT_GT_ACTUAL_FREQUENCY:
+	case XE_PMU_EVENT_GT_REQUESTED_FREQUENCY:
+		if (engine_class || engine_instance || function_id)
 			return false;
 		break;
 	case XE_PMU_EVENT_ENGINE_ACTIVE_TICKS:
 	case XE_PMU_EVENT_ENGINE_TOTAL_TICKS:
 		if (!event_to_hwe(event))
 			return false;
+		/* PF(0) and total vfs when SRIOV is enabled */
+		if (IS_SRIOV_PF(xe)) {
+			if (function_id > xe_sriov_pf_get_totalvfs(xe))
+				return false;
+		} else if (function_id) {
+			return false;
+		}
 		break;
 	}
 static u64 read_engine_events(struct xe_gt *gt, struct perf_event *event)
 {
 	struct xe_hw_engine *hwe;
-	u64 val = 0;
+	unsigned int function_id;
+	u64 config, val = 0;
+	config = event->attr.config;
+	function_id = config_to_function_id(config);
 	hwe = event_to_hwe(event);
-	if (config_to_event_id(event->attr.config) == XE_PMU_EVENT_ENGINE_ACTIVE_TICKS)
+	if (config_to_event_id(config) == XE_PMU_EVENT_ENGINE_ACTIVE_TICKS)
-		val = xe_guc_engine_activity_active_ticks(&gt->uc.guc, hwe);
+		val = xe_guc_engine_activity_active_ticks(&gt->uc.guc, hwe, function_id);
 	else
-		val = xe_guc_engine_activity_total_ticks(&gt->uc.guc, hwe);
+		val = xe_guc_engine_activity_total_ticks(&gt->uc.guc, hwe, function_id);
 	return val;
 }
 	case XE_PMU_EVENT_ENGINE_ACTIVE_TICKS:
 	case XE_PMU_EVENT_ENGINE_TOTAL_TICKS:
 		return read_engine_events(gt, event);
+	case XE_PMU_EVENT_GT_ACTUAL_FREQUENCY:
+		return xe_guc_pc_get_act_freq(&gt->uc.guc.pc);
+	case XE_PMU_EVENT_GT_REQUESTED_FREQUENCY:
+		return xe_guc_pc_get_cur_freq_fw(&gt->uc.guc.pc);
 	}
 	return 0;
 		new = __xe_pmu_event_read(event);
 	} while (!local64_try_cmpxchg(&hwc->prev_count, &prev, new));
-	local64_add(new - prev, &event->count);
+	/*
+	 * GT frequency is not a monotonically increasing counter, so add the
+	 * instantaneous value instead.
+	 */
+	if (is_gt_frequency_event(event))
+		local64_add(new, &event->count);
+	else
+		local64_add(new - prev, &event->count);
 }
 static void xe_pmu_event_read(struct perf_event *event)
 }
 PMU_FORMAT_ATTR(gt,			"config:60-63");
+PMU_FORMAT_ATTR(function,		"config:44-59");
 PMU_FORMAT_ATTR(engine_class,		"config:20-27");
 PMU_FORMAT_ATTR(engine_instance,	"config:12-19");
 PMU_FORMAT_ATTR(event,			"config:0-11");
 	&format_attr_event.attr,
 	&format_attr_engine_class.attr,
 	&format_attr_engine_instance.attr,
+	&format_attr_function.attr,
 	&format_attr_gt.attr,
 	NULL,
 };
 XE_EVENT_ATTR_SIMPLE(gt-c6-residency, gt_c6_residency, XE_PMU_EVENT_GT_C6_RESIDENCY, "ms");
 XE_EVENT_ATTR_NOUNIT(engine-active-ticks, engine_active_ticks, XE_PMU_EVENT_ENGINE_ACTIVE_TICKS);
 XE_EVENT_ATTR_NOUNIT(engine-total-ticks, engine_total_ticks, XE_PMU_EVENT_ENGINE_TOTAL_TICKS);
+XE_EVENT_ATTR_SIMPLE(gt-actual-frequency, gt_actual_frequency,
+		     XE_PMU_EVENT_GT_ACTUAL_FREQUENCY, "MHz");
+XE_EVENT_ATTR_SIMPLE(gt-requested-frequency, gt_requested_frequency,
+		     XE_PMU_EVENT_GT_REQUESTED_FREQUENCY, "MHz");
 static struct attribute *pmu_empty_event_attrs[] = {
 	/* Empty - all events are added as groups with .attr_update() */
 	&pmu_group_gt_c6_residency,
 	&pmu_group_engine_active_ticks,
 	&pmu_group_engine_total_ticks,
+	&pmu_group_gt_actual_frequency,
+	&pmu_group_gt_requested_frequency,
 	NULL,
 };
 	struct xe_device *xe = container_of(pmu, typeof(*xe), pmu);
 	struct xe_gt *gt = xe_device_get_gt(xe, 0);
-	if (!xe->info.skip_guc_pc)
+	if (!xe->info.skip_guc_pc) {
 		pmu->supported_events |= BIT_ULL(XE_PMU_EVENT_GT_C6_RESIDENCY);
+		pmu->supported_events |= BIT_ULL(XE_PMU_EVENT_GT_ACTUAL_FREQUENCY);
+		pmu->supported_events |= BIT_ULL(XE_PMU_EVENT_GT_REQUESTED_FREQUENCY);
+	}
 	if (xe_guc_engine_activity_supported(&gt->uc.guc)) {
 		pmu->supported_events |= BIT_ULL(XE_PMU_EVENT_ENGINE_ACTIVE_TICKS);

drivers/gpu/drm/xe/xe_pt.c+140−98

 {
 	struct xe_pt *pt;
 	struct xe_bo *bo;
+	u32 bo_flags;
 	int err;
 	if (level) {
 	if (!pt)
 		return ERR_PTR(-ENOMEM);
+	bo_flags = XE_BO_FLAG_VRAM_IF_DGFX(tile) |
+		   XE_BO_FLAG_IGNORE_MIN_PAGE_SIZE |
+		   XE_BO_FLAG_NO_RESV_EVICT | XE_BO_FLAG_PAGETABLE;
+	if (vm->xef) /* userspace */
+		bo_flags |= XE_BO_FLAG_PINNED_LATE_RESTORE;
 	pt->level = level;
 	bo = xe_bo_create_pin_map(vm->xe, tile, vm, SZ_4K,
 				  ttm_bo_type_kernel,
-				  XE_BO_FLAG_VRAM_IF_DGFX(tile) |
+				  bo_flags);
-				  XE_BO_FLAG_IGNORE_MIN_PAGE_SIZE |
-				  XE_BO_FLAG_PINNED |
-				  XE_BO_FLAG_NO_RESV_EVICT |
-				  XE_BO_FLAG_PAGETABLE);
 	if (IS_ERR(bo)) {
 		err = PTR_ERR(bo);
 		goto err_kfree;
 	bool preexisting;
 };
+/**
+ * struct xe_pt_stage_bind_walk - Walk state for the stage_bind walk.
+ */
 struct xe_pt_stage_bind_walk {
-	/** base: The base class. */
+	/** @base: The base class. */
 	struct xe_pt_walk base;
 	/* Input parameters for the walk */
 	struct xe_vm *vm;
 	/** @tile: The tile we're building for. */
 	struct xe_tile *tile;
-	/** @default_pte: PTE flag only template. No address is associated */
+	/** @default_vram_pte: PTE flag only template for VRAM. No address is associated */
-	u64 default_pte;
+	u64 default_vram_pte;
+	/** @default_system_pte: PTE flag only template for System. No address is associated */
+	u64 default_system_pte;
 	/** @dma_offset: DMA offset to add to the PTE. */
 	u64 dma_offset;
 	/**
-	 * @needs_64k: This address range enforces 64K alignment and
+	 * @needs_64K: This address range enforces 64K alignment and
-	 * granularity.
+	 * granularity on VRAM.
 	 */
 	bool needs_64K;
+	/** @clear_pt: clear page table entries during the bind walk */
+	bool clear_pt;
 	/**
 	 * @vma: VMA being mapped
 	 */
 	u64 va_curs_start;
 	/* Output */
+	/** @wupd: Walk output data for page-table updates. */
 	struct xe_walk_update {
 		/** @wupd.entries: Caller provided storage. */
 		struct xe_vm_pgtable_update *entries;
 	u64 l0_end_addr;
 	/** @addr_64K: The start address of the current 64K chunk. */
 	u64 addr_64K;
-	/** @found_64: Whether @add_64K actually points to a 64K chunk. */
+	/** @found_64K: Whether @add_64K actually points to a 64K chunk. */
 	bool found_64K;
 };
 	if (xe_vma_is_null(xe_walk->vma))
 		return true;
+	/* if we are clearing page table, no dma addresses*/
+	if (xe_walk->clear_pt)
+		return true;
 	/* Is the DMA address huge PTE size aligned? */
 	size = next - addr;
 	dma = addr - xe_walk->va_curs_start + xe_res_dma(xe_walk->curs);
 	if (level == 0 || xe_pt_hugepte_possible(addr, next, level, xe_walk)) {
 		struct xe_res_cursor *curs = xe_walk->curs;
 		bool is_null = xe_vma_is_null(xe_walk->vma);
+		bool is_vram = is_null ? false : xe_res_is_vram(curs);
 		XE_WARN_ON(xe_walk->va_curs_start != addr);
-		pte = vm->pt_ops->pte_encode_vma(is_null ? 0 :
+		if (xe_walk->clear_pt) {
-						 xe_res_dma(curs) + xe_walk->dma_offset,
+			pte = 0;
-						 xe_walk->vma, pat_index, level);
+		} else {
-		pte |= xe_walk->default_pte;
+			pte = vm->pt_ops->pte_encode_vma(is_null ? 0 :
+							 xe_res_dma(curs) +
+							 xe_walk->dma_offset,
+							 xe_walk->vma,
+							 pat_index, level);
+			if (!is_null)
+				pte |= is_vram ? xe_walk->default_vram_pte :
+					xe_walk->default_system_pte;
-		/*
+			/*
-		 * Set the XE_PTE_PS64 hint if possible, otherwise if
+			 * Set the XE_PTE_PS64 hint if possible, otherwise if
-		 * this device *requires* 64K PTE size for VRAM, fail.
+			 * this device *requires* 64K PTE size for VRAM, fail.
-		 */
+			 */
-		if (level == 0 && !xe_parent->is_compact) {
+			if (level == 0 && !xe_parent->is_compact) {
-			if (xe_pt_is_pte_ps64K(addr, next, xe_walk)) {
+				if (xe_pt_is_pte_ps64K(addr, next, xe_walk)) {
-				xe_walk->vma->gpuva.flags |= XE_VMA_PTE_64K;
+					xe_walk->vma->gpuva.flags |=
-				pte |= XE_PTE_PS64;
+							XE_VMA_PTE_64K;
-			} else if (XE_WARN_ON(xe_walk->needs_64K)) {
+					pte |= XE_PTE_PS64;
-				return -EINVAL;
+				} else if (XE_WARN_ON(xe_walk->needs_64K &&
+					   is_vram)) {
+					return -EINVAL;
+				}
 			}
 		}
 		if (unlikely(ret))
 			return ret;
-		if (!is_null)
+		if (!is_null && !xe_walk->clear_pt)
 			xe_res_next(curs, next - addr);
 		xe_walk->va_curs_start = next;
 		xe_walk->vma->gpuva.flags |= (XE_VMA_PTE_4K << level);
 	.pt_entry = xe_pt_stage_bind_entry,
 };
+/*
+ * Default atomic expectations for different allocation scenarios are as follows:
+ *
+ * 1. Traditional API: When the VM is not in LR mode:
+ *    - Device atomics are expected to function with all allocations.
+ *
+ * 2. Compute/SVM API: When the VM is in LR mode:
+ *    - Device atomics are the default behavior when the bo is placed in a single region.
+ *    - In all other cases device atomics will be disabled with AE=0 until an application
+ *      request differently using a ioctl like madvise.
+ */
+static bool xe_atomic_for_vram(struct xe_vm *vm)
+{
+	return true;
+}
+static bool xe_atomic_for_system(struct xe_vm *vm, struct xe_bo *bo)
+{
+	struct xe_device *xe = vm->xe;
+	if (!xe->info.has_device_atomics_on_smem)
+		return false;
+	/*
+	 * If a SMEM+LMEM allocation is backed by SMEM, a device
+	 * atomics will cause a gpu page fault and which then
+	 * gets migrated to LMEM, bind such allocations with
+	 * device atomics enabled.
+	 *
+	 * TODO: Revisit this. Perhaps add something like a
+	 * fault_on_atomics_in_system UAPI flag.
+	 * Note that this also prohibits GPU atomics in LR mode for
+	 * userptr and system memory on DGFX.
+	 */
+	return (!IS_DGFX(xe) || (!xe_vm_in_lr_mode(vm) ||
+				 (bo && xe_bo_has_single_placement(bo))));
+}
 /**
  * xe_pt_stage_bind() - Build a disconnected page-table tree for a given address
  * range.
  * @entries: Storage for the update entries used for connecting the tree to
  * the main tree at commit time.
  * @num_entries: On output contains the number of @entries used.
+ * @clear_pt: Clear the page table entries.
  *
  * This function builds a disconnected page-table tree for a given address
  * range. The tree is connected to the main vm tree for the gpu using
 static int
 xe_pt_stage_bind(struct xe_tile *tile, struct xe_vma *vma,
 		 struct xe_svm_range *range,
-		 struct xe_vm_pgtable_update *entries, u32 *num_entries)
+		 struct xe_vm_pgtable_update *entries,
+		 u32 *num_entries, bool clear_pt)
 {
 	struct xe_device *xe = tile_to_xe(tile);
 	struct xe_bo *bo = xe_vma_bo(vma);
-	bool is_devmem = !xe_vma_is_userptr(vma) && bo &&
-		(xe_bo_is_vram(bo) || xe_bo_is_stolen_devmem(bo));
 	struct xe_res_cursor curs;
+	struct xe_vm *vm = xe_vma_vm(vma);
 	struct xe_pt_stage_bind_walk xe_walk = {
 		.base = {
 			.ops = &xe_pt_stage_bind_ops,
 			.max_level = XE_PT_HIGHEST_LEVEL,
 			.staging = true,
 		},
-		.vm = xe_vma_vm(vma),
+		.vm = vm,
 		.tile = tile,
 		.curs = &curs,
 		.va_curs_start = range ? range->base.itree.start :
 			xe_vma_start(vma),
 		.vma = vma,
 		.wupd.entries = entries,
+		.clear_pt = clear_pt,
 	};
-	struct xe_pt *pt = xe_vma_vm(vma)->pt_root[tile->id];
+	struct xe_pt *pt = vm->pt_root[tile->id];
 	int ret;
 	if (range) {
 		/* Move this entire thing to xe_svm.c? */
-		xe_svm_notifier_lock(xe_vma_vm(vma));
+		xe_svm_notifier_lock(vm);
 		if (!xe_svm_range_pages_valid(range)) {
 			xe_svm_range_debug(range, "BIND PREPARE - RETRY");
-			xe_svm_notifier_unlock(xe_vma_vm(vma));
+			xe_svm_notifier_unlock(vm);
 			return -EAGAIN;
 		}
 		if (xe_svm_range_has_dma_mapping(range)) {
 			xe_res_first_dma(range->base.dma_addr, 0,
 					 range->base.itree.last + 1 - range->base.itree.start,
 					 &curs);
-			is_devmem = xe_res_is_vram(&curs);
+			xe_svm_range_debug(range, "BIND PREPARE - MIXED");
-			if (is_devmem)
-				xe_svm_range_debug(range, "BIND PREPARE - DMA VRAM");
-			else
-				xe_svm_range_debug(range, "BIND PREPARE - DMA");
 		} else {
 			xe_assert(xe, false);
 		}
 		 * Note, when unlocking the resource cursor dma addresses may become
 		 * stale, but the bind will be aborted anyway at commit time.
 		 */
-		xe_svm_notifier_unlock(xe_vma_vm(vma));
+		xe_svm_notifier_unlock(vm);
 	}
-	xe_walk.needs_64K = (xe_vma_vm(vma)->flags & XE_VM_FLAG_64K) && is_devmem;
+	xe_walk.needs_64K = (vm->flags & XE_VM_FLAG_64K);
+	if (clear_pt)
+		goto walk_pt;
-	/**
-	 * Default atomic expectations for different allocation scenarios are as follows:
-	 *
-	 * 1. Traditional API: When the VM is not in LR mode:
-	 *    - Device atomics are expected to function with all allocations.
-	 *
-	 * 2. Compute/SVM API: When the VM is in LR mode:
-	 *    - Device atomics are the default behavior when the bo is placed in a single region.
-	 *    - In all other cases device atomics will be disabled with AE=0 until an application
-	 *      request differently using a ioctl like madvise.
-	 */
 	if (vma->gpuva.flags & XE_VMA_ATOMIC_PTE_BIT) {
-		if (xe_vm_in_lr_mode(xe_vma_vm(vma))) {
+		xe_walk.default_vram_pte = xe_atomic_for_vram(vm) ? XE_USM_PPGTT_PTE_AE : 0;
-			if (bo && xe_bo_has_single_placement(bo))
+		xe_walk.default_system_pte = xe_atomic_for_system(vm, bo) ?
-				xe_walk.default_pte |= XE_USM_PPGTT_PTE_AE;
+			XE_USM_PPGTT_PTE_AE : 0;
-			/**
-			 * If a SMEM+LMEM allocation is backed by SMEM, a device
-			 * atomics will cause a gpu page fault and which then
-			 * gets migrated to LMEM, bind such allocations with
-			 * device atomics enabled.
-			 */
-			else if (is_devmem)
-				xe_walk.default_pte |= XE_USM_PPGTT_PTE_AE;
-		} else {
-			xe_walk.default_pte |= XE_USM_PPGTT_PTE_AE;
-		}
-		/**
-		 * Unset AE if the platform(PVC) doesn't support it on an
-		 * allocation
-		 */
-		if (!xe->info.has_device_atomics_on_smem && !is_devmem)
-			xe_walk.default_pte &= ~XE_USM_PPGTT_PTE_AE;
-	}
-	if (is_devmem) {
-		xe_walk.default_pte |= XE_PPGTT_PTE_DM;
-		xe_walk.dma_offset = bo ? vram_region_gpu_offset(bo->ttm.resource) : 0;
 	}
-	if (!xe_vma_has_no_bo(vma) && xe_bo_is_stolen(bo))
+	xe_walk.default_vram_pte |= XE_PPGTT_PTE_DM;
-		xe_walk.dma_offset = xe_ttm_stolen_gpu_offset(xe_bo_device(bo));
+	xe_walk.dma_offset = bo ? vram_region_gpu_offset(bo->ttm.resource) : 0;
 	if (!range)
 		xe_bo_assert_held(bo);
 		curs.size = xe_vma_size(vma);
 	}
+walk_pt:
 	ret = xe_pt_walk_range(&pt->base, pt->level,
 			       range ? range->base.itree.start : xe_vma_start(vma),
 			       range ? range->base.itree.last + 1 : xe_vma_end(vma),
 static int
 xe_pt_prepare_bind(struct xe_tile *tile, struct xe_vma *vma,
 		   struct xe_svm_range *range,
-		   struct xe_vm_pgtable_update *entries, u32 *num_entries)
+		   struct xe_vm_pgtable_update *entries,
+		   u32 *num_entries, bool invalidate_on_bind)
 {
 	int err;
 	*num_entries = 0;
-	err = xe_pt_stage_bind(tile, vma, range, entries, num_entries);
+	err = xe_pt_stage_bind(tile, vma, range, entries, num_entries,
+			       invalidate_on_bind);
 	if (!err)
 		xe_tile_assert(tile, *num_entries);
 	return err;
 }
+#if IS_ENABLED(CONFIG_DRM_XE_GPUSVM)
 static int xe_pt_svm_pre_commit(struct xe_migrate_pt_update *pt_update)
 {
 	struct xe_vm *vm = pt_update->vops->vm;
 	return 0;
 }
+#endif
 struct invalidation_fence {
 	struct xe_gt_tlb_invalidation_fence base;
 static int bind_op_prepare(struct xe_vm *vm, struct xe_tile *tile,
 			   struct xe_vm_pgtable_update_ops *pt_update_ops,
-			   struct xe_vma *vma)
+			   struct xe_vma *vma, bool invalidate_on_bind)
 {
 	u32 current_op = pt_update_ops->current_op;
 	struct xe_vm_pgtable_update_op *pt_op = &pt_update_ops->ops[current_op];
 		return err;
 	err = xe_pt_prepare_bind(tile, vma, NULL, pt_op->entries,
-				 &pt_op->num_entries);
+				 &pt_op->num_entries, invalidate_on_bind);
 	if (!err) {
 		xe_tile_assert(tile, pt_op->num_entries <=
 			       ARRAY_SIZE(pt_op->entries));
 		 * If !rebind, and scratch enabled VMs, there is a chance the scratch
 		 * PTE is already cached in the TLB so it needs to be invalidated.
 		 * On !LR VMs this is done in the ring ops preceding a batch, but on
-		 * non-faulting LR, in particular on user-space batch buffer chaining,
+		 * LR, in particular on user-space batch buffer chaining, it needs to
-		 * it needs to be done here.
+		 * be done here.
 		 */
 		if ((!pt_op->rebind && xe_vm_has_scratch(vm) &&
-		     xe_vm_in_preempt_fence_mode(vm)))
+		     xe_vm_in_lr_mode(vm)))
 			pt_update_ops->needs_invalidation = true;
 		else if (pt_op->rebind && !xe_vm_in_lr_mode(vm))
 			/* We bump also if batch_invalidate_tlb is true */
 	pt_op->rebind = BIT(tile->id) & range->tile_present;
 	err = xe_pt_prepare_bind(tile, vma, range, pt_op->entries,
-				 &pt_op->num_entries);
+				 &pt_op->num_entries, false);
 	if (!err) {
 		xe_tile_assert(tile, pt_op->num_entries <=
 			       ARRAY_SIZE(pt_op->entries));
 	switch (op->base.op) {
 	case DRM_GPUVA_OP_MAP:
-		if ((!op->map.immediate && xe_vm_in_fault_mode(vm)) ||
+		if ((!op->map.immediate && xe_vm_in_fault_mode(vm) &&
+		     !op->map.invalidate_on_bind) ||
 		    op->map.is_cpu_addr_mirror)
 			break;
-		err = bind_op_prepare(vm, tile, pt_update_ops, op->map.vma);
+		err = bind_op_prepare(vm, tile, pt_update_ops, op->map.vma,
+				      op->map.invalidate_on_bind);
 		pt_update_ops->wait_vm_kernel = true;
 		break;
 	case DRM_GPUVA_OP_REMAP:
 		if (!err && op->remap.prev) {
 			err = bind_op_prepare(vm, tile, pt_update_ops,
-					      op->remap.prev);
+					      op->remap.prev, false);
 			pt_update_ops->wait_vm_bookkeep = true;
 		}
 		if (!err && op->remap.next) {
 			err = bind_op_prepare(vm, tile, pt_update_ops,
-					      op->remap.next);
+					      op->remap.next, false);
 			pt_update_ops->wait_vm_bookkeep = true;
 		}
 		break;
 		if (xe_vma_is_cpu_addr_mirror(vma))
 			break;
-		err = bind_op_prepare(vm, tile, pt_update_ops, vma);
+		err = bind_op_prepare(vm, tile, pt_update_ops, vma, false);
 		pt_update_ops->wait_vm_kernel = true;
 		break;
 	}
 static void bind_op_commit(struct xe_vm *vm, struct xe_tile *tile,
 			   struct xe_vm_pgtable_update_ops *pt_update_ops,
 			   struct xe_vma *vma, struct dma_fence *fence,
-			   struct dma_fence *fence2)
+			   struct dma_fence *fence2, bool invalidate_on_bind)
 {
 	xe_tile_assert(tile, !xe_vma_is_cpu_addr_mirror(vma));
 	}
 	vma->tile_present |= BIT(tile->id);
 	vma->tile_staged &= ~BIT(tile->id);
+	if (invalidate_on_bind)
+		vma->tile_invalidated |= BIT(tile->id);
 	if (xe_vma_is_userptr(vma)) {
 		lockdep_assert_held_read(&vm->userptr.notifier_lock);
 		to_userptr_vma(vma)->userptr.initial_bind = true;
 			break;
 		bind_op_commit(vm, tile, pt_update_ops, op->map.vma, fence,
-			       fence2);
+			       fence2, op->map.invalidate_on_bind);
 		break;
 	case DRM_GPUVA_OP_REMAP:
 	{
 		if (op->remap.prev)
 			bind_op_commit(vm, tile, pt_update_ops, op->remap.prev,
-				       fence, fence2);
+				       fence, fence2, false);
 		if (op->remap.next)
 			bind_op_commit(vm, tile, pt_update_ops, op->remap.next,
-				       fence, fence2);
+				       fence, fence2, false);
 		break;
 	}
 	case DRM_GPUVA_OP_UNMAP:
 		if (!xe_vma_is_cpu_addr_mirror(vma))
 			bind_op_commit(vm, tile, pt_update_ops, vma, fence,
-				       fence2);
+				       fence2, false);
 		break;
 	}
 	case DRM_GPUVA_OP_DRIVER:
 	.pre_commit = xe_pt_userptr_pre_commit,
 };
+#if IS_ENABLED(CONFIG_DRM_XE_GPUSVM)
 static const struct xe_migrate_pt_update_ops svm_migrate_ops = {
 	.populate = xe_vm_populate_pgtable,
 	.clear = xe_migrate_clear_pgtable_callback,
 	.pre_commit = xe_pt_svm_pre_commit,
 };
+#else
+static const struct xe_migrate_pt_update_ops svm_migrate_ops;
+#endif
 /**
  * xe_pt_update_ops_run() - Run PT update operations

drivers/gpu/drm/xe/xe_query.c+1−1

@@ -340,7 +340,7 @@ static int query_config(struct xe_device xe, struct drm_xe_device_query query) · 339 unmodified lines
340	if (xe_device_get_root_tile(xe)->mem.vram.usable_size)	340	if (xe_device_get_root_tile(xe)->mem.vram.usable_size)
341	config->info[DRM_XE_QUERY_CONFIG_FLAGS] \|=	341	config->info[DRM_XE_QUERY_CONFIG_FLAGS] \|=
342	DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM;	342	DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM;
343	if (xe->info.has_usm && IS_ENABLED(CONFIG_DRM_GPUSVM))	343	if (xe->info.has_usm && IS_ENABLED(CONFIG_DRM_XE_GPUSVM))
344	config->info[DRM_XE_QUERY_CONFIG_FLAGS] \|=	344	config->info[DRM_XE_QUERY_CONFIG_FLAGS] \|=
345	DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR;	345	DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR;
346	config->info[DRM_XE_QUERY_CONFIG_FLAGS] \|=	346	config->info[DRM_XE_QUERY_CONFIG_FLAGS] \|=

drivers/gpu/drm/xe/xe_reg_sr.c+3−0

@@ -173,6 +173,9 @@ void xe_reg_sr_apply_mmio(struct xe_reg_sr sr, struct xe_gt gt) · 172 unmodified lines
173	if (xa_empty(&sr->xa))	173	if (xa_empty(&sr->xa))
174	return;	174	return;
175		175
		176	if (IS_SRIOV_VF(gt_to_xe(gt)))
		177	return;
		178
176	xe_gt_dbg(gt, "Applying %s save-restore MMIOs\n", sr->name);	179	xe_gt_dbg(gt, "Applying %s save-restore MMIOs\n", sr->name);
177		180
178	fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL);	181	fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL);

drivers/gpu/drm/xe/xe_ring_ops_types.h+1−1

@@ -8,7 +8,7 @@ · 7 unmodified lines
8		8
9	struct xe_sched_job;	9	struct xe_sched_job;
10		10
11	#define MAX_JOB_SIZE_DW 48	11	#define MAX_JOB_SIZE_DW 58
12	#define MAX_JOB_SIZE_BYTES (MAX_JOB_SIZE_DW * 4)	12	#define MAX_JOB_SIZE_BYTES (MAX_JOB_SIZE_DW * 4)
13		13
14	/**	14	/**

drivers/gpu/drm/xe/xe_rtp.c+0−3

@@ -258,9 +258,6 @@ void xe_rtp_process_to_sr(struct xe_rtp_process_ctx *ctx, · 257 unmodified lines
258		258
259	rtp_get_context(ctx, &hwe, &gt, &xe);	259	rtp_get_context(ctx, &hwe, &gt, &xe);
260		260
261	if (IS_SRIOV_VF(xe))
262	return;
263
264	xe_assert(xe, entries);	261	xe_assert(xe, entries);
265		262
266	for (entry = entries; entry - entries < n_entries; entry++) {	263	for (entry = entries; entry - entries < n_entries; entry++) {

drivers/gpu/drm/xe/xe_sa.c+2−1

 	bo = xe_managed_bo_create_pin_map(xe, tile, size,
 					  XE_BO_FLAG_VRAM_IF_DGFX(tile) |
 					  XE_BO_FLAG_GGTT |
-					  XE_BO_FLAG_GGTT_INVALIDATE);
+					  XE_BO_FLAG_GGTT_INVALIDATE |
+					  XE_BO_FLAG_PINNED_NORESTORE);
 	if (IS_ERR(bo)) {
 		drm_err(&xe->drm, "Failed to prepare %uKiB BO for SA manager (%pe)\n",
 			size / SZ_1K, bo);

drivers/gpu/drm/xe/xe_survivability_mode.c+50−19

 #include <linux/pci.h>
 #include <linux/sysfs.h>
+#include "xe_configfs.h"
 #include "xe_device.h"
 #include "xe_gt.h"
 #include "xe_heci_gsc.h"
  * This is implemented by loading the driver with bare minimum (no drm card) to allow the firmware
  * to be flashed through mei and collect telemetry. The driver's probe flow is modified
  * such that it enters survivability mode when pcode initialization is incomplete and boot status
- * denotes a failure. The driver then  populates the survivability_mode PCI sysfs indicating
+ * denotes a failure.
- * survivability mode and provides additional information required for debug
  *
- * KMD exposes below admin-only readable sysfs in survivability mode
+ * Survivability mode can also be entered manually using the survivability mode attribute available
+ * through configfs which is beneficial in several usecases. It can be used to address scenarios
+ * where pcode does not detect failure or for validation purposes. It can also be used in
+ * In-Field-Repair (IFR) to repair a single card without impacting the other cards in a node.
  *
- * device/survivability_mode: The presence of this file indicates that the card is in survivability
+ * Use below command enable survivability mode manually::
- *			      mode. Also, provides additional information on why the driver entered
- *			      survivability mode.
  *
- *			      Capability Information - Provides boot status
+ *	# echo 1 > /sys/kernel/config/xe/0000:03:00.0/survivability_mode
- *			      Postcode Information   - Provides information about the failure
+ *
- *			      Overflow Information   - Provides history of previous failures
+ * Refer :ref:`xe_configfs` for more details on how to use configfs
- *			      Auxiliary Information  - Certain failures may have information in
+ *
- *						       addition to postcode information
+ * Survivability mode is indicated by the below admin-only readable sysfs which provides additional
+ * debug information::
+ *
+ *	/sys/bus/pci/devices/<device>/surivability_mode
+ *
+ * Capability Information:
+ *	Provides boot status
+ * Postcode Information:
+ *	Provides information about the failure
+ * Overflow Information
+ *	Provides history of previous failures
+ * Auxiliary Information
+ *	Certain failures may have information in addition to postcode information
  */
 static u32 aux_history_offset(u32 reg_value)
 	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
 	struct device *dev = &pdev->dev;
+	xe_configfs_clear_survivability_mode(pdev);
 	sysfs_remove_file(&dev->kobj, &dev_attr_survivability_mode.attr);
 }
 	return xe->survivability.mode;
 }
-/*
+/**
- * survivability_mode_requested - check if it's possible to enable
+ * xe_survivability_mode_is_requested - check if it's possible to enable survivability
- * survivability mode and that was requested by firmware
+ *					mode that was requested by firmware or userspace
+ * @xe: xe device instance
  *
- * This function reads the boot status from Pcode.
+ * This function reads configfs and  boot status from Pcode.
  *
  * Return: true if platform support is available and boot status indicates
- * failure, false otherwise.
+ * failure or if survivability mode is requested, false otherwise.
  */
-static bool survivability_mode_requested(struct xe_device *xe)
+bool xe_survivability_mode_is_requested(struct xe_device *xe)
 {
 	struct xe_survivability *survivability = &xe->survivability;
 	struct xe_mmio *mmio = xe_root_tile_mmio(xe);
+	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
 	u32 data;
+	bool survivability_mode;
-	if (!IS_DGFX(xe) || xe->info.platform < XE_BATTLEMAGE || IS_SRIOV_VF(xe))
+	if (!IS_DGFX(xe) || IS_SRIOV_VF(xe))
 		return false;
+	survivability_mode = xe_configfs_get_survivability_mode(pdev);
+	if (xe->info.platform < XE_BATTLEMAGE) {
+		if (survivability_mode) {
+			dev_err(&pdev->dev, "Survivability Mode is not supported on this card\n");
+			xe_configfs_clear_survivability_mode(pdev);
+		}
+		return false;
+	}
+	/* Enable survivability mode if set via configfs */
+	if (survivability_mode)
+		return true;
 	data = xe_mmio_read32(mmio, PCODE_SCRATCH(0));
 	survivability->boot_status = REG_FIELD_GET(BOOT_STATUS, data);
 	struct xe_survivability_info *info;
 	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
-	if (!survivability_mode_requested(xe))
+	if (!xe_survivability_mode_is_requested(xe))
 		return 0;
 	survivability->size = MAX_SCRATCH_MMIO;

drivers/gpu/drm/xe/xe_survivability_mode.h+1−0

@@ -12,5 +12,6 @@ struct xe_device; · 11 unmodified lines
12		12
13	int xe_survivability_mode_enable(struct xe_device *xe);	13	int xe_survivability_mode_enable(struct xe_device *xe);
14	bool xe_survivability_mode_is_enabled(struct xe_device *xe);	14	bool xe_survivability_mode_is_enabled(struct xe_device *xe);
		15	bool xe_survivability_mode_is_requested(struct xe_device *xe);
15		16
16	#endif /* _XE_SURVIVABILITY_MODE_H_ */	17	#endif /* _XE_SURVIVABILITY_MODE_H_ */

drivers/gpu/drm/xe/xe_svm.c+21−2

  */
 #include "xe_bo.h"
+#include "xe_gt_stats.h"
 #include "xe_gt_tlb_invalidation.h"
 #include "xe_migrate.h"
 #include "xe_module.h"
 	up_write(&vm->lock);
 }
+#if IS_ENABLED(CONFIG_DRM_XE_DEVMEM_MIRROR)
 static struct xe_vram_region *page_to_vr(struct page *page)
 {
 	return container_of(page_pgmap(page), struct xe_vram_region, pagemap);
 	.copy_to_ram = xe_svm_copy_to_ram,
 };
+#endif
 static const struct drm_gpusvm_ops gpusvm_ops = {
 	.range_alloc = xe_svm_range_alloc,
 	.range_free = xe_svm_range_free,
 	return (range->tile_present & ~range->tile_invalidated) & BIT(tile->id);
 }
+#if IS_ENABLED(CONFIG_DRM_XE_DEVMEM_MIRROR)
 static struct xe_vram_region *tile_to_vr(struct xe_tile *tile)
 {
 	return &tile->mem.vram;
 	return err;
 }
+#else
+static int xe_svm_alloc_vram(struct xe_vm *vm, struct xe_tile *tile,
+			     struct xe_svm_range *range,
+			     const struct drm_gpusvm_ctx *ctx)
+{
+	return -EOPNOTSUPP;
+}
+#endif
 /**
  * xe_svm_handle_pagefault() - SVM handle page fault
  * @vm: The VM.
  * @vma: The CPU address mirror VMA.
- * @tile: The tile upon the fault occurred.
+ * @gt: The gt upon the fault occurred.
  * @fault_addr: The GPU fault address.
  * @atomic: The fault atomic access bit.
  *
  * Return: 0 on success, negative error code on error.
  */
 int xe_svm_handle_pagefault(struct xe_vm *vm, struct xe_vma *vma,
-			    struct xe_tile *tile, u64 fault_addr,
+			    struct xe_gt *gt, u64 fault_addr,
 			    bool atomic)
 {
 	struct drm_gpusvm_ctx ctx = {
 	struct drm_gpusvm_range *r;
 	struct drm_exec exec;
 	struct dma_fence *fence;
+	struct xe_tile *tile = gt_to_tile(gt);
 	ktime_t end = 0;
 	int err;
 	lockdep_assert_held_write(&vm->lock);
 	xe_assert(vm->xe, xe_vma_is_cpu_addr_mirror(vma));
+	xe_gt_stats_incr(gt, XE_GT_STATS_ID_SVM_PAGEFAULT_COUNT, 1);
 retry:
 	/* Always process UNMAPs first so view SVM ranges is current */
 	err = xe_svm_garbage_collector(vm);
 }
 #if IS_ENABLED(CONFIG_DRM_XE_DEVMEM_MIRROR)
 static struct drm_pagemap_device_addr
 xe_drm_pagemap_device_map(struct drm_pagemap *dpagemap,
 			  struct device *dev,

drivers/gpu/drm/xe/xe_svm.h+57−23

@@ -6,16 +6,19 @@ · 5 unmodified lines
6	#ifndef _XE_SVM_H_	6	#ifndef _XE_SVM_H_
7	#define _XE_SVM_H_	7	#define _XE_SVM_H_
8		8
		9	#if IS_ENABLED(CONFIG_DRM_XE_GPUSVM)
		10
9	#include <drm/drm_pagemap.h>	11	#include <drm/drm_pagemap.h>
10	#include <drm/drm_gpusvm.h>	12	#include <drm/drm_gpusvm.h>
11		13
12	#define XE_INTERCONNECT_VRAM DRM_INTERCONNECT_DRIVER	14	#define XE_INTERCONNECT_VRAM DRM_INTERCONNECT_DRIVER
13		15
14	struct xe_bo;	16	struct xe_bo;
15	struct xe_vram_region;	17	struct xe_gt;
16	struct xe_tile;	18	struct xe_tile;
17	struct xe_vm;	19	struct xe_vm;
18	struct xe_vma;	20	struct xe_vma;
		21	struct xe_vram_region;
19		22
20	/** struct xe_svm_range - SVM range */	23	/** struct xe_svm_range - SVM range */
21	struct xe_svm_range {	24	struct xe_svm_range {
@@ -43,7 +46,6 @@ struct xe_svm_range { · 21 unmodified lines
43	u8 skip_migrate :1;	46	u8 skip_migrate :1;
44	};	47	};
45		48
46	#if IS_ENABLED(CONFIG_DRM_GPUSVM)
47	/**	49	/**
48	* xe_svm_range_pages_valid() - SVM range pages valid	50	* xe_svm_range_pages_valid() - SVM range pages valid
49	* @range: SVM range	51	* @range: SVM range
@@ -64,7 +66,7 @@ void xe_svm_fini(struct xe_vm *vm); · 14 unmodified lines
64	void xe_svm_close(struct xe_vm *vm);	66	void xe_svm_close(struct xe_vm *vm);
65		67
66	int xe_svm_handle_pagefault(struct xe_vm vm, struct xe_vma vma,	68	int xe_svm_handle_pagefault(struct xe_vm vm, struct xe_vma vma,
67	struct xe_tile *tile, u64 fault_addr,	69	struct xe_gt *gt, u64 fault_addr,
68	bool atomic);	70	bool atomic);
69		71
70	bool xe_svm_has_mapping(struct xe_vm *vm, u64 start, u64 end);	72	bool xe_svm_has_mapping(struct xe_vm *vm, u64 start, u64 end);
@@ -72,7 +74,50 @@ bool xe_svm_has_mapping(struct xe_vm *vm, u64 start, u64 end); · 1 unmodified line
72	int xe_svm_bo_evict(struct xe_bo *bo);	74	int xe_svm_bo_evict(struct xe_bo *bo);
73		75
74	void xe_svm_range_debug(struct xe_svm_range range, const char operation);	76	void xe_svm_range_debug(struct xe_svm_range range, const char operation);
		77
		78	/**
		79	* xe_svm_range_has_dma_mapping() - SVM range has DMA mapping
		80	* @range: SVM range
		81	*
		82	* Return: True if SVM range has a DMA mapping, False otherwise
		83	*/
		84	static inline bool xe_svm_range_has_dma_mapping(struct xe_svm_range *range)
		85	{
		86	lockdep_assert_held(&range->base.gpusvm->notifier_lock);
		87	return range->base.flags.has_dma_mapping;
		88	}
		89
		90	#define xe_svm_assert_in_notifier(vm__) \
		91	lockdep_assert_held_write(&(vm__)->svm.gpusvm.notifier_lock)
		92
		93	#define xe_svm_notifier_lock(vm__) \
		94	drm_gpusvm_notifier_lock(&(vm__)->svm.gpusvm)
		95
		96	#define xe_svm_notifier_unlock(vm__) \
		97	drm_gpusvm_notifier_unlock(&(vm__)->svm.gpusvm)
		98
75	#else	99	#else
		100	#include <linux/interval_tree.h>
		101
		102	struct drm_pagemap_device_addr;
		103	struct xe_bo;
		104	struct xe_gt;
		105	struct xe_vm;
		106	struct xe_vma;
		107	struct xe_tile;
		108	struct xe_vram_region;
		109
		110	#define XE_INTERCONNECT_VRAM 1
		111
		112	struct xe_svm_range {
		113	struct {
		114	struct interval_tree_node itree;
		115	const struct drm_pagemap_device_addr *dma_addr;
		116	} base;
		117	u32 tile_present;
		118	u32 tile_invalidated;
		119	};
		120
76	static inline bool xe_svm_range_pages_valid(struct xe_svm_range *range)	121	static inline bool xe_svm_range_pages_valid(struct xe_svm_range *range)
77	{	122	{
78	return false;	123	return false;
@@ -102,7 +147,7 @@ void xe_svm_close(struct xe_vm *vm) · 23 unmodified lines
102		147
103	static inline	148	static inline
104	int xe_svm_handle_pagefault(struct xe_vm vm, struct xe_vma vma,	149	int xe_svm_handle_pagefault(struct xe_vm vm, struct xe_vma vma,
105	struct xe_tile *tile, u64 fault_addr,	150	struct xe_gt *gt, u64 fault_addr,
106	bool atomic)	151	bool atomic)
107	{	152	{
108	return 0;	153	return 0;
@@ -124,27 +169,16 @@ static inline · 15 unmodified lines
124	void xe_svm_range_debug(struct xe_svm_range range, const char operation)	169	void xe_svm_range_debug(struct xe_svm_range range, const char operation)
125	{	170	{
126	}	171	}
127	#endif
128		172
129	/**	173	#define xe_svm_assert_in_notifier(...) do {} while (0)
130	* xe_svm_range_has_dma_mapping() - SVM range has DMA mapping	174	#define xe_svm_range_has_dma_mapping(...) false
131	* @range: SVM range	175
132	*	176	static inline void xe_svm_notifier_lock(struct xe_vm *vm)
133	* Return: True if SVM range has a DMA mapping, False otherwise
134	*/
135	static inline bool xe_svm_range_has_dma_mapping(struct xe_svm_range *range)
136	{	177	{
137	lockdep_assert_held(&range->base.gpusvm->notifier_lock);
138	return range->base.flags.has_dma_mapping;
139	}	178	}
140		179
141	#define xe_svm_assert_in_notifier(vm__) \	180	static inline void xe_svm_notifier_unlock(struct xe_vm *vm)
142	lockdep_assert_held_write(&(vm__)->svm.gpusvm.notifier_lock)	181	{
143		182	}
144	#define xe_svm_notifier_lock(vm__) \	183	#endif
145	drm_gpusvm_notifier_lock(&(vm__)->svm.gpusvm)
146
147	#define xe_svm_notifier_unlock(vm__) \
148	drm_gpusvm_notifier_unlock(&(vm__)->svm.gpusvm)
149
150	#endif	184	#endif

drivers/gpu/drm/xe/xe_uc_fw.c+55−39

@@ -92,6 +92,8 @@ · 91 unmodified lines
92		92
93	struct uc_fw_entry {	93	struct uc_fw_entry {
94	enum xe_platform platform;	94	enum xe_platform platform;
		95	enum xe_gt_type gt_type;
		96
95	struct {	97	struct {
96	const char *path;	98	const char *path;
97	u16 major;	99	u16 major;
@@ -106,32 +108,37 @@ struct fw_blobs_by_type { · 8 unmodified lines
106	u32 count;	108	u32 count;
107	};	109	};
108		110
109	#define XE_GUC_FIRMWARE_DEFS(fw_def, mmp_ver, major_ver) \	111	/*
110	fw_def(BATTLEMAGE, major_ver(xe, guc, bmg, 70, 29, 2)) \	112	* Add an "ANY" define just to convey the meaning it's given here.
111	fw_def(LUNARLAKE, major_ver(xe, guc, lnl, 70, 29, 2)) \	113	*/
112	fw_def(METEORLAKE, major_ver(i915, guc, mtl, 70, 29, 2)) \	114	#define XE_GT_TYPE_ANY XE_GT_TYPE_UNINITIALIZED
113	fw_def(DG2, major_ver(i915, guc, dg2, 70, 29, 2)) \	115
114	fw_def(DG1, major_ver(i915, guc, dg1, 70, 29, 2)) \	116	#define XE_GUC_FIRMWARE_DEFS(fw_def, mmp_ver, major_ver) \
115	fw_def(ALDERLAKE_N, major_ver(i915, guc, tgl, 70, 29, 2)) \	117	fw_def(BATTLEMAGE, GT_TYPE_ANY, major_ver(xe, guc, bmg, 70, 44, 1)) \
116	fw_def(ALDERLAKE_P, major_ver(i915, guc, adlp, 70, 29, 2)) \	118	fw_def(LUNARLAKE, GT_TYPE_ANY, major_ver(xe, guc, lnl, 70, 44, 1)) \
117	fw_def(ALDERLAKE_S, major_ver(i915, guc, tgl, 70, 29, 2)) \	119	fw_def(METEORLAKE, GT_TYPE_ANY, major_ver(i915, guc, mtl, 70, 44, 1)) \
118	fw_def(ROCKETLAKE, major_ver(i915, guc, tgl, 70, 29, 2)) \	120	fw_def(DG2, GT_TYPE_ANY, major_ver(i915, guc, dg2, 70, 44, 1)) \
119	fw_def(TIGERLAKE, major_ver(i915, guc, tgl, 70, 29, 2))	121	fw_def(DG1, GT_TYPE_ANY, major_ver(i915, guc, dg1, 70, 44, 1)) \
		122	fw_def(ALDERLAKE_N, GT_TYPE_ANY, major_ver(i915, guc, tgl, 70, 44, 1)) \
		123	fw_def(ALDERLAKE_P, GT_TYPE_ANY, major_ver(i915, guc, adlp, 70, 44, 1)) \
		124	fw_def(ALDERLAKE_S, GT_TYPE_ANY, major_ver(i915, guc, tgl, 70, 44, 1)) \
		125	fw_def(ROCKETLAKE, GT_TYPE_ANY, major_ver(i915, guc, tgl, 70, 44, 1)) \
		126	fw_def(TIGERLAKE, GT_TYPE_ANY, major_ver(i915, guc, tgl, 70, 44, 1))
120		127
121	#define XE_HUC_FIRMWARE_DEFS(fw_def, mmp_ver, no_ver) \	128	#define XE_HUC_FIRMWARE_DEFS(fw_def, mmp_ver, no_ver) \
122	fw_def(BATTLEMAGE, no_ver(xe, huc, bmg)) \	129	fw_def(BATTLEMAGE, GT_TYPE_ANY, no_ver(xe, huc, bmg)) \
123	fw_def(LUNARLAKE, no_ver(xe, huc, lnl)) \	130	fw_def(LUNARLAKE, GT_TYPE_ANY, no_ver(xe, huc, lnl)) \
124	fw_def(METEORLAKE, no_ver(i915, huc_gsc, mtl)) \	131	fw_def(METEORLAKE, GT_TYPE_ANY, no_ver(i915, huc_gsc, mtl)) \
125	fw_def(DG1, no_ver(i915, huc, dg1)) \	132	fw_def(DG1, GT_TYPE_ANY, no_ver(i915, huc, dg1)) \
126	fw_def(ALDERLAKE_P, no_ver(i915, huc, tgl)) \	133	fw_def(ALDERLAKE_P, GT_TYPE_ANY, no_ver(i915, huc, tgl)) \
127	fw_def(ALDERLAKE_S, no_ver(i915, huc, tgl)) \	134	fw_def(ALDERLAKE_S, GT_TYPE_ANY, no_ver(i915, huc, tgl)) \
128	fw_def(ROCKETLAKE, no_ver(i915, huc, tgl)) \	135	fw_def(ROCKETLAKE, GT_TYPE_ANY, no_ver(i915, huc, tgl)) \
129	fw_def(TIGERLAKE, no_ver(i915, huc, tgl))	136	fw_def(TIGERLAKE, GT_TYPE_ANY, no_ver(i915, huc, tgl))
130		137
131	/* for the GSC FW we match the compatibility version and not the release one */	138	/* for the GSC FW we match the compatibility version and not the release one */
132	#define XE_GSC_FIRMWARE_DEFS(fw_def, major_ver) \	139	#define XE_GSC_FIRMWARE_DEFS(fw_def, major_ver) \
133	fw_def(LUNARLAKE, major_ver(xe, gsc, lnl, 104, 1, 0)) \	140	fw_def(LUNARLAKE, GT_TYPE_ANY, major_ver(xe, gsc, lnl, 104, 1, 0)) \
134	fw_def(METEORLAKE, major_ver(i915, gsc, mtl, 102, 1, 0))	141	fw_def(METEORLAKE, GT_TYPE_ANY, major_ver(i915, gsc, mtl, 102, 1, 0))
135		142
136	#define MAKE_FW_PATH(dir__, uc__, shortname__, version__) \	143	#define MAKE_FW_PATH(dir__, uc__, shortname__, version__) \
137	__stringify(dir__) "/" __stringify(shortname__) "_" __stringify(uc__) version__ ".bin"	144	__stringify(dir__) "/" __stringify(shortname__) "_" __stringify(uc__) version__ ".bin"
@@ -159,12 +166,13 @@ struct fw_blobs_by_type { · 21 unmodified lines
159	a, b, c }	166	a, b, c }
160		167
161	/* All blobs need to be declared via MODULE_FIRMWARE() */	168	/* All blobs need to be declared via MODULE_FIRMWARE() */
162	#define XE_UC_MODULE_FIRMWARE(platform__, fw_filename) \	169	#define XE_UC_MODULE_FIRMWARE(platform__, gt_type__, fw_filename) \
163	MODULE_FIRMWARE(fw_filename);	170	MODULE_FIRMWARE(fw_filename);
164		171
165	#define XE_UC_FW_ENTRY(platform__, entry__) \	172	#define XE_UC_FW_ENTRY(platform__, gt_type__, entry__) \
166	{ \	173	{ \
167	.platform = XE_ ## platform__, \	174	.platform = XE_ ## platform__, \
		175	.gt_type = XE_ ## gt_type__, \
168	entry__, \	176	entry__, \
169	},	177	},
170		178
@@ -222,30 +230,38 @@ uc_fw_auto_select(struct xe_device xe, struct xe_uc_fw uc_fw) · 51 unmodified lines
222	[XE_UC_FW_TYPE_HUC] = { entries_huc, ARRAY_SIZE(entries_huc) },	230	[XE_UC_FW_TYPE_HUC] = { entries_huc, ARRAY_SIZE(entries_huc) },
223	[XE_UC_FW_TYPE_GSC] = { entries_gsc, ARRAY_SIZE(entries_gsc) },	231	[XE_UC_FW_TYPE_GSC] = { entries_gsc, ARRAY_SIZE(entries_gsc) },
224	};	232	};
225	static const struct uc_fw_entry *entries;	233	struct xe_gt *gt = uc_fw_to_gt(uc_fw);
226	enum xe_platform p = xe->info.platform;	234	enum xe_platform p = xe->info.platform;
		235	const struct uc_fw_entry *entries;
227	u32 count;	236	u32 count;
228	int i;	237	int i;
229		238
230	xe_assert(xe, uc_fw->type < ARRAY_SIZE(blobs_all));	239	xe_gt_assert(gt, uc_fw->type < ARRAY_SIZE(blobs_all));
		240	xe_gt_assert(gt, gt->info.type != XE_GT_TYPE_UNINITIALIZED);
		241
231	entries = blobs_all[uc_fw->type].entries;	242	entries = blobs_all[uc_fw->type].entries;
232	count = blobs_all[uc_fw->type].count;	243	count = blobs_all[uc_fw->type].count;
233		244
234	for (i = 0; i < count && p <= entries[i].platform; i++) {	245	for (i = 0; i < count && p <= entries[i].platform; i++) {
235	if (p == entries[i].platform) {	246	if (p != entries[i].platform)
236	uc_fw->path = entries[i].path;	247	continue;
237	uc_fw->versions.wanted.major = entries[i].major;	248
238	uc_fw->versions.wanted.minor = entries[i].minor;	249	if (entries[i].gt_type != XE_GT_TYPE_ANY &&
239	uc_fw->versions.wanted.patch = entries[i].patch;	250	entries[i].gt_type != gt->info.type)
240	uc_fw->full_ver_required = entries[i].full_ver_required;	251	continue;
241		252
242	if (uc_fw->type == XE_UC_FW_TYPE_GSC)	253	uc_fw->path = entries[i].path;
243	uc_fw->versions.wanted_type = XE_UC_FW_VER_COMPATIBILITY;	254	uc_fw->versions.wanted.major = entries[i].major;
244	else	255	uc_fw->versions.wanted.minor = entries[i].minor;
245	uc_fw->versions.wanted_type = XE_UC_FW_VER_RELEASE;	256	uc_fw->versions.wanted.patch = entries[i].patch;
246		257	uc_fw->full_ver_required = entries[i].full_ver_required;
247	break;	258
248	}	259	if (uc_fw->type == XE_UC_FW_TYPE_GSC)
		260	uc_fw->versions.wanted_type = XE_UC_FW_VER_COMPATIBILITY;
		261	else
		262	uc_fw->versions.wanted_type = XE_UC_FW_VER_RELEASE;
		263
		264	break;
249	}	265	}
250	}	266	}
251		267

drivers/gpu/drm/xe/xe_vm.c+29−10

 		return -EINVAL;
 	if (XE_IOCTL_DBG(xe, args->flags & DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE &&
-			 args->flags & DRM_XE_VM_CREATE_FLAG_FAULT_MODE))
+			 args->flags & DRM_XE_VM_CREATE_FLAG_FAULT_MODE &&
+			 !xe->info.needs_scratch))
 		return -EINVAL;
 	if (XE_IOCTL_DBG(xe, !(args->flags & DRM_XE_VM_CREATE_FLAG_LR_MODE) &&
 }
 #endif
+static bool __xe_vm_needs_clear_scratch_pages(struct xe_vm *vm, u32 bind_flags)
+{
+	if (!xe_vm_in_fault_mode(vm))
+		return false;
+	if (!xe_vm_has_scratch(vm))
+		return false;
+	if (bind_flags & DRM_XE_VM_BIND_FLAG_IMMEDIATE)
+		return false;
+	return true;
+}
 /*
  * Create operations list from IOCTL arguments, setup operations fields so parse
  * and commit steps are decoupled from IOCTL arguments. This step can fail.
 				DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR;
 			op->map.dumpable = flags & DRM_XE_VM_BIND_FLAG_DUMPABLE;
 			op->map.pat_index = pat_index;
+			op->map.invalidate_on_bind =
+				__xe_vm_needs_clear_scratch_pages(vm, flags);
 		} else if (__op->op == DRM_GPUVA_OP_PREFETCH) {
 			op->prefetch.region = prefetch_region;
 		}
 				return PTR_ERR(vma);
 			op->map.vma = vma;
-			if ((op->map.immediate || !xe_vm_in_fault_mode(vm)) &&
+			if (((op->map.immediate || !xe_vm_in_fault_mode(vm)) &&
-			    !op->map.is_cpu_addr_mirror)
+			     !op->map.is_cpu_addr_mirror) ||
+			    op->map.invalidate_on_bind)
 				xe_vma_ops_incr_pt_update_ops(vops,
 							      op->tile_mask);
 			break;
 	switch (op->base.op) {
 	case DRM_GPUVA_OP_MAP:
-		err = vma_lock_and_validate(exec, op->map.vma,
+		if (!op->map.invalidate_on_bind)
-					    !xe_vm_in_fault_mode(vm) ||
+			err = vma_lock_and_validate(exec, op->map.vma,
-					    op->map.immediate);
+						    !xe_vm_in_fault_mode(vm) ||
+						    op->map.immediate);
 		break;
 	case DRM_GPUVA_OP_REMAP:
 		err = check_ufence(gpuva_to_vma(op->base.remap.unmap->va));
 		if (XE_IOCTL_DBG(xe, is_cpu_addr_mirror &&
 				 (!xe_vm_in_fault_mode(vm) ||
-				 !IS_ENABLED(CONFIG_DRM_GPUSVM)))) {
+				 !IS_ENABLED(CONFIG_DRM_XE_GPUSVM)))) {
 			err = -EINVAL;
 			goto free_bind_ops;
 		}
 				 XE_64K_PAGE_MASK) ||
 		    XE_IOCTL_DBG(xe, addr & XE_64K_PAGE_MASK) ||
 		    XE_IOCTL_DBG(xe, range & XE_64K_PAGE_MASK)) {
-			return  -EINVAL;
+			return -EINVAL;
 		}
 	}
 	if (bo->cpu_caching) {
 		if (XE_IOCTL_DBG(xe, coh_mode == XE_COH_NONE &&
 				 bo->cpu_caching == DRM_XE_GEM_CPU_CACHING_WB)) {
-			return  -EINVAL;
+			return -EINVAL;
 		}
 	} else if (XE_IOCTL_DBG(xe, coh_mode == XE_COH_NONE)) {
 		/*
 		 * how it was mapped on the CPU. Just assume is it
 		 * potentially cached on CPU side.
 		 */
-		return  -EINVAL;
+		return -EINVAL;
 	}
 	/* If a BO is protected it can only be mapped if the key is still valid */

drivers/gpu/drm/xe/xe_vm_types.h+2−0

 	bool is_cpu_addr_mirror;
 	/** @dumpable: whether BO is dumped on GPU hang */
 	bool dumpable;
+	/** @invalidate: invalidate the VMA before bind */
+	bool invalidate_on_bind;
 	/** @pat_index: The pat index to use for this operation. */
 	u16 pat_index;
 };

drivers/gpu/drm/xe/xe_vram.c+4−1

  */
 static void resize_vram_bar(struct xe_device *xe)
 {
-	u64 force_vram_bar_size = xe_modparam.force_vram_bar_size;
+	int force_vram_bar_size = xe_modparam.force_vram_bar_size;
 	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
 	struct pci_bus *root = pdev->bus;
 	resource_size_t current_size;
 	if (!bar_size_mask)
 		return;
+	if (force_vram_bar_size < 0)
+		return;
 	/* set to a specific size? */
 	if (force_vram_bar_size) {
 		u32 bar_size_bit;

drivers/gpu/drm/xe/xe_wa.c+12−0

@@ -230,6 +230,18 @@ static const struct xe_rtp_entry_sr gt_was[] = { · 229 unmodified lines
230	XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),	230	XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
231	},	231	},
232		232
		233	/* Xe2_HPG */
		234
		235	{ XE_RTP_NAME("16025250150"),
		236	XE_RTP_RULES(GRAPHICS_VERSION(2001)),
		237	XE_RTP_ACTIONS(SET(LSN_VC_REG2,
		238	LSN_LNI_WGT(1) \|
		239	LSN_LNE_WGT(1) \|
		240	LSN_DIM_X_WGT(1) \|
		241	LSN_DIM_Y_WGT(1) \|
		242	LSN_DIM_Z_WGT(1)))
		243	},
		244
233	/* Xe2_HPM */	245	/* Xe2_HPM */
234		246
235	{ XE_RTP_NAME("16021867713"),	247	{ XE_RTP_NAME("16021867713"),

drivers/gpu/drm/xe/xe_wa_oob.rules+2−0

@@ -57,3 +57,5 @@ no_media_l3 MEDIA_VERSION(3000) · 56 unmodified lines
57	GRAPHICS_VERSION(1260), GRAPHICS_STEP(A0, B0)	57	GRAPHICS_VERSION(1260), GRAPHICS_STEP(A0, B0)
58	16023105232 GRAPHICS_VERSION_RANGE(2001, 3001)	58	16023105232 GRAPHICS_VERSION_RANGE(2001, 3001)
59	MEDIA_VERSION_RANGE(1301, 3000)	59	MEDIA_VERSION_RANGE(1301, 3000)
		60	16026508708 GRAPHICS_VERSION_RANGE(1200, 3001)
		61	MEDIA_VERSION_RANGE(1300, 3000)

include/uapi/drm/xe_drm.h+5−1

  * struct drm_xe_vm_create - Input of &DRM_IOCTL_XE_VM_CREATE
  *
  * The @flags can be:
- *  - %DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE
+ *  - %DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE - Map the whole virtual address
+ *    space of the VM to scratch page. A vm_bind would overwrite the scratch
+ *    page mapping. This flag is mutually exclusive with the
+ *    %DRM_XE_VM_CREATE_FLAG_FAULT_MODE flag, with an exception of on x2 and
+ *    xe3 platform.
  *  - %DRM_XE_VM_CREATE_FLAG_LR_MODE - An LR, or Long Running VM accepts
  *    exec submissions to its exec_queues that don't have an upper time
  *    limit on the job execution time. But exec submissions to these

Merge tag 'drm-xe-next-2025-04-17' of https://gitlab.freedesktop.org/drm/xe/kernel into drm-next

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