The PASID Capability and Control registers are both 16 bits wide. Use 16-bit wide constants in field names to match the register width. No functional change intended.
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| @@ -930,12 +930,12 @@ · 929 unmodified lines | |||
| 930 | 930 | ||
| 931 | /* Process Address Space ID */ | 931 | /* Process Address Space ID */ |
| 932 | #define PCI_PASID_CAP 0x04 /* PASID feature register */ | 932 | #define PCI_PASID_CAP 0x04 /* PASID feature register */ |
| 933 | #define PCI_PASID_CAP_EXEC 0x02 /* Exec permissions Supported */ | 933 | #define PCI_PASID_CAP_EXEC 0x0002 /* Exec permissions Supported */ |
| 934 | #define PCI_PASID_CAP_PRIV 0x04 /* Privilege Mode Supported */ | 934 | #define PCI_PASID_CAP_PRIV 0x0004 /* Privilege Mode Supported */ |
| 935 | #define PCI_PASID_CTRL 0x06 /* PASID control register */ | 935 | #define PCI_PASID_CTRL 0x06 /* PASID control register */ |
| 936 | #define PCI_PASID_CTRL_ENABLE 0x01 /* Enable bit */ | 936 | #define PCI_PASID_CTRL_ENABLE 0x0001 /* Enable bit */ |
| 937 | #define PCI_PASID_CTRL_EXEC 0x02 /* Exec permissions Enable */ | 937 | #define PCI_PASID_CTRL_EXEC 0x0002 /* Exec permissions Enable */ |
| 938 | #define PCI_PASID_CTRL_PRIV 0x04 /* Privilege Mode Enable */ | 938 | #define PCI_PASID_CTRL_PRIV 0x0004 /* Privilege Mode Enable */ |
| 939 | #define PCI_EXT_CAP_PASID_SIZEOF 8 | 939 | #define PCI_EXT_CAP_PASID_SIZEOF 8 |
| 940 | 940 | ||
| 941 | /* Single Root I/O Virtualization */ | 941 | /* Single Root I/O Virtualization */ |