Remove pre-3.0 channel status reads. 3.0 and later chansts register is 64bit and can be read 64bit. This was clarified with the hardware architects and since the driver now only support 3.0+ we don't need the legacy support
Unified · Split
| @@ -235,43 +235,11 @@ ioat_chan_by_index(struct ioatdma_device *ioat_dma, int index) · 234 unmodified lines | |||
| 235 | return ioat_dma->idx[index]; | 235 | return ioat_dma->idx[index]; |
| 236 | } | 236 | } |
| 237 | 237 | ||
| 238 | static inline u64 ioat_chansts_32(struct ioatdma_chan *ioat_chan) | ||
| 239 | { | ||
| 240 | u8 ver = ioat_chan->ioat_dma->version; | ||
| 241 | u64 status; | ||
| 242 | u32 status_lo; | ||
| 243 | |||
| 244 | /* We need to read the low address first as this causes the | ||
| 245 | * chipset to latch the upper bits for the subsequent read | ||
| 246 | */ | ||
| 247 | status_lo = readl(ioat_chan->reg_base + IOAT_CHANSTS_OFFSET_LOW(ver)); | ||
| 248 | status = readl(ioat_chan->reg_base + IOAT_CHANSTS_OFFSET_HIGH(ver)); | ||
| 249 | status <<= 32; | ||
| 250 | status |= status_lo; | ||
| 251 | |||
| 252 | return status; | ||
| 253 | } | ||
| 254 | |||
| 255 | #if BITS_PER_LONG == 64 | ||
| 256 | |||
| 257 | static inline u64 ioat_chansts(struct ioatdma_chan *ioat_chan) | 238 | static inline u64 ioat_chansts(struct ioatdma_chan *ioat_chan) |
| 258 | { | 239 | { |
| 259 | u8 ver = ioat_chan->ioat_dma->version; | 240 | return readq(ioat_chan->reg_base + IOAT_CHANSTS_OFFSET); |
| 260 | u64 status; | ||
| 261 | |||
| 262 | /* With IOAT v3.3 the status register is 64bit. */ | ||
| 263 | if (ver >= IOAT_VER_3_3) | ||
| 264 | status = readq(ioat_chan->reg_base + IOAT_CHANSTS_OFFSET(ver)); | ||
| 265 | else | ||
| 266 | status = ioat_chansts_32(ioat_chan); | ||
| 267 | |||
| 268 | return status; | ||
| 269 | } | 241 | } |
| 270 | 242 | ||
| 271 | #else | ||
| 272 | #define ioat_chansts ioat_chansts_32 | ||
| 273 | #endif | ||
| 274 | |||
| 275 | static inline u64 ioat_chansts_to_addr(u64 status) | 243 | static inline u64 ioat_chansts_to_addr(u64 status) |
| 276 | { | 244 | { |
| 277 | return status & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR; | 245 | return status & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR; |
| @@ -99,19 +99,9 @@ · 98 unmodified lines | |||
| 99 | #define IOAT_DMA_COMP_V1 0x0001 /* Compatibility with DMA version 1 */ | 99 | #define IOAT_DMA_COMP_V1 0x0001 /* Compatibility with DMA version 1 */ |
| 100 | #define IOAT_DMA_COMP_V2 0x0002 /* Compatibility with DMA version 2 */ | 100 | #define IOAT_DMA_COMP_V2 0x0002 /* Compatibility with DMA version 2 */ |
| 101 | 101 | ||
| 102 | 102 | /* IOAT1 define left for i7300_idle driver to not fail compiling */ | |
| 103 | #define IOAT1_CHANSTS_OFFSET 0x04 /* 64-bit Channel Status Register */ | 103 | #define IOAT1_CHANSTS_OFFSET 0x04 |
| 104 | #define IOAT2_CHANSTS_OFFSET 0x08 /* 64-bit Channel Status Register */ | 104 | #define IOAT_CHANSTS_OFFSET 0x08 /* 64-bit Channel Status Register */ |
| 105 | #define IOAT_CHANSTS_OFFSET(ver) ((ver) < IOAT_VER_2_0 \ | ||
| 106 | ? IOAT1_CHANSTS_OFFSET : IOAT2_CHANSTS_OFFSET) | ||
| 107 | #define IOAT1_CHANSTS_OFFSET_LOW 0x04 | ||
| 108 | #define IOAT2_CHANSTS_OFFSET_LOW 0x08 | ||
| 109 | #define IOAT_CHANSTS_OFFSET_LOW(ver) ((ver) < IOAT_VER_2_0 \ | ||
| 110 | ? IOAT1_CHANSTS_OFFSET_LOW : IOAT2_CHANSTS_OFFSET_LOW) | ||
| 111 | #define IOAT1_CHANSTS_OFFSET_HIGH 0x08 | ||
| 112 | #define IOAT2_CHANSTS_OFFSET_HIGH 0x0C | ||
| 113 | #define IOAT_CHANSTS_OFFSET_HIGH(ver) ((ver) < IOAT_VER_2_0 \ | ||
| 114 | ? IOAT1_CHANSTS_OFFSET_HIGH : IOAT2_CHANSTS_OFFSET_HIGH) | ||
| 115 | #define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR (~0x3fULL) | 105 | #define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR (~0x3fULL) |
| 116 | #define IOAT_CHANSTS_SOFT_ERR 0x10ULL | 106 | #define IOAT_CHANSTS_SOFT_ERR 0x10ULL |
| 117 | #define IOAT_CHANSTS_UNAFFILIATED_ERR 0x8ULL | 107 | #define IOAT_CHANSTS_UNAFFILIATED_ERR 0x8ULL |