Pull pin control fixes from Linus Walleij: "Some pin control fixes here. All of them are driver fixes, the Intel Cherryview being the most interesting one. - Fix a mux problem for I2C in the MVEBU driver. - Fix a really hairy inversion problem in the Intel Cherryview driver. - Fix the register for the sdc2_clk in the Qualcomm SM8250 driver. - Check the virtual GPIO boot failur in the Mediatek driver" * tag 'pinctrl-v5.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: pinctrl: mediatek: check mtk_is_virt_gpio input parameter pinctrl: qcom: sm8250: correct sdc2_clk pinctrl: cherryview: Preserve CHV_PADCTRL1_INVRXTX_TXDATA flag on GPIOs pinctrl: mvebu: Fix i2c sda definition for 98DX3236
Unified · Split
| @@ -58,6 +58,7 @@ · 57 unmodified lines | ||
| 58 | 58 | #define CHV_PADCTRL1_CFGLOCK BIT(31) |
| 59 | 59 | #define CHV_PADCTRL1_INVRXTX_SHIFT 4 |
| 60 | 60 | #define CHV_PADCTRL1_INVRXTX_MASK GENMASK(7, 4) |
| 61 | +#define CHV_PADCTRL1_INVRXTX_TXDATA BIT(7) | |
| 61 | 62 | #define CHV_PADCTRL1_INVRXTX_RXDATA BIT(6) |
| 62 | 63 | #define CHV_PADCTRL1_INVRXTX_TXENABLE BIT(5) |
| 63 | 64 | #define CHV_PADCTRL1_ODEN BIT(3) |
| @@ -792,11 +793,22 @@ static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, · 728 unmodified lines | ||
| 792 | 793 | static void chv_gpio_clear_triggering(struct chv_pinctrl *pctrl, |
| 793 | 794 | unsigned int offset) |
| 794 | 795 | { |
| 796 | + u32 invrxtx_mask = CHV_PADCTRL1_INVRXTX_MASK; | |
| 795 | 797 | u32 value; |
| 796 | 798 | |
| 799 | + /* | |
| 800 | + * One some devices the GPIO should output the inverted value from what | |
| 801 | + * device-drivers / ACPI code expects (inverted external buffer?). The | |
| 802 | + * BIOS makes this work by setting the CHV_PADCTRL1_INVRXTX_TXDATA flag, | |
| 803 | + * preserve this flag if the pin is already setup as GPIO. | |
| 804 | + */ | |
| 805 | + value = chv_readl(pctrl, offset, CHV_PADCTRL0); | |
| 806 | + if (value & CHV_PADCTRL0_GPIOEN) | |
| 807 | + invrxtx_mask &= ~CHV_PADCTRL1_INVRXTX_TXDATA; | |
| 808 | + | |
| 797 | 809 | value = chv_readl(pctrl, offset, CHV_PADCTRL1); |
| 798 | 810 | value &= ~CHV_PADCTRL1_INTWAKECFG_MASK; |
| 799 | − value &= ~CHV_PADCTRL1_INVRXTX_MASK; | |
| 811 | + value &= ~invrxtx_mask; | |
| 800 | 812 | chv_writel(pctrl, offset, CHV_PADCTRL1, value); |
| 801 | 813 | } |
| 802 | 814 | |
| @@ -259,6 +259,10 @@ bool mtk_is_virt_gpio(struct mtk_pinctrl *hw, unsigned int gpio_n) · 258 unmodified lines | ||
| 259 | 259 | |
| 260 | 260 | desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n]; |
| 261 | 261 | |
| 262 | + /* if the GPIO is not supported for eint mode */ | |
| 263 | + if (desc->eint.eint_m == NO_EINT_SUPPORT) | |
| 264 | + return virt_gpio; | |
| 265 | + | |
| 262 | 266 | if (desc->funcs && !desc->funcs[desc->eint.eint_m].name) |
| 263 | 267 | virt_gpio = true; |
| 264 | 268 | |
| @@ -414,7 +414,7 @@ static struct mvebu_mpp_mode mv98dx3236_mpp_modes[] = { · 413 unmodified lines | ||
| 414 | 414 | MPP_VAR_FUNCTION(0x1, "i2c0", "sck", V_98DX3236_PLUS)), |
| 415 | 415 | MPP_MODE(15, |
| 416 | 416 | MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), |
| 417 | − MPP_VAR_FUNCTION(0x4, "i2c0", "sda", V_98DX3236_PLUS)), | |
| 417 | + MPP_VAR_FUNCTION(0x1, "i2c0", "sda", V_98DX3236_PLUS)), | |
| 418 | 418 | MPP_MODE(16, |
| 419 | 419 | MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), |
| 420 | 420 | MPP_VAR_FUNCTION(0x4, "dev", "oe", V_98DX3236_PLUS)), |
| @@ -1308,7 +1308,7 @@ static const struct msm_pingroup sm8250_groups[] = { · 1307 unmodified lines | ||
| 1308 | 1308 | [178] = PINGROUP(178, WEST, _, _, _, _, _, _, _, _, _), |
| 1309 | 1309 | [179] = PINGROUP(179, WEST, _, _, _, _, _, _, _, _, _), |
| 1310 | 1310 | [180] = UFS_RESET(ufs_reset, 0xb8000), |
| 1311 | − [181] = SDC_PINGROUP(sdc2_clk, 0x7000, 14, 6), | |
| 1311 | + [181] = SDC_PINGROUP(sdc2_clk, 0xb7000, 14, 6), | |
| 1312 | 1312 | [182] = SDC_PINGROUP(sdc2_cmd, 0xb7000, 11, 3), |
| 1313 | 1313 | [183] = SDC_PINGROUP(sdc2_data, 0xb7000, 9, 0), |
| 1314 | 1314 | }; |