tuning-step is the delay cell steps in tuning procedure. The default value of tuning-step is 1. Some boards or cards need another value to pass the tuning procedure. For example, imx7d-sdb board need the tuning-step value as 2, otherwise it can't pass the tuning procedure. So this patch add the tuning-step setting in driver, so that user can set the tuning-step value in dts.
Unified · Split
| @@ -75,6 +75,7 @@ · 74 unmodified lines | |||
| 75 | #define ESDHC_STD_TUNING_EN (1 << 24) | 75 | #define ESDHC_STD_TUNING_EN (1 << 24) |
| 76 | /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */ | 76 | /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */ |
| 77 | #define ESDHC_TUNING_START_TAP 0x1 | 77 | #define ESDHC_TUNING_START_TAP 0x1 |
| 78 | #define ESDHC_TUNING_STEP_SHIFT 16 | ||
| 78 | 79 | ||
| 79 | /* pinctrl state */ | 80 | /* pinctrl state */ |
| 80 | #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz" | 81 | #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz" |
| @@ -474,6 +475,7 @@ static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) · 393 unmodified lines | |||
| 474 | } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { | 475 | } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { |
| 475 | u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR); | 476 | u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR); |
| 476 | u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); | 477 | u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); |
| 478 | u32 tuning_ctrl; | ||
| 477 | if (val & SDHCI_CTRL_TUNED_CLK) { | 479 | if (val & SDHCI_CTRL_TUNED_CLK) { |
| 478 | v |= ESDHC_MIX_CTRL_SMPCLK_SEL; | 480 | v |= ESDHC_MIX_CTRL_SMPCLK_SEL; |
| 479 | } else { | 481 | } else { |
| @@ -484,6 +486,11 @@ static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) · 4 unmodified lines | |||
| 484 | if (val & SDHCI_CTRL_EXEC_TUNING) { | 486 | if (val & SDHCI_CTRL_EXEC_TUNING) { |
| 485 | v |= ESDHC_MIX_CTRL_EXE_TUNE; | 487 | v |= ESDHC_MIX_CTRL_EXE_TUNE; |
| 486 | m |= ESDHC_MIX_CTRL_FBCLK_SEL; | 488 | m |= ESDHC_MIX_CTRL_FBCLK_SEL; |
| 489 | tuning_ctrl = readl(host->ioaddr + ESDHC_TUNING_CTRL); | ||
| 490 | tuning_ctrl |= ESDHC_STD_TUNING_EN | ESDHC_TUNING_START_TAP; | ||
| 491 | if (imx_data->boarddata.tuning_step) | ||
| 492 | tuning_ctrl |= imx_data->boarddata.tuning_step << ESDHC_TUNING_STEP_SHIFT; | ||
| 493 | writel(tuning_ctrl, host->ioaddr + ESDHC_TUNING_CTRL); | ||
| 487 | } else { | 494 | } else { |
| 488 | v &= ~ESDHC_MIX_CTRL_EXE_TUNE; | 495 | v &= ~ESDHC_MIX_CTRL_EXE_TUNE; |
| 489 | } | 496 | } |
| @@ -963,6 +970,8 @@ sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, · 473 unmodified lines | |||
| 963 | if (gpio_is_valid(boarddata->wp_gpio)) | 970 | if (gpio_is_valid(boarddata->wp_gpio)) |
| 964 | boarddata->wp_type = ESDHC_WP_GPIO; | 971 | boarddata->wp_type = ESDHC_WP_GPIO; |
| 965 | 972 | ||
| 973 | of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step); | ||
| 974 | |||
| 966 | if (of_find_property(np, "no-1-8-v", NULL)) | 975 | if (of_find_property(np, "no-1-8-v", NULL)) |
| 967 | boarddata->support_vsel = false; | 976 | boarddata->support_vsel = false; |
| 968 | else | 977 | else |
| @@ -45,5 +45,6 @@ struct esdhc_platform_data { · 44 unmodified lines | |||
| 45 | int max_bus_width; | 45 | int max_bus_width; |
| 46 | bool support_vsel; | 46 | bool support_vsel; |
| 47 | unsigned int delay_line; | 47 | unsigned int delay_line; |
| 48 | unsigned int tuning_step; /* The delay cell steps in tuning procedure */ | ||
| 48 | }; | 49 | }; |
| 49 | #endif /* __ASM_ARCH_IMX_ESDHC_H */ | 50 | #endif /* __ASM_ARCH_IMX_ESDHC_H */ |