lael-labs/linux

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c+18−31

 	spinlock_t mem_limit_lock;
 } kfd_mem_limit;
-/* Struct used for amdgpu_amdkfd_bo_validate */
-struct amdgpu_vm_parser {
-	uint32_t        domain;
-	bool            wait;
-};
 static const char * const domain_bit_to_string[] = {
 		"CPU",
 		"GTT",
 	return ret;
 }
-static int amdgpu_amdkfd_validate(void *param, struct amdgpu_bo *bo)
+static int amdgpu_amdkfd_validate_vm_bo(void *_unused, struct amdgpu_bo *bo)
 {
-	struct amdgpu_vm_parser *p = param;
+	return amdgpu_amdkfd_bo_validate(bo, bo->allowed_domains, false);
-	return amdgpu_amdkfd_bo_validate(bo, p->domain, p->wait);
 }
 /* vm_validate_pt_pd_bos - Validate page table and directory BOs
  */
 static int vm_validate_pt_pd_bos(struct amdgpu_vm *vm)
 {
-	struct amdgpu_bo *pd = vm->root.base.bo;
+	struct amdgpu_bo *pd = vm->root.bo;
 	struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
-	struct amdgpu_vm_parser param;
 	int ret;
-	param.domain = AMDGPU_GEM_DOMAIN_VRAM;
+	ret = amdgpu_vm_validate_pt_bos(adev, vm, amdgpu_amdkfd_validate_vm_bo, NULL);
-	param.wait = false;
-	ret = amdgpu_vm_validate_pt_bos(adev, vm, amdgpu_amdkfd_validate,
-					&param);
 	if (ret) {
 		pr_err("failed to validate PT BOs\n");
 		return ret;
 	}
-	ret = amdgpu_amdkfd_validate(&param, pd);
+	ret = amdgpu_amdkfd_validate_vm_bo(NULL, pd);
 	if (ret) {
 		pr_err("failed to validate PD\n");
 		return ret;
 	}
-	vm->pd_phys_addr = amdgpu_gmc_pd_addr(vm->root.base.bo);
+	vm->pd_phys_addr = amdgpu_gmc_pd_addr(vm->root.bo);
 	if (vm->use_cpu_for_update) {
 		ret = amdgpu_bo_kmap(pd, NULL);
 static int vm_update_pds(struct amdgpu_vm *vm, struct amdgpu_sync *sync)
 {
-	struct amdgpu_bo *pd = vm->root.base.bo;
+	struct amdgpu_bo *pd = vm->root.bo;
 	struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
 	int ret;
 		}
 	}
-	gobj = amdgpu_gem_prime_import(&adev->ddev, mem->dmabuf);
+	gobj = amdgpu_gem_prime_import(adev_to_drm(adev), mem->dmabuf);
 	if (IS_ERR(gobj))
 		return PTR_ERR(gobj);
 	list_for_each_entry(peer_vm, &process_info->vm_list_head,
 			    vm_list_node) {
-		struct amdgpu_bo *pd = peer_vm->root.base.bo;
+		struct amdgpu_bo *pd = peer_vm->root.bo;
 		ret = amdgpu_sync_resv(NULL, sync, pd->tbo.base.resv,
 				       AMDGPU_SYNC_NE_OWNER,
 	vm->process_info = *process_info;
 	/* Validate page directory and attach eviction fence */
-	ret = amdgpu_bo_reserve(vm->root.base.bo, true);
+	ret = amdgpu_bo_reserve(vm->root.bo, true);
 	if (ret)
 		goto reserve_pd_fail;
 	ret = vm_validate_pt_pd_bos(vm);
 		pr_err("validate_pt_pd_bos() failed\n");
 		goto validate_pd_fail;
 	}
-	ret = amdgpu_bo_sync_wait(vm->root.base.bo,
+	ret = amdgpu_bo_sync_wait(vm->root.bo,
 				  AMDGPU_FENCE_OWNER_KFD, false);
 	if (ret)
 		goto wait_pd_fail;
-	ret = dma_resv_reserve_shared(vm->root.base.bo->tbo.base.resv, 1);
+	ret = dma_resv_reserve_shared(vm->root.bo->tbo.base.resv, 1);
 	if (ret)
 		goto reserve_shared_fail;
-	amdgpu_bo_fence(vm->root.base.bo,
+	amdgpu_bo_fence(vm->root.bo,
 			&vm->process_info->eviction_fence->base, true);
-	amdgpu_bo_unreserve(vm->root.base.bo);
+	amdgpu_bo_unreserve(vm->root.bo);
 	/* Update process info */
 	mutex_lock(&vm->process_info->lock);
 reserve_shared_fail:
 wait_pd_fail:
 validate_pd_fail:
-	amdgpu_bo_unreserve(vm->root.base.bo);
+	amdgpu_bo_unreserve(vm->root.bo);
 reserve_pd_fail:
 	vm->process_info = NULL;
 	if (info) {
 				    struct amdgpu_vm *vm)
 {
 	struct amdkfd_process_info *process_info = vm->process_info;
-	struct amdgpu_bo *pd = vm->root.base.bo;
+	struct amdgpu_bo *pd = vm->root.bo;
 	if (!process_info)
 		return;
 uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv)
 {
 	struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
-	struct amdgpu_bo *pd = avm->root.base.bo;
+	struct amdgpu_bo *pd = avm->root.bo;
 	struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
 	if (adev->asic_type < CHIP_VEGA10)
 	/* Attach eviction fence to PD / PT BOs */
 	list_for_each_entry(peer_vm, &process_info->vm_list_head,
 			    vm_list_node) {
-		struct amdgpu_bo *bo = peer_vm->root.base.bo;
+		struct amdgpu_bo *bo = peer_vm->root.bo;
 		amdgpu_bo_fence(bo, &process_info->eviction_fence->base, true);
 	}

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c+1−1

@@ -832,7 +832,7 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p) · 831 unmodified lines
832	if (r)	832	if (r)
833	return r;	833	return r;
834		834
835	p->job->vm_pd_addr = amdgpu_gmc_pd_addr(vm->root.base.bo);	835	p->job->vm_pd_addr = amdgpu_gmc_pd_addr(vm->root.bo);
836		836
837	if (amdgpu_vm_debug) {	837	if (amdgpu_vm_debug) {
838	/* Invalidate all BOs to test for userspace bugs */	838	/* Invalidate all BOs to test for userspace bugs */

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c+2−2

@@ -1304,11 +1304,11 @@ static int amdgpu_debugfs_vm_info_show(struct seq_file m, void unused) · 1303 unmodified lines
1304		1304
1305	seq_printf(m, "pid:%d\tProcess:%s ----------\n",	1305	seq_printf(m, "pid:%d\tProcess:%s ----------\n",
1306	vm->task_info.pid, vm->task_info.process_name);	1306	vm->task_info.pid, vm->task_info.process_name);
1307	r = amdgpu_bo_reserve(vm->root.base.bo, true);	1307	r = amdgpu_bo_reserve(vm->root.bo, true);
1308	if (r)	1308	if (r)
1309	break;	1309	break;
1310	amdgpu_debugfs_vm_bo_info(vm, m);	1310	amdgpu_debugfs_vm_bo_info(vm, m);
1311	amdgpu_bo_unreserve(vm->root.base.bo);	1311	amdgpu_bo_unreserve(vm->root.bo);
1312	}	1312	}
1313		1313
1314	mutex_unlock(&dev->filelist_mutex);	1314	mutex_unlock(&dev->filelist_mutex);

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c+3−2

@@ -4124,6 +4124,7 @@ static int amdgpu_device_recover_vram(struct amdgpu_device *adev) · 4123 unmodified lines
4124	{	4124	{
4125	struct dma_fence fence = NULL, next = NULL;	4125	struct dma_fence fence = NULL, next = NULL;
4126	struct amdgpu_bo *shadow;	4126	struct amdgpu_bo *shadow;
		4127	struct amdgpu_bo_vm *vmbo;
4127	long r = 1, tmo;	4128	long r = 1, tmo;
4128		4129
4129	if (amdgpu_sriov_runtime(adev))	4130	if (amdgpu_sriov_runtime(adev))
@@ -4133,8 +4134,8 @@ static int amdgpu_device_recover_vram(struct amdgpu_device *adev) · 3 unmodified lines
4133		4134
4134	dev_info(adev->dev, "recover vram bo from shadow start\n");	4135	dev_info(adev->dev, "recover vram bo from shadow start\n");
4135	mutex_lock(&adev->shadow_list_lock);	4136	mutex_lock(&adev->shadow_list_lock);
4136	list_for_each_entry(shadow, &adev->shadow_list, shadow_list) {	4137	list_for_each_entry(vmbo, &adev->shadow_list, shadow_list) {
4137		4138	shadow = &vmbo->bo;
4138	/* No need to recover an evicted BO */	4139	/* No need to recover an evicted BO */
4139	if (shadow->tbo.resource->mem_type != TTM_PL_TT \|\|	4140	if (shadow->tbo.resource->mem_type != TTM_PL_TT \|\|
4140	shadow->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET \|\|	4141	shadow->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET \|\|

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c+2−2

@@ -325,7 +325,7 @@ int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) · 324 unmodified lines
325	return 0;	325	return 0;
326	}	326	}
327		327
328	int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id,	328	int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, int number_instance,
329	int major, int minor, int *revision)	329	int major, int minor, int *revision)
330	{	330	{
331	struct binary_header *bhdr;	331	struct binary_header *bhdr;
@@ -357,7 +357,7 @@ int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, · 25 unmodified lines
357	for (j = 0; j < num_ips; j++) {	357	for (j = 0; j < num_ips; j++) {
358	ip = (struct ip *)(adev->mman.discovery_bin + ip_offset);	358	ip = (struct ip *)(adev->mman.discovery_bin + ip_offset);
359		359
360	if (le16_to_cpu(ip->hw_id) == hw_id) {	360	if ((le16_to_cpu(ip->hw_id) == hw_id) && (ip->number_instance == number_instance)) {
361	if (major)	361	if (major)
362	*major = ip->major;	362	*major = ip->major;
363	if (minor)	363	if (minor)

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h+1−1

@@ -30,7 +30,7 @@ · 29 unmodified lines
30	void amdgpu_discovery_fini(struct amdgpu_device *adev);	30	void amdgpu_discovery_fini(struct amdgpu_device *adev);
31	int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev);	31	int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev);
32	void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev);	32	void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev);
33	int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id,	33	int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, int number_instance,
34	int major, int minor, int *revision);	34	int major, int minor, int *revision);
35	int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev);	35	int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev);
36		36

drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c+1−1

@@ -448,7 +448,7 @@ amdgpu_dma_buf_move_notify(struct dma_buf_attachment *attach) · 447 unmodified lines
448		448
449	for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {	449	for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
450	struct amdgpu_vm *vm = bo_base->vm;	450	struct amdgpu_vm *vm = bo_base->vm;
451	struct dma_resv *resv = vm->root.base.bo->tbo.base.resv;	451	struct dma_resv *resv = vm->root.bo->tbo.base.resv;
452		452
453	if (ticket) {	453	if (ticket) {
454	/* When we get an error here it means that somebody	454	/* When we get an error here it means that somebody

drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c+2−2

@@ -69,13 +69,13 @@ void amdgpu_show_fdinfo(struct seq_file m, struct file f) · 68 unmodified lines
69	dev = PCI_SLOT(adev->pdev->devfn);	69	dev = PCI_SLOT(adev->pdev->devfn);
70	fn = PCI_FUNC(adev->pdev->devfn);	70	fn = PCI_FUNC(adev->pdev->devfn);
71		71
72	ret = amdgpu_bo_reserve(fpriv->vm.root.base.bo, false);	72	ret = amdgpu_bo_reserve(fpriv->vm.root.bo, false);
73	if (ret) {	73	if (ret) {
74	DRM_ERROR("Fail to reserve bo\n");	74	DRM_ERROR("Fail to reserve bo\n");
75	return;	75	return;
76	}	76	}
77	amdgpu_vm_get_memory(&fpriv->vm, &vram_mem, &gtt_mem, &cpu_mem);	77	amdgpu_vm_get_memory(&fpriv->vm, &vram_mem, &gtt_mem, &cpu_mem);
78	amdgpu_bo_unreserve(fpriv->vm.root.base.bo);	78	amdgpu_bo_unreserve(fpriv->vm.root.bo);
79	seq_printf(m, "pdev:\t%04x:%02x:%02x.%d\npasid:\t%u\n", domain, bus,	79	seq_printf(m, "pdev:\t%04x:%02x:%02x.%d\npasid:\t%u\n", domain, bus,
80	dev, fn, fpriv->vm.pasid);	80	dev, fn, fpriv->vm.pasid);
81	seq_printf(m, "vram mem:\t%llu kB\n", vram_mem/1024UL);	81	seq_printf(m, "vram mem:\t%llu kB\n", vram_mem/1024UL);

drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c+6−6

@@ -170,7 +170,7 @@ static int amdgpu_gem_object_open(struct drm_gem_object *obj, · 169 unmodified lines
170	return -EPERM;	170	return -EPERM;
171		171
172	if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID &&	172	if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID &&
173	abo->tbo.base.resv != vm->root.base.bo->tbo.base.resv)	173	abo->tbo.base.resv != vm->root.bo->tbo.base.resv)
174	return -EPERM;	174	return -EPERM;
175		175
176	r = amdgpu_bo_reserve(abo, false);	176	r = amdgpu_bo_reserve(abo, false);
@@ -320,11 +320,11 @@ int amdgpu_gem_create_ioctl(struct drm_device dev, void data, · 143 unmodified lines
320	}	320	}
321		321
322	if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {	322	if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
323	r = amdgpu_bo_reserve(vm->root.base.bo, false);	323	r = amdgpu_bo_reserve(vm->root.bo, false);
324	if (r)	324	if (r)
325	return r;	325	return r;
326		326
327	resv = vm->root.base.bo->tbo.base.resv;	327	resv = vm->root.bo->tbo.base.resv;
328	}	328	}
329		329
330	initial_domain = (u32)(0xffffffff & args->in.domains);	330	initial_domain = (u32)(0xffffffff & args->in.domains);
@@ -353,9 +353,9 @@ retry: · 22 unmodified lines
353	if (!r) {	353	if (!r) {
354	struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);	354	struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
355		355
356	abo->parent = amdgpu_bo_ref(vm->root.base.bo);	356	abo->parent = amdgpu_bo_ref(vm->root.bo);
357	}	357	}
358	amdgpu_bo_unreserve(vm->root.base.bo);	358	amdgpu_bo_unreserve(vm->root.bo);
359	}	359	}
360	if (r)	360	if (r)
361	return r;	361	return r;
@@ -841,7 +841,7 @@ int amdgpu_gem_op_ioctl(struct drm_device dev, void data, · 479 unmodified lines
841	}	841	}
842	for (base = robj->vm_bo; base; base = base->next)	842	for (base = robj->vm_bo; base; base = base->next)
843	if (amdgpu_xgmi_same_hive(amdgpu_ttm_adev(robj->tbo.bdev),	843	if (amdgpu_xgmi_same_hive(amdgpu_ttm_adev(robj->tbo.bdev),
844	amdgpu_ttm_adev(base->vm->root.base.bo->tbo.bdev))) {	844	amdgpu_ttm_adev(base->vm->root.bo->tbo.bdev))) {
845	r = -EINVAL;	845	r = -EINVAL;
846	amdgpu_bo_unreserve(robj);	846	amdgpu_bo_unreserve(robj);
847	goto out;	847	goto out;

drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c+43−1

@@ -124,6 +124,22 @@ void amdgpu_register_gpu_instance(struct amdgpu_device *adev) · 123 unmodified lines
124	mutex_unlock(&mgpu_info.mutex);	124	mutex_unlock(&mgpu_info.mutex);
125	}	125	}
126		126
		127	static void amdgpu_get_audio_func(struct amdgpu_device *adev)
		128	{
		129	struct pci_dev *p = NULL;
		130
		131	p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
		132	adev->pdev->bus->number, 1);
		133	if (p) {
		134	pm_runtime_get_sync(&p->dev);
		135
		136	pm_runtime_mark_last_busy(&p->dev);
		137	pm_runtime_put_autosuspend(&p->dev);
		138
		139	pci_dev_put(p);
		140	}
		141	}
		142
127	/**	143	/**
128	* amdgpu_driver_load_kms - Main load function for KMS.	144	* amdgpu_driver_load_kms - Main load function for KMS.
129	*	145	*
@@ -213,9 +229,35 @@ int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags) · 83 unmodified lines
213	DPM_FLAG_MAY_SKIP_RESUME);	229	DPM_FLAG_MAY_SKIP_RESUME);
214	pm_runtime_use_autosuspend(dev->dev);	230	pm_runtime_use_autosuspend(dev->dev);
215	pm_runtime_set_autosuspend_delay(dev->dev, 5000);	231	pm_runtime_set_autosuspend_delay(dev->dev, 5000);
		232
216	pm_runtime_allow(dev->dev);	233	pm_runtime_allow(dev->dev);
		234
217	pm_runtime_mark_last_busy(dev->dev);	235	pm_runtime_mark_last_busy(dev->dev);
218	pm_runtime_put_autosuspend(dev->dev);	236	pm_runtime_put_autosuspend(dev->dev);
		237
		238	/*
		239	* For runpm implemented via BACO, PMFW will handle the
		240	* timing for BACO in and out:
		241	* - put ASIC into BACO state only when both video and
		242	* audio functions are in D3 state.
		243	* - pull ASIC out of BACO state when either video or
		244	* audio function is in D0 state.
		245	* Also, at startup, PMFW assumes both functions are in
		246	* D0 state.
		247	*
		248	* So if snd driver was loaded prior to amdgpu driver
		249	* and audio function was put into D3 state, there will
		250	* be no PMFW-aware D-state transition(D0->D3) on runpm
		251	* suspend. Thus the BACO will be not correctly kicked in.
		252	*
		253	* Via amdgpu_get_audio_func(), the audio dev is put
		254	* into D0 state. Then there will be a PMFW-aware D-state
		255	* transition(D0->D3) on runpm suspend.
		256	*/
		257	if (amdgpu_device_supports_baco(dev) &&
		258	!(adev->flags & AMD_IS_APU) &&
		259	(adev->asic_type >= CHIP_NAVI10))
		260	amdgpu_get_audio_func(adev);
219	}	261	}
220		262
221	if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD))	263	if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD))
@@ -1220,7 +1262,7 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev, · 998 unmodified lines
1220	}	1262	}
1221		1263
1222	pasid = fpriv->vm.pasid;	1264	pasid = fpriv->vm.pasid;
1223	pd = amdgpu_bo_ref(fpriv->vm.root.base.bo);	1265	pd = amdgpu_bo_ref(fpriv->vm.root.bo);
1224		1266
1225	amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);	1267	amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
1226	amdgpu_vm_fini(adev, &fpriv->vm);	1268	amdgpu_vm_fini(adev, &fpriv->vm);

drivers/gpu/drm/amd/amdgpu/amdgpu_object.c+38−17

 static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo)
 {
-	struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
 	struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo);
-	struct amdgpu_bo_user *ubo;
 	amdgpu_bo_kunmap(bo);
 	if (bo->tbo.base.import_attach)
 		drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg);
 	drm_gem_object_release(&bo->tbo.base);
+	amdgpu_bo_unref(&bo->parent);
+	kvfree(bo);
+}
+static void amdgpu_bo_user_destroy(struct ttm_buffer_object *tbo)
+{
+	struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo);
+	struct amdgpu_bo_user *ubo;
+	ubo = to_amdgpu_bo_user(bo);
+	kfree(ubo->metadata);
+	amdgpu_bo_destroy(tbo);
+}
+static void amdgpu_bo_vm_destroy(struct ttm_buffer_object *tbo)
+{
+	struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
+	struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo);
+	struct amdgpu_bo_vm *vmbo;
+	vmbo = to_amdgpu_bo_vm(bo);
 	/* in case amdgpu_device_recover_vram got NULL of bo->parent */
-	if (!list_empty(&bo->shadow_list)) {
+	if (!list_empty(&vmbo->shadow_list)) {
 		mutex_lock(&adev->shadow_list_lock);
-		list_del_init(&bo->shadow_list);
+		list_del_init(&vmbo->shadow_list);
 		mutex_unlock(&adev->shadow_list_lock);
 	}
-	amdgpu_bo_unref(&bo->parent);
-	if (bo->tbo.type != ttm_bo_type_kernel) {
-		ubo = to_amdgpu_bo_user(bo);
-		kfree(ubo->metadata);
-	}
-	kvfree(bo);
+	amdgpu_bo_destroy(tbo);
 }
 /**
  */
 bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo)
 {
-	if (bo->destroy == &amdgpu_bo_destroy)
+	if (bo->destroy == &amdgpu_bo_destroy ||
+	    bo->destroy == &amdgpu_bo_user_destroy ||
+	    bo->destroy == &amdgpu_bo_vm_destroy)
 		return true;
 	return false;
 }
 	if (bo == NULL)
 		return -ENOMEM;
 	drm_gem_private_object_init(adev_to_drm(adev), &bo->tbo.base, size);
-	INIT_LIST_HEAD(&bo->shadow_list);
 	bo->vm_bo = NULL;
 	bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain :
 		bp->domain;
 	if (bp->type == ttm_bo_type_kernel)
 		bo->tbo.priority = 1;
+	if (!bp->destroy)
+		bp->destroy = &amdgpu_bo_destroy;
 	r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, bp->type,
 				 &bo->placement, page_align, &ctx,  NULL,
-				 bp->resv, &amdgpu_bo_destroy);
+				 bp->resv, bp->destroy);
 	if (unlikely(r != 0))
 		return r;
 	int r;
 	bp->bo_ptr_size = sizeof(struct amdgpu_bo_user);
+	bp->destroy = &amdgpu_bo_user_destroy;
 	r = amdgpu_bo_create(adev, bp, &bo_ptr);
 	if (r)
 		return r;
 	 * num of amdgpu_vm_pt entries.
 	 */
 	BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo_vm));
+	bp->destroy = &amdgpu_bo_vm_destroy;
 	r = amdgpu_bo_create(adev, bp, &bo_ptr);
 	if (r)
 		return r;
 	*vmbo_ptr = to_amdgpu_bo_vm(bo_ptr);
+	INIT_LIST_HEAD(&(*vmbo_ptr)->shadow_list);
 	return r;
 }
  *
  * Insert a BO to the shadow list.
  */
-void amdgpu_bo_add_to_shadow_list(struct amdgpu_bo *bo)
+void amdgpu_bo_add_to_shadow_list(struct amdgpu_bo_vm *vmbo)
 {
-	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
+	struct amdgpu_device *adev = amdgpu_ttm_adev(vmbo->bo.tbo.bdev);
 	mutex_lock(&adev->shadow_list_lock);
-	list_add_tail(&bo->shadow_list, &adev->shadow_list);
+	list_add_tail(&vmbo->shadow_list, &adev->shadow_list);
 	mutex_unlock(&adev->shadow_list_lock);
 }

drivers/gpu/drm/amd/amdgpu/amdgpu_object.h+5−6

 	u64				flags;
 	enum ttm_bo_type		type;
 	bool				no_wait_gpu;
-	struct dma_resv	*resv;
+	struct dma_resv			*resv;
+	void				(*destroy)(struct ttm_buffer_object *bo);
 };
 /* bo virtual addresses in a vm */
 #ifdef CONFIG_MMU_NOTIFIER
 	struct mmu_interval_notifier	notifier;
 #endif
-	struct list_head		shadow_list;
 	struct kgd_mem                  *kfd_bo;
 };
 struct amdgpu_bo_vm {
 	struct amdgpu_bo		bo;
 	struct amdgpu_bo		*shadow;
-	struct amdgpu_vm_pt             entries[];
+	struct list_head		shadow_list;
+	struct amdgpu_vm_bo_base        entries[];
 };
 static inline struct amdgpu_bo *ttm_to_amdgpu_bo(struct ttm_buffer_object *tbo)
 int amdgpu_bo_validate(struct amdgpu_bo *bo);
 void amdgpu_bo_get_memory(struct amdgpu_bo *bo, uint64_t *vram_mem,
 				uint64_t *gtt_mem, uint64_t *cpu_mem);
-void amdgpu_bo_add_to_shadow_list(struct amdgpu_bo *bo);
+void amdgpu_bo_add_to_shadow_list(struct amdgpu_bo_vm *vmbo);
 int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow,
 			     struct dma_fence **fence);
 uint32_t amdgpu_bo_get_preferred_pin_domain(struct amdgpu_device *adev,

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c+253−57

@@ -171,11 +171,81 @@ Err_out: · 170 unmodified lines
171	return ret;	171	return ret;
172	}	172	}
173		173
		174	/*
		175	* Helper funciton to query psp runtime database entry
		176	*
		177	* @adev: amdgpu_device pointer
		178	* @entry_type: the type of psp runtime database entry
		179	* @db_entry: runtime database entry pointer
		180	*
		181	* Return false if runtime database doesn't exit or entry is invalid
		182	* or true if the specific database entry is found, and copy to @db_entry
		183	*/
		184	static bool psp_get_runtime_db_entry(struct amdgpu_device *adev,
		185	enum psp_runtime_entry_type entry_type,
		186	void *db_entry)
		187	{
		188	uint64_t db_header_pos, db_dir_pos;
		189	struct psp_runtime_data_header db_header = {0};
		190	struct psp_runtime_data_directory db_dir = {0};
		191	bool ret = false;
		192	int i;
		193
		194	db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET;
		195	db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header);
		196
		197	/* read runtime db header from vram */
		198	amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header,
		199	sizeof(struct psp_runtime_data_header), false);
		200
		201	if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) {
		202	/* runtime db doesn't exist, exit */
		203	dev_warn(adev->dev, "PSP runtime database doesn't exist\n");
		204	return false;
		205	}
		206
		207	/* read runtime database entry from vram */
		208	amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir,
		209	sizeof(struct psp_runtime_data_directory), false);
		210
		211	if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) {
		212	/* invalid db entry count, exit */
		213	dev_warn(adev->dev, "Invalid PSP runtime database entry count\n");
		214	return false;
		215	}
		216
		217	/* look up for requested entry type */
		218	for (i = 0; i < db_dir.entry_count && !ret; i++) {
		219	if (db_dir.entry_list[i].entry_type == entry_type) {
		220	switch (entry_type) {
		221	case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG:
		222	if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) {
		223	/* invalid db entry size */
		224	dev_warn(adev->dev, "Invalid PSP runtime database entry size\n");
		225	return false;
		226	}
		227	/* read runtime database entry */
		228	amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
		229	(uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false);
		230	ret = true;
		231	break;
		232	default:
		233	ret = false;
		234	break;
		235	}
		236	}
		237	}
		238
		239	return ret;
		240	}
		241
174	static int psp_sw_init(void *handle)	242	static int psp_sw_init(void *handle)
175	{	243	{
176	struct amdgpu_device adev = (struct amdgpu_device )handle;	244	struct amdgpu_device adev = (struct amdgpu_device )handle;
177	struct psp_context *psp = &adev->psp;	245	struct psp_context *psp = &adev->psp;
178	int ret;	246	int ret;
		247	struct psp_runtime_boot_cfg_entry boot_cfg_entry;
		248	struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx;
179		249
180	if (!amdgpu_sriov_vf(adev)) {	250	if (!amdgpu_sriov_vf(adev)) {
181	ret = psp_init_microcode(psp);	251	ret = psp_init_microcode(psp);
@@ -191,15 +261,39 @@ static int psp_sw_init(void *handle) · 9 unmodified lines
191	}	261	}
192	}	262	}
193		263
194	ret = psp_memory_training_init(psp);	264	memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry));
195	if (ret) {	265	if (psp_get_runtime_db_entry(adev,
196	DRM_ERROR("Failed to initialize memory training!\n");	266	PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG,
197	return ret;	267	&boot_cfg_entry)) {
		268	psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask;
		269	if ((psp->boot_cfg_bitmask) &
		270	BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) {
		271	/* If psp runtime database exists, then
		272	* only enable two stage memory training
		273	* when TWO_STAGE_DRAM_TRAINING bit is set
		274	* in runtime database */
		275	mem_training_ctx->enable_mem_training = true;
		276	}
		277
		278	} else {
		279	/* If psp runtime database doesn't exist or
		280	* is invalid, force enable two stage memory
		281	* training */
		282	mem_training_ctx->enable_mem_training = true;
198	}	283	}
199	ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);	284
200	if (ret) {	285	if (mem_training_ctx->enable_mem_training) {
201	DRM_ERROR("Failed to process memory training!\n");	286	ret = psp_memory_training_init(psp);
202	return ret;	287	if (ret) {
		288	DRM_ERROR("Failed to initialize memory training!\n");
		289	return ret;
		290	}
		291
		292	ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
		293	if (ret) {
		294	DRM_ERROR("Failed to process memory training!\n");
		295	return ret;
		296	}
203	}	297	}
204		298
205	if (adev->asic_type == CHIP_NAVI10 \|\| adev->asic_type == CHIP_SIENNA_CICHLID) {	299	if (adev->asic_type == CHIP_NAVI10 \|\| adev->asic_type == CHIP_SIENNA_CICHLID) {
@@ -551,7 +645,30 @@ int psp_get_fw_attestation_records_addr(struct psp_context *psp, · 345 unmodified lines
551	return ret;	645	return ret;
552	}	646	}
553		647
554	static int psp_boot_config_set(struct amdgpu_device *adev)	648	static int psp_boot_config_get(struct amdgpu_device adev, uint32_t boot_cfg)
		649	{
		650	struct psp_context *psp = &adev->psp;
		651	struct psp_gfx_cmd_resp *cmd = psp->cmd;
		652	int ret;
		653
		654	if (amdgpu_sriov_vf(adev))
		655	return 0;
		656
		657	memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
		658
		659	cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
		660	cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET;
		661
		662	ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
		663	if (!ret) {
		664	*boot_cfg =
		665	(cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0;
		666	}
		667
		668	return ret;
		669	}
		670
		671	static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg)
555	{	672	{
556	struct psp_context *psp = &adev->psp;	673	struct psp_context *psp = &adev->psp;
557	struct psp_gfx_cmd_resp *cmd = psp->cmd;	674	struct psp_gfx_cmd_resp *cmd = psp->cmd;
@@ -563,8 +680,8 @@ static int psp_boot_config_set(struct amdgpu_device *adev) · 5 unmodified lines
563		680
564	cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;	681	cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
565	cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET;	682	cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET;
566	cmd->cmd.boot_cfg.boot_config = BOOT_CONFIG_GECC;	683	cmd->cmd.boot_cfg.boot_config = boot_cfg;
567	cmd->cmd.boot_cfg.boot_config_valid = BOOT_CONFIG_GECC;	684	cmd->cmd.boot_cfg.boot_config_valid = boot_cfg;
568		685
569	return psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);	686	return psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
570	}	687	}
@@ -1212,19 +1329,62 @@ static int psp_ras_terminate(struct psp_context *psp) · 641 unmodified lines
1212	static int psp_ras_initialize(struct psp_context *psp)	1329	static int psp_ras_initialize(struct psp_context *psp)
1213	{	1330	{
1214	int ret;	1331	int ret;
		1332	uint32_t boot_cfg = 0xFF;
		1333	struct amdgpu_device *adev = psp->adev;
1215		1334
1216	/*	1335	/*
1217	* TODO: bypass the initialize in sriov for now	1336	* TODO: bypass the initialize in sriov for now
1218	*/	1337	*/
1219	if (amdgpu_sriov_vf(psp->adev))	1338	if (amdgpu_sriov_vf(adev))
1220	return 0;	1339	return 0;
1221		1340
1222	if (!psp->adev->psp.ta_ras_ucode_size \|\|	1341	if (!adev->psp.ta_ras_ucode_size \|\|
1223	!psp->adev->psp.ta_ras_start_addr) {	1342	!adev->psp.ta_ras_start_addr) {
1224	dev_info(psp->adev->dev, "RAS: optional ras ta ucode is not available\n");	1343	dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n");
1225	return 0;	1344	return 0;
1226	}	1345	}
1227		1346
		1347	if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) {
		1348	/* query GECC enablement status from boot config
		1349	* boot_cfg: 1: GECC is enabled or 0: GECC is disabled
		1350	*/
		1351	ret = psp_boot_config_get(adev, &boot_cfg);
		1352	if (ret)
		1353	dev_warn(adev->dev, "PSP get boot config failed\n");
		1354
		1355	if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) {
		1356	if (!boot_cfg) {
		1357	dev_info(adev->dev, "GECC is disabled\n");
		1358	} else {
		1359	/* disable GECC in next boot cycle if ras is
		1360	* disabled by module parameter amdgpu_ras_enable
		1361	* and/or amdgpu_ras_mask, or boot_config_get call
		1362	* is failed
		1363	*/
		1364	ret = psp_boot_config_set(adev, 0);
		1365	if (ret)
		1366	dev_warn(adev->dev, "PSP set boot config failed\n");
		1367	else
		1368	dev_warn(adev->dev, "GECC will be disabled in next boot cycle "
		1369	"if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n");
		1370	}
		1371	} else {
		1372	if (1 == boot_cfg) {
		1373	dev_info(adev->dev, "GECC is enabled\n");
		1374	} else {
		1375	/* enable GECC in next boot cycle if it is disabled
		1376	* in boot config, or force enable GECC if failed to
		1377	* get boot configuration
		1378	*/
		1379	ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC);
		1380	if (ret)
		1381	dev_warn(adev->dev, "PSP set boot config failed\n");
		1382	else
		1383	dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n");
		1384	}
		1385	}
		1386	}
		1387
1228	if (!psp->ras.ras_initialized) {	1388	if (!psp->ras.ras_initialized) {
1229	ret = psp_ras_init_shared_buf(psp);	1389	ret = psp_ras_init_shared_buf(psp);
1230	if (ret)	1390	if (ret)
@@ -1945,12 +2105,6 @@ static int psp_hw_start(struct psp_context *psp) · 714 unmodified lines
1945	return ret;	2105	return ret;
1946	}	2106	}
1947		2107
1948	if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) {
1949	ret = psp_boot_config_set(adev);
1950	if (ret)
1951	dev_warn(adev->dev, "PSP set boot config failed\n");
1952	}
1953
1954	ret = psp_tmr_init(psp);	2108	ret = psp_tmr_init(psp);
1955	if (ret) {	2109	if (ret) {
1956	DRM_ERROR("PSP tmr init failed!\n");	2110	DRM_ERROR("PSP tmr init failed!\n");
@@ -2188,10 +2342,7 @@ static int psp_load_smu_fw(struct psp_context *psp) · 231 unmodified lines
2188	if ((amdgpu_in_reset(adev) &&	2342	if ((amdgpu_in_reset(adev) &&
2189	ras && adev->ras_enabled &&	2343	ras && adev->ras_enabled &&
2190	(adev->asic_type == CHIP_ARCTURUS \|\|	2344	(adev->asic_type == CHIP_ARCTURUS \|\|
2191	adev->asic_type == CHIP_VEGA20)) \|\|	2345	adev->asic_type == CHIP_VEGA20))) {
2192	(adev->in_runpm &&
2193	adev->asic_type >= CHIP_NAVI10 &&
2194	adev->asic_type <= CHIP_NAVI12)) {
2195	ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);	2346	ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
2196	if (ret) {	2347	if (ret) {
2197	DRM_WARN("Failed to set MP1 state prepare for reload\n");	2348	DRM_WARN("Failed to set MP1 state prepare for reload\n");
@@ -2562,10 +2713,12 @@ static int psp_resume(void *handle) · 364 unmodified lines
2562		2713
2563	DRM_INFO("PSP is resuming...\n");	2714	DRM_INFO("PSP is resuming...\n");
2564		2715
2565	ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME);	2716	if (psp->mem_train_ctx.enable_mem_training) {
2566	if (ret) {	2717	ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME);
2567	DRM_ERROR("Failed to process memory training!\n");	2718	if (ret) {
2568	return ret;	2719	DRM_ERROR("Failed to process memory training!\n");
		2720	return ret;
		2721	}
2569	}	2722	}
2570		2723
2571	mutex_lock(&adev->firmware.mutex);	2724	mutex_lock(&adev->firmware.mutex);
@@ -2749,7 +2902,7 @@ int psp_init_asd_microcode(struct psp_context *psp, · 177 unmodified lines
2749		2902
2750	asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;	2903	asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
2751	adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version);	2904	adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
2752	adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version);	2905	adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->sos.fw_version);
2753	adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes);	2906	adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
2754	adev->psp.asd_start_addr = (uint8_t *)asd_hdr +	2907	adev->psp.asd_start_addr = (uint8_t *)asd_hdr +
2755	le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);	2908	le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
@@ -2785,7 +2938,7 @@ int psp_init_toc_microcode(struct psp_context *psp, · 29 unmodified lines
2785		2938
2786	toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;	2939	toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
2787	adev->psp.toc_fw_version = le32_to_cpu(toc_hdr->header.ucode_version);	2940	adev->psp.toc_fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
2788	adev->psp.toc_feature_version = le32_to_cpu(toc_hdr->ucode_feature_version);	2941	adev->psp.toc_feature_version = le32_to_cpu(toc_hdr->sos.fw_version);
2789	adev->psp.toc_bin_size = le32_to_cpu(toc_hdr->header.ucode_size_bytes);	2942	adev->psp.toc_bin_size = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
2790	adev->psp.toc_start_addr = (uint8_t *)toc_hdr +	2943	adev->psp.toc_start_addr = (uint8_t *)toc_hdr +
2791	le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);	2944	le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
@@ -2797,6 +2950,50 @@ out: · 5 unmodified lines
2797	return err;	2950	return err;
2798	}	2951	}
2799		2952
		2953	static int psp_init_sos_base_fw(struct amdgpu_device *adev)
		2954	{
		2955	const struct psp_firmware_header_v1_0 *sos_hdr;
		2956	const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
		2957	uint8_t *ucode_array_start_addr;
		2958
		2959	sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
		2960	ucode_array_start_addr = (uint8_t *)sos_hdr +
		2961	le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
		2962
		2963	if (adev->gmc.xgmi.connected_to_cpu \|\| (adev->asic_type != CHIP_ALDEBARAN)) {
		2964	adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
		2965	adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->sos.fw_version);
		2966
		2967	adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos.offset_bytes);
		2968	adev->psp.sys_start_addr = ucode_array_start_addr;
		2969
		2970	adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos.size_bytes);
		2971	adev->psp.sos_start_addr = ucode_array_start_addr +
		2972	le32_to_cpu(sos_hdr->sos.offset_bytes);
		2973	} else {
		2974	/* Load alternate PSP SOS FW */
		2975	sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
		2976
		2977	adev->psp.sos_fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
		2978	adev->psp.sos_feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
		2979
		2980	adev->psp.sys_bin_size = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes);
		2981	adev->psp.sys_start_addr = ucode_array_start_addr +
		2982	le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes);
		2983
		2984	adev->psp.sos_bin_size = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes);
		2985	adev->psp.sos_start_addr = ucode_array_start_addr +
		2986	le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes);
		2987	}
		2988
		2989	if ((adev->psp.sys_bin_size == 0) \|\| (adev->psp.sos_bin_size == 0)) {
		2990	dev_warn(adev->dev, "PSP SOS FW not available");
		2991	return -EINVAL;
		2992	}
		2993
		2994	return 0;
		2995	}
		2996
2800	int psp_init_sos_microcode(struct psp_context *psp,	2997	int psp_init_sos_microcode(struct psp_context *psp,
2801	const char *chip_name)	2998	const char *chip_name)
2802	{	2999	{
@@ -2807,6 +3004,7 @@ int psp_init_sos_microcode(struct psp_context *psp, · 4 unmodified lines
2807	const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;	3004	const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
2808	const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;	3005	const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
2809	int err = 0;	3006	int err = 0;
		3007	uint8_t *ucode_array_start_addr;
2810		3008
2811	if (!chip_name) {	3009	if (!chip_name) {
2812	dev_err(adev->dev, "invalid chip name for sos microcode\n");	3010	dev_err(adev->dev, "invalid chip name for sos microcode\n");
@@ -2823,47 +3021,45 @@ int psp_init_sos_microcode(struct psp_context *psp, · 10 unmodified lines
2823	goto out;	3021	goto out;
2824		3022
2825	sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;	3023	sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
		3024	ucode_array_start_addr = (uint8_t *)sos_hdr +
		3025	le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
2826	amdgpu_ucode_print_psp_hdr(&sos_hdr->header);	3026	amdgpu_ucode_print_psp_hdr(&sos_hdr->header);
2827		3027
2828	switch (sos_hdr->header.header_version_major) {	3028	switch (sos_hdr->header.header_version_major) {
2829	case 1:	3029	case 1:
2830	adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version);	3030	err = psp_init_sos_base_fw(adev);
2831	adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version);	3031	if (err)
2832	adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes);	3032	goto out;
2833	adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos_offset_bytes);	3033
2834	adev->psp.sys_start_addr = (uint8_t *)sos_hdr +
2835	le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
2836	adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2837	le32_to_cpu(sos_hdr->sos_offset_bytes);
2838	if (sos_hdr->header.header_version_minor == 1) {	3034	if (sos_hdr->header.header_version_minor == 1) {
2839	sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;	3035	sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;
2840	adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc_size_bytes);	3036	adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes);
2841	adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr +	3037	adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2842	le32_to_cpu(sos_hdr_v1_1->toc_offset_bytes);	3038	le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes);
2843	adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb_size_bytes);	3039	adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes);
2844	adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +	3040	adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2845	le32_to_cpu(sos_hdr_v1_1->kdb_offset_bytes);	3041	le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes);
2846	}	3042	}
2847	if (sos_hdr->header.header_version_minor == 2) {	3043	if (sos_hdr->header.header_version_minor == 2) {
2848	sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;	3044	sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
2849	adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_2->kdb_size_bytes);	3045	adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes);
2850	adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +	3046	adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2851	le32_to_cpu(sos_hdr_v1_2->kdb_offset_bytes);	3047	le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes);
2852	}	3048	}
2853	if (sos_hdr->header.header_version_minor == 3) {	3049	if (sos_hdr->header.header_version_minor == 3) {
2854	sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;	3050	sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
2855	adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.toc_size_bytes);	3051	adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes);
2856	adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr +	3052	adev->psp.toc_start_addr = ucode_array_start_addr +
2857	le32_to_cpu(sos_hdr_v1_3->v1_1.toc_offset_bytes);	3053	le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes);
2858	adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb_size_bytes);	3054	adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes);
2859	adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +	3055	adev->psp.kdb_start_addr = ucode_array_start_addr +
2860	le32_to_cpu(sos_hdr_v1_3->v1_1.kdb_offset_bytes);	3056	le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes);
2861	adev->psp.spl_bin_size = le32_to_cpu(sos_hdr_v1_3->spl_size_bytes);	3057	adev->psp.spl_bin_size = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes);
2862	adev->psp.spl_start_addr = (uint8_t *)adev->psp.sys_start_addr +	3058	adev->psp.spl_start_addr = ucode_array_start_addr +
2863	le32_to_cpu(sos_hdr_v1_3->spl_offset_bytes);	3059	le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes);
2864	adev->psp.rl_bin_size = le32_to_cpu(sos_hdr_v1_3->rl_size_bytes);	3060	adev->psp.rl_bin_size = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes);
2865	adev->psp.rl_start_addr = (uint8_t *)adev->psp.sys_start_addr +	3061	adev->psp.rl_start_addr = ucode_array_start_addr +
2866	le32_to_cpu(sos_hdr_v1_3->rl_offset_bytes);	3062	le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes);
2867	}	3063	}
2868	break;	3064	break;
2869	default:	3065	default:

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h+57−0

@@ -225,6 +225,61 @@ struct psp_memory_training_context { · 224 unmodified lines
225		225
226	enum psp_memory_training_init_flag init;	226	enum psp_memory_training_init_flag init;
227	u32 training_cnt;	227	u32 training_cnt;
		228	bool enable_mem_training;
		229	};
		230
		231	/ PSP runtime DB /
		232	#define PSP_RUNTIME_DB_SIZE_IN_BYTES 0x10000
		233	#define PSP_RUNTIME_DB_OFFSET 0x100000
		234	#define PSP_RUNTIME_DB_COOKIE_ID 0x0ed5
		235	#define PSP_RUNTIME_DB_VER_1 0x0100
		236	#define PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT 0x40
		237
		238	enum psp_runtime_entry_type {
		239	PSP_RUNTIME_ENTRY_TYPE_INVALID = 0x0,
		240	PSP_RUNTIME_ENTRY_TYPE_TEST = 0x1,
		241	PSP_RUNTIME_ENTRY_TYPE_MGPU_COMMON = 0x2, /* Common mGPU runtime data */
		242	PSP_RUNTIME_ENTRY_TYPE_MGPU_WAFL = 0x3, /* WAFL runtime data */
		243	PSP_RUNTIME_ENTRY_TYPE_MGPU_XGMI = 0x4, /* XGMI runtime data */
		244	PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG = 0x5, /* Boot Config runtime data */
		245	};
		246
		247	/* PSP runtime DB header */
		248	struct psp_runtime_data_header {
		249	/* determine the existence of runtime db */
		250	uint16_t cookie;
		251	/* version of runtime db */
		252	uint16_t version;
		253	};
		254
		255	/* PSP runtime DB entry */
		256	struct psp_runtime_entry {
		257	/* type of runtime db entry */
		258	uint32_t entry_type;
		259	/* offset of entry in bytes */
		260	uint16_t offset;
		261	/* size of entry in bytes */
		262	uint16_t size;
		263	};
		264
		265	/* PSP runtime DB directory */
		266	struct psp_runtime_data_directory {
		267	/* number of valid entries */
		268	uint16_t entry_count;
		269	/* db entries*/
		270	struct psp_runtime_entry entry_list[PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT];
		271	};
		272
		273	/* PSP runtime DB boot config feature bitmask */
		274	enum psp_runtime_boot_cfg_feature {
		275	BOOT_CFG_FEATURE_GECC = 0x1,
		276	BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING = 0x2,
		277	};
		278
		279	/* PSP runtime DB boot config entry */
		280	struct psp_runtime_boot_cfg_entry {
		281	uint32_t boot_cfg_bitmask;
		282	uint32_t reserved;
228	};	283	};
229		284
230	struct psp_context	285	struct psp_context
@@ -325,6 +380,8 @@ struct psp_context · 94 unmodified lines
325	struct psp_securedisplay_context securedisplay_context;	380	struct psp_securedisplay_context securedisplay_context;
326	struct mutex mutex;	381	struct mutex mutex;
327	struct psp_memory_training_context mem_train_ctx;	382	struct psp_memory_training_context mem_train_ctx;
		383
		384	uint32_t boot_cfg_bitmask;
328	};	385	};
329		386
330	struct amdgpu_psp_funcs {	387	struct amdgpu_psp_funcs {

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c+1−1

@@ -2122,7 +2122,7 @@ static void amdgpu_ras_counte_dw(struct work_struct *work) · 2121 unmodified lines
2122	struct amdgpu_ras *con = container_of(work, struct amdgpu_ras,	2122	struct amdgpu_ras *con = container_of(work, struct amdgpu_ras,
2123	ras_counte_delay_work.work);	2123	ras_counte_delay_work.work);
2124	struct amdgpu_device *adev = con->adev;	2124	struct amdgpu_device *adev = con->adev;
2125	struct drm_device *dev = &adev->ddev;	2125	struct drm_device *dev = adev_to_drm(adev);
2126	unsigned long ce_count, ue_count;	2126	unsigned long ce_count, ue_count;
2127	int res;	2127	int res;
2128		2128

drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c+21−21

@@ -257,36 +257,36 @@ void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr) · 256 unmodified lines
257	container_of(hdr, struct psp_firmware_header_v1_0, header);	257	container_of(hdr, struct psp_firmware_header_v1_0, header);
258		258
259	DRM_DEBUG("ucode_feature_version: %u\n",	259	DRM_DEBUG("ucode_feature_version: %u\n",
260	le32_to_cpu(psp_hdr->ucode_feature_version));	260	le32_to_cpu(psp_hdr->sos.fw_version));
261	DRM_DEBUG("sos_offset_bytes: %u\n",	261	DRM_DEBUG("sos_offset_bytes: %u\n",
262	le32_to_cpu(psp_hdr->sos_offset_bytes));	262	le32_to_cpu(psp_hdr->sos.offset_bytes));
263	DRM_DEBUG("sos_size_bytes: %u\n",	263	DRM_DEBUG("sos_size_bytes: %u\n",
264	le32_to_cpu(psp_hdr->sos_size_bytes));	264	le32_to_cpu(psp_hdr->sos.size_bytes));
265	if (version_minor == 1) {	265	if (version_minor == 1) {
266	const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 =	266	const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 =
267	container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0);	267	container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0);
268	DRM_DEBUG("toc_header_version: %u\n",	268	DRM_DEBUG("toc_header_version: %u\n",
269	le32_to_cpu(psp_hdr_v1_1->toc_header_version));	269	le32_to_cpu(psp_hdr_v1_1->toc.fw_version));
270	DRM_DEBUG("toc_offset_bytes: %u\n",	270	DRM_DEBUG("toc_offset_bytes: %u\n",
271	le32_to_cpu(psp_hdr_v1_1->toc_offset_bytes));	271	le32_to_cpu(psp_hdr_v1_1->toc.offset_bytes));
272	DRM_DEBUG("toc_size_bytes: %u\n",	272	DRM_DEBUG("toc_size_bytes: %u\n",
273	le32_to_cpu(psp_hdr_v1_1->toc_size_bytes));	273	le32_to_cpu(psp_hdr_v1_1->toc.size_bytes));
274	DRM_DEBUG("kdb_header_version: %u\n",	274	DRM_DEBUG("kdb_header_version: %u\n",
275	le32_to_cpu(psp_hdr_v1_1->kdb_header_version));	275	le32_to_cpu(psp_hdr_v1_1->kdb.fw_version));
276	DRM_DEBUG("kdb_offset_bytes: %u\n",	276	DRM_DEBUG("kdb_offset_bytes: %u\n",
277	le32_to_cpu(psp_hdr_v1_1->kdb_offset_bytes));	277	le32_to_cpu(psp_hdr_v1_1->kdb.offset_bytes));
278	DRM_DEBUG("kdb_size_bytes: %u\n",	278	DRM_DEBUG("kdb_size_bytes: %u\n",
279	le32_to_cpu(psp_hdr_v1_1->kdb_size_bytes));	279	le32_to_cpu(psp_hdr_v1_1->kdb.size_bytes));
280	}	280	}
281	if (version_minor == 2) {	281	if (version_minor == 2) {
282	const struct psp_firmware_header_v1_2 *psp_hdr_v1_2 =	282	const struct psp_firmware_header_v1_2 *psp_hdr_v1_2 =
283	container_of(psp_hdr, struct psp_firmware_header_v1_2, v1_0);	283	container_of(psp_hdr, struct psp_firmware_header_v1_2, v1_0);
284	DRM_DEBUG("kdb_header_version: %u\n",	284	DRM_DEBUG("kdb_header_version: %u\n",
285	le32_to_cpu(psp_hdr_v1_2->kdb_header_version));	285	le32_to_cpu(psp_hdr_v1_2->kdb.fw_version));
286	DRM_DEBUG("kdb_offset_bytes: %u\n",	286	DRM_DEBUG("kdb_offset_bytes: %u\n",
287	le32_to_cpu(psp_hdr_v1_2->kdb_offset_bytes));	287	le32_to_cpu(psp_hdr_v1_2->kdb.offset_bytes));
288	DRM_DEBUG("kdb_size_bytes: %u\n",	288	DRM_DEBUG("kdb_size_bytes: %u\n",
289	le32_to_cpu(psp_hdr_v1_2->kdb_size_bytes));	289	le32_to_cpu(psp_hdr_v1_2->kdb.size_bytes));
290	}	290	}
291	if (version_minor == 3) {	291	if (version_minor == 3) {
292	const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 =	292	const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 =
@@ -294,23 +294,23 @@ void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr) · 1 unmodified line
294	const struct psp_firmware_header_v1_3 *psp_hdr_v1_3 =	294	const struct psp_firmware_header_v1_3 *psp_hdr_v1_3 =
295	container_of(psp_hdr_v1_1, struct psp_firmware_header_v1_3, v1_1);	295	container_of(psp_hdr_v1_1, struct psp_firmware_header_v1_3, v1_1);
296	DRM_DEBUG("toc_header_version: %u\n",	296	DRM_DEBUG("toc_header_version: %u\n",
297	le32_to_cpu(psp_hdr_v1_3->v1_1.toc_header_version));	297	le32_to_cpu(psp_hdr_v1_3->v1_1.toc.fw_version));
298	DRM_DEBUG("toc_offset_bytes: %u\n",	298	DRM_DEBUG("toc_offset_bytes: %u\n",
299	le32_to_cpu(psp_hdr_v1_3->v1_1.toc_offset_bytes));	299	le32_to_cpu(psp_hdr_v1_3->v1_1.toc.offset_bytes));
300	DRM_DEBUG("toc_size_bytes: %u\n",	300	DRM_DEBUG("toc_size_bytes: %u\n",
301	le32_to_cpu(psp_hdr_v1_3->v1_1.toc_size_bytes));	301	le32_to_cpu(psp_hdr_v1_3->v1_1.toc.size_bytes));
302	DRM_DEBUG("kdb_header_version: %u\n",	302	DRM_DEBUG("kdb_header_version: %u\n",
303	le32_to_cpu(psp_hdr_v1_3->v1_1.kdb_header_version));	303	le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.fw_version));
304	DRM_DEBUG("kdb_offset_bytes: %u\n",	304	DRM_DEBUG("kdb_offset_bytes: %u\n",
305	le32_to_cpu(psp_hdr_v1_3->v1_1.kdb_offset_bytes));	305	le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.offset_bytes));
306	DRM_DEBUG("kdb_size_bytes: %u\n",	306	DRM_DEBUG("kdb_size_bytes: %u\n",
307	le32_to_cpu(psp_hdr_v1_3->v1_1.kdb_size_bytes));	307	le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.size_bytes));
308	DRM_DEBUG("spl_header_version: %u\n",	308	DRM_DEBUG("spl_header_version: %u\n",
309	le32_to_cpu(psp_hdr_v1_3->spl_header_version));	309	le32_to_cpu(psp_hdr_v1_3->spl.fw_version));
310	DRM_DEBUG("spl_offset_bytes: %u\n",	310	DRM_DEBUG("spl_offset_bytes: %u\n",
311	le32_to_cpu(psp_hdr_v1_3->spl_offset_bytes));	311	le32_to_cpu(psp_hdr_v1_3->spl.offset_bytes));
312	DRM_DEBUG("spl_size_bytes: %u\n",	312	DRM_DEBUG("spl_size_bytes: %u\n",
313	le32_to_cpu(psp_hdr_v1_3->spl_size_bytes));	313	le32_to_cpu(psp_hdr_v1_3->spl.size_bytes));
314	}	314	}
315	} else {	315	} else {
316	DRM_ERROR("Unknown PSP ucode version: %u.%u\n",	316	DRM_ERROR("Unknown PSP ucode version: %u.%u\n",

drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h+15−19

         uint32_t pptable_entry_offset;
 };
+struct psp_fw_bin_desc {
+	uint32_t fw_version;
+	uint32_t offset_bytes;
+	uint32_t size_bytes;
+};
 /* version_major=1, version_minor=0 */
 struct psp_firmware_header_v1_0 {
 	struct common_firmware_header header;
-	uint32_t ucode_feature_version;
+	struct psp_fw_bin_desc sos;
-	uint32_t sos_offset_bytes;
-	uint32_t sos_size_bytes;
 };
 /* version_major=1, version_minor=1 */
 struct psp_firmware_header_v1_1 {
 	struct psp_firmware_header_v1_0 v1_0;
-	uint32_t toc_header_version;
+	struct psp_fw_bin_desc toc;
-	uint32_t toc_offset_bytes;
+	struct psp_fw_bin_desc kdb;
-	uint32_t toc_size_bytes;
-	uint32_t kdb_header_version;
-	uint32_t kdb_offset_bytes;
-	uint32_t kdb_size_bytes;
 };
 /* version_major=1, version_minor=2 */
 struct psp_firmware_header_v1_2 {
 	struct psp_firmware_header_v1_0 v1_0;
-	uint32_t reserve[3];
+	struct psp_fw_bin_desc res;
-	uint32_t kdb_header_version;
+	struct psp_fw_bin_desc kdb;
-	uint32_t kdb_offset_bytes;
-	uint32_t kdb_size_bytes;
 };
 /* version_major=1, version_minor=3 */
 struct psp_firmware_header_v1_3 {
 	struct psp_firmware_header_v1_1 v1_1;
-	uint32_t spl_header_version;
+	struct psp_fw_bin_desc spl;
-	uint32_t spl_offset_bytes;
+	struct psp_fw_bin_desc rl;
-	uint32_t spl_size_bytes;
+	struct psp_fw_bin_desc sys_drv_aux;
-	uint32_t rl_header_version;
+	struct psp_fw_bin_desc sos_aux;
-	uint32_t rl_offset_bytes;
-	uint32_t rl_size_bytes;
 };
 /* version_major=1, version_minor=0 */

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c+81−94

 	base->next = bo->vm_bo;
 	bo->vm_bo = base;
-	if (bo->tbo.base.resv != vm->root.base.bo->tbo.base.resv)
+	if (bo->tbo.base.resv != vm->root.bo->tbo.base.resv)
 		return;
 	vm->bulk_moveable = false;
  * Helper to get the parent entry for the child page table. NULL if we are at
  * the root page directory.
  */
-static struct amdgpu_vm_pt *amdgpu_vm_pt_parent(struct amdgpu_vm_pt *pt)
+static struct amdgpu_vm_bo_base *amdgpu_vm_pt_parent(struct amdgpu_vm_bo_base *pt)
 {
-	struct amdgpu_bo *parent = pt->base.bo->parent;
+	struct amdgpu_bo *parent = pt->bo->parent;
 	if (!parent)
 		return NULL;
-	return container_of(parent->vm_bo, struct amdgpu_vm_pt, base);
+	return parent->vm_bo;
 }
 /*
  */
 struct amdgpu_vm_pt_cursor {
 	uint64_t pfn;
-	struct amdgpu_vm_pt *parent;
+	struct amdgpu_vm_bo_base *parent;
-	struct amdgpu_vm_pt *entry;
+	struct amdgpu_vm_bo_base *entry;
 	unsigned level;
 };
 {
 	unsigned mask, shift, idx;
-	if (!cursor->entry->entries)
+	if ((cursor->level == AMDGPU_VM_PTB) || !cursor->entry ||
+	    !cursor->entry->bo)
 		return false;
-	BUG_ON(!cursor->entry->base.bo);
 	mask = amdgpu_vm_entries_mask(adev, cursor->level);
 	shift = amdgpu_vm_level_shift(adev, cursor->level);
 	++cursor->level;
 	idx = (cursor->pfn >> shift) & mask;
 	cursor->parent = cursor->entry;
-	cursor->entry = &cursor->entry->entries[idx];
+	cursor->entry = &to_amdgpu_bo_vm(cursor->entry->bo)->entries[idx];
 	return true;
 }
 	shift = amdgpu_vm_level_shift(adev, cursor->level - 1);
 	num_entries = amdgpu_vm_num_entries(adev, cursor->level - 1);
-	if (cursor->entry == &cursor->parent->entries[num_entries - 1])
+	if (cursor->entry == &to_amdgpu_bo_vm(cursor->parent->bo)->entries[num_entries - 1])
 		return false;
 	cursor->pfn += 1ULL << shift;
  * True when the search should continue, false otherwise.
  */
 static bool amdgpu_vm_pt_continue_dfs(struct amdgpu_vm_pt_cursor *start,
-				      struct amdgpu_vm_pt *entry)
+				      struct amdgpu_vm_bo_base *entry)
 {
 	return entry && (!start || entry != start->entry);
 }
 			 struct amdgpu_bo_list_entry *entry)
 {
 	entry->priority = 0;
-	entry->tv.bo = &vm->root.base.bo->tbo;
+	entry->tv.bo = &vm->root.bo->tbo;
 	/* Two for VM updates, one for TTM and one for the CS job */
 	entry->tv.num_shared = 4;
 	entry->user_pages = NULL;
 	for (bo_base = abo->vm_bo; bo_base; bo_base = bo_base->next) {
 		struct amdgpu_vm *vm = bo_base->vm;
-		if (abo->tbo.base.resv == vm->root.base.bo->tbo.base.resv)
+		if (abo->tbo.base.resv == vm->root.bo->tbo.base.resv)
 			vm->bulk_moveable = false;
 	}
 		entries -= ats_entries;
 	} else {
-		struct amdgpu_vm_pt *pt;
+		struct amdgpu_vm_bo_base *pt;
-		pt = container_of(ancestor->vm_bo, struct amdgpu_vm_pt, base);
+		pt = ancestor->vm_bo;
 		ats_entries = amdgpu_vm_num_ats_entries(adev);
-		if ((pt - vm->root.entries) >= ats_entries) {
+		if ((pt - to_amdgpu_bo_vm(vm->root.bo)->entries) >= ats_entries) {
 			ats_entries = 0;
 		} else {
 			ats_entries = entries;
 	bp.type = ttm_bo_type_kernel;
 	bp.no_wait_gpu = immediate;
-	if (vm->root.base.bo)
+	if (vm->root.bo)
-		bp.resv = vm->root.base.bo->tbo.base.resv;
+		bp.resv = vm->root.bo->tbo.base.resv;
 	r = amdgpu_bo_create_vm(adev, &bp, vmbo);
 	if (r)
 	}
 	(*vmbo)->shadow->parent = amdgpu_bo_ref(bo);
-	amdgpu_bo_add_to_shadow_list((*vmbo)->shadow);
+	amdgpu_bo_add_to_shadow_list(*vmbo);
 	return 0;
 }
 			       struct amdgpu_vm_pt_cursor *cursor,
 			       bool immediate)
 {
-	struct amdgpu_vm_pt *entry = cursor->entry;
+	struct amdgpu_vm_bo_base *entry = cursor->entry;
 	struct amdgpu_bo *pt_bo;
 	struct amdgpu_bo_vm *pt;
 	int r;
-	if (entry->base.bo) {
+	if (entry->bo)
-		if (cursor->level < AMDGPU_VM_PTB)
-			entry->entries =
-				to_amdgpu_bo_vm(entry->base.bo)->entries;
-		else
-			entry->entries = NULL;
 		return 0;
-	}
 	r = amdgpu_vm_pt_create(adev, vm, cursor->level, immediate, &pt);
 	if (r)
 	 * freeing them up in the wrong order.
 	 */
 	pt_bo = &pt->bo;
-	pt_bo->parent = amdgpu_bo_ref(cursor->parent->base.bo);
+	pt_bo->parent = amdgpu_bo_ref(cursor->parent->bo);
-	amdgpu_vm_bo_base_init(&entry->base, vm, pt_bo);
+	amdgpu_vm_bo_base_init(entry, vm, pt_bo);
-	if (cursor->level < AMDGPU_VM_PTB)
-		entry->entries = pt->entries;
-	else
-		entry->entries = NULL;
 	r = amdgpu_vm_clear_bo(adev, vm, pt, immediate);
 	if (r)
 		goto error_free_pt;
  *
  * @entry: PDE to free
  */
-static void amdgpu_vm_free_table(struct amdgpu_vm_pt *entry)
+static void amdgpu_vm_free_table(struct amdgpu_vm_bo_base *entry)
 {
 	struct amdgpu_bo *shadow;
-	if (entry->base.bo) {
+	if (!entry->bo)
-		shadow = amdgpu_bo_shadowed(entry->base.bo);
+		return;
-		entry->base.bo->vm_bo = NULL;
+	shadow = amdgpu_bo_shadowed(entry->bo);
-		list_del(&entry->base.vm_status);
+	entry->bo->vm_bo = NULL;
-		amdgpu_bo_unref(&shadow);
+	list_del(&entry->vm_status);
-		amdgpu_bo_unref(&entry->base.bo);
+	amdgpu_bo_unref(&shadow);
-	}
+	amdgpu_bo_unref(&entry->bo);
-	entry->entries = NULL;
 }
 /**
 			       struct amdgpu_vm_pt_cursor *start)
 {
 	struct amdgpu_vm_pt_cursor cursor;
-	struct amdgpu_vm_pt *entry;
+	struct amdgpu_vm_bo_base *entry;
 	vm->bulk_moveable = false;
  */
 static int amdgpu_vm_update_pde(struct amdgpu_vm_update_params *params,
 				struct amdgpu_vm *vm,
-				struct amdgpu_vm_pt *entry)
+				struct amdgpu_vm_bo_base *entry)
 {
-	struct amdgpu_vm_pt *parent = amdgpu_vm_pt_parent(entry);
+	struct amdgpu_vm_bo_base *parent = amdgpu_vm_pt_parent(entry);
-	struct amdgpu_bo *bo = parent->base.bo, *pbo;
+	struct amdgpu_bo *bo = parent->bo, *pbo;
 	uint64_t pde, pt, flags;
 	unsigned level;
 		pbo = pbo->parent;
 	level += params->adev->vm_manager.root_level;
-	amdgpu_gmc_get_pde_for_bo(entry->base.bo, level, &pt, &flags);
+	amdgpu_gmc_get_pde_for_bo(entry->bo, level, &pt, &flags);
-	pde = (entry - parent->entries) * 8;
+	pde = (entry - to_amdgpu_bo_vm(parent->bo)->entries) * 8;
 	return vm->update_funcs->update(params, to_amdgpu_bo_vm(bo), pde, pt,
 					1, 0, flags);
 }
 				     struct amdgpu_vm *vm)
 {
 	struct amdgpu_vm_pt_cursor cursor;
-	struct amdgpu_vm_pt *entry;
+	struct amdgpu_vm_bo_base *entry;
 	for_each_amdgpu_vm_pt_dfs_safe(adev, vm, NULL, cursor, entry)
-		if (entry->base.bo && !entry->base.moved)
+		if (entry->bo && !entry->moved)
-			amdgpu_vm_bo_relocated(&entry->base);
+			amdgpu_vm_bo_relocated(entry);
 }
 /**
 		return r;
 	while (!list_empty(&vm->relocated)) {
-		struct amdgpu_vm_pt *entry;
+		struct amdgpu_vm_bo_base *entry;
-		entry = list_first_entry(&vm->relocated, struct amdgpu_vm_pt,
+		entry = list_first_entry(&vm->relocated,
-					 base.vm_status);
+					 struct amdgpu_vm_bo_base,
-		amdgpu_vm_bo_idle(&entry->base);
+					 vm_status);
+		amdgpu_vm_bo_idle(entry);
 		r = amdgpu_vm_update_pde(&params, vm, entry);
 		if (r)
 			continue;
 		}
-		pt = cursor.entry->base.bo;
+		pt = cursor.entry->bo;
 		if (!pt) {
 			/* We need all PDs and PTs for mapping something, */
 			if (flags & AMDGPU_PTE_VALID)
 			if (!amdgpu_vm_pt_ancestor(&cursor))
 				return -EINVAL;
-			pt = cursor.entry->base.bo;
+			pt = cursor.entry->bo;
 			shift = parent_shift;
 			frag_end = max(frag_end, ALIGN(frag_start + 1,
 				   1ULL << shift));
 			 */
 			while (cursor.pfn < frag_start) {
 				/* Make sure previous mapping is freed */
-				if (cursor.entry->base.bo) {
+				if (cursor.entry->bo) {
 					params->table_freed = true;
 					amdgpu_vm_free_pts(adev, params->vm, &cursor);
 				}
 	if (!unlocked && !dma_fence_is_signaled(vm->last_unlocked)) {
 		struct dma_fence *tmp = dma_fence_get_stub();
-		amdgpu_bo_fence(vm->root.base.bo, vm->last_unlocked, true);
+		amdgpu_bo_fence(vm->root.bo, vm->last_unlocked, true);
 		swap(vm->last_unlocked, tmp);
 		dma_fence_put(tmp);
 	}
 	if (clear || !bo) {
 		mem = NULL;
-		resv = vm->root.base.bo->tbo.base.resv;
+		resv = vm->root.bo->tbo.base.resv;
 	} else {
 		struct drm_gem_object *obj = &bo->tbo.base;
 	}
 	if (clear || (bo && bo->tbo.base.resv ==
-		      vm->root.base.bo->tbo.base.resv))
+		      vm->root.bo->tbo.base.resv))
 		last_update = &vm->last_update;
 	else
 		last_update = &bo_va->last_pt_update;
 	 * the evicted list so that it gets validated again on the
 	 * next command submission.
 	 */
-	if (bo && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv) {
+	if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv) {
 		uint32_t mem_type = bo->tbo.resource->mem_type;
 		if (!(bo->preferred_domains &
  */
 static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
 {
-	struct dma_resv *resv = vm->root.base.bo->tbo.base.resv;
+	struct dma_resv *resv = vm->root.bo->tbo.base.resv;
 	struct dma_fence *excl, **shared;
 	unsigned i, shared_count;
 	int r;
 			  struct amdgpu_vm *vm,
 			  struct dma_fence **fence)
 {
-	struct dma_resv *resv = vm->root.base.bo->tbo.base.resv;
+	struct dma_resv *resv = vm->root.bo->tbo.base.resv;
 	struct amdgpu_bo_va_mapping *mapping;
 	uint64_t init_pte_value = 0;
 	struct dma_fence *f = NULL;
 	if (mapping->flags & AMDGPU_PTE_PRT)
 		amdgpu_vm_prt_get(adev);
-	if (bo && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv &&
+	if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv &&
 	    !bo_va->base.moved) {
 		list_move(&bo_va->base.vm_status, &vm->moved);
 	}
 	struct amdgpu_vm_bo_base **base;
 	if (bo) {
-		if (bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv)
+		if (bo->tbo.base.resv == vm->root.bo->tbo.base.resv)
 			vm->bulk_moveable = false;
 		for (base = &bo_va->base.bo->vm_bo; *base;
 	for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
 		struct amdgpu_vm *vm = bo_base->vm;
-		if (evicted && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv) {
+		if (evicted && bo->tbo.base.resv == vm->root.bo->tbo.base.resv) {
 			amdgpu_vm_bo_evicted(bo_base);
 			continue;
 		}
 		if (bo->tbo.type == ttm_bo_type_kernel)
 			amdgpu_vm_bo_relocated(bo_base);
-		else if (bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv)
+		else if (bo->tbo.base.resv == vm->root.bo->tbo.base.resv)
 			amdgpu_vm_bo_moved(bo_base);
 		else
 			amdgpu_vm_bo_invalidated(bo_base);
  */
 long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout)
 {
-	timeout = dma_resv_wait_timeout(vm->root.base.bo->tbo.base.resv, true,
+	timeout = dma_resv_wait_timeout(vm->root.bo->tbo.base.resv, true,
 					true, timeout);
 	if (timeout <= 0)
 		return timeout;
 	if (r)
 		goto error_unreserve;
-	amdgpu_vm_bo_base_init(&vm->root.base, vm, root_bo);
+	amdgpu_vm_bo_base_init(&vm->root, vm, root_bo);
 	r = amdgpu_vm_clear_bo(adev, vm, root, false);
 	if (r)
 		goto error_unreserve;
-	amdgpu_bo_unreserve(vm->root.base.bo);
+	amdgpu_bo_unreserve(vm->root.bo);
 	if (pasid) {
 		unsigned long flags;
 	return 0;
 error_unreserve:
-	amdgpu_bo_unreserve(vm->root.base.bo);
+	amdgpu_bo_unreserve(vm->root.bo);
 error_free_root:
 	amdgpu_bo_unref(&root->shadow);
 	amdgpu_bo_unref(&root_bo);
-	vm->root.base.bo = NULL;
+	vm->root.bo = NULL;
 error_free_delayed:
 	dma_fence_put(vm->last_unlocked);
  *	0 if this VM is clean
  */
 static int amdgpu_vm_check_clean_reserved(struct amdgpu_device *adev,
-	struct amdgpu_vm *vm)
+					  struct amdgpu_vm *vm)
 {
 	enum amdgpu_vm_level root = adev->vm_manager.root_level;
 	unsigned int entries = amdgpu_vm_num_entries(adev, root);
 	unsigned int i = 0;
-	if (!(vm->root.entries))
-		return 0;
 	for (i = 0; i < entries; i++) {
-		if (vm->root.entries[i].base.bo)
+		if (to_amdgpu_bo_vm(vm->root.bo)->entries[i].bo)
 			return -EINVAL;
 	}
 	bool pte_support_ats = (adev->asic_type == CHIP_RAVEN);
 	int r;
-	r = amdgpu_bo_reserve(vm->root.base.bo, true);
+	r = amdgpu_bo_reserve(vm->root.bo, true);
 	if (r)
 		return r;
 	if (pte_support_ats != vm->pte_support_ats) {
 		vm->pte_support_ats = pte_support_ats;
 		r = amdgpu_vm_clear_bo(adev, vm,
-				       to_amdgpu_bo_vm(vm->root.base.bo),
+				       to_amdgpu_bo_vm(vm->root.bo),
 				       false);
 		if (r)
 			goto free_idr;
 	if (vm->use_cpu_for_update) {
 		/* Sync with last SDMA update/clear before switching to CPU */
-		r = amdgpu_bo_sync_wait(vm->root.base.bo,
+		r = amdgpu_bo_sync_wait(vm->root.bo,
 					AMDGPU_FENCE_OWNER_UNDEFINED, true);
 		if (r)
 			goto free_idr;
 	}
 	/* Free the shadow bo for compute VM */
-	amdgpu_bo_unref(&to_amdgpu_bo_vm(vm->root.base.bo)->shadow);
+	amdgpu_bo_unref(&to_amdgpu_bo_vm(vm->root.bo)->shadow);
 	if (pasid)
 		vm->pasid = pasid;
 		spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
 	}
 unreserve_bo:
-	amdgpu_bo_unreserve(vm->root.base.bo);
+	amdgpu_bo_unreserve(vm->root.bo);
 	return r;
 }
 	amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm);
-	root = amdgpu_bo_ref(vm->root.base.bo);
+	root = amdgpu_bo_ref(vm->root.bo);
 	amdgpu_bo_reserve(root, true);
 	if (vm->pasid) {
 		unsigned long flags;
 	amdgpu_vm_free_pts(adev, vm, NULL);
 	amdgpu_bo_unreserve(root);
 	amdgpu_bo_unref(&root);
-	WARN_ON(vm->root.base.bo);
+	WARN_ON(vm->root.bo);
 	drm_sched_entity_destroy(&vm->immediate);
 	drm_sched_entity_destroy(&vm->delayed);
 		/* Wait vm idle to make sure the vmid set in SPM_VMID is
 		 * not referenced anymore.
 		 */
-		r = amdgpu_bo_reserve(fpriv->vm.root.base.bo, true);
+		r = amdgpu_bo_reserve(fpriv->vm.root.bo, true);
 		if (r)
 			return r;
 		if (r < 0)
 			return r;
-		amdgpu_bo_unreserve(fpriv->vm.root.base.bo);
+		amdgpu_bo_unreserve(fpriv->vm.root.bo);
 		amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB_0);
 		break;
 	default:
 {
 	bool is_compute_context = false;
 	struct amdgpu_bo *root;
+	unsigned long irqflags;
 	uint64_t value, flags;
 	struct amdgpu_vm *vm;
 	int r;
-	spin_lock(&adev->vm_manager.pasid_lock);
+	spin_lock_irqsave(&adev->vm_manager.pasid_lock, irqflags);
 	vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
 	if (vm) {
-		root = amdgpu_bo_ref(vm->root.base.bo);
+		root = amdgpu_bo_ref(vm->root.bo);
 		is_compute_context = vm->is_compute_context;
 	} else {
 		root = NULL;
 	}
-	spin_unlock(&adev->vm_manager.pasid_lock);
+	spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, irqflags);
 	if (!root)
 		return false;
 		goto error_unref;
 	/* Double check that the VM still exists */
-	spin_lock(&adev->vm_manager.pasid_lock);
+	spin_lock_irqsave(&adev->vm_manager.pasid_lock, irqflags);
 	vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
-	if (vm && vm->root.base.bo != root)
+	if (vm && vm->root.bo != root)
 		vm = NULL;
-	spin_unlock(&adev->vm_manager.pasid_lock);
+	spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, irqflags);
 	if (!vm)
 		goto error_unlock;

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h+1−8

 	bool				moved;
 };
-struct amdgpu_vm_pt {
-	struct amdgpu_vm_bo_base	base;
-	/* array of page tables, one for each directory entry */
-	struct amdgpu_vm_pt		*entries;
-};
 /* provided by hw blocks that can write ptes, e.g., sdma */
 struct amdgpu_vm_pte_funcs {
 	/* number of dw to reserve per operation */
 	struct list_head        done;
 	/* contains the page directory */
-	struct amdgpu_vm_pt     root;
+	struct amdgpu_vm_bo_base     root;
 	struct dma_fence	*last_update;
 	/* Scheduler entities for page table updates */

drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c+1−1

@@ -112,7 +112,7 @@ static int amdgpu_vm_sdma_commit(struct amdgpu_vm_update_params *p, · 111 unmodified lines
112	swap(p->vm->last_unlocked, f);	112	swap(p->vm->last_unlocked, f);
113	dma_fence_put(tmp);	113	dma_fence_put(tmp);
114	} else {	114	} else {
115	amdgpu_bo_fence(p->vm->root.base.bo, f, true);	115	amdgpu_bo_fence(p->vm->root.bo, f, true);
116	}	116	}
117		117
118	if (fence && !p->immediate)	118	if (fence && !p->immediate)

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c+5−1

 	if (ring->use_doorbell) {
 		WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
 			(adev->doorbell_index.kiq * 2) << 2);
+		/* If GC has entered CGPG, ringing doorbell > first page doesn't
+		 * wakeup GC. Enlarge CP_MEC_DOORBELL_RANGE_UPPER to workaround
+		 * this issue.
+		 */
 		WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
-			(adev->doorbell_index.userqueue_end * 2) << 2);
+			(adev->doorbell.size - 4));
 	}
 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c+5−1

 	if (ring->use_doorbell) {
 		WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
 					(adev->doorbell_index.kiq * 2) << 2);
+		/* If GC has entered CGPG, ringing doorbell > first page doesn't
+		 * wakeup GC. Enlarge CP_MEC_DOORBELL_RANGE_UPPER to workaround
+		 * this issue.
+		 */
 		WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
-					(adev->doorbell_index.userqueue_end * 2) << 2);
+					(adev->doorbell.size - 4));
 	}
 	WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,

drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h+9−4

     uint32_t fwar_db_addr_hi;
 };
+/* Command-specific response for boot config. */
+struct psp_gfx_uresp_bootcfg {
+	uint32_t boot_cfg;	/* boot config data */
+};
 /* Union of command-specific responses for GPCOM ring. */
-union psp_gfx_uresp
+union psp_gfx_uresp {
-{
+	struct psp_gfx_uresp_reserved		reserved;
-    struct psp_gfx_uresp_reserved reserved;
+	struct psp_gfx_uresp_bootcfg		boot_cfg;
-    struct psp_gfx_uresp_fwar_db_info fwar_db_info;
+	struct psp_gfx_uresp_fwar_db_info	fwar_db_info;
 };
 /* Structure of GFX Response buffer.

drivers/gpu/drm/amd/amdgpu/psp_v11_0.c+1−0

@@ -461,6 +461,7 @@ static int psp_v11_0_ring_create(struct psp_context *psp, · 460 unmodified lines
461	struct amdgpu_device *adev = psp->adev;	461	struct amdgpu_device *adev = psp->adev;
462		462
463	if (amdgpu_sriov_vf(adev)) {	463	if (amdgpu_sriov_vf(adev)) {
		464	ring->ring_wptr = 0;
464	ret = psp_v11_0_ring_stop(psp, ring_type);	465	ret = psp_v11_0_ring_stop(psp, ring_type);
465	if (ret) {	466	if (ret) {
466	DRM_ERROR("psp_v11_0_ring_stop_sriov failed!\n");	467	DRM_ERROR("psp_v11_0_ring_stop_sriov failed!\n");

drivers/gpu/drm/amd/amdgpu/psp_v3_1.c+1−0

@@ -227,6 +227,7 @@ static int psp_v3_1_ring_create(struct psp_context *psp, · 226 unmodified lines
227	psp_v3_1_reroute_ih(psp);	227	psp_v3_1_reroute_ih(psp);
228		228
229	if (amdgpu_sriov_vf(adev)) {	229	if (amdgpu_sriov_vf(adev)) {
		230	ring->ring_wptr = 0;
230	ret = psp_v3_1_ring_stop(psp, ring_type);	231	ret = psp_v3_1_ring_stop(psp, ring_type);
231	if (ret) {	232	if (ret) {
232	DRM_ERROR("psp_v3_1_ring_stop_sriov failed!\n");	233	DRM_ERROR("psp_v3_1_ring_stop_sriov failed!\n");

drivers/gpu/drm/amd/amdkfd/kfd_chardev.c+20−6

 			       i, args->n_devices);
 			goto unmap_memory_from_gpu_failed;
 		}
-		kfd_flush_tlb(peer_pdd, TLB_FLUSH_HEAVYWEIGHT);
 		args->n_success = i+1;
 	}
-	kfree(devices_arr);
 	mutex_unlock(&p->mutex);
+	err = amdgpu_amdkfd_gpuvm_sync_memory(dev->kgd, (struct kgd_mem *) mem, true);
+	if (err) {
+		pr_debug("Sync memory failed, wait interrupted by user signal\n");
+		goto sync_memory_failed;
+	}
+	/* Flush TLBs after waiting for the page table updates to complete */
+	for (i = 0; i < args->n_devices; i++) {
+		peer = kfd_device_by_id(devices_arr[i]);
+		if (WARN_ON_ONCE(!peer))
+			continue;
+		peer_pdd = kfd_get_process_device_data(peer, p);
+		if (WARN_ON_ONCE(!peer_pdd))
+			continue;
+		kfd_flush_tlb(peer_pdd, TLB_FLUSH_HEAVYWEIGHT);
+	}
+	kfree(devices_arr);
 	return 0;
 bind_process_to_device_failed:
 unmap_memory_from_gpu_failed:
 	mutex_unlock(&p->mutex);
 copy_from_user_failed:
+sync_memory_failed:
 	kfree(devices_arr);
 	return err;
 }
 	struct kfd_ioctl_svm_args *args = data;
 	int r = 0;
-	if (p->svm_disabled)
-		return -EPERM;
 	pr_debug("start 0x%llx size 0x%llx op 0x%x nattr 0x%x\n",
 		 args->start_addr, args->size, args->op, args->nattr);

drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c+26−20

@@ -486,9 +486,6 @@ static int destroy_queue_nocpsch_locked(struct device_queue_manager *dqm, · 485 unmodified lines
486	if (retval == -ETIME)	486	if (retval == -ETIME)
487	qpd->reset_wavefronts = true;	487	qpd->reset_wavefronts = true;
488		488
489
490	mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
491
492	list_del(&q->list);	489	list_del(&q->list);
493	if (list_empty(&qpd->queues_list)) {	490	if (list_empty(&qpd->queues_list)) {
494	if (qpd->reset_wavefronts) {	491	if (qpd->reset_wavefronts) {
@@ -523,6 +520,8 @@ static int destroy_queue_nocpsch(struct device_queue_manager *dqm, · 28 unmodified lines
523	int retval;	520	int retval;
524	uint64_t sdma_val = 0;	521	uint64_t sdma_val = 0;
525	struct kfd_process_device *pdd = qpd_to_pdd(qpd);	522	struct kfd_process_device *pdd = qpd_to_pdd(qpd);
		523	struct mqd_manager *mqd_mgr =
		524	dqm->mqd_mgrs[get_mqd_type_from_queue_type(q->properties.type)];
526		525
527	/* Get the SDMA queue stats */	526	/* Get the SDMA queue stats */
528	if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) \|\|	527	if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) \|\|
@@ -540,6 +539,8 @@ static int destroy_queue_nocpsch(struct device_queue_manager *dqm, · 11 unmodified lines
540	pdd->sdma_past_activity_counter += sdma_val;	539	pdd->sdma_past_activity_counter += sdma_val;
541	dqm_unlock(dqm);	540	dqm_unlock(dqm);
542		541
		542	mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
		543
543	return retval;	544	return retval;
544	}	545	}
545		546
@@ -1629,7 +1630,7 @@ out: · 1083 unmodified lines
1629	static int process_termination_nocpsch(struct device_queue_manager *dqm,	1630	static int process_termination_nocpsch(struct device_queue_manager *dqm,
1630	struct qcm_process_device *qpd)	1631	struct qcm_process_device *qpd)
1631	{	1632	{
1632	struct queue q, next;	1633	struct queue *q;
1633	struct device_process_node cur, next_dpn;	1634	struct device_process_node cur, next_dpn;
1634	int retval = 0;	1635	int retval = 0;
1635	bool found = false;	1636	bool found = false;
@@ -1637,12 +1638,19 @@ static int process_termination_nocpsch(struct device_queue_manager *dqm, · 1 unmodified line
1637	dqm_lock(dqm);	1638	dqm_lock(dqm);
1638		1639
1639	/* Clear all user mode queues */	1640	/* Clear all user mode queues */
1640	list_for_each_entry_safe(q, next, &qpd->queues_list, list) {	1641	while (!list_empty(&qpd->queues_list)) {
		1642	struct mqd_manager *mqd_mgr;
1641	int ret;	1643	int ret;
1642		1644
		1645	q = list_first_entry(&qpd->queues_list, struct queue, list);
		1646	mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
		1647	q->properties.type)];
1643	ret = destroy_queue_nocpsch_locked(dqm, qpd, q);	1648	ret = destroy_queue_nocpsch_locked(dqm, qpd, q);
1644	if (ret)	1649	if (ret)
1645	retval = ret;	1650	retval = ret;
		1651	dqm_unlock(dqm);
		1652	mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
		1653	dqm_lock(dqm);
1646	}	1654	}
1647		1655
1648	/* Unregister process */	1656	/* Unregister process */
@@ -1674,29 +1682,27 @@ static int get_wave_state(struct device_queue_manager *dqm, · 25 unmodified lines
1674	u32 *save_area_used_size)	1682	u32 *save_area_used_size)
1675	{	1683	{
1676	struct mqd_manager *mqd_mgr;	1684	struct mqd_manager *mqd_mgr;
1677	int r;
1678		1685
1679	dqm_lock(dqm);	1686	dqm_lock(dqm);
1680		1687
1681	if (q->properties.type != KFD_QUEUE_TYPE_COMPUTE \|\|
1682	q->properties.is_active \|\| !q->device->cwsr_enabled) {
1683	r = -EINVAL;
1684	goto dqm_unlock;
1685	}
1686
1687	mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_CP];	1688	mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_CP];
1688		1689
1689	if (!mqd_mgr->get_wave_state) {	1690	if (q->properties.type != KFD_QUEUE_TYPE_COMPUTE \|\|
1690	r = -EINVAL;	1691	q->properties.is_active \|\| !q->device->cwsr_enabled \|\|
1691	goto dqm_unlock;	1692	!mqd_mgr->get_wave_state) {
		1693	dqm_unlock(dqm);
		1694	return -EINVAL;
1692	}	1695	}
1693		1696
1694	r = mqd_mgr->get_wave_state(mqd_mgr, q->mqd, ctl_stack,
1695	ctl_stack_used_size, save_area_used_size);
1696
1697	dqm_unlock:
1698	dqm_unlock(dqm);	1697	dqm_unlock(dqm);
1699	return r;	1698
		1699	/*
		1700	* get_wave_state is outside the dqm lock to prevent circular locking
		1701	* and the queue should be protected against destruction by the process
		1702	* lock.
		1703	*/
		1704	return mqd_mgr->get_wave_state(mqd_mgr, q->mqd, ctl_stack,
		1705	ctl_stack_used_size, save_area_used_size);
1700	}	1706	}
1701		1707
1702	static int process_termination_cpsch(struct device_queue_manager *dqm,	1708	static int process_termination_cpsch(struct device_queue_manager *dqm,

drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c+0−4

 			case CHIP_POLARIS12:
 			case CHIP_VEGAM:
 				kfd_init_apertures_vi(pdd, id);
-				/* VI GPUs cannot support SVM with only
-				 * 40 bits of virtual address space.
-				 */
-				process->svm_disabled = true;
 				break;
 			case CHIP_VEGA10:
 			case CHIP_VEGA12:

drivers/gpu/drm/amd/amdkfd/kfd_priv.h+1−1

 	spinlock_t			deferred_list_lock;
 	atomic_t			evicted_ranges;
 	struct delayed_work		restore_work;
+	DECLARE_BITMAP(bitmap_supported, MAX_GPU_INSTANCE);
 };
 /* Process data */
 	/* shared virtual memory registered by this process */
 	struct svm_range_list svms;
-	bool svm_disabled;
 	bool xnack_enabled;
 };

drivers/gpu/drm/amd/amdkfd/kfd_process.c+0−1

@@ -1260,7 +1260,6 @@ static struct kfd_process create_process(const struct task_struct thread) · 1259 unmodified lines
1260	process->mm = thread->mm;	1260	process->mm = thread->mm;
1261	process->lead_thread = thread->group_leader;	1261	process->lead_thread = thread->group_leader;
1262	process->n_pdds = 0;	1262	process->n_pdds = 0;
1263	process->svm_disabled = false;
1264	INIT_DELAYED_WORK(&process->eviction_work, evict_process_worker);	1263	INIT_DELAYED_WORK(&process->eviction_work, evict_process_worker);
1265	INIT_DELAYED_WORK(&process->restore_work, restore_process_worker);	1264	INIT_DELAYED_WORK(&process->restore_work, restore_process_worker);
1266	process->last_restore_timestamp = get_jiffies_64();	1265	process->last_restore_timestamp = get_jiffies_64();

drivers/gpu/drm/amd/amdkfd/kfd_svm.c+36−26

 	p = container_of(svms, struct kfd_process, svms);
 	if (p->xnack_enabled)
-		bitmap_fill(prange->bitmap_access, MAX_GPU_INSTANCE);
+		bitmap_copy(prange->bitmap_access, svms->bitmap_supported,
+			    MAX_GPU_INSTANCE);
 	svm_range_set_default_attributes(&prange->preferred_loc,
 					 &prange->prefetch_loc,
 		     uint32_t nattr, struct kfd_ioctl_svm_attribute *attrs)
 {
 	uint32_t i;
-	int gpuidx;
 	for (i = 0; i < nattr; i++) {
+		uint32_t val = attrs[i].value;
+		int gpuidx = MAX_GPU_INSTANCE;
 		switch (attrs[i].type) {
 		case KFD_IOCTL_SVM_ATTR_PREFERRED_LOC:
-			if (attrs[i].value != KFD_IOCTL_SVM_LOCATION_SYSMEM &&
+			if (val != KFD_IOCTL_SVM_LOCATION_SYSMEM &&
-			    attrs[i].value != KFD_IOCTL_SVM_LOCATION_UNDEFINED &&
+			    val != KFD_IOCTL_SVM_LOCATION_UNDEFINED)
-			    kfd_process_gpuidx_from_gpuid(p,
+				gpuidx = kfd_process_gpuidx_from_gpuid(p, val);
-							  attrs[i].value) < 0) {
-				pr_debug("no GPU 0x%x found\n", attrs[i].value);
-				return -EINVAL;
-			}
 			break;
 		case KFD_IOCTL_SVM_ATTR_PREFETCH_LOC:
-			if (attrs[i].value != KFD_IOCTL_SVM_LOCATION_SYSMEM &&
+			if (val != KFD_IOCTL_SVM_LOCATION_SYSMEM)
-			    kfd_process_gpuidx_from_gpuid(p,
+				gpuidx = kfd_process_gpuidx_from_gpuid(p, val);
-							  attrs[i].value) < 0) {
-				pr_debug("no GPU 0x%x found\n", attrs[i].value);
-				return -EINVAL;
-			}
 			break;
 		case KFD_IOCTL_SVM_ATTR_ACCESS:
 		case KFD_IOCTL_SVM_ATTR_ACCESS_IN_PLACE:
 		case KFD_IOCTL_SVM_ATTR_NO_ACCESS:
-			gpuidx = kfd_process_gpuidx_from_gpuid(p,
+			gpuidx = kfd_process_gpuidx_from_gpuid(p, val);
-							       attrs[i].value);
-			if (gpuidx < 0) {
-				pr_debug("no GPU 0x%x found\n", attrs[i].value);
-				return -EINVAL;
-			}
 			break;
 		case KFD_IOCTL_SVM_ATTR_SET_FLAGS:
 			break;
 			pr_debug("unknown attr type 0x%x\n", attrs[i].type);
 			return -EINVAL;
 		}
+		if (gpuidx < 0) {
+			pr_debug("no GPU 0x%x found\n", val);
+			return -EINVAL;
+		} else if (gpuidx < MAX_GPU_INSTANCE &&
+			   !test_bit(gpuidx, p->svms.bitmap_supported)) {
+			pr_debug("GPU 0x%x not supported\n", val);
+			return -EINVAL;
+		}
 	}
 	return 0;
 		adev = (struct amdgpu_device *)pdd->dev->kgd;
 		vm = drm_priv_to_vm(pdd->drm_priv);
-		ctx->tv[gpuidx].bo = &vm->root.base.bo->tbo;
+		ctx->tv[gpuidx].bo = &vm->root.bo->tbo;
 		ctx->tv[gpuidx].num_shared = 4;
 		list_add(&ctx->tv[gpuidx].head, &ctx->validate_list);
 	}
 	p = container_of(svms, struct kfd_process, svms);
-	for (i = 0; i < p->n_pdds; i++) {
+	for_each_set_bit(i, svms->bitmap_supported, p->n_pdds) {
 		pdd = p->pdds[i];
 		if (!pdd)
 			continue;
 	bool write_locked = false;
 	int r = 0;
+	if (!KFD_IS_SVM_API_SUPPORTED(adev->kfd.dev)) {
+		pr_debug("device does not support SVM\n");
+		return -EFAULT;
+	}
 	p = kfd_lookup_process_by_pasid(pasid);
 	if (!p) {
 		pr_debug("kfd process not founded pasid 0x%x\n", pasid);
 int svm_range_list_init(struct kfd_process *p)
 {
 	struct svm_range_list *svms = &p->svms;
+	int i;
 	svms->objects = RB_ROOT_CACHED;
 	mutex_init(&svms->lock);
 	INIT_LIST_HEAD(&svms->deferred_range_list);
 	spin_lock_init(&svms->deferred_list_lock);
+	for (i = 0; i < p->n_pdds; i++)
+		if (KFD_IS_SVM_API_SUPPORTED(p->pdds[i]->dev))
+			bitmap_set(svms->bitmap_supported, i, 1);
 	return 0;
 }
 		svm_range_set_default_attributes(&location, &prefetch_loc,
 						 &granularity, &flags);
 		if (p->xnack_enabled)
-			bitmap_fill(bitmap_access, MAX_GPU_INSTANCE);
+			bitmap_copy(bitmap_access, svms->bitmap_supported,
+				    MAX_GPU_INSTANCE);
 		else
 			bitmap_zero(bitmap_access, MAX_GPU_INSTANCE);
 		bitmap_zero(bitmap_aip, MAX_GPU_INSTANCE);
 		goto fill_values;
 	}
-	bitmap_fill(bitmap_access, MAX_GPU_INSTANCE);
+	bitmap_copy(bitmap_access, svms->bitmap_supported, MAX_GPU_INSTANCE);
-	bitmap_fill(bitmap_aip, MAX_GPU_INSTANCE);
+	bitmap_copy(bitmap_aip, svms->bitmap_supported, MAX_GPU_INSTANCE);
 	while (node) {
 		struct interval_tree_node *next;

drivers/gpu/drm/amd/amdkfd/kfd_svm.h+7−0

 void svm_range_free_dma_mappings(struct svm_range *prange);
 void svm_range_prefault(struct svm_range *prange, struct mm_struct *mm);
+/* SVM API and HMM page migration work together, device memory type
+ * is initialized to not 0 when page migration register device memory.
+ */
+#define KFD_IS_SVM_API_SUPPORTED(dev) ((dev)->pgmap.type != 0)
 #else
 struct kfd_process;
 	return -EINVAL;
 }
+#define KFD_IS_SVM_API_SUPPORTED(dev) false
 #endif /* IS_ENABLED(CONFIG_HSA_AMD_SVM) */
 #endif /* KFD_SVM_H_ */

drivers/gpu/drm/amd/amdkfd/kfd_topology.c+2−4

 #include "kfd_topology.h"
 #include "kfd_device_queue_manager.h"
 #include "kfd_iommu.h"
+#include "kfd_svm.h"
 #include "amdgpu_amdkfd.h"
 #include "amdgpu_ras.h"
 		dev->node_props.capability |= (adev->ras_enabled != 0) ?
 			HSA_CAP_RASEVENTNOTIFY : 0;
-	/* SVM API and HMM page migration work together, device memory type
+	if (KFD_IS_SVM_API_SUPPORTED(adev->kfd.dev))
-	 * is initialized to not 0 when page migration register device memory.
-	 */
-	if (adev->kfd.dev->pgmap.type != 0)
 		dev->node_props.capability |= HSA_CAP_SVMAPI_SUPPORTED;
 	kfd_debug_print_topology();

drivers/gpu/drm/amd/amdkfd/kfd_topology.h+3−4

@@ -54,8 +54,8 @@ · 53 unmodified lines
54	#define HSA_CAP_ASIC_REVISION_SHIFT 22	54	#define HSA_CAP_ASIC_REVISION_SHIFT 22
55	#define HSA_CAP_SRAM_EDCSUPPORTED 0x04000000	55	#define HSA_CAP_SRAM_EDCSUPPORTED 0x04000000
56	#define HSA_CAP_SVMAPI_SUPPORTED 0x08000000	56	#define HSA_CAP_SVMAPI_SUPPORTED 0x08000000
57		57	#define HSA_CAP_FLAGS_COHERENTHOSTACCESS 0x10000000
58	#define HSA_CAP_RESERVED 0xf00f8000	58	#define HSA_CAP_RESERVED 0xe00f8000
59		59
60	struct kfd_node_properties {	60	struct kfd_node_properties {
61	uint64_t hive_id;	61	uint64_t hive_id;
@@ -101,8 +101,7 @@ struct kfd_node_properties { · 39 unmodified lines
101		101
102	#define HSA_MEM_FLAGS_HOT_PLUGGABLE 0x00000001	102	#define HSA_MEM_FLAGS_HOT_PLUGGABLE 0x00000001
103	#define HSA_MEM_FLAGS_NON_VOLATILE 0x00000002	103	#define HSA_MEM_FLAGS_NON_VOLATILE 0x00000002
104	#define HSA_MEM_FLAGS_COHERENTHOSTACCESS 0x00000004	104	#define HSA_MEM_FLAGS_RESERVED 0xfffffffc
105	#define HSA_MEM_FLAGS_RESERVED 0xfffffff8
106		105
107	struct kfd_mem_properties {	106	struct kfd_mem_properties {
108	struct list_head list;	107	struct list_head list;

drivers/gpu/drm/amd/display/amdgpu_dm/Makefile+1−1

@@ -28,7 +28,7 @@ · 27 unmodified lines
28	AMDGPUDM = amdgpu_dm.o amdgpu_dm_irq.o amdgpu_dm_mst_types.o amdgpu_dm_color.o	28	AMDGPUDM = amdgpu_dm.o amdgpu_dm_irq.o amdgpu_dm_mst_types.o amdgpu_dm_color.o
29		29
30	ifneq ($(CONFIG_DRM_AMD_DC),)	30	ifneq ($(CONFIG_DRM_AMD_DC),)
31	AMDGPUDM += amdgpu_dm_services.o amdgpu_dm_helpers.o amdgpu_dm_pp_smu.o	31	AMDGPUDM += amdgpu_dm_services.o amdgpu_dm_helpers.o amdgpu_dm_pp_smu.o amdgpu_dm_psr.o
32	endif	32	endif
33		33
34	ifdef CONFIG_DRM_AMD_DC_HDCP	34	ifdef CONFIG_DRM_AMD_DC_HDCP

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c+5−136

@@ -58,6 +58,7 @@ · 57 unmodified lines
58	#if defined(CONFIG_DEBUG_FS)	58	#if defined(CONFIG_DEBUG_FS)
59	#include "amdgpu_dm_debugfs.h"	59	#include "amdgpu_dm_debugfs.h"
60	#endif	60	#endif
		61	#include "amdgpu_dm_psr.h"
61		62
62	#include "ivsrcid/ivsrcid_vislands30.h"	63	#include "ivsrcid/ivsrcid_vislands30.h"
63		64
@@ -213,12 +214,6 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, · 149 unmodified lines
213	static void handle_cursor_update(struct drm_plane *plane,	214	static void handle_cursor_update(struct drm_plane *plane,
214	struct drm_plane_state *old_plane_state);	215	struct drm_plane_state *old_plane_state);
215		216
216	static void amdgpu_dm_set_psr_caps(struct dc_link *link);
217	static bool amdgpu_dm_psr_enable(struct dc_stream_state *stream);
218	static bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream);
219	static bool amdgpu_dm_psr_disable(struct dc_stream_state *stream);
220	static bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm);
221
222	static const struct drm_format_info *	217	static const struct drm_format_info *
223	amd_get_format_info(const struct drm_mode_fb_cmd2 *cmd);	218	amd_get_format_info(const struct drm_mode_fb_cmd2 *cmd);
224		219
@@ -10245,6 +10240,10 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, · 10020 unmodified lines
10245	dm_old_crtc_state->dsc_force_changed == false)	10240	dm_old_crtc_state->dsc_force_changed == false)
10246	continue;	10241	continue;
10247		10242
		10243	ret = amdgpu_dm_verify_lut_sizes(new_crtc_state);
		10244	if (ret)
		10245	goto fail;
		10246
10248	if (!new_crtc_state->enable)	10247	if (!new_crtc_state->enable)
10249	continue;	10248	continue;
10250		10249
@@ -10725,136 +10724,6 @@ update: · 474 unmodified lines
10725	freesync_capable);	10724	freesync_capable);
10726	}	10725	}
10727		10726
10728	static void amdgpu_dm_set_psr_caps(struct dc_link *link)
10729	{
10730	uint8_t dpcd_data[EDP_PSR_RECEIVER_CAP_SIZE];
10731
10732	if (!(link->connector_signal & SIGNAL_TYPE_EDP))
10733	return;
10734	if (link->type == dc_connection_none)
10735	return;
10736	if (dm_helpers_dp_read_dpcd(NULL, link, DP_PSR_SUPPORT,
10737	dpcd_data, sizeof(dpcd_data))) {
10738	link->dpcd_caps.psr_caps.psr_version = dpcd_data[0];
10739
10740	if (dpcd_data[0] == 0) {
10741	link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
10742	link->psr_settings.psr_feature_enabled = false;
10743	} else {
10744	link->psr_settings.psr_version = DC_PSR_VERSION_1;
10745	link->psr_settings.psr_feature_enabled = true;
10746	}
10747
10748	DRM_INFO("PSR support:%d\n", link->psr_settings.psr_feature_enabled);
10749	}
10750	}
10751
10752	/*
10753	* amdgpu_dm_link_setup_psr() - configure psr link
10754	* @stream: stream state
10755	*
10756	* Return: true if success
10757	*/
10758	static bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream)
10759	{
10760	struct dc_link *link = NULL;
10761	struct psr_config psr_config = {0};
10762	struct psr_context psr_context = {0};
10763	bool ret = false;
10764
10765	if (stream == NULL)
10766	return false;
10767
10768	link = stream->link;
10769
10770	psr_config.psr_version = link->dpcd_caps.psr_caps.psr_version;
10771
10772	if (psr_config.psr_version > 0) {
10773	psr_config.psr_exit_link_training_required = 0x1;
10774	psr_config.psr_frame_capture_indication_req = 0;
10775	psr_config.psr_rfb_setup_time = 0x37;
10776	psr_config.psr_sdp_transmit_line_num_deadline = 0x20;
10777	psr_config.allow_smu_optimizations = 0x0;
10778
10779	ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context);
10780
10781	}
10782	DRM_DEBUG_DRIVER("PSR link: %d\n", link->psr_settings.psr_feature_enabled);
10783
10784	return ret;
10785	}
10786
10787	/*
10788	* amdgpu_dm_psr_enable() - enable psr f/w
10789	* @stream: stream state
10790	*
10791	* Return: true if success
10792	*/
10793	bool amdgpu_dm_psr_enable(struct dc_stream_state *stream)
10794	{
10795	struct dc_link *link = stream->link;
10796	unsigned int vsync_rate_hz = 0;
10797	struct dc_static_screen_params params = {0};
10798	/* Calculate number of static frames before generating interrupt to
10799	* enter PSR.
10800	*/
10801	// Init fail safe of 2 frames static
10802	unsigned int num_frames_static = 2;
10803
10804	DRM_DEBUG_DRIVER("Enabling psr...\n");
10805
10806	vsync_rate_hz = div64_u64(div64_u64((
10807	stream->timing.pix_clk_100hz * 100),
10808	stream->timing.v_total),
10809	stream->timing.h_total);
10810
10811	/* Round up
10812	* Calculate number of frames such that at least 30 ms of time has
10813	* passed.
10814	*/
10815	if (vsync_rate_hz != 0) {
10816	unsigned int frame_time_microsec = 1000000 / vsync_rate_hz;
10817	num_frames_static = (30000 / frame_time_microsec) + 1;
10818	}
10819
10820	params.triggers.cursor_update = true;
10821	params.triggers.overlay_update = true;
10822	params.triggers.surface_update = true;
10823	params.num_frames = num_frames_static;
10824
10825	dc_stream_set_static_screen_params(link->ctx->dc,
10826	&stream, 1,
10827	&params);
10828
10829	return dc_link_set_psr_allow_active(link, true, false, false);
10830	}
10831
10832	/*
10833	* amdgpu_dm_psr_disable() - disable psr f/w
10834	* @stream: stream state
10835	*
10836	* Return: true if success
10837	*/
10838	static bool amdgpu_dm_psr_disable(struct dc_stream_state *stream)
10839	{
10840
10841	DRM_DEBUG_DRIVER("Disabling psr...\n");
10842
10843	return dc_link_set_psr_allow_active(stream->link, false, true, false);
10844	}
10845
10846	/*
10847	* amdgpu_dm_psr_disable() - disable psr f/w
10848	* if psr is enabled on any stream
10849	*
10850	* Return: true if success
10851	*/
10852	static bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm)
10853	{
10854	DRM_DEBUG_DRIVER("Disabling psr if psr is enabled on any stream\n");
10855	return dc_set_psr_allow_active(dm->dc, false);
10856	}
10857
10858	void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)	10727	void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
10859	{	10728	{
10860	struct amdgpu_device *adev = drm_to_adev(dev);	10729	struct amdgpu_device *adev = drm_to_adev(dev);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h+1−0

@@ -617,6 +617,7 @@ void amdgpu_dm_trigger_timing_sync(struct drm_device *dev); · 616 unmodified lines
617	#define MAX_COLOR_LEGACY_LUT_ENTRIES 256	617	#define MAX_COLOR_LEGACY_LUT_ENTRIES 256
618		618
619	void amdgpu_dm_init_color_mod(void);	619	void amdgpu_dm_init_color_mod(void);
		620	int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state);
620	int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc);	621	int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc);
621	int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,	622	int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
622	struct dc_plane_state *dc_plane_state);	623	struct dc_plane_state *dc_plane_state);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c+35−6

@@ -284,6 +284,37 @@ static int __set_input_tf(struct dc_transfer_func *func, · 283 unmodified lines
284	return res ? 0 : -ENOMEM;	284	return res ? 0 : -ENOMEM;
285	}	285	}
286		286
		287	/**
		288	* Verifies that the Degamma and Gamma LUTs attached to the \|crtc_state\| are of
		289	* the expected size.
		290	* Returns 0 on success.
		291	*/
		292	int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state)
		293	{
		294	const struct drm_color_lut *lut = NULL;
		295	uint32_t size = 0;
		296
		297	lut = __extract_blob_lut(crtc_state->degamma_lut, &size);
		298	if (lut && size != MAX_COLOR_LUT_ENTRIES) {
		299	DRM_DEBUG_DRIVER(
		300	"Invalid Degamma LUT size. Should be %u but got %u.\n",
		301	MAX_COLOR_LUT_ENTRIES, size);
		302	return -EINVAL;
		303	}
		304
		305	lut = __extract_blob_lut(crtc_state->gamma_lut, &size);
		306	if (lut && size != MAX_COLOR_LUT_ENTRIES &&
		307	size != MAX_COLOR_LEGACY_LUT_ENTRIES) {
		308	DRM_DEBUG_DRIVER(
		309	"Invalid Gamma LUT size. Should be %u (or %u for legacy) but got %u.\n",
		310	MAX_COLOR_LUT_ENTRIES, MAX_COLOR_LEGACY_LUT_ENTRIES,
		311	size);
		312	return -EINVAL;
		313	}
		314
		315	return 0;
		316	}
		317
287	/**	318	/**
288	* amdgpu_dm_update_crtc_color_mgmt: Maps DRM color management to DC stream.	319	* amdgpu_dm_update_crtc_color_mgmt: Maps DRM color management to DC stream.
289	* @crtc: amdgpu_dm crtc state	320	* @crtc: amdgpu_dm crtc state
@@ -317,14 +348,12 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc) · 27 unmodified lines
317	bool is_legacy;	348	bool is_legacy;
318	int r;	349	int r;
319		350
320	degamma_lut = __extract_blob_lut(crtc->base.degamma_lut, &degamma_size);	351	r = amdgpu_dm_verify_lut_sizes(&crtc->base);
321	if (degamma_lut && degamma_size != MAX_COLOR_LUT_ENTRIES)	352	if (r)
322	return -EINVAL;	353	return r;
323		354
		355	degamma_lut = __extract_blob_lut(crtc->base.degamma_lut, &degamma_size);
324	regamma_lut = __extract_blob_lut(crtc->base.gamma_lut, &regamma_size);	356	regamma_lut = __extract_blob_lut(crtc->base.gamma_lut, &regamma_size);
325	if (regamma_lut && regamma_size != MAX_COLOR_LUT_ENTRIES &&
326	regamma_size != MAX_COLOR_LEGACY_LUT_ENTRIES)
327	return -EINVAL;
328		357
329	has_degamma =	358	has_degamma =
330	degamma_lut && !__is_lut_linear(degamma_lut, degamma_size);	359	degamma_lut && !__is_lut_linear(degamma_lut, degamma_size);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c+166−0

@@ -0,0 +1,166 @@
	1	/*
	2	* Copyright 2021 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: AMD
	23	*
	24	*/
	25
	26	#include "amdgpu_dm_psr.h"
	27	#include "dc.h"
	28	#include "dm_helpers.h"
	29
	30	/*
	31	* amdgpu_dm_set_psr_caps() - set link psr capabilities
	32	* @link: link
	33	*
	34	*/
	35	void amdgpu_dm_set_psr_caps(struct dc_link *link)
	36	{
	37	uint8_t dpcd_data[EDP_PSR_RECEIVER_CAP_SIZE];
	38
	39	if (!(link->connector_signal & SIGNAL_TYPE_EDP))
	40	return;
	41	if (link->type == dc_connection_none)
	42	return;
	43	if (dm_helpers_dp_read_dpcd(NULL, link, DP_PSR_SUPPORT,
	44	dpcd_data, sizeof(dpcd_data))) {
	45	link->dpcd_caps.psr_caps.psr_version = dpcd_data[0];
	46
	47	if (dpcd_data[0] == 0) {
	48	link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
	49	link->psr_settings.psr_feature_enabled = false;
	50	} else {
	51	link->psr_settings.psr_version = DC_PSR_VERSION_1;
	52	link->psr_settings.psr_feature_enabled = true;
	53	}
	54
	55	DRM_INFO("PSR support:%d\n", link->psr_settings.psr_feature_enabled);
	56	}
	57	}
	58
	59	/*
	60	* amdgpu_dm_link_setup_psr() - configure psr link
	61	* @stream: stream state
	62	*
	63	* Return: true if success
	64	*/
	65	bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream)
	66	{
	67	struct dc_link *link = NULL;
	68	struct psr_config psr_config = {0};
	69	struct psr_context psr_context = {0};
	70	struct dc *dc = NULL;
	71	bool ret = false;
	72
	73	if (stream == NULL)
	74	return false;
	75
	76	link = stream->link;
	77	dc = link->ctx->dc;
	78
	79	psr_config.psr_version = link->dpcd_caps.psr_caps.psr_version;
	80
	81	if (psr_config.psr_version > 0) {
	82	psr_config.psr_exit_link_training_required = 0x1;
	83	psr_config.psr_frame_capture_indication_req = 0;
	84	psr_config.psr_rfb_setup_time = 0x37;
	85	psr_config.psr_sdp_transmit_line_num_deadline = 0x20;
	86	psr_config.allow_smu_optimizations = 0x0;
	87
	88	ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context);
	89
	90	}
	91	DRM_DEBUG_DRIVER("PSR link: %d\n", link->psr_settings.psr_feature_enabled);
	92
	93	return ret;
	94	}
	95
	96	/*
	97	* amdgpu_dm_psr_enable() - enable psr f/w
	98	* @stream: stream state
	99	*
	100	* Return: true if success
	101	*/
	102	bool amdgpu_dm_psr_enable(struct dc_stream_state *stream)
	103	{
	104	struct dc_link *link = stream->link;
	105	unsigned int vsync_rate_hz = 0;
	106	struct dc_static_screen_params params = {0};
	107	/* Calculate number of static frames before generating interrupt to
	108	* enter PSR.
	109	*/
	110	// Init fail safe of 2 frames static
	111	unsigned int num_frames_static = 2;
	112
	113	DRM_DEBUG_DRIVER("Enabling psr...\n");
	114
	115	vsync_rate_hz = div64_u64(div64_u64((
	116	stream->timing.pix_clk_100hz * 100),
	117	stream->timing.v_total),
	118	stream->timing.h_total);
	119
	120	/* Round up
	121	* Calculate number of frames such that at least 30 ms of time has
	122	* passed.
	123	*/
	124	if (vsync_rate_hz != 0) {
	125	unsigned int frame_time_microsec = 1000000 / vsync_rate_hz;
	126	num_frames_static = (30000 / frame_time_microsec) + 1;
	127	}
	128
	129	params.triggers.cursor_update = true;
	130	params.triggers.overlay_update = true;
	131	params.triggers.surface_update = true;
	132	params.num_frames = num_frames_static;
	133
	134	dc_stream_set_static_screen_params(link->ctx->dc,
	135	&stream, 1,
	136	&params);
	137
	138	return dc_link_set_psr_allow_active(link, true, false, false);
	139	}
	140
	141	/*
	142	* amdgpu_dm_psr_disable() - disable psr f/w
	143	* @stream: stream state
	144	*
	145	* Return: true if success
	146	*/
	147	bool amdgpu_dm_psr_disable(struct dc_stream_state *stream)
	148	{
	149
	150	DRM_DEBUG_DRIVER("Disabling psr...\n");
	151
	152	return dc_link_set_psr_allow_active(stream->link, false, true, false);
	153	}
	154
	155	/*
	156	* amdgpu_dm_psr_disable() - disable psr f/w
	157	* if psr is enabled on any stream
	158	*
	159	* Return: true if success
	160	*/
	161	bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm)
	162	{
	163	DRM_DEBUG_DRIVER("Disabling psr if psr is enabled on any stream\n");
	164	return dc_set_psr_allow_active(dm->dc, false);
	165	}
	166

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h+37−0

@@ -0,0 +1,37 @@
	1	/*
	2	* Copyright 2021 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: AMD
	23	*
	24	*/
	25
	26	#ifndef AMDGPU_DM_AMDGPU_DM_PSR_H_
	27	#define AMDGPU_DM_AMDGPU_DM_PSR_H_
	28
	29	#include "amdgpu.h"
	30
	31	void amdgpu_dm_set_psr_caps(struct dc_link *link);
	32	bool amdgpu_dm_psr_enable(struct dc_stream_state *stream);
	33	bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream);
	34	bool amdgpu_dm_psr_disable(struct dc_stream_state *stream);
	35	bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm);
	36
	37	#endif /* AMDGPU_DM_AMDGPU_DM_PSR_H_ */

drivers/gpu/drm/amd/display/dc/Makefile+1−1

@@ -60,7 +60,7 @@ include $(AMD_DC) · 59 unmodified lines
60		60
61	DISPLAY_CORE = dc.o dc_stat.o dc_link.o dc_resource.o dc_hw_sequencer.o dc_sink.o \	61	DISPLAY_CORE = dc.o dc_stat.o dc_link.o dc_resource.o dc_hw_sequencer.o dc_sink.o \
62	dc_surface.o dc_link_hwss.o dc_link_dp.o dc_link_ddc.o dc_debug.o dc_stream.o \	62	dc_surface.o dc_link_hwss.o dc_link_dp.o dc_link_ddc.o dc_debug.o dc_stream.o \
63	dc_link_enc_cfg.o	63	dc_link_enc_cfg.o dc_link_dpcd.o
64		64
65	ifdef CONFIG_DRM_AMD_DC_DCN	65	ifdef CONFIG_DRM_AMD_DC_DCN
66	DISPLAY_CORE += dc_vm_helper.o	66	DISPLAY_CORE += dc_vm_helper.o

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c+65−3

@@ -123,7 +123,7 @@ void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, · 122 unmodified lines
123	}	123	}
124	}	124	}
125		125
126	void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr)	126	void dcn20_update_clocks_update_dentist(struct clk_mgr_internal clk_mgr, struct dc_state context)
127	{	127	{
128	int dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR	128	int dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
129	* clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz;	129	* clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz;
@@ -132,6 +132,68 @@ void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr) · 2 unmodified lines
132		132
133	uint32_t dppclk_wdivider = dentist_get_did_from_divider(dpp_divider);	133	uint32_t dppclk_wdivider = dentist_get_did_from_divider(dpp_divider);
134	uint32_t dispclk_wdivider = dentist_get_did_from_divider(disp_divider);	134	uint32_t dispclk_wdivider = dentist_get_did_from_divider(disp_divider);
		135	uint32_t current_dispclk_wdivider;
		136	uint32_t i;
		137
		138	REG_GET(DENTIST_DISPCLK_CNTL,
		139	DENTIST_DISPCLK_WDIVIDER, &current_dispclk_wdivider);
		140
		141	/* When changing divider to or from 127, some extra programming is required to prevent corruption */
		142	if (current_dispclk_wdivider == 127 && dispclk_wdivider != 127) {
		143	for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
		144	struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
		145	uint32_t fifo_level;
		146	struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg;
		147	struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
		148	int32_t N;
		149	int32_t j;
		150
		151	if (!pipe_ctx->stream)
		152	continue;
		153	/* Virtual encoders don't have this function */
		154	if (!stream_enc->funcs->get_fifo_cal_average_level)
		155	continue;
		156	fifo_level = stream_enc->funcs->get_fifo_cal_average_level(
		157	stream_enc);
		158	N = fifo_level / 4;
		159	dccg->funcs->set_fifo_errdet_ovr_en(
		160	dccg,
		161	true);
		162	for (j = 0; j < N - 4; j++)
		163	dccg->funcs->otg_drop_pixel(
		164	dccg,
		165	pipe_ctx->stream_res.tg->inst);
		166	dccg->funcs->set_fifo_errdet_ovr_en(
		167	dccg,
		168	false);
		169	}
		170	} else if (dispclk_wdivider == 127 && current_dispclk_wdivider != 127) {
		171	REG_UPDATE(DENTIST_DISPCLK_CNTL,
		172	DENTIST_DISPCLK_WDIVIDER, 126);
		173	REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 100);
		174	for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
		175	struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
		176	struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg;
		177	struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
		178	uint32_t fifo_level;
		179	int32_t N;
		180	int32_t j;
		181
		182	if (!pipe_ctx->stream)
		183	continue;
		184	/* Virtual encoders don't have this function */
		185	if (!stream_enc->funcs->get_fifo_cal_average_level)
		186	continue;
		187	fifo_level = stream_enc->funcs->get_fifo_cal_average_level(
		188	stream_enc);
		189	N = fifo_level / 4;
		190	dccg->funcs->set_fifo_errdet_ovr_en(dccg, true);
		191	for (j = 0; j < 12 - N; j++)
		192	dccg->funcs->otg_add_pixel(dccg,
		193	pipe_ctx->stream_res.tg->inst);
		194	dccg->funcs->set_fifo_errdet_ovr_en(dccg, false);
		195	}
		196	}
135		197
136	REG_UPDATE(DENTIST_DISPCLK_CNTL,	198	REG_UPDATE(DENTIST_DISPCLK_CNTL,
137	DENTIST_DISPCLK_WDIVIDER, dispclk_wdivider);	199	DENTIST_DISPCLK_WDIVIDER, dispclk_wdivider);
@@ -251,11 +313,11 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base, · 113 unmodified lines
251	if (dpp_clock_lowered) {	313	if (dpp_clock_lowered) {
252	// if clock is being lowered, increase DTO before lowering refclk	314	// if clock is being lowered, increase DTO before lowering refclk
253	dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);	315	dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
254	dcn20_update_clocks_update_dentist(clk_mgr);	316	dcn20_update_clocks_update_dentist(clk_mgr, context);
255	} else {	317	} else {
256	// if clock is being raised, increase refclk before lowering DTO	318	// if clock is being raised, increase refclk before lowering DTO
257	if (update_dppclk \|\| update_dispclk)	319	if (update_dppclk \|\| update_dispclk)
258	dcn20_update_clocks_update_dentist(clk_mgr);	320	dcn20_update_clocks_update_dentist(clk_mgr, context);
259	// always update dtos unless clock is lowered and not safe to lower	321	// always update dtos unless clock is lowered and not safe to lower
260	dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);	322	dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
261	}	323	}

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h+2−1

@@ -50,7 +50,8 @@ void dcn2_get_clock(struct clk_mgr *clk_mgr, · 49 unmodified lines
50	enum dc_clock_type clock_type,	50	enum dc_clock_type clock_type,
51	struct dc_clock_config *clock_cfg);	51	struct dc_clock_config *clock_cfg);
52		52
53	void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr);	53	void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr,
		54	struct dc_state *context);
54		55
55	void dcn2_read_clocks_from_hw_dentist(struct clk_mgr *clk_mgr_base);	56	void dcn2_read_clocks_from_hw_dentist(struct clk_mgr *clk_mgr_base);
56		57

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c+2−2

@@ -334,11 +334,11 @@ static void dcn3_update_clocks(struct clk_mgr *clk_mgr_base, · 333 unmodified lines
334	if (dpp_clock_lowered) {	334	if (dpp_clock_lowered) {
335	/* if clock is being lowered, increase DTO before lowering refclk */	335	/* if clock is being lowered, increase DTO before lowering refclk */
336	dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);	336	dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
337	dcn20_update_clocks_update_dentist(clk_mgr);	337	dcn20_update_clocks_update_dentist(clk_mgr, context);
338	} else {	338	} else {
339	/* if clock is being raised, increase refclk before lowering DTO */	339	/* if clock is being raised, increase refclk before lowering DTO */
340	if (update_dppclk \|\| update_dispclk)	340	if (update_dppclk \|\| update_dispclk)
341	dcn20_update_clocks_update_dentist(clk_mgr);	341	dcn20_update_clocks_update_dentist(clk_mgr, context);
342	/* There is a check inside dcn20_update_clocks_update_dpp_dto which ensures	342	/* There is a check inside dcn20_update_clocks_update_dpp_dto which ensures
343	* that we do not lower dto when it is not safe to lower. We do not need to	343	* that we do not lower dto when it is not safe to lower. We do not need to
344	* compare the current and new dppclk before calling this function.*/	344	* compare the current and new dppclk before calling this function.*/

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c+5−5

@@ -409,13 +409,13 @@ void get_surface_tile_visual_confirm_color( · 408 unmodified lines
409	struct tg_color *color)	409	struct tg_color *color)
410	{	410	{
411	uint32_t color_value = MAX_TG_COLOR_VALUE;	411	uint32_t color_value = MAX_TG_COLOR_VALUE;
412	/* Determine the overscan color based on the top-most (desktop) plane's context */	412	/* Determine the overscan color based on the bottom-most plane's context */
413	struct pipe_ctx *top_pipe_ctx = pipe_ctx;	413	struct pipe_ctx *bottom_pipe_ctx = pipe_ctx;
414		414
415	while (top_pipe_ctx->top_pipe != NULL)	415	while (bottom_pipe_ctx->bottom_pipe != NULL)
416	top_pipe_ctx = top_pipe_ctx->top_pipe;	416	bottom_pipe_ctx = bottom_pipe_ctx->bottom_pipe;
417		417
418	switch (top_pipe_ctx->plane_state->tiling_info.gfx9.swizzle) {	418	switch (bottom_pipe_ctx->plane_state->tiling_info.gfx9.swizzle) {
419	case DC_SW_LINEAR:	419	case DC_SW_LINEAR:
420	/* LINEAR Surface - set border color to red */	420	/* LINEAR Surface - set border color to red */
421	color->color_r_cr = color_value;	421	color->color_r_cr = color_value;

drivers/gpu/drm/amd/display/dc/core/dc_link.c+68−99

 #include "dmub/dmub_srv.h"
 #include "inc/hw/panel_cntl.h"
 #include "inc/link_enc_cfg.h"
+#include "inc/link_dpcd.h"
 #define DC_LOGGER_INIT(logger)
 #define RETIMER_REDRIVER_INFO(...) \
 	DC_LOG_RETIMER_REDRIVER(  \
 		__VA_ARGS__)
-/*******************************************************************************
- * Private structures
- ******************************************************************************/
-enum {
-	PEAK_FACTOR_X1000 = 1006,
-	/*
-	 * Some receivers fail to train on first try and are good
-	 * on subsequent tries. 2 retries should be plenty. If we
-	 * don't have a successful training then we don't expect to
-	 * ever get one.
-	 */
-	LINK_TRAINING_MAX_VERIFY_RETRY = 2
-};
 /*******************************************************************************
  * Private functions
 static bool detect_dp(struct dc_link *link,
 		      struct display_sink_capability *sink_caps,
-		      bool *converter_disable_audio,
-		      struct audio_support *audio_support,
 		      enum dc_detect_reason reason)
 {
-	bool boot = false;
+	struct audio_support *audio_support = &link->dc->res_pool->audio_support;
 	sink_caps->signal = link_detect_sink(link, reason);
 	sink_caps->transaction_type =
 			 * of this function). */
 			query_hdcp_capability(SIGNAL_TYPE_DISPLAY_PORT_MST, link);
 #endif
-			/*
-			 * This call will initiate MST topology discovery. Which
-			 * will detect MST ports and add new DRM connector DRM
-			 * framework. Then read EDID via remote i2c over aux. In
-			 * the end, will notify DRM detect result and save EDID
-			 * into DRM framework.
-			 *
-			 * .detect is called by .fill_modes.
-			 * .fill_modes is called by user mode ioctl
-			 * DRM_IOCTL_MODE_GETCONNECTOR.
-			 *
-			 * .get_modes is called by .fill_modes.
-			 *
-			 * call .get_modes, AMDGPU DM implementation will create
-			 * new dc_sink and add to dc_link. For long HPD plug
-			 * in/out, MST has its own handle.
-			 *
-			 * Therefore, just after dc_create, link->sink is not
-			 * created for MST until user mode app calls
-			 * DRM_IOCTL_MODE_GETCONNECTOR.
-			 *
-			 * Need check ->sink usages in case ->sink = NULL
-			 * TODO: s3 resume check
-			 */
-			if (reason == DETECT_REASON_BOOT)
-				boot = true;
-			dm_helpers_dp_update_branch_info(link->ctx, link);
-			if (!dm_helpers_dp_mst_start_top_mgr(link->ctx,
-							     link, boot)) {
-				/* MST not supported */
-				link->type = dc_connection_single;
-				sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
-			}
 		}
 		if (link->type != dc_connection_mst_branch &&
-		    is_dp_branch_device(link)) {
+				is_dp_branch_device(link))
 			/* DP SST branch */
 			link->type = dc_connection_sst_branch;
-			if (!link->dpcd_caps.sink_count.bits.SINK_COUNT) {
-				/*
-				 * SST branch unplug processing for short irq
-				 */
-				link_disconnect_sink(link);
-				return true;
-			}
-			if (is_dp_active_dongle(link) &&
-				(link->dpcd_caps.dongle_type !=
-					DISPLAY_DONGLE_DP_HDMI_CONVERTER))
-				*converter_disable_audio = true;
-		}
 	} else {
 		/* DP passive dongles */
 		sink_caps->signal = dp_passive_dongle_detection(link->ddc,
 	struct dc_sink *sink = NULL;
 	struct dc_sink *prev_sink = NULL;
 	struct dpcd_caps prev_dpcd_caps;
-	bool same_dpcd = true;
 	enum dc_connection_type new_connection_type = dc_connection_none;
 	enum dc_connection_type pre_connection_type = dc_connection_none;
 	bool perform_dp_seamless_boot = false;
 	if (dc_is_virtual_signal(link->connector_signal))
 		return false;
-	if ((link->connector_signal == SIGNAL_TYPE_LVDS ||
+	if (((link->connector_signal == SIGNAL_TYPE_LVDS ||
-	     link->connector_signal == SIGNAL_TYPE_EDP) &&
+		link->connector_signal == SIGNAL_TYPE_EDP) &&
-	    link->local_sink) {
+		(!link->dc->config.allow_edp_hotplug_detection)) &&
+		link->local_sink) {
 		// need to re-write OUI and brightness in resume case
 		if (link->connector_signal == SIGNAL_TYPE_EDP) {
 			dpcd_set_source_specific_data(link);
 					return false;
 			}
-			if (!detect_dp(link, &sink_caps,
+			if (!detect_dp(link, &sink_caps, reason)) {
-				       &converter_disable_audio,
-				       aud_support, reason)) {
 				if (prev_sink)
 					dc_sink_release(prev_sink);
 				return false;
 			}
-			// Check if dpcp block is the same
+			if (link->type == dc_connection_mst_branch) {
-			if (prev_sink) {
+				LINK_INFO("link=%d, mst branch is now Connected\n",
-				if (memcmp(&link->dpcd_caps, &prev_dpcd_caps,
+					  link->link_index);
-					   sizeof(struct dpcd_caps)))
+				/* Need to setup mst link_cap struct here
-					same_dpcd = false;
+				 * otherwise dc_link_detect() will leave mst link_cap
+				 * empty which leads to allocate_mst_payload() has "0"
+				 * pbn_per_slot value leading to exception on dc_fixpt_div()
+				 */
+				dp_verify_mst_link_cap(link);
+				/*
+				 * This call will initiate MST topology discovery. Which
+				 * will detect MST ports and add new DRM connector DRM
+				 * framework. Then read EDID via remote i2c over aux. In
+				 * the end, will notify DRM detect result and save EDID
+				 * into DRM framework.
+				 *
+				 * .detect is called by .fill_modes.
+				 * .fill_modes is called by user mode ioctl
+				 * DRM_IOCTL_MODE_GETCONNECTOR.
+				 *
+				 * .get_modes is called by .fill_modes.
+				 *
+				 * call .get_modes, AMDGPU DM implementation will create
+				 * new dc_sink and add to dc_link. For long HPD plug
+				 * in/out, MST has its own handle.
+				 *
+				 * Therefore, just after dc_create, link->sink is not
+				 * created for MST until user mode app calls
+				 * DRM_IOCTL_MODE_GETCONNECTOR.
+				 *
+				 * Need check ->sink usages in case ->sink = NULL
+				 * TODO: s3 resume check
+				 */
+				dm_helpers_dp_update_branch_info(link->ctx, link);
+				if (dm_helpers_dp_mst_start_top_mgr(link->ctx,
+						link, reason == DETECT_REASON_BOOT)) {
+					if (prev_sink)
+						dc_sink_release(prev_sink);
+					return false;
+				} else {
+					link->type = dc_connection_sst_branch;
+					sink_caps.signal = SIGNAL_TYPE_DISPLAY_PORT;
+				}
 			}
 			/* Active SST downstream branch device unplug*/
 			if (link->type == dc_connection_sst_branch &&
 			    link->dpcd_caps.sink_count.bits.SINK_COUNT == 0) {
 				return true;
 			}
+			/* disable audio for non DP to HDMI active sst converter */
+			if (link->type == dc_connection_sst_branch &&
+					is_dp_active_dongle(link) &&
+					(link->dpcd_caps.dongle_type !=
+							DISPLAY_DONGLE_DP_HDMI_CONVERTER))
+				converter_disable_audio = true;
 			// link switch from MST to non-MST stop topology manager
 			if (pre_connection_type == dc_connection_mst_branch &&
-				link->type != dc_connection_mst_branch) {
+					link->type != dc_connection_mst_branch)
 				dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
-			}
-			if (link->type == dc_connection_mst_branch) {
-				LINK_INFO("link=%d, mst branch is now Connected\n",
-					  link->link_index);
-				/* Need to setup mst link_cap struct here
-				 * otherwise dc_link_detect() will leave mst link_cap
-				 * empty which leads to allocate_mst_payload() has "0"
-				 * pbn_per_slot value leading to exception on dc_fixpt_div()
-				 */
-				dp_verify_mst_link_cap(link);
-				if (prev_sink)
-					dc_sink_release(prev_sink);
-				return false;
-			}
 			// For seamless boot, to skip verify link cap, we read UEFI settings and set them as verified.
 			if (reason == DETECT_REASON_BOOT &&
-			    !dc_ctx->dc->config.power_down_display_on_boot &&
+					!dc_ctx->dc->config.power_down_display_on_boot &&
-			    link->link_status.link_active)
+					link->link_status.link_active)
 				perform_dp_seamless_boot = true;
 			if (perform_dp_seamless_boot) {
 		link->dongle_max_pix_clk = 0;
 	}
-	LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p dpcd same=%d edid same=%d\n",
+	LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p edid same=%d\n",
 		  link->link_index, sink,
 		  (sink_caps.signal ==
 		   SIGNAL_TYPE_NONE ? "Disconnected" : "Connected"),
-		  prev_sink, same_dpcd, same_edid);
+		  prev_sink, same_edid);
 	if (prev_sink)
 		dc_sink_release(prev_sink);
 		link->connector_signal = SIGNAL_TYPE_EDP;
 		if (link->hpd_gpio) {
-			link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
+			if (!link->dc->config.allow_edp_hotplug_detection)
+				link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
 			link->irq_source_hpd_rx =
 					dal_irq_get_rx_source(link->hpd_gpio);
 		}

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c+89−81

 	link->ctx->logger
 #define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
+#include "link_dpcd.h"
 	/* maximum pre emphasis level allowed for each voltage swing level*/
 	static const enum dc_pre_emphasis
 	voltage_swing_to_pre_emphasis[] = { PRE_EMPHASIS_LEVEL3,
 {
 	enum dc_status status = DC_OK;
-	if (lt_settings->lttpr_mode == LTTPR_MODE_TRANSPARENT)
+	if (lt_settings->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
-		status = configure_lttpr_mode_transparent(link);
-	else if (lt_settings->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
 		status = configure_lttpr_mode_non_transparent(link, lt_settings);
+	else
+		status = configure_lttpr_mode_transparent(link);
 	return status;
 }
 	enum dp_panel_mode panel_mode;
 	struct link_encoder *link_enc;
 	enum link_training_result status = LINK_TRAINING_CR_FAIL_LANE0;
-	struct dc_link_settings currnet_setting = *link_setting;
+	struct dc_link_settings current_setting = *link_setting;
 	/* Dynamically assigned link encoders associated with stream rather than
 	 * link.
 			link,
 			signal,
 			pipe_ctx->clock_source->id,
-			&currnet_setting);
+			&current_setting);
 		if (stream->sink_patches.dppowerup_delay > 0) {
 			int delay_dp_power_up_in_ms = stream->sink_patches.dppowerup_delay;
 			 panel_mode != DP_PANEL_MODE_DEFAULT);
 		if (link->aux_access_disabled) {
-			dc_link_dp_perform_link_training_skip_aux(link, &currnet_setting);
+			dc_link_dp_perform_link_training_skip_aux(link, &current_setting);
 			return true;
 		} else {
 				status = dc_link_dp_perform_link_training(
 										link,
-										&currnet_setting,
+										&current_setting,
 										skip_video_pattern);
 			if (status == LINK_TRAINING_SUCCESS)
 				return true;
 		if (status == LINK_TRAINING_ABORT)
 			break;
 		else if (do_fallback) {
-			decide_fallback_link_setting(*link_setting, &currnet_setting, status);
+			decide_fallback_link_setting(*link_setting, &current_setting, status);
 			/* Fail link training if reduced link bandwidth no longer meets
 			 * stream requirements.
 			 */
 			if (dc_bandwidth_in_kbps_from_timing(&stream->timing) <
-					dc_link_bandwidth_kbps(link, &currnet_setting))
+					dc_link_bandwidth_kbps(link, &current_setting))
 				break;
 		}
 	return true;
 }
-static bool retrieve_link_cap(struct dc_link *link)
+bool dp_retrieve_lttpr_cap(struct dc_link *link)
 {
-	/* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16,
-	 * which means size 16 will be good for both of those DPCD register block reads
-	 */
-	uint8_t dpcd_data[16];
 	uint8_t lttpr_dpcd_data[6];
-	/*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST.
-	 */
-	uint8_t dpcd_dprx_data = '\0';
-	uint8_t dpcd_power_state = '\0';
-	struct dp_device_vendor_id sink_id;
-	union down_stream_port_count down_strm_port_count;
-	union edp_configuration_cap edp_config_cap;
-	union dp_downstream_port_present ds_port = { 0 };
-	enum dc_status status = DC_ERROR_UNEXPECTED;
-	uint32_t read_dpcd_retry_cnt = 3;
-	int i;
-	struct dp_sink_hw_fw_revision dp_hw_fw_revision;
-	bool is_lttpr_present = false;
-	const uint32_t post_oui_delay = 30; // 30ms
 	bool vbios_lttpr_enable = false;
 	bool vbios_lttpr_interop = false;
 	struct dc_bios *bios = link->dc->ctx->dc_bios;
+	enum dc_status status = DC_ERROR_UNEXPECTED;
+	bool is_lttpr_present = false;
-	memset(dpcd_data, '\0', sizeof(dpcd_data));
 	memset(lttpr_dpcd_data, '\0', sizeof(lttpr_dpcd_data));
-	memset(&down_strm_port_count,
-		'\0', sizeof(union down_stream_port_count));
-	memset(&edp_config_cap, '\0',
-		sizeof(union edp_configuration_cap));
-	/* if extended timeout is supported in hardware,
-	 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
-	 * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
-	 */
-	dc_link_aux_try_to_configure_timeout(link->ddc,
-			LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
-	status = core_link_read_dpcd(link, DP_SET_POWER,
-				&dpcd_power_state, sizeof(dpcd_power_state));
-	/* Delay 1 ms if AUX CH is in power down state. Based on spec
-	 * section 2.3.1.2, if AUX CH may be powered down due to
-	 * write to DPCD 600h = 2. Sink AUX CH is monitoring differential
-	 * signal and may need up to 1 ms before being able to reply.
-	 */
-	if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3)
-		udelay(1000);
-	dpcd_set_source_specific_data(link);
-	/* Sink may need to configure internals based on vendor, so allow some
-	 * time before proceeding with possibly vendor specific transactions
-	 */
-	msleep(post_oui_delay);
-	for (i = 0; i < read_dpcd_retry_cnt; i++) {
-		status = core_link_read_dpcd(
-				link,
-				DP_DPCD_REV,
-				dpcd_data,
-				sizeof(dpcd_data));
-		if (status == DC_OK)
-			break;
-	}
-	if (status != DC_OK) {
-		dm_error("%s: Read dpcd data failed.\n", __func__);
-		return false;
-	}
 	/* Query BIOS to determine if LTTPR functionality is forced on by system */
 	if (bios->funcs->get_lttpr_caps) {
 		enum bp_result bp_query_result;
 								DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
 		/* Attempt to train in LTTPR transparent mode if repeater count exceeds 8. */
-		is_lttpr_present = (link->dpcd_caps.lttpr_caps.phy_repeater_cnt > 0 &&
+		is_lttpr_present = (dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) != 0 &&
-				link->dpcd_caps.lttpr_caps.phy_repeater_cnt < 0xff &&
 				link->dpcd_caps.lttpr_caps.max_lane_count > 0 &&
 				link->dpcd_caps.lttpr_caps.max_lane_count <= 4 &&
 				link->dpcd_caps.lttpr_caps.revision.raw >= 0x14);
-		if (is_lttpr_present)
+		if (is_lttpr_present) {
 			CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: ");
-		else
+			configure_lttpr_mode_transparent(link);
+		} else
 			link->lttpr_mode = LTTPR_MODE_NON_LTTPR;
 	}
+	return is_lttpr_present;
+}
+static bool retrieve_link_cap(struct dc_link *link)
+{
+	/* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16,
+	 * which means size 16 will be good for both of those DPCD register block reads
+	 */
+	uint8_t dpcd_data[16];
+	/*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST.
+	 */
+	uint8_t dpcd_dprx_data = '\0';
+	uint8_t dpcd_power_state = '\0';
+	struct dp_device_vendor_id sink_id;
+	union down_stream_port_count down_strm_port_count;
+	union edp_configuration_cap edp_config_cap;
+	union dp_downstream_port_present ds_port = { 0 };
+	enum dc_status status = DC_ERROR_UNEXPECTED;
+	uint32_t read_dpcd_retry_cnt = 3;
+	int i;
+	struct dp_sink_hw_fw_revision dp_hw_fw_revision;
+	const uint32_t post_oui_delay = 30; // 30ms
+	bool is_lttpr_present = false;
+	memset(dpcd_data, '\0', sizeof(dpcd_data));
+	memset(&down_strm_port_count,
+		'\0', sizeof(union down_stream_port_count));
+	memset(&edp_config_cap, '\0',
+		sizeof(union edp_configuration_cap));
+	/* if extended timeout is supported in hardware,
+	 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
+	 * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
+	 */
+	dc_link_aux_try_to_configure_timeout(link->ddc,
+			LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
+	is_lttpr_present = dp_retrieve_lttpr_cap(link);
+	status = core_link_read_dpcd(link, DP_SET_POWER,
+			&dpcd_power_state, sizeof(dpcd_power_state));
+	/* Delay 1 ms if AUX CH is in power down state. Based on spec
+	 * section 2.3.1.2, if AUX CH may be powered down due to
+	 * write to DPCD 600h = 2. Sink AUX CH is monitoring differential
+	 * signal and may need up to 1 ms before being able to reply.
+	 */
+	if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3)
+		udelay(1000);
+	dpcd_set_source_specific_data(link);
+	/* Sink may need to configure internals based on vendor, so allow some
+	 * time before proceeding with possibly vendor specific transactions
+	 */
+	msleep(post_oui_delay);
+	for (i = 0; i < read_dpcd_retry_cnt; i++) {
+		status = core_link_read_dpcd(
+				link,
+				DP_DPCD_REV,
+				dpcd_data,
+				sizeof(dpcd_data));
+		if (status == DC_OK)
+			break;
+	}
+	if (status != DC_OK) {
+		dm_error("%s: Read receiver caps dpcd data failed.\n", __func__);
+		return false;
+	}
 	if (!is_lttpr_present)
 		dc_link_aux_try_to_configure_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
 	{
 		union training_aux_rd_interval aux_rd_interval;

drivers/gpu/drm/amd/display/dc/core/dc_link_dpcd.c+218−0

@@ -0,0 +1,218 @@
	1	#include <inc/core_status.h>
	2	#include <dc_link.h>
	3	#include <inc/link_hwss.h>
	4	#include <inc/link_dpcd.h>
	5	#include "drm/drm_dp_helper.h"
	6	#include <dc_dp_types.h>
	7	#include "dm_helpers.h"
	8
	9	#define END_ADDRESS(start, size) (start + size - 1)
	10	#define ADDRESS_RANGE_SIZE(start, end) (end - start + 1)
	11	struct dpcd_address_range {
	12	uint32_t start;
	13	uint32_t end;
	14	};
	15
	16	static enum dc_status internal_link_read_dpcd(
	17	struct dc_link *link,
	18	uint32_t address,
	19	uint8_t *data,
	20	uint32_t size)
	21	{
	22	if (!link->aux_access_disabled &&
	23	!dm_helpers_dp_read_dpcd(link->ctx,
	24	link, address, data, size)) {
	25	return DC_ERROR_UNEXPECTED;
	26	}
	27
	28	return DC_OK;
	29	}
	30
	31	static enum dc_status internal_link_write_dpcd(
	32	struct dc_link *link,
	33	uint32_t address,
	34	const uint8_t *data,
	35	uint32_t size)
	36	{
	37	if (!link->aux_access_disabled &&
	38	!dm_helpers_dp_write_dpcd(link->ctx,
	39	link, address, data, size)) {
	40	return DC_ERROR_UNEXPECTED;
	41	}
	42
	43	return DC_OK;
	44	}
	45
	46	/*
	47	* Partition the entire DPCD address space
	48	* XXX: This partitioning must cover the entire DPCD address space,
	49	* and must contain no gaps or overlapping address ranges.
	50	*/
	51	static const struct dpcd_address_range mandatory_dpcd_partitions[] = {
	52	{ 0, DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR1) - 1},
	53	{ DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR1), DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR2) - 1 },
	54	{ DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR2), DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR3) - 1 },
	55	{ DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR3), DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR4) - 1 },
	56	{ DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR4), DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR5) - 1 },
	57	{ DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR5), DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR6) - 1 },
	58	{ DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR6), DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR7) - 1 },
	59	{ DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR7), DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR8) - 1 },
	60	{ DP_TRAINING_PATTERN_SET_PHY_REPEATER(DP_PHY_LTTPR8), DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR1) - 1 },
	61	/*
	62	* The FEC registers are contiguous
	63	*/
	64	{ DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR1), DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR1) - 1 },
	65	{ DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR2), DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR2) - 1 },
	66	{ DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR3), DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR3) - 1 },
	67	{ DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR4), DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR4) - 1 },
	68	{ DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR5), DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR5) - 1 },
	69	{ DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR6), DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR6) - 1 },
	70	{ DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR7), DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR7) - 1 },
	71	{ DP_FEC_STATUS_PHY_REPEATER(DP_PHY_LTTPR8), DP_LTTPR_MAX_ADD },
	72	/* all remaining DPCD addresses */
	73	{ DP_LTTPR_MAX_ADD + 1, DP_DPCD_MAX_ADD } };
	74
	75	static inline bool do_addresses_intersect_with_range(
	76	const struct dpcd_address_range *range,
	77	const uint32_t start_address,
	78	const uint32_t end_address)
	79	{
	80	return start_address <= range->end && end_address >= range->start;
	81	}
	82
	83	static uint32_t dpcd_get_next_partition_size(const uint32_t address, const uint32_t size)
	84	{
	85	const uint32_t end_address = END_ADDRESS(address, size);
	86	uint32_t partition_iterator = 0;
	87
	88	/*
	89	* find current partition
	90	* this loop spins forever if partition map above is not surjective
	91	*/
	92	while (!do_addresses_intersect_with_range(&mandatory_dpcd_partitions[partition_iterator],
	93	address, end_address))
	94	partition_iterator++;
	95	if (end_address < mandatory_dpcd_partitions[partition_iterator].end)
	96	return size;
	97	return ADDRESS_RANGE_SIZE(address, mandatory_dpcd_partitions[partition_iterator].end);
	98	}
	99
	100	/*
	101	* Ranges of DPCD addresses that must be read in a single transaction
	102	* XXX: Do not allow any two address ranges in this array to overlap
	103	*/
	104	static const struct dpcd_address_range mandatory_dpcd_blocks[] = {
	105	{ DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT }};
	106
	107	/*
	108	* extend addresses to read all mandatory blocks together
	109	*/
	110	static void dpcd_extend_address_range(
	111	const uint32_t in_address,
	112	uint8_t * const in_data,
	113	const uint32_t in_size,
	114	uint32_t *out_address,
	115	uint8_t **out_data,
	116	uint32_t *out_size)
	117	{
	118	const uint32_t end_address = END_ADDRESS(in_address, in_size);
	119	const struct dpcd_address_range *addr_range;
	120	struct dpcd_address_range new_addr_range;
	121	uint32_t i;
	122
	123	new_addr_range.start = in_address;
	124	new_addr_range.end = end_address;
	125	for (i = 0; i < ARRAY_SIZE(mandatory_dpcd_blocks); i++) {
	126	addr_range = &mandatory_dpcd_blocks[i];
	127	if (addr_range->start <= in_address && addr_range->end >= in_address)
	128	new_addr_range.start = addr_range->start;
	129
	130	if (addr_range->start <= end_address && addr_range->end >= end_address)
	131	new_addr_range.end = addr_range->end;
	132	}
	133	*out_address = in_address;
	134	*out_size = in_size;
	135	*out_data = in_data;
	136	if (new_addr_range.start != in_address \|\| new_addr_range.end != end_address) {
	137	*out_address = new_addr_range.start;
	138	*out_size = ADDRESS_RANGE_SIZE(new_addr_range.start, new_addr_range.end);
	139	out_data = kzalloc(out_size * sizeof(**out_data), GFP_KERNEL);
	140	}
	141	}
	142
	143	/*
	144	* Reduce the AUX reply down to the values the caller requested
	145	*/
	146	static void dpcd_reduce_address_range(
	147	const uint32_t extended_address,
	148	uint8_t * const extended_data,
	149	const uint32_t extended_size,
	150	const uint32_t reduced_address,
	151	uint8_t * const reduced_data,
	152	const uint32_t reduced_size)
	153	{
	154	const uint32_t reduced_end_address = END_ADDRESS(reduced_address, reduced_size);
	155	const uint32_t extended_end_address = END_ADDRESS(reduced_address, extended_size);
	156	const uint32_t offset = reduced_address - extended_address;
	157
	158	if (extended_end_address == reduced_end_address && extended_address == reduced_address)
	159	return; /* extended and reduced address ranges point to the same data */
	160
	161	memcpy(&extended_data[offset], reduced_data, reduced_size);
	162	kfree(extended_data);
	163	}
	164
	165	enum dc_status core_link_read_dpcd(
	166	struct dc_link *link,
	167	uint32_t address,
	168	uint8_t *data,
	169	uint32_t size)
	170	{
	171	uint32_t extended_address;
	172	uint32_t partitioned_address;
	173	uint8_t *extended_data;
	174	uint32_t extended_size;
	175	/* size of the remaining partitioned address space */
	176	uint32_t size_left_to_read;
	177	enum dc_status status;
	178	/* size of the next partition to be read from */
	179	uint32_t partition_size;
	180	uint32_t data_index = 0;
	181
	182	dpcd_extend_address_range(address, data, size, &extended_address, &extended_data, &extended_size);
	183	partitioned_address = extended_address;
	184	size_left_to_read = extended_size;
	185	while (size_left_to_read) {
	186	partition_size = dpcd_get_next_partition_size(partitioned_address, size_left_to_read);
	187	status = internal_link_read_dpcd(link, partitioned_address, &extended_data[data_index], partition_size);
	188	if (status != DC_OK)
	189	break;
	190	partitioned_address += partition_size;
	191	data_index += partition_size;
	192	size_left_to_read -= partition_size;
	193	}
	194	dpcd_reduce_address_range(extended_address, extended_data, extended_size, address, data, size);
	195	return status;
	196	}
	197
	198	enum dc_status core_link_write_dpcd(
	199	struct dc_link *link,
	200	uint32_t address,
	201	const uint8_t *data,
	202	uint32_t size)
	203	{
	204	uint32_t partition_size;
	205	uint32_t data_index = 0;
	206	enum dc_status status;
	207
	208	while (size) {
	209	partition_size = dpcd_get_next_partition_size(address, size);
	210	status = internal_link_write_dpcd(link, address, &data[data_index], partition_size);
	211	if (status != DC_OK)
	212	break;
	213	address += partition_size;
	214	data_index += partition_size;
	215	size -= partition_size;
	216	}
	217	return status;
	218	}

drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c+1−30

@@ -16,6 +16,7 @@ · 15 unmodified lines
16	#include "resource.h"	16	#include "resource.h"
17	#include "link_enc_cfg.h"	17	#include "link_enc_cfg.h"
18	#include "clk_mgr.h"	18	#include "clk_mgr.h"
		19	#include "inc/link_dpcd.h"
19		20
20	static uint8_t convert_to_count(uint8_t lttpr_repeater_count)	21	static uint8_t convert_to_count(uint8_t lttpr_repeater_count)
21	{	22	{
@@ -47,36 +48,6 @@ static inline bool is_immediate_downstream(struct dc_link *link, uint32_t offset · 25 unmodified lines
47	return (convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) == offset);	48	return (convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) == offset);
48	}	49	}
49		50
50	enum dc_status core_link_read_dpcd(
51	struct dc_link *link,
52	uint32_t address,
53	uint8_t *data,
54	uint32_t size)
55	{
56	if (!link->aux_access_disabled &&
57	!dm_helpers_dp_read_dpcd(link->ctx,
58	link, address, data, size)) {
59	return DC_ERROR_UNEXPECTED;
60	}
61
62	return DC_OK;
63	}
64
65	enum dc_status core_link_write_dpcd(
66	struct dc_link *link,
67	uint32_t address,
68	const uint8_t *data,
69	uint32_t size)
70	{
71	if (!link->aux_access_disabled &&
72	!dm_helpers_dp_write_dpcd(link->ctx,
73	link, address, data, size)) {
74	return DC_ERROR_UNEXPECTED;
75	}
76
77	return DC_OK;
78	}
79
80	void dp_receiver_power_ctrl(struct dc_link *link, bool on)	51	void dp_receiver_power_ctrl(struct dc_link *link, bool on)
81	{	52	{
82	uint8_t state;	53	uint8_t state;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c+1−1

@@ -445,7 +445,7 @@ bool resource_are_vblanks_synchronizable( · 444 unmodified lines
445	{	445	{
446	uint32_t base60_refresh_rates[] = {10, 20, 5};	446	uint32_t base60_refresh_rates[] = {10, 20, 5};
447	uint8_t i;	447	uint8_t i;
448	uint8_t rr_count = sizeof(base60_refresh_rates)/sizeof(base60_refresh_rates[0]);	448	uint8_t rr_count = ARRAY_SIZE(base60_refresh_rates);
449	uint64_t frame_time_diff;	449	uint64_t frame_time_diff;
450		450
451	if (stream1->ctx->dc->config.vblank_alignment_dto_params &&	451	if (stream1->ctx->dc->config.vblank_alignment_dto_params &&

drivers/gpu/drm/amd/display/dc/dc.h+2−1

 /* forward declaration */
 struct aux_payload;
-#define DC_VER "3.2.139"
+#define DC_VER "3.2.140"
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
 	bool multi_mon_pp_mclk_switch;
 	bool disable_dmcu;
 	bool enable_4to1MPC;
+	bool allow_edp_hotplug_detection;
 #if defined(CONFIG_DRM_AMD_DC_DCN)
 	bool clamp_min_dcfclk;
 #endif

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c+98−2

@@ -86,6 +86,7 @@ void dc_dmub_srv_cmd_queue(struct dc_dmub_srv *dc_dmub_srv, · 85 unmodified lines
86		86
87	error:	87	error:
88	DC_ERROR("Error queuing DMUB command: status=%d\n", status);	88	DC_ERROR("Error queuing DMUB command: status=%d\n", status);
		89	dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
89	}	90	}
90		91
91	void dc_dmub_srv_cmd_execute(struct dc_dmub_srv *dc_dmub_srv)	92	void dc_dmub_srv_cmd_execute(struct dc_dmub_srv *dc_dmub_srv)
@@ -95,8 +96,10 @@ void dc_dmub_srv_cmd_execute(struct dc_dmub_srv *dc_dmub_srv) · 3 unmodified lines
95	enum dmub_status status;	96	enum dmub_status status;
96		97
97	status = dmub_srv_cmd_execute(dmub);	98	status = dmub_srv_cmd_execute(dmub);
98	if (status != DMUB_STATUS_OK)	99	if (status != DMUB_STATUS_OK) {
99	DC_ERROR("Error starting DMUB execution: status=%d\n", status);	100	DC_ERROR("Error starting DMUB execution: status=%d\n", status);
		101	dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
		102	}
100	}	103	}
101		104
102	void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv)	105	void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv)
@@ -106,8 +109,10 @@ void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv) · 3 unmodified lines
106	enum dmub_status status;	109	enum dmub_status status;
107		110
108	status = dmub_srv_wait_for_idle(dmub, 100000);	111	status = dmub_srv_wait_for_idle(dmub, 100000);
109	if (status != DMUB_STATUS_OK)	112	if (status != DMUB_STATUS_OK) {
110	DC_ERROR("Error waiting for DMUB idle: status=%d\n", status);	113	DC_ERROR("Error waiting for DMUB idle: status=%d\n", status);
		114	dc_dmub_srv_log_diagnostic_data(dc_dmub_srv);
		115	}
111	}	116	}
112		117
113	void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dmub_srv,	118	void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dmub_srv,
@@ -214,3 +219,94 @@ void dc_dmub_trace_event_control(struct dc *dc, bool enable) · 100 unmodified lines
214	{	219	{
215	dm_helpers_dmub_outbox_interrupt_control(dc->ctx, enable);	220	dm_helpers_dmub_outbox_interrupt_control(dc->ctx, enable);
216	}	221	}
		222
		223	bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv dc_dmub_srv, struct dmub_diagnostic_data diag_data)
		224	{
		225	if (!dc_dmub_srv \|\| !dc_dmub_srv->dmub \|\| !diag_data)
		226	return false;
		227	return dmub_srv_get_diagnostic_data(dc_dmub_srv->dmub, diag_data);
		228	}
		229
		230	void dc_dmub_srv_log_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv)
		231	{
		232	struct dmub_diagnostic_data diag_data = {0};
		233
		234	if (!dc_dmub_srv \|\| !dc_dmub_srv->dmub) {
		235	DC_LOG_ERROR("%s: invalid parameters.", __func__);
		236	return;
		237	}
		238
		239	if (!dc_dmub_srv_get_diagnostic_data(dc_dmub_srv, &diag_data)) {
		240	DC_LOG_ERROR("%s: dc_dmub_srv_get_diagnostic_data failed.", __func__);
		241	return;
		242	}
		243
		244	DC_LOG_DEBUG(
		245	"DMCUB STATE\n"
		246	" dmcub_version : %08x\n"
		247	" scratch [0] : %08x\n"
		248	" scratch [1] : %08x\n"
		249	" scratch [2] : %08x\n"
		250	" scratch [3] : %08x\n"
		251	" scratch [4] : %08x\n"
		252	" scratch [5] : %08x\n"
		253	" scratch [6] : %08x\n"
		254	" scratch [7] : %08x\n"
		255	" scratch [8] : %08x\n"
		256	" scratch [9] : %08x\n"
		257	" scratch [10] : %08x\n"
		258	" scratch [11] : %08x\n"
		259	" scratch [12] : %08x\n"
		260	" scratch [13] : %08x\n"
		261	" scratch [14] : %08x\n"
		262	" scratch [15] : %08x\n"
		263	" pc : %08x\n"
		264	" unk_fault_addr : %08x\n"
		265	" inst_fault_addr : %08x\n"
		266	" data_fault_addr : %08x\n"
		267	" inbox1_rptr : %08x\n"
		268	" inbox1_wptr : %08x\n"
		269	" inbox1_size : %08x\n"
		270	" inbox0_rptr : %08x\n"
		271	" inbox0_wptr : %08x\n"
		272	" inbox0_size : %08x\n"
		273	" is_enabled : %d\n"
		274	" is_soft_reset : %d\n"
		275	" is_secure_reset : %d\n"
		276	" is_traceport_en : %d\n"
		277	" is_cw0_en : %d\n"
		278	" is_cw6_en : %d\n",
		279	diag_data.dmcub_version,
		280	diag_data.scratch[0],
		281	diag_data.scratch[1],
		282	diag_data.scratch[2],
		283	diag_data.scratch[3],
		284	diag_data.scratch[4],
		285	diag_data.scratch[5],
		286	diag_data.scratch[6],
		287	diag_data.scratch[7],
		288	diag_data.scratch[8],
		289	diag_data.scratch[9],
		290	diag_data.scratch[10],
		291	diag_data.scratch[11],
		292	diag_data.scratch[12],
		293	diag_data.scratch[13],
		294	diag_data.scratch[14],
		295	diag_data.scratch[15],
		296	diag_data.pc,
		297	diag_data.undefined_address_fault_addr,
		298	diag_data.inst_fetch_fault_addr,
		299	diag_data.data_write_fault_addr,
		300	diag_data.inbox1_rptr,
		301	diag_data.inbox1_wptr,
		302	diag_data.inbox1_size,
		303	diag_data.inbox0_rptr,
		304	diag_data.inbox0_wptr,
		305	diag_data.inbox0_size,
		306	diag_data.is_dmcub_enabled,
		307	diag_data.is_dmcub_soft_reset,
		308	diag_data.is_dmcub_secure_reset,
		309	diag_data.is_traceport_en,
		310	diag_data.is_cw0_enabled,
		311	diag_data.is_cw6_enabled);
		312	}

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h+4−0

@@ -71,4 +71,8 @@ void dc_dmub_trace_event_control(struct dc *dc, bool enable); · 70 unmodified lines
71		71
72	void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dmub_srv, union dmub_inbox0_data_register data);	72	void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dmub_srv, union dmub_inbox0_data_register data);
73		73
		74	bool dc_dmub_srv_get_diagnostic_data(struct dc_dmub_srv dc_dmub_srv, struct dmub_diagnostic_data dmub_oca);
		75
		76	void dc_dmub_srv_log_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv);
		77
74	#endif /* _DMUB_DC_SRV_H_ */	78	#endif /* _DMUB_DC_SRV_H_ */

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c+18−5

 }
 #define AUX_MAX_RETRIES 7
-#define AUX_MAX_DEFER_RETRIES 7
+#define AUX_MIN_DEFER_RETRIES 7
+#define AUX_MAX_DEFER_TIMEOUT_MS 50
 #define AUX_MAX_I2C_DEFER_RETRIES 7
 #define AUX_MAX_INVALID_REPLY_RETRIES 2
 #define AUX_MAX_TIMEOUT_RETRIES 3
 	bool payload_reply = true;
 	enum aux_return_code_type operation_result;
 	bool retry_on_defer = false;
+	struct ddc *ddc_pin = ddc->ddc_pin;
+	struct dce_aux *aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en];
+	struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(aux_engine);
+	uint32_t defer_time_in_ms = 0;
 	int aux_ack_retries = 0,
 		aux_defer_retries = 0,
 			break;
 			case AUX_TRANSACTION_REPLY_AUX_DEFER:
+				/* polling_timeout_period is in us */
+				defer_time_in_ms += aux110->polling_timeout_period / 1000;
+				++aux_defer_retries;
+				/* fall through */
 			case AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER:
 				retry_on_defer = true;
 				fallthrough;
 			case AUX_TRANSACTION_REPLY_I2C_OVER_AUX_NACK:
-				if (++aux_defer_retries >= AUX_MAX_DEFER_RETRIES) {
+				if (aux_defer_retries >= AUX_MIN_DEFER_RETRIES
+						&& defer_time_in_ms >= AUX_MAX_DEFER_TIMEOUT_MS) {
 					goto fail;
 				} else {
 					if ((*payload->reply == AUX_TRANSACTION_REPLY_AUX_DEFER) ||
 						(*payload->reply == AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER)) {
-						if (payload->defer_delay > 1)
+						if (payload->defer_delay > 1) {
 							msleep(payload->defer_delay);
-						else if (payload->defer_delay <= 1)
+							defer_time_in_ms += payload->defer_delay;
+						} else if (payload->defer_delay <= 1) {
 							udelay(payload->defer_delay * 1000);
+							defer_time_in_ms += payload->defer_delay;
+						}
 					}
 				}
 				break;
 			// Check whether a DEFER had occurred before the timeout.
 			// If so, treat timeout as a DEFER.
 			if (retry_on_defer) {
-				if (++aux_defer_retries >= AUX_MAX_DEFER_RETRIES)
+				if (++aux_defer_retries >= AUX_MIN_DEFER_RETRIES)
 					goto fail;
 				else if (payload->defer_delay > 0)
 					msleep(payload->defer_delay);

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c+0−1

@@ -65,7 +65,6 @@ · 64 unmodified lines
65		65
66	#include "atomfirmware.h"	66	#include "atomfirmware.h"
67		67
68	#include "dce110_hw_sequencer.h"
69	#include "dcn10/dcn10_hw_sequencer.h"	68	#include "dcn10/dcn10_hw_sequencer.h"
70		69
71	#define GAMMA_HW_POINTS_NUM 256	70	#define GAMMA_HW_POINTS_NUM 256

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c+5−0

 #include "dce/dmub_hw_lock_mgr.h"
 #include "dc_trace.h"
 #include "dce/dmub_outbox.h"
+#include "inc/dc_link_dp.h"
+#include "inc/link_dpcd.h"
 #define DC_LOGGER_INIT(logger)
 			if (dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT)
 				continue;
+			/* DP 2.0 requires that LTTPR Caps be read first */
+			dp_retrieve_lttpr_cap(dc->links[i]);
 			/*
 			 * If any of the displays are lit up turn them off.
 			 * The reason is that some MST hubs cannot be turned off

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h+24−0

 	SRI(AFMT_60958_1, DIG, id), \
 	SRI(AFMT_60958_2, DIG, id), \
 	SRI(DIG_FE_CNTL, DIG, id), \
+	SRI(DIG_FIFO_STATUS, DIG, id), \
 	SRI(HDMI_CONTROL, DIG, id), \
 	SRI(HDMI_DB_CONTROL, DIG, id), \
 	SRI(HDMI_GC, DIG, id), \
 	uint32_t AFMT_60958_2;
 	uint32_t DIG_FE_CNTL;
 	uint32_t DIG_FE_CNTL2;
+	uint32_t DIG_FIFO_STATUS;
 	uint32_t DP_MSE_RATE_CNTL;
 	uint32_t DP_MSE_RATE_UPDATE;
 	uint32_t DP_PIXEL_FORMAT;
 	SE_SF(DIG0_DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\
 	SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\
 	SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_LEVEL_ERROR, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_USE_OVERWRITE_LEVEL, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_OVERWRITE_LEVEL, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_ERROR_ACK, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_CAL_AVERAGE_LEVEL, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_MAXIMUM_LEVEL, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_MINIMUM_LEVEL, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_READ_CLOCK_SRC, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_CALIBRATED, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_FORCE_RECAL_AVERAGE, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_FORCE_RECOMP_MINMAX, mask_sh),\
 	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, mask_sh),\
 	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, mask_sh),\
 	SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, mask_sh),\
 	type DP_VID_N_MUL;\
 	type DP_VID_M_DOUBLE_VALUE_EN;\
 	type DIG_SOURCE_SELECT;\
+	type DIG_FIFO_LEVEL_ERROR;\
+	type DIG_FIFO_USE_OVERWRITE_LEVEL;\
+	type DIG_FIFO_OVERWRITE_LEVEL;\
+	type DIG_FIFO_ERROR_ACK;\
+	type DIG_FIFO_CAL_AVERAGE_LEVEL;\
+	type DIG_FIFO_MAXIMUM_LEVEL;\
+	type DIG_FIFO_MINIMUM_LEVEL;\
+	type DIG_FIFO_READ_CLOCK_SRC;\
+	type DIG_FIFO_CALIBRATED;\
+	type DIG_FIFO_FORCE_RECAL_AVERAGE;\
+	type DIG_FIFO_FORCE_RECOMP_MINMAX;\
 	type DIG_CLOCK_PATTERN
 #define SE_REG_FIELD_LIST_DCN2_0(type) \

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c+12−0

 		DP_SST_SDP_SPLITTING, enable_sdp_splitting);
 }
+uint32_t enc2_get_fifo_cal_average_level(
+		struct stream_encoder *enc)
+{
+	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+	uint32_t fifo_level;
+	REG_GET(DIG_FIFO_STATUS,
+			DIG_FIFO_CAL_AVERAGE_LEVEL, &fifo_level);
+	return fifo_level;
+}
 static const struct stream_encoder_funcs dcn20_str_enc_funcs = {
 	.dp_set_odm_combine =
 		enc2_dp_set_odm_combine,
 	.dp_set_dsc_pps_info_packet = enc2_dp_set_dsc_pps_info_packet,
 	.set_dynamic_metadata = enc2_set_dynamic_metadata,
 	.hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute,
+	.get_fifo_cal_average_level = enc2_get_fifo_cal_average_level,
 };
 void dcn20_stream_encoder_construct(

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h+3−0

@@ -112,4 +112,7 @@ void enc2_set_dynamic_metadata(struct stream_encoder *enc, · 111 unmodified lines
112	uint32_t hubp_requestor_id,	112	uint32_t hubp_requestor_id,
113	enum dynamic_metadata_mode dmdata_mode);	113	enum dynamic_metadata_mode dmdata_mode);
114		114
		115	uint32_t enc2_get_fifo_cal_average_level(
		116	struct stream_encoder *enc);
		117
115	#endif /* __DC_STREAM_ENCODER_DCN20_H__ */	118	#endif /* __DC_STREAM_ENCODER_DCN20_H__ */

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c+2−0

@@ -823,6 +823,8 @@ static const struct stream_encoder_funcs dcn30_str_enc_funcs = { · 822 unmodified lines
823	.dp_set_dsc_pps_info_packet = enc3_dp_set_dsc_pps_info_packet,	823	.dp_set_dsc_pps_info_packet = enc3_dp_set_dsc_pps_info_packet,
824	.set_dynamic_metadata = enc2_set_dynamic_metadata,	824	.set_dynamic_metadata = enc2_set_dynamic_metadata,
825	.hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute,	825	.hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute,
		826
		827	.get_fifo_cal_average_level = enc2_get_fifo_cal_average_level,
826	};	828	};
827		829
828	void dcn30_dio_stream_encoder_construct(	830	void dcn30_dio_stream_encoder_construct(

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.h+12−0

 	SRI(DP_SEC_METADATA_TRANSMISSION, DP, id), \
 	SRI(HDMI_METADATA_PACKET_CONTROL, DIG, id), \
 	SRI(DIG_FE_CNTL, DIG, id), \
+	SRI(DIG_FIFO_STATUS, DIG, id), \
 	SRI(DIG_CLOCK_PATTERN, DIG, id)
 	SE_SF(DIG0_DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\
 	SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\
 	SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_LEVEL_ERROR, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_USE_OVERWRITE_LEVEL, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_OVERWRITE_LEVEL, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_ERROR_ACK, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_CAL_AVERAGE_LEVEL, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_MAXIMUM_LEVEL, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_MINIMUM_LEVEL, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_READ_CLOCK_SRC, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_CALIBRATED, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_FORCE_RECAL_AVERAGE, mask_sh),\
+	SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_FORCE_RECOMP_MINMAX, mask_sh),\
 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP4_ENABLE, mask_sh),\
 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, mask_sh),\
 	SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP6_ENABLE, mask_sh),\

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c+4−0

 #include "dc_dmub_srv.h"
 #include "link_hwss.h"
 #include "dpcd_defs.h"
+#include "inc/dc_link_dp.h"
+#include "inc/link_dpcd.h"
 		for (i = 0; i < dc->link_count; i++) {
 			if (dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT)
 				continue;
+			/* DP 2.0 states that LTTPR regs must be read first */
+			dp_retrieve_lttpr_cap(dc->links[i]);
 			/* if any of the displays are lit up turn them off */
 			status = core_link_read_dpcd(dc->links[i], DP_SET_POWER,

drivers/gpu/drm/amd/display/dc/dcn303/dcn303_hwseq.c+5−0

@@ -38,3 +38,8 @@ void dcn303_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool po · 37 unmodified lines
38	{	38	{
39	/DCN303 removes PG registers/	39	/DCN303 removes PG registers/
40	}	40	}
		41
		42	void dcn303_enable_power_gating_plane(struct dce_hwseq *hws, bool enable)
		43	{
		44	/DCN303 removes PG registers/
		45	}

drivers/gpu/drm/amd/display/dc/dcn303/dcn303_hwseq.h+1−0

@@ -13,5 +13,6 @@ · 12 unmodified lines
13	void dcn303_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on);	13	void dcn303_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on);
14	void dcn303_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on);	14	void dcn303_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on);
15	void dcn303_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on);	15	void dcn303_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on);
		16	void dcn303_enable_power_gating_plane(struct dce_hwseq *hws, bool enable);
16		17
17	#endif /* __DC_HWSS_DCN303_H__ */	18	#endif /* __DC_HWSS_DCN303_H__ */

drivers/gpu/drm/amd/display/dc/dcn303/dcn303_init.c+1−0

@@ -16,4 +16,5 @@ void dcn303_hw_sequencer_construct(struct dc *dc) · 15 unmodified lines
16	dc->hwseq->funcs.dpp_pg_control = dcn303_dpp_pg_control;	16	dc->hwseq->funcs.dpp_pg_control = dcn303_dpp_pg_control;
17	dc->hwseq->funcs.hubp_pg_control = dcn303_hubp_pg_control;	17	dc->hwseq->funcs.hubp_pg_control = dcn303_hubp_pg_control;
18	dc->hwseq->funcs.dsc_pg_control = dcn303_dsc_pg_control;	18	dc->hwseq->funcs.dsc_pg_control = dcn303_dsc_pg_control;
		19	dc->hwseq->funcs.enable_power_gating_plane = dcn303_enable_power_gating_plane;
19	}	20	}

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c+1−1

 #include "clk_mgr.h"
 #include "reg_helper.h"
 #include "abm.h"
-#include "clk_mgr.h"
 #include "hubp.h"
 #include "dchubbub.h"
 #include "timing_generator.h"
 #include "dpcd_defs.h"
 #include "dce/dmub_outbox.h"
 #include "dc_link_dp.h"
+#include "inc/link_dpcd.h"
 #define DC_LOGGER_INIT(logger)

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c+0−1

@@ -934,7 +934,6 @@ static const struct dc_debug_options debug_defaults_drv = { · 933 unmodified lines
934	.dmub_command_table = true,	934	.dmub_command_table = true,
935	.pstate_enabled = true,	935	.pstate_enabled = true,
936	.use_max_lb = true,	936	.use_max_lb = true,
937	.pstate_enabled = true,
938	.enable_mem_low_power = {	937	.enable_mem_low_power = {
939	.bits = {	938	.bits = {
940	.vga = false,	939	.vga = false,

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c+2−2

@@ -3536,7 +3536,7 @@ static bool CalculateBytePerPixelAnd256BBlockSizes( · 3535 unmodified lines
3536	*BytePerPixelDETC = 0;	3536	*BytePerPixelDETC = 0;
3537	*BytePerPixelY = 4;	3537	*BytePerPixelY = 4;
3538	*BytePerPixelC = 0;	3538	*BytePerPixelC = 0;
3539	} else if (SourcePixelFormat == dm_444_16 \|\| SourcePixelFormat == dm_444_16) {	3539	} else if (SourcePixelFormat == dm_444_16) {
3540	*BytePerPixelDETY = 2;	3540	*BytePerPixelDETY = 2;
3541	*BytePerPixelDETC = 0;	3541	*BytePerPixelDETC = 0;
3542	*BytePerPixelY = 2;	3542	*BytePerPixelY = 2;
@@ -5674,7 +5674,7 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l · 2131 unmodified lines
5674	for (k = 0; k < v->NumberOfActivePlanes; k++) {	5674	for (k = 0; k < v->NumberOfActivePlanes; k++) {
5675	if (v->ViewportWidth[k] > v->SurfaceWidthY[k] \|\| v->ViewportHeight[k] > v->SurfaceHeightY[k]) {	5675	if (v->ViewportWidth[k] > v->SurfaceWidthY[k] \|\| v->ViewportHeight[k] > v->SurfaceHeightY[k]) {
5676	ViewportExceedsSurface = true;	5676	ViewportExceedsSurface = true;
5677	if (v->SourcePixelFormat[k] != dm_444_64 && v->SourcePixelFormat[k] != dm_444_32 && v->SourcePixelFormat[k] != dm_444_16	5677	if (v->SourcePixelFormat[k] != dm_444_64 && v->SourcePixelFormat[k] != dm_444_32
5678	&& v->SourcePixelFormat[k] != dm_444_16 && v->SourcePixelFormat[k] != dm_444_8	5678	&& v->SourcePixelFormat[k] != dm_444_16 && v->SourcePixelFormat[k] != dm_444_8
5679	&& v->SourcePixelFormat[k] != dm_rgbe) {	5679	&& v->SourcePixelFormat[k] != dm_rgbe) {
5680	if (v->ViewportWidthChroma[k] > v->SurfaceWidthC[k]	5680	if (v->ViewportWidthChroma[k] > v->SurfaceWidthC[k]

drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c+0−2

@@ -159,7 +159,6 @@ dml_get_pipe_attr_func(refcyc_per_meta_chunk_vblank_l_in_us, mode_lib->vba.TimeP · 158 unmodified lines
159	dml_get_pipe_attr_func(refcyc_per_meta_chunk_vblank_c_in_us, mode_lib->vba.TimePerChromaMetaChunkVBlank);	159	dml_get_pipe_attr_func(refcyc_per_meta_chunk_vblank_c_in_us, mode_lib->vba.TimePerChromaMetaChunkVBlank);
160	dml_get_pipe_attr_func(refcyc_per_meta_chunk_flip_l_in_us, mode_lib->vba.TimePerMetaChunkFlip);	160	dml_get_pipe_attr_func(refcyc_per_meta_chunk_flip_l_in_us, mode_lib->vba.TimePerMetaChunkFlip);
161	dml_get_pipe_attr_func(refcyc_per_meta_chunk_flip_c_in_us, mode_lib->vba.TimePerChromaMetaChunkFlip);	161	dml_get_pipe_attr_func(refcyc_per_meta_chunk_flip_c_in_us, mode_lib->vba.TimePerChromaMetaChunkFlip);
162
163	dml_get_pipe_attr_func(vstartup, mode_lib->vba.VStartup);	162	dml_get_pipe_attr_func(vstartup, mode_lib->vba.VStartup);
164	dml_get_pipe_attr_func(vupdate_offset, mode_lib->vba.VUpdateOffsetPix);	163	dml_get_pipe_attr_func(vupdate_offset, mode_lib->vba.VUpdateOffsetPix);
165	dml_get_pipe_attr_func(vupdate_width, mode_lib->vba.VUpdateWidthPix);	164	dml_get_pipe_attr_func(vupdate_width, mode_lib->vba.VUpdateWidthPix);
@@ -419,7 +418,6 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib) · 253 unmodified lines
419	visited[j] = true;	418	visited[j] = true;
420		419
421	mode_lib->vba.pipe_plane[j] = mode_lib->vba.NumberOfActivePlanes;	420	mode_lib->vba.pipe_plane[j] = mode_lib->vba.NumberOfActivePlanes;
422
423	mode_lib->vba.DPPPerPlane[mode_lib->vba.NumberOfActivePlanes] = 1;	421	mode_lib->vba.DPPPerPlane[mode_lib->vba.NumberOfActivePlanes] = 1;
424	mode_lib->vba.SourceScan[mode_lib->vba.NumberOfActivePlanes] =	422	mode_lib->vba.SourceScan[mode_lib->vba.NumberOfActivePlanes] =
425	(enum scan_direction_class) (src->source_scan);	423	(enum scan_direction_class) (src->source_scan);

drivers/gpu/drm/amd/display/dc/hdcp/hdcp_msg.c+1−0

@@ -33,6 +33,7 @@ · 32 unmodified lines
33	#include "core_types.h"	33	#include "core_types.h"
34	#include "dc_link_ddc.h"	34	#include "dc_link_ddc.h"
35	#include "link_hwss.h"	35	#include "link_hwss.h"
		36	#include "inc/link_dpcd.h"
36		37
37	#define DC_LOGGER \	38	#define DC_LOGGER \
38	link->ctx->logger	39	link->ctx->logger

drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h+10−1

 	/* to avoid infinite loop where-in the receiver
 	 * switches between different VS
 	 */
-	LINK_TRAINING_MAX_CR_RETRY = 100
+	LINK_TRAINING_MAX_CR_RETRY = 100,
+	/*
+	 * Some receivers fail to train on first try and are good
+	 * on subsequent tries. 2 retries should be plenty. If we
+	 * don't have a successful training then we don't expect to
+	 * ever get one.
+	 */
+	LINK_TRAINING_MAX_VERIFY_RETRY = 2,
+	PEAK_FACTOR_X1000 = 1006,
 };
 bool dp_verify_link_cap(
 		struct link_training_settings *lt_settings);
 enum dp_link_encoding dp_get_link_encoding_format(const struct dc_link_settings *link_settings);
+bool dp_retrieve_lttpr_cap(struct dc_link *link);
 #endif /* __DC_LINK_DP_H__ */

drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h+3−0

@@ -237,6 +237,9 @@ struct stream_encoder_funcs { · 236 unmodified lines
237	void (*dp_set_odm_combine)(	237	void (*dp_set_odm_combine)(
238	struct stream_encoder *enc,	238	struct stream_encoder *enc,
239	bool odm_combine);	239	bool odm_combine);
		240
		241	uint32_t (*get_fifo_cal_average_level)(
		242	struct stream_encoder *enc);
240	};	243	};
241		244
242	#endif /* STREAM_ENCODER_H_ */	245	#endif /* STREAM_ENCODER_H_ */

drivers/gpu/drm/amd/display/dc/inc/link_dpcd.h+18−0

@@ -0,0 +1,18 @@
	1	#ifndef __LINK_DPCD_H__
	2	#define __LINK_DPCD_H__
	3	#include <inc/core_status.h>
	4	#include <dc_link.h>
	5	#include <inc/link_hwss.h>
	6
	7	enum dc_status core_link_read_dpcd(
	8	struct dc_link *link,
	9	uint32_t address,
	10	uint8_t *data,
	11	uint32_t size);
	12
	13	enum dc_status core_link_write_dpcd(
	14	struct dc_link *link,
	15	uint32_t address,
	16	const uint8_t *data,
	17	uint32_t size);
	18	#endif

drivers/gpu/drm/amd/display/dc/inc/link_hwss.h+0−14

@@ -26,20 +26,6 @@ · 25 unmodified lines
26	#ifndef __DC_LINK_HWSS_H__	26	#ifndef __DC_LINK_HWSS_H__
27	#define __DC_LINK_HWSS_H__	27	#define __DC_LINK_HWSS_H__
28		28
29	#include "inc/core_status.h"
30
31	enum dc_status core_link_read_dpcd(
32	struct dc_link *link,
33	uint32_t address,
34	uint8_t *data,
35	uint32_t size);
36
37	enum dc_status core_link_write_dpcd(
38	struct dc_link *link,
39	uint32_t address,
40	const uint8_t *data,
41	uint32_t size);
42
43	struct gpio get_hpd_gpio(struct dc_bios dcb,	29	struct gpio get_hpd_gpio(struct dc_bios dcb,
44	struct graphics_object_id link_id,	30	struct graphics_object_id link_id,
45	struct gpio_service *gpio_service);	31	struct gpio_service *gpio_service);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h+29−0

@@ -243,6 +243,31 @@ struct dmub_srv_hw_params { · 242 unmodified lines
243	#endif	243	#endif
244	};	244	};
245		245
		246	/**
		247	* struct dmub_diagnostic_data - Diagnostic data retrieved from DMCUB for
		248	* debugging purposes, including logging, crash analysis, etc.
		249	*/
		250	struct dmub_diagnostic_data {
		251	uint32_t dmcub_version;
		252	uint32_t scratch[16];
		253	uint32_t pc;
		254	uint32_t undefined_address_fault_addr;
		255	uint32_t inst_fetch_fault_addr;
		256	uint32_t data_write_fault_addr;
		257	uint32_t inbox1_rptr;
		258	uint32_t inbox1_wptr;
		259	uint32_t inbox1_size;
		260	uint32_t inbox0_rptr;
		261	uint32_t inbox0_wptr;
		262	uint32_t inbox0_size;
		263	uint8_t is_dmcub_enabled : 1;
		264	uint8_t is_dmcub_soft_reset : 1;
		265	uint8_t is_dmcub_secure_reset : 1;
		266	uint8_t is_traceport_en : 1;
		267	uint8_t is_cw0_enabled : 1;
		268	uint8_t is_cw6_enabled : 1;
		269	};
		270
246	/**	271	/**
247	* struct dmub_srv_base_funcs - Driver specific base callbacks	272	* struct dmub_srv_base_funcs - Driver specific base callbacks
248	*/	273	*/
@@ -335,6 +360,8 @@ struct dmub_srv_hw_funcs { · 86 unmodified lines
335		360
336	void (send_inbox0_cmd)(struct dmub_srv dmub, union dmub_inbox0_data_register data);	361	void (send_inbox0_cmd)(struct dmub_srv dmub, union dmub_inbox0_data_register data);
337	uint32_t (get_current_time)(struct dmub_srv dmub);	362	uint32_t (get_current_time)(struct dmub_srv dmub);
		363
		364	void (get_diagnostic_data)(struct dmub_srv dmub, struct dmub_diagnostic_data *dmub_oca);
338	};	365	};
339		366
340	/**	367	/**
@@ -685,6 +712,8 @@ enum dmub_status dmub_srv_cmd_with_reply_data(struct dmub_srv *dmub, · 344 unmodified lines
685		712
686	bool dmub_srv_get_outbox0_msg(struct dmub_srv dmub, struct dmcub_trace_buf_entry entry);	713	bool dmub_srv_get_outbox0_msg(struct dmub_srv dmub, struct dmcub_trace_buf_entry entry);
687		714
		715	bool dmub_srv_get_diagnostic_data(struct dmub_srv dmub, struct dmub_diagnostic_data diag_data);
		716
688	#if defined(__cplusplus)	717	#if defined(__cplusplus)
689	}	718	}
690	#endif	719	#endif

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h+2−2

@@ -47,10 +47,10 @@ · 46 unmodified lines
47		47
48	/* Firmware versioning. */	48	/* Firmware versioning. */
49	#ifdef DMUB_EXPOSE_VERSION	49	#ifdef DMUB_EXPOSE_VERSION
50	#define DMUB_FW_VERSION_GIT_HASH 0xefd666c1	50	#define DMUB_FW_VERSION_GIT_HASH 0x5cac099d3
51	#define DMUB_FW_VERSION_MAJOR 0	51	#define DMUB_FW_VERSION_MAJOR 0
52	#define DMUB_FW_VERSION_MINOR 0	52	#define DMUB_FW_VERSION_MINOR 0
53	#define DMUB_FW_VERSION_REVISION 69	53	#define DMUB_FW_VERSION_REVISION 70
54	#define DMUB_FW_VERSION_TEST 0	54	#define DMUB_FW_VERSION_TEST 0
55	#define DMUB_FW_VERSION_VBIOS 0	55	#define DMUB_FW_VERSION_VBIOS 0
56	#define DMUB_FW_VERSION_HOTFIX 0	56	#define DMUB_FW_VERSION_HOTFIX 0

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c+64−1

@@ -40,7 +40,10 @@ · 39 unmodified lines
40		40
41	const struct dmub_srv_common_regs dmub_srv_dcn20_regs = {	41	const struct dmub_srv_common_regs dmub_srv_dcn20_regs = {
42	#define DMUB_SR(reg) REG_OFFSET(reg),	42	#define DMUB_SR(reg) REG_OFFSET(reg),
43	{ DMUB_COMMON_REGS() },	43	{
		44	DMUB_COMMON_REGS()
		45	DMCUB_INTERNAL_REGS()
		46	},
44	#undef DMUB_SR	47	#undef DMUB_SR
45		48
46	#define DMUB_SF(reg, field) FD_MASK(reg, field),	49	#define DMUB_SF(reg, field) FD_MASK(reg, field),
@@ -404,3 +407,63 @@ uint32_t dmub_dcn20_get_current_time(struct dmub_srv *dmub) · 357 unmodified lines
404	{	407	{
405	return REG_READ(DMCUB_TIMER_CURRENT);	408	return REG_READ(DMCUB_TIMER_CURRENT);
406	}	409	}
		410
		411	void dmub_dcn20_get_diagnostic_data(struct dmub_srv dmub, struct dmub_diagnostic_data diag_data)
		412	{
		413	uint32_t is_dmub_enabled, is_soft_reset, is_sec_reset;
		414	uint32_t is_traceport_enabled, is_cw0_enabled, is_cw6_enabled;
		415
		416	if (!dmub \|\| !diag_data)
		417	return;
		418
		419	memset(diag_data, 0, sizeof(*diag_data));
		420
		421	diag_data->dmcub_version = dmub->fw_version;
		422
		423	diag_data->scratch[0] = REG_READ(DMCUB_SCRATCH0);
		424	diag_data->scratch[1] = REG_READ(DMCUB_SCRATCH1);
		425	diag_data->scratch[2] = REG_READ(DMCUB_SCRATCH2);
		426	diag_data->scratch[3] = REG_READ(DMCUB_SCRATCH3);
		427	diag_data->scratch[4] = REG_READ(DMCUB_SCRATCH4);
		428	diag_data->scratch[5] = REG_READ(DMCUB_SCRATCH5);
		429	diag_data->scratch[6] = REG_READ(DMCUB_SCRATCH6);
		430	diag_data->scratch[7] = REG_READ(DMCUB_SCRATCH7);
		431	diag_data->scratch[8] = REG_READ(DMCUB_SCRATCH8);
		432	diag_data->scratch[9] = REG_READ(DMCUB_SCRATCH9);
		433	diag_data->scratch[10] = REG_READ(DMCUB_SCRATCH10);
		434	diag_data->scratch[11] = REG_READ(DMCUB_SCRATCH11);
		435	diag_data->scratch[12] = REG_READ(DMCUB_SCRATCH12);
		436	diag_data->scratch[13] = REG_READ(DMCUB_SCRATCH13);
		437	diag_data->scratch[14] = REG_READ(DMCUB_SCRATCH14);
		438	diag_data->scratch[15] = REG_READ(DMCUB_SCRATCH15);
		439
		440	diag_data->undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR);
		441	diag_data->inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR);
		442	diag_data->data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR);
		443
		444	diag_data->inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR);
		445	diag_data->inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR);
		446	diag_data->inbox1_size = REG_READ(DMCUB_INBOX1_SIZE);
		447
		448	diag_data->inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR);
		449	diag_data->inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR);
		450	diag_data->inbox0_size = REG_READ(DMCUB_INBOX0_SIZE);
		451
		452	REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled);
		453	diag_data->is_dmcub_enabled = is_dmub_enabled;
		454
		455	REG_GET(DMCUB_CNTL, DMCUB_SOFT_RESET, &is_soft_reset);
		456	diag_data->is_dmcub_soft_reset = is_soft_reset;
		457
		458	REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset);
		459	diag_data->is_dmcub_secure_reset = is_sec_reset;
		460
		461	REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled);
		462	diag_data->is_traceport_en = is_traceport_enabled;
		463
		464	REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled);
		465	diag_data->is_cw0_enabled = is_cw0_enabled;
		466
		467	REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled);
		468	diag_data->is_cw6_enabled = is_cw6_enabled;
		469	}

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h+13−1

 	DMUB_SR(DMCUB_CNTL) \
 	DMUB_SR(DMCUB_MEM_CNTL) \
 	DMUB_SR(DMCUB_SEC_CNTL) \
+	DMUB_SR(DMCUB_INBOX0_SIZE) \
+	DMUB_SR(DMCUB_INBOX0_RPTR) \
+	DMUB_SR(DMCUB_INBOX0_WPTR) \
 	DMUB_SR(DMCUB_INBOX1_BASE_ADDRESS) \
 	DMUB_SR(DMCUB_INBOX1_SIZE) \
 	DMUB_SR(DMCUB_INBOX1_RPTR) \
 	DMUB_SR(DCN_VM_FB_LOCATION_BASE) \
 	DMUB_SR(DCN_VM_FB_OFFSET) \
 	DMUB_SR(DMCUB_INTERRUPT_ACK) \
-	DMUB_SR(DMCUB_TIMER_CURRENT)
+	DMUB_SR(DMCUB_TIMER_CURRENT) \
+	DMUB_SR(DMCUB_INST_FETCH_FAULT_ADDR) \
+	DMUB_SR(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR) \
+	DMUB_SR(DMCUB_DATA_WRITE_FAULT_ADDR)
+#define DMCUB_INTERNAL_REGS()
 #define DMUB_COMMON_FIELDS() \
 	DMUB_SF(DMCUB_CNTL, DMCUB_ENABLE) \
 	DMUB_SF(DMCUB_MEM_CNTL, DMCUB_MEM_WRITE_SPACE) \
 	DMUB_SF(DMCUB_SEC_CNTL, DMCUB_SEC_RESET) \
 	DMUB_SF(DMCUB_SEC_CNTL, DMCUB_MEM_UNIT_ID) \
+	DMUB_SF(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS) \
 	DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_TOP_ADDRESS) \
 	DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE) \
 	DMUB_SF(DMCUB_REGION3_CW1_TOP_ADDRESS, DMCUB_REGION3_CW1_TOP_ADDRESS) \
 struct dmub_srv_common_reg_offset {
 #define DMUB_SR(reg) uint32_t reg;
 	DMUB_COMMON_REGS()
+	DMCUB_INTERNAL_REGS()
 #undef DMUB_SR
 };
 uint32_t dmub_dcn20_get_current_time(struct dmub_srv *dmub);
+void dmub_dcn20_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *dmub_oca);
 #endif /* _DMUB_DCN20_H_ */

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c+4−1

 const struct dmub_srv_common_regs dmub_srv_dcn21_regs = {
 #define DMUB_SR(reg) REG_OFFSET(reg),
-	{ DMUB_COMMON_REGS() },
+	{
+		DMUB_COMMON_REGS()
+		DMCUB_INTERNAL_REGS()
+	},
 #undef DMUB_SR
 #define DMUB_SF(reg, field) FD_MASK(reg, field),

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c+4−1

 const struct dmub_srv_common_regs dmub_srv_dcn30_regs = {
 #define DMUB_SR(reg) REG_OFFSET(reg),
-	{ DMUB_COMMON_REGS() },
+	{
+		DMUB_COMMON_REGS()
+		DMCUB_INTERNAL_REGS()
+	},
 #undef DMUB_SR
 #define DMUB_SF(reg, field) FD_MASK(reg, field),

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn301.c+4−1

 const struct dmub_srv_common_regs dmub_srv_dcn301_regs = {
 #define DMUB_SR(reg) REG_OFFSET(reg),
-	{ DMUB_COMMON_REGS() },
+	{
+		DMUB_COMMON_REGS()
+		DMCUB_INTERNAL_REGS()
+	},
 #undef DMUB_SR
 #define DMUB_SF(reg, field) FD_MASK(reg, field),

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn302.c+4−1

 const struct dmub_srv_common_regs dmub_srv_dcn302_regs = {
 #define DMUB_SR(reg) REG_OFFSET(reg),
-	{ DMUB_COMMON_REGS() },
+	{
+		DMUB_COMMON_REGS()
+		DMCUB_INTERNAL_REGS()
+	},
 #undef DMUB_SR
 #define DMUB_SF(reg, field) FD_MASK(reg, field),

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn303.c+4−1

 const struct dmub_srv_common_regs dmub_srv_dcn303_regs = {
 #define DMUB_SR(reg) REG_OFFSET(reg),
-	{ DMUB_COMMON_REGS() },
+	{
+		DMUB_COMMON_REGS()
+		DMCUB_INTERNAL_REGS()
+	},
 #undef DMUB_SR
 #define DMUB_SF(reg, field) FD_MASK(reg, field),

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c+10−0

@@ -176,6 +176,8 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) · 175 unmodified lines
176	funcs->get_outbox0_wptr = dmub_dcn20_get_outbox0_wptr;	176	funcs->get_outbox0_wptr = dmub_dcn20_get_outbox0_wptr;
177	funcs->set_outbox0_rptr = dmub_dcn20_set_outbox0_rptr;	177	funcs->set_outbox0_rptr = dmub_dcn20_set_outbox0_rptr;
178		178
		179	funcs->get_diagnostic_data = dmub_dcn20_get_diagnostic_data;
		180
179	if (asic == DMUB_ASIC_DCN21) {	181	if (asic == DMUB_ASIC_DCN21) {
180	dmub->regs = &dmub_srv_dcn21_regs;	182	dmub->regs = &dmub_srv_dcn21_regs;
181		183
@@ -794,3 +796,11 @@ bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entr · 612 unmodified lines
794		796
795	return dmub_rb_out_trace_buffer_front(&dmub->outbox0_rb, (void *)entry);	797	return dmub_rb_out_trace_buffer_front(&dmub->outbox0_rb, (void *)entry);
796	}	798	}
		799
		800	bool dmub_srv_get_diagnostic_data(struct dmub_srv dmub, struct dmub_diagnostic_data diag_data)
		801	{
		802	if (!dmub \|\| !dmub->hw_funcs.get_diagnostic_data \|\| !diag_data)
		803	return false;
		804	dmub->hw_funcs.get_diagnostic_data(dmub, diag_data);
		805	return true;
		806	}

drivers/gpu/drm/amd/display/modules/power/power_helpers.c+10−10

@@ -87,19 +87,19 @@ struct abm_parameters { · 86 unmodified lines
87	};	87	};
88		88
89	static const struct abm_parameters abm_settings_config0[abm_defines_max_level] = {	89	static const struct abm_parameters abm_settings_config0[abm_defines_max_level] = {
90	// min_red max_red bright_pos dark_pos bright_gain contrast dev min_knee max_knee blStart blRed	90	// min_red max_red bright_pos dark_pos bright_gain contrast dev min_knee max_knee blRed blStart
91	{0xff, 0xbf, 0x20, 0x00, 0xff, 0x99, 0xb3, 0x40, 0xe0, 0xCCCC, 0xCCCC},	91	{0xff, 0xbf, 0x20, 0x00, 0xff, 0x99, 0xb3, 0x40, 0xe0, 0xf777, 0xcccc},
92	{0xde, 0x85, 0x20, 0x00, 0xff, 0x90, 0xa8, 0x40, 0xdf, 0xCCCC, 0xCCCC},	92	{0xde, 0x85, 0x20, 0x00, 0xe0, 0x90, 0xa8, 0x40, 0xc8, 0xf777, 0xcccc},
93	{0xb0, 0x50, 0x20, 0x00, 0xc0, 0x88, 0x78, 0x70, 0xa0, 0xCCCC, 0xCCCC},	93	{0xb0, 0x50, 0x20, 0x00, 0xc0, 0x88, 0x78, 0x70, 0xa0, 0xeeee, 0x9999},
94	{0x82, 0x40, 0x20, 0x00, 0x00, 0xff, 0xb3, 0x70, 0x70, 0xCCCC, 0xCCCC},	94	{0x82, 0x40, 0x20, 0x00, 0x00, 0xb8, 0xb3, 0x70, 0x70, 0xe333, 0xb333},
95	};	95	};
96		96
97	static const struct abm_parameters abm_settings_config1[abm_defines_max_level] = {	97	static const struct abm_parameters abm_settings_config1[abm_defines_max_level] = {
98	// min_red max_red bright_pos dark_pos bright_gain contrast dev min_knee max_knee blStart blRed	98	// min_red max_red bright_pos dark_pos bright_gain contrast dev min_knee max_knee blRed blStart
99	{0xf0, 0xd9, 0x20, 0x00, 0x00, 0xff, 0xb3, 0x70, 0x70, 0xCCCC, 0xCCCC},	99	{0xf0, 0xd9, 0x20, 0x00, 0x00, 0xff, 0xb3, 0x70, 0x70, 0xcccc, 0xcccc},
100	{0xcd, 0xa5, 0x20, 0x00, 0x00, 0xff, 0xb3, 0x70, 0x70, 0xCCCC, 0xCCCC},	100	{0xcd, 0xa5, 0x20, 0x00, 0x00, 0xff, 0xb3, 0x70, 0x70, 0xcccc, 0xcccc},
101	{0x99, 0x65, 0x20, 0x00, 0x00, 0xff, 0xb3, 0x70, 0x70, 0xCCCC, 0xCCCC},	101	{0x99, 0x65, 0x20, 0x00, 0x00, 0xff, 0xb3, 0x70, 0x70, 0xcccc, 0xcccc},
102	{0x82, 0x4d, 0x20, 0x00, 0x00, 0xff, 0xb3, 0x70, 0x70, 0xCCCC, 0xCCCC},	102	{0x82, 0x4d, 0x20, 0x00, 0x00, 0xff, 0xb3, 0x70, 0x70, 0xcccc, 0xcccc},
103	};	103	};
104		104
105	static const struct abm_parameters * const abm_settings[] = {	105	static const struct abm_parameters * const abm_settings[] = {

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_1_sh_mask.h+2−0

 #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                   0x000000FCL
 #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK                                                         0x00000100L
 #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                 0x0000FC00L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK                                                     0x001F0000L
 #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK                                                     0x03C00000L
 #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK                                                    0x04000000L
 #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK                                                        0x20000000L
 #define DIG3_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                 0x2
 #define DIG3_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT                                                       0x8
 #define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                               0xa
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT                                                   0x10
 #define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                   0x16
 #define DIG3_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                  0x1a
 #define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT                                                      0x1d

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h+2−0

 #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                 0x2
 #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT                                                       0x8
 #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                               0xa
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT                                                   0x10
 #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                   0x16
 #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                  0x1a
 #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT                                                      0x1d
 #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                   0x000000FCL
 #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK                                                         0x00000100L
 #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                 0x0000FC00L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK                                                     0x001F0000L
 #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK                                                     0x03C00000L
 #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK                                                    0x04000000L
 #define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK                                                        0x20000000L

drivers/gpu/drm/amd/include/kgd_pp_interface.h+57−1

@@ -560,7 +560,7 @@ struct gpu_metrics_v1_2 { · 559 unmodified lines
560	uint16_t current_vclk1;	560	uint16_t current_vclk1;
561	uint16_t current_dclk1;	561	uint16_t current_dclk1;
562		562
563	/* Throttle status */	563	/* Throttle status (ASIC dependent) */
564	uint32_t throttle_status;	564	uint32_t throttle_status;
565		565
566	/* Fans */	566	/* Fans */
@@ -648,6 +648,9 @@ struct gpu_metrics_v1_3 { · 81 unmodified lines
648	uint16_t voltage_mem;	648	uint16_t voltage_mem;
649		649
650	uint16_t padding1;	650	uint16_t padding1;
		651
		652	/* Throttle status (ASIC independent) */
		653	uint64_t indep_throttle_status;
651	};	654	};
652		655
653	/*	656	/*
@@ -754,4 +757,57 @@ struct gpu_metrics_v2_1 { · 100 unmodified lines
754	uint16_t padding[3];	757	uint16_t padding[3];
755	};	758	};
756		759
		760	struct gpu_metrics_v2_2 {
		761	struct metrics_table_header common_header;
		762
		763	/* Temperature */
		764	uint16_t temperature_gfx; // gfx temperature on APUs
		765	uint16_t temperature_soc; // soc temperature on APUs
		766	uint16_t temperature_core[8]; // CPU core temperature on APUs
		767	uint16_t temperature_l3[2];
		768
		769	/* Utilization */
		770	uint16_t average_gfx_activity;
		771	uint16_t average_mm_activity; // UVD or VCN
		772
		773	/* Driver attached timestamp (in ns) */
		774	uint64_t system_clock_counter;
		775
		776	/* Power/Energy */
		777	uint16_t average_socket_power; // dGPU + APU power on A + A platform
		778	uint16_t average_cpu_power;
		779	uint16_t average_soc_power;
		780	uint16_t average_gfx_power;
		781	uint16_t average_core_power[8]; // CPU core power on APUs
		782
		783	/* Average clocks */
		784	uint16_t average_gfxclk_frequency;
		785	uint16_t average_socclk_frequency;
		786	uint16_t average_uclk_frequency;
		787	uint16_t average_fclk_frequency;
		788	uint16_t average_vclk_frequency;
		789	uint16_t average_dclk_frequency;
		790
		791	/* Current clocks */
		792	uint16_t current_gfxclk;
		793	uint16_t current_socclk;
		794	uint16_t current_uclk;
		795	uint16_t current_fclk;
		796	uint16_t current_vclk;
		797	uint16_t current_dclk;
		798	uint16_t current_coreclk[8]; // CPU core clocks
		799	uint16_t current_l3clk[2];
		800
		801	/* Throttle status (ASIC dependent) */
		802	uint32_t throttle_status;
		803
		804	/* Fans */
		805	uint16_t fan_pwm;
		806
		807	uint16_t padding[3];
		808
		809	/* Throttle status (ASIC independent) */
		810	uint64_t indep_throttle_status;
		811	};
		812
757	#endif	813	#endif

drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h+49−2

@@ -35,6 +35,48 @@ · 34 unmodified lines
35		35
36	#define SMU_DPM_USER_PROFILE_RESTORE (1 << 0)	36	#define SMU_DPM_USER_PROFILE_RESTORE (1 << 0)
37		37
		38	// Power Throttlers
		39	#define SMU_THROTTLER_PPT0_BIT 0
		40	#define SMU_THROTTLER_PPT1_BIT 1
		41	#define SMU_THROTTLER_PPT2_BIT 2
		42	#define SMU_THROTTLER_PPT3_BIT 3
		43	#define SMU_THROTTLER_SPL_BIT 4
		44	#define SMU_THROTTLER_FPPT_BIT 5
		45	#define SMU_THROTTLER_SPPT_BIT 6
		46	#define SMU_THROTTLER_SPPT_APU_BIT 7
		47
		48	// Current Throttlers
		49	#define SMU_THROTTLER_TDC_GFX_BIT 16
		50	#define SMU_THROTTLER_TDC_SOC_BIT 17
		51	#define SMU_THROTTLER_TDC_MEM_BIT 18
		52	#define SMU_THROTTLER_TDC_VDD_BIT 19
		53	#define SMU_THROTTLER_TDC_CVIP_BIT 20
		54	#define SMU_THROTTLER_EDC_CPU_BIT 21
		55	#define SMU_THROTTLER_EDC_GFX_BIT 22
		56	#define SMU_THROTTLER_APCC_BIT 23
		57
		58	// Temperature
		59	#define SMU_THROTTLER_TEMP_GPU_BIT 32
		60	#define SMU_THROTTLER_TEMP_CORE_BIT 33
		61	#define SMU_THROTTLER_TEMP_MEM_BIT 34
		62	#define SMU_THROTTLER_TEMP_EDGE_BIT 35
		63	#define SMU_THROTTLER_TEMP_HOTSPOT_BIT 36
		64	#define SMU_THROTTLER_TEMP_SOC_BIT 37
		65	#define SMU_THROTTLER_TEMP_VR_GFX_BIT 38
		66	#define SMU_THROTTLER_TEMP_VR_SOC_BIT 39
		67	#define SMU_THROTTLER_TEMP_VR_MEM0_BIT 40
		68	#define SMU_THROTTLER_TEMP_VR_MEM1_BIT 41
		69	#define SMU_THROTTLER_TEMP_LIQUID0_BIT 42
		70	#define SMU_THROTTLER_TEMP_LIQUID1_BIT 43
		71	#define SMU_THROTTLER_VRHOT0_BIT 44
		72	#define SMU_THROTTLER_VRHOT1_BIT 45
		73	#define SMU_THROTTLER_PROCHOT_CPU_BIT 46
		74	#define SMU_THROTTLER_PROCHOT_GFX_BIT 47
		75
		76	// Other
		77	#define SMU_THROTTLER_PPM_BIT 56
		78	#define SMU_THROTTLER_FIT_BIT 57
		79
38	struct smu_hw_power_state {	80	struct smu_hw_power_state {
39	unsigned int magic;	81	unsigned int magic;
40	};	82	};
@@ -723,7 +765,10 @@ struct pptable_funcs { · 682 unmodified lines
723	/**	765	/**
724	* @get_power_limit: Get the device's power limits.	766	* @get_power_limit: Get the device's power limits.
725	*/	767	*/
726	int (get_power_limit)(struct smu_context smu);	768	int (get_power_limit)(struct smu_context smu,
		769	uint32_t *current_power_limit,
		770	uint32_t *default_power_limit,
		771	uint32_t *max_power_limit);
727		772
728	/**	773	/**
729	* @get_ppt_limit: Get the device's ppt limits.	774	* @get_ppt_limit: Get the device's ppt limits.
@@ -932,7 +977,9 @@ struct pptable_funcs { · 202 unmodified lines
932	* @disable_all_features_with_exception: Disable all features with	977	* @disable_all_features_with_exception: Disable all features with
933	* exception to those in &mask.	978	* exception to those in &mask.
934	*/	979	*/
935	int (disable_all_features_with_exception)(struct smu_context smu, enum smu_feature_mask mask);	980	int (disable_all_features_with_exception)(struct smu_context smu,
		981	bool no_hw_disablement,
		982	enum smu_feature_mask mask);
936		983
937	/**	984	/**
938	* @notify_display_change: Enable fast memory clock switching.	985	* @notify_display_change: Enable fast memory clock switching.

drivers/gpu/drm/amd/pm/inc/smu_v11_0.h+3−0

@@ -244,6 +244,9 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state) · 243 unmodified lines
244	int smu_v11_0_baco_enter(struct smu_context *smu);	244	int smu_v11_0_baco_enter(struct smu_context *smu);
245	int smu_v11_0_baco_exit(struct smu_context *smu);	245	int smu_v11_0_baco_exit(struct smu_context *smu);
246		246
		247	int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu,
		248	enum smu_v11_0_baco_seq baco_seq);
		249
247	int smu_v11_0_mode1_reset(struct smu_context *smu);	250	int smu_v11_0_mode1_reset(struct smu_context *smu);
248		251
249	int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,	252	int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c+22−4

 		return ret;
 	}
-	ret = smu_get_asic_power_limits(smu);
+	ret = smu_get_asic_power_limits(smu,
+					&smu->current_power_limit,
+					&smu->default_power_limit,
+					&smu->max_power_limit);
 	if (ret) {
 		dev_err(adev->dev, "Failed to get asic power limits!\n");
 		return ret;
 	if (smu->uploading_custom_pp_table &&
 	    (adev->asic_type >= CHIP_NAVI10) &&
 	    (adev->asic_type <= CHIP_DIMGREY_CAVEFISH))
-		return 0;
+		return smu_disable_all_features_with_exception(smu,
+							       true,
+							       SMU_FEATURE_COUNT);
 	/*
 	 * For Sienna_Cichlid, PMFW will handle the features disablement properly
 	 * on BACO in. Driver involvement is unnecessary.
 	 */
-	if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
+	if (((adev->asic_type == CHIP_SIENNA_CICHLID) ||
+	     ((adev->asic_type >= CHIP_NAVI10) && (adev->asic_type <= CHIP_NAVI12))) &&
 	     use_baco)
-		return 0;
+		return smu_disable_all_features_with_exception(smu,
+							       true,
+							       SMU_FEATURE_BACO_BIT);
 	/*
 	 * For gpu reset, runpm and hibernation through BACO,
 	 */
 	if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) {
 		ret = smu_disable_all_features_with_exception(smu,
+							      false,
 							      SMU_FEATURE_BACO_BIT);
 		if (ret)
 			dev_err(adev->dev, "Failed to disable smu features except BACO.\n");
 	} else {
 		switch (limit_level) {
 		case SMU_PPT_LIMIT_CURRENT:
+			if ((smu->adev->asic_type == CHIP_ALDEBARAN) ||
+			     (smu->adev->asic_type == CHIP_SIENNA_CICHLID) ||
+			     (smu->adev->asic_type == CHIP_NAVY_FLOUNDER) ||
+			     (smu->adev->asic_type == CHIP_DIMGREY_CAVEFISH) ||
+			     (smu->adev->asic_type == CHIP_BEIGE_GOBY))
+				ret = smu_get_asic_power_limits(smu,
+								&smu->current_power_limit,
+								NULL,
+								NULL);
 			*limit = smu->current_power_limit;
 			break;
 		case SMU_PPT_LIMIT_DEFAULT:

drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c+46−13

 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,		WORKLOAD_PPLIB_CUSTOM_BIT),
 };
+static const uint8_t arcturus_throttler_map[] = {
+	[THROTTLER_TEMP_EDGE_BIT]	= (SMU_THROTTLER_TEMP_EDGE_BIT),
+	[THROTTLER_TEMP_HOTSPOT_BIT]	= (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
+	[THROTTLER_TEMP_MEM_BIT]	= (SMU_THROTTLER_TEMP_MEM_BIT),
+	[THROTTLER_TEMP_VR_GFX_BIT]	= (SMU_THROTTLER_TEMP_VR_GFX_BIT),
+	[THROTTLER_TEMP_VR_MEM_BIT]	= (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
+	[THROTTLER_TEMP_VR_SOC_BIT]	= (SMU_THROTTLER_TEMP_VR_SOC_BIT),
+	[THROTTLER_TDC_GFX_BIT]		= (SMU_THROTTLER_TDC_GFX_BIT),
+	[THROTTLER_TDC_SOC_BIT]		= (SMU_THROTTLER_TDC_SOC_BIT),
+	[THROTTLER_PPT0_BIT]		= (SMU_THROTTLER_PPT0_BIT),
+	[THROTTLER_PPT1_BIT]		= (SMU_THROTTLER_PPT1_BIT),
+	[THROTTLER_PPT2_BIT]		= (SMU_THROTTLER_PPT2_BIT),
+	[THROTTLER_PPT3_BIT]		= (SMU_THROTTLER_PPT3_BIT),
+	[THROTTLER_PPM_BIT]		= (SMU_THROTTLER_PPM_BIT),
+	[THROTTLER_FIT_BIT]		= (SMU_THROTTLER_FIT_BIT),
+	[THROTTLER_APCC_BIT]		= (SMU_THROTTLER_APCC_BIT),
+	[THROTTLER_VRHOT0_BIT]		= (SMU_THROTTLER_VRHOT0_BIT),
+	[THROTTLER_VRHOT1_BIT]		= (SMU_THROTTLER_VRHOT1_BIT),
+};
 static int arcturus_tables_init(struct smu_context *smu)
 {
 	struct smu_table_context *smu_table = &smu->smu_table;
 		return -ENOMEM;
 	smu_table->metrics_time = 0;
-	smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_1);
+	smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
 	smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 	if (!smu_table->gpu_metrics_table) {
 		kfree(smu_table->metrics_table);
 	return 0;
 }
-static int arcturus_get_power_limit(struct smu_context *smu)
+static int arcturus_get_power_limit(struct smu_context *smu,
+				    uint32_t *current_power_limit,
+				    uint32_t *default_power_limit,
+				    uint32_t *max_power_limit)
 {
 	struct smu_11_0_powerplay_table *powerplay_table =
 		(struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table;
 		power_limit =
 			pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
 	}
-	smu->current_power_limit = smu->default_power_limit = power_limit;
-	if (smu->od_enabled) {
+	if (current_power_limit)
-		od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
+		*current_power_limit = power_limit;
+	if (default_power_limit)
+		*default_power_limit = power_limit;
+	if (max_power_limit) {
+		if (smu->od_enabled) {
+			od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
-		dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
+			dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
+			power_limit *= (100 + od_percent);
+			power_limit /= 100;
+		}
-		power_limit *= (100 + od_percent);
+		*max_power_limit = power_limit;
-		power_limit /= 100;
 	}
-	smu->max_power_limit = power_limit;
 	return 0;
 }
 					void **table)
 {
 	struct smu_table_context *smu_table = &smu->smu_table;
-	struct gpu_metrics_v1_1 *gpu_metrics =
+	struct gpu_metrics_v1_3 *gpu_metrics =
-		(struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table;
+		(struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
 	SmuMetrics_t metrics;
 	int ret = 0;
 	if (ret)
 		return ret;
-	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1);
+	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
 	gpu_metrics->temperature_edge = metrics.TemperatureEdge;
 	gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
 	gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
 	gpu_metrics->throttle_status = metrics.ThrottlerStatus;
+	gpu_metrics->indep_throttle_status =
+			smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
+							   arcturus_throttler_map);
 	gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
 	*table = (void *)gpu_metrics;
-	return sizeof(struct gpu_metrics_v1_1);
+	return sizeof(struct gpu_metrics_v1_3);
 }
 static const struct pptable_funcs arcturus_ppt_funcs = {

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c+79−36

@@ -238,6 +238,28 @@ static struct cmn2asic_mapping navi10_workload_map[PP_SMC_POWER_PROFILE_COUNT] = · 237 unmodified lines
238	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),	238	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
239	};	239	};
240		240
		241	static const uint8_t navi1x_throttler_map[] = {
		242	[THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT),
		243	[THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
		244	[THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
		245	[THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
		246	[THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
		247	[THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
		248	[THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
		249	[THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
		250	[THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
		251	[THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
		252	[THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
		253	[THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT),
		254	[THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT),
		255	[THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT),
		256	[THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT),
		257	[THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT),
		258	[THROTTLER_PPM_BIT] = (SMU_THROTTLER_PPM_BIT),
		259	[THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT),
		260	};
		261
		262
241	static bool is_asic_secure(struct smu_context *smu)	263	static bool is_asic_secure(struct smu_context *smu)
242	{	264	{
243	struct amdgpu_device *adev = smu->adev;	265	struct amdgpu_device *adev = smu->adev;
@@ -446,30 +468,6 @@ static int navi10_store_powerplay_table(struct smu_context *smu) · 202 unmodified lines
446	return 0;	468	return 0;
447	}	469	}
448		470
449	static int navi10_set_mp1_state(struct smu_context *smu,
450	enum pp_mp1_state mp1_state)
451	{
452	struct amdgpu_device *adev = smu->adev;
453	uint32_t mp1_fw_flags;
454	int ret = 0;
455
456	ret = smu_cmn_set_mp1_state(smu, mp1_state);
457	if (ret)
458	return ret;
459
460	if (mp1_state == PP_MP1_STATE_UNLOAD) {
461	mp1_fw_flags = RREG32_PCIE(MP1_Public \|
462	(smnMP1_FIRMWARE_FLAGS & 0xffffffff));
463
464	mp1_fw_flags &= ~MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK;
465
466	WREG32_PCIE(MP1_Public \|
467	(smnMP1_FIRMWARE_FLAGS & 0xffffffff), mp1_fw_flags);
468	}
469
470	return 0;
471	}
472
473	static int navi10_setup_pptable(struct smu_context *smu)	471	static int navi10_setup_pptable(struct smu_context *smu)
474	{	472	{
475	int ret = 0;	473	int ret = 0;
@@ -2138,7 +2136,10 @@ static int navi10_display_disable_memory_clock_switch(struct smu_context *smu, · 1662 unmodified lines
2138	return ret;	2136	return ret;
2139	}	2137	}
2140		2138
2141	static int navi10_get_power_limit(struct smu_context *smu)	2139	static int navi10_get_power_limit(struct smu_context *smu,
		2140	uint32_t *current_power_limit,
		2141	uint32_t *default_power_limit,
		2142	uint32_t *max_power_limit)
2142	{	2143	{
2143	struct smu_11_0_powerplay_table *powerplay_table =	2144	struct smu_11_0_powerplay_table *powerplay_table =
2144	(struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table;	2145	(struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table;
@@ -2155,18 +2156,25 @@ static int navi10_get_power_limit(struct smu_context *smu) · 10 unmodified lines
2155	power_limit =	2156	power_limit =
2156	pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];	2157	pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
2157	}	2158	}
2158	smu->current_power_limit = smu->default_power_limit = power_limit;
2159		2159
2160	if (smu->od_enabled &&	2160	if (current_power_limit)
2161	navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_POWER_LIMIT)) {	2161	*current_power_limit = power_limit;
2162	od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);	2162	if (default_power_limit)
		2163	*default_power_limit = power_limit;
2163		2164
2164	dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);	2165	if (max_power_limit) {
		2166	if (smu->od_enabled &&
		2167	navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_POWER_LIMIT)) {
		2168	od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
2165		2169
2166	power_limit *= (100 + od_percent);	2170	dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
2167	power_limit /= 100;	2171
		2172	power_limit *= (100 + od_percent);
		2173	power_limit /= 100;
		2174	}
		2175
		2176	*max_power_limit = power_limit;
2168	}	2177	}
2169	smu->max_power_limit = power_limit;
2170		2178
2171	return 0;	2179	return 0;
2172	}	2180	}
@@ -2257,6 +2265,29 @@ static int navi10_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu, · 84 unmodified lines
2257	return 0;	2265	return 0;
2258	}	2266	}
2259		2267
		2268	static int navi10_baco_enter(struct smu_context *smu)
		2269	{
		2270	struct amdgpu_device *adev = smu->adev;
		2271
		2272	if (adev->in_runpm)
		2273	return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
		2274	else
		2275	return smu_v11_0_baco_enter(smu);
		2276	}
		2277
		2278	static int navi10_baco_exit(struct smu_context *smu)
		2279	{
		2280	struct amdgpu_device *adev = smu->adev;
		2281
		2282	if (adev->in_runpm) {
		2283	/* Wait for PMFW handling for the Dstate change */
		2284	msleep(10);
		2285	return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
		2286	} else {
		2287	return smu_v11_0_baco_exit(smu);
		2288	}
		2289	}
		2290
2260	static int navi10_set_default_od_settings(struct smu_context *smu)	2291	static int navi10_set_default_od_settings(struct smu_context *smu)
2261	{	2292	{
2262	OverDriveTable_t *od_table =	2293	OverDriveTable_t *od_table =
@@ -2676,6 +2707,9 @@ static ssize_t navi10_get_legacy_gpu_metrics(struct smu_context *smu, · 413 unmodified lines
2676	gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];	2707	gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
2677		2708
2678	gpu_metrics->throttle_status = metrics.ThrottlerStatus;	2709	gpu_metrics->throttle_status = metrics.ThrottlerStatus;
		2710	gpu_metrics->indep_throttle_status =
		2711	smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
		2712	navi1x_throttler_map);
2679		2713
2680	gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;	2714	gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
2681		2715
@@ -2753,6 +2787,9 @@ static ssize_t navi10_get_gpu_metrics(struct smu_context *smu, · 71 unmodified lines
2753	gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];	2787	gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
2754		2788
2755	gpu_metrics->throttle_status = metrics.ThrottlerStatus;	2789	gpu_metrics->throttle_status = metrics.ThrottlerStatus;
		2790	gpu_metrics->indep_throttle_status =
		2791	smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
		2792	navi1x_throttler_map);
2756		2793
2757	gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;	2794	gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
2758		2795
@@ -2829,6 +2866,9 @@ static ssize_t navi12_get_legacy_gpu_metrics(struct smu_context *smu, · 70 unmodified lines
2829	gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];	2866	gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
2830		2867
2831	gpu_metrics->throttle_status = metrics.ThrottlerStatus;	2868	gpu_metrics->throttle_status = metrics.ThrottlerStatus;
		2869	gpu_metrics->indep_throttle_status =
		2870	smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
		2871	navi1x_throttler_map);
2832		2872
2833	gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;	2873	gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
2834		2874
@@ -2911,6 +2951,9 @@ static ssize_t navi12_get_gpu_metrics(struct smu_context *smu, · 76 unmodified lines
2911	gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];	2951	gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
2912		2952
2913	gpu_metrics->throttle_status = metrics.ThrottlerStatus;	2953	gpu_metrics->throttle_status = metrics.ThrottlerStatus;
		2954	gpu_metrics->indep_throttle_status =
		2955	smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
		2956	navi1x_throttler_map);
2914		2957
2915	gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;	2958	gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
2916		2959
@@ -3095,8 +3138,8 @@ static const struct pptable_funcs navi10_ppt_funcs = { · 178 unmodified lines
3095	.baco_is_support = smu_v11_0_baco_is_support,	3138	.baco_is_support = smu_v11_0_baco_is_support,
3096	.baco_get_state = smu_v11_0_baco_get_state,	3139	.baco_get_state = smu_v11_0_baco_get_state,
3097	.baco_set_state = smu_v11_0_baco_set_state,	3140	.baco_set_state = smu_v11_0_baco_set_state,
3098	.baco_enter = smu_v11_0_baco_enter,	3141	.baco_enter = navi10_baco_enter,
3099	.baco_exit = smu_v11_0_baco_exit,	3142	.baco_exit = navi10_baco_exit,
3100	.get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,	3143	.get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
3101	.set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,	3144	.set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
3102	.set_default_od_settings = navi10_set_default_od_settings,	3145	.set_default_od_settings = navi10_set_default_od_settings,
@@ -3112,7 +3155,7 @@ static const struct pptable_funcs navi10_ppt_funcs = { · 9 unmodified lines
3112	.get_fan_parameters = navi10_get_fan_parameters,	3155	.get_fan_parameters = navi10_get_fan_parameters,
3113	.post_init = navi10_post_smu_init,	3156	.post_init = navi10_post_smu_init,
3114	.interrupt_work = smu_v11_0_interrupt_work,	3157	.interrupt_work = smu_v11_0_interrupt_work,
3115	.set_mp1_state = navi10_set_mp1_state,	3158	.set_mp1_state = smu_cmn_set_mp1_state,
3116	};	3159	};
3117		3160
3118	void navi10_set_ppt_funcs(struct smu_context *smu)	3161	void navi10_set_ppt_funcs(struct smu_context *smu)

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c+71−15

 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,		WORKLOAD_PPLIB_CUSTOM_BIT),
 };
+static const uint8_t sienna_cichlid_throttler_map[] = {
+	[THROTTLER_TEMP_EDGE_BIT]	= (SMU_THROTTLER_TEMP_EDGE_BIT),
+	[THROTTLER_TEMP_HOTSPOT_BIT]	= (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
+	[THROTTLER_TEMP_MEM_BIT]	= (SMU_THROTTLER_TEMP_MEM_BIT),
+	[THROTTLER_TEMP_VR_GFX_BIT]	= (SMU_THROTTLER_TEMP_VR_GFX_BIT),
+	[THROTTLER_TEMP_VR_MEM0_BIT]	= (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
+	[THROTTLER_TEMP_VR_MEM1_BIT]	= (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
+	[THROTTLER_TEMP_VR_SOC_BIT]	= (SMU_THROTTLER_TEMP_VR_SOC_BIT),
+	[THROTTLER_TEMP_LIQUID0_BIT]	= (SMU_THROTTLER_TEMP_LIQUID0_BIT),
+	[THROTTLER_TEMP_LIQUID1_BIT]	= (SMU_THROTTLER_TEMP_LIQUID1_BIT),
+	[THROTTLER_TDC_GFX_BIT]		= (SMU_THROTTLER_TDC_GFX_BIT),
+	[THROTTLER_TDC_SOC_BIT]		= (SMU_THROTTLER_TDC_SOC_BIT),
+	[THROTTLER_PPT0_BIT]		= (SMU_THROTTLER_PPT0_BIT),
+	[THROTTLER_PPT1_BIT]		= (SMU_THROTTLER_PPT1_BIT),
+	[THROTTLER_PPT2_BIT]		= (SMU_THROTTLER_PPT2_BIT),
+	[THROTTLER_PPT3_BIT]		= (SMU_THROTTLER_PPT3_BIT),
+	[THROTTLER_FIT_BIT]		= (SMU_THROTTLER_FIT_BIT),
+	[THROTTLER_PPM_BIT]		= (SMU_THROTTLER_PPM_BIT),
+	[THROTTLER_APCC_BIT]		= (SMU_THROTTLER_APCC_BIT),
+};
 static int
 sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
 				  uint32_t *feature_mask, uint32_t num)
 		goto err0_out;
 	smu_table->metrics_time = 0;
-	smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_1);
+	smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
 	smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 	if (!smu_table->gpu_metrics_table)
 		goto err1_out;
 	return ret;
 }
-static int sienna_cichlid_get_power_limit(struct smu_context *smu)
+static int sienna_cichlid_get_power_limit(struct smu_context *smu,
+					  uint32_t *current_power_limit,
+					  uint32_t *default_power_limit,
+					  uint32_t *max_power_limit)
 {
 	struct smu_11_0_7_powerplay_table *powerplay_table =
 		(struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table;
 		power_limit =
 			table_member[PPT_THROTTLER_PPT0];
 	}
-	smu->current_power_limit = smu->default_power_limit = power_limit;
-	if (smu->od_enabled) {
+	if (current_power_limit)
-		od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
+		*current_power_limit = power_limit;
+	if (default_power_limit)
+		*default_power_limit = power_limit;
+	if (max_power_limit) {
+		if (smu->od_enabled) {
+			od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
-		dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
+			dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
-		power_limit *= (100 + od_percent);
+			power_limit *= (100 + od_percent);
-		power_limit /= 100;
+			power_limit /= 100;
+		}
+		*max_power_limit = power_limit;
 	}
-	smu->max_power_limit = power_limit;
 	return 0;
 }
 	return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
 }
+static int sienna_cichlid_baco_enter(struct smu_context *smu)
+{
+	struct amdgpu_device *adev = smu->adev;
+	if (adev->in_runpm)
+		return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
+	else
+		return smu_v11_0_baco_enter(smu);
+}
+static int sienna_cichlid_baco_exit(struct smu_context *smu)
+{
+	struct amdgpu_device *adev = smu->adev;
+	if (adev->in_runpm) {
+		/* Wait for PMFW handling for the Dstate change */
+		msleep(10);
+		return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
+	} else {
+		return smu_v11_0_baco_exit(smu);
+	}
+}
 static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu)
 {
 	struct amdgpu_device *adev = smu->adev;
 					      void **table)
 {
 	struct smu_table_context *smu_table = &smu->smu_table;
-	struct gpu_metrics_v1_1 *gpu_metrics =
+	struct gpu_metrics_v1_3 *gpu_metrics =
-		(struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table;
+		(struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
 	SmuMetricsExternal_t metrics_external;
 	SmuMetrics_t *metrics =
 		&(metrics_external.SmuMetrics);
 	if (ret)
 		return ret;
-	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1);
+	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
 	gpu_metrics->temperature_edge = metrics->TemperatureEdge;
 	gpu_metrics->temperature_hotspot = metrics->TemperatureHotspot;
 	gpu_metrics->current_dclk1 = metrics->CurrClock[PPCLK_DCLK_1];
 	gpu_metrics->throttle_status = metrics->ThrottlerStatus;
+	gpu_metrics->indep_throttle_status =
+			smu_cmn_get_indep_throttler_status(metrics->ThrottlerStatus,
+							   sienna_cichlid_throttler_map);
 	gpu_metrics->current_fan_speed = metrics->CurrFanSpeed;
 	*table = (void *)gpu_metrics;
-	return sizeof(struct gpu_metrics_v1_1);
+	return sizeof(struct gpu_metrics_v1_3);
 }
 static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
 	.baco_is_support = smu_v11_0_baco_is_support,
 	.baco_get_state = smu_v11_0_baco_get_state,
 	.baco_set_state = smu_v11_0_baco_set_state,
-	.baco_enter = smu_v11_0_baco_enter,
+	.baco_enter = sienna_cichlid_baco_enter,
-	.baco_exit = smu_v11_0_baco_exit,
+	.baco_exit = sienna_cichlid_baco_exit,
 	.mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported,
 	.mode1_reset = smu_v11_0_mode1_reset,
 	.get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c+2−9

 	return smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
 }
-static int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu, enum smu_v11_0_baco_seq baco_seq)
+int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu,
+				      enum smu_v11_0_baco_seq baco_seq)
 {
 	return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq, NULL);
 }
 int smu_v11_0_baco_enter(struct smu_context *smu)
 {
-	struct amdgpu_device *adev = smu->adev;
 	int ret = 0;
-	/* Arcturus does not need this audio workaround */
-	if (adev->asic_type != CHIP_ARCTURUS) {
-		ret = smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
-		if (ret)
-			return ret;
-	}
 	ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);
 	if (ret)
 		return ret;

drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c+39−12

 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,		WORKLOAD_PPLIB_CUSTOM_BIT),
 };
+static const uint8_t vangogh_throttler_map[] = {
+	[THROTTLER_STATUS_BIT_SPL]	= (SMU_THROTTLER_SPL_BIT),
+	[THROTTLER_STATUS_BIT_FPPT]	= (SMU_THROTTLER_FPPT_BIT),
+	[THROTTLER_STATUS_BIT_SPPT]	= (SMU_THROTTLER_SPPT_BIT),
+	[THROTTLER_STATUS_BIT_SPPT_APU]	= (SMU_THROTTLER_SPPT_APU_BIT),
+	[THROTTLER_STATUS_BIT_THM_CORE]	= (SMU_THROTTLER_TEMP_CORE_BIT),
+	[THROTTLER_STATUS_BIT_THM_GFX]	= (SMU_THROTTLER_TEMP_GPU_BIT),
+	[THROTTLER_STATUS_BIT_THM_SOC]	= (SMU_THROTTLER_TEMP_SOC_BIT),
+	[THROTTLER_STATUS_BIT_TDC_VDD]	= (SMU_THROTTLER_TDC_VDD_BIT),
+	[THROTTLER_STATUS_BIT_TDC_SOC]	= (SMU_THROTTLER_TDC_SOC_BIT),
+	[THROTTLER_STATUS_BIT_TDC_GFX]	= (SMU_THROTTLER_TDC_GFX_BIT),
+	[THROTTLER_STATUS_BIT_TDC_CVIP]	= (SMU_THROTTLER_TDC_CVIP_BIT),
+};
 static int vangogh_tables_init(struct smu_context *smu)
 {
 	struct smu_table_context *smu_table = &smu->smu_table;
 		goto err0_out;
 	smu_table->metrics_time = 0;
-	smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_1);
+	smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_2);
 	smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 	if (!smu_table->gpu_metrics_table)
 		goto err1_out;
 				      void **table)
 {
 	struct smu_table_context *smu_table = &smu->smu_table;
-	struct gpu_metrics_v2_1 *gpu_metrics =
+	struct gpu_metrics_v2_2 *gpu_metrics =
-		(struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table;
+		(struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table;
 	SmuMetrics_legacy_t metrics;
 	int ret = 0;
 	if (ret)
 		return ret;
-	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 1);
+	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2);
 	gpu_metrics->temperature_gfx = metrics.GfxTemperature;
 	gpu_metrics->temperature_soc = metrics.SocTemperature;
 	gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0];
 	gpu_metrics->throttle_status = metrics.ThrottlerStatus;
+	gpu_metrics->indep_throttle_status =
+			smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
+							   vangogh_throttler_map);
 	gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
 	*table = (void *)gpu_metrics;
-	return sizeof(struct gpu_metrics_v2_1);
+	return sizeof(struct gpu_metrics_v2_2);
 }
 static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu,
 				      void **table)
 {
 	struct smu_table_context *smu_table = &smu->smu_table;
-	struct gpu_metrics_v2_1 *gpu_metrics =
+	struct gpu_metrics_v2_2 *gpu_metrics =
-		(struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table;
+		(struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table;
 	SmuMetrics_t metrics;
 	int ret = 0;
 	if (ret)
 		return ret;
-	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 1);
+	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2);
 	gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature;
 	gpu_metrics->temperature_soc = metrics.Current.SocTemperature;
 	gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0];
 	gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus;
+	gpu_metrics->indep_throttle_status =
+			smu_cmn_get_indep_throttler_status(metrics.Current.ThrottlerStatus,
+							   vangogh_throttler_map);
 	gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
 	*table = (void *)gpu_metrics;
-	return sizeof(struct gpu_metrics_v2_1);
+	return sizeof(struct gpu_metrics_v2_2);
 }
 static ssize_t vangogh_common_get_gpu_metrics(struct smu_context *smu,
 	return vangogh_mode_reset(smu, SMU_RESET_MODE_2);
 }
-static int vangogh_get_power_limit(struct smu_context *smu)
+static int vangogh_get_power_limit(struct smu_context *smu,
+				   uint32_t *current_power_limit,
+				   uint32_t *default_power_limit,
+				   uint32_t *max_power_limit)
 {
 	struct smu_11_5_power_context *power_context =
 								smu->smu_power.power_context;
 		return ret;
 	}
 	/* convert from milliwatt to watt */
-	smu->current_power_limit = smu->default_power_limit = ppt_limit / 1000;
+	if (current_power_limit)
-	smu->max_power_limit = 29;
+		*current_power_limit = ppt_limit / 1000;
+	if (default_power_limit)
+		*default_power_limit = ppt_limit / 1000;
+	if (max_power_limit)
+		*max_power_limit = 29;
 	ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetFastPPTLimit, &ppt_limit);
 	if (ret) {

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c+58−5

 	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,		WORKLOAD_PPLIB_CUSTOM_BIT),
 };
+static const uint8_t renoir_throttler_map[] = {
+	[THROTTLER_STATUS_BIT_SPL]		= (SMU_THROTTLER_SPL_BIT),
+	[THROTTLER_STATUS_BIT_FPPT]		= (SMU_THROTTLER_FPPT_BIT),
+	[THROTTLER_STATUS_BIT_SPPT]		= (SMU_THROTTLER_SPPT_BIT),
+	[THROTTLER_STATUS_BIT_SPPT_APU]		= (SMU_THROTTLER_SPPT_APU_BIT),
+	[THROTTLER_STATUS_BIT_THM_CORE]		= (SMU_THROTTLER_TEMP_CORE_BIT),
+	[THROTTLER_STATUS_BIT_THM_GFX]		= (SMU_THROTTLER_TEMP_GPU_BIT),
+	[THROTTLER_STATUS_BIT_THM_SOC]		= (SMU_THROTTLER_TEMP_SOC_BIT),
+	[THROTTLER_STATUS_BIT_TDC_VDD]		= (SMU_THROTTLER_TDC_VDD_BIT),
+	[THROTTLER_STATUS_BIT_TDC_SOC]		= (SMU_THROTTLER_TDC_SOC_BIT),
+	[THROTTLER_STATUS_BIT_PROCHOT_CPU]	= (SMU_THROTTLER_PROCHOT_CPU_BIT),
+	[THROTTLER_STATUS_BIT_PROCHOT_GFX]	= (SMU_THROTTLER_PROCHOT_GFX_BIT),
+	[THROTTLER_STATUS_BIT_EDC_CPU]		= (SMU_THROTTLER_EDC_CPU_BIT),
+	[THROTTLER_STATUS_BIT_EDC_GFX]		= (SMU_THROTTLER_EDC_GFX_BIT),
+};
 static int renoir_init_smc_tables(struct smu_context *smu)
 {
 	struct smu_table_context *smu_table = &smu->smu_table;
 	if (!smu_table->watermarks_table)
 		goto err2_out;
-	smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_1);
+	smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_2);
 	smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 	if (!smu_table->gpu_metrics_table)
 		goto err3_out;
 	case METRICS_VOLTAGE_VDDSOC:
 		*value = metrics->Voltage[1];
 		break;
+	case METRICS_SS_APU_SHARE:
+		/* return the percentage of APU power with respect to APU's power limit.
+		 * percentage is reported, this isn't boost value. Smartshift power
+		 * boost/shift is only when the percentage is more than 100.
+		 */
+		if (metrics->StapmOriginalLimit > 0)
+			*value =  (metrics->ApuPower * 100) / metrics->StapmOriginalLimit;
+		else
+			*value = 0;
+		break;
+	case METRICS_SS_DGPU_SHARE:
+		/* return the percentage of dGPU power with respect to dGPU's power limit.
+		 * percentage is reported, this isn't boost value. Smartshift power
+		 * boost/shift is only when the percentage is more than 100.
+		 */
+		if ((metrics->dGpuPower > 0) &&
+		    (metrics->StapmCurrentLimit > metrics->StapmOriginalLimit))
+			*value = (metrics->dGpuPower * 100) /
+				  (metrics->StapmCurrentLimit - metrics->StapmOriginalLimit);
+		else
+			*value = 0;
+		break;
 	default:
 		*value = UINT_MAX;
 		break;
 						  (uint32_t *)data);
 		*size = 4;
 		break;
+	case AMDGPU_PP_SENSOR_SS_APU_SHARE:
+		ret = renoir_get_smu_metrics_data(smu,
+						  METRICS_SS_APU_SHARE,
+						  (uint32_t *)data);
+		*size = 4;
+		break;
+	case AMDGPU_PP_SENSOR_SS_DGPU_SHARE:
+		ret = renoir_get_smu_metrics_data(smu,
+						  METRICS_SS_DGPU_SHARE,
+						  (uint32_t *)data);
+		*size = 4;
+		break;
 	default:
 		ret = -EOPNOTSUPP;
 		break;
 				      void **table)
 {
 	struct smu_table_context *smu_table = &smu->smu_table;
-	struct gpu_metrics_v2_1 *gpu_metrics =
+	struct gpu_metrics_v2_2 *gpu_metrics =
-		(struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table;
+		(struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table;
 	SmuMetrics_t metrics;
 	int ret = 0;
 	if (ret)
 		return ret;
-	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 1);
+	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2);
 	gpu_metrics->temperature_gfx = metrics.GfxTemperature;
 	gpu_metrics->temperature_soc = metrics.SocTemperature;
 	gpu_metrics->current_l3clk[1] = metrics.L3Frequency[1];
 	gpu_metrics->throttle_status = metrics.ThrottlerStatus;
+	gpu_metrics->indep_throttle_status =
+		smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
+						   renoir_throttler_map);
 	gpu_metrics->fan_pwm = metrics.FanPwm;
 	*table = (void *)gpu_metrics;
-	return sizeof(struct gpu_metrics_v2_1);
+	return sizeof(struct gpu_metrics_v2_2);
 }
 static int renoir_gfx_state_change_set(struct smu_context *smu, uint32_t state)

drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c+81−20

 	TAB_MAP(I2C_COMMANDS),
 };
+static const uint8_t aldebaran_throttler_map[] = {
+	[THROTTLER_PPT0_BIT]		= (SMU_THROTTLER_PPT0_BIT),
+	[THROTTLER_PPT1_BIT]		= (SMU_THROTTLER_PPT1_BIT),
+	[THROTTLER_TDC_GFX_BIT]		= (SMU_THROTTLER_TDC_GFX_BIT),
+	[THROTTLER_TDC_SOC_BIT]		= (SMU_THROTTLER_TDC_SOC_BIT),
+	[THROTTLER_TDC_HBM_BIT]		= (SMU_THROTTLER_TDC_MEM_BIT),
+	[THROTTLER_TEMP_GPU_BIT]	= (SMU_THROTTLER_TEMP_GPU_BIT),
+	[THROTTLER_TEMP_MEM_BIT]	= (SMU_THROTTLER_TEMP_MEM_BIT),
+	[THROTTLER_TEMP_VR_GFX_BIT]	= (SMU_THROTTLER_TEMP_VR_GFX_BIT),
+	[THROTTLER_TEMP_VR_SOC_BIT]	= (SMU_THROTTLER_TEMP_VR_SOC_BIT),
+	[THROTTLER_TEMP_VR_MEM_BIT]	= (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
+	[THROTTLER_APCC_BIT]		= (SMU_THROTTLER_APCC_BIT),
+};
 static int aldebaran_tables_init(struct smu_context *smu)
 {
 	struct smu_table_context *smu_table = &smu->smu_table;
 		return -ENOMEM;
 	smu_table->metrics_time = 0;
-	smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_2);
+	smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
 	smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 	if (!smu_table->gpu_metrics_table) {
 		kfree(smu_table->metrics_table);
 	return (abs(frequency1 - frequency2) <= EPSILON);
 }
+static bool aldebaran_is_primary(struct smu_context *smu)
+{
+	struct amdgpu_device *adev = smu->adev;
+	if (adev->smuio.funcs && adev->smuio.funcs->get_die_id)
+		return adev->smuio.funcs->get_die_id(adev) == 0;
+	return true;
+}
 static int aldebaran_get_smu_metrics_data(struct smu_context *smu,
 					  MetricsMember_t member,
 					  uint32_t *value)
 		*value = metrics->AverageUclkActivity;
 		break;
 	case METRICS_AVERAGE_SOCKETPOWER:
-		*value = metrics->AverageSocketPower << 8;
+		/* Valid power data is available only from primary die */
+		*value = aldebaran_is_primary(smu) ?
+				 metrics->AverageSocketPower << 8 :
+				 0;
 		break;
 	case METRICS_TEMPERATURE_EDGE:
 		*value = metrics->TemperatureEdge *
 	return ret;
 }
-static int aldebaran_get_power_limit(struct smu_context *smu)
+static int aldebaran_get_power_limit(struct smu_context *smu,
+				     uint32_t *current_power_limit,
+				     uint32_t *default_power_limit,
+				     uint32_t *max_power_limit)
 {
 	PPTable_t *pptable = smu->smu_table.driver_pptable;
 	uint32_t power_limit = 0;
 	if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
 		return -EINVAL;
-	ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetPptLimit, &power_limit);
+	/* Valid power data is available only from primary die.
+	 * For secondary die show the value as 0.
+	 */
+	if (aldebaran_is_primary(smu)) {
+		ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetPptLimit,
+					   &power_limit);
-	if (ret) {
+		if (ret) {
-		/* the last hope to figure out the ppt limit */
+			/* the last hope to figure out the ppt limit */
-		if (!pptable) {
+			if (!pptable) {
-			dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!");
+				dev_err(smu->adev->dev,
-			return -EINVAL;
+					"Cannot get PPT limit due to pptable missing!");
+				return -EINVAL;
+			}
+			power_limit = pptable->PptLimit;
 		}
-		power_limit = pptable->PptLimit;
 	}
-	smu->current_power_limit = smu->default_power_limit = power_limit;
+	if (current_power_limit)
-	if (pptable)
+		*current_power_limit = power_limit;
-		smu->max_power_limit = pptable->PptLimit;
+	if (default_power_limit)
+		*default_power_limit = power_limit;
+	if (max_power_limit) {
+		if (pptable)
+			*max_power_limit = pptable->PptLimit;
+	}
 	return 0;
 }
+static int aldebaran_set_power_limit(struct smu_context *smu, uint32_t n)
+{
+	/* Power limit can be set only through primary die */
+	if (aldebaran_is_primary(smu))
+		return smu_v13_0_set_power_limit(smu, n);
+	return -EINVAL;
+}
 static int aldebaran_system_features_control(struct  smu_context *smu, bool enable)
 {
 	int ret;
 					 void **table)
 {
 	struct smu_table_context *smu_table = &smu->smu_table;
-	struct gpu_metrics_v1_2 *gpu_metrics =
+	struct gpu_metrics_v1_3 *gpu_metrics =
-		(struct gpu_metrics_v1_2 *)smu_table->gpu_metrics_table;
+		(struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
 	SmuMetrics_t metrics;
 	int i, ret = 0;
 	if (ret)
 		return ret;
-	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 2);
+	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
 	gpu_metrics->temperature_edge = metrics.TemperatureEdge;
 	gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
 	gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
 	gpu_metrics->average_mm_activity = 0;
-	gpu_metrics->average_socket_power = metrics.AverageSocketPower;
+	/* Valid power data is available only from primary die */
-	gpu_metrics->energy_accumulator =
+	if (aldebaran_is_primary(smu)) {
+		gpu_metrics->average_socket_power = metrics.AverageSocketPower;
+		gpu_metrics->energy_accumulator =
 			(uint64_t)metrics.EnergyAcc64bitHigh << 32 |
 			metrics.EnergyAcc64bitLow;
+	} else {
+		gpu_metrics->average_socket_power = 0;
+		gpu_metrics->energy_accumulator = 0;
+	}
 	gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
 	gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
 	gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
 	gpu_metrics->throttle_status = metrics.ThrottlerStatus;
+	gpu_metrics->indep_throttle_status =
+			smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
+							   aldebaran_throttler_map);
 	gpu_metrics->current_fan_speed = 0;
 	*table = (void *)gpu_metrics;
-	return sizeof(struct gpu_metrics_v1_2);
+	return sizeof(struct gpu_metrics_v1_3);
 }
 static int aldebaran_mode2_reset(struct smu_context *smu)
 	.get_enabled_mask = smu_cmn_get_enabled_mask,
 	.feature_is_enabled = smu_cmn_feature_is_enabled,
 	.disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
-	.set_power_limit = smu_v13_0_set_power_limit,
+	.set_power_limit = aldebaran_set_power_limit,
 	.init_max_sustainable_clocks = smu_v13_0_init_max_sustainable_clocks,
 	.enable_thermal_alert = smu_v13_0_enable_thermal_alert,
 	.disable_thermal_alert = smu_v13_0_disable_thermal_alert,

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c+34−0

@@ -356,6 +356,28 @@ static int yellow_carp_get_smu_metrics_data(struct smu_context *smu, · 355 unmodified lines
356	case METRICS_VOLTAGE_VDDSOC:	356	case METRICS_VOLTAGE_VDDSOC:
357	*value = metrics->Voltage[1];	357	*value = metrics->Voltage[1];
358	break;	358	break;
		359	case METRICS_SS_APU_SHARE:
		360	/* return the percentage of APU power with respect to APU's power limit.
		361	* percentage is reported, this isn't boost value. Smartshift power
		362	* boost/shift is only when the percentage is more than 100.
		363	*/
		364	if (metrics->StapmOpnLimit > 0)
		365	value = (metrics->ApuPower 100) / metrics->StapmOpnLimit;
		366	else
		367	*value = 0;
		368	break;
		369	case METRICS_SS_DGPU_SHARE:
		370	/* return the percentage of dGPU power with respect to dGPU's power limit.
		371	* percentage is reported, this isn't boost value. Smartshift power
		372	* boost/shift is only when the percentage is more than 100.
		373	*/
		374	if ((metrics->dGpuPower > 0) &&
		375	(metrics->StapmCurrentLimit > metrics->StapmOpnLimit))
		376	value = (metrics->dGpuPower 100) /
		377	(metrics->StapmCurrentLimit - metrics->StapmOpnLimit);
		378	else
		379	*value = 0;
		380	break;
359	default:	381	default:
360	*value = UINT_MAX;	382	*value = UINT_MAX;
361	break;	383	break;
@@ -427,6 +449,18 @@ static int yellow_carp_read_sensor(struct smu_context *smu, · 65 unmodified lines
427	(uint32_t *)data);	449	(uint32_t *)data);
428	*size = 4;	450	*size = 4;
429	break;	451	break;
		452	case AMDGPU_PP_SENSOR_SS_APU_SHARE:
		453	ret = yellow_carp_get_smu_metrics_data(smu,
		454	METRICS_SS_APU_SHARE,
		455	(uint32_t *)data);
		456	*size = 4;
		457	break;
		458	case AMDGPU_PP_SENSOR_SS_DGPU_SHARE:
		459	ret = yellow_carp_get_smu_metrics_data(smu,
		460	METRICS_SS_DGPU_SHARE,
		461	(uint32_t *)data);
		462	*size = 4;
		463	break;
430	default:	464	default:
431	ret = -EOPNOTSUPP;	465	ret = -EOPNOTSUPP;
432	break;	466	break;

drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c+54−9

@@ -398,6 +398,19 @@ int smu_cmn_get_enabled_32_bits_mask(struct smu_context *smu, · 397 unmodified lines
398		398
399	}	399	}
400		400
		401	uint64_t smu_cmn_get_indep_throttler_status(
		402	const unsigned long dep_status,
		403	const uint8_t *throttler_map)
		404	{
		405	uint64_t indep_status = 0;
		406	uint8_t dep_bit = 0;
		407
		408	for_each_set_bit(dep_bit, &dep_status, 32)
		409	indep_status \|= 1ULL << throttler_map[dep_bit];
		410
		411	return indep_status;
		412	}
		413
401	int smu_cmn_feature_update_enable_state(struct smu_context *smu,	414	int smu_cmn_feature_update_enable_state(struct smu_context *smu,
402	uint64_t feature_mask,	415	uint64_t feature_mask,
403	bool enabled)	416	bool enabled)
@@ -575,23 +588,52 @@ int smu_cmn_set_pp_feature_mask(struct smu_context *smu, · 171 unmodified lines
575	return ret;	588	return ret;
576	}	589	}
577		590
		591	/**
		592	* smu_cmn_disable_all_features_with_exception - disable all dpm features
		593	* except this specified by
		594	* @mask
		595	*
		596	* @smu: smu_context pointer
		597	* @no_hw_disablement: whether real dpm disablement should be performed
		598	* true: update the cache(about dpm enablement state) only
		599	* false: real dpm disablement plus cache update
		600	* @mask: the dpm feature which should not be disabled
		601	* SMU_FEATURE_COUNT: no exception, all dpm features
		602	* to disable
		603	*
		604	* Returns:
		605	* 0 on success or a negative error code on failure.
		606	*/
578	int smu_cmn_disable_all_features_with_exception(struct smu_context *smu,	607	int smu_cmn_disable_all_features_with_exception(struct smu_context *smu,
		608	bool no_hw_disablement,
579	enum smu_feature_mask mask)	609	enum smu_feature_mask mask)
580	{	610	{
		611	struct smu_feature *feature = &smu->smu_feature;
581	uint64_t features_to_disable = U64_MAX;	612	uint64_t features_to_disable = U64_MAX;
582	int skipped_feature_id;	613	int skipped_feature_id;
583		614
584	skipped_feature_id = smu_cmn_to_asic_specific_index(smu,	615	if (mask != SMU_FEATURE_COUNT) {
585	CMN2ASIC_MAPPING_FEATURE,	616	skipped_feature_id = smu_cmn_to_asic_specific_index(smu,
586	mask);	617	CMN2ASIC_MAPPING_FEATURE,
587	if (skipped_feature_id < 0)	618	mask);
588	return -EINVAL;	619	if (skipped_feature_id < 0)
		620	return -EINVAL;
589		621
590	features_to_disable &= ~(1ULL << skipped_feature_id);	622	features_to_disable &= ~(1ULL << skipped_feature_id);
		623	}
591		624
592	return smu_cmn_feature_update_enable_state(smu,	625	if (no_hw_disablement) {
593	features_to_disable,	626	mutex_lock(&feature->mutex);
594	0);	627	bitmap_andnot(feature->enabled, feature->enabled,
		628	(unsigned long *)(&features_to_disable), SMU_FEATURE_MAX);
		629	mutex_unlock(&feature->mutex);
		630
		631	return 0;
		632	} else {
		633	return smu_cmn_feature_update_enable_state(smu,
		634	features_to_disable,
		635	0);
		636	}
595	}	637	}
596		638
597	int smu_cmn_get_smc_version(struct smu_context *smu,	639	int smu_cmn_get_smc_version(struct smu_context *smu,
@@ -773,6 +815,9 @@ void smu_cmn_init_soft_gpu_metrics(void *table, uint8_t frev, uint8_t crev) · 175 unmodified lines
773	case METRICS_VERSION(2, 1):	815	case METRICS_VERSION(2, 1):
774	structure_size = sizeof(struct gpu_metrics_v2_1);	816	structure_size = sizeof(struct gpu_metrics_v2_1);
775	break;	817	break;
		818	case METRICS_VERSION(2, 2):
		819	structure_size = sizeof(struct gpu_metrics_v2_2);
		820	break;
776	default:	821	default:
777	return;	822	return;
778	}	823	}

drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h+5−0

 					uint32_t *feature_mask,
 					uint32_t num);
+uint64_t smu_cmn_get_indep_throttler_status(
+					const unsigned long dep_status,
+					const uint8_t *throttler_map);
 int smu_cmn_feature_update_enable_state(struct smu_context *smu,
 					uint64_t feature_mask,
 					bool enabled);
 				uint64_t new_mask);
 int smu_cmn_disable_all_features_with_exception(struct smu_context *smu,
+						bool no_hw_disablement,
 						enum smu_feature_mask mask);
 int smu_cmn_get_smc_version(struct smu_context *smu,

drivers/gpu/drm/amd/pm/swsmu/smu_internal.h+2−2

include/drm/drm_dp_helper.h+17−0

@@ -1377,10 +1377,27 @@ enum drm_dp_phy { · 1376 unmodified lines
1377	#define DP_SYMBOL_ERROR_COUNT_LANE1_PHY_REPEATER1 0xf0037 /* 1.3 */	1377	#define DP_SYMBOL_ERROR_COUNT_LANE1_PHY_REPEATER1 0xf0037 /* 1.3 */
1378	#define DP_SYMBOL_ERROR_COUNT_LANE2_PHY_REPEATER1 0xf0039 /* 1.3 */	1378	#define DP_SYMBOL_ERROR_COUNT_LANE2_PHY_REPEATER1 0xf0039 /* 1.3 */
1379	#define DP_SYMBOL_ERROR_COUNT_LANE3_PHY_REPEATER1 0xf003b /* 1.3 */	1379	#define DP_SYMBOL_ERROR_COUNT_LANE3_PHY_REPEATER1 0xf003b /* 1.3 */
		1380
		1381	#define __DP_FEC1_BASE 0xf0290 /* 1.4 */
		1382	#define __DP_FEC2_BASE 0xf0298 /* 1.4 */
		1383	#define DP_FEC_BASE(dp_phy) \
		1384	(__DP_FEC1_BASE + ((__DP_FEC2_BASE - __DP_FEC1_BASE) * \
		1385	((dp_phy) - DP_PHY_LTTPR1)))
		1386
		1387	#define DP_FEC_REG(dp_phy, fec1_reg) \
		1388	(DP_FEC_BASE(dp_phy) - DP_FEC_BASE(DP_PHY_LTTPR1) + fec1_reg)
		1389
1380	#define DP_FEC_STATUS_PHY_REPEATER1 0xf0290 /* 1.4 */	1390	#define DP_FEC_STATUS_PHY_REPEATER1 0xf0290 /* 1.4 */
		1391	#define DP_FEC_STATUS_PHY_REPEATER(dp_phy) \
		1392	DP_FEC_REG(dp_phy, DP_FEC_STATUS_PHY_REPEATER1)
		1393
1381	#define DP_FEC_ERROR_COUNT_PHY_REPEATER1 0xf0291 /* 1.4 */	1394	#define DP_FEC_ERROR_COUNT_PHY_REPEATER1 0xf0291 /* 1.4 */
1382	#define DP_FEC_CAPABILITY_PHY_REPEATER1 0xf0294 /* 1.4a */	1395	#define DP_FEC_CAPABILITY_PHY_REPEATER1 0xf0294 /* 1.4a */
1383		1396
		1397	#define DP_LTTPR_MAX_ADD 0xf02ff /* 1.4 */
		1398
		1399	#define DP_DPCD_MAX_ADD 0xfffff /* 1.4 */
		1400
1384	/* Repeater modes */	1401	/* Repeater modes */
1385	#define DP_PHY_REPEATER_MODE_TRANSPARENT 0x55 /* 1.3 */	1402	#define DP_PHY_REPEATER_MODE_TRANSPARENT 0x55 /* 1.3 */
1386	#define DP_PHY_REPEATER_MODE_NON_TRANSPARENT 0xaa /* 1.3 */	1403	#define DP_PHY_REPEATER_MODE_NON_TRANSPARENT 0xaa /* 1.3 */

@@ -57,7 +57,7 @@ · 56 unmodified lines
57	#define smu_feature_set_allowed_mask(smu) smu_ppt_funcs(set_allowed_mask, 0, smu)	57	#define smu_feature_set_allowed_mask(smu) smu_ppt_funcs(set_allowed_mask, 0, smu)
58	#define smu_feature_get_enabled_mask(smu, mask, num) smu_ppt_funcs(get_enabled_mask, 0, smu, mask, num)	58	#define smu_feature_get_enabled_mask(smu, mask, num) smu_ppt_funcs(get_enabled_mask, 0, smu, mask, num)
59	#define smu_feature_is_enabled(smu, mask) smu_ppt_funcs(feature_is_enabled, 0, smu, mask)	59	#define smu_feature_is_enabled(smu, mask) smu_ppt_funcs(feature_is_enabled, 0, smu, mask)
60	#define smu_disable_all_features_with_exception(smu, mask) smu_ppt_funcs(disable_all_features_with_exception, 0, smu, mask)	60	#define smu_disable_all_features_with_exception(smu, no_hw_disablement, mask) smu_ppt_funcs(disable_all_features_with_exception, 0, smu, no_hw_disablement, mask)
61	#define smu_is_dpm_running(smu) smu_ppt_funcs(is_dpm_running, 0 , smu)	61	#define smu_is_dpm_running(smu) smu_ppt_funcs(is_dpm_running, 0 , smu)
62	#define smu_notify_display_change(smu) smu_ppt_funcs(notify_display_change, 0, smu)	62	#define smu_notify_display_change(smu) smu_ppt_funcs(notify_display_change, 0, smu)
63	#define smu_populate_umd_state_clk(smu) smu_ppt_funcs(populate_umd_state_clk, 0, smu)	63	#define smu_populate_umd_state_clk(smu) smu_ppt_funcs(populate_umd_state_clk, 0, smu)
@@ -82,7 +82,7 @@ · 18 unmodified lines
82	#define smu_i2c_fini(smu, control) smu_ppt_funcs(i2c_fini, 0, smu, control)	82	#define smu_i2c_fini(smu, control) smu_ppt_funcs(i2c_fini, 0, smu, control)
83	#define smu_get_unique_id(smu) smu_ppt_funcs(get_unique_id, 0, smu)	83	#define smu_get_unique_id(smu) smu_ppt_funcs(get_unique_id, 0, smu)
84	#define smu_log_thermal_throttling(smu) smu_ppt_funcs(log_thermal_throttling_event, 0, smu)	84	#define smu_log_thermal_throttling(smu) smu_ppt_funcs(log_thermal_throttling_event, 0, smu)
85	#define smu_get_asic_power_limits(smu) smu_ppt_funcs(get_power_limit, 0, smu)	85	#define smu_get_asic_power_limits(smu, current, default, max) smu_ppt_funcs(get_power_limit, 0, smu, current, default, max)
86	#define smu_get_pp_feature_mask(smu, buf) smu_ppt_funcs(get_pp_feature_mask, 0, smu, buf)	86	#define smu_get_pp_feature_mask(smu, buf) smu_ppt_funcs(get_pp_feature_mask, 0, smu, buf)
87	#define smu_set_pp_feature_mask(smu, new_mask) smu_ppt_funcs(set_pp_feature_mask, 0, smu, new_mask)	87	#define smu_set_pp_feature_mask(smu, new_mask) smu_ppt_funcs(set_pp_feature_mask, 0, smu, new_mask)
88	#define smu_gfx_ulv_control(smu, enablement) smu_ppt_funcs(gfx_ulv_control, 0, smu, enablement)	88	#define smu_gfx_ulv_control(smu, enablement) smu_ppt_funcs(gfx_ulv_control, 0, smu, enablement)