History

Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull arm64 fixes from Will Deacon: "These are almost exclusively related to CPU errata in CPUs from Broadcom and Qualcomm where the workarounds were either not being enabled when they should have been or enabled when they shouldn't have been. The only "interesting" fix is ensuring that writeable, shared mappings are initially mapped as clean since we inadvertently broke the logic back in v4.14 and then noticed the problem via code inspection the other day. The only critical issue we have outstanding is a sporadic NULL dereference in the scheduler, which doesn't appear to be arm64-specific and PeterZ is tearing his hair out over it at the moment. Summary: - Enable CPU errata workarounds for Broadcom Brahma-B53 - Enable CPU errata workarounds for Qualcomm Hydra/Kryo CPUs - Fix initial dirty status of writeable, shared mappings" * tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: arm64: apply ARM64_ERRATUM_843419 workaround for Brahma-B53 core arm64: Brahma-B53 is SSB and spectre v2 safe arm64: apply ARM64_ERRATUM_845719 workaround for Brahma-B53 core arm64: cpufeature: Enable Qualcomm Falkor errata 1009 for Kryo arm64: cpufeature: Enable Qualcomm Falkor/Kryo errata 1003 arm64: Ensure VM_WRITE|VM_SHARED ptes are clean by default

Linus Torvalds committed 7 years ago

Commit d540c392 parents b88866b 1cf45b84 files · +64 −19Browse files

Unified · Split

4 files
  1. Documentation/arm64/silicon-errata.rst +6 −1
  2. arch/arm64/include/asm/cputype.h +2 −0
  3. arch/arm64/include/asm/pgtable-prot.h +8 −7
  4. arch/arm64/kernel/cpu_errata.c +48 −11
Documentation/arm64/silicon-errata.rst+6−1
@@ -91,6 +91,11 @@ stable kernels. · 90 unmodified lines
9191 | ARM | MMU-500 | #841119,826419 | N/A |
9292 +----------------+-----------------+-----------------+-----------------------------+
9393 +----------------+-----------------+-----------------+-----------------------------+
94+| Broadcom | Brahma-B53 | N/A | ARM64_ERRATUM_845719 |
95++----------------+-----------------+-----------------+-----------------------------+
96+| Broadcom | Brahma-B53 | N/A | ARM64_ERRATUM_843419 |
97++----------------+-----------------+-----------------+-----------------------------+
98++----------------+-----------------+-----------------+-----------------------------+
9499 | Cavium | ThunderX ITS | #22375,24313 | CAVIUM_ERRATUM_22375 |
95100 +----------------+-----------------+-----------------+-----------------------------+
96101 | Cavium | ThunderX ITS | #23144 | CAVIUM_ERRATUM_23144 |
@@ -126,7 +131,7 @@ stable kernels. · 29 unmodified lines
126131 +----------------+-----------------+-----------------+-----------------------------+
127132 | Qualcomm Tech. | Kryo/Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 |
128133 +----------------+-----------------+-----------------+-----------------------------+
129−| Qualcomm Tech. | Falkor v1 | E1009 | QCOM_FALKOR_ERRATUM_1009 |
134+| Qualcomm Tech. | Kryo/Falkor v1 | E1009 | QCOM_FALKOR_ERRATUM_1009 |
130135 +----------------+-----------------+-----------------+-----------------------------+
131136 | Qualcomm Tech. | QDF2400 ITS | E0065 | QCOM_QDF2400_ERRATUM_0065 |
132137 +----------------+-----------------+-----------------+-----------------------------+
arch/arm64/include/asm/cputype.h+2−0
@@ -79,6 +79,7 @@ · 78 unmodified lines
7979 #define CAVIUM_CPU_PART_THUNDERX_83XX 0x0A3
8080 #define CAVIUM_CPU_PART_THUNDERX2 0x0AF
8181
82+#define BRCM_CPU_PART_BRAHMA_B53 0x100
8283 #define BRCM_CPU_PART_VULCAN 0x516
8384
8485 #define QCOM_CPU_PART_FALKOR_V1 0x800
@@ -105,6 +106,7 @@ · 20 unmodified lines
105106 #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
106107 #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
107108 #define MIDR_CAVIUM_THUNDERX2 MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX2)
109+#define MIDR_BRAHMA_B53 MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_BRAHMA_B53)
108110 #define MIDR_BRCM_VULCAN MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_VULCAN)
109111 #define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1)
110112 #define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR)
arch/arm64/include/asm/pgtable-prot.h+8−7
@@ -32,11 +32,11 @@ · 31 unmodified lines
3232 #define PROT_DEFAULT (_PROT_DEFAULT | PTE_MAYBE_NG)
3333 #define PROT_SECT_DEFAULT (_PROT_SECT_DEFAULT | PMD_MAYBE_NG)
3434
35−#define PROT_DEVICE_nGnRnE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRnE))
36−#define PROT_DEVICE_nGnRE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRE))
37−#define PROT_NORMAL_NC (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_NC))
38−#define PROT_NORMAL_WT (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_WT))
39−#define PROT_NORMAL (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL))
35+#define PROT_DEVICE_nGnRnE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRnE))
36+#define PROT_DEVICE_nGnRE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRE))
37+#define PROT_NORMAL_NC (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_NC))
38+#define PROT_NORMAL_WT (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_WT))
39+#define PROT_NORMAL (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL))
4040
4141 #define PROT_SECT_DEVICE_nGnRE (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
4242 #define PROT_SECT_NORMAL (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
@@ -80,8 +80,9 @@ · 37 unmodified lines
8080 #define PAGE_S2_DEVICE __pgprot(_PROT_DEFAULT | PAGE_S2_MEMATTR(DEVICE_nGnRE) | PTE_S2_RDONLY | PTE_S2_XN)
8181
8282 #define PAGE_NONE __pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PROT_NONE | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN)
83−#define PAGE_SHARED __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE)
84−#define PAGE_SHARED_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_WRITE)
83+/* shared+writable pages are clean by default, hence PTE_RDONLY|PTE_WRITE */
84+#define PAGE_SHARED __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE)
85+#define PAGE_SHARED_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_WRITE)
8586 #define PAGE_READONLY __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN)
8687 #define PAGE_READONLY_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN)
8788 #define PAGE_EXECONLY __pgprot(_PAGE_DEFAULT | PTE_RDONLY | PTE_NG | PTE_PXN)
arch/arm64/kernel/cpu_errata.c+48−11
@@ -489,6 +489,7 @@ static const struct midr_range arm64_ssb_cpus[] = { · 488 unmodified lines
489489 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
490490 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
491491 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
492+ MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
492493 {},
493494 };
494495
@@ -573,6 +574,7 @@ static const struct midr_range spectre_v2_safe_list[] = { · 78 unmodified lines
573574 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
574575 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
575576 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
577+ MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
576578 { /* sentinel */ }
577579 };
578580
@@ -659,17 +661,23 @@ static const struct midr_range arm64_harden_el2_vectors[] = { · 80 unmodified lines
659661 #endif
660662
661663 #ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
662−
663−static const struct midr_range arm64_repeat_tlbi_cpus[] = {
664+static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = {
664665 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009
665− MIDR_RANGE(MIDR_QCOM_FALKOR_V1, 0, 0, 0, 0),
666+ {
667+ ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0)
668+ },
669+ {
670+ .midr_range.model = MIDR_QCOM_KRYO,
671+ .matches = is_kryo_midr,
672+ },
666673 #endif
667674 #ifdef CONFIG_ARM64_ERRATUM_1286807
668− MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0),
675+ {
676+ ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0),
677+ },
669678 #endif
670679 {},
671680 };
672−
673681 #endif
674682
675683 #ifdef CONFIG_CAVIUM_ERRATUM_27456
@@ -737,6 +745,33 @@ static const struct midr_range erratum_1418040_list[] = { · 61 unmodified lines
737745 };
738746 #endif
739747
748+#ifdef CONFIG_ARM64_ERRATUM_845719
749+static const struct midr_range erratum_845719_list[] = {
750+ /* Cortex-A53 r0p[01234] */
751+ MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
752+ /* Brahma-B53 r0p[0] */
753+ MIDR_REV(MIDR_BRAHMA_B53, 0, 0),
754+ {},
755+};
756+#endif
757+
758+#ifdef CONFIG_ARM64_ERRATUM_843419
759+static const struct arm64_cpu_capabilities erratum_843419_list[] = {
760+ {
761+ /* Cortex-A53 r0p[01234] */
762+ .matches = is_affected_midr_range,
763+ ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
764+ MIDR_FIXED(0x4, BIT(8)),
765+ },
766+ {
767+ /* Brahma-B53 r0p[0] */
768+ .matches = is_affected_midr_range,
769+ ERRATA_MIDR_REV(MIDR_BRAHMA_B53, 0, 0),
770+ },
771+ {},
772+};
773+#endif
774+
740775 const struct arm64_cpu_capabilities arm64_errata[] = {
741776 #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
742777 {
@@ -768,19 +803,18 @@ const struct arm64_cpu_capabilities arm64_errata[] = { · 25 unmodified lines
768803 #endif
769804 #ifdef CONFIG_ARM64_ERRATUM_843419
770805 {
771− /* Cortex-A53 r0p[01234] */
772806 .desc = "ARM erratum 843419",
773807 .capability = ARM64_WORKAROUND_843419,
774− ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
775− MIDR_FIXED(0x4, BIT(8)),
808+ .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
809+ .matches = cpucap_multi_entry_cap_matches,
810+ .match_list = erratum_843419_list,
776811 },
777812 #endif
778813 #ifdef CONFIG_ARM64_ERRATUM_845719
779814 {
780− /* Cortex-A53 r0p[01234] */
781815 .desc = "ARM erratum 845719",
782816 .capability = ARM64_WORKAROUND_845719,
783− ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
817+ ERRATA_MIDR_RANGE_LIST(erratum_845719_list),
784818 },
785819 #endif
786820 #ifdef CONFIG_CAVIUM_ERRATUM_23154
@@ -816,6 +850,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = { · 29 unmodified lines
816850 {
817851 .desc = "Qualcomm Technologies Falkor/Kryo erratum 1003",
818852 .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
853+ .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
819854 .matches = cpucap_multi_entry_cap_matches,
820855 .match_list = qcom_erratum_1003_list,
821856 },
@@ -824,7 +859,9 @@ const struct arm64_cpu_capabilities arm64_errata[] = { · 2 unmodified lines
824859 {
825860 .desc = "Qualcomm erratum 1009, ARM erratum 1286807",
826861 .capability = ARM64_WORKAROUND_REPEAT_TLBI,
827− ERRATA_MIDR_RANGE_LIST(arm64_repeat_tlbi_cpus),
862+ .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
863+ .matches = cpucap_multi_entry_cap_matches,
864+ .match_list = arm64_repeat_tlbi_list,
828865 },
829866 #endif
830867 #ifdef CONFIG_ARM64_ERRATUM_858921

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