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drm/i915/uapi: expose GTT alignment

On some platforms we potentially have different alignment restrictions depending on the memory type. We also now have different alignment restrictions for the same region across different kernel versions. Extend the region query to return the minimum required GTT alignment.

Matthew Auld committed 4 years ago

Commit d54576a1 parent 8133a6d2 files · +28 −2Browse files

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include/uapi/drm/i915_drm.h+27−2
@@ -3346,8 +3346,33 @@ struct drm_i915_memory_region_info { · 3345 unmodified lines
33463346 /** @region: The class:instance pair encoding */
33473347 struct drm_i915_gem_memory_class_instance region;
33483348
3349− /** @rsvd0: MBZ */
3350− __u32 rsvd0;
3349+ union {
3350+ /** @rsvd0: MBZ */
3351+ __u32 rsvd0;
3352+ /**
3353+ * @gtt_alignment:
3354+ *
3355+ * The minimum required GTT alignment for this type of memory.
3356+ * When allocating a GTT address it must be aligned to this
3357+ * value or larger. On some platforms the kernel might opt to
3358+ * using 64K pages for I915_MEMORY_CLASS_DEVICE, where 64K GTT
3359+ * pages can then be used if we also use 64K GTT alignment.
3360+ *
3361+ * NOTE: If this is zero then this must be an older
3362+ * kernel which lacks support for this field.
3363+ *
3364+ * Side note: For larger objects (especially for
3365+ * I915_MEMORY_CLASS_DEVICE), like 2M+ in size, userspace should
3366+ * consider potentially bumping the GTT alignment to say 2M,
3367+ * which could potentially increase the likelihood of the kernel
3368+ * being able to utilise 2M GTT pages underneath, if the layout
3369+ * of the physical pages allows it. On some configurations we
3370+ * can then also use a more efficient page-table layout, if we
3371+ * can't use the more desirable 2M GTT page, so long as we know
3372+ * that the entire page-table will be used by this object.
3373+ */
3374+ __u32 gtt_alignment;
3375+ };
33513376
33523377 /**
33533378 * @probed_size: Memory probed by the driver