We need to backmerge drm-next to fix the komeda build failure.
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| @@ -523,6 +523,7 @@ struct drm_amdgpu_gem_va { · 522 unmodified lines | |||
| 523 | #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 | 523 | #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 |
| 524 | #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 | 524 | #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 |
| 525 | #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06 | 525 | #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06 |
| 526 | #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07 | ||
| 526 | 527 | ||
| 527 | struct drm_amdgpu_cs_chunk { | 528 | struct drm_amdgpu_cs_chunk { |
| 528 | __u32 chunk_id; | 529 | __u32 chunk_id; |
| @@ -565,6 +566,11 @@ union drm_amdgpu_cs { · 36 unmodified lines | |||
| 565 | * caches (L2/vL1/sL1/I$). */ | 566 | * caches (L2/vL1/sL1/I$). */ |
| 566 | #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3) | 567 | #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3) |
| 567 | 568 | ||
| 569 | /* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER. | ||
| 570 | * This will reset wave ID counters for the IB. | ||
| 571 | */ | ||
| 572 | #define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4) | ||
| 573 | |||
| 568 | struct drm_amdgpu_cs_chunk_ib { | 574 | struct drm_amdgpu_cs_chunk_ib { |
| 569 | __u32 _pad; | 575 | __u32 _pad; |
| 570 | /** AMDGPU_IB_FLAG_* */ | 576 | /** AMDGPU_IB_FLAG_* */ |
| @@ -595,6 +595,9 @@ extern "C" { · 594 unmodified lines | |||
| 595 | * AFBC has several features which may be supported and/or used, which are | 595 | * AFBC has several features which may be supported and/or used, which are |
| 596 | * represented using bits in the modifier. Not all combinations are valid, | 596 | * represented using bits in the modifier. Not all combinations are valid, |
| 597 | * and different devices or use-cases may support different combinations. | 597 | * and different devices or use-cases may support different combinations. |
| 598 | * | ||
| 599 | * Further information on the use of AFBC modifiers can be found in | ||
| 600 | * Documentation/gpu/afbc.rst | ||
| 598 | */ | 601 | */ |
| 599 | #define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) fourcc_mod_code(ARM, __afbc_mode) | 602 | #define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) fourcc_mod_code(ARM, __afbc_mode) |
| 600 | 603 | ||
| @@ -1486,9 +1486,73 @@ struct drm_i915_gem_context_param { · 1485 unmodified lines | |||
| 1486 | #define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */ | 1486 | #define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */ |
| 1487 | #define I915_CONTEXT_DEFAULT_PRIORITY 0 | 1487 | #define I915_CONTEXT_DEFAULT_PRIORITY 0 |
| 1488 | #define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */ | 1488 | #define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */ |
| 1489 | /* | ||
| 1490 | * When using the following param, value should be a pointer to | ||
| 1491 | * drm_i915_gem_context_param_sseu. | ||
| 1492 | */ | ||
| 1493 | #define I915_CONTEXT_PARAM_SSEU 0x7 | ||
| 1489 | __u64 value; | 1494 | __u64 value; |
| 1490 | }; | 1495 | }; |
| 1491 | 1496 | ||
| 1497 | /** | ||
| 1498 | * Context SSEU programming | ||
| 1499 | * | ||
| 1500 | * It may be necessary for either functional or performance reason to configure | ||
| 1501 | * a context to run with a reduced number of SSEU (where SSEU stands for Slice/ | ||
| 1502 | * Sub-slice/EU). | ||
| 1503 | * | ||
| 1504 | * This is done by configuring SSEU configuration using the below | ||
| 1505 | * @struct drm_i915_gem_context_param_sseu for every supported engine which | ||
| 1506 | * userspace intends to use. | ||
| 1507 | * | ||
| 1508 | * Not all GPUs or engines support this functionality in which case an error | ||
| 1509 | * code -ENODEV will be returned. | ||
| 1510 | * | ||
| 1511 | * Also, flexibility of possible SSEU configuration permutations varies between | ||
| 1512 | * GPU generations and software imposed limitations. Requesting such a | ||
| 1513 | * combination will return an error code of -EINVAL. | ||
| 1514 | * | ||
| 1515 | * NOTE: When perf/OA is active the context's SSEU configuration is ignored in | ||
| 1516 | * favour of a single global setting. | ||
| 1517 | */ | ||
| 1518 | struct drm_i915_gem_context_param_sseu { | ||
| 1519 | /* | ||
| 1520 | * Engine class & instance to be configured or queried. | ||
| 1521 | */ | ||
| 1522 | __u16 engine_class; | ||
| 1523 | __u16 engine_instance; | ||
| 1524 | |||
| 1525 | /* | ||
| 1526 | * Unused for now. Must be cleared to zero. | ||
| 1527 | */ | ||
| 1528 | __u32 flags; | ||
| 1529 | |||
| 1530 | /* | ||
| 1531 | * Mask of slices to enable for the context. Valid values are a subset | ||
| 1532 | * of the bitmask value returned for I915_PARAM_SLICE_MASK. | ||
| 1533 | */ | ||
| 1534 | __u64 slice_mask; | ||
| 1535 | |||
| 1536 | /* | ||
| 1537 | * Mask of subslices to enable for the context. Valid values are a | ||
| 1538 | * subset of the bitmask value return by I915_PARAM_SUBSLICE_MASK. | ||
| 1539 | */ | ||
| 1540 | __u64 subslice_mask; | ||
| 1541 | |||
| 1542 | /* | ||
| 1543 | * Minimum/Maximum number of EUs to enable per subslice for the | ||
| 1544 | * context. min_eus_per_subslice must be inferior or equal to | ||
| 1545 | * max_eus_per_subslice. | ||
| 1546 | */ | ||
| 1547 | __u16 min_eus_per_subslice; | ||
| 1548 | __u16 max_eus_per_subslice; | ||
| 1549 | |||
| 1550 | /* | ||
| 1551 | * Unused for now. Must be cleared to zero. | ||
| 1552 | */ | ||
| 1553 | __u32 rsvd; | ||
| 1554 | }; | ||
| 1555 | |||
| 1492 | enum drm_i915_oa_format { | 1556 | enum drm_i915_oa_format { |
| 1493 | I915_OA_FORMAT_A13 = 1, /* HSW only */ | 1557 | I915_OA_FORMAT_A13 = 1, /* HSW only */ |
| 1494 | I915_OA_FORMAT_A29, /* HSW only */ | 1558 | I915_OA_FORMAT_A29, /* HSW only */ |