Most constants defined in xe_drm.h use DRM_XE_ as prefix which is helpful to identify the name space. Make this systematic and add this prefix where it was missing. v2: - fix vertical alignment of define values - remove double DRM_ in some variables (José Roberto de Souza) v3: Rebase
Unified · Split
| @@ -209,7 +209,7 @@ static int __xe_bo_placement_for_flags(struct xe_device *xe, struct xe_bo *bo, · 208 unmodified lines | |||
| 209 | 209 | ||
| 210 | /* The order of placements should indicate preferred location */ | 210 | /* The order of placements should indicate preferred location */ |
| 211 | 211 | ||
| 212 | if (bo->props.preferred_mem_class == XE_MEM_REGION_CLASS_SYSMEM) { | 212 | if (bo->props.preferred_mem_class == DRM_XE_MEM_REGION_CLASS_SYSMEM) { |
| 213 | try_add_system(bo, places, bo_flags, &c); | 213 | try_add_system(bo, places, bo_flags, &c); |
| 214 | try_add_vram(xe, bo, places, bo_flags, &c); | 214 | try_add_vram(xe, bo, places, bo_flags, &c); |
| 215 | } else { | 215 | } else { |
| @@ -1814,9 +1814,9 @@ int xe_gem_create_ioctl(struct drm_device *dev, void *data, · 1598 unmodified lines | |||
| 1814 | return -EINVAL; | 1814 | return -EINVAL; |
| 1815 | 1815 | ||
| 1816 | if (XE_IOCTL_DBG(xe, args->flags & | 1816 | if (XE_IOCTL_DBG(xe, args->flags & |
| 1817 | ~(XE_GEM_CREATE_FLAG_DEFER_BACKING | | 1817 | ~(DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING | |
| 1818 | XE_GEM_CREATE_FLAG_SCANOUT | | 1818 | DRM_XE_GEM_CREATE_FLAG_SCANOUT | |
| 1819 | XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM | | 1819 | DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM | |
| 1820 | xe->info.mem_region_mask))) | 1820 | xe->info.mem_region_mask))) |
| 1821 | return -EINVAL; | 1821 | return -EINVAL; |
| 1822 | 1822 | ||
| @@ -1836,15 +1836,15 @@ int xe_gem_create_ioctl(struct drm_device *dev, void *data, · 13 unmodified lines | |||
| 1836 | if (XE_IOCTL_DBG(xe, args->size & ~PAGE_MASK)) | 1836 | if (XE_IOCTL_DBG(xe, args->size & ~PAGE_MASK)) |
| 1837 | return -EINVAL; | 1837 | return -EINVAL; |
| 1838 | 1838 | ||
| 1839 | if (args->flags & XE_GEM_CREATE_FLAG_DEFER_BACKING) | 1839 | if (args->flags & DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING) |
| 1840 | bo_flags |= XE_BO_DEFER_BACKING; | 1840 | bo_flags |= XE_BO_DEFER_BACKING; |
| 1841 | 1841 | ||
| 1842 | if (args->flags & XE_GEM_CREATE_FLAG_SCANOUT) | 1842 | if (args->flags & DRM_XE_GEM_CREATE_FLAG_SCANOUT) |
| 1843 | bo_flags |= XE_BO_SCANOUT_BIT; | 1843 | bo_flags |= XE_BO_SCANOUT_BIT; |
| 1844 | 1844 | ||
| 1845 | bo_flags |= args->flags << (ffs(XE_BO_CREATE_SYSTEM_BIT) - 1); | 1845 | bo_flags |= args->flags << (ffs(XE_BO_CREATE_SYSTEM_BIT) - 1); |
| 1846 | 1846 | ||
| 1847 | if (args->flags & XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM) { | 1847 | if (args->flags & DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM) { |
| 1848 | if (XE_IOCTL_DBG(xe, !(bo_flags & XE_BO_CREATE_VRAM_MASK))) | 1848 | if (XE_IOCTL_DBG(xe, !(bo_flags & XE_BO_CREATE_VRAM_MASK))) |
| 1849 | return -EINVAL; | 1849 | return -EINVAL; |
| 1850 | 1850 | ||
| @@ -393,7 +393,7 @@ static int exec_queue_set_acc_granularity(struct xe_device *xe, struct xe_exec_q · 392 unmodified lines | |||
| 393 | if (XE_IOCTL_DBG(xe, !xe->info.supports_usm)) | 393 | if (XE_IOCTL_DBG(xe, !xe->info.supports_usm)) |
| 394 | return -EINVAL; | 394 | return -EINVAL; |
| 395 | 395 | ||
| 396 | if (value > XE_ACC_GRANULARITY_64M) | 396 | if (value > DRM_XE_ACC_GRANULARITY_64M) |
| 397 | return -EINVAL; | 397 | return -EINVAL; |
| 398 | 398 | ||
| 399 | q->usm.acc_granularity = value; | 399 | q->usm.acc_granularity = value; |
| @@ -406,14 +406,14 @@ typedef int (*xe_exec_queue_set_property_fn)(struct xe_device *xe, · 6 unmodified lines | |||
| 406 | u64 value, bool create); | 406 | u64 value, bool create); |
| 407 | 407 | ||
| 408 | static const xe_exec_queue_set_property_fn exec_queue_set_property_funcs[] = { | 408 | static const xe_exec_queue_set_property_fn exec_queue_set_property_funcs[] = { |
| 409 | [XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY] = exec_queue_set_priority, | 409 | [DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY] = exec_queue_set_priority, |
| 410 | [XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE] = exec_queue_set_timeslice, | 410 | [DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE] = exec_queue_set_timeslice, |
| 411 | [XE_EXEC_QUEUE_SET_PROPERTY_PREEMPTION_TIMEOUT] = exec_queue_set_preemption_timeout, | 411 | [DRM_XE_EXEC_QUEUE_SET_PROPERTY_PREEMPTION_TIMEOUT] = exec_queue_set_preemption_timeout, |
| 412 | [XE_EXEC_QUEUE_SET_PROPERTY_PERSISTENCE] = exec_queue_set_persistence, | 412 | [DRM_XE_EXEC_QUEUE_SET_PROPERTY_PERSISTENCE] = exec_queue_set_persistence, |
| 413 | [XE_EXEC_QUEUE_SET_PROPERTY_JOB_TIMEOUT] = exec_queue_set_job_timeout, | 413 | [DRM_XE_EXEC_QUEUE_SET_PROPERTY_JOB_TIMEOUT] = exec_queue_set_job_timeout, |
| 414 | [XE_EXEC_QUEUE_SET_PROPERTY_ACC_TRIGGER] = exec_queue_set_acc_trigger, | 414 | [DRM_XE_EXEC_QUEUE_SET_PROPERTY_ACC_TRIGGER] = exec_queue_set_acc_trigger, |
| 415 | [XE_EXEC_QUEUE_SET_PROPERTY_ACC_NOTIFY] = exec_queue_set_acc_notify, | 415 | [DRM_XE_EXEC_QUEUE_SET_PROPERTY_ACC_NOTIFY] = exec_queue_set_acc_notify, |
| 416 | [XE_EXEC_QUEUE_SET_PROPERTY_ACC_GRANULARITY] = exec_queue_set_acc_granularity, | 416 | [DRM_XE_EXEC_QUEUE_SET_PROPERTY_ACC_GRANULARITY] = exec_queue_set_acc_granularity, |
| 417 | }; | 417 | }; |
| 418 | 418 | ||
| 419 | static int exec_queue_user_ext_set_property(struct xe_device *xe, | 419 | static int exec_queue_user_ext_set_property(struct xe_device *xe, |
| @@ -445,7 +445,7 @@ typedef int (*xe_exec_queue_user_extension_fn)(struct xe_device *xe, · 25 unmodified lines | |||
| 445 | bool create); | 445 | bool create); |
| 446 | 446 | ||
| 447 | static const xe_exec_queue_set_property_fn exec_queue_user_extension_funcs[] = { | 447 | static const xe_exec_queue_set_property_fn exec_queue_user_extension_funcs[] = { |
| 448 | [XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY] = exec_queue_user_ext_set_property, | 448 | [DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY] = exec_queue_user_ext_set_property, |
| 449 | }; | 449 | }; |
| 450 | 450 | ||
| 451 | #define MAX_USER_EXTENSIONS 16 | 451 | #define MAX_USER_EXTENSIONS 16 |
| @@ -764,7 +764,7 @@ int xe_exec_queue_get_property_ioctl(struct drm_device *dev, void *data, · 312 unmodified lines | |||
| 764 | return -ENOENT; | 764 | return -ENOENT; |
| 765 | 765 | ||
| 766 | switch (args->property) { | 766 | switch (args->property) { |
| 767 | case XE_EXEC_QUEUE_GET_PROPERTY_BAN: | 767 | case DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN: |
| 768 | args->value = !!(q->flags & EXEC_QUEUE_FLAG_BANNED); | 768 | args->value = !!(q->flags & EXEC_QUEUE_FLAG_BANNED); |
| 769 | ret = 0; | 769 | ret = 0; |
| 770 | break; | 770 | break; |
| @@ -560,7 +560,7 @@ static void xe_uevent_gt_reset_failure(struct pci_dev *pdev, u8 tile_id, u8 gt_i · 559 unmodified lines | |||
| 560 | { | 560 | { |
| 561 | char *reset_event[4]; | 561 | char *reset_event[4]; |
| 562 | 562 | ||
| 563 | reset_event[0] = XE_RESET_FAILED_UEVENT "=NEEDS_RESET"; | 563 | reset_event[0] = DRM_XE_RESET_FAILED_UEVENT "=NEEDS_RESET"; |
| 564 | reset_event[1] = kasprintf(GFP_KERNEL, "TILE_ID=%d", tile_id); | 564 | reset_event[1] = kasprintf(GFP_KERNEL, "TILE_ID=%d", tile_id); |
| 565 | reset_event[2] = kasprintf(GFP_KERNEL, "GT_ID=%d", gt_id); | 565 | reset_event[2] = kasprintf(GFP_KERNEL, "GT_ID=%d", gt_id); |
| 566 | reset_event[3] = NULL; | 566 | reset_event[3] = NULL; |
| @@ -17,12 +17,12 @@ static unsigned int xe_pmu_target_cpu = -1; · 16 unmodified lines | |||
| 17 | 17 | ||
| 18 | static unsigned int config_gt_id(const u64 config) | 18 | static unsigned int config_gt_id(const u64 config) |
| 19 | { | 19 | { |
| 20 | return config >> __XE_PMU_GT_SHIFT; | 20 | return config >> __DRM_XE_PMU_GT_SHIFT; |
| 21 | } | 21 | } |
| 22 | 22 | ||
| 23 | static u64 config_counter(const u64 config) | 23 | static u64 config_counter(const u64 config) |
| 24 | { | 24 | { |
| 25 | return config & ~(~0ULL << __XE_PMU_GT_SHIFT); | 25 | return config & ~(~0ULL << __DRM_XE_PMU_GT_SHIFT); |
| 26 | } | 26 | } |
| 27 | 27 | ||
| 28 | static void xe_pmu_event_destroy(struct perf_event *event) | 28 | static void xe_pmu_event_destroy(struct perf_event *event) |
| @@ -114,13 +114,13 @@ config_status(struct xe_device *xe, u64 config) · 85 unmodified lines | |||
| 114 | return -ENOENT; | 114 | return -ENOENT; |
| 115 | 115 | ||
| 116 | switch (config_counter(config)) { | 116 | switch (config_counter(config)) { |
| 117 | case XE_PMU_RENDER_GROUP_BUSY(0): | 117 | case DRM_XE_PMU_RENDER_GROUP_BUSY(0): |
| 118 | case XE_PMU_COPY_GROUP_BUSY(0): | 118 | case DRM_XE_PMU_COPY_GROUP_BUSY(0): |
| 119 | case XE_PMU_ANY_ENGINE_GROUP_BUSY(0): | 119 | case DRM_XE_PMU_ANY_ENGINE_GROUP_BUSY(0): |
| 120 | if (gt->info.type == XE_GT_TYPE_MEDIA) | 120 | if (gt->info.type == XE_GT_TYPE_MEDIA) |
| 121 | return -ENOENT; | 121 | return -ENOENT; |
| 122 | break; | 122 | break; |
| 123 | case XE_PMU_MEDIA_GROUP_BUSY(0): | 123 | case DRM_XE_PMU_MEDIA_GROUP_BUSY(0): |
| 124 | if (!(gt->info.engine_mask & (BIT(XE_HW_ENGINE_VCS0) | BIT(XE_HW_ENGINE_VECS0)))) | 124 | if (!(gt->info.engine_mask & (BIT(XE_HW_ENGINE_VCS0) | BIT(XE_HW_ENGINE_VECS0)))) |
| 125 | return -ENOENT; | 125 | return -ENOENT; |
| 126 | break; | 126 | break; |
| @@ -180,10 +180,10 @@ static u64 __xe_pmu_event_read(struct perf_event *event) · 53 unmodified lines | |||
| 180 | u64 val; | 180 | u64 val; |
| 181 | 181 | ||
| 182 | switch (config_counter(config)) { | 182 | switch (config_counter(config)) { |
| 183 | case XE_PMU_RENDER_GROUP_BUSY(0): | 183 | case DRM_XE_PMU_RENDER_GROUP_BUSY(0): |
| 184 | case XE_PMU_COPY_GROUP_BUSY(0): | 184 | case DRM_XE_PMU_COPY_GROUP_BUSY(0): |
| 185 | case XE_PMU_ANY_ENGINE_GROUP_BUSY(0): | 185 | case DRM_XE_PMU_ANY_ENGINE_GROUP_BUSY(0): |
| 186 | case XE_PMU_MEDIA_GROUP_BUSY(0): | 186 | case DRM_XE_PMU_MEDIA_GROUP_BUSY(0): |
| 187 | val = engine_group_busyness_read(gt, config); | 187 | val = engine_group_busyness_read(gt, config); |
| 188 | break; | 188 | break; |
| 189 | default: | 189 | default: |
| @@ -369,7 +369,7 @@ create_event_attributes(struct xe_pmu *pmu) · 179 unmodified lines | |||
| 369 | /* Count how many counters we will be exposing. */ | 369 | /* Count how many counters we will be exposing. */ |
| 370 | for_each_gt(gt, xe, j) { | 370 | for_each_gt(gt, xe, j) { |
| 371 | for (i = 0; i < ARRAY_SIZE(events); i++) { | 371 | for (i = 0; i < ARRAY_SIZE(events); i++) { |
| 372 | u64 config = ___XE_PMU_OTHER(j, events[i].counter); | 372 | u64 config = ___DRM_XE_PMU_OTHER(j, events[i].counter); |
| 373 | 373 | ||
| 374 | if (!config_status(xe, config)) | 374 | if (!config_status(xe, config)) |
| 375 | count++; | 375 | count++; |
| @@ -396,7 +396,7 @@ create_event_attributes(struct xe_pmu *pmu) · 20 unmodified lines | |||
| 396 | 396 | ||
| 397 | for_each_gt(gt, xe, j) { | 397 | for_each_gt(gt, xe, j) { |
| 398 | for (i = 0; i < ARRAY_SIZE(events); i++) { | 398 | for (i = 0; i < ARRAY_SIZE(events); i++) { |
| 399 | u64 config = ___XE_PMU_OTHER(j, events[i].counter); | 399 | u64 config = ___DRM_XE_PMU_OTHER(j, events[i].counter); |
| 400 | char *str; | 400 | char *str; |
| 401 | 401 | ||
| 402 | if (config_status(xe, config)) | 402 | if (config_status(xe, config)) |
| @@ -261,7 +261,7 @@ static int query_memory_usage(struct xe_device *xe, · 260 unmodified lines | |||
| 261 | return -ENOMEM; | 261 | return -ENOMEM; |
| 262 | 262 | ||
| 263 | man = ttm_manager_type(&xe->ttm, XE_PL_TT); | 263 | man = ttm_manager_type(&xe->ttm, XE_PL_TT); |
| 264 | usage->regions[0].mem_class = XE_MEM_REGION_CLASS_SYSMEM; | 264 | usage->regions[0].mem_class = DRM_XE_MEM_REGION_CLASS_SYSMEM; |
| 265 | usage->regions[0].instance = 0; | 265 | usage->regions[0].instance = 0; |
| 266 | usage->regions[0].min_page_size = PAGE_SIZE; | 266 | usage->regions[0].min_page_size = PAGE_SIZE; |
| 267 | usage->regions[0].total_size = man->size << PAGE_SHIFT; | 267 | usage->regions[0].total_size = man->size << PAGE_SHIFT; |
| @@ -273,7 +273,7 @@ static int query_memory_usage(struct xe_device *xe, · 5 unmodified lines | |||
| 273 | man = ttm_manager_type(&xe->ttm, i); | 273 | man = ttm_manager_type(&xe->ttm, i); |
| 274 | if (man) { | 274 | if (man) { |
| 275 | usage->regions[usage->num_regions].mem_class = | 275 | usage->regions[usage->num_regions].mem_class = |
| 276 | XE_MEM_REGION_CLASS_VRAM; | 276 | DRM_XE_MEM_REGION_CLASS_VRAM; |
| 277 | usage->regions[usage->num_regions].instance = | 277 | usage->regions[usage->num_regions].instance = |
| 278 | usage->num_regions; | 278 | usage->num_regions; |
| 279 | usage->regions[usage->num_regions].min_page_size = | 279 | usage->regions[usage->num_regions].min_page_size = |
| @@ -305,7 +305,7 @@ static int query_memory_usage(struct xe_device *xe, · 25 unmodified lines | |||
| 305 | 305 | ||
| 306 | static int query_config(struct xe_device *xe, struct drm_xe_device_query *query) | 306 | static int query_config(struct xe_device *xe, struct drm_xe_device_query *query) |
| 307 | { | 307 | { |
| 308 | const u32 num_params = XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY + 1; | 308 | const u32 num_params = DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY + 1; |
| 309 | size_t size = | 309 | size_t size = |
| 310 | sizeof(struct drm_xe_query_config) + num_params * sizeof(u64); | 310 | sizeof(struct drm_xe_query_config) + num_params * sizeof(u64); |
| 311 | struct drm_xe_query_config __user *query_ptr = | 311 | struct drm_xe_query_config __user *query_ptr = |
| @@ -324,15 +324,15 @@ static int query_config(struct xe_device *xe, struct drm_xe_device_query *query) · 12 unmodified lines | |||
| 324 | return -ENOMEM; | 324 | return -ENOMEM; |
| 325 | 325 | ||
| 326 | config->num_params = num_params; | 326 | config->num_params = num_params; |
| 327 | config->info[XE_QUERY_CONFIG_REV_AND_DEVICE_ID] = | 327 | config->info[DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID] = |
| 328 | xe->info.devid | (xe->info.revid << 16); | 328 | xe->info.devid | (xe->info.revid << 16); |
| 329 | if (xe_device_get_root_tile(xe)->mem.vram.usable_size) | 329 | if (xe_device_get_root_tile(xe)->mem.vram.usable_size) |
| 330 | config->info[XE_QUERY_CONFIG_FLAGS] = | 330 | config->info[DRM_XE_QUERY_CONFIG_FLAGS] = |
| 331 | XE_QUERY_CONFIG_FLAGS_HAS_VRAM; | 331 | DRM_XE_QUERY_CONFIG_FLAGS_HAS_VRAM; |
| 332 | config->info[XE_QUERY_CONFIG_MIN_ALIGNMENT] = | 332 | config->info[DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT] = |
| 333 | xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K ? SZ_64K : SZ_4K; | 333 | xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K ? SZ_64K : SZ_4K; |
| 334 | config->info[XE_QUERY_CONFIG_VA_BITS] = xe->info.va_bits; | 334 | config->info[DRM_XE_QUERY_CONFIG_VA_BITS] = xe->info.va_bits; |
| 335 | config->info[XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY] = | 335 | config->info[DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY] = |
| 336 | xe_exec_queue_device_get_max_priority(xe); | 336 | xe_exec_queue_device_get_max_priority(xe); |
| 337 | 337 | ||
| 338 | if (copy_to_user(query_ptr, config, size)) { | 338 | if (copy_to_user(query_ptr, config, size)) { |
| @@ -368,9 +368,9 @@ static int query_gt_list(struct xe_device *xe, struct drm_xe_device_query *query · 29 unmodified lines | |||
| 368 | gt_list->num_gt = xe->info.gt_count; | 368 | gt_list->num_gt = xe->info.gt_count; |
| 369 | for_each_gt(gt, xe, id) { | 369 | for_each_gt(gt, xe, id) { |
| 370 | if (xe_gt_is_media_type(gt)) | 370 | if (xe_gt_is_media_type(gt)) |
| 371 | gt_list->gt_list[id].type = XE_QUERY_GT_TYPE_MEDIA; | 371 | gt_list->gt_list[id].type = DRM_XE_QUERY_GT_TYPE_MEDIA; |
| 372 | else | 372 | else |
| 373 | gt_list->gt_list[id].type = XE_QUERY_GT_TYPE_MAIN; | 373 | gt_list->gt_list[id].type = DRM_XE_QUERY_GT_TYPE_MAIN; |
| 374 | gt_list->gt_list[id].gt_id = gt->info.id; | 374 | gt_list->gt_list[id].gt_id = gt->info.id; |
| 375 | gt_list->gt_list[id].clock_freq = gt->info.clock_freq; | 375 | gt_list->gt_list[id].clock_freq = gt->info.clock_freq; |
| 376 | if (!IS_DGFX(xe)) | 376 | if (!IS_DGFX(xe)) |
| @@ -468,21 +468,21 @@ static int query_gt_topology(struct xe_device *xe, · 91 unmodified lines | |||
| 468 | for_each_gt(gt, xe, id) { | 468 | for_each_gt(gt, xe, id) { |
| 469 | topo.gt_id = id; | 469 | topo.gt_id = id; |
| 470 | 470 | ||
| 471 | topo.type = XE_TOPO_DSS_GEOMETRY; | 471 | topo.type = DRM_XE_TOPO_DSS_GEOMETRY; |
| 472 | query_ptr = copy_mask(query_ptr, &topo, | 472 | query_ptr = copy_mask(query_ptr, &topo, |
| 473 | gt->fuse_topo.g_dss_mask, | 473 | gt->fuse_topo.g_dss_mask, |
| 474 | sizeof(gt->fuse_topo.g_dss_mask)); | 474 | sizeof(gt->fuse_topo.g_dss_mask)); |
| 475 | if (IS_ERR(query_ptr)) | 475 | if (IS_ERR(query_ptr)) |
| 476 | return PTR_ERR(query_ptr); | 476 | return PTR_ERR(query_ptr); |
| 477 | 477 | ||
| 478 | topo.type = XE_TOPO_DSS_COMPUTE; | 478 | topo.type = DRM_XE_TOPO_DSS_COMPUTE; |
| 479 | query_ptr = copy_mask(query_ptr, &topo, | 479 | query_ptr = copy_mask(query_ptr, &topo, |
| 480 | gt->fuse_topo.c_dss_mask, | 480 | gt->fuse_topo.c_dss_mask, |
| 481 | sizeof(gt->fuse_topo.c_dss_mask)); | 481 | sizeof(gt->fuse_topo.c_dss_mask)); |
| 482 | if (IS_ERR(query_ptr)) | 482 | if (IS_ERR(query_ptr)) |
| 483 | return PTR_ERR(query_ptr); | 483 | return PTR_ERR(query_ptr); |
| 484 | 484 | ||
| 485 | topo.type = XE_TOPO_EU_PER_DSS; | 485 | topo.type = DRM_XE_TOPO_EU_PER_DSS; |
| 486 | query_ptr = copy_mask(query_ptr, &topo, | 486 | query_ptr = copy_mask(query_ptr, &topo, |
| 487 | gt->fuse_topo.eu_mask_per_dss, | 487 | gt->fuse_topo.eu_mask_per_dss, |
| 488 | sizeof(gt->fuse_topo.eu_mask_per_dss)); | 488 | sizeof(gt->fuse_topo.eu_mask_per_dss)); |
| @@ -2177,8 +2177,8 @@ vm_bind_ioctl_ops_create(struct xe_vm *vm, struct xe_bo *bo, · 2176 unmodified lines | |||
| 2177 | (ULL)bo_offset_or_userptr); | 2177 | (ULL)bo_offset_or_userptr); |
| 2178 | 2178 | ||
| 2179 | switch (operation) { | 2179 | switch (operation) { |
| 2180 | case XE_VM_BIND_OP_MAP: | 2180 | case DRM_XE_VM_BIND_OP_MAP: |
| 2181 | case XE_VM_BIND_OP_MAP_USERPTR: | 2181 | case DRM_XE_VM_BIND_OP_MAP_USERPTR: |
| 2182 | ops = drm_gpuvm_sm_map_ops_create(&vm->gpuvm, addr, range, | 2182 | ops = drm_gpuvm_sm_map_ops_create(&vm->gpuvm, addr, range, |
| 2183 | obj, bo_offset_or_userptr); | 2183 | obj, bo_offset_or_userptr); |
| 2184 | if (IS_ERR(ops)) | 2184 | if (IS_ERR(ops)) |
| @@ -2189,13 +2189,13 @@ vm_bind_ioctl_ops_create(struct xe_vm *vm, struct xe_bo *bo, · 4 unmodified lines | |||
| 2189 | 2189 | ||
| 2190 | op->tile_mask = tile_mask; | 2190 | op->tile_mask = tile_mask; |
| 2191 | op->map.immediate = | 2191 | op->map.immediate = |
| 2192 | flags & XE_VM_BIND_FLAG_IMMEDIATE; | 2192 | flags & DRM_XE_VM_BIND_FLAG_IMMEDIATE; |
| 2193 | op->map.read_only = | 2193 | op->map.read_only = |
| 2194 | flags & XE_VM_BIND_FLAG_READONLY; | 2194 | flags & DRM_XE_VM_BIND_FLAG_READONLY; |
| 2195 | op->map.is_null = flags & XE_VM_BIND_FLAG_NULL; | 2195 | op->map.is_null = flags & DRM_XE_VM_BIND_FLAG_NULL; |
| 2196 | } | 2196 | } |
| 2197 | break; | 2197 | break; |
| 2198 | case XE_VM_BIND_OP_UNMAP: | 2198 | case DRM_XE_VM_BIND_OP_UNMAP: |
| 2199 | ops = drm_gpuvm_sm_unmap_ops_create(&vm->gpuvm, addr, range); | 2199 | ops = drm_gpuvm_sm_unmap_ops_create(&vm->gpuvm, addr, range); |
| 2200 | if (IS_ERR(ops)) | 2200 | if (IS_ERR(ops)) |
| 2201 | return ops; | 2201 | return ops; |
| @@ -2206,7 +2206,7 @@ vm_bind_ioctl_ops_create(struct xe_vm *vm, struct xe_bo *bo, · 4 unmodified lines | |||
| 2206 | op->tile_mask = tile_mask; | 2206 | op->tile_mask = tile_mask; |
| 2207 | } | 2207 | } |
| 2208 | break; | 2208 | break; |
| 2209 | case XE_VM_BIND_OP_PREFETCH: | 2209 | case DRM_XE_VM_BIND_OP_PREFETCH: |
| 2210 | ops = drm_gpuvm_prefetch_ops_create(&vm->gpuvm, addr, range); | 2210 | ops = drm_gpuvm_prefetch_ops_create(&vm->gpuvm, addr, range); |
| 2211 | if (IS_ERR(ops)) | 2211 | if (IS_ERR(ops)) |
| 2212 | return ops; | 2212 | return ops; |
| @@ -2218,7 +2218,7 @@ vm_bind_ioctl_ops_create(struct xe_vm *vm, struct xe_bo *bo, · 5 unmodified lines | |||
| 2218 | op->prefetch.region = region; | 2218 | op->prefetch.region = region; |
| 2219 | } | 2219 | } |
| 2220 | break; | 2220 | break; |
| 2221 | case XE_VM_BIND_OP_UNMAP_ALL: | 2221 | case DRM_XE_VM_BIND_OP_UNMAP_ALL: |
| 2222 | xe_assert(vm->xe, bo); | 2222 | xe_assert(vm->xe, bo); |
| 2223 | 2223 | ||
| 2224 | err = xe_bo_lock(bo, true); | 2224 | err = xe_bo_lock(bo, true); |
| @@ -2828,13 +2828,13 @@ static int vm_bind_ioctl_ops_execute(struct xe_vm *vm, · 603 unmodified lines | |||
| 2828 | 2828 | ||
| 2829 | #ifdef TEST_VM_ASYNC_OPS_ERROR | 2829 | #ifdef TEST_VM_ASYNC_OPS_ERROR |
| 2830 | #define SUPPORTED_FLAGS \ | 2830 | #define SUPPORTED_FLAGS \ |
| 2831 | (FORCE_ASYNC_OP_ERROR | XE_VM_BIND_FLAG_ASYNC | \ | 2831 | (FORCE_ASYNC_OP_ERROR | DRM_XE_VM_BIND_FLAG_ASYNC | \ |
| 2832 | XE_VM_BIND_FLAG_READONLY | XE_VM_BIND_FLAG_IMMEDIATE | \ | 2832 | DRM_XE_VM_BIND_FLAG_READONLY | DRM_XE_VM_BIND_FLAG_IMMEDIATE | \ |
| 2833 | XE_VM_BIND_FLAG_NULL | 0xffff) | 2833 | DRM_XE_VM_BIND_FLAG_NULL | 0xffff) |
| 2834 | #else | 2834 | #else |
| 2835 | #define SUPPORTED_FLAGS \ | 2835 | #define SUPPORTED_FLAGS \ |
| 2836 | (XE_VM_BIND_FLAG_ASYNC | XE_VM_BIND_FLAG_READONLY | \ | 2836 | (DRM_XE_VM_BIND_FLAG_ASYNC | DRM_XE_VM_BIND_FLAG_READONLY | \ |
| 2837 | XE_VM_BIND_FLAG_IMMEDIATE | XE_VM_BIND_FLAG_NULL | \ | 2837 | DRM_XE_VM_BIND_FLAG_IMMEDIATE | DRM_XE_VM_BIND_FLAG_NULL | \ |
| 2838 | 0xffff) | 2838 | 0xffff) |
| 2839 | #endif | 2839 | #endif |
| 2840 | #define XE_64K_PAGE_MASK 0xffffull | 2840 | #define XE_64K_PAGE_MASK 0xffffull |
| @@ -2882,45 +2882,45 @@ static int vm_bind_ioctl_check_args(struct xe_device *xe, · 41 unmodified lines | |||
| 2882 | u32 obj = (*bind_ops)[i].obj; | 2882 | u32 obj = (*bind_ops)[i].obj; |
| 2883 | u64 obj_offset = (*bind_ops)[i].obj_offset; | 2883 | u64 obj_offset = (*bind_ops)[i].obj_offset; |
| 2884 | u32 region = (*bind_ops)[i].region; | 2884 | u32 region = (*bind_ops)[i].region; |
| 2885 | bool is_null = flags & XE_VM_BIND_FLAG_NULL; | 2885 | bool is_null = flags & DRM_XE_VM_BIND_FLAG_NULL; |
| 2886 | 2886 | ||
| 2887 | if (i == 0) { | 2887 | if (i == 0) { |
| 2888 | *async = !!(flags & XE_VM_BIND_FLAG_ASYNC); | 2888 | *async = !!(flags & DRM_XE_VM_BIND_FLAG_ASYNC); |
| 2889 | if (XE_IOCTL_DBG(xe, !*async && args->num_syncs)) { | 2889 | if (XE_IOCTL_DBG(xe, !*async && args->num_syncs)) { |
| 2890 | err = -EINVAL; | 2890 | err = -EINVAL; |
| 2891 | goto free_bind_ops; | 2891 | goto free_bind_ops; |
| 2892 | } | 2892 | } |
| 2893 | } else if (XE_IOCTL_DBG(xe, *async != | 2893 | } else if (XE_IOCTL_DBG(xe, *async != |
| 2894 | !!(flags & XE_VM_BIND_FLAG_ASYNC))) { | 2894 | !!(flags & DRM_XE_VM_BIND_FLAG_ASYNC))) { |
| 2895 | err = -EINVAL; | 2895 | err = -EINVAL; |
| 2896 | goto free_bind_ops; | 2896 | goto free_bind_ops; |
| 2897 | } | 2897 | } |
| 2898 | 2898 | ||
| 2899 | if (XE_IOCTL_DBG(xe, op > XE_VM_BIND_OP_PREFETCH) || | 2899 | if (XE_IOCTL_DBG(xe, op > DRM_XE_VM_BIND_OP_PREFETCH) || |
| 2900 | XE_IOCTL_DBG(xe, flags & ~SUPPORTED_FLAGS) || | 2900 | XE_IOCTL_DBG(xe, flags & ~SUPPORTED_FLAGS) || |
| 2901 | XE_IOCTL_DBG(xe, obj && is_null) || | 2901 | XE_IOCTL_DBG(xe, obj && is_null) || |
| 2902 | XE_IOCTL_DBG(xe, obj_offset && is_null) || | 2902 | XE_IOCTL_DBG(xe, obj_offset && is_null) || |
| 2903 | XE_IOCTL_DBG(xe, op != XE_VM_BIND_OP_MAP && | 2903 | XE_IOCTL_DBG(xe, op != DRM_XE_VM_BIND_OP_MAP && |
| 2904 | is_null) || | 2904 | is_null) || |
| 2905 | XE_IOCTL_DBG(xe, !obj && | 2905 | XE_IOCTL_DBG(xe, !obj && |
| 2906 | op == XE_VM_BIND_OP_MAP && | 2906 | op == DRM_XE_VM_BIND_OP_MAP && |
| 2907 | !is_null) || | 2907 | !is_null) || |
| 2908 | XE_IOCTL_DBG(xe, !obj && | 2908 | XE_IOCTL_DBG(xe, !obj && |
| 2909 | op == XE_VM_BIND_OP_UNMAP_ALL) || | 2909 | op == DRM_XE_VM_BIND_OP_UNMAP_ALL) || |
| 2910 | XE_IOCTL_DBG(xe, addr && | 2910 | XE_IOCTL_DBG(xe, addr && |
| 2911 | op == XE_VM_BIND_OP_UNMAP_ALL) || | 2911 | op == DRM_XE_VM_BIND_OP_UNMAP_ALL) || |
| 2912 | XE_IOCTL_DBG(xe, range && | 2912 | XE_IOCTL_DBG(xe, range && |
| 2913 | op == XE_VM_BIND_OP_UNMAP_ALL) || | 2913 | op == DRM_XE_VM_BIND_OP_UNMAP_ALL) || |
| 2914 | XE_IOCTL_DBG(xe, obj && | 2914 | XE_IOCTL_DBG(xe, obj && |
| 2915 | op == XE_VM_BIND_OP_MAP_USERPTR) || | 2915 | op == DRM_XE_VM_BIND_OP_MAP_USERPTR) || |
| 2916 | XE_IOCTL_DBG(xe, obj && | 2916 | XE_IOCTL_DBG(xe, obj && |
| 2917 | op == XE_VM_BIND_OP_PREFETCH) || | 2917 | op == DRM_XE_VM_BIND_OP_PREFETCH) || |
| 2918 | XE_IOCTL_DBG(xe, region && | 2918 | XE_IOCTL_DBG(xe, region && |
| 2919 | op != XE_VM_BIND_OP_PREFETCH) || | 2919 | op != DRM_XE_VM_BIND_OP_PREFETCH) || |
| 2920 | XE_IOCTL_DBG(xe, !(BIT(region) & | 2920 | XE_IOCTL_DBG(xe, !(BIT(region) & |
| 2921 | xe->info.mem_region_mask)) || | 2921 | xe->info.mem_region_mask)) || |
| 2922 | XE_IOCTL_DBG(xe, obj && | 2922 | XE_IOCTL_DBG(xe, obj && |
| 2923 | op == XE_VM_BIND_OP_UNMAP)) { | 2923 | op == DRM_XE_VM_BIND_OP_UNMAP)) { |
| 2924 | err = -EINVAL; | 2924 | err = -EINVAL; |
| 2925 | goto free_bind_ops; | 2925 | goto free_bind_ops; |
| 2926 | } | 2926 | } |
| @@ -2929,7 +2929,7 @@ static int vm_bind_ioctl_check_args(struct xe_device *xe, · 2 unmodified lines | |||
| 2929 | XE_IOCTL_DBG(xe, addr & ~PAGE_MASK) || | 2929 | XE_IOCTL_DBG(xe, addr & ~PAGE_MASK) || |
| 2930 | XE_IOCTL_DBG(xe, range & ~PAGE_MASK) || | 2930 | XE_IOCTL_DBG(xe, range & ~PAGE_MASK) || |
| 2931 | XE_IOCTL_DBG(xe, !range && | 2931 | XE_IOCTL_DBG(xe, !range && |
| 2932 | op != XE_VM_BIND_OP_UNMAP_ALL)) { | 2932 | op != DRM_XE_VM_BIND_OP_UNMAP_ALL)) { |
| 2933 | err = -EINVAL; | 2933 | err = -EINVAL; |
| 2934 | goto free_bind_ops; | 2934 | goto free_bind_ops; |
| 2935 | } | 2935 | } |
| @@ -32,9 +32,9 @@ · 31 unmodified lines | |||
| 32 | * Operations | 32 | * Operations |
| 33 | * ---------- | 33 | * ---------- |
| 34 | * | 34 | * |
| 35 | * XE_VM_BIND_OP_MAP - Create mapping for a BO | 35 | * DRM_XE_VM_BIND_OP_MAP - Create mapping for a BO |
| 36 | * XE_VM_BIND_OP_UNMAP - Destroy mapping for a BO / userptr | 36 | * DRM_XE_VM_BIND_OP_UNMAP - Destroy mapping for a BO / userptr |
| 37 | * XE_VM_BIND_OP_MAP_USERPTR - Create mapping for userptr | 37 | * DRM_XE_VM_BIND_OP_MAP_USERPTR - Create mapping for userptr |
| 38 | * | 38 | * |
| 39 | * Implementation details | 39 | * Implementation details |
| 40 | * ~~~~~~~~~~~~~~~~~~~~~~ | 40 | * ~~~~~~~~~~~~~~~~~~~~~~ |
| @@ -113,7 +113,7 @@ · 72 unmodified lines | |||
| 113 | * VM uses to report errors to. The ufence wait interface can be used to wait on | 113 | * VM uses to report errors to. The ufence wait interface can be used to wait on |
| 114 | * a VM going into an error state. Once an error is reported the VM's async | 114 | * a VM going into an error state. Once an error is reported the VM's async |
| 115 | * worker is paused. While the VM's async worker is paused sync, | 115 | * worker is paused. While the VM's async worker is paused sync, |
| 116 | * XE_VM_BIND_OP_UNMAP operations are allowed (this can free memory). Once the | 116 | * DRM_XE_VM_BIND_OP_UNMAP operations are allowed (this can free memory). Once the |
| 117 | * uses believe the error state is fixed, the async worker can be resumed via | 117 | * uses believe the error state is fixed, the async worker can be resumed via |
| 118 | * XE_VM_BIND_OP_RESTART operation. When VM async bind work is restarted, the | 118 | * XE_VM_BIND_OP_RESTART operation. When VM async bind work is restarted, the |
| 119 | * first operation processed is the operation that caused the original error. | 119 | * first operation processed is the operation that caused the original error. |
| @@ -193,7 +193,7 @@ · 73 unmodified lines | |||
| 193 | * In a VM is in fault mode (TODO: link to fault mode), new bind operations that | 193 | * In a VM is in fault mode (TODO: link to fault mode), new bind operations that |
| 194 | * create mappings are by default are deferred to the page fault handler (first | 194 | * create mappings are by default are deferred to the page fault handler (first |
| 195 | * use). This behavior can be overriden by setting the flag | 195 | * use). This behavior can be overriden by setting the flag |
| 196 | * XE_VM_BIND_FLAG_IMMEDIATE which indicates to creating the mapping | 196 | * DRM_XE_VM_BIND_FLAG_IMMEDIATE which indicates to creating the mapping |
| 197 | * immediately. | 197 | * immediately. |
| 198 | * | 198 | * |
| 199 | * User pointer | 199 | * User pointer |
| @@ -322,7 +322,7 @@ · 122 unmodified lines | |||
| 322 | * | 322 | * |
| 323 | * By default, on a faulting VM binds just allocate the VMA and the actual | 323 | * By default, on a faulting VM binds just allocate the VMA and the actual |
| 324 | * updating of the page tables is defered to the page fault handler. This | 324 | * updating of the page tables is defered to the page fault handler. This |
| 325 | * behavior can be overridden by setting the flag XE_VM_BIND_FLAG_IMMEDIATE in | 325 | * behavior can be overridden by setting the flag DRM_XE_VM_BIND_FLAG_IMMEDIATE in |
| 326 | * the VM bind which will then do the bind immediately. | 326 | * the VM bind which will then do the bind immediately. |
| 327 | * | 327 | * |
| 328 | * Page fault handler | 328 | * Page fault handler |
| @@ -19,12 +19,12 @@ extern "C" { · 18 unmodified lines | |||
| 19 | /** | 19 | /** |
| 20 | * DOC: uevent generated by xe on it's pci node. | 20 | * DOC: uevent generated by xe on it's pci node. |
| 21 | * | 21 | * |
| 22 | * XE_RESET_FAILED_UEVENT - Event is generated when attempt to reset gt | 22 | * DRM_XE_RESET_FAILED_UEVENT - Event is generated when attempt to reset gt |
| 23 | * fails. The value supplied with the event is always "NEEDS_RESET". | 23 | * fails. The value supplied with the event is always "NEEDS_RESET". |
| 24 | * Additional information supplied is tile id and gt id of the gt unit for | 24 | * Additional information supplied is tile id and gt id of the gt unit for |
| 25 | * which reset has failed. | 25 | * which reset has failed. |
| 26 | */ | 26 | */ |
| 27 | #define XE_RESET_FAILED_UEVENT "DEVICE_STATUS" | 27 | #define DRM_XE_RESET_FAILED_UEVENT "DEVICE_STATUS" |
| 28 | 28 | ||
| 29 | /** | 29 | /** |
| 30 | * struct xe_user_extension - Base class for defining a chain of extensions | 30 | * struct xe_user_extension - Base class for defining a chain of extensions |
| @@ -148,14 +148,14 @@ struct drm_xe_engine_class_instance { · 117 unmodified lines | |||
| 148 | * enum drm_xe_memory_class - Supported memory classes. | 148 | * enum drm_xe_memory_class - Supported memory classes. |
| 149 | */ | 149 | */ |
| 150 | enum drm_xe_memory_class { | 150 | enum drm_xe_memory_class { |
| 151 | /** @XE_MEM_REGION_CLASS_SYSMEM: Represents system memory. */ | 151 | /** @DRM_XE_MEM_REGION_CLASS_SYSMEM: Represents system memory. */ |
| 152 | XE_MEM_REGION_CLASS_SYSMEM = 0, | 152 | DRM_XE_MEM_REGION_CLASS_SYSMEM = 0, |
| 153 | /** | 153 | /** |
| 154 | * @XE_MEM_REGION_CLASS_VRAM: On discrete platforms, this | 154 | * @DRM_XE_MEM_REGION_CLASS_VRAM: On discrete platforms, this |
| 155 | * represents the memory that is local to the device, which we | 155 | * represents the memory that is local to the device, which we |
| 156 | * call VRAM. Not valid on integrated platforms. | 156 | * call VRAM. Not valid on integrated platforms. |
| 157 | */ | 157 | */ |
| 158 | XE_MEM_REGION_CLASS_VRAM | 158 | DRM_XE_MEM_REGION_CLASS_VRAM |
| 159 | }; | 159 | }; |
| 160 | 160 | ||
| 161 | /** | 161 | /** |
| @@ -215,7 +215,7 @@ struct drm_xe_query_mem_region { · 53 unmodified lines | |||
| 215 | * always equal the @total_size, since all of it will be CPU | 215 | * always equal the @total_size, since all of it will be CPU |
| 216 | * accessible. | 216 | * accessible. |
| 217 | * | 217 | * |
| 218 | * Note this is only tracked for XE_MEM_REGION_CLASS_VRAM | 218 | * Note this is only tracked for DRM_XE_MEM_REGION_CLASS_VRAM |
| 219 | * regions (for other types the value here will always equal | 219 | * regions (for other types the value here will always equal |
| 220 | * zero). | 220 | * zero). |
| 221 | */ | 221 | */ |
| @@ -227,7 +227,7 @@ struct drm_xe_query_mem_region { · 5 unmodified lines | |||
| 227 | * Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable | 227 | * Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable |
| 228 | * accounting. Without this the value here will always equal | 228 | * accounting. Without this the value here will always equal |
| 229 | * zero. Note this is only currently tracked for | 229 | * zero. Note this is only currently tracked for |
| 230 | * XE_MEM_REGION_CLASS_VRAM regions (for other types the value | 230 | * DRM_XE_MEM_REGION_CLASS_VRAM regions (for other types the value |
| 231 | * here will always be zero). | 231 | * here will always be zero). |
| 232 | */ | 232 | */ |
| 233 | __u64 cpu_visible_used; | 233 | __u64 cpu_visible_used; |
| @@ -320,12 +320,12 @@ struct drm_xe_query_config { · 86 unmodified lines | |||
| 320 | /** @pad: MBZ */ | 320 | /** @pad: MBZ */ |
| 321 | __u32 pad; | 321 | __u32 pad; |
| 322 | 322 | ||
| 323 | #define XE_QUERY_CONFIG_REV_AND_DEVICE_ID 0 | 323 | #define DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID 0 |
| 324 | #define XE_QUERY_CONFIG_FLAGS 1 | 324 | #define DRM_XE_QUERY_CONFIG_FLAGS 1 |
| 325 | #define XE_QUERY_CONFIG_FLAGS_HAS_VRAM (0x1 << 0) | 325 | #define DRM_XE_QUERY_CONFIG_FLAGS_HAS_VRAM (0x1 << 0) |
| 326 | #define XE_QUERY_CONFIG_MIN_ALIGNMENT 2 | 326 | #define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT 2 |
| 327 | #define XE_QUERY_CONFIG_VA_BITS 3 | 327 | #define DRM_XE_QUERY_CONFIG_VA_BITS 3 |
| 328 | #define XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY 4 | 328 | #define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY 4 |
| 329 | /** @info: array of elements containing the config info */ | 329 | /** @info: array of elements containing the config info */ |
| 330 | __u64 info[]; | 330 | __u64 info[]; |
| 331 | }; | 331 | }; |
| @@ -339,8 +339,8 @@ struct drm_xe_query_config { · 7 unmodified lines | |||
| 339 | * implementing graphics and/or media operations. | 339 | * implementing graphics and/or media operations. |
| 340 | */ | 340 | */ |
| 341 | struct drm_xe_query_gt { | 341 | struct drm_xe_query_gt { |
| 342 | #define XE_QUERY_GT_TYPE_MAIN 0 | 342 | #define DRM_XE_QUERY_GT_TYPE_MAIN 0 |
| 343 | #define XE_QUERY_GT_TYPE_MEDIA 1 | 343 | #define DRM_XE_QUERY_GT_TYPE_MEDIA 1 |
| 344 | /** @type: GT type: Main or Media */ | 344 | /** @type: GT type: Main or Media */ |
| 345 | __u16 type; | 345 | __u16 type; |
| 346 | /** @gt_id: Unique ID of this GT within the PCI Device */ | 346 | /** @gt_id: Unique ID of this GT within the PCI Device */ |
| @@ -400,7 +400,7 @@ struct drm_xe_query_topology_mask { · 53 unmodified lines | |||
| 400 | * DSS_GEOMETRY ff ff ff ff 00 00 00 00 | 400 | * DSS_GEOMETRY ff ff ff ff 00 00 00 00 |
| 401 | * means 32 DSS are available for geometry. | 401 | * means 32 DSS are available for geometry. |
| 402 | */ | 402 | */ |
| 403 | #define XE_TOPO_DSS_GEOMETRY (1 << 0) | 403 | #define DRM_XE_TOPO_DSS_GEOMETRY (1 << 0) |
| 404 | /* | 404 | /* |
| 405 | * To query the mask of Dual Sub Slices (DSS) available for compute | 405 | * To query the mask of Dual Sub Slices (DSS) available for compute |
| 406 | * operations. For example a query response containing the following | 406 | * operations. For example a query response containing the following |
| @@ -408,7 +408,7 @@ struct drm_xe_query_topology_mask { · 1 unmodified line | |||
| 408 | * DSS_COMPUTE ff ff ff ff 00 00 00 00 | 408 | * DSS_COMPUTE ff ff ff ff 00 00 00 00 |
| 409 | * means 32 DSS are available for compute. | 409 | * means 32 DSS are available for compute. |
| 410 | */ | 410 | */ |
| 411 | #define XE_TOPO_DSS_COMPUTE (1 << 1) | 411 | #define DRM_XE_TOPO_DSS_COMPUTE (1 << 1) |
| 412 | /* | 412 | /* |
| 413 | * To query the mask of Execution Units (EU) available per Dual Sub | 413 | * To query the mask of Execution Units (EU) available per Dual Sub |
| 414 | * Slices (DSS). For example a query response containing the following | 414 | * Slices (DSS). For example a query response containing the following |
| @@ -416,7 +416,7 @@ struct drm_xe_query_topology_mask { · 1 unmodified line | |||
| 416 | * EU_PER_DSS ff ff 00 00 00 00 00 00 | 416 | * EU_PER_DSS ff ff 00 00 00 00 00 00 |
| 417 | * means each DSS has 16 EU. | 417 | * means each DSS has 16 EU. |
| 418 | */ | 418 | */ |
| 419 | #define XE_TOPO_EU_PER_DSS (1 << 2) | 419 | #define DRM_XE_TOPO_EU_PER_DSS (1 << 2) |
| 420 | /** @type: type of mask */ | 420 | /** @type: type of mask */ |
| 421 | __u16 type; | 421 | __u16 type; |
| 422 | 422 | ||
| @@ -497,8 +497,8 @@ struct drm_xe_gem_create { · 74 unmodified lines | |||
| 497 | */ | 497 | */ |
| 498 | __u64 size; | 498 | __u64 size; |
| 499 | 499 | ||
| 500 | #define XE_GEM_CREATE_FLAG_DEFER_BACKING (0x1 << 24) | 500 | #define DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING (0x1 << 24) |
| 501 | #define XE_GEM_CREATE_FLAG_SCANOUT (0x1 << 25) | 501 | #define DRM_XE_GEM_CREATE_FLAG_SCANOUT (0x1 << 25) |
| 502 | /* | 502 | /* |
| 503 | * When using VRAM as a possible placement, ensure that the corresponding VRAM | 503 | * When using VRAM as a possible placement, ensure that the corresponding VRAM |
| 504 | * allocation will always use the CPU accessible part of VRAM. This is important | 504 | * allocation will always use the CPU accessible part of VRAM. This is important |
| @@ -514,7 +514,7 @@ struct drm_xe_gem_create { · 9 unmodified lines | |||
| 514 | * display surfaces, therefore the kernel requires setting this flag for such | 514 | * display surfaces, therefore the kernel requires setting this flag for such |
| 515 | * objects, otherwise an error is thrown on small-bar systems. | 515 | * objects, otherwise an error is thrown on small-bar systems. |
| 516 | */ | 516 | */ |
| 517 | #define XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM (0x1 << 26) | 517 | #define DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM (0x1 << 26) |
| 518 | /** | 518 | /** |
| 519 | * @flags: Flags, currently a mask of memory instances of where BO can | 519 | * @flags: Flags, currently a mask of memory instances of where BO can |
| 520 | * be placed | 520 | * be placed |
| @@ -581,14 +581,14 @@ struct drm_xe_ext_set_property { · 60 unmodified lines | |||
| 581 | }; | 581 | }; |
| 582 | 582 | ||
| 583 | struct drm_xe_vm_create { | 583 | struct drm_xe_vm_create { |
| 584 | #define XE_VM_EXTENSION_SET_PROPERTY 0 | 584 | #define DRM_XE_VM_EXTENSION_SET_PROPERTY 0 |
| 585 | /** @extensions: Pointer to the first extension struct, if any */ | 585 | /** @extensions: Pointer to the first extension struct, if any */ |
| 586 | __u64 extensions; | 586 | __u64 extensions; |
| 587 | 587 | ||
| 588 | #define DRM_XE_VM_CREATE_SCRATCH_PAGE (0x1 << 0) | 588 | #define DRM_XE_VM_CREATE_SCRATCH_PAGE (0x1 << 0) |
| 589 | #define DRM_XE_VM_CREATE_COMPUTE_MODE (0x1 << 1) | 589 | #define DRM_XE_VM_CREATE_COMPUTE_MODE (0x1 << 1) |
| 590 | #define DRM_XE_VM_CREATE_ASYNC_DEFAULT (0x1 << 2) | 590 | #define DRM_XE_VM_CREATE_ASYNC_DEFAULT (0x1 << 2) |
| 591 | #define DRM_XE_VM_CREATE_FAULT_MODE (0x1 << 3) | 591 | #define DRM_XE_VM_CREATE_FAULT_MODE (0x1 << 3) |
| 592 | /** @flags: Flags */ | 592 | /** @flags: Flags */ |
| 593 | __u32 flags; | 593 | __u32 flags; |
| 594 | 594 | ||
| @@ -644,29 +644,29 @@ struct drm_xe_vm_bind_op { · 49 unmodified lines | |||
| 644 | */ | 644 | */ |
| 645 | __u64 tile_mask; | 645 | __u64 tile_mask; |
| 646 | 646 | ||
| 647 | #define XE_VM_BIND_OP_MAP 0x0 | 647 | #define DRM_XE_VM_BIND_OP_MAP 0x0 |
| 648 | #define XE_VM_BIND_OP_UNMAP 0x1 | 648 | #define DRM_XE_VM_BIND_OP_UNMAP 0x1 |
| 649 | #define XE_VM_BIND_OP_MAP_USERPTR 0x2 | 649 | #define DRM_XE_VM_BIND_OP_MAP_USERPTR 0x2 |
| 650 | #define XE_VM_BIND_OP_UNMAP_ALL 0x3 | 650 | #define DRM_XE_VM_BIND_OP_UNMAP_ALL 0x3 |
| 651 | #define XE_VM_BIND_OP_PREFETCH 0x4 | 651 | #define DRM_XE_VM_BIND_OP_PREFETCH 0x4 |
| 652 | /** @op: Bind operation to perform */ | 652 | /** @op: Bind operation to perform */ |
| 653 | __u32 op; | 653 | __u32 op; |
| 654 | 654 | ||
| 655 | #define XE_VM_BIND_FLAG_READONLY (0x1 << 0) | 655 | #define DRM_XE_VM_BIND_FLAG_READONLY (0x1 << 0) |
| 656 | #define XE_VM_BIND_FLAG_ASYNC (0x1 << 1) | 656 | #define DRM_XE_VM_BIND_FLAG_ASYNC (0x1 << 1) |
| 657 | /* | 657 | /* |
| 658 | * Valid on a faulting VM only, do the MAP operation immediately rather | 658 | * Valid on a faulting VM only, do the MAP operation immediately rather |
| 659 | * than deferring the MAP to the page fault handler. | 659 | * than deferring the MAP to the page fault handler. |
| 660 | */ | 660 | */ |
| 661 | #define XE_VM_BIND_FLAG_IMMEDIATE (0x1 << 2) | 661 | #define DRM_XE_VM_BIND_FLAG_IMMEDIATE (0x1 << 2) |
| 662 | /* | 662 | /* |
| 663 | * When the NULL flag is set, the page tables are setup with a special | 663 | * When the NULL flag is set, the page tables are setup with a special |
| 664 | * bit which indicates writes are dropped and all reads return zero. In | 664 | * bit which indicates writes are dropped and all reads return zero. In |
| 665 | * the future, the NULL flags will only be valid for XE_VM_BIND_OP_MAP | 665 | * the future, the NULL flags will only be valid for DRM_XE_VM_BIND_OP_MAP |
| 666 | * operations, the BO handle MBZ, and the BO offset MBZ. This flag is | 666 | * operations, the BO handle MBZ, and the BO offset MBZ. This flag is |
| 667 | * intended to implement VK sparse bindings. | 667 | * intended to implement VK sparse bindings. |
| 668 | */ | 668 | */ |
| 669 | #define XE_VM_BIND_FLAG_NULL (0x1 << 3) | 669 | #define DRM_XE_VM_BIND_FLAG_NULL (0x1 << 3) |
| 670 | /** @flags: Bind flags */ | 670 | /** @flags: Bind flags */ |
| 671 | __u32 flags; | 671 | __u32 flags; |
| 672 | 672 | ||
| @@ -721,19 +721,19 @@ struct drm_xe_vm_bind { · 48 unmodified lines | |||
| 721 | __u64 reserved[2]; | 721 | __u64 reserved[2]; |
| 722 | }; | 722 | }; |
| 723 | 723 | ||
| 724 | /* For use with XE_EXEC_QUEUE_SET_PROPERTY_ACC_GRANULARITY */ | 724 | /* For use with DRM_XE_EXEC_QUEUE_SET_PROPERTY_ACC_GRANULARITY */ |
| 725 | 725 | ||
| 726 | /* Monitor 128KB contiguous region with 4K sub-granularity */ | 726 | /* Monitor 128KB contiguous region with 4K sub-granularity */ |
| 727 | #define XE_ACC_GRANULARITY_128K 0 | 727 | #define DRM_XE_ACC_GRANULARITY_128K 0 |
| 728 | 728 | ||
| 729 | /* Monitor 2MB contiguous region with 64KB sub-granularity */ | 729 | /* Monitor 2MB contiguous region with 64KB sub-granularity */ |
| 730 | #define XE_ACC_GRANULARITY_2M 1 | 730 | #define DRM_XE_ACC_GRANULARITY_2M 1 |
| 731 | 731 | ||
| 732 | /* Monitor 16MB contiguous region with 512KB sub-granularity */ | 732 | /* Monitor 16MB contiguous region with 512KB sub-granularity */ |
| 733 | #define XE_ACC_GRANULARITY_16M 2 | 733 | #define DRM_XE_ACC_GRANULARITY_16M 2 |
| 734 | 734 | ||
| 735 | /* Monitor 64MB contiguous region with 2M sub-granularity */ | 735 | /* Monitor 64MB contiguous region with 2M sub-granularity */ |
| 736 | #define XE_ACC_GRANULARITY_64M 3 | 736 | #define DRM_XE_ACC_GRANULARITY_64M 3 |
| 737 | 737 | ||
| 738 | /** | 738 | /** |
| 739 | * struct drm_xe_exec_queue_set_property - exec queue set property | 739 | * struct drm_xe_exec_queue_set_property - exec queue set property |
| @@ -747,14 +747,14 @@ struct drm_xe_exec_queue_set_property { · 7 unmodified lines | |||
| 747 | /** @exec_queue_id: Exec queue ID */ | 747 | /** @exec_queue_id: Exec queue ID */ |
| 748 | __u32 exec_queue_id; | 748 | __u32 exec_queue_id; |
| 749 | 749 | ||
| 750 | #define XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY 0 | 750 | #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY 0 |
| 751 | #define XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE 1 | 751 | #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE 1 |
| 752 | #define XE_EXEC_QUEUE_SET_PROPERTY_PREEMPTION_TIMEOUT 2 | 752 | #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PREEMPTION_TIMEOUT 2 |
| 753 | #define XE_EXEC_QUEUE_SET_PROPERTY_PERSISTENCE 3 | 753 | #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PERSISTENCE 3 |
| 754 | #define XE_EXEC_QUEUE_SET_PROPERTY_JOB_TIMEOUT 4 | 754 | #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_JOB_TIMEOUT 4 |
| 755 | #define XE_EXEC_QUEUE_SET_PROPERTY_ACC_TRIGGER 5 | 755 | #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_ACC_TRIGGER 5 |
| 756 | #define XE_EXEC_QUEUE_SET_PROPERTY_ACC_NOTIFY 6 | 756 | #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_ACC_NOTIFY 6 |
| 757 | #define XE_EXEC_QUEUE_SET_PROPERTY_ACC_GRANULARITY 7 | 757 | #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_ACC_GRANULARITY 7 |
| 758 | /** @property: property to set */ | 758 | /** @property: property to set */ |
| 759 | __u32 property; | 759 | __u32 property; |
| 760 | 760 | ||
| @@ -766,7 +766,7 @@ struct drm_xe_exec_queue_set_property { · 5 unmodified lines | |||
| 766 | }; | 766 | }; |
| 767 | 767 | ||
| 768 | struct drm_xe_exec_queue_create { | 768 | struct drm_xe_exec_queue_create { |
| 769 | #define XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY 0 | 769 | #define DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY 0 |
| 770 | /** @extensions: Pointer to the first extension struct, if any */ | 770 | /** @extensions: Pointer to the first extension struct, if any */ |
| 771 | __u64 extensions; | 771 | __u64 extensions; |
| 772 | 772 | ||
| @@ -805,7 +805,7 @@ struct drm_xe_exec_queue_get_property { · 32 unmodified lines | |||
| 805 | /** @exec_queue_id: Exec queue ID */ | 805 | /** @exec_queue_id: Exec queue ID */ |
| 806 | __u32 exec_queue_id; | 806 | __u32 exec_queue_id; |
| 807 | 807 | ||
| 808 | #define XE_EXEC_QUEUE_GET_PROPERTY_BAN 0 | 808 | #define DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN 0 |
| 809 | /** @property: property to get */ | 809 | /** @property: property to get */ |
| 810 | __u32 property; | 810 | __u32 property; |
| 811 | 811 | ||
| @@ -973,11 +973,11 @@ struct drm_xe_wait_user_fence { · 161 unmodified lines | |||
| 973 | /** | 973 | /** |
| 974 | * DOC: XE PMU event config IDs | 974 | * DOC: XE PMU event config IDs |
| 975 | * | 975 | * |
| 976 | * Check 'man perf_event_open' to use the ID's XE_PMU_XXXX listed in xe_drm.h | 976 | * Check 'man perf_event_open' to use the ID's DRM_XE_PMU_XXXX listed in xe_drm.h |
| 977 | * in 'struct perf_event_attr' as part of perf_event_open syscall to read a | 977 | * in 'struct perf_event_attr' as part of perf_event_open syscall to read a |
| 978 | * particular event. | 978 | * particular event. |
| 979 | * | 979 | * |
| 980 | * For example to open the XE_PMU_RENDER_GROUP_BUSY(0): | 980 | * For example to open the DRMXE_PMU_RENDER_GROUP_BUSY(0): |
| 981 | * | 981 | * |
| 982 | * .. code-block:: C | 982 | * .. code-block:: C |
| 983 | * | 983 | * |
| @@ -991,7 +991,7 @@ struct drm_xe_wait_user_fence { · 7 unmodified lines | |||
| 991 | * attr.read_format = PERF_FORMAT_TOTAL_TIME_ENABLED; | 991 | * attr.read_format = PERF_FORMAT_TOTAL_TIME_ENABLED; |
| 992 | * attr.use_clockid = 1; | 992 | * attr.use_clockid = 1; |
| 993 | * attr.clockid = CLOCK_MONOTONIC; | 993 | * attr.clockid = CLOCK_MONOTONIC; |
| 994 | * attr.config = XE_PMU_RENDER_GROUP_BUSY(0); | 994 | * attr.config = DRM_XE_PMU_RENDER_GROUP_BUSY(0); |
| 995 | * | 995 | * |
| 996 | * fd = syscall(__NR_perf_event_open, &attr, -1, cpu, -1, 0); | 996 | * fd = syscall(__NR_perf_event_open, &attr, -1, cpu, -1, 0); |
| 997 | */ | 997 | */ |
| @@ -999,15 +999,15 @@ struct drm_xe_wait_user_fence { · 1 unmodified line | |||
| 999 | /* | 999 | /* |
| 1000 | * Top bits of every counter are GT id. | 1000 | * Top bits of every counter are GT id. |
| 1001 | */ | 1001 | */ |
| 1002 | #define __XE_PMU_GT_SHIFT (56) | 1002 | #define __DRM_XE_PMU_GT_SHIFT (56) |
| 1003 | 1003 | ||
| 1004 | #define ___XE_PMU_OTHER(gt, x) \ | 1004 | #define ___DRM_XE_PMU_OTHER(gt, x) \ |
| 1005 | (((__u64)(x)) | ((__u64)(gt) << __XE_PMU_GT_SHIFT)) | 1005 | (((__u64)(x)) | ((__u64)(gt) << __DRM_XE_PMU_GT_SHIFT)) |
| 1006 | 1006 | ||
| 1007 | #define XE_PMU_RENDER_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 0) | 1007 | #define DRM_XE_PMU_RENDER_GROUP_BUSY(gt) ___DRM_XE_PMU_OTHER(gt, 0) |
| 1008 | #define XE_PMU_COPY_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 1) | 1008 | #define DRM_XE_PMU_COPY_GROUP_BUSY(gt) ___DRM_XE_PMU_OTHER(gt, 1) |
| 1009 | #define XE_PMU_MEDIA_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 2) | 1009 | #define DRM_XE_PMU_MEDIA_GROUP_BUSY(gt) ___DRM_XE_PMU_OTHER(gt, 2) |
| 1010 | #define XE_PMU_ANY_ENGINE_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 3) | 1010 | #define DRM_XE_PMU_ANY_ENGINE_GROUP_BUSY(gt) ___DRM_XE_PMU_OTHER(gt, 3) |
| 1011 | 1011 | ||
| 1012 | #if defined(__cplusplus) | 1012 | #if defined(__cplusplus) |
| 1013 | } | 1013 | } |