This reverts commit 2a027b47dba6 ("MIPS: BCM47XX: Enable 74K Core ExternalSync for PCIe erratum"). Enabling ExternalSync caused a regression for BCM4718A1 (used e.g. in Netgear E3000 and ASUS RT-N16): it simply hangs during PCIe initialization. It's likely that BCM4717A1 is also affected. I didn't notice that earlier as the only BCM47XX devices with PCIe I own are: 1) BCM4706 with 2 x 14e4:4331 2) BCM4706 with 14e4:4360 and 14e4:4331 it appears that BCM4706 is unaffected. While BCM5300X-ES300-RDS.pdf seems to document that erratum and its workarounds (according to quotes provided by Tokunori) it seems not even Broadcom follows them. According to the provided info Broadcom should define CONF7_ES in their SDK's mipsinc.h and implement workaround in the si_mips_init(). Checking both didn't reveal such code. It *could* mean Broadcom also had some problems with the given workaround.
Unified · Split
| @@ -212,12 +212,6 @@ static int __init bcm47xx_cpu_fixes(void) · 211 unmodified lines | |||
| 212 | */ | 212 | */ |
| 213 | if (bcm47xx_bus.bcma.bus.chipinfo.id == BCMA_CHIP_ID_BCM4706) | 213 | if (bcm47xx_bus.bcma.bus.chipinfo.id == BCMA_CHIP_ID_BCM4706) |
| 214 | cpu_wait = NULL; | 214 | cpu_wait = NULL; |
| 215 | |||
| 216 | /* | ||
| 217 | * BCM47XX Erratum "R10: PCIe Transactions Periodically Fail" | ||
| 218 | * Enable ExternalSync for sync instruction to take effect | ||
| 219 | */ | ||
| 220 | set_c0_config7(MIPS_CONF7_ES); | ||
| 221 | break; | 215 | break; |
| 222 | #endif | 216 | #endif |
| 223 | } | 217 | } |
| @@ -681,8 +681,6 @@ · 680 unmodified lines | |||
| 681 | #define MIPS_CONF7_WII (_ULCAST_(1) << 31) | 681 | #define MIPS_CONF7_WII (_ULCAST_(1) << 31) |
| 682 | 682 | ||
| 683 | #define MIPS_CONF7_RPS (_ULCAST_(1) << 2) | 683 | #define MIPS_CONF7_RPS (_ULCAST_(1) << 2) |
| 684 | /* ExternalSync */ | ||
| 685 | #define MIPS_CONF7_ES (_ULCAST_(1) << 8) | ||
| 686 | 684 | ||
| 687 | #define MIPS_CONF7_IAR (_ULCAST_(1) << 10) | 685 | #define MIPS_CONF7_IAR (_ULCAST_(1) << 10) |
| 688 | #define MIPS_CONF7_AR (_ULCAST_(1) << 16) | 686 | #define MIPS_CONF7_AR (_ULCAST_(1) << 16) |
| @@ -2767,7 +2765,6 @@ __BUILD_SET_C0(status) · 2078 unmodified lines | |||
| 2767 | __BUILD_SET_C0(cause) | 2765 | __BUILD_SET_C0(cause) |
| 2768 | __BUILD_SET_C0(config) | 2766 | __BUILD_SET_C0(config) |
| 2769 | __BUILD_SET_C0(config5) | 2767 | __BUILD_SET_C0(config5) |
| 2770 | __BUILD_SET_C0(config7) | ||
| 2771 | __BUILD_SET_C0(intcontrol) | 2768 | __BUILD_SET_C0(intcontrol) |
| 2772 | __BUILD_SET_C0(intctl) | 2769 | __BUILD_SET_C0(intctl) |
| 2773 | __BUILD_SET_C0(srsmap) | 2770 | __BUILD_SET_C0(srsmap) |