PCI: Add support for Immediate Readiness

PCIe r4.0, sec 7.5.1.1.4 defines a new bit in the Status Register: Immediate Readiness – This optional bit, when Set, indicates the Function is guaranteed to be ready to successfully complete valid configuration accesses at any time following any reset that the host is capable of issuing Configuration Requests to this Function. When this bit is Set, for accesses to this Function, software is exempt from all requirements to delay configuration accesses following any type of reset, including but not limited to the timing requirements defined in Section 6.6. This means that all delays after a Conventional or Function Reset can be skipped. This patch reads such bit and caches its value in a flag inside struct pci_dev to be checked later if we should delay or can skip delays after a reset. While at that, also move the explicit msleep(100) call from pcie_flr() and pci_af_flr() to pci_dev_wait().

Felipe Balbi committed 8 years ago

Commit d6112f81 parent bad7dcd3 files · +14 −1Browse files

Unified · Split

3 files

drivers/pci/pci.c +12 −1
include/linux/pci.h +1 −0
include/uapi/linux/pci_regs.h +1 −0

drivers/pci/pci.c+12−1

 		 * because have already delayed for the bridge.
 		 */
 		if (dev->runtime_d3cold) {
-			if (dev->d3cold_delay)
+			if (dev->d3cold_delay && !dev->imm_ready)
 				msleep(dev->d3cold_delay);
 			/*
 			 * When powering on a bridge from D3cold, the
 void pci_pm_init(struct pci_dev *dev)
 {
 	int pm;
+	u16 status;
 	u16 pmc;
 	pm_runtime_forbid(&dev->dev);
 		/* Disable the PME# generation functionality */
 		pci_pme_active(dev, false);
 	}
+	pci_read_config_word(dev, PCI_STATUS, &status);
+	if (status & PCI_STATUS_IMM_READY)
+		dev->imm_ready = 1;
 }
 static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop)
 	pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
+	if (dev->imm_ready)
+		return 0;
 	/*
 	 * Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within
 	 * 100ms, but may silently discard requests while the FLR is in
 	pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
+	if (dev->imm_ready)
+		return 0;
 	/*
 	 * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006,
 	 * updated 27 July 2006; a device must complete an FLR within

include/linux/pci.h+1−0

@@ -325,6 +325,7 @@ struct pci_dev { · 324 unmodified lines
325	pci_power_t current_state; /* Current operating state. In ACPI,	325	pci_power_t current_state; /* Current operating state. In ACPI,
326	this is D0-D3, D0 being fully	326	this is D0-D3, D0 being fully
327	functional, and D3 being off. */	327	functional, and D3 being off. */
		328	unsigned int imm_ready:1; /* Supports Immediate Readiness */
328	u8 pm_cap; /* PM capability offset */	329	u8 pm_cap; /* PM capability offset */
329	unsigned int pme_support:5; /* Bitmask of states from which PME#	330	unsigned int pme_support:5; /* Bitmask of states from which PME#
330	can be generated */	331	can be generated */

include/uapi/linux/pci_regs.h+1−0

@@ -52,6 +52,7 @@ · 51 unmodified lines
52	#define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */	52	#define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
53		53
54	#define PCI_STATUS 0x06 /* 16 bits */	54	#define PCI_STATUS 0x06 /* 16 bits */
		55	#define PCI_STATUS_IMM_READY 0x01 /* Immediate Readiness */
55	#define PCI_STATUS_INTERRUPT 0x08 /* Interrupt status */	56	#define PCI_STATUS_INTERRUPT 0x08 /* Interrupt status */
56	#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */	57	#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
57	#define PCI_STATUS_66MHZ 0x20 /* Support 66 MHz PCI 2.1 bus */	58	#define PCI_STATUS_66MHZ 0x20 /* Support 66 MHz PCI 2.1 bus */

PCI: Add support for Immediate Readiness

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