lael-labs/linux

Documentation/admin-guide/devices.txt+2−2

@@ -2693,8 +2693,8 @@ · 2692 unmodified lines
2693	41 = /dev/ttySMX0 Motorola i.MX - port 0	2693	41 = /dev/ttySMX0 Motorola i.MX - port 0
2694	42 = /dev/ttySMX1 Motorola i.MX - port 1	2694	42 = /dev/ttySMX1 Motorola i.MX - port 1
2695	43 = /dev/ttySMX2 Motorola i.MX - port 2	2695	43 = /dev/ttySMX2 Motorola i.MX - port 2
2696	44 = /dev/ttyMM0 Marvell MPSC - port 0	2696	44 = /dev/ttyMM0 Marvell MPSC - port 0 (obsolete unused)
2697	45 = /dev/ttyMM1 Marvell MPSC - port 1	2697	45 = /dev/ttyMM1 Marvell MPSC - port 1 (obsolete unused)
2698	46 = /dev/ttyCPM0 PPC CPM (SCC or SMC) - port 0	2698	46 = /dev/ttyCPM0 PPC CPM (SCC or SMC) - port 0
2699	...	2699	...
2700	47 = /dev/ttyCPM5 PPC CPM (SCC or SMC) - port 5	2700	47 = /dev/ttyCPM5 PPC CPM (SCC or SMC) - port 5

Documentation/devicetree/bindings/serial/8250.txt+19−0

@@ -53,6 +53,9 @@ Optional properties: · 52 unmodified lines
53	programmable TX FIFO thresholds.	53	programmable TX FIFO thresholds.
54	- resets : phandle + reset specifier pairs	54	- resets : phandle + reset specifier pairs
55	- overrun-throttle-ms : how long to pause uart rx when input overrun is encountered.	55	- overrun-throttle-ms : how long to pause uart rx when input overrun is encountered.
		56	- {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD
		57	line respectively. It will use specified GPIO instead of the peripheral
		58	function pin for the UART feature. If unsure, don't specify this property.
56		59
57	Note:	60	Note:
58	* fsl,ns16550:	61	* fsl,ns16550:
@@ -74,3 +77,19 @@ Example: · 15 unmodified lines
74	interrupts = <10>;	77	interrupts = <10>;
75	reg-shift = <2>;	78	reg-shift = <2>;
76	};	79	};
		80
		81	Example for OMAP UART using GPIO-based modem control signals:
		82
		83	uart4: serial@49042000 {
		84	compatible = "ti,omap3-uart";
		85	reg = <0x49042000 0x400>;
		86	interrupts = <80>;
		87	ti,hwmods = "uart4";
		88	clock-frequency = <48000000>;
		89	cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
		90	rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
		91	dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
		92	dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
		93	dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
		94	rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
		95	};

arch/ia64/hp/sim/simserial.c+0−2

@@ -324,8 +324,6 @@ static int rs_ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg) · 323 unmodified lines
324	return -ENOIOCTLCMD;	324	return -ENOIOCTLCMD;
325	}	325	}
326		326
327	#define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK\|BRKINT\|IGNPAR\|PARMRK\|INPCK))
328
329	/*	327	/*
330	* This routine will shutdown a serial port; interrupts are disabled, and	328	* This routine will shutdown a serial port; interrupts are disabled, and
331	* DTR is dropped if the hangup on close termio flag is on.	329	* DTR is dropped if the hangup on close termio flag is on.

drivers/ipack/devices/ipoctal.h+0−1

@@ -15,7 +15,6 @@ · 14 unmodified lines
15	#define NR_CHANNELS 8	15	#define NR_CHANNELS 8
16	#define IPOCTAL_MAX_BOARDS 16	16	#define IPOCTAL_MAX_BOARDS 16
17	#define MAX_DEVICES (NR_CHANNELS * IPOCTAL_MAX_BOARDS)	17	#define MAX_DEVICES (NR_CHANNELS * IPOCTAL_MAX_BOARDS)
18	#define RELEVANT_IFLAG(iflag) ((iflag) & (IGNBRK\|BRKINT\|IGNPAR\|PARMRK\|INPCK))
19		18
20	/**	19	/**
21	* struct ipoctal_stats -- Stats since last reset	20	* struct ipoctal_stats -- Stats since last reset

drivers/tty/serial/8250/8250.h+89−1

@@ -11,6 +11,8 @@ · 10 unmodified lines
11	#include <linux/serial_reg.h>	11	#include <linux/serial_reg.h>
12	#include <linux/dmaengine.h>	12	#include <linux/dmaengine.h>
13		13
		14	#include "../serial_mctrl_gpio.h"
		15
14	struct uart_8250_dma {	16	struct uart_8250_dma {
15	int (tx_dma)(struct uart_8250_port p);	17	int (tx_dma)(struct uart_8250_port p);
16	int (rx_dma)(struct uart_8250_port p);	18	int (rx_dma)(struct uart_8250_port p);
@@ -128,6 +130,24 @@ static inline void serial_dl_write(struct uart_8250_port *up, int value) · 111 unmodified lines
128	up->dl_write(up, value);	130	up->dl_write(up, value);
129	}	131	}
130		132
		133	static inline bool serial8250_set_THRI(struct uart_8250_port *up)
		134	{
		135	if (up->ier & UART_IER_THRI)
		136	return false;
		137	up->ier \|= UART_IER_THRI;
		138	serial_out(up, UART_IER, up->ier);
		139	return true;
		140	}
		141
		142	static inline bool serial8250_clear_THRI(struct uart_8250_port *up)
		143	{
		144	if (!(up->ier & UART_IER_THRI))
		145	return false;
		146	up->ier &= ~UART_IER_THRI;
		147	serial_out(up, UART_IER, up->ier);
		148	return true;
		149	}
		150
131	struct uart_8250_port *serial8250_get_port(int line);	151	struct uart_8250_port *serial8250_get_port(int line);
132		152
133	void serial8250_rpm_get(struct uart_8250_port *p);	153	void serial8250_rpm_get(struct uart_8250_port *p);
@@ -139,14 +159,82 @@ void serial8250_rpm_put_tx(struct uart_8250_port *p); · 5 unmodified lines
139	int serial8250_em485_init(struct uart_8250_port *p);	159	int serial8250_em485_init(struct uart_8250_port *p);
140	void serial8250_em485_destroy(struct uart_8250_port *p);	160	void serial8250_em485_destroy(struct uart_8250_port *p);
141		161
		162	/* MCR <-> TIOCM conversion */
		163	static inline int serial8250_TIOCM_to_MCR(int tiocm)
		164	{
		165	int mcr = 0;
		166
		167	if (tiocm & TIOCM_RTS)
		168	mcr \|= UART_MCR_RTS;
		169	if (tiocm & TIOCM_DTR)
		170	mcr \|= UART_MCR_DTR;
		171	if (tiocm & TIOCM_OUT1)
		172	mcr \|= UART_MCR_OUT1;
		173	if (tiocm & TIOCM_OUT2)
		174	mcr \|= UART_MCR_OUT2;
		175	if (tiocm & TIOCM_LOOP)
		176	mcr \|= UART_MCR_LOOP;
		177
		178	return mcr;
		179	}
		180
		181	static inline int serial8250_MCR_to_TIOCM(int mcr)
		182	{
		183	int tiocm = 0;
		184
		185	if (mcr & UART_MCR_RTS)
		186	tiocm \|= TIOCM_RTS;
		187	if (mcr & UART_MCR_DTR)
		188	tiocm \|= TIOCM_DTR;
		189	if (mcr & UART_MCR_OUT1)
		190	tiocm \|= TIOCM_OUT1;
		191	if (mcr & UART_MCR_OUT2)
		192	tiocm \|= TIOCM_OUT2;
		193	if (mcr & UART_MCR_LOOP)
		194	tiocm \|= TIOCM_LOOP;
		195
		196	return tiocm;
		197	}
		198
		199	/* MSR <-> TIOCM conversion */
		200	static inline int serial8250_MSR_to_TIOCM(int msr)
		201	{
		202	int tiocm = 0;
		203
		204	if (msr & UART_MSR_DCD)
		205	tiocm \|= TIOCM_CAR;
		206	if (msr & UART_MSR_RI)
		207	tiocm \|= TIOCM_RNG;
		208	if (msr & UART_MSR_DSR)
		209	tiocm \|= TIOCM_DSR;
		210	if (msr & UART_MSR_CTS)
		211	tiocm \|= TIOCM_CTS;
		212
		213	return tiocm;
		214	}
		215
142	static inline void serial8250_out_MCR(struct uart_8250_port *up, int value)	216	static inline void serial8250_out_MCR(struct uart_8250_port *up, int value)
143	{	217	{
144	serial_out(up, UART_MCR, value);	218	serial_out(up, UART_MCR, value);
		219
		220	if (up->gpios)
		221	mctrl_gpio_set(up->gpios, serial8250_MCR_to_TIOCM(value));
145	}	222	}
146		223
147	static inline int serial8250_in_MCR(struct uart_8250_port *up)	224	static inline int serial8250_in_MCR(struct uart_8250_port *up)
148	{	225	{
149	return serial_in(up, UART_MCR);	226	int mctrl;
		227
		228	mctrl = serial_in(up, UART_MCR);
		229
		230	if (up->gpios) {
		231	unsigned int mctrl_gpio = 0;
		232
		233	mctrl_gpio = mctrl_gpio_get_outputs(up->gpios, &mctrl_gpio);
		234	mctrl \|= serial8250_TIOCM_to_MCR(mctrl_gpio);
		235	}
		236
		237	return mctrl;
150	}	238	}
151		239
152	#if defined(__alpha__) && !defined(CONFIG_PCI)	240	#if defined(__alpha__) && !defined(CONFIG_PCI)

drivers/tty/serial/8250/8250_core.c+20−0

  *	      serial8250_register_8250_port() ports
  */
+#include <linux/acpi.h>
 #include <linux/module.h>
 #include <linux/moduleparam.h>
 #include <linux/ioport.h>
 	uart = serial8250_find_match_or_unused(&up->port);
 	if (uart && uart->port.type != PORT_8250_CIR) {
+		struct mctrl_gpios *gpios;
 		if (uart->port.dev)
 			uart_remove_one_port(&serial8250_reg, &uart->port);
 		if (up->port.flags & UPF_FIXED_TYPE)
 			uart->port.type = up->port.type;
+		/*
+		 * Only call mctrl_gpio_init(), if the device has no ACPI
+		 * companion device
+		 */
+		if (!has_acpi_companion(uart->port.dev)) {
+			gpios = mctrl_gpio_init(&uart->port, 0);
+			if (IS_ERR(gpios)) {
+				if (PTR_ERR(gpios) != -ENOSYS) {
+					ret = PTR_ERR(gpios);
+					goto out_unlock;
+				}
+			} else {
+				uart->gpios = gpios;
+			}
+		}
 		serial8250_set_defaults(uart);
 		/* Possibly override default I/O functions.  */
 		}
 	}
+out_unlock:
 	mutex_unlock(&serial_mutex);
 	return ret;

drivers/tty/serial/8250/8250_dma.c+3−8

 		uart_write_wakeup(&p->port);
 	ret = serial8250_tx_dma(p);
-	if (ret) {
+	if (ret)
-		p->ier |= UART_IER_THRI;
+		serial8250_set_THRI(p);
-		serial_port_out(&p->port, UART_IER, p->ier);
-	}
 	spin_unlock_irqrestore(&p->port.lock, flags);
 }
 	dma_async_issue_pending(dma->txchan);
 	if (dma->tx_err) {
 		dma->tx_err = 0;
-		if (p->ier & UART_IER_THRI) {
+		serial8250_clear_THRI(p);
-			p->ier &= ~UART_IER_THRI;
-			serial_out(p, UART_IER, p->ier);
-		}
 	}
 	return 0;
 err:

drivers/tty/serial/8250/8250_mtk.c+44−29

@@ -10,6 +10,7 @@ · 9 unmodified lines
10	#include <linux/module.h>	10	#include <linux/module.h>
11	#include <linux/of_irq.h>	11	#include <linux/of_irq.h>
12	#include <linux/of_platform.h>	12	#include <linux/of_platform.h>
		13	#include <linux/pinctrl/consumer.h>
13	#include <linux/platform_device.h>	14	#include <linux/platform_device.h>
14	#include <linux/pm_runtime.h>	15	#include <linux/pm_runtime.h>
15	#include <linux/serial_8250.h>	16	#include <linux/serial_8250.h>
@@ -47,7 +48,6 @@ · 31 unmodified lines
47	#define MTK_UART_DMA_EN_RX 0x5	48	#define MTK_UART_DMA_EN_RX 0x5
48		49
49	#define MTK_UART_ESCAPE_CHAR 0x77 /* Escape char added under sw fc */	50	#define MTK_UART_ESCAPE_CHAR 0x77 /* Escape char added under sw fc */
50	#define MTK_UART_TX_SIZE UART_XMIT_SIZE
51	#define MTK_UART_RX_SIZE 0x8000	51	#define MTK_UART_RX_SIZE 0x8000
52	#define MTK_UART_TX_TRIGGER 1	52	#define MTK_UART_TX_TRIGGER 1
53	#define MTK_UART_RX_TRIGGER MTK_UART_RX_SIZE	53	#define MTK_UART_RX_TRIGGER MTK_UART_RX_SIZE
@@ -70,6 +70,7 @@ struct mtk8250_data { · 16 unmodified lines
70	#ifdef CONFIG_SERIAL_8250_DMA	70	#ifdef CONFIG_SERIAL_8250_DMA
71	enum dma_rx_status rx_status;	71	enum dma_rx_status rx_status;
72	#endif	72	#endif
		73	int rx_wakeup_irq;
73	};	74	};
74		75
75	/* flow control mode */	76	/* flow control mode */
@@ -89,28 +90,30 @@ static void mtk8250_dma_rx_complete(void *param) · 13 unmodified lines
89	struct mtk8250_data *data = up->port.private_data;	90	struct mtk8250_data *data = up->port.private_data;
90	struct tty_port *tty_port = &up->port.state->port;	91	struct tty_port *tty_port = &up->port.state->port;
91	struct dma_tx_state state;	92	struct dma_tx_state state;
		93	int copied, total, cnt;
92	unsigned char *ptr;	94	unsigned char *ptr;
93	int copied;
94		95
95	dma_sync_single_for_cpu(dma->rxchan->device->dev, dma->rx_addr,	96	if (data->rx_status == DMA_RX_SHUTDOWN)
96	dma->rx_size, DMA_FROM_DEVICE);	97	return;
97		98
98	dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);	99	dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
		100	total = dma->rx_size - state.residue;
		101	cnt = total;
99		102
100	if (data->rx_status == DMA_RX_SHUTDOWN)	103	if ((data->rx_pos + cnt) > dma->rx_size)
101	return;	104	cnt = dma->rx_size - data->rx_pos;
102		105
103	if ((data->rx_pos + state.residue) <= dma->rx_size) {	106	ptr = (unsigned char *)(data->rx_pos + dma->rx_buf);
104	ptr = (unsigned char *)(data->rx_pos + dma->rx_buf);	107	copied = tty_insert_flip_string(tty_port, ptr, cnt);
105	copied = tty_insert_flip_string(tty_port, ptr, state.residue);	108	data->rx_pos += cnt;
106	} else {	109
107	ptr = (unsigned char *)(data->rx_pos + dma->rx_buf);	110	if (total > cnt) {
108	copied = tty_insert_flip_string(tty_port, ptr,
109	dma->rx_size - data->rx_pos);
110	ptr = (unsigned char *)(dma->rx_buf);	111	ptr = (unsigned char *)(dma->rx_buf);
111	copied += tty_insert_flip_string(tty_port, ptr,	112	cnt = total - cnt;
112	data->rx_pos + state.residue - dma->rx_size);	113	copied += tty_insert_flip_string(tty_port, ptr, cnt);
		114	data->rx_pos = cnt;
113	}	115	}
		116
114	up->port.icount.rx += copied;	117	up->port.icount.rx += copied;
115		118
116	tty_flip_buffer_push(tty_port);	119	tty_flip_buffer_push(tty_port);
@@ -121,9 +124,7 @@ static void mtk8250_dma_rx_complete(void *param) · 4 unmodified lines
121	static void mtk8250_rx_dma(struct uart_8250_port *up)	124	static void mtk8250_rx_dma(struct uart_8250_port *up)
122	{	125	{
123	struct uart_8250_dma *dma = up->dma;	126	struct uart_8250_dma *dma = up->dma;
124	struct mtk8250_data *data = up->port.private_data;
125	struct dma_async_tx_descriptor *desc;	127	struct dma_async_tx_descriptor *desc;
126	struct dma_tx_state state;
127		128
128	desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,	129	desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
129	dma->rx_size, DMA_DEV_TO_MEM,	130	dma->rx_size, DMA_DEV_TO_MEM,
@@ -138,12 +139,6 @@ static void mtk8250_rx_dma(struct uart_8250_port *up) · 8 unmodified lines
138		139
139	dma->rx_cookie = dmaengine_submit(desc);	140	dma->rx_cookie = dmaengine_submit(desc);
140		141
141	dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
142	data->rx_pos = state.residue;
143
144	dma_sync_single_for_device(dma->rxchan->device->dev, dma->rx_addr,
145	dma->rx_size, DMA_FROM_DEVICE);
146
147	dma_async_issue_pending(dma->rxchan);	142	dma_async_issue_pending(dma->rxchan);
148	}	143	}
149		144
@@ -156,13 +151,11 @@ static void mtk8250_dma_enable(struct uart_8250_port *up) · 6 unmodified lines
156	if (data->rx_status != DMA_RX_START)	151	if (data->rx_status != DMA_RX_START)
157	return;	152	return;
158		153
159	dma->rxconf.direction = DMA_DEV_TO_MEM;	154	dma->rxconf.src_port_window_size = dma->rx_size;
160	dma->rxconf.src_addr_width = dma->rx_size / 1024;	155	dma->rxconf.src_addr = dma->rx_addr;
161	dma->rxconf.src_addr = dma->rx_addr;
162		156
163	dma->txconf.direction = DMA_MEM_TO_DEV;	157	dma->txconf.dst_port_window_size = UART_XMIT_SIZE;
164	dma->txconf.dst_addr_width = MTK_UART_TX_SIZE / 1024;	158	dma->txconf.dst_addr = dma->tx_addr;
165	dma->txconf.dst_addr = dma->tx_addr;
166		159
167	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO \| UART_FCR_CLEAR_RCVR \|	160	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO \| UART_FCR_CLEAR_RCVR \|
168	UART_FCR_CLEAR_XMIT);	161	UART_FCR_CLEAR_XMIT);
@@ -551,6 +544,8 @@ static int mtk8250_probe(struct platform_device *pdev) · 382 unmodified lines
551	pm_runtime_set_active(&pdev->dev);	544	pm_runtime_set_active(&pdev->dev);
552	pm_runtime_enable(&pdev->dev);	545	pm_runtime_enable(&pdev->dev);
553		546
		547	data->rx_wakeup_irq = platform_get_irq(pdev, 1);
		548
554	return 0;	549	return 0;
555	}	550	}
556		551
@@ -572,15 +567,35 @@ static int mtk8250_remove(struct platform_device *pdev) · 15 unmodified lines
572	static int __maybe_unused mtk8250_suspend(struct device *dev)	567	static int __maybe_unused mtk8250_suspend(struct device *dev)
573	{	568	{
574	struct mtk8250_data *data = dev_get_drvdata(dev);	569	struct mtk8250_data *data = dev_get_drvdata(dev);
		570	int irq = data->rx_wakeup_irq;
		571	int err;
575		572
576	serial8250_suspend_port(data->line);	573	serial8250_suspend_port(data->line);
577		574
		575	pinctrl_pm_select_sleep_state(dev);
		576	if (irq >= 0) {
		577	err = enable_irq_wake(irq);
		578	if (err) {
		579	dev_err(dev,
		580	"failed to enable irq wake on IRQ %d: %d\n",
		581	irq, err);
		582	pinctrl_pm_select_default_state(dev);
		583	serial8250_resume_port(data->line);
		584	return err;
		585	}
		586	}
		587
578	return 0;	588	return 0;
579	}	589	}
580		590
581	static int __maybe_unused mtk8250_resume(struct device *dev)	591	static int __maybe_unused mtk8250_resume(struct device *dev)
582	{	592	{
583	struct mtk8250_data *data = dev_get_drvdata(dev);	593	struct mtk8250_data *data = dev_get_drvdata(dev);
		594	int irq = data->rx_wakeup_irq;
		595
		596	if (irq >= 0)
		597	disable_irq_wake(irq);
		598	pinctrl_pm_select_default_state(dev);
584		599
585	serial8250_resume_port(data->line);	600	serial8250_resume_port(data->line);
586		601

drivers/tty/serial/8250/8250_of.c+6−8

 		/* Get clk rate through clk driver if present */
 		info->clk = devm_clk_get(&ofdev->dev, NULL);
 		if (IS_ERR(info->clk)) {
-			dev_warn(&ofdev->dev,
-				"clk or clock-frequency not defined\n");
 			ret = PTR_ERR(info->clk);
+			if (ret != -EPROBE_DEFER)
+				dev_warn(&ofdev->dev,
+					 "failed to get clock: %d\n", ret);
 			goto err_pmruntime;
 		}
 /*
  * Try to register a serial port
  */
-static const struct of_device_id of_platform_serial_table[];
 static int of_platform_serial_probe(struct platform_device *ofdev)
 {
-	const struct of_device_id *match;
 	struct of_serial_info *info;
 	struct uart_8250_port port8250;
+	unsigned int port_type;
 	u32 tx_threshold;
-	int port_type;
 	int ret;
-	match = of_match_device(of_platform_serial_table, &ofdev->dev);
+	port_type = (unsigned long)of_device_get_match_data(&ofdev->dev);
-	if (!match)
+	if (port_type == PORT_UNKNOWN)
 		return -EINVAL;
 	if (of_property_read_bool(ofdev->dev.of_node, "used-by-rtas"))
 	if (info == NULL)
 		return -ENOMEM;
-	port_type = (unsigned long)match->data;
 	memset(&port8250, 0, sizeof(port8250));
 	ret = of_platform_serial_setup(ofdev, port_type, &port8250.port, info);
 	if (ret)

drivers/tty/serial/8250/8250_omap.c+19−24

 	serial8250_do_set_mctrl(port, mctrl);
-	/*
+	if (!up->gpios) {
-	 * Turn off autoRTS if RTS is lowered and restore autoRTS setting
+		/*
-	 * if RTS is raised
+		 * Turn off autoRTS if RTS is lowered and restore autoRTS
-	 */
+		 * setting if RTS is raised
-	lcr = serial_in(up, UART_LCR);
+		 */
-	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
+		lcr = serial_in(up, UART_LCR);
-	if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
+		serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
-		priv->efr |= UART_EFR_RTS;
+		if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
-	else
+			priv->efr |= UART_EFR_RTS;
-		priv->efr &= ~UART_EFR_RTS;
+		else
-	serial_out(up, UART_EFR, priv->efr);
+			priv->efr &= ~UART_EFR_RTS;
-	serial_out(up, UART_LCR, lcr);
+		serial_out(up, UART_EFR, priv->efr);
+		serial_out(up, UART_LCR, lcr);
+	}
 }
 /*
 	priv->efr = 0;
 	up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
-	if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
+	if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW &&
+	    !up->gpios) {
 		/* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
 		up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
 		priv->efr |= UART_EFR_CTS;
 		ret = omap_8250_tx_dma(p);
 		if (ret)
 			en_thri = true;
 	} else if (p->capabilities & UART_CAP_RPM) {
 		en_thri = true;
 	}
 	if (en_thri) {
 		dma->tx_err = 1;
-		p->ier |= UART_IER_THRI;
+		serial8250_set_THRI(p);
-		serial_port_out(&p->port, UART_IER, p->ier);
 	}
 	spin_unlock_irqrestore(&p->port.lock, flags);
 			ret = -EBUSY;
 			goto err;
 		}
-		if (p->ier & UART_IER_THRI) {
+		serial8250_clear_THRI(p);
-			p->ier &= ~UART_IER_THRI;
-			serial_out(p, UART_IER, p->ier);
-		}
 		return 0;
 	}
 	if (dma->tx_err)
 		dma->tx_err = 0;
-	if (p->ier & UART_IER_THRI) {
+	serial8250_clear_THRI(p);
-		p->ier &= ~UART_IER_THRI;
-		serial_out(p, UART_IER, p->ier);
-	}
 	if (skip_byte)
 		serial_out(p, UART_TX, xmit->buf[xmit->tail]);
 	return 0;

drivers/tty/serial/8250/8250_pci.c+79−18

@@ -1326,13 +1326,66 @@ static int pci_default_setup(struct serial_private *priv, · 1325 unmodified lines
1326		1326
1327	return setup_port(priv, port, bar, offset, board->reg_shift);	1327	return setup_port(priv, port, bar, offset, board->reg_shift);
1328	}	1328	}
1329		1329	static void
		1330	pericom_do_set_divisor(struct uart_port *port, unsigned int baud,
		1331	unsigned int quot, unsigned int quot_frac)
		1332	{
		1333	int scr;
		1334	int lcr;
		1335	int actual_baud;
		1336	int tolerance;
		1337
		1338	for (scr = 5 ; scr <= 15 ; scr++) {
		1339	actual_baud = 921600 * 16 / scr;
		1340	tolerance = actual_baud / 50;
		1341
		1342	if ((baud < actual_baud + tolerance) &&
		1343	(baud > actual_baud - tolerance)) {
		1344
		1345	lcr = serial_port_in(port, UART_LCR);
		1346	serial_port_out(port, UART_LCR, lcr \| 0x80);
		1347
		1348	serial_port_out(port, UART_DLL, 1);
		1349	serial_port_out(port, UART_DLM, 0);
		1350	serial_port_out(port, 2, 16 - scr);
		1351	serial_port_out(port, UART_LCR, lcr);
		1352	return;
		1353	} else if (baud > actual_baud) {
		1354	break;
		1355	}
		1356	}
		1357	serial8250_do_set_divisor(port, baud, quot, quot_frac);
		1358	}
1330	static int pci_pericom_setup(struct serial_private *priv,	1359	static int pci_pericom_setup(struct serial_private *priv,
1331	const struct pciserial_board *board,	1360	const struct pciserial_board *board,
1332	struct uart_8250_port *port, int idx)	1361	struct uart_8250_port *port, int idx)
1333	{	1362	{
1334	unsigned int bar, offset = board->first_offset, maxnr;	1363	unsigned int bar, offset = board->first_offset, maxnr;
1335		1364
		1365	bar = FL_GET_BASE(board->flags);
		1366	if (board->flags & FL_BASE_BARS)
		1367	bar += idx;
		1368	else
		1369	offset += idx * board->uart_offset;
		1370
		1371
		1372	maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
		1373	(board->reg_shift + 3);
		1374
		1375	if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
		1376	return 1;
		1377
		1378	port->port.set_divisor = pericom_do_set_divisor;
		1379
		1380	return setup_port(priv, port, bar, offset, board->reg_shift);
		1381	}
		1382
		1383	static int pci_pericom_setup_four_at_eight(struct serial_private *priv,
		1384	const struct pciserial_board *board,
		1385	struct uart_8250_port *port, int idx)
		1386	{
		1387	unsigned int bar, offset = board->first_offset, maxnr;
		1388
1336	bar = FL_GET_BASE(board->flags);	1389	bar = FL_GET_BASE(board->flags);
1337	if (board->flags & FL_BASE_BARS)	1390	if (board->flags & FL_BASE_BARS)
1338	bar += idx;	1391	bar += idx;
@@ -1348,6 +1401,8 @@ static int pci_pericom_setup(struct serial_private *priv, · 9 unmodified lines
1348	if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)	1401	if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1349	return 1;	1402	return 1;
1350		1403
		1404	port->port.set_divisor = pericom_do_set_divisor;
		1405
1351	return setup_port(priv, port, bar, offset, board->reg_shift);	1406	return setup_port(priv, port, bar, offset, board->reg_shift);
1352	}	1407	}
1353		1408
@@ -1995,7 +2050,7 @@ static struct pci_serial_quirk pci_serial_quirks[] __refdata = { · 641 unmodified lines
1995	.device = PCI_DEVICE_ID_PERICOM_PI7C9X7954,	2050	.device = PCI_DEVICE_ID_PERICOM_PI7C9X7954,
1996	.subvendor = PCI_ANY_ID,	2051	.subvendor = PCI_ANY_ID,
1997	.subdevice = PCI_ANY_ID,	2052	.subdevice = PCI_ANY_ID,
1998	.setup = pci_pericom_setup,	2053	.setup = pci_pericom_setup_four_at_eight,
1999	},	2054	},
2000	/*	2055	/*
2001	* PLX	2056	* PLX
@@ -2032,107 +2087,113 @@ static struct pci_serial_quirk pci_serial_quirks[] __refdata = { · 30 unmodified lines
2032	.device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB,	2087	.device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB,
2033	.subvendor = PCI_ANY_ID,	2088	.subvendor = PCI_ANY_ID,
2034	.subdevice = PCI_ANY_ID,	2089	.subdevice = PCI_ANY_ID,
2035	.setup = pci_pericom_setup,	2090	.setup = pci_pericom_setup_four_at_eight,
2036	},	2091	},
2037	{	2092	{
2038	.vendor = PCI_VENDOR_ID_ACCESIO,	2093	.vendor = PCI_VENDOR_ID_ACCESIO,
2039	.device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S,	2094	.device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S,
2040	.subvendor = PCI_ANY_ID,	2095	.subvendor = PCI_ANY_ID,
2041	.subdevice = PCI_ANY_ID,	2096	.subdevice = PCI_ANY_ID,
2042	.setup = pci_pericom_setup,	2097	.setup = pci_pericom_setup_four_at_eight,
2043	},	2098	},
2044	{	2099	{
2045	.vendor = PCI_VENDOR_ID_ACCESIO,	2100	.vendor = PCI_VENDOR_ID_ACCESIO,
2046	.device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB,	2101	.device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB,
2047	.subvendor = PCI_ANY_ID,	2102	.subvendor = PCI_ANY_ID,
2048	.subdevice = PCI_ANY_ID,	2103	.subdevice = PCI_ANY_ID,
2049	.setup = pci_pericom_setup,	2104	.setup = pci_pericom_setup_four_at_eight,
2050	},	2105	},
2051	{	2106	{
2052	.vendor = PCI_VENDOR_ID_ACCESIO,	2107	.vendor = PCI_VENDOR_ID_ACCESIO,
2053	.device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4,	2108	.device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4,
2054	.subvendor = PCI_ANY_ID,	2109	.subvendor = PCI_ANY_ID,
2055	.subdevice = PCI_ANY_ID,	2110	.subdevice = PCI_ANY_ID,
2056	.setup = pci_pericom_setup,	2111	.setup = pci_pericom_setup_four_at_eight,
2057	},	2112	},
2058	{	2113	{
2059	.vendor = PCI_VENDOR_ID_ACCESIO,	2114	.vendor = PCI_VENDOR_ID_ACCESIO,
2060	.device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB,	2115	.device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB,
2061	.subvendor = PCI_ANY_ID,	2116	.subvendor = PCI_ANY_ID,
2062	.subdevice = PCI_ANY_ID,	2117	.subdevice = PCI_ANY_ID,
2063	.setup = pci_pericom_setup,	2118	.setup = pci_pericom_setup_four_at_eight,
2064	},	2119	},
2065	{	2120	{
2066	.vendor = PCI_VENDOR_ID_ACCESIO,	2121	.vendor = PCI_VENDOR_ID_ACCESIO,
2067	.device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM,	2122	.device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM,
2068	.subvendor = PCI_ANY_ID,	2123	.subvendor = PCI_ANY_ID,
2069	.subdevice = PCI_ANY_ID,	2124	.subdevice = PCI_ANY_ID,
2070	.setup = pci_pericom_setup,	2125	.setup = pci_pericom_setup_four_at_eight,
2071	},	2126	},
2072	{	2127	{
2073	.vendor = PCI_VENDOR_ID_ACCESIO,	2128	.vendor = PCI_VENDOR_ID_ACCESIO,
2074	.device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4,	2129	.device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4,
2075	.subvendor = PCI_ANY_ID,	2130	.subvendor = PCI_ANY_ID,
2076	.subdevice = PCI_ANY_ID,	2131	.subdevice = PCI_ANY_ID,
2077	.setup = pci_pericom_setup,	2132	.setup = pci_pericom_setup_four_at_eight,
2078	},	2133	},
2079	{	2134	{
2080	.vendor = PCI_VENDOR_ID_ACCESIO,	2135	.vendor = PCI_VENDOR_ID_ACCESIO,
2081	.device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4,	2136	.device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4,
2082	.subvendor = PCI_ANY_ID,	2137	.subvendor = PCI_ANY_ID,
2083	.subdevice = PCI_ANY_ID,	2138	.subdevice = PCI_ANY_ID,
2084	.setup = pci_pericom_setup,	2139	.setup = pci_pericom_setup_four_at_eight,
2085	},	2140	},
2086	{	2141	{
2087	.vendor = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S,	2142	.vendor = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S,
2088	.device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4,	2143	.device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4,
2089	.subvendor = PCI_ANY_ID,	2144	.subvendor = PCI_ANY_ID,
2090	.subdevice = PCI_ANY_ID,	2145	.subdevice = PCI_ANY_ID,
2091	.setup = pci_pericom_setup,	2146	.setup = pci_pericom_setup_four_at_eight,
2092	},	2147	},
2093	{	2148	{
2094	.vendor = PCI_VENDOR_ID_ACCESIO,	2149	.vendor = PCI_VENDOR_ID_ACCESIO,
2095	.device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4,	2150	.device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4,
2096	.subvendor = PCI_ANY_ID,	2151	.subvendor = PCI_ANY_ID,
2097	.subdevice = PCI_ANY_ID,	2152	.subdevice = PCI_ANY_ID,
2098	.setup = pci_pericom_setup,	2153	.setup = pci_pericom_setup_four_at_eight,
2099	},	2154	},
2100	{	2155	{
2101	.vendor = PCI_VENDOR_ID_ACCESIO,	2156	.vendor = PCI_VENDOR_ID_ACCESIO,
2102	.device = PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4,	2157	.device = PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4,
2103	.subvendor = PCI_ANY_ID,	2158	.subvendor = PCI_ANY_ID,
2104	.subdevice = PCI_ANY_ID,	2159	.subdevice = PCI_ANY_ID,
2105	.setup = pci_pericom_setup,	2160	.setup = pci_pericom_setup_four_at_eight,
2106	},	2161	},
2107	{	2162	{
2108	.vendor = PCI_VENDOR_ID_ACCESIO,	2163	.vendor = PCI_VENDOR_ID_ACCESIO,
2109	.device = PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4,	2164	.device = PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4,
2110	.subvendor = PCI_ANY_ID,	2165	.subvendor = PCI_ANY_ID,
2111	.subdevice = PCI_ANY_ID,	2166	.subdevice = PCI_ANY_ID,
2112	.setup = pci_pericom_setup,	2167	.setup = pci_pericom_setup_four_at_eight,
2113	},	2168	},
2114	{	2169	{
2115	.vendor = PCI_VENDOR_ID_ACCESIO,	2170	.vendor = PCI_VENDOR_ID_ACCESIO,
2116	.device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4,	2171	.device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4,
2117	.subvendor = PCI_ANY_ID,	2172	.subvendor = PCI_ANY_ID,
2118	.subdevice = PCI_ANY_ID,	2173	.subdevice = PCI_ANY_ID,
2119	.setup = pci_pericom_setup,	2174	.setup = pci_pericom_setup_four_at_eight,
2120	},	2175	},
2121	{	2176	{
2122	.vendor = PCI_VENDOR_ID_ACCESIO,	2177	.vendor = PCI_VENDOR_ID_ACCESIO,
2123	.device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM,	2178	.device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM,
2124	.subvendor = PCI_ANY_ID,	2179	.subvendor = PCI_ANY_ID,
2125	.subdevice = PCI_ANY_ID,	2180	.subdevice = PCI_ANY_ID,
2126	.setup = pci_pericom_setup,	2181	.setup = pci_pericom_setup_four_at_eight,
2127	},	2182	},
2128	{	2183	{
2129	.vendor = PCI_VENDOR_ID_ACCESIO,	2184	.vendor = PCI_VENDOR_ID_ACCESIO,
2130	.device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM,	2185	.device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM,
2131	.subvendor = PCI_ANY_ID,	2186	.subvendor = PCI_ANY_ID,
2132	.subdevice = PCI_ANY_ID,	2187	.subdevice = PCI_ANY_ID,
2133	.setup = pci_pericom_setup,	2188	.setup = pci_pericom_setup_four_at_eight,
2134	},	2189	},
2135	/*	2190	{
		2191	.vendor = PCI_VENDOR_ID_ACCESIO,
		2192	.device = PCI_ANY_ID,
		2193	.subvendor = PCI_ANY_ID,
		2194	.subdevice = PCI_ANY_ID,
		2195	.setup = pci_pericom_setup,
		2196	}, /*
2136	* SBS Technologies, Inc., PMC-OCTALPRO 232	2197	* SBS Technologies, Inc., PMC-OCTALPRO 232
2137	*/	2198	*/
2138	{	2199	{

drivers/tty/serial/8250/8250_pnp.c+2−2

@@ -462,8 +462,8 @@ serial_pnp_probe(struct pnp_dev dev, const struct pnp_device_id dev_id) · 461 unmodified lines
462	return -ENODEV;	462	return -ENODEV;
463		463
464	dev_dbg(&dev->dev,	464	dev_dbg(&dev->dev,
465	"Setup PNP port: port %lx, mem %pa, irq %d, type %d\n",	465	"Setup PNP port: port %#lx, mem %#llx, irq %u, type %u\n",
466	uart.port.iobase, &uart.port.mapbase,	466	uart.port.iobase, (unsigned long long)uart.port.mapbase,
467	uart.port.irq, uart.port.iotype);	467	uart.port.irq, uart.port.iotype);
468		468
469	if (flags & CIR_PORT) {	469	if (flags & CIR_PORT) {

drivers/tty/serial/8250/8250_port.c+17−33

@@ -1502,11 +1502,8 @@ static void __stop_tx_rs485(struct uart_8250_port *p) · 1501 unmodified lines
1502		1502
1503	static inline void __do_stop_tx(struct uart_8250_port *p)	1503	static inline void __do_stop_tx(struct uart_8250_port *p)
1504	{	1504	{
1505	if (p->ier & UART_IER_THRI) {	1505	if (serial8250_clear_THRI(p))
1506	p->ier &= ~UART_IER_THRI;
1507	serial_out(p, UART_IER, p->ier);
1508	serial8250_rpm_put_tx(p);	1506	serial8250_rpm_put_tx(p);
1509	}
1510	}	1507	}
1511		1508
1512	static inline void __stop_tx(struct uart_8250_port *p)	1509	static inline void __stop_tx(struct uart_8250_port *p)
@@ -1555,10 +1552,7 @@ static inline void __start_tx(struct uart_port *port) · 42 unmodified lines
1555	if (up->dma && !up->dma->tx_dma(up))	1552	if (up->dma && !up->dma->tx_dma(up))
1556	return;	1553	return;
1557		1554
1558	if (!(up->ier & UART_IER_THRI)) {	1555	if (serial8250_set_THRI(up)) {
1559	up->ier \|= UART_IER_THRI;
1560	serial_port_out(port, UART_IER, up->ier);
1561
1562	if (up->bugs & UART_BUG_TXEN) {	1556	if (up->bugs & UART_BUG_TXEN) {
1563	unsigned char lsr;	1557	unsigned char lsr;
1564		1558
@@ -1662,6 +1656,8 @@ static void serial8250_disable_ms(struct uart_port *port) · 97 unmodified lines
1662	if (up->bugs & UART_BUG_NOMSR)	1656	if (up->bugs & UART_BUG_NOMSR)
1663	return;	1657	return;
1664		1658
		1659	mctrl_gpio_disable_ms(up->gpios);
		1660
1665	up->ier &= ~UART_IER_MSI;	1661	up->ier &= ~UART_IER_MSI;
1666	serial_port_out(port, UART_IER, up->ier);	1662	serial_port_out(port, UART_IER, up->ier);
1667	}	1663	}
@@ -1674,6 +1670,8 @@ static void serial8250_enable_ms(struct uart_port *port) · 6 unmodified lines
1674	if (up->bugs & UART_BUG_NOMSR)	1670	if (up->bugs & UART_BUG_NOMSR)
1675	return;	1671	return;
1676		1672
		1673	mctrl_gpio_enable_ms(up->gpios);
		1674
1677	up->ier \|= UART_IER_MSI;	1675	up->ier \|= UART_IER_MSI;
1678		1676
1679	serial8250_rpm_get(up);	1677	serial8250_rpm_get(up);
@@ -1869,13 +1867,13 @@ int serial8250_handle_irq(struct uart_port *port, unsigned int iir) · 189 unmodified lines
1869		1867
1870	status = serial_port_in(port, UART_LSR);	1868	status = serial_port_in(port, UART_LSR);
1871		1869
1872	if (status & (UART_LSR_DR \| UART_LSR_BI) &&	1870	if (status & (UART_LSR_DR \| UART_LSR_BI)) {
1873	iir & UART_IIR_RDI) {
1874	if (!up->dma \|\| handle_rx_dma(up, iir))	1871	if (!up->dma \|\| handle_rx_dma(up, iir))
1875	status = serial8250_rx_chars(up, status);	1872	status = serial8250_rx_chars(up, status);
1876	}	1873	}
1877	serial8250_modem_status(up);	1874	serial8250_modem_status(up);
1878	if ((!up->dma \|\| up->dma->tx_err) && (status & UART_LSR_THRE))	1875	if ((!up->dma \|\| up->dma->tx_err) && (status & UART_LSR_THRE) &&
		1876	(up->ier & UART_IER_THRI))
1879	serial8250_tx_chars(up);	1877	serial8250_tx_chars(up);
1880		1878
1881	uart_unlock_and_check_sysrq(port, flags);	1879	uart_unlock_and_check_sysrq(port, flags);
@@ -1944,22 +1942,17 @@ unsigned int serial8250_do_get_mctrl(struct uart_port *port) · 62 unmodified lines
1944	{	1942	{
1945	struct uart_8250_port *up = up_to_u8250p(port);	1943	struct uart_8250_port *up = up_to_u8250p(port);
1946	unsigned int status;	1944	unsigned int status;
1947	unsigned int ret;	1945	unsigned int val;
1948		1946
1949	serial8250_rpm_get(up);	1947	serial8250_rpm_get(up);
1950	status = serial8250_modem_status(up);	1948	status = serial8250_modem_status(up);
1951	serial8250_rpm_put(up);	1949	serial8250_rpm_put(up);
1952		1950
1953	ret = 0;	1951	val = serial8250_MSR_to_TIOCM(status);
1954	if (status & UART_MSR_DCD)	1952	if (up->gpios)
1955	ret \|= TIOCM_CAR;	1953	return mctrl_gpio_get(up->gpios, &val);
1956	if (status & UART_MSR_RI)	1954
1957	ret \|= TIOCM_RNG;	1955	return val;
1958	if (status & UART_MSR_DSR)
1959	ret \|= TIOCM_DSR;
1960	if (status & UART_MSR_CTS)
1961	ret \|= TIOCM_CTS;
1962	return ret;
1963	}	1956	}
1964	EXPORT_SYMBOL_GPL(serial8250_do_get_mctrl);	1957	EXPORT_SYMBOL_GPL(serial8250_do_get_mctrl);
1965		1958
@@ -1973,18 +1966,9 @@ static unsigned int serial8250_get_mctrl(struct uart_port *port) · 7 unmodified lines
1973	void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)	1966	void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
1974	{	1967	{
1975	struct uart_8250_port *up = up_to_u8250p(port);	1968	struct uart_8250_port *up = up_to_u8250p(port);
1976	unsigned char mcr = 0;	1969	unsigned char mcr;
1977		1970
1978	if (mctrl & TIOCM_RTS)	1971	mcr = serial8250_TIOCM_to_MCR(mctrl);
1979	mcr \|= UART_MCR_RTS;
1980	if (mctrl & TIOCM_DTR)
1981	mcr \|= UART_MCR_DTR;
1982	if (mctrl & TIOCM_OUT1)
1983	mcr \|= UART_MCR_OUT1;
1984	if (mctrl & TIOCM_OUT2)
1985	mcr \|= UART_MCR_OUT2;
1986	if (mctrl & TIOCM_LOOP)
1987	mcr \|= UART_MCR_LOOP;
1988		1972
1989	mcr = (mcr & up->mcr_mask) \| up->mcr_force \| up->mcr;	1973	mcr = (mcr & up->mcr_mask) \| up->mcr_force \| up->mcr;
1990		1974

drivers/tty/serial/8250/Kconfig+1−0

@@ -8,6 +8,7 @@ config SERIAL_8250 · 7 unmodified lines
8	tristate "8250/16550 and compatible serial support"	8	tristate "8250/16550 and compatible serial support"
9	depends on !S390	9	depends on !S390
10	select SERIAL_CORE	10	select SERIAL_CORE
		11	select SERIAL_MCTRL_GPIO if GPIOLIB
11	---help---	12	---help---
12	This selects whether you want to include the driver for the standard	13	This selects whether you want to include the driver for the standard
13	serial ports. The standard answer is Y. People who might say N	14	serial ports. The standard answer is Y. People who might say N

drivers/tty/serial/Kconfig+0−14

@@ -457,20 +457,6 @@ config SERIAL_21285_CONSOLE · 456 unmodified lines
457	your boot loader (lilo or loadlin) about how to pass options to the	457	your boot loader (lilo or loadlin) about how to pass options to the
458	kernel at boot time.)	458	kernel at boot time.)
459		459
460	config SERIAL_MPSC
461	bool "Marvell MPSC serial port support"
462	depends on MV64X60
463	select SERIAL_CORE
464	help
465	Say Y here if you want to use the Marvell MPSC serial controller.
466
467	config SERIAL_MPSC_CONSOLE
468	bool "Support for console on Marvell MPSC serial port"
469	depends on SERIAL_MPSC
470	select SERIAL_CORE_CONSOLE
471	help
472	Say Y here if you want to support a serial console on a Marvell MPSC.
473
474	config SERIAL_PXA	460	config SERIAL_PXA
475	bool "PXA serial port support (DEPRECATED)"	461	bool "PXA serial port support (DEPRECATED)"
476	depends on ARCH_PXA \|\| ARCH_MMP	462	depends on ARCH_PXA \|\| ARCH_MMP

drivers/tty/serial/Makefile+0−1

@@ -46,7 +46,6 @@ obj-$(CONFIG_SERIAL_CPM) += cpm_uart/ · 45 unmodified lines
46	obj-$(CONFIG_SERIAL_IMX) += imx.o	46	obj-$(CONFIG_SERIAL_IMX) += imx.o
47	obj-$(CONFIG_SERIAL_MPC52xx) += mpc52xx_uart.o	47	obj-$(CONFIG_SERIAL_MPC52xx) += mpc52xx_uart.o
48	obj-$(CONFIG_SERIAL_ICOM) += icom.o	48	obj-$(CONFIG_SERIAL_ICOM) += icom.o
49	obj-$(CONFIG_SERIAL_MPSC) += mpsc.o
50	obj-$(CONFIG_SERIAL_MESON) += meson_uart.o	49	obj-$(CONFIG_SERIAL_MESON) += meson_uart.o
51	obj-$(CONFIG_SERIAL_SB1250_DUART) += sb1250-duart.o	50	obj-$(CONFIG_SERIAL_SB1250_DUART) += sb1250-duart.o
52	obj-$(CONFIG_SERIAL_SCCNXP) += sccnxp.o	51	obj-$(CONFIG_SERIAL_SCCNXP) += sccnxp.o

drivers/tty/serial/amba-pl011.c+1−1

@@ -1717,7 +1717,7 @@ static int pl011_allocate_irq(struct uart_amba_port *uap) · 1716 unmodified lines
1717	{	1717	{
1718	pl011_write(uap->im, uap, REG_IMSC);	1718	pl011_write(uap->im, uap, REG_IMSC);
1719		1719
1720	return request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);	1720	return request_irq(uap->port.irq, pl011_int, IRQF_SHARED, "uart-pl011", uap);
1721	}	1721	}
1722		1722
1723	/*	1723	/*

drivers/tty/serial/cpm_uart/cpm_uart_core.c+11−8

 			clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX);
 		}
 		cpm_uart_initbd(pinfo);
-		cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX);
+		if (IS_SMC(pinfo)) {
+			out_be32(&pinfo->smcup->smc_rstate, 0);
+			out_be32(&pinfo->smcup->smc_tstate, 0);
+			out_be16(&pinfo->smcup->smc_rbptr,
+				 in_be16(&pinfo->smcup->smc_rbase));
+			out_be16(&pinfo->smcup->smc_tbptr,
+				 in_be16(&pinfo->smcup->smc_tbase));
+		} else {
+			cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX);
+		}
 	}
 	/* Install interrupt handler. */
 	retval = request_irq(port->irq, cpm_uart_int, 0, "cpm_uart", port);
 	/*
 	 * Set up parity check flag
 	 */
-#define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
 	port->read_status_mask = (BD_SC_EMPTY | BD_SC_OV);
 	if (termios->c_iflag & INPCK)
 		port->read_status_mask |= BD_SC_FR | BD_SC_PR;
 	         (u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE);
 /*
- *  In case SMC1 is being relocated...
+ *  In case SMC is being relocated...
  */
-#if defined (CONFIG_I2C_SPI_SMC1_UCODE_PATCH)
 	out_be16(&up->smc_rbptr, in_be16(&pinfo->smcup->smc_rbase));
 	out_be16(&up->smc_tbptr, in_be16(&pinfo->smcup->smc_tbase));
 	out_be32(&up->smc_rstate, 0);
 	out_be32(&up->smc_tstate, 0);
 	out_be16(&up->smc_brkcr, 1);              /* number of break chars */
 	out_be16(&up->smc_brkec, 0);
-#endif
 	/* Set up the uart parameters in the
 	 * parameter ram.
 	out_be16(&up->smc_brkec, 0);
 	out_be16(&up->smc_brkcr, 1);
-	cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX);
 	/* Set UART mode, 8 bit, no parity, one stop.
 	 * Enable receive and transmit.
 	 */

drivers/tty/serial/digicolor-usart.c+5−1

 	if (ret)
 		return ret;
-	return platform_driver_register(&digicolor_uart_platform);
+	ret = platform_driver_register(&digicolor_uart_platform);
+	if (ret)
+		uart_unregister_driver(&digicolor_uart);
+	return ret;
 }
 module_init(digicolor_uart_init);

drivers/tty/serial/fsl_lpuart.c+89−25

 static DEFINE_IDA(fsl_lpuart_ida);
+enum lpuart_type {
+	VF610_LPUART,
+	LS1021A_LPUART,
+	IMX7ULP_LPUART,
+	IMX8QXP_LPUART,
+};
 struct lpuart_port {
 	struct uart_port	port;
-	struct clk		*clk;
+	enum lpuart_type	devtype;
+	struct clk		*ipg_clk;
+	struct clk		*baud_clk;
 	unsigned int		txfifo_size;
 	unsigned int		rxfifo_size;
 };
 struct lpuart_soc_data {
-	char	iotype;
+	enum lpuart_type devtype;
-	u8	reg_off;
+	char iotype;
+	u8 reg_off;
 };
 static const struct lpuart_soc_data vf_data = {
+	.devtype = VF610_LPUART,
 	.iotype = UPIO_MEM,
 };
 static const struct lpuart_soc_data ls_data = {
+	.devtype = LS1021A_LPUART,
 	.iotype = UPIO_MEM32BE,
 };
-static struct lpuart_soc_data imx_data = {
+static struct lpuart_soc_data imx7ulp_data = {
+	.devtype = IMX7ULP_LPUART,
+	.iotype = UPIO_MEM32,
+	.reg_off = IMX_REG_OFF,
+};
+static struct lpuart_soc_data imx8qxp_data = {
+	.devtype = IMX8QXP_LPUART,
 	.iotype = UPIO_MEM32,
 	.reg_off = IMX_REG_OFF,
 };
 static const struct of_device_id lpuart_dt_ids[] = {
 	{ .compatible = "fsl,vf610-lpuart",	.data = &vf_data, },
 	{ .compatible = "fsl,ls1021a-lpuart",	.data = &ls_data, },
-	{ .compatible = "fsl,imx7ulp-lpuart",	.data = &imx_data, },
+	{ .compatible = "fsl,imx7ulp-lpuart",	.data = &imx7ulp_data, },
+	{ .compatible = "fsl,imx8qxp-lpuart",	.data = &imx8qxp_data, },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
 /* Forward declare this for the dma callbacks*/
 static void lpuart_dma_tx_complete(void *arg);
+static inline bool is_imx8qxp_lpuart(struct lpuart_port *sport)
+{
+	return sport->devtype == IMX8QXP_LPUART;
+}
 static inline u32 lpuart32_read(struct uart_port *port, u32 off)
 {
 	switch (port->iotype) {
 	}
 }
+static int __lpuart_enable_clks(struct lpuart_port *sport, bool is_en)
+{
+	int ret = 0;
+	if (is_en) {
+		ret = clk_prepare_enable(sport->ipg_clk);
+		if (ret)
+			return ret;
+		ret = clk_prepare_enable(sport->baud_clk);
+		if (ret) {
+			clk_disable_unprepare(sport->ipg_clk);
+			return ret;
+		}
+	} else {
+		clk_disable_unprepare(sport->baud_clk);
+		clk_disable_unprepare(sport->ipg_clk);
+	}
+	return 0;
+}
+static unsigned int lpuart_get_baud_clk_rate(struct lpuart_port *sport)
+{
+	if (is_imx8qxp_lpuart(sport))
+		return clk_get_rate(sport->baud_clk);
+	return clk_get_rate(sport->ipg_clk);
+}
+#define lpuart_enable_clks(x)	__lpuart_enable_clks(x, true)
+#define lpuart_disable_clks(x)	__lpuart_enable_clks(x, false)
 static void lpuart_stop_tx(struct uart_port *port)
 {
 	unsigned char temp;
 		sport->rx_dma_rng_buf_len = 16;
 	ring->buf = kmalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC);
-	if (!ring->buf) {
+	if (!ring->buf)
-		dev_err(sport->port.dev, "Ring buf alloc failed\n");
 		return -ENOMEM;
-	}
 	sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
 	sg_set_buf(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
 	brfa = readb(sport->port.membase + UARTCR4);
 	brfa &= UARTCR4_BRFA_MASK;
-	uartclk = clk_get_rate(sport->clk);
+	uartclk = lpuart_get_baud_clk_rate(sport);
 	/*
 	 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
 	 */
 	baud_raw = uartclk / (16 * (sbr + brfa / 32));
 	if (*baud != baud_raw)
-		printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
+		dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
 				"from %d to %d\n", baud_raw, *baud);
 }
 	bd = lpuart32_read(&sport->port, UARTBAUD);
 	bd &= UARTBAUD_SBR_MASK;
 	sbr = bd;
-	uartclk = clk_get_rate(sport->clk);
+	uartclk = lpuart_get_baud_clk_rate(sport);
 	/*
 	 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
 	 */
 	baud_raw = uartclk / (16 * sbr);
 	if (*baud != baud_raw)
-		printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
+		dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
 				"from %d to %d\n", baud_raw, *baud);
 }
 	sport->port.mapbase = res->start;
 	sport->port.dev = &pdev->dev;
 	sport->port.type = PORT_LPUART;
+	sport->devtype = sdata->devtype;
 	ret = platform_get_irq(pdev, 0);
 	if (ret < 0) {
 		dev_err(&pdev->dev, "cannot obtain irq\n");
 	sport->port.rs485_config = lpuart_config_rs485;
-	sport->clk = devm_clk_get(&pdev->dev, "ipg");
+	sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
-	if (IS_ERR(sport->clk)) {
+	if (IS_ERR(sport->ipg_clk)) {
-		ret = PTR_ERR(sport->clk);
+		ret = PTR_ERR(sport->ipg_clk);
-		dev_err(&pdev->dev, "failed to get uart clk: %d\n", ret);
+		dev_err(&pdev->dev, "failed to get uart ipg clk: %d\n", ret);
 		return ret;
 	}
-	ret = clk_prepare_enable(sport->clk);
+	sport->baud_clk = NULL;
-	if (ret) {
+	if (is_imx8qxp_lpuart(sport)) {
-		dev_err(&pdev->dev, "failed to enable uart clk: %d\n", ret);
+		sport->baud_clk = devm_clk_get(&pdev->dev, "baud");
-		return ret;
+		if (IS_ERR(sport->baud_clk)) {
+			ret = PTR_ERR(sport->baud_clk);
+			dev_err(&pdev->dev, "failed to get uart baud clk: %d\n", ret);
+			return ret;
+		}
 	}
-	sport->port.uartclk = clk_get_rate(sport->clk);
+	ret = lpuart_enable_clks(sport);
+	if (ret)
+		return ret;
+	sport->port.uartclk = lpuart_get_baud_clk_rate(sport);
 	lpuart_ports[sport->port.line] = sport;
 failed_attach_port:
 failed_irq_request:
-	clk_disable_unprepare(sport->clk);
+	lpuart_disable_clks(sport);
 	return ret;
 }
 	ida_simple_remove(&fsl_lpuart_ida, sport->port.line);
-	clk_disable_unprepare(sport->clk);
+	lpuart_disable_clks(sport);
 	if (sport->dma_tx_chan)
 		dma_release_channel(sport->dma_tx_chan);
 	}
 	if (sport->port.suspended && !irq_wake)
-		clk_disable_unprepare(sport->clk);
+		lpuart_disable_clks(sport);
 	return 0;
 }
 	unsigned long temp;
 	if (sport->port.suspended && !irq_wake)
-		clk_prepare_enable(sport->clk);
+		lpuart_enable_clks(sport);
 	if (lpuart_is_32(sport)) {
 		lpuart32_setup_watermark(sport);

drivers/tty/serial/imx.c+39−43

@@ -383,6 +383,7 @@ static void imx_uart_ucrs_restore(struct imx_port *sport, · 382 unmodified lines
383	}	383	}
384	#endif	384	#endif
385		385
		386	/* called with port.lock taken and irqs caller dependent */
386	static void imx_uart_rts_active(struct imx_port sport, u32 ucr2)	387	static void imx_uart_rts_active(struct imx_port sport, u32 ucr2)
387	{	388	{
388	*ucr2 &= ~(UCR2_CTSC \| UCR2_CTS);	389	*ucr2 &= ~(UCR2_CTSC \| UCR2_CTS);
@@ -391,6 +392,7 @@ static void imx_uart_rts_active(struct imx_port sport, u32 ucr2) · 2 unmodified lines
391	mctrl_gpio_set(sport->gpios, sport->port.mctrl);	392	mctrl_gpio_set(sport->gpios, sport->port.mctrl);
392	}	393	}
393		394
		395	/* called with port.lock taken and irqs caller dependent */
394	static void imx_uart_rts_inactive(struct imx_port sport, u32 ucr2)	396	static void imx_uart_rts_inactive(struct imx_port sport, u32 ucr2)
395	{	397	{
396	*ucr2 &= ~UCR2_CTSC;	398	*ucr2 &= ~UCR2_CTSC;
@@ -400,6 +402,7 @@ static void imx_uart_rts_inactive(struct imx_port sport, u32 ucr2) · 3 unmodified lines
400	mctrl_gpio_set(sport->gpios, sport->port.mctrl);	402	mctrl_gpio_set(sport->gpios, sport->port.mctrl);
401	}	403	}
402		404
		405	/* called with port.lock taken and irqs caller dependent */
403	static void imx_uart_rts_auto(struct imx_port sport, u32 ucr2)	406	static void imx_uart_rts_auto(struct imx_port sport, u32 ucr2)
404	{	407	{
405	*ucr2 \|= UCR2_CTSC;	408	*ucr2 \|= UCR2_CTSC;
@@ -1549,40 +1552,46 @@ imx_uart_set_termios(struct uart_port port, struct ktermios termios, · 1143 unmodified lines
1549	old_csize = CS8;	1552	old_csize = CS8;
1550	}	1553	}
1551		1554
		1555	del_timer_sync(&sport->timer);
		1556
		1557	/*
		1558	* Ask the core to calculate the divisor for us.
		1559	*/
		1560	baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
		1561	quot = uart_get_divisor(port, baud);
		1562
		1563	spin_lock_irqsave(&sport->port.lock, flags);
		1564
		1565	/*
		1566	* Read current UCR2 and save it for future use, then clear all the bits
		1567	* except those we will or may need to preserve.
		1568	*/
		1569	old_ucr2 = imx_uart_readl(sport, UCR2);
		1570	ucr2 = old_ucr2 & (UCR2_TXEN \| UCR2_RXEN \| UCR2_ATEN \| UCR2_CTS);
		1571
		1572	ucr2 \|= UCR2_SRST \| UCR2_IRTS;
1552	if ((termios->c_cflag & CSIZE) == CS8)	1573	if ((termios->c_cflag & CSIZE) == CS8)
1553	ucr2 = UCR2_WS \| UCR2_SRST \| UCR2_IRTS;	1574	ucr2 \|= UCR2_WS;
1554	else	1575
1555	ucr2 = UCR2_SRST \| UCR2_IRTS;	1576	if (!sport->have_rtscts)
1556		1577	termios->c_cflag &= ~CRTSCTS;
1557	if (termios->c_cflag & CRTSCTS) {	1578
1558	if (sport->have_rtscts) {	1579	if (port->rs485.flags & SER_RS485_ENABLED) {
1559	ucr2 &= ~UCR2_IRTS;	1580	/*
1560		1581	* RTS is mandatory for rs485 operation, so keep
1561	if (port->rs485.flags & SER_RS485_ENABLED) {	1582	* it under manual control and keep transmitter
1562	/*	1583	* disabled.
1563	* RTS is mandatory for rs485 operation, so keep	1584	*/
1564	* it under manual control and keep transmitter
1565	* disabled.
1566	*/
1567	if (port->rs485.flags &
1568	SER_RS485_RTS_AFTER_SEND)
1569	imx_uart_rts_active(sport, &ucr2);
1570	else
1571	imx_uart_rts_inactive(sport, &ucr2);
1572	} else {
1573	imx_uart_rts_auto(sport, &ucr2);
1574	}
1575	} else {
1576	termios->c_cflag &= ~CRTSCTS;
1577	}
1578	} else if (port->rs485.flags & SER_RS485_ENABLED) {
1579	/* disable transmitter */
1580	if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)	1585	if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1581	imx_uart_rts_active(sport, &ucr2);	1586	imx_uart_rts_active(sport, &ucr2);
1582	else	1587	else
1583	imx_uart_rts_inactive(sport, &ucr2);	1588	imx_uart_rts_inactive(sport, &ucr2);
1584	}
1585		1589
		1590	} else if (termios->c_cflag & CRTSCTS)
		1591	imx_uart_rts_auto(sport, &ucr2);
		1592
		1593	if (termios->c_cflag & CRTSCTS)
		1594	ucr2 &= ~UCR2_IRTS;
1586		1595
1587	if (termios->c_cflag & CSTOPB)	1596	if (termios->c_cflag & CSTOPB)
1588	ucr2 \|= UCR2_STPB;	1597	ucr2 \|= UCR2_STPB;
@@ -1592,16 +1601,6 @@ imx_uart_set_termios(struct uart_port port, struct ktermios termios, · 3 unmodified lines
1592	ucr2 \|= UCR2_PROE;	1601	ucr2 \|= UCR2_PROE;
1593	}	1602	}
1594		1603
1595	del_timer_sync(&sport->timer);
1596
1597	/*
1598	* Ask the core to calculate the divisor for us.
1599	*/
1600	baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1601	quot = uart_get_divisor(port, baud);
1602
1603	spin_lock_irqsave(&sport->port.lock, flags);
1604
1605	sport->port.read_status_mask = 0;	1604	sport->port.read_status_mask = 0;
1606	if (termios->c_iflag & INPCK)	1605	if (termios->c_iflag & INPCK)
1607	sport->port.read_status_mask \|= (URXD_FRMERR \| URXD_PRERR);	1606	sport->port.read_status_mask \|= (URXD_FRMERR \| URXD_PRERR);
@@ -1639,7 +1638,6 @@ imx_uart_set_termios(struct uart_port port, struct ktermios termios, · 31 unmodified lines
1639	imx_uart_writel(sport,	1638	imx_uart_writel(sport,
1640	old_ucr1 & ~(UCR1_TXMPTYEN \| UCR1_RRDYEN \| UCR1_RTSDEN),	1639	old_ucr1 & ~(UCR1_TXMPTYEN \| UCR1_RRDYEN \| UCR1_RTSDEN),
1641	UCR1);	1640	UCR1);
1642	old_ucr2 = imx_uart_readl(sport, UCR2);
1643	imx_uart_writel(sport, old_ucr2 & ~UCR2_ATEN, UCR2);	1641	imx_uart_writel(sport, old_ucr2 & ~UCR2_ATEN, UCR2);
1644		1642
1645	while (!(imx_uart_readl(sport, USR2) & USR2_TXDC))	1643	while (!(imx_uart_readl(sport, USR2) & USR2_TXDC))
@@ -1647,7 +1645,6 @@ imx_uart_set_termios(struct uart_port port, struct ktermios termios, · 1 unmodified line
1647		1645
1648	/* then, disable everything */	1646	/* then, disable everything */
1649	imx_uart_writel(sport, old_ucr2 & ~(UCR2_TXEN \| UCR2_RXEN \| UCR2_ATEN), UCR2);	1647	imx_uart_writel(sport, old_ucr2 & ~(UCR2_TXEN \| UCR2_RXEN \| UCR2_ATEN), UCR2);
1650	old_ucr2 &= (UCR2_TXEN \| UCR2_RXEN \| UCR2_ATEN);
1651		1648
1652	/* custom-baudrate handling */	1649	/* custom-baudrate handling */
1653	div = sport->port.uartclk / (baud * 16);	1650	div = sport->port.uartclk / (baud * 16);
@@ -1685,8 +1682,7 @@ imx_uart_set_termios(struct uart_port port, struct ktermios termios, · 31 unmodified lines
1685		1682
1686	imx_uart_writel(sport, old_ucr1, UCR1);	1683	imx_uart_writel(sport, old_ucr1, UCR1);
1687		1684
1688	/* set the parity, stop bits and data size */	1685	imx_uart_writel(sport, ucr2, UCR2);
1689	imx_uart_writel(sport, ucr2 \| old_ucr2, UCR2);
1690		1686
1691	if (UART_ENABLE_MS(&sport->port, termios->c_cflag))	1687	if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1692	imx_uart_enable_ms(&sport->port);	1688	imx_uart_enable_ms(&sport->port);
@@ -2015,7 +2011,7 @@ imx_uart_console_get_options(struct imx_port sport, int baud, · 322 unmodified lines
2015	}	2011	}
2016		2012
2017	if (*baud != baud_raw)	2013	if (*baud != baud_raw)
2018	pr_info("Console IMX rounded baud rate from %d to %d\n",	2014	dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n",
2019	baud_raw, *baud);	2015	baud_raw, *baud);
2020	}	2016	}
2021	}	2017	}

drivers/tty/serial/max310x.c+95−62

@@ -258,12 +258,17 @@ struct max310x_one { · 257 unmodified lines
258	struct work_struct tx_work;	258	struct work_struct tx_work;
259	struct work_struct md_work;	259	struct work_struct md_work;
260	struct work_struct rs_work;	260	struct work_struct rs_work;
		261
		262	u8 wr_header;
		263	u8 rd_header;
		264	u8 rx_buf[MAX310X_FIFO_SIZE];
261	};	265	};
		266	#define to_max310x_port(_port) \
		267	container_of(_port, struct max310x_one, port)
262		268
263	struct max310x_port {	269	struct max310x_port {
264	struct max310x_devtype *devtype;	270	struct max310x_devtype *devtype;
265	struct regmap *regmap;	271	struct regmap *regmap;
266	struct mutex mutex;
267	struct clk *clk;	272	struct clk *clk;
268	#ifdef CONFIG_GPIOLIB	273	#ifdef CONFIG_GPIOLIB
269	struct gpio_chip gpio;	274	struct gpio_chip gpio;
@@ -496,37 +501,48 @@ static bool max310x_reg_precious(struct device *dev, unsigned int reg) · 226 unmodified lines
496		501
497	static int max310x_set_baud(struct uart_port *port, int baud)	502	static int max310x_set_baud(struct uart_port *port, int baud)
498	{	503	{
499	unsigned int mode = 0, clk = port->uartclk, div = clk / baud;	504	unsigned int mode = 0, div = 0, frac = 0, c = 0, F = 0;
500
501	/* Check for minimal value for divider */
502	if (div < 16)
503	div = 16;
504		505
505	if (clk % baud && (div / 16) < 0x8000) {	506	/*
		507	* Calculate the integer divisor first. Select a proper mode
		508	* in case if the requested baud is too high for the pre-defined
		509	* clocks frequency.
		510	*/
		511	div = port->uartclk / baud;
		512	if (div < 8) {
		513	/* Mode x4 */
		514	c = 4;
		515	mode = MAX310X_BRGCFG_4XMODE_BIT;
		516	} else if (div < 16) {
506	/* Mode x2 */	517	/* Mode x2 */
		518	c = 8;
507	mode = MAX310X_BRGCFG_2XMODE_BIT;	519	mode = MAX310X_BRGCFG_2XMODE_BIT;
508	clk = port->uartclk * 2;	520	} else {
509	div = clk / baud;	521	c = 16;
510
511	if (clk % baud && (div / 16) < 0x8000) {
512	/* Mode x4 */
513	mode = MAX310X_BRGCFG_4XMODE_BIT;
514	clk = port->uartclk * 4;
515	div = clk / baud;
516	}
517	}	522	}
518		523
519	max310x_port_write(port, MAX310X_BRGDIVMSB_REG, (div / 16) >> 8);	524	/* Calculate the divisor in accordance with the fraction coefficient */
520	max310x_port_write(port, MAX310X_BRGDIVLSB_REG, div / 16);	525	div /= c;
521	max310x_port_write(port, MAX310X_BRGCFG_REG, (div % 16) \| mode);	526	F = c*baud;
522		527
523	return DIV_ROUND_CLOSEST(clk, div);	528	/* Calculate the baud rate fraction */
		529	if (div > 0)
		530	frac = (16*(port->uartclk % F)) / F;
		531	else
		532	div = 1;
		533
		534	max310x_port_write(port, MAX310X_BRGDIVMSB_REG, div >> 8);
		535	max310x_port_write(port, MAX310X_BRGDIVLSB_REG, div);
		536	max310x_port_write(port, MAX310X_BRGCFG_REG, frac \| mode);
		537
		538	/* Return the actual baud rate we just programmed */
		539	return (16port->uartclk) / (c(16*div + frac));
524	}	540	}
525		541
526	static int max310x_update_best_err(unsigned long f, long *besterr)	542	static int max310x_update_best_err(unsigned long f, long *besterr)
527	{	543	{
528	/* Use baudrate 115200 for calculate error */	544	/* Use baudrate 115200 for calculate error */
529	long err = f % (115200 * 16);	545	long err = f % (460800 * 16);
530		546
531	if ((besterr < 0) \|\| (besterr > err)) {	547	if ((besterr < 0) \|\| (besterr > err)) {
532	*besterr = err;	548	*besterr = err;
@@ -607,11 +623,11 @@ static int max310x_set_ref_clk(struct device dev, struct max310x_port s, · 74 unmodified lines
607		623
608	static void max310x_batch_write(struct uart_port port, u8 txbuf, unsigned int len)	624	static void max310x_batch_write(struct uart_port port, u8 txbuf, unsigned int len)
609	{	625	{
610	u8 header[] = { (port->iobase + MAX310X_THR_REG) \| MAX310X_WRITE_BIT };	626	struct max310x_one *one = to_max310x_port(port);
611	struct spi_transfer xfer[] = {	627	struct spi_transfer xfer[] = {
612	{	628	{
613	.tx_buf = &header,	629	.tx_buf = &one->wr_header,
614	.len = sizeof(header),	630	.len = sizeof(one->wr_header),
615	}, {	631	}, {
616	.tx_buf = txbuf,	632	.tx_buf = txbuf,
617	.len = len,	633	.len = len,
@@ -622,11 +638,11 @@ static void max310x_batch_write(struct uart_port port, u8 txbuf, unsigned int · 4 unmodified lines
622		638
623	static void max310x_batch_read(struct uart_port port, u8 rxbuf, unsigned int len)	639	static void max310x_batch_read(struct uart_port port, u8 rxbuf, unsigned int len)
624	{	640	{
625	u8 header[] = { port->iobase + MAX310X_RHR_REG };	641	struct max310x_one *one = to_max310x_port(port);
626	struct spi_transfer xfer[] = {	642	struct spi_transfer xfer[] = {
627	{	643	{
628	.tx_buf = &header,	644	.tx_buf = &one->rd_header,
629	.len = sizeof(header),	645	.len = sizeof(one->rd_header),
630	}, {	646	}, {
631	.rx_buf = rxbuf,	647	.rx_buf = rxbuf,
632	.len = len,	648	.len = len,
@@ -637,8 +653,8 @@ static void max310x_batch_read(struct uart_port port, u8 rxbuf, unsigned int l · 4 unmodified lines
637		653
638	static void max310x_handle_rx(struct uart_port *port, unsigned int rxlen)	654	static void max310x_handle_rx(struct uart_port *port, unsigned int rxlen)
639	{	655	{
		656	struct max310x_one *one = to_max310x_port(port);
640	unsigned int sts, ch, flag, i;	657	unsigned int sts, ch, flag, i;
641	u8 buf[MAX310X_FIFO_SIZE];
642		658
643	if (port->read_status_mask == MAX310X_LSR_RXOVR_BIT) {	659	if (port->read_status_mask == MAX310X_LSR_RXOVR_BIT) {
644	/* We are just reading, happily ignoring any error conditions.	660	/* We are just reading, happily ignoring any error conditions.
@@ -653,7 +669,7 @@ static void max310x_handle_rx(struct uart_port *port, unsigned int rxlen) · 8 unmodified lines
653	* */	669	* */
654		670
655	sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);	671	sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);
656	max310x_batch_read(port, buf, rxlen);	672	max310x_batch_read(port, one->rx_buf, rxlen);
657		673
658	port->icount.rx += rxlen;	674	port->icount.rx += rxlen;
659	flag = TTY_NORMAL;	675	flag = TTY_NORMAL;
@@ -664,9 +680,16 @@ static void max310x_handle_rx(struct uart_port *port, unsigned int rxlen) · 4 unmodified lines
664	port->icount.overrun++;	680	port->icount.overrun++;
665	}	681	}
666		682
667	for (i = 0; i < rxlen; ++i) {	683	for (i = 0; i < (rxlen - 1); ++i)
668	uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, buf[i], flag);	684	uart_insert_char(port, sts, 0, one->rx_buf[i], flag);
669	}	685
		686	/*
		687	* Handle the overrun case for the last character only, since
		688	* the RxFIFO overflow happens after it is pushed to the FIFO
		689	* tail.
		690	*/
		691	uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT,
		692	one->rx_buf[rxlen], flag);
670		693
671	} else {	694	} else {
672	if (unlikely(rxlen >= port->fifosize)) {	695	if (unlikely(rxlen >= port->fifosize)) {
@@ -766,10 +789,9 @@ static void max310x_handle_tx(struct uart_port *port) · 93 unmodified lines
766		789
767	static void max310x_start_tx(struct uart_port *port)	790	static void max310x_start_tx(struct uart_port *port)
768	{	791	{
769	struct max310x_one *one = container_of(port, struct max310x_one, port);	792	struct max310x_one *one = to_max310x_port(port);
770		793
771	if (!work_pending(&one->tx_work))	794	schedule_work(&one->tx_work);
772	schedule_work(&one->tx_work);
773	}	795	}
774		796
775	static irqreturn_t max310x_port_irq(struct max310x_port *s, int portno)	797	static irqreturn_t max310x_port_irq(struct max310x_port *s, int portno)
@@ -826,14 +848,11 @@ static irqreturn_t max310x_ist(int irq, void *dev_id) · 50 unmodified lines
826	return IRQ_RETVAL(handled);	848	return IRQ_RETVAL(handled);
827	}	849	}
828		850
829	static void max310x_wq_proc(struct work_struct *ws)	851	static void max310x_tx_proc(struct work_struct *ws)
830	{	852	{
831	struct max310x_one *one = container_of(ws, struct max310x_one, tx_work);	853	struct max310x_one *one = container_of(ws, struct max310x_one, tx_work);
832	struct max310x_port *s = dev_get_drvdata(one->port.dev);
833		854
834	mutex_lock(&s->mutex);
835	max310x_handle_tx(&one->port);	855	max310x_handle_tx(&one->port);
836	mutex_unlock(&s->mutex);
837	}	856	}
838		857
839	static unsigned int max310x_tx_empty(struct uart_port *port)	858	static unsigned int max310x_tx_empty(struct uart_port *port)
@@ -863,7 +882,7 @@ static void max310x_md_proc(struct work_struct *ws) · 23 unmodified lines
863		882
864	static void max310x_set_mctrl(struct uart_port *port, unsigned int mctrl)	883	static void max310x_set_mctrl(struct uart_port *port, unsigned int mctrl)
865	{	884	{
866	struct max310x_one *one = container_of(port, struct max310x_one, port);	885	struct max310x_one *one = to_max310x_port(port);
867		886
868	schedule_work(&one->md_work);	887	schedule_work(&one->md_work);
869	}	888	}
@@ -962,37 +981,36 @@ static void max310x_set_termios(struct uart_port *port, · 92 unmodified lines
962	static void max310x_rs_proc(struct work_struct *ws)	981	static void max310x_rs_proc(struct work_struct *ws)
963	{	982	{
964	struct max310x_one *one = container_of(ws, struct max310x_one, rs_work);	983	struct max310x_one *one = container_of(ws, struct max310x_one, rs_work);
965	unsigned int val;	984	unsigned int delay, mode1 = 0, mode2 = 0;
966		985
967	val = (one->port.rs485.delay_rts_before_send << 4) \|	986	delay = (one->port.rs485.delay_rts_before_send << 4) \|
968	one->port.rs485.delay_rts_after_send;	987	one->port.rs485.delay_rts_after_send;
969	max310x_port_write(&one->port, MAX310X_HDPIXDELAY_REG, val);	988	max310x_port_write(&one->port, MAX310X_HDPIXDELAY_REG, delay);
970		989
971	if (one->port.rs485.flags & SER_RS485_ENABLED) {	990	if (one->port.rs485.flags & SER_RS485_ENABLED) {
972	max310x_port_update(&one->port, MAX310X_MODE1_REG,	991	mode1 = MAX310X_MODE1_TRNSCVCTRL_BIT;
973	MAX310X_MODE1_TRNSCVCTRL_BIT,	992
974	MAX310X_MODE1_TRNSCVCTRL_BIT);	993	if (!(one->port.rs485.flags & SER_RS485_RX_DURING_TX))
975	max310x_port_update(&one->port, MAX310X_MODE2_REG,	994	mode2 = MAX310X_MODE2_ECHOSUPR_BIT;
976	MAX310X_MODE2_ECHOSUPR_BIT,
977	MAX310X_MODE2_ECHOSUPR_BIT);
978	} else {
979	max310x_port_update(&one->port, MAX310X_MODE1_REG,
980	MAX310X_MODE1_TRNSCVCTRL_BIT, 0);
981	max310x_port_update(&one->port, MAX310X_MODE2_REG,
982	MAX310X_MODE2_ECHOSUPR_BIT, 0);
983	}	995	}
		996
		997	max310x_port_update(&one->port, MAX310X_MODE1_REG,
		998	MAX310X_MODE1_TRNSCVCTRL_BIT, mode1);
		999	max310x_port_update(&one->port, MAX310X_MODE2_REG,
		1000	MAX310X_MODE2_ECHOSUPR_BIT, mode2);
984	}	1001	}
985		1002
986	static int max310x_rs485_config(struct uart_port *port,	1003	static int max310x_rs485_config(struct uart_port *port,
987	struct serial_rs485 *rs485)	1004	struct serial_rs485 *rs485)
988	{	1005	{
989	struct max310x_one *one = container_of(port, struct max310x_one, port);	1006	struct max310x_one *one = to_max310x_port(port);
990		1007
991	if ((rs485->delay_rts_before_send > 0x0f) \|\|	1008	if ((rs485->delay_rts_before_send > 0x0f) \|\|
992	(rs485->delay_rts_after_send > 0x0f))	1009	(rs485->delay_rts_after_send > 0x0f))
993	return -ERANGE;	1010	return -ERANGE;
994		1011
995	rs485->flags &= SER_RS485_RTS_ON_SEND \| SER_RS485_ENABLED;	1012	rs485->flags &= SER_RS485_RTS_ON_SEND \| SER_RS485_RX_DURING_TX \|
		1013	SER_RS485_ENABLED;
996	memset(rs485->padding, 0, sizeof(rs485->padding));	1014	memset(rs485->padding, 0, sizeof(rs485->padding));
997	port->rs485 = *rs485;	1015	port->rs485 = *rs485;
998		1016
@@ -1018,6 +1036,22 @@ static int max310x_startup(struct uart_port *port) · 19 unmodified lines
1018	max310x_port_update(port, MAX310X_MODE2_REG,	1036	max310x_port_update(port, MAX310X_MODE2_REG,
1019	MAX310X_MODE2_FIFORST_BIT, 0);	1037	MAX310X_MODE2_FIFORST_BIT, 0);
1020		1038
		1039	/* Configure mode1/mode2 to have rs485/rs232 enabled at startup */
		1040	val = (clamp(port->rs485.delay_rts_before_send, 0U, 15U) << 4) \|
		1041	clamp(port->rs485.delay_rts_after_send, 0U, 15U);
		1042	max310x_port_write(port, MAX310X_HDPIXDELAY_REG, val);
		1043
		1044	if (port->rs485.flags & SER_RS485_ENABLED) {
		1045	max310x_port_update(port, MAX310X_MODE1_REG,
		1046	MAX310X_MODE1_TRNSCVCTRL_BIT,
		1047	MAX310X_MODE1_TRNSCVCTRL_BIT);
		1048
		1049	if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
		1050	max310x_port_update(port, MAX310X_MODE2_REG,
		1051	MAX310X_MODE2_ECHOSUPR_BIT,
		1052	MAX310X_MODE2_ECHOSUPR_BIT);
		1053	}
		1054
1021	/* Configure flow control levels */	1055	/* Configure flow control levels */
1022	/* Flow control halt level 96, resume level 48 */	1056	/* Flow control halt level 96, resume level 48 */
1023	max310x_port_write(port, MAX310X_FLOWLVL_REG,	1057	max310x_port_write(port, MAX310X_FLOWLVL_REG,
@@ -1269,8 +1303,6 @@ static int max310x_probe(struct device dev, struct max310x_devtype devtype, · 245 unmodified lines
1269	uartclk = max310x_set_ref_clk(dev, s, freq, xtal);	1303	uartclk = max310x_set_ref_clk(dev, s, freq, xtal);
1270	dev_dbg(dev, "Reference clock set to %i Hz\n", uartclk);	1304	dev_dbg(dev, "Reference clock set to %i Hz\n", uartclk);
1271		1305
1272	mutex_init(&s->mutex);
1273
1274	for (i = 0; i < devtype->nr; i++) {	1306	for (i = 0; i < devtype->nr; i++) {
1275	unsigned int line;	1307	unsigned int line;
1276		1308
@@ -1298,11 +1330,15 @@ static int max310x_probe(struct device dev, struct max310x_devtype devtype, · 21 unmodified lines
1298	/* Clear IRQ status register */	1330	/* Clear IRQ status register */
1299	max310x_port_read(&s->p[i].port, MAX310X_IRQSTS_REG);	1331	max310x_port_read(&s->p[i].port, MAX310X_IRQSTS_REG);
1300	/* Initialize queue for start TX */	1332	/* Initialize queue for start TX */
1301	INIT_WORK(&s->p[i].tx_work, max310x_wq_proc);	1333	INIT_WORK(&s->p[i].tx_work, max310x_tx_proc);
1302	/* Initialize queue for changing LOOPBACK mode */	1334	/* Initialize queue for changing LOOPBACK mode */
1303	INIT_WORK(&s->p[i].md_work, max310x_md_proc);	1335	INIT_WORK(&s->p[i].md_work, max310x_md_proc);
1304	/* Initialize queue for changing RS485 mode */	1336	/* Initialize queue for changing RS485 mode */
1305	INIT_WORK(&s->p[i].rs_work, max310x_rs_proc);	1337	INIT_WORK(&s->p[i].rs_work, max310x_rs_proc);
		1338	/* Initialize SPI-transfer buffers */
		1339	s->p[i].wr_header = (s->p[i].port.iobase + MAX310X_THR_REG) \|
		1340	MAX310X_WRITE_BIT;
		1341	s->p[i].rd_header = (s->p[i].port.iobase + MAX310X_RHR_REG);
1306		1342
1307	/* Register port */	1343	/* Register port */
1308	ret = uart_add_one_port(&max310x_uart, &s->p[i].port);	1344	ret = uart_add_one_port(&max310x_uart, &s->p[i].port);
@@ -1350,8 +1386,6 @@ out_uart: · 41 unmodified lines
1350	}	1386	}
1351	}	1387	}
1352		1388
1353	mutex_destroy(&s->mutex);
1354
1355	out_clk:	1389	out_clk:
1356	clk_disable_unprepare(s->clk);	1390	clk_disable_unprepare(s->clk);
1357		1391
@@ -1372,7 +1406,6 @@ static int max310x_remove(struct device *dev) · 14 unmodified lines
1372	s->devtype->power(&s->p[i].port, 0);	1406	s->devtype->power(&s->p[i].port, 0);
1373	}	1407	}
1374		1408
1375	mutex_destroy(&s->mutex);
1376	clk_disable_unprepare(s->clk);	1409	clk_disable_unprepare(s->clk);
1377		1410
1378	return 0;	1411	return 0;

drivers/tty/serial/mpsc.c+0−2138

@@ -1,2138 +0,0 @@
1	// SPDX-License-Identifier: GPL-2.0
2	/*
3	* Generic driver for the MPSC (UART mode) on Marvell parts (e.g., GT64240,
4	* GT64260, MV64340, MV64360, GT96100, ... ).
5	*
6	* Author: Mark A. Greer <mgreer@mvista.com>
7	*
8	* Based on an old MPSC driver that was in the linuxppc tree. It appears to
9	* have been created by Chris Zankel (formerly of MontaVista) but there
10	* is no proper Copyright so I'm not sure. Apparently, parts were also
11	* taken from PPCBoot (now U-Boot). Also based on drivers/serial/8250.c
12	* by Russell King.
13	*
14	* 2004 (c) MontaVista, Software, Inc.
15	*/
16	/*
17	* The MPSC interface is much like a typical network controller's interface.
18	* That is, you set up separate rings of descriptors for transmitting and
19	* receiving data. There is also a pool of buffers with (one buffer per
20	* descriptor) that incoming data are dma'd into or outgoing data are dma'd
21	* out of.
22	*
23	* The MPSC requires two other controllers to be able to work. The Baud Rate
24	* Generator (BRG) provides a clock at programmable frequencies which determines
25	* the baud rate. The Serial DMA Controller (SDMA) takes incoming data from the
26	* MPSC and DMA's it into memory or DMA's outgoing data and passes it to the
27	* MPSC. It is actually the SDMA interrupt that the driver uses to keep the
28	* transmit and receive "engines" going (i.e., indicate data has been
29	* transmitted or received).
30	*
31	* NOTES:
32	*
33	* 1) Some chips have an erratum where several regs cannot be
34	* read. To work around that, we keep a local copy of those regs in
35	* 'mpsc_port_info'.
36	*
37	* 2) Some chips have an erratum where the ctlr will hang when the SDMA ctlr
38	* accesses system mem with coherency enabled. For that reason, the driver
39	* assumes that coherency for that ctlr has been disabled. This means
40	* that when in a cache coherent system, the driver has to manually manage
41	* the data cache on the areas that it touches because the dma_* macro are
42	* basically no-ops.
43	*
44	* 3) There is an erratum (on PPC) where you can't use the instruction to do
45	* a DMA_TO_DEVICE/cache clean so DMA_BIDIRECTIONAL/flushes are used in places
46	* where a DMA_TO_DEVICE/clean would have [otherwise] sufficed.
47	*
48	* 4) AFAICT, hardware flow control isn't supported by the controller --MAG.
49	*/
50
51
52	#if defined(CONFIG_SERIAL_MPSC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
53	#define SUPPORT_SYSRQ
54	#endif
55
56	#include <linux/tty.h>
57	#include <linux/tty_flip.h>
58	#include <linux/ioport.h>
59	#include <linux/init.h>
60	#include <linux/console.h>
61	#include <linux/sysrq.h>
62	#include <linux/serial.h>
63	#include <linux/serial_core.h>
64	#include <linux/delay.h>
65	#include <linux/device.h>
66	#include <linux/dma-mapping.h>
67	#include <linux/mv643xx.h>
68	#include <linux/platform_device.h>
69	#include <linux/gfp.h>
70
71	#include <asm/io.h>
72	#include <asm/irq.h>
73
74	#define MPSC_NUM_CTLRS 2
75
76	/*
77	* Descriptors and buffers must be cache line aligned.
78	* Buffers lengths must be multiple of cache line size.
79	* Number of Tx & Rx descriptors must be powers of 2.
80	*/
81	#define MPSC_RXR_ENTRIES 32
82	#define MPSC_RXRE_SIZE dma_get_cache_alignment()
83	#define MPSC_RXR_SIZE (MPSC_RXR_ENTRIES * MPSC_RXRE_SIZE)
84	#define MPSC_RXBE_SIZE dma_get_cache_alignment()
85	#define MPSC_RXB_SIZE (MPSC_RXR_ENTRIES * MPSC_RXBE_SIZE)
86
87	#define MPSC_TXR_ENTRIES 32
88	#define MPSC_TXRE_SIZE dma_get_cache_alignment()
89	#define MPSC_TXR_SIZE (MPSC_TXR_ENTRIES * MPSC_TXRE_SIZE)
90	#define MPSC_TXBE_SIZE dma_get_cache_alignment()
91	#define MPSC_TXB_SIZE (MPSC_TXR_ENTRIES * MPSC_TXBE_SIZE)
92
93	#define MPSC_DMA_ALLOC_SIZE (MPSC_RXR_SIZE + MPSC_RXB_SIZE + MPSC_TXR_SIZE \
94	+ MPSC_TXB_SIZE + dma_get_cache_alignment() /* for alignment */)
95
96	/* Rx and Tx Ring entry descriptors -- assume entry size is <= cacheline size */
97	struct mpsc_rx_desc {
98	u16 bufsize;
99	u16 bytecnt;
100	u32 cmdstat;
101	u32 link;
102	u32 buf_ptr;
103	} __attribute((packed));
104
105	struct mpsc_tx_desc {
106	u16 bytecnt;
107	u16 shadow;
108	u32 cmdstat;
109	u32 link;
110	u32 buf_ptr;
111	} __attribute((packed));
112
113	/*
114	* Some regs that have the erratum that you can't read them are are shared
115	* between the two MPSC controllers. This struct contains those shared regs.
116	*/
117	struct mpsc_shared_regs {
118	phys_addr_t mpsc_routing_base_p;
119	phys_addr_t sdma_intr_base_p;
120
121	void __iomem *mpsc_routing_base;
122	void __iomem *sdma_intr_base;
123
124	u32 MPSC_MRR_m;
125	u32 MPSC_RCRR_m;
126	u32 MPSC_TCRR_m;
127	u32 SDMA_INTR_CAUSE_m;
128	u32 SDMA_INTR_MASK_m;
129	};
130
131	/* The main driver data structure */
132	struct mpsc_port_info {
133	struct uart_port port; /* Overlay uart_port structure */
134
135	/* Internal driver state for this ctlr */
136	u8 ready;
137	u8 rcv_data;
138
139	/* Info passed in from platform */
140	u8 mirror_regs; /* Need to mirror regs? */
141	u8 cache_mgmt; /* Need manual cache mgmt? */
142	u8 brg_can_tune; /* BRG has baud tuning? */
143	u32 brg_clk_src;
144	u16 mpsc_max_idle;
145	int default_baud;
146	int default_bits;
147	int default_parity;
148	int default_flow;
149
150	/* Physical addresses of various blocks of registers (from platform) */
151	phys_addr_t mpsc_base_p;
152	phys_addr_t sdma_base_p;
153	phys_addr_t brg_base_p;
154
155	/* Virtual addresses of various blocks of registers (from platform) */
156	void __iomem *mpsc_base;
157	void __iomem *sdma_base;
158	void __iomem *brg_base;
159
160	/* Descriptor ring and buffer allocations */
161	void *dma_region;
162	dma_addr_t dma_region_p;
163
164	dma_addr_t rxr; /* Rx descriptor ring */
165	dma_addr_t rxr_p; /* Phys addr of rxr */
166	u8 rxb; / Rx Ring I/O buf */
167	u8 rxb_p; / Phys addr of rxb */
168	u32 rxr_posn; /* First desc w/ Rx data */
169
170	dma_addr_t txr; /* Tx descriptor ring */
171	dma_addr_t txr_p; /* Phys addr of txr */
172	u8 txb; / Tx Ring I/O buf */
173	u8 txb_p; / Phys addr of txb */
174	int txr_head; /* Where new data goes */
175	int txr_tail; /* Where sent data comes off */
176	spinlock_t tx_lock; /* transmit lock */
177
178	/* Mirrored values of regs we can't read (if 'mirror_regs' set) */
179	u32 MPSC_MPCR_m;
180	u32 MPSC_CHR_1_m;
181	u32 MPSC_CHR_2_m;
182	u32 MPSC_CHR_10_m;
183	u32 BRG_BCR_m;
184	struct mpsc_shared_regs *shared_regs;
185	};
186
187	/* Hooks to platform-specific code */
188	int mpsc_platform_register_driver(void);
189	void mpsc_platform_unregister_driver(void);
190
191	/* Hooks back in to mpsc common to be called by platform-specific code */
192	struct mpsc_port_info *mpsc_device_probe(int index);
193	struct mpsc_port_info *mpsc_device_remove(int index);
194
195	/* Main MPSC Configuration Register Offsets */
196	#define MPSC_MMCRL 0x0000
197	#define MPSC_MMCRH 0x0004
198	#define MPSC_MPCR 0x0008
199	#define MPSC_CHR_1 0x000c
200	#define MPSC_CHR_2 0x0010
201	#define MPSC_CHR_3 0x0014
202	#define MPSC_CHR_4 0x0018
203	#define MPSC_CHR_5 0x001c
204	#define MPSC_CHR_6 0x0020
205	#define MPSC_CHR_7 0x0024
206	#define MPSC_CHR_8 0x0028
207	#define MPSC_CHR_9 0x002c
208	#define MPSC_CHR_10 0x0030
209	#define MPSC_CHR_11 0x0034
210
211	#define MPSC_MPCR_FRZ (1 << 9)
212	#define MPSC_MPCR_CL_5 0
213	#define MPSC_MPCR_CL_6 1
214	#define MPSC_MPCR_CL_7 2
215	#define MPSC_MPCR_CL_8 3
216	#define MPSC_MPCR_SBL_1 0
217	#define MPSC_MPCR_SBL_2 1
218
219	#define MPSC_CHR_2_TEV (1<<1)
220	#define MPSC_CHR_2_TA (1<<7)
221	#define MPSC_CHR_2_TTCS (1<<9)
222	#define MPSC_CHR_2_REV (1<<17)
223	#define MPSC_CHR_2_RA (1<<23)
224	#define MPSC_CHR_2_CRD (1<<25)
225	#define MPSC_CHR_2_EH (1<<31)
226	#define MPSC_CHR_2_PAR_ODD 0
227	#define MPSC_CHR_2_PAR_SPACE 1
228	#define MPSC_CHR_2_PAR_EVEN 2
229	#define MPSC_CHR_2_PAR_MARK 3
230
231	/* MPSC Signal Routing */
232	#define MPSC_MRR 0x0000
233	#define MPSC_RCRR 0x0004
234	#define MPSC_TCRR 0x0008
235
236	/* Serial DMA Controller Interface Registers */
237	#define SDMA_SDC 0x0000
238	#define SDMA_SDCM 0x0008
239	#define SDMA_RX_DESC 0x0800
240	#define SDMA_RX_BUF_PTR 0x0808
241	#define SDMA_SCRDP 0x0810
242	#define SDMA_TX_DESC 0x0c00
243	#define SDMA_SCTDP 0x0c10
244	#define SDMA_SFTDP 0x0c14
245
246	#define SDMA_DESC_CMDSTAT_PE (1<<0)
247	#define SDMA_DESC_CMDSTAT_CDL (1<<1)
248	#define SDMA_DESC_CMDSTAT_FR (1<<3)
249	#define SDMA_DESC_CMDSTAT_OR (1<<6)
250	#define SDMA_DESC_CMDSTAT_BR (1<<9)
251	#define SDMA_DESC_CMDSTAT_MI (1<<10)
252	#define SDMA_DESC_CMDSTAT_A (1<<11)
253	#define SDMA_DESC_CMDSTAT_AM (1<<12)
254	#define SDMA_DESC_CMDSTAT_CT (1<<13)
255	#define SDMA_DESC_CMDSTAT_C (1<<14)
256	#define SDMA_DESC_CMDSTAT_ES (1<<15)
257	#define SDMA_DESC_CMDSTAT_L (1<<16)
258	#define SDMA_DESC_CMDSTAT_F (1<<17)
259	#define SDMA_DESC_CMDSTAT_P (1<<18)
260	#define SDMA_DESC_CMDSTAT_EI (1<<23)
261	#define SDMA_DESC_CMDSTAT_O (1<<31)
262
263	#define SDMA_DESC_DFLT (SDMA_DESC_CMDSTAT_O \
264	\| SDMA_DESC_CMDSTAT_EI)
265
266	#define SDMA_SDC_RFT (1<<0)
267	#define SDMA_SDC_SFM (1<<1)
268	#define SDMA_SDC_BLMR (1<<6)
269	#define SDMA_SDC_BLMT (1<<7)
270	#define SDMA_SDC_POVR (1<<8)
271	#define SDMA_SDC_RIFB (1<<9)
272
273	#define SDMA_SDCM_ERD (1<<7)
274	#define SDMA_SDCM_AR (1<<15)
275	#define SDMA_SDCM_STD (1<<16)
276	#define SDMA_SDCM_TXD (1<<23)
277	#define SDMA_SDCM_AT (1<<31)
278
279	#define SDMA_0_CAUSE_RXBUF (1<<0)
280	#define SDMA_0_CAUSE_RXERR (1<<1)
281	#define SDMA_0_CAUSE_TXBUF (1<<2)
282	#define SDMA_0_CAUSE_TXEND (1<<3)
283	#define SDMA_1_CAUSE_RXBUF (1<<8)
284	#define SDMA_1_CAUSE_RXERR (1<<9)
285	#define SDMA_1_CAUSE_TXBUF (1<<10)
286	#define SDMA_1_CAUSE_TXEND (1<<11)
287
288	#define SDMA_CAUSE_RX_MASK (SDMA_0_CAUSE_RXBUF \| SDMA_0_CAUSE_RXERR \
289	\| SDMA_1_CAUSE_RXBUF \| SDMA_1_CAUSE_RXERR)
290	#define SDMA_CAUSE_TX_MASK (SDMA_0_CAUSE_TXBUF \| SDMA_0_CAUSE_TXEND \
291	\| SDMA_1_CAUSE_TXBUF \| SDMA_1_CAUSE_TXEND)
292
293	/* SDMA Interrupt registers */
294	#define SDMA_INTR_CAUSE 0x0000
295	#define SDMA_INTR_MASK 0x0080
296
297	/* Baud Rate Generator Interface Registers */
298	#define BRG_BCR 0x0000
299	#define BRG_BTR 0x0004
300
301	/*
302	* Define how this driver is known to the outside (we've been assigned a
303	* range on the "Low-density serial ports" major).
304	*/
305	#define MPSC_MAJOR 204
306	#define MPSC_MINOR_START 44
307	#define MPSC_DRIVER_NAME "MPSC"
308	#define MPSC_DEV_NAME "ttyMM"
309	#define MPSC_VERSION "1.00"
310
311	static struct mpsc_port_info mpsc_ports[MPSC_NUM_CTLRS];
312	static struct mpsc_shared_regs mpsc_shared_regs;
313	static struct uart_driver mpsc_reg;
314
315	static void mpsc_start_rx(struct mpsc_port_info *pi);
316	static void mpsc_free_ring_mem(struct mpsc_port_info *pi);
317	static void mpsc_release_port(struct uart_port *port);
318	/*
319	******************************************************************************
320	*
321	* Baud Rate Generator Routines (BRG)
322	*
323	******************************************************************************
324	*/
325	static void mpsc_brg_init(struct mpsc_port_info *pi, u32 clk_src)
326	{
327	u32 v;
328
329	v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
330	v = (v & ~(0xf << 18)) \| ((clk_src & 0xf) << 18);
331
332	if (pi->brg_can_tune)
333	v &= ~(1 << 25);
334
335	if (pi->mirror_regs)
336	pi->BRG_BCR_m = v;
337	writel(v, pi->brg_base + BRG_BCR);
338
339	writel(readl(pi->brg_base + BRG_BTR) & 0xffff0000,
340	pi->brg_base + BRG_BTR);
341	}
342
343	static void mpsc_brg_enable(struct mpsc_port_info *pi)
344	{
345	u32 v;
346
347	v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
348	v \|= (1 << 16);
349
350	if (pi->mirror_regs)
351	pi->BRG_BCR_m = v;
352	writel(v, pi->brg_base + BRG_BCR);
353	}
354
355	static void mpsc_brg_disable(struct mpsc_port_info *pi)
356	{
357	u32 v;
358
359	v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
360	v &= ~(1 << 16);
361
362	if (pi->mirror_regs)
363	pi->BRG_BCR_m = v;
364	writel(v, pi->brg_base + BRG_BCR);
365	}
366
367	/*
368	* To set the baud, we adjust the CDV field in the BRG_BCR reg.
369	* From manual: Baud = clk / ((CDV+1)2) ==> CDV = (clk / (baud2)) - 1.
370	* However, the input clock is divided by 16 in the MPSC b/c of how
371	* 'MPSC_MMCRH' was set up so we have to divide the 'clk' used in our
372	* calculation by 16 to account for that. So the real calculation
373	* that accounts for the way the mpsc is set up is:
374	* CDV = (clk / (baud216)) - 1 ==> CDV = (clk / (baud << 5)) - 1.
375	*/
376	static void mpsc_set_baudrate(struct mpsc_port_info *pi, u32 baud)
377	{
378	u32 cdv = (pi->port.uartclk / (baud << 5)) - 1;
379	u32 v;
380
381	mpsc_brg_disable(pi);
382	v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
383	v = (v & 0xffff0000) \| (cdv & 0xffff);
384
385	if (pi->mirror_regs)
386	pi->BRG_BCR_m = v;
387	writel(v, pi->brg_base + BRG_BCR);
388	mpsc_brg_enable(pi);
389	}
390
391	/*
392	******************************************************************************
393	*
394	* Serial DMA Routines (SDMA)
395	*
396	******************************************************************************
397	*/
398
399	static void mpsc_sdma_burstsize(struct mpsc_port_info *pi, u32 burst_size)
400	{
401	u32 v;
402
403	pr_debug("mpsc_sdma_burstsize[%d]: burst_size: %d\n",
404	pi->port.line, burst_size);
405
406	burst_size >>= 3; /* Divide by 8 b/c reg values are 8-byte chunks */
407
408	if (burst_size < 2)
409	v = 0x0; /* 1 64-bit word */
410	else if (burst_size < 4)
411	v = 0x1; /* 2 64-bit words */
412	else if (burst_size < 8)
413	v = 0x2; /* 4 64-bit words */
414	else
415	v = 0x3; /* 8 64-bit words */
416
417	writel((readl(pi->sdma_base + SDMA_SDC) & (0x3 << 12)) \| (v << 12),
418	pi->sdma_base + SDMA_SDC);
419	}
420
421	static void mpsc_sdma_init(struct mpsc_port_info *pi, u32 burst_size)
422	{
423	pr_debug("mpsc_sdma_init[%d]: burst_size: %d\n", pi->port.line,
424	burst_size);
425
426	writel((readl(pi->sdma_base + SDMA_SDC) & 0x3ff) \| 0x03f,
427	pi->sdma_base + SDMA_SDC);
428	mpsc_sdma_burstsize(pi, burst_size);
429	}
430
431	static u32 mpsc_sdma_intr_mask(struct mpsc_port_info *pi, u32 mask)
432	{
433	u32 old, v;
434
435	pr_debug("mpsc_sdma_intr_mask[%d]: mask: 0x%x\n", pi->port.line, mask);
436
437	old = v = (pi->mirror_regs) ? pi->shared_regs->SDMA_INTR_MASK_m :
438	readl(pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
439
440	mask &= 0xf;
441	if (pi->port.line)
442	mask <<= 8;
443	v &= ~mask;
444
445	if (pi->mirror_regs)
446	pi->shared_regs->SDMA_INTR_MASK_m = v;
447	writel(v, pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
448
449	if (pi->port.line)
450	old >>= 8;
451	return old & 0xf;
452	}
453
454	static void mpsc_sdma_intr_unmask(struct mpsc_port_info *pi, u32 mask)
455	{
456	u32 v;
457
458	pr_debug("mpsc_sdma_intr_unmask[%d]: mask: 0x%x\n", pi->port.line,mask);
459
460	v = (pi->mirror_regs) ? pi->shared_regs->SDMA_INTR_MASK_m
461	: readl(pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
462
463	mask &= 0xf;
464	if (pi->port.line)
465	mask <<= 8;
466	v \|= mask;
467
468	if (pi->mirror_regs)
469	pi->shared_regs->SDMA_INTR_MASK_m = v;
470	writel(v, pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
471	}
472
473	static void mpsc_sdma_intr_ack(struct mpsc_port_info *pi)
474	{
475	pr_debug("mpsc_sdma_intr_ack[%d]: Acknowledging IRQ\n", pi->port.line);
476
477	if (pi->mirror_regs)
478	pi->shared_regs->SDMA_INTR_CAUSE_m = 0;
479	writeb(0x00, pi->shared_regs->sdma_intr_base + SDMA_INTR_CAUSE
480	+ pi->port.line);
481	}
482
483	static void mpsc_sdma_set_rx_ring(struct mpsc_port_info *pi,
484	struct mpsc_rx_desc *rxre_p)
485	{
486	pr_debug("mpsc_sdma_set_rx_ring[%d]: rxre_p: 0x%x\n",
487	pi->port.line, (u32)rxre_p);
488
489	writel((u32)rxre_p, pi->sdma_base + SDMA_SCRDP);
490	}
491
492	static void mpsc_sdma_set_tx_ring(struct mpsc_port_info *pi,
493	struct mpsc_tx_desc *txre_p)
494	{
495	writel((u32)txre_p, pi->sdma_base + SDMA_SFTDP);
496	writel((u32)txre_p, pi->sdma_base + SDMA_SCTDP);
497	}
498
499	static void mpsc_sdma_cmd(struct mpsc_port_info *pi, u32 val)
500	{
501	u32 v;
502
503	v = readl(pi->sdma_base + SDMA_SDCM);
504	if (val)
505	v \|= val;
506	else
507	v = 0;
508	wmb();
509	writel(v, pi->sdma_base + SDMA_SDCM);
510	wmb();
511	}
512
513	static uint mpsc_sdma_tx_active(struct mpsc_port_info *pi)
514	{
515	return readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_TXD;
516	}
517
518	static void mpsc_sdma_start_tx(struct mpsc_port_info *pi)
519	{
520	struct mpsc_tx_desc txre, txre_p;
521
522	/* If tx isn't running & there's a desc ready to go, start it */
523	if (!mpsc_sdma_tx_active(pi)) {
524	txre = (struct mpsc_tx_desc *)(pi->txr
525	+ (pi->txr_tail * MPSC_TXRE_SIZE));
526	dma_cache_sync(pi->port.dev, (void *)txre, MPSC_TXRE_SIZE,
527	DMA_FROM_DEVICE);
528	#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
529	if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
530	invalidate_dcache_range((ulong)txre,
531	(ulong)txre + MPSC_TXRE_SIZE);
532	#endif
533
534	if (be32_to_cpu(txre->cmdstat) & SDMA_DESC_CMDSTAT_O) {
535	txre_p = (struct mpsc_tx_desc *)
536	(pi->txr_p + (pi->txr_tail * MPSC_TXRE_SIZE));
537
538	mpsc_sdma_set_tx_ring(pi, txre_p);
539	mpsc_sdma_cmd(pi, SDMA_SDCM_STD \| SDMA_SDCM_TXD);
540	}
541	}
542	}
543
544	static void mpsc_sdma_stop(struct mpsc_port_info *pi)
545	{
546	pr_debug("mpsc_sdma_stop[%d]: Stopping SDMA\n", pi->port.line);
547
548	/* Abort any SDMA transfers */
549	mpsc_sdma_cmd(pi, 0);
550	mpsc_sdma_cmd(pi, SDMA_SDCM_AR \| SDMA_SDCM_AT);
551
552	/* Clear the SDMA current and first TX and RX pointers */
553	mpsc_sdma_set_tx_ring(pi, NULL);
554	mpsc_sdma_set_rx_ring(pi, NULL);
555
556	/* Disable interrupts */
557	mpsc_sdma_intr_mask(pi, 0xf);
558	mpsc_sdma_intr_ack(pi);
559	}
560
561	/*
562	******************************************************************************
563	*
564	* Multi-Protocol Serial Controller Routines (MPSC)
565	*
566	******************************************************************************
567	*/
568
569	static void mpsc_hw_init(struct mpsc_port_info *pi)
570	{
571	u32 v;
572
573	pr_debug("mpsc_hw_init[%d]: Initializing hardware\n", pi->port.line);
574
575	/* Set up clock routing */
576	if (pi->mirror_regs) {
577	v = pi->shared_regs->MPSC_MRR_m;
578	v &= ~0x1c7;
579	pi->shared_regs->MPSC_MRR_m = v;
580	writel(v, pi->shared_regs->mpsc_routing_base + MPSC_MRR);
581
582	v = pi->shared_regs->MPSC_RCRR_m;
583	v = (v & ~0xf0f) \| 0x100;
584	pi->shared_regs->MPSC_RCRR_m = v;
585	writel(v, pi->shared_regs->mpsc_routing_base + MPSC_RCRR);
586
587	v = pi->shared_regs->MPSC_TCRR_m;
588	v = (v & ~0xf0f) \| 0x100;
589	pi->shared_regs->MPSC_TCRR_m = v;
590	writel(v, pi->shared_regs->mpsc_routing_base + MPSC_TCRR);
591	} else {
592	v = readl(pi->shared_regs->mpsc_routing_base + MPSC_MRR);
593	v &= ~0x1c7;
594	writel(v, pi->shared_regs->mpsc_routing_base + MPSC_MRR);
595
596	v = readl(pi->shared_regs->mpsc_routing_base + MPSC_RCRR);
597	v = (v & ~0xf0f) \| 0x100;
598	writel(v, pi->shared_regs->mpsc_routing_base + MPSC_RCRR);
599
600	v = readl(pi->shared_regs->mpsc_routing_base + MPSC_TCRR);
601	v = (v & ~0xf0f) \| 0x100;
602	writel(v, pi->shared_regs->mpsc_routing_base + MPSC_TCRR);
603	}
604
605	/* Put MPSC in UART mode & enabel Tx/Rx egines */
606	writel(0x000004c4, pi->mpsc_base + MPSC_MMCRL);
607
608	/* No preamble, 16x divider, low-latency, */
609	writel(0x04400400, pi->mpsc_base + MPSC_MMCRH);
610	mpsc_set_baudrate(pi, pi->default_baud);
611
612	if (pi->mirror_regs) {
613	pi->MPSC_CHR_1_m = 0;
614	pi->MPSC_CHR_2_m = 0;
615	}
616	writel(0, pi->mpsc_base + MPSC_CHR_1);
617	writel(0, pi->mpsc_base + MPSC_CHR_2);
618	writel(pi->mpsc_max_idle, pi->mpsc_base + MPSC_CHR_3);
619	writel(0, pi->mpsc_base + MPSC_CHR_4);
620	writel(0, pi->mpsc_base + MPSC_CHR_5);
621	writel(0, pi->mpsc_base + MPSC_CHR_6);
622	writel(0, pi->mpsc_base + MPSC_CHR_7);
623	writel(0, pi->mpsc_base + MPSC_CHR_8);
624	writel(0, pi->mpsc_base + MPSC_CHR_9);
625	writel(0, pi->mpsc_base + MPSC_CHR_10);
626	}
627
628	static void mpsc_enter_hunt(struct mpsc_port_info *pi)
629	{
630	pr_debug("mpsc_enter_hunt[%d]: Hunting...\n", pi->port.line);
631
632	if (pi->mirror_regs) {
633	writel(pi->MPSC_CHR_2_m \| MPSC_CHR_2_EH,
634	pi->mpsc_base + MPSC_CHR_2);
635	/* Erratum prevents reading CHR_2 so just delay for a while */
636	udelay(100);
637	} else {
638	writel(readl(pi->mpsc_base + MPSC_CHR_2) \| MPSC_CHR_2_EH,
639	pi->mpsc_base + MPSC_CHR_2);
640
641	while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_EH)
642	udelay(10);
643	}
644	}
645
646	static void mpsc_freeze(struct mpsc_port_info *pi)
647	{
648	u32 v;
649
650	pr_debug("mpsc_freeze[%d]: Freezing\n", pi->port.line);
651
652	v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
653	readl(pi->mpsc_base + MPSC_MPCR);
654	v \|= MPSC_MPCR_FRZ;
655
656	if (pi->mirror_regs)
657	pi->MPSC_MPCR_m = v;
658	writel(v, pi->mpsc_base + MPSC_MPCR);
659	}
660
661	static void mpsc_unfreeze(struct mpsc_port_info *pi)
662	{
663	u32 v;
664
665	v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
666	readl(pi->mpsc_base + MPSC_MPCR);
667	v &= ~MPSC_MPCR_FRZ;
668
669	if (pi->mirror_regs)
670	pi->MPSC_MPCR_m = v;
671	writel(v, pi->mpsc_base + MPSC_MPCR);
672
673	pr_debug("mpsc_unfreeze[%d]: Unfrozen\n", pi->port.line);
674	}
675
676	static void mpsc_set_char_length(struct mpsc_port_info *pi, u32 len)
677	{
678	u32 v;
679
680	pr_debug("mpsc_set_char_length[%d]: char len: %d\n", pi->port.line,len);
681
682	v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
683	readl(pi->mpsc_base + MPSC_MPCR);
684	v = (v & ~(0x3 << 12)) \| ((len & 0x3) << 12);
685
686	if (pi->mirror_regs)
687	pi->MPSC_MPCR_m = v;
688	writel(v, pi->mpsc_base + MPSC_MPCR);
689	}
690
691	static void mpsc_set_stop_bit_length(struct mpsc_port_info *pi, u32 len)
692	{
693	u32 v;
694
695	pr_debug("mpsc_set_stop_bit_length[%d]: stop bits: %d\n",
696	pi->port.line, len);
697
698	v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
699	readl(pi->mpsc_base + MPSC_MPCR);
700
701	v = (v & ~(1 << 14)) \| ((len & 0x1) << 14);
702
703	if (pi->mirror_regs)
704	pi->MPSC_MPCR_m = v;
705	writel(v, pi->mpsc_base + MPSC_MPCR);
706	}
707
708	static void mpsc_set_parity(struct mpsc_port_info *pi, u32 p)
709	{
710	u32 v;
711
712	pr_debug("mpsc_set_parity[%d]: parity bits: 0x%x\n", pi->port.line, p);
713
714	v = (pi->mirror_regs) ? pi->MPSC_CHR_2_m :
715	readl(pi->mpsc_base + MPSC_CHR_2);
716
717	p &= 0x3;
718	v = (v & ~0xc000c) \| (p << 18) \| (p << 2);
719
720	if (pi->mirror_regs)
721	pi->MPSC_CHR_2_m = v;
722	writel(v, pi->mpsc_base + MPSC_CHR_2);
723	}
724
725	/*
726	******************************************************************************
727	*
728	* Driver Init Routines
729	*
730	******************************************************************************
731	*/
732
733	static void mpsc_init_hw(struct mpsc_port_info *pi)
734	{
735	pr_debug("mpsc_init_hw[%d]: Initializing\n", pi->port.line);
736
737	mpsc_brg_init(pi, pi->brg_clk_src);
738	mpsc_brg_enable(pi);
739	mpsc_sdma_init(pi, dma_get_cache_alignment()); /* burst a cacheline */
740	mpsc_sdma_stop(pi);
741	mpsc_hw_init(pi);
742	}
743
744	static int mpsc_alloc_ring_mem(struct mpsc_port_info *pi)
745	{
746	int rc = 0;
747
748	pr_debug("mpsc_alloc_ring_mem[%d]: Allocating ring mem\n",
749	pi->port.line);
750
751	if (!pi->dma_region) {
752	if (!dma_set_mask(pi->port.dev, 0xffffffff)) {
753	printk(KERN_ERR "MPSC: Inadequate DMA support\n");
754	rc = -ENXIO;
755	} else if ((pi->dma_region = dma_alloc_attrs(pi->port.dev,
756	MPSC_DMA_ALLOC_SIZE,
757	&pi->dma_region_p, GFP_KERNEL,
758	DMA_ATTR_NON_CONSISTENT))
759	== NULL) {
760	printk(KERN_ERR "MPSC: Can't alloc Desc region\n");
761	rc = -ENOMEM;
762	}
763	}
764
765	return rc;
766	}
767
768	static void mpsc_free_ring_mem(struct mpsc_port_info *pi)
769	{
770	pr_debug("mpsc_free_ring_mem[%d]: Freeing ring mem\n", pi->port.line);
771
772	if (pi->dma_region) {
773	dma_free_attrs(pi->port.dev, MPSC_DMA_ALLOC_SIZE,
774	pi->dma_region, pi->dma_region_p,
775	DMA_ATTR_NON_CONSISTENT);
776	pi->dma_region = NULL;
777	pi->dma_region_p = (dma_addr_t)NULL;
778	}
779	}
780
781	static void mpsc_init_rings(struct mpsc_port_info *pi)
782	{
783	struct mpsc_rx_desc *rxre;
784	struct mpsc_tx_desc *txre;
785	dma_addr_t dp, dp_p;
786	u8 bp, bp_p;
787	int i;
788
789	pr_debug("mpsc_init_rings[%d]: Initializing rings\n", pi->port.line);
790
791	BUG_ON(pi->dma_region == NULL);
792
793	memset(pi->dma_region, 0, MPSC_DMA_ALLOC_SIZE);
794
795	/*
796	* Descriptors & buffers are multiples of cacheline size and must be
797	* cacheline aligned.
798	*/
799	dp = ALIGN((u32)pi->dma_region, dma_get_cache_alignment());
800	dp_p = ALIGN((u32)pi->dma_region_p, dma_get_cache_alignment());
801
802	/*
803	* Partition dma region into rx ring descriptor, rx buffers,
804	* tx ring descriptors, and tx buffers.
805	*/
806	pi->rxr = dp;
807	pi->rxr_p = dp_p;
808	dp += MPSC_RXR_SIZE;
809	dp_p += MPSC_RXR_SIZE;
810
811	pi->rxb = (u8 *)dp;
812	pi->rxb_p = (u8 *)dp_p;
813	dp += MPSC_RXB_SIZE;
814	dp_p += MPSC_RXB_SIZE;
815
816	pi->rxr_posn = 0;
817
818	pi->txr = dp;
819	pi->txr_p = dp_p;
820	dp += MPSC_TXR_SIZE;
821	dp_p += MPSC_TXR_SIZE;
822
823	pi->txb = (u8 *)dp;
824	pi->txb_p = (u8 *)dp_p;
825
826	pi->txr_head = 0;
827	pi->txr_tail = 0;
828
829	/* Init rx ring descriptors */
830	dp = pi->rxr;
831	dp_p = pi->rxr_p;
832	bp = pi->rxb;
833	bp_p = pi->rxb_p;
834
835	for (i = 0; i < MPSC_RXR_ENTRIES; i++) {
836	rxre = (struct mpsc_rx_desc *)dp;
837
838	rxre->bufsize = cpu_to_be16(MPSC_RXBE_SIZE);
839	rxre->bytecnt = cpu_to_be16(0);
840	rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O
841	\| SDMA_DESC_CMDSTAT_EI \| SDMA_DESC_CMDSTAT_F
842	\| SDMA_DESC_CMDSTAT_L);
843	rxre->link = cpu_to_be32(dp_p + MPSC_RXRE_SIZE);
844	rxre->buf_ptr = cpu_to_be32(bp_p);
845
846	dp += MPSC_RXRE_SIZE;
847	dp_p += MPSC_RXRE_SIZE;
848	bp += MPSC_RXBE_SIZE;
849	bp_p += MPSC_RXBE_SIZE;
850	}
851	rxre->link = cpu_to_be32(pi->rxr_p); /* Wrap last back to first */
852
853	/* Init tx ring descriptors */
854	dp = pi->txr;
855	dp_p = pi->txr_p;
856	bp = pi->txb;
857	bp_p = pi->txb_p;
858
859	for (i = 0; i < MPSC_TXR_ENTRIES; i++) {
860	txre = (struct mpsc_tx_desc *)dp;
861
862	txre->link = cpu_to_be32(dp_p + MPSC_TXRE_SIZE);
863	txre->buf_ptr = cpu_to_be32(bp_p);
864
865	dp += MPSC_TXRE_SIZE;
866	dp_p += MPSC_TXRE_SIZE;
867	bp += MPSC_TXBE_SIZE;
868	bp_p += MPSC_TXBE_SIZE;
869	}
870	txre->link = cpu_to_be32(pi->txr_p); /* Wrap last back to first */
871
872	dma_cache_sync(pi->port.dev, (void *)pi->dma_region,
873	MPSC_DMA_ALLOC_SIZE, DMA_BIDIRECTIONAL);
874	#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
875	if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
876	flush_dcache_range((ulong)pi->dma_region,
877	(ulong)pi->dma_region
878	+ MPSC_DMA_ALLOC_SIZE);
879	#endif
880
881	return;
882	}
883
884	static void mpsc_uninit_rings(struct mpsc_port_info *pi)
885	{
886	pr_debug("mpsc_uninit_rings[%d]: Uninitializing rings\n",pi->port.line);
887
888	BUG_ON(pi->dma_region == NULL);
889
890	pi->rxr = 0;
891	pi->rxr_p = 0;
892	pi->rxb = NULL;
893	pi->rxb_p = NULL;
894	pi->rxr_posn = 0;
895
896	pi->txr = 0;
897	pi->txr_p = 0;
898	pi->txb = NULL;
899	pi->txb_p = NULL;
900	pi->txr_head = 0;
901	pi->txr_tail = 0;
902	}
903
904	static int mpsc_make_ready(struct mpsc_port_info *pi)
905	{
906	int rc;
907
908	pr_debug("mpsc_make_ready[%d]: Making cltr ready\n", pi->port.line);
909
910	if (!pi->ready) {
911	mpsc_init_hw(pi);
912	rc = mpsc_alloc_ring_mem(pi);
913	if (rc)
914	return rc;
915	mpsc_init_rings(pi);
916	pi->ready = 1;
917	}
918
919	return 0;
920	}
921
922	#ifdef CONFIG_CONSOLE_POLL
923	static int serial_polled;
924	#endif
925
926	/*
927	******************************************************************************
928	*
929	* Interrupt Handling Routines
930	*
931	******************************************************************************
932	*/
933
934	static int mpsc_rx_intr(struct mpsc_port_info pi, unsigned long flags)
935	{
936	struct mpsc_rx_desc *rxre;
937	struct tty_port *port = &pi->port.state->port;
938	u32 cmdstat, bytes_in, i;
939	int rc = 0;
940	u8 *bp;
941	char flag = TTY_NORMAL;
942
943	pr_debug("mpsc_rx_intr[%d]: Handling Rx intr\n", pi->port.line);
944
945	rxre = (struct mpsc_rx_desc )(pi->rxr + (pi->rxr_posnMPSC_RXRE_SIZE));
946
947	dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE,
948	DMA_FROM_DEVICE);
949	#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
950	if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
951	invalidate_dcache_range((ulong)rxre,
952	(ulong)rxre + MPSC_RXRE_SIZE);
953	#endif
954
955	/*
956	* Loop through Rx descriptors handling ones that have been completed.
957	*/
958	while (!((cmdstat = be32_to_cpu(rxre->cmdstat))
959	& SDMA_DESC_CMDSTAT_O)) {
960	bytes_in = be16_to_cpu(rxre->bytecnt);
961	#ifdef CONFIG_CONSOLE_POLL
962	if (unlikely(serial_polled)) {
963	serial_polled = 0;
964	return 0;
965	}
966	#endif
967	/* Following use of tty struct directly is deprecated */
968	if (tty_buffer_request_room(port, bytes_in) < bytes_in) {
969	if (port->low_latency) {
970	spin_unlock_irqrestore(&pi->port.lock, *flags);
971	tty_flip_buffer_push(port);
972	spin_lock_irqsave(&pi->port.lock, *flags);
973	}
974	/*
975	* If this failed then we will throw away the bytes
976	* but must do so to clear interrupts.
977	*/
978	}
979
980	bp = pi->rxb + (pi->rxr_posn * MPSC_RXBE_SIZE);
981	dma_cache_sync(pi->port.dev, (void *)bp, MPSC_RXBE_SIZE,
982	DMA_FROM_DEVICE);
983	#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
984	if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
985	invalidate_dcache_range((ulong)bp,
986	(ulong)bp + MPSC_RXBE_SIZE);
987	#endif
988
989	/*
990	* Other than for parity error, the manual provides little
991	* info on what data will be in a frame flagged by any of
992	* these errors. For parity error, it is the last byte in
993	* the buffer that had the error. As for the rest, I guess
994	* we'll assume there is no data in the buffer.
995	* If there is...it gets lost.
996	*/
997	if (unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR
998	\| SDMA_DESC_CMDSTAT_FR
999	\| SDMA_DESC_CMDSTAT_OR))) {
1000
1001	pi->port.icount.rx++;
1002
1003	if (cmdstat & SDMA_DESC_CMDSTAT_BR) { /* Break */
1004	pi->port.icount.brk++;
1005
1006	if (uart_handle_break(&pi->port))
1007	goto next_frame;
1008	} else if (cmdstat & SDMA_DESC_CMDSTAT_FR) {
1009	pi->port.icount.frame++;
1010	} else if (cmdstat & SDMA_DESC_CMDSTAT_OR) {
1011	pi->port.icount.overrun++;
1012	}
1013
1014	cmdstat &= pi->port.read_status_mask;
1015
1016	if (cmdstat & SDMA_DESC_CMDSTAT_BR)
1017	flag = TTY_BREAK;
1018	else if (cmdstat & SDMA_DESC_CMDSTAT_FR)
1019	flag = TTY_FRAME;
1020	else if (cmdstat & SDMA_DESC_CMDSTAT_OR)
1021	flag = TTY_OVERRUN;
1022	else if (cmdstat & SDMA_DESC_CMDSTAT_PE)
1023	flag = TTY_PARITY;
1024	}
1025
1026	if (uart_handle_sysrq_char(&pi->port, *bp)) {
1027	bp++;
1028	bytes_in--;
1029	#ifdef CONFIG_CONSOLE_POLL
1030	if (unlikely(serial_polled)) {
1031	serial_polled = 0;
1032	return 0;
1033	}
1034	#endif
1035	goto next_frame;
1036	}
1037
1038	if ((unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR
1039	\| SDMA_DESC_CMDSTAT_FR
1040	\| SDMA_DESC_CMDSTAT_OR)))
1041	&& !(cmdstat & pi->port.ignore_status_mask)) {
1042	tty_insert_flip_char(port, *bp, flag);
1043	} else {
1044	for (i=0; i<bytes_in; i++)
1045	tty_insert_flip_char(port, *bp++, TTY_NORMAL);
1046
1047	pi->port.icount.rx += bytes_in;
1048	}
1049
1050	next_frame:
1051	rxre->bytecnt = cpu_to_be16(0);
1052	wmb();
1053	rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O
1054	\| SDMA_DESC_CMDSTAT_EI \| SDMA_DESC_CMDSTAT_F
1055	\| SDMA_DESC_CMDSTAT_L);
1056	wmb();
1057	dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE,
1058	DMA_BIDIRECTIONAL);
1059	#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1060	if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1061	flush_dcache_range((ulong)rxre,
1062	(ulong)rxre + MPSC_RXRE_SIZE);
1063	#endif
1064
1065	/* Advance to next descriptor */
1066	pi->rxr_posn = (pi->rxr_posn + 1) & (MPSC_RXR_ENTRIES - 1);
1067	rxre = (struct mpsc_rx_desc *)
1068	(pi->rxr + (pi->rxr_posn * MPSC_RXRE_SIZE));
1069	dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE,
1070	DMA_FROM_DEVICE);
1071	#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1072	if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1073	invalidate_dcache_range((ulong)rxre,
1074	(ulong)rxre + MPSC_RXRE_SIZE);
1075	#endif
1076	rc = 1;
1077	}
1078
1079	/* Restart rx engine, if its stopped */
1080	if ((readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_ERD) == 0)
1081	mpsc_start_rx(pi);
1082
1083	spin_unlock_irqrestore(&pi->port.lock, *flags);
1084	tty_flip_buffer_push(port);
1085	spin_lock_irqsave(&pi->port.lock, *flags);
1086	return rc;
1087	}
1088
1089	static void mpsc_setup_tx_desc(struct mpsc_port_info *pi, u32 count, u32 intr)
1090	{
1091	struct mpsc_tx_desc *txre;
1092
1093	txre = (struct mpsc_tx_desc *)(pi->txr
1094	+ (pi->txr_head * MPSC_TXRE_SIZE));
1095
1096	txre->bytecnt = cpu_to_be16(count);
1097	txre->shadow = txre->bytecnt;
1098	wmb(); /* ensure cmdstat is last field updated */
1099	txre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O \| SDMA_DESC_CMDSTAT_F
1100	\| SDMA_DESC_CMDSTAT_L
1101	\| ((intr) ? SDMA_DESC_CMDSTAT_EI : 0));
1102	wmb();
1103	dma_cache_sync(pi->port.dev, (void *)txre, MPSC_TXRE_SIZE,
1104	DMA_BIDIRECTIONAL);
1105	#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1106	if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1107	flush_dcache_range((ulong)txre,
1108	(ulong)txre + MPSC_TXRE_SIZE);
1109	#endif
1110	}
1111
1112	static void mpsc_copy_tx_data(struct mpsc_port_info *pi)
1113	{
1114	struct circ_buf *xmit = &pi->port.state->xmit;
1115	u8 *bp;
1116	u32 i;
1117
1118	/* Make sure the desc ring isn't full */
1119	while (CIRC_CNT(pi->txr_head, pi->txr_tail, MPSC_TXR_ENTRIES)
1120	< (MPSC_TXR_ENTRIES - 1)) {
1121	if (pi->port.x_char) {
1122	/*
1123	* Ideally, we should use the TCS field in
1124	* CHR_1 to put the x_char out immediately but
1125	* errata prevents us from being able to read
1126	* CHR_2 to know that its safe to write to
1127	* CHR_1. Instead, just put it in-band with
1128	* all the other Tx data.
1129	*/
1130	bp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE);
1131	*bp = pi->port.x_char;
1132	pi->port.x_char = 0;
1133	i = 1;
1134	} else if (!uart_circ_empty(xmit)
1135	&& !uart_tx_stopped(&pi->port)) {
1136	i = min((u32)MPSC_TXBE_SIZE,
1137	(u32)uart_circ_chars_pending(xmit));
1138	i = min(i, (u32)CIRC_CNT_TO_END(xmit->head, xmit->tail,
1139	UART_XMIT_SIZE));
1140	bp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE);
1141	memcpy(bp, &xmit->buf[xmit->tail], i);
1142	xmit->tail = (xmit->tail + i) & (UART_XMIT_SIZE - 1);
1143
1144	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1145	uart_write_wakeup(&pi->port);
1146	} else { /* All tx data copied into ring bufs */
1147	return;
1148	}
1149
1150	dma_cache_sync(pi->port.dev, (void *)bp, MPSC_TXBE_SIZE,
1151	DMA_BIDIRECTIONAL);
1152	#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1153	if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1154	flush_dcache_range((ulong)bp,
1155	(ulong)bp + MPSC_TXBE_SIZE);
1156	#endif
1157	mpsc_setup_tx_desc(pi, i, 1);
1158
1159	/* Advance to next descriptor */
1160	pi->txr_head = (pi->txr_head + 1) & (MPSC_TXR_ENTRIES - 1);
1161	}
1162	}
1163
1164	static int mpsc_tx_intr(struct mpsc_port_info *pi)
1165	{
1166	struct mpsc_tx_desc *txre;
1167	int rc = 0;
1168	unsigned long iflags;
1169
1170	spin_lock_irqsave(&pi->tx_lock, iflags);
1171
1172	if (!mpsc_sdma_tx_active(pi)) {
1173	txre = (struct mpsc_tx_desc *)(pi->txr
1174	+ (pi->txr_tail * MPSC_TXRE_SIZE));
1175
1176	dma_cache_sync(pi->port.dev, (void *)txre, MPSC_TXRE_SIZE,
1177	DMA_FROM_DEVICE);
1178	#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1179	if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1180	invalidate_dcache_range((ulong)txre,
1181	(ulong)txre + MPSC_TXRE_SIZE);
1182	#endif
1183
1184	while (!(be32_to_cpu(txre->cmdstat) & SDMA_DESC_CMDSTAT_O)) {
1185	rc = 1;
1186	pi->port.icount.tx += be16_to_cpu(txre->bytecnt);
1187	pi->txr_tail = (pi->txr_tail+1) & (MPSC_TXR_ENTRIES-1);
1188
1189	/* If no more data to tx, fall out of loop */
1190	if (pi->txr_head == pi->txr_tail)
1191	break;
1192
1193	txre = (struct mpsc_tx_desc *)(pi->txr
1194	+ (pi->txr_tail * MPSC_TXRE_SIZE));
1195	dma_cache_sync(pi->port.dev, (void *)txre,
1196	MPSC_TXRE_SIZE, DMA_FROM_DEVICE);
1197	#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1198	if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1199	invalidate_dcache_range((ulong)txre,
1200	(ulong)txre + MPSC_TXRE_SIZE);
1201	#endif
1202	}
1203
1204	mpsc_copy_tx_data(pi);
1205	mpsc_sdma_start_tx(pi); /* start next desc if ready */
1206	}
1207
1208	spin_unlock_irqrestore(&pi->tx_lock, iflags);
1209	return rc;
1210	}
1211
1212	/*
1213	* This is the driver's interrupt handler. To avoid a race, we first clear
1214	* the interrupt, then handle any completed Rx/Tx descriptors. When done
1215	* handling those descriptors, we restart the Rx/Tx engines if they're stopped.
1216	*/
1217	static irqreturn_t mpsc_sdma_intr(int irq, void *dev_id)
1218	{
1219	struct mpsc_port_info *pi = dev_id;
1220	ulong iflags;
1221	int rc = IRQ_NONE;
1222
1223	pr_debug("mpsc_sdma_intr[%d]: SDMA Interrupt Received\n",pi->port.line);
1224
1225	spin_lock_irqsave(&pi->port.lock, iflags);
1226	mpsc_sdma_intr_ack(pi);
1227	if (mpsc_rx_intr(pi, &iflags))
1228	rc = IRQ_HANDLED;
1229	if (mpsc_tx_intr(pi))
1230	rc = IRQ_HANDLED;
1231	spin_unlock_irqrestore(&pi->port.lock, iflags);
1232
1233	pr_debug("mpsc_sdma_intr[%d]: SDMA Interrupt Handled\n", pi->port.line);
1234	return rc;
1235	}
1236
1237	/*
1238	******************************************************************************
1239	*
1240	* serial_core.c Interface routines
1241	*
1242	******************************************************************************
1243	*/
1244	static uint mpsc_tx_empty(struct uart_port *port)
1245	{
1246	struct mpsc_port_info *pi =
1247	container_of(port, struct mpsc_port_info, port);
1248	ulong iflags;
1249	uint rc;
1250
1251	spin_lock_irqsave(&pi->port.lock, iflags);
1252	rc = mpsc_sdma_tx_active(pi) ? 0 : TIOCSER_TEMT;
1253	spin_unlock_irqrestore(&pi->port.lock, iflags);
1254
1255	return rc;
1256	}
1257
1258	static void mpsc_set_mctrl(struct uart_port *port, uint mctrl)
1259	{
1260	/* Have no way to set modem control lines AFAICT */
1261	}
1262
1263	static uint mpsc_get_mctrl(struct uart_port *port)
1264	{
1265	struct mpsc_port_info *pi =
1266	container_of(port, struct mpsc_port_info, port);
1267	u32 mflags, status;
1268
1269	status = (pi->mirror_regs) ? pi->MPSC_CHR_10_m
1270	: readl(pi->mpsc_base + MPSC_CHR_10);
1271
1272	mflags = 0;
1273	if (status & 0x1)
1274	mflags \|= TIOCM_CTS;
1275	if (status & 0x2)
1276	mflags \|= TIOCM_CAR;
1277
1278	return mflags \| TIOCM_DSR; /* No way to tell if DSR asserted */
1279	}
1280
1281	static void mpsc_stop_tx(struct uart_port *port)
1282	{
1283	struct mpsc_port_info *pi =
1284	container_of(port, struct mpsc_port_info, port);
1285
1286	pr_debug("mpsc_stop_tx[%d]\n", port->line);
1287
1288	mpsc_freeze(pi);
1289	}
1290
1291	static void mpsc_start_tx(struct uart_port *port)
1292	{
1293	struct mpsc_port_info *pi =
1294	container_of(port, struct mpsc_port_info, port);
1295	unsigned long iflags;
1296
1297	spin_lock_irqsave(&pi->tx_lock, iflags);
1298
1299	mpsc_unfreeze(pi);
1300	mpsc_copy_tx_data(pi);
1301	mpsc_sdma_start_tx(pi);
1302
1303	spin_unlock_irqrestore(&pi->tx_lock, iflags);
1304
1305	pr_debug("mpsc_start_tx[%d]\n", port->line);
1306	}
1307
1308	static void mpsc_start_rx(struct mpsc_port_info *pi)
1309	{
1310	pr_debug("mpsc_start_rx[%d]: Starting...\n", pi->port.line);
1311
1312	if (pi->rcv_data) {
1313	mpsc_enter_hunt(pi);
1314	mpsc_sdma_cmd(pi, SDMA_SDCM_ERD);
1315	}
1316	}
1317
1318	static void mpsc_stop_rx(struct uart_port *port)
1319	{
1320	struct mpsc_port_info *pi =
1321	container_of(port, struct mpsc_port_info, port);
1322
1323	pr_debug("mpsc_stop_rx[%d]: Stopping...\n", port->line);
1324
1325	if (pi->mirror_regs) {
1326	writel(pi->MPSC_CHR_2_m \| MPSC_CHR_2_RA,
1327	pi->mpsc_base + MPSC_CHR_2);
1328	/* Erratum prevents reading CHR_2 so just delay for a while */
1329	udelay(100);
1330	} else {
1331	writel(readl(pi->mpsc_base + MPSC_CHR_2) \| MPSC_CHR_2_RA,
1332	pi->mpsc_base + MPSC_CHR_2);
1333
1334	while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_RA)
1335	udelay(10);
1336	}
1337
1338	mpsc_sdma_cmd(pi, SDMA_SDCM_AR);
1339	}
1340
1341	static void mpsc_break_ctl(struct uart_port *port, int ctl)
1342	{
1343	struct mpsc_port_info *pi =
1344	container_of(port, struct mpsc_port_info, port);
1345	ulong flags;
1346	u32 v;
1347
1348	v = ctl ? 0x00ff0000 : 0;
1349
1350	spin_lock_irqsave(&pi->port.lock, flags);
1351	if (pi->mirror_regs)
1352	pi->MPSC_CHR_1_m = v;
1353	writel(v, pi->mpsc_base + MPSC_CHR_1);
1354	spin_unlock_irqrestore(&pi->port.lock, flags);
1355	}
1356
1357	static int mpsc_startup(struct uart_port *port)
1358	{
1359	struct mpsc_port_info *pi =
1360	container_of(port, struct mpsc_port_info, port);
1361	u32 flag = 0;
1362	int rc;
1363
1364	pr_debug("mpsc_startup[%d]: Starting up MPSC, irq: %d\n",
1365	port->line, pi->port.irq);
1366
1367	if ((rc = mpsc_make_ready(pi)) == 0) {
1368	/* Setup IRQ handler */
1369	mpsc_sdma_intr_ack(pi);
1370
1371	/* If irq's are shared, need to set flag */
1372	if (mpsc_ports[0].port.irq == mpsc_ports[1].port.irq)
1373	flag = IRQF_SHARED;
1374
1375	if (request_irq(pi->port.irq, mpsc_sdma_intr, flag,
1376	"mpsc-sdma", pi))
1377	printk(KERN_ERR "MPSC: Can't get SDMA IRQ %d\n",
1378	pi->port.irq);
1379
1380	mpsc_sdma_intr_unmask(pi, 0xf);
1381	mpsc_sdma_set_rx_ring(pi, (struct mpsc_rx_desc *)(pi->rxr_p
1382	+ (pi->rxr_posn * MPSC_RXRE_SIZE)));
1383	}
1384
1385	return rc;
1386	}
1387
1388	static void mpsc_shutdown(struct uart_port *port)
1389	{
1390	struct mpsc_port_info *pi =
1391	container_of(port, struct mpsc_port_info, port);
1392
1393	pr_debug("mpsc_shutdown[%d]: Shutting down MPSC\n", port->line);
1394
1395	mpsc_sdma_stop(pi);
1396	free_irq(pi->port.irq, pi);
1397	}
1398
1399	static void mpsc_set_termios(struct uart_port port, struct ktermios termios,
1400	struct ktermios *old)
1401	{
1402	struct mpsc_port_info *pi =
1403	container_of(port, struct mpsc_port_info, port);
1404	u32 baud;
1405	ulong flags;
1406	u32 chr_bits, stop_bits, par;
1407
1408	switch (termios->c_cflag & CSIZE) {
1409	case CS5:
1410	chr_bits = MPSC_MPCR_CL_5;
1411	break;
1412	case CS6:
1413	chr_bits = MPSC_MPCR_CL_6;
1414	break;
1415	case CS7:
1416	chr_bits = MPSC_MPCR_CL_7;
1417	break;
1418	case CS8:
1419	default:
1420	chr_bits = MPSC_MPCR_CL_8;
1421	break;
1422	}
1423
1424	if (termios->c_cflag & CSTOPB)
1425	stop_bits = MPSC_MPCR_SBL_2;
1426	else
1427	stop_bits = MPSC_MPCR_SBL_1;
1428
1429	par = MPSC_CHR_2_PAR_EVEN;
1430	if (termios->c_cflag & PARENB)
1431	if (termios->c_cflag & PARODD)
1432	par = MPSC_CHR_2_PAR_ODD;
1433	#ifdef CMSPAR
1434	if (termios->c_cflag & CMSPAR) {
1435	if (termios->c_cflag & PARODD)
1436	par = MPSC_CHR_2_PAR_MARK;
1437	else
1438	par = MPSC_CHR_2_PAR_SPACE;
1439	}
1440	#endif
1441
1442	baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk);
1443
1444	spin_lock_irqsave(&pi->port.lock, flags);
1445
1446	uart_update_timeout(port, termios->c_cflag, baud);
1447
1448	mpsc_set_char_length(pi, chr_bits);
1449	mpsc_set_stop_bit_length(pi, stop_bits);
1450	mpsc_set_parity(pi, par);
1451	mpsc_set_baudrate(pi, baud);
1452
1453	/* Characters/events to read */
1454	pi->port.read_status_mask = SDMA_DESC_CMDSTAT_OR;
1455
1456	if (termios->c_iflag & INPCK)
1457	pi->port.read_status_mask \|= SDMA_DESC_CMDSTAT_PE
1458	\| SDMA_DESC_CMDSTAT_FR;
1459
1460	if (termios->c_iflag & (IGNBRK \| BRKINT \| PARMRK))
1461	pi->port.read_status_mask \|= SDMA_DESC_CMDSTAT_BR;
1462
1463	/* Characters/events to ignore */
1464	pi->port.ignore_status_mask = 0;
1465
1466	if (termios->c_iflag & IGNPAR)
1467	pi->port.ignore_status_mask \|= SDMA_DESC_CMDSTAT_PE
1468	\| SDMA_DESC_CMDSTAT_FR;
1469
1470	if (termios->c_iflag & IGNBRK) {
1471	pi->port.ignore_status_mask \|= SDMA_DESC_CMDSTAT_BR;
1472
1473	if (termios->c_iflag & IGNPAR)
1474	pi->port.ignore_status_mask \|= SDMA_DESC_CMDSTAT_OR;
1475	}
1476
1477	if ((termios->c_cflag & CREAD)) {
1478	if (!pi->rcv_data) {
1479	pi->rcv_data = 1;
1480	mpsc_start_rx(pi);
1481	}
1482	} else if (pi->rcv_data) {
1483	mpsc_stop_rx(port);
1484	pi->rcv_data = 0;
1485	}
1486
1487	spin_unlock_irqrestore(&pi->port.lock, flags);
1488	}
1489
1490	static const char mpsc_type(struct uart_port port)
1491	{
1492	pr_debug("mpsc_type[%d]: port type: %s\n", port->line,MPSC_DRIVER_NAME);
1493	return MPSC_DRIVER_NAME;
1494	}
1495
1496	static int mpsc_request_port(struct uart_port *port)
1497	{
1498	/* Should make chip/platform specific call */
1499	return 0;
1500	}
1501
1502	static void mpsc_release_port(struct uart_port *port)
1503	{
1504	struct mpsc_port_info *pi =
1505	container_of(port, struct mpsc_port_info, port);
1506
1507	if (pi->ready) {
1508	mpsc_uninit_rings(pi);
1509	mpsc_free_ring_mem(pi);
1510	pi->ready = 0;
1511	}
1512	}
1513
1514	static void mpsc_config_port(struct uart_port *port, int flags)
1515	{
1516	}
1517
1518	static int mpsc_verify_port(struct uart_port port, struct serial_struct ser)
1519	{
1520	struct mpsc_port_info *pi =
1521	container_of(port, struct mpsc_port_info, port);
1522	int rc = 0;
1523
1524	pr_debug("mpsc_verify_port[%d]: Verifying port data\n", pi->port.line);
1525
1526	if (ser->type != PORT_UNKNOWN && ser->type != PORT_MPSC)
1527	rc = -EINVAL;
1528	else if (pi->port.irq != ser->irq)
1529	rc = -EINVAL;
1530	else if (ser->io_type != SERIAL_IO_MEM)
1531	rc = -EINVAL;
1532	else if (pi->port.uartclk / 16 != ser->baud_base) /* Not sure */
1533	rc = -EINVAL;
1534	else if ((void *)pi->port.mapbase != ser->iomem_base)
1535	rc = -EINVAL;
1536	else if (pi->port.iobase != ser->port)
1537	rc = -EINVAL;
1538	else if (ser->hub6 != 0)
1539	rc = -EINVAL;
1540
1541	return rc;
1542	}
1543	#ifdef CONFIG_CONSOLE_POLL
1544	/* Serial polling routines for writing and reading from the uart while
1545	* in an interrupt or debug context.
1546	*/
1547
1548	static char poll_buf[2048];
1549	static int poll_ptr;
1550	static int poll_cnt;
1551	static void mpsc_put_poll_char(struct uart_port *port,
1552	unsigned char c);
1553
1554	static int mpsc_get_poll_char(struct uart_port *port)
1555	{
1556	struct mpsc_port_info *pi =
1557	container_of(port, struct mpsc_port_info, port);
1558	struct mpsc_rx_desc *rxre;
1559	u32 cmdstat, bytes_in, i;
1560	u8 *bp;
1561
1562	if (!serial_polled)
1563	serial_polled = 1;
1564
1565	pr_debug("mpsc_rx_intr[%d]: Handling Rx intr\n", pi->port.line);
1566
1567	if (poll_cnt) {
1568	poll_cnt--;
1569	return poll_buf[poll_ptr++];
1570	}
1571	poll_ptr = 0;
1572	poll_cnt = 0;
1573
1574	while (poll_cnt == 0) {
1575	rxre = (struct mpsc_rx_desc *)(pi->rxr +
1576	(pi->rxr_posn*MPSC_RXRE_SIZE));
1577	dma_cache_sync(pi->port.dev, (void *)rxre,
1578	MPSC_RXRE_SIZE, DMA_FROM_DEVICE);
1579	#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1580	if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1581	invalidate_dcache_range((ulong)rxre,
1582	(ulong)rxre + MPSC_RXRE_SIZE);
1583	#endif
1584	/*
1585	* Loop through Rx descriptors handling ones that have
1586	* been completed.
1587	*/
1588	while (poll_cnt == 0 &&
1589	!((cmdstat = be32_to_cpu(rxre->cmdstat)) &
1590	SDMA_DESC_CMDSTAT_O)){
1591	bytes_in = be16_to_cpu(rxre->bytecnt);
1592	bp = pi->rxb + (pi->rxr_posn * MPSC_RXBE_SIZE);
1593	dma_cache_sync(pi->port.dev, (void *) bp,
1594	MPSC_RXBE_SIZE, DMA_FROM_DEVICE);
1595	#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1596	if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1597	invalidate_dcache_range((ulong)bp,
1598	(ulong)bp + MPSC_RXBE_SIZE);
1599	#endif
1600	if ((unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR \|
1601	SDMA_DESC_CMDSTAT_FR \| SDMA_DESC_CMDSTAT_OR))) &&
1602	!(cmdstat & pi->port.ignore_status_mask)) {
1603	poll_buf[poll_cnt] = *bp;
1604	poll_cnt++;
1605	} else {
1606	for (i = 0; i < bytes_in; i++) {
1607	poll_buf[poll_cnt] = *bp++;
1608	poll_cnt++;
1609	}
1610	pi->port.icount.rx += bytes_in;
1611	}
1612	rxre->bytecnt = cpu_to_be16(0);
1613	wmb();
1614	rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O \|
1615	SDMA_DESC_CMDSTAT_EI \|
1616	SDMA_DESC_CMDSTAT_F \|
1617	SDMA_DESC_CMDSTAT_L);
1618	wmb();
1619	dma_cache_sync(pi->port.dev, (void *)rxre,
1620	MPSC_RXRE_SIZE, DMA_BIDIRECTIONAL);
1621	#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1622	if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1623	flush_dcache_range((ulong)rxre,
1624	(ulong)rxre + MPSC_RXRE_SIZE);
1625	#endif
1626
1627	/* Advance to next descriptor */
1628	pi->rxr_posn = (pi->rxr_posn + 1) &
1629	(MPSC_RXR_ENTRIES - 1);
1630	rxre = (struct mpsc_rx_desc *)(pi->rxr +
1631	(pi->rxr_posn * MPSC_RXRE_SIZE));
1632	dma_cache_sync(pi->port.dev, (void *)rxre,
1633	MPSC_RXRE_SIZE, DMA_FROM_DEVICE);
1634	#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1635	if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1636	invalidate_dcache_range((ulong)rxre,
1637	(ulong)rxre + MPSC_RXRE_SIZE);
1638	#endif
1639	}
1640
1641	/* Restart rx engine, if its stopped */
1642	if ((readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_ERD) == 0)
1643	mpsc_start_rx(pi);
1644	}
1645	if (poll_cnt) {
1646	poll_cnt--;
1647	return poll_buf[poll_ptr++];
1648	}
1649
1650	return 0;
1651	}
1652
1653
1654	static void mpsc_put_poll_char(struct uart_port *port,
1655	unsigned char c)
1656	{
1657	struct mpsc_port_info *pi =
1658	container_of(port, struct mpsc_port_info, port);
1659	u32 data;
1660
1661	data = readl(pi->mpsc_base + MPSC_MPCR);
1662	writeb(c, pi->mpsc_base + MPSC_CHR_1);
1663	mb();
1664	data = readl(pi->mpsc_base + MPSC_CHR_2);
1665	data \|= MPSC_CHR_2_TTCS;
1666	writel(data, pi->mpsc_base + MPSC_CHR_2);
1667	mb();
1668
1669	while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_TTCS);
1670	}
1671	#endif
1672
1673	static const struct uart_ops mpsc_pops = {
1674	.tx_empty = mpsc_tx_empty,
1675	.set_mctrl = mpsc_set_mctrl,
1676	.get_mctrl = mpsc_get_mctrl,
1677	.stop_tx = mpsc_stop_tx,
1678	.start_tx = mpsc_start_tx,
1679	.stop_rx = mpsc_stop_rx,
1680	.break_ctl = mpsc_break_ctl,
1681	.startup = mpsc_startup,
1682	.shutdown = mpsc_shutdown,
1683	.set_termios = mpsc_set_termios,
1684	.type = mpsc_type,
1685	.release_port = mpsc_release_port,
1686	.request_port = mpsc_request_port,
1687	.config_port = mpsc_config_port,
1688	.verify_port = mpsc_verify_port,
1689	#ifdef CONFIG_CONSOLE_POLL
1690	.poll_get_char = mpsc_get_poll_char,
1691	.poll_put_char = mpsc_put_poll_char,
1692	#endif
1693	};
1694
1695	/*
1696	******************************************************************************
1697	*
1698	* Console Interface Routines
1699	*
1700	******************************************************************************
1701	*/
1702
1703	#ifdef CONFIG_SERIAL_MPSC_CONSOLE
1704	static void mpsc_console_write(struct console co, const char s, uint count)
1705	{
1706	struct mpsc_port_info *pi = &mpsc_ports[co->index];
1707	u8 bp, dp, add_cr = 0;
1708	int i;
1709	unsigned long iflags;
1710
1711	spin_lock_irqsave(&pi->tx_lock, iflags);
1712
1713	while (pi->txr_head != pi->txr_tail) {
1714	while (mpsc_sdma_tx_active(pi))
1715	udelay(100);
1716	mpsc_sdma_intr_ack(pi);
1717	mpsc_tx_intr(pi);
1718	}
1719
1720	while (mpsc_sdma_tx_active(pi))
1721	udelay(100);
1722
1723	while (count > 0) {
1724	bp = dp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE);
1725
1726	for (i = 0; i < MPSC_TXBE_SIZE; i++) {
1727	if (count == 0)
1728	break;
1729
1730	if (add_cr) {
1731	*(dp++) = '\r';
1732	add_cr = 0;
1733	} else {
1734	(dp++) = s;
1735
1736	if ((s++) == '\n') { / add '\r' after '\n' */
1737	add_cr = 1;
1738	count++;
1739	}
1740	}
1741
1742	count--;
1743	}
1744
1745	dma_cache_sync(pi->port.dev, (void *)bp, MPSC_TXBE_SIZE,
1746	DMA_BIDIRECTIONAL);
1747	#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1748	if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1749	flush_dcache_range((ulong)bp,
1750	(ulong)bp + MPSC_TXBE_SIZE);
1751	#endif
1752	mpsc_setup_tx_desc(pi, i, 0);
1753	pi->txr_head = (pi->txr_head + 1) & (MPSC_TXR_ENTRIES - 1);
1754	mpsc_sdma_start_tx(pi);
1755
1756	while (mpsc_sdma_tx_active(pi))
1757	udelay(100);
1758
1759	pi->txr_tail = (pi->txr_tail + 1) & (MPSC_TXR_ENTRIES - 1);
1760	}
1761
1762	spin_unlock_irqrestore(&pi->tx_lock, iflags);
1763	}
1764
1765	static int __init mpsc_console_setup(struct console co, char options)
1766	{
1767	struct mpsc_port_info *pi;
1768	int baud, bits, parity, flow;
1769
1770	pr_debug("mpsc_console_setup[%d]: options: %s\n", co->index, options);
1771
1772	if (co->index >= MPSC_NUM_CTLRS)
1773	co->index = 0;
1774
1775	pi = &mpsc_ports[co->index];
1776
1777	baud = pi->default_baud;
1778	bits = pi->default_bits;
1779	parity = pi->default_parity;
1780	flow = pi->default_flow;
1781
1782	if (!pi->port.ops)
1783	return -ENODEV;
1784
1785	spin_lock_init(&pi->port.lock); /* Temporary fix--copied from 8250.c */
1786
1787	if (options)
1788	uart_parse_options(options, &baud, &parity, &bits, &flow);
1789
1790	return uart_set_options(&pi->port, co, baud, parity, bits, flow);
1791	}
1792
1793	static struct console mpsc_console = {
1794	.name = MPSC_DEV_NAME,
1795	.write = mpsc_console_write,
1796	.device = uart_console_device,
1797	.setup = mpsc_console_setup,
1798	.flags = CON_PRINTBUFFER,
1799	.index = -1,
1800	.data = &mpsc_reg,
1801	};
1802
1803	static int __init mpsc_late_console_init(void)
1804	{
1805	pr_debug("mpsc_late_console_init: Enter\n");
1806
1807	if (!(mpsc_console.flags & CON_ENABLED))
1808	register_console(&mpsc_console);
1809	return 0;
1810	}
1811
1812	late_initcall(mpsc_late_console_init);
1813
1814	#define MPSC_CONSOLE &mpsc_console
1815	#else
1816	#define MPSC_CONSOLE NULL
1817	#endif
1818	/*
1819	******************************************************************************
1820	*
1821	* Dummy Platform Driver to extract & map shared register regions
1822	*
1823	******************************************************************************
1824	*/
1825	static void mpsc_resource_err(char *s)
1826	{
1827	printk(KERN_WARNING "MPSC: Platform device resource error in %s\n", s);
1828	}
1829
1830	static int mpsc_shared_map_regs(struct platform_device *pd)
1831	{
1832	struct resource *r;
1833
1834	if ((r = platform_get_resource(pd, IORESOURCE_MEM,
1835	MPSC_ROUTING_BASE_ORDER))
1836	&& request_mem_region(r->start,
1837	MPSC_ROUTING_REG_BLOCK_SIZE,
1838	"mpsc_routing_regs")) {
1839	mpsc_shared_regs.mpsc_routing_base = ioremap(r->start,
1840	MPSC_ROUTING_REG_BLOCK_SIZE);
1841	mpsc_shared_regs.mpsc_routing_base_p = r->start;
1842	} else {
1843	mpsc_resource_err("MPSC routing base");
1844	return -ENOMEM;
1845	}
1846
1847	if ((r = platform_get_resource(pd, IORESOURCE_MEM,
1848	MPSC_SDMA_INTR_BASE_ORDER))
1849	&& request_mem_region(r->start,
1850	MPSC_SDMA_INTR_REG_BLOCK_SIZE,
1851	"sdma_intr_regs")) {
1852	mpsc_shared_regs.sdma_intr_base = ioremap(r->start,
1853	MPSC_SDMA_INTR_REG_BLOCK_SIZE);
1854	mpsc_shared_regs.sdma_intr_base_p = r->start;
1855	} else {
1856	iounmap(mpsc_shared_regs.mpsc_routing_base);
1857	release_mem_region(mpsc_shared_regs.mpsc_routing_base_p,
1858	MPSC_ROUTING_REG_BLOCK_SIZE);
1859	mpsc_resource_err("SDMA intr base");
1860	return -ENOMEM;
1861	}
1862
1863	return 0;
1864	}
1865
1866	static void mpsc_shared_unmap_regs(void)
1867	{
1868	if (mpsc_shared_regs.mpsc_routing_base) {
1869	iounmap(mpsc_shared_regs.mpsc_routing_base);
1870	release_mem_region(mpsc_shared_regs.mpsc_routing_base_p,
1871	MPSC_ROUTING_REG_BLOCK_SIZE);
1872	}
1873	if (mpsc_shared_regs.sdma_intr_base) {
1874	iounmap(mpsc_shared_regs.sdma_intr_base);
1875	release_mem_region(mpsc_shared_regs.sdma_intr_base_p,
1876	MPSC_SDMA_INTR_REG_BLOCK_SIZE);
1877	}
1878
1879	mpsc_shared_regs.mpsc_routing_base = NULL;
1880	mpsc_shared_regs.sdma_intr_base = NULL;
1881
1882	mpsc_shared_regs.mpsc_routing_base_p = 0;
1883	mpsc_shared_regs.sdma_intr_base_p = 0;
1884	}
1885
1886	static int mpsc_shared_drv_probe(struct platform_device *dev)
1887	{
1888	struct mpsc_shared_pdata *pdata;
1889	int rc;
1890
1891	if (dev->id != 0)
1892	return -ENODEV;
1893
1894	rc = mpsc_shared_map_regs(dev);
1895	if (rc)
1896	return rc;
1897
1898	pdata = dev_get_platdata(&dev->dev);
1899
1900	mpsc_shared_regs.MPSC_MRR_m = pdata->mrr_val;
1901	mpsc_shared_regs.MPSC_RCRR_m= pdata->rcrr_val;
1902	mpsc_shared_regs.MPSC_TCRR_m= pdata->tcrr_val;
1903	mpsc_shared_regs.SDMA_INTR_CAUSE_m = pdata->intr_cause_val;
1904	mpsc_shared_regs.SDMA_INTR_MASK_m = pdata->intr_mask_val;
1905
1906	return 0;
1907	}
1908
1909	static int mpsc_shared_drv_remove(struct platform_device *dev)
1910	{
1911	if (dev->id != 0)
1912	return -ENODEV;
1913
1914	mpsc_shared_unmap_regs();
1915	mpsc_shared_regs.MPSC_MRR_m = 0;
1916	mpsc_shared_regs.MPSC_RCRR_m = 0;
1917	mpsc_shared_regs.MPSC_TCRR_m = 0;
1918	mpsc_shared_regs.SDMA_INTR_CAUSE_m = 0;
1919	mpsc_shared_regs.SDMA_INTR_MASK_m = 0;
1920
1921	return 0;
1922	}
1923
1924	static struct platform_driver mpsc_shared_driver = {
1925	.probe = mpsc_shared_drv_probe,
1926	.remove = mpsc_shared_drv_remove,
1927	.driver = {
1928	.name = MPSC_SHARED_NAME,
1929	},
1930	};
1931
1932	/*
1933	******************************************************************************
1934	*
1935	* Driver Interface Routines
1936	*
1937	******************************************************************************
1938	*/
1939	static struct uart_driver mpsc_reg = {
1940	.owner = THIS_MODULE,
1941	.driver_name = MPSC_DRIVER_NAME,
1942	.dev_name = MPSC_DEV_NAME,
1943	.major = MPSC_MAJOR,
1944	.minor = MPSC_MINOR_START,
1945	.nr = MPSC_NUM_CTLRS,
1946	.cons = MPSC_CONSOLE,
1947	};
1948
1949	static int mpsc_drv_map_regs(struct mpsc_port_info *pi,
1950	struct platform_device *pd)
1951	{
1952	struct resource *r;
1953
1954	if ((r = platform_get_resource(pd, IORESOURCE_MEM, MPSC_BASE_ORDER))
1955	&& request_mem_region(r->start, MPSC_REG_BLOCK_SIZE,
1956	"mpsc_regs")) {
1957	pi->mpsc_base = ioremap(r->start, MPSC_REG_BLOCK_SIZE);
1958	pi->mpsc_base_p = r->start;
1959	} else {
1960	mpsc_resource_err("MPSC base");
1961	goto err;
1962	}
1963
1964	if ((r = platform_get_resource(pd, IORESOURCE_MEM,
1965	MPSC_SDMA_BASE_ORDER))
1966	&& request_mem_region(r->start,
1967	MPSC_SDMA_REG_BLOCK_SIZE, "sdma_regs")) {
1968	pi->sdma_base = ioremap(r->start,MPSC_SDMA_REG_BLOCK_SIZE);
1969	pi->sdma_base_p = r->start;
1970	} else {
1971	mpsc_resource_err("SDMA base");
1972	goto err;
1973	}
1974
1975	if ((r = platform_get_resource(pd,IORESOURCE_MEM,MPSC_BRG_BASE_ORDER))
1976	&& request_mem_region(r->start,
1977	MPSC_BRG_REG_BLOCK_SIZE, "brg_regs")) {
1978	pi->brg_base = ioremap(r->start, MPSC_BRG_REG_BLOCK_SIZE);
1979	pi->brg_base_p = r->start;
1980	} else {
1981	mpsc_resource_err("BRG base");
1982	goto err;
1983	}
1984	return 0;
1985
1986	err:
1987	if (pi->sdma_base) {
1988	iounmap(pi->sdma_base);
1989	pi->sdma_base = NULL;
1990	}
1991	if (pi->mpsc_base) {
1992	iounmap(pi->mpsc_base);
1993	pi->mpsc_base = NULL;
1994	}
1995	return -ENOMEM;
1996	}
1997
1998	static void mpsc_drv_unmap_regs(struct mpsc_port_info *pi)
1999	{
2000	if (pi->mpsc_base) {
2001	iounmap(pi->mpsc_base);
2002	release_mem_region(pi->mpsc_base_p, MPSC_REG_BLOCK_SIZE);
2003	}
2004	if (pi->sdma_base) {
2005	iounmap(pi->sdma_base);
2006	release_mem_region(pi->sdma_base_p, MPSC_SDMA_REG_BLOCK_SIZE);
2007	}
2008	if (pi->brg_base) {
2009	iounmap(pi->brg_base);
2010	release_mem_region(pi->brg_base_p, MPSC_BRG_REG_BLOCK_SIZE);
2011	}
2012
2013	pi->mpsc_base = NULL;
2014	pi->sdma_base = NULL;
2015	pi->brg_base = NULL;
2016
2017	pi->mpsc_base_p = 0;
2018	pi->sdma_base_p = 0;
2019	pi->brg_base_p = 0;
2020	}
2021
2022	static void mpsc_drv_get_platform_data(struct mpsc_port_info *pi,
2023	struct platform_device *pd, int num)
2024	{
2025	struct mpsc_pdata *pdata;
2026
2027	pdata = dev_get_platdata(&pd->dev);
2028
2029	pi->port.uartclk = pdata->brg_clk_freq;
2030	pi->port.iotype = UPIO_MEM;
2031	pi->port.line = num;
2032	pi->port.type = PORT_MPSC;
2033	pi->port.fifosize = MPSC_TXBE_SIZE;
2034	pi->port.membase = pi->mpsc_base;
2035	pi->port.mapbase = (ulong)pi->mpsc_base;
2036	pi->port.ops = &mpsc_pops;
2037
2038	pi->mirror_regs = pdata->mirror_regs;
2039	pi->cache_mgmt = pdata->cache_mgmt;
2040	pi->brg_can_tune = pdata->brg_can_tune;
2041	pi->brg_clk_src = pdata->brg_clk_src;
2042	pi->mpsc_max_idle = pdata->max_idle;
2043	pi->default_baud = pdata->default_baud;
2044	pi->default_bits = pdata->default_bits;
2045	pi->default_parity = pdata->default_parity;
2046	pi->default_flow = pdata->default_flow;
2047
2048	/* Initial values of mirrored regs */
2049	pi->MPSC_CHR_1_m = pdata->chr_1_val;
2050	pi->MPSC_CHR_2_m = pdata->chr_2_val;
2051	pi->MPSC_CHR_10_m = pdata->chr_10_val;
2052	pi->MPSC_MPCR_m = pdata->mpcr_val;
2053	pi->BRG_BCR_m = pdata->bcr_val;
2054
2055	pi->shared_regs = &mpsc_shared_regs;
2056
2057	pi->port.irq = platform_get_irq(pd, 0);
2058	}
2059
2060	static int mpsc_drv_probe(struct platform_device *dev)
2061	{
2062	struct mpsc_port_info *pi;
2063	int rc;
2064
2065	dev_dbg(&dev->dev, "mpsc_drv_probe: Adding MPSC %d\n", dev->id);
2066
2067	if (dev->id >= MPSC_NUM_CTLRS)
2068	return -ENODEV;
2069
2070	pi = &mpsc_ports[dev->id];
2071
2072	rc = mpsc_drv_map_regs(pi, dev);
2073	if (rc)
2074	return rc;
2075
2076	mpsc_drv_get_platform_data(pi, dev, dev->id);
2077	pi->port.dev = &dev->dev;
2078
2079	rc = mpsc_make_ready(pi);
2080	if (rc)
2081	goto err_unmap;
2082
2083	spin_lock_init(&pi->tx_lock);
2084	rc = uart_add_one_port(&mpsc_reg, &pi->port);
2085	if (rc)
2086	goto err_relport;
2087
2088	return 0;
2089	err_relport:
2090	mpsc_release_port(&pi->port);
2091	err_unmap:
2092	mpsc_drv_unmap_regs(pi);
2093	return rc;
2094	}
2095
2096	static struct platform_driver mpsc_driver = {
2097	.probe = mpsc_drv_probe,
2098	.driver = {
2099	.name = MPSC_CTLR_NAME,
2100	.suppress_bind_attrs = true,
2101	},
2102	};
2103
2104	static int __init mpsc_drv_init(void)
2105	{
2106	int rc;
2107
2108	printk(KERN_INFO "Serial: MPSC driver\n");
2109
2110	memset(mpsc_ports, 0, sizeof(mpsc_ports));
2111	memset(&mpsc_shared_regs, 0, sizeof(mpsc_shared_regs));
2112
2113	rc = uart_register_driver(&mpsc_reg);
2114	if (rc)
2115	return rc;
2116
2117	rc = platform_driver_register(&mpsc_shared_driver);
2118	if (rc)
2119	goto err_unreg_uart;
2120
2121	rc = platform_driver_register(&mpsc_driver);
2122	if (rc)
2123	goto err_unreg_plat;
2124
2125	return 0;
2126	err_unreg_plat:
2127	platform_driver_unregister(&mpsc_shared_driver);
2128	err_unreg_uart:
2129	uart_unregister_driver(&mpsc_reg);
2130	return rc;
2131	}
2132	device_initcall(mpsc_drv_init);
2133
2134	/*
2135	MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>");
2136	MODULE_DESCRIPTION("Generic Marvell MPSC serial/UART driver");
2137	MODULE_LICENSE("GPL");
2138	*/

drivers/tty/serial/msm_serial.c+4−0

 static inline void msm_wait_for_xmitr(struct uart_port *port)
 {
+	unsigned int timeout = 500000;
 	while (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY)) {
 		if (msm_read(port, UART_ISR) & UART_ISR_TX_READY)
 			break;
 		udelay(1);
+		if (!timeout--)
+			break;
 	}
 	msm_write(port, UART_CR_CMD_RESET_TX_READY, UART_CR);
 }

drivers/tty/serial/serial_core.c+6−1

 {
 	struct uart_state *state = container_of(port, struct uart_state, port);
 	struct uart_port *uport;
+	int ret;
 	uport = uart_port_check(state);
 	if (!uport || uport->flags & UPF_DEAD)
 	/*
 	 * Start up the serial port.
 	 */
-	return uart_startup(tty, state, 0);
+	ret = uart_startup(tty, state, 0);
+	if (ret > 0)
+		tty_port_set_active(port, 1);
+	return ret;
 }
 static const char *uart_type(struct uart_port *port)

drivers/tty/serial/serial_mctrl_gpio.c+14−0

@@ -12,6 +12,7 @@ · 11 unmodified lines
12	#include <linux/termios.h>	12	#include <linux/termios.h>
13	#include <linux/serial_core.h>	13	#include <linux/serial_core.h>
14	#include <linux/module.h>	14	#include <linux/module.h>
		15	#include <linux/property.h>
15		16
16	#include "serial_mctrl_gpio.h"	17	#include "serial_mctrl_gpio.h"
17		18
@@ -116,6 +117,19 @@ struct mctrl_gpios mctrl_gpio_init_noauto(struct device dev, unsigned int idx) · 98 unmodified lines
116		117
117	for (i = 0; i < UART_GPIO_MAX; i++) {	118	for (i = 0; i < UART_GPIO_MAX; i++) {
118	enum gpiod_flags flags;	119	enum gpiod_flags flags;
		120	char *gpio_str;
		121	bool present;
		122
		123	/* Check if GPIO property exists and continue if not */
		124	gpio_str = kasprintf(GFP_KERNEL, "%s-gpios",
		125	mctrl_gpios_desc[i].name);
		126	if (!gpio_str)
		127	continue;
		128
		129	present = device_property_present(dev, gpio_str);
		130	kfree(gpio_str);
		131	if (!present)
		132	continue;
119		133
120	if (mctrl_gpios_desc[i].dir_out)	134	if (mctrl_gpios_desc[i].dir_out)
121	flags = GPIOD_OUT_LOW;	135	flags = GPIOD_OUT_LOW;

drivers/tty/serial/sh-sci.c+24−9

 	struct circ_buf *xmit = &port->state->xmit;
 	unsigned long flags;
 	dma_addr_t buf;
+	int head, tail;
 	/*
 	 * DMA is idle now.
 	 * consistent xmit buffer state.
 	 */
 	spin_lock_irq(&port->lock);
-	buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
+	head = xmit->head;
+	tail = xmit->tail;
+	buf = s->tx_dma_addr + (tail & (UART_XMIT_SIZE - 1));
 	s->tx_dma_len = min_t(unsigned int,
-		CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
+		CIRC_CNT(head, tail, UART_XMIT_SIZE),
-		CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
+		CIRC_CNT_TO_END(head, tail, UART_XMIT_SIZE));
-	spin_unlock_irq(&port->lock);
+	if (!s->tx_dma_len) {
+		/* Transmit buffer has been flushed */
+		spin_unlock_irq(&port->lock);
+		return;
+	}
 	desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
 					   DMA_MEM_TO_DEV,
 					   DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 	if (!desc) {
+		spin_unlock_irq(&port->lock);
 		dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
 		goto switch_to_pio;
 	}
 	dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
 				   DMA_TO_DEVICE);
-	spin_lock_irq(&port->lock);
 	desc->callback = sci_dma_tx_complete;
 	desc->callback_param = s;
-	spin_unlock_irq(&port->lock);
 	s->cookie_tx = dmaengine_submit(desc);
 	if (dma_submit_error(s->cookie_tx)) {
+		spin_unlock_irq(&port->lock);
 		dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
 		goto switch_to_pio;
 	}
+	spin_unlock_irq(&port->lock);
 	dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
-		__func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
+		__func__, xmit->buf, tail, head, s->cookie_tx);
 	dma_async_issue_pending(chan);
 	return;
 static void sci_flush_buffer(struct uart_port *port)
 {
+	struct sci_port *s = to_sci_port(port);
 	/*
 	 * In uart_flush_buffer(), the xmit circular buffer has just been
-	 * cleared, so we have to reset tx_dma_len accordingly.
+	 * cleared, so we have to reset tx_dma_len accordingly, and stop any
+	 * pending transfers
 	 */
-	to_sci_port(port)->tx_dma_len = 0;
+	s->tx_dma_len = 0;
+	if (s->chan_tx) {
+		dmaengine_terminate_async(s->chan_tx);
+		s->cookie_tx = -EINVAL;
+	}
 }
 #else /* !CONFIG_SERIAL_SH_SCI_DMA */
 static inline void sci_request_dma(struct uart_port *port)

drivers/tty/serial/stm32-usart.c+249−99

@@ -105,9 +105,7 @@ static int stm32_config_rs485(struct uart_port *port, · 104 unmodified lines
105	struct stm32_usart_config *cfg = &stm32_port->info->cfg;	105	struct stm32_usart_config *cfg = &stm32_port->info->cfg;
106	u32 usartdiv, baud, cr1, cr3;	106	u32 usartdiv, baud, cr1, cr3;
107	bool over8;	107	bool over8;
108	unsigned long flags;
109		108
110	spin_lock_irqsave(&port->lock, flags);
111	stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));	109	stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
112		110
113	port->rs485 = *rs485conf;	111	port->rs485 = *rs485conf;
@@ -147,7 +145,6 @@ static int stm32_config_rs485(struct uart_port *port, · 33 unmodified lines
147	}	145	}
148		146
149	stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));	147	stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
150	spin_unlock_irqrestore(&port->lock, flags);
151		148
152	return 0;	149	return 0;
153	}	150	}
@@ -194,8 +191,8 @@ static int stm32_pending_rx(struct uart_port port, u32 sr, int *last_res, · 40 unmodified lines
194	return 0;	191	return 0;
195	}	192	}
196		193
197	static unsigned long	194	static unsigned long stm32_get_char(struct uart_port port, u32 sr,
198	stm32_get_char(struct uart_port port, u32 sr, int *last_res)	195	int *last_res)
199	{	196	{
200	struct stm32_port *stm32_port = to_stm32_port(port);	197	struct stm32_port *stm32_port = to_stm32_port(port);
201	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;	198	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
@@ -205,10 +202,13 @@ stm32_get_char(struct uart_port port, u32 sr, int *last_res) · 3 unmodified lines
205	c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--];	202	c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--];
206	if ((*last_res) == 0)	203	if ((*last_res) == 0)
207	*last_res = RX_BUF_L;	204	*last_res = RX_BUF_L;
208	return c;
209	} else {	205	} else {
210	return readl_relaxed(port->membase + ofs->rdr);	206	c = readl_relaxed(port->membase + ofs->rdr);
		207	/* apply RDR data mask */
		208	c &= stm32_port->rdr_mask;
211	}	209	}
		210
		211	return c;
212	}	212	}
213		213
214	static void stm32_receive_chars(struct uart_port *port, bool threaded)	214	static void stm32_receive_chars(struct uart_port *port, bool threaded)
@@ -225,35 +225,51 @@ static void stm32_receive_chars(struct uart_port *port, bool threaded) · 10 unmodified lines
225		225
226	while (stm32_pending_rx(port, &sr, &stm32_port->last_res, threaded)) {	226	while (stm32_pending_rx(port, &sr, &stm32_port->last_res, threaded)) {
227	sr \|= USART_SR_DUMMY_RX;	227	sr \|= USART_SR_DUMMY_RX;
228	c = stm32_get_char(port, &sr, &stm32_port->last_res);
229	flag = TTY_NORMAL;	228	flag = TTY_NORMAL;
230	port->icount.rx++;
231		229
		230	/*
		231	* Status bits has to be cleared before reading the RDR:
		232	* In FIFO mode, reading the RDR will pop the next data
		233	* (if any) along with its status bits into the SR.
		234	* Not doing so leads to misalignement between RDR and SR,
		235	* and clear status bits of the next rx data.
		236	*
		237	* Clear errors flags for stm32f7 and stm32h7 compatible
		238	* devices. On stm32f4 compatible devices, the error bit is
		239	* cleared by the sequence [read SR - read DR].
		240	*/
		241	if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG)
		242	stm32_clr_bits(port, ofs->icr, USART_ICR_ORECF \|
		243	USART_ICR_PECF \| USART_ICR_FECF);
		244
		245	c = stm32_get_char(port, &sr, &stm32_port->last_res);
		246	port->icount.rx++;
232	if (sr & USART_SR_ERR_MASK) {	247	if (sr & USART_SR_ERR_MASK) {
233	if (sr & USART_SR_LBD) {	248	if (sr & USART_SR_ORE) {
234	port->icount.brk++;
235	if (uart_handle_break(port))
236	continue;
237	} else if (sr & USART_SR_ORE) {
238	if (ofs->icr != UNDEF_REG)
239	writel_relaxed(USART_ICR_ORECF,
240	port->membase +
241	ofs->icr);
242	port->icount.overrun++;	249	port->icount.overrun++;
243	} else if (sr & USART_SR_PE) {	250	} else if (sr & USART_SR_PE) {
244	port->icount.parity++;	251	port->icount.parity++;
245	} else if (sr & USART_SR_FE) {	252	} else if (sr & USART_SR_FE) {
246	port->icount.frame++;	253	/* Break detection if character is null */
		254	if (!c) {
		255	port->icount.brk++;
		256	if (uart_handle_break(port))
		257	continue;
		258	} else {
		259	port->icount.frame++;
		260	}
247	}	261	}
248		262
249	sr &= port->read_status_mask;	263	sr &= port->read_status_mask;
250		264
251	if (sr & USART_SR_LBD)	265	if (sr & USART_SR_PE) {
252	flag = TTY_BREAK;
253	else if (sr & USART_SR_PE)
254	flag = TTY_PARITY;	266	flag = TTY_PARITY;
255	else if (sr & USART_SR_FE)	267	} else if (sr & USART_SR_FE) {
256	flag = TTY_FRAME;	268	if (!c)
		269	flag = TTY_BREAK;
		270	else
		271	flag = TTY_FRAME;
		272	}
257	}	273	}
258		274
259	if (uart_handle_sysrq_char(port, c))	275	if (uart_handle_sysrq_char(port, c))
@@ -271,21 +287,6 @@ static void stm32_tx_dma_complete(void *arg) · 11 unmodified lines
271	struct uart_port *port = arg;	287	struct uart_port *port = arg;
272	struct stm32_port *stm32port = to_stm32_port(port);	288	struct stm32_port *stm32port = to_stm32_port(port);
273	struct stm32_usart_offsets *ofs = &stm32port->info->ofs;	289	struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
274	unsigned int isr;
275	int ret;
276
277	ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
278	isr,
279	(isr & USART_SR_TC),
280	10, 100000);
281
282	if (ret)
283	dev_err(port->dev, "terminal count not set\n");
284
285	if (ofs->icr == UNDEF_REG)
286	stm32_clr_bits(port, ofs->isr, USART_SR_TC);
287	else
288	stm32_set_bits(port, ofs->icr, USART_CR_TC);
289		290
290	stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);	291	stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
291	stm32port->tx_dma_busy = false;	292	stm32port->tx_dma_busy = false;
@@ -294,32 +295,57 @@ static void stm32_tx_dma_complete(void *arg) · 2 unmodified lines
294	stm32_transmit_chars(port);	295	stm32_transmit_chars(port);
295	}	296	}
296		297
		298	static void stm32_tx_interrupt_enable(struct uart_port *port)
		299	{
		300	struct stm32_port *stm32_port = to_stm32_port(port);
		301	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
		302
		303	/*
		304	* Enables TX FIFO threashold irq when FIFO is enabled,
		305	* or TX empty irq when FIFO is disabled
		306	*/
		307	if (stm32_port->fifoen)
		308	stm32_set_bits(port, ofs->cr3, USART_CR3_TXFTIE);
		309	else
		310	stm32_set_bits(port, ofs->cr1, USART_CR1_TXEIE);
		311	}
		312
		313	static void stm32_tx_interrupt_disable(struct uart_port *port)
		314	{
		315	struct stm32_port *stm32_port = to_stm32_port(port);
		316	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
		317
		318	if (stm32_port->fifoen)
		319	stm32_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE);
		320	else
		321	stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
		322	}
		323
297	static void stm32_transmit_chars_pio(struct uart_port *port)	324	static void stm32_transmit_chars_pio(struct uart_port *port)
298	{	325	{
299	struct stm32_port *stm32_port = to_stm32_port(port);	326	struct stm32_port *stm32_port = to_stm32_port(port);
300	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;	327	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
301	struct circ_buf *xmit = &port->state->xmit;	328	struct circ_buf *xmit = &port->state->xmit;
302	unsigned int isr;
303	int ret;
304		329
305	if (stm32_port->tx_dma_busy) {	330	if (stm32_port->tx_dma_busy) {
306	stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);	331	stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
307	stm32_port->tx_dma_busy = false;	332	stm32_port->tx_dma_busy = false;
308	}	333	}
309		334
310	ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,	335	while (!uart_circ_empty(xmit)) {
311	isr,	336	/* Check that TDR is empty before filling FIFO */
312	(isr & USART_SR_TXE),	337	if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
313	10, 100000);	338	break;
314		339	writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr);
315	if (ret)	340	xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
316	dev_err(port->dev, "tx empty not set\n");	341	port->icount.tx++;
317		342	}
318	stm32_set_bits(port, ofs->cr1, USART_CR1_TXEIE);
319		343
320	writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr);	344	/* rely on TXE irq (mask or unmask) for sending remaining data */
321	xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);	345	if (uart_circ_empty(xmit))
322	port->icount.tx++;	346	stm32_tx_interrupt_disable(port);
		347	else
		348	stm32_tx_interrupt_enable(port);
323	}	349	}
324		350
325	static void stm32_transmit_chars_dma(struct uart_port *port)	351	static void stm32_transmit_chars_dma(struct uart_port *port)
@@ -377,7 +403,6 @@ static void stm32_transmit_chars_dma(struct uart_port *port) · 51 unmodified lines
377	/* Issue pending DMA TX requests */	403	/* Issue pending DMA TX requests */
378	dma_async_issue_pending(stm32port->tx_ch);	404	dma_async_issue_pending(stm32port->tx_ch);
379		405
380	stm32_clr_bits(port, ofs->isr, USART_SR_TC);
381	stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT);	406	stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT);
382		407
383	xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);	408	xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
@@ -401,15 +426,15 @@ static void stm32_transmit_chars(struct uart_port *port) · 17 unmodified lines
401	return;	426	return;
402	}	427	}
403		428
404	if (uart_tx_stopped(port)) {	429	if (uart_circ_empty(xmit) \|\| uart_tx_stopped(port)) {
405	stm32_stop_tx(port);	430	stm32_tx_interrupt_disable(port);
406	return;	431	return;
407	}	432	}
408		433
409	if (uart_circ_empty(xmit)) {	434	if (ofs->icr == UNDEF_REG)
410	stm32_stop_tx(port);	435	stm32_clr_bits(port, ofs->isr, USART_SR_TC);
411	return;	436	else
412	}	437	stm32_set_bits(port, ofs->icr, USART_ICR_TCCF);
413		438
414	if (stm32_port->tx_ch)	439	if (stm32_port->tx_ch)
415	stm32_transmit_chars_dma(port);	440	stm32_transmit_chars_dma(port);
@@ -420,7 +445,7 @@ static void stm32_transmit_chars(struct uart_port *port) · 4 unmodified lines
420	uart_write_wakeup(port);	445	uart_write_wakeup(port);
421		446
422	if (uart_circ_empty(xmit))	447	if (uart_circ_empty(xmit))
423	stm32_stop_tx(port);	448	stm32_tx_interrupt_disable(port);
424	}	449	}
425		450
426	static irqreturn_t stm32_interrupt(int irq, void *ptr)	451	static irqreturn_t stm32_interrupt(int irq, void *ptr)
@@ -434,6 +459,10 @@ static irqreturn_t stm32_interrupt(int irq, void *ptr) · 7 unmodified lines
434		459
435	sr = readl_relaxed(port->membase + ofs->isr);	460	sr = readl_relaxed(port->membase + ofs->isr);
436		461
		462	if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG)
		463	writel_relaxed(USART_ICR_RTOCF,
		464	port->membase + ofs->icr);
		465
437	if ((sr & USART_SR_WUF) && (ofs->icr != UNDEF_REG))	466	if ((sr & USART_SR_WUF) && (ofs->icr != UNDEF_REG))
438	writel_relaxed(USART_ICR_WUCF,	467	writel_relaxed(USART_ICR_WUCF,
439	port->membase + ofs->icr);	468	port->membase + ofs->icr);
@@ -495,10 +524,7 @@ static unsigned int stm32_get_mctrl(struct uart_port *port) · 55 unmodified lines
495	/* Transmit stop */	524	/* Transmit stop */
496	static void stm32_stop_tx(struct uart_port *port)	525	static void stm32_stop_tx(struct uart_port *port)
497	{	526	{
498	struct stm32_port *stm32_port = to_stm32_port(port);	527	stm32_tx_interrupt_disable(port);
499	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
500
501	stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
502	}	528	}
503		529
504	/* There are probably characters waiting to be transmitted. */	530	/* There are probably characters waiting to be transmitted. */
@@ -520,7 +546,10 @@ static void stm32_throttle(struct uart_port *port) · 15 unmodified lines
520	unsigned long flags;	546	unsigned long flags;
521		547
522	spin_lock_irqsave(&port->lock, flags);	548	spin_lock_irqsave(&port->lock, flags);
523	stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE);	549	stm32_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
		550	if (stm32_port->cr3_irq)
		551	stm32_clr_bits(port, ofs->cr3, stm32_port->cr3_irq);
		552
524	spin_unlock_irqrestore(&port->lock, flags);	553	spin_unlock_irqrestore(&port->lock, flags);
525	}	554	}
526		555
@@ -532,7 +561,10 @@ static void stm32_unthrottle(struct uart_port *port) · 5 unmodified lines
532	unsigned long flags;	561	unsigned long flags;
533		562
534	spin_lock_irqsave(&port->lock, flags);	563	spin_lock_irqsave(&port->lock, flags);
535	stm32_set_bits(port, ofs->cr1, USART_CR1_RXNEIE);	564	stm32_set_bits(port, ofs->cr1, stm32_port->cr1_irq);
		565	if (stm32_port->cr3_irq)
		566	stm32_set_bits(port, ofs->cr3, stm32_port->cr3_irq);
		567
536	spin_unlock_irqrestore(&port->lock, flags);	568	spin_unlock_irqrestore(&port->lock, flags);
537	}	569	}
538		570
@@ -542,7 +574,10 @@ static void stm32_stop_rx(struct uart_port *port) · 3 unmodified lines
542	struct stm32_port *stm32_port = to_stm32_port(port);	574	struct stm32_port *stm32_port = to_stm32_port(port);
543	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;	575	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
544		576
545	stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE);	577	stm32_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
		578	if (stm32_port->cr3_irq)
		579	stm32_clr_bits(port, ofs->cr3, stm32_port->cr3_irq);
		580
546	}	581	}
547		582
548	/* Handle breaks - ignored by us */	583	/* Handle breaks - ignored by us */
@@ -554,7 +589,6 @@ static int stm32_startup(struct uart_port *port) · 5 unmodified lines
554	{	589	{
555	struct stm32_port *stm32_port = to_stm32_port(port);	590	struct stm32_port *stm32_port = to_stm32_port(port);
556	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;	591	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
557	struct stm32_usart_config *cfg = &stm32_port->info->cfg;
558	const char *name = to_platform_device(port->dev)->name;	592	const char *name = to_platform_device(port->dev)->name;
559	u32 val;	593	u32 val;
560	int ret;	594	int ret;
@@ -565,16 +599,21 @@ static int stm32_startup(struct uart_port *port) · 4 unmodified lines
565	if (ret)	599	if (ret)
566	return ret;	600	return ret;
567		601
568	if (cfg->has_wakeup && stm32_port->wakeirq >= 0) {	602	/* RX FIFO Flush */
569	ret = dev_pm_set_dedicated_wake_irq(port->dev,	603	if (ofs->rqr != UNDEF_REG)
570	stm32_port->wakeirq);	604	stm32_set_bits(port, ofs->rqr, USART_RQR_RXFRQ);
571	if (ret) {	605
572	free_irq(port->irq, port);	606	/* Tx and RX FIFO configuration */
573	return ret;	607	if (stm32_port->fifoen) {
574	}	608	val = readl_relaxed(port->membase + ofs->cr3);
		609	val &= ~(USART_CR3_TXFTCFG_MASK \| USART_CR3_RXFTCFG_MASK);
		610	val \|= USART_CR3_TXFTCFG_HALF << USART_CR3_TXFTCFG_SHIFT;
		611	val \|= USART_CR3_RXFTCFG_HALF << USART_CR3_RXFTCFG_SHIFT;
		612	writel_relaxed(val, port->membase + ofs->cr3);
575	}	613	}
576		614
577	val = USART_CR1_RXNEIE \| USART_CR1_TE \| USART_CR1_RE;	615	/* RX FIFO enabling */
		616	val = stm32_port->cr1_irq \| USART_CR1_RE;
578	if (stm32_port->fifoen)	617	if (stm32_port->fifoen)
579	val \|= USART_CR1_FIFOEN;	618	val \|= USART_CR1_FIFOEN;
580	stm32_set_bits(port, ofs->cr1, val);	619	stm32_set_bits(port, ofs->cr1, val);
@@ -587,18 +626,57 @@ static void stm32_shutdown(struct uart_port *port) · 6 unmodified lines
587	struct stm32_port *stm32_port = to_stm32_port(port);	626	struct stm32_port *stm32_port = to_stm32_port(port);
588	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;	627	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
589	struct stm32_usart_config *cfg = &stm32_port->info->cfg;	628	struct stm32_usart_config *cfg = &stm32_port->info->cfg;
590	u32 val;	629	u32 val, isr;
		630	int ret;
591		631
592	val = USART_CR1_TXEIE \| USART_CR1_RXNEIE \| USART_CR1_TE \| USART_CR1_RE;	632	val = USART_CR1_TXEIE \| USART_CR1_TE;
		633	val \|= stm32_port->cr1_irq \| USART_CR1_RE;
593	val \|= BIT(cfg->uart_enable_bit);	634	val \|= BIT(cfg->uart_enable_bit);
594	if (stm32_port->fifoen)	635	if (stm32_port->fifoen)
595	val \|= USART_CR1_FIFOEN;	636	val \|= USART_CR1_FIFOEN;
		637
		638	ret = readl_relaxed_poll_timeout(port->membase + ofs->isr,
		639	isr, (isr & USART_SR_TC),
		640	10, 100000);
		641
		642	if (ret)
		643	dev_err(port->dev, "transmission complete not set\n");
		644
596	stm32_clr_bits(port, ofs->cr1, val);	645	stm32_clr_bits(port, ofs->cr1, val);
597		646
598	dev_pm_clear_wake_irq(port->dev);
599	free_irq(port->irq, port);	647	free_irq(port->irq, port);
600	}	648	}
601		649
		650	static unsigned int stm32_get_databits(struct ktermios *termios)
		651	{
		652	unsigned int bits;
		653
		654	tcflag_t cflag = termios->c_cflag;
		655
		656	switch (cflag & CSIZE) {
		657	/*
		658	* CSIZE settings are not necessarily supported in hardware.
		659	* CSIZE unsupported configurations are handled here to set word length
		660	* to 8 bits word as default configuration and to print debug message.
		661	*/
		662	case CS5:
		663	bits = 5;
		664	break;
		665	case CS6:
		666	bits = 6;
		667	break;
		668	case CS7:
		669	bits = 7;
		670	break;
		671	/* default including CS8 */
		672	default:
		673	bits = 8;
		674	break;
		675	}
		676
		677	return bits;
		678	}
		679
602	static void stm32_set_termios(struct uart_port port, struct ktermios termios,	680	static void stm32_set_termios(struct uart_port port, struct ktermios termios,
603	struct ktermios *old)	681	struct ktermios *old)
604	{	682	{
@@ -606,7 +684,7 @@ static void stm32_set_termios(struct uart_port port, struct ktermios termios, · 1 unmodified line
606	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;	684	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
607	struct stm32_usart_config *cfg = &stm32_port->info->cfg;	685	struct stm32_usart_config *cfg = &stm32_port->info->cfg;
608	struct serial_rs485 *rs485conf = &port->rs485;	686	struct serial_rs485 *rs485conf = &port->rs485;
609	unsigned int baud;	687	unsigned int baud, bits;
610	u32 usartdiv, mantissa, fraction, oversampling;	688	u32 usartdiv, mantissa, fraction, oversampling;
611	tcflag_t cflag = termios->c_cflag;	689	tcflag_t cflag = termios->c_cflag;
612	u32 cr1, cr2, cr3;	690	u32 cr1, cr2, cr3;
@@ -622,26 +700,64 @@ static void stm32_set_termios(struct uart_port port, struct ktermios termios, · 9 unmodified lines
622	/* Stop serial port and reset value */	700	/* Stop serial port and reset value */
623	writel_relaxed(0, port->membase + ofs->cr1);	701	writel_relaxed(0, port->membase + ofs->cr1);
624		702
625	cr1 = USART_CR1_TE \| USART_CR1_RE \| USART_CR1_RXNEIE;	703	/* flush RX & TX FIFO */
		704	if (ofs->rqr != UNDEF_REG)
		705	stm32_set_bits(port, ofs->rqr,
		706	USART_RQR_TXFRQ \| USART_RQR_RXFRQ);
626		707
		708	cr1 = USART_CR1_TE \| USART_CR1_RE;
627	if (stm32_port->fifoen)	709	if (stm32_port->fifoen)
628	cr1 \|= USART_CR1_FIFOEN;	710	cr1 \|= USART_CR1_FIFOEN;
629	cr2 = 0;	711	cr2 = 0;
630	cr3 = 0;	712	cr3 = readl_relaxed(port->membase + ofs->cr3);
		713	cr3 &= USART_CR3_TXFTIE \| USART_CR3_RXFTCFG_MASK \| USART_CR3_RXFTIE
		714	\| USART_CR3_TXFTCFG_MASK;
631		715
632	if (cflag & CSTOPB)	716	if (cflag & CSTOPB)
633	cr2 \|= USART_CR2_STOP_2B;	717	cr2 \|= USART_CR2_STOP_2B;
634		718
		719	bits = stm32_get_databits(termios);
		720	stm32_port->rdr_mask = (BIT(bits) - 1);
		721
635	if (cflag & PARENB) {	722	if (cflag & PARENB) {
		723	bits++;
636	cr1 \|= USART_CR1_PCE;	724	cr1 \|= USART_CR1_PCE;
637	if ((cflag & CSIZE) == CS8) {
638	if (cfg->has_7bits_data)
639	cr1 \|= USART_CR1_M0;
640	else
641	cr1 \|= USART_CR1_M;
642	}
643	}	725	}
644		726
		727	/*
		728	* Word length configuration:
		729	* CS8 + parity, 9 bits word aka [M1:M0] = 0b01
		730	* CS7 or (CS6 + parity), 7 bits word aka [M1:M0] = 0b10
		731	* CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00
		732	* M0 and M1 already cleared by cr1 initialization.
		733	*/
		734	if (bits == 9)
		735	cr1 \|= USART_CR1_M0;
		736	else if ((bits == 7) && cfg->has_7bits_data)
		737	cr1 \|= USART_CR1_M1;
		738	else if (bits != 8)
		739	dev_dbg(port->dev, "Unsupported data bits config: %u bits\n"
		740	, bits);
		741
		742	if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch \|\|
		743	stm32_port->fifoen)) {
		744	if (cflag & CSTOPB)
		745	bits = bits + 3; /* 1 start bit + 2 stop bits */
		746	else
		747	bits = bits + 2; /* 1 start bit + 1 stop bit */
		748
		749	/* RX timeout irq to occur after last stop bit + bits */
		750	stm32_port->cr1_irq = USART_CR1_RTOIE;
		751	writel_relaxed(bits, port->membase + ofs->rtor);
		752	cr2 \|= USART_CR2_RTOEN;
		753	/* Not using dma, enable fifo threshold irq */
		754	if (!stm32_port->rx_ch)
		755	stm32_port->cr3_irq = USART_CR3_RXFTIE;
		756	}
		757
		758	cr1 \|= stm32_port->cr1_irq;
		759	cr3 \|= stm32_port->cr3_irq;
		760
645	if (cflag & PARODD)	761	if (cflag & PARODD)
646	cr1 \|= USART_CR1_PS;	762	cr1 \|= USART_CR1_PS;
647		763
@@ -679,14 +795,14 @@ static void stm32_set_termios(struct uart_port port, struct ktermios termios, · 31 unmodified lines
679	if (termios->c_iflag & INPCK)	795	if (termios->c_iflag & INPCK)
680	port->read_status_mask \|= USART_SR_PE \| USART_SR_FE;	796	port->read_status_mask \|= USART_SR_PE \| USART_SR_FE;
681	if (termios->c_iflag & (IGNBRK \| BRKINT \| PARMRK))	797	if (termios->c_iflag & (IGNBRK \| BRKINT \| PARMRK))
682	port->read_status_mask \|= USART_SR_LBD;	798	port->read_status_mask \|= USART_SR_FE;
683		799
684	/* Characters to ignore */	800	/* Characters to ignore */
685	port->ignore_status_mask = 0;	801	port->ignore_status_mask = 0;
686	if (termios->c_iflag & IGNPAR)	802	if (termios->c_iflag & IGNPAR)
687	port->ignore_status_mask = USART_SR_PE \| USART_SR_FE;	803	port->ignore_status_mask = USART_SR_PE \| USART_SR_FE;
688	if (termios->c_iflag & IGNBRK) {	804	if (termios->c_iflag & IGNBRK) {
689	port->ignore_status_mask \|= USART_SR_LBD;	805	port->ignore_status_mask \|= USART_SR_FE;
690	/*	806	/*
691	* If we're ignoring parity and break indicators,	807	* If we're ignoring parity and break indicators,
692	* ignore overruns too (for real raw support).	808	* ignore overruns too (for real raw support).
@@ -808,12 +924,32 @@ static int stm32_init_port(struct stm32_port *stm32port, · 115 unmodified lines
808	port->flags = UPF_BOOT_AUTOCONF;	924	port->flags = UPF_BOOT_AUTOCONF;
809	port->ops = &stm32_uart_ops;	925	port->ops = &stm32_uart_ops;
810	port->dev = &pdev->dev;	926	port->dev = &pdev->dev;
811	port->irq = platform_get_irq(pdev, 0);	927	port->fifosize = stm32port->info->cfg.fifosize;
		928
		929	ret = platform_get_irq(pdev, 0);
		930	if (ret <= 0) {
		931	if (ret != -EPROBE_DEFER)
		932	dev_err(&pdev->dev, "Can't get event IRQ: %d\n", ret);
		933	return ret ? ret : -ENODEV;
		934	}
		935	port->irq = ret;
		936
812	port->rs485_config = stm32_config_rs485;	937	port->rs485_config = stm32_config_rs485;
813		938
814	stm32_init_rs485(port, pdev);	939	stm32_init_rs485(port, pdev);
815		940
816	stm32port->wakeirq = platform_get_irq(pdev, 1);	941	if (stm32port->info->cfg.has_wakeup) {
		942	stm32port->wakeirq = platform_get_irq(pdev, 1);
		943	if (stm32port->wakeirq <= 0 && stm32port->wakeirq != -ENXIO) {
		944	if (stm32port->wakeirq != -EPROBE_DEFER)
		945	dev_err(&pdev->dev,
		946	"Can't get event wake IRQ: %d\n",
		947	stm32port->wakeirq);
		948	return stm32port->wakeirq ? stm32port->wakeirq :
		949	-ENODEV;
		950	}
		951	}
		952
817	stm32port->fifoen = stm32port->info->cfg.has_fifo;	953	stm32port->fifoen = stm32port->info->cfg.has_fifo;
818		954
819	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);	955	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -862,6 +998,8 @@ static struct stm32_port stm32_of_get_stm32_port(struct platform_device pdev) · 42 unmodified lines
862	stm32_ports[id].hw_flow_control = of_property_read_bool(np,	998	stm32_ports[id].hw_flow_control = of_property_read_bool(np,
863	"st,hw-flow-ctrl");	999	"st,hw-flow-ctrl");
864	stm32_ports[id].port.line = id;	1000	stm32_ports[id].port.line = id;
		1001	stm32_ports[id].cr1_irq = USART_CR1_RXNEIE;
		1002	stm32_ports[id].cr3_irq = 0;
865	stm32_ports[id].last_res = RX_BUF_L;	1003	stm32_ports[id].last_res = RX_BUF_L;
866	return &stm32_ports[id];	1004	return &stm32_ports[id];
867	}	1005	}
@@ -1020,15 +1158,22 @@ static int stm32_serial_probe(struct platform_device *pdev) · 152 unmodified lines
1020	if (ret)	1158	if (ret)
1021	return ret;	1159	return ret;
1022		1160
1023	if (stm32port->info->cfg.has_wakeup && stm32port->wakeirq >= 0) {	1161	if (stm32port->wakeirq > 0) {
1024	ret = device_init_wakeup(&pdev->dev, true);	1162	ret = device_init_wakeup(&pdev->dev, true);
1025	if (ret)	1163	if (ret)
1026	goto err_uninit;	1164	goto err_uninit;
		1165
		1166	ret = dev_pm_set_dedicated_wake_irq(&pdev->dev,
		1167	stm32port->wakeirq);
		1168	if (ret)
		1169	goto err_nowup;
		1170
		1171	device_set_wakeup_enable(&pdev->dev, false);
1027	}	1172	}
1028		1173
1029	ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port);	1174	ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port);
1030	if (ret)	1175	if (ret)
1031	goto err_nowup;	1176	goto err_wirq;
1032		1177
1033	ret = stm32_of_dma_rx_probe(stm32port, pdev);	1178	ret = stm32_of_dma_rx_probe(stm32port, pdev);
1034	if (ret)	1179	if (ret)
@@ -1042,8 +1187,12 @@ static int stm32_serial_probe(struct platform_device *pdev) · 7 unmodified lines
1042		1187
1043	return 0;	1188	return 0;
1044		1189
		1190	err_wirq:
		1191	if (stm32port->wakeirq > 0)
		1192	dev_pm_clear_wake_irq(&pdev->dev);
		1193
1045	err_nowup:	1194	err_nowup:
1046	if (stm32port->info->cfg.has_wakeup && stm32port->wakeirq >= 0)	1195	if (stm32port->wakeirq > 0)
1047	device_init_wakeup(&pdev->dev, false);	1196	device_init_wakeup(&pdev->dev, false);
1048		1197
1049	err_uninit:	1198	err_uninit:
@@ -1057,7 +1206,6 @@ static int stm32_serial_remove(struct platform_device *pdev) · 7 unmodified lines
1057	struct uart_port *port = platform_get_drvdata(pdev);	1206	struct uart_port *port = platform_get_drvdata(pdev);
1058	struct stm32_port *stm32_port = to_stm32_port(port);	1207	struct stm32_port *stm32_port = to_stm32_port(port);
1059	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;	1208	struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1060	struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1061		1209
1062	stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAR);	1210	stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
1063		1211
@@ -1079,8 +1227,10 @@ static int stm32_serial_remove(struct platform_device *pdev) · 15 unmodified lines
1079	TX_BUF_L, stm32_port->tx_buf,	1227	TX_BUF_L, stm32_port->tx_buf,
1080	stm32_port->tx_dma_buf);	1228	stm32_port->tx_dma_buf);
1081		1229
1082	if (cfg->has_wakeup && stm32_port->wakeirq >= 0)	1230	if (stm32_port->wakeirq > 0) {
		1231	dev_pm_clear_wake_irq(&pdev->dev);
1083	device_init_wakeup(&pdev->dev, false);	1232	device_init_wakeup(&pdev->dev, false);
		1233	}
1084		1234
1085	clk_disable_unprepare(stm32_port->clk);	1235	clk_disable_unprepare(stm32_port->clk);
1086		1236
@@ -1195,7 +1345,7 @@ static void stm32_serial_enable_wakeup(struct uart_port *port, bool enable) · 108 unmodified lines
1195	struct stm32_usart_config *cfg = &stm32_port->info->cfg;	1345	struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1196	u32 val;	1346	u32 val;
1197		1347
1198	if (!cfg->has_wakeup \|\| stm32_port->wakeirq < 0)	1348	if (stm32_port->wakeirq <= 0)
1199	return;	1349	return;
1200		1350
1201	if (enable) {	1351	if (enable) {

drivers/tty/serial/stm32-usart.h+23−10

 	bool has_7bits_data;
 	bool has_wakeup;
 	bool has_fifo;
+	int fifosize;
 };
 struct stm32_usart_info {
 	.cfg = {
 		.uart_enable_bit = 13,
 		.has_7bits_data = false,
+		.fifosize = 1,
 	}
 };
 	.cfg = {
 		.uart_enable_bit = 0,
 		.has_7bits_data = true,
+		.fifosize = 1,
 	}
 };
 		.has_7bits_data = true,
 		.has_wakeup = true,
 		.has_fifo = true,
+		.fifosize = 16,
 	}
 };
 #define USART_SR_RXNE		BIT(5)
 #define USART_SR_TC		BIT(6)
 #define USART_SR_TXE		BIT(7)
-#define USART_SR_LBD		BIT(8)
 #define USART_SR_CTSIF		BIT(9)
 #define USART_SR_CTS		BIT(10)		/* F7 */
 #define USART_SR_RTOF		BIT(11)		/* F7 */
 #define USART_SR_SBKF		BIT(18)		/* F7 */
 #define USART_SR_WUF		BIT(20)		/* H7 */
 #define USART_SR_TEACK		BIT(21)		/* F7 */
-#define USART_SR_ERR_MASK	(USART_SR_LBD | USART_SR_ORE | \
+#define USART_SR_ERR_MASK	(USART_SR_ORE | USART_SR_FE | USART_SR_PE)
-				 USART_SR_FE | USART_SR_PE)
 /* Dummy bits */
 #define USART_SR_DUMMY_RX	BIT(16)
 #define USART_CR1_PS		BIT(9)
 #define USART_CR1_PCE		BIT(10)
 #define USART_CR1_WAKE		BIT(11)
-#define USART_CR1_M		BIT(12)
+#define USART_CR1_M0		BIT(12)		/* F7 (CR1_M for F4) */
-#define USART_CR1_M0		BIT(12)		/* F7 */
 #define USART_CR1_MME		BIT(13)		/* F7 */
 #define USART_CR1_CMIE		BIT(14)		/* F7 */
 #define USART_CR1_OVER8		BIT(15)
 /* USART_CR2 */
 #define USART_CR2_ADD_MASK	GENMASK(3, 0)	/* F4 */
 #define USART_CR2_ADDM7		BIT(4)		/* F7 */
-#define USART_CR2_LBDL		BIT(5)
-#define USART_CR2_LBDIE		BIT(6)
 #define USART_CR2_LBCL		BIT(8)
 #define USART_CR2_CPHA		BIT(9)
 #define USART_CR2_CPOL		BIT(10)
 #define USART_CR3_WUS_MASK	GENMASK(21, 20)	/* H7 */
 #define USART_CR3_WUS_START_BIT	BIT(21)		/* H7 */
 #define USART_CR3_WUFIE		BIT(22)		/* H7 */
+#define USART_CR3_TXFTIE	BIT(23)		/* H7 */
+#define USART_CR3_TCBGTIE	BIT(24)		/* H7 */
+#define USART_CR3_RXFTCFG_MASK	GENMASK(27, 25)	/* H7 */
+#define USART_CR3_RXFTCFG_SHIFT	25		/* H7 */
+#define USART_CR3_RXFTIE	BIT(28)		/* H7 */
+#define USART_CR3_TXFTCFG_MASK	GENMASK(31, 29)	/* H7 */
+#define USART_CR3_TXFTCFG_SHIFT	29		/* H7 */
+/* TX FIFO threashold set to half of its depth */
+#define USART_CR3_TXFTCFG_HALF	0x2
+/* RX FIFO threashold set to half of its depth */
+#define USART_CR3_RXFTCFG_HALF	0x2
 /* USART_GTPR */
 #define USART_GTPR_PSC_MASK	GENMASK(7, 0)
 /* USART_ICR */
 #define USART_ICR_PECF		BIT(0)		/* F7 */
-#define USART_ICR_FFECF		BIT(1)		/* F7 */
+#define USART_ICR_FECF		BIT(1)		/* F7 */
-#define USART_ICR_NCF		BIT(2)		/* F7 */
 #define USART_ICR_ORECF		BIT(3)		/* F7 */
 #define USART_ICR_IDLECF	BIT(4)		/* F7 */
 #define USART_ICR_TCCF		BIT(6)		/* F7 */
-#define USART_ICR_LBDCF		BIT(8)		/* F7 */
 #define USART_ICR_CTSCF		BIT(9)		/* F7 */
 #define USART_ICR_RTOCF		BIT(11)		/* F7 */
 #define USART_ICR_EOBCF		BIT(12)		/* F7 */
 	struct dma_chan *tx_ch;  /* dma tx channel            */
 	dma_addr_t tx_dma_buf;   /* dma tx buffer bus address */
 	unsigned char *tx_buf;   /* dma tx buffer cpu address */
+	u32 cr1_irq;		 /* USART_CR1_RXNEIE or RTOIE */
+	u32 cr3_irq;		 /* USART_CR3_RXFTIE */
 	int last_res;
 	bool tx_dma_busy;	 /* dma tx busy               */
 	bool hw_flow_control;
 	bool fifoen;
 	int wakeirq;
+	int rdr_mask;		/* receive data register mask */
 };
 static struct stm32_port stm32_ports[STM32_MAX_PORTS];

drivers/tty/serial/xilinx_uartps.c+21−16

@@ -26,21 +26,23 @@ · 25 unmodified lines
26	#include <linux/of.h>	26	#include <linux/of.h>
27	#include <linux/module.h>	27	#include <linux/module.h>
28	#include <linux/pm_runtime.h>	28	#include <linux/pm_runtime.h>
		29	#include <linux/iopoll.h>
29		30
30	#define CDNS_UART_TTY_NAME "ttyPS"	31	#define CDNS_UART_TTY_NAME "ttyPS"
31	#define CDNS_UART_NAME "xuartps"	32	#define CDNS_UART_NAME "xuartps"
32	#define CDNS_UART_MAJOR 0 /* use dynamic node allocation */
33	#define CDNS_UART_FIFO_SIZE 64 /* FIFO size */	33	#define CDNS_UART_FIFO_SIZE 64 /* FIFO size */
34	#define CDNS_UART_REGISTER_SPACE 0x1000	34	#define CDNS_UART_REGISTER_SPACE 0x1000
		35	#define TX_TIMEOUT 500000
35		36
36	/* Rx Trigger level */	37	/* Rx Trigger level */
37	static int rx_trigger_level = 56;	38	static int rx_trigger_level = 56;
38	module_param(rx_trigger_level, uint, S_IRUGO);	39	static int uartps_major;
		40	module_param(rx_trigger_level, uint, 0444);
39	MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");	41	MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
40		42
41	/* Rx Timeout */	43	/* Rx Timeout */
42	static int rx_timeout = 10;	44	static int rx_timeout = 10;
43	module_param(rx_timeout, uint, S_IRUGO);	45	module_param(rx_timeout, uint, 0444);
44	MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");	46	MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
45		47
46	/* Register offsets for the UART. */	48	/* Register offsets for the UART. */
@@ -199,7 +201,7 @@ struct cdns_platform_data { · 152 unmodified lines
199	u32 quirks;	201	u32 quirks;
200	};	202	};
201	#define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \	203	#define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \
202	clk_rate_change_nb);	204	clk_rate_change_nb)
203		205
204	/**	206	/**
205	* cdns_uart_handle_rx - Handle the received bytes along with Rx errors.	207	* cdns_uart_handle_rx - Handle the received bytes along with Rx errors.
@@ -312,15 +314,16 @@ static void cdns_uart_handle_tx(void *dev_id) · 106 unmodified lines
312	} else {	314	} else {
313	numbytes = port->fifosize;	315	numbytes = port->fifosize;
314	while (numbytes && !uart_circ_empty(&port->state->xmit) &&	316	while (numbytes && !uart_circ_empty(&port->state->xmit) &&
315	!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)) {	317	!(readl(port->membase + CDNS_UART_SR) &
		318	CDNS_UART_SR_TXFULL)) {
316	/*	319	/*
317	* Get the data from the UART circular buffer	320	* Get the data from the UART circular buffer
318	* and write it to the cdns_uart's TX_FIFO	321	* and write it to the cdns_uart's TX_FIFO
319	* register.	322	* register.
320	*/	323	*/
321	writel(	324	writel(
322	port->state->xmit.buf[port->state->xmit.	325	port->state->xmit.buf[port->state->xmit.tail],
323	tail], port->membase + CDNS_UART_FIFO);	326	port->membase + CDNS_UART_FIFO);
324		327
325	port->icount.tx++;	328	port->icount.tx++;
326		329
@@ -684,18 +687,21 @@ static void cdns_uart_set_termios(struct uart_port *port, · 357 unmodified lines
684	unsigned int cval = 0;	687	unsigned int cval = 0;
685	unsigned int baud, minbaud, maxbaud;	688	unsigned int baud, minbaud, maxbaud;
686	unsigned long flags;	689	unsigned long flags;
687	unsigned int ctrl_reg, mode_reg;	690	unsigned int ctrl_reg, mode_reg, val;
688		691	int err;
689	spin_lock_irqsave(&port->lock, flags);
690		692
691	/* Wait for the transmit FIFO to empty before making changes */	693	/* Wait for the transmit FIFO to empty before making changes */
692	if (!(readl(port->membase + CDNS_UART_CR) &	694	if (!(readl(port->membase + CDNS_UART_CR) &
693	CDNS_UART_CR_TX_DIS)) {	695	CDNS_UART_CR_TX_DIS)) {
694	while (!(readl(port->membase + CDNS_UART_SR) &	696	err = readl_poll_timeout(port->membase + CDNS_UART_SR,
695	CDNS_UART_SR_TXEMPTY)) {	697	val, (val & CDNS_UART_SR_TXEMPTY),
696	cpu_relax();	698	1000, TX_TIMEOUT);
		699	if (err) {
		700	dev_err(port->dev, "timed out waiting for tx empty");
		701	return;
697	}	702	}
698	}	703	}
		704	spin_lock_irqsave(&port->lock, flags);
699		705
700	/* Disable the TX and RX to set baud rate */	706	/* Disable the TX and RX to set baud rate */
701	ctrl_reg = readl(port->membase + CDNS_UART_CR);	707	ctrl_reg = readl(port->membase + CDNS_UART_CR);
@@ -1073,8 +1079,6 @@ static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c) · 371 unmodified lines
1073	cpu_relax();	1079	cpu_relax();
1074		1080
1075	spin_unlock_irqrestore(&port->lock, flags);	1081	spin_unlock_irqrestore(&port->lock, flags);
1076
1077	return;
1078	}	1082	}
1079	#endif	1083	#endif
1080		1084
@@ -1517,7 +1521,7 @@ static int cdns_uart_probe(struct platform_device *pdev) · 436 unmodified lines
1517	cdns_uart_uart_driver->owner = THIS_MODULE;	1521	cdns_uart_uart_driver->owner = THIS_MODULE;
1518	cdns_uart_uart_driver->driver_name = driver_name;	1522	cdns_uart_uart_driver->driver_name = driver_name;
1519	cdns_uart_uart_driver->dev_name = CDNS_UART_TTY_NAME;	1523	cdns_uart_uart_driver->dev_name = CDNS_UART_TTY_NAME;
1520	cdns_uart_uart_driver->major = CDNS_UART_MAJOR;	1524	cdns_uart_uart_driver->major = uartps_major;
1521	cdns_uart_uart_driver->minor = cdns_uart_data->id;	1525	cdns_uart_uart_driver->minor = cdns_uart_data->id;
1522	cdns_uart_uart_driver->nr = 1;	1526	cdns_uart_uart_driver->nr = 1;
1523		1527
@@ -1546,6 +1550,7 @@ static int cdns_uart_probe(struct platform_device *pdev) · 22 unmodified lines
1546	goto err_out_id;	1550	goto err_out_id;
1547	}	1551	}
1548		1552
		1553	uartps_major = cdns_uart_uart_driver->tty_driver->major;
1549	cdns_uart_data->cdns_uart_driver = cdns_uart_uart_driver;	1554	cdns_uart_data->cdns_uart_driver = cdns_uart_uart_driver;
1550		1555
1551	/*	1556	/*

drivers/tty/tty_io.c+3−1

 static struct tty_driver *tty_lookup_driver(dev_t device, struct file *filp,
 		int *index)
 {
-	struct tty_driver *driver;
+	struct tty_driver *driver = NULL;
 	switch (device) {
 #ifdef CONFIG_VT
 				break;
 			}
 		}
+		if (driver)
+			tty_driver_kref_put(driver);
 		return ERR_PTR(-ENODEV);
 	}
 	default:

include/linux/mv643xx.h+0−46

@@ -918,52 +918,6 @@ · 917 unmodified lines
918		918
919	extern void mv64340_irq_init(unsigned int base);	919	extern void mv64340_irq_init(unsigned int base);
920		920
921	/* MPSC Platform Device, Driver Data (Shared register regions) */
922	#define MPSC_SHARED_NAME "mpsc_shared"
923
924	#define MPSC_ROUTING_BASE_ORDER 0
925	#define MPSC_SDMA_INTR_BASE_ORDER 1
926
927	#define MPSC_ROUTING_REG_BLOCK_SIZE 0x000c
928	#define MPSC_SDMA_INTR_REG_BLOCK_SIZE 0x0084
929
930	struct mpsc_shared_pdata {
931	u32 mrr_val;
932	u32 rcrr_val;
933	u32 tcrr_val;
934	u32 intr_cause_val;
935	u32 intr_mask_val;
936	};
937
938	/* MPSC Platform Device, Driver Data */
939	#define MPSC_CTLR_NAME "mpsc"
940
941	#define MPSC_BASE_ORDER 0
942	#define MPSC_SDMA_BASE_ORDER 1
943	#define MPSC_BRG_BASE_ORDER 2
944
945	#define MPSC_REG_BLOCK_SIZE 0x0038
946	#define MPSC_SDMA_REG_BLOCK_SIZE 0x0c18
947	#define MPSC_BRG_REG_BLOCK_SIZE 0x0008
948
949	struct mpsc_pdata {
950	u8 mirror_regs;
951	u8 cache_mgmt;
952	u8 max_idle;
953	int default_baud;
954	int default_bits;
955	int default_parity;
956	int default_flow;
957	u32 chr_1_val;
958	u32 chr_2_val;
959	u32 chr_10_val;
960	u32 mpcr_val;
961	u32 bcr_val;
962	u8 brg_can_tune;
963	u8 brg_clk_src;
964	u32 brg_clk_freq;
965	};
966
967	/* Watchdog Platform Device, Driver Data */	921	/* Watchdog Platform Device, Driver Data */
968	#define MV64x60_WDT_NAME "mv64x60_wdt"	922	#define MV64x60_WDT_NAME "mv64x60_wdt"
969		923

include/linux/serial_8250.h+1−0

@@ -110,6 +110,7 @@ struct uart_8250_port { · 109 unmodified lines
110	* if no_console_suspend	110	* if no_console_suspend
111	*/	111	*/
112	unsigned char probe;	112	unsigned char probe;
		113	struct mctrl_gpios *gpios;
113	#define UART_PROBE_RSA (1 << 0)	114	#define UART_PROBE_RSA (1 << 0)
114		115
115	/*	116	/*

include/uapi/linux/serial_core.h+1−1

@@ -129,7 +129,7 @@ · 128 unmodified lines
129	/* Motorola i.MX SoC */	129	/* Motorola i.MX SoC */
130	#define PORT_IMX 62	130	#define PORT_IMX 62
131		131
132	/* Marvell MPSC */	132	/* Marvell MPSC (obsolete unused) */
133	#define PORT_MPSC 63	133	#define PORT_MPSC 63
134		134
135	/* TXX9 type number */	135	/* TXX9 type number */

Merge tag 'tty-5.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty

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