History

Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma

Pull rdma updates from Jason Gunthorpe: "A quiet cycle after the larger 5.8 effort. Substantially cleanup and driver work with a few smaller features this time. - Driver updates for hfi1, rxe, mlx5, hns, qedr, usnic, bnxt_re - Removal of dead or redundant code across the drivers - RAW resource tracker dumps to include a device specific data blob for device objects to aide device debugging - Further advance the IOCTL interface, remove the ability to turn it off. Add QUERY_CONTEXT, QUERY_MR, and QUERY_PD commands - Remove stubs related to devices with no pkey table - A shared CQ scheme to allow multiple ULPs to share the CQ rings of a device to give higher performance - Several more static checker, syzkaller and rare crashers fixed" * tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma: (121 commits) RDMA/mlx5: Fix flow destination setting for RDMA TX flow table RDMA/rxe: Remove pkey table RDMA/umem: Add a schedule point in ib_umem_get() RDMA/hns: Fix the unneeded process when getting a general type of CQE error RDMA/hns: Fix error during modify qp RTS2RTS RDMA/hns: Delete unnecessary memset when allocating VF resource RDMA/hns: Remove redundant parameters in set_rc_wqe() RDMA/hns: Remove support for HIP08_A RDMA/hns: Refactor hns_roce_v2_set_hem() RDMA/hns: Remove redundant hardware opcode definitions RDMA/netlink: Remove CAP_NET_RAW check when dump a raw QP RDMA/include: Replace license text with SPDX tags RDMA/rtrs: remove WQ_MEM_RECLAIM for rtrs_wq RDMA/rtrs-clt: add an additional random 8 seconds before reconnecting RDMA/cma: Execute rdma_cm destruction from a handler properly RDMA/cma: Remove unneeded locking for req paths RDMA/cma: Using the standard locking pattern when delivering the removal event RDMA/cma: Simplify DEVICE_REMOVAL for internal_id RDMA/efa: Add EFA 0xefa1 PCI ID RDMA/efa: User/kernel compatibility handshake mechanism ...

Linus Torvalds committed 6 years ago

Commit d7806bb2 parents d6efb3a 23fcc7d166 files · +6945 −7569Browse files

Showing the changes to include/linux (3 of 166 files). Show all

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3 files
  1. include/linux/mlx5/device.h +5 −4
  2. include/linux/mlx5/driver.h +2 −0
  3. include/linux/mlx5/mlx5_ifc.h +113 −16
include/linux/mlx5/device.h+5−4
@@ -276,7 +276,9 @@ enum { · 275 unmodified lines
276 MLX5_MKEY_MASK_RW = 1ull << 20,276 MLX5_MKEY_MASK_RW = 1ull << 20,
277 MLX5_MKEY_MASK_A = 1ull << 21,277 MLX5_MKEY_MASK_A = 1ull << 21,
278 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,278 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
279 MLX5_MKEY_MASK_FREE = 1ull << 29,279 MLX5_MKEY_MASK_RELAXED_ORDERING_WRITE = 1ull << 25,
280 MLX5_MKEY_MASK_FREE = 1ull << 29,
281 MLX5_MKEY_MASK_RELAXED_ORDERING_READ = 1ull << 47,
280};282};
281 283
282enum {284enum {
@@ -1007,7 +1009,6 @@ enum { · 724 unmodified lines
1007 MLX5_MKEY_REMOTE_INVAL = 1 << 24,1009 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
1008 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,1010 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
1009 MLX5_MKEY_BSF_EN = 1 << 30,1011 MLX5_MKEY_BSF_EN = 1 << 30,
1010 MLX5_MKEY_LEN64 = 1 << 31,
1011};1012};
1012 1013
1013struct mlx5_mkey_seg {1014struct mlx5_mkey_seg {
@@ -1361,11 +1362,11 @@ enum mlx5_qcam_feature_groups { · 347 unmodified lines
1361 MLX5_ADDR_OF(device_event_cap, (mdev)->caps.hca_cur[MLX5_CAP_DEV_EVENT], cap)1362 MLX5_ADDR_OF(device_event_cap, (mdev)->caps.hca_cur[MLX5_CAP_DEV_EVENT], cap)
1362 1363
1363#define MLX5_CAP_DEV_VDPA_EMULATION(mdev, cap)\1364#define MLX5_CAP_DEV_VDPA_EMULATION(mdev, cap)\
1364 MLX5_GET(device_virtio_emulation_cap, \1365 MLX5_GET(virtio_emulation_cap, \
1365 (mdev)->caps.hca_cur[MLX5_CAP_VDPA_EMULATION], cap)1366 (mdev)->caps.hca_cur[MLX5_CAP_VDPA_EMULATION], cap)
1366 1367
1367#define MLX5_CAP64_DEV_VDPA_EMULATION(mdev, cap)\1368#define MLX5_CAP64_DEV_VDPA_EMULATION(mdev, cap)\
1368 MLX5_GET64(device_virtio_emulation_cap, \1369 MLX5_GET64(virtio_emulation_cap, \
1369 (mdev)->caps.hca_cur[MLX5_CAP_VDPA_EMULATION], cap)1370 (mdev)->caps.hca_cur[MLX5_CAP_VDPA_EMULATION], cap)
1370 1371
1371#define MLX5_CAP_IPSEC(mdev, cap)\1372#define MLX5_CAP_IPSEC(mdev, cap)\
include/linux/mlx5/driver.h+2−0
@@ -975,6 +975,7 @@ void mlx5_register_debugfs(void); · 974 unmodified lines
975void mlx5_unregister_debugfs(void);975void mlx5_unregister_debugfs(void);
976 976
977void mlx5_fill_page_array(struct mlx5_frag_buf *buf, __be64 *pas);977void mlx5_fill_page_array(struct mlx5_frag_buf *buf, __be64 *pas);
978void mlx5_fill_page_frag_array_perm(struct mlx5_frag_buf *buf, __be64 *pas, u8 perm);
978void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);979void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
979int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,980int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
980 unsigned int *irqn);981 unsigned int *irqn);
@@ -1057,6 +1058,7 @@ enum { · 76 unmodified lines
1057enum {1058enum {
1058 MLX5_INTERFACE_PROTOCOL_IB = 0,1059 MLX5_INTERFACE_PROTOCOL_IB = 0,
1059 MLX5_INTERFACE_PROTOCOL_ETH = 1,1060 MLX5_INTERFACE_PROTOCOL_ETH = 1,
1061 MLX5_INTERFACE_PROTOCOL_VDPA = 2,
1060};1062};
1061 1063
1062struct mlx5_interface {1064struct mlx5_interface {
include/linux/mlx5/mlx5_ifc.h+113−16
@@ -93,6 +93,7 @@ enum { · 92 unmodified lines
93 93
94enum {94enum {
95 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,95 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
96 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d,
96 MLX5_OBJ_TYPE_MKEY = 0xff01,97 MLX5_OBJ_TYPE_MKEY = 0xff01,
97 MLX5_OBJ_TYPE_QP = 0xff02,98 MLX5_OBJ_TYPE_QP = 0xff02,
98 MLX5_OBJ_TYPE_PSV = 0xff03,99 MLX5_OBJ_TYPE_PSV = 0xff03,
@@ -985,17 +986,40 @@ struct mlx5_ifc_device_event_cap_bits { · 886 unmodified lines
985 u8 user_unaffiliated_events[4][0x40];986 u8 user_unaffiliated_events[4][0x40];
986};987};
987 988
988struct mlx5_ifc_device_virtio_emulation_cap_bits {989struct mlx5_ifc_virtio_emulation_cap_bits {
989 u8 reserved_at_0[0x20];990 u8 desc_tunnel_offload_type[0x1];
991 u8 eth_frame_offload_type[0x1];
992 u8 virtio_version_1_0[0x1];
993 u8 device_features_bits_mask[0xd];
994 u8 event_mode[0x8];
995 u8 virtio_queue_type[0x8];
990 996
991 u8 reserved_at_20[0x13];997 u8 max_tunnel_desc[0x10];
998 u8 reserved_at_30[0x3];
992 u8 log_doorbell_stride[0x5];999 u8 log_doorbell_stride[0x5];
993 u8 reserved_at_38[0x3];1000 u8 reserved_at_38[0x3];
994 u8 log_doorbell_bar_size[0x5];1001 u8 log_doorbell_bar_size[0x5];
995 1002
996 u8 doorbell_bar_offset[0x40];1003 u8 doorbell_bar_offset[0x40];
997 1004
998 u8 reserved_at_80[0x780];1005 u8 max_emulated_devices[0x8];
1006 u8 max_num_virtio_queues[0x18];
1007
1008 u8 reserved_at_a0[0x60];
1009
1010 u8 umem_1_buffer_param_a[0x20];
1011
1012 u8 umem_1_buffer_param_b[0x20];
1013
1014 u8 umem_2_buffer_param_a[0x20];
1015
1016 u8 umem_2_buffer_param_b[0x20];
1017
1018 u8 umem_3_buffer_param_a[0x20];
1019
1020 u8 umem_3_buffer_param_b[0x20];
1021
1022 u8 reserved_at_1c0[0x640];
999};1023};
1000 1024
1001enum {1025enum {
@@ -1220,7 +1244,11 @@ struct mlx5_ifc_cmd_hca_cap_bits { · 218 unmodified lines
1220 1244
1221 u8 max_sgl_for_optimized_performance[0x8];1245 u8 max_sgl_for_optimized_performance[0x8];
1222 u8 log_max_cq_sz[0x8];1246 u8 log_max_cq_sz[0x8];
1223 u8 reserved_at_d0[0xb];1247 u8 relaxed_ordering_write_umr[0x1];
1248 u8 relaxed_ordering_read_umr[0x1];
1249 u8 reserved_at_d2[0x7];
1250 u8 virtio_net_device_emualtion_manager[0x1];
1251 u8 virtio_blk_device_emualtion_manager[0x1];
1224 u8 log_max_cq[0x5];1252 u8 log_max_cq[0x5];
1225 1253
1226 u8 log_max_eq_sz[0x8];1254 u8 log_max_eq_sz[0x8];
@@ -1396,7 +1424,10 @@ struct mlx5_ifc_cmd_hca_cap_bits { · 169 unmodified lines
1396 u8 bf[0x1];1424 u8 bf[0x1];
1397 u8 driver_version[0x1];1425 u8 driver_version[0x1];
1398 u8 pad_tx_eth_packet[0x1];1426 u8 pad_tx_eth_packet[0x1];
1399 u8 reserved_at_263[0x8];1427 u8 reserved_at_263[0x3];
1428 u8 mkey_by_name[0x1];
1429 u8 reserved_at_267[0x4];
1430
1400 u8 log_bf_reg_size[0x5];1431 u8 log_bf_reg_size[0x5];
1401 1432
1402 u8 reserved_at_270[0x8];1433 u8 reserved_at_270[0x8];
@@ -2953,7 +2984,7 @@ union mlx5_ifc_hca_cap_union_bits { · 1550 unmodified lines
2953 struct mlx5_ifc_fpga_cap_bits fpga_cap;2984 struct mlx5_ifc_fpga_cap_bits fpga_cap;
2954 struct mlx5_ifc_tls_cap_bits tls_cap;2985 struct mlx5_ifc_tls_cap_bits tls_cap;
2955 struct mlx5_ifc_device_mem_cap_bits device_mem_cap;2986 struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
2956 struct mlx5_ifc_device_virtio_emulation_cap_bits virtio_emulation_cap;2987 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap;
2957 u8 reserved_at_0[0x8000];2988 u8 reserved_at_0[0x8000];
2958};2989};
2959 2990
@@ -3302,15 +3333,18 @@ struct mlx5_ifc_scheduling_context_bits { · 342 unmodified lines
3302};3333};
3303 3334
3304struct mlx5_ifc_rqtc_bits {3335struct mlx5_ifc_rqtc_bits {
3305 u8 reserved_at_0[0xa0];3336 u8 reserved_at_0[0xa0];
3306 3337
3307 u8 reserved_at_a0[0x10];3338 u8 reserved_at_a0[0x5];
3308 u8 rqt_max_size[0x10];3339 u8 list_q_type[0x3];
3340 u8 reserved_at_a8[0x8];
3341 u8 rqt_max_size[0x10];
3309 3342
3310 u8 reserved_at_c0[0x10];3343 u8 rq_vhca_id_format[0x1];
3311 u8 rqt_actual_size[0x10];3344 u8 reserved_at_c1[0xf];
3345 u8 rqt_actual_size[0x10];
3312 3346
3313 u8 reserved_at_e0[0x6a0];3347 u8 reserved_at_e0[0x6a0];
3314 3348
3315 struct mlx5_ifc_rq_num_bits rq_num[];3349 struct mlx5_ifc_rq_num_bits rq_num[];
3316};3350};
@@ -7092,7 +7126,7 @@ struct mlx5_ifc_destroy_mkey_out_bits { · 3775 unmodified lines
7092 7126
7093struct mlx5_ifc_destroy_mkey_in_bits {7127struct mlx5_ifc_destroy_mkey_in_bits {
7094 u8 opcode[0x10];7128 u8 opcode[0x10];
7095 u8 reserved_at_10[0x10];7129 u8 uid[0x10];
7096 7130
7097 u8 reserved_at_20[0x10];7131 u8 reserved_at_20[0x10];
7098 u8 op_mod[0x10];7132 u8 op_mod[0x10];
@@ -7723,8 +7757,10 @@ struct mlx5_ifc_create_qp_in_bits { · 624 unmodified lines
7723 u8 reserved_at_20[0x10];7757 u8 reserved_at_20[0x10];
7724 u8 op_mod[0x10];7758 u8 op_mod[0x10];
7725 7759
7726 u8 reserved_at_40[0x40];7760 u8 reserved_at_40[0x8];
7761 u8 input_qpn[0x18];
7727 7762
7763 u8 reserved_at_60[0x20];
7728 u8 opt_param_mask[0x20];7764 u8 opt_param_mask[0x20];
7729 7765
7730 u8 ece[0x20];7766 u8 ece[0x20];
@@ -7788,7 +7824,7 @@ struct mlx5_ifc_create_mkey_out_bits { · 57 unmodified lines
7788 7824
7789struct mlx5_ifc_create_mkey_in_bits {7825struct mlx5_ifc_create_mkey_in_bits {
7790 u8 opcode[0x10];7826 u8 opcode[0x10];
7791 u8 reserved_at_10[0x10];7827 u8 uid[0x10];
7792 7828
7793 u8 reserved_at_20[0x10];7829 u8 reserved_at_20[0x10];
7794 u8 op_mod[0x10];7830 u8 op_mod[0x10];
@@ -10346,6 +10382,40 @@ struct mlx5_ifc_create_umem_in_bits { · 2551 unmodified lines
10346 struct mlx5_ifc_umem_bits umem;10382 struct mlx5_ifc_umem_bits umem;
10347};10383};
10348 10384
10385struct mlx5_ifc_create_umem_out_bits {
10386 u8 status[0x8];
10387 u8 reserved_at_8[0x18];
10388
10389 u8 syndrome[0x20];
10390
10391 u8 reserved_at_40[0x8];
10392 u8 umem_id[0x18];
10393
10394 u8 reserved_at_60[0x20];
10395};
10396
10397struct mlx5_ifc_destroy_umem_in_bits {
10398 u8 opcode[0x10];
10399 u8 uid[0x10];
10400
10401 u8 reserved_at_20[0x10];
10402 u8 op_mod[0x10];
10403
10404 u8 reserved_at_40[0x8];
10405 u8 umem_id[0x18];
10406
10407 u8 reserved_at_60[0x20];
10408};
10409
10410struct mlx5_ifc_destroy_umem_out_bits {
10411 u8 status[0x8];
10412 u8 reserved_at_8[0x18];
10413
10414 u8 syndrome[0x20];
10415
10416 u8 reserved_at_40[0x40];
10417};
10418
10349struct mlx5_ifc_create_uctx_in_bits {10419struct mlx5_ifc_create_uctx_in_bits {
10350 u8 opcode[0x10];10420 u8 opcode[0x10];
10351 u8 reserved_at_10[0x10];10421 u8 reserved_at_10[0x10];
@@ -10358,6 +10428,18 @@ struct mlx5_ifc_create_uctx_in_bits { · 6 unmodified lines
10358 struct mlx5_ifc_uctx_bits uctx;10428 struct mlx5_ifc_uctx_bits uctx;
10359};10429};
10360 10430
10431struct mlx5_ifc_create_uctx_out_bits {
10432 u8 status[0x8];
10433 u8 reserved_at_8[0x18];
10434
10435 u8 syndrome[0x20];
10436
10437 u8 reserved_at_40[0x10];
10438 u8 uid[0x10];
10439
10440 u8 reserved_at_60[0x20];
10441};
10442
10361struct mlx5_ifc_destroy_uctx_in_bits {10443struct mlx5_ifc_destroy_uctx_in_bits {
10362 u8 opcode[0x10];10444 u8 opcode[0x10];
10363 u8 reserved_at_10[0x10];10445 u8 reserved_at_10[0x10];
@@ -10371,6 +10453,15 @@ struct mlx5_ifc_destroy_uctx_in_bits { · 7 unmodified lines
10371 u8 reserved_at_60[0x20];10453 u8 reserved_at_60[0x20];
10372};10454};
10373 10455
10456struct mlx5_ifc_destroy_uctx_out_bits {
10457 u8 status[0x8];
10458 u8 reserved_at_8[0x18];
10459
10460 u8 syndrome[0x20];
10461
10462 u8 reserved_at_40[0x40];
10463};
10464
10374struct mlx5_ifc_create_sw_icm_in_bits {10465struct mlx5_ifc_create_sw_icm_in_bits {
10375 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;10466 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
10376 struct mlx5_ifc_sw_icm_bits sw_icm;10467 struct mlx5_ifc_sw_icm_bits sw_icm;
@@ -10687,4 +10778,10 @@ struct mlx5_ifc_tls_progress_params_bits { · 310 unmodified lines
10687 u8 hw_offset_record_number[0x18];10778 u8 hw_offset_record_number[0x18];
10688};10779};
10689 10780
10781enum {
10782 MLX5_MTT_PERM_READ = 1 << 0,
10783 MLX5_MTT_PERM_WRITE = 1 << 1,
10784 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE,
10785};
10786
10690#endif /* MLX5_IFC_H */10787#endif /* MLX5_IFC_H */