* git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb-2.6: USB: unbind all interfaces before rebinding them USB: serial: digi_acceleport: Eliminate a NULL pointer dereference usb: fix ehci_hcd build failure when both generic-OF and xilinx is selected USB: cdc-acm: fix resource reclaim in error path of acm_probe USB: ftdi_sio: fix DTR/RTS line modes USB: s3c-hsotg: Ensure FIFOs are fully flushed after layout USB: s3c-hsotg: SoftDisconnect minimum 3ms USB: s3c-hsotg: Ensure TX FIFO addresses setup when initialising FIFOs USB: s3c_hsotg: define USB_GADGET_DUALSPEED in Kconfig USB: s3c: Enable soft disconnect during initialization USB: xhci: Print NEC firmware version. USB: xhci: Wait for host to start running. USB: xhci: Wait for controller to be ready after reset. USB: isp1362: fix inw warning on Blackfin systems USB: mos7840: fix null-pointer dereference
Unified · Split
| @@ -1201,7 +1201,7 @@ made_compressed_probe: · 1200 unmodified lines | ||
| 1201 | 1201 | if (rcv->urb == NULL) { |
| 1202 | 1202 | dev_dbg(&intf->dev, |
| 1203 | 1203 | "out of memory (read urbs usb_alloc_urb)\n"); |
| 1204 | − goto alloc_fail7; | |
| 1204 | + goto alloc_fail6; | |
| 1205 | 1205 | } |
| 1206 | 1206 | |
| 1207 | 1207 | rcv->urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP; |
| @@ -1225,7 +1225,7 @@ made_compressed_probe: · 17 unmodified lines | ||
| 1225 | 1225 | if (snd->urb == NULL) { |
| 1226 | 1226 | dev_dbg(&intf->dev, |
| 1227 | 1227 | "out of memory (write urbs usb_alloc_urb)"); |
| 1228 | − goto alloc_fail7; | |
| 1228 | + goto alloc_fail8; | |
| 1229 | 1229 | } |
| 1230 | 1230 | |
| 1231 | 1231 | if (usb_endpoint_xfer_int(epwrite)) |
| @@ -1264,6 +1264,7 @@ made_compressed_probe: · 32 unmodified lines | ||
| 1264 | 1264 | i = device_create_file(&intf->dev, |
| 1265 | 1265 | &dev_attr_iCountryCodeRelDate); |
| 1266 | 1266 | if (i < 0) { |
| 1267 | + device_remove_file(&intf->dev, &dev_attr_wCountryCodes); | |
| 1267 | 1268 | kfree(acm->country_codes); |
| 1268 | 1269 | goto skip_countries; |
| 1269 | 1270 | } |
| @@ -1300,6 +1301,7 @@ alloc_fail8: · 30 unmodified lines | ||
| 1300 | 1301 | usb_free_urb(acm->wb[i].urb); |
| 1301 | 1302 | alloc_fail7: |
| 1302 | 1303 | acm_read_buffers_free(acm); |
| 1304 | +alloc_fail6: | |
| 1303 | 1305 | for (i = 0; i < num_rx_buf; i++) |
| 1304 | 1306 | usb_free_urb(acm->ru[i].urb); |
| 1305 | 1307 | usb_free_urb(acm->ctrlurb); |
| @@ -1328,6 +1328,7 @@ int usb_resume(struct device *dev, pm_message_t msg) · 1327 unmodified lines | ||
| 1328 | 1328 | |
| 1329 | 1329 | /* For all other calls, take the device back to full power and |
| 1330 | 1330 | * tell the PM core in case it was autosuspended previously. |
| 1331 | + * Unbind the interfaces that will need rebinding later. | |
| 1331 | 1332 | */ |
| 1332 | 1333 | } else { |
| 1333 | 1334 | status = usb_resume_both(udev, msg); |
| @@ -1336,6 +1337,7 @@ int usb_resume(struct device *dev, pm_message_t msg) · 2 unmodified lines | ||
| 1336 | 1337 | pm_runtime_set_active(dev); |
| 1337 | 1338 | pm_runtime_enable(dev); |
| 1338 | 1339 | udev->last_busy = jiffies; |
| 1340 | + do_unbind_rebind(udev, DO_REBIND); | |
| 1339 | 1341 | } |
| 1340 | 1342 | } |
| 1341 | 1343 | |
| @@ -295,6 +295,7 @@ config USB_GADGET_S3C_HSOTG · 294 unmodified lines | ||
| 295 | 295 | boolean "S3C HS/OtG USB Device controller" |
| 296 | 296 | depends on S3C_DEV_USB_HSOTG |
| 297 | 297 | select USB_GADGET_S3C_HSOTG_PIO |
| 298 | + select USB_GADGET_DUALSPEED | |
| 298 | 299 | help |
| 299 | 300 | The Samsung S3C64XX USB2.0 high-speed gadget controller |
| 300 | 301 | integrated into the S3C64XX series SoC. |
| @@ -297,6 +297,12 @@ static void s3c_hsotg_ctrl_epint(struct s3c_hsotg *hsotg, · 296 unmodified lines | ||
| 297 | 297 | */ |
| 298 | 298 | static void s3c_hsotg_init_fifo(struct s3c_hsotg *hsotg) |
| 299 | 299 | { |
| 300 | + unsigned int ep; | |
| 301 | + unsigned int addr; | |
| 302 | + unsigned int size; | |
| 303 | + int timeout; | |
| 304 | + u32 val; | |
| 305 | + | |
| 300 | 306 | /* the ryu 2.6.24 release ahs |
| 301 | 307 | writel(0x1C0, hsotg->regs + S3C_GRXFSIZ); |
| 302 | 308 | writel(S3C_GNPTXFSIZ_NPTxFStAddr(0x200) | |
| @@ -310,6 +316,51 @@ static void s3c_hsotg_init_fifo(struct s3c_hsotg *hsotg) · 7 unmodified lines | ||
| 310 | 316 | writel(S3C_GNPTXFSIZ_NPTxFStAddr(2048) | |
| 311 | 317 | S3C_GNPTXFSIZ_NPTxFDep(0x1C0), |
| 312 | 318 | hsotg->regs + S3C_GNPTXFSIZ); |
| 319 | + | |
| 320 | + /* arange all the rest of the TX FIFOs, as some versions of this | |
| 321 | + * block have overlapping default addresses. This also ensures | |
| 322 | + * that if the settings have been changed, then they are set to | |
| 323 | + * known values. */ | |
| 324 | + | |
| 325 | + /* start at the end of the GNPTXFSIZ, rounded up */ | |
| 326 | + addr = 2048 + 1024; | |
| 327 | + size = 768; | |
| 328 | + | |
| 329 | + /* currently we allocate TX FIFOs for all possible endpoints, | |
| 330 | + * and assume that they are all the same size. */ | |
| 331 | + | |
| 332 | + for (ep = 0; ep <= 15; ep++) { | |
| 333 | + val = addr; | |
| 334 | + val |= size << S3C_DPTXFSIZn_DPTxFSize_SHIFT; | |
| 335 | + addr += size; | |
| 336 | + | |
| 337 | + writel(val, hsotg->regs + S3C_DPTXFSIZn(ep)); | |
| 338 | + } | |
| 339 | + | |
| 340 | + /* according to p428 of the design guide, we need to ensure that | |
| 341 | + * all fifos are flushed before continuing */ | |
| 342 | + | |
| 343 | + writel(S3C_GRSTCTL_TxFNum(0x10) | S3C_GRSTCTL_TxFFlsh | | |
| 344 | + S3C_GRSTCTL_RxFFlsh, hsotg->regs + S3C_GRSTCTL); | |
| 345 | + | |
| 346 | + /* wait until the fifos are both flushed */ | |
| 347 | + timeout = 100; | |
| 348 | + while (1) { | |
| 349 | + val = readl(hsotg->regs + S3C_GRSTCTL); | |
| 350 | + | |
| 351 | + if ((val & (S3C_GRSTCTL_TxFFlsh | S3C_GRSTCTL_RxFFlsh)) == 0) | |
| 352 | + break; | |
| 353 | + | |
| 354 | + if (--timeout == 0) { | |
| 355 | + dev_err(hsotg->dev, | |
| 356 | + "%s: timeout flushing fifos (GRSTCTL=%08x)\n", | |
| 357 | + __func__, val); | |
| 358 | + } | |
| 359 | + | |
| 360 | + udelay(1); | |
| 361 | + } | |
| 362 | + | |
| 363 | + dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout); | |
| 313 | 364 | } |
| 314 | 365 | |
| 315 | 366 | /** |
| @@ -2574,6 +2625,9 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver) · 2258 unmodified lines | ||
| 2574 | 2625 | writel(S3C_DCTL_CGOUTNak | S3C_DCTL_CGNPInNAK, |
| 2575 | 2626 | hsotg->regs + S3C_DCTL); |
| 2576 | 2627 | |
| 2628 | + /* must be at-least 3ms to allow bus to see disconnect */ | |
| 2629 | + msleep(3); | |
| 2630 | + | |
| 2577 | 2631 | /* remove the soft-disconnect and let's go */ |
| 2578 | 2632 | __bic32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon); |
| 2579 | 2633 | |
| @@ -2730,6 +2784,9 @@ static void s3c_hsotg_init(struct s3c_hsotg *hsotg) · 150 unmodified lines | ||
| 2730 | 2784 | |
| 2731 | 2785 | writel(0, hsotg->regs + S3C_DAINTMSK); |
| 2732 | 2786 | |
| 2787 | + /* Be in disconnected state until gadget is registered */ | |
| 2788 | + __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon); | |
| 2789 | + | |
| 2733 | 2790 | if (0) { |
| 2734 | 2791 | /* post global nak until we're ready */ |
| 2735 | 2792 | writel(S3C_DCTL_SGNPInNAK | S3C_DCTL_SGOUTNak, |
| @@ -1135,7 +1135,7 @@ MODULE_LICENSE ("GPL"); · 1134 unmodified lines | ||
| 1135 | 1135 | |
| 1136 | 1136 | #ifdef CONFIG_XPS_USB_HCD_XILINX |
| 1137 | 1137 | #include "ehci-xilinx-of.c" |
| 1138 | −#define OF_PLATFORM_DRIVER ehci_hcd_xilinx_of_driver | |
| 1138 | +#define XILINX_OF_PLATFORM_DRIVER ehci_hcd_xilinx_of_driver | |
| 1139 | 1139 | #endif |
| 1140 | 1140 | |
| 1141 | 1141 | #ifdef CONFIG_PLAT_ORION |
| @@ -1159,7 +1159,8 @@ MODULE_LICENSE ("GPL"); · 17 unmodified lines | ||
| 1159 | 1159 | #endif |
| 1160 | 1160 | |
| 1161 | 1161 | #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ |
| 1162 | − !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) | |
| 1162 | + !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \ | |
| 1163 | + !defined(XILINX_OF_PLATFORM_DRIVER) | |
| 1163 | 1164 | #error "missing bus glue for ehci-hcd" |
| 1164 | 1165 | #endif |
| 1165 | 1166 | |
| @@ -1213,10 +1214,20 @@ static int __init ehci_hcd_init(void) · 47 unmodified lines | ||
| 1213 | 1214 | if (retval < 0) |
| 1214 | 1215 | goto clean3; |
| 1215 | 1216 | #endif |
| 1217 | + | |
| 1218 | +#ifdef XILINX_OF_PLATFORM_DRIVER | |
| 1219 | + retval = of_register_platform_driver(&XILINX_OF_PLATFORM_DRIVER); | |
| 1220 | + if (retval < 0) | |
| 1221 | + goto clean4; | |
| 1222 | +#endif | |
| 1216 | 1223 | return retval; |
| 1217 | 1224 | |
| 1225 | +#ifdef XILINX_OF_PLATFORM_DRIVER | |
| 1226 | + /* of_unregister_platform_driver(&XILINX_OF_PLATFORM_DRIVER); */ | |
| 1227 | +clean4: | |
| 1228 | +#endif | |
| 1218 | 1229 | #ifdef OF_PLATFORM_DRIVER |
| 1219 | − /* of_unregister_platform_driver(&OF_PLATFORM_DRIVER); */ | |
| 1230 | + of_unregister_platform_driver(&OF_PLATFORM_DRIVER); | |
| 1220 | 1231 | clean3: |
| 1221 | 1232 | #endif |
| 1222 | 1233 | #ifdef PS3_SYSTEM_BUS_DRIVER |
| @@ -1243,6 +1254,9 @@ module_init(ehci_hcd_init); · 20 unmodified lines | ||
| 1243 | 1254 | |
| 1244 | 1255 | static void __exit ehci_hcd_cleanup(void) |
| 1245 | 1256 | { |
| 1257 | +#ifdef XILINX_OF_PLATFORM_DRIVER | |
| 1258 | + of_unregister_platform_driver(&XILINX_OF_PLATFORM_DRIVER); | |
| 1259 | +#endif | |
| 1246 | 1260 | #ifdef OF_PLATFORM_DRIVER |
| 1247 | 1261 | of_unregister_platform_driver(&OF_PLATFORM_DRIVER); |
| 1248 | 1262 | #endif |
| @@ -65,7 +65,7 @@ static inline void delayed_insw(unsigned int addr, void *buf, int len) · 64 unmodified lines | ||
| 65 | 65 | unsigned short *bp = (unsigned short *)buf; |
| 66 | 66 | while (len--) { |
| 67 | 67 | DUMMY_DELAY_ACCESS; |
| 68 | − *bp++ = inw((void *)addr); | |
| 68 | + *bp++ = inw(addr); | |
| 69 | 69 | } |
| 70 | 70 | } |
| 71 | 71 | |
| @@ -78,6 +78,8 @@ static int xhci_pci_setup(struct usb_hcd *hcd) · 77 unmodified lines | ||
| 78 | 78 | xhci_dbg(xhci, "QUIRK: Fresco Logic xHC needs configure" |
| 79 | 79 | " endpoint cmd after reset endpoint\n"); |
| 80 | 80 | } |
| 81 | + if (pdev->vendor == PCI_VENDOR_ID_NEC) | |
| 82 | + xhci->quirks |= XHCI_NEC_HOST; | |
| 81 | 83 | |
| 82 | 84 | /* Make sure the HC is halted. */ |
| 83 | 85 | retval = xhci_halt(xhci); |
| @@ -1071,6 +1071,15 @@ bandwidth_change: · 1070 unmodified lines | ||
| 1071 | 1071 | xhci_warn(xhci, "Reset device command completion " |
| 1072 | 1072 | "for disabled slot %u\n", slot_id); |
| 1073 | 1073 | break; |
| 1074 | + case TRB_TYPE(TRB_NEC_GET_FW): | |
| 1075 | + if (!(xhci->quirks & XHCI_NEC_HOST)) { | |
| 1076 | + xhci->error_bitmask |= 1 << 6; | |
| 1077 | + break; | |
| 1078 | + } | |
| 1079 | + xhci_dbg(xhci, "NEC firmware version %2x.%02x\n", | |
| 1080 | + NEC_FW_MAJOR(event->status), | |
| 1081 | + NEC_FW_MINOR(event->status)); | |
| 1082 | + break; | |
| 1074 | 1083 | default: |
| 1075 | 1084 | /* Skip over unknown commands on the event ring */ |
| 1076 | 1085 | xhci->error_bitmask |= 1 << 6; |
| @@ -1079,6 +1088,17 @@ bandwidth_change: · 2 unmodified lines | ||
| 1079 | 1088 | inc_deq(xhci, xhci->cmd_ring, false); |
| 1080 | 1089 | } |
| 1081 | 1090 | |
| 1091 | +static void handle_vendor_event(struct xhci_hcd *xhci, | |
| 1092 | + union xhci_trb *event) | |
| 1093 | +{ | |
| 1094 | + u32 trb_type; | |
| 1095 | + | |
| 1096 | + trb_type = TRB_FIELD_TO_TYPE(event->generic.field[3]); | |
| 1097 | + xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type); | |
| 1098 | + if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST)) | |
| 1099 | + handle_cmd_completion(xhci, &event->event_cmd); | |
| 1100 | +} | |
| 1101 | + | |
| 1082 | 1102 | static void handle_port_status(struct xhci_hcd *xhci, |
| 1083 | 1103 | union xhci_trb *event) |
| 1084 | 1104 | { |
| @@ -1659,7 +1679,10 @@ void xhci_handle_event(struct xhci_hcd *xhci) · 574 unmodified lines | ||
| 1659 | 1679 | update_ptrs = 0; |
| 1660 | 1680 | break; |
| 1661 | 1681 | default: |
| 1662 | − xhci->error_bitmask |= 1 << 3; | |
| 1682 | + if ((event->event_cmd.flags & TRB_TYPE_BITMASK) >= TRB_TYPE(48)) | |
| 1683 | + handle_vendor_event(xhci, event); | |
| 1684 | + else | |
| 1685 | + xhci->error_bitmask |= 1 << 3; | |
| 1663 | 1686 | } |
| 1664 | 1687 | /* Any of the above functions may drop and re-acquire the lock, so check |
| 1665 | 1688 | * to make sure a watchdog timer didn't mark the host as non-responsive. |
| @@ -2378,6 +2401,12 @@ int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, · 712 unmodified lines | ||
| 2378 | 2401 | false); |
| 2379 | 2402 | } |
| 2380 | 2403 | |
| 2404 | +int xhci_queue_vendor_command(struct xhci_hcd *xhci, | |
| 2405 | + u32 field1, u32 field2, u32 field3, u32 field4) | |
| 2406 | +{ | |
| 2407 | + return queue_command(xhci, field1, field2, field3, field4, false); | |
| 2408 | +} | |
| 2409 | + | |
| 2381 | 2410 | /* Queue a reset device command TRB */ |
| 2382 | 2411 | int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id) |
| 2383 | 2412 | { |
| @@ -105,6 +105,33 @@ int xhci_halt(struct xhci_hcd *xhci) · 104 unmodified lines | ||
| 105 | 105 | STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC); |
| 106 | 106 | } |
| 107 | 107 | |
| 108 | +/* | |
| 109 | + * Set the run bit and wait for the host to be running. | |
| 110 | + */ | |
| 111 | +int xhci_start(struct xhci_hcd *xhci) | |
| 112 | +{ | |
| 113 | + u32 temp; | |
| 114 | + int ret; | |
| 115 | + | |
| 116 | + temp = xhci_readl(xhci, &xhci->op_regs->command); | |
| 117 | + temp |= (CMD_RUN); | |
| 118 | + xhci_dbg(xhci, "// Turn on HC, cmd = 0x%x.\n", | |
| 119 | + temp); | |
| 120 | + xhci_writel(xhci, temp, &xhci->op_regs->command); | |
| 121 | + | |
| 122 | + /* | |
| 123 | + * Wait for the HCHalted Status bit to be 0 to indicate the host is | |
| 124 | + * running. | |
| 125 | + */ | |
| 126 | + ret = handshake(xhci, &xhci->op_regs->status, | |
| 127 | + STS_HALT, 0, XHCI_MAX_HALT_USEC); | |
| 128 | + if (ret == -ETIMEDOUT) | |
| 129 | + xhci_err(xhci, "Host took too long to start, " | |
| 130 | + "waited %u microseconds.\n", | |
| 131 | + XHCI_MAX_HALT_USEC); | |
| 132 | + return ret; | |
| 133 | +} | |
| 134 | + | |
| 108 | 135 | /* |
| 109 | 136 | * Reset a halted HC, and set the internal HC state to HC_STATE_HALT. |
| 110 | 137 | * |
| @@ -116,6 +143,7 @@ int xhci_reset(struct xhci_hcd *xhci) · 5 unmodified lines | ||
| 116 | 143 | { |
| 117 | 144 | u32 command; |
| 118 | 145 | u32 state; |
| 146 | + int ret; | |
| 119 | 147 | |
| 120 | 148 | state = xhci_readl(xhci, &xhci->op_regs->status); |
| 121 | 149 | if ((state & STS_HALT) == 0) { |
| @@ -130,7 +158,17 @@ int xhci_reset(struct xhci_hcd *xhci) · 8 unmodified lines | ||
| 130 | 158 | /* XXX: Why does EHCI set this here? Shouldn't other code do this? */ |
| 131 | 159 | xhci_to_hcd(xhci)->state = HC_STATE_HALT; |
| 132 | 160 | |
| 133 | − return handshake(xhci, &xhci->op_regs->command, CMD_RESET, 0, 250 * 1000); | |
| 161 | + ret = handshake(xhci, &xhci->op_regs->command, | |
| 162 | + CMD_RESET, 0, 250 * 1000); | |
| 163 | + if (ret) | |
| 164 | + return ret; | |
| 165 | + | |
| 166 | + xhci_dbg(xhci, "Wait for controller to be ready for doorbell rings\n"); | |
| 167 | + /* | |
| 168 | + * xHCI cannot write to any doorbells or operational registers other | |
| 169 | + * than status until the "Controller Not Ready" flag is cleared. | |
| 170 | + */ | |
| 171 | + return handshake(xhci, &xhci->op_regs->status, STS_CNR, 0, 250 * 1000); | |
| 134 | 172 | } |
| 135 | 173 | |
| 136 | 174 | |
| @@ -448,17 +486,20 @@ int xhci_run(struct usb_hcd *hcd) · 311 unmodified lines | ||
| 448 | 486 | |
| 449 | 487 | if (NUM_TEST_NOOPS > 0) |
| 450 | 488 | doorbell = xhci_setup_one_noop(xhci); |
| 489 | + if (xhci->quirks & XHCI_NEC_HOST) | |
| 490 | + xhci_queue_vendor_command(xhci, 0, 0, 0, | |
| 491 | + TRB_TYPE(TRB_NEC_GET_FW)); | |
| 492 | + | |
| 493 | + if (xhci_start(xhci)) { | |
| 494 | + xhci_halt(xhci); | |
| 495 | + return -ENODEV; | |
| 496 | + } | |
| 451 | 497 | |
| 452 | − temp = xhci_readl(xhci, &xhci->op_regs->command); | |
| 453 | − temp |= (CMD_RUN); | |
| 454 | − xhci_dbg(xhci, "// Turn on HC, cmd = 0x%x.\n", | |
| 455 | − temp); | |
| 456 | − xhci_writel(xhci, temp, &xhci->op_regs->command); | |
| 457 | − /* Flush PCI posted writes */ | |
| 458 | − temp = xhci_readl(xhci, &xhci->op_regs->command); | |
| 459 | 498 | xhci_dbg(xhci, "// @%p = 0x%x\n", &xhci->op_regs->command, temp); |
| 460 | 499 | if (doorbell) |
| 461 | 500 | (*doorbell)(xhci); |
| 501 | + if (xhci->quirks & XHCI_NEC_HOST) | |
| 502 | + xhci_ring_cmd_db(xhci); | |
| 462 | 503 | |
| 463 | 504 | xhci_dbg(xhci, "Finished xhci_run\n"); |
| 464 | 505 | return 0; |
| @@ -925,6 +925,7 @@ union xhci_trb { · 924 unmodified lines | ||
| 925 | 925 | /* TRB bit mask */ |
| 926 | 926 | #define TRB_TYPE_BITMASK (0xfc00) |
| 927 | 927 | #define TRB_TYPE(p) ((p) << 10) |
| 928 | +#define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10) | |
| 928 | 929 | /* TRB type IDs */ |
| 929 | 930 | /* bulk, interrupt, isoc scatter/gather, and control data stage */ |
| 930 | 931 | #define TRB_NORMAL 1 |
| @@ -992,6 +993,14 @@ union xhci_trb { · 61 unmodified lines | ||
| 992 | 993 | #define TRB_MFINDEX_WRAP 39 |
| 993 | 994 | /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */ |
| 994 | 995 | |
| 996 | +/* Nec vendor-specific command completion event. */ | |
| 997 | +#define TRB_NEC_CMD_COMP 48 | |
| 998 | +/* Get NEC firmware revision. */ | |
| 999 | +#define TRB_NEC_GET_FW 49 | |
| 1000 | + | |
| 1001 | +#define NEC_FW_MINOR(p) (((p) >> 0) & 0xff) | |
| 1002 | +#define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff) | |
| 1003 | + | |
| 995 | 1004 | /* |
| 996 | 1005 | * TRBS_PER_SEGMENT must be a multiple of 4, |
| 997 | 1006 | * since the command ring is 64-byte aligned. |
| @@ -1172,6 +1181,7 @@ struct xhci_hcd { · 174 unmodified lines | ||
| 1172 | 1181 | unsigned int quirks; |
| 1173 | 1182 | #define XHCI_LINK_TRB_QUIRK (1 << 0) |
| 1174 | 1183 | #define XHCI_RESET_EP_QUIRK (1 << 1) |
| 1184 | +#define XHCI_NEC_HOST (1 << 2) | |
| 1175 | 1185 | }; |
| 1176 | 1186 | |
| 1177 | 1187 | /* For testing purposes */ |
| @@ -1379,6 +1389,8 @@ void xhci_set_hc_event_deq(struct xhci_hcd *xhci); · 201 unmodified lines | ||
| 1379 | 1389 | int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id); |
| 1380 | 1390 | int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, |
| 1381 | 1391 | u32 slot_id); |
| 1392 | +int xhci_queue_vendor_command(struct xhci_hcd *xhci, | |
| 1393 | + u32 field1, u32 field2, u32 field3, u32 field4); | |
| 1382 | 1394 | int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id, |
| 1383 | 1395 | unsigned int ep_index); |
| 1384 | 1396 | int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, |
| @@ -1239,8 +1239,7 @@ static void digi_write_bulk_callback(struct urb *urb) · 1238 unmodified lines | ||
| 1239 | 1239 | |
| 1240 | 1240 | /* port and serial sanity check */ |
| 1241 | 1241 | if (port == NULL || (priv = usb_get_serial_port_data(port)) == NULL) { |
| 1242 | − dev_err(&port->dev, | |
| 1243 | − "%s: port or port->private is NULL, status=%d\n", | |
| 1242 | + pr_err("%s: port or port->private is NULL, status=%d\n", | |
| 1244 | 1243 | __func__, status); |
| 1245 | 1244 | return; |
| 1246 | 1245 | } |
| @@ -2005,6 +2005,8 @@ static void ftdi_set_termios(struct tty_struct *tty, · 2004 unmodified lines | ||
| 2005 | 2005 | "urb failed to set to rts/cts flow control\n"); |
| 2006 | 2006 | } |
| 2007 | 2007 | |
| 2008 | + /* raise DTR/RTS */ | |
| 2009 | + set_mctrl(port, TIOCM_DTR | TIOCM_RTS); | |
| 2008 | 2010 | } else { |
| 2009 | 2011 | /* |
| 2010 | 2012 | * Xon/Xoff code |
| @@ -2052,6 +2054,8 @@ static void ftdi_set_termios(struct tty_struct *tty, · 41 unmodified lines | ||
| 2052 | 2054 | } |
| 2053 | 2055 | } |
| 2054 | 2056 | |
| 2057 | + /* lower DTR/RTS */ | |
| 2058 | + clear_mctrl(port, TIOCM_DTR | TIOCM_RTS); | |
| 2055 | 2059 | } |
| 2056 | 2060 | return; |
| 2057 | 2061 | } |
| @@ -730,7 +730,6 @@ static void mos7840_bulk_in_callback(struct urb *urb) · 729 unmodified lines | ||
| 730 | 730 | mos7840_port = urb->context; |
| 731 | 731 | if (!mos7840_port) { |
| 732 | 732 | dbg("%s", "NULL mos7840_port pointer"); |
| 733 | − mos7840_port->read_urb_busy = false; | |
| 734 | 733 | return; |
| 735 | 734 | } |
| 736 | 735 | |