With the recent feature added to enable perf events to use pseudo NMIs as interrupts on platforms which support GICv3 or later, its now been possible to enable hard lockup detector (or NMI watchdog) on arm64 platforms. So enable corresponding support. One thing to note here is that normally lockup detector is initialized just after the early initcalls but PMU on arm64 comes up much later as device_initcall(). To cope with that, override arch_perf_nmi_is_available() to let the watchdog framework know PMU not ready, and inform the framework to re-initialize lockup detection once PMU has been initialized. [dianders@chromium.org: only HAVE_HARDLOCKUP_DETECTOR_PERF if the PMU config is enabled] Link: https://lkml.kernel.org/r/20230523073952.1.I60217a63acc35621e13f10be16c0cd7c363caf8c@changeid Link: https://lkml.kernel.org/r/20230519101840.v5.18.Ia44852044cdcb074f387e80df6b45e892965d4a1@changeid Co-developed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Co-developed-by: Pingfan Liu <kernelfans@gmail.com> Signed-off-by: Pingfan Liu <kernelfans@gmail.com> Signed-off-by: Lecopzer Chen <lecopzer.chen@mediatek.com> Signed-off-by: Douglas Anderson <dianders@chromium.org> Cc: Andi Kleen <ak@linux.intel.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Christophe Leroy <christophe.leroy@csgroup.eu> Cc: Colin Cross <ccross@android.com> Cc: Daniel Thompson <daniel.thompson@linaro.org> Cc: "David S. Miller" <davem@davemloft.net> Cc: Guenter Roeck <groeck@chromium.org> Cc: Ian Rogers <irogers@google.com> Cc: Marc Zyngier <maz@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Masayoshi Mizuma <msys.mizuma@gmail.com> Cc: Matthias Kaehlcke <mka@chromium.org> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Nicholas Piggin <npiggin@gmail.com> Cc: Petr Mladek <pmladek@suse.com> Cc: Randy Dunlap <rdunlap@infradead.org> Cc: "Ravi V. Shankar" <ravi.v.shankar@intel.com> Cc: Ricardo Neri <ricardo.neri@intel.com> Cc: Stephane Eranian <eranian@google.com> Cc: Stephen Boyd <swboyd@chromium.org> Cc: Tzung-Bi Shih <tzungbi@chromium.org> Cc: Will Deacon <will@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Unified · Split
| @@ -203,12 +203,15 @@ config ARM64 · 202 unmodified lines | ||
| 203 | 203 | select HAVE_FUNCTION_ERROR_INJECTION |
| 204 | 204 | select HAVE_FUNCTION_GRAPH_TRACER |
| 205 | 205 | select HAVE_GCC_PLUGINS |
| 206 | + select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && \ | |
| 207 | + HW_PERF_EVENTS && HAVE_PERF_EVENTS_NMI | |
| 206 | 208 | select HAVE_HW_BREAKPOINT if PERF_EVENTS |
| 207 | 209 | select HAVE_IOREMAP_PROT |
| 208 | 210 | select HAVE_IRQ_TIME_ACCOUNTING |
| 209 | 211 | select HAVE_KVM |
| 210 | 212 | select HAVE_NMI |
| 211 | 213 | select HAVE_PERF_EVENTS |
| 214 | + select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI | |
| 212 | 215 | select HAVE_PERF_REGS |
| 213 | 216 | select HAVE_PERF_USER_STACK_DUMP |
| 214 | 217 | select HAVE_PREEMPT_DYNAMIC_KEY |
| @@ -1,5 +1,7 @@ | ||
| 1 | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | +#include <linux/nmi.h> | |
| 2 | 3 | #include <linux/cpufreq.h> |
| 4 | +#include <linux/perf/arm_pmu.h> | |
| 3 | 5 | |
| 4 | 6 | /* |
| 5 | 7 | * Safe maximum CPU frequency in case a particular platform doesn't implement |
| @@ -22,3 +24,13 @@ u64 hw_nmi_get_sample_period(int watchdog_thresh) · 16 unmodified lines | ||
| 22 | 24 | |
| 23 | 25 | return (u64)max_cpu_freq * watchdog_thresh; |
| 24 | 26 | } |
| 27 | + | |
| 28 | +bool __init arch_perf_nmi_is_available(void) | |
| 29 | +{ | |
| 30 | + /* | |
| 31 | + * hardlockup_detector_perf_init() will success even if Pseudo-NMI turns off, | |
| 32 | + * however, the pmu interrupts will act like a normal interrupt instead of | |
| 33 | + * NMI and the hardlockup detector would be broken. | |
| 34 | + */ | |
| 35 | + return arm_pmu_irq_is_nmi(); | |
| 36 | +} | |
| @@ -687,6 +687,11 @@ static int armpmu_get_cpu_irq(struct arm_pmu *pmu, int cpu) · 686 unmodified lines | ||
| 687 | 687 | return per_cpu(hw_events->irq, cpu); |
| 688 | 688 | } |
| 689 | 689 | |
| 690 | +bool arm_pmu_irq_is_nmi(void) | |
| 691 | +{ | |
| 692 | + return has_nmi; | |
| 693 | +} | |
| 694 | + | |
| 690 | 695 | /* |
| 691 | 696 | * PMU hardware loses all context when a CPU goes offline. |
| 692 | 697 | * When a CPU is hotplugged back in, since some hardware registers are |
| @@ -22,6 +22,7 @@ · 21 unmodified lines | ||
| 22 | 22 | #include <linux/platform_device.h> |
| 23 | 23 | #include <linux/sched_clock.h> |
| 24 | 24 | #include <linux/smp.h> |
| 25 | +#include <linux/nmi.h> | |
| 25 | 26 | |
| 26 | 27 | #include <asm/arm_pmuv3.h> |
| 27 | 28 | |
| @@ -1348,10 +1349,17 @@ static struct platform_driver armv8_pmu_driver = { · 1320 unmodified lines | ||
| 1348 | 1349 | |
| 1349 | 1350 | static int __init armv8_pmu_driver_init(void) |
| 1350 | 1351 | { |
| 1352 | + int ret; | |
| 1353 | + | |
| 1351 | 1354 | if (acpi_disabled) |
| 1352 | − return platform_driver_register(&armv8_pmu_driver); | |
| 1355 | + ret = platform_driver_register(&armv8_pmu_driver); | |
| 1353 | 1356 | else |
| 1354 | − return arm_pmu_acpi_probe(armv8_pmuv3_pmu_init); | |
| 1357 | + ret = arm_pmu_acpi_probe(armv8_pmuv3_pmu_init); | |
| 1358 | + | |
| 1359 | + if (!ret) | |
| 1360 | + lockup_detector_retry_init(); | |
| 1361 | + | |
| 1362 | + return ret; | |
| 1355 | 1363 | } |
| 1356 | 1364 | device_initcall(armv8_pmu_driver_init) |
| 1357 | 1365 | |
| @@ -171,6 +171,8 @@ void kvm_host_pmu_init(struct arm_pmu *pmu); · 170 unmodified lines | ||
| 171 | 171 | #define kvm_host_pmu_init(x) do { } while(0) |
| 172 | 172 | #endif |
| 173 | 173 | |
| 174 | +bool arm_pmu_irq_is_nmi(void); | |
| 175 | + | |
| 174 | 176 | /* Internal functions only for core arm_pmu code */ |
| 175 | 177 | struct arm_pmu *armpmu_alloc(void); |
| 176 | 178 | void armpmu_free(struct arm_pmu *pmu); |