Oxford Semiconductor 950 serial port devices have a 128-byte FIFO and in the enhanced (650) mode, which we select in `autoconfig_has_efr' with the ECB bit set in the EFR register, they support the receive interrupt trigger level selectable with FCR bits 7:6 from the set of 16, 32, 112, 120. This applies to the original OX16C950 discrete UART[1] as well as 950 cores embedded into more complex devices. For these devices we set the default to 112, which sets an excessively high level of 112 or 7/8 of the FIFO capacity, unlike with other port types where we choose at most 1/2 of their respective FIFO capacities. Additionally we don't make the trigger level configurable. Consequently frequent input overruns happen with high bit rates where hardware flow control cannot be used (e.g. terminal applications) even with otherwise highly-performant systems. Lower the default receive interrupt trigger level to 32 then, and make it configurable. Document the trigger levels along with other port types, including the set of 16, 32, 64, 112 for the transmit interrupt as well[2]. References: [1] "OX16C950 rev B High Performance UART with 128 byte FIFOs", Oxford Semiconductor, Inc., DS-0031, Sep 05, Table 10: "Receiver Trigger Levels", p. 22 [2] same, Table 9: "Transmit Interrupt Trigger Levels", p. 22
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| 62 | * ST16C654: 8 16 56 60 8 16 32 56 PORT_16654 | 62 | * ST16C654: 8 16 56 60 8 16 32 56 PORT_16654 |
| 63 | * TI16C750: 1 16 32 56 xx xx xx xx PORT_16750 | 63 | * TI16C750: 1 16 32 56 xx xx xx xx PORT_16750 |
| 64 | * TI16C752: 8 16 56 60 8 16 32 56 | 64 | * TI16C752: 8 16 56 60 8 16 32 56 |
| 65 | * OX16C950: 16 32 112 120 16 32 64 112 PORT_16C950 | ||
| 65 | * Tegra: 1 4 8 14 16 8 4 1 PORT_TEGRA | 66 | * Tegra: 1 4 8 14 16 8 4 1 PORT_TEGRA |
| 66 | */ | 67 | */ |
| 67 | #define UART_FCR_R_TRIG_00 0x00 | 68 | #define UART_FCR_R_TRIG_00 0x00 |