Add RISC-V to the list of supported kexec architectures, we need to add the definition early-on so that later patches can use it. EM_RISCV is 243 as per ELF psABI specification here: https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
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| @@ -42,6 +42,7 @@ · 41 unmodified lines | |||
| 42 | #define KEXEC_ARCH_MIPS_LE (10 << 16) | 42 | #define KEXEC_ARCH_MIPS_LE (10 << 16) |
| 43 | #define KEXEC_ARCH_MIPS ( 8 << 16) | 43 | #define KEXEC_ARCH_MIPS ( 8 << 16) |
| 44 | #define KEXEC_ARCH_AARCH64 (183 << 16) | 44 | #define KEXEC_ARCH_AARCH64 (183 << 16) |
| 45 | #define KEXEC_ARCH_RISCV (243 << 16) | ||
| 45 | 46 | ||
| 46 | /* The artificial cap on the number of segments passed to kexec_load. */ | 47 | /* The artificial cap on the number of segments passed to kexec_load. */ |
| 47 | #define KEXEC_SEGMENT_MAX 16 | 48 | #define KEXEC_SEGMENT_MAX 16 |