History

Merge branch 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull IRQ chip updates from Ingo Molnar: "A late irqchips update: - New TI INTR/INTA set of drivers - Rewrite of the stm32mp1-exti driver as a platform driver - Update the IOMMU MSI mapping API to be RT friendly - A number of cleanups and other low impact fixes" * 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (34 commits) iommu/dma-iommu: Remove iommu_dma_map_msi_msg() irqchip/gic-v3-mbi: Don't map the MSI page in mbi_compose_m{b, s}i_msg() irqchip/ls-scfg-msi: Don't map the MSI page in ls_scfg_msi_compose_msg() irqchip/gic-v3-its: Don't map the MSI page in its_irq_compose_msi_msg() irqchip/gicv2m: Don't map the MSI page in gicv2m_compose_msi_msg() iommu/dma-iommu: Split iommu_dma_map_msi_msg() in two parts genirq/msi: Add a new field in msi_desc to store an IOMMU cookie arm64: arch_k3: Enable interrupt controller drivers irqchip/ti-sci-inta: Add msi domain support soc: ti: Add MSI domain bus support for Interrupt Aggregator irqchip/ti-sci-inta: Add support for Interrupt Aggregator driver dt-bindings: irqchip: Introduce TISCI Interrupt Aggregator bindings irqchip/ti-sci-intr: Add support for Interrupt Router driver dt-bindings: irqchip: Introduce TISCI Interrupt router bindings gpio: thunderx: Use the default parent apis for {request,release}_resources genirq: Introduce irq_chip_{request,release}_resource_parent() apis firmware: ti_sci: Add helper apis to manage resources firmware: ti_sci: Add RM mapping table for am654 firmware: ti_sci: Add support for IRQ management firmware: ti_sci: Add support for RM core ops ...

Linus Torvalds committed 7 years ago

Commit d9351ea2 parents 39feaa3 fb4e05938 files · +2511 −229Browse files

Showing the changes to include/linux (7 of 38 files). Show all

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7 files
  1. include/linux/dma-iommu.h +22 −2
  2. include/linux/irq.h +2 −0
  3. include/linux/irqchip/arm-gic-v3.h +6 −6
  4. include/linux/irqdomain.h +1 −0
  5. include/linux/msi.h +36 −0
  6. include/linux/soc/ti/ti_sci_inta_msi.h +23 −0
  7. include/linux/soc/ti/ti_sci_protocol.h +124 −0
include/linux/dma-iommu.h+22−2
@@ -71,12 +71,25 @@ void iommu_dma_unmap_resource(struct device *dev, dma_addr_t handle, · 70 unmodified lines
7171 size_t size, enum dma_data_direction dir, unsigned long attrs);
7272
7373 /* The DMA API isn't _quite_ the whole story, though... */
74−void iommu_dma_map_msi_msg(int irq, struct msi_msg *msg);
74+/*
75+ * iommu_dma_prepare_msi() - Map the MSI page in the IOMMU device
76+ *
77+ * The MSI page will be stored in @desc.
78+ *
79+ * Return: 0 on success otherwise an error describing the failure.
80+ */
81+int iommu_dma_prepare_msi(struct msi_desc *desc, phys_addr_t msi_addr);
82+
83+/* Update the MSI message if required. */
84+void iommu_dma_compose_msi_msg(struct msi_desc *desc,
85+ struct msi_msg *msg);
86+
7587 void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list);
7688
7789 #else
7890
7991 struct iommu_domain;
92+struct msi_desc;
8093 struct msi_msg;
8194 struct device;
8295
@@ -99,7 +112,14 @@ static inline void iommu_put_dma_cookie(struct iommu_domain *domain) · 16 unmodified lines
99112 {
100113 }
101114
102−static inline void iommu_dma_map_msi_msg(int irq, struct msi_msg *msg)
115+static inline int iommu_dma_prepare_msi(struct msi_desc *desc,
116+ phys_addr_t msi_addr)
117+{
118+ return 0;
119+}
120+
121+static inline void iommu_dma_compose_msi_msg(struct msi_desc *desc,
122+ struct msi_msg *msg)
103123 {
104124 }
105125
include/linux/irq.h+2−0
@@ -625,6 +625,8 @@ extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on); · 624 unmodified lines
625625 extern int irq_chip_set_vcpu_affinity_parent(struct irq_data *data,
626626 void *vcpu_info);
627627 extern int irq_chip_set_type_parent(struct irq_data *data, unsigned int type);
628+extern int irq_chip_request_resources_parent(struct irq_data *data);
629+extern void irq_chip_release_resources_parent(struct irq_data *data);
628630 #endif
629631
630632 /* Handling of unhandled and spurious interrupts: */
include/linux/irqchip/arm-gic-v3.h+6−6
@@ -165,7 +165,7 @@ · 164 unmodified lines
165165 #define GICR_PROPBASER_nCnB GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, nCnB)
166166 #define GICR_PROPBASER_nC GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, nC)
167167 #define GICR_PROPBASER_RaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWt)
168−#define GICR_PROPBASER_RaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWt)
168+#define GICR_PROPBASER_RaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWb)
169169 #define GICR_PROPBASER_WaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WaWt)
170170 #define GICR_PROPBASER_WaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WaWb)
171171 #define GICR_PROPBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWaWt)
@@ -192,7 +192,7 @@ · 20 unmodified lines
192192 #define GICR_PENDBASER_nCnB GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, nCnB)
193193 #define GICR_PENDBASER_nC GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, nC)
194194 #define GICR_PENDBASER_RaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWt)
195−#define GICR_PENDBASER_RaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWt)
195+#define GICR_PENDBASER_RaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWb)
196196 #define GICR_PENDBASER_WaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WaWt)
197197 #define GICR_PENDBASER_WaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WaWb)
198198 #define GICR_PENDBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWaWt)
@@ -251,7 +251,7 @@ · 52 unmodified lines
251251 #define GICR_VPROPBASER_nCnB GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, nCnB)
252252 #define GICR_VPROPBASER_nC GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, nC)
253253 #define GICR_VPROPBASER_RaWt GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, RaWt)
254−#define GICR_VPROPBASER_RaWb GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, RaWt)
254+#define GICR_VPROPBASER_RaWb GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, RaWb)
255255 #define GICR_VPROPBASER_WaWt GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, WaWt)
256256 #define GICR_VPROPBASER_WaWb GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, WaWb)
257257 #define GICR_VPROPBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, RaWaWt)
@@ -277,7 +277,7 @@ · 19 unmodified lines
277277 #define GICR_VPENDBASER_nCnB GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, nCnB)
278278 #define GICR_VPENDBASER_nC GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, nC)
279279 #define GICR_VPENDBASER_RaWt GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWt)
280−#define GICR_VPENDBASER_RaWb GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWt)
280+#define GICR_VPENDBASER_RaWb GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWb)
281281 #define GICR_VPENDBASER_WaWt GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, WaWt)
282282 #define GICR_VPENDBASER_WaWb GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, WaWb)
283283 #define GICR_VPENDBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWaWt)
@@ -351,7 +351,7 @@ · 67 unmodified lines
351351 #define GITS_CBASER_nCnB GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, nCnB)
352352 #define GITS_CBASER_nC GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, nC)
353353 #define GITS_CBASER_RaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWt)
354−#define GITS_CBASER_RaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWt)
354+#define GITS_CBASER_RaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWb)
355355 #define GITS_CBASER_WaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, WaWt)
356356 #define GITS_CBASER_WaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, WaWb)
357357 #define GITS_CBASER_RaWaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWaWt)
@@ -377,7 +377,7 @@ · 19 unmodified lines
377377 #define GITS_BASER_nCnB GIC_BASER_CACHEABILITY(GITS_BASER, INNER, nCnB)
378378 #define GITS_BASER_nC GIC_BASER_CACHEABILITY(GITS_BASER, INNER, nC)
379379 #define GITS_BASER_RaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWt)
380−#define GITS_BASER_RaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWt)
380+#define GITS_BASER_RaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWb)
381381 #define GITS_BASER_WaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, WaWt)
382382 #define GITS_BASER_WaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, WaWb)
383383 #define GITS_BASER_RaWaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWaWt)
include/linux/irqdomain.h+1−0
@@ -82,6 +82,7 @@ enum irq_domain_bus_token { · 81 unmodified lines
8282 DOMAIN_BUS_NEXUS,
8383 DOMAIN_BUS_IPI,
8484 DOMAIN_BUS_FSL_MC_MSI,
85+ DOMAIN_BUS_TI_SCI_INTA_MSI,
8586 };
8687
8788 /**
include/linux/msi.h+36−0
@@ -47,6 +47,14 @@ struct fsl_mc_msi_desc { · 46 unmodified lines
4747 u16 msi_index;
4848 };
4949
50+/**
51+ * ti_sci_inta_msi_desc - TISCI based INTA specific msi descriptor data
52+ * @dev_index: TISCI device index
53+ */
54+struct ti_sci_inta_msi_desc {
55+ u16 dev_index;
56+};
57+
5058 /**
5159 * struct msi_desc - Descriptor structure for MSI based interrupts
5260 * @list: List head for management
@@ -68,6 +76,7 @@ struct fsl_mc_msi_desc { · 15 unmodified lines
6876 * @mask_base: [PCI MSI-X] Mask register base address
6977 * @platform: [platform] Platform device specific msi descriptor data
7078 * @fsl_mc: [fsl-mc] FSL MC device specific msi descriptor data
79+ * @inta: [INTA] TISCI based INTA specific msi descriptor data
7180 */
7281 struct msi_desc {
7382 /* Shared device/bus type independent data */
@@ -77,6 +86,9 @@ struct msi_desc { · 3 unmodified lines
7786 struct device *dev;
7887 struct msi_msg msg;
7988 struct irq_affinity_desc *affinity;
89+#ifdef CONFIG_IRQ_MSI_IOMMU
90+ const void *iommu_cookie;
91+#endif
8092
8193 union {
8294 /* PCI MSI/X specific data */
@@ -106,6 +118,7 @@ struct msi_desc { · 23 unmodified lines
106118 */
107119 struct platform_msi_desc platform;
108120 struct fsl_mc_msi_desc fsl_mc;
121+ struct ti_sci_inta_msi_desc inta;
109122 };
110123 };
111124
@@ -119,6 +132,29 @@ struct msi_desc { · 7 unmodified lines
119132 #define for_each_msi_entry_safe(desc, tmp, dev) \
120133 list_for_each_entry_safe((desc), (tmp), dev_to_msi_list((dev)), list)
121134
135+#ifdef CONFIG_IRQ_MSI_IOMMU
136+static inline const void *msi_desc_get_iommu_cookie(struct msi_desc *desc)
137+{
138+ return desc->iommu_cookie;
139+}
140+
141+static inline void msi_desc_set_iommu_cookie(struct msi_desc *desc,
142+ const void *iommu_cookie)
143+{
144+ desc->iommu_cookie = iommu_cookie;
145+}
146+#else
147+static inline const void *msi_desc_get_iommu_cookie(struct msi_desc *desc)
148+{
149+ return NULL;
150+}
151+
152+static inline void msi_desc_set_iommu_cookie(struct msi_desc *desc,
153+ const void *iommu_cookie)
154+{
155+}
156+#endif
157+
122158 #ifdef CONFIG_PCI_MSI
123159 #define first_pci_msi_entry(pdev) first_msi_entry(&(pdev)->dev)
124160 #define for_each_pci_msi_entry(desc, pdev) \
include/linux/soc/ti/ti_sci_inta_msi.h+23−0
@@ -0,0 +1,23 @@
1+/* SPDX-License-Identifier: GPL-2.0 */
2+/*
3+ * Texas Instruments' K3 TI SCI INTA MSI helper
4+ *
5+ * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
6+ * Lokesh Vutla <lokeshvutla@ti.com>
7+ */
8+
9+#ifndef __INCLUDE_LINUX_TI_SCI_INTA_MSI_H
10+#define __INCLUDE_LINUX_TI_SCI_INTA_MSI_H
11+
12+#include <linux/msi.h>
13+#include <linux/soc/ti/ti_sci_protocol.h>
14+
15+struct irq_domain
16+*ti_sci_inta_msi_create_irq_domain(struct fwnode_handle *fwnode,
17+ struct msi_domain_info *info,
18+ struct irq_domain *parent);
19+int ti_sci_inta_msi_domain_alloc_irqs(struct device *dev,
20+ struct ti_sci_resource *res);
21+unsigned int ti_sci_inta_msi_get_virq(struct device *dev, u32 index);
22+void ti_sci_inta_msi_domain_free_irqs(struct device *dev);
23+#endif /* __INCLUDE_LINUX_IRQCHIP_TI_SCI_INTA_H */
include/linux/soc/ti/ti_sci_protocol.h+124−0
@@ -192,15 +192,68 @@ struct ti_sci_clk_ops { · 191 unmodified lines
192192 u64 *current_freq);
193193 };
194194
195+/**
196+ * struct ti_sci_rm_core_ops - Resource management core operations
197+ * @get_range: Get a range of resources belonging to ti sci host.
198+ * @get_rage_from_shost: Get a range of resources belonging to
199+ * specified host id.
200+ * - s_host: Host processing entity to which the
201+ * resources are allocated
202+ *
203+ * NOTE: for these functions, all the parameters are consolidated and defined
204+ * as below:
205+ * - handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle
206+ * - dev_id: TISCI device ID.
207+ * - subtype: Resource assignment subtype that is being requested
208+ * from the given device.
209+ * - range_start: Start index of the resource range
210+ * - range_end: Number of resources in the range
211+ */
212+struct ti_sci_rm_core_ops {
213+ int (*get_range)(const struct ti_sci_handle *handle, u32 dev_id,
214+ u8 subtype, u16 *range_start, u16 *range_num);
215+ int (*get_range_from_shost)(const struct ti_sci_handle *handle,
216+ u32 dev_id, u8 subtype, u8 s_host,
217+ u16 *range_start, u16 *range_num);
218+};
219+
220+/**
221+ * struct ti_sci_rm_irq_ops: IRQ management operations
222+ * @set_irq: Set an IRQ route between the requested source
223+ * and destination
224+ * @set_event_map: Set an Event based peripheral irq to Interrupt
225+ * Aggregator.
226+ * @free_irq: Free an an IRQ route between the requested source
227+ * destination.
228+ * @free_event_map: Free an event based peripheral irq to Interrupt
229+ * Aggregator.
230+ */
231+struct ti_sci_rm_irq_ops {
232+ int (*set_irq)(const struct ti_sci_handle *handle, u16 src_id,
233+ u16 src_index, u16 dst_id, u16 dst_host_irq);
234+ int (*set_event_map)(const struct ti_sci_handle *handle, u16 src_id,
235+ u16 src_index, u16 ia_id, u16 vint,
236+ u16 global_event, u8 vint_status_bit);
237+ int (*free_irq)(const struct ti_sci_handle *handle, u16 src_id,
238+ u16 src_index, u16 dst_id, u16 dst_host_irq);
239+ int (*free_event_map)(const struct ti_sci_handle *handle, u16 src_id,
240+ u16 src_index, u16 ia_id, u16 vint,
241+ u16 global_event, u8 vint_status_bit);
242+};
243+
195244 /**
196245 * struct ti_sci_ops - Function support for TI SCI
197246 * @dev_ops: Device specific operations
198247 * @clk_ops: Clock specific operations
248+ * @rm_core_ops: Resource management core operations.
249+ * @rm_irq_ops: IRQ management specific operations
199250 */
200251 struct ti_sci_ops {
201252 struct ti_sci_core_ops core_ops;
202253 struct ti_sci_dev_ops dev_ops;
203254 struct ti_sci_clk_ops clk_ops;
255+ struct ti_sci_rm_core_ops rm_core_ops;
256+ struct ti_sci_rm_irq_ops rm_irq_ops;
204257 };
205258
206259 /**
@@ -213,10 +266,47 @@ struct ti_sci_handle { · 6 unmodified lines
213266 struct ti_sci_ops ops;
214267 };
215268
269+#define TI_SCI_RESOURCE_NULL 0xffff
270+
271+/**
272+ * struct ti_sci_resource_desc - Description of TI SCI resource instance range.
273+ * @start: Start index of the resource.
274+ * @num: Number of resources.
275+ * @res_map: Bitmap to manage the allocation of these resources.
276+ */
277+struct ti_sci_resource_desc {
278+ u16 start;
279+ u16 num;
280+ unsigned long *res_map;
281+};
282+
283+/**
284+ * struct ti_sci_resource - Structure representing a resource assigned
285+ * to a device.
286+ * @sets: Number of sets available from this resource type
287+ * @lock: Lock to guard the res map in each set.
288+ * @desc: Array of resource descriptors.
289+ */
290+struct ti_sci_resource {
291+ u16 sets;
292+ raw_spinlock_t lock;
293+ struct ti_sci_resource_desc *desc;
294+};
295+
216296 #if IS_ENABLED(CONFIG_TI_SCI_PROTOCOL)
217297 const struct ti_sci_handle *ti_sci_get_handle(struct device *dev);
218298 int ti_sci_put_handle(const struct ti_sci_handle *handle);
219299 const struct ti_sci_handle *devm_ti_sci_get_handle(struct device *dev);
300+const struct ti_sci_handle *ti_sci_get_by_phandle(struct device_node *np,
301+ const char *property);
302+const struct ti_sci_handle *devm_ti_sci_get_by_phandle(struct device *dev,
303+ const char *property);
304+u16 ti_sci_get_free_resource(struct ti_sci_resource *res);
305+void ti_sci_release_resource(struct ti_sci_resource *res, u16 id);
306+u32 ti_sci_get_num_resources(struct ti_sci_resource *res);
307+struct ti_sci_resource *
308+devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
309+ struct device *dev, u32 dev_id, char *of_prop);
220310
221311 #else /* CONFIG_TI_SCI_PROTOCOL */
222312
@@ -236,6 +326,40 @@ const struct ti_sci_handle *devm_ti_sci_get_handle(struct device *dev) · 13 unmodified lines
236326 return ERR_PTR(-EINVAL);
237327 }
238328
329+static inline
330+const struct ti_sci_handle *ti_sci_get_by_phandle(struct device_node *np,
331+ const char *property)
332+{
333+ return ERR_PTR(-EINVAL);
334+}
335+
336+static inline
337+const struct ti_sci_handle *devm_ti_sci_get_by_phandle(struct device *dev,
338+ const char *property)
339+{
340+ return ERR_PTR(-EINVAL);
341+}
342+
343+static inline u16 ti_sci_get_free_resource(struct ti_sci_resource *res)
344+{
345+ return TI_SCI_RESOURCE_NULL;
346+}
347+
348+static inline void ti_sci_release_resource(struct ti_sci_resource *res, u16 id)
349+{
350+}
351+
352+static inline u32 ti_sci_get_num_resources(struct ti_sci_resource *res)
353+{
354+ return 0;
355+}
356+
357+static inline struct ti_sci_resource *
358+devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
359+ struct device *dev, u32 dev_id, char *of_prop)
360+{
361+ return ERR_PTR(-EINVAL);
362+}
239363 #endif /* CONFIG_TI_SCI_PROTOCOL */
240364
241365 #endif /* __TISCI_PROTOCOL_H */

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