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Merge drm-upstream/drm-next into drm-misc-next

We got a few conflicts in drm_atomic.c after merging the DRM writeback support, now we need a backmerge to unlock develop development on drm-misc-next.

Gustavo Padovan committed 8 years ago

Commit d98c71d2 parents d67b6a2 daf06781448 files · +57660 −24139Browse files

Showing the changes to include/uapi (23 of 1448 files). Show all

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23 files
  1. include/uapi/drm/amdgpu_drm.h +20 −0
  2. include/uapi/drm/exynos_drm.h +240 −0
  3. include/uapi/drm/tegra_drm.h +482 −10
  4. include/uapi/linux/if_infiniband.h +1 −1
  5. include/uapi/linux/nl80211.h +2 −0
  6. include/uapi/linux/rds.h +1 −1
  7. include/uapi/linux/tls.h +1 −1
  8. include/uapi/rdma/cxgb3-abi.h +1 −1
  9. include/uapi/rdma/cxgb4-abi.h +1 −1
  10. include/uapi/rdma/hns-abi.h +1 −1
  11. include/uapi/rdma/ib_user_cm.h +1 −1
  12. include/uapi/rdma/ib_user_ioctl_verbs.h +1 −1
  13. include/uapi/rdma/ib_user_mad.h +1 −1
  14. include/uapi/rdma/ib_user_sa.h +1 −1
  15. include/uapi/rdma/ib_user_verbs.h +1 −1
  16. include/uapi/rdma/mlx4-abi.h +1 −1
  17. include/uapi/rdma/mlx5-abi.h +1 −1
  18. include/uapi/rdma/mthca-abi.h +1 −1
  19. include/uapi/rdma/nes-abi.h +1 −1
  20. include/uapi/rdma/qedr-abi.h +1 −1
  21. include/uapi/rdma/rdma_user_cm.h +1 −1
  22. include/uapi/rdma/rdma_user_ioctl.h +1 −1
  23. include/uapi/rdma/rdma_user_rxe.h +1 −1
include/uapi/drm/amdgpu_drm.h+20−0
@@ -78,6 +78,12 @@ extern "C" { · 77 unmodified lines
78#define AMDGPU_GEM_DOMAIN_GDS 0x878#define AMDGPU_GEM_DOMAIN_GDS 0x8
79#define AMDGPU_GEM_DOMAIN_GWS 0x1079#define AMDGPU_GEM_DOMAIN_GWS 0x10
80#define AMDGPU_GEM_DOMAIN_OA 0x2080#define AMDGPU_GEM_DOMAIN_OA 0x20
81#define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \
82 AMDGPU_GEM_DOMAIN_GTT | \
83 AMDGPU_GEM_DOMAIN_VRAM | \
84 AMDGPU_GEM_DOMAIN_GDS | \
85 AMDGPU_GEM_DOMAIN_GWS | \
86 AMDGPU_GEM_DOMAIN_OA)
81 87
82/* Flag that CPU access will be required for the case of VRAM domain */88/* Flag that CPU access will be required for the case of VRAM domain */
83#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)89#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
@@ -95,6 +101,10 @@ extern "C" { · 11 unmodified lines
95#define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)101#define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)
96/* Flag that BO sharing will be explicitly synchronized */102/* Flag that BO sharing will be explicitly synchronized */
97#define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7)103#define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7)
104/* Flag that indicates allocating MQD gart on GFX9, where the mtype
105 * for the second page onward should be set to NC.
106 */
107#define AMDGPU_GEM_CREATE_MQD_GFX9 (1 << 8)
98 108
99struct drm_amdgpu_gem_create_in {109struct drm_amdgpu_gem_create_in {
100 /** the requested memory size */110 /** the requested memory size */
@@ -520,6 +530,10 @@ union drm_amdgpu_cs { · 419 unmodified lines
520/* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */530/* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */
521#define AMDGPU_IB_FLAG_PREEMPT (1<<2)531#define AMDGPU_IB_FLAG_PREEMPT (1<<2)
522 532
533/* The IB fence should do the L2 writeback but not invalidate any shader
534 * caches (L2/vL1/sL1/I$). */
535#define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3)
536
523struct drm_amdgpu_cs_chunk_ib {537struct drm_amdgpu_cs_chunk_ib {
524 __u32 _pad;538 __u32 _pad;
525 /** AMDGPU_IB_FLAG_* */539 /** AMDGPU_IB_FLAG_* */
@@ -620,6 +634,12 @@ struct drm_amdgpu_cs_chunk_data { · 94 unmodified lines
620 #define AMDGPU_INFO_FW_ASD 0x0d634 #define AMDGPU_INFO_FW_ASD 0x0d
621 /* Subquery id: Query VCN firmware version */635 /* Subquery id: Query VCN firmware version */
622 #define AMDGPU_INFO_FW_VCN 0x0e636 #define AMDGPU_INFO_FW_VCN 0x0e
637 /* Subquery id: Query GFX RLC SRLC firmware version */
638 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f
639 /* Subquery id: Query GFX RLC SRLG firmware version */
640 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10
641 /* Subquery id: Query GFX RLC SRLS firmware version */
642 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11
623/* number of bytes moved for TTM migration */643/* number of bytes moved for TTM migration */
624#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f644#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
625/* the used VRAM size */645/* the used VRAM size */
include/uapi/drm/exynos_drm.h+240−0
@@ -135,6 +135,219 @@ struct drm_exynos_g2d_exec { · 134 unmodified lines
135 __u64 async;135 __u64 async;
136};136};
137 137
138/* Exynos DRM IPP v2 API */
139
140/**
141 * Enumerate available IPP hardware modules.
142 *
143 * @count_ipps: size of ipp_id array / number of ipp modules (set by driver)
144 * @reserved: padding
145 * @ipp_id_ptr: pointer to ipp_id array or NULL
146 */
147struct drm_exynos_ioctl_ipp_get_res {
148 __u32 count_ipps;
149 __u32 reserved;
150 __u64 ipp_id_ptr;
151};
152
153enum drm_exynos_ipp_format_type {
154 DRM_EXYNOS_IPP_FORMAT_SOURCE = 0x01,
155 DRM_EXYNOS_IPP_FORMAT_DESTINATION = 0x02,
156};
157
158struct drm_exynos_ipp_format {
159 __u32 fourcc;
160 __u32 type;
161 __u64 modifier;
162};
163
164enum drm_exynos_ipp_capability {
165 DRM_EXYNOS_IPP_CAP_CROP = 0x01,
166 DRM_EXYNOS_IPP_CAP_ROTATE = 0x02,
167 DRM_EXYNOS_IPP_CAP_SCALE = 0x04,
168 DRM_EXYNOS_IPP_CAP_CONVERT = 0x08,
169};
170
171/**
172 * Get IPP hardware capabilities and supported image formats.
173 *
174 * @ipp_id: id of IPP module to query
175 * @capabilities: bitmask of drm_exynos_ipp_capability (set by driver)
176 * @reserved: padding
177 * @formats_count: size of formats array (in entries) / number of filled
178 * formats (set by driver)
179 * @formats_ptr: pointer to formats array or NULL
180 */
181struct drm_exynos_ioctl_ipp_get_caps {
182 __u32 ipp_id;
183 __u32 capabilities;
184 __u32 reserved;
185 __u32 formats_count;
186 __u64 formats_ptr;
187};
188
189enum drm_exynos_ipp_limit_type {
190 /* size (horizontal/vertial) limits, in pixels (min, max, alignment) */
191 DRM_EXYNOS_IPP_LIMIT_TYPE_SIZE = 0x0001,
192 /* scale ratio (horizonta/vertial), 16.16 fixed point (min, max) */
193 DRM_EXYNOS_IPP_LIMIT_TYPE_SCALE = 0x0002,
194
195 /* image buffer area */
196 DRM_EXYNOS_IPP_LIMIT_SIZE_BUFFER = 0x0001 << 16,
197 /* src/dst rectangle area */
198 DRM_EXYNOS_IPP_LIMIT_SIZE_AREA = 0x0002 << 16,
199 /* src/dst rectangle area when rotation enabled */
200 DRM_EXYNOS_IPP_LIMIT_SIZE_ROTATED = 0x0003 << 16,
201
202 DRM_EXYNOS_IPP_LIMIT_TYPE_MASK = 0x000f,
203 DRM_EXYNOS_IPP_LIMIT_SIZE_MASK = 0x000f << 16,
204};
205
206struct drm_exynos_ipp_limit_val {
207 __u32 min;
208 __u32 max;
209 __u32 align;
210 __u32 reserved;
211};
212
213/**
214 * IPP module limitation.
215 *
216 * @type: limit type (see drm_exynos_ipp_limit_type enum)
217 * @reserved: padding
218 * @h: horizontal limits
219 * @v: vertical limits
220 */
221struct drm_exynos_ipp_limit {
222 __u32 type;
223 __u32 reserved;
224 struct drm_exynos_ipp_limit_val h;
225 struct drm_exynos_ipp_limit_val v;
226};
227
228/**
229 * Get IPP limits for given image format.
230 *
231 * @ipp_id: id of IPP module to query
232 * @fourcc: image format code (see DRM_FORMAT_* in drm_fourcc.h)
233 * @modifier: image format modifier (see DRM_FORMAT_MOD_* in drm_fourcc.h)
234 * @type: source/destination identifier (drm_exynos_ipp_format_flag enum)
235 * @limits_count: size of limits array (in entries) / number of filled entries
236 * (set by driver)
237 * @limits_ptr: pointer to limits array or NULL
238 */
239struct drm_exynos_ioctl_ipp_get_limits {
240 __u32 ipp_id;
241 __u32 fourcc;
242 __u64 modifier;
243 __u32 type;
244 __u32 limits_count;
245 __u64 limits_ptr;
246};
247
248enum drm_exynos_ipp_task_id {
249 /* buffer described by struct drm_exynos_ipp_task_buffer */
250 DRM_EXYNOS_IPP_TASK_BUFFER = 0x0001,
251 /* rectangle described by struct drm_exynos_ipp_task_rect */
252 DRM_EXYNOS_IPP_TASK_RECTANGLE = 0x0002,
253 /* transformation described by struct drm_exynos_ipp_task_transform */
254 DRM_EXYNOS_IPP_TASK_TRANSFORM = 0x0003,
255 /* alpha configuration described by struct drm_exynos_ipp_task_alpha */
256 DRM_EXYNOS_IPP_TASK_ALPHA = 0x0004,
257
258 /* source image data (for buffer and rectangle chunks) */
259 DRM_EXYNOS_IPP_TASK_TYPE_SOURCE = 0x0001 << 16,
260 /* destination image data (for buffer and rectangle chunks) */
261 DRM_EXYNOS_IPP_TASK_TYPE_DESTINATION = 0x0002 << 16,
262};
263
264/**
265 * Memory buffer with image data.
266 *
267 * @id: must be DRM_EXYNOS_IPP_TASK_BUFFER
268 * other parameters are same as for AddFB2 generic DRM ioctl
269 */
270struct drm_exynos_ipp_task_buffer {
271 __u32 id;
272 __u32 fourcc;
273 __u32 width, height;
274 __u32 gem_id[4];
275 __u32 offset[4];
276 __u32 pitch[4];
277 __u64 modifier;
278};
279
280/**
281 * Rectangle for processing.
282 *
283 * @id: must be DRM_EXYNOS_IPP_TASK_RECTANGLE
284 * @reserved: padding
285 * @x,@y: left corner in pixels
286 * @w,@h: width/height in pixels
287 */
288struct drm_exynos_ipp_task_rect {
289 __u32 id;
290 __u32 reserved;
291 __u32 x;
292 __u32 y;
293 __u32 w;
294 __u32 h;
295};
296
297/**
298 * Image tranformation description.
299 *
300 * @id: must be DRM_EXYNOS_IPP_TASK_TRANSFORM
301 * @rotation: DRM_MODE_ROTATE_* and DRM_MODE_REFLECT_* values
302 */
303struct drm_exynos_ipp_task_transform {
304 __u32 id;
305 __u32 rotation;
306};
307
308/**
309 * Image global alpha configuration for formats without alpha values.
310 *
311 * @id: must be DRM_EXYNOS_IPP_TASK_ALPHA
312 * @value: global alpha value (0-255)
313 */
314struct drm_exynos_ipp_task_alpha {
315 __u32 id;
316 __u32 value;
317};
318
319enum drm_exynos_ipp_flag {
320 /* generate DRM event after processing */
321 DRM_EXYNOS_IPP_FLAG_EVENT = 0x01,
322 /* dry run, only check task parameters */
323 DRM_EXYNOS_IPP_FLAG_TEST_ONLY = 0x02,
324 /* non-blocking processing */
325 DRM_EXYNOS_IPP_FLAG_NONBLOCK = 0x04,
326};
327
328#define DRM_EXYNOS_IPP_FLAGS (DRM_EXYNOS_IPP_FLAG_EVENT |\
329 DRM_EXYNOS_IPP_FLAG_TEST_ONLY | DRM_EXYNOS_IPP_FLAG_NONBLOCK)
330
331/**
332 * Perform image processing described by array of drm_exynos_ipp_task_*
333 * structures (parameters array).
334 *
335 * @ipp_id: id of IPP module to run the task
336 * @flags: bitmask of drm_exynos_ipp_flag values
337 * @reserved: padding
338 * @params_size: size of parameters array (in bytes)
339 * @params_ptr: pointer to parameters array or NULL
340 * @user_data: (optional) data for drm event
341 */
342struct drm_exynos_ioctl_ipp_commit {
343 __u32 ipp_id;
344 __u32 flags;
345 __u32 reserved;
346 __u32 params_size;
347 __u64 params_ptr;
348 __u64 user_data;
349};
350
138#define DRM_EXYNOS_GEM_CREATE 0x00351#define DRM_EXYNOS_GEM_CREATE 0x00
139#define DRM_EXYNOS_GEM_MAP 0x01352#define DRM_EXYNOS_GEM_MAP 0x01
140/* Reserved 0x03 ~ 0x05 for exynos specific gem ioctl */353/* Reserved 0x03 ~ 0x05 for exynos specific gem ioctl */
@@ -147,6 +360,11 @@ struct drm_exynos_g2d_exec { · 6 unmodified lines
147#define DRM_EXYNOS_G2D_EXEC 0x22360#define DRM_EXYNOS_G2D_EXEC 0x22
148 361
149/* Reserved 0x30 ~ 0x33 for obsolete Exynos IPP ioctls */362/* Reserved 0x30 ~ 0x33 for obsolete Exynos IPP ioctls */
363/* IPP - Image Post Processing */
364#define DRM_EXYNOS_IPP_GET_RESOURCES 0x40
365#define DRM_EXYNOS_IPP_GET_CAPS 0x41
366#define DRM_EXYNOS_IPP_GET_LIMITS 0x42
367#define DRM_EXYNOS_IPP_COMMIT 0x43
150 368
151#define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \369#define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \
152 DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create)370 DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create)
@@ -165,8 +383,20 @@ struct drm_exynos_g2d_exec { · 12 unmodified lines
165#define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + \383#define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + \
166 DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec)384 DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec)
167 385
386#define DRM_IOCTL_EXYNOS_IPP_GET_RESOURCES DRM_IOWR(DRM_COMMAND_BASE + \
387 DRM_EXYNOS_IPP_GET_RESOURCES, \
388 struct drm_exynos_ioctl_ipp_get_res)
389#define DRM_IOCTL_EXYNOS_IPP_GET_CAPS DRM_IOWR(DRM_COMMAND_BASE + \
390 DRM_EXYNOS_IPP_GET_CAPS, struct drm_exynos_ioctl_ipp_get_caps)
391#define DRM_IOCTL_EXYNOS_IPP_GET_LIMITS DRM_IOWR(DRM_COMMAND_BASE + \
392 DRM_EXYNOS_IPP_GET_LIMITS, \
393 struct drm_exynos_ioctl_ipp_get_limits)
394#define DRM_IOCTL_EXYNOS_IPP_COMMIT DRM_IOWR(DRM_COMMAND_BASE + \
395 DRM_EXYNOS_IPP_COMMIT, struct drm_exynos_ioctl_ipp_commit)
396
168/* EXYNOS specific events */397/* EXYNOS specific events */
169#define DRM_EXYNOS_G2D_EVENT 0x80000000398#define DRM_EXYNOS_G2D_EVENT 0x80000000
399#define DRM_EXYNOS_IPP_EVENT 0x80000002
170 400
171struct drm_exynos_g2d_event {401struct drm_exynos_g2d_event {
172 struct drm_event base;402 struct drm_event base;
@@ -177,6 +407,16 @@ struct drm_exynos_g2d_event { · 4 unmodified lines
177 __u32 reserved;407 __u32 reserved;
178};408};
179 409
410struct drm_exynos_ipp_event {
411 struct drm_event base;
412 __u64 user_data;
413 __u32 tv_sec;
414 __u32 tv_usec;
415 __u32 ipp_id;
416 __u32 sequence;
417 __u64 reserved;
418};
419
180#if defined(__cplusplus)420#if defined(__cplusplus)
181}421}
182#endif422#endif
include/uapi/drm/tegra_drm.h+482−10
@@ -32,143 +32,615 @@ extern "C" { · 31 unmodified lines
32#define DRM_TEGRA_GEM_CREATE_TILED (1 << 0)32#define DRM_TEGRA_GEM_CREATE_TILED (1 << 0)
33#define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1)33#define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1)
34 34
35/**
36 * struct drm_tegra_gem_create - parameters for the GEM object creation IOCTL
37 */
35struct drm_tegra_gem_create {38struct drm_tegra_gem_create {
39 /**
40 * @size:
41 *
42 * The size, in bytes, of the buffer object to be created.
43 */
36 __u64 size;44 __u64 size;
45
46 /**
47 * @flags:
48 *
49 * A bitmask of flags that influence the creation of GEM objects:
50 *
51 * DRM_TEGRA_GEM_CREATE_TILED
52 * Use the 16x16 tiling format for this buffer.
53 *
54 * DRM_TEGRA_GEM_CREATE_BOTTOM_UP
55 * The buffer has a bottom-up layout.
56 */
37 __u32 flags;57 __u32 flags;
58
59 /**
60 * @handle:
61 *
62 * The handle of the created GEM object. Set by the kernel upon
63 * successful completion of the IOCTL.
64 */
38 __u32 handle;65 __u32 handle;
39};66};
40 67
68/**
69 * struct drm_tegra_gem_mmap - parameters for the GEM mmap IOCTL
70 */
41struct drm_tegra_gem_mmap {71struct drm_tegra_gem_mmap {
72 /**
73 * @handle:
74 *
75 * Handle of the GEM object to obtain an mmap offset for.
76 */
42 __u32 handle;77 __u32 handle;
78
79 /**
80 * @pad:
81 *
82 * Structure padding that may be used in the future. Must be 0.
83 */
43 __u32 pad;84 __u32 pad;
85
86 /**
87 * @offset:
88 *
89 * The mmap offset for the given GEM object. Set by the kernel upon
90 * successful completion of the IOCTL.
91 */
44 __u64 offset;92 __u64 offset;
45};93};
46 94
95/**
96 * struct drm_tegra_syncpt_read - parameters for the read syncpoint IOCTL
97 */
47struct drm_tegra_syncpt_read {98struct drm_tegra_syncpt_read {
99 /**
100 * @id:
101 *
102 * ID of the syncpoint to read the current value from.
103 */
48 __u32 id;104 __u32 id;
105
106 /**
107 * @value:
108 *
109 * The current syncpoint value. Set by the kernel upon successful
110 * completion of the IOCTL.
111 */
49 __u32 value;112 __u32 value;
50};113};
51 114
115/**
116 * struct drm_tegra_syncpt_incr - parameters for the increment syncpoint IOCTL
117 */
52struct drm_tegra_syncpt_incr {118struct drm_tegra_syncpt_incr {
119 /**
120 * @id:
121 *
122 * ID of the syncpoint to increment.
123 */
53 __u32 id;124 __u32 id;
125
126 /**
127 * @pad:
128 *
129 * Structure padding that may be used in the future. Must be 0.
130 */
54 __u32 pad;131 __u32 pad;
55};132};
56 133
134/**
135 * struct drm_tegra_syncpt_wait - parameters for the wait syncpoint IOCTL
136 */
57struct drm_tegra_syncpt_wait {137struct drm_tegra_syncpt_wait {
138 /**
139 * @id:
140 *
141 * ID of the syncpoint to wait on.
142 */
58 __u32 id;143 __u32 id;
144
145 /**
146 * @thresh:
147 *
148 * Threshold value for which to wait.
149 */
59 __u32 thresh;150 __u32 thresh;
151
152 /**
153 * @timeout:
154 *
155 * Timeout, in milliseconds, to wait.
156 */
60 __u32 timeout;157 __u32 timeout;
158
159 /**
160 * @value:
161 *
162 * The new syncpoint value after the wait. Set by the kernel upon
163 * successful completion of the IOCTL.
164 */
61 __u32 value;165 __u32 value;
62};166};
63 167
64#define DRM_TEGRA_NO_TIMEOUT (0xffffffff)168#define DRM_TEGRA_NO_TIMEOUT (0xffffffff)
65 169
170/**
171 * struct drm_tegra_open_channel - parameters for the open channel IOCTL
172 */
66struct drm_tegra_open_channel {173struct drm_tegra_open_channel {
174 /**
175 * @client:
176 *
177 * The client ID for this channel.
178 */
67 __u32 client;179 __u32 client;
180
181 /**
182 * @pad:
183 *
184 * Structure padding that may be used in the future. Must be 0.
185 */
68 __u32 pad;186 __u32 pad;
187
188 /**
189 * @context:
190 *
191 * The application context of this channel. Set by the kernel upon
192 * successful completion of the IOCTL. This context needs to be passed
193 * to the DRM_TEGRA_CHANNEL_CLOSE or the DRM_TEGRA_SUBMIT IOCTLs.
194 */
69 __u64 context;195 __u64 context;
70};196};
71 197
198/**
199 * struct drm_tegra_close_channel - parameters for the close channel IOCTL
200 */
72struct drm_tegra_close_channel {201struct drm_tegra_close_channel {
202 /**
203 * @context:
204 *
205 * The application context of this channel. This is obtained from the
206 * DRM_TEGRA_OPEN_CHANNEL IOCTL.
207 */
73 __u64 context;208 __u64 context;
74};209};
75 210
211/**
212 * struct drm_tegra_get_syncpt - parameters for the get syncpoint IOCTL
213 */
76struct drm_tegra_get_syncpt {214struct drm_tegra_get_syncpt {
215 /**
216 * @context:
217 *
218 * The application context identifying the channel for which to obtain
219 * the syncpoint ID.
220 */
77 __u64 context;221 __u64 context;
222
223 /**
224 * @index:
225 *
226 * Index of the client syncpoint for which to obtain the ID.
227 */
78 __u32 index;228 __u32 index;
229
230 /**
231 * @id:
232 *
233 * The ID of the given syncpoint. Set by the kernel upon successful
234 * completion of the IOCTL.
235 */
79 __u32 id;236 __u32 id;
80};237};
81 238
239/**
240 * struct drm_tegra_get_syncpt_base - parameters for the get wait base IOCTL
241 */
82struct drm_tegra_get_syncpt_base {242struct drm_tegra_get_syncpt_base {
243 /**
244 * @context:
245 *
246 * The application context identifying for which channel to obtain the
247 * wait base.
248 */
83 __u64 context;249 __u64 context;
250
251 /**
252 * @syncpt:
253 *
254 * ID of the syncpoint for which to obtain the wait base.
255 */
84 __u32 syncpt;256 __u32 syncpt;
257
258 /**
259 * @id:
260 *
261 * The ID of the wait base corresponding to the client syncpoint. Set
262 * by the kernel upon successful completion of the IOCTL.
263 */
85 __u32 id;264 __u32 id;
86};265};
87 266
267/**
268 * struct drm_tegra_syncpt - syncpoint increment operation
269 */
88struct drm_tegra_syncpt {270struct drm_tegra_syncpt {
271 /**
272 * @id:
273 *
274 * ID of the syncpoint to operate on.
275 */
89 __u32 id;276 __u32 id;
277
278 /**
279 * @incrs:
280 *
281 * Number of increments to perform for the syncpoint.
282 */
90 __u32 incrs;283 __u32 incrs;
91};284};
92 285
286/**
287 * struct drm_tegra_cmdbuf - structure describing a command buffer
288 */
93struct drm_tegra_cmdbuf {289struct drm_tegra_cmdbuf {
290 /**
291 * @handle:
292 *
293 * Handle to a GEM object containing the command buffer.
294 */
94 __u32 handle;295 __u32 handle;
296
297 /**
298 * @offset:
299 *
300 * Offset, in bytes, into the GEM object identified by @handle at
301 * which the command buffer starts.
302 */
95 __u32 offset;303 __u32 offset;
304
305 /**
306 * @words:
307 *
308 * Number of 32-bit words in this command buffer.
309 */
96 __u32 words;310 __u32 words;
311
312 /**
313 * @pad:
314 *
315 * Structure padding that may be used in the future. Must be 0.
316 */
97 __u32 pad;317 __u32 pad;
98};318};
99 319
320/**
321 * struct drm_tegra_reloc - GEM object relocation structure
322 */
100struct drm_tegra_reloc {323struct drm_tegra_reloc {
101 struct {324 struct {
325 /**
326 * @cmdbuf.handle:
327 *
328 * Handle to the GEM object containing the command buffer for
329 * which to perform this GEM object relocation.
330 */
102 __u32 handle;331 __u32 handle;
332
333 /**
334 * @cmdbuf.offset:
335 *
336 * Offset, in bytes, into the command buffer at which to
337 * insert the relocated address.
338 */
103 __u32 offset;339 __u32 offset;
104 } cmdbuf;340 } cmdbuf;
105 struct {341 struct {
342 /**
343 * @target.handle:
344 *
345 * Handle to the GEM object to be relocated.
346 */
106 __u32 handle;347 __u32 handle;
348
349 /**
350 * @target.offset:
351 *
352 * Offset, in bytes, into the target GEM object at which the
353 * relocated data starts.
354 */
107 __u32 offset;355 __u32 offset;
108 } target;356 } target;
357
358 /**
359 * @shift:
360 *
361 * The number of bits by which to shift relocated addresses.
362 */
109 __u32 shift;363 __u32 shift;
364
365 /**
366 * @pad:
367 *
368 * Structure padding that may be used in the future. Must be 0.
369 */
110 __u32 pad;370 __u32 pad;
111};371};
112 372
373/**
374 * struct drm_tegra_waitchk - wait check structure
375 */
113struct drm_tegra_waitchk {376struct drm_tegra_waitchk {
377 /**
378 * @handle:
379 *
380 * Handle to the GEM object containing a command stream on which to
381 * perform the wait check.
382 */
114 __u32 handle;383 __u32 handle;
384
385 /**
386 * @offset:
387 *
388 * Offset, in bytes, of the location in the command stream to perform
389 * the wait check on.
390 */
115 __u32 offset;391 __u32 offset;
392
393 /**
394 * @syncpt:
395 *
396 * ID of the syncpoint to wait check.
397 */
116 __u32 syncpt;398 __u32 syncpt;
399
400 /**
401 * @thresh:
402 *
403 * Threshold value for which to check.
404 */
117 __u32 thresh;405 __u32 thresh;
118};406};
119 407
408/**
409 * struct drm_tegra_submit - job submission structure
410 */
120struct drm_tegra_submit {411struct drm_tegra_submit {
412 /**
413 * @context:
414 *
415 * The application context identifying the channel to use for the
416 * execution of this job.
417 */
121 __u64 context;418 __u64 context;
419
420 /**
421 * @num_syncpts:
422 *
423 * The number of syncpoints operated on by this job. This defines the
424 * length of the array pointed to by @syncpts.
425 */
122 __u32 num_syncpts;426 __u32 num_syncpts;
427
428 /**
429 * @num_cmdbufs:
430 *
431 * The number of command buffers to execute as part of this job. This
432 * defines the length of the array pointed to by @cmdbufs.
433 */
123 __u32 num_cmdbufs;434 __u32 num_cmdbufs;
435
436 /**
437 * @num_relocs:
438 *
439 * The number of relocations to perform before executing this job.
440 * This defines the length of the array pointed to by @relocs.
441 */
124 __u32 num_relocs;442 __u32 num_relocs;
443
444 /**
445 * @num_waitchks:
446 *
447 * The number of wait checks to perform as part of this job. This
448 * defines the length of the array pointed to by @waitchks.
449 */
125 __u32 num_waitchks;450 __u32 num_waitchks;
451
452 /**
453 * @waitchk_mask:
454 *
455 * Bitmask of valid wait checks.
456 */
126 __u32 waitchk_mask;457 __u32 waitchk_mask;
458
459 /**
460 * @timeout:
461 *
462 * Timeout, in milliseconds, before this job is cancelled.
463 */
127 __u32 timeout;464 __u32 timeout;
465
466 /**
467 * @syncpts:
468 *
469 * A pointer to an array of &struct drm_tegra_syncpt structures that
470 * specify the syncpoint operations performed as part of this job.
471 * The number of elements in the array must be equal to the value
472 * given by @num_syncpts.
473 */
128 __u64 syncpts;474 __u64 syncpts;
475
476 /**
477 * @cmdbufs:
478 *
479 * A pointer to an array of &struct drm_tegra_cmdbuf structures that
480 * define the command buffers to execute as part of this job. The
481 * number of elements in the array must be equal to the value given
482 * by @num_syncpts.
483 */
129 __u64 cmdbufs;484 __u64 cmdbufs;
485
486 /**
487 * @relocs:
488 *
489 * A pointer to an array of &struct drm_tegra_reloc structures that
490 * specify the relocations that need to be performed before executing
491 * this job. The number of elements in the array must be equal to the
492 * value given by @num_relocs.
493 */
130 __u64 relocs;494 __u64 relocs;
495
496 /**
497 * @waitchks:
498 *
499 * A pointer to an array of &struct drm_tegra_waitchk structures that
500 * specify the wait checks to be performed while executing this job.
501 * The number of elements in the array must be equal to the value
502 * given by @num_waitchks.
503 */
131 __u64 waitchks;504 __u64 waitchks;
132 __u32 fence; /* Return value */
133 505
134 __u32 reserved[5]; /* future expansion */506 /**
507 * @fence:
508 *
509 * The threshold of the syncpoint associated with this job after it
510 * has been completed. Set by the kernel upon successful completion of
511 * the IOCTL. This can be used with the DRM_TEGRA_SYNCPT_WAIT IOCTL to
512 * wait for this job to be finished.
513 */
514 __u32 fence;
515
516 /**
517 * @reserved:
518 *
519 * This field is reserved for future use. Must be 0.
520 */
521 __u32 reserved[5];
135};522};
136 523
137#define DRM_TEGRA_GEM_TILING_MODE_PITCH 0524#define DRM_TEGRA_GEM_TILING_MODE_PITCH 0
138#define DRM_TEGRA_GEM_TILING_MODE_TILED 1525#define DRM_TEGRA_GEM_TILING_MODE_TILED 1
139#define DRM_TEGRA_GEM_TILING_MODE_BLOCK 2526#define DRM_TEGRA_GEM_TILING_MODE_BLOCK 2
140 527
528/**
529 * struct drm_tegra_gem_set_tiling - parameters for the set tiling IOCTL
530 */
141struct drm_tegra_gem_set_tiling {531struct drm_tegra_gem_set_tiling {
142 /* input */532 /**
533 * @handle:
534 *
535 * Handle to the GEM object for which to set the tiling parameters.
536 */
143 __u32 handle;537 __u32 handle;
538
539 /**
540 * @mode:
541 *
542 * The tiling mode to set. Must be one of:
543 *
544 * DRM_TEGRA_GEM_TILING_MODE_PITCH
545 * pitch linear format
546 *
547 * DRM_TEGRA_GEM_TILING_MODE_TILED
548 * 16x16 tiling format
549 *
550 * DRM_TEGRA_GEM_TILING_MODE_BLOCK
551 * 16Bx2 tiling format
552 */
144 __u32 mode;553 __u32 mode;
554
555 /**
556 * @value:
557 *
558 * The value to set for the tiling mode parameter.
559 */
145 __u32 value;560 __u32 value;
561
562 /**
563 * @pad:
564 *
565 * Structure padding that may be used in the future. Must be 0.
566 */
146 __u32 pad;567 __u32 pad;
147};568};
148 569
570/**
571 * struct drm_tegra_gem_get_tiling - parameters for the get tiling IOCTL
572 */
149struct drm_tegra_gem_get_tiling {573struct drm_tegra_gem_get_tiling {
150 /* input */574 /**
575 * @handle:
576 *
577 * Handle to the GEM object for which to query the tiling parameters.
578 */
151 __u32 handle;579 __u32 handle;
152 /* output */580
581 /**
582 * @mode:
583 *
584 * The tiling mode currently associated with the GEM object. Set by
585 * the kernel upon successful completion of the IOCTL.
586 */
153 __u32 mode;587 __u32 mode;
588
589 /**
590 * @value:
591 *
592 * The tiling mode parameter currently associated with the GEM object.
593 * Set by the kernel upon successful completion of the IOCTL.
594 */
154 __u32 value;595 __u32 value;
596
597 /**
598 * @pad:
599 *
600 * Structure padding that may be used in the future. Must be 0.
601 */
155 __u32 pad;602 __u32 pad;
156};603};
157 604
158#define DRM_TEGRA_GEM_BOTTOM_UP (1 << 0)605#define DRM_TEGRA_GEM_BOTTOM_UP (1 << 0)
159#define DRM_TEGRA_GEM_FLAGS (DRM_TEGRA_GEM_BOTTOM_UP)606#define DRM_TEGRA_GEM_FLAGS (DRM_TEGRA_GEM_BOTTOM_UP)
160 607
608/**
609 * struct drm_tegra_gem_set_flags - parameters for the set flags IOCTL
610 */
161struct drm_tegra_gem_set_flags {611struct drm_tegra_gem_set_flags {
162 /* input */612 /**
613 * @handle:
614 *
615 * Handle to the GEM object for which to set the flags.
616 */
163 __u32 handle;617 __u32 handle;
164 /* output */618
619 /**
620 * @flags:
621 *
622 * The flags to set for the GEM object.
623 */
165 __u32 flags;624 __u32 flags;
166};625};
167 626
627/**
628 * struct drm_tegra_gem_get_flags - parameters for the get flags IOCTL
629 */
168struct drm_tegra_gem_get_flags {630struct drm_tegra_gem_get_flags {
169 /* input */631 /**
632 * @handle:
633 *
634 * Handle to the GEM object for which to query the flags.
635 */
170 __u32 handle;636 __u32 handle;
171 /* output */637
638 /**
639 * @flags:
640 *
641 * The flags currently associated with the GEM object. Set by the
642 * kernel upon successful completion of the IOCTL.
643 */
172 __u32 flags;644 __u32 flags;
173};645};
174 646
@@ -193,7 +665,7 @@ struct drm_tegra_gem_get_flags { · 18 unmodified lines
193#define DRM_IOCTL_TEGRA_SYNCPT_INCR DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_INCR, struct drm_tegra_syncpt_incr)665#define DRM_IOCTL_TEGRA_SYNCPT_INCR DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_INCR, struct drm_tegra_syncpt_incr)
194#define DRM_IOCTL_TEGRA_SYNCPT_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_WAIT, struct drm_tegra_syncpt_wait)666#define DRM_IOCTL_TEGRA_SYNCPT_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_WAIT, struct drm_tegra_syncpt_wait)
195#define DRM_IOCTL_TEGRA_OPEN_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_OPEN_CHANNEL, struct drm_tegra_open_channel)667#define DRM_IOCTL_TEGRA_OPEN_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_OPEN_CHANNEL, struct drm_tegra_open_channel)
196#define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_open_channel)668#define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_close_channel)
197#define DRM_IOCTL_TEGRA_GET_SYNCPT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, struct drm_tegra_get_syncpt)669#define DRM_IOCTL_TEGRA_GET_SYNCPT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, struct drm_tegra_get_syncpt)
198#define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit)670#define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit)
199#define DRM_IOCTL_TEGRA_GET_SYNCPT_BASE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT_BASE, struct drm_tegra_get_syncpt_base)671#define DRM_IOCTL_TEGRA_GET_SYNCPT_BASE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT_BASE, struct drm_tegra_get_syncpt_base)
include/uapi/linux/if_infiniband.h+1−1
@@ -1,4 +1,4 @@
1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) */
2/*2/*
3 * This software is available to you under a choice of one of two3 * This software is available to you under a choice of one of two
4 * licenses. You may choose to be licensed under the terms of the GNU4 * licenses. You may choose to be licensed under the terms of the GNU
include/uapi/linux/nl80211.h+2−0
@@ -2698,6 +2698,8 @@ enum nl80211_attrs { · 2697 unmodified lines
2698#define NL80211_ATTR_KEYS NL80211_ATTR_KEYS2698#define NL80211_ATTR_KEYS NL80211_ATTR_KEYS
2699#define NL80211_ATTR_FEATURE_FLAGS NL80211_ATTR_FEATURE_FLAGS2699#define NL80211_ATTR_FEATURE_FLAGS NL80211_ATTR_FEATURE_FLAGS
2700 2700
2701#define NL80211_WIPHY_NAME_MAXLEN 128
2702
2701#define NL80211_MAX_SUPP_RATES 322703#define NL80211_MAX_SUPP_RATES 32
2702#define NL80211_MAX_SUPP_HT_RATES 772704#define NL80211_MAX_SUPP_HT_RATES 77
2703#define NL80211_MAX_SUPP_REG_RULES 642705#define NL80211_MAX_SUPP_REG_RULES 64
include/uapi/linux/rds.h+1−1
@@ -1,4 +1,4 @@
1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) */1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) */
2/*2/*
3 * Copyright (c) 2008 Oracle. All rights reserved.3 * Copyright (c) 2008 Oracle. All rights reserved.
4 *4 *
include/uapi/linux/tls.h+1−1
@@ -1,4 +1,4 @@
1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) */1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) */
2/*2/*
3 * Copyright (c) 2016-2017, Mellanox Technologies. All rights reserved.3 * Copyright (c) 2016-2017, Mellanox Technologies. All rights reserved.
4 *4 *
include/uapi/rdma/cxgb3-abi.h+1−1
@@ -1,4 +1,4 @@
1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) */1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) */
2/*2/*
3 * Copyright (c) 2006 Chelsio, Inc. All rights reserved.3 * Copyright (c) 2006 Chelsio, Inc. All rights reserved.
4 *4 *
include/uapi/rdma/cxgb4-abi.h+1−1
@@ -1,4 +1,4 @@
1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) */1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) */
2/*2/*
3 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.3 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
4 *4 *
include/uapi/rdma/hns-abi.h+1−1
@@ -1,4 +1,4 @@
1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) */1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) */
2/*2/*
3 * Copyright (c) 2016 Hisilicon Limited.3 * Copyright (c) 2016 Hisilicon Limited.
4 *4 *
include/uapi/rdma/ib_user_cm.h+1−1
@@ -1,4 +1,4 @@
1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) */1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) */
2/*2/*
3 * Copyright (c) 2005 Topspin Communications. All rights reserved.3 * Copyright (c) 2005 Topspin Communications. All rights reserved.
4 * Copyright (c) 2005 Intel Corporation. All rights reserved.4 * Copyright (c) 2005 Intel Corporation. All rights reserved.
include/uapi/rdma/ib_user_ioctl_verbs.h+1−1
@@ -1,4 +1,4 @@
1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) */1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) */
2/*2/*
3 * Copyright (c) 2017-2018, Mellanox Technologies inc. All rights reserved.3 * Copyright (c) 2017-2018, Mellanox Technologies inc. All rights reserved.
4 *4 *
include/uapi/rdma/ib_user_mad.h+1−1
@@ -1,4 +1,4 @@
1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) */1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) */
2/*2/*
3 * Copyright (c) 2004 Topspin Communications. All rights reserved.3 * Copyright (c) 2004 Topspin Communications. All rights reserved.
4 * Copyright (c) 2005 Voltaire, Inc. All rights reserved.4 * Copyright (c) 2005 Voltaire, Inc. All rights reserved.
include/uapi/rdma/ib_user_sa.h+1−1
@@ -1,4 +1,4 @@
1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) */1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) */
2/*2/*
3 * Copyright (c) 2005 Intel Corporation. All rights reserved.3 * Copyright (c) 2005 Intel Corporation. All rights reserved.
4 *4 *
include/uapi/rdma/ib_user_verbs.h+1−1
@@ -1,4 +1,4 @@
1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) */1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) */
2/*2/*
3 * Copyright (c) 2005 Topspin Communications. All rights reserved.3 * Copyright (c) 2005 Topspin Communications. All rights reserved.
4 * Copyright (c) 2005, 2006 Cisco Systems. All rights reserved.4 * Copyright (c) 2005, 2006 Cisco Systems. All rights reserved.
include/uapi/rdma/mlx4-abi.h+1−1
@@ -1,4 +1,4 @@
1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) */1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) */
2/*2/*
3 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.3 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
4 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.4 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
include/uapi/rdma/mlx5-abi.h+1−1
@@ -1,4 +1,4 @@
1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) */1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) */
2/*2/*
3 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.3 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 *4 *
include/uapi/rdma/mthca-abi.h+1−1
@@ -1,4 +1,4 @@
1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) */1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) */
2/*2/*
3 * Copyright (c) 2005 Topspin Communications. All rights reserved.3 * Copyright (c) 2005 Topspin Communications. All rights reserved.
4 * Copyright (c) 2005, 2006 Cisco Systems. All rights reserved.4 * Copyright (c) 2005, 2006 Cisco Systems. All rights reserved.
include/uapi/rdma/nes-abi.h+1−1
@@ -1,4 +1,4 @@
1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) */1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) */
2/*2/*
3 * Copyright (c) 2006 - 2011 Intel Corporation. All rights reserved.3 * Copyright (c) 2006 - 2011 Intel Corporation. All rights reserved.
4 * Copyright (c) 2005 Topspin Communications. All rights reserved.4 * Copyright (c) 2005 Topspin Communications. All rights reserved.
include/uapi/rdma/qedr-abi.h+1−1
@@ -1,4 +1,4 @@
1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) */1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) */
2/* QLogic qedr NIC Driver2/* QLogic qedr NIC Driver
3 * Copyright (c) 2015-2016 QLogic Corporation3 * Copyright (c) 2015-2016 QLogic Corporation
4 *4 *
include/uapi/rdma/rdma_user_cm.h+1−1
@@ -1,4 +1,4 @@
1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) */1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) */
2/*2/*
3 * Copyright (c) 2005-2006 Intel Corporation. All rights reserved.3 * Copyright (c) 2005-2006 Intel Corporation. All rights reserved.
4 *4 *
include/uapi/rdma/rdma_user_ioctl.h+1−1
@@ -1,4 +1,4 @@
1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) */1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) */
2/*2/*
3 * Copyright (c) 2016 Mellanox Technologies, LTD. All rights reserved.3 * Copyright (c) 2016 Mellanox Technologies, LTD. All rights reserved.
4 *4 *
include/uapi/rdma/rdma_user_rxe.h+1−1
@@ -1,4 +1,4 @@
1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) */1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) */
2/*2/*
3 * Copyright (c) 2016 Mellanox Technologies Ltd. All rights reserved.3 * Copyright (c) 2016 Mellanox Technologies Ltd. All rights reserved.
4 *4 *

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