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net: hns3: create common cmdq resource allocate/free/query APIs

The PF and VF cmdq module resource allocate/free/query APIs are almost the same espect the suffixes of API names. These same implementations bring double development and bugfix work. This patch creates common cmdq resource allocate/free/query APIs called by PF and VF cmdq init/uninit APIs. The next patch will use the new unified APIs to replace init/uninit APIs.

Jie Wang committed 4 years ago

Commit da77aef1 parent 076bb532 files · +311 −1Browse files

Unified · Split

2 files
  1. drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c +223 −0
  2. drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h +88 −1
drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c+223−0
@@ -4,6 +4,229 @@ · 3 unmodified lines
44 #include "hnae3.h"
55 #include "hclge_comm_cmd.h"
66
7+static void hclge_comm_cmd_config_regs(struct hclge_comm_hw *hw,
8+ struct hclge_comm_cmq_ring *ring)
9+{
10+ dma_addr_t dma = ring->desc_dma_addr;
11+ u32 reg_val;
12+
13+ if (ring->ring_type == HCLGE_COMM_TYPE_CSQ) {
14+ hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CSQ_BASEADDR_L_REG,
15+ lower_32_bits(dma));
16+ hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CSQ_BASEADDR_H_REG,
17+ upper_32_bits(dma));
18+ reg_val = hclge_comm_read_dev(hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG);
19+ reg_val &= HCLGE_COMM_NIC_SW_RST_RDY;
20+ reg_val |= ring->desc_num >> HCLGE_COMM_NIC_CMQ_DESC_NUM_S;
21+ hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG, reg_val);
22+ hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CSQ_HEAD_REG, 0);
23+ hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CSQ_TAIL_REG, 0);
24+ } else {
25+ hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CRQ_BASEADDR_L_REG,
26+ lower_32_bits(dma));
27+ hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CRQ_BASEADDR_H_REG,
28+ upper_32_bits(dma));
29+ reg_val = ring->desc_num >> HCLGE_COMM_NIC_CMQ_DESC_NUM_S;
30+ hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CRQ_DEPTH_REG, reg_val);
31+ hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CRQ_HEAD_REG, 0);
32+ hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CRQ_TAIL_REG, 0);
33+ }
34+}
35+
36+void hclge_comm_cmd_init_regs(struct hclge_comm_hw *hw)
37+{
38+ hclge_comm_cmd_config_regs(hw, &hw->cmq.csq);
39+ hclge_comm_cmd_config_regs(hw, &hw->cmq.crq);
40+}
41+
42+void hclge_comm_cmd_reuse_desc(struct hclge_desc *desc, bool is_read)
43+{
44+ desc->flag = cpu_to_le16(HCLGE_COMM_CMD_FLAG_NO_INTR |
45+ HCLGE_COMM_CMD_FLAG_IN);
46+ if (is_read)
47+ desc->flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_WR);
48+ else
49+ desc->flag &= cpu_to_le16(~HCLGE_COMM_CMD_FLAG_WR);
50+}
51+
52+static void hclge_comm_set_default_capability(struct hnae3_ae_dev *ae_dev,
53+ bool is_pf)
54+{
55+ set_bit(HNAE3_DEV_SUPPORT_FD_B, ae_dev->caps);
56+ set_bit(HNAE3_DEV_SUPPORT_GRO_B, ae_dev->caps);
57+ if (is_pf && ae_dev->dev_version == HNAE3_DEVICE_VERSION_V2) {
58+ set_bit(HNAE3_DEV_SUPPORT_FEC_B, ae_dev->caps);
59+ set_bit(HNAE3_DEV_SUPPORT_PAUSE_B, ae_dev->caps);
60+ }
61+}
62+
63+void hclge_comm_cmd_setup_basic_desc(struct hclge_desc *desc,
64+ enum hclge_comm_opcode_type opcode,
65+ bool is_read)
66+{
67+ memset((void *)desc, 0, sizeof(struct hclge_desc));
68+ desc->opcode = cpu_to_le16(opcode);
69+ desc->flag = cpu_to_le16(HCLGE_COMM_CMD_FLAG_NO_INTR |
70+ HCLGE_COMM_CMD_FLAG_IN);
71+
72+ if (is_read)
73+ desc->flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_WR);
74+}
75+
76+int hclge_comm_firmware_compat_config(struct hnae3_ae_dev *ae_dev, bool is_pf,
77+ struct hclge_comm_hw *hw, bool en)
78+{
79+ struct hclge_comm_firmware_compat_cmd *req;
80+ struct hclge_desc desc;
81+ u32 compat = 0;
82+
83+ hclge_comm_cmd_setup_basic_desc(&desc, HCLGE_COMM_OPC_IMP_COMPAT_CFG,
84+ false);
85+
86+ if (en) {
87+ req = (struct hclge_comm_firmware_compat_cmd *)desc.data;
88+
89+ hnae3_set_bit(compat, HCLGE_COMM_LINK_EVENT_REPORT_EN_B, 1);
90+ hnae3_set_bit(compat, HCLGE_COMM_NCSI_ERROR_REPORT_EN_B, 1);
91+ if (hclge_comm_dev_phy_imp_supported(ae_dev))
92+ hnae3_set_bit(compat, HCLGE_COMM_PHY_IMP_EN_B, 1);
93+ hnae3_set_bit(compat, HCLGE_COMM_MAC_STATS_EXT_EN_B, 1);
94+ hnae3_set_bit(compat, HCLGE_COMM_SYNC_RX_RING_HEAD_EN_B, 1);
95+
96+ req->compat = cpu_to_le32(compat);
97+ }
98+
99+ return hclge_comm_cmd_send(hw, &desc, 1, is_pf);
100+}
101+
102+void hclge_comm_free_cmd_desc(struct hclge_comm_cmq_ring *ring)
103+{
104+ int size = ring->desc_num * sizeof(struct hclge_desc);
105+
106+ if (!ring->desc)
107+ return;
108+
109+ dma_free_coherent(&ring->pdev->dev, size,
110+ ring->desc, ring->desc_dma_addr);
111+ ring->desc = NULL;
112+}
113+
114+static int hclge_comm_alloc_cmd_desc(struct hclge_comm_cmq_ring *ring)
115+{
116+ int size = ring->desc_num * sizeof(struct hclge_desc);
117+
118+ ring->desc = dma_alloc_coherent(&ring->pdev->dev,
119+ size, &ring->desc_dma_addr, GFP_KERNEL);
120+ if (!ring->desc)
121+ return -ENOMEM;
122+
123+ return 0;
124+}
125+
126+static __le32 hclge_comm_build_api_caps(void)
127+{
128+ u32 api_caps = 0;
129+
130+ hnae3_set_bit(api_caps, HCLGE_COMM_API_CAP_FLEX_RSS_TBL_B, 1);
131+
132+ return cpu_to_le32(api_caps);
133+}
134+
135+static const struct hclge_comm_caps_bit_map hclge_pf_cmd_caps[] = {
136+ {HCLGE_COMM_CAP_UDP_GSO_B, HNAE3_DEV_SUPPORT_UDP_GSO_B},
137+ {HCLGE_COMM_CAP_PTP_B, HNAE3_DEV_SUPPORT_PTP_B},
138+ {HCLGE_COMM_CAP_INT_QL_B, HNAE3_DEV_SUPPORT_INT_QL_B},
139+ {HCLGE_COMM_CAP_TQP_TXRX_INDEP_B, HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B},
140+ {HCLGE_COMM_CAP_HW_TX_CSUM_B, HNAE3_DEV_SUPPORT_HW_TX_CSUM_B},
141+ {HCLGE_COMM_CAP_UDP_TUNNEL_CSUM_B, HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B},
142+ {HCLGE_COMM_CAP_FD_FORWARD_TC_B, HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B},
143+ {HCLGE_COMM_CAP_FEC_B, HNAE3_DEV_SUPPORT_FEC_B},
144+ {HCLGE_COMM_CAP_PAUSE_B, HNAE3_DEV_SUPPORT_PAUSE_B},
145+ {HCLGE_COMM_CAP_PHY_IMP_B, HNAE3_DEV_SUPPORT_PHY_IMP_B},
146+ {HCLGE_COMM_CAP_QB_B, HNAE3_DEV_SUPPORT_QB_B},
147+ {HCLGE_COMM_CAP_TX_PUSH_B, HNAE3_DEV_SUPPORT_TX_PUSH_B},
148+ {HCLGE_COMM_CAP_RAS_IMP_B, HNAE3_DEV_SUPPORT_RAS_IMP_B},
149+ {HCLGE_COMM_CAP_RXD_ADV_LAYOUT_B, HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B},
150+ {HCLGE_COMM_CAP_PORT_VLAN_BYPASS_B,
151+ HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B},
152+ {HCLGE_COMM_CAP_PORT_VLAN_BYPASS_B, HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B},
153+};
154+
155+static const struct hclge_comm_caps_bit_map hclge_vf_cmd_caps[] = {
156+ {HCLGE_COMM_CAP_UDP_GSO_B, HNAE3_DEV_SUPPORT_UDP_GSO_B},
157+ {HCLGE_COMM_CAP_INT_QL_B, HNAE3_DEV_SUPPORT_INT_QL_B},
158+ {HCLGE_COMM_CAP_TQP_TXRX_INDEP_B, HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B},
159+ {HCLGE_COMM_CAP_HW_TX_CSUM_B, HNAE3_DEV_SUPPORT_HW_TX_CSUM_B},
160+ {HCLGE_COMM_CAP_UDP_TUNNEL_CSUM_B, HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B},
161+ {HCLGE_COMM_CAP_QB_B, HNAE3_DEV_SUPPORT_QB_B},
162+ {HCLGE_COMM_CAP_TX_PUSH_B, HNAE3_DEV_SUPPORT_TX_PUSH_B},
163+ {HCLGE_COMM_CAP_RXD_ADV_LAYOUT_B, HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B},
164+};
165+
166+static void
167+hclge_comm_parse_capability(struct hnae3_ae_dev *ae_dev, bool is_pf,
168+ struct hclge_comm_query_version_cmd *cmd)
169+{
170+ const struct hclge_comm_caps_bit_map *caps_map =
171+ is_pf ? hclge_pf_cmd_caps : hclge_vf_cmd_caps;
172+ u32 size = is_pf ? ARRAY_SIZE(hclge_pf_cmd_caps) :
173+ ARRAY_SIZE(hclge_vf_cmd_caps);
174+ u32 caps, i;
175+
176+ caps = __le32_to_cpu(cmd->caps[0]);
177+ for (i = 0; i < size; i++)
178+ if (hnae3_get_bit(caps, caps_map[i].imp_bit))
179+ set_bit(caps_map[i].local_bit, ae_dev->caps);
180+}
181+
182+int hclge_comm_alloc_cmd_queue(struct hclge_comm_hw *hw, int ring_type)
183+{
184+ struct hclge_comm_cmq_ring *ring =
185+ (ring_type == HCLGE_COMM_TYPE_CSQ) ? &hw->cmq.csq :
186+ &hw->cmq.crq;
187+ int ret;
188+
189+ ring->ring_type = ring_type;
190+
191+ ret = hclge_comm_alloc_cmd_desc(ring);
192+ if (ret)
193+ dev_err(&ring->pdev->dev, "descriptor %s alloc error %d\n",
194+ (ring_type == HCLGE_COMM_TYPE_CSQ) ? "CSQ" : "CRQ",
195+ ret);
196+
197+ return ret;
198+}
199+
200+int hclge_comm_cmd_query_version_and_capability(struct hnae3_ae_dev *ae_dev,
201+ struct hclge_comm_hw *hw,
202+ u32 *fw_version, bool is_pf)
203+{
204+ struct hclge_comm_query_version_cmd *resp;
205+ struct hclge_desc desc;
206+ int ret;
207+
208+ hclge_comm_cmd_setup_basic_desc(&desc, HCLGE_COMM_OPC_QUERY_FW_VER, 1);
209+ resp = (struct hclge_comm_query_version_cmd *)desc.data;
210+ resp->api_caps = hclge_comm_build_api_caps();
211+
212+ ret = hclge_comm_cmd_send(hw, &desc, 1, is_pf);
213+ if (ret)
214+ return ret;
215+
216+ *fw_version = le32_to_cpu(resp->firmware);
217+
218+ ae_dev->dev_version = le32_to_cpu(resp->hardware) <<
219+ HNAE3_PCI_REVISION_BIT_SIZE;
220+ ae_dev->dev_version |= ae_dev->pdev->revision;
221+
222+ if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2)
223+ hclge_comm_set_default_capability(ae_dev, is_pf);
224+
225+ hclge_comm_parse_capability(ae_dev, is_pf, resp);
226+
227+ return ret;
228+}
229+
7230 static bool hclge_is_elem_in_array(const u16 *spec_opcode, u32 size, u16 opcode)
8231 {
9232 u32 i;
drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h+88−1
@@ -7,13 +7,41 @@ · 6 unmodified lines
77
88 #include "hnae3.h"
99
10+#define HCLGE_COMM_CMD_FLAG_IN BIT(0)
11+#define HCLGE_COMM_CMD_FLAG_NEXT BIT(2)
12+#define HCLGE_COMM_CMD_FLAG_WR BIT(3)
1013 #define HCLGE_COMM_CMD_FLAG_NO_INTR BIT(4)
1114
1215 #define HCLGE_COMM_SEND_SYNC(flag) \
1316 ((flag) & HCLGE_COMM_CMD_FLAG_NO_INTR)
1417
18+#define HCLGE_COMM_LINK_EVENT_REPORT_EN_B 0
19+#define HCLGE_COMM_NCSI_ERROR_REPORT_EN_B 1
20+#define HCLGE_COMM_PHY_IMP_EN_B 2
21+#define HCLGE_COMM_MAC_STATS_EXT_EN_B 3
22+#define HCLGE_COMM_SYNC_RX_RING_HEAD_EN_B 4
23+
24+#define hclge_comm_dev_phy_imp_supported(ae_dev) \
25+ test_bit(HNAE3_DEV_SUPPORT_PHY_IMP_B, (ae_dev)->caps)
26+
27+#define HCLGE_COMM_TYPE_CRQ 0
28+#define HCLGE_COMM_TYPE_CSQ 1
29+
30+#define HCLGE_COMM_NIC_CSQ_BASEADDR_L_REG 0x27000
31+#define HCLGE_COMM_NIC_CSQ_BASEADDR_H_REG 0x27004
32+#define HCLGE_COMM_NIC_CSQ_DEPTH_REG 0x27008
1533 #define HCLGE_COMM_NIC_CSQ_TAIL_REG 0x27010
1634 #define HCLGE_COMM_NIC_CSQ_HEAD_REG 0x27014
35+#define HCLGE_COMM_NIC_CRQ_BASEADDR_L_REG 0x27018
36+#define HCLGE_COMM_NIC_CRQ_BASEADDR_H_REG 0x2701C
37+#define HCLGE_COMM_NIC_CRQ_DEPTH_REG 0x27020
38+#define HCLGE_COMM_NIC_CRQ_TAIL_REG 0x27024
39+#define HCLGE_COMM_NIC_CRQ_HEAD_REG 0x27028
40+
41+/* this bit indicates that the driver is ready for hardware reset */
42+#define HCLGE_COMM_NIC_SW_RST_RDY_B 16
43+#define HCLGE_COMM_NIC_SW_RST_RDY BIT(HCLGE_COMM_NIC_SW_RST_RDY_B)
44+#define HCLGE_COMM_NIC_CMQ_DESC_NUM_S 3
1745
1846 enum hclge_comm_cmd_return_status {
1947 HCLGE_COMM_CMD_EXEC_SUCCESS = 0,
@@ -44,6 +72,46 @@ enum hclge_comm_special_cmd { · 24 unmodified lines
4472 HCLGE_COMM_QUERY_ALL_ERR_INFO = 0x1517,
4573 };
4674
75+enum HCLGE_COMM_CAP_BITS {
76+ HCLGE_COMM_CAP_UDP_GSO_B,
77+ HCLGE_COMM_CAP_QB_B,
78+ HCLGE_COMM_CAP_FD_FORWARD_TC_B,
79+ HCLGE_COMM_CAP_PTP_B,
80+ HCLGE_COMM_CAP_INT_QL_B,
81+ HCLGE_COMM_CAP_HW_TX_CSUM_B,
82+ HCLGE_COMM_CAP_TX_PUSH_B,
83+ HCLGE_COMM_CAP_PHY_IMP_B,
84+ HCLGE_COMM_CAP_TQP_TXRX_INDEP_B,
85+ HCLGE_COMM_CAP_HW_PAD_B,
86+ HCLGE_COMM_CAP_STASH_B,
87+ HCLGE_COMM_CAP_UDP_TUNNEL_CSUM_B,
88+ HCLGE_COMM_CAP_RAS_IMP_B = 12,
89+ HCLGE_COMM_CAP_FEC_B = 13,
90+ HCLGE_COMM_CAP_PAUSE_B = 14,
91+ HCLGE_COMM_CAP_RXD_ADV_LAYOUT_B = 15,
92+ HCLGE_COMM_CAP_PORT_VLAN_BYPASS_B = 17,
93+};
94+
95+enum HCLGE_COMM_API_CAP_BITS {
96+ HCLGE_COMM_API_CAP_FLEX_RSS_TBL_B,
97+};
98+
99+enum hclge_comm_opcode_type {
100+ HCLGE_COMM_OPC_QUERY_FW_VER = 0x0001,
101+ HCLGE_COMM_OPC_IMP_COMPAT_CFG = 0x701A,
102+};
103+
104+/* capabilities bits map between imp firmware and local driver */
105+struct hclge_comm_caps_bit_map {
106+ u16 imp_bit;
107+ u16 local_bit;
108+};
109+
110+struct hclge_comm_firmware_compat_cmd {
111+ __le32 compat;
112+ u8 rsv[20];
113+};
114+
47115 enum hclge_comm_cmd_state {
48116 HCLGE_COMM_STATE_CMD_DISABLE,
49117 };
@@ -53,6 +121,14 @@ struct hclge_comm_errcode { · 3 unmodified lines
53121 int common_errno;
54122 };
55123
124+#define HCLGE_COMM_QUERY_CAP_LENGTH 3
125+struct hclge_comm_query_version_cmd {
126+ __le32 firmware;
127+ __le32 hardware;
128+ __le32 api_caps;
129+ __le32 caps[HCLGE_COMM_QUERY_CAP_LENGTH]; /* capabilities of device */
130+};
131+
56132 #define HCLGE_DESC_DATA_LEN 6
57133 struct hclge_desc {
58134 __le16 opcode;
@@ -115,7 +191,18 @@ static inline u32 hclge_comm_read_reg(u8 __iomem *base, u32 reg) · 56 unmodified lines
115191 #define hclge_comm_read_dev(a, reg) \
116192 hclge_comm_read_reg((a)->io_base, reg)
117193
194+void hclge_comm_cmd_init_regs(struct hclge_comm_hw *hw);
195+int hclge_comm_cmd_query_version_and_capability(struct hnae3_ae_dev *ae_dev,
196+ struct hclge_comm_hw *hw,
197+ u32 *fw_version, bool is_pf);
198+int hclge_comm_alloc_cmd_queue(struct hclge_comm_hw *hw, int ring_type);
118199 int hclge_comm_cmd_send(struct hclge_comm_hw *hw, struct hclge_desc *desc,
119200 int num, bool is_pf);
120−
201+void hclge_comm_cmd_reuse_desc(struct hclge_desc *desc, bool is_read);
202+int hclge_comm_firmware_compat_config(struct hnae3_ae_dev *ae_dev, bool is_pf,
203+ struct hclge_comm_hw *hw, bool en);
204+void hclge_comm_free_cmd_desc(struct hclge_comm_cmq_ring *ring);
205+void hclge_comm_cmd_setup_basic_desc(struct hclge_desc *desc,
206+ enum hclge_comm_opcode_type opcode,
207+ bool is_read);
121208 #endif