From rdma.git Jason Gunthorpe says: ==================== This is a collection of general cleanups for ODP to clarify some of the flows around umem creation and use of the interval tree. ==================== The branch is based on v5.3-rc5 due to dependencies, and is being taken into hmm.git due to dependencies in the next patches. * odp_fixes: RDMA/mlx5: Use odp instead of mr->umem in pagefault_mr RDMA/mlx5: Use ib_umem_start instead of umem.address RDMA/core: Make invalidate_range a device operation RDMA/odp: Use kvcalloc for the dma_list and page_list RDMA/odp: Check for overflow when computing the umem_odp end RDMA/odp: Provide ib_umem_odp_release() to undo the allocs RDMA/odp: Split creating a umem_odp from ib_umem_get RDMA/odp: Make the three ways to create a umem_odp clear RMDA/odp: Consolidate umem_odp initialization RDMA/odp: Make it clearer when a umem is an implicit ODP umem RDMA/odp: Iterate over the whole rbtree directly RDMA/odp: Use the common interval tree library instead of generic RDMA/mlx5: Fix MR npages calculation for IB_ACCESS_HUGETLB
Unified · Split
| @@ -142,3 +142,6 @@ x509.genkey · 141 unmodified lines | |||
| 142 | 142 | ||
| 143 | # Kdevelop4 | 143 | # Kdevelop4 |
| 144 | *.kdev4 | 144 | *.kdev4 |
| 145 | |||
| 146 | # Clang's compilation database file | ||
| 147 | /compile_commands.json | ||
| @@ -98,6 +98,7 @@ Jason Gunthorpe <jgg@ziepe.ca> <jgunthorpe@obsidianresearch.com> · 97 unmodified lines | |||
| 98 | Javi Merino <javi.merino@kernel.org> <javi.merino@arm.com> | 98 | Javi Merino <javi.merino@kernel.org> <javi.merino@arm.com> |
| 99 | <javier@osg.samsung.com> <javier.martinez@collabora.co.uk> | 99 | <javier@osg.samsung.com> <javier.martinez@collabora.co.uk> |
| 100 | Jean Tourrilhes <jt@hpl.hp.com> | 100 | Jean Tourrilhes <jt@hpl.hp.com> |
| 101 | <jean-philippe@linaro.org> <jean-philippe.brucker@arm.com> | ||
| 101 | Jeff Garzik <jgarzik@pretzel.yyz.us> | 102 | Jeff Garzik <jgarzik@pretzel.yyz.us> |
| 102 | Jeff Layton <jlayton@kernel.org> <jlayton@redhat.com> | 103 | Jeff Layton <jlayton@kernel.org> <jlayton@redhat.com> |
| 103 | Jeff Layton <jlayton@kernel.org> <jlayton@poochiereds.net> | 104 | Jeff Layton <jlayton@kernel.org> <jlayton@poochiereds.net> |
| @@ -116,6 +117,7 @@ John Stultz <johnstul@us.ibm.com> · 12 unmodified lines | |||
| 116 | Juha Yrjola <at solidboot.com> | 117 | Juha Yrjola <at solidboot.com> |
| 117 | Juha Yrjola <juha.yrjola@nokia.com> | 118 | Juha Yrjola <juha.yrjola@nokia.com> |
| 118 | Juha Yrjola <juha.yrjola@solidboot.com> | 119 | Juha Yrjola <juha.yrjola@solidboot.com> |
| 120 | Julien Thierry <julien.thierry.kdev@gmail.com> <julien.thierry@arm.com> | ||
| 119 | Kay Sievers <kay.sievers@vrfy.org> | 121 | Kay Sievers <kay.sievers@vrfy.org> |
| 120 | Kenneth W Chen <kenneth.w.chen@intel.com> | 122 | Kenneth W Chen <kenneth.w.chen@intel.com> |
| 121 | Konstantin Khlebnikov <koct9i@gmail.com> <k.khlebnikov@samsung.com> | 123 | Konstantin Khlebnikov <koct9i@gmail.com> <k.khlebnikov@samsung.com> |
| @@ -132,6 +134,7 @@ Linus Lüssing <linus.luessing@c0d3.blue> <linus.luessing@ascom.ch> · 10 unmodified lines | |||
| 132 | Li Yang <leoyang.li@nxp.com> <leo@zh-kernel.org> | 134 | Li Yang <leoyang.li@nxp.com> <leo@zh-kernel.org> |
| 133 | Li Yang <leoyang.li@nxp.com> <leoli@freescale.com> | 135 | Li Yang <leoyang.li@nxp.com> <leoli@freescale.com> |
| 134 | Maciej W. Rozycki <macro@mips.com> <macro@imgtec.com> | 136 | Maciej W. Rozycki <macro@mips.com> <macro@imgtec.com> |
| 137 | Marc Zyngier <maz@kernel.org> <marc.zyngier@arm.com> | ||
| 135 | Marcin Nowakowski <marcin.nowakowski@mips.com> <marcin.nowakowski@imgtec.com> | 138 | Marcin Nowakowski <marcin.nowakowski@mips.com> <marcin.nowakowski@imgtec.com> |
| 136 | Mark Brown <broonie@sirena.org.uk> | 139 | Mark Brown <broonie@sirena.org.uk> |
| 137 | Mark Yao <markyao0591@gmail.com> <mark.yao@rock-chips.com> | 140 | Mark Yao <markyao0591@gmail.com> <mark.yao@rock-chips.com> |
| @@ -403,7 +403,7 @@ That is, the recovery API only requires that: · 402 unmodified lines | |||
| 403 | .. note:: | 403 | .. note:: |
| 404 | 404 | ||
| 405 | Implementation details for the powerpc platform are discussed in | 405 | Implementation details for the powerpc platform are discussed in |
| 406 | the file Documentation/powerpc/eeh-pci-error-recovery.txt | 406 | the file Documentation/powerpc/eeh-pci-error-recovery.rst |
| 407 | 407 | ||
| 408 | As of this writing, there is a growing list of device drivers with | 408 | As of this writing, there is a growing list of device drivers with |
| 409 | patches implementing error recovery. Not all of these patches are in | 409 | patches implementing error recovery. Not all of these patches are in |
| @@ -422,3 +422,6 @@ That is, the recovery API only requires that: · 12 unmodified lines | |||
| 422 | - drivers/net/cxgb3 | 422 | - drivers/net/cxgb3 |
| 423 | - drivers/net/s2io.c | 423 | - drivers/net/s2io.c |
| 424 | - drivers/net/qlge | 424 | - drivers/net/qlge |
| 425 | |||
| 426 | The End | ||
| 427 | ------- | ||
| @@ -1,7 +1,7 @@ | |||
| 1 | Using hlist_nulls to protect read-mostly linked lists and | 1 | Using hlist_nulls to protect read-mostly linked lists and |
| 2 | objects using SLAB_TYPESAFE_BY_RCU allocations. | 2 | objects using SLAB_TYPESAFE_BY_RCU allocations. |
| 3 | 3 | ||
| 4 | Please read the basics in Documentation/RCU/listRCU.txt | 4 | Please read the basics in Documentation/RCU/listRCU.rst |
| 5 | 5 | ||
| 6 | Using special makers (called 'nulls') is a convenient way | 6 | Using special makers (called 'nulls') is a convenient way |
| 7 | to solve following problem : | 7 | to solve following problem : |
| @@ -1,10 +0,0 @@ | |||
| 1 | # -*- coding: utf-8; mode: python -*- | ||
| 2 | |||
| 3 | project = 'Linux Kernel User Documentation' | ||
| 4 | |||
| 5 | tags.add("subproject") | ||
| 6 | |||
| 7 | latex_documents = [ | ||
| 8 | ('index', 'linux-user.tex', 'Linux Kernel User Documentation', | ||
| 9 | 'The kernel development community', 'manual'), | ||
| 10 | ] | ||
| @@ -41,10 +41,11 @@ Related CVEs · 40 unmodified lines | |||
| 41 | 41 | ||
| 42 | The following CVE entries describe Spectre variants: | 42 | The following CVE entries describe Spectre variants: |
| 43 | 43 | ||
| 44 | ============= ======================= ================= | 44 | ============= ======================= ========================== |
| 45 | CVE-2017-5753 Bounds check bypass Spectre variant 1 | 45 | CVE-2017-5753 Bounds check bypass Spectre variant 1 |
| 46 | CVE-2017-5715 Branch target injection Spectre variant 2 | 46 | CVE-2017-5715 Branch target injection Spectre variant 2 |
| 47 | ============= ======================= ================= | 47 | CVE-2019-1125 Spectre v1 swapgs Spectre variant 1 (swapgs) |
| 48 | ============= ======================= ========================== | ||
| 48 | 49 | ||
| 49 | Problem | 50 | Problem |
| 50 | ------- | 51 | ------- |
| @@ -78,6 +79,13 @@ There are some extensions of Spectre variant 1 attacks for reading data · 27 unmodified lines | |||
| 78 | over the network, see :ref:`[12] <spec_ref12>`. However such attacks | 79 | over the network, see :ref:`[12] <spec_ref12>`. However such attacks |
| 79 | are difficult, low bandwidth, fragile, and are considered low risk. | 80 | are difficult, low bandwidth, fragile, and are considered low risk. |
| 80 | 81 | ||
| 82 | Note that, despite "Bounds Check Bypass" name, Spectre variant 1 is not | ||
| 83 | only about user-controlled array bounds checks. It can affect any | ||
| 84 | conditional checks. The kernel entry code interrupt, exception, and NMI | ||
| 85 | handlers all have conditional swapgs checks. Those may be problematic | ||
| 86 | in the context of Spectre v1, as kernel code can speculatively run with | ||
| 87 | a user GS. | ||
| 88 | |||
| 81 | Spectre variant 2 (Branch Target Injection) | 89 | Spectre variant 2 (Branch Target Injection) |
| 82 | ------------------------------------------- | 90 | ------------------------------------------- |
| 83 | 91 | ||
| @@ -132,6 +140,9 @@ not cover all possible attack vectors. · 48 unmodified lines | |||
| 132 | 1. A user process attacking the kernel | 140 | 1. A user process attacking the kernel |
| 133 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ | 141 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
| 134 | 142 | ||
| 143 | Spectre variant 1 | ||
| 144 | ~~~~~~~~~~~~~~~~~ | ||
| 145 | |||
| 135 | The attacker passes a parameter to the kernel via a register or | 146 | The attacker passes a parameter to the kernel via a register or |
| 136 | via a known address in memory during a syscall. Such parameter may | 147 | via a known address in memory during a syscall. Such parameter may |
| 137 | be used later by the kernel as an index to an array or to derive | 148 | be used later by the kernel as an index to an array or to derive |
| @@ -144,7 +155,40 @@ not cover all possible attack vectors. · 6 unmodified lines | |||
| 144 | potentially be influenced for Spectre attacks, new "nospec" accessor | 155 | potentially be influenced for Spectre attacks, new "nospec" accessor |
| 145 | macros are used to prevent speculative loading of data. | 156 | macros are used to prevent speculative loading of data. |
| 146 | 157 | ||
| 147 | Spectre variant 2 attacker can :ref:`poison <poison_btb>` the branch | 158 | Spectre variant 1 (swapgs) |
| 159 | ~~~~~~~~~~~~~~~~~~~~~~~~~~ | ||
| 160 | |||
| 161 | An attacker can train the branch predictor to speculatively skip the | ||
| 162 | swapgs path for an interrupt or exception. If they initialize | ||
| 163 | the GS register to a user-space value, if the swapgs is speculatively | ||
| 164 | skipped, subsequent GS-related percpu accesses in the speculation | ||
| 165 | window will be done with the attacker-controlled GS value. This | ||
| 166 | could cause privileged memory to be accessed and leaked. | ||
| 167 | |||
| 168 | For example: | ||
| 169 | |||
| 170 | :: | ||
| 171 | |||
| 172 | if (coming from user space) | ||
| 173 | swapgs | ||
| 174 | mov %gs:<percpu_offset>, %reg | ||
| 175 | mov (%reg), %reg1 | ||
| 176 | |||
| 177 | When coming from user space, the CPU can speculatively skip the | ||
| 178 | swapgs, and then do a speculative percpu load using the user GS | ||
| 179 | value. So the user can speculatively force a read of any kernel | ||
| 180 | value. If a gadget exists which uses the percpu value as an address | ||
| 181 | in another load/store, then the contents of the kernel value may | ||
| 182 | become visible via an L1 side channel attack. | ||
| 183 | |||
| 184 | A similar attack exists when coming from kernel space. The CPU can | ||
| 185 | speculatively do the swapgs, causing the user GS to get used for the | ||
| 186 | rest of the speculative window. | ||
| 187 | |||
| 188 | Spectre variant 2 | ||
| 189 | ~~~~~~~~~~~~~~~~~ | ||
| 190 | |||
| 191 | A spectre variant 2 attacker can :ref:`poison <poison_btb>` the branch | ||
| 148 | target buffer (BTB) before issuing syscall to launch an attack. | 192 | target buffer (BTB) before issuing syscall to launch an attack. |
| 149 | After entering the kernel, the kernel could use the poisoned branch | 193 | After entering the kernel, the kernel could use the poisoned branch |
| 150 | target buffer on indirect jump and jump to gadget code in speculative | 194 | target buffer on indirect jump and jump to gadget code in speculative |
| @@ -280,11 +324,18 @@ The sysfs file showing Spectre variant 1 mitigation status is: · 129 unmodified lines | |||
| 280 | 324 | ||
| 281 | The possible values in this file are: | 325 | The possible values in this file are: |
| 282 | 326 | ||
| 283 | ======================================= ================================= | 327 | .. list-table:: |
| 284 | 'Mitigation: __user pointer sanitation' Protection in kernel on a case by | 328 | |
| 285 | case base with explicit pointer | 329 | * - 'Not affected' |
| 286 | sanitation. | 330 | - The processor is not vulnerable. |
| 287 | ======================================= ================================= | 331 | * - 'Vulnerable: __user pointer sanitization and usercopy barriers only; no swapgs barriers' |
| 332 | - The swapgs protections are disabled; otherwise it has | ||
| 333 | protection in the kernel on a case by case base with explicit | ||
| 334 | pointer sanitation and usercopy LFENCE barriers. | ||
| 335 | * - 'Mitigation: usercopy/swapgs barriers and __user pointer sanitization' | ||
| 336 | - Protection in the kernel on a case by case base with explicit | ||
| 337 | pointer sanitation, usercopy LFENCE barriers, and swapgs LFENCE | ||
| 338 | barriers. | ||
| 288 | 339 | ||
| 289 | However, the protections are put in place on a case by case basis, | 340 | However, the protections are put in place on a case by case basis, |
| 290 | and there is no guarantee that all possible attack vectors for Spectre | 341 | and there is no guarantee that all possible attack vectors for Spectre |
| @@ -366,12 +417,27 @@ Turning on mitigation for Spectre variant 1 and Spectre variant 2 · 75 unmodified lines | |||
| 366 | 1. Kernel mitigation | 417 | 1. Kernel mitigation |
| 367 | ^^^^^^^^^^^^^^^^^^^^ | 418 | ^^^^^^^^^^^^^^^^^^^^ |
| 368 | 419 | ||
| 420 | Spectre variant 1 | ||
| 421 | ~~~~~~~~~~~~~~~~~ | ||
| 422 | |||
| 369 | For the Spectre variant 1, vulnerable kernel code (as determined | 423 | For the Spectre variant 1, vulnerable kernel code (as determined |
| 370 | by code audit or scanning tools) is annotated on a case by case | 424 | by code audit or scanning tools) is annotated on a case by case |
| 371 | basis to use nospec accessor macros for bounds clipping :ref:`[2] | 425 | basis to use nospec accessor macros for bounds clipping :ref:`[2] |
| 372 | <spec_ref2>` to avoid any usable disclosure gadgets. However, it may | 426 | <spec_ref2>` to avoid any usable disclosure gadgets. However, it may |
| 373 | not cover all attack vectors for Spectre variant 1. | 427 | not cover all attack vectors for Spectre variant 1. |
| 374 | 428 | ||
| 429 | Copy-from-user code has an LFENCE barrier to prevent the access_ok() | ||
| 430 | check from being mis-speculated. The barrier is done by the | ||
| 431 | barrier_nospec() macro. | ||
| 432 | |||
| 433 | For the swapgs variant of Spectre variant 1, LFENCE barriers are | ||
| 434 | added to interrupt, exception and NMI entry where needed. These | ||
| 435 | barriers are done by the FENCE_SWAPGS_KERNEL_ENTRY and | ||
| 436 | FENCE_SWAPGS_USER_ENTRY macros. | ||
| 437 | |||
| 438 | Spectre variant 2 | ||
| 439 | ~~~~~~~~~~~~~~~~~ | ||
| 440 | |||
| 375 | For Spectre variant 2 mitigation, the compiler turns indirect calls or | 441 | For Spectre variant 2 mitigation, the compiler turns indirect calls or |
| 376 | jumps in the kernel into equivalent return trampolines (retpolines) | 442 | jumps in the kernel into equivalent return trampolines (retpolines) |
| 377 | :ref:`[3] <spec_ref3>` :ref:`[9] <spec_ref9>` to go to the target | 443 | :ref:`[3] <spec_ref3>` :ref:`[9] <spec_ref9>` to go to the target |
| @@ -473,6 +539,12 @@ Mitigation control on the kernel command line · 95 unmodified lines | |||
| 473 | Spectre variant 2 mitigation can be disabled or force enabled at the | 539 | Spectre variant 2 mitigation can be disabled or force enabled at the |
| 474 | kernel command line. | 540 | kernel command line. |
| 475 | 541 | ||
| 542 | nospectre_v1 | ||
| 543 | |||
| 544 | [X86,PPC] Disable mitigations for Spectre Variant 1 | ||
| 545 | (bounds check bypass). With this option data leaks are | ||
| 546 | possible in the system. | ||
| 547 | |||
| 476 | nospectre_v2 | 548 | nospectre_v2 |
| 477 | 549 | ||
| 478 | [X86] Disable all mitigations for the Spectre variant 2 | 550 | [X86] Disable all mitigations for the Spectre variant 2 |
| @@ -2545,7 +2545,7 @@ · 2544 unmodified lines | |||
| 2545 | mem_encrypt=on: Activate SME | 2545 | mem_encrypt=on: Activate SME |
| 2546 | mem_encrypt=off: Do not activate SME | 2546 | mem_encrypt=off: Do not activate SME |
| 2547 | 2547 | ||
| 2548 | Refer to Documentation/virtual/kvm/amd-memory-encryption.rst | 2548 | Refer to Documentation/virt/kvm/amd-memory-encryption.rst |
| 2549 | for details on when memory encryption can be activated. | 2549 | for details on when memory encryption can be activated. |
| 2550 | 2550 | ||
| 2551 | mem_sleep_default= [SUSPEND] Default system suspend mode: | 2551 | mem_sleep_default= [SUSPEND] Default system suspend mode: |
| @@ -2604,7 +2604,7 @@ · 52 unmodified lines | |||
| 2604 | expose users to several CPU vulnerabilities. | 2604 | expose users to several CPU vulnerabilities. |
| 2605 | Equivalent to: nopti [X86,PPC] | 2605 | Equivalent to: nopti [X86,PPC] |
| 2606 | kpti=0 [ARM64] | 2606 | kpti=0 [ARM64] |
| 2607 | nospectre_v1 [PPC] | 2607 | nospectre_v1 [X86,PPC] |
| 2608 | nobp=0 [S390] | 2608 | nobp=0 [S390] |
| 2609 | nospectre_v2 [X86,PPC,S390,ARM64] | 2609 | nospectre_v2 [X86,PPC,S390,ARM64] |
| 2610 | spectre_v2_user=off [X86] | 2610 | spectre_v2_user=off [X86] |
| @@ -2965,9 +2965,9 @@ · 354 unmodified lines | |||
| 2965 | nosmt=force: Force disable SMT, cannot be undone | 2965 | nosmt=force: Force disable SMT, cannot be undone |
| 2966 | via the sysfs control file. | 2966 | via the sysfs control file. |
| 2967 | 2967 | ||
| 2968 | nospectre_v1 [PPC] Disable mitigations for Spectre Variant 1 (bounds | 2968 | nospectre_v1 [X86,PPC] Disable mitigations for Spectre Variant 1 |
| 2969 | check bypass). With this option data leaks are possible | 2969 | (bounds check bypass). With this option data leaks are |
| 2970 | in the system. | 2970 | possible in the system. |
| 2971 | 2971 | ||
| 2972 | nospectre_v2 [X86,PPC_FSL_BOOK3E,ARM64] Disable all mitigations for | 2972 | nospectre_v2 [X86,PPC_FSL_BOOK3E,ARM64] Disable all mitigations for |
| 2973 | the Spectre variant 2 (indirect branch prediction) | 2973 | the Spectre variant 2 (indirect branch prediction) |
| @@ -53,7 +53,7 @@ disabled, there is ``khugepaged`` daemon that scans memory and · 52 unmodified lines | |||
| 53 | collapses sequences of basic pages into huge pages. | 53 | collapses sequences of basic pages into huge pages. |
| 54 | 54 | ||
| 55 | The THP behaviour is controlled via :ref:`sysfs <thp_sysfs>` | 55 | The THP behaviour is controlled via :ref:`sysfs <thp_sysfs>` |
| 56 | interface and using madivse(2) and prctl(2) system calls. | 56 | interface and using madvise(2) and prctl(2) system calls. |
| 57 | 57 | ||
| 58 | Transparent Hugepage Support maximizes the usefulness of free memory | 58 | Transparent Hugepage Support maximizes the usefulness of free memory |
| 59 | if compared to the reservation approach of hugetlbfs by allowing all | 59 | if compared to the reservation approach of hugetlbfs by allowing all |
| @@ -16,6 +16,8 @@ import sys · 15 unmodified lines | |||
| 16 | import os | 16 | import os |
| 17 | import sphinx | 17 | import sphinx |
| 18 | 18 | ||
| 19 | from subprocess import check_output | ||
| 20 | |||
| 19 | # Get Sphinx version | 21 | # Get Sphinx version |
| 20 | major, minor, patch = sphinx.version_info[:3] | 22 | major, minor, patch = sphinx.version_info[:3] |
| 21 | 23 | ||
| @@ -276,10 +278,21 @@ latex_elements = { · 254 unmodified lines | |||
| 276 | \\setsansfont{DejaVu Sans} | 278 | \\setsansfont{DejaVu Sans} |
| 277 | \\setromanfont{DejaVu Serif} | 279 | \\setromanfont{DejaVu Serif} |
| 278 | \\setmonofont{DejaVu Sans Mono} | 280 | \\setmonofont{DejaVu Sans Mono} |
| 279 | |||
| 280 | ''' | 281 | ''' |
| 281 | } | 282 | } |
| 282 | 283 | ||
| 284 | # At least one book (translations) may have Asian characters | ||
| 285 | # with are only displayed if xeCJK is used | ||
| 286 | |||
| 287 | cjk_cmd = check_output(['fc-list', '--format="%{family[0]}\n"']).decode('utf-8', 'ignore') | ||
| 288 | if cjk_cmd.find("Noto Sans CJK SC") >= 0: | ||
| 289 | print ("enabling CJK for LaTeX builder") | ||
| 290 | latex_elements['preamble'] += ''' | ||
| 291 | % This is needed for translations | ||
| 292 | \\usepackage{xeCJK} | ||
| 293 | \\setCJKmainfont{Noto Sans CJK SC} | ||
| 294 | ''' | ||
| 295 | |||
| 283 | # Fix reference escape troubles with Sphinx 1.4.x | 296 | # Fix reference escape troubles with Sphinx 1.4.x |
| 284 | if major == 1 and minor > 3: | 297 | if major == 1 and minor > 3: |
| 285 | latex_elements['preamble'] += '\\renewcommand*{\\DUrole}[2]{ #2 }\n' | 298 | latex_elements['preamble'] += '\\renewcommand*{\\DUrole}[2]{ #2 }\n' |
| @@ -410,6 +423,21 @@ latex_documents = [ · 124 unmodified lines | |||
| 410 | 'The kernel development community', 'manual'), | 423 | 'The kernel development community', 'manual'), |
| 411 | ] | 424 | ] |
| 412 | 425 | ||
| 426 | # Add all other index files from Documentation/ subdirectories | ||
| 427 | for fn in os.listdir('.'): | ||
| 428 | doc = os.path.join(fn, "index") | ||
| 429 | if os.path.exists(doc + ".rst"): | ||
| 430 | has = False | ||
| 431 | for l in latex_documents: | ||
| 432 | if l[0] == doc: | ||
| 433 | has = True | ||
| 434 | break | ||
| 435 | if not has: | ||
| 436 | latex_documents.append((doc, fn + '.tex', | ||
| 437 | 'Linux %s Documentation' % fn.capitalize(), | ||
| 438 | 'The kernel development community', | ||
| 439 | 'manual')) | ||
| 440 | |||
| 413 | # The name of an image file (relative to this directory) to place at the top of | 441 | # The name of an image file (relative to this directory) to place at the top of |
| 414 | # the title page. | 442 | # the title page. |
| 415 | #latex_logo = None | 443 | #latex_logo = None |
| @@ -1,10 +0,0 @@ | |||
| 1 | # -*- coding: utf-8; mode: python -*- | ||
| 2 | |||
| 3 | project = "Core-API Documentation" | ||
| 4 | |||
| 5 | tags.add("subproject") | ||
| 6 | |||
| 7 | latex_documents = [ | ||
| 8 | ('index', 'core-api.tex', project, | ||
| 9 | 'The kernel development community', 'manual'), | ||
| 10 | ] | ||
| @@ -1,10 +0,0 @@ | |||
| 1 | # -*- coding: utf-8; mode: python -*- | ||
| 2 | |||
| 3 | project = 'Linux Kernel Crypto API' | ||
| 4 | |||
| 5 | tags.add("subproject") | ||
| 6 | |||
| 7 | latex_documents = [ | ||
| 8 | ('index', 'crypto-api.tex', 'Linux Kernel Crypto API manual', | ||
| 9 | 'The kernel development community', 'manual'), | ||
| 10 | ] | ||
| @@ -1,10 +0,0 @@ | |||
| 1 | # -*- coding: utf-8; mode: python -*- | ||
| 2 | |||
| 3 | project = "Development tools for the kernel" | ||
| 4 | |||
| 5 | tags.add("subproject") | ||
| 6 | |||
| 7 | latex_documents = [ | ||
| 8 | ('index', 'dev-tools.tex', project, | ||
| 9 | 'The kernel development community', 'manual'), | ||
| 10 | ] | ||
| @@ -19,7 +19,9 @@ quiet_cmd_mk_schema = SCHEMA $@ · 18 unmodified lines | |||
| 19 | 19 | ||
| 20 | DT_DOCS = $(shell \ | 20 | DT_DOCS = $(shell \ |
| 21 | cd $(srctree)/$(src) && \ | 21 | cd $(srctree)/$(src) && \ |
| 22 | find * \( -name '*.yaml' ! -name $(DT_TMP_SCHEMA) \) \ | 22 | find * \( -name '*.yaml' ! \ |
| 23 | -name $(DT_TMP_SCHEMA) ! \ | ||
| 24 | -name '*.example.dt.yaml' \) \ | ||
| 23 | ) | 25 | ) |
| 24 | 26 | ||
| 25 | DT_SCHEMA_FILES ?= $(addprefix $(src)/,$(DT_DOCS)) | 27 | DT_SCHEMA_FILES ?= $(addprefix $(src)/,$(DT_DOCS)) |
| @@ -703,4 +703,4 @@ cpus { · 702 unmodified lines | |||
| 703 | https://www.devicetree.org/specifications/ | 703 | https://www.devicetree.org/specifications/ |
| 704 | 704 | ||
| 705 | [6] ARM Linux Kernel documentation - Booting AArch64 Linux | 705 | [6] ARM Linux Kernel documentation - Booting AArch64 Linux |
| 706 | Documentation/arm64/booting.txt | 706 | Documentation/arm64/booting.rst |
| @@ -1,7 +1,7 @@ | |||
| 1 | # SPDX-License-Identifier: GPL-2.0 | 1 | # SPDX-License-Identifier: GPL-2.0 |
| 2 | %YAML 1.2 | 2 | %YAML 1.2 |
| 3 | --- | 3 | --- |
| 4 | $id: http://devicetree.org/schemas/arm/shmobile.yaml# | 4 | $id: http://devicetree.org/schemas/arm/renesas.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | 6 | ||
| 7 | title: Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings | 7 | title: Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings |
| @@ -1,7 +1,7 @@ | |||
| 1 | # SPDX-License-Identifier: GPL-2.0 | 1 | # SPDX-License-Identifier: GPL-2.0 |
| 2 | %YAML 1.2 | 2 | %YAML 1.2 |
| 3 | --- | 3 | --- |
| 4 | $id: http://devicetree.org/schemas/arm/milbeaut.yaml# | 4 | $id: http://devicetree.org/schemas/arm/socionext/milbeaut.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | 6 | ||
| 7 | title: Milbeaut platforms device tree bindings | 7 | title: Milbeaut platforms device tree bindings |
| @@ -1,7 +1,7 @@ | |||
| 1 | # SPDX-License-Identifier: GPL-2.0 | 1 | # SPDX-License-Identifier: GPL-2.0 |
| 2 | %YAML 1.2 | 2 | %YAML 1.2 |
| 3 | --- | 3 | --- |
| 4 | $id: http://devicetree.org/schemas/arm/ti/davinci.yaml# | 4 | $id: http://devicetree.org/schemas/arm/ti/ti,davinci.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | 6 | ||
| 7 | title: Texas Instruments DaVinci Platforms Device Tree Bindings | 7 | title: Texas Instruments DaVinci Platforms Device Tree Bindings |
| @@ -1,7 +1,7 @@ | |||
| 1 | # SPDX-License-Identifier: GPL-2.0 | 1 | # SPDX-License-Identifier: GPL-2.0 |
| 2 | %YAML 1.2 | 2 | %YAML 1.2 |
| 3 | --- | 3 | --- |
| 4 | $id: http://devicetree.org/schemas/phy/allwinner,sun4i-a10-ccu.yaml# | 4 | $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-ccu.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | 6 | ||
| 7 | title: Allwinner Clock Control Unit Device Tree Bindings | 7 | title: Allwinner Clock Control Unit Device Tree Bindings |
| @@ -2,7 +2,7 @@ · 1 unmodified line | |||
| 2 | # Copyright 2019 Linaro Ltd. | 2 | # Copyright 2019 Linaro Ltd. |
| 3 | %YAML 1.2 | 3 | %YAML 1.2 |
| 4 | --- | 4 | --- |
| 5 | $id: "http://devicetree.org/schemas/firmware/intel-ixp4xx-network-processing-engine.yaml#" | 5 | $id: "http://devicetree.org/schemas/firmware/intel,ixp4xx-network-processing-engine.yaml#" |
| 6 | $schema: "http://devicetree.org/meta-schemas/core.yaml#" | 6 | $schema: "http://devicetree.org/meta-schemas/core.yaml#" |
| 7 | 7 | ||
| 8 | title: Intel IXP4xx Network Processing Engine | 8 | title: Intel IXP4xx Network Processing Engine |
| @@ -1,7 +1,7 @@ | |||
| 1 | # SPDX-License-Identifier: GPL-2.0 | 1 | # SPDX-License-Identifier: GPL-2.0 |
| 2 | %YAML 1.2 | 2 | %YAML 1.2 |
| 3 | --- | 3 | --- |
| 4 | $id: http://devicetree.org/schemas/iio/accelerometers/adi,adxl345.yaml# | 4 | $id: http://devicetree.org/schemas/iio/accel/adi,adxl345.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | 6 | ||
| 7 | title: Analog Devices ADXL345/ADXL375 3-Axis Digital Accelerometers | 7 | title: Analog Devices ADXL345/ADXL375 3-Axis Digital Accelerometers |
| @@ -1,7 +1,7 @@ | |||
| 1 | # SPDX-License-Identifier: GPL-2.0 | 1 | # SPDX-License-Identifier: GPL-2.0 |
| 2 | %YAML 1.2 | 2 | %YAML 1.2 |
| 3 | --- | 3 | --- |
| 4 | $id: http://devicetree.org/schemas/iio/accelerometers/adi,adxl372.yaml# | 4 | $id: http://devicetree.org/schemas/iio/accel/adi,adxl372.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | 6 | ||
| 7 | title: Analog Devices ADXL372 3-Axis, +/-(200g) Digital Accelerometer | 7 | title: Analog Devices ADXL372 3-Axis, +/-(200g) Digital Accelerometer |
| @@ -5,21 +5,19 @@ Required properties: · 4 unmodified lines | |||
| 5 | - compatible: should be "amazon,al-fic" | 5 | - compatible: should be "amazon,al-fic" |
| 6 | - reg: physical base address and size of the registers | 6 | - reg: physical base address and size of the registers |
| 7 | - interrupt-controller: identifies the node as an interrupt controller | 7 | - interrupt-controller: identifies the node as an interrupt controller |
| 8 | - #interrupt-cells: must be 2. | 8 | - #interrupt-cells : must be 2. Specifies the number of cells needed to encode |
| 9 | First cell defines the index of the interrupt within the controller. | 9 | an interrupt source. Supported trigger types are low-to-high edge |
| 10 | Second cell is used to specify the trigger type and must be one of the | 10 | triggered and active high level-sensitive. |
| 11 | following: | ||
| 12 | - bits[3:0] trigger type and level flags | ||
| 13 | 1 = low-to-high edge triggered | ||
| 14 | 4 = active high level-sensitive | ||
| 15 | - interrupt-parent: specifies the parent interrupt controller. | ||
| 16 | - interrupts: describes which input line in the interrupt parent, this | 11 | - interrupts: describes which input line in the interrupt parent, this |
| 17 | fic's output is connected to. This field property depends on the parent's | 12 | fic's output is connected to. This field property depends on the parent's |
| 18 | binding | 13 | binding |
| 19 | 14 | ||
| 15 | Please refer to interrupts.txt in this directory for details of the common | ||
| 16 | Interrupt Controllers bindings used by client devices. | ||
| 17 | |||
| 20 | Example: | 18 | Example: |
| 21 | 19 | ||
| 22 | amazon_fic: interrupt-controller@0xfd8a8500 { | 20 | amazon_fic: interrupt-controller@fd8a8500 { |
| 23 | compatible = "amazon,al-fic"; | 21 | compatible = "amazon,al-fic"; |
| 24 | interrupt-controller; | 22 | interrupt-controller; |
| 25 | #interrupt-cells = <2>; | 23 | #interrupt-cells = <2>; |
| @@ -2,7 +2,7 @@ · 1 unmodified line | |||
| 2 | # Copyright 2018 Linaro Ltd. | 2 | # Copyright 2018 Linaro Ltd. |
| 3 | %YAML 1.2 | 3 | %YAML 1.2 |
| 4 | --- | 4 | --- |
| 5 | $id: "http://devicetree.org/schemas/interrupt/intel-ixp4xx-interrupt.yaml#" | 5 | $id: "http://devicetree.org/schemas/interrupt-controller/intel,ixp4xx-interrupt.yaml#" |
| 6 | $schema: "http://devicetree.org/meta-schemas/core.yaml#" | 6 | $schema: "http://devicetree.org/meta-schemas/core.yaml#" |
| 7 | 7 | ||
| 8 | title: Intel IXP4xx XScale Networking Processors Interrupt Controller | 8 | title: Intel IXP4xx XScale Networking Processors Interrupt Controller |
| @@ -2,7 +2,7 @@ · 1 unmodified line | |||
| 2 | # Copyright 2019 Linaro Ltd. | 2 | # Copyright 2019 Linaro Ltd. |
| 3 | %YAML 1.2 | 3 | %YAML 1.2 |
| 4 | --- | 4 | --- |
| 5 | $id: "http://devicetree.org/schemas/misc/intel-ixp4xx-ahb-queue-manager.yaml#" | 5 | $id: "http://devicetree.org/schemas/misc/intel,ixp4xx-ahb-queue-manager.yaml#" |
| 6 | $schema: "http://devicetree.org/meta-schemas/core.yaml#" | 6 | $schema: "http://devicetree.org/meta-schemas/core.yaml#" |
| 7 | 7 | ||
| 8 | title: Intel IXP4xx AHB Queue Manager | 8 | title: Intel IXP4xx AHB Queue Manager |
| @@ -1,7 +1,7 @@ | |||
| 1 | # SPDX-License-Identifier: GPL-2.0 | 1 | # SPDX-License-Identifier: GPL-2.0 |
| 2 | %YAML 1.2 | 2 | %YAML 1.2 |
| 3 | --- | 3 | --- |
| 4 | $id: http://devicetree.org/schemas/net/allwinner,sun8i-a83t-gmac.yaml# | 4 | $id: http://devicetree.org/schemas/net/allwinner,sun8i-a83t-emac.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | 6 | ||
| 7 | title: Allwinner A83t EMAC Device Tree Bindings | 7 | title: Allwinner A83t EMAC Device Tree Bindings |
| @@ -7,18 +7,6 @@ Required properties: · 6 unmodified lines | |||
| 7 | - phy-mode : See ethernet.txt file in the same directory | 7 | - phy-mode : See ethernet.txt file in the same directory |
| 8 | 8 | ||
| 9 | Optional properties: | 9 | Optional properties: |
| 10 | - phy-reset-gpios : Should specify the gpio for phy reset | ||
| 11 | - phy-reset-duration : Reset duration in milliseconds. Should present | ||
| 12 | only if property "phy-reset-gpios" is available. Missing the property | ||
| 13 | will have the duration be 1 millisecond. Numbers greater than 1000 are | ||
| 14 | invalid and 1 millisecond will be used instead. | ||
| 15 | - phy-reset-active-high : If present then the reset sequence using the GPIO | ||
| 16 | specified in the "phy-reset-gpios" property is reversed (H=reset state, | ||
| 17 | L=operation state). | ||
| 18 | - phy-reset-post-delay : Post reset delay in milliseconds. If present then | ||
| 19 | a delay of phy-reset-post-delay milliseconds will be observed after the | ||
| 20 | phy-reset-gpios has been toggled. Can be omitted thus no delay is | ||
| 21 | observed. Delay is in range of 1ms to 1000ms. Other delays are invalid. | ||
| 22 | - phy-supply : regulator that powers the Ethernet PHY. | 10 | - phy-supply : regulator that powers the Ethernet PHY. |
| 23 | - phy-handle : phandle to the PHY device connected to this device. | 11 | - phy-handle : phandle to the PHY device connected to this device. |
| 24 | - fixed-link : Assume a fixed link. See fixed-link.txt in the same directory. | 12 | - fixed-link : Assume a fixed link. See fixed-link.txt in the same directory. |
| @@ -47,11 +35,27 @@ Optional properties: · 22 unmodified lines | |||
| 47 | For imx6sx, "int0" handles all 3 queues and ENET_MII. "pps" is for the pulse | 35 | For imx6sx, "int0" handles all 3 queues and ENET_MII. "pps" is for the pulse |
| 48 | per second interrupt associated with 1588 precision time protocol(PTP). | 36 | per second interrupt associated with 1588 precision time protocol(PTP). |
| 49 | 37 | ||
| 50 | |||
| 51 | Optional subnodes: | 38 | Optional subnodes: |
| 52 | - mdio : specifies the mdio bus in the FEC, used as a container for phy nodes | 39 | - mdio : specifies the mdio bus in the FEC, used as a container for phy nodes |
| 53 | according to phy.txt in the same directory | 40 | according to phy.txt in the same directory |
| 54 | 41 | ||
| 42 | Deprecated optional properties: | ||
| 43 | To avoid these, create a phy node according to phy.txt in the same | ||
| 44 | directory, and point the fec's "phy-handle" property to it. Then use | ||
| 45 | the phy's reset binding, again described by phy.txt. | ||
| 46 | - phy-reset-gpios : Should specify the gpio for phy reset | ||
| 47 | - phy-reset-duration : Reset duration in milliseconds. Should present | ||
| 48 | only if property "phy-reset-gpios" is available. Missing the property | ||
| 49 | will have the duration be 1 millisecond. Numbers greater than 1000 are | ||
| 50 | invalid and 1 millisecond will be used instead. | ||
| 51 | - phy-reset-active-high : If present then the reset sequence using the GPIO | ||
| 52 | specified in the "phy-reset-gpios" property is reversed (H=reset state, | ||
| 53 | L=operation state). | ||
| 54 | - phy-reset-post-delay : Post reset delay in milliseconds. If present then | ||
| 55 | a delay of phy-reset-post-delay milliseconds will be observed after the | ||
| 56 | phy-reset-gpios has been toggled. Can be omitted thus no delay is | ||
| 57 | observed. Delay is in range of 1ms to 1000ms. Other delays are invalid. | ||
| 58 | |||
| 55 | Example: | 59 | Example: |
| 56 | 60 | ||
| 57 | ethernet@83fec000 { | 61 | ethernet@83fec000 { |
| @@ -37,13 +37,13 @@ required: · 36 unmodified lines | |||
| 37 | 37 | ||
| 38 | examples: | 38 | examples: |
| 39 | - | | 39 | - | |
| 40 | sid@1c23800 { | 40 | efuse@1c23800 { |
| 41 | compatible = "allwinner,sun4i-a10-sid"; | 41 | compatible = "allwinner,sun4i-a10-sid"; |
| 42 | reg = <0x01c23800 0x10>; | 42 | reg = <0x01c23800 0x10>; |
| 43 | }; | 43 | }; |
| 44 | 44 | ||
| 45 | - | | 45 | - | |
| 46 | sid@1c23800 { | 46 | efuse@1c23800 { |
| 47 | compatible = "allwinner,sun7i-a20-sid"; | 47 | compatible = "allwinner,sun7i-a20-sid"; |
| 48 | reg = <0x01c23800 0x200>; | 48 | reg = <0x01c23800 0x200>; |
| 49 | }; | 49 | }; |
| @@ -0,0 +1,45 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/nvmem/nvmem-consumer.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: NVMEM (Non Volatile Memory) Consumer Device Tree Bindings | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> | ||
| 11 | |||
| 12 | select: true | ||
| 13 | |||
| 14 | properties: | ||
| 15 | nvmem: | ||
| 16 | $ref: /schemas/types.yaml#/definitions/phandle-array | ||
| 17 | description: | ||
| 18 | List of phandle to the nvmem providers. | ||
| 19 | |||
| 20 | nvmem-cells: | ||
| 21 | $ref: /schemas/types.yaml#/definitions/phandle-array | ||
| 22 | description: | ||
| 23 | List of phandle to the nvmem data cells. | ||
| 24 | |||
| 25 | nvmem-names: | ||
| 26 | $ref: /schemas/types.yaml#/definitions/string-array | ||
| 27 | description: | ||
| 28 | Names for the each nvmem provider. | ||
| 29 | |||
| 30 | nvmem-cell-names: | ||
| 31 | $ref: /schemas/types.yaml#/definitions/string-array | ||
| 32 | description: | ||
| 33 | Names for each nvmem-cells specified. | ||
| 34 | |||
| 35 | dependencies: | ||
| 36 | nvmem-names: [ nvmem ] | ||
| 37 | nvmem-cell-names: [ nvmem-cells ] | ||
| 38 | |||
| 39 | examples: | ||
| 40 | - | | ||
| 41 | tsens { | ||
| 42 | /* ... */ | ||
| 43 | nvmem-cells = <&tsens_calibration>; | ||
| 44 | nvmem-cell-names = "calibration"; | ||
| 45 | }; | ||
| @@ -1,80 +1 @@ | |||
| 1 | = NVMEM(Non Volatile Memory) Data Device Tree Bindings = | 1 | This file has been moved to nvmem.yaml and nvmem-consumer.yaml. |
| 2 | |||
| 3 | This binding is intended to represent the location of hardware | ||
| 4 | configuration data stored in NVMEMs like eeprom, efuses and so on. | ||
| 5 | |||
| 6 | On a significant proportion of boards, the manufacturer has stored | ||
| 7 | some data on NVMEM, for the OS to be able to retrieve these information | ||
| 8 | and act upon it. Obviously, the OS has to know about where to retrieve | ||
| 9 | these data from, and where they are stored on the storage device. | ||
| 10 | |||
| 11 | This document is here to document this. | ||
| 12 | |||
| 13 | = Data providers = | ||
| 14 | Contains bindings specific to provider drivers and data cells as children | ||
| 15 | of this node. | ||
| 16 | |||
| 17 | Optional properties: | ||
| 18 | read-only: Mark the provider as read only. | ||
| 19 | |||
| 20 | = Data cells = | ||
| 21 | These are the child nodes of the provider which contain data cell | ||
| 22 | information like offset and size in nvmem provider. | ||
| 23 | |||
| 24 | Required properties: | ||
| 25 | reg: specifies the offset in byte within the storage device. | ||
| 26 | |||
| 27 | Optional properties: | ||
| 28 | |||
| 29 | bits: Is pair of bit location and number of bits, which specifies offset | ||
| 30 | in bit and number of bits within the address range specified by reg property. | ||
| 31 | Offset takes values from 0-7. | ||
| 32 | |||
| 33 | For example: | ||
| 34 | |||
| 35 | /* Provider */ | ||
| 36 | qfprom: qfprom@700000 { | ||
| 37 | ... | ||
| 38 | |||
| 39 | /* Data cells */ | ||
| 40 | tsens_calibration: calib@404 { | ||
| 41 | reg = <0x404 0x10>; | ||
| 42 | }; | ||
| 43 | |||
| 44 | tsens_calibration_bckp: calib_bckp@504 { | ||
| 45 | reg = <0x504 0x11>; | ||
| 46 | bits = <6 128> | ||
| 47 | }; | ||
| 48 | |||
| 49 | pvs_version: pvs-version@6 { | ||
| 50 | reg = <0x6 0x2> | ||
| 51 | bits = <7 2> | ||
| 52 | }; | ||
| 53 | |||
| 54 | speed_bin: speed-bin@c{ | ||
| 55 | reg = <0xc 0x1>; | ||
| 56 | bits = <2 3>; | ||
| 57 | |||
| 58 | }; | ||
| 59 | ... | ||
| 60 | }; | ||
| 61 | |||
| 62 | = Data consumers = | ||
| 63 | Are device nodes which consume nvmem data cells/providers. | ||
| 64 | |||
| 65 | Required-properties: | ||
| 66 | nvmem-cells: list of phandle to the nvmem data cells. | ||
| 67 | nvmem-cell-names: names for the each nvmem-cells specified. Required if | ||
| 68 | nvmem-cells is used. | ||
| 69 | |||
| 70 | Optional-properties: | ||
| 71 | nvmem : list of phandles to nvmem providers. | ||
| 72 | nvmem-names: names for the each nvmem provider. required if nvmem is used. | ||
| 73 | |||
| 74 | For example: | ||
| 75 | |||
| 76 | tsens { | ||
| 77 | ... | ||
| 78 | nvmem-cells = <&tsens_calibration>; | ||
| 79 | nvmem-cell-names = "calibration"; | ||
| 80 | }; | ||
| @@ -0,0 +1,93 @@ | |||
| 1 | # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) | ||
| 2 | %YAML 1.2 | ||
| 3 | --- | ||
| 4 | $id: http://devicetree.org/schemas/nvmem/nvmem.yaml# | ||
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | ||
| 6 | |||
| 7 | title: NVMEM (Non Volatile Memory) Device Tree Bindings | ||
| 8 | |||
| 9 | maintainers: | ||
| 10 | - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> | ||
| 11 | |||
| 12 | description: | | ||
| 13 | This binding is intended to represent the location of hardware | ||
| 14 | configuration data stored in NVMEMs like eeprom, efuses and so on. | ||
| 15 | |||
| 16 | On a significant proportion of boards, the manufacturer has stored | ||
| 17 | some data on NVMEM, for the OS to be able to retrieve these | ||
| 18 | information and act upon it. Obviously, the OS has to know about | ||
| 19 | where to retrieve these data from, and where they are stored on the | ||
| 20 | storage device. | ||
| 21 | |||
| 22 | properties: | ||
| 23 | $nodename: | ||
| 24 | pattern: "^(eeprom|efuse|nvram)(@.*|-[0-9a-f])*$" | ||
| 25 | |||
| 26 | "#address-cells": | ||
| 27 | const: 1 | ||
| 28 | |||
| 29 | "#size-cells": | ||
| 30 | const: 1 | ||
| 31 | |||
| 32 | read-only: | ||
| 33 | $ref: /schemas/types.yaml#/definitions/flag | ||
| 34 | description: | ||
| 35 | Mark the provider as read only. | ||
| 36 | |||
| 37 | patternProperties: | ||
| 38 | "^.*@[0-9a-f]+$": | ||
| 39 | type: object | ||
| 40 | |||
| 41 | properties: | ||
| 42 | reg: | ||
| 43 | maxItems: 1 | ||
| 44 | description: | ||
| 45 | Offset and size in bytes within the storage device. | ||
| 46 | |||
| 47 | bits: | ||
| 48 | maxItems: 1 | ||
| 49 | items: | ||
| 50 | items: | ||
| 51 | - minimum: 0 | ||
| 52 | maximum: 7 | ||
| 53 | description: | ||
| 54 | Offset in bit within the address range specified by reg. | ||
| 55 | - minimum: 1 | ||
| 56 | description: | ||
| 57 | Size in bit within the address range specified by reg. | ||
| 58 | |||
| 59 | required: | ||
| 60 | - reg | ||
| 61 | |||
| 62 | additionalProperties: false | ||
| 63 | |||
| 64 | examples: | ||
| 65 | - | | ||
| 66 | qfprom: eeprom@700000 { | ||
| 67 | #address-cells = <1>; | ||
| 68 | #size-cells = <1>; | ||
| 69 | |||
| 70 | /* ... */ | ||
| 71 | |||
| 72 | /* Data cells */ | ||
| 73 | tsens_calibration: calib@404 { | ||
| 74 | reg = <0x404 0x10>; | ||
| 75 | }; | ||
| 76 | |||
| 77 | tsens_calibration_bckp: calib_bckp@504 { | ||
| 78 | reg = <0x504 0x11>; | ||
| 79 | bits = <6 128>; | ||
| 80 | }; | ||
| 81 | |||
| 82 | pvs_version: pvs-version@6 { | ||
| 83 | reg = <0x6 0x2>; | ||
| 84 | bits = <7 2>; | ||
| 85 | }; | ||
| 86 | |||
| 87 | speed_bin: speed-bin@c{ | ||
| 88 | reg = <0xc 0x1>; | ||
| 89 | bits = <2 3>; | ||
| 90 | }; | ||
| 91 | }; | ||
| 92 | |||
| 93 | ... | ||
| @@ -1,7 +1,7 @@ | |||
| 1 | # SPDX-License-Identifier: GPL-2.0 | 1 | # SPDX-License-Identifier: GPL-2.0 |
| 2 | %YAML 1.2 | 2 | %YAML 1.2 |
| 3 | --- | 3 | --- |
| 4 | $id: http://devicetree.org/schemas/display/allwinner,sun6i-a31-mipi-dphy.yaml# | 4 | $id: http://devicetree.org/schemas/phy/allwinner,sun6i-a31-mipi-dphy.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# | 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | 6 | ||
| 7 | title: Allwinner A31 MIPI D-PHY Controller Device Tree Bindings | 7 | title: Allwinner A31 MIPI D-PHY Controller Device Tree Bindings |
| @@ -37,7 +37,8 @@ properties: · 36 unmodified lines | |||
| 37 | hwlocks: true | 37 | hwlocks: true |
| 38 | 38 | ||
| 39 | st,syscfg: | 39 | st,syscfg: |
| 40 | $ref: "/schemas/types.yaml#/definitions/phandle-array" | 40 | allOf: |
| 41 | - $ref: "/schemas/types.yaml#/definitions/phandle-array" | ||
| 41 | description: Should be phandle/offset/mask | 42 | description: Should be phandle/offset/mask |
| 42 | items: | 43 | items: |
| 43 | - description: Phandle to the syscon node which includes IRQ mux selection. | 44 | - description: Phandle to the syscon node which includes IRQ mux selection. |
| @@ -1,162 +0,0 @@ | |||
| 1 | =================== | ||
| 2 | RISC-V CPU Bindings | ||
| 3 | =================== | ||
| 4 | |||
| 5 | The device tree allows to describe the layout of CPUs in a system through | ||
| 6 | the "cpus" node, which in turn contains a number of subnodes (ie "cpu") | ||
| 7 | defining properties for every cpu. | ||
| 8 | |||
| 9 | Bindings for CPU nodes follow the Devicetree Specification, available from: | ||
| 10 | |||
| 11 | https://www.devicetree.org/specifications/ | ||
| 12 | |||
| 13 | with updates for 32-bit and 64-bit RISC-V systems provided in this document. | ||
| 14 | |||
| 15 | =========== | ||
| 16 | Terminology | ||
| 17 | =========== | ||
| 18 | |||
| 19 | This document uses some terminology common to the RISC-V community that is not | ||
| 20 | widely used, the definitions of which are listed here: | ||
| 21 | |||
| 22 | * hart: A hardware execution context, which contains all the state mandated by | ||
| 23 | the RISC-V ISA: a PC and some registers. This terminology is designed to | ||
| 24 | disambiguate software's view of execution contexts from any particular | ||
| 25 | microarchitectural implementation strategy. For example, my Intel laptop is | ||
| 26 | described as having one socket with two cores, each of which has two hyper | ||
| 27 | threads. Therefore this system has four harts. | ||
| 28 | |||
| 29 | ===================================== | ||
| 30 | cpus and cpu node bindings definition | ||
| 31 | ===================================== | ||
| 32 | |||
| 33 | The RISC-V architecture, in accordance with the Devicetree Specification, | ||
| 34 | requires the cpus and cpu nodes to be present and contain the properties | ||
| 35 | described below. | ||
| 36 | |||
| 37 | - cpus node | ||
| 38 | |||
| 39 | Description: Container of cpu nodes | ||
| 40 | |||
| 41 | The node name must be "cpus". | ||
| 42 | |||
| 43 | A cpus node must define the following properties: | ||
| 44 | |||
| 45 | - #address-cells | ||
| 46 | Usage: required | ||
| 47 | Value type: <u32> | ||
| 48 | Definition: must be set to 1 | ||
| 49 | - #size-cells | ||
| 50 | Usage: required | ||
| 51 | Value type: <u32> | ||
| 52 | Definition: must be set to 0 | ||
| 53 | |||
| 54 | - cpu node | ||
| 55 | |||
| 56 | Description: Describes a hart context | ||
| 57 | |||
| 58 | PROPERTIES | ||
| 59 | |||
| 60 | - device_type | ||
| 61 | Usage: required | ||
| 62 | Value type: <string> | ||
| 63 | Definition: must be "cpu" | ||
| 64 | - reg | ||
| 65 | Usage: required | ||
| 66 | Value type: <u32> | ||
| 67 | Definition: The hart ID of this CPU node | ||
| 68 | - compatible: | ||
| 69 | Usage: required | ||
| 70 | Value type: <stringlist> | ||
| 71 | Definition: must contain "riscv", may contain one of | ||
| 72 | "sifive,rocket0" | ||
| 73 | - mmu-type: | ||
| 74 | Usage: optional | ||
| 75 | Value type: <string> | ||
| 76 | Definition: Specifies the CPU's MMU type. Possible values are | ||
| 77 | "riscv,sv32" | ||
| 78 | "riscv,sv39" | ||
| 79 | "riscv,sv48" | ||
| 80 | - riscv,isa: | ||
| 81 | Usage: required | ||
| 82 | Value type: <string> | ||
| 83 | Definition: Contains the RISC-V ISA string of this hart. These | ||
| 84 | ISA strings are defined by the RISC-V ISA manual. | ||
| 85 | |||
| 86 | Example: SiFive Freedom U540G Development Kit | ||
| 87 | --------------------------------------------- | ||
| 88 | |||
| 89 | This system contains two harts: a hart marked as disabled that's used for | ||
| 90 | low-level system tasks and should be ignored by Linux, and a second hart that | ||
| 91 | Linux is allowed to run on. | ||
| 92 | |||
| 93 | cpus { | ||
| 94 | #address-cells = <1>; | ||
| 95 | #size-cells = <0>; | ||
| 96 | timebase-frequency = <1000000>; | ||
| 97 | cpu@0 { | ||
| 98 | clock-frequency = <1600000000>; | ||
| 99 | compatible = "sifive,rocket0", "riscv"; | ||
| 100 | device_type = "cpu"; | ||
| 101 | i-cache-block-size = <64>; | ||
| 102 | i-cache-sets = <128>; | ||
| 103 | i-cache-size = <16384>; | ||
| 104 | next-level-cache = <&L15 &L0>; | ||
| 105 | reg = <0>; | ||
| 106 | riscv,isa = "rv64imac"; | ||
| 107 | status = "disabled"; | ||
| 108 | L10: interrupt-controller { | ||
| 109 | #interrupt-cells = <1>; | ||
| 110 | compatible = "riscv,cpu-intc"; | ||
| 111 | interrupt-controller; | ||
| 112 | }; | ||
| 113 | }; | ||
| 114 | cpu@1 { | ||
| 115 | clock-frequency = <1600000000>; | ||
| 116 | compatible = "sifive,rocket0", "riscv"; | ||
| 117 | d-cache-block-size = <64>; | ||
| 118 | d-cache-sets = <64>; | ||
| 119 | d-cache-size = <32768>; | ||
| 120 | d-tlb-sets = <1>; | ||
| 121 | d-tlb-size = <32>; | ||
| 122 | device_type = "cpu"; | ||
| 123 | i-cache-block-size = <64>; | ||
| 124 | i-cache-sets = <64>; | ||
| 125 | i-cache-size = <32768>; | ||
| 126 | i-tlb-sets = <1>; | ||
| 127 | i-tlb-size = <32>; | ||
| 128 | mmu-type = "riscv,sv39"; | ||
| 129 | next-level-cache = <&L15 &L0>; | ||
| 130 | reg = <1>; | ||
| 131 | riscv,isa = "rv64imafdc"; | ||
| 132 | status = "okay"; | ||
| 133 | tlb-split; | ||
| 134 | L13: interrupt-controller { | ||
| 135 | #interrupt-cells = <1>; | ||
| 136 | compatible = "riscv,cpu-intc"; | ||
| 137 | interrupt-controller; | ||
| 138 | }; | ||
| 139 | }; | ||
| 140 | }; | ||
| 141 | |||
| 142 | Example: Spike ISA Simulator with 1 Hart | ||
| 143 | ---------------------------------------- | ||
| 144 | |||
| 145 | This device tree matches the Spike ISA golden model as run with `spike -p1`. | ||
| 146 | |||
| 147 | cpus { | ||
| 148 | cpu@0 { | ||
| 149 | device_type = "cpu"; | ||
| 150 | reg = <0x00000000>; | ||
| 151 | status = "okay"; | ||
| 152 | compatible = "riscv"; | ||
| 153 | riscv,isa = "rv64imafdc"; | ||
| 154 | mmu-type = "riscv,sv48"; | ||
| 155 | clock-frequency = <0x3b9aca00>; | ||
| 156 | interrupt-controller { | ||
| 157 | #interrupt-cells = <0x00000001>; | ||
| 158 | interrupt-controller; | ||
| 159 | compatible = "riscv,cpu-intc"; | ||
| 160 | } | ||
| 161 | } | ||
| 162 | } | ||
| @@ -10,6 +10,18 @@ maintainers: · 9 unmodified lines | |||
| 10 | - Paul Walmsley <paul.walmsley@sifive.com> | 10 | - Paul Walmsley <paul.walmsley@sifive.com> |
| 11 | - Palmer Dabbelt <palmer@sifive.com> | 11 | - Palmer Dabbelt <palmer@sifive.com> |
| 12 | 12 | ||
| 13 | description: | | ||
| 14 | This document uses some terminology common to the RISC-V community | ||
| 15 | that is not widely used, the definitions of which are listed here: | ||
| 16 | |||
| 17 | hart: A hardware execution context, which contains all the state | ||
| 18 | mandated by the RISC-V ISA: a PC and some registers. This | ||
| 19 | terminology is designed to disambiguate software's view of execution | ||
| 20 | contexts from any particular microarchitectural implementation | ||
| 21 | strategy. For example, an Intel laptop containing one socket with | ||
| 22 | two cores, each of which has two hyperthreads, could be described as | ||
| 23 | having four harts. | ||
| 24 | |||
| 13 | properties: | 25 | properties: |
| 14 | compatible: | 26 | compatible: |
| 15 | items: | 27 | items: |
| @@ -50,6 +62,10 @@ properties: · 34 unmodified lines | |||
| 50 | User-Level ISA document, available from | 62 | User-Level ISA document, available from |
| 51 | https://riscv.org/specifications/ | 63 | https://riscv.org/specifications/ |
| 52 | 64 | ||
| 65 | While the isa strings in ISA specification are case | ||
| 66 | insensitive, letters in the riscv,isa string must be all | ||
| 67 | lowercase to simplify parsing. | ||
| 68 | |||
| 53 | timebase-frequency: | 69 | timebase-frequency: |
| 54 | type: integer | 70 | type: integer |
| 55 | minimum: 1 | 71 | minimum: 1 |
| @@ -19,7 +19,7 @@ properties: · 18 unmodified lines | |||
| 19 | compatible: | 19 | compatible: |
| 20 | items: | 20 | items: |
| 21 | - enum: | 21 | - enum: |
| 22 | - sifive,freedom-unleashed-a00 | 22 | - sifive,hifive-unleashed-a00 |
| 23 | - const: sifive,fu540-c000 | 23 | - const: sifive,fu540-c000 |
| 24 | - const: sifive,fu540 | 24 | - const: sifive,fu540 |
| 25 | ... | 25 | ... |
| @@ -73,7 +73,6 @@ patternProperties: · 72 unmodified lines | |||
| 73 | Compatible of the SPI device. | 73 | Compatible of the SPI device. |
| 74 | 74 | ||
| 75 | reg: | 75 | reg: |
| 76 | maxItems: 1 | ||
| 77 | minimum: 0 | 76 | minimum: 0 |
| 78 | maximum: 256 | 77 | maximum: 256 |
| 79 | description: | 78 | description: |
| @@ -2,7 +2,7 @@ · 1 unmodified line | |||
| 2 | # Copyright 2018 Linaro Ltd. | 2 | # Copyright 2018 Linaro Ltd. |
| 3 | %YAML 1.2 | 3 | %YAML 1.2 |
| 4 | --- | 4 | --- |
| 5 | $id: "http://devicetree.org/schemas/timer/intel-ixp4xx-timer.yaml#" | 5 | $id: "http://devicetree.org/schemas/timer/intel,ixp4xx-timer.yaml#" |
| 6 | $schema: "http://devicetree.org/meta-schemas/core.yaml#" | 6 | $schema: "http://devicetree.org/meta-schemas/core.yaml#" |
| 7 | 7 | ||
| 8 | title: Intel IXP4xx XScale Networking Processors Timers | 8 | title: Intel IXP4xx XScale Networking Processors Timers |
| @@ -64,10 +64,8 @@ Optional properties : · 63 unmodified lines | |||
| 64 | - power-on-time-ms : Specifies the time it takes from the time the host | 64 | - power-on-time-ms : Specifies the time it takes from the time the host |
| 65 | initiates the power-on sequence to a port until the port has adequate | 65 | initiates the power-on sequence to a port until the port has adequate |
| 66 | power. The value is given in ms in a 0 - 510 range (default is 100ms). | 66 | power. The value is given in ms in a 0 - 510 range (default is 100ms). |
| 67 | - swap-dx-lanes : Specifies the downstream ports which will swap the | 67 | - swap-dx-lanes : Specifies the ports which will swap the differential-pair |
| 68 | differential-pair (D+/D-), default is not-swapped. | 68 | (D+/D-), default is not-swapped. |
| 69 | - swap-us-lanes : Selects the upstream port differential-pair (D+/D-) | ||
| 70 | swapping (boolean, default is not-swapped) | ||
| 71 | 69 | ||
| 72 | Examples: | 70 | Examples: |
| 73 | usb2512b@2c { | 71 | usb2512b@2c { |
| @@ -1,10 +0,0 @@ | |||
| 1 | # -*- coding: utf-8; mode: python -*- | ||
| 2 | |||
| 3 | project = 'Linux Kernel Documentation Guide' | ||
| 4 | |||
| 5 | tags.add("subproject") | ||
| 6 | |||
| 7 | latex_documents = [ | ||
| 8 | ('index', 'kernel-doc-guide.tex', 'Linux Kernel Documentation Guide', | ||
| 9 | 'The kernel development community', 'manual'), | ||
| 10 | ] | ||
| @@ -1,10 +0,0 @@ | |||
| 1 | # -*- coding: utf-8; mode: python -*- | ||
| 2 | |||
| 3 | project = "Linux 802.11 Driver Developer's Guide" | ||
| 4 | |||
| 5 | tags.add("subproject") | ||
| 6 | |||
| 7 | latex_documents = [ | ||
| 8 | ('index', '80211.tex', project, | ||
| 9 | 'The kernel development community', 'manual'), | ||
| 10 | ] | ||
| @@ -1,10 +0,0 @@ | |||
| 1 | # -*- coding: utf-8; mode: python -*- | ||
| 2 | |||
| 3 | project = "The Linux driver implementer's API guide" | ||
| 4 | |||
| 5 | tags.add("subproject") | ||
| 6 | |||
| 7 | latex_documents = [ | ||
| 8 | ('index', 'driver-api.tex', project, | ||
| 9 | 'The kernel development community', 'manual'), | ||
| 10 | ] | ||
| @@ -233,7 +233,7 @@ Userspace Interface · 232 unmodified lines | |||
| 233 | Several sysfs attributes are generated by the Generic Counter interface, | 233 | Several sysfs attributes are generated by the Generic Counter interface, |
| 234 | and reside under the /sys/bus/counter/devices/counterX directory, where | 234 | and reside under the /sys/bus/counter/devices/counterX directory, where |
| 235 | counterX refers to the respective counter device. Please see | 235 | counterX refers to the respective counter device. Please see |
| 236 | Documentation/ABI/testing/sys-bus-counter-generic-sysfs for detailed | 236 | Documentation/ABI/testing/sysfs-bus-counter for detailed |
| 237 | information on each Generic Counter interface sysfs attribute. | 237 | information on each Generic Counter interface sysfs attribute. |
| 238 | 238 | ||
| 239 | Through these sysfs attributes, programs and scripts may interact with | 239 | Through these sysfs attributes, programs and scripts may interact with |
| @@ -325,7 +325,7 @@ sysfs attributes, where Y is the unique ID of the respective Count: · 85 unmodified lines | |||
| 325 | 325 | ||
| 326 | For a more detailed breakdown of the available Generic Counter interface | 326 | For a more detailed breakdown of the available Generic Counter interface |
| 327 | sysfs attributes, please refer to the | 327 | sysfs attributes, please refer to the |
| 328 | Documentation/ABI/testing/sys-bus-counter file. | 328 | Documentation/ABI/testing/sysfs-bus-counter file. |
| 329 | 329 | ||
| 330 | The Signals and Counts associated with the Counter device are registered | 330 | The Signals and Counts associated with the Counter device are registered |
| 331 | to the system as well by the counter_register function. The | 331 | to the system as well by the counter_register function. The |
| @@ -179,8 +179,8 @@ PHY Mappings · 178 unmodified lines | |||
| 179 | 179 | ||
| 180 | In order to get reference to a PHY without help from DeviceTree, the framework | 180 | In order to get reference to a PHY without help from DeviceTree, the framework |
| 181 | offers lookups which can be compared to clkdev that allow clk structures to be | 181 | offers lookups which can be compared to clkdev that allow clk structures to be |
| 182 | bound to devices. A lookup can be made be made during runtime when a handle to | 182 | bound to devices. A lookup can be made during runtime when a handle to the |
| 183 | the struct phy already exists. | 183 | struct phy already exists. |
| 184 | 184 | ||
| 185 | The framework offers the following API for registering and unregistering the | 185 | The framework offers the following API for registering and unregistering the |
| 186 | lookups:: | 186 | lookups:: |
| @@ -1,10 +0,0 @@ | |||
| 1 | # -*- coding: utf-8; mode: python -*- | ||
| 2 | |||
| 3 | project = "Device Power Management" | ||
| 4 | |||
| 5 | tags.add("subproject") | ||
| 6 | |||
| 7 | latex_documents = [ | ||
| 8 | ('index', 'pm.tex', project, | ||
| 9 | 'The kernel development community', 'manual'), | ||
| 10 | ] | ||
| @@ -13,7 +13,8 @@ a) SMB3 (and SMB3.1.1) missing optional features: · 12 unmodified lines | |||
| 13 | - T10 copy offload ie "ODX" (copy chunk, and "Duplicate Extents" ioctl | 13 | - T10 copy offload ie "ODX" (copy chunk, and "Duplicate Extents" ioctl |
| 14 | currently the only two server side copy mechanisms supported) | 14 | currently the only two server side copy mechanisms supported) |
| 15 | 15 | ||
| 16 | b) improved sparse file support | 16 | b) improved sparse file support (fiemap and SEEK_HOLE are implemented |
| 17 | but additional features would be supportable by the protocol). | ||
| 17 | 18 | ||
| 18 | c) Directory entry caching relies on a 1 second timer, rather than | 19 | c) Directory entry caching relies on a 1 second timer, rather than |
| 19 | using Directory Leases, currently only the root file handle is cached longer | 20 | using Directory Leases, currently only the root file handle is cached longer |
| @@ -21,9 +22,13 @@ using Directory Leases, currently only the root file handle is cached longer · 1 unmodified line | |||
| 21 | d) quota support (needs minor kernel change since quota calls | 22 | d) quota support (needs minor kernel change since quota calls |
| 22 | to make it to network filesystems or deviceless filesystems) | 23 | to make it to network filesystems or deviceless filesystems) |
| 23 | 24 | ||
| 24 | e) Additional use cases where we use "compoounding" (e.g. open/query/close | 25 | e) Additional use cases can be optimized to use "compounding" |
| 25 | and open/setinfo/close) to reduce the number of roundtrips, and also | 26 | (e.g. open/query/close and open/setinfo/close) to reduce the number |
| 26 | open to reduce redundant opens (using deferred close and reference counts more). | 27 | of roundtrips to the server and improve performance. Various cases |
| 28 | (stat, statfs, create, unlink, mkdir) already have been improved by | ||
| 29 | using compounding but more can be done. In addition we could significantly | ||
| 30 | reduce redundant opens by using deferred close (with handle caching leases) | ||
| 31 | and better using reference counters on file handles. | ||
| 27 | 32 | ||
| 28 | f) Finish inotify support so kde and gnome file list windows | 33 | f) Finish inotify support so kde and gnome file list windows |
| 29 | will autorefresh (partially complete by Asser). Needs minor kernel | 34 | will autorefresh (partially complete by Asser). Needs minor kernel |
| @@ -43,18 +48,17 @@ mount or a per server basis to client UIDs or nobody if no mapping · 13 unmodified lines | |||
| 43 | exists. Also better integration with winbind for resolving SID owners | 48 | exists. Also better integration with winbind for resolving SID owners |
| 44 | 49 | ||
| 45 | k) Add tools to take advantage of more smb3 specific ioctls and features | 50 | k) Add tools to take advantage of more smb3 specific ioctls and features |
| 46 | (passthrough ioctl/fsctl for sending various SMB3 fsctls to the server | 51 | (passthrough ioctl/fsctl is now implemented in cifs.ko to allow sending |
| 47 | is in progress, and a passthrough query_info call is already implemented | 52 | various SMB3 fsctls and query info and set info calls directly from user space) |
| 48 | in cifs.ko to allow smb3 info levels queries to be sent from userspace) | 53 | Add tools to make setting various non-POSIX metadata attributes easier |
| 54 | from tools (e.g. extending what was done in smb-info tool). | ||
| 49 | 55 | ||
| 50 | l) encrypted file support | 56 | l) encrypted file support |
| 51 | 57 | ||
| 52 | m) improved stats gathering tools (perhaps integration with nfsometer?) | 58 | m) improved stats gathering tools (perhaps integration with nfsometer?) |
| 53 | to extend and make easier to use what is currently in /proc/fs/cifs/Stats | 59 | to extend and make easier to use what is currently in /proc/fs/cifs/Stats |
| 54 | 60 | ||
| 55 | n) allow setting more NTFS/SMB3 file attributes remotely (currently limited to compressed | 61 | n) Add support for claims based ACLs ("DAC") |
| 56 | file attribute via chflags) and improve user space tools for managing and | ||
| 57 | viewing them. | ||
| 58 | 62 | ||
| 59 | o) mount helper GUI (to simplify the various configuration options on mount) | 63 | o) mount helper GUI (to simplify the various configuration options on mount) |
| 60 | 64 | ||
| @@ -82,6 +86,8 @@ so far). · 21 unmodified lines | |||
| 82 | w) Add support for additional strong encryption types, and additional spnego | 86 | w) Add support for additional strong encryption types, and additional spnego |
| 83 | authentication mechanisms (see MS-SMB2) | 87 | authentication mechanisms (see MS-SMB2) |
| 84 | 88 | ||
| 89 | x) Finish support for SMB3.1.1 compression | ||
| 90 | |||
| 85 | KNOWN BUGS | 91 | KNOWN BUGS |
| 86 | ==================================== | 92 | ==================================== |
| 87 | See http://bugzilla.samba.org - search on product "CifsVFS" for | 93 | See http://bugzilla.samba.org - search on product "CifsVFS" for |
| @@ -1,10 +0,0 @@ | |||
| 1 | # -*- coding: utf-8; mode: python -*- | ||
| 2 | |||
| 3 | project = "Linux Filesystems API" | ||
| 4 | |||
| 5 | tags.add("subproject") | ||
| 6 | |||
| 7 | latex_documents = [ | ||
| 8 | ('index', 'filesystems.tex', project, | ||
| 9 | 'The kernel development community', 'manual'), | ||
| 10 | ] | ||
| @@ -1,10 +0,0 @@ | |||
| 1 | # -*- coding: utf-8; mode: python -*- | ||
| 2 | |||
| 3 | project = "Linux GPU Driver Developer's Guide" | ||
| 4 | |||
| 5 | tags.add("subproject") | ||
| 6 | |||
| 7 | latex_documents = [ | ||
| 8 | ('index', 'gpu.tex', project, | ||
| 9 | 'The kernel development community', 'manual'), | ||
| 10 | ] | ||
| @@ -9,7 +9,7 @@ Supported chips: · 8 unmodified lines | |||
| 9 | 9 | ||
| 10 | Addresses scanned: PCI space | 10 | Addresses scanned: PCI space |
| 11 | 11 | ||
| 12 | Datasheet: http://support.amd.com/us/Processor_TechDocs/32559.pdf | 12 | Datasheet: http://www.amd.com/system/files/TechDocs/32559.pdf |
| 13 | 13 | ||
| 14 | Author: Rudolf Marek | 14 | Author: Rudolf Marek |
| 15 | 15 | ||
| @@ -111,9 +111,11 @@ needed). · 110 unmodified lines | |||
| 111 | netlabel/index | 111 | netlabel/index |
| 112 | networking/index | 112 | networking/index |
| 113 | pcmcia/index | 113 | pcmcia/index |
| 114 | power/index | ||
| 114 | target/index | 115 | target/index |
| 115 | timers/index | 116 | timers/index |
| 116 | watchdog/index | 117 | watchdog/index |
| 118 | virtual/index | ||
| 117 | input/index | 119 | input/index |
| 118 | hwmon/index | 120 | hwmon/index |
| 119 | gpu/index | 121 | gpu/index |
| @@ -143,6 +145,7 @@ implementation. · 23 unmodified lines | |||
| 143 | arm64/index | 145 | arm64/index |
| 144 | ia64/index | 146 | ia64/index |
| 145 | m68k/index | 147 | m68k/index |
| 148 | powerpc/index | ||
| 146 | riscv/index | 149 | riscv/index |
| 147 | s390/index | 150 | s390/index |
| 148 | sh/index | 151 | sh/index |
| @@ -1,10 +0,0 @@ | |||
| 1 | # -*- coding: utf-8; mode: python -*- | ||
| 2 | |||
| 3 | project = "The Linux input driver subsystem" | ||
| 4 | |||
| 5 | tags.add("subproject") | ||
| 6 | |||
| 7 | latex_documents = [ | ||
| 8 | ('index', 'linux-input.tex', project, | ||
| 9 | 'The kernel development community', 'manual'), | ||
| 10 | ] | ||
| @@ -1,10 +0,0 @@ | |||
| 1 | # -*- coding: utf-8; mode: python -*- | ||
| 2 | |||
| 3 | project = "Kernel Hacking Guides" | ||
| 4 | |||
| 5 | tags.add("subproject") | ||
| 6 | |||
| 7 | latex_documents = [ | ||
| 8 | ('index', 'kernel-hacking.tex', project, | ||
| 9 | 'The kernel development community', 'manual'), | ||
| 10 | ] | ||
| @@ -82,7 +82,7 @@ itself. The read lock allows many concurrent readers. Anything that · 81 unmodified lines | |||
| 82 | **changes** the list will have to get the write lock. | 82 | **changes** the list will have to get the write lock. |
| 83 | 83 | ||
| 84 | NOTE! RCU is better for list traversal, but requires careful | 84 | NOTE! RCU is better for list traversal, but requires careful |
| 85 | attention to design detail (see Documentation/RCU/listRCU.txt). | 85 | attention to design detail (see Documentation/RCU/listRCU.rst). |
| 86 | 86 | ||
| 87 | Also, you cannot "upgrade" a read-lock to a write-lock, so if you at _any_ | 87 | Also, you cannot "upgrade" a read-lock to a write-lock, so if you at _any_ |
| 88 | time need to do any changes (even if you don't do it every time), you have | 88 | time need to do any changes (even if you don't do it every time), you have |
| @@ -90,7 +90,7 @@ to get the write-lock at the very beginning. · 1 unmodified line | |||
| 90 | 90 | ||
| 91 | NOTE! We are working hard to remove reader-writer spinlocks in most | 91 | NOTE! We are working hard to remove reader-writer spinlocks in most |
| 92 | cases, so please don't add a new one without consensus. (Instead, see | 92 | cases, so please don't add a new one without consensus. (Instead, see |
| 93 | Documentation/RCU/rcu.txt for complete information.) | 93 | Documentation/RCU/rcu.rst for complete information.) |
| 94 | 94 | ||
| 95 | ---- | 95 | ---- |
| 96 | 96 | ||
| @@ -1,10 +0,0 @@ | |||
| 1 | # -*- coding: utf-8; mode: python -*- | ||
| 2 | |||
| 3 | project = 'Linux Kernel Development Documentation' | ||
| 4 | |||
| 5 | tags.add("subproject") | ||
| 6 | |||
| 7 | latex_documents = [ | ||
| 8 | ('index', 'maintainer.tex', 'Linux Kernel Development Documentation', | ||
| 9 | 'The kernel development community', 'manual'), | ||
| 10 | ] | ||
| @@ -1,12 +0,0 @@ | |||
| 1 | # -*- coding: utf-8; mode: python -*- | ||
| 2 | |||
| 3 | # SPDX-License-Identifier: GPL-2.0 | ||
| 4 | |||
| 5 | project = 'Linux Media Subsystem Documentation' | ||
| 6 | |||
| 7 | tags.add("subproject") | ||
| 8 | |||
| 9 | latex_documents = [ | ||
| 10 | ('index', 'media.tex', 'Linux Media Subsystem Documentation', | ||
| 11 | 'The kernel development community', 'manual'), | ||
| 12 | ] | ||
| @@ -548,7 +548,7 @@ There are certain things that the Linux kernel memory barriers do not guarantee: · 547 unmodified lines | |||
| 548 | 548 | ||
| 549 | [*] For information on bus mastering DMA and coherency please read: | 549 | [*] For information on bus mastering DMA and coherency please read: |
| 550 | 550 | ||
| 551 | Documentation/PCI/pci.rst | 551 | Documentation/driver-api/pci/pci.rst |
| 552 | Documentation/DMA-API-HOWTO.txt | 552 | Documentation/DMA-API-HOWTO.txt |
| 553 | Documentation/DMA-API.txt | 553 | Documentation/DMA-API.txt |
| 554 | 554 | ||
| @@ -1,10 +0,0 @@ | |||
| 1 | # -*- coding: utf-8; mode: python -*- | ||
| 2 | |||
| 3 | project = "Linux Networking Documentation" | ||
| 4 | |||
| 5 | tags.add("subproject") | ||
| 6 | |||
| 7 | latex_documents = [ | ||
| 8 | ('index', 'networking.tex', project, | ||
| 9 | 'The kernel development community', 'manual'), | ||
| 10 | ] | ||
| @@ -424,13 +424,24 @@ Statistics · 423 unmodified lines | |||
| 424 | Following minimum set of TLS-related statistics should be reported | 424 | Following minimum set of TLS-related statistics should be reported |
| 425 | by the driver: | 425 | by the driver: |
| 426 | 426 | ||
| 427 | * ``rx_tls_decrypted`` - number of successfully decrypted TLS segments | 427 | * ``rx_tls_decrypted_packets`` - number of successfully decrypted RX packets |
| 428 | * ``tx_tls_encrypted`` - number of in-order TLS segments passed to device | 428 | which were part of a TLS stream. |
| 429 | for encryption | 429 | * ``rx_tls_decrypted_bytes`` - number of TLS payload bytes in RX packets |
| 430 | which were successfully decrypted. | ||
| 431 | * ``tx_tls_encrypted_packets`` - number of TX packets passed to the device | ||
| 432 | for encryption of their TLS payload. | ||
| 433 | * ``tx_tls_encrypted_bytes`` - number of TLS payload bytes in TX packets | ||
| 434 | passed to the device for encryption. | ||
| 435 | * ``tx_tls_ctx`` - number of TLS TX HW offload contexts added to device for | ||
| 436 | encryption. | ||
| 430 | * ``tx_tls_ooo`` - number of TX packets which were part of a TLS stream | 437 | * ``tx_tls_ooo`` - number of TX packets which were part of a TLS stream |
| 431 | but did not arrive in the expected order | 438 | but did not arrive in the expected order. |
| 432 | * ``tx_tls_drop_no_sync_data`` - number of TX packets dropped because | 439 | * ``tx_tls_drop_no_sync_data`` - number of TX packets which were part of |
| 433 | they arrived out of order and associated record could not be found | 440 | a TLS stream dropped, because they arrived out of order and associated |
| 441 | record could not be found. | ||
| 442 | * ``tx_tls_drop_bypass_req`` - number of TX packets which were part of a TLS | ||
| 443 | stream dropped, because they contain both data that has been encrypted by | ||
| 444 | software and data that expects hardware crypto offload. | ||
| 434 | 445 | ||
| 435 | Notable corner cases, exceptions and additional requirements | 446 | Notable corner cases, exceptions and additional requirements |
| 436 | ============================================================ | 447 | ============================================================ |
| @@ -1,4 +1,4 @@ | |||
| 1 | :orphan: | 1 | .. SPDX-License-Identifier: GPL-2.0 |
| 2 | 2 | ||
| 3 | ================ | 3 | ================ |
| 4 | Power Management | 4 | Power Management |
| @@ -1,5 +1,7 @@ | |||
| 1 | ======================== | ||
| 1 | The PowerPC boot wrapper | 2 | The PowerPC boot wrapper |
| 2 | ------------------------ | 3 | ======================== |
| 4 | |||
| 3 | Copyright (C) Secret Lab Technologies Ltd. | 5 | Copyright (C) Secret Lab Technologies Ltd. |
| 4 | 6 | ||
| 5 | PowerPC image targets compresses and wraps the kernel image (vmlinux) with | 7 | PowerPC image targets compresses and wraps the kernel image (vmlinux) with |
| @@ -21,6 +23,7 @@ it uses the wrapper script (arch/powerpc/boot/wrapper) to generate target · 15 unmodified lines | |||
| 21 | image. The details of the build system is discussed in the next section. | 23 | image. The details of the build system is discussed in the next section. |
| 22 | Currently, the following image format targets exist: | 24 | Currently, the following image format targets exist: |
| 23 | 25 | ||
| 26 | ==================== ======================================================== | ||
| 24 | cuImage.%: Backwards compatible uImage for older version of | 27 | cuImage.%: Backwards compatible uImage for older version of |
| 25 | U-Boot (for versions that don't understand the device | 28 | U-Boot (for versions that don't understand the device |
| 26 | tree). This image embeds a device tree blob inside | 29 | tree). This image embeds a device tree blob inside |
| @@ -29,31 +32,36 @@ Currently, the following image format targets exist: · 2 unmodified lines | |||
| 29 | with boot wrapper code that extracts data from the old | 32 | with boot wrapper code that extracts data from the old |
| 30 | bd_info structure and loads the data into the device | 33 | bd_info structure and loads the data into the device |
| 31 | tree before jumping into the kernel. | 34 | tree before jumping into the kernel. |
| 32 | Because of the series of #ifdefs found in the | 35 | |
| 36 | Because of the series of #ifdefs found in the | ||
| 33 | bd_info structure used in the old U-Boot interfaces, | 37 | bd_info structure used in the old U-Boot interfaces, |
| 34 | cuImages are platform specific. Each specific | 38 | cuImages are platform specific. Each specific |
| 35 | U-Boot platform has a different platform init file | 39 | U-Boot platform has a different platform init file |
| 36 | which populates the embedded device tree with data | 40 | which populates the embedded device tree with data |
| 37 | from the platform specific bd_info file. The platform | 41 | from the platform specific bd_info file. The platform |
| 38 | specific cuImage platform init code can be found in | 42 | specific cuImage platform init code can be found in |
| 39 | arch/powerpc/boot/cuboot.*.c. Selection of the correct | 43 | `arch/powerpc/boot/cuboot.*.c`. Selection of the correct |
| 40 | cuImage init code for a specific board can be found in | 44 | cuImage init code for a specific board can be found in |
| 41 | the wrapper structure. | 45 | the wrapper structure. |
| 46 | |||
| 42 | dtbImage.%: Similar to zImage, except device tree blob is embedded | 47 | dtbImage.%: Similar to zImage, except device tree blob is embedded |
| 43 | inside the image instead of provided by firmware. The | 48 | inside the image instead of provided by firmware. The |
| 44 | output image file can be either an elf file or a flat | 49 | output image file can be either an elf file or a flat |
| 45 | binary depending on the platform. | 50 | binary depending on the platform. |
| 46 | dtbImages are used on systems which do not have an | 51 | |
| 52 | dtbImages are used on systems which do not have an | ||
| 47 | interface for passing a device tree directly. | 53 | interface for passing a device tree directly. |
| 48 | dtbImages are similar to simpleImages except that | 54 | dtbImages are similar to simpleImages except that |
| 49 | dtbImages have platform specific code for extracting | 55 | dtbImages have platform specific code for extracting |
| 50 | data from the board firmware, but simpleImages do not | 56 | data from the board firmware, but simpleImages do not |
| 51 | talk to the firmware at all. | 57 | talk to the firmware at all. |
| 52 | PlayStation 3 support uses dtbImage. So do Embedded | 58 | |
| 59 | PlayStation 3 support uses dtbImage. So do Embedded | ||
| 53 | Planet boards using the PlanetCore firmware. Board | 60 | Planet boards using the PlanetCore firmware. Board |
| 54 | specific initialization code is typically found in a | 61 | specific initialization code is typically found in a |
| 55 | file named arch/powerpc/boot/<platform>.c; but this | 62 | file named arch/powerpc/boot/<platform>.c; but this |
| 56 | can be overridden by the wrapper script. | 63 | can be overridden by the wrapper script. |
| 64 | |||
| 57 | simpleImage.%: Firmware independent compressed image that does not | 65 | simpleImage.%: Firmware independent compressed image that does not |
| 58 | depend on any particular firmware interface and embeds | 66 | depend on any particular firmware interface and embeds |
| 59 | a device tree blob. This image is a flat binary that | 67 | a device tree blob. This image is a flat binary that |
| @@ -61,14 +69,16 @@ Currently, the following image format targets exist: · 1 unmodified line | |||
| 61 | Firmware cannot pass any configuration data to the | 69 | Firmware cannot pass any configuration data to the |
| 62 | kernel with this image type and it depends entirely on | 70 | kernel with this image type and it depends entirely on |
| 63 | the embedded device tree for all information. | 71 | the embedded device tree for all information. |
| 64 | The simpleImage is useful for booting systems with | 72 | |
| 73 | The simpleImage is useful for booting systems with | ||
| 65 | an unknown firmware interface or for booting from | 74 | an unknown firmware interface or for booting from |
| 66 | a debugger when no firmware is present (such as on | 75 | a debugger when no firmware is present (such as on |
| 67 | the Xilinx Virtex platform). The only assumption that | 76 | the Xilinx Virtex platform). The only assumption that |
| 68 | simpleImage makes is that RAM is correctly initialized | 77 | simpleImage makes is that RAM is correctly initialized |
| 69 | and that the MMU is either off or has RAM mapped to | 78 | and that the MMU is either off or has RAM mapped to |
| 70 | base address 0. | 79 | base address 0. |
| 71 | simpleImage also supports inserting special platform | 80 | |
| 81 | simpleImage also supports inserting special platform | ||
| 72 | specific initialization code to the start of the bootup | 82 | specific initialization code to the start of the bootup |
| 73 | sequence. The virtex405 platform uses this feature to | 83 | sequence. The virtex405 platform uses this feature to |
| 74 | ensure that the cache is invalidated before caching | 84 | ensure that the cache is invalidated before caching |
| @@ -81,9 +91,11 @@ Currently, the following image format targets exist: · 6 unmodified lines | |||
| 81 | named (virtex405-<board>.dts). Search the wrapper | 91 | named (virtex405-<board>.dts). Search the wrapper |
| 82 | script for 'virtex405' and see the file | 92 | script for 'virtex405' and see the file |
| 83 | arch/powerpc/boot/virtex405-head.S for details. | 93 | arch/powerpc/boot/virtex405-head.S for details. |
| 94 | |||
| 84 | treeImage.%; Image format for used with OpenBIOS firmware found | 95 | treeImage.%; Image format for used with OpenBIOS firmware found |
| 85 | on some ppc4xx hardware. This image embeds a device | 96 | on some ppc4xx hardware. This image embeds a device |
| 86 | tree blob inside the image. | 97 | tree blob inside the image. |
| 98 | |||
| 87 | uImage: Native image format used by U-Boot. The uImage target | 99 | uImage: Native image format used by U-Boot. The uImage target |
| 88 | does not add any boot code. It just wraps a compressed | 100 | does not add any boot code. It just wraps a compressed |
| 89 | vmlinux in the uImage data structure. This image | 101 | vmlinux in the uImage data structure. This image |
| @@ -91,12 +103,14 @@ Currently, the following image format targets exist: · 1 unmodified line | |||
| 91 | a device tree to the kernel at boot. If using an older | 103 | a device tree to the kernel at boot. If using an older |
| 92 | version of U-Boot, then you need to use a cuImage | 104 | version of U-Boot, then you need to use a cuImage |
| 93 | instead. | 105 | instead. |
| 106 | |||
| 94 | zImage.%: Image format which does not embed a device tree. | 107 | zImage.%: Image format which does not embed a device tree. |
| 95 | Used by OpenFirmware and other firmware interfaces | 108 | Used by OpenFirmware and other firmware interfaces |
| 96 | which are able to supply a device tree. This image | 109 | which are able to supply a device tree. This image |
| 97 | expects firmware to provide the device tree at boot. | 110 | expects firmware to provide the device tree at boot. |
| 98 | Typically, if you have general purpose PowerPC | 111 | Typically, if you have general purpose PowerPC |
| 99 | hardware then you want this image format. | 112 | hardware then you want this image format. |
| 113 | ==================== ======================================================== | ||
| 100 | 114 | ||
| 101 | Image types which embed a device tree blob (simpleImage, dtbImage, treeImage, | 115 | Image types which embed a device tree blob (simpleImage, dtbImage, treeImage, |
| 102 | and cuImage) all generate the device tree blob from a file in the | 116 | and cuImage) all generate the device tree blob from a file in the |
| @@ -1,3 +1,4 @@ | |||
| 1 | ============ | ||
| 1 | CPU Families | 2 | CPU Families |
| 2 | ============ | 3 | ============ |
| 3 | 4 | ||
| @@ -8,8 +9,8 @@ and are supported by arch/powerpc. · 4 unmodified lines | |||
| 8 | Book3S (aka sPAPR) | 9 | Book3S (aka sPAPR) |
| 9 | ------------------ | 10 | ------------------ |
| 10 | 11 | ||
| 11 | - Hash MMU | 12 | - Hash MMU |
| 12 | - Mix of 32 & 64 bit | 13 | - Mix of 32 & 64 bit:: |
| 13 | 14 | ||
| 14 | +--------------+ +----------------+ | 15 | +--------------+ +----------------+ |
| 15 | | Old POWER | --------------> | RS64 (threads) | | 16 | | Old POWER | --------------> | RS64 (threads) | |
| @@ -108,8 +109,8 @@ Book3S (aka sPAPR) · 92 unmodified lines | |||
| 108 | IBM BookE | 109 | IBM BookE |
| 109 | --------- | 110 | --------- |
| 110 | 111 | ||
| 111 | - Software loaded TLB. | 112 | - Software loaded TLB. |
| 112 | - All 32 bit | 113 | - All 32 bit:: |
| 113 | 114 | ||
| 114 | +--------------+ | 115 | +--------------+ |
| 115 | | 401 | | 116 | | 401 | |
| @@ -155,8 +156,8 @@ IBM BookE · 39 unmodified lines | |||
| 155 | Motorola/Freescale 8xx | 156 | Motorola/Freescale 8xx |
| 156 | ---------------------- | 157 | ---------------------- |
| 157 | 158 | ||
| 158 | - Software loaded with hardware assist. | 159 | - Software loaded with hardware assist. |
| 159 | - All 32 bit | 160 | - All 32 bit:: |
| 160 | 161 | ||
| 161 | +-------------+ | 162 | +-------------+ |
| 162 | | MPC8xx Core | | 163 | | MPC8xx Core | |
| @@ -166,9 +167,9 @@ Motorola/Freescale 8xx · 3 unmodified lines | |||
| 166 | Freescale BookE | 167 | Freescale BookE |
| 167 | --------------- | 168 | --------------- |
| 168 | 169 | ||
| 169 | - Software loaded TLB. | 170 | - Software loaded TLB. |
| 170 | - e6500 adds HW loaded indirect TLB entries. | 171 | - e6500 adds HW loaded indirect TLB entries. |
| 171 | - Mix of 32 & 64 bit | 172 | - Mix of 32 & 64 bit:: |
| 172 | 173 | ||
| 173 | +--------------+ | 174 | +--------------+ |
| 174 | | e200 | | 175 | | e200 | |
| @@ -207,8 +208,8 @@ Freescale BookE · 32 unmodified lines | |||
| 207 | IBM A2 core | 208 | IBM A2 core |
| 208 | ----------- | 209 | ----------- |
| 209 | 210 | ||
| 210 | - Book3E, software loaded TLB + HW loaded indirect TLB entries. | 211 | - Book3E, software loaded TLB + HW loaded indirect TLB entries. |
| 211 | - 64 bit | 212 | - 64 bit:: |
| 212 | 213 | ||
| 213 | +--------------+ +----------------+ | 214 | +--------------+ +----------------+ |
| 214 | | A2 core | --> | WSP | | 215 | | A2 core | --> | WSP | |
| @@ -1,3 +1,7 @@ | |||
| 1 | ============ | ||
| 2 | CPU Features | ||
| 3 | ============ | ||
| 4 | |||
| 1 | Hollis Blanchard <hollis@austin.ibm.com> | 5 | Hollis Blanchard <hollis@austin.ibm.com> |
| 2 | 5 Jun 2002 | 6 | 5 Jun 2002 |
| 3 | 7 | ||
| @@ -32,7 +36,7 @@ anyways). · 28 unmodified lines | |||
| 32 | After detecting the processor type, the kernel patches out sections of code | 36 | After detecting the processor type, the kernel patches out sections of code |
| 33 | that shouldn't be used by writing nop's over it. Using cpufeatures requires | 37 | that shouldn't be used by writing nop's over it. Using cpufeatures requires |
| 34 | just 2 macros (found in arch/powerpc/include/asm/cputable.h), as seen in head.S | 38 | just 2 macros (found in arch/powerpc/include/asm/cputable.h), as seen in head.S |
| 35 | transfer_to_handler: | 39 | transfer_to_handler:: |
| 36 | 40 | ||
| 37 | #ifdef CONFIG_ALTIVEC | 41 | #ifdef CONFIG_ALTIVEC |
| 38 | BEGIN_FTR_SECTION | 42 | BEGIN_FTR_SECTION |
| @@ -1,3 +1,4 @@ | |||
| 1 | ==================================== | ||
| 1 | Coherent Accelerator Interface (CXL) | 2 | Coherent Accelerator Interface (CXL) |
| 2 | ==================================== | 3 | ==================================== |
| 3 | 4 | ||
| @@ -21,6 +22,8 @@ Introduction · 17 unmodified lines | |||
| 21 | Hardware overview | 22 | Hardware overview |
| 22 | ================= | 23 | ================= |
| 23 | 24 | ||
| 25 | :: | ||
| 26 | |||
| 24 | POWER8/9 FPGA | 27 | POWER8/9 FPGA |
| 25 | +----------+ +---------+ | 28 | +----------+ +---------+ |
| 26 | | | | | | 29 | | | | | |
| @@ -59,14 +62,16 @@ Hardware overview · 32 unmodified lines | |||
| 59 | the fault. The context to which this fault is serviced is based on | 62 | the fault. The context to which this fault is serviced is based on |
| 60 | who owns that acceleration function. | 63 | who owns that acceleration function. |
| 61 | 64 | ||
| 62 | POWER8 <-----> PSL Version 8 is compliant to the CAIA Version 1.0. | 65 | - POWER8 and PSL Version 8 are compliant to the CAIA Version 1.0. |
| 63 | POWER9 <-----> PSL Version 9 is compliant to the CAIA Version 2.0. | 66 | - POWER9 and PSL Version 9 are compliant to the CAIA Version 2.0. |
| 67 | |||
| 64 | This PSL Version 9 provides new features such as: | 68 | This PSL Version 9 provides new features such as: |
| 69 | |||
| 65 | * Interaction with the nest MMU on the P9 chip. | 70 | * Interaction with the nest MMU on the P9 chip. |
| 66 | * Native DMA support. | 71 | * Native DMA support. |
| 67 | * Supports sending ASB_Notify messages for host thread wakeup. | 72 | * Supports sending ASB_Notify messages for host thread wakeup. |
| 68 | * Supports Atomic operations. | 73 | * Supports Atomic operations. |
| 69 | * .... | 74 | * etc. |
| 70 | 75 | ||
| 71 | Cards with a PSL9 won't work on a POWER8 system and cards with a | 76 | Cards with a PSL9 won't work on a POWER8 system and cards with a |
| 72 | PSL8 won't work on a POWER9 system. | 77 | PSL8 won't work on a POWER9 system. |
| @@ -147,7 +152,9 @@ User API · 74 unmodified lines | |||
| 147 | master devices. | 152 | master devices. |
| 148 | 153 | ||
| 149 | A userspace library libcxl is available here: | 154 | A userspace library libcxl is available here: |
| 155 | |||
| 150 | https://github.com/ibm-capi/libcxl | 156 | https://github.com/ibm-capi/libcxl |
| 157 | |||
| 151 | This provides a C interface to this kernel API. | 158 | This provides a C interface to this kernel API. |
| 152 | 159 | ||
| 153 | open | 160 | open |
| @@ -165,7 +172,8 @@ open · 11 unmodified lines | |||
| 165 | When all available contexts are allocated the open call will fail | 172 | When all available contexts are allocated the open call will fail |
| 166 | and return -ENOSPC. | 173 | and return -ENOSPC. |
| 167 | 174 | ||
| 168 | Note: IRQs need to be allocated for each context, which may limit | 175 | Note: |
| 176 | IRQs need to be allocated for each context, which may limit | ||
| 169 | the number of contexts that can be created, and therefore | 177 | the number of contexts that can be created, and therefore |
| 170 | how many times the device can be opened. The POWER8 CAPP | 178 | how many times the device can be opened. The POWER8 CAPP |
| 171 | supports 2040 IRQs and 3 are used by the kernel, so 2037 are | 179 | supports 2040 IRQs and 3 are used by the kernel, so 2037 are |
| @@ -186,7 +194,9 @@ ioctl · 14 unmodified lines | |||
| 186 | updated as userspace allocates and frees memory. This ioctl | 194 | updated as userspace allocates and frees memory. This ioctl |
| 187 | returns once the AFU context is started. | 195 | returns once the AFU context is started. |
| 188 | 196 | ||
| 189 | Takes a pointer to a struct cxl_ioctl_start_work: | 197 | Takes a pointer to a struct cxl_ioctl_start_work |
| 198 | |||
| 199 | :: | ||
| 190 | 200 | ||
| 191 | struct cxl_ioctl_start_work { | 201 | struct cxl_ioctl_start_work { |
| 192 | __u64 flags; | 202 | __u64 flags; |
| @@ -269,7 +279,7 @@ read · 76 unmodified lines | |||
| 269 | The buffer passed to read() must be at least 4K bytes. | 279 | The buffer passed to read() must be at least 4K bytes. |
| 270 | 280 | ||
| 271 | The result of the read will be a buffer of one or more events, | 281 | The result of the read will be a buffer of one or more events, |
| 272 | each event is of type struct cxl_event, of varying size. | 282 | each event is of type struct cxl_event, of varying size:: |
| 273 | 283 | ||
| 274 | struct cxl_event { | 284 | struct cxl_event { |
| 275 | struct cxl_event_header header; | 285 | struct cxl_event_header header; |
| @@ -280,7 +290,9 @@ read · 4 unmodified lines | |||
| 280 | }; | 290 | }; |
| 281 | }; | 291 | }; |
| 282 | 292 | ||
| 283 | The struct cxl_event_header is defined as: | 293 | The struct cxl_event_header is defined as |
| 294 | |||
| 295 | :: | ||
| 284 | 296 | ||
| 285 | struct cxl_event_header { | 297 | struct cxl_event_header { |
| 286 | __u16 type; | 298 | __u16 type; |
| @@ -307,7 +319,9 @@ read · 20 unmodified lines | |||
| 307 | For future extensions and padding. | 319 | For future extensions and padding. |
| 308 | 320 | ||
| 309 | If the event type is CXL_EVENT_AFU_INTERRUPT then the event | 321 | If the event type is CXL_EVENT_AFU_INTERRUPT then the event |
| 310 | structure is defined as: | 322 | structure is defined as |
| 323 | |||
| 324 | :: | ||
| 311 | 325 | ||
| 312 | struct cxl_event_afu_interrupt { | 326 | struct cxl_event_afu_interrupt { |
| 313 | __u16 flags; | 327 | __u16 flags; |
| @@ -326,7 +340,9 @@ read · 12 unmodified lines | |||
| 326 | For future extensions and padding. | 340 | For future extensions and padding. |
| 327 | 341 | ||
| 328 | If the event type is CXL_EVENT_DATA_STORAGE then the event | 342 | If the event type is CXL_EVENT_DATA_STORAGE then the event |
| 329 | structure is defined as: | 343 | structure is defined as |
| 344 | |||
| 345 | :: | ||
| 330 | 346 | ||
| 331 | struct cxl_event_data_storage { | 347 | struct cxl_event_data_storage { |
| 332 | __u16 flags; | 348 | __u16 flags; |
| @@ -356,7 +372,9 @@ read · 23 unmodified lines | |||
| 356 | For future extensions | 372 | For future extensions |
| 357 | 373 | ||
| 358 | If the event type is CXL_EVENT_AFU_ERROR then the event structure | 374 | If the event type is CXL_EVENT_AFU_ERROR then the event structure |
| 359 | is defined as: | 375 | is defined as |
| 376 | |||
| 377 | :: | ||
| 360 | 378 | ||
| 361 | struct cxl_event_afu_error { | 379 | struct cxl_event_afu_error { |
| 362 | __u16 flags; | 380 | __u16 flags; |
| @@ -393,15 +411,15 @@ open · 30 unmodified lines | |||
| 393 | ioctl | 411 | ioctl |
| 394 | ----- | 412 | ----- |
| 395 | 413 | ||
| 396 | CXL_IOCTL_DOWNLOAD_IMAGE: | 414 | CXL_IOCTL_DOWNLOAD_IMAGE / CXL_IOCTL_VALIDATE_IMAGE: |
| 397 | CXL_IOCTL_VALIDATE_IMAGE: | ||
| 398 | Starts and controls flashing a new FPGA image. Partial | 415 | Starts and controls flashing a new FPGA image. Partial |
| 399 | reconfiguration is not supported (yet), so the image must contain | 416 | reconfiguration is not supported (yet), so the image must contain |
| 400 | a copy of the PSL and AFU(s). Since an image can be quite large, | 417 | a copy of the PSL and AFU(s). Since an image can be quite large, |
| 401 | the caller may have to iterate, splitting the image in smaller | 418 | the caller may have to iterate, splitting the image in smaller |
| 402 | chunks. | 419 | chunks. |
| 403 | 420 | ||
| 404 | Takes a pointer to a struct cxl_adapter_image: | 421 | Takes a pointer to a struct cxl_adapter_image:: |
| 422 | |||
| 405 | struct cxl_adapter_image { | 423 | struct cxl_adapter_image { |
| 406 | __u64 flags; | 424 | __u64 flags; |
| 407 | __u64 data; | 425 | __u64 data; |
| @@ -442,7 +460,7 @@ Udev rules · 34 unmodified lines | |||
| 442 | The following udev rules could be used to create a symlink to the | 460 | The following udev rules could be used to create a symlink to the |
| 443 | most logical chardev to use in any programming mode (afuX.Yd for | 461 | most logical chardev to use in any programming mode (afuX.Yd for |
| 444 | dedicated, afuX.Ys for afu directed), since the API is virtually | 462 | dedicated, afuX.Ys for afu directed), since the API is virtually |
| 445 | identical for each: | 463 | identical for each:: |
| 446 | 464 | ||
| 447 | SUBSYSTEM=="cxl", ATTRS{mode}=="dedicated_process", SYMLINK="cxl/%b" | 465 | SUBSYSTEM=="cxl", ATTRS{mode}=="dedicated_process", SYMLINK="cxl/%b" |
| 448 | SUBSYSTEM=="cxl", ATTRS{mode}=="afu_directed", \ | 466 | SUBSYSTEM=="cxl", ATTRS{mode}=="afu_directed", \ |
| @@ -1,3 +1,7 @@ | |||
| 1 | ================================ | ||
| 2 | Coherent Accelerator (CXL) Flash | ||
| 3 | ================================ | ||
| 4 | |||
| 1 | Introduction | 5 | Introduction |
| 2 | ============ | 6 | ============ |
| 3 | 7 | ||
| @@ -28,7 +32,7 @@ Introduction · 24 unmodified lines | |||
| 28 | responsible for the initialization of the adapter, setting up the | 32 | responsible for the initialization of the adapter, setting up the |
| 29 | special path for user space access, and performing error recovery. It | 33 | special path for user space access, and performing error recovery. It |
| 30 | communicates directly the Flash Accelerator Functional Unit (AFU) | 34 | communicates directly the Flash Accelerator Functional Unit (AFU) |
| 31 | as described in Documentation/powerpc/cxl.txt. | 35 | as described in Documentation/powerpc/cxl.rst. |
| 32 | 36 | ||
| 33 | The cxlflash driver supports two, mutually exclusive, modes of | 37 | The cxlflash driver supports two, mutually exclusive, modes of |
| 34 | operation at the device (LUN) level: | 38 | operation at the device (LUN) level: |
| @@ -58,7 +62,7 @@ Overview · 23 unmodified lines | |||
| 58 | 62 | ||
| 59 | The CXL Flash Adapter Driver establishes a master context with the | 63 | The CXL Flash Adapter Driver establishes a master context with the |
| 60 | AFU. It uses memory mapped I/O (MMIO) for this control and setup. The | 64 | AFU. It uses memory mapped I/O (MMIO) for this control and setup. The |
| 61 | Adapter Problem Space Memory Map looks like this: | 65 | Adapter Problem Space Memory Map looks like this:: |
| 62 | 66 | ||
| 63 | +-------------------------------+ | 67 | +-------------------------------+ |
| 64 | | 512 * 64 KB User MMIO | | 68 | | 512 * 64 KB User MMIO | |
| @@ -375,7 +379,7 @@ CXL Flash Driver Host IOCTLs · 310 unmodified lines | |||
| 375 | Each host adapter instance that is supported by the cxlflash driver | 379 | Each host adapter instance that is supported by the cxlflash driver |
| 376 | has a special character device associated with it to enable a set of | 380 | has a special character device associated with it to enable a set of |
| 377 | host management function. These character devices are hosted in a | 381 | host management function. These character devices are hosted in a |
| 378 | class dedicated for cxlflash and can be accessed via /dev/cxlflash/*. | 382 | class dedicated for cxlflash and can be accessed via `/dev/cxlflash/*`. |
| 379 | 383 | ||
| 380 | Applications can be written to perform various functions using the | 384 | Applications can be written to perform various functions using the |
| 381 | host ioctl APIs below. | 385 | host ioctl APIs below. |
| @@ -1,10 +1,11 @@ | |||
| 1 | ===================== | ||
| 1 | DAWR issues on POWER9 | 2 | DAWR issues on POWER9 |
| 2 | ============================ | 3 | ===================== |
| 3 | 4 | ||
| 4 | On POWER9 the Data Address Watchpoint Register (DAWR) can cause a checkstop | 5 | On POWER9 the Data Address Watchpoint Register (DAWR) can cause a checkstop |
| 5 | if it points to cache inhibited (CI) memory. Currently Linux has no way to | 6 | if it points to cache inhibited (CI) memory. Currently Linux has no way to |
| 6 | disinguish CI memory when configuring the DAWR, so (for now) the DAWR is | 7 | disinguish CI memory when configuring the DAWR, so (for now) the DAWR is |
| 7 | disabled by this commit: | 8 | disabled by this commit:: |
| 8 | 9 | ||
| 9 | commit 9654153158d3e0684a1bdb76dbababdb7111d5a0 | 10 | commit 9654153158d3e0684a1bdb76dbababdb7111d5a0 |
| 10 | Author: Michael Neuling <mikey@neuling.org> | 11 | Author: Michael Neuling <mikey@neuling.org> |
| @@ -12,7 +13,7 @@ disabled by this commit: · 1 unmodified line | |||
| 12 | powerpc: Disable DAWR in the base POWER9 CPU features | 13 | powerpc: Disable DAWR in the base POWER9 CPU features |
| 13 | 14 | ||
| 14 | Technical Details: | 15 | Technical Details: |
| 15 | ============================ | 16 | ================== |
| 16 | 17 | ||
| 17 | DAWR has 6 different ways of being set. | 18 | DAWR has 6 different ways of being set. |
| 18 | 1) ptrace | 19 | 1) ptrace |
| @@ -37,7 +38,7 @@ DAWR on the migration. · 18 unmodified lines | |||
| 37 | For xmon, the 'bd' command will return an error on P9. | 38 | For xmon, the 'bd' command will return an error on P9. |
| 38 | 39 | ||
| 39 | Consequences for users | 40 | Consequences for users |
| 40 | ============================ | 41 | ====================== |
| 41 | 42 | ||
| 42 | For GDB watchpoints (ie 'watch' command) on POWER9 bare metal , GDB | 43 | For GDB watchpoints (ie 'watch' command) on POWER9 bare metal , GDB |
| 43 | will accept the command. Unfortunately since there is no hardware | 44 | will accept the command. Unfortunately since there is no hardware |
| @@ -57,8 +58,8 @@ trapped in GDB. The watchpoint is remembered, so if the guest is · 13 unmodified lines | |||
| 57 | migrated back to the POWER8 host, it will start working again. | 58 | migrated back to the POWER8 host, it will start working again. |
| 58 | 59 | ||
| 59 | Force enabling the DAWR | 60 | Force enabling the DAWR |
| 60 | ============================= | 61 | ======================= |
| 61 | Kernels (since ~v5.2) have an option to force enable the DAWR via: | 62 | Kernels (since ~v5.2) have an option to force enable the DAWR via:: |
| 62 | 63 | ||
| 63 | echo Y > /sys/kernel/debug/powerpc/dawr_enable_dangerous | 64 | echo Y > /sys/kernel/debug/powerpc/dawr_enable_dangerous |
| 64 | 65 | ||
| @@ -86,5 +87,7 @@ dawr_enable_dangerous file will fail if the hypervisor doesn't support · 21 unmodified lines | |||
| 86 | writing the DAWR. | 87 | writing the DAWR. |
| 87 | 88 | ||
| 88 | To double check the DAWR is working, run this kernel selftest: | 89 | To double check the DAWR is working, run this kernel selftest: |
| 90 | |||
| 89 | tools/testing/selftests/powerpc/ptrace/ptrace-hwbreak.c | 91 | tools/testing/selftests/powerpc/ptrace/ptrace-hwbreak.c |
| 92 | |||
| 90 | Any errors/failures/skips mean something is wrong. | 93 | Any errors/failures/skips mean something is wrong. |
| @@ -1,5 +1,6 @@ | |||
| 1 | DSCR (Data Stream Control Register) | 1 | =================================== |
| 2 | ================================================ | 2 | DSCR (Data Stream Control Register) |
| 3 | =================================== | ||
| 3 | 4 | ||
| 4 | DSCR register in powerpc allows user to have some control of prefetch of data | 5 | DSCR register in powerpc allows user to have some control of prefetch of data |
| 5 | stream in the processor. Please refer to the ISA documents or related manual | 6 | stream in the processor. Please refer to the ISA documents or related manual |
| @@ -10,14 +11,17 @@ user interface. · 4 unmodified lines | |||
| 10 | 11 | ||
| 11 | (A) Data Structures: | 12 | (A) Data Structures: |
| 12 | 13 | ||
| 13 | (1) thread_struct: | 14 | (1) thread_struct:: |
| 15 | |||
| 14 | dscr /* Thread DSCR value */ | 16 | dscr /* Thread DSCR value */ |
| 15 | dscr_inherit /* Thread has changed default DSCR */ | 17 | dscr_inherit /* Thread has changed default DSCR */ |
| 16 | 18 | ||
| 17 | (2) PACA: | 19 | (2) PACA:: |
| 20 | |||
| 18 | dscr_default /* per-CPU DSCR default value */ | 21 | dscr_default /* per-CPU DSCR default value */ |
| 19 | 22 | ||
| 20 | (3) sysfs.c: | 23 | (3) sysfs.c:: |
| 24 | |||
| 21 | dscr_default /* System DSCR default value */ | 25 | dscr_default /* System DSCR default value */ |
| 22 | 26 | ||
| 23 | (B) Scheduler Changes: | 27 | (B) Scheduler Changes: |
| @@ -35,8 +39,8 @@ user interface. · 11 unmodified lines | |||
| 35 | 39 | ||
| 36 | (C) SYSFS Interface: | 40 | (C) SYSFS Interface: |
| 37 | 41 | ||
| 38 | Global DSCR default: /sys/devices/system/cpu/dscr_default | 42 | - Global DSCR default: /sys/devices/system/cpu/dscr_default |
| 39 | CPU specific DSCR default: /sys/devices/system/cpu/cpuN/dscr | 43 | - CPU specific DSCR default: /sys/devices/system/cpu/cpuN/dscr |
| 40 | 44 | ||
| 41 | Changing the global DSCR default in the sysfs will change all the CPU | 45 | Changing the global DSCR default in the sysfs will change all the CPU |
| 42 | specific DSCR defaults immediately in their PACA structures. Again if | 46 | specific DSCR defaults immediately in their PACA structures. Again if |
| @@ -1,10 +1,10 @@ | |||
| 1 | ========================== | ||
| 2 | PCI Bus EEH Error Recovery | ||
| 3 | ========================== | ||
| 1 | 4 | ||
| 5 | Linas Vepstas <linas@austin.ibm.com> | ||
| 2 | 6 | ||
| 3 | PCI Bus EEH Error Recovery | 7 | 12 January 2005 |
| 4 | -------------------------- | ||
| 5 | Linas Vepstas | ||
| 6 | <linas@austin.ibm.com> | ||
| 7 | 12 January 2005 | ||
| 8 | 8 | ||
| 9 | 9 | ||
| 10 | Overview: | 10 | Overview: |
| @@ -143,17 +143,17 @@ seen in /proc/ppc64/eeh (subject to change). Normally, almost · 132 unmodified lines | |||
| 143 | all of these occur during boot, when the PCI bus is scanned, where | 143 | all of these occur during boot, when the PCI bus is scanned, where |
| 144 | a large number of 0xff reads are part of the bus scan procedure. | 144 | a large number of 0xff reads are part of the bus scan procedure. |
| 145 | 145 | ||
| 146 | If a frozen slot is detected, code in | 146 | If a frozen slot is detected, code in |
| 147 | arch/powerpc/platforms/pseries/eeh.c will print a stack trace to | 147 | arch/powerpc/platforms/pseries/eeh.c will print a stack trace to |
| 148 | syslog (/var/log/messages). This stack trace has proven to be very | 148 | syslog (/var/log/messages). This stack trace has proven to be very |
| 149 | useful to device-driver authors for finding out at what point the EEH | 149 | useful to device-driver authors for finding out at what point the EEH |
| 150 | error was detected, as the error itself usually occurs slightly | 150 | error was detected, as the error itself usually occurs slightly |
| 151 | beforehand. | 151 | beforehand. |
| 152 | 152 | ||
| 153 | Next, it uses the Linux kernel notifier chain/work queue mechanism to | 153 | Next, it uses the Linux kernel notifier chain/work queue mechanism to |
| 154 | allow any interested parties to find out about the failure. Device | 154 | allow any interested parties to find out about the failure. Device |
| 155 | drivers, or other parts of the kernel, can use | 155 | drivers, or other parts of the kernel, can use |
| 156 | eeh_register_notifier(struct notifier_block *) to find out about EEH | 156 | `eeh_register_notifier(struct notifier_block *)` to find out about EEH |
| 157 | events. The event will include a pointer to the pci device, the | 157 | events. The event will include a pointer to the pci device, the |
| 158 | device node and some state info. Receivers of the event can "do as | 158 | device node and some state info. Receivers of the event can "do as |
| 159 | they wish"; the default handler will be described further in this | 159 | they wish"; the default handler will be described further in this |
| @@ -162,10 +162,13 @@ section. · 2 unmodified lines | |||
| 162 | To assist in the recovery of the device, eeh.c exports the | 162 | To assist in the recovery of the device, eeh.c exports the |
| 163 | following functions: | 163 | following functions: |
| 164 | 164 | ||
| 165 | rtas_set_slot_reset() -- assert the PCI #RST line for 1/8th of a second | 165 | rtas_set_slot_reset() |
| 166 | rtas_configure_bridge() -- ask firmware to configure any PCI bridges | 166 | assert the PCI #RST line for 1/8th of a second |
| 167 | rtas_configure_bridge() | ||
| 168 | ask firmware to configure any PCI bridges | ||
| 167 | located topologically under the pci slot. | 169 | located topologically under the pci slot. |
| 168 | eeh_save_bars() and eeh_restore_bars(): save and restore the PCI | 170 | eeh_save_bars() and eeh_restore_bars(): |
| 171 | save and restore the PCI | ||
| 169 | config-space info for a device and any devices under it. | 172 | config-space info for a device and any devices under it. |
| 170 | 173 | ||
| 171 | 174 | ||
| @@ -191,7 +194,7 @@ events get delivered to user-space scripts. · 19 unmodified lines | |||
| 191 | 194 | ||
| 192 | Following is an example sequence of events that cause a device driver | 195 | Following is an example sequence of events that cause a device driver |
| 193 | close function to be called during the first phase of an EEH reset. | 196 | close function to be called during the first phase of an EEH reset. |
| 194 | The following sequence is an example of the pcnet32 device driver. | 197 | The following sequence is an example of the pcnet32 device driver:: |
| 195 | 198 | ||
| 196 | rpa_php_unconfig_pci_adapter (struct slot *) // in rpaphp_pci.c | 199 | rpa_php_unconfig_pci_adapter (struct slot *) // in rpaphp_pci.c |
| 197 | { | 200 | { |
| @@ -241,53 +244,54 @@ The following sequence is an example of the pcnet32 device driver. · 43 unmodified lines | |||
| 241 | }}}}}} | 244 | }}}}}} |
| 242 | 245 | ||
| 243 | 246 | ||
| 244 | in drivers/pci/pci_driver.c, | 247 | in drivers/pci/pci_driver.c, |
| 245 | struct device_driver->remove() is just pci_device_remove() | 248 | struct device_driver->remove() is just pci_device_remove() |
| 246 | which calls struct pci_driver->remove() which is pcnet32_remove_one() | 249 | which calls struct pci_driver->remove() which is pcnet32_remove_one() |
| 247 | which calls unregister_netdev() (in net/core/dev.c) | 250 | which calls unregister_netdev() (in net/core/dev.c) |
| 248 | which calls dev_close() (in net/core/dev.c) | 251 | which calls dev_close() (in net/core/dev.c) |
| 249 | which calls dev->stop() which is pcnet32_close() | 252 | which calls dev->stop() which is pcnet32_close() |
| 250 | which then does the appropriate shutdown. | 253 | which then does the appropriate shutdown. |
| 251 | 254 | ||
| 252 | --- | 255 | --- |
| 256 | |||
| 253 | Following is the analogous stack trace for events sent to user-space | 257 | Following is the analogous stack trace for events sent to user-space |
| 254 | when the pci device is unconfigured. | 258 | when the pci device is unconfigured:: |
| 255 | 259 | ||
| 256 | rpa_php_unconfig_pci_adapter() { // in rpaphp_pci.c | 260 | rpa_php_unconfig_pci_adapter() { // in rpaphp_pci.c |
| 257 | calls | ||
| 258 | pci_remove_bus_device (struct pci_dev *) { // in /drivers/pci/remove.c | ||
| 259 | calls | 261 | calls |
| 260 | pci_destroy_dev (struct pci_dev *) { | 262 | pci_remove_bus_device (struct pci_dev *) { // in /drivers/pci/remove.c |
| 261 | calls | 263 | calls |
| 262 | device_unregister (&dev->dev) { // in /drivers/base/core.c | 264 | pci_destroy_dev (struct pci_dev *) { |
| 263 | calls | 265 | calls |
| 264 | device_del(struct device * dev) { // in /drivers/base/core.c | 266 | device_unregister (&dev->dev) { // in /drivers/base/core.c |
| 265 | calls | 267 | calls |
| 266 | kobject_del() { //in /libs/kobject.c | 268 | device_del(struct device * dev) { // in /drivers/base/core.c |
| 267 | calls | 269 | calls |
| 268 | kobject_uevent() { // in /libs/kobject.c | 270 | kobject_del() { //in /libs/kobject.c |
| 269 | calls | 271 | calls |
| 270 | kset_uevent() { // in /lib/kobject.c | 272 | kobject_uevent() { // in /libs/kobject.c |
| 271 | calls | 273 | calls |
| 272 | kset->uevent_ops->uevent() // which is really just | 274 | kset_uevent() { // in /lib/kobject.c |
| 273 | a call to | ||
| 274 | dev_uevent() { // in /drivers/base/core.c | ||
| 275 | calls | 275 | calls |
| 276 | dev->bus->uevent() which is really just a call to | 276 | kset->uevent_ops->uevent() // which is really just |
| 277 | pci_uevent () { // in drivers/pci/hotplug.c | 277 | a call to |
| 278 | which prints device name, etc.... | 278 | dev_uevent() { // in /drivers/base/core.c |
| 279 | calls | ||
| 280 | dev->bus->uevent() which is really just a call to | ||
| 281 | pci_uevent () { // in drivers/pci/hotplug.c | ||
| 282 | which prints device name, etc.... | ||
| 283 | } | ||
| 279 | } | 284 | } |
| 280 | } | 285 | then kobject_uevent() sends a netlink uevent to userspace |
| 281 | then kobject_uevent() sends a netlink uevent to userspace | 286 | --> userspace uevent |
| 282 | --> userspace uevent | 287 | (during early boot, nobody listens to netlink events and |
| 283 | (during early boot, nobody listens to netlink events and | 288 | kobject_uevent() executes uevent_helper[], which runs the |
| 284 | kobject_uevent() executes uevent_helper[], which runs the | 289 | event process /sbin/hotplug) |
| 285 | event process /sbin/hotplug) | 290 | } |
| 286 | } | 291 | } |
| 287 | } | 292 | kobject_del() then calls sysfs_remove_dir(), which would |
| 288 | kobject_del() then calls sysfs_remove_dir(), which would | 293 | trigger any user-space daemon that was watching /sysfs, |
| 289 | trigger any user-space daemon that was watching /sysfs, | 294 | and notice the delete event. |
| 290 | and notice the delete event. | ||
| 291 | 295 | ||
| 292 | 296 | ||
| 293 | Pro's and Con's of the Current Design | 297 | Pro's and Con's of the Current Design |
| @@ -299,12 +303,12 @@ individual device drivers, so that the current design throws a wide net. · 5 unmodified lines | |||
| 299 | The biggest negative of the design is that it potentially disturbs | 303 | The biggest negative of the design is that it potentially disturbs |
| 300 | network daemons and file systems that didn't need to be disturbed. | 304 | network daemons and file systems that didn't need to be disturbed. |
| 301 | 305 | ||
| 302 | -- A minor complaint is that resetting the network card causes | 306 | - A minor complaint is that resetting the network card causes |
| 303 | user-space back-to-back ifdown/ifup burps that potentially disturb | 307 | user-space back-to-back ifdown/ifup burps that potentially disturb |
| 304 | network daemons, that didn't need to even know that the pci | 308 | network daemons, that didn't need to even know that the pci |
| 305 | card was being rebooted. | 309 | card was being rebooted. |
| 306 | 310 | ||
| 307 | -- A more serious concern is that the same reset, for SCSI devices, | 311 | - A more serious concern is that the same reset, for SCSI devices, |
| 308 | causes havoc to mounted file systems. Scripts cannot post-facto | 312 | causes havoc to mounted file systems. Scripts cannot post-facto |
| 309 | unmount a file system without flushing pending buffers, but this | 313 | unmount a file system without flushing pending buffers, but this |
| 310 | is impossible, because I/O has already been stopped. Thus, | 314 | is impossible, because I/O has already been stopped. Thus, |
| @@ -322,7 +326,7 @@ network daemons and file systems that didn't need to be disturbed. · 11 unmodified lines | |||
| 322 | from the block layer. It would be very natural to add an EEH | 326 | from the block layer. It would be very natural to add an EEH |
| 323 | reset into this chain of events. | 327 | reset into this chain of events. |
| 324 | 328 | ||
| 325 | -- If a SCSI error occurs for the root device, all is lost unless | 329 | - If a SCSI error occurs for the root device, all is lost unless |
| 326 | the sysadmin had the foresight to run /bin, /sbin, /etc, /var | 330 | the sysadmin had the foresight to run /bin, /sbin, /etc, /var |
| 327 | and so on, out of ramdisk/tmpfs. | 331 | and so on, out of ramdisk/tmpfs. |
| 328 | 332 | ||
| @@ -330,5 +334,3 @@ network daemons and file systems that didn't need to be disturbed. · 1 unmodified line | |||
| 330 | Conclusions | 334 | Conclusions |
| 331 | ----------- | 335 | ----------- |
| 332 | There's forward progress ... | 336 | There's forward progress ... |
| 333 | |||
| 334 | |||
| @@ -1,7 +1,8 @@ | |||
| 1 | ====================== | ||
| 2 | Firmware-Assisted Dump | ||
| 3 | ====================== | ||
| 1 | 4 | ||
| 2 | Firmware-Assisted Dump | 5 | July 2011 |
| 3 | ------------------------ | ||
| 4 | July 2011 | ||
| 5 | 6 | ||
| 6 | The goal of firmware-assisted dump is to enable the dump of | 7 | The goal of firmware-assisted dump is to enable the dump of |
| 7 | a crashed system, and to do so from a fully-reset system, and | 8 | a crashed system, and to do so from a fully-reset system, and |
| @@ -27,11 +28,11 @@ in production use. · 19 unmodified lines | |||
| 27 | Comparing with kdump or other strategies, firmware-assisted | 28 | Comparing with kdump or other strategies, firmware-assisted |
| 28 | dump offers several strong, practical advantages: | 29 | dump offers several strong, practical advantages: |
| 29 | 30 | ||
| 30 | -- Unlike kdump, the system has been reset, and loaded | 31 | - Unlike kdump, the system has been reset, and loaded |
| 31 | with a fresh copy of the kernel. In particular, | 32 | with a fresh copy of the kernel. In particular, |
| 32 | PCI and I/O devices have been reinitialized and are | 33 | PCI and I/O devices have been reinitialized and are |
| 33 | in a clean, consistent state. | 34 | in a clean, consistent state. |
| 34 | -- Once the dump is copied out, the memory that held the dump | 35 | - Once the dump is copied out, the memory that held the dump |
| 35 | is immediately available to the running kernel. And therefore, | 36 | is immediately available to the running kernel. And therefore, |
| 36 | unlike kdump, fadump doesn't need a 2nd reboot to get back | 37 | unlike kdump, fadump doesn't need a 2nd reboot to get back |
| 37 | the system to the production configuration. | 38 | the system to the production configuration. |
| @@ -40,17 +41,18 @@ The above can only be accomplished by coordination with, · 2 unmodified lines | |||
| 40 | and assistance from the Power firmware. The procedure is | 41 | and assistance from the Power firmware. The procedure is |
| 41 | as follows: | 42 | as follows: |
| 42 | 43 | ||
| 43 | -- The first kernel registers the sections of memory with the | 44 | - The first kernel registers the sections of memory with the |
| 44 | Power firmware for dump preservation during OS initialization. | 45 | Power firmware for dump preservation during OS initialization. |
| 45 | These registered sections of memory are reserved by the first | 46 | These registered sections of memory are reserved by the first |
| 46 | kernel during early boot. | 47 | kernel during early boot. |
| 47 | 48 | ||
| 48 | -- When a system crashes, the Power firmware will save | 49 | - When a system crashes, the Power firmware will save |
| 49 | the low memory (boot memory of size larger of 5% of system RAM | 50 | the low memory (boot memory of size larger of 5% of system RAM |
| 50 | or 256MB) of RAM to the previous registered region. It will | 51 | or 256MB) of RAM to the previous registered region. It will |
| 51 | also save system registers, and hardware PTE's. | 52 | also save system registers, and hardware PTE's. |
| 52 | 53 | ||
| 53 | NOTE: The term 'boot memory' means size of the low memory chunk | 54 | NOTE: |
| 55 | The term 'boot memory' means size of the low memory chunk | ||
| 54 | that is required for a kernel to boot successfully when | 56 | that is required for a kernel to boot successfully when |
| 55 | booted with restricted memory. By default, the boot memory | 57 | booted with restricted memory. By default, the boot memory |
| 56 | size will be the larger of 5% of system RAM or 256MB. | 58 | size will be the larger of 5% of system RAM or 256MB. |
| @@ -64,12 +66,12 @@ as follows: · 7 unmodified lines | |||
| 64 | as fadump uses a predefined offset to reserve memory | 66 | as fadump uses a predefined offset to reserve memory |
| 65 | for boot memory dump preservation in case of a crash. | 67 | for boot memory dump preservation in case of a crash. |
| 66 | 68 | ||
| 67 | -- After the low memory (boot memory) area has been saved, the | 69 | - After the low memory (boot memory) area has been saved, the |
| 68 | firmware will reset PCI and other hardware state. It will | 70 | firmware will reset PCI and other hardware state. It will |
| 69 | *not* clear the RAM. It will then launch the bootloader, as | 71 | *not* clear the RAM. It will then launch the bootloader, as |
| 70 | normal. | 72 | normal. |
| 71 | 73 | ||
| 72 | -- The freshly booted kernel will notice that there is a new | 74 | - The freshly booted kernel will notice that there is a new |
| 73 | node (ibm,dump-kernel) in the device tree, indicating that | 75 | node (ibm,dump-kernel) in the device tree, indicating that |
| 74 | there is crash data available from a previous boot. During | 76 | there is crash data available from a previous boot. During |
| 75 | the early boot OS will reserve rest of the memory above | 77 | the early boot OS will reserve rest of the memory above |
| @@ -77,17 +79,18 @@ as follows: · 1 unmodified line | |||
| 77 | size. This will make sure that the second kernel will not | 79 | size. This will make sure that the second kernel will not |
| 78 | touch any of the dump memory area. | 80 | touch any of the dump memory area. |
| 79 | 81 | ||
| 80 | -- User-space tools will read /proc/vmcore to obtain the contents | 82 | - User-space tools will read /proc/vmcore to obtain the contents |
| 81 | of memory, which holds the previous crashed kernel dump in ELF | 83 | of memory, which holds the previous crashed kernel dump in ELF |
| 82 | format. The userspace tools may copy this info to disk, or | 84 | format. The userspace tools may copy this info to disk, or |
| 83 | network, nas, san, iscsi, etc. as desired. | 85 | network, nas, san, iscsi, etc. as desired. |
| 84 | 86 | ||
| 85 | -- Once the userspace tool is done saving dump, it will echo | 87 | - Once the userspace tool is done saving dump, it will echo |
| 86 | '1' to /sys/kernel/fadump_release_mem to release the reserved | 88 | '1' to /sys/kernel/fadump_release_mem to release the reserved |
| 87 | memory back to general use, except the memory required for | 89 | memory back to general use, except the memory required for |
| 88 | next firmware-assisted dump registration. | 90 | next firmware-assisted dump registration. |
| 89 | 91 | ||
| 90 | e.g. | 92 | e.g.:: |
| 93 | |||
| 91 | # echo 1 > /sys/kernel/fadump_release_mem | 94 | # echo 1 > /sys/kernel/fadump_release_mem |
| 92 | 95 | ||
| 93 | Please note that the firmware-assisted dump feature | 96 | Please note that the firmware-assisted dump feature |
| @@ -95,7 +98,7 @@ is only available on Power6 and above systems with recent · 1 unmodified line | |||
| 95 | firmware versions. | 98 | firmware versions. |
| 96 | 99 | ||
| 97 | Implementation details: | 100 | Implementation details: |
| 98 | ---------------------- | 101 | ----------------------- |
| 99 | 102 | ||
| 100 | During boot, a check is made to see if firmware supports | 103 | During boot, a check is made to see if firmware supports |
| 101 | this feature on that particular machine. If it does, then | 104 | this feature on that particular machine. If it does, then |
| @@ -121,7 +124,7 @@ Allocator (CMA) for memory reservation if CMA is configured for kernel. · 19 unmodified lines | |||
| 121 | With CMA reservation this memory will be available for applications to | 124 | With CMA reservation this memory will be available for applications to |
| 122 | use it, while kernel is prevented from using it. With this fadump will | 125 | use it, while kernel is prevented from using it. With this fadump will |
| 123 | still be able to capture all of the kernel memory and most of the user | 126 | still be able to capture all of the kernel memory and most of the user |
| 124 | space memory except the user pages that were present in CMA region. | 127 | space memory except the user pages that were present in CMA region:: |
| 125 | 128 | ||
| 126 | o Memory Reservation during first kernel | 129 | o Memory Reservation during first kernel |
| 127 | 130 | ||
| @@ -166,7 +169,7 @@ The tools to examine the dump will be same as the ones · 38 unmodified lines | |||
| 166 | used for kdump. | 169 | used for kdump. |
| 167 | 170 | ||
| 168 | How to enable firmware-assisted dump (fadump): | 171 | How to enable firmware-assisted dump (fadump): |
| 169 | ------------------------------------- | 172 | ---------------------------------------------- |
| 170 | 173 | ||
| 171 | 1. Set config option CONFIG_FA_DUMP=y and build kernel. | 174 | 1. Set config option CONFIG_FA_DUMP=y and build kernel. |
| 172 | 2. Boot into linux kernel with 'fadump=on' kernel cmdline option. | 175 | 2. Boot into linux kernel with 'fadump=on' kernel cmdline option. |
| @@ -177,19 +180,20 @@ How to enable firmware-assisted dump (fadump): · 4 unmodified lines | |||
| 177 | to specify size of the memory to reserve for boot memory dump | 180 | to specify size of the memory to reserve for boot memory dump |
| 178 | preservation. | 181 | preservation. |
| 179 | 182 | ||
| 180 | NOTE: 1. 'fadump_reserve_mem=' parameter has been deprecated. Instead | 183 | NOTE: |
| 181 | use 'crashkernel=' to specify size of the memory to reserve | 184 | 1. 'fadump_reserve_mem=' parameter has been deprecated. Instead |
| 182 | for boot memory dump preservation. | 185 | use 'crashkernel=' to specify size of the memory to reserve |
| 183 | 2. If firmware-assisted dump fails to reserve memory then it | 186 | for boot memory dump preservation. |
| 184 | will fallback to existing kdump mechanism if 'crashkernel=' | 187 | 2. If firmware-assisted dump fails to reserve memory then it |
| 185 | option is set at kernel cmdline. | 188 | will fallback to existing kdump mechanism if 'crashkernel=' |
| 186 | 3. if user wants to capture all of user space memory and ok with | 189 | option is set at kernel cmdline. |
| 187 | reserved memory not available to production system, then | 190 | 3. if user wants to capture all of user space memory and ok with |
| 188 | 'fadump=nocma' kernel parameter can be used to fallback to | 191 | reserved memory not available to production system, then |
| 189 | old behaviour. | 192 | 'fadump=nocma' kernel parameter can be used to fallback to |
| 193 | old behaviour. | ||
| 190 | 194 | ||
| 191 | Sysfs/debugfs files: | 195 | Sysfs/debugfs files: |
| 192 | ------------ | 196 | -------------------- |
| 193 | 197 | ||
| 194 | Firmware-assisted dump feature uses sysfs file system to hold | 198 | Firmware-assisted dump feature uses sysfs file system to hold |
| 195 | the control files and debugfs file to display memory reserved region. | 199 | the control files and debugfs file to display memory reserved region. |
| @@ -197,20 +201,20 @@ the control files and debugfs file to display memory reserved region. · 1 unmodified line | |||
| 197 | Here is the list of files under kernel sysfs: | 201 | Here is the list of files under kernel sysfs: |
| 198 | 202 | ||
| 199 | /sys/kernel/fadump_enabled | 203 | /sys/kernel/fadump_enabled |
| 200 | |||
| 201 | This is used to display the fadump status. | 204 | This is used to display the fadump status. |
| 202 | 0 = fadump is disabled | 205 | |
| 203 | 1 = fadump is enabled | 206 | - 0 = fadump is disabled |
| 207 | - 1 = fadump is enabled | ||
| 204 | 208 | ||
| 205 | This interface can be used by kdump init scripts to identify if | 209 | This interface can be used by kdump init scripts to identify if |
| 206 | fadump is enabled in the kernel and act accordingly. | 210 | fadump is enabled in the kernel and act accordingly. |
| 207 | 211 | ||
| 208 | /sys/kernel/fadump_registered | 212 | /sys/kernel/fadump_registered |
| 209 | |||
| 210 | This is used to display the fadump registration status as well | 213 | This is used to display the fadump registration status as well |
| 211 | as to control (start/stop) the fadump registration. | 214 | as to control (start/stop) the fadump registration. |
| 212 | 0 = fadump is not registered. | 215 | |
| 213 | 1 = fadump is registered and ready to handle system crash. | 216 | - 0 = fadump is not registered. |
| 217 | - 1 = fadump is registered and ready to handle system crash. | ||
| 214 | 218 | ||
| 215 | To register fadump echo 1 > /sys/kernel/fadump_registered and | 219 | To register fadump echo 1 > /sys/kernel/fadump_registered and |
| 216 | echo 0 > /sys/kernel/fadump_registered for un-register and stop the | 220 | echo 0 > /sys/kernel/fadump_registered for un-register and stop the |
| @@ -219,13 +223,12 @@ Here is the list of files under kernel sysfs: · 2 unmodified lines | |||
| 219 | easily integrated with kdump service start/stop. | 223 | easily integrated with kdump service start/stop. |
| 220 | 224 | ||
| 221 | /sys/kernel/fadump_release_mem | 225 | /sys/kernel/fadump_release_mem |
| 222 | |||
| 223 | This file is available only when fadump is active during | 226 | This file is available only when fadump is active during |
| 224 | second kernel. This is used to release the reserved memory | 227 | second kernel. This is used to release the reserved memory |
| 225 | region that are held for saving crash dump. To release the | 228 | region that are held for saving crash dump. To release the |
| 226 | reserved memory echo 1 to it: | 229 | reserved memory echo 1 to it:: |
| 227 | 230 | ||
| 228 | echo 1 > /sys/kernel/fadump_release_mem | 231 | echo 1 > /sys/kernel/fadump_release_mem |
| 229 | 232 | ||
| 230 | After echo 1, the content of the /sys/kernel/debug/powerpc/fadump_region | 233 | After echo 1, the content of the /sys/kernel/debug/powerpc/fadump_region |
| 231 | file will change to reflect the new memory reservations. | 234 | file will change to reflect the new memory reservations. |
| @@ -238,38 +241,39 @@ Here is the list of files under powerpc debugfs: · 6 unmodified lines | |||
| 238 | (Assuming debugfs is mounted on /sys/kernel/debug directory.) | 241 | (Assuming debugfs is mounted on /sys/kernel/debug directory.) |
| 239 | 242 | ||
| 240 | /sys/kernel/debug/powerpc/fadump_region | 243 | /sys/kernel/debug/powerpc/fadump_region |
| 241 | |||
| 242 | This file shows the reserved memory regions if fadump is | 244 | This file shows the reserved memory regions if fadump is |
| 243 | enabled otherwise this file is empty. The output format | 245 | enabled otherwise this file is empty. The output format |
| 244 | is: | 246 | is:: |
| 245 | <region>: [<start>-<end>] <reserved-size> bytes, Dumped: <dump-size> | 247 | |
| 248 | <region>: [<start>-<end>] <reserved-size> bytes, Dumped: <dump-size> | ||
| 246 | 249 | ||
| 247 | e.g. | 250 | e.g. |
| 248 | Contents when fadump is registered during first kernel | 251 | Contents when fadump is registered during first kernel:: |
| 249 | 252 | ||
| 250 | # cat /sys/kernel/debug/powerpc/fadump_region | 253 | # cat /sys/kernel/debug/powerpc/fadump_region |
| 251 | CPU : [0x0000006ffb0000-0x0000006fff001f] 0x40020 bytes, Dumped: 0x0 | 254 | CPU : [0x0000006ffb0000-0x0000006fff001f] 0x40020 bytes, Dumped: 0x0 |
| 252 | HPTE: [0x0000006fff0020-0x0000006fff101f] 0x1000 bytes, Dumped: 0x0 | 255 | HPTE: [0x0000006fff0020-0x0000006fff101f] 0x1000 bytes, Dumped: 0x0 |
| 253 | DUMP: [0x0000006fff1020-0x0000007fff101f] 0x10000000 bytes, Dumped: 0x0 | 256 | DUMP: [0x0000006fff1020-0x0000007fff101f] 0x10000000 bytes, Dumped: 0x0 |
| 254 | 257 | ||
| 255 | Contents when fadump is active during second kernel | 258 | Contents when fadump is active during second kernel:: |
| 256 | 259 | ||
| 257 | # cat /sys/kernel/debug/powerpc/fadump_region | 260 | # cat /sys/kernel/debug/powerpc/fadump_region |
| 258 | CPU : [0x0000006ffb0000-0x0000006fff001f] 0x40020 bytes, Dumped: 0x40020 | 261 | CPU : [0x0000006ffb0000-0x0000006fff001f] 0x40020 bytes, Dumped: 0x40020 |
| 259 | HPTE: [0x0000006fff0020-0x0000006fff101f] 0x1000 bytes, Dumped: 0x1000 | 262 | HPTE: [0x0000006fff0020-0x0000006fff101f] 0x1000 bytes, Dumped: 0x1000 |
| 260 | DUMP: [0x0000006fff1020-0x0000007fff101f] 0x10000000 bytes, Dumped: 0x10000000 | 263 | DUMP: [0x0000006fff1020-0x0000007fff101f] 0x10000000 bytes, Dumped: 0x10000000 |
| 261 | : [0x00000010000000-0x0000006ffaffff] 0x5ffb0000 bytes, Dumped: 0x5ffb0000 | 264 | : [0x00000010000000-0x0000006ffaffff] 0x5ffb0000 bytes, Dumped: 0x5ffb0000 |
| 262 | 265 | ||
| 263 | NOTE: Please refer to Documentation/filesystems/debugfs.txt on | 266 | NOTE: |
| 267 | Please refer to Documentation/filesystems/debugfs.txt on | ||
| 264 | how to mount the debugfs filesystem. | 268 | how to mount the debugfs filesystem. |
| 265 | 269 | ||
| 266 | 270 | ||
| 267 | TODO: | 271 | TODO: |
| 268 | ----- | 272 | ----- |
| 269 | o Need to come up with the better approach to find out more | 273 | - Need to come up with the better approach to find out more |
| 270 | accurate boot memory size that is required for a kernel to | 274 | accurate boot memory size that is required for a kernel to |
| 271 | boot successfully when booted with restricted memory. | 275 | boot successfully when booted with restricted memory. |
| 272 | o The fadump implementation introduces a fadump crash info structure | 276 | - The fadump implementation introduces a fadump crash info structure |
| 273 | in the scratch area before the ELF core header. The idea of introducing | 277 | in the scratch area before the ELF core header. The idea of introducing |
| 274 | this structure is to pass some important crash info data to the second | 278 | this structure is to pass some important crash info data to the second |
| 275 | kernel which will help second kernel to populate ELF core header with | 279 | kernel which will help second kernel to populate ELF core header with |
| @@ -277,7 +281,9 @@ TODO: · 1 unmodified line | |||
| 277 | design implementation does not address a possibility of introducing | 281 | design implementation does not address a possibility of introducing |
| 278 | additional fields (in future) to this structure without affecting | 282 | additional fields (in future) to this structure without affecting |
| 279 | compatibility. Need to come up with the better approach to address this. | 283 | compatibility. Need to come up with the better approach to address this. |
| 284 | |||
| 280 | The possible approaches are: | 285 | The possible approaches are: |
| 286 | |||
| 281 | 1. Introduce version field for version tracking, bump up the version | 287 | 1. Introduce version field for version tracking, bump up the version |
| 282 | whenever a new field is added to the structure in future. The version | 288 | whenever a new field is added to the structure in future. The version |
| 283 | field can be used to find out what fields are valid for the current | 289 | field can be used to find out what fields are valid for the current |
| @@ -285,8 +291,11 @@ TODO: · 1 unmodified line | |||
| 285 | 2. Reserve the area of predefined size (say PAGE_SIZE) for this | 291 | 2. Reserve the area of predefined size (say PAGE_SIZE) for this |
| 286 | structure and have unused area as reserved (initialized to zero) | 292 | structure and have unused area as reserved (initialized to zero) |
| 287 | for future field additions. | 293 | for future field additions. |
| 294 | |||
| 288 | The advantage of approach 1 over 2 is we don't need to reserve extra space. | 295 | The advantage of approach 1 over 2 is we don't need to reserve extra space. |
| 289 | --- | 296 | |
| 290 | Author: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> | 297 | Author: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> |
| 298 | |||
| 291 | This document is based on the original documentation written for phyp | 299 | This document is based on the original documentation written for phyp |
| 300 | |||
| 292 | assisted dump by Linas Vepstas and Manish Ahuja. | 301 | assisted dump by Linas Vepstas and Manish Ahuja. |
| @@ -1,19 +1,22 @@ | |||
| 1 | =========================================================================== | 1 | =============================================================== |
| 2 | HVCS | 2 | HVCS IBM "Hypervisor Virtual Console Server" Installation Guide |
| 3 | IBM "Hypervisor Virtual Console Server" Installation Guide | 3 | =============================================================== |
| 4 | for Linux Kernel 2.6.4+ | ||
| 5 | Copyright (C) 2004 IBM Corporation | ||
| 6 | 4 | ||
| 7 | =========================================================================== | 5 | for Linux Kernel 2.6.4+ |
| 8 | NOTE:Eight space tabs are the optimum editor setting for reading this file. | ||
| 9 | =========================================================================== | ||
| 10 | 6 | ||
| 11 | Author(s) : Ryan S. Arnold <rsa@us.ibm.com> | 7 | Copyright (C) 2004 IBM Corporation |
| 12 | Date Created: March, 02, 2004 | ||
| 13 | Last Changed: August, 24, 2004 | ||
| 14 | 8 | ||
| 15 | --------------------------------------------------------------------------- | 9 | .. =========================================================================== |
| 16 | Table of contents: | 10 | .. NOTE:Eight space tabs are the optimum editor setting for reading this file. |
| 11 | .. =========================================================================== | ||
| 12 | |||
| 13 | |||
| 14 | Author(s): Ryan S. Arnold <rsa@us.ibm.com> | ||
| 15 | |||
| 16 | Date Created: March, 02, 2004 | ||
| 17 | Last Changed: August, 24, 2004 | ||
| 18 | |||
| 19 | .. Table of contents: | ||
| 17 | 20 | ||
| 18 | 1. Driver Introduction: | 21 | 1. Driver Introduction: |
| 19 | 2. System Requirements | 22 | 2. System Requirements |
| @@ -27,8 +30,8 @@ Table of contents: · 7 unmodified lines | |||
| 27 | 8. Questions & Answers: | 30 | 8. Questions & Answers: |
| 28 | 9. Reporting Bugs: | 31 | 9. Reporting Bugs: |
| 29 | 32 | ||
| 30 | --------------------------------------------------------------------------- | ||
| 31 | 1. Driver Introduction: | 33 | 1. Driver Introduction: |
| 34 | ======================= | ||
| 32 | 35 | ||
| 33 | This is the device driver for the IBM Hypervisor Virtual Console Server, | 36 | This is the device driver for the IBM Hypervisor Virtual Console Server, |
| 34 | "hvcs". The IBM hvcs provides a tty driver interface to allow Linux user | 37 | "hvcs". The IBM hvcs provides a tty driver interface to allow Linux user |
| @@ -38,8 +41,8 @@ ppc64 system. Physical hardware consoles per partition are not practical · 3 unmodified lines | |||
| 38 | on this hardware so system consoles are accessed by this driver using | 41 | on this hardware so system consoles are accessed by this driver using |
| 39 | firmware interfaces to virtual terminal devices. | 42 | firmware interfaces to virtual terminal devices. |
| 40 | 43 | ||
| 41 | --------------------------------------------------------------------------- | ||
| 42 | 2. System Requirements: | 44 | 2. System Requirements: |
| 45 | ======================= | ||
| 43 | 46 | ||
| 44 | This device driver was written using 2.6.4 Linux kernel APIs and will only | 47 | This device driver was written using 2.6.4 Linux kernel APIs and will only |
| 45 | build and run on kernels of this version or later. | 48 | build and run on kernels of this version or later. |
| @@ -52,8 +55,8 @@ Sysfs must be mounted on the system so that the user can determine which · 6 unmodified lines | |||
| 52 | major and minor numbers are associated with each vty-server. Directions | 55 | major and minor numbers are associated with each vty-server. Directions |
| 53 | for sysfs mounting are outside the scope of this document. | 56 | for sysfs mounting are outside the scope of this document. |
| 54 | 57 | ||
| 55 | --------------------------------------------------------------------------- | ||
| 56 | 3. Build Options: | 58 | 3. Build Options: |
| 59 | ================= | ||
| 57 | 60 | ||
| 58 | The hvcs driver registers itself as a tty driver. The tty layer | 61 | The hvcs driver registers itself as a tty driver. The tty layer |
| 59 | dynamically allocates a block of major and minor numbers in a quantity | 62 | dynamically allocates a block of major and minor numbers in a quantity |
| @@ -65,11 +68,11 @@ If the default number of device entries is adequate then this driver can be · 5 unmodified lines | |||
| 65 | built into the kernel. If not, the default can be over-ridden by inserting | 68 | built into the kernel. If not, the default can be over-ridden by inserting |
| 66 | the driver as a module with insmod parameters. | 69 | the driver as a module with insmod parameters. |
| 67 | 70 | ||
| 68 | --------------------------------------------------------------------------- | ||
| 69 | 3.1 Built-in: | 71 | 3.1 Built-in: |
| 72 | ------------- | ||
| 70 | 73 | ||
| 71 | The following menuconfig example demonstrates selecting to build this | 74 | The following menuconfig example demonstrates selecting to build this |
| 72 | driver into the kernel. | 75 | driver into the kernel:: |
| 73 | 76 | ||
| 74 | Device Drivers ---> | 77 | Device Drivers ---> |
| 75 | Character devices ---> | 78 | Character devices ---> |
| @@ -77,11 +80,11 @@ driver into the kernel. · 1 unmodified line | |||
| 77 | 80 | ||
| 78 | Begin the kernel make process. | 81 | Begin the kernel make process. |
| 79 | 82 | ||
| 80 | --------------------------------------------------------------------------- | ||
| 81 | 3.2 Module: | 83 | 3.2 Module: |
| 84 | ----------- | ||
| 82 | 85 | ||
| 83 | The following menuconfig example demonstrates selecting to build this | 86 | The following menuconfig example demonstrates selecting to build this |
| 84 | driver as a kernel module. | 87 | driver as a kernel module:: |
| 85 | 88 | ||
| 86 | Device Drivers ---> | 89 | Device Drivers ---> |
| 87 | Character devices ---> | 90 | Character devices ---> |
| @@ -89,11 +92,11 @@ driver as a kernel module. · 1 unmodified line | |||
| 89 | 92 | ||
| 90 | The make process will build the following kernel modules: | 93 | The make process will build the following kernel modules: |
| 91 | 94 | ||
| 92 | hvcs.ko | 95 | - hvcs.ko |
| 93 | hvcserver.ko | 96 | - hvcserver.ko |
| 94 | 97 | ||
| 95 | To insert the module with the default allocation execute the following | 98 | To insert the module with the default allocation execute the following |
| 96 | commands in the order they appear: | 99 | commands in the order they appear:: |
| 97 | 100 | ||
| 98 | insmod hvcserver.ko | 101 | insmod hvcserver.ko |
| 99 | insmod hvcs.ko | 102 | insmod hvcs.ko |
| @@ -103,7 +106,7 @@ be inserted first, otherwise the hvcs module will not find some of the · 3 unmodified lines | |||
| 103 | symbols it expects. | 106 | symbols it expects. |
| 104 | 107 | ||
| 105 | To override the default use an insmod parameter as follows (requesting 4 | 108 | To override the default use an insmod parameter as follows (requesting 4 |
| 106 | tty devices as an example): | 109 | tty devices as an example):: |
| 107 | 110 | ||
| 108 | insmod hvcs.ko hvcs_parm_num_devs=4 | 111 | insmod hvcs.ko hvcs_parm_num_devs=4 |
| 109 | 112 | ||
| @@ -115,31 +118,31 @@ source file before building. · 5 unmodified lines | |||
| 115 | NOTE: The length of time it takes to insmod the driver seems to be related | 118 | NOTE: The length of time it takes to insmod the driver seems to be related |
| 116 | to the number of tty interfaces the registering driver requests. | 119 | to the number of tty interfaces the registering driver requests. |
| 117 | 120 | ||
| 118 | In order to remove the driver module execute the following command: | 121 | In order to remove the driver module execute the following command:: |
| 119 | 122 | ||
| 120 | rmmod hvcs.ko | 123 | rmmod hvcs.ko |
| 121 | 124 | ||
| 122 | The recommended method for installing hvcs as a module is to use depmod to | 125 | The recommended method for installing hvcs as a module is to use depmod to |
| 123 | build a current modules.dep file in /lib/modules/`uname -r` and then | 126 | build a current modules.dep file in /lib/modules/`uname -r` and then |
| 124 | execute: | 127 | execute:: |
| 125 | 128 | ||
| 126 | modprobe hvcs hvcs_parm_num_devs=4 | 129 | modprobe hvcs hvcs_parm_num_devs=4 |
| 127 | 130 | ||
| 128 | The modules.dep file indicates that hvcserver.ko needs to be inserted | 131 | The modules.dep file indicates that hvcserver.ko needs to be inserted |
| 129 | before hvcs.ko and modprobe uses this file to smartly insert the modules in | 132 | before hvcs.ko and modprobe uses this file to smartly insert the modules in |
| 130 | the proper order. | 133 | the proper order. |
| 131 | 134 | ||
| 132 | The following modprobe command is used to remove hvcs and hvcserver in the | 135 | The following modprobe command is used to remove hvcs and hvcserver in the |
| 133 | proper order: | 136 | proper order:: |
| 134 | 137 | ||
| 135 | modprobe -r hvcs | 138 | modprobe -r hvcs |
| 136 | 139 | ||
| 137 | --------------------------------------------------------------------------- | ||
| 138 | 4. Installation: | 140 | 4. Installation: |
| 141 | ================ | ||
| 139 | 142 | ||
| 140 | The tty layer creates sysfs entries which contain the major and minor | 143 | The tty layer creates sysfs entries which contain the major and minor |
| 141 | numbers allocated for the hvcs driver. The following snippet of "tree" | 144 | numbers allocated for the hvcs driver. The following snippet of "tree" |
| 142 | output of the sysfs directory shows where these numbers are presented: | 145 | output of the sysfs directory shows where these numbers are presented:: |
| 143 | 146 | ||
| 144 | sys/ | 147 | sys/ |
| 145 | |-- *other sysfs base dirs* | 148 | |-- *other sysfs base dirs* |
| @@ -164,7 +167,7 @@ output of the sysfs directory shows where these numbers are presented: · 18 unmodified lines | |||
| 164 | |-- *other sysfs base dirs* | 167 | |-- *other sysfs base dirs* |
| 165 | 168 | ||
| 166 | For the above examples the following output is a result of cat'ing the | 169 | For the above examples the following output is a result of cat'ing the |
| 167 | "dev" entry in the hvcs directory: | 170 | "dev" entry in the hvcs directory:: |
| 168 | 171 | ||
| 169 | Pow5:/sys/class/tty/hvcs0/ # cat dev | 172 | Pow5:/sys/class/tty/hvcs0/ # cat dev |
| 170 | 254:0 | 173 | 254:0 |
| @@ -184,7 +187,7 @@ systems running hvcs will already have the device entries created or udev · 13 unmodified lines | |||
| 184 | will do it automatically. | 187 | will do it automatically. |
| 185 | 188 | ||
| 186 | Given the example output above, to manually create a /dev/hvcs* node entry | 189 | Given the example output above, to manually create a /dev/hvcs* node entry |
| 187 | mknod can be used as follows: | 190 | mknod can be used as follows:: |
| 188 | 191 | ||
| 189 | mknod /dev/hvcs0 c 254 0 | 192 | mknod /dev/hvcs0 c 254 0 |
| 190 | mknod /dev/hvcs1 c 254 1 | 193 | mknod /dev/hvcs1 c 254 1 |
| @@ -195,15 +198,15 @@ Using mknod to manually create the device entries makes these device nodes · 4 unmodified lines | |||
| 195 | persistent. Once created they will exist prior to the driver insmod. | 198 | persistent. Once created they will exist prior to the driver insmod. |
| 196 | 199 | ||
| 197 | Attempting to connect an application to /dev/hvcs* prior to insertion of | 200 | Attempting to connect an application to /dev/hvcs* prior to insertion of |
| 198 | the hvcs module will result in an error message similar to the following: | 201 | the hvcs module will result in an error message similar to the following:: |
| 199 | 202 | ||
| 200 | "/dev/hvcs*: No such device". | 203 | "/dev/hvcs*: No such device". |
| 201 | 204 | ||
| 202 | NOTE: Just because there is a device node present doesn't mean that there | 205 | NOTE: Just because there is a device node present doesn't mean that there |
| 203 | is a vty-server device configured for that node. | 206 | is a vty-server device configured for that node. |
| 204 | 207 | ||
| 205 | --------------------------------------------------------------------------- | ||
| 206 | 5. Connection | 208 | 5. Connection |
| 209 | ============= | ||
| 207 | 210 | ||
| 208 | Since this driver controls devices that provide a tty interface a user can | 211 | Since this driver controls devices that provide a tty interface a user can |
| 209 | interact with the device node entries using any standard tty-interactive | 212 | interact with the device node entries using any standard tty-interactive |
| @@ -249,7 +252,7 @@ vty-server adapter is associated with which /dev/hvcs* node a special sysfs · 39 unmodified lines | |||
| 249 | attribute has been added to each vty-server sysfs entry. This entry is | 252 | attribute has been added to each vty-server sysfs entry. This entry is |
| 250 | called "index" and showing it reveals an integer that refers to the | 253 | called "index" and showing it reveals an integer that refers to the |
| 251 | /dev/hvcs* entry to use to connect to that device. For instance cating the | 254 | /dev/hvcs* entry to use to connect to that device. For instance cating the |
| 252 | index attribute of vty-server adapter 30000004 shows the following. | 255 | index attribute of vty-server adapter 30000004 shows the following:: |
| 253 | 256 | ||
| 254 | Pow5:/sys/bus/vio/drivers/hvcs/30000004 # cat index | 257 | Pow5:/sys/bus/vio/drivers/hvcs/30000004 # cat index |
| 255 | 2 | 258 | 2 |
| @@ -262,8 +265,8 @@ system the /dev/hvcs* entry that interacts with a particular vty-server · 6 unmodified lines | |||
| 262 | adapter is not guaranteed to remain the same across system reboots. Look | 265 | adapter is not guaranteed to remain the same across system reboots. Look |
| 263 | in the Q & A section for more on this issue. | 266 | in the Q & A section for more on this issue. |
| 264 | 267 | ||
| 265 | --------------------------------------------------------------------------- | ||
| 266 | 6. Disconnection | 268 | 6. Disconnection |
| 269 | ================ | ||
| 267 | 270 | ||
| 268 | As a security feature to prevent the delivery of stale data to an | 271 | As a security feature to prevent the delivery of stale data to an |
| 269 | unintended target the Power5 system firmware disables the fetching of data | 272 | unintended target the Power5 system firmware disables the fetching of data |
| @@ -305,7 +308,7 @@ connection between the vty-server and target vty ONLY if the vterm_state · 35 unmodified lines | |||
| 305 | previously read '1'. The write directive is ignored if the vterm_state | 308 | previously read '1'. The write directive is ignored if the vterm_state |
| 306 | read '0' or if any value other than '0' was written to the vterm_state | 309 | read '0' or if any value other than '0' was written to the vterm_state |
| 307 | attribute. The following example will show the method used for verifying | 310 | attribute. The following example will show the method used for verifying |
| 308 | the vty-server connection status and disconnecting a vty-server connection. | 311 | the vty-server connection status and disconnecting a vty-server connection:: |
| 309 | 312 | ||
| 310 | Pow5:/sys/bus/vio/drivers/hvcs/30000004 # cat vterm_state | 313 | Pow5:/sys/bus/vio/drivers/hvcs/30000004 # cat vterm_state |
| 311 | 1 | 314 | 1 |
| @@ -318,12 +321,12 @@ the vty-server connection status and disconnecting a vty-server connection. · 6 unmodified lines | |||
| 318 | All vty-server connections are automatically terminated when the device is | 321 | All vty-server connections are automatically terminated when the device is |
| 319 | hotplug removed and when the module is removed. | 322 | hotplug removed and when the module is removed. |
| 320 | 323 | ||
| 321 | --------------------------------------------------------------------------- | ||
| 322 | 7. Configuration | 324 | 7. Configuration |
| 325 | ================ | ||
| 323 | 326 | ||
| 324 | Each vty-server has a sysfs entry in the /sys/devices/vio directory, which | 327 | Each vty-server has a sysfs entry in the /sys/devices/vio directory, which |
| 325 | is symlinked in several other sysfs tree directories, notably under the | 328 | is symlinked in several other sysfs tree directories, notably under the |
| 326 | hvcs driver entry, which looks like the following example: | 329 | hvcs driver entry, which looks like the following example:: |
| 327 | 330 | ||
| 328 | Pow5:/sys/bus/vio/drivers/hvcs # ls | 331 | Pow5:/sys/bus/vio/drivers/hvcs # ls |
| 329 | . .. 30000003 30000004 rescan | 332 | . .. 30000003 30000004 rescan |
| @@ -344,7 +347,7 @@ completed or was never executed. · 14 unmodified lines | |||
| 344 | 347 | ||
| 345 | Vty-server entries in this directory are a 32 bit partition unique unit | 348 | Vty-server entries in this directory are a 32 bit partition unique unit |
| 346 | address that is created by firmware. An example vty-server sysfs entry | 349 | address that is created by firmware. An example vty-server sysfs entry |
| 347 | looks like the following: | 350 | looks like the following:: |
| 348 | 351 | ||
| 349 | Pow5:/sys/bus/vio/drivers/hvcs/30000004 # ls | 352 | Pow5:/sys/bus/vio/drivers/hvcs/30000004 # ls |
| 350 | . current_vty devspec name partner_vtys | 353 | . current_vty devspec name partner_vtys |
| @@ -352,21 +355,21 @@ looks like the following: · 1 unmodified line | |||
| 352 | 355 | ||
| 353 | Each entry is provided, by default with a "name" attribute. Reading the | 356 | Each entry is provided, by default with a "name" attribute. Reading the |
| 354 | "name" attribute will reveal the device type as shown in the following | 357 | "name" attribute will reveal the device type as shown in the following |
| 355 | example: | 358 | example:: |
| 356 | 359 | ||
| 357 | Pow5:/sys/bus/vio/drivers/hvcs/30000003 # cat name | 360 | Pow5:/sys/bus/vio/drivers/hvcs/30000003 # cat name |
| 358 | vty-server | 361 | vty-server |
| 359 | 362 | ||
| 360 | Each entry is also provided, by default, with a "devspec" attribute which | 363 | Each entry is also provided, by default, with a "devspec" attribute which |
| 361 | reveals the full device specification when read, as shown in the following | 364 | reveals the full device specification when read, as shown in the following |
| 362 | example: | 365 | example:: |
| 363 | 366 | ||
| 364 | Pow5:/sys/bus/vio/drivers/hvcs/30000004 # cat devspec | 367 | Pow5:/sys/bus/vio/drivers/hvcs/30000004 # cat devspec |
| 365 | /vdevice/vty-server@30000004 | 368 | /vdevice/vty-server@30000004 |
| 366 | 369 | ||
| 367 | Each vty-server sysfs dir is provided with two read-only attributes that | 370 | Each vty-server sysfs dir is provided with two read-only attributes that |
| 368 | provide lists of easily parsed partner vty data: "partner_vtys" and | 371 | provide lists of easily parsed partner vty data: "partner_vtys" and |
| 369 | "partner_clcs". | 372 | "partner_clcs":: |
| 370 | 373 | ||
| 371 | Pow5:/sys/bus/vio/drivers/hvcs/30000004 # cat partner_vtys | 374 | Pow5:/sys/bus/vio/drivers/hvcs/30000004 # cat partner_vtys |
| 372 | 30000000 | 375 | 30000000 |
| @@ -396,7 +399,7 @@ A vty-server can only be connected to a single vty at a time. The entry, · 23 unmodified lines | |||
| 396 | read. | 399 | read. |
| 397 | 400 | ||
| 398 | The current_vty can be changed by writing a valid partner clc to the entry | 401 | The current_vty can be changed by writing a valid partner clc to the entry |
| 399 | as in the following example: | 402 | as in the following example:: |
| 400 | 403 | ||
| 401 | Pow5:/sys/bus/vio/drivers/hvcs/30000004 # echo U5112.428.10304 | 404 | Pow5:/sys/bus/vio/drivers/hvcs/30000004 # echo U5112.428.10304 |
| 402 | 8A-V4-C0 > current_vty | 405 | 8A-V4-C0 > current_vty |
| @@ -408,9 +411,9 @@ currently open connection is freed. · 5 unmodified lines | |||
| 408 | Information on the "vterm_state" attribute was covered earlier on the | 411 | Information on the "vterm_state" attribute was covered earlier on the |
| 409 | chapter entitled "disconnection". | 412 | chapter entitled "disconnection". |
| 410 | 413 | ||
| 411 | --------------------------------------------------------------------------- | ||
| 412 | 8. Questions & Answers: | 414 | 8. Questions & Answers: |
| 413 | =========================================================================== | 415 | ======================= |
| 416 | |||
| 414 | Q: What are the security concerns involving hvcs? | 417 | Q: What are the security concerns involving hvcs? |
| 415 | 418 | ||
| 416 | A: There are three main security concerns: | 419 | A: There are three main security concerns: |
| @@ -429,6 +432,7 @@ A: There are three main security concerns: · 12 unmodified lines | |||
| 429 | partition) will experience the previously logged in session. | 432 | partition) will experience the previously logged in session. |
| 430 | 433 | ||
| 431 | --------------------------------------------------------------------------- | 434 | --------------------------------------------------------------------------- |
| 435 | |||
| 432 | Q: How do I multiplex a console that I grab through hvcs so that other | 436 | Q: How do I multiplex a console that I grab through hvcs so that other |
| 433 | people can see it: | 437 | people can see it: |
| 434 | 438 | ||
| @@ -440,6 +444,7 @@ term type "screen" to others. This means that curses based programs may · 5 unmodified lines | |||
| 440 | not display properly in screen sessions. | 444 | not display properly in screen sessions. |
| 441 | 445 | ||
| 442 | --------------------------------------------------------------------------- | 446 | --------------------------------------------------------------------------- |
| 447 | |||
| 443 | Q: Why are the colors all messed up? | 448 | Q: Why are the colors all messed up? |
| 444 | Q: Why are the control characters acting strange or not working? | 449 | Q: Why are the control characters acting strange or not working? |
| 445 | Q: Why is the console output all strange and unintelligible? | 450 | Q: Why is the console output all strange and unintelligible? |
| @@ -455,6 +460,7 @@ disconnect from the console. This will ensure that the next user gets · 9 unmodified lines | |||
| 455 | their own TERM type set when they login. | 460 | their own TERM type set when they login. |
| 456 | 461 | ||
| 457 | --------------------------------------------------------------------------- | 462 | --------------------------------------------------------------------------- |
| 463 | |||
| 458 | Q: When I try to CONNECT kermit to an hvcs device I get: | 464 | Q: When I try to CONNECT kermit to an hvcs device I get: |
| 459 | "Sorry, can't open connection: /dev/hvcs*"What is happening? | 465 | "Sorry, can't open connection: /dev/hvcs*"What is happening? |
| 460 | 466 | ||
| @@ -490,6 +496,7 @@ A: There is not a corresponding vty-server device that maps to an existing · 29 unmodified lines | |||
| 490 | /dev/hvcs* entry. | 496 | /dev/hvcs* entry. |
| 491 | 497 | ||
| 492 | --------------------------------------------------------------------------- | 498 | --------------------------------------------------------------------------- |
| 499 | |||
| 493 | Q: When I try to CONNECT kermit to an hvcs device I get: | 500 | Q: When I try to CONNECT kermit to an hvcs device I get: |
| 494 | "Sorry, write access to UUCP lockfile directory denied." | 501 | "Sorry, write access to UUCP lockfile directory denied." |
| 495 | 502 | ||
| @@ -497,6 +504,7 @@ A: The /dev/hvcs* entry you have specified doesn't exist where you said it · 1 unmodified line | |||
| 497 | does? Maybe you haven't inserted the module (on systems with udev). | 504 | does? Maybe you haven't inserted the module (on systems with udev). |
| 498 | 505 | ||
| 499 | --------------------------------------------------------------------------- | 506 | --------------------------------------------------------------------------- |
| 507 | |||
| 500 | Q: If I already have one Linux partition installed can I use hvcs on said | 508 | Q: If I already have one Linux partition installed can I use hvcs on said |
| 501 | partition to provide the console for the install of a second Linux | 509 | partition to provide the console for the install of a second Linux |
| 502 | partition? | 510 | partition? |
| @@ -505,6 +513,7 @@ A: Yes granted that your are connected to the /dev/hvcs* device using · 2 unmodified lines | |||
| 505 | kermit or cu or some other program that doesn't provide terminal emulation. | 513 | kermit or cu or some other program that doesn't provide terminal emulation. |
| 506 | 514 | ||
| 507 | --------------------------------------------------------------------------- | 515 | --------------------------------------------------------------------------- |
| 516 | |||
| 508 | Q: Can I connect to more than one partition's console at a time using this | 517 | Q: Can I connect to more than one partition's console at a time using this |
| 509 | driver? | 518 | driver? |
| 510 | 519 | ||
| @@ -512,6 +521,7 @@ A: Yes. Of course this means that there must be more than one vty-server · 1 unmodified line | |||
| 512 | configured for this partition and each must point to a disconnected vty. | 521 | configured for this partition and each must point to a disconnected vty. |
| 513 | 522 | ||
| 514 | --------------------------------------------------------------------------- | 523 | --------------------------------------------------------------------------- |
| 524 | |||
| 515 | Q: Does the hvcs driver support dynamic (hotplug) addition of devices? | 525 | Q: Does the hvcs driver support dynamic (hotplug) addition of devices? |
| 516 | 526 | ||
| 517 | A: Yes, if you have dlpar and hotplug enabled for your system and it has | 527 | A: Yes, if you have dlpar and hotplug enabled for your system and it has |
| @@ -519,6 +529,7 @@ been built into the kernel the hvcs drivers is configured to dynamically · 1 unmodified line | |||
| 519 | handle additions of new devices and removals of unused devices. | 529 | handle additions of new devices and removals of unused devices. |
| 520 | 530 | ||
| 521 | --------------------------------------------------------------------------- | 531 | --------------------------------------------------------------------------- |
| 532 | |||
| 522 | Q: For some reason /dev/hvcs* doesn't map to the same vty-server adapter | 533 | Q: For some reason /dev/hvcs* doesn't map to the same vty-server adapter |
| 523 | after a reboot. What happened? | 534 | after a reboot. What happened? |
| 524 | 535 | ||
| @@ -533,6 +544,7 @@ on how to determine which vty-server goes with which /dev/hvcs* node. · 8 unmodified lines | |||
| 533 | Hint; look at the sysfs "index" attribute for the vty-server. | 544 | Hint; look at the sysfs "index" attribute for the vty-server. |
| 534 | 545 | ||
| 535 | --------------------------------------------------------------------------- | 546 | --------------------------------------------------------------------------- |
| 547 | |||
| 536 | Q: Can I use /dev/hvcs* as a conduit to another partition and use a tty | 548 | Q: Can I use /dev/hvcs* as a conduit to another partition and use a tty |
| 537 | device on that partition as the other end of the pipe? | 549 | device on that partition as the other end of the pipe? |
| 538 | 550 | ||
| @@ -554,7 +566,9 @@ read or write to /dev/hvcs*. Now you have a tty conduit between two · 15 unmodified lines | |||
| 554 | partitions. | 566 | partitions. |
| 555 | 567 | ||
| 556 | --------------------------------------------------------------------------- | 568 | --------------------------------------------------------------------------- |
| 569 | |||
| 557 | 9. Reporting Bugs: | 570 | 9. Reporting Bugs: |
| 571 | ================== | ||
| 558 | 572 | ||
| 559 | The proper channel for reporting bugs is either through the Linux OS | 573 | The proper channel for reporting bugs is either through the Linux OS |
| 560 | distribution company that provided your OS or by posting issues to the | 574 | distribution company that provided your OS or by posting issues to the |
| @@ -0,0 +1,34 @@ | |||
| 1 | .. SPDX-License-Identifier: GPL-2.0 | ||
| 2 | |||
| 3 | ======= | ||
| 4 | powerpc | ||
| 5 | ======= | ||
| 6 | |||
| 7 | .. toctree:: | ||
| 8 | :maxdepth: 1 | ||
| 9 | |||
| 10 | bootwrapper | ||
| 11 | cpu_families | ||
| 12 | cpu_features | ||
| 13 | cxl | ||
| 14 | cxlflash | ||
| 15 | dawr-power9 | ||
| 16 | dscr | ||
| 17 | eeh-pci-error-recovery | ||
| 18 | firmware-assisted-dump | ||
| 19 | hvcs | ||
| 20 | isa-versions | ||
| 21 | mpc52xx | ||
| 22 | pci_iov_resource_on_powernv | ||
| 23 | pmu-ebb | ||
| 24 | ptrace | ||
| 25 | qe_firmware | ||
| 26 | syscall64-abi | ||
| 27 | transactional_memory | ||
| 28 | |||
| 29 | .. only:: subproject and html | ||
| 30 | |||
| 31 | Indices | ||
| 32 | ======= | ||
| 33 | |||
| 34 | * :ref:`genindex` | ||
| @@ -1,13 +1,12 @@ | |||
| 1 | :orphan: | 1 | ========================== |
| 2 | |||
| 3 | CPU to ISA Version Mapping | 2 | CPU to ISA Version Mapping |
| 4 | ========================== | 3 | ========================== |
| 5 | 4 | ||
| 6 | Mapping of some CPU versions to relevant ISA versions. | 5 | Mapping of some CPU versions to relevant ISA versions. |
| 7 | 6 | ||
| 8 | ========= ==================== | 7 | ========= ==================================================================== |
| 9 | CPU Architecture version | 8 | CPU Architecture version |
| 10 | ========= ==================== | 9 | ========= ==================================================================== |
| 11 | Power9 Power ISA v3.0B | 10 | Power9 Power ISA v3.0B |
| 12 | Power8 Power ISA v2.07 | 11 | Power8 Power ISA v2.07 |
| 13 | Power7 Power ISA v2.06 | 12 | Power7 Power ISA v2.06 |
| @@ -24,7 +23,7 @@ PPC970 - PowerPC User Instruction Set Architecture Book I v2.01 · 10 unmodified lines | |||
| 24 | - PowerPC Virtual Environment Architecture Book II v2.01 | 23 | - PowerPC Virtual Environment Architecture Book II v2.01 |
| 25 | - PowerPC Operating Environment Architecture Book III v2.01 | 24 | - PowerPC Operating Environment Architecture Book III v2.01 |
| 26 | - Plus Altivec/VMX ~= 2.03 | 25 | - Plus Altivec/VMX ~= 2.03 |
| 27 | ========= ==================== | 26 | ========= ==================================================================== |
| 28 | 27 | ||
| 29 | 28 | ||
| 30 | Key Features | 29 | Key Features |
| @@ -60,9 +59,9 @@ Power5 No · 29 unmodified lines | |||
| 60 | PPC970 No | 59 | PPC970 No |
| 61 | ========== ==== | 60 | ========== ==== |
| 62 | 61 | ||
| 63 | ========== ==================== | 62 | ========== ==================================== |
| 64 | CPU Transactional Memory | 63 | CPU Transactional Memory |
| 65 | ========== ==================== | 64 | ========== ==================================== |
| 66 | Power9 Yes (* see transactional_memory.txt) | 65 | Power9 Yes (* see transactional_memory.txt) |
| 67 | Power8 Yes | 66 | Power8 Yes |
| 68 | Power7 No | 67 | Power7 No |
| @@ -73,4 +72,4 @@ Power5++ No · 4 unmodified lines | |||
| 73 | Power5+ No | 72 | Power5+ No |
| 74 | Power5 No | 73 | Power5 No |
| 75 | PPC970 No | 74 | PPC970 No |
| 76 | ========== ==================== | 75 | ========== ==================================== |
| @@ -1,11 +1,13 @@ | |||
| 1 | ============================= | ||
| 1 | Linux 2.6.x on MPC52xx family | 2 | Linux 2.6.x on MPC52xx family |
| 2 | ----------------------------- | 3 | ============================= |
| 3 | 4 | ||
| 4 | For the latest info, go to http://www.246tNt.com/mpc52xx/ | 5 | For the latest info, go to http://www.246tNt.com/mpc52xx/ |
| 5 | 6 | ||
| 6 | To compile/use : | 7 | To compile/use : |
| 7 | 8 | ||
| 8 | - U-Boot: | 9 | - U-Boot:: |
| 10 | |||
| 9 | # <edit Makefile to set ARCH=ppc & CROSS_COMPILE=... ( also EXTRAVERSION | 11 | # <edit Makefile to set ARCH=ppc & CROSS_COMPILE=... ( also EXTRAVERSION |
| 10 | if you wish to ). | 12 | if you wish to ). |
| 11 | # make lite5200_defconfig | 13 | # make lite5200_defconfig |
| @@ -16,7 +18,8 @@ To compile/use : · 4 unmodified lines | |||
| 16 | => tftpboot 400000 pRamdisk | 18 | => tftpboot 400000 pRamdisk |
| 17 | => bootm 200000 400000 | 19 | => bootm 200000 400000 |
| 18 | 20 | ||
| 19 | - DBug: | 21 | - DBug:: |
| 22 | |||
| 20 | # <edit Makefile to set ARCH=ppc & CROSS_COMPILE=... ( also EXTRAVERSION | 23 | # <edit Makefile to set ARCH=ppc & CROSS_COMPILE=... ( also EXTRAVERSION |
| 21 | if you wish to ). | 24 | if you wish to ). |
| 22 | # make lite5200_defconfig | 25 | # make lite5200_defconfig |
| @@ -28,7 +31,8 @@ To compile/use : · 5 unmodified lines | |||
| 28 | DBug> dn -i zImage.initrd.lite5200 | 31 | DBug> dn -i zImage.initrd.lite5200 |
| 29 | 32 | ||
| 30 | 33 | ||
| 31 | Some remarks : | 34 | Some remarks: |
| 35 | |||
| 32 | - The port is named mpc52xxx, and config options are PPC_MPC52xx. The MGT5100 | 36 | - The port is named mpc52xxx, and config options are PPC_MPC52xx. The MGT5100 |
| 33 | is not supported, and I'm not sure anyone is interesting in working on it | 37 | is not supported, and I'm not sure anyone is interesting in working on it |
| 34 | so. I didn't took 5xxx because there's apparently a lot of 5xxx that have | 38 | so. I didn't took 5xxx because there's apparently a lot of 5xxx that have |
| @@ -1,6 +1,13 @@ | |||
| 1 | =================================================== | ||
| 2 | PCI Express I/O Virtualization Resource on Powerenv | ||
| 3 | =================================================== | ||
| 4 | |||
| 1 | Wei Yang <weiyang@linux.vnet.ibm.com> | 5 | Wei Yang <weiyang@linux.vnet.ibm.com> |
| 6 | |||
| 2 | Benjamin Herrenschmidt <benh@au1.ibm.com> | 7 | Benjamin Herrenschmidt <benh@au1.ibm.com> |
| 8 | |||
| 3 | Bjorn Helgaas <bhelgaas@google.com> | 9 | Bjorn Helgaas <bhelgaas@google.com> |
| 10 | |||
| 4 | 26 Aug 2014 | 11 | 26 Aug 2014 |
| 5 | 12 | ||
| 6 | This document describes the requirement from hardware for PCI MMIO resource | 13 | This document describes the requirement from hardware for PCI MMIO resource |
| @@ -10,6 +17,7 @@ Endpoints and the implementation on P8 (IODA2). The next two sections talks · 3 unmodified lines | |||
| 10 | about considerations on enabling SRIOV on IODA2. | 17 | about considerations on enabling SRIOV on IODA2. |
| 11 | 18 | ||
| 12 | 1. Introduction to Partitionable Endpoints | 19 | 1. Introduction to Partitionable Endpoints |
| 20 | ========================================== | ||
| 13 | 21 | ||
| 14 | A Partitionable Endpoint (PE) is a way to group the various resources | 22 | A Partitionable Endpoint (PE) is a way to group the various resources |
| 15 | associated with a device or a set of devices to provide isolation between | 23 | associated with a device or a set of devices to provide isolation between |
| @@ -35,6 +43,7 @@ is a completely separate HW entity that replicates the entire logic, so has · 19 unmodified lines | |||
| 35 | its own set of PEs, etc. | 43 | its own set of PEs, etc. |
| 36 | 44 | ||
| 37 | 2. Implementation of Partitionable Endpoints on P8 (IODA2) | 45 | 2. Implementation of Partitionable Endpoints on P8 (IODA2) |
| 46 | ========================================================== | ||
| 38 | 47 | ||
| 39 | P8 supports up to 256 Partitionable Endpoints per PHB. | 48 | P8 supports up to 256 Partitionable Endpoints per PHB. |
| 40 | 49 | ||
| @@ -149,6 +158,7 @@ P8 supports up to 256 Partitionable Endpoints per PHB. · 108 unmodified lines | |||
| 149 | sense, but we haven't done it yet. | 158 | sense, but we haven't done it yet. |
| 150 | 159 | ||
| 151 | 3. Considerations for SR-IOV on PowerKVM | 160 | 3. Considerations for SR-IOV on PowerKVM |
| 161 | ======================================== | ||
| 152 | 162 | ||
| 153 | * SR-IOV Background | 163 | * SR-IOV Background |
| 154 | 164 | ||
| @@ -224,7 +234,7 @@ P8 supports up to 256 Partitionable Endpoints per PHB. · 69 unmodified lines | |||
| 224 | IODA supports 256 PEs, so segmented windows contain 256 segments, so if | 234 | IODA supports 256 PEs, so segmented windows contain 256 segments, so if |
| 225 | total_VFs is less than 256, we have the situation in Figure 1.0, where | 235 | total_VFs is less than 256, we have the situation in Figure 1.0, where |
| 226 | segments [total_VFs, 255] of the M64 window may map to some MMIO range on | 236 | segments [total_VFs, 255] of the M64 window may map to some MMIO range on |
| 227 | other devices: | 237 | other devices:: |
| 228 | 238 | ||
| 229 | 0 1 total_VFs - 1 | 239 | 0 1 total_VFs - 1 |
| 230 | +------+------+- -+------+------+ | 240 | +------+------+- -+------+------+ |
| @@ -243,7 +253,7 @@ P8 supports up to 256 Partitionable Endpoints per PHB. · 12 unmodified lines | |||
| 243 | Figure 1.0 Direct map VF(n) BAR space | 253 | Figure 1.0 Direct map VF(n) BAR space |
| 244 | 254 | ||
| 245 | Our current solution is to allocate 256 segments even if the VF(n) BAR | 255 | Our current solution is to allocate 256 segments even if the VF(n) BAR |
| 246 | space doesn't need that much, as shown in Figure 1.1: | 256 | space doesn't need that much, as shown in Figure 1.1:: |
| 247 | 257 | ||
| 248 | 0 1 total_VFs - 1 255 | 258 | 0 1 total_VFs - 1 255 |
| 249 | +------+------+- -+------+------+- -+------+------+ | 259 | +------+------+- -+------+------+- -+------+------+ |
| @@ -269,6 +279,7 @@ P8 supports up to 256 Partitionable Endpoints per PHB. · 19 unmodified lines | |||
| 269 | responds to segments [total_VFs, 255]. | 279 | responds to segments [total_VFs, 255]. |
| 270 | 280 | ||
| 271 | 4. Implications for the Generic PCI Code | 281 | 4. Implications for the Generic PCI Code |
| 282 | ======================================== | ||
| 272 | 283 | ||
| 273 | The PCIe SR-IOV spec requires that the base of the VF(n) BAR space be | 284 | The PCIe SR-IOV spec requires that the base of the VF(n) BAR space be |
| 274 | aligned to the size of an individual VF BAR. | 285 | aligned to the size of an individual VF BAR. |
| @@ -1,3 +1,4 @@ | |||
| 1 | ======================== | ||
| 1 | PMU Event Based Branches | 2 | PMU Event Based Branches |
| 2 | ======================== | 3 | ======================== |
| 3 | 4 | ||
| @@ -0,0 +1,156 @@ | |||
| 1 | ====== | ||
| 2 | Ptrace | ||
| 3 | ====== | ||
| 4 | |||
| 5 | GDB intends to support the following hardware debug features of BookE | ||
| 6 | processors: | ||
| 7 | |||
| 8 | 4 hardware breakpoints (IAC) | ||
| 9 | 2 hardware watchpoints (read, write and read-write) (DAC) | ||
| 10 | 2 value conditions for the hardware watchpoints (DVC) | ||
| 11 | |||
| 12 | For that, we need to extend ptrace so that GDB can query and set these | ||
| 13 | resources. Since we're extending, we're trying to create an interface | ||
| 14 | that's extendable and that covers both BookE and server processors, so | ||
| 15 | that GDB doesn't need to special-case each of them. We added the | ||
| 16 | following 3 new ptrace requests. | ||
| 17 | |||
| 18 | 1. PTRACE_PPC_GETHWDEBUGINFO | ||
| 19 | ============================ | ||
| 20 | |||
| 21 | Query for GDB to discover the hardware debug features. The main info to | ||
| 22 | be returned here is the minimum alignment for the hardware watchpoints. | ||
| 23 | BookE processors don't have restrictions here, but server processors have | ||
| 24 | an 8-byte alignment restriction for hardware watchpoints. We'd like to avoid | ||
| 25 | adding special cases to GDB based on what it sees in AUXV. | ||
| 26 | |||
| 27 | Since we're at it, we added other useful info that the kernel can return to | ||
| 28 | GDB: this query will return the number of hardware breakpoints, hardware | ||
| 29 | watchpoints and whether it supports a range of addresses and a condition. | ||
| 30 | The query will fill the following structure provided by the requesting process:: | ||
| 31 | |||
| 32 | struct ppc_debug_info { | ||
| 33 | unit32_t version; | ||
| 34 | unit32_t num_instruction_bps; | ||
| 35 | unit32_t num_data_bps; | ||
| 36 | unit32_t num_condition_regs; | ||
| 37 | unit32_t data_bp_alignment; | ||
| 38 | unit32_t sizeof_condition; /* size of the DVC register */ | ||
| 39 | uint64_t features; /* bitmask of the individual flags */ | ||
| 40 | }; | ||
| 41 | |||
| 42 | features will have bits indicating whether there is support for:: | ||
| 43 | |||
| 44 | #define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x1 | ||
| 45 | #define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x2 | ||
| 46 | #define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x4 | ||
| 47 | #define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x8 | ||
| 48 | #define PPC_DEBUG_FEATURE_DATA_BP_DAWR 0x10 | ||
| 49 | |||
| 50 | 2. PTRACE_SETHWDEBUG | ||
| 51 | |||
| 52 | Sets a hardware breakpoint or watchpoint, according to the provided structure:: | ||
| 53 | |||
| 54 | struct ppc_hw_breakpoint { | ||
| 55 | uint32_t version; | ||
| 56 | #define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x1 | ||
| 57 | #define PPC_BREAKPOINT_TRIGGER_READ 0x2 | ||
| 58 | #define PPC_BREAKPOINT_TRIGGER_WRITE 0x4 | ||
| 59 | uint32_t trigger_type; /* only some combinations allowed */ | ||
| 60 | #define PPC_BREAKPOINT_MODE_EXACT 0x0 | ||
| 61 | #define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x1 | ||
| 62 | #define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x2 | ||
| 63 | #define PPC_BREAKPOINT_MODE_MASK 0x3 | ||
| 64 | uint32_t addr_mode; /* address match mode */ | ||
| 65 | |||
| 66 | #define PPC_BREAKPOINT_CONDITION_MODE 0x3 | ||
| 67 | #define PPC_BREAKPOINT_CONDITION_NONE 0x0 | ||
| 68 | #define PPC_BREAKPOINT_CONDITION_AND 0x1 | ||
| 69 | #define PPC_BREAKPOINT_CONDITION_EXACT 0x1 /* different name for the same thing as above */ | ||
| 70 | #define PPC_BREAKPOINT_CONDITION_OR 0x2 | ||
| 71 | #define PPC_BREAKPOINT_CONDITION_AND_OR 0x3 | ||
| 72 | #define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000 /* byte enable bits */ | ||
| 73 | #define PPC_BREAKPOINT_CONDITION_BE(n) (1<<((n)+16)) | ||
| 74 | uint32_t condition_mode; /* break/watchpoint condition flags */ | ||
| 75 | |||
| 76 | uint64_t addr; | ||
| 77 | uint64_t addr2; | ||
| 78 | uint64_t condition_value; | ||
| 79 | }; | ||
| 80 | |||
| 81 | A request specifies one event, not necessarily just one register to be set. | ||
| 82 | For instance, if the request is for a watchpoint with a condition, both the | ||
| 83 | DAC and DVC registers will be set in the same request. | ||
| 84 | |||
| 85 | With this GDB can ask for all kinds of hardware breakpoints and watchpoints | ||
| 86 | that the BookE supports. COMEFROM breakpoints available in server processors | ||
| 87 | are not contemplated, but that is out of the scope of this work. | ||
| 88 | |||
| 89 | ptrace will return an integer (handle) uniquely identifying the breakpoint or | ||
| 90 | watchpoint just created. This integer will be used in the PTRACE_DELHWDEBUG | ||
| 91 | request to ask for its removal. Return -ENOSPC if the requested breakpoint | ||
| 92 | can't be allocated on the registers. | ||
| 93 | |||
| 94 | Some examples of using the structure to: | ||
| 95 | |||
| 96 | - set a breakpoint in the first breakpoint register:: | ||
| 97 | |||
| 98 | p.version = PPC_DEBUG_CURRENT_VERSION; | ||
| 99 | p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE; | ||
| 100 | p.addr_mode = PPC_BREAKPOINT_MODE_EXACT; | ||
| 101 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | ||
| 102 | p.addr = (uint64_t) address; | ||
| 103 | p.addr2 = 0; | ||
| 104 | p.condition_value = 0; | ||
| 105 | |||
| 106 | - set a watchpoint which triggers on reads in the second watchpoint register:: | ||
| 107 | |||
| 108 | p.version = PPC_DEBUG_CURRENT_VERSION; | ||
| 109 | p.trigger_type = PPC_BREAKPOINT_TRIGGER_READ; | ||
| 110 | p.addr_mode = PPC_BREAKPOINT_MODE_EXACT; | ||
| 111 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | ||
| 112 | p.addr = (uint64_t) address; | ||
| 113 | p.addr2 = 0; | ||
| 114 | p.condition_value = 0; | ||
| 115 | |||
| 116 | - set a watchpoint which triggers only with a specific value:: | ||
| 117 | |||
| 118 | p.version = PPC_DEBUG_CURRENT_VERSION; | ||
| 119 | p.trigger_type = PPC_BREAKPOINT_TRIGGER_READ; | ||
| 120 | p.addr_mode = PPC_BREAKPOINT_MODE_EXACT; | ||
| 121 | p.condition_mode = PPC_BREAKPOINT_CONDITION_AND | PPC_BREAKPOINT_CONDITION_BE_ALL; | ||
| 122 | p.addr = (uint64_t) address; | ||
| 123 | p.addr2 = 0; | ||
| 124 | p.condition_value = (uint64_t) condition; | ||
| 125 | |||
| 126 | - set a ranged hardware breakpoint:: | ||
| 127 | |||
| 128 | p.version = PPC_DEBUG_CURRENT_VERSION; | ||
| 129 | p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE; | ||
| 130 | p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE; | ||
| 131 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | ||
| 132 | p.addr = (uint64_t) begin_range; | ||
| 133 | p.addr2 = (uint64_t) end_range; | ||
| 134 | p.condition_value = 0; | ||
| 135 | |||
| 136 | - set a watchpoint in server processors (BookS):: | ||
| 137 | |||
| 138 | p.version = 1; | ||
| 139 | p.trigger_type = PPC_BREAKPOINT_TRIGGER_RW; | ||
| 140 | p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE; | ||
| 141 | or | ||
| 142 | p.addr_mode = PPC_BREAKPOINT_MODE_EXACT; | ||
| 143 | |||
| 144 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | ||
| 145 | p.addr = (uint64_t) begin_range; | ||
| 146 | /* For PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE addr2 needs to be specified, where | ||
| 147 | * addr2 - addr <= 8 Bytes. | ||
| 148 | */ | ||
| 149 | p.addr2 = (uint64_t) end_range; | ||
| 150 | p.condition_value = 0; | ||
| 151 | |||
| 152 | 3. PTRACE_DELHWDEBUG | ||
| 153 | |||
| 154 | Takes an integer which identifies an existing breakpoint or watchpoint | ||
| 155 | (i.e., the value returned from PTRACE_SETHWDEBUG), and deletes the | ||
| 156 | corresponding breakpoint or watchpoint.. | ||
| @@ -1,151 +0,0 @@ | |||
| 1 | GDB intends to support the following hardware debug features of BookE | ||
| 2 | processors: | ||
| 3 | |||
| 4 | 4 hardware breakpoints (IAC) | ||
| 5 | 2 hardware watchpoints (read, write and read-write) (DAC) | ||
| 6 | 2 value conditions for the hardware watchpoints (DVC) | ||
| 7 | |||
| 8 | For that, we need to extend ptrace so that GDB can query and set these | ||
| 9 | resources. Since we're extending, we're trying to create an interface | ||
| 10 | that's extendable and that covers both BookE and server processors, so | ||
| 11 | that GDB doesn't need to special-case each of them. We added the | ||
| 12 | following 3 new ptrace requests. | ||
| 13 | |||
| 14 | 1. PTRACE_PPC_GETHWDEBUGINFO | ||
| 15 | |||
| 16 | Query for GDB to discover the hardware debug features. The main info to | ||
| 17 | be returned here is the minimum alignment for the hardware watchpoints. | ||
| 18 | BookE processors don't have restrictions here, but server processors have | ||
| 19 | an 8-byte alignment restriction for hardware watchpoints. We'd like to avoid | ||
| 20 | adding special cases to GDB based on what it sees in AUXV. | ||
| 21 | |||
| 22 | Since we're at it, we added other useful info that the kernel can return to | ||
| 23 | GDB: this query will return the number of hardware breakpoints, hardware | ||
| 24 | watchpoints and whether it supports a range of addresses and a condition. | ||
| 25 | The query will fill the following structure provided by the requesting process: | ||
| 26 | |||
| 27 | struct ppc_debug_info { | ||
| 28 | unit32_t version; | ||
| 29 | unit32_t num_instruction_bps; | ||
| 30 | unit32_t num_data_bps; | ||
| 31 | unit32_t num_condition_regs; | ||
| 32 | unit32_t data_bp_alignment; | ||
| 33 | unit32_t sizeof_condition; /* size of the DVC register */ | ||
| 34 | uint64_t features; /* bitmask of the individual flags */ | ||
| 35 | }; | ||
| 36 | |||
| 37 | features will have bits indicating whether there is support for: | ||
| 38 | |||
| 39 | #define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x1 | ||
| 40 | #define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x2 | ||
| 41 | #define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x4 | ||
| 42 | #define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x8 | ||
| 43 | #define PPC_DEBUG_FEATURE_DATA_BP_DAWR 0x10 | ||
| 44 | |||
| 45 | 2. PTRACE_SETHWDEBUG | ||
| 46 | |||
| 47 | Sets a hardware breakpoint or watchpoint, according to the provided structure: | ||
| 48 | |||
| 49 | struct ppc_hw_breakpoint { | ||
| 50 | uint32_t version; | ||
| 51 | #define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x1 | ||
| 52 | #define PPC_BREAKPOINT_TRIGGER_READ 0x2 | ||
| 53 | #define PPC_BREAKPOINT_TRIGGER_WRITE 0x4 | ||
| 54 | uint32_t trigger_type; /* only some combinations allowed */ | ||
| 55 | #define PPC_BREAKPOINT_MODE_EXACT 0x0 | ||
| 56 | #define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x1 | ||
| 57 | #define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x2 | ||
| 58 | #define PPC_BREAKPOINT_MODE_MASK 0x3 | ||
| 59 | uint32_t addr_mode; /* address match mode */ | ||
| 60 | |||
| 61 | #define PPC_BREAKPOINT_CONDITION_MODE 0x3 | ||
| 62 | #define PPC_BREAKPOINT_CONDITION_NONE 0x0 | ||
| 63 | #define PPC_BREAKPOINT_CONDITION_AND 0x1 | ||
| 64 | #define PPC_BREAKPOINT_CONDITION_EXACT 0x1 /* different name for the same thing as above */ | ||
| 65 | #define PPC_BREAKPOINT_CONDITION_OR 0x2 | ||
| 66 | #define PPC_BREAKPOINT_CONDITION_AND_OR 0x3 | ||
| 67 | #define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000 /* byte enable bits */ | ||
| 68 | #define PPC_BREAKPOINT_CONDITION_BE(n) (1<<((n)+16)) | ||
| 69 | uint32_t condition_mode; /* break/watchpoint condition flags */ | ||
| 70 | |||
| 71 | uint64_t addr; | ||
| 72 | uint64_t addr2; | ||
| 73 | uint64_t condition_value; | ||
| 74 | }; | ||
| 75 | |||
| 76 | A request specifies one event, not necessarily just one register to be set. | ||
| 77 | For instance, if the request is for a watchpoint with a condition, both the | ||
| 78 | DAC and DVC registers will be set in the same request. | ||
| 79 | |||
| 80 | With this GDB can ask for all kinds of hardware breakpoints and watchpoints | ||
| 81 | that the BookE supports. COMEFROM breakpoints available in server processors | ||
| 82 | are not contemplated, but that is out of the scope of this work. | ||
| 83 | |||
| 84 | ptrace will return an integer (handle) uniquely identifying the breakpoint or | ||
| 85 | watchpoint just created. This integer will be used in the PTRACE_DELHWDEBUG | ||
| 86 | request to ask for its removal. Return -ENOSPC if the requested breakpoint | ||
| 87 | can't be allocated on the registers. | ||
| 88 | |||
| 89 | Some examples of using the structure to: | ||
| 90 | |||
| 91 | - set a breakpoint in the first breakpoint register | ||
| 92 | |||
| 93 | p.version = PPC_DEBUG_CURRENT_VERSION; | ||
| 94 | p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE; | ||
| 95 | p.addr_mode = PPC_BREAKPOINT_MODE_EXACT; | ||
| 96 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | ||
| 97 | p.addr = (uint64_t) address; | ||
| 98 | p.addr2 = 0; | ||
| 99 | p.condition_value = 0; | ||
| 100 | |||
| 101 | - set a watchpoint which triggers on reads in the second watchpoint register | ||
| 102 | |||
| 103 | p.version = PPC_DEBUG_CURRENT_VERSION; | ||
| 104 | p.trigger_type = PPC_BREAKPOINT_TRIGGER_READ; | ||
| 105 | p.addr_mode = PPC_BREAKPOINT_MODE_EXACT; | ||
| 106 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | ||
| 107 | p.addr = (uint64_t) address; | ||
| 108 | p.addr2 = 0; | ||
| 109 | p.condition_value = 0; | ||
| 110 | |||
| 111 | - set a watchpoint which triggers only with a specific value | ||
| 112 | |||
| 113 | p.version = PPC_DEBUG_CURRENT_VERSION; | ||
| 114 | p.trigger_type = PPC_BREAKPOINT_TRIGGER_READ; | ||
| 115 | p.addr_mode = PPC_BREAKPOINT_MODE_EXACT; | ||
| 116 | p.condition_mode = PPC_BREAKPOINT_CONDITION_AND | PPC_BREAKPOINT_CONDITION_BE_ALL; | ||
| 117 | p.addr = (uint64_t) address; | ||
| 118 | p.addr2 = 0; | ||
| 119 | p.condition_value = (uint64_t) condition; | ||
| 120 | |||
| 121 | - set a ranged hardware breakpoint | ||
| 122 | |||
| 123 | p.version = PPC_DEBUG_CURRENT_VERSION; | ||
| 124 | p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE; | ||
| 125 | p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE; | ||
| 126 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | ||
| 127 | p.addr = (uint64_t) begin_range; | ||
| 128 | p.addr2 = (uint64_t) end_range; | ||
| 129 | p.condition_value = 0; | ||
| 130 | |||
| 131 | - set a watchpoint in server processors (BookS) | ||
| 132 | |||
| 133 | p.version = 1; | ||
| 134 | p.trigger_type = PPC_BREAKPOINT_TRIGGER_RW; | ||
| 135 | p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE; | ||
| 136 | or | ||
| 137 | p.addr_mode = PPC_BREAKPOINT_MODE_EXACT; | ||
| 138 | |||
| 139 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | ||
| 140 | p.addr = (uint64_t) begin_range; | ||
| 141 | /* For PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE addr2 needs to be specified, where | ||
| 142 | * addr2 - addr <= 8 Bytes. | ||
| 143 | */ | ||
| 144 | p.addr2 = (uint64_t) end_range; | ||
| 145 | p.condition_value = 0; | ||
| 146 | |||
| 147 | 3. PTRACE_DELHWDEBUG | ||
| 148 | |||
| 149 | Takes an integer which identifies an existing breakpoint or watchpoint | ||
| 150 | (i.e., the value returned from PTRACE_SETHWDEBUG), and deletes the | ||
| 151 | corresponding breakpoint or watchpoint.. | ||
| @@ -1,23 +1,23 @@ | |||
| 1 | Freescale QUICC Engine Firmware Uploading | 1 | ========================================= |
| 2 | ----------------------------------------- | 2 | Freescale QUICC Engine Firmware Uploading |
| 3 | ========================================= | ||
| 3 | 4 | ||
| 4 | (c) 2007 Timur Tabi <timur at freescale.com>, | 5 | (c) 2007 Timur Tabi <timur at freescale.com>, |
| 5 | Freescale Semiconductor | 6 | Freescale Semiconductor |
| 6 | 7 | ||
| 7 | Table of Contents | 8 | .. Table of Contents |
| 8 | ================= | ||
| 9 | 9 | ||
| 10 | I - Software License for Firmware | 10 | I - Software License for Firmware |
| 11 | 11 | ||
| 12 | II - Microcode Availability | 12 | II - Microcode Availability |
| 13 | 13 | ||
| 14 | III - Description and Terminology | 14 | III - Description and Terminology |
| 15 | 15 | ||
| 16 | IV - Microcode Programming Details | 16 | IV - Microcode Programming Details |
| 17 | 17 | ||
| 18 | V - Firmware Structure Layout | 18 | V - Firmware Structure Layout |
| 19 | 19 | ||
| 20 | VI - Sample Code for Creating Firmware Files | 20 | VI - Sample Code for Creating Firmware Files |
| 21 | 21 | ||
| 22 | Revision Information | 22 | Revision Information |
| 23 | ==================== | 23 | ==================== |
| @@ -39,7 +39,7 @@ http://opensource.freescale.com. For other firmware files, please contact · 15 unmodified lines | |||
| 39 | your Freescale representative or your operating system vendor. | 39 | your Freescale representative or your operating system vendor. |
| 40 | 40 | ||
| 41 | III - Description and Terminology | 41 | III - Description and Terminology |
| 42 | ================================ | 42 | ================================= |
| 43 | 43 | ||
| 44 | In this document, the term 'microcode' refers to the sequence of 32-bit | 44 | In this document, the term 'microcode' refers to the sequence of 32-bit |
| 45 | integers that compose the actual QE microcode. | 45 | integers that compose the actual QE microcode. |
| @@ -89,7 +89,7 @@ being fixed in the RAM package utilizing they should be activated. This data · 43 unmodified lines | |||
| 89 | structure signals the microcode which of these virtual traps is active. | 89 | structure signals the microcode which of these virtual traps is active. |
| 90 | 90 | ||
| 91 | This structure contains 6 words that the application should copy to some | 91 | This structure contains 6 words that the application should copy to some |
| 92 | specific been defined. This table describes the structure. | 92 | specific been defined. This table describes the structure:: |
| 93 | 93 | ||
| 94 | --------------------------------------------------------------- | 94 | --------------------------------------------------------------- |
| 95 | | Offset in | | Destination Offset | Size of | | 95 | | Offset in | | Destination Offset | Size of | |
| @@ -119,7 +119,7 @@ Extended Modes · 23 unmodified lines | |||
| 119 | This is a double word bit array (64 bits) that defines special functionality | 119 | This is a double word bit array (64 bits) that defines special functionality |
| 120 | which has an impact on the software drivers. Each bit has its own impact | 120 | which has an impact on the software drivers. Each bit has its own impact |
| 121 | and has special instructions for the s/w associated with it. This structure is | 121 | and has special instructions for the s/w associated with it. This structure is |
| 122 | described in this table: | 122 | described in this table:: |
| 123 | 123 | ||
| 124 | ----------------------------------------------------------------------- | 124 | ----------------------------------------------------------------------- |
| 125 | | Bit # | Name | Description | | 125 | | Bit # | Name | Description | |
| @@ -220,7 +220,8 @@ The 'model' field is a 16-bit number that matches the actual SOC. The · 94 unmodified lines | |||
| 220 | 'major' and 'minor' fields are the major and minor revision numbers, | 220 | 'major' and 'minor' fields are the major and minor revision numbers, |
| 221 | respectively, of the SOC. | 221 | respectively, of the SOC. |
| 222 | 222 | ||
| 223 | For example, to match the 8323, revision 1.0: | 223 | For example, to match the 8323, revision 1.0:: |
| 224 | |||
| 224 | soc.model = 8323 | 225 | soc.model = 8323 |
| 225 | soc.major = 1 | 226 | soc.major = 1 |
| 226 | soc.minor = 0 | 227 | soc.minor = 0 |
| @@ -273,10 +274,10 @@ library and available to any driver that calles qe_get_firmware_info(). · 46 unmodified lines | |||
| 273 | 'reserved'. | 274 | 'reserved'. |
| 274 | 275 | ||
| 275 | After the last microcode is a 32-bit CRC. It can be calculated using | 276 | After the last microcode is a 32-bit CRC. It can be calculated using |
| 276 | this algorithm: | 277 | this algorithm:: |
| 277 | 278 | ||
| 278 | u32 crc32(const u8 *p, unsigned int len) | 279 | u32 crc32(const u8 *p, unsigned int len) |
| 279 | { | 280 | { |
| 280 | unsigned int i; | 281 | unsigned int i; |
| 281 | u32 crc = 0; | 282 | u32 crc = 0; |
| 282 | 283 | ||
| @@ -286,7 +287,7 @@ u32 crc32(const u8 *p, unsigned int len) · 3 unmodified lines | |||
| 286 | crc = (crc >> 1) ^ ((crc & 1) ? 0xedb88320 : 0); | 287 | crc = (crc >> 1) ^ ((crc & 1) ? 0xedb88320 : 0); |
| 287 | } | 288 | } |
| 288 | return crc; | 289 | return crc; |
| 289 | } | 290 | } |
| 290 | 291 | ||
| 291 | VI - Sample Code for Creating Firmware Files | 292 | VI - Sample Code for Creating Firmware Files |
| 292 | ============================================ | 293 | ============================================ |
| @@ -5,12 +5,12 @@ Power Architecture 64-bit Linux system call ABI · 4 unmodified lines | |||
| 5 | syscall | 5 | syscall |
| 6 | ======= | 6 | ======= |
| 7 | 7 | ||
| 8 | syscall calling sequence[*] matches the Power Architecture 64-bit ELF ABI | 8 | syscall calling sequence\ [1]_ matches the Power Architecture 64-bit ELF ABI |
| 9 | specification C function calling sequence, including register preservation | 9 | specification C function calling sequence, including register preservation |
| 10 | rules, with the following differences. | 10 | rules, with the following differences. |
| 11 | 11 | ||
| 12 | [*] Some syscalls (typically low-level management functions) may have | 12 | .. [1] Some syscalls (typically low-level management functions) may have |
| 13 | different calling sequences (e.g., rt_sigreturn). | 13 | different calling sequences (e.g., rt_sigreturn). |
| 14 | 14 | ||
| 15 | Parameters and return value | 15 | Parameters and return value |
| 16 | --------------------------- | 16 | --------------------------- |
| @@ -33,12 +33,14 @@ Register preservation rules · 16 unmodified lines | |||
| 33 | Register preservation rules match the ELF ABI calling sequence with the | 33 | Register preservation rules match the ELF ABI calling sequence with the |
| 34 | following differences: | 34 | following differences: |
| 35 | 35 | ||
| 36 | r0: Volatile. (System call number.) | 36 | =========== ============= ======================================== |
| 37 | r3: Volatile. (Parameter 1, and return value.) | 37 | r0 Volatile (System call number.) |
| 38 | r4-r8: Volatile. (Parameters 2-6.) | 38 | r3 Volatile (Parameter 1, and return value.) |
| 39 | cr0: Volatile (cr0.SO is the return error condition) | 39 | r4-r8 Volatile (Parameters 2-6.) |
| 40 | cr1, cr5-7: Nonvolatile. | 40 | cr0 Volatile (cr0.SO is the return error condition) |
| 41 | lr: Nonvolatile. | 41 | cr1, cr5-7 Nonvolatile |
| 42 | lr Nonvolatile | ||
| 43 | =========== ============= ======================================== | ||
| 42 | 44 | ||
| 43 | All floating point and vector data registers as well as control and status | 45 | All floating point and vector data registers as well as control and status |
| 44 | registers are nonvolatile. | 46 | registers are nonvolatile. |
| @@ -90,9 +92,12 @@ The vsyscall may or may not use the caller's stack frame save areas. · 45 unmodified lines | |||
| 90 | 92 | ||
| 91 | Register preservation rules | 93 | Register preservation rules |
| 92 | --------------------------- | 94 | --------------------------- |
| 93 | r0: Volatile. | 95 | |
| 94 | cr1, cr5-7: Volatile. | 96 | =========== ======== |
| 95 | lr: Volatile. | 97 | r0 Volatile |
| 98 | cr1, cr5-7 Volatile | ||
| 99 | lr Volatile | ||
| 100 | =========== ======== | ||
| 96 | 101 | ||
| 97 | Invocation | 102 | Invocation |
| 98 | ---------- | 103 | ---------- |
| @@ -1,3 +1,4 @@ | |||
| 1 | ============================ | ||
| 1 | Transactional Memory support | 2 | Transactional Memory support |
| 2 | ============================ | 3 | ============================ |
| 3 | 4 | ||
| @@ -17,29 +18,29 @@ instructions are presented to delimit transactions; transactions are · 13 unmodified lines | |||
| 17 | guaranteed to either complete atomically or roll back and undo any partial | 18 | guaranteed to either complete atomically or roll back and undo any partial |
| 18 | changes. | 19 | changes. |
| 19 | 20 | ||
| 20 | A simple transaction looks like this: | 21 | A simple transaction looks like this:: |
| 21 | 22 | ||
| 22 | begin_move_money: | 23 | begin_move_money: |
| 23 | tbegin | 24 | tbegin |
| 24 | beq abort_handler | 25 | beq abort_handler |
| 25 | 26 | ||
| 26 | ld r4, SAVINGS_ACCT(r3) | 27 | ld r4, SAVINGS_ACCT(r3) |
| 27 | ld r5, CURRENT_ACCT(r3) | 28 | ld r5, CURRENT_ACCT(r3) |
| 28 | subi r5, r5, 1 | 29 | subi r5, r5, 1 |
| 29 | addi r4, r4, 1 | 30 | addi r4, r4, 1 |
| 30 | std r4, SAVINGS_ACCT(r3) | 31 | std r4, SAVINGS_ACCT(r3) |
| 31 | std r5, CURRENT_ACCT(r3) | 32 | std r5, CURRENT_ACCT(r3) |
| 32 | 33 | ||
| 33 | tend | 34 | tend |
| 34 | 35 | ||
| 35 | b continue | 36 | b continue |
| 36 | 37 | ||
| 37 | abort_handler: | 38 | abort_handler: |
| 38 | ... test for odd failures ... | 39 | ... test for odd failures ... |
| 39 | 40 | ||
| 40 | /* Retry the transaction if it failed because it conflicted with | 41 | /* Retry the transaction if it failed because it conflicted with |
| 41 | * someone else: */ | 42 | * someone else: */ |
| 42 | b begin_move_money | 43 | b begin_move_money |
| 43 | 44 | ||
| 44 | 45 | ||
| 45 | The 'tbegin' instruction denotes the start point, and 'tend' the end point. | 46 | The 'tbegin' instruction denotes the start point, and 'tend' the end point. |
| @@ -123,7 +124,7 @@ Transaction-aware signal handlers can read the transactional register state · 77 unmodified lines | |||
| 123 | from the second ucontext. This will be necessary for crash handlers to | 124 | from the second ucontext. This will be necessary for crash handlers to |
| 124 | determine, for example, the address of the instruction causing the SIGSEGV. | 125 | determine, for example, the address of the instruction causing the SIGSEGV. |
| 125 | 126 | ||
| 126 | Example signal handler: | 127 | Example signal handler:: |
| 127 | 128 | ||
| 128 | void crash_handler(int sig, siginfo_t *si, void *uc) | 129 | void crash_handler(int sig, siginfo_t *si, void *uc) |
| 129 | { | 130 | { |
| @@ -133,9 +134,9 @@ Example signal handler: · 3 unmodified lines | |||
| 133 | if (ucp_link) { | 134 | if (ucp_link) { |
| 134 | u64 msr = ucp->uc_mcontext.regs->msr; | 135 | u64 msr = ucp->uc_mcontext.regs->msr; |
| 135 | /* May have transactional ucontext! */ | 136 | /* May have transactional ucontext! */ |
| 136 | #ifndef __powerpc64__ | 137 | #ifndef __powerpc64__ |
| 137 | msr |= ((u64)transactional_ucp->uc_mcontext.regs->msr) << 32; | 138 | msr |= ((u64)transactional_ucp->uc_mcontext.regs->msr) << 32; |
| 138 | #endif | 139 | #endif |
| 139 | if (MSR_TM_ACTIVE(msr)) { | 140 | if (MSR_TM_ACTIVE(msr)) { |
| 140 | /* Yes, we crashed during a transaction. Oops. */ | 141 | /* Yes, we crashed during a transaction. Oops. */ |
| 141 | fprintf(stderr, "Transaction to be restarted at 0x%llx, but " | 142 | fprintf(stderr, "Transaction to be restarted at 0x%llx, but " |
| @@ -176,6 +177,7 @@ Failure cause codes used by kernel · 34 unmodified lines | |||
| 176 | These are defined in <asm/reg.h>, and distinguish different reasons why the | 177 | These are defined in <asm/reg.h>, and distinguish different reasons why the |
| 177 | kernel aborted a transaction: | 178 | kernel aborted a transaction: |
| 178 | 179 | ||
| 180 | ====================== ================================ | ||
| 179 | TM_CAUSE_RESCHED Thread was rescheduled. | 181 | TM_CAUSE_RESCHED Thread was rescheduled. |
| 180 | TM_CAUSE_TLBI Software TLB invalid. | 182 | TM_CAUSE_TLBI Software TLB invalid. |
| 181 | TM_CAUSE_FAC_UNAV FP/VEC/VSX unavailable trap. | 183 | TM_CAUSE_FAC_UNAV FP/VEC/VSX unavailable trap. |
| @@ -184,6 +186,7 @@ kernel aborted a transaction: · 2 unmodified lines | |||
| 184 | TM_CAUSE_MISC Currently unused. | 186 | TM_CAUSE_MISC Currently unused. |
| 185 | TM_CAUSE_ALIGNMENT Alignment fault. | 187 | TM_CAUSE_ALIGNMENT Alignment fault. |
| 186 | TM_CAUSE_EMULATE Emulation that touched memory. | 188 | TM_CAUSE_EMULATE Emulation that touched memory. |
| 189 | ====================== ================================ | ||
| 187 | 190 | ||
| 188 | These can be checked by the user program's abort handler as TEXASR[0:7]. If | 191 | These can be checked by the user program's abort handler as TEXASR[0:7]. If |
| 189 | bit 7 is set, it indicates that the error is consider persistent. For example | 192 | bit 7 is set, it indicates that the error is consider persistent. For example |
| @@ -203,7 +206,7 @@ POWER9 · 13 unmodified lines | |||
| 203 | ====== | 206 | ====== |
| 204 | 207 | ||
| 205 | TM on POWER9 has issues with storing the complete register state. This | 208 | TM on POWER9 has issues with storing the complete register state. This |
| 206 | is described in this commit: | 209 | is described in this commit:: |
| 207 | 210 | ||
| 208 | commit 4bb3c7a0208fc13ca70598efd109901a7cd45ae7 | 211 | commit 4bb3c7a0208fc13ca70598efd109901a7cd45ae7 |
| 209 | Author: Paul Mackerras <paulus@ozlabs.org> | 212 | Author: Paul Mackerras <paulus@ozlabs.org> |
| @@ -1,10 +0,0 @@ | |||
| 1 | # -*- coding: utf-8; mode: python -*- | ||
| 2 | |||
| 3 | project = 'Linux Kernel Development Documentation' | ||
| 4 | |||
| 5 | tags.add("subproject") | ||
| 6 | |||
| 7 | latex_documents = [ | ||
| 8 | ('index', 'process.tex', 'Linux Kernel Development Documentation', | ||
| 9 | 'The kernel development community', 'manual'), | ||
| 10 | ] | ||
| @@ -119,3 +119,17 @@ array may exceed the remaining memory in the stack segment. This could · 118 unmodified lines | |||
| 119 | lead to a crash, possible overwriting sensitive contents at the end of the | 119 | lead to a crash, possible overwriting sensitive contents at the end of the |
| 120 | stack (when built without `CONFIG_THREAD_INFO_IN_TASK=y`), or overwriting | 120 | stack (when built without `CONFIG_THREAD_INFO_IN_TASK=y`), or overwriting |
| 121 | memory adjacent to the stack (when built without `CONFIG_VMAP_STACK=y`) | 121 | memory adjacent to the stack (when built without `CONFIG_VMAP_STACK=y`) |
| 122 | |||
| 123 | Implicit switch case fall-through | ||
| 124 | --------------------------------- | ||
| 125 | The C language allows switch cases to "fall through" when | ||
| 126 | a "break" statement is missing at the end of a case. This, | ||
| 127 | however, introduces ambiguity in the code, as it's not always | ||
| 128 | clear if the missing break is intentional or a bug. As there | ||
| 129 | have been a long list of flaws `due to missing "break" statements | ||
| 130 | <https://cwe.mitre.org/data/definitions/484.html>`_, we no longer allow | ||
| 131 | "implicit fall-through". In order to identify an intentional fall-through | ||
| 132 | case, we have adopted the marking used by static analyzers: a comment | ||
| 133 | saying `/* Fall through */`. Once the C++17 `__attribute__((fallthrough))` | ||
| 134 | is more widely handled by C compilers, static analyzers, and IDEs, we can | ||
| 135 | switch to using that instead. | ||
| @@ -180,6 +180,13 @@ The process of how these work together. · 179 unmodified lines | |||
| 180 | add it to an iommu_group and a vfio_group. Then we could pass through | 180 | add it to an iommu_group and a vfio_group. Then we could pass through |
| 181 | the mdev to a guest. | 181 | the mdev to a guest. |
| 182 | 182 | ||
| 183 | |||
| 184 | VFIO-CCW Regions | ||
| 185 | ---------------- | ||
| 186 | |||
| 187 | The vfio-ccw driver exposes MMIO regions to accept requests from and return | ||
| 188 | results to userspace. | ||
| 189 | |||
| 183 | vfio-ccw I/O region | 190 | vfio-ccw I/O region |
| 184 | ------------------- | 191 | ------------------- |
| 185 | 192 | ||
| @@ -205,6 +212,25 @@ irb_area stores the I/O result. · 19 unmodified lines | |||
| 205 | 212 | ||
| 206 | ret_code stores a return code for each access of the region. | 213 | ret_code stores a return code for each access of the region. |
| 207 | 214 | ||
| 215 | This region is always available. | ||
| 216 | |||
| 217 | vfio-ccw cmd region | ||
| 218 | ------------------- | ||
| 219 | |||
| 220 | The vfio-ccw cmd region is used to accept asynchronous instructions | ||
| 221 | from userspace:: | ||
| 222 | |||
| 223 | #define VFIO_CCW_ASYNC_CMD_HSCH (1 << 0) | ||
| 224 | #define VFIO_CCW_ASYNC_CMD_CSCH (1 << 1) | ||
| 225 | struct ccw_cmd_region { | ||
| 226 | __u32 command; | ||
| 227 | __u32 ret_code; | ||
| 228 | } __packed; | ||
| 229 | |||
| 230 | This region is exposed via region type VFIO_REGION_SUBTYPE_CCW_ASYNC_CMD. | ||
| 231 | |||
| 232 | Currently, CLEAR SUBCHANNEL and HALT SUBCHANNEL use this region. | ||
| 233 | |||
| 208 | vfio-ccw operation details | 234 | vfio-ccw operation details |
| 209 | -------------------------- | 235 | -------------------------- |
| 210 | 236 | ||
| @@ -306,9 +332,8 @@ Together with the corresponding work in QEMU, we can bring the passed · 95 unmodified lines | |||
| 306 | through DASD/ECKD device online in a guest now and use it as a block | 332 | through DASD/ECKD device online in a guest now and use it as a block |
| 307 | device. | 333 | device. |
| 308 | 334 | ||
| 309 | While the current code allows the guest to start channel programs via | 335 | The current code allows the guest to start channel programs via |
| 310 | START SUBCHANNEL, support for HALT SUBCHANNEL or CLEAR SUBCHANNEL is | 336 | START SUBCHANNEL, and to issue HALT SUBCHANNEL and CLEAR SUBCHANNEL. |
| 311 | not yet implemented. | ||
| 312 | 337 | ||
| 313 | vfio-ccw supports classic (command mode) channel I/O only. Transport | 338 | vfio-ccw supports classic (command mode) channel I/O only. Transport |
| 314 | mode (HPF) is not supported. | 339 | mode (HPF) is not supported. |
| @@ -1,10 +0,0 @@ | |||
| 1 | # -*- coding: utf-8; mode: python -*- | ||
| 2 | |||
| 3 | project = "SuperH architecture implementation manual" | ||
| 4 | |||
| 5 | tags.add("subproject") | ||
| 6 | |||
| 7 | latex_documents = [ | ||
| 8 | ('index', 'sh.tex', project, | ||
| 9 | 'The kernel development community', 'manual'), | ||
| 10 | ] | ||
| @@ -1,10 +0,0 @@ | |||
| 1 | # -*- coding: utf-8; mode: python -*- | ||
| 2 | |||
| 3 | project = "Linux Sound Subsystem Documentation" | ||
| 4 | |||
| 5 | tags.add("subproject") | ||
| 6 | |||
| 7 | latex_documents = [ | ||
| 8 | ('index', 'sound.tex', project, | ||
| 9 | 'The kernel development community', 'manual'), | ||
| 10 | ] | ||
| @@ -21,6 +21,29 @@ def loadConfig(namespace): · 20 unmodified lines | |||
| 21 | and os.path.normpath(namespace["__file__"]) != os.path.normpath(config_file) ): | 21 | and os.path.normpath(namespace["__file__"]) != os.path.normpath(config_file) ): |
| 22 | config_file = os.path.abspath(config_file) | 22 | config_file = os.path.abspath(config_file) |
| 23 | 23 | ||
| 24 | # Let's avoid one conf.py file just due to latex_documents | ||
| 25 | start = config_file.find('Documentation/') | ||
| 26 | if start >= 0: | ||
| 27 | start = config_file.find('/', start + 1) | ||
| 28 | |||
| 29 | end = config_file.rfind('/') | ||
| 30 | if start >= 0 and end > 0: | ||
| 31 | dir = config_file[start + 1:end] | ||
| 32 | |||
| 33 | print("source directory: %s" % dir) | ||
| 34 | new_latex_docs = [] | ||
| 35 | latex_documents = namespace['latex_documents'] | ||
| 36 | |||
| 37 | for l in latex_documents: | ||
| 38 | if l[0].find(dir + '/') == 0: | ||
| 39 | has = True | ||
| 40 | fn = l[0][len(dir) + 1:] | ||
| 41 | new_latex_docs.append((fn, l[1], l[2], l[3], l[4])) | ||
| 42 | break | ||
| 43 | |||
| 44 | namespace['latex_documents'] = new_latex_docs | ||
| 45 | |||
| 46 | # If there is an extra conf.py file, load it | ||
| 24 | if os.path.isfile(config_file): | 47 | if os.path.isfile(config_file): |
| 25 | sys.stdout.write("load additional sphinx-config: %s\n" % config_file) | 48 | sys.stdout.write("load additional sphinx-config: %s\n" % config_file) |
| 26 | config = namespace.copy() | 49 | config = namespace.copy() |
| @@ -29,4 +52,6 @@ def loadConfig(namespace): · 2 unmodified lines | |||
| 29 | del config['__file__'] | 52 | del config['__file__'] |
| 30 | namespace.update(config) | 53 | namespace.update(config) |
| 31 | else: | 54 | else: |
| 32 | sys.stderr.write("WARNING: additional sphinx-config not found: %s\n" % config_file) | 55 | config = namespace.copy() |
| 56 | config['tags'].add("subproject") | ||
| 57 | namespace.update(config) | ||
| @@ -242,8 +242,9 @@ del kernel: · 241 unmodified lines | |||
| 242 | * Per inserire blocchi di testo con caratteri a dimensione fissa (codici di | 242 | * Per inserire blocchi di testo con caratteri a dimensione fissa (codici di |
| 243 | esempio, casi d'uso, eccetera): utilizzate ``::`` quando non è necessario | 243 | esempio, casi d'uso, eccetera): utilizzate ``::`` quando non è necessario |
| 244 | evidenziare la sintassi, specialmente per piccoli frammenti; invece, | 244 | evidenziare la sintassi, specialmente per piccoli frammenti; invece, |
| 245 | utilizzate ``.. code-block:: <language>`` per blocchi di più lunghi che | 245 | utilizzate ``.. code-block:: <language>`` per blocchi più lunghi che |
| 246 | potranno beneficiare dell'avere la sintassi evidenziata. | 246 | beneficeranno della sintassi evidenziata. Per un breve pezzo di codice da |
| 247 | inserire nel testo, usate \`\`. | ||
| 247 | 248 | ||
| 248 | 249 | ||
| 249 | Il dominio C | 250 | Il dominio C |
| @@ -267,12 +268,14 @@ molto comune come ``open`` o ``ioctl``: · 17 unmodified lines | |||
| 267 | 268 | ||
| 268 | Il nome della funzione (per esempio ioctl) rimane nel testo ma il nome del suo | 269 | Il nome della funzione (per esempio ioctl) rimane nel testo ma il nome del suo |
| 269 | riferimento cambia da ``ioctl`` a ``VIDIOC_LOG_STATUS``. Anche la voce | 270 | riferimento cambia da ``ioctl`` a ``VIDIOC_LOG_STATUS``. Anche la voce |
| 270 | nell'indice cambia in ``VIDIOC_LOG_STATUS`` e si potrà quindi fare riferimento | 271 | nell'indice cambia in ``VIDIOC_LOG_STATUS``. |
| 271 | a questa funzione scrivendo: | 272 | |
| 272 | 273 | Notate che per una funzione non c'è bisogno di usare ``c:func:`` per generarne | |
| 273 | .. code-block:: rst | 274 | i riferimenti nella documentazione. Grazie a qualche magica estensione a |
| 274 | 275 | Sphinx, il sistema di generazione della documentazione trasformerà | |
| 275 | :c:func:`VIDIOC_LOG_STATUS` | 276 | automaticamente un riferimento ad una ``funzione()`` in un riferimento |
| 277 | incrociato quando questa ha una voce nell'indice. Se trovate degli usi di | ||
| 278 | ``c:func:`` nella documentazione del kernel, sentitevi liberi di rimuoverli. | ||
| 276 | 279 | ||
| 277 | 280 | ||
| 278 | Tabelle a liste | 281 | Tabelle a liste |
| @@ -27,6 +27,7 @@ Di seguito le guide che ogni sviluppatore dovrebbe leggere. · 26 unmodified lines | |||
| 27 | code-of-conduct | 27 | code-of-conduct |
| 28 | development-process | 28 | development-process |
| 29 | submitting-patches | 29 | submitting-patches |
| 30 | programming-language | ||
| 30 | coding-style | 31 | coding-style |
| 31 | maintainer-pgp-guide | 32 | maintainer-pgp-guide |
| 32 | email-clients | 33 | email-clients |
| @@ -1,6 +1,7 @@ | |||
| 1 | .. include:: ../disclaimer-ita.rst | 1 | .. include:: ../disclaimer-ita.rst |
| 2 | 2 | ||
| 3 | :Original: :ref:`Documentation/process/kernel-docs.rst <kernel_docs>` | 3 | :Original: :ref:`Documentation/process/kernel-docs.rst <kernel_docs>` |
| 4 | :Translator: Federico Vaga <federico.vaga@vaga.pv.it> | ||
| 4 | 5 | ||
| 5 | 6 | ||
| 6 | .. _it_kernel_docs: | 7 | .. _it_kernel_docs: |
| @@ -8,6 +9,10 @@ · 1 unmodified line | |||
| 8 | Indice di documenti per le persone interessate a capire e/o scrivere per il kernel Linux | 9 | Indice di documenti per le persone interessate a capire e/o scrivere per il kernel Linux |
| 9 | ======================================================================================== | 10 | ======================================================================================== |
| 10 | 11 | ||
| 11 | .. warning:: | 12 | .. note:: |
| 12 | 13 | Questo documento contiene riferimenti a documenti in lingua inglese; inoltre | |
| 13 | TODO ancora da tradurre | 14 | utilizza dai campi *ReStructuredText* di supporto alla ricerca e che per |
| 15 | questo motivo è meglio non tradurre al fine di garantirne un corretto | ||
| 16 | utilizzo. | ||
| 17 | Per questi motivi il documento non verrà tradotto. Per favore fate | ||
| 18 | riferimento al documento originale in lingua inglese. | ||
| @@ -248,7 +248,10 @@ possano ricevere la vostra nuova sottochiave:: · 247 unmodified lines | |||
| 248 | kernel. | 248 | kernel. |
| 249 | 249 | ||
| 250 | Se per qualche ragione preferite rimanere con sottochiavi RSA, nel comando | 250 | Se per qualche ragione preferite rimanere con sottochiavi RSA, nel comando |
| 251 | precedente, sostituite "ed25519" con "rsa2048". | 251 | precedente, sostituite "ed25519" con "rsa2048". In aggiunta, se avete |
| 252 | intenzione di usare un dispositivo hardware che non supporta le chiavi | ||
| 253 | ED25519 ECC, come la Nitrokey Pro o la Yubikey, allora dovreste usare | ||
| 254 | "nistp256" al posto di "ed25519". | ||
| 252 | 255 | ||
| 253 | Copia di riserva della chiave primaria per gestire il recupero da disastro | 256 | Copia di riserva della chiave primaria per gestire il recupero da disastro |
| 254 | -------------------------------------------------------------------------- | 257 | -------------------------------------------------------------------------- |
| @@ -449,23 +452,27 @@ implementi le funzionalità delle smartcard. Sul mercato ci sono diverse · 194 unmodified lines | |||
| 449 | soluzioni disponibili: | 452 | soluzioni disponibili: |
| 450 | 453 | ||
| 451 | - `Nitrokey Start`_: è Open hardware e Free Software, è basata sul progetto | 454 | - `Nitrokey Start`_: è Open hardware e Free Software, è basata sul progetto |
| 452 | `GnuK`_ della FSIJ. Ha il supporto per chiavi ECC, ma meno funzionalità di | 455 | `GnuK`_ della FSIJ. Questo è uno dei pochi dispositivi a supportare le chiavi |
| 453 | sicurezza (come la resistenza alla manomissione o alcuni attacchi ad un | 456 | ECC ED25519, ma offre meno funzionalità di sicurezza (come la resistenza |
| 454 | canale laterale). | 457 | alla manomissione o alcuni attacchi ad un canale laterale). |
| 455 | - `Nitrokey Pro`_: è simile alla Nitrokey Start, ma è più resistente alla | 458 | - `Nitrokey Pro`_: è simile alla Nitrokey Start, ma è più resistente alla |
| 456 | manomissione e offre più funzionalità di sicurezza, ma l'ECC. | 459 | manomissione e offre più funzionalità di sicurezza. La Pro 2 supporta la |
| 457 | - `Yubikey 4`_: l'hardware e il software sono proprietari, ma è più economica | 460 | crittografia ECC (NISTP). |
| 461 | - `Yubikey 5`_: l'hardware e il software sono proprietari, ma è più economica | ||
| 458 | della Nitrokey Pro ed è venduta anche con porta USB-C il che è utile con i | 462 | della Nitrokey Pro ed è venduta anche con porta USB-C il che è utile con i |
| 459 | computer portatili più recenti. In aggiunta, offre altre funzionalità di | 463 | computer portatili più recenti. In aggiunta, offre altre funzionalità di |
| 460 | sicurezza come FIDO, U2F, ma non l'ECC | 464 | sicurezza come FIDO, U2F, e ora supporta anche le chiavi ECC (NISTP) |
| 461 | 465 | ||
| 462 | `Su LWN c'è una buona recensione`_ dei modelli elencati qui sopra e altri. | 466 | `Su LWN c'è una buona recensione`_ dei modelli elencati qui sopra e altri. |
| 467 | La scelta dipenderà dal costo, dalla disponibilità nella vostra area | ||
| 468 | geografica e vostre considerazioni sull'hardware aperto/proprietario. | ||
| 469 | |||
| 463 | Se volete usare chiavi ECC, la vostra migliore scelta sul mercato è la | 470 | Se volete usare chiavi ECC, la vostra migliore scelta sul mercato è la |
| 464 | Nitrokey Start. | 471 | Nitrokey Start. |
| 465 | 472 | ||
| 466 | .. _`Nitrokey Start`: https://shop.nitrokey.com/shop/product/nitrokey-start-6 | 473 | .. _`Nitrokey Start`: https://shop.nitrokey.com/shop/product/nitrokey-start-6 |
| 467 | .. _`Nitrokey Pro`: https://shop.nitrokey.com/shop/product/nitrokey-pro-3 | 474 | .. _`Nitrokey Pro 2`: https://shop.nitrokey.com/shop/product/nitrokey-pro-2-3 |
| 468 | .. _`Yubikey 4`: https://www.yubico.com/product/yubikey-4-series/ | 475 | .. _`Yubikey 5`: https://www.yubico.com/product/yubikey-5-overview/ |
| 469 | .. _Gnuk: http://www.fsij.org/doc-gnuk/ | 476 | .. _Gnuk: http://www.fsij.org/doc-gnuk/ |
| 470 | .. _`Su LWN c'è una buona recensione`: https://lwn.net/Articles/736231/ | 477 | .. _`Su LWN c'è una buona recensione`: https://lwn.net/Articles/736231/ |
| 471 | 478 | ||
| @@ -0,0 +1,51 @@ | |||
| 1 | .. include:: ../disclaimer-ita.rst | ||
| 2 | |||
| 3 | :Original: :ref:`Documentation/process/programming-language.rst <programming_language>` | ||
| 4 | :Translator: Federico Vaga <federico.vaga@vaga.pv.it> | ||
| 5 | |||
| 6 | .. _it_programming_language: | ||
| 7 | |||
| 8 | Linguaggio di programmazione | ||
| 9 | ============================ | ||
| 10 | |||
| 11 | Il kernel è scritto nel linguaggio di programmazione C [c-language]_. | ||
| 12 | Più precisamente, il kernel viene compilato con ``gcc`` [gcc]_ usando | ||
| 13 | l'opzione ``-std=gnu89`` [gcc-c-dialect-options]_: il dialetto GNU | ||
| 14 | dello standard ISO C90 (con l'aggiunta di alcune funzionalità da C99) | ||
| 15 | |||
| 16 | Questo dialetto contiene diverse estensioni al linguaggio [gnu-extensions]_, | ||
| 17 | e molte di queste vengono usate sistematicamente dal kernel. | ||
| 18 | |||
| 19 | Il kernel offre un certo livello di supporto per la compilazione con ``clang`` | ||
| 20 | [clang]_ e ``icc`` [icc]_ su diverse architetture, tuttavia in questo momento | ||
| 21 | il supporto non è completo e richiede delle patch aggiuntive. | ||
| 22 | |||
| 23 | Attributi | ||
| 24 | --------- | ||
| 25 | |||
| 26 | Una delle estensioni più comuni e usate nel kernel sono gli attributi | ||
| 27 | [gcc-attribute-syntax]_. Gli attributi permettono di aggiungere una semantica, | ||
| 28 | definita dell'implementazione, alle entità del linguaggio (come le variabili, | ||
| 29 | le funzioni o i tipi) senza dover fare importanti modifiche sintattiche al | ||
| 30 | linguaggio stesso (come l'aggiunta di nuove parole chiave) [n2049]_. | ||
| 31 | |||
| 32 | In alcuni casi, gli attributi sono opzionali (ovvero un compilatore che non | ||
| 33 | dovesse supportarli dovrebbe produrre comunque codice corretto, anche se | ||
| 34 | più lento o che non esegue controlli aggiuntivi durante la compilazione). | ||
| 35 | |||
| 36 | Il kernel definisce alcune pseudo parole chiave (per esempio ``__pure``) | ||
| 37 | in alternativa alla sintassi GNU per gli attributi (per esempio | ||
| 38 | ``__attribute__((__pure__))``) allo scopo di mostrare quali funzionalità si | ||
| 39 | possono usare e/o per accorciare il codice. | ||
| 40 | |||
| 41 | Per maggiori informazioni consultate il file d'intestazione | ||
| 42 | ``include/linux/compiler_attributes.h``. | ||
| 43 | |||
| 44 | .. [c-language] http://www.open-std.org/jtc1/sc22/wg14/www/standards | ||
| 45 | .. [gcc] https://gcc.gnu.org | ||
| 46 | .. [clang] https://clang.llvm.org | ||
| 47 | .. [icc] https://software.intel.com/en-us/c-compilers | ||
| 48 | .. [gcc-c-dialect-options] https://gcc.gnu.org/onlinedocs/gcc/C-Dialect-Options.html | ||
| 49 | .. [gnu-extensions] https://gcc.gnu.org/onlinedocs/gcc/C-Extensions.html | ||
| 50 | .. [gcc-attribute-syntax] https://gcc.gnu.org/onlinedocs/gcc/Attribute-Syntax.html | ||
| 51 | .. [n2049] http://www.open-std.org/jtc1/sc22/wg14/www/docs/n2049.pdf | ||
| @@ -569,7 +569,7 @@ ACQUIRE 는 해당 오퍼레이션의 로드 부분에만 적용되고 RELEASE · 568 unmodified lines | |||
| 569 | 569 | ||
| 570 | [*] 버스 마스터링 DMA 와 일관성에 대해서는 다음을 참고하시기 바랍니다: | 570 | [*] 버스 마스터링 DMA 와 일관성에 대해서는 다음을 참고하시기 바랍니다: |
| 571 | 571 | ||
| 572 | Documentation/PCI/pci.rst | 572 | Documentation/driver-api/pci/pci.rst |
| 573 | Documentation/DMA-API-HOWTO.txt | 573 | Documentation/DMA-API-HOWTO.txt |
| 574 | Documentation/DMA-API.txt | 574 | Documentation/DMA-API.txt |
| 575 | 575 | ||
| @@ -1,10 +0,0 @@ | |||
| 1 | # -*- coding: utf-8; mode: python -*- | ||
| 2 | |||
| 3 | project = "The Linux kernel user-space API guide" | ||
| 4 | |||
| 5 | tags.add("subproject") | ||
| 6 | |||
| 7 | latex_documents = [ | ||
| 8 | ('index', 'userspace-api.tex', project, | ||
| 9 | 'The kernel development community', 'manual'), | ||
| 10 | ] | ||
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| @@ -3781,7 +3781,7 @@ encrypted VMs. · 3780 unmodified lines | |||
| 3781 | 3781 | ||
| 3782 | Currently, this ioctl is used for issuing Secure Encrypted Virtualization | 3782 | Currently, this ioctl is used for issuing Secure Encrypted Virtualization |
| 3783 | (SEV) commands on AMD Processors. The SEV commands are defined in | 3783 | (SEV) commands on AMD Processors. The SEV commands are defined in |
| 3784 | Documentation/virtual/kvm/amd-memory-encryption.rst. | 3784 | Documentation/virt/kvm/amd-memory-encryption.rst. |
| 3785 | 3785 | ||
| 3786 | 4.111 KVM_MEMORY_ENCRYPT_REG_REGION | 3786 | 4.111 KVM_MEMORY_ENCRYPT_REG_REGION |
| 3787 | 3787 | ||
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| @@ -18,7 +18,7 @@ S390: · 17 unmodified lines | |||
| 18 | number in R1. | 18 | number in R1. |
| 19 | 19 | ||
| 20 | For further information on the S390 diagnose call as supported by KVM, | 20 | For further information on the S390 diagnose call as supported by KVM, |
| 21 | refer to Documentation/virtual/kvm/s390-diag.txt. | 21 | refer to Documentation/virt/kvm/s390-diag.txt. |
| 22 | 22 | ||
| 23 | PowerPC: | 23 | PowerPC: |
| 24 | It uses R3-R10 and hypercall number in R11. R4-R11 are used as output registers. | 24 | It uses R3-R10 and hypercall number in R11. R4-R11 are used as output registers. |
| @@ -26,7 +26,7 @@ S390: · 1 unmodified line | |||
| 26 | 26 | ||
| 27 | KVM hypercalls uses 4 byte opcode, that are patched with 'hypercall-instructions' | 27 | KVM hypercalls uses 4 byte opcode, that are patched with 'hypercall-instructions' |
| 28 | property inside the device tree's /hypervisor node. | 28 | property inside the device tree's /hypervisor node. |
| 29 | For more information refer to Documentation/virtual/kvm/ppc-pv.txt | 29 | For more information refer to Documentation/virt/kvm/ppc-pv.txt |
| 30 | 30 | ||
| 31 | MIPS: | 31 | MIPS: |
| 32 | KVM hypercalls use the HYPCALL instruction with code 0 and the hypercall | 32 | KVM hypercalls use the HYPCALL instruction with code 0 and the hypercall |
| @@ -9,3 +9,4 @@ KVM · 8 unmodified lines | |||
| 9 | 9 | ||
| 10 | amd-memory-encryption | 10 | amd-memory-encryption |
| 11 | cpuid | 11 | cpuid |
| 12 | vcpu-requests | ||
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| @@ -298,7 +298,7 @@ Handling a page fault is performed as follows: · 297 unmodified lines | |||
| 298 | vcpu->arch.mmio_gfn, and call the emulator | 298 | vcpu->arch.mmio_gfn, and call the emulator |
| 299 | - If both P bit and R/W bit of error code are set, this could possibly | 299 | - If both P bit and R/W bit of error code are set, this could possibly |
| 300 | be handled as a "fast page fault" (fixed without taking the MMU lock). See | 300 | be handled as a "fast page fault" (fixed without taking the MMU lock). See |
| 301 | the description in Documentation/virtual/kvm/locking.txt. | 301 | the description in Documentation/virt/kvm/locking.txt. |
| 302 | - if needed, walk the guest page tables to determine the guest translation | 302 | - if needed, walk the guest page tables to determine the guest translation |
| 303 | (gva->gpa or ngpa->gpa) | 303 | (gva->gpa or ngpa->gpa) |
| 304 | - if permissions are insufficient, reflect the fault back to the guest | 304 | - if permissions are insufficient, reflect the fault back to the guest |
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| @@ -7,7 +7,7 @@ Review checklist for kvm patches · 6 unmodified lines | |||
| 7 | 2. Patches should be against kvm.git master branch. | 7 | 2. Patches should be against kvm.git master branch. |
| 8 | 8 | ||
| 9 | 3. If the patch introduces or modifies a new userspace API: | 9 | 3. If the patch introduces or modifies a new userspace API: |
| 10 | - the API must be documented in Documentation/virtual/kvm/api.txt | 10 | - the API must be documented in Documentation/virt/kvm/api.txt |
| 11 | - the API must be discoverable using KVM_CHECK_EXTENSION | 11 | - the API must be discoverable using KVM_CHECK_EXTENSION |
| 12 | 12 | ||
| 13 | 4. New state must include support for save/restore. | 13 | 4. New state must include support for save/restore. |
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| @@ -1,10 +0,0 @@ | |||
| 1 | # -*- coding: utf-8; mode: python -*- | ||
| 2 | |||
| 3 | project = "Linux Memory Management Documentation" | ||
| 4 | |||
| 5 | tags.add("subproject") | ||
| 6 | |||
| 7 | latex_documents = [ | ||
| 8 | ('index', 'memory-management.tex', project, | ||
| 9 | 'The kernel development community', 'manual'), | ||
| 10 | ] | ||
| @@ -63,7 +63,7 @@ Last reviewed: 08/20/2018 · 62 unmodified lines | |||
| 63 | and loop forever. This is generally not what a watchdog user wants. | 63 | and loop forever. This is generally not what a watchdog user wants. |
| 64 | 64 | ||
| 65 | For those wishing to learn more please see: | 65 | For those wishing to learn more please see: |
| 66 | Documentation/kdump/kdump.rst | 66 | Documentation/admin-guide/kdump/kdump.rst |
| 67 | Documentation/admin-guide/kernel-parameters.txt (panic=) | 67 | Documentation/admin-guide/kernel-parameters.txt (panic=) |
| 68 | Your Linux Distribution specific documentation. | 68 | Your Linux Distribution specific documentation. |
| 69 | 69 | ||
| @@ -1,10 +0,0 @@ | |||
| 1 | # -*- coding: utf-8; mode: python -*- | ||
| 2 | |||
| 3 | project = "X86 architecture specific documentation" | ||
| 4 | |||
| 5 | tags.add("subproject") | ||
| 6 | |||
| 7 | latex_documents = [ | ||
| 8 | ('index', 'x86.tex', project, | ||
| 9 | 'The kernel development community', 'manual'), | ||
| 10 | ] | ||
| @@ -899,7 +899,7 @@ L: linux-iio@vger.kernel.org · 898 unmodified lines | |||
| 899 | W: http://ez.analog.com/community/linux-device-drivers | 899 | W: http://ez.analog.com/community/linux-device-drivers |
| 900 | S: Supported | 900 | S: Supported |
| 901 | F: drivers/iio/adc/ad7124.c | 901 | F: drivers/iio/adc/ad7124.c |
| 902 | F: Documentation/devicetree/bindings/iio/adc/adi,ad7124.txt | 902 | F: Documentation/devicetree/bindings/iio/adc/adi,ad7124.yaml |
| 903 | 903 | ||
| 904 | ANALOG DEVICES INC AD7606 DRIVER | 904 | ANALOG DEVICES INC AD7606 DRIVER |
| 905 | M: Stefan Popa <stefan.popa@analog.com> | 905 | M: Stefan Popa <stefan.popa@analog.com> |
| @@ -1194,7 +1194,7 @@ F: include/uapi/linux/if_arcnet.h · 288 unmodified lines | |||
| 1194 | 1194 | ||
| 1195 | ARM ARCHITECTED TIMER DRIVER | 1195 | ARM ARCHITECTED TIMER DRIVER |
| 1196 | M: Mark Rutland <mark.rutland@arm.com> | 1196 | M: Mark Rutland <mark.rutland@arm.com> |
| 1197 | M: Marc Zyngier <marc.zyngier@arm.com> | 1197 | M: Marc Zyngier <maz@kernel.org> |
| 1198 | L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) | 1198 | L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) |
| 1199 | S: Maintained | 1199 | S: Maintained |
| 1200 | F: arch/arm/include/asm/arch_timer.h | 1200 | F: arch/arm/include/asm/arch_timer.h |
| @@ -2155,10 +2155,12 @@ F: Documentation/devicetree/bindings/arm/realtek.txt · 954 unmodified lines | |||
| 2155 | 2155 | ||
| 2156 | ARM/RENESAS ARM64 ARCHITECTURE | 2156 | ARM/RENESAS ARM64 ARCHITECTURE |
| 2157 | M: Simon Horman <horms@verge.net.au> | 2157 | M: Simon Horman <horms@verge.net.au> |
| 2158 | M: Geert Uytterhoeven <geert+renesas@glider.be> | ||
| 2158 | M: Magnus Damm <magnus.damm@gmail.com> | 2159 | M: Magnus Damm <magnus.damm@gmail.com> |
| 2159 | L: linux-renesas-soc@vger.kernel.org | 2160 | L: linux-renesas-soc@vger.kernel.org |
| 2160 | Q: http://patchwork.kernel.org/project/linux-renesas-soc/list/ | 2161 | Q: http://patchwork.kernel.org/project/linux-renesas-soc/list/ |
| 2161 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git next | 2162 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git next |
| 2163 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git next | ||
| 2162 | S: Supported | 2164 | S: Supported |
| 2163 | F: arch/arm64/boot/dts/renesas/ | 2165 | F: arch/arm64/boot/dts/renesas/ |
| 2164 | F: Documentation/devicetree/bindings/arm/renesas.yaml | 2166 | F: Documentation/devicetree/bindings/arm/renesas.yaml |
| @@ -2269,10 +2271,12 @@ F: drivers/media/platform/s5p-mfc/ · 104 unmodified lines | |||
| 2269 | 2271 | ||
| 2270 | ARM/SHMOBILE ARM ARCHITECTURE | 2272 | ARM/SHMOBILE ARM ARCHITECTURE |
| 2271 | M: Simon Horman <horms@verge.net.au> | 2273 | M: Simon Horman <horms@verge.net.au> |
| 2274 | M: Geert Uytterhoeven <geert+renesas@glider.be> | ||
| 2272 | M: Magnus Damm <magnus.damm@gmail.com> | 2275 | M: Magnus Damm <magnus.damm@gmail.com> |
| 2273 | L: linux-renesas-soc@vger.kernel.org | 2276 | L: linux-renesas-soc@vger.kernel.org |
| 2274 | Q: http://patchwork.kernel.org/project/linux-renesas-soc/list/ | 2277 | Q: http://patchwork.kernel.org/project/linux-renesas-soc/list/ |
| 2275 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git next | 2278 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git next |
| 2279 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git next | ||
| 2276 | S: Supported | 2280 | S: Supported |
| 2277 | F: arch/arm/boot/dts/emev2* | 2281 | F: arch/arm/boot/dts/emev2* |
| 2278 | F: arch/arm/boot/dts/gr-peach* | 2282 | F: arch/arm/boot/dts/gr-peach* |
| @@ -4190,7 +4194,7 @@ M: Jens Axboe <axboe@kernel.dk> · 1911 unmodified lines | |||
| 4190 | L: cgroups@vger.kernel.org | 4194 | L: cgroups@vger.kernel.org |
| 4191 | L: linux-block@vger.kernel.org | 4195 | L: linux-block@vger.kernel.org |
| 4192 | T: git git://git.kernel.dk/linux-block | 4196 | T: git git://git.kernel.dk/linux-block |
| 4193 | F: Documentation/cgroup-v1/blkio-controller.rst | 4197 | F: Documentation/admin-guide/cgroup-v1/blkio-controller.rst |
| 4194 | F: block/blk-cgroup.c | 4198 | F: block/blk-cgroup.c |
| 4195 | F: include/linux/blk-cgroup.h | 4199 | F: include/linux/blk-cgroup.h |
| 4196 | F: block/blk-throttle.c | 4200 | F: block/blk-throttle.c |
| @@ -4469,7 +4473,7 @@ F: arch/powerpc/platforms/powernv/pci-cxl.c · 272 unmodified lines | |||
| 4469 | F: drivers/misc/cxl/ | 4473 | F: drivers/misc/cxl/ |
| 4470 | F: include/misc/cxl* | 4474 | F: include/misc/cxl* |
| 4471 | F: include/uapi/misc/cxl.h | 4475 | F: include/uapi/misc/cxl.h |
| 4472 | F: Documentation/powerpc/cxl.txt | 4476 | F: Documentation/powerpc/cxl.rst |
| 4473 | F: Documentation/ABI/testing/sysfs-class-cxl | 4477 | F: Documentation/ABI/testing/sysfs-class-cxl |
| 4474 | 4478 | ||
| 4475 | CXLFLASH (IBM Coherent Accelerator Processor Interface CAPI Flash) SCSI DRIVER | 4479 | CXLFLASH (IBM Coherent Accelerator Processor Interface CAPI Flash) SCSI DRIVER |
| @@ -4480,7 +4484,7 @@ L: linux-scsi@vger.kernel.org · 4 unmodified lines | |||
| 4480 | S: Supported | 4484 | S: Supported |
| 4481 | F: drivers/scsi/cxlflash/ | 4485 | F: drivers/scsi/cxlflash/ |
| 4482 | F: include/uapi/scsi/cxlflash_ioctl.h | 4486 | F: include/uapi/scsi/cxlflash_ioctl.h |
| 4483 | F: Documentation/powerpc/cxlflash.txt | 4487 | F: Documentation/powerpc/cxlflash.rst |
| 4484 | 4488 | ||
| 4485 | CYBERPRO FB DRIVER | 4489 | CYBERPRO FB DRIVER |
| 4486 | M: Russell King <linux@armlinux.org.uk> | 4490 | M: Russell King <linux@armlinux.org.uk> |
| @@ -6322,7 +6326,8 @@ F: Documentation/devicetree/bindings/counter/ftm-quaddec.txt · 1835 unmodified lines | |||
| 6322 | F: drivers/counter/ftm-quaddec.c | 6326 | F: drivers/counter/ftm-quaddec.c |
| 6323 | 6327 | ||
| 6324 | FLOPPY DRIVER | 6328 | FLOPPY DRIVER |
| 6325 | S: Orphan | 6329 | M: Denis Efremov <efremov@linux.com> |
| 6330 | S: Odd Fixes | ||
| 6326 | L: linux-block@vger.kernel.org | 6331 | L: linux-block@vger.kernel.org |
| 6327 | F: drivers/block/floppy.c | 6332 | F: drivers/block/floppy.c |
| 6328 | 6333 | ||
| @@ -6339,7 +6344,7 @@ FPGA MANAGER FRAMEWORK · 10 unmodified lines | |||
| 6339 | M: Moritz Fischer <mdf@kernel.org> | 6344 | M: Moritz Fischer <mdf@kernel.org> |
| 6340 | L: linux-fpga@vger.kernel.org | 6345 | L: linux-fpga@vger.kernel.org |
| 6341 | S: Maintained | 6346 | S: Maintained |
| 6342 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/atull/linux-fpga.git | 6347 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/mdf/linux-fpga.git |
| 6343 | Q: http://patchwork.kernel.org/project/linux-fpga/list/ | 6348 | Q: http://patchwork.kernel.org/project/linux-fpga/list/ |
| 6344 | F: Documentation/fpga/ | 6349 | F: Documentation/fpga/ |
| 6345 | F: Documentation/driver-api/fpga/ | 6350 | F: Documentation/driver-api/fpga/ |
| @@ -6372,7 +6377,7 @@ FRAMEBUFFER LAYER · 26 unmodified lines | |||
| 6372 | M: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> | 6377 | M: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> |
| 6373 | L: dri-devel@lists.freedesktop.org | 6378 | L: dri-devel@lists.freedesktop.org |
| 6374 | L: linux-fbdev@vger.kernel.org | 6379 | L: linux-fbdev@vger.kernel.org |
| 6375 | T: git git://github.com/bzolnier/linux.git | 6380 | T: git git://anongit.freedesktop.org/drm/drm-misc |
| 6376 | Q: http://patchwork.kernel.org/project/linux-fbdev/list/ | 6381 | Q: http://patchwork.kernel.org/project/linux-fbdev/list/ |
| 6377 | S: Maintained | 6382 | S: Maintained |
| 6378 | F: Documentation/fb/ | 6383 | F: Documentation/fb/ |
| @@ -6436,6 +6441,14 @@ S: Maintained · 57 unmodified lines | |||
| 6436 | F: drivers/perf/fsl_imx8_ddr_perf.c | 6441 | F: drivers/perf/fsl_imx8_ddr_perf.c |
| 6437 | F: Documentation/devicetree/bindings/perf/fsl-imx-ddr.txt | 6442 | F: Documentation/devicetree/bindings/perf/fsl-imx-ddr.txt |
| 6438 | 6443 | ||
| 6444 | FREESCALE IMX I2C DRIVER | ||
| 6445 | M: Oleksij Rempel <o.rempel@pengutronix.de> | ||
| 6446 | R: Pengutronix Kernel Team <kernel@pengutronix.de> | ||
| 6447 | L: linux-i2c@vger.kernel.org | ||
| 6448 | S: Maintained | ||
| 6449 | F: drivers/i2c/busses/i2c-imx.c | ||
| 6450 | F: Documentation/devicetree/bindings/i2c/i2c-imx.txt | ||
| 6451 | |||
| 6439 | FREESCALE IMX LPI2C DRIVER | 6452 | FREESCALE IMX LPI2C DRIVER |
| 6440 | M: Dong Aisheng <aisheng.dong@nxp.com> | 6453 | M: Dong Aisheng <aisheng.dong@nxp.com> |
| 6441 | L: linux-i2c@vger.kernel.org | 6454 | L: linux-i2c@vger.kernel.org |
| @@ -6822,13 +6835,6 @@ F: Documentation/filesystems/gfs2*.txt · 380 unmodified lines | |||
| 6822 | F: fs/gfs2/ | 6835 | F: fs/gfs2/ |
| 6823 | F: include/uapi/linux/gfs2_ondisk.h | 6836 | F: include/uapi/linux/gfs2_ondisk.h |
| 6824 | 6837 | ||
| 6825 | GIGASET ISDN DRIVERS | ||
| 6826 | M: Paul Bolle <pebolle@tiscali.nl> | ||
| 6827 | L: gigaset307x-common@lists.sourceforge.net | ||
| 6828 | W: http://gigaset307x.sourceforge.net/ | ||
| 6829 | S: Odd Fixes | ||
| 6830 | F: drivers/staging/isdn/gigaset/ | ||
| 6831 | |||
| 6832 | GNSS SUBSYSTEM | 6838 | GNSS SUBSYSTEM |
| 6833 | M: Johan Hovold <johan@kernel.org> | 6839 | M: Johan Hovold <johan@kernel.org> |
| 6834 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/johan/gnss.git | 6840 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/johan/gnss.git |
| @@ -6856,7 +6862,7 @@ R: Sagi Shahar <sagis@google.com> · 21 unmodified lines | |||
| 6856 | R: Jon Olson <jonolson@google.com> | 6862 | R: Jon Olson <jonolson@google.com> |
| 6857 | L: netdev@vger.kernel.org | 6863 | L: netdev@vger.kernel.org |
| 6858 | S: Supported | 6864 | S: Supported |
| 6859 | F: Documentation/networking/device_drivers/google/gve.txt | 6865 | F: Documentation/networking/device_drivers/google/gve.rst |
| 6860 | F: drivers/net/ethernet/google | 6866 | F: drivers/net/ethernet/google |
| 6861 | 6867 | ||
| 6862 | GPD POCKET FAN DRIVER | 6868 | GPD POCKET FAN DRIVER |
| @@ -7454,7 +7460,7 @@ F: drivers/net/hyperv/ · 591 unmodified lines | |||
| 7454 | F: drivers/scsi/storvsc_drv.c | 7460 | F: drivers/scsi/storvsc_drv.c |
| 7455 | F: drivers/uio/uio_hv_generic.c | 7461 | F: drivers/uio/uio_hv_generic.c |
| 7456 | F: drivers/video/fbdev/hyperv_fb.c | 7462 | F: drivers/video/fbdev/hyperv_fb.c |
| 7457 | F: drivers/iommu/hyperv_iommu.c | 7463 | F: drivers/iommu/hyperv-iommu.c |
| 7458 | F: net/vmw_vsock/hyperv_transport.c | 7464 | F: net/vmw_vsock/hyperv_transport.c |
| 7459 | F: include/clocksource/hyperv_timer.h | 7465 | F: include/clocksource/hyperv_timer.h |
| 7460 | F: include/linux/hyperv.h | 7466 | F: include/linux/hyperv.h |
| @@ -8044,6 +8050,7 @@ S: Maintained · 583 unmodified lines | |||
| 8044 | F: drivers/video/fbdev/i810/ | 8050 | F: drivers/video/fbdev/i810/ |
| 8045 | 8051 | ||
| 8046 | INTEL ASoC DRIVERS | 8052 | INTEL ASoC DRIVERS |
| 8053 | M: Cezary Rojewski <cezary.rojewski@intel.com> | ||
| 8047 | M: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> | 8054 | M: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> |
| 8048 | M: Liam Girdwood <liam.r.girdwood@linux.intel.com> | 8055 | M: Liam Girdwood <liam.r.girdwood@linux.intel.com> |
| 8049 | M: Jie Yang <yang.jie@linux.intel.com> | 8056 | M: Jie Yang <yang.jie@linux.intel.com> |
| @@ -8065,6 +8072,13 @@ T: git git://git.code.sf.net/p/intel-sas/isci · 15 unmodified lines | |||
| 8065 | S: Supported | 8072 | S: Supported |
| 8066 | F: drivers/scsi/isci/ | 8073 | F: drivers/scsi/isci/ |
| 8067 | 8074 | ||
| 8075 | INTEL CPU family model numbers | ||
| 8076 | M: Tony Luck <tony.luck@intel.com> | ||
| 8077 | M: x86@kernel.org | ||
| 8078 | L: linux-kernel@vger.kernel.org | ||
| 8079 | S: Supported | ||
| 8080 | F: arch/x86/include/asm/intel-family.h | ||
| 8081 | |||
| 8068 | INTEL DRM DRIVERS (excluding Poulsbo, Moorestown and derivative chipsets) | 8082 | INTEL DRM DRIVERS (excluding Poulsbo, Moorestown and derivative chipsets) |
| 8069 | M: Jani Nikula <jani.nikula@linux.intel.com> | 8083 | M: Jani Nikula <jani.nikula@linux.intel.com> |
| 8070 | M: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> | 8084 | M: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> |
| @@ -8416,7 +8430,6 @@ L: linux-xfs@vger.kernel.org · 345 unmodified lines | |||
| 8416 | L: linux-fsdevel@vger.kernel.org | 8430 | L: linux-fsdevel@vger.kernel.org |
| 8417 | T: git git://git.kernel.org/pub/scm/fs/xfs/xfs-linux.git | 8431 | T: git git://git.kernel.org/pub/scm/fs/xfs/xfs-linux.git |
| 8418 | S: Supported | 8432 | S: Supported |
| 8419 | F: fs/iomap.c | ||
| 8420 | F: fs/iomap/ | 8433 | F: fs/iomap/ |
| 8421 | F: include/linux/iomap.h | 8434 | F: include/linux/iomap.h |
| 8422 | 8435 | ||
| @@ -8490,7 +8503,7 @@ S: Obsolete · 67 unmodified lines | |||
| 8490 | F: include/uapi/linux/ipx.h | 8503 | F: include/uapi/linux/ipx.h |
| 8491 | 8504 | ||
| 8492 | IRQ DOMAINS (IRQ NUMBER MAPPING LIBRARY) | 8505 | IRQ DOMAINS (IRQ NUMBER MAPPING LIBRARY) |
| 8493 | M: Marc Zyngier <marc.zyngier@arm.com> | 8506 | M: Marc Zyngier <maz@kernel.org> |
| 8494 | S: Maintained | 8507 | S: Maintained |
| 8495 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq/core | 8508 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq/core |
| 8496 | F: Documentation/IRQ-domain.txt | 8509 | F: Documentation/IRQ-domain.txt |
| @@ -8508,7 +8521,7 @@ F: kernel/irq/ · 11 unmodified lines | |||
| 8508 | IRQCHIP DRIVERS | 8521 | IRQCHIP DRIVERS |
| 8509 | M: Thomas Gleixner <tglx@linutronix.de> | 8522 | M: Thomas Gleixner <tglx@linutronix.de> |
| 8510 | M: Jason Cooper <jason@lakedaemon.net> | 8523 | M: Jason Cooper <jason@lakedaemon.net> |
| 8511 | M: Marc Zyngier <marc.zyngier@arm.com> | 8524 | M: Marc Zyngier <maz@kernel.org> |
| 8512 | L: linux-kernel@vger.kernel.org | 8525 | L: linux-kernel@vger.kernel.org |
| 8513 | S: Maintained | 8526 | S: Maintained |
| 8514 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq/core | 8527 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq/core |
| @@ -8808,7 +8821,7 @@ L: kvm@vger.kernel.org · 293 unmodified lines | |||
| 8808 | W: http://www.linux-kvm.org | 8821 | W: http://www.linux-kvm.org |
| 8809 | T: git git://git.kernel.org/pub/scm/virt/kvm/kvm.git | 8822 | T: git git://git.kernel.org/pub/scm/virt/kvm/kvm.git |
| 8810 | S: Supported | 8823 | S: Supported |
| 8811 | F: Documentation/virtual/kvm/ | 8824 | F: Documentation/virt/kvm/ |
| 8812 | F: include/trace/events/kvm.h | 8825 | F: include/trace/events/kvm.h |
| 8813 | F: include/uapi/asm-generic/kvm* | 8826 | F: include/uapi/asm-generic/kvm* |
| 8814 | F: include/uapi/linux/kvm* | 8827 | F: include/uapi/linux/kvm* |
| @@ -8828,10 +8841,10 @@ F: arch/x86/include/asm/svm.h · 13 unmodified lines | |||
| 8828 | F: arch/x86/kvm/svm.c | 8841 | F: arch/x86/kvm/svm.c |
| 8829 | 8842 | ||
| 8830 | KERNEL VIRTUAL MACHINE FOR ARM/ARM64 (KVM/arm, KVM/arm64) | 8843 | KERNEL VIRTUAL MACHINE FOR ARM/ARM64 (KVM/arm, KVM/arm64) |
| 8831 | M: Marc Zyngier <marc.zyngier@arm.com> | 8844 | M: Marc Zyngier <maz@kernel.org> |
| 8832 | R: James Morse <james.morse@arm.com> | 8845 | R: James Morse <james.morse@arm.com> |
| 8833 | R: Julien Thierry <julien.thierry@arm.com> | 8846 | R: Julien Thierry <julien.thierry.kdev@gmail.com> |
| 8834 | R: Suzuki K Pouloze <suzuki.poulose@arm.com> | 8847 | R: Suzuki K Poulose <suzuki.poulose@arm.com> |
| 8835 | L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) | 8848 | L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) |
| 8836 | L: kvmarm@lists.cs.columbia.edu | 8849 | L: kvmarm@lists.cs.columbia.edu |
| 8837 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm.git | 8850 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm.git |
| @@ -11144,6 +11157,7 @@ L: netdev@vger.kernel.org · 2306 unmodified lines | |||
| 11144 | S: Maintained | 11157 | S: Maintained |
| 11145 | W: https://fedorahosted.org/dropwatch/ | 11158 | W: https://fedorahosted.org/dropwatch/ |
| 11146 | F: net/core/drop_monitor.c | 11159 | F: net/core/drop_monitor.c |
| 11160 | F: include/uapi/linux/net_dropmon.h | ||
| 11147 | 11161 | ||
| 11148 | NETWORKING DRIVERS | 11162 | NETWORKING DRIVERS |
| 11149 | M: "David S. Miller" <davem@davemloft.net> | 11163 | M: "David S. Miller" <davem@davemloft.net> |
| @@ -11282,6 +11296,7 @@ M: Aviad Yehezkel <aviadye@mellanox.com> · 132 unmodified lines | |||
| 11282 | M: Dave Watson <davejwatson@fb.com> | 11296 | M: Dave Watson <davejwatson@fb.com> |
| 11283 | M: John Fastabend <john.fastabend@gmail.com> | 11297 | M: John Fastabend <john.fastabend@gmail.com> |
| 11284 | M: Daniel Borkmann <daniel@iogearbox.net> | 11298 | M: Daniel Borkmann <daniel@iogearbox.net> |
| 11299 | M: Jakub Kicinski <jakub.kicinski@netronome.com> | ||
| 11285 | L: netdev@vger.kernel.org | 11300 | L: netdev@vger.kernel.org |
| 11286 | S: Maintained | 11301 | S: Maintained |
| 11287 | F: net/tls/* | 11302 | F: net/tls/* |
| @@ -12137,7 +12152,7 @@ M: Thomas Hellstrom <thellstrom@vmware.com> · 849 unmodified lines | |||
| 12137 | M: "VMware, Inc." <pv-drivers@vmware.com> | 12152 | M: "VMware, Inc." <pv-drivers@vmware.com> |
| 12138 | L: virtualization@lists.linux-foundation.org | 12153 | L: virtualization@lists.linux-foundation.org |
| 12139 | S: Supported | 12154 | S: Supported |
| 12140 | F: Documentation/virtual/paravirt_ops.txt | 12155 | F: Documentation/virt/paravirt_ops.rst |
| 12141 | F: arch/*/kernel/paravirt* | 12156 | F: arch/*/kernel/paravirt* |
| 12142 | F: arch/*/include/asm/paravirt*.h | 12157 | F: arch/*/include/asm/paravirt*.h |
| 12143 | F: include/linux/hypervisor.h | 12158 | F: include/linux/hypervisor.h |
| @@ -12394,7 +12409,7 @@ F: Documentation/PCI/pci-error-recovery.rst · 250 unmodified lines | |||
| 12394 | F: drivers/pci/pcie/aer.c | 12409 | F: drivers/pci/pcie/aer.c |
| 12395 | F: drivers/pci/pcie/dpc.c | 12410 | F: drivers/pci/pcie/dpc.c |
| 12396 | F: drivers/pci/pcie/err.c | 12411 | F: drivers/pci/pcie/err.c |
| 12397 | F: Documentation/powerpc/eeh-pci-error-recovery.txt | 12412 | F: Documentation/powerpc/eeh-pci-error-recovery.rst |
| 12398 | F: arch/powerpc/kernel/eeh*.c | 12413 | F: arch/powerpc/kernel/eeh*.c |
| 12399 | F: arch/powerpc/platforms/*/eeh*.c | 12414 | F: arch/powerpc/platforms/*/eeh*.c |
| 12400 | F: arch/powerpc/include/*/eeh*.h | 12415 | F: arch/powerpc/include/*/eeh*.h |
| @@ -13725,6 +13740,7 @@ F: drivers/mtd/nand/raw/r852.c · 1324 unmodified lines | |||
| 13725 | F: drivers/mtd/nand/raw/r852.h | 13740 | F: drivers/mtd/nand/raw/r852.h |
| 13726 | 13741 | ||
| 13727 | RISC-V ARCHITECTURE | 13742 | RISC-V ARCHITECTURE |
| 13743 | M: Paul Walmsley <paul.walmsley@sifive.com> | ||
| 13728 | M: Palmer Dabbelt <palmer@sifive.com> | 13744 | M: Palmer Dabbelt <palmer@sifive.com> |
| 13729 | M: Albert Ou <aou@eecs.berkeley.edu> | 13745 | M: Albert Ou <aou@eecs.berkeley.edu> |
| 13730 | L: linux-riscv@lists.infradead.org | 13746 | L: linux-riscv@lists.infradead.org |
| @@ -13947,7 +13963,6 @@ F: drivers/pci/hotplug/s390_pci_hpc.c · 216 unmodified lines | |||
| 13947 | 13963 | ||
| 13948 | S390 VFIO-CCW DRIVER | 13964 | S390 VFIO-CCW DRIVER |
| 13949 | M: Cornelia Huck <cohuck@redhat.com> | 13965 | M: Cornelia Huck <cohuck@redhat.com> |
| 13950 | M: Farhan Ali <alifm@linux.ibm.com> | ||
| 13951 | M: Eric Farman <farman@linux.ibm.com> | 13966 | M: Eric Farman <farman@linux.ibm.com> |
| 13952 | R: Halil Pasic <pasic@linux.ibm.com> | 13967 | R: Halil Pasic <pasic@linux.ibm.com> |
| 13953 | L: linux-s390@vger.kernel.org | 13968 | L: linux-s390@vger.kernel.org |
| @@ -14016,6 +14031,12 @@ F: drivers/media/common/saa7146/ · 62 unmodified lines | |||
| 14016 | F: drivers/media/pci/saa7146/ | 14031 | F: drivers/media/pci/saa7146/ |
| 14017 | F: include/media/drv-intf/saa7146* | 14032 | F: include/media/drv-intf/saa7146* |
| 14018 | 14033 | ||
| 14034 | SAFESETID SECURITY MODULE | ||
| 14035 | M: Micah Morton <mortonm@chromium.org> | ||
| 14036 | S: Supported | ||
| 14037 | F: security/safesetid/ | ||
| 14038 | F: Documentation/admin-guide/LSM/SafeSetID.rst | ||
| 14039 | |||
| 14019 | SAMSUNG AUDIO (ASoC) DRIVERS | 14040 | SAMSUNG AUDIO (ASoC) DRIVERS |
| 14020 | M: Krzysztof Kozlowski <krzk@kernel.org> | 14041 | M: Krzysztof Kozlowski <krzk@kernel.org> |
| 14021 | M: Sangbeom Kim <sbkim73@samsung.com> | 14042 | M: Sangbeom Kim <sbkim73@samsung.com> |
| @@ -16078,7 +16099,7 @@ S: Maintained · 2056 unmodified lines | |||
| 16078 | F: drivers/net/ethernet/ti/netcp* | 16099 | F: drivers/net/ethernet/ti/netcp* |
| 16079 | 16100 | ||
| 16080 | TI PCM3060 ASoC CODEC DRIVER | 16101 | TI PCM3060 ASoC CODEC DRIVER |
| 16081 | M: Kirill Marinushkin <kmarinushkin@birdec.tech> | 16102 | M: Kirill Marinushkin <kmarinushkin@birdec.com> |
| 16082 | L: alsa-devel@alsa-project.org (moderated for non-subscribers) | 16103 | L: alsa-devel@alsa-project.org (moderated for non-subscribers) |
| 16083 | S: Maintained | 16104 | S: Maintained |
| 16084 | F: Documentation/devicetree/bindings/sound/pcm3060.txt | 16105 | F: Documentation/devicetree/bindings/sound/pcm3060.txt |
| @@ -16854,7 +16875,7 @@ W: http://user-mode-linux.sourceforge.net · 769 unmodified lines | |||
| 16854 | Q: https://patchwork.ozlabs.org/project/linux-um/list/ | 16875 | Q: https://patchwork.ozlabs.org/project/linux-um/list/ |
| 16855 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/rw/uml.git | 16876 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/rw/uml.git |
| 16856 | S: Maintained | 16877 | S: Maintained |
| 16857 | F: Documentation/virtual/uml/ | 16878 | F: Documentation/virt/uml/ |
| 16858 | F: arch/um/ | 16879 | F: arch/um/ |
| 16859 | F: arch/x86/um/ | 16880 | F: arch/x86/um/ |
| 16860 | F: fs/hostfs/ | 16881 | F: fs/hostfs/ |
| @@ -17123,7 +17144,7 @@ F: drivers/virtio/virtio_input.c · 262 unmodified lines | |||
| 17123 | F: include/uapi/linux/virtio_input.h | 17144 | F: include/uapi/linux/virtio_input.h |
| 17124 | 17145 | ||
| 17125 | VIRTIO IOMMU DRIVER | 17146 | VIRTIO IOMMU DRIVER |
| 17126 | M: Jean-Philippe Brucker <jean-philippe.brucker@arm.com> | 17147 | M: Jean-Philippe Brucker <jean-philippe@linaro.org> |
| 17127 | L: virtualization@lists.linux-foundation.org | 17148 | L: virtualization@lists.linux-foundation.org |
| 17128 | S: Maintained | 17149 | S: Maintained |
| 17129 | F: drivers/iommu/virtio-iommu.c | 17150 | F: drivers/iommu/virtio-iommu.c |
| @@ -17172,7 +17193,6 @@ F: drivers/vme/ · 42 unmodified lines | |||
| 17172 | F: include/linux/vme* | 17193 | F: include/linux/vme* |
| 17173 | 17194 | ||
| 17174 | VMWARE BALLOON DRIVER | 17195 | VMWARE BALLOON DRIVER |
| 17175 | M: Julien Freche <jfreche@vmware.com> | ||
| 17176 | M: Nadav Amit <namit@vmware.com> | 17196 | M: Nadav Amit <namit@vmware.com> |
| 17177 | M: "VMware, Inc." <pv-drivers@vmware.com> | 17197 | M: "VMware, Inc." <pv-drivers@vmware.com> |
| 17178 | L: linux-kernel@vger.kernel.org | 17198 | L: linux-kernel@vger.kernel.org |
| @@ -17555,7 +17575,6 @@ M: Jakub Kicinski <jakub.kicinski@netronome.com> · 376 unmodified lines | |||
| 17555 | M: Jesper Dangaard Brouer <hawk@kernel.org> | 17575 | M: Jesper Dangaard Brouer <hawk@kernel.org> |
| 17556 | M: John Fastabend <john.fastabend@gmail.com> | 17576 | M: John Fastabend <john.fastabend@gmail.com> |
| 17557 | L: netdev@vger.kernel.org | 17577 | L: netdev@vger.kernel.org |
| 17558 | L: xdp-newbies@vger.kernel.org | ||
| 17559 | L: bpf@vger.kernel.org | 17578 | L: bpf@vger.kernel.org |
| 17560 | S: Supported | 17579 | S: Supported |
| 17561 | F: net/core/xdp.c | 17580 | F: net/core/xdp.c |
| @@ -2,7 +2,7 @@ · 1 unmodified line | |||
| 2 | VERSION = 5 | 2 | VERSION = 5 |
| 3 | PATCHLEVEL = 3 | 3 | PATCHLEVEL = 3 |
| 4 | SUBLEVEL = 0 | 4 | SUBLEVEL = 0 |
| 5 | EXTRAVERSION = -rc1 | 5 | EXTRAVERSION = -rc5 |
| 6 | NAME = Bobtail Squid | 6 | NAME = Bobtail Squid |
| 7 | 7 | ||
| 8 | # *DOCUMENTATION* | 8 | # *DOCUMENTATION* |
| @@ -419,6 +419,7 @@ NM = $(CROSS_COMPILE)nm · 410 unmodified lines | |||
| 419 | STRIP = $(CROSS_COMPILE)strip | 419 | STRIP = $(CROSS_COMPILE)strip |
| 420 | OBJCOPY = $(CROSS_COMPILE)objcopy | 420 | OBJCOPY = $(CROSS_COMPILE)objcopy |
| 421 | OBJDUMP = $(CROSS_COMPILE)objdump | 421 | OBJDUMP = $(CROSS_COMPILE)objdump |
| 422 | OBJSIZE = $(CROSS_COMPILE)size | ||
| 422 | PAHOLE = pahole | 423 | PAHOLE = pahole |
| 423 | LEX = flex | 424 | LEX = flex |
| 424 | YACC = bison | 425 | YACC = bison |
| @@ -472,11 +473,12 @@ KBUILD_CFLAGS_MODULE := -DMODULE · 47 unmodified lines | |||
| 472 | KBUILD_LDFLAGS_MODULE := -T $(srctree)/scripts/module-common.lds | 473 | KBUILD_LDFLAGS_MODULE := -T $(srctree)/scripts/module-common.lds |
| 473 | KBUILD_LDFLAGS := | 474 | KBUILD_LDFLAGS := |
| 474 | GCC_PLUGINS_CFLAGS := | 475 | GCC_PLUGINS_CFLAGS := |
| 476 | CLANG_FLAGS := | ||
| 475 | 477 | ||
| 476 | export ARCH SRCARCH CONFIG_SHELL HOSTCC KBUILD_HOSTCFLAGS CROSS_COMPILE AS LD CC | 478 | export ARCH SRCARCH CONFIG_SHELL HOSTCC KBUILD_HOSTCFLAGS CROSS_COMPILE AS LD CC |
| 477 | export CPP AR NM STRIP OBJCOPY OBJDUMP PAHOLE KBUILD_HOSTLDFLAGS KBUILD_HOSTLDLIBS | 479 | export CPP AR NM STRIP OBJCOPY OBJDUMP OBJSIZE PAHOLE LEX YACC AWK INSTALLKERNEL |
| 478 | export MAKE LEX YACC AWK INSTALLKERNEL PERL PYTHON PYTHON2 PYTHON3 UTS_MACHINE | 480 | export PERL PYTHON PYTHON2 PYTHON3 CHECK CHECKFLAGS MAKE UTS_MACHINE HOSTCXX |
| 479 | export HOSTCXX KBUILD_HOSTCXXFLAGS LDFLAGS_MODULE CHECK CHECKFLAGS | 481 | export KBUILD_HOSTCXXFLAGS KBUILD_HOSTLDFLAGS KBUILD_HOSTLDLIBS LDFLAGS_MODULE |
| 480 | 482 | ||
| 481 | export KBUILD_CPPFLAGS NOSTDINC_FLAGS LINUXINCLUDE OBJCOPYFLAGS KBUILD_LDFLAGS | 483 | export KBUILD_CPPFLAGS NOSTDINC_FLAGS LINUXINCLUDE OBJCOPYFLAGS KBUILD_LDFLAGS |
| 482 | export KBUILD_CFLAGS CFLAGS_KERNEL CFLAGS_MODULE | 484 | export KBUILD_CFLAGS CFLAGS_KERNEL CFLAGS_MODULE |
| @@ -519,7 +521,7 @@ endif · 36 unmodified lines | |||
| 519 | 521 | ||
| 520 | ifneq ($(shell $(CC) --version 2>&1 | head -n 1 | grep clang),) | 522 | ifneq ($(shell $(CC) --version 2>&1 | head -n 1 | grep clang),) |
| 521 | ifneq ($(CROSS_COMPILE),) | 523 | ifneq ($(CROSS_COMPILE),) |
| 522 | CLANG_FLAGS := --target=$(notdir $(CROSS_COMPILE:%-=%)) | 524 | CLANG_FLAGS += --target=$(notdir $(CROSS_COMPILE:%-=%)) |
| 523 | GCC_TOOLCHAIN_DIR := $(dir $(shell which $(CROSS_COMPILE)elfedit)) | 525 | GCC_TOOLCHAIN_DIR := $(dir $(shell which $(CROSS_COMPILE)elfedit)) |
| 524 | CLANG_FLAGS += --prefix=$(GCC_TOOLCHAIN_DIR) | 526 | CLANG_FLAGS += --prefix=$(GCC_TOOLCHAIN_DIR) |
| 525 | GCC_TOOLCHAIN := $(realpath $(GCC_TOOLCHAIN_DIR)/..) | 527 | GCC_TOOLCHAIN := $(realpath $(GCC_TOOLCHAIN_DIR)/..) |
| @@ -843,6 +845,9 @@ NOSTDINC_FLAGS += -nostdinc -isystem $(shell $(CC) -print-file-name=include) · 317 unmodified lines | |||
| 843 | # warn about C99 declaration after statement | 845 | # warn about C99 declaration after statement |
| 844 | KBUILD_CFLAGS += -Wdeclaration-after-statement | 846 | KBUILD_CFLAGS += -Wdeclaration-after-statement |
| 845 | 847 | ||
| 848 | # Warn about unmarked fall-throughs in switch statement. | ||
| 849 | KBUILD_CFLAGS += $(call cc-option,-Wimplicit-fallthrough,) | ||
| 850 | |||
| 846 | # Variable Length Arrays (VLAs) should not be used anywhere in the kernel | 851 | # Variable Length Arrays (VLAs) should not be used anywhere in the kernel |
| 847 | KBUILD_CFLAGS += -Wvla | 852 | KBUILD_CFLAGS += -Wvla |
| 848 | 853 | ||
| @@ -998,6 +1003,8 @@ endif · 149 unmodified lines | |||
| 998 | 1003 | ||
| 999 | PHONY += prepare0 | 1004 | PHONY += prepare0 |
| 1000 | 1005 | ||
| 1006 | export MODORDER := $(if $(KBUILD_EXTMOD),$(KBUILD_EXTMOD)/)modules.order | ||
| 1007 | |||
| 1001 | ifeq ($(KBUILD_EXTMOD),) | 1008 | ifeq ($(KBUILD_EXTMOD),) |
| 1002 | core-y += kernel/ certs/ mm/ fs/ ipc/ security/ crypto/ block/ | 1009 | core-y += kernel/ certs/ mm/ fs/ ipc/ security/ crypto/ block/ |
| 1003 | 1010 | ||
| @@ -1767,13 +1774,22 @@ build-dir = $(patsubst %/,%,$(dir $(build-target))) · 763 unmodified lines | |||
| 1767 | $(Q)$(MAKE) $(build)=$(build-dir) $(build-target) | 1774 | $(Q)$(MAKE) $(build)=$(build-dir) $(build-target) |
| 1768 | %.symtypes: prepare FORCE | 1775 | %.symtypes: prepare FORCE |
| 1769 | $(Q)$(MAKE) $(build)=$(build-dir) $(build-target) | 1776 | $(Q)$(MAKE) $(build)=$(build-dir) $(build-target) |
| 1777 | ifeq ($(KBUILD_EXTMOD),) | ||
| 1778 | # For the single build of an in-tree module, use a temporary file to avoid | ||
| 1779 | # the situation of modules_install installing an invalid modules.order. | ||
| 1780 | %.ko: MODORDER := .modules.tmp | ||
| 1781 | endif | ||
| 1782 | %.ko: prepare FORCE | ||
| 1783 | $(Q)$(MAKE) $(build)=$(build-dir) $(build-target:.ko=.mod) | ||
| 1784 | $(Q)echo $(build-target) > $(MODORDER) | ||
| 1785 | $(Q)$(MAKE) -f $(srctree)/scripts/Makefile.modpost | ||
| 1770 | 1786 | ||
| 1771 | # Modules | 1787 | # Modules |
| 1772 | PHONY += / | 1788 | PHONY += / |
| 1773 | /: ./ | 1789 | /: ./ |
| 1774 | 1790 | ||
| 1775 | %/: prepare FORCE | 1791 | %/: prepare FORCE |
| 1776 | $(Q)$(MAKE) KBUILD_MODULES=1 $(build)=$(build-dir) | 1792 | $(Q)$(MAKE) KBUILD_MODULES=1 $(build)=$(build-dir) need-modorder=1 |
| 1777 | 1793 | ||
| 1778 | # FIXME Should go into a make.lib or something | 1794 | # FIXME Should go into a make.lib or something |
| 1779 | # =========================================================================== | 1795 | # =========================================================================== |
| @@ -1535,7 +1535,6 @@ config DEBUG_LL_INCLUDE · 1534 unmodified lines | |||
| 1535 | DEBUG_IMX7D_UART | 1535 | DEBUG_IMX7D_UART |
| 1536 | default "debug/ks8695.S" if DEBUG_KS8695_UART | 1536 | default "debug/ks8695.S" if DEBUG_KS8695_UART |
| 1537 | default "debug/msm.S" if DEBUG_QCOM_UARTDM | 1537 | default "debug/msm.S" if DEBUG_QCOM_UARTDM |
| 1538 | default "debug/netx.S" if DEBUG_NETX_UART | ||
| 1539 | default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART | 1538 | default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART |
| 1540 | default "debug/renesas-scif.S" if DEBUG_R7S72100_SCIF2 | 1539 | default "debug/renesas-scif.S" if DEBUG_R7S72100_SCIF2 |
| 1541 | default "debug/renesas-scif.S" if DEBUG_RCAR_GEN1_SCIF0 | 1540 | default "debug/renesas-scif.S" if DEBUG_RCAR_GEN1_SCIF0 |
| @@ -1575,7 +1574,6 @@ config DEBUG_UART_8250 · 33 unmodified lines | |||
| 1575 | 1574 | ||
| 1576 | config DEBUG_UART_PHYS | 1575 | config DEBUG_UART_PHYS |
| 1577 | hex "Physical base address of debug UART" | 1576 | hex "Physical base address of debug UART" |
| 1578 | default 0x00100a00 if DEBUG_NETX_UART | ||
| 1579 | default 0x01c20000 if DEBUG_DAVINCI_DMx_UART0 | 1577 | default 0x01c20000 if DEBUG_DAVINCI_DMx_UART0 |
| 1580 | default 0x01c28000 if DEBUG_SUNXI_UART0 | 1578 | default 0x01c28000 if DEBUG_SUNXI_UART0 |
| 1581 | default 0x01c28400 if DEBUG_SUNXI_UART1 | 1579 | default 0x01c28400 if DEBUG_SUNXI_UART1 |
| @@ -1700,7 +1698,6 @@ config DEBUG_UART_PHYS · 118 unmodified lines | |||
| 1700 | DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \ | 1698 | DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \ |
| 1701 | DEBUG_LL_UART_EFM32 || \ | 1699 | DEBUG_LL_UART_EFM32 || \ |
| 1702 | DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \ | 1700 | DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \ |
| 1703 | DEBUG_NETX_UART || \ | ||
| 1704 | DEBUG_QCOM_UARTDM || DEBUG_R7S72100_SCIF2 || \ | 1701 | DEBUG_QCOM_UARTDM || DEBUG_R7S72100_SCIF2 || \ |
| 1705 | DEBUG_RCAR_GEN1_SCIF0 || DEBUG_RCAR_GEN1_SCIF2 || \ | 1702 | DEBUG_RCAR_GEN1_SCIF0 || DEBUG_RCAR_GEN1_SCIF2 || \ |
| 1706 | DEBUG_RCAR_GEN2_SCIF0 || DEBUG_RCAR_GEN2_SCIF1 || \ | 1703 | DEBUG_RCAR_GEN2_SCIF0 || DEBUG_RCAR_GEN2_SCIF1 || \ |
| @@ -1717,7 +1714,6 @@ config DEBUG_UART_VIRT · 10 unmodified lines | |||
| 1717 | default 0xc881f000 if DEBUG_RV1108_UART2 | 1714 | default 0xc881f000 if DEBUG_RV1108_UART2 |
| 1718 | default 0xc8821000 if DEBUG_RV1108_UART1 | 1715 | default 0xc8821000 if DEBUG_RV1108_UART1 |
| 1719 | default 0xc8912000 if DEBUG_RV1108_UART0 | 1716 | default 0xc8912000 if DEBUG_RV1108_UART0 |
| 1720 | default 0xe0000a00 if DEBUG_NETX_UART | ||
| 1721 | default 0xe0010fe0 if ARCH_RPC | 1717 | default 0xe0010fe0 if ARCH_RPC |
| 1722 | default 0xf0000be0 if ARCH_EBSA110 | 1718 | default 0xf0000be0 if ARCH_EBSA110 |
| 1723 | default 0xf0010000 if DEBUG_ASM9260_UART | 1719 | default 0xf0010000 if DEBUG_ASM9260_UART |
| @@ -1822,7 +1818,6 @@ config DEBUG_UART_VIRT · 98 unmodified lines | |||
| 1822 | default DEBUG_UART_PHYS if !MMU | 1818 | default DEBUG_UART_PHYS if !MMU |
| 1823 | depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \ | 1819 | depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \ |
| 1824 | DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \ | 1820 | DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \ |
| 1825 | DEBUG_NETX_UART || \ | ||
| 1826 | DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART || \ | 1821 | DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART || \ |
| 1827 | DEBUG_S3C64XX_UART || \ | 1822 | DEBUG_S3C64XX_UART || \ |
| 1828 | DEBUG_BCM63XX_UART || DEBUG_ASM9260_UART || \ | 1823 | DEBUG_BCM63XX_UART || DEBUG_ASM9260_UART || \ |
| @@ -124,6 +124,9 @@ · 123 unmodified lines | |||
| 124 | }; | 124 | }; |
| 125 | 125 | ||
| 126 | mdio-bus-mux { | 126 | mdio-bus-mux { |
| 127 | #address-cells = <1>; | ||
| 128 | #size-cells = <0>; | ||
| 129 | |||
| 127 | /* BIT(9) = 1 => external mdio */ | 130 | /* BIT(9) = 1 => external mdio */ |
| 128 | mdio_ext: mdio@200 { | 131 | mdio_ext: mdio@200 { |
| 129 | reg = <0x200>; | 132 | reg = <0x200>; |
| @@ -112,7 +112,7 @@ · 111 unmodified lines | |||
| 112 | }; | 112 | }; |
| 113 | 113 | ||
| 114 | &i2c2 { | 114 | &i2c2 { |
| 115 | clock_frequency = <100000>; | 115 | clock-frequency = <100000>; |
| 116 | pinctrl-names = "default"; | 116 | pinctrl-names = "default"; |
| 117 | pinctrl-0 = <&pinctrl_i2c2>; | 117 | pinctrl-0 = <&pinctrl_i2c2>; |
| 118 | status = "okay"; | 118 | status = "okay"; |
| @@ -156,7 +156,7 @@ · 155 unmodified lines | |||
| 156 | }; | 156 | }; |
| 157 | 157 | ||
| 158 | &i2c2 { | 158 | &i2c2 { |
| 159 | clock_frequency = <100000>; | 159 | clock-frequency = <100000>; |
| 160 | pinctrl-names = "default"; | 160 | pinctrl-names = "default"; |
| 161 | pinctrl-0 = <&pinctrl_i2c2>; | 161 | pinctrl-0 = <&pinctrl_i2c2>; |
| 162 | status = "okay"; | 162 | status = "okay"; |
| @@ -148,7 +148,7 @@ · 147 unmodified lines | |||
| 148 | }; | 148 | }; |
| 149 | 149 | ||
| 150 | &i2c2 { | 150 | &i2c2 { |
| 151 | clock_frequency = <100000>; | 151 | clock-frequency = <100000>; |
| 152 | pinctrl-names = "default"; | 152 | pinctrl-names = "default"; |
| 153 | pinctrl-0 = <&pinctrl_i2c2>; | 153 | pinctrl-0 = <&pinctrl_i2c2>; |
| 154 | status = "okay"; | 154 | status = "okay"; |
| @@ -43,7 +43,7 @@ · 42 unmodified lines | |||
| 43 | }; | 43 | }; |
| 44 | 44 | ||
| 45 | &i2c2 { | 45 | &i2c2 { |
| 46 | clock_frequency = <100000>; | 46 | clock-frequency = <100000>; |
| 47 | pinctrl-names = "default"; | 47 | pinctrl-names = "default"; |
| 48 | pinctrl-0 = <&pinctrl_i2c2>; | 48 | pinctrl-0 = <&pinctrl_i2c2>; |
| 49 | status = "okay"; | 49 | status = "okay"; |
| @@ -43,7 +43,7 @@ · 42 unmodified lines | |||
| 43 | }; | 43 | }; |
| 44 | 44 | ||
| 45 | &i2c2 { | 45 | &i2c2 { |
| 46 | clock_frequency = <100000>; | 46 | clock-frequency = <100000>; |
| 47 | pinctrl-names = "default"; | 47 | pinctrl-names = "default"; |
| 48 | pinctrl-0 = <&pinctrl_i2c2>; | 48 | pinctrl-0 = <&pinctrl_i2c2>; |
| 49 | status = "okay"; | 49 | status = "okay"; |
| @@ -58,7 +58,7 @@ · 8 unmodified lines | |||
| 58 | }; | 58 | }; |
| 59 | 59 | ||
| 60 | &i2c3 { | 60 | &i2c3 { |
| 61 | clock_frequency = <100000>; | 61 | clock-frequency = <100000>; |
| 62 | pinctrl-names = "default"; | 62 | pinctrl-names = "default"; |
| 63 | pinctrl-0 = <&pinctrl_i2c3>; | 63 | pinctrl-0 = <&pinctrl_i2c3>; |
| 64 | status = "okay"; | 64 | status = "okay"; |
| @@ -186,7 +186,7 @@ · 185 unmodified lines | |||
| 186 | reg = <0x40330200 0x200>; | 186 | reg = <0x40330200 0x200>; |
| 187 | }; | 187 | }; |
| 188 | 188 | ||
| 189 | usbphy1: usb-phy@0x40350000 { | 189 | usbphy1: usb-phy@40350000 { |
| 190 | compatible = "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy"; | 190 | compatible = "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy"; |
| 191 | reg = <0x40350000 0x1000>; | 191 | reg = <0x40350000 0x1000>; |
| 192 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; | 192 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
| @@ -4,17 +4,9 @@ CONFIG_NO_HZ_IDLE=y · 3 unmodified lines | |||
| 4 | CONFIG_HIGH_RES_TIMERS=y | 4 | CONFIG_HIGH_RES_TIMERS=y |
| 5 | CONFIG_BLK_DEV_INITRD=y | 5 | CONFIG_BLK_DEV_INITRD=y |
| 6 | CONFIG_KALLSYMS_ALL=y | 6 | CONFIG_KALLSYMS_ALL=y |
| 7 | CONFIG_MODULES=y | ||
| 8 | CONFIG_MODULE_UNLOAD=y | ||
| 9 | # CONFIG_BLK_DEV_BSG is not set | ||
| 10 | CONFIG_PARTITION_ADVANCED=y | ||
| 11 | CONFIG_ARCH_U8500=y | 7 | CONFIG_ARCH_U8500=y |
| 12 | CONFIG_MACH_HREFV60=y | ||
| 13 | CONFIG_MACH_SNOWBALL=y | ||
| 14 | CONFIG_SMP=y | 8 | CONFIG_SMP=y |
| 15 | CONFIG_NR_CPUS=2 | 9 | CONFIG_NR_CPUS=2 |
| 16 | CONFIG_PREEMPT=y | ||
| 17 | CONFIG_AEABI=y | ||
| 18 | CONFIG_HIGHMEM=y | 10 | CONFIG_HIGHMEM=y |
| 19 | CONFIG_ARM_APPENDED_DTB=y | 11 | CONFIG_ARM_APPENDED_DTB=y |
| 20 | CONFIG_ARM_ATAG_DTB_COMPAT=y | 12 | CONFIG_ARM_ATAG_DTB_COMPAT=y |
| @@ -25,6 +17,11 @@ CONFIG_CPU_IDLE=y · 4 unmodified lines | |||
| 25 | CONFIG_ARM_U8500_CPUIDLE=y | 17 | CONFIG_ARM_U8500_CPUIDLE=y |
| 26 | CONFIG_VFP=y | 18 | CONFIG_VFP=y |
| 27 | CONFIG_NEON=y | 19 | CONFIG_NEON=y |
| 20 | CONFIG_MODULES=y | ||
| 21 | CONFIG_MODULE_UNLOAD=y | ||
| 22 | # CONFIG_BLK_DEV_BSG is not set | ||
| 23 | CONFIG_PARTITION_ADVANCED=y | ||
| 24 | CONFIG_CMA=y | ||
| 28 | CONFIG_NET=y | 25 | CONFIG_NET=y |
| 29 | CONFIG_PACKET=y | 26 | CONFIG_PACKET=y |
| 30 | CONFIG_UNIX=y | 27 | CONFIG_UNIX=y |
| @@ -47,7 +44,6 @@ CONFIG_SMSC911X=y · 16 unmodified lines | |||
| 47 | CONFIG_SMSC_PHY=y | 44 | CONFIG_SMSC_PHY=y |
| 48 | CONFIG_CW1200=y | 45 | CONFIG_CW1200=y |
| 49 | CONFIG_CW1200_WLAN_SDIO=y | 46 | CONFIG_CW1200_WLAN_SDIO=y |
| 50 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set | ||
| 51 | CONFIG_INPUT_EVDEV=y | 47 | CONFIG_INPUT_EVDEV=y |
| 52 | # CONFIG_KEYBOARD_ATKBD is not set | 48 | # CONFIG_KEYBOARD_ATKBD is not set |
| 53 | CONFIG_KEYBOARD_GPIO=y | 49 | CONFIG_KEYBOARD_GPIO=y |
| @@ -63,7 +59,6 @@ CONFIG_RMI4_CORE=y · 9 unmodified lines | |||
| 63 | CONFIG_RMI4_I2C=y | 59 | CONFIG_RMI4_I2C=y |
| 64 | CONFIG_RMI4_F11=y | 60 | CONFIG_RMI4_F11=y |
| 65 | # CONFIG_SERIO is not set | 61 | # CONFIG_SERIO is not set |
| 66 | CONFIG_VT_HW_CONSOLE_BINDING=y | ||
| 67 | # CONFIG_LEGACY_PTYS is not set | 62 | # CONFIG_LEGACY_PTYS is not set |
| 68 | CONFIG_SERIAL_AMBA_PL011=y | 63 | CONFIG_SERIAL_AMBA_PL011=y |
| 69 | CONFIG_SERIAL_AMBA_PL011_CONSOLE=y | 64 | CONFIG_SERIAL_AMBA_PL011_CONSOLE=y |
| @@ -72,6 +67,7 @@ CONFIG_SPI=y · 2 unmodified lines | |||
| 72 | CONFIG_SPI_PL022=y | 67 | CONFIG_SPI_PL022=y |
| 73 | CONFIG_GPIO_STMPE=y | 68 | CONFIG_GPIO_STMPE=y |
| 74 | CONFIG_GPIO_TC3589X=y | 69 | CONFIG_GPIO_TC3589X=y |
| 70 | CONFIG_SENSORS_IIO_HWMON=y | ||
| 75 | CONFIG_THERMAL=y | 71 | CONFIG_THERMAL=y |
| 76 | CONFIG_CPU_THERMAL=y | 72 | CONFIG_CPU_THERMAL=y |
| 77 | CONFIG_WATCHDOG=y | 73 | CONFIG_WATCHDOG=y |
| @@ -79,6 +75,13 @@ CONFIG_MFD_STMPE=y · 1 unmodified line | |||
| 79 | CONFIG_MFD_TC3589X=y | 75 | CONFIG_MFD_TC3589X=y |
| 80 | CONFIG_REGULATOR_AB8500=y | 76 | CONFIG_REGULATOR_AB8500=y |
| 81 | CONFIG_REGULATOR_GPIO=y | 77 | CONFIG_REGULATOR_GPIO=y |
| 78 | CONFIG_DRM=y | ||
| 79 | CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=y | ||
| 80 | CONFIG_DRM_LIMA=y | ||
| 81 | CONFIG_DRM_MCDE=y | ||
| 82 | CONFIG_BACKLIGHT_CLASS_DEVICE=y | ||
| 83 | CONFIG_BACKLIGHT_GENERIC=m | ||
| 84 | CONFIG_LOGO=y | ||
| 82 | CONFIG_SOUND=y | 85 | CONFIG_SOUND=y |
| 83 | CONFIG_SND=y | 86 | CONFIG_SND=y |
| 84 | CONFIG_SND_SOC=y | 87 | CONFIG_SND_SOC=y |
| @@ -87,6 +90,7 @@ CONFIG_SND_SOC_UX500_MACH_MOP500=y · 2 unmodified lines | |||
| 87 | CONFIG_USB=y | 90 | CONFIG_USB=y |
| 88 | CONFIG_USB_MUSB_HDRC=y | 91 | CONFIG_USB_MUSB_HDRC=y |
| 89 | CONFIG_USB_MUSB_UX500=y | 92 | CONFIG_USB_MUSB_UX500=y |
| 93 | CONFIG_MUSB_PIO_ONLY=y | ||
| 90 | CONFIG_AB8500_USB=y | 94 | CONFIG_AB8500_USB=y |
| 91 | CONFIG_USB_GADGET=y | 95 | CONFIG_USB_GADGET=y |
| 92 | CONFIG_USB_ETH=m | 96 | CONFIG_USB_ETH=m |
| @@ -103,6 +107,7 @@ CONFIG_RTC_DRV_AB8500=y · 10 unmodified lines | |||
| 103 | CONFIG_RTC_DRV_PL031=y | 107 | CONFIG_RTC_DRV_PL031=y |
| 104 | CONFIG_DMADEVICES=y | 108 | CONFIG_DMADEVICES=y |
| 105 | CONFIG_STE_DMA40=y | 109 | CONFIG_STE_DMA40=y |
| 110 | CONFIG_HWSPINLOCK=y | ||
| 106 | CONFIG_HSEM_U8500=y | 111 | CONFIG_HSEM_U8500=y |
| 107 | CONFIG_IIO=y | 112 | CONFIG_IIO=y |
| 108 | CONFIG_IIO_SW_TRIGGER=y | 113 | CONFIG_IIO_SW_TRIGGER=y |
| @@ -126,20 +131,19 @@ CONFIG_NFS_FS=y · 17 unmodified lines | |||
| 126 | CONFIG_ROOT_NFS=y | 131 | CONFIG_ROOT_NFS=y |
| 127 | CONFIG_NLS_CODEPAGE_437=y | 132 | CONFIG_NLS_CODEPAGE_437=y |
| 128 | CONFIG_NLS_ISO8859_1=y | 133 | CONFIG_NLS_ISO8859_1=y |
| 134 | CONFIG_CRYPTO_DEV_UX500=y | ||
| 135 | CONFIG_CRYPTO_DEV_UX500_CRYP=y | ||
| 136 | CONFIG_CRYPTO_DEV_UX500_HASH=y | ||
| 137 | CONFIG_CRYPTO_DEV_UX500_DEBUG=y | ||
| 129 | CONFIG_PRINTK_TIME=y | 138 | CONFIG_PRINTK_TIME=y |
| 130 | CONFIG_DEBUG_INFO=y | 139 | CONFIG_DEBUG_INFO=y |
| 131 | CONFIG_DEBUG_FS=y | 140 | CONFIG_DEBUG_FS=y |
| 132 | CONFIG_MAGIC_SYSRQ=y | 141 | CONFIG_MAGIC_SYSRQ=y |
| 133 | CONFIG_DEBUG_KERNEL=y | 142 | CONFIG_DEBUG_KERNEL=y |
| 134 | # CONFIG_SCHED_DEBUG is not set | 143 | # CONFIG_SCHED_DEBUG is not set |
| 135 | # CONFIG_DEBUG_PREEMPT is not set | ||
| 136 | # CONFIG_FTRACE is not set | 144 | # CONFIG_FTRACE is not set |
| 137 | CONFIG_DEBUG_USER=y | 145 | CONFIG_DEBUG_USER=y |
| 138 | CONFIG_CORESIGHT=y | 146 | CONFIG_CORESIGHT=y |
| 139 | CONFIG_CORESIGHT_SINK_TPIU=y | 147 | CONFIG_CORESIGHT_SINK_TPIU=y |
| 140 | CONFIG_CORESIGHT_SINK_ETBV10=y | 148 | CONFIG_CORESIGHT_SINK_ETBV10=y |
| 141 | CONFIG_CORESIGHT_SOURCE_ETM3X=y | 149 | CONFIG_CORESIGHT_SOURCE_ETM3X=y |
| 142 | CONFIG_CRYPTO_DEV_UX500=y | ||
| 143 | CONFIG_CRYPTO_DEV_UX500_CRYP=y | ||
| 144 | CONFIG_CRYPTO_DEV_UX500_HASH=y | ||
| 145 | CONFIG_CRYPTO_DEV_UX500_DEBUG=y | ||
| @@ -18,7 +18,9 @@ extern const struct dma_map_ops arm_coherent_dma_ops; · 17 unmodified lines | |||
| 18 | 18 | ||
| 19 | static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus) | 19 | static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus) |
| 20 | { | 20 | { |
| 21 | return IS_ENABLED(CONFIG_MMU) ? &arm_dma_ops : NULL; | 21 | if (IS_ENABLED(CONFIG_MMU) && !IS_ENABLED(CONFIG_ARM_LPAE)) |
| 22 | return &arm_dma_ops; | ||
| 23 | return NULL; | ||
| 22 | } | 24 | } |
| 23 | 25 | ||
| 24 | #ifdef __arch_page_to_dma | 26 | #ifdef __arch_page_to_dma |
| @@ -544,6 +544,7 @@ static int arch_build_bp_info(struct perf_event *bp, · 543 unmodified lines | |||
| 544 | if ((hw->ctrl.type != ARM_BREAKPOINT_EXECUTE) | 544 | if ((hw->ctrl.type != ARM_BREAKPOINT_EXECUTE) |
| 545 | && max_watchpoint_len >= 8) | 545 | && max_watchpoint_len >= 8) |
| 546 | break; | 546 | break; |
| 547 | /* Else, fall through */ | ||
| 547 | default: | 548 | default: |
| 548 | return -EINVAL; | 549 | return -EINVAL; |
| 549 | } | 550 | } |
| @@ -608,10 +609,12 @@ int hw_breakpoint_arch_parse(struct perf_event *bp, · 58 unmodified lines | |||
| 608 | /* Allow halfword watchpoints and breakpoints. */ | 609 | /* Allow halfword watchpoints and breakpoints. */ |
| 609 | if (hw->ctrl.len == ARM_BREAKPOINT_LEN_2) | 610 | if (hw->ctrl.len == ARM_BREAKPOINT_LEN_2) |
| 610 | break; | 611 | break; |
| 612 | /* Else, fall through */ | ||
| 611 | case 3: | 613 | case 3: |
| 612 | /* Allow single byte watchpoint. */ | 614 | /* Allow single byte watchpoint. */ |
| 613 | if (hw->ctrl.len == ARM_BREAKPOINT_LEN_1) | 615 | if (hw->ctrl.len == ARM_BREAKPOINT_LEN_1) |
| 614 | break; | 616 | break; |
| 617 | /* Else, fall through */ | ||
| 615 | default: | 618 | default: |
| 616 | ret = -EINVAL; | 619 | ret = -EINVAL; |
| 617 | goto out; | 620 | goto out; |
| @@ -861,6 +864,7 @@ static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr, · 243 unmodified lines | |||
| 861 | break; | 864 | break; |
| 862 | case ARM_ENTRY_ASYNC_WATCHPOINT: | 865 | case ARM_ENTRY_ASYNC_WATCHPOINT: |
| 863 | WARN(1, "Asynchronous watchpoint exception taken. Debugging results may be unreliable\n"); | 866 | WARN(1, "Asynchronous watchpoint exception taken. Debugging results may be unreliable\n"); |
| 867 | /* Fall through */ | ||
| 864 | case ARM_ENTRY_SYNC_WATCHPOINT: | 868 | case ARM_ENTRY_SYNC_WATCHPOINT: |
| 865 | watchpoint_handler(addr, fsr, regs); | 869 | watchpoint_handler(addr, fsr, regs); |
| 866 | break; | 870 | break; |
| @@ -909,6 +913,7 @@ static bool core_has_os_save_restore(void) · 42 unmodified lines | |||
| 909 | ARM_DBG_READ(c1, c1, 4, oslsr); | 913 | ARM_DBG_READ(c1, c1, 4, oslsr); |
| 910 | if (oslsr & ARM_OSLSR_OSLM0) | 914 | if (oslsr & ARM_OSLSR_OSLM0) |
| 911 | return true; | 915 | return true; |
| 916 | /* Else, fall through */ | ||
| 912 | default: | 917 | default: |
| 913 | return false; | 918 | return false; |
| 914 | } | 919 | } |
| @@ -596,6 +596,7 @@ static int do_signal(struct pt_regs *regs, int syscall) · 595 unmodified lines | |||
| 596 | switch (retval) { | 596 | switch (retval) { |
| 597 | case -ERESTART_RESTARTBLOCK: | 597 | case -ERESTART_RESTARTBLOCK: |
| 598 | restart -= 2; | 598 | restart -= 2; |
| 599 | /* Fall through */ | ||
| 599 | case -ERESTARTNOHAND: | 600 | case -ERESTARTNOHAND: |
| 600 | case -ERESTARTSYS: | 601 | case -ERESTARTSYS: |
| 601 | case -ERESTARTNOINTR: | 602 | case -ERESTARTNOINTR: |
| @@ -651,13 +651,22 @@ int kvm_handle_cp14_64(struct kvm_vcpu *vcpu, struct kvm_run *run) · 650 unmodified lines | |||
| 651 | } | 651 | } |
| 652 | 652 | ||
| 653 | static void reset_coproc_regs(struct kvm_vcpu *vcpu, | 653 | static void reset_coproc_regs(struct kvm_vcpu *vcpu, |
| 654 | const struct coproc_reg *table, size_t num) | 654 | const struct coproc_reg *table, size_t num, |
| 655 | unsigned long *bmap) | ||
| 655 | { | 656 | { |
| 656 | unsigned long i; | 657 | unsigned long i; |
| 657 | 658 | ||
| 658 | for (i = 0; i < num; i++) | 659 | for (i = 0; i < num; i++) |
| 659 | if (table[i].reset) | 660 | if (table[i].reset) { |
| 661 | int reg = table[i].reg; | ||
| 662 | |||
| 660 | table[i].reset(vcpu, &table[i]); | 663 | table[i].reset(vcpu, &table[i]); |
| 664 | if (reg > 0 && reg < NR_CP15_REGS) { | ||
| 665 | set_bit(reg, bmap); | ||
| 666 | if (table[i].is_64bit) | ||
| 667 | set_bit(reg + 1, bmap); | ||
| 668 | } | ||
| 669 | } | ||
| 661 | } | 670 | } |
| 662 | 671 | ||
| 663 | static struct coproc_params decode_32bit_hsr(struct kvm_vcpu *vcpu) | 672 | static struct coproc_params decode_32bit_hsr(struct kvm_vcpu *vcpu) |
| @@ -1432,17 +1441,15 @@ void kvm_reset_coprocs(struct kvm_vcpu *vcpu) · 768 unmodified lines | |||
| 1432 | { | 1441 | { |
| 1433 | size_t num; | 1442 | size_t num; |
| 1434 | const struct coproc_reg *table; | 1443 | const struct coproc_reg *table; |
| 1435 | 1444 | DECLARE_BITMAP(bmap, NR_CP15_REGS) = { 0, }; | |
| 1436 | /* Catch someone adding a register without putting in reset entry. */ | ||
| 1437 | memset(vcpu->arch.ctxt.cp15, 0x42, sizeof(vcpu->arch.ctxt.cp15)); | ||
| 1438 | 1445 | ||
| 1439 | /* Generic chip reset first (so target could override). */ | 1446 | /* Generic chip reset first (so target could override). */ |
| 1440 | reset_coproc_regs(vcpu, cp15_regs, ARRAY_SIZE(cp15_regs)); | 1447 | reset_coproc_regs(vcpu, cp15_regs, ARRAY_SIZE(cp15_regs), bmap); |
| 1441 | 1448 | ||
| 1442 | table = get_target_table(vcpu->arch.target, &num); | 1449 | table = get_target_table(vcpu->arch.target, &num); |
| 1443 | reset_coproc_regs(vcpu, table, num); | 1450 | reset_coproc_regs(vcpu, table, num, bmap); |
| 1444 | 1451 | ||
| 1445 | for (num = 1; num < NR_CP15_REGS; num++) | 1452 | for (num = 1; num < NR_CP15_REGS; num++) |
| 1446 | WARN(vcpu_cp15(vcpu, num) == 0x42424242, | 1453 | WARN(!test_bit(num, bmap), |
| 1447 | "Didn't reset vcpu_cp15(vcpu, %zi)", num); | 1454 | "Didn't reset vcpu_cp15(vcpu, %zi)", num); |
| 1448 | } | 1455 | } |
| @@ -24,6 +24,7 @@ · 23 unmodified lines | |||
| 24 | #define DEEPSLEEP_SLEEPENABLE_BIT BIT(31) | 24 | #define DEEPSLEEP_SLEEPENABLE_BIT BIT(31) |
| 25 | 25 | ||
| 26 | .text | 26 | .text |
| 27 | .arch armv5te | ||
| 27 | /* | 28 | /* |
| 28 | * Move DaVinci into deep sleep state | 29 | * Move DaVinci into deep sleep state |
| 29 | * | 30 | * |
| @@ -49,6 +49,7 @@ static int crunch_do(struct notifier_block *self, unsigned long cmd, void *t) · 48 unmodified lines | |||
| 49 | * FALLTHROUGH: Ensure we don't try to overwrite our newly | 49 | * FALLTHROUGH: Ensure we don't try to overwrite our newly |
| 50 | * initialised state information on the first fault. | 50 | * initialised state information on the first fault. |
| 51 | */ | 51 | */ |
| 52 | /* Fall through */ | ||
| 52 | 53 | ||
| 53 | case THREAD_NOTIFY_EXIT: | 54 | case THREAD_NOTIFY_EXIT: |
| 54 | crunch_task_release(thread); | 55 | crunch_task_release(thread); |
| @@ -1,22 +0,0 @@ | |||
| 1 | # SPDX-License-Identifier: GPL-2.0-only | ||
| 2 | menu "NetX Implementations" | ||
| 3 | depends on ARCH_NETX | ||
| 4 | |||
| 5 | config MACH_NXDKN | ||
| 6 | bool "Enable Hilscher nxdkn Eval Board support" | ||
| 7 | help | ||
| 8 | Board support for the Hilscher NetX Eval Board | ||
| 9 | |||
| 10 | config MACH_NXDB500 | ||
| 11 | bool "Enable Hilscher nxdb500 Eval Board support" | ||
| 12 | select ARM_AMBA | ||
| 13 | help | ||
| 14 | Board support for the Hilscher nxdb500 Eval Board | ||
| 15 | |||
| 16 | config MACH_NXEB500HMI | ||
| 17 | bool "Enable Hilscher nxeb500hmi Eval Board support" | ||
| 18 | select ARM_AMBA | ||
| 19 | help | ||
| 20 | Board support for the Hilscher nxeb500hmi Eval Board | ||
| 21 | |||
| 22 | endmenu | ||
| @@ -1,13 +0,0 @@ | |||
| 1 | # SPDX-License-Identifier: GPL-2.0-only | ||
| 2 | # | ||
| 3 | # Makefile for the linux kernel. | ||
| 4 | # | ||
| 5 | |||
| 6 | # Object file lists. | ||
| 7 | |||
| 8 | obj-y += time.o generic.o pfifo.o xc.o | ||
| 9 | |||
| 10 | # Specific board support | ||
| 11 | obj-$(CONFIG_MACH_NXDKN) += nxdkn.o | ||
| 12 | obj-$(CONFIG_MACH_NXDB500) += nxdb500.o fb.o | ||
| 13 | obj-$(CONFIG_MACH_NXEB500HMI) += nxeb500hmi.o fb.o | ||
| @@ -1,3 +0,0 @@ | |||
| 1 | # SPDX-License-Identifier: GPL-2.0-only | ||
| 2 | zreladdr-y += 0x80008000 | ||
| 3 | |||
| @@ -1,65 +0,0 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0-only | ||
| 2 | /* | ||
| 3 | * arch/arm/mach-netx/fb.c | ||
| 4 | * | ||
| 5 | * Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix | ||
| 6 | */ | ||
| 7 | |||
| 8 | #include <linux/device.h> | ||
| 9 | #include <linux/init.h> | ||
| 10 | #include <linux/dma-mapping.h> | ||
| 11 | #include <linux/amba/bus.h> | ||
| 12 | #include <linux/amba/clcd.h> | ||
| 13 | #include <linux/err.h> | ||
| 14 | #include <linux/gfp.h> | ||
| 15 | |||
| 16 | #include <asm/irq.h> | ||
| 17 | |||
| 18 | #include <mach/netx-regs.h> | ||
| 19 | #include <mach/hardware.h> | ||
| 20 | |||
| 21 | static struct clcd_panel *netx_panel; | ||
| 22 | |||
| 23 | void netx_clcd_enable(struct clcd_fb *fb) | ||
| 24 | { | ||
| 25 | } | ||
| 26 | |||
| 27 | int netx_clcd_setup(struct clcd_fb *fb) | ||
| 28 | { | ||
| 29 | dma_addr_t dma; | ||
| 30 | |||
| 31 | fb->panel = netx_panel; | ||
| 32 | |||
| 33 | fb->fb.screen_base = dma_alloc_wc(&fb->dev->dev, 1024 * 1024, &dma, | ||
| 34 | GFP_KERNEL); | ||
| 35 | if (!fb->fb.screen_base) { | ||
| 36 | printk(KERN_ERR "CLCD: unable to map framebuffer\n"); | ||
| 37 | return -ENOMEM; | ||
| 38 | } | ||
| 39 | |||
| 40 | fb->fb.fix.smem_start = dma; | ||
| 41 | fb->fb.fix.smem_len = 1024*1024; | ||
| 42 | |||
| 43 | return 0; | ||
| 44 | } | ||
| 45 | |||
| 46 | int netx_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma) | ||
| 47 | { | ||
| 48 | return dma_mmap_wc(&fb->dev->dev, vma, fb->fb.screen_base, | ||
| 49 | fb->fb.fix.smem_start, fb->fb.fix.smem_len); | ||
| 50 | } | ||
| 51 | |||
| 52 | void netx_clcd_remove(struct clcd_fb *fb) | ||
| 53 | { | ||
| 54 | dma_free_wc(&fb->dev->dev, fb->fb.fix.smem_len, fb->fb.screen_base, | ||
| 55 | fb->fb.fix.smem_start); | ||
| 56 | } | ||
| 57 | |||
| 58 | static AMBA_AHB_DEVICE(fb, "fb", 0, 0x00104000, { NETX_IRQ_LCD }, NULL); | ||
| 59 | |||
| 60 | int netx_fb_init(struct clcd_board *board, struct clcd_panel *panel) | ||
| 61 | { | ||
| 62 | netx_panel = panel; | ||
| 63 | fb_device.dev.platform_data = board; | ||
| 64 | return amba_device_register(&fb_device, &iomem_resource); | ||
| 65 | } | ||
| @@ -1,12 +0,0 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ | ||
| 2 | /* | ||
| 3 | * arch/arm/mach-netx/fb.h | ||
| 4 | * | ||
| 5 | * Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix | ||
| 6 | */ | ||
| 7 | |||
| 8 | void netx_clcd_enable(struct clcd_fb *fb); | ||
| 9 | int netx_clcd_setup(struct clcd_fb *fb); | ||
| 10 | int netx_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma); | ||
| 11 | void netx_clcd_remove(struct clcd_fb *fb); | ||
| 12 | int netx_fb_init(struct clcd_board *board, struct clcd_panel *panel); | ||
| @@ -1,182 +0,0 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0-only | ||
| 2 | /* | ||
| 3 | * arch/arm/mach-netx/generic.c | ||
| 4 | * | ||
| 5 | * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix | ||
| 6 | */ | ||
| 7 | |||
| 8 | #include <linux/device.h> | ||
| 9 | #include <linux/init.h> | ||
| 10 | #include <linux/kernel.h> | ||
| 11 | #include <linux/module.h> | ||
| 12 | #include <linux/platform_device.h> | ||
| 13 | #include <linux/io.h> | ||
| 14 | #include <linux/irqchip/arm-vic.h> | ||
| 15 | #include <linux/reboot.h> | ||
| 16 | #include <mach/hardware.h> | ||
| 17 | #include <asm/mach/map.h> | ||
| 18 | #include <mach/netx-regs.h> | ||
| 19 | #include <asm/mach/irq.h> | ||
| 20 | |||
| 21 | static struct map_desc netx_io_desc[] __initdata = { | ||
| 22 | { | ||
| 23 | .virtual = NETX_IO_VIRT, | ||
| 24 | .pfn = __phys_to_pfn(NETX_IO_PHYS), | ||
| 25 | .length = NETX_IO_SIZE, | ||
| 26 | .type = MT_DEVICE | ||
| 27 | } | ||
| 28 | }; | ||
| 29 | |||
| 30 | void __init netx_map_io(void) | ||
| 31 | { | ||
| 32 | iotable_init(netx_io_desc, ARRAY_SIZE(netx_io_desc)); | ||
| 33 | } | ||
| 34 | |||
| 35 | static struct resource netx_rtc_resources[] = { | ||
| 36 | [0] = { | ||
| 37 | .start = 0x00101200, | ||
| 38 | .end = 0x00101220, | ||
| 39 | .flags = IORESOURCE_MEM, | ||
| 40 | }, | ||
| 41 | }; | ||
| 42 | |||
| 43 | static struct platform_device netx_rtc_device = { | ||
| 44 | .name = "netx-rtc", | ||
| 45 | .id = 0, | ||
| 46 | .num_resources = ARRAY_SIZE(netx_rtc_resources), | ||
| 47 | .resource = netx_rtc_resources, | ||
| 48 | }; | ||
| 49 | |||
| 50 | static struct platform_device *devices[] __initdata = { | ||
| 51 | &netx_rtc_device, | ||
| 52 | }; | ||
| 53 | |||
| 54 | #if 0 | ||
| 55 | #define DEBUG_IRQ(fmt...) printk(fmt) | ||
| 56 | #else | ||
| 57 | #define DEBUG_IRQ(fmt...) while (0) {} | ||
| 58 | #endif | ||
| 59 | |||
| 60 | static void netx_hif_demux_handler(struct irq_desc *desc) | ||
| 61 | { | ||
| 62 | unsigned int irq = NETX_IRQ_HIF_CHAINED(0); | ||
| 63 | unsigned int stat; | ||
| 64 | |||
| 65 | stat = ((readl(NETX_DPMAS_INT_EN) & | ||
| 66 | readl(NETX_DPMAS_INT_STAT)) >> 24) & 0x1f; | ||
| 67 | |||
| 68 | while (stat) { | ||
| 69 | if (stat & 1) { | ||
| 70 | DEBUG_IRQ("handling irq %d\n", irq); | ||
| 71 | generic_handle_irq(irq); | ||
| 72 | } | ||
| 73 | irq++; | ||
| 74 | stat >>= 1; | ||
| 75 | } | ||
| 76 | } | ||
| 77 | |||
| 78 | static int | ||
| 79 | netx_hif_irq_type(struct irq_data *d, unsigned int type) | ||
| 80 | { | ||
| 81 | unsigned int val, irq; | ||
| 82 | |||
| 83 | val = readl(NETX_DPMAS_IF_CONF1); | ||
| 84 | |||
| 85 | irq = d->irq - NETX_IRQ_HIF_CHAINED(0); | ||
| 86 | |||
| 87 | if (type & IRQ_TYPE_EDGE_RISING) { | ||
| 88 | DEBUG_IRQ("rising edges\n"); | ||
| 89 | val |= (1 << 26) << irq; | ||
| 90 | } | ||
| 91 | if (type & IRQ_TYPE_EDGE_FALLING) { | ||
| 92 | DEBUG_IRQ("falling edges\n"); | ||
| 93 | val &= ~((1 << 26) << irq); | ||
| 94 | } | ||
| 95 | if (type & IRQ_TYPE_LEVEL_LOW) { | ||
| 96 | DEBUG_IRQ("low level\n"); | ||
| 97 | val &= ~((1 << 26) << irq); | ||
| 98 | } | ||
| 99 | if (type & IRQ_TYPE_LEVEL_HIGH) { | ||
| 100 | DEBUG_IRQ("high level\n"); | ||
| 101 | val |= (1 << 26) << irq; | ||
| 102 | } | ||
| 103 | |||
| 104 | writel(val, NETX_DPMAS_IF_CONF1); | ||
| 105 | |||
| 106 | return 0; | ||
| 107 | } | ||
| 108 | |||
| 109 | static void | ||
| 110 | netx_hif_ack_irq(struct irq_data *d) | ||
| 111 | { | ||
| 112 | unsigned int val, irq; | ||
| 113 | |||
| 114 | irq = d->irq - NETX_IRQ_HIF_CHAINED(0); | ||
| 115 | writel((1 << 24) << irq, NETX_DPMAS_INT_STAT); | ||
| 116 | |||
| 117 | val = readl(NETX_DPMAS_INT_EN); | ||
| 118 | val &= ~((1 << 24) << irq); | ||
| 119 | writel(val, NETX_DPMAS_INT_EN); | ||
| 120 | |||
| 121 | DEBUG_IRQ("%s: irq %d\n", __func__, d->irq); | ||
| 122 | } | ||
| 123 | |||
| 124 | static void | ||
| 125 | netx_hif_mask_irq(struct irq_data *d) | ||
| 126 | { | ||
| 127 | unsigned int val, irq; | ||
| 128 | |||
| 129 | irq = d->irq - NETX_IRQ_HIF_CHAINED(0); | ||
| 130 | val = readl(NETX_DPMAS_INT_EN); | ||
| 131 | val &= ~((1 << 24) << irq); | ||
| 132 | writel(val, NETX_DPMAS_INT_EN); | ||
| 133 | DEBUG_IRQ("%s: irq %d\n", __func__, d->irq); | ||
| 134 | } | ||
| 135 | |||
| 136 | static void | ||
| 137 | netx_hif_unmask_irq(struct irq_data *d) | ||
| 138 | { | ||
| 139 | unsigned int val, irq; | ||
| 140 | |||
| 141 | irq = d->irq - NETX_IRQ_HIF_CHAINED(0); | ||
| 142 | val = readl(NETX_DPMAS_INT_EN); | ||
| 143 | val |= (1 << 24) << irq; | ||
| 144 | writel(val, NETX_DPMAS_INT_EN); | ||
| 145 | DEBUG_IRQ("%s: irq %d\n", __func__, d->irq); | ||
| 146 | } | ||
| 147 | |||
| 148 | static struct irq_chip netx_hif_chip = { | ||
| 149 | .irq_ack = netx_hif_ack_irq, | ||
| 150 | .irq_mask = netx_hif_mask_irq, | ||
| 151 | .irq_unmask = netx_hif_unmask_irq, | ||
| 152 | .irq_set_type = netx_hif_irq_type, | ||
| 153 | }; | ||
| 154 | |||
| 155 | void __init netx_init_irq(void) | ||
| 156 | { | ||
| 157 | int irq; | ||
| 158 | |||
| 159 | vic_init(io_p2v(NETX_PA_VIC), NETX_IRQ_VIC_START, ~0, 0); | ||
| 160 | |||
| 161 | for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) { | ||
| 162 | irq_set_chip_and_handler(irq, &netx_hif_chip, | ||
| 163 | handle_level_irq); | ||
| 164 | irq_clear_status_flags(irq, IRQ_NOREQUEST); | ||
| 165 | } | ||
| 166 | |||
| 167 | writel(NETX_DPMAS_INT_EN_GLB_EN, NETX_DPMAS_INT_EN); | ||
| 168 | irq_set_chained_handler(NETX_IRQ_HIF, netx_hif_demux_handler); | ||
| 169 | } | ||
| 170 | |||
| 171 | static int __init netx_init(void) | ||
| 172 | { | ||
| 173 | return platform_add_devices(devices, ARRAY_SIZE(devices)); | ||
| 174 | } | ||
| 175 | |||
| 176 | subsys_initcall(netx_init); | ||
| 177 | |||
| 178 | void netx_restart(enum reboot_mode mode, const char *cmd) | ||
| 179 | { | ||
| 180 | writel(NETX_SYSTEM_RES_CR_FIRMW_RES_EN | NETX_SYSTEM_RES_CR_FIRMW_RES, | ||
| 181 | NETX_SYSTEM_RES_CR); | ||
| 182 | } | ||
| @@ -1,14 +0,0 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ | ||
| 2 | /* | ||
| 3 | * arch/arm/mach-netx/generic.h | ||
| 4 | * | ||
| 5 | * Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix | ||
| 6 | */ | ||
| 7 | |||
| 8 | #include <linux/reboot.h> | ||
| 9 | |||
| 10 | extern void __init netx_map_io(void); | ||
| 11 | extern void __init netx_init_irq(void); | ||
| 12 | extern void netx_restart(enum reboot_mode, const char *); | ||
| 13 | |||
| 14 | extern void netx_timer_init(void); | ||
| @@ -1,27 +0,0 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ | ||
| 2 | /* | ||
| 3 | * arch/arm/mach-netx/include/mach/hardware.h | ||
| 4 | * | ||
| 5 | * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix | ||
| 6 | */ | ||
| 7 | #ifndef __ASM_ARCH_HARDWARE_H | ||
| 8 | #define __ASM_ARCH_HARDWARE_H | ||
| 9 | |||
| 10 | #define NETX_IO_PHYS 0x00100000 | ||
| 11 | #define NETX_IO_VIRT 0xe0000000 | ||
| 12 | #define NETX_IO_SIZE 0x00100000 | ||
| 13 | |||
| 14 | #define SRAM_INTERNAL_PHYS_0 0x00000 | ||
| 15 | #define SRAM_INTERNAL_PHYS_1 0x08000 | ||
| 16 | #define SRAM_INTERNAL_PHYS_2 0x10000 | ||
| 17 | #define SRAM_INTERNAL_PHYS_3 0x18000 | ||
| 18 | #define SRAM_INTERNAL_PHYS(no) ((no) * 0x8000) | ||
| 19 | |||
| 20 | #define XPEC_MEM_SIZE 0x4000 | ||
| 21 | #define XMAC_MEM_SIZE 0x1000 | ||
| 22 | #define SRAM_MEM_SIZE 0x8000 | ||
| 23 | |||
| 24 | #define io_p2v(x) IOMEM((x) - NETX_IO_PHYS + NETX_IO_VIRT) | ||
| 25 | #define io_v2p(x) ((x) - NETX_IO_VIRT + NETX_IO_PHYS) | ||
| 26 | |||
| 27 | #endif | ||
| @@ -1,58 +0,0 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ | ||
| 2 | /* | ||
| 3 | * arch/arm/mach-netx/include/mach/irqs.h | ||
| 4 | * | ||
| 5 | * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix | ||
| 6 | */ | ||
| 7 | |||
| 8 | #define NETX_IRQ_VIC_START 64 | ||
| 9 | #define NETX_IRQ_SOFTINT (NETX_IRQ_VIC_START + 0) | ||
| 10 | #define NETX_IRQ_TIMER0 (NETX_IRQ_VIC_START + 1) | ||
| 11 | #define NETX_IRQ_TIMER1 (NETX_IRQ_VIC_START + 2) | ||
| 12 | #define NETX_IRQ_TIMER2 (NETX_IRQ_VIC_START + 3) | ||
| 13 | #define NETX_IRQ_SYSTIME_NS (NETX_IRQ_VIC_START + 4) | ||
| 14 | #define NETX_IRQ_SYSTIME_S (NETX_IRQ_VIC_START + 5) | ||
| 15 | #define NETX_IRQ_GPIO_15 (NETX_IRQ_VIC_START + 6) | ||
| 16 | #define NETX_IRQ_WATCHDOG (NETX_IRQ_VIC_START + 7) | ||
| 17 | #define NETX_IRQ_UART0 (NETX_IRQ_VIC_START + 8) | ||
| 18 | #define NETX_IRQ_UART1 (NETX_IRQ_VIC_START + 9) | ||
| 19 | #define NETX_IRQ_UART2 (NETX_IRQ_VIC_START + 10) | ||
| 20 | #define NETX_IRQ_USB (NETX_IRQ_VIC_START + 11) | ||
| 21 | #define NETX_IRQ_SPI (NETX_IRQ_VIC_START + 12) | ||
| 22 | #define NETX_IRQ_I2C (NETX_IRQ_VIC_START + 13) | ||
| 23 | #define NETX_IRQ_LCD (NETX_IRQ_VIC_START + 14) | ||
| 24 | #define NETX_IRQ_HIF (NETX_IRQ_VIC_START + 15) | ||
| 25 | #define NETX_IRQ_GPIO_0_14 (NETX_IRQ_VIC_START + 16) | ||
| 26 | #define NETX_IRQ_XPEC0 (NETX_IRQ_VIC_START + 17) | ||
| 27 | #define NETX_IRQ_XPEC1 (NETX_IRQ_VIC_START + 18) | ||
| 28 | #define NETX_IRQ_XPEC2 (NETX_IRQ_VIC_START + 19) | ||
| 29 | #define NETX_IRQ_XPEC3 (NETX_IRQ_VIC_START + 20) | ||
| 30 | #define NETX_IRQ_XPEC(no) (NETX_IRQ_VIC_START + 17 + (no)) | ||
| 31 | #define NETX_IRQ_MSYNC0 (NETX_IRQ_VIC_START + 21) | ||
| 32 | #define NETX_IRQ_MSYNC1 (NETX_IRQ_VIC_START + 22) | ||
| 33 | #define NETX_IRQ_MSYNC2 (NETX_IRQ_VIC_START + 23) | ||
| 34 | #define NETX_IRQ_MSYNC3 (NETX_IRQ_VIC_START + 24) | ||
| 35 | #define NETX_IRQ_IRQ_PHY (NETX_IRQ_VIC_START + 25) | ||
| 36 | #define NETX_IRQ_ISO_AREA (NETX_IRQ_VIC_START + 26) | ||
| 37 | /* int 27 is reserved */ | ||
| 38 | /* int 28 is reserved */ | ||
| 39 | #define NETX_IRQ_TIMER3 (NETX_IRQ_VIC_START + 29) | ||
| 40 | #define NETX_IRQ_TIMER4 (NETX_IRQ_VIC_START + 30) | ||
| 41 | /* int 31 is reserved */ | ||
| 42 | |||
| 43 | #define NETX_IRQS (NETX_IRQ_VIC_START + 32) | ||
| 44 | |||
| 45 | /* for multiplexed irqs on gpio 0..14 */ | ||
| 46 | #define NETX_IRQ_GPIO(x) (NETX_IRQS + (x)) | ||
| 47 | #define NETX_IRQ_GPIO_LAST NETX_IRQ_GPIO(14) | ||
| 48 | |||
| 49 | /* Host interface interrupts */ | ||
| 50 | #define NETX_IRQ_HIF_CHAINED(x) (NETX_IRQ_GPIO_LAST + 1 + (x)) | ||
| 51 | #define NETX_IRQ_HIF_PIO35 NETX_IRQ_HIF_CHAINED(0) | ||
| 52 | #define NETX_IRQ_HIF_PIO36 NETX_IRQ_HIF_CHAINED(1) | ||
| 53 | #define NETX_IRQ_HIF_PIO40 NETX_IRQ_HIF_CHAINED(2) | ||
| 54 | #define NETX_IRQ_HIF_PIO47 NETX_IRQ_HIF_CHAINED(3) | ||
| 55 | #define NETX_IRQ_HIF_PIO72 NETX_IRQ_HIF_CHAINED(4) | ||
| 56 | #define NETX_IRQ_HIF_LAST NETX_IRQ_HIF_CHAINED(4) | ||
| 57 | |||
| 58 | #define NR_IRQS (NETX_IRQ_HIF_LAST + 1) | ||
| @@ -1,420 +0,0 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ | ||
| 2 | /* | ||
| 3 | * arch/arm/mach-netx/include/mach/netx-regs.h | ||
| 4 | * | ||
| 5 | * Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix | ||
| 6 | */ | ||
| 7 | |||
| 8 | #ifndef __ASM_ARCH_NETX_REGS_H | ||
| 9 | #define __ASM_ARCH_NETX_REGS_H | ||
| 10 | |||
| 11 | /* offsets relative to the beginning of the io space */ | ||
| 12 | #define NETX_OFS_SYSTEM 0x00000 | ||
| 13 | #define NETX_OFS_MEMCR 0x00100 | ||
| 14 | #define NETX_OFS_DPMAS 0x03000 | ||
| 15 | #define NETX_OFS_GPIO 0x00800 | ||
| 16 | #define NETX_OFS_PIO 0x00900 | ||
| 17 | #define NETX_OFS_UART0 0x00a00 | ||
| 18 | #define NETX_OFS_UART1 0x00a40 | ||
| 19 | #define NETX_OFS_UART2 0x00a80 | ||
| 20 | #define NETX_OF_MIIMU 0x00b00 | ||
| 21 | #define NETX_OFS_SPI 0x00c00 | ||
| 22 | #define NETX_OFS_I2C 0x00d00 | ||
| 23 | #define NETX_OFS_SYSTIME 0x01100 | ||
| 24 | #define NETX_OFS_RTC 0x01200 | ||
| 25 | #define NETX_OFS_EXTBUS 0x03600 | ||
| 26 | #define NETX_OFS_LCD 0x04000 | ||
| 27 | #define NETX_OFS_USB 0x20000 | ||
| 28 | #define NETX_OFS_XMAC0 0x60000 | ||
| 29 | #define NETX_OFS_XMAC1 0x61000 | ||
| 30 | #define NETX_OFS_XMAC2 0x62000 | ||
| 31 | #define NETX_OFS_XMAC3 0x63000 | ||
| 32 | #define NETX_OFS_XMAC(no) (0x60000 + (no) * 0x1000) | ||
| 33 | #define NETX_OFS_PFIFO 0x64000 | ||
| 34 | #define NETX_OFS_XPEC0 0x70000 | ||
| 35 | #define NETX_OFS_XPEC1 0x74000 | ||
| 36 | #define NETX_OFS_XPEC2 0x78000 | ||
| 37 | #define NETX_OFS_XPEC3 0x7c000 | ||
| 38 | #define NETX_OFS_XPEC(no) (0x70000 + (no) * 0x4000) | ||
| 39 | #define NETX_OFS_VIC 0xff000 | ||
| 40 | |||
| 41 | /* physical addresses */ | ||
| 42 | #define NETX_PA_SYSTEM (NETX_IO_PHYS + NETX_OFS_SYSTEM) | ||
| 43 | #define NETX_PA_MEMCR (NETX_IO_PHYS + NETX_OFS_MEMCR) | ||
| 44 | #define NETX_PA_DPMAS (NETX_IO_PHYS + NETX_OFS_DPMAS) | ||
| 45 | #define NETX_PA_GPIO (NETX_IO_PHYS + NETX_OFS_GPIO) | ||
| 46 | #define NETX_PA_PIO (NETX_IO_PHYS + NETX_OFS_PIO) | ||
| 47 | #define NETX_PA_UART0 (NETX_IO_PHYS + NETX_OFS_UART0) | ||
| 48 | #define NETX_PA_UART1 (NETX_IO_PHYS + NETX_OFS_UART1) | ||
| 49 | #define NETX_PA_UART2 (NETX_IO_PHYS + NETX_OFS_UART2) | ||
| 50 | #define NETX_PA_MIIMU (NETX_IO_PHYS + NETX_OF_MIIMU) | ||
| 51 | #define NETX_PA_SPI (NETX_IO_PHYS + NETX_OFS_SPI) | ||
| 52 | #define NETX_PA_I2C (NETX_IO_PHYS + NETX_OFS_I2C) | ||
| 53 | #define NETX_PA_SYSTIME (NETX_IO_PHYS + NETX_OFS_SYSTIME) | ||
| 54 | #define NETX_PA_RTC (NETX_IO_PHYS + NETX_OFS_RTC) | ||
| 55 | #define NETX_PA_EXTBUS (NETX_IO_PHYS + NETX_OFS_EXTBUS) | ||
| 56 | #define NETX_PA_LCD (NETX_IO_PHYS + NETX_OFS_LCD) | ||
| 57 | #define NETX_PA_USB (NETX_IO_PHYS + NETX_OFS_USB) | ||
| 58 | #define NETX_PA_XMAC0 (NETX_IO_PHYS + NETX_OFS_XMAC0) | ||
| 59 | #define NETX_PA_XMAC1 (NETX_IO_PHYS + NETX_OFS_XMAC1) | ||
| 60 | #define NETX_PA_XMAC2 (NETX_IO_PHYS + NETX_OFS_XMAC2) | ||
| 61 | #define NETX_PA_XMAC3 (NETX_IO_PHYS + NETX_OFS_XMAC3) | ||
| 62 | #define NETX_PA_XMAC(no) (NETX_IO_PHYS + NETX_OFS_XMAC(no)) | ||
| 63 | #define NETX_PA_PFIFO (NETX_IO_PHYS + NETX_OFS_PFIFO) | ||
| 64 | #define NETX_PA_XPEC0 (NETX_IO_PHYS + NETX_OFS_XPEC0) | ||
| 65 | #define NETX_PA_XPEC1 (NETX_IO_PHYS + NETX_OFS_XPEC1) | ||
| 66 | #define NETX_PA_XPEC2 (NETX_IO_PHYS + NETX_OFS_XPEC2) | ||
| 67 | #define NETX_PA_XPEC3 (NETX_IO_PHYS + NETX_OFS_XPEC3) | ||
| 68 | #define NETX_PA_XPEC(no) (NETX_IO_PHYS + NETX_OFS_XPEC(no)) | ||
| 69 | #define NETX_PA_VIC (NETX_IO_PHYS + NETX_OFS_VIC) | ||
| 70 | |||
| 71 | /* virtual addresses */ | ||
| 72 | #define NETX_VA_SYSTEM (NETX_IO_VIRT + NETX_OFS_SYSTEM) | ||
| 73 | #define NETX_VA_MEMCR (NETX_IO_VIRT + NETX_OFS_MEMCR) | ||
| 74 | #define NETX_VA_DPMAS (NETX_IO_VIRT + NETX_OFS_DPMAS) | ||
| 75 | #define NETX_VA_GPIO (NETX_IO_VIRT + NETX_OFS_GPIO) | ||
| 76 | #define NETX_VA_PIO (NETX_IO_VIRT + NETX_OFS_PIO) | ||
| 77 | #define NETX_VA_UART0 (NETX_IO_VIRT + NETX_OFS_UART0) | ||
| 78 | #define NETX_VA_UART1 (NETX_IO_VIRT + NETX_OFS_UART1) | ||
| 79 | #define NETX_VA_UART2 (NETX_IO_VIRT + NETX_OFS_UART2) | ||
| 80 | #define NETX_VA_MIIMU (NETX_IO_VIRT + NETX_OF_MIIMU) | ||
| 81 | #define NETX_VA_SPI (NETX_IO_VIRT + NETX_OFS_SPI) | ||
| 82 | #define NETX_VA_I2C (NETX_IO_VIRT + NETX_OFS_I2C) | ||
| 83 | #define NETX_VA_SYSTIME (NETX_IO_VIRT + NETX_OFS_SYSTIME) | ||
| 84 | #define NETX_VA_RTC (NETX_IO_VIRT + NETX_OFS_RTC) | ||
| 85 | #define NETX_VA_EXTBUS (NETX_IO_VIRT + NETX_OFS_EXTBUS) | ||
| 86 | #define NETX_VA_LCD (NETX_IO_VIRT + NETX_OFS_LCD) | ||
| 87 | #define NETX_VA_USB (NETX_IO_VIRT + NETX_OFS_USB) | ||
| 88 | #define NETX_VA_XMAC0 (NETX_IO_VIRT + NETX_OFS_XMAC0) | ||
| 89 | #define NETX_VA_XMAC1 (NETX_IO_VIRT + NETX_OFS_XMAC1) | ||
| 90 | #define NETX_VA_XMAC2 (NETX_IO_VIRT + NETX_OFS_XMAC2) | ||
| 91 | #define NETX_VA_XMAC3 (NETX_IO_VIRT + NETX_OFS_XMAC3) | ||
| 92 | #define NETX_VA_XMAC(no) (NETX_IO_VIRT + NETX_OFS_XMAC(no)) | ||
| 93 | #define NETX_VA_PFIFO (NETX_IO_VIRT + NETX_OFS_PFIFO) | ||
| 94 | #define NETX_VA_XPEC0 (NETX_IO_VIRT + NETX_OFS_XPEC0) | ||
| 95 | #define NETX_VA_XPEC1 (NETX_IO_VIRT + NETX_OFS_XPEC1) | ||
| 96 | #define NETX_VA_XPEC2 (NETX_IO_VIRT + NETX_OFS_XPEC2) | ||
| 97 | #define NETX_VA_XPEC3 (NETX_IO_VIRT + NETX_OFS_XPEC3) | ||
| 98 | #define NETX_VA_XPEC(no) (NETX_IO_VIRT + NETX_OFS_XPEC(no)) | ||
| 99 | #define NETX_VA_VIC (NETX_IO_VIRT + NETX_OFS_VIC) | ||
| 100 | |||
| 101 | /********************************* | ||
| 102 | * System functions * | ||
| 103 | *********************************/ | ||
| 104 | |||
| 105 | /* Registers */ | ||
| 106 | #define NETX_SYSTEM_REG(ofs) IOMEM(NETX_VA_SYSTEM + (ofs)) | ||
| 107 | #define NETX_SYSTEM_BOO_SR NETX_SYSTEM_REG(0x00) | ||
| 108 | #define NETX_SYSTEM_IOC_CR NETX_SYSTEM_REG(0x04) | ||
| 109 | #define NETX_SYSTEM_IOC_MR NETX_SYSTEM_REG(0x08) | ||
| 110 | |||
| 111 | /* FIXME: Docs are not consistent */ | ||
| 112 | /* #define NETX_SYSTEM_RES_CR NETX_SYSTEM_REG(0x08) */ | ||
| 113 | #define NETX_SYSTEM_RES_CR NETX_SYSTEM_REG(0x0c) | ||
| 114 | |||
| 115 | #define NETX_SYSTEM_PHY_CONTROL NETX_SYSTEM_REG(0x10) | ||
| 116 | #define NETX_SYSTEM_REV NETX_SYSTEM_REG(0x34) | ||
| 117 | #define NETX_SYSTEM_IOC_ACCESS_KEY NETX_SYSTEM_REG(0x70) | ||
| 118 | #define NETX_SYSTEM_WDG_TR NETX_SYSTEM_REG(0x200) | ||
| 119 | #define NETX_SYSTEM_WDG_CTR NETX_SYSTEM_REG(0x204) | ||
| 120 | #define NETX_SYSTEM_WDG_IRQ_TIMEOUT NETX_SYSTEM_REG(0x208) | ||
| 121 | #define NETX_SYSTEM_WDG_RES_TIMEOUT NETX_SYSTEM_REG(0x20c) | ||
| 122 | |||
| 123 | /* Bits */ | ||
| 124 | #define NETX_SYSTEM_RES_CR_RSTIN (1<<0) | ||
| 125 | #define NETX_SYSTEM_RES_CR_WDG_RES (1<<1) | ||
| 126 | #define NETX_SYSTEM_RES_CR_HOST_RES (1<<2) | ||
| 127 | #define NETX_SYSTEM_RES_CR_FIRMW_RES (1<<3) | ||
| 128 | #define NETX_SYSTEM_RES_CR_XPEC0_RES (1<<4) | ||
| 129 | #define NETX_SYSTEM_RES_CR_XPEC1_RES (1<<5) | ||
| 130 | #define NETX_SYSTEM_RES_CR_XPEC2_RES (1<<6) | ||
| 131 | #define NETX_SYSTEM_RES_CR_XPEC3_RES (1<<7) | ||
| 132 | #define NETX_SYSTEM_RES_CR_DIS_XPEC0_RES (1<<16) | ||
| 133 | #define NETX_SYSTEM_RES_CR_DIS_XPEC1_RES (1<<17) | ||
| 134 | #define NETX_SYSTEM_RES_CR_DIS_XPEC2_RES (1<<18) | ||
| 135 | #define NETX_SYSTEM_RES_CR_DIS_XPEC3_RES (1<<19) | ||
| 136 | #define NETX_SYSTEM_RES_CR_FIRMW_FLG0 (1<<20) | ||
| 137 | #define NETX_SYSTEM_RES_CR_FIRMW_FLG1 (1<<21) | ||
| 138 | #define NETX_SYSTEM_RES_CR_FIRMW_FLG2 (1<<22) | ||
| 139 | #define NETX_SYSTEM_RES_CR_FIRMW_FLG3 (1<<23) | ||
| 140 | #define NETX_SYSTEM_RES_CR_FIRMW_RES_EN (1<<24) | ||
| 141 | #define NETX_SYSTEM_RES_CR_RSTOUT (1<<25) | ||
| 142 | #define NETX_SYSTEM_RES_CR_EN_RSTOUT (1<<26) | ||
| 143 | |||
| 144 | #define PHY_CONTROL_RESET (1<<31) | ||
| 145 | #define PHY_CONTROL_SIM_BYP (1<<30) | ||
| 146 | #define PHY_CONTROL_CLK_XLATIN (1<<29) | ||
| 147 | #define PHY_CONTROL_PHY1_EN (1<<21) | ||
| 148 | #define PHY_CONTROL_PHY1_NP_MSG_CODE | ||
| 149 | #define PHY_CONTROL_PHY1_AUTOMDIX (1<<17) | ||
| 150 | #define PHY_CONTROL_PHY1_FIXMODE (1<<16) | ||
| 151 | #define PHY_CONTROL_PHY1_MODE(mode) (((mode) & 0x7) << 13) | ||
| 152 | #define PHY_CONTROL_PHY0_EN (1<<12) | ||
| 153 | #define PHY_CONTROL_PHY0_NP_MSG_CODE | ||
| 154 | #define PHY_CONTROL_PHY0_AUTOMDIX (1<<8) | ||
| 155 | #define PHY_CONTROL_PHY0_FIXMODE (1<<7) | ||
| 156 | #define PHY_CONTROL_PHY0_MODE(mode) (((mode) & 0x7) << 4) | ||
| 157 | #define PHY_CONTROL_PHY_ADDRESS(adr) ((adr) & 0xf) | ||
| 158 | |||
| 159 | #define PHY_MODE_10BASE_T_HALF 0 | ||
| 160 | #define PHY_MODE_10BASE_T_FULL 1 | ||
| 161 | #define PHY_MODE_100BASE_TX_FX_FULL 2 | ||
| 162 | #define PHY_MODE_100BASE_TX_FX_HALF 3 | ||
| 163 | #define PHY_MODE_100BASE_TX_HALF 4 | ||
| 164 | #define PHY_MODE_REPEATER 5 | ||
| 165 | #define PHY_MODE_POWER_DOWN 6 | ||
| 166 | #define PHY_MODE_ALL 7 | ||
| 167 | |||
| 168 | /* Bits */ | ||
| 169 | #define VECT_CNTL_ENABLE (1 << 5) | ||
| 170 | |||
| 171 | /******************************* | ||
| 172 | * GPIO and timer module * | ||
| 173 | *******************************/ | ||
| 174 | |||
| 175 | /* Registers */ | ||
| 176 | #define NETX_GPIO_REG(ofs) IOMEM(NETX_VA_GPIO + (ofs)) | ||
| 177 | #define NETX_GPIO_CFG(gpio) NETX_GPIO_REG(0x0 + ((gpio)<<2)) | ||
| 178 | #define NETX_GPIO_THRESHOLD_CAPTURE(gpio) NETX_GPIO_REG(0x40 + ((gpio)<<2)) | ||
| 179 | #define NETX_GPIO_COUNTER_CTRL(counter) NETX_GPIO_REG(0x80 + ((counter)<<2)) | ||
| 180 | #define NETX_GPIO_COUNTER_MAX(counter) NETX_GPIO_REG(0x94 + ((counter)<<2)) | ||
| 181 | #define NETX_GPIO_COUNTER_CURRENT(counter) NETX_GPIO_REG(0xa8 + ((counter)<<2)) | ||
| 182 | #define NETX_GPIO_IRQ_ENABLE NETX_GPIO_REG(0xbc) | ||
| 183 | #define NETX_GPIO_IRQ_DISABLE NETX_GPIO_REG(0xc0) | ||
| 184 | #define NETX_GPIO_SYSTIME_NS_CMP NETX_GPIO_REG(0xc4) | ||
| 185 | #define NETX_GPIO_LINE NETX_GPIO_REG(0xc8) | ||
| 186 | #define NETX_GPIO_IRQ NETX_GPIO_REG(0xd0) | ||
| 187 | |||
| 188 | /* Bits */ | ||
| 189 | #define NETX_GPIO_CFG_IOCFG_GP_INPUT (0x0) | ||
| 190 | #define NETX_GPIO_CFG_IOCFG_GP_OUTPUT (0x1) | ||
| 191 | #define NETX_GPIO_CFG_IOCFG_GP_UART (0x2) | ||
| 192 | #define NETX_GPIO_CFG_INV (1<<2) | ||
| 193 | #define NETX_GPIO_CFG_MODE_INPUT_READ (0<<3) | ||
| 194 | #define NETX_GPIO_CFG_MODE_INPUT_CAPTURE_CONT_RISING (1<<3) | ||
| 195 | #define NETX_GPIO_CFG_MODE_INPUT_CAPTURE_ONCE_RISING (2<<3) | ||
| 196 | #define NETX_GPIO_CFG_MODE_INPUT_CAPTURE_HIGH_LEVEL (3<<3) | ||
| 197 | #define NETX_GPIO_CFG_COUNT_REF_COUNTER0 (0<<5) | ||
| 198 | #define NETX_GPIO_CFG_COUNT_REF_COUNTER1 (1<<5) | ||
| 199 | #define NETX_GPIO_CFG_COUNT_REF_COUNTER2 (2<<5) | ||
| 200 | #define NETX_GPIO_CFG_COUNT_REF_COUNTER3 (3<<5) | ||
| 201 | #define NETX_GPIO_CFG_COUNT_REF_COUNTER4 (4<<5) | ||
| 202 | #define NETX_GPIO_CFG_COUNT_REF_SYSTIME (7<<5) | ||
| 203 | |||
| 204 | #define NETX_GPIO_COUNTER_CTRL_RUN (1<<0) | ||
| 205 | #define NETX_GPIO_COUNTER_CTRL_SYM (1<<1) | ||
| 206 | #define NETX_GPIO_COUNTER_CTRL_ONCE (1<<2) | ||
| 207 | #define NETX_GPIO_COUNTER_CTRL_IRQ_EN (1<<3) | ||
| 208 | #define NETX_GPIO_COUNTER_CTRL_CNT_EVENT (1<<4) | ||
| 209 | #define NETX_GPIO_COUNTER_CTRL_RST_EN (1<<5) | ||
| 210 | #define NETX_GPIO_COUNTER_CTRL_SEL_EVENT (1<<6) | ||
| 211 | #define NETX_GPIO_COUNTER_CTRL_GPIO_REF /* FIXME */ | ||
| 212 | |||
| 213 | #define GPIO_BIT(gpio) (1<<(gpio)) | ||
| 214 | #define COUNTER_BIT(counter) ((1<<16)<<(counter)) | ||
| 215 | |||
| 216 | /******************************* | ||
| 217 | * PIO * | ||
| 218 | *******************************/ | ||
| 219 | |||
| 220 | /* Registers */ | ||
| 221 | #define NETX_PIO_REG(ofs) IOMEM(NETX_VA_PIO + (ofs)) | ||
| 222 | #define NETX_PIO_INPIO NETX_PIO_REG(0x0) | ||
| 223 | #define NETX_PIO_OUTPIO NETX_PIO_REG(0x4) | ||
| 224 | #define NETX_PIO_OEPIO NETX_PIO_REG(0x8) | ||
| 225 | |||
| 226 | /******************************* | ||
| 227 | * MII Unit * | ||
| 228 | *******************************/ | ||
| 229 | |||
| 230 | /* Registers */ | ||
| 231 | #define NETX_MIIMU IOMEM(NETX_VA_MIIMU) | ||
| 232 | |||
| 233 | /* Bits */ | ||
| 234 | #define MIIMU_SNRDY (1<<0) | ||
| 235 | #define MIIMU_PREAMBLE (1<<1) | ||
| 236 | #define MIIMU_OPMODE_WRITE (1<<2) | ||
| 237 | #define MIIMU_MDC_PERIOD (1<<3) | ||
| 238 | #define MIIMU_PHY_NRES (1<<4) | ||
| 239 | #define MIIMU_RTA (1<<5) | ||
| 240 | #define MIIMU_REGADDR(adr) (((adr) & 0x1f) << 6) | ||
| 241 | #define MIIMU_PHYADDR(adr) (((adr) & 0x1f) << 11) | ||
| 242 | #define MIIMU_DATA(data) (((data) & 0xffff) << 16) | ||
| 243 | |||
| 244 | /******************************* | ||
| 245 | * xmac / xpec * | ||
| 246 | *******************************/ | ||
| 247 | |||
| 248 | /* XPEC register offsets relative to NETX_VA_XPEC(no) */ | ||
| 249 | #define NETX_XPEC_R0_OFS 0x00 | ||
| 250 | #define NETX_XPEC_R1_OFS 0x04 | ||
| 251 | #define NETX_XPEC_R2_OFS 0x08 | ||
| 252 | #define NETX_XPEC_R3_OFS 0x0c | ||
| 253 | #define NETX_XPEC_R4_OFS 0x10 | ||
| 254 | #define NETX_XPEC_R5_OFS 0x14 | ||
| 255 | #define NETX_XPEC_R6_OFS 0x18 | ||
| 256 | #define NETX_XPEC_R7_OFS 0x1c | ||
| 257 | #define NETX_XPEC_RANGE01_OFS 0x20 | ||
| 258 | #define NETX_XPEC_RANGE23_OFS 0x24 | ||
| 259 | #define NETX_XPEC_RANGE45_OFS 0x28 | ||
| 260 | #define NETX_XPEC_RANGE67_OFS 0x2c | ||
| 261 | #define NETX_XPEC_PC_OFS 0x48 | ||
| 262 | #define NETX_XPEC_TIMER_OFS(timer) (0x30 + ((timer)<<2)) | ||
| 263 | #define NETX_XPEC_IRQ_OFS 0x8c | ||
| 264 | #define NETX_XPEC_SYSTIME_NS_OFS 0x90 | ||
| 265 | #define NETX_XPEC_FIFO_DATA_OFS 0x94 | ||
| 266 | #define NETX_XPEC_SYSTIME_S_OFS 0x98 | ||
| 267 | #define NETX_XPEC_ADC_OFS 0x9c | ||
| 268 | #define NETX_XPEC_URX_COUNT_OFS 0x40 | ||
| 269 | #define NETX_XPEC_UTX_COUNT_OFS 0x44 | ||
| 270 | #define NETX_XPEC_PC_OFS 0x48 | ||
| 271 | #define NETX_XPEC_ZERO_OFS 0x4c | ||
| 272 | #define NETX_XPEC_STATCFG_OFS 0x50 | ||
| 273 | #define NETX_XPEC_EC_MASKA_OFS 0x54 | ||
| 274 | #define NETX_XPEC_EC_MASKB_OFS 0x58 | ||
| 275 | #define NETX_XPEC_EC_MASK0_OFS 0x5c | ||
| 276 | #define NETX_XPEC_EC_MASK8_OFS 0x7c | ||
| 277 | #define NETX_XPEC_EC_MASK9_OFS 0x80 | ||
| 278 | #define NETX_XPEC_XPU_HOLD_PC_OFS 0x100 | ||
| 279 | #define NETX_XPEC_RAM_START_OFS 0x2000 | ||
| 280 | |||
| 281 | /* Bits */ | ||
| 282 | #define XPU_HOLD_PC (1<<0) | ||
| 283 | |||
| 284 | /* XMAC register offsets relative to NETX_VA_XMAC(no) */ | ||
| 285 | #define NETX_XMAC_RPU_PROGRAM_START_OFS 0x000 | ||
| 286 | #define NETX_XMAC_RPU_PROGRAM_END_OFS 0x3ff | ||
| 287 | #define NETX_XMAC_TPU_PROGRAM_START_OFS 0x400 | ||
| 288 | #define NETX_XMAC_TPU_PROGRAM_END_OFS 0x7ff | ||
| 289 | #define NETX_XMAC_RPU_HOLD_PC_OFS 0xa00 | ||
| 290 | #define NETX_XMAC_TPU_HOLD_PC_OFS 0xa04 | ||
| 291 | #define NETX_XMAC_STATUS_SHARED0_OFS 0x840 | ||
| 292 | #define NETX_XMAC_CONFIG_SHARED0_OFS 0x844 | ||
| 293 | #define NETX_XMAC_STATUS_SHARED1_OFS 0x848 | ||
| 294 | #define NETX_XMAC_CONFIG_SHARED1_OFS 0x84c | ||
| 295 | #define NETX_XMAC_STATUS_SHARED2_OFS 0x850 | ||
| 296 | #define NETX_XMAC_CONFIG_SHARED2_OFS 0x854 | ||
| 297 | #define NETX_XMAC_STATUS_SHARED3_OFS 0x858 | ||
| 298 | #define NETX_XMAC_CONFIG_SHARED3_OFS 0x85c | ||
| 299 | |||
| 300 | #define RPU_HOLD_PC (1<<15) | ||
| 301 | #define TPU_HOLD_PC (1<<15) | ||
| 302 | |||
| 303 | /******************************* | ||
| 304 | * Pointer FIFO * | ||
| 305 | *******************************/ | ||
| 306 | |||
| 307 | /* Registers */ | ||
| 308 | #define NETX_PFIFO_REG(ofs) IOMEM(NETX_VA_PFIFO + (ofs)) | ||
| 309 | #define NETX_PFIFO_BASE(pfifo) NETX_PFIFO_REG(0x00 + ((pfifo)<<2)) | ||
| 310 | #define NETX_PFIFO_BORDER_BASE(pfifo) NETX_PFIFO_REG(0x80 + ((pfifo)<<2)) | ||
| 311 | #define NETX_PFIFO_RESET NETX_PFIFO_REG(0x100) | ||
| 312 | #define NETX_PFIFO_FULL NETX_PFIFO_REG(0x104) | ||
| 313 | #define NETX_PFIFO_EMPTY NETX_PFIFO_REG(0x108) | ||
| 314 | #define NETX_PFIFO_OVEFLOW NETX_PFIFO_REG(0x10c) | ||
| 315 | #define NETX_PFIFO_UNDERRUN NETX_PFIFO_REG(0x110) | ||
| 316 | #define NETX_PFIFO_FILL_LEVEL(pfifo) NETX_PFIFO_REG(0x180 + ((pfifo)<<2)) | ||
| 317 | #define NETX_PFIFO_XPEC_ISR(xpec) NETX_PFIFO_REG(0x400 + ((xpec) << 2)) | ||
| 318 | |||
| 319 | |||
| 320 | /******************************* | ||
| 321 | * Memory Controller * | ||
| 322 | *******************************/ | ||
| 323 | |||
| 324 | /* Registers */ | ||
| 325 | #define NETX_MEMCR_REG(ofs) IOMEM(NETX_VA_MEMCR + (ofs)) | ||
| 326 | #define NETX_MEMCR_SRAM_CTRL(cs) NETX_MEMCR_REG(0x0 + 4 * (cs)) /* SRAM for CS 0..2 */ | ||
| 327 | #define NETX_MEMCR_SDRAM_CFG_CTRL NETX_MEMCR_REG(0x40) | ||
| 328 | #define NETX_MEMCR_SDRAM_TIMING_CTRL NETX_MEMCR_REG(0x44) | ||
| 329 | #define NETX_MEMCR_SDRAM_MODE NETX_MEMCR_REG(0x48) | ||
| 330 | #define NETX_MEMCR_SDRAM_EXT_MODE NETX_MEMCR_REG(0x4c) | ||
| 331 | #define NETX_MEMCR_PRIO_TIMESLOT_CTRL NETX_MEMCR_REG(0x80) | ||
| 332 | #define NETX_MEMCR_PRIO_ACCESS_CTRL NETX_MEMCR_REG(0x84) | ||
| 333 | |||
| 334 | /* Bits */ | ||
| 335 | #define NETX_MEMCR_SRAM_CTRL_WIDTHEXTMEM(x) (((x) & 0x3) << 24) | ||
| 336 | #define NETX_MEMCR_SRAM_CTRL_WSPOSTPAUSEEXTMEM(x) (((x) & 0x3) << 16) | ||
| 337 | #define NETX_MEMCR_SRAM_CTRL_WSPREPASEEXTMEM(x) (((x) & 0x3) << 8) | ||
| 338 | #define NETX_MEMCR_SRAM_CTRL_WSEXTMEM(x) (((x) & 0x1f) << 0) | ||
| 339 | |||
| 340 | |||
| 341 | /******************************* | ||
| 342 | * Dual Port Memory * | ||
| 343 | *******************************/ | ||
| 344 | |||
| 345 | /* Registers */ | ||
| 346 | #define NETX_DPMAS_REG(ofs) IOMEM(NETX_VA_DPMAS + (ofs)) | ||
| 347 | #define NETX_DPMAS_SYS_STAT NETX_DPMAS_REG(0x4d8) | ||
| 348 | #define NETX_DPMAS_INT_STAT NETX_DPMAS_REG(0x4e0) | ||
| 349 | #define NETX_DPMAS_INT_EN NETX_DPMAS_REG(0x4f0) | ||
| 350 | #define NETX_DPMAS_IF_CONF0 NETX_DPMAS_REG(0x608) | ||
| 351 | #define NETX_DPMAS_IF_CONF1 NETX_DPMAS_REG(0x60c) | ||
| 352 | #define NETX_DPMAS_EXT_CONFIG(cs) NETX_DPMAS_REG(0x610 + 4 * (cs)) | ||
| 353 | #define NETX_DPMAS_IO_MODE0 NETX_DPMAS_REG(0x620) /* I/O 32..63 */ | ||
| 354 | #define NETX_DPMAS_DRV_EN0 NETX_DPMAS_REG(0x624) | ||
| 355 | #define NETX_DPMAS_DATA0 NETX_DPMAS_REG(0x628) | ||
| 356 | #define NETX_DPMAS_IO_MODE1 NETX_DPMAS_REG(0x630) /* I/O 64..84 */ | ||
| 357 | #define NETX_DPMAS_DRV_EN1 NETX_DPMAS_REG(0x634) | ||
| 358 | #define NETX_DPMAS_DATA1 NETX_DPMAS_REG(0x638) | ||
| 359 | |||
| 360 | /* Bits */ | ||
| 361 | #define NETX_DPMAS_INT_EN_GLB_EN (1<<31) | ||
| 362 | #define NETX_DPMAS_INT_EN_MEM_LCK (1<<30) | ||
| 363 | #define NETX_DPMAS_INT_EN_WDG (1<<29) | ||
| 364 | #define NETX_DPMAS_INT_EN_PIO72 (1<<28) | ||
| 365 | #define NETX_DPMAS_INT_EN_PIO47 (1<<27) | ||
| 366 | #define NETX_DPMAS_INT_EN_PIO40 (1<<26) | ||
| 367 | #define NETX_DPMAS_INT_EN_PIO36 (1<<25) | ||
| 368 | #define NETX_DPMAS_INT_EN_PIO35 (1<<24) | ||
| 369 | |||
| 370 | #define NETX_DPMAS_IF_CONF0_HIF_DISABLED (0<<28) | ||
| 371 | #define NETX_DPMAS_IF_CONF0_HIF_EXT_BUS (1<<28) | ||
| 372 | #define NETX_DPMAS_IF_CONF0_HIF_UP_8BIT (2<<28) | ||
| 373 | #define NETX_DPMAS_IF_CONF0_HIF_UP_16BIT (3<<28) | ||
| 374 | #define NETX_DPMAS_IF_CONF0_HIF_IO (4<<28) | ||
| 375 | #define NETX_DPMAS_IF_CONF0_WAIT_DRV_PP (1<<14) | ||
| 376 | #define NETX_DPMAS_IF_CONF0_WAIT_DRV_OD (2<<14) | ||
| 377 | #define NETX_DPMAS_IF_CONF0_WAIT_DRV_TRI (3<<14) | ||
| 378 | |||
| 379 | #define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO35 (1<<26) | ||
| 380 | #define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO36 (1<<27) | ||
| 381 | #define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO40 (1<<28) | ||
| 382 | #define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO47 (1<<29) | ||
| 383 | #define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO72 (1<<30) | ||
| 384 | |||
| 385 | #define NETX_EXT_CONFIG_TALEWIDTH(x) (((x) & 0x7) << 29) | ||
| 386 | #define NETX_EXT_CONFIG_TADRHOLD(x) (((x) & 0x7) << 26) | ||
| 387 | #define NETX_EXT_CONFIG_TCSON(x) (((x) & 0x7) << 23) | ||
| 388 | #define NETX_EXT_CONFIG_TRDON(x) (((x) & 0x7) << 20) | ||
| 389 | #define NETX_EXT_CONFIG_TWRON(x) (((x) & 0x7) << 17) | ||
| 390 | #define NETX_EXT_CONFIG_TWROFF(x) (((x) & 0x1f) << 12) | ||
| 391 | #define NETX_EXT_CONFIG_TRDWRCYC(x) (((x) & 0x1f) << 7) | ||
| 392 | #define NETX_EXT_CONFIG_WAIT_POL (1<<6) | ||
| 393 | #define NETX_EXT_CONFIG_WAIT_EN (1<<5) | ||
| 394 | #define NETX_EXT_CONFIG_NRD_MODE (1<<4) | ||
| 395 | #define NETX_EXT_CONFIG_DS_MODE (1<<3) | ||
| 396 | #define NETX_EXT_CONFIG_NWR_MODE (1<<2) | ||
| 397 | #define NETX_EXT_CONFIG_16BIT (1<<1) | ||
| 398 | #define NETX_EXT_CONFIG_CS_ENABLE (1<<0) | ||
| 399 | |||
| 400 | #define NETX_DPMAS_IO_MODE0_WRL (1<<13) | ||
| 401 | #define NETX_DPMAS_IO_MODE0_WAIT (1<<14) | ||
| 402 | #define NETX_DPMAS_IO_MODE0_READY (1<<15) | ||
| 403 | #define NETX_DPMAS_IO_MODE0_CS0 (1<<19) | ||
| 404 | #define NETX_DPMAS_IO_MODE0_EXTRD (1<<20) | ||
| 405 | |||
| 406 | #define NETX_DPMAS_IO_MODE1_CS2 (1<<15) | ||
| 407 | #define NETX_DPMAS_IO_MODE1_CS1 (1<<16) | ||
| 408 | #define NETX_DPMAS_IO_MODE1_SAMPLE_NPOR (0<<30) | ||
| 409 | #define NETX_DPMAS_IO_MODE1_SAMPLE_100MHZ (1<<30) | ||
| 410 | #define NETX_DPMAS_IO_MODE1_SAMPLE_NPIO36 (2<<30) | ||
| 411 | #define NETX_DPMAS_IO_MODE1_SAMPLE_PIO36 (3<<30) | ||
| 412 | |||
| 413 | /******************************* | ||
| 414 | * I2C * | ||
| 415 | *******************************/ | ||
| 416 | #define NETX_I2C_REG(ofs) IOMEM(NETX_VA_I2C, (ofs)) | ||
| 417 | #define NETX_I2C_CTRL NETX_I2C_REG(0x0) | ||
| 418 | #define NETX_I2C_DATA NETX_I2C_REG(0x4) | ||
| 419 | |||
| 420 | #endif /* __ASM_ARCH_NETX_REGS_H */ | ||
| @@ -1,42 +0,0 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ | ||
| 2 | /* | ||
| 3 | * arch/arm/mach-netx/include/mach/pfifo.h | ||
| 4 | * | ||
| 5 | * Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix | ||
| 6 | */ | ||
| 7 | |||
| 8 | |||
| 9 | #ifndef ASM_ARCH_PFIFO_H | ||
| 10 | #define ASM_ARCH_PFIFO_H | ||
| 11 | |||
| 12 | static inline int pfifo_push(int no, unsigned int pointer) | ||
| 13 | { | ||
| 14 | writel(pointer, NETX_PFIFO_BASE(no)); | ||
| 15 | return 0; | ||
| 16 | } | ||
| 17 | |||
| 18 | static inline unsigned int pfifo_pop(int no) | ||
| 19 | { | ||
| 20 | return readl(NETX_PFIFO_BASE(no)); | ||
| 21 | } | ||
| 22 | |||
| 23 | static inline int pfifo_fill_level(int no) | ||
| 24 | { | ||
| 25 | |||
| 26 | return readl(NETX_PFIFO_FILL_LEVEL(no)); | ||
| 27 | } | ||
| 28 | |||
| 29 | static inline int pfifo_full(int no) | ||
| 30 | { | ||
| 31 | return readl(NETX_PFIFO_FULL) & (1<<no) ? 1 : 0; | ||
| 32 | } | ||
| 33 | |||
| 34 | static inline int pfifo_empty(int no) | ||
| 35 | { | ||
| 36 | return readl(NETX_PFIFO_EMPTY) & (1<<no) ? 1 : 0; | ||
| 37 | } | ||
| 38 | |||
| 39 | int pfifo_request(unsigned int pfifo_mask); | ||
| 40 | void pfifo_free(unsigned int pfifo_mask); | ||
| 41 | |||
| 42 | #endif /* ASM_ARCH_PFIFO_H */ | ||
| @@ -1,63 +0,0 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ | ||
| 2 | /* | ||
| 3 | * arch/arm/mach-netx/include/mach/uncompress.h | ||
| 4 | * | ||
| 5 | * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix | ||
| 6 | */ | ||
| 7 | |||
| 8 | /* | ||
| 9 | * The following code assumes the serial port has already been | ||
| 10 | * initialized by the bootloader. We search for the first enabled | ||
| 11 | * port in the most probable order. If you didn't setup a port in | ||
| 12 | * your bootloader then nothing will appear (which might be desired). | ||
| 13 | * | ||
| 14 | * This does not append a newline | ||
| 15 | */ | ||
| 16 | |||
| 17 | #define REG(x) (*(volatile unsigned long *)(x)) | ||
| 18 | |||
| 19 | #define UART1_BASE 0x100a00 | ||
| 20 | #define UART2_BASE 0x100a80 | ||
| 21 | |||
| 22 | #define UART_DR 0x0 | ||
| 23 | |||
| 24 | #define UART_CR 0x14 | ||
| 25 | #define CR_UART_EN (1<<0) | ||
| 26 | |||
| 27 | #define UART_FR 0x18 | ||
| 28 | #define FR_BUSY (1<<3) | ||
| 29 | #define FR_TXFF (1<<5) | ||
| 30 | |||
| 31 | static inline void putc(char c) | ||
| 32 | { | ||
| 33 | unsigned long base; | ||
| 34 | |||
| 35 | if (REG(UART1_BASE + UART_CR) & CR_UART_EN) | ||
| 36 | base = UART1_BASE; | ||
| 37 | else if (REG(UART2_BASE + UART_CR) & CR_UART_EN) | ||
| 38 | base = UART2_BASE; | ||
| 39 | else | ||
| 40 | return; | ||
| 41 | |||
| 42 | while (REG(base + UART_FR) & FR_TXFF); | ||
| 43 | REG(base + UART_DR) = c; | ||
| 44 | } | ||
| 45 | |||
| 46 | static inline void flush(void) | ||
| 47 | { | ||
| 48 | unsigned long base; | ||
| 49 | |||
| 50 | if (REG(UART1_BASE + UART_CR) & CR_UART_EN) | ||
| 51 | base = UART1_BASE; | ||
| 52 | else if (REG(UART2_BASE + UART_CR) & CR_UART_EN) | ||
| 53 | base = UART2_BASE; | ||
| 54 | else | ||
| 55 | return; | ||
| 56 | |||
| 57 | while (REG(base + UART_FR) & FR_BUSY); | ||
| 58 | } | ||
| 59 | |||
| 60 | /* | ||
| 61 | * nothing to do | ||
| 62 | */ | ||
| 63 | #define arch_decomp_setup() | ||
| @@ -1,30 +0,0 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ | ||
| 2 | /* | ||
| 3 | * arch/arm/mach-netx/include/mach/xc.h | ||
| 4 | * | ||
| 5 | * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix | ||
| 6 | */ | ||
| 7 | |||
| 8 | #ifndef __ASM_ARCH_XC_H | ||
| 9 | #define __ASM_ARCH_XC_H | ||
| 10 | |||
| 11 | struct xc { | ||
| 12 | int no; | ||
| 13 | unsigned int type; | ||
| 14 | unsigned int version; | ||
| 15 | void __iomem *xpec_base; | ||
| 16 | void __iomem *xmac_base; | ||
| 17 | void __iomem *sram_base; | ||
| 18 | int irq; | ||
| 19 | struct device *dev; | ||
| 20 | }; | ||
| 21 | |||
| 22 | int xc_reset(struct xc *x); | ||
| 23 | int xc_stop(struct xc* x); | ||
| 24 | int xc_start(struct xc *x); | ||
| 25 | int xc_running(struct xc *x); | ||
| 26 | int xc_request_firmware(struct xc* x); | ||
| 27 | struct xc* request_xc(int xcno, struct device *dev); | ||
| 28 | void free_xc(struct xc *x); | ||
| 29 | |||
| 30 | #endif /* __ASM_ARCH_XC_H */ | ||
| @@ -1,197 +0,0 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0-only | ||
| 2 | /* | ||
| 3 | * arch/arm/mach-netx/nxdb500.c | ||
| 4 | * | ||
| 5 | * Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix | ||
| 6 | */ | ||
| 7 | |||
| 8 | #include <linux/dma-mapping.h> | ||
| 9 | #include <linux/init.h> | ||
| 10 | #include <linux/interrupt.h> | ||
| 11 | #include <linux/mtd/plat-ram.h> | ||
| 12 | #include <linux/platform_device.h> | ||
| 13 | #include <linux/amba/bus.h> | ||
| 14 | #include <linux/amba/clcd.h> | ||
| 15 | |||
| 16 | #include <mach/hardware.h> | ||
| 17 | #include <asm/mach-types.h> | ||
| 18 | #include <asm/mach/arch.h> | ||
| 19 | #include <mach/netx-regs.h> | ||
| 20 | #include <linux/platform_data/eth-netx.h> | ||
| 21 | |||
| 22 | #include "generic.h" | ||
| 23 | #include "fb.h" | ||
| 24 | |||
| 25 | static struct clcd_panel qvga = { | ||
| 26 | .mode = { | ||
| 27 | .name = "QVGA", | ||
| 28 | .refresh = 60, | ||
| 29 | .xres = 240, | ||
| 30 | .yres = 320, | ||
| 31 | .pixclock = 187617, | ||
| 32 | .left_margin = 6, | ||
| 33 | .right_margin = 26, | ||
| 34 | .upper_margin = 0, | ||
| 35 | .lower_margin = 6, | ||
| 36 | .hsync_len = 6, | ||
| 37 | .vsync_len = 1, | ||
| 38 | .sync = 0, | ||
| 39 | .vmode = FB_VMODE_NONINTERLACED, | ||
| 40 | }, | ||
| 41 | .width = -1, | ||
| 42 | .height = -1, | ||
| 43 | .tim2 = 16, | ||
| 44 | .cntl = CNTL_LCDTFT | CNTL_BGR, | ||
| 45 | .bpp = 16, | ||
| 46 | .grayscale = 0, | ||
| 47 | }; | ||
| 48 | |||
| 49 | static inline int nxdb500_check(struct clcd_fb *fb, struct fb_var_screeninfo *var) | ||
| 50 | { | ||
| 51 | var->green.length = 5; | ||
| 52 | var->green.msb_right = 0; | ||
| 53 | |||
| 54 | return clcdfb_check(fb, var); | ||
| 55 | } | ||
| 56 | |||
| 57 | static int nxdb500_clcd_setup(struct clcd_fb *fb) | ||
| 58 | { | ||
| 59 | unsigned int val; | ||
| 60 | |||
| 61 | fb->fb.var.green.length = 5; | ||
| 62 | fb->fb.var.green.msb_right = 0; | ||
| 63 | |||
| 64 | /* enable asic control */ | ||
| 65 | val = readl(NETX_SYSTEM_IOC_ACCESS_KEY); | ||
| 66 | writel(val, NETX_SYSTEM_IOC_ACCESS_KEY); | ||
| 67 | |||
| 68 | writel(3, NETX_SYSTEM_IOC_CR); | ||
| 69 | |||
| 70 | val = readl(NETX_PIO_OUTPIO); | ||
| 71 | writel(val | 1, NETX_PIO_OUTPIO); | ||
| 72 | |||
| 73 | val = readl(NETX_PIO_OEPIO); | ||
| 74 | writel(val | 1, NETX_PIO_OEPIO); | ||
| 75 | return netx_clcd_setup(fb); | ||
| 76 | } | ||
| 77 | |||
| 78 | static struct clcd_board clcd_data = { | ||
| 79 | .name = "netX", | ||
| 80 | .check = nxdb500_check, | ||
| 81 | .decode = clcdfb_decode, | ||
| 82 | .enable = netx_clcd_enable, | ||
| 83 | .setup = nxdb500_clcd_setup, | ||
| 84 | .mmap = netx_clcd_mmap, | ||
| 85 | .remove = netx_clcd_remove, | ||
| 86 | }; | ||
| 87 | |||
| 88 | static struct netxeth_platform_data eth0_platform_data = { | ||
| 89 | .xcno = 0, | ||
| 90 | }; | ||
| 91 | |||
| 92 | static struct platform_device netx_eth0_device = { | ||
| 93 | .name = "netx-eth", | ||
| 94 | .id = 0, | ||
| 95 | .num_resources = 0, | ||
| 96 | .resource = NULL, | ||
| 97 | .dev = { | ||
| 98 | .platform_data = ð0_platform_data, | ||
| 99 | } | ||
| 100 | }; | ||
| 101 | |||
| 102 | static struct netxeth_platform_data eth1_platform_data = { | ||
| 103 | .xcno = 1, | ||
| 104 | }; | ||
| 105 | |||
| 106 | static struct platform_device netx_eth1_device = { | ||
| 107 | .name = "netx-eth", | ||
| 108 | .id = 1, | ||
| 109 | .num_resources = 0, | ||
| 110 | .resource = NULL, | ||
| 111 | .dev = { | ||
| 112 | .platform_data = ð1_platform_data, | ||
| 113 | } | ||
| 114 | }; | ||
| 115 | |||
| 116 | static struct resource netx_uart0_resources[] = { | ||
| 117 | [0] = { | ||
| 118 | .start = 0x00100A00, | ||
| 119 | .end = 0x00100A3F, | ||
| 120 | .flags = IORESOURCE_MEM, | ||
| 121 | }, | ||
| 122 | [1] = { | ||
| 123 | .start = (NETX_IRQ_UART0), | ||
| 124 | .end = (NETX_IRQ_UART0), | ||
| 125 | .flags = IORESOURCE_IRQ, | ||
| 126 | }, | ||
| 127 | }; | ||
| 128 | |||
| 129 | static struct platform_device netx_uart0_device = { | ||
| 130 | .name = "netx-uart", | ||
| 131 | .id = 0, | ||
| 132 | .num_resources = ARRAY_SIZE(netx_uart0_resources), | ||
| 133 | .resource = netx_uart0_resources, | ||
| 134 | }; | ||
| 135 | |||
| 136 | static struct resource netx_uart1_resources[] = { | ||
| 137 | [0] = { | ||
| 138 | .start = 0x00100A40, | ||
| 139 | .end = 0x00100A7F, | ||
| 140 | .flags = IORESOURCE_MEM, | ||
| 141 | }, | ||
| 142 | [1] = { | ||
| 143 | .start = (NETX_IRQ_UART1), | ||
| 144 | .end = (NETX_IRQ_UART1), | ||
| 145 | .flags = IORESOURCE_IRQ, | ||
| 146 | }, | ||
| 147 | }; | ||
| 148 | |||
| 149 | static struct platform_device netx_uart1_device = { | ||
| 150 | .name = "netx-uart", | ||
| 151 | .id = 1, | ||
| 152 | .num_resources = ARRAY_SIZE(netx_uart1_resources), | ||
| 153 | .resource = netx_uart1_resources, | ||
| 154 | }; | ||
| 155 | |||
| 156 | static struct resource netx_uart2_resources[] = { | ||
| 157 | [0] = { | ||
| 158 | .start = 0x00100A80, | ||
| 159 | .end = 0x00100ABF, | ||
| 160 | .flags = IORESOURCE_MEM, | ||
| 161 | }, | ||
| 162 | [1] = { | ||
| 163 | .start = (NETX_IRQ_UART2), | ||
| 164 | .end = (NETX_IRQ_UART2), | ||
| 165 | .flags = IORESOURCE_IRQ, | ||
| 166 | }, | ||
| 167 | }; | ||
| 168 | |||
| 169 | static struct platform_device netx_uart2_device = { | ||
| 170 | .name = "netx-uart", | ||
| 171 | .id = 2, | ||
| 172 | .num_resources = ARRAY_SIZE(netx_uart2_resources), | ||
| 173 | .resource = netx_uart2_resources, | ||
| 174 | }; | ||
| 175 | |||
| 176 | static struct platform_device *devices[] __initdata = { | ||
| 177 | &netx_eth0_device, | ||
| 178 | &netx_eth1_device, | ||
| 179 | &netx_uart0_device, | ||
| 180 | &netx_uart1_device, | ||
| 181 | &netx_uart2_device, | ||
| 182 | }; | ||
| 183 | |||
| 184 | static void __init nxdb500_init(void) | ||
| 185 | { | ||
| 186 | netx_fb_init(&clcd_data, &qvga); | ||
| 187 | platform_add_devices(devices, ARRAY_SIZE(devices)); | ||
| 188 | } | ||
| 189 | |||
| 190 | MACHINE_START(NXDB500, "Hilscher nxdb500") | ||
| 191 | .atag_offset = 0x100, | ||
| 192 | .map_io = netx_map_io, | ||
| 193 | .init_irq = netx_init_irq, | ||
| 194 | .init_time = netx_timer_init, | ||
| 195 | .init_machine = nxdb500_init, | ||
| 196 | .restart = netx_restart, | ||
| 197 | MACHINE_END | ||
| @@ -1,90 +0,0 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0-only | ||
| 2 | /* | ||
| 3 | * arch/arm/mach-netx/nxdkn.c | ||
| 4 | * | ||
| 5 | * Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix | ||
| 6 | */ | ||
| 7 | |||
| 8 | #include <linux/dma-mapping.h> | ||
| 9 | #include <linux/init.h> | ||
| 10 | #include <linux/interrupt.h> | ||
| 11 | #include <linux/mtd/plat-ram.h> | ||
| 12 | #include <linux/platform_device.h> | ||
| 13 | #include <linux/amba/bus.h> | ||
| 14 | #include <linux/amba/clcd.h> | ||
| 15 | |||
| 16 | #include <mach/hardware.h> | ||
| 17 | #include <asm/mach-types.h> | ||
| 18 | #include <asm/mach/arch.h> | ||
| 19 | #include <mach/netx-regs.h> | ||
| 20 | #include <linux/platform_data/eth-netx.h> | ||
| 21 | |||
| 22 | #include "generic.h" | ||
| 23 | |||
| 24 | static struct netxeth_platform_data eth0_platform_data = { | ||
| 25 | .xcno = 0, | ||
| 26 | }; | ||
| 27 | |||
| 28 | static struct platform_device nxdkn_eth0_device = { | ||
| 29 | .name = "netx-eth", | ||
| 30 | .id = 0, | ||
| 31 | .num_resources = 0, | ||
| 32 | .resource = NULL, | ||
| 33 | .dev = { | ||
| 34 | .platform_data = ð0_platform_data, | ||
| 35 | } | ||
| 36 | }; | ||
| 37 | |||
| 38 | static struct netxeth_platform_data eth1_platform_data = { | ||
| 39 | .xcno = 1, | ||
| 40 | }; | ||
| 41 | |||
| 42 | static struct platform_device nxdkn_eth1_device = { | ||
| 43 | .name = "netx-eth", | ||
| 44 | .id = 1, | ||
| 45 | .num_resources = 0, | ||
| 46 | .resource = NULL, | ||
| 47 | .dev = { | ||
| 48 | .platform_data = ð1_platform_data, | ||
| 49 | } | ||
| 50 | }; | ||
| 51 | |||
| 52 | static struct resource netx_uart0_resources[] = { | ||
| 53 | [0] = { | ||
| 54 | .start = 0x00100A00, | ||
| 55 | .end = 0x00100A3F, | ||
| 56 | .flags = IORESOURCE_MEM, | ||
| 57 | }, | ||
| 58 | [1] = { | ||
| 59 | .start = (NETX_IRQ_UART0), | ||
| 60 | .end = (NETX_IRQ_UART0), | ||
| 61 | .flags = IORESOURCE_IRQ, | ||
| 62 | }, | ||
| 63 | }; | ||
| 64 | |||
| 65 | static struct platform_device netx_uart0_device = { | ||
| 66 | .name = "netx-uart", | ||
| 67 | .id = 0, | ||
| 68 | .num_resources = ARRAY_SIZE(netx_uart0_resources), | ||
| 69 | .resource = netx_uart0_resources, | ||
| 70 | }; | ||
| 71 | |||
| 72 | static struct platform_device *devices[] __initdata = { | ||
| 73 | &nxdkn_eth0_device, | ||
| 74 | &nxdkn_eth1_device, | ||
| 75 | &netx_uart0_device, | ||
| 76 | }; | ||
| 77 | |||
| 78 | static void __init nxdkn_init(void) | ||
| 79 | { | ||
| 80 | platform_add_devices(devices, ARRAY_SIZE(devices)); | ||
| 81 | } | ||
| 82 | |||
| 83 | MACHINE_START(NXDKN, "Hilscher nxdkn") | ||
| 84 | .atag_offset = 0x100, | ||
| 85 | .map_io = netx_map_io, | ||
| 86 | .init_irq = netx_init_irq, | ||
| 87 | .init_time = netx_timer_init, | ||
| 88 | .init_machine = nxdkn_init, | ||
| 89 | .restart = netx_restart, | ||
| 90 | MACHINE_END | ||
| @@ -1,174 +0,0 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0-only | ||
| 2 | /* | ||
| 3 | * arch/arm/mach-netx/nxeb500hmi.c | ||
| 4 | * | ||
| 5 | * Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix | ||
| 6 | */ | ||
| 7 | |||
| 8 | #include <linux/dma-mapping.h> | ||
| 9 | #include <linux/init.h> | ||
| 10 | #include <linux/interrupt.h> | ||
| 11 | #include <linux/mtd/plat-ram.h> | ||
| 12 | #include <linux/platform_device.h> | ||
| 13 | #include <linux/amba/bus.h> | ||
| 14 | #include <linux/amba/clcd.h> | ||
| 15 | |||
| 16 | #include <mach/hardware.h> | ||
| 17 | #include <asm/mach-types.h> | ||
| 18 | #include <asm/mach/arch.h> | ||
| 19 | #include <mach/netx-regs.h> | ||
| 20 | #include <linux/platform_data/eth-netx.h> | ||
| 21 | |||
| 22 | #include "generic.h" | ||
| 23 | #include "fb.h" | ||
| 24 | |||
| 25 | static struct clcd_panel qvga = { | ||
| 26 | .mode = { | ||
| 27 | .name = "QVGA", | ||
| 28 | .refresh = 60, | ||
| 29 | .xres = 240, | ||
| 30 | .yres = 320, | ||
| 31 | .pixclock = 187617, | ||
| 32 | .left_margin = 6, | ||
| 33 | .right_margin = 26, | ||
| 34 | .upper_margin = 0, | ||
| 35 | .lower_margin = 6, | ||
| 36 | .hsync_len = 6, | ||
| 37 | .vsync_len = 1, | ||
| 38 | .sync = 0, | ||
| 39 | .vmode = FB_VMODE_NONINTERLACED, | ||
| 40 | }, | ||
| 41 | .width = -1, | ||
| 42 | .height = -1, | ||
| 43 | .tim2 = 16, | ||
| 44 | .cntl = CNTL_LCDTFT | CNTL_BGR, | ||
| 45 | .bpp = 16, | ||
| 46 | .grayscale = 0, | ||
| 47 | }; | ||
| 48 | |||
| 49 | static inline int nxeb500hmi_check(struct clcd_fb *fb, struct fb_var_screeninfo *var) | ||
| 50 | { | ||
| 51 | var->green.length = 5; | ||
| 52 | var->green.msb_right = 0; | ||
| 53 | |||
| 54 | return clcdfb_check(fb, var); | ||
| 55 | } | ||
| 56 | |||
| 57 | static int nxeb500hmi_clcd_setup(struct clcd_fb *fb) | ||
| 58 | { | ||
| 59 | unsigned int val; | ||
| 60 | |||
| 61 | fb->fb.var.green.length = 5; | ||
| 62 | fb->fb.var.green.msb_right = 0; | ||
| 63 | |||
| 64 | /* enable asic control */ | ||
| 65 | val = readl(NETX_SYSTEM_IOC_ACCESS_KEY); | ||
| 66 | writel(val, NETX_SYSTEM_IOC_ACCESS_KEY); | ||
| 67 | |||
| 68 | writel(3, NETX_SYSTEM_IOC_CR); | ||
| 69 | |||
| 70 | /* GPIO 14 is used for display enable on newer boards */ | ||
| 71 | writel(9, NETX_GPIO_CFG(14)); | ||
| 72 | |||
| 73 | val = readl(NETX_PIO_OUTPIO); | ||
| 74 | writel(val | 1, NETX_PIO_OUTPIO); | ||
| 75 | |||
| 76 | val = readl(NETX_PIO_OEPIO); | ||
| 77 | writel(val | 1, NETX_PIO_OEPIO); | ||
| 78 | return netx_clcd_setup(fb); | ||
| 79 | } | ||
| 80 | |||
| 81 | static struct clcd_board clcd_data = { | ||
| 82 | .name = "netX", | ||
| 83 | .check = nxeb500hmi_check, | ||
| 84 | .decode = clcdfb_decode, | ||
| 85 | .enable = netx_clcd_enable, | ||
| 86 | .setup = nxeb500hmi_clcd_setup, | ||
| 87 | .mmap = netx_clcd_mmap, | ||
| 88 | .remove = netx_clcd_remove, | ||
| 89 | }; | ||
| 90 | |||
| 91 | static struct netxeth_platform_data eth0_platform_data = { | ||
| 92 | .xcno = 0, | ||
| 93 | }; | ||
| 94 | |||
| 95 | static struct platform_device netx_eth0_device = { | ||
| 96 | .name = "netx-eth", | ||
| 97 | .id = 0, | ||
| 98 | .num_resources = 0, | ||
| 99 | .resource = NULL, | ||
| 100 | .dev = { | ||
| 101 | .platform_data = ð0_platform_data, | ||
| 102 | } | ||
| 103 | }; | ||
| 104 | |||
| 105 | static struct netxeth_platform_data eth1_platform_data = { | ||
| 106 | .xcno = 1, | ||
| 107 | }; | ||
| 108 | |||
| 109 | static struct platform_device netx_eth1_device = { | ||
| 110 | .name = "netx-eth", | ||
| 111 | .id = 1, | ||
| 112 | .num_resources = 0, | ||
| 113 | .resource = NULL, | ||
| 114 | .dev = { | ||
| 115 | .platform_data = ð1_platform_data, | ||
| 116 | } | ||
| 117 | }; | ||
| 118 | |||
| 119 | static struct resource netx_cf_resources[] = { | ||
| 120 | [0] = { | ||
| 121 | .start = 0x20000000, | ||
| 122 | .end = 0x25ffffff, | ||
| 123 | .flags = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT, | ||
| 124 | }, | ||
| 125 | }; | ||
| 126 | |||
| 127 | static struct platform_device netx_cf_device = { | ||
| 128 | .name = "netx-cf", | ||
| 129 | .id = 0, | ||
| 130 | .resource = netx_cf_resources, | ||
| 131 | .num_resources = ARRAY_SIZE(netx_cf_resources), | ||
| 132 | }; | ||
| 133 | |||
| 134 | static struct resource netx_uart0_resources[] = { | ||
| 135 | [0] = { | ||
| 136 | .start = 0x00100A00, | ||
| 137 | .end = 0x00100A3F, | ||
| 138 | .flags = IORESOURCE_MEM, | ||
| 139 | }, | ||
| 140 | [1] = { | ||
| 141 | .start = (NETX_IRQ_UART0), | ||
| 142 | .end = (NETX_IRQ_UART0), | ||
| 143 | .flags = IORESOURCE_IRQ, | ||
| 144 | }, | ||
| 145 | }; | ||
| 146 | |||
| 147 | static struct platform_device netx_uart0_device = { | ||
| 148 | .name = "netx-uart", | ||
| 149 | .id = 0, | ||
| 150 | .num_resources = ARRAY_SIZE(netx_uart0_resources), | ||
| 151 | .resource = netx_uart0_resources, | ||
| 152 | }; | ||
| 153 | |||
| 154 | static struct platform_device *devices[] __initdata = { | ||
| 155 | &netx_eth0_device, | ||
| 156 | &netx_eth1_device, | ||
| 157 | &netx_cf_device, | ||
| 158 | &netx_uart0_device, | ||
| 159 | }; | ||
| 160 | |||
| 161 | static void __init nxeb500hmi_init(void) | ||
| 162 | { | ||
| 163 | netx_fb_init(&clcd_data, &qvga); | ||
| 164 | platform_add_devices(devices, ARRAY_SIZE(devices)); | ||
| 165 | } | ||
| 166 | |||
| 167 | MACHINE_START(NXEB500HMI, "Hilscher nxeb500hmi") | ||
| 168 | .atag_offset = 0x100, | ||
| 169 | .map_io = netx_map_io, | ||
| 170 | .init_irq = netx_init_irq, | ||
| 171 | .init_time = netx_timer_init, | ||
| 172 | .init_machine = nxeb500hmi_init, | ||
| 173 | .restart = netx_restart, | ||
| 174 | MACHINE_END | ||
| @@ -1,56 +0,0 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0-only | ||
| 2 | /* | ||
| 3 | * arch/arm/mach-netx/pfifo.c | ||
| 4 | * | ||
| 5 | * Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix | ||
| 6 | */ | ||
| 7 | |||
| 8 | #include <linux/init.h> | ||
| 9 | #include <linux/module.h> | ||
| 10 | #include <linux/mutex.h> | ||
| 11 | #include <linux/io.h> | ||
| 12 | |||
| 13 | #include <mach/hardware.h> | ||
| 14 | #include <mach/netx-regs.h> | ||
| 15 | #include <mach/pfifo.h> | ||
| 16 | |||
| 17 | static DEFINE_MUTEX(pfifo_lock); | ||
| 18 | |||
| 19 | static unsigned int pfifo_used = 0; | ||
| 20 | |||
| 21 | int pfifo_request(unsigned int pfifo_mask) | ||
| 22 | { | ||
| 23 | int err = 0; | ||
| 24 | unsigned int val; | ||
| 25 | |||
| 26 | mutex_lock(&pfifo_lock); | ||
| 27 | |||
| 28 | if (pfifo_mask & pfifo_used) { | ||
| 29 | err = -EBUSY; | ||
| 30 | goto out; | ||
| 31 | } | ||
| 32 | |||
| 33 | pfifo_used |= pfifo_mask; | ||
| 34 | |||
| 35 | val = readl(NETX_PFIFO_RESET); | ||
| 36 | writel(val | pfifo_mask, NETX_PFIFO_RESET); | ||
| 37 | writel(val, NETX_PFIFO_RESET); | ||
| 38 | |||
| 39 | out: | ||
| 40 | mutex_unlock(&pfifo_lock); | ||
| 41 | return err; | ||
| 42 | } | ||
| 43 | |||
| 44 | void pfifo_free(unsigned int pfifo_mask) | ||
| 45 | { | ||
| 46 | mutex_lock(&pfifo_lock); | ||
| 47 | pfifo_used &= ~pfifo_mask; | ||
| 48 | mutex_unlock(&pfifo_lock); | ||
| 49 | } | ||
| 50 | |||
| 51 | EXPORT_SYMBOL(pfifo_push); | ||
| 52 | EXPORT_SYMBOL(pfifo_pop); | ||
| 53 | EXPORT_SYMBOL(pfifo_fill_level); | ||
| 54 | EXPORT_SYMBOL(pfifo_empty); | ||
| 55 | EXPORT_SYMBOL(pfifo_request); | ||
| 56 | EXPORT_SYMBOL(pfifo_free); | ||
| @@ -1,141 +0,0 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0-only | ||
| 2 | /* | ||
| 3 | * arch/arm/mach-netx/time.c | ||
| 4 | * | ||
| 5 | * Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix | ||
| 6 | */ | ||
| 7 | |||
| 8 | #include <linux/init.h> | ||
| 9 | #include <linux/interrupt.h> | ||
| 10 | #include <linux/irq.h> | ||
| 11 | #include <linux/clocksource.h> | ||
| 12 | #include <linux/clockchips.h> | ||
| 13 | #include <linux/io.h> | ||
| 14 | |||
| 15 | #include <mach/hardware.h> | ||
| 16 | #include <asm/mach/time.h> | ||
| 17 | #include <mach/netx-regs.h> | ||
| 18 | |||
| 19 | #define NETX_CLOCK_FREQ 100000000 | ||
| 20 | #define NETX_LATCH DIV_ROUND_CLOSEST(NETX_CLOCK_FREQ, HZ) | ||
| 21 | |||
| 22 | #define TIMER_CLOCKEVENT 0 | ||
| 23 | #define TIMER_CLOCKSOURCE 1 | ||
| 24 | |||
| 25 | static inline void timer_shutdown(struct clock_event_device *evt) | ||
| 26 | { | ||
| 27 | /* disable timer */ | ||
| 28 | writel(0, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKEVENT)); | ||
| 29 | } | ||
| 30 | |||
| 31 | static int netx_shutdown(struct clock_event_device *evt) | ||
| 32 | { | ||
| 33 | timer_shutdown(evt); | ||
| 34 | |||
| 35 | return 0; | ||
| 36 | } | ||
| 37 | |||
| 38 | static int netx_set_oneshot(struct clock_event_device *evt) | ||
| 39 | { | ||
| 40 | u32 tmode = NETX_GPIO_COUNTER_CTRL_IRQ_EN | NETX_GPIO_COUNTER_CTRL_RUN; | ||
| 41 | |||
| 42 | timer_shutdown(evt); | ||
| 43 | writel(0, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKEVENT)); | ||
| 44 | writel(tmode, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKEVENT)); | ||
| 45 | |||
| 46 | return 0; | ||
| 47 | } | ||
| 48 | |||
| 49 | static int netx_set_periodic(struct clock_event_device *evt) | ||
| 50 | { | ||
| 51 | u32 tmode = NETX_GPIO_COUNTER_CTRL_RST_EN | | ||
| 52 | NETX_GPIO_COUNTER_CTRL_IRQ_EN | NETX_GPIO_COUNTER_CTRL_RUN; | ||
| 53 | |||
| 54 | timer_shutdown(evt); | ||
| 55 | writel(NETX_LATCH, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKEVENT)); | ||
| 56 | writel(tmode, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKEVENT)); | ||
| 57 | |||
| 58 | return 0; | ||
| 59 | } | ||
| 60 | |||
| 61 | static int netx_set_next_event(unsigned long evt, | ||
| 62 | struct clock_event_device *clk) | ||
| 63 | { | ||
| 64 | writel(0 - evt, NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKEVENT)); | ||
| 65 | return 0; | ||
| 66 | } | ||
| 67 | |||
| 68 | static struct clock_event_device netx_clockevent = { | ||
| 69 | .name = "netx-timer" __stringify(TIMER_CLOCKEVENT), | ||
| 70 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | ||
| 71 | .set_next_event = netx_set_next_event, | ||
| 72 | .set_state_shutdown = netx_shutdown, | ||
| 73 | .set_state_periodic = netx_set_periodic, | ||
| 74 | .set_state_oneshot = netx_set_oneshot, | ||
| 75 | .tick_resume = netx_shutdown, | ||
| 76 | }; | ||
| 77 | |||
| 78 | /* | ||
| 79 | * IRQ handler for the timer | ||
| 80 | */ | ||
| 81 | static irqreturn_t | ||
| 82 | netx_timer_interrupt(int irq, void *dev_id) | ||
| 83 | { | ||
| 84 | struct clock_event_device *evt = &netx_clockevent; | ||
| 85 | |||
| 86 | /* acknowledge interrupt */ | ||
| 87 | writel(COUNTER_BIT(0), NETX_GPIO_IRQ); | ||
| 88 | |||
| 89 | evt->event_handler(evt); | ||
| 90 | |||
| 91 | return IRQ_HANDLED; | ||
| 92 | } | ||
| 93 | |||
| 94 | static struct irqaction netx_timer_irq = { | ||
| 95 | .name = "NetX Timer Tick", | ||
| 96 | .flags = IRQF_TIMER | IRQF_IRQPOLL, | ||
| 97 | .handler = netx_timer_interrupt, | ||
| 98 | }; | ||
| 99 | |||
| 100 | /* | ||
| 101 | * Set up timer interrupt | ||
| 102 | */ | ||
| 103 | void __init netx_timer_init(void) | ||
| 104 | { | ||
| 105 | /* disable timer initially */ | ||
| 106 | writel(0, NETX_GPIO_COUNTER_CTRL(0)); | ||
| 107 | |||
| 108 | /* Reset the timer value to zero */ | ||
| 109 | writel(0, NETX_GPIO_COUNTER_CURRENT(0)); | ||
| 110 | |||
| 111 | writel(NETX_LATCH, NETX_GPIO_COUNTER_MAX(0)); | ||
| 112 | |||
| 113 | /* acknowledge interrupt */ | ||
| 114 | writel(COUNTER_BIT(0), NETX_GPIO_IRQ); | ||
| 115 | |||
| 116 | /* Enable the interrupt in the specific timer | ||
| 117 | * register and start timer | ||
| 118 | */ | ||
| 119 | writel(COUNTER_BIT(0), NETX_GPIO_IRQ_ENABLE); | ||
| 120 | writel(NETX_GPIO_COUNTER_CTRL_IRQ_EN | NETX_GPIO_COUNTER_CTRL_RUN, | ||
| 121 | NETX_GPIO_COUNTER_CTRL(0)); | ||
| 122 | |||
| 123 | setup_irq(NETX_IRQ_TIMER0, &netx_timer_irq); | ||
| 124 | |||
| 125 | /* Setup timer one for clocksource */ | ||
| 126 | writel(0, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKSOURCE)); | ||
| 127 | writel(0, NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKSOURCE)); | ||
| 128 | writel(0xffffffff, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKSOURCE)); | ||
| 129 | |||
| 130 | writel(NETX_GPIO_COUNTER_CTRL_RUN, | ||
| 131 | NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKSOURCE)); | ||
| 132 | |||
| 133 | clocksource_mmio_init(NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKSOURCE), | ||
| 134 | "netx_timer", NETX_CLOCK_FREQ, 200, 32, clocksource_mmio_readl_up); | ||
| 135 | |||
| 136 | /* with max_delta_ns >= delta2ns(0x800) the system currently runs fine. | ||
| 137 | * Adding some safety ... */ | ||
| 138 | netx_clockevent.cpumask = cpumask_of(0); | ||
| 139 | clockevents_config_and_register(&netx_clockevent, NETX_CLOCK_FREQ, | ||
| 140 | 0xa00, 0xfffffffe); | ||
| 141 | } | ||
| @@ -1,246 +0,0 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0-only | ||
| 2 | /* | ||
| 3 | * arch/arm/mach-netx/xc.c | ||
| 4 | * | ||
| 5 | * Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix | ||
| 6 | */ | ||
| 7 | |||
| 8 | #include <linux/init.h> | ||
| 9 | #include <linux/device.h> | ||
| 10 | #include <linux/firmware.h> | ||
| 11 | #include <linux/mutex.h> | ||
| 12 | #include <linux/slab.h> | ||
| 13 | #include <linux/io.h> | ||
| 14 | #include <linux/export.h> | ||
| 15 | |||
| 16 | #include <mach/hardware.h> | ||
| 17 | #include <mach/irqs.h> | ||
| 18 | #include <mach/netx-regs.h> | ||
| 19 | |||
| 20 | #include <mach/xc.h> | ||
| 21 | |||
| 22 | static DEFINE_MUTEX(xc_lock); | ||
| 23 | |||
| 24 | static int xc_in_use = 0; | ||
| 25 | |||
| 26 | struct fw_desc { | ||
| 27 | unsigned int ofs; | ||
| 28 | unsigned int size; | ||
| 29 | unsigned int patch_ofs; | ||
| 30 | unsigned int patch_entries; | ||
| 31 | }; | ||
| 32 | |||
| 33 | struct fw_header { | ||
| 34 | unsigned int magic; | ||
| 35 | unsigned int type; | ||
| 36 | unsigned int version; | ||
| 37 | unsigned int reserved[5]; | ||
| 38 | struct fw_desc fw_desc[3]; | ||
| 39 | } __attribute__ ((packed)); | ||
| 40 | |||
| 41 | int xc_stop(struct xc *x) | ||
| 42 | { | ||
| 43 | writel(RPU_HOLD_PC, x->xmac_base + NETX_XMAC_RPU_HOLD_PC_OFS); | ||
| 44 | writel(TPU_HOLD_PC, x->xmac_base + NETX_XMAC_TPU_HOLD_PC_OFS); | ||
| 45 | writel(XPU_HOLD_PC, x->xpec_base + NETX_XPEC_XPU_HOLD_PC_OFS); | ||
| 46 | return 0; | ||
| 47 | } | ||
| 48 | |||
| 49 | int xc_start(struct xc *x) | ||
| 50 | { | ||
| 51 | writel(0, x->xmac_base + NETX_XMAC_RPU_HOLD_PC_OFS); | ||
| 52 | writel(0, x->xmac_base + NETX_XMAC_TPU_HOLD_PC_OFS); | ||
| 53 | writel(0, x->xpec_base + NETX_XPEC_XPU_HOLD_PC_OFS); | ||
| 54 | return 0; | ||
| 55 | } | ||
| 56 | |||
| 57 | int xc_running(struct xc *x) | ||
| 58 | { | ||
| 59 | return (readl(x->xmac_base + NETX_XMAC_RPU_HOLD_PC_OFS) & RPU_HOLD_PC) | ||
| 60 | || (readl(x->xmac_base + NETX_XMAC_TPU_HOLD_PC_OFS) & TPU_HOLD_PC) | ||
| 61 | || (readl(x->xpec_base + NETX_XPEC_XPU_HOLD_PC_OFS) & XPU_HOLD_PC) ? | ||
| 62 | 0 : 1; | ||
| 63 | } | ||
| 64 | |||
| 65 | int xc_reset(struct xc *x) | ||
| 66 | { | ||
| 67 | writel(0, x->xpec_base + NETX_XPEC_PC_OFS); | ||
| 68 | return 0; | ||
| 69 | } | ||
| 70 | |||
| 71 | static int xc_check_ptr(struct xc *x, unsigned long adr, unsigned int size) | ||
| 72 | { | ||
| 73 | if (adr >= NETX_PA_XMAC(x->no) && | ||
| 74 | adr + size < NETX_PA_XMAC(x->no) + XMAC_MEM_SIZE) | ||
| 75 | return 0; | ||
| 76 | |||
| 77 | if (adr >= NETX_PA_XPEC(x->no) && | ||
| 78 | adr + size < NETX_PA_XPEC(x->no) + XPEC_MEM_SIZE) | ||
| 79 | return 0; | ||
| 80 | |||
| 81 | dev_err(x->dev, "Illegal pointer in firmware found. aborting\n"); | ||
| 82 | |||
| 83 | return -1; | ||
| 84 | } | ||
| 85 | |||
| 86 | static int xc_patch(struct xc *x, const void *patch, int count) | ||
| 87 | { | ||
| 88 | unsigned int val, adr; | ||
| 89 | const unsigned int *data = patch; | ||
| 90 | |||
| 91 | int i; | ||
| 92 | for (i = 0; i < count; i++) { | ||
| 93 | adr = *data++; | ||
| 94 | val = *data++; | ||
| 95 | if (xc_check_ptr(x, adr, 4) < 0) | ||
| 96 | return -EINVAL; | ||
| 97 | |||
| 98 | writel(val, (void __iomem *)io_p2v(adr)); | ||
| 99 | } | ||
| 100 | return 0; | ||
| 101 | } | ||
| 102 | |||
| 103 | int xc_request_firmware(struct xc *x) | ||
| 104 | { | ||
| 105 | int ret; | ||
| 106 | char name[16]; | ||
| 107 | const struct firmware *fw; | ||
| 108 | struct fw_header *head; | ||
| 109 | unsigned int size; | ||
| 110 | int i; | ||
| 111 | const void *src; | ||
| 112 | unsigned long dst; | ||
| 113 | |||
| 114 | sprintf(name, "xc%d.bin", x->no); | ||
| 115 | |||
| 116 | ret = request_firmware(&fw, name, x->dev); | ||
| 117 | |||
| 118 | if (ret < 0) { | ||
| 119 | dev_err(x->dev, "request_firmware failed\n"); | ||
| 120 | return ret; | ||
| 121 | } | ||
| 122 | |||
| 123 | head = (struct fw_header *)fw->data; | ||
| 124 | if (head->magic != 0x4e657458) { | ||
| 125 | if (head->magic == 0x5874654e) { | ||
| 126 | dev_err(x->dev, | ||
| 127 | "firmware magic is 'XteN'. Endianness problems?\n"); | ||
| 128 | ret = -ENODEV; | ||
| 129 | goto exit_release_firmware; | ||
| 130 | } | ||
| 131 | dev_err(x->dev, "unrecognized firmware magic 0x%08x\n", | ||
| 132 | head->magic); | ||
| 133 | ret = -ENODEV; | ||
| 134 | goto exit_release_firmware; | ||
| 135 | } | ||
| 136 | |||
| 137 | x->type = head->type; | ||
| 138 | x->version = head->version; | ||
| 139 | |||
| 140 | ret = -EINVAL; | ||
| 141 | |||
| 142 | for (i = 0; i < 3; i++) { | ||
| 143 | src = fw->data + head->fw_desc[i].ofs; | ||
| 144 | dst = *(unsigned int *)src; | ||
| 145 | src += sizeof (unsigned int); | ||
| 146 | size = head->fw_desc[i].size - sizeof (unsigned int); | ||
| 147 | |||
| 148 | if (xc_check_ptr(x, dst, size)) | ||
| 149 | goto exit_release_firmware; | ||
| 150 | |||
| 151 | memcpy((void *)io_p2v(dst), src, size); | ||
| 152 | |||
| 153 | src = fw->data + head->fw_desc[i].patch_ofs; | ||
| 154 | size = head->fw_desc[i].patch_entries; | ||
| 155 | ret = xc_patch(x, src, size); | ||
| 156 | if (ret < 0) | ||
| 157 | goto exit_release_firmware; | ||
| 158 | } | ||
| 159 | |||
| 160 | ret = 0; | ||
| 161 | |||
| 162 | exit_release_firmware: | ||
| 163 | release_firmware(fw); | ||
| 164 | |||
| 165 | return ret; | ||
| 166 | } | ||
| 167 | |||
| 168 | struct xc *request_xc(int xcno, struct device *dev) | ||
| 169 | { | ||
| 170 | struct xc *x = NULL; | ||
| 171 | |||
| 172 | mutex_lock(&xc_lock); | ||
| 173 | |||
| 174 | if (xcno > 3) | ||
| 175 | goto exit; | ||
| 176 | if (xc_in_use & (1 << xcno)) | ||
| 177 | goto exit; | ||
| 178 | |||
| 179 | x = kmalloc(sizeof (struct xc), GFP_KERNEL); | ||
| 180 | if (!x) | ||
| 181 | goto exit; | ||
| 182 | |||
| 183 | if (!request_mem_region | ||
| 184 | (NETX_PA_XPEC(xcno), XPEC_MEM_SIZE, kobject_name(&dev->kobj))) | ||
| 185 | goto exit_free; | ||
| 186 | |||
| 187 | if (!request_mem_region | ||
| 188 | (NETX_PA_XMAC(xcno), XMAC_MEM_SIZE, kobject_name(&dev->kobj))) | ||
| 189 | goto exit_release_1; | ||
| 190 | |||
| 191 | if (!request_mem_region | ||
| 192 | (SRAM_INTERNAL_PHYS(xcno), SRAM_MEM_SIZE, kobject_name(&dev->kobj))) | ||
| 193 | goto exit_release_2; | ||
| 194 | |||
| 195 | x->xpec_base = (void * __iomem)io_p2v(NETX_PA_XPEC(xcno)); | ||
| 196 | x->xmac_base = (void * __iomem)io_p2v(NETX_PA_XMAC(xcno)); | ||
| 197 | x->sram_base = ioremap(SRAM_INTERNAL_PHYS(xcno), SRAM_MEM_SIZE); | ||
| 198 | if (!x->sram_base) | ||
| 199 | goto exit_release_3; | ||
| 200 | |||
| 201 | x->irq = NETX_IRQ_XPEC(xcno); | ||
| 202 | |||
| 203 | x->no = xcno; | ||
| 204 | x->dev = dev; | ||
| 205 | |||
| 206 | xc_in_use |= (1 << xcno); | ||
| 207 | |||
| 208 | goto exit; | ||
| 209 | |||
| 210 | exit_release_3: | ||
| 211 | release_mem_region(SRAM_INTERNAL_PHYS(xcno), SRAM_MEM_SIZE); | ||
| 212 | exit_release_2: | ||
| 213 | release_mem_region(NETX_PA_XMAC(xcno), XMAC_MEM_SIZE); | ||
| 214 | exit_release_1: | ||
| 215 | release_mem_region(NETX_PA_XPEC(xcno), XPEC_MEM_SIZE); | ||
| 216 | exit_free: | ||
| 217 | kfree(x); | ||
| 218 | x = NULL; | ||
| 219 | exit: | ||
| 220 | mutex_unlock(&xc_lock); | ||
| 221 | return x; | ||
| 222 | } | ||
| 223 | |||
| 224 | void free_xc(struct xc *x) | ||
| 225 | { | ||
| 226 | int xcno = x->no; | ||
| 227 | |||
| 228 | mutex_lock(&xc_lock); | ||
| 229 | |||
| 230 | iounmap(x->sram_base); | ||
| 231 | release_mem_region(SRAM_INTERNAL_PHYS(xcno), SRAM_MEM_SIZE); | ||
| 232 | release_mem_region(NETX_PA_XMAC(xcno), XMAC_MEM_SIZE); | ||
| 233 | release_mem_region(NETX_PA_XPEC(xcno), XPEC_MEM_SIZE); | ||
| 234 | xc_in_use &= ~(1 << x->no); | ||
| 235 | kfree(x); | ||
| 236 | |||
| 237 | mutex_unlock(&xc_lock); | ||
| 238 | } | ||
| 239 | |||
| 240 | EXPORT_SYMBOL(free_xc); | ||
| 241 | EXPORT_SYMBOL(request_xc); | ||
| 242 | EXPORT_SYMBOL(xc_request_firmware); | ||
| 243 | EXPORT_SYMBOL(xc_reset); | ||
| 244 | EXPORT_SYMBOL(xc_running); | ||
| 245 | EXPORT_SYMBOL(xc_start); | ||
| 246 | EXPORT_SYMBOL(xc_stop); | ||
| @@ -70,7 +70,7 @@ static void __init tegra_cpu_reset_handler_enable(void) · 69 unmodified lines | |||
| 70 | switch (err) { | 70 | switch (err) { |
| 71 | case -ENOSYS: | 71 | case -ENOSYS: |
| 72 | tegra_cpu_reset_handler_set(reset_address); | 72 | tegra_cpu_reset_handler_set(reset_address); |
| 73 | /* pass-through */ | 73 | /* fall through */ |
| 74 | case 0: | 74 | case 0: |
| 75 | is_enabled = true; | 75 | is_enabled = true; |
| 76 | break; | 76 | break; |
| @@ -663,6 +663,11 @@ config ARM_LPAE · 662 unmodified lines | |||
| 663 | depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \ | 663 | depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \ |
| 664 | !CPU_32v4 && !CPU_32v3 | 664 | !CPU_32v4 && !CPU_32v3 |
| 665 | select PHYS_ADDR_T_64BIT | 665 | select PHYS_ADDR_T_64BIT |
| 666 | select SWIOTLB | ||
| 667 | select ARCH_HAS_DMA_COHERENT_TO_PFN | ||
| 668 | select ARCH_HAS_DMA_MMAP_PGPROT | ||
| 669 | select ARCH_HAS_SYNC_DMA_FOR_DEVICE | ||
| 670 | select ARCH_HAS_SYNC_DMA_FOR_CPU | ||
| 666 | help | 671 | help |
| 667 | Say Y if you have an ARMv7 processor supporting the LPAE page | 672 | Say Y if you have an ARMv7 processor supporting the LPAE page |
| 668 | table format and you would like to access memory beyond the | 673 | table format and you would like to access memory beyond the |
| @@ -695,7 +695,7 @@ thumb2arm(u16 tinstr) · 694 unmodified lines | |||
| 695 | return subset[(L<<1) | ((tinstr & (1<<8)) >> 8)] | | 695 | return subset[(L<<1) | ((tinstr & (1<<8)) >> 8)] | |
| 696 | (tinstr & 255); /* register_list */ | 696 | (tinstr & 255); /* register_list */ |
| 697 | } | 697 | } |
| 698 | /* Else fall through for illegal instruction case */ | 698 | /* Else, fall through - for illegal instruction case */ |
| 699 | 699 | ||
| 700 | default: | 700 | default: |
| 701 | return BAD_INSTR; | 701 | return BAD_INSTR; |
| @@ -751,6 +751,8 @@ do_alignment_t32_to_handler(unsigned long *pinstr, struct pt_regs *regs, · 49 unmodified lines | |||
| 751 | case 0xe8e0: | 751 | case 0xe8e0: |
| 752 | case 0xe9e0: | 752 | case 0xe9e0: |
| 753 | poffset->un = (tinst2 & 0xff) << 2; | 753 | poffset->un = (tinst2 & 0xff) << 2; |
| 754 | /* Fall through */ | ||
| 755 | |||
| 754 | case 0xe940: | 756 | case 0xe940: |
| 755 | case 0xe9c0: | 757 | case 0xe9c0: |
| 756 | return do_alignment_ldrdstrd; | 758 | return do_alignment_ldrdstrd; |
| @@ -15,6 +15,7 @@ · 14 unmodified lines | |||
| 15 | #include <linux/init.h> | 15 | #include <linux/init.h> |
| 16 | #include <linux/device.h> | 16 | #include <linux/device.h> |
| 17 | #include <linux/dma-mapping.h> | 17 | #include <linux/dma-mapping.h> |
| 18 | #include <linux/dma-noncoherent.h> | ||
| 18 | #include <linux/dma-contiguous.h> | 19 | #include <linux/dma-contiguous.h> |
| 19 | #include <linux/highmem.h> | 20 | #include <linux/highmem.h> |
| 20 | #include <linux/memblock.h> | 21 | #include <linux/memblock.h> |
| @@ -1125,6 +1126,19 @@ int arm_dma_supported(struct device *dev, u64 mask) · 1104 unmodified lines | |||
| 1125 | 1126 | ||
| 1126 | static const struct dma_map_ops *arm_get_dma_map_ops(bool coherent) | 1127 | static const struct dma_map_ops *arm_get_dma_map_ops(bool coherent) |
| 1127 | { | 1128 | { |
| 1129 | /* | ||
| 1130 | * When CONFIG_ARM_LPAE is set, physical address can extend above | ||
| 1131 | * 32-bits, which then can't be addressed by devices that only support | ||
| 1132 | * 32-bit DMA. | ||
| 1133 | * Use the generic dma-direct / swiotlb ops code in that case, as that | ||
| 1134 | * handles bounce buffering for us. | ||
| 1135 | * | ||
| 1136 | * Note: this checks CONFIG_ARM_LPAE instead of CONFIG_SWIOTLB as the | ||
| 1137 | * latter is also selected by the Xen code, but that code for now relies | ||
| 1138 | * on non-NULL dev_dma_ops. To be cleaned up later. | ||
| 1139 | */ | ||
| 1140 | if (IS_ENABLED(CONFIG_ARM_LPAE)) | ||
| 1141 | return NULL; | ||
| 1128 | return coherent ? &arm_coherent_dma_ops : &arm_dma_ops; | 1142 | return coherent ? &arm_coherent_dma_ops : &arm_dma_ops; |
| 1129 | } | 1143 | } |
| 1130 | 1144 | ||
| @@ -2329,6 +2343,9 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, · 1198 unmodified lines | |||
| 2329 | const struct dma_map_ops *dma_ops; | 2343 | const struct dma_map_ops *dma_ops; |
| 2330 | 2344 | ||
| 2331 | dev->archdata.dma_coherent = coherent; | 2345 | dev->archdata.dma_coherent = coherent; |
| 2346 | #ifdef CONFIG_SWIOTLB | ||
| 2347 | dev->dma_coherent = coherent; | ||
| 2348 | #endif | ||
| 2332 | 2349 | ||
| 2333 | /* | 2350 | /* |
| 2334 | * Don't override the dma_ops if they have already been set. Ideally | 2351 | * Don't override the dma_ops if they have already been set. Ideally |
| @@ -2363,3 +2380,45 @@ void arch_teardown_dma_ops(struct device *dev) · 28 unmodified lines | |||
| 2363 | /* Let arch_setup_dma_ops() start again from scratch upon re-probe */ | 2380 | /* Let arch_setup_dma_ops() start again from scratch upon re-probe */ |
| 2364 | set_dma_ops(dev, NULL); | 2381 | set_dma_ops(dev, NULL); |
| 2365 | } | 2382 | } |
| 2383 | |||
| 2384 | #ifdef CONFIG_SWIOTLB | ||
| 2385 | void arch_sync_dma_for_device(struct device *dev, phys_addr_t paddr, | ||
| 2386 | size_t size, enum dma_data_direction dir) | ||
| 2387 | { | ||
| 2388 | __dma_page_cpu_to_dev(phys_to_page(paddr), paddr & (PAGE_SIZE - 1), | ||
| 2389 | size, dir); | ||
| 2390 | } | ||
| 2391 | |||
| 2392 | void arch_sync_dma_for_cpu(struct device *dev, phys_addr_t paddr, | ||
| 2393 | size_t size, enum dma_data_direction dir) | ||
| 2394 | { | ||
| 2395 | __dma_page_dev_to_cpu(phys_to_page(paddr), paddr & (PAGE_SIZE - 1), | ||
| 2396 | size, dir); | ||
| 2397 | } | ||
| 2398 | |||
| 2399 | long arch_dma_coherent_to_pfn(struct device *dev, void *cpu_addr, | ||
| 2400 | dma_addr_t dma_addr) | ||
| 2401 | { | ||
| 2402 | return dma_to_pfn(dev, dma_addr); | ||
| 2403 | } | ||
| 2404 | |||
| 2405 | pgprot_t arch_dma_mmap_pgprot(struct device *dev, pgprot_t prot, | ||
| 2406 | unsigned long attrs) | ||
| 2407 | { | ||
| 2408 | return __get_dma_pgprot(attrs, prot); | ||
| 2409 | } | ||
| 2410 | |||
| 2411 | void *arch_dma_alloc(struct device *dev, size_t size, dma_addr_t *dma_handle, | ||
| 2412 | gfp_t gfp, unsigned long attrs) | ||
| 2413 | { | ||
| 2414 | return __dma_alloc(dev, size, dma_handle, gfp, | ||
| 2415 | __get_dma_pgprot(attrs, PAGE_KERNEL), false, | ||
| 2416 | attrs, __builtin_return_address(0)); | ||
| 2417 | } | ||
| 2418 | |||
| 2419 | void arch_dma_free(struct device *dev, size_t size, void *cpu_addr, | ||
| 2420 | dma_addr_t dma_handle, unsigned long attrs) | ||
| 2421 | { | ||
| 2422 | __arm_dma_free(dev, size, cpu_addr, dma_handle, attrs, false); | ||
| 2423 | } | ||
| 2424 | #endif /* CONFIG_SWIOTLB */ | ||
| @@ -21,6 +21,7 @@ · 20 unmodified lines | |||
| 21 | #include <linux/dma-contiguous.h> | 21 | #include <linux/dma-contiguous.h> |
| 22 | #include <linux/sizes.h> | 22 | #include <linux/sizes.h> |
| 23 | #include <linux/stop_machine.h> | 23 | #include <linux/stop_machine.h> |
| 24 | #include <linux/swiotlb.h> | ||
| 24 | 25 | ||
| 25 | #include <asm/cp15.h> | 26 | #include <asm/cp15.h> |
| 26 | #include <asm/mach-types.h> | 27 | #include <asm/mach-types.h> |
| @@ -463,6 +464,10 @@ static void __init free_highpages(void) · 436 unmodified lines | |||
| 463 | */ | 464 | */ |
| 464 | void __init mem_init(void) | 465 | void __init mem_init(void) |
| 465 | { | 466 | { |
| 467 | #ifdef CONFIG_ARM_LPAE | ||
| 468 | swiotlb_init(1); | ||
| 469 | #endif | ||
| 470 | |||
| 466 | set_max_mapnr(pfn_to_page(max_pfn) - mem_map); | 471 | set_max_mapnr(pfn_to_page(max_pfn) - mem_map); |
| 467 | 472 | ||
| 468 | /* this will put all unused low memory onto the freelists */ | 473 | /* this will put all unused low memory onto the freelists */ |
| @@ -388,17 +388,15 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) · 387 unmodified lines | |||
| 388 | /* | 388 | /* |
| 389 | * not supported by current hardware on OMAP1 | 389 | * not supported by current hardware on OMAP1 |
| 390 | * w |= (0x03 << 7); | 390 | * w |= (0x03 << 7); |
| 391 | * fall through | ||
| 392 | */ | 391 | */ |
| 392 | /* fall through */ | ||
| 393 | case OMAP_DMA_DATA_BURST_16: | 393 | case OMAP_DMA_DATA_BURST_16: |
| 394 | if (dma_omap2plus()) { | 394 | if (dma_omap2plus()) { |
| 395 | burst = 0x3; | 395 | burst = 0x3; |
| 396 | break; | 396 | break; |
| 397 | } | 397 | } |
| 398 | /* | 398 | /* OMAP1 don't support burst 16 */ |
| 399 | * OMAP1 don't support burst 16 | 399 | /* fall through */ |
| 400 | * fall through | ||
| 401 | */ | ||
| 402 | default: | 400 | default: |
| 403 | BUG(); | 401 | BUG(); |
| 404 | } | 402 | } |
| @@ -474,10 +472,8 @@ void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) · 69 unmodified lines | |||
| 474 | burst = 0x3; | 472 | burst = 0x3; |
| 475 | break; | 473 | break; |
| 476 | } | 474 | } |
| 477 | /* | 475 | /* OMAP1 don't support burst 16 */ |
| 478 | * OMAP1 don't support burst 16 | 476 | /* fall through */ |
| 479 | * fall through | ||
| 480 | */ | ||
| 481 | default: | 477 | default: |
| 482 | printk(KERN_ERR "Invalid DMA burst mode\n"); | 478 | printk(KERN_ERR "Invalid DMA burst mode\n"); |
| 483 | BUG(); | 479 | BUG(); |
| @@ -52,7 +52,7 @@ ifeq ($(CONFIG_GENERIC_COMPAT_VDSO), y) · 51 unmodified lines | |||
| 52 | 52 | ||
| 53 | ifeq ($(CONFIG_CC_IS_CLANG), y) | 53 | ifeq ($(CONFIG_CC_IS_CLANG), y) |
| 54 | $(warning CROSS_COMPILE_COMPAT is clang, the compat vDSO will not be built) | 54 | $(warning CROSS_COMPILE_COMPAT is clang, the compat vDSO will not be built) |
| 55 | else ifeq ($(CROSS_COMPILE_COMPAT),) | 55 | else ifeq ($(strip $(CROSS_COMPILE_COMPAT)),) |
| 56 | $(warning CROSS_COMPILE_COMPAT not defined or empty, the compat vDSO will not be built) | 56 | $(warning CROSS_COMPILE_COMPAT not defined or empty, the compat vDSO will not be built) |
| 57 | else ifeq ($(shell which $(CROSS_COMPILE_COMPAT)gcc 2> /dev/null),) | 57 | else ifeq ($(shell which $(CROSS_COMPILE_COMPAT)gcc 2> /dev/null),) |
| 58 | $(error $(CROSS_COMPILE_COMPAT)gcc not found, check CROSS_COMPILE_COMPAT) | 58 | $(error $(CROSS_COMPILE_COMPAT)gcc not found, check CROSS_COMPILE_COMPAT) |
| @@ -462,7 +462,7 @@ · 461 unmodified lines | |||
| 462 | #define MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1CC 0x434 0x000 0x5 0x0 | 462 | #define MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1CC 0x434 0x000 0x5 0x0 |
| 463 | #define MX8MM_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0 0x1CC 0x434 0x000 0x7 0x0 | 463 | #define MX8MM_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0 0x1CC 0x434 0x000 0x7 0x0 |
| 464 | #define MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0 | 464 | #define MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0 |
| 465 | #define MX8MM_IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x1D0 0x438 0x000 0x1 0x0 | 465 | #define MX8MM_IOMUXC_SAI3_RXC_GPT1_CLK 0x1D0 0x438 0x000 0x1 0x0 |
| 466 | #define MX8MM_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2 | 466 | #define MX8MM_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2 |
| 467 | #define MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0 | 467 | #define MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0 |
| 468 | #define MX8MM_IOMUXC_SAI3_RXC_TPSMP_HTRANS1 0x1D0 0x438 0x000 0x7 0x0 | 468 | #define MX8MM_IOMUXC_SAI3_RXC_TPSMP_HTRANS1 0x1D0 0x438 0x000 0x7 0x0 |
| @@ -472,7 +472,7 @@ · 3 unmodified lines | |||
| 472 | #define MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0 | 472 | #define MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0 |
| 473 | #define MX8MM_IOMUXC_SAI3_RXD_TPSMP_HDATA0 0x1D4 0x43C 0x000 0x7 0x0 | 473 | #define MX8MM_IOMUXC_SAI3_RXD_TPSMP_HDATA0 0x1D4 0x43C 0x000 0x7 0x0 |
| 474 | #define MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0 | 474 | #define MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0 |
| 475 | #define MX8MM_IOMUXC_SAI3_TXFS_GPT1_CLK 0x1D8 0x440 0x000 0x1 0x0 | 475 | #define MX8MM_IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x1D8 0x440 0x000 0x1 0x0 |
| 476 | #define MX8MM_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x2 | 476 | #define MX8MM_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x2 |
| 477 | #define MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0 | 477 | #define MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0 |
| 478 | #define MX8MM_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 0x1D8 0x440 0x000 0x7 0x0 | 478 | #define MX8MM_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 0x1D8 0x440 0x000 0x7 0x0 |
| @@ -715,8 +715,7 @@ · 714 unmodified lines | |||
| 715 | 715 | ||
| 716 | sai2: sai@308b0000 { | 716 | sai2: sai@308b0000 { |
| 717 | #sound-dai-cells = <0>; | 717 | #sound-dai-cells = <0>; |
| 718 | compatible = "fsl,imx8mq-sai", | 718 | compatible = "fsl,imx8mq-sai"; |
| 719 | "fsl,imx6sx-sai"; | ||
| 720 | reg = <0x308b0000 0x10000>; | 719 | reg = <0x308b0000 0x10000>; |
| 721 | interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; | 720 | interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; |
| 722 | clocks = <&clk IMX8MQ_CLK_SAI2_IPG>, | 721 | clocks = <&clk IMX8MQ_CLK_SAI2_IPG>, |
| @@ -155,6 +155,12 @@ static inline void gic_pmr_mask_irqs(void) · 154 unmodified lines | |||
| 155 | BUILD_BUG_ON(GICD_INT_DEF_PRI < (GIC_PRIO_IRQOFF | | 155 | BUILD_BUG_ON(GICD_INT_DEF_PRI < (GIC_PRIO_IRQOFF | |
| 156 | GIC_PRIO_PSR_I_SET)); | 156 | GIC_PRIO_PSR_I_SET)); |
| 157 | BUILD_BUG_ON(GICD_INT_DEF_PRI >= GIC_PRIO_IRQON); | 157 | BUILD_BUG_ON(GICD_INT_DEF_PRI >= GIC_PRIO_IRQON); |
| 158 | /* | ||
| 159 | * Need to make sure IRQON allows IRQs when SCR_EL3.FIQ is cleared | ||
| 160 | * and non-secure PMR accesses are not subject to the shifts that | ||
| 161 | * are applied to IRQ priorities | ||
| 162 | */ | ||
| 163 | BUILD_BUG_ON((0x80 | (GICD_INT_DEF_PRI >> 1)) >= GIC_PRIO_IRQON); | ||
| 158 | gic_write_pmr(GIC_PRIO_IRQOFF); | 164 | gic_write_pmr(GIC_PRIO_IRQOFF); |
| 159 | } | 165 | } |
| 160 | 166 | ||
| @@ -35,9 +35,10 @@ · 34 unmodified lines | |||
| 35 | */ | 35 | */ |
| 36 | 36 | ||
| 37 | enum ftr_type { | 37 | enum ftr_type { |
| 38 | FTR_EXACT, /* Use a predefined safe value */ | 38 | FTR_EXACT, /* Use a predefined safe value */ |
| 39 | FTR_LOWER_SAFE, /* Smaller value is safe */ | 39 | FTR_LOWER_SAFE, /* Smaller value is safe */ |
| 40 | FTR_HIGHER_SAFE,/* Bigger value is safe */ | 40 | FTR_HIGHER_SAFE, /* Bigger value is safe */ |
| 41 | FTR_HIGHER_OR_ZERO_SAFE, /* Bigger value is safe, but 0 is biggest */ | ||
| 41 | }; | 42 | }; |
| 42 | 43 | ||
| 43 | #define FTR_STRICT true /* SANITY check strict matching required */ | 44 | #define FTR_STRICT true /* SANITY check strict matching required */ |
| @@ -13,6 +13,8 @@ · 12 unmodified lines | |||
| 13 | #define DAIF_PROCCTX 0 | 13 | #define DAIF_PROCCTX 0 |
| 14 | #define DAIF_PROCCTX_NOIRQ PSR_I_BIT | 14 | #define DAIF_PROCCTX_NOIRQ PSR_I_BIT |
| 15 | #define DAIF_ERRCTX (PSR_I_BIT | PSR_A_BIT) | 15 | #define DAIF_ERRCTX (PSR_I_BIT | PSR_A_BIT) |
| 16 | #define DAIF_MASK (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT) | ||
| 17 | |||
| 16 | 18 | ||
| 17 | /* mask/save/unmask/restore all exceptions, including interrupts. */ | 19 | /* mask/save/unmask/restore all exceptions, including interrupts. */ |
| 18 | static inline void local_daif_mask(void) | 20 | static inline void local_daif_mask(void) |
| @@ -105,7 +105,11 @@ static inline unsigned long efi_get_max_initrd_addr(unsigned long dram_base, · 104 unmodified lines | |||
| 105 | ((protocol##_t *)instance)->f(instance, ##__VA_ARGS__) | 105 | ((protocol##_t *)instance)->f(instance, ##__VA_ARGS__) |
| 106 | 106 | ||
| 107 | #define alloc_screen_info(x...) &screen_info | 107 | #define alloc_screen_info(x...) &screen_info |
| 108 | #define free_screen_info(x...) | 108 | |
| 109 | static inline void free_screen_info(efi_system_table_t *sys_table_arg, | ||
| 110 | struct screen_info *si) | ||
| 111 | { | ||
| 112 | } | ||
| 109 | 113 | ||
| 110 | /* redeclare as 'hidden' so the compiler will generate relative references */ | 114 | /* redeclare as 'hidden' so the compiler will generate relative references */ |
| 111 | extern struct screen_info screen_info __attribute__((__visibility__("hidden"))); | 115 | extern struct screen_info screen_info __attribute__((__visibility__("hidden"))); |
| @@ -202,7 +202,7 @@ typedef compat_elf_greg_t compat_elf_gregset_t[COMPAT_ELF_NGREG]; · 201 unmodified lines | |||
| 202 | ({ \ | 202 | ({ \ |
| 203 | set_thread_flag(TIF_32BIT); \ | 203 | set_thread_flag(TIF_32BIT); \ |
| 204 | }) | 204 | }) |
| 205 | #ifdef CONFIG_GENERIC_COMPAT_VDSO | 205 | #ifdef CONFIG_COMPAT_VDSO |
| 206 | #define COMPAT_ARCH_DLINFO \ | 206 | #define COMPAT_ARCH_DLINFO \ |
| 207 | do { \ | 207 | do { \ |
| 208 | /* \ | 208 | /* \ |
| @@ -316,9 +316,10 @@ · 315 unmodified lines | |||
| 316 | 316 | ||
| 317 | #define kvm_arm_exception_class \ | 317 | #define kvm_arm_exception_class \ |
| 318 | ECN(UNKNOWN), ECN(WFx), ECN(CP15_32), ECN(CP15_64), ECN(CP14_MR), \ | 318 | ECN(UNKNOWN), ECN(WFx), ECN(CP15_32), ECN(CP15_64), ECN(CP14_MR), \ |
| 319 | ECN(CP14_LS), ECN(FP_ASIMD), ECN(CP10_ID), ECN(CP14_64), ECN(SVC64), \ | 319 | ECN(CP14_LS), ECN(FP_ASIMD), ECN(CP10_ID), ECN(PAC), ECN(CP14_64), \ |
| 320 | ECN(HVC64), ECN(SMC64), ECN(SYS64), ECN(IMP_DEF), ECN(IABT_LOW), \ | 320 | ECN(SVC64), ECN(HVC64), ECN(SMC64), ECN(SYS64), ECN(SVE), \ |
| 321 | ECN(IABT_CUR), ECN(PC_ALIGN), ECN(DABT_LOW), ECN(DABT_CUR), \ | 321 | ECN(IMP_DEF), ECN(IABT_LOW), ECN(IABT_CUR), \ |
| 322 | ECN(PC_ALIGN), ECN(DABT_LOW), ECN(DABT_CUR), \ | ||
| 322 | ECN(SP_ALIGN), ECN(FP_EXC32), ECN(FP_EXC64), ECN(SERROR), \ | 323 | ECN(SP_ALIGN), ECN(FP_EXC32), ECN(FP_EXC64), ECN(SERROR), \ |
| 323 | ECN(BREAKPT_LOW), ECN(BREAKPT_CUR), ECN(SOFTSTP_LOW), \ | 324 | ECN(BREAKPT_LOW), ECN(BREAKPT_CUR), ECN(SOFTSTP_LOW), \ |
| 324 | ECN(SOFTSTP_CUR), ECN(WATCHPT_LOW), ECN(WATCHPT_CUR), \ | 325 | ECN(SOFTSTP_CUR), ECN(WATCHPT_LOW), ECN(WATCHPT_CUR), \ |
| @@ -210,7 +210,11 @@ extern u64 vabits_user; · 209 unmodified lines | |||
| 210 | #define __tag_reset(addr) untagged_addr(addr) | 210 | #define __tag_reset(addr) untagged_addr(addr) |
| 211 | #define __tag_get(addr) (__u8)((u64)(addr) >> 56) | 211 | #define __tag_get(addr) (__u8)((u64)(addr) >> 56) |
| 212 | #else | 212 | #else |
| 213 | #define __tag_set(addr, tag) (addr) | 213 | static inline const void *__tag_set(const void *addr, u8 tag) |
| 214 | { | ||
| 215 | return addr; | ||
| 216 | } | ||
| 217 | |||
| 214 | #define __tag_reset(addr) (addr) | 218 | #define __tag_reset(addr) (addr) |
| 215 | #define __tag_get(addr) 0 | 219 | #define __tag_get(addr) 0 |
| 216 | #endif | 220 | #endif |
| @@ -301,8 +305,8 @@ static inline void *phys_to_virt(phys_addr_t x) · 84 unmodified lines | |||
| 301 | #define page_to_virt(page) ({ \ | 305 | #define page_to_virt(page) ({ \ |
| 302 | unsigned long __addr = \ | 306 | unsigned long __addr = \ |
| 303 | ((__page_to_voff(page)) | PAGE_OFFSET); \ | 307 | ((__page_to_voff(page)) | PAGE_OFFSET); \ |
| 304 | unsigned long __addr_tag = \ | 308 | const void *__addr_tag = \ |
| 305 | __tag_set(__addr, page_kasan_tag(page)); \ | 309 | __tag_set((void *)__addr, page_kasan_tag(page)); \ |
| 306 | ((void *)__addr_tag); \ | 310 | ((void *)__addr_tag); \ |
| 307 | }) | 311 | }) |
| 308 | 312 | ||
| @@ -209,7 +209,7 @@ static inline pmd_t pmd_mkcont(pmd_t pmd) · 208 unmodified lines | |||
| 209 | 209 | ||
| 210 | static inline pte_t pte_mkdevmap(pte_t pte) | 210 | static inline pte_t pte_mkdevmap(pte_t pte) |
| 211 | { | 211 | { |
| 212 | return set_pte_bit(pte, __pgprot(PTE_DEVMAP)); | 212 | return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL)); |
| 213 | } | 213 | } |
| 214 | 214 | ||
| 215 | static inline void set_pte(pte_t *ptep, pte_t pte) | 215 | static inline void set_pte(pte_t *ptep, pte_t pte) |
| @@ -301,7 +301,6 @@ static inline int pte_same(pte_t pte_a, pte_t pte_b) · 85 unmodified lines | |||
| 301 | /* | 301 | /* |
| 302 | * Huge pte definitions. | 302 | * Huge pte definitions. |
| 303 | */ | 303 | */ |
| 304 | #define pte_huge(pte) (!(pte_val(pte) & PTE_TABLE_BIT)) | ||
| 305 | #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) | 304 | #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) |
| 306 | 305 | ||
| 307 | /* | 306 | /* |
| @@ -397,7 +396,10 @@ static inline int pmd_protnone(pmd_t pmd) · 89 unmodified lines | |||
| 397 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE | 396 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
| 398 | #define pmd_devmap(pmd) pte_devmap(pmd_pte(pmd)) | 397 | #define pmd_devmap(pmd) pte_devmap(pmd_pte(pmd)) |
| 399 | #endif | 398 | #endif |
| 400 | #define pmd_mkdevmap(pmd) pte_pmd(pte_mkdevmap(pmd_pte(pmd))) | 399 | static inline pmd_t pmd_mkdevmap(pmd_t pmd) |
| 400 | { | ||
| 401 | return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP))); | ||
| 402 | } | ||
| 401 | 403 | ||
| 402 | #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd)) | 404 | #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd)) |
| 403 | #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys) | 405 | #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys) |
| @@ -448,8 +450,8 @@ extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, · 44 unmodified lines | |||
| 448 | PMD_TYPE_SECT) | 450 | PMD_TYPE_SECT) |
| 449 | 451 | ||
| 450 | #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3 | 452 | #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3 |
| 451 | #define pud_sect(pud) (0) | 453 | static inline bool pud_sect(pud_t pud) { return false; } |
| 452 | #define pud_table(pud) (1) | 454 | static inline bool pud_table(pud_t pud) { return true; } |
| 453 | #else | 455 | #else |
| 454 | #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ | 456 | #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ |
| 455 | PUD_TYPE_SECT) | 457 | PUD_TYPE_SECT) |
| @@ -193,6 +193,16 @@ static inline void start_thread_common(struct pt_regs *regs, unsigned long pc) · 192 unmodified lines | |||
| 193 | regs->pmr_save = GIC_PRIO_IRQON; | 193 | regs->pmr_save = GIC_PRIO_IRQON; |
| 194 | } | 194 | } |
| 195 | 195 | ||
| 196 | static inline void set_ssbs_bit(struct pt_regs *regs) | ||
| 197 | { | ||
| 198 | regs->pstate |= PSR_SSBS_BIT; | ||
| 199 | } | ||
| 200 | |||
| 201 | static inline void set_compat_ssbs_bit(struct pt_regs *regs) | ||
| 202 | { | ||
| 203 | regs->pstate |= PSR_AA32_SSBS_BIT; | ||
| 204 | } | ||
| 205 | |||
| 196 | static inline void start_thread(struct pt_regs *regs, unsigned long pc, | 206 | static inline void start_thread(struct pt_regs *regs, unsigned long pc, |
| 197 | unsigned long sp) | 207 | unsigned long sp) |
| 198 | { | 208 | { |
| @@ -200,7 +210,7 @@ static inline void start_thread(struct pt_regs *regs, unsigned long pc, · 1 unmodified line | |||
| 200 | regs->pstate = PSR_MODE_EL0t; | 210 | regs->pstate = PSR_MODE_EL0t; |
| 201 | 211 | ||
| 202 | if (arm64_get_ssbd_state() != ARM64_SSBD_FORCE_ENABLE) | 212 | if (arm64_get_ssbd_state() != ARM64_SSBD_FORCE_ENABLE) |
| 203 | regs->pstate |= PSR_SSBS_BIT; | 213 | set_ssbs_bit(regs); |
| 204 | 214 | ||
| 205 | regs->sp = sp; | 215 | regs->sp = sp; |
| 206 | } | 216 | } |
| @@ -219,7 +229,7 @@ static inline void compat_start_thread(struct pt_regs *regs, unsigned long pc, · 12 unmodified lines | |||
| 219 | #endif | 229 | #endif |
| 220 | 230 | ||
| 221 | if (arm64_get_ssbd_state() != ARM64_SSBD_FORCE_ENABLE) | 231 | if (arm64_get_ssbd_state() != ARM64_SSBD_FORCE_ENABLE) |
| 222 | regs->pstate |= PSR_AA32_SSBS_BIT; | 232 | set_compat_ssbs_bit(regs); |
| 223 | 233 | ||
| 224 | regs->compat_sp = sp; | 234 | regs->compat_sp = sp; |
| 225 | } | 235 | } |
| @@ -30,7 +30,7 @@ · 29 unmodified lines | |||
| 30 | * in the the priority mask, it indicates that PSR.I should be set and | 30 | * in the the priority mask, it indicates that PSR.I should be set and |
| 31 | * interrupt disabling temporarily does not rely on IRQ priorities. | 31 | * interrupt disabling temporarily does not rely on IRQ priorities. |
| 32 | */ | 32 | */ |
| 33 | #define GIC_PRIO_IRQON 0xc0 | 33 | #define GIC_PRIO_IRQON 0xe0 |
| 34 | #define GIC_PRIO_IRQOFF (GIC_PRIO_IRQON & ~0x80) | 34 | #define GIC_PRIO_IRQOFF (GIC_PRIO_IRQON & ~0x80) |
| 35 | #define GIC_PRIO_PSR_I_SET (1 << 4) | 35 | #define GIC_PRIO_PSR_I_SET (1 << 4) |
| 36 | 36 | ||
| @@ -8,19 +8,12 @@ · 7 unmodified lines | |||
| 8 | #include <linux/percpu.h> | 8 | #include <linux/percpu.h> |
| 9 | #include <linux/sched.h> | 9 | #include <linux/sched.h> |
| 10 | #include <linux/sched/task_stack.h> | 10 | #include <linux/sched/task_stack.h> |
| 11 | #include <linux/types.h> | ||
| 11 | 12 | ||
| 12 | #include <asm/memory.h> | 13 | #include <asm/memory.h> |
| 13 | #include <asm/ptrace.h> | 14 | #include <asm/ptrace.h> |
| 14 | #include <asm/sdei.h> | 15 | #include <asm/sdei.h> |
| 15 | 16 | ||
| 16 | struct stackframe { | ||
| 17 | unsigned long fp; | ||
| 18 | unsigned long pc; | ||
| 19 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER | ||
| 20 | int graph; | ||
| 21 | #endif | ||
| 22 | }; | ||
| 23 | |||
| 24 | enum stack_type { | 17 | enum stack_type { |
| 25 | STACK_TYPE_UNKNOWN, | 18 | STACK_TYPE_UNKNOWN, |
| 26 | STACK_TYPE_TASK, | 19 | STACK_TYPE_TASK, |
| @@ -28,6 +21,7 @@ enum stack_type { · 1 unmodified line | |||
| 28 | STACK_TYPE_OVERFLOW, | 21 | STACK_TYPE_OVERFLOW, |
| 29 | STACK_TYPE_SDEI_NORMAL, | 22 | STACK_TYPE_SDEI_NORMAL, |
| 30 | STACK_TYPE_SDEI_CRITICAL, | 23 | STACK_TYPE_SDEI_CRITICAL, |
| 24 | __NR_STACK_TYPES | ||
| 31 | }; | 25 | }; |
| 32 | 26 | ||
| 33 | struct stack_info { | 27 | struct stack_info { |
| @@ -36,6 +30,37 @@ struct stack_info { · 2 unmodified lines | |||
| 36 | enum stack_type type; | 30 | enum stack_type type; |
| 37 | }; | 31 | }; |
| 38 | 32 | ||
| 33 | /* | ||
| 34 | * A snapshot of a frame record or fp/lr register values, along with some | ||
| 35 | * accounting information necessary for robust unwinding. | ||
| 36 | * | ||
| 37 | * @fp: The fp value in the frame record (or the real fp) | ||
| 38 | * @pc: The fp value in the frame record (or the real lr) | ||
| 39 | * | ||
| 40 | * @stacks_done: Stacks which have been entirely unwound, for which it is no | ||
| 41 | * longer valid to unwind to. | ||
| 42 | * | ||
| 43 | * @prev_fp: The fp that pointed to this frame record, or a synthetic value | ||
| 44 | * of 0. This is used to ensure that within a stack, each | ||
| 45 | * subsequent frame record is at an increasing address. | ||
| 46 | * @prev_type: The type of stack this frame record was on, or a synthetic | ||
| 47 | * value of STACK_TYPE_UNKNOWN. This is used to detect a | ||
| 48 | * transition from one stack to another. | ||
| 49 | * | ||
| 50 | * @graph: When FUNCTION_GRAPH_TRACER is selected, holds the index of a | ||
| 51 | * replacement lr value in the ftrace graph stack. | ||
| 52 | */ | ||
| 53 | struct stackframe { | ||
| 54 | unsigned long fp; | ||
| 55 | unsigned long pc; | ||
| 56 | DECLARE_BITMAP(stacks_done, __NR_STACK_TYPES); | ||
| 57 | unsigned long prev_fp; | ||
| 58 | enum stack_type prev_type; | ||
| 59 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER | ||
| 60 | int graph; | ||
| 61 | #endif | ||
| 62 | }; | ||
| 63 | |||
| 39 | extern int unwind_frame(struct task_struct *tsk, struct stackframe *frame); | 64 | extern int unwind_frame(struct task_struct *tsk, struct stackframe *frame); |
| 40 | extern void walk_stackframe(struct task_struct *tsk, struct stackframe *frame, | 65 | extern void walk_stackframe(struct task_struct *tsk, struct stackframe *frame, |
| 41 | int (*fn)(struct stackframe *, void *), void *data); | 66 | int (*fn)(struct stackframe *, void *), void *data); |
| @@ -64,8 +89,9 @@ static inline bool on_irq_stack(unsigned long sp, · 22 unmodified lines | |||
| 64 | return true; | 89 | return true; |
| 65 | } | 90 | } |
| 66 | 91 | ||
| 67 | static inline bool on_task_stack(struct task_struct *tsk, unsigned long sp, | 92 | static inline bool on_task_stack(const struct task_struct *tsk, |
| 68 | struct stack_info *info) | 93 | unsigned long sp, |
| 94 | struct stack_info *info) | ||
| 69 | { | 95 | { |
| 70 | unsigned long low = (unsigned long)task_stack_page(tsk); | 96 | unsigned long low = (unsigned long)task_stack_page(tsk); |
| 71 | unsigned long high = low + THREAD_SIZE; | 97 | unsigned long high = low + THREAD_SIZE; |
| @@ -112,10 +138,13 @@ static inline bool on_overflow_stack(unsigned long sp, · 40 unmodified lines | |||
| 112 | * We can only safely access per-cpu stacks from current in a non-preemptible | 138 | * We can only safely access per-cpu stacks from current in a non-preemptible |
| 113 | * context. | 139 | * context. |
| 114 | */ | 140 | */ |
| 115 | static inline bool on_accessible_stack(struct task_struct *tsk, | 141 | static inline bool on_accessible_stack(const struct task_struct *tsk, |
| 116 | unsigned long sp, | 142 | unsigned long sp, |
| 117 | struct stack_info *info) | 143 | struct stack_info *info) |
| 118 | { | 144 | { |
| 145 | if (info) | ||
| 146 | info->type = STACK_TYPE_UNKNOWN; | ||
| 147 | |||
| 119 | if (on_task_stack(tsk, sp, info)) | 148 | if (on_task_stack(tsk, sp, info)) |
| 120 | return true; | 149 | return true; |
| 121 | if (tsk != current || preemptible()) | 150 | if (tsk != current || preemptible()) |
| @@ -130,4 +159,27 @@ static inline bool on_accessible_stack(struct task_struct *tsk, · 8 unmodified lines | |||
| 130 | return false; | 159 | return false; |
| 131 | } | 160 | } |
| 132 | 161 | ||
| 162 | static inline void start_backtrace(struct stackframe *frame, | ||
| 163 | unsigned long fp, unsigned long pc) | ||
| 164 | { | ||
| 165 | frame->fp = fp; | ||
| 166 | frame->pc = pc; | ||
| 167 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER | ||
| 168 | frame->graph = 0; | ||
| 169 | #endif | ||
| 170 | |||
| 171 | /* | ||
| 172 | * Prime the first unwind. | ||
| 173 | * | ||
| 174 | * In unwind_frame() we'll check that the FP points to a valid stack, | ||
| 175 | * which can't be STACK_TYPE_UNKNOWN, and the first unwind will be | ||
| 176 | * treated as a transition to whichever stack that happens to be. The | ||
| 177 | * prev_fp value won't be used, but we set it to 0 such that it is | ||
| 178 | * definitely not an accessible stack address. | ||
| 179 | */ | ||
| 180 | bitmap_zero(frame->stacks_done, __NR_STACK_TYPES); | ||
| 181 | frame->prev_fp = 0; | ||
| 182 | frame->prev_type = STACK_TYPE_UNKNOWN; | ||
| 183 | } | ||
| 184 | |||
| 133 | #endif /* __ASM_STACKTRACE_H */ | 185 | #endif /* __ASM_STACKTRACE_H */ |
| @@ -16,6 +16,8 @@ · 15 unmodified lines | |||
| 16 | 16 | ||
| 17 | #define VDSO_HAS_CLOCK_GETRES 1 | 17 | #define VDSO_HAS_CLOCK_GETRES 1 |
| 18 | 18 | ||
| 19 | #define VDSO_HAS_32BIT_FALLBACK 1 | ||
| 20 | |||
| 19 | static __always_inline | 21 | static __always_inline |
| 20 | int gettimeofday_fallback(struct __kernel_old_timeval *_tv, | 22 | int gettimeofday_fallback(struct __kernel_old_timeval *_tv, |
| 21 | struct timezone *_tz) | 23 | struct timezone *_tz) |
| @@ -51,6 +53,23 @@ long clock_gettime_fallback(clockid_t _clkid, struct __kernel_timespec *_ts) · 29 unmodified lines | |||
| 51 | return ret; | 53 | return ret; |
| 52 | } | 54 | } |
| 53 | 55 | ||
| 56 | static __always_inline | ||
| 57 | long clock_gettime32_fallback(clockid_t _clkid, struct old_timespec32 *_ts) | ||
| 58 | { | ||
| 59 | register struct old_timespec32 *ts asm("r1") = _ts; | ||
| 60 | register clockid_t clkid asm("r0") = _clkid; | ||
| 61 | register long ret asm ("r0"); | ||
| 62 | register long nr asm("r7") = __NR_compat_clock_gettime; | ||
| 63 | |||
| 64 | asm volatile( | ||
| 65 | " swi #0\n" | ||
| 66 | : "=r" (ret) | ||
| 67 | : "r" (clkid), "r" (ts), "r" (nr) | ||
| 68 | : "memory"); | ||
| 69 | |||
| 70 | return ret; | ||
| 71 | } | ||
| 72 | |||
| 54 | static __always_inline | 73 | static __always_inline |
| 55 | int clock_getres_fallback(clockid_t _clkid, struct __kernel_timespec *_ts) | 74 | int clock_getres_fallback(clockid_t _clkid, struct __kernel_timespec *_ts) |
| 56 | { | 75 | { |
| @@ -72,6 +91,27 @@ int clock_getres_fallback(clockid_t _clkid, struct __kernel_timespec *_ts) · 15 unmodified lines | |||
| 72 | return ret; | 91 | return ret; |
| 73 | } | 92 | } |
| 74 | 93 | ||
| 94 | static __always_inline | ||
| 95 | int clock_getres32_fallback(clockid_t _clkid, struct old_timespec32 *_ts) | ||
| 96 | { | ||
| 97 | register struct old_timespec32 *ts asm("r1") = _ts; | ||
| 98 | register clockid_t clkid asm("r0") = _clkid; | ||
| 99 | register long ret asm ("r0"); | ||
| 100 | register long nr asm("r7") = __NR_compat_clock_getres; | ||
| 101 | |||
| 102 | /* The checks below are required for ABI consistency with arm */ | ||
| 103 | if ((_clkid >= MAX_CLOCKS) && (_ts == NULL)) | ||
| 104 | return -EINVAL; | ||
| 105 | |||
| 106 | asm volatile( | ||
| 107 | " swi #0\n" | ||
| 108 | : "=r" (ret) | ||
| 109 | : "r" (clkid), "r" (ts), "r" (nr) | ||
| 110 | : "memory"); | ||
| 111 | |||
| 112 | return ret; | ||
| 113 | } | ||
| 114 | |||
| 75 | static __always_inline u64 __arch_get_hw_counter(s32 clock_mode) | 115 | static __always_inline u64 __arch_get_hw_counter(s32 clock_mode) |
| 76 | { | 116 | { |
| 77 | u64 res; | 117 | u64 res; |
| @@ -1,4 +1,4 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0 */ | 1 | /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ |
| 2 | #ifndef _UAPI__ASM_BPF_PERF_EVENT_H__ | 2 | #ifndef _UAPI__ASM_BPF_PERF_EVENT_H__ |
| 3 | #define _UAPI__ASM_BPF_PERF_EVENT_H__ | 3 | #define _UAPI__ASM_BPF_PERF_EVENT_H__ |
| 4 | 4 | ||
| @@ -184,9 +184,17 @@ static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { · 183 unmodified lines | |||
| 184 | }; | 184 | }; |
| 185 | 185 | ||
| 186 | static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { | 186 | static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { |
| 187 | S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI), | 187 | /* |
| 188 | S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI), | 188 | * We already refuse to boot CPUs that don't support our configured |
| 189 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI), | 189 | * page size, so we can only detect mismatches for a page size other |
| 190 | * than the one we're currently using. Unfortunately, SoCs like this | ||
| 191 | * exist in the wild so, even though we don't like it, we'll have to go | ||
| 192 | * along with it and treat them as non-strict. | ||
| 193 | */ | ||
| 194 | S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI), | ||
| 195 | S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI), | ||
| 196 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI), | ||
| 197 | |||
| 190 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0), | 198 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0), |
| 191 | /* Linux shouldn't care about secure memory */ | 199 | /* Linux shouldn't care about secure memory */ |
| 192 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0), | 200 | ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0), |
| @@ -225,8 +233,8 @@ static const struct arm64_ftr_bits ftr_ctr[] = { · 32 unmodified lines | |||
| 225 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ | 233 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ |
| 226 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1), | 234 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1), |
| 227 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1), | 235 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1), |
| 228 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, CTR_CWG_SHIFT, 4, 0), | 236 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0), |
| 229 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, CTR_ERG_SHIFT, 4, 0), | 237 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0), |
| 230 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1), | 238 | ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1), |
| 231 | /* | 239 | /* |
| 232 | * Linux can handle differing I-cache policies. Userspace JITs will | 240 | * Linux can handle differing I-cache policies. Userspace JITs will |
| @@ -468,6 +476,10 @@ static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, · 235 unmodified lines | |||
| 468 | case FTR_LOWER_SAFE: | 476 | case FTR_LOWER_SAFE: |
| 469 | ret = new < cur ? new : cur; | 477 | ret = new < cur ? new : cur; |
| 470 | break; | 478 | break; |
| 479 | case FTR_HIGHER_OR_ZERO_SAFE: | ||
| 480 | if (!cur || !new) | ||
| 481 | break; | ||
| 482 | /* Fallthrough */ | ||
| 471 | case FTR_HIGHER_SAFE: | 483 | case FTR_HIGHER_SAFE: |
| 472 | ret = new > cur ? new : cur; | 484 | ret = new > cur ? new : cur; |
| 473 | break; | 485 | break; |
| @@ -207,16 +207,16 @@ static int call_step_hook(struct pt_regs *regs, unsigned int esr) · 206 unmodified lines | |||
| 207 | 207 | ||
| 208 | list = user_mode(regs) ? &user_step_hook : &kernel_step_hook; | 208 | list = user_mode(regs) ? &user_step_hook : &kernel_step_hook; |
| 209 | 209 | ||
| 210 | rcu_read_lock(); | 210 | /* |
| 211 | 211 | * Since single-step exception disables interrupt, this function is | |
| 212 | * entirely not preemptible, and we can use rcu list safely here. | ||
| 213 | */ | ||
| 212 | list_for_each_entry_rcu(hook, list, node) { | 214 | list_for_each_entry_rcu(hook, list, node) { |
| 213 | retval = hook->fn(regs, esr); | 215 | retval = hook->fn(regs, esr); |
| 214 | if (retval == DBG_HOOK_HANDLED) | 216 | if (retval == DBG_HOOK_HANDLED) |
| 215 | break; | 217 | break; |
| 216 | } | 218 | } |
| 217 | 219 | ||
| 218 | rcu_read_unlock(); | ||
| 219 | |||
| 220 | return retval; | 220 | return retval; |
| 221 | } | 221 | } |
| 222 | NOKPROBE_SYMBOL(call_step_hook); | 222 | NOKPROBE_SYMBOL(call_step_hook); |
| @@ -305,14 +305,16 @@ static int call_break_hook(struct pt_regs *regs, unsigned int esr) · 82 unmodified lines | |||
| 305 | 305 | ||
| 306 | list = user_mode(regs) ? &user_break_hook : &kernel_break_hook; | 306 | list = user_mode(regs) ? &user_break_hook : &kernel_break_hook; |
| 307 | 307 | ||
| 308 | rcu_read_lock(); | 308 | /* |
| 309 | * Since brk exception disables interrupt, this function is | ||
| 310 | * entirely not preemptible, and we can use rcu list safely here. | ||
| 311 | */ | ||
| 309 | list_for_each_entry_rcu(hook, list, node) { | 312 | list_for_each_entry_rcu(hook, list, node) { |
| 310 | unsigned int comment = esr & ESR_ELx_BRK64_ISS_COMMENT_MASK; | 313 | unsigned int comment = esr & ESR_ELx_BRK64_ISS_COMMENT_MASK; |
| 311 | 314 | ||
| 312 | if ((comment & ~hook->mask) == hook->imm) | 315 | if ((comment & ~hook->mask) == hook->imm) |
| 313 | fn = hook->fn; | 316 | fn = hook->fn; |
| 314 | } | 317 | } |
| 315 | rcu_read_unlock(); | ||
| 316 | 318 | ||
| 317 | return fn ? fn(regs, esr) : DBG_HOOK_ERROR; | 319 | return fn ? fn(regs, esr) : DBG_HOOK_ERROR; |
| 318 | } | 320 | } |
| @@ -586,10 +586,8 @@ el1_sync: · 585 unmodified lines | |||
| 586 | b.eq el1_ia | 586 | b.eq el1_ia |
| 587 | cmp x24, #ESR_ELx_EC_SYS64 // configurable trap | 587 | cmp x24, #ESR_ELx_EC_SYS64 // configurable trap |
| 588 | b.eq el1_undef | 588 | b.eq el1_undef |
| 589 | cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception | ||
| 590 | b.eq el1_sp_pc | ||
| 591 | cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception | 589 | cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception |
| 592 | b.eq el1_sp_pc | 590 | b.eq el1_pc |
| 593 | cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL1 | 591 | cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL1 |
| 594 | b.eq el1_undef | 592 | b.eq el1_undef |
| 595 | cmp x24, #ESR_ELx_EC_BREAKPT_CUR // debug exception in EL1 | 593 | cmp x24, #ESR_ELx_EC_BREAKPT_CUR // debug exception in EL1 |
| @@ -611,9 +609,11 @@ el1_da: · 15 unmodified lines | |||
| 611 | bl do_mem_abort | 609 | bl do_mem_abort |
| 612 | 610 | ||
| 613 | kernel_exit 1 | 611 | kernel_exit 1 |
| 614 | el1_sp_pc: | 612 | el1_pc: |
| 615 | /* | 613 | /* |
| 616 | * Stack or PC alignment exception handling | 614 | * PC alignment exception handling. We don't handle SP alignment faults, |
| 615 | * since we will have hit a recursive exception when trying to push the | ||
| 616 | * initial pt_regs. | ||
| 617 | */ | 617 | */ |
| 618 | mrs x0, far_el1 | 618 | mrs x0, far_el1 |
| 619 | inherit_daif pstate=x23, tmp=x2 | 619 | inherit_daif pstate=x23, tmp=x2 |
| @@ -732,9 +732,9 @@ el0_sync: · 112 unmodified lines | |||
| 732 | ccmp x24, #ESR_ELx_EC_WFx, #4, ne | 732 | ccmp x24, #ESR_ELx_EC_WFx, #4, ne |
| 733 | b.eq el0_sys | 733 | b.eq el0_sys |
| 734 | cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception | 734 | cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception |
| 735 | b.eq el0_sp_pc | 735 | b.eq el0_sp |
| 736 | cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception | 736 | cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception |
| 737 | b.eq el0_sp_pc | 737 | b.eq el0_pc |
| 738 | cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0 | 738 | cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0 |
| 739 | b.eq el0_undef | 739 | b.eq el0_undef |
| 740 | cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0 | 740 | cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0 |
| @@ -758,7 +758,7 @@ el0_sync_compat: · 17 unmodified lines | |||
| 758 | cmp x24, #ESR_ELx_EC_FP_EXC32 // FP/ASIMD exception | 758 | cmp x24, #ESR_ELx_EC_FP_EXC32 // FP/ASIMD exception |
| 759 | b.eq el0_fpsimd_exc | 759 | b.eq el0_fpsimd_exc |
| 760 | cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception | 760 | cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception |
| 761 | b.eq el0_sp_pc | 761 | b.eq el0_pc |
| 762 | cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0 | 762 | cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0 |
| 763 | b.eq el0_undef | 763 | b.eq el0_undef |
| 764 | cmp x24, #ESR_ELx_EC_CP15_32 // CP15 MRC/MCR trap | 764 | cmp x24, #ESR_ELx_EC_CP15_32 // CP15 MRC/MCR trap |
| @@ -858,11 +858,15 @@ el0_fpsimd_exc: · 93 unmodified lines | |||
| 858 | mov x1, sp | 858 | mov x1, sp |
| 859 | bl do_fpsimd_exc | 859 | bl do_fpsimd_exc |
| 860 | b ret_to_user | 860 | b ret_to_user |
| 861 | el0_sp: | ||
| 862 | ldr x26, [sp, #S_SP] | ||
| 863 | b el0_sp_pc | ||
| 864 | el0_pc: | ||
| 865 | mrs x26, far_el1 | ||
| 861 | el0_sp_pc: | 866 | el0_sp_pc: |
| 862 | /* | 867 | /* |
| 863 | * Stack or PC alignment exception handling | 868 | * Stack or PC alignment exception handling |
| 864 | */ | 869 | */ |
| 865 | mrs x26, far_el1 | ||
| 866 | gic_prio_kentry_setup tmp=x0 | 870 | gic_prio_kentry_setup tmp=x0 |
| 867 | enable_da_f | 871 | enable_da_f |
| 868 | #ifdef CONFIG_TRACE_IRQFLAGS | 872 | #ifdef CONFIG_TRACE_IRQFLAGS |
| @@ -406,6 +406,18 @@ static __uint128_t arm64_cpu_to_le128(__uint128_t x) · 405 unmodified lines | |||
| 406 | 406 | ||
| 407 | #define arm64_le128_to_cpu(x) arm64_cpu_to_le128(x) | 407 | #define arm64_le128_to_cpu(x) arm64_cpu_to_le128(x) |
| 408 | 408 | ||
| 409 | static void __fpsimd_to_sve(void *sst, struct user_fpsimd_state const *fst, | ||
| 410 | unsigned int vq) | ||
| 411 | { | ||
| 412 | unsigned int i; | ||
| 413 | __uint128_t *p; | ||
| 414 | |||
| 415 | for (i = 0; i < SVE_NUM_ZREGS; ++i) { | ||
| 416 | p = (__uint128_t *)ZREG(sst, vq, i); | ||
| 417 | *p = arm64_cpu_to_le128(fst->vregs[i]); | ||
| 418 | } | ||
| 419 | } | ||
| 420 | |||
| 409 | /* | 421 | /* |
| 410 | * Transfer the FPSIMD state in task->thread.uw.fpsimd_state to | 422 | * Transfer the FPSIMD state in task->thread.uw.fpsimd_state to |
| 411 | * task->thread.sve_state. | 423 | * task->thread.sve_state. |
| @@ -423,17 +435,12 @@ static void fpsimd_to_sve(struct task_struct *task) · 11 unmodified lines | |||
| 423 | unsigned int vq; | 435 | unsigned int vq; |
| 424 | void *sst = task->thread.sve_state; | 436 | void *sst = task->thread.sve_state; |
| 425 | struct user_fpsimd_state const *fst = &task->thread.uw.fpsimd_state; | 437 | struct user_fpsimd_state const *fst = &task->thread.uw.fpsimd_state; |
| 426 | unsigned int i; | ||
| 427 | __uint128_t *p; | ||
| 428 | 438 | ||
| 429 | if (!system_supports_sve()) | 439 | if (!system_supports_sve()) |
| 430 | return; | 440 | return; |
| 431 | 441 | ||
| 432 | vq = sve_vq_from_vl(task->thread.sve_vl); | 442 | vq = sve_vq_from_vl(task->thread.sve_vl); |
| 433 | for (i = 0; i < 32; ++i) { | 443 | __fpsimd_to_sve(sst, fst, vq); |
| 434 | p = (__uint128_t *)ZREG(sst, vq, i); | ||
| 435 | *p = arm64_cpu_to_le128(fst->vregs[i]); | ||
| 436 | } | ||
| 437 | } | 444 | } |
| 438 | 445 | ||
| 439 | /* | 446 | /* |
| @@ -459,7 +466,7 @@ static void sve_to_fpsimd(struct task_struct *task) · 19 unmodified lines | |||
| 459 | return; | 466 | return; |
| 460 | 467 | ||
| 461 | vq = sve_vq_from_vl(task->thread.sve_vl); | 468 | vq = sve_vq_from_vl(task->thread.sve_vl); |
| 462 | for (i = 0; i < 32; ++i) { | 469 | for (i = 0; i < SVE_NUM_ZREGS; ++i) { |
| 463 | p = (__uint128_t const *)ZREG(sst, vq, i); | 470 | p = (__uint128_t const *)ZREG(sst, vq, i); |
| 464 | fst->vregs[i] = arm64_le128_to_cpu(*p); | 471 | fst->vregs[i] = arm64_le128_to_cpu(*p); |
| 465 | } | 472 | } |
| @@ -550,8 +557,6 @@ void sve_sync_from_fpsimd_zeropad(struct task_struct *task) · 84 unmodified lines | |||
| 550 | unsigned int vq; | 557 | unsigned int vq; |
| 551 | void *sst = task->thread.sve_state; | 558 | void *sst = task->thread.sve_state; |
| 552 | struct user_fpsimd_state const *fst = &task->thread.uw.fpsimd_state; | 559 | struct user_fpsimd_state const *fst = &task->thread.uw.fpsimd_state; |
| 553 | unsigned int i; | ||
| 554 | __uint128_t *p; | ||
| 555 | 560 | ||
| 556 | if (!test_tsk_thread_flag(task, TIF_SVE)) | 561 | if (!test_tsk_thread_flag(task, TIF_SVE)) |
| 557 | return; | 562 | return; |
| @@ -559,11 +564,7 @@ void sve_sync_from_fpsimd_zeropad(struct task_struct *task) · 1 unmodified line | |||
| 559 | vq = sve_vq_from_vl(task->thread.sve_vl); | 564 | vq = sve_vq_from_vl(task->thread.sve_vl); |
| 560 | 565 | ||
| 561 | memset(sst, 0, SVE_SIG_REGS_SIZE(vq)); | 566 | memset(sst, 0, SVE_SIG_REGS_SIZE(vq)); |
| 562 | 567 | __fpsimd_to_sve(sst, fst, vq); | |
| 563 | for (i = 0; i < 32; ++i) { | ||
| 564 | p = (__uint128_t *)ZREG(sst, vq, i); | ||
| 565 | *p = arm64_cpu_to_le128(fst->vregs[i]); | ||
| 566 | } | ||
| 567 | } | 568 | } |
| 568 | 569 | ||
| 569 | int sve_set_vector_length(struct task_struct *task, | 570 | int sve_set_vector_length(struct task_struct *task, |
| @@ -73,7 +73,7 @@ int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr) · 72 unmodified lines | |||
| 73 | 73 | ||
| 74 | if (offset < -SZ_128M || offset >= SZ_128M) { | 74 | if (offset < -SZ_128M || offset >= SZ_128M) { |
| 75 | #ifdef CONFIG_ARM64_MODULE_PLTS | 75 | #ifdef CONFIG_ARM64_MODULE_PLTS |
| 76 | struct plt_entry trampoline; | 76 | struct plt_entry trampoline, *dst; |
| 77 | struct module *mod; | 77 | struct module *mod; |
| 78 | 78 | ||
| 79 | /* | 79 | /* |
| @@ -106,23 +106,27 @@ int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr) · 26 unmodified lines | |||
| 106 | * to check if the actual opcodes are in fact identical, | 106 | * to check if the actual opcodes are in fact identical, |
| 107 | * regardless of the offset in memory so use memcmp() instead. | 107 | * regardless of the offset in memory so use memcmp() instead. |
| 108 | */ | 108 | */ |
| 109 | trampoline = get_plt_entry(addr, mod->arch.ftrace_trampoline); | 109 | dst = mod->arch.ftrace_trampoline; |
| 110 | if (memcmp(mod->arch.ftrace_trampoline, &trampoline, | 110 | trampoline = get_plt_entry(addr, dst); |
| 111 | sizeof(trampoline))) { | 111 | if (memcmp(dst, &trampoline, sizeof(trampoline))) { |
| 112 | if (plt_entry_is_initialized(mod->arch.ftrace_trampoline)) { | 112 | if (plt_entry_is_initialized(dst)) { |
| 113 | pr_err("ftrace: far branches to multiple entry points unsupported inside a single module\n"); | 113 | pr_err("ftrace: far branches to multiple entry points unsupported inside a single module\n"); |
| 114 | return -EINVAL; | 114 | return -EINVAL; |
| 115 | } | 115 | } |
| 116 | 116 | ||
| 117 | /* point the trampoline to our ftrace entry point */ | 117 | /* point the trampoline to our ftrace entry point */ |
| 118 | module_disable_ro(mod); | 118 | module_disable_ro(mod); |
| 119 | *mod->arch.ftrace_trampoline = trampoline; | 119 | *dst = trampoline; |
| 120 | module_enable_ro(mod, true); | 120 | module_enable_ro(mod, true); |
| 121 | 121 | ||
| 122 | /* update trampoline before patching in the branch */ | 122 | /* |
| 123 | smp_wmb(); | 123 | * Ensure updated trampoline is visible to instruction |
| 124 | * fetch before we patch in the branch. | ||
| 125 | */ | ||
| 126 | __flush_icache_range((unsigned long)&dst[0], | ||
| 127 | (unsigned long)&dst[1]); | ||
| 124 | } | 128 | } |
| 125 | addr = (unsigned long)(void *)mod->arch.ftrace_trampoline; | 129 | addr = (unsigned long)dst; |
| 126 | #else /* CONFIG_ARM64_MODULE_PLTS */ | 130 | #else /* CONFIG_ARM64_MODULE_PLTS */ |
| 127 | return -EINVAL; | 131 | return -EINVAL; |
| 128 | #endif /* CONFIG_ARM64_MODULE_PLTS */ | 132 | #endif /* CONFIG_ARM64_MODULE_PLTS */ |
| @@ -536,13 +536,18 @@ int hw_breakpoint_arch_parse(struct perf_event *bp, · 535 unmodified lines | |||
| 536 | /* Aligned */ | 536 | /* Aligned */ |
| 537 | break; | 537 | break; |
| 538 | case 1: | 538 | case 1: |
| 539 | /* Allow single byte watchpoint. */ | ||
| 540 | if (hw->ctrl.len == ARM_BREAKPOINT_LEN_1) | ||
| 541 | break; | ||
| 542 | case 2: | 539 | case 2: |
| 543 | /* Allow halfword watchpoints and breakpoints. */ | 540 | /* Allow halfword watchpoints and breakpoints. */ |
| 544 | if (hw->ctrl.len == ARM_BREAKPOINT_LEN_2) | 541 | if (hw->ctrl.len == ARM_BREAKPOINT_LEN_2) |
| 545 | break; | 542 | break; |
| 543 | |||
| 544 | /* Fallthrough */ | ||
| 545 | case 3: | ||
| 546 | /* Allow single byte watchpoint. */ | ||
| 547 | if (hw->ctrl.len == ARM_BREAKPOINT_LEN_1) | ||
| 548 | break; | ||
| 549 | |||
| 550 | /* Fallthrough */ | ||
| 546 | default: | 551 | default: |
| 547 | return -EINVAL; | 552 | return -EINVAL; |
| 548 | } | 553 | } |
| @@ -314,18 +314,21 @@ int apply_relocate_add(Elf64_Shdr *sechdrs, · 313 unmodified lines | |||
| 314 | /* MOVW instruction relocations. */ | 314 | /* MOVW instruction relocations. */ |
| 315 | case R_AARCH64_MOVW_UABS_G0_NC: | 315 | case R_AARCH64_MOVW_UABS_G0_NC: |
| 316 | overflow_check = false; | 316 | overflow_check = false; |
| 317 | /* Fall through */ | ||
| 317 | case R_AARCH64_MOVW_UABS_G0: | 318 | case R_AARCH64_MOVW_UABS_G0: |
| 318 | ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0, | 319 | ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0, |
| 319 | AARCH64_INSN_IMM_MOVKZ); | 320 | AARCH64_INSN_IMM_MOVKZ); |
| 320 | break; | 321 | break; |
| 321 | case R_AARCH64_MOVW_UABS_G1_NC: | 322 | case R_AARCH64_MOVW_UABS_G1_NC: |
| 322 | overflow_check = false; | 323 | overflow_check = false; |
| 324 | /* Fall through */ | ||
| 323 | case R_AARCH64_MOVW_UABS_G1: | 325 | case R_AARCH64_MOVW_UABS_G1: |
| 324 | ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16, | 326 | ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16, |
| 325 | AARCH64_INSN_IMM_MOVKZ); | 327 | AARCH64_INSN_IMM_MOVKZ); |
| 326 | break; | 328 | break; |
| 327 | case R_AARCH64_MOVW_UABS_G2_NC: | 329 | case R_AARCH64_MOVW_UABS_G2_NC: |
| 328 | overflow_check = false; | 330 | overflow_check = false; |
| 331 | /* Fall through */ | ||
| 329 | case R_AARCH64_MOVW_UABS_G2: | 332 | case R_AARCH64_MOVW_UABS_G2: |
| 330 | ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32, | 333 | ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32, |
| 331 | AARCH64_INSN_IMM_MOVKZ); | 334 | AARCH64_INSN_IMM_MOVKZ); |
| @@ -393,6 +396,7 @@ int apply_relocate_add(Elf64_Shdr *sechdrs, · 61 unmodified lines | |||
| 393 | break; | 396 | break; |
| 394 | case R_AARCH64_ADR_PREL_PG_HI21_NC: | 397 | case R_AARCH64_ADR_PREL_PG_HI21_NC: |
| 395 | overflow_check = false; | 398 | overflow_check = false; |
| 399 | /* Fall through */ | ||
| 396 | case R_AARCH64_ADR_PREL_PG_HI21: | 400 | case R_AARCH64_ADR_PREL_PG_HI21: |
| 397 | ovf = reloc_insn_adrp(me, sechdrs, loc, val); | 401 | ovf = reloc_insn_adrp(me, sechdrs, loc, val); |
| 398 | if (ovf && ovf != -ERANGE) | 402 | if (ovf && ovf != -ERANGE) |
| @@ -154,12 +154,7 @@ void perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, · 153 unmodified lines | |||
| 154 | return; | 154 | return; |
| 155 | } | 155 | } |
| 156 | 156 | ||
| 157 | frame.fp = regs->regs[29]; | 157 | start_backtrace(&frame, regs->regs[29], regs->pc); |
| 158 | frame.pc = regs->pc; | ||
| 159 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER | ||
| 160 | frame.graph = 0; | ||
| 161 | #endif | ||
| 162 | |||
| 163 | walk_stackframe(current, &frame, callchain_trace, entry); | 158 | walk_stackframe(current, &frame, callchain_trace, entry); |
| 164 | } | 159 | } |
| 165 | 160 | ||
| @@ -21,6 +21,7 @@ · 20 unmodified lines | |||
| 21 | #include <asm/ptrace.h> | 21 | #include <asm/ptrace.h> |
| 22 | #include <asm/cacheflush.h> | 22 | #include <asm/cacheflush.h> |
| 23 | #include <asm/debug-monitors.h> | 23 | #include <asm/debug-monitors.h> |
| 24 | #include <asm/daifflags.h> | ||
| 24 | #include <asm/system_misc.h> | 25 | #include <asm/system_misc.h> |
| 25 | #include <asm/insn.h> | 26 | #include <asm/insn.h> |
| 26 | #include <linux/uaccess.h> | 27 | #include <linux/uaccess.h> |
| @@ -167,33 +168,6 @@ static void __kprobes set_current_kprobe(struct kprobe *p) · 140 unmodified lines | |||
| 167 | __this_cpu_write(current_kprobe, p); | 168 | __this_cpu_write(current_kprobe, p); |
| 168 | } | 169 | } |
| 169 | 170 | ||
| 170 | /* | ||
| 171 | * When PSTATE.D is set (masked), then software step exceptions can not be | ||
| 172 | * generated. | ||
| 173 | * SPSR's D bit shows the value of PSTATE.D immediately before the | ||
| 174 | * exception was taken. PSTATE.D is set while entering into any exception | ||
| 175 | * mode, however software clears it for any normal (none-debug-exception) | ||
| 176 | * mode in the exception entry. Therefore, when we are entering into kprobe | ||
| 177 | * breakpoint handler from any normal mode then SPSR.D bit is already | ||
| 178 | * cleared, however it is set when we are entering from any debug exception | ||
| 179 | * mode. | ||
| 180 | * Since we always need to generate single step exception after a kprobe | ||
| 181 | * breakpoint exception therefore we need to clear it unconditionally, when | ||
| 182 | * we become sure that the current breakpoint exception is for kprobe. | ||
| 183 | */ | ||
| 184 | static void __kprobes | ||
| 185 | spsr_set_debug_flag(struct pt_regs *regs, int mask) | ||
| 186 | { | ||
| 187 | unsigned long spsr = regs->pstate; | ||
| 188 | |||
| 189 | if (mask) | ||
| 190 | spsr |= PSR_D_BIT; | ||
| 191 | else | ||
| 192 | spsr &= ~PSR_D_BIT; | ||
| 193 | |||
| 194 | regs->pstate = spsr; | ||
| 195 | } | ||
| 196 | |||
| 197 | /* | 171 | /* |
| 198 | * Interrupts need to be disabled before single-step mode is set, and not | 172 | * Interrupts need to be disabled before single-step mode is set, and not |
| 199 | * reenabled until after single-step mode ends. | 173 | * reenabled until after single-step mode ends. |
| @@ -205,17 +179,17 @@ spsr_set_debug_flag(struct pt_regs *regs, int mask) · 5 unmodified lines | |||
| 205 | static void __kprobes kprobes_save_local_irqflag(struct kprobe_ctlblk *kcb, | 179 | static void __kprobes kprobes_save_local_irqflag(struct kprobe_ctlblk *kcb, |
| 206 | struct pt_regs *regs) | 180 | struct pt_regs *regs) |
| 207 | { | 181 | { |
| 208 | kcb->saved_irqflag = regs->pstate; | 182 | kcb->saved_irqflag = regs->pstate & DAIF_MASK; |
| 209 | regs->pstate |= PSR_I_BIT; | 183 | regs->pstate |= PSR_I_BIT; |
| 184 | /* Unmask PSTATE.D for enabling software step exceptions. */ | ||
| 185 | regs->pstate &= ~PSR_D_BIT; | ||
| 210 | } | 186 | } |
| 211 | 187 | ||
| 212 | static void __kprobes kprobes_restore_local_irqflag(struct kprobe_ctlblk *kcb, | 188 | static void __kprobes kprobes_restore_local_irqflag(struct kprobe_ctlblk *kcb, |
| 213 | struct pt_regs *regs) | 189 | struct pt_regs *regs) |
| 214 | { | 190 | { |
| 215 | if (kcb->saved_irqflag & PSR_I_BIT) | 191 | regs->pstate &= ~DAIF_MASK; |
| 216 | regs->pstate |= PSR_I_BIT; | 192 | regs->pstate |= kcb->saved_irqflag; |
| 217 | else | ||
| 218 | regs->pstate &= ~PSR_I_BIT; | ||
| 219 | } | 193 | } |
| 220 | 194 | ||
| 221 | static void __kprobes | 195 | static void __kprobes |
| @@ -252,8 +226,6 @@ static void __kprobes setup_singlestep(struct kprobe *p, · 30 unmodified lines | |||
| 252 | 226 | ||
| 253 | set_ss_context(kcb, slot); /* mark pending ss */ | 227 | set_ss_context(kcb, slot); /* mark pending ss */ |
| 254 | 228 | ||
| 255 | spsr_set_debug_flag(regs, 0); | ||
| 256 | |||
| 257 | /* IRQs and single stepping do not mix well. */ | 229 | /* IRQs and single stepping do not mix well. */ |
| 258 | kprobes_save_local_irqflag(kcb, regs); | 230 | kprobes_save_local_irqflag(kcb, regs); |
| 259 | kernel_enable_single_step(regs); | 231 | kernel_enable_single_step(regs); |
| @@ -398,7 +398,7 @@ int copy_thread(unsigned long clone_flags, unsigned long stack_start, · 397 unmodified lines | |||
| 398 | childregs->pstate |= PSR_UAO_BIT; | 398 | childregs->pstate |= PSR_UAO_BIT; |
| 399 | 399 | ||
| 400 | if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) | 400 | if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) |
| 401 | childregs->pstate |= PSR_SSBS_BIT; | 401 | set_ssbs_bit(childregs); |
| 402 | 402 | ||
| 403 | if (system_uses_irq_prio_masking()) | 403 | if (system_uses_irq_prio_masking()) |
| 404 | childregs->pmr_save = GIC_PRIO_IRQON; | 404 | childregs->pmr_save = GIC_PRIO_IRQON; |
| @@ -442,6 +442,32 @@ void uao_thread_switch(struct task_struct *next) · 37 unmodified lines | |||
| 442 | } | 442 | } |
| 443 | } | 443 | } |
| 444 | 444 | ||
| 445 | /* | ||
| 446 | * Force SSBS state on context-switch, since it may be lost after migrating | ||
| 447 | * from a CPU which treats the bit as RES0 in a heterogeneous system. | ||
| 448 | */ | ||
| 449 | static void ssbs_thread_switch(struct task_struct *next) | ||
| 450 | { | ||
| 451 | struct pt_regs *regs = task_pt_regs(next); | ||
| 452 | |||
| 453 | /* | ||
| 454 | * Nothing to do for kernel threads, but 'regs' may be junk | ||
| 455 | * (e.g. idle task) so check the flags and bail early. | ||
| 456 | */ | ||
| 457 | if (unlikely(next->flags & PF_KTHREAD)) | ||
| 458 | return; | ||
| 459 | |||
| 460 | /* If the mitigation is enabled, then we leave SSBS clear. */ | ||
| 461 | if ((arm64_get_ssbd_state() == ARM64_SSBD_FORCE_ENABLE) || | ||
| 462 | test_tsk_thread_flag(next, TIF_SSBD)) | ||
| 463 | return; | ||
| 464 | |||
| 465 | if (compat_user_mode(regs)) | ||
| 466 | set_compat_ssbs_bit(regs); | ||
| 467 | else if (user_mode(regs)) | ||
| 468 | set_ssbs_bit(regs); | ||
| 469 | } | ||
| 470 | |||
| 445 | /* | 471 | /* |
| 446 | * We store our current task in sp_el0, which is clobbered by userspace. Keep a | 472 | * We store our current task in sp_el0, which is clobbered by userspace. Keep a |
| 447 | * shadow copy so that we can restore this upon entry from userspace. | 473 | * shadow copy so that we can restore this upon entry from userspace. |
| @@ -471,6 +497,7 @@ __notrace_funcgraph struct task_struct *__switch_to(struct task_struct *prev, · 23 unmodified lines | |||
| 471 | entry_task_switch(next); | 497 | entry_task_switch(next); |
| 472 | uao_thread_switch(next); | 498 | uao_thread_switch(next); |
| 473 | ptrauth_thread_switch(next); | 499 | ptrauth_thread_switch(next); |
| 500 | ssbs_thread_switch(next); | ||
| 474 | 501 | ||
| 475 | /* | 502 | /* |
| 476 | * Complete any pending TLB or cache maintenance on this CPU in case | 503 | * Complete any pending TLB or cache maintenance on this CPU in case |
| @@ -498,11 +525,8 @@ unsigned long get_wchan(struct task_struct *p) · 21 unmodified lines | |||
| 498 | if (!stack_page) | 525 | if (!stack_page) |
| 499 | return 0; | 526 | return 0; |
| 500 | 527 | ||
| 501 | frame.fp = thread_saved_fp(p); | 528 | start_backtrace(&frame, thread_saved_fp(p), thread_saved_pc(p)); |
| 502 | frame.pc = thread_saved_pc(p); | 529 | |
| 503 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER | ||
| 504 | frame.graph = 0; | ||
| 505 | #endif | ||
| 506 | do { | 530 | do { |
| 507 | if (unwind_frame(p, &frame)) | 531 | if (unwind_frame(p, &frame)) |
| 508 | goto out; | 532 | goto out; |
| @@ -8,6 +8,7 @@ · 7 unmodified lines | |||
| 8 | 8 | ||
| 9 | #include <linux/export.h> | 9 | #include <linux/export.h> |
| 10 | #include <linux/ftrace.h> | 10 | #include <linux/ftrace.h> |
| 11 | #include <linux/kprobes.h> | ||
| 11 | 12 | ||
| 12 | #include <asm/stack_pointer.h> | 13 | #include <asm/stack_pointer.h> |
| 13 | #include <asm/stacktrace.h> | 14 | #include <asm/stacktrace.h> |
| @@ -29,6 +30,7 @@ static int save_return_addr(struct stackframe *frame, void *d) · 15 unmodified lines | |||
| 29 | return 0; | 30 | return 0; |
| 30 | } | 31 | } |
| 31 | } | 32 | } |
| 33 | NOKPROBE_SYMBOL(save_return_addr); | ||
| 32 | 34 | ||
| 33 | void *return_address(unsigned int level) | 35 | void *return_address(unsigned int level) |
| 34 | { | 36 | { |
| @@ -38,12 +40,9 @@ void *return_address(unsigned int level) · 3 unmodified lines | |||
| 38 | data.level = level + 2; | 40 | data.level = level + 2; |
| 39 | data.addr = NULL; | 41 | data.addr = NULL; |
| 40 | 42 | ||
| 41 | frame.fp = (unsigned long)__builtin_frame_address(0); | 43 | start_backtrace(&frame, |
| 42 | frame.pc = (unsigned long)return_address; /* dummy */ | 44 | (unsigned long)__builtin_frame_address(0), |
| 43 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER | 45 | (unsigned long)return_address); |
| 44 | frame.graph = 0; | ||
| 45 | #endif | ||
| 46 | |||
| 47 | walk_stackframe(current, &frame, save_return_addr, &data); | 46 | walk_stackframe(current, &frame, save_return_addr, &data); |
| 48 | 47 | ||
| 49 | if (!data.level) | 48 | if (!data.level) |
| @@ -52,3 +51,4 @@ void *return_address(unsigned int level) · 2 unmodified lines | |||
| 52 | return NULL; | 51 | return NULL; |
| 53 | } | 52 | } |
| 54 | EXPORT_SYMBOL_GPL(return_address); | 53 | EXPORT_SYMBOL_GPL(return_address); |
| 54 | NOKPROBE_SYMBOL(return_address); | ||
| @@ -152,8 +152,8 @@ int __cpu_up(unsigned int cpu, struct task_struct *idle) · 151 unmodified lines | |||
| 152 | pr_crit("CPU%u: died during early boot\n", cpu); | 152 | pr_crit("CPU%u: died during early boot\n", cpu); |
| 153 | break; | 153 | break; |
| 154 | } | 154 | } |
| 155 | /* Fall through */ | ||
| 156 | pr_crit("CPU%u: may not have shut down cleanly\n", cpu); | 155 | pr_crit("CPU%u: may not have shut down cleanly\n", cpu); |
| 156 | /* Fall through */ | ||
| 157 | case CPU_STUCK_IN_KERNEL: | 157 | case CPU_STUCK_IN_KERNEL: |
| 158 | pr_crit("CPU%u: is stuck in kernel\n", cpu); | 158 | pr_crit("CPU%u: is stuck in kernel\n", cpu); |
| 159 | if (status & CPU_STUCK_REASON_52_BIT_VA) | 159 | if (status & CPU_STUCK_REASON_52_BIT_VA) |
| @@ -7,6 +7,7 @@ · 6 unmodified lines | |||
| 7 | #include <linux/kernel.h> | 7 | #include <linux/kernel.h> |
| 8 | #include <linux/export.h> | 8 | #include <linux/export.h> |
| 9 | #include <linux/ftrace.h> | 9 | #include <linux/ftrace.h> |
| 10 | #include <linux/kprobes.h> | ||
| 10 | #include <linux/sched.h> | 11 | #include <linux/sched.h> |
| 11 | #include <linux/sched/debug.h> | 12 | #include <linux/sched/debug.h> |
| 12 | #include <linux/sched/task_stack.h> | 13 | #include <linux/sched/task_stack.h> |
| @@ -29,9 +30,18 @@ · 16 unmodified lines | |||
| 29 | * ldp x29, x30, [sp] | 30 | * ldp x29, x30, [sp] |
| 30 | * add sp, sp, #0x10 | 31 | * add sp, sp, #0x10 |
| 31 | */ | 32 | */ |
| 33 | |||
| 34 | /* | ||
| 35 | * Unwind from one frame record (A) to the next frame record (B). | ||
| 36 | * | ||
| 37 | * We terminate early if the location of B indicates a malformed chain of frame | ||
| 38 | * records (e.g. a cycle), determined based on the location and fp value of A | ||
| 39 | * and the location (but not the fp value) of B. | ||
| 40 | */ | ||
| 32 | int notrace unwind_frame(struct task_struct *tsk, struct stackframe *frame) | 41 | int notrace unwind_frame(struct task_struct *tsk, struct stackframe *frame) |
| 33 | { | 42 | { |
| 34 | unsigned long fp = frame->fp; | 43 | unsigned long fp = frame->fp; |
| 44 | struct stack_info info; | ||
| 35 | 45 | ||
| 36 | if (fp & 0xf) | 46 | if (fp & 0xf) |
| 37 | return -EINVAL; | 47 | return -EINVAL; |
| @@ -39,11 +49,40 @@ int notrace unwind_frame(struct task_struct *tsk, struct stackframe *frame) · 1 unmodified line | |||
| 39 | if (!tsk) | 49 | if (!tsk) |
| 40 | tsk = current; | 50 | tsk = current; |
| 41 | 51 | ||
| 42 | if (!on_accessible_stack(tsk, fp, NULL)) | 52 | if (!on_accessible_stack(tsk, fp, &info)) |
| 53 | return -EINVAL; | ||
| 54 | |||
| 55 | if (test_bit(info.type, frame->stacks_done)) | ||
| 43 | return -EINVAL; | 56 | return -EINVAL; |
| 44 | 57 | ||
| 58 | /* | ||
| 59 | * As stacks grow downward, any valid record on the same stack must be | ||
| 60 | * at a strictly higher address than the prior record. | ||
| 61 | * | ||
| 62 | * Stacks can nest in several valid orders, e.g. | ||
| 63 | * | ||
| 64 | * TASK -> IRQ -> OVERFLOW -> SDEI_NORMAL | ||
| 65 | * TASK -> SDEI_NORMAL -> SDEI_CRITICAL -> OVERFLOW | ||
| 66 | * | ||
| 67 | * ... but the nesting itself is strict. Once we transition from one | ||
| 68 | * stack to another, it's never valid to unwind back to that first | ||
| 69 | * stack. | ||
| 70 | */ | ||
| 71 | if (info.type == frame->prev_type) { | ||
| 72 | if (fp <= frame->prev_fp) | ||
| 73 | return -EINVAL; | ||
| 74 | } else { | ||
| 75 | set_bit(frame->prev_type, frame->stacks_done); | ||
| 76 | } | ||
| 77 | |||
| 78 | /* | ||
| 79 | * Record this frame record's values and location. The prev_fp and | ||
| 80 | * prev_type are only meaningful to the next unwind_frame() invocation. | ||
| 81 | */ | ||
| 45 | frame->fp = READ_ONCE_NOCHECK(*(unsigned long *)(fp)); | 82 | frame->fp = READ_ONCE_NOCHECK(*(unsigned long *)(fp)); |
| 46 | frame->pc = READ_ONCE_NOCHECK(*(unsigned long *)(fp + 8)); | 83 | frame->pc = READ_ONCE_NOCHECK(*(unsigned long *)(fp + 8)); |
| 84 | frame->prev_fp = fp; | ||
| 85 | frame->prev_type = info.type; | ||
| 47 | 86 | ||
| 48 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER | 87 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER |
| 49 | if (tsk->ret_stack && | 88 | if (tsk->ret_stack && |
| @@ -73,6 +112,7 @@ int notrace unwind_frame(struct task_struct *tsk, struct stackframe *frame) · 23 unmodified lines | |||
| 73 | 112 | ||
| 74 | return 0; | 113 | return 0; |
| 75 | } | 114 | } |
| 115 | NOKPROBE_SYMBOL(unwind_frame); | ||
| 76 | 116 | ||
| 77 | void notrace walk_stackframe(struct task_struct *tsk, struct stackframe *frame, | 117 | void notrace walk_stackframe(struct task_struct *tsk, struct stackframe *frame, |
| 78 | int (*fn)(struct stackframe *, void *), void *data) | 118 | int (*fn)(struct stackframe *, void *), void *data) |
| @@ -87,6 +127,7 @@ void notrace walk_stackframe(struct task_struct *tsk, struct stackframe *frame, · 8 unmodified lines | |||
| 87 | break; | 127 | break; |
| 88 | } | 128 | } |
| 89 | } | 129 | } |
| 130 | NOKPROBE_SYMBOL(walk_stackframe); | ||
| 90 | 131 | ||
| 91 | #ifdef CONFIG_STACKTRACE | 132 | #ifdef CONFIG_STACKTRACE |
| 92 | struct stack_trace_data { | 133 | struct stack_trace_data { |
| @@ -122,12 +163,7 @@ void save_stack_trace_regs(struct pt_regs *regs, struct stack_trace *trace) · 29 unmodified lines | |||
| 122 | data.skip = trace->skip; | 163 | data.skip = trace->skip; |
| 123 | data.no_sched_functions = 0; | 164 | data.no_sched_functions = 0; |
| 124 | 165 | ||
| 125 | frame.fp = regs->regs[29]; | 166 | start_backtrace(&frame, regs->regs[29], regs->pc); |
| 126 | frame.pc = regs->pc; | ||
| 127 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER | ||
| 128 | frame.graph = 0; | ||
| 129 | #endif | ||
| 130 | |||
| 131 | walk_stackframe(current, &frame, save_trace, &data); | 167 | walk_stackframe(current, &frame, save_trace, &data); |
| 132 | } | 168 | } |
| 133 | EXPORT_SYMBOL_GPL(save_stack_trace_regs); | 169 | EXPORT_SYMBOL_GPL(save_stack_trace_regs); |
| @@ -146,17 +182,15 @@ static noinline void __save_stack_trace(struct task_struct *tsk, · 12 unmodified lines | |||
| 146 | data.no_sched_functions = nosched; | 182 | data.no_sched_functions = nosched; |
| 147 | 183 | ||
| 148 | if (tsk != current) { | 184 | if (tsk != current) { |
| 149 | frame.fp = thread_saved_fp(tsk); | 185 | start_backtrace(&frame, thread_saved_fp(tsk), |
| 150 | frame.pc = thread_saved_pc(tsk); | 186 | thread_saved_pc(tsk)); |
| 151 | } else { | 187 | } else { |
| 152 | /* We don't want this function nor the caller */ | 188 | /* We don't want this function nor the caller */ |
| 153 | data.skip += 2; | 189 | data.skip += 2; |
| 154 | frame.fp = (unsigned long)__builtin_frame_address(0); | 190 | start_backtrace(&frame, |
| 155 | frame.pc = (unsigned long)__save_stack_trace; | 191 | (unsigned long)__builtin_frame_address(0), |
| 192 | (unsigned long)__save_stack_trace); | ||
| 156 | } | 193 | } |
| 157 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER | ||
| 158 | frame.graph = 0; | ||
| 159 | #endif | ||
| 160 | 194 | ||
| 161 | walk_stackframe(tsk, &frame, save_trace, &data); | 195 | walk_stackframe(tsk, &frame, save_trace, &data); |
| 162 | 196 | ||
| @@ -38,11 +38,8 @@ unsigned long profile_pc(struct pt_regs *regs) · 37 unmodified lines | |||
| 38 | if (!in_lock_functions(regs->pc)) | 38 | if (!in_lock_functions(regs->pc)) |
| 39 | return regs->pc; | 39 | return regs->pc; |
| 40 | 40 | ||
| 41 | frame.fp = regs->regs[29]; | 41 | start_backtrace(&frame, regs->regs[29], regs->pc); |
| 42 | frame.pc = regs->pc; | 42 | |
| 43 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER | ||
| 44 | frame.graph = 0; | ||
| 45 | #endif | ||
| 46 | do { | 43 | do { |
| 47 | int ret = unwind_frame(NULL, &frame); | 44 | int ret = unwind_frame(NULL, &frame); |
| 48 | if (ret < 0) | 45 | if (ret < 0) |
| @@ -100,18 +100,17 @@ void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk) · 99 unmodified lines | |||
| 100 | return; | 100 | return; |
| 101 | 101 | ||
| 102 | if (tsk == current) { | 102 | if (tsk == current) { |
| 103 | frame.fp = (unsigned long)__builtin_frame_address(0); | 103 | start_backtrace(&frame, |
| 104 | frame.pc = (unsigned long)dump_backtrace; | 104 | (unsigned long)__builtin_frame_address(0), |
| 105 | (unsigned long)dump_backtrace); | ||
| 105 | } else { | 106 | } else { |
| 106 | /* | 107 | /* |
| 107 | * task blocked in __switch_to | 108 | * task blocked in __switch_to |
| 108 | */ | 109 | */ |
| 109 | frame.fp = thread_saved_fp(tsk); | 110 | start_backtrace(&frame, |
| 110 | frame.pc = thread_saved_pc(tsk); | 111 | thread_saved_fp(tsk), |
| 112 | thread_saved_pc(tsk)); | ||
| 111 | } | 113 | } |
| 112 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER | ||
| 113 | frame.graph = 0; | ||
| 114 | #endif | ||
| 115 | 114 | ||
| 116 | printk("Call trace:\n"); | 115 | printk("Call trace:\n"); |
| 117 | do { | 116 | do { |
| @@ -734,6 +733,7 @@ static const char *esr_class_str[] = { · 616 unmodified lines | |||
| 734 | [ESR_ELx_EC_CP14_LS] = "CP14 LDC/STC", | 733 | [ESR_ELx_EC_CP14_LS] = "CP14 LDC/STC", |
| 735 | [ESR_ELx_EC_FP_ASIMD] = "ASIMD", | 734 | [ESR_ELx_EC_FP_ASIMD] = "ASIMD", |
| 736 | [ESR_ELx_EC_CP10_ID] = "CP10 MRC/VMRS", | 735 | [ESR_ELx_EC_CP10_ID] = "CP10 MRC/VMRS", |
| 736 | [ESR_ELx_EC_PAC] = "PAC", | ||
| 737 | [ESR_ELx_EC_CP14_64] = "CP14 MCRR/MRRC", | 737 | [ESR_ELx_EC_CP14_64] = "CP14 MCRR/MRRC", |
| 738 | [ESR_ELx_EC_ILL] = "PSTATE.IL", | 738 | [ESR_ELx_EC_ILL] = "PSTATE.IL", |
| 739 | [ESR_ELx_EC_SVC32] = "SVC (AArch32)", | 739 | [ESR_ELx_EC_SVC32] = "SVC (AArch32)", |
| @@ -32,10 +32,10 @@ UBSAN_SANITIZE := n · 31 unmodified lines | |||
| 32 | OBJECT_FILES_NON_STANDARD := y | 32 | OBJECT_FILES_NON_STANDARD := y |
| 33 | KCOV_INSTRUMENT := n | 33 | KCOV_INSTRUMENT := n |
| 34 | 34 | ||
| 35 | ifeq ($(c-gettimeofday-y),) | ||
| 36 | CFLAGS_vgettimeofday.o = -O2 -mcmodel=tiny | 35 | CFLAGS_vgettimeofday.o = -O2 -mcmodel=tiny |
| 37 | else | 36 | |
| 38 | CFLAGS_vgettimeofday.o = -O2 -mcmodel=tiny -include $(c-gettimeofday-y) | 37 | ifneq ($(c-gettimeofday-y),) |
| 38 | CFLAGS_vgettimeofday.o += -include $(c-gettimeofday-y) | ||
| 39 | endif | 39 | endif |
| 40 | 40 | ||
| 41 | # Clang versions less than 8 do not support -mcmodel=tiny | 41 | # Clang versions less than 8 do not support -mcmodel=tiny |
| @@ -57,8 +57,7 @@ $(obj)/vdso.o : $(obj)/vdso.so · 15 unmodified lines | |||
| 57 | 57 | ||
| 58 | # Link rule for the .so file, .lds has to be first | 58 | # Link rule for the .so file, .lds has to be first |
| 59 | $(obj)/vdso.so.dbg: $(obj)/vdso.lds $(obj-vdso) FORCE | 59 | $(obj)/vdso.so.dbg: $(obj)/vdso.lds $(obj-vdso) FORCE |
| 60 | $(call if_changed,ld) | 60 | $(call if_changed,vdsold_and_vdso_check) |
| 61 | $(call if_changed,vdso_check) | ||
| 62 | 61 | ||
| 63 | # Strip rule for the .so file | 62 | # Strip rule for the .so file |
| 64 | $(obj)/%.so: OBJCOPYFLAGS := -S | 63 | $(obj)/%.so: OBJCOPYFLAGS := -S |
| @@ -74,8 +73,8 @@ include/generated/vdso-offsets.h: $(obj)/vdso.so.dbg FORCE · 9 unmodified lines | |||
| 74 | $(call if_changed,vdsosym) | 73 | $(call if_changed,vdsosym) |
| 75 | 74 | ||
| 76 | # Actual build commands | 75 | # Actual build commands |
| 77 | quiet_cmd_vdsocc = VDSOCC $@ | 76 | quiet_cmd_vdsold_and_vdso_check = LD $@ |
| 78 | cmd_vdsocc = $(CC) $(a_flags) $(c_flags) -c -o $@ $< | 77 | cmd_vdsold_and_vdso_check = $(cmd_ld); $(cmd_vdso_check) |
| 79 | 78 | ||
| 80 | # Install commands for the unstripped file | 79 | # Install commands for the unstripped file |
| 81 | quiet_cmd_vdso_install = INSTALL $@ | 80 | quiet_cmd_vdso_install = INSTALL $@ |
| @@ -144,8 +144,7 @@ $(obj)/vdso.so.dbg: $(obj)/vdso.so.raw $(obj)/$(munge) FORCE · 143 unmodified lines | |||
| 144 | 144 | ||
| 145 | # Link rule for the .so file, .lds has to be first | 145 | # Link rule for the .so file, .lds has to be first |
| 146 | $(obj)/vdso.so.raw: $(src)/vdso.lds $(obj-vdso) FORCE | 146 | $(obj)/vdso.so.raw: $(src)/vdso.lds $(obj-vdso) FORCE |
| 147 | $(call if_changed,vdsold) | 147 | $(call if_changed,vdsold_and_vdso_check) |
| 148 | $(call if_changed,vdso_check) | ||
| 149 | 148 | ||
| 150 | # Compilation rules for the vDSO sources | 149 | # Compilation rules for the vDSO sources |
| 151 | $(c-obj-vdso): %.o: %.c FORCE | 150 | $(c-obj-vdso): %.o: %.c FORCE |
| @@ -156,14 +155,17 @@ $(asm-obj-vdso): %.o: %.S FORCE · 4 unmodified lines | |||
| 156 | $(call if_changed_dep,vdsoas) | 155 | $(call if_changed_dep,vdsoas) |
| 157 | 156 | ||
| 158 | # Actual build commands | 157 | # Actual build commands |
| 159 | quiet_cmd_vdsold = VDSOL $@ | 158 | quiet_cmd_vdsold_and_vdso_check = LD32 $@ |
| 159 | cmd_vdsold_and_vdso_check = $(cmd_vdsold); $(cmd_vdso_check) | ||
| 160 | |||
| 161 | quiet_cmd_vdsold = LD32 $@ | ||
| 160 | cmd_vdsold = $(COMPATCC) -Wp,-MD,$(depfile) $(VDSO_LDFLAGS) \ | 162 | cmd_vdsold = $(COMPATCC) -Wp,-MD,$(depfile) $(VDSO_LDFLAGS) \ |
| 161 | -Wl,-T $(filter %.lds,$^) $(filter %.o,$^) -o $@ | 163 | -Wl,-T $(filter %.lds,$^) $(filter %.o,$^) -o $@ |
| 162 | quiet_cmd_vdsocc = VDSOC $@ | 164 | quiet_cmd_vdsocc = CC32 $@ |
| 163 | cmd_vdsocc = $(COMPATCC) -Wp,-MD,$(depfile) $(VDSO_CFLAGS) -c -o $@ $< | 165 | cmd_vdsocc = $(COMPATCC) -Wp,-MD,$(depfile) $(VDSO_CFLAGS) -c -o $@ $< |
| 164 | quiet_cmd_vdsocc_gettimeofday = VDSOC_GTD $@ | 166 | quiet_cmd_vdsocc_gettimeofday = CC32 $@ |
| 165 | cmd_vdsocc_gettimeofday = $(COMPATCC) -Wp,-MD,$(depfile) $(VDSO_CFLAGS) $(VDSO_CFLAGS_gettimeofday_o) -c -o $@ $< | 167 | cmd_vdsocc_gettimeofday = $(COMPATCC) -Wp,-MD,$(depfile) $(VDSO_CFLAGS) $(VDSO_CFLAGS_gettimeofday_o) -c -o $@ $< |
| 166 | quiet_cmd_vdsoas = VDSOA $@ | 168 | quiet_cmd_vdsoas = AS32 $@ |
| 167 | cmd_vdsoas = $(COMPATCC) -Wp,-MD,$(depfile) $(VDSO_AFLAGS) -c -o $@ $< | 169 | cmd_vdsoas = $(COMPATCC) -Wp,-MD,$(depfile) $(VDSO_AFLAGS) -c -o $@ $< |
| 168 | 170 | ||
| 169 | quiet_cmd_vdsomunge = MUNGE $@ | 171 | quiet_cmd_vdsomunge = MUNGE $@ |
| @@ -18,40 +18,70 @@ · 17 unmodified lines | |||
| 18 | #define save_debug(ptr,reg,nr) \ | 18 | #define save_debug(ptr,reg,nr) \ |
| 19 | switch (nr) { \ | 19 | switch (nr) { \ |
| 20 | case 15: ptr[15] = read_debug(reg, 15); \ | 20 | case 15: ptr[15] = read_debug(reg, 15); \ |
| 21 | /* Fall through */ \ | ||
| 21 | case 14: ptr[14] = read_debug(reg, 14); \ | 22 | case 14: ptr[14] = read_debug(reg, 14); \ |
| 23 | /* Fall through */ \ | ||
| 22 | case 13: ptr[13] = read_debug(reg, 13); \ | 24 | case 13: ptr[13] = read_debug(reg, 13); \ |
| 25 | /* Fall through */ \ | ||
| 23 | case 12: ptr[12] = read_debug(reg, 12); \ | 26 | case 12: ptr[12] = read_debug(reg, 12); \ |
| 27 | /* Fall through */ \ | ||
| 24 | case 11: ptr[11] = read_debug(reg, 11); \ | 28 | case 11: ptr[11] = read_debug(reg, 11); \ |
| 29 | /* Fall through */ \ | ||
| 25 | case 10: ptr[10] = read_debug(reg, 10); \ | 30 | case 10: ptr[10] = read_debug(reg, 10); \ |
| 31 | /* Fall through */ \ | ||
| 26 | case 9: ptr[9] = read_debug(reg, 9); \ | 32 | case 9: ptr[9] = read_debug(reg, 9); \ |
| 33 | /* Fall through */ \ | ||
| 27 | case 8: ptr[8] = read_debug(reg, 8); \ | 34 | case 8: ptr[8] = read_debug(reg, 8); \ |
| 35 | /* Fall through */ \ | ||
| 28 | case 7: ptr[7] = read_debug(reg, 7); \ | 36 | case 7: ptr[7] = read_debug(reg, 7); \ |
| 37 | /* Fall through */ \ | ||
| 29 | case 6: ptr[6] = read_debug(reg, 6); \ | 38 | case 6: ptr[6] = read_debug(reg, 6); \ |
| 39 | /* Fall through */ \ | ||
| 30 | case 5: ptr[5] = read_debug(reg, 5); \ | 40 | case 5: ptr[5] = read_debug(reg, 5); \ |
| 41 | /* Fall through */ \ | ||
| 31 | case 4: ptr[4] = read_debug(reg, 4); \ | 42 | case 4: ptr[4] = read_debug(reg, 4); \ |
| 43 | /* Fall through */ \ | ||
| 32 | case 3: ptr[3] = read_debug(reg, 3); \ | 44 | case 3: ptr[3] = read_debug(reg, 3); \ |
| 45 | /* Fall through */ \ | ||
| 33 | case 2: ptr[2] = read_debug(reg, 2); \ | 46 | case 2: ptr[2] = read_debug(reg, 2); \ |
| 47 | /* Fall through */ \ | ||
| 34 | case 1: ptr[1] = read_debug(reg, 1); \ | 48 | case 1: ptr[1] = read_debug(reg, 1); \ |
| 49 | /* Fall through */ \ | ||
| 35 | default: ptr[0] = read_debug(reg, 0); \ | 50 | default: ptr[0] = read_debug(reg, 0); \ |
| 36 | } | 51 | } |
| 37 | 52 | ||
| 38 | #define restore_debug(ptr,reg,nr) \ | 53 | #define restore_debug(ptr,reg,nr) \ |
| 39 | switch (nr) { \ | 54 | switch (nr) { \ |
| 40 | case 15: write_debug(ptr[15], reg, 15); \ | 55 | case 15: write_debug(ptr[15], reg, 15); \ |
| 56 | /* Fall through */ \ | ||
| 41 | case 14: write_debug(ptr[14], reg, 14); \ | 57 | case 14: write_debug(ptr[14], reg, 14); \ |
| 58 | /* Fall through */ \ | ||
| 42 | case 13: write_debug(ptr[13], reg, 13); \ | 59 | case 13: write_debug(ptr[13], reg, 13); \ |
| 60 | /* Fall through */ \ | ||
| 43 | case 12: write_debug(ptr[12], reg, 12); \ | 61 | case 12: write_debug(ptr[12], reg, 12); \ |
| 62 | /* Fall through */ \ | ||
| 44 | case 11: write_debug(ptr[11], reg, 11); \ | 63 | case 11: write_debug(ptr[11], reg, 11); \ |
| 64 | /* Fall through */ \ | ||
| 45 | case 10: write_debug(ptr[10], reg, 10); \ | 65 | case 10: write_debug(ptr[10], reg, 10); \ |
| 66 | /* Fall through */ \ | ||
| 46 | case 9: write_debug(ptr[9], reg, 9); \ | 67 | case 9: write_debug(ptr[9], reg, 9); \ |
| 68 | /* Fall through */ \ | ||
| 47 | case 8: write_debug(ptr[8], reg, 8); \ | 69 | case 8: write_debug(ptr[8], reg, 8); \ |
| 70 | /* Fall through */ \ | ||
| 48 | case 7: write_debug(ptr[7], reg, 7); \ | 71 | case 7: write_debug(ptr[7], reg, 7); \ |
| 72 | /* Fall through */ \ | ||
| 49 | case 6: write_debug(ptr[6], reg, 6); \ | 73 | case 6: write_debug(ptr[6], reg, 6); \ |
| 74 | /* Fall through */ \ | ||
| 50 | case 5: write_debug(ptr[5], reg, 5); \ | 75 | case 5: write_debug(ptr[5], reg, 5); \ |
| 76 | /* Fall through */ \ | ||
| 51 | case 4: write_debug(ptr[4], reg, 4); \ | 77 | case 4: write_debug(ptr[4], reg, 4); \ |
| 78 | /* Fall through */ \ | ||
| 52 | case 3: write_debug(ptr[3], reg, 3); \ | 79 | case 3: write_debug(ptr[3], reg, 3); \ |
| 80 | /* Fall through */ \ | ||
| 53 | case 2: write_debug(ptr[2], reg, 2); \ | 81 | case 2: write_debug(ptr[2], reg, 2); \ |
| 82 | /* Fall through */ \ | ||
| 54 | case 1: write_debug(ptr[1], reg, 1); \ | 83 | case 1: write_debug(ptr[1], reg, 1); \ |
| 84 | /* Fall through */ \ | ||
| 55 | default: write_debug(ptr[0], reg, 0); \ | 85 | default: write_debug(ptr[0], reg, 0); \ |
| 56 | } | 86 | } |
| 57 | 87 | ||
| @@ -178,13 +178,18 @@ void vcpu_write_spsr32(struct kvm_vcpu *vcpu, unsigned long v) · 177 unmodified lines | |||
| 178 | switch (spsr_idx) { | 178 | switch (spsr_idx) { |
| 179 | case KVM_SPSR_SVC: | 179 | case KVM_SPSR_SVC: |
| 180 | write_sysreg_el1(v, SYS_SPSR); | 180 | write_sysreg_el1(v, SYS_SPSR); |
| 181 | break; | ||
| 181 | case KVM_SPSR_ABT: | 182 | case KVM_SPSR_ABT: |
| 182 | write_sysreg(v, spsr_abt); | 183 | write_sysreg(v, spsr_abt); |
| 184 | break; | ||
| 183 | case KVM_SPSR_UND: | 185 | case KVM_SPSR_UND: |
| 184 | write_sysreg(v, spsr_und); | 186 | write_sysreg(v, spsr_und); |
| 187 | break; | ||
| 185 | case KVM_SPSR_IRQ: | 188 | case KVM_SPSR_IRQ: |
| 186 | write_sysreg(v, spsr_irq); | 189 | write_sysreg(v, spsr_irq); |
| 190 | break; | ||
| 187 | case KVM_SPSR_FIQ: | 191 | case KVM_SPSR_FIQ: |
| 188 | write_sysreg(v, spsr_fiq); | 192 | write_sysreg(v, spsr_fiq); |
| 193 | break; | ||
| 189 | } | 194 | } |
| 190 | } | 195 | } |
| @@ -632,7 +632,7 @@ static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) · 631 unmodified lines | |||
| 632 | */ | 632 | */ |
| 633 | val = ((pmcr & ~ARMV8_PMU_PMCR_MASK) | 633 | val = ((pmcr & ~ARMV8_PMU_PMCR_MASK) |
| 634 | | (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E); | 634 | | (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E); |
| 635 | __vcpu_sys_reg(vcpu, PMCR_EL0) = val; | 635 | __vcpu_sys_reg(vcpu, r->reg) = val; |
| 636 | } | 636 | } |
| 637 | 637 | ||
| 638 | static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags) | 638 | static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags) |
| @@ -981,13 +981,13 @@ static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, · 342 unmodified lines | |||
| 981 | /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ | 981 | /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ |
| 982 | #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ | 982 | #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ |
| 983 | { SYS_DESC(SYS_DBGBVRn_EL1(n)), \ | 983 | { SYS_DESC(SYS_DBGBVRn_EL1(n)), \ |
| 984 | trap_bvr, reset_bvr, n, 0, get_bvr, set_bvr }, \ | 984 | trap_bvr, reset_bvr, 0, 0, get_bvr, set_bvr }, \ |
| 985 | { SYS_DESC(SYS_DBGBCRn_EL1(n)), \ | 985 | { SYS_DESC(SYS_DBGBCRn_EL1(n)), \ |
| 986 | trap_bcr, reset_bcr, n, 0, get_bcr, set_bcr }, \ | 986 | trap_bcr, reset_bcr, 0, 0, get_bcr, set_bcr }, \ |
| 987 | { SYS_DESC(SYS_DBGWVRn_EL1(n)), \ | 987 | { SYS_DESC(SYS_DBGWVRn_EL1(n)), \ |
| 988 | trap_wvr, reset_wvr, n, 0, get_wvr, set_wvr }, \ | 988 | trap_wvr, reset_wvr, 0, 0, get_wvr, set_wvr }, \ |
| 989 | { SYS_DESC(SYS_DBGWCRn_EL1(n)), \ | 989 | { SYS_DESC(SYS_DBGWCRn_EL1(n)), \ |
| 990 | trap_wcr, reset_wcr, n, 0, get_wcr, set_wcr } | 990 | trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr } |
| 991 | 991 | ||
| 992 | /* Macro to expand the PMEVCNTRn_EL0 register */ | 992 | /* Macro to expand the PMEVCNTRn_EL0 register */ |
| 993 | #define PMU_PMEVCNTR_EL0(n) \ | 993 | #define PMU_PMEVCNTR_EL0(n) \ |
| @@ -1540,7 +1540,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { · 546 unmodified lines | |||
| 1540 | { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, | 1540 | { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, |
| 1541 | { SYS_DESC(SYS_CTR_EL0), access_ctr }, | 1541 | { SYS_DESC(SYS_CTR_EL0), access_ctr }, |
| 1542 | 1542 | ||
| 1543 | { SYS_DESC(SYS_PMCR_EL0), access_pmcr, reset_pmcr, }, | 1543 | { SYS_DESC(SYS_PMCR_EL0), access_pmcr, reset_pmcr, PMCR_EL0 }, |
| 1544 | { SYS_DESC(SYS_PMCNTENSET_EL0), access_pmcnten, reset_unknown, PMCNTENSET_EL0 }, | 1544 | { SYS_DESC(SYS_PMCNTENSET_EL0), access_pmcnten, reset_unknown, PMCNTENSET_EL0 }, |
| 1545 | { SYS_DESC(SYS_PMCNTENCLR_EL0), access_pmcnten, NULL, PMCNTENSET_EL0 }, | 1545 | { SYS_DESC(SYS_PMCNTENCLR_EL0), access_pmcnten, NULL, PMCNTENSET_EL0 }, |
| 1546 | { SYS_DESC(SYS_PMOVSCLR_EL0), access_pmovs, NULL, PMOVSSET_EL0 }, | 1546 | { SYS_DESC(SYS_PMOVSCLR_EL0), access_pmovs, NULL, PMOVSSET_EL0 }, |
| @@ -2254,13 +2254,19 @@ static int emulate_sys_reg(struct kvm_vcpu *vcpu, · 707 unmodified lines | |||
| 2254 | } | 2254 | } |
| 2255 | 2255 | ||
| 2256 | static void reset_sys_reg_descs(struct kvm_vcpu *vcpu, | 2256 | static void reset_sys_reg_descs(struct kvm_vcpu *vcpu, |
| 2257 | const struct sys_reg_desc *table, size_t num) | 2257 | const struct sys_reg_desc *table, size_t num, |
| 2258 | unsigned long *bmap) | ||
| 2258 | { | 2259 | { |
| 2259 | unsigned long i; | 2260 | unsigned long i; |
| 2260 | 2261 | ||
| 2261 | for (i = 0; i < num; i++) | 2262 | for (i = 0; i < num; i++) |
| 2262 | if (table[i].reset) | 2263 | if (table[i].reset) { |
| 2264 | int reg = table[i].reg; | ||
| 2265 | |||
| 2263 | table[i].reset(vcpu, &table[i]); | 2266 | table[i].reset(vcpu, &table[i]); |
| 2267 | if (reg > 0 && reg < NR_SYS_REGS) | ||
| 2268 | set_bit(reg, bmap); | ||
| 2269 | } | ||
| 2264 | } | 2270 | } |
| 2265 | 2271 | ||
| 2266 | /** | 2272 | /** |
| @@ -2774,18 +2780,16 @@ void kvm_reset_sys_regs(struct kvm_vcpu *vcpu) · 507 unmodified lines | |||
| 2774 | { | 2780 | { |
| 2775 | size_t num; | 2781 | size_t num; |
| 2776 | const struct sys_reg_desc *table; | 2782 | const struct sys_reg_desc *table; |
| 2777 | 2783 | DECLARE_BITMAP(bmap, NR_SYS_REGS) = { 0, }; | |
| 2778 | /* Catch someone adding a register without putting in reset entry. */ | ||
| 2779 | memset(&vcpu->arch.ctxt.sys_regs, 0x42, sizeof(vcpu->arch.ctxt.sys_regs)); | ||
| 2780 | 2784 | ||
| 2781 | /* Generic chip reset first (so target could override). */ | 2785 | /* Generic chip reset first (so target could override). */ |
| 2782 | reset_sys_reg_descs(vcpu, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); | 2786 | reset_sys_reg_descs(vcpu, sys_reg_descs, ARRAY_SIZE(sys_reg_descs), bmap); |
| 2783 | 2787 | ||
| 2784 | table = get_target_table(vcpu->arch.target, true, &num); | 2788 | table = get_target_table(vcpu->arch.target, true, &num); |
| 2785 | reset_sys_reg_descs(vcpu, table, num); | 2789 | reset_sys_reg_descs(vcpu, table, num, bmap); |
| 2786 | 2790 | ||
| 2787 | for (num = 1; num < NR_SYS_REGS; num++) { | 2791 | for (num = 1; num < NR_SYS_REGS; num++) { |
| 2788 | if (WARN(__vcpu_sys_reg(vcpu, num) == 0x4242424242424242, | 2792 | if (WARN(!test_bit(num, bmap), |
| 2789 | "Didn't reset __vcpu_sys_reg(%zi)\n", num)) | 2793 | "Didn't reset __vcpu_sys_reg(%zi)\n", num)) |
| 2790 | break; | 2794 | break; |
| 2791 | } | 2795 | } |
| @@ -14,9 +14,7 @@ · 13 unmodified lines | |||
| 14 | pgprot_t arch_dma_mmap_pgprot(struct device *dev, pgprot_t prot, | 14 | pgprot_t arch_dma_mmap_pgprot(struct device *dev, pgprot_t prot, |
| 15 | unsigned long attrs) | 15 | unsigned long attrs) |
| 16 | { | 16 | { |
| 17 | if (!dev_is_dma_coherent(dev) || (attrs & DMA_ATTR_WRITE_COMBINE)) | 17 | return pgprot_writecombine(prot); |
| 18 | return pgprot_writecombine(prot); | ||
| 19 | return prot; | ||
| 20 | } | 18 | } |
| 21 | 19 | ||
| 22 | void arch_sync_dma_for_device(struct device *dev, phys_addr_t paddr, | 20 | void arch_sync_dma_for_device(struct device *dev, phys_addr_t paddr, |
| @@ -777,6 +777,53 @@ void __init hook_debug_fault_code(int nr, · 776 unmodified lines | |||
| 777 | debug_fault_info[nr].name = name; | 777 | debug_fault_info[nr].name = name; |
| 778 | } | 778 | } |
| 779 | 779 | ||
| 780 | /* | ||
| 781 | * In debug exception context, we explicitly disable preemption despite | ||
| 782 | * having interrupts disabled. | ||
| 783 | * This serves two purposes: it makes it much less likely that we would | ||
| 784 | * accidentally schedule in exception context and it will force a warning | ||
| 785 | * if we somehow manage to schedule by accident. | ||
| 786 | */ | ||
| 787 | static void debug_exception_enter(struct pt_regs *regs) | ||
| 788 | { | ||
| 789 | /* | ||
| 790 | * Tell lockdep we disabled irqs in entry.S. Do nothing if they were | ||
| 791 | * already disabled to preserve the last enabled/disabled addresses. | ||
| 792 | */ | ||
| 793 | if (interrupts_enabled(regs)) | ||
| 794 | trace_hardirqs_off(); | ||
| 795 | |||
| 796 | if (user_mode(regs)) { | ||
| 797 | RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU"); | ||
| 798 | } else { | ||
| 799 | /* | ||
| 800 | * We might have interrupted pretty much anything. In | ||
| 801 | * fact, if we're a debug exception, we can even interrupt | ||
| 802 | * NMI processing. We don't want this code makes in_nmi() | ||
| 803 | * to return true, but we need to notify RCU. | ||
| 804 | */ | ||
| 805 | rcu_nmi_enter(); | ||
| 806 | } | ||
| 807 | |||
| 808 | preempt_disable(); | ||
| 809 | |||
| 810 | /* This code is a bit fragile. Test it. */ | ||
| 811 | RCU_LOCKDEP_WARN(!rcu_is_watching(), "exception_enter didn't work"); | ||
| 812 | } | ||
| 813 | NOKPROBE_SYMBOL(debug_exception_enter); | ||
| 814 | |||
| 815 | static void debug_exception_exit(struct pt_regs *regs) | ||
| 816 | { | ||
| 817 | preempt_enable_no_resched(); | ||
| 818 | |||
| 819 | if (!user_mode(regs)) | ||
| 820 | rcu_nmi_exit(); | ||
| 821 | |||
| 822 | if (interrupts_enabled(regs)) | ||
| 823 | trace_hardirqs_on(); | ||
| 824 | } | ||
| 825 | NOKPROBE_SYMBOL(debug_exception_exit); | ||
| 826 | |||
| 780 | #ifdef CONFIG_ARM64_ERRATUM_1463225 | 827 | #ifdef CONFIG_ARM64_ERRATUM_1463225 |
| 781 | DECLARE_PER_CPU(int, __in_cortex_a76_erratum_1463225_wa); | 828 | DECLARE_PER_CPU(int, __in_cortex_a76_erratum_1463225_wa); |
| 782 | 829 | ||
| @@ -817,12 +864,7 @@ asmlinkage void __exception do_debug_exception(unsigned long addr_if_watchpoint, · 34 unmodified lines | |||
| 817 | if (cortex_a76_erratum_1463225_debug_handler(regs)) | 864 | if (cortex_a76_erratum_1463225_debug_handler(regs)) |
| 818 | return; | 865 | return; |
| 819 | 866 | ||
| 820 | /* | 867 | debug_exception_enter(regs); |
| 821 | * Tell lockdep we disabled irqs in entry.S. Do nothing if they were | ||
| 822 | * already disabled to preserve the last enabled/disabled addresses. | ||
| 823 | */ | ||
| 824 | if (interrupts_enabled(regs)) | ||
| 825 | trace_hardirqs_off(); | ||
| 826 | 868 | ||
| 827 | if (user_mode(regs) && !is_ttbr0_addr(pc)) | 869 | if (user_mode(regs) && !is_ttbr0_addr(pc)) |
| 828 | arm64_apply_bp_hardening(); | 870 | arm64_apply_bp_hardening(); |
| @@ -832,7 +874,6 @@ asmlinkage void __exception do_debug_exception(unsigned long addr_if_watchpoint, · 3 unmodified lines | |||
| 832 | inf->sig, inf->code, (void __user *)pc, esr); | 874 | inf->sig, inf->code, (void __user *)pc, esr); |
| 833 | } | 875 | } |
| 834 | 876 | ||
| 835 | if (interrupts_enabled(regs)) | 877 | debug_exception_exit(regs); |
| 836 | trace_hardirqs_on(); | ||
| 837 | } | 878 | } |
| 838 | NOKPROBE_SYMBOL(do_debug_exception); | 879 | NOKPROBE_SYMBOL(do_debug_exception); |
| @@ -1,4 +1,4 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0 */ | 1 | /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ |
| 2 | // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. | 2 | // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. |
| 3 | 3 | ||
| 4 | #ifndef __ASM_CSKY_BYTEORDER_H | 4 | #ifndef __ASM_CSKY_BYTEORDER_H |
| @@ -1,4 +1,4 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0 */ | 1 | /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ |
| 2 | 2 | ||
| 3 | #ifndef __ASM_CSKY_CACHECTL_H | 3 | #ifndef __ASM_CSKY_CACHECTL_H |
| 4 | #define __ASM_CSKY_CACHECTL_H | 4 | #define __ASM_CSKY_CACHECTL_H |
| @@ -1,4 +1,4 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0 */ | 1 | /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ |
| 2 | // Copyright (C) 2019 Hangzhou C-SKY Microsystems co.,ltd. | 2 | // Copyright (C) 2019 Hangzhou C-SKY Microsystems co.,ltd. |
| 3 | 3 | ||
| 4 | #ifndef _ASM_CSKY_PERF_REGS_H | 4 | #ifndef _ASM_CSKY_PERF_REGS_H |
| @@ -1,4 +1,4 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0 */ | 1 | /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ |
| 2 | // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. | 2 | // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. |
| 3 | 3 | ||
| 4 | #ifndef _CSKY_PTRACE_H | 4 | #ifndef _CSKY_PTRACE_H |
| @@ -1,4 +1,4 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0 */ | 1 | /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ |
| 2 | // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. | 2 | // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. |
| 3 | 3 | ||
| 4 | #ifndef __ASM_CSKY_SIGCONTEXT_H | 4 | #ifndef __ASM_CSKY_SIGCONTEXT_H |
| @@ -1,4 +1,4 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0 */ | 1 | /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ |
| 2 | // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. | 2 | // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. |
| 3 | 3 | ||
| 4 | #define __ARCH_WANT_SYS_CLONE | 4 | #define __ARCH_WANT_SYS_CLONE |
| @@ -398,6 +398,7 @@ static int dwc3_octeon_clocks_start(struct device *dev, u64 base) · 397 unmodified lines | |||
| 398 | default: | 398 | default: |
| 399 | dev_err(dev, "Invalid ref_clk %u, using 100000000 instead\n", | 399 | dev_err(dev, "Invalid ref_clk %u, using 100000000 instead\n", |
| 400 | clock_rate); | 400 | clock_rate); |
| 401 | /* fall through */ | ||
| 401 | case 100000000: | 402 | case 100000000: |
| 402 | mpll_mul = 0x19; | 403 | mpll_mul = 0x19; |
| 403 | if (ref_clk_sel < 2) | 404 | if (ref_clk_sel < 2) |
| @@ -69,6 +69,8 @@ static int __populate_cache_leaves(unsigned int cpu) · 68 unmodified lines | |||
| 69 | if (c->tcache.waysize) | 69 | if (c->tcache.waysize) |
| 70 | populate_cache(tcache, this_leaf, 3, CACHE_TYPE_UNIFIED); | 70 | populate_cache(tcache, this_leaf, 3, CACHE_TYPE_UNIFIED); |
| 71 | 71 | ||
| 72 | this_cpu_ci->cpu_map_populated = true; | ||
| 73 | |||
| 72 | return 0; | 74 | return 0; |
| 73 | } | 75 | } |
| 74 | 76 | ||
| @@ -32,7 +32,8 @@ void __init setup_pit_timer(void) · 31 unmodified lines | |||
| 32 | 32 | ||
| 33 | static int __init init_pit_clocksource(void) | 33 | static int __init init_pit_clocksource(void) |
| 34 | { | 34 | { |
| 35 | if (num_possible_cpus() > 1) /* PIT does not scale! */ | 35 | if (num_possible_cpus() > 1 || /* PIT does not scale! */ |
| 36 | !clockevent_state_periodic(&i8253_clockevent)) | ||
| 36 | return 0; | 37 | return 0; |
| 37 | 38 | ||
| 38 | return clocksource_i8253_init(); | 39 | return clocksource_i8253_init(); |
| @@ -140,6 +140,7 @@ static int kvm_compute_return_epc(struct kvm_vcpu *vcpu, unsigned long instpc, · 139 unmodified lines | |||
| 140 | /* These are unconditional and in j_format. */ | 140 | /* These are unconditional and in j_format. */ |
| 141 | case jal_op: | 141 | case jal_op: |
| 142 | arch->gprs[31] = instpc + 8; | 142 | arch->gprs[31] = instpc + 8; |
| 143 | /* fall through */ | ||
| 143 | case j_op: | 144 | case j_op: |
| 144 | epc += 4; | 145 | epc += 4; |
| 145 | epc >>= 28; | 146 | epc >>= 28; |
| @@ -150,16 +150,6 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) · 149 unmodified lines | |||
| 150 | return 0; | 150 | return 0; |
| 151 | } | 151 | } |
| 152 | 152 | ||
| 153 | bool kvm_arch_has_vcpu_debugfs(void) | ||
| 154 | { | ||
| 155 | return false; | ||
| 156 | } | ||
| 157 | |||
| 158 | int kvm_arch_create_vcpu_debugfs(struct kvm_vcpu *vcpu) | ||
| 159 | { | ||
| 160 | return 0; | ||
| 161 | } | ||
| 162 | |||
| 163 | void kvm_mips_free_vcpus(struct kvm *kvm) | 153 | void kvm_mips_free_vcpus(struct kvm *kvm) |
| 164 | { | 154 | { |
| 165 | unsigned int i; | 155 | unsigned int i; |
| @@ -172,12 +172,15 @@ static void mipsxx_cpu_setup(void *args) · 171 unmodified lines | |||
| 172 | case 4: | 172 | case 4: |
| 173 | w_c0_perfctrl3(0); | 173 | w_c0_perfctrl3(0); |
| 174 | w_c0_perfcntr3(reg.counter[3]); | 174 | w_c0_perfcntr3(reg.counter[3]); |
| 175 | /* fall through */ | ||
| 175 | case 3: | 176 | case 3: |
| 176 | w_c0_perfctrl2(0); | 177 | w_c0_perfctrl2(0); |
| 177 | w_c0_perfcntr2(reg.counter[2]); | 178 | w_c0_perfcntr2(reg.counter[2]); |
| 179 | /* fall through */ | ||
| 178 | case 2: | 180 | case 2: |
| 179 | w_c0_perfctrl1(0); | 181 | w_c0_perfctrl1(0); |
| 180 | w_c0_perfcntr1(reg.counter[1]); | 182 | w_c0_perfcntr1(reg.counter[1]); |
| 183 | /* fall through */ | ||
| 181 | case 1: | 184 | case 1: |
| 182 | w_c0_perfctrl0(0); | 185 | w_c0_perfctrl0(0); |
| 183 | w_c0_perfcntr0(reg.counter[0]); | 186 | w_c0_perfcntr0(reg.counter[0]); |
| @@ -195,10 +198,13 @@ static void mipsxx_cpu_start(void *args) · 11 unmodified lines | |||
| 195 | switch (counters) { | 198 | switch (counters) { |
| 196 | case 4: | 199 | case 4: |
| 197 | w_c0_perfctrl3(WHAT | reg.control[3]); | 200 | w_c0_perfctrl3(WHAT | reg.control[3]); |
| 201 | /* fall through */ | ||
| 198 | case 3: | 202 | case 3: |
| 199 | w_c0_perfctrl2(WHAT | reg.control[2]); | 203 | w_c0_perfctrl2(WHAT | reg.control[2]); |
| 204 | /* fall through */ | ||
| 200 | case 2: | 205 | case 2: |
| 201 | w_c0_perfctrl1(WHAT | reg.control[1]); | 206 | w_c0_perfctrl1(WHAT | reg.control[1]); |
| 207 | /* fall through */ | ||
| 202 | case 1: | 208 | case 1: |
| 203 | w_c0_perfctrl0(WHAT | reg.control[0]); | 209 | w_c0_perfctrl0(WHAT | reg.control[0]); |
| 204 | } | 210 | } |
| @@ -215,10 +221,13 @@ static void mipsxx_cpu_stop(void *args) · 10 unmodified lines | |||
| 215 | switch (counters) { | 221 | switch (counters) { |
| 216 | case 4: | 222 | case 4: |
| 217 | w_c0_perfctrl3(0); | 223 | w_c0_perfctrl3(0); |
| 224 | /* fall through */ | ||
| 218 | case 3: | 225 | case 3: |
| 219 | w_c0_perfctrl2(0); | 226 | w_c0_perfctrl2(0); |
| 227 | /* fall through */ | ||
| 220 | case 2: | 228 | case 2: |
| 221 | w_c0_perfctrl1(0); | 229 | w_c0_perfctrl1(0); |
| 230 | /* fall through */ | ||
| 222 | case 1: | 231 | case 1: |
| 223 | w_c0_perfctrl0(0); | 232 | w_c0_perfctrl0(0); |
| 224 | } | 233 | } |
| @@ -236,6 +245,7 @@ static int mipsxx_perfcount_handler(void) · 11 unmodified lines | |||
| 236 | 245 | ||
| 237 | switch (counters) { | 246 | switch (counters) { |
| 238 | #define HANDLE_COUNTER(n) \ | 247 | #define HANDLE_COUNTER(n) \ |
| 248 | /* fall through */ \ | ||
| 239 | case n + 1: \ | 249 | case n + 1: \ |
| 240 | control = r_c0_perfctrl ## n(); \ | 250 | control = r_c0_perfctrl ## n(); \ |
| 241 | counter = r_c0_perfcntr ## n(); \ | 251 | counter = r_c0_perfcntr ## n(); \ |
| @@ -297,12 +307,15 @@ static void reset_counters(void *arg) · 55 unmodified lines | |||
| 297 | case 4: | 307 | case 4: |
| 298 | w_c0_perfctrl3(0); | 308 | w_c0_perfctrl3(0); |
| 299 | w_c0_perfcntr3(0); | 309 | w_c0_perfcntr3(0); |
| 310 | /* fall through */ | ||
| 300 | case 3: | 311 | case 3: |
| 301 | w_c0_perfctrl2(0); | 312 | w_c0_perfctrl2(0); |
| 302 | w_c0_perfcntr2(0); | 313 | w_c0_perfcntr2(0); |
| 314 | /* fall through */ | ||
| 303 | case 2: | 315 | case 2: |
| 304 | w_c0_perfctrl1(0); | 316 | w_c0_perfctrl1(0); |
| 305 | w_c0_perfcntr1(0); | 317 | w_c0_perfcntr1(0); |
| 318 | /* fall through */ | ||
| 306 | case 1: | 319 | case 1: |
| 307 | w_c0_perfctrl0(0); | 320 | w_c0_perfctrl0(0); |
| 308 | w_c0_perfcntr0(0); | 321 | w_c0_perfcntr0(0); |
| @@ -474,6 +474,7 @@ static int bcm63xx_pcie_can_access(struct pci_bus *bus, int devfn) · 473 unmodified lines | |||
| 474 | if (PCI_SLOT(devfn) == 0) | 474 | if (PCI_SLOT(devfn) == 0) |
| 475 | return bcm_pcie_readl(PCIE_DLSTATUS_REG) | 475 | return bcm_pcie_readl(PCIE_DLSTATUS_REG) |
| 476 | & DLSTATUS_PHYLINKUP; | 476 | & DLSTATUS_PHYLINKUP; |
| 477 | /* else, fall through */ | ||
| 477 | default: | 478 | default: |
| 478 | return false; | 479 | return false; |
| 479 | } | 480 | } |
| @@ -9,6 +9,7 @@ · 8 unmodified lines | |||
| 9 | #if _MIPS_SIM != _MIPS_SIM_ABI64 && defined(CONFIG_64BIT) | 9 | #if _MIPS_SIM != _MIPS_SIM_ABI64 && defined(CONFIG_64BIT) |
| 10 | 10 | ||
| 11 | /* Building 32-bit VDSO for the 64-bit kernel. Fake a 32-bit Kconfig. */ | 11 | /* Building 32-bit VDSO for the 64-bit kernel. Fake a 32-bit Kconfig. */ |
| 12 | #define BUILD_VDSO32_64 | ||
| 12 | #undef CONFIG_64BIT | 13 | #undef CONFIG_64BIT |
| 13 | #define CONFIG_32BIT 1 | 14 | #define CONFIG_32BIT 1 |
| 14 | #ifndef __ASSEMBLY__ | 15 | #ifndef __ASSEMBLY__ |
| @@ -1,4 +1,4 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0 */ | 1 | /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ |
| 2 | // Copyright (C) 2005-2017 Andes Technology Corporation | 2 | // Copyright (C) 2005-2017 Andes Technology Corporation |
| 3 | 3 | ||
| 4 | #ifndef __ASM_AUXVEC_H | 4 | #ifndef __ASM_AUXVEC_H |
| @@ -1,4 +1,4 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0 */ | 1 | /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ |
| 2 | // Copyright (C) 2005-2017 Andes Technology Corporation | 2 | // Copyright (C) 2005-2017 Andes Technology Corporation |
| 3 | 3 | ||
| 4 | #ifndef __NDS32_BYTEORDER_H__ | 4 | #ifndef __NDS32_BYTEORDER_H__ |
| @@ -1,4 +1,4 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0 */ | 1 | /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ |
| 2 | // Copyright (C) 1994, 1995, 1996 by Ralf Baechle | 2 | // Copyright (C) 1994, 1995, 1996 by Ralf Baechle |
| 3 | // Copyright (C) 2005-2017 Andes Technology Corporation | 3 | // Copyright (C) 2005-2017 Andes Technology Corporation |
| 4 | #ifndef _ASM_CACHECTL | 4 | #ifndef _ASM_CACHECTL |
| @@ -1,4 +1,4 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0 */ | 1 | /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ |
| 2 | /* Copyright (C) 2005-2019 Andes Technology Corporation */ | 2 | /* Copyright (C) 2005-2019 Andes Technology Corporation */ |
| 3 | #ifndef _FP_UDF_IEX_CRTL_H | 3 | #ifndef _FP_UDF_IEX_CRTL_H |
| 4 | #define _FP_UDF_IEX_CRTL_H | 4 | #define _FP_UDF_IEX_CRTL_H |
| @@ -1,4 +1,4 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0 */ | 1 | /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ |
| 2 | // Copyright (C) 2005-2017 Andes Technology Corporation | 2 | // Copyright (C) 2005-2017 Andes Technology Corporation |
| 3 | 3 | ||
| 4 | #ifndef __ASM_NDS32_PARAM_H | 4 | #ifndef __ASM_NDS32_PARAM_H |
| @@ -1,4 +1,4 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0 */ | 1 | /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ |
| 2 | // Copyright (C) 2005-2017 Andes Technology Corporation | 2 | // Copyright (C) 2005-2017 Andes Technology Corporation |
| 3 | 3 | ||
| 4 | #ifndef __UAPI_ASM_NDS32_PTRACE_H | 4 | #ifndef __UAPI_ASM_NDS32_PTRACE_H |
| @@ -1,4 +1,4 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0 */ | 1 | /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ |
| 2 | // Copyright (C) 2005-2017 Andes Technology Corporation | 2 | // Copyright (C) 2005-2017 Andes Technology Corporation |
| 3 | 3 | ||
| 4 | #ifndef _ASMNDS32_SIGCONTEXT_H | 4 | #ifndef _ASMNDS32_SIGCONTEXT_H |
| @@ -1,4 +1,4 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0 */ | 1 | /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ |
| 2 | // Copyright (C) 2005-2017 Andes Technology Corporation | 2 | // Copyright (C) 2005-2017 Andes Technology Corporation |
| 3 | 3 | ||
| 4 | #define __ARCH_WANT_STAT64 | 4 | #define __ARCH_WANT_STAT64 |
| @@ -19,8 +19,6 @@ · 18 unmodified lines | |||
| 19 | 19 | ||
| 20 | KBUILD_IMAGE := vmlinuz | 20 | KBUILD_IMAGE := vmlinuz |
| 21 | 21 | ||
| 22 | KBUILD_DEFCONFIG := default_defconfig | ||
| 23 | |||
| 24 | NM = sh $(srctree)/arch/parisc/nm | 22 | NM = sh $(srctree)/arch/parisc/nm |
| 25 | CHECKFLAGS += -D__hppa__=1 | 23 | CHECKFLAGS += -D__hppa__=1 |
| 26 | LIBGCC = $(shell $(CC) $(KBUILD_CFLAGS) -print-libgcc-file-name) | 24 | LIBGCC = $(shell $(CC) $(KBUILD_CFLAGS) -print-libgcc-file-name) |
| @@ -182,5 +180,8 @@ define archhelp · 155 unmodified lines | |||
| 182 | @echo ' zinstall - Install compressed vmlinuz kernel' | 180 | @echo ' zinstall - Install compressed vmlinuz kernel' |
| 183 | endef | 181 | endef |
| 184 | 182 | ||
| 183 | archclean: | ||
| 184 | $(Q)$(MAKE) $(clean)=$(boot) | ||
| 185 | |||
| 185 | archheaders: | 186 | archheaders: |
| 186 | $(Q)$(MAKE) $(build)=arch/parisc/kernel/syscalls all | 187 | $(Q)$(MAKE) $(build)=arch/parisc/kernel/syscalls all |
| @@ -12,6 +12,7 @@ UBSAN_SANITIZE := n · 11 unmodified lines | |||
| 12 | targets := vmlinux.lds vmlinux vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 | 12 | targets := vmlinux.lds vmlinux vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 |
| 13 | targets += vmlinux.bin.xz vmlinux.bin.lzma vmlinux.bin.lzo vmlinux.bin.lz4 | 13 | targets += vmlinux.bin.xz vmlinux.bin.lzma vmlinux.bin.lzo vmlinux.bin.lz4 |
| 14 | targets += misc.o piggy.o sizes.h head.o real2.o firmware.o | 14 | targets += misc.o piggy.o sizes.h head.o real2.o firmware.o |
| 15 | targets += real2.S firmware.c | ||
| 15 | 16 | ||
| 16 | KBUILD_CFLAGS := -D__KERNEL__ -O2 -DBOOTLOADER | 17 | KBUILD_CFLAGS := -D__KERNEL__ -O2 -DBOOTLOADER |
| 17 | KBUILD_CFLAGS += -DDISABLE_BRANCH_PROFILING | 18 | KBUILD_CFLAGS += -DDISABLE_BRANCH_PROFILING |
| @@ -55,7 +56,8 @@ $(obj)/misc.o: $(obj)/sizes.h · 37 unmodified lines | |||
| 55 | CPPFLAGS_vmlinux.lds += -I$(objtree)/$(obj) -DBOOTLOADER | 56 | CPPFLAGS_vmlinux.lds += -I$(objtree)/$(obj) -DBOOTLOADER |
| 56 | $(obj)/vmlinux.lds: $(obj)/sizes.h | 57 | $(obj)/vmlinux.lds: $(obj)/sizes.h |
| 57 | 58 | ||
| 58 | $(obj)/vmlinux.bin: vmlinux | 59 | OBJCOPYFLAGS_vmlinux.bin := -R .comment -R .note -S |
| 60 | $(obj)/vmlinux.bin: vmlinux FORCE | ||
| 59 | $(call if_changed,objcopy) | 61 | $(call if_changed,objcopy) |
| 60 | 62 | ||
| 61 | vmlinux.bin.all-y := $(obj)/vmlinux.bin | 63 | vmlinux.bin.all-y := $(obj)/vmlinux.bin |
| @@ -48,8 +48,8 @@ SECTIONS · 47 unmodified lines | |||
| 48 | *(.rodata.compressed) | 48 | *(.rodata.compressed) |
| 49 | } | 49 | } |
| 50 | 50 | ||
| 51 | /* bootloader code and data starts behind area of extracted kernel */ | 51 | /* bootloader code and data starts at least behind area of extracted kernel */ |
| 52 | . = (SZ_end - SZparisc_kernel_start + KERNEL_BINARY_TEXT_START); | 52 | . = MAX(ABSOLUTE(.), (SZ_end - SZparisc_kernel_start + KERNEL_BINARY_TEXT_START)); |
| 53 | 53 | ||
| 54 | /* align on next page boundary */ | 54 | /* align on next page boundary */ |
| 55 | . = ALIGN(4096); | 55 | . = ALIGN(4096); |
File renamed without changes.
| @@ -50,6 +50,10 @@ struct kprobe_ctlblk { · 49 unmodified lines | |||
| 50 | 50 | ||
| 51 | int __kprobes parisc_kprobe_break_handler(struct pt_regs *regs); | 51 | int __kprobes parisc_kprobe_break_handler(struct pt_regs *regs); |
| 52 | int __kprobes parisc_kprobe_ss_handler(struct pt_regs *regs); | 52 | int __kprobes parisc_kprobe_ss_handler(struct pt_regs *regs); |
| 53 | static inline int kprobe_fault_handler(struct pt_regs *regs, int trapnr) | ||
| 54 | { | ||
| 55 | return 0; | ||
| 56 | } | ||
| 53 | 57 | ||
| 54 | #endif /* CONFIG_KPROBES */ | 58 | #endif /* CONFIG_KPROBES */ |
| 55 | #endif /* _PARISC_KPROBES_H */ | 59 | #endif /* _PARISC_KPROBES_H */ |
| @@ -181,8 +181,9 @@ int ftrace_make_nop(struct module *mod, struct dyn_ftrace *rec, · 180 unmodified lines | |||
| 181 | for (i = 0; i < ARRAY_SIZE(insn); i++) | 181 | for (i = 0; i < ARRAY_SIZE(insn); i++) |
| 182 | insn[i] = INSN_NOP; | 182 | insn[i] = INSN_NOP; |
| 183 | 183 | ||
| 184 | __patch_text((void *)rec->ip, INSN_NOP); | ||
| 184 | __patch_text_multiple((void *)rec->ip + 4 - sizeof(insn), | 185 | __patch_text_multiple((void *)rec->ip + 4 - sizeof(insn), |
| 185 | insn, sizeof(insn)); | 186 | insn, sizeof(insn)-4); |
| 186 | return 0; | 187 | return 0; |
| 187 | } | 188 | } |
| 188 | #endif | 189 | #endif |
| @@ -63,7 +63,7 @@ ENTRY_CFI(flush_tlb_all_local) · 62 unmodified lines | |||
| 63 | 63 | ||
| 64 | /* Flush Instruction Tlb */ | 64 | /* Flush Instruction Tlb */ |
| 65 | 65 | ||
| 66 | LDREG ITLB_SID_BASE(%r1), %r20 | 66 | 88: LDREG ITLB_SID_BASE(%r1), %r20 |
| 67 | LDREG ITLB_SID_STRIDE(%r1), %r21 | 67 | LDREG ITLB_SID_STRIDE(%r1), %r21 |
| 68 | LDREG ITLB_SID_COUNT(%r1), %r22 | 68 | LDREG ITLB_SID_COUNT(%r1), %r22 |
| 69 | LDREG ITLB_OFF_BASE(%r1), %arg0 | 69 | LDREG ITLB_OFF_BASE(%r1), %arg0 |
| @@ -103,6 +103,7 @@ fitonemiddle: /* Loop if LOOP = 1 */ · 33 unmodified lines | |||
| 103 | add %r21, %r20, %r20 /* increment space */ | 103 | add %r21, %r20, %r20 /* increment space */ |
| 104 | 104 | ||
| 105 | fitdone: | 105 | fitdone: |
| 106 | ALTERNATIVE(88b, fitdone, ALT_COND_NO_SPLIT_TLB, INSN_NOP) | ||
| 106 | 107 | ||
| 107 | /* Flush Data Tlb */ | 108 | /* Flush Data Tlb */ |
| 108 | 109 | ||
| @@ -18,3 +18,4 @@ obj-y := frnd.o driver.o decode_exc.o fpudispatch.o denormal.o \ · 17 unmodified lines | |||
| 18 | # other very old or stripped-down PA-RISC CPUs -- not currently supported | 18 | # other very old or stripped-down PA-RISC CPUs -- not currently supported |
| 19 | 19 | ||
| 20 | obj-$(CONFIG_MATH_EMULATION) += unimplemented-math-emulation.o | 20 | obj-$(CONFIG_MATH_EMULATION) += unimplemented-math-emulation.o |
| 21 | CFLAGS_REMOVE_fpudispatch.o = -Wimplicit-fallthrough | ||
| @@ -66,6 +66,7 @@ parisc_acctyp(unsigned long code, unsigned int inst) · 65 unmodified lines | |||
| 66 | case 0x30000000: /* coproc2 */ | 66 | case 0x30000000: /* coproc2 */ |
| 67 | if (bit22set(inst)) | 67 | if (bit22set(inst)) |
| 68 | return VM_WRITE; | 68 | return VM_WRITE; |
| 69 | /* fall through */ | ||
| 69 | 70 | ||
| 70 | case 0x0: /* indexed/memory management */ | 71 | case 0x0: /* indexed/memory management */ |
| 71 | if (bit22set(inst)) { | 72 | if (bit22set(inst)) { |
| @@ -107,22 +107,22 @@ extern void _set_L3CR(unsigned long); · 106 unmodified lines | |||
| 107 | 107 | ||
| 108 | static inline void dcbz(void *addr) | 108 | static inline void dcbz(void *addr) |
| 109 | { | 109 | { |
| 110 | __asm__ __volatile__ ("dcbz %y0" : : "Z"(*(u8 *)addr) : "memory"); | 110 | __asm__ __volatile__ ("dcbz 0, %0" : : "r"(addr) : "memory"); |
| 111 | } | 111 | } |
| 112 | 112 | ||
| 113 | static inline void dcbi(void *addr) | 113 | static inline void dcbi(void *addr) |
| 114 | { | 114 | { |
| 115 | __asm__ __volatile__ ("dcbi %y0" : : "Z"(*(u8 *)addr) : "memory"); | 115 | __asm__ __volatile__ ("dcbi 0, %0" : : "r"(addr) : "memory"); |
| 116 | } | 116 | } |
| 117 | 117 | ||
| 118 | static inline void dcbf(void *addr) | 118 | static inline void dcbf(void *addr) |
| 119 | { | 119 | { |
| 120 | __asm__ __volatile__ ("dcbf %y0" : : "Z"(*(u8 *)addr) : "memory"); | 120 | __asm__ __volatile__ ("dcbf 0, %0" : : "r"(addr) : "memory"); |
| 121 | } | 121 | } |
| 122 | 122 | ||
| 123 | static inline void dcbst(void *addr) | 123 | static inline void dcbst(void *addr) |
| 124 | { | 124 | { |
| 125 | __asm__ __volatile__ ("dcbst %y0" : : "Z"(*(u8 *)addr) : "memory"); | 125 | __asm__ __volatile__ ("dcbst 0, %0" : : "r"(addr) : "memory"); |
| 126 | } | 126 | } |
| 127 | #endif /* !__ASSEMBLY__ */ | 127 | #endif /* !__ASSEMBLY__ */ |
| 128 | #endif /* __KERNEL__ */ | 128 | #endif /* __KERNEL__ */ |
| @@ -302,9 +302,14 @@ · 301 unmodified lines | |||
| 302 | #define H_SCM_UNBIND_MEM 0x3F0 | 302 | #define H_SCM_UNBIND_MEM 0x3F0 |
| 303 | #define H_SCM_QUERY_BLOCK_MEM_BINDING 0x3F4 | 303 | #define H_SCM_QUERY_BLOCK_MEM_BINDING 0x3F4 |
| 304 | #define H_SCM_QUERY_LOGICAL_MEM_BINDING 0x3F8 | 304 | #define H_SCM_QUERY_LOGICAL_MEM_BINDING 0x3F8 |
| 305 | #define H_SCM_MEM_QUERY 0x3FC | 305 | #define H_SCM_UNBIND_ALL 0x3FC |
| 306 | #define H_SCM_BLOCK_CLEAR 0x400 | 306 | #define H_SCM_HEALTH 0x400 |
| 307 | #define MAX_HCALL_OPCODE H_SCM_BLOCK_CLEAR | 307 | #define H_SCM_PERFORMANCE_STATS 0x418 |
| 308 | #define MAX_HCALL_OPCODE H_SCM_PERFORMANCE_STATS | ||
| 309 | |||
| 310 | /* Scope args for H_SCM_UNBIND_ALL */ | ||
| 311 | #define H_UNBIND_SCOPE_ALL (0x1) | ||
| 312 | #define H_UNBIND_SCOPE_DRC (0x2) | ||
| 308 | 313 | ||
| 309 | /* H_VIOCTL functions */ | 314 | /* H_VIOCTL functions */ |
| 310 | #define H_GET_VIOA_DUMP_SIZE 0x01 | 315 | #define H_GET_VIOA_DUMP_SIZE 0x01 |
| @@ -27,11 +27,10 @@ static inline void ppc_set_pmu_inuse(int inuse) · 26 unmodified lines | |||
| 27 | #ifdef CONFIG_PPC_PSERIES | 27 | #ifdef CONFIG_PPC_PSERIES |
| 28 | get_lppaca()->pmcregs_in_use = inuse; | 28 | get_lppaca()->pmcregs_in_use = inuse; |
| 29 | #endif | 29 | #endif |
| 30 | } else { | 30 | } |
| 31 | #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE | 31 | #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE |
| 32 | get_paca()->pmcregs_in_use = inuse; | 32 | get_paca()->pmcregs_in_use = inuse; |
| 33 | #endif | 33 | #endif |
| 34 | } | ||
| 35 | #endif | 34 | #endif |
| 36 | } | 35 | } |
| 37 | 36 | ||
| @@ -49,6 +49,7 @@ · 48 unmodified lines | |||
| 49 | #define __ARCH_WANT_SYS_FORK | 49 | #define __ARCH_WANT_SYS_FORK |
| 50 | #define __ARCH_WANT_SYS_VFORK | 50 | #define __ARCH_WANT_SYS_VFORK |
| 51 | #define __ARCH_WANT_SYS_CLONE | 51 | #define __ARCH_WANT_SYS_CLONE |
| 52 | #define __ARCH_WANT_SYS_CLONE3 | ||
| 52 | 53 | ||
| 53 | #endif /* __ASSEMBLY__ */ | 54 | #endif /* __ASSEMBLY__ */ |
| 54 | #endif /* _ASM_POWERPC_UNISTD_H_ */ | 55 | #endif /* _ASM_POWERPC_UNISTD_H_ */ |
| @@ -1,4 +1,4 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0 */ | 1 | /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ |
| 2 | #ifndef _UAPI__ASM_BPF_PERF_EVENT_H__ | 2 | #ifndef _UAPI__ASM_BPF_PERF_EVENT_H__ |
| 3 | #define _UAPI__ASM_BPF_PERF_EVENT_H__ | 3 | #define _UAPI__ASM_BPF_PERF_EVENT_H__ |
| 4 | 4 | ||
| @@ -31,7 +31,7 @@ · 30 unmodified lines | |||
| 31 | * Struct fields are always 32 or 64 bit aligned, depending on them being 32 | 31 | * Struct fields are always 32 or 64 bit aligned, depending on them being 32 |
| 32 | * or 64 bit wide respectively. | 32 | * or 64 bit wide respectively. |
| 33 | * | 33 | * |
| 34 | * See Documentation/virtual/kvm/ppc-pv.txt | 34 | * See Documentation/virt/kvm/ppc-pv.txt |
| 35 | */ | 35 | */ |
| 36 | struct kvm_vcpu_arch_shared { | 36 | struct kvm_vcpu_arch_shared { |
| 37 | __u64 scratch1; | 37 | __u64 scratch1; |
| @@ -176,9 +176,11 @@ static int emulate_spe(struct pt_regs *regs, unsigned int reg, · 175 unmodified lines | |||
| 176 | ret |= __get_user_inatomic(temp.v[1], p++); | 176 | ret |= __get_user_inatomic(temp.v[1], p++); |
| 177 | ret |= __get_user_inatomic(temp.v[2], p++); | 177 | ret |= __get_user_inatomic(temp.v[2], p++); |
| 178 | ret |= __get_user_inatomic(temp.v[3], p++); | 178 | ret |= __get_user_inatomic(temp.v[3], p++); |
| 179 | /* fall through */ | ||
| 179 | case 4: | 180 | case 4: |
| 180 | ret |= __get_user_inatomic(temp.v[4], p++); | 181 | ret |= __get_user_inatomic(temp.v[4], p++); |
| 181 | ret |= __get_user_inatomic(temp.v[5], p++); | 182 | ret |= __get_user_inatomic(temp.v[5], p++); |
| 183 | /* fall through */ | ||
| 182 | case 2: | 184 | case 2: |
| 183 | ret |= __get_user_inatomic(temp.v[6], p++); | 185 | ret |= __get_user_inatomic(temp.v[6], p++); |
| 184 | ret |= __get_user_inatomic(temp.v[7], p++); | 186 | ret |= __get_user_inatomic(temp.v[7], p++); |
| @@ -259,9 +261,11 @@ static int emulate_spe(struct pt_regs *regs, unsigned int reg, · 74 unmodified lines | |||
| 259 | ret |= __put_user_inatomic(data.v[1], p++); | 261 | ret |= __put_user_inatomic(data.v[1], p++); |
| 260 | ret |= __put_user_inatomic(data.v[2], p++); | 262 | ret |= __put_user_inatomic(data.v[2], p++); |
| 261 | ret |= __put_user_inatomic(data.v[3], p++); | 263 | ret |= __put_user_inatomic(data.v[3], p++); |
| 264 | /* fall through */ | ||
| 262 | case 4: | 265 | case 4: |
| 263 | ret |= __put_user_inatomic(data.v[4], p++); | 266 | ret |= __put_user_inatomic(data.v[4], p++); |
| 264 | ret |= __put_user_inatomic(data.v[5], p++); | 267 | ret |= __put_user_inatomic(data.v[5], p++); |
| 268 | /* fall through */ | ||
| 265 | case 2: | 269 | case 2: |
| 266 | ret |= __put_user_inatomic(data.v[6], p++); | 270 | ret |= __put_user_inatomic(data.v[6], p++); |
| 267 | ret |= __put_user_inatomic(data.v[7], p++); | 271 | ret |= __put_user_inatomic(data.v[7], p++); |
| @@ -597,6 +597,14 @@ ppc_clone: · 596 unmodified lines | |||
| 597 | stw r0,_TRAP(r1) /* register set saved */ | 597 | stw r0,_TRAP(r1) /* register set saved */ |
| 598 | b sys_clone | 598 | b sys_clone |
| 599 | 599 | ||
| 600 | .globl ppc_clone3 | ||
| 601 | ppc_clone3: | ||
| 602 | SAVE_NVGPRS(r1) | ||
| 603 | lwz r0,_TRAP(r1) | ||
| 604 | rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */ | ||
| 605 | stw r0,_TRAP(r1) /* register set saved */ | ||
| 606 | b sys_clone3 | ||
| 607 | |||
| 600 | .globl ppc_swapcontext | 608 | .globl ppc_swapcontext |
| 601 | ppc_swapcontext: | 609 | ppc_swapcontext: |
| 602 | SAVE_NVGPRS(r1) | 610 | SAVE_NVGPRS(r1) |
| @@ -487,6 +487,11 @@ _GLOBAL(ppc_clone) · 486 unmodified lines | |||
| 487 | bl sys_clone | 487 | bl sys_clone |
| 488 | b .Lsyscall_exit | 488 | b .Lsyscall_exit |
| 489 | 489 | ||
| 490 | _GLOBAL(ppc_clone3) | ||
| 491 | bl save_nvgprs | ||
| 492 | bl sys_clone3 | ||
| 493 | b .Lsyscall_exit | ||
| 494 | |||
| 490 | _GLOBAL(ppc32_swapcontext) | 495 | _GLOBAL(ppc32_swapcontext) |
| 491 | bl save_nvgprs | 496 | bl save_nvgprs |
| 492 | bl compat_sys_swapcontext | 497 | bl compat_sys_swapcontext |
| @@ -1531,7 +1531,7 @@ EXC_COMMON(trap_0b_common, 0xb00, unknown_exception) · 1530 unmodified lines | |||
| 1531 | * | 1531 | * |
| 1532 | * Call convention: | 1532 | * Call convention: |
| 1533 | * | 1533 | * |
| 1534 | * syscall register convention is in Documentation/powerpc/syscall64-abi.txt | 1534 | * syscall register convention is in Documentation/powerpc/syscall64-abi.rst |
| 1535 | * | 1535 | * |
| 1536 | * For hypercalls, the register convention is as follows: | 1536 | * For hypercalls, the register convention is as follows: |
| 1537 | * r0 volatile | 1537 | * r0 volatile |
| @@ -1198,6 +1198,9 @@ SYSCALL_DEFINE0(rt_sigreturn) · 1197 unmodified lines | |||
| 1198 | goto bad; | 1198 | goto bad; |
| 1199 | 1199 | ||
| 1200 | if (MSR_TM_ACTIVE(msr_hi<<32)) { | 1200 | if (MSR_TM_ACTIVE(msr_hi<<32)) { |
| 1201 | /* Trying to start TM on non TM system */ | ||
| 1202 | if (!cpu_has_feature(CPU_FTR_TM)) | ||
| 1203 | goto bad; | ||
| 1201 | /* We only recheckpoint on return if we're | 1204 | /* We only recheckpoint on return if we're |
| 1202 | * transaction. | 1205 | * transaction. |
| 1203 | */ | 1206 | */ |
| @@ -771,6 +771,11 @@ SYSCALL_DEFINE0(rt_sigreturn) · 770 unmodified lines | |||
| 771 | if (MSR_TM_ACTIVE(msr)) { | 771 | if (MSR_TM_ACTIVE(msr)) { |
| 772 | /* We recheckpoint on return. */ | 772 | /* We recheckpoint on return. */ |
| 773 | struct ucontext __user *uc_transact; | 773 | struct ucontext __user *uc_transact; |
| 774 | |||
| 775 | /* Trying to start TM on non TM system */ | ||
| 776 | if (!cpu_has_feature(CPU_FTR_TM)) | ||
| 777 | goto badframe; | ||
| 778 | |||
| 774 | if (__get_user(uc_transact, &uc->uc_link)) | 779 | if (__get_user(uc_transact, &uc->uc_link)) |
| 775 | goto badframe; | 780 | goto badframe; |
| 776 | if (restore_tm_sigcontexts(current, &uc->uc_mcontext, | 781 | if (restore_tm_sigcontexts(current, &uc->uc_mcontext, |
| @@ -516,4 +516,4 @@ · 515 unmodified lines | |||
| 516 | 432 common fsmount sys_fsmount | 516 | 432 common fsmount sys_fsmount |
| 517 | 433 common fspick sys_fspick | 517 | 433 common fspick sys_fspick |
| 518 | 434 common pidfd_open sys_pidfd_open | 518 | 434 common pidfd_open sys_pidfd_open |
| 519 | # 435 reserved for clone3 | 519 | 435 nospu clone3 ppc_clone3 |
| @@ -239,6 +239,7 @@ static int kvmppc_mmu_book3s_32_xlate_pte(struct kvm_vcpu *vcpu, gva_t eaddr, · 238 unmodified lines | |||
| 239 | case 2: | 239 | case 2: |
| 240 | case 6: | 240 | case 6: |
| 241 | pte->may_write = true; | 241 | pte->may_write = true; |
| 242 | /* fall through */ | ||
| 242 | case 3: | 243 | case 3: |
| 243 | case 5: | 244 | case 5: |
| 244 | case 7: | 245 | case 7: |
| @@ -3569,9 +3569,18 @@ int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit, · 3568 unmodified lines | |||
| 3569 | mtspr(SPRN_DEC, vcpu->arch.dec_expires - mftb()); | 3569 | mtspr(SPRN_DEC, vcpu->arch.dec_expires - mftb()); |
| 3570 | 3570 | ||
| 3571 | if (kvmhv_on_pseries()) { | 3571 | if (kvmhv_on_pseries()) { |
| 3572 | /* | ||
| 3573 | * We need to save and restore the guest visible part of the | ||
| 3574 | * psscr (i.e. using SPRN_PSSCR_PR) since the hypervisor | ||
| 3575 | * doesn't do this for us. Note only required if pseries since | ||
| 3576 | * this is done in kvmhv_load_hv_regs_and_go() below otherwise. | ||
| 3577 | */ | ||
| 3578 | unsigned long host_psscr; | ||
| 3572 | /* call our hypervisor to load up HV regs and go */ | 3579 | /* call our hypervisor to load up HV regs and go */ |
| 3573 | struct hv_guest_state hvregs; | 3580 | struct hv_guest_state hvregs; |
| 3574 | 3581 | ||
| 3582 | host_psscr = mfspr(SPRN_PSSCR_PR); | ||
| 3583 | mtspr(SPRN_PSSCR_PR, vcpu->arch.psscr); | ||
| 3575 | kvmhv_save_hv_regs(vcpu, &hvregs); | 3584 | kvmhv_save_hv_regs(vcpu, &hvregs); |
| 3576 | hvregs.lpcr = lpcr; | 3585 | hvregs.lpcr = lpcr; |
| 3577 | vcpu->arch.regs.msr = vcpu->arch.shregs.msr; | 3586 | vcpu->arch.regs.msr = vcpu->arch.shregs.msr; |
| @@ -3590,6 +3599,8 @@ int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit, · 12 unmodified lines | |||
| 3590 | vcpu->arch.shregs.msr = vcpu->arch.regs.msr; | 3599 | vcpu->arch.shregs.msr = vcpu->arch.regs.msr; |
| 3591 | vcpu->arch.shregs.dar = mfspr(SPRN_DAR); | 3600 | vcpu->arch.shregs.dar = mfspr(SPRN_DAR); |
| 3592 | vcpu->arch.shregs.dsisr = mfspr(SPRN_DSISR); | 3601 | vcpu->arch.shregs.dsisr = mfspr(SPRN_DSISR); |
| 3602 | vcpu->arch.psscr = mfspr(SPRN_PSSCR_PR); | ||
| 3603 | mtspr(SPRN_PSSCR_PR, host_psscr); | ||
| 3593 | 3604 | ||
| 3594 | /* H_CEDE has to be handled now, not later */ | 3605 | /* H_CEDE has to be handled now, not later */ |
| 3595 | if (trap == BOOK3S_INTERRUPT_SYSCALL && !vcpu->arch.nested && | 3606 | if (trap == BOOK3S_INTERRUPT_SYSCALL && !vcpu->arch.nested && |
| @@ -3654,6 +3665,8 @@ int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit, · 58 unmodified lines | |||
| 3654 | vcpu->arch.vpa.dirty = 1; | 3665 | vcpu->arch.vpa.dirty = 1; |
| 3655 | save_pmu = lp->pmcregs_in_use; | 3666 | save_pmu = lp->pmcregs_in_use; |
| 3656 | } | 3667 | } |
| 3668 | /* Must save pmu if this guest is capable of running nested guests */ | ||
| 3669 | save_pmu |= nesting_enabled(vcpu->kvm); | ||
| 3657 | 3670 | ||
| 3658 | kvmhv_save_guest_pmu(vcpu, save_pmu); | 3671 | kvmhv_save_guest_pmu(vcpu, save_pmu); |
| 3659 | 3672 | ||
| @@ -1986,10 +1986,8 @@ static int kvmppc_xive_create(struct kvm_device *dev, u32 type) · 1985 unmodified lines | |||
| 1986 | 1986 | ||
| 1987 | xive->single_escalation = xive_native_has_single_escalation(); | 1987 | xive->single_escalation = xive_native_has_single_escalation(); |
| 1988 | 1988 | ||
| 1989 | if (ret) { | 1989 | if (ret) |
| 1990 | kfree(xive); | ||
| 1991 | return ret; | 1990 | return ret; |
| 1992 | } | ||
| 1993 | 1991 | ||
| 1994 | return 0; | 1992 | return 0; |
| 1995 | } | 1993 | } |
| @@ -1090,9 +1090,9 @@ static int kvmppc_xive_native_create(struct kvm_device *dev, u32 type) · 1089 unmodified lines | |||
| 1090 | xive->ops = &kvmppc_xive_native_ops; | 1090 | xive->ops = &kvmppc_xive_native_ops; |
| 1091 | 1091 | ||
| 1092 | if (ret) | 1092 | if (ret) |
| 1093 | kfree(xive); | 1093 | return ret; |
| 1094 | 1094 | ||
| 1095 | return ret; | 1095 | return 0; |
| 1096 | } | 1096 | } |
| 1097 | 1097 | ||
| 1098 | /* | 1098 | /* |
| @@ -50,6 +50,11 @@ int kvm_arch_vcpu_runnable(struct kvm_vcpu *v) · 49 unmodified lines | |||
| 50 | return !!(v->arch.pending_exceptions) || kvm_request_pending(v); | 50 | return !!(v->arch.pending_exceptions) || kvm_request_pending(v); |
| 51 | } | 51 | } |
| 52 | 52 | ||
| 53 | bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu) | ||
| 54 | { | ||
| 55 | return kvm_arch_vcpu_runnable(vcpu); | ||
| 56 | } | ||
| 57 | |||
| 53 | bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) | 58 | bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) |
| 54 | { | 59 | { |
| 55 | return false; | 60 | return false; |
| @@ -452,16 +457,6 @@ err_out: · 396 unmodified lines | |||
| 452 | return -EINVAL; | 457 | return -EINVAL; |
| 453 | } | 458 | } |
| 454 | 459 | ||
| 455 | bool kvm_arch_has_vcpu_debugfs(void) | ||
| 456 | { | ||
| 457 | return false; | ||
| 458 | } | ||
| 459 | |||
| 460 | int kvm_arch_create_vcpu_debugfs(struct kvm_vcpu *vcpu) | ||
| 461 | { | ||
| 462 | return 0; | ||
| 463 | } | ||
| 464 | |||
| 465 | void kvm_arch_destroy_vm(struct kvm *kvm) | 460 | void kvm_arch_destroy_vm(struct kvm *kvm) |
| 466 | { | 461 | { |
| 467 | unsigned int i; | 462 | unsigned int i; |
| @@ -1899,11 +1899,20 @@ void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base, · 1898 unmodified lines | |||
| 1899 | * | 1899 | * |
| 1900 | * For guests on platforms before POWER9, we clamp the it limit to 1G | 1900 | * For guests on platforms before POWER9, we clamp the it limit to 1G |
| 1901 | * to avoid some funky things such as RTAS bugs etc... | 1901 | * to avoid some funky things such as RTAS bugs etc... |
| 1902 | * | ||
| 1903 | * On POWER9 we limit to 1TB in case the host erroneously told us that | ||
| 1904 | * the RMA was >1TB. Effective address bits 0:23 are treated as zero | ||
| 1905 | * (meaning the access is aliased to zero i.e. addr = addr % 1TB) | ||
| 1906 | * for virtual real mode addressing and so it doesn't make sense to | ||
| 1907 | * have an area larger than 1TB as it can't be addressed. | ||
| 1902 | */ | 1908 | */ |
| 1903 | if (!early_cpu_has_feature(CPU_FTR_HVMODE)) { | 1909 | if (!early_cpu_has_feature(CPU_FTR_HVMODE)) { |
| 1904 | ppc64_rma_size = first_memblock_size; | 1910 | ppc64_rma_size = first_memblock_size; |
| 1905 | if (!early_cpu_has_feature(CPU_FTR_ARCH_300)) | 1911 | if (!early_cpu_has_feature(CPU_FTR_ARCH_300)) |
| 1906 | ppc64_rma_size = min_t(u64, ppc64_rma_size, 0x40000000); | 1912 | ppc64_rma_size = min_t(u64, ppc64_rma_size, 0x40000000); |
| 1913 | else | ||
| 1914 | ppc64_rma_size = min_t(u64, ppc64_rma_size, | ||
| 1915 | 1UL << SID_SHIFT_1T); | ||
| 1907 | 1916 | ||
| 1908 | /* Finally limit subsequent allocations */ | 1917 | /* Finally limit subsequent allocations */ |
| 1909 | memblock_set_current_limit(ppc64_rma_size); | 1918 | memblock_set_current_limit(ppc64_rma_size); |
| @@ -21,7 +21,7 @@ static void kasan_populate_pte(pte_t *ptep, pgprot_t prot) · 20 unmodified lines | |||
| 21 | __set_pte_at(&init_mm, va, ptep, pfn_pte(PHYS_PFN(pa), prot), 0); | 21 | __set_pte_at(&init_mm, va, ptep, pfn_pte(PHYS_PFN(pa), prot), 0); |
| 22 | } | 22 | } |
| 23 | 23 | ||
| 24 | static int kasan_init_shadow_page_tables(unsigned long k_start, unsigned long k_end) | 24 | static int __ref kasan_init_shadow_page_tables(unsigned long k_start, unsigned long k_end) |
| 25 | { | 25 | { |
| 26 | pmd_t *pmd; | 26 | pmd_t *pmd; |
| 27 | unsigned long k_cur, k_next; | 27 | unsigned long k_cur, k_next; |
| @@ -35,7 +35,10 @@ static int kasan_init_shadow_page_tables(unsigned long k_start, unsigned long k_ · 7 unmodified lines | |||
| 35 | if ((void *)pmd_page_vaddr(*pmd) != kasan_early_shadow_pte) | 35 | if ((void *)pmd_page_vaddr(*pmd) != kasan_early_shadow_pte) |
| 36 | continue; | 36 | continue; |
| 37 | 37 | ||
| 38 | new = pte_alloc_one_kernel(&init_mm); | 38 | if (slab_is_available()) |
| 39 | new = pte_alloc_one_kernel(&init_mm); | ||
| 40 | else | ||
| 41 | new = memblock_alloc(PTE_FRAG_SIZE, PTE_FRAG_SIZE); | ||
| 39 | 42 | ||
| 40 | if (!new) | 43 | if (!new) |
| 41 | return -ENOMEM; | 44 | return -ENOMEM; |
| @@ -239,7 +239,7 @@ void __init paging_init(void) · 238 unmodified lines | |||
| 239 | 239 | ||
| 240 | #ifdef CONFIG_ZONE_DMA | 240 | #ifdef CONFIG_ZONE_DMA |
| 241 | max_zone_pfns[ZONE_DMA] = min(max_low_pfn, | 241 | max_zone_pfns[ZONE_DMA] = min(max_low_pfn, |
| 242 | ((1UL << ARCH_ZONE_DMA_BITS) - 1) >> PAGE_SHIFT); | 242 | 1UL << (ARCH_ZONE_DMA_BITS - PAGE_SHIFT)); |
| 243 | #endif | 243 | #endif |
| 244 | max_zone_pfns[ZONE_NORMAL] = max_low_pfn; | 244 | max_zone_pfns[ZONE_NORMAL] = max_low_pfn; |
| 245 | #ifdef CONFIG_HIGHMEM | 245 | #ifdef CONFIG_HIGHMEM |
| @@ -11,6 +11,7 @@ · 10 unmodified lines | |||
| 11 | #include <linux/sched.h> | 11 | #include <linux/sched.h> |
| 12 | #include <linux/libnvdimm.h> | 12 | #include <linux/libnvdimm.h> |
| 13 | #include <linux/platform_device.h> | 13 | #include <linux/platform_device.h> |
| 14 | #include <linux/delay.h> | ||
| 14 | 15 | ||
| 15 | #include <asm/plpar_wrappers.h> | 16 | #include <asm/plpar_wrappers.h> |
| 16 | 17 | ||
| @@ -43,8 +44,9 @@ struct papr_scm_priv { · 26 unmodified lines | |||
| 43 | static int drc_pmem_bind(struct papr_scm_priv *p) | 44 | static int drc_pmem_bind(struct papr_scm_priv *p) |
| 44 | { | 45 | { |
| 45 | unsigned long ret[PLPAR_HCALL_BUFSIZE]; | 46 | unsigned long ret[PLPAR_HCALL_BUFSIZE]; |
| 46 | uint64_t rc, token; | ||
| 47 | uint64_t saved = 0; | 47 | uint64_t saved = 0; |
| 48 | uint64_t token; | ||
| 49 | int64_t rc; | ||
| 48 | 50 | ||
| 49 | /* | 51 | /* |
| 50 | * When the hypervisor cannot map all the requested memory in a single | 52 | * When the hypervisor cannot map all the requested memory in a single |
| @@ -64,6 +66,10 @@ static int drc_pmem_bind(struct papr_scm_priv *p) · 13 unmodified lines | |||
| 64 | } while (rc == H_BUSY); | 66 | } while (rc == H_BUSY); |
| 65 | 67 | ||
| 66 | if (rc) { | 68 | if (rc) { |
| 69 | /* H_OVERLAP needs a separate error path */ | ||
| 70 | if (rc == H_OVERLAP) | ||
| 71 | return -EBUSY; | ||
| 72 | |||
| 67 | dev_err(&p->pdev->dev, "bind err: %lld\n", rc); | 73 | dev_err(&p->pdev->dev, "bind err: %lld\n", rc); |
| 68 | return -ENXIO; | 74 | return -ENXIO; |
| 69 | } | 75 | } |
| @@ -78,22 +84,36 @@ static int drc_pmem_bind(struct papr_scm_priv *p) · 8 unmodified lines | |||
| 78 | static int drc_pmem_unbind(struct papr_scm_priv *p) | 84 | static int drc_pmem_unbind(struct papr_scm_priv *p) |
| 79 | { | 85 | { |
| 80 | unsigned long ret[PLPAR_HCALL_BUFSIZE]; | 86 | unsigned long ret[PLPAR_HCALL_BUFSIZE]; |
| 81 | uint64_t rc, token; | 87 | uint64_t token = 0; |
| 88 | int64_t rc; | ||
| 82 | 89 | ||
| 83 | token = 0; | 90 | dev_dbg(&p->pdev->dev, "unbind drc %x\n", p->drc_index); |
| 84 | 91 | ||
| 85 | /* NB: unbind has the same retry requirements mentioned above */ | 92 | /* NB: unbind has the same retry requirements as drc_pmem_bind() */ |
| 86 | do { | 93 | do { |
| 87 | rc = plpar_hcall(H_SCM_UNBIND_MEM, ret, p->drc_index, | 94 | |
| 88 | p->bound_addr, p->blocks, token); | 95 | /* Unbind of all SCM resources associated with drcIndex */ |
| 96 | rc = plpar_hcall(H_SCM_UNBIND_ALL, ret, H_UNBIND_SCOPE_DRC, | ||
| 97 | p->drc_index, token); | ||
| 89 | token = ret[0]; | 98 | token = ret[0]; |
| 90 | cond_resched(); | 99 | |
| 100 | /* Check if we are stalled for some time */ | ||
| 101 | if (H_IS_LONG_BUSY(rc)) { | ||
| 102 | msleep(get_longbusy_msecs(rc)); | ||
| 103 | rc = H_BUSY; | ||
| 104 | } else if (rc == H_BUSY) { | ||
| 105 | cond_resched(); | ||
| 106 | } | ||
| 107 | |||
| 91 | } while (rc == H_BUSY); | 108 | } while (rc == H_BUSY); |
| 92 | 109 | ||
| 93 | if (rc) | 110 | if (rc) |
| 94 | dev_err(&p->pdev->dev, "unbind error: %lld\n", rc); | 111 | dev_err(&p->pdev->dev, "unbind error: %lld\n", rc); |
| 112 | else | ||
| 113 | dev_dbg(&p->pdev->dev, "unbind drc %x complete\n", | ||
| 114 | p->drc_index); | ||
| 95 | 115 | ||
| 96 | return !!rc; | 116 | return rc == H_SUCCESS ? 0 : -ENXIO; |
| 97 | } | 117 | } |
| 98 | 118 | ||
| 99 | static int papr_scm_meta_get(struct papr_scm_priv *p, | 119 | static int papr_scm_meta_get(struct papr_scm_priv *p, |
| @@ -255,12 +275,32 @@ static const struct attribute_group *papr_scm_dimm_groups[] = { · 155 unmodified lines | |||
| 255 | NULL, | 275 | NULL, |
| 256 | }; | 276 | }; |
| 257 | 277 | ||
| 278 | static inline int papr_scm_node(int node) | ||
| 279 | { | ||
| 280 | int min_dist = INT_MAX, dist; | ||
| 281 | int nid, min_node; | ||
| 282 | |||
| 283 | if ((node == NUMA_NO_NODE) || node_online(node)) | ||
| 284 | return node; | ||
| 285 | |||
| 286 | min_node = first_online_node; | ||
| 287 | for_each_online_node(nid) { | ||
| 288 | dist = node_distance(node, nid); | ||
| 289 | if (dist < min_dist) { | ||
| 290 | min_dist = dist; | ||
| 291 | min_node = nid; | ||
| 292 | } | ||
| 293 | } | ||
| 294 | return min_node; | ||
| 295 | } | ||
| 296 | |||
| 258 | static int papr_scm_nvdimm_init(struct papr_scm_priv *p) | 297 | static int papr_scm_nvdimm_init(struct papr_scm_priv *p) |
| 259 | { | 298 | { |
| 260 | struct device *dev = &p->pdev->dev; | 299 | struct device *dev = &p->pdev->dev; |
| 261 | struct nd_mapping_desc mapping; | 300 | struct nd_mapping_desc mapping; |
| 262 | struct nd_region_desc ndr_desc; | 301 | struct nd_region_desc ndr_desc; |
| 263 | unsigned long dimm_flags; | 302 | unsigned long dimm_flags; |
| 303 | int target_nid, online_nid; | ||
| 264 | 304 | ||
| 265 | p->bus_desc.ndctl = papr_scm_ndctl; | 305 | p->bus_desc.ndctl = papr_scm_ndctl; |
| 266 | p->bus_desc.module = THIS_MODULE; | 306 | p->bus_desc.module = THIS_MODULE; |
| @@ -299,8 +339,10 @@ static int papr_scm_nvdimm_init(struct papr_scm_priv *p) · 32 unmodified lines | |||
| 299 | 339 | ||
| 300 | memset(&ndr_desc, 0, sizeof(ndr_desc)); | 340 | memset(&ndr_desc, 0, sizeof(ndr_desc)); |
| 301 | ndr_desc.attr_groups = region_attr_groups; | 341 | ndr_desc.attr_groups = region_attr_groups; |
| 302 | ndr_desc.numa_node = dev_to_node(&p->pdev->dev); | 342 | target_nid = dev_to_node(&p->pdev->dev); |
| 303 | ndr_desc.target_node = ndr_desc.numa_node; | 343 | online_nid = papr_scm_node(target_nid); |
| 344 | ndr_desc.numa_node = online_nid; | ||
| 345 | ndr_desc.target_node = target_nid; | ||
| 304 | ndr_desc.res = &p->res; | 346 | ndr_desc.res = &p->res; |
| 305 | ndr_desc.of_node = p->dn; | 347 | ndr_desc.of_node = p->dn; |
| 306 | ndr_desc.provider_data = p; | 348 | ndr_desc.provider_data = p; |
| @@ -318,6 +360,9 @@ static int papr_scm_nvdimm_init(struct papr_scm_priv *p) · 11 unmodified lines | |||
| 318 | ndr_desc.res, p->dn); | 360 | ndr_desc.res, p->dn); |
| 319 | goto err; | 361 | goto err; |
| 320 | } | 362 | } |
| 363 | if (target_nid != online_nid) | ||
| 364 | dev_info(dev, "Region registered with target node %d and online node %d", | ||
| 365 | target_nid, online_nid); | ||
| 321 | 366 | ||
| 322 | return 0; | 367 | return 0; |
| 323 | 368 | ||
| @@ -389,6 +434,14 @@ static int papr_scm_probe(struct platform_device *pdev) · 65 unmodified lines | |||
| 389 | 434 | ||
| 390 | /* request the hypervisor to bind this region to somewhere in memory */ | 435 | /* request the hypervisor to bind this region to somewhere in memory */ |
| 391 | rc = drc_pmem_bind(p); | 436 | rc = drc_pmem_bind(p); |
| 437 | |||
| 438 | /* If phyp says drc memory still bound then force unbound and retry */ | ||
| 439 | if (rc == -EBUSY) { | ||
| 440 | dev_warn(&pdev->dev, "Retrying bind after unbinding\n"); | ||
| 441 | drc_pmem_unbind(p); | ||
| 442 | rc = drc_pmem_bind(p); | ||
| 443 | } | ||
| 444 | |||
| 392 | if (rc) | 445 | if (rc) |
| 393 | goto err; | 446 | goto err; |
| 394 | 447 | ||
| @@ -479,7 +479,7 @@ static int xive_find_target_in_mask(const struct cpumask *mask, · 478 unmodified lines | |||
| 479 | * Now go through the entire mask until we find a valid | 479 | * Now go through the entire mask until we find a valid |
| 480 | * target. | 480 | * target. |
| 481 | */ | 481 | */ |
| 482 | for (;;) { | 482 | do { |
| 483 | /* | 483 | /* |
| 484 | * We re-check online as the fallback case passes us | 484 | * We re-check online as the fallback case passes us |
| 485 | * an untested affinity mask | 485 | * an untested affinity mask |
| @@ -487,12 +487,11 @@ static int xive_find_target_in_mask(const struct cpumask *mask, · 1 unmodified line | |||
| 487 | if (cpu_online(cpu) && xive_try_pick_target(cpu)) | 487 | if (cpu_online(cpu) && xive_try_pick_target(cpu)) |
| 488 | return cpu; | 488 | return cpu; |
| 489 | cpu = cpumask_next(cpu, mask); | 489 | cpu = cpumask_next(cpu, mask); |
| 490 | if (cpu == first) | ||
| 491 | break; | ||
| 492 | /* Wrap around */ | 490 | /* Wrap around */ |
| 493 | if (cpu >= nr_cpu_ids) | 491 | if (cpu >= nr_cpu_ids) |
| 494 | cpu = cpumask_first(mask); | 492 | cpu = cpumask_first(mask); |
| 495 | } | 493 | } while (cpu != first); |
| 494 | |||
| 496 | return -1; | 495 | return -1; |
| 497 | } | 496 | } |
| 498 | 497 | ||
| @@ -21,7 +21,6 @@ · 20 unmodified lines | |||
| 21 | cpus { | 21 | cpus { |
| 22 | #address-cells = <1>; | 22 | #address-cells = <1>; |
| 23 | #size-cells = <0>; | 23 | #size-cells = <0>; |
| 24 | timebase-frequency = <1000000>; | ||
| 25 | cpu0: cpu@0 { | 24 | cpu0: cpu@0 { |
| 26 | compatible = "sifive,e51", "sifive,rocket0", "riscv"; | 25 | compatible = "sifive,e51", "sifive,rocket0", "riscv"; |
| 27 | device_type = "cpu"; | 26 | device_type = "cpu"; |
| @@ -217,5 +216,20 @@ · 189 unmodified lines | |||
| 217 | #size-cells = <0>; | 216 | #size-cells = <0>; |
| 218 | status = "disabled"; | 217 | status = "disabled"; |
| 219 | }; | 218 | }; |
| 219 | eth0: ethernet@10090000 { | ||
| 220 | compatible = "sifive,fu540-c000-gem"; | ||
| 221 | interrupt-parent = <&plic0>; | ||
| 222 | interrupts = <53>; | ||
| 223 | reg = <0x0 0x10090000 0x0 0x2000 | ||
| 224 | 0x0 0x100a0000 0x0 0x1000>; | ||
| 225 | local-mac-address = [00 00 00 00 00 00]; | ||
| 226 | clock-names = "pclk", "hclk"; | ||
| 227 | clocks = <&prci PRCI_CLK_GEMGXLPLL>, | ||
| 228 | <&prci PRCI_CLK_GEMGXLPLL>; | ||
| 229 | #address-cells = <1>; | ||
| 230 | #size-cells = <0>; | ||
| 231 | status = "disabled"; | ||
| 232 | }; | ||
| 233 | |||
| 220 | }; | 234 | }; |
| 221 | }; | 235 | }; |
| @@ -76,3 +76,12 @@ · 75 unmodified lines | |||
| 76 | disable-wp; | 76 | disable-wp; |
| 77 | }; | 77 | }; |
| 78 | }; | 78 | }; |
| 79 | |||
| 80 | ð0 { | ||
| 81 | status = "okay"; | ||
| 82 | phy-mode = "gmii"; | ||
| 83 | phy-handle = <&phy0>; | ||
| 84 | phy0: ethernet-phy@0 { | ||
| 85 | reg = <0>; | ||
| 86 | }; | ||
| 87 | }; | ||
| @@ -34,6 +34,7 @@ CONFIG_PCIEPORTBUS=y · 33 unmodified lines | |||
| 34 | CONFIG_PCI_HOST_GENERIC=y | 34 | CONFIG_PCI_HOST_GENERIC=y |
| 35 | CONFIG_PCIE_XILINX=y | 35 | CONFIG_PCIE_XILINX=y |
| 36 | CONFIG_DEVTMPFS=y | 36 | CONFIG_DEVTMPFS=y |
| 37 | CONFIG_DEVTMPFS_MOUNT=y | ||
| 37 | CONFIG_BLK_DEV_LOOP=y | 38 | CONFIG_BLK_DEV_LOOP=y |
| 38 | CONFIG_VIRTIO_BLK=y | 39 | CONFIG_VIRTIO_BLK=y |
| 39 | CONFIG_BLK_DEV_SD=y | 40 | CONFIG_BLK_DEV_SD=y |
| @@ -53,6 +54,10 @@ CONFIG_SERIAL_8250_CONSOLE=y · 13 unmodified lines | |||
| 53 | CONFIG_SERIAL_OF_PLATFORM=y | 54 | CONFIG_SERIAL_OF_PLATFORM=y |
| 54 | CONFIG_SERIAL_EARLYCON_RISCV_SBI=y | 55 | CONFIG_SERIAL_EARLYCON_RISCV_SBI=y |
| 55 | CONFIG_HVC_RISCV_SBI=y | 56 | CONFIG_HVC_RISCV_SBI=y |
| 57 | CONFIG_HW_RANDOM=y | ||
| 58 | CONFIG_HW_RANDOM_VIRTIO=y | ||
| 59 | CONFIG_SPI=y | ||
| 60 | CONFIG_SPI_SIFIVE=y | ||
| 56 | # CONFIG_PTP_1588_CLOCK is not set | 61 | # CONFIG_PTP_1588_CLOCK is not set |
| 57 | CONFIG_DRM=y | 62 | CONFIG_DRM=y |
| 58 | CONFIG_DRM_RADEON=y | 63 | CONFIG_DRM_RADEON=y |
| @@ -66,8 +71,9 @@ CONFIG_USB_OHCI_HCD=y · 7 unmodified lines | |||
| 66 | CONFIG_USB_OHCI_HCD_PLATFORM=y | 71 | CONFIG_USB_OHCI_HCD_PLATFORM=y |
| 67 | CONFIG_USB_STORAGE=y | 72 | CONFIG_USB_STORAGE=y |
| 68 | CONFIG_USB_UAS=y | 73 | CONFIG_USB_UAS=y |
| 74 | CONFIG_MMC=y | ||
| 75 | CONFIG_MMC_SPI=y | ||
| 69 | CONFIG_VIRTIO_MMIO=y | 76 | CONFIG_VIRTIO_MMIO=y |
| 70 | CONFIG_SPI_SIFIVE=y | ||
| 71 | CONFIG_EXT4_FS=y | 77 | CONFIG_EXT4_FS=y |
| 72 | CONFIG_EXT4_FS_POSIX_ACL=y | 78 | CONFIG_EXT4_FS_POSIX_ACL=y |
| 73 | CONFIG_AUTOFS4_FS=y | 79 | CONFIG_AUTOFS4_FS=y |
| @@ -83,8 +89,4 @@ CONFIG_ROOT_NFS=y · 9 unmodified lines | |||
| 83 | CONFIG_CRYPTO_USER_API_HASH=y | 89 | CONFIG_CRYPTO_USER_API_HASH=y |
| 84 | CONFIG_CRYPTO_DEV_VIRTIO=y | 90 | CONFIG_CRYPTO_DEV_VIRTIO=y |
| 85 | CONFIG_PRINTK_TIME=y | 91 | CONFIG_PRINTK_TIME=y |
| 86 | CONFIG_SPI=y | ||
| 87 | CONFIG_MMC_SPI=y | ||
| 88 | CONFIG_MMC=y | ||
| 89 | CONFIG_DEVTMPFS_MOUNT=y | ||
| 90 | # CONFIG_RCU_TRACE is not set | 92 | # CONFIG_RCU_TRACE is not set |
| @@ -34,6 +34,7 @@ CONFIG_PCIEPORTBUS=y · 33 unmodified lines | |||
| 34 | CONFIG_PCI_HOST_GENERIC=y | 34 | CONFIG_PCI_HOST_GENERIC=y |
| 35 | CONFIG_PCIE_XILINX=y | 35 | CONFIG_PCIE_XILINX=y |
| 36 | CONFIG_DEVTMPFS=y | 36 | CONFIG_DEVTMPFS=y |
| 37 | CONFIG_DEVTMPFS_MOUNT=y | ||
| 37 | CONFIG_BLK_DEV_LOOP=y | 38 | CONFIG_BLK_DEV_LOOP=y |
| 38 | CONFIG_VIRTIO_BLK=y | 39 | CONFIG_VIRTIO_BLK=y |
| 39 | CONFIG_BLK_DEV_SD=y | 40 | CONFIG_BLK_DEV_SD=y |
| @@ -53,6 +54,8 @@ CONFIG_SERIAL_8250_CONSOLE=y · 13 unmodified lines | |||
| 53 | CONFIG_SERIAL_OF_PLATFORM=y | 54 | CONFIG_SERIAL_OF_PLATFORM=y |
| 54 | CONFIG_SERIAL_EARLYCON_RISCV_SBI=y | 55 | CONFIG_SERIAL_EARLYCON_RISCV_SBI=y |
| 55 | CONFIG_HVC_RISCV_SBI=y | 56 | CONFIG_HVC_RISCV_SBI=y |
| 57 | CONFIG_HW_RANDOM=y | ||
| 58 | CONFIG_HW_RANDOM_VIRTIO=y | ||
| 56 | # CONFIG_PTP_1588_CLOCK is not set | 59 | # CONFIG_PTP_1588_CLOCK is not set |
| 57 | CONFIG_DRM=y | 60 | CONFIG_DRM=y |
| 58 | CONFIG_DRM_RADEON=y | 61 | CONFIG_DRM_RADEON=y |
| @@ -22,6 +22,7 @@ generic-y += kvm_para.h · 21 unmodified lines | |||
| 22 | generic-y += local.h | 22 | generic-y += local.h |
| 23 | generic-y += local64.h | 23 | generic-y += local64.h |
| 24 | generic-y += mm-arch-hooks.h | 24 | generic-y += mm-arch-hooks.h |
| 25 | generic-y += msi.h | ||
| 25 | generic-y += percpu.h | 26 | generic-y += percpu.h |
| 26 | generic-y += preempt.h | 27 | generic-y += preempt.h |
| 27 | generic-y += sections.h | 28 | generic-y += sections.h |
| @@ -16,7 +16,13 @@ extern void __fstate_restore(struct task_struct *restore_from); · 15 unmodified lines | |||
| 16 | 16 | ||
| 17 | static inline void __fstate_clean(struct pt_regs *regs) | 17 | static inline void __fstate_clean(struct pt_regs *regs) |
| 18 | { | 18 | { |
| 19 | regs->sstatus |= (regs->sstatus & ~(SR_FS)) | SR_FS_CLEAN; | 19 | regs->sstatus = (regs->sstatus & ~SR_FS) | SR_FS_CLEAN; |
| 20 | } | ||
| 21 | |||
| 22 | static inline void fstate_off(struct task_struct *task, | ||
| 23 | struct pt_regs *regs) | ||
| 24 | { | ||
| 25 | regs->sstatus = (regs->sstatus & ~SR_FS) | SR_FS_OFF; | ||
| 20 | } | 26 | } |
| 21 | 27 | ||
| 22 | static inline void fstate_save(struct task_struct *task, | 28 | static inline void fstate_save(struct task_struct *task, |
| @@ -53,10 +53,17 @@ static inline void remote_sfence_vma(struct cpumask *cmask, unsigned long start, · 52 unmodified lines | |||
| 53 | } | 53 | } |
| 54 | 54 | ||
| 55 | #define flush_tlb_all() sbi_remote_sfence_vma(NULL, 0, -1) | 55 | #define flush_tlb_all() sbi_remote_sfence_vma(NULL, 0, -1) |
| 56 | #define flush_tlb_page(vma, addr) flush_tlb_range(vma, addr, 0) | 56 | |
| 57 | #define flush_tlb_range(vma, start, end) \ | 57 | #define flush_tlb_range(vma, start, end) \ |
| 58 | remote_sfence_vma(mm_cpumask((vma)->vm_mm), start, (end) - (start)) | 58 | remote_sfence_vma(mm_cpumask((vma)->vm_mm), start, (end) - (start)) |
| 59 | #define flush_tlb_mm(mm) \ | 59 | |
| 60 | static inline void flush_tlb_page(struct vm_area_struct *vma, | ||
| 61 | unsigned long addr) | ||
| 62 | { | ||
| 63 | flush_tlb_range(vma, addr, addr + PAGE_SIZE); | ||
| 64 | } | ||
| 65 | |||
| 66 | #define flush_tlb_mm(mm) \ | ||
| 60 | remote_sfence_vma(mm_cpumask(mm), 0, -1) | 67 | remote_sfence_vma(mm_cpumask(mm), 0, -1) |
| 61 | 68 | ||
| 62 | #endif /* CONFIG_SMP */ | 69 | #endif /* CONFIG_SMP */ |
| @@ -1,4 +1,4 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ | 1 | /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ |
| 2 | /* | 2 | /* |
| 3 | * Copyright (C) 2012 ARM Ltd. | 3 | * Copyright (C) 2012 ARM Ltd. |
| 4 | * Copyright (C) 2015 Regents of the University of California | 4 | * Copyright (C) 2015 Regents of the University of California |
| @@ -1,4 +1,4 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ | 1 | /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ |
| 2 | /* | 2 | /* |
| 3 | * Copyright (C) 2012 ARM Ltd. | 3 | * Copyright (C) 2012 ARM Ltd. |
| 4 | * Copyright (C) 2015 Regents of the University of California | 4 | * Copyright (C) 2015 Regents of the University of California |
| @@ -1,4 +1,4 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ | 1 | /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ |
| 2 | /* | 2 | /* |
| 3 | * Copyright (C) 2012 ARM Ltd. | 3 | * Copyright (C) 2012 ARM Ltd. |
| 4 | * Copyright (C) 2015 Regents of the University of California | 4 | * Copyright (C) 2015 Regents of the University of California |
| @@ -1,4 +1,4 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ | 1 | /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ |
| 2 | /* | 2 | /* |
| 3 | * Copied from arch/arm64/include/asm/hwcap.h | 3 | * Copied from arch/arm64/include/asm/hwcap.h |
| 4 | * | 4 | * |
| @@ -1,4 +1,4 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ | 1 | /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ |
| 2 | /* | 2 | /* |
| 3 | * Copyright (C) 2012 Regents of the University of California | 3 | * Copyright (C) 2012 Regents of the University of California |
| 4 | */ | 4 | */ |
| @@ -1,4 +1,4 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ | 1 | /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ |
| 2 | /* | 2 | /* |
| 3 | * Copyright (C) 2012 Regents of the University of California | 3 | * Copyright (C) 2012 Regents of the University of California |
| 4 | */ | 4 | */ |
| @@ -1,4 +1,4 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ | 1 | /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ |
| 2 | /* | 2 | /* |
| 3 | * Copyright (C) 2012 ARM Ltd. | 3 | * Copyright (C) 2012 ARM Ltd. |
| 4 | * Copyright (C) 2017 SiFive, Inc. | 4 | * Copyright (C) 2017 SiFive, Inc. |
| @@ -18,6 +18,7 @@ · 17 unmodified lines | |||
| 18 | #ifdef __LP64__ | 18 | #ifdef __LP64__ |
| 19 | #define __ARCH_WANT_NEW_STAT | 19 | #define __ARCH_WANT_NEW_STAT |
| 20 | #define __ARCH_WANT_SET_GET_RLIMIT | 20 | #define __ARCH_WANT_SET_GET_RLIMIT |
| 21 | #define __ARCH_WANT_SYS_CLONE3 | ||
| 21 | #endif /* __LP64__ */ | 22 | #endif /* __LP64__ */ |
| 22 | 23 | ||
| 23 | #include <asm-generic/unistd.h> | 24 | #include <asm-generic/unistd.h> |
| @@ -64,8 +64,14 @@ void start_thread(struct pt_regs *regs, unsigned long pc, · 63 unmodified lines | |||
| 64 | unsigned long sp) | 64 | unsigned long sp) |
| 65 | { | 65 | { |
| 66 | regs->sstatus = SR_SPIE; | 66 | regs->sstatus = SR_SPIE; |
| 67 | if (has_fpu) | 67 | if (has_fpu) { |
| 68 | regs->sstatus |= SR_FS_INITIAL; | 68 | regs->sstatus |= SR_FS_INITIAL; |
| 69 | /* | ||
| 70 | * Restore the initial value to the FP register | ||
| 71 | * before starting the user program. | ||
| 72 | */ | ||
| 73 | fstate_restore(current, regs); | ||
| 74 | } | ||
| 69 | regs->sepc = pc; | 75 | regs->sepc = pc; |
| 70 | regs->sp = sp; | 76 | regs->sp = sp; |
| 71 | set_fs(USER_DS); | 77 | set_fs(USER_DS); |
| @@ -75,10 +81,11 @@ void flush_thread(void) · 3 unmodified lines | |||
| 75 | { | 81 | { |
| 76 | #ifdef CONFIG_FPU | 82 | #ifdef CONFIG_FPU |
| 77 | /* | 83 | /* |
| 78 | * Reset FPU context | 84 | * Reset FPU state and context |
| 79 | * frm: round to nearest, ties to even (IEEE default) | 85 | * frm: round to nearest, ties to even (IEEE default) |
| 80 | * fflags: accrued exceptions cleared | 86 | * fflags: accrued exceptions cleared |
| 81 | */ | 87 | */ |
| 88 | fstate_off(current, task_pt_regs(current)); | ||
| 82 | memset(¤t->thread.fstate, 0, sizeof(current->thread.fstate)); | 89 | memset(¤t->thread.fstate, 0, sizeof(current->thread.fstate)); |
| 83 | #endif | 90 | #endif |
| 84 | } | 91 | } |
| @@ -37,7 +37,7 @@ $(obj)/vdso.so.dbg: $(src)/vdso.lds $(obj-vdso) FORCE · 36 unmodified lines | |||
| 37 | # these symbols in the kernel code rather than hand-coded addresses. | 37 | # these symbols in the kernel code rather than hand-coded addresses. |
| 38 | 38 | ||
| 39 | SYSCFLAGS_vdso.so.dbg = -shared -s -Wl,-soname=linux-vdso.so.1 \ | 39 | SYSCFLAGS_vdso.so.dbg = -shared -s -Wl,-soname=linux-vdso.so.1 \ |
| 40 | -Wl,--hash-style=both | 40 | -Wl,--build-id -Wl,--hash-style=both |
| 41 | $(obj)/vdso-dummy.o: $(src)/vdso.lds $(obj)/rt_sigreturn.o FORCE | 41 | $(obj)/vdso-dummy.o: $(src)/vdso.lds $(obj)/rt_sigreturn.o FORCE |
| 42 | $(call if_changed,vdsold) | 42 | $(call if_changed,vdsold) |
| 43 | 43 | ||
| @@ -5,5 +5,3 @@ lib-y += memset.o · 4 unmodified lines | |||
| 5 | lib-y += uaccess.o | 5 | lib-y += uaccess.o |
| 6 | 6 | ||
| 7 | lib-$(CONFIG_64BIT) += tishift.o | 7 | lib-$(CONFIG_64BIT) += tishift.o |
| 8 | |||
| 9 | lib-$(CONFIG_32BIT) += udivdi3.o | ||
| @@ -81,9 +81,13 @@ EXPORT_SYMBOL(__delay); · 80 unmodified lines | |||
| 81 | void udelay(unsigned long usecs) | 81 | void udelay(unsigned long usecs) |
| 82 | { | 82 | { |
| 83 | u64 ucycles = (u64)usecs * lpj_fine * UDELAY_MULT; | 83 | u64 ucycles = (u64)usecs * lpj_fine * UDELAY_MULT; |
| 84 | u64 n; | ||
| 84 | 85 | ||
| 85 | if (unlikely(usecs > MAX_UDELAY_US)) { | 86 | if (unlikely(usecs > MAX_UDELAY_US)) { |
| 86 | __delay((u64)usecs * riscv_timebase / 1000000ULL); | 87 | n = (u64)usecs * riscv_timebase; |
| 88 | do_div(n, 1000000); | ||
| 89 | |||
| 90 | __delay(n); | ||
| 87 | return; | 91 | return; |
| 88 | } | 92 | } |
| 89 | 93 | ||
| @@ -1,32 +0,0 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ | ||
| 2 | /* | ||
| 3 | * Copyright (C) 2016-2017 Free Software Foundation, Inc. | ||
| 4 | */ | ||
| 5 | |||
| 6 | #include <linux/linkage.h> | ||
| 7 | |||
| 8 | ENTRY(__udivdi3) | ||
| 9 | mv a2, a1 | ||
| 10 | mv a1, a0 | ||
| 11 | li a0, -1 | ||
| 12 | beqz a2, .L5 | ||
| 13 | li a3, 1 | ||
| 14 | bgeu a2, a1, .L2 | ||
| 15 | .L1: | ||
| 16 | blez a2, .L2 | ||
| 17 | slli a2, a2, 1 | ||
| 18 | slli a3, a3, 1 | ||
| 19 | bgtu a1, a2, .L1 | ||
| 20 | .L2: | ||
| 21 | li a0, 0 | ||
| 22 | .L3: | ||
| 23 | bltu a1, a2, .L4 | ||
| 24 | sub a1, a1, a2 | ||
| 25 | or a0, a0, a3 | ||
| 26 | .L4: | ||
| 27 | srli a3, a3, 1 | ||
| 28 | srli a2, a2, 1 | ||
| 29 | bnez a3, .L3 | ||
| 30 | .L5: | ||
| 31 | ret | ||
| 32 | ENDPROC(__udivdi3) | ||
| @@ -36,7 +36,7 @@ CFLAGS_sclp_early_core.o += -I$(srctree)/drivers/s390/char · 35 unmodified lines | |||
| 36 | 36 | ||
| 37 | obj-y := head.o als.o startup.o mem_detect.o ipl_parm.o ipl_report.o | 37 | obj-y := head.o als.o startup.o mem_detect.o ipl_parm.o ipl_report.o |
| 38 | obj-y += string.o ebcdic.o sclp_early_core.o mem.o ipl_vmparm.o cmdline.o | 38 | obj-y += string.o ebcdic.o sclp_early_core.o mem.o ipl_vmparm.o cmdline.o |
| 39 | obj-y += ctype.o text_dma.o | 39 | obj-y += version.o ctype.o text_dma.o |
| 40 | obj-$(CONFIG_PROTECTED_VIRTUALIZATION_GUEST) += uv.o | 40 | obj-$(CONFIG_PROTECTED_VIRTUALIZATION_GUEST) += uv.o |
| 41 | obj-$(CONFIG_RELOCATABLE) += machine_kexec_reloc.o | 41 | obj-$(CONFIG_RELOCATABLE) += machine_kexec_reloc.o |
| 42 | obj-$(CONFIG_RANDOMIZE_BASE) += kaslr.o | 42 | obj-$(CONFIG_RANDOMIZE_BASE) += kaslr.o |
| @@ -8,10 +8,12 @@ void store_ipl_parmblock(void); · 7 unmodified lines | |||
| 8 | void setup_boot_command_line(void); | 8 | void setup_boot_command_line(void); |
| 9 | void parse_boot_command_line(void); | 9 | void parse_boot_command_line(void); |
| 10 | void setup_memory_end(void); | 10 | void setup_memory_end(void); |
| 11 | void verify_facilities(void); | ||
| 11 | void print_missing_facilities(void); | 12 | void print_missing_facilities(void); |
| 12 | unsigned long get_random_base(unsigned long safe_addr); | 13 | unsigned long get_random_base(unsigned long safe_addr); |
| 13 | 14 | ||
| 14 | extern int kaslr_enabled; | 15 | extern int kaslr_enabled; |
| 16 | extern const char kernel_version[]; | ||
| 15 | 17 | ||
| 16 | unsigned long read_ipl_report(unsigned long safe_offset); | 18 | unsigned long read_ipl_report(unsigned long safe_offset); |
| 17 | 19 | ||
| @@ -361,6 +361,7 @@ ENTRY(startup_kdump) · 360 unmodified lines | |||
| 361 | .quad 0 # INITRD_SIZE | 361 | .quad 0 # INITRD_SIZE |
| 362 | .quad 0 # OLDMEM_BASE | 362 | .quad 0 # OLDMEM_BASE |
| 363 | .quad 0 # OLDMEM_SIZE | 363 | .quad 0 # OLDMEM_SIZE |
| 364 | .quad kernel_version # points to kernel version string | ||
| 364 | 365 | ||
| 365 | .org COMMAND_LINE | 366 | .org COMMAND_LINE |
| 366 | .byte "root=/dev/ram0 ro" | 367 | .byte "root=/dev/ram0 ro" |
| @@ -48,9 +48,7 @@ void store_ipl_parmblock(void) · 47 unmodified lines | |||
| 48 | { | 48 | { |
| 49 | int rc; | 49 | int rc; |
| 50 | 50 | ||
| 51 | uv_set_shared(__pa(&ipl_block)); | ||
| 52 | rc = __diag308(DIAG308_STORE, &ipl_block); | 51 | rc = __diag308(DIAG308_STORE, &ipl_block); |
| 53 | uv_remove_shared(__pa(&ipl_block)); | ||
| 54 | if (rc == DIAG308_RC_OK && | 52 | if (rc == DIAG308_RC_OK && |
| 55 | ipl_block.hdr.version <= IPL_MAX_SUPPORTED_VERSION) | 53 | ipl_block.hdr.version <= IPL_MAX_SUPPORTED_VERSION) |
| 56 | ipl_block_valid = 1; | 54 | ipl_block_valid = 1; |
| @@ -7,6 +7,7 @@ · 6 unmodified lines | |||
| 7 | #include <asm/timex.h> | 7 | #include <asm/timex.h> |
| 8 | #include <asm/sclp.h> | 8 | #include <asm/sclp.h> |
| 9 | #include "compressed/decompressor.h" | 9 | #include "compressed/decompressor.h" |
| 10 | #include "boot.h" | ||
| 10 | 11 | ||
| 11 | #define PRNG_MODE_TDES 1 | 12 | #define PRNG_MODE_TDES 1 |
| 12 | #define PRNG_MODE_SHA512 2 | 13 | #define PRNG_MODE_SHA512 2 |
| @@ -0,0 +1,7 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | ||
| 2 | #include <generated/utsrelease.h> | ||
| 3 | #include <generated/compile.h> | ||
| 4 | #include "boot.h" | ||
| 5 | |||
| 6 | const char kernel_version[] = UTS_RELEASE | ||
| 7 | " (" LINUX_COMPILE_BY "@" LINUX_COMPILE_HOST ") " UTS_VERSION; | ||
| @@ -3,6 +3,7 @@ CONFIG_POSIX_MQUEUE=y · 2 unmodified lines | |||
| 3 | CONFIG_AUDIT=y | 3 | CONFIG_AUDIT=y |
| 4 | CONFIG_NO_HZ_IDLE=y | 4 | CONFIG_NO_HZ_IDLE=y |
| 5 | CONFIG_HIGH_RES_TIMERS=y | 5 | CONFIG_HIGH_RES_TIMERS=y |
| 6 | CONFIG_PREEMPT=y | ||
| 6 | CONFIG_BSD_PROCESS_ACCT=y | 7 | CONFIG_BSD_PROCESS_ACCT=y |
| 7 | CONFIG_BSD_PROCESS_ACCT_V3=y | 8 | CONFIG_BSD_PROCESS_ACCT_V3=y |
| 8 | CONFIG_TASKSTATS=y | 9 | CONFIG_TASKSTATS=y |
| @@ -18,55 +19,71 @@ CONFIG_BLK_CGROUP=y · 9 unmodified lines | |||
| 18 | CONFIG_CFS_BANDWIDTH=y | 19 | CONFIG_CFS_BANDWIDTH=y |
| 19 | CONFIG_RT_GROUP_SCHED=y | 20 | CONFIG_RT_GROUP_SCHED=y |
| 20 | CONFIG_CGROUP_PIDS=y | 21 | CONFIG_CGROUP_PIDS=y |
| 22 | CONFIG_CGROUP_RDMA=y | ||
| 21 | CONFIG_CGROUP_FREEZER=y | 23 | CONFIG_CGROUP_FREEZER=y |
| 22 | CONFIG_CGROUP_HUGETLB=y | 24 | CONFIG_CGROUP_HUGETLB=y |
| 23 | CONFIG_CPUSETS=y | 25 | CONFIG_CPUSETS=y |
| 24 | CONFIG_CGROUP_DEVICE=y | 26 | CONFIG_CGROUP_DEVICE=y |
| 25 | CONFIG_CGROUP_CPUACCT=y | 27 | CONFIG_CGROUP_CPUACCT=y |
| 26 | CONFIG_CGROUP_PERF=y | 28 | CONFIG_CGROUP_PERF=y |
| 29 | CONFIG_CGROUP_BPF=y | ||
| 27 | CONFIG_NAMESPACES=y | 30 | CONFIG_NAMESPACES=y |
| 28 | CONFIG_USER_NS=y | 31 | CONFIG_USER_NS=y |
| 32 | CONFIG_CHECKPOINT_RESTORE=y | ||
| 29 | CONFIG_SCHED_AUTOGROUP=y | 33 | CONFIG_SCHED_AUTOGROUP=y |
| 30 | CONFIG_BLK_DEV_INITRD=y | 34 | CONFIG_BLK_DEV_INITRD=y |
| 31 | CONFIG_EXPERT=y | 35 | CONFIG_EXPERT=y |
| 32 | # CONFIG_SYSFS_SYSCALL is not set | 36 | # CONFIG_SYSFS_SYSCALL is not set |
| 33 | CONFIG_CHECKPOINT_RESTORE=y | ||
| 34 | CONFIG_BPF_SYSCALL=y | 37 | CONFIG_BPF_SYSCALL=y |
| 35 | CONFIG_USERFAULTFD=y | 38 | CONFIG_USERFAULTFD=y |
| 36 | # CONFIG_COMPAT_BRK is not set | 39 | # CONFIG_COMPAT_BRK is not set |
| 37 | CONFIG_PROFILING=y | 40 | CONFIG_PROFILING=y |
| 41 | CONFIG_LIVEPATCH=y | ||
| 42 | CONFIG_TUNE_ZEC12=y | ||
| 43 | CONFIG_NR_CPUS=512 | ||
| 44 | CONFIG_NUMA=y | ||
| 45 | CONFIG_HZ_100=y | ||
| 46 | CONFIG_KEXEC_FILE=y | ||
| 47 | CONFIG_EXPOLINE=y | ||
| 48 | CONFIG_EXPOLINE_AUTO=y | ||
| 49 | CONFIG_CHSC_SCH=y | ||
| 50 | CONFIG_VFIO_CCW=m | ||
| 51 | CONFIG_VFIO_AP=m | ||
| 52 | CONFIG_CRASH_DUMP=y | ||
| 53 | CONFIG_HIBERNATION=y | ||
| 54 | CONFIG_PM_DEBUG=y | ||
| 55 | CONFIG_CMM=m | ||
| 56 | CONFIG_APPLDATA_BASE=y | ||
| 57 | CONFIG_KVM=m | ||
| 58 | CONFIG_VHOST_NET=m | ||
| 59 | CONFIG_VHOST_VSOCK=m | ||
| 38 | CONFIG_OPROFILE=m | 60 | CONFIG_OPROFILE=m |
| 39 | CONFIG_KPROBES=y | 61 | CONFIG_KPROBES=y |
| 40 | CONFIG_JUMP_LABEL=y | 62 | CONFIG_JUMP_LABEL=y |
| 41 | CONFIG_STATIC_KEYS_SELFTEST=y | 63 | CONFIG_STATIC_KEYS_SELFTEST=y |
| 64 | CONFIG_REFCOUNT_FULL=y | ||
| 65 | CONFIG_LOCK_EVENT_COUNTS=y | ||
| 42 | CONFIG_MODULES=y | 66 | CONFIG_MODULES=y |
| 43 | CONFIG_MODULE_FORCE_LOAD=y | 67 | CONFIG_MODULE_FORCE_LOAD=y |
| 44 | CONFIG_MODULE_UNLOAD=y | 68 | CONFIG_MODULE_UNLOAD=y |
| 45 | CONFIG_MODULE_FORCE_UNLOAD=y | 69 | CONFIG_MODULE_FORCE_UNLOAD=y |
| 46 | CONFIG_MODVERSIONS=y | 70 | CONFIG_MODVERSIONS=y |
| 47 | CONFIG_MODULE_SRCVERSION_ALL=y | 71 | CONFIG_MODULE_SRCVERSION_ALL=y |
| 72 | CONFIG_MODULE_SIG=y | ||
| 73 | CONFIG_MODULE_SIG_SHA256=y | ||
| 48 | CONFIG_BLK_DEV_INTEGRITY=y | 74 | CONFIG_BLK_DEV_INTEGRITY=y |
| 49 | CONFIG_BLK_DEV_THROTTLING=y | 75 | CONFIG_BLK_DEV_THROTTLING=y |
| 50 | CONFIG_BLK_WBT=y | 76 | CONFIG_BLK_WBT=y |
| 51 | CONFIG_BLK_WBT_SQ=y | 77 | CONFIG_BLK_CGROUP_IOLATENCY=y |
| 52 | CONFIG_PARTITION_ADVANCED=y | 78 | CONFIG_PARTITION_ADVANCED=y |
| 53 | CONFIG_IBM_PARTITION=y | 79 | CONFIG_IBM_PARTITION=y |
| 54 | CONFIG_BSD_DISKLABEL=y | 80 | CONFIG_BSD_DISKLABEL=y |
| 55 | CONFIG_MINIX_SUBPARTITION=y | 81 | CONFIG_MINIX_SUBPARTITION=y |
| 56 | CONFIG_SOLARIS_X86_PARTITION=y | 82 | CONFIG_SOLARIS_X86_PARTITION=y |
| 57 | CONFIG_UNIXWARE_DISKLABEL=y | 83 | CONFIG_UNIXWARE_DISKLABEL=y |
| 58 | CONFIG_CFQ_GROUP_IOSCHED=y | 84 | CONFIG_IOSCHED_BFQ=y |
| 59 | CONFIG_DEFAULT_DEADLINE=y | 85 | CONFIG_BFQ_GROUP_IOSCHED=y |
| 60 | CONFIG_LIVEPATCH=y | 86 | CONFIG_BINFMT_MISC=m |
| 61 | CONFIG_TUNE_ZEC12=y | ||
| 62 | CONFIG_NR_CPUS=512 | ||
| 63 | CONFIG_NUMA=y | ||
| 64 | CONFIG_PREEMPT=y | ||
| 65 | CONFIG_HZ_100=y | ||
| 66 | CONFIG_KEXEC_FILE=y | ||
| 67 | CONFIG_KEXEC_VERIFY_SIG=y | ||
| 68 | CONFIG_EXPOLINE=y | ||
| 69 | CONFIG_EXPOLINE_AUTO=y | ||
| 70 | CONFIG_MEMORY_HOTPLUG=y | 87 | CONFIG_MEMORY_HOTPLUG=y |
| 71 | CONFIG_MEMORY_HOTREMOVE=y | 88 | CONFIG_MEMORY_HOTREMOVE=y |
| 72 | CONFIG_KSM=y | 89 | CONFIG_KSM=y |
| @@ -82,17 +99,8 @@ CONFIG_ZSMALLOC=m · 9 unmodified lines | |||
| 82 | CONFIG_ZSMALLOC_STAT=y | 99 | CONFIG_ZSMALLOC_STAT=y |
| 83 | CONFIG_DEFERRED_STRUCT_PAGE_INIT=y | 100 | CONFIG_DEFERRED_STRUCT_PAGE_INIT=y |
| 84 | CONFIG_IDLE_PAGE_TRACKING=y | 101 | CONFIG_IDLE_PAGE_TRACKING=y |
| 85 | CONFIG_PCI=y | 102 | CONFIG_PERCPU_STATS=y |
| 86 | CONFIG_PCI_DEBUG=y | 103 | CONFIG_GUP_BENCHMARK=y |
| 87 | CONFIG_HOTPLUG_PCI=y | ||
| 88 | CONFIG_HOTPLUG_PCI_S390=y | ||
| 89 | CONFIG_CHSC_SCH=y | ||
| 90 | CONFIG_VFIO_AP=m | ||
| 91 | CONFIG_VFIO_CCW=m | ||
| 92 | CONFIG_CRASH_DUMP=y | ||
| 93 | CONFIG_BINFMT_MISC=m | ||
| 94 | CONFIG_HIBERNATION=y | ||
| 95 | CONFIG_PM_DEBUG=y | ||
| 96 | CONFIG_NET=y | 104 | CONFIG_NET=y |
| 97 | CONFIG_PACKET=y | 105 | CONFIG_PACKET=y |
| 98 | CONFIG_PACKET_DIAG=m | 106 | CONFIG_PACKET_DIAG=m |
| @@ -121,9 +129,6 @@ CONFIG_NET_IPVTI=m · 22 unmodified lines | |||
| 121 | CONFIG_INET_AH=m | 129 | CONFIG_INET_AH=m |
| 122 | CONFIG_INET_ESP=m | 130 | CONFIG_INET_ESP=m |
| 123 | CONFIG_INET_IPCOMP=m | 131 | CONFIG_INET_IPCOMP=m |
| 124 | CONFIG_INET_XFRM_MODE_TRANSPORT=m | ||
| 125 | CONFIG_INET_XFRM_MODE_TUNNEL=m | ||
| 126 | CONFIG_INET_XFRM_MODE_BEET=m | ||
| 127 | CONFIG_INET_DIAG=m | 132 | CONFIG_INET_DIAG=m |
| 128 | CONFIG_INET_UDP_DIAG=m | 133 | CONFIG_INET_UDP_DIAG=m |
| 129 | CONFIG_TCP_CONG_ADVANCED=y | 134 | CONFIG_TCP_CONG_ADVANCED=y |
| @@ -139,10 +144,6 @@ CONFIG_INET6_AH=m · 9 unmodified lines | |||
| 139 | CONFIG_INET6_ESP=m | 144 | CONFIG_INET6_ESP=m |
| 140 | CONFIG_INET6_IPCOMP=m | 145 | CONFIG_INET6_IPCOMP=m |
| 141 | CONFIG_IPV6_MIP6=m | 146 | CONFIG_IPV6_MIP6=m |
| 142 | CONFIG_INET6_XFRM_MODE_TRANSPORT=m | ||
| 143 | CONFIG_INET6_XFRM_MODE_TUNNEL=m | ||
| 144 | CONFIG_INET6_XFRM_MODE_BEET=m | ||
| 145 | CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m | ||
| 146 | CONFIG_IPV6_VTI=m | 147 | CONFIG_IPV6_VTI=m |
| 147 | CONFIG_IPV6_SIT=m | 148 | CONFIG_IPV6_SIT=m |
| 148 | CONFIG_IPV6_GRE=m | 149 | CONFIG_IPV6_GRE=m |
| @@ -264,11 +265,8 @@ CONFIG_IP_VS_SED=m · 115 unmodified lines | |||
| 264 | CONFIG_IP_VS_NQ=m | 265 | CONFIG_IP_VS_NQ=m |
| 265 | CONFIG_IP_VS_FTP=m | 266 | CONFIG_IP_VS_FTP=m |
| 266 | CONFIG_IP_VS_PE_SIP=m | 267 | CONFIG_IP_VS_PE_SIP=m |
| 267 | CONFIG_NF_CONNTRACK_IPV4=m | ||
| 268 | CONFIG_NF_TABLES_IPV4=y | 268 | CONFIG_NF_TABLES_IPV4=y |
| 269 | CONFIG_NFT_CHAIN_ROUTE_IPV4=m | ||
| 270 | CONFIG_NF_TABLES_ARP=y | 269 | CONFIG_NF_TABLES_ARP=y |
| 271 | CONFIG_NFT_CHAIN_NAT_IPV4=m | ||
| 272 | CONFIG_IP_NF_IPTABLES=m | 270 | CONFIG_IP_NF_IPTABLES=m |
| 273 | CONFIG_IP_NF_MATCH_AH=m | 271 | CONFIG_IP_NF_MATCH_AH=m |
| 274 | CONFIG_IP_NF_MATCH_ECN=m | 272 | CONFIG_IP_NF_MATCH_ECN=m |
| @@ -287,10 +285,7 @@ CONFIG_IP_NF_SECURITY=m · 12 unmodified lines | |||
| 287 | CONFIG_IP_NF_ARPTABLES=m | 285 | CONFIG_IP_NF_ARPTABLES=m |
| 288 | CONFIG_IP_NF_ARPFILTER=m | 286 | CONFIG_IP_NF_ARPFILTER=m |
| 289 | CONFIG_IP_NF_ARP_MANGLE=m | 287 | CONFIG_IP_NF_ARP_MANGLE=m |
| 290 | CONFIG_NF_CONNTRACK_IPV6=m | ||
| 291 | CONFIG_NF_TABLES_IPV6=y | 288 | CONFIG_NF_TABLES_IPV6=y |
| 292 | CONFIG_NFT_CHAIN_ROUTE_IPV6=m | ||
| 293 | CONFIG_NFT_CHAIN_NAT_IPV6=m | ||
| 294 | CONFIG_IP6_NF_IPTABLES=m | 289 | CONFIG_IP6_NF_IPTABLES=m |
| 295 | CONFIG_IP6_NF_MATCH_AH=m | 290 | CONFIG_IP6_NF_MATCH_AH=m |
| 296 | CONFIG_IP6_NF_MATCH_EUI64=m | 291 | CONFIG_IP6_NF_MATCH_EUI64=m |
| @@ -309,7 +304,7 @@ CONFIG_IP6_NF_RAW=m · 12 unmodified lines | |||
| 309 | CONFIG_IP6_NF_SECURITY=m | 304 | CONFIG_IP6_NF_SECURITY=m |
| 310 | CONFIG_IP6_NF_NAT=m | 305 | CONFIG_IP6_NF_NAT=m |
| 311 | CONFIG_IP6_NF_TARGET_MASQUERADE=m | 306 | CONFIG_IP6_NF_TARGET_MASQUERADE=m |
| 312 | CONFIG_NF_TABLES_BRIDGE=y | 307 | CONFIG_NF_TABLES_BRIDGE=m |
| 313 | CONFIG_RDS=m | 308 | CONFIG_RDS=m |
| 314 | CONFIG_RDS_RDMA=m | 309 | CONFIG_RDS_RDMA=m |
| 315 | CONFIG_RDS_TCP=m | 310 | CONFIG_RDS_TCP=m |
| @@ -375,9 +370,11 @@ CONFIG_NETLINK_DIAG=m · 59 unmodified lines | |||
| 375 | CONFIG_CGROUP_NET_PRIO=y | 370 | CONFIG_CGROUP_NET_PRIO=y |
| 376 | CONFIG_BPF_JIT=y | 371 | CONFIG_BPF_JIT=y |
| 377 | CONFIG_NET_PKTGEN=m | 372 | CONFIG_NET_PKTGEN=m |
| 373 | CONFIG_PCI=y | ||
| 374 | CONFIG_PCI_DEBUG=y | ||
| 375 | CONFIG_HOTPLUG_PCI=y | ||
| 376 | CONFIG_HOTPLUG_PCI_S390=y | ||
| 378 | CONFIG_DEVTMPFS=y | 377 | CONFIG_DEVTMPFS=y |
| 379 | CONFIG_DMA_CMA=y | ||
| 380 | CONFIG_CMA_SIZE_MBYTES=0 | ||
| 381 | CONFIG_CONNECTOR=y | 378 | CONFIG_CONNECTOR=y |
| 382 | CONFIG_ZRAM=m | 379 | CONFIG_ZRAM=m |
| 383 | CONFIG_BLK_DEV_LOOP=m | 380 | CONFIG_BLK_DEV_LOOP=m |
| @@ -395,7 +392,6 @@ CONFIG_RAID_ATTRS=m · 11 unmodified lines | |||
| 395 | CONFIG_SCSI=y | 392 | CONFIG_SCSI=y |
| 396 | CONFIG_BLK_DEV_SD=y | 393 | CONFIG_BLK_DEV_SD=y |
| 397 | CONFIG_CHR_DEV_ST=m | 394 | CONFIG_CHR_DEV_ST=m |
| 398 | CONFIG_CHR_DEV_OSST=m | ||
| 399 | CONFIG_BLK_DEV_SR=m | 395 | CONFIG_BLK_DEV_SR=m |
| 400 | CONFIG_CHR_DEV_SG=y | 396 | CONFIG_CHR_DEV_SG=y |
| 401 | CONFIG_CHR_DEV_SCH=m | 397 | CONFIG_CHR_DEV_SCH=m |
| @@ -415,17 +411,19 @@ CONFIG_SCSI_DH_RDAC=m · 13 unmodified lines | |||
| 415 | CONFIG_SCSI_DH_HP_SW=m | 411 | CONFIG_SCSI_DH_HP_SW=m |
| 416 | CONFIG_SCSI_DH_EMC=m | 412 | CONFIG_SCSI_DH_EMC=m |
| 417 | CONFIG_SCSI_DH_ALUA=m | 413 | CONFIG_SCSI_DH_ALUA=m |
| 418 | CONFIG_SCSI_OSD_INITIATOR=m | ||
| 419 | CONFIG_SCSI_OSD_ULD=m | ||
| 420 | CONFIG_MD=y | 414 | CONFIG_MD=y |
| 421 | CONFIG_BLK_DEV_MD=y | 415 | CONFIG_BLK_DEV_MD=y |
| 422 | CONFIG_MD_LINEAR=m | 416 | CONFIG_MD_LINEAR=m |
| 423 | CONFIG_MD_MULTIPATH=m | 417 | CONFIG_MD_MULTIPATH=m |
| 424 | CONFIG_MD_FAULTY=m | 418 | CONFIG_MD_FAULTY=m |
| 419 | CONFIG_MD_CLUSTER=m | ||
| 420 | CONFIG_BCACHE=m | ||
| 425 | CONFIG_BLK_DEV_DM=m | 421 | CONFIG_BLK_DEV_DM=m |
| 422 | CONFIG_DM_UNSTRIPED=m | ||
| 426 | CONFIG_DM_CRYPT=m | 423 | CONFIG_DM_CRYPT=m |
| 427 | CONFIG_DM_SNAPSHOT=m | 424 | CONFIG_DM_SNAPSHOT=m |
| 428 | CONFIG_DM_THIN_PROVISIONING=m | 425 | CONFIG_DM_THIN_PROVISIONING=m |
| 426 | CONFIG_DM_WRITECACHE=m | ||
| 429 | CONFIG_DM_MIRROR=m | 427 | CONFIG_DM_MIRROR=m |
| 430 | CONFIG_DM_LOG_USERSPACE=m | 428 | CONFIG_DM_LOG_USERSPACE=m |
| 431 | CONFIG_DM_RAID=m | 429 | CONFIG_DM_RAID=m |
| @@ -445,23 +443,78 @@ CONFIG_EQUALIZER=m · 13 unmodified lines | |||
| 445 | CONFIG_IFB=m | 443 | CONFIG_IFB=m |
| 446 | CONFIG_MACVLAN=m | 444 | CONFIG_MACVLAN=m |
| 447 | CONFIG_MACVTAP=m | 445 | CONFIG_MACVTAP=m |
| 448 | CONFIG_VXLAN=m | ||
| 449 | CONFIG_TUN=m | 446 | CONFIG_TUN=m |
| 450 | CONFIG_VETH=m | 447 | CONFIG_VETH=m |
| 451 | CONFIG_VIRTIO_NET=m | 448 | CONFIG_VIRTIO_NET=m |
| 452 | CONFIG_NLMON=m | 449 | CONFIG_NLMON=m |
| 450 | # CONFIG_NET_VENDOR_3COM is not set | ||
| 451 | # CONFIG_NET_VENDOR_ADAPTEC is not set | ||
| 452 | # CONFIG_NET_VENDOR_AGERE is not set | ||
| 453 | # CONFIG_NET_VENDOR_ALACRITECH is not set | ||
| 454 | # CONFIG_NET_VENDOR_ALTEON is not set | ||
| 455 | # CONFIG_NET_VENDOR_AMAZON is not set | ||
| 456 | # CONFIG_NET_VENDOR_AMD is not set | ||
| 457 | # CONFIG_NET_VENDOR_AQUANTIA is not set | ||
| 453 | # CONFIG_NET_VENDOR_ARC is not set | 458 | # CONFIG_NET_VENDOR_ARC is not set |
| 459 | # CONFIG_NET_VENDOR_ATHEROS is not set | ||
| 460 | # CONFIG_NET_VENDOR_AURORA is not set | ||
| 461 | # CONFIG_NET_VENDOR_BROADCOM is not set | ||
| 462 | # CONFIG_NET_VENDOR_BROCADE is not set | ||
| 463 | # CONFIG_NET_VENDOR_CADENCE is not set | ||
| 464 | # CONFIG_NET_VENDOR_CAVIUM is not set | ||
| 454 | # CONFIG_NET_VENDOR_CHELSIO is not set | 465 | # CONFIG_NET_VENDOR_CHELSIO is not set |
| 466 | # CONFIG_NET_VENDOR_CISCO is not set | ||
| 467 | # CONFIG_NET_VENDOR_CORTINA is not set | ||
| 468 | # CONFIG_NET_VENDOR_DEC is not set | ||
| 469 | # CONFIG_NET_VENDOR_DLINK is not set | ||
| 470 | # CONFIG_NET_VENDOR_EMULEX is not set | ||
| 471 | # CONFIG_NET_VENDOR_EZCHIP is not set | ||
| 472 | # CONFIG_NET_VENDOR_GOOGLE is not set | ||
| 473 | # CONFIG_NET_VENDOR_HP is not set | ||
| 474 | # CONFIG_NET_VENDOR_HUAWEI is not set | ||
| 455 | # CONFIG_NET_VENDOR_INTEL is not set | 475 | # CONFIG_NET_VENDOR_INTEL is not set |
| 456 | # CONFIG_NET_VENDOR_MARVELL is not set | 476 | # CONFIG_NET_VENDOR_MARVELL is not set |
| 457 | CONFIG_MLX4_EN=m | 477 | CONFIG_MLX4_EN=m |
| 458 | CONFIG_MLX5_CORE=m | 478 | CONFIG_MLX5_CORE=m |
| 459 | CONFIG_MLX5_CORE_EN=y | 479 | CONFIG_MLX5_CORE_EN=y |
| 480 | # CONFIG_MLXFW is not set | ||
| 481 | # CONFIG_NET_VENDOR_MICREL is not set | ||
| 482 | # CONFIG_NET_VENDOR_MICROCHIP is not set | ||
| 483 | # CONFIG_NET_VENDOR_MICROSEMI is not set | ||
| 484 | # CONFIG_NET_VENDOR_MYRI is not set | ||
| 460 | # CONFIG_NET_VENDOR_NATSEMI is not set | 485 | # CONFIG_NET_VENDOR_NATSEMI is not set |
| 486 | # CONFIG_NET_VENDOR_NETERION is not set | ||
| 487 | # CONFIG_NET_VENDOR_NETRONOME is not set | ||
| 488 | # CONFIG_NET_VENDOR_NI is not set | ||
| 489 | # CONFIG_NET_VENDOR_NVIDIA is not set | ||
| 490 | # CONFIG_NET_VENDOR_OKI is not set | ||
| 491 | # CONFIG_NET_VENDOR_PACKET_ENGINES is not set | ||
| 492 | # CONFIG_NET_VENDOR_QLOGIC is not set | ||
| 493 | # CONFIG_NET_VENDOR_QUALCOMM is not set | ||
| 494 | # CONFIG_NET_VENDOR_RDC is not set | ||
| 495 | # CONFIG_NET_VENDOR_REALTEK is not set | ||
| 496 | # CONFIG_NET_VENDOR_RENESAS is not set | ||
| 497 | # CONFIG_NET_VENDOR_ROCKER is not set | ||
| 498 | # CONFIG_NET_VENDOR_SAMSUNG is not set | ||
| 499 | # CONFIG_NET_VENDOR_SEEQ is not set | ||
| 500 | # CONFIG_NET_VENDOR_SOLARFLARE is not set | ||
| 501 | # CONFIG_NET_VENDOR_SILAN is not set | ||
| 502 | # CONFIG_NET_VENDOR_SIS is not set | ||
| 503 | # CONFIG_NET_VENDOR_SMSC is not set | ||
| 504 | # CONFIG_NET_VENDOR_SOCIONEXT is not set | ||
| 505 | # CONFIG_NET_VENDOR_STMICRO is not set | ||
| 506 | # CONFIG_NET_VENDOR_SUN is not set | ||
| 507 | # CONFIG_NET_VENDOR_SYNOPSYS is not set | ||
| 508 | # CONFIG_NET_VENDOR_TEHUTI is not set | ||
| 509 | # CONFIG_NET_VENDOR_TI is not set | ||
| 510 | # CONFIG_NET_VENDOR_VIA is not set | ||
| 511 | # CONFIG_NET_VENDOR_WIZNET is not set | ||
| 461 | CONFIG_PPP=m | 512 | CONFIG_PPP=m |
| 462 | CONFIG_PPP_BSDCOMP=m | 513 | CONFIG_PPP_BSDCOMP=m |
| 463 | CONFIG_PPP_DEFLATE=m | 514 | CONFIG_PPP_DEFLATE=m |
| 515 | CONFIG_PPP_FILTER=y | ||
| 464 | CONFIG_PPP_MPPE=m | 516 | CONFIG_PPP_MPPE=m |
| 517 | CONFIG_PPP_MULTILINK=y | ||
| 465 | CONFIG_PPPOE=m | 518 | CONFIG_PPPOE=m |
| 466 | CONFIG_PPTP=m | 519 | CONFIG_PPTP=m |
| 467 | CONFIG_PPPOL2TP=m | 520 | CONFIG_PPPOL2TP=m |
| @@ -473,10 +526,13 @@ CONFIG_INPUT_EVDEV=y · 5 unmodified lines | |||
| 473 | # CONFIG_INPUT_MOUSE is not set | 526 | # CONFIG_INPUT_MOUSE is not set |
| 474 | # CONFIG_SERIO is not set | 527 | # CONFIG_SERIO is not set |
| 475 | CONFIG_LEGACY_PTY_COUNT=0 | 528 | CONFIG_LEGACY_PTY_COUNT=0 |
| 529 | CONFIG_NULL_TTY=m | ||
| 476 | CONFIG_HW_RANDOM_VIRTIO=m | 530 | CONFIG_HW_RANDOM_VIRTIO=m |
| 477 | CONFIG_RAW_DRIVER=m | 531 | CONFIG_RAW_DRIVER=m |
| 478 | CONFIG_HANGCHECK_TIMER=m | 532 | CONFIG_HANGCHECK_TIMER=m |
| 479 | CONFIG_TN3270_FS=y | 533 | CONFIG_TN3270_FS=y |
| 534 | CONFIG_PPS=m | ||
| 535 | # CONFIG_PTP_1588_CLOCK is not set | ||
| 480 | # CONFIG_HWMON is not set | 536 | # CONFIG_HWMON is not set |
| 481 | CONFIG_WATCHDOG=y | 537 | CONFIG_WATCHDOG=y |
| 482 | CONFIG_WATCHDOG_NOWAYOUT=y | 538 | CONFIG_WATCHDOG_NOWAYOUT=y |
| @@ -498,8 +554,8 @@ CONFIG_VFIO_MDEV_DEVICE=m · 15 unmodified lines | |||
| 498 | CONFIG_VIRTIO_PCI=m | 554 | CONFIG_VIRTIO_PCI=m |
| 499 | CONFIG_VIRTIO_BALLOON=m | 555 | CONFIG_VIRTIO_BALLOON=m |
| 500 | CONFIG_VIRTIO_INPUT=y | 556 | CONFIG_VIRTIO_INPUT=y |
| 501 | CONFIG_S390_AP_IOMMU=y | ||
| 502 | CONFIG_S390_CCW_IOMMU=y | 557 | CONFIG_S390_CCW_IOMMU=y |
| 558 | CONFIG_S390_AP_IOMMU=y | ||
| 503 | CONFIG_EXT4_FS=y | 559 | CONFIG_EXT4_FS=y |
| 504 | CONFIG_EXT4_FS_POSIX_ACL=y | 560 | CONFIG_EXT4_FS_POSIX_ACL=y |
| 505 | CONFIG_EXT4_FS_SECURITY=y | 561 | CONFIG_EXT4_FS_SECURITY=y |
| @@ -519,6 +575,7 @@ CONFIG_OCFS2_FS=m · 13 unmodified lines | |||
| 519 | CONFIG_BTRFS_FS=y | 575 | CONFIG_BTRFS_FS=y |
| 520 | CONFIG_BTRFS_FS_POSIX_ACL=y | 576 | CONFIG_BTRFS_FS_POSIX_ACL=y |
| 521 | CONFIG_BTRFS_DEBUG=y | 577 | CONFIG_BTRFS_DEBUG=y |
| 578 | CONFIG_BTRFS_ASSERT=y | ||
| 522 | CONFIG_NILFS2_FS=m | 579 | CONFIG_NILFS2_FS=m |
| 523 | CONFIG_FS_DAX=y | 580 | CONFIG_FS_DAX=y |
| 524 | CONFIG_EXPORTFS_BLOCK_OPS=y | 581 | CONFIG_EXPORTFS_BLOCK_OPS=y |
| @@ -552,8 +609,10 @@ CONFIG_ECRYPT_FS=m · 27 unmodified lines | |||
| 552 | CONFIG_CRAMFS=m | 609 | CONFIG_CRAMFS=m |
| 553 | CONFIG_SQUASHFS=m | 610 | CONFIG_SQUASHFS=m |
| 554 | CONFIG_SQUASHFS_XATTR=y | 611 | CONFIG_SQUASHFS_XATTR=y |
| 612 | CONFIG_SQUASHFS_LZ4=y | ||
| 555 | CONFIG_SQUASHFS_LZO=y | 613 | CONFIG_SQUASHFS_LZO=y |
| 556 | CONFIG_SQUASHFS_XZ=y | 614 | CONFIG_SQUASHFS_XZ=y |
| 615 | CONFIG_SQUASHFS_ZSTD=y | ||
| 557 | CONFIG_ROMFS_FS=m | 616 | CONFIG_ROMFS_FS=m |
| 558 | CONFIG_NFS_FS=m | 617 | CONFIG_NFS_FS=m |
| 559 | CONFIG_NFS_V3_ACL=y | 618 | CONFIG_NFS_V3_ACL=y |
| @@ -564,7 +623,6 @@ CONFIG_NFSD_V3_ACL=y · 4 unmodified lines | |||
| 564 | CONFIG_NFSD_V4=y | 623 | CONFIG_NFSD_V4=y |
| 565 | CONFIG_NFSD_V4_SECURITY_LABEL=y | 624 | CONFIG_NFSD_V4_SECURITY_LABEL=y |
| 566 | CONFIG_CIFS=m | 625 | CONFIG_CIFS=m |
| 567 | CONFIG_CIFS_STATS=y | ||
| 568 | CONFIG_CIFS_STATS2=y | 626 | CONFIG_CIFS_STATS2=y |
| 569 | CONFIG_CIFS_WEAK_PW_HASH=y | 627 | CONFIG_CIFS_WEAK_PW_HASH=y |
| 570 | CONFIG_CIFS_UPCALL=y | 628 | CONFIG_CIFS_UPCALL=y |
| @@ -580,19 +638,112 @@ CONFIG_NLS_ISO8859_1=m · 9 unmodified lines | |||
| 580 | CONFIG_NLS_ISO8859_15=m | 638 | CONFIG_NLS_ISO8859_15=m |
| 581 | CONFIG_NLS_UTF8=m | 639 | CONFIG_NLS_UTF8=m |
| 582 | CONFIG_DLM=m | 640 | CONFIG_DLM=m |
| 641 | CONFIG_UNICODE=y | ||
| 642 | CONFIG_PERSISTENT_KEYRINGS=y | ||
| 643 | CONFIG_BIG_KEYS=y | ||
| 644 | CONFIG_ENCRYPTED_KEYS=m | ||
| 645 | CONFIG_SECURITY=y | ||
| 646 | CONFIG_SECURITY_NETWORK=y | ||
| 647 | CONFIG_FORTIFY_SOURCE=y | ||
| 648 | CONFIG_SECURITY_SELINUX=y | ||
| 649 | CONFIG_SECURITY_SELINUX_BOOTPARAM=y | ||
| 650 | CONFIG_SECURITY_SELINUX_DISABLE=y | ||
| 651 | CONFIG_INTEGRITY_SIGNATURE=y | ||
| 652 | CONFIG_INTEGRITY_ASYMMETRIC_KEYS=y | ||
| 653 | CONFIG_IMA=y | ||
| 654 | CONFIG_IMA_DEFAULT_HASH_SHA256=y | ||
| 655 | CONFIG_IMA_WRITE_POLICY=y | ||
| 656 | CONFIG_IMA_APPRAISE=y | ||
| 657 | CONFIG_CRYPTO_USER=m | ||
| 658 | # CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set | ||
| 659 | CONFIG_CRYPTO_PCRYPT=m | ||
| 660 | CONFIG_CRYPTO_CRYPTD=m | ||
| 661 | CONFIG_CRYPTO_TEST=m | ||
| 662 | CONFIG_CRYPTO_DH=m | ||
| 663 | CONFIG_CRYPTO_ECDH=m | ||
| 664 | CONFIG_CRYPTO_ECRDSA=m | ||
| 665 | CONFIG_CRYPTO_CHACHA20POLY1305=m | ||
| 666 | CONFIG_CRYPTO_AEGIS128=m | ||
| 667 | CONFIG_CRYPTO_AEGIS128L=m | ||
| 668 | CONFIG_CRYPTO_AEGIS256=m | ||
| 669 | CONFIG_CRYPTO_MORUS640=m | ||
| 670 | CONFIG_CRYPTO_MORUS1280=m | ||
| 671 | CONFIG_CRYPTO_CFB=m | ||
| 672 | CONFIG_CRYPTO_LRW=m | ||
| 673 | CONFIG_CRYPTO_PCBC=m | ||
| 674 | CONFIG_CRYPTO_KEYWRAP=m | ||
| 675 | CONFIG_CRYPTO_ADIANTUM=m | ||
| 676 | CONFIG_CRYPTO_XCBC=m | ||
| 677 | CONFIG_CRYPTO_VMAC=m | ||
| 678 | CONFIG_CRYPTO_CRC32=m | ||
| 679 | CONFIG_CRYPTO_XXHASH=m | ||
| 680 | CONFIG_CRYPTO_MICHAEL_MIC=m | ||
| 681 | CONFIG_CRYPTO_RMD128=m | ||
| 682 | CONFIG_CRYPTO_RMD160=m | ||
| 683 | CONFIG_CRYPTO_RMD256=m | ||
| 684 | CONFIG_CRYPTO_RMD320=m | ||
| 685 | CONFIG_CRYPTO_SHA3=m | ||
| 686 | CONFIG_CRYPTO_SM3=m | ||
| 687 | CONFIG_CRYPTO_TGR192=m | ||
| 688 | CONFIG_CRYPTO_WP512=m | ||
| 689 | CONFIG_CRYPTO_AES_TI=m | ||
| 690 | CONFIG_CRYPTO_ANUBIS=m | ||
| 691 | CONFIG_CRYPTO_ARC4=m | ||
| 692 | CONFIG_CRYPTO_BLOWFISH=m | ||
| 693 | CONFIG_CRYPTO_CAMELLIA=m | ||
| 694 | CONFIG_CRYPTO_CAST5=m | ||
| 695 | CONFIG_CRYPTO_CAST6=m | ||
| 696 | CONFIG_CRYPTO_FCRYPT=m | ||
| 697 | CONFIG_CRYPTO_KHAZAD=m | ||
| 698 | CONFIG_CRYPTO_SALSA20=m | ||
| 699 | CONFIG_CRYPTO_SEED=m | ||
| 700 | CONFIG_CRYPTO_SERPENT=m | ||
| 701 | CONFIG_CRYPTO_SM4=m | ||
| 702 | CONFIG_CRYPTO_TEA=m | ||
| 703 | CONFIG_CRYPTO_TWOFISH=m | ||
| 704 | CONFIG_CRYPTO_842=m | ||
| 705 | CONFIG_CRYPTO_LZ4=m | ||
| 706 | CONFIG_CRYPTO_LZ4HC=m | ||
| 707 | CONFIG_CRYPTO_ZSTD=m | ||
| 708 | CONFIG_CRYPTO_ANSI_CPRNG=m | ||
| 709 | CONFIG_CRYPTO_USER_API_HASH=m | ||
| 710 | CONFIG_CRYPTO_USER_API_SKCIPHER=m | ||
| 711 | CONFIG_CRYPTO_USER_API_RNG=m | ||
| 712 | CONFIG_CRYPTO_USER_API_AEAD=m | ||
| 713 | CONFIG_CRYPTO_STATS=y | ||
| 714 | CONFIG_ZCRYPT=m | ||
| 715 | CONFIG_PKEY=m | ||
| 716 | CONFIG_CRYPTO_PAES_S390=m | ||
| 717 | CONFIG_CRYPTO_SHA1_S390=m | ||
| 718 | CONFIG_CRYPTO_SHA256_S390=m | ||
| 719 | CONFIG_CRYPTO_SHA512_S390=m | ||
| 720 | CONFIG_CRYPTO_DES_S390=m | ||
| 721 | CONFIG_CRYPTO_AES_S390=m | ||
| 722 | CONFIG_CRYPTO_GHASH_S390=m | ||
| 723 | CONFIG_CRYPTO_CRC32_S390=y | ||
| 724 | CONFIG_CORDIC=m | ||
| 725 | CONFIG_CRC32_SELFTEST=y | ||
| 726 | CONFIG_CRC4=m | ||
| 727 | CONFIG_CRC7=m | ||
| 728 | CONFIG_CRC8=m | ||
| 729 | CONFIG_RANDOM32_SELFTEST=y | ||
| 730 | CONFIG_DMA_CMA=y | ||
| 731 | CONFIG_CMA_SIZE_MBYTES=0 | ||
| 732 | CONFIG_DMA_API_DEBUG=y | ||
| 733 | CONFIG_STRING_SELFTEST=y | ||
| 583 | CONFIG_PRINTK_TIME=y | 734 | CONFIG_PRINTK_TIME=y |
| 584 | CONFIG_DYNAMIC_DEBUG=y | 735 | CONFIG_DYNAMIC_DEBUG=y |
| 585 | CONFIG_DEBUG_INFO=y | 736 | CONFIG_DEBUG_INFO=y |
| 586 | CONFIG_DEBUG_INFO_DWARF4=y | 737 | CONFIG_DEBUG_INFO_DWARF4=y |
| 587 | CONFIG_GDB_SCRIPTS=y | 738 | CONFIG_GDB_SCRIPTS=y |
| 588 | CONFIG_FRAME_WARN=1024 | 739 | CONFIG_FRAME_WARN=1024 |
| 589 | CONFIG_READABLE_ASM=y | ||
| 590 | CONFIG_UNUSED_SYMBOLS=y | 740 | CONFIG_UNUSED_SYMBOLS=y |
| 591 | CONFIG_HEADERS_INSTALL=y | 741 | CONFIG_HEADERS_INSTALL=y |
| 592 | CONFIG_HEADERS_CHECK=y | 742 | CONFIG_HEADERS_CHECK=y |
| 593 | CONFIG_DEBUG_SECTION_MISMATCH=y | 743 | CONFIG_DEBUG_SECTION_MISMATCH=y |
| 594 | CONFIG_MAGIC_SYSRQ=y | 744 | CONFIG_MAGIC_SYSRQ=y |
| 595 | CONFIG_DEBUG_PAGEALLOC=y | 745 | CONFIG_DEBUG_PAGEALLOC=y |
| 746 | CONFIG_PAGE_OWNER=y | ||
| 596 | CONFIG_DEBUG_RODATA_TEST=y | 747 | CONFIG_DEBUG_RODATA_TEST=y |
| 597 | CONFIG_DEBUG_OBJECTS=y | 748 | CONFIG_DEBUG_OBJECTS=y |
| 598 | CONFIG_DEBUG_OBJECTS_SELFTEST=y | 749 | CONFIG_DEBUG_OBJECTS_SELFTEST=y |
| @@ -645,7 +796,6 @@ CONFIG_STACK_TRACER=y · 46 unmodified lines | |||
| 645 | CONFIG_BLK_DEV_IO_TRACE=y | 796 | CONFIG_BLK_DEV_IO_TRACE=y |
| 646 | CONFIG_FUNCTION_PROFILER=y | 797 | CONFIG_FUNCTION_PROFILER=y |
| 647 | CONFIG_HIST_TRIGGERS=y | 798 | CONFIG_HIST_TRIGGERS=y |
| 648 | CONFIG_DMA_API_DEBUG=y | ||
| 649 | CONFIG_LKDTM=m | 799 | CONFIG_LKDTM=m |
| 650 | CONFIG_TEST_LIST_SORT=y | 800 | CONFIG_TEST_LIST_SORT=y |
| 651 | CONFIG_TEST_SORT=y | 801 | CONFIG_TEST_SORT=y |
| @@ -657,85 +807,3 @@ CONFIG_ATOMIC64_SELFTEST=y · 5 unmodified lines | |||
| 657 | CONFIG_TEST_BPF=m | 807 | CONFIG_TEST_BPF=m |
| 658 | CONFIG_BUG_ON_DATA_CORRUPTION=y | 808 | CONFIG_BUG_ON_DATA_CORRUPTION=y |
| 659 | CONFIG_S390_PTDUMP=y | 809 | CONFIG_S390_PTDUMP=y |
| 660 | CONFIG_PERSISTENT_KEYRINGS=y | ||
| 661 | CONFIG_BIG_KEYS=y | ||
| 662 | CONFIG_ENCRYPTED_KEYS=m | ||
| 663 | CONFIG_SECURITY=y | ||
| 664 | CONFIG_SECURITY_NETWORK=y | ||
| 665 | CONFIG_FORTIFY_SOURCE=y | ||
| 666 | CONFIG_SECURITY_SELINUX=y | ||
| 667 | CONFIG_SECURITY_SELINUX_BOOTPARAM=y | ||
| 668 | CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=0 | ||
| 669 | CONFIG_SECURITY_SELINUX_DISABLE=y | ||
| 670 | CONFIG_INTEGRITY_SIGNATURE=y | ||
| 671 | CONFIG_INTEGRITY_ASYMMETRIC_KEYS=y | ||
| 672 | CONFIG_IMA=y | ||
| 673 | CONFIG_IMA_DEFAULT_HASH_SHA256=y | ||
| 674 | CONFIG_IMA_WRITE_POLICY=y | ||
| 675 | CONFIG_IMA_APPRAISE=y | ||
| 676 | CONFIG_CRYPTO_DH=m | ||
| 677 | CONFIG_CRYPTO_ECDH=m | ||
| 678 | CONFIG_CRYPTO_USER=m | ||
| 679 | # CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set | ||
| 680 | CONFIG_CRYPTO_PCRYPT=m | ||
| 681 | CONFIG_CRYPTO_CRYPTD=m | ||
| 682 | CONFIG_CRYPTO_TEST=m | ||
| 683 | CONFIG_CRYPTO_CHACHA20POLY1305=m | ||
| 684 | CONFIG_CRYPTO_LRW=m | ||
| 685 | CONFIG_CRYPTO_PCBC=m | ||
| 686 | CONFIG_CRYPTO_KEYWRAP=m | ||
| 687 | CONFIG_CRYPTO_XCBC=m | ||
| 688 | CONFIG_CRYPTO_VMAC=m | ||
| 689 | CONFIG_CRYPTO_CRC32=m | ||
| 690 | CONFIG_CRYPTO_MICHAEL_MIC=m | ||
| 691 | CONFIG_CRYPTO_RMD128=m | ||
| 692 | CONFIG_CRYPTO_RMD160=m | ||
| 693 | CONFIG_CRYPTO_RMD256=m | ||
| 694 | CONFIG_CRYPTO_RMD320=m | ||
| 695 | CONFIG_CRYPTO_SHA512=m | ||
| 696 | CONFIG_CRYPTO_SHA3=m | ||
| 697 | CONFIG_CRYPTO_TGR192=m | ||
| 698 | CONFIG_CRYPTO_WP512=m | ||
| 699 | CONFIG_CRYPTO_AES_TI=m | ||
| 700 | CONFIG_CRYPTO_ANUBIS=m | ||
| 701 | CONFIG_CRYPTO_BLOWFISH=m | ||
| 702 | CONFIG_CRYPTO_CAMELLIA=m | ||
| 703 | CONFIG_CRYPTO_CAST5=m | ||
| 704 | CONFIG_CRYPTO_CAST6=m | ||
| 705 | CONFIG_CRYPTO_FCRYPT=m | ||
| 706 | CONFIG_CRYPTO_KHAZAD=m | ||
| 707 | CONFIG_CRYPTO_SALSA20=m | ||
| 708 | CONFIG_CRYPTO_SEED=m | ||
| 709 | CONFIG_CRYPTO_SERPENT=m | ||
| 710 | CONFIG_CRYPTO_TEA=m | ||
| 711 | CONFIG_CRYPTO_TWOFISH=m | ||
| 712 | CONFIG_CRYPTO_842=m | ||
| 713 | CONFIG_CRYPTO_LZ4=m | ||
| 714 | CONFIG_CRYPTO_LZ4HC=m | ||
| 715 | CONFIG_CRYPTO_ANSI_CPRNG=m | ||
| 716 | CONFIG_CRYPTO_USER_API_HASH=m | ||
| 717 | CONFIG_CRYPTO_USER_API_SKCIPHER=m | ||
| 718 | CONFIG_CRYPTO_USER_API_RNG=m | ||
| 719 | CONFIG_CRYPTO_USER_API_AEAD=m | ||
| 720 | CONFIG_ZCRYPT=m | ||
| 721 | CONFIG_PKEY=m | ||
| 722 | CONFIG_CRYPTO_PAES_S390=m | ||
| 723 | CONFIG_CRYPTO_SHA1_S390=m | ||
| 724 | CONFIG_CRYPTO_SHA256_S390=m | ||
| 725 | CONFIG_CRYPTO_SHA512_S390=m | ||
| 726 | CONFIG_CRYPTO_DES_S390=m | ||
| 727 | CONFIG_CRYPTO_AES_S390=m | ||
| 728 | CONFIG_CRYPTO_GHASH_S390=m | ||
| 729 | CONFIG_CRYPTO_CRC32_S390=y | ||
| 730 | CONFIG_PKCS7_MESSAGE_PARSER=y | ||
| 731 | CONFIG_SYSTEM_TRUSTED_KEYRING=y | ||
| 732 | CONFIG_CRC7=m | ||
| 733 | CONFIG_CRC8=m | ||
| 734 | CONFIG_RANDOM32_SELFTEST=y | ||
| 735 | CONFIG_CORDIC=m | ||
| 736 | CONFIG_CMM=m | ||
| 737 | CONFIG_APPLDATA_BASE=y | ||
| 738 | CONFIG_KVM=m | ||
| 739 | CONFIG_KVM_S390_UCONTROL=y | ||
| 740 | CONFIG_VHOST_NET=m | ||
| 741 | CONFIG_VHOST_VSOCK=m | ||
| @@ -12,30 +12,51 @@ CONFIG_TASK_IO_ACCOUNTING=y · 11 unmodified lines | |||
| 12 | CONFIG_IKCONFIG=y | 12 | CONFIG_IKCONFIG=y |
| 13 | CONFIG_IKCONFIG_PROC=y | 13 | CONFIG_IKCONFIG_PROC=y |
| 14 | CONFIG_NUMA_BALANCING=y | 14 | CONFIG_NUMA_BALANCING=y |
| 15 | # CONFIG_NUMA_BALANCING_DEFAULT_ENABLED is not set | ||
| 16 | CONFIG_MEMCG=y | 15 | CONFIG_MEMCG=y |
| 17 | CONFIG_MEMCG_SWAP=y | 16 | CONFIG_MEMCG_SWAP=y |
| 18 | CONFIG_BLK_CGROUP=y | 17 | CONFIG_BLK_CGROUP=y |
| 19 | CONFIG_CFS_BANDWIDTH=y | 18 | CONFIG_CFS_BANDWIDTH=y |
| 20 | CONFIG_RT_GROUP_SCHED=y | 19 | CONFIG_RT_GROUP_SCHED=y |
| 21 | CONFIG_CGROUP_PIDS=y | 20 | CONFIG_CGROUP_PIDS=y |
| 21 | CONFIG_CGROUP_RDMA=y | ||
| 22 | CONFIG_CGROUP_FREEZER=y | 22 | CONFIG_CGROUP_FREEZER=y |
| 23 | CONFIG_CGROUP_HUGETLB=y | 23 | CONFIG_CGROUP_HUGETLB=y |
| 24 | CONFIG_CPUSETS=y | 24 | CONFIG_CPUSETS=y |
| 25 | CONFIG_CGROUP_DEVICE=y | 25 | CONFIG_CGROUP_DEVICE=y |
| 26 | CONFIG_CGROUP_CPUACCT=y | 26 | CONFIG_CGROUP_CPUACCT=y |
| 27 | CONFIG_CGROUP_PERF=y | 27 | CONFIG_CGROUP_PERF=y |
| 28 | CONFIG_CGROUP_BPF=y | ||
| 28 | CONFIG_NAMESPACES=y | 29 | CONFIG_NAMESPACES=y |
| 29 | CONFIG_USER_NS=y | 30 | CONFIG_USER_NS=y |
| 31 | CONFIG_CHECKPOINT_RESTORE=y | ||
| 30 | CONFIG_SCHED_AUTOGROUP=y | 32 | CONFIG_SCHED_AUTOGROUP=y |
| 31 | CONFIG_BLK_DEV_INITRD=y | 33 | CONFIG_BLK_DEV_INITRD=y |
| 32 | CONFIG_EXPERT=y | 34 | CONFIG_EXPERT=y |
| 33 | # CONFIG_SYSFS_SYSCALL is not set | 35 | # CONFIG_SYSFS_SYSCALL is not set |
| 34 | CONFIG_CHECKPOINT_RESTORE=y | ||
| 35 | CONFIG_BPF_SYSCALL=y | 36 | CONFIG_BPF_SYSCALL=y |
| 36 | CONFIG_USERFAULTFD=y | 37 | CONFIG_USERFAULTFD=y |
| 37 | # CONFIG_COMPAT_BRK is not set | 38 | # CONFIG_COMPAT_BRK is not set |
| 38 | CONFIG_PROFILING=y | 39 | CONFIG_PROFILING=y |
| 40 | CONFIG_LIVEPATCH=y | ||
| 41 | CONFIG_TUNE_ZEC12=y | ||
| 42 | CONFIG_NR_CPUS=512 | ||
| 43 | CONFIG_NUMA=y | ||
| 44 | # CONFIG_NUMA_EMU is not set | ||
| 45 | CONFIG_HZ_100=y | ||
| 46 | CONFIG_KEXEC_FILE=y | ||
| 47 | CONFIG_EXPOLINE=y | ||
| 48 | CONFIG_EXPOLINE_AUTO=y | ||
| 49 | CONFIG_CHSC_SCH=y | ||
| 50 | CONFIG_VFIO_CCW=m | ||
| 51 | CONFIG_VFIO_AP=m | ||
| 52 | CONFIG_CRASH_DUMP=y | ||
| 53 | CONFIG_HIBERNATION=y | ||
| 54 | CONFIG_PM_DEBUG=y | ||
| 55 | CONFIG_CMM=m | ||
| 56 | CONFIG_APPLDATA_BASE=y | ||
| 57 | CONFIG_KVM=m | ||
| 58 | CONFIG_VHOST_NET=m | ||
| 59 | CONFIG_VHOST_VSOCK=m | ||
| 39 | CONFIG_OPROFILE=m | 60 | CONFIG_OPROFILE=m |
| 40 | CONFIG_KPROBES=y | 61 | CONFIG_KPROBES=y |
| 41 | CONFIG_JUMP_LABEL=y | 62 | CONFIG_JUMP_LABEL=y |
| @@ -47,27 +68,18 @@ CONFIG_MODVERSIONS=y · 5 unmodified lines | |||
| 47 | CONFIG_MODULE_SRCVERSION_ALL=y | 68 | CONFIG_MODULE_SRCVERSION_ALL=y |
| 48 | CONFIG_MODULE_SIG=y | 69 | CONFIG_MODULE_SIG=y |
| 49 | CONFIG_MODULE_SIG_SHA256=y | 70 | CONFIG_MODULE_SIG_SHA256=y |
| 50 | CONFIG_BLK_DEV_INTEGRITY=y | ||
| 51 | CONFIG_BLK_DEV_THROTTLING=y | 71 | CONFIG_BLK_DEV_THROTTLING=y |
| 52 | CONFIG_BLK_WBT=y | 72 | CONFIG_BLK_WBT=y |
| 53 | CONFIG_BLK_WBT_SQ=y | 73 | CONFIG_BLK_CGROUP_IOLATENCY=y |
| 54 | CONFIG_PARTITION_ADVANCED=y | 74 | CONFIG_PARTITION_ADVANCED=y |
| 55 | CONFIG_IBM_PARTITION=y | 75 | CONFIG_IBM_PARTITION=y |
| 56 | CONFIG_BSD_DISKLABEL=y | 76 | CONFIG_BSD_DISKLABEL=y |
| 57 | CONFIG_MINIX_SUBPARTITION=y | 77 | CONFIG_MINIX_SUBPARTITION=y |
| 58 | CONFIG_SOLARIS_X86_PARTITION=y | 78 | CONFIG_SOLARIS_X86_PARTITION=y |
| 59 | CONFIG_UNIXWARE_DISKLABEL=y | 79 | CONFIG_UNIXWARE_DISKLABEL=y |
| 60 | CONFIG_CFQ_GROUP_IOSCHED=y | 80 | CONFIG_IOSCHED_BFQ=y |
| 61 | CONFIG_DEFAULT_DEADLINE=y | 81 | CONFIG_BFQ_GROUP_IOSCHED=y |
| 62 | CONFIG_LIVEPATCH=y | 82 | CONFIG_BINFMT_MISC=m |
| 63 | CONFIG_TUNE_ZEC12=y | ||
| 64 | CONFIG_NR_CPUS=512 | ||
| 65 | CONFIG_NUMA=y | ||
| 66 | CONFIG_HZ_100=y | ||
| 67 | CONFIG_KEXEC_FILE=y | ||
| 68 | CONFIG_KEXEC_VERIFY_SIG=y | ||
| 69 | CONFIG_EXPOLINE=y | ||
| 70 | CONFIG_EXPOLINE_AUTO=y | ||
| 71 | CONFIG_MEMORY_HOTPLUG=y | 83 | CONFIG_MEMORY_HOTPLUG=y |
| 72 | CONFIG_MEMORY_HOTREMOVE=y | 84 | CONFIG_MEMORY_HOTREMOVE=y |
| 73 | CONFIG_KSM=y | 85 | CONFIG_KSM=y |
| @@ -81,16 +93,8 @@ CONFIG_ZSMALLOC=m · 7 unmodified lines | |||
| 81 | CONFIG_ZSMALLOC_STAT=y | 93 | CONFIG_ZSMALLOC_STAT=y |
| 82 | CONFIG_DEFERRED_STRUCT_PAGE_INIT=y | 94 | CONFIG_DEFERRED_STRUCT_PAGE_INIT=y |
| 83 | CONFIG_IDLE_PAGE_TRACKING=y | 95 | CONFIG_IDLE_PAGE_TRACKING=y |
| 84 | CONFIG_PCI=y | 96 | CONFIG_PERCPU_STATS=y |
| 85 | CONFIG_HOTPLUG_PCI=y | 97 | CONFIG_GUP_BENCHMARK=y |
| 86 | CONFIG_HOTPLUG_PCI_S390=y | ||
| 87 | CONFIG_CHSC_SCH=y | ||
| 88 | CONFIG_VFIO_AP=m | ||
| 89 | CONFIG_VFIO_CCW=m | ||
| 90 | CONFIG_CRASH_DUMP=y | ||
| 91 | CONFIG_BINFMT_MISC=m | ||
| 92 | CONFIG_HIBERNATION=y | ||
| 93 | CONFIG_PM_DEBUG=y | ||
| 94 | CONFIG_NET=y | 98 | CONFIG_NET=y |
| 95 | CONFIG_PACKET=y | 99 | CONFIG_PACKET=y |
| 96 | CONFIG_PACKET_DIAG=m | 100 | CONFIG_PACKET_DIAG=m |
| @@ -119,9 +123,6 @@ CONFIG_NET_IPVTI=m · 22 unmodified lines | |||
| 119 | CONFIG_INET_AH=m | 123 | CONFIG_INET_AH=m |
| 120 | CONFIG_INET_ESP=m | 124 | CONFIG_INET_ESP=m |
| 121 | CONFIG_INET_IPCOMP=m | 125 | CONFIG_INET_IPCOMP=m |
| 122 | CONFIG_INET_XFRM_MODE_TRANSPORT=m | ||
| 123 | CONFIG_INET_XFRM_MODE_TUNNEL=m | ||
| 124 | CONFIG_INET_XFRM_MODE_BEET=m | ||
| 125 | CONFIG_INET_DIAG=m | 126 | CONFIG_INET_DIAG=m |
| 126 | CONFIG_INET_UDP_DIAG=m | 127 | CONFIG_INET_UDP_DIAG=m |
| 127 | CONFIG_TCP_CONG_ADVANCED=y | 128 | CONFIG_TCP_CONG_ADVANCED=y |
| @@ -137,10 +138,6 @@ CONFIG_INET6_AH=m · 9 unmodified lines | |||
| 137 | CONFIG_INET6_ESP=m | 138 | CONFIG_INET6_ESP=m |
| 138 | CONFIG_INET6_IPCOMP=m | 139 | CONFIG_INET6_IPCOMP=m |
| 139 | CONFIG_IPV6_MIP6=m | 140 | CONFIG_IPV6_MIP6=m |
| 140 | CONFIG_INET6_XFRM_MODE_TRANSPORT=m | ||
| 141 | CONFIG_INET6_XFRM_MODE_TUNNEL=m | ||
| 142 | CONFIG_INET6_XFRM_MODE_BEET=m | ||
| 143 | CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m | ||
| 144 | CONFIG_IPV6_VTI=m | 141 | CONFIG_IPV6_VTI=m |
| 145 | CONFIG_IPV6_SIT=m | 142 | CONFIG_IPV6_SIT=m |
| 146 | CONFIG_IPV6_GRE=m | 143 | CONFIG_IPV6_GRE=m |
| @@ -262,11 +259,8 @@ CONFIG_IP_VS_SED=m · 115 unmodified lines | |||
| 262 | CONFIG_IP_VS_NQ=m | 259 | CONFIG_IP_VS_NQ=m |
| 263 | CONFIG_IP_VS_FTP=m | 260 | CONFIG_IP_VS_FTP=m |
| 264 | CONFIG_IP_VS_PE_SIP=m | 261 | CONFIG_IP_VS_PE_SIP=m |
| 265 | CONFIG_NF_CONNTRACK_IPV4=m | ||
| 266 | CONFIG_NF_TABLES_IPV4=y | 262 | CONFIG_NF_TABLES_IPV4=y |
| 267 | CONFIG_NFT_CHAIN_ROUTE_IPV4=m | ||
| 268 | CONFIG_NF_TABLES_ARP=y | 263 | CONFIG_NF_TABLES_ARP=y |
| 269 | CONFIG_NFT_CHAIN_NAT_IPV4=m | ||
| 270 | CONFIG_IP_NF_IPTABLES=m | 264 | CONFIG_IP_NF_IPTABLES=m |
| 271 | CONFIG_IP_NF_MATCH_AH=m | 265 | CONFIG_IP_NF_MATCH_AH=m |
| 272 | CONFIG_IP_NF_MATCH_ECN=m | 266 | CONFIG_IP_NF_MATCH_ECN=m |
| @@ -285,10 +279,7 @@ CONFIG_IP_NF_SECURITY=m · 12 unmodified lines | |||
| 285 | CONFIG_IP_NF_ARPTABLES=m | 279 | CONFIG_IP_NF_ARPTABLES=m |
| 286 | CONFIG_IP_NF_ARPFILTER=m | 280 | CONFIG_IP_NF_ARPFILTER=m |
| 287 | CONFIG_IP_NF_ARP_MANGLE=m | 281 | CONFIG_IP_NF_ARP_MANGLE=m |
| 288 | CONFIG_NF_CONNTRACK_IPV6=m | ||
| 289 | CONFIG_NF_TABLES_IPV6=y | 282 | CONFIG_NF_TABLES_IPV6=y |
| 290 | CONFIG_NFT_CHAIN_ROUTE_IPV6=m | ||
| 291 | CONFIG_NFT_CHAIN_NAT_IPV6=m | ||
| 292 | CONFIG_IP6_NF_IPTABLES=m | 283 | CONFIG_IP6_NF_IPTABLES=m |
| 293 | CONFIG_IP6_NF_MATCH_AH=m | 284 | CONFIG_IP6_NF_MATCH_AH=m |
| 294 | CONFIG_IP6_NF_MATCH_EUI64=m | 285 | CONFIG_IP6_NF_MATCH_EUI64=m |
| @@ -307,7 +298,7 @@ CONFIG_IP6_NF_RAW=m · 12 unmodified lines | |||
| 307 | CONFIG_IP6_NF_SECURITY=m | 298 | CONFIG_IP6_NF_SECURITY=m |
| 308 | CONFIG_IP6_NF_NAT=m | 299 | CONFIG_IP6_NF_NAT=m |
| 309 | CONFIG_IP6_NF_TARGET_MASQUERADE=m | 300 | CONFIG_IP6_NF_TARGET_MASQUERADE=m |
| 310 | CONFIG_NF_TABLES_BRIDGE=y | 301 | CONFIG_NF_TABLES_BRIDGE=m |
| 311 | CONFIG_RDS=m | 302 | CONFIG_RDS=m |
| 312 | CONFIG_RDS_RDMA=m | 303 | CONFIG_RDS_RDMA=m |
| 313 | CONFIG_RDS_TCP=m | 304 | CONFIG_RDS_TCP=m |
| @@ -372,9 +363,11 @@ CONFIG_NETLINK_DIAG=m · 58 unmodified lines | |||
| 372 | CONFIG_CGROUP_NET_PRIO=y | 363 | CONFIG_CGROUP_NET_PRIO=y |
| 373 | CONFIG_BPF_JIT=y | 364 | CONFIG_BPF_JIT=y |
| 374 | CONFIG_NET_PKTGEN=m | 365 | CONFIG_NET_PKTGEN=m |
| 366 | CONFIG_PCI=y | ||
| 367 | CONFIG_HOTPLUG_PCI=y | ||
| 368 | CONFIG_HOTPLUG_PCI_S390=y | ||
| 369 | CONFIG_UEVENT_HELPER=y | ||
| 375 | CONFIG_DEVTMPFS=y | 370 | CONFIG_DEVTMPFS=y |
| 376 | CONFIG_DMA_CMA=y | ||
| 377 | CONFIG_CMA_SIZE_MBYTES=0 | ||
| 378 | CONFIG_CONNECTOR=y | 371 | CONFIG_CONNECTOR=y |
| 379 | CONFIG_ZRAM=m | 372 | CONFIG_ZRAM=m |
| 380 | CONFIG_BLK_DEV_LOOP=m | 373 | CONFIG_BLK_DEV_LOOP=m |
| @@ -383,6 +376,7 @@ CONFIG_BLK_DEV_DRBD=m · 2 unmodified lines | |||
| 383 | CONFIG_BLK_DEV_NBD=m | 376 | CONFIG_BLK_DEV_NBD=m |
| 384 | CONFIG_BLK_DEV_RAM=y | 377 | CONFIG_BLK_DEV_RAM=y |
| 385 | CONFIG_BLK_DEV_RAM_SIZE=32768 | 378 | CONFIG_BLK_DEV_RAM_SIZE=32768 |
| 379 | # CONFIG_BLK_DEV_XPRAM is not set | ||
| 386 | CONFIG_VIRTIO_BLK=y | 380 | CONFIG_VIRTIO_BLK=y |
| 387 | CONFIG_BLK_DEV_RBD=m | 381 | CONFIG_BLK_DEV_RBD=m |
| 388 | CONFIG_BLK_DEV_NVME=m | 382 | CONFIG_BLK_DEV_NVME=m |
| @@ -392,7 +386,6 @@ CONFIG_RAID_ATTRS=m · 3 unmodified lines | |||
| 392 | CONFIG_SCSI=y | 386 | CONFIG_SCSI=y |
| 393 | CONFIG_BLK_DEV_SD=y | 387 | CONFIG_BLK_DEV_SD=y |
| 394 | CONFIG_CHR_DEV_ST=m | 388 | CONFIG_CHR_DEV_ST=m |
| 395 | CONFIG_CHR_DEV_OSST=m | ||
| 396 | CONFIG_BLK_DEV_SR=m | 389 | CONFIG_BLK_DEV_SR=m |
| 397 | CONFIG_CHR_DEV_SG=y | 390 | CONFIG_CHR_DEV_SG=y |
| 398 | CONFIG_CHR_DEV_SCH=m | 391 | CONFIG_CHR_DEV_SCH=m |
| @@ -412,17 +405,19 @@ CONFIG_SCSI_DH_RDAC=m · 13 unmodified lines | |||
| 412 | CONFIG_SCSI_DH_HP_SW=m | 405 | CONFIG_SCSI_DH_HP_SW=m |
| 413 | CONFIG_SCSI_DH_EMC=m | 406 | CONFIG_SCSI_DH_EMC=m |
| 414 | CONFIG_SCSI_DH_ALUA=m | 407 | CONFIG_SCSI_DH_ALUA=m |
| 415 | CONFIG_SCSI_OSD_INITIATOR=m | ||
| 416 | CONFIG_SCSI_OSD_ULD=m | ||
| 417 | CONFIG_MD=y | 408 | CONFIG_MD=y |
| 418 | CONFIG_BLK_DEV_MD=y | 409 | CONFIG_BLK_DEV_MD=y |
| 419 | CONFIG_MD_LINEAR=m | 410 | CONFIG_MD_LINEAR=m |
| 420 | CONFIG_MD_MULTIPATH=m | 411 | CONFIG_MD_MULTIPATH=m |
| 421 | CONFIG_MD_FAULTY=m | 412 | CONFIG_MD_FAULTY=m |
| 413 | CONFIG_MD_CLUSTER=m | ||
| 414 | CONFIG_BCACHE=m | ||
| 422 | CONFIG_BLK_DEV_DM=m | 415 | CONFIG_BLK_DEV_DM=m |
| 416 | CONFIG_DM_UNSTRIPED=m | ||
| 423 | CONFIG_DM_CRYPT=m | 417 | CONFIG_DM_CRYPT=m |
| 424 | CONFIG_DM_SNAPSHOT=m | 418 | CONFIG_DM_SNAPSHOT=m |
| 425 | CONFIG_DM_THIN_PROVISIONING=m | 419 | CONFIG_DM_THIN_PROVISIONING=m |
| 420 | CONFIG_DM_WRITECACHE=m | ||
| 426 | CONFIG_DM_MIRROR=m | 421 | CONFIG_DM_MIRROR=m |
| 427 | CONFIG_DM_LOG_USERSPACE=m | 422 | CONFIG_DM_LOG_USERSPACE=m |
| 428 | CONFIG_DM_RAID=m | 423 | CONFIG_DM_RAID=m |
| @@ -435,6 +430,7 @@ CONFIG_DM_UEVENT=y · 6 unmodified lines | |||
| 435 | CONFIG_DM_FLAKEY=m | 430 | CONFIG_DM_FLAKEY=m |
| 436 | CONFIG_DM_VERITY=m | 431 | CONFIG_DM_VERITY=m |
| 437 | CONFIG_DM_SWITCH=m | 432 | CONFIG_DM_SWITCH=m |
| 433 | CONFIG_DM_INTEGRITY=m | ||
| 438 | CONFIG_NETDEVICES=y | 434 | CONFIG_NETDEVICES=y |
| 439 | CONFIG_BONDING=m | 435 | CONFIG_BONDING=m |
| 440 | CONFIG_DUMMY=m | 436 | CONFIG_DUMMY=m |
| @@ -442,23 +438,78 @@ CONFIG_EQUALIZER=m · 1 unmodified line | |||
| 442 | CONFIG_IFB=m | 438 | CONFIG_IFB=m |
| 443 | CONFIG_MACVLAN=m | 439 | CONFIG_MACVLAN=m |
| 444 | CONFIG_MACVTAP=m | 440 | CONFIG_MACVTAP=m |
| 445 | CONFIG_VXLAN=m | ||
| 446 | CONFIG_TUN=m | 441 | CONFIG_TUN=m |
| 447 | CONFIG_VETH=m | 442 | CONFIG_VETH=m |
| 448 | CONFIG_VIRTIO_NET=m | 443 | CONFIG_VIRTIO_NET=m |
| 449 | CONFIG_NLMON=m | 444 | CONFIG_NLMON=m |
| 445 | # CONFIG_NET_VENDOR_3COM is not set | ||
| 446 | # CONFIG_NET_VENDOR_ADAPTEC is not set | ||
| 447 | # CONFIG_NET_VENDOR_AGERE is not set | ||
| 448 | # CONFIG_NET_VENDOR_ALACRITECH is not set | ||
| 449 | # CONFIG_NET_VENDOR_ALTEON is not set | ||
| 450 | # CONFIG_NET_VENDOR_AMAZON is not set | ||
| 451 | # CONFIG_NET_VENDOR_AMD is not set | ||
| 452 | # CONFIG_NET_VENDOR_AQUANTIA is not set | ||
| 450 | # CONFIG_NET_VENDOR_ARC is not set | 453 | # CONFIG_NET_VENDOR_ARC is not set |
| 454 | # CONFIG_NET_VENDOR_ATHEROS is not set | ||
| 455 | # CONFIG_NET_VENDOR_AURORA is not set | ||
| 456 | # CONFIG_NET_VENDOR_BROADCOM is not set | ||
| 457 | # CONFIG_NET_VENDOR_BROCADE is not set | ||
| 458 | # CONFIG_NET_VENDOR_CADENCE is not set | ||
| 459 | # CONFIG_NET_VENDOR_CAVIUM is not set | ||
| 451 | # CONFIG_NET_VENDOR_CHELSIO is not set | 460 | # CONFIG_NET_VENDOR_CHELSIO is not set |
| 461 | # CONFIG_NET_VENDOR_CISCO is not set | ||
| 462 | # CONFIG_NET_VENDOR_CORTINA is not set | ||
| 463 | # CONFIG_NET_VENDOR_DEC is not set | ||
| 464 | # CONFIG_NET_VENDOR_DLINK is not set | ||
| 465 | # CONFIG_NET_VENDOR_EMULEX is not set | ||
| 466 | # CONFIG_NET_VENDOR_EZCHIP is not set | ||
| 467 | # CONFIG_NET_VENDOR_GOOGLE is not set | ||
| 468 | # CONFIG_NET_VENDOR_HP is not set | ||
| 469 | # CONFIG_NET_VENDOR_HUAWEI is not set | ||
| 452 | # CONFIG_NET_VENDOR_INTEL is not set | 470 | # CONFIG_NET_VENDOR_INTEL is not set |
| 453 | # CONFIG_NET_VENDOR_MARVELL is not set | 471 | # CONFIG_NET_VENDOR_MARVELL is not set |
| 454 | CONFIG_MLX4_EN=m | 472 | CONFIG_MLX4_EN=m |
| 455 | CONFIG_MLX5_CORE=m | 473 | CONFIG_MLX5_CORE=m |
| 456 | CONFIG_MLX5_CORE_EN=y | 474 | CONFIG_MLX5_CORE_EN=y |
| 475 | # CONFIG_MLXFW is not set | ||
| 476 | # CONFIG_NET_VENDOR_MICREL is not set | ||
| 477 | # CONFIG_NET_VENDOR_MICROCHIP is not set | ||
| 478 | # CONFIG_NET_VENDOR_MICROSEMI is not set | ||
| 479 | # CONFIG_NET_VENDOR_MYRI is not set | ||
| 457 | # CONFIG_NET_VENDOR_NATSEMI is not set | 480 | # CONFIG_NET_VENDOR_NATSEMI is not set |
| 481 | # CONFIG_NET_VENDOR_NETERION is not set | ||
| 482 | # CONFIG_NET_VENDOR_NETRONOME is not set | ||
| 483 | # CONFIG_NET_VENDOR_NI is not set | ||
| 484 | # CONFIG_NET_VENDOR_NVIDIA is not set | ||
| 485 | # CONFIG_NET_VENDOR_OKI is not set | ||
| 486 | # CONFIG_NET_VENDOR_PACKET_ENGINES is not set | ||
| 487 | # CONFIG_NET_VENDOR_QLOGIC is not set | ||
| 488 | # CONFIG_NET_VENDOR_QUALCOMM is not set | ||
| 489 | # CONFIG_NET_VENDOR_RDC is not set | ||
| 490 | # CONFIG_NET_VENDOR_REALTEK is not set | ||
| 491 | # CONFIG_NET_VENDOR_RENESAS is not set | ||
| 492 | # CONFIG_NET_VENDOR_ROCKER is not set | ||
| 493 | # CONFIG_NET_VENDOR_SAMSUNG is not set | ||
| 494 | # CONFIG_NET_VENDOR_SEEQ is not set | ||
| 495 | # CONFIG_NET_VENDOR_SOLARFLARE is not set | ||
| 496 | # CONFIG_NET_VENDOR_SILAN is not set | ||
| 497 | # CONFIG_NET_VENDOR_SIS is not set | ||
| 498 | # CONFIG_NET_VENDOR_SMSC is not set | ||
| 499 | # CONFIG_NET_VENDOR_SOCIONEXT is not set | ||
| 500 | # CONFIG_NET_VENDOR_STMICRO is not set | ||
| 501 | # CONFIG_NET_VENDOR_SUN is not set | ||
| 502 | # CONFIG_NET_VENDOR_SYNOPSYS is not set | ||
| 503 | # CONFIG_NET_VENDOR_TEHUTI is not set | ||
| 504 | # CONFIG_NET_VENDOR_TI is not set | ||
| 505 | # CONFIG_NET_VENDOR_VIA is not set | ||
| 506 | # CONFIG_NET_VENDOR_WIZNET is not set | ||
| 458 | CONFIG_PPP=m | 507 | CONFIG_PPP=m |
| 459 | CONFIG_PPP_BSDCOMP=m | 508 | CONFIG_PPP_BSDCOMP=m |
| 460 | CONFIG_PPP_DEFLATE=m | 509 | CONFIG_PPP_DEFLATE=m |
| 510 | CONFIG_PPP_FILTER=y | ||
| 461 | CONFIG_PPP_MPPE=m | 511 | CONFIG_PPP_MPPE=m |
| 512 | CONFIG_PPP_MULTILINK=y | ||
| 462 | CONFIG_PPPOE=m | 513 | CONFIG_PPPOE=m |
| 463 | CONFIG_PPTP=m | 514 | CONFIG_PPTP=m |
| 464 | CONFIG_PPPOL2TP=m | 515 | CONFIG_PPPOL2TP=m |
| @@ -470,17 +521,21 @@ CONFIG_INPUT_EVDEV=y · 5 unmodified lines | |||
| 470 | # CONFIG_INPUT_MOUSE is not set | 521 | # CONFIG_INPUT_MOUSE is not set |
| 471 | # CONFIG_SERIO is not set | 522 | # CONFIG_SERIO is not set |
| 472 | CONFIG_LEGACY_PTY_COUNT=0 | 523 | CONFIG_LEGACY_PTY_COUNT=0 |
| 524 | CONFIG_NULL_TTY=m | ||
| 473 | CONFIG_HW_RANDOM_VIRTIO=m | 525 | CONFIG_HW_RANDOM_VIRTIO=m |
| 474 | CONFIG_RAW_DRIVER=m | 526 | CONFIG_RAW_DRIVER=m |
| 475 | CONFIG_HANGCHECK_TIMER=m | 527 | CONFIG_HANGCHECK_TIMER=m |
| 476 | CONFIG_TN3270_FS=y | 528 | CONFIG_TN3270_FS=y |
| 529 | # CONFIG_PTP_1588_CLOCK is not set | ||
| 477 | # CONFIG_HWMON is not set | 530 | # CONFIG_HWMON is not set |
| 478 | CONFIG_WATCHDOG=y | 531 | CONFIG_WATCHDOG=y |
| 532 | CONFIG_WATCHDOG_CORE=y | ||
| 479 | CONFIG_WATCHDOG_NOWAYOUT=y | 533 | CONFIG_WATCHDOG_NOWAYOUT=y |
| 480 | CONFIG_SOFT_WATCHDOG=m | 534 | CONFIG_SOFT_WATCHDOG=m |
| 481 | CONFIG_DIAG288_WATCHDOG=m | 535 | CONFIG_DIAG288_WATCHDOG=m |
| 482 | CONFIG_DRM=y | 536 | CONFIG_DRM=y |
| 483 | CONFIG_DRM_VIRTIO_GPU=y | 537 | CONFIG_DRM_VIRTIO_GPU=y |
| 538 | # CONFIG_BACKLIGHT_CLASS_DEVICE is not set | ||
| 484 | CONFIG_FRAMEBUFFER_CONSOLE=y | 539 | CONFIG_FRAMEBUFFER_CONSOLE=y |
| 485 | # CONFIG_HID is not set | 540 | # CONFIG_HID is not set |
| 486 | # CONFIG_USB_SUPPORT is not set | 541 | # CONFIG_USB_SUPPORT is not set |
| @@ -495,8 +550,8 @@ CONFIG_VFIO_MDEV_DEVICE=m · 8 unmodified lines | |||
| 495 | CONFIG_VIRTIO_PCI=m | 550 | CONFIG_VIRTIO_PCI=m |
| 496 | CONFIG_VIRTIO_BALLOON=m | 551 | CONFIG_VIRTIO_BALLOON=m |
| 497 | CONFIG_VIRTIO_INPUT=y | 552 | CONFIG_VIRTIO_INPUT=y |
| 498 | CONFIG_S390_AP_IOMMU=y | ||
| 499 | CONFIG_S390_CCW_IOMMU=y | 553 | CONFIG_S390_CCW_IOMMU=y |
| 554 | CONFIG_S390_AP_IOMMU=y | ||
| 500 | CONFIG_EXT4_FS=y | 555 | CONFIG_EXT4_FS=y |
| 501 | CONFIG_EXT4_FS_POSIX_ACL=y | 556 | CONFIG_EXT4_FS_POSIX_ACL=y |
| 502 | CONFIG_EXT4_FS_SECURITY=y | 557 | CONFIG_EXT4_FS_SECURITY=y |
| @@ -546,8 +601,10 @@ CONFIG_ECRYPT_FS=m · 43 unmodified lines | |||
| 546 | CONFIG_CRAMFS=m | 601 | CONFIG_CRAMFS=m |
| 547 | CONFIG_SQUASHFS=m | 602 | CONFIG_SQUASHFS=m |
| 548 | CONFIG_SQUASHFS_XATTR=y | 603 | CONFIG_SQUASHFS_XATTR=y |
| 604 | CONFIG_SQUASHFS_LZ4=y | ||
| 549 | CONFIG_SQUASHFS_LZO=y | 605 | CONFIG_SQUASHFS_LZO=y |
| 550 | CONFIG_SQUASHFS_XZ=y | 606 | CONFIG_SQUASHFS_XZ=y |
| 607 | CONFIG_SQUASHFS_ZSTD=y | ||
| 551 | CONFIG_ROMFS_FS=m | 608 | CONFIG_ROMFS_FS=m |
| 552 | CONFIG_NFS_FS=m | 609 | CONFIG_NFS_FS=m |
| 553 | CONFIG_NFS_V3_ACL=y | 610 | CONFIG_NFS_V3_ACL=y |
| @@ -558,7 +615,6 @@ CONFIG_NFSD_V3_ACL=y · 4 unmodified lines | |||
| 558 | CONFIG_NFSD_V4=y | 615 | CONFIG_NFSD_V4=y |
| 559 | CONFIG_NFSD_V4_SECURITY_LABEL=y | 616 | CONFIG_NFSD_V4_SECURITY_LABEL=y |
| 560 | CONFIG_CIFS=m | 617 | CONFIG_CIFS=m |
| 561 | CONFIG_CIFS_STATS=y | ||
| 562 | CONFIG_CIFS_STATS2=y | 618 | CONFIG_CIFS_STATS2=y |
| 563 | CONFIG_CIFS_WEAK_PW_HASH=y | 619 | CONFIG_CIFS_WEAK_PW_HASH=y |
| 564 | CONFIG_CIFS_UPCALL=y | 620 | CONFIG_CIFS_UPCALL=y |
| @@ -574,31 +630,7 @@ CONFIG_NLS_ISO8859_1=m · 9 unmodified lines | |||
| 574 | CONFIG_NLS_ISO8859_15=m | 630 | CONFIG_NLS_ISO8859_15=m |
| 575 | CONFIG_NLS_UTF8=m | 631 | CONFIG_NLS_UTF8=m |
| 576 | CONFIG_DLM=m | 632 | CONFIG_DLM=m |
| 577 | CONFIG_PRINTK_TIME=y | 633 | CONFIG_UNICODE=y |
| 578 | CONFIG_DEBUG_INFO=y | ||
| 579 | CONFIG_DEBUG_INFO_DWARF4=y | ||
| 580 | CONFIG_GDB_SCRIPTS=y | ||
| 581 | # CONFIG_ENABLE_MUST_CHECK is not set | ||
| 582 | CONFIG_FRAME_WARN=1024 | ||
| 583 | CONFIG_UNUSED_SYMBOLS=y | ||
| 584 | CONFIG_MAGIC_SYSRQ=y | ||
| 585 | CONFIG_DEBUG_MEMORY_INIT=y | ||
| 586 | CONFIG_PANIC_ON_OOPS=y | ||
| 587 | CONFIG_RCU_TORTURE_TEST=m | ||
| 588 | CONFIG_RCU_CPU_STALL_TIMEOUT=60 | ||
| 589 | CONFIG_LATENCYTOP=y | ||
| 590 | CONFIG_SCHED_TRACER=y | ||
| 591 | CONFIG_FTRACE_SYSCALLS=y | ||
| 592 | CONFIG_STACK_TRACER=y | ||
| 593 | CONFIG_BLK_DEV_IO_TRACE=y | ||
| 594 | CONFIG_FUNCTION_PROFILER=y | ||
| 595 | CONFIG_HIST_TRIGGERS=y | ||
| 596 | CONFIG_LKDTM=m | ||
| 597 | CONFIG_PERCPU_TEST=m | ||
| 598 | CONFIG_ATOMIC64_SELFTEST=y | ||
| 599 | CONFIG_TEST_BPF=m | ||
| 600 | CONFIG_BUG_ON_DATA_CORRUPTION=y | ||
| 601 | CONFIG_S390_PTDUMP=y | ||
| 602 | CONFIG_PERSISTENT_KEYRINGS=y | 634 | CONFIG_PERSISTENT_KEYRINGS=y |
| 603 | CONFIG_BIG_KEYS=y | 635 | CONFIG_BIG_KEYS=y |
| 604 | CONFIG_ENCRYPTED_KEYS=m | 636 | CONFIG_ENCRYPTED_KEYS=m |
| @@ -606,7 +638,6 @@ CONFIG_SECURITY=y · 1 unmodified line | |||
| 606 | CONFIG_SECURITY_NETWORK=y | 638 | CONFIG_SECURITY_NETWORK=y |
| 607 | CONFIG_SECURITY_SELINUX=y | 639 | CONFIG_SECURITY_SELINUX=y |
| 608 | CONFIG_SECURITY_SELINUX_BOOTPARAM=y | 640 | CONFIG_SECURITY_SELINUX_BOOTPARAM=y |
| 609 | CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=0 | ||
| 610 | CONFIG_SECURITY_SELINUX_DISABLE=y | 641 | CONFIG_SECURITY_SELINUX_DISABLE=y |
| 611 | CONFIG_INTEGRITY_SIGNATURE=y | 642 | CONFIG_INTEGRITY_SIGNATURE=y |
| 612 | CONFIG_INTEGRITY_ASYMMETRIC_KEYS=y | 643 | CONFIG_INTEGRITY_ASYMMETRIC_KEYS=y |
| @@ -615,31 +646,42 @@ CONFIG_IMA_DEFAULT_HASH_SHA256=y · 2 unmodified lines | |||
| 615 | CONFIG_IMA_WRITE_POLICY=y | 646 | CONFIG_IMA_WRITE_POLICY=y |
| 616 | CONFIG_IMA_APPRAISE=y | 647 | CONFIG_IMA_APPRAISE=y |
| 617 | CONFIG_CRYPTO_FIPS=y | 648 | CONFIG_CRYPTO_FIPS=y |
| 618 | CONFIG_CRYPTO_DH=m | ||
| 619 | CONFIG_CRYPTO_ECDH=m | ||
| 620 | CONFIG_CRYPTO_USER=m | 649 | CONFIG_CRYPTO_USER=m |
| 621 | # CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set | 650 | # CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set |
| 622 | CONFIG_CRYPTO_PCRYPT=m | 651 | CONFIG_CRYPTO_PCRYPT=m |
| 623 | CONFIG_CRYPTO_CRYPTD=m | 652 | CONFIG_CRYPTO_CRYPTD=m |
| 624 | CONFIG_CRYPTO_TEST=m | 653 | CONFIG_CRYPTO_TEST=m |
| 654 | CONFIG_CRYPTO_DH=m | ||
| 655 | CONFIG_CRYPTO_ECDH=m | ||
| 656 | CONFIG_CRYPTO_ECRDSA=m | ||
| 625 | CONFIG_CRYPTO_CHACHA20POLY1305=m | 657 | CONFIG_CRYPTO_CHACHA20POLY1305=m |
| 658 | CONFIG_CRYPTO_AEGIS128=m | ||
| 659 | CONFIG_CRYPTO_AEGIS128L=m | ||
| 660 | CONFIG_CRYPTO_AEGIS256=m | ||
| 661 | CONFIG_CRYPTO_MORUS640=m | ||
| 662 | CONFIG_CRYPTO_MORUS1280=m | ||
| 663 | CONFIG_CRYPTO_CFB=m | ||
| 626 | CONFIG_CRYPTO_LRW=m | 664 | CONFIG_CRYPTO_LRW=m |
| 665 | CONFIG_CRYPTO_OFB=m | ||
| 627 | CONFIG_CRYPTO_PCBC=m | 666 | CONFIG_CRYPTO_PCBC=m |
| 628 | CONFIG_CRYPTO_KEYWRAP=m | 667 | CONFIG_CRYPTO_KEYWRAP=m |
| 668 | CONFIG_CRYPTO_ADIANTUM=m | ||
| 629 | CONFIG_CRYPTO_XCBC=m | 669 | CONFIG_CRYPTO_XCBC=m |
| 630 | CONFIG_CRYPTO_VMAC=m | 670 | CONFIG_CRYPTO_VMAC=m |
| 631 | CONFIG_CRYPTO_CRC32=m | 671 | CONFIG_CRYPTO_CRC32=m |
| 672 | CONFIG_CRYPTO_XXHASH=m | ||
| 632 | CONFIG_CRYPTO_MICHAEL_MIC=m | 673 | CONFIG_CRYPTO_MICHAEL_MIC=m |
| 633 | CONFIG_CRYPTO_RMD128=m | 674 | CONFIG_CRYPTO_RMD128=m |
| 634 | CONFIG_CRYPTO_RMD160=m | 675 | CONFIG_CRYPTO_RMD160=m |
| 635 | CONFIG_CRYPTO_RMD256=m | 676 | CONFIG_CRYPTO_RMD256=m |
| 636 | CONFIG_CRYPTO_RMD320=m | 677 | CONFIG_CRYPTO_RMD320=m |
| 637 | CONFIG_CRYPTO_SHA512=m | ||
| 638 | CONFIG_CRYPTO_SHA3=m | 678 | CONFIG_CRYPTO_SHA3=m |
| 679 | CONFIG_CRYPTO_SM3=m | ||
| 639 | CONFIG_CRYPTO_TGR192=m | 680 | CONFIG_CRYPTO_TGR192=m |
| 640 | CONFIG_CRYPTO_WP512=m | 681 | CONFIG_CRYPTO_WP512=m |
| 641 | CONFIG_CRYPTO_AES_TI=m | 682 | CONFIG_CRYPTO_AES_TI=m |
| 642 | CONFIG_CRYPTO_ANUBIS=m | 683 | CONFIG_CRYPTO_ANUBIS=m |
| 684 | CONFIG_CRYPTO_ARC4=m | ||
| 643 | CONFIG_CRYPTO_BLOWFISH=m | 685 | CONFIG_CRYPTO_BLOWFISH=m |
| 644 | CONFIG_CRYPTO_CAMELLIA=m | 686 | CONFIG_CRYPTO_CAMELLIA=m |
| 645 | CONFIG_CRYPTO_CAST5=m | 687 | CONFIG_CRYPTO_CAST5=m |
| @@ -649,16 +691,19 @@ CONFIG_CRYPTO_KHAZAD=m · 3 unmodified lines | |||
| 649 | CONFIG_CRYPTO_SALSA20=m | 691 | CONFIG_CRYPTO_SALSA20=m |
| 650 | CONFIG_CRYPTO_SEED=m | 692 | CONFIG_CRYPTO_SEED=m |
| 651 | CONFIG_CRYPTO_SERPENT=m | 693 | CONFIG_CRYPTO_SERPENT=m |
| 694 | CONFIG_CRYPTO_SM4=m | ||
| 652 | CONFIG_CRYPTO_TEA=m | 695 | CONFIG_CRYPTO_TEA=m |
| 653 | CONFIG_CRYPTO_TWOFISH=m | 696 | CONFIG_CRYPTO_TWOFISH=m |
| 654 | CONFIG_CRYPTO_842=m | 697 | CONFIG_CRYPTO_842=m |
| 655 | CONFIG_CRYPTO_LZ4=m | 698 | CONFIG_CRYPTO_LZ4=m |
| 656 | CONFIG_CRYPTO_LZ4HC=m | 699 | CONFIG_CRYPTO_LZ4HC=m |
| 700 | CONFIG_CRYPTO_ZSTD=m | ||
| 657 | CONFIG_CRYPTO_ANSI_CPRNG=m | 701 | CONFIG_CRYPTO_ANSI_CPRNG=m |
| 658 | CONFIG_CRYPTO_USER_API_HASH=m | 702 | CONFIG_CRYPTO_USER_API_HASH=m |
| 659 | CONFIG_CRYPTO_USER_API_SKCIPHER=m | 703 | CONFIG_CRYPTO_USER_API_SKCIPHER=m |
| 660 | CONFIG_CRYPTO_USER_API_RNG=m | 704 | CONFIG_CRYPTO_USER_API_RNG=m |
| 661 | CONFIG_CRYPTO_USER_API_AEAD=m | 705 | CONFIG_CRYPTO_USER_API_AEAD=m |
| 706 | CONFIG_CRYPTO_STATS=y | ||
| 662 | CONFIG_ZCRYPT=m | 707 | CONFIG_ZCRYPT=m |
| 663 | CONFIG_PKEY=m | 708 | CONFIG_PKEY=m |
| 664 | CONFIG_CRYPTO_PAES_S390=m | 709 | CONFIG_CRYPTO_PAES_S390=m |
| @@ -669,12 +714,34 @@ CONFIG_CRYPTO_DES_S390=m · 4 unmodified lines | |||
| 669 | CONFIG_CRYPTO_AES_S390=m | 714 | CONFIG_CRYPTO_AES_S390=m |
| 670 | CONFIG_CRYPTO_GHASH_S390=m | 715 | CONFIG_CRYPTO_GHASH_S390=m |
| 671 | CONFIG_CRYPTO_CRC32_S390=y | 716 | CONFIG_CRYPTO_CRC32_S390=y |
| 717 | CONFIG_CORDIC=m | ||
| 718 | CONFIG_CRC4=m | ||
| 672 | CONFIG_CRC7=m | 719 | CONFIG_CRC7=m |
| 673 | CONFIG_CRC8=m | 720 | CONFIG_CRC8=m |
| 674 | CONFIG_CORDIC=m | 721 | CONFIG_DMA_CMA=y |
| 675 | CONFIG_CMM=m | 722 | CONFIG_CMA_SIZE_MBYTES=0 |
| 676 | CONFIG_APPLDATA_BASE=y | 723 | CONFIG_PRINTK_TIME=y |
| 677 | CONFIG_KVM=m | 724 | CONFIG_DEBUG_INFO=y |
| 678 | CONFIG_KVM_S390_UCONTROL=y | 725 | CONFIG_DEBUG_INFO_DWARF4=y |
| 679 | CONFIG_VHOST_NET=m | 726 | CONFIG_GDB_SCRIPTS=y |
| 680 | CONFIG_VHOST_VSOCK=m | 727 | CONFIG_FRAME_WARN=1024 |
| 728 | CONFIG_UNUSED_SYMBOLS=y | ||
| 729 | CONFIG_DEBUG_SECTION_MISMATCH=y | ||
| 730 | CONFIG_MAGIC_SYSRQ=y | ||
| 731 | CONFIG_DEBUG_MEMORY_INIT=y | ||
| 732 | CONFIG_PANIC_ON_OOPS=y | ||
| 733 | CONFIG_RCU_TORTURE_TEST=m | ||
| 734 | CONFIG_RCU_CPU_STALL_TIMEOUT=60 | ||
| 735 | CONFIG_LATENCYTOP=y | ||
| 736 | CONFIG_SCHED_TRACER=y | ||
| 737 | CONFIG_FTRACE_SYSCALLS=y | ||
| 738 | CONFIG_STACK_TRACER=y | ||
| 739 | CONFIG_BLK_DEV_IO_TRACE=y | ||
| 740 | CONFIG_FUNCTION_PROFILER=y | ||
| 741 | CONFIG_HIST_TRIGGERS=y | ||
| 742 | CONFIG_LKDTM=m | ||
| 743 | CONFIG_PERCPU_TEST=m | ||
| 744 | CONFIG_ATOMIC64_SELFTEST=y | ||
| 745 | CONFIG_TEST_BPF=m | ||
| 746 | CONFIG_BUG_ON_DATA_CORRUPTION=y | ||
| 747 | CONFIG_S390_PTDUMP=y | ||
| @@ -1,27 +1,33 @@ | |||
| 1 | # CONFIG_SWAP is not set | 1 | # CONFIG_SWAP is not set |
| 2 | CONFIG_NO_HZ_IDLE=y | 2 | CONFIG_NO_HZ_IDLE=y |
| 3 | CONFIG_HIGH_RES_TIMERS=y | 3 | CONFIG_HIGH_RES_TIMERS=y |
| 4 | # CONFIG_CPU_ISOLATION is not set | ||
| 5 | # CONFIG_UTS_NS is not set | ||
| 6 | # CONFIG_PID_NS is not set | ||
| 7 | # CONFIG_NET_NS is not set | ||
| 4 | CONFIG_BLK_DEV_INITRD=y | 8 | CONFIG_BLK_DEV_INITRD=y |
| 5 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | 9 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y |
| 6 | # CONFIG_COMPAT_BRK is not set | 10 | # CONFIG_COMPAT_BRK is not set |
| 7 | CONFIG_PARTITION_ADVANCED=y | ||
| 8 | CONFIG_IBM_PARTITION=y | ||
| 9 | CONFIG_DEFAULT_DEADLINE=y | ||
| 10 | CONFIG_TUNE_ZEC12=y | 11 | CONFIG_TUNE_ZEC12=y |
| 11 | # CONFIG_COMPAT is not set | 12 | # CONFIG_COMPAT is not set |
| 12 | CONFIG_NR_CPUS=2 | 13 | CONFIG_NR_CPUS=2 |
| 13 | # CONFIG_HOTPLUG_CPU is not set | ||
| 14 | CONFIG_HZ_100=y | 14 | CONFIG_HZ_100=y |
| 15 | # CONFIG_ARCH_RANDOM is not set | 15 | # CONFIG_ARCH_RANDOM is not set |
| 16 | # CONFIG_COMPACTION is not set | 16 | # CONFIG_RELOCATABLE is not set |
| 17 | # CONFIG_MIGRATION is not set | ||
| 18 | # CONFIG_BOUNCE is not set | ||
| 19 | # CONFIG_CHECK_STACK is not set | ||
| 20 | # CONFIG_CHSC_SCH is not set | 17 | # CONFIG_CHSC_SCH is not set |
| 21 | # CONFIG_SCM_BUS is not set | 18 | # CONFIG_SCM_BUS is not set |
| 22 | CONFIG_CRASH_DUMP=y | 19 | CONFIG_CRASH_DUMP=y |
| 23 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
| 24 | # CONFIG_SECCOMP is not set | 20 | # CONFIG_SECCOMP is not set |
| 21 | # CONFIG_PFAULT is not set | ||
| 22 | # CONFIG_S390_HYPFS_FS is not set | ||
| 23 | # CONFIG_VIRTUALIZATION is not set | ||
| 24 | # CONFIG_S390_GUEST is not set | ||
| 25 | CONFIG_PARTITION_ADVANCED=y | ||
| 26 | CONFIG_IBM_PARTITION=y | ||
| 27 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
| 28 | # CONFIG_COMPACTION is not set | ||
| 29 | # CONFIG_MIGRATION is not set | ||
| 30 | # CONFIG_BOUNCE is not set | ||
| 25 | CONFIG_NET=y | 31 | CONFIG_NET=y |
| 26 | # CONFIG_IUCV is not set | 32 | # CONFIG_IUCV is not set |
| 27 | CONFIG_DEVTMPFS=y | 33 | CONFIG_DEVTMPFS=y |
| @@ -43,7 +49,6 @@ CONFIG_ZFCP=y · 15 unmodified lines | |||
| 43 | # CONFIG_HVC_IUCV is not set | 49 | # CONFIG_HVC_IUCV is not set |
| 44 | # CONFIG_HW_RANDOM_S390 is not set | 50 | # CONFIG_HW_RANDOM_S390 is not set |
| 45 | CONFIG_RAW_DRIVER=y | 51 | CONFIG_RAW_DRIVER=y |
| 46 | # CONFIG_SCLP_ASYNC is not set | ||
| 47 | # CONFIG_HMC_DRV is not set | 52 | # CONFIG_HMC_DRV is not set |
| 48 | # CONFIG_S390_TAPE is not set | 53 | # CONFIG_S390_TAPE is not set |
| 49 | # CONFIG_VMCP is not set | 54 | # CONFIG_VMCP is not set |
| @@ -56,6 +61,7 @@ CONFIG_RAW_DRIVER=y · 6 unmodified lines | |||
| 56 | CONFIG_CONFIGFS_FS=y | 61 | CONFIG_CONFIGFS_FS=y |
| 57 | # CONFIG_MISC_FILESYSTEMS is not set | 62 | # CONFIG_MISC_FILESYSTEMS is not set |
| 58 | # CONFIG_NETWORK_FILESYSTEMS is not set | 63 | # CONFIG_NETWORK_FILESYSTEMS is not set |
| 64 | # CONFIG_DIMLIB is not set | ||
| 59 | CONFIG_PRINTK_TIME=y | 65 | CONFIG_PRINTK_TIME=y |
| 60 | CONFIG_DEBUG_INFO=y | 66 | CONFIG_DEBUG_INFO=y |
| 61 | CONFIG_DEBUG_FS=y | 67 | CONFIG_DEBUG_FS=y |
| @@ -64,7 +70,4 @@ CONFIG_PANIC_ON_OOPS=y · 2 unmodified lines | |||
| 64 | # CONFIG_SCHED_DEBUG is not set | 70 | # CONFIG_SCHED_DEBUG is not set |
| 65 | CONFIG_RCU_CPU_STALL_TIMEOUT=60 | 71 | CONFIG_RCU_CPU_STALL_TIMEOUT=60 |
| 66 | # CONFIG_FTRACE is not set | 72 | # CONFIG_FTRACE is not set |
| 67 | # CONFIG_PFAULT is not set | 73 | # CONFIG_RUNTIME_TESTING_MENU is not set |
| 68 | # CONFIG_S390_HYPFS_FS is not set | ||
| 69 | # CONFIG_VIRTUALIZATION is not set | ||
| 70 | # CONFIG_S390_GUEST is not set | ||
| @@ -118,7 +118,7 @@ do { \ · 117 unmodified lines | |||
| 118 | return PTR_ERR(rc); \ | 118 | return PTR_ERR(rc); \ |
| 119 | } while(0) | 119 | } while(0) |
| 120 | 120 | ||
| 121 | static int hpyfs_vm_create_guest(struct dentry *systems_dir, | 121 | static int hypfs_vm_create_guest(struct dentry *systems_dir, |
| 122 | struct diag2fc_data *data) | 122 | struct diag2fc_data *data) |
| 123 | { | 123 | { |
| 124 | char guest_name[NAME_LEN + 1] = {}; | 124 | char guest_name[NAME_LEN + 1] = {}; |
| @@ -219,7 +219,7 @@ int hypfs_vm_create_files(struct dentry *root) · 94 unmodified lines | |||
| 219 | } | 219 | } |
| 220 | 220 | ||
| 221 | for (i = 0; i < count; i++) { | 221 | for (i = 0; i < count; i++) { |
| 222 | rc = hpyfs_vm_create_guest(dir, &(data[i])); | 222 | rc = hypfs_vm_create_guest(dir, &(data[i])); |
| 223 | if (rc) | 223 | if (rc) |
| 224 | goto failed; | 224 | goto failed; |
| 225 | } | 225 | } |
| @@ -35,6 +35,7 @@ · 34 unmodified lines | |||
| 35 | 35 | ||
| 36 | #include <linux/typecheck.h> | 36 | #include <linux/typecheck.h> |
| 37 | #include <linux/compiler.h> | 37 | #include <linux/compiler.h> |
| 38 | #include <linux/types.h> | ||
| 38 | #include <asm/atomic_ops.h> | 39 | #include <asm/atomic_ops.h> |
| 39 | #include <asm/barrier.h> | 40 | #include <asm/barrier.h> |
| 40 | 41 | ||
| @@ -55,7 +56,7 @@ __bitops_byte(unsigned long nr, volatile unsigned long *ptr) · 14 unmodified lines | |||
| 55 | return ((unsigned char *)ptr) + ((nr ^ (BITS_PER_LONG - 8)) >> 3); | 56 | return ((unsigned char *)ptr) + ((nr ^ (BITS_PER_LONG - 8)) >> 3); |
| 56 | } | 57 | } |
| 57 | 58 | ||
| 58 | static inline void set_bit(unsigned long nr, volatile unsigned long *ptr) | 59 | static inline void arch_set_bit(unsigned long nr, volatile unsigned long *ptr) |
| 59 | { | 60 | { |
| 60 | unsigned long *addr = __bitops_word(nr, ptr); | 61 | unsigned long *addr = __bitops_word(nr, ptr); |
| 61 | unsigned long mask; | 62 | unsigned long mask; |
| @@ -76,7 +77,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *ptr) · 14 unmodified lines | |||
| 76 | __atomic64_or(mask, (long *)addr); | 77 | __atomic64_or(mask, (long *)addr); |
| 77 | } | 78 | } |
| 78 | 79 | ||
| 79 | static inline void clear_bit(unsigned long nr, volatile unsigned long *ptr) | 80 | static inline void arch_clear_bit(unsigned long nr, volatile unsigned long *ptr) |
| 80 | { | 81 | { |
| 81 | unsigned long *addr = __bitops_word(nr, ptr); | 82 | unsigned long *addr = __bitops_word(nr, ptr); |
| 82 | unsigned long mask; | 83 | unsigned long mask; |
| @@ -97,7 +98,8 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *ptr) · 14 unmodified lines | |||
| 97 | __atomic64_and(mask, (long *)addr); | 98 | __atomic64_and(mask, (long *)addr); |
| 98 | } | 99 | } |
| 99 | 100 | ||
| 100 | static inline void change_bit(unsigned long nr, volatile unsigned long *ptr) | 101 | static inline void arch_change_bit(unsigned long nr, |
| 102 | volatile unsigned long *ptr) | ||
| 101 | { | 103 | { |
| 102 | unsigned long *addr = __bitops_word(nr, ptr); | 104 | unsigned long *addr = __bitops_word(nr, ptr); |
| 103 | unsigned long mask; | 105 | unsigned long mask; |
| @@ -118,8 +120,8 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *ptr) · 14 unmodified lines | |||
| 118 | __atomic64_xor(mask, (long *)addr); | 120 | __atomic64_xor(mask, (long *)addr); |
| 119 | } | 121 | } |
| 120 | 122 | ||
| 121 | static inline int | 123 | static inline bool arch_test_and_set_bit(unsigned long nr, |
| 122 | test_and_set_bit(unsigned long nr, volatile unsigned long *ptr) | 124 | volatile unsigned long *ptr) |
| 123 | { | 125 | { |
| 124 | unsigned long *addr = __bitops_word(nr, ptr); | 126 | unsigned long *addr = __bitops_word(nr, ptr); |
| 125 | unsigned long old, mask; | 127 | unsigned long old, mask; |
| @@ -129,8 +131,8 @@ test_and_set_bit(unsigned long nr, volatile unsigned long *ptr) · 3 unmodified lines | |||
| 129 | return (old & mask) != 0; | 131 | return (old & mask) != 0; |
| 130 | } | 132 | } |
| 131 | 133 | ||
| 132 | static inline int | 134 | static inline bool arch_test_and_clear_bit(unsigned long nr, |
| 133 | test_and_clear_bit(unsigned long nr, volatile unsigned long *ptr) | 135 | volatile unsigned long *ptr) |
| 134 | { | 136 | { |
| 135 | unsigned long *addr = __bitops_word(nr, ptr); | 137 | unsigned long *addr = __bitops_word(nr, ptr); |
| 136 | unsigned long old, mask; | 138 | unsigned long old, mask; |
| @@ -140,8 +142,8 @@ test_and_clear_bit(unsigned long nr, volatile unsigned long *ptr) · 3 unmodified lines | |||
| 140 | return (old & ~mask) != 0; | 142 | return (old & ~mask) != 0; |
| 141 | } | 143 | } |
| 142 | 144 | ||
| 143 | static inline int | 145 | static inline bool arch_test_and_change_bit(unsigned long nr, |
| 144 | test_and_change_bit(unsigned long nr, volatile unsigned long *ptr) | 146 | volatile unsigned long *ptr) |
| 145 | { | 147 | { |
| 146 | unsigned long *addr = __bitops_word(nr, ptr); | 148 | unsigned long *addr = __bitops_word(nr, ptr); |
| 147 | unsigned long old, mask; | 149 | unsigned long old, mask; |
| @@ -151,30 +153,31 @@ test_and_change_bit(unsigned long nr, volatile unsigned long *ptr) · 3 unmodified lines | |||
| 151 | return (old & mask) != 0; | 153 | return (old & mask) != 0; |
| 152 | } | 154 | } |
| 153 | 155 | ||
| 154 | static inline void __set_bit(unsigned long nr, volatile unsigned long *ptr) | 156 | static inline void arch___set_bit(unsigned long nr, volatile unsigned long *ptr) |
| 155 | { | 157 | { |
| 156 | unsigned char *addr = __bitops_byte(nr, ptr); | 158 | unsigned char *addr = __bitops_byte(nr, ptr); |
| 157 | 159 | ||
| 158 | *addr |= 1 << (nr & 7); | 160 | *addr |= 1 << (nr & 7); |
| 159 | } | 161 | } |
| 160 | 162 | ||
| 161 | static inline void | 163 | static inline void arch___clear_bit(unsigned long nr, |
| 162 | __clear_bit(unsigned long nr, volatile unsigned long *ptr) | 164 | volatile unsigned long *ptr) |
| 163 | { | 165 | { |
| 164 | unsigned char *addr = __bitops_byte(nr, ptr); | 166 | unsigned char *addr = __bitops_byte(nr, ptr); |
| 165 | 167 | ||
| 166 | *addr &= ~(1 << (nr & 7)); | 168 | *addr &= ~(1 << (nr & 7)); |
| 167 | } | 169 | } |
| 168 | 170 | ||
| 169 | static inline void __change_bit(unsigned long nr, volatile unsigned long *ptr) | 171 | static inline void arch___change_bit(unsigned long nr, |
| 172 | volatile unsigned long *ptr) | ||
| 170 | { | 173 | { |
| 171 | unsigned char *addr = __bitops_byte(nr, ptr); | 174 | unsigned char *addr = __bitops_byte(nr, ptr); |
| 172 | 175 | ||
| 173 | *addr ^= 1 << (nr & 7); | 176 | *addr ^= 1 << (nr & 7); |
| 174 | } | 177 | } |
| 175 | 178 | ||
| 176 | static inline int | 179 | static inline bool arch___test_and_set_bit(unsigned long nr, |
| 177 | __test_and_set_bit(unsigned long nr, volatile unsigned long *ptr) | 180 | volatile unsigned long *ptr) |
| 178 | { | 181 | { |
| 179 | unsigned char *addr = __bitops_byte(nr, ptr); | 182 | unsigned char *addr = __bitops_byte(nr, ptr); |
| 180 | unsigned char ch; | 183 | unsigned char ch; |
| @@ -184,8 +187,8 @@ __test_and_set_bit(unsigned long nr, volatile unsigned long *ptr) · 3 unmodified lines | |||
| 184 | return (ch >> (nr & 7)) & 1; | 187 | return (ch >> (nr & 7)) & 1; |
| 185 | } | 188 | } |
| 186 | 189 | ||
| 187 | static inline int | 190 | static inline bool arch___test_and_clear_bit(unsigned long nr, |
| 188 | __test_and_clear_bit(unsigned long nr, volatile unsigned long *ptr) | 191 | volatile unsigned long *ptr) |
| 189 | { | 192 | { |
| 190 | unsigned char *addr = __bitops_byte(nr, ptr); | 193 | unsigned char *addr = __bitops_byte(nr, ptr); |
| 191 | unsigned char ch; | 194 | unsigned char ch; |
| @@ -195,8 +198,8 @@ __test_and_clear_bit(unsigned long nr, volatile unsigned long *ptr) · 3 unmodified lines | |||
| 195 | return (ch >> (nr & 7)) & 1; | 198 | return (ch >> (nr & 7)) & 1; |
| 196 | } | 199 | } |
| 197 | 200 | ||
| 198 | static inline int | 201 | static inline bool arch___test_and_change_bit(unsigned long nr, |
| 199 | __test_and_change_bit(unsigned long nr, volatile unsigned long *ptr) | 202 | volatile unsigned long *ptr) |
| 200 | { | 203 | { |
| 201 | unsigned char *addr = __bitops_byte(nr, ptr); | 204 | unsigned char *addr = __bitops_byte(nr, ptr); |
| 202 | unsigned char ch; | 205 | unsigned char ch; |
| @@ -206,7 +209,8 @@ __test_and_change_bit(unsigned long nr, volatile unsigned long *ptr) · 3 unmodified lines | |||
| 206 | return (ch >> (nr & 7)) & 1; | 209 | return (ch >> (nr & 7)) & 1; |
| 207 | } | 210 | } |
| 208 | 211 | ||
| 209 | static inline int test_bit(unsigned long nr, const volatile unsigned long *ptr) | 212 | static inline bool arch_test_bit(unsigned long nr, |
| 213 | const volatile unsigned long *ptr) | ||
| 210 | { | 214 | { |
| 211 | const volatile unsigned char *addr; | 215 | const volatile unsigned char *addr; |
| 212 | 216 | ||
| @@ -215,28 +219,30 @@ static inline int test_bit(unsigned long nr, const volatile unsigned long *ptr) · 2 unmodified lines | |||
| 215 | return (*addr >> (nr & 7)) & 1; | 219 | return (*addr >> (nr & 7)) & 1; |
| 216 | } | 220 | } |
| 217 | 221 | ||
| 218 | static inline int test_and_set_bit_lock(unsigned long nr, | 222 | static inline bool arch_test_and_set_bit_lock(unsigned long nr, |
| 219 | volatile unsigned long *ptr) | 223 | volatile unsigned long *ptr) |
| 220 | { | 224 | { |
| 221 | if (test_bit(nr, ptr)) | 225 | if (arch_test_bit(nr, ptr)) |
| 222 | return 1; | 226 | return 1; |
| 223 | return test_and_set_bit(nr, ptr); | 227 | return arch_test_and_set_bit(nr, ptr); |
| 224 | } | 228 | } |
| 225 | 229 | ||
| 226 | static inline void clear_bit_unlock(unsigned long nr, | 230 | static inline void arch_clear_bit_unlock(unsigned long nr, |
| 227 | volatile unsigned long *ptr) | 231 | volatile unsigned long *ptr) |
| 228 | { | 232 | { |
| 229 | smp_mb__before_atomic(); | 233 | smp_mb__before_atomic(); |
| 230 | clear_bit(nr, ptr); | 234 | arch_clear_bit(nr, ptr); |
| 231 | } | 235 | } |
| 232 | 236 | ||
| 233 | static inline void __clear_bit_unlock(unsigned long nr, | 237 | static inline void arch___clear_bit_unlock(unsigned long nr, |
| 234 | volatile unsigned long *ptr) | 238 | volatile unsigned long *ptr) |
| 235 | { | 239 | { |
| 236 | smp_mb(); | 240 | smp_mb(); |
| 237 | __clear_bit(nr, ptr); | 241 | arch___clear_bit(nr, ptr); |
| 238 | } | 242 | } |
| 239 | 243 | ||
| 244 | #include <asm-generic/bitops-instrumented.h> | ||
| 245 | |||
| 240 | /* | 246 | /* |
| 241 | * Functions which use MSB0 bit numbering. | 247 | * Functions which use MSB0 bit numbering. |
| 242 | * The bits are numbered: | 248 | * The bits are numbered: |
| @@ -261,7 +267,8 @@ static inline void clear_bit_inv(unsigned long nr, volatile unsigned long *ptr) · 18 unmodified lines | |||
| 261 | return clear_bit(nr ^ (BITS_PER_LONG - 1), ptr); | 267 | return clear_bit(nr ^ (BITS_PER_LONG - 1), ptr); |
| 262 | } | 268 | } |
| 263 | 269 | ||
| 264 | static inline int test_and_clear_bit_inv(unsigned long nr, volatile unsigned long *ptr) | 270 | static inline bool test_and_clear_bit_inv(unsigned long nr, |
| 271 | volatile unsigned long *ptr) | ||
| 265 | { | 272 | { |
| 266 | return test_and_clear_bit(nr ^ (BITS_PER_LONG - 1), ptr); | 273 | return test_and_clear_bit(nr ^ (BITS_PER_LONG - 1), ptr); |
| 267 | } | 274 | } |
| @@ -276,8 +283,8 @@ static inline void __clear_bit_inv(unsigned long nr, volatile unsigned long *ptr · 8 unmodified lines | |||
| 276 | return __clear_bit(nr ^ (BITS_PER_LONG - 1), ptr); | 283 | return __clear_bit(nr ^ (BITS_PER_LONG - 1), ptr); |
| 277 | } | 284 | } |
| 278 | 285 | ||
| 279 | static inline int test_bit_inv(unsigned long nr, | 286 | static inline bool test_bit_inv(unsigned long nr, |
| 280 | const volatile unsigned long *ptr) | 287 | const volatile unsigned long *ptr) |
| 281 | { | 288 | { |
| 282 | return test_bit(nr ^ (BITS_PER_LONG - 1), ptr); | 289 | return test_bit(nr ^ (BITS_PER_LONG - 1), ptr); |
| 283 | } | 290 | } |
| @@ -177,6 +177,8 @@ static inline int devmem_is_allowed(unsigned long pfn) · 176 unmodified lines | |||
| 177 | #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | \ | 177 | #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | \ |
| 178 | VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) | 178 | VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) |
| 179 | 179 | ||
| 180 | #define ARCH_ZONE_DMA_BITS 31 | ||
| 181 | |||
| 180 | #include <asm-generic/memory_model.h> | 182 | #include <asm-generic/memory_model.h> |
| 181 | #include <asm-generic/getorder.h> | 183 | #include <asm-generic/getorder.h> |
| 182 | 184 | ||
| @@ -28,7 +28,7 @@ · 27 unmodified lines | |||
| 28 | * @sliba: storage list information block address | 28 | * @sliba: storage list information block address |
| 29 | * @sla: storage list address | 29 | * @sla: storage list address |
| 30 | * @slsba: storage list state block address | 30 | * @slsba: storage list state block address |
| 31 | * @akey: access key for DLIB | 31 | * @akey: access key for SLIB |
| 32 | * @bkey: access key for SL | 32 | * @bkey: access key for SL |
| 33 | * @ckey: access key for SBALs | 33 | * @ckey: access key for SBALs |
| 34 | * @dkey: access key for SLSB | 34 | * @dkey: access key for SLSB |
| @@ -50,11 +50,10 @@ struct qdesfmt0 { · 15 unmodified lines | |||
| 50 | /** | 50 | /** |
| 51 | * struct qdr - queue description record (QDR) | 51 | * struct qdr - queue description record (QDR) |
| 52 | * @qfmt: queue format | 52 | * @qfmt: queue format |
| 53 | * @pfmt: implementation dependent parameter format | ||
| 54 | * @ac: adapter characteristics | 53 | * @ac: adapter characteristics |
| 55 | * @iqdcnt: input queue descriptor count | 54 | * @iqdcnt: input queue descriptor count |
| 56 | * @oqdcnt: output queue descriptor count | 55 | * @oqdcnt: output queue descriptor count |
| 57 | * @iqdsz: inpout queue descriptor size | 56 | * @iqdsz: input queue descriptor size |
| 58 | * @oqdsz: output queue descriptor size | 57 | * @oqdsz: output queue descriptor size |
| 59 | * @qiba: queue information block address | 58 | * @qiba: queue information block address |
| 60 | * @qkey: queue information block key | 59 | * @qkey: queue information block key |
| @@ -62,8 +61,7 @@ struct qdesfmt0 { · 1 unmodified line | |||
| 62 | */ | 61 | */ |
| 63 | struct qdr { | 62 | struct qdr { |
| 64 | u32 qfmt : 8; | 63 | u32 qfmt : 8; |
| 65 | u32 pfmt : 8; | 64 | u32 : 16; |
| 66 | u32 : 8; | ||
| 67 | u32 ac : 8; | 65 | u32 ac : 8; |
| 68 | u32 : 8; | 66 | u32 : 8; |
| 69 | u32 iqdcnt : 8; | 67 | u32 iqdcnt : 8; |
| @@ -327,6 +325,7 @@ typedef void qdio_handler_t(struct ccw_device *, unsigned int, int, · 257 unmodified lines | |||
| 327 | * struct qdio_initialize - qdio initialization data | 325 | * struct qdio_initialize - qdio initialization data |
| 328 | * @cdev: associated ccw device | 326 | * @cdev: associated ccw device |
| 329 | * @q_format: queue format | 327 | * @q_format: queue format |
| 328 | * @qdr_ac: feature flags to set | ||
| 330 | * @adapter_name: name for the adapter | 329 | * @adapter_name: name for the adapter |
| 331 | * @qib_param_field_format: format for qib_parm_field | 330 | * @qib_param_field_format: format for qib_parm_field |
| 332 | * @qib_param_field: pointer to 128 bytes or NULL, if no param field | 331 | * @qib_param_field: pointer to 128 bytes or NULL, if no param field |
| @@ -338,6 +337,7 @@ typedef void qdio_handler_t(struct ccw_device *, unsigned int, int, · 5 unmodified lines | |||
| 338 | * @input_handler: handler to be called for input queues | 337 | * @input_handler: handler to be called for input queues |
| 339 | * @output_handler: handler to be called for output queues | 338 | * @output_handler: handler to be called for output queues |
| 340 | * @queue_start_poll_array: polling handlers (one per input queue or NULL) | 339 | * @queue_start_poll_array: polling handlers (one per input queue or NULL) |
| 340 | * @scan_threshold: # of in-use buffers that triggers scan on output queue | ||
| 341 | * @int_parm: interruption parameter | 341 | * @int_parm: interruption parameter |
| 342 | * @input_sbal_addr_array: address of no_input_qs * 128 pointers | 342 | * @input_sbal_addr_array: address of no_input_qs * 128 pointers |
| 343 | * @output_sbal_addr_array: address of no_output_qs * 128 pointers | 343 | * @output_sbal_addr_array: address of no_output_qs * 128 pointers |
| @@ -54,6 +54,7 @@ · 53 unmodified lines | |||
| 54 | #define INITRD_SIZE_OFFSET 0x10410 | 54 | #define INITRD_SIZE_OFFSET 0x10410 |
| 55 | #define OLDMEM_BASE_OFFSET 0x10418 | 55 | #define OLDMEM_BASE_OFFSET 0x10418 |
| 56 | #define OLDMEM_SIZE_OFFSET 0x10420 | 56 | #define OLDMEM_SIZE_OFFSET 0x10420 |
| 57 | #define KERNEL_VERSION_OFFSET 0x10428 | ||
| 57 | #define COMMAND_LINE_OFFSET 0x10480 | 58 | #define COMMAND_LINE_OFFSET 0x10480 |
| 58 | 59 | ||
| 59 | #ifndef __ASSEMBLY__ | 60 | #ifndef __ASSEMBLY__ |
| @@ -74,7 +75,8 @@ struct parmarea { · 14 unmodified lines | |||
| 74 | unsigned long initrd_size; /* 0x10410 */ | 75 | unsigned long initrd_size; /* 0x10410 */ |
| 75 | unsigned long oldmem_base; /* 0x10418 */ | 76 | unsigned long oldmem_base; /* 0x10418 */ |
| 76 | unsigned long oldmem_size; /* 0x10420 */ | 77 | unsigned long oldmem_size; /* 0x10420 */ |
| 77 | char pad1[0x10480 - 0x10428]; /* 0x10428 - 0x10480 */ | 78 | unsigned long kernel_version; /* 0x10428 */ |
| 79 | char pad1[0x10480 - 0x10430]; /* 0x10430 - 0x10480 */ | ||
| 78 | char command_line[ARCH_COMMAND_LINE_SIZE]; /* 0x10480 */ | 80 | char command_line[ARCH_COMMAND_LINE_SIZE]; /* 0x10480 */ |
| 79 | }; | 81 | }; |
| 80 | 82 | ||
| @@ -82,6 +84,7 @@ extern int noexec_disabled; · 1 unmodified line | |||
| 82 | extern int memory_end_set; | 84 | extern int memory_end_set; |
| 83 | extern unsigned long memory_end; | 85 | extern unsigned long memory_end; |
| 84 | extern unsigned long max_physmem_end; | 86 | extern unsigned long max_physmem_end; |
| 87 | extern unsigned long __swsusp_reset_dma; | ||
| 85 | 88 | ||
| 86 | #define MACHINE_IS_VM (S390_lowcore.machine_flags & MACHINE_FLAG_VM) | 89 | #define MACHINE_IS_VM (S390_lowcore.machine_flags & MACHINE_FLAG_VM) |
| 87 | #define MACHINE_IS_KVM (S390_lowcore.machine_flags & MACHINE_FLAG_KVM) | 90 | #define MACHINE_IS_KVM (S390_lowcore.machine_flags & MACHINE_FLAG_KVM) |
| @@ -34,5 +34,6 @@ · 33 unmodified lines | |||
| 34 | #define __ARCH_WANT_SYS_FORK | 34 | #define __ARCH_WANT_SYS_FORK |
| 35 | #define __ARCH_WANT_SYS_VFORK | 35 | #define __ARCH_WANT_SYS_VFORK |
| 36 | #define __ARCH_WANT_SYS_CLONE | 36 | #define __ARCH_WANT_SYS_CLONE |
| 37 | #define __ARCH_WANT_SYS_CLONE3 | ||
| 37 | 38 | ||
| 38 | #endif /* _ASM_S390_UNISTD_H_ */ | 39 | #endif /* _ASM_S390_UNISTD_H_ */ |
| @@ -1,4 +1,4 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0 */ | 1 | /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ |
| 2 | #ifndef _UAPI__ASM_BPF_PERF_EVENT_H__ | 2 | #ifndef _UAPI__ASM_BPF_PERF_EVENT_H__ |
| 3 | #define _UAPI__ASM_BPF_PERF_EVENT_H__ | 3 | #define _UAPI__ASM_BPF_PERF_EVENT_H__ |
| 4 | 4 | ||
| @@ -1,4 +1,4 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0 */ | 1 | /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ |
| 2 | #ifndef _ASM_S390_UAPI_IPL_H | 2 | #ifndef _ASM_S390_UAPI_IPL_H |
| 3 | #define _ASM_S390_UAPI_IPL_H | 3 | #define _ASM_S390_UAPI_IPL_H |
| 4 | 4 | ||
| @@ -20,6 +20,7 @@ · 19 unmodified lines | |||
| 20 | 20 | ||
| 21 | #include <linux/ioctl.h> | 21 | #include <linux/ioctl.h> |
| 22 | #include <linux/compiler.h> | 22 | #include <linux/compiler.h> |
| 23 | #include <linux/types.h> | ||
| 23 | 24 | ||
| 24 | /* Name of the zcrypt device driver. */ | 25 | /* Name of the zcrypt device driver. */ |
| 25 | #define ZCRYPT_NAME "zcrypt" | 26 | #define ZCRYPT_NAME "zcrypt" |
| @@ -160,17 +161,17 @@ struct ica_xcRB { · 134 unmodified lines | |||
| 160 | * @payload_len: Payload length | 161 | * @payload_len: Payload length |
| 161 | */ | 162 | */ |
| 162 | struct ep11_cprb { | 163 | struct ep11_cprb { |
| 163 | uint16_t cprb_len; | 164 | __u16 cprb_len; |
| 164 | unsigned char cprb_ver_id; | 165 | unsigned char cprb_ver_id; |
| 165 | unsigned char pad_000[2]; | 166 | unsigned char pad_000[2]; |
| 166 | unsigned char flags; | 167 | unsigned char flags; |
| 167 | unsigned char func_id[2]; | 168 | unsigned char func_id[2]; |
| 168 | uint32_t source_id; | 169 | __u32 source_id; |
| 169 | uint32_t target_id; | 170 | __u32 target_id; |
| 170 | uint32_t ret_code; | 171 | __u32 ret_code; |
| 171 | uint32_t reserved1; | 172 | __u32 reserved1; |
| 172 | uint32_t reserved2; | 173 | __u32 reserved2; |
| 173 | uint32_t payload_len; | 174 | __u32 payload_len; |
| 174 | } __attribute__((packed)); | 175 | } __attribute__((packed)); |
| 175 | 176 | ||
| 176 | /** | 177 | /** |
| @@ -179,8 +180,8 @@ struct ep11_cprb { · 2 unmodified lines | |||
| 179 | * @dom_id: Usage domain id | 180 | * @dom_id: Usage domain id |
| 180 | */ | 181 | */ |
| 181 | struct ep11_target_dev { | 182 | struct ep11_target_dev { |
| 182 | uint16_t ap_id; | 183 | __u16 ap_id; |
| 183 | uint16_t dom_id; | 184 | __u16 dom_id; |
| 184 | }; | 185 | }; |
| 185 | 186 | ||
| 186 | /** | 187 | /** |
| @@ -195,14 +196,14 @@ struct ep11_target_dev { · 8 unmodified lines | |||
| 195 | * @resp: Addr to response block | 196 | * @resp: Addr to response block |
| 196 | */ | 197 | */ |
| 197 | struct ep11_urb { | 198 | struct ep11_urb { |
| 198 | uint16_t targets_num; | 199 | __u16 targets_num; |
| 199 | uint64_t targets; | 200 | __u64 targets; |
| 200 | uint64_t weight; | 201 | __u64 weight; |
| 201 | uint64_t req_no; | 202 | __u64 req_no; |
| 202 | uint64_t req_len; | 203 | __u64 req_len; |
| 203 | uint64_t req; | 204 | __u64 req; |
| 204 | uint64_t resp_len; | 205 | __u64 resp_len; |
| 205 | uint64_t resp; | 206 | __u64 resp; |
| 206 | } __attribute__((packed)); | 207 | } __attribute__((packed)); |
| 207 | 208 | ||
| 208 | /** | 209 | /** |
| @@ -114,12 +114,8 @@ recursion_check: · 113 unmodified lines | |||
| 114 | * If it comes up a second time then there's something wrong going on: | 114 | * If it comes up a second time then there's something wrong going on: |
| 115 | * just break out and report an unknown stack type. | 115 | * just break out and report an unknown stack type. |
| 116 | */ | 116 | */ |
| 117 | if (*visit_mask & (1UL << info->type)) { | 117 | if (*visit_mask & (1UL << info->type)) |
| 118 | printk_deferred_once(KERN_WARNING | ||
| 119 | "WARNING: stack recursion on stack type %d\n", | ||
| 120 | info->type); | ||
| 121 | goto unknown; | 118 | goto unknown; |
| 122 | } | ||
| 123 | *visit_mask |= 1UL << info->type; | 119 | *visit_mask |= 1UL << info->type; |
| 124 | return 0; | 120 | return 0; |
| 125 | unknown: | 121 | unknown: |
| @@ -60,12 +60,5 @@ ENTRY(startup_continue) · 59 unmodified lines | |||
| 60 | 60 | ||
| 61 | .align 16 | 61 | .align 16 |
| 62 | .LPG1: | 62 | .LPG1: |
| 63 | .Lpcmsk:.quad 0x0000000180000000 | ||
| 64 | .L4malign:.quad 0xffffffffffc00000 | ||
| 65 | .Lscan2g:.quad 0x80000000 + 0x20000 - 8 # 2GB + 128K - 8 | ||
| 66 | .Lnop: .long 0x07000700 | ||
| 67 | .Lparmaddr: | ||
| 68 | .quad PARMAREA | ||
| 69 | .align 64 | ||
| 70 | .Ldw: .quad 0x0002000180000000,0x0000000000000000 | 63 | .Ldw: .quad 0x0002000180000000,0x0000000000000000 |
| 71 | .Laregs:.long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 | 64 | .Laregs:.long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 |
| @@ -31,7 +31,6 @@ · 30 unmodified lines | |||
| 31 | #include <asm/os_info.h> | 31 | #include <asm/os_info.h> |
| 32 | #include <asm/sections.h> | 32 | #include <asm/sections.h> |
| 33 | #include <asm/boot_data.h> | 33 | #include <asm/boot_data.h> |
| 34 | #include <asm/uv.h> | ||
| 35 | #include "entry.h" | 34 | #include "entry.h" |
| 36 | 35 | ||
| 37 | #define IPL_PARM_BLOCK_VERSION 0 | 36 | #define IPL_PARM_BLOCK_VERSION 0 |
| @@ -892,21 +891,15 @@ static void __reipl_run(void *unused) · 854 unmodified lines | |||
| 892 | { | 891 | { |
| 893 | switch (reipl_type) { | 892 | switch (reipl_type) { |
| 894 | case IPL_TYPE_CCW: | 893 | case IPL_TYPE_CCW: |
| 895 | uv_set_shared(__pa(reipl_block_ccw)); | ||
| 896 | diag308(DIAG308_SET, reipl_block_ccw); | 894 | diag308(DIAG308_SET, reipl_block_ccw); |
| 897 | uv_remove_shared(__pa(reipl_block_ccw)); | ||
| 898 | diag308(DIAG308_LOAD_CLEAR, NULL); | 895 | diag308(DIAG308_LOAD_CLEAR, NULL); |
| 899 | break; | 896 | break; |
| 900 | case IPL_TYPE_FCP: | 897 | case IPL_TYPE_FCP: |
| 901 | uv_set_shared(__pa(reipl_block_fcp)); | ||
| 902 | diag308(DIAG308_SET, reipl_block_fcp); | 898 | diag308(DIAG308_SET, reipl_block_fcp); |
| 903 | uv_remove_shared(__pa(reipl_block_fcp)); | ||
| 904 | diag308(DIAG308_LOAD_CLEAR, NULL); | 899 | diag308(DIAG308_LOAD_CLEAR, NULL); |
| 905 | break; | 900 | break; |
| 906 | case IPL_TYPE_NSS: | 901 | case IPL_TYPE_NSS: |
| 907 | uv_set_shared(__pa(reipl_block_nss)); | ||
| 908 | diag308(DIAG308_SET, reipl_block_nss); | 902 | diag308(DIAG308_SET, reipl_block_nss); |
| 909 | uv_remove_shared(__pa(reipl_block_nss)); | ||
| 910 | diag308(DIAG308_LOAD_CLEAR, NULL); | 903 | diag308(DIAG308_LOAD_CLEAR, NULL); |
| 911 | break; | 904 | break; |
| 912 | case IPL_TYPE_UNKNOWN: | 905 | case IPL_TYPE_UNKNOWN: |
| @@ -1176,9 +1169,7 @@ static struct kset *dump_kset; · 263 unmodified lines | |||
| 1176 | 1169 | ||
| 1177 | static void diag308_dump(void *dump_block) | 1170 | static void diag308_dump(void *dump_block) |
| 1178 | { | 1171 | { |
| 1179 | uv_set_shared(__pa(dump_block)); | ||
| 1180 | diag308(DIAG308_SET, dump_block); | 1172 | diag308(DIAG308_SET, dump_block); |
| 1181 | uv_remove_shared(__pa(dump_block)); | ||
| 1182 | while (1) { | 1173 | while (1) { |
| 1183 | if (diag308(DIAG308_LOAD_NORMAL_DUMP, NULL) != 0x302) | 1174 | if (diag308(DIAG308_LOAD_NORMAL_DUMP, NULL) != 0x302) |
| 1184 | break; | 1175 | break; |
| @@ -1,5 +1,6 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | #include <linux/elf.h> | 2 | #include <linux/elf.h> |
| 3 | #include <asm/kexec.h> | ||
| 3 | 4 | ||
| 4 | int arch_kexec_do_relocs(int r_type, void *loc, unsigned long val, | 5 | int arch_kexec_do_relocs(int r_type, void *loc, unsigned long val, |
| 5 | unsigned long addr) | 6 | unsigned long addr) |
| @@ -34,7 +34,7 @@ struct cf_diag_csd { /* Counter set data per CPU */ · 33 unmodified lines | |||
| 34 | unsigned char start[PAGE_SIZE]; /* Counter set at event start */ | 34 | unsigned char start[PAGE_SIZE]; /* Counter set at event start */ |
| 35 | unsigned char data[PAGE_SIZE]; /* Counter set at event delete */ | 35 | unsigned char data[PAGE_SIZE]; /* Counter set at event delete */ |
| 36 | }; | 36 | }; |
| 37 | DEFINE_PER_CPU(struct cf_diag_csd, cf_diag_csd); | 37 | static DEFINE_PER_CPU(struct cf_diag_csd, cf_diag_csd); |
| 38 | 38 | ||
| 39 | /* Counter sets are stored as data stream in a page sized memory buffer and | 39 | /* Counter sets are stored as data stream in a page sized memory buffer and |
| 40 | * exported to user space via raw data attached to the event sample data. | 40 | * exported to user space via raw data attached to the event sample data. |
| @@ -1114,8 +1114,7 @@ void __init setup_arch(char **cmdline_p) · 1113 unmodified lines | |||
| 1114 | 1114 | ||
| 1115 | ROOT_DEV = Root_RAM0; | 1115 | ROOT_DEV = Root_RAM0; |
| 1116 | 1116 | ||
| 1117 | /* Is init_mm really needed? */ | 1117 | init_mm.start_code = (unsigned long) _text; |
| 1118 | init_mm.start_code = PAGE_OFFSET; | ||
| 1119 | init_mm.end_code = (unsigned long) _etext; | 1118 | init_mm.end_code = (unsigned long) _etext; |
| 1120 | init_mm.end_data = (unsigned long) _edata; | 1119 | init_mm.end_data = (unsigned long) _edata; |
| 1121 | init_mm.brk = (unsigned long) _end; | 1120 | init_mm.brk = (unsigned long) _end; |
| @@ -437,4 +437,4 @@ · 436 unmodified lines | |||
| 437 | 432 common fsmount sys_fsmount sys_fsmount | 437 | 432 common fsmount sys_fsmount sys_fsmount |
| 438 | 433 common fspick sys_fspick sys_fspick | 438 | 433 common fspick sys_fspick sys_fspick |
| 439 | 434 common pidfd_open sys_pidfd_open sys_pidfd_open | 439 | 434 common pidfd_open sys_pidfd_open sys_pidfd_open |
| 440 | # 435 reserved for clone3 | 440 | 435 common clone3 sys_clone3 sys_clone3 |
| @@ -216,11 +216,6 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp) · 215 unmodified lines | |||
| 216 | 216 | ||
| 217 | if (!vdso_enabled) | 217 | if (!vdso_enabled) |
| 218 | return 0; | 218 | return 0; |
| 219 | /* | ||
| 220 | * Only map the vdso for dynamically linked elf binaries. | ||
| 221 | */ | ||
| 222 | if (!uses_interp) | ||
| 223 | return 0; | ||
| 224 | 219 | ||
| 225 | vdso_pages = vdso64_pages; | 220 | vdso_pages = vdso64_pages; |
| 226 | #ifdef CONFIG_COMPAT_VDSO | 221 | #ifdef CONFIG_COMPAT_VDSO |
| @@ -32,10 +32,9 @@ PHDRS { · 31 unmodified lines | |||
| 32 | SECTIONS | 32 | SECTIONS |
| 33 | { | 33 | { |
| 34 | . = 0x100000; | 34 | . = 0x100000; |
| 35 | _stext = .; /* Start of text section */ | ||
| 36 | .text : { | 35 | .text : { |
| 37 | /* Text and read-only data */ | 36 | _stext = .; /* Start of text section */ |
| 38 | _text = .; | 37 | _text = .; /* Text and read-only data */ |
| 39 | HEAD_TEXT | 38 | HEAD_TEXT |
| 40 | TEXT_TEXT | 39 | TEXT_TEXT |
| 41 | SCHED_TEXT | 40 | SCHED_TEXT |
| @@ -47,11 +46,10 @@ SECTIONS · 5 unmodified lines | |||
| 47 | *(.text.*_indirect_*) | 46 | *(.text.*_indirect_*) |
| 48 | *(.fixup) | 47 | *(.fixup) |
| 49 | *(.gnu.warning) | 48 | *(.gnu.warning) |
| 49 | . = ALIGN(PAGE_SIZE); | ||
| 50 | _etext = .; /* End of text section */ | ||
| 50 | } :text = 0x0700 | 51 | } :text = 0x0700 |
| 51 | 52 | ||
| 52 | . = ALIGN(PAGE_SIZE); | ||
| 53 | _etext = .; /* End of text section */ | ||
| 54 | |||
| 55 | NOTES :text :note | 53 | NOTES :text :note |
| 56 | 54 | ||
| 57 | .dummy : { *(.dummy) } :data | 55 | .dummy : { *(.dummy) } :data |
| @@ -2516,16 +2516,6 @@ out_err: · 2515 unmodified lines | |||
| 2516 | return rc; | 2516 | return rc; |
| 2517 | } | 2517 | } |
| 2518 | 2518 | ||
| 2519 | bool kvm_arch_has_vcpu_debugfs(void) | ||
| 2520 | { | ||
| 2521 | return false; | ||
| 2522 | } | ||
| 2523 | |||
| 2524 | int kvm_arch_create_vcpu_debugfs(struct kvm_vcpu *vcpu) | ||
| 2525 | { | ||
| 2526 | return 0; | ||
| 2527 | } | ||
| 2528 | |||
| 2529 | void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) | 2519 | void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) |
| 2530 | { | 2520 | { |
| 2531 | VCPU_EVENT(vcpu, 3, "%s", "free cpu"); | 2521 | VCPU_EVENT(vcpu, 3, "%s", "free cpu"); |
| @@ -9,6 +9,7 @@ · 8 unmodified lines | |||
| 9 | #include <linux/types.h> | 9 | #include <linux/types.h> |
| 10 | #include <linux/export.h> | 10 | #include <linux/export.h> |
| 11 | #include <linux/raid/xor.h> | 11 | #include <linux/raid/xor.h> |
| 12 | #include <asm/xor.h> | ||
| 12 | 13 | ||
| 13 | static void xor_xc_2(unsigned long bytes, unsigned long *p1, unsigned long *p2) | 14 | static void xor_xc_2(unsigned long bytes, unsigned long *p1, unsigned long *p2) |
| 14 | { | 15 | { |
| @@ -161,9 +161,9 @@ static void walk_pmd_level(struct seq_file *m, struct pg_state *st, · 160 unmodified lines | |||
| 161 | } | 161 | } |
| 162 | #endif | 162 | #endif |
| 163 | 163 | ||
| 164 | for (i = 0; i < PTRS_PER_PMD && addr < max_addr; i++) { | 164 | pmd = pmd_offset(pud, addr); |
| 165 | for (i = 0; i < PTRS_PER_PMD && addr < max_addr; i++, pmd++) { | ||
| 165 | st->current_address = addr; | 166 | st->current_address = addr; |
| 166 | pmd = pmd_offset(pud, addr); | ||
| 167 | if (!pmd_none(*pmd)) { | 167 | if (!pmd_none(*pmd)) { |
| 168 | if (pmd_large(*pmd)) { | 168 | if (pmd_large(*pmd)) { |
| 169 | prot = pmd_val(*pmd) & | 169 | prot = pmd_val(*pmd) & |
| @@ -192,9 +192,9 @@ static void walk_pud_level(struct seq_file *m, struct pg_state *st, · 22 unmodified lines | |||
| 192 | } | 192 | } |
| 193 | #endif | 193 | #endif |
| 194 | 194 | ||
| 195 | for (i = 0; i < PTRS_PER_PUD && addr < max_addr; i++) { | 195 | pud = pud_offset(p4d, addr); |
| 196 | for (i = 0; i < PTRS_PER_PUD && addr < max_addr; i++, pud++) { | ||
| 196 | st->current_address = addr; | 197 | st->current_address = addr; |
| 197 | pud = pud_offset(p4d, addr); | ||
| 198 | if (!pud_none(*pud)) | 198 | if (!pud_none(*pud)) |
| 199 | if (pud_large(*pud)) { | 199 | if (pud_large(*pud)) { |
| 200 | prot = pud_val(*pud) & | 200 | prot = pud_val(*pud) & |
| @@ -222,9 +222,9 @@ static void walk_p4d_level(struct seq_file *m, struct pg_state *st, · 21 unmodified lines | |||
| 222 | } | 222 | } |
| 223 | #endif | 223 | #endif |
| 224 | 224 | ||
| 225 | for (i = 0; i < PTRS_PER_P4D && addr < max_addr; i++) { | 225 | p4d = p4d_offset(pgd, addr); |
| 226 | for (i = 0; i < PTRS_PER_P4D && addr < max_addr; i++, p4d++) { | ||
| 226 | st->current_address = addr; | 227 | st->current_address = addr; |
| 227 | p4d = p4d_offset(pgd, addr); | ||
| 228 | if (!p4d_none(*p4d)) | 228 | if (!p4d_none(*p4d)) |
| 229 | walk_pud_level(m, st, p4d, addr); | 229 | walk_pud_level(m, st, p4d, addr); |
| 230 | else | 230 | else |
| @@ -327,6 +327,7 @@ static noinline void do_fault_error(struct pt_regs *regs, int access, · 326 unmodified lines | |||
| 327 | case VM_FAULT_BADACCESS: | 327 | case VM_FAULT_BADACCESS: |
| 328 | if (access == VM_EXEC && signal_return(regs) == 0) | 328 | if (access == VM_EXEC && signal_return(regs) == 0) |
| 329 | break; | 329 | break; |
| 330 | /* fallthrough */ | ||
| 330 | case VM_FAULT_BADMAP: | 331 | case VM_FAULT_BADMAP: |
| 331 | /* Bad memory access. Check if it is kernel or user space. */ | 332 | /* Bad memory access. Check if it is kernel or user space. */ |
| 332 | if (user_mode(regs)) { | 333 | if (user_mode(regs)) { |
| @@ -336,7 +337,9 @@ static noinline void do_fault_error(struct pt_regs *regs, int access, · 3 unmodified lines | |||
| 336 | do_sigsegv(regs, si_code); | 337 | do_sigsegv(regs, si_code); |
| 337 | break; | 338 | break; |
| 338 | } | 339 | } |
| 340 | /* fallthrough */ | ||
| 339 | case VM_FAULT_BADCONTEXT: | 341 | case VM_FAULT_BADCONTEXT: |
| 342 | /* fallthrough */ | ||
| 340 | case VM_FAULT_PFAULT: | 343 | case VM_FAULT_PFAULT: |
| 341 | do_no_context(regs); | 344 | do_no_context(regs); |
| 342 | break; | 345 | break; |
| @@ -2424,8 +2424,8 @@ EXPORT_SYMBOL_GPL(gmap_pmdp_idte_global); · 2423 unmodified lines | |||
| 2424 | * This function is assumed to be called with the guest_table_lock | 2424 | * This function is assumed to be called with the guest_table_lock |
| 2425 | * held. | 2425 | * held. |
| 2426 | */ | 2426 | */ |
| 2427 | bool gmap_test_and_clear_dirty_pmd(struct gmap *gmap, pmd_t *pmdp, | 2427 | static bool gmap_test_and_clear_dirty_pmd(struct gmap *gmap, pmd_t *pmdp, |
| 2428 | unsigned long gaddr) | 2428 | unsigned long gaddr) |
| 2429 | { | 2429 | { |
| 2430 | if (pmd_val(*pmdp) & _SEGMENT_ENTRY_INVALID) | 2430 | if (pmd_val(*pmdp) & _SEGMENT_ENTRY_INVALID) |
| 2431 | return false; | 2431 | return false; |
| @@ -17,8 +17,6 @@ · 16 unmodified lines | |||
| 17 | 17 | ||
| 18 | #ifdef CONFIG_PGSTE | 18 | #ifdef CONFIG_PGSTE |
| 19 | 19 | ||
| 20 | static int page_table_allocate_pgste_min = 0; | ||
| 21 | static int page_table_allocate_pgste_max = 1; | ||
| 22 | int page_table_allocate_pgste = 0; | 20 | int page_table_allocate_pgste = 0; |
| 23 | EXPORT_SYMBOL(page_table_allocate_pgste); | 21 | EXPORT_SYMBOL(page_table_allocate_pgste); |
| 24 | 22 | ||
| @@ -29,8 +27,8 @@ static struct ctl_table page_table_sysctl[] = { · 4 unmodified lines | |||
| 29 | .maxlen = sizeof(int), | 27 | .maxlen = sizeof(int), |
| 30 | .mode = S_IRUGO | S_IWUSR, | 28 | .mode = S_IRUGO | S_IWUSR, |
| 31 | .proc_handler = proc_dointvec_minmax, | 29 | .proc_handler = proc_dointvec_minmax, |
| 32 | .extra1 = &page_table_allocate_pgste_min, | 30 | .extra1 = SYSCTL_ZERO, |
| 33 | .extra2 = &page_table_allocate_pgste_max, | 31 | .extra2 = SYSCTL_ONE, |
| 34 | }, | 32 | }, |
| 35 | { } | 33 | { } |
| 36 | }; | 34 | }; |
| @@ -11,8 +11,7 @@ chkbss: $(addprefix $(obj)/, $(chkbss-files)) · 10 unmodified lines | |||
| 11 | 11 | ||
| 12 | quiet_cmd_chkbss = CHKBSS $< | 12 | quiet_cmd_chkbss = CHKBSS $< |
| 13 | cmd_chkbss = \ | 13 | cmd_chkbss = \ |
| 14 | if $(OBJDUMP) -h $< | grep -q "\.bss" && \ | 14 | if ! $(OBJSIZE) --common $< | $(AWK) 'END { if ($$3) exit 1 }'; then \ |
| 15 | ! $(OBJDUMP) -j .bss -w -h $< | awk 'END { if ($$3) exit 1 }'; then \ | ||
| 16 | echo "error: $< .bss section is not empty" >&2; exit 1; \ | 15 | echo "error: $< .bss section is not empty" >&2; exit 1; \ |
| 17 | fi; \ | 16 | fi; \ |
| 18 | touch $@; | 17 | touch $@; |
| @@ -1,2 +1,2 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0 */ | 1 | /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ |
| 2 | #include <asm-generic/setup.h> | 2 | #include <asm-generic/setup.h> |
| @@ -1,2 +1,2 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0 */ | 1 | /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ |
| 2 | #include <asm-generic/types.h> | 2 | #include <asm-generic/types.h> |
| @@ -475,8 +475,6 @@ static void print_sh_insn(u32 memaddr, u16 insn) · 474 unmodified lines | |||
| 475 | printk("dbr"); | 475 | printk("dbr"); |
| 476 | break; | 476 | break; |
| 477 | case FD_REG_N: | 477 | case FD_REG_N: |
| 478 | if (0) | ||
| 479 | goto d_reg_n; | ||
| 480 | case F_REG_N: | 478 | case F_REG_N: |
| 481 | printk("fr%d", rn); | 479 | printk("fr%d", rn); |
| 482 | break; | 480 | break; |
| @@ -488,7 +486,7 @@ static void print_sh_insn(u32 memaddr, u16 insn) · 5 unmodified lines | |||
| 488 | printk("xd%d", rn & ~1); | 486 | printk("xd%d", rn & ~1); |
| 489 | break; | 487 | break; |
| 490 | } | 488 | } |
| 491 | d_reg_n: | 489 | /* else, fall through */ |
| 492 | case D_REG_N: | 490 | case D_REG_N: |
| 493 | printk("dr%d", rn); | 491 | printk("dr%d", rn); |
| 494 | break; | 492 | break; |
| @@ -497,6 +495,7 @@ static void print_sh_insn(u32 memaddr, u16 insn) · 2 unmodified lines | |||
| 497 | printk("xd%d", rm & ~1); | 495 | printk("xd%d", rm & ~1); |
| 498 | break; | 496 | break; |
| 499 | } | 497 | } |
| 498 | /* else, fall through */ | ||
| 500 | case D_REG_M: | 499 | case D_REG_M: |
| 501 | printk("dr%d", rm); | 500 | printk("dr%d", rm); |
| 502 | break; | 501 | break; |
| @@ -157,6 +157,7 @@ int arch_bp_generic_fields(int sh_len, int sh_type, · 156 unmodified lines | |||
| 157 | switch (sh_type) { | 157 | switch (sh_type) { |
| 158 | case SH_BREAKPOINT_READ: | 158 | case SH_BREAKPOINT_READ: |
| 159 | *gen_type = HW_BREAKPOINT_R; | 159 | *gen_type = HW_BREAKPOINT_R; |
| 160 | break; | ||
| 160 | case SH_BREAKPOINT_WRITE: | 161 | case SH_BREAKPOINT_WRITE: |
| 161 | *gen_type = HW_BREAKPOINT_W; | 162 | *gen_type = HW_BREAKPOINT_W; |
| 162 | break; | 163 | break; |
| @@ -1,4 +1,4 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later WITH Linux-syscall-note */ |
| 2 | /* | 2 | /* |
| 3 | * Copyright (c) 2017, Oracle and/or its affiliates. All rights reserved. | 3 | * Copyright (c) 2017, Oracle and/or its affiliates. All rights reserved. |
| 4 | */ | 4 | */ |
| @@ -37,6 +37,14 @@ int memcmp(const void *s1, const void *s2, size_t len) · 36 unmodified lines | |||
| 37 | return diff; | 37 | return diff; |
| 38 | } | 38 | } |
| 39 | 39 | ||
| 40 | /* | ||
| 41 | * Clang may lower `memcmp == 0` to `bcmp == 0`. | ||
| 42 | */ | ||
| 43 | int bcmp(const void *s1, const void *s2, size_t len) | ||
| 44 | { | ||
| 45 | return memcmp(s1, s2, len); | ||
| 46 | } | ||
| 47 | |||
| 40 | int strcmp(const char *str1, const char *str2) | 48 | int strcmp(const char *str1, const char *str2) |
| 41 | { | 49 | { |
| 42 | const unsigned char *s1 = (const unsigned char *)str1; | 50 | const unsigned char *s1 = (const unsigned char *)str1; |
| @@ -314,6 +314,23 @@ For 32-bit we have the following conventions - kernel is built with · 313 unmodified lines | |||
| 314 | 314 | ||
| 315 | #endif | 315 | #endif |
| 316 | 316 | ||
| 317 | /* | ||
| 318 | * Mitigate Spectre v1 for conditional swapgs code paths. | ||
| 319 | * | ||
| 320 | * FENCE_SWAPGS_USER_ENTRY is used in the user entry swapgs code path, to | ||
| 321 | * prevent a speculative swapgs when coming from kernel space. | ||
| 322 | * | ||
| 323 | * FENCE_SWAPGS_KERNEL_ENTRY is used in the kernel entry non-swapgs code path, | ||
| 324 | * to prevent the swapgs from getting speculatively skipped when coming from | ||
| 325 | * user space. | ||
| 326 | */ | ||
| 327 | .macro FENCE_SWAPGS_USER_ENTRY | ||
| 328 | ALTERNATIVE "", "lfence", X86_FEATURE_FENCE_SWAPGS_USER | ||
| 329 | .endm | ||
| 330 | .macro FENCE_SWAPGS_KERNEL_ENTRY | ||
| 331 | ALTERNATIVE "", "lfence", X86_FEATURE_FENCE_SWAPGS_KERNEL | ||
| 332 | .endm | ||
| 333 | |||
| 317 | .macro STACKLEAK_ERASE_NOCLOBBER | 334 | .macro STACKLEAK_ERASE_NOCLOBBER |
| 318 | #ifdef CONFIG_GCC_PLUGIN_STACKLEAK | 335 | #ifdef CONFIG_GCC_PLUGIN_STACKLEAK |
| 319 | PUSH_AND_CLEAR_REGS | 336 | PUSH_AND_CLEAR_REGS |
| @@ -1443,8 +1443,12 @@ BUILD_INTERRUPT3(hv_stimer0_callback_vector, HYPERV_STIMER0_VECTOR, · 1442 unmodified lines | |||
| 1443 | 1443 | ||
| 1444 | ENTRY(page_fault) | 1444 | ENTRY(page_fault) |
| 1445 | ASM_CLAC | 1445 | ASM_CLAC |
| 1446 | pushl $0; /* %gs's slot on the stack */ | 1446 | pushl $do_page_fault |
| 1447 | jmp common_exception_read_cr2 | ||
| 1448 | END(page_fault) | ||
| 1447 | 1449 | ||
| 1450 | common_exception_read_cr2: | ||
| 1451 | /* the function address is in %gs's slot on the stack */ | ||
| 1448 | SAVE_ALL switch_stacks=1 skip_gs=1 | 1452 | SAVE_ALL switch_stacks=1 skip_gs=1 |
| 1449 | 1453 | ||
| 1450 | ENCODE_FRAME_POINTER | 1454 | ENCODE_FRAME_POINTER |
| @@ -1452,6 +1456,7 @@ ENTRY(page_fault) · 1 unmodified line | |||
| 1452 | 1456 | ||
| 1453 | /* fixup %gs */ | 1457 | /* fixup %gs */ |
| 1454 | GS_TO_REG %ecx | 1458 | GS_TO_REG %ecx |
| 1459 | movl PT_GS(%esp), %edi | ||
| 1455 | REG_TO_PTGS %ecx | 1460 | REG_TO_PTGS %ecx |
| 1456 | SET_KERNEL_GS %ecx | 1461 | SET_KERNEL_GS %ecx |
| 1457 | 1462 | ||
| @@ -1463,9 +1468,9 @@ ENTRY(page_fault) · 5 unmodified lines | |||
| 1463 | 1468 | ||
| 1464 | TRACE_IRQS_OFF | 1469 | TRACE_IRQS_OFF |
| 1465 | movl %esp, %eax # pt_regs pointer | 1470 | movl %esp, %eax # pt_regs pointer |
| 1466 | call do_page_fault | 1471 | CALL_NOSPEC %edi |
| 1467 | jmp ret_from_exception | 1472 | jmp ret_from_exception |
| 1468 | END(page_fault) | 1473 | END(common_exception_read_cr2) |
| 1469 | 1474 | ||
| 1470 | common_exception: | 1475 | common_exception: |
| 1471 | /* the function address is in %gs's slot on the stack */ | 1476 | /* the function address is in %gs's slot on the stack */ |
| @@ -1595,7 +1600,7 @@ END(general_protection) · 123 unmodified lines | |||
| 1595 | ENTRY(async_page_fault) | 1600 | ENTRY(async_page_fault) |
| 1596 | ASM_CLAC | 1601 | ASM_CLAC |
| 1597 | pushl $do_async_page_fault | 1602 | pushl $do_async_page_fault |
| 1598 | jmp common_exception | 1603 | jmp common_exception_read_cr2 |
| 1599 | END(async_page_fault) | 1604 | END(async_page_fault) |
| 1600 | #endif | 1605 | #endif |
| 1601 | 1606 | ||
| @@ -519,7 +519,7 @@ ENTRY(interrupt_entry) · 518 unmodified lines | |||
| 519 | testb $3, CS-ORIG_RAX+8(%rsp) | 519 | testb $3, CS-ORIG_RAX+8(%rsp) |
| 520 | jz 1f | 520 | jz 1f |
| 521 | SWAPGS | 521 | SWAPGS |
| 522 | 522 | FENCE_SWAPGS_USER_ENTRY | |
| 523 | /* | 523 | /* |
| 524 | * Switch to the thread stack. The IRET frame and orig_ax are | 524 | * Switch to the thread stack. The IRET frame and orig_ax are |
| 525 | * on the stack, as well as the return address. RDI..R12 are | 525 | * on the stack, as well as the return address. RDI..R12 are |
| @@ -549,8 +549,10 @@ ENTRY(interrupt_entry) · 23 unmodified lines | |||
| 549 | UNWIND_HINT_FUNC | 549 | UNWIND_HINT_FUNC |
| 550 | 550 | ||
| 551 | movq (%rdi), %rdi | 551 | movq (%rdi), %rdi |
| 552 | jmp 2f | ||
| 552 | 1: | 553 | 1: |
| 553 | 554 | FENCE_SWAPGS_KERNEL_ENTRY | |
| 555 | 2: | ||
| 554 | PUSH_AND_CLEAR_REGS save_ret=1 | 556 | PUSH_AND_CLEAR_REGS save_ret=1 |
| 555 | ENCODE_FRAME_POINTER 8 | 557 | ENCODE_FRAME_POINTER 8 |
| 556 | 558 | ||
| @@ -1238,6 +1240,13 @@ ENTRY(paranoid_entry) · 681 unmodified lines | |||
| 1238 | */ | 1240 | */ |
| 1239 | SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg=%rax save_reg=%r14 | 1241 | SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg=%rax save_reg=%r14 |
| 1240 | 1242 | ||
| 1243 | /* | ||
| 1244 | * The above SAVE_AND_SWITCH_TO_KERNEL_CR3 macro doesn't do an | ||
| 1245 | * unconditional CR3 write, even in the PTI case. So do an lfence | ||
| 1246 | * to prevent GS speculation, regardless of whether PTI is enabled. | ||
| 1247 | */ | ||
| 1248 | FENCE_SWAPGS_KERNEL_ENTRY | ||
| 1249 | |||
| 1241 | ret | 1250 | ret |
| 1242 | END(paranoid_entry) | 1251 | END(paranoid_entry) |
| 1243 | 1252 | ||
| @@ -1288,6 +1297,7 @@ ENTRY(error_entry) · 44 unmodified lines | |||
| 1288 | * from user mode due to an IRET fault. | 1297 | * from user mode due to an IRET fault. |
| 1289 | */ | 1298 | */ |
| 1290 | SWAPGS | 1299 | SWAPGS |
| 1300 | FENCE_SWAPGS_USER_ENTRY | ||
| 1291 | /* We have user CR3. Change to kernel CR3. */ | 1301 | /* We have user CR3. Change to kernel CR3. */ |
| 1292 | SWITCH_TO_KERNEL_CR3 scratch_reg=%rax | 1302 | SWITCH_TO_KERNEL_CR3 scratch_reg=%rax |
| 1293 | 1303 | ||
| @@ -1301,6 +1311,8 @@ ENTRY(error_entry) · 7 unmodified lines | |||
| 1301 | pushq %r12 | 1311 | pushq %r12 |
| 1302 | ret | 1312 | ret |
| 1303 | 1313 | ||
| 1314 | .Lerror_entry_done_lfence: | ||
| 1315 | FENCE_SWAPGS_KERNEL_ENTRY | ||
| 1304 | .Lerror_entry_done: | 1316 | .Lerror_entry_done: |
| 1305 | ret | 1317 | ret |
| 1306 | 1318 | ||
| @@ -1318,7 +1330,7 @@ ENTRY(error_entry) · 11 unmodified lines | |||
| 1318 | cmpq %rax, RIP+8(%rsp) | 1330 | cmpq %rax, RIP+8(%rsp) |
| 1319 | je .Lbstep_iret | 1331 | je .Lbstep_iret |
| 1320 | cmpq $.Lgs_change, RIP+8(%rsp) | 1332 | cmpq $.Lgs_change, RIP+8(%rsp) |
| 1321 | jne .Lerror_entry_done | 1333 | jne .Lerror_entry_done_lfence |
| 1322 | 1334 | ||
| 1323 | /* | 1335 | /* |
| 1324 | * hack: .Lgs_change can fail with user gsbase. If this happens, fix up | 1336 | * hack: .Lgs_change can fail with user gsbase. If this happens, fix up |
| @@ -1326,6 +1338,7 @@ ENTRY(error_entry) · 1 unmodified line | |||
| 1326 | * .Lgs_change's error handler with kernel gsbase. | 1338 | * .Lgs_change's error handler with kernel gsbase. |
| 1327 | */ | 1339 | */ |
| 1328 | SWAPGS | 1340 | SWAPGS |
| 1341 | FENCE_SWAPGS_USER_ENTRY | ||
| 1329 | SWITCH_TO_KERNEL_CR3 scratch_reg=%rax | 1342 | SWITCH_TO_KERNEL_CR3 scratch_reg=%rax |
| 1330 | jmp .Lerror_entry_done | 1343 | jmp .Lerror_entry_done |
| 1331 | 1344 | ||
| @@ -1340,6 +1353,7 @@ ENTRY(error_entry) · 8 unmodified lines | |||
| 1340 | * gsbase and CR3. Switch to kernel gsbase and CR3: | 1353 | * gsbase and CR3. Switch to kernel gsbase and CR3: |
| 1341 | */ | 1354 | */ |
| 1342 | SWAPGS | 1355 | SWAPGS |
| 1356 | FENCE_SWAPGS_USER_ENTRY | ||
| 1343 | SWITCH_TO_KERNEL_CR3 scratch_reg=%rax | 1357 | SWITCH_TO_KERNEL_CR3 scratch_reg=%rax |
| 1344 | 1358 | ||
| 1345 | /* | 1359 | /* |
| @@ -1431,6 +1445,7 @@ ENTRY(nmi) · 85 unmodified lines | |||
| 1431 | 1445 | ||
| 1432 | swapgs | 1446 | swapgs |
| 1433 | cld | 1447 | cld |
| 1448 | FENCE_SWAPGS_USER_ENTRY | ||
| 1434 | SWITCH_TO_KERNEL_CR3 scratch_reg=%rdx | 1449 | SWITCH_TO_KERNEL_CR3 scratch_reg=%rdx |
| 1435 | movq %rsp, %rdx | 1450 | movq %rsp, %rdx |
| 1436 | movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp | 1451 | movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp |
| @@ -20,7 +20,6 @@ · 19 unmodified lines | |||
| 20 | #include <asm/intel-family.h> | 20 | #include <asm/intel-family.h> |
| 21 | #include <asm/apic.h> | 21 | #include <asm/apic.h> |
| 22 | #include <asm/cpu_device_id.h> | 22 | #include <asm/cpu_device_id.h> |
| 23 | #include <asm/hypervisor.h> | ||
| 24 | 23 | ||
| 25 | #include "../perf_event.h" | 24 | #include "../perf_event.h" |
| 26 | 25 | ||
| @@ -263,8 +262,8 @@ static struct event_constraint intel_icl_event_constraints[] = { · 236 unmodified lines | |||
| 263 | }; | 262 | }; |
| 264 | 263 | ||
| 265 | static struct extra_reg intel_icl_extra_regs[] __read_mostly = { | 264 | static struct extra_reg intel_icl_extra_regs[] __read_mostly = { |
| 266 | INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff9fffull, RSP_0), | 265 | INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffbfffull, RSP_0), |
| 267 | INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff9fffull, RSP_1), | 266 | INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, RSP_1), |
| 268 | INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), | 267 | INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), |
| 269 | INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), | 268 | INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE), |
| 270 | EVENT_EXTRA_END | 269 | EVENT_EXTRA_END |
| @@ -4053,7 +4052,7 @@ static bool check_msr(unsigned long msr, u64 mask) · 3782 unmodified lines | |||
| 4053 | * Disable the check for real HW, so we don't | 4052 | * Disable the check for real HW, so we don't |
| 4054 | * mess with potentionaly enabled registers: | 4053 | * mess with potentionaly enabled registers: |
| 4055 | */ | 4054 | */ |
| 4056 | if (hypervisor_is_type(X86_HYPER_NATIVE)) | 4055 | if (!boot_cpu_has(X86_FEATURE_HYPERVISOR)) |
| 4057 | return true; | 4056 | return true; |
| 4058 | 4057 | ||
| 4059 | /* | 4058 | /* |
| @@ -4955,6 +4954,7 @@ __init int intel_pmu_init(void) · 895 unmodified lines | |||
| 4955 | 4954 | ||
| 4956 | case INTEL_FAM6_SKYLAKE_X: | 4955 | case INTEL_FAM6_SKYLAKE_X: |
| 4957 | pmem = true; | 4956 | pmem = true; |
| 4957 | /* fall through */ | ||
| 4958 | case INTEL_FAM6_SKYLAKE_MOBILE: | 4958 | case INTEL_FAM6_SKYLAKE_MOBILE: |
| 4959 | case INTEL_FAM6_SKYLAKE_DESKTOP: | 4959 | case INTEL_FAM6_SKYLAKE_DESKTOP: |
| 4960 | case INTEL_FAM6_KABYLAKE_MOBILE: | 4960 | case INTEL_FAM6_KABYLAKE_MOBILE: |
| @@ -5004,6 +5004,7 @@ __init int intel_pmu_init(void) · 43 unmodified lines | |||
| 5004 | case INTEL_FAM6_ICELAKE_X: | 5004 | case INTEL_FAM6_ICELAKE_X: |
| 5005 | case INTEL_FAM6_ICELAKE_XEON_D: | 5005 | case INTEL_FAM6_ICELAKE_XEON_D: |
| 5006 | pmem = true; | 5006 | pmem = true; |
| 5007 | /* fall through */ | ||
| 5007 | case INTEL_FAM6_ICELAKE_MOBILE: | 5008 | case INTEL_FAM6_ICELAKE_MOBILE: |
| 5008 | case INTEL_FAM6_ICELAKE_DESKTOP: | 5009 | case INTEL_FAM6_ICELAKE_DESKTOP: |
| 5009 | x86_pmu.late_ack = true; | 5010 | x86_pmu.late_ack = true; |
| @@ -851,7 +851,7 @@ struct event_constraint intel_skl_pebs_event_constraints[] = { · 850 unmodified lines | |||
| 851 | 851 | ||
| 852 | struct event_constraint intel_icl_pebs_event_constraints[] = { | 852 | struct event_constraint intel_icl_pebs_event_constraints[] = { |
| 853 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x100000000ULL), /* INST_RETIRED.PREC_DIST */ | 853 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x100000000ULL), /* INST_RETIRED.PREC_DIST */ |
| 854 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x400000000ULL), /* SLOTS */ | 854 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL), /* SLOTS */ |
| 855 | 855 | ||
| 856 | INTEL_PLD_CONSTRAINT(0x1cd, 0xff), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ | 856 | INTEL_PLD_CONSTRAINT(0x1cd, 0xff), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ |
| 857 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x1d0, 0xf), /* MEM_INST_RETIRED.LOAD */ | 857 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x1d0, 0xf), /* MEM_INST_RETIRED.LOAD */ |
| @@ -18,6 +18,20 @@ · 17 unmodified lines | |||
| 18 | * Note: efi_info is commonly left uninitialized, but that field has a | 18 | * Note: efi_info is commonly left uninitialized, but that field has a |
| 19 | * private magic, so it is better to leave it unchanged. | 19 | * private magic, so it is better to leave it unchanged. |
| 20 | */ | 20 | */ |
| 21 | |||
| 22 | #define sizeof_mbr(type, member) ({ sizeof(((type *)0)->member); }) | ||
| 23 | |||
| 24 | #define BOOT_PARAM_PRESERVE(struct_member) \ | ||
| 25 | { \ | ||
| 26 | .start = offsetof(struct boot_params, struct_member), \ | ||
| 27 | .len = sizeof_mbr(struct boot_params, struct_member), \ | ||
| 28 | } | ||
| 29 | |||
| 30 | struct boot_params_to_save { | ||
| 31 | unsigned int start; | ||
| 32 | unsigned int len; | ||
| 33 | }; | ||
| 34 | |||
| 21 | static void sanitize_boot_params(struct boot_params *boot_params) | 35 | static void sanitize_boot_params(struct boot_params *boot_params) |
| 22 | { | 36 | { |
| 23 | /* | 37 | /* |
| @@ -35,21 +49,40 @@ static void sanitize_boot_params(struct boot_params *boot_params) · 11 unmodified lines | |||
| 35 | * problems again. | 49 | * problems again. |
| 36 | */ | 50 | */ |
| 37 | if (boot_params->sentinel) { | 51 | if (boot_params->sentinel) { |
| 38 | /* fields in boot_params are left uninitialized, clear them */ | 52 | static struct boot_params scratch; |
| 39 | boot_params->acpi_rsdp_addr = 0; | 53 | char *bp_base = (char *)boot_params; |
| 40 | memset(&boot_params->ext_ramdisk_image, 0, | 54 | char *save_base = (char *)&scratch; |
| 41 | (char *)&boot_params->efi_info - | 55 | int i; |
| 42 | (char *)&boot_params->ext_ramdisk_image); | 56 | |
| 43 | memset(&boot_params->kbd_status, 0, | 57 | const struct boot_params_to_save to_save[] = { |
| 44 | (char *)&boot_params->hdr - | 58 | BOOT_PARAM_PRESERVE(screen_info), |
| 45 | (char *)&boot_params->kbd_status); | 59 | BOOT_PARAM_PRESERVE(apm_bios_info), |
| 46 | memset(&boot_params->_pad7[0], 0, | 60 | BOOT_PARAM_PRESERVE(tboot_addr), |
| 47 | (char *)&boot_params->edd_mbr_sig_buffer[0] - | 61 | BOOT_PARAM_PRESERVE(ist_info), |
| 48 | (char *)&boot_params->_pad7[0]); | 62 | BOOT_PARAM_PRESERVE(acpi_rsdp_addr), |
| 49 | memset(&boot_params->_pad8[0], 0, | 63 | BOOT_PARAM_PRESERVE(hd0_info), |
| 50 | (char *)&boot_params->eddbuf[0] - | 64 | BOOT_PARAM_PRESERVE(hd1_info), |
| 51 | (char *)&boot_params->_pad8[0]); | 65 | BOOT_PARAM_PRESERVE(sys_desc_table), |
| 52 | memset(&boot_params->_pad9[0], 0, sizeof(boot_params->_pad9)); | 66 | BOOT_PARAM_PRESERVE(olpc_ofw_header), |
| 67 | BOOT_PARAM_PRESERVE(efi_info), | ||
| 68 | BOOT_PARAM_PRESERVE(alt_mem_k), | ||
| 69 | BOOT_PARAM_PRESERVE(scratch), | ||
| 70 | BOOT_PARAM_PRESERVE(e820_entries), | ||
| 71 | BOOT_PARAM_PRESERVE(eddbuf_entries), | ||
| 72 | BOOT_PARAM_PRESERVE(edd_mbr_sig_buf_entries), | ||
| 73 | BOOT_PARAM_PRESERVE(edd_mbr_sig_buffer), | ||
| 74 | BOOT_PARAM_PRESERVE(e820_table), | ||
| 75 | BOOT_PARAM_PRESERVE(eddbuf), | ||
| 76 | }; | ||
| 77 | |||
| 78 | memset(&scratch, 0, sizeof(scratch)); | ||
| 79 | |||
| 80 | for (i = 0; i < ARRAY_SIZE(to_save); i++) { | ||
| 81 | memcpy(save_base + to_save[i].start, | ||
| 82 | bp_base + to_save[i].start, to_save[i].len); | ||
| 83 | } | ||
| 84 | |||
| 85 | memcpy(boot_params, save_base, sizeof(*boot_params)); | ||
| 53 | } | 86 | } |
| 54 | } | 87 | } |
| 55 | 88 | ||
| @@ -281,6 +281,8 @@ · 280 unmodified lines | |||
| 281 | #define X86_FEATURE_CQM_OCCUP_LLC (11*32+ 1) /* LLC occupancy monitoring */ | 281 | #define X86_FEATURE_CQM_OCCUP_LLC (11*32+ 1) /* LLC occupancy monitoring */ |
| 282 | #define X86_FEATURE_CQM_MBM_TOTAL (11*32+ 2) /* LLC Total MBM monitoring */ | 282 | #define X86_FEATURE_CQM_MBM_TOTAL (11*32+ 2) /* LLC Total MBM monitoring */ |
| 283 | #define X86_FEATURE_CQM_MBM_LOCAL (11*32+ 3) /* LLC Local MBM monitoring */ | 283 | #define X86_FEATURE_CQM_MBM_LOCAL (11*32+ 3) /* LLC Local MBM monitoring */ |
| 284 | #define X86_FEATURE_FENCE_SWAPGS_USER (11*32+ 4) /* "" LFENCE in user entry SWAPGS path */ | ||
| 285 | #define X86_FEATURE_FENCE_SWAPGS_KERNEL (11*32+ 5) /* "" LFENCE in kernel entry SWAPGS path */ | ||
| 284 | 286 | ||
| 285 | /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ | 287 | /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ |
| 286 | #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */ | 288 | #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */ |
| @@ -394,5 +396,6 @@ · 107 unmodified lines | |||
| 394 | #define X86_BUG_L1TF X86_BUG(18) /* CPU is affected by L1 Terminal Fault */ | 396 | #define X86_BUG_L1TF X86_BUG(18) /* CPU is affected by L1 Terminal Fault */ |
| 395 | #define X86_BUG_MDS X86_BUG(19) /* CPU is affected by Microarchitectural data sampling */ | 397 | #define X86_BUG_MDS X86_BUG(19) /* CPU is affected by Microarchitectural data sampling */ |
| 396 | #define X86_BUG_MSBDS_ONLY X86_BUG(20) /* CPU is only affected by the MSDBS variant of BUG_MDS */ | 398 | #define X86_BUG_MSBDS_ONLY X86_BUG(20) /* CPU is only affected by the MSDBS variant of BUG_MDS */ |
| 399 | #define X86_BUG_SWAPGS X86_BUG(21) /* CPU is affected by speculation through SWAPGS */ | ||
| 397 | 400 | ||
| 398 | #endif /* _ASM_X86_CPUFEATURES_H */ | 401 | #endif /* _ASM_X86_CPUFEATURES_H */ |
| @@ -35,6 +35,8 @@ · 34 unmodified lines | |||
| 35 | #include <asm/kvm_vcpu_regs.h> | 35 | #include <asm/kvm_vcpu_regs.h> |
| 36 | #include <asm/hyperv-tlfs.h> | 36 | #include <asm/hyperv-tlfs.h> |
| 37 | 37 | ||
| 38 | #define __KVM_HAVE_ARCH_VCPU_DEBUGFS | ||
| 39 | |||
| 38 | #define KVM_MAX_VCPUS 288 | 40 | #define KVM_MAX_VCPUS 288 |
| 39 | #define KVM_SOFT_MAX_VCPUS 240 | 41 | #define KVM_SOFT_MAX_VCPUS 240 |
| 40 | #define KVM_MAX_VCPU_ID 1023 | 42 | #define KVM_MAX_VCPU_ID 1023 |
| @@ -607,15 +609,16 @@ struct kvm_vcpu_arch { · 566 unmodified lines | |||
| 607 | 609 | ||
| 608 | /* | 610 | /* |
| 609 | * QEMU userspace and the guest each have their own FPU state. | 611 | * QEMU userspace and the guest each have their own FPU state. |
| 610 | * In vcpu_run, we switch between the user, maintained in the | 612 | * In vcpu_run, we switch between the user and guest FPU contexts. |
| 611 | * task_struct struct, and guest FPU contexts. While running a VCPU, | 613 | * While running a VCPU, the VCPU thread will have the guest FPU |
| 612 | * the VCPU thread will have the guest FPU context. | 614 | * context. |
| 613 | * | 615 | * |
| 614 | * Note that while the PKRU state lives inside the fpu registers, | 616 | * Note that while the PKRU state lives inside the fpu registers, |
| 615 | * it is switched out separately at VMENTER and VMEXIT time. The | 617 | * it is switched out separately at VMENTER and VMEXIT time. The |
| 616 | * "guest_fpu" state here contains the guest FPU context, with the | 618 | * "guest_fpu" state here contains the guest FPU context, with the |
| 617 | * host PRKU bits. | 619 | * host PRKU bits. |
| 618 | */ | 620 | */ |
| 621 | struct fpu *user_fpu; | ||
| 619 | struct fpu *guest_fpu; | 622 | struct fpu *guest_fpu; |
| 620 | 623 | ||
| 621 | u64 xcr0; | 624 | u64 xcr0; |
| @@ -1174,6 +1177,7 @@ struct kvm_x86_ops { · 552 unmodified lines | |||
| 1174 | int (*update_pi_irte)(struct kvm *kvm, unsigned int host_irq, | 1177 | int (*update_pi_irte)(struct kvm *kvm, unsigned int host_irq, |
| 1175 | uint32_t guest_irq, bool set); | 1178 | uint32_t guest_irq, bool set); |
| 1176 | void (*apicv_post_state_restore)(struct kvm_vcpu *vcpu); | 1179 | void (*apicv_post_state_restore)(struct kvm_vcpu *vcpu); |
| 1180 | bool (*dy_apicv_has_pending_interrupt)(struct kvm_vcpu *vcpu); | ||
| 1177 | 1181 | ||
| 1178 | int (*set_hv_timer)(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc, | 1182 | int (*set_hv_timer)(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc, |
| 1179 | bool *expired); | 1183 | bool *expired); |
| @@ -96,6 +96,8 @@ long clock_getres_fallback(clockid_t _clkid, struct __kernel_timespec *_ts) · 95 unmodified lines | |||
| 96 | 96 | ||
| 97 | #else | 97 | #else |
| 98 | 98 | ||
| 99 | #define VDSO_HAS_32BIT_FALLBACK 1 | ||
| 100 | |||
| 99 | static __always_inline | 101 | static __always_inline |
| 100 | long clock_gettime_fallback(clockid_t _clkid, struct __kernel_timespec *_ts) | 102 | long clock_gettime_fallback(clockid_t _clkid, struct __kernel_timespec *_ts) |
| 101 | { | 103 | { |
| @@ -113,6 +115,23 @@ long clock_gettime_fallback(clockid_t _clkid, struct __kernel_timespec *_ts) · 11 unmodified lines | |||
| 113 | return ret; | 115 | return ret; |
| 114 | } | 116 | } |
| 115 | 117 | ||
| 118 | static __always_inline | ||
| 119 | long clock_gettime32_fallback(clockid_t _clkid, struct old_timespec32 *_ts) | ||
| 120 | { | ||
| 121 | long ret; | ||
| 122 | |||
| 123 | asm ( | ||
| 124 | "mov %%ebx, %%edx \n" | ||
| 125 | "mov %[clock], %%ebx \n" | ||
| 126 | "call __kernel_vsyscall \n" | ||
| 127 | "mov %%edx, %%ebx \n" | ||
| 128 | : "=a" (ret), "=m" (*_ts) | ||
| 129 | : "0" (__NR_clock_gettime), [clock] "g" (_clkid), "c" (_ts) | ||
| 130 | : "edx"); | ||
| 131 | |||
| 132 | return ret; | ||
| 133 | } | ||
| 134 | |||
| 116 | static __always_inline | 135 | static __always_inline |
| 117 | long gettimeofday_fallback(struct __kernel_old_timeval *_tv, | 136 | long gettimeofday_fallback(struct __kernel_old_timeval *_tv, |
| 118 | struct timezone *_tz) | 137 | struct timezone *_tz) |
| @@ -148,6 +167,23 @@ clock_getres_fallback(clockid_t _clkid, struct __kernel_timespec *_ts) · 29 unmodified lines | |||
| 148 | return ret; | 167 | return ret; |
| 149 | } | 168 | } |
| 150 | 169 | ||
| 170 | static __always_inline | ||
| 171 | long clock_getres32_fallback(clockid_t _clkid, struct old_timespec32 *_ts) | ||
| 172 | { | ||
| 173 | long ret; | ||
| 174 | |||
| 175 | asm ( | ||
| 176 | "mov %%ebx, %%edx \n" | ||
| 177 | "mov %[clock], %%ebx \n" | ||
| 178 | "call __kernel_vsyscall \n" | ||
| 179 | "mov %%edx, %%ebx \n" | ||
| 180 | : "=a" (ret), "=m" (*_ts) | ||
| 181 | : "0" (__NR_clock_getres), [clock] "g" (_clkid), "c" (_ts) | ||
| 182 | : "edx"); | ||
| 183 | |||
| 184 | return ret; | ||
| 185 | } | ||
| 186 | |||
| 151 | #endif | 187 | #endif |
| 152 | 188 | ||
| 153 | #ifdef CONFIG_PARAVIRT_CLOCK | 189 | #ifdef CONFIG_PARAVIRT_CLOCK |
| @@ -1,4 +1,4 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0 */ | 1 | /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ |
| 2 | #ifndef _ASM_X86_BYTEORDER_H | 2 | #ifndef _ASM_X86_BYTEORDER_H |
| 3 | #define _ASM_X86_BYTEORDER_H | 3 | #define _ASM_X86_BYTEORDER_H |
| 4 | 4 | ||
| @@ -1,4 +1,4 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0 */ | 1 | /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ |
| 2 | #ifndef _ASM_X86_HWCAP2_H | 2 | #ifndef _ASM_X86_HWCAP2_H |
| 3 | #define _ASM_X86_HWCAP2_H | 3 | #define _ASM_X86_HWCAP2_H |
| 4 | 4 | ||
| @@ -1,4 +1,4 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0 */ | 1 | /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ |
| 2 | #ifndef _ASM_X86_SIGCONTEXT32_H | 2 | #ifndef _ASM_X86_SIGCONTEXT32_H |
| 3 | #define _ASM_X86_SIGCONTEXT32_H | 3 | #define _ASM_X86_SIGCONTEXT32_H |
| 4 | 4 | ||
| @@ -1,4 +1,4 @@ | |||
| 1 | /* SPDX-License-Identifier: GPL-2.0 */ | 1 | /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ |
| 2 | #ifndef _ASM_X86_TYPES_H | 2 | #ifndef _ASM_X86_TYPES_H |
| 3 | #define _ASM_X86_TYPES_H | 3 | #define _ASM_X86_TYPES_H |
| 4 | 4 | ||
| @@ -184,7 +184,8 @@ void __init default_setup_apic_routing(void) · 183 unmodified lines | |||
| 184 | def_to_bigsmp = 0; | 184 | def_to_bigsmp = 0; |
| 185 | break; | 185 | break; |
| 186 | } | 186 | } |
| 187 | /* If P4 and above fall through */ | 187 | /* P4 and above */ |
| 188 | /* fall through */ | ||
| 188 | case X86_VENDOR_HYGON: | 189 | case X86_VENDOR_HYGON: |
| 189 | case X86_VENDOR_AMD: | 190 | case X86_VENDOR_AMD: |
| 190 | def_to_bigsmp = 1; | 191 | def_to_bigsmp = 1; |
| @@ -34,6 +34,7 @@ · 33 unmodified lines | |||
| 34 | 34 | ||
| 35 | #include "cpu.h" | 35 | #include "cpu.h" |
| 36 | 36 | ||
| 37 | static void __init spectre_v1_select_mitigation(void); | ||
| 37 | static void __init spectre_v2_select_mitigation(void); | 38 | static void __init spectre_v2_select_mitigation(void); |
| 38 | static void __init ssb_select_mitigation(void); | 39 | static void __init ssb_select_mitigation(void); |
| 39 | static void __init l1tf_select_mitigation(void); | 40 | static void __init l1tf_select_mitigation(void); |
| @@ -98,17 +99,11 @@ void __init check_bugs(void) · 58 unmodified lines | |||
| 98 | if (boot_cpu_has(X86_FEATURE_STIBP)) | 99 | if (boot_cpu_has(X86_FEATURE_STIBP)) |
| 99 | x86_spec_ctrl_mask |= SPEC_CTRL_STIBP; | 100 | x86_spec_ctrl_mask |= SPEC_CTRL_STIBP; |
| 100 | 101 | ||
| 101 | /* Select the proper spectre mitigation before patching alternatives */ | 102 | /* Select the proper CPU mitigations before patching alternatives: */ |
| 103 | spectre_v1_select_mitigation(); | ||
| 102 | spectre_v2_select_mitigation(); | 104 | spectre_v2_select_mitigation(); |
| 103 | |||
| 104 | /* | ||
| 105 | * Select proper mitigation for any exposure to the Speculative Store | ||
| 106 | * Bypass vulnerability. | ||
| 107 | */ | ||
| 108 | ssb_select_mitigation(); | 105 | ssb_select_mitigation(); |
| 109 | |||
| 110 | l1tf_select_mitigation(); | 106 | l1tf_select_mitigation(); |
| 111 | |||
| 112 | mds_select_mitigation(); | 107 | mds_select_mitigation(); |
| 113 | 108 | ||
| 114 | arch_smt_update(); | 109 | arch_smt_update(); |
| @@ -273,6 +268,98 @@ static int __init mds_cmdline(char *str) · 158 unmodified lines | |||
| 273 | } | 268 | } |
| 274 | early_param("mds", mds_cmdline); | 269 | early_param("mds", mds_cmdline); |
| 275 | 270 | ||
| 271 | #undef pr_fmt | ||
| 272 | #define pr_fmt(fmt) "Spectre V1 : " fmt | ||
| 273 | |||
| 274 | enum spectre_v1_mitigation { | ||
| 275 | SPECTRE_V1_MITIGATION_NONE, | ||
| 276 | SPECTRE_V1_MITIGATION_AUTO, | ||
| 277 | }; | ||
| 278 | |||
| 279 | static enum spectre_v1_mitigation spectre_v1_mitigation __ro_after_init = | ||
| 280 | SPECTRE_V1_MITIGATION_AUTO; | ||
| 281 | |||
| 282 | static const char * const spectre_v1_strings[] = { | ||
| 283 | [SPECTRE_V1_MITIGATION_NONE] = "Vulnerable: __user pointer sanitization and usercopy barriers only; no swapgs barriers", | ||
| 284 | [SPECTRE_V1_MITIGATION_AUTO] = "Mitigation: usercopy/swapgs barriers and __user pointer sanitization", | ||
| 285 | }; | ||
| 286 | |||
| 287 | /* | ||
| 288 | * Does SMAP provide full mitigation against speculative kernel access to | ||
| 289 | * userspace? | ||
| 290 | */ | ||
| 291 | static bool smap_works_speculatively(void) | ||
| 292 | { | ||
| 293 | if (!boot_cpu_has(X86_FEATURE_SMAP)) | ||
| 294 | return false; | ||
| 295 | |||
| 296 | /* | ||
| 297 | * On CPUs which are vulnerable to Meltdown, SMAP does not | ||
| 298 | * prevent speculative access to user data in the L1 cache. | ||
| 299 | * Consider SMAP to be non-functional as a mitigation on these | ||
| 300 | * CPUs. | ||
| 301 | */ | ||
| 302 | if (boot_cpu_has(X86_BUG_CPU_MELTDOWN)) | ||
| 303 | return false; | ||
| 304 | |||
| 305 | return true; | ||
| 306 | } | ||
| 307 | |||
| 308 | static void __init spectre_v1_select_mitigation(void) | ||
| 309 | { | ||
| 310 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V1) || cpu_mitigations_off()) { | ||
| 311 | spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE; | ||
| 312 | return; | ||
| 313 | } | ||
| 314 | |||
| 315 | if (spectre_v1_mitigation == SPECTRE_V1_MITIGATION_AUTO) { | ||
| 316 | /* | ||
| 317 | * With Spectre v1, a user can speculatively control either | ||
| 318 | * path of a conditional swapgs with a user-controlled GS | ||
| 319 | * value. The mitigation is to add lfences to both code paths. | ||
| 320 | * | ||
| 321 | * If FSGSBASE is enabled, the user can put a kernel address in | ||
| 322 | * GS, in which case SMAP provides no protection. | ||
| 323 | * | ||
| 324 | * [ NOTE: Don't check for X86_FEATURE_FSGSBASE until the | ||
| 325 | * FSGSBASE enablement patches have been merged. ] | ||
| 326 | * | ||
| 327 | * If FSGSBASE is disabled, the user can only put a user space | ||
| 328 | * address in GS. That makes an attack harder, but still | ||
| 329 | * possible if there's no SMAP protection. | ||
| 330 | */ | ||
| 331 | if (!smap_works_speculatively()) { | ||
| 332 | /* | ||
| 333 | * Mitigation can be provided from SWAPGS itself or | ||
| 334 | * PTI as the CR3 write in the Meltdown mitigation | ||
| 335 | * is serializing. | ||
| 336 | * | ||
| 337 | * If neither is there, mitigate with an LFENCE to | ||
| 338 | * stop speculation through swapgs. | ||
| 339 | */ | ||
| 340 | if (boot_cpu_has_bug(X86_BUG_SWAPGS) && | ||
| 341 | !boot_cpu_has(X86_FEATURE_PTI)) | ||
| 342 | setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_USER); | ||
| 343 | |||
| 344 | /* | ||
| 345 | * Enable lfences in the kernel entry (non-swapgs) | ||
| 346 | * paths, to prevent user entry from speculatively | ||
| 347 | * skipping swapgs. | ||
| 348 | */ | ||
| 349 | setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_KERNEL); | ||
| 350 | } | ||
| 351 | } | ||
| 352 | |||
| 353 | pr_info("%s\n", spectre_v1_strings[spectre_v1_mitigation]); | ||
| 354 | } | ||
| 355 | |||
| 356 | static int __init nospectre_v1_cmdline(char *str) | ||
| 357 | { | ||
| 358 | spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE; | ||
| 359 | return 0; | ||
| 360 | } | ||
| 361 | early_param("nospectre_v1", nospectre_v1_cmdline); | ||
| 362 | |||
| 276 | #undef pr_fmt | 363 | #undef pr_fmt |
| 277 | #define pr_fmt(fmt) "Spectre V2 : " fmt | 364 | #define pr_fmt(fmt) "Spectre V2 : " fmt |
| 278 | 365 | ||
| @@ -1226,7 +1313,7 @@ static ssize_t l1tf_show_state(char *buf) · 947 unmodified lines | |||
| 1226 | 1313 | ||
| 1227 | static ssize_t mds_show_state(char *buf) | 1314 | static ssize_t mds_show_state(char *buf) |
| 1228 | { | 1315 | { |
| 1229 | if (!hypervisor_is_type(X86_HYPER_NATIVE)) { | 1316 | if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) { |
| 1230 | return sprintf(buf, "%s; SMT Host state unknown\n", | 1317 | return sprintf(buf, "%s; SMT Host state unknown\n", |
| 1231 | mds_strings[mds_mitigation]); | 1318 | mds_strings[mds_mitigation]); |
| 1232 | } | 1319 | } |
| @@ -1290,7 +1377,7 @@ static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr · 57 unmodified lines | |||
| 1290 | break; | 1377 | break; |
| 1291 | 1378 | ||
| 1292 | case X86_BUG_SPECTRE_V1: | 1379 | case X86_BUG_SPECTRE_V1: |
| 1293 | return sprintf(buf, "Mitigation: __user pointer sanitization\n"); | 1380 | return sprintf(buf, "%s\n", spectre_v1_strings[spectre_v1_mitigation]); |
| 1294 | 1381 | ||
| 1295 | case X86_BUG_SPECTRE_V2: | 1382 | case X86_BUG_SPECTRE_V2: |
| 1296 | return sprintf(buf, "%s%s%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled], | 1383 | return sprintf(buf, "%s%s%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled], |
| @@ -1022,6 +1022,7 @@ static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) · 1021 unmodified lines | |||
| 1022 | #define NO_L1TF BIT(3) | 1022 | #define NO_L1TF BIT(3) |
| 1023 | #define NO_MDS BIT(4) | 1023 | #define NO_MDS BIT(4) |
| 1024 | #define MSBDS_ONLY BIT(5) | 1024 | #define MSBDS_ONLY BIT(5) |
| 1025 | #define NO_SWAPGS BIT(6) | ||
| 1025 | 1026 | ||
| 1026 | #define VULNWL(_vendor, _family, _model, _whitelist) \ | 1027 | #define VULNWL(_vendor, _family, _model, _whitelist) \ |
| 1027 | { X86_VENDOR_##_vendor, _family, _model, X86_FEATURE_ANY, _whitelist } | 1028 | { X86_VENDOR_##_vendor, _family, _model, X86_FEATURE_ANY, _whitelist } |
| @@ -1048,30 +1049,38 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { · 20 unmodified lines | |||
| 1048 | VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION), | 1049 | VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION), |
| 1049 | VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION), | 1050 | VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION), |
| 1050 | 1051 | ||
| 1051 | VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY), | 1052 | VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS), |
| 1052 | VULNWL_INTEL(ATOM_SILVERMONT_X, NO_SSB | NO_L1TF | MSBDS_ONLY), | 1053 | VULNWL_INTEL(ATOM_SILVERMONT_X, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS), |
| 1053 | VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY), | 1054 | VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS), |
| 1054 | VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY), | 1055 | VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS), |
| 1055 | VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY), | 1056 | VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS), |
| 1056 | VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY), | 1057 | VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS), |
| 1057 | 1058 | ||
| 1058 | VULNWL_INTEL(CORE_YONAH, NO_SSB), | 1059 | VULNWL_INTEL(CORE_YONAH, NO_SSB), |
| 1059 | 1060 | ||
| 1060 | VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY), | 1061 | VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS), |
| 1061 | 1062 | ||
| 1062 | VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF), | 1063 | VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS), |
| 1063 | VULNWL_INTEL(ATOM_GOLDMONT_X, NO_MDS | NO_L1TF), | 1064 | VULNWL_INTEL(ATOM_GOLDMONT_X, NO_MDS | NO_L1TF | NO_SWAPGS), |
| 1064 | VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF), | 1065 | VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS), |
| 1066 | |||
| 1067 | /* | ||
| 1068 | * Technically, swapgs isn't serializing on AMD (despite it previously | ||
| 1069 | * being documented as such in the APM). But according to AMD, %gs is | ||
| 1070 | * updated non-speculatively, and the issuing of %gs-relative memory | ||
| 1071 | * operands will be blocked until the %gs update completes, which is | ||
| 1072 | * good enough for our purposes. | ||
| 1073 | */ | ||
| 1065 | 1074 | ||
| 1066 | /* AMD Family 0xf - 0x12 */ | 1075 | /* AMD Family 0xf - 0x12 */ |
| 1067 | VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS), | 1076 | VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS), |
| 1068 | VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS), | 1077 | VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS), |
| 1069 | VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS), | 1078 | VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS), |
| 1070 | VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS), | 1079 | VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS), |
| 1071 | 1080 | ||
| 1072 | /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */ | 1081 | /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */ |
| 1073 | VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS), | 1082 | VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS), |
| 1074 | VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS), | 1083 | VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS), |
| 1075 | {} | 1084 | {} |
| 1076 | }; | 1085 | }; |
| 1077 | 1086 | ||
| @@ -1108,6 +1117,9 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) · 30 unmodified lines | |||
| 1108 | setup_force_cpu_bug(X86_BUG_MSBDS_ONLY); | 1117 | setup_force_cpu_bug(X86_BUG_MSBDS_ONLY); |
| 1109 | } | 1118 | } |
| 1110 | 1119 | ||
| 1120 | if (!cpu_matches(NO_SWAPGS)) | ||
| 1121 | setup_force_cpu_bug(X86_BUG_SWAPGS); | ||
| 1122 | |||
| 1111 | if (cpu_matches(NO_MELTDOWN)) | 1123 | if (cpu_matches(NO_MELTDOWN)) |
| 1112 | return; | 1124 | return; |
| 1113 | 1125 | ||
| @@ -98,6 +98,7 @@ cyrix_get_free_region(unsigned long base, unsigned long size, int replace_reg) · 97 unmodified lines | |||
| 98 | case 7: | 98 | case 7: |
| 99 | if (size < 0x40) | 99 | if (size < 0x40) |
| 100 | break; | 100 | break; |
| 101 | /* Else, fall through */ | ||
| 101 | case 6: | 102 | case 6: |
| 102 | case 5: | 103 | case 5: |
| 103 | case 4: | 104 | case 4: |
| @@ -17,6 +17,12 @@ · 16 unmodified lines | |||
| 17 | */ | 17 | */ |
| 18 | static u32 umwait_control_cached = UMWAIT_CTRL_VAL(100000, UMWAIT_C02_ENABLE); | 18 | static u32 umwait_control_cached = UMWAIT_CTRL_VAL(100000, UMWAIT_C02_ENABLE); |
| 19 | 19 | ||
| 20 | /* | ||
| 21 | * Cache the original IA32_UMWAIT_CONTROL MSR value which is configured by | ||
| 22 | * hardware or BIOS before kernel boot. | ||
| 23 | */ | ||
| 24 | static u32 orig_umwait_control_cached __ro_after_init; | ||
| 25 | |||
| 20 | /* | 26 | /* |
| 21 | * Serialize access to umwait_control_cached and IA32_UMWAIT_CONTROL MSR in | 27 | * Serialize access to umwait_control_cached and IA32_UMWAIT_CONTROL MSR in |
| 22 | * the sysfs write functions. | 28 | * the sysfs write functions. |
| @@ -52,6 +58,23 @@ static int umwait_cpu_online(unsigned int cpu) · 29 unmodified lines | |||
| 52 | return 0; | 58 | return 0; |
| 53 | } | 59 | } |
| 54 | 60 | ||
| 61 | /* | ||
| 62 | * The CPU hotplug callback sets the control MSR to the original control | ||
| 63 | * value. | ||
| 64 | */ | ||
| 65 | static int umwait_cpu_offline(unsigned int cpu) | ||
| 66 | { | ||
| 67 | /* | ||
| 68 | * This code is protected by the CPU hotplug already and | ||
| 69 | * orig_umwait_control_cached is never changed after it caches | ||
| 70 | * the original control MSR value in umwait_init(). So there | ||
| 71 | * is no race condition here. | ||
| 72 | */ | ||
| 73 | wrmsr(MSR_IA32_UMWAIT_CONTROL, orig_umwait_control_cached, 0); | ||
| 74 | |||
| 75 | return 0; | ||
| 76 | } | ||
| 77 | |||
| 55 | /* | 78 | /* |
| 56 | * On resume, restore IA32_UMWAIT_CONTROL MSR on the boot processor which | 79 | * On resume, restore IA32_UMWAIT_CONTROL MSR on the boot processor which |
| 57 | * is the only active CPU at this time. The MSR is set up on the APs via the | 80 | * is the only active CPU at this time. The MSR is set up on the APs via the |
| @@ -185,8 +208,22 @@ static int __init umwait_init(void) · 127 unmodified lines | |||
| 185 | if (!boot_cpu_has(X86_FEATURE_WAITPKG)) | 208 | if (!boot_cpu_has(X86_FEATURE_WAITPKG)) |
| 186 | return -ENODEV; | 209 | return -ENODEV; |
| 187 | 210 | ||
| 211 | /* | ||
| 212 | * Cache the original control MSR value before the control MSR is | ||
| 213 | * changed. This is the only place where orig_umwait_control_cached | ||
| 214 | * is modified. | ||
| 215 | */ | ||
| 216 | rdmsrl(MSR_IA32_UMWAIT_CONTROL, orig_umwait_control_cached); | ||
| 217 | |||
| 188 | ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "umwait:online", | 218 | ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "umwait:online", |
| 189 | umwait_cpu_online, NULL); | 219 | umwait_cpu_online, umwait_cpu_offline); |
| 220 | if (ret < 0) { | ||
| 221 | /* | ||
| 222 | * On failure, the control MSR on all CPUs has the | ||
| 223 | * original control value. | ||
| 224 | */ | ||
| 225 | return ret; | ||
| 226 | } | ||
| 190 | 227 | ||
| 191 | register_syscore_ops(&umwait_syscore_ops); | 228 | register_syscore_ops(&umwait_syscore_ops); |
| 192 | 229 | ||
| @@ -193,10 +193,10 @@ ENTRY(secondary_startup_64) · 192 unmodified lines | |||
| 193 | 193 | ||
| 194 | /* Set up %gs. | 194 | /* Set up %gs. |
| 195 | * | 195 | * |
| 196 | * The base of %gs always points to the bottom of the irqstack | 196 | * The base of %gs always points to fixed_percpu_data. If the |
| 197 | * union. If the stack protector canary is enabled, it is | 197 | * stack protector canary is enabled, it is located at %gs:40. |
| 198 | * located at %gs:40. Note that, on SMP, the boot cpu uses | 198 | * Note that, on SMP, the boot cpu uses init data section until |
| 199 | * init data section till per cpu areas are set up. | 199 | * the per cpu areas are set up. |
| 200 | */ | 200 | */ |
| 201 | movl $MSR_GS_BASE,%ecx | 201 | movl $MSR_GS_BASE,%ecx |
| 202 | movl initial_gs(%rip),%eax | 202 | movl initial_gs(%rip),%eax |
| @@ -827,10 +827,6 @@ int __init hpet_enable(void) · 826 unmodified lines | |||
| 827 | if (!hpet_cfg_working()) | 827 | if (!hpet_cfg_working()) |
| 828 | goto out_nohpet; | 828 | goto out_nohpet; |
| 829 | 829 | ||
| 830 | /* Validate that the counter is counting */ | ||
| 831 | if (!hpet_counting()) | ||
| 832 | goto out_nohpet; | ||
| 833 | |||
| 834 | /* | 830 | /* |
| 835 | * Read the period and check for a sane value: | 831 | * Read the period and check for a sane value: |
| 836 | */ | 832 | */ |
| @@ -896,6 +892,14 @@ int __init hpet_enable(void) · 59 unmodified lines | |||
| 896 | } | 892 | } |
| 897 | hpet_print_config(); | 893 | hpet_print_config(); |
| 898 | 894 | ||
| 895 | /* | ||
| 896 | * Validate that the counter is counting. This needs to be done | ||
| 897 | * after sanitizing the config registers to properly deal with | ||
| 898 | * force enabled HPETs. | ||
| 899 | */ | ||
| 900 | if (!hpet_counting()) | ||
| 901 | goto out_nohpet; | ||
| 902 | |||
| 899 | clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq); | 903 | clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq); |
| 900 | 904 | ||
| 901 | if (id & HPET_ID_LEGSUP) { | 905 | if (id & HPET_ID_LEGSUP) { |
| @@ -308,9 +308,6 @@ static notrace void kvm_guest_apic_eoi_write(u32 reg, u32 val) · 307 unmodified lines | |||
| 308 | 308 | ||
| 309 | static void kvm_guest_cpu_init(void) | 309 | static void kvm_guest_cpu_init(void) |
| 310 | { | 310 | { |
| 311 | if (!kvm_para_available()) | ||
| 312 | return; | ||
| 313 | |||
| 314 | if (kvm_para_has_feature(KVM_FEATURE_ASYNC_PF) && kvmapf) { | 311 | if (kvm_para_has_feature(KVM_FEATURE_ASYNC_PF) && kvmapf) { |
| 315 | u64 pa = slow_virt_to_phys(this_cpu_ptr(&apf_reason)); | 312 | u64 pa = slow_virt_to_phys(this_cpu_ptr(&apf_reason)); |
| 316 | 313 | ||
| @@ -625,9 +622,6 @@ static void __init kvm_guest_init(void) · 308 unmodified lines | |||
| 625 | { | 622 | { |
| 626 | int i; | 623 | int i; |
| 627 | 624 | ||
| 628 | if (!kvm_para_available()) | ||
| 629 | return; | ||
| 630 | |||
| 631 | paravirt_ops_setup(); | 625 | paravirt_ops_setup(); |
| 632 | register_reboot_notifier(&kvm_pv_reboot_nb); | 626 | register_reboot_notifier(&kvm_pv_reboot_nb); |
| 633 | for (i = 0; i < KVM_TASK_SLEEP_HASHSIZE; i++) | 627 | for (i = 0; i < KVM_TASK_SLEEP_HASHSIZE; i++) |
| @@ -848,8 +842,6 @@ asm( · 214 unmodified lines | |||
| 848 | */ | 842 | */ |
| 849 | void __init kvm_spinlock_init(void) | 843 | void __init kvm_spinlock_init(void) |
| 850 | { | 844 | { |
| 851 | if (!kvm_para_available()) | ||
| 852 | return; | ||
| 853 | /* Does host kernel support KVM_FEATURE_PV_UNHALT? */ | 845 | /* Does host kernel support KVM_FEATURE_PV_UNHALT? */ |
| 854 | if (!kvm_para_has_feature(KVM_FEATURE_PV_UNHALT)) | 846 | if (!kvm_para_has_feature(KVM_FEATURE_PV_UNHALT)) |
| 855 | return; | 847 | return; |
| @@ -201,6 +201,7 @@ static int set_segment_reg(struct task_struct *task, · 200 unmodified lines | |||
| 201 | case offsetof(struct user_regs_struct, ss): | 201 | case offsetof(struct user_regs_struct, ss): |
| 202 | if (unlikely(value == 0)) | 202 | if (unlikely(value == 0)) |
| 203 | return -EIO; | 203 | return -EIO; |
| 204 | /* Else, fall through */ | ||
| 204 | 205 | ||
| 205 | default: | 206 | default: |
| 206 | *pt_regs_access(task_pt_regs(task), offset) = value; | 207 | *pt_regs_access(task_pt_regs(task), offset) = value; |
| @@ -100,7 +100,7 @@ copy_stack_frame(const void __user *fp, struct stack_frame_user *frame) · 99 unmodified lines | |||
| 100 | { | 100 | { |
| 101 | int ret; | 101 | int ret; |
| 102 | 102 | ||
| 103 | if (!access_ok(fp, sizeof(*frame))) | 103 | if (__range_not_ok(fp, sizeof(*frame), TASK_SIZE)) |
| 104 | return 0; | 104 | return 0; |
| 105 | 105 | ||
| 106 | ret = 1; | 106 | ret = 1; |
| @@ -230,9 +230,55 @@ static const struct dmi_system_id efifb_dmi_system_table[] __initconst = { · 229 unmodified lines | |||
| 230 | {}, | 230 | {}, |
| 231 | }; | 231 | }; |
| 232 | 232 | ||
| 233 | /* | ||
| 234 | * Some devices have a portrait LCD but advertise a landscape resolution (and | ||
| 235 | * pitch). We simply swap width and height for these devices so that we can | ||
| 236 | * correctly deal with some of them coming with multiple resolutions. | ||
| 237 | */ | ||
| 238 | static const struct dmi_system_id efifb_dmi_swap_width_height[] __initconst = { | ||
| 239 | { | ||
| 240 | /* | ||
| 241 | * Lenovo MIIX310-10ICR, only some batches have the troublesome | ||
| 242 | * 800x1280 portrait screen. Luckily the portrait version has | ||
| 243 | * its own BIOS version, so we match on that. | ||
| 244 | */ | ||
| 245 | .matches = { | ||
| 246 | DMI_EXACT_MATCH(DMI_SYS_VENDOR, "LENOVO"), | ||
| 247 | DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, "MIIX 310-10ICR"), | ||
| 248 | DMI_EXACT_MATCH(DMI_BIOS_VERSION, "1HCN44WW"), | ||
| 249 | }, | ||
| 250 | }, | ||
| 251 | { | ||
| 252 | /* Lenovo MIIX 320-10ICR with 800x1280 portrait screen */ | ||
| 253 | .matches = { | ||
| 254 | DMI_EXACT_MATCH(DMI_SYS_VENDOR, "LENOVO"), | ||
| 255 | DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, | ||
| 256 | "Lenovo MIIX 320-10ICR"), | ||
| 257 | }, | ||
| 258 | }, | ||
| 259 | { | ||
| 260 | /* Lenovo D330 with 800x1280 or 1200x1920 portrait screen */ | ||
| 261 | .matches = { | ||
| 262 | DMI_EXACT_MATCH(DMI_SYS_VENDOR, "LENOVO"), | ||
| 263 | DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, | ||
| 264 | "Lenovo ideapad D330-10IGM"), | ||
| 265 | }, | ||
| 266 | }, | ||
| 267 | {}, | ||
| 268 | }; | ||
| 269 | |||
| 233 | __init void sysfb_apply_efi_quirks(void) | 270 | __init void sysfb_apply_efi_quirks(void) |
| 234 | { | 271 | { |
| 235 | if (screen_info.orig_video_isVGA != VIDEO_TYPE_EFI || | 272 | if (screen_info.orig_video_isVGA != VIDEO_TYPE_EFI || |
| 236 | !(screen_info.capabilities & VIDEO_CAPABILITY_SKIP_QUIRKS)) | 273 | !(screen_info.capabilities & VIDEO_CAPABILITY_SKIP_QUIRKS)) |
| 237 | dmi_check_system(efifb_dmi_system_table); | 274 | dmi_check_system(efifb_dmi_system_table); |
| 275 | |||
| 276 | if (screen_info.orig_video_isVGA == VIDEO_TYPE_EFI && | ||
| 277 | dmi_check_system(efifb_dmi_swap_width_height)) { | ||
| 278 | u16 temp = screen_info.lfb_width; | ||
| 279 | |||
| 280 | screen_info.lfb_width = screen_info.lfb_height; | ||
| 281 | screen_info.lfb_height = temp; | ||
| 282 | screen_info.lfb_linelength = 4 * screen_info.lfb_width; | ||
| 283 | } | ||
| 238 | } | 284 | } |
| @@ -8,11 +8,6 @@ · 7 unmodified lines | |||
| 8 | #include <linux/debugfs.h> | 8 | #include <linux/debugfs.h> |
| 9 | #include "lapic.h" | 9 | #include "lapic.h" |
| 10 | 10 | ||
| 11 | bool kvm_arch_has_vcpu_debugfs(void) | ||
| 12 | { | ||
| 13 | return true; | ||
| 14 | } | ||
| 15 | |||
| 16 | static int vcpu_get_timer_advance_ns(void *data, u64 *val) | 11 | static int vcpu_get_timer_advance_ns(void *data, u64 *val) |
| 17 | { | 12 | { |
| 18 | struct kvm_vcpu *vcpu = (struct kvm_vcpu *) data; | 13 | struct kvm_vcpu *vcpu = (struct kvm_vcpu *) data; |
| @@ -48,37 +43,22 @@ static int vcpu_get_tsc_scaling_frac_bits(void *data, u64 *val) · 29 unmodified lines | |||
| 48 | 43 | ||
| 49 | DEFINE_SIMPLE_ATTRIBUTE(vcpu_tsc_scaling_frac_fops, vcpu_get_tsc_scaling_frac_bits, NULL, "%llu\n"); | 44 | DEFINE_SIMPLE_ATTRIBUTE(vcpu_tsc_scaling_frac_fops, vcpu_get_tsc_scaling_frac_bits, NULL, "%llu\n"); |
| 50 | 45 | ||
| 51 | int kvm_arch_create_vcpu_debugfs(struct kvm_vcpu *vcpu) | 46 | void kvm_arch_create_vcpu_debugfs(struct kvm_vcpu *vcpu) |
| 52 | { | 47 | { |
| 53 | struct dentry *ret; | 48 | debugfs_create_file("tsc-offset", 0444, vcpu->debugfs_dentry, vcpu, |
| 54 | 49 | &vcpu_tsc_offset_fops); | |
| 55 | ret = debugfs_create_file("tsc-offset", 0444, | ||
| 56 | vcpu->debugfs_dentry, | ||
| 57 | vcpu, &vcpu_tsc_offset_fops); | ||
| 58 | if (!ret) | ||
| 59 | return -ENOMEM; | ||
| 60 | 50 | ||
| 61 | if (lapic_in_kernel(vcpu)) { | 51 | if (lapic_in_kernel(vcpu)) |
| 62 | ret = debugfs_create_file("lapic_timer_advance_ns", 0444, | 52 | debugfs_create_file("lapic_timer_advance_ns", 0444, |
| 63 | vcpu->debugfs_dentry, | 53 | vcpu->debugfs_dentry, vcpu, |
| 64 | vcpu, &vcpu_timer_advance_ns_fops); | 54 | &vcpu_timer_advance_ns_fops); |
| 65 | if (!ret) | ||
| 66 | return -ENOMEM; | ||
| 67 | } | ||
| 68 | 55 | ||
| 69 | if (kvm_has_tsc_control) { | 56 | if (kvm_has_tsc_control) { |
| 70 | ret = debugfs_create_file("tsc-scaling-ratio", 0444, | 57 | debugfs_create_file("tsc-scaling-ratio", 0444, |
| 71 | vcpu->debugfs_dentry, | 58 | vcpu->debugfs_dentry, vcpu, |
| 72 | vcpu, &vcpu_tsc_scaling_fops); | 59 | &vcpu_tsc_scaling_fops); |
| 73 | if (!ret) | 60 | debugfs_create_file("tsc-scaling-ratio-frac-bits", 0444, |
| 74 | return -ENOMEM; | 61 | vcpu->debugfs_dentry, vcpu, |
| 75 | ret = debugfs_create_file("tsc-scaling-ratio-frac-bits", 0444, | 62 | &vcpu_tsc_scaling_frac_fops); |
| 76 | vcpu->debugfs_dentry, | ||
| 77 | vcpu, &vcpu_tsc_scaling_frac_fops); | ||
| 78 | if (!ret) | ||
| 79 | return -ENOMEM; | ||
| 80 | |||
| 81 | } | 63 | } |
| 82 | |||
| 83 | return 0; | ||
| 84 | } | 64 | } |
| @@ -1548,7 +1548,6 @@ static void kvm_apic_inject_pending_timer_irqs(struct kvm_lapic *apic) · 1547 unmodified lines | |||
| 1548 | static void apic_timer_expired(struct kvm_lapic *apic) | 1548 | static void apic_timer_expired(struct kvm_lapic *apic) |
| 1549 | { | 1549 | { |
| 1550 | struct kvm_vcpu *vcpu = apic->vcpu; | 1550 | struct kvm_vcpu *vcpu = apic->vcpu; |
| 1551 | struct swait_queue_head *q = &vcpu->wq; | ||
| 1552 | struct kvm_timer *ktimer = &apic->lapic_timer; | 1551 | struct kvm_timer *ktimer = &apic->lapic_timer; |
| 1553 | 1552 | ||
| 1554 | if (atomic_read(&apic->lapic_timer.pending)) | 1553 | if (atomic_read(&apic->lapic_timer.pending)) |
| @@ -1566,13 +1565,6 @@ static void apic_timer_expired(struct kvm_lapic *apic) · 11 unmodified lines | |||
| 1566 | 1565 | ||
| 1567 | atomic_inc(&apic->lapic_timer.pending); | 1566 | atomic_inc(&apic->lapic_timer.pending); |
| 1568 | kvm_set_pending_timer(vcpu); | 1567 | kvm_set_pending_timer(vcpu); |
| 1569 | |||
| 1570 | /* | ||
| 1571 | * For x86, the atomic_inc() is serialized, thus | ||
| 1572 | * using swait_active() is safe. | ||
| 1573 | */ | ||
| 1574 | if (swait_active(q)) | ||
| 1575 | swake_up_one(q); | ||
| 1576 | } | 1568 | } |
| 1577 | 1569 | ||
| 1578 | static void start_sw_tscdeadline(struct kvm_lapic *apic) | 1570 | static void start_sw_tscdeadline(struct kvm_lapic *apic) |
| @@ -3466,7 +3466,7 @@ static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level, · 3465 unmodified lines | |||
| 3466 | /* | 3466 | /* |
| 3467 | * Currently, fast page fault only works for direct mapping | 3467 | * Currently, fast page fault only works for direct mapping |
| 3468 | * since the gfn is not stable for indirect shadow page. See | 3468 | * since the gfn is not stable for indirect shadow page. See |
| 3469 | * Documentation/virtual/kvm/locking.txt to get more detail. | 3469 | * Documentation/virt/kvm/locking.txt to get more detail. |
| 3470 | */ | 3470 | */ |
| 3471 | fault_handled = fast_pf_fix_direct_spte(vcpu, sp, | 3471 | fault_handled = fast_pf_fix_direct_spte(vcpu, sp, |
| 3472 | iterator.sptep, spte, | 3472 | iterator.sptep, spte, |
| @@ -2143,12 +2143,20 @@ static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) · 2142 unmodified lines | |||
| 2143 | goto out; | 2143 | goto out; |
| 2144 | } | 2144 | } |
| 2145 | 2145 | ||
| 2146 | svm->vcpu.arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache, | ||
| 2147 | GFP_KERNEL_ACCOUNT); | ||
| 2148 | if (!svm->vcpu.arch.user_fpu) { | ||
| 2149 | printk(KERN_ERR "kvm: failed to allocate kvm userspace's fpu\n"); | ||
| 2150 | err = -ENOMEM; | ||
| 2151 | goto free_partial_svm; | ||
| 2152 | } | ||
| 2153 | |||
| 2146 | svm->vcpu.arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache, | 2154 | svm->vcpu.arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache, |
| 2147 | GFP_KERNEL_ACCOUNT); | 2155 | GFP_KERNEL_ACCOUNT); |
| 2148 | if (!svm->vcpu.arch.guest_fpu) { | 2156 | if (!svm->vcpu.arch.guest_fpu) { |
| 2149 | printk(KERN_ERR "kvm: failed to allocate vcpu's fpu\n"); | 2157 | printk(KERN_ERR "kvm: failed to allocate vcpu's fpu\n"); |
| 2150 | err = -ENOMEM; | 2158 | err = -ENOMEM; |
| 2151 | goto free_partial_svm; | 2159 | goto free_user_fpu; |
| 2152 | } | 2160 | } |
| 2153 | 2161 | ||
| 2154 | err = kvm_vcpu_init(&svm->vcpu, kvm, id); | 2162 | err = kvm_vcpu_init(&svm->vcpu, kvm, id); |
| @@ -2211,6 +2219,8 @@ uninit: · 56 unmodified lines | |||
| 2211 | kvm_vcpu_uninit(&svm->vcpu); | 2219 | kvm_vcpu_uninit(&svm->vcpu); |
| 2212 | free_svm: | 2220 | free_svm: |
| 2213 | kmem_cache_free(x86_fpu_cache, svm->vcpu.arch.guest_fpu); | 2221 | kmem_cache_free(x86_fpu_cache, svm->vcpu.arch.guest_fpu); |
| 2222 | free_user_fpu: | ||
| 2223 | kmem_cache_free(x86_fpu_cache, svm->vcpu.arch.user_fpu); | ||
| 2214 | free_partial_svm: | 2224 | free_partial_svm: |
| 2215 | kmem_cache_free(kvm_vcpu_cache, svm); | 2225 | kmem_cache_free(kvm_vcpu_cache, svm); |
| 2216 | out: | 2226 | out: |
| @@ -2241,6 +2251,7 @@ static void svm_free_vcpu(struct kvm_vcpu *vcpu) · 24 unmodified lines | |||
| 2241 | __free_page(virt_to_page(svm->nested.hsave)); | 2251 | __free_page(virt_to_page(svm->nested.hsave)); |
| 2242 | __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER); | 2252 | __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER); |
| 2243 | kvm_vcpu_uninit(vcpu); | 2253 | kvm_vcpu_uninit(vcpu); |
| 2254 | kmem_cache_free(x86_fpu_cache, svm->vcpu.arch.user_fpu); | ||
| 2244 | kmem_cache_free(x86_fpu_cache, svm->vcpu.arch.guest_fpu); | 2255 | kmem_cache_free(x86_fpu_cache, svm->vcpu.arch.guest_fpu); |
| 2245 | kmem_cache_free(kvm_vcpu_cache, svm); | 2256 | kmem_cache_free(kvm_vcpu_cache, svm); |
| 2246 | } | 2257 | } |
| @@ -5179,6 +5190,11 @@ static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec) · 2932 unmodified lines | |||
| 5179 | kvm_vcpu_wake_up(vcpu); | 5190 | kvm_vcpu_wake_up(vcpu); |
| 5180 | } | 5191 | } |
| 5181 | 5192 | ||
| 5193 | static bool svm_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu) | ||
| 5194 | { | ||
| 5195 | return false; | ||
| 5196 | } | ||
| 5197 | |||
| 5182 | static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi) | 5198 | static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi) |
| 5183 | { | 5199 | { |
| 5184 | unsigned long flags; | 5200 | unsigned long flags; |
| @@ -7303,6 +7319,7 @@ static struct kvm_x86_ops svm_x86_ops __ro_after_init = { · 2118 unmodified lines | |||
| 7303 | 7319 | ||
| 7304 | .pmu_ops = &amd_pmu_ops, | 7320 | .pmu_ops = &amd_pmu_ops, |
| 7305 | .deliver_posted_interrupt = svm_deliver_avic_intr, | 7321 | .deliver_posted_interrupt = svm_deliver_avic_intr, |
| 7322 | .dy_apicv_has_pending_interrupt = svm_dy_apicv_has_pending_interrupt, | ||
| 7306 | .update_pi_irte = svm_update_pi_irte, | 7323 | .update_pi_irte = svm_update_pi_irte, |
| 7307 | .setup_mce = svm_setup_mce, | 7324 | .setup_mce = svm_setup_mce, |
| 7308 | 7325 | ||
| @@ -220,6 +220,8 @@ static void free_nested(struct kvm_vcpu *vcpu) · 219 unmodified lines | |||
| 220 | if (!vmx->nested.vmxon && !vmx->nested.smm.vmxon) | 220 | if (!vmx->nested.vmxon && !vmx->nested.smm.vmxon) |
| 221 | return; | 221 | return; |
| 222 | 222 | ||
| 223 | kvm_clear_request(KVM_REQ_GET_VMCS12_PAGES, vcpu); | ||
| 224 | |||
| 223 | vmx->nested.vmxon = false; | 225 | vmx->nested.vmxon = false; |
| 224 | vmx->nested.smm.vmxon = false; | 226 | vmx->nested.smm.vmxon = false; |
| 225 | free_vpid(vmx->nested.vpid02); | 227 | free_vpid(vmx->nested.vpid02); |
| @@ -232,7 +234,9 @@ static void free_nested(struct kvm_vcpu *vcpu) · 6 unmodified lines | |||
| 232 | vmx->vmcs01.shadow_vmcs = NULL; | 234 | vmx->vmcs01.shadow_vmcs = NULL; |
| 233 | } | 235 | } |
| 234 | kfree(vmx->nested.cached_vmcs12); | 236 | kfree(vmx->nested.cached_vmcs12); |
| 237 | vmx->nested.cached_vmcs12 = NULL; | ||
| 235 | kfree(vmx->nested.cached_shadow_vmcs12); | 238 | kfree(vmx->nested.cached_shadow_vmcs12); |
| 239 | vmx->nested.cached_shadow_vmcs12 = NULL; | ||
| 236 | /* Unpin physical memory we referred to in the vmcs02 */ | 240 | /* Unpin physical memory we referred to in the vmcs02 */ |
| 237 | if (vmx->nested.apic_access_page) { | 241 | if (vmx->nested.apic_access_page) { |
| 238 | kvm_release_page_dirty(vmx->nested.apic_access_page); | 242 | kvm_release_page_dirty(vmx->nested.apic_access_page); |
| @@ -6117,6 +6117,11 @@ static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu) · 6116 unmodified lines | |||
| 6117 | return max_irr; | 6117 | return max_irr; |
| 6118 | } | 6118 | } |
| 6119 | 6119 | ||
| 6120 | static bool vmx_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu) | ||
| 6121 | { | ||
| 6122 | return pi_test_on(vcpu_to_pi_desc(vcpu)); | ||
| 6123 | } | ||
| 6124 | |||
| 6120 | static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap) | 6125 | static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap) |
| 6121 | { | 6126 | { |
| 6122 | if (!kvm_vcpu_apicv_active(vcpu)) | 6127 | if (!kvm_vcpu_apicv_active(vcpu)) |
| @@ -6598,6 +6603,7 @@ static void vmx_free_vcpu(struct kvm_vcpu *vcpu) · 475 unmodified lines | |||
| 6598 | free_loaded_vmcs(vmx->loaded_vmcs); | 6603 | free_loaded_vmcs(vmx->loaded_vmcs); |
| 6599 | kfree(vmx->guest_msrs); | 6604 | kfree(vmx->guest_msrs); |
| 6600 | kvm_vcpu_uninit(vcpu); | 6605 | kvm_vcpu_uninit(vcpu); |
| 6606 | kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.user_fpu); | ||
| 6601 | kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu); | 6607 | kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu); |
| 6602 | kmem_cache_free(kvm_vcpu_cache, vmx); | 6608 | kmem_cache_free(kvm_vcpu_cache, vmx); |
| 6603 | } | 6609 | } |
| @@ -6613,12 +6619,20 @@ static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id) · 9 unmodified lines | |||
| 6613 | if (!vmx) | 6619 | if (!vmx) |
| 6614 | return ERR_PTR(-ENOMEM); | 6620 | return ERR_PTR(-ENOMEM); |
| 6615 | 6621 | ||
| 6622 | vmx->vcpu.arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache, | ||
| 6623 | GFP_KERNEL_ACCOUNT); | ||
| 6624 | if (!vmx->vcpu.arch.user_fpu) { | ||
| 6625 | printk(KERN_ERR "kvm: failed to allocate kvm userspace's fpu\n"); | ||
| 6626 | err = -ENOMEM; | ||
| 6627 | goto free_partial_vcpu; | ||
| 6628 | } | ||
| 6629 | |||
| 6616 | vmx->vcpu.arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache, | 6630 | vmx->vcpu.arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache, |
| 6617 | GFP_KERNEL_ACCOUNT); | 6631 | GFP_KERNEL_ACCOUNT); |
| 6618 | if (!vmx->vcpu.arch.guest_fpu) { | 6632 | if (!vmx->vcpu.arch.guest_fpu) { |
| 6619 | printk(KERN_ERR "kvm: failed to allocate vcpu's fpu\n"); | 6633 | printk(KERN_ERR "kvm: failed to allocate vcpu's fpu\n"); |
| 6620 | err = -ENOMEM; | 6634 | err = -ENOMEM; |
| 6621 | goto free_partial_vcpu; | 6635 | goto free_user_fpu; |
| 6622 | } | 6636 | } |
| 6623 | 6637 | ||
| 6624 | vmx->vpid = allocate_vpid(); | 6638 | vmx->vpid = allocate_vpid(); |
| @@ -6721,6 +6735,8 @@ uninit_vcpu: · 96 unmodified lines | |||
| 6721 | free_vcpu: | 6735 | free_vcpu: |
| 6722 | free_vpid(vmx->vpid); | 6736 | free_vpid(vmx->vpid); |
| 6723 | kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu); | 6737 | kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu); |
| 6738 | free_user_fpu: | ||
| 6739 | kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.user_fpu); | ||
| 6724 | free_partial_vcpu: | 6740 | free_partial_vcpu: |
| 6725 | kmem_cache_free(kvm_vcpu_cache, vmx); | 6741 | kmem_cache_free(kvm_vcpu_cache, vmx); |
| 6726 | return ERR_PTR(err); | 6742 | return ERR_PTR(err); |
| @@ -7715,6 +7731,7 @@ static struct kvm_x86_ops vmx_x86_ops __ro_after_init = { · 988 unmodified lines | |||
| 7715 | .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt, | 7731 | .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt, |
| 7716 | .sync_pir_to_irr = vmx_sync_pir_to_irr, | 7732 | .sync_pir_to_irr = vmx_sync_pir_to_irr, |
| 7717 | .deliver_posted_interrupt = vmx_deliver_posted_interrupt, | 7733 | .deliver_posted_interrupt = vmx_deliver_posted_interrupt, |
| 7734 | .dy_apicv_has_pending_interrupt = vmx_dy_apicv_has_pending_interrupt, | ||
| 7718 | 7735 | ||
| 7719 | .set_tss_addr = vmx_set_tss_addr, | 7736 | .set_tss_addr = vmx_set_tss_addr, |
| 7720 | .set_identity_map_addr = vmx_set_identity_map_addr, | 7737 | .set_identity_map_addr = vmx_set_identity_map_addr, |
| @@ -3306,6 +3306,10 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) · 3305 unmodified lines | |||
| 3306 | 3306 | ||
| 3307 | kvm_x86_ops->vcpu_load(vcpu, cpu); | 3307 | kvm_x86_ops->vcpu_load(vcpu, cpu); |
| 3308 | 3308 | ||
| 3309 | fpregs_assert_state_consistent(); | ||
| 3310 | if (test_thread_flag(TIF_NEED_FPU_LOAD)) | ||
| 3311 | switch_fpu_return(); | ||
| 3312 | |||
| 3309 | /* Apply any externally detected TSC adjustments (due to suspend) */ | 3313 | /* Apply any externally detected TSC adjustments (due to suspend) */ |
| 3310 | if (unlikely(vcpu->arch.tsc_offset_adjustment)) { | 3314 | if (unlikely(vcpu->arch.tsc_offset_adjustment)) { |
| 3311 | adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); | 3315 | adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); |
| @@ -7202,7 +7206,7 @@ static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id) · 3890 unmodified lines | |||
| 7202 | 7206 | ||
| 7203 | rcu_read_unlock(); | 7207 | rcu_read_unlock(); |
| 7204 | 7208 | ||
| 7205 | if (target) | 7209 | if (target && READ_ONCE(target->ready)) |
| 7206 | kvm_vcpu_yield_to(target); | 7210 | kvm_vcpu_yield_to(target); |
| 7207 | } | 7211 | } |
| 7208 | 7212 | ||
| @@ -7242,6 +7246,7 @@ int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) · 33 unmodified lines | |||
| 7242 | break; | 7246 | break; |
| 7243 | case KVM_HC_KICK_CPU: | 7247 | case KVM_HC_KICK_CPU: |
| 7244 | kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); | 7248 | kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1); |
| 7249 | kvm_sched_yield(vcpu->kvm, a1); | ||
| 7245 | ret = 0; | 7250 | ret = 0; |
| 7246 | break; | 7251 | break; |
| 7247 | #ifdef CONFIG_X86_64 | 7252 | #ifdef CONFIG_X86_64 |
| @@ -7990,9 +7995,8 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu) · 742 unmodified lines | |||
| 7990 | trace_kvm_entry(vcpu->vcpu_id); | 7995 | trace_kvm_entry(vcpu->vcpu_id); |
| 7991 | guest_enter_irqoff(); | 7996 | guest_enter_irqoff(); |
| 7992 | 7997 | ||
| 7993 | fpregs_assert_state_consistent(); | 7998 | /* The preempt notifier should have taken care of the FPU already. */ |
| 7994 | if (test_thread_flag(TIF_NEED_FPU_LOAD)) | 7999 | WARN_ON_ONCE(test_thread_flag(TIF_NEED_FPU_LOAD)); |
| 7995 | switch_fpu_return(); | ||
| 7996 | 8000 | ||
| 7997 | if (unlikely(vcpu->arch.switch_db_regs)) { | 8001 | if (unlikely(vcpu->arch.switch_db_regs)) { |
| 7998 | set_debugreg(0, 7); | 8002 | set_debugreg(0, 7); |
| @@ -8270,7 +8274,7 @@ static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) · 271 unmodified lines | |||
| 8270 | { | 8274 | { |
| 8271 | fpregs_lock(); | 8275 | fpregs_lock(); |
| 8272 | 8276 | ||
| 8273 | copy_fpregs_to_fpstate(¤t->thread.fpu); | 8277 | copy_fpregs_to_fpstate(vcpu->arch.user_fpu); |
| 8274 | /* PKRU is separately restored in kvm_x86_ops->run. */ | 8278 | /* PKRU is separately restored in kvm_x86_ops->run. */ |
| 8275 | __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state, | 8279 | __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state, |
| 8276 | ~XFEATURE_MASK_PKRU); | 8280 | ~XFEATURE_MASK_PKRU); |
| @@ -8287,7 +8291,7 @@ static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) · 10 unmodified lines | |||
| 8287 | fpregs_lock(); | 8291 | fpregs_lock(); |
| 8288 | 8292 | ||
| 8289 | copy_fpregs_to_fpstate(vcpu->arch.guest_fpu); | 8293 | copy_fpregs_to_fpstate(vcpu->arch.guest_fpu); |
| 8290 | copy_kernel_to_fpregs(¤t->thread.fpu.state); | 8294 | copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state); |
| 8291 | 8295 | ||
| 8292 | fpregs_mark_activate(); | 8296 | fpregs_mark_activate(); |
| 8293 | fpregs_unlock(); | 8297 | fpregs_unlock(); |
| @@ -9694,6 +9698,22 @@ int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) · 1400 unmodified lines | |||
| 9694 | return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); | 9698 | return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); |
| 9695 | } | 9699 | } |
| 9696 | 9700 | ||
| 9701 | bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu) | ||
| 9702 | { | ||
| 9703 | if (READ_ONCE(vcpu->arch.pv.pv_unhalted)) | ||
| 9704 | return true; | ||
| 9705 | |||
| 9706 | if (kvm_test_request(KVM_REQ_NMI, vcpu) || | ||
| 9707 | kvm_test_request(KVM_REQ_SMI, vcpu) || | ||
| 9708 | kvm_test_request(KVM_REQ_EVENT, vcpu)) | ||
| 9709 | return true; | ||
| 9710 | |||
| 9711 | if (vcpu->arch.apicv_active && kvm_x86_ops->dy_apicv_has_pending_interrupt(vcpu)) | ||
| 9712 | return true; | ||
| 9713 | |||
| 9714 | return false; | ||
| 9715 | } | ||
| 9716 | |||
| 9697 | bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) | 9717 | bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) |
| 9698 | { | 9718 | { |
| 9699 | return vcpu->arch.preempted_in_kernel; | 9719 | return vcpu->arch.preempted_in_kernel; |
| @@ -1,6 +1,7 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0-only | 1 | // SPDX-License-Identifier: GPL-2.0-only |
| 2 | #include <linux/types.h> | 2 | #include <linux/types.h> |
| 3 | #include <linux/export.h> | 3 | #include <linux/export.h> |
| 4 | #include <asm/cpu.h> | ||
| 4 | 5 | ||
| 5 | unsigned int x86_family(unsigned int sig) | 6 | unsigned int x86_family(unsigned int sig) |
| 6 | { | 7 | { |
| @@ -178,13 +178,15 @@ void FPU_printall(void) · 177 unmodified lines | |||
| 178 | for (i = 0; i < 8; i++) { | 178 | for (i = 0; i < 8; i++) { |
| 179 | FPU_REG *r = &st(i); | 179 | FPU_REG *r = &st(i); |
| 180 | u_char tagi = FPU_gettagi(i); | 180 | u_char tagi = FPU_gettagi(i); |
| 181 | |||
| 181 | switch (tagi) { | 182 | switch (tagi) { |
| 182 | case TAG_Empty: | 183 | case TAG_Empty: |
| 183 | continue; | 184 | continue; |
| 184 | break; | ||
| 185 | case TAG_Zero: | 185 | case TAG_Zero: |
| 186 | case TAG_Special: | 186 | case TAG_Special: |
| 187 | /* Update tagi for the printk below */ | ||
| 187 | tagi = FPU_Special(r); | 188 | tagi = FPU_Special(r); |
| 189 | /* fall through */ | ||
| 188 | case TAG_Valid: | 190 | case TAG_Valid: |
| 189 | printk("st(%d) %c .%04lx %04lx %04lx %04lx e%+-6d ", i, | 191 | printk("st(%d) %c .%04lx %04lx %04lx %04lx e%+-6d ", i, |
| 190 | getsign(r) ? '-' : '+', | 192 | getsign(r) ? '-' : '+', |
| @@ -198,7 +200,6 @@ void FPU_printall(void) · 7 unmodified lines | |||
| 198 | printk("Whoops! Error in errors.c: tag%d is %d ", i, | 200 | printk("Whoops! Error in errors.c: tag%d is %d ", i, |
| 199 | tagi); | 201 | tagi); |
| 200 | continue; | 202 | continue; |
| 201 | break; | ||
| 202 | } | 203 | } |
| 203 | printk("%s\n", tag_desc[(int)(unsigned)tagi]); | 204 | printk("%s\n", tag_desc[(int)(unsigned)tagi]); |
| 204 | } | 205 | } |
| @@ -1352,7 +1352,7 @@ static void fyl2xp1(FPU_REG *st0_ptr, u_char st0_tag) · 1351 unmodified lines | |||
| 1352 | case TW_Denormal: | 1352 | case TW_Denormal: |
| 1353 | if (denormal_operand() < 0) | 1353 | if (denormal_operand() < 0) |
| 1354 | return; | 1354 | return; |
| 1355 | 1355 | /* fall through */ | |
| 1356 | case TAG_Zero: | 1356 | case TAG_Zero: |
| 1357 | case TAG_Valid: | 1357 | case TAG_Valid: |
| 1358 | setsign(st0_ptr, getsign(st0_ptr) ^ getsign(st1_ptr)); | 1358 | setsign(st0_ptr, getsign(st0_ptr) ^ getsign(st1_ptr)); |
| @@ -177,13 +177,14 @@ static inline pmd_t *vmalloc_sync_one(pgd_t *pgd, unsigned long address) · 176 unmodified lines | |||
| 177 | 177 | ||
| 178 | pmd = pmd_offset(pud, address); | 178 | pmd = pmd_offset(pud, address); |
| 179 | pmd_k = pmd_offset(pud_k, address); | 179 | pmd_k = pmd_offset(pud_k, address); |
| 180 | if (!pmd_present(*pmd_k)) | ||
| 181 | return NULL; | ||
| 182 | 180 | ||
| 183 | if (!pmd_present(*pmd)) | 181 | if (pmd_present(*pmd) != pmd_present(*pmd_k)) |
| 184 | set_pmd(pmd, *pmd_k); | 182 | set_pmd(pmd, *pmd_k); |
| 183 | |||
| 184 | if (!pmd_present(*pmd_k)) | ||
| 185 | return NULL; | ||
| 185 | else | 186 | else |
| 186 | BUG_ON(pmd_page(*pmd) != pmd_page(*pmd_k)); | 187 | BUG_ON(pmd_pfn(*pmd) != pmd_pfn(*pmd_k)); |
| 187 | 188 | ||
| 188 | return pmd_k; | 189 | return pmd_k; |
| 189 | } | 190 | } |
| @@ -203,17 +204,13 @@ void vmalloc_sync_all(void) · 13 unmodified lines | |||
| 203 | spin_lock(&pgd_lock); | 204 | spin_lock(&pgd_lock); |
| 204 | list_for_each_entry(page, &pgd_list, lru) { | 205 | list_for_each_entry(page, &pgd_list, lru) { |
| 205 | spinlock_t *pgt_lock; | 206 | spinlock_t *pgt_lock; |
| 206 | pmd_t *ret; | ||
| 207 | 207 | ||
| 208 | /* the pgt_lock only for Xen */ | 208 | /* the pgt_lock only for Xen */ |
| 209 | pgt_lock = &pgd_page_get_mm(page)->page_table_lock; | 209 | pgt_lock = &pgd_page_get_mm(page)->page_table_lock; |
| 210 | 210 | ||
| 211 | spin_lock(pgt_lock); | 211 | spin_lock(pgt_lock); |
| 212 | ret = vmalloc_sync_one(page_address(page), address); | 212 | vmalloc_sync_one(page_address(page), address); |
| 213 | spin_unlock(pgt_lock); | 213 | spin_unlock(pgt_lock); |
| 214 | |||
| 215 | if (!ret) | ||
| 216 | break; | ||
| 217 | } | 214 | } |
| 218 | spin_unlock(&pgd_lock); | 215 | spin_unlock(&pgd_lock); |
| 219 | } | 216 | } |
| @@ -6,6 +6,9 @@ purgatory-y := purgatory.o stack.o setup-x86_$(BITS).o sha256.o entry64.o string · 5 unmodified lines | |||
| 6 | targets += $(purgatory-y) | 6 | targets += $(purgatory-y) |
| 7 | PURGATORY_OBJS = $(addprefix $(obj)/,$(purgatory-y)) | 7 | PURGATORY_OBJS = $(addprefix $(obj)/,$(purgatory-y)) |
| 8 | 8 | ||
| 9 | $(obj)/string.o: $(srctree)/arch/x86/boot/compressed/string.c FORCE | ||
| 10 | $(call if_changed_rule,cc_o_c) | ||
| 11 | |||
| 9 | $(obj)/sha256.o: $(srctree)/lib/sha256.c FORCE | 12 | $(obj)/sha256.o: $(srctree)/lib/sha256.c FORCE |
| 10 | $(call if_changed_rule,cc_o_c) | 13 | $(call if_changed_rule,cc_o_c) |
| 11 | 14 | ||
| @@ -17,11 +20,34 @@ KCOV_INSTRUMENT := n · 5 unmodified lines | |||
| 17 | 20 | ||
| 18 | # Default KBUILD_CFLAGS can have -pg option set when FTRACE is enabled. That | 21 | # Default KBUILD_CFLAGS can have -pg option set when FTRACE is enabled. That |
| 19 | # in turn leaves some undefined symbols like __fentry__ in purgatory and not | 22 | # in turn leaves some undefined symbols like __fentry__ in purgatory and not |
| 20 | # sure how to relocate those. Like kexec-tools, use custom flags. | 23 | # sure how to relocate those. |
| 21 | 24 | ifdef CONFIG_FUNCTION_TRACER | |
| 22 | KBUILD_CFLAGS := -fno-strict-aliasing -Wall -Wstrict-prototypes -fno-zero-initialized-in-bss -fno-builtin -ffreestanding -c -Os -mcmodel=large | 25 | CFLAGS_REMOVE_sha256.o += $(CC_FLAGS_FTRACE) |
| 23 | KBUILD_CFLAGS += -m$(BITS) | 26 | CFLAGS_REMOVE_purgatory.o += $(CC_FLAGS_FTRACE) |
| 24 | KBUILD_CFLAGS += $(call cc-option,-fno-PIE) | 27 | CFLAGS_REMOVE_string.o += $(CC_FLAGS_FTRACE) |
| 28 | CFLAGS_REMOVE_kexec-purgatory.o += $(CC_FLAGS_FTRACE) | ||
| 29 | endif | ||
| 30 | |||
| 31 | ifdef CONFIG_STACKPROTECTOR | ||
| 32 | CFLAGS_REMOVE_sha256.o += -fstack-protector | ||
| 33 | CFLAGS_REMOVE_purgatory.o += -fstack-protector | ||
| 34 | CFLAGS_REMOVE_string.o += -fstack-protector | ||
| 35 | CFLAGS_REMOVE_kexec-purgatory.o += -fstack-protector | ||
| 36 | endif | ||
| 37 | |||
| 38 | ifdef CONFIG_STACKPROTECTOR_STRONG | ||
| 39 | CFLAGS_REMOVE_sha256.o += -fstack-protector-strong | ||
| 40 | CFLAGS_REMOVE_purgatory.o += -fstack-protector-strong | ||
| 41 | CFLAGS_REMOVE_string.o += -fstack-protector-strong | ||
| 42 | CFLAGS_REMOVE_kexec-purgatory.o += -fstack-protector-strong | ||
| 43 | endif | ||
| 44 | |||
| 45 | ifdef CONFIG_RETPOLINE | ||
| 46 | CFLAGS_REMOVE_sha256.o += $(RETPOLINE_CFLAGS) | ||
| 47 | CFLAGS_REMOVE_purgatory.o += $(RETPOLINE_CFLAGS) | ||
| 48 | CFLAGS_REMOVE_string.o += $(RETPOLINE_CFLAGS) | ||
| 49 | CFLAGS_REMOVE_kexec-purgatory.o += $(RETPOLINE_CFLAGS) | ||
| 50 | endif | ||
| 25 | 51 | ||
| 26 | $(obj)/purgatory.ro: $(PURGATORY_OBJS) FORCE | 52 | $(obj)/purgatory.ro: $(PURGATORY_OBJS) FORCE |
| 27 | $(call if_changed,ld) | 53 | $(call if_changed,ld) |
| @@ -68,3 +68,9 @@ void purgatory(void) · 67 unmodified lines | |||
| 68 | } | 68 | } |
| 69 | copy_backup_region(); | 69 | copy_backup_region(); |
| 70 | } | 70 | } |
| 71 | |||
| 72 | /* | ||
| 73 | * Defined in order to reuse memcpy() and memset() from | ||
| 74 | * arch/x86/boot/compressed/string.c | ||
| 75 | */ | ||
| 76 | void warn(const char *msg) {} | ||
| @@ -1,23 +0,0 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0-only | ||
| 2 | /* | ||
| 3 | * Simple string functions. | ||
| 4 | * | ||
| 5 | * Copyright (C) 2014 Red Hat Inc. | ||
| 6 | * | ||
| 7 | * Author: | ||
| 8 | * Vivek Goyal <vgoyal@redhat.com> | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/types.h> | ||
| 12 | |||
| 13 | #include "../boot/string.c" | ||
| 14 | |||
| 15 | void *memcpy(void *dst, const void *src, size_t len) | ||
| 16 | { | ||
| 17 | return __builtin_memcpy(dst, src, len); | ||
| 18 | } | ||
| 19 | |||
| 20 | void *memset(void *dst, int c, size_t len) | ||
| 21 | { | ||
| 22 | return __builtin_memset(dst, c, len); | ||
| 23 | } | ||
| @@ -14,6 +14,7 @@ · 13 unmodified lines | |||
| 14 | 14 | ||
| 15 | #include <linux/linkage.h> | 15 | #include <linux/linkage.h> |
| 16 | #include <asm/asm-offsets.h> | 16 | #include <asm/asm-offsets.h> |
| 17 | #include <asm/asmmacro.h> | ||
| 17 | #include <asm/processor.h> | 18 | #include <asm/processor.h> |
| 18 | #include <asm/coprocessor.h> | 19 | #include <asm/coprocessor.h> |
| 19 | #include <asm/thread_info.h> | 20 | #include <asm/thread_info.h> |
| @@ -511,6 +511,7 @@ void cpu_reset(void) · 510 unmodified lines | |||
| 511 | "add %2, %2, %7\n\t" | 511 | "add %2, %2, %7\n\t" |
| 512 | "addi %0, %0, -1\n\t" | 512 | "addi %0, %0, -1\n\t" |
| 513 | "bnez %0, 1b\n\t" | 513 | "bnez %0, 1b\n\t" |
| 514 | "isync\n\t" | ||
| 514 | /* Jump to identity mapping */ | 515 | /* Jump to identity mapping */ |
| 515 | "jx %3\n" | 516 | "jx %3\n" |
| 516 | "2:\n\t" | 517 | "2:\n\t" |
| @@ -1924,12 +1924,13 @@ static void bfq_add_request(struct request *rq) · 1923 unmodified lines | |||
| 1924 | * confirmed no later than during the next | 1924 | * confirmed no later than during the next |
| 1925 | * I/O-plugging interval for bfqq. | 1925 | * I/O-plugging interval for bfqq. |
| 1926 | */ | 1926 | */ |
| 1927 | if (!bfq_bfqq_has_short_ttime(bfqq) && | 1927 | if (bfqd->last_completed_rq_bfqq && |
| 1928 | !bfq_bfqq_has_short_ttime(bfqq) && | ||
| 1928 | ktime_get_ns() - bfqd->last_completion < | 1929 | ktime_get_ns() - bfqd->last_completion < |
| 1929 | 200 * NSEC_PER_USEC) { | 1930 | 200 * NSEC_PER_USEC) { |
| 1930 | if (bfqd->last_completed_rq_bfqq != bfqq && | 1931 | if (bfqd->last_completed_rq_bfqq != bfqq && |
| 1931 | bfqd->last_completed_rq_bfqq != | 1932 | bfqd->last_completed_rq_bfqq != |
| 1932 | bfqq->waker_bfqq) { | 1933 | bfqq->waker_bfqq) { |
| 1933 | /* | 1934 | /* |
| 1934 | * First synchronization detected with | 1935 | * First synchronization detected with |
| 1935 | * a candidate waker queue, or with a | 1936 | * a candidate waker queue, or with a |
| @@ -2250,9 +2251,14 @@ static void bfq_request_merged(struct request_queue *q, struct request *req, · 314 unmodified lines | |||
| 2250 | blk_rq_pos(container_of(rb_prev(&req->rb_node), | 2251 | blk_rq_pos(container_of(rb_prev(&req->rb_node), |
| 2251 | struct request, rb_node))) { | 2252 | struct request, rb_node))) { |
| 2252 | struct bfq_queue *bfqq = bfq_init_rq(req); | 2253 | struct bfq_queue *bfqq = bfq_init_rq(req); |
| 2253 | struct bfq_data *bfqd = bfqq->bfqd; | 2254 | struct bfq_data *bfqd; |
| 2254 | struct request *prev, *next_rq; | 2255 | struct request *prev, *next_rq; |
| 2255 | 2256 | ||
| 2257 | if (!bfqq) | ||
| 2258 | return; | ||
| 2259 | |||
| 2260 | bfqd = bfqq->bfqd; | ||
| 2261 | |||
| 2256 | /* Reposition request in its sort_list */ | 2262 | /* Reposition request in its sort_list */ |
| 2257 | elv_rb_del(&bfqq->sort_list, req); | 2263 | elv_rb_del(&bfqq->sort_list, req); |
| 2258 | elv_rb_add(&bfqq->sort_list, req); | 2264 | elv_rb_add(&bfqq->sort_list, req); |
| @@ -2299,6 +2305,9 @@ static void bfq_requests_merged(struct request_queue *q, struct request *rq, · 40 unmodified lines | |||
| 2299 | struct bfq_queue *bfqq = bfq_init_rq(rq), | 2305 | struct bfq_queue *bfqq = bfq_init_rq(rq), |
| 2300 | *next_bfqq = bfq_init_rq(next); | 2306 | *next_bfqq = bfq_init_rq(next); |
| 2301 | 2307 | ||
| 2308 | if (!bfqq) | ||
| 2309 | return; | ||
| 2310 | |||
| 2302 | /* | 2311 | /* |
| 2303 | * If next and rq belong to the same bfq_queue and next is older | 2312 | * If next and rq belong to the same bfq_queue and next is older |
| 2304 | * than rq, then reposition rq in the fifo (by substituting next | 2313 | * than rq, then reposition rq in the fifo (by substituting next |
| @@ -3354,38 +3363,57 @@ static void bfq_dispatch_remove(struct request_queue *q, struct request *rq) · 1049 unmodified lines | |||
| 3354 | * there is no active group, then the primary expectation for | 3363 | * there is no active group, then the primary expectation for |
| 3355 | * this device is probably a high throughput. | 3364 | * this device is probably a high throughput. |
| 3356 | * | 3365 | * |
| 3357 | * We are now left only with explaining the additional | 3366 | * We are now left only with explaining the two sub-conditions in the |
| 3358 | * compound condition that is checked below for deciding | 3367 | * additional compound condition that is checked below for deciding |
| 3359 | * whether the scenario is asymmetric. To explain this | 3368 | * whether the scenario is asymmetric. To explain the first |
| 3360 | * compound condition, we need to add that the function | 3369 | * sub-condition, we need to add that the function |
| 3361 | * bfq_asymmetric_scenario checks the weights of only | 3370 | * bfq_asymmetric_scenario checks the weights of only |
| 3362 | * non-weight-raised queues, for efficiency reasons (see | 3371 | * non-weight-raised queues, for efficiency reasons (see comments on |
| 3363 | * comments on bfq_weights_tree_add()). Then the fact that | 3372 | * bfq_weights_tree_add()). Then the fact that bfqq is weight-raised |
| 3364 | * bfqq is weight-raised is checked explicitly here. More | 3373 | * is checked explicitly here. More precisely, the compound condition |
| 3365 | * precisely, the compound condition below takes into account | 3374 | * below takes into account also the fact that, even if bfqq is being |
| 3366 | * also the fact that, even if bfqq is being weight-raised, | 3375 | * weight-raised, the scenario is still symmetric if all queues with |
| 3367 | * the scenario is still symmetric if all queues with requests | 3376 | * requests waiting for completion happen to be |
| 3368 | * waiting for completion happen to be | 3377 | * weight-raised. Actually, we should be even more precise here, and |
| 3369 | * weight-raised. Actually, we should be even more precise | 3378 | * differentiate between interactive weight raising and soft real-time |
| 3370 | * here, and differentiate between interactive weight raising | 3379 | * weight raising. |
| 3371 | * and soft real-time weight raising. | 3380 | * |
| 3381 | * The second sub-condition checked in the compound condition is | ||
| 3382 | * whether there is a fair amount of already in-flight I/O not | ||
| 3383 | * belonging to bfqq. If so, I/O dispatching is to be plugged, for the | ||
| 3384 | * following reason. The drive may decide to serve in-flight | ||
| 3385 | * non-bfqq's I/O requests before bfqq's ones, thereby delaying the | ||
| 3386 | * arrival of new I/O requests for bfqq (recall that bfqq is sync). If | ||
| 3387 | * I/O-dispatching is not plugged, then, while bfqq remains empty, a | ||
| 3388 | * basically uncontrolled amount of I/O from other queues may be | ||
| 3389 | * dispatched too, possibly causing the service of bfqq's I/O to be | ||
| 3390 | * delayed even longer in the drive. This problem gets more and more | ||
| 3391 | * serious as the speed and the queue depth of the drive grow, | ||
| 3392 | * because, as these two quantities grow, the probability to find no | ||
| 3393 | * queue busy but many requests in flight grows too. By contrast, | ||
| 3394 | * plugging I/O dispatching minimizes the delay induced by already | ||
| 3395 | * in-flight I/O, and enables bfqq to recover the bandwidth it may | ||
| 3396 | * lose because of this delay. | ||
| 3372 | * | 3397 | * |
| 3373 | * As a side note, it is worth considering that the above | 3398 | * As a side note, it is worth considering that the above |
| 3374 | * device-idling countermeasures may however fail in the | 3399 | * device-idling countermeasures may however fail in the following |
| 3375 | * following unlucky scenario: if idling is (correctly) | 3400 | * unlucky scenario: if I/O-dispatch plugging is (correctly) disabled |
| 3376 | * disabled in a time period during which all symmetry | 3401 | * in a time period during which all symmetry sub-conditions hold, and |
| 3377 | * sub-conditions hold, and hence the device is allowed to | 3402 | * therefore the device is allowed to enqueue many requests, but at |
| 3378 | * enqueue many requests, but at some later point in time some | 3403 | * some later point in time some sub-condition stops to hold, then it |
| 3379 | * sub-condition stops to hold, then it may become impossible | 3404 | * may become impossible to make requests be served in the desired |
| 3380 | * to let requests be served in the desired order until all | 3405 | * order until all the requests already queued in the device have been |
| 3381 | * the requests already queued in the device have been served. | 3406 | * served. The last sub-condition commented above somewhat mitigates |
| 3407 | * this problem for weight-raised queues. | ||
| 3382 | */ | 3408 | */ |
| 3383 | static bool idling_needed_for_service_guarantees(struct bfq_data *bfqd, | 3409 | static bool idling_needed_for_service_guarantees(struct bfq_data *bfqd, |
| 3384 | struct bfq_queue *bfqq) | 3410 | struct bfq_queue *bfqq) |
| 3385 | { | 3411 | { |
| 3386 | return (bfqq->wr_coeff > 1 && | 3412 | return (bfqq->wr_coeff > 1 && |
| 3387 | bfqd->wr_busy_queues < | 3413 | (bfqd->wr_busy_queues < |
| 3388 | bfq_tot_busy_queues(bfqd)) || | 3414 | bfq_tot_busy_queues(bfqd) || |
| 3415 | bfqd->rq_in_driver >= | ||
| 3416 | bfqq->dispatched + 4)) || | ||
| 3389 | bfq_asymmetric_scenario(bfqd, bfqq); | 3417 | bfq_asymmetric_scenario(bfqd, bfqq); |
| 3390 | } | 3418 | } |
| 3391 | 3419 | ||
| @@ -4745,6 +4773,8 @@ static struct request *bfq_dispatch_request(struct blk_mq_hw_ctx *hctx) · 1353 unmodified lines | |||
| 4745 | */ | 4773 | */ |
| 4746 | void bfq_put_queue(struct bfq_queue *bfqq) | 4774 | void bfq_put_queue(struct bfq_queue *bfqq) |
| 4747 | { | 4775 | { |
| 4776 | struct bfq_queue *item; | ||
| 4777 | struct hlist_node *n; | ||
| 4748 | #ifdef CONFIG_BFQ_GROUP_IOSCHED | 4778 | #ifdef CONFIG_BFQ_GROUP_IOSCHED |
| 4749 | struct bfq_group *bfqg = bfqq_group(bfqq); | 4779 | struct bfq_group *bfqg = bfqq_group(bfqq); |
| 4750 | #endif | 4780 | #endif |
| @@ -4789,6 +4819,36 @@ void bfq_put_queue(struct bfq_queue *bfqq) · 38 unmodified lines | |||
| 4789 | bfqq->bfqd->burst_size--; | 4819 | bfqq->bfqd->burst_size--; |
| 4790 | } | 4820 | } |
| 4791 | 4821 | ||
| 4822 | /* | ||
| 4823 | * bfqq does not exist any longer, so it cannot be woken by | ||
| 4824 | * any other queue, and cannot wake any other queue. Then bfqq | ||
| 4825 | * must be removed from the woken list of its possible waker | ||
| 4826 | * queue, and all queues in the woken list of bfqq must stop | ||
| 4827 | * having a waker queue. Strictly speaking, these updates | ||
| 4828 | * should be performed when bfqq remains with no I/O source | ||
| 4829 | * attached to it, which happens before bfqq gets freed. In | ||
| 4830 | * particular, this happens when the last process associated | ||
| 4831 | * with bfqq exits or gets associated with a different | ||
| 4832 | * queue. However, both events lead to bfqq being freed soon, | ||
| 4833 | * and dangling references would come out only after bfqq gets | ||
| 4834 | * freed. So these updates are done here, as a simple and safe | ||
| 4835 | * way to handle all cases. | ||
| 4836 | */ | ||
| 4837 | /* remove bfqq from woken list */ | ||
| 4838 | if (!hlist_unhashed(&bfqq->woken_list_node)) | ||
| 4839 | hlist_del_init(&bfqq->woken_list_node); | ||
| 4840 | |||
| 4841 | /* reset waker for all queues in woken list */ | ||
| 4842 | hlist_for_each_entry_safe(item, n, &bfqq->woken_list, | ||
| 4843 | woken_list_node) { | ||
| 4844 | item->waker_bfqq = NULL; | ||
| 4845 | bfq_clear_bfqq_has_waker(item); | ||
| 4846 | hlist_del_init(&item->woken_list_node); | ||
| 4847 | } | ||
| 4848 | |||
| 4849 | if (bfqq->bfqd && bfqq->bfqd->last_completed_rq_bfqq == bfqq) | ||
| 4850 | bfqq->bfqd->last_completed_rq_bfqq = NULL; | ||
| 4851 | |||
| 4792 | kmem_cache_free(bfq_pool, bfqq); | 4852 | kmem_cache_free(bfq_pool, bfqq); |
| 4793 | #ifdef CONFIG_BFQ_GROUP_IOSCHED | 4853 | #ifdef CONFIG_BFQ_GROUP_IOSCHED |
| 4794 | bfqg_and_blkg_put(bfqg); | 4854 | bfqg_and_blkg_put(bfqg); |
| @@ -4816,9 +4876,6 @@ static void bfq_put_cooperator(struct bfq_queue *bfqq) · 21 unmodified lines | |||
| 4816 | 4876 | ||
| 4817 | static void bfq_exit_bfqq(struct bfq_data *bfqd, struct bfq_queue *bfqq) | 4877 | static void bfq_exit_bfqq(struct bfq_data *bfqd, struct bfq_queue *bfqq) |
| 4818 | { | 4878 | { |
| 4819 | struct bfq_queue *item; | ||
| 4820 | struct hlist_node *n; | ||
| 4821 | |||
| 4822 | if (bfqq == bfqd->in_service_queue) { | 4879 | if (bfqq == bfqd->in_service_queue) { |
| 4823 | __bfq_bfqq_expire(bfqd, bfqq, BFQQE_BUDGET_TIMEOUT); | 4880 | __bfq_bfqq_expire(bfqd, bfqq, BFQQE_BUDGET_TIMEOUT); |
| 4824 | bfq_schedule_dispatch(bfqd); | 4881 | bfq_schedule_dispatch(bfqd); |
| @@ -4828,18 +4885,6 @@ static void bfq_exit_bfqq(struct bfq_data *bfqd, struct bfq_queue *bfqq) · 3 unmodified lines | |||
| 4828 | 4885 | ||
| 4829 | bfq_put_cooperator(bfqq); | 4886 | bfq_put_cooperator(bfqq); |
| 4830 | 4887 | ||
| 4831 | /* remove bfqq from woken list */ | ||
| 4832 | if (!hlist_unhashed(&bfqq->woken_list_node)) | ||
| 4833 | hlist_del_init(&bfqq->woken_list_node); | ||
| 4834 | |||
| 4835 | /* reset waker for all queues in woken list */ | ||
| 4836 | hlist_for_each_entry_safe(item, n, &bfqq->woken_list, | ||
| 4837 | woken_list_node) { | ||
| 4838 | item->waker_bfqq = NULL; | ||
| 4839 | bfq_clear_bfqq_has_waker(item); | ||
| 4840 | hlist_del_init(&item->woken_list_node); | ||
| 4841 | } | ||
| 4842 | |||
| 4843 | bfq_put_queue(bfqq); /* release process reference */ | 4888 | bfq_put_queue(bfqq); /* release process reference */ |
| 4844 | } | 4889 | } |
| 4845 | 4890 | ||
| @@ -5417,12 +5462,12 @@ static void bfq_insert_request(struct blk_mq_hw_ctx *hctx, struct request *rq, · 571 unmodified lines | |||
| 5417 | 5462 | ||
| 5418 | spin_lock_irq(&bfqd->lock); | 5463 | spin_lock_irq(&bfqd->lock); |
| 5419 | bfqq = bfq_init_rq(rq); | 5464 | bfqq = bfq_init_rq(rq); |
| 5420 | if (at_head || blk_rq_is_passthrough(rq)) { | 5465 | if (!bfqq || at_head || blk_rq_is_passthrough(rq)) { |
| 5421 | if (at_head) | 5466 | if (at_head) |
| 5422 | list_add(&rq->queuelist, &bfqd->dispatch); | 5467 | list_add(&rq->queuelist, &bfqd->dispatch); |
| 5423 | else | 5468 | else |
| 5424 | list_add_tail(&rq->queuelist, &bfqd->dispatch); | 5469 | list_add_tail(&rq->queuelist, &bfqd->dispatch); |
| 5425 | } else { /* bfqq is assumed to be non null here */ | 5470 | } else { |
| 5426 | idle_timer_disabled = __bfq_insert_request(bfqd, rq); | 5471 | idle_timer_disabled = __bfq_insert_request(bfqd, rq); |
| 5427 | /* | 5472 | /* |
| 5428 | * Update bfqq, because, if a queue merge has occurred | 5473 | * Update bfqq, because, if a queue merge has occurred |
| @@ -54,7 +54,7 @@ static struct blkcg_policy *blkcg_policy[BLKCG_MAX_POLS]; · 53 unmodified lines | |||
| 54 | 54 | ||
| 55 | static LIST_HEAD(all_blkcgs); /* protected by blkcg_pol_mutex */ | 55 | static LIST_HEAD(all_blkcgs); /* protected by blkcg_pol_mutex */ |
| 56 | 56 | ||
| 57 | static bool blkcg_debug_stats = false; | 57 | bool blkcg_debug_stats = false; |
| 58 | static struct workqueue_struct *blkcg_punt_bio_wq; | 58 | static struct workqueue_struct *blkcg_punt_bio_wq; |
| 59 | 59 | ||
| 60 | static bool blkcg_policy_enabled(struct request_queue *q, | 60 | static bool blkcg_policy_enabled(struct request_queue *q, |
| @@ -944,10 +944,7 @@ static int blkcg_print_stat(struct seq_file *sf, void *v) · 883 unmodified lines | |||
| 944 | dbytes, dios); | 944 | dbytes, dios); |
| 945 | } | 945 | } |
| 946 | 946 | ||
| 947 | if (!blkcg_debug_stats) | 947 | if (blkcg_debug_stats && atomic_read(&blkg->use_delay)) { |
| 948 | goto next; | ||
| 949 | |||
| 950 | if (atomic_read(&blkg->use_delay)) { | ||
| 951 | has_stats = true; | 948 | has_stats = true; |
| 952 | off += scnprintf(buf+off, size-off, | 949 | off += scnprintf(buf+off, size-off, |
| 953 | " use_delay=%d delay_nsec=%llu", | 950 | " use_delay=%d delay_nsec=%llu", |
| @@ -967,7 +964,7 @@ static int blkcg_print_stat(struct seq_file *sf, void *v) · 13 unmodified lines | |||
| 967 | has_stats = true; | 964 | has_stats = true; |
| 968 | off += written; | 965 | off += written; |
| 969 | } | 966 | } |
| 970 | next: | 967 | |
| 971 | if (has_stats) { | 968 | if (has_stats) { |
| 972 | if (off < size - 1) { | 969 | if (off < size - 1) { |
| 973 | off += scnprintf(buf+off, size-off, "\n"); | 970 | off += scnprintf(buf+off, size-off, "\n"); |
| @@ -917,6 +917,9 @@ static size_t iolatency_pd_stat(struct blkg_policy_data *pd, char *buf, · 916 unmodified lines | |||
| 917 | unsigned long long avg_lat; | 917 | unsigned long long avg_lat; |
| 918 | unsigned long long cur_win; | 918 | unsigned long long cur_win; |
| 919 | 919 | ||
| 920 | if (!blkcg_debug_stats) | ||
| 921 | return 0; | ||
| 922 | |||
| 920 | if (iolat->ssd) | 923 | if (iolat->ssd) |
| 921 | return iolatency_ssd_stat(iolat, buf, size); | 924 | return iolatency_ssd_stat(iolat, buf, size); |
| 922 | 925 | ||
| @@ -61,15 +61,6 @@ static inline void blk_mq_sched_completed_request(struct request *rq, u64 now) · 60 unmodified lines | |||
| 61 | e->type->ops.completed_request(rq, now); | 61 | e->type->ops.completed_request(rq, now); |
| 62 | } | 62 | } |
| 63 | 63 | ||
| 64 | static inline void blk_mq_sched_started_request(struct request *rq) | ||
| 65 | { | ||
| 66 | struct request_queue *q = rq->q; | ||
| 67 | struct elevator_queue *e = q->elevator; | ||
| 68 | |||
| 69 | if (e && e->type->ops.started_request) | ||
| 70 | e->type->ops.started_request(rq); | ||
| 71 | } | ||
| 72 | |||
| 73 | static inline void blk_mq_sched_requeue_request(struct request *rq) | 64 | static inline void blk_mq_sched_requeue_request(struct request *rq) |
| 74 | { | 65 | { |
| 75 | struct request_queue *q = rq->q; | 66 | struct request_queue *q = rq->q; |
| @@ -669,8 +669,6 @@ void blk_mq_start_request(struct request *rq) · 668 unmodified lines | |||
| 669 | { | 669 | { |
| 670 | struct request_queue *q = rq->q; | 670 | struct request_queue *q = rq->q; |
| 671 | 671 | ||
| 672 | blk_mq_sched_started_request(rq); | ||
| 673 | |||
| 674 | trace_block_rq_issue(q, rq); | 672 | trace_block_rq_issue(q, rq); |
| 675 | 673 | ||
| 676 | if (test_bit(QUEUE_FLAG_STATS, &q->queue_flags)) { | 674 | if (test_bit(QUEUE_FLAG_STATS, &q->queue_flags)) { |
| @@ -2664,8 +2662,6 @@ void blk_mq_release(struct request_queue *q) · 1987 unmodified lines | |||
| 2664 | struct blk_mq_hw_ctx *hctx, *next; | 2662 | struct blk_mq_hw_ctx *hctx, *next; |
| 2665 | int i; | 2663 | int i; |
| 2666 | 2664 | ||
| 2667 | cancel_delayed_work_sync(&q->requeue_work); | ||
| 2668 | |||
| 2669 | queue_for_each_hw_ctx(q, hctx, i) | 2665 | queue_for_each_hw_ctx(q, hctx, i) |
| 2670 | WARN_ON_ONCE(hctx && list_empty(&hctx->hctx_list)); | 2666 | WARN_ON_ONCE(hctx && list_empty(&hctx->hctx_list)); |
| 2671 | 2667 | ||
| @@ -202,6 +202,7 @@ static int rq_qos_wake_function(struct wait_queue_entry *curr, · 201 unmodified lines | |||
| 202 | return -1; | 202 | return -1; |
| 203 | 203 | ||
| 204 | data->got_token = true; | 204 | data->got_token = true; |
| 205 | smp_wmb(); | ||
| 205 | list_del_init(&curr->entry); | 206 | list_del_init(&curr->entry); |
| 206 | wake_up_process(data->task); | 207 | wake_up_process(data->task); |
| 207 | return 1; | 208 | return 1; |
| @@ -244,7 +245,9 @@ void rq_qos_wait(struct rq_wait *rqw, void *private_data, · 36 unmodified lines | |||
| 244 | return; | 245 | return; |
| 245 | 246 | ||
| 246 | prepare_to_wait_exclusive(&rqw->wait, &data.wq, TASK_UNINTERRUPTIBLE); | 247 | prepare_to_wait_exclusive(&rqw->wait, &data.wq, TASK_UNINTERRUPTIBLE); |
| 248 | has_sleeper = !wq_has_single_sleeper(&rqw->wait); | ||
| 247 | do { | 249 | do { |
| 250 | /* The memory barrier in set_task_state saves us here. */ | ||
| 248 | if (data.got_token) | 251 | if (data.got_token) |
| 249 | break; | 252 | break; |
| 250 | if (!has_sleeper && acquire_inflight_cb(rqw, private_data)) { | 253 | if (!has_sleeper && acquire_inflight_cb(rqw, private_data)) { |
| @@ -255,12 +258,14 @@ void rq_qos_wait(struct rq_wait *rqw, void *private_data, · 4 unmodified lines | |||
| 255 | * which means we now have two. Put our local token | 258 | * which means we now have two. Put our local token |
| 256 | * and wake anyone else potentially waiting for one. | 259 | * and wake anyone else potentially waiting for one. |
| 257 | */ | 260 | */ |
| 261 | smp_rmb(); | ||
| 258 | if (data.got_token) | 262 | if (data.got_token) |
| 259 | cleanup_cb(rqw, private_data); | 263 | cleanup_cb(rqw, private_data); |
| 260 | break; | 264 | break; |
| 261 | } | 265 | } |
| 262 | io_schedule(); | 266 | io_schedule(); |
| 263 | has_sleeper = false; | 267 | has_sleeper = true; |
| 268 | set_current_state(TASK_UNINTERRUPTIBLE); | ||
| 264 | } while (1); | 269 | } while (1); |
| 265 | finish_wait(&rqw->wait, &data.wq); | 270 | finish_wait(&rqw->wait, &data.wq); |
| 266 | } | 271 | } |
| @@ -752,7 +752,8 @@ void blk_queue_virt_boundary(struct request_queue *q, unsigned long mask) · 751 unmodified lines | |||
| 752 | * page (which might not be idential to the Linux PAGE_SIZE). Because | 752 | * page (which might not be idential to the Linux PAGE_SIZE). Because |
| 753 | * of that they are not limited by our notion of "segment size". | 753 | * of that they are not limited by our notion of "segment size". |
| 754 | */ | 754 | */ |
| 755 | q->limits.max_segment_size = UINT_MAX; | 755 | if (mask) |
| 756 | q->limits.max_segment_size = UINT_MAX; | ||
| 756 | } | 757 | } |
| 757 | EXPORT_SYMBOL(blk_queue_virt_boundary); | 758 | EXPORT_SYMBOL(blk_queue_virt_boundary); |
| 758 | 759 | ||
| @@ -892,6 +892,9 @@ static void __blk_release_queue(struct work_struct *work) · 891 unmodified lines | |||
| 892 | 892 | ||
| 893 | blk_free_queue_stats(q->stats); | 893 | blk_free_queue_stats(q->stats); |
| 894 | 894 | ||
| 895 | if (queue_is_mq(q)) | ||
| 896 | cancel_delayed_work_sync(&q->requeue_work); | ||
| 897 | |||
| 895 | blk_exit_queue(q); | 898 | blk_exit_queue(q); |
| 896 | 899 | ||
| 897 | blk_queue_free_zone_bitmaps(q); | 900 | blk_queue_free_zone_bitmaps(q); |
| @@ -1969,7 +1969,7 @@ static const struct attribute *disk_events_attrs[] = { · 1968 unmodified lines | |||
| 1969 | * The default polling interval can be specified by the kernel | 1969 | * The default polling interval can be specified by the kernel |
| 1970 | * parameter block.events_dfl_poll_msecs which defaults to 0 | 1970 | * parameter block.events_dfl_poll_msecs which defaults to 0 |
| 1971 | * (disable). This can also be modified runtime by writing to | 1971 | * (disable). This can also be modified runtime by writing to |
| 1972 | * /sys/module/block/events_dfl_poll_msecs. | 1972 | * /sys/module/block/parameters/events_dfl_poll_msecs. |
| 1973 | */ | 1973 | */ |
| 1974 | static int disk_events_set_dfl_poll_msecs(const char *val, | 1974 | static int disk_events_set_dfl_poll_msecs(const char *val, |
| 1975 | const struct kernel_param *kp) | 1975 | const struct kernel_param *kp) |
| @@ -611,8 +611,8 @@ static int iort_dev_find_its_id(struct device *dev, u32 req_id, · 610 unmodified lines | |||
| 611 | 611 | ||
| 612 | /* Move to ITS specific data */ | 612 | /* Move to ITS specific data */ |
| 613 | its = (struct acpi_iort_its_group *)node->node_data; | 613 | its = (struct acpi_iort_its_group *)node->node_data; |
| 614 | if (idx > its->its_count) { | 614 | if (idx >= its->its_count) { |
| 615 | dev_err(dev, "requested ITS ID index [%d] is greater than available [%d]\n", | 615 | dev_err(dev, "requested ITS ID index [%d] overruns ITS entries [%d]\n", |
| 616 | idx, its->its_count); | 616 | idx, its->its_count); |
| 617 | return -ENXIO; | 617 | return -ENXIO; |
| 618 | } | 618 | } |
| @@ -232,13 +232,15 @@ int acpi_device_set_power(struct acpi_device *device, int state) · 231 unmodified lines | |||
| 232 | if (device->power.flags.power_resources) | 232 | if (device->power.flags.power_resources) |
| 233 | result = acpi_power_transition(device, target_state); | 233 | result = acpi_power_transition(device, target_state); |
| 234 | } else { | 234 | } else { |
| 235 | int cur_state = device->power.state; | ||
| 236 | |||
| 235 | if (device->power.flags.power_resources) { | 237 | if (device->power.flags.power_resources) { |
| 236 | result = acpi_power_transition(device, ACPI_STATE_D0); | 238 | result = acpi_power_transition(device, ACPI_STATE_D0); |
| 237 | if (result) | 239 | if (result) |
| 238 | goto end; | 240 | goto end; |
| 239 | } | 241 | } |
| 240 | 242 | ||
| 241 | if (device->power.state == ACPI_STATE_D0) { | 243 | if (cur_state == ACPI_STATE_D0) { |
| 242 | int psc; | 244 | int psc; |
| 243 | 245 | ||
| 244 | /* Nothing to do here if _PSC is not present. */ | 246 | /* Nothing to do here if _PSC is not present. */ |
| @@ -1282,7 +1282,7 @@ static ssize_t hw_error_scrub_store(struct device *dev, · 1281 unmodified lines | |||
| 1282 | if (rc) | 1282 | if (rc) |
| 1283 | return rc; | 1283 | return rc; |
| 1284 | 1284 | ||
| 1285 | device_lock(dev); | 1285 | nfit_device_lock(dev); |
| 1286 | nd_desc = dev_get_drvdata(dev); | 1286 | nd_desc = dev_get_drvdata(dev); |
| 1287 | if (nd_desc) { | 1287 | if (nd_desc) { |
| 1288 | struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc); | 1288 | struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc); |
| @@ -1299,7 +1299,7 @@ static ssize_t hw_error_scrub_store(struct device *dev, · 10 unmodified lines | |||
| 1299 | break; | 1299 | break; |
| 1300 | } | 1300 | } |
| 1301 | } | 1301 | } |
| 1302 | device_unlock(dev); | 1302 | nfit_device_unlock(dev); |
| 1303 | if (rc) | 1303 | if (rc) |
| 1304 | return rc; | 1304 | return rc; |
| 1305 | return size; | 1305 | return size; |
| @@ -1319,7 +1319,7 @@ static ssize_t scrub_show(struct device *dev, · 13 unmodified lines | |||
| 1319 | ssize_t rc = -ENXIO; | 1319 | ssize_t rc = -ENXIO; |
| 1320 | bool busy; | 1320 | bool busy; |
| 1321 | 1321 | ||
| 1322 | device_lock(dev); | 1322 | nfit_device_lock(dev); |
| 1323 | nd_desc = dev_get_drvdata(dev); | 1323 | nd_desc = dev_get_drvdata(dev); |
| 1324 | if (!nd_desc) { | 1324 | if (!nd_desc) { |
| 1325 | device_unlock(dev); | 1325 | device_unlock(dev); |
| @@ -1339,7 +1339,7 @@ static ssize_t scrub_show(struct device *dev, · 13 unmodified lines | |||
| 1339 | } | 1339 | } |
| 1340 | 1340 | ||
| 1341 | mutex_unlock(&acpi_desc->init_mutex); | 1341 | mutex_unlock(&acpi_desc->init_mutex); |
| 1342 | device_unlock(dev); | 1342 | nfit_device_unlock(dev); |
| 1343 | return rc; | 1343 | return rc; |
| 1344 | } | 1344 | } |
| 1345 | 1345 | ||
| @@ -1356,14 +1356,14 @@ static ssize_t scrub_store(struct device *dev, · 10 unmodified lines | |||
| 1356 | if (val != 1) | 1356 | if (val != 1) |
| 1357 | return -EINVAL; | 1357 | return -EINVAL; |
| 1358 | 1358 | ||
| 1359 | device_lock(dev); | 1359 | nfit_device_lock(dev); |
| 1360 | nd_desc = dev_get_drvdata(dev); | 1360 | nd_desc = dev_get_drvdata(dev); |
| 1361 | if (nd_desc) { | 1361 | if (nd_desc) { |
| 1362 | struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc); | 1362 | struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc); |
| 1363 | 1363 | ||
| 1364 | rc = acpi_nfit_ars_rescan(acpi_desc, ARS_REQ_LONG); | 1364 | rc = acpi_nfit_ars_rescan(acpi_desc, ARS_REQ_LONG); |
| 1365 | } | 1365 | } |
| 1366 | device_unlock(dev); | 1366 | nfit_device_unlock(dev); |
| 1367 | if (rc) | 1367 | if (rc) |
| 1368 | return rc; | 1368 | return rc; |
| 1369 | return size; | 1369 | return size; |
| @@ -1749,9 +1749,9 @@ static void acpi_nvdimm_notify(acpi_handle handle, u32 event, void *data) · 379 unmodified lines | |||
| 1749 | struct acpi_device *adev = data; | 1749 | struct acpi_device *adev = data; |
| 1750 | struct device *dev = &adev->dev; | 1750 | struct device *dev = &adev->dev; |
| 1751 | 1751 | ||
| 1752 | device_lock(dev->parent); | 1752 | nfit_device_lock(dev->parent); |
| 1753 | __acpi_nvdimm_notify(dev, event); | 1753 | __acpi_nvdimm_notify(dev, event); |
| 1754 | device_unlock(dev->parent); | 1754 | nfit_device_unlock(dev->parent); |
| 1755 | } | 1755 | } |
| 1756 | 1756 | ||
| 1757 | static bool acpi_nvdimm_has_method(struct acpi_device *adev, char *method) | 1757 | static bool acpi_nvdimm_has_method(struct acpi_device *adev, char *method) |
| @@ -3457,8 +3457,8 @@ static int acpi_nfit_flush_probe(struct nvdimm_bus_descriptor *nd_desc) · 1699 unmodified lines | |||
| 3457 | struct device *dev = acpi_desc->dev; | 3457 | struct device *dev = acpi_desc->dev; |
| 3458 | 3458 | ||
| 3459 | /* Bounce the device lock to flush acpi_nfit_add / acpi_nfit_notify */ | 3459 | /* Bounce the device lock to flush acpi_nfit_add / acpi_nfit_notify */ |
| 3460 | device_lock(dev); | 3460 | nfit_device_lock(dev); |
| 3461 | device_unlock(dev); | 3461 | nfit_device_unlock(dev); |
| 3462 | 3462 | ||
| 3463 | /* Bounce the init_mutex to complete initial registration */ | 3463 | /* Bounce the init_mutex to complete initial registration */ |
| 3464 | mutex_lock(&acpi_desc->init_mutex); | 3464 | mutex_lock(&acpi_desc->init_mutex); |
| @@ -3602,8 +3602,8 @@ void acpi_nfit_shutdown(void *data) · 137 unmodified lines | |||
| 3602 | * acpi_nfit_ars_rescan() submissions have had a chance to | 3602 | * acpi_nfit_ars_rescan() submissions have had a chance to |
| 3603 | * either submit or see ->cancel set. | 3603 | * either submit or see ->cancel set. |
| 3604 | */ | 3604 | */ |
| 3605 | device_lock(bus_dev); | 3605 | nfit_device_lock(bus_dev); |
| 3606 | device_unlock(bus_dev); | 3606 | nfit_device_unlock(bus_dev); |
| 3607 | 3607 | ||
| 3608 | flush_workqueue(nfit_wq); | 3608 | flush_workqueue(nfit_wq); |
| 3609 | } | 3609 | } |
| @@ -3746,9 +3746,9 @@ EXPORT_SYMBOL_GPL(__acpi_nfit_notify); · 136 unmodified lines | |||
| 3746 | 3746 | ||
| 3747 | static void acpi_nfit_notify(struct acpi_device *adev, u32 event) | 3747 | static void acpi_nfit_notify(struct acpi_device *adev, u32 event) |
| 3748 | { | 3748 | { |
| 3749 | device_lock(&adev->dev); | 3749 | nfit_device_lock(&adev->dev); |
| 3750 | __acpi_nfit_notify(&adev->dev, adev->handle, event); | 3750 | __acpi_nfit_notify(&adev->dev, adev->handle, event); |
| 3751 | device_unlock(&adev->dev); | 3751 | nfit_device_unlock(&adev->dev); |
| 3752 | } | 3752 | } |
| 3753 | 3753 | ||
| 3754 | static const struct acpi_device_id acpi_nfit_ids[] = { | 3754 | static const struct acpi_device_id acpi_nfit_ids[] = { |
| @@ -312,6 +312,30 @@ static inline struct acpi_nfit_desc *to_acpi_desc( · 311 unmodified lines | |||
| 312 | return container_of(nd_desc, struct acpi_nfit_desc, nd_desc); | 312 | return container_of(nd_desc, struct acpi_nfit_desc, nd_desc); |
| 313 | } | 313 | } |
| 314 | 314 | ||
| 315 | #ifdef CONFIG_PROVE_LOCKING | ||
| 316 | static inline void nfit_device_lock(struct device *dev) | ||
| 317 | { | ||
| 318 | device_lock(dev); | ||
| 319 | mutex_lock(&dev->lockdep_mutex); | ||
| 320 | } | ||
| 321 | |||
| 322 | static inline void nfit_device_unlock(struct device *dev) | ||
| 323 | { | ||
| 324 | mutex_unlock(&dev->lockdep_mutex); | ||
| 325 | device_unlock(dev); | ||
| 326 | } | ||
| 327 | #else | ||
| 328 | static inline void nfit_device_lock(struct device *dev) | ||
| 329 | { | ||
| 330 | device_lock(dev); | ||
| 331 | } | ||
| 332 | |||
| 333 | static inline void nfit_device_unlock(struct device *dev) | ||
| 334 | { | ||
| 335 | device_unlock(dev); | ||
| 336 | } | ||
| 337 | #endif | ||
| 338 | |||
| 315 | const guid_t *to_nfit_uuid(enum nfit_uuids id); | 339 | const guid_t *to_nfit_uuid(enum nfit_uuids id); |
| 316 | int acpi_nfit_init(struct acpi_nfit_desc *acpi_desc, void *nfit, acpi_size sz); | 340 | int acpi_nfit_init(struct acpi_nfit_desc *acpi_desc, void *nfit, acpi_size sz); |
| 317 | void acpi_nfit_shutdown(void *data); | 341 | void acpi_nfit_shutdown(void *data); |
| @@ -2204,6 +2204,12 @@ int __init acpi_scan_init(void) · 2203 unmodified lines | |||
| 2204 | acpi_gpe_apply_masked_gpes(); | 2204 | acpi_gpe_apply_masked_gpes(); |
| 2205 | acpi_update_all_gpes(); | 2205 | acpi_update_all_gpes(); |
| 2206 | 2206 | ||
| 2207 | /* | ||
| 2208 | * Although we call __add_memory() that is documented to require the | ||
| 2209 | * device_hotplug_lock, it is not necessary here because this is an | ||
| 2210 | * early code when userspace or any other code path cannot trigger | ||
| 2211 | * hotplug/hotunplug operations. | ||
| 2212 | */ | ||
| 2207 | mutex_lock(&acpi_scan_lock); | 2213 | mutex_lock(&acpi_scan_lock); |
| 2208 | /* | 2214 | /* |
| 2209 | * Enumerate devices in the ACPI namespace. | 2215 | * Enumerate devices in the ACPI namespace. |
| @@ -2988,7 +2988,7 @@ static void binder_transaction(struct binder_proc *proc, · 2987 unmodified lines | |||
| 2988 | else | 2988 | else |
| 2989 | return_error = BR_DEAD_REPLY; | 2989 | return_error = BR_DEAD_REPLY; |
| 2990 | mutex_unlock(&context->context_mgr_node_lock); | 2990 | mutex_unlock(&context->context_mgr_node_lock); |
| 2991 | if (target_node && target_proc == proc) { | 2991 | if (target_node && target_proc->pid == proc->pid) { |
| 2992 | binder_user_error("%d:%d got transaction to context manager from process owning it\n", | 2992 | binder_user_error("%d:%d got transaction to context manager from process owning it\n", |
| 2993 | proc->pid, thread->pid); | 2993 | proc->pid, thread->pid); |
| 2994 | return_error = BR_FAILED_REPLY; | 2994 | return_error = BR_FAILED_REPLY; |
| @@ -3239,7 +3239,8 @@ static void binder_transaction(struct binder_proc *proc, · 244 unmodified lines | |||
| 3239 | buffer_offset = off_start_offset; | 3239 | buffer_offset = off_start_offset; |
| 3240 | off_end_offset = off_start_offset + tr->offsets_size; | 3240 | off_end_offset = off_start_offset + tr->offsets_size; |
| 3241 | sg_buf_offset = ALIGN(off_end_offset, sizeof(void *)); | 3241 | sg_buf_offset = ALIGN(off_end_offset, sizeof(void *)); |
| 3242 | sg_buf_end_offset = sg_buf_offset + extra_buffers_size; | 3242 | sg_buf_end_offset = sg_buf_offset + extra_buffers_size - |
| 3243 | ALIGN(secctx_sz, sizeof(u64)); | ||
| 3243 | off_min = 0; | 3244 | off_min = 0; |
| 3244 | for (buffer_offset = off_start_offset; buffer_offset < off_end_offset; | 3245 | for (buffer_offset = off_start_offset; buffer_offset < off_end_offset; |
| 3245 | buffer_offset += sizeof(binder_size_t)) { | 3246 | buffer_offset += sizeof(binder_size_t)) { |
| @@ -338,6 +338,9 @@ static int ahci_platform_get_phy(struct ahci_host_priv *hpriv, u32 port, · 337 unmodified lines | |||
| 338 | hpriv->phys[port] = NULL; | 338 | hpriv->phys[port] = NULL; |
| 339 | rc = 0; | 339 | rc = 0; |
| 340 | break; | 340 | break; |
| 341 | case -EPROBE_DEFER: | ||
| 342 | /* Do not complain yet */ | ||
| 343 | break; | ||
| 341 | 344 | ||
| 342 | default: | 345 | default: |
| 343 | dev_err(dev, | 346 | dev_err(dev, |
| @@ -408,7 +411,6 @@ struct ahci_host_priv *ahci_platform_get_resources(struct platform_device *pdev, · 64 unmodified lines | |||
| 408 | hpriv->mmio = devm_ioremap_resource(dev, | 411 | hpriv->mmio = devm_ioremap_resource(dev, |
| 409 | platform_get_resource(pdev, IORESOURCE_MEM, 0)); | 412 | platform_get_resource(pdev, IORESOURCE_MEM, 0)); |
| 410 | if (IS_ERR(hpriv->mmio)) { | 413 | if (IS_ERR(hpriv->mmio)) { |
| 411 | dev_err(dev, "no mmio space\n"); | ||
| 412 | rc = PTR_ERR(hpriv->mmio); | 414 | rc = PTR_ERR(hpriv->mmio); |
| 413 | goto err_out; | 415 | goto err_out; |
| 414 | } | 416 | } |
| @@ -1786,6 +1786,21 @@ nothing_to_do: · 1785 unmodified lines | |||
| 1786 | return 1; | 1786 | return 1; |
| 1787 | } | 1787 | } |
| 1788 | 1788 | ||
| 1789 | static bool ata_check_nblocks(struct scsi_cmnd *scmd, u32 n_blocks) | ||
| 1790 | { | ||
| 1791 | struct request *rq = scmd->request; | ||
| 1792 | u32 req_blocks; | ||
| 1793 | |||
| 1794 | if (!blk_rq_is_passthrough(rq)) | ||
| 1795 | return true; | ||
| 1796 | |||
| 1797 | req_blocks = blk_rq_bytes(rq) / scmd->device->sector_size; | ||
| 1798 | if (n_blocks > req_blocks) | ||
| 1799 | return false; | ||
| 1800 | |||
| 1801 | return true; | ||
| 1802 | } | ||
| 1803 | |||
| 1789 | /** | 1804 | /** |
| 1790 | * ata_scsi_rw_xlat - Translate SCSI r/w command into an ATA one | 1805 | * ata_scsi_rw_xlat - Translate SCSI r/w command into an ATA one |
| 1791 | * @qc: Storage for translated ATA taskfile | 1806 | * @qc: Storage for translated ATA taskfile |
| @@ -1830,6 +1845,8 @@ static unsigned int ata_scsi_rw_xlat(struct ata_queued_cmd *qc) · 38 unmodified lines | |||
| 1830 | scsi_10_lba_len(cdb, &block, &n_block); | 1845 | scsi_10_lba_len(cdb, &block, &n_block); |
| 1831 | if (cdb[1] & (1 << 3)) | 1846 | if (cdb[1] & (1 << 3)) |
| 1832 | tf_flags |= ATA_TFLAG_FUA; | 1847 | tf_flags |= ATA_TFLAG_FUA; |
| 1848 | if (!ata_check_nblocks(scmd, n_block)) | ||
| 1849 | goto invalid_fld; | ||
| 1833 | break; | 1850 | break; |
| 1834 | case READ_6: | 1851 | case READ_6: |
| 1835 | case WRITE_6: | 1852 | case WRITE_6: |
| @@ -1844,6 +1861,8 @@ static unsigned int ata_scsi_rw_xlat(struct ata_queued_cmd *qc) · 8 unmodified lines | |||
| 1844 | */ | 1861 | */ |
| 1845 | if (!n_block) | 1862 | if (!n_block) |
| 1846 | n_block = 256; | 1863 | n_block = 256; |
| 1864 | if (!ata_check_nblocks(scmd, n_block)) | ||
| 1865 | goto invalid_fld; | ||
| 1847 | break; | 1866 | break; |
| 1848 | case READ_16: | 1867 | case READ_16: |
| 1849 | case WRITE_16: | 1868 | case WRITE_16: |
| @@ -1854,6 +1873,8 @@ static unsigned int ata_scsi_rw_xlat(struct ata_queued_cmd *qc) · 4 unmodified lines | |||
| 1854 | scsi_16_lba_len(cdb, &block, &n_block); | 1873 | scsi_16_lba_len(cdb, &block, &n_block); |
| 1855 | if (cdb[1] & (1 << 3)) | 1874 | if (cdb[1] & (1 << 3)) |
| 1856 | tf_flags |= ATA_TFLAG_FUA; | 1875 | tf_flags |= ATA_TFLAG_FUA; |
| 1876 | if (!ata_check_nblocks(scmd, n_block)) | ||
| 1877 | goto invalid_fld; | ||
| 1857 | break; | 1878 | break; |
| 1858 | default: | 1879 | default: |
| 1859 | DPRINTK("no-byte command\n"); | 1880 | DPRINTK("no-byte command\n"); |
| @@ -658,6 +658,10 @@ static void ata_pio_sector(struct ata_queued_cmd *qc) · 657 unmodified lines | |||
| 658 | unsigned int offset; | 658 | unsigned int offset; |
| 659 | unsigned char *buf; | 659 | unsigned char *buf; |
| 660 | 660 | ||
| 661 | if (!qc->cursg) { | ||
| 662 | qc->curbytes = qc->nbytes; | ||
| 663 | return; | ||
| 664 | } | ||
| 661 | if (qc->curbytes == qc->nbytes - qc->sect_size) | 665 | if (qc->curbytes == qc->nbytes - qc->sect_size) |
| 662 | ap->hsm_task_state = HSM_ST_LAST; | 666 | ap->hsm_task_state = HSM_ST_LAST; |
| 663 | 667 | ||
| @@ -683,6 +687,8 @@ static void ata_pio_sector(struct ata_queued_cmd *qc) · 19 unmodified lines | |||
| 683 | 687 | ||
| 684 | if (qc->cursg_ofs == qc->cursg->length) { | 688 | if (qc->cursg_ofs == qc->cursg->length) { |
| 685 | qc->cursg = sg_next(qc->cursg); | 689 | qc->cursg = sg_next(qc->cursg); |
| 690 | if (!qc->cursg) | ||
| 691 | ap->hsm_task_state = HSM_ST_LAST; | ||
| 686 | qc->cursg_ofs = 0; | 692 | qc->cursg_ofs = 0; |
| 687 | } | 693 | } |
| 688 | } | 694 | } |
| @@ -56,7 +56,7 @@ static enum odd_mech_type zpodd_get_mech_type(struct ata_device *dev) · 55 unmodified lines | |||
| 56 | unsigned int ret; | 56 | unsigned int ret; |
| 57 | struct rm_feature_desc *desc; | 57 | struct rm_feature_desc *desc; |
| 58 | struct ata_taskfile tf; | 58 | struct ata_taskfile tf; |
| 59 | static const char cdb[] = { GPCMD_GET_CONFIGURATION, | 59 | static const char cdb[ATAPI_CDB_LEN] = { GPCMD_GET_CONFIGURATION, |
| 60 | 2, /* only 1 feature descriptor requested */ | 60 | 2, /* only 1 feature descriptor requested */ |
| 61 | 0, 3, /* 3, removable medium feature */ | 61 | 0, 3, /* 3, removable medium feature */ |
| 62 | 0, 0, 0,/* reserved */ | 62 | 0, 0, 0,/* reserved */ |
| @@ -158,7 +158,6 @@ static int rb532_pata_driver_probe(struct platform_device *pdev) · 157 unmodified lines | |||
| 158 | static int rb532_pata_driver_remove(struct platform_device *pdev) | 158 | static int rb532_pata_driver_remove(struct platform_device *pdev) |
| 159 | { | 159 | { |
| 160 | struct ata_host *ah = platform_get_drvdata(pdev); | 160 | struct ata_host *ah = platform_get_drvdata(pdev); |
| 161 | struct rb532_cf_info *info = ah->private_data; | ||
| 162 | 161 | ||
| 163 | ata_host_detach(ah); | 162 | ata_host_detach(ah); |
| 164 | 163 | ||
| @@ -63,6 +63,7 @@ · 62 unmodified lines | |||
| 63 | #include <asm/byteorder.h> | 63 | #include <asm/byteorder.h> |
| 64 | #include <linux/vmalloc.h> | 64 | #include <linux/vmalloc.h> |
| 65 | #include <linux/jiffies.h> | 65 | #include <linux/jiffies.h> |
| 66 | #include <linux/nospec.h> | ||
| 66 | #include "iphase.h" | 67 | #include "iphase.h" |
| 67 | #include "suni.h" | 68 | #include "suni.h" |
| 68 | #define swap_byte_order(x) (((x & 0xff) << 8) | ((x & 0xff00) >> 8)) | 69 | #define swap_byte_order(x) (((x & 0xff) << 8) | ((x & 0xff00) >> 8)) |
| @@ -2760,8 +2761,11 @@ static int ia_ioctl(struct atm_dev *dev, unsigned int cmd, void __user *arg) · 2691 unmodified lines | |||
| 2760 | } | 2761 | } |
| 2761 | if (copy_from_user(&ia_cmds, arg, sizeof ia_cmds)) return -EFAULT; | 2762 | if (copy_from_user(&ia_cmds, arg, sizeof ia_cmds)) return -EFAULT; |
| 2762 | board = ia_cmds.status; | 2763 | board = ia_cmds.status; |
| 2763 | if ((board < 0) || (board > iadev_count)) | 2764 | |
| 2764 | board = 0; | 2765 | if ((board < 0) || (board > iadev_count)) |
| 2766 | board = 0; | ||
| 2767 | board = array_index_nospec(board, iadev_count + 1); | ||
| 2768 | |||
| 2765 | iadev = ia_dev[board]; | 2769 | iadev = ia_dev[board]; |
| 2766 | switch (ia_cmds.cmd) { | 2770 | switch (ia_cmds.cmd) { |
| 2767 | case MEMDUMP: | 2771 | case MEMDUMP: |
| @@ -448,6 +448,11 @@ config PANEL_BOOT_MESSAGE · 447 unmodified lines | |||
| 448 | choice | 448 | choice |
| 449 | prompt "Backlight initial state" | 449 | prompt "Backlight initial state" |
| 450 | default CHARLCD_BL_FLASH | 450 | default CHARLCD_BL_FLASH |
| 451 | ---help--- | ||
| 452 | Select the initial backlight state on boot or module load. | ||
| 453 | |||
| 454 | Previously, there was no option for this: the backlight flashed | ||
| 455 | briefly on init. Now you can also turn it off/on. | ||
| 451 | 456 | ||
| 452 | config CHARLCD_BL_OFF | 457 | config CHARLCD_BL_OFF |
| 453 | bool "Off" | 458 | bool "Off" |
| @@ -20,7 +20,7 @@ · 19 unmodified lines | |||
| 20 | 20 | ||
| 21 | #include <generated/utsrelease.h> | 21 | #include <generated/utsrelease.h> |
| 22 | 22 | ||
| 23 | #include <misc/charlcd.h> | 23 | #include "charlcd.h" |
| 24 | 24 | ||
| 25 | #define LCD_MINOR 156 | 25 | #define LCD_MINOR 156 |
| 26 | 26 | ||
| @@ -6,6 +6,9 @@ · 5 unmodified lines | |||
| 6 | * Copyright (C) 2016-2017 Glider bvba | 6 | * Copyright (C) 2016-2017 Glider bvba |
| 7 | */ | 7 | */ |
| 8 | 8 | ||
| 9 | #ifndef _CHARLCD_H | ||
| 10 | #define _CHARLCD_H | ||
| 11 | |||
| 9 | struct charlcd { | 12 | struct charlcd { |
| 10 | const struct charlcd_ops *ops; | 13 | const struct charlcd_ops *ops; |
| 11 | const unsigned char *char_conv; /* Optional */ | 14 | const unsigned char *char_conv; /* Optional */ |
| @@ -37,3 +40,5 @@ int charlcd_register(struct charlcd *lcd); · 25 unmodified lines | |||
| 37 | int charlcd_unregister(struct charlcd *lcd); | 40 | int charlcd_unregister(struct charlcd *lcd); |
| 38 | 41 | ||
| 39 | void charlcd_poke(struct charlcd *lcd); | 42 | void charlcd_poke(struct charlcd *lcd); |
| 43 | |||
| 44 | #endif /* CHARLCD_H */ | ||
| @@ -14,8 +14,7 @@ · 13 unmodified lines | |||
| 14 | #include <linux/property.h> | 14 | #include <linux/property.h> |
| 15 | #include <linux/slab.h> | 15 | #include <linux/slab.h> |
| 16 | 16 | ||
| 17 | #include <misc/charlcd.h> | 17 | #include "charlcd.h" |
| 18 | |||
| 19 | 18 | ||
| 20 | enum hd44780_pin { | 19 | enum hd44780_pin { |
| 21 | /* Order does matter due to writing to GPIO array subsets! */ | 20 | /* Order does matter due to writing to GPIO array subsets! */ |
| @@ -55,7 +55,7 @@ · 54 unmodified lines | |||
| 55 | #include <linux/io.h> | 55 | #include <linux/io.h> |
| 56 | #include <linux/uaccess.h> | 56 | #include <linux/uaccess.h> |
| 57 | 57 | ||
| 58 | #include <misc/charlcd.h> | 58 | #include "charlcd.h" |
| 59 | 59 | ||
| 60 | #define KEYPAD_MINOR 185 | 60 | #define KEYPAD_MINOR 185 |
| 61 | 61 | ||
| @@ -1617,6 +1617,8 @@ static void panel_attach(struct parport *port) · 1555 unmodified lines | |||
| 1617 | return; | 1617 | return; |
| 1618 | 1618 | ||
| 1619 | err_lcd_unreg: | 1619 | err_lcd_unreg: |
| 1620 | if (scan_timer.function) | ||
| 1621 | del_timer_sync(&scan_timer); | ||
| 1620 | if (lcd.enabled) | 1622 | if (lcd.enabled) |
| 1621 | charlcd_unregister(lcd.charlcd); | 1623 | charlcd_unregister(lcd.charlcd); |
| 1622 | err_unreg_device: | 1624 | err_unreg_device: |
| @@ -1663,6 +1663,9 @@ void device_initialize(struct device *dev) · 1662 unmodified lines | |||
| 1663 | kobject_init(&dev->kobj, &device_ktype); | 1663 | kobject_init(&dev->kobj, &device_ktype); |
| 1664 | INIT_LIST_HEAD(&dev->dma_pools); | 1664 | INIT_LIST_HEAD(&dev->dma_pools); |
| 1665 | mutex_init(&dev->mutex); | 1665 | mutex_init(&dev->mutex); |
| 1666 | #ifdef CONFIG_PROVE_LOCKING | ||
| 1667 | mutex_init(&dev->lockdep_mutex); | ||
| 1668 | #endif | ||
| 1666 | lockdep_set_novalidate_class(&dev->mutex); | 1669 | lockdep_set_novalidate_class(&dev->mutex); |
| 1667 | spin_lock_init(&dev->devres_lock); | 1670 | spin_lock_init(&dev->devres_lock); |
| 1668 | INIT_LIST_HEAD(&dev->devres_head); | 1671 | INIT_LIST_HEAD(&dev->devres_head); |
| @@ -1820,12 +1823,63 @@ static inline struct kobject *get_glue_dir(struct device *dev) · 151 unmodified lines | |||
| 1820 | */ | 1823 | */ |
| 1821 | static void cleanup_glue_dir(struct device *dev, struct kobject *glue_dir) | 1824 | static void cleanup_glue_dir(struct device *dev, struct kobject *glue_dir) |
| 1822 | { | 1825 | { |
| 1826 | unsigned int ref; | ||
| 1827 | |||
| 1823 | /* see if we live in a "glue" directory */ | 1828 | /* see if we live in a "glue" directory */ |
| 1824 | if (!live_in_glue_dir(glue_dir, dev)) | 1829 | if (!live_in_glue_dir(glue_dir, dev)) |
| 1825 | return; | 1830 | return; |
| 1826 | 1831 | ||
| 1827 | mutex_lock(&gdp_mutex); | 1832 | mutex_lock(&gdp_mutex); |
| 1828 | if (!kobject_has_children(glue_dir)) | 1833 | /** |
| 1834 | * There is a race condition between removing glue directory | ||
| 1835 | * and adding a new device under the glue directory. | ||
| 1836 | * | ||
| 1837 | * CPU1: CPU2: | ||
| 1838 | * | ||
| 1839 | * device_add() | ||
| 1840 | * get_device_parent() | ||
| 1841 | * class_dir_create_and_add() | ||
| 1842 | * kobject_add_internal() | ||
| 1843 | * create_dir() // create glue_dir | ||
| 1844 | * | ||
| 1845 | * device_add() | ||
| 1846 | * get_device_parent() | ||
| 1847 | * kobject_get() // get glue_dir | ||
| 1848 | * | ||
| 1849 | * device_del() | ||
| 1850 | * cleanup_glue_dir() | ||
| 1851 | * kobject_del(glue_dir) | ||
| 1852 | * | ||
| 1853 | * kobject_add() | ||
| 1854 | * kobject_add_internal() | ||
| 1855 | * create_dir() // in glue_dir | ||
| 1856 | * sysfs_create_dir_ns() | ||
| 1857 | * kernfs_create_dir_ns(sd) | ||
| 1858 | * | ||
| 1859 | * sysfs_remove_dir() // glue_dir->sd=NULL | ||
| 1860 | * sysfs_put() // free glue_dir->sd | ||
| 1861 | * | ||
| 1862 | * // sd is freed | ||
| 1863 | * kernfs_new_node(sd) | ||
| 1864 | * kernfs_get(glue_dir) | ||
| 1865 | * kernfs_add_one() | ||
| 1866 | * kernfs_put() | ||
| 1867 | * | ||
| 1868 | * Before CPU1 remove last child device under glue dir, if CPU2 add | ||
| 1869 | * a new device under glue dir, the glue_dir kobject reference count | ||
| 1870 | * will be increase to 2 in kobject_get(k). And CPU2 has been called | ||
| 1871 | * kernfs_create_dir_ns(). Meanwhile, CPU1 call sysfs_remove_dir() | ||
| 1872 | * and sysfs_put(). This result in glue_dir->sd is freed. | ||
| 1873 | * | ||
| 1874 | * Then the CPU2 will see a stale "empty" but still potentially used | ||
| 1875 | * glue dir around in kernfs_new_node(). | ||
| 1876 | * | ||
| 1877 | * In order to avoid this happening, we also should make sure that | ||
| 1878 | * kernfs_node for glue_dir is released in CPU1 only when refcount | ||
| 1879 | * for glue_dir kobj is 1. | ||
| 1880 | */ | ||
| 1881 | ref = kref_read(&glue_dir->kref); | ||
| 1882 | if (!kobject_has_children(glue_dir) && !--ref) | ||
| 1829 | kobject_del(glue_dir); | 1883 | kobject_del(glue_dir); |
| 1830 | kobject_put(glue_dir); | 1884 | kobject_put(glue_dir); |
| 1831 | mutex_unlock(&gdp_mutex); | 1885 | mutex_unlock(&gdp_mutex); |
| @@ -2211,6 +2265,24 @@ void put_device(struct device *dev) · 379 unmodified lines | |||
| 2211 | } | 2265 | } |
| 2212 | EXPORT_SYMBOL_GPL(put_device); | 2266 | EXPORT_SYMBOL_GPL(put_device); |
| 2213 | 2267 | ||
| 2268 | bool kill_device(struct device *dev) | ||
| 2269 | { | ||
| 2270 | /* | ||
| 2271 | * Require the device lock and set the "dead" flag to guarantee that | ||
| 2272 | * the update behavior is consistent with the other bitfields near | ||
| 2273 | * it and that we cannot have an asynchronous probe routine trying | ||
| 2274 | * to run while we are tearing out the bus/class/sysfs from | ||
| 2275 | * underneath the device. | ||
| 2276 | */ | ||
| 2277 | lockdep_assert_held(&dev->mutex); | ||
| 2278 | |||
| 2279 | if (dev->p->dead) | ||
| 2280 | return false; | ||
| 2281 | dev->p->dead = true; | ||
| 2282 | return true; | ||
| 2283 | } | ||
| 2284 | EXPORT_SYMBOL_GPL(kill_device); | ||
| 2285 | |||
| 2214 | /** | 2286 | /** |
| 2215 | * device_del - delete device from system. | 2287 | * device_del - delete device from system. |
| 2216 | * @dev: device. | 2288 | * @dev: device. |
| @@ -2230,15 +2302,8 @@ void device_del(struct device *dev) · 13 unmodified lines | |||
| 2230 | struct kobject *glue_dir = NULL; | 2302 | struct kobject *glue_dir = NULL; |
| 2231 | struct class_interface *class_intf; | 2303 | struct class_interface *class_intf; |
| 2232 | 2304 | ||
| 2233 | /* | ||
| 2234 | * Hold the device lock and set the "dead" flag to guarantee that | ||
| 2235 | * the update behavior is consistent with the other bitfields near | ||
| 2236 | * it and that we cannot have an asynchronous probe routine trying | ||
| 2237 | * to run while we are tearing out the bus/class/sysfs from | ||
| 2238 | * underneath the device. | ||
| 2239 | */ | ||
| 2240 | device_lock(dev); | 2305 | device_lock(dev); |
| 2241 | dev->p->dead = true; | 2306 | kill_device(dev); |
| 2242 | device_unlock(dev); | 2307 | device_unlock(dev); |
| 2243 | 2308 | ||
| 2244 | /* Notify clients of device removal. This call must come | 2309 | /* Notify clients of device removal. This call must come |
| @@ -141,8 +141,8 @@ int fw_grow_paged_buf(struct fw_priv *fw_priv, int pages_needed); · 140 unmodified lines | |||
| 141 | int fw_map_paged_buf(struct fw_priv *fw_priv); | 141 | int fw_map_paged_buf(struct fw_priv *fw_priv); |
| 142 | #else | 142 | #else |
| 143 | static inline void fw_free_paged_buf(struct fw_priv *fw_priv) {} | 143 | static inline void fw_free_paged_buf(struct fw_priv *fw_priv) {} |
| 144 | int fw_grow_paged_buf(struct fw_priv *fw_priv, int pages_needed) { return -ENXIO; } | 144 | static inline int fw_grow_paged_buf(struct fw_priv *fw_priv, int pages_needed) { return -ENXIO; } |
| 145 | int fw_map_paged_buf(struct fw_priv *fw_priv) { return -ENXIO; } | 145 | static inline int fw_map_paged_buf(struct fw_priv *fw_priv) { return -ENXIO; } |
| 146 | #endif | 146 | #endif |
| 147 | 147 | ||
| 148 | #endif /* __FIRMWARE_LOADER_H */ | 148 | #endif /* __FIRMWARE_LOADER_H */ |
| @@ -157,8 +157,13 @@ int platform_get_irq(struct platform_device *dev, unsigned int num) · 156 unmodified lines | |||
| 157 | * the device will only expose one IRQ, and this fallback | 157 | * the device will only expose one IRQ, and this fallback |
| 158 | * allows a common code path across either kind of resource. | 158 | * allows a common code path across either kind of resource. |
| 159 | */ | 159 | */ |
| 160 | if (num == 0 && has_acpi_companion(&dev->dev)) | 160 | if (num == 0 && has_acpi_companion(&dev->dev)) { |
| 161 | return acpi_dev_gpio_irq_get(ACPI_COMPANION(&dev->dev), num); | 161 | int ret = acpi_dev_gpio_irq_get(ACPI_COMPANION(&dev->dev), num); |
| 162 | |||
| 163 | /* Our callers expect -ENXIO for missing IRQs. */ | ||
| 164 | if (ret >= 0 || ret == -EPROBE_DEFER) | ||
| 165 | return ret; | ||
| 166 | } | ||
| 162 | 167 | ||
| 163 | return -ENXIO; | 168 | return -ENXIO; |
| 164 | #endif | 169 | #endif |
| @@ -44,7 +44,7 @@ config REGMAP_IRQ · 43 unmodified lines | |||
| 44 | 44 | ||
| 45 | config REGMAP_SOUNDWIRE | 45 | config REGMAP_SOUNDWIRE |
| 46 | tristate | 46 | tristate |
| 47 | depends on SOUNDWIRE_BUS | 47 | depends on SOUNDWIRE |
| 48 | 48 | ||
| 49 | config REGMAP_SCCB | 49 | config REGMAP_SCCB |
| 50 | tristate | 50 | tristate |
| @@ -323,10 +323,14 @@ flush(const char __user *str, size_t cnt, int exiting) · 322 unmodified lines | |||
| 323 | } | 323 | } |
| 324 | 324 | ||
| 325 | flush_scheduled_work(); | 325 | flush_scheduled_work(); |
| 326 | /* pass one: without sleeping, do aoedev_downdev */ | 326 | /* pass one: do aoedev_downdev, which might sleep */ |
| 327 | restart1: | ||
| 327 | spin_lock_irqsave(&devlist_lock, flags); | 328 | spin_lock_irqsave(&devlist_lock, flags); |
| 328 | for (d = devlist; d; d = d->next) { | 329 | for (d = devlist; d; d = d->next) { |
| 329 | spin_lock(&d->lock); | 330 | spin_lock(&d->lock); |
| 331 | if (d->flags & DEVFL_TKILL) | ||
| 332 | goto cont; | ||
| 333 | |||
| 330 | if (exiting) { | 334 | if (exiting) { |
| 331 | /* unconditionally take each device down */ | 335 | /* unconditionally take each device down */ |
| 332 | } else if (specified) { | 336 | } else if (specified) { |
| @@ -338,8 +342,11 @@ flush(const char __user *str, size_t cnt, int exiting) · 5 unmodified lines | |||
| 338 | || d->ref) | 342 | || d->ref) |
| 339 | goto cont; | 343 | goto cont; |
| 340 | 344 | ||
| 345 | spin_unlock(&d->lock); | ||
| 346 | spin_unlock_irqrestore(&devlist_lock, flags); | ||
| 341 | aoedev_downdev(d); | 347 | aoedev_downdev(d); |
| 342 | d->flags |= DEVFL_TKILL; | 348 | d->flags |= DEVFL_TKILL; |
| 349 | goto restart1; | ||
| 343 | cont: | 350 | cont: |
| 344 | spin_unlock(&d->lock); | 351 | spin_unlock(&d->lock); |
| 345 | } | 352 | } |
| @@ -348,7 +355,7 @@ cont: · 2 unmodified lines | |||
| 348 | /* pass two: call freedev, which might sleep, | 355 | /* pass two: call freedev, which might sleep, |
| 349 | * for aoedevs marked with DEVFL_TKILL | 356 | * for aoedevs marked with DEVFL_TKILL |
| 350 | */ | 357 | */ |
| 351 | restart: | 358 | restart2: |
| 352 | spin_lock_irqsave(&devlist_lock, flags); | 359 | spin_lock_irqsave(&devlist_lock, flags); |
| 353 | for (d = devlist; d; d = d->next) { | 360 | for (d = devlist; d; d = d->next) { |
| 354 | spin_lock(&d->lock); | 361 | spin_lock(&d->lock); |
| @@ -357,7 +364,7 @@ restart: · 2 unmodified lines | |||
| 357 | spin_unlock(&d->lock); | 364 | spin_unlock(&d->lock); |
| 358 | spin_unlock_irqrestore(&devlist_lock, flags); | 365 | spin_unlock_irqrestore(&devlist_lock, flags); |
| 359 | freedev(d); | 366 | freedev(d); |
| 360 | goto restart; | 367 | goto restart2; |
| 361 | } | 368 | } |
| 362 | spin_unlock(&d->lock); | 369 | spin_unlock(&d->lock); |
| 363 | } | 370 | } |
| @@ -1726,6 +1726,7 @@ static int fd_locked_ioctl(struct block_device *bdev, fmode_t mode, · 1725 unmodified lines | |||
| 1726 | /* MSch: invalidate default_params */ | 1726 | /* MSch: invalidate default_params */ |
| 1727 | default_params[drive].blocks = 0; | 1727 | default_params[drive].blocks = 0; |
| 1728 | set_capacity(floppy->disk, MAX_DISK_SIZE * 2); | 1728 | set_capacity(floppy->disk, MAX_DISK_SIZE * 2); |
| 1729 | /* Fall through */ | ||
| 1729 | case FDFMTEND: | 1730 | case FDFMTEND: |
| 1730 | case FDFLUSH: | 1731 | case FDFLUSH: |
| 1731 | /* invalidate the buffer track to force a reread */ | 1732 | /* invalidate the buffer track to force a reread */ |
| @@ -5417,7 +5417,7 @@ static int drbd_do_auth(struct drbd_connection *connection) · 5416 unmodified lines | |||
| 5417 | unsigned int key_len; | 5417 | unsigned int key_len; |
| 5418 | char secret[SHARED_SECRET_MAX]; /* 64 byte */ | 5418 | char secret[SHARED_SECRET_MAX]; /* 64 byte */ |
| 5419 | unsigned int resp_size; | 5419 | unsigned int resp_size; |
| 5420 | SHASH_DESC_ON_STACK(desc, connection->cram_hmac_tfm); | 5420 | struct shash_desc *desc; |
| 5421 | struct packet_info pi; | 5421 | struct packet_info pi; |
| 5422 | struct net_conf *nc; | 5422 | struct net_conf *nc; |
| 5423 | int err, rv; | 5423 | int err, rv; |
| @@ -5430,6 +5430,13 @@ static int drbd_do_auth(struct drbd_connection *connection) · 6 unmodified lines | |||
| 5430 | memcpy(secret, nc->shared_secret, key_len); | 5430 | memcpy(secret, nc->shared_secret, key_len); |
| 5431 | rcu_read_unlock(); | 5431 | rcu_read_unlock(); |
| 5432 | 5432 | ||
| 5433 | desc = kmalloc(sizeof(struct shash_desc) + | ||
| 5434 | crypto_shash_descsize(connection->cram_hmac_tfm), | ||
| 5435 | GFP_KERNEL); | ||
| 5436 | if (!desc) { | ||
| 5437 | rv = -1; | ||
| 5438 | goto fail; | ||
| 5439 | } | ||
| 5433 | desc->tfm = connection->cram_hmac_tfm; | 5440 | desc->tfm = connection->cram_hmac_tfm; |
| 5434 | 5441 | ||
| 5435 | rv = crypto_shash_setkey(connection->cram_hmac_tfm, (u8 *)secret, key_len); | 5442 | rv = crypto_shash_setkey(connection->cram_hmac_tfm, (u8 *)secret, key_len); |
| @@ -5571,7 +5578,10 @@ static int drbd_do_auth(struct drbd_connection *connection) · 135 unmodified lines | |||
| 5571 | kfree(peers_ch); | 5578 | kfree(peers_ch); |
| 5572 | kfree(response); | 5579 | kfree(response); |
| 5573 | kfree(right_response); | 5580 | kfree(right_response); |
| 5574 | shash_desc_zero(desc); | 5581 | if (desc) { |
| 5582 | shash_desc_zero(desc); | ||
| 5583 | kfree(desc); | ||
| 5584 | } | ||
| 5575 | 5585 | ||
| 5576 | return rv; | 5586 | return rv; |
| 5577 | } | 5587 | } |
| @@ -885,7 +885,7 @@ static void loop_unprepare_queue(struct loop_device *lo) · 884 unmodified lines | |||
| 885 | 885 | ||
| 886 | static int loop_kthread_worker_fn(void *worker_ptr) | 886 | static int loop_kthread_worker_fn(void *worker_ptr) |
| 887 | { | 887 | { |
| 888 | current->flags |= PF_LESS_THROTTLE; | 888 | current->flags |= PF_LESS_THROTTLE | PF_MEMALLOC_NOIO; |
| 889 | return kthread_worker_fn(worker_ptr); | 889 | return kthread_worker_fn(worker_ptr); |
| 890 | } | 890 | } |
| 891 | 891 | ||
| @@ -924,6 +924,7 @@ static int loop_set_fd(struct loop_device *lo, fmode_t mode, · 32 unmodified lines | |||
| 924 | struct file *file; | 924 | struct file *file; |
| 925 | struct inode *inode; | 925 | struct inode *inode; |
| 926 | struct address_space *mapping; | 926 | struct address_space *mapping; |
| 927 | struct block_device *claimed_bdev = NULL; | ||
| 927 | int lo_flags = 0; | 928 | int lo_flags = 0; |
| 928 | int error; | 929 | int error; |
| 929 | loff_t size; | 930 | loff_t size; |
| @@ -942,10 +943,11 @@ static int loop_set_fd(struct loop_device *lo, fmode_t mode, · 12 unmodified lines | |||
| 942 | * here to avoid changing device under exclusive owner. | 943 | * here to avoid changing device under exclusive owner. |
| 943 | */ | 944 | */ |
| 944 | if (!(mode & FMODE_EXCL)) { | 945 | if (!(mode & FMODE_EXCL)) { |
| 945 | bdgrab(bdev); | 946 | claimed_bdev = bd_start_claiming(bdev, loop_set_fd); |
| 946 | error = blkdev_get(bdev, mode | FMODE_EXCL, loop_set_fd); | 947 | if (IS_ERR(claimed_bdev)) { |
| 947 | if (error) | 948 | error = PTR_ERR(claimed_bdev); |
| 948 | goto out_putf; | 949 | goto out_putf; |
| 950 | } | ||
| 949 | } | 951 | } |
| 950 | 952 | ||
| 951 | error = mutex_lock_killable(&loop_ctl_mutex); | 953 | error = mutex_lock_killable(&loop_ctl_mutex); |
| @@ -1015,15 +1017,15 @@ static int loop_set_fd(struct loop_device *lo, fmode_t mode, · 63 unmodified lines | |||
| 1015 | mutex_unlock(&loop_ctl_mutex); | 1017 | mutex_unlock(&loop_ctl_mutex); |
| 1016 | if (partscan) | 1018 | if (partscan) |
| 1017 | loop_reread_partitions(lo, bdev); | 1019 | loop_reread_partitions(lo, bdev); |
| 1018 | if (!(mode & FMODE_EXCL)) | 1020 | if (claimed_bdev) |
| 1019 | blkdev_put(bdev, mode | FMODE_EXCL); | 1021 | bd_abort_claiming(bdev, claimed_bdev, loop_set_fd); |
| 1020 | return 0; | 1022 | return 0; |
| 1021 | 1023 | ||
| 1022 | out_unlock: | 1024 | out_unlock: |
| 1023 | mutex_unlock(&loop_ctl_mutex); | 1025 | mutex_unlock(&loop_ctl_mutex); |
| 1024 | out_bdev: | 1026 | out_bdev: |
| 1025 | if (!(mode & FMODE_EXCL)) | 1027 | if (claimed_bdev) |
| 1026 | blkdev_put(bdev, mode | FMODE_EXCL); | 1028 | bd_abort_claiming(bdev, claimed_bdev, loop_set_fd); |
| 1027 | out_putf: | 1029 | out_putf: |
| 1028 | fput(file); | 1030 | fput(file); |
| 1029 | out: | 1031 | out: |
| @@ -1231,7 +1231,7 @@ static void nbd_clear_sock_ioctl(struct nbd_device *nbd, · 1230 unmodified lines | |||
| 1231 | struct block_device *bdev) | 1231 | struct block_device *bdev) |
| 1232 | { | 1232 | { |
| 1233 | sock_shutdown(nbd); | 1233 | sock_shutdown(nbd); |
| 1234 | kill_bdev(bdev); | 1234 | __invalidate_device(bdev, true); |
| 1235 | nbd_bdev_reset(bdev); | 1235 | nbd_bdev_reset(bdev); |
| 1236 | if (test_and_clear_bit(NBD_HAS_CONFIG_REF, | 1236 | if (test_and_clear_bit(NBD_HAS_CONFIG_REF, |
| 1237 | &nbd->config->runtime_flags)) | 1237 | &nbd->config->runtime_flags)) |
| @@ -965,6 +965,7 @@ static int read_per_ring_refs(struct xen_blkif_ring *ring, const char *dir) · 964 unmodified lines | |||
| 965 | } | 965 | } |
| 966 | } | 966 | } |
| 967 | 967 | ||
| 968 | err = -ENOMEM; | ||
| 968 | for (i = 0; i < nr_grefs * XEN_BLKIF_REQS_PER_PAGE; i++) { | 969 | for (i = 0; i < nr_grefs * XEN_BLKIF_REQS_PER_PAGE; i++) { |
| 969 | req = kzalloc(sizeof(*req), GFP_KERNEL); | 970 | req = kzalloc(sizeof(*req), GFP_KERNEL); |
| 970 | if (!req) | 971 | if (!req) |
| @@ -987,7 +988,7 @@ static int read_per_ring_refs(struct xen_blkif_ring *ring, const char *dir) · 16 unmodified lines | |||
| 987 | err = xen_blkif_map(ring, ring_ref, nr_grefs, evtchn); | 988 | err = xen_blkif_map(ring, ring_ref, nr_grefs, evtchn); |
| 988 | if (err) { | 989 | if (err) { |
| 989 | xenbus_dev_fatal(dev, err, "mapping ring-ref port %u", evtchn); | 990 | xenbus_dev_fatal(dev, err, "mapping ring-ref port %u", evtchn); |
| 990 | return err; | 991 | goto fail; |
| 991 | } | 992 | } |
| 992 | 993 | ||
| 993 | return 0; | 994 | return 0; |
| @@ -1007,8 +1008,7 @@ fail: · 13 unmodified lines | |||
| 1007 | } | 1008 | } |
| 1008 | kfree(req); | 1009 | kfree(req); |
| 1009 | } | 1010 | } |
| 1010 | return -ENOMEM; | 1011 | return err; |
| 1011 | |||
| 1012 | } | 1012 | } |
| 1013 | 1013 | ||
| 1014 | static int connect_ring(struct backend_info *be) | 1014 | static int connect_ring(struct backend_info *be) |
| @@ -98,6 +98,9 @@ static int ath_open(struct hci_uart *hu) · 97 unmodified lines | |||
| 98 | 98 | ||
| 99 | BT_DBG("hu %p", hu); | 99 | BT_DBG("hu %p", hu); |
| 100 | 100 | ||
| 101 | if (!hci_uart_has_flow_control(hu)) | ||
| 102 | return -EOPNOTSUPP; | ||
| 103 | |||
| 101 | ath = kzalloc(sizeof(*ath), GFP_KERNEL); | 104 | ath = kzalloc(sizeof(*ath), GFP_KERNEL); |
| 102 | if (!ath) | 105 | if (!ath) |
| 103 | return -ENOMEM; | 106 | return -ENOMEM; |
| @@ -406,6 +406,9 @@ static int bcm_open(struct hci_uart *hu) · 405 unmodified lines | |||
| 406 | 406 | ||
| 407 | bt_dev_dbg(hu->hdev, "hu %p", hu); | 407 | bt_dev_dbg(hu->hdev, "hu %p", hu); |
| 408 | 408 | ||
| 409 | if (!hci_uart_has_flow_control(hu)) | ||
| 410 | return -EOPNOTSUPP; | ||
| 411 | |||
| 409 | bcm = kzalloc(sizeof(*bcm), GFP_KERNEL); | 412 | bcm = kzalloc(sizeof(*bcm), GFP_KERNEL); |
| 410 | if (!bcm) | 413 | if (!bcm) |
| 411 | return -ENOMEM; | 414 | return -ENOMEM; |
| @@ -391,6 +391,9 @@ static int intel_open(struct hci_uart *hu) · 390 unmodified lines | |||
| 391 | 391 | ||
| 392 | BT_DBG("hu %p", hu); | 392 | BT_DBG("hu %p", hu); |
| 393 | 393 | ||
| 394 | if (!hci_uart_has_flow_control(hu)) | ||
| 395 | return -EOPNOTSUPP; | ||
| 396 | |||
| 394 | intel = kzalloc(sizeof(*intel), GFP_KERNEL); | 397 | intel = kzalloc(sizeof(*intel), GFP_KERNEL); |
| 395 | if (!intel) | 398 | if (!intel) |
| 396 | return -ENOMEM; | 399 | return -ENOMEM; |
| @@ -292,6 +292,19 @@ static int hci_uart_send_frame(struct hci_dev *hdev, struct sk_buff *skb) · 291 unmodified lines | |||
| 292 | return 0; | 292 | return 0; |
| 293 | } | 293 | } |
| 294 | 294 | ||
| 295 | /* Check the underlying device or tty has flow control support */ | ||
| 296 | bool hci_uart_has_flow_control(struct hci_uart *hu) | ||
| 297 | { | ||
| 298 | /* serdev nodes check if the needed operations are present */ | ||
| 299 | if (hu->serdev) | ||
| 300 | return true; | ||
| 301 | |||
| 302 | if (hu->tty->driver->ops->tiocmget && hu->tty->driver->ops->tiocmset) | ||
| 303 | return true; | ||
| 304 | |||
| 305 | return false; | ||
| 306 | } | ||
| 307 | |||
| 295 | /* Flow control or un-flow control the device */ | 308 | /* Flow control or un-flow control the device */ |
| 296 | void hci_uart_set_flow_control(struct hci_uart *hu, bool enable) | 309 | void hci_uart_set_flow_control(struct hci_uart *hu, bool enable) |
| 297 | { | 310 | { |
| @@ -59,6 +59,9 @@ static int mrvl_open(struct hci_uart *hu) · 58 unmodified lines | |||
| 59 | 59 | ||
| 60 | BT_DBG("hu %p", hu); | 60 | BT_DBG("hu %p", hu); |
| 61 | 61 | ||
| 62 | if (!hci_uart_has_flow_control(hu)) | ||
| 63 | return -EOPNOTSUPP; | ||
| 64 | |||
| 62 | mrvl = kzalloc(sizeof(*mrvl), GFP_KERNEL); | 65 | mrvl = kzalloc(sizeof(*mrvl), GFP_KERNEL); |
| 63 | if (!mrvl) | 66 | if (!mrvl) |
| 64 | return -ENOMEM; | 67 | return -ENOMEM; |
| @@ -473,6 +473,9 @@ static int qca_open(struct hci_uart *hu) · 472 unmodified lines | |||
| 473 | 473 | ||
| 474 | BT_DBG("hu %p qca_open", hu); | 474 | BT_DBG("hu %p qca_open", hu); |
| 475 | 475 | ||
| 476 | if (!hci_uart_has_flow_control(hu)) | ||
| 477 | return -EOPNOTSUPP; | ||
| 478 | |||
| 476 | qca = kzalloc(sizeof(struct qca_data), GFP_KERNEL); | 479 | qca = kzalloc(sizeof(struct qca_data), GFP_KERNEL); |
| 477 | if (!qca) | 480 | if (!qca) |
| 478 | return -ENOMEM; | 481 | return -ENOMEM; |
| @@ -104,6 +104,7 @@ int hci_uart_wait_until_sent(struct hci_uart *hu); · 103 unmodified lines | |||
| 104 | int hci_uart_init_ready(struct hci_uart *hu); | 104 | int hci_uart_init_ready(struct hci_uart *hu); |
| 105 | void hci_uart_init_work(struct work_struct *work); | 105 | void hci_uart_init_work(struct work_struct *work); |
| 106 | void hci_uart_set_baudrate(struct hci_uart *hu, unsigned int speed); | 106 | void hci_uart_set_baudrate(struct hci_uart *hu, unsigned int speed); |
| 107 | bool hci_uart_has_flow_control(struct hci_uart *hu); | ||
| 107 | void hci_uart_set_flow_control(struct hci_uart *hu, bool enable); | 108 | void hci_uart_set_flow_control(struct hci_uart *hu, bool enable); |
| 108 | void hci_uart_set_speeds(struct hci_uart *hu, unsigned int init_speed, | 109 | void hci_uart_set_speeds(struct hci_uart *hu, unsigned int init_speed, |
| 109 | unsigned int oper_speed); | 110 | unsigned int oper_speed); |
| @@ -567,8 +567,7 @@ static inline unsigned long hpet_time_div(struct hpets *hpets, · 566 unmodified lines | |||
| 567 | unsigned long long m; | 567 | unsigned long long m; |
| 568 | 568 | ||
| 569 | m = hpets->hp_tick_freq + (dis >> 1); | 569 | m = hpets->hp_tick_freq + (dis >> 1); |
| 570 | do_div(m, dis); | 570 | return div64_ul(m, dis); |
| 571 | return (unsigned long)m; | ||
| 572 | } | 571 | } |
| 573 | 572 | ||
| 574 | static int | 573 | static int |
| @@ -76,7 +76,7 @@ static ssize_t ipmb_read(struct file *file, char __user *buf, size_t count, · 75 unmodified lines | |||
| 76 | struct ipmb_dev *ipmb_dev = to_ipmb_dev(file); | 76 | struct ipmb_dev *ipmb_dev = to_ipmb_dev(file); |
| 77 | struct ipmb_request_elem *queue_elem; | 77 | struct ipmb_request_elem *queue_elem; |
| 78 | struct ipmb_msg msg; | 78 | struct ipmb_msg msg; |
| 79 | ssize_t ret; | 79 | ssize_t ret = 0; |
| 80 | 80 | ||
| 81 | memset(&msg, 0, sizeof(msg)); | 81 | memset(&msg, 0, sizeof(msg)); |
| 82 | 82 | ||
| @@ -77,6 +77,18 @@ static int tpm_go_idle(struct tpm_chip *chip) · 76 unmodified lines | |||
| 77 | return chip->ops->go_idle(chip); | 77 | return chip->ops->go_idle(chip); |
| 78 | } | 78 | } |
| 79 | 79 | ||
| 80 | static void tpm_clk_enable(struct tpm_chip *chip) | ||
| 81 | { | ||
| 82 | if (chip->ops->clk_enable) | ||
| 83 | chip->ops->clk_enable(chip, true); | ||
| 84 | } | ||
| 85 | |||
| 86 | static void tpm_clk_disable(struct tpm_chip *chip) | ||
| 87 | { | ||
| 88 | if (chip->ops->clk_enable) | ||
| 89 | chip->ops->clk_enable(chip, false); | ||
| 90 | } | ||
| 91 | |||
| 80 | /** | 92 | /** |
| 81 | * tpm_chip_start() - power on the TPM | 93 | * tpm_chip_start() - power on the TPM |
| 82 | * @chip: a TPM chip to use | 94 | * @chip: a TPM chip to use |
| @@ -89,13 +101,12 @@ int tpm_chip_start(struct tpm_chip *chip) · 6 unmodified lines | |||
| 89 | { | 101 | { |
| 90 | int ret; | 102 | int ret; |
| 91 | 103 | ||
| 92 | if (chip->ops->clk_enable) | 104 | tpm_clk_enable(chip); |
| 93 | chip->ops->clk_enable(chip, true); | ||
| 94 | 105 | ||
| 95 | if (chip->locality == -1) { | 106 | if (chip->locality == -1) { |
| 96 | ret = tpm_request_locality(chip); | 107 | ret = tpm_request_locality(chip); |
| 97 | if (ret) { | 108 | if (ret) { |
| 98 | chip->ops->clk_enable(chip, false); | 109 | tpm_clk_disable(chip); |
| 99 | return ret; | 110 | return ret; |
| 100 | } | 111 | } |
| 101 | } | 112 | } |
| @@ -103,8 +114,7 @@ int tpm_chip_start(struct tpm_chip *chip) · 1 unmodified line | |||
| 103 | ret = tpm_cmd_ready(chip); | 114 | ret = tpm_cmd_ready(chip); |
| 104 | if (ret) { | 115 | if (ret) { |
| 105 | tpm_relinquish_locality(chip); | 116 | tpm_relinquish_locality(chip); |
| 106 | if (chip->ops->clk_enable) | 117 | tpm_clk_disable(chip); |
| 107 | chip->ops->clk_enable(chip, false); | ||
| 108 | return ret; | 118 | return ret; |
| 109 | } | 119 | } |
| 110 | 120 | ||
| @@ -124,8 +134,7 @@ void tpm_chip_stop(struct tpm_chip *chip) · 13 unmodified lines | |||
| 124 | { | 134 | { |
| 125 | tpm_go_idle(chip); | 135 | tpm_go_idle(chip); |
| 126 | tpm_relinquish_locality(chip); | 136 | tpm_relinquish_locality(chip); |
| 127 | if (chip->ops->clk_enable) | 137 | tpm_clk_disable(chip); |
| 128 | chip->ops->clk_enable(chip, false); | ||
| 129 | } | 138 | } |
| 130 | EXPORT_SYMBOL_GPL(tpm_chip_stop); | 139 | EXPORT_SYMBOL_GPL(tpm_chip_stop); |
| 131 | 140 | ||
| @@ -545,6 +554,20 @@ static int tpm_add_hwrng(struct tpm_chip *chip) · 413 unmodified lines | |||
| 545 | return hwrng_register(&chip->hwrng); | 554 | return hwrng_register(&chip->hwrng); |
| 546 | } | 555 | } |
| 547 | 556 | ||
| 557 | static int tpm_get_pcr_allocation(struct tpm_chip *chip) | ||
| 558 | { | ||
| 559 | int rc; | ||
| 560 | |||
| 561 | rc = (chip->flags & TPM_CHIP_FLAG_TPM2) ? | ||
| 562 | tpm2_get_pcr_allocation(chip) : | ||
| 563 | tpm1_get_pcr_allocation(chip); | ||
| 564 | |||
| 565 | if (rc > 0) | ||
| 566 | return -ENODEV; | ||
| 567 | |||
| 568 | return rc; | ||
| 569 | } | ||
| 570 | |||
| 548 | /* | 571 | /* |
| 549 | * tpm_chip_register() - create a character device for the TPM chip | 572 | * tpm_chip_register() - create a character device for the TPM chip |
| 550 | * @chip: TPM chip to use. | 573 | * @chip: TPM chip to use. |
| @@ -564,6 +587,12 @@ int tpm_chip_register(struct tpm_chip *chip) · 13 unmodified lines | |||
| 564 | if (rc) | 587 | if (rc) |
| 565 | return rc; | 588 | return rc; |
| 566 | rc = tpm_auto_startup(chip); | 589 | rc = tpm_auto_startup(chip); |
| 590 | if (rc) { | ||
| 591 | tpm_chip_stop(chip); | ||
| 592 | return rc; | ||
| 593 | } | ||
| 594 | |||
| 595 | rc = tpm_get_pcr_allocation(chip); | ||
| 567 | tpm_chip_stop(chip); | 596 | tpm_chip_stop(chip); |
| 568 | if (rc) | 597 | if (rc) |
| 569 | return rc; | 598 | return rc; |
| @@ -394,6 +394,7 @@ int tpm1_pcr_read(struct tpm_chip *chip, u32 pcr_idx, u8 *res_buf); · 393 unmodified lines | |||
| 394 | ssize_t tpm1_getcap(struct tpm_chip *chip, u32 subcap_id, cap_t *cap, | 394 | ssize_t tpm1_getcap(struct tpm_chip *chip, u32 subcap_id, cap_t *cap, |
| 395 | const char *desc, size_t min_cap_length); | 395 | const char *desc, size_t min_cap_length); |
| 396 | int tpm1_get_random(struct tpm_chip *chip, u8 *out, size_t max); | 396 | int tpm1_get_random(struct tpm_chip *chip, u8 *out, size_t max); |
| 397 | int tpm1_get_pcr_allocation(struct tpm_chip *chip); | ||
| 397 | unsigned long tpm_calc_ordinal_duration(struct tpm_chip *chip, u32 ordinal); | 398 | unsigned long tpm_calc_ordinal_duration(struct tpm_chip *chip, u32 ordinal); |
| 398 | int tpm_pm_suspend(struct device *dev); | 399 | int tpm_pm_suspend(struct device *dev); |
| 399 | int tpm_pm_resume(struct device *dev); | 400 | int tpm_pm_resume(struct device *dev); |
| @@ -449,6 +450,7 @@ int tpm2_unseal_trusted(struct tpm_chip *chip, · 49 unmodified lines | |||
| 449 | ssize_t tpm2_get_tpm_pt(struct tpm_chip *chip, u32 property_id, | 450 | ssize_t tpm2_get_tpm_pt(struct tpm_chip *chip, u32 property_id, |
| 450 | u32 *value, const char *desc); | 451 | u32 *value, const char *desc); |
| 451 | 452 | ||
| 453 | ssize_t tpm2_get_pcr_allocation(struct tpm_chip *chip); | ||
| 452 | int tpm2_auto_startup(struct tpm_chip *chip); | 454 | int tpm2_auto_startup(struct tpm_chip *chip); |
| 453 | void tpm2_shutdown(struct tpm_chip *chip, u16 shutdown_type); | 455 | void tpm2_shutdown(struct tpm_chip *chip, u16 shutdown_type); |
| 454 | unsigned long tpm2_calc_ordinal_duration(struct tpm_chip *chip, u32 ordinal); | 456 | unsigned long tpm2_calc_ordinal_duration(struct tpm_chip *chip, u32 ordinal); |
| @@ -699,18 +699,6 @@ int tpm1_auto_startup(struct tpm_chip *chip) · 698 unmodified lines | |||
| 699 | goto out; | 699 | goto out; |
| 700 | } | 700 | } |
| 701 | 701 | ||
| 702 | chip->allocated_banks = kcalloc(1, sizeof(*chip->allocated_banks), | ||
| 703 | GFP_KERNEL); | ||
| 704 | if (!chip->allocated_banks) { | ||
| 705 | rc = -ENOMEM; | ||
| 706 | goto out; | ||
| 707 | } | ||
| 708 | |||
| 709 | chip->allocated_banks[0].alg_id = TPM_ALG_SHA1; | ||
| 710 | chip->allocated_banks[0].digest_size = hash_digest_size[HASH_ALGO_SHA1]; | ||
| 711 | chip->allocated_banks[0].crypto_id = HASH_ALGO_SHA1; | ||
| 712 | chip->nr_allocated_banks = 1; | ||
| 713 | |||
| 714 | return rc; | 702 | return rc; |
| 715 | out: | 703 | out: |
| 716 | if (rc > 0) | 704 | if (rc > 0) |
| @@ -779,3 +767,27 @@ int tpm1_pm_suspend(struct tpm_chip *chip, u32 tpm_suspend_pcr) · 62 unmodified lines | |||
| 779 | return rc; | 767 | return rc; |
| 780 | } | 768 | } |
| 781 | 769 | ||
| 770 | /** | ||
| 771 | * tpm1_get_pcr_allocation() - initialize the allocated bank | ||
| 772 | * @chip: TPM chip to use. | ||
| 773 | * | ||
| 774 | * The function initializes the SHA1 allocated bank to extend PCR | ||
| 775 | * | ||
| 776 | * Return: | ||
| 777 | * * 0 on success, | ||
| 778 | * * < 0 on error. | ||
| 779 | */ | ||
| 780 | int tpm1_get_pcr_allocation(struct tpm_chip *chip) | ||
| 781 | { | ||
| 782 | chip->allocated_banks = kcalloc(1, sizeof(*chip->allocated_banks), | ||
| 783 | GFP_KERNEL); | ||
| 784 | if (!chip->allocated_banks) | ||
| 785 | return -ENOMEM; | ||
| 786 | |||
| 787 | chip->allocated_banks[0].alg_id = TPM_ALG_SHA1; | ||
| 788 | chip->allocated_banks[0].digest_size = hash_digest_size[HASH_ALGO_SHA1]; | ||
| 789 | chip->allocated_banks[0].crypto_id = HASH_ALGO_SHA1; | ||
| 790 | chip->nr_allocated_banks = 1; | ||
| 791 | |||
| 792 | return 0; | ||
| 793 | } | ||
| @@ -840,7 +840,7 @@ struct tpm2_pcr_selection { · 839 unmodified lines | |||
| 840 | u8 pcr_select[3]; | 840 | u8 pcr_select[3]; |
| 841 | } __packed; | 841 | } __packed; |
| 842 | 842 | ||
| 843 | static ssize_t tpm2_get_pcr_allocation(struct tpm_chip *chip) | 843 | ssize_t tpm2_get_pcr_allocation(struct tpm_chip *chip) |
| 844 | { | 844 | { |
| 845 | struct tpm2_pcr_selection pcr_selection; | 845 | struct tpm2_pcr_selection pcr_selection; |
| 846 | struct tpm_buf buf; | 846 | struct tpm_buf buf; |
| @@ -1040,10 +1040,6 @@ int tpm2_auto_startup(struct tpm_chip *chip) · 193 unmodified lines | |||
| 1040 | goto out; | 1040 | goto out; |
| 1041 | } | 1041 | } |
| 1042 | 1042 | ||
| 1043 | rc = tpm2_get_pcr_allocation(chip); | ||
| 1044 | if (rc) | ||
| 1045 | goto out; | ||
| 1046 | |||
| 1047 | rc = tpm2_get_cc_attrs_tbl(chip); | 1043 | rc = tpm2_get_cc_attrs_tbl(chip); |
| 1048 | 1044 | ||
| 1049 | out: | 1045 | out: |
| @@ -141,6 +141,8 @@ static int clk_generated_determine_rate(struct clk_hw *hw, · 140 unmodified lines | |||
| 141 | continue; | 141 | continue; |
| 142 | 142 | ||
| 143 | div = DIV_ROUND_CLOSEST(parent_rate, req->rate); | 143 | div = DIV_ROUND_CLOSEST(parent_rate, req->rate); |
| 144 | if (div > GENERATED_MAX_DIV + 1) | ||
| 145 | div = GENERATED_MAX_DIV + 1; | ||
| 144 | 146 | ||
| 145 | clk_generated_best_diff(req, parent, parent_rate, div, | 147 | clk_generated_best_diff(req, parent, parent_rate, div, |
| 146 | &best_diff, &best_rate); | 148 | &best_diff, &best_rate); |
| @@ -25,9 +25,11 @@ static const struct mtk_fixed_clk top_fixed_clks[] = { · 24 unmodified lines | |||
| 25 | FIXED_CLK(CLK_TOP_UNIVP_192M, "univpll_192m", "univpll", 192000000), | 25 | FIXED_CLK(CLK_TOP_UNIVP_192M, "univpll_192m", "univpll", 192000000), |
| 26 | }; | 26 | }; |
| 27 | 27 | ||
| 28 | static const struct mtk_fixed_factor top_early_divs[] = { | ||
| 29 | FACTOR(CLK_TOP_CLK13M, "clk13m", "clk26m", 1, 2), | ||
| 30 | }; | ||
| 31 | |||
| 28 | static const struct mtk_fixed_factor top_divs[] = { | 32 | static const struct mtk_fixed_factor top_divs[] = { |
| 29 | FACTOR(CLK_TOP_CLK13M, "clk13m", "clk26m", 1, | ||
| 30 | 2), | ||
| 31 | FACTOR(CLK_TOP_F26M_CK_D2, "csw_f26m_ck_d2", "clk26m", 1, | 33 | FACTOR(CLK_TOP_F26M_CK_D2, "csw_f26m_ck_d2", "clk26m", 1, |
| 32 | 2), | 34 | 2), |
| 33 | FACTOR(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1, | 35 | FACTOR(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1, |
| @@ -1148,37 +1150,57 @@ static int clk_mt8183_apmixed_probe(struct platform_device *pdev) · 1114 unmodified lines | |||
| 1148 | return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); | 1150 | return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| 1149 | } | 1151 | } |
| 1150 | 1152 | ||
| 1153 | static struct clk_onecell_data *top_clk_data; | ||
| 1154 | |||
| 1155 | static void clk_mt8183_top_init_early(struct device_node *node) | ||
| 1156 | { | ||
| 1157 | int i; | ||
| 1158 | |||
| 1159 | top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); | ||
| 1160 | |||
| 1161 | for (i = 0; i < CLK_TOP_NR_CLK; i++) | ||
| 1162 | top_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER); | ||
| 1163 | |||
| 1164 | mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), | ||
| 1165 | top_clk_data); | ||
| 1166 | |||
| 1167 | of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data); | ||
| 1168 | } | ||
| 1169 | |||
| 1170 | CLK_OF_DECLARE_DRIVER(mt8183_topckgen, "mediatek,mt8183-topckgen", | ||
| 1171 | clk_mt8183_top_init_early); | ||
| 1172 | |||
| 1151 | static int clk_mt8183_top_probe(struct platform_device *pdev) | 1173 | static int clk_mt8183_top_probe(struct platform_device *pdev) |
| 1152 | { | 1174 | { |
| 1153 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 1175 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1154 | void __iomem *base; | 1176 | void __iomem *base; |
| 1155 | struct clk_onecell_data *clk_data; | ||
| 1156 | struct device_node *node = pdev->dev.of_node; | 1177 | struct device_node *node = pdev->dev.of_node; |
| 1157 | 1178 | ||
| 1158 | base = devm_ioremap_resource(&pdev->dev, res); | 1179 | base = devm_ioremap_resource(&pdev->dev, res); |
| 1159 | if (IS_ERR(base)) | 1180 | if (IS_ERR(base)) |
| 1160 | return PTR_ERR(base); | 1181 | return PTR_ERR(base); |
| 1161 | 1182 | ||
| 1162 | clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); | ||
| 1163 | |||
| 1164 | mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), | 1183 | mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), |
| 1165 | clk_data); | 1184 | top_clk_data); |
| 1185 | |||
| 1186 | mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), | ||
| 1187 | top_clk_data); | ||
| 1166 | 1188 | ||
| 1167 | mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); | 1189 | mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data); |
| 1168 | 1190 | ||
| 1169 | mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), | 1191 | mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), |
| 1170 | node, &mt8183_clk_lock, clk_data); | 1192 | node, &mt8183_clk_lock, top_clk_data); |
| 1171 | 1193 | ||
| 1172 | mtk_clk_register_composites(top_aud_muxes, ARRAY_SIZE(top_aud_muxes), | 1194 | mtk_clk_register_composites(top_aud_muxes, ARRAY_SIZE(top_aud_muxes), |
| 1173 | base, &mt8183_clk_lock, clk_data); | 1195 | base, &mt8183_clk_lock, top_clk_data); |
| 1174 | 1196 | ||
| 1175 | mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs), | 1197 | mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs), |
| 1176 | base, &mt8183_clk_lock, clk_data); | 1198 | base, &mt8183_clk_lock, top_clk_data); |
| 1177 | 1199 | ||
| 1178 | mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), | 1200 | mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), |
| 1179 | clk_data); | 1201 | top_clk_data); |
| 1180 | 1202 | ||
| 1181 | return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); | 1203 | return of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data); |
| 1182 | } | 1204 | } |
| 1183 | 1205 | ||
| 1184 | static int clk_mt8183_infra_probe(struct platform_device *pdev) | 1206 | static int clk_mt8183_infra_probe(struct platform_device *pdev) |
| @@ -572,17 +572,11 @@ static int cpg_mssr_reset(struct reset_controller_dev *rcdev, · 571 unmodified lines | |||
| 572 | unsigned int reg = id / 32; | 572 | unsigned int reg = id / 32; |
| 573 | unsigned int bit = id % 32; | 573 | unsigned int bit = id % 32; |
| 574 | u32 bitmask = BIT(bit); | 574 | u32 bitmask = BIT(bit); |
| 575 | unsigned long flags; | ||
| 576 | u32 value; | ||
| 577 | 575 | ||
| 578 | dev_dbg(priv->dev, "reset %u%02u\n", reg, bit); | 576 | dev_dbg(priv->dev, "reset %u%02u\n", reg, bit); |
| 579 | 577 | ||
| 580 | /* Reset module */ | 578 | /* Reset module */ |
| 581 | spin_lock_irqsave(&priv->rmw_lock, flags); | 579 | writel(bitmask, priv->base + SRCR(reg)); |
| 582 | value = readl(priv->base + SRCR(reg)); | ||
| 583 | value |= bitmask; | ||
| 584 | writel(value, priv->base + SRCR(reg)); | ||
| 585 | spin_unlock_irqrestore(&priv->rmw_lock, flags); | ||
| 586 | 580 | ||
| 587 | /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */ | 581 | /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */ |
| 588 | udelay(35); | 582 | udelay(35); |
| @@ -599,16 +593,10 @@ static int cpg_mssr_assert(struct reset_controller_dev *rcdev, unsigned long id) · 10 unmodified lines | |||
| 599 | unsigned int reg = id / 32; | 593 | unsigned int reg = id / 32; |
| 600 | unsigned int bit = id % 32; | 594 | unsigned int bit = id % 32; |
| 601 | u32 bitmask = BIT(bit); | 595 | u32 bitmask = BIT(bit); |
| 602 | unsigned long flags; | ||
| 603 | u32 value; | ||
| 604 | 596 | ||
| 605 | dev_dbg(priv->dev, "assert %u%02u\n", reg, bit); | 597 | dev_dbg(priv->dev, "assert %u%02u\n", reg, bit); |
| 606 | 598 | ||
| 607 | spin_lock_irqsave(&priv->rmw_lock, flags); | 599 | writel(bitmask, priv->base + SRCR(reg)); |
| 608 | value = readl(priv->base + SRCR(reg)); | ||
| 609 | value |= bitmask; | ||
| 610 | writel(value, priv->base + SRCR(reg)); | ||
| 611 | spin_unlock_irqrestore(&priv->rmw_lock, flags); | ||
| 612 | return 0; | 600 | return 0; |
| 613 | } | 601 | } |
| 614 | 602 | ||
| @@ -3,6 +3,7 @@ config SPRD_COMMON_CLK · 2 unmodified lines | |||
| 3 | tristate "Clock support for Spreadtrum SoCs" | 3 | tristate "Clock support for Spreadtrum SoCs" |
| 4 | depends on ARCH_SPRD || COMPILE_TEST | 4 | depends on ARCH_SPRD || COMPILE_TEST |
| 5 | default ARCH_SPRD | 5 | default ARCH_SPRD |
| 6 | select REGMAP_MMIO | ||
| 6 | 7 | ||
| 7 | if SPRD_COMMON_CLK | 8 | if SPRD_COMMON_CLK |
| 8 | 9 | ||
| @@ -55,7 +55,7 @@ static u64 riscv_sched_clock(void) · 54 unmodified lines | |||
| 55 | return get_cycles64(); | 55 | return get_cycles64(); |
| 56 | } | 56 | } |
| 57 | 57 | ||
| 58 | static DEFINE_PER_CPU(struct clocksource, riscv_clocksource) = { | 58 | static struct clocksource riscv_clocksource = { |
| 59 | .name = "riscv_clocksource", | 59 | .name = "riscv_clocksource", |
| 60 | .rating = 300, | 60 | .rating = 300, |
| 61 | .mask = CLOCKSOURCE_MASK(64), | 61 | .mask = CLOCKSOURCE_MASK(64), |
| @@ -92,7 +92,6 @@ void riscv_timer_interrupt(void) · 30 unmodified lines | |||
| 92 | static int __init riscv_timer_init_dt(struct device_node *n) | 92 | static int __init riscv_timer_init_dt(struct device_node *n) |
| 93 | { | 93 | { |
| 94 | int cpuid, hartid, error; | 94 | int cpuid, hartid, error; |
| 95 | struct clocksource *cs; | ||
| 96 | 95 | ||
| 97 | hartid = riscv_of_processor_hartid(n); | 96 | hartid = riscv_of_processor_hartid(n); |
| 98 | if (hartid < 0) { | 97 | if (hartid < 0) { |
| @@ -112,8 +111,7 @@ static int __init riscv_timer_init_dt(struct device_node *n) · 13 unmodified lines | |||
| 112 | 111 | ||
| 113 | pr_info("%s: Registering clocksource cpuid [%d] hartid [%d]\n", | 112 | pr_info("%s: Registering clocksource cpuid [%d] hartid [%d]\n", |
| 114 | __func__, cpuid, hartid); | 113 | __func__, cpuid, hartid); |
| 115 | cs = per_cpu_ptr(&riscv_clocksource, cpuid); | 114 | error = clocksource_register_hz(&riscv_clocksource, riscv_timebase); |
| 116 | error = clocksource_register_hz(cs, riscv_timebase); | ||
| 117 | if (error) { | 115 | if (error) { |
| 118 | pr_err("RISCV timer register failed [%d] for cpu = [%d]\n", | 116 | pr_err("RISCV timer register failed [%d] for cpu = [%d]\n", |
| 119 | error, cpuid); | 117 | error, cpuid); |
| @@ -248,16 +248,12 @@ static int __maybe_unused cn_proc_show(struct seq_file *m, void *v) · 247 unmodified lines | |||
| 248 | return 0; | 248 | return 0; |
| 249 | } | 249 | } |
| 250 | 250 | ||
| 251 | static struct cn_dev cdev = { | ||
| 252 | .input = cn_rx_skb, | ||
| 253 | }; | ||
| 254 | |||
| 255 | static int cn_init(void) | 251 | static int cn_init(void) |
| 256 | { | 252 | { |
| 257 | struct cn_dev *dev = &cdev; | 253 | struct cn_dev *dev = &cdev; |
| 258 | struct netlink_kernel_cfg cfg = { | 254 | struct netlink_kernel_cfg cfg = { |
| 259 | .groups = CN_NETLINK_USERS + 0xf, | 255 | .groups = CN_NETLINK_USERS + 0xf, |
| 260 | .input = dev->input, | 256 | .input = cn_rx_skb, |
| 261 | }; | 257 | }; |
| 262 | 258 | ||
| 263 | dev->nls = netlink_kernel_create(&init_net, NETLINK_CONNECTOR, &cfg); | 259 | dev->nls = netlink_kernel_create(&init_net, NETLINK_CONNECTOR, &cfg); |
| @@ -2528,7 +2528,7 @@ static int cpufreq_boost_set_sw(int state) · 2527 unmodified lines | |||
| 2528 | } | 2528 | } |
| 2529 | 2529 | ||
| 2530 | ret = dev_pm_qos_update_request(policy->max_freq_req, policy->max); | 2530 | ret = dev_pm_qos_update_request(policy->max_freq_req, policy->max); |
| 2531 | if (ret) | 2531 | if (ret < 0) |
| 2532 | break; | 2532 | break; |
| 2533 | } | 2533 | } |
| 2534 | 2534 | ||
| @@ -131,10 +131,18 @@ static int pas_cpufreq_cpu_init(struct cpufreq_policy *policy) · 130 unmodified lines | |||
| 131 | int err = -ENODEV; | 131 | int err = -ENODEV; |
| 132 | 132 | ||
| 133 | cpu = of_get_cpu_node(policy->cpu, NULL); | 133 | cpu = of_get_cpu_node(policy->cpu, NULL); |
| 134 | if (!cpu) | ||
| 135 | goto out; | ||
| 134 | 136 | ||
| 137 | max_freqp = of_get_property(cpu, "clock-frequency", NULL); | ||
| 135 | of_node_put(cpu); | 138 | of_node_put(cpu); |
| 136 | if (!cpu) | 139 | if (!max_freqp) { |
| 140 | err = -EINVAL; | ||
| 137 | goto out; | 141 | goto out; |
| 142 | } | ||
| 143 | |||
| 144 | /* we need the freq in kHz */ | ||
| 145 | max_freq = *max_freqp / 1000; | ||
| 138 | 146 | ||
| 139 | dn = of_find_compatible_node(NULL, NULL, "1682m-sdc"); | 147 | dn = of_find_compatible_node(NULL, NULL, "1682m-sdc"); |
| 140 | if (!dn) | 148 | if (!dn) |
| @@ -171,16 +179,6 @@ static int pas_cpufreq_cpu_init(struct cpufreq_policy *policy) · 30 unmodified lines | |||
| 171 | } | 179 | } |
| 172 | 180 | ||
| 173 | pr_debug("init cpufreq on CPU %d\n", policy->cpu); | 181 | pr_debug("init cpufreq on CPU %d\n", policy->cpu); |
| 174 | |||
| 175 | max_freqp = of_get_property(cpu, "clock-frequency", NULL); | ||
| 176 | if (!max_freqp) { | ||
| 177 | err = -EINVAL; | ||
| 178 | goto out_unmap_sdcpwr; | ||
| 179 | } | ||
| 180 | |||
| 181 | /* we need the freq in kHz */ | ||
| 182 | max_freq = *max_freqp / 1000; | ||
| 183 | |||
| 184 | pr_debug("max clock-frequency is at %u kHz\n", max_freq); | 182 | pr_debug("max clock-frequency is at %u kHz\n", max_freq); |
| 185 | pr_debug("initializing frequency table\n"); | 183 | pr_debug("initializing frequency table\n"); |
| 186 | 184 | ||
| @@ -199,9 +197,6 @@ static int pas_cpufreq_cpu_init(struct cpufreq_policy *policy) · 12 unmodified lines | |||
| 199 | cpufreq_generic_init(policy, pas_freqs, get_gizmo_latency()); | 197 | cpufreq_generic_init(policy, pas_freqs, get_gizmo_latency()); |
| 200 | return 0; | 198 | return 0; |
| 201 | 199 | ||
| 202 | out_unmap_sdcpwr: | ||
| 203 | iounmap(sdcpwr_mapbase); | ||
| 204 | |||
| 205 | out_unmap_sdcasr: | 200 | out_unmap_sdcasr: |
| 206 | iounmap(sdcasr_mapbase); | 201 | iounmap(sdcasr_mapbase); |
| 207 | out: | 202 | out: |
| @@ -58,6 +58,19 @@ static int ccp_aes_gcm_setkey(struct crypto_aead *tfm, const u8 *key, · 57 unmodified lines | |||
| 58 | static int ccp_aes_gcm_setauthsize(struct crypto_aead *tfm, | 58 | static int ccp_aes_gcm_setauthsize(struct crypto_aead *tfm, |
| 59 | unsigned int authsize) | 59 | unsigned int authsize) |
| 60 | { | 60 | { |
| 61 | switch (authsize) { | ||
| 62 | case 16: | ||
| 63 | case 15: | ||
| 64 | case 14: | ||
| 65 | case 13: | ||
| 66 | case 12: | ||
| 67 | case 8: | ||
| 68 | case 4: | ||
| 69 | break; | ||
| 70 | default: | ||
| 71 | return -EINVAL; | ||
| 72 | } | ||
| 73 | |||
| 61 | return 0; | 74 | return 0; |
| 62 | } | 75 | } |
| 63 | 76 | ||
| @@ -104,6 +117,7 @@ static int ccp_aes_gcm_crypt(struct aead_request *req, bool encrypt) · 40 unmodified lines | |||
| 104 | memset(&rctx->cmd, 0, sizeof(rctx->cmd)); | 117 | memset(&rctx->cmd, 0, sizeof(rctx->cmd)); |
| 105 | INIT_LIST_HEAD(&rctx->cmd.entry); | 118 | INIT_LIST_HEAD(&rctx->cmd.entry); |
| 106 | rctx->cmd.engine = CCP_ENGINE_AES; | 119 | rctx->cmd.engine = CCP_ENGINE_AES; |
| 120 | rctx->cmd.u.aes.authsize = crypto_aead_authsize(tfm); | ||
| 107 | rctx->cmd.u.aes.type = ctx->u.aes.type; | 121 | rctx->cmd.u.aes.type = ctx->u.aes.type; |
| 108 | rctx->cmd.u.aes.mode = ctx->u.aes.mode; | 122 | rctx->cmd.u.aes.mode = ctx->u.aes.mode; |
| 109 | rctx->cmd.u.aes.action = encrypt; | 123 | rctx->cmd.u.aes.action = encrypt; |
| @@ -622,6 +622,7 @@ static int ccp_run_aes_gcm_cmd(struct ccp_cmd_queue *cmd_q, · 621 unmodified lines | |||
| 622 | 622 | ||
| 623 | unsigned long long *final; | 623 | unsigned long long *final; |
| 624 | unsigned int dm_offset; | 624 | unsigned int dm_offset; |
| 625 | unsigned int authsize; | ||
| 625 | unsigned int jobid; | 626 | unsigned int jobid; |
| 626 | unsigned int ilen; | 627 | unsigned int ilen; |
| 627 | bool in_place = true; /* Default value */ | 628 | bool in_place = true; /* Default value */ |
| @@ -643,6 +644,21 @@ static int ccp_run_aes_gcm_cmd(struct ccp_cmd_queue *cmd_q, · 15 unmodified lines | |||
| 643 | if (!aes->key) /* Gotta have a key SGL */ | 644 | if (!aes->key) /* Gotta have a key SGL */ |
| 644 | return -EINVAL; | 645 | return -EINVAL; |
| 645 | 646 | ||
| 647 | /* Zero defaults to 16 bytes, the maximum size */ | ||
| 648 | authsize = aes->authsize ? aes->authsize : AES_BLOCK_SIZE; | ||
| 649 | switch (authsize) { | ||
| 650 | case 16: | ||
| 651 | case 15: | ||
| 652 | case 14: | ||
| 653 | case 13: | ||
| 654 | case 12: | ||
| 655 | case 8: | ||
| 656 | case 4: | ||
| 657 | break; | ||
| 658 | default: | ||
| 659 | return -EINVAL; | ||
| 660 | } | ||
| 661 | |||
| 646 | /* First, decompose the source buffer into AAD & PT, | 662 | /* First, decompose the source buffer into AAD & PT, |
| 647 | * and the destination buffer into AAD, CT & tag, or | 663 | * and the destination buffer into AAD, CT & tag, or |
| 648 | * the input into CT & tag. | 664 | * the input into CT & tag. |
| @@ -657,7 +673,7 @@ static int ccp_run_aes_gcm_cmd(struct ccp_cmd_queue *cmd_q, · 8 unmodified lines | |||
| 657 | p_tag = scatterwalk_ffwd(sg_tag, p_outp, ilen); | 673 | p_tag = scatterwalk_ffwd(sg_tag, p_outp, ilen); |
| 658 | } else { | 674 | } else { |
| 659 | /* Input length for decryption includes tag */ | 675 | /* Input length for decryption includes tag */ |
| 660 | ilen = aes->src_len - AES_BLOCK_SIZE; | 676 | ilen = aes->src_len - authsize; |
| 661 | p_tag = scatterwalk_ffwd(sg_tag, p_inp, ilen); | 677 | p_tag = scatterwalk_ffwd(sg_tag, p_inp, ilen); |
| 662 | } | 678 | } |
| 663 | 679 | ||
| @@ -766,8 +782,7 @@ static int ccp_run_aes_gcm_cmd(struct ccp_cmd_queue *cmd_q, · 102 unmodified lines | |||
| 766 | while (src.sg_wa.bytes_left) { | 782 | while (src.sg_wa.bytes_left) { |
| 767 | ccp_prepare_data(&src, &dst, &op, AES_BLOCK_SIZE, true); | 783 | ccp_prepare_data(&src, &dst, &op, AES_BLOCK_SIZE, true); |
| 768 | if (!src.sg_wa.bytes_left) { | 784 | if (!src.sg_wa.bytes_left) { |
| 769 | unsigned int nbytes = aes->src_len | 785 | unsigned int nbytes = ilen % AES_BLOCK_SIZE; |
| 770 | % AES_BLOCK_SIZE; | ||
| 771 | 786 | ||
| 772 | if (nbytes) { | 787 | if (nbytes) { |
| 773 | op.eom = 1; | 788 | op.eom = 1; |
| @@ -839,19 +854,19 @@ static int ccp_run_aes_gcm_cmd(struct ccp_cmd_queue *cmd_q, · 65 unmodified lines | |||
| 839 | 854 | ||
| 840 | if (aes->action == CCP_AES_ACTION_ENCRYPT) { | 855 | if (aes->action == CCP_AES_ACTION_ENCRYPT) { |
| 841 | /* Put the ciphered tag after the ciphertext. */ | 856 | /* Put the ciphered tag after the ciphertext. */ |
| 842 | ccp_get_dm_area(&final_wa, 0, p_tag, 0, AES_BLOCK_SIZE); | 857 | ccp_get_dm_area(&final_wa, 0, p_tag, 0, authsize); |
| 843 | } else { | 858 | } else { |
| 844 | /* Does this ciphered tag match the input? */ | 859 | /* Does this ciphered tag match the input? */ |
| 845 | ret = ccp_init_dm_workarea(&tag, cmd_q, AES_BLOCK_SIZE, | 860 | ret = ccp_init_dm_workarea(&tag, cmd_q, authsize, |
| 846 | DMA_BIDIRECTIONAL); | 861 | DMA_BIDIRECTIONAL); |
| 847 | if (ret) | 862 | if (ret) |
| 848 | goto e_tag; | 863 | goto e_tag; |
| 849 | ret = ccp_set_dm_area(&tag, 0, p_tag, 0, AES_BLOCK_SIZE); | 864 | ret = ccp_set_dm_area(&tag, 0, p_tag, 0, authsize); |
| 850 | if (ret) | 865 | if (ret) |
| 851 | goto e_tag; | 866 | goto e_tag; |
| 852 | 867 | ||
| 853 | ret = crypto_memneq(tag.address, final_wa.address, | 868 | ret = crypto_memneq(tag.address, final_wa.address, |
| 854 | AES_BLOCK_SIZE) ? -EBADMSG : 0; | 869 | authsize) ? -EBADMSG : 0; |
| 855 | ccp_dm_free(&tag); | 870 | ccp_dm_free(&tag); |
| 856 | } | 871 | } |
| 857 | 872 | ||
| @@ -859,11 +874,11 @@ e_tag: · 1 unmodified line | |||
| 859 | ccp_dm_free(&final_wa); | 874 | ccp_dm_free(&final_wa); |
| 860 | 875 | ||
| 861 | e_dst: | 876 | e_dst: |
| 862 | if (aes->src_len && !in_place) | 877 | if (ilen > 0 && !in_place) |
| 863 | ccp_free_data(&dst, cmd_q); | 878 | ccp_free_data(&dst, cmd_q); |
| 864 | 879 | ||
| 865 | e_src: | 880 | e_src: |
| 866 | if (aes->src_len) | 881 | if (ilen > 0) |
| 867 | ccp_free_data(&src, cmd_q); | 882 | ccp_free_data(&src, cmd_q); |
| 868 | 883 | ||
| 869 | e_aad: | 884 | e_aad: |
| @@ -314,14 +314,17 @@ void cryp_save_device_context(struct cryp_device_data *device_data, · 313 unmodified lines | |||
| 314 | case CRYP_KEY_SIZE_256: | 314 | case CRYP_KEY_SIZE_256: |
| 315 | ctx->key_4_l = readl_relaxed(&src_reg->key_4_l); | 315 | ctx->key_4_l = readl_relaxed(&src_reg->key_4_l); |
| 316 | ctx->key_4_r = readl_relaxed(&src_reg->key_4_r); | 316 | ctx->key_4_r = readl_relaxed(&src_reg->key_4_r); |
| 317 | /* Fall through */ | ||
| 317 | 318 | ||
| 318 | case CRYP_KEY_SIZE_192: | 319 | case CRYP_KEY_SIZE_192: |
| 319 | ctx->key_3_l = readl_relaxed(&src_reg->key_3_l); | 320 | ctx->key_3_l = readl_relaxed(&src_reg->key_3_l); |
| 320 | ctx->key_3_r = readl_relaxed(&src_reg->key_3_r); | 321 | ctx->key_3_r = readl_relaxed(&src_reg->key_3_r); |
| 322 | /* Fall through */ | ||
| 321 | 323 | ||
| 322 | case CRYP_KEY_SIZE_128: | 324 | case CRYP_KEY_SIZE_128: |
| 323 | ctx->key_2_l = readl_relaxed(&src_reg->key_2_l); | 325 | ctx->key_2_l = readl_relaxed(&src_reg->key_2_l); |
| 324 | ctx->key_2_r = readl_relaxed(&src_reg->key_2_r); | 326 | ctx->key_2_r = readl_relaxed(&src_reg->key_2_r); |
| 327 | /* Fall through */ | ||
| 325 | 328 | ||
| 326 | default: | 329 | default: |
| 327 | ctx->key_1_l = readl_relaxed(&src_reg->key_1_l); | 330 | ctx->key_1_l = readl_relaxed(&src_reg->key_1_l); |
| @@ -361,14 +364,17 @@ void cryp_restore_device_context(struct cryp_device_data *device_data, · 33 unmodified lines | |||
| 361 | case CRYP_KEY_SIZE_256: | 364 | case CRYP_KEY_SIZE_256: |
| 362 | writel_relaxed(ctx->key_4_l, ®->key_4_l); | 365 | writel_relaxed(ctx->key_4_l, ®->key_4_l); |
| 363 | writel_relaxed(ctx->key_4_r, ®->key_4_r); | 366 | writel_relaxed(ctx->key_4_r, ®->key_4_r); |
| 367 | /* Fall through */ | ||
| 364 | 368 | ||
| 365 | case CRYP_KEY_SIZE_192: | 369 | case CRYP_KEY_SIZE_192: |
| 366 | writel_relaxed(ctx->key_3_l, ®->key_3_l); | 370 | writel_relaxed(ctx->key_3_l, ®->key_3_l); |
| 367 | writel_relaxed(ctx->key_3_r, ®->key_3_r); | 371 | writel_relaxed(ctx->key_3_r, ®->key_3_r); |
| 372 | /* Fall through */ | ||
| 368 | 373 | ||
| 369 | case CRYP_KEY_SIZE_128: | 374 | case CRYP_KEY_SIZE_128: |
| 370 | writel_relaxed(ctx->key_2_l, ®->key_2_l); | 375 | writel_relaxed(ctx->key_2_l, ®->key_2_l); |
| 371 | writel_relaxed(ctx->key_2_r, ®->key_2_r); | 376 | writel_relaxed(ctx->key_2_r, ®->key_2_r); |
| 377 | /* Fall through */ | ||
| 372 | 378 | ||
| 373 | default: | 379 | default: |
| 374 | writel_relaxed(ctx->key_1_l, ®->key_1_l); | 380 | writel_relaxed(ctx->key_1_l, ®->key_1_l); |
| @@ -50,7 +50,7 @@ struct dw_edma_burst { · 49 unmodified lines | |||
| 50 | 50 | ||
| 51 | struct dw_edma_region { | 51 | struct dw_edma_region { |
| 52 | phys_addr_t paddr; | 52 | phys_addr_t paddr; |
| 53 | dma_addr_t vaddr; | 53 | void __iomem *vaddr; |
| 54 | size_t sz; | 54 | size_t sz; |
| 55 | }; | 55 | }; |
| 56 | 56 | ||
| @@ -130,19 +130,19 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, · 129 unmodified lines | |||
| 130 | chip->id = pdev->devfn; | 130 | chip->id = pdev->devfn; |
| 131 | chip->irq = pdev->irq; | 131 | chip->irq = pdev->irq; |
| 132 | 132 | ||
| 133 | dw->rg_region.vaddr = (dma_addr_t)pcim_iomap_table(pdev)[pdata->rg_bar]; | 133 | dw->rg_region.vaddr = pcim_iomap_table(pdev)[pdata->rg_bar]; |
| 134 | dw->rg_region.vaddr += pdata->rg_off; | 134 | dw->rg_region.vaddr += pdata->rg_off; |
| 135 | dw->rg_region.paddr = pdev->resource[pdata->rg_bar].start; | 135 | dw->rg_region.paddr = pdev->resource[pdata->rg_bar].start; |
| 136 | dw->rg_region.paddr += pdata->rg_off; | 136 | dw->rg_region.paddr += pdata->rg_off; |
| 137 | dw->rg_region.sz = pdata->rg_sz; | 137 | dw->rg_region.sz = pdata->rg_sz; |
| 138 | 138 | ||
| 139 | dw->ll_region.vaddr = (dma_addr_t)pcim_iomap_table(pdev)[pdata->ll_bar]; | 139 | dw->ll_region.vaddr = pcim_iomap_table(pdev)[pdata->ll_bar]; |
| 140 | dw->ll_region.vaddr += pdata->ll_off; | 140 | dw->ll_region.vaddr += pdata->ll_off; |
| 141 | dw->ll_region.paddr = pdev->resource[pdata->ll_bar].start; | 141 | dw->ll_region.paddr = pdev->resource[pdata->ll_bar].start; |
| 142 | dw->ll_region.paddr += pdata->ll_off; | 142 | dw->ll_region.paddr += pdata->ll_off; |
| 143 | dw->ll_region.sz = pdata->ll_sz; | 143 | dw->ll_region.sz = pdata->ll_sz; |
| 144 | 144 | ||
| 145 | dw->dt_region.vaddr = (dma_addr_t)pcim_iomap_table(pdev)[pdata->dt_bar]; | 145 | dw->dt_region.vaddr = pcim_iomap_table(pdev)[pdata->dt_bar]; |
| 146 | dw->dt_region.vaddr += pdata->dt_off; | 146 | dw->dt_region.vaddr += pdata->dt_off; |
| 147 | dw->dt_region.paddr = pdev->resource[pdata->dt_bar].start; | 147 | dw->dt_region.paddr = pdev->resource[pdata->dt_bar].start; |
| 148 | dw->dt_region.paddr += pdata->dt_off; | 148 | dw->dt_region.paddr += pdata->dt_off; |
| @@ -158,17 +158,17 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, · 9 unmodified lines | |||
| 158 | pci_dbg(pdev, "Mode:\t%s\n", | 158 | pci_dbg(pdev, "Mode:\t%s\n", |
| 159 | dw->mode == EDMA_MODE_LEGACY ? "Legacy" : "Unroll"); | 159 | dw->mode == EDMA_MODE_LEGACY ? "Legacy" : "Unroll"); |
| 160 | 160 | ||
| 161 | pci_dbg(pdev, "Registers:\tBAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%pa, p=%pa)\n", | 161 | pci_dbg(pdev, "Registers:\tBAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%p, p=%pa)\n", |
| 162 | pdata->rg_bar, pdata->rg_off, pdata->rg_sz, | 162 | pdata->rg_bar, pdata->rg_off, pdata->rg_sz, |
| 163 | &dw->rg_region.vaddr, &dw->rg_region.paddr); | 163 | dw->rg_region.vaddr, &dw->rg_region.paddr); |
| 164 | 164 | ||
| 165 | pci_dbg(pdev, "L. List:\tBAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%pa, p=%pa)\n", | 165 | pci_dbg(pdev, "L. List:\tBAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%p, p=%pa)\n", |
| 166 | pdata->ll_bar, pdata->ll_off, pdata->ll_sz, | 166 | pdata->ll_bar, pdata->ll_off, pdata->ll_sz, |
| 167 | &dw->ll_region.vaddr, &dw->ll_region.paddr); | 167 | dw->ll_region.vaddr, &dw->ll_region.paddr); |
| 168 | 168 | ||
| 169 | pci_dbg(pdev, "Data:\tBAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%pa, p=%pa)\n", | 169 | pci_dbg(pdev, "Data:\tBAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%p, p=%pa)\n", |
| 170 | pdata->dt_bar, pdata->dt_off, pdata->dt_sz, | 170 | pdata->dt_bar, pdata->dt_off, pdata->dt_sz, |
| 171 | &dw->dt_region.vaddr, &dw->dt_region.paddr); | 171 | dw->dt_region.vaddr, &dw->dt_region.paddr); |
| 172 | 172 | ||
| 173 | pci_dbg(pdev, "Nr. IRQs:\t%u\n", dw->nr_irqs); | 173 | pci_dbg(pdev, "Nr. IRQs:\t%u\n", dw->nr_irqs); |
| 174 | 174 | ||
| @@ -25,7 +25,7 @@ enum dw_edma_control { · 24 unmodified lines | |||
| 25 | 25 | ||
| 26 | static inline struct dw_edma_v0_regs __iomem *__dw_regs(struct dw_edma *dw) | 26 | static inline struct dw_edma_v0_regs __iomem *__dw_regs(struct dw_edma *dw) |
| 27 | { | 27 | { |
| 28 | return (struct dw_edma_v0_regs __iomem *)dw->rg_region.vaddr; | 28 | return dw->rg_region.vaddr; |
| 29 | } | 29 | } |
| 30 | 30 | ||
| 31 | #define SET(dw, name, value) \ | 31 | #define SET(dw, name, value) \ |
| @@ -192,13 +192,12 @@ u32 dw_edma_v0_core_status_abort_int(struct dw_edma *dw, enum dw_edma_dir dir) · 160 unmodified lines | |||
| 192 | static void dw_edma_v0_core_write_chunk(struct dw_edma_chunk *chunk) | 192 | static void dw_edma_v0_core_write_chunk(struct dw_edma_chunk *chunk) |
| 193 | { | 193 | { |
| 194 | struct dw_edma_burst *child; | 194 | struct dw_edma_burst *child; |
| 195 | struct dw_edma_v0_lli *lli; | 195 | struct dw_edma_v0_lli __iomem *lli; |
| 196 | struct dw_edma_v0_llp *llp; | 196 | struct dw_edma_v0_llp __iomem *llp; |
| 197 | u32 control = 0, i = 0; | 197 | u32 control = 0, i = 0; |
| 198 | u64 sar, dar, addr; | ||
| 199 | int j; | 198 | int j; |
| 200 | 199 | ||
| 201 | lli = (struct dw_edma_v0_lli *)chunk->ll_region.vaddr; | 200 | lli = chunk->ll_region.vaddr; |
| 202 | 201 | ||
| 203 | if (chunk->cb) | 202 | if (chunk->cb) |
| 204 | control = DW_EDMA_V0_CB; | 203 | control = DW_EDMA_V0_CB; |
| @@ -214,17 +213,15 @@ static void dw_edma_v0_core_write_chunk(struct dw_edma_chunk *chunk) · 9 unmodified lines | |||
| 214 | /* Transfer size */ | 213 | /* Transfer size */ |
| 215 | SET_LL(&lli[i].transfer_size, child->sz); | 214 | SET_LL(&lli[i].transfer_size, child->sz); |
| 216 | /* SAR - low, high */ | 215 | /* SAR - low, high */ |
| 217 | sar = cpu_to_le64(child->sar); | 216 | SET_LL(&lli[i].sar_low, lower_32_bits(child->sar)); |
| 218 | SET_LL(&lli[i].sar_low, lower_32_bits(sar)); | 217 | SET_LL(&lli[i].sar_high, upper_32_bits(child->sar)); |
| 219 | SET_LL(&lli[i].sar_high, upper_32_bits(sar)); | ||
| 220 | /* DAR - low, high */ | 218 | /* DAR - low, high */ |
| 221 | dar = cpu_to_le64(child->dar); | 219 | SET_LL(&lli[i].dar_low, lower_32_bits(child->dar)); |
| 222 | SET_LL(&lli[i].dar_low, lower_32_bits(dar)); | 220 | SET_LL(&lli[i].dar_high, upper_32_bits(child->dar)); |
| 223 | SET_LL(&lli[i].dar_high, upper_32_bits(dar)); | ||
| 224 | i++; | 221 | i++; |
| 225 | } | 222 | } |
| 226 | 223 | ||
| 227 | llp = (struct dw_edma_v0_llp *)&lli[i]; | 224 | llp = (void __iomem *)&lli[i]; |
| 228 | control = DW_EDMA_V0_LLP | DW_EDMA_V0_TCB; | 225 | control = DW_EDMA_V0_LLP | DW_EDMA_V0_TCB; |
| 229 | if (!chunk->cb) | 226 | if (!chunk->cb) |
| 230 | control |= DW_EDMA_V0_CB; | 227 | control |= DW_EDMA_V0_CB; |
| @@ -232,9 +229,8 @@ static void dw_edma_v0_core_write_chunk(struct dw_edma_chunk *chunk) · 1 unmodified line | |||
| 232 | /* Channel control */ | 229 | /* Channel control */ |
| 233 | SET_LL(&llp->control, control); | 230 | SET_LL(&llp->control, control); |
| 234 | /* Linked list - low, high */ | 231 | /* Linked list - low, high */ |
| 235 | addr = cpu_to_le64(chunk->ll_region.paddr); | 232 | SET_LL(&llp->llp_low, lower_32_bits(chunk->ll_region.paddr)); |
| 236 | SET_LL(&llp->llp_low, lower_32_bits(addr)); | 233 | SET_LL(&llp->llp_high, upper_32_bits(chunk->ll_region.paddr)); |
| 237 | SET_LL(&llp->llp_high, upper_32_bits(addr)); | ||
| 238 | } | 234 | } |
| 239 | 235 | ||
| 240 | void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first) | 236 | void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first) |
| @@ -242,7 +238,6 @@ void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first) · 1 unmodified line | |||
| 242 | struct dw_edma_chan *chan = chunk->chan; | 238 | struct dw_edma_chan *chan = chunk->chan; |
| 243 | struct dw_edma *dw = chan->chip->dw; | 239 | struct dw_edma *dw = chan->chip->dw; |
| 244 | u32 tmp; | 240 | u32 tmp; |
| 245 | u64 llp; | ||
| 246 | 241 | ||
| 247 | dw_edma_v0_core_write_chunk(chunk); | 242 | dw_edma_v0_core_write_chunk(chunk); |
| 248 | 243 | ||
| @@ -262,9 +257,10 @@ void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first) · 13 unmodified lines | |||
| 262 | SET_CH(dw, chan->dir, chan->id, ch_control1, | 257 | SET_CH(dw, chan->dir, chan->id, ch_control1, |
| 263 | (DW_EDMA_V0_CCS | DW_EDMA_V0_LLE)); | 258 | (DW_EDMA_V0_CCS | DW_EDMA_V0_LLE)); |
| 264 | /* Linked list - low, high */ | 259 | /* Linked list - low, high */ |
| 265 | llp = cpu_to_le64(chunk->ll_region.paddr); | 260 | SET_CH(dw, chan->dir, chan->id, llp_low, |
| 266 | SET_CH(dw, chan->dir, chan->id, llp_low, lower_32_bits(llp)); | 261 | lower_32_bits(chunk->ll_region.paddr)); |
| 267 | SET_CH(dw, chan->dir, chan->id, llp_high, upper_32_bits(llp)); | 262 | SET_CH(dw, chan->dir, chan->id, llp_high, |
| 263 | upper_32_bits(chunk->ll_region.paddr)); | ||
| 268 | } | 264 | } |
| 269 | /* Doorbell */ | 265 | /* Doorbell */ |
| 270 | SET_RW(dw, chan->dir, doorbell, | 266 | SET_RW(dw, chan->dir, doorbell, |
| @@ -14,7 +14,7 @@ · 13 unmodified lines | |||
| 14 | #include "dw-edma-core.h" | 14 | #include "dw-edma-core.h" |
| 15 | 15 | ||
| 16 | #define REGS_ADDR(name) \ | 16 | #define REGS_ADDR(name) \ |
| 17 | ((dma_addr_t *)®s->name) | 17 | ((void __force *)®s->name) |
| 18 | #define REGISTER(name) \ | 18 | #define REGISTER(name) \ |
| 19 | { #name, REGS_ADDR(name) } | 19 | { #name, REGS_ADDR(name) } |
| 20 | 20 | ||
| @@ -40,36 +40,37 @@ · 19 unmodified lines | |||
| 40 | 40 | ||
| 41 | static struct dentry *base_dir; | 41 | static struct dentry *base_dir; |
| 42 | static struct dw_edma *dw; | 42 | static struct dw_edma *dw; |
| 43 | static struct dw_edma_v0_regs *regs; | 43 | static struct dw_edma_v0_regs __iomem *regs; |
| 44 | 44 | ||
| 45 | static struct { | 45 | static struct { |
| 46 | void *start; | 46 | void __iomem *start; |
| 47 | void *end; | 47 | void __iomem *end; |
| 48 | } lim[2][EDMA_V0_MAX_NR_CH]; | 48 | } lim[2][EDMA_V0_MAX_NR_CH]; |
| 49 | 49 | ||
| 50 | struct debugfs_entries { | 50 | struct debugfs_entries { |
| 51 | char name[24]; | 51 | const char *name; |
| 52 | dma_addr_t *reg; | 52 | dma_addr_t *reg; |
| 53 | }; | 53 | }; |
| 54 | 54 | ||
| 55 | static int dw_edma_debugfs_u32_get(void *data, u64 *val) | 55 | static int dw_edma_debugfs_u32_get(void *data, u64 *val) |
| 56 | { | 56 | { |
| 57 | void __iomem *reg = (void __force __iomem *)data; | ||
| 57 | if (dw->mode == EDMA_MODE_LEGACY && | 58 | if (dw->mode == EDMA_MODE_LEGACY && |
| 58 | data >= (void *)®s->type.legacy.ch) { | 59 | reg >= (void __iomem *)®s->type.legacy.ch) { |
| 59 | void *ptr = (void *)®s->type.legacy.ch; | 60 | void __iomem *ptr = ®s->type.legacy.ch; |
| 60 | u32 viewport_sel = 0; | 61 | u32 viewport_sel = 0; |
| 61 | unsigned long flags; | 62 | unsigned long flags; |
| 62 | u16 ch; | 63 | u16 ch; |
| 63 | 64 | ||
| 64 | for (ch = 0; ch < dw->wr_ch_cnt; ch++) | 65 | for (ch = 0; ch < dw->wr_ch_cnt; ch++) |
| 65 | if (lim[0][ch].start >= data && data < lim[0][ch].end) { | 66 | if (lim[0][ch].start >= reg && reg < lim[0][ch].end) { |
| 66 | ptr += (data - lim[0][ch].start); | 67 | ptr += (reg - lim[0][ch].start); |
| 67 | goto legacy_sel_wr; | 68 | goto legacy_sel_wr; |
| 68 | } | 69 | } |
| 69 | 70 | ||
| 70 | for (ch = 0; ch < dw->rd_ch_cnt; ch++) | 71 | for (ch = 0; ch < dw->rd_ch_cnt; ch++) |
| 71 | if (lim[1][ch].start >= data && data < lim[1][ch].end) { | 72 | if (lim[1][ch].start >= reg && reg < lim[1][ch].end) { |
| 72 | ptr += (data - lim[1][ch].start); | 73 | ptr += (reg - lim[1][ch].start); |
| 73 | goto legacy_sel_rd; | 74 | goto legacy_sel_rd; |
| 74 | } | 75 | } |
| 75 | 76 | ||
| @@ -86,7 +87,7 @@ legacy_sel_wr: · 10 unmodified lines | |||
| 86 | 87 | ||
| 87 | raw_spin_unlock_irqrestore(&dw->lock, flags); | 88 | raw_spin_unlock_irqrestore(&dw->lock, flags); |
| 88 | } else { | 89 | } else { |
| 89 | *val = readl(data); | 90 | *val = readl(reg); |
| 90 | } | 91 | } |
| 91 | 92 | ||
| 92 | return 0; | 93 | return 0; |
| @@ -105,7 +106,7 @@ static void dw_edma_debugfs_create_x32(const struct debugfs_entries entries[], · 12 unmodified lines | |||
| 105 | } | 106 | } |
| 106 | } | 107 | } |
| 107 | 108 | ||
| 108 | static void dw_edma_debugfs_regs_ch(struct dw_edma_v0_ch_regs *regs, | 109 | static void dw_edma_debugfs_regs_ch(struct dw_edma_v0_ch_regs __iomem *regs, |
| 109 | struct dentry *dir) | 110 | struct dentry *dir) |
| 110 | { | 111 | { |
| 111 | int nr_entries; | 112 | int nr_entries; |
| @@ -288,7 +289,7 @@ void dw_edma_v0_debugfs_on(struct dw_edma_chip *chip) · 176 unmodified lines | |||
| 288 | if (!dw) | 289 | if (!dw) |
| 289 | return; | 290 | return; |
| 290 | 291 | ||
| 291 | regs = (struct dw_edma_v0_regs *)dw->rg_region.vaddr; | 292 | regs = dw->rg_region.vaddr; |
| 292 | if (!regs) | 293 | if (!regs) |
| 293 | return; | 294 | return; |
| 294 | 295 | ||
| @@ -142,7 +142,7 @@ enum d40_events { · 141 unmodified lines | |||
| 142 | * when the DMA hw is powered off. | 142 | * when the DMA hw is powered off. |
| 143 | * TODO: Add save/restore of D40_DREG_GCC on dma40 v3 or later, if that works. | 143 | * TODO: Add save/restore of D40_DREG_GCC on dma40 v3 or later, if that works. |
| 144 | */ | 144 | */ |
| 145 | static u32 d40_backup_regs[] = { | 145 | static __maybe_unused u32 d40_backup_regs[] = { |
| 146 | D40_DREG_LCPA, | 146 | D40_DREG_LCPA, |
| 147 | D40_DREG_LCLA, | 147 | D40_DREG_LCLA, |
| 148 | D40_DREG_PRMSE, | 148 | D40_DREG_PRMSE, |
| @@ -211,7 +211,7 @@ static u32 d40_backup_regs_v4b[] = { · 62 unmodified lines | |||
| 211 | 211 | ||
| 212 | #define BACKUP_REGS_SZ_V4B ARRAY_SIZE(d40_backup_regs_v4b) | 212 | #define BACKUP_REGS_SZ_V4B ARRAY_SIZE(d40_backup_regs_v4b) |
| 213 | 213 | ||
| 214 | static u32 d40_backup_regs_chan[] = { | 214 | static __maybe_unused u32 d40_backup_regs_chan[] = { |
| 215 | D40_CHAN_REG_SSCFG, | 215 | D40_CHAN_REG_SSCFG, |
| 216 | D40_CHAN_REG_SSELT, | 216 | D40_CHAN_REG_SSELT, |
| 217 | D40_CHAN_REG_SSPTR, | 217 | D40_CHAN_REG_SSPTR, |
| @@ -1366,7 +1366,7 @@ static irqreturn_t stm32_mdma_irq_handler(int irq, void *devid) · 1365 unmodified lines | |||
| 1366 | 1366 | ||
| 1367 | chan = &dmadev->chan[id]; | 1367 | chan = &dmadev->chan[id]; |
| 1368 | if (!chan) { | 1368 | if (!chan) { |
| 1369 | dev_err(chan2dev(chan), "MDMA channel not initialized\n"); | 1369 | dev_dbg(mdma2dev(dmadev), "MDMA channel not initialized\n"); |
| 1370 | goto exit; | 1370 | goto exit; |
| 1371 | } | 1371 | } |
| 1372 | 1372 | ||
| @@ -712,7 +712,7 @@ static struct dma_chan *tegra_dma_of_xlate(struct of_phandle_args *dma_spec, · 711 unmodified lines | |||
| 712 | return chan; | 712 | return chan; |
| 713 | } | 713 | } |
| 714 | 714 | ||
| 715 | static int tegra_adma_runtime_suspend(struct device *dev) | 715 | static int __maybe_unused tegra_adma_runtime_suspend(struct device *dev) |
| 716 | { | 716 | { |
| 717 | struct tegra_adma *tdma = dev_get_drvdata(dev); | 717 | struct tegra_adma *tdma = dev_get_drvdata(dev); |
| 718 | struct tegra_adma_chan_regs *ch_reg; | 718 | struct tegra_adma_chan_regs *ch_reg; |
| @@ -744,7 +744,7 @@ clk_disable: · 25 unmodified lines | |||
| 744 | return 0; | 744 | return 0; |
| 745 | } | 745 | } |
| 746 | 746 | ||
| 747 | static int tegra_adma_runtime_resume(struct device *dev) | 747 | static int __maybe_unused tegra_adma_runtime_resume(struct device *dev) |
| 748 | { | 748 | { |
| 749 | struct tegra_adma *tdma = dev_get_drvdata(dev); | 749 | struct tegra_adma *tdma = dev_get_drvdata(dev); |
| 750 | struct tegra_adma_chan_regs *ch_reg; | 750 | struct tegra_adma_chan_regs *ch_reg; |
| @@ -1234,7 +1234,7 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_interleaved( · 1233 unmodified lines | |||
| 1234 | if (src_icg) { | 1234 | if (src_icg) { |
| 1235 | d->ccr |= CCR_SRC_AMODE_DBLIDX; | 1235 | d->ccr |= CCR_SRC_AMODE_DBLIDX; |
| 1236 | d->ei = 1; | 1236 | d->ei = 1; |
| 1237 | d->fi = src_icg; | 1237 | d->fi = src_icg + 1; |
| 1238 | } else if (xt->src_inc) { | 1238 | } else if (xt->src_inc) { |
| 1239 | d->ccr |= CCR_SRC_AMODE_POSTINC; | 1239 | d->ccr |= CCR_SRC_AMODE_POSTINC; |
| 1240 | d->fi = 0; | 1240 | d->fi = 0; |
| @@ -1249,7 +1249,7 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_interleaved( · 8 unmodified lines | |||
| 1249 | if (dst_icg) { | 1249 | if (dst_icg) { |
| 1250 | d->ccr |= CCR_DST_AMODE_DBLIDX; | 1250 | d->ccr |= CCR_DST_AMODE_DBLIDX; |
| 1251 | sg->ei = 1; | 1251 | sg->ei = 1; |
| 1252 | sg->fi = dst_icg; | 1252 | sg->fi = dst_icg + 1; |
| 1253 | } else if (xt->dst_inc) { | 1253 | } else if (xt->dst_inc) { |
| 1254 | d->ccr |= CCR_DST_AMODE_POSTINC; | 1254 | d->ccr |= CCR_DST_AMODE_POSTINC; |
| 1255 | sg->fi = 0; | 1255 | sg->fi = 0; |
| @@ -957,7 +957,7 @@ static void set_broadcast_channel(struct fw_device *device, int generation) · 956 unmodified lines | |||
| 957 | device->bc_implemented = BC_IMPLEMENTED; | 957 | device->bc_implemented = BC_IMPLEMENTED; |
| 958 | break; | 958 | break; |
| 959 | } | 959 | } |
| 960 | /* else fall through to case address error */ | 960 | /* else, fall through - to case address error */ |
| 961 | case RCODE_ADDRESS_ERROR: | 961 | case RCODE_ADDRESS_ERROR: |
| 962 | device->bc_implemented = BC_UNIMPLEMENTED; | 962 | device->bc_implemented = BC_UNIMPLEMENTED; |
| 963 | } | 963 | } |
| @@ -284,7 +284,7 @@ static int manage_channel(struct fw_card *card, int irm_id, int generation, · 283 unmodified lines | |||
| 284 | if ((data[0] & bit) == (data[1] & bit)) | 284 | if ((data[0] & bit) == (data[1] & bit)) |
| 285 | continue; | 285 | continue; |
| 286 | 286 | ||
| 287 | /* 1394-1995 IRM, fall through to retry. */ | 287 | /* fall through - It's a 1394-1995 IRM, retry. */ |
| 288 | default: | 288 | default: |
| 289 | if (retry) { | 289 | if (retry) { |
| 290 | retry--; | 290 | retry--; |
| @@ -54,6 +54,7 @@ static u32 *count_ports(u32 *sid, int *total_port_count, int *child_port_count) · 53 unmodified lines | |||
| 54 | switch (port_type) { | 54 | switch (port_type) { |
| 55 | case SELFID_PORT_CHILD: | 55 | case SELFID_PORT_CHILD: |
| 56 | (*child_port_count)++; | 56 | (*child_port_count)++; |
| 57 | /* fall through */ | ||
| 57 | case SELFID_PORT_PARENT: | 58 | case SELFID_PORT_PARENT: |
| 58 | case SELFID_PORT_NCONN: | 59 | case SELFID_PORT_NCONN: |
| 59 | (*total_port_count)++; | 60 | (*total_port_count)++; |
| @@ -157,7 +157,7 @@ config DMI_SCAN_MACHINE_NON_EFI_FALLBACK · 156 unmodified lines | |||
| 157 | 157 | ||
| 158 | config ISCSI_IBFT_FIND | 158 | config ISCSI_IBFT_FIND |
| 159 | bool "iSCSI Boot Firmware Table Attributes" | 159 | bool "iSCSI Boot Firmware Table Attributes" |
| 160 | depends on X86 && ACPI | 160 | depends on X86 && ISCSI_IBFT |
| 161 | default n | 161 | default n |
| 162 | help | 162 | help |
| 163 | This option enables the kernel to find the region of memory | 163 | This option enables the kernel to find the region of memory |
| @@ -168,7 +168,8 @@ config ISCSI_IBFT_FIND · 4 unmodified lines | |||
| 168 | config ISCSI_IBFT | 168 | config ISCSI_IBFT |
| 169 | tristate "iSCSI Boot Firmware Table Attributes module" | 169 | tristate "iSCSI Boot Firmware Table Attributes module" |
| 170 | select ISCSI_BOOT_SYSFS | 170 | select ISCSI_BOOT_SYSFS |
| 171 | depends on ISCSI_IBFT_FIND && SCSI && SCSI_LOWLEVEL | 171 | select ISCSI_IBFT_FIND if X86 |
| 172 | depends on ACPI && SCSI && SCSI_LOWLEVEL | ||
| 172 | default n | 173 | default n |
| 173 | help | 174 | help |
| 174 | This option enables support for detection and exposing of iSCSI | 175 | This option enables support for detection and exposing of iSCSI |
| @@ -927,17 +927,33 @@ fail: · 926 unmodified lines | |||
| 927 | return status; | 927 | return status; |
| 928 | } | 928 | } |
| 929 | 929 | ||
| 930 | #define GET_EFI_CONFIG_TABLE(bits) \ | ||
| 931 | static void *get_efi_config_table##bits(efi_system_table_t *_sys_table, \ | ||
| 932 | efi_guid_t guid) \ | ||
| 933 | { \ | ||
| 934 | efi_system_table_##bits##_t *sys_table; \ | ||
| 935 | efi_config_table_##bits##_t *tables; \ | ||
| 936 | int i; \ | ||
| 937 | \ | ||
| 938 | sys_table = (typeof(sys_table))_sys_table; \ | ||
| 939 | tables = (typeof(tables))(unsigned long)sys_table->tables; \ | ||
| 940 | \ | ||
| 941 | for (i = 0; i < sys_table->nr_tables; i++) { \ | ||
| 942 | if (efi_guidcmp(tables[i].guid, guid) != 0) \ | ||
| 943 | continue; \ | ||
| 944 | \ | ||
| 945 | return (void *)(unsigned long)tables[i].table; \ | ||
| 946 | } \ | ||
| 947 | \ | ||
| 948 | return NULL; \ | ||
| 949 | } | ||
| 950 | GET_EFI_CONFIG_TABLE(32) | ||
| 951 | GET_EFI_CONFIG_TABLE(64) | ||
| 952 | |||
| 930 | void *get_efi_config_table(efi_system_table_t *sys_table, efi_guid_t guid) | 953 | void *get_efi_config_table(efi_system_table_t *sys_table, efi_guid_t guid) |
| 931 | { | 954 | { |
| 932 | efi_config_table_t *tables = (efi_config_table_t *)sys_table->tables; | 955 | if (efi_is_64bit()) |
| 933 | int i; | 956 | return get_efi_config_table64(sys_table, guid); |
| 934 | 957 | else | |
| 935 | for (i = 0; i < sys_table->nr_tables; i++) { | 958 | return get_efi_config_table32(sys_table, guid); |
| 936 | if (efi_guidcmp(tables[i].guid, guid) != 0) | ||
| 937 | continue; | ||
| 938 | |||
| 939 | return (void *)tables[i].table; | ||
| 940 | } | ||
| 941 | |||
| 942 | return NULL; | ||
| 943 | } | 959 | } |
| @@ -84,6 +84,10 @@ MODULE_DESCRIPTION("sysfs interface to BIOS iBFT information"); · 83 unmodified lines | |||
| 84 | MODULE_LICENSE("GPL"); | 84 | MODULE_LICENSE("GPL"); |
| 85 | MODULE_VERSION(IBFT_ISCSI_VERSION); | 85 | MODULE_VERSION(IBFT_ISCSI_VERSION); |
| 86 | 86 | ||
| 87 | #ifndef CONFIG_ISCSI_IBFT_FIND | ||
| 88 | struct acpi_table_ibft *ibft_addr; | ||
| 89 | #endif | ||
| 90 | |||
| 87 | struct ibft_hdr { | 91 | struct ibft_hdr { |
| 88 | u8 id; | 92 | u8 id; |
| 89 | u8 version; | 93 | u8 version; |
| @@ -40,6 +40,7 @@ config ALTERA_PR_IP_CORE_PLAT · 39 unmodified lines | |||
| 40 | config FPGA_MGR_ALTERA_PS_SPI | 40 | config FPGA_MGR_ALTERA_PS_SPI |
| 41 | tristate "Altera FPGA Passive Serial over SPI" | 41 | tristate "Altera FPGA Passive Serial over SPI" |
| 42 | depends on SPI | 42 | depends on SPI |
| 43 | select BITREVERSE | ||
| 43 | help | 44 | help |
| 44 | FPGA manager driver support for Altera Arria/Cyclone/Stratix | 45 | FPGA manager driver support for Altera Arria/Cyclone/Stratix |
| 45 | using the passive serial interface over SPI. | 46 | using the passive serial interface over SPI. |
| @@ -956,9 +956,11 @@ static int lineevent_create(struct gpio_device *gdev, void __user *ip) · 955 unmodified lines | |||
| 956 | } | 956 | } |
| 957 | 957 | ||
| 958 | if (eflags & GPIOEVENT_REQUEST_RISING_EDGE) | 958 | if (eflags & GPIOEVENT_REQUEST_RISING_EDGE) |
| 959 | irqflags |= IRQF_TRIGGER_RISING; | 959 | irqflags |= test_bit(FLAG_ACTIVE_LOW, &desc->flags) ? |
| 960 | IRQF_TRIGGER_FALLING : IRQF_TRIGGER_RISING; | ||
| 960 | if (eflags & GPIOEVENT_REQUEST_FALLING_EDGE) | 961 | if (eflags & GPIOEVENT_REQUEST_FALLING_EDGE) |
| 961 | irqflags |= IRQF_TRIGGER_FALLING; | 962 | irqflags |= test_bit(FLAG_ACTIVE_LOW, &desc->flags) ? |
| 963 | IRQF_TRIGGER_RISING : IRQF_TRIGGER_FALLING; | ||
| 962 | irqflags |= IRQF_ONESHOT; | 964 | irqflags |= IRQF_ONESHOT; |
| 963 | 965 | ||
| 964 | INIT_KFIFO(le->events); | 966 | INIT_KFIFO(le->events); |
| @@ -1392,12 +1394,17 @@ int gpiochip_add_data_with_key(struct gpio_chip *chip, void *data, · 427 unmodified lines | |||
| 1392 | for (i = 0; i < chip->ngpio; i++) { | 1394 | for (i = 0; i < chip->ngpio; i++) { |
| 1393 | struct gpio_desc *desc = &gdev->descs[i]; | 1395 | struct gpio_desc *desc = &gdev->descs[i]; |
| 1394 | 1396 | ||
| 1395 | if (chip->get_direction && gpiochip_line_is_valid(chip, i)) | 1397 | if (chip->get_direction && gpiochip_line_is_valid(chip, i)) { |
| 1396 | desc->flags = !chip->get_direction(chip, i) ? | 1398 | if (!chip->get_direction(chip, i)) |
| 1397 | (1 << FLAG_IS_OUT) : 0; | 1399 | set_bit(FLAG_IS_OUT, &desc->flags); |
| 1398 | else | 1400 | else |
| 1399 | desc->flags = !chip->direction_input ? | 1401 | clear_bit(FLAG_IS_OUT, &desc->flags); |
| 1400 | (1 << FLAG_IS_OUT) : 0; | 1402 | } else { |
| 1403 | if (!chip->direction_input) | ||
| 1404 | set_bit(FLAG_IS_OUT, &desc->flags); | ||
| 1405 | else | ||
| 1406 | clear_bit(FLAG_IS_OUT, &desc->flags); | ||
| 1407 | } | ||
| 1401 | } | 1408 | } |
| 1402 | 1409 | ||
| 1403 | acpi_gpiochip_add(chip); | 1410 | acpi_gpiochip_add(chip); |
| @@ -394,7 +394,7 @@ config DRM_R128 · 393 unmodified lines | |||
| 394 | config DRM_I810 | 394 | config DRM_I810 |
| 395 | tristate "Intel I810" | 395 | tristate "Intel I810" |
| 396 | # !PREEMPT because of missing ioctl locking | 396 | # !PREEMPT because of missing ioctl locking |
| 397 | depends on DRM && AGP && AGP_INTEL && (!PREEMPT || BROKEN) | 397 | depends on DRM && AGP && AGP_INTEL && (!PREEMPTION || BROKEN) |
| 398 | help | 398 | help |
| 399 | Choose this option if you have an Intel I810 graphics card. If M is | 399 | Choose this option if you have an Intel I810 graphics card. If M is |
| 400 | selected, the module will be called i810. AGP support is required | 400 | selected, the module will be called i810. AGP support is required |
| @@ -1140,7 +1140,8 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( · 1139 unmodified lines | |||
| 1140 | adev->asic_type != CHIP_FIJI && | 1140 | adev->asic_type != CHIP_FIJI && |
| 1141 | adev->asic_type != CHIP_POLARIS10 && | 1141 | adev->asic_type != CHIP_POLARIS10 && |
| 1142 | adev->asic_type != CHIP_POLARIS11 && | 1142 | adev->asic_type != CHIP_POLARIS11 && |
| 1143 | adev->asic_type != CHIP_POLARIS12) ? | 1143 | adev->asic_type != CHIP_POLARIS12 && |
| 1144 | adev->asic_type != CHIP_VEGAM) ? | ||
| 1144 | VI_BO_SIZE_ALIGN : 1; | 1145 | VI_BO_SIZE_ALIGN : 1; |
| 1145 | 1146 | ||
| 1146 | mapping_flags = AMDGPU_VM_PAGE_READABLE; | 1147 | mapping_flags = AMDGPU_VM_PAGE_READABLE; |
| @@ -1044,29 +1044,27 @@ static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p, · 1043 unmodified lines | |||
| 1044 | return r; | 1044 | return r; |
| 1045 | } | 1045 | } |
| 1046 | 1046 | ||
| 1047 | fence = amdgpu_ctx_get_fence(ctx, entity, | 1047 | fence = amdgpu_ctx_get_fence(ctx, entity, deps[i].handle); |
| 1048 | deps[i].handle); | 1048 | amdgpu_ctx_put(ctx); |
| 1049 | |||
| 1050 | if (IS_ERR(fence)) | ||
| 1051 | return PTR_ERR(fence); | ||
| 1052 | else if (!fence) | ||
| 1053 | continue; | ||
| 1049 | 1054 | ||
| 1050 | if (chunk->chunk_id == AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES) { | 1055 | if (chunk->chunk_id == AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES) { |
| 1051 | struct drm_sched_fence *s_fence = to_drm_sched_fence(fence); | 1056 | struct drm_sched_fence *s_fence; |
| 1052 | struct dma_fence *old = fence; | 1057 | struct dma_fence *old = fence; |
| 1053 | 1058 | ||
| 1059 | s_fence = to_drm_sched_fence(fence); | ||
| 1054 | fence = dma_fence_get(&s_fence->scheduled); | 1060 | fence = dma_fence_get(&s_fence->scheduled); |
| 1055 | dma_fence_put(old); | 1061 | dma_fence_put(old); |
| 1056 | } | 1062 | } |
| 1057 | 1063 | ||
| 1058 | if (IS_ERR(fence)) { | 1064 | r = amdgpu_sync_fence(p->adev, &p->job->sync, fence, true); |
| 1059 | r = PTR_ERR(fence); | 1065 | dma_fence_put(fence); |
| 1060 | amdgpu_ctx_put(ctx); | 1066 | if (r) |
| 1061 | return r; | 1067 | return r; |
| 1062 | } else if (fence) { | ||
| 1063 | r = amdgpu_sync_fence(p->adev, &p->job->sync, fence, | ||
| 1064 | true); | ||
| 1065 | dma_fence_put(fence); | ||
| 1066 | amdgpu_ctx_put(ctx); | ||
| 1067 | if (r) | ||
| 1068 | return r; | ||
| 1069 | } | ||
| 1070 | } | 1068 | } |
| 1071 | return 0; | 1069 | return 0; |
| 1072 | } | 1070 | } |
| @@ -707,7 +707,7 @@ static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf, · 706 unmodified lines | |||
| 707 | thread = (*pos & GENMASK_ULL(59, 52)) >> 52; | 707 | thread = (*pos & GENMASK_ULL(59, 52)) >> 52; |
| 708 | bank = (*pos & GENMASK_ULL(61, 60)) >> 60; | 708 | bank = (*pos & GENMASK_ULL(61, 60)) >> 60; |
| 709 | 709 | ||
| 710 | data = kmalloc_array(1024, sizeof(*data), GFP_KERNEL); | 710 | data = kcalloc(1024, sizeof(*data), GFP_KERNEL); |
| 711 | if (!data) | 711 | if (!data) |
| 712 | return -ENOMEM; | 712 | return -ENOMEM; |
| 713 | 713 | ||
| @@ -149,7 +149,7 @@ struct amdgpu_mgpu_info mgpu_info = { · 148 unmodified lines | |||
| 149 | .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), | 149 | .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), |
| 150 | }; | 150 | }; |
| 151 | int amdgpu_ras_enable = -1; | 151 | int amdgpu_ras_enable = -1; |
| 152 | uint amdgpu_ras_mask = 0xffffffff; | 152 | uint amdgpu_ras_mask = 0xfffffffb; |
| 153 | 153 | ||
| 154 | /** | 154 | /** |
| 155 | * DOC: vramlimit (int) | 155 | * DOC: vramlimit (int) |
| @@ -32,7 +32,6 @@ struct amdgpu_gds { · 31 unmodified lines | |||
| 32 | uint32_t gws_size; | 32 | uint32_t gws_size; |
| 33 | uint32_t oa_size; | 33 | uint32_t oa_size; |
| 34 | uint32_t gds_compute_max_wave_id; | 34 | uint32_t gds_compute_max_wave_id; |
| 35 | uint32_t vgt_gs_max_wave_id; | ||
| 36 | }; | 35 | }; |
| 37 | 36 | ||
| 38 | struct amdgpu_gds_reg_offset { | 37 | struct amdgpu_gds_reg_offset { |
| @@ -159,12 +159,16 @@ static ssize_t amdgpu_get_dpm_state(struct device *dev, · 158 unmodified lines | |||
| 159 | struct amdgpu_device *adev = ddev->dev_private; | 159 | struct amdgpu_device *adev = ddev->dev_private; |
| 160 | enum amd_pm_state_type pm; | 160 | enum amd_pm_state_type pm; |
| 161 | 161 | ||
| 162 | if (is_support_sw_smu(adev) && adev->smu.ppt_funcs->get_current_power_state) | 162 | if (is_support_sw_smu(adev)) { |
| 163 | pm = amdgpu_smu_get_current_power_state(adev); | 163 | if (adev->smu.ppt_funcs->get_current_power_state) |
| 164 | else if (adev->powerplay.pp_funcs->get_current_power_state) | 164 | pm = amdgpu_smu_get_current_power_state(adev); |
| 165 | else | ||
| 166 | pm = adev->pm.dpm.user_state; | ||
| 167 | } else if (adev->powerplay.pp_funcs->get_current_power_state) { | ||
| 165 | pm = amdgpu_dpm_get_current_power_state(adev); | 168 | pm = amdgpu_dpm_get_current_power_state(adev); |
| 166 | else | 169 | } else { |
| 167 | pm = adev->pm.dpm.user_state; | 170 | pm = adev->pm.dpm.user_state; |
| 171 | } | ||
| 168 | 172 | ||
| 169 | return snprintf(buf, PAGE_SIZE, "%s\n", | 173 | return snprintf(buf, PAGE_SIZE, "%s\n", |
| 170 | (pm == POWER_STATE_TYPE_BATTERY) ? "battery" : | 174 | (pm == POWER_STATE_TYPE_BATTERY) ? "battery" : |
| @@ -191,7 +195,11 @@ static ssize_t amdgpu_set_dpm_state(struct device *dev, · 20 unmodified lines | |||
| 191 | goto fail; | 195 | goto fail; |
| 192 | } | 196 | } |
| 193 | 197 | ||
| 194 | if (adev->powerplay.pp_funcs->dispatch_tasks) { | 198 | if (is_support_sw_smu(adev)) { |
| 199 | mutex_lock(&adev->pm.mutex); | ||
| 200 | adev->pm.dpm.user_state = state; | ||
| 201 | mutex_unlock(&adev->pm.mutex); | ||
| 202 | } else if (adev->powerplay.pp_funcs->dispatch_tasks) { | ||
| 195 | amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state); | 203 | amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state); |
| 196 | } else { | 204 | } else { |
| 197 | mutex_lock(&adev->pm.mutex); | 205 | mutex_lock(&adev->pm.mutex); |
| @@ -1734,7 +1742,7 @@ static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev, · 1536 unmodified lines | |||
| 1734 | return -EINVAL; | 1742 | return -EINVAL; |
| 1735 | 1743 | ||
| 1736 | if (is_support_sw_smu(adev)) { | 1744 | if (is_support_sw_smu(adev)) { |
| 1737 | err = smu_get_current_rpm(&adev->smu, &speed); | 1745 | err = smu_get_fan_speed_rpm(&adev->smu, &speed); |
| 1738 | if (err) | 1746 | if (err) |
| 1739 | return err; | 1747 | return err; |
| 1740 | } else if (adev->powerplay.pp_funcs->get_fan_speed_rpm) { | 1748 | } else if (adev->powerplay.pp_funcs->get_fan_speed_rpm) { |
| @@ -1794,7 +1802,7 @@ static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev, · 53 unmodified lines | |||
| 1794 | return -EINVAL; | 1802 | return -EINVAL; |
| 1795 | 1803 | ||
| 1796 | if (is_support_sw_smu(adev)) { | 1804 | if (is_support_sw_smu(adev)) { |
| 1797 | err = smu_get_current_rpm(&adev->smu, &rpm); | 1805 | err = smu_get_fan_speed_rpm(&adev->smu, &rpm); |
| 1798 | if (err) | 1806 | if (err) |
| 1799 | return err; | 1807 | return err; |
| 1800 | } else if (adev->powerplay.pp_funcs->get_fan_speed_rpm) { | 1808 | } else if (adev->powerplay.pp_funcs->get_fan_speed_rpm) { |
| @@ -3067,28 +3075,44 @@ static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *a · 1266 unmodified lines | |||
| 3067 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size)) | 3075 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size)) |
| 3068 | seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64); | 3076 | seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64); |
| 3069 | 3077 | ||
| 3070 | /* UVD clocks */ | 3078 | if (adev->asic_type > CHIP_VEGA20) { |
| 3071 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) { | 3079 | /* VCN clocks */ |
| 3072 | if (!value) { | 3080 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_POWER_STATE, (void *)&value, &size)) { |
| 3073 | seq_printf(m, "UVD: Disabled\n"); | 3081 | if (!value) { |
| 3074 | } else { | 3082 | seq_printf(m, "VCN: Disabled\n"); |
| 3075 | seq_printf(m, "UVD: Enabled\n"); | 3083 | } else { |
| 3076 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size)) | 3084 | seq_printf(m, "VCN: Enabled\n"); |
| 3077 | seq_printf(m, "\t%u MHz (DCLK)\n", value/100); | 3085 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size)) |
| 3078 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size)) | 3086 | seq_printf(m, "\t%u MHz (DCLK)\n", value/100); |
| 3079 | seq_printf(m, "\t%u MHz (VCLK)\n", value/100); | 3087 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size)) |
| 3088 | seq_printf(m, "\t%u MHz (VCLK)\n", value/100); | ||
| 3089 | } | ||
| 3080 | } | 3090 | } |
| 3081 | } | 3091 | seq_printf(m, "\n"); |
| 3082 | seq_printf(m, "\n"); | 3092 | } else { |
| 3093 | /* UVD clocks */ | ||
| 3094 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) { | ||
| 3095 | if (!value) { | ||
| 3096 | seq_printf(m, "UVD: Disabled\n"); | ||
| 3097 | } else { | ||
| 3098 | seq_printf(m, "UVD: Enabled\n"); | ||
| 3099 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size)) | ||
| 3100 | seq_printf(m, "\t%u MHz (DCLK)\n", value/100); | ||
| 3101 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size)) | ||
| 3102 | seq_printf(m, "\t%u MHz (VCLK)\n", value/100); | ||
| 3103 | } | ||
| 3104 | } | ||
| 3105 | seq_printf(m, "\n"); | ||
| 3083 | 3106 | ||
| 3084 | /* VCE clocks */ | 3107 | /* VCE clocks */ |
| 3085 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) { | 3108 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) { |
| 3086 | if (!value) { | 3109 | if (!value) { |
| 3087 | seq_printf(m, "VCE: Disabled\n"); | 3110 | seq_printf(m, "VCE: Disabled\n"); |
| 3088 | } else { | 3111 | } else { |
| 3089 | seq_printf(m, "VCE: Enabled\n"); | 3112 | seq_printf(m, "VCE: Enabled\n"); |
| 3090 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size)) | 3113 | if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size)) |
| 3091 | seq_printf(m, "\t%u MHz (ECCLK)\n", value/100); | 3114 | seq_printf(m, "\t%u MHz (ECCLK)\n", value/100); |
| 3115 | } | ||
| 3092 | } | 3116 | } |
| 3093 | } | 3117 | } |
| 3094 | 3118 | ||
| @@ -136,11 +136,6 @@ static int amdgpu_ras_reserve_vram(struct amdgpu_device *adev, · 135 unmodified lines | |||
| 136 | static int amdgpu_ras_release_vram(struct amdgpu_device *adev, | 136 | static int amdgpu_ras_release_vram(struct amdgpu_device *adev, |
| 137 | struct amdgpu_bo **bo_ptr); | 137 | struct amdgpu_bo **bo_ptr); |
| 138 | 138 | ||
| 139 | static void amdgpu_ras_self_test(struct amdgpu_device *adev) | ||
| 140 | { | ||
| 141 | /* TODO */ | ||
| 142 | } | ||
| 143 | |||
| 144 | static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf, | 139 | static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf, |
| 145 | size_t size, loff_t *pos) | 140 | size_t size, loff_t *pos) |
| 146 | { | 141 | { |
| @@ -689,6 +684,12 @@ int amdgpu_ras_error_inject(struct amdgpu_device *adev, · 542 unmodified lines | |||
| 689 | if (!obj) | 684 | if (!obj) |
| 690 | return -EINVAL; | 685 | return -EINVAL; |
| 691 | 686 | ||
| 687 | if (block_info.block_id != TA_RAS_BLOCK__UMC) { | ||
| 688 | DRM_INFO("%s error injection is not supported yet\n", | ||
| 689 | ras_block_str(info->head.block)); | ||
| 690 | return -EINVAL; | ||
| 691 | } | ||
| 692 | |||
| 692 | ret = psp_ras_trigger_error(&adev->psp, &block_info); | 693 | ret = psp_ras_trigger_error(&adev->psp, &block_info); |
| 693 | if (ret) | 694 | if (ret) |
| 694 | DRM_ERROR("RAS ERROR: inject %s error failed ret %d\n", | 695 | DRM_ERROR("RAS ERROR: inject %s error failed ret %d\n", |
| @@ -1557,6 +1558,12 @@ int amdgpu_ras_init(struct amdgpu_device *adev) · 862 unmodified lines | |||
| 1557 | 1558 | ||
| 1558 | amdgpu_ras_check_supported(adev, &con->hw_supported, | 1559 | amdgpu_ras_check_supported(adev, &con->hw_supported, |
| 1559 | &con->supported); | 1560 | &con->supported); |
| 1561 | if (!con->hw_supported) { | ||
| 1562 | amdgpu_ras_set_context(adev, NULL); | ||
| 1563 | kfree(con); | ||
| 1564 | return 0; | ||
| 1565 | } | ||
| 1566 | |||
| 1560 | con->features = 0; | 1567 | con->features = 0; |
| 1561 | INIT_LIST_HEAD(&con->head); | 1568 | INIT_LIST_HEAD(&con->head); |
| 1562 | /* Might need get this flag from vbios. */ | 1569 | /* Might need get this flag from vbios. */ |
| @@ -1570,8 +1577,6 @@ int amdgpu_ras_init(struct amdgpu_device *adev) · 7 unmodified lines | |||
| 1570 | if (amdgpu_ras_fs_init(adev)) | 1577 | if (amdgpu_ras_fs_init(adev)) |
| 1571 | goto fs_out; | 1578 | goto fs_out; |
| 1572 | 1579 | ||
| 1573 | amdgpu_ras_self_test(adev); | ||
| 1574 | |||
| 1575 | DRM_INFO("RAS INFO: ras initialized successfully, " | 1580 | DRM_INFO("RAS INFO: ras initialized successfully, " |
| 1576 | "hardware ability[%x] ras_mask[%x]\n", | 1581 | "hardware ability[%x] ras_mask[%x]\n", |
| 1577 | con->hw_supported, con->supported); | 1582 | con->hw_supported, con->supported); |
| @@ -30,6 +30,7 @@ · 29 unmodified lines | |||
| 30 | #define AMDGPU_VCN_FIRMWARE_OFFSET 256 | 30 | #define AMDGPU_VCN_FIRMWARE_OFFSET 256 |
| 31 | #define AMDGPU_VCN_MAX_ENC_RINGS 3 | 31 | #define AMDGPU_VCN_MAX_ENC_RINGS 3 |
| 32 | 32 | ||
| 33 | #define VCN_DEC_KMD_CMD 0x80000000 | ||
| 33 | #define VCN_DEC_CMD_FENCE 0x00000000 | 34 | #define VCN_DEC_CMD_FENCE 0x00000000 |
| 34 | #define VCN_DEC_CMD_TRAP 0x00000001 | 35 | #define VCN_DEC_CMD_TRAP 0x00000001 |
| 35 | #define VCN_DEC_CMD_WRITE_REG 0x00000004 | 36 | #define VCN_DEC_CMD_WRITE_REG 0x00000004 |
| @@ -1441,6 +1441,15 @@ static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) · 1440 unmodified lines | |||
| 1441 | } | 1441 | } |
| 1442 | nv_grbm_select(adev, 0, 0, 0, 0); | 1442 | nv_grbm_select(adev, 0, 0, 0, 0); |
| 1443 | mutex_unlock(&adev->srbm_mutex); | 1443 | mutex_unlock(&adev->srbm_mutex); |
| 1444 | |||
| 1445 | /* Initialize all compute VMIDs to have no GDS, GWS, or OA | ||
| 1446 | acccess. These should be enabled by FW for target VMIDs. */ | ||
| 1447 | for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { | ||
| 1448 | WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); | ||
| 1449 | WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); | ||
| 1450 | WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); | ||
| 1451 | WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); | ||
| 1452 | } | ||
| 1444 | } | 1453 | } |
| 1445 | 1454 | ||
| 1446 | static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) | 1455 | static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) |
| @@ -4197,15 +4206,6 @@ static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, · 2750 unmodified lines | |||
| 4197 | unsigned vmid = AMDGPU_JOB_GET_VMID(job); | 4206 | unsigned vmid = AMDGPU_JOB_GET_VMID(job); |
| 4198 | u32 header, control = 0; | 4207 | u32 header, control = 0; |
| 4199 | 4208 | ||
| 4200 | /* Prevent a hw deadlock due to a wave ID mismatch between ME and GDS. | ||
| 4201 | * This resets the wave ID counters. (needed by transform feedback) | ||
| 4202 | * TODO: This might only be needed on a VMID switch when we change | ||
| 4203 | * the GDS OA mapping, not sure. | ||
| 4204 | */ | ||
| 4205 | amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); | ||
| 4206 | amdgpu_ring_write(ring, mmVGT_GS_MAX_WAVE_ID); | ||
| 4207 | amdgpu_ring_write(ring, ring->adev->gds.vgt_gs_max_wave_id); | ||
| 4208 | |||
| 4209 | if (ib->flags & AMDGPU_IB_FLAG_CE) | 4209 | if (ib->flags & AMDGPU_IB_FLAG_CE) |
| 4210 | header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2); | 4210 | header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2); |
| 4211 | else | 4211 | else |
| @@ -4611,6 +4611,7 @@ gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, · 399 unmodified lines | |||
| 4611 | cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, | 4611 | cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, |
| 4612 | TIME_STAMP_INT_ENABLE, 0); | 4612 | TIME_STAMP_INT_ENABLE, 0); |
| 4613 | WREG32(cp_int_cntl_reg, cp_int_cntl); | 4613 | WREG32(cp_int_cntl_reg, cp_int_cntl); |
| 4614 | break; | ||
| 4614 | case AMDGPU_IRQ_STATE_ENABLE: | 4615 | case AMDGPU_IRQ_STATE_ENABLE: |
| 4615 | cp_int_cntl = RREG32(cp_int_cntl_reg); | 4616 | cp_int_cntl = RREG32(cp_int_cntl_reg); |
| 4616 | cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, | 4617 | cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, |
| @@ -4951,7 +4952,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { · 334 unmodified lines | |||
| 4951 | 5 + /* HDP_INVL */ | 4952 | 5 + /* HDP_INVL */ |
| 4952 | 8 + 8 + /* FENCE x2 */ | 4953 | 8 + 8 + /* FENCE x2 */ |
| 4953 | 2, /* SWITCH_BUFFER */ | 4954 | 2, /* SWITCH_BUFFER */ |
| 4954 | .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_gfx */ | 4955 | .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */ |
| 4955 | .emit_ib = gfx_v10_0_ring_emit_ib_gfx, | 4956 | .emit_ib = gfx_v10_0_ring_emit_ib_gfx, |
| 4956 | .emit_fence = gfx_v10_0_ring_emit_fence, | 4957 | .emit_fence = gfx_v10_0_ring_emit_fence, |
| 4957 | .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, | 4958 | .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, |
| @@ -5102,7 +5103,6 @@ static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev) · 144 unmodified lines | |||
| 5102 | default: | 5103 | default: |
| 5103 | adev->gds.gds_size = 0x10000; | 5104 | adev->gds.gds_size = 0x10000; |
| 5104 | adev->gds.gds_compute_max_wave_id = 0x4ff; | 5105 | adev->gds.gds_compute_max_wave_id = 0x4ff; |
| 5105 | adev->gds.vgt_gs_max_wave_id = 0x3ff; | ||
| 5106 | break; | 5106 | break; |
| 5107 | } | 5107 | } |
| 5108 | 5108 | ||
| @@ -1879,6 +1879,15 @@ static void gfx_v7_0_init_compute_vmid(struct amdgpu_device *adev) · 1878 unmodified lines | |||
| 1879 | } | 1879 | } |
| 1880 | cik_srbm_select(adev, 0, 0, 0, 0); | 1880 | cik_srbm_select(adev, 0, 0, 0, 0); |
| 1881 | mutex_unlock(&adev->srbm_mutex); | 1881 | mutex_unlock(&adev->srbm_mutex); |
| 1882 | |||
| 1883 | /* Initialize all compute VMIDs to have no GDS, GWS, or OA | ||
| 1884 | acccess. These should be enabled by FW for target VMIDs. */ | ||
| 1885 | for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { | ||
| 1886 | WREG32(amdgpu_gds_reg_offset[i].mem_base, 0); | ||
| 1887 | WREG32(amdgpu_gds_reg_offset[i].mem_size, 0); | ||
| 1888 | WREG32(amdgpu_gds_reg_offset[i].gws, 0); | ||
| 1889 | WREG32(amdgpu_gds_reg_offset[i].oa, 0); | ||
| 1890 | } | ||
| 1882 | } | 1891 | } |
| 1883 | 1892 | ||
| 1884 | static void gfx_v7_0_config_init(struct amdgpu_device *adev) | 1893 | static void gfx_v7_0_config_init(struct amdgpu_device *adev) |
| @@ -1321,6 +1321,39 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev) · 1320 unmodified lines | |||
| 1321 | return 0; | 1321 | return 0; |
| 1322 | } | 1322 | } |
| 1323 | 1323 | ||
| 1324 | static int gfx_v8_0_csb_vram_pin(struct amdgpu_device *adev) | ||
| 1325 | { | ||
| 1326 | int r; | ||
| 1327 | |||
| 1328 | r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); | ||
| 1329 | if (unlikely(r != 0)) | ||
| 1330 | return r; | ||
| 1331 | |||
| 1332 | r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, | ||
| 1333 | AMDGPU_GEM_DOMAIN_VRAM); | ||
| 1334 | if (!r) | ||
| 1335 | adev->gfx.rlc.clear_state_gpu_addr = | ||
| 1336 | amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj); | ||
| 1337 | |||
| 1338 | amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); | ||
| 1339 | |||
| 1340 | return r; | ||
| 1341 | } | ||
| 1342 | |||
| 1343 | static void gfx_v8_0_csb_vram_unpin(struct amdgpu_device *adev) | ||
| 1344 | { | ||
| 1345 | int r; | ||
| 1346 | |||
| 1347 | if (!adev->gfx.rlc.clear_state_obj) | ||
| 1348 | return; | ||
| 1349 | |||
| 1350 | r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true); | ||
| 1351 | if (likely(r == 0)) { | ||
| 1352 | amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj); | ||
| 1353 | amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); | ||
| 1354 | } | ||
| 1355 | } | ||
| 1356 | |||
| 1324 | static void gfx_v8_0_mec_fini(struct amdgpu_device *adev) | 1357 | static void gfx_v8_0_mec_fini(struct amdgpu_device *adev) |
| 1325 | { | 1358 | { |
| 1326 | amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); | 1359 | amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); |
| @@ -3706,6 +3739,15 @@ static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev) · 2379 unmodified lines | |||
| 3706 | } | 3739 | } |
| 3707 | vi_srbm_select(adev, 0, 0, 0, 0); | 3740 | vi_srbm_select(adev, 0, 0, 0, 0); |
| 3708 | mutex_unlock(&adev->srbm_mutex); | 3741 | mutex_unlock(&adev->srbm_mutex); |
| 3742 | |||
| 3743 | /* Initialize all compute VMIDs to have no GDS, GWS, or OA | ||
| 3744 | acccess. These should be enabled by FW for target VMIDs. */ | ||
| 3745 | for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { | ||
| 3746 | WREG32(amdgpu_gds_reg_offset[i].mem_base, 0); | ||
| 3747 | WREG32(amdgpu_gds_reg_offset[i].mem_size, 0); | ||
| 3748 | WREG32(amdgpu_gds_reg_offset[i].gws, 0); | ||
| 3749 | WREG32(amdgpu_gds_reg_offset[i].oa, 0); | ||
| 3750 | } | ||
| 3709 | } | 3751 | } |
| 3710 | 3752 | ||
| 3711 | static void gfx_v8_0_config_init(struct amdgpu_device *adev) | 3753 | static void gfx_v8_0_config_init(struct amdgpu_device *adev) |
| @@ -4776,6 +4818,10 @@ static int gfx_v8_0_hw_init(void *handle) · 1064 unmodified lines | |||
| 4776 | gfx_v8_0_init_golden_registers(adev); | 4818 | gfx_v8_0_init_golden_registers(adev); |
| 4777 | gfx_v8_0_constants_init(adev); | 4819 | gfx_v8_0_constants_init(adev); |
| 4778 | 4820 | ||
| 4821 | r = gfx_v8_0_csb_vram_pin(adev); | ||
| 4822 | if (r) | ||
| 4823 | return r; | ||
| 4824 | |||
| 4779 | r = adev->gfx.rlc.funcs->resume(adev); | 4825 | r = adev->gfx.rlc.funcs->resume(adev); |
| 4780 | if (r) | 4826 | if (r) |
| 4781 | return r; | 4827 | return r; |
| @@ -4892,6 +4938,9 @@ static int gfx_v8_0_hw_fini(void *handle) · 110 unmodified lines | |||
| 4892 | else | 4938 | else |
| 4893 | pr_err("rlc is busy, skip halt rlc\n"); | 4939 | pr_err("rlc is busy, skip halt rlc\n"); |
| 4894 | amdgpu_gfx_rlc_exit_safe_mode(adev); | 4940 | amdgpu_gfx_rlc_exit_safe_mode(adev); |
| 4941 | |||
| 4942 | gfx_v8_0_csb_vram_unpin(adev); | ||
| 4943 | |||
| 4895 | return 0; | 4944 | return 0; |
| 4896 | } | 4945 | } |
| 4897 | 4946 | ||
| @@ -1918,6 +1918,15 @@ static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev) · 1917 unmodified lines | |||
| 1918 | } | 1918 | } |
| 1919 | soc15_grbm_select(adev, 0, 0, 0, 0); | 1919 | soc15_grbm_select(adev, 0, 0, 0, 0); |
| 1920 | mutex_unlock(&adev->srbm_mutex); | 1920 | mutex_unlock(&adev->srbm_mutex); |
| 1921 | |||
| 1922 | /* Initialize all compute VMIDs to have no GDS, GWS, or OA | ||
| 1923 | acccess. These should be enabled by FW for target VMIDs. */ | ||
| 1924 | for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { | ||
| 1925 | WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); | ||
| 1926 | WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); | ||
| 1927 | WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); | ||
| 1928 | WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); | ||
| 1929 | } | ||
| 1921 | } | 1930 | } |
| 1922 | 1931 | ||
| 1923 | static void gfx_v9_0_constants_init(struct amdgpu_device *adev) | 1932 | static void gfx_v9_0_constants_init(struct amdgpu_device *adev) |
| @@ -4860,7 +4869,7 @@ static void gfx_v9_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid) · 2936 unmodified lines | |||
| 4860 | value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); | 4869 | value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); |
| 4861 | value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); | 4870 | value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); |
| 4862 | value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); | 4871 | value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); |
| 4863 | WREG32(mmSQ_CMD, value); | 4872 | WREG32_SOC15(GC, 0, mmSQ_CMD, value); |
| 4864 | } | 4873 | } |
| 4865 | 4874 | ||
| 4866 | static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, | 4875 | static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, |
| @@ -372,11 +372,8 @@ static void vcn_v2_0_mc_resume(struct amdgpu_device *adev) · 371 unmodified lines | |||
| 372 | WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, | 372 | WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, |
| 373 | upper_32_bits(adev->vcn.gpu_addr)); | 373 | upper_32_bits(adev->vcn.gpu_addr)); |
| 374 | offset = size; | 374 | offset = size; |
| 375 | /* No signed header for now from firmware | ||
| 376 | WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, | 375 | WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, |
| 377 | AMDGPU_UVD_FIRMWARE_OFFSET >> 3); | 376 | AMDGPU_UVD_FIRMWARE_OFFSET >> 3); |
| 378 | */ | ||
| 379 | WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0); | ||
| 380 | } | 377 | } |
| 381 | 378 | ||
| 382 | WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size); | 379 | WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size); |
| @@ -1488,7 +1485,7 @@ static void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring) · 1105 unmodified lines | |||
| 1488 | amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET, 0)); | 1485 | amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET, 0)); |
| 1489 | amdgpu_ring_write(ring, 0); | 1486 | amdgpu_ring_write(ring, 0); |
| 1490 | amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0)); | 1487 | amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0)); |
| 1491 | amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1); | 1488 | amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1)); |
| 1492 | } | 1489 | } |
| 1493 | 1490 | ||
| 1494 | /** | 1491 | /** |
| @@ -1501,7 +1498,7 @@ static void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring) · 6 unmodified lines | |||
| 1501 | static void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring) | 1498 | static void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring) |
| 1502 | { | 1499 | { |
| 1503 | amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0)); | 1500 | amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0)); |
| 1504 | amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1); | 1501 | amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_END << 1)); |
| 1505 | } | 1502 | } |
| 1506 | 1503 | ||
| 1507 | /** | 1504 | /** |
| @@ -1546,7 +1543,7 @@ static void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 · 38 unmodified lines | |||
| 1546 | amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); | 1543 | amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); |
| 1547 | 1544 | ||
| 1548 | amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0)); | 1545 | amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0)); |
| 1549 | amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1); | 1546 | amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_FENCE << 1)); |
| 1550 | 1547 | ||
| 1551 | amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET, 0)); | 1548 | amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET, 0)); |
| 1552 | amdgpu_ring_write(ring, 0); | 1549 | amdgpu_ring_write(ring, 0); |
| @@ -1556,7 +1553,7 @@ static void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 · 3 unmodified lines | |||
| 1556 | 1553 | ||
| 1557 | amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0)); | 1554 | amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0)); |
| 1558 | 1555 | ||
| 1559 | amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1); | 1556 | amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_TRAP << 1)); |
| 1560 | } | 1557 | } |
| 1561 | 1558 | ||
| 1562 | /** | 1559 | /** |
| @@ -1600,7 +1597,7 @@ static void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, · 37 unmodified lines | |||
| 1600 | 1597 | ||
| 1601 | amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0)); | 1598 | amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0)); |
| 1602 | 1599 | ||
| 1603 | amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1); | 1600 | amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_REG_READ_COND_WAIT << 1)); |
| 1604 | } | 1601 | } |
| 1605 | 1602 | ||
| 1606 | static void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, | 1603 | static void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, |
| @@ -1629,7 +1626,7 @@ static void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, · 22 unmodified lines | |||
| 1629 | 1626 | ||
| 1630 | amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0)); | 1627 | amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0)); |
| 1631 | 1628 | ||
| 1632 | amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1); | 1629 | amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_WRITE_REG << 1)); |
| 1633 | } | 1630 | } |
| 1634 | 1631 | ||
| 1635 | /** | 1632 | /** |
| @@ -2082,6 +2079,36 @@ static int vcn_v2_0_process_interrupt(struct amdgpu_device *adev, · 446 unmodified lines | |||
| 2082 | return 0; | 2079 | return 0; |
| 2083 | } | 2080 | } |
| 2084 | 2081 | ||
| 2082 | static int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring) | ||
| 2083 | { | ||
| 2084 | struct amdgpu_device *adev = ring->adev; | ||
| 2085 | uint32_t tmp = 0; | ||
| 2086 | unsigned i; | ||
| 2087 | int r; | ||
| 2088 | |||
| 2089 | WREG32(adev->vcn.external.scratch9, 0xCAFEDEAD); | ||
| 2090 | r = amdgpu_ring_alloc(ring, 4); | ||
| 2091 | if (r) | ||
| 2092 | return r; | ||
| 2093 | amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET, 0)); | ||
| 2094 | amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1)); | ||
| 2095 | amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0)); | ||
| 2096 | amdgpu_ring_write(ring, 0xDEADBEEF); | ||
| 2097 | amdgpu_ring_commit(ring); | ||
| 2098 | for (i = 0; i < adev->usec_timeout; i++) { | ||
| 2099 | tmp = RREG32(adev->vcn.external.scratch9); | ||
| 2100 | if (tmp == 0xDEADBEEF) | ||
| 2101 | break; | ||
| 2102 | DRM_UDELAY(1); | ||
| 2103 | } | ||
| 2104 | |||
| 2105 | if (i >= adev->usec_timeout) | ||
| 2106 | r = -ETIMEDOUT; | ||
| 2107 | |||
| 2108 | return r; | ||
| 2109 | } | ||
| 2110 | |||
| 2111 | |||
| 2085 | static int vcn_v2_0_set_powergating_state(void *handle, | 2112 | static int vcn_v2_0_set_powergating_state(void *handle, |
| 2086 | enum amd_powergating_state state) | 2113 | enum amd_powergating_state state) |
| 2087 | { | 2114 | { |
| @@ -2145,7 +2172,7 @@ static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = { · 57 unmodified lines | |||
| 2145 | .emit_ib = vcn_v2_0_dec_ring_emit_ib, | 2172 | .emit_ib = vcn_v2_0_dec_ring_emit_ib, |
| 2146 | .emit_fence = vcn_v2_0_dec_ring_emit_fence, | 2173 | .emit_fence = vcn_v2_0_dec_ring_emit_fence, |
| 2147 | .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush, | 2174 | .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush, |
| 2148 | .test_ring = amdgpu_vcn_dec_ring_test_ring, | 2175 | .test_ring = vcn_v2_0_dec_ring_test_ring, |
| 2149 | .test_ib = amdgpu_vcn_dec_ring_test_ib, | 2176 | .test_ib = amdgpu_vcn_dec_ring_test_ib, |
| 2150 | .insert_nop = vcn_v2_0_dec_ring_insert_nop, | 2177 | .insert_nop = vcn_v2_0_dec_ring_insert_nop, |
| 2151 | .insert_start = vcn_v2_0_dec_ring_insert_start, | 2178 | .insert_start = vcn_v2_0_dec_ring_insert_start, |
| @@ -1567,32 +1567,6 @@ copy_from_user_failed: · 1566 unmodified lines | |||
| 1567 | return err; | 1567 | return err; |
| 1568 | } | 1568 | } |
| 1569 | 1569 | ||
| 1570 | static int kfd_ioctl_alloc_queue_gws(struct file *filep, | ||
| 1571 | struct kfd_process *p, void *data) | ||
| 1572 | { | ||
| 1573 | int retval; | ||
| 1574 | struct kfd_ioctl_alloc_queue_gws_args *args = data; | ||
| 1575 | struct kfd_dev *dev; | ||
| 1576 | |||
| 1577 | if (!hws_gws_support) | ||
| 1578 | return -ENODEV; | ||
| 1579 | |||
| 1580 | dev = kfd_device_by_id(args->gpu_id); | ||
| 1581 | if (!dev) { | ||
| 1582 | pr_debug("Could not find gpu id 0x%x\n", args->gpu_id); | ||
| 1583 | return -ENODEV; | ||
| 1584 | } | ||
| 1585 | if (dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) | ||
| 1586 | return -ENODEV; | ||
| 1587 | |||
| 1588 | mutex_lock(&p->mutex); | ||
| 1589 | retval = pqm_set_gws(&p->pqm, args->queue_id, args->num_gws ? dev->gws : NULL); | ||
| 1590 | mutex_unlock(&p->mutex); | ||
| 1591 | |||
| 1592 | args->first_gws = 0; | ||
| 1593 | return retval; | ||
| 1594 | } | ||
| 1595 | |||
| 1596 | static int kfd_ioctl_get_dmabuf_info(struct file *filep, | 1570 | static int kfd_ioctl_get_dmabuf_info(struct file *filep, |
| 1597 | struct kfd_process *p, void *data) | 1571 | struct kfd_process *p, void *data) |
| 1598 | { | 1572 | { |
| @@ -1795,8 +1769,6 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { · 196 unmodified lines | |||
| 1795 | AMDKFD_IOCTL_DEF(AMDKFD_IOC_IMPORT_DMABUF, | 1769 | AMDKFD_IOCTL_DEF(AMDKFD_IOC_IMPORT_DMABUF, |
| 1796 | kfd_ioctl_import_dmabuf, 0), | 1770 | kfd_ioctl_import_dmabuf, 0), |
| 1797 | 1771 | ||
| 1798 | AMDKFD_IOCTL_DEF(AMDKFD_IOC_ALLOC_QUEUE_GWS, | ||
| 1799 | kfd_ioctl_alloc_queue_gws, 0), | ||
| 1800 | }; | 1772 | }; |
| 1801 | 1773 | ||
| 1802 | #define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls) | 1774 | #define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls) |
| @@ -668,6 +668,7 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev, · 667 unmodified lines | |||
| 668 | case CHIP_RAVEN: | 668 | case CHIP_RAVEN: |
| 669 | pcache_info = raven_cache_info; | 669 | pcache_info = raven_cache_info; |
| 670 | num_of_cache_types = ARRAY_SIZE(raven_cache_info); | 670 | num_of_cache_types = ARRAY_SIZE(raven_cache_info); |
| 671 | break; | ||
| 671 | case CHIP_NAVI10: | 672 | case CHIP_NAVI10: |
| 672 | pcache_info = navi10_cache_info; | 673 | pcache_info = navi10_cache_info; |
| 673 | num_of_cache_types = ARRAY_SIZE(navi10_cache_info); | 674 | num_of_cache_types = ARRAY_SIZE(navi10_cache_info); |
| @@ -429,7 +429,6 @@ struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type, · 428 unmodified lines | |||
| 429 | 429 | ||
| 430 | switch (type) { | 430 | switch (type) { |
| 431 | case KFD_MQD_TYPE_CP: | 431 | case KFD_MQD_TYPE_CP: |
| 432 | pr_debug("%s@%i\n", __func__, __LINE__); | ||
| 433 | case KFD_MQD_TYPE_COMPUTE: | 432 | case KFD_MQD_TYPE_COMPUTE: |
| 434 | pr_debug("%s@%i\n", __func__, __LINE__); | 433 | pr_debug("%s@%i\n", __func__, __LINE__); |
| 435 | mqd->allocate_mqd = allocate_mqd; | 434 | mqd->allocate_mqd = allocate_mqd; |
| @@ -262,12 +262,12 @@ void dce110_clk_mgr_construct( · 261 unmodified lines | |||
| 262 | struct dc_context *ctx, | 262 | struct dc_context *ctx, |
| 263 | struct clk_mgr_internal *clk_mgr) | 263 | struct clk_mgr_internal *clk_mgr) |
| 264 | { | 264 | { |
| 265 | dce_clk_mgr_construct(ctx, clk_mgr); | ||
| 266 | |||
| 265 | memcpy(clk_mgr->max_clks_by_state, | 267 | memcpy(clk_mgr->max_clks_by_state, |
| 266 | dce110_max_clks_by_state, | 268 | dce110_max_clks_by_state, |
| 267 | sizeof(dce110_max_clks_by_state)); | 269 | sizeof(dce110_max_clks_by_state)); |
| 268 | 270 | ||
| 269 | dce_clk_mgr_construct(ctx, clk_mgr); | ||
| 270 | |||
| 271 | clk_mgr->regs = &disp_clk_regs; | 271 | clk_mgr->regs = &disp_clk_regs; |
| 272 | clk_mgr->clk_mgr_shift = &disp_clk_shift; | 272 | clk_mgr->clk_mgr_shift = &disp_clk_shift; |
| 273 | clk_mgr->clk_mgr_mask = &disp_clk_mask; | 273 | clk_mgr->clk_mgr_mask = &disp_clk_mask; |
| @@ -226,12 +226,12 @@ void dce112_clk_mgr_construct( · 225 unmodified lines | |||
| 226 | struct dc_context *ctx, | 226 | struct dc_context *ctx, |
| 227 | struct clk_mgr_internal *clk_mgr) | 227 | struct clk_mgr_internal *clk_mgr) |
| 228 | { | 228 | { |
| 229 | dce_clk_mgr_construct(ctx, clk_mgr); | ||
| 230 | |||
| 229 | memcpy(clk_mgr->max_clks_by_state, | 231 | memcpy(clk_mgr->max_clks_by_state, |
| 230 | dce112_max_clks_by_state, | 232 | dce112_max_clks_by_state, |
| 231 | sizeof(dce112_max_clks_by_state)); | 233 | sizeof(dce112_max_clks_by_state)); |
| 232 | 234 | ||
| 233 | dce_clk_mgr_construct(ctx, clk_mgr); | ||
| 234 | |||
| 235 | clk_mgr->regs = &disp_clk_regs; | 235 | clk_mgr->regs = &disp_clk_regs; |
| 236 | clk_mgr->clk_mgr_shift = &disp_clk_shift; | 236 | clk_mgr->clk_mgr_shift = &disp_clk_shift; |
| 237 | clk_mgr->clk_mgr_mask = &disp_clk_mask; | 237 | clk_mgr->clk_mgr_mask = &disp_clk_mask; |
| @@ -127,12 +127,12 @@ static struct clk_mgr_funcs dce120_funcs = { · 126 unmodified lines | |||
| 127 | 127 | ||
| 128 | void dce120_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr) | 128 | void dce120_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr) |
| 129 | { | 129 | { |
| 130 | dce_clk_mgr_construct(ctx, clk_mgr); | ||
| 131 | |||
| 130 | memcpy(clk_mgr->max_clks_by_state, | 132 | memcpy(clk_mgr->max_clks_by_state, |
| 131 | dce120_max_clks_by_state, | 133 | dce120_max_clks_by_state, |
| 132 | sizeof(dce120_max_clks_by_state)); | 134 | sizeof(dce120_max_clks_by_state)); |
| 133 | 135 | ||
| 134 | dce_clk_mgr_construct(ctx, clk_mgr); | ||
| 135 | |||
| 136 | clk_mgr->base.dprefclk_khz = 600000; | 136 | clk_mgr->base.dprefclk_khz = 600000; |
| 137 | clk_mgr->base.funcs = &dce120_funcs; | 137 | clk_mgr->base.funcs = &dce120_funcs; |
| 138 | } | 138 | } |
| @@ -301,6 +301,8 @@ void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr, · 300 unmodified lines | |||
| 301 | void dcn2_init_clocks(struct clk_mgr *clk_mgr) | 301 | void dcn2_init_clocks(struct clk_mgr *clk_mgr) |
| 302 | { | 302 | { |
| 303 | memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); | 303 | memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); |
| 304 | // Assumption is that boot state always supports pstate | ||
| 305 | clk_mgr->clks.p_state_change_support = true; | ||
| 304 | } | 306 | } |
| 305 | 307 | ||
| 306 | void dcn2_enable_pme_wa(struct clk_mgr *clk_mgr_base) | 308 | void dcn2_enable_pme_wa(struct clk_mgr *clk_mgr_base) |
| @@ -331,6 +333,7 @@ void dcn20_clk_mgr_construct( · 24 unmodified lines | |||
| 331 | struct dccg *dccg) | 333 | struct dccg *dccg) |
| 332 | { | 334 | { |
| 333 | clk_mgr->base.ctx = ctx; | 335 | clk_mgr->base.ctx = ctx; |
| 336 | clk_mgr->pp_smu = pp_smu; | ||
| 334 | clk_mgr->base.funcs = &dcn2_funcs; | 337 | clk_mgr->base.funcs = &dcn2_funcs; |
| 335 | clk_mgr->regs = &clk_mgr_regs; | 338 | clk_mgr->regs = &clk_mgr_regs; |
| 336 | clk_mgr->clk_mgr_shift = &clk_mgr_shift; | 339 | clk_mgr->clk_mgr_shift = &clk_mgr_shift; |
| @@ -23,6 +23,7 @@ · 22 unmodified lines | |||
| 23 | */ | 23 | */ |
| 24 | 24 | ||
| 25 | #include <linux/slab.h> | 25 | #include <linux/slab.h> |
| 26 | #include <linux/mm.h> | ||
| 26 | 27 | ||
| 27 | #include "dm_services.h" | 28 | #include "dm_services.h" |
| 28 | 29 | ||
| @@ -502,8 +503,10 @@ void dc_stream_set_static_screen_events(struct dc *dc, · 473 unmodified lines | |||
| 502 | 503 | ||
| 503 | static void destruct(struct dc *dc) | 504 | static void destruct(struct dc *dc) |
| 504 | { | 505 | { |
| 505 | dc_release_state(dc->current_state); | 506 | if (dc->current_state) { |
| 506 | dc->current_state = NULL; | 507 | dc_release_state(dc->current_state); |
| 508 | dc->current_state = NULL; | ||
| 509 | } | ||
| 507 | 510 | ||
| 508 | destroy_links(dc); | 511 | destroy_links(dc); |
| 509 | 512 | ||
| @@ -1169,8 +1172,8 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc) · 659 unmodified lines | |||
| 1169 | 1172 | ||
| 1170 | struct dc_state *dc_create_state(struct dc *dc) | 1173 | struct dc_state *dc_create_state(struct dc *dc) |
| 1171 | { | 1174 | { |
| 1172 | struct dc_state *context = kzalloc(sizeof(struct dc_state), | 1175 | struct dc_state *context = kvzalloc(sizeof(struct dc_state), |
| 1173 | GFP_KERNEL); | 1176 | GFP_KERNEL); |
| 1174 | 1177 | ||
| 1175 | if (!context) | 1178 | if (!context) |
| 1176 | return NULL; | 1179 | return NULL; |
| @@ -1190,11 +1193,11 @@ struct dc_state *dc_create_state(struct dc *dc) · 13 unmodified lines | |||
| 1190 | struct dc_state *dc_copy_state(struct dc_state *src_ctx) | 1193 | struct dc_state *dc_copy_state(struct dc_state *src_ctx) |
| 1191 | { | 1194 | { |
| 1192 | int i, j; | 1195 | int i, j; |
| 1193 | struct dc_state *new_ctx = kmemdup(src_ctx, | 1196 | struct dc_state *new_ctx = kvmalloc(sizeof(struct dc_state), GFP_KERNEL); |
| 1194 | sizeof(struct dc_state), GFP_KERNEL); | ||
| 1195 | 1197 | ||
| 1196 | if (!new_ctx) | 1198 | if (!new_ctx) |
| 1197 | return NULL; | 1199 | return NULL; |
| 1200 | memcpy(new_ctx, src_ctx, sizeof(struct dc_state)); | ||
| 1198 | 1201 | ||
| 1199 | for (i = 0; i < MAX_PIPES; i++) { | 1202 | for (i = 0; i < MAX_PIPES; i++) { |
| 1200 | struct pipe_ctx *cur_pipe = &new_ctx->res_ctx.pipe_ctx[i]; | 1203 | struct pipe_ctx *cur_pipe = &new_ctx->res_ctx.pipe_ctx[i]; |
| @@ -1228,7 +1231,7 @@ static void dc_state_free(struct kref *kref) · 27 unmodified lines | |||
| 1228 | { | 1231 | { |
| 1229 | struct dc_state *context = container_of(kref, struct dc_state, refcount); | 1232 | struct dc_state *context = container_of(kref, struct dc_state, refcount); |
| 1230 | dc_resource_state_destruct(context); | 1233 | dc_resource_state_destruct(context); |
| 1231 | kfree(context); | 1234 | kvfree(context); |
| 1232 | } | 1235 | } |
| 1233 | 1236 | ||
| 1234 | void dc_release_state(struct dc_state *context) | 1237 | void dc_release_state(struct dc_state *context) |
| @@ -532,6 +532,7 @@ static void read_edp_current_link_settings_on_detect(struct dc_link *link) · 531 unmodified lines | |||
| 532 | uint32_t read_dpcd_retry_cnt = 10; | 532 | uint32_t read_dpcd_retry_cnt = 10; |
| 533 | enum dc_status status = DC_ERROR_UNEXPECTED; | 533 | enum dc_status status = DC_ERROR_UNEXPECTED; |
| 534 | int i; | 534 | int i; |
| 535 | union max_down_spread max_down_spread = { {0} }; | ||
| 535 | 536 | ||
| 536 | // Read DPCD 00101h to find out the number of lanes currently set | 537 | // Read DPCD 00101h to find out the number of lanes currently set |
| 537 | for (i = 0; i < read_dpcd_retry_cnt; i++) { | 538 | for (i = 0; i < read_dpcd_retry_cnt; i++) { |
| @@ -553,8 +554,6 @@ static void read_edp_current_link_settings_on_detect(struct dc_link *link) · 15 unmodified lines | |||
| 553 | msleep(8); | 554 | msleep(8); |
| 554 | } | 555 | } |
| 555 | 556 | ||
| 556 | ASSERT(status == DC_OK); | ||
| 557 | |||
| 558 | // Read DPCD 00100h to find if standard link rates are set | 557 | // Read DPCD 00100h to find if standard link rates are set |
| 559 | core_link_read_dpcd(link, DP_LINK_BW_SET, | 558 | core_link_read_dpcd(link, DP_LINK_BW_SET, |
| 560 | &link_bw_set, sizeof(link_bw_set)); | 559 | &link_bw_set, sizeof(link_bw_set)); |
| @@ -576,6 +575,12 @@ static void read_edp_current_link_settings_on_detect(struct dc_link *link) · 15 unmodified lines | |||
| 576 | link->cur_link_settings.link_rate = link_bw_set; | 575 | link->cur_link_settings.link_rate = link_bw_set; |
| 577 | link->cur_link_settings.use_link_rate_set = false; | 576 | link->cur_link_settings.use_link_rate_set = false; |
| 578 | } | 577 | } |
| 578 | // Read DPCD 00003h to find the max down spread. | ||
| 579 | core_link_read_dpcd(link, DP_MAX_DOWNSPREAD, | ||
| 580 | &max_down_spread.raw, sizeof(max_down_spread)); | ||
| 581 | link->cur_link_settings.link_spread = | ||
| 582 | max_down_spread.bits.MAX_DOWN_SPREAD ? | ||
| 583 | LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED; | ||
| 579 | } | 584 | } |
| 580 | 585 | ||
| 581 | static bool detect_dp( | 586 | static bool detect_dp( |
| @@ -717,13 +722,6 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason) · 135 unmodified lines | |||
| 717 | return false; | 722 | return false; |
| 718 | } | 723 | } |
| 719 | 724 | ||
| 720 | if (link->connector_signal == SIGNAL_TYPE_EDP) { | ||
| 721 | /* On detect, we want to make sure current link settings are | ||
| 722 | * up to date, especially if link was powered on by GOP. | ||
| 723 | */ | ||
| 724 | read_edp_current_link_settings_on_detect(link); | ||
| 725 | } | ||
| 726 | |||
| 727 | prev_sink = link->local_sink; | 725 | prev_sink = link->local_sink; |
| 728 | if (prev_sink != NULL) { | 726 | if (prev_sink != NULL) { |
| 729 | dc_sink_retain(prev_sink); | 727 | dc_sink_retain(prev_sink); |
| @@ -765,6 +763,7 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason) · 35 unmodified lines | |||
| 765 | } | 763 | } |
| 766 | 764 | ||
| 767 | case SIGNAL_TYPE_EDP: { | 765 | case SIGNAL_TYPE_EDP: { |
| 766 | read_edp_current_link_settings_on_detect(link); | ||
| 768 | detect_edp_sink_caps(link); | 767 | detect_edp_sink_caps(link); |
| 769 | sink_caps.transaction_type = | 768 | sink_caps.transaction_type = |
| 770 | DDC_TRANSACTION_TYPE_I2C_OVER_AUX; | 769 | DDC_TRANSACTION_TYPE_I2C_OVER_AUX; |
| @@ -2329,7 +2328,7 @@ bool dc_link_set_backlight_level(const struct dc_link *link, · 1558 unmodified lines | |||
| 2329 | if (core_dc->current_state->res_ctx.pipe_ctx[i].stream) { | 2328 | if (core_dc->current_state->res_ctx.pipe_ctx[i].stream) { |
| 2330 | if (core_dc->current_state->res_ctx. | 2329 | if (core_dc->current_state->res_ctx. |
| 2331 | pipe_ctx[i].stream->link | 2330 | pipe_ctx[i].stream->link |
| 2332 | == link) | 2331 | == link) { |
| 2333 | /* DMCU -1 for all controller id values, | 2332 | /* DMCU -1 for all controller id values, |
| 2334 | * therefore +1 here | 2333 | * therefore +1 here |
| 2335 | */ | 2334 | */ |
| @@ -2337,6 +2336,13 @@ bool dc_link_set_backlight_level(const struct dc_link *link, · 1 unmodified line | |||
| 2337 | core_dc->current_state-> | 2336 | core_dc->current_state-> |
| 2338 | res_ctx.pipe_ctx[i].stream_res.tg->inst + | 2337 | res_ctx.pipe_ctx[i].stream_res.tg->inst + |
| 2339 | 1; | 2338 | 1; |
| 2339 | |||
| 2340 | /* Disable brightness ramping when the display is blanked | ||
| 2341 | * as it can hang the DMCU | ||
| 2342 | */ | ||
| 2343 | if (core_dc->current_state->res_ctx.pipe_ctx[i].plane_state == NULL) | ||
| 2344 | frame_ramp = 0; | ||
| 2345 | } | ||
| 2340 | } | 2346 | } |
| 2341 | } | 2347 | } |
| 2342 | abm->funcs->set_backlight_level_pwm( | 2348 | abm->funcs->set_backlight_level_pwm( |
| @@ -2984,8 +2990,10 @@ void dc_link_set_preferred_link_settings(struct dc *dc, · 641 unmodified lines | |||
| 2984 | 2990 | ||
| 2985 | /* Retrain with preferred link settings only relevant for | 2991 | /* Retrain with preferred link settings only relevant for |
| 2986 | * DP signal type | 2992 | * DP signal type |
| 2993 | * Check for non-DP signal or if passive dongle present | ||
| 2987 | */ | 2994 | */ |
| 2988 | if (!dc_is_dp_signal(link->connector_signal)) | 2995 | if (!dc_is_dp_signal(link->connector_signal) || |
| 2996 | link->dongle_max_pix_clk > 0) | ||
| 2989 | return; | 2997 | return; |
| 2990 | 2998 | ||
| 2991 | for (i = 0; i < MAX_PIPES; i++) { | 2999 | for (i = 0; i < MAX_PIPES; i++) { |
| @@ -2230,18 +2230,25 @@ static void get_active_converter_info( · 2229 unmodified lines | |||
| 2230 | link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE; | 2230 | link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE; |
| 2231 | ddc_service_set_dongle_type(link->ddc, | 2231 | ddc_service_set_dongle_type(link->ddc, |
| 2232 | link->dpcd_caps.dongle_type); | 2232 | link->dpcd_caps.dongle_type); |
| 2233 | link->dpcd_caps.is_branch_dev = false; | ||
| 2233 | return; | 2234 | return; |
| 2234 | } | 2235 | } |
| 2235 | 2236 | ||
| 2236 | /* DPCD 0x5 bit 0 = 1, it indicate it's branch device */ | 2237 | /* DPCD 0x5 bit 0 = 1, it indicate it's branch device */ |
| 2237 | link->dpcd_caps.is_branch_dev = ds_port.fields.PORT_PRESENT; | 2238 | if (ds_port.fields.PORT_TYPE == DOWNSTREAM_DP) { |
| 2239 | link->dpcd_caps.is_branch_dev = false; | ||
| 2240 | } | ||
| 2241 | |||
| 2242 | else { | ||
| 2243 | link->dpcd_caps.is_branch_dev = ds_port.fields.PORT_PRESENT; | ||
| 2244 | } | ||
| 2238 | 2245 | ||
| 2239 | switch (ds_port.fields.PORT_TYPE) { | 2246 | switch (ds_port.fields.PORT_TYPE) { |
| 2240 | case DOWNSTREAM_VGA: | 2247 | case DOWNSTREAM_VGA: |
| 2241 | link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER; | 2248 | link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER; |
| 2242 | break; | 2249 | break; |
| 2243 | case DOWNSTREAM_DVI_HDMI: | 2250 | case DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS: |
| 2244 | /* At this point we don't know is it DVI or HDMI, | 2251 | /* At this point we don't know is it DVI or HDMI or DP++, |
| 2245 | * assume DVI.*/ | 2252 | * assume DVI.*/ |
| 2246 | link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER; | 2253 | link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER; |
| 2247 | break; | 2254 | break; |
| @@ -2258,6 +2265,10 @@ static void get_active_converter_info( · 10 unmodified lines | |||
| 2258 | det_caps, sizeof(det_caps)); | 2265 | det_caps, sizeof(det_caps)); |
| 2259 | 2266 | ||
| 2260 | switch (port_caps->bits.DWN_STRM_PORTX_TYPE) { | 2267 | switch (port_caps->bits.DWN_STRM_PORTX_TYPE) { |
| 2268 | /*Handle DP case as DONGLE_NONE*/ | ||
| 2269 | case DOWN_STREAM_DETAILED_DP: | ||
| 2270 | link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE; | ||
| 2271 | break; | ||
| 2261 | case DOWN_STREAM_DETAILED_VGA: | 2272 | case DOWN_STREAM_DETAILED_VGA: |
| 2262 | link->dpcd_caps.dongle_type = | 2273 | link->dpcd_caps.dongle_type = |
| 2263 | DISPLAY_DONGLE_DP_VGA_CONVERTER; | 2274 | DISPLAY_DONGLE_DP_VGA_CONVERTER; |
| @@ -2267,6 +2278,8 @@ static void get_active_converter_info( · 3 unmodified lines | |||
| 2267 | DISPLAY_DONGLE_DP_DVI_CONVERTER; | 2278 | DISPLAY_DONGLE_DP_DVI_CONVERTER; |
| 2268 | break; | 2279 | break; |
| 2269 | case DOWN_STREAM_DETAILED_HDMI: | 2280 | case DOWN_STREAM_DETAILED_HDMI: |
| 2281 | case DOWN_STREAM_DETAILED_DP_PLUS_PLUS: | ||
| 2282 | /*Handle DP++ active converter case, process DP++ case as HDMI case according DP1.4 spec*/ | ||
| 2270 | link->dpcd_caps.dongle_type = | 2283 | link->dpcd_caps.dongle_type = |
| 2271 | DISPLAY_DONGLE_DP_HDMI_CONVERTER; | 2284 | DISPLAY_DONGLE_DP_HDMI_CONVERTER; |
| 2272 | 2285 | ||
| @@ -2282,14 +2295,18 @@ static void get_active_converter_info( · 9 unmodified lines | |||
| 2282 | 2295 | ||
| 2283 | link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter = | 2296 | link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter = |
| 2284 | hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK; | 2297 | hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK; |
| 2285 | link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through = | 2298 | /*YCBCR capability only for HDMI case*/ |
| 2286 | hdmi_caps.bits.YCrCr422_PASS_THROUGH; | 2299 | if (port_caps->bits.DWN_STRM_PORTX_TYPE |
| 2287 | link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through = | 2300 | == DOWN_STREAM_DETAILED_HDMI) { |
| 2288 | hdmi_caps.bits.YCrCr420_PASS_THROUGH; | 2301 | link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through = |
| 2289 | link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter = | 2302 | hdmi_caps.bits.YCrCr422_PASS_THROUGH; |
| 2290 | hdmi_caps.bits.YCrCr422_CONVERSION; | 2303 | link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through = |
| 2291 | link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter = | 2304 | hdmi_caps.bits.YCrCr420_PASS_THROUGH; |
| 2292 | hdmi_caps.bits.YCrCr420_CONVERSION; | 2305 | link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter = |
| 2306 | hdmi_caps.bits.YCrCr422_CONVERSION; | ||
| 2307 | link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter = | ||
| 2308 | hdmi_caps.bits.YCrCr420_CONVERSION; | ||
| 2309 | } | ||
| 2293 | 2310 | ||
| 2294 | link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc = | 2311 | link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc = |
| 2295 | translate_dpcd_max_bpc( | 2312 | translate_dpcd_max_bpc( |
| @@ -258,7 +258,7 @@ bool resource_construct( · 257 unmodified lines | |||
| 258 | * PORT_CONNECTIVITY == 1 (as instructed by HW team). | 258 | * PORT_CONNECTIVITY == 1 (as instructed by HW team). |
| 259 | */ | 259 | */ |
| 260 | update_num_audio(&straps, &num_audio, &pool->audio_support); | 260 | update_num_audio(&straps, &num_audio, &pool->audio_support); |
| 261 | for (i = 0; i < pool->pipe_count && i < num_audio; i++) { | 261 | for (i = 0; i < caps->num_audio; i++) { |
| 262 | struct audio *aud = create_funcs->create_audio(ctx, i); | 262 | struct audio *aud = create_funcs->create_audio(ctx, i); |
| 263 | 263 | ||
| 264 | if (aud == NULL) { | 264 | if (aud == NULL) { |
| @@ -1669,6 +1669,12 @@ static struct audio *find_first_free_audio( · 1404 unmodified lines | |||
| 1669 | return pool->audios[i]; | 1669 | return pool->audios[i]; |
| 1670 | } | 1670 | } |
| 1671 | } | 1671 | } |
| 1672 | |||
| 1673 | /* use engine id to find free audio */ | ||
| 1674 | if ((id < pool->audio_count) && (res_ctx->is_audio_acquired[id] == false)) { | ||
| 1675 | return pool->audios[id]; | ||
| 1676 | } | ||
| 1677 | |||
| 1672 | /*not found the matching one, first come first serve*/ | 1678 | /*not found the matching one, first come first serve*/ |
| 1673 | for (i = 0; i < pool->audio_count; i++) { | 1679 | for (i = 0; i < pool->audio_count; i++) { |
| 1674 | if (res_ctx->is_audio_acquired[i] == false) { | 1680 | if (res_ctx->is_audio_acquired[i] == false) { |
| @@ -1833,6 +1839,7 @@ static int get_norm_pix_clk(const struct dc_crtc_timing *timing) · 158 unmodified lines | |||
| 1833 | pix_clk /= 2; | 1839 | pix_clk /= 2; |
| 1834 | if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) { | 1840 | if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) { |
| 1835 | switch (timing->display_color_depth) { | 1841 | switch (timing->display_color_depth) { |
| 1842 | case COLOR_DEPTH_666: | ||
| 1836 | case COLOR_DEPTH_888: | 1843 | case COLOR_DEPTH_888: |
| 1837 | normalized_pix_clk = pix_clk; | 1844 | normalized_pix_clk = pix_clk; |
| 1838 | break; | 1845 | break; |
| @@ -1979,7 +1986,7 @@ enum dc_status resource_map_pool_resources( · 140 unmodified lines | |||
| 1979 | /* TODO: Add check if ASIC support and EDID audio */ | 1986 | /* TODO: Add check if ASIC support and EDID audio */ |
| 1980 | if (!stream->converter_disable_audio && | 1987 | if (!stream->converter_disable_audio && |
| 1981 | dc_is_audio_capable_signal(pipe_ctx->stream->signal) && | 1988 | dc_is_audio_capable_signal(pipe_ctx->stream->signal) && |
| 1982 | stream->audio_info.mode_count) { | 1989 | stream->audio_info.mode_count && stream->audio_info.flags.all) { |
| 1983 | pipe_ctx->stream_res.audio = find_first_free_audio( | 1990 | pipe_ctx->stream_res.audio = find_first_free_audio( |
| 1984 | &context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id); | 1991 | &context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id); |
| 1985 | 1992 | ||
| @@ -612,7 +612,8 @@ bool dc_stream_set_dynamic_metadata(struct dc *dc, · 611 unmodified lines | |||
| 612 | 612 | ||
| 613 | pipe_ctx->stream->dmdata_address = attr->address; | 613 | pipe_ctx->stream->dmdata_address = attr->address; |
| 614 | 614 | ||
| 615 | if (pipe_ctx->stream_res.stream_enc->funcs->set_dynamic_metadata != NULL) { | 615 | if (pipe_ctx->stream_res.stream_enc && |
| 616 | pipe_ctx->stream_res.stream_enc->funcs->set_dynamic_metadata != NULL) { | ||
| 616 | if (pipe_ctx->stream->dmdata_address.quad_part != 0) { | 617 | if (pipe_ctx->stream->dmdata_address.quad_part != 0) { |
| 617 | /* if using dynamic meta, don't set up generic infopackets */ | 618 | /* if using dynamic meta, don't set up generic infopackets */ |
| 618 | pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false; | 619 | pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false; |
| @@ -239,6 +239,10 @@ static void dmcu_set_backlight_level( · 238 unmodified lines | |||
| 239 | s2 |= (backlight_8_bit << ATOM_S2_CURRENT_BL_LEVEL_SHIFT); | 239 | s2 |= (backlight_8_bit << ATOM_S2_CURRENT_BL_LEVEL_SHIFT); |
| 240 | 240 | ||
| 241 | REG_WRITE(BIOS_SCRATCH_2, s2); | 241 | REG_WRITE(BIOS_SCRATCH_2, s2); |
| 242 | |||
| 243 | /* waitDMCUReadyForCmd */ | ||
| 244 | REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, | ||
| 245 | 0, 1, 80000); | ||
| 242 | } | 246 | } |
| 243 | 247 | ||
| 244 | static void dce_abm_init(struct abm *abm) | 248 | static void dce_abm_init(struct abm *abm) |
| @@ -965,11 +965,17 @@ void hwss_edp_backlight_control( · 964 unmodified lines | |||
| 965 | void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx) | 965 | void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx) |
| 966 | { | 966 | { |
| 967 | /* notify audio driver for audio modes of monitor */ | 967 | /* notify audio driver for audio modes of monitor */ |
| 968 | struct dc *core_dc = pipe_ctx->stream->ctx->dc; | 968 | struct dc *core_dc; |
| 969 | struct pp_smu_funcs *pp_smu = NULL; | 969 | struct pp_smu_funcs *pp_smu = NULL; |
| 970 | struct clk_mgr *clk_mgr = core_dc->clk_mgr; | 970 | struct clk_mgr *clk_mgr; |
| 971 | unsigned int i, num_audio = 1; | 971 | unsigned int i, num_audio = 1; |
| 972 | 972 | ||
| 973 | if (!pipe_ctx->stream) | ||
| 974 | return; | ||
| 975 | |||
| 976 | core_dc = pipe_ctx->stream->ctx->dc; | ||
| 977 | clk_mgr = core_dc->clk_mgr; | ||
| 978 | |||
| 973 | if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == true) | 979 | if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == true) |
| 974 | return; | 980 | return; |
| 975 | 981 | ||
| @@ -999,9 +1005,15 @@ void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx) · 23 unmodified lines | |||
| 999 | 1005 | ||
| 1000 | void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx, int option) | 1006 | void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx, int option) |
| 1001 | { | 1007 | { |
| 1002 | struct dc *dc = pipe_ctx->stream->ctx->dc; | 1008 | struct dc *dc; |
| 1003 | struct pp_smu_funcs *pp_smu = NULL; | 1009 | struct pp_smu_funcs *pp_smu = NULL; |
| 1004 | struct clk_mgr *clk_mgr = dc->clk_mgr; | 1010 | struct clk_mgr *clk_mgr; |
| 1011 | |||
| 1012 | if (!pipe_ctx || !pipe_ctx->stream) | ||
| 1013 | return; | ||
| 1014 | |||
| 1015 | dc = pipe_ctx->stream->ctx->dc; | ||
| 1016 | clk_mgr = dc->clk_mgr; | ||
| 1005 | 1017 | ||
| 1006 | if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == false) | 1018 | if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == false) |
| 1007 | return; | 1019 | return; |
| @@ -1009,6 +1021,8 @@ void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx, int option) · 1 unmodified line | |||
| 1009 | pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control( | 1021 | pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control( |
| 1010 | pipe_ctx->stream_res.stream_enc, true); | 1022 | pipe_ctx->stream_res.stream_enc, true); |
| 1011 | if (pipe_ctx->stream_res.audio) { | 1023 | if (pipe_ctx->stream_res.audio) { |
| 1024 | pipe_ctx->stream_res.audio->enabled = false; | ||
| 1025 | |||
| 1012 | if (dc->res_pool->pp_smu) | 1026 | if (dc->res_pool->pp_smu) |
| 1013 | pp_smu = dc->res_pool->pp_smu; | 1027 | pp_smu = dc->res_pool->pp_smu; |
| 1014 | 1028 | ||
| @@ -1039,8 +1053,6 @@ void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx, int option) · 24 unmodified lines | |||
| 1039 | /* dal_audio_disable_azalia_audio_jack_presence(stream->audio, | 1053 | /* dal_audio_disable_azalia_audio_jack_presence(stream->audio, |
| 1040 | * stream->stream_engine_id); | 1054 | * stream->stream_engine_id); |
| 1041 | */ | 1055 | */ |
| 1042 | if (pipe_ctx->stream_res.audio) | ||
| 1043 | pipe_ctx->stream_res.audio->enabled = false; | ||
| 1044 | } | 1056 | } |
| 1045 | } | 1057 | } |
| 1046 | 1058 | ||
| @@ -1195,16 +1195,7 @@ static void dcn10_init_hw(struct dc *dc) · 1194 unmodified lines | |||
| 1195 | * everything down. | 1195 | * everything down. |
| 1196 | */ | 1196 | */ |
| 1197 | if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.power_down_display_on_boot) { | 1197 | if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.power_down_display_on_boot) { |
| 1198 | for (i = 0; i < dc->res_pool->pipe_count; i++) { | 1198 | dc->hwss.init_pipes(dc, dc->current_state); |
| 1199 | struct hubp *hubp = dc->res_pool->hubps[i]; | ||
| 1200 | struct dpp *dpp = dc->res_pool->dpps[i]; | ||
| 1201 | |||
| 1202 | hubp->funcs->hubp_init(hubp); | ||
| 1203 | dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst; | ||
| 1204 | plane_atomic_power_down(dc, dpp, hubp); | ||
| 1205 | } | ||
| 1206 | |||
| 1207 | apply_DEGVIDCN10_253_wa(dc); | ||
| 1208 | } | 1199 | } |
| 1209 | 1200 | ||
| 1210 | for (i = 0; i < dc->res_pool->audio_count; i++) { | 1201 | for (i = 0; i < dc->res_pool->audio_count; i++) { |
| @@ -1375,10 +1366,6 @@ static bool dcn10_set_input_transfer_func(struct pipe_ctx *pipe_ctx, · 164 unmodified lines | |||
| 1375 | return result; | 1366 | return result; |
| 1376 | } | 1367 | } |
| 1377 | 1368 | ||
| 1378 | |||
| 1379 | |||
| 1380 | |||
| 1381 | |||
| 1382 | static bool | 1369 | static bool |
| 1383 | dcn10_set_output_transfer_func(struct pipe_ctx *pipe_ctx, | 1370 | dcn10_set_output_transfer_func(struct pipe_ctx *pipe_ctx, |
| 1384 | const struct dc_stream_state *stream) | 1371 | const struct dc_stream_state *stream) |
| @@ -2516,6 +2503,12 @@ static void dcn10_apply_ctx_for_surface( · 1131 unmodified lines | |||
| 2516 | if (removed_pipe[i]) | 2503 | if (removed_pipe[i]) |
| 2517 | dcn10_disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]); | 2504 | dcn10_disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]); |
| 2518 | 2505 | ||
| 2506 | for (i = 0; i < dc->res_pool->pipe_count; i++) | ||
| 2507 | if (removed_pipe[i]) { | ||
| 2508 | dc->hwss.optimize_bandwidth(dc, context); | ||
| 2509 | break; | ||
| 2510 | } | ||
| 2511 | |||
| 2519 | if (dc->hwseq->wa.DEGVIDCN10_254) | 2512 | if (dc->hwseq->wa.DEGVIDCN10_254) |
| 2520 | hubbub1_wm_change_req_wa(dc->res_pool->hubbub); | 2513 | hubbub1_wm_change_req_wa(dc->res_pool->hubbub); |
| 2521 | } | 2514 | } |
| @@ -508,7 +508,7 @@ static const struct resource_caps rv2_res_cap = { · 507 unmodified lines | |||
| 508 | .num_audio = 3, | 508 | .num_audio = 3, |
| 509 | .num_stream_encoder = 3, | 509 | .num_stream_encoder = 3, |
| 510 | .num_pll = 3, | 510 | .num_pll = 3, |
| 511 | .num_ddc = 3, | 511 | .num_ddc = 4, |
| 512 | }; | 512 | }; |
| 513 | 513 | ||
| 514 | static const struct dc_plane_cap plane_cap = { | 514 | static const struct dc_plane_cap plane_cap = { |
| @@ -102,14 +102,19 @@ void dccg2_init(struct dccg *dccg) · 101 unmodified lines | |||
| 102 | switch (dccg_dcn->base.ctx->dc->res_pool->pipe_count) { | 102 | switch (dccg_dcn->base.ctx->dc->res_pool->pipe_count) { |
| 103 | case 6: | 103 | case 6: |
| 104 | REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[5], 1); | 104 | REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[5], 1); |
| 105 | /* Fall through */ | ||
| 105 | case 5: | 106 | case 5: |
| 106 | REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[4], 1); | 107 | REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[4], 1); |
| 108 | /* Fall through */ | ||
| 107 | case 4: | 109 | case 4: |
| 108 | REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[3], 1); | 110 | REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[3], 1); |
| 111 | /* Fall through */ | ||
| 109 | case 3: | 112 | case 3: |
| 110 | REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[2], 1); | 113 | REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[2], 1); |
| 114 | /* Fall through */ | ||
| 111 | case 2: | 115 | case 2: |
| 112 | REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[1], 1); | 116 | REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[1], 1); |
| 117 | /* Fall through */ | ||
| 113 | case 1: | 118 | case 1: |
| 114 | REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[0], 1); | 119 | REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_DB_EN[0], 1); |
| 115 | break; | 120 | break; |
| @@ -337,6 +337,7 @@ static enum dcn_hubbub_page_table_block_size page_table_block_size_to_hw(unsigne · 336 unmodified lines | |||
| 337 | break; | 337 | break; |
| 338 | default: | 338 | default: |
| 339 | ASSERT(false); | 339 | ASSERT(false); |
| 340 | block_size = page_table_block_size; | ||
| 340 | break; | 341 | break; |
| 341 | } | 342 | } |
| 342 | 343 | ||
| @@ -366,25 +367,24 @@ int hubbub2_init_dchub_sys_ctx(struct hubbub *hubbub, · 23 unmodified lines | |||
| 366 | struct dcn_vmid_page_table_config phys_config; | 367 | struct dcn_vmid_page_table_config phys_config; |
| 367 | 368 | ||
| 368 | REG_SET(DCN_VM_FB_LOCATION_BASE, 0, | 369 | REG_SET(DCN_VM_FB_LOCATION_BASE, 0, |
| 369 | FB_BASE, pa_config->system_aperture.fb_base); | 370 | FB_BASE, pa_config->system_aperture.fb_base >> 24); |
| 370 | REG_SET(DCN_VM_FB_LOCATION_TOP, 0, | 371 | REG_SET(DCN_VM_FB_LOCATION_TOP, 0, |
| 371 | FB_TOP, pa_config->system_aperture.fb_top); | 372 | FB_TOP, pa_config->system_aperture.fb_top >> 24); |
| 372 | REG_SET(DCN_VM_FB_OFFSET, 0, | 373 | REG_SET(DCN_VM_FB_OFFSET, 0, |
| 373 | FB_OFFSET, pa_config->system_aperture.fb_offset); | 374 | FB_OFFSET, pa_config->system_aperture.fb_offset >> 24); |
| 374 | REG_SET(DCN_VM_AGP_BOT, 0, | 375 | REG_SET(DCN_VM_AGP_BOT, 0, |
| 375 | AGP_BOT, pa_config->system_aperture.agp_bot); | 376 | AGP_BOT, pa_config->system_aperture.agp_bot >> 24); |
| 376 | REG_SET(DCN_VM_AGP_TOP, 0, | 377 | REG_SET(DCN_VM_AGP_TOP, 0, |
| 377 | AGP_TOP, pa_config->system_aperture.agp_top); | 378 | AGP_TOP, pa_config->system_aperture.agp_top >> 24); |
| 378 | REG_SET(DCN_VM_AGP_BASE, 0, | 379 | REG_SET(DCN_VM_AGP_BASE, 0, |
| 379 | AGP_BASE, pa_config->system_aperture.agp_base); | 380 | AGP_BASE, pa_config->system_aperture.agp_base >> 24); |
| 380 | 381 | ||
| 381 | if (pa_config->gart_config.page_table_start_addr != pa_config->gart_config.page_table_end_addr) { | 382 | if (pa_config->gart_config.page_table_start_addr != pa_config->gart_config.page_table_end_addr) { |
| 382 | phys_config.depth = 1; | ||
| 383 | phys_config.block_size = 4096; | ||
| 384 | phys_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr >> 12; | 383 | phys_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr >> 12; |
| 385 | phys_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr >> 12; | 384 | phys_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr >> 12; |
| 386 | phys_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr; | 385 | phys_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr; |
| 387 | 386 | phys_config.depth = 0; | |
| 387 | phys_config.block_size = 0; | ||
| 388 | // Init VMID 0 based on PA config | 388 | // Init VMID 0 based on PA config |
| 389 | dcn20_vmid_setup(&hubbub1->vmid[0], &phys_config); | 389 | dcn20_vmid_setup(&hubbub1->vmid[0], &phys_config); |
| 390 | } | 390 | } |
| @@ -1153,8 +1153,8 @@ void dcn20_enable_plane( · 1152 unmodified lines | |||
| 1153 | 1153 | ||
| 1154 | apt.sys_default.quad_part = 0; | 1154 | apt.sys_default.quad_part = 0; |
| 1155 | 1155 | ||
| 1156 | apt.sys_high.quad_part = dc->vm_pa_config.system_aperture.start_addr; | 1156 | apt.sys_low.quad_part = dc->vm_pa_config.system_aperture.start_addr; |
| 1157 | apt.sys_low.quad_part = dc->vm_pa_config.system_aperture.end_addr; | 1157 | apt.sys_high.quad_part = dc->vm_pa_config.system_aperture.end_addr; |
| 1158 | 1158 | ||
| 1159 | // Program system aperture settings | 1159 | // Program system aperture settings |
| 1160 | pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt); | 1160 | pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt); |
| @@ -1242,6 +1242,8 @@ void dcn20_pipe_control_lock_global( · 81 unmodified lines | |||
| 1242 | CRTC_STATE_VACTIVE); | 1242 | CRTC_STATE_VACTIVE); |
| 1243 | pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, | 1243 | pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, |
| 1244 | CRTC_STATE_VBLANK); | 1244 | CRTC_STATE_VBLANK); |
| 1245 | pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, | ||
| 1246 | CRTC_STATE_VACTIVE); | ||
| 1245 | pipe->stream_res.tg->funcs->lock_doublebuffer_disable( | 1247 | pipe->stream_res.tg->funcs->lock_doublebuffer_disable( |
| 1246 | pipe->stream_res.tg); | 1248 | pipe->stream_res.tg); |
| 1247 | } | 1249 | } |
| @@ -1263,6 +1265,17 @@ void dcn20_pipe_control_lock( · 15 unmodified lines | |||
| 1263 | if (pipe->plane_state != NULL) | 1265 | if (pipe->plane_state != NULL) |
| 1264 | flip_immediate = pipe->plane_state->flip_immediate; | 1266 | flip_immediate = pipe->plane_state->flip_immediate; |
| 1265 | 1267 | ||
| 1268 | if (flip_immediate && lock) { | ||
| 1269 | while (pipe->plane_res.hubp->funcs->hubp_is_flip_pending(pipe->plane_res.hubp)) { | ||
| 1270 | udelay(1); | ||
| 1271 | } | ||
| 1272 | |||
| 1273 | if (pipe->bottom_pipe != NULL) | ||
| 1274 | while (pipe->bottom_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(pipe->bottom_pipe->plane_res.hubp)) { | ||
| 1275 | udelay(1); | ||
| 1276 | } | ||
| 1277 | } | ||
| 1278 | |||
| 1266 | /* In flip immediate and pipe splitting case, we need to use GSL | 1279 | /* In flip immediate and pipe splitting case, we need to use GSL |
| 1267 | * for synchronization. Only do setup on locking and on flip type change. | 1280 | * for synchronization. Only do setup on locking and on flip type change. |
| 1268 | */ | 1281 | */ |
| @@ -1740,8 +1753,11 @@ static void dcn20_reset_back_end_for_pipe( · 471 unmodified lines | |||
| 1740 | else if (pipe_ctx->stream_res.audio) { | 1753 | else if (pipe_ctx->stream_res.audio) { |
| 1741 | dc->hwss.disable_audio_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE); | 1754 | dc->hwss.disable_audio_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE); |
| 1742 | } | 1755 | } |
| 1743 | |||
| 1744 | } | 1756 | } |
| 1757 | #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT | ||
| 1758 | else if (pipe_ctx->stream_res.dsc) | ||
| 1759 | dp_set_dsc_enable(pipe_ctx, false); | ||
| 1760 | #endif | ||
| 1745 | 1761 | ||
| 1746 | /* by upper caller loop, parent pipe: pipe0, will be reset last. | 1762 | /* by upper caller loop, parent pipe: pipe0, will be reset last. |
| 1747 | * back end share by all pipes and will be disable only when disable | 1763 | * back end share by all pipes and will be disable only when disable |
| @@ -535,7 +535,7 @@ void dcn20_timing_generator_init(struct optc *optc1) · 534 unmodified lines | |||
| 535 | optc1->min_h_blank = 32; | 535 | optc1->min_h_blank = 32; |
| 536 | optc1->min_v_blank = 3; | 536 | optc1->min_v_blank = 3; |
| 537 | optc1->min_v_blank_interlace = 5; | 537 | optc1->min_v_blank_interlace = 5; |
| 538 | optc1->min_h_sync_width = 8; | 538 | optc1->min_h_sync_width = 4;// Minimum HSYNC = 8 pixels asked By HW in the first place for no actual reason. Oculus Rift S will not light up with 8 as it's hsyncWidth is 6. Changing it to 4 to fix that issue. |
| 539 | optc1->min_v_sync_width = 1; | 539 | optc1->min_v_sync_width = 1; |
| 540 | optc1->comb_opp_id = 0xf; | 540 | optc1->comb_opp_id = 0xf; |
| 541 | } | 541 | } |
| @@ -2643,6 +2643,10 @@ static void update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_ · 2642 unmodified lines | |||
| 2643 | 2643 | ||
| 2644 | if (dc->bb_overrides.min_dcfclk_mhz > 0) | 2644 | if (dc->bb_overrides.min_dcfclk_mhz > 0) |
| 2645 | min_dcfclk = dc->bb_overrides.min_dcfclk_mhz; | 2645 | min_dcfclk = dc->bb_overrides.min_dcfclk_mhz; |
| 2646 | else | ||
| 2647 | // Accounting for SOC/DCF relationship, we can go as high as | ||
| 2648 | // 506Mhz in Vmin. We need to code 507 since SMU will round down to 506. | ||
| 2649 | min_dcfclk = 507; | ||
| 2646 | 2650 | ||
| 2647 | for (i = 0; i < num_states; i++) { | 2651 | for (i = 0; i < num_states; i++) { |
| 2648 | int min_fclk_required_by_uclk; | 2652 | int min_fclk_required_by_uclk; |
| @@ -23,6 +23,8 @@ · 22 unmodified lines | |||
| 23 | * | 23 | * |
| 24 | */ | 24 | */ |
| 25 | 25 | ||
| 26 | #include <linux/delay.h> | ||
| 27 | |||
| 26 | #include "dcn20_vmid.h" | 28 | #include "dcn20_vmid.h" |
| 27 | #include "reg_helper.h" | 29 | #include "reg_helper.h" |
| 28 | 30 | ||
| @@ -36,6 +38,38 @@ · 7 unmodified lines | |||
| 36 | #define FN(reg_name, field_name) \ | 38 | #define FN(reg_name, field_name) \ |
| 37 | vmid->shifts->field_name, vmid->masks->field_name | 39 | vmid->shifts->field_name, vmid->masks->field_name |
| 38 | 40 | ||
| 41 | static void dcn20_wait_for_vmid_ready(struct dcn20_vmid *vmid) | ||
| 42 | { | ||
| 43 | /* According the hardware spec, we need to poll for the lowest | ||
| 44 | * bit of PAGE_TABLE_BASE_ADDR_LO32 = 1 any time a GPUVM | ||
| 45 | * context is updated. We can't use REG_WAIT here since we | ||
| 46 | * don't have a seperate field to wait on. | ||
| 47 | * | ||
| 48 | * TODO: Confirm timeout / poll interval with hardware team | ||
| 49 | */ | ||
| 50 | |||
| 51 | int max_times = 10000; | ||
| 52 | int delay_us = 5; | ||
| 53 | int i; | ||
| 54 | |||
| 55 | for (i = 0; i < max_times; ++i) { | ||
| 56 | uint32_t entry_lo32; | ||
| 57 | |||
| 58 | REG_GET(PAGE_TABLE_BASE_ADDR_LO32, | ||
| 59 | VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32, | ||
| 60 | &entry_lo32); | ||
| 61 | |||
| 62 | if (entry_lo32 & 0x1) | ||
| 63 | return; | ||
| 64 | |||
| 65 | udelay(delay_us); | ||
| 66 | } | ||
| 67 | |||
| 68 | /* VM setup timed out */ | ||
| 69 | DC_LOG_WARNING("Timeout while waiting for GPUVM context update\n"); | ||
| 70 | ASSERT(0); | ||
| 71 | } | ||
| 72 | |||
| 39 | void dcn20_vmid_setup(struct dcn20_vmid *vmid, const struct dcn_vmid_page_table_config *config) | 73 | void dcn20_vmid_setup(struct dcn20_vmid *vmid, const struct dcn_vmid_page_table_config *config) |
| 40 | { | 74 | { |
| 41 | REG_SET(PAGE_TABLE_START_ADDR_HI32, 0, | 75 | REG_SET(PAGE_TABLE_START_ADDR_HI32, 0, |
| @@ -54,6 +88,9 @@ void dcn20_vmid_setup(struct dcn20_vmid *vmid, const struct dcn_vmid_page_table_ · 12 unmodified lines | |||
| 54 | 88 | ||
| 55 | REG_SET(PAGE_TABLE_BASE_ADDR_HI32, 0, | 89 | REG_SET(PAGE_TABLE_BASE_ADDR_HI32, 0, |
| 56 | VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32, (config->page_table_base_addr >> 32) & 0xFFFFFFFF); | 90 | VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32, (config->page_table_base_addr >> 32) & 0xFFFFFFFF); |
| 91 | /* Note: per hardware spec PAGE_TABLE_BASE_ADDR_LO32 must be programmed last in sequence */ | ||
| 57 | REG_SET(PAGE_TABLE_BASE_ADDR_LO32, 0, | 92 | REG_SET(PAGE_TABLE_BASE_ADDR_LO32, 0, |
| 58 | VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32, config->page_table_base_addr & 0xFFFFFFFF); | 93 | VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32, config->page_table_base_addr & 0xFFFFFFFF); |
| 94 | |||
| 95 | dcn20_wait_for_vmid_ready(vmid); | ||
| 59 | } | 96 | } |
| @@ -377,6 +377,12 @@ int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg) · 376 unmodified lines | |||
| 377 | vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16; | 377 | vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16; |
| 378 | vdsc_cfg->initial_dec_delay = hrd_delay - vdsc_cfg->initial_xmit_delay; | 378 | vdsc_cfg->initial_dec_delay = hrd_delay - vdsc_cfg->initial_xmit_delay; |
| 379 | 379 | ||
| 380 | /* As per DSC spec v1.2a recommendation: */ | ||
| 381 | if (vdsc_cfg->native_420) | ||
| 382 | vdsc_cfg->second_line_offset_adj = 512; | ||
| 383 | else | ||
| 384 | vdsc_cfg->second_line_offset_adj = 0; | ||
| 385 | |||
| 380 | return 0; | 386 | return 0; |
| 381 | } | 387 | } |
| 382 | EXPORT_SYMBOL(drm_dsc_compute_rc_parameters); | 388 | EXPORT_SYMBOL(drm_dsc_compute_rc_parameters); |
| @@ -212,7 +212,7 @@ struct resource_pool { · 211 unmodified lines | |||
| 212 | struct clock_source *clock_sources[MAX_CLOCK_SOURCES]; | 212 | struct clock_source *clock_sources[MAX_CLOCK_SOURCES]; |
| 213 | unsigned int clk_src_count; | 213 | unsigned int clk_src_count; |
| 214 | 214 | ||
| 215 | struct audio *audios[MAX_PIPES]; | 215 | struct audio *audios[MAX_AUDIOS]; |
| 216 | unsigned int audio_count; | 216 | unsigned int audio_count; |
| 217 | struct audio_support audio_support; | 217 | struct audio_support audio_support; |
| 218 | 218 | ||
| @@ -61,8 +61,8 @@ enum dcn_hubbub_page_table_depth { · 60 unmodified lines | |||
| 61 | }; | 61 | }; |
| 62 | 62 | ||
| 63 | enum dcn_hubbub_page_table_block_size { | 63 | enum dcn_hubbub_page_table_block_size { |
| 64 | DCN_PAGE_TABLE_BLOCK_SIZE_4KB, | 64 | DCN_PAGE_TABLE_BLOCK_SIZE_4KB = 0, |
| 65 | DCN_PAGE_TABLE_BLOCK_SIZE_64KB | 65 | DCN_PAGE_TABLE_BLOCK_SIZE_64KB = 4, |
| 66 | }; | 66 | }; |
| 67 | 67 | ||
| 68 | struct dcn_hubbub_phys_addr_config { | 68 | struct dcn_hubbub_phys_addr_config { |
| @@ -34,6 +34,7 @@ · 33 unmodified lines | |||
| 34 | * Data types shared between different Virtual HW blocks | 34 | * Data types shared between different Virtual HW blocks |
| 35 | ******************************************************************************/ | 35 | ******************************************************************************/ |
| 36 | 36 | ||
| 37 | #define MAX_AUDIOS 7 | ||
| 37 | #define MAX_PIPES 6 | 38 | #define MAX_PIPES 6 |
| 38 | #if defined(CONFIG_DRM_AMD_DC_DCN2_0) | 39 | #if defined(CONFIG_DRM_AMD_DC_DCN2_0) |
| 39 | #define MAX_DWB_PIPES 1 | 40 | #define MAX_DWB_PIPES 1 |
| @@ -43,7 +43,7 @@ enum dpcd_revision { · 42 unmodified lines | |||
| 43 | enum dpcd_downstream_port_type { | 43 | enum dpcd_downstream_port_type { |
| 44 | DOWNSTREAM_DP = 0, | 44 | DOWNSTREAM_DP = 0, |
| 45 | DOWNSTREAM_VGA, | 45 | DOWNSTREAM_VGA, |
| 46 | DOWNSTREAM_DVI_HDMI, | 46 | DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS,/* DVI, HDMI, DP++ */ |
| 47 | DOWNSTREAM_NONDDC /* has no EDID (TV,CV) */ | 47 | DOWNSTREAM_NONDDC /* has no EDID (TV,CV) */ |
| 48 | }; | 48 | }; |
| 49 | 49 | ||
| @@ -123,6 +123,7 @@ enum amd_pp_sensors { · 122 unmodified lines | |||
| 123 | AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, | 123 | AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, |
| 124 | AMDGPU_PP_SENSOR_MIN_FAN_RPM, | 124 | AMDGPU_PP_SENSOR_MIN_FAN_RPM, |
| 125 | AMDGPU_PP_SENSOR_MAX_FAN_RPM, | 125 | AMDGPU_PP_SENSOR_MAX_FAN_RPM, |
| 126 | AMDGPU_PP_SENSOR_VCN_POWER_STATE, | ||
| 126 | }; | 127 | }; |
| 127 | 128 | ||
| 128 | enum amd_pp_task { | 129 | enum amd_pp_task { |
| @@ -137,12 +137,37 @@ int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, · 136 unmodified lines | |||
| 137 | { | 137 | { |
| 138 | int ret = 0, clk_id = 0; | 138 | int ret = 0, clk_id = 0; |
| 139 | uint32_t param = 0; | 139 | uint32_t param = 0; |
| 140 | uint32_t clock_limit; | ||
| 140 | 141 | ||
| 141 | if (!min && !max) | 142 | if (!min && !max) |
| 142 | return -EINVAL; | 143 | return -EINVAL; |
| 143 | 144 | ||
| 144 | if (!smu_clk_dpm_is_enabled(smu, clk_type)) | 145 | if (!smu_clk_dpm_is_enabled(smu, clk_type)) { |
| 146 | switch (clk_type) { | ||
| 147 | case SMU_MCLK: | ||
| 148 | case SMU_UCLK: | ||
| 149 | clock_limit = smu->smu_table.boot_values.uclk; | ||
| 150 | break; | ||
| 151 | case SMU_GFXCLK: | ||
| 152 | case SMU_SCLK: | ||
| 153 | clock_limit = smu->smu_table.boot_values.gfxclk; | ||
| 154 | break; | ||
| 155 | case SMU_SOCCLK: | ||
| 156 | clock_limit = smu->smu_table.boot_values.socclk; | ||
| 157 | break; | ||
| 158 | default: | ||
| 159 | clock_limit = 0; | ||
| 160 | break; | ||
| 161 | } | ||
| 162 | |||
| 163 | /* clock in Mhz unit */ | ||
| 164 | if (min) | ||
| 165 | *min = clock_limit / 100; | ||
| 166 | if (max) | ||
| 167 | *max = clock_limit / 100; | ||
| 168 | |||
| 145 | return 0; | 169 | return 0; |
| 170 | } | ||
| 146 | 171 | ||
| 147 | mutex_lock(&smu->mutex); | 172 | mutex_lock(&smu->mutex); |
| 148 | clk_id = smu_clk_get_index(smu, clk_type); | 173 | clk_id = smu_clk_get_index(smu, clk_type); |
| @@ -281,7 +306,8 @@ int smu_get_power_num_states(struct smu_context *smu, · 132 unmodified lines | |||
| 281 | 306 | ||
| 282 | /* not support power state */ | 307 | /* not support power state */ |
| 283 | memset(state_info, 0, sizeof(struct pp_states_info)); | 308 | memset(state_info, 0, sizeof(struct pp_states_info)); |
| 284 | state_info->nums = 0; | 309 | state_info->nums = 1; |
| 310 | state_info->states[0] = POWER_STATE_TYPE_DEFAULT; | ||
| 285 | 311 | ||
| 286 | return 0; | 312 | return 0; |
| 287 | } | 313 | } |
| @@ -289,6 +315,8 @@ int smu_get_power_num_states(struct smu_context *smu, · 1 unmodified line | |||
| 289 | int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor, | 315 | int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor, |
| 290 | void *data, uint32_t *size) | 316 | void *data, uint32_t *size) |
| 291 | { | 317 | { |
| 318 | struct smu_power_context *smu_power = &smu->smu_power; | ||
| 319 | struct smu_power_gate *power_gate = &smu_power->power_gate; | ||
| 292 | int ret = 0; | 320 | int ret = 0; |
| 293 | 321 | ||
| 294 | switch (sensor) { | 322 | switch (sensor) { |
| @@ -312,6 +340,10 @@ int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor, · 17 unmodified lines | |||
| 312 | *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; | 340 | *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; |
| 313 | *size = 4; | 341 | *size = 4; |
| 314 | break; | 342 | break; |
| 343 | case AMDGPU_PP_SENSOR_VCN_POWER_STATE: | ||
| 344 | *(uint32_t *)data = power_gate->vcn_gated ? 0 : 1; | ||
| 345 | *size = 4; | ||
| 346 | break; | ||
| 315 | default: | 347 | default: |
| 316 | ret = -EINVAL; | 348 | ret = -EINVAL; |
| 317 | break; | 349 | break; |
| @@ -698,6 +730,12 @@ static int smu_sw_init(void *handle) · 380 unmodified lines | |||
| 698 | return ret; | 730 | return ret; |
| 699 | } | 731 | } |
| 700 | 732 | ||
| 733 | ret = smu_register_irq_handler(smu); | ||
| 734 | if (ret) { | ||
| 735 | pr_err("Failed to register smc irq handler!\n"); | ||
| 736 | return ret; | ||
| 737 | } | ||
| 738 | |||
| 701 | return 0; | 739 | return 0; |
| 702 | } | 740 | } |
| 703 | 741 | ||
| @@ -707,6 +745,9 @@ static int smu_sw_fini(void *handle) · 3 unmodified lines | |||
| 707 | struct smu_context *smu = &adev->smu; | 745 | struct smu_context *smu = &adev->smu; |
| 708 | int ret; | 746 | int ret; |
| 709 | 747 | ||
| 748 | kfree(smu->irq_source); | ||
| 749 | smu->irq_source = NULL; | ||
| 750 | |||
| 710 | ret = smu_smc_table_sw_fini(smu); | 751 | ret = smu_smc_table_sw_fini(smu); |
| 711 | if (ret) { | 752 | if (ret) { |
| 712 | pr_err("Failed to sw fini smc table!\n"); | 753 | pr_err("Failed to sw fini smc table!\n"); |
| @@ -1063,10 +1104,6 @@ static int smu_hw_init(void *handle) · 350 unmodified lines | |||
| 1063 | if (ret) | 1104 | if (ret) |
| 1064 | goto failed; | 1105 | goto failed; |
| 1065 | 1106 | ||
| 1066 | ret = smu_register_irq_handler(smu); | ||
| 1067 | if (ret) | ||
| 1068 | goto failed; | ||
| 1069 | |||
| 1070 | if (!smu->pm_enabled) | 1107 | if (!smu->pm_enabled) |
| 1071 | adev->pm.dpm_enabled = false; | 1108 | adev->pm.dpm_enabled = false; |
| 1072 | else | 1109 | else |
| @@ -1096,9 +1133,6 @@ static int smu_hw_fini(void *handle) · 23 unmodified lines | |||
| 1096 | kfree(table_context->overdrive_table); | 1133 | kfree(table_context->overdrive_table); |
| 1097 | table_context->overdrive_table = NULL; | 1134 | table_context->overdrive_table = NULL; |
| 1098 | 1135 | ||
| 1099 | kfree(smu->irq_source); | ||
| 1100 | smu->irq_source = NULL; | ||
| 1101 | |||
| 1102 | ret = smu_fini_fb_allocations(smu); | 1136 | ret = smu_fini_fb_allocations(smu); |
| 1103 | if (ret) | 1137 | if (ret) |
| 1104 | return ret; | 1138 | return ret; |
| @@ -1349,13 +1383,49 @@ static int smu_enable_umd_pstate(void *handle, · 244 unmodified lines | |||
| 1349 | return 0; | 1383 | return 0; |
| 1350 | } | 1384 | } |
| 1351 | 1385 | ||
| 1386 | static int smu_default_set_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level) | ||
| 1387 | { | ||
| 1388 | int ret = 0; | ||
| 1389 | uint32_t sclk_mask, mclk_mask, soc_mask; | ||
| 1390 | |||
| 1391 | switch (level) { | ||
| 1392 | case AMD_DPM_FORCED_LEVEL_HIGH: | ||
| 1393 | ret = smu_force_dpm_limit_value(smu, true); | ||
| 1394 | break; | ||
| 1395 | case AMD_DPM_FORCED_LEVEL_LOW: | ||
| 1396 | ret = smu_force_dpm_limit_value(smu, false); | ||
| 1397 | break; | ||
| 1398 | case AMD_DPM_FORCED_LEVEL_AUTO: | ||
| 1399 | case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: | ||
| 1400 | ret = smu_unforce_dpm_levels(smu); | ||
| 1401 | break; | ||
| 1402 | case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: | ||
| 1403 | case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: | ||
| 1404 | case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: | ||
| 1405 | ret = smu_get_profiling_clk_mask(smu, level, | ||
| 1406 | &sclk_mask, | ||
| 1407 | &mclk_mask, | ||
| 1408 | &soc_mask); | ||
| 1409 | if (ret) | ||
| 1410 | return ret; | ||
| 1411 | smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask); | ||
| 1412 | smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask); | ||
| 1413 | smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask); | ||
| 1414 | break; | ||
| 1415 | case AMD_DPM_FORCED_LEVEL_MANUAL: | ||
| 1416 | case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: | ||
| 1417 | default: | ||
| 1418 | break; | ||
| 1419 | } | ||
| 1420 | return ret; | ||
| 1421 | } | ||
| 1422 | |||
| 1352 | int smu_adjust_power_state_dynamic(struct smu_context *smu, | 1423 | int smu_adjust_power_state_dynamic(struct smu_context *smu, |
| 1353 | enum amd_dpm_forced_level level, | 1424 | enum amd_dpm_forced_level level, |
| 1354 | bool skip_display_settings) | 1425 | bool skip_display_settings) |
| 1355 | { | 1426 | { |
| 1356 | int ret = 0; | 1427 | int ret = 0; |
| 1357 | int index = 0; | 1428 | int index = 0; |
| 1358 | uint32_t sclk_mask, mclk_mask, soc_mask; | ||
| 1359 | long workload; | 1429 | long workload; |
| 1360 | struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); | 1430 | struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); |
| 1361 | 1431 | ||
| @@ -1386,39 +1456,10 @@ int smu_adjust_power_state_dynamic(struct smu_context *smu, · 24 unmodified lines | |||
| 1386 | } | 1456 | } |
| 1387 | 1457 | ||
| 1388 | if (smu_dpm_ctx->dpm_level != level) { | 1458 | if (smu_dpm_ctx->dpm_level != level) { |
| 1389 | switch (level) { | 1459 | ret = smu_asic_set_performance_level(smu, level); |
| 1390 | case AMD_DPM_FORCED_LEVEL_HIGH: | 1460 | if (ret) { |
| 1391 | ret = smu_force_dpm_limit_value(smu, true); | 1461 | ret = smu_default_set_performance_level(smu, level); |
| 1392 | break; | ||
| 1393 | case AMD_DPM_FORCED_LEVEL_LOW: | ||
| 1394 | ret = smu_force_dpm_limit_value(smu, false); | ||
| 1395 | break; | ||
| 1396 | |||
| 1397 | case AMD_DPM_FORCED_LEVEL_AUTO: | ||
| 1398 | case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: | ||
| 1399 | ret = smu_unforce_dpm_levels(smu); | ||
| 1400 | break; | ||
| 1401 | |||
| 1402 | case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: | ||
| 1403 | case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: | ||
| 1404 | case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: | ||
| 1405 | ret = smu_get_profiling_clk_mask(smu, level, | ||
| 1406 | &sclk_mask, | ||
| 1407 | &mclk_mask, | ||
| 1408 | &soc_mask); | ||
| 1409 | if (ret) | ||
| 1410 | return ret; | ||
| 1411 | smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask); | ||
| 1412 | smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask); | ||
| 1413 | smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask); | ||
| 1414 | break; | ||
| 1415 | |||
| 1416 | case AMD_DPM_FORCED_LEVEL_MANUAL: | ||
| 1417 | case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: | ||
| 1418 | default: | ||
| 1419 | break; | ||
| 1420 | } | 1462 | } |
| 1421 | |||
| 1422 | if (!ret) | 1463 | if (!ret) |
| 1423 | smu_dpm_ctx->dpm_level = level; | 1464 | smu_dpm_ctx->dpm_level = level; |
| 1424 | } | 1465 | } |
| @@ -1111,6 +1111,7 @@ static int smu10_thermal_get_temperature(struct pp_hwmgr *hwmgr) · 1110 unmodified lines | |||
| 1111 | static int smu10_read_sensor(struct pp_hwmgr *hwmgr, int idx, | 1111 | static int smu10_read_sensor(struct pp_hwmgr *hwmgr, int idx, |
| 1112 | void *value, int *size) | 1112 | void *value, int *size) |
| 1113 | { | 1113 | { |
| 1114 | struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); | ||
| 1114 | uint32_t sclk, mclk; | 1115 | uint32_t sclk, mclk; |
| 1115 | int ret = 0; | 1116 | int ret = 0; |
| 1116 | 1117 | ||
| @@ -1132,6 +1133,10 @@ static int smu10_read_sensor(struct pp_hwmgr *hwmgr, int idx, · 15 unmodified lines | |||
| 1132 | case AMDGPU_PP_SENSOR_GPU_TEMP: | 1133 | case AMDGPU_PP_SENSOR_GPU_TEMP: |
| 1133 | *((uint32_t *)value) = smu10_thermal_get_temperature(hwmgr); | 1134 | *((uint32_t *)value) = smu10_thermal_get_temperature(hwmgr); |
| 1134 | break; | 1135 | break; |
| 1136 | case AMDGPU_PP_SENSOR_VCN_POWER_STATE: | ||
| 1137 | *(uint32_t *)value = smu10_data->vcn_power_gated ? 0 : 1; | ||
| 1138 | *size = 4; | ||
| 1139 | break; | ||
| 1135 | default: | 1140 | default: |
| 1136 | ret = -EINVAL; | 1141 | ret = -EINVAL; |
| 1137 | break; | 1142 | break; |
| @@ -1175,18 +1180,22 @@ static int smu10_powergate_sdma(struct pp_hwmgr *hwmgr, bool gate) · 37 unmodified lines | |||
| 1175 | 1180 | ||
| 1176 | static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate) | 1181 | static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate) |
| 1177 | { | 1182 | { |
| 1183 | struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); | ||
| 1184 | |||
| 1178 | if (bgate) { | 1185 | if (bgate) { |
| 1179 | amdgpu_device_ip_set_powergating_state(hwmgr->adev, | 1186 | amdgpu_device_ip_set_powergating_state(hwmgr->adev, |
| 1180 | AMD_IP_BLOCK_TYPE_VCN, | 1187 | AMD_IP_BLOCK_TYPE_VCN, |
| 1181 | AMD_PG_STATE_GATE); | 1188 | AMD_PG_STATE_GATE); |
| 1182 | smum_send_msg_to_smc_with_parameter(hwmgr, | 1189 | smum_send_msg_to_smc_with_parameter(hwmgr, |
| 1183 | PPSMC_MSG_PowerDownVcn, 0); | 1190 | PPSMC_MSG_PowerDownVcn, 0); |
| 1191 | smu10_data->vcn_power_gated = true; | ||
| 1184 | } else { | 1192 | } else { |
| 1185 | smum_send_msg_to_smc_with_parameter(hwmgr, | 1193 | smum_send_msg_to_smc_with_parameter(hwmgr, |
| 1186 | PPSMC_MSG_PowerUpVcn, 0); | 1194 | PPSMC_MSG_PowerUpVcn, 0); |
| 1187 | amdgpu_device_ip_set_powergating_state(hwmgr->adev, | 1195 | amdgpu_device_ip_set_powergating_state(hwmgr->adev, |
| 1188 | AMD_IP_BLOCK_TYPE_VCN, | 1196 | AMD_IP_BLOCK_TYPE_VCN, |
| 1189 | AMD_PG_STATE_UNGATE); | 1197 | AMD_PG_STATE_UNGATE); |
| 1198 | smu10_data->vcn_power_gated = false; | ||
| 1190 | } | 1199 | } |
| 1191 | } | 1200 | } |
| 1192 | 1201 | ||
| @@ -429,7 +429,6 @@ struct smu_table_context · 428 unmodified lines | |||
| 429 | struct smu_table *tables; | 429 | struct smu_table *tables; |
| 430 | uint32_t table_count; | 430 | uint32_t table_count; |
| 431 | struct smu_table memory_pool; | 431 | struct smu_table memory_pool; |
| 432 | uint16_t software_shutdown_temp; | ||
| 433 | uint8_t thermal_controller_type; | 432 | uint8_t thermal_controller_type; |
| 434 | uint16_t TDPODLimit; | 433 | uint16_t TDPODLimit; |
| 435 | 434 | ||
| @@ -452,6 +451,7 @@ struct smu_dpm_context { · 16 unmodified lines | |||
| 452 | struct smu_power_gate { | 451 | struct smu_power_gate { |
| 453 | bool uvd_gated; | 452 | bool uvd_gated; |
| 454 | bool vce_gated; | 453 | bool vce_gated; |
| 454 | bool vcn_gated; | ||
| 455 | }; | 455 | }; |
| 456 | 456 | ||
| 457 | struct smu_power_context { | 457 | struct smu_power_context { |
| @@ -613,6 +613,7 @@ struct pptable_funcs { · 155 unmodified lines | |||
| 613 | int (*tables_init)(struct smu_context *smu, struct smu_table *tables); | 613 | int (*tables_init)(struct smu_context *smu, struct smu_table *tables); |
| 614 | int (*set_thermal_fan_table)(struct smu_context *smu); | 614 | int (*set_thermal_fan_table)(struct smu_context *smu); |
| 615 | int (*get_fan_speed_percent)(struct smu_context *smu, uint32_t *speed); | 615 | int (*get_fan_speed_percent)(struct smu_context *smu, uint32_t *speed); |
| 616 | int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed); | ||
| 616 | int (*set_watermarks_table)(struct smu_context *smu, void *watermarks, | 617 | int (*set_watermarks_table)(struct smu_context *smu, void *watermarks, |
| 617 | struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges); | 618 | struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges); |
| 618 | int (*get_current_clk_freq_by_table)(struct smu_context *smu, | 619 | int (*get_current_clk_freq_by_table)(struct smu_context *smu, |
| @@ -621,6 +622,7 @@ struct pptable_funcs { · 2 unmodified lines | |||
| 621 | int (*get_thermal_temperature_range)(struct smu_context *smu, struct smu_temperature_range *range); | 622 | int (*get_thermal_temperature_range)(struct smu_context *smu, struct smu_temperature_range *range); |
| 622 | int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states); | 623 | int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states); |
| 623 | int (*set_default_od_settings)(struct smu_context *smu, bool initialize); | 624 | int (*set_default_od_settings)(struct smu_context *smu, bool initialize); |
| 625 | int (*set_performance_level)(struct smu_context *smu, enum amd_dpm_forced_level level); | ||
| 624 | }; | 626 | }; |
| 625 | 627 | ||
| 626 | struct smu_funcs | 628 | struct smu_funcs |
| @@ -685,7 +687,6 @@ struct smu_funcs · 58 unmodified lines | |||
| 685 | int (*set_watermarks_for_clock_ranges)(struct smu_context *smu, | 687 | int (*set_watermarks_for_clock_ranges)(struct smu_context *smu, |
| 686 | struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges); | 688 | struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges); |
| 687 | int (*conv_power_profile_to_pplib_workload)(int power_profile); | 689 | int (*conv_power_profile_to_pplib_workload)(int power_profile); |
| 688 | int (*get_current_rpm)(struct smu_context *smu, uint32_t *speed); | ||
| 689 | uint32_t (*get_fan_control_mode)(struct smu_context *smu); | 690 | uint32_t (*get_fan_control_mode)(struct smu_context *smu); |
| 690 | int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode); | 691 | int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode); |
| 691 | int (*set_fan_speed_percent)(struct smu_context *smu, uint32_t speed); | 692 | int (*set_fan_speed_percent)(struct smu_context *smu, uint32_t speed); |
| @@ -751,8 +752,6 @@ struct smu_funcs · 59 unmodified lines | |||
| 751 | ((smu)->funcs->init_max_sustainable_clocks ? (smu)->funcs->init_max_sustainable_clocks((smu)) : 0) | 752 | ((smu)->funcs->init_max_sustainable_clocks ? (smu)->funcs->init_max_sustainable_clocks((smu)) : 0) |
| 752 | #define smu_set_default_od_settings(smu, initialize) \ | 753 | #define smu_set_default_od_settings(smu, initialize) \ |
| 753 | ((smu)->ppt_funcs->set_default_od_settings ? (smu)->ppt_funcs->set_default_od_settings((smu), (initialize)) : 0) | 754 | ((smu)->ppt_funcs->set_default_od_settings ? (smu)->ppt_funcs->set_default_od_settings((smu), (initialize)) : 0) |
| 754 | #define smu_get_current_rpm(smu, speed) \ | ||
| 755 | ((smu)->funcs->get_current_rpm ? (smu)->funcs->get_current_rpm((smu), (speed)) : 0) | ||
| 756 | #define smu_set_fan_speed_rpm(smu, speed) \ | 755 | #define smu_set_fan_speed_rpm(smu, speed) \ |
| 757 | ((smu)->funcs->set_fan_speed_rpm ? (smu)->funcs->set_fan_speed_rpm((smu), (speed)) : 0) | 756 | ((smu)->funcs->set_fan_speed_rpm ? (smu)->funcs->set_fan_speed_rpm((smu), (speed)) : 0) |
| 758 | #define smu_send_smc_msg(smu, msg) \ | 757 | #define smu_send_smc_msg(smu, msg) \ |
| @@ -841,6 +840,8 @@ struct smu_funcs · 82 unmodified lines | |||
| 841 | ((smu)->ppt_funcs->get_fan_speed_percent ? (smu)->ppt_funcs->get_fan_speed_percent((smu), (speed)) : 0) | 840 | ((smu)->ppt_funcs->get_fan_speed_percent ? (smu)->ppt_funcs->get_fan_speed_percent((smu), (speed)) : 0) |
| 842 | #define smu_set_fan_speed_percent(smu, speed) \ | 841 | #define smu_set_fan_speed_percent(smu, speed) \ |
| 843 | ((smu)->funcs->set_fan_speed_percent ? (smu)->funcs->set_fan_speed_percent((smu), (speed)) : 0) | 842 | ((smu)->funcs->set_fan_speed_percent ? (smu)->funcs->set_fan_speed_percent((smu), (speed)) : 0) |
| 843 | #define smu_get_fan_speed_rpm(smu, speed) \ | ||
| 844 | ((smu)->ppt_funcs->get_fan_speed_rpm ? (smu)->ppt_funcs->get_fan_speed_rpm((smu), (speed)) : 0) | ||
| 844 | 845 | ||
| 845 | #define smu_msg_get_index(smu, msg) \ | 846 | #define smu_msg_get_index(smu, msg) \ |
| 846 | ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_msg_index? (smu)->ppt_funcs->get_smu_msg_index((smu), (msg)) : -EINVAL) : -EINVAL) | 847 | ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_msg_index? (smu)->ppt_funcs->get_smu_msg_index((smu), (msg)) : -EINVAL) : -EINVAL) |
| @@ -918,6 +919,9 @@ struct smu_funcs · 71 unmodified lines | |||
| 918 | ((smu)->funcs->baco_get_state? (smu)->funcs->baco_get_state((smu), (state)) : 0) | 919 | ((smu)->funcs->baco_get_state? (smu)->funcs->baco_get_state((smu), (state)) : 0) |
| 919 | #define smu_baco_reset(smu) \ | 920 | #define smu_baco_reset(smu) \ |
| 920 | ((smu)->funcs->baco_reset? (smu)->funcs->baco_reset((smu)) : 0) | 921 | ((smu)->funcs->baco_reset? (smu)->funcs->baco_reset((smu)) : 0) |
| 922 | #define smu_asic_set_performance_level(smu, level) \ | ||
| 923 | ((smu)->ppt_funcs->set_performance_level? (smu)->ppt_funcs->set_performance_level((smu), (level)) : -EINVAL); | ||
| 924 | |||
| 921 | 925 | ||
| 922 | extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table, | 926 | extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table, |
| 923 | uint16_t *size, uint8_t *frev, uint8_t *crev, | 927 | uint16_t *size, uint8_t *frev, uint8_t *crev, |
| @@ -23,6 +23,7 @@ · 22 unmodified lines | |||
| 23 | 23 | ||
| 24 | #include "pp_debug.h" | 24 | #include "pp_debug.h" |
| 25 | #include <linux/firmware.h> | 25 | #include <linux/firmware.h> |
| 26 | #include <linux/pci.h> | ||
| 26 | #include "amdgpu.h" | 27 | #include "amdgpu.h" |
| 27 | #include "amdgpu_smu.h" | 28 | #include "amdgpu_smu.h" |
| 28 | #include "atomfirmware.h" | 29 | #include "atomfirmware.h" |
| @@ -501,6 +502,8 @@ static int navi10_store_powerplay_table(struct smu_context *smu) · 472 unmodified lines | |||
| 501 | 502 | ||
| 502 | static int navi10_tables_init(struct smu_context *smu, struct smu_table *tables) | 503 | static int navi10_tables_init(struct smu_context *smu, struct smu_table *tables) |
| 503 | { | 504 | { |
| 505 | struct smu_table_context *smu_table = &smu->smu_table; | ||
| 506 | |||
| 504 | SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t), | 507 | SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t), |
| 505 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); | 508 | PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); |
| 506 | SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), | 509 | SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), |
| @@ -515,9 +518,35 @@ static int navi10_tables_init(struct smu_context *smu, struct smu_table *tables) · 8 unmodified lines | |||
| 515 | sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE, | 518 | sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE, |
| 516 | AMDGPU_GEM_DOMAIN_VRAM); | 519 | AMDGPU_GEM_DOMAIN_VRAM); |
| 517 | 520 | ||
| 521 | smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL); | ||
| 522 | if (!smu_table->metrics_table) | ||
| 523 | return -ENOMEM; | ||
| 524 | smu_table->metrics_time = 0; | ||
| 525 | |||
| 518 | return 0; | 526 | return 0; |
| 519 | } | 527 | } |
| 520 | 528 | ||
| 529 | static int navi10_get_metrics_table(struct smu_context *smu, | ||
| 530 | SmuMetrics_t *metrics_table) | ||
| 531 | { | ||
| 532 | struct smu_table_context *smu_table= &smu->smu_table; | ||
| 533 | int ret = 0; | ||
| 534 | |||
| 535 | if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + HZ / 1000)) { | ||
| 536 | ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0, | ||
| 537 | (void *)smu_table->metrics_table, false); | ||
| 538 | if (ret) { | ||
| 539 | pr_info("Failed to export SMU metrics table!\n"); | ||
| 540 | return ret; | ||
| 541 | } | ||
| 542 | smu_table->metrics_time = jiffies; | ||
| 543 | } | ||
| 544 | |||
| 545 | memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t)); | ||
| 546 | |||
| 547 | return ret; | ||
| 548 | } | ||
| 549 | |||
| 521 | static int navi10_allocate_dpm_context(struct smu_context *smu) | 550 | static int navi10_allocate_dpm_context(struct smu_context *smu) |
| 522 | { | 551 | { |
| 523 | struct smu_dpm_context *smu_dpm = &smu->smu_dpm; | 552 | struct smu_dpm_context *smu_dpm = &smu->smu_dpm; |
| @@ -576,44 +605,38 @@ static int navi10_set_default_dpm_table(struct smu_context *smu) · 52 unmodified lines | |||
| 576 | 605 | ||
| 577 | static int navi10_dpm_set_uvd_enable(struct smu_context *smu, bool enable) | 606 | static int navi10_dpm_set_uvd_enable(struct smu_context *smu, bool enable) |
| 578 | { | 607 | { |
| 579 | int ret = 0; | ||
| 580 | struct smu_power_context *smu_power = &smu->smu_power; | 608 | struct smu_power_context *smu_power = &smu->smu_power; |
| 581 | struct smu_power_gate *power_gate = &smu_power->power_gate; | 609 | struct smu_power_gate *power_gate = &smu_power->power_gate; |
| 610 | int ret = 0; | ||
| 582 | 611 | ||
| 583 | if (enable && power_gate->uvd_gated) { | 612 | if (enable) { |
| 584 | if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) { | 613 | /* vcn dpm on is a prerequisite for vcn power gate messages */ |
| 614 | if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { | ||
| 585 | ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1); | 615 | ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1); |
| 586 | if (ret) | 616 | if (ret) |
| 587 | return ret; | 617 | return ret; |
| 588 | } | 618 | } |
| 589 | power_gate->uvd_gated = false; | 619 | power_gate->vcn_gated = false; |
| 590 | } else { | 620 | } else { |
| 591 | if (!enable && !power_gate->uvd_gated) { | 621 | if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { |
| 592 | if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) { | 622 | ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn); |
| 593 | ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn); | 623 | if (ret) |
| 594 | if (ret) | 624 | return ret; |
| 595 | return ret; | ||
| 596 | } | ||
| 597 | power_gate->uvd_gated = true; | ||
| 598 | } | 625 | } |
| 626 | power_gate->vcn_gated = true; | ||
| 599 | } | 627 | } |
| 600 | 628 | ||
| 601 | return 0; | 629 | return ret; |
| 602 | } | 630 | } |
| 603 | 631 | ||
| 604 | static int navi10_get_current_clk_freq_by_table(struct smu_context *smu, | 632 | static int navi10_get_current_clk_freq_by_table(struct smu_context *smu, |
| 605 | enum smu_clk_type clk_type, | 633 | enum smu_clk_type clk_type, |
| 606 | uint32_t *value) | 634 | uint32_t *value) |
| 607 | { | 635 | { |
| 608 | static SmuMetrics_t metrics; | ||
| 609 | int ret = 0, clk_id = 0; | 636 | int ret = 0, clk_id = 0; |
| 637 | SmuMetrics_t metrics; | ||
| 610 | 638 | ||
| 611 | if (!value) | 639 | ret = navi10_get_metrics_table(smu, &metrics); |
| 612 | return -EINVAL; | ||
| 613 | |||
| 614 | memset(&metrics, 0, sizeof(metrics)); | ||
| 615 | |||
| 616 | ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0, (void *)&metrics, false); | ||
| 617 | if (ret) | 640 | if (ret) |
| 618 | return ret; | 641 | return ret; |
| 619 | 642 | ||
| @@ -626,11 +649,26 @@ static int navi10_get_current_clk_freq_by_table(struct smu_context *smu, · 6 unmodified lines | |||
| 626 | return ret; | 649 | return ret; |
| 627 | } | 650 | } |
| 628 | 651 | ||
| 652 | static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type) | ||
| 653 | { | ||
| 654 | PPTable_t *pptable = smu->smu_table.driver_pptable; | ||
| 655 | DpmDescriptor_t *dpm_desc = NULL; | ||
| 656 | uint32_t clk_index = 0; | ||
| 657 | |||
| 658 | clk_index = smu_clk_get_index(smu, clk_type); | ||
| 659 | dpm_desc = &pptable->DpmDescriptor[clk_index]; | ||
| 660 | |||
| 661 | /* 0 - Fine grained DPM, 1 - Discrete DPM */ | ||
| 662 | return dpm_desc->SnapToDiscrete == 0 ? true : false; | ||
| 663 | } | ||
| 664 | |||
| 629 | static int navi10_print_clk_levels(struct smu_context *smu, | 665 | static int navi10_print_clk_levels(struct smu_context *smu, |
| 630 | enum smu_clk_type clk_type, char *buf) | 666 | enum smu_clk_type clk_type, char *buf) |
| 631 | { | 667 | { |
| 632 | int i, size = 0, ret = 0; | 668 | int i, size = 0, ret = 0; |
| 633 | uint32_t cur_value = 0, value = 0, count = 0; | 669 | uint32_t cur_value = 0, value = 0, count = 0; |
| 670 | uint32_t freq_values[3] = {0}; | ||
| 671 | uint32_t mark_index = 0; | ||
| 634 | 672 | ||
| 635 | switch (clk_type) { | 673 | switch (clk_type) { |
| 636 | case SMU_GFXCLK: | 674 | case SMU_GFXCLK: |
| @@ -643,22 +681,42 @@ static int navi10_print_clk_levels(struct smu_context *smu, · 6 unmodified lines | |||
| 643 | ret = smu_get_current_clk_freq(smu, clk_type, &cur_value); | 681 | ret = smu_get_current_clk_freq(smu, clk_type, &cur_value); |
| 644 | if (ret) | 682 | if (ret) |
| 645 | return size; | 683 | return size; |
| 684 | |||
| 646 | /* 10KHz -> MHz */ | 685 | /* 10KHz -> MHz */ |
| 647 | cur_value = cur_value / 100; | 686 | cur_value = cur_value / 100; |
| 648 | 687 | ||
| 649 | size += sprintf(buf, "current clk: %uMhz\n", cur_value); | ||
| 650 | |||
| 651 | ret = smu_get_dpm_level_count(smu, clk_type, &count); | 688 | ret = smu_get_dpm_level_count(smu, clk_type, &count); |
| 652 | if (ret) | 689 | if (ret) |
| 653 | return size; | 690 | return size; |
| 654 | 691 | ||
| 655 | for (i = 0; i < count; i++) { | 692 | if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) { |
| 656 | ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &value); | 693 | for (i = 0; i < count; i++) { |
| 694 | ret = smu_get_dpm_freq_by_index(smu, clk_type, i, &value); | ||
| 695 | if (ret) | ||
| 696 | return size; | ||
| 697 | |||
| 698 | size += sprintf(buf + size, "%d: %uMhz %s\n", i, value, | ||
| 699 | cur_value == value ? "*" : ""); | ||
| 700 | } | ||
| 701 | } else { | ||
| 702 | ret = smu_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]); | ||
| 657 | if (ret) | 703 | if (ret) |
| 658 | return size; | 704 | return size; |
| 705 | ret = smu_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]); | ||
| 706 | if (ret) | ||
| 707 | return size; | ||
| 708 | |||
| 709 | freq_values[1] = cur_value; | ||
| 710 | mark_index = cur_value == freq_values[0] ? 0 : | ||
| 711 | cur_value == freq_values[2] ? 2 : 1; | ||
| 712 | if (mark_index != 1) | ||
| 713 | freq_values[1] = (freq_values[0] + freq_values[2]) / 2; | ||
| 714 | |||
| 715 | for (i = 0; i < 3; i++) { | ||
| 716 | size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i], | ||
| 717 | i == mark_index ? "*" : ""); | ||
| 718 | } | ||
| 659 | 719 | ||
| 660 | size += sprintf(buf + size, "%d: %uMhz %s\n", i, value, | ||
| 661 | cur_value == value ? "*" : ""); | ||
| 662 | } | 720 | } |
| 663 | break; | 721 | break; |
| 664 | default: | 722 | default: |
| @@ -866,8 +924,9 @@ static int navi10_get_gpu_power(struct smu_context *smu, uint32_t *value) · 201 unmodified lines | |||
| 866 | if (!value) | 924 | if (!value) |
| 867 | return -EINVAL; | 925 | return -EINVAL; |
| 868 | 926 | ||
| 869 | ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0, (void *)&metrics, | 927 | ret = navi10_get_metrics_table(smu, &metrics); |
| 870 | false); | 928 | if (ret) |
| 929 | return ret; | ||
| 871 | if (ret) | 930 | if (ret) |
| 872 | return ret; | 931 | return ret; |
| 873 | 932 | ||
| @@ -886,10 +945,7 @@ static int navi10_get_current_activity_percent(struct smu_context *smu, · 12 unmodified lines | |||
| 886 | if (!value) | 945 | if (!value) |
| 887 | return -EINVAL; | 946 | return -EINVAL; |
| 888 | 947 | ||
| 889 | msleep(1); | 948 | ret = navi10_get_metrics_table(smu, &metrics); |
| 890 | |||
| 891 | ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0, | ||
| 892 | (void *)&metrics, false); | ||
| 893 | if (ret) | 949 | if (ret) |
| 894 | return ret; | 950 | return ret; |
| 895 | 951 | ||
| @@ -919,22 +975,22 @@ static bool navi10_is_dpm_running(struct smu_context *smu) · 23 unmodified lines | |||
| 919 | return !!(feature_enabled & SMC_DPM_FEATURE); | 975 | return !!(feature_enabled & SMC_DPM_FEATURE); |
| 920 | } | 976 | } |
| 921 | 977 | ||
| 922 | static int navi10_get_fan_speed(struct smu_context *smu, uint16_t *value) | 978 | static int navi10_get_fan_speed_rpm(struct smu_context *smu, |
| 979 | uint32_t *speed) | ||
| 923 | { | 980 | { |
| 924 | SmuMetrics_t metrics; | 981 | SmuMetrics_t metrics; |
| 925 | int ret = 0; | 982 | int ret = 0; |
| 926 | 983 | ||
| 927 | if (!value) | 984 | if (!speed) |
| 928 | return -EINVAL; | 985 | return -EINVAL; |
| 929 | 986 | ||
| 930 | memset(&metrics, 0, sizeof(metrics)); | 987 | ret = navi10_get_metrics_table(smu, &metrics); |
| 931 | 988 | if (ret) | |
| 932 | ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0, | 989 | return ret; |
| 933 | (void *)&metrics, false); | ||
| 934 | if (ret) | 990 | if (ret) |
| 935 | return ret; | 991 | return ret; |
| 936 | 992 | ||
| 937 | *value = metrics.CurrFanSpeed; | 993 | *speed = metrics.CurrFanSpeed; |
| 938 | 994 | ||
| 939 | return ret; | 995 | return ret; |
| 940 | } | 996 | } |
| @@ -944,10 +1000,10 @@ static int navi10_get_fan_speed_percent(struct smu_context *smu, · 3 unmodified lines | |||
| 944 | { | 1000 | { |
| 945 | int ret = 0; | 1001 | int ret = 0; |
| 946 | uint32_t percent = 0; | 1002 | uint32_t percent = 0; |
| 947 | uint16_t current_rpm; | 1003 | uint32_t current_rpm; |
| 948 | PPTable_t *pptable = smu->smu_table.driver_pptable; | 1004 | PPTable_t *pptable = smu->smu_table.driver_pptable; |
| 949 | 1005 | ||
| 950 | ret = navi10_get_fan_speed(smu, ¤t_rpm); | 1006 | ret = navi10_get_fan_speed_rpm(smu, ¤t_rpm); |
| 951 | if (ret) | 1007 | if (ret) |
| 952 | return ret; | 1008 | return ret; |
| 953 | 1009 | ||
| @@ -1278,7 +1334,7 @@ static int navi10_thermal_get_temperature(struct smu_context *smu, · 324 unmodified lines | |||
| 1278 | if (!value) | 1334 | if (!value) |
| 1279 | return -EINVAL; | 1335 | return -EINVAL; |
| 1280 | 1336 | ||
| 1281 | ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0, (void *)&metrics, false); | 1337 | ret = navi10_get_metrics_table(smu, &metrics); |
| 1282 | if (ret) | 1338 | if (ret) |
| 1283 | return ret; | 1339 | return ret; |
| 1284 | 1340 | ||
| @@ -1530,6 +1586,76 @@ static int navi10_set_ppfeature_status(struct smu_context *smu, · 245 unmodified lines | |||
| 1530 | return 0; | 1586 | return 0; |
| 1531 | } | 1587 | } |
| 1532 | 1588 | ||
| 1589 | static int navi10_set_peak_clock_by_device(struct smu_context *smu) | ||
| 1590 | { | ||
| 1591 | struct amdgpu_device *adev = smu->adev; | ||
| 1592 | int ret = 0; | ||
| 1593 | uint32_t sclk_freq = 0, uclk_freq = 0; | ||
| 1594 | uint32_t uclk_level = 0; | ||
| 1595 | |||
| 1596 | switch (adev->pdev->revision) { | ||
| 1597 | case 0xf0: /* XTX */ | ||
| 1598 | case 0xc0: | ||
| 1599 | sclk_freq = NAVI10_PEAK_SCLK_XTX; | ||
| 1600 | break; | ||
| 1601 | case 0xf1: /* XT */ | ||
| 1602 | case 0xc1: | ||
| 1603 | sclk_freq = NAVI10_PEAK_SCLK_XT; | ||
| 1604 | break; | ||
| 1605 | default: /* XL */ | ||
| 1606 | sclk_freq = NAVI10_PEAK_SCLK_XL; | ||
| 1607 | break; | ||
| 1608 | } | ||
| 1609 | |||
| 1610 | ret = smu_get_dpm_level_count(smu, SMU_UCLK, &uclk_level); | ||
| 1611 | if (ret) | ||
| 1612 | return ret; | ||
| 1613 | ret = smu_get_dpm_freq_by_index(smu, SMU_UCLK, uclk_level - 1, &uclk_freq); | ||
| 1614 | if (ret) | ||
| 1615 | return ret; | ||
| 1616 | |||
| 1617 | ret = smu_set_soft_freq_range(smu, SMU_SCLK, sclk_freq, sclk_freq); | ||
| 1618 | if (ret) | ||
| 1619 | return ret; | ||
| 1620 | ret = smu_set_soft_freq_range(smu, SMU_UCLK, uclk_freq, uclk_freq); | ||
| 1621 | if (ret) | ||
| 1622 | return ret; | ||
| 1623 | |||
| 1624 | return ret; | ||
| 1625 | } | ||
| 1626 | |||
| 1627 | static int navi10_set_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level) | ||
| 1628 | { | ||
| 1629 | int ret = 0; | ||
| 1630 | |||
| 1631 | switch (level) { | ||
| 1632 | case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: | ||
| 1633 | ret = navi10_set_peak_clock_by_device(smu); | ||
| 1634 | break; | ||
| 1635 | default: | ||
| 1636 | ret = -EINVAL; | ||
| 1637 | break; | ||
| 1638 | } | ||
| 1639 | |||
| 1640 | return ret; | ||
| 1641 | } | ||
| 1642 | |||
| 1643 | static int navi10_get_thermal_temperature_range(struct smu_context *smu, | ||
| 1644 | struct smu_temperature_range *range) | ||
| 1645 | { | ||
| 1646 | struct smu_table_context *table_context = &smu->smu_table; | ||
| 1647 | struct smu_11_0_powerplay_table *powerplay_table = table_context->power_play_table; | ||
| 1648 | |||
| 1649 | if (!range || !powerplay_table) | ||
| 1650 | return -EINVAL; | ||
| 1651 | |||
| 1652 | /* The unit is temperature */ | ||
| 1653 | range->min = 0; | ||
| 1654 | range->max = powerplay_table->software_shutdown_temp; | ||
| 1655 | |||
| 1656 | return 0; | ||
| 1657 | } | ||
| 1658 | |||
| 1533 | static const struct pptable_funcs navi10_ppt_funcs = { | 1659 | static const struct pptable_funcs navi10_ppt_funcs = { |
| 1534 | .tables_init = navi10_tables_init, | 1660 | .tables_init = navi10_tables_init, |
| 1535 | .alloc_dpm_context = navi10_allocate_dpm_context, | 1661 | .alloc_dpm_context = navi10_allocate_dpm_context, |
| @@ -1557,6 +1683,7 @@ static const struct pptable_funcs navi10_ppt_funcs = { · 21 unmodified lines | |||
| 1557 | .unforce_dpm_levels = navi10_unforce_dpm_levels, | 1683 | .unforce_dpm_levels = navi10_unforce_dpm_levels, |
| 1558 | .is_dpm_running = navi10_is_dpm_running, | 1684 | .is_dpm_running = navi10_is_dpm_running, |
| 1559 | .get_fan_speed_percent = navi10_get_fan_speed_percent, | 1685 | .get_fan_speed_percent = navi10_get_fan_speed_percent, |
| 1686 | .get_fan_speed_rpm = navi10_get_fan_speed_rpm, | ||
| 1560 | .get_power_profile_mode = navi10_get_power_profile_mode, | 1687 | .get_power_profile_mode = navi10_get_power_profile_mode, |
| 1561 | .set_power_profile_mode = navi10_set_power_profile_mode, | 1688 | .set_power_profile_mode = navi10_set_power_profile_mode, |
| 1562 | .get_profiling_clk_mask = navi10_get_profiling_clk_mask, | 1689 | .get_profiling_clk_mask = navi10_get_profiling_clk_mask, |
| @@ -1565,6 +1692,8 @@ static const struct pptable_funcs navi10_ppt_funcs = { · 2 unmodified lines | |||
| 1565 | .get_uclk_dpm_states = navi10_get_uclk_dpm_states, | 1692 | .get_uclk_dpm_states = navi10_get_uclk_dpm_states, |
| 1566 | .get_ppfeature_status = navi10_get_ppfeature_status, | 1693 | .get_ppfeature_status = navi10_get_ppfeature_status, |
| 1567 | .set_ppfeature_status = navi10_set_ppfeature_status, | 1694 | .set_ppfeature_status = navi10_set_ppfeature_status, |
| 1695 | .set_performance_level = navi10_set_performance_level, | ||
| 1696 | .get_thermal_temperature_range = navi10_get_thermal_temperature_range, | ||
| 1568 | }; | 1697 | }; |
| 1569 | 1698 | ||
| 1570 | void navi10_set_ppt_funcs(struct smu_context *smu) | 1699 | void navi10_set_ppt_funcs(struct smu_context *smu) |
| @@ -23,6 +23,10 @@ · 22 unmodified lines | |||
| 23 | #ifndef __NAVI10_PPT_H__ | 23 | #ifndef __NAVI10_PPT_H__ |
| 24 | #define __NAVI10_PPT_H__ | 24 | #define __NAVI10_PPT_H__ |
| 25 | 25 | ||
| 26 | #define NAVI10_PEAK_SCLK_XTX (1830) | ||
| 27 | #define NAVI10_PEAK_SCLK_XT (1755) | ||
| 28 | #define NAVI10_PEAK_SCLK_XL (1625) | ||
| 29 | |||
| 26 | extern void navi10_set_ppt_funcs(struct smu_context *smu); | 30 | extern void navi10_set_ppt_funcs(struct smu_context *smu); |
| 27 | 31 | ||
| 28 | #endif | 32 | #endif |
| @@ -1124,10 +1124,8 @@ static int smu_v11_0_set_thermal_range(struct smu_context *smu, · 1123 unmodified lines | |||
| 1124 | struct smu_temperature_range *range) | 1124 | struct smu_temperature_range *range) |
| 1125 | { | 1125 | { |
| 1126 | struct amdgpu_device *adev = smu->adev; | 1126 | struct amdgpu_device *adev = smu->adev; |
| 1127 | int low = SMU_THERMAL_MINIMUM_ALERT_TEMP * | 1127 | int low = SMU_THERMAL_MINIMUM_ALERT_TEMP; |
| 1128 | SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; | 1128 | int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP; |
| 1129 | int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP * | ||
| 1130 | SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; | ||
| 1131 | uint32_t val; | 1129 | uint32_t val; |
| 1132 | 1130 | ||
| 1133 | if (!range) | 1131 | if (!range) |
| @@ -1138,6 +1136,9 @@ static int smu_v11_0_set_thermal_range(struct smu_context *smu, · 4 unmodified lines | |||
| 1138 | if (high > range->max) | 1136 | if (high > range->max) |
| 1139 | high = range->max; | 1137 | high = range->max; |
| 1140 | 1138 | ||
| 1139 | low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP, range->min); | ||
| 1140 | high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP, range->max); | ||
| 1141 | |||
| 1141 | if (low > high) | 1142 | if (low > high) |
| 1142 | return -EINVAL; | 1143 | return -EINVAL; |
| 1143 | 1144 | ||
| @@ -1146,8 +1147,8 @@ static int smu_v11_0_set_thermal_range(struct smu_context *smu, · 2 unmodified lines | |||
| 1146 | val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1); | 1147 | val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1); |
| 1147 | val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0); | 1148 | val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0); |
| 1148 | val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0); | 1149 | val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0); |
| 1149 | val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES)); | 1150 | val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff)); |
| 1150 | val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES)); | 1151 | val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff)); |
| 1151 | val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK); | 1152 | val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK); |
| 1152 | 1153 | ||
| 1153 | WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val); | 1154 | WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val); |
| @@ -1186,7 +1187,10 @@ static int smu_v11_0_start_thermal_control(struct smu_context *smu) · 32 unmodified lines | |||
| 1186 | 1187 | ||
| 1187 | if (!smu->pm_enabled) | 1188 | if (!smu->pm_enabled) |
| 1188 | return ret; | 1189 | return ret; |
| 1190 | |||
| 1189 | ret = smu_get_thermal_temperature_range(smu, &range); | 1191 | ret = smu_get_thermal_temperature_range(smu, &range); |
| 1192 | if (ret) | ||
| 1193 | return ret; | ||
| 1190 | 1194 | ||
| 1191 | if (smu->smu_table.thermal_controller_type) { | 1195 | if (smu->smu_table.thermal_controller_type) { |
| 1192 | ret = smu_v11_0_set_thermal_range(smu, &range); | 1196 | ret = smu_v11_0_set_thermal_range(smu, &range); |
| @@ -1202,15 +1206,17 @@ static int smu_v11_0_start_thermal_control(struct smu_context *smu) · 9 unmodified lines | |||
| 1202 | return ret; | 1206 | return ret; |
| 1203 | } | 1207 | } |
| 1204 | 1208 | ||
| 1205 | adev->pm.dpm.thermal.min_temp = range.min; | 1209 | adev->pm.dpm.thermal.min_temp = range.min * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; |
| 1206 | adev->pm.dpm.thermal.max_temp = range.max; | 1210 | adev->pm.dpm.thermal.max_temp = range.max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; |
| 1207 | adev->pm.dpm.thermal.max_edge_emergency_temp = range.edge_emergency_max; | 1211 | adev->pm.dpm.thermal.max_edge_emergency_temp = range.edge_emergency_max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; |
| 1208 | adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min; | 1212 | adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; |
| 1209 | adev->pm.dpm.thermal.max_hotspot_crit_temp = range.hotspot_crit_max; | 1213 | adev->pm.dpm.thermal.max_hotspot_crit_temp = range.hotspot_crit_max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; |
| 1210 | adev->pm.dpm.thermal.max_hotspot_emergency_temp = range.hotspot_emergency_max; | 1214 | adev->pm.dpm.thermal.max_hotspot_emergency_temp = range.hotspot_emergency_max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; |
| 1211 | adev->pm.dpm.thermal.min_mem_temp = range.mem_min; | 1215 | adev->pm.dpm.thermal.min_mem_temp = range.mem_min * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; |
| 1212 | adev->pm.dpm.thermal.max_mem_crit_temp = range.mem_crit_max; | 1216 | adev->pm.dpm.thermal.max_mem_crit_temp = range.mem_crit_max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; |
| 1213 | adev->pm.dpm.thermal.max_mem_emergency_temp = range.mem_emergency_max; | 1217 | adev->pm.dpm.thermal.max_mem_emergency_temp = range.mem_emergency_max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; |
| 1218 | adev->pm.dpm.thermal.min_temp = range.min * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; | ||
| 1219 | adev->pm.dpm.thermal.max_temp = range.max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; | ||
| 1214 | 1220 | ||
| 1215 | return ret; | 1221 | return ret; |
| 1216 | } | 1222 | } |
| @@ -1371,23 +1377,6 @@ static int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable) · 154 unmodified lines | |||
| 1371 | return ret; | 1377 | return ret; |
| 1372 | } | 1378 | } |
| 1373 | 1379 | ||
| 1374 | static int smu_v11_0_get_current_rpm(struct smu_context *smu, | ||
| 1375 | uint32_t *current_rpm) | ||
| 1376 | { | ||
| 1377 | int ret; | ||
| 1378 | |||
| 1379 | ret = smu_send_smc_msg(smu, SMU_MSG_GetCurrentRpm); | ||
| 1380 | |||
| 1381 | if (ret) { | ||
| 1382 | pr_err("Attempt to get current RPM from SMC Failed!\n"); | ||
| 1383 | return ret; | ||
| 1384 | } | ||
| 1385 | |||
| 1386 | smu_read_smc_arg(smu, current_rpm); | ||
| 1387 | |||
| 1388 | return 0; | ||
| 1389 | } | ||
| 1390 | |||
| 1391 | static uint32_t | 1380 | static uint32_t |
| 1392 | smu_v11_0_get_fan_control_mode(struct smu_context *smu) | 1381 | smu_v11_0_get_fan_control_mode(struct smu_context *smu) |
| 1393 | { | 1382 | { |
| @@ -1402,7 +1391,7 @@ smu_v11_0_smc_fan_control(struct smu_context *smu, bool start) · 8 unmodified lines | |||
| 1402 | { | 1391 | { |
| 1403 | int ret = 0; | 1392 | int ret = 0; |
| 1404 | 1393 | ||
| 1405 | if (smu_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT)) | 1394 | if (!smu_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT)) |
| 1406 | return 0; | 1395 | return 0; |
| 1407 | 1396 | ||
| 1408 | ret = smu_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, start); | 1397 | ret = smu_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, start); |
| @@ -1773,7 +1762,6 @@ static const struct smu_funcs smu_v11_0_funcs = { · 364 unmodified lines | |||
| 1773 | .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk, | 1762 | .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk, |
| 1774 | .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request, | 1763 | .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request, |
| 1775 | .set_watermarks_for_clock_ranges = smu_v11_0_set_watermarks_for_clock_ranges, | 1764 | .set_watermarks_for_clock_ranges = smu_v11_0_set_watermarks_for_clock_ranges, |
| 1776 | .get_current_rpm = smu_v11_0_get_current_rpm, | ||
| 1777 | .get_fan_control_mode = smu_v11_0_get_fan_control_mode, | 1765 | .get_fan_control_mode = smu_v11_0_get_fan_control_mode, |
| 1778 | .set_fan_control_mode = smu_v11_0_set_fan_control_mode, | 1766 | .set_fan_control_mode = smu_v11_0_set_fan_control_mode, |
| 1779 | .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent, | 1767 | .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent, |
| @@ -450,7 +450,6 @@ static int vega20_store_powerplay_table(struct smu_context *smu) · 449 unmodified lines | |||
| 450 | memcpy(table_context->driver_pptable, &powerplay_table->smcPPTable, | 450 | memcpy(table_context->driver_pptable, &powerplay_table->smcPPTable, |
| 451 | sizeof(PPTable_t)); | 451 | sizeof(PPTable_t)); |
| 452 | 452 | ||
| 453 | table_context->software_shutdown_temp = powerplay_table->usSoftwareShutdownTemp; | ||
| 454 | table_context->thermal_controller_type = powerplay_table->ucThermalControllerType; | 453 | table_context->thermal_controller_type = powerplay_table->ucThermalControllerType; |
| 455 | table_context->TDPODLimit = le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingsMax[ATOM_VEGA20_ODSETTING_POWERPERCENTAGE]); | 454 | table_context->TDPODLimit = le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingsMax[ATOM_VEGA20_ODSETTING_POWERPERCENTAGE]); |
| 456 | 455 | ||
| @@ -3015,6 +3014,23 @@ static int vega20_set_thermal_fan_table(struct smu_context *smu) · 2558 unmodified lines | |||
| 3015 | return ret; | 3014 | return ret; |
| 3016 | } | 3015 | } |
| 3017 | 3016 | ||
| 3017 | static int vega20_get_fan_speed_rpm(struct smu_context *smu, | ||
| 3018 | uint32_t *speed) | ||
| 3019 | { | ||
| 3020 | int ret; | ||
| 3021 | |||
| 3022 | ret = smu_send_smc_msg(smu, SMU_MSG_GetCurrentRpm); | ||
| 3023 | |||
| 3024 | if (ret) { | ||
| 3025 | pr_err("Attempt to get current RPM from SMC Failed!\n"); | ||
| 3026 | return ret; | ||
| 3027 | } | ||
| 3028 | |||
| 3029 | smu_read_smc_arg(smu, speed); | ||
| 3030 | |||
| 3031 | return 0; | ||
| 3032 | } | ||
| 3033 | |||
| 3018 | static int vega20_get_fan_speed_percent(struct smu_context *smu, | 3034 | static int vega20_get_fan_speed_percent(struct smu_context *smu, |
| 3019 | uint32_t *speed) | 3035 | uint32_t *speed) |
| 3020 | { | 3036 | { |
| @@ -3022,7 +3038,7 @@ static int vega20_get_fan_speed_percent(struct smu_context *smu, · 1 unmodified line | |||
| 3022 | uint32_t current_rpm = 0, percent = 0; | 3038 | uint32_t current_rpm = 0, percent = 0; |
| 3023 | PPTable_t *pptable = smu->smu_table.driver_pptable; | 3039 | PPTable_t *pptable = smu->smu_table.driver_pptable; |
| 3024 | 3040 | ||
| 3025 | ret = smu_get_current_rpm(smu, ¤t_rpm); | 3041 | ret = vega20_get_fan_speed_rpm(smu, ¤t_rpm); |
| 3026 | if (ret) | 3042 | if (ret) |
| 3027 | return ret; | 3043 | return ret; |
| 3028 | 3044 | ||
| @@ -3217,35 +3233,24 @@ static int vega20_set_watermarks_table(struct smu_context *smu, · 188 unmodified lines | |||
| 3217 | return 0; | 3233 | return 0; |
| 3218 | } | 3234 | } |
| 3219 | 3235 | ||
| 3220 | static const struct smu_temperature_range vega20_thermal_policy[] = | ||
| 3221 | { | ||
| 3222 | {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000}, | ||
| 3223 | { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000}, | ||
| 3224 | }; | ||
| 3225 | |||
| 3226 | static int vega20_get_thermal_temperature_range(struct smu_context *smu, | 3236 | static int vega20_get_thermal_temperature_range(struct smu_context *smu, |
| 3227 | struct smu_temperature_range *range) | 3237 | struct smu_temperature_range *range) |
| 3228 | { | 3238 | { |
| 3229 | 3239 | struct smu_table_context *table_context = &smu->smu_table; | |
| 3240 | ATOM_Vega20_POWERPLAYTABLE *powerplay_table = table_context->power_play_table; | ||
| 3230 | PPTable_t *pptable = smu->smu_table.driver_pptable; | 3241 | PPTable_t *pptable = smu->smu_table.driver_pptable; |
| 3231 | 3242 | ||
| 3232 | if (!range) | 3243 | if (!range || !powerplay_table) |
| 3233 | return -EINVAL; | 3244 | return -EINVAL; |
| 3234 | 3245 | ||
| 3235 | memcpy(range, &vega20_thermal_policy[0], sizeof(struct smu_temperature_range)); | 3246 | /* The unit is temperature */ |
| 3236 | 3247 | range->min = 0; | |
| 3237 | range->max = pptable->TedgeLimit * | 3248 | range->max = powerplay_table->usSoftwareShutdownTemp; |
| 3238 | SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; | 3249 | range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE); |
| 3239 | range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) * | 3250 | range->hotspot_crit_max = pptable->ThotspotLimit; |
| 3240 | SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; | 3251 | range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT); |
| 3241 | range->hotspot_crit_max = pptable->ThotspotLimit * | 3252 | range->mem_crit_max = pptable->ThbmLimit; |
| 3242 | SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; | 3253 | range->mem_emergency_max = (pptable->ThbmLimit + CTF_OFFSET_HBM); |
| 3243 | range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) * | ||
| 3244 | SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; | ||
| 3245 | range->mem_crit_max = pptable->ThbmLimit * | ||
| 3246 | SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; | ||
| 3247 | range->mem_emergency_max = (pptable->ThbmLimit + CTF_OFFSET_HBM)* | ||
| 3248 | SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; | ||
| 3249 | 3254 | ||
| 3250 | 3255 | ||
| 3251 | return 0; | 3256 | return 0; |
| @@ -3293,6 +3298,7 @@ static const struct pptable_funcs vega20_ppt_funcs = { · 41 unmodified lines | |||
| 3293 | .is_dpm_running = vega20_is_dpm_running, | 3298 | .is_dpm_running = vega20_is_dpm_running, |
| 3294 | .set_thermal_fan_table = vega20_set_thermal_fan_table, | 3299 | .set_thermal_fan_table = vega20_set_thermal_fan_table, |
| 3295 | .get_fan_speed_percent = vega20_get_fan_speed_percent, | 3300 | .get_fan_speed_percent = vega20_get_fan_speed_percent, |
| 3301 | .get_fan_speed_rpm = vega20_get_fan_speed_rpm, | ||
| 3296 | .set_watermarks_table = vega20_set_watermarks_table, | 3302 | .set_watermarks_table = vega20_set_watermarks_table, |
| 3297 | .get_thermal_temperature_range = vega20_get_thermal_temperature_range | 3303 | .get_thermal_temperature_range = vega20_get_thermal_temperature_range |
| 3298 | }; | 3304 | }; |
| @@ -131,8 +131,8 @@ static int ast_detect_chip(struct drm_device *dev, bool *need_post) · 130 unmodified lines | |||
| 131 | 131 | ||
| 132 | 132 | ||
| 133 | /* Enable extended register access */ | 133 | /* Enable extended register access */ |
| 134 | ast_enable_mmio(dev); | ||
| 135 | ast_open_key(ast); | 134 | ast_open_key(ast); |
| 135 | ast_enable_mmio(dev); | ||
| 136 | 136 | ||
| 137 | /* Find out whether P2A works or whether to use device-tree */ | 137 | /* Find out whether P2A works or whether to use device-tree */ |
| 138 | ast_detect_config_mode(dev, &scu_rev); | 138 | ast_detect_config_mode(dev, &scu_rev); |
| @@ -576,6 +576,9 @@ void ast_driver_unload(struct drm_device *dev) · 437 unmodified lines | |||
| 576 | { | 576 | { |
| 577 | struct ast_private *ast = dev->dev_private; | 577 | struct ast_private *ast = dev->dev_private; |
| 578 | 578 | ||
| 579 | /* enable standard VGA decode */ | ||
| 580 | ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x04); | ||
| 581 | |||
| 579 | ast_release_firmware(dev); | 582 | ast_release_firmware(dev); |
| 580 | kfree(ast->dp501_fw_addr); | 583 | kfree(ast->dp501_fw_addr); |
| 581 | ast_mode_fini(dev); | 584 | ast_mode_fini(dev); |
| @@ -604,7 +604,7 @@ static int ast_crtc_mode_set(struct drm_crtc *crtc, · 603 unmodified lines | |||
| 604 | return -EINVAL; | 604 | return -EINVAL; |
| 605 | ast_open_key(ast); | 605 | ast_open_key(ast); |
| 606 | 606 | ||
| 607 | ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x04); | 607 | ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x06); |
| 608 | 608 | ||
| 609 | ast_set_std_reg(crtc, adjusted_mode, &vbios_mode); | 609 | ast_set_std_reg(crtc, adjusted_mode, &vbios_mode); |
| 610 | ast_set_crtc_reg(crtc, adjusted_mode, &vbios_mode); | 610 | ast_set_crtc_reg(crtc, adjusted_mode, &vbios_mode); |
| @@ -46,7 +46,7 @@ void ast_enable_mmio(struct drm_device *dev) · 45 unmodified lines | |||
| 46 | { | 46 | { |
| 47 | struct ast_private *ast = dev->dev_private; | 47 | struct ast_private *ast = dev->dev_private; |
| 48 | 48 | ||
| 49 | ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x04); | 49 | ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x06); |
| 50 | } | 50 | } |
| 51 | 51 | ||
| 52 | 52 | ||
| @@ -191,6 +191,7 @@ int bochs_kms_init(struct bochs_device *bochs) · 190 unmodified lines | |||
| 191 | bochs->dev->mode_config.fb_base = bochs->fb_base; | 191 | bochs->dev->mode_config.fb_base = bochs->fb_base; |
| 192 | bochs->dev->mode_config.preferred_depth = 24; | 192 | bochs->dev->mode_config.preferred_depth = 24; |
| 193 | bochs->dev->mode_config.prefer_shadow = 0; | 193 | bochs->dev->mode_config.prefer_shadow = 0; |
| 194 | bochs->dev->mode_config.prefer_shadow_fbdev = 1; | ||
| 194 | bochs->dev->mode_config.quirk_addfb_prefer_host_byte_order = true; | 195 | bochs->dev->mode_config.quirk_addfb_prefer_host_byte_order = true; |
| 195 | 196 | ||
| 196 | bochs->dev->mode_config.funcs = &bochs_mode_funcs; | 197 | bochs->dev->mode_config.funcs = &bochs_mode_funcs; |
| @@ -48,6 +48,7 @@ config DRM_DUMB_VGA_DAC · 47 unmodified lines | |||
| 48 | config DRM_LVDS_ENCODER | 48 | config DRM_LVDS_ENCODER |
| 49 | tristate "Transparent parallel to LVDS encoder support" | 49 | tristate "Transparent parallel to LVDS encoder support" |
| 50 | depends on OF | 50 | depends on OF |
| 51 | select DRM_KMS_HELPER | ||
| 51 | select DRM_PANEL_BRIDGE | 52 | select DRM_PANEL_BRIDGE |
| 52 | help | 53 | help |
| 53 | Support for transparent parallel to LVDS encoders that don't require | 54 | Support for transparent parallel to LVDS encoders that don't require |
| @@ -116,9 +117,10 @@ config DRM_THINE_THC63LVD1024 · 62 unmodified lines | |||
| 116 | 117 | ||
| 117 | config DRM_TOSHIBA_TC358764 | 118 | config DRM_TOSHIBA_TC358764 |
| 118 | tristate "TC358764 DSI/LVDS bridge" | 119 | tristate "TC358764 DSI/LVDS bridge" |
| 119 | depends on DRM && DRM_PANEL | ||
| 120 | depends on OF | 120 | depends on OF |
| 121 | select DRM_MIPI_DSI | 121 | select DRM_MIPI_DSI |
| 122 | select DRM_KMS_HELPER | ||
| 123 | select DRM_PANEL | ||
| 122 | help | 124 | help |
| 123 | Toshiba TC358764 DSI/LVDS bridge driver. | 125 | Toshiba TC358764 DSI/LVDS bridge driver. |
| 124 | 126 | ||
| @@ -254,7 +254,6 @@ drm_client_buffer_create(struct drm_client_dev *client, u32 width, u32 height, u · 253 unmodified lines | |||
| 254 | struct drm_device *dev = client->dev; | 254 | struct drm_device *dev = client->dev; |
| 255 | struct drm_client_buffer *buffer; | 255 | struct drm_client_buffer *buffer; |
| 256 | struct drm_gem_object *obj; | 256 | struct drm_gem_object *obj; |
| 257 | void *vaddr; | ||
| 258 | int ret; | 257 | int ret; |
| 259 | 258 | ||
| 260 | buffer = kzalloc(sizeof(*buffer), GFP_KERNEL); | 259 | buffer = kzalloc(sizeof(*buffer), GFP_KERNEL); |
| @@ -281,6 +280,36 @@ drm_client_buffer_create(struct drm_client_dev *client, u32 width, u32 height, u · 20 unmodified lines | |||
| 281 | 280 | ||
| 282 | buffer->gem = obj; | 281 | buffer->gem = obj; |
| 283 | 282 | ||
| 283 | return buffer; | ||
| 284 | |||
| 285 | err_delete: | ||
| 286 | drm_client_buffer_delete(buffer); | ||
| 287 | |||
| 288 | return ERR_PTR(ret); | ||
| 289 | } | ||
| 290 | |||
| 291 | /** | ||
| 292 | * drm_client_buffer_vmap - Map DRM client buffer into address space | ||
| 293 | * @buffer: DRM client buffer | ||
| 294 | * | ||
| 295 | * This function maps a client buffer into kernel address space. If the | ||
| 296 | * buffer is already mapped, it returns the mapping's address. | ||
| 297 | * | ||
| 298 | * Client buffer mappings are not ref'counted. Each call to | ||
| 299 | * drm_client_buffer_vmap() should be followed by a call to | ||
| 300 | * drm_client_buffer_vunmap(); or the client buffer should be mapped | ||
| 301 | * throughout its lifetime. | ||
| 302 | * | ||
| 303 | * Returns: | ||
| 304 | * The mapped memory's address | ||
| 305 | */ | ||
| 306 | void *drm_client_buffer_vmap(struct drm_client_buffer *buffer) | ||
| 307 | { | ||
| 308 | void *vaddr; | ||
| 309 | |||
| 310 | if (buffer->vaddr) | ||
| 311 | return buffer->vaddr; | ||
| 312 | |||
| 284 | /* | 313 | /* |
| 285 | * FIXME: The dependency on GEM here isn't required, we could | 314 | * FIXME: The dependency on GEM here isn't required, we could |
| 286 | * convert the driver handle to a dma-buf instead and use the | 315 | * convert the driver handle to a dma-buf instead and use the |
| @@ -289,21 +318,30 @@ drm_client_buffer_create(struct drm_client_dev *client, u32 width, u32 height, u · 2 unmodified lines | |||
| 289 | * fd_install step out of the driver backend hooks, to make that | 318 | * fd_install step out of the driver backend hooks, to make that |
| 290 | * final step optional for internal users. | 319 | * final step optional for internal users. |
| 291 | */ | 320 | */ |
| 292 | vaddr = drm_gem_vmap(obj); | 321 | vaddr = drm_gem_vmap(buffer->gem); |
| 293 | if (IS_ERR(vaddr)) { | 322 | if (IS_ERR(vaddr)) |
| 294 | ret = PTR_ERR(vaddr); | 323 | return vaddr; |
| 295 | goto err_delete; | ||
| 296 | } | ||
| 297 | 324 | ||
| 298 | buffer->vaddr = vaddr; | 325 | buffer->vaddr = vaddr; |
| 299 | 326 | ||
| 300 | return buffer; | 327 | return vaddr; |
| 301 | 328 | } | |
| 302 | err_delete: | 329 | EXPORT_SYMBOL(drm_client_buffer_vmap); |
| 303 | drm_client_buffer_delete(buffer); | ||
| 304 | 330 | ||
| 305 | return ERR_PTR(ret); | 331 | /** |
| 332 | * drm_client_buffer_vunmap - Unmap DRM client buffer | ||
| 333 | * @buffer: DRM client buffer | ||
| 334 | * | ||
| 335 | * This function removes a client buffer's memory mapping. Calling this | ||
| 336 | * function is only required by clients that manage their buffer mappings | ||
| 337 | * by themselves. | ||
| 338 | */ | ||
| 339 | void drm_client_buffer_vunmap(struct drm_client_buffer *buffer) | ||
| 340 | { | ||
| 341 | drm_gem_vunmap(buffer->gem, buffer->vaddr); | ||
| 342 | buffer->vaddr = NULL; | ||
| 306 | } | 343 | } |
| 344 | EXPORT_SYMBOL(drm_client_buffer_vunmap); | ||
| 307 | 345 | ||
| 308 | static void drm_client_buffer_rmfb(struct drm_client_buffer *buffer) | 346 | static void drm_client_buffer_rmfb(struct drm_client_buffer *buffer) |
| 309 | { | 347 | { |
| @@ -859,7 +859,7 @@ bool drm_client_rotation(struct drm_mode_set *modeset, unsigned int *rotation) · 858 unmodified lines | |||
| 859 | * simple XOR between the two handle the addition nicely. | 859 | * simple XOR between the two handle the addition nicely. |
| 860 | */ | 860 | */ |
| 861 | cmdline = &connector->cmdline_mode; | 861 | cmdline = &connector->cmdline_mode; |
| 862 | if (cmdline->specified) { | 862 | if (cmdline->specified && cmdline->rotation_reflection) { |
| 863 | unsigned int cmdline_rest, panel_rest; | 863 | unsigned int cmdline_rest, panel_rest; |
| 864 | unsigned int cmdline_rot, panel_rot; | 864 | unsigned int cmdline_rot, panel_rot; |
| 865 | unsigned int sum_rot, sum_rest; | 865 | unsigned int sum_rot, sum_rest; |
| @@ -403,6 +403,7 @@ static void drm_fb_helper_dirty_work(struct work_struct *work) · 402 unmodified lines | |||
| 403 | struct drm_clip_rect *clip = &helper->dirty_clip; | 403 | struct drm_clip_rect *clip = &helper->dirty_clip; |
| 404 | struct drm_clip_rect clip_copy; | 404 | struct drm_clip_rect clip_copy; |
| 405 | unsigned long flags; | 405 | unsigned long flags; |
| 406 | void *vaddr; | ||
| 406 | 407 | ||
| 407 | spin_lock_irqsave(&helper->dirty_lock, flags); | 408 | spin_lock_irqsave(&helper->dirty_lock, flags); |
| 408 | clip_copy = *clip; | 409 | clip_copy = *clip; |
| @@ -412,10 +413,20 @@ static void drm_fb_helper_dirty_work(struct work_struct *work) · 3 unmodified lines | |||
| 412 | 413 | ||
| 413 | /* call dirty callback only when it has been really touched */ | 414 | /* call dirty callback only when it has been really touched */ |
| 414 | if (clip_copy.x1 < clip_copy.x2 && clip_copy.y1 < clip_copy.y2) { | 415 | if (clip_copy.x1 < clip_copy.x2 && clip_copy.y1 < clip_copy.y2) { |
| 416 | |||
| 415 | /* Generic fbdev uses a shadow buffer */ | 417 | /* Generic fbdev uses a shadow buffer */ |
| 416 | if (helper->buffer) | 418 | if (helper->buffer) { |
| 419 | vaddr = drm_client_buffer_vmap(helper->buffer); | ||
| 420 | if (IS_ERR(vaddr)) | ||
| 421 | return; | ||
| 417 | drm_fb_helper_dirty_blit_real(helper, &clip_copy); | 422 | drm_fb_helper_dirty_blit_real(helper, &clip_copy); |
| 418 | helper->fb->funcs->dirty(helper->fb, NULL, 0, 0, &clip_copy, 1); | 423 | } |
| 424 | if (helper->fb->funcs->dirty) | ||
| 425 | helper->fb->funcs->dirty(helper->fb, NULL, 0, 0, | ||
| 426 | &clip_copy, 1); | ||
| 427 | |||
| 428 | if (helper->buffer) | ||
| 429 | drm_client_buffer_vunmap(helper->buffer); | ||
| 419 | } | 430 | } |
| 420 | } | 431 | } |
| 421 | 432 | ||
| @@ -604,6 +615,16 @@ void drm_fb_helper_unlink_fbi(struct drm_fb_helper *fb_helper) · 182 unmodified lines | |||
| 604 | } | 615 | } |
| 605 | EXPORT_SYMBOL(drm_fb_helper_unlink_fbi); | 616 | EXPORT_SYMBOL(drm_fb_helper_unlink_fbi); |
| 606 | 617 | ||
| 618 | static bool drm_fbdev_use_shadow_fb(struct drm_fb_helper *fb_helper) | ||
| 619 | { | ||
| 620 | struct drm_device *dev = fb_helper->dev; | ||
| 621 | struct drm_framebuffer *fb = fb_helper->fb; | ||
| 622 | |||
| 623 | return dev->mode_config.prefer_shadow_fbdev || | ||
| 624 | dev->mode_config.prefer_shadow || | ||
| 625 | fb->funcs->dirty; | ||
| 626 | } | ||
| 627 | |||
| 607 | static void drm_fb_helper_dirty(struct fb_info *info, u32 x, u32 y, | 628 | static void drm_fb_helper_dirty(struct fb_info *info, u32 x, u32 y, |
| 608 | u32 width, u32 height) | 629 | u32 width, u32 height) |
| 609 | { | 630 | { |
| @@ -611,7 +632,7 @@ static void drm_fb_helper_dirty(struct fb_info *info, u32 x, u32 y, · 1 unmodified line | |||
| 611 | struct drm_clip_rect *clip = &helper->dirty_clip; | 632 | struct drm_clip_rect *clip = &helper->dirty_clip; |
| 612 | unsigned long flags; | 633 | unsigned long flags; |
| 613 | 634 | ||
| 614 | if (!helper->fb->funcs->dirty) | 635 | if (!drm_fbdev_use_shadow_fb(helper)) |
| 615 | return; | 636 | return; |
| 616 | 637 | ||
| 617 | spin_lock_irqsave(&helper->dirty_lock, flags); | 638 | spin_lock_irqsave(&helper->dirty_lock, flags); |
| @@ -2178,6 +2199,7 @@ int drm_fb_helper_generic_probe(struct drm_fb_helper *fb_helper, · 1560 unmodified lines | |||
| 2178 | struct drm_framebuffer *fb; | 2199 | struct drm_framebuffer *fb; |
| 2179 | struct fb_info *fbi; | 2200 | struct fb_info *fbi; |
| 2180 | u32 format; | 2201 | u32 format; |
| 2202 | void *vaddr; | ||
| 2181 | 2203 | ||
| 2182 | DRM_DEBUG_KMS("surface width(%d), height(%d) and bpp(%d)\n", | 2204 | DRM_DEBUG_KMS("surface width(%d), height(%d) and bpp(%d)\n", |
| 2183 | sizes->surface_width, sizes->surface_height, | 2205 | sizes->surface_width, sizes->surface_height, |
| @@ -2200,16 +2222,10 @@ int drm_fb_helper_generic_probe(struct drm_fb_helper *fb_helper, · 16 unmodified lines | |||
| 2200 | fbi->fbops = &drm_fbdev_fb_ops; | 2222 | fbi->fbops = &drm_fbdev_fb_ops; |
| 2201 | fbi->screen_size = fb->height * fb->pitches[0]; | 2223 | fbi->screen_size = fb->height * fb->pitches[0]; |
| 2202 | fbi->fix.smem_len = fbi->screen_size; | 2224 | fbi->fix.smem_len = fbi->screen_size; |
| 2203 | fbi->screen_buffer = buffer->vaddr; | 2225 | |
| 2204 | /* Shamelessly leak the physical address to user-space */ | ||
| 2205 | #if IS_ENABLED(CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM) | ||
| 2206 | if (drm_leak_fbdev_smem && fbi->fix.smem_start == 0) | ||
| 2207 | fbi->fix.smem_start = | ||
| 2208 | page_to_phys(virt_to_page(fbi->screen_buffer)); | ||
| 2209 | #endif | ||
| 2210 | drm_fb_helper_fill_info(fbi, fb_helper, sizes); | 2226 | drm_fb_helper_fill_info(fbi, fb_helper, sizes); |
| 2211 | 2227 | ||
| 2212 | if (fb->funcs->dirty) { | 2228 | if (drm_fbdev_use_shadow_fb(fb_helper)) { |
| 2213 | struct fb_ops *fbops; | 2229 | struct fb_ops *fbops; |
| 2214 | void *shadow; | 2230 | void *shadow; |
| 2215 | 2231 | ||
| @@ -2231,6 +2247,19 @@ int drm_fb_helper_generic_probe(struct drm_fb_helper *fb_helper, · 15 unmodified lines | |||
| 2231 | fbi->fbdefio = &drm_fbdev_defio; | 2247 | fbi->fbdefio = &drm_fbdev_defio; |
| 2232 | 2248 | ||
| 2233 | fb_deferred_io_init(fbi); | 2249 | fb_deferred_io_init(fbi); |
| 2250 | } else { | ||
| 2251 | /* buffer is mapped for HW framebuffer */ | ||
| 2252 | vaddr = drm_client_buffer_vmap(fb_helper->buffer); | ||
| 2253 | if (IS_ERR(vaddr)) | ||
| 2254 | return PTR_ERR(vaddr); | ||
| 2255 | |||
| 2256 | fbi->screen_buffer = vaddr; | ||
| 2257 | /* Shamelessly leak the physical address to user-space */ | ||
| 2258 | #if IS_ENABLED(CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM) | ||
| 2259 | if (drm_leak_fbdev_smem && fbi->fix.smem_start == 0) | ||
| 2260 | fbi->fix.smem_start = | ||
| 2261 | page_to_phys(virt_to_page(fbi->screen_buffer)); | ||
| 2262 | #endif | ||
| 2234 | } | 2263 | } |
| 2235 | 2264 | ||
| 2236 | return 0; | 2265 | return 0; |
| @@ -835,7 +835,7 @@ static int atomic_remove_fb(struct drm_framebuffer *fb) · 834 unmodified lines | |||
| 835 | struct drm_device *dev = fb->dev; | 835 | struct drm_device *dev = fb->dev; |
| 836 | struct drm_atomic_state *state; | 836 | struct drm_atomic_state *state; |
| 837 | struct drm_plane *plane; | 837 | struct drm_plane *plane; |
| 838 | struct drm_connector *conn; | 838 | struct drm_connector *conn __maybe_unused; |
| 839 | struct drm_connector_state *conn_state; | 839 | struct drm_connector_state *conn_state; |
| 840 | int i, ret; | 840 | int i, ret; |
| 841 | unsigned plane_mask; | 841 | unsigned plane_mask; |
| @@ -1686,7 +1686,7 @@ static int drm_mode_parse_cmdline_options(char *str, size_t len, · 1685 unmodified lines | |||
| 1686 | * | 1686 | * |
| 1687 | * Additionals options can be provided following the mode, using a comma to | 1687 | * Additionals options can be provided following the mode, using a comma to |
| 1688 | * separate each option. Valid options can be found in | 1688 | * separate each option. Valid options can be found in |
| 1689 | * Documentation/fb/modedb.txt. | 1689 | * Documentation/fb/modedb.rst. |
| 1690 | * | 1690 | * |
| 1691 | * The intermediate drm_cmdline_mode structure is required to store additional | 1691 | * The intermediate drm_cmdline_mode structure is required to store additional |
| 1692 | * options from the command line modline like the force-enable/disable flag. | 1692 | * options from the command line modline like the force-enable/disable flag. |
| @@ -1770,7 +1770,9 @@ bool drm_mode_parse_command_line_for_connector(const char *mode_option, · 77 unmodified lines | |||
| 1770 | } | 1770 | } |
| 1771 | 1771 | ||
| 1772 | if (named_mode) { | 1772 | if (named_mode) { |
| 1773 | strncpy(mode->name, name, mode_end); | 1773 | if (mode_end + 1 > DRM_DISPLAY_MODE_LEN) |
| 1774 | return false; | ||
| 1775 | strscpy(mode->name, name, mode_end + 1); | ||
| 1774 | } else { | 1776 | } else { |
| 1775 | ret = drm_mode_parse_cmdline_res_mode(name, mode_end, | 1777 | ret = drm_mode_parse_cmdline_res_mode(name, mode_end, |
| 1776 | parse_extras, | 1778 | parse_extras, |
| @@ -2,6 +2,7 @@ · 1 unmodified line | |||
| 2 | config DRM_EXYNOS | 2 | config DRM_EXYNOS |
| 3 | tristate "DRM Support for Samsung SoC EXYNOS Series" | 3 | tristate "DRM Support for Samsung SoC EXYNOS Series" |
| 4 | depends on OF && DRM && (ARCH_S3C64XX || ARCH_S5PV210 || ARCH_EXYNOS || ARCH_MULTIPLATFORM || COMPILE_TEST) | 4 | depends on OF && DRM && (ARCH_S3C64XX || ARCH_S5PV210 || ARCH_EXYNOS || ARCH_MULTIPLATFORM || COMPILE_TEST) |
| 5 | depends on MMU | ||
| 5 | select DRM_KMS_HELPER | 6 | select DRM_KMS_HELPER |
| 6 | select VIDEOMODE_HELPERS | 7 | select VIDEOMODE_HELPERS |
| 7 | select SND_SOC_HDMI_CODEC if SND_SOC | 8 | select SND_SOC_HDMI_CODEC if SND_SOC |
| @@ -44,7 +44,7 @@ static unsigned int fimc_mask = 0xc; · 43 unmodified lines | |||
| 44 | module_param_named(fimc_devs, fimc_mask, uint, 0644); | 44 | module_param_named(fimc_devs, fimc_mask, uint, 0644); |
| 45 | MODULE_PARM_DESC(fimc_devs, "Alias mask for assigning FIMC devices to Exynos DRM"); | 45 | MODULE_PARM_DESC(fimc_devs, "Alias mask for assigning FIMC devices to Exynos DRM"); |
| 46 | 46 | ||
| 47 | #define get_fimc_context(dev) platform_get_drvdata(to_platform_device(dev)) | 47 | #define get_fimc_context(dev) dev_get_drvdata(dev) |
| 48 | 48 | ||
| 49 | enum { | 49 | enum { |
| 50 | FIMC_CLK_LCLK, | 50 | FIMC_CLK_LCLK, |
| @@ -267,7 +267,7 @@ static inline void g2d_hw_reset(struct g2d_data *g2d) · 266 unmodified lines | |||
| 267 | static int g2d_init_cmdlist(struct g2d_data *g2d) | 267 | static int g2d_init_cmdlist(struct g2d_data *g2d) |
| 268 | { | 268 | { |
| 269 | struct device *dev = g2d->dev; | 269 | struct device *dev = g2d->dev; |
| 270 | struct g2d_cmdlist_node *node = g2d->cmdlist_node; | 270 | struct g2d_cmdlist_node *node; |
| 271 | int nr; | 271 | int nr; |
| 272 | int ret; | 272 | int ret; |
| 273 | struct g2d_buf_info *buf_info; | 273 | struct g2d_buf_info *buf_info; |
| @@ -58,7 +58,7 @@ · 57 unmodified lines | |||
| 58 | #define GSC_COEF_DEPTH 3 | 58 | #define GSC_COEF_DEPTH 3 |
| 59 | #define GSC_AUTOSUSPEND_DELAY 2000 | 59 | #define GSC_AUTOSUSPEND_DELAY 2000 |
| 60 | 60 | ||
| 61 | #define get_gsc_context(dev) platform_get_drvdata(to_platform_device(dev)) | 61 | #define get_gsc_context(dev) dev_get_drvdata(dev) |
| 62 | #define gsc_read(offset) readl(ctx->regs + (offset)) | 62 | #define gsc_read(offset) readl(ctx->regs + (offset)) |
| 63 | #define gsc_write(cfg, offset) writel(cfg, ctx->regs + (offset)) | 63 | #define gsc_write(cfg, offset) writel(cfg, ctx->regs + (offset)) |
| 64 | 64 | ||
| @@ -94,12 +94,12 @@ static inline int scaler_reset(struct scaler_context *scaler) · 93 unmodified lines | |||
| 94 | scaler_write(SCALER_CFG_SOFT_RESET, SCALER_CFG); | 94 | scaler_write(SCALER_CFG_SOFT_RESET, SCALER_CFG); |
| 95 | do { | 95 | do { |
| 96 | cpu_relax(); | 96 | cpu_relax(); |
| 97 | } while (retry > 1 && | 97 | } while (--retry > 1 && |
| 98 | scaler_read(SCALER_CFG) & SCALER_CFG_SOFT_RESET); | 98 | scaler_read(SCALER_CFG) & SCALER_CFG_SOFT_RESET); |
| 99 | do { | 99 | do { |
| 100 | cpu_relax(); | 100 | cpu_relax(); |
| 101 | scaler_write(1, SCALER_INT_EN); | 101 | scaler_write(1, SCALER_INT_EN); |
| 102 | } while (retry > 0 && scaler_read(SCALER_INT_EN) != 1); | 102 | } while (--retry > 0 && scaler_read(SCALER_INT_EN) != 1); |
| 103 | 103 | ||
| 104 | return retry ? 0 : -EIO; | 104 | return retry ? 0 : -EIO; |
| 105 | } | 105 | } |
| @@ -16,7 +16,6 @@ subdir-ccflags-y := -Wall -Wextra · 15 unmodified lines | |||
| 16 | subdir-ccflags-y += $(call cc-disable-warning, unused-parameter) | 16 | subdir-ccflags-y += $(call cc-disable-warning, unused-parameter) |
| 17 | subdir-ccflags-y += $(call cc-disable-warning, type-limits) | 17 | subdir-ccflags-y += $(call cc-disable-warning, type-limits) |
| 18 | subdir-ccflags-y += $(call cc-disable-warning, missing-field-initializers) | 18 | subdir-ccflags-y += $(call cc-disable-warning, missing-field-initializers) |
| 19 | subdir-ccflags-y += $(call cc-disable-warning, implicit-fallthrough) | ||
| 20 | subdir-ccflags-y += $(call cc-disable-warning, unused-but-set-variable) | 19 | subdir-ccflags-y += $(call cc-disable-warning, unused-but-set-variable) |
| 21 | # clang warnings | 20 | # clang warnings |
| 22 | subdir-ccflags-y += $(call cc-disable-warning, sign-compare) | 21 | subdir-ccflags-y += $(call cc-disable-warning, sign-compare) |
| @@ -765,7 +765,7 @@ parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb) · 764 unmodified lines | |||
| 765 | } | 765 | } |
| 766 | 766 | ||
| 767 | if (bdb->version >= 226) { | 767 | if (bdb->version >= 226) { |
| 768 | u32 wakeup_time = psr_table->psr2_tp2_tp3_wakeup_time; | 768 | u32 wakeup_time = psr->psr2_tp2_tp3_wakeup_time; |
| 769 | 769 | ||
| 770 | wakeup_time = (wakeup_time >> (2 * panel_type)) & 0x3; | 770 | wakeup_time = (wakeup_time >> (2 * panel_type)) & 0x3; |
| 771 | switch (wakeup_time) { | 771 | switch (wakeup_time) { |
| @@ -178,6 +178,8 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv) · 177 unmodified lines | |||
| 178 | clpchgroup = (sa->deburst * deinterleave / num_channels) << i; | 178 | clpchgroup = (sa->deburst * deinterleave / num_channels) << i; |
| 179 | bi->num_planes = (ipqdepth - clpchgroup) / clpchgroup + 1; | 179 | bi->num_planes = (ipqdepth - clpchgroup) / clpchgroup + 1; |
| 180 | 180 | ||
| 181 | bi->num_qgv_points = qi.num_points; | ||
| 182 | |||
| 181 | for (j = 0; j < qi.num_points; j++) { | 183 | for (j = 0; j < qi.num_points; j++) { |
| 182 | const struct intel_qgv_point *sp = &qi.points[j]; | 184 | const struct intel_qgv_point *sp = &qi.points[j]; |
| 183 | int ct, bw; | 185 | int ct, bw; |
| @@ -195,7 +197,7 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv) · 11 unmodified lines | |||
| 195 | bi->deratedbw[j] = min(maxdebw, | 197 | bi->deratedbw[j] = min(maxdebw, |
| 196 | bw * 9 / 10); /* 90% */ | 198 | bw * 9 / 10); /* 90% */ |
| 197 | 199 | ||
| 198 | DRM_DEBUG_KMS("BW%d / QGV %d: num_planes=%d deratedbw=%d\n", | 200 | DRM_DEBUG_KMS("BW%d / QGV %d: num_planes=%d deratedbw=%u\n", |
| 199 | i, j, bi->num_planes, bi->deratedbw[j]); | 201 | i, j, bi->num_planes, bi->deratedbw[j]); |
| 200 | } | 202 | } |
| 201 | 203 | ||
| @@ -211,14 +213,17 @@ static unsigned int icl_max_bw(struct drm_i915_private *dev_priv, · 9 unmodified lines | |||
| 211 | { | 213 | { |
| 212 | int i; | 214 | int i; |
| 213 | 215 | ||
| 214 | /* Did we initialize the bw limits successfully? */ | ||
| 215 | if (dev_priv->max_bw[0].num_planes == 0) | ||
| 216 | return UINT_MAX; | ||
| 217 | |||
| 218 | for (i = 0; i < ARRAY_SIZE(dev_priv->max_bw); i++) { | 216 | for (i = 0; i < ARRAY_SIZE(dev_priv->max_bw); i++) { |
| 219 | const struct intel_bw_info *bi = | 217 | const struct intel_bw_info *bi = |
| 220 | &dev_priv->max_bw[i]; | 218 | &dev_priv->max_bw[i]; |
| 221 | 219 | ||
| 220 | /* | ||
| 221 | * Pcode will not expose all QGV points when | ||
| 222 | * SAGV is forced to off/min/med/max. | ||
| 223 | */ | ||
| 224 | if (qgv_point >= bi->num_qgv_points) | ||
| 225 | return UINT_MAX; | ||
| 226 | |||
| 222 | if (num_planes >= bi->num_planes) | 227 | if (num_planes >= bi->num_planes) |
| 223 | return bi->deratedbw[qgv_point]; | 228 | return bi->deratedbw[qgv_point]; |
| 224 | } | 229 | } |
| @@ -2239,6 +2239,17 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) · 2238 unmodified lines | |||
| 2239 | if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9) | 2239 | if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9) |
| 2240 | min_cdclk = max(2 * 96000, min_cdclk); | 2240 | min_cdclk = max(2 * 96000, min_cdclk); |
| 2241 | 2241 | ||
| 2242 | /* | ||
| 2243 | * "For DP audio configuration, cdclk frequency shall be set to | ||
| 2244 | * meet the following requirements: | ||
| 2245 | * DP Link Frequency(MHz) | Cdclk frequency(MHz) | ||
| 2246 | * 270 | 320 or higher | ||
| 2247 | * 162 | 200 or higher" | ||
| 2248 | */ | ||
| 2249 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && | ||
| 2250 | intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio) | ||
| 2251 | min_cdclk = max(crtc_state->port_clock, min_cdclk); | ||
| 2252 | |||
| 2242 | /* | 2253 | /* |
| 2243 | * On Valleyview some DSI panels lose (v|h)sync when the clock is lower | 2254 | * On Valleyview some DSI panels lose (v|h)sync when the clock is lower |
| 2244 | * than 320000KHz. | 2255 | * than 320000KHz. |
| @@ -1839,7 +1839,7 @@ static void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state) · 1838 unmodified lines | |||
| 1839 | /* FIXME: assert CPU port conditions for SNB+ */ | 1839 | /* FIXME: assert CPU port conditions for SNB+ */ |
| 1840 | } | 1840 | } |
| 1841 | 1841 | ||
| 1842 | trace_intel_pipe_enable(dev_priv, pipe); | 1842 | trace_intel_pipe_enable(crtc); |
| 1843 | 1843 | ||
| 1844 | reg = PIPECONF(cpu_transcoder); | 1844 | reg = PIPECONF(cpu_transcoder); |
| 1845 | val = I915_READ(reg); | 1845 | val = I915_READ(reg); |
| @@ -1880,7 +1880,7 @@ static void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state) · 34 unmodified lines | |||
| 1880 | */ | 1880 | */ |
| 1881 | assert_planes_disabled(crtc); | 1881 | assert_planes_disabled(crtc); |
| 1882 | 1882 | ||
| 1883 | trace_intel_pipe_disable(dev_priv, pipe); | 1883 | trace_intel_pipe_disable(crtc); |
| 1884 | 1884 | ||
| 1885 | reg = PIPECONF(cpu_transcoder); | 1885 | reg = PIPECONF(cpu_transcoder); |
| 1886 | val = I915_READ(reg); | 1886 | val = I915_READ(reg); |
| @@ -12042,7 +12042,7 @@ static bool check_digital_port_conflicts(struct intel_atomic_state *state) · 10155 unmodified lines | |||
| 12042 | case INTEL_OUTPUT_DDI: | 12042 | case INTEL_OUTPUT_DDI: |
| 12043 | if (WARN_ON(!HAS_DDI(to_i915(dev)))) | 12043 | if (WARN_ON(!HAS_DDI(to_i915(dev)))) |
| 12044 | break; | 12044 | break; |
| 12045 | /* else: fall through */ | 12045 | /* else, fall through */ |
| 12046 | case INTEL_OUTPUT_DP: | 12046 | case INTEL_OUTPUT_DP: |
| 12047 | case INTEL_OUTPUT_HDMI: | 12047 | case INTEL_OUTPUT_HDMI: |
| 12048 | case INTEL_OUTPUT_EDP: | 12048 | case INTEL_OUTPUT_EDP: |
| @@ -438,16 +438,23 @@ icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv, · 437 unmodified lines | |||
| 438 | #define ICL_AUX_PW_TO_CH(pw_idx) \ | 438 | #define ICL_AUX_PW_TO_CH(pw_idx) \ |
| 439 | ((pw_idx) - ICL_PW_CTL_IDX_AUX_A + AUX_CH_A) | 439 | ((pw_idx) - ICL_PW_CTL_IDX_AUX_A + AUX_CH_A) |
| 440 | 440 | ||
| 441 | #define ICL_TBT_AUX_PW_TO_CH(pw_idx) \ | ||
| 442 | ((pw_idx) - ICL_PW_CTL_IDX_AUX_TBT1 + AUX_CH_C) | ||
| 443 | |||
| 441 | static void | 444 | static void |
| 442 | icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv, | 445 | icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv, |
| 443 | struct i915_power_well *power_well) | 446 | struct i915_power_well *power_well) |
| 444 | { | 447 | { |
| 445 | enum aux_ch aux_ch = ICL_AUX_PW_TO_CH(power_well->desc->hsw.idx); | 448 | int pw_idx = power_well->desc->hsw.idx; |
| 449 | bool is_tbt = power_well->desc->hsw.is_tc_tbt; | ||
| 450 | enum aux_ch aux_ch; | ||
| 446 | u32 val; | 451 | u32 val; |
| 447 | 452 | ||
| 453 | aux_ch = is_tbt ? ICL_TBT_AUX_PW_TO_CH(pw_idx) : | ||
| 454 | ICL_AUX_PW_TO_CH(pw_idx); | ||
| 448 | val = I915_READ(DP_AUX_CH_CTL(aux_ch)); | 455 | val = I915_READ(DP_AUX_CH_CTL(aux_ch)); |
| 449 | val &= ~DP_AUX_CH_CTL_TBT_IO; | 456 | val &= ~DP_AUX_CH_CTL_TBT_IO; |
| 450 | if (power_well->desc->hsw.is_tc_tbt) | 457 | if (is_tbt) |
| 451 | val |= DP_AUX_CH_CTL_TBT_IO; | 458 | val |= DP_AUX_CH_CTL_TBT_IO; |
| 452 | I915_WRITE(DP_AUX_CH_CTL(aux_ch), val); | 459 | I915_WRITE(DP_AUX_CH_CTL(aux_ch), val); |
| 453 | 460 | ||
| @@ -231,6 +231,7 @@ static int intel_dp_get_fia_supported_lane_count(struct intel_dp *intel_dp) · 230 unmodified lines | |||
| 231 | switch (lane_info) { | 231 | switch (lane_info) { |
| 232 | default: | 232 | default: |
| 233 | MISSING_CASE(lane_info); | 233 | MISSING_CASE(lane_info); |
| 234 | /* fall through */ | ||
| 234 | case 1: | 235 | case 1: |
| 235 | case 2: | 236 | case 2: |
| 236 | case 4: | 237 | case 4: |
| @@ -536,7 +536,8 @@ int intel_hdcp_auth_downstream(struct intel_connector *connector) · 535 unmodified lines | |||
| 536 | 536 | ||
| 537 | if (drm_hdcp_check_ksvs_revoked(dev, ksv_fifo, num_downstream)) { | 537 | if (drm_hdcp_check_ksvs_revoked(dev, ksv_fifo, num_downstream)) { |
| 538 | DRM_ERROR("Revoked Ksv(s) in ksv_fifo\n"); | 538 | DRM_ERROR("Revoked Ksv(s) in ksv_fifo\n"); |
| 539 | return -EPERM; | 539 | ret = -EPERM; |
| 540 | goto err; | ||
| 540 | } | 541 | } |
| 541 | 542 | ||
| 542 | /* | 543 | /* |
| @@ -478,13 +478,13 @@ struct psr_table { · 477 unmodified lines | |||
| 478 | /* TP wake up time in multiple of 100 */ | 478 | /* TP wake up time in multiple of 100 */ |
| 479 | u16 tp1_wakeup_time; | 479 | u16 tp1_wakeup_time; |
| 480 | u16 tp2_tp3_wakeup_time; | 480 | u16 tp2_tp3_wakeup_time; |
| 481 | |||
| 482 | /* PSR2 TP2/TP3 wakeup time for 16 panels */ | ||
| 483 | u32 psr2_tp2_tp3_wakeup_time; | ||
| 484 | } __packed; | 481 | } __packed; |
| 485 | 482 | ||
| 486 | struct bdb_psr { | 483 | struct bdb_psr { |
| 487 | struct psr_table psr_table[16]; | 484 | struct psr_table psr_table[16]; |
| 485 | |||
| 486 | /* PSR2 TP2/TP3 wakeup time for 16 panels */ | ||
| 487 | u32 psr2_tp2_tp3_wakeup_time; | ||
| 488 | } __packed; | 488 | } __packed; |
| 489 | 489 | ||
| 490 | /* | 490 | /* |
| @@ -396,8 +396,8 @@ static void glk_dsi_program_esc_clock(struct drm_device *dev, · 395 unmodified lines | |||
| 396 | else | 396 | else |
| 397 | txesc2_div = 10; | 397 | txesc2_div = 10; |
| 398 | 398 | ||
| 399 | I915_WRITE(MIPIO_TXESC_CLK_DIV1, txesc1_div & GLK_TX_ESC_CLK_DIV1_MASK); | 399 | I915_WRITE(MIPIO_TXESC_CLK_DIV1, (1 << (txesc1_div - 1)) & GLK_TX_ESC_CLK_DIV1_MASK); |
| 400 | I915_WRITE(MIPIO_TXESC_CLK_DIV2, txesc2_div & GLK_TX_ESC_CLK_DIV2_MASK); | 400 | I915_WRITE(MIPIO_TXESC_CLK_DIV2, (1 << (txesc2_div - 1)) & GLK_TX_ESC_CLK_DIV2_MASK); |
| 401 | } | 401 | } |
| 402 | 402 | ||
| 403 | /* Program BXT Mipi clocks and dividers */ | 403 | /* Program BXT Mipi clocks and dividers */ |
| @@ -1628,6 +1628,7 @@ static int check_relocations(const struct drm_i915_gem_exec_object2 *entry) · 1627 unmodified lines | |||
| 1628 | 1628 | ||
| 1629 | static int eb_copy_relocations(const struct i915_execbuffer *eb) | 1629 | static int eb_copy_relocations(const struct i915_execbuffer *eb) |
| 1630 | { | 1630 | { |
| 1631 | struct drm_i915_gem_relocation_entry *relocs; | ||
| 1631 | const unsigned int count = eb->buffer_count; | 1632 | const unsigned int count = eb->buffer_count; |
| 1632 | unsigned int i; | 1633 | unsigned int i; |
| 1633 | int err; | 1634 | int err; |
| @@ -1635,7 +1636,6 @@ static int eb_copy_relocations(const struct i915_execbuffer *eb) · 1 unmodified line | |||
| 1635 | for (i = 0; i < count; i++) { | 1636 | for (i = 0; i < count; i++) { |
| 1636 | const unsigned int nreloc = eb->exec[i].relocation_count; | 1637 | const unsigned int nreloc = eb->exec[i].relocation_count; |
| 1637 | struct drm_i915_gem_relocation_entry __user *urelocs; | 1638 | struct drm_i915_gem_relocation_entry __user *urelocs; |
| 1638 | struct drm_i915_gem_relocation_entry *relocs; | ||
| 1639 | unsigned long size; | 1639 | unsigned long size; |
| 1640 | unsigned long copied; | 1640 | unsigned long copied; |
| 1641 | 1641 | ||
| @@ -1663,14 +1663,8 @@ static int eb_copy_relocations(const struct i915_execbuffer *eb) · 21 unmodified lines | |||
| 1663 | 1663 | ||
| 1664 | if (__copy_from_user((char *)relocs + copied, | 1664 | if (__copy_from_user((char *)relocs + copied, |
| 1665 | (char __user *)urelocs + copied, | 1665 | (char __user *)urelocs + copied, |
| 1666 | len)) { | 1666 | len)) |
| 1667 | end_user: | 1667 | goto end; |
| 1668 | user_access_end(); | ||
| 1669 | end: | ||
| 1670 | kvfree(relocs); | ||
| 1671 | err = -EFAULT; | ||
| 1672 | goto err; | ||
| 1673 | } | ||
| 1674 | 1668 | ||
| 1675 | copied += len; | 1669 | copied += len; |
| 1676 | } while (copied < size); | 1670 | } while (copied < size); |
| @@ -1699,10 +1693,14 @@ end: · 22 unmodified lines | |||
| 1699 | 1693 | ||
| 1700 | return 0; | 1694 | return 0; |
| 1701 | 1695 | ||
| 1696 | end_user: | ||
| 1697 | user_access_end(); | ||
| 1698 | end: | ||
| 1699 | kvfree(relocs); | ||
| 1700 | err = -EFAULT; | ||
| 1702 | err: | 1701 | err: |
| 1703 | while (i--) { | 1702 | while (i--) { |
| 1704 | struct drm_i915_gem_relocation_entry *relocs = | 1703 | relocs = u64_to_ptr(typeof(*relocs), eb->exec[i].relocs_ptr); |
| 1705 | u64_to_ptr(typeof(*relocs), eb->exec[i].relocs_ptr); | ||
| 1706 | if (eb->exec[i].relocation_count) | 1704 | if (eb->exec[i].relocation_count) |
| 1707 | kvfree(relocs); | 1705 | kvfree(relocs); |
| 1708 | } | 1706 | } |
| @@ -341,7 +341,7 @@ err: · 340 unmodified lines | |||
| 341 | */ | 341 | */ |
| 342 | if (!i915_terminally_wedged(i915)) | 342 | if (!i915_terminally_wedged(i915)) |
| 343 | return VM_FAULT_SIGBUS; | 343 | return VM_FAULT_SIGBUS; |
| 344 | /* else: fall through */ | 344 | /* else, fall through */ |
| 345 | case -EAGAIN: | 345 | case -EAGAIN: |
| 346 | /* | 346 | /* |
| 347 | * EAGAIN means the gpu is hung and we'll wait for the error | 347 | * EAGAIN means the gpu is hung and we'll wait for the error |
| @@ -268,7 +268,7 @@ static void *i915_gem_object_map(const struct drm_i915_gem_object *obj, · 267 unmodified lines | |||
| 268 | switch (type) { | 268 | switch (type) { |
| 269 | default: | 269 | default: |
| 270 | MISSING_CASE(type); | 270 | MISSING_CASE(type); |
| 271 | /* fallthrough to use PAGE_KERNEL anyway */ | 271 | /* fallthrough - to use PAGE_KERNEL anyway */ |
| 272 | case I915_MAP_WB: | 272 | case I915_MAP_WB: |
| 273 | pgprot = PAGE_KERNEL; | 273 | pgprot = PAGE_KERNEL; |
| 274 | break; | 274 | break; |
| @@ -253,14 +253,15 @@ void i915_gem_resume(struct drm_i915_private *i915) · 252 unmodified lines | |||
| 253 | i915_gem_restore_gtt_mappings(i915); | 253 | i915_gem_restore_gtt_mappings(i915); |
| 254 | i915_gem_restore_fences(i915); | 254 | i915_gem_restore_fences(i915); |
| 255 | 255 | ||
| 256 | if (i915_gem_init_hw(i915)) | ||
| 257 | goto err_wedged; | ||
| 258 | |||
| 256 | /* | 259 | /* |
| 257 | * As we didn't flush the kernel context before suspend, we cannot | 260 | * As we didn't flush the kernel context before suspend, we cannot |
| 258 | * guarantee that the context image is complete. So let's just reset | 261 | * guarantee that the context image is complete. So let's just reset |
| 259 | * it and start again. | 262 | * it and start again. |
| 260 | */ | 263 | */ |
| 261 | intel_gt_resume(i915); | 264 | if (intel_gt_resume(i915)) |
| 262 | |||
| 263 | if (i915_gem_init_hw(i915)) | ||
| 264 | goto err_wedged; | 265 | goto err_wedged; |
| 265 | 266 | ||
| 266 | intel_uc_resume(i915); | 267 | intel_uc_resume(i915); |
| @@ -664,7 +664,15 @@ i915_gem_userptr_put_pages(struct drm_i915_gem_object *obj, · 663 unmodified lines | |||
| 664 | 664 | ||
| 665 | for_each_sgt_page(page, sgt_iter, pages) { | 665 | for_each_sgt_page(page, sgt_iter, pages) { |
| 666 | if (obj->mm.dirty) | 666 | if (obj->mm.dirty) |
| 667 | set_page_dirty(page); | 667 | /* |
| 668 | * As this may not be anonymous memory (e.g. shmem) | ||
| 669 | * but exist on a real mapping, we have to lock | ||
| 670 | * the page in order to dirty it -- holding | ||
| 671 | * the page reference is not sufficient to | ||
| 672 | * prevent the inode from being truncated. | ||
| 673 | * Play safe and take the lock. | ||
| 674 | */ | ||
| 675 | set_page_dirty_lock(page); | ||
| 668 | 676 | ||
| 669 | mark_page_accessed(page); | 677 | mark_page_accessed(page); |
| 670 | put_page(page); | 678 | put_page(page); |
| @@ -126,6 +126,7 @@ static void intel_context_retire(struct i915_active *active) · 125 unmodified lines | |||
| 126 | if (ce->state) | 126 | if (ce->state) |
| 127 | __context_unpin_state(ce->state); | 127 | __context_unpin_state(ce->state); |
| 128 | 128 | ||
| 129 | intel_ring_unpin(ce->ring); | ||
| 129 | intel_context_put(ce); | 130 | intel_context_put(ce); |
| 130 | } | 131 | } |
| 131 | 132 | ||
| @@ -160,27 +161,35 @@ int intel_context_active_acquire(struct intel_context *ce, unsigned long flags) · 28 unmodified lines | |||
| 160 | 161 | ||
| 161 | intel_context_get(ce); | 162 | intel_context_get(ce); |
| 162 | 163 | ||
| 164 | err = intel_ring_pin(ce->ring); | ||
| 165 | if (err) | ||
| 166 | goto err_put; | ||
| 167 | |||
| 163 | if (!ce->state) | 168 | if (!ce->state) |
| 164 | return 0; | 169 | return 0; |
| 165 | 170 | ||
| 166 | err = __context_pin_state(ce->state, flags); | 171 | err = __context_pin_state(ce->state, flags); |
| 167 | if (err) { | 172 | if (err) |
| 168 | i915_active_cancel(&ce->active); | 173 | goto err_ring; |
| 169 | intel_context_put(ce); | ||
| 170 | return err; | ||
| 171 | } | ||
| 172 | 174 | ||
| 173 | /* Preallocate tracking nodes */ | 175 | /* Preallocate tracking nodes */ |
| 174 | if (!i915_gem_context_is_kernel(ce->gem_context)) { | 176 | if (!i915_gem_context_is_kernel(ce->gem_context)) { |
| 175 | err = i915_active_acquire_preallocate_barrier(&ce->active, | 177 | err = i915_active_acquire_preallocate_barrier(&ce->active, |
| 176 | ce->engine); | 178 | ce->engine); |
| 177 | if (err) { | 179 | if (err) |
| 178 | i915_active_release(&ce->active); | 180 | goto err_state; |
| 179 | return err; | ||
| 180 | } | ||
| 181 | } | 181 | } |
| 182 | 182 | ||
| 183 | return 0; | 183 | return 0; |
| 184 | |||
| 185 | err_state: | ||
| 186 | __context_unpin_state(ce->state); | ||
| 187 | err_ring: | ||
| 188 | intel_ring_unpin(ce->ring); | ||
| 189 | err_put: | ||
| 190 | intel_context_put(ce); | ||
| 191 | i915_active_cancel(&ce->active); | ||
| 192 | return err; | ||
| 184 | } | 193 | } |
| 185 | 194 | ||
| 186 | void intel_context_active_release(struct intel_context *ce) | 195 | void intel_context_active_release(struct intel_context *ce) |
| @@ -969,9 +969,14 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type) · 968 unmodified lines | |||
| 969 | u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv) | 969 | u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv) |
| 970 | { | 970 | { |
| 971 | const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; | 971 | const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu; |
| 972 | unsigned int slice = fls(sseu->slice_mask) - 1; | ||
| 973 | unsigned int subslice; | ||
| 972 | u32 mcr_s_ss_select; | 974 | u32 mcr_s_ss_select; |
| 973 | u32 slice = fls(sseu->slice_mask); | 975 | |
| 974 | u32 subslice = fls(sseu->subslice_mask[slice]); | 976 | GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask)); |
| 977 | subslice = fls(sseu->subslice_mask[slice]); | ||
| 978 | GEM_BUG_ON(!subslice); | ||
| 979 | subslice--; | ||
| 975 | 980 | ||
| 976 | if (IS_GEN(dev_priv, 10)) | 981 | if (IS_GEN(dev_priv, 10)) |
| 977 | mcr_s_ss_select = GEN8_MCR_SLICE(slice) | | 982 | mcr_s_ss_select = GEN8_MCR_SLICE(slice) | |
| @@ -1471,6 +1476,7 @@ void intel_engine_dump(struct intel_engine_cs *engine, · 493 unmodified lines | |||
| 1471 | struct i915_gpu_error * const error = &engine->i915->gpu_error; | 1476 | struct i915_gpu_error * const error = &engine->i915->gpu_error; |
| 1472 | struct i915_request *rq; | 1477 | struct i915_request *rq; |
| 1473 | intel_wakeref_t wakeref; | 1478 | intel_wakeref_t wakeref; |
| 1479 | unsigned long flags; | ||
| 1474 | 1480 | ||
| 1475 | if (header) { | 1481 | if (header) { |
| 1476 | va_list ap; | 1482 | va_list ap; |
| @@ -1490,10 +1496,9 @@ void intel_engine_dump(struct intel_engine_cs *engine, · 13 unmodified lines | |||
| 1490 | i915_reset_engine_count(error, engine), | 1496 | i915_reset_engine_count(error, engine), |
| 1491 | i915_reset_count(error)); | 1497 | i915_reset_count(error)); |
| 1492 | 1498 | ||
| 1493 | rcu_read_lock(); | ||
| 1494 | |||
| 1495 | drm_printf(m, "\tRequests:\n"); | 1499 | drm_printf(m, "\tRequests:\n"); |
| 1496 | 1500 | ||
| 1501 | spin_lock_irqsave(&engine->active.lock, flags); | ||
| 1497 | rq = intel_engine_find_active_request(engine); | 1502 | rq = intel_engine_find_active_request(engine); |
| 1498 | if (rq) { | 1503 | if (rq) { |
| 1499 | print_request(m, rq, "\t\tactive "); | 1504 | print_request(m, rq, "\t\tactive "); |
| @@ -1513,8 +1518,7 @@ void intel_engine_dump(struct intel_engine_cs *engine, · 13 unmodified lines | |||
| 1513 | 1518 | ||
| 1514 | print_request_ring(m, rq); | 1519 | print_request_ring(m, rq); |
| 1515 | } | 1520 | } |
| 1516 | 1521 | spin_unlock_irqrestore(&engine->active.lock, flags); | |
| 1517 | rcu_read_unlock(); | ||
| 1518 | 1522 | ||
| 1519 | wakeref = intel_runtime_pm_get_if_in_use(&engine->i915->runtime_pm); | 1523 | wakeref = intel_runtime_pm_get_if_in_use(&engine->i915->runtime_pm); |
| 1520 | if (wakeref) { | 1524 | if (wakeref) { |
| @@ -1672,7 +1676,6 @@ struct i915_request * · 151 unmodified lines | |||
| 1672 | intel_engine_find_active_request(struct intel_engine_cs *engine) | 1676 | intel_engine_find_active_request(struct intel_engine_cs *engine) |
| 1673 | { | 1677 | { |
| 1674 | struct i915_request *request, *active = NULL; | 1678 | struct i915_request *request, *active = NULL; |
| 1675 | unsigned long flags; | ||
| 1676 | 1679 | ||
| 1677 | /* | 1680 | /* |
| 1678 | * We are called by the error capture, reset and to dump engine | 1681 | * We are called by the error capture, reset and to dump engine |
| @@ -1685,7 +1688,7 @@ intel_engine_find_active_request(struct intel_engine_cs *engine) · 6 unmodified lines | |||
| 1685 | * At all other times, we must assume the GPU is still running, but | 1688 | * At all other times, we must assume the GPU is still running, but |
| 1686 | * we only care about the snapshot of this moment. | 1689 | * we only care about the snapshot of this moment. |
| 1687 | */ | 1690 | */ |
| 1688 | spin_lock_irqsave(&engine->active.lock, flags); | 1691 | lockdep_assert_held(&engine->active.lock); |
| 1689 | list_for_each_entry(request, &engine->active.requests, sched.link) { | 1692 | list_for_each_entry(request, &engine->active.requests, sched.link) { |
| 1690 | if (i915_request_completed(request)) | 1693 | if (i915_request_completed(request)) |
| 1691 | continue; | 1694 | continue; |
| @@ -1700,7 +1703,6 @@ intel_engine_find_active_request(struct intel_engine_cs *engine) · 8 unmodified lines | |||
| 1700 | active = request; | 1703 | active = request; |
| 1701 | break; | 1704 | break; |
| 1702 | } | 1705 | } |
| 1703 | spin_unlock_irqrestore(&engine->active.lock, flags); | ||
| 1704 | 1706 | ||
| 1705 | return active; | 1707 | return active; |
| 1706 | } | 1708 | } |
| @@ -142,27 +142,3 @@ void intel_engine_init__pm(struct intel_engine_cs *engine) · 141 unmodified lines | |||
| 142 | { | 142 | { |
| 143 | intel_wakeref_init(&engine->wakeref); | 143 | intel_wakeref_init(&engine->wakeref); |
| 144 | } | 144 | } |
| 145 | |||
| 146 | int intel_engines_resume(struct drm_i915_private *i915) | ||
| 147 | { | ||
| 148 | struct intel_engine_cs *engine; | ||
| 149 | enum intel_engine_id id; | ||
| 150 | int err = 0; | ||
| 151 | |||
| 152 | intel_gt_pm_get(i915); | ||
| 153 | for_each_engine(engine, i915, id) { | ||
| 154 | intel_engine_pm_get(engine); | ||
| 155 | engine->serial++; /* kernel context lost */ | ||
| 156 | err = engine->resume(engine); | ||
| 157 | intel_engine_pm_put(engine); | ||
| 158 | if (err) { | ||
| 159 | dev_err(i915->drm.dev, | ||
| 160 | "Failed to restart %s (%d)\n", | ||
| 161 | engine->name, err); | ||
| 162 | break; | ||
| 163 | } | ||
| 164 | } | ||
| 165 | intel_gt_pm_put(i915); | ||
| 166 | |||
| 167 | return err; | ||
| 168 | } | ||
| @@ -7,16 +7,22 @@ · 6 unmodified lines | |||
| 7 | #ifndef INTEL_ENGINE_PM_H | 7 | #ifndef INTEL_ENGINE_PM_H |
| 8 | #define INTEL_ENGINE_PM_H | 8 | #define INTEL_ENGINE_PM_H |
| 9 | 9 | ||
| 10 | #include "intel_engine_types.h" | ||
| 11 | #include "intel_wakeref.h" | ||
| 12 | |||
| 10 | struct drm_i915_private; | 13 | struct drm_i915_private; |
| 11 | struct intel_engine_cs; | ||
| 12 | 14 | ||
| 13 | void intel_engine_pm_get(struct intel_engine_cs *engine); | 15 | void intel_engine_pm_get(struct intel_engine_cs *engine); |
| 14 | void intel_engine_pm_put(struct intel_engine_cs *engine); | 16 | void intel_engine_pm_put(struct intel_engine_cs *engine); |
| 15 | 17 | ||
| 18 | static inline bool | ||
| 19 | intel_engine_pm_get_if_awake(struct intel_engine_cs *engine) | ||
| 20 | { | ||
| 21 | return intel_wakeref_get_if_active(&engine->wakeref); | ||
| 22 | } | ||
| 23 | |||
| 16 | void intel_engine_park(struct intel_engine_cs *engine); | 24 | void intel_engine_park(struct intel_engine_cs *engine); |
| 17 | 25 | ||
| 18 | void intel_engine_init__pm(struct intel_engine_cs *engine); | 26 | void intel_engine_init__pm(struct intel_engine_cs *engine); |
| 19 | 27 | ||
| 20 | int intel_engines_resume(struct drm_i915_private *i915); | ||
| 21 | |||
| 22 | #endif /* INTEL_ENGINE_PM_H */ | 28 | #endif /* INTEL_ENGINE_PM_H */ |
| @@ -70,6 +70,18 @@ struct intel_ring { · 69 unmodified lines | |||
| 70 | struct list_head request_list; | 70 | struct list_head request_list; |
| 71 | struct list_head active_link; | 71 | struct list_head active_link; |
| 72 | 72 | ||
| 73 | /* | ||
| 74 | * As we have two types of rings, one global to the engine used | ||
| 75 | * by ringbuffer submission and those that are exclusive to a | ||
| 76 | * context used by execlists, we have to play safe and allow | ||
| 77 | * atomic updates to the pin_count. However, the actual pinning | ||
| 78 | * of the context is either done during initialisation for | ||
| 79 | * ringbuffer submission or serialised as part of the context | ||
| 80 | * pinning for execlists, and so we do not need a mutex ourselves | ||
| 81 | * to serialise intel_ring_pin/intel_ring_unpin. | ||
| 82 | */ | ||
| 83 | atomic_t pin_count; | ||
| 84 | |||
| 73 | u32 head; | 85 | u32 head; |
| 74 | u32 tail; | 86 | u32 tail; |
| 75 | u32 emit; | 87 | u32 emit; |
| @@ -5,6 +5,7 @@ · 4 unmodified lines | |||
| 5 | */ | 5 | */ |
| 6 | 6 | ||
| 7 | #include "i915_drv.h" | 7 | #include "i915_drv.h" |
| 8 | #include "intel_engine_pm.h" | ||
| 8 | #include "intel_gt_pm.h" | 9 | #include "intel_gt_pm.h" |
| 9 | #include "intel_pm.h" | 10 | #include "intel_pm.h" |
| 10 | #include "intel_wakeref.h" | 11 | #include "intel_wakeref.h" |
| @@ -118,10 +119,11 @@ void intel_gt_sanitize(struct drm_i915_private *i915, bool force) · 107 unmodified lines | |||
| 118 | intel_engine_reset(engine, false); | 119 | intel_engine_reset(engine, false); |
| 119 | } | 120 | } |
| 120 | 121 | ||
| 121 | void intel_gt_resume(struct drm_i915_private *i915) | 122 | int intel_gt_resume(struct drm_i915_private *i915) |
| 122 | { | 123 | { |
| 123 | struct intel_engine_cs *engine; | 124 | struct intel_engine_cs *engine; |
| 124 | enum intel_engine_id id; | 125 | enum intel_engine_id id; |
| 126 | int err = 0; | ||
| 125 | 127 | ||
| 126 | /* | 128 | /* |
| 127 | * After resume, we may need to poke into the pinned kernel | 129 | * After resume, we may need to poke into the pinned kernel |
| @@ -129,9 +131,12 @@ void intel_gt_resume(struct drm_i915_private *i915) · 1 unmodified line | |||
| 129 | * Only the kernel contexts should remain pinned over suspend, | 131 | * Only the kernel contexts should remain pinned over suspend, |
| 130 | * allowing us to fixup the user contexts on their first pin. | 132 | * allowing us to fixup the user contexts on their first pin. |
| 131 | */ | 133 | */ |
| 134 | intel_gt_pm_get(i915); | ||
| 132 | for_each_engine(engine, i915, id) { | 135 | for_each_engine(engine, i915, id) { |
| 133 | struct intel_context *ce; | 136 | struct intel_context *ce; |
| 134 | 137 | ||
| 138 | intel_engine_pm_get(engine); | ||
| 139 | |||
| 135 | ce = engine->kernel_context; | 140 | ce = engine->kernel_context; |
| 136 | if (ce) | 141 | if (ce) |
| 137 | ce->ops->reset(ce); | 142 | ce->ops->reset(ce); |
| @@ -139,5 +144,19 @@ void intel_gt_resume(struct drm_i915_private *i915) · 1 unmodified line | |||
| 139 | ce = engine->preempt_context; | 144 | ce = engine->preempt_context; |
| 140 | if (ce) | 145 | if (ce) |
| 141 | ce->ops->reset(ce); | 146 | ce->ops->reset(ce); |
| 147 | |||
| 148 | engine->serial++; /* kernel context lost */ | ||
| 149 | err = engine->resume(engine); | ||
| 150 | |||
| 151 | intel_engine_pm_put(engine); | ||
| 152 | if (err) { | ||
| 153 | dev_err(i915->drm.dev, | ||
| 154 | "Failed to restart %s (%d)\n", | ||
| 155 | engine->name, err); | ||
| 156 | break; | ||
| 157 | } | ||
| 142 | } | 158 | } |
| 159 | intel_gt_pm_put(i915); | ||
| 160 | |||
| 161 | return err; | ||
| 143 | } | 162 | } |
| @@ -22,6 +22,6 @@ void intel_gt_pm_put(struct drm_i915_private *i915); · 21 unmodified lines | |||
| 22 | void intel_gt_pm_init(struct drm_i915_private *i915); | 22 | void intel_gt_pm_init(struct drm_i915_private *i915); |
| 23 | 23 | ||
| 24 | void intel_gt_sanitize(struct drm_i915_private *i915, bool force); | 24 | void intel_gt_sanitize(struct drm_i915_private *i915, bool force); |
| 25 | void intel_gt_resume(struct drm_i915_private *i915); | 25 | int intel_gt_resume(struct drm_i915_private *i915); |
| 26 | 26 | ||
| 27 | #endif /* INTEL_GT_PM_H */ | 27 | #endif /* INTEL_GT_PM_H */ |
| @@ -1414,6 +1414,7 @@ static void execlists_context_destroy(struct kref *kref) · 1413 unmodified lines | |||
| 1414 | { | 1414 | { |
| 1415 | struct intel_context *ce = container_of(kref, typeof(*ce), ref); | 1415 | struct intel_context *ce = container_of(kref, typeof(*ce), ref); |
| 1416 | 1416 | ||
| 1417 | GEM_BUG_ON(!i915_active_is_idle(&ce->active)); | ||
| 1417 | GEM_BUG_ON(intel_context_is_pinned(ce)); | 1418 | GEM_BUG_ON(intel_context_is_pinned(ce)); |
| 1418 | 1419 | ||
| 1419 | if (ce->state) | 1420 | if (ce->state) |
| @@ -1426,7 +1427,6 @@ static void execlists_context_unpin(struct intel_context *ce) · 6 unmodified lines | |||
| 1426 | { | 1427 | { |
| 1427 | i915_gem_context_unpin_hw_id(ce->gem_context); | 1428 | i915_gem_context_unpin_hw_id(ce->gem_context); |
| 1428 | i915_gem_object_unpin_map(ce->state->obj); | 1429 | i915_gem_object_unpin_map(ce->state->obj); |
| 1429 | intel_ring_unpin(ce->ring); | ||
| 1430 | } | 1430 | } |
| 1431 | 1431 | ||
| 1432 | static void | 1432 | static void |
| @@ -1478,13 +1478,9 @@ __execlists_context_pin(struct intel_context *ce, · 45 unmodified lines | |||
| 1478 | goto unpin_active; | 1478 | goto unpin_active; |
| 1479 | } | 1479 | } |
| 1480 | 1480 | ||
| 1481 | ret = intel_ring_pin(ce->ring); | ||
| 1482 | if (ret) | ||
| 1483 | goto unpin_map; | ||
| 1484 | |||
| 1485 | ret = i915_gem_context_pin_hw_id(ce->gem_context); | 1481 | ret = i915_gem_context_pin_hw_id(ce->gem_context); |
| 1486 | if (ret) | 1482 | if (ret) |
| 1487 | goto unpin_ring; | 1483 | goto unpin_map; |
| 1488 | 1484 | ||
| 1489 | ce->lrc_desc = lrc_descriptor(ce, engine); | 1485 | ce->lrc_desc = lrc_descriptor(ce, engine); |
| 1490 | ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE; | 1486 | ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE; |
| @@ -1492,8 +1488,6 @@ __execlists_context_pin(struct intel_context *ce, · 1 unmodified line | |||
| 1492 | 1488 | ||
| 1493 | return 0; | 1489 | return 0; |
| 1494 | 1490 | ||
| 1495 | unpin_ring: | ||
| 1496 | intel_ring_unpin(ce->ring); | ||
| 1497 | unpin_map: | 1491 | unpin_map: |
| 1498 | i915_gem_object_unpin_map(ce->state->obj); | 1492 | i915_gem_object_unpin_map(ce->state->obj); |
| 1499 | unpin_active: | 1493 | unpin_active: |
| @@ -687,7 +687,6 @@ static void reset_prepare_engine(struct intel_engine_cs *engine) · 686 unmodified lines | |||
| 687 | * written to the powercontext is undefined and so we may lose | 687 | * written to the powercontext is undefined and so we may lose |
| 688 | * GPU state upon resume, i.e. fail to restart after a reset. | 688 | * GPU state upon resume, i.e. fail to restart after a reset. |
| 689 | */ | 689 | */ |
| 690 | intel_engine_pm_get(engine); | ||
| 691 | intel_uncore_forcewake_get(engine->uncore, FORCEWAKE_ALL); | 690 | intel_uncore_forcewake_get(engine->uncore, FORCEWAKE_ALL); |
| 692 | engine->reset.prepare(engine); | 691 | engine->reset.prepare(engine); |
| 693 | } | 692 | } |
| @@ -718,16 +717,21 @@ static void revoke_mmaps(struct drm_i915_private *i915) · 24 unmodified lines | |||
| 718 | } | 717 | } |
| 719 | } | 718 | } |
| 720 | 719 | ||
| 721 | static void reset_prepare(struct drm_i915_private *i915) | 720 | static intel_engine_mask_t reset_prepare(struct drm_i915_private *i915) |
| 722 | { | 721 | { |
| 723 | struct intel_engine_cs *engine; | 722 | struct intel_engine_cs *engine; |
| 723 | intel_engine_mask_t awake = 0; | ||
| 724 | enum intel_engine_id id; | 724 | enum intel_engine_id id; |
| 725 | 725 | ||
| 726 | intel_gt_pm_get(i915); | 726 | for_each_engine(engine, i915, id) { |
| 727 | for_each_engine(engine, i915, id) | 727 | if (intel_engine_pm_get_if_awake(engine)) |
| 728 | awake |= engine->mask; | ||
| 728 | reset_prepare_engine(engine); | 729 | reset_prepare_engine(engine); |
| 730 | } | ||
| 729 | 731 | ||
| 730 | intel_uc_reset_prepare(i915); | 732 | intel_uc_reset_prepare(i915); |
| 733 | |||
| 734 | return awake; | ||
| 731 | } | 735 | } |
| 732 | 736 | ||
| 733 | static void gt_revoke(struct drm_i915_private *i915) | 737 | static void gt_revoke(struct drm_i915_private *i915) |
| @@ -761,20 +765,22 @@ static int gt_reset(struct drm_i915_private *i915, · 27 unmodified lines | |||
| 761 | static void reset_finish_engine(struct intel_engine_cs *engine) | 765 | static void reset_finish_engine(struct intel_engine_cs *engine) |
| 762 | { | 766 | { |
| 763 | engine->reset.finish(engine); | 767 | engine->reset.finish(engine); |
| 764 | intel_engine_pm_put(engine); | ||
| 765 | intel_uncore_forcewake_put(engine->uncore, FORCEWAKE_ALL); | 768 | intel_uncore_forcewake_put(engine->uncore, FORCEWAKE_ALL); |
| 769 | |||
| 770 | intel_engine_signal_breadcrumbs(engine); | ||
| 766 | } | 771 | } |
| 767 | 772 | ||
| 768 | static void reset_finish(struct drm_i915_private *i915) | 773 | static void reset_finish(struct drm_i915_private *i915, |
| 774 | intel_engine_mask_t awake) | ||
| 769 | { | 775 | { |
| 770 | struct intel_engine_cs *engine; | 776 | struct intel_engine_cs *engine; |
| 771 | enum intel_engine_id id; | 777 | enum intel_engine_id id; |
| 772 | 778 | ||
| 773 | for_each_engine(engine, i915, id) { | 779 | for_each_engine(engine, i915, id) { |
| 774 | reset_finish_engine(engine); | 780 | reset_finish_engine(engine); |
| 775 | intel_engine_signal_breadcrumbs(engine); | 781 | if (awake & engine->mask) |
| 782 | intel_engine_pm_put(engine); | ||
| 776 | } | 783 | } |
| 777 | intel_gt_pm_put(i915); | ||
| 778 | } | 784 | } |
| 779 | 785 | ||
| 780 | static void nop_submit_request(struct i915_request *request) | 786 | static void nop_submit_request(struct i915_request *request) |
| @@ -798,6 +804,7 @@ static void __i915_gem_set_wedged(struct drm_i915_private *i915) · 17 unmodified lines | |||
| 798 | { | 804 | { |
| 799 | struct i915_gpu_error *error = &i915->gpu_error; | 805 | struct i915_gpu_error *error = &i915->gpu_error; |
| 800 | struct intel_engine_cs *engine; | 806 | struct intel_engine_cs *engine; |
| 807 | intel_engine_mask_t awake; | ||
| 801 | enum intel_engine_id id; | 808 | enum intel_engine_id id; |
| 802 | 809 | ||
| 803 | if (test_bit(I915_WEDGED, &error->flags)) | 810 | if (test_bit(I915_WEDGED, &error->flags)) |
| @@ -817,7 +824,7 @@ static void __i915_gem_set_wedged(struct drm_i915_private *i915) · 13 unmodified lines | |||
| 817 | * rolling the global seqno forward (since this would complete requests | 824 | * rolling the global seqno forward (since this would complete requests |
| 818 | * for which we haven't set the fence error to EIO yet). | 825 | * for which we haven't set the fence error to EIO yet). |
| 819 | */ | 826 | */ |
| 820 | reset_prepare(i915); | 827 | awake = reset_prepare(i915); |
| 821 | 828 | ||
| 822 | /* Even if the GPU reset fails, it should still stop the engines */ | 829 | /* Even if the GPU reset fails, it should still stop the engines */ |
| 823 | if (!INTEL_INFO(i915)->gpu_reset_clobbers_display) | 830 | if (!INTEL_INFO(i915)->gpu_reset_clobbers_display) |
| @@ -841,7 +848,7 @@ static void __i915_gem_set_wedged(struct drm_i915_private *i915) · 17 unmodified lines | |||
| 841 | for_each_engine(engine, i915, id) | 848 | for_each_engine(engine, i915, id) |
| 842 | engine->cancel_requests(engine); | 849 | engine->cancel_requests(engine); |
| 843 | 850 | ||
| 844 | reset_finish(i915); | 851 | reset_finish(i915, awake); |
| 845 | 852 | ||
| 846 | GEM_TRACE("end\n"); | 853 | GEM_TRACE("end\n"); |
| 847 | } | 854 | } |
| @@ -951,6 +958,21 @@ static int do_reset(struct drm_i915_private *i915, · 103 unmodified lines | |||
| 951 | return gt_reset(i915, stalled_mask); | 958 | return gt_reset(i915, stalled_mask); |
| 952 | } | 959 | } |
| 953 | 960 | ||
| 961 | static int resume(struct drm_i915_private *i915) | ||
| 962 | { | ||
| 963 | struct intel_engine_cs *engine; | ||
| 964 | enum intel_engine_id id; | ||
| 965 | int ret; | ||
| 966 | |||
| 967 | for_each_engine(engine, i915, id) { | ||
| 968 | ret = engine->resume(engine); | ||
| 969 | if (ret) | ||
| 970 | return ret; | ||
| 971 | } | ||
| 972 | |||
| 973 | return 0; | ||
| 974 | } | ||
| 975 | |||
| 954 | /** | 976 | /** |
| 955 | * i915_reset - reset chip after a hang | 977 | * i915_reset - reset chip after a hang |
| 956 | * @i915: #drm_i915_private to reset | 978 | * @i915: #drm_i915_private to reset |
| @@ -973,6 +995,7 @@ void i915_reset(struct drm_i915_private *i915, · 16 unmodified lines | |||
| 973 | const char *reason) | 995 | const char *reason) |
| 974 | { | 996 | { |
| 975 | struct i915_gpu_error *error = &i915->gpu_error; | 997 | struct i915_gpu_error *error = &i915->gpu_error; |
| 998 | intel_engine_mask_t awake; | ||
| 976 | int ret; | 999 | int ret; |
| 977 | 1000 | ||
| 978 | GEM_TRACE("flags=%lx\n", error->flags); | 1001 | GEM_TRACE("flags=%lx\n", error->flags); |
| @@ -989,7 +1012,7 @@ void i915_reset(struct drm_i915_private *i915, · 10 unmodified lines | |||
| 989 | dev_notice(i915->drm.dev, "Resetting chip for %s\n", reason); | 1012 | dev_notice(i915->drm.dev, "Resetting chip for %s\n", reason); |
| 990 | error->reset_count++; | 1013 | error->reset_count++; |
| 991 | 1014 | ||
| 992 | reset_prepare(i915); | 1015 | awake = reset_prepare(i915); |
| 993 | 1016 | ||
| 994 | if (!intel_has_gpu_reset(i915)) { | 1017 | if (!intel_has_gpu_reset(i915)) { |
| 995 | if (i915_modparams.reset) | 1018 | if (i915_modparams.reset) |
| @@ -1024,13 +1047,17 @@ void i915_reset(struct drm_i915_private *i915, · 28 unmodified lines | |||
| 1024 | if (ret) { | 1047 | if (ret) { |
| 1025 | DRM_ERROR("Failed to initialise HW following reset (%d)\n", | 1048 | DRM_ERROR("Failed to initialise HW following reset (%d)\n", |
| 1026 | ret); | 1049 | ret); |
| 1027 | goto error; | 1050 | goto taint; |
| 1028 | } | 1051 | } |
| 1029 | 1052 | ||
| 1053 | ret = resume(i915); | ||
| 1054 | if (ret) | ||
| 1055 | goto taint; | ||
| 1056 | |||
| 1030 | i915_queue_hangcheck(i915); | 1057 | i915_queue_hangcheck(i915); |
| 1031 | 1058 | ||
| 1032 | finish: | 1059 | finish: |
| 1033 | reset_finish(i915); | 1060 | reset_finish(i915, awake); |
| 1034 | unlock: | 1061 | unlock: |
| 1035 | mutex_unlock(&error->wedge_mutex); | 1062 | mutex_unlock(&error->wedge_mutex); |
| 1036 | return; | 1063 | return; |
| @@ -1081,7 +1108,7 @@ int i915_reset_engine(struct intel_engine_cs *engine, const char *msg) · 44 unmodified lines | |||
| 1081 | GEM_TRACE("%s flags=%lx\n", engine->name, error->flags); | 1108 | GEM_TRACE("%s flags=%lx\n", engine->name, error->flags); |
| 1082 | GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags)); | 1109 | GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags)); |
| 1083 | 1110 | ||
| 1084 | if (!intel_wakeref_active(&engine->wakeref)) | 1111 | if (!intel_engine_pm_get_if_awake(engine)) |
| 1085 | return 0; | 1112 | return 0; |
| 1086 | 1113 | ||
| 1087 | reset_prepare_engine(engine); | 1114 | reset_prepare_engine(engine); |
| @@ -1116,12 +1143,11 @@ int i915_reset_engine(struct intel_engine_cs *engine, const char *msg) · 28 unmodified lines | |||
| 1116 | * process to program RING_MODE, HWSP and re-enable submission. | 1143 | * process to program RING_MODE, HWSP and re-enable submission. |
| 1117 | */ | 1144 | */ |
| 1118 | ret = engine->resume(engine); | 1145 | ret = engine->resume(engine); |
| 1119 | if (ret) | ||
| 1120 | goto out; | ||
| 1121 | 1146 | ||
| 1122 | out: | 1147 | out: |
| 1123 | intel_engine_cancel_stop_cs(engine); | 1148 | intel_engine_cancel_stop_cs(engine); |
| 1124 | reset_finish_engine(engine); | 1149 | reset_finish_engine(engine); |
| 1150 | intel_engine_pm_put(engine); | ||
| 1125 | return ret; | 1151 | return ret; |
| 1126 | } | 1152 | } |
| 1127 | 1153 | ||
| @@ -1149,16 +1149,16 @@ i915_emit_bb_start(struct i915_request *rq, · 1148 unmodified lines | |||
| 1149 | int intel_ring_pin(struct intel_ring *ring) | 1149 | int intel_ring_pin(struct intel_ring *ring) |
| 1150 | { | 1150 | { |
| 1151 | struct i915_vma *vma = ring->vma; | 1151 | struct i915_vma *vma = ring->vma; |
| 1152 | enum i915_map_type map = i915_coherent_map_type(vma->vm->i915); | ||
| 1153 | unsigned int flags; | 1152 | unsigned int flags; |
| 1154 | void *addr; | 1153 | void *addr; |
| 1155 | int ret; | 1154 | int ret; |
| 1156 | 1155 | ||
| 1157 | GEM_BUG_ON(ring->vaddr); | 1156 | if (atomic_fetch_inc(&ring->pin_count)) |
| 1157 | return 0; | ||
| 1158 | 1158 | ||
| 1159 | ret = i915_timeline_pin(ring->timeline); | 1159 | ret = i915_timeline_pin(ring->timeline); |
| 1160 | if (ret) | 1160 | if (ret) |
| 1161 | return ret; | 1161 | goto err_unpin; |
| 1162 | 1162 | ||
| 1163 | flags = PIN_GLOBAL; | 1163 | flags = PIN_GLOBAL; |
| 1164 | 1164 | ||
| @@ -1172,26 +1172,31 @@ int intel_ring_pin(struct intel_ring *ring) · 7 unmodified lines | |||
| 1172 | 1172 | ||
| 1173 | ret = i915_vma_pin(vma, 0, 0, flags); | 1173 | ret = i915_vma_pin(vma, 0, 0, flags); |
| 1174 | if (unlikely(ret)) | 1174 | if (unlikely(ret)) |
| 1175 | goto unpin_timeline; | 1175 | goto err_timeline; |
| 1176 | 1176 | ||
| 1177 | if (i915_vma_is_map_and_fenceable(vma)) | 1177 | if (i915_vma_is_map_and_fenceable(vma)) |
| 1178 | addr = (void __force *)i915_vma_pin_iomap(vma); | 1178 | addr = (void __force *)i915_vma_pin_iomap(vma); |
| 1179 | else | 1179 | else |
| 1180 | addr = i915_gem_object_pin_map(vma->obj, map); | 1180 | addr = i915_gem_object_pin_map(vma->obj, |
| 1181 | i915_coherent_map_type(vma->vm->i915)); | ||
| 1181 | if (IS_ERR(addr)) { | 1182 | if (IS_ERR(addr)) { |
| 1182 | ret = PTR_ERR(addr); | 1183 | ret = PTR_ERR(addr); |
| 1183 | goto unpin_ring; | 1184 | goto err_ring; |
| 1184 | } | 1185 | } |
| 1185 | 1186 | ||
| 1186 | vma->obj->pin_global++; | 1187 | vma->obj->pin_global++; |
| 1187 | 1188 | ||
| 1189 | GEM_BUG_ON(ring->vaddr); | ||
| 1188 | ring->vaddr = addr; | 1190 | ring->vaddr = addr; |
| 1191 | |||
| 1189 | return 0; | 1192 | return 0; |
| 1190 | 1193 | ||
| 1191 | unpin_ring: | 1194 | err_ring: |
| 1192 | i915_vma_unpin(vma); | 1195 | i915_vma_unpin(vma); |
| 1193 | unpin_timeline: | 1196 | err_timeline: |
| 1194 | i915_timeline_unpin(ring->timeline); | 1197 | i915_timeline_unpin(ring->timeline); |
| 1198 | err_unpin: | ||
| 1199 | atomic_dec(&ring->pin_count); | ||
| 1195 | return ret; | 1200 | return ret; |
| 1196 | } | 1201 | } |
| 1197 | 1202 | ||
| @@ -1207,16 +1212,19 @@ void intel_ring_reset(struct intel_ring *ring, u32 tail) · 9 unmodified lines | |||
| 1207 | 1212 | ||
| 1208 | void intel_ring_unpin(struct intel_ring *ring) | 1213 | void intel_ring_unpin(struct intel_ring *ring) |
| 1209 | { | 1214 | { |
| 1210 | GEM_BUG_ON(!ring->vma); | 1215 | if (!atomic_dec_and_test(&ring->pin_count)) |
| 1211 | GEM_BUG_ON(!ring->vaddr); | 1216 | return; |
| 1212 | 1217 | ||
| 1213 | /* Discard any unused bytes beyond that submitted to hw. */ | 1218 | /* Discard any unused bytes beyond that submitted to hw. */ |
| 1214 | intel_ring_reset(ring, ring->tail); | 1219 | intel_ring_reset(ring, ring->tail); |
| 1215 | 1220 | ||
| 1221 | GEM_BUG_ON(!ring->vma); | ||
| 1216 | if (i915_vma_is_map_and_fenceable(ring->vma)) | 1222 | if (i915_vma_is_map_and_fenceable(ring->vma)) |
| 1217 | i915_vma_unpin_iomap(ring->vma); | 1223 | i915_vma_unpin_iomap(ring->vma); |
| 1218 | else | 1224 | else |
| 1219 | i915_gem_object_unpin_map(ring->vma->obj); | 1225 | i915_gem_object_unpin_map(ring->vma->obj); |
| 1226 | |||
| 1227 | GEM_BUG_ON(!ring->vaddr); | ||
| 1220 | ring->vaddr = NULL; | 1228 | ring->vaddr = NULL; |
| 1221 | 1229 | ||
| 1222 | ring->vma->obj->pin_global--; | 1230 | ring->vma->obj->pin_global--; |
| @@ -2081,10 +2089,11 @@ static void ring_destroy(struct intel_engine_cs *engine) · 858 unmodified lines | |||
| 2081 | WARN_ON(INTEL_GEN(dev_priv) > 2 && | 2089 | WARN_ON(INTEL_GEN(dev_priv) > 2 && |
| 2082 | (ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0); | 2090 | (ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0); |
| 2083 | 2091 | ||
| 2092 | intel_engine_cleanup_common(engine); | ||
| 2093 | |||
| 2084 | intel_ring_unpin(engine->buffer); | 2094 | intel_ring_unpin(engine->buffer); |
| 2085 | intel_ring_put(engine->buffer); | 2095 | intel_ring_put(engine->buffer); |
| 2086 | 2096 | ||
| 2087 | intel_engine_cleanup_common(engine); | ||
| 2088 | kfree(engine); | 2097 | kfree(engine); |
| 2089 | } | 2098 | } |
| 2090 | 2099 | ||
| @@ -1098,10 +1098,25 @@ static void glk_whitelist_build(struct intel_engine_cs *engine) · 1097 unmodified lines | |||
| 1098 | 1098 | ||
| 1099 | static void cfl_whitelist_build(struct intel_engine_cs *engine) | 1099 | static void cfl_whitelist_build(struct intel_engine_cs *engine) |
| 1100 | { | 1100 | { |
| 1101 | struct i915_wa_list *w = &engine->whitelist; | ||
| 1102 | |||
| 1101 | if (engine->class != RENDER_CLASS) | 1103 | if (engine->class != RENDER_CLASS) |
| 1102 | return; | 1104 | return; |
| 1103 | 1105 | ||
| 1104 | gen9_whitelist_build(&engine->whitelist); | 1106 | gen9_whitelist_build(w); |
| 1107 | |||
| 1108 | /* | ||
| 1109 | * WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl,whl,cml,aml | ||
| 1110 | * | ||
| 1111 | * This covers 4 register which are next to one another : | ||
| 1112 | * - PS_INVOCATION_COUNT | ||
| 1113 | * - PS_INVOCATION_COUNT_UDW | ||
| 1114 | * - PS_DEPTH_COUNT | ||
| 1115 | * - PS_DEPTH_COUNT_UDW | ||
| 1116 | */ | ||
| 1117 | whitelist_reg_ext(w, PS_INVOCATION_COUNT, | ||
| 1118 | RING_FORCE_TO_NONPRIV_RD | | ||
| 1119 | RING_FORCE_TO_NONPRIV_RANGE_4); | ||
| 1105 | } | 1120 | } |
| 1106 | 1121 | ||
| 1107 | static void cnl_whitelist_build(struct intel_engine_cs *engine) | 1122 | static void cnl_whitelist_build(struct intel_engine_cs *engine) |
| @@ -1129,6 +1144,19 @@ static void icl_whitelist_build(struct intel_engine_cs *engine) · 21 unmodified lines | |||
| 1129 | 1144 | ||
| 1130 | /* WaEnableStateCacheRedirectToCS:icl */ | 1145 | /* WaEnableStateCacheRedirectToCS:icl */ |
| 1131 | whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); | 1146 | whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1); |
| 1147 | |||
| 1148 | /* | ||
| 1149 | * WaAllowPMDepthAndInvocationCountAccessFromUMD:icl | ||
| 1150 | * | ||
| 1151 | * This covers 4 register which are next to one another : | ||
| 1152 | * - PS_INVOCATION_COUNT | ||
| 1153 | * - PS_INVOCATION_COUNT_UDW | ||
| 1154 | * - PS_DEPTH_COUNT | ||
| 1155 | * - PS_DEPTH_COUNT_UDW | ||
| 1156 | */ | ||
| 1157 | whitelist_reg_ext(w, PS_INVOCATION_COUNT, | ||
| 1158 | RING_FORCE_TO_NONPRIV_RD | | ||
| 1159 | RING_FORCE_TO_NONPRIV_RANGE_4); | ||
| 1132 | break; | 1160 | break; |
| 1133 | 1161 | ||
| 1134 | case VIDEO_DECODE_CLASS: | 1162 | case VIDEO_DECODE_CLASS: |
| @@ -1258,8 +1286,12 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) · 123 unmodified lines | |||
| 1258 | if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0)) | 1286 | if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0)) |
| 1259 | wa_write_or(wal, | 1287 | wa_write_or(wal, |
| 1260 | GEN7_SARCHKMD, | 1288 | GEN7_SARCHKMD, |
| 1261 | GEN7_DISABLE_DEMAND_PREFETCH | | 1289 | GEN7_DISABLE_DEMAND_PREFETCH); |
| 1262 | GEN7_DISABLE_SAMPLER_PREFETCH); | 1290 | |
| 1291 | /* Wa_1606682166:icl */ | ||
| 1292 | wa_write_or(wal, | ||
| 1293 | GEN7_SARCHKMD, | ||
| 1294 | GEN7_DISABLE_SAMPLER_PREFETCH); | ||
| 1263 | } | 1295 | } |
| 1264 | 1296 | ||
| 1265 | if (IS_GEN_RANGE(i915, 9, 11)) { | 1297 | if (IS_GEN_RANGE(i915, 9, 11)) { |
| @@ -66,6 +66,7 @@ static struct intel_ring *mock_ring(struct intel_engine_cs *engine) · 65 unmodified lines | |||
| 66 | ring->base.effective_size = sz; | 66 | ring->base.effective_size = sz; |
| 67 | ring->base.vaddr = (void *)(ring + 1); | 67 | ring->base.vaddr = (void *)(ring + 1); |
| 68 | ring->base.timeline = &ring->timeline; | 68 | ring->base.timeline = &ring->timeline; |
| 69 | atomic_set(&ring->base.pin_count, 1); | ||
| 69 | 70 | ||
| 70 | INIT_LIST_HEAD(&ring->base.request_list); | 71 | INIT_LIST_HEAD(&ring->base.request_list); |
| 71 | intel_ring_update_space(&ring->base); | 72 | intel_ring_update_space(&ring->base); |
| @@ -71,13 +71,16 @@ static int igt_atomic_reset(void *arg) · 70 unmodified lines | |||
| 71 | goto unlock; | 71 | goto unlock; |
| 72 | 72 | ||
| 73 | for (p = igt_atomic_phases; p->name; p++) { | 73 | for (p = igt_atomic_phases; p->name; p++) { |
| 74 | intel_engine_mask_t awake; | ||
| 75 | |||
| 74 | GEM_TRACE("intel_gpu_reset under %s\n", p->name); | 76 | GEM_TRACE("intel_gpu_reset under %s\n", p->name); |
| 75 | 77 | ||
| 78 | awake = reset_prepare(i915); | ||
| 76 | p->critical_section_begin(); | 79 | p->critical_section_begin(); |
| 77 | reset_prepare(i915); | 80 | reset_prepare(i915); |
| 78 | err = intel_gpu_reset(i915, ALL_ENGINES); | 81 | err = intel_gpu_reset(i915, ALL_ENGINES); |
| 79 | reset_finish(i915); | ||
| 80 | p->critical_section_end(); | 82 | p->critical_section_end(); |
| 83 | reset_finish(i915, awake); | ||
| 81 | 84 | ||
| 82 | if (err) { | 85 | if (err) { |
| 83 | pr_err("intel_gpu_reset failed under %s\n", p->name); | 86 | pr_err("intel_gpu_reset failed under %s\n", p->name); |
| @@ -925,7 +925,12 @@ check_whitelisted_registers(struct intel_engine_cs *engine, · 924 unmodified lines | |||
| 925 | 925 | ||
| 926 | err = 0; | 926 | err = 0; |
| 927 | for (i = 0; i < engine->whitelist.count; i++) { | 927 | for (i = 0; i < engine->whitelist.count; i++) { |
| 928 | if (!fn(engine, a[i], b[i], engine->whitelist.list[i].reg)) | 928 | const struct i915_wa *wa = &engine->whitelist.list[i]; |
| 929 | |||
| 930 | if (i915_mmio_reg_offset(wa->reg) & RING_FORCE_TO_NONPRIV_RD) | ||
| 931 | continue; | ||
| 932 | |||
| 933 | if (!fn(engine, a[i], b[i], wa->reg)) | ||
| 929 | err = -EINVAL; | 934 | err = -EINVAL; |
| 930 | } | 935 | } |
| 931 | 936 | ||
| @@ -2674,11 +2674,6 @@ static int scan_workload(struct intel_vgpu_workload *workload) · 2673 unmodified lines | |||
| 2674 | gma_head == gma_tail) | 2674 | gma_head == gma_tail) |
| 2675 | return 0; | 2675 | return 0; |
| 2676 | 2676 | ||
| 2677 | if (!intel_gvt_ggtt_validate_range(s.vgpu, s.ring_start, s.ring_size)) { | ||
| 2678 | ret = -EINVAL; | ||
| 2679 | goto out; | ||
| 2680 | } | ||
| 2681 | |||
| 2682 | ret = ip_gma_set(&s, gma_head); | 2677 | ret = ip_gma_set(&s, gma_head); |
| 2683 | if (ret) | 2678 | if (ret) |
| 2684 | goto out; | 2679 | goto out; |
| @@ -2724,11 +2719,6 @@ static int scan_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx) · 39 unmodified lines | |||
| 2724 | s.workload = workload; | 2719 | s.workload = workload; |
| 2725 | s.is_ctx_wa = true; | 2720 | s.is_ctx_wa = true; |
| 2726 | 2721 | ||
| 2727 | if (!intel_gvt_ggtt_validate_range(s.vgpu, s.ring_start, s.ring_size)) { | ||
| 2728 | ret = -EINVAL; | ||
| 2729 | goto out; | ||
| 2730 | } | ||
| 2731 | |||
| 2732 | ret = ip_gma_set(&s, gma_head); | 2722 | ret = ip_gma_set(&s, gma_head); |
| 2733 | if (ret) | 2723 | if (ret) |
| 2734 | goto out; | 2724 | goto out; |
| @@ -245,7 +245,7 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu, · 244 unmodified lines | |||
| 245 | plane->hw_format = fmt; | 245 | plane->hw_format = fmt; |
| 246 | 246 | ||
| 247 | plane->base = vgpu_vreg_t(vgpu, DSPSURF(pipe)) & I915_GTT_PAGE_MASK; | 247 | plane->base = vgpu_vreg_t(vgpu, DSPSURF(pipe)) & I915_GTT_PAGE_MASK; |
| 248 | if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0)) | 248 | if (!vgpu_gmadr_is_valid(vgpu, plane->base)) |
| 249 | return -EINVAL; | 249 | return -EINVAL; |
| 250 | 250 | ||
| 251 | plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base); | 251 | plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base); |
| @@ -368,7 +368,7 @@ int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu, · 116 unmodified lines | |||
| 368 | alpha_plane, alpha_force); | 368 | alpha_plane, alpha_force); |
| 369 | 369 | ||
| 370 | plane->base = vgpu_vreg_t(vgpu, CURBASE(pipe)) & I915_GTT_PAGE_MASK; | 370 | plane->base = vgpu_vreg_t(vgpu, CURBASE(pipe)) & I915_GTT_PAGE_MASK; |
| 371 | if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0)) | 371 | if (!vgpu_gmadr_is_valid(vgpu, plane->base)) |
| 372 | return -EINVAL; | 372 | return -EINVAL; |
| 373 | 373 | ||
| 374 | plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base); | 374 | plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base); |
| @@ -472,7 +472,7 @@ int intel_vgpu_decode_sprite_plane(struct intel_vgpu *vgpu, · 97 unmodified lines | |||
| 472 | plane->drm_format = drm_format; | 472 | plane->drm_format = drm_format; |
| 473 | 473 | ||
| 474 | plane->base = vgpu_vreg_t(vgpu, SPRSURF(pipe)) & I915_GTT_PAGE_MASK; | 474 | plane->base = vgpu_vreg_t(vgpu, SPRSURF(pipe)) & I915_GTT_PAGE_MASK; |
| 475 | if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0)) | 475 | if (!vgpu_gmadr_is_valid(vgpu, plane->base)) |
| 476 | return -EINVAL; | 476 | return -EINVAL; |
| 477 | 477 | ||
| 478 | plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base); | 478 | plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base); |
| @@ -2141,11 +2141,20 @@ static int emulate_ggtt_mmio_read(struct intel_vgpu *vgpu, · 2140 unmodified lines | |||
| 2141 | struct intel_vgpu_mm *ggtt_mm = vgpu->gtt.ggtt_mm; | 2141 | struct intel_vgpu_mm *ggtt_mm = vgpu->gtt.ggtt_mm; |
| 2142 | const struct intel_gvt_device_info *info = &vgpu->gvt->device_info; | 2142 | const struct intel_gvt_device_info *info = &vgpu->gvt->device_info; |
| 2143 | unsigned long index = off >> info->gtt_entry_size_shift; | 2143 | unsigned long index = off >> info->gtt_entry_size_shift; |
| 2144 | unsigned long gma; | ||
| 2144 | struct intel_gvt_gtt_entry e; | 2145 | struct intel_gvt_gtt_entry e; |
| 2145 | 2146 | ||
| 2146 | if (bytes != 4 && bytes != 8) | 2147 | if (bytes != 4 && bytes != 8) |
| 2147 | return -EINVAL; | 2148 | return -EINVAL; |
| 2148 | 2149 | ||
| 2150 | gma = index << I915_GTT_PAGE_SHIFT; | ||
| 2151 | if (!intel_gvt_ggtt_validate_range(vgpu, | ||
| 2152 | gma, 1 << I915_GTT_PAGE_SHIFT)) { | ||
| 2153 | gvt_dbg_mm("read invalid ggtt at 0x%lx\n", gma); | ||
| 2154 | memset(p_data, 0, bytes); | ||
| 2155 | return 0; | ||
| 2156 | } | ||
| 2157 | |||
| 2149 | ggtt_get_guest_entry(ggtt_mm, &e, index); | 2158 | ggtt_get_guest_entry(ggtt_mm, &e, index); |
| 2150 | memcpy(p_data, (void *)&e.val64 + (off & (info->gtt_entry_size - 1)), | 2159 | memcpy(p_data, (void *)&e.val64 + (off & (info->gtt_entry_size - 1)), |
| 2151 | bytes); | 2160 | bytes); |
| @@ -1904,6 +1904,18 @@ static int kvmgt_dma_map_guest_page(unsigned long handle, unsigned long gfn, · 1903 unmodified lines | |||
| 1904 | 1904 | ||
| 1905 | entry = __gvt_cache_find_gfn(info->vgpu, gfn); | 1905 | entry = __gvt_cache_find_gfn(info->vgpu, gfn); |
| 1906 | if (!entry) { | 1906 | if (!entry) { |
| 1907 | ret = gvt_dma_map_page(vgpu, gfn, dma_addr, size); | ||
| 1908 | if (ret) | ||
| 1909 | goto err_unlock; | ||
| 1910 | |||
| 1911 | ret = __gvt_cache_add(info->vgpu, gfn, *dma_addr, size); | ||
| 1912 | if (ret) | ||
| 1913 | goto err_unmap; | ||
| 1914 | } else if (entry->size != size) { | ||
| 1915 | /* the same gfn with different size: unmap and re-map */ | ||
| 1916 | gvt_dma_unmap_page(vgpu, gfn, entry->dma_addr, entry->size); | ||
| 1917 | __gvt_cache_remove_entry(vgpu, entry); | ||
| 1918 | |||
| 1907 | ret = gvt_dma_map_page(vgpu, gfn, dma_addr, size); | 1919 | ret = gvt_dma_map_page(vgpu, gfn, dma_addr, size); |
| 1908 | if (ret) | 1920 | if (ret) |
| 1909 | goto err_unlock; | 1921 | goto err_unlock; |
| @@ -364,16 +364,13 @@ static void release_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx) · 363 unmodified lines | |||
| 364 | wa_ctx->indirect_ctx.shadow_va = NULL; | 364 | wa_ctx->indirect_ctx.shadow_va = NULL; |
| 365 | } | 365 | } |
| 366 | 366 | ||
| 367 | static int set_context_ppgtt_from_shadow(struct intel_vgpu_workload *workload, | 367 | static void set_context_ppgtt_from_shadow(struct intel_vgpu_workload *workload, |
| 368 | struct i915_gem_context *ctx) | 368 | struct i915_gem_context *ctx) |
| 369 | { | 369 | { |
| 370 | struct intel_vgpu_mm *mm = workload->shadow_mm; | 370 | struct intel_vgpu_mm *mm = workload->shadow_mm; |
| 371 | struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(ctx->vm); | 371 | struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(ctx->vm); |
| 372 | int i = 0; | 372 | int i = 0; |
| 373 | 373 | ||
| 374 | if (mm->type != INTEL_GVT_MM_PPGTT || !mm->ppgtt_mm.shadowed) | ||
| 375 | return -EINVAL; | ||
| 376 | |||
| 377 | if (mm->ppgtt_mm.root_entry_type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY) { | 374 | if (mm->ppgtt_mm.root_entry_type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY) { |
| 378 | px_dma(ppgtt->pd) = mm->ppgtt_mm.shadow_pdps[0]; | 375 | px_dma(ppgtt->pd) = mm->ppgtt_mm.shadow_pdps[0]; |
| 379 | } else { | 376 | } else { |
| @@ -384,8 +381,6 @@ static int set_context_ppgtt_from_shadow(struct intel_vgpu_workload *workload, · 4 unmodified lines | |||
| 384 | px_dma(pd) = mm->ppgtt_mm.shadow_pdps[i]; | 381 | px_dma(pd) = mm->ppgtt_mm.shadow_pdps[i]; |
| 385 | } | 382 | } |
| 386 | } | 383 | } |
| 387 | |||
| 388 | return 0; | ||
| 389 | } | 384 | } |
| 390 | 385 | ||
| 391 | static int | 386 | static int |
| @@ -614,6 +609,8 @@ static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload) · 222 unmodified lines | |||
| 614 | static int prepare_workload(struct intel_vgpu_workload *workload) | 609 | static int prepare_workload(struct intel_vgpu_workload *workload) |
| 615 | { | 610 | { |
| 616 | struct intel_vgpu *vgpu = workload->vgpu; | 611 | struct intel_vgpu *vgpu = workload->vgpu; |
| 612 | struct intel_vgpu_submission *s = &vgpu->submission; | ||
| 613 | int ring = workload->ring_id; | ||
| 617 | int ret = 0; | 614 | int ret = 0; |
| 618 | 615 | ||
| 619 | ret = intel_vgpu_pin_mm(workload->shadow_mm); | 616 | ret = intel_vgpu_pin_mm(workload->shadow_mm); |
| @@ -622,8 +619,16 @@ static int prepare_workload(struct intel_vgpu_workload *workload) · 2 unmodified lines | |||
| 622 | return ret; | 619 | return ret; |
| 623 | } | 620 | } |
| 624 | 621 | ||
| 622 | if (workload->shadow_mm->type != INTEL_GVT_MM_PPGTT || | ||
| 623 | !workload->shadow_mm->ppgtt_mm.shadowed) { | ||
| 624 | gvt_vgpu_err("workload shadow ppgtt isn't ready\n"); | ||
| 625 | return -EINVAL; | ||
| 626 | } | ||
| 627 | |||
| 625 | update_shadow_pdps(workload); | 628 | update_shadow_pdps(workload); |
| 626 | 629 | ||
| 630 | set_context_ppgtt_from_shadow(workload, s->shadow[ring]->gem_context); | ||
| 631 | |||
| 627 | ret = intel_vgpu_sync_oos_pages(workload->vgpu); | 632 | ret = intel_vgpu_sync_oos_pages(workload->vgpu); |
| 628 | if (ret) { | 633 | if (ret) { |
| 629 | gvt_vgpu_err("fail to vgpu sync oos pages\n"); | 634 | gvt_vgpu_err("fail to vgpu sync oos pages\n"); |
| @@ -674,7 +679,6 @@ static int dispatch_workload(struct intel_vgpu_workload *workload) · 44 unmodified lines | |||
| 674 | { | 679 | { |
| 675 | struct intel_vgpu *vgpu = workload->vgpu; | 680 | struct intel_vgpu *vgpu = workload->vgpu; |
| 676 | struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; | 681 | struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; |
| 677 | struct intel_vgpu_submission *s = &vgpu->submission; | ||
| 678 | struct i915_request *rq; | 682 | struct i915_request *rq; |
| 679 | int ring_id = workload->ring_id; | 683 | int ring_id = workload->ring_id; |
| 680 | int ret; | 684 | int ret; |
| @@ -685,13 +689,6 @@ static int dispatch_workload(struct intel_vgpu_workload *workload) · 4 unmodified lines | |||
| 685 | mutex_lock(&vgpu->vgpu_lock); | 689 | mutex_lock(&vgpu->vgpu_lock); |
| 686 | mutex_lock(&dev_priv->drm.struct_mutex); | 690 | mutex_lock(&dev_priv->drm.struct_mutex); |
| 687 | 691 | ||
| 688 | ret = set_context_ppgtt_from_shadow(workload, | ||
| 689 | s->shadow[ring_id]->gem_context); | ||
| 690 | if (ret < 0) { | ||
| 691 | gvt_vgpu_err("workload shadow ppgtt isn't ready\n"); | ||
| 692 | goto err_req; | ||
| 693 | } | ||
| 694 | |||
| 695 | ret = intel_gvt_workload_req_alloc(workload); | 692 | ret = intel_gvt_workload_req_alloc(workload); |
| 696 | if (ret) | 693 | if (ret) |
| 697 | goto err_req; | 694 | goto err_req; |
| @@ -990,6 +987,7 @@ static int workload_thread(void *priv) · 292 unmodified lines | |||
| 990 | int ret; | 987 | int ret; |
| 991 | bool need_force_wake = (INTEL_GEN(gvt->dev_priv) >= 9); | 988 | bool need_force_wake = (INTEL_GEN(gvt->dev_priv) >= 9); |
| 992 | DEFINE_WAIT_FUNC(wait, woken_wake_function); | 989 | DEFINE_WAIT_FUNC(wait, woken_wake_function); |
| 990 | struct intel_runtime_pm *rpm = &gvt->dev_priv->runtime_pm; | ||
| 993 | 991 | ||
| 994 | kfree(p); | 992 | kfree(p); |
| 995 | 993 | ||
| @@ -1013,6 +1011,8 @@ static int workload_thread(void *priv) · 17 unmodified lines | |||
| 1013 | workload->ring_id, workload, | 1011 | workload->ring_id, workload, |
| 1014 | workload->vgpu->id); | 1012 | workload->vgpu->id); |
| 1015 | 1013 | ||
| 1014 | intel_runtime_pm_get(rpm); | ||
| 1015 | |||
| 1016 | gvt_dbg_sched("ring id %d will dispatch workload %p\n", | 1016 | gvt_dbg_sched("ring id %d will dispatch workload %p\n", |
| 1017 | workload->ring_id, workload); | 1017 | workload->ring_id, workload); |
| 1018 | 1018 | ||
| @@ -1042,6 +1042,7 @@ complete: · 23 unmodified lines | |||
| 1042 | intel_uncore_forcewake_put(&gvt->dev_priv->uncore, | 1042 | intel_uncore_forcewake_put(&gvt->dev_priv->uncore, |
| 1043 | FORCEWAKE_ALL); | 1043 | FORCEWAKE_ALL); |
| 1044 | 1044 | ||
| 1045 | intel_runtime_pm_put_unchecked(rpm); | ||
| 1045 | if (ret && (vgpu_is_vm_unhealthy(ret))) | 1046 | if (ret && (vgpu_is_vm_unhealthy(ret))) |
| 1046 | enter_failsafe_mode(vgpu, GVT_FAILSAFE_GUEST_ERR); | 1047 | enter_failsafe_mode(vgpu, GVT_FAILSAFE_GUEST_ERR); |
| 1047 | } | 1048 | } |
| @@ -1492,6 +1493,12 @@ intel_vgpu_create_workload(struct intel_vgpu *vgpu, int ring_id, · 444 unmodified lines | |||
| 1492 | intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa + | 1493 | intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa + |
| 1493 | RING_CTX_OFF(ctx_ctrl.val), &ctx_ctl, 4); | 1494 | RING_CTX_OFF(ctx_ctrl.val), &ctx_ctl, 4); |
| 1494 | 1495 | ||
| 1496 | if (!intel_gvt_ggtt_validate_range(vgpu, start, | ||
| 1497 | _RING_CTL_BUF_SIZE(ctl))) { | ||
| 1498 | gvt_vgpu_err("context contain invalid rb at: 0x%x\n", start); | ||
| 1499 | return ERR_PTR(-EINVAL); | ||
| 1500 | } | ||
| 1501 | |||
| 1495 | workload = alloc_workload(vgpu); | 1502 | workload = alloc_workload(vgpu); |
| 1496 | if (IS_ERR(workload)) | 1503 | if (IS_ERR(workload)) |
| 1497 | return workload; | 1504 | return workload; |
| @@ -1516,9 +1523,31 @@ intel_vgpu_create_workload(struct intel_vgpu *vgpu, int ring_id, · 18 unmodified lines | |||
| 1516 | workload->wa_ctx.indirect_ctx.size = | 1523 | workload->wa_ctx.indirect_ctx.size = |
| 1517 | (indirect_ctx & INDIRECT_CTX_SIZE_MASK) * | 1524 | (indirect_ctx & INDIRECT_CTX_SIZE_MASK) * |
| 1518 | CACHELINE_BYTES; | 1525 | CACHELINE_BYTES; |
| 1526 | |||
| 1527 | if (workload->wa_ctx.indirect_ctx.size != 0) { | ||
| 1528 | if (!intel_gvt_ggtt_validate_range(vgpu, | ||
| 1529 | workload->wa_ctx.indirect_ctx.guest_gma, | ||
| 1530 | workload->wa_ctx.indirect_ctx.size)) { | ||
| 1531 | gvt_vgpu_err("invalid wa_ctx at: 0x%lx\n", | ||
| 1532 | workload->wa_ctx.indirect_ctx.guest_gma); | ||
| 1533 | kmem_cache_free(s->workloads, workload); | ||
| 1534 | return ERR_PTR(-EINVAL); | ||
| 1535 | } | ||
| 1536 | } | ||
| 1537 | |||
| 1519 | workload->wa_ctx.per_ctx.guest_gma = | 1538 | workload->wa_ctx.per_ctx.guest_gma = |
| 1520 | per_ctx & PER_CTX_ADDR_MASK; | 1539 | per_ctx & PER_CTX_ADDR_MASK; |
| 1521 | workload->wa_ctx.per_ctx.valid = per_ctx & 1; | 1540 | workload->wa_ctx.per_ctx.valid = per_ctx & 1; |
| 1541 | if (workload->wa_ctx.per_ctx.valid) { | ||
| 1542 | if (!intel_gvt_ggtt_validate_range(vgpu, | ||
| 1543 | workload->wa_ctx.per_ctx.guest_gma, | ||
| 1544 | CACHELINE_BYTES)) { | ||
| 1545 | gvt_vgpu_err("invalid per_ctx at: 0x%lx\n", | ||
| 1546 | workload->wa_ctx.per_ctx.guest_gma); | ||
| 1547 | kmem_cache_free(s->workloads, workload); | ||
| 1548 | return ERR_PTR(-EINVAL); | ||
| 1549 | } | ||
| 1550 | } | ||
| 1522 | } | 1551 | } |
| 1523 | 1552 | ||
| 1524 | gvt_dbg_el("workload %p ring id %d head %x tail %x start %x ctl %x\n", | 1553 | gvt_dbg_el("workload %p ring id %d head %x tail %x start %x ctl %x\n", |
| @@ -28,8 +28,6 @@ · 27 unmodified lines | |||
| 28 | * | 28 | * |
| 29 | */ | 29 | */ |
| 30 | 30 | ||
| 31 | #include "trace.h" | ||
| 32 | |||
| 33 | #ifndef __CHECKER__ | 31 | #ifndef __CHECKER__ |
| 34 | #define CREATE_TRACE_POINTS | 32 | #define CREATE_TRACE_POINTS |
| 35 | #include "trace.h" | 33 | #include "trace.h" |
| @@ -1674,8 +1674,9 @@ struct drm_i915_private { · 1673 unmodified lines | |||
| 1674 | } dram_info; | 1674 | } dram_info; |
| 1675 | 1675 | ||
| 1676 | struct intel_bw_info { | 1676 | struct intel_bw_info { |
| 1677 | int num_planes; | 1677 | unsigned int deratedbw[3]; /* for each QGV point */ |
| 1678 | int deratedbw[3]; | 1678 | u8 num_qgv_points; |
| 1679 | u8 num_planes; | ||
| 1679 | } max_bw[6]; | 1680 | } max_bw[6]; |
| 1680 | 1681 | ||
| 1681 | struct drm_private_obj bw_obj; | 1682 | struct drm_private_obj bw_obj; |
| @@ -46,7 +46,6 @@ · 45 unmodified lines | |||
| 46 | #include "gem/i915_gem_ioctls.h" | 46 | #include "gem/i915_gem_ioctls.h" |
| 47 | #include "gem/i915_gem_pm.h" | 47 | #include "gem/i915_gem_pm.h" |
| 48 | #include "gem/i915_gemfs.h" | 48 | #include "gem/i915_gemfs.h" |
| 49 | #include "gt/intel_engine_pm.h" | ||
| 50 | #include "gt/intel_gt_pm.h" | 49 | #include "gt/intel_gt_pm.h" |
| 51 | #include "gt/intel_mocs.h" | 50 | #include "gt/intel_mocs.h" |
| 52 | #include "gt/intel_reset.h" | 51 | #include "gt/intel_reset.h" |
| @@ -1307,21 +1306,13 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv) · 1254 unmodified lines | |||
| 1307 | 1306 | ||
| 1308 | intel_mocs_init_l3cc_table(dev_priv); | 1307 | intel_mocs_init_l3cc_table(dev_priv); |
| 1309 | 1308 | ||
| 1310 | /* Only when the HW is re-initialised, can we replay the requests */ | ||
| 1311 | ret = intel_engines_resume(dev_priv); | ||
| 1312 | if (ret) | ||
| 1313 | goto cleanup_uc; | ||
| 1314 | |||
| 1315 | intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); | 1309 | intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); |
| 1316 | 1310 | ||
| 1317 | intel_engines_set_scheduler_caps(dev_priv); | 1311 | intel_engines_set_scheduler_caps(dev_priv); |
| 1318 | return 0; | 1312 | return 0; |
| 1319 | 1313 | ||
| 1320 | cleanup_uc: | ||
| 1321 | intel_uc_fini_hw(dev_priv); | ||
| 1322 | out: | 1314 | out: |
| 1323 | intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); | 1315 | intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); |
| 1324 | |||
| 1325 | return ret; | 1316 | return ret; |
| 1326 | } | 1317 | } |
| 1327 | 1318 | ||
| @@ -1580,6 +1571,11 @@ int i915_gem_init(struct drm_i915_private *dev_priv) · 252 unmodified lines | |||
| 1580 | if (ret) | 1571 | if (ret) |
| 1581 | goto err_uc_init; | 1572 | goto err_uc_init; |
| 1582 | 1573 | ||
| 1574 | /* Only when the HW is re-initialised, can we replay the requests */ | ||
| 1575 | ret = intel_gt_resume(dev_priv); | ||
| 1576 | if (ret) | ||
| 1577 | goto err_init_hw; | ||
| 1578 | |||
| 1583 | /* | 1579 | /* |
| 1584 | * Despite its name intel_init_clock_gating applies both display | 1580 | * Despite its name intel_init_clock_gating applies both display |
| 1585 | * clock gating workarounds; GT mmio workarounds and the occasional | 1581 | * clock gating workarounds; GT mmio workarounds and the occasional |
| @@ -1593,20 +1589,20 @@ int i915_gem_init(struct drm_i915_private *dev_priv) · 7 unmodified lines | |||
| 1593 | 1589 | ||
| 1594 | ret = intel_engines_verify_workarounds(dev_priv); | 1590 | ret = intel_engines_verify_workarounds(dev_priv); |
| 1595 | if (ret) | 1591 | if (ret) |
| 1596 | goto err_init_hw; | 1592 | goto err_gt; |
| 1597 | 1593 | ||
| 1598 | ret = __intel_engines_record_defaults(dev_priv); | 1594 | ret = __intel_engines_record_defaults(dev_priv); |
| 1599 | if (ret) | 1595 | if (ret) |
| 1600 | goto err_init_hw; | 1596 | goto err_gt; |
| 1601 | 1597 | ||
| 1602 | if (i915_inject_load_failure()) { | 1598 | if (i915_inject_load_failure()) { |
| 1603 | ret = -ENODEV; | 1599 | ret = -ENODEV; |
| 1604 | goto err_init_hw; | 1600 | goto err_gt; |
| 1605 | } | 1601 | } |
| 1606 | 1602 | ||
| 1607 | if (i915_inject_load_failure()) { | 1603 | if (i915_inject_load_failure()) { |
| 1608 | ret = -EIO; | 1604 | ret = -EIO; |
| 1609 | goto err_init_hw; | 1605 | goto err_gt; |
| 1610 | } | 1606 | } |
| 1611 | 1607 | ||
| 1612 | intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); | 1608 | intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); |
| @@ -1620,7 +1616,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv) · 7 unmodified lines | |||
| 1620 | * HW as irrevisibly wedged, but keep enough state around that the | 1616 | * HW as irrevisibly wedged, but keep enough state around that the |
| 1621 | * driver doesn't explode during runtime. | 1617 | * driver doesn't explode during runtime. |
| 1622 | */ | 1618 | */ |
| 1623 | err_init_hw: | 1619 | err_gt: |
| 1624 | mutex_unlock(&dev_priv->drm.struct_mutex); | 1620 | mutex_unlock(&dev_priv->drm.struct_mutex); |
| 1625 | 1621 | ||
| 1626 | i915_gem_set_wedged(dev_priv); | 1622 | i915_gem_set_wedged(dev_priv); |
| @@ -1630,6 +1626,7 @@ err_init_hw: · 3 unmodified lines | |||
| 1630 | i915_gem_drain_workqueue(dev_priv); | 1626 | i915_gem_drain_workqueue(dev_priv); |
| 1631 | 1627 | ||
| 1632 | mutex_lock(&dev_priv->drm.struct_mutex); | 1628 | mutex_lock(&dev_priv->drm.struct_mutex); |
| 1629 | err_init_hw: | ||
| 1633 | intel_uc_fini_hw(dev_priv); | 1630 | intel_uc_fini_hw(dev_priv); |
| 1634 | err_uc_init: | 1631 | err_uc_init: |
| 1635 | intel_uc_fini(dev_priv); | 1632 | intel_uc_fini(dev_priv); |
| @@ -1444,9 +1444,11 @@ unwind_pd: · 1443 unmodified lines | |||
| 1444 | spin_lock(&pdp->lock); | 1444 | spin_lock(&pdp->lock); |
| 1445 | if (atomic_dec_and_test(&pd->used)) { | 1445 | if (atomic_dec_and_test(&pd->used)) { |
| 1446 | gen8_ppgtt_set_pdpe(pdp, vm->scratch_pd, pdpe); | 1446 | gen8_ppgtt_set_pdpe(pdp, vm->scratch_pd, pdpe); |
| 1447 | pdp->entry[pdpe] = vm->scratch_pd; | ||
| 1447 | GEM_BUG_ON(!atomic_read(&pdp->used)); | 1448 | GEM_BUG_ON(!atomic_read(&pdp->used)); |
| 1448 | atomic_dec(&pdp->used); | 1449 | atomic_dec(&pdp->used); |
| 1449 | free_pd(vm, pd); | 1450 | GEM_BUG_ON(alloc); |
| 1451 | alloc = pd; /* defer the free to after the lock */ | ||
| 1450 | } | 1452 | } |
| 1451 | spin_unlock(&pdp->lock); | 1453 | spin_unlock(&pdp->lock); |
| 1452 | unwind: | 1454 | unwind: |
| @@ -1515,7 +1517,9 @@ unwind_pdp: · 62 unmodified lines | |||
| 1515 | spin_lock(&pml4->lock); | 1517 | spin_lock(&pml4->lock); |
| 1516 | if (atomic_dec_and_test(&pdp->used)) { | 1518 | if (atomic_dec_and_test(&pdp->used)) { |
| 1517 | gen8_ppgtt_set_pml4e(pml4, vm->scratch_pdp, pml4e); | 1519 | gen8_ppgtt_set_pml4e(pml4, vm->scratch_pdp, pml4e); |
| 1518 | free_pd(vm, pdp); | 1520 | pml4->entry[pml4e] = vm->scratch_pdp; |
| 1521 | GEM_BUG_ON(alloc); | ||
| 1522 | alloc = pdp; /* defer the free until after the lock */ | ||
| 1519 | } | 1523 | } |
| 1520 | spin_unlock(&pml4->lock); | 1524 | spin_unlock(&pml4->lock); |
| 1521 | unwind: | 1525 | unwind: |
| @@ -1194,6 +1194,7 @@ static void error_record_engine_registers(struct i915_gpu_state *error, · 1193 unmodified lines | |||
| 1194 | switch (engine->id) { | 1194 | switch (engine->id) { |
| 1195 | default: | 1195 | default: |
| 1196 | MISSING_CASE(engine->id); | 1196 | MISSING_CASE(engine->id); |
| 1197 | /* fall through */ | ||
| 1197 | case RCS0: | 1198 | case RCS0: |
| 1198 | mmio = RENDER_HWS_PGA_GEN7; | 1199 | mmio = RENDER_HWS_PGA_GEN7; |
| 1199 | break; | 1200 | break; |
| @@ -1417,6 +1418,7 @@ static void gem_record_rings(struct i915_gpu_state *error) · 217 unmodified lines | |||
| 1417 | struct intel_engine_cs *engine = i915->engine[i]; | 1418 | struct intel_engine_cs *engine = i915->engine[i]; |
| 1418 | struct drm_i915_error_engine *ee = &error->engine[i]; | 1419 | struct drm_i915_error_engine *ee = &error->engine[i]; |
| 1419 | struct i915_request *request; | 1420 | struct i915_request *request; |
| 1421 | unsigned long flags; | ||
| 1420 | 1422 | ||
| 1421 | ee->engine_id = -1; | 1423 | ee->engine_id = -1; |
| 1422 | 1424 | ||
| @@ -1428,10 +1430,11 @@ static void gem_record_rings(struct i915_gpu_state *error) · 5 unmodified lines | |||
| 1428 | error_record_engine_registers(error, engine, ee); | 1430 | error_record_engine_registers(error, engine, ee); |
| 1429 | error_record_engine_execlists(engine, ee); | 1431 | error_record_engine_execlists(engine, ee); |
| 1430 | 1432 | ||
| 1433 | spin_lock_irqsave(&engine->active.lock, flags); | ||
| 1431 | request = intel_engine_find_active_request(engine); | 1434 | request = intel_engine_find_active_request(engine); |
| 1432 | if (request) { | 1435 | if (request) { |
| 1433 | struct i915_gem_context *ctx = request->gem_context; | 1436 | struct i915_gem_context *ctx = request->gem_context; |
| 1434 | struct intel_ring *ring; | 1437 | struct intel_ring *ring = request->ring; |
| 1435 | 1438 | ||
| 1436 | ee->vm = ctx->vm ?: &ggtt->vm; | 1439 | ee->vm = ctx->vm ?: &ggtt->vm; |
| 1437 | 1440 | ||
| @@ -1461,7 +1464,6 @@ static void gem_record_rings(struct i915_gpu_state *error) · 23 unmodified lines | |||
| 1461 | ee->rq_post = request->postfix; | 1464 | ee->rq_post = request->postfix; |
| 1462 | ee->rq_tail = request->tail; | 1465 | ee->rq_tail = request->tail; |
| 1463 | 1466 | ||
| 1464 | ring = request->ring; | ||
| 1465 | ee->cpu_ring_head = ring->head; | 1467 | ee->cpu_ring_head = ring->head; |
| 1466 | ee->cpu_ring_tail = ring->tail; | 1468 | ee->cpu_ring_tail = ring->tail; |
| 1467 | ee->ringbuffer = | 1469 | ee->ringbuffer = |
| @@ -1469,6 +1471,7 @@ static void gem_record_rings(struct i915_gpu_state *error) · 1 unmodified line | |||
| 1469 | 1471 | ||
| 1470 | engine_record_requests(engine, request, ee); | 1472 | engine_record_requests(engine, request, ee); |
| 1471 | } | 1473 | } |
| 1474 | spin_unlock_irqrestore(&engine->active.lock, flags); | ||
| 1472 | 1475 | ||
| 1473 | ee->hws_page = | 1476 | ee->hws_page = |
| 1474 | i915_error_object_create(i915, | 1477 | i915_error_object_create(i915, |
| @@ -1567,28 +1567,10 @@ static void config_oa_regs(struct drm_i915_private *dev_priv, · 1566 unmodified lines | |||
| 1567 | } | 1567 | } |
| 1568 | } | 1568 | } |
| 1569 | 1569 | ||
| 1570 | static int hsw_enable_metric_set(struct i915_perf_stream *stream) | 1570 | static void delay_after_mux(void) |
| 1571 | { | 1571 | { |
| 1572 | struct drm_i915_private *dev_priv = stream->dev_priv; | 1572 | /* |
| 1573 | const struct i915_oa_config *oa_config = stream->oa_config; | 1573 | * It apparently takes a fairly long time for a new MUX |
| 1574 | |||
| 1575 | /* PRM: | ||
| 1576 | * | ||
| 1577 | * OA unit is using “crclk” for its functionality. When trunk | ||
| 1578 | * level clock gating takes place, OA clock would be gated, | ||
| 1579 | * unable to count the events from non-render clock domain. | ||
| 1580 | * Render clock gating must be disabled when OA is enabled to | ||
| 1581 | * count the events from non-render domain. Unit level clock | ||
| 1582 | * gating for RCS should also be disabled. | ||
| 1583 | */ | ||
| 1584 | I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) & | ||
| 1585 | ~GEN7_DOP_CLOCK_GATE_ENABLE)); | ||
| 1586 | I915_WRITE(GEN6_UCGCTL1, (I915_READ(GEN6_UCGCTL1) | | ||
| 1587 | GEN6_CSUNIT_CLOCK_GATE_DISABLE)); | ||
| 1588 | |||
| 1589 | config_oa_regs(dev_priv, oa_config->mux_regs, oa_config->mux_regs_len); | ||
| 1590 | |||
| 1591 | /* It apparently takes a fairly long time for a new MUX | ||
| 1592 | * configuration to be be applied after these register writes. | 1574 | * configuration to be be applied after these register writes. |
| 1593 | * This delay duration was derived empirically based on the | 1575 | * This delay duration was derived empirically based on the |
| 1594 | * render_basic config but hopefully it covers the maximum | 1576 | * render_basic config but hopefully it covers the maximum |
| @@ -1610,6 +1592,30 @@ static int hsw_enable_metric_set(struct i915_perf_stream *stream) · 15 unmodified lines | |||
| 1610 | * a delay at this location would mitigate any invalid reports. | 1592 | * a delay at this location would mitigate any invalid reports. |
| 1611 | */ | 1593 | */ |
| 1612 | usleep_range(15000, 20000); | 1594 | usleep_range(15000, 20000); |
| 1595 | } | ||
| 1596 | |||
| 1597 | static int hsw_enable_metric_set(struct i915_perf_stream *stream) | ||
| 1598 | { | ||
| 1599 | struct drm_i915_private *dev_priv = stream->dev_priv; | ||
| 1600 | const struct i915_oa_config *oa_config = stream->oa_config; | ||
| 1601 | |||
| 1602 | /* | ||
| 1603 | * PRM: | ||
| 1604 | * | ||
| 1605 | * OA unit is using “crclk” for its functionality. When trunk | ||
| 1606 | * level clock gating takes place, OA clock would be gated, | ||
| 1607 | * unable to count the events from non-render clock domain. | ||
| 1608 | * Render clock gating must be disabled when OA is enabled to | ||
| 1609 | * count the events from non-render domain. Unit level clock | ||
| 1610 | * gating for RCS should also be disabled. | ||
| 1611 | */ | ||
| 1612 | I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) & | ||
| 1613 | ~GEN7_DOP_CLOCK_GATE_ENABLE)); | ||
| 1614 | I915_WRITE(GEN6_UCGCTL1, (I915_READ(GEN6_UCGCTL1) | | ||
| 1615 | GEN6_CSUNIT_CLOCK_GATE_DISABLE)); | ||
| 1616 | |||
| 1617 | config_oa_regs(dev_priv, oa_config->mux_regs, oa_config->mux_regs_len); | ||
| 1618 | delay_after_mux(); | ||
| 1613 | 1619 | ||
| 1614 | config_oa_regs(dev_priv, oa_config->b_counter_regs, | 1620 | config_oa_regs(dev_priv, oa_config->b_counter_regs, |
| 1615 | oa_config->b_counter_regs_len); | 1621 | oa_config->b_counter_regs_len); |
| @@ -1835,6 +1841,7 @@ static int gen8_enable_metric_set(struct i915_perf_stream *stream) · 219 unmodified lines | |||
| 1835 | return ret; | 1841 | return ret; |
| 1836 | 1842 | ||
| 1837 | config_oa_regs(dev_priv, oa_config->mux_regs, oa_config->mux_regs_len); | 1843 | config_oa_regs(dev_priv, oa_config->mux_regs, oa_config->mux_regs_len); |
| 1844 | delay_after_mux(); | ||
| 1838 | 1845 | ||
| 1839 | config_oa_regs(dev_priv, oa_config->b_counter_regs, | 1846 | config_oa_regs(dev_priv, oa_config->b_counter_regs, |
| 1840 | oa_config->b_counter_regs_len); | 1847 | oa_config->b_counter_regs_len); |
| @@ -2515,6 +2522,9 @@ static int i915_perf_release(struct inode *inode, struct file *file) · 674 unmodified lines | |||
| 2515 | i915_perf_destroy_locked(stream); | 2522 | i915_perf_destroy_locked(stream); |
| 2516 | mutex_unlock(&dev_priv->perf.lock); | 2523 | mutex_unlock(&dev_priv->perf.lock); |
| 2517 | 2524 | ||
| 2525 | /* Release the reference the perf stream kept on the driver. */ | ||
| 2526 | drm_dev_put(&dev_priv->drm); | ||
| 2527 | |||
| 2518 | return 0; | 2528 | return 0; |
| 2519 | } | 2529 | } |
| 2520 | 2530 | ||
| @@ -2650,6 +2660,11 @@ i915_perf_open_ioctl_locked(struct drm_i915_private *dev_priv, · 129 unmodified lines | |||
| 2650 | if (!(param->flags & I915_PERF_FLAG_DISABLED)) | 2660 | if (!(param->flags & I915_PERF_FLAG_DISABLED)) |
| 2651 | i915_perf_enable_locked(stream); | 2661 | i915_perf_enable_locked(stream); |
| 2652 | 2662 | ||
| 2663 | /* Take a reference on the driver that will be kept with stream_fd | ||
| 2664 | * until its release. | ||
| 2665 | */ | ||
| 2666 | drm_dev_get(&dev_priv->drm); | ||
| 2667 | |||
| 2653 | return stream_fd; | 2668 | return stream_fd; |
| 2654 | 2669 | ||
| 2655 | err_open: | 2670 | err_open: |
| @@ -3477,9 +3492,13 @@ void i915_perf_init(struct drm_i915_private *dev_priv) · 821 unmodified lines | |||
| 3477 | dev_priv->perf.oa.ops.enable_metric_set = gen8_enable_metric_set; | 3492 | dev_priv->perf.oa.ops.enable_metric_set = gen8_enable_metric_set; |
| 3478 | dev_priv->perf.oa.ops.disable_metric_set = gen10_disable_metric_set; | 3493 | dev_priv->perf.oa.ops.disable_metric_set = gen10_disable_metric_set; |
| 3479 | 3494 | ||
| 3480 | dev_priv->perf.oa.ctx_oactxctrl_offset = 0x128; | 3495 | if (IS_GEN(dev_priv, 10)) { |
| 3481 | dev_priv->perf.oa.ctx_flexeu0_offset = 0x3de; | 3496 | dev_priv->perf.oa.ctx_oactxctrl_offset = 0x128; |
| 3482 | 3497 | dev_priv->perf.oa.ctx_flexeu0_offset = 0x3de; | |
| 3498 | } else { | ||
| 3499 | dev_priv->perf.oa.ctx_oactxctrl_offset = 0x124; | ||
| 3500 | dev_priv->perf.oa.ctx_flexeu0_offset = 0x78e; | ||
| 3501 | } | ||
| 3483 | dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<16); | 3502 | dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<16); |
| 3484 | } | 3503 | } |
| 3485 | } | 3504 | } |
| @@ -21,24 +21,22 @@ · 20 unmodified lines | |||
| 21 | /* watermark/fifo updates */ | 21 | /* watermark/fifo updates */ |
| 22 | 22 | ||
| 23 | TRACE_EVENT(intel_pipe_enable, | 23 | TRACE_EVENT(intel_pipe_enable, |
| 24 | TP_PROTO(struct drm_i915_private *dev_priv, enum pipe pipe), | 24 | TP_PROTO(struct intel_crtc *crtc), |
| 25 | TP_ARGS(dev_priv, pipe), | 25 | TP_ARGS(crtc), |
| 26 | 26 | ||
| 27 | TP_STRUCT__entry( | 27 | TP_STRUCT__entry( |
| 28 | __array(u32, frame, 3) | 28 | __array(u32, frame, 3) |
| 29 | __array(u32, scanline, 3) | 29 | __array(u32, scanline, 3) |
| 30 | __field(enum pipe, pipe) | 30 | __field(enum pipe, pipe) |
| 31 | ), | 31 | ), |
| 32 | |||
| 33 | TP_fast_assign( | 32 | TP_fast_assign( |
| 34 | enum pipe _pipe; | 33 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
| 35 | for_each_pipe(dev_priv, _pipe) { | 34 | struct intel_crtc *it__; |
| 36 | __entry->frame[_pipe] = | 35 | for_each_intel_crtc(&dev_priv->drm, it__) { |
| 37 | dev_priv->drm.driver->get_vblank_counter(&dev_priv->drm, _pipe); | 36 | __entry->frame[it__->pipe] = intel_crtc_get_vblank_counter(it__); |
| 38 | __entry->scanline[_pipe] = | 37 | __entry->scanline[it__->pipe] = intel_get_crtc_scanline(it__); |
| 39 | intel_get_crtc_scanline(intel_get_crtc_for_pipe(dev_priv, _pipe)); | ||
| 40 | } | 38 | } |
| 41 | __entry->pipe = pipe; | 39 | __entry->pipe = crtc->pipe; |
| 42 | ), | 40 | ), |
| 43 | 41 | ||
| 44 | TP_printk("pipe %c enable, pipe A: frame=%u, scanline=%u, pipe B: frame=%u, scanline=%u, pipe C: frame=%u, scanline=%u", | 42 | TP_printk("pipe %c enable, pipe A: frame=%u, scanline=%u, pipe B: frame=%u, scanline=%u, pipe C: frame=%u, scanline=%u", |
| @@ -49,8 +47,8 @@ TRACE_EVENT(intel_pipe_enable, · 4 unmodified lines | |||
| 49 | ); | 47 | ); |
| 50 | 48 | ||
| 51 | TRACE_EVENT(intel_pipe_disable, | 49 | TRACE_EVENT(intel_pipe_disable, |
| 52 | TP_PROTO(struct drm_i915_private *dev_priv, enum pipe pipe), | 50 | TP_PROTO(struct intel_crtc *crtc), |
| 53 | TP_ARGS(dev_priv, pipe), | 51 | TP_ARGS(crtc), |
| 54 | 52 | ||
| 55 | TP_STRUCT__entry( | 53 | TP_STRUCT__entry( |
| 56 | __array(u32, frame, 3) | 54 | __array(u32, frame, 3) |
| @@ -59,14 +57,13 @@ TRACE_EVENT(intel_pipe_disable, · 2 unmodified lines | |||
| 59 | ), | 57 | ), |
| 60 | 58 | ||
| 61 | TP_fast_assign( | 59 | TP_fast_assign( |
| 62 | enum pipe _pipe; | 60 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
| 63 | for_each_pipe(dev_priv, _pipe) { | 61 | struct intel_crtc *it__; |
| 64 | __entry->frame[_pipe] = | 62 | for_each_intel_crtc(&dev_priv->drm, it__) { |
| 65 | dev_priv->drm.driver->get_vblank_counter(&dev_priv->drm, _pipe); | 63 | __entry->frame[it__->pipe] = intel_crtc_get_vblank_counter(it__); |
| 66 | __entry->scanline[_pipe] = | 64 | __entry->scanline[it__->pipe] = intel_get_crtc_scanline(it__); |
| 67 | intel_get_crtc_scanline(intel_get_crtc_for_pipe(dev_priv, _pipe)); | ||
| 68 | } | 65 | } |
| 69 | __entry->pipe = pipe; | 66 | __entry->pipe = crtc->pipe; |
| 70 | ), | 67 | ), |
| 71 | 68 | ||
| 72 | TP_printk("pipe %c disable, pipe A: frame=%u, scanline=%u, pipe B: frame=%u, scanline=%u, pipe C: frame=%u, scanline=%u", | 69 | TP_printk("pipe %c disable, pipe A: frame=%u, scanline=%u, pipe B: frame=%u, scanline=%u, pipe C: frame=%u, scanline=%u", |
| @@ -89,8 +86,7 @@ TRACE_EVENT(intel_pipe_crc, · 16 unmodified lines | |||
| 89 | 86 | ||
| 90 | TP_fast_assign( | 87 | TP_fast_assign( |
| 91 | __entry->pipe = crtc->pipe; | 88 | __entry->pipe = crtc->pipe; |
| 92 | __entry->frame = crtc->base.dev->driver->get_vblank_counter(crtc->base.dev, | 89 | __entry->frame = intel_crtc_get_vblank_counter(crtc); |
| 93 | crtc->pipe); | ||
| 94 | __entry->scanline = intel_get_crtc_scanline(crtc); | 90 | __entry->scanline = intel_get_crtc_scanline(crtc); |
| 95 | memcpy(__entry->crcs, crcs, sizeof(__entry->crcs)); | 91 | memcpy(__entry->crcs, crcs, sizeof(__entry->crcs)); |
| 96 | ), | 92 | ), |
| @@ -112,9 +108,10 @@ TRACE_EVENT(intel_cpu_fifo_underrun, · 15 unmodified lines | |||
| 112 | ), | 108 | ), |
| 113 | 109 | ||
| 114 | TP_fast_assign( | 110 | TP_fast_assign( |
| 111 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); | ||
| 115 | __entry->pipe = pipe; | 112 | __entry->pipe = pipe; |
| 116 | __entry->frame = dev_priv->drm.driver->get_vblank_counter(&dev_priv->drm, pipe); | 113 | __entry->frame = intel_crtc_get_vblank_counter(crtc); |
| 117 | __entry->scanline = intel_get_crtc_scanline(intel_get_crtc_for_pipe(dev_priv, pipe)); | 114 | __entry->scanline = intel_get_crtc_scanline(crtc); |
| 118 | ), | 115 | ), |
| 119 | 116 | ||
| 120 | TP_printk("pipe %c, frame=%u, scanline=%u", | 117 | TP_printk("pipe %c, frame=%u, scanline=%u", |
| @@ -134,9 +131,10 @@ TRACE_EVENT(intel_pch_fifo_underrun, · 13 unmodified lines | |||
| 134 | 131 | ||
| 135 | TP_fast_assign( | 132 | TP_fast_assign( |
| 136 | enum pipe pipe = pch_transcoder; | 133 | enum pipe pipe = pch_transcoder; |
| 134 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); | ||
| 137 | __entry->pipe = pipe; | 135 | __entry->pipe = pipe; |
| 138 | __entry->frame = dev_priv->drm.driver->get_vblank_counter(&dev_priv->drm, pipe); | 136 | __entry->frame = intel_crtc_get_vblank_counter(crtc); |
| 139 | __entry->scanline = intel_get_crtc_scanline(intel_get_crtc_for_pipe(dev_priv, pipe)); | 137 | __entry->scanline = intel_get_crtc_scanline(crtc); |
| 140 | ), | 138 | ), |
| 141 | 139 | ||
| 142 | TP_printk("pch transcoder %c, frame=%u, scanline=%u", | 140 | TP_printk("pch transcoder %c, frame=%u, scanline=%u", |
| @@ -156,12 +154,10 @@ TRACE_EVENT(intel_memory_cxsr, · 13 unmodified lines | |||
| 156 | ), | 154 | ), |
| 157 | 155 | ||
| 158 | TP_fast_assign( | 156 | TP_fast_assign( |
| 159 | enum pipe pipe; | 157 | struct intel_crtc *crtc; |
| 160 | for_each_pipe(dev_priv, pipe) { | 158 | for_each_intel_crtc(&dev_priv->drm, crtc) { |
| 161 | __entry->frame[pipe] = | 159 | __entry->frame[crtc->pipe] = intel_crtc_get_vblank_counter(crtc); |
| 162 | dev_priv->drm.driver->get_vblank_counter(&dev_priv->drm, pipe); | 160 | __entry->scanline[crtc->pipe] = intel_get_crtc_scanline(crtc); |
| 163 | __entry->scanline[pipe] = | ||
| 164 | intel_get_crtc_scanline(intel_get_crtc_for_pipe(dev_priv, pipe)); | ||
| 165 | } | 161 | } |
| 166 | __entry->old = old; | 162 | __entry->old = old; |
| 167 | __entry->new = new; | 163 | __entry->new = new; |
| @@ -198,8 +194,7 @@ TRACE_EVENT(g4x_wm, · 30 unmodified lines | |||
| 198 | 194 | ||
| 199 | TP_fast_assign( | 195 | TP_fast_assign( |
| 200 | __entry->pipe = crtc->pipe; | 196 | __entry->pipe = crtc->pipe; |
| 201 | __entry->frame = crtc->base.dev->driver->get_vblank_counter(crtc->base.dev, | 197 | __entry->frame = intel_crtc_get_vblank_counter(crtc); |
| 202 | crtc->pipe); | ||
| 203 | __entry->scanline = intel_get_crtc_scanline(crtc); | 198 | __entry->scanline = intel_get_crtc_scanline(crtc); |
| 204 | __entry->primary = wm->pipe[crtc->pipe].plane[PLANE_PRIMARY]; | 199 | __entry->primary = wm->pipe[crtc->pipe].plane[PLANE_PRIMARY]; |
| 205 | __entry->sprite = wm->pipe[crtc->pipe].plane[PLANE_SPRITE0]; | 200 | __entry->sprite = wm->pipe[crtc->pipe].plane[PLANE_SPRITE0]; |
| @@ -243,8 +238,7 @@ TRACE_EVENT(vlv_wm, · 37 unmodified lines | |||
| 243 | 238 | ||
| 244 | TP_fast_assign( | 239 | TP_fast_assign( |
| 245 | __entry->pipe = crtc->pipe; | 240 | __entry->pipe = crtc->pipe; |
| 246 | __entry->frame = crtc->base.dev->driver->get_vblank_counter(crtc->base.dev, | 241 | __entry->frame = intel_crtc_get_vblank_counter(crtc); |
| 247 | crtc->pipe); | ||
| 248 | __entry->scanline = intel_get_crtc_scanline(crtc); | 242 | __entry->scanline = intel_get_crtc_scanline(crtc); |
| 249 | __entry->level = wm->level; | 243 | __entry->level = wm->level; |
| 250 | __entry->cxsr = wm->cxsr; | 244 | __entry->cxsr = wm->cxsr; |
| @@ -278,8 +272,7 @@ TRACE_EVENT(vlv_fifo_size, · 27 unmodified lines | |||
| 278 | 272 | ||
| 279 | TP_fast_assign( | 273 | TP_fast_assign( |
| 280 | __entry->pipe = crtc->pipe; | 274 | __entry->pipe = crtc->pipe; |
| 281 | __entry->frame = crtc->base.dev->driver->get_vblank_counter(crtc->base.dev, | 275 | __entry->frame = intel_crtc_get_vblank_counter(crtc); |
| 282 | crtc->pipe); | ||
| 283 | __entry->scanline = intel_get_crtc_scanline(crtc); | 276 | __entry->scanline = intel_get_crtc_scanline(crtc); |
| 284 | __entry->sprite0_start = sprite0_start; | 277 | __entry->sprite0_start = sprite0_start; |
| 285 | __entry->sprite1_start = sprite1_start; | 278 | __entry->sprite1_start = sprite1_start; |
| @@ -310,8 +303,7 @@ TRACE_EVENT(intel_update_plane, · 24 unmodified lines | |||
| 310 | TP_fast_assign( | 303 | TP_fast_assign( |
| 311 | __entry->pipe = crtc->pipe; | 304 | __entry->pipe = crtc->pipe; |
| 312 | __entry->name = plane->name; | 305 | __entry->name = plane->name; |
| 313 | __entry->frame = crtc->base.dev->driver->get_vblank_counter(crtc->base.dev, | 306 | __entry->frame = intel_crtc_get_vblank_counter(crtc); |
| 314 | crtc->pipe); | ||
| 315 | __entry->scanline = intel_get_crtc_scanline(crtc); | 307 | __entry->scanline = intel_get_crtc_scanline(crtc); |
| 316 | memcpy(__entry->src, &plane->state->src, sizeof(__entry->src)); | 308 | memcpy(__entry->src, &plane->state->src, sizeof(__entry->src)); |
| 317 | memcpy(__entry->dst, &plane->state->dst, sizeof(__entry->dst)); | 309 | memcpy(__entry->dst, &plane->state->dst, sizeof(__entry->dst)); |
| @@ -338,8 +330,7 @@ TRACE_EVENT(intel_disable_plane, · 20 unmodified lines | |||
| 338 | TP_fast_assign( | 330 | TP_fast_assign( |
| 339 | __entry->pipe = crtc->pipe; | 331 | __entry->pipe = crtc->pipe; |
| 340 | __entry->name = plane->name; | 332 | __entry->name = plane->name; |
| 341 | __entry->frame = crtc->base.dev->driver->get_vblank_counter(crtc->base.dev, | 333 | __entry->frame = intel_crtc_get_vblank_counter(crtc); |
| 342 | crtc->pipe); | ||
| 343 | __entry->scanline = intel_get_crtc_scanline(crtc); | 334 | __entry->scanline = intel_get_crtc_scanline(crtc); |
| 344 | ), | 335 | ), |
| 345 | 336 | ||
| @@ -364,8 +355,7 @@ TRACE_EVENT(i915_pipe_update_start, · 18 unmodified lines | |||
| 364 | 355 | ||
| 365 | TP_fast_assign( | 356 | TP_fast_assign( |
| 366 | __entry->pipe = crtc->pipe; | 357 | __entry->pipe = crtc->pipe; |
| 367 | __entry->frame = crtc->base.dev->driver->get_vblank_counter(crtc->base.dev, | 358 | __entry->frame = intel_crtc_get_vblank_counter(crtc); |
| 368 | crtc->pipe); | ||
| 369 | __entry->scanline = intel_get_crtc_scanline(crtc); | 359 | __entry->scanline = intel_get_crtc_scanline(crtc); |
| 370 | __entry->min = crtc->debug.min_vbl; | 360 | __entry->min = crtc->debug.min_vbl; |
| 371 | __entry->max = crtc->debug.max_vbl; | 361 | __entry->max = crtc->debug.max_vbl; |
| @@ -221,13 +221,11 @@ __untrack_all_wakerefs(struct intel_runtime_pm_debug *debug, · 220 unmodified lines | |||
| 221 | static void | 221 | static void |
| 222 | dump_and_free_wakeref_tracking(struct intel_runtime_pm_debug *debug) | 222 | dump_and_free_wakeref_tracking(struct intel_runtime_pm_debug *debug) |
| 223 | { | 223 | { |
| 224 | struct drm_printer p; | 224 | if (debug->count) { |
| 225 | struct drm_printer p = drm_debug_printer("i915"); | ||
| 225 | 226 | ||
| 226 | if (!debug->count) | 227 | __print_intel_runtime_pm_wakeref(&p, debug); |
| 227 | return; | 228 | } |
| 228 | |||
| 229 | p = drm_debug_printer("i915"); | ||
| 230 | __print_intel_runtime_pm_wakeref(&p, debug); | ||
| 231 | 229 | ||
| 232 | kfree(debug->owners); | 230 | kfree(debug->owners); |
| 233 | } | 231 | } |
| @@ -65,6 +65,21 @@ intel_wakeref_get(struct intel_runtime_pm *rpm, · 64 unmodified lines | |||
| 65 | return 0; | 65 | return 0; |
| 66 | } | 66 | } |
| 67 | 67 | ||
| 68 | /** | ||
| 69 | * intel_wakeref_get_if_in_use: Acquire the wakeref | ||
| 70 | * @wf: the wakeref | ||
| 71 | * | ||
| 72 | * Acquire a hold on the wakeref, but only if the wakeref is already | ||
| 73 | * active. | ||
| 74 | * | ||
| 75 | * Returns: true if the wakeref was acquired, false otherwise. | ||
| 76 | */ | ||
| 77 | static inline bool | ||
| 78 | intel_wakeref_get_if_active(struct intel_wakeref *wf) | ||
| 79 | { | ||
| 80 | return atomic_inc_not_zero(&wf->count); | ||
| 81 | } | ||
| 82 | |||
| 68 | /** | 83 | /** |
| 69 | * intel_wakeref_put: Release the wakeref | 84 | * intel_wakeref_put: Release the wakeref |
| 70 | * @i915: the drm_i915_private device | 85 | * @i915: the drm_i915_private device |
| @@ -59,6 +59,7 @@ static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct msm_gem_submit *submit · 58 unmodified lines | |||
| 59 | case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: | 59 | case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: |
| 60 | if (priv->lastctx == ctx) | 60 | if (priv->lastctx == ctx) |
| 61 | break; | 61 | break; |
| 62 | /* fall-thru */ | ||
| 62 | case MSM_SUBMIT_CMD_BUF: | 63 | case MSM_SUBMIT_CMD_BUF: |
| 63 | /* copy commands into RB: */ | 64 | /* copy commands into RB: */ |
| 64 | obj = submit->bos[submit->cmd[i].idx].obj; | 65 | obj = submit->bos[submit->cmd[i].idx].obj; |
| @@ -149,6 +150,7 @@ static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, · 84 unmodified lines | |||
| 149 | case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: | 150 | case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: |
| 150 | if (priv->lastctx == ctx) | 151 | if (priv->lastctx == ctx) |
| 151 | break; | 152 | break; |
| 153 | /* fall-thru */ | ||
| 152 | case MSM_SUBMIT_CMD_BUF: | 154 | case MSM_SUBMIT_CMD_BUF: |
| 153 | OUT_PKT7(ring, CP_INDIRECT_BUFFER_PFE, 3); | 155 | OUT_PKT7(ring, CP_INDIRECT_BUFFER_PFE, 3); |
| 154 | OUT_RING(ring, lower_32_bits(submit->cmd[i].iova)); | 156 | OUT_RING(ring, lower_32_bits(submit->cmd[i].iova)); |
| @@ -115,6 +115,7 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, · 114 unmodified lines | |||
| 115 | case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: | 115 | case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: |
| 116 | if (priv->lastctx == ctx) | 116 | if (priv->lastctx == ctx) |
| 117 | break; | 117 | break; |
| 118 | /* fall-thru */ | ||
| 118 | case MSM_SUBMIT_CMD_BUF: | 119 | case MSM_SUBMIT_CMD_BUF: |
| 119 | OUT_PKT7(ring, CP_INDIRECT_BUFFER_PFE, 3); | 120 | OUT_PKT7(ring, CP_INDIRECT_BUFFER_PFE, 3); |
| 120 | OUT_RING(ring, lower_32_bits(submit->cmd[i].iova)); | 121 | OUT_RING(ring, lower_32_bits(submit->cmd[i].iova)); |
| @@ -428,6 +428,7 @@ void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, · 427 unmodified lines | |||
| 428 | /* ignore if there has not been a ctx switch: */ | 428 | /* ignore if there has not been a ctx switch: */ |
| 429 | if (priv->lastctx == ctx) | 429 | if (priv->lastctx == ctx) |
| 430 | break; | 430 | break; |
| 431 | /* fall-thru */ | ||
| 431 | case MSM_SUBMIT_CMD_BUF: | 432 | case MSM_SUBMIT_CMD_BUF: |
| 432 | OUT_PKT3(ring, adreno_is_a430(adreno_gpu) ? | 433 | OUT_PKT3(ring, adreno_is_a430(adreno_gpu) ? |
| 433 | CP_INDIRECT_BUFFER_PFE : CP_INDIRECT_BUFFER_PFD, 2); | 434 | CP_INDIRECT_BUFFER_PFE : CP_INDIRECT_BUFFER_PFD, 2); |
| @@ -2221,8 +2221,6 @@ int dpu_encoder_setup(struct drm_device *dev, struct drm_encoder *enc, · 2220 unmodified lines | |||
| 2221 | if (ret) | 2221 | if (ret) |
| 2222 | goto fail; | 2222 | goto fail; |
| 2223 | 2223 | ||
| 2224 | spin_lock_init(&dpu_enc->enc_spinlock); | ||
| 2225 | |||
| 2226 | atomic_set(&dpu_enc->frame_done_timeout_ms, 0); | 2224 | atomic_set(&dpu_enc->frame_done_timeout_ms, 0); |
| 2227 | timer_setup(&dpu_enc->frame_done_timer, | 2225 | timer_setup(&dpu_enc->frame_done_timer, |
| 2228 | dpu_encoder_frame_done_timeout, 0); | 2226 | dpu_encoder_frame_done_timeout, 0); |
| @@ -2276,6 +2274,7 @@ struct drm_encoder *dpu_encoder_init(struct drm_device *dev, · 47 unmodified lines | |||
| 2276 | 2274 | ||
| 2277 | drm_encoder_helper_add(&dpu_enc->base, &dpu_encoder_helper_funcs); | 2275 | drm_encoder_helper_add(&dpu_enc->base, &dpu_encoder_helper_funcs); |
| 2278 | 2276 | ||
| 2277 | spin_lock_init(&dpu_enc->enc_spinlock); | ||
| 2279 | dpu_enc->enabled = false; | 2278 | dpu_enc->enabled = false; |
| 2280 | 2279 | ||
| 2281 | return &dpu_enc->base; | 2280 | return &dpu_enc->base; |
| @@ -439,6 +439,18 @@ static void mdp5_crtc_atomic_disable(struct drm_crtc *crtc, · 438 unmodified lines | |||
| 439 | mdp5_crtc->enabled = false; | 439 | mdp5_crtc->enabled = false; |
| 440 | } | 440 | } |
| 441 | 441 | ||
| 442 | static void mdp5_crtc_vblank_on(struct drm_crtc *crtc) | ||
| 443 | { | ||
| 444 | struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); | ||
| 445 | struct mdp5_interface *intf = mdp5_cstate->pipeline.intf; | ||
| 446 | u32 count; | ||
| 447 | |||
| 448 | count = intf->mode == MDP5_INTF_DSI_MODE_COMMAND ? 0 : 0xffffffff; | ||
| 449 | drm_crtc_set_max_vblank_count(crtc, count); | ||
| 450 | |||
| 451 | drm_crtc_vblank_on(crtc); | ||
| 452 | } | ||
| 453 | |||
| 442 | static void mdp5_crtc_atomic_enable(struct drm_crtc *crtc, | 454 | static void mdp5_crtc_atomic_enable(struct drm_crtc *crtc, |
| 443 | struct drm_crtc_state *old_state) | 455 | struct drm_crtc_state *old_state) |
| 444 | { | 456 | { |
| @@ -475,7 +487,7 @@ static void mdp5_crtc_atomic_enable(struct drm_crtc *crtc, · 30 unmodified lines | |||
| 475 | } | 487 | } |
| 476 | 488 | ||
| 477 | /* Restore vblank irq handling after power is enabled */ | 489 | /* Restore vblank irq handling after power is enabled */ |
| 478 | drm_crtc_vblank_on(crtc); | 490 | mdp5_crtc_vblank_on(crtc); |
| 479 | 491 | ||
| 480 | mdp5_crtc_mode_set_nofb(crtc); | 492 | mdp5_crtc_mode_set_nofb(crtc); |
| 481 | 493 | ||
| @@ -1028,6 +1040,8 @@ static void mdp5_crtc_reset(struct drm_crtc *crtc) · 546 unmodified lines | |||
| 1028 | mdp5_crtc_destroy_state(crtc, crtc->state); | 1040 | mdp5_crtc_destroy_state(crtc, crtc->state); |
| 1029 | 1041 | ||
| 1030 | __drm_atomic_helper_crtc_reset(crtc, &mdp5_cstate->base); | 1042 | __drm_atomic_helper_crtc_reset(crtc, &mdp5_cstate->base); |
| 1043 | |||
| 1044 | drm_crtc_vblank_reset(crtc); | ||
| 1031 | } | 1045 | } |
| 1032 | 1046 | ||
| 1033 | static const struct drm_crtc_funcs mdp5_crtc_funcs = { | 1047 | static const struct drm_crtc_funcs mdp5_crtc_funcs = { |
| @@ -740,7 +740,7 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev) · 739 unmodified lines | |||
| 740 | dev->driver->get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos; | 740 | dev->driver->get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos; |
| 741 | dev->driver->get_scanout_position = mdp5_get_scanoutpos; | 741 | dev->driver->get_scanout_position = mdp5_get_scanoutpos; |
| 742 | dev->driver->get_vblank_counter = mdp5_get_vblank_counter; | 742 | dev->driver->get_vblank_counter = mdp5_get_vblank_counter; |
| 743 | dev->max_vblank_count = 0xffffffff; | 743 | dev->max_vblank_count = 0; /* max_vblank_count is set on each CRTC */ |
| 744 | dev->vblank_disable_immediate = true; | 744 | dev->vblank_disable_immediate = true; |
| 745 | 745 | ||
| 746 | return kms; | 746 | return kms; |
| @@ -619,7 +619,7 @@ static int context_init(struct drm_device *dev, struct drm_file *file) · 618 unmodified lines | |||
| 619 | 619 | ||
| 620 | msm_submitqueue_init(dev, ctx); | 620 | msm_submitqueue_init(dev, ctx); |
| 621 | 621 | ||
| 622 | ctx->aspace = priv->gpu->aspace; | 622 | ctx->aspace = priv->gpu ? priv->gpu->aspace : NULL; |
| 623 | file->driver_priv = ctx; | 623 | file->driver_priv = ctx; |
| 624 | 624 | ||
| 625 | return 0; | 625 | return 0; |
| @@ -1279,7 +1279,8 @@ static int add_gpu_components(struct device *dev, · 653 unmodified lines | |||
| 1279 | if (!np) | 1279 | if (!np) |
| 1280 | return 0; | 1280 | return 0; |
| 1281 | 1281 | ||
| 1282 | drm_of_component_match_add(dev, matchptr, compare_of, np); | 1282 | if (of_device_is_available(np)) |
| 1283 | drm_of_component_match_add(dev, matchptr, compare_of, np); | ||
| 1283 | 1284 | ||
| 1284 | of_node_put(np); | 1285 | of_node_put(np); |
| 1285 | 1286 | ||
| @@ -32,6 +32,46 @@ static bool use_pages(struct drm_gem_object *obj) · 31 unmodified lines | |||
| 32 | return !msm_obj->vram_node; | 32 | return !msm_obj->vram_node; |
| 33 | } | 33 | } |
| 34 | 34 | ||
| 35 | /* | ||
| 36 | * Cache sync.. this is a bit over-complicated, to fit dma-mapping | ||
| 37 | * API. Really GPU cache is out of scope here (handled on cmdstream) | ||
| 38 | * and all we need to do is invalidate newly allocated pages before | ||
| 39 | * mapping to CPU as uncached/writecombine. | ||
| 40 | * | ||
| 41 | * On top of this, we have the added headache, that depending on | ||
| 42 | * display generation, the display's iommu may be wired up to either | ||
| 43 | * the toplevel drm device (mdss), or to the mdp sub-node, meaning | ||
| 44 | * that here we either have dma-direct or iommu ops. | ||
| 45 | * | ||
| 46 | * Let this be a cautionary tail of abstraction gone wrong. | ||
| 47 | */ | ||
| 48 | |||
| 49 | static void sync_for_device(struct msm_gem_object *msm_obj) | ||
| 50 | { | ||
| 51 | struct device *dev = msm_obj->base.dev->dev; | ||
| 52 | |||
| 53 | if (get_dma_ops(dev)) { | ||
| 54 | dma_sync_sg_for_device(dev, msm_obj->sgt->sgl, | ||
| 55 | msm_obj->sgt->nents, DMA_BIDIRECTIONAL); | ||
| 56 | } else { | ||
| 57 | dma_map_sg(dev, msm_obj->sgt->sgl, | ||
| 58 | msm_obj->sgt->nents, DMA_BIDIRECTIONAL); | ||
| 59 | } | ||
| 60 | } | ||
| 61 | |||
| 62 | static void sync_for_cpu(struct msm_gem_object *msm_obj) | ||
| 63 | { | ||
| 64 | struct device *dev = msm_obj->base.dev->dev; | ||
| 65 | |||
| 66 | if (get_dma_ops(dev)) { | ||
| 67 | dma_sync_sg_for_cpu(dev, msm_obj->sgt->sgl, | ||
| 68 | msm_obj->sgt->nents, DMA_BIDIRECTIONAL); | ||
| 69 | } else { | ||
| 70 | dma_unmap_sg(dev, msm_obj->sgt->sgl, | ||
| 71 | msm_obj->sgt->nents, DMA_BIDIRECTIONAL); | ||
| 72 | } | ||
| 73 | } | ||
| 74 | |||
| 35 | /* allocate pages from VRAM carveout, used when no IOMMU: */ | 75 | /* allocate pages from VRAM carveout, used when no IOMMU: */ |
| 36 | static struct page **get_pages_vram(struct drm_gem_object *obj, int npages) | 76 | static struct page **get_pages_vram(struct drm_gem_object *obj, int npages) |
| 37 | { | 77 | { |
| @@ -97,8 +137,7 @@ static struct page **get_pages(struct drm_gem_object *obj) · 59 unmodified lines | |||
| 97 | * because display controller, GPU, etc. are not coherent: | 137 | * because display controller, GPU, etc. are not coherent: |
| 98 | */ | 138 | */ |
| 99 | if (msm_obj->flags & (MSM_BO_WC|MSM_BO_UNCACHED)) | 139 | if (msm_obj->flags & (MSM_BO_WC|MSM_BO_UNCACHED)) |
| 100 | dma_map_sg(dev->dev, msm_obj->sgt->sgl, | 140 | sync_for_device(msm_obj); |
| 101 | msm_obj->sgt->nents, DMA_BIDIRECTIONAL); | ||
| 102 | } | 141 | } |
| 103 | 142 | ||
| 104 | return msm_obj->pages; | 143 | return msm_obj->pages; |
| @@ -127,9 +166,7 @@ static void put_pages(struct drm_gem_object *obj) · 22 unmodified lines | |||
| 127 | * GPU, etc. are not coherent: | 166 | * GPU, etc. are not coherent: |
| 128 | */ | 167 | */ |
| 129 | if (msm_obj->flags & (MSM_BO_WC|MSM_BO_UNCACHED)) | 168 | if (msm_obj->flags & (MSM_BO_WC|MSM_BO_UNCACHED)) |
| 130 | dma_unmap_sg(obj->dev->dev, msm_obj->sgt->sgl, | 169 | sync_for_cpu(msm_obj); |
| 131 | msm_obj->sgt->nents, | ||
| 132 | DMA_BIDIRECTIONAL); | ||
| 133 | 170 | ||
| 134 | sg_free_table(msm_obj->sgt); | 171 | sg_free_table(msm_obj->sgt); |
| 135 | kfree(msm_obj->sgt); | 172 | kfree(msm_obj->sgt); |
| @@ -771,16 +771,20 @@ nv50_msto_atomic_check(struct drm_encoder *encoder, · 770 unmodified lines | |||
| 771 | struct nv50_head_atom *asyh = nv50_head_atom(crtc_state); | 771 | struct nv50_head_atom *asyh = nv50_head_atom(crtc_state); |
| 772 | int slots; | 772 | int slots; |
| 773 | 773 | ||
| 774 | /* When restoring duplicated states, we need to make sure that the | 774 | if (crtc_state->mode_changed || crtc_state->connectors_changed) { |
| 775 | * bw remains the same and avoid recalculating it, as the connector's | 775 | /* |
| 776 | * bpc may have changed after the state was duplicated | 776 | * When restoring duplicated states, we need to make sure that |
| 777 | */ | 777 | * the bw remains the same and avoid recalculating it, as the |
| 778 | if (!state->duplicated) | 778 | * connector's bpc may have changed after the state was |
| 779 | asyh->dp.pbn = | 779 | * duplicated |
| 780 | drm_dp_calc_pbn_mode(crtc_state->adjusted_mode.clock, | 780 | */ |
| 781 | connector->display_info.bpc * 3); | 781 | if (!state->duplicated) { |
| 782 | const int bpp = connector->display_info.bpc * 3; | ||
| 783 | const int clock = crtc_state->adjusted_mode.clock; | ||
| 784 | |||
| 785 | asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, bpp); | ||
| 786 | } | ||
| 782 | 787 | ||
| 783 | if (drm_atomic_crtc_needs_modeset(crtc_state)) { | ||
| 784 | slots = drm_dp_atomic_find_vcpi_slots(state, &mstm->mgr, | 788 | slots = drm_dp_atomic_find_vcpi_slots(state, &mstm->mgr, |
| 785 | mstc->port, | 789 | mstc->port, |
| 786 | asyh->dp.pbn); | 790 | asyh->dp.pbn); |
| @@ -432,7 +432,7 @@ static int rockchip_dp_resume(struct device *dev) · 431 unmodified lines | |||
| 432 | 432 | ||
| 433 | static const struct dev_pm_ops rockchip_dp_pm_ops = { | 433 | static const struct dev_pm_ops rockchip_dp_pm_ops = { |
| 434 | #ifdef CONFIG_PM_SLEEP | 434 | #ifdef CONFIG_PM_SLEEP |
| 435 | .suspend = rockchip_dp_suspend, | 435 | .suspend_late = rockchip_dp_suspend, |
| 436 | .resume_early = rockchip_dp_resume, | 436 | .resume_early = rockchip_dp_resume, |
| 437 | #endif | 437 | #endif |
| 438 | }; | 438 | }; |
| @@ -95,7 +95,7 @@ static bool drm_sched_entity_is_idle(struct drm_sched_entity *entity) · 94 unmodified lines | |||
| 95 | rmb(); /* for list_empty to work without lock */ | 95 | rmb(); /* for list_empty to work without lock */ |
| 96 | 96 | ||
| 97 | if (list_empty(&entity->list) || | 97 | if (list_empty(&entity->list) || |
| 98 | spsc_queue_peek(&entity->job_queue) == NULL) | 98 | spsc_queue_count(&entity->job_queue) == 0) |
| 99 | return true; | 99 | return true; |
| 100 | 100 | ||
| 101 | return false; | 101 | return false; |
| @@ -281,7 +281,7 @@ void drm_sched_entity_fini(struct drm_sched_entity *entity) · 179 unmodified lines | |||
| 281 | /* Consumption of existing IBs wasn't completed. Forcefully | 281 | /* Consumption of existing IBs wasn't completed. Forcefully |
| 282 | * remove them here. | 282 | * remove them here. |
| 283 | */ | 283 | */ |
| 284 | if (spsc_queue_peek(&entity->job_queue)) { | 284 | if (spsc_queue_count(&entity->job_queue)) { |
| 285 | if (sched) { | 285 | if (sched) { |
| 286 | /* Park the kernel for a moment to make sure it isn't processing | 286 | /* Park the kernel for a moment to make sure it isn't processing |
| 287 | * our enity. | 287 | * our enity. |
| @@ -126,8 +126,12 @@ int tegra_output_probe(struct tegra_output *output) · 125 unmodified lines | |||
| 126 | "nvidia,hpd-gpio", 0, | 126 | "nvidia,hpd-gpio", 0, |
| 127 | GPIOD_IN, | 127 | GPIOD_IN, |
| 128 | "HDMI hotplug detect"); | 128 | "HDMI hotplug detect"); |
| 129 | if (IS_ERR(output->hpd_gpio)) | 129 | if (IS_ERR(output->hpd_gpio)) { |
| 130 | return PTR_ERR(output->hpd_gpio); | 130 | if (PTR_ERR(output->hpd_gpio) != -ENOENT) |
| 131 | return PTR_ERR(output->hpd_gpio); | ||
| 132 | |||
| 133 | output->hpd_gpio = NULL; | ||
| 134 | } | ||
| 131 | 135 | ||
| 132 | if (output->hpd_gpio) { | 136 | if (output->hpd_gpio) { |
| 133 | err = gpiod_to_irq(output->hpd_gpio); | 137 | err = gpiod_to_irq(output->hpd_gpio); |
| @@ -285,9 +285,13 @@ static int ttm_set_pages_caching(struct dma_pool *pool, · 284 unmodified lines | |||
| 285 | 285 | ||
| 286 | static void __ttm_dma_free_page(struct dma_pool *pool, struct dma_page *d_page) | 286 | static void __ttm_dma_free_page(struct dma_pool *pool, struct dma_page *d_page) |
| 287 | { | 287 | { |
| 288 | unsigned long attrs = 0; | ||
| 288 | dma_addr_t dma = d_page->dma; | 289 | dma_addr_t dma = d_page->dma; |
| 289 | d_page->vaddr &= ~VADDR_FLAG_HUGE_POOL; | 290 | d_page->vaddr &= ~VADDR_FLAG_HUGE_POOL; |
| 290 | dma_free_coherent(pool->dev, pool->size, (void *)d_page->vaddr, dma); | 291 | if (pool->type & IS_HUGE) |
| 292 | attrs = DMA_ATTR_NO_WARN; | ||
| 293 | |||
| 294 | dma_free_attrs(pool->dev, pool->size, (void *)d_page->vaddr, dma, attrs); | ||
| 291 | 295 | ||
| 292 | kfree(d_page); | 296 | kfree(d_page); |
| 293 | d_page = NULL; | 297 | d_page = NULL; |
| @@ -389,8 +389,10 @@ static int vmw_recv_msg(struct rpc_channel *channel, void **msg, · 388 unmodified lines | |||
| 389 | break; | 389 | break; |
| 390 | } | 390 | } |
| 391 | 391 | ||
| 392 | if (retries == RETRIES) | 392 | if (retries == RETRIES) { |
| 393 | kfree(reply); | ||
| 393 | return -EINVAL; | 394 | return -EINVAL; |
| 395 | } | ||
| 394 | 396 | ||
| 395 | *msg_len = reply_len; | 397 | *msg_len = reply_len; |
| 396 | *msg = reply; | 398 | *msg = reply; |
| @@ -23,12 +23,36 @@ · 22 unmodified lines | |||
| 23 | #define A4_2WHEEL_MOUSE_HACK_7 0x01 | 23 | #define A4_2WHEEL_MOUSE_HACK_7 0x01 |
| 24 | #define A4_2WHEEL_MOUSE_HACK_B8 0x02 | 24 | #define A4_2WHEEL_MOUSE_HACK_B8 0x02 |
| 25 | 25 | ||
| 26 | #define A4_WHEEL_ORIENTATION (HID_UP_GENDESK | 0x000000b8) | ||
| 27 | |||
| 26 | struct a4tech_sc { | 28 | struct a4tech_sc { |
| 27 | unsigned long quirks; | 29 | unsigned long quirks; |
| 28 | unsigned int hw_wheel; | 30 | unsigned int hw_wheel; |
| 29 | __s32 delayed_value; | 31 | __s32 delayed_value; |
| 30 | }; | 32 | }; |
| 31 | 33 | ||
| 34 | static int a4_input_mapping(struct hid_device *hdev, struct hid_input *hi, | ||
| 35 | struct hid_field *field, struct hid_usage *usage, | ||
| 36 | unsigned long **bit, int *max) | ||
| 37 | { | ||
| 38 | struct a4tech_sc *a4 = hid_get_drvdata(hdev); | ||
| 39 | |||
| 40 | if (a4->quirks & A4_2WHEEL_MOUSE_HACK_B8 && | ||
| 41 | usage->hid == A4_WHEEL_ORIENTATION) { | ||
| 42 | /* | ||
| 43 | * We do not want to have this usage mapped to anything as it's | ||
| 44 | * nonstandard and doesn't really behave like an HID report. | ||
| 45 | * It's only selecting the orientation (vertical/horizontal) of | ||
| 46 | * the previous mouse wheel report. The input_events will be | ||
| 47 | * generated once both reports are recorded in a4_event(). | ||
| 48 | */ | ||
| 49 | return -1; | ||
| 50 | } | ||
| 51 | |||
| 52 | return 0; | ||
| 53 | |||
| 54 | } | ||
| 55 | |||
| 32 | static int a4_input_mapped(struct hid_device *hdev, struct hid_input *hi, | 56 | static int a4_input_mapped(struct hid_device *hdev, struct hid_input *hi, |
| 33 | struct hid_field *field, struct hid_usage *usage, | 57 | struct hid_field *field, struct hid_usage *usage, |
| 34 | unsigned long **bit, int *max) | 58 | unsigned long **bit, int *max) |
| @@ -52,8 +76,7 @@ static int a4_event(struct hid_device *hdev, struct hid_field *field, · 17 unmodified lines | |||
| 52 | struct a4tech_sc *a4 = hid_get_drvdata(hdev); | 76 | struct a4tech_sc *a4 = hid_get_drvdata(hdev); |
| 53 | struct input_dev *input; | 77 | struct input_dev *input; |
| 54 | 78 | ||
| 55 | if (!(hdev->claimed & HID_CLAIMED_INPUT) || !field->hidinput || | 79 | if (!(hdev->claimed & HID_CLAIMED_INPUT) || !field->hidinput) |
| 56 | !usage->type) | ||
| 57 | return 0; | 80 | return 0; |
| 58 | 81 | ||
| 59 | input = field->hidinput->input; | 82 | input = field->hidinput->input; |
| @@ -64,7 +87,7 @@ static int a4_event(struct hid_device *hdev, struct hid_field *field, · 4 unmodified lines | |||
| 64 | return 1; | 87 | return 1; |
| 65 | } | 88 | } |
| 66 | 89 | ||
| 67 | if (usage->hid == 0x000100b8) { | 90 | if (usage->hid == A4_WHEEL_ORIENTATION) { |
| 68 | input_event(input, EV_REL, value ? REL_HWHEEL : | 91 | input_event(input, EV_REL, value ? REL_HWHEEL : |
| 69 | REL_WHEEL, a4->delayed_value); | 92 | REL_WHEEL, a4->delayed_value); |
| 70 | input_event(input, EV_REL, value ? REL_HWHEEL_HI_RES : | 93 | input_event(input, EV_REL, value ? REL_HWHEEL_HI_RES : |
| @@ -131,6 +154,7 @@ MODULE_DEVICE_TABLE(hid, a4_devices); · 60 unmodified lines | |||
| 131 | static struct hid_driver a4_driver = { | 154 | static struct hid_driver a4_driver = { |
| 132 | .name = "a4tech", | 155 | .name = "a4tech", |
| 133 | .id_table = a4_devices, | 156 | .id_table = a4_devices, |
| 157 | .input_mapping = a4_input_mapping, | ||
| 134 | .input_mapped = a4_input_mapped, | 158 | .input_mapped = a4_input_mapped, |
| 135 | .event = a4_event, | 159 | .event = a4_event, |
| 136 | .probe = a4_probe, | 160 | .probe = a4_probe, |
| @@ -123,9 +123,14 @@ static int holtek_kbd_input_event(struct input_dev *dev, unsigned int type, · 122 unmodified lines | |||
| 123 | 123 | ||
| 124 | /* Locate the boot interface, to receive the LED change events */ | 124 | /* Locate the boot interface, to receive the LED change events */ |
| 125 | struct usb_interface *boot_interface = usb_ifnum_to_if(usb_dev, 0); | 125 | struct usb_interface *boot_interface = usb_ifnum_to_if(usb_dev, 0); |
| 126 | struct hid_device *boot_hid; | ||
| 127 | struct hid_input *boot_hid_input; | ||
| 126 | 128 | ||
| 127 | struct hid_device *boot_hid = usb_get_intfdata(boot_interface); | 129 | if (unlikely(boot_interface == NULL)) |
| 128 | struct hid_input *boot_hid_input = list_first_entry(&boot_hid->inputs, | 130 | return -ENODEV; |
| 131 | |||
| 132 | boot_hid = usb_get_intfdata(boot_interface); | ||
| 133 | boot_hid_input = list_first_entry(&boot_hid->inputs, | ||
| 129 | struct hid_input, list); | 134 | struct hid_input, list); |
| 130 | 135 | ||
| 131 | return boot_hid_input->input->event(boot_hid_input->input, type, code, | 136 | return boot_hid_input->input->event(boot_hid_input->input, type, code, |
| @@ -568,6 +568,7 @@ · 567 unmodified lines | |||
| 568 | #define USB_PRODUCT_ID_HP_LOGITECH_OEM_USB_OPTICAL_MOUSE_0B4A 0x0b4a | 568 | #define USB_PRODUCT_ID_HP_LOGITECH_OEM_USB_OPTICAL_MOUSE_0B4A 0x0b4a |
| 569 | #define USB_PRODUCT_ID_HP_PIXART_OEM_USB_OPTICAL_MOUSE 0x134a | 569 | #define USB_PRODUCT_ID_HP_PIXART_OEM_USB_OPTICAL_MOUSE 0x134a |
| 570 | #define USB_PRODUCT_ID_HP_PIXART_OEM_USB_OPTICAL_MOUSE_094A 0x094a | 570 | #define USB_PRODUCT_ID_HP_PIXART_OEM_USB_OPTICAL_MOUSE_094A 0x094a |
| 571 | #define USB_PRODUCT_ID_HP_PIXART_OEM_USB_OPTICAL_MOUSE_0641 0x0641 | ||
| 571 | 572 | ||
| 572 | #define USB_VENDOR_ID_HUION 0x256c | 573 | #define USB_VENDOR_ID_HUION 0x256c |
| 573 | #define USB_DEVICE_ID_HUION_TABLET 0x006e | 574 | #define USB_DEVICE_ID_HUION_TABLET 0x006e |
| @@ -768,7 +769,8 @@ · 194 unmodified lines | |||
| 768 | #define USB_DEVICE_ID_LOGITECH_NANO_RECEIVER 0xc52f | 769 | #define USB_DEVICE_ID_LOGITECH_NANO_RECEIVER 0xc52f |
| 769 | #define USB_DEVICE_ID_LOGITECH_UNIFYING_RECEIVER_2 0xc532 | 770 | #define USB_DEVICE_ID_LOGITECH_UNIFYING_RECEIVER_2 0xc532 |
| 770 | #define USB_DEVICE_ID_LOGITECH_NANO_RECEIVER_2 0xc534 | 771 | #define USB_DEVICE_ID_LOGITECH_NANO_RECEIVER_2 0xc534 |
| 771 | #define USB_DEVICE_ID_LOGITECH_NANO_RECEIVER_GAMING 0xc539 | 772 | #define USB_DEVICE_ID_LOGITECH_NANO_RECEIVER_LIGHTSPEED 0xc539 |
| 773 | #define USB_DEVICE_ID_LOGITECH_NANO_RECEIVER_POWERPLAY 0xc53a | ||
| 772 | #define USB_DEVICE_ID_SPACETRAVELLER 0xc623 | 774 | #define USB_DEVICE_ID_SPACETRAVELLER 0xc623 |
| 773 | #define USB_DEVICE_ID_SPACENAVIGATOR 0xc626 | 775 | #define USB_DEVICE_ID_SPACENAVIGATOR 0xc626 |
| 774 | #define USB_DEVICE_ID_DINOVO_DESKTOP 0xc704 | 776 | #define USB_DEVICE_ID_DINOVO_DESKTOP 0xc704 |
| @@ -989,6 +991,7 @@ · 214 unmodified lines | |||
| 989 | #define USB_DEVICE_ID_SAITEK_RAT7 0x0cd7 | 991 | #define USB_DEVICE_ID_SAITEK_RAT7 0x0cd7 |
| 990 | #define USB_DEVICE_ID_SAITEK_RAT9 0x0cfa | 992 | #define USB_DEVICE_ID_SAITEK_RAT9 0x0cfa |
| 991 | #define USB_DEVICE_ID_SAITEK_MMO7 0x0cd0 | 993 | #define USB_DEVICE_ID_SAITEK_MMO7 0x0cd0 |
| 994 | #define USB_DEVICE_ID_SAITEK_X52 0x075c | ||
| 992 | 995 | ||
| 993 | #define USB_VENDOR_ID_SAMSUNG 0x0419 | 996 | #define USB_VENDOR_ID_SAMSUNG 0x0419 |
| 994 | #define USB_DEVICE_ID_SAMSUNG_IR_REMOTE 0x0001 | 997 | #define USB_DEVICE_ID_SAMSUNG_IR_REMOTE 0x0001 |
| @@ -1125,7 +1125,7 @@ static int logi_dj_recv_query_hidpp_devices(struct dj_receiver_dev *djrcv_dev) · 1124 unmodified lines | |||
| 1125 | HID_REQ_SET_REPORT); | 1125 | HID_REQ_SET_REPORT); |
| 1126 | 1126 | ||
| 1127 | kfree(hidpp_report); | 1127 | kfree(hidpp_report); |
| 1128 | return retval; | 1128 | return (retval < 0) ? retval : 0; |
| 1129 | } | 1129 | } |
| 1130 | 1130 | ||
| 1131 | static int logi_dj_recv_query_paired_devices(struct dj_receiver_dev *djrcv_dev) | 1131 | static int logi_dj_recv_query_paired_devices(struct dj_receiver_dev *djrcv_dev) |
| @@ -1832,13 +1832,17 @@ static const struct hid_device_id logi_dj_receivers[] = { · 700 unmodified lines | |||
| 1832 | HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, | 1832 | HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, |
| 1833 | USB_DEVICE_ID_LOGITECH_NANO_RECEIVER_2), | 1833 | USB_DEVICE_ID_LOGITECH_NANO_RECEIVER_2), |
| 1834 | .driver_data = recvr_type_hidpp}, | 1834 | .driver_data = recvr_type_hidpp}, |
| 1835 | { /* Logitech gaming receiver (0xc539) */ | 1835 | { /* Logitech lightspeed receiver (0xc539) */ |
| 1836 | HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, | 1836 | HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, |
| 1837 | USB_DEVICE_ID_LOGITECH_NANO_RECEIVER_GAMING), | 1837 | USB_DEVICE_ID_LOGITECH_NANO_RECEIVER_LIGHTSPEED), |
| 1838 | .driver_data = recvr_type_gaming_hidpp}, | 1838 | .driver_data = recvr_type_gaming_hidpp}, |
| 1839 | { /* Logitech 27 MHz HID++ 1.0 receiver (0xc513) */ | 1839 | { /* Logitech 27 MHz HID++ 1.0 receiver (0xc513) */ |
| 1840 | HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_MX3000_RECEIVER), | 1840 | HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_MX3000_RECEIVER), |
| 1841 | .driver_data = recvr_type_27mhz}, | 1841 | .driver_data = recvr_type_27mhz}, |
| 1842 | { /* Logitech powerplay receiver (0xc53a) */ | ||
| 1843 | HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, | ||
| 1844 | USB_DEVICE_ID_LOGITECH_NANO_RECEIVER_POWERPLAY), | ||
| 1845 | .driver_data = recvr_type_gaming_hidpp}, | ||
| 1842 | { /* Logitech 27 MHz HID++ 1.0 receiver (0xc517) */ | 1846 | { /* Logitech 27 MHz HID++ 1.0 receiver (0xc517) */ |
| 1843 | HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, | 1847 | HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, |
| 1844 | USB_DEVICE_ID_S510_RECEIVER_2), | 1848 | USB_DEVICE_ID_S510_RECEIVER_2), |
| @@ -3749,15 +3749,45 @@ static const struct hid_device_id hidpp_devices[] = { · 3748 unmodified lines | |||
| 3749 | 3749 | ||
| 3750 | { L27MHZ_DEVICE(HID_ANY_ID) }, | 3750 | { L27MHZ_DEVICE(HID_ANY_ID) }, |
| 3751 | 3751 | ||
| 3752 | { /* Logitech G403 Gaming Mouse over USB */ | 3752 | { /* Logitech G203/Prodigy Gaming Mouse */ |
| 3753 | HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, 0xC084) }, | ||
| 3754 | { /* Logitech G302 Gaming Mouse */ | ||
| 3755 | HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, 0xC07F) }, | ||
| 3756 | { /* Logitech G303 Gaming Mouse */ | ||
| 3757 | HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, 0xC080) }, | ||
| 3758 | { /* Logitech G400 Gaming Mouse */ | ||
| 3759 | HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, 0xC07E) }, | ||
| 3760 | { /* Logitech G403 Wireless Gaming Mouse over USB */ | ||
| 3753 | HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, 0xC082) }, | 3761 | HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, 0xC082) }, |
| 3762 | { /* Logitech G403 Gaming Mouse */ | ||
| 3763 | HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, 0xC083) }, | ||
| 3764 | { /* Logitech G403 Hero Gaming Mouse over USB */ | ||
| 3765 | HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, 0xC08F) }, | ||
| 3766 | { /* Logitech G502 Proteus Core Gaming Mouse */ | ||
| 3767 | HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, 0xC07D) }, | ||
| 3768 | { /* Logitech G502 Proteus Spectrum Gaming Mouse over USB */ | ||
| 3769 | HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, 0xC332) }, | ||
| 3770 | { /* Logitech G502 Hero Gaming Mouse over USB */ | ||
| 3771 | HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, 0xC08B) }, | ||
| 3754 | { /* Logitech G700 Gaming Mouse over USB */ | 3772 | { /* Logitech G700 Gaming Mouse over USB */ |
| 3755 | HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, 0xC06B) }, | 3773 | HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, 0xC06B) }, |
| 3774 | { /* Logitech G700s Gaming Mouse over USB */ | ||
| 3775 | HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, 0xC07C) }, | ||
| 3776 | { /* Logitech G703 Gaming Mouse over USB */ | ||
| 3777 | HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, 0xC087) }, | ||
| 3778 | { /* Logitech G703 Hero Gaming Mouse over USB */ | ||
| 3779 | HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, 0xC090) }, | ||
| 3756 | { /* Logitech G900 Gaming Mouse over USB */ | 3780 | { /* Logitech G900 Gaming Mouse over USB */ |
| 3757 | HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, 0xC081) }, | 3781 | HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, 0xC081) }, |
| 3782 | { /* Logitech G903 Gaming Mouse over USB */ | ||
| 3783 | HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, 0xC086) }, | ||
| 3784 | { /* Logitech G903 Hero Gaming Mouse over USB */ | ||
| 3785 | HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, 0xC091) }, | ||
| 3758 | { /* Logitech G920 Wheel over USB */ | 3786 | { /* Logitech G920 Wheel over USB */ |
| 3759 | HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_G920_WHEEL), | 3787 | HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_G920_WHEEL), |
| 3760 | .driver_data = HIDPP_QUIRK_CLASS_G920 | HIDPP_QUIRK_FORCE_OUTPUT_REPORTS}, | 3788 | .driver_data = HIDPP_QUIRK_CLASS_G920 | HIDPP_QUIRK_FORCE_OUTPUT_REPORTS}, |
| 3789 | { /* Logitech G Pro Gaming Mouse over USB */ | ||
| 3790 | HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, 0xC088) }, | ||
| 3761 | 3791 | ||
| 3762 | { /* MX5000 keyboard over Bluetooth */ | 3792 | { /* MX5000 keyboard over Bluetooth */ |
| 3763 | HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_LOGITECH, 0xb305), | 3793 | HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_LOGITECH, 0xb305), |
| @@ -92,6 +92,7 @@ static const struct hid_device_id hid_quirks[] = { · 91 unmodified lines | |||
| 92 | { HID_USB_DEVICE(USB_VENDOR_ID_HP, USB_PRODUCT_ID_HP_LOGITECH_OEM_USB_OPTICAL_MOUSE_0B4A), HID_QUIRK_ALWAYS_POLL }, | 92 | { HID_USB_DEVICE(USB_VENDOR_ID_HP, USB_PRODUCT_ID_HP_LOGITECH_OEM_USB_OPTICAL_MOUSE_0B4A), HID_QUIRK_ALWAYS_POLL }, |
| 93 | { HID_USB_DEVICE(USB_VENDOR_ID_HP, USB_PRODUCT_ID_HP_PIXART_OEM_USB_OPTICAL_MOUSE), HID_QUIRK_ALWAYS_POLL }, | 93 | { HID_USB_DEVICE(USB_VENDOR_ID_HP, USB_PRODUCT_ID_HP_PIXART_OEM_USB_OPTICAL_MOUSE), HID_QUIRK_ALWAYS_POLL }, |
| 94 | { HID_USB_DEVICE(USB_VENDOR_ID_HP, USB_PRODUCT_ID_HP_PIXART_OEM_USB_OPTICAL_MOUSE_094A), HID_QUIRK_ALWAYS_POLL }, | 94 | { HID_USB_DEVICE(USB_VENDOR_ID_HP, USB_PRODUCT_ID_HP_PIXART_OEM_USB_OPTICAL_MOUSE_094A), HID_QUIRK_ALWAYS_POLL }, |
| 95 | { HID_USB_DEVICE(USB_VENDOR_ID_HP, USB_PRODUCT_ID_HP_PIXART_OEM_USB_OPTICAL_MOUSE_0641), HID_QUIRK_ALWAYS_POLL }, | ||
| 95 | { HID_USB_DEVICE(USB_VENDOR_ID_IDEACOM, USB_DEVICE_ID_IDEACOM_IDC6680), HID_QUIRK_MULTI_INPUT }, | 96 | { HID_USB_DEVICE(USB_VENDOR_ID_IDEACOM, USB_DEVICE_ID_IDEACOM_IDC6680), HID_QUIRK_MULTI_INPUT }, |
| 96 | { HID_USB_DEVICE(USB_VENDOR_ID_INNOMEDIA, USB_DEVICE_ID_INNEX_GENESIS_ATARI), HID_QUIRK_MULTI_INPUT }, | 97 | { HID_USB_DEVICE(USB_VENDOR_ID_INNOMEDIA, USB_DEVICE_ID_INNEX_GENESIS_ATARI), HID_QUIRK_MULTI_INPUT }, |
| 97 | { HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_EASYPEN_M610X), HID_QUIRK_MULTI_INPUT }, | 98 | { HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_EASYPEN_M610X), HID_QUIRK_MULTI_INPUT }, |
| @@ -141,6 +142,7 @@ static const struct hid_device_id hid_quirks[] = { · 43 unmodified lines | |||
| 141 | { HID_USB_DEVICE(USB_VENDOR_ID_RETROUSB, USB_DEVICE_ID_RETROUSB_SNES_RETROPAD), HID_QUIRK_INCREMENT_USAGE_ON_DUPLICATE }, | 142 | { HID_USB_DEVICE(USB_VENDOR_ID_RETROUSB, USB_DEVICE_ID_RETROUSB_SNES_RETROPAD), HID_QUIRK_INCREMENT_USAGE_ON_DUPLICATE }, |
| 142 | { HID_USB_DEVICE(USB_VENDOR_ID_RETROUSB, USB_DEVICE_ID_RETROUSB_SNES_RETROPORT), HID_QUIRK_INCREMENT_USAGE_ON_DUPLICATE }, | 143 | { HID_USB_DEVICE(USB_VENDOR_ID_RETROUSB, USB_DEVICE_ID_RETROUSB_SNES_RETROPORT), HID_QUIRK_INCREMENT_USAGE_ON_DUPLICATE }, |
| 143 | { HID_USB_DEVICE(USB_VENDOR_ID_SAITEK, USB_DEVICE_ID_SAITEK_RUMBLEPAD), HID_QUIRK_BADPAD }, | 144 | { HID_USB_DEVICE(USB_VENDOR_ID_SAITEK, USB_DEVICE_ID_SAITEK_RUMBLEPAD), HID_QUIRK_BADPAD }, |
| 145 | { HID_USB_DEVICE(USB_VENDOR_ID_SAITEK, USB_DEVICE_ID_SAITEK_X52), HID_QUIRK_INCREMENT_USAGE_ON_DUPLICATE }, | ||
| 144 | { HID_USB_DEVICE(USB_VENDOR_ID_SEMICO, USB_DEVICE_ID_SEMICO_USB_KEYKOARD2), HID_QUIRK_NO_INIT_REPORTS }, | 146 | { HID_USB_DEVICE(USB_VENDOR_ID_SEMICO, USB_DEVICE_ID_SEMICO_USB_KEYKOARD2), HID_QUIRK_NO_INIT_REPORTS }, |
| 145 | { HID_USB_DEVICE(USB_VENDOR_ID_SEMICO, USB_DEVICE_ID_SEMICO_USB_KEYKOARD), HID_QUIRK_NO_INIT_REPORTS }, | 147 | { HID_USB_DEVICE(USB_VENDOR_ID_SEMICO, USB_DEVICE_ID_SEMICO_USB_KEYKOARD), HID_QUIRK_NO_INIT_REPORTS }, |
| 146 | { HID_USB_DEVICE(USB_VENDOR_ID_SENNHEISER, USB_DEVICE_ID_SENNHEISER_BTD500USB), HID_QUIRK_NOGET }, | 148 | { HID_USB_DEVICE(USB_VENDOR_ID_SENNHEISER, USB_DEVICE_ID_SENNHEISER_BTD500USB), HID_QUIRK_NOGET }, |
| @@ -585,10 +585,14 @@ static void sony_set_leds(struct sony_sc *sc); · 584 unmodified lines | |||
| 585 | static inline void sony_schedule_work(struct sony_sc *sc, | 585 | static inline void sony_schedule_work(struct sony_sc *sc, |
| 586 | enum sony_worker which) | 586 | enum sony_worker which) |
| 587 | { | 587 | { |
| 588 | unsigned long flags; | ||
| 589 | |||
| 588 | switch (which) { | 590 | switch (which) { |
| 589 | case SONY_WORKER_STATE: | 591 | case SONY_WORKER_STATE: |
| 590 | if (!sc->defer_initialization) | 592 | spin_lock_irqsave(&sc->lock, flags); |
| 593 | if (!sc->defer_initialization && sc->state_worker_initialized) | ||
| 591 | schedule_work(&sc->state_worker); | 594 | schedule_work(&sc->state_worker); |
| 595 | spin_unlock_irqrestore(&sc->lock, flags); | ||
| 592 | break; | 596 | break; |
| 593 | case SONY_WORKER_HOTPLUG: | 597 | case SONY_WORKER_HOTPLUG: |
| 594 | if (sc->hotplug_worker_initialized) | 598 | if (sc->hotplug_worker_initialized) |
| @@ -2558,13 +2562,18 @@ static inline void sony_init_output_report(struct sony_sc *sc, · 1963 unmodified lines | |||
| 2558 | 2562 | ||
| 2559 | static inline void sony_cancel_work_sync(struct sony_sc *sc) | 2563 | static inline void sony_cancel_work_sync(struct sony_sc *sc) |
| 2560 | { | 2564 | { |
| 2565 | unsigned long flags; | ||
| 2566 | |||
| 2561 | if (sc->hotplug_worker_initialized) | 2567 | if (sc->hotplug_worker_initialized) |
| 2562 | cancel_work_sync(&sc->hotplug_worker); | 2568 | cancel_work_sync(&sc->hotplug_worker); |
| 2563 | if (sc->state_worker_initialized) | 2569 | if (sc->state_worker_initialized) { |
| 2570 | spin_lock_irqsave(&sc->lock, flags); | ||
| 2571 | sc->state_worker_initialized = 0; | ||
| 2572 | spin_unlock_irqrestore(&sc->lock, flags); | ||
| 2564 | cancel_work_sync(&sc->state_worker); | 2573 | cancel_work_sync(&sc->state_worker); |
| 2574 | } | ||
| 2565 | } | 2575 | } |
| 2566 | 2576 | ||
| 2567 | |||
| 2568 | static int sony_input_configured(struct hid_device *hdev, | 2577 | static int sony_input_configured(struct hid_device *hdev, |
| 2569 | struct hid_input *hidinput) | 2578 | struct hid_input *hidinput) |
| 2570 | { | 2579 | { |
| @@ -22,6 +22,8 @@ · 21 unmodified lines | |||
| 22 | 22 | ||
| 23 | #include "hid-ids.h" | 23 | #include "hid-ids.h" |
| 24 | 24 | ||
| 25 | #define THRUSTMASTER_DEVICE_ID_2_IN_1_DT 0xb320 | ||
| 26 | |||
| 25 | static const signed short ff_rumble[] = { | 27 | static const signed short ff_rumble[] = { |
| 26 | FF_RUMBLE, | 28 | FF_RUMBLE, |
| 27 | -1 | 29 | -1 |
| @@ -76,6 +78,7 @@ static int tmff_play(struct input_dev *dev, void *data, · 48 unmodified lines | |||
| 76 | struct hid_field *ff_field = tmff->ff_field; | 78 | struct hid_field *ff_field = tmff->ff_field; |
| 77 | int x, y; | 79 | int x, y; |
| 78 | int left, right; /* Rumbling */ | 80 | int left, right; /* Rumbling */ |
| 81 | int motor_swap; | ||
| 79 | 82 | ||
| 80 | switch (effect->type) { | 83 | switch (effect->type) { |
| 81 | case FF_CONSTANT: | 84 | case FF_CONSTANT: |
| @@ -100,6 +103,13 @@ static int tmff_play(struct input_dev *dev, void *data, · 18 unmodified lines | |||
| 100 | ff_field->logical_minimum, | 103 | ff_field->logical_minimum, |
| 101 | ff_field->logical_maximum); | 104 | ff_field->logical_maximum); |
| 102 | 105 | ||
| 106 | /* 2-in-1 strong motor is left */ | ||
| 107 | if (hid->product == THRUSTMASTER_DEVICE_ID_2_IN_1_DT) { | ||
| 108 | motor_swap = left; | ||
| 109 | left = right; | ||
| 110 | right = motor_swap; | ||
| 111 | } | ||
| 112 | |||
| 103 | dbg_hid("(left,right)=(%08x, %08x)\n", left, right); | 113 | dbg_hid("(left,right)=(%08x, %08x)\n", left, right); |
| 104 | ff_field->value[0] = left; | 114 | ff_field->value[0] = left; |
| 105 | ff_field->value[1] = right; | 115 | ff_field->value[1] = right; |
| @@ -226,6 +236,8 @@ static const struct hid_device_id tm_devices[] = { · 120 unmodified lines | |||
| 226 | .driver_data = (unsigned long)ff_rumble }, | 236 | .driver_data = (unsigned long)ff_rumble }, |
| 227 | { HID_USB_DEVICE(USB_VENDOR_ID_THRUSTMASTER, 0xb304), /* FireStorm Dual Power 2 (and 3) */ | 237 | { HID_USB_DEVICE(USB_VENDOR_ID_THRUSTMASTER, 0xb304), /* FireStorm Dual Power 2 (and 3) */ |
| 228 | .driver_data = (unsigned long)ff_rumble }, | 238 | .driver_data = (unsigned long)ff_rumble }, |
| 239 | { HID_USB_DEVICE(USB_VENDOR_ID_THRUSTMASTER, THRUSTMASTER_DEVICE_ID_2_IN_1_DT), /* Dual Trigger 2-in-1 */ | ||
| 240 | .driver_data = (unsigned long)ff_rumble }, | ||
| 229 | { HID_USB_DEVICE(USB_VENDOR_ID_THRUSTMASTER, 0xb323), /* Dual Trigger 3-in-1 (PC Mode) */ | 241 | { HID_USB_DEVICE(USB_VENDOR_ID_THRUSTMASTER, 0xb323), /* Dual Trigger 3-in-1 (PC Mode) */ |
| 230 | .driver_data = (unsigned long)ff_rumble }, | 242 | .driver_data = (unsigned long)ff_rumble }, |
| 231 | { HID_USB_DEVICE(USB_VENDOR_ID_THRUSTMASTER, 0xb324), /* Dual Trigger 3-in-1 (PS3 Mode) */ | 243 | { HID_USB_DEVICE(USB_VENDOR_ID_THRUSTMASTER, 0xb324), /* Dual Trigger 3-in-1 (PS3 Mode) */ |
| @@ -284,6 +284,14 @@ static int hiddev_open(struct inode *inode, struct file *file) · 283 unmodified lines | |||
| 284 | spin_unlock_irq(&list->hiddev->list_lock); | 284 | spin_unlock_irq(&list->hiddev->list_lock); |
| 285 | 285 | ||
| 286 | mutex_lock(&hiddev->existancelock); | 286 | mutex_lock(&hiddev->existancelock); |
| 287 | /* | ||
| 288 | * recheck exist with existance lock held to | ||
| 289 | * avoid opening a disconnected device | ||
| 290 | */ | ||
| 291 | if (!list->hiddev->exist) { | ||
| 292 | res = -ENODEV; | ||
| 293 | goto bail_unlock; | ||
| 294 | } | ||
| 287 | if (!list->hiddev->open++) | 295 | if (!list->hiddev->open++) |
| 288 | if (list->hiddev->exist) { | 296 | if (list->hiddev->exist) { |
| 289 | struct hid_device *hid = hiddev->hid; | 297 | struct hid_device *hid = hiddev->hid; |
| @@ -300,6 +308,10 @@ bail_normal_power: · 10 unmodified lines | |||
| 300 | hid_hw_power(hid, PM_HINT_NORMAL); | 308 | hid_hw_power(hid, PM_HINT_NORMAL); |
| 301 | bail_unlock: | 309 | bail_unlock: |
| 302 | mutex_unlock(&hiddev->existancelock); | 310 | mutex_unlock(&hiddev->existancelock); |
| 311 | |||
| 312 | spin_lock_irq(&list->hiddev->list_lock); | ||
| 313 | list_del(&list->node); | ||
| 314 | spin_unlock_irq(&list->hiddev->list_lock); | ||
| 303 | bail: | 315 | bail: |
| 304 | file->private_data = NULL; | 316 | file->private_data = NULL; |
| 305 | vfree(list); | 317 | vfree(list); |
| @@ -533,14 +533,14 @@ static int wacom_intuos_pad(struct wacom_wac *wacom) · 532 unmodified lines | |||
| 533 | */ | 533 | */ |
| 534 | buttons = (data[4] << 1) | (data[3] & 0x01); | 534 | buttons = (data[4] << 1) | (data[3] & 0x01); |
| 535 | } else if (features->type == CINTIQ_COMPANION_2) { | 535 | } else if (features->type == CINTIQ_COMPANION_2) { |
| 536 | /* d-pad right -> data[4] & 0x10 | 536 | /* d-pad right -> data[2] & 0x10 |
| 537 | * d-pad up -> data[4] & 0x20 | 537 | * d-pad up -> data[2] & 0x20 |
| 538 | * d-pad left -> data[4] & 0x40 | 538 | * d-pad left -> data[2] & 0x40 |
| 539 | * d-pad down -> data[4] & 0x80 | 539 | * d-pad down -> data[2] & 0x80 |
| 540 | * d-pad center -> data[3] & 0x01 | 540 | * d-pad center -> data[1] & 0x01 |
| 541 | */ | 541 | */ |
| 542 | buttons = ((data[2] >> 4) << 7) | | 542 | buttons = ((data[2] >> 4) << 7) | |
| 543 | ((data[1] & 0x04) << 6) | | 543 | ((data[1] & 0x04) << 4) | |
| 544 | ((data[2] & 0x0F) << 2) | | 544 | ((data[2] & 0x0F) << 2) | |
| 545 | (data[1] & 0x03); | 545 | (data[1] & 0x03); |
| 546 | } else if (features->type >= INTUOS5S && features->type <= INTUOSPL) { | 546 | } else if (features->type >= INTUOS5S && features->type <= INTUOSPL) { |
| @@ -1,4 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | 2 | ||
| 3 | #undef TRACE_SYSTEM | 3 | #undef TRACE_SYSTEM |
| 4 | #define TRACE_SYSTEM hyperv | 4 | #define TRACE_SYSTEM hyperv |
| @@ -343,7 +343,7 @@ lm75_probe(struct i2c_client *client, const struct i2c_device_id *id) · 342 unmodified lines | |||
| 343 | data->sample_time = MSEC_PER_SEC / 2; | 343 | data->sample_time = MSEC_PER_SEC / 2; |
| 344 | break; | 344 | break; |
| 345 | case tmp75b: /* not one-shot mode, Conversion rate 37Hz */ | 345 | case tmp75b: /* not one-shot mode, Conversion rate 37Hz */ |
| 346 | clr_mask |= 1 << 15 | 0x3 << 13; | 346 | clr_mask |= 1 << 7 | 0x3 << 5; |
| 347 | data->resolution = 12; | 347 | data->resolution = 12; |
| 348 | data->sample_time = MSEC_PER_SEC / 37; | 348 | data->sample_time = MSEC_PER_SEC / 37; |
| 349 | break; | 349 | break; |
| @@ -852,7 +852,7 @@ static const u16 NCT6106_REG_TARGET[] = { 0x111, 0x121, 0x131 }; · 851 unmodified lines | |||
| 852 | static const u16 NCT6106_REG_WEIGHT_TEMP_SEL[] = { 0x168, 0x178, 0x188 }; | 852 | static const u16 NCT6106_REG_WEIGHT_TEMP_SEL[] = { 0x168, 0x178, 0x188 }; |
| 853 | static const u16 NCT6106_REG_WEIGHT_TEMP_STEP[] = { 0x169, 0x179, 0x189 }; | 853 | static const u16 NCT6106_REG_WEIGHT_TEMP_STEP[] = { 0x169, 0x179, 0x189 }; |
| 854 | static const u16 NCT6106_REG_WEIGHT_TEMP_STEP_TOL[] = { 0x16a, 0x17a, 0x18a }; | 854 | static const u16 NCT6106_REG_WEIGHT_TEMP_STEP_TOL[] = { 0x16a, 0x17a, 0x18a }; |
| 855 | static const u16 NCT6106_REG_WEIGHT_DUTY_STEP[] = { 0x16b, 0x17b, 0x17c }; | 855 | static const u16 NCT6106_REG_WEIGHT_DUTY_STEP[] = { 0x16b, 0x17b, 0x18b }; |
| 856 | static const u16 NCT6106_REG_WEIGHT_TEMP_BASE[] = { 0x16c, 0x17c, 0x18c }; | 856 | static const u16 NCT6106_REG_WEIGHT_TEMP_BASE[] = { 0x16c, 0x17c, 0x18c }; |
| 857 | static const u16 NCT6106_REG_WEIGHT_DUTY_BASE[] = { 0x16d, 0x17d, 0x18d }; | 857 | static const u16 NCT6106_REG_WEIGHT_DUTY_BASE[] = { 0x16d, 0x17d, 0x18d }; |
| 858 | 858 | ||
| @@ -3764,6 +3764,7 @@ static int nct6775_probe(struct platform_device *pdev) · 2905 unmodified lines | |||
| 3764 | data->REG_FAN_TIME[0] = NCT6106_REG_FAN_STOP_TIME; | 3764 | data->REG_FAN_TIME[0] = NCT6106_REG_FAN_STOP_TIME; |
| 3765 | data->REG_FAN_TIME[1] = NCT6106_REG_FAN_STEP_UP_TIME; | 3765 | data->REG_FAN_TIME[1] = NCT6106_REG_FAN_STEP_UP_TIME; |
| 3766 | data->REG_FAN_TIME[2] = NCT6106_REG_FAN_STEP_DOWN_TIME; | 3766 | data->REG_FAN_TIME[2] = NCT6106_REG_FAN_STEP_DOWN_TIME; |
| 3767 | data->REG_TOLERANCE_H = NCT6106_REG_TOLERANCE_H; | ||
| 3767 | data->REG_PWM[0] = NCT6106_REG_PWM; | 3768 | data->REG_PWM[0] = NCT6106_REG_PWM; |
| 3768 | data->REG_PWM[1] = NCT6106_REG_FAN_START_OUTPUT; | 3769 | data->REG_PWM[1] = NCT6106_REG_FAN_START_OUTPUT; |
| 3769 | data->REG_PWM[2] = NCT6106_REG_FAN_STOP_OUTPUT; | 3770 | data->REG_PWM[2] = NCT6106_REG_FAN_STOP_OUTPUT; |
| @@ -704,7 +704,7 @@ static struct attribute *nct7802_in_attrs[] = { · 703 unmodified lines | |||
| 704 | &sensor_dev_attr_in3_alarm.dev_attr.attr, | 704 | &sensor_dev_attr_in3_alarm.dev_attr.attr, |
| 705 | &sensor_dev_attr_in3_beep.dev_attr.attr, | 705 | &sensor_dev_attr_in3_beep.dev_attr.attr, |
| 706 | 706 | ||
| 707 | &sensor_dev_attr_in4_input.dev_attr.attr, /* 17 */ | 707 | &sensor_dev_attr_in4_input.dev_attr.attr, /* 16 */ |
| 708 | &sensor_dev_attr_in4_min.dev_attr.attr, | 708 | &sensor_dev_attr_in4_min.dev_attr.attr, |
| 709 | &sensor_dev_attr_in4_max.dev_attr.attr, | 709 | &sensor_dev_attr_in4_max.dev_attr.attr, |
| 710 | &sensor_dev_attr_in4_alarm.dev_attr.attr, | 710 | &sensor_dev_attr_in4_alarm.dev_attr.attr, |
| @@ -730,9 +730,9 @@ static umode_t nct7802_in_is_visible(struct kobject *kobj, · 19 unmodified lines | |||
| 730 | 730 | ||
| 731 | if (index >= 6 && index < 11 && (reg & 0x03) != 0x03) /* VSEN1 */ | 731 | if (index >= 6 && index < 11 && (reg & 0x03) != 0x03) /* VSEN1 */ |
| 732 | return 0; | 732 | return 0; |
| 733 | if (index >= 11 && index < 17 && (reg & 0x0c) != 0x0c) /* VSEN2 */ | 733 | if (index >= 11 && index < 16 && (reg & 0x0c) != 0x0c) /* VSEN2 */ |
| 734 | return 0; | 734 | return 0; |
| 735 | if (index >= 17 && (reg & 0x30) != 0x30) /* VSEN3 */ | 735 | if (index >= 16 && (reg & 0x30) != 0x30) /* VSEN3 */ |
| 736 | return 0; | 736 | return 0; |
| 737 | 737 | ||
| 738 | return attr->mode; | 738 | return attr->mode; |
| @@ -408,8 +408,10 @@ static ssize_t occ_show_power_1(struct device *dev, · 407 unmodified lines | |||
| 408 | 408 | ||
| 409 | static u64 occ_get_powr_avg(u64 *accum, u32 *samples) | 409 | static u64 occ_get_powr_avg(u64 *accum, u32 *samples) |
| 410 | { | 410 | { |
| 411 | return div64_u64(get_unaligned_be64(accum) * 1000000ULL, | 411 | u64 divisor = get_unaligned_be32(samples); |
| 412 | get_unaligned_be32(samples)); | 412 | |
| 413 | return (divisor == 0) ? 0 : | ||
| 414 | div64_u64(get_unaligned_be64(accum) * 1000000ULL, divisor); | ||
| 413 | } | 415 | } |
| 414 | 416 | ||
| 415 | static ssize_t occ_show_power_2(struct device *dev, | 417 | static ssize_t occ_show_power_2(struct device *dev, |
| @@ -544,6 +544,7 @@ int etm_perf_add_symlink_sink(struct coresight_device *csdev) · 543 unmodified lines | |||
| 544 | /* See function coresight_get_sink_by_id() to know where this is used */ | 544 | /* See function coresight_get_sink_by_id() to know where this is used */ |
| 545 | hash = hashlen_hash(hashlen_string(NULL, name)); | 545 | hash = hashlen_hash(hashlen_string(NULL, name)); |
| 546 | 546 | ||
| 547 | sysfs_attr_init(&ea->attr.attr); | ||
| 547 | ea->attr.attr.name = devm_kstrdup(dev, name, GFP_KERNEL); | 548 | ea->attr.attr.name = devm_kstrdup(dev, name, GFP_KERNEL); |
| 548 | if (!ea->attr.attr.name) | 549 | if (!ea->attr.attr.name) |
| 549 | return -ENOMEM; | 550 | return -ENOMEM; |
| @@ -1,4 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* | 2 | /* |
| 3 | * Intel(R) Trace Hub Memory Storage Unit (MSU) data structures | 3 | * Intel(R) Trace Hub Memory Storage Unit (MSU) data structures |
| 4 | * | 4 | * |
| @@ -1,4 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* | 2 | /* |
| 3 | * Intel(R) Trace Hub PTI output data structures | 3 | * Intel(R) Trace Hub PTI output data structures |
| 4 | * | 4 | * |
| @@ -142,7 +142,7 @@ static struct at91_twi_pdata sama5d4_config = { · 141 unmodified lines | |||
| 142 | 142 | ||
| 143 | static struct at91_twi_pdata sama5d2_config = { | 143 | static struct at91_twi_pdata sama5d2_config = { |
| 144 | .clk_max_div = 7, | 144 | .clk_max_div = 7, |
| 145 | .clk_offset = 4, | 145 | .clk_offset = 3, |
| 146 | .has_unre_flag = true, | 146 | .has_unre_flag = true, |
| 147 | .has_alt_cmd = true, | 147 | .has_alt_cmd = true, |
| 148 | .has_hold_field = true, | 148 | .has_hold_field = true, |
| @@ -122,9 +122,11 @@ static void at91_twi_write_next_byte(struct at91_twi_dev *dev) · 121 unmodified lines | |||
| 122 | writeb_relaxed(*dev->buf, dev->base + AT91_TWI_THR); | 122 | writeb_relaxed(*dev->buf, dev->base + AT91_TWI_THR); |
| 123 | 123 | ||
| 124 | /* send stop when last byte has been written */ | 124 | /* send stop when last byte has been written */ |
| 125 | if (--dev->buf_len == 0) | 125 | if (--dev->buf_len == 0) { |
| 126 | if (!dev->use_alt_cmd) | 126 | if (!dev->use_alt_cmd) |
| 127 | at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP); | 127 | at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP); |
| 128 | at91_twi_write(dev, AT91_TWI_IDR, AT91_TWI_TXRDY); | ||
| 129 | } | ||
| 128 | 130 | ||
| 129 | dev_dbg(dev->dev, "wrote 0x%x, to go %zu\n", *dev->buf, dev->buf_len); | 131 | dev_dbg(dev->dev, "wrote 0x%x, to go %zu\n", *dev->buf, dev->buf_len); |
| 130 | 132 | ||
| @@ -542,9 +544,8 @@ static int at91_do_twi_transfer(struct at91_twi_dev *dev) · 411 unmodified lines | |||
| 542 | } else { | 544 | } else { |
| 543 | at91_twi_write_next_byte(dev); | 545 | at91_twi_write_next_byte(dev); |
| 544 | at91_twi_write(dev, AT91_TWI_IER, | 546 | at91_twi_write(dev, AT91_TWI_IER, |
| 545 | AT91_TWI_TXCOMP | | 547 | AT91_TWI_TXCOMP | AT91_TWI_NACK | |
| 546 | AT91_TWI_NACK | | 548 | (dev->buf_len ? AT91_TWI_TXRDY : 0)); |
| 547 | AT91_TWI_TXRDY); | ||
| 548 | } | 549 | } |
| 549 | } | 550 | } |
| 550 | 551 | ||
| @@ -392,16 +392,18 @@ static bool bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev *iproc_i2c, · 391 unmodified lines | |||
| 392 | static void bcm_iproc_i2c_read_valid_bytes(struct bcm_iproc_i2c_dev *iproc_i2c) | 392 | static void bcm_iproc_i2c_read_valid_bytes(struct bcm_iproc_i2c_dev *iproc_i2c) |
| 393 | { | 393 | { |
| 394 | struct i2c_msg *msg = iproc_i2c->msg; | 394 | struct i2c_msg *msg = iproc_i2c->msg; |
| 395 | uint32_t val; | ||
| 395 | 396 | ||
| 396 | /* Read valid data from RX FIFO */ | 397 | /* Read valid data from RX FIFO */ |
| 397 | while (iproc_i2c->rx_bytes < msg->len) { | 398 | while (iproc_i2c->rx_bytes < msg->len) { |
| 398 | if (!((iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET) >> M_FIFO_RX_CNT_SHIFT) | 399 | val = iproc_i2c_rd_reg(iproc_i2c, M_RX_OFFSET); |
| 399 | & M_FIFO_RX_CNT_MASK)) | 400 | |
| 401 | /* rx fifo empty */ | ||
| 402 | if (!((val >> M_RX_STATUS_SHIFT) & M_RX_STATUS_MASK)) | ||
| 400 | break; | 403 | break; |
| 401 | 404 | ||
| 402 | msg->buf[iproc_i2c->rx_bytes] = | 405 | msg->buf[iproc_i2c->rx_bytes] = |
| 403 | (iproc_i2c_rd_reg(iproc_i2c, M_RX_OFFSET) >> | 406 | (val >> M_RX_DATA_SHIFT) & M_RX_DATA_MASK; |
| 404 | M_RX_DATA_SHIFT) & M_RX_DATA_MASK; | ||
| 405 | iproc_i2c->rx_bytes++; | 407 | iproc_i2c->rx_bytes++; |
| 406 | } | 408 | } |
| 407 | } | 409 | } |
| @@ -69,6 +69,7 @@ struct em_i2c_device { · 68 unmodified lines | |||
| 69 | struct completion msg_done; | 69 | struct completion msg_done; |
| 70 | struct clk *sclk; | 70 | struct clk *sclk; |
| 71 | struct i2c_client *slave; | 71 | struct i2c_client *slave; |
| 72 | int irq; | ||
| 72 | }; | 73 | }; |
| 73 | 74 | ||
| 74 | static inline void em_clear_set_bit(struct em_i2c_device *priv, u8 clear, u8 set, u8 reg) | 75 | static inline void em_clear_set_bit(struct em_i2c_device *priv, u8 clear, u8 set, u8 reg) |
| @@ -339,6 +340,12 @@ static int em_i2c_unreg_slave(struct i2c_client *slave) · 264 unmodified lines | |||
| 339 | 340 | ||
| 340 | writeb(0, priv->base + I2C_OFS_SVA0); | 341 | writeb(0, priv->base + I2C_OFS_SVA0); |
| 341 | 342 | ||
| 343 | /* | ||
| 344 | * Wait for interrupt to finish. New slave irqs cannot happen because we | ||
| 345 | * cleared the slave address and, thus, only extension codes will be | ||
| 346 | * detected which do not use the slave ptr. | ||
| 347 | */ | ||
| 348 | synchronize_irq(priv->irq); | ||
| 342 | priv->slave = NULL; | 349 | priv->slave = NULL; |
| 343 | 350 | ||
| 344 | return 0; | 351 | return 0; |
| @@ -355,7 +362,7 @@ static int em_i2c_probe(struct platform_device *pdev) · 10 unmodified lines | |||
| 355 | { | 362 | { |
| 356 | struct em_i2c_device *priv; | 363 | struct em_i2c_device *priv; |
| 357 | struct resource *r; | 364 | struct resource *r; |
| 358 | int irq, ret; | 365 | int ret; |
| 359 | 366 | ||
| 360 | priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); | 367 | priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); |
| 361 | if (!priv) | 368 | if (!priv) |
| @@ -390,8 +397,8 @@ static int em_i2c_probe(struct platform_device *pdev) · 28 unmodified lines | |||
| 390 | 397 | ||
| 391 | em_i2c_reset(&priv->adap); | 398 | em_i2c_reset(&priv->adap); |
| 392 | 399 | ||
| 393 | irq = platform_get_irq(pdev, 0); | 400 | priv->irq = platform_get_irq(pdev, 0); |
| 394 | ret = devm_request_irq(&pdev->dev, irq, em_i2c_irq_handler, 0, | 401 | ret = devm_request_irq(&pdev->dev, priv->irq, em_i2c_irq_handler, 0, |
| 395 | "em_i2c", priv); | 402 | "em_i2c", priv); |
| 396 | if (ret) | 403 | if (ret) |
| 397 | goto err_clk; | 404 | goto err_clk; |
| @@ -401,7 +408,8 @@ static int em_i2c_probe(struct platform_device *pdev) · 3 unmodified lines | |||
| 401 | if (ret) | 408 | if (ret) |
| 402 | goto err_clk; | 409 | goto err_clk; |
| 403 | 410 | ||
| 404 | dev_info(&pdev->dev, "Added i2c controller %d, irq %d\n", priv->adap.nr, irq); | 411 | dev_info(&pdev->dev, "Added i2c controller %d, irq %d\n", priv->adap.nr, |
| 412 | priv->irq); | ||
| 405 | 413 | ||
| 406 | return 0; | 414 | return 0; |
| 407 | 415 | ||
| @@ -273,8 +273,8 @@ static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx, · 272 unmodified lines | |||
| 273 | } | 273 | } |
| 274 | 274 | ||
| 275 | /* Functions for DMA support */ | 275 | /* Functions for DMA support */ |
| 276 | static int i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx, | 276 | static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx, |
| 277 | dma_addr_t phy_addr) | 277 | dma_addr_t phy_addr) |
| 278 | { | 278 | { |
| 279 | struct imx_i2c_dma *dma; | 279 | struct imx_i2c_dma *dma; |
| 280 | struct dma_slave_config dma_sconfig; | 280 | struct dma_slave_config dma_sconfig; |
| @@ -283,7 +283,7 @@ static int i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx, · 2 unmodified lines | |||
| 283 | 283 | ||
| 284 | dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL); | 284 | dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL); |
| 285 | if (!dma) | 285 | if (!dma) |
| 286 | return -ENOMEM; | 286 | return; |
| 287 | 287 | ||
| 288 | dma->chan_tx = dma_request_chan(dev, "tx"); | 288 | dma->chan_tx = dma_request_chan(dev, "tx"); |
| 289 | if (IS_ERR(dma->chan_tx)) { | 289 | if (IS_ERR(dma->chan_tx)) { |
| @@ -328,7 +328,7 @@ static int i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx, · 38 unmodified lines | |||
| 328 | dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n", | 328 | dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n", |
| 329 | dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx)); | 329 | dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx)); |
| 330 | 330 | ||
| 331 | return 0; | 331 | return; |
| 332 | 332 | ||
| 333 | fail_rx: | 333 | fail_rx: |
| 334 | dma_release_channel(dma->chan_rx); | 334 | dma_release_channel(dma->chan_rx); |
| @@ -336,8 +336,6 @@ fail_tx: · 1 unmodified line | |||
| 336 | dma_release_channel(dma->chan_tx); | 336 | dma_release_channel(dma->chan_tx); |
| 337 | fail_al: | 337 | fail_al: |
| 338 | devm_kfree(dev, dma); | 338 | devm_kfree(dev, dma); |
| 339 | /* return successfully if there is no dma support */ | ||
| 340 | return ret == -ENODEV ? 0 : ret; | ||
| 341 | } | 339 | } |
| 342 | 340 | ||
| 343 | static void i2c_imx_dma_callback(void *arg) | 341 | static void i2c_imx_dma_callback(void *arg) |
| @@ -1165,17 +1163,13 @@ static int i2c_imx_probe(struct platform_device *pdev) · 821 unmodified lines | |||
| 1165 | dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res); | 1163 | dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res); |
| 1166 | dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n", | 1164 | dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n", |
| 1167 | i2c_imx->adapter.name); | 1165 | i2c_imx->adapter.name); |
| 1166 | dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n"); | ||
| 1168 | 1167 | ||
| 1169 | /* Init DMA config if supported */ | 1168 | /* Init DMA config if supported */ |
| 1170 | ret = i2c_imx_dma_request(i2c_imx, phy_addr); | 1169 | i2c_imx_dma_request(i2c_imx, phy_addr); |
| 1171 | if (ret < 0) | ||
| 1172 | goto del_adapter; | ||
| 1173 | 1170 | ||
| 1174 | dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n"); | ||
| 1175 | return 0; /* Return OK */ | 1171 | return 0; /* Return OK */ |
| 1176 | 1172 | ||
| 1177 | del_adapter: | ||
| 1178 | i2c_del_adapter(&i2c_imx->adapter); | ||
| 1179 | clk_notifier_unregister: | 1173 | clk_notifier_unregister: |
| 1180 | clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb); | 1174 | clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb); |
| 1181 | rpm_disable: | 1175 | rpm_disable: |
| @@ -364,7 +364,7 @@ static void gpu_i2c_remove(struct pci_dev *pdev) · 363 unmodified lines | |||
| 364 | /* | 364 | /* |
| 365 | * We need gpu_i2c_suspend() even if it is stub, for runtime pm to work | 365 | * We need gpu_i2c_suspend() even if it is stub, for runtime pm to work |
| 366 | * correctly. Without it, lspci shows runtime pm status as "D0" for the card. | 366 | * correctly. Without it, lspci shows runtime pm status as "D0" for the card. |
| 367 | * Documentation/power/pci.txt also insists for driver to provide this. | 367 | * Documentation/power/pci.rst also insists for driver to provide this. |
| 368 | */ | 368 | */ |
| 369 | static __maybe_unused int gpu_i2c_suspend(struct device *dev) | 369 | static __maybe_unused int gpu_i2c_suspend(struct device *dev) |
| 370 | { | 370 | { |
| @@ -139,6 +139,7 @@ struct rcar_i2c_priv { · 138 unmodified lines | |||
| 139 | enum dma_data_direction dma_direction; | 139 | enum dma_data_direction dma_direction; |
| 140 | 140 | ||
| 141 | struct reset_control *rstc; | 141 | struct reset_control *rstc; |
| 142 | int irq; | ||
| 142 | }; | 143 | }; |
| 143 | 144 | ||
| 144 | #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent) | 145 | #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent) |
| @@ -861,9 +862,11 @@ static int rcar_unreg_slave(struct i2c_client *slave) · 716 unmodified lines | |||
| 861 | 862 | ||
| 862 | WARN_ON(!priv->slave); | 863 | WARN_ON(!priv->slave); |
| 863 | 864 | ||
| 865 | /* disable irqs and ensure none is running before clearing ptr */ | ||
| 864 | rcar_i2c_write(priv, ICSIER, 0); | 866 | rcar_i2c_write(priv, ICSIER, 0); |
| 865 | rcar_i2c_write(priv, ICSCR, 0); | 867 | rcar_i2c_write(priv, ICSCR, 0); |
| 866 | 868 | ||
| 869 | synchronize_irq(priv->irq); | ||
| 867 | priv->slave = NULL; | 870 | priv->slave = NULL; |
| 868 | 871 | ||
| 869 | pm_runtime_put(rcar_i2c_priv_to_dev(priv)); | 872 | pm_runtime_put(rcar_i2c_priv_to_dev(priv)); |
| @@ -918,7 +921,7 @@ static int rcar_i2c_probe(struct platform_device *pdev) · 48 unmodified lines | |||
| 918 | struct i2c_adapter *adap; | 921 | struct i2c_adapter *adap; |
| 919 | struct device *dev = &pdev->dev; | 922 | struct device *dev = &pdev->dev; |
| 920 | struct i2c_timings i2c_t; | 923 | struct i2c_timings i2c_t; |
| 921 | int irq, ret; | 924 | int ret; |
| 922 | 925 | ||
| 923 | /* Otherwise logic will break because some bytes must always use PIO */ | 926 | /* Otherwise logic will break because some bytes must always use PIO */ |
| 924 | BUILD_BUG_ON_MSG(RCAR_MIN_DMA_LEN < 3, "Invalid min DMA length"); | 927 | BUILD_BUG_ON_MSG(RCAR_MIN_DMA_LEN < 3, "Invalid min DMA length"); |
| @@ -984,10 +987,10 @@ static int rcar_i2c_probe(struct platform_device *pdev) · 59 unmodified lines | |||
| 984 | pm_runtime_put(dev); | 987 | pm_runtime_put(dev); |
| 985 | 988 | ||
| 986 | 989 | ||
| 987 | irq = platform_get_irq(pdev, 0); | 990 | priv->irq = platform_get_irq(pdev, 0); |
| 988 | ret = devm_request_irq(dev, irq, rcar_i2c_irq, 0, dev_name(dev), priv); | 991 | ret = devm_request_irq(dev, priv->irq, rcar_i2c_irq, 0, dev_name(dev), priv); |
| 989 | if (ret < 0) { | 992 | if (ret < 0) { |
| 990 | dev_err(dev, "cannot get irq %d\n", irq); | 993 | dev_err(dev, "cannot get irq %d\n", priv->irq); |
| 991 | goto out_pm_disable; | 994 | goto out_pm_disable; |
| 992 | } | 995 | } |
| 993 | 996 | ||
| @@ -435,6 +435,7 @@ static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat) · 434 unmodified lines | |||
| 435 | * fall through to the write state, as we will need to | 435 | * fall through to the write state, as we will need to |
| 436 | * send a byte as well | 436 | * send a byte as well |
| 437 | */ | 437 | */ |
| 438 | /* Fall through */ | ||
| 438 | 439 | ||
| 439 | case STATE_WRITE: | 440 | case STATE_WRITE: |
| 440 | /* | 441 | /* |
| @@ -1,4 +1,4 @@ | |||
| 1 | // SPDX-License-Identifier: GPL-2.0 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* | 2 | /* |
| 3 | * i2c-stm32.h | 3 | * i2c-stm32.h |
| 4 | * | 4 | * |
| @@ -319,7 +319,6 @@ static const struct iio_chan_spec_ext_info cros_ec_accel_legacy_ext_info[] = { · 318 unmodified lines | |||
| 319 | .modified = 1, \ | 319 | .modified = 1, \ |
| 320 | .info_mask_separate = \ | 320 | .info_mask_separate = \ |
| 321 | BIT(IIO_CHAN_INFO_RAW) | \ | 321 | BIT(IIO_CHAN_INFO_RAW) | \ |
| 322 | BIT(IIO_CHAN_INFO_SCALE) | \ | ||
| 323 | BIT(IIO_CHAN_INFO_CALIBBIAS), \ | 322 | BIT(IIO_CHAN_INFO_CALIBBIAS), \ |
| 324 | .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE), \ | 323 | .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE), \ |
| 325 | .ext_info = cros_ec_accel_legacy_ext_info, \ | 324 | .ext_info = cros_ec_accel_legacy_ext_info, \ |
| @@ -11,6 +11,7 @@ · 10 unmodified lines | |||
| 11 | #include <linux/iio/iio.h> | 11 | #include <linux/iio/iio.h> |
| 12 | #include <linux/io.h> | 12 | #include <linux/io.h> |
| 13 | #include <linux/iopoll.h> | 13 | #include <linux/iopoll.h> |
| 14 | #include <linux/kernel.h> | ||
| 14 | #include <linux/module.h> | 15 | #include <linux/module.h> |
| 15 | #include <linux/mutex.h> | 16 | #include <linux/mutex.h> |
| 16 | #include <linux/platform_device.h> | 17 | #include <linux/platform_device.h> |
| @@ -22,8 +23,11 @@ · 5 unmodified lines | |||
| 22 | #define JZ_ADC_REG_ADTCH 0x18 | 23 | #define JZ_ADC_REG_ADTCH 0x18 |
| 23 | #define JZ_ADC_REG_ADBDAT 0x1c | 24 | #define JZ_ADC_REG_ADBDAT 0x1c |
| 24 | #define JZ_ADC_REG_ADSDAT 0x20 | 25 | #define JZ_ADC_REG_ADSDAT 0x20 |
| 26 | #define JZ_ADC_REG_ADCLK 0x28 | ||
| 25 | 27 | ||
| 26 | #define JZ_ADC_REG_CFG_BAT_MD BIT(4) | 28 | #define JZ_ADC_REG_CFG_BAT_MD BIT(4) |
| 29 | #define JZ_ADC_REG_ADCLK_CLKDIV_LSB 0 | ||
| 30 | #define JZ_ADC_REG_ADCLK_CLKDIV10US_LSB 16 | ||
| 27 | 31 | ||
| 28 | #define JZ_ADC_AUX_VREF 3300 | 32 | #define JZ_ADC_AUX_VREF 3300 |
| 29 | #define JZ_ADC_AUX_VREF_BITS 12 | 33 | #define JZ_ADC_AUX_VREF_BITS 12 |
| @@ -34,6 +38,8 @@ · 4 unmodified lines | |||
| 34 | #define JZ4740_ADC_BATTERY_HIGH_VREF (7500 * 0.986) | 38 | #define JZ4740_ADC_BATTERY_HIGH_VREF (7500 * 0.986) |
| 35 | #define JZ4740_ADC_BATTERY_HIGH_VREF_BITS 12 | 39 | #define JZ4740_ADC_BATTERY_HIGH_VREF_BITS 12 |
| 36 | 40 | ||
| 41 | struct ingenic_adc; | ||
| 42 | |||
| 37 | struct ingenic_adc_soc_data { | 43 | struct ingenic_adc_soc_data { |
| 38 | unsigned int battery_high_vref; | 44 | unsigned int battery_high_vref; |
| 39 | unsigned int battery_high_vref_bits; | 45 | unsigned int battery_high_vref_bits; |
| @@ -41,6 +47,7 @@ struct ingenic_adc_soc_data { · 1 unmodified line | |||
| 41 | size_t battery_raw_avail_size; | 47 | size_t battery_raw_avail_size; |
| 42 | const int *battery_scale_avail; | 48 | const int *battery_scale_avail; |
| 43 | size_t battery_scale_avail_size; | 49 | size_t battery_scale_avail_size; |
| 50 | int (*init_clk_div)(struct device *dev, struct ingenic_adc *adc); | ||
| 44 | }; | 51 | }; |
| 45 | 52 | ||
| 46 | struct ingenic_adc { | 53 | struct ingenic_adc { |
| @@ -151,6 +158,42 @@ static const int jz4740_adc_battery_scale_avail[] = { · 104 unmodified lines | |||
| 151 | JZ_ADC_BATTERY_LOW_VREF, JZ_ADC_BATTERY_LOW_VREF_BITS, | 158 | JZ_ADC_BATTERY_LOW_VREF, JZ_ADC_BATTERY_LOW_VREF_BITS, |
| 152 | }; | 159 | }; |
| 153 | 160 | ||
| 161 | static int jz4725b_adc_init_clk_div(struct device *dev, struct ingenic_adc *adc) | ||
| 162 | { | ||
| 163 | struct clk *parent_clk; | ||
| 164 | unsigned long parent_rate, rate; | ||
| 165 | unsigned int div_main, div_10us; | ||
| 166 | |||
| 167 | parent_clk = clk_get_parent(adc->clk); | ||
| 168 | if (!parent_clk) { | ||
| 169 | dev_err(dev, "ADC clock has no parent\n"); | ||
| 170 | return -ENODEV; | ||
| 171 | } | ||
| 172 | parent_rate = clk_get_rate(parent_clk); | ||
| 173 | |||
| 174 | /* | ||
| 175 | * The JZ4725B ADC works at 500 kHz to 8 MHz. | ||
| 176 | * We pick the highest rate possible. | ||
| 177 | * In practice we typically get 6 MHz, half of the 12 MHz EXT clock. | ||
| 178 | */ | ||
| 179 | div_main = DIV_ROUND_UP(parent_rate, 8000000); | ||
| 180 | div_main = clamp(div_main, 1u, 64u); | ||
| 181 | rate = parent_rate / div_main; | ||
| 182 | if (rate < 500000 || rate > 8000000) { | ||
| 183 | dev_err(dev, "No valid divider for ADC main clock\n"); | ||
| 184 | return -EINVAL; | ||
| 185 | } | ||
| 186 | |||
| 187 | /* We also need a divider that produces a 10us clock. */ | ||
| 188 | div_10us = DIV_ROUND_UP(rate, 100000); | ||
| 189 | |||
| 190 | writel(((div_10us - 1) << JZ_ADC_REG_ADCLK_CLKDIV10US_LSB) | | ||
| 191 | (div_main - 1) << JZ_ADC_REG_ADCLK_CLKDIV_LSB, | ||
| 192 | adc->base + JZ_ADC_REG_ADCLK); | ||
| 193 | |||
| 194 | return 0; | ||
| 195 | } | ||
| 196 | |||
| 154 | static const struct ingenic_adc_soc_data jz4725b_adc_soc_data = { | 197 | static const struct ingenic_adc_soc_data jz4725b_adc_soc_data = { |
| 155 | .battery_high_vref = JZ4725B_ADC_BATTERY_HIGH_VREF, | 198 | .battery_high_vref = JZ4725B_ADC_BATTERY_HIGH_VREF, |
| 156 | .battery_high_vref_bits = JZ4725B_ADC_BATTERY_HIGH_VREF_BITS, | 199 | .battery_high_vref_bits = JZ4725B_ADC_BATTERY_HIGH_VREF_BITS, |
| @@ -158,6 +201,7 @@ static const struct ingenic_adc_soc_data jz4725b_adc_soc_data = { · 1 unmodified line | |||
| 158 | .battery_raw_avail_size = ARRAY_SIZE(jz4725b_adc_battery_raw_avail), | 201 | .battery_raw_avail_size = ARRAY_SIZE(jz4725b_adc_battery_raw_avail), |
| 159 | .battery_scale_avail = jz4725b_adc_battery_scale_avail, | 202 | .battery_scale_avail = jz4725b_adc_battery_scale_avail, |
| 160 | .battery_scale_avail_size = ARRAY_SIZE(jz4725b_adc_battery_scale_avail), | 203 | .battery_scale_avail_size = ARRAY_SIZE(jz4725b_adc_battery_scale_avail), |
| 204 | .init_clk_div = jz4725b_adc_init_clk_div, | ||
| 161 | }; | 205 | }; |
| 162 | 206 | ||
| 163 | static const struct ingenic_adc_soc_data jz4740_adc_soc_data = { | 207 | static const struct ingenic_adc_soc_data jz4740_adc_soc_data = { |
| @@ -167,6 +211,7 @@ static const struct ingenic_adc_soc_data jz4740_adc_soc_data = { · 3 unmodified lines | |||
| 167 | .battery_raw_avail_size = ARRAY_SIZE(jz4740_adc_battery_raw_avail), | 211 | .battery_raw_avail_size = ARRAY_SIZE(jz4740_adc_battery_raw_avail), |
| 168 | .battery_scale_avail = jz4740_adc_battery_scale_avail, | 212 | .battery_scale_avail = jz4740_adc_battery_scale_avail, |
| 169 | .battery_scale_avail_size = ARRAY_SIZE(jz4740_adc_battery_scale_avail), | 213 | .battery_scale_avail_size = ARRAY_SIZE(jz4740_adc_battery_scale_avail), |
| 214 | .init_clk_div = NULL, /* no ADCLK register on JZ4740 */ | ||
| 170 | }; | 215 | }; |
| 171 | 216 | ||
| 172 | static int ingenic_adc_read_avail(struct iio_dev *iio_dev, | 217 | static int ingenic_adc_read_avail(struct iio_dev *iio_dev, |
| @@ -317,6 +362,15 @@ static int ingenic_adc_probe(struct platform_device *pdev) · 144 unmodified lines | |||
| 317 | return ret; | 362 | return ret; |
| 318 | } | 363 | } |
| 319 | 364 | ||
| 365 | /* Set clock dividers. */ | ||
| 366 | if (soc_data->init_clk_div) { | ||
| 367 | ret = soc_data->init_clk_div(dev, adc); | ||
| 368 | if (ret) { | ||
| 369 | clk_disable_unprepare(adc->clk); | ||
| 370 | return ret; | ||
| 371 | } | ||
| 372 | } | ||
| 373 | |||
| 320 | /* Put hardware in a known passive state. */ | 374 | /* Put hardware in a known passive state. */ |
| 321 | writeb(0x00, adc->base + JZ_ADC_REG_ENABLE); | 375 | writeb(0x00, adc->base + JZ_ADC_REG_ENABLE); |
| 322 | writeb(0xff, adc->base + JZ_ADC_REG_CTRL); | 376 | writeb(0xff, adc->base + JZ_ADC_REG_CTRL); |
| @@ -83,7 +83,7 @@ · 82 unmodified lines | |||
| 83 | #define MAX9611_TEMP_MAX_POS 0x7f80 | 83 | #define MAX9611_TEMP_MAX_POS 0x7f80 |
| 84 | #define MAX9611_TEMP_MAX_NEG 0xff80 | 84 | #define MAX9611_TEMP_MAX_NEG 0xff80 |
| 85 | #define MAX9611_TEMP_MIN_NEG 0xd980 | 85 | #define MAX9611_TEMP_MIN_NEG 0xd980 |
| 86 | #define MAX9611_TEMP_MASK GENMASK(7, 15) | 86 | #define MAX9611_TEMP_MASK GENMASK(15, 7) |
| 87 | #define MAX9611_TEMP_SHIFT 0x07 | 87 | #define MAX9611_TEMP_SHIFT 0x07 |
| 88 | #define MAX9611_TEMP_RAW(_r) ((_r) >> MAX9611_TEMP_SHIFT) | 88 | #define MAX9611_TEMP_RAW(_r) ((_r) >> MAX9611_TEMP_SHIFT) |
| 89 | #define MAX9611_TEMP_SCALE_NUM 1000000 | 89 | #define MAX9611_TEMP_SCALE_NUM 1000000 |
| @@ -480,7 +480,7 @@ static int max9611_init(struct max9611_dev *max9611) · 390 unmodified lines | |||
| 480 | if (ret) | 480 | if (ret) |
| 481 | return ret; | 481 | return ret; |
| 482 | 482 | ||
| 483 | regval = ret & MAX9611_TEMP_MASK; | 483 | regval &= MAX9611_TEMP_MASK; |
| 484 | 484 | ||
| 485 | if ((regval > MAX9611_TEMP_MAX_POS && | 485 | if ((regval > MAX9611_TEMP_MAX_POS && |
| 486 | regval < MAX9611_TEMP_MIN_NEG) || | 486 | regval < MAX9611_TEMP_MIN_NEG) || |
| @@ -382,7 +382,7 @@ static int rcar_gyroadc_parse_subdevs(struct iio_dev *indio_dev) · 381 unmodified lines | |||
| 382 | dev_err(dev, | 382 | dev_err(dev, |
| 383 | "Only %i channels supported with %pOFn, but reg = <%i>.\n", | 383 | "Only %i channels supported with %pOFn, but reg = <%i>.\n", |
| 384 | num_channels, child, reg); | 384 | num_channels, child, reg); |
| 385 | return ret; | 385 | return -EINVAL; |
| 386 | } | 386 | } |
| 387 | } | 387 | } |
| 388 | 388 | ||
| @@ -391,7 +391,7 @@ static int rcar_gyroadc_parse_subdevs(struct iio_dev *indio_dev) · 2 unmodified lines | |||
| 391 | dev_err(dev, | 391 | dev_err(dev, |
| 392 | "Channel %i uses different ADC mode than the rest.\n", | 392 | "Channel %i uses different ADC mode than the rest.\n", |
| 393 | reg); | 393 | reg); |
| 394 | return ret; | 394 | return -EINVAL; |
| 395 | } | 395 | } |
| 396 | 396 | ||
| 397 | /* Channel is valid, grab the regulator. */ | 397 | /* Channel is valid, grab the regulator. */ |
| @@ -276,11 +276,11 @@ static int adf4371_set_freq(struct adf4371_state *st, unsigned long long freq, · 275 unmodified lines | |||
| 276 | st->buf[0] = st->integer >> 8; | 276 | st->buf[0] = st->integer >> 8; |
| 277 | st->buf[1] = 0x40; /* REG12 default */ | 277 | st->buf[1] = 0x40; /* REG12 default */ |
| 278 | st->buf[2] = 0x00; | 278 | st->buf[2] = 0x00; |
| 279 | st->buf[3] = st->fract2 & 0xFF; | 279 | st->buf[3] = st->fract1 & 0xFF; |
| 280 | st->buf[4] = st->fract2 >> 7; | 280 | st->buf[4] = st->fract1 >> 8; |
| 281 | st->buf[5] = st->fract2 >> 15; | 281 | st->buf[5] = st->fract1 >> 16; |
| 282 | st->buf[6] = ADF4371_FRAC2WORD_L(st->fract2 & 0x7F) | | 282 | st->buf[6] = ADF4371_FRAC2WORD_L(st->fract2 & 0x7F) | |
| 283 | ADF4371_FRAC1WORD(st->fract1 >> 23); | 283 | ADF4371_FRAC1WORD(st->fract1 >> 24); |
| 284 | st->buf[7] = ADF4371_FRAC2WORD_H(st->fract2 >> 7); | 284 | st->buf[7] = ADF4371_FRAC2WORD_H(st->fract2 >> 7); |
| 285 | st->buf[8] = st->mod2 & 0xFF; | 285 | st->buf[8] = st->mod2 & 0xFF; |
| 286 | st->buf[9] = ADF4371_MOD2WORD(st->mod2 >> 8); | 286 | st->buf[9] = ADF4371_MOD2WORD(st->mod2 >> 8); |
| @@ -845,6 +845,25 @@ static const struct iio_chan_spec inv_mpu_channels[] = { · 844 unmodified lines | |||
| 845 | INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Z, INV_MPU6050_SCAN_ACCL_Z), | 845 | INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Z, INV_MPU6050_SCAN_ACCL_Z), |
| 846 | }; | 846 | }; |
| 847 | 847 | ||
| 848 | static const unsigned long inv_mpu_scan_masks[] = { | ||
| 849 | /* 3-axis accel */ | ||
| 850 | BIT(INV_MPU6050_SCAN_ACCL_X) | ||
| 851 | | BIT(INV_MPU6050_SCAN_ACCL_Y) | ||
| 852 | | BIT(INV_MPU6050_SCAN_ACCL_Z), | ||
| 853 | /* 3-axis gyro */ | ||
| 854 | BIT(INV_MPU6050_SCAN_GYRO_X) | ||
| 855 | | BIT(INV_MPU6050_SCAN_GYRO_Y) | ||
| 856 | | BIT(INV_MPU6050_SCAN_GYRO_Z), | ||
| 857 | /* 6-axis accel + gyro */ | ||
| 858 | BIT(INV_MPU6050_SCAN_ACCL_X) | ||
| 859 | | BIT(INV_MPU6050_SCAN_ACCL_Y) | ||
| 860 | | BIT(INV_MPU6050_SCAN_ACCL_Z) | ||
| 861 | | BIT(INV_MPU6050_SCAN_GYRO_X) | ||
| 862 | | BIT(INV_MPU6050_SCAN_GYRO_Y) | ||
| 863 | | BIT(INV_MPU6050_SCAN_GYRO_Z), | ||
| 864 | 0, | ||
| 865 | }; | ||
| 866 | |||
| 848 | static const struct iio_chan_spec inv_icm20602_channels[] = { | 867 | static const struct iio_chan_spec inv_icm20602_channels[] = { |
| 849 | IIO_CHAN_SOFT_TIMESTAMP(INV_ICM20602_SCAN_TIMESTAMP), | 868 | IIO_CHAN_SOFT_TIMESTAMP(INV_ICM20602_SCAN_TIMESTAMP), |
| 850 | { | 869 | { |
| @@ -871,6 +890,28 @@ static const struct iio_chan_spec inv_icm20602_channels[] = { · 20 unmodified lines | |||
| 871 | INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Z, INV_ICM20602_SCAN_ACCL_Z), | 890 | INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Z, INV_ICM20602_SCAN_ACCL_Z), |
| 872 | }; | 891 | }; |
| 873 | 892 | ||
| 893 | static const unsigned long inv_icm20602_scan_masks[] = { | ||
| 894 | /* 3-axis accel + temp (mandatory) */ | ||
| 895 | BIT(INV_ICM20602_SCAN_ACCL_X) | ||
| 896 | | BIT(INV_ICM20602_SCAN_ACCL_Y) | ||
| 897 | | BIT(INV_ICM20602_SCAN_ACCL_Z) | ||
| 898 | | BIT(INV_ICM20602_SCAN_TEMP), | ||
| 899 | /* 3-axis gyro + temp (mandatory) */ | ||
| 900 | BIT(INV_ICM20602_SCAN_GYRO_X) | ||
| 901 | | BIT(INV_ICM20602_SCAN_GYRO_Y) | ||
| 902 | | BIT(INV_ICM20602_SCAN_GYRO_Z) | ||
| 903 | | BIT(INV_ICM20602_SCAN_TEMP), | ||
| 904 | /* 6-axis accel + gyro + temp (mandatory) */ | ||
| 905 | BIT(INV_ICM20602_SCAN_ACCL_X) | ||
| 906 | | BIT(INV_ICM20602_SCAN_ACCL_Y) | ||
| 907 | | BIT(INV_ICM20602_SCAN_ACCL_Z) | ||
| 908 | | BIT(INV_ICM20602_SCAN_GYRO_X) | ||
| 909 | | BIT(INV_ICM20602_SCAN_GYRO_Y) | ||
| 910 | | BIT(INV_ICM20602_SCAN_GYRO_Z) | ||
| 911 | | BIT(INV_ICM20602_SCAN_TEMP), | ||
| 912 | 0, | ||
| 913 | }; | ||
| 914 | |||
| 874 | /* | 915 | /* |
| 875 | * The user can choose any frequency between INV_MPU6050_MIN_FIFO_RATE and | 916 | * The user can choose any frequency between INV_MPU6050_MIN_FIFO_RATE and |
| 876 | * INV_MPU6050_MAX_FIFO_RATE, but only these frequencies are matched by the | 917 | * INV_MPU6050_MAX_FIFO_RATE, but only these frequencies are matched by the |
| @@ -1130,9 +1171,11 @@ int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name, · 253 unmodified lines | |||
| 1130 | if (chip_type == INV_ICM20602) { | 1171 | if (chip_type == INV_ICM20602) { |
| 1131 | indio_dev->channels = inv_icm20602_channels; | 1172 | indio_dev->channels = inv_icm20602_channels; |
| 1132 | indio_dev->num_channels = ARRAY_SIZE(inv_icm20602_channels); | 1173 | indio_dev->num_channels = ARRAY_SIZE(inv_icm20602_channels); |
| 1174 | indio_dev->available_scan_masks = inv_icm20602_scan_masks; | ||
| 1133 | } else { | 1175 | } else { |
| 1134 | indio_dev->channels = inv_mpu_channels; | 1176 | indio_dev->channels = inv_mpu_channels; |
| 1135 | indio_dev->num_channels = ARRAY_SIZE(inv_mpu_channels); | 1177 | indio_dev->num_channels = ARRAY_SIZE(inv_mpu_channels); |
| 1178 | indio_dev->available_scan_masks = inv_mpu_scan_masks; | ||
| 1136 | } | 1179 | } |
| 1137 | 1180 | ||
| 1138 | indio_dev->info = &mpu_info; | 1181 | indio_dev->info = &mpu_info; |
| @@ -55,6 +55,7 @@ config INFINIBAND_ON_DEMAND_PAGING · 54 unmodified lines | |||
| 55 | bool "InfiniBand on-demand paging support" | 55 | bool "InfiniBand on-demand paging support" |
| 56 | depends on INFINIBAND_USER_MEM | 56 | depends on INFINIBAND_USER_MEM |
| 57 | select MMU_NOTIFIER | 57 | select MMU_NOTIFIER |
| 58 | select INTERVAL_TREE | ||
| 58 | default y | 59 | default y |
| 59 | ---help--- | 60 | ---help--- |
| 60 | On demand paging support for the InfiniBand subsystem. | 61 | On demand paging support for the InfiniBand subsystem. |
| @@ -302,7 +302,9 @@ static inline struct ib_qp *_ib_create_qp(struct ib_device *dev, · 301 unmodified lines | |||
| 302 | struct ib_udata *udata, | 302 | struct ib_udata *udata, |
| 303 | struct ib_uobject *uobj) | 303 | struct ib_uobject *uobj) |
| 304 | { | 304 | { |
| 305 | enum ib_qp_type qp_type = attr->qp_type; | ||
| 305 | struct ib_qp *qp; | 306 | struct ib_qp *qp; |
| 307 | bool is_xrc; | ||
| 306 | 308 | ||
| 307 | if (!dev->ops.create_qp) | 309 | if (!dev->ops.create_qp) |
| 308 | return ERR_PTR(-EOPNOTSUPP); | 310 | return ERR_PTR(-EOPNOTSUPP); |
| @@ -320,7 +322,8 @@ static inline struct ib_qp *_ib_create_qp(struct ib_device *dev, · 11 unmodified lines | |||
| 320 | * and more importantly they are created internaly by driver, | 322 | * and more importantly they are created internaly by driver, |
| 321 | * see mlx5 create_dev_resources() as an example. | 323 | * see mlx5 create_dev_resources() as an example. |
| 322 | */ | 324 | */ |
| 323 | if (attr->qp_type < IB_QPT_XRC_INI) { | 325 | is_xrc = qp_type == IB_QPT_XRC_INI || qp_type == IB_QPT_XRC_TGT; |
| 326 | if ((qp_type < IB_QPT_MAX && !is_xrc) || qp_type == IB_QPT_DRIVER) { | ||
| 324 | qp->res.type = RDMA_RESTRACK_QP; | 327 | qp->res.type = RDMA_RESTRACK_QP; |
| 325 | if (uobj) | 328 | if (uobj) |
| 326 | rdma_restrack_uadd(&qp->res); | 329 | rdma_restrack_uadd(&qp->res); |
| @@ -38,6 +38,9 @@ int rdma_counter_set_auto_mode(struct ib_device *dev, u8 port, · 37 unmodified lines | |||
| 38 | int ret; | 38 | int ret; |
| 39 | 39 | ||
| 40 | port_counter = &dev->port_data[port].port_counter; | 40 | port_counter = &dev->port_data[port].port_counter; |
| 41 | if (!port_counter->hstats) | ||
| 42 | return -EOPNOTSUPP; | ||
| 43 | |||
| 41 | mutex_lock(&port_counter->lock); | 44 | mutex_lock(&port_counter->lock); |
| 42 | if (on) { | 45 | if (on) { |
| 43 | ret = __counter_set_mode(&port_counter->mode, | 46 | ret = __counter_set_mode(&port_counter->mode, |
| @@ -393,6 +396,9 @@ u64 rdma_counter_get_hwstat_value(struct ib_device *dev, u8 port, u32 index) · 349 unmodified lines | |||
| 393 | u64 sum; | 396 | u64 sum; |
| 394 | 397 | ||
| 395 | port_counter = &dev->port_data[port].port_counter; | 398 | port_counter = &dev->port_data[port].port_counter; |
| 399 | if (!port_counter->hstats) | ||
| 400 | return 0; | ||
| 401 | |||
| 396 | sum = get_running_counters_hwstat_sum(dev, port, index); | 402 | sum = get_running_counters_hwstat_sum(dev, port, index); |
| 397 | sum += port_counter->hstats->value[index]; | 403 | sum += port_counter->hstats->value[index]; |
| 398 | 404 | ||
| @@ -506,6 +512,9 @@ int rdma_counter_bind_qpn_alloc(struct ib_device *dev, u8 port, · 107 unmodified lines | |||
| 506 | if (!rdma_is_port_valid(dev, port)) | 512 | if (!rdma_is_port_valid(dev, port)) |
| 507 | return -EINVAL; | 513 | return -EINVAL; |
| 508 | 514 | ||
| 515 | if (!dev->port_data[port].port_counter.hstats) | ||
| 516 | return -EOPNOTSUPP; | ||
| 517 | |||
| 509 | qp = rdma_counter_get_qp(dev, qp_num); | 518 | qp = rdma_counter_get_qp(dev, qp_num); |
| 510 | if (!qp) | 519 | if (!qp) |
| 511 | return -ENOENT; | 520 | return -ENOENT; |
| @@ -594,7 +603,7 @@ void rdma_counter_init(struct ib_device *dev) · 82 unmodified lines | |||
| 594 | struct rdma_port_counter *port_counter; | 603 | struct rdma_port_counter *port_counter; |
| 595 | u32 port; | 604 | u32 port; |
| 596 | 605 | ||
| 597 | if (!dev->ops.alloc_hw_stats || !dev->port_data) | 606 | if (!dev->port_data) |
| 598 | return; | 607 | return; |
| 599 | 608 | ||
| 600 | rdma_for_each_port(dev, port) { | 609 | rdma_for_each_port(dev, port) { |
| @@ -602,6 +611,9 @@ void rdma_counter_init(struct ib_device *dev) · 1 unmodified line | |||
| 602 | port_counter->mode.mode = RDMA_COUNTER_MODE_NONE; | 611 | port_counter->mode.mode = RDMA_COUNTER_MODE_NONE; |
| 603 | mutex_init(&port_counter->lock); | 612 | mutex_init(&port_counter->lock); |
| 604 | 613 | ||
| 614 | if (!dev->ops.alloc_hw_stats) | ||
| 615 | continue; | ||
| 616 | |||
| 605 | port_counter->hstats = dev->ops.alloc_hw_stats(dev, port); | 617 | port_counter->hstats = dev->ops.alloc_hw_stats(dev, port); |
| 606 | if (!port_counter->hstats) | 618 | if (!port_counter->hstats) |
| 607 | goto fail; | 619 | goto fail; |
| @@ -624,9 +636,6 @@ void rdma_counter_release(struct ib_device *dev) · 16 unmodified lines | |||
| 624 | struct rdma_port_counter *port_counter; | 636 | struct rdma_port_counter *port_counter; |
| 625 | u32 port; | 637 | u32 port; |
| 626 | 638 | ||
| 627 | if (!dev->ops.alloc_hw_stats) | ||
| 628 | return; | ||
| 629 | |||
| 630 | rdma_for_each_port(dev, port) { | 639 | rdma_for_each_port(dev, port) { |
| 631 | port_counter = &dev->port_data[port].port_counter; | 640 | port_counter = &dev->port_data[port].port_counter; |
| 632 | kfree(port_counter->hstats); | 641 | kfree(port_counter->hstats); |
| @@ -94,11 +94,17 @@ static DEFINE_XARRAY_FLAGS(devices, XA_FLAGS_ALLOC); · 93 unmodified lines | |||
| 94 | static DECLARE_RWSEM(devices_rwsem); | 94 | static DECLARE_RWSEM(devices_rwsem); |
| 95 | #define DEVICE_REGISTERED XA_MARK_1 | 95 | #define DEVICE_REGISTERED XA_MARK_1 |
| 96 | 96 | ||
| 97 | static LIST_HEAD(client_list); | 97 | static u32 highest_client_id; |
| 98 | #define CLIENT_REGISTERED XA_MARK_1 | 98 | #define CLIENT_REGISTERED XA_MARK_1 |
| 99 | static DEFINE_XARRAY_FLAGS(clients, XA_FLAGS_ALLOC); | 99 | static DEFINE_XARRAY_FLAGS(clients, XA_FLAGS_ALLOC); |
| 100 | static DECLARE_RWSEM(clients_rwsem); | 100 | static DECLARE_RWSEM(clients_rwsem); |
| 101 | 101 | ||
| 102 | static void ib_client_put(struct ib_client *client) | ||
| 103 | { | ||
| 104 | if (refcount_dec_and_test(&client->uses)) | ||
| 105 | complete(&client->uses_zero); | ||
| 106 | } | ||
| 107 | |||
| 102 | /* | 108 | /* |
| 103 | * If client_data is registered then the corresponding client must also still | 109 | * If client_data is registered then the corresponding client must also still |
| 104 | * be registered. | 110 | * be registered. |
| @@ -660,6 +666,14 @@ static int add_client_context(struct ib_device *device, · 555 unmodified lines | |||
| 660 | return 0; | 666 | return 0; |
| 661 | 667 | ||
| 662 | down_write(&device->client_data_rwsem); | 668 | down_write(&device->client_data_rwsem); |
| 669 | /* | ||
| 670 | * So long as the client is registered hold both the client and device | ||
| 671 | * unregistration locks. | ||
| 672 | */ | ||
| 673 | if (!refcount_inc_not_zero(&client->uses)) | ||
| 674 | goto out_unlock; | ||
| 675 | refcount_inc(&device->refcount); | ||
| 676 | |||
| 663 | /* | 677 | /* |
| 664 | * Another caller to add_client_context got here first and has already | 678 | * Another caller to add_client_context got here first and has already |
| 665 | * completely initialized context. | 679 | * completely initialized context. |
| @@ -683,6 +697,9 @@ static int add_client_context(struct ib_device *device, · 17 unmodified lines | |||
| 683 | return 0; | 697 | return 0; |
| 684 | 698 | ||
| 685 | out: | 699 | out: |
| 700 | ib_device_put(device); | ||
| 701 | ib_client_put(client); | ||
| 702 | out_unlock: | ||
| 686 | up_write(&device->client_data_rwsem); | 703 | up_write(&device->client_data_rwsem); |
| 687 | return ret; | 704 | return ret; |
| 688 | } | 705 | } |
| @@ -702,7 +719,7 @@ static void remove_client_context(struct ib_device *device, · 13 unmodified lines | |||
| 702 | client_data = xa_load(&device->client_data, client_id); | 719 | client_data = xa_load(&device->client_data, client_id); |
| 703 | xa_clear_mark(&device->client_data, client_id, CLIENT_DATA_REGISTERED); | 720 | xa_clear_mark(&device->client_data, client_id, CLIENT_DATA_REGISTERED); |
| 704 | client = xa_load(&clients, client_id); | 721 | client = xa_load(&clients, client_id); |
| 705 | downgrade_write(&device->client_data_rwsem); | 722 | up_write(&device->client_data_rwsem); |
| 706 | 723 | ||
| 707 | /* | 724 | /* |
| 708 | * Notice we cannot be holding any exclusive locks when calling the | 725 | * Notice we cannot be holding any exclusive locks when calling the |
| @@ -712,17 +729,13 @@ static void remove_client_context(struct ib_device *device, · 3 unmodified lines | |||
| 712 | * | 729 | * |
| 713 | * For this reason clients and drivers should not call the | 730 | * For this reason clients and drivers should not call the |
| 714 | * unregistration functions will holdling any locks. | 731 | * unregistration functions will holdling any locks. |
| 715 | * | ||
| 716 | * It tempting to drop the client_data_rwsem too, but this is required | ||
| 717 | * to ensure that unregister_client does not return until all clients | ||
| 718 | * are completely unregistered, which is required to avoid module | ||
| 719 | * unloading races. | ||
| 720 | */ | 732 | */ |
| 721 | if (client->remove) | 733 | if (client->remove) |
| 722 | client->remove(device, client_data); | 734 | client->remove(device, client_data); |
| 723 | 735 | ||
| 724 | xa_erase(&device->client_data, client_id); | 736 | xa_erase(&device->client_data, client_id); |
| 725 | up_read(&device->client_data_rwsem); | 737 | ib_device_put(device); |
| 738 | ib_client_put(client); | ||
| 726 | } | 739 | } |
| 727 | 740 | ||
| 728 | static int alloc_port_data(struct ib_device *device) | 741 | static int alloc_port_data(struct ib_device *device) |
| @@ -1224,7 +1237,7 @@ static int setup_device(struct ib_device *device) · 495 unmodified lines | |||
| 1224 | 1237 | ||
| 1225 | static void disable_device(struct ib_device *device) | 1238 | static void disable_device(struct ib_device *device) |
| 1226 | { | 1239 | { |
| 1227 | struct ib_client *client; | 1240 | u32 cid; |
| 1228 | 1241 | ||
| 1229 | WARN_ON(!refcount_read(&device->refcount)); | 1242 | WARN_ON(!refcount_read(&device->refcount)); |
| 1230 | 1243 | ||
| @@ -1232,10 +1245,19 @@ static void disable_device(struct ib_device *device) · 1 unmodified line | |||
| 1232 | xa_clear_mark(&devices, device->index, DEVICE_REGISTERED); | 1245 | xa_clear_mark(&devices, device->index, DEVICE_REGISTERED); |
| 1233 | up_write(&devices_rwsem); | 1246 | up_write(&devices_rwsem); |
| 1234 | 1247 | ||
| 1248 | /* | ||
| 1249 | * Remove clients in LIFO order, see assign_client_id. This could be | ||
| 1250 | * more efficient if xarray learns to reverse iterate. Since no new | ||
| 1251 | * clients can be added to this ib_device past this point we only need | ||
| 1252 | * the maximum possible client_id value here. | ||
| 1253 | */ | ||
| 1235 | down_read(&clients_rwsem); | 1254 | down_read(&clients_rwsem); |
| 1236 | list_for_each_entry_reverse(client, &client_list, list) | 1255 | cid = highest_client_id; |
| 1237 | remove_client_context(device, client->client_id); | ||
| 1238 | up_read(&clients_rwsem); | 1256 | up_read(&clients_rwsem); |
| 1257 | while (cid) { | ||
| 1258 | cid--; | ||
| 1259 | remove_client_context(device, cid); | ||
| 1260 | } | ||
| 1239 | 1261 | ||
| 1240 | /* Pairs with refcount_set in enable_device */ | 1262 | /* Pairs with refcount_set in enable_device */ |
| 1241 | ib_device_put(device); | 1263 | ib_device_put(device); |
| @@ -1662,30 +1684,31 @@ static int assign_client_id(struct ib_client *client) · 420 unmodified lines | |||
| 1662 | /* | 1684 | /* |
| 1663 | * The add/remove callbacks must be called in FIFO/LIFO order. To | 1685 | * The add/remove callbacks must be called in FIFO/LIFO order. To |
| 1664 | * achieve this we assign client_ids so they are sorted in | 1686 | * achieve this we assign client_ids so they are sorted in |
| 1665 | * registration order, and retain a linked list we can reverse iterate | ||
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