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Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: [MIPS] Fix scheduling latency issue on 24K, 34K and 74K cores [MIPS] Add macros to encode processor revisions. [MIPS] RM7000: Enable ICACHE_REFILLS_WORKAROUND_WAR. [MIPS] SMTC: Fix cut'n'paste bug in Kconfig.debug [MIPS] Change libgcc-style functions from lib-y to obj-y [MIPS] Fix timer/performance interrupt detection [MIPS] AP/SP: Avoid triggering the 34K E125 performance issue [MIPS] 64-bit TO_PHYS_MASK macro for RM9000 processors

Linus Torvalds committed 19 years ago

Commit dadde132 parents 23c1fb5 4b3e9759 files · +44 −19Browse files

Unified · Split

9 files
  1. arch/mips/Kconfig.debug +1 −1
  2. arch/mips/kernel/cpu-probe.c +13 −2
  3. arch/mips/kernel/traps.c +4 −4
  4. arch/mips/kernel/vpe.c +0 −4
  5. arch/mips/lib/Makefile +1 −1
  6. include/asm-mips/addrspace.h +1 −0
  7. include/asm-mips/cpu.h +11 −0
  8. include/asm-mips/mipsregs.h +2 −0
  9. include/asm-mips/war.h +11 −7
arch/mips/Kconfig.debug+1−1
@@ -37,7 +37,7 @@ config DEBUG_STACK_USAGE · 36 unmodified lines
3737
3838 This option will slow down process creation somewhat.
3939
40−config CONFIG_SMTC_IDLE_HOOK_DEBUG
40+config SMTC_IDLE_HOOK_DEBUG
4141 bool "Enable additional debug checks before going into CPU idle loop"
4242 depends on DEBUG_KERNEL && MIPS_MT_SMTC
4343 help
arch/mips/kernel/cpu-probe.c+13−2
@@ -137,13 +137,24 @@ static inline void check_wait(void) · 136 unmodified lines
137137 case CPU_4KEC:
138138 case CPU_4KSC:
139139 case CPU_5KC:
140− case CPU_24K:
141140 case CPU_25KF:
141+ case CPU_PR4450:
142+ cpu_wait = r4k_wait;
143+ break;
144+
145+ case CPU_24K:
142146 case CPU_34K:
147+ cpu_wait = r4k_wait;
148+ if (read_c0_config7() & MIPS_CONF7_WII)
149+ cpu_wait = r4k_wait_irqoff;
150+ break;
151+
143152 case CPU_74K:
144− case CPU_PR4450:
145153 cpu_wait = r4k_wait;
154+ if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
155+ cpu_wait = r4k_wait_irqoff;
146156 break;
157+
147158 case CPU_TX49XX:
148159 cpu_wait = r4k_wait_irqoff;
149160 break;
arch/mips/kernel/traps.c+4−4
@@ -1372,12 +1372,12 @@ void __init per_cpu_trap_init(void) · 1371 unmodified lines
13721372 */
13731373 if (cpu_has_mips_r2) {
13741374 cp0_compare_irq = (read_c0_intctl () >> 29) & 7;
1375− cp0_perfcount_irq = -1;
1376− } else {
1377− cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
13781375 cp0_perfcount_irq = (read_c0_intctl () >> 26) & 7;
1379− if (cp0_perfcount_irq != cp0_compare_irq)
1376+ if (cp0_perfcount_irq == cp0_compare_irq)
13801377 cp0_perfcount_irq = -1;
1378+ } else {
1379+ cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
1380+ cp0_perfcount_irq = -1;
13811381 }
13821382
13831383 #ifdef CONFIG_MIPS_MT_SMTC
arch/mips/kernel/vpe.c+0−4
@@ -1436,10 +1436,6 @@ static int __init vpe_module_init(void) · 1435 unmodified lines
14361436 write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & ~VPECONTROL_TE);
14371437
14381438 if (i != 0) {
1439− write_vpe_c0_status((read_c0_status() &
1440− ~(ST0_IM | ST0_IE | ST0_KSU))
1441− | ST0_CU0);
1442−
14431439 /*
14441440 * Set config to be the same as vpe0,
14451441 * particularly kseg0 coherency alg
arch/mips/lib/Makefile+1−1
@@ -9,4 +9,4 @@ obj-y += iomap.o · 8 unmodified lines
99 obj-$(CONFIG_PCI) += iomap-pci.o
1010
1111 # libgcc-style stuff needed in the kernel
12−lib-y += ashldi3.o ashrdi3.o lshrdi3.o ucmpdi2.o
12+obj-y += ashldi3.o ashrdi3.o lshrdi3.o ucmpdi2.o
include/asm-mips/addrspace.h+1−0
@@ -133,6 +133,7 @@ · 132 unmodified lines
133133 || defined (CONFIG_CPU_R4X00) \
134134 || defined (CONFIG_CPU_R5000) \
135135 || defined (CONFIG_CPU_RM7000) \
136+ || defined (CONFIG_CPU_RM9000) \
136137 || defined (CONFIG_CPU_NEVADA) \
137138 || defined (CONFIG_CPU_TX49XX) \
138139 || defined (CONFIG_CPU_MIPS64)
include/asm-mips/cpu.h+11−0
@@ -124,6 +124,17 @@ · 123 unmodified lines
124124 #define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */
125125 #define PRID_REV_VR4130 0x0080
126126
127+/*
128+ * Older processors used to encode processor version and revision in two
129+ * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores
130+ * have switched to use the 8-bits as 3:3:2 bitfield with the last field as
131+ * the patch number. *ARGH*
132+ */
133+#define PRID_REV_ENCODE_44(ver, rev) \
134+ ((ver) << 4 | (rev))
135+#define PRID_REV_ENCODE_332(ver, rev, patch) \
136+ ((ver) << 5 | (rev) << 2 | (patch))
137+
127138 /*
128139 * FPU implementation/revision register (CP1 control register 0).
129140 *
include/asm-mips/mipsregs.h+2−0
@@ -534,6 +534,8 @@ · 533 unmodified lines
534534 #define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
535535 #define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
536536
537+#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
538+
537539 /*
538540 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
539541 */
include/asm-mips/war.h+11−7
@@ -177,18 +177,22 @@ · 176 unmodified lines
177177 #endif
178178
179179 /*
180− * The RM9000 has a bug (though PMC-Sierra opposes it being called that)
181− * where invalid instructions in the same I-cache line worth of instructions
182− * being fetched may case spurious exceptions.
183− */
184−#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_MOMENCO_OCELOT_3) || \
185− defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_BASLER_EXCITE)
180+ * The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
181+ * opposes it being called that) where invalid instructions in the same
182+ * I-cache line worth of instructions being fetched may case spurious
183+ * exceptions.
184+ */
185+#if defined(CONFIG_BASLER_EXCITE) || defined(CONFIG_MOMENCO_JAGUAR_ATX) || \
186+ defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA) || \
187+ defined(CONFIG_MOMENCO_OCELOT) || defined(CONFIG_MOMENCO_OCELOT_3) || \
188+ defined(CONFIG_MOMENCO_OCELOT_C) || defined(CONFIG_PMC_YOSEMITE) || \
189+ defined(CONFIG_SGI_IP32) || defined(CONFIG_WR_PPMC)
186190 #define ICACHE_REFILLS_WORKAROUND_WAR 1
187191 #endif
188192
189193
190194 /*
191− * ON the R10000 upto version 2.6 (not sure about 2.7) there is a bug that
195+ * On the R10000 upto version 2.6 (not sure about 2.7) there is a bug that
192196 * may cause ll / sc and lld / scd sequences to execute non-atomically.
193197 */
194198 #ifdef CONFIG_SGI_IP27