History

tg3: Fix crc errors on jumbo frame receive

TG3_PHY_AUXCTL_SMDSP_ENABLE/DISABLE macros do a blind write to the phy auxiliary control register and overwrite the EXT_PKT_LEN (bit 14) resulting in intermittent crc errors on jumbo frames with some link partners. Change the code to do a read/modify/write.

Nithin Nayak Sujir committed 13 years ago

Commit daf3ec61 parent 9c13cb81 file · +35 −23Browse files

Unified · Split

drivers/net/ethernet/broadcom/tg3.c+35−23
@@ -1283,14 +1283,26 @@ static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set) · 1282 unmodified lines
12831283 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
12841284 }
12851285
1286−#define TG3_PHY_AUXCTL_SMDSP_ENABLE(tp) \
1287− tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
1288− MII_TG3_AUXCTL_ACTL_SMDSP_ENA | \
1289− MII_TG3_AUXCTL_ACTL_TX_6DB)
1286+static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable)
1287+{
1288+ u32 val;
1289+ int err;
1290+
1291+ err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
12901292
1291−#define TG3_PHY_AUXCTL_SMDSP_DISABLE(tp) \
1292− tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
1293− MII_TG3_AUXCTL_ACTL_TX_6DB);
1293+ if (err)
1294+ return err;
1295+ if (enable)
1296+
1297+ val |= MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1298+ else
1299+ val &= ~MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1300+
1301+ err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1302+ val | MII_TG3_AUXCTL_ACTL_TX_6DB);
1303+
1304+ return err;
1305+}
12941306
12951307 static int tg3_bmcr_reset(struct tg3 *tp)
12961308 {
@@ -2223,7 +2235,7 @@ static void tg3_phy_apply_otp(struct tg3 *tp) · 926 unmodified lines
22232235
22242236 otp = tp->phy_otp;
22252237
2226− if (TG3_PHY_AUXCTL_SMDSP_ENABLE(tp))
2238+ if (tg3_phy_toggle_auxctl_smdsp(tp, true))
22272239 return;
22282240
22292241 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
@@ -2248,7 +2260,7 @@ static void tg3_phy_apply_otp(struct tg3 *tp) · 18 unmodified lines
22482260 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
22492261 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
22502262
2251− TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2263+ tg3_phy_toggle_auxctl_smdsp(tp, false);
22522264 }
22532265
22542266 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
@@ -2284,9 +2296,9 @@ static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up) · 29 unmodified lines
22842296
22852297 if (!tp->setlpicnt) {
22862298 if (current_link_up == 1 &&
2287− !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2299+ !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
22882300 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
2289− TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2301+ tg3_phy_toggle_auxctl_smdsp(tp, false);
22902302 }
22912303
22922304 val = tr32(TG3_CPMU_EEE_MODE);
@@ -2302,11 +2314,11 @@ static void tg3_phy_eee_enable(struct tg3 *tp) · 9 unmodified lines
23022314 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
23032315 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
23042316 tg3_flag(tp, 57765_CLASS)) &&
2305− !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2317+ !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
23062318 val = MII_TG3_DSP_TAP26_ALNOKO |
23072319 MII_TG3_DSP_TAP26_RMRXSTO;
23082320 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
2309− TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2321+ tg3_phy_toggle_auxctl_smdsp(tp, false);
23102322 }
23112323
23122324 val = tr32(TG3_CPMU_EEE_MODE);
@@ -2450,7 +2462,7 @@ static int tg3_phy_reset_5703_4_5(struct tg3 *tp) · 137 unmodified lines
24502462 tg3_writephy(tp, MII_CTRL1000,
24512463 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
24522464
2453− err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
2465+ err = tg3_phy_toggle_auxctl_smdsp(tp, true);
24542466 if (err)
24552467 return err;
24562468
@@ -2471,7 +2483,7 @@ static int tg3_phy_reset_5703_4_5(struct tg3 *tp) · 14 unmodified lines
24712483 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
24722484 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
24732485
2474− TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2486+ tg3_phy_toggle_auxctl_smdsp(tp, false);
24752487
24762488 tg3_writephy(tp, MII_CTRL1000, phy9_orig);
24772489
@@ -2572,10 +2584,10 @@ static int tg3_phy_reset(struct tg3 *tp) · 94 unmodified lines
25722584
25732585 out:
25742586 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
2575− !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2587+ !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
25762588 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
25772589 tg3_phydsp_write(tp, 0x000a, 0x0323);
2578− TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2590+ tg3_phy_toggle_auxctl_smdsp(tp, false);
25792591 }
25802592
25812593 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
@@ -2584,14 +2596,14 @@ out: · 2 unmodified lines
25842596 }
25852597
25862598 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2587− if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2599+ if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
25882600 tg3_phydsp_write(tp, 0x000a, 0x310b);
25892601 tg3_phydsp_write(tp, 0x201f, 0x9506);
25902602 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2591− TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2603+ tg3_phy_toggle_auxctl_smdsp(tp, false);
25922604 }
25932605 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2594− if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2606+ if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
25952607 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
25962608 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
25972609 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
@@ -2600,7 +2612,7 @@ out: · 2 unmodified lines
26002612 } else
26012613 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
26022614
2603− TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2615+ tg3_phy_toggle_auxctl_smdsp(tp, false);
26042616 }
26052617 }
26062618
@@ -4009,7 +4021,7 @@ static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl) · 1402 unmodified lines
40094021 tw32(TG3_CPMU_EEE_MODE,
40104022 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
40114023
4012− err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
4024+ err = tg3_phy_toggle_auxctl_smdsp(tp, true);
40134025 if (!err) {
40144026 u32 err2;
40154027
@@ -4042,7 +4054,7 @@ static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl) · 26 unmodified lines
40424054 MII_TG3_DSP_CH34TP2_HIBW01);
40434055 }
40444056
4045− err2 = TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
4057+ err2 = tg3_phy_toggle_auxctl_smdsp(tp, false);
40464058 if (!err)
40474059 err = err2;
40484060 }

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