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drm/i915/gsc: ARL-H and ARL-U need a newer GSC FW.

All MTL and ARL SKUs share the same GSC FW, but the newer platforms are only supported in newer blobs. In particular, ARL-S is supported starting from 102.0.10.1878 (which is already the minimum required version for ARL in the code), while ARL-H and ARL-U are supported from 102.1.15.1926. Therefore, the driver needs to check which specific ARL subplatform its running on when verifying that the GSC FW is new enough for it.

Daniele Ceraolo Spurio committed 2 years ago

Commit db0fc581 parent 2d5404c5 files · +75 −30Browse files

Unified · Split

5 files
  1. drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c +32 −18
  2. drivers/gpu/drm/i915/i915_drv.h +6 −2
  3. drivers/gpu/drm/i915/intel_device_info.c +19 −5
  4. drivers/gpu/drm/i915/intel_device_info.h +3 −1
  5. include/drm/intel/i915_pciids.h +15 −4
drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c+32−18
@@ -80,6 +80,7 @@ int intel_gsc_fw_get_binary_info(struct intel_uc_fw *gsc_fw, const void *data, s · 79 unmodified lines
80 const struct intel_gsc_cpd_header_v2 *cpd_header = NULL;80 const struct intel_gsc_cpd_header_v2 *cpd_header = NULL;
81 const struct intel_gsc_cpd_entry *cpd_entry = NULL;81 const struct intel_gsc_cpd_entry *cpd_entry = NULL;
82 const struct intel_gsc_manifest_header *manifest;82 const struct intel_gsc_manifest_header *manifest;
83 struct intel_uc_fw_ver min_ver = { 0 };
83 size_t min_size = sizeof(*layout);84 size_t min_size = sizeof(*layout);
84 int i;85 int i;
85 86
@@ -212,33 +213,46 @@ int intel_gsc_fw_get_binary_info(struct intel_uc_fw *gsc_fw, const void *data, s · 126 unmodified lines
212 }213 }
213 }214 }
214 215
215 if (IS_ARROWLAKE(gt->i915)) {216 /*
217 * ARL SKUs require newer firmwares, but the blob is actually common
218 * across all MTL and ARL SKUs, so we need to do an explicit version check
219 * here rather than using a separate table entry. If a too old version
220 * is found, then just don't use GSC rather than aborting the driver load.
221 * Note that the major number in the GSC FW version is used to indicate
222 * the platform, so we expect it to always be 102 for MTL/ARL binaries.
223 */
224 if (IS_ARROWLAKE_S(gt->i915))
225 min_ver = (struct intel_uc_fw_ver){ 102, 0, 10, 1878 };
226 else if (IS_ARROWLAKE_H(gt->i915) || IS_ARROWLAKE_U(gt->i915))
227 min_ver = (struct intel_uc_fw_ver){ 102, 1, 15, 1926 };
228
229 if (IS_METEORLAKE(gt->i915) && gsc->release.major != 102) {
230 gt_info(gt, "Invalid GSC firmware for MTL/ARL, got %d.%d.%d.%d but need 102.x.x.x",
231 gsc->release.major, gsc->release.minor,
232 gsc->release.patch, gsc->release.build);
233 return -EINVAL;
234 }
235
236 if (min_ver.major) {
216 bool too_old = false;237 bool too_old = false;
217 238
218 /*239 if (gsc->release.minor < min_ver.minor) {
219 * ARL requires a newer firmware than MTL did (102.0.10.1878) but the
220 * firmware is actually common. So, need to do an explicit version check
221 * here rather than using a separate table entry. And if the older
222 * MTL-only version is found, then just don't use GSC rather than aborting
223 * the driver load.
224 */
225 if (gsc->release.major < 102) {
226 too_old = true;240 too_old = true;
227 } else if (gsc->release.major == 102) {241 } else if (gsc->release.minor == min_ver.minor) {
228 if (gsc->release.minor == 0) {242 if (gsc->release.patch < min_ver.patch) {
229 if (gsc->release.patch < 10) {243 too_old = true;
244 } else if (gsc->release.patch == min_ver.patch) {
245 if (gsc->release.build < min_ver.build)
230 too_old = true;246 too_old = true;
231 } else if (gsc->release.patch == 10) {
232 if (gsc->release.build < 1878)
233 too_old = true;
234 }
235 }247 }
236 }248 }
237 249
238 if (too_old) {250 if (too_old) {
239 gt_info(gt, "GSC firmware too old for ARL, got %d.%d.%d.%d but need at least 102.0.10.1878",251 gt_info(gt, "GSC firmware too old for ARL, got %d.%d.%d.%d but need at least %d.%d.%d.%d",
240 gsc->release.major, gsc->release.minor,252 gsc->release.major, gsc->release.minor,
241 gsc->release.patch, gsc->release.build);253 gsc->release.patch, gsc->release.build,
254 min_ver.major, min_ver.minor,
255 min_ver.patch, min_ver.build);
242 return -EINVAL;256 return -EINVAL;
243 }257 }
244 }258 }
drivers/gpu/drm/i915/i915_drv.h+6−2
@@ -540,8 +540,12 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, · 539 unmodified lines
540#define IS_LUNARLAKE(i915) (0 && i915)540#define IS_LUNARLAKE(i915) (0 && i915)
541#define IS_BATTLEMAGE(i915) (0 && i915)541#define IS_BATTLEMAGE(i915) (0 && i915)
542 542
543#define IS_ARROWLAKE(i915) \543#define IS_ARROWLAKE_H(i915) \
544 IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_ARL)544 IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_ARL_H)
545#define IS_ARROWLAKE_U(i915) \
546 IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_ARL_U)
547#define IS_ARROWLAKE_S(i915) \
548 IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_ARL_S)
545#define IS_DG2_G10(i915) \549#define IS_DG2_G10(i915) \
546 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10)550 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10)
547#define IS_DG2_G11(i915) \551#define IS_DG2_G11(i915) \
drivers/gpu/drm/i915/intel_device_info.c+19−5
@@ -200,8 +200,16 @@ static const u16 subplatform_g12_ids[] = { · 199 unmodified lines
200 INTEL_DG2_G12_IDS(ID),200 INTEL_DG2_G12_IDS(ID),
201};201};
202 202
203static const u16 subplatform_arl_ids[] = {203static const u16 subplatform_arl_h_ids[] = {
204 INTEL_ARL_IDS(ID),204 INTEL_ARL_H_IDS(ID),
205};
206
207static const u16 subplatform_arl_u_ids[] = {
208 INTEL_ARL_U_IDS(ID),
209};
210
211static const u16 subplatform_arl_s_ids[] = {
212 INTEL_ARL_S_IDS(ID),
205};213};
206 214
207static bool find_devid(u16 id, const u16 *p, unsigned int num)215static bool find_devid(u16 id, const u16 *p, unsigned int num)
@@ -261,9 +269,15 @@ static void intel_device_info_subplatform_init(struct drm_i915_private *i915) · 53 unmodified lines
261 } else if (find_devid(devid, subplatform_g12_ids,269 } else if (find_devid(devid, subplatform_g12_ids,
262 ARRAY_SIZE(subplatform_g12_ids))) {270 ARRAY_SIZE(subplatform_g12_ids))) {
263 mask = BIT(INTEL_SUBPLATFORM_G12);271 mask = BIT(INTEL_SUBPLATFORM_G12);
264 } else if (find_devid(devid, subplatform_arl_ids,272 } else if (find_devid(devid, subplatform_arl_h_ids,
265 ARRAY_SIZE(subplatform_arl_ids))) {273 ARRAY_SIZE(subplatform_arl_h_ids))) {
266 mask = BIT(INTEL_SUBPLATFORM_ARL);274 mask = BIT(INTEL_SUBPLATFORM_ARL_H);
275 } else if (find_devid(devid, subplatform_arl_u_ids,
276 ARRAY_SIZE(subplatform_arl_u_ids))) {
277 mask = BIT(INTEL_SUBPLATFORM_ARL_U);
278 } else if (find_devid(devid, subplatform_arl_s_ids,
279 ARRAY_SIZE(subplatform_arl_s_ids))) {
280 mask = BIT(INTEL_SUBPLATFORM_ARL_S);
267 }281 }
268 282
269 GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK);283 GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK);
drivers/gpu/drm/i915/intel_device_info.h+3−1
@@ -128,7 +128,9 @@ enum intel_platform { · 127 unmodified lines
128#define INTEL_SUBPLATFORM_RPLU 2128#define INTEL_SUBPLATFORM_RPLU 2
129 129
130/* MTL */130/* MTL */
131#define INTEL_SUBPLATFORM_ARL 0131#define INTEL_SUBPLATFORM_ARL_H 0
132#define INTEL_SUBPLATFORM_ARL_U 1
133#define INTEL_SUBPLATFORM_ARL_S 2
132 134
133enum intel_ppgtt_type {135enum intel_ppgtt_type {
134 INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,136 INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
include/drm/intel/i915_pciids.h+15−4
@@ -771,13 +771,24 @@ · 770 unmodified lines
771 INTEL_ATS_M150_IDS(MACRO__, ## __VA_ARGS__), \771 INTEL_ATS_M150_IDS(MACRO__, ## __VA_ARGS__), \
772 INTEL_ATS_M75_IDS(MACRO__, ## __VA_ARGS__)772 INTEL_ATS_M75_IDS(MACRO__, ## __VA_ARGS__)
773 773
774/* MTL */774/* ARL */
775#define INTEL_ARL_IDS(MACRO__, ...) \775#define INTEL_ARL_H_IDS(MACRO__, ...) \
776 MACRO__(0x7D41, ## __VA_ARGS__), \
777 MACRO__(0x7D51, ## __VA_ARGS__), \776 MACRO__(0x7D51, ## __VA_ARGS__), \
778 MACRO__(0x7D67, ## __VA_ARGS__), \
779 MACRO__(0x7DD1, ## __VA_ARGS__)777 MACRO__(0x7DD1, ## __VA_ARGS__)
780 778
779#define INTEL_ARL_U_IDS(MACRO__, ...) \
780 MACRO__(0x7D41, ## __VA_ARGS__) \
781
782#define INTEL_ARL_S_IDS(MACRO__, ...) \
783 MACRO__(0x7D67, ## __VA_ARGS__), \
784 MACRO__(0xB640, ## __VA_ARGS__)
785
786#define INTEL_ARL_IDS(MACRO__, ...) \
787 INTEL_ARL_H_IDS(MACRO__, ## __VA_ARGS__), \
788 INTEL_ARL_U_IDS(MACRO__, ## __VA_ARGS__), \
789 INTEL_ARL_S_IDS(MACRO__, ## __VA_ARGS__)
790
791/* MTL */
781#define INTEL_MTL_IDS(MACRO__, ...) \792#define INTEL_MTL_IDS(MACRO__, ...) \
782 INTEL_ARL_IDS(MACRO__, ## __VA_ARGS__), \793 INTEL_ARL_IDS(MACRO__, ## __VA_ARGS__), \
783 MACRO__(0x7D40, ## __VA_ARGS__), \794 MACRO__(0x7D40, ## __VA_ARGS__), \