It is easy to miss already defined region types. Let's re-arrange the definitions a bit and add more comments to make it hopefully a bit clearer. No functional change.
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| @@ -295,15 +295,38 @@ struct vfio_region_info_cap_type { · 294 unmodified lines | ||
| 295 | 295 | __u32 subtype; /* type specific */ |
| 296 | 296 | }; |
| 297 | 297 | |
| 298 | +/* | |
| 299 | + * List of region types, global per bus driver. | |
| 300 | + * If you introduce a new type, please add it here. | |
| 301 | + */ | |
| 302 | + | |
| 303 | +/* PCI region type containing a PCI vendor part */ | |
| 298 | 304 | #define VFIO_REGION_TYPE_PCI_VENDOR_TYPE (1 << 31) |
| 299 | 305 | #define VFIO_REGION_TYPE_PCI_VENDOR_MASK (0xffff) |
| 306 | +#define VFIO_REGION_TYPE_GFX (1) | |
| 307 | +#define VFIO_REGION_TYPE_CCW (2) | |
| 308 | + | |
| 309 | +/* sub-types for VFIO_REGION_TYPE_PCI_* */ | |
| 300 | 310 | |
| 301 | −/* 8086 Vendor sub-types */ | |
| 311 | +/* 8086 vendor PCI sub-types */ | |
| 302 | 312 | #define VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION (1) |
| 303 | 313 | #define VFIO_REGION_SUBTYPE_INTEL_IGD_HOST_CFG (2) |
| 304 | 314 | #define VFIO_REGION_SUBTYPE_INTEL_IGD_LPC_CFG (3) |
| 305 | 315 | |
| 306 | −#define VFIO_REGION_TYPE_GFX (1) | |
| 316 | +/* 10de vendor PCI sub-types */ | |
| 317 | +/* | |
| 318 | + * NVIDIA GPU NVlink2 RAM is coherent RAM mapped onto the host address space. | |
| 319 | + */ | |
| 320 | +#define VFIO_REGION_SUBTYPE_NVIDIA_NVLINK2_RAM (1) | |
| 321 | + | |
| 322 | +/* 1014 vendor PCI sub-types */ | |
| 323 | +/* | |
| 324 | + * IBM NPU NVlink2 ATSD (Address Translation Shootdown) register of NPU | |
| 325 | + * to do TLB invalidation on a GPU. | |
| 326 | + */ | |
| 327 | +#define VFIO_REGION_SUBTYPE_IBM_NVLINK2_ATSD (1) | |
| 328 | + | |
| 329 | +/* sub-types for VFIO_REGION_TYPE_GFX */ | |
| 307 | 330 | #define VFIO_REGION_SUBTYPE_GFX_EDID (1) |
| 308 | 331 | |
| 309 | 332 | /** |
| @@ -353,25 +376,9 @@ struct vfio_region_gfx_edid { · 43 unmodified lines | ||
| 353 | 376 | #define VFIO_DEVICE_GFX_LINK_STATE_DOWN 2 |
| 354 | 377 | }; |
| 355 | 378 | |
| 356 | −#define VFIO_REGION_TYPE_CCW (2) | |
| 357 | −/* ccw sub-types */ | |
| 379 | +/* sub-types for VFIO_REGION_TYPE_CCW */ | |
| 358 | 380 | #define VFIO_REGION_SUBTYPE_CCW_ASYNC_CMD (1) |
| 359 | 381 | |
| 360 | −/* | |
| 361 | − * 10de vendor sub-type | |
| 362 | − * | |
| 363 | − * NVIDIA GPU NVlink2 RAM is coherent RAM mapped onto the host address space. | |
| 364 | − */ | |
| 365 | −#define VFIO_REGION_SUBTYPE_NVIDIA_NVLINK2_RAM (1) | |
| 366 | − | |
| 367 | −/* | |
| 368 | − * 1014 vendor sub-type | |
| 369 | − * | |
| 370 | − * IBM NPU NVlink2 ATSD (Address Translation Shootdown) register of NPU | |
| 371 | − * to do TLB invalidation on a GPU. | |
| 372 | − */ | |
| 373 | −#define VFIO_REGION_SUBTYPE_IBM_NVLINK2_ATSD (1) | |
| 374 | − | |
| 375 | 382 | /* |
| 376 | 383 | * The MSIX mappable capability informs that MSIX data of a BAR can be mmapped |
| 377 | 384 | * which allows direct access to non-MSIX registers which happened to be within |