History

Merge drm/drm-next into drm-intel-gt-next

Matt needed some buddy allocator changes for landing DG2 small BAR support patches.

Tvrtko Ursulin committed 4 years ago

Commit db927682 parents b8986c8 54f43c11576 files · +272369 −25486Browse files

Unified · Split

470 files
  1. .mailmap +3 −0
  2. Documentation/ABI/testing/sysfs-driver-aspeed-uart-routing +3 −3
  3. Documentation/arm64/silicon-errata.rst +2 −0
  4. Documentation/dev-tools/kselftest.rst +8 −0
  5. Documentation/dev-tools/kunit/usage.rst +1 −1
  6. Documentation/devicetree/bindings/arm/omap/omap.txt +3 −0
  7. Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml +17 −0
  8. Documentation/devicetree/bindings/display/bridge/ingenic,jz4780-hdmi.yaml +82 −0
  9. Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml +1 −1
  10. Documentation/devicetree/bindings/display/lvds.yaml +4 −31
  11. Documentation/devicetree/bindings/display/panel/advantech,idk-1110wr.yaml +17 −2
  12. Documentation/devicetree/bindings/display/panel/innolux,ee101ia-01d.yaml +21 −2
  13. Documentation/devicetree/bindings/display/panel/mitsubishi,aa104xd12.yaml +17 −2
  14. Documentation/devicetree/bindings/display/panel/mitsubishi,aa121td01.yaml +17 −2
  15. Documentation/devicetree/bindings/display/panel/panel-lvds.yaml +57 −0
  16. Documentation/devicetree/bindings/display/panel/panel-simple.yaml +2 −0
  17. Documentation/devicetree/bindings/display/panel/sgd,gktw70sdae4se.yaml +17 −2
  18. Documentation/devicetree/bindings/display/solomon,ssd1307fb.yaml +1 −0
  19. Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +15 −0
  20. Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +15 −6
  21. Documentation/devicetree/bindings/net/qcom,ipa.yaml +6 −0
  22. Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml +3 −2
  23. Documentation/driver-api/device-io.rst +9 −0
  24. Documentation/driver-api/dma-buf.rst +0 −9
  25. Documentation/filesystems/netfs_library.rst +16 −0
  26. Documentation/gpu/todo.rst +10 −34
  27. Documentation/userspace-api/ioctl/ioctl-number.rst +3 −0
  28. MAINTAINERS +89 −20
  29. Makefile +2 −2
  30. arch/arm/boot/dts/Makefile +1 −0
  31. arch/arm/boot/dts/am335x-wega.dtsi +1 −1
  32. arch/arm/boot/dts/dra7.dtsi +10 −10
  33. arch/arm/boot/dts/imx23-evk.dts +0 −1
  34. arch/arm/boot/dts/imx6qdl-udoo.dtsi +4 −1
  35. arch/arm/boot/dts/imx7ulp.dtsi +1 −1
  36. arch/arm/boot/dts/meson.dtsi +4 −4
  37. arch/arm/boot/dts/meson8.dtsi +12 −12
  38. arch/arm/boot/dts/meson8b.dtsi +12 −12
  39. arch/arm/boot/dts/omap3-beagle-ab4.dts +47 −0
  40. arch/arm/boot/dts/omap3-beagle.dts +0 −33
  41. arch/arm/boot/dts/spear320-hmi.dts +0 −1
  42. arch/arm/boot/dts/ste-ux500-samsung-skomer.dts +0 −4
  43. arch/arm/crypto/blake2s-shash.c +2 −2
  44. arch/arm/mach-omap2/display.c +1 −1
  45. arch/arm/mach-omap2/omap_hwmod.c +3 −1
  46. arch/arm/mach-socfpga/Kconfig +2 −0
  47. arch/arm64/Kconfig +17 −0
  48. arch/arm64/Kconfig.platforms +0 −3
  49. arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi +6 −0
  50. arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts +0 −8
  51. arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi +2 −2
  52. arch/arm64/boot/dts/amlogic/meson-gx.dtsi +6 −0
  53. arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m5.dts +1 −1
  54. arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi +1 −1
  55. arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts +0 −8
  56. arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts +4 −0
  57. arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +2 −2
  58. arch/arm64/boot/dts/freescale/imx8mq.dtsi +5 −5
  59. arch/arm64/boot/dts/freescale/mba8mx.dtsi +1 −1
  60. arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +12 −2
  61. arch/arm64/boot/dts/ti/k3-j721s2.dtsi +0 −22
  62. arch/arm64/kernel/cpu_errata.c +8 −0
  63. arch/arm64/kvm/arm.c +33 −18
  64. arch/arm64/kvm/handle_exit.c +8 −0
  65. arch/arm64/kvm/hyp/include/hyp/switch.h +21 −2
  66. arch/arm64/tools/cpucaps +3 −2
  67. arch/mips/boot/dts/ingenic/ci20.dts +2 −13
  68. arch/mips/cavium-octeon/octeon-memcpy.S +1 −1
  69. arch/mips/kvm/mips.c +46 −4
  70. arch/mips/kvm/vz.c +9 −3
  71. arch/riscv/Makefile +6 −0
  72. arch/riscv/kernel/cpu-hotplug.c +2 −0
  73. arch/riscv/kernel/head.S +5 −6
  74. arch/riscv/kernel/stacktrace.c +5 −4
  75. arch/riscv/kvm/vcpu.c +31 −17
  76. arch/riscv/kvm/vcpu_sbi_base.c +2 −1
  77. arch/riscv/mm/extable.c +3 −3
  78. arch/riscv/mm/init.c +2 −0
  79. arch/s390/kvm/kvm-s390.c +2 −0
  80. arch/s390/lib/test_modules.c +0 −3
  81. arch/s390/lib/test_modules.h +3 −0
  82. arch/x86/crypto/blake2s-shash.c +2 −2
  83. arch/x86/events/intel/core.c +13 −0
  84. arch/x86/events/intel/pt.c +3 −2
  85. arch/x86/include/asm/bug.h +11 −9
  86. arch/x86/include/asm/kvm-x86-ops.h +1 −1
  87. arch/x86/include/asm/kvm_host.h +2 −1
  88. arch/x86/include/asm/xen/cpuid.h +7 −0
  89. arch/x86/include/asm/xen/hypervisor.h +0 −14
  90. arch/x86/kernel/cpu/sgx/encl.c +2 −0
  91. arch/x86/kernel/early-quirks.c +1 −0
  92. arch/x86/kernel/resource.c +1 −22
  93. arch/x86/kvm/cpuid.c +7 −6
  94. arch/x86/kvm/lapic.c +2 −8
  95. arch/x86/kvm/svm/svm.c +18 −3
  96. arch/x86/kvm/vmx/vmx.c +18 −3
  97. arch/x86/kvm/x86.c +6 −4
  98. arch/x86/kvm/x86.h +0 −45
  99. arch/x86/xen/enlighten_hvm.c +11 −11
  100. arch/x86/xen/enlighten_pv.c +0 −4
  101. arch/x86/xen/smp_pv.c +6 −20
  102. arch/x86/xen/vga.c +8 −8
  103. block/bio-integrity.c +1 −1
  104. block/fops.c +19 −14
  105. crypto/algapi.c +1 −0
  106. crypto/api.c +0 −1
  107. crypto/blake2s_generic.c +2 −2
  108. drivers/accessibility/speakup/speakup_dectlk.c +1 −0
  109. drivers/acpi/Kconfig +1 −0
  110. drivers/acpi/arm64/iort.c +11 −3
  111. drivers/acpi/ec.c +10 −0
  112. drivers/acpi/sleep.c +5 −10
  113. drivers/acpi/x86/s2idle.c +4 −8
  114. drivers/ata/libata-core.c +17 −8
  115. drivers/ata/sata_fsl.c +7 −9
  116. drivers/base/power/wakeup.c +34 −7
  117. drivers/block/loop.c +29 −36
  118. drivers/block/loop.h +0 −1
  119. drivers/bus/mhi/pci_generic.c +2 −0
  120. drivers/char/random.c +22 −17
  121. drivers/clocksource/timer-ti-dm-systimer.c +1 −1
  122. drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c +2 −1
  123. drivers/dma-buf/dma-buf.c +11 −11
  124. drivers/dma-buf/dma-fence-array.c +14 −0
  125. drivers/dma-buf/dma-fence-chain.c +11 −4
  126. drivers/dma-buf/dma-heap.c +2 −0
  127. drivers/dma-buf/dma-resv.c +20 −14
  128. drivers/dma-buf/heaps/cma_heap.c +5 −5
  129. drivers/dma-buf/heaps/system_heap.c +5 −5
  130. drivers/edac/altera_edac.c +1 −1
  131. drivers/edac/xgene_edac.c +1 −1
  132. drivers/gpio/gpio-aggregator.c +14 −4
  133. drivers/gpio/gpio-sifive.c +1 −1
  134. drivers/gpio/gpio-sim.c +15 −4
  135. drivers/gpio/gpiolib-cdev.c +3 −3
  136. drivers/gpio/gpiolib-sysfs.c +2 −5
  137. drivers/gpio/gpiolib.h +12 −0
  138. drivers/gpu/drm/Kconfig +3 −0
  139. drivers/gpu/drm/Makefile +1 −0
  140. drivers/gpu/drm/amd/amdgpu/aldebaran.c +1 −1
  141. drivers/gpu/drm/amd/amdgpu/amdgpu.h +39 −17
  142. drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c +32 −5
  143. drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +6 −1
  144. drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c +0 −3
  145. drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c +0 −3
  146. drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c +0 −24
  147. drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c +0 −25
  148. drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c +0 −96
  149. drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c +0 −24
  150. drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c +2 −26
  151. drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h +0 −10
  152. drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +64 −12
  153. drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c +2 −0
  154. drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h +12 −10
  155. drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c +38 −0
  156. drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +13 −6
  157. drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c +1 −1
  158. drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +128 −4
  159. drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h +1 −1
  160. drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +27 −17
  161. drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +262 −143
  162. drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +544 −7
  163. drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +20 −15
  164. drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +87 −34
  165. drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +5 −38
  166. drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c +31 −22
  167. drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c +12 −24
  168. drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h +7 −8
  169. drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +1 −1
  170. drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +11 −59
  171. drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h +5 −19
  172. drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +63 −64
  173. drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h +6 −7
  174. drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c +13 −45
  175. drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c +2 −38
  176. drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h +5 −8
  177. drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c +6 −6
  178. drivers/gpu/drm/amd/amdgpu/amdgpu_job.c +4 −1
  179. drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +33 −93
  180. drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c +1 −40
  181. drivers/gpu/drm/amd/amdgpu/amdgpu_mca.h +3 −14
  182. drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.c +2 −38
  183. drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h +3 −10
  184. drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c +7 −37
  185. drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h +4 −7
  186. drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +7 −3
  187. drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c +5 −57
  188. drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +105 −19
  189. drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +9 −0
  190. drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +285 −240
  191. drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h +43 −34
  192. drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +20 −15
  193. drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c +56 −0
  194. drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h +40 −0
  195. drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +3 −2
  196. drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +3 −3
  197. drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h +14 −2
  198. drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c +7 −43
  199. drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h +5 −9
  200. drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c +2 −3
  201. drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h +2 −3
  202. drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +246 −165
  203. drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +9 −12
  204. drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h +1 −0
  205. drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c +47 −59
  206. drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h +14 −9
  207. drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +2 −0
  208. drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +149 −2
  209. drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h +24 −2
  210. drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +9 −3
  211. drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +1 −1
  212. drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c +22 −38
  213. drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c +75 −44
  214. drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h +4 −3
  215. drivers/gpu/drm/amd/amdgpu/athub_v1_0.c +7 −6
  216. drivers/gpu/drm/amd/amdgpu/athub_v2_0.c +1 −0
  217. drivers/gpu/drm/amd/amdgpu/athub_v2_1.c +1 −0
  218. drivers/gpu/drm/amd/amdgpu/atom.c +3 −1
  219. drivers/gpu/drm/amd/amdgpu/cik.c +1 −1
  220. drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +3 −1
  221. drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +3 −1
  222. drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +2 −1
  223. drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +3 −1
  224. drivers/gpu/drm/amd/amdgpu/df_v3_6.c +3 −3
  225. drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +177 −157
  226. drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +72 −162
  227. drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c +14 −10
  228. drivers/gpu/drm/amd/amdgpu/gfx_v9_4.h +1 −1
  229. drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c +14 −11
  230. drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.h +1 −1
  231. drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c +6 −1
  232. drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +47 −13
  233. drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +6 −6
  234. drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +6 −7
  235. drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +6 −7
  236. drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +74 −31
  237. drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c +13 −3
  238. drivers/gpu/drm/amd/amdgpu/hdp_v4_0.h +1 −1
  239. drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c +7 −2
  240. drivers/gpu/drm/amd/amdgpu/mca_v3_0.c +67 −35
  241. drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c +7 −3
  242. drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h +1 −1
  243. drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c +7 −3
  244. drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.h +1 −1
  245. drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c +1 −0
  246. drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c +7 −3
  247. drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h +1 −1
  248. drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c +12 −7
  249. drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c +12 −7
  250. drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c +9 −4
  251. drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c +31 −13
  252. drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c +16 −4
  253. drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h +1 −1
  254. drivers/gpu/drm/amd/amdgpu/nv.c +35 −67
  255. drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h +1 −0
  256. drivers/gpu/drm/amd/amdgpu/psp_v11_0.c +2 −2
  257. drivers/gpu/drm/amd/amdgpu/psp_v13_0.c +7 −0
  258. drivers/gpu/drm/amd/amdgpu/psp_v3_1.c +1 −0
  259. drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +59 −18
  260. drivers/gpu/drm/amd/amdgpu/sdma_v4_4.c +21 −4
  261. drivers/gpu/drm/amd/amdgpu/sdma_v4_4.h +1 −1
  262. drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c +12 −7
  263. drivers/gpu/drm/amd/amdgpu/si.c +1 −1
  264. drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c +54 −27
  265. drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.h +3 −3
  266. drivers/gpu/drm/amd/amdgpu/soc15.c +14 −50
  267. drivers/gpu/drm/amd/amdgpu/soc15_common.h +4 −4
  268. drivers/gpu/drm/amd/amdgpu/ta_ras_if.h +2 −1
  269. drivers/gpu/drm/amd/amdgpu/umc_v6_1.c +11 −19
  270. drivers/gpu/drm/amd/amdgpu/umc_v6_1.h +1 −1
  271. drivers/gpu/drm/amd/amdgpu/umc_v6_7.c +142 −83
  272. drivers/gpu/drm/amd/amdgpu/umc_v6_7.h +24 −1
  273. drivers/gpu/drm/amd/amdgpu/umc_v8_7.c +149 −24
  274. drivers/gpu/drm/amd/amdgpu/umc_v8_7.h +1 −1
  275. drivers/gpu/drm/amd/amdgpu/vi.c +1 −1
  276. drivers/gpu/drm/amd/amdkfd/Makefile +0 −2
  277. drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c +1 −1
  278. drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +1182 −428
  279. drivers/gpu/drm/amd/amdkfd/kfd_crat.c +4 −2
  280. drivers/gpu/drm/amd/amdkfd/kfd_crat.h +3 −2
  281. drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c +0 −845
  282. drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h +0 −230
  283. drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.c +0 −158
  284. drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.h +0 −293
  285. drivers/gpu/drm/amd/amdkfd/kfd_debugfs.c +3 −2
  286. drivers/gpu/drm/amd/amdkfd/kfd_device.c +34 −33
  287. drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +221 −48
  288. drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h +55 −7
  289. drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c +2 −1
  290. drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v10.c +2 −10
  291. drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c +2 −1
  292. drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_vi.c +2 −1
  293. drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c +2 −1
  294. drivers/gpu/drm/amd/amdkfd/kfd_events.c +281 −35
  295. drivers/gpu/drm/amd/amdkfd/kfd_events.h +2 −1
  296. drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c +3 −2
  297. drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c +6 −5
  298. drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c +2 −1
  299. drivers/gpu/drm/amd/amdkfd/kfd_iommu.c +2 −13
  300. drivers/gpu/drm/amd/amdkfd/kfd_iommu.h +2 −1
  301. drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c +2 −1
  302. drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.h +2 −1
  303. drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +11 −13
  304. drivers/gpu/drm/amd/amdkfd/kfd_module.c +2 −1
  305. drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c +66 −1
  306. drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h +43 −1
  307. drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c +74 −52
  308. drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c +86 −69
  309. drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c +100 −75
  310. drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c +92 −59
  311. drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c +5 −6
  312. drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c +16 −36
  313. drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_vi.c +5 −24
  314. drivers/gpu/drm/amd/amdkfd/kfd_pasid.c +2 −1
  315. drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h +2 −1
  316. drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h +2 −1
  317. drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h +2 −1
  318. drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_diq.h +2 −1
  319. drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h +4 −3
  320. drivers/gpu/drm/amd/amdkfd/kfd_pm4_opcodes.h +2 −1
  321. drivers/gpu/drm/amd/amdkfd/kfd_priv.h +171 −24
  322. drivers/gpu/drm/amd/amdkfd/kfd_process.c +67 −28
  323. drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c +371 −4
  324. drivers/gpu/drm/amd/amdkfd/kfd_queue.c +2 −1
  325. drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c +3 −2
  326. drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h +2 −1
  327. drivers/gpu/drm/amd/amdkfd/kfd_svm.c +380 −57
  328. drivers/gpu/drm/amd/amdkfd/kfd_svm.h +39 −0
  329. drivers/gpu/drm/amd/amdkfd/kfd_topology.c +5 −4
  330. drivers/gpu/drm/amd/amdkfd/kfd_topology.h +2 −1
  331. drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +61 −47
  332. drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +13 −0
  333. drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +92 −30
  334. drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c +2 −1
  335. drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +186 −33
  336. drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +280 −9
  337. drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h +14 −0
  338. drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c +88 −160
  339. drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c +2 −4
  340. drivers/gpu/drm/amd/display/dc/Makefile +4 −3
  341. drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c +0 −2
  342. drivers/gpu/drm/amd/display/dc/bios/command_table2.c +0 −4
  343. drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c +1 −0
  344. drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile +10 −0
  345. drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c +16 −0
  346. drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c +5 −2
  347. drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c +8 −8
  348. drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c +13 −13
  349. drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c +20 −7
  350. drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h +1 −1
  351. drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c +706 −0
  352. drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.h +49 −0
  353. drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c +328 −0
  354. drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h +128 −0
  355. drivers/gpu/drm/amd/display/dc/core/dc.c +71 −13
  356. drivers/gpu/drm/amd/display/dc/core/dc_link.c +366 −501
  357. drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +853 −535
  358. drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c +23 −1
  359. drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c +0 −917
  360. drivers/gpu/drm/amd/display/dc/core/dc_resource.c +74 −26
  361. drivers/gpu/drm/amd/display/dc/core/dc_stream.c +16 −0
  362. drivers/gpu/drm/amd/display/dc/dc.h +20 −21
  363. drivers/gpu/drm/amd/display/dc/dc_dp_types.h +17 −42
  364. drivers/gpu/drm/amd/display/dc/dc_helper.c +60 −0
  365. drivers/gpu/drm/amd/display/dc/dc_hw_types.h +1 −0
  366. drivers/gpu/drm/amd/display/dc/dc_link.h +14 −7
  367. drivers/gpu/drm/amd/display/dc/dc_stream.h +0 −6
  368. drivers/gpu/drm/amd/display/dc/dc_types.h +0 −6
  369. drivers/gpu/drm/amd/display/dc/dce/dce_aux.c +1 −1
  370. drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c +9 −8
  371. drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h +2 −1
  372. drivers/gpu/drm/amd/display/dc/dce/dmub_outbox.c +14 −11
  373. drivers/gpu/drm/amd/display/dc/dce/dmub_outbox.h +2 −2
  374. drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c +4 −0
  375. drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +37 −95
  376. drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +2 −7
  377. drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c +9 −9
  378. drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h +2 −1
  379. drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c +0 −15
  380. drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h +0 −3
  381. drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h +13 −2
  382. drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +9 −32
  383. drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +9 −12
  384. drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c +0 −2
  385. drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_stream_encoder.c +0 −2
  386. drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c +3 −4
  387. drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c +2 −2
  388. drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c +2 −2
  389. drivers/gpu/drm/amd/display/dc/dcn302/Makefile +0 −12
  390. drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c +12 −308
  391. drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.h +3 −0
  392. drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c +2 −2
  393. drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c +81 −25
  394. drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h +6 −0
  395. drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.c +11 −0
  396. drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.h +6 −3
  397. drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c +32 −29
  398. drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c +21 −7
  399. drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c +1 −1
  400. drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h +2 −0
  401. drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c +3 −1
  402. drivers/gpu/drm/amd/display/dc/dcn316/Makefile +12 −24
  403. drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c +2306 −0
  404. drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.h +42 −0
  405. drivers/gpu/drm/amd/display/dc/dm_helpers.h +3 −3
  406. drivers/gpu/drm/amd/display/dc/dml/Makefile +11 −1
  407. drivers/gpu/drm/amd/display/dc/dml/calcs/bw_fixed.c +0 −0
  408. drivers/gpu/drm/amd/display/dc/dml/calcs/calcs_logger.h +0 −0
  409. drivers/gpu/drm/amd/display/dc/dml/calcs/custom_float.c +0 −0
  410. drivers/gpu/drm/amd/display/dc/dml/calcs/dce_calcs.c +23 −25
  411. drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.c +0 −0
  412. drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.h +0 −0
  413. drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_math.c +0 −0
  414. drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c +0 −0
  415. drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c +357 −0
  416. drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.h +32 −0
  417. drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c +26 −3
  418. drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c +24 −0
  419. drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h +3 −0
  420. drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c +1 −1
  421. drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c +2 −2
  422. drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c +2 −2
  423. drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c +1 −0
  424. drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c +1 −0
  425. drivers/gpu/drm/amd/display/dc/inc/core_types.h +1 −12
  426. drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h +44 −12
  427. drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h +2 −2
  428. drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h +0 −2
  429. drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h +2 −3
  430. drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h +4 −6
  431. drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +0 −2
  432. drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h +0 −2
  433. drivers/gpu/drm/amd/display/dc/inc/link_dpcd.h +1 −1
  434. drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h +3 −0
  435. drivers/gpu/drm/amd/display/dc/inc/link_hwss.h +44 −42
  436. drivers/gpu/drm/amd/display/dc/inc/reg_helper.h +34 −0
  437. drivers/gpu/drm/amd/display/dc/inc/resource.h +6 −10
  438. drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c +2 −2
  439. drivers/gpu/drm/amd/display/dc/link/Makefile +30 −0
  440. drivers/gpu/drm/amd/display/dc/link/link_hwss_dio.c +137 −0
  441. drivers/gpu/drm/amd/display/dc/link/link_hwss_dio.h +53 −0
  442. drivers/gpu/drm/amd/display/dc/link/link_hwss_dpia.c +51 −0
  443. drivers/gpu/drm/amd/display/dc/link/link_hwss_dpia.h +34 −0
  444. drivers/gpu/drm/amd/display/dc/link/link_hwss_hpo_dp.c +254 −0
  445. drivers/gpu/drm/amd/display/dc/link/link_hwss_hpo_dp.h +35 −0
  446. drivers/gpu/drm/amd/display/dc/link/link_hwss_hpo_frl.c +43 −0
  447. drivers/gpu/drm/amd/display/dc/link/link_hwss_hpo_frl.h +34 −0
  448. drivers/gpu/drm/amd/display/dc/virtual/Makefile +1 −1
  449. drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c +2 −1
  450. drivers/gpu/drm/amd/display/dc/virtual/virtual_link_hwss.c +43 −0
  451. drivers/gpu/drm/amd/display/dc/virtual/virtual_link_hwss.h +34 −0
  452. drivers/gpu/drm/amd/display/dmub/dmub_srv.h +1 −0
  453. drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +8 −5
  454. drivers/gpu/drm/amd/display/dmub/src/Makefile +2 −0
  455. drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c +1 −1
  456. drivers/gpu/drm/amd/display/dmub/src/dmub_dcn316.c +62 −0
  457. drivers/gpu/drm/amd/display/dmub/src/dmub_dcn316.h +33 −0
  458. drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c +4 −0
  459. drivers/gpu/drm/amd/display/include/bios_parser_types.h +0 −2
  460. drivers/gpu/drm/amd/display/include/dal_asic_id.h +6 −1
  461. drivers/gpu/drm/amd/display/include/dal_types.h +1 −0
  462. drivers/gpu/drm/amd/display/include/ddc_service_types.h +5 −0
  463. drivers/gpu/drm/amd/display/include/dpcd_defs.h +0 −4
  464. drivers/gpu/drm/amd/display/include/grph_object_defs.h +0 −2
  465. drivers/gpu/drm/amd/display/include/grph_object_id.h +0 −2
  466. drivers/gpu/drm/amd/display/include/link_service_types.h +0 −12
  467. drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h +2 −1
  468. drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c +13 −12
  469. drivers/gpu/drm/amd/include/amd_shared.h +1 −2
  470. drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_6_offset.h +15682 −0
.mailmap+3−0
@@ -80,6 +80,9 @@ Chris Chiu <chris.chiu@canonical.com> <chiu@endlessos.org> · 79 unmodified lines
8080 Christian Borntraeger <borntraeger@linux.ibm.com> <borntraeger@de.ibm.com>
8181 Christian Borntraeger <borntraeger@linux.ibm.com> <cborntra@de.ibm.com>
8282 Christian Borntraeger <borntraeger@linux.ibm.com> <borntrae@de.ibm.com>
83+Christian Brauner <brauner@kernel.org> <christian@brauner.io>
84+Christian Brauner <brauner@kernel.org> <christian.brauner@canonical.com>
85+Christian Brauner <brauner@kernel.org> <christian.brauner@ubuntu.com>
8386 Christophe Ricard <christophe.ricard@gmail.com>
8487 Christoph Hellwig <hch@lst.de>
8588 Colin Ian King <colin.king@intel.com> <colin.king@canonical.com>
Documentation/ABI/testing/sysfs-driver-aspeed-uart-routing+3−3
@@ -1,4 +1,4 @@
1−What: /sys/bus/platform/drivers/aspeed-uart-routing/*/uart*
1+What: /sys/bus/platform/drivers/aspeed-uart-routing/\*/uart\*
22 Date: September 2021
33 Contact: Oskar Senft <osk@google.com>
44 Chia-Wei Wang <chiawei_wang@aspeedtech.com>
@@ -9,7 +9,7 @@ Description: Selects the RX source of the UARTx device. · 4 unmodified lines
99 depends on the selected file.
1010
1111 e.g.
12− cat /sys/bus/platform/drivers/aspeed-uart-routing/*.uart_routing/uart1
12+ cat /sys/bus/platform/drivers/aspeed-uart-routing/\*.uart_routing/uart1
1313 [io1] io2 io3 io4 uart2 uart3 uart4 io6
1414
1515 In this case, UART1 gets its input from IO1 (physical serial port 1).
@@ -17,7 +17,7 @@ Description: Selects the RX source of the UARTx device. · 1 unmodified line
1717 Users: OpenBMC. Proposed changes should be mailed to
1818 openbmc@lists.ozlabs.org
1919
20−What: /sys/bus/platform/drivers/aspeed-uart-routing/*/io*
20+What: /sys/bus/platform/drivers/aspeed-uart-routing/\*/io\*
2121 Date: September 2021
2222 Contact: Oskar Senft <osk@google.com>
2323 Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Documentation/arm64/silicon-errata.rst+2−0
@@ -100,6 +100,8 @@ stable kernels. · 99 unmodified lines
100100 +----------------+-----------------+-----------------+-----------------------------+
101101 | ARM | Cortex-A510 | #2051678 | ARM64_ERRATUM_2051678 |
102102 +----------------+-----------------+-----------------+-----------------------------+
103+| ARM | Cortex-A510 | #2077057 | ARM64_ERRATUM_2077057 |
104++----------------+-----------------+-----------------+-----------------------------+
103105 | ARM | Cortex-A710 | #2119858 | ARM64_ERRATUM_2119858 |
104106 +----------------+-----------------+-----------------+-----------------------------+
105107 | ARM | Cortex-A710 | #2054223 | ARM64_ERRATUM_2054223 |
Documentation/dev-tools/kselftest.rst+8−0
@@ -7,6 +7,14 @@ directory. These are intended to be small tests to exercise individual code · 6 unmodified lines
77 paths in the kernel. Tests are intended to be run after building, installing
88 and booting a kernel.
99
10+Kselftest from mainline can be run on older stable kernels. Running tests
11+from mainline offers the best coverage. Several test rings run mainline
12+kselftest suite on stable releases. The reason is that when a new test
13+gets added to test existing code to regression test a bug, we should be
14+able to run that test on an older kernel. Hence, it is important to keep
15+code that can still test an older kernel and make sure it skips the test
16+gracefully on newer releases.
17+
1018 You can find additional information on Kselftest framework, how to
1119 write new tests using the framework on Kselftest wiki:
1220
Documentation/dev-tools/kunit/usage.rst+1−1
@@ -242,7 +242,7 @@ example: · 241 unmodified lines
242242
243243 int rectangle_area(struct shape *this)
244244 {
245− struct rectangle *self = container_of(this, struct shape, parent);
245+ struct rectangle *self = container_of(this, struct rectangle, parent);
246246
247247 return self->length * self->width;
248248 };
Documentation/devicetree/bindings/arm/omap/omap.txt+3−0
@@ -119,6 +119,9 @@ Boards (incomplete list of examples): · 118 unmodified lines
119119 - OMAP3 BeagleBoard : Low cost community board
120120 compatible = "ti,omap3-beagle", "ti,omap3430", "ti,omap3"
121121
122+- OMAP3 BeagleBoard A to B4 : Early BeagleBoard revisions A to B4 with a timer quirk
123+ compatible = "ti,omap3-beagle-ab4", "ti,omap3-beagle", "ti,omap3430", "ti,omap3"
124+
122125 - OMAP3 Tobi with Overo : Commercial expansion board with daughter board
123126 compatible = "gumstix,omap3-overo-tobi", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"
124127
Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml+17−0
@@ -83,6 +83,9 @@ properties: · 82 unmodified lines
8383 type: boolean
8484 description: let the driver enable audio HDMI codec function or not.
8585
86+ aux-bus:
87+ $ref: /schemas/display/dp-aux-bus.yaml#
88+
8689 ports:
8790 $ref: /schemas/graph.yaml#/properties/ports
8891
@@ -167,5 +170,19 @@ examples: · 78 unmodified lines
167170 };
168171 };
169172 };
173+
174+ aux-bus {
175+ panel {
176+ compatible = "innolux,n125hce-gn1";
177+ power-supply = <&pp3300_disp_x>;
178+ backlight = <&backlight_lcd0>;
179+
180+ port {
181+ panel_in: endpoint {
182+ remote-endpoint = <&anx7625_out>;
183+ };
184+ };
185+ };
186+ };
170187 };
171188 };
Documentation/devicetree/bindings/display/bridge/ingenic,jz4780-hdmi.yaml+82−0
@@ -0,0 +1,82 @@
1+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2+%YAML 1.2
3+---
4+$id: http://devicetree.org/schemas/display/bridge/ingenic,jz4780-hdmi.yaml#
5+$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+title: Bindings for Ingenic JZ4780 HDMI Transmitter
8+
9+maintainers:
10+ - H. Nikolaus Schaller <hns@goldelico.com>
11+
12+description: |
13+ The HDMI Transmitter in the Ingenic JZ4780 is a Synopsys DesignWare HDMI 1.4
14+ TX controller IP with accompanying PHY IP.
15+
16+allOf:
17+ - $ref: synopsys,dw-hdmi.yaml#
18+
19+properties:
20+ compatible:
21+ const: ingenic,jz4780-dw-hdmi
22+
23+ reg-io-width:
24+ const: 4
25+
26+ clocks:
27+ maxItems: 2
28+
29+ ports:
30+ $ref: /schemas/graph.yaml#/properties/ports
31+
32+ properties:
33+ port@0:
34+ $ref: /schemas/graph.yaml#/properties/port
35+ description: Input from LCD controller output.
36+
37+ port@1:
38+ $ref: /schemas/graph.yaml#/properties/port
39+ description: Link to the HDMI connector.
40+
41+required:
42+ - compatible
43+ - clocks
44+ - clock-names
45+ - ports
46+ - reg-io-width
47+
48+unevaluatedProperties: false
49+
50+examples:
51+ - |
52+ #include <dt-bindings/clock/ingenic,jz4780-cgu.h>
53+
54+ hdmi: hdmi@10180000 {
55+ compatible = "ingenic,jz4780-dw-hdmi";
56+ reg = <0x10180000 0x8000>;
57+ reg-io-width = <4>;
58+ ddc-i2c-bus = <&i2c4>;
59+ interrupt-parent = <&intc>;
60+ interrupts = <3>;
61+ clocks = <&cgu JZ4780_CLK_AHB0>, <&cgu JZ4780_CLK_HDMI>;
62+ clock-names = "iahb", "isfr";
63+
64+ ports {
65+ #address-cells = <1>;
66+ #size-cells = <0>;
67+ hdmi_in: port@0 {
68+ reg = <0>;
69+ dw_hdmi_in: endpoint {
70+ remote-endpoint = <&jz4780_lcd_out>;
71+ };
72+ };
73+ hdmi_out: port@1 {
74+ reg = <1>;
75+ dw_hdmi_out: endpoint {
76+ remote-endpoint = <&hdmi_con>;
77+ };
78+ };
79+ };
80+ };
81+
82+...
Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml+1−1
@@ -68,7 +68,7 @@ properties: · 67 unmodified lines
6868 - vesa-24
6969 description: |
7070 The color signals mapping order. See details in
71− Documentation/devicetree/bindings/display/panel/lvds.yaml
71+ Documentation/devicetree/bindings/display/lvds.yaml
7272
7373 port@1:
7474 $ref: /schemas/graph.yaml#/properties/port
Documentation/devicetree/bindings/display/lvds.yamlrenamed from Documentation/devicetree/bindings/display/panel/lvds.yaml+4−31
@@ -1,10 +1,10 @@
11 # SPDX-License-Identifier: GPL-2.0
22 %YAML 1.2
33 ---
4−$id: http://devicetree.org/schemas/display/panel/lvds.yaml#
4+$id: http://devicetree.org/schemas/display/lvds.yaml#
55 $schema: http://devicetree.org/meta-schemas/core.yaml#
66
7−title: LVDS Display Panel
7+title: LVDS Display Common Properties
88
99 maintainers:
1010 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
@@ -13,8 +13,8 @@ maintainers: · 2 unmodified lines
1313 description: |+
1414 LVDS is a physical layer specification defined in ANSI/TIA/EIA-644-A. Multiple
1515 incompatible data link layers have been used over time to transmit image data
16− to LVDS panels. This bindings supports display panels compatible with the
17− following specifications.
16+ to LVDS devices. This bindings supports devices compatible with the following
17+ specifications.
1818
1919 [JEIDA] "Digital Interface Standards for Monitor", JEIDA-59-1999, February
2020 1999 (Version 1.0), Japan Electronic Industry Development Association (JEIDA)
@@ -26,18 +26,7 @@ description: |+ · 5 unmodified lines
2626 Device compatible with those specifications have been marketed under the
2727 FPD-Link and FlatLink brands.
2828
29−allOf:
30− - $ref: panel-common.yaml#
31−
3229 properties:
33− compatible:
34− contains:
35− const: panel-lvds
36− description:
37− Shall contain "panel-lvds" in addition to a mandatory panel-specific
38− compatible string defined in individual panel bindings. The "panel-lvds"
39− value shall never be used on its own.
40−
4130 data-mapping:
4231 enum:
4332 - jeida-18
@@ -96,22 +85,6 @@ properties: · 52 unmodified lines
9685 If set, reverse the bit order described in the data mappings below on all
9786 data lanes, transmitting bits for slots 6 to 0 instead of 0 to 6.
9887
99− port: true
100− ports: true
101−
102−required:
103− - compatible
104− - data-mapping
105− - width-mm
106− - height-mm
107− - panel-timing
108−
109−oneOf:
110− - required:
111− - port
112− - required:
113− - ports
114−
11588 additionalProperties: true
11689
11790 ...
Documentation/devicetree/bindings/display/panel/advantech,idk-1110wr.yaml+17−2
@@ -11,13 +11,23 @@ maintainers: · 10 unmodified lines
1111 - Thierry Reding <thierry.reding@gmail.com>
1212
1313 allOf:
14− - $ref: lvds.yaml#
14+ - $ref: panel-common.yaml#
15+ - $ref: /schemas/display/lvds.yaml/#
16+
17+select:
18+ properties:
19+ compatible:
20+ contains:
21+ const: advantech,idk-1110wr
22+
23+ required:
24+ - compatible
1525
1626 properties:
1727 compatible:
1828 items:
1929 - const: advantech,idk-1110wr
20− - {} # panel-lvds, but not listed here to avoid false select
30+ - const: panel-lvds
2131
2232 data-mapping:
2333 const: jeida-24
@@ -35,6 +45,11 @@ additionalProperties: false · 11 unmodified lines
3545
3646 required:
3747 - compatible
48+ - data-mapping
49+ - width-mm
50+ - height-mm
51+ - panel-timing
52+ - port
3853
3954 examples:
4055 - |+
Documentation/devicetree/bindings/display/panel/innolux,ee101ia-01d.yaml+21−2
@@ -11,15 +11,26 @@ maintainers: · 10 unmodified lines
1111 - Thierry Reding <thierry.reding@gmail.com>
1212
1313 allOf:
14− - $ref: lvds.yaml#
14+ - $ref: panel-common.yaml#
15+ - $ref: /schemas/display/lvds.yaml/#
16+
17+select:
18+ properties:
19+ compatible:
20+ contains:
21+ const: innolux,ee101ia-01d
22+
23+ required:
24+ - compatible
1525
1626 properties:
1727 compatible:
1828 items:
1929 - const: innolux,ee101ia-01d
20− - {} # panel-lvds, but not listed here to avoid false select
30+ - const: panel-lvds
2131
2232 backlight: true
33+ data-mapping: true
2334 enable-gpios: true
2435 power-supply: true
2536 width-mm: true
@@ -27,5 +38,13 @@ properties: · 1 unmodified line
2738 panel-timing: true
2839 port: true
2940
41+required:
42+ - compatible
43+ - data-mapping
44+ - width-mm
45+ - height-mm
46+ - panel-timing
47+ - port
48+
3049 additionalProperties: false
3150 ...
Documentation/devicetree/bindings/display/panel/mitsubishi,aa104xd12.yaml+17−2
@@ -11,13 +11,23 @@ maintainers: · 10 unmodified lines
1111 - Thierry Reding <thierry.reding@gmail.com>
1212
1313 allOf:
14− - $ref: lvds.yaml#
14+ - $ref: panel-common.yaml#
15+ - $ref: /schemas/display/lvds.yaml/#
16+
17+select:
18+ properties:
19+ compatible:
20+ contains:
21+ const: mitsubishi,aa104xd12
22+
23+ required:
24+ - compatible
1525
1626 properties:
1727 compatible:
1828 items:
1929 - const: mitsubishi,aa104xd12
20− - {} # panel-lvds, but not listed here to avoid false select
30+ - const: panel-lvds
2131
2232 vcc-supply:
2333 description: Reference to the regulator powering the panel VCC pins.
@@ -39,6 +49,11 @@ additionalProperties: false · 15 unmodified lines
3949 required:
4050 - compatible
4151 - vcc-supply
52+ - data-mapping
53+ - width-mm
54+ - height-mm
55+ - panel-timing
56+ - port
4257
4358 examples:
4459 - |+
Documentation/devicetree/bindings/display/panel/mitsubishi,aa121td01.yaml+17−2
@@ -11,13 +11,23 @@ maintainers: · 10 unmodified lines
1111 - Thierry Reding <thierry.reding@gmail.com>
1212
1313 allOf:
14− - $ref: lvds.yaml#
14+ - $ref: panel-common.yaml#
15+ - $ref: /schemas/display/lvds.yaml/#
16+
17+select:
18+ properties:
19+ compatible:
20+ contains:
21+ const: mitsubishi,aa121td01
22+
23+ required:
24+ - compatible
1525
1626 properties:
1727 compatible:
1828 items:
1929 - const: mitsubishi,aa121td01
20− - {} # panel-lvds, but not listed here to avoid false select
30+ - const: panel-lvds
2131
2232 vcc-supply:
2333 description: Reference to the regulator powering the panel VCC pins.
@@ -39,6 +49,11 @@ additionalProperties: false · 15 unmodified lines
3949 required:
4050 - compatible
4151 - vcc-supply
52+ - data-mapping
53+ - width-mm
54+ - height-mm
55+ - panel-timing
56+ - port
4257
4358 examples:
4459 - |+
Documentation/devicetree/bindings/display/panel/panel-lvds.yaml+57−0
@@ -0,0 +1,57 @@
1+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+%YAML 1.2
3+---
4+$id: http://devicetree.org/schemas/display/panel/panel-lvds.yaml#
5+$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+title: Generic LVDS Display Panel Device Tree Bindings
8+
9+maintainers:
10+ - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
11+ - Thierry Reding <thierry.reding@gmail.com>
12+
13+allOf:
14+ - $ref: panel-common.yaml#
15+ - $ref: /schemas/display/lvds.yaml/#
16+
17+select:
18+ properties:
19+ compatible:
20+ contains:
21+ const: panel-lvds
22+
23+ not:
24+ properties:
25+ compatible:
26+ contains:
27+ enum:
28+ - advantech,idk-1110wr
29+ - advantech,idk-2121wr
30+ - innolux,ee101ia-01d
31+ - mitsubishi,aa104xd12
32+ - mitsubishi,aa121td01
33+ - sgd,gktw70sdae4se
34+
35+ required:
36+ - compatible
37+
38+properties:
39+ compatible:
40+ items:
41+ - enum:
42+ - auo,b101ew05
43+ - tbs,a711-panel
44+
45+ - const: panel-lvds
46+
47+unevaluatedProperties: false
48+
49+required:
50+ - compatible
51+ - data-mapping
52+ - width-mm
53+ - height-mm
54+ - panel-timing
55+ - port
56+
57+...
Documentation/devicetree/bindings/display/panel/panel-simple.yaml+2−0
@@ -284,6 +284,8 @@ properties: · 283 unmodified lines
284284 - sharp,lq101k1ly04
285285 # Sharp 12.3" (2400x1600 pixels) TFT LCD panel
286286 - sharp,lq123p1jx31
287+ # Sharp 14" (1920x1080 pixels) TFT LCD panel
288+ - sharp,lq140m1jw46
287289 # Sharp LS020B1DD01D 2.0" HQVGA TFT LCD panel
288290 - sharp,ls020b1dd01d
289291 # Shelly SCA07010-BFN-LNN 7.0" WVGA TFT LCD panel
Documentation/devicetree/bindings/display/panel/sgd,gktw70sdae4se.yaml+17−2
@@ -11,13 +11,23 @@ maintainers: · 10 unmodified lines
1111 - Thierry Reding <thierry.reding@gmail.com>
1212
1313 allOf:
14− - $ref: lvds.yaml#
14+ - $ref: panel-common.yaml#
15+ - $ref: /schemas/display/lvds.yaml/#
16+
17+select:
18+ properties:
19+ compatible:
20+ contains:
21+ const: sgd,gktw70sdae4se
22+
23+ required:
24+ - compatible
1525
1626 properties:
1727 compatible:
1828 items:
1929 - const: sgd,gktw70sdae4se
20− - {} # panel-lvds, but not listed here to avoid false select
30+ - const: panel-lvds
2131
2232 data-mapping:
2333 const: jeida-18
@@ -35,6 +45,11 @@ additionalProperties: false · 11 unmodified lines
3545
3646 required:
3747 - compatible
48+ - port
49+ - data-mapping
50+ - width-mm
51+ - height-mm
52+ - panel-timing
3853
3954 examples:
4055 - |+
Documentation/devicetree/bindings/display/solomon,ssd1307fb.yaml+1−0
@@ -8,6 +8,7 @@ title: Solomon SSD1307 OLED Controller Framebuffer · 7 unmodified lines
88
99 maintainers:
1010 - Maxime Ripard <mripard@kernel.org>
11+ - Javier Martinez Canillas <javierm@redhat.com>
1112
1213 properties:
1314 compatible:
Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml+15−0
@@ -159,6 +159,21 @@ allOf: · 158 unmodified lines
159159 power-domains:
160160 maxItems: 1
161161 sram-supply: false
162+ - if:
163+ properties:
164+ compatible:
165+ contains:
166+ const: rockchip,rk3568-mali
167+ then:
168+ properties:
169+ clocks:
170+ minItems: 2
171+ clock-names:
172+ items:
173+ - const: gpu
174+ - const: bus
175+ required:
176+ - clock-names
162177
163178 examples:
164179 - |
Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml+15−6
@@ -35,6 +35,10 @@ description: · 34 unmodified lines
3535 contains a specific memory layout, which is documented in chapter 8 of the
3636 SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
3737
38+ The thead,c900-plic is different from sifive,plic-1.0.0 in opensbi, the
39+ T-HEAD PLIC implementation requires setting a delegation bit to allow access
40+ from S-mode. So add thead,c900-plic to distinguish them.
41+
3842 maintainers:
3943 - Sagar Kadam <sagar.kadam@sifive.com>
4044 - Paul Walmsley <paul.walmsley@sifive.com>
@@ -42,12 +46,17 @@ maintainers: · 1 unmodified line
4246
4347 properties:
4448 compatible:
45− items:
46− - enum:
47− - sifive,fu540-c000-plic
48− - starfive,jh7100-plic
49− - canaan,k210-plic
50− - const: sifive,plic-1.0.0
49+ oneOf:
50+ - items:
51+ - enum:
52+ - sifive,fu540-c000-plic
53+ - starfive,jh7100-plic
54+ - canaan,k210-plic
55+ - const: sifive,plic-1.0.0
56+ - items:
57+ - enum:
58+ - allwinner,sun20i-d1-plic
59+ - const: thead,c900-plic
5160
5261 reg:
5362 maxItems: 1
Documentation/devicetree/bindings/net/qcom,ipa.yaml+6−0
@@ -107,6 +107,10 @@ properties: · 106 unmodified lines
107107 - const: imem
108108 - const: config
109109
110+ qcom,qmp:
111+ $ref: /schemas/types.yaml#/definitions/phandle
112+ description: phandle to the AOSS side-channel message RAM
113+
110114 qcom,smem-states:
111115 $ref: /schemas/types.yaml#/definitions/phandle-array
112116 description: State bits used in by the AP to signal the modem.
@@ -222,6 +226,8 @@ examples: · 109 unmodified lines
222226 "imem",
223227 "config";
224228
229+ qcom,qmp = <&aoss_qmp>;
230+
225231 qcom,smem-states = <&ipa_smp2p_out 0>,
226232 <&ipa_smp2p_out 1>;
227233 qcom,smem-state-names = "ipa-clock-enabled-valid",
Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml+3−2
@@ -23,8 +23,9 @@ properties: · 22 unmodified lines
2323 minItems: 1
2424 maxItems: 256
2525 items:
26− minimum: 0
27− maximum: 256
26+ items:
27+ - minimum: 0
28+ maximum: 256
2829 description:
2930 Chip select used by the device.
3031
Documentation/driver-api/device-io.rst+9−0
@@ -502,6 +502,15 @@ pcim_iomap() · 501 unmodified lines
502502 Not using these wrappers may make drivers unusable on certain platforms with
503503 stricter rules for mapping I/O memory.
504504
505+Generalizing Access to System and I/O Memory
506+============================================
507+
508+.. kernel-doc:: include/linux/iosys-map.h
509+ :doc: overview
510+
511+.. kernel-doc:: include/linux/iosys-map.h
512+ :internal:
513+
505514 Public Functions Provided
506515 =========================
507516
Documentation/driver-api/dma-buf.rst+0−9
@@ -128,15 +128,6 @@ Kernel Functions and Structures Reference · 127 unmodified lines
128128 .. kernel-doc:: include/linux/dma-buf.h
129129 :internal:
130130
131−Buffer Mapping Helpers
132−~~~~~~~~~~~~~~~~~~~~~~
133−
134−.. kernel-doc:: include/linux/dma-buf-map.h
135− :doc: overview
136−
137−.. kernel-doc:: include/linux/dma-buf-map.h
138− :internal:
139−
140131 Reservation Objects
141132 -------------------
142133
Documentation/filesystems/netfs_library.rst+16−0
@@ -462,6 +462,10 @@ operation table looks like the following:: · 461 unmodified lines
462462 struct iov_iter *iter,
463463 netfs_io_terminated_t term_func,
464464 void *term_func_priv);
465+
466+ int (*query_occupancy)(struct netfs_cache_resources *cres,
467+ loff_t start, size_t len, size_t granularity,
468+ loff_t *_data_start, size_t *_data_len);
465469 };
466470
467471 With a termination handler function pointer::
@@ -536,6 +540,18 @@ The methods defined in the table are: · 68 unmodified lines
536540 indicating whether the termination is definitely happening in the caller's
537541 context.
538542
543+ * ``query_occupancy()``
544+
545+ [Required] Called to find out where the next piece of data is within a
546+ particular region of the cache. The start and length of the region to be
547+ queried are passed in, along with the granularity to which the answer needs
548+ to be aligned. The function passes back the start and length of the data,
549+ if any, available within that region. Note that there may be a hole at the
550+ front.
551+
552+ It returns 0 if some data was found, -ENODATA if there was no usable data
553+ within the region or -ENOBUFS if there is no caching on this file.
554+
539555 Note that these methods are passed a pointer to the cache resource structure,
540556 not the read request structure as they could be used in other situations where
541557 there isn't a read request structure as well, such as writing dirty data to the
Documentation/gpu/todo.rst+10−34
@@ -222,7 +222,7 @@ Convert drivers to use drm_fbdev_generic_setup() · 221 unmodified lines
222222 Most drivers can use drm_fbdev_generic_setup(). Driver have to implement
223223 atomic modesetting and GEM vmap support. Historically, generic fbdev emulation
224224 expected the framebuffer in system memory or system-like memory. By employing
225−struct dma_buf_map, drivers with frambuffers in I/O memory can be supported
225+struct iosys_map, drivers with frambuffers in I/O memory can be supported
226226 as well.
227227
228228 Contact: Maintainer of the driver you plan to convert
@@ -234,7 +234,7 @@ Reimplement functions in drm_fbdev_fb_ops without fbdev · 5 unmodified lines
234234
235235 A number of callback functions in drm_fbdev_fb_ops could benefit from
236236 being rewritten without dependencies on the fbdev module. Some of the
237−helpers could further benefit from using struct dma_buf_map instead of
237+helpers could further benefit from using struct iosys_map instead of
238238 raw pointers.
239239
240240 Contact: Thomas Zimmermann <tzimmermann@suse.de>, Daniel Vetter
@@ -300,30 +300,6 @@ Contact: Daniel Vetter, Noralf Tronnes · 59 unmodified lines
300300
301301 Level: Advanced
302302
303−Garbage collect fbdev scrolling acceleration
304−--------------------------------------------
305−
306−Scroll acceleration has been disabled in fbcon. Now it works as the old
307−SCROLL_REDRAW mode. A ton of code was removed in fbcon.c and the hook bmove was
308−removed from fbcon_ops.
309−Remaining tasks:
310−
311−- a bunch of the hooks in fbcon_ops could be removed or simplified by calling
312− directly instead of the function table (with a switch on p->rotate)
313−
314−- fb_copyarea is unused after this, and can be deleted from all drivers
315−
316−- after that, fb_copyarea can be deleted from fb_ops in include/linux/fb.h as
317− well as cfb_copyarea
318−
319−Note that not all acceleration code can be deleted, since clearing and cursor
320−support is still accelerated, which might be good candidates for further
321−deletion projects.
322−
323−Contact: Daniel Vetter
324−
325−Level: Intermediate
326−
327303 idr_init_base()
328304 ---------------
329305
@@ -434,19 +410,19 @@ Contact: Emil Velikov, respective driver maintainers · 104 unmodified lines
434410
435411 Level: Intermediate
436412
437−Use struct dma_buf_map throughout codebase
438−------------------------------------------
413+Use struct iosys_map throughout codebase
414+----------------------------------------
439415
440−Pointers to shared device memory are stored in struct dma_buf_map. Each
416+Pointers to shared device memory are stored in struct iosys_map. Each
441417 instance knows whether it refers to system or I/O memory. Most of the DRM-wide
442−interface have been converted to use struct dma_buf_map, but implementations
418+interface have been converted to use struct iosys_map, but implementations
443419 often still use raw pointers.
444420
445−The task is to use struct dma_buf_map where it makes sense.
421+The task is to use struct iosys_map where it makes sense.
446422
447−* Memory managers should use struct dma_buf_map for dma-buf-imported buffers.
448−* TTM might benefit from using struct dma_buf_map internally.
449−* Framebuffer copying and blitting helpers should operate on struct dma_buf_map.
423+* Memory managers should use struct iosys_map for dma-buf-imported buffers.
424+* TTM might benefit from using struct iosys_map internally.
425+* Framebuffer copying and blitting helpers should operate on struct iosys_map.
450426
451427 Contact: Thomas Zimmermann <tzimmermann@suse.de>, Christian König, Daniel Vetter
452428
Documentation/userspace-api/ioctl/ioctl-number.rst+3−0
@@ -115,6 +115,7 @@ Code Seq# Include File Comments · 114 unmodified lines
115115 'B' 00-1F linux/cciss_ioctl.h conflict!
116116 'B' 00-0F include/linux/pmu.h conflict!
117117 'B' C0-FF advanced bbus <mailto:maassen@uni-freiburg.de>
118+'B' 00-0F xen/xenbus_dev.h conflict!
118119 'C' all linux/soundcard.h conflict!
119120 'C' 01-2F linux/capi.h conflict!
120121 'C' F0-FF drivers/net/wan/cosa.h conflict!
@@ -134,6 +135,7 @@ Code Seq# Include File Comments · 13 unmodified lines
134135 'F' 80-8F linux/arcfb.h conflict!
135136 'F' DD video/sstfb.h conflict!
136137 'G' 00-3F drivers/misc/sgi-gru/grulib.h conflict!
138+'G' 00-0F xen/gntalloc.h, xen/gntdev.h conflict!
137139 'H' 00-7F linux/hiddev.h conflict!
138140 'H' 00-0F linux/hidraw.h conflict!
139141 'H' 01 linux/mei.h conflict!
@@ -176,6 +178,7 @@ Code Seq# Include File Comments · 36 unmodified lines
176178 'P' 60-6F sound/sscape_ioctl.h conflict!
177179 'P' 00-0F drivers/usb/class/usblp.c conflict!
178180 'P' 01-09 drivers/misc/pci_endpoint_test.c conflict!
181+'P' 00-0F xen/privcmd.h conflict!
179182 'Q' all linux/soundcard.h
180183 'R' 00-1F linux/random.h conflict!
181184 'R' 01 linux/rfkill.h conflict!
MAINTAINERS+89−20
@@ -1620,6 +1620,7 @@ M: Olof Johansson <olof@lixom.net> · 1619 unmodified lines
16201620 M: soc@kernel.org
16211621 L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
16221622 S: Maintained
1623+C: irc://irc.libera.chat/armlinux
16231624 T: git git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git
16241625 F: arch/arm/boot/dts/Makefile
16251626 F: arch/arm64/boot/dts/Makefile
@@ -1627,6 +1628,7 @@ F: arch/arm64/boot/dts/Makefile · 1 unmodified line
16271628 ARM SUB-ARCHITECTURES
16281629 L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
16291630 S: Maintained
1631+C: irc://irc.libera.chat/armlinux
16301632 T: git git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git
16311633 F: arch/arm/mach-*/
16321634 F: arch/arm/plat-*/
@@ -1780,6 +1782,7 @@ F: drivers/irqchip/irq-apple-aic.c · 147 unmodified lines
17801782 F: drivers/mailbox/apple-mailbox.c
17811783 F: drivers/pinctrl/pinctrl-apple-gpio.c
17821784 F: drivers/soc/apple/*
1785+F: drivers/watchdog/apple_wdt.c
17831786 F: include/dt-bindings/interrupt-controller/apple-aic.h
17841787 F: include/dt-bindings/pinctrl/apple.h
17851788 F: include/linux/apple-mailbox.h
@@ -2570,10 +2573,13 @@ N: rockchip · 784 unmodified lines
25702573
25712574 ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES
25722575 M: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2576+R: Alim Akhtar <alim.akhtar@samsung.com>
25732577 L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
25742578 L: linux-samsung-soc@vger.kernel.org
25752579 S: Maintained
2580+C: irc://irc.libera.chat/linux-exynos
25762581 Q: https://patchwork.kernel.org/project/linux-samsung-soc/list/
2582+T: git git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git
25772583 F: Documentation/arm/samsung/
25782584 F: Documentation/devicetree/bindings/arm/samsung/
25792585 F: Documentation/devicetree/bindings/power/pd-samsung.yaml
@@ -4157,9 +4163,8 @@ N: csky · 1577 unmodified lines
41574163 K: csky
41584164
41594165 CA8210 IEEE-802.15.4 RADIO DRIVER
4160−M: Harry Morris <h.morris@cascoda.com>
41614166 L: linux-wpan@vger.kernel.org
4162−S: Maintained
4167+S: Orphan
41634168 W: https://github.com/Cascoda/ca8210-linux.git
41644169 F: Documentation/devicetree/bindings/net/ieee802154/ca8210.txt
41654170 F: drivers/net/ieee802154/ca8210.c
@@ -5734,7 +5739,7 @@ T: git git://anongit.freedesktop.org/drm/drm-misc · 1568 unmodified lines
57345739 F: Documentation/driver-api/dma-buf.rst
57355740 F: drivers/dma-buf/
57365741 F: include/linux/*fence.h
5737−F: include/linux/dma-buf*
5742+F: include/linux/dma-buf.h
57385743 F: include/linux/dma-resv.h
57395744 K: \bdma_(?:buf|fence|resv)\b
57405745
@@ -5773,7 +5778,7 @@ F: tools/testing/selftests/dma/ · 32 unmodified lines
57735778
57745779 DMA-BUF HEAPS FRAMEWORK
57755780 M: Sumit Semwal <sumit.semwal@linaro.org>
5776−R: Benjamin Gaignard <benjamin.gaignard@linaro.org>
5781+R: Benjamin Gaignard <benjamin.gaignard@collabora.com>
57775782 R: Liam Mark <lmark@codeaurora.org>
57785783 R: Laura Abbott <labbott@redhat.com>
57795784 R: Brian Starkey <Brian.Starkey@arm.com>
@@ -6077,7 +6082,8 @@ L: dri-devel@lists.freedesktop.org · 297 unmodified lines
60776082 T: git git://anongit.freedesktop.org/drm/drm-misc
60786083 S: Maintained
60796084 F: drivers/gpu/drm/panel/panel-lvds.c
6080−F: Documentation/devicetree/bindings/display/panel/lvds.yaml
6085+F: Documentation/devicetree/bindings/display/lvds.yaml
6086+F: Documentation/devicetree/bindings/display/panel/panel-lvds.yaml
60816087
60826088 DRM DRIVER FOR MANTIX MLAF057WE51 PANELS
60836089 M: Guido Günther <agx@sigxcpu.org>
@@ -6126,6 +6132,13 @@ T: git git://anongit.freedesktop.org/drm/drm-misc · 42 unmodified lines
61266132 F: Documentation/devicetree/bindings/display/panel/novatek,nt35510.yaml
61276133 F: drivers/gpu/drm/panel/panel-novatek-nt35510.c
61286134
6135+DRM DRIVER FOR NOVATEK NT35560 PANELS
6136+M: Linus Walleij <linus.walleij@linaro.org>
6137+S: Maintained
6138+T: git git://anongit.freedesktop.org/drm/drm-misc
6139+F: Documentation/devicetree/bindings/display/panel/sony,acx424akp.yaml
6140+F: drivers/gpu/drm/panel/panel-novatek-nt35560.c
6141+
61296142 DRM DRIVER FOR NOVATEK NT36672A PANELS
61306143 M: Sumit Semwal <sumit.semwal@linaro.org>
61316144 S: Maintained
@@ -6162,6 +6175,13 @@ T: git git://anongit.freedesktop.org/drm/drm-misc · 30 unmodified lines
61626175 F: Documentation/devicetree/bindings/display/repaper.txt
61636176 F: drivers/gpu/drm/tiny/repaper.c
61646177
6178+DRM DRIVER FOR SOLOMON SSD130X OLED DISPLAYS
6179+M: Javier Martinez Canillas <javierm@redhat.com>
6180+S: Maintained
6181+T: git git://anongit.freedesktop.org/drm/drm-misc
6182+F: Documentation/devicetree/bindings/display/solomon,ssd1307fb.yaml
6183+F: drivers/gpu/drm/solomon/ssd130x*
6184+
61656185 DRM DRIVER FOR QEMU'S CIRRUS DEVICE
61666186 M: Dave Airlie <airlied@redhat.com>
61676187 M: Gerd Hoffmann <kraxel@redhat.com>
@@ -6250,12 +6270,6 @@ T: git git://anongit.freedesktop.org/drm/drm-misc · 82 unmodified lines
62506270 F: Documentation/devicetree/bindings/display/sitronix,st7735r.yaml
62516271 F: drivers/gpu/drm/tiny/st7735r.c
62526272
6253−DRM DRIVER FOR SONY ACX424AKP PANELS
6254−M: Linus Walleij <linus.walleij@linaro.org>
6255−S: Maintained
6256−T: git git://anongit.freedesktop.org/drm/drm-misc
6257−F: drivers/gpu/drm/panel/panel-sony-acx424akp.c
6258−
62596273 DRM DRIVER FOR ST-ERICSSON MCDE
62606274 M: Linus Walleij <linus.walleij@linaro.org>
62616275 S: Maintained
@@ -6503,7 +6517,7 @@ F: Documentation/devicetree/bindings/display/rockchip/ · 241 unmodified lines
65036517 F: drivers/gpu/drm/rockchip/
65046518
65056519 DRM DRIVERS FOR STI
6506−M: Benjamin Gaignard <benjamin.gaignard@linaro.org>
6520+M: Alain Volmat <alain.volmat@foss.st.com>
65076521 L: dri-devel@lists.freedesktop.org
65086522 S: Maintained
65096523 T: git git://anongit.freedesktop.org/drm/drm-misc
@@ -6512,8 +6526,8 @@ F: drivers/gpu/drm/sti · 2 unmodified lines
65126526
65136527 DRM DRIVERS FOR STM
65146528 M: Yannick Fertre <yannick.fertre@foss.st.com>
6529+M: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
65156530 M: Philippe Cornu <philippe.cornu@foss.st.com>
6516−M: Benjamin Gaignard <benjamin.gaignard@linaro.org>
65176531 L: dri-devel@lists.freedesktop.org
65186532 S: Maintained
65196533 T: git git://anongit.freedesktop.org/drm/drm-misc
@@ -7576,6 +7590,12 @@ S: Maintained · 1056 unmodified lines
75767590 W: http://floatingpoint.sourceforge.net/emulator/index.html
75777591 F: arch/x86/math-emu/
75787592
7593+FRAMEBUFFER CORE
7594+M: Daniel Vetter <daniel@ffwll.ch>
7595+F: drivers/video/fbdev/core/
7596+S: Odd Fixes
7597+T: git git://anongit.freedesktop.org/drm/drm-misc
7598+
75797599 FRAMEBUFFER LAYER
75807600 M: Helge Deller <deller@gmx.de>
75817601 L: linux-fbdev@vger.kernel.org
@@ -10050,6 +10070,13 @@ F: include/linux/iova.h · 2468 unmodified lines
1005010070 F: include/linux/of_iommu.h
1005110071 F: include/uapi/linux/iommu.h
1005210072
10073+IOSYS-MAP HELPERS
10074+M: Thomas Zimmermann <tzimmermann@suse.de>
10075+L: dri-devel@lists.freedesktop.org
10076+S: Maintained
10077+T: git git://anongit.freedesktop.org/drm/drm-misc
10078+F: include/linux/iosys-map.h
10079+
1005310080 IO_URING
1005410081 M: Jens Axboe <axboe@kernel.dk>
1005510082 R: Pavel Begunkov <asml.silence@gmail.com>
@@ -10880,6 +10907,12 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/axboe/linux-block.git · 824 unmodified lines
1088010907 F: drivers/ata/pata_arasan_cf.c
1088110908 F: include/linux/pata_arasan_cf_data.h
1088210909
10910+LIBATA PATA DRIVERS
10911+R: Sergey Shtylyov <s.shtylyov@omp.ru>
10912+L: linux-ide@vger.kernel.org
10913+F: drivers/ata/ata_*.c
10914+F: drivers/ata/pata_*.c
10915+
1088310916 LIBATA PATA FARADAY FTIDE010 AND GEMINI SATA BRIDGE DRIVERS
1088410917 M: Linus Walleij <linus.walleij@linaro.org>
1088510918 L: linux-ide@vger.kernel.org
@@ -12400,7 +12433,7 @@ F: include/uapi/linux/membarrier.h · 1514 unmodified lines
1240012433 F: kernel/sched/membarrier.c
1240112434
1240212435 MEMBLOCK
12403−M: Mike Rapoport <rppt@linux.ibm.com>
12436+M: Mike Rapoport <rppt@kernel.org>
1240412437 L: linux-mm@kvack.org
1240512438 S: Maintained
1240612439 F: Documentation/core-api/boot-time-mm.rst
@@ -13298,8 +13331,8 @@ W: http://www.iptables.org/ · 891 unmodified lines
1329813331 W: http://www.nftables.org/
1329913332 Q: http://patchwork.ozlabs.org/project/netfilter-devel/list/
1330013333 C: irc://irc.libera.chat/netfilter
13301−T: git git://git.kernel.org/pub/scm/linux/kernel/git/pablo/nf.git
13302−T: git git://git.kernel.org/pub/scm/linux/kernel/git/pablo/nf-next.git
13334+T: git git://git.kernel.org/pub/scm/linux/kernel/git/netfilter/nf.git
13335+T: git git://git.kernel.org/pub/scm/linux/kernel/git/netfilter/nf-next.git
1330313336 F: include/linux/netfilter*
1330413337 F: include/linux/netfilter/
1330513338 F: include/net/netfilter/
@@ -13566,7 +13599,7 @@ F: tools/testing/selftests/nci/ · 260 unmodified lines
1356613599
1356713600 NFS, SUNRPC, AND LOCKD CLIENTS
1356813601 M: Trond Myklebust <trond.myklebust@hammerspace.com>
13569−M: Anna Schumaker <anna.schumaker@netapp.com>
13602+M: Anna Schumaker <anna@kernel.org>
1357013603 L: linux-nfs@vger.kernel.org
1357113604 S: Maintained
1357213605 W: http://client.linux-nfs.org
@@ -14384,6 +14417,7 @@ M: Rob Herring <robh+dt@kernel.org> · 811 unmodified lines
1438414417 M: Frank Rowand <frowand.list@gmail.com>
1438514418 L: devicetree@vger.kernel.org
1438614419 S: Maintained
14420+C: irc://irc.libera.chat/devicetree
1438714421 W: http://www.devicetree.org/
1438814422 T: git git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git
1438914423 F: Documentation/ABI/testing/sysfs-firmware-ofw
@@ -14395,6 +14429,7 @@ OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS · 5 unmodified lines
1439514429 M: Rob Herring <robh+dt@kernel.org>
1439614430 L: devicetree@vger.kernel.org
1439714431 S: Maintained
14432+C: irc://irc.libera.chat/devicetree
1439814433 Q: http://patchwork.ozlabs.org/project/devicetree-bindings/list/
1439914434 T: git git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git
1440014435 F: Documentation/devicetree/
@@ -15285,9 +15320,11 @@ PIN CONTROLLER - SAMSUNG · 884 unmodified lines
1528515320 M: Tomasz Figa <tomasz.figa@gmail.com>
1528615321 M: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
1528715322 M: Sylwester Nawrocki <s.nawrocki@samsung.com>
15323+R: Alim Akhtar <alim.akhtar@samsung.com>
1528815324 L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
1528915325 L: linux-samsung-soc@vger.kernel.org
1529015326 S: Maintained
15327+C: irc://irc.libera.chat/linux-exynos
1529115328 Q: https://patchwork.kernel.org/project/linux-samsung-soc/list/
1529215329 T: git git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung.git
1529315330 F: Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -16469,6 +16506,14 @@ F: Documentation/devicetree/bindings/i2c/renesas,rmobile-iic.yaml · 1175 unmodified lines
1646916506 F: drivers/i2c/busses/i2c-rcar.c
1647016507 F: drivers/i2c/busses/i2c-sh_mobile.c
1647116508
16509+RENESAS R-CAR SATA DRIVER
16510+R: Sergey Shtylyov <s.shtylyov@omp.ru>
16511+S: Supported
16512+L: linux-ide@vger.kernel.org
16513+L: linux-renesas-soc@vger.kernel.org
16514+F: Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml
16515+F: drivers/ata/sata_rcar.c
16516+
1647216517 RENESAS R-CAR THERMAL DRIVERS
1647316518 M: Niklas Söderlund <niklas.soderlund@ragnatech.se>
1647416519 L: linux-renesas-soc@vger.kernel.org
@@ -16804,8 +16849,8 @@ F: drivers/video/fbdev/savage/ · 329 unmodified lines
1680416849 S390
1680516850 M: Heiko Carstens <hca@linux.ibm.com>
1680616851 M: Vasily Gorbik <gor@linux.ibm.com>
16807−M: Christian Borntraeger <borntraeger@linux.ibm.com>
16808−R: Alexander Gordeev <agordeev@linux.ibm.com>
16852+M: Alexander Gordeev <agordeev@linux.ibm.com>
16853+R: Christian Borntraeger <borntraeger@linux.ibm.com>
1680916854 R: Sven Schnelle <svens@linux.ibm.com>
1681016855 L: linux-s390@vger.kernel.org
1681116856 S: Supported
@@ -17076,6 +17121,7 @@ SAMSUNG SOC CLOCK DRIVERS · 264 unmodified lines
1707617121 M: Sylwester Nawrocki <s.nawrocki@samsung.com>
1707717122 M: Tomasz Figa <tomasz.figa@gmail.com>
1707817123 M: Chanwoo Choi <cw00.choi@samsung.com>
17124+R: Alim Akhtar <alim.akhtar@samsung.com>
1707917125 L: linux-samsung-soc@vger.kernel.org
1708017126 S: Supported
1708117127 T: git git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk.git
@@ -17712,6 +17758,21 @@ S: Maintained · 630 unmodified lines
1771217758 W: http://www.winischhofer.at/linuxsisusbvga.shtml
1771317759 F: drivers/usb/misc/sisusbvga/
1771417760
17761+SL28 CPLD MFD DRIVER
17762+M: Michael Walle <michael@walle.cc>
17763+S: Maintained
17764+F: Documentation/devicetree/bindings/gpio/kontron,sl28cpld-gpio.yaml
17765+F: Documentation/devicetree/bindings/hwmon/kontron,sl28cpld-hwmon.yaml
17766+F: Documentation/devicetree/bindings/interrupt-controller/kontron,sl28cpld-intc.yaml
17767+F: Documentation/devicetree/bindings/mfd/kontron,sl28cpld.yaml
17768+F: Documentation/devicetree/bindings/pwm/kontron,sl28cpld-pwm.yaml
17769+F: Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml
17770+F: drivers/gpio/gpio-sl28cpld.c
17771+F: drivers/hwmon/sl28cpld-hwmon.c
17772+F: drivers/irqchip/irq-sl28cpld.c
17773+F: drivers/pwm/pwm-sl28cpld.c
17774+F: drivers/watchdog/sl28cpld_wdt.c
17775+
1771517776 SLAB ALLOCATOR
1771617777 M: Christoph Lameter <cl@linux.com>
1771717778 M: Pekka Enberg <penberg@kernel.org>
@@ -18428,7 +18489,7 @@ F: Documentation/devicetree/bindings/sound/st,sti-asoc-card.txt · 710 unmodified lines
1842818489 F: sound/soc/sti/
1842918490
1843018491 STI CEC DRIVER
18431−M: Benjamin Gaignard <benjamin.gaignard@linaro.org>
18492+M: Alain Volmat <alain.volmat@foss.st.com>
1843218493 S: Maintained
1843318494 F: Documentation/devicetree/bindings/media/stih-cec.txt
1843418495 F: drivers/media/cec/platform/sti/
@@ -19582,6 +19643,14 @@ F: Documentation/trace/timerlat-tracer.rst · 1147 unmodified lines
1958219643 F: Documentation/trace/hwlat_detector.rst
1958319644 F: arch/*/kernel/trace.c
1958419645
19646+Real-time Linux Analysis (RTLA) tools
19647+M: Daniel Bristot de Oliveira <bristot@kernel.org>
19648+M: Steven Rostedt <rostedt@goodmis.org>
19649+L: linux-trace-devel@vger.kernel.org
19650+S: Maintained
19651+F: Documentation/tools/rtla/
19652+F: tools/tracing/rtla/
19653+
1958519654 TRADITIONAL CHINESE DOCUMENTATION
1958619655 M: Hu Haowen <src.res@email.cn>
1958719656 L: linux-doc-tw-discuss@lists.sourceforge.net
Makefile+2−2
@@ -2,8 +2,8 @@ · 1 unmodified line
22 VERSION = 5
33 PATCHLEVEL = 17
44 SUBLEVEL = 0
5−EXTRAVERSION = -rc2
6−NAME = Gobble Gobble
5+EXTRAVERSION = -rc4
6+NAME = Superb Owl
77
88 # *DOCUMENTATION*
99 # To see a list of typical targets execute "make help"
arch/arm/boot/dts/Makefile+1−0
@@ -806,6 +806,7 @@ dtb-$(CONFIG_ARCH_OMAP3) += \ · 805 unmodified lines
806806 logicpd-som-lv-37xx-devkit.dtb \
807807 omap3430-sdp.dtb \
808808 omap3-beagle.dtb \
809+ omap3-beagle-ab4.dtb \
809810 omap3-beagle-xm.dtb \
810811 omap3-beagle-xm-ab.dtb \
811812 omap3-cm-t3517.dtb \
arch/arm/boot/dts/am335x-wega.dtsi+1−1
@@ -55,7 +55,7 @@ · 54 unmodified lines
5555 2 1 0 0 /* # 0: INACTIVE, 1: TX, 2: RX */
5656 >;
5757 tx-num-evt = <16>;
58− rt-num-evt = <16>;
58+ rx-num-evt = <16>;
5959 status = "okay";
6060 };
6161
arch/arm/boot/dts/dra7.dtsi+10−10
@@ -160,7 +160,7 @@ · 159 unmodified lines
160160 target-module@48210000 {
161161 compatible = "ti,sysc-omap4-simple", "ti,sysc";
162162 power-domains = <&prm_mpu>;
163− clocks = <&mpu_clkctrl DRA7_MPU_CLKCTRL 0>;
163+ clocks = <&mpu_clkctrl DRA7_MPU_MPU_CLKCTRL 0>;
164164 clock-names = "fck";
165165 #address-cells = <1>;
166166 #size-cells = <1>;
@@ -875,10 +875,10 @@ · 708 unmodified lines
875875 <0x58000014 4>;
876876 reg-names = "rev", "syss";
877877 ti,syss-mask = <1>;
878− clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 0>,
879− <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>,
880− <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 10>,
881− <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 11>;
878+ clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 0>,
879+ <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>,
880+ <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>,
881+ <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 11>;
882882 clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
883883 #address-cells = <1>;
884884 #size-cells = <1>;
@@ -912,7 +912,7 @@ · 27 unmodified lines
912912 SYSC_OMAP2_SOFTRESET |
913913 SYSC_OMAP2_AUTOIDLE)>;
914914 ti,syss-mask = <1>;
915− clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>;
915+ clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>;
916916 clock-names = "fck";
917917 #address-cells = <1>;
918918 #size-cells = <1>;
@@ -939,8 +939,8 @@ · 20 unmodified lines
939939 <SYSC_IDLE_SMART>,
940940 <SYSC_IDLE_SMART_WKUP>;
941941 ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
942− clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>,
943− <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>;
942+ clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>,
943+ <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>;
944944 clock-names = "fck", "dss_clk";
945945 #address-cells = <1>;
946946 #size-cells = <1>;
@@ -979,7 +979,7 @@ · 32 unmodified lines
979979 compatible = "vivante,gc";
980980 reg = <0x0 0x700>;
981981 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
982− clocks = <&dss_clkctrl DRA7_BB2D_CLKCTRL 0>;
982+ clocks = <&dss_clkctrl DRA7_DSS_BB2D_CLKCTRL 0>;
983983 clock-names = "core";
984984 };
985985 };
@@ -1333,7 +1333,7 @@ · 347 unmodified lines
13331333 ti,no-reset-on-init;
13341334 ti,no-idle;
13351335 timer@0 {
1336− assigned-clocks = <&wkupaon_clkctrl DRA7_TIMER1_CLKCTRL 24>;
1336+ assigned-clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 24>;
13371337 assigned-clock-parents = <&sys_32k_ck>;
13381338 };
13391339 };
arch/arm/boot/dts/imx23-evk.dts+0−1
@@ -79,7 +79,6 @@ · 78 unmodified lines
7979 MX23_PAD_LCD_RESET__GPIO_1_18
8080 MX23_PAD_PWM3__GPIO_1_29
8181 MX23_PAD_PWM4__GPIO_1_30
82− MX23_PAD_SSP1_DETECT__SSP1_DETECT
8382 >;
8483 fsl,drive-strength = <MXS_DRIVE_4mA>;
8584 fsl,voltage = <MXS_VOLTAGE_HIGH>;
arch/arm/boot/dts/imx6qdl-udoo.dtsi+4−1
@@ -5,6 +5,8 @@ · 4 unmodified lines
55 * Author: Fabio Estevam <fabio.estevam@freescale.com>
66 */
77
8+#include <dt-bindings/gpio/gpio.h>
9+
810 / {
911 aliases {
1012 backlight = &backlight;
@@ -226,6 +228,7 @@ · 215 unmodified lines
226228 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
227229 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
228230 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
231+ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0
229232 >;
230233 };
231234
@@ -304,7 +307,7 @@ · 72 unmodified lines
304307 &usdhc3 {
305308 pinctrl-names = "default";
306309 pinctrl-0 = <&pinctrl_usdhc3>;
307− non-removable;
310+ cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
308311 status = "okay";
309312 };
310313
arch/arm/boot/dts/imx7ulp.dtsi+1−1
@@ -259,7 +259,7 @@ · 258 unmodified lines
259259 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
260260 clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
261261 assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
262− assigned-clocks-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
262+ assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
263263 timeout-sec = <40>;
264264 };
265265
arch/arm/boot/dts/meson.dtsi+4−4
@@ -59,7 +59,7 @@ · 58 unmodified lines
5959 };
6060
6161 uart_A: serial@84c0 {
62− compatible = "amlogic,meson6-uart", "amlogic,meson-uart";
62+ compatible = "amlogic,meson6-uart";
6363 reg = <0x84c0 0x18>;
6464 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
6565 fifo-size = <128>;
@@ -67,7 +67,7 @@ · 1 unmodified line
6767 };
6868
6969 uart_B: serial@84dc {
70− compatible = "amlogic,meson6-uart", "amlogic,meson-uart";
70+ compatible = "amlogic,meson6-uart";
7171 reg = <0x84dc 0x18>;
7272 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
7373 status = "disabled";
@@ -105,7 +105,7 @@ · 31 unmodified lines
105105 };
106106
107107 uart_C: serial@8700 {
108− compatible = "amlogic,meson6-uart", "amlogic,meson-uart";
108+ compatible = "amlogic,meson6-uart";
109109 reg = <0x8700 0x18>;
110110 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
111111 status = "disabled";
@@ -228,7 +228,7 @@ · 116 unmodified lines
228228 };
229229
230230 uart_AO: serial@4c0 {
231− compatible = "amlogic,meson6-uart", "amlogic,meson-ao-uart", "amlogic,meson-uart";
231+ compatible = "amlogic,meson6-uart", "amlogic,meson-ao-uart";
232232 reg = <0x4c0 0x18>;
233233 interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
234234 status = "disabled";
arch/arm/boot/dts/meson8.dtsi+12−12
@@ -736,27 +736,27 @@ · 735 unmodified lines
736736 };
737737
738738 &uart_AO {
739− compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
740− clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_CLK81>;
741− clock-names = "baud", "xtal", "pclk";
739+ compatible = "amlogic,meson8-uart", "amlogic,meson-ao-uart";
740+ clocks = <&xtal>, <&clkc CLKID_CLK81>, <&clkc CLKID_CLK81>;
741+ clock-names = "xtal", "pclk", "baud";
742742 };
743743
744744 &uart_A {
745− compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
746− clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART0>;
747− clock-names = "baud", "xtal", "pclk";
745+ compatible = "amlogic,meson8-uart";
746+ clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>;
747+ clock-names = "xtal", "pclk", "baud";
748748 };
749749
750750 &uart_B {
751− compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
752− clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART1>;
753− clock-names = "baud", "xtal", "pclk";
751+ compatible = "amlogic,meson8-uart";
752+ clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>;
753+ clock-names = "xtal", "pclk", "baud";
754754 };
755755
756756 &uart_C {
757− compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
758− clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART2>;
759− clock-names = "baud", "xtal", "pclk";
757+ compatible = "amlogic,meson8-uart";
758+ clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>;
759+ clock-names = "xtal", "pclk", "baud";
760760 };
761761
762762 &usb0 {
arch/arm/boot/dts/meson8b.dtsi+12−12
@@ -724,27 +724,27 @@ · 723 unmodified lines
724724 };
725725
726726 &uart_AO {
727− compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
728− clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_CLK81>;
729− clock-names = "baud", "xtal", "pclk";
727+ compatible = "amlogic,meson8b-uart", "amlogic,meson-ao-uart";
728+ clocks = <&xtal>, <&clkc CLKID_CLK81>, <&clkc CLKID_CLK81>;
729+ clock-names = "xtal", "pclk", "baud";
730730 };
731731
732732 &uart_A {
733− compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
734− clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART0>;
735− clock-names = "baud", "xtal", "pclk";
733+ compatible = "amlogic,meson8b-uart";
734+ clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>;
735+ clock-names = "xtal", "pclk", "baud";
736736 };
737737
738738 &uart_B {
739− compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
740− clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART1>;
741− clock-names = "baud", "xtal", "pclk";
739+ compatible = "amlogic,meson8b-uart";
740+ clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>;
741+ clock-names = "xtal", "pclk", "baud";
742742 };
743743
744744 &uart_C {
745− compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
746− clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART2>;
747− clock-names = "baud", "xtal", "pclk";
745+ compatible = "amlogic,meson8b-uart";
746+ clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>;
747+ clock-names = "xtal", "pclk", "baud";
748748 };
749749
750750 &usb0 {
arch/arm/boot/dts/omap3-beagle-ab4.dts+47−0
@@ -0,0 +1,47 @@
1+// SPDX-License-Identifier: GPL-2.0-only
2+/dts-v1/;
3+
4+#include "omap3-beagle.dts"
5+
6+/ {
7+ model = "TI OMAP3 BeagleBoard A to B4";
8+ compatible = "ti,omap3-beagle-ab4", "ti,omap3-beagle", "ti,omap3430", "ti,omap3";
9+};
10+
11+/*
12+ * Workaround for capacitor C70 issue, see "Boards revision A and < B5"
13+ * section at https://elinux.org/BeagleBoard_Community
14+ */
15+
16+/* Unusable as clocksource because of unreliable oscillator */
17+&counter32k {
18+ status = "disabled";
19+};
20+
21+/* Unusable as clockevent because of unreliable oscillator, allow to idle */
22+&timer1_target {
23+ /delete-property/ti,no-reset-on-init;
24+ /delete-property/ti,no-idle;
25+ timer@0 {
26+ /delete-property/ti,timer-alwon;
27+ };
28+};
29+
30+/* Preferred always-on timer for clocksource */
31+&timer12_target {
32+ ti,no-reset-on-init;
33+ ti,no-idle;
34+ timer@0 {
35+ /* Always clocked by secure_32k_fck */
36+ };
37+};
38+
39+/* Preferred timer for clockevent */
40+&timer2_target {
41+ ti,no-reset-on-init;
42+ ti,no-idle;
43+ timer@0 {
44+ assigned-clocks = <&gpt2_fck>;
45+ assigned-clock-parents = <&sys_ck>;
46+ };
47+};
arch/arm/boot/dts/omap3-beagle.dts+0−33
@@ -304,39 +304,6 @@ · 303 unmodified lines
304304 phys = <0 &hsusb2_phy>;
305305 };
306306
307−/* Unusable as clocksource because of unreliable oscillator */
308−&counter32k {
309− status = "disabled";
310−};
311−
312−/* Unusable as clockevent because if unreliable oscillator, allow to idle */
313−&timer1_target {
314− /delete-property/ti,no-reset-on-init;
315− /delete-property/ti,no-idle;
316− timer@0 {
317− /delete-property/ti,timer-alwon;
318− };
319−};
320−
321−/* Preferred always-on timer for clocksource */
322−&timer12_target {
323− ti,no-reset-on-init;
324− ti,no-idle;
325− timer@0 {
326− /* Always clocked by secure_32k_fck */
327− };
328−};
329−
330−/* Preferred timer for clockevent */
331−&timer2_target {
332− ti,no-reset-on-init;
333− ti,no-idle;
334− timer@0 {
335− assigned-clocks = <&gpt2_fck>;
336− assigned-clock-parents = <&sys_ck>;
337− };
338−};
339−
340307 &twl_gpio {
341308 ti,use-leds;
342309 /* pullups: BIT(1) */
arch/arm/boot/dts/spear320-hmi.dts+0−1
@@ -235,7 +235,6 @@ · 234 unmodified lines
235235 #address-cells = <1>;
236236 #size-cells = <0>;
237237 reg = <0x41>;
238− irq-over-gpio;
239238 irq-gpios = <&gpiopinctrl 29 0x4>;
240239 id = <0>;
241240 blocks = <0x5>;
arch/arm/boot/dts/ste-ux500-samsung-skomer.dts+0−4
@@ -185,10 +185,6 @@ · 184 unmodified lines
185185 cap-sd-highspeed;
186186 cap-mmc-highspeed;
187187 /* All direction control is used */
188− st,sig-dir-cmd;
189− st,sig-dir-dat0;
190− st,sig-dir-dat2;
191− st,sig-dir-dat31;
192188 st,sig-pin-fbclk;
193189 full-pwr-cycle;
194190 vmmc-supply = <&ab8500_ldo_aux3_reg>;
arch/arm/crypto/blake2s-shash.c+2−2
@@ -13,12 +13,12 @@ · 12 unmodified lines
1313 static int crypto_blake2s_update_arm(struct shash_desc *desc,
1414 const u8 *in, unsigned int inlen)
1515 {
16− return crypto_blake2s_update(desc, in, inlen, blake2s_compress);
16+ return crypto_blake2s_update(desc, in, inlen, false);
1717 }
1818
1919 static int crypto_blake2s_final_arm(struct shash_desc *desc, u8 *out)
2020 {
21− return crypto_blake2s_final(desc, out, blake2s_compress);
21+ return crypto_blake2s_final(desc, out, false);
2222 }
2323
2424 #define BLAKE2S_ALG(name, driver_name, digest_size) \
arch/arm/mach-omap2/display.c+1−1
@@ -263,9 +263,9 @@ static int __init omapdss_init_of(void) · 262 unmodified lines
263263 }
264264
265265 r = of_platform_populate(node, NULL, NULL, &pdev->dev);
266+ put_device(&pdev->dev);
266267 if (r) {
267268 pr_err("Unable to populate DSS submodule devices\n");
268− put_device(&pdev->dev);
269269 return r;
270270 }
271271
arch/arm/mach-omap2/omap_hwmod.c+3−1
@@ -752,8 +752,10 @@ static int __init _init_clkctrl_providers(void) · 751 unmodified lines
752752
753753 for_each_matching_node(np, ti_clkctrl_match_table) {
754754 ret = _setup_clkctrl_provider(np);
755− if (ret)
755+ if (ret) {
756+ of_node_put(np);
756757 break;
758+ }
757759 }
758760
759761 return ret;
arch/arm/mach-socfpga/Kconfig+2−0
@@ -2,6 +2,7 @@ · 1 unmodified line
22 menuconfig ARCH_INTEL_SOCFPGA
33 bool "Altera SOCFPGA family"
44 depends on ARCH_MULTI_V7
5+ select ARCH_HAS_RESET_CONTROLLER
56 select ARCH_SUPPORTS_BIG_ENDIAN
67 select ARM_AMBA
78 select ARM_GIC
@@ -18,6 +19,7 @@ menuconfig ARCH_INTEL_SOCFPGA · 10 unmodified lines
1819 select PL310_ERRATA_727915
1920 select PL310_ERRATA_753970 if PL310
2021 select PL310_ERRATA_769419
22+ select RESET_CONTROLLER
2123
2224 if ARCH_INTEL_SOCFPGA
2325 config SOCFPGA_SUSPEND
arch/arm64/Kconfig+17−0
@@ -672,6 +672,7 @@ config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE · 671 unmodified lines
672672
673673 config ARM64_ERRATUM_2051678
674674 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"
675+ default y
675676 help
676677 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
677678 Affected Coretex-A510 might not respect the ordering rules for
@@ -680,6 +681,22 @@ config ARM64_ERRATUM_2051678 · 2 unmodified lines
680681
681682 If unsure, say Y.
682683
684+config ARM64_ERRATUM_2077057
685+ bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"
686+ help
687+ This option adds the workaround for ARM Cortex-A510 erratum 2077057.
688+ Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is
689+ expected, but a Pointer Authentication trap is taken instead. The
690+ erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow
691+ EL1 to cause a return to EL2 with a guest controlled ELR_EL2.
692+
693+ This can only happen when EL2 is stepping EL1.
694+
695+ When these conditions occur, the SPSR_EL2 value is unchanged from the
696+ previous guest entry, and can be restored from the in-memory copy.
697+
698+ If unsure, say Y.
699+
683700 config ARM64_ERRATUM_2119858
684701 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
685702 default y
arch/arm64/Kconfig.platforms+0−3
@@ -309,9 +309,6 @@ config ARCH_VISCONTI · 308 unmodified lines
309309 help
310310 This enables support for Toshiba Visconti SoCs Family.
311311
312−config ARCH_VULCAN
313− def_bool n
314−
315312 config ARCH_XGENE
316313 bool "AppliedMicro X-Gene SOC Family"
317314 help
arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi+6−0
@@ -107,6 +107,12 @@ · 106 unmodified lines
107107 no-map;
108108 };
109109
110+ /* 32 MiB reserved for ARM Trusted Firmware (BL32) */
111+ secmon_reserved_bl32: secmon@5300000 {
112+ reg = <0x0 0x05300000 0x0 0x2000000>;
113+ no-map;
114+ };
115+
110116 linux,cma {
111117 compatible = "shared-dma-pool";
112118 reusable;
arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts+0−8
@@ -157,14 +157,6 @@ · 156 unmodified lines
157157 regulator-always-on;
158158 };
159159
160− reserved-memory {
161− /* TEE Reserved Memory */
162− bl32_reserved: bl32@5000000 {
163− reg = <0x0 0x05300000 0x0 0x2000000>;
164− no-map;
165− };
166− };
167−
168160 sdio_pwrseq: sdio-pwrseq {
169161 compatible = "mmc-pwrseq-simple";
170162 reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi+2−2
@@ -17,7 +17,7 @@ · 16 unmodified lines
1717 rtc1 = &vrtc;
1818 };
1919
20− dioo2133: audio-amplifier-0 {
20+ dio2133: audio-amplifier-0 {
2121 compatible = "simple-audio-amplifier";
2222 enable-gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>;
2323 VCC-supply = <&vcc_5v>;
@@ -219,7 +219,7 @@ · 195 unmodified lines
219219 audio-widgets = "Line", "Lineout";
220220 audio-aux-devs = <&tdmout_b>, <&tdmout_c>, <&tdmin_a>,
221221 <&tdmin_b>, <&tdmin_c>, <&tdmin_lb>,
222− <&dioo2133>;
222+ <&dio2133>;
223223 audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
224224 "TDMOUT_B IN 1", "FRDDR_B OUT 1",
225225 "TDMOUT_B IN 2", "FRDDR_C OUT 1",
arch/arm64/boot/dts/amlogic/meson-gx.dtsi+6−0
@@ -49,6 +49,12 @@ · 48 unmodified lines
4949 no-map;
5050 };
5151
52+ /* 32 MiB reserved for ARM Trusted Firmware (BL32) */
53+ secmon_reserved_bl32: secmon@5300000 {
54+ reg = <0x0 0x05300000 0x0 0x2000000>;
55+ no-map;
56+ };
57+
5258 linux,cma {
5359 compatible = "shared-dma-pool";
5460 reusable;
arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m5.dts+1−1
@@ -123,7 +123,7 @@ · 122 unmodified lines
123123 regulator-min-microvolt = <1800000>;
124124 regulator-max-microvolt = <3300000>;
125125
126− enable-gpio = <&gpio GPIOE_2 GPIO_ACTIVE_HIGH>;
126+ enable-gpio = <&gpio_ao GPIOE_2 GPIO_ACTIVE_HIGH>;
127127 enable-active-high;
128128 regulator-always-on;
129129
arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi+1−1
@@ -48,7 +48,7 @@ · 47 unmodified lines
4848 regulator-max-microvolt = <3300000>;
4949 vin-supply = <&vcc_5v>;
5050
51− enable-gpio = <&gpio GPIOE_2 GPIO_ACTIVE_HIGH>;
51+ enable-gpio = <&gpio_ao GPIOE_2 GPIO_OPEN_DRAIN>;
5252 enable-active-high;
5353 regulator-always-on;
5454
arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts+0−8
@@ -203,14 +203,6 @@ · 202 unmodified lines
203203 regulator-always-on;
204204 };
205205
206− reserved-memory {
207− /* TEE Reserved Memory */
208− bl32_reserved: bl32@5000000 {
209− reg = <0x0 0x05300000 0x0 0x2000000>;
210− no-map;
211− };
212− };
213−
214206 sdio_pwrseq: sdio-pwrseq {
215207 compatible = "mmc-pwrseq-simple";
216208 reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts+4−0
@@ -157,6 +157,10 @@ · 156 unmodified lines
157157 };
158158 };
159159
160+&ftm_alarm0 {
161+ status = "okay";
162+};
163+
160164 &gpio1 {
161165 gpio-line-names =
162166 "", "", "", "", "", "", "", "",
arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi+2−2
@@ -1115,8 +1115,8 @@ · 1114 unmodified lines
11151115 status = "okay";
11161116
11171117 ports {
1118− port@1 {
1119− reg = <1>;
1118+ port@0 {
1119+ reg = <0>;
11201120
11211121 mipi1_sensor_ep: endpoint {
11221122 remote-endpoint = <&camera1_ep>;
arch/arm64/boot/dts/freescale/imx8mq.dtsi+5−5
@@ -554,7 +554,7 @@ · 553 unmodified lines
554554 assigned-clock-rates = <0>, <0>, <0>, <594000000>;
555555 status = "disabled";
556556
557− port@0 {
557+ port {
558558 lcdif_mipi_dsi: endpoint {
559559 remote-endpoint = <&mipi_dsi_lcdif_in>;
560560 };
@@ -1151,8 +1151,8 @@ · 590 unmodified lines
11511151 #address-cells = <1>;
11521152 #size-cells = <0>;
11531153
1154− port@0 {
1155− reg = <0>;
1154+ port@1 {
1155+ reg = <1>;
11561156
11571157 csi1_mipi_ep: endpoint {
11581158 remote-endpoint = <&csi1_ep>;
@@ -1203,8 +1203,8 @@ · 44 unmodified lines
12031203 #address-cells = <1>;
12041204 #size-cells = <0>;
12051205
1206− port@0 {
1207− reg = <0>;
1206+ port@1 {
1207+ reg = <1>;
12081208
12091209 csi2_mipi_ep: endpoint {
12101210 remote-endpoint = <&csi2_ep>;
arch/arm64/boot/dts/freescale/mba8mx.dtsi+1−1
@@ -91,7 +91,7 @@ · 90 unmodified lines
9191
9292 sound {
9393 compatible = "fsl,imx-audio-tlv320aic32x4";
94− model = "tqm-tlv320aic32";
94+ model = "imx-audio-tlv320aic32x4";
9595 ssi-controller = <&sai3>;
9696 audio-codec = <&tlv320aic3x04>;
9797 };
arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts+12−2
@@ -15,8 +15,18 @@ · 14 unmodified lines
1515 model = "Texas Instruments J721S2 EVM";
1616
1717 chosen {
18− stdout-path = "serial10:115200n8";
19− bootargs = "console=ttyS10,115200n8 earlycon=ns16550a,mmio32,2880000";
18+ stdout-path = "serial2:115200n8";
19+ bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,2880000";
20+ };
21+
22+ aliases {
23+ serial1 = &mcu_uart0;
24+ serial2 = &main_uart8;
25+ mmc0 = &main_sdhci0;
26+ mmc1 = &main_sdhci1;
27+ can0 = &main_mcan16;
28+ can1 = &mcu_mcan0;
29+ can2 = &mcu_mcan1;
2030 };
2131
2232 evm_12v0: fixedregulator-evm12v0 {
arch/arm64/boot/dts/ti/k3-j721s2.dtsi+0−22
@@ -21,28 +21,6 @@ · 20 unmodified lines
2121 #address-cells = <2>;
2222 #size-cells = <2>;
2323
24− aliases {
25− serial0 = &wkup_uart0;
26− serial1 = &mcu_uart0;
27− serial2 = &main_uart0;
28− serial3 = &main_uart1;
29− serial4 = &main_uart2;
30− serial5 = &main_uart3;
31− serial6 = &main_uart4;
32− serial7 = &main_uart5;
33− serial8 = &main_uart6;
34− serial9 = &main_uart7;
35− serial10 = &main_uart8;
36− serial11 = &main_uart9;
37− mmc0 = &main_sdhci0;
38− mmc1 = &main_sdhci1;
39− can0 = &main_mcan16;
40− can1 = &mcu_mcan0;
41− can2 = &mcu_mcan1;
42− can3 = &main_mcan3;
43− can4 = &main_mcan5;
44− };
45−
4624 chosen { };
4725
4826 cpus {
arch/arm64/kernel/cpu_errata.c+8−0
@@ -600,6 +600,14 @@ const struct arm64_cpu_capabilities arm64_errata[] = { · 599 unmodified lines
600600 CAP_MIDR_RANGE_LIST(trbe_write_out_of_range_cpus),
601601 },
602602 #endif
603+#ifdef CONFIG_ARM64_ERRATUM_2077057
604+ {
605+ .desc = "ARM erratum 2077057",
606+ .capability = ARM64_WORKAROUND_2077057,
607+ .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
608+ ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2),
609+ },
610+#endif
603611 #ifdef CONFIG_ARM64_ERRATUM_2064142
604612 {
605613 .desc = "ARM erratum 2064142",
arch/arm64/kvm/arm.c+33−18
@@ -797,6 +797,24 @@ static bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu, int *ret) · 796 unmodified lines
797797 xfer_to_guest_mode_work_pending();
798798 }
799799
800+/*
801+ * Actually run the vCPU, entering an RCU extended quiescent state (EQS) while
802+ * the vCPU is running.
803+ *
804+ * This must be noinstr as instrumentation may make use of RCU, and this is not
805+ * safe during the EQS.
806+ */
807+static int noinstr kvm_arm_vcpu_enter_exit(struct kvm_vcpu *vcpu)
808+{
809+ int ret;
810+
811+ guest_state_enter_irqoff();
812+ ret = kvm_call_hyp_ret(__kvm_vcpu_run, vcpu);
813+ guest_state_exit_irqoff();
814+
815+ return ret;
816+}
817+
800818 /**
801819 * kvm_arch_vcpu_ioctl_run - the main VCPU run function to execute guest code
802820 * @vcpu: The VCPU pointer
@@ -881,9 +899,9 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) · 78 unmodified lines
881899 * Enter the guest
882900 */
883901 trace_kvm_entry(*vcpu_pc(vcpu));
884− guest_enter_irqoff();
902+ guest_timing_enter_irqoff();
885903
886− ret = kvm_call_hyp_ret(__kvm_vcpu_run, vcpu);
904+ ret = kvm_arm_vcpu_enter_exit(vcpu);
887905
888906 vcpu->mode = OUTSIDE_GUEST_MODE;
889907 vcpu->stat.exits++;
@@ -918,26 +936,23 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) · 28 unmodified lines
918936 kvm_arch_vcpu_ctxsync_fp(vcpu);
919937
920938 /*
921− * We may have taken a host interrupt in HYP mode (ie
922− * while executing the guest). This interrupt is still
923− * pending, as we haven't serviced it yet!
939+ * We must ensure that any pending interrupts are taken before
940+ * we exit guest timing so that timer ticks are accounted as
941+ * guest time. Transiently unmask interrupts so that any
942+ * pending interrupts are taken.
924943 *
925− * We're now back in SVC mode, with interrupts
926− * disabled. Enabling the interrupts now will have
927− * the effect of taking the interrupt again, in SVC
928− * mode this time.
944+ * Per ARM DDI 0487G.b section D1.13.4, an ISB (or other
945+ * context synchronization event) is necessary to ensure that
946+ * pending interrupts are taken.
929947 */
930948 local_irq_enable();
949+ isb();
950+ local_irq_disable();
951+
952+ guest_timing_exit_irqoff();
953+
954+ local_irq_enable();
931955
932− /*
933− * We do local_irq_enable() before calling guest_exit() so
934− * that if a timer interrupt hits while running the guest we
935− * account that tick as being spent in the guest. We enable
936− * preemption after calling guest_exit() so that if we get
937− * preempted we make sure ticks after that is not counted as
938− * guest time.
939− */
940− guest_exit();
941956 trace_kvm_exit(ret, kvm_vcpu_trap_get_class(vcpu), *vcpu_pc(vcpu));
942957
943958 /* Exit types that need handling before we can be preempted */
arch/arm64/kvm/handle_exit.c+8−0
@@ -228,6 +228,14 @@ int handle_exit(struct kvm_vcpu *vcpu, int exception_index) · 227 unmodified lines
228228 {
229229 struct kvm_run *run = vcpu->run;
230230
231+ if (ARM_SERROR_PENDING(exception_index)) {
232+ /*
233+ * The SError is handled by handle_exit_early(). If the guest
234+ * survives it will re-execute the original instruction.
235+ */
236+ return 1;
237+ }
238+
231239 exception_index = ARM_EXCEPTION_CODE(exception_index);
232240
233241 switch (exception_index) {
arch/arm64/kvm/hyp/include/hyp/switch.h+21−2
@@ -402,6 +402,24 @@ static inline bool kvm_hyp_handle_exit(struct kvm_vcpu *vcpu, u64 *exit_code) · 401 unmodified lines
402402 return false;
403403 }
404404
405+static inline void synchronize_vcpu_pstate(struct kvm_vcpu *vcpu, u64 *exit_code)
406+{
407+ /*
408+ * Check for the conditions of Cortex-A510's #2077057. When these occur
409+ * SPSR_EL2 can't be trusted, but isn't needed either as it is
410+ * unchanged from the value in vcpu_gp_regs(vcpu)->pstate.
411+ * Are we single-stepping the guest, and took a PAC exception from the
412+ * active-not-pending state?
413+ */
414+ if (cpus_have_final_cap(ARM64_WORKAROUND_2077057) &&
415+ vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
416+ *vcpu_cpsr(vcpu) & DBG_SPSR_SS &&
417+ ESR_ELx_EC(read_sysreg_el2(SYS_ESR)) == ESR_ELx_EC_PAC)
418+ write_sysreg_el2(*vcpu_cpsr(vcpu), SYS_SPSR);
419+
420+ vcpu->arch.ctxt.regs.pstate = read_sysreg_el2(SYS_SPSR);
421+}
422+
405423 /*
406424 * Return true when we were able to fixup the guest exit and should return to
407425 * the guest, false when we should restore the host state and return to the
@@ -413,7 +431,7 @@ static inline bool fixup_guest_exit(struct kvm_vcpu *vcpu, u64 *exit_code) · 5 unmodified lines
413431 * Save PSTATE early so that we can evaluate the vcpu mode
414432 * early on.
415433 */
416− vcpu->arch.ctxt.regs.pstate = read_sysreg_el2(SYS_SPSR);
434+ synchronize_vcpu_pstate(vcpu, exit_code);
417435
418436 /*
419437 * Check whether we want to repaint the state one way or
@@ -424,7 +442,8 @@ static inline bool fixup_guest_exit(struct kvm_vcpu *vcpu, u64 *exit_code) · 4 unmodified lines
424442 if (ARM_EXCEPTION_CODE(*exit_code) != ARM_EXCEPTION_IRQ)
425443 vcpu->arch.fault.esr_el2 = read_sysreg_el2(SYS_ESR);
426444
427− if (ARM_SERROR_PENDING(*exit_code)) {
445+ if (ARM_SERROR_PENDING(*exit_code) &&
446+ ARM_EXCEPTION_CODE(*exit_code) != ARM_EXCEPTION_IRQ) {
428447 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu);
429448
430449 /*
arch/arm64/tools/cpucaps+3−2
@@ -55,9 +55,10 @@ WORKAROUND_1418040 · 54 unmodified lines
5555 WORKAROUND_1463225
5656 WORKAROUND_1508412
5757 WORKAROUND_1542419
58−WORKAROUND_2064142
59−WORKAROUND_2038923
6058 WORKAROUND_1902691
59+WORKAROUND_2038923
60+WORKAROUND_2064142
61+WORKAROUND_2077057
6162 WORKAROUND_TRBE_OVERWRITE_FILL_MODE
6263 WORKAROUND_TSB_FLUSH_FAILURE
6364 WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
arch/mips/boot/dts/ingenic/ci20.dts+2−13
@@ -83,6 +83,8 @@ · 82 unmodified lines
8383 label = "HDMI OUT";
8484 type = "a";
8585
86+ ddc-en-gpios = <&gpa 25 GPIO_ACTIVE_HIGH>;
87+
8688 port {
8789 hdmi_con: endpoint {
8890 remote-endpoint = <&dw_hdmi_out>;
@@ -114,17 +116,6 @@ · 25 unmodified lines
114116 gpio = <&gpf 14 GPIO_ACTIVE_LOW>;
115117 enable-active-high;
116118 };
117−
118− hdmi_power: fixedregulator@3 {
119− compatible = "regulator-fixed";
120−
121− regulator-name = "hdmi_power";
122− regulator-min-microvolt = <5000000>;
123− regulator-max-microvolt = <5000000>;
124−
125− gpio = <&gpa 25 0>;
126− enable-active-high;
127− };
128119 };
129120
130121 &ext {
@@ -576,8 +567,6 @@ · 445 unmodified lines
576567 pinctrl-names = "default";
577568 pinctrl-0 = <&pins_hdmi_ddc>;
578569
579− hdmi-5v-supply = <&hdmi_power>;
580−
581570 ports {
582571 #address-cells = <1>;
583572 #size-cells = <0>;
arch/mips/cavium-octeon/octeon-memcpy.S+1−1
@@ -74,7 +74,7 @@ · 73 unmodified lines
7474 #define EXC(inst_reg,addr,handler) \
7575 9: inst_reg, addr; \
7676 .section __ex_table,"a"; \
77− PTR 9b, handler; \
77+ PTR_WD 9b, handler; \
7878 .previous
7979
8080 /*
arch/mips/kvm/mips.c+46−4
@@ -414,6 +414,24 @@ int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, · 413 unmodified lines
414414 return -ENOIOCTLCMD;
415415 }
416416
417+/*
418+ * Actually run the vCPU, entering an RCU extended quiescent state (EQS) while
419+ * the vCPU is running.
420+ *
421+ * This must be noinstr as instrumentation may make use of RCU, and this is not
422+ * safe during the EQS.
423+ */
424+static int noinstr kvm_mips_vcpu_enter_exit(struct kvm_vcpu *vcpu)
425+{
426+ int ret;
427+
428+ guest_state_enter_irqoff();
429+ ret = kvm_mips_callbacks->vcpu_run(vcpu);
430+ guest_state_exit_irqoff();
431+
432+ return ret;
433+}
434+
417435 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
418436 {
419437 int r = -EINTR;
@@ -434,7 +452,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) · 14 unmodified lines
434452 lose_fpu(1);
435453
436454 local_irq_disable();
437− guest_enter_irqoff();
455+ guest_timing_enter_irqoff();
438456 trace_kvm_enter(vcpu);
439457
440458 /*
@@ -445,10 +463,23 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) · 4 unmodified lines
445463 */
446464 smp_store_mb(vcpu->mode, IN_GUEST_MODE);
447465
448− r = kvm_mips_callbacks->vcpu_run(vcpu);
466+ r = kvm_mips_vcpu_enter_exit(vcpu);
467+
468+ /*
469+ * We must ensure that any pending interrupts are taken before
470+ * we exit guest timing so that timer ticks are accounted as
471+ * guest time. Transiently unmask interrupts so that any
472+ * pending interrupts are taken.
473+ *
474+ * TODO: is there a barrier which ensures that pending interrupts are
475+ * recognised? Currently this just hopes that the CPU takes any pending
476+ * interrupts between the enable and disable.
477+ */
478+ local_irq_enable();
479+ local_irq_disable();
449480
450481 trace_kvm_out(vcpu);
451− guest_exit_irqoff();
482+ guest_timing_exit_irqoff();
452483 local_irq_enable();
453484
454485 out:
@@ -1168,7 +1199,7 @@ static void kvm_mips_set_c0_status(void) · 713 unmodified lines
11681199 /*
11691200 * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
11701201 */
1171−int kvm_mips_handle_exit(struct kvm_vcpu *vcpu)
1202+static int __kvm_mips_handle_exit(struct kvm_vcpu *vcpu)
11721203 {
11731204 struct kvm_run *run = vcpu->run;
11741205 u32 cause = vcpu->arch.host_cp0_cause;
@@ -1357,6 +1388,17 @@ int kvm_mips_handle_exit(struct kvm_vcpu *vcpu) · 182 unmodified lines
13571388 return ret;
13581389 }
13591390
1391+int noinstr kvm_mips_handle_exit(struct kvm_vcpu *vcpu)
1392+{
1393+ int ret;
1394+
1395+ guest_state_exit_irqoff();
1396+ ret = __kvm_mips_handle_exit(vcpu);
1397+ guest_state_enter_irqoff();
1398+
1399+ return ret;
1400+}
1401+
13601402 /* Enable FPU for guest and restore context */
13611403 void kvm_own_fpu(struct kvm_vcpu *vcpu)
13621404 {
arch/mips/kvm/vz.c+9−3
@@ -458,8 +458,8 @@ void kvm_vz_acquire_htimer(struct kvm_vcpu *vcpu) · 457 unmodified lines
458458 /**
459459 * _kvm_vz_save_htimer() - Switch to software emulation of guest timer.
460460 * @vcpu: Virtual CPU.
461− * @compare: Pointer to write compare value to.
462− * @cause: Pointer to write cause value to.
461+ * @out_compare: Pointer to write compare value to.
462+ * @out_cause: Pointer to write cause value to.
463463 *
464464 * Save VZ guest timer state and switch to software emulation of guest CP0
465465 * timer. The hard timer must already be in use, so preemption should be
@@ -1541,11 +1541,14 @@ static int kvm_trap_vz_handle_guest_exit(struct kvm_vcpu *vcpu) · 1075 unmodified lines
15411541 }
15421542
15431543 /**
1544− * kvm_trap_vz_handle_cop_unusuable() - Guest used unusable coprocessor.
1544+ * kvm_trap_vz_handle_cop_unusable() - Guest used unusable coprocessor.
15451545 * @vcpu: Virtual CPU context.
15461546 *
15471547 * Handle when the guest attempts to use a coprocessor which hasn't been allowed
15481548 * by the root context.
1549+ *
1550+ * Return: value indicating whether to resume the host or the guest
1551+ * (RESUME_HOST or RESUME_GUEST)
15491552 */
15501553 static int kvm_trap_vz_handle_cop_unusable(struct kvm_vcpu *vcpu)
15511554 {
@@ -1592,6 +1595,9 @@ static int kvm_trap_vz_handle_cop_unusable(struct kvm_vcpu *vcpu) · 40 unmodified lines
15921595 *
15931596 * Handle when the guest attempts to use MSA when it is disabled in the root
15941597 * context.
1598+ *
1599+ * Return: value indicating whether to resume the host or the guest
1600+ * (RESUME_HOST or RESUME_GUEST)
15951601 */
15961602 static int kvm_trap_vz_handle_msa_disabled(struct kvm_vcpu *vcpu)
15971603 {
arch/riscv/Makefile+6−0
@@ -50,6 +50,12 @@ riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima · 49 unmodified lines
5050 riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima
5151 riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd
5252 riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c
53+
54+# Newer binutils versions default to ISA spec version 20191213 which moves some
55+# instructions from the I extension to the Zicsr and Zifencei extensions.
56+toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei)
57+riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei
58+
5359 KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y))
5460 KBUILD_AFLAGS += -march=$(riscv-march-y)
5561
arch/riscv/kernel/cpu-hotplug.c+2−0
@@ -12,6 +12,7 @@ · 11 unmodified lines
1212 #include <linux/sched/hotplug.h>
1313 #include <asm/irq.h>
1414 #include <asm/cpu_ops.h>
15+#include <asm/numa.h>
1516 #include <asm/sbi.h>
1617
1718 bool cpu_has_hotplug(unsigned int cpu)
@@ -40,6 +41,7 @@ int __cpu_disable(void) · 22 unmodified lines
4041 return ret;
4142
4243 remove_cpu_topology(cpu);
44+ numa_remove_cpu(cpu);
4345 set_cpu_online(cpu, false);
4446 irq_migrate_all_off_this_cpu();
4547
arch/riscv/kernel/head.S+5−6
@@ -22,14 +22,13 @@ · 21 unmodified lines
2222 add \reg, \reg, t0
2323 .endm
2424 .macro XIP_FIXUP_FLASH_OFFSET reg
25− la t1, __data_loc
26− li t0, XIP_OFFSET_MASK
27− and t1, t1, t0
28− li t1, XIP_OFFSET
29− sub t0, t0, t1
30− sub \reg, \reg, t0
25+ la t0, __data_loc
26+ REG_L t1, _xip_phys_offset
27+ sub \reg, \reg, t1
28+ add \reg, \reg, t0
3129 .endm
3230 _xip_fixup: .dword CONFIG_PHYS_RAM_BASE - CONFIG_XIP_PHYS_ADDR - XIP_OFFSET
31+_xip_phys_offset: .dword CONFIG_XIP_PHYS_ADDR + XIP_OFFSET
3332 #else
3433 .macro XIP_FIXUP_OFFSET reg
3534 .endm
arch/riscv/kernel/stacktrace.c+5−4
@@ -22,15 +22,16 @@ void notrace walk_stackframe(struct task_struct *task, struct pt_regs *regs, · 21 unmodified lines
2222 bool (*fn)(void *, unsigned long), void *arg)
2323 {
2424 unsigned long fp, sp, pc;
25+ int level = 0;
2526
2627 if (regs) {
2728 fp = frame_pointer(regs);
2829 sp = user_stack_pointer(regs);
2930 pc = instruction_pointer(regs);
3031 } else if (task == NULL || task == current) {
31− fp = (unsigned long)__builtin_frame_address(1);
32− sp = (unsigned long)__builtin_frame_address(0);
33− pc = (unsigned long)__builtin_return_address(0);
32+ fp = (unsigned long)__builtin_frame_address(0);
33+ sp = sp_in_global;
34+ pc = (unsigned long)walk_stackframe;
3435 } else {
3536 /* task blocked in __switch_to */
3637 fp = task->thread.s[0];
@@ -42,7 +43,7 @@ void notrace walk_stackframe(struct task_struct *task, struct pt_regs *regs, · 5 unmodified lines
4243 unsigned long low, high;
4344 struct stackframe *frame;
4445
45− if (unlikely(!__kernel_text_address(pc) || !fn(arg, pc)))
46+ if (unlikely(!__kernel_text_address(pc) || (level++ >= 1 && !fn(arg, pc))))
4647 break;
4748
4849 /* Validate frame pointer */
arch/riscv/kvm/vcpu.c+31−17
@@ -90,6 +90,7 @@ int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) · 89 unmodified lines
9090 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
9191 {
9292 struct kvm_cpu_context *cntx;
93+ struct kvm_vcpu_csr *reset_csr = &vcpu->arch.guest_reset_csr;
9394
9495 /* Mark this VCPU never ran */
9596 vcpu->arch.ran_atleast_once = false;
@@ -106,6 +107,9 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) · 10 unmodified lines
106107 cntx->hstatus |= HSTATUS_SPVP;
107108 cntx->hstatus |= HSTATUS_SPV;
108109
110+ /* By default, make CY, TM, and IR counters accessible in VU mode */
111+ reset_csr->scounteren = 0x7;
112+
109113 /* Setup VCPU timer */
110114 kvm_riscv_vcpu_timer_init(vcpu);
111115
@@ -699,6 +703,20 @@ static void kvm_riscv_update_hvip(struct kvm_vcpu *vcpu) · 587 unmodified lines
699703 csr_write(CSR_HVIP, csr->hvip);
700704 }
701705
706+/*
707+ * Actually run the vCPU, entering an RCU extended quiescent state (EQS) while
708+ * the vCPU is running.
709+ *
710+ * This must be noinstr as instrumentation may make use of RCU, and this is not
711+ * safe during the EQS.
712+ */
713+static void noinstr kvm_riscv_vcpu_enter_exit(struct kvm_vcpu *vcpu)
714+{
715+ guest_state_enter_irqoff();
716+ __kvm_riscv_switch_to(&vcpu->arch);
717+ guest_state_exit_irqoff();
718+}
719+
702720 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
703721 {
704722 int ret;
@@ -790,9 +808,9 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) · 85 unmodified lines
790808 continue;
791809 }
792810
793− guest_enter_irqoff();
811+ guest_timing_enter_irqoff();
794812
795− __kvm_riscv_switch_to(&vcpu->arch);
813+ kvm_riscv_vcpu_enter_exit(vcpu);
796814
797815 vcpu->mode = OUTSIDE_GUEST_MODE;
798816 vcpu->stat.exits++;
@@ -812,25 +830,21 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) · 13 unmodified lines
812830 kvm_riscv_vcpu_sync_interrupts(vcpu);
813831
814832 /*
815− * We may have taken a host interrupt in VS/VU-mode (i.e.
816− * while executing the guest). This interrupt is still
817− * pending, as we haven't serviced it yet!
833+ * We must ensure that any pending interrupts are taken before
834+ * we exit guest timing so that timer ticks are accounted as
835+ * guest time. Transiently unmask interrupts so that any
836+ * pending interrupts are taken.
818837 *
819− * We're now back in HS-mode with interrupts disabled
820− * so enabling the interrupts now will have the effect
821− * of taking the interrupt again, in HS-mode this time.
838+ * There's no barrier which ensures that pending interrupts are
839+ * recognised, so we just hope that the CPU takes any pending
840+ * interrupts between the enable and disable.
822841 */
823842 local_irq_enable();
843+ local_irq_disable();
824844
825− /*
826− * We do local_irq_enable() before calling guest_exit() so
827− * that if a timer interrupt hits while running the guest
828− * we account that tick as being spent in the guest. We
829− * enable preemption after calling guest_exit() so that if
830− * we get preempted we make sure ticks after that is not
831− * counted as guest time.
832− */
833− guest_exit();
845+ guest_timing_exit_irqoff();
846+
847+ local_irq_enable();
834848
835849 preempt_enable();
836850
arch/riscv/kvm/vcpu_sbi_base.c+2−1
@@ -9,6 +9,7 @@ · 8 unmodified lines
99 #include <linux/errno.h>
1010 #include <linux/err.h>
1111 #include <linux/kvm_host.h>
12+#include <linux/version.h>
1213 #include <asm/csr.h>
1314 #include <asm/sbi.h>
1415 #include <asm/kvm_vcpu_timer.h>
@@ -32,7 +33,7 @@ static int kvm_sbi_ext_base_handler(struct kvm_vcpu *vcpu, struct kvm_run *run, · 17 unmodified lines
3233 *out_val = KVM_SBI_IMPID;
3334 break;
3435 case SBI_EXT_BASE_GET_IMP_VERSION:
35− *out_val = 0;
36+ *out_val = LINUX_VERSION_CODE;
3637 break;
3738 case SBI_EXT_BASE_PROBE_EXT:
3839 if ((cp->a0 >= SBI_EXT_EXPERIMENTAL_START &&
arch/riscv/mm/extable.c+3−3
@@ -33,7 +33,7 @@ static inline void regs_set_gpr(struct pt_regs *regs, unsigned int offset, · 32 unmodified lines
3333 if (unlikely(offset > MAX_REG_OFFSET))
3434 return;
3535
36− if (!offset)
36+ if (offset)
3737 *(unsigned long *)((unsigned long)regs + offset) = val;
3838 }
3939
@@ -43,8 +43,8 @@ static bool ex_handler_uaccess_err_zero(const struct exception_table_entry *ex, · 3 unmodified lines
4343 int reg_err = FIELD_GET(EX_DATA_REG_ERR, ex->data);
4444 int reg_zero = FIELD_GET(EX_DATA_REG_ZERO, ex->data);
4545
46− regs_set_gpr(regs, reg_err, -EFAULT);
47− regs_set_gpr(regs, reg_zero, 0);
46+ regs_set_gpr(regs, reg_err * sizeof(unsigned long), -EFAULT);
47+ regs_set_gpr(regs, reg_zero * sizeof(unsigned long), 0);
4848
4949 regs->epc = get_ex_fixup(ex);
5050 return true;
arch/riscv/mm/init.c+2−0
@@ -232,6 +232,7 @@ static pmd_t __maybe_unused early_dtb_pmd[PTRS_PER_PMD] __initdata __aligned(PAG · 231 unmodified lines
232232
233233 #ifdef CONFIG_XIP_KERNEL
234234 #define pt_ops (*(struct pt_alloc_ops *)XIP_FIXUP(&pt_ops))
235+#define riscv_pfn_base (*(unsigned long *)XIP_FIXUP(&riscv_pfn_base))
235236 #define trampoline_pg_dir ((pgd_t *)XIP_FIXUP(trampoline_pg_dir))
236237 #define fixmap_pte ((pte_t *)XIP_FIXUP(fixmap_pte))
237238 #define early_pg_dir ((pgd_t *)XIP_FIXUP(early_pg_dir))
@@ -522,6 +523,7 @@ static uintptr_t __init best_map_size(phys_addr_t base, phys_addr_t size) · 284 unmodified lines
522523 }
523524
524525 #ifdef CONFIG_XIP_KERNEL
526+#define phys_ram_base (*(phys_addr_t *)XIP_FIXUP(&phys_ram_base))
525527 extern char _xiprom[], _exiprom[], __data_loc;
526528
527529 /* called from head.S with MMU off */
arch/s390/kvm/kvm-s390.c+2−0
@@ -4667,6 +4667,8 @@ static long kvm_s390_guest_sida_op(struct kvm_vcpu *vcpu, · 4666 unmodified lines
46674667 return -EINVAL;
46684668 if (mop->size + mop->sida_offset > sida_size(vcpu->arch.sie_block))
46694669 return -E2BIG;
4670+ if (!kvm_s390_pv_cpu_is_protected(vcpu))
4671+ return -EINVAL;
46704672
46714673 switch (mop->op) {
46724674 case KVM_S390_MEMOP_SIDA_READ:
arch/s390/lib/test_modules.c+0−3
@@ -5,9 +5,6 @@ · 4 unmodified lines
55
66 #include "test_modules.h"
77
8−#define DECLARE_RETURN(i) int test_modules_return_ ## i(void)
9−REPEAT_10000(DECLARE_RETURN);
10−
118 /*
129 * Test that modules with many relocations are loaded properly.
1310 */
arch/s390/lib/test_modules.h+3−0
@@ -47,4 +47,7 @@ · 46 unmodified lines
4747 __REPEAT_10000_1(f, 8); \
4848 __REPEAT_10000_1(f, 9)
4949
50+#define DECLARE_RETURN(i) int test_modules_return_ ## i(void)
51+REPEAT_10000(DECLARE_RETURN);
52+
5053 #endif
arch/x86/crypto/blake2s-shash.c+2−2
@@ -18,12 +18,12 @@ · 17 unmodified lines
1818 static int crypto_blake2s_update_x86(struct shash_desc *desc,
1919 const u8 *in, unsigned int inlen)
2020 {
21− return crypto_blake2s_update(desc, in, inlen, blake2s_compress);
21+ return crypto_blake2s_update(desc, in, inlen, false);
2222 }
2323
2424 static int crypto_blake2s_final_x86(struct shash_desc *desc, u8 *out)
2525 {
26− return crypto_blake2s_final(desc, out, blake2s_compress);
26+ return crypto_blake2s_final(desc, out, false);
2727 }
2828
2929 #define BLAKE2S_ALG(name, driver_name, digest_size) \
arch/x86/events/intel/core.c+13−0
@@ -4703,6 +4703,19 @@ static __initconst const struct x86_pmu intel_pmu = { · 4702 unmodified lines
47034703 .lbr_read = intel_pmu_lbr_read_64,
47044704 .lbr_save = intel_pmu_lbr_save,
47054705 .lbr_restore = intel_pmu_lbr_restore,
4706+
4707+ /*
4708+ * SMM has access to all 4 rings and while traditionally SMM code only
4709+ * ran in CPL0, 2021-era firmware is starting to make use of CPL3 in SMM.
4710+ *
4711+ * Since the EVENTSEL.{USR,OS} CPL filtering makes no distinction
4712+ * between SMM or not, this results in what should be pure userspace
4713+ * counters including SMM data.
4714+ *
4715+ * This is a clear privilege issue, therefore globally disable
4716+ * counting SMM by default.
4717+ */
4718+ .attr_freeze_on_smi = 1,
47064719 };
47074720
47084721 static __init void intel_clovertown_quirk(void)
arch/x86/events/intel/pt.c+3−2
@@ -897,8 +897,9 @@ static void pt_handle_status(struct pt *pt) · 896 unmodified lines
897897 * means we are already losing data; need to let the decoder
898898 * know.
899899 */
900− if (!intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries) ||
901− buf->output_off == pt_buffer_region_size(buf)) {
900+ if (!buf->single &&
901+ (!intel_pt_validate_hw_cap(PT_CAP_topa_multiple_entries) ||
902+ buf->output_off == pt_buffer_region_size(buf))) {
902903 perf_aux_output_flag(&pt->handle,
903904 PERF_AUX_FLAG_TRUNCATED);
904905 advance++;
arch/x86/include/asm/bug.h+11−9
@@ -22,7 +22,7 @@ · 21 unmodified lines
2222
2323 #ifdef CONFIG_DEBUG_BUGVERBOSE
2424
25−#define _BUG_FLAGS(ins, flags) \
25+#define _BUG_FLAGS(ins, flags, extra) \
2626 do { \
2727 asm_inline volatile("1:\t" ins "\n" \
2828 ".pushsection __bug_table,\"aw\"\n" \
@@ -31,7 +31,8 @@ do { \ · 2 unmodified lines
3131 "\t.word %c1" "\t# bug_entry::line\n" \
3232 "\t.word %c2" "\t# bug_entry::flags\n" \
3333 "\t.org 2b+%c3\n" \
34− ".popsection" \
34+ ".popsection\n" \
35+ extra \
3536 : : "i" (__FILE__), "i" (__LINE__), \
3637 "i" (flags), \
3738 "i" (sizeof(struct bug_entry))); \
@@ -39,14 +40,15 @@ do { \ · 1 unmodified line
3940
4041 #else /* !CONFIG_DEBUG_BUGVERBOSE */
4142
42−#define _BUG_FLAGS(ins, flags) \
43+#define _BUG_FLAGS(ins, flags, extra) \
4344 do { \
4445 asm_inline volatile("1:\t" ins "\n" \
4546 ".pushsection __bug_table,\"aw\"\n" \
4647 "2:\t" __BUG_REL(1b) "\t# bug_entry::bug_addr\n" \
4748 "\t.word %c0" "\t# bug_entry::flags\n" \
4849 "\t.org 2b+%c1\n" \
49− ".popsection" \
50+ ".popsection\n" \
51+ extra \
5052 : : "i" (flags), \
5153 "i" (sizeof(struct bug_entry))); \
5254 } while (0)
@@ -55,7 +57,7 @@ do { \ · 2 unmodified lines
5557
5658 #else
5759
58−#define _BUG_FLAGS(ins, flags) asm volatile(ins)
60+#define _BUG_FLAGS(ins, flags, extra) asm volatile(ins)
5961
6062 #endif /* CONFIG_GENERIC_BUG */
6163
@@ -63,8 +65,8 @@ do { \ · 1 unmodified line
6365 #define BUG() \
6466 do { \
6567 instrumentation_begin(); \
66− _BUG_FLAGS(ASM_UD2, 0); \
67− unreachable(); \
68+ _BUG_FLAGS(ASM_UD2, 0, ""); \
69+ __builtin_unreachable(); \
6870 } while (0)
6971
7072 /*
@@ -75,9 +77,9 @@ do { \ · 4 unmodified lines
7577 */
7678 #define __WARN_FLAGS(flags) \
7779 do { \
80+ __auto_type f = BUGFLAG_WARNING|(flags); \
7881 instrumentation_begin(); \
79− _BUG_FLAGS(ASM_UD2, BUGFLAG_WARNING|(flags)); \
80− annotate_reachable(); \
82+ _BUG_FLAGS(ASM_UD2, f, ASM_REACHABLE); \
8183 instrumentation_end(); \
8284 } while (0)
8385
arch/x86/include/asm/kvm-x86-ops.h+1−1
@@ -82,7 +82,7 @@ KVM_X86_OP_NULL(guest_apic_has_interrupt) · 81 unmodified lines
8282 KVM_X86_OP(load_eoi_exitmap)
8383 KVM_X86_OP(set_virtual_apic_mode)
8484 KVM_X86_OP_NULL(set_apic_access_page_addr)
85−KVM_X86_OP(deliver_posted_interrupt)
85+KVM_X86_OP(deliver_interrupt)
8686 KVM_X86_OP_NULL(sync_pir_to_irr)
8787 KVM_X86_OP(set_tss_addr)
8888 KVM_X86_OP(set_identity_map_addr)
arch/x86/include/asm/kvm_host.h+2−1
@@ -1410,7 +1410,8 @@ struct kvm_x86_ops { · 1409 unmodified lines
14101410 void (*load_eoi_exitmap)(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap);
14111411 void (*set_virtual_apic_mode)(struct kvm_vcpu *vcpu);
14121412 void (*set_apic_access_page_addr)(struct kvm_vcpu *vcpu);
1413− int (*deliver_posted_interrupt)(struct kvm_vcpu *vcpu, int vector);
1413+ void (*deliver_interrupt)(struct kvm_lapic *apic, int delivery_mode,
1414+ int trig_mode, int vector);
14141415 int (*sync_pir_to_irr)(struct kvm_vcpu *vcpu);
14151416 int (*set_tss_addr)(struct kvm *kvm, unsigned int addr);
14161417 int (*set_identity_map_addr)(struct kvm *kvm, u64 ident_addr);
arch/x86/include/asm/xen/cpuid.h+7−0
@@ -100,6 +100,13 @@ · 99 unmodified lines
100100 /* Memory mapped from other domains has valid IOMMU entries */
101101 #define XEN_HVM_CPUID_IOMMU_MAPPINGS (1u << 2)
102102 #define XEN_HVM_CPUID_VCPU_ID_PRESENT (1u << 3) /* vcpu id is present in EBX */
103+#define XEN_HVM_CPUID_DOMID_PRESENT (1u << 4) /* domid is present in ECX */
104+/*
105+ * Bits 55:49 from the IO-APIC RTE and bits 11:5 from the MSI address can be
106+ * used to store high bits for the Destination ID. This expands the Destination
107+ * ID field from 8 to 15 bits, allowing to target APIC IDs up 32768.
108+ */
109+#define XEN_HVM_CPUID_EXT_DEST_ID (1u << 5)
103110
104111 /*
105112 * Leaf 6 (0x40000x05)
arch/x86/include/asm/xen/hypervisor.h+0−14
@@ -43,20 +43,6 @@ static inline uint32_t xen_cpuid_base(void) · 42 unmodified lines
4343 return hypervisor_cpuid_base("XenVMMXenVMM", 2);
4444 }
4545
46−#ifdef CONFIG_XEN
47−extern bool __init xen_hvm_need_lapic(void);
48−
49−static inline bool __init xen_x2apic_para_available(void)
50−{
51− return xen_hvm_need_lapic();
52−}
53−#else
54−static inline bool __init xen_x2apic_para_available(void)
55−{
56− return (xen_cpuid_base() != 0);
57−}
58−#endif
59−
6046 struct pci_dev;
6147
6248 #ifdef CONFIG_XEN_PV_DOM0
arch/x86/kernel/cpu/sgx/encl.c+2−0
@@ -410,6 +410,8 @@ void sgx_encl_release(struct kref *ref) · 409 unmodified lines
410410 }
411411
412412 kfree(entry);
413+ /* Invoke scheduler to prevent soft lockups. */
414+ cond_resched();
413415 }
414416
415417 xa_destroy(&encl->page_array);
arch/x86/kernel/early-quirks.c+1−0
@@ -555,6 +555,7 @@ static const struct pci_device_id intel_early_ids[] __initconst = { · 554 unmodified lines
555555 INTEL_RKL_IDS(&gen11_early_ops),
556556 INTEL_ADLS_IDS(&gen11_early_ops),
557557 INTEL_ADLP_IDS(&gen11_early_ops),
558+ INTEL_ADLN_IDS(&gen11_early_ops),
558559 INTEL_RPLS_IDS(&gen11_early_ops),
559560 };
560561
arch/x86/kernel/resource.c+1−22
@@ -1,5 +1,4 @@
11 // SPDX-License-Identifier: GPL-2.0
2−#include <linux/dmi.h>
32 #include <linux/ioport.h>
43 #include <asm/e820/api.h>
54
@@ -24,31 +23,11 @@ static void resource_clip(struct resource *res, resource_size_t start, · 18 unmodified lines
2423 res->start = end + 1;
2524 }
2625
27−/*
28− * Some BIOS-es contain a bug where they add addresses which map to
29− * system RAM in the PCI host bridge window returned by the ACPI _CRS
30− * method, see commit 4dc2287c1805 ("x86: avoid E820 regions when
31− * allocating address space"). To avoid this Linux by default excludes
32− * E820 reservations when allocating addresses since 2010.
33− * In 2019 some systems have shown-up with E820 reservations which cover
34− * the entire _CRS returned PCI host bridge window, causing all attempts
35− * to assign memory to PCI BARs to fail if Linux uses E820 reservations.
36− *
37− * Ideally Linux would fully stop using E820 reservations, but then
38− * the old systems this was added for will regress.
39− * Instead keep the old behavior for old systems, while ignoring the
40− * E820 reservations for any systems from now on.
41− */
4226 static void remove_e820_regions(struct resource *avail)
4327 {
44− int i, year = dmi_get_bios_year();
28+ int i;
4529 struct e820_entry *entry;
4630
47− if (year >= 2018)
48− return;
49−
50− pr_info_once("PCI: Removing E820 reservations from host bridge windows\n");
51−
5231 for (i = 0; i < e820_table->nr_entries; i++) {
5332 entry = &e820_table->entries[i];
5433
arch/x86/kvm/cpuid.c+7−6
@@ -554,12 +554,13 @@ void kvm_set_cpu_caps(void) · 553 unmodified lines
554554 );
555555
556556 kvm_cpu_cap_mask(CPUID_7_0_EBX,
557− F(FSGSBASE) | F(SGX) | F(BMI1) | F(HLE) | F(AVX2) | F(SMEP) |
558− F(BMI2) | F(ERMS) | F(INVPCID) | F(RTM) | 0 /*MPX*/ | F(RDSEED) |
559− F(ADX) | F(SMAP) | F(AVX512IFMA) | F(AVX512F) | F(AVX512PF) |
560− F(AVX512ER) | F(AVX512CD) | F(CLFLUSHOPT) | F(CLWB) | F(AVX512DQ) |
561− F(SHA_NI) | F(AVX512BW) | F(AVX512VL) | 0 /*INTEL_PT*/
562− );
557+ F(FSGSBASE) | F(SGX) | F(BMI1) | F(HLE) | F(AVX2) |
558+ F(FDP_EXCPTN_ONLY) | F(SMEP) | F(BMI2) | F(ERMS) | F(INVPCID) |
559+ F(RTM) | F(ZERO_FCS_FDS) | 0 /*MPX*/ | F(AVX512F) |
560+ F(AVX512DQ) | F(RDSEED) | F(ADX) | F(SMAP) | F(AVX512IFMA) |
561+ F(CLFLUSHOPT) | F(CLWB) | 0 /*INTEL_PT*/ | F(AVX512PF) |
562+ F(AVX512ER) | F(AVX512CD) | F(SHA_NI) | F(AVX512BW) |
563+ F(AVX512VL));
563564
564565 kvm_cpu_cap_mask(CPUID_7_ECX,
565566 F(AVX512VBMI) | F(LA57) | F(PKU) | 0 /*OSPKE*/ | F(RDPID) |
arch/x86/kvm/lapic.c+2−8
@@ -1096,14 +1096,8 @@ static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode, · 1095 unmodified lines
10961096 apic->regs + APIC_TMR);
10971097 }
10981098
1099− if (static_call(kvm_x86_deliver_posted_interrupt)(vcpu, vector)) {
1100− kvm_lapic_set_irr(vector, apic);
1101− kvm_make_request(KVM_REQ_EVENT, vcpu);
1102− kvm_vcpu_kick(vcpu);
1103− } else {
1104− trace_kvm_apicv_accept_irq(vcpu->vcpu_id, delivery_mode,
1105− trig_mode, vector);
1106− }
1099+ static_call(kvm_x86_deliver_interrupt)(apic, delivery_mode,
1100+ trig_mode, vector);
11071101 break;
11081102
11091103 case APIC_DM_REMRD:
arch/x86/kvm/svm/svm.c+18−3
@@ -3291,6 +3291,21 @@ static void svm_set_irq(struct kvm_vcpu *vcpu) · 3290 unmodified lines
32913291 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
32923292 }
32933293
3294+static void svm_deliver_interrupt(struct kvm_lapic *apic, int delivery_mode,
3295+ int trig_mode, int vector)
3296+{
3297+ struct kvm_vcpu *vcpu = apic->vcpu;
3298+
3299+ if (svm_deliver_avic_intr(vcpu, vector)) {
3300+ kvm_lapic_set_irr(vector, apic);
3301+ kvm_make_request(KVM_REQ_EVENT, vcpu);
3302+ kvm_vcpu_kick(vcpu);
3303+ } else {
3304+ trace_kvm_apicv_accept_irq(vcpu->vcpu_id, delivery_mode,
3305+ trig_mode, vector);
3306+ }
3307+}
3308+
32943309 static void svm_update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
32953310 {
32963311 struct vcpu_svm *svm = to_svm(vcpu);
@@ -3615,7 +3630,7 @@ static noinstr void svm_vcpu_enter_exit(struct kvm_vcpu *vcpu) · 318 unmodified lines
36153630 struct vcpu_svm *svm = to_svm(vcpu);
36163631 unsigned long vmcb_pa = svm->current_vmcb->pa;
36173632
3618− kvm_guest_enter_irqoff();
3633+ guest_state_enter_irqoff();
36193634
36203635 if (sev_es_guest(vcpu->kvm)) {
36213636 __svm_sev_es_vcpu_run(vmcb_pa);
@@ -3635,7 +3650,7 @@ static noinstr void svm_vcpu_enter_exit(struct kvm_vcpu *vcpu) · 13 unmodified lines
36353650 vmload(__sme_page_pa(sd->save_area));
36363651 }
36373652
3638− kvm_guest_exit_irqoff();
3653+ guest_state_exit_irqoff();
36393654 }
36403655
36413656 static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu)
@@ -4545,7 +4560,7 @@ static struct kvm_x86_ops svm_x86_ops __initdata = { · 903 unmodified lines
45454560 .pmu_ops = &amd_pmu_ops,
45464561 .nested_ops = &svm_nested_ops,
45474562
4548− .deliver_posted_interrupt = svm_deliver_avic_intr,
4563+ .deliver_interrupt = svm_deliver_interrupt,
45494564 .dy_apicv_has_pending_interrupt = svm_dy_apicv_has_pending_interrupt,
45504565 .update_pi_irte = svm_update_pi_irte,
45514566 .setup_mce = svm_setup_mce,
arch/x86/kvm/vmx/vmx.c+18−3
@@ -4041,6 +4041,21 @@ static int vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector) · 4040 unmodified lines
40414041 return 0;
40424042 }
40434043
4044+static void vmx_deliver_interrupt(struct kvm_lapic *apic, int delivery_mode,
4045+ int trig_mode, int vector)
4046+{
4047+ struct kvm_vcpu *vcpu = apic->vcpu;
4048+
4049+ if (vmx_deliver_posted_interrupt(vcpu, vector)) {
4050+ kvm_lapic_set_irr(vector, apic);
4051+ kvm_make_request(KVM_REQ_EVENT, vcpu);
4052+ kvm_vcpu_kick(vcpu);
4053+ } else {
4054+ trace_kvm_apicv_accept_irq(vcpu->vcpu_id, delivery_mode,
4055+ trig_mode, vector);
4056+ }
4057+}
4058+
40444059 /*
40454060 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
40464061 * will not change in the lifetime of the guest.
@@ -6754,7 +6769,7 @@ static fastpath_t vmx_exit_handlers_fastpath(struct kvm_vcpu *vcpu) · 2707 unmodified lines
67546769 static noinstr void vmx_vcpu_enter_exit(struct kvm_vcpu *vcpu,
67556770 struct vcpu_vmx *vmx)
67566771 {
6757− kvm_guest_enter_irqoff();
6772+ guest_state_enter_irqoff();
67586773
67596774 /* L1D Flush includes CPU buffer clear to mitigate MDS */
67606775 if (static_branch_unlikely(&vmx_l1d_should_flush))
@@ -6770,7 +6785,7 @@ static noinstr void vmx_vcpu_enter_exit(struct kvm_vcpu *vcpu, · 9 unmodified lines
67706785
67716786 vcpu->arch.cr2 = native_read_cr2();
67726787
6773− kvm_guest_exit_irqoff();
6788+ guest_state_exit_irqoff();
67746789 }
67756790
67766791 static fastpath_t vmx_vcpu_run(struct kvm_vcpu *vcpu)
@@ -7768,7 +7783,7 @@ static struct kvm_x86_ops vmx_x86_ops __initdata = { · 991 unmodified lines
77687783 .hwapic_isr_update = vmx_hwapic_isr_update,
77697784 .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
77707785 .sync_pir_to_irr = vmx_sync_pir_to_irr,
7771− .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
7786+ .deliver_interrupt = vmx_deliver_interrupt,
77727787 .dy_apicv_has_pending_interrupt = pi_has_pending_interrupt,
77737788
77747789 .set_tss_addr = vmx_set_tss_addr,
arch/x86/kvm/x86.c+6−4
@@ -90,6 +90,8 @@ · 89 unmodified lines
9090 u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
9191 EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
9292
93+#define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e))
94+
9395 #define emul_to_vcpu(ctxt) \
9496 ((struct kvm_vcpu *)(ctxt)->vcpu)
9597
@@ -4340,7 +4342,7 @@ static inline void __user *kvm_get_attr_addr(struct kvm_device_attr *attr) · 4244 unmodified lines
43404342 void __user *uaddr = (void __user*)(unsigned long)attr->addr;
43414343
43424344 if ((u64)(unsigned long)uaddr != attr->addr)
4343− return ERR_PTR(-EFAULT);
4345+ return ERR_PTR_USR(-EFAULT);
43444346 return uaddr;
43454347 }
43464348
@@ -10041,6 +10043,8 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu) · 5694 unmodified lines
1004110043 set_debugreg(0, 7);
1004210044 }
1004310045
10046+ guest_timing_enter_irqoff();
10047+
1004410048 for (;;) {
1004510049 /*
1004610050 * Assert that vCPU vs. VM APICv state is consistent. An APICv
@@ -10125,7 +10129,7 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu) · 78 unmodified lines
1012510129 * of accounting via context tracking, but the loss of accuracy is
1012610130 * acceptable for all known use cases.
1012710131 */
10128− vtime_account_guest_exit();
10132+ guest_timing_exit_irqoff();
1012910133
1013010134 if (lapic_in_kernel(vcpu)) {
1013110135 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
@@ -11639,8 +11643,6 @@ void kvm_arch_sync_events(struct kvm *kvm) · 1507 unmodified lines
1163911643 kvm_free_pit(kvm);
1164011644 }
1164111645
11642−#define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e))
11643−
1164411646 /**
1164511647 * __x86_set_memory_region: Setup KVM internal memory slot
1164611648 *
arch/x86/kvm/x86.h+0−45
@@ -10,51 +10,6 @@ · 9 unmodified lines
1010
1111 void kvm_spurious_fault(void);
1212
13−static __always_inline void kvm_guest_enter_irqoff(void)
14−{
15− /*
16− * VMENTER enables interrupts (host state), but the kernel state is
17− * interrupts disabled when this is invoked. Also tell RCU about
18− * it. This is the same logic as for exit_to_user_mode().
19− *
20− * This ensures that e.g. latency analysis on the host observes
21− * guest mode as interrupt enabled.
22− *
23− * guest_enter_irqoff() informs context tracking about the
24− * transition to guest mode and if enabled adjusts RCU state
25− * accordingly.
26− */
27− instrumentation_begin();
28− trace_hardirqs_on_prepare();
29− lockdep_hardirqs_on_prepare(CALLER_ADDR0);
30− instrumentation_end();
31−
32− guest_enter_irqoff();
33− lockdep_hardirqs_on(CALLER_ADDR0);
34−}
35−
36−static __always_inline void kvm_guest_exit_irqoff(void)
37−{
38− /*
39− * VMEXIT disables interrupts (host state), but tracing and lockdep
40− * have them in state 'on' as recorded before entering guest mode.
41− * Same as enter_from_user_mode().
42− *
43− * context_tracking_guest_exit() restores host context and reinstates
44− * RCU if enabled and required.
45− *
46− * This needs to be done immediately after VM-Exit, before any code
47− * that might contain tracepoints or call out to the greater world,
48− * e.g. before x86_spec_ctrl_restore_host().
49− */
50− lockdep_hardirqs_off(CALLER_ADDR0);
51− context_tracking_guest_exit();
52−
53− instrumentation_begin();
54− trace_hardirqs_off_finish();
55− instrumentation_end();
56−}
57−
5813 #define KVM_NESTED_VMENTER_CONSISTENCY_CHECK(consistency_check) \
5914 ({ \
6015 bool failed = (consistency_check); \
arch/x86/xen/enlighten_hvm.c+11−11
@@ -9,6 +9,7 @@ · 8 unmodified lines
99 #include <xen/events.h>
1010 #include <xen/interface/memory.h>
1111
12+#include <asm/apic.h>
1213 #include <asm/cpu.h>
1314 #include <asm/smp.h>
1415 #include <asm/io_apic.h>
@@ -184,8 +185,7 @@ static int xen_cpu_dead_hvm(unsigned int cpu) · 169 unmodified lines
184185
185186 if (xen_have_vector_callback && xen_feature(XENFEAT_hvm_safe_pvclock))
186187 xen_teardown_timer(cpu);
187−
188− return 0;
188+ return 0;
189189 }
190190
191191 static bool no_vector_callback __initdata;
@@ -242,15 +242,14 @@ static __init int xen_parse_no_vector_callback(char *arg) · 50 unmodified lines
242242 }
243243 early_param("xen_no_vector_callback", xen_parse_no_vector_callback);
244244
245−bool __init xen_hvm_need_lapic(void)
245+static __init bool xen_x2apic_available(void)
246246 {
247− if (xen_pv_domain())
248− return false;
249− if (!xen_hvm_domain())
250− return false;
251− if (xen_feature(XENFEAT_hvm_pirqs) && xen_have_vector_callback)
252− return false;
253− return true;
247+ return x2apic_supported();
248+}
249+
250+static bool __init msi_ext_dest_id(void)
251+{
252+ return cpuid_eax(xen_cpuid_base() + 4) & XEN_HVM_CPUID_EXT_DEST_ID;
254253 }
255254
256255 static __init void xen_hvm_guest_late_init(void)
@@ -312,9 +311,10 @@ struct hypervisor_x86 x86_hyper_xen_hvm __initdata = { · 55 unmodified lines
312311 .detect = xen_platform_hvm,
313312 .type = X86_HYPER_XEN_HVM,
314313 .init.init_platform = xen_hvm_guest_init,
315− .init.x2apic_available = xen_x2apic_para_available,
314+ .init.x2apic_available = xen_x2apic_available,
316315 .init.init_mem_mapping = xen_hvm_init_mem_mapping,
317316 .init.guest_late_init = xen_hvm_guest_late_init,
317+ .init.msi_ext_dest_id = msi_ext_dest_id,
318318 .runtime.pin_vcpu = xen_pin_vcpu,
319319 .ignore_nopv = true,
320320 };
arch/x86/xen/enlighten_pv.c+0−4
@@ -1341,10 +1341,6 @@ asmlinkage __visible void __init xen_start_kernel(void) · 1340 unmodified lines
13411341
13421342 xen_acpi_sleep_register();
13431343
1344− /* Avoid searching for BIOS MP tables */
1345− x86_init.mpparse.find_smp_config = x86_init_noop;
1346− x86_init.mpparse.get_smp_config = x86_init_uint_noop;
1347−
13481344 xen_boot_params_init_edd();
13491345
13501346 #ifdef CONFIG_ACPI
arch/x86/xen/smp_pv.c+6−20
@@ -148,28 +148,12 @@ int xen_smp_intr_init_pv(unsigned int cpu) · 147 unmodified lines
148148 return rc;
149149 }
150150
151−static void __init xen_fill_possible_map(void)
152−{
153− int i, rc;
154−
155− if (xen_initial_domain())
156− return;
157−
158− for (i = 0; i < nr_cpu_ids; i++) {
159− rc = HYPERVISOR_vcpu_op(VCPUOP_is_up, i, NULL);
160− if (rc >= 0) {
161− num_processors++;
162− set_cpu_possible(i, true);
163− }
164− }
165−}
166−
167−static void __init xen_filter_cpu_maps(void)
151+static void __init _get_smp_config(unsigned int early)
168152 {
169153 int i, rc;
170154 unsigned int subtract = 0;
171155
172− if (!xen_initial_domain())
156+ if (early)
173157 return;
174158
175159 num_processors = 0;
@@ -210,7 +194,6 @@ static void __init xen_pv_smp_prepare_boot_cpu(void) · 34 unmodified lines
210194 * sure the old memory can be recycled. */
211195 make_lowmem_page_readwrite(xen_initial_gdt);
212196
213− xen_filter_cpu_maps();
214197 xen_setup_vcpu_info_placement();
215198
216199 /*
@@ -476,5 +459,8 @@ static const struct smp_ops xen_smp_ops __initconst = { · 259 unmodified lines
476459 void __init xen_smp_init(void)
477460 {
478461 smp_ops = xen_smp_ops;
479− xen_fill_possible_map();
462+
463+ /* Avoid searching for BIOS MP tables */
464+ x86_init.mpparse.find_smp_config = x86_init_noop;
465+ x86_init.mpparse.get_smp_config = _get_smp_config;
480466 }
arch/x86/xen/vga.c+8−8
@@ -57,6 +57,14 @@ void __init xen_init_vga(const struct dom0_vga_console_info *info, size_t size) · 56 unmodified lines
5757 screen_info->rsvd_size = info->u.vesa_lfb.rsvd_size;
5858 screen_info->rsvd_pos = info->u.vesa_lfb.rsvd_pos;
5959
60+ if (size >= offsetof(struct dom0_vga_console_info,
61+ u.vesa_lfb.ext_lfb_base)
62+ + sizeof(info->u.vesa_lfb.ext_lfb_base)
63+ && info->u.vesa_lfb.ext_lfb_base) {
64+ screen_info->ext_lfb_base = info->u.vesa_lfb.ext_lfb_base;
65+ screen_info->capabilities |= VIDEO_CAPABILITY_64BIT_BASE;
66+ }
67+
6068 if (info->video_type == XEN_VGATYPE_EFI_LFB) {
6169 screen_info->orig_video_isVGA = VIDEO_TYPE_EFI;
6270 break;
@@ -66,14 +74,6 @@ void __init xen_init_vga(const struct dom0_vga_console_info *info, size_t size) · 3 unmodified lines
6674 u.vesa_lfb.mode_attrs)
6775 + sizeof(info->u.vesa_lfb.mode_attrs))
6876 screen_info->vesa_attributes = info->u.vesa_lfb.mode_attrs;
69−
70− if (size >= offsetof(struct dom0_vga_console_info,
71− u.vesa_lfb.ext_lfb_base)
72− + sizeof(info->u.vesa_lfb.ext_lfb_base)
73− && info->u.vesa_lfb.ext_lfb_base) {
74− screen_info->ext_lfb_base = info->u.vesa_lfb.ext_lfb_base;
75− screen_info->capabilities |= VIDEO_CAPABILITY_64BIT_BASE;
76− }
7777 break;
7878 }
7979 }
block/bio-integrity.c+1−1
@@ -373,7 +373,7 @@ void bio_integrity_advance(struct bio *bio, unsigned int bytes_done) · 372 unmodified lines
373373 struct blk_integrity *bi = blk_get_integrity(bio->bi_bdev->bd_disk);
374374 unsigned bytes = bio_integrity_bytes(bi, bytes_done >> 9);
375375
376− bip->bip_iter.bi_sector += bytes_done >> 9;
376+ bip->bip_iter.bi_sector += bio_integrity_intervals(bi, bytes_done >> 9);
377377 bvec_iter_advance(bip->bip_vec, &bip->bip_iter, bytes);
378378 }
379379
block/fops.c+19−14
@@ -566,34 +566,37 @@ static ssize_t blkdev_read_iter(struct kiocb *iocb, struct iov_iter *to) · 565 unmodified lines
566566 {
567567 struct block_device *bdev = iocb->ki_filp->private_data;
568568 loff_t size = bdev_nr_bytes(bdev);
569− size_t count = iov_iter_count(to);
570569 loff_t pos = iocb->ki_pos;
571570 size_t shorted = 0;
572571 ssize_t ret = 0;
572+ size_t count;
573573
574− if (unlikely(pos + count > size)) {
574+ if (unlikely(pos + iov_iter_count(to) > size)) {
575575 if (pos >= size)
576576 return 0;
577577 size -= pos;
578− if (count > size) {
579− shorted = count - size;
580− iov_iter_truncate(to, size);
581− }
578+ shorted = iov_iter_count(to) - size;
579+ iov_iter_truncate(to, size);
582580 }
583581
582+ count = iov_iter_count(to);
583+ if (!count)
584+ goto reexpand; /* skip atime */
585+
584586 if (iocb->ki_flags & IOCB_DIRECT) {
585587 struct address_space *mapping = iocb->ki_filp->f_mapping;
586588
587589 if (iocb->ki_flags & IOCB_NOWAIT) {
588− if (filemap_range_needs_writeback(mapping, iocb->ki_pos,
589− iocb->ki_pos + count - 1))
590− return -EAGAIN;
590+ if (filemap_range_needs_writeback(mapping, pos,
591+ pos + count - 1)) {
592+ ret = -EAGAIN;
593+ goto reexpand;
594+ }
591595 } else {
592− ret = filemap_write_and_wait_range(mapping,
593− iocb->ki_pos,
594− iocb->ki_pos + count - 1);
596+ ret = filemap_write_and_wait_range(mapping, pos,
597+ pos + count - 1);
595598 if (ret < 0)
596− return ret;
599+ goto reexpand;
597600 }
598601
599602 file_accessed(iocb->ki_filp);
@@ -603,12 +606,14 @@ static ssize_t blkdev_read_iter(struct kiocb *iocb, struct iov_iter *to) · 3 unmodified lines
603606 iocb->ki_pos += ret;
604607 count -= ret;
605608 }
609+ iov_iter_revert(to, count - iov_iter_count(to));
606610 if (ret < 0 || !count)
607− return ret;
611+ goto reexpand;
608612 }
609613
610614 ret = filemap_read(iocb, to, ret);
611615
616+reexpand:
612617 if (unlikely(shorted))
613618 iov_iter_reexpand(to, iov_iter_count(to) + shorted);
614619 return ret;
crypto/algapi.c+1−0
@@ -1324,3 +1324,4 @@ module_exit(crypto_algapi_exit); · 1323 unmodified lines
13241324
13251325 MODULE_LICENSE("GPL");
13261326 MODULE_DESCRIPTION("Cryptographic algorithms API");
1327+MODULE_SOFTDEP("pre: cryptomgr");
crypto/api.c+0−1
@@ -643,4 +643,3 @@ EXPORT_SYMBOL_GPL(crypto_req_done); · 642 unmodified lines
643643
644644 MODULE_DESCRIPTION("Cryptographic core API");
645645 MODULE_LICENSE("GPL");
646−MODULE_SOFTDEP("pre: cryptomgr");
crypto/blake2s_generic.c+2−2
@@ -15,12 +15,12 @@ · 14 unmodified lines
1515 static int crypto_blake2s_update_generic(struct shash_desc *desc,
1616 const u8 *in, unsigned int inlen)
1717 {
18− return crypto_blake2s_update(desc, in, inlen, blake2s_compress_generic);
18+ return crypto_blake2s_update(desc, in, inlen, true);
1919 }
2020
2121 static int crypto_blake2s_final_generic(struct shash_desc *desc, u8 *out)
2222 {
23− return crypto_blake2s_final(desc, out, blake2s_compress_generic);
23+ return crypto_blake2s_final(desc, out, true);
2424 }
2525
2626 #define BLAKE2S_ALG(name, driver_name, digest_size) \
drivers/accessibility/speakup/speakup_dectlk.c+1−0
@@ -44,6 +44,7 @@ static struct var_t vars[] = { · 43 unmodified lines
4444 { CAPS_START, .u.s = {"[:dv ap 160] " } },
4545 { CAPS_STOP, .u.s = {"[:dv ap 100 ] " } },
4646 { RATE, .u.n = {"[:ra %d] ", 180, 75, 650, 0, 0, NULL } },
47+ { PITCH, .u.n = {"[:dv ap %d] ", 122, 50, 350, 0, 0, NULL } },
4748 { INFLECTION, .u.n = {"[:dv pr %d] ", 100, 0, 10000, 0, 0, NULL } },
4849 { VOL, .u.n = {"[:dv g5 %d] ", 86, 60, 86, 0, 0, NULL } },
4950 { PUNCT, .u.n = {"[:pu %c] ", 0, 0, 2, 0, 0, "nsa" } },
drivers/acpi/Kconfig+1−0
@@ -11,6 +11,7 @@ menuconfig ACPI · 10 unmodified lines
1111 depends on ARCH_SUPPORTS_ACPI
1212 select PNP
1313 select NLS
14+ select CRC32
1415 default y if X86
1516 help
1617 Advanced Configuration and Power Interface (ACPI) support for
drivers/acpi/arm64/iort.c+11−3
@@ -1361,9 +1361,17 @@ static void __init arm_smmu_v3_pmcg_init_resources(struct resource *res, · 1360 unmodified lines
13611361 res[0].start = pmcg->page0_base_address;
13621362 res[0].end = pmcg->page0_base_address + SZ_4K - 1;
13631363 res[0].flags = IORESOURCE_MEM;
1364− res[1].start = pmcg->page1_base_address;
1365− res[1].end = pmcg->page1_base_address + SZ_4K - 1;
1366− res[1].flags = IORESOURCE_MEM;
1364+ /*
1365+ * The initial version in DEN0049C lacked a way to describe register
1366+ * page 1, which makes it broken for most PMCG implementations; in
1367+ * that case, just let the driver fail gracefully if it expects to
1368+ * find a second memory resource.
1369+ */
1370+ if (node->revision > 0) {
1371+ res[1].start = pmcg->page1_base_address;
1372+ res[1].end = pmcg->page1_base_address + SZ_4K - 1;
1373+ res[1].flags = IORESOURCE_MEM;
1374+ }
13671375
13681376 if (pmcg->overflow_gsiv)
13691377 acpi_iort_register_irq(pmcg->overflow_gsiv, "overflow",
drivers/acpi/ec.c+10−0
@@ -2065,6 +2065,16 @@ bool acpi_ec_dispatch_gpe(void) · 2064 unmodified lines
20652065 if (acpi_any_gpe_status_set(first_ec->gpe))
20662066 return true;
20672067
2068+ /*
2069+ * Cancel the SCI wakeup and process all pending events in case there
2070+ * are any wakeup ones in there.
2071+ *
2072+ * Note that if any non-EC GPEs are active at this point, the SCI will
2073+ * retrigger after the rearming in acpi_s2idle_wake(), so no events
2074+ * should be missed by canceling the wakeup here.
2075+ */
2076+ pm_system_cancel_wakeup();
2077+
20682078 /*
20692079 * Dispatch the EC GPE in-band, but do not report wakeup in any case
20702080 * to allow the caller to process events properly after that.
drivers/acpi/sleep.c+5−10
@@ -736,21 +736,15 @@ bool acpi_s2idle_wake(void) · 735 unmodified lines
736736 return true;
737737 }
738738
739− /* Check non-EC GPE wakeups and dispatch the EC GPE. */
739+ /*
740+ * Check non-EC GPE wakeups and if there are none, cancel the
741+ * SCI-related wakeup and dispatch the EC GPE.
742+ */
740743 if (acpi_ec_dispatch_gpe()) {
741744 pm_pr_dbg("ACPI non-EC GPE wakeup\n");
742745 return true;
743746 }
744747
745− /*
746− * Cancel the SCI wakeup and process all pending events in case
747− * there are any wakeup ones in there.
748− *
749− * Note that if any non-EC GPEs are active at this point, the
750− * SCI will retrigger after the rearming below, so no events
751− * should be missed by canceling the wakeup here.
752− */
753− pm_system_cancel_wakeup();
754748 acpi_os_wait_events_complete();
755749
756750 /*
@@ -764,6 +758,7 @@ bool acpi_s2idle_wake(void) · 7 unmodified lines
764758 return true;
765759 }
766760
761+ pm_wakeup_clear(acpi_sci_irq);
767762 rearm_wake_irq(acpi_sci_irq);
768763 }
769764
drivers/acpi/x86/s2idle.c+4−8
@@ -424,15 +424,11 @@ static int lps0_device_attach(struct acpi_device *adev, · 423 unmodified lines
424424 mem_sleep_current = PM_SUSPEND_TO_IDLE;
425425
426426 /*
427− * Some Intel based LPS0 systems, like ASUS Zenbook UX430UNR/i7-8550U don't
428− * use intel-hid or intel-vbtn but require the EC GPE to be enabled while
429− * suspended for certain wakeup devices to work, so mark it as wakeup-capable.
430− *
431− * Only enable on !AMD as enabling this universally causes problems for a number
432− * of AMD based systems.
427+ * Some LPS0 systems, like ASUS Zenbook UX430UNR/i7-8550U, require the
428+ * EC GPE to be enabled while suspended for certain wakeup devices to
429+ * work, so mark it as wakeup-capable.
433430 */
434− if (!acpi_s2idle_vendor_amd())
435− acpi_ec_mark_gpe_for_wake();
431+ acpi_ec_mark_gpe_for_wake();
436432
437433 return 0;
438434 }
drivers/ata/libata-core.c+17−8
@@ -2007,6 +2007,9 @@ static bool ata_log_supported(struct ata_device *dev, u8 log) · 2006 unmodified lines
20072007 {
20082008 struct ata_port *ap = dev->link->ap;
20092009
2010+ if (dev->horkage & ATA_HORKAGE_NO_LOG_DIR)
2011+ return false;
2012+
20102013 if (ata_read_log_page(dev, ATA_LOG_DIRECTORY, 0, ap->sector_buf, 1))
20112014 return false;
20122015 return get_unaligned_le16(&ap->sector_buf[log * 2]) ? true : false;
@@ -2445,23 +2448,21 @@ static void ata_dev_config_cpr(struct ata_device *dev) · 432 unmodified lines
24452448 struct ata_cpr_log *cpr_log = NULL;
24462449 u8 *desc, *buf = NULL;
24472450
2448− if (!ata_identify_page_supported(dev,
2449− ATA_LOG_CONCURRENT_POSITIONING_RANGES))
2451+ if (ata_id_major_version(dev->id) < 11 ||
2452+ !ata_log_supported(dev, ATA_LOG_CONCURRENT_POSITIONING_RANGES))
24502453 goto out;
24512454
24522455 /*
2453− * Read IDENTIFY DEVICE data log, page 0x47
2454− * (concurrent positioning ranges). We can have at most 255 32B range
2455− * descriptors plus a 64B header.
2456+ * Read the concurrent positioning ranges log (0x47). We can have at
2457+ * most 255 32B range descriptors plus a 64B header.
24562458 */
24572459 buf_len = (64 + 255 * 32 + 511) & ~511;
24582460 buf = kzalloc(buf_len, GFP_KERNEL);
24592461 if (!buf)
24602462 goto out;
24612463
2462− err_mask = ata_read_log_page(dev, ATA_LOG_IDENTIFY_DEVICE,
2463− ATA_LOG_CONCURRENT_POSITIONING_RANGES,
2464− buf, buf_len >> 9);
2464+ err_mask = ata_read_log_page(dev, ATA_LOG_CONCURRENT_POSITIONING_RANGES,
2465+ 0, buf, buf_len >> 9);
24652466 if (err_mask)
24662467 goto out;
24672468
@@ -4028,6 +4029,7 @@ static const struct ata_blacklist_entry ata_device_blacklist [] = { · 1560 unmodified lines
40284029
40294030 /* devices that don't properly handle TRIM commands */
40304031 { "SuperSSpeed S238*", NULL, ATA_HORKAGE_NOTRIM, },
4032+ { "M88V29*", NULL, ATA_HORKAGE_NOTRIM, },
40314033
40324034 /*
40334035 * As defined, the DRAT (Deterministic Read After Trim) and RZAT
@@ -4073,6 +4075,13 @@ static const struct ata_blacklist_entry ata_device_blacklist [] = { · 39 unmodified lines
40734075 { "WDC WD3000JD-*", NULL, ATA_HORKAGE_WD_BROKEN_LPM },
40744076 { "WDC WD3200JD-*", NULL, ATA_HORKAGE_WD_BROKEN_LPM },
40754077
4078+ /*
4079+ * This sata dom device goes on a walkabout when the ATA_LOG_DIRECTORY
4080+ * log page is accessed. Ensure we never ask for this log page with
4081+ * these devices.
4082+ */
4083+ { "SATADOM-ML 3ME", NULL, ATA_HORKAGE_NO_LOG_DIR },
4084+
40764085 /* End Marker */
40774086 { }
40784087 };
drivers/ata/sata_fsl.c+7−9
@@ -322,7 +322,7 @@ static void fsl_sata_set_irq_coalescing(struct ata_host *host, · 321 unmodified lines
322322 static ssize_t fsl_sata_intr_coalescing_show(struct device *dev,
323323 struct device_attribute *attr, char *buf)
324324 {
325− return sysfs_emit(buf, "%d %d\n",
325+ return sysfs_emit(buf, "%u %u\n",
326326 intr_coalescing_count, intr_coalescing_ticks);
327327 }
328328
@@ -332,10 +332,8 @@ static ssize_t fsl_sata_intr_coalescing_store(struct device *dev, · 3 unmodified lines
332332 {
333333 unsigned int coalescing_count, coalescing_ticks;
334334
335− if (sscanf(buf, "%d%d",
336− &coalescing_count,
337− &coalescing_ticks) != 2) {
338− printk(KERN_ERR "fsl-sata: wrong parameter format.\n");
335+ if (sscanf(buf, "%u%u", &coalescing_count, &coalescing_ticks) != 2) {
336+ dev_err(dev, "fsl-sata: wrong parameter format.\n");
339337 return -EINVAL;
340338 }
341339
@@ -359,7 +357,7 @@ static ssize_t fsl_sata_rx_watermark_show(struct device *dev, · 17 unmodified lines
359357 rx_watermark &= 0x1f;
360358 spin_unlock_irqrestore(&host->lock, flags);
361359
362− return sysfs_emit(buf, "%d\n", rx_watermark);
360+ return sysfs_emit(buf, "%u\n", rx_watermark);
363361 }
364362
365363 static ssize_t fsl_sata_rx_watermark_store(struct device *dev,
@@ -373,8 +371,8 @@ static ssize_t fsl_sata_rx_watermark_store(struct device *dev, · 7 unmodified lines
373371 void __iomem *csr_base = host_priv->csr_base;
374372 u32 temp;
375373
376− if (sscanf(buf, "%d", &rx_watermark) != 1) {
377− printk(KERN_ERR "fsl-sata: wrong parameter format.\n");
374+ if (kstrtouint(buf, 10, &rx_watermark) < 0) {
375+ dev_err(dev, "fsl-sata: wrong parameter format.\n");
378376 return -EINVAL;
379377 }
380378
@@ -382,8 +380,8 @@ static ssize_t fsl_sata_rx_watermark_store(struct device *dev, · 1 unmodified line
382380 temp = ioread32(csr_base + TRANSCFG);
383381 temp &= 0xffffffe0;
384382 iowrite32(temp | rx_watermark, csr_base + TRANSCFG);
385−
386383 spin_unlock_irqrestore(&host->lock, flags);
384+
387385 return strlen(buf);
388386 }
389387
drivers/base/power/wakeup.c+34−7
@@ -34,7 +34,8 @@ suspend_state_t pm_suspend_target_state; · 33 unmodified lines
3434 bool events_check_enabled __read_mostly;
3535
3636 /* First wakeup IRQ seen by the kernel in the last cycle. */
37−unsigned int pm_wakeup_irq __read_mostly;
37+static unsigned int wakeup_irq[2] __read_mostly;
38+static DEFINE_RAW_SPINLOCK(wakeup_irq_lock);
3839
3940 /* If greater than 0 and the system is suspending, terminate the suspend. */
4041 static atomic_t pm_abort_suspend __read_mostly;
@@ -942,19 +943,45 @@ void pm_system_cancel_wakeup(void) · 901 unmodified lines
942943 atomic_dec_if_positive(&pm_abort_suspend);
943944 }
944945
945−void pm_wakeup_clear(bool reset)
946+void pm_wakeup_clear(unsigned int irq_number)
946947 {
947− pm_wakeup_irq = 0;
948− if (reset)
948+ raw_spin_lock_irq(&wakeup_irq_lock);
949+
950+ if (irq_number && wakeup_irq[0] == irq_number)
951+ wakeup_irq[0] = wakeup_irq[1];
952+ else
953+ wakeup_irq[0] = 0;
954+
955+ wakeup_irq[1] = 0;
956+
957+ raw_spin_unlock_irq(&wakeup_irq_lock);
958+
959+ if (!irq_number)
949960 atomic_set(&pm_abort_suspend, 0);
950961 }
951962
952963 void pm_system_irq_wakeup(unsigned int irq_number)
953964 {
954− if (pm_wakeup_irq == 0) {
955− pm_wakeup_irq = irq_number;
965+ unsigned long flags;
966+
967+ raw_spin_lock_irqsave(&wakeup_irq_lock, flags);
968+
969+ if (wakeup_irq[0] == 0)
970+ wakeup_irq[0] = irq_number;
971+ else if (wakeup_irq[1] == 0)
972+ wakeup_irq[1] = irq_number;
973+ else
974+ irq_number = 0;
975+
976+ raw_spin_unlock_irqrestore(&wakeup_irq_lock, flags);
977+
978+ if (irq_number)
956979 pm_system_wakeup();
957− }
980+}
981+
982+unsigned int pm_wakeup_irq(void)
983+{
984+ return wakeup_irq[0];
958985 }
959986
960987 /**
drivers/block/loop.c+29−36
@@ -1082,7 +1082,7 @@ out_putf: · 1081 unmodified lines
10821082 return error;
10831083 }
10841084
1085−static void __loop_clr_fd(struct loop_device *lo)
1085+static void __loop_clr_fd(struct loop_device *lo, bool release)
10861086 {
10871087 struct file *filp;
10881088 gfp_t gfp = lo->old_gfp_mask;
@@ -1144,6 +1144,8 @@ static void __loop_clr_fd(struct loop_device *lo) · 55 unmodified lines
11441144 /* let user-space know about this change */
11451145 kobject_uevent(&disk_to_dev(lo->lo_disk)->kobj, KOBJ_CHANGE);
11461146 mapping_set_gfp_mask(filp->f_mapping, gfp);
1147+ /* This is safe: open() is still holding a reference. */
1148+ module_put(THIS_MODULE);
11471149 blk_mq_unfreeze_queue(lo->lo_queue);
11481150
11491151 disk_force_media_change(lo->lo_disk, DISK_EVENT_MEDIA_CHANGE);
@@ -1151,52 +1153,44 @@ static void __loop_clr_fd(struct loop_device *lo) · 1 unmodified line
11511153 if (lo->lo_flags & LO_FLAGS_PARTSCAN) {
11521154 int err;
11531155
1154− mutex_lock(&lo->lo_disk->open_mutex);
1156+ /*
1157+ * open_mutex has been held already in release path, so don't
1158+ * acquire it if this function is called in such case.
1159+ *
1160+ * If the reread partition isn't from release path, lo_refcnt
1161+ * must be at least one and it can only become zero when the
1162+ * current holder is released.
1163+ */
1164+ if (!release)
1165+ mutex_lock(&lo->lo_disk->open_mutex);
11551166 err = bdev_disk_changed(lo->lo_disk, false);
1156− mutex_unlock(&lo->lo_disk->open_mutex);
1167+ if (!release)
1168+ mutex_unlock(&lo->lo_disk->open_mutex);
11571169 if (err)
11581170 pr_warn("%s: partition scan of loop%d failed (rc=%d)\n",
11591171 __func__, lo->lo_number, err);
11601172 /* Device is gone, no point in returning error */
11611173 }
11621174
1175+ /*
1176+ * lo->lo_state is set to Lo_unbound here after above partscan has
1177+ * finished. There cannot be anybody else entering __loop_clr_fd() as
1178+ * Lo_rundown state protects us from all the other places trying to
1179+ * change the 'lo' device.
1180+ */
11631181 lo->lo_flags = 0;
11641182 if (!part_shift)
11651183 lo->lo_disk->flags |= GENHD_FL_NO_PART;
1166−
1167− fput(filp);
1168−}
1169−
1170−static void loop_rundown_completed(struct loop_device *lo)
1171−{
11721184 mutex_lock(&lo->lo_mutex);
11731185 lo->lo_state = Lo_unbound;
11741186 mutex_unlock(&lo->lo_mutex);
1175− module_put(THIS_MODULE);
1176−}
1177−
1178−static void loop_rundown_workfn(struct work_struct *work)
1179−{
1180− struct loop_device *lo = container_of(work, struct loop_device,
1181− rundown_work);
1182− struct block_device *bdev = lo->lo_device;
1183− struct gendisk *disk = lo->lo_disk;
1184−
1185− __loop_clr_fd(lo);
1186− kobject_put(&bdev->bd_device.kobj);
1187− module_put(disk->fops->owner);
1188− loop_rundown_completed(lo);
1189−}
11901187
1191−static void loop_schedule_rundown(struct loop_device *lo)
1192−{
1193− struct block_device *bdev = lo->lo_device;
1194− struct gendisk *disk = lo->lo_disk;
1195−
1196− __module_get(disk->fops->owner);
1197− kobject_get(&bdev->bd_device.kobj);
1198− INIT_WORK(&lo->rundown_work, loop_rundown_workfn);
1199− queue_work(system_long_wq, &lo->rundown_work);
1188+ /*
1189+ * Need not hold lo_mutex to fput backing file. Calling fput holding
1190+ * lo_mutex triggers a circular lock dependency possibility warning as
1191+ * fput can take open_mutex which is usually taken before lo_mutex.
1192+ */
1193+ fput(filp);
12001194 }
12011195
12021196 static int loop_clr_fd(struct loop_device *lo)
@@ -1228,8 +1222,7 @@ static int loop_clr_fd(struct loop_device *lo) · 25 unmodified lines
12281222 lo->lo_state = Lo_rundown;
12291223 mutex_unlock(&lo->lo_mutex);
12301224
1231− __loop_clr_fd(lo);
1232− loop_rundown_completed(lo);
1225+ __loop_clr_fd(lo, false);
12331226 return 0;
12341227 }
12351228
@@ -1754,7 +1747,7 @@ static void lo_release(struct gendisk *disk, fmode_t mode) · 518 unmodified lines
17541747 * In autoclear mode, stop the loop thread
17551748 * and remove configuration after last close.
17561749 */
1757− loop_schedule_rundown(lo);
1750+ __loop_clr_fd(lo, true);
17581751 return;
17591752 } else if (lo->lo_state == Lo_bound) {
17601753 /*
drivers/block/loop.h+0−1
@@ -56,7 +56,6 @@ struct loop_device { · 55 unmodified lines
5656 struct gendisk *lo_disk;
5757 struct mutex lo_mutex;
5858 bool idr_visible;
59− struct work_struct rundown_work;
6059 };
6160
6261 struct loop_cmd {
drivers/bus/mhi/pci_generic.c+2−0
@@ -366,6 +366,7 @@ static const struct mhi_pci_dev_info mhi_foxconn_sdx55_info = { · 365 unmodified lines
366366 .config = &modem_foxconn_sdx55_config,
367367 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
368368 .dma_data_width = 32,
369+ .mru_default = 32768,
369370 .sideband_wake = false,
370371 };
371372
@@ -401,6 +402,7 @@ static const struct mhi_pci_dev_info mhi_mv31_info = { · 29 unmodified lines
401402 .config = &modem_mv31_config,
402403 .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
403404 .dma_data_width = 32,
405+ .mru_default = 32768,
404406 };
405407
406408 static const struct mhi_channel_config mhi_sierra_em919x_channels[] = {
drivers/char/random.c+22−17
@@ -762,7 +762,7 @@ static bool crng_init_try_arch(struct crng_state *crng) · 761 unmodified lines
762762 return arch_init;
763763 }
764764
765−static bool __init crng_init_try_arch_early(struct crng_state *crng)
765+static bool __init crng_init_try_arch_early(void)
766766 {
767767 int i;
768768 bool arch_init = true;
@@ -774,7 +774,7 @@ static bool __init crng_init_try_arch_early(struct crng_state *crng) · 5 unmodified lines
774774 rv = random_get_entropy();
775775 arch_init = false;
776776 }
777− crng->state[i] ^= rv;
777+ primary_crng.state[i] ^= rv;
778778 }
779779
780780 return arch_init;
@@ -788,22 +788,20 @@ static void crng_initialize_secondary(struct crng_state *crng) · 7 unmodified lines
788788 crng->init_time = jiffies - CRNG_RESEED_INTERVAL - 1;
789789 }
790790
791−static void __init crng_initialize_primary(struct crng_state *crng)
791+static void __init crng_initialize_primary(void)
792792 {
793− _extract_entropy(&crng->state[4], sizeof(u32) * 12);
794− if (crng_init_try_arch_early(crng) && trust_cpu && crng_init < 2) {
793+ _extract_entropy(&primary_crng.state[4], sizeof(u32) * 12);
794+ if (crng_init_try_arch_early() && trust_cpu && crng_init < 2) {
795795 invalidate_batched_entropy();
796796 numa_crng_init();
797797 crng_init = 2;
798798 pr_notice("crng init done (trusting CPU's manufacturer)\n");
799799 }
800− crng->init_time = jiffies - CRNG_RESEED_INTERVAL - 1;
800+ primary_crng.init_time = jiffies - CRNG_RESEED_INTERVAL - 1;
801801 }
802802
803−static void crng_finalize_init(struct crng_state *crng)
803+static void crng_finalize_init(void)
804804 {
805− if (crng != &primary_crng || crng_init >= 2)
806− return;
807805 if (!system_wq) {
808806 /* We can't call numa_crng_init until we have workqueues,
809807 * so mark this for processing later. */
@@ -814,6 +812,7 @@ static void crng_finalize_init(struct crng_state *crng) · 4 unmodified lines
814812 invalidate_batched_entropy();
815813 numa_crng_init();
816814 crng_init = 2;
815+ crng_need_final_init = false;
817816 process_random_ready_list();
818817 wake_up_interruptible(&crng_init_wait);
819818 kill_fasync(&fasync, SIGIO, POLL_IN);
@@ -980,7 +979,8 @@ static void crng_reseed(struct crng_state *crng, bool use_input_pool) · 160 unmodified lines
980979 memzero_explicit(&buf, sizeof(buf));
981980 WRITE_ONCE(crng->init_time, jiffies);
982981 spin_unlock_irqrestore(&crng->lock, flags);
983− crng_finalize_init(crng);
982+ if (crng == &primary_crng && crng_init < 2)
983+ crng_finalize_init();
984984 }
985985
986986 static void _extract_crng(struct crng_state *crng, u8 out[CHACHA_BLOCK_SIZE])
@@ -1697,8 +1697,8 @@ int __init rand_initialize(void) · 710 unmodified lines
16971697 {
16981698 init_std_data();
16991699 if (crng_need_final_init)
1700− crng_finalize_init(&primary_crng);
1701− crng_initialize_primary(&primary_crng);
1700+ crng_finalize_init();
1701+ crng_initialize_primary();
17021702 crng_global_init_time = jiffies;
17031703 if (ratelimit_disable) {
17041704 urandom_warning.interval = 0;
@@ -1856,7 +1856,10 @@ static long random_ioctl(struct file *f, unsigned int cmd, unsigned long arg) · 151 unmodified lines
18561856 */
18571857 if (!capable(CAP_SYS_ADMIN))
18581858 return -EPERM;
1859− input_pool.entropy_count = 0;
1859+ if (xchg(&input_pool.entropy_count, 0) && random_write_wakeup_bits) {
1860+ wake_up_interruptible(&random_write_wait);
1861+ kill_fasync(&fasync, SIGIO, POLL_OUT);
1862+ }
18601863 return 0;
18611864 case RNDRESEEDCRNG:
18621865 if (!capable(CAP_SYS_ADMIN))
@@ -2205,13 +2208,15 @@ void add_hwgenerator_randomness(const char *buffer, size_t count, · 342 unmodified lines
22052208 return;
22062209 }
22072210
2208− /* Suspend writing if we're above the trickle threshold.
2211+ /* Throttle writing if we're above the trickle threshold.
22092212 * We'll be woken up again once below random_write_wakeup_thresh,
2210− * or when the calling thread is about to terminate.
2213+ * when the calling thread is about to terminate, or once
2214+ * CRNG_RESEED_INTERVAL has lapsed.
22112215 */
2212− wait_event_interruptible(random_write_wait,
2216+ wait_event_interruptible_timeout(random_write_wait,
22132217 !system_wq || kthread_should_stop() ||
2214− POOL_ENTROPY_BITS() <= random_write_wakeup_bits);
2218+ POOL_ENTROPY_BITS() <= random_write_wakeup_bits,
2219+ CRNG_RESEED_INTERVAL);
22152220 mix_pool_bytes(buffer, count);
22162221 credit_entropy_bits(entropy);
22172222 }
drivers/clocksource/timer-ti-dm-systimer.c+1−1
@@ -241,7 +241,7 @@ static void __init dmtimer_systimer_assign_alwon(void) · 240 unmodified lines
241241 bool quirk_unreliable_oscillator = false;
242242
243243 /* Quirk unreliable 32 KiHz oscillator with incomplete dts */
244− if (of_machine_is_compatible("ti,omap3-beagle") ||
244+ if (of_machine_is_compatible("ti,omap3-beagle-ab4") ||
245245 of_machine_is_compatible("timll,omap3-devkit8000")) {
246246 quirk_unreliable_oscillator = true;
247247 counter_32k = -ENODEV;
drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c+2−1
@@ -1753,7 +1753,6 @@ void otx2_cpt_print_uc_dbg_info(struct otx2_cptpf_dev *cptpf) · 1752 unmodified lines
17531753 char engs_info[2 * OTX2_CPT_NAME_LENGTH];
17541754 struct otx2_cpt_eng_grp_info *grp;
17551755 struct otx2_cpt_engs_rsvd *engs;
1756− u32 mask[4];
17571756 int i, j;
17581757
17591758 pr_debug("Engine groups global info");
@@ -1785,6 +1784,8 @@ void otx2_cpt_print_uc_dbg_info(struct otx2_cptpf_dev *cptpf) · 25 unmodified lines
17851784 for (j = 0; j < OTX2_CPT_MAX_ETYPES_PER_GRP; j++) {
17861785 engs = &grp->engs[j];
17871786 if (engs->type) {
1787+ u32 mask[5] = { };
1788+
17881789 get_engs_info(grp, engs_info,
17891790 2 * OTX2_CPT_NAME_LENGTH, j);
17901791 pr_debug("Slot%d: %s", j, engs_info);
drivers/dma-buf/dma-buf.c+11−11
@@ -1047,8 +1047,8 @@ EXPORT_SYMBOL_NS_GPL(dma_buf_move_notify, DMA_BUF); · 1046 unmodified lines
10471047 *
10481048 * Interfaces::
10491049 *
1050− * void \*dma_buf_vmap(struct dma_buf \*dmabuf, struct dma_buf_map \*map)
1051− * void dma_buf_vunmap(struct dma_buf \*dmabuf, struct dma_buf_map \*map)
1050+ * void \*dma_buf_vmap(struct dma_buf \*dmabuf, struct iosys_map \*map)
1051+ * void dma_buf_vunmap(struct dma_buf \*dmabuf, struct iosys_map \*map)
10521052 *
10531053 * The vmap call can fail if there is no vmap support in the exporter, or if
10541054 * it runs out of vmalloc space. Note that the dma-buf layer keeps a reference
@@ -1260,12 +1260,12 @@ EXPORT_SYMBOL_NS_GPL(dma_buf_mmap, DMA_BUF); · 205 unmodified lines
12601260 *
12611261 * Returns 0 on success, or a negative errno code otherwise.
12621262 */
1263−int dma_buf_vmap(struct dma_buf *dmabuf, struct dma_buf_map *map)
1263+int dma_buf_vmap(struct dma_buf *dmabuf, struct iosys_map *map)
12641264 {
1265− struct dma_buf_map ptr;
1265+ struct iosys_map ptr;
12661266 int ret = 0;
12671267
1268− dma_buf_map_clear(map);
1268+ iosys_map_clear(map);
12691269
12701270 if (WARN_ON(!dmabuf))
12711271 return -EINVAL;
@@ -1276,12 +1276,12 @@ int dma_buf_vmap(struct dma_buf *dmabuf, struct dma_buf_map *map) · 4 unmodified lines
12761276 mutex_lock(&dmabuf->lock);
12771277 if (dmabuf->vmapping_counter) {
12781278 dmabuf->vmapping_counter++;
1279− BUG_ON(dma_buf_map_is_null(&dmabuf->vmap_ptr));
1279+ BUG_ON(iosys_map_is_null(&dmabuf->vmap_ptr));
12801280 *map = dmabuf->vmap_ptr;
12811281 goto out_unlock;
12821282 }
12831283
1284− BUG_ON(dma_buf_map_is_set(&dmabuf->vmap_ptr));
1284+ BUG_ON(iosys_map_is_set(&dmabuf->vmap_ptr));
12851285
12861286 ret = dmabuf->ops->vmap(dmabuf, &ptr);
12871287 if (WARN_ON_ONCE(ret))
@@ -1303,20 +1303,20 @@ EXPORT_SYMBOL_NS_GPL(dma_buf_vmap, DMA_BUF); · 15 unmodified lines
13031303 * @dmabuf: [in] buffer to vunmap
13041304 * @map: [in] vmap pointer to vunmap
13051305 */
1306−void dma_buf_vunmap(struct dma_buf *dmabuf, struct dma_buf_map *map)
1306+void dma_buf_vunmap(struct dma_buf *dmabuf, struct iosys_map *map)
13071307 {
13081308 if (WARN_ON(!dmabuf))
13091309 return;
13101310
1311− BUG_ON(dma_buf_map_is_null(&dmabuf->vmap_ptr));
1311+ BUG_ON(iosys_map_is_null(&dmabuf->vmap_ptr));
13121312 BUG_ON(dmabuf->vmapping_counter == 0);
1313− BUG_ON(!dma_buf_map_is_equal(&dmabuf->vmap_ptr, map));
1313+ BUG_ON(!iosys_map_is_equal(&dmabuf->vmap_ptr, map));
13141314
13151315 mutex_lock(&dmabuf->lock);
13161316 if (--dmabuf->vmapping_counter == 0) {
13171317 if (dmabuf->ops->vunmap)
13181318 dmabuf->ops->vunmap(dmabuf, map);
1319− dma_buf_map_clear(&dmabuf->vmap_ptr);
1319+ iosys_map_clear(&dmabuf->vmap_ptr);
13201320 }
13211321 mutex_unlock(&dmabuf->lock);
13221322 }
drivers/dma-buf/dma-fence-array.c+14−0
@@ -176,6 +176,20 @@ struct dma_fence_array *dma_fence_array_create(int num_fences, · 175 unmodified lines
176176
177177 array->base.error = PENDING_ERROR;
178178
179+ /*
180+ * dma_fence_array objects should never contain any other fence
181+ * containers or otherwise we run into recursion and potential kernel
182+ * stack overflow on operations on the dma_fence_array.
183+ *
184+ * The correct way of handling this is to flatten out the array by the
185+ * caller instead.
186+ *
187+ * Enforce this here by checking that we don't create a dma_fence_array
188+ * with any container inside.
189+ */
190+ while (num_fences--)
191+ WARN_ON(dma_fence_is_container(fences[num_fences]));
192+
179193 return array;
180194 }
181195 EXPORT_SYMBOL(dma_fence_array_create);
drivers/dma-buf/dma-fence-chain.c+11−4
@@ -148,8 +148,7 @@ static bool dma_fence_chain_enable_signaling(struct dma_fence *fence) · 147 unmodified lines
148148
149149 dma_fence_get(&head->base);
150150 dma_fence_chain_for_each(fence, &head->base) {
151− struct dma_fence_chain *chain = to_dma_fence_chain(fence);
152− struct dma_fence *f = chain ? chain->fence : fence;
151+ struct dma_fence *f = dma_fence_chain_contained(fence);
153152
154153 dma_fence_get(f);
155154 if (!dma_fence_add_callback(f, &head->cb, dma_fence_chain_cb)) {
@@ -165,8 +164,7 @@ static bool dma_fence_chain_enable_signaling(struct dma_fence *fence) · 9 unmodified lines
165164 static bool dma_fence_chain_signaled(struct dma_fence *fence)
166165 {
167166 dma_fence_chain_for_each(fence, fence) {
168− struct dma_fence_chain *chain = to_dma_fence_chain(fence);
169− struct dma_fence *f = chain ? chain->fence : fence;
167+ struct dma_fence *f = dma_fence_chain_contained(fence);
170168
171169 if (!dma_fence_is_signaled(f)) {
172170 dma_fence_put(fence);
@@ -254,5 +252,14 @@ void dma_fence_chain_init(struct dma_fence_chain *chain, · 81 unmodified lines
254252
255253 dma_fence_init(&chain->base, &dma_fence_chain_ops,
256254 &chain->lock, context, seqno);
255+
256+ /*
257+ * Chaining dma_fence_chain container together is only allowed through
258+ * the prev fence and not through the contained fence.
259+ *
260+ * The correct way of handling this is to flatten out the fence
261+ * structure into a dma_fence_array by the caller instead.
262+ */
263+ WARN_ON(dma_fence_is_chain(fence));
257264 }
258265 EXPORT_SYMBOL(dma_fence_chain_init);
drivers/dma-buf/dma-heap.c+2−0
@@ -14,6 +14,7 @@ · 13 unmodified lines
1414 #include <linux/xarray.h>
1515 #include <linux/list.h>
1616 #include <linux/slab.h>
17+#include <linux/nospec.h>
1718 #include <linux/uaccess.h>
1819 #include <linux/syscalls.h>
1920 #include <linux/dma-heap.h>
@@ -135,6 +136,7 @@ static long dma_heap_ioctl(struct file *file, unsigned int ucmd, · 115 unmodified lines
135136 if (nr >= ARRAY_SIZE(dma_heap_ioctl_cmds))
136137 return -EINVAL;
137138
139+ nr = array_index_nospec(nr, ARRAY_SIZE(dma_heap_ioctl_cmds));
138140 /* Get the kernel ioctl cmd that matches */
139141 kcmd = dma_heap_ioctl_cmds[nr];
140142
drivers/dma-buf/dma-resv.c+20−14
@@ -256,6 +256,11 @@ void dma_resv_add_shared_fence(struct dma_resv *obj, struct dma_fence *fence) · 255 unmodified lines
256256
257257 dma_resv_assert_held(obj);
258258
259+ /* Drivers should not add containers here, instead add each fence
260+ * individually.
261+ */
262+ WARN_ON(dma_fence_is_container(fence));
263+
259264 fobj = dma_resv_shared_list(obj);
260265 count = fobj->shared_count;
261266
@@ -323,12 +328,8 @@ void dma_resv_add_excl_fence(struct dma_resv *obj, struct dma_fence *fence) · 61 unmodified lines
323328 }
324329 EXPORT_SYMBOL(dma_resv_add_excl_fence);
325330
326−/**
327− * dma_resv_iter_restart_unlocked - restart the unlocked iterator
328− * @cursor: The dma_resv_iter object to restart
329− *
330− * Restart the unlocked iteration by initializing the cursor object.
331− */
331+/* Restart the iterator by initializing all the necessary fields, but not the
332+ * relation to the dma_resv object. */
332333 static void dma_resv_iter_restart_unlocked(struct dma_resv_iter *cursor)
333334 {
334335 cursor->seq = read_seqcount_begin(&cursor->obj->seq);
@@ -344,14 +345,7 @@ static void dma_resv_iter_restart_unlocked(struct dma_resv_iter *cursor) · 9 unmodified lines
344345 cursor->is_restarted = true;
345346 }
346347
347−/**
348− * dma_resv_iter_walk_unlocked - walk over fences in a dma_resv obj
349− * @cursor: cursor to record the current position
350− *
351− * Return all the fences in the dma_resv object which are not yet signaled.
352− * The returned fence has an extra local reference so will stay alive.
353− * If a concurrent modify is detected the whole iteration is started over again.
354− */
348+/* Walk to the next not signaled fence and grab a reference to it */
355349 static void dma_resv_iter_walk_unlocked(struct dma_resv_iter *cursor)
356350 {
357351 struct dma_resv *obj = cursor->obj;
@@ -387,6 +381,12 @@ static void dma_resv_iter_walk_unlocked(struct dma_resv_iter *cursor) · 29 unmodified lines
387381 * dma_resv_iter_first_unlocked - first fence in an unlocked dma_resv obj.
388382 * @cursor: the cursor with the current position
389383 *
384+ * Subsequent fences are iterated with dma_resv_iter_next_unlocked().
385+ *
386+ * Beware that the iterator can be restarted. Code which accumulates statistics
387+ * or similar needs to check for this with dma_resv_iter_is_restarted(). For
388+ * this reason prefer the locked dma_resv_iter_first() whenver possible.
389+ *
390390 * Returns the first fence from an unlocked dma_resv obj.
391391 */
392392 struct dma_fence *dma_resv_iter_first_unlocked(struct dma_resv_iter *cursor)
@@ -406,6 +406,10 @@ EXPORT_SYMBOL(dma_resv_iter_first_unlocked); · 13 unmodified lines
406406 * dma_resv_iter_next_unlocked - next fence in an unlocked dma_resv obj.
407407 * @cursor: the cursor with the current position
408408 *
409+ * Beware that the iterator can be restarted. Code which accumulates statistics
410+ * or similar needs to check for this with dma_resv_iter_is_restarted(). For
411+ * this reason prefer the locked dma_resv_iter_next() whenver possible.
412+ *
409413 * Returns the next fence from an unlocked dma_resv obj.
410414 */
411415 struct dma_fence *dma_resv_iter_next_unlocked(struct dma_resv_iter *cursor)
@@ -431,6 +435,8 @@ EXPORT_SYMBOL(dma_resv_iter_next_unlocked); · 19 unmodified lines
431435 * dma_resv_iter_first - first fence from a locked dma_resv object
432436 * @cursor: cursor to record the current position
433437 *
438+ * Subsequent fences are iterated with dma_resv_iter_next_unlocked().
439+ *
434440 * Return the first fence in the dma_resv object while holding the
435441 * &dma_resv.lock.
436442 */
drivers/dma-buf/heaps/cma_heap.c+5−5
@@ -202,7 +202,7 @@ static void *cma_heap_do_vmap(struct cma_heap_buffer *buffer) · 201 unmodified lines
202202 return vaddr;
203203 }
204204
205−static int cma_heap_vmap(struct dma_buf *dmabuf, struct dma_buf_map *map)
205+static int cma_heap_vmap(struct dma_buf *dmabuf, struct iosys_map *map)
206206 {
207207 struct cma_heap_buffer *buffer = dmabuf->priv;
208208 void *vaddr;
@@ -211,7 +211,7 @@ static int cma_heap_vmap(struct dma_buf *dmabuf, struct dma_buf_map *map) · 2 unmodified lines
211211 mutex_lock(&buffer->lock);
212212 if (buffer->vmap_cnt) {
213213 buffer->vmap_cnt++;
214− dma_buf_map_set_vaddr(map, buffer->vaddr);
214+ iosys_map_set_vaddr(map, buffer->vaddr);
215215 goto out;
216216 }
217217
@@ -222,14 +222,14 @@ static int cma_heap_vmap(struct dma_buf *dmabuf, struct dma_buf_map *map) · 4 unmodified lines
222222 }
223223 buffer->vaddr = vaddr;
224224 buffer->vmap_cnt++;
225− dma_buf_map_set_vaddr(map, buffer->vaddr);
225+ iosys_map_set_vaddr(map, buffer->vaddr);
226226 out:
227227 mutex_unlock(&buffer->lock);
228228
229229 return ret;
230230 }
231231
232−static void cma_heap_vunmap(struct dma_buf *dmabuf, struct dma_buf_map *map)
232+static void cma_heap_vunmap(struct dma_buf *dmabuf, struct iosys_map *map)
233233 {
234234 struct cma_heap_buffer *buffer = dmabuf->priv;
235235
@@ -239,7 +239,7 @@ static void cma_heap_vunmap(struct dma_buf *dmabuf, struct dma_buf_map *map) · 3 unmodified lines
239239 buffer->vaddr = NULL;
240240 }
241241 mutex_unlock(&buffer->lock);
242− dma_buf_map_clear(map);
242+ iosys_map_clear(map);
243243 }
244244
245245 static void cma_heap_dma_buf_release(struct dma_buf *dmabuf)
drivers/dma-buf/heaps/system_heap.c+5−5
@@ -241,7 +241,7 @@ static void *system_heap_do_vmap(struct system_heap_buffer *buffer) · 240 unmodified lines
241241 return vaddr;
242242 }
243243
244−static int system_heap_vmap(struct dma_buf *dmabuf, struct dma_buf_map *map)
244+static int system_heap_vmap(struct dma_buf *dmabuf, struct iosys_map *map)
245245 {
246246 struct system_heap_buffer *buffer = dmabuf->priv;
247247 void *vaddr;
@@ -250,7 +250,7 @@ static int system_heap_vmap(struct dma_buf *dmabuf, struct dma_buf_map *map) · 2 unmodified lines
250250 mutex_lock(&buffer->lock);
251251 if (buffer->vmap_cnt) {
252252 buffer->vmap_cnt++;
253− dma_buf_map_set_vaddr(map, buffer->vaddr);
253+ iosys_map_set_vaddr(map, buffer->vaddr);
254254 goto out;
255255 }
256256
@@ -262,14 +262,14 @@ static int system_heap_vmap(struct dma_buf *dmabuf, struct dma_buf_map *map) · 5 unmodified lines
262262
263263 buffer->vaddr = vaddr;
264264 buffer->vmap_cnt++;
265− dma_buf_map_set_vaddr(map, buffer->vaddr);
265+ iosys_map_set_vaddr(map, buffer->vaddr);
266266 out:
267267 mutex_unlock(&buffer->lock);
268268
269269 return ret;
270270 }
271271
272−static void system_heap_vunmap(struct dma_buf *dmabuf, struct dma_buf_map *map)
272+static void system_heap_vunmap(struct dma_buf *dmabuf, struct iosys_map *map)
273273 {
274274 struct system_heap_buffer *buffer = dmabuf->priv;
275275
@@ -279,7 +279,7 @@ static void system_heap_vunmap(struct dma_buf *dmabuf, struct dma_buf_map *map) · 3 unmodified lines
279279 buffer->vaddr = NULL;
280280 }
281281 mutex_unlock(&buffer->lock);
282− dma_buf_map_clear(map);
282+ iosys_map_clear(map);
283283 }
284284
285285 static void system_heap_dma_buf_release(struct dma_buf *dmabuf)
drivers/edac/altera_edac.c+1−1
@@ -350,7 +350,7 @@ static int altr_sdram_probe(struct platform_device *pdev) · 349 unmodified lines
350350 if (irq < 0) {
351351 edac_printk(KERN_ERR, EDAC_MC,
352352 "No irq %d in DT\n", irq);
353− return -ENODEV;
353+ return irq;
354354 }
355355
356356 /* Arria10 has a 2nd IRQ */
drivers/edac/xgene_edac.c+1−1
@@ -1919,7 +1919,7 @@ static int xgene_edac_probe(struct platform_device *pdev) · 1918 unmodified lines
19191919 irq = platform_get_irq_optional(pdev, i);
19201920 if (irq < 0) {
19211921 dev_err(&pdev->dev, "No IRQ resource\n");
1922− rc = -EINVAL;
1922+ rc = irq;
19231923 goto out_err;
19241924 }
19251925 rc = devm_request_irq(&pdev->dev, irq,
drivers/gpio/gpio-aggregator.c+14−4
@@ -278,7 +278,8 @@ static int gpio_fwd_get(struct gpio_chip *chip, unsigned int offset) · 277 unmodified lines
278278 {
279279 struct gpiochip_fwd *fwd = gpiochip_get_data(chip);
280280
281− return gpiod_get_value(fwd->descs[offset]);
281+ return chip->can_sleep ? gpiod_get_value_cansleep(fwd->descs[offset])
282+ : gpiod_get_value(fwd->descs[offset]);
282283 }
283284
284285 static int gpio_fwd_get_multiple(struct gpiochip_fwd *fwd, unsigned long *mask,
@@ -293,7 +294,10 @@ static int gpio_fwd_get_multiple(struct gpiochip_fwd *fwd, unsigned long *mask, · 8 unmodified lines
293294 for_each_set_bit(i, mask, fwd->chip.ngpio)
294295 descs[j++] = fwd->descs[i];
295296
296− error = gpiod_get_array_value(j, descs, NULL, values);
297+ if (fwd->chip.can_sleep)
298+ error = gpiod_get_array_value_cansleep(j, descs, NULL, values);
299+ else
300+ error = gpiod_get_array_value(j, descs, NULL, values);
297301 if (error)
298302 return error;
299303
@@ -328,7 +332,10 @@ static void gpio_fwd_set(struct gpio_chip *chip, unsigned int offset, int value) · 28 unmodified lines
328332 {
329333 struct gpiochip_fwd *fwd = gpiochip_get_data(chip);
330334
331− gpiod_set_value(fwd->descs[offset], value);
335+ if (chip->can_sleep)
336+ gpiod_set_value_cansleep(fwd->descs[offset], value);
337+ else
338+ gpiod_set_value(fwd->descs[offset], value);
332339 }
333340
334341 static void gpio_fwd_set_multiple(struct gpiochip_fwd *fwd, unsigned long *mask,
@@ -343,7 +350,10 @@ static void gpio_fwd_set_multiple(struct gpiochip_fwd *fwd, unsigned long *mask, · 8 unmodified lines
343350 descs[j++] = fwd->descs[i];
344351 }
345352
346− gpiod_set_array_value(j, descs, NULL, values);
353+ if (fwd->chip.can_sleep)
354+ gpiod_set_array_value_cansleep(j, descs, NULL, values);
355+ else
356+ gpiod_set_array_value(j, descs, NULL, values);
347357 }
348358
349359 static void gpio_fwd_set_multiple_locked(struct gpio_chip *chip,
drivers/gpio/gpio-sifive.c+1−1
@@ -223,7 +223,7 @@ static int sifive_gpio_probe(struct platform_device *pdev) · 222 unmodified lines
223223 NULL,
224224 chip->base + SIFIVE_GPIO_OUTPUT_EN,
225225 chip->base + SIFIVE_GPIO_INPUT_EN,
226− 0);
226+ BGPIOF_READ_OUTPUT_REG_SET);
227227 if (ret) {
228228 dev_err(dev, "unable to init generic GPIO\n");
229229 return ret;
drivers/gpio/gpio-sim.c+15−4
@@ -570,6 +570,11 @@ static struct gpio_sim_bank *to_gpio_sim_bank(struct config_item *item) · 569 unmodified lines
570570 return container_of(group, struct gpio_sim_bank, group);
571571 }
572572
573+static bool gpio_sim_bank_has_label(struct gpio_sim_bank *bank)
574+{
575+ return bank->label && *bank->label;
576+}
577+
573578 static struct gpio_sim_device *
574579 gpio_sim_bank_get_device(struct gpio_sim_bank *bank)
575580 {
@@ -770,9 +775,15 @@ static int gpio_sim_add_hogs(struct gpio_sim_device *dev) · 194 unmodified lines
770775 * point the device doesn't exist yet and so dev_name()
771776 * is not available.
772777 */
773− hog->chip_label = kasprintf(GFP_KERNEL,
774− "gpio-sim.%u-%s", dev->id,
775− fwnode_get_name(bank->swnode));
778+ if (gpio_sim_bank_has_label(bank))
779+ hog->chip_label = kstrdup(bank->label,
780+ GFP_KERNEL);
781+ else
782+ hog->chip_label = kasprintf(GFP_KERNEL,
783+ "gpio-sim.%u-%s",
784+ dev->id,
785+ fwnode_get_name(
786+ bank->swnode));
776787 if (!hog->chip_label) {
777788 gpio_sim_remove_hogs(dev);
778789 return -ENOMEM;
@@ -816,7 +827,7 @@ gpio_sim_make_bank_swnode(struct gpio_sim_bank *bank, · 37 unmodified lines
816827
817828 properties[prop_idx++] = PROPERTY_ENTRY_U32("ngpios", bank->num_lines);
818829
819− if (bank->label && (strlen(bank->label) > 0))
830+ if (gpio_sim_bank_has_label(bank))
820831 properties[prop_idx++] = PROPERTY_ENTRY_STRING("gpio-sim,label",
821832 bank->label);
822833
drivers/gpio/gpiolib-cdev.c+3−3
@@ -330,7 +330,7 @@ static int linehandle_create(struct gpio_device *gdev, void __user *ip) · 329 unmodified lines
330330 goto out_free_lh;
331331 }
332332
333− ret = gpiod_request(desc, lh->label);
333+ ret = gpiod_request_user(desc, lh->label);
334334 if (ret)
335335 goto out_free_lh;
336336 lh->descs[i] = desc;
@@ -1378,7 +1378,7 @@ static int linereq_create(struct gpio_device *gdev, void __user *ip) · 1041 unmodified lines
13781378 goto out_free_linereq;
13791379 }
13801380
1381− ret = gpiod_request(desc, lr->label);
1381+ ret = gpiod_request_user(desc, lr->label);
13821382 if (ret)
13831383 goto out_free_linereq;
13841384
@@ -1764,7 +1764,7 @@ static int lineevent_create(struct gpio_device *gdev, void __user *ip) · 379 unmodified lines
17641764 }
17651765 }
17661766
1767− ret = gpiod_request(desc, le->label);
1767+ ret = gpiod_request_user(desc, le->label);
17681768 if (ret)
17691769 goto out_free_le;
17701770 le->desc = desc;
drivers/gpio/gpiolib-sysfs.c+2−5
@@ -475,12 +475,9 @@ static ssize_t export_store(struct class *class, · 474 unmodified lines
475475 * they may be undone on its behalf too.
476476 */
477477
478− status = gpiod_request(desc, "sysfs");
479− if (status) {
480− if (status == -EPROBE_DEFER)
481− status = -ENODEV;
478+ status = gpiod_request_user(desc, "sysfs");
479+ if (status)
482480 goto done;
483− }
484481
485482 status = gpiod_set_transitory(desc, false);
486483 if (!status) {
drivers/gpio/gpiolib.h+12−0
@@ -135,6 +135,18 @@ struct gpio_desc { · 134 unmodified lines
135135
136136 int gpiod_request(struct gpio_desc *desc, const char *label);
137137 void gpiod_free(struct gpio_desc *desc);
138+
139+static inline int gpiod_request_user(struct gpio_desc *desc, const char *label)
140+{
141+ int ret;
142+
143+ ret = gpiod_request(desc, label);
144+ if (ret == -EPROBE_DEFER)
145+ ret = -ENODEV;
146+
147+ return ret;
148+}
149+
138150 int gpiod_configure_flags(struct gpio_desc *desc, const char *con_id,
139151 unsigned long lflags, enum gpiod_flags dflags);
140152 int gpio_set_debounce_timeout(struct gpio_desc *desc, unsigned int debounce);
drivers/gpu/drm/Kconfig+3−0
@@ -71,6 +71,7 @@ config DRM_DEBUG_SELFTEST · 70 unmodified lines
7171 select DRM_DP_HELPER
7272 select DRM_LIB_RANDOM
7373 select DRM_KMS_HELPER
74+ select DRM_BUDDY
7475 select DRM_EXPORT_FOR_TESTS if m
7576 default n
7677 help
@@ -403,6 +404,8 @@ source "drivers/gpu/drm/xlnx/Kconfig" · 326 unmodified lines
403404
404405 source "drivers/gpu/drm/gud/Kconfig"
405406
407+source "drivers/gpu/drm/solomon/Kconfig"
408+
406409 source "drivers/gpu/drm/sprd/Kconfig"
407410
408411 config DRM_HYPERV
drivers/gpu/drm/Makefile+1−0
@@ -132,4 +132,5 @@ obj-$(CONFIG_DRM_TIDSS) += tidss/ · 131 unmodified lines
132132 obj-y += xlnx/
133133 obj-y += gud/
134134 obj-$(CONFIG_DRM_HYPERV) += hyperv/
135+obj-y += solomon/
135136 obj-$(CONFIG_DRM_SPRD) += sprd/
drivers/gpu/drm/amd/amdgpu/aldebaran.c+1−1
@@ -260,7 +260,7 @@ static int aldebaran_mode2_restore_ip(struct amdgpu_device *adev) · 259 unmodified lines
260260 adev->gfx.rlc.funcs->resume(adev);
261261
262262 /* Wait for FW reset event complete */
263− r = smu_wait_for_event(adev, SMU_EVENT_RESET_COMPLETE, 0);
263+ r = amdgpu_dpm_wait_for_event(adev, SMU_EVENT_RESET_COMPLETE, 0);
264264 if (r) {
265265 dev_err(adev->dev,
266266 "Failed to get response from firmware after reset\n");
drivers/gpu/drm/amd/amdgpu/amdgpu.h+39−17
@@ -99,7 +99,6 @@ · 98 unmodified lines
9999 #include "amdgpu_gem.h"
100100 #include "amdgpu_doorbell.h"
101101 #include "amdgpu_amdkfd.h"
102−#include "amdgpu_smu.h"
103102 #include "amdgpu_discovery.h"
104103 #include "amdgpu_mes.h"
105104 #include "amdgpu_umc.h"
@@ -109,6 +108,7 @@ · 3 unmodified lines
109108 #include "amdgpu_smuio.h"
110109 #include "amdgpu_fdinfo.h"
111110 #include "amdgpu_mca.h"
111+#include "amdgpu_ras.h"
112112
113113 #define MAX_GPU_INSTANCE 16
114114
@@ -197,7 +197,6 @@ extern int amdgpu_emu_mode; · 82 unmodified lines
197197 extern uint amdgpu_smu_memory_pool_size;
198198 extern int amdgpu_smu_pptable_id;
199199 extern uint amdgpu_dc_feature_mask;
200−extern uint amdgpu_freesync_vid_mode;
201200 extern uint amdgpu_dc_debug_mask;
202201 extern uint amdgpu_dm_abm_level;
203202 extern int amdgpu_backlight;
@@ -373,7 +372,8 @@ int amdgpu_device_ip_block_add(struct amdgpu_device *adev, · 169 unmodified lines
373372 */
374373 bool amdgpu_get_bios(struct amdgpu_device *adev);
375374 bool amdgpu_read_bios(struct amdgpu_device *adev);
376−
375+bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev,
376+ u8 *bios, u32 length_bytes);
377377 /*
378378 * Clocks
379379 */
@@ -771,6 +771,8 @@ struct amd_powerplay { · 391 unmodified lines
771771 const struct amd_pm_funcs *pp_funcs;
772772 };
773773
774+struct ip_discovery_top;
775+
774776 /* polaris10 kickers */
775777 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \
776778 ((rid == 0xE3) || \
@@ -813,6 +815,8 @@ struct amd_powerplay { · 36 unmodified lines
813815 #define AMDGPU_RESET_MAGIC_NUM 64
814816 #define AMDGPU_MAX_DF_PERFMONS 4
815817 #define AMDGPU_PRODUCT_NAME_LEN 64
818+struct amdgpu_reset_domain;
819+
816820 struct amdgpu_device {
817821 struct device *dev;
818822 struct pci_dev *pdev;
@@ -950,12 +954,6 @@ struct amdgpu_device { · 131 unmodified lines
950954
951955 /* powerplay */
952956 struct amd_powerplay powerplay;
953− bool pp_force_state_enabled;
954−
955− /* smu */
956− struct smu_context smu;
957−
958− /* dpm */
959957 struct amdgpu_pm pm;
960958 u32 cg_flags;
961959 u32 pg_flags;
@@ -1054,9 +1052,7 @@ struct amdgpu_device { · 92 unmodified lines
10541052 bool in_s4;
10551053 bool in_s0ix;
10561054
1057− atomic_t in_gpu_reset;
10581055 enum pp_mp1_state mp1_state;
1059− struct rw_semaphore reset_sem;
10601056 struct amdgpu_doorbell_index doorbell_index;
10611057
10621058 struct mutex notifier_lock;
@@ -1100,6 +1096,12 @@ struct amdgpu_device { · 37 unmodified lines
11001096 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE];
11011097
11021098 bool ram_is_direct_mapped;
1099+
1100+ struct list_head ras_list;
1101+
1102+ struct ip_discovery_top *ip_top;
1103+
1104+ struct amdgpu_reset_domain *reset_domain;
11031105 };
11041106
11051107 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
@@ -1293,9 +1295,12 @@ bool amdgpu_device_has_job_running(struct amdgpu_device *adev); · 187 unmodified lines
12931295 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
12941296 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
12951297 struct amdgpu_job* job);
1298+int amdgpu_device_gpu_recover_imp(struct amdgpu_device *adev,
1299+ struct amdgpu_job *job);
12961300 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
12971301 int amdgpu_device_pci_reset(struct amdgpu_device *adev);
12981302 bool amdgpu_device_need_post(struct amdgpu_device *adev);
1303+bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev);
12991304
13001305 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
13011306 u64 num_vis_bytes);
@@ -1321,6 +1326,10 @@ void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, · 19 unmodified lines
13211326 struct amdgpu_ring *ring);
13221327
13231328 void amdgpu_device_halt(struct amdgpu_device *adev);
1329+u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev,
1330+ u32 reg);
1331+void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev,
1332+ u32 reg, u32 v);
13241333
13251334 /* atpx handler */
13261335 #if defined(CONFIG_VGA_SWITCHEROO)
@@ -1408,12 +1417,10 @@ int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_sta · 81 unmodified lines
14081417 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
14091418
14101419 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps);
1411−bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev);
14121420 void amdgpu_acpi_detect(void);
14131421 #else
14141422 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
14151423 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1416−static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; }
14171424 static inline void amdgpu_acpi_detect(void) { }
14181425 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; }
14191426 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
@@ -1422,6 +1429,14 @@ static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev, · 2 unmodified lines
14221429 enum amdgpu_ss ss_state) { return 0; }
14231430 #endif
14241431
1432+#if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND)
1433+bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev);
1434+bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev);
1435+#else
1436+static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; }
1437+static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; }
1438+#endif
1439+
14251440 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
14261441 uint64_t addr, struct amdgpu_bo **bo,
14271442 struct amdgpu_bo_va_mapping **mapping);
@@ -1452,6 +1467,15 @@ int amdgpu_device_set_cg_state(struct amdgpu_device *adev, · 24 unmodified lines
14521467 int amdgpu_device_set_pg_state(struct amdgpu_device *adev,
14531468 enum amd_powergating_state state);
14541469
1470+static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev)
1471+{
1472+ return amdgpu_gpu_recovery != 0 &&
1473+ adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT &&
1474+ adev->compute_timeout != MAX_SCHEDULE_TIMEOUT &&
1475+ adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT &&
1476+ adev->video_timeout != MAX_SCHEDULE_TIMEOUT;
1477+}
1478+
14551479 #include "amdgpu_object.h"
14561480
14571481 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev)
@@ -1459,8 +1483,6 @@ static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) · 1 unmodified line
14591483 return adev->gmc.tmz_enabled;
14601484 }
14611485
1462−static inline int amdgpu_in_reset(struct amdgpu_device *adev)
1463−{
1464− return atomic_read(&adev->in_gpu_reset);
1465−}
1486+int amdgpu_in_reset(struct amdgpu_device *adev);
1487+
14661488 #endif
drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c+32−5
@@ -1031,6 +1031,20 @@ void amdgpu_acpi_detect(void) · 1030 unmodified lines
10311031 }
10321032 }
10331033
1034+#if IS_ENABLED(CONFIG_SUSPEND)
1035+/**
1036+ * amdgpu_acpi_is_s3_active
1037+ *
1038+ * @adev: amdgpu_device_pointer
1039+ *
1040+ * returns true if supported, false if not.
1041+ */
1042+bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev)
1043+{
1044+ return !(adev->flags & AMD_IS_APU) ||
1045+ (pm_suspend_target_state == PM_SUSPEND_MEM);
1046+}
1047+
10341048 /**
10351049 * amdgpu_acpi_is_s0ix_active
10361050 *
@@ -1040,11 +1054,24 @@ void amdgpu_acpi_detect(void) · 3 unmodified lines
10401054 */
10411055 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev)
10421056 {
1043−#if IS_ENABLED(CONFIG_AMD_PMC) && IS_ENABLED(CONFIG_SUSPEND)
1044− if (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0) {
1045− if (adev->flags & AMD_IS_APU)
1046− return pm_suspend_target_state == PM_SUSPEND_TO_IDLE;
1057+ if (!(adev->flags & AMD_IS_APU) ||
1058+ (pm_suspend_target_state != PM_SUSPEND_TO_IDLE))
1059+ return false;
1060+
1061+ if (!(acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) {
1062+ dev_warn_once(adev->dev,
1063+ "Power consumption will be higher as BIOS has not been configured for suspend-to-idle.\n"
1064+ "To use suspend-to-idle change the sleep mode in BIOS setup.\n");
1065+ return false;
10471066 }
1048−#endif
1067+
1068+#if !IS_ENABLED(CONFIG_AMD_PMC)
1069+ dev_warn_once(adev->dev,
1070+ "Power consumption will be higher as the kernel has not been compiled with CONFIG_AMD_PMC.\n");
10491071 return false;
1072+#else
1073+ return true;
1074+#endif /* CONFIG_AMD_PMC */
10501075 }
1076+
1077+#endif /* CONFIG_SUSPEND */
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h+6−1
@@ -131,6 +131,7 @@ struct amdkfd_process_info { · 130 unmodified lines
131131 atomic_t evicted_bos;
132132 struct delayed_work restore_userptr_work;
133133 struct pid *pid;
134+ bool block_mmu_notifications;
134135 };
135136
136137 int amdgpu_amdkfd_init(void);
@@ -268,7 +269,7 @@ uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv); · 131 unmodified lines
268269 int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
269270 struct amdgpu_device *adev, uint64_t va, uint64_t size,
270271 void *drm_priv, struct kgd_mem **mem,
271− uint64_t *offset, uint32_t flags);
272+ uint64_t *offset, uint32_t flags, bool criu_resume);
272273 int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
273274 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv,
274275 uint64_t *size);
@@ -297,6 +298,10 @@ int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev, · 22 unmodified lines
297298 struct tile_config *config);
298299 void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev,
299300 bool reset);
301+bool amdgpu_amdkfd_bo_mapped_to_dev(struct amdgpu_device *adev, struct kgd_mem *mem);
302+void amdgpu_amdkfd_block_mmu_notifications(void *p);
303+int amdgpu_amdkfd_criu_resume(void *p);
304+
300305 #if IS_ENABLED(CONFIG_HSA_AMD)
301306 void amdgpu_amdkfd_gpuvm_init_mem_limits(void);
302307 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c+0−3
@@ -37,10 +37,7 @@ const struct kfd2kgd_calls aldebaran_kfd2kgd = { · 36 unmodified lines
3737 .hqd_sdma_is_occupied = kgd_arcturus_hqd_sdma_is_occupied,
3838 .hqd_destroy = kgd_gfx_v9_hqd_destroy,
3939 .hqd_sdma_destroy = kgd_arcturus_hqd_sdma_destroy,
40− .address_watch_disable = kgd_gfx_v9_address_watch_disable,
41− .address_watch_execute = kgd_gfx_v9_address_watch_execute,
4240 .wave_control_execute = kgd_gfx_v9_wave_control_execute,
43− .address_watch_get_offset = kgd_gfx_v9_address_watch_get_offset,
4441 .get_atc_vmid_pasid_mapping_info =
4542 kgd_gfx_v9_get_atc_vmid_pasid_mapping_info,
4643 .set_vm_context_page_table_base = kgd_gfx_v9_set_vm_context_page_table_base,
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c+0−3
@@ -289,10 +289,7 @@ const struct kfd2kgd_calls arcturus_kfd2kgd = { · 288 unmodified lines
289289 .hqd_sdma_is_occupied = kgd_arcturus_hqd_sdma_is_occupied,
290290 .hqd_destroy = kgd_gfx_v9_hqd_destroy,
291291 .hqd_sdma_destroy = kgd_arcturus_hqd_sdma_destroy,
292− .address_watch_disable = kgd_gfx_v9_address_watch_disable,
293− .address_watch_execute = kgd_gfx_v9_address_watch_execute,
294292 .wave_control_execute = kgd_gfx_v9_wave_control_execute,
295− .address_watch_get_offset = kgd_gfx_v9_address_watch_get_offset,
296293 .get_atc_vmid_pasid_mapping_info =
297294 kgd_gfx_v9_get_atc_vmid_pasid_mapping_info,
298295 .set_vm_context_page_table_base =
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c+0−24
@@ -671,20 +671,6 @@ static bool get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev, · 670 unmodified lines
671671 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
672672 }
673673
674−static int kgd_address_watch_disable(struct amdgpu_device *adev)
675−{
676− return 0;
677−}
678−
679−static int kgd_address_watch_execute(struct amdgpu_device *adev,
680− unsigned int watch_point_id,
681− uint32_t cntl_val,
682− uint32_t addr_hi,
683− uint32_t addr_lo)
684−{
685− return 0;
686−}
687−
688674 static int kgd_wave_control_execute(struct amdgpu_device *adev,
689675 uint32_t gfx_index_val,
690676 uint32_t sq_cmd)
@@ -709,13 +695,6 @@ static int kgd_wave_control_execute(struct amdgpu_device *adev, · 18 unmodified lines
709695 return 0;
710696 }
711697
712−static uint32_t kgd_address_watch_get_offset(struct amdgpu_device *adev,
713− unsigned int watch_point_id,
714− unsigned int reg_offset)
715−{
716− return 0;
717−}
718−
719698 static void set_vm_context_page_table_base(struct amdgpu_device *adev,
720699 uint32_t vmid, uint64_t page_table_base)
721700 {
@@ -767,10 +746,7 @@ const struct kfd2kgd_calls gfx_v10_kfd2kgd = { · 45 unmodified lines
767746 .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
768747 .hqd_destroy = kgd_hqd_destroy,
769748 .hqd_sdma_destroy = kgd_hqd_sdma_destroy,
770− .address_watch_disable = kgd_address_watch_disable,
771− .address_watch_execute = kgd_address_watch_execute,
772749 .wave_control_execute = kgd_wave_control_execute,
773− .address_watch_get_offset = kgd_address_watch_get_offset,
774750 .get_atc_vmid_pasid_mapping_info =
775751 get_atc_vmid_pasid_mapping_info,
776752 .set_vm_context_page_table_base = set_vm_context_page_table_base,
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c+0−25
@@ -582,21 +582,6 @@ static int hqd_sdma_destroy_v10_3(struct amdgpu_device *adev, void *mqd, · 581 unmodified lines
582582 return 0;
583583 }
584584
585−
586−static int address_watch_disable_v10_3(struct amdgpu_device *adev)
587−{
588− return 0;
589−}
590−
591−static int address_watch_execute_v10_3(struct amdgpu_device *adev,
592− unsigned int watch_point_id,
593− uint32_t cntl_val,
594− uint32_t addr_hi,
595− uint32_t addr_lo)
596−{
597− return 0;
598−}
599−
600585 static int wave_control_execute_v10_3(struct amdgpu_device *adev,
601586 uint32_t gfx_index_val,
602587 uint32_t sq_cmd)
@@ -621,13 +606,6 @@ static int wave_control_execute_v10_3(struct amdgpu_device *adev, · 18 unmodified lines
621606 return 0;
622607 }
623608
624−static uint32_t address_watch_get_offset_v10_3(struct amdgpu_device *adev,
625− unsigned int watch_point_id,
626− unsigned int reg_offset)
627−{
628− return 0;
629−}
630−
631609 static void set_vm_context_page_table_base_v10_3(struct amdgpu_device *adev,
632610 uint32_t vmid, uint64_t page_table_base)
633611 {
@@ -809,10 +787,7 @@ const struct kfd2kgd_calls gfx_v10_3_kfd2kgd = { · 175 unmodified lines
809787 .hqd_sdma_is_occupied = hqd_sdma_is_occupied_v10_3,
810788 .hqd_destroy = hqd_destroy_v10_3,
811789 .hqd_sdma_destroy = hqd_sdma_destroy_v10_3,
812− .address_watch_disable = address_watch_disable_v10_3,
813− .address_watch_execute = address_watch_execute_v10_3,
814790 .wave_control_execute = wave_control_execute_v10_3,
815− .address_watch_get_offset = address_watch_get_offset_v10_3,
816791 .get_atc_vmid_pasid_mapping_info = NULL,
817792 .set_vm_context_page_table_base = set_vm_context_page_table_base_v10_3,
818793 .program_trap_handler_settings = program_trap_handler_settings_v10_3,
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c+0−96
@@ -45,43 +45,6 @@ enum { · 44 unmodified lines
4545 MAX_WATCH_ADDRESSES = 4
4646 };
4747
48−enum {
49− ADDRESS_WATCH_REG_ADDR_HI = 0,
50− ADDRESS_WATCH_REG_ADDR_LO,
51− ADDRESS_WATCH_REG_CNTL,
52− ADDRESS_WATCH_REG_MAX
53−};
54−
55−/* not defined in the CI/KV reg file */
56−enum {
57− ADDRESS_WATCH_REG_CNTL_ATC_BIT = 0x10000000UL,
58− ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK = 0x00FFFFFF,
59− ADDRESS_WATCH_REG_ADDLOW_MASK_EXTENSION = 0x03000000,
60− /* extend the mask to 26 bits to match the low address field */
61− ADDRESS_WATCH_REG_ADDLOW_SHIFT = 6,
62− ADDRESS_WATCH_REG_ADDHIGH_MASK = 0xFFFF
63−};
64−
65−static const uint32_t watchRegs[MAX_WATCH_ADDRESSES * ADDRESS_WATCH_REG_MAX] = {
66− mmTCP_WATCH0_ADDR_H, mmTCP_WATCH0_ADDR_L, mmTCP_WATCH0_CNTL,
67− mmTCP_WATCH1_ADDR_H, mmTCP_WATCH1_ADDR_L, mmTCP_WATCH1_CNTL,
68− mmTCP_WATCH2_ADDR_H, mmTCP_WATCH2_ADDR_L, mmTCP_WATCH2_CNTL,
69− mmTCP_WATCH3_ADDR_H, mmTCP_WATCH3_ADDR_L, mmTCP_WATCH3_CNTL
70−};
71−
72−union TCP_WATCH_CNTL_BITS {
73− struct {
74− uint32_t mask:24;
75− uint32_t vmid:4;
76− uint32_t atc:1;
77− uint32_t mode:2;
78− uint32_t valid:1;
79− } bitfields, bits;
80− uint32_t u32All;
81− signed int i32All;
82− float f32All;
83−};
84−
8548 static void lock_srbm(struct amdgpu_device *adev, uint32_t mec, uint32_t pipe,
8649 uint32_t queue, uint32_t vmid)
8750 {
@@ -529,55 +492,6 @@ static int kgd_hqd_sdma_destroy(struct amdgpu_device *adev, void *mqd, · 441 unmodified lines
529492 return 0;
530493 }
531494
532−static int kgd_address_watch_disable(struct amdgpu_device *adev)
533−{
534− union TCP_WATCH_CNTL_BITS cntl;
535− unsigned int i;
536−
537− cntl.u32All = 0;
538−
539− cntl.bitfields.valid = 0;
540− cntl.bitfields.mask = ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK;
541− cntl.bitfields.atc = 1;
542−
543− /* Turning off this address until we set all the registers */
544− for (i = 0; i < MAX_WATCH_ADDRESSES; i++)
545− WREG32(watchRegs[i * ADDRESS_WATCH_REG_MAX +
546− ADDRESS_WATCH_REG_CNTL], cntl.u32All);
547−
548− return 0;
549−}
550−
551−static int kgd_address_watch_execute(struct amdgpu_device *adev,
552− unsigned int watch_point_id,
553− uint32_t cntl_val,
554− uint32_t addr_hi,
555− uint32_t addr_lo)
556−{
557− union TCP_WATCH_CNTL_BITS cntl;
558−
559− cntl.u32All = cntl_val;
560−
561− /* Turning off this watch point until we set all the registers */
562− cntl.bitfields.valid = 0;
563− WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
564− ADDRESS_WATCH_REG_CNTL], cntl.u32All);
565−
566− WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
567− ADDRESS_WATCH_REG_ADDR_HI], addr_hi);
568−
569− WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
570− ADDRESS_WATCH_REG_ADDR_LO], addr_lo);
571−
572− /* Enable the watch point */
573− cntl.bitfields.valid = 1;
574−
575− WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX +
576− ADDRESS_WATCH_REG_CNTL], cntl.u32All);
577−
578− return 0;
579−}
580−
581495 static int kgd_wave_control_execute(struct amdgpu_device *adev,
582496 uint32_t gfx_index_val,
583497 uint32_t sq_cmd)
@@ -602,13 +516,6 @@ static int kgd_wave_control_execute(struct amdgpu_device *adev, · 18 unmodified lines
602516 return 0;
603517 }
604518
605−static uint32_t kgd_address_watch_get_offset(struct amdgpu_device *adev,
606− unsigned int watch_point_id,
607− unsigned int reg_offset)
608−{
609− return watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + reg_offset];
610−}
611−
612519 static bool get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,
613520 uint8_t vmid, uint16_t *p_pasid)
614521 {
@@ -665,10 +572,7 @@ const struct kfd2kgd_calls gfx_v7_kfd2kgd = { · 50 unmodified lines
665572 .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
666573 .hqd_destroy = kgd_hqd_destroy,
667574 .hqd_sdma_destroy = kgd_hqd_sdma_destroy,
668− .address_watch_disable = kgd_address_watch_disable,
669− .address_watch_execute = kgd_address_watch_execute,
670575 .wave_control_execute = kgd_wave_control_execute,
671− .address_watch_get_offset = kgd_address_watch_get_offset,
672576 .get_atc_vmid_pasid_mapping_info = get_atc_vmid_pasid_mapping_info,
673577 .set_scratch_backing_va = set_scratch_backing_va,
674578 .set_vm_context_page_table_base = set_vm_context_page_table_base,
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c+0−24
@@ -538,20 +538,6 @@ static bool get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev, · 537 unmodified lines
538538 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
539539 }
540540
541−static int kgd_address_watch_disable(struct amdgpu_device *adev)
542−{
543− return 0;
544−}
545−
546−static int kgd_address_watch_execute(struct amdgpu_device *adev,
547− unsigned int watch_point_id,
548− uint32_t cntl_val,
549− uint32_t addr_hi,
550− uint32_t addr_lo)
551−{
552− return 0;
553−}
554−
555541 static int kgd_wave_control_execute(struct amdgpu_device *adev,
556542 uint32_t gfx_index_val,
557543 uint32_t sq_cmd)
@@ -576,13 +562,6 @@ static int kgd_wave_control_execute(struct amdgpu_device *adev, · 18 unmodified lines
576562 return 0;
577563 }
578564
579−static uint32_t kgd_address_watch_get_offset(struct amdgpu_device *adev,
580− unsigned int watch_point_id,
581− unsigned int reg_offset)
582−{
583− return 0;
584−}
585−
586565 static void set_scratch_backing_va(struct amdgpu_device *adev,
587566 uint64_t va, uint32_t vmid)
588567 {
@@ -614,10 +593,7 @@ const struct kfd2kgd_calls gfx_v8_kfd2kgd = { · 25 unmodified lines
614593 .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
615594 .hqd_destroy = kgd_hqd_destroy,
616595 .hqd_sdma_destroy = kgd_hqd_sdma_destroy,
617− .address_watch_disable = kgd_address_watch_disable,
618− .address_watch_execute = kgd_address_watch_execute,
619596 .wave_control_execute = kgd_wave_control_execute,
620− .address_watch_get_offset = kgd_address_watch_get_offset,
621597 .get_atc_vmid_pasid_mapping_info =
622598 get_atc_vmid_pasid_mapping_info,
623599 .set_scratch_backing_va = set_scratch_backing_va,
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c+2−26
@@ -622,20 +622,6 @@ bool kgd_gfx_v9_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev, · 621 unmodified lines
622622 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
623623 }
624624
625−int kgd_gfx_v9_address_watch_disable(struct amdgpu_device *adev)
626−{
627− return 0;
628−}
629−
630−int kgd_gfx_v9_address_watch_execute(struct amdgpu_device *adev,
631− unsigned int watch_point_id,
632− uint32_t cntl_val,
633− uint32_t addr_hi,
634− uint32_t addr_lo)
635−{
636− return 0;
637−}
638−
639625 int kgd_gfx_v9_wave_control_execute(struct amdgpu_device *adev,
640626 uint32_t gfx_index_val,
641627 uint32_t sq_cmd)
@@ -660,13 +646,6 @@ int kgd_gfx_v9_wave_control_execute(struct amdgpu_device *adev, · 18 unmodified lines
660646 return 0;
661647 }
662648
663−uint32_t kgd_gfx_v9_address_watch_get_offset(struct amdgpu_device *adev,
664− unsigned int watch_point_id,
665− unsigned int reg_offset)
666−{
667− return 0;
668−}
669−
670649 void kgd_gfx_v9_set_vm_context_page_table_base(struct amdgpu_device *adev,
671650 uint32_t vmid, uint64_t page_table_base)
672651 {
@@ -736,7 +715,7 @@ static void get_wave_count(struct amdgpu_device *adev, int queue_idx, · 63 unmodified lines
736715 * process whose pasid is provided as a parameter. The process could have ZERO
737716 * or more queues running and submitting waves to compute units.
738717 *
739− * @kgd: Handle of device from which to get number of waves in flight
718+ * @adev: Handle of device from which to get number of waves in flight
740719 * @pasid: Identifies the process for which this query call is invoked
741720 * @pasid_wave_cnt: Output parameter updated with number of waves in flight that
742721 * belong to process with given pasid
@@ -745,7 +724,7 @@ static void get_wave_count(struct amdgpu_device *adev, int queue_idx, · 2 unmodified lines
745724 *
746725 * Note: It's possible that the device has too many queues (oversubscription)
747726 * in which case a VMID could be remapped to a different PASID. This could lead
748− * to an iaccurate wave count. Following is a high-level sequence:
727+ * to an inaccurate wave count. Following is a high-level sequence:
749728 * Time T1: vmid = getVmid(); vmid is associated with Pasid P1
750729 * Time T2: passId = getPasId(vmid); vmid is associated with Pasid P2
751730 * In the sequence above wave count obtained from time T1 will be incorrectly
@@ -888,10 +867,7 @@ const struct kfd2kgd_calls gfx_v9_kfd2kgd = { · 136 unmodified lines
888867 .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
889868 .hqd_destroy = kgd_gfx_v9_hqd_destroy,
890869 .hqd_sdma_destroy = kgd_hqd_sdma_destroy,
891− .address_watch_disable = kgd_gfx_v9_address_watch_disable,
892− .address_watch_execute = kgd_gfx_v9_address_watch_execute,
893870 .wave_control_execute = kgd_gfx_v9_wave_control_execute,
894− .address_watch_get_offset = kgd_gfx_v9_address_watch_get_offset,
895871 .get_atc_vmid_pasid_mapping_info =
896872 kgd_gfx_v9_get_atc_vmid_pasid_mapping_info,
897873 .set_vm_context_page_table_base = kgd_gfx_v9_set_vm_context_page_table_base,
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h+0−10
@@ -46,19 +46,9 @@ int kgd_gfx_v9_hqd_destroy(struct amdgpu_device *adev, void *mqd, · 45 unmodified lines
4646 enum kfd_preempt_type reset_type,
4747 unsigned int utimeout, uint32_t pipe_id,
4848 uint32_t queue_id);
49−int kgd_gfx_v9_address_watch_disable(struct amdgpu_device *adev);
50−int kgd_gfx_v9_address_watch_execute(struct amdgpu_device *adev,
51− unsigned int watch_point_id,
52− uint32_t cntl_val,
53− uint32_t addr_hi,
54− uint32_t addr_lo);
5549 int kgd_gfx_v9_wave_control_execute(struct amdgpu_device *adev,
5650 uint32_t gfx_index_val,
5751 uint32_t sq_cmd);
58−uint32_t kgd_gfx_v9_address_watch_get_offset(struct amdgpu_device *adev,
59− unsigned int watch_point_id,
60− unsigned int reg_offset);
61−
6252 bool kgd_gfx_v9_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,
6353 uint8_t vmid, uint16_t *p_pasid);
6454
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c+64−12
@@ -121,7 +121,7 @@ static size_t amdgpu_amdkfd_acc_size(uint64_t size) · 120 unmodified lines
121121 }
122122
123123 /**
124− * @amdgpu_amdkfd_reserve_mem_limit() - Decrease available memory by size
124+ * amdgpu_amdkfd_reserve_mem_limit() - Decrease available memory by size
125125 * of buffer including any reserved for control structures
126126 *
127127 * @adev: Device to which allocated BO belongs to
@@ -778,7 +778,7 @@ unwind: · 650 unmodified lines
778778 continue;
779779 if (attachment[i]->bo_va) {
780780 amdgpu_bo_reserve(bo[i], true);
781− amdgpu_vm_bo_rmv(adev, attachment[i]->bo_va);
781+ amdgpu_vm_bo_del(adev, attachment[i]->bo_va);
782782 amdgpu_bo_unreserve(bo[i]);
783783 list_del(&attachment[i]->list);
784784 }
@@ -795,7 +795,7 @@ static void kfd_mem_detach(struct kfd_mem_attachment *attachment) · 10 unmodified lines
795795
796796 pr_debug("\t remove VA 0x%llx in entry %p\n",
797797 attachment->va, attachment);
798− amdgpu_vm_bo_rmv(attachment->adev, attachment->bo_va);
798+ amdgpu_vm_bo_del(attachment->adev, attachment->bo_va);
799799 drm_gem_object_put(&bo->tbo.base);
800800 list_del(&attachment->list);
801801 kfree(attachment);
@@ -842,7 +842,8 @@ static void remove_kgd_mem_from_kfd_bo_list(struct kgd_mem *mem, · 40 unmodified lines
842842 *
843843 * Returns 0 for success, negative errno for errors.
844844 */
845−static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr)
845+static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr,
846+ bool criu_resume)
846847 {
847848 struct amdkfd_process_info *process_info = mem->process_info;
848849 struct amdgpu_bo *bo = mem->bo;
@@ -864,6 +865,18 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr) · 15 unmodified lines
864865 goto out;
865866 }
866867
868+ if (criu_resume) {
869+ /*
870+ * During a CRIU restore operation, the userptr buffer objects
871+ * will be validated in the restore_userptr_work worker at a
872+ * later stage when it is scheduled by another ioctl called by
873+ * CRIU master process for the target pid for restore.
874+ */
875+ atomic_inc(&mem->invalid);
876+ mutex_unlock(&process_info->lock);
877+ return 0;
878+ }
879+
867880 ret = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages);
868881 if (ret) {
869882 pr_err("%s: Failed to get user pages: %d\n", __func__, ret);
@@ -1452,10 +1465,39 @@ uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv) · 582 unmodified lines
14521465 return avm->pd_phys_addr;
14531466 }
14541467
1468+void amdgpu_amdkfd_block_mmu_notifications(void *p)
1469+{
1470+ struct amdkfd_process_info *pinfo = (struct amdkfd_process_info *)p;
1471+
1472+ mutex_lock(&pinfo->lock);
1473+ WRITE_ONCE(pinfo->block_mmu_notifications, true);
1474+ mutex_unlock(&pinfo->lock);
1475+}
1476+
1477+int amdgpu_amdkfd_criu_resume(void *p)
1478+{
1479+ int ret = 0;
1480+ struct amdkfd_process_info *pinfo = (struct amdkfd_process_info *)p;
1481+
1482+ mutex_lock(&pinfo->lock);
1483+ pr_debug("scheduling work\n");
1484+ atomic_inc(&pinfo->evicted_bos);
1485+ if (!READ_ONCE(pinfo->block_mmu_notifications)) {
1486+ ret = -EINVAL;
1487+ goto out_unlock;
1488+ }
1489+ WRITE_ONCE(pinfo->block_mmu_notifications, false);
1490+ schedule_delayed_work(&pinfo->restore_userptr_work, 0);
1491+
1492+out_unlock:
1493+ mutex_unlock(&pinfo->lock);
1494+ return ret;
1495+}
1496+
14551497 int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
14561498 struct amdgpu_device *adev, uint64_t va, uint64_t size,
14571499 void *drm_priv, struct kgd_mem **mem,
1458− uint64_t *offset, uint32_t flags)
1500+ uint64_t *offset, uint32_t flags, bool criu_resume)
14591501 {
14601502 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
14611503 enum ttm_bo_type bo_type = ttm_bo_type_device;
@@ -1558,7 +1600,8 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( · 96 unmodified lines
15581600 add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, user_addr);
15591601
15601602 if (user_addr) {
1561− ret = init_user_pages(*mem, user_addr);
1603+ pr_debug("creating userptr BO for user_addr = %llu\n", user_addr);
1604+ ret = init_user_pages(*mem, user_addr, criu_resume);
15621605 if (ret)
15631606 goto allocate_init_user_pages_failed;
15641607 } else if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
@@ -1813,12 +1856,6 @@ int amdgpu_amdkfd_gpuvm_map_memory_to_gpu( · 248 unmodified lines
18131856 true);
18141857 ret = unreserve_bo_and_vms(&ctx, false, false);
18151858
1816− /* Only apply no TLB flush on Aldebaran to
1817− * workaround regressions on other Asics.
1818− */
1819− if (table_freed && (adev->asic_type != CHIP_ALDEBARAN))
1820− *table_freed = true;
1821−
18221859 goto out;
18231860
18241861 out_unreserve:
@@ -2068,6 +2105,10 @@ int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, · 243 unmodified lines
20682105 int evicted_bos;
20692106 int r = 0;
20702107
2108+ /* Do not process MMU notifications until stage-4 IOCTL is received */
2109+ if (READ_ONCE(process_info->block_mmu_notifications))
2110+ return 0;
2111+
20712112 atomic_inc(&mem->invalid);
20722113 evicted_bos = atomic_inc_return(&process_info->evicted_bos);
20732114 if (evicted_bos == 1) {
@@ -2635,3 +2676,14 @@ int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev, · 561 unmodified lines
26352676
26362677 return 0;
26372678 }
2679+
2680+bool amdgpu_amdkfd_bo_mapped_to_dev(struct amdgpu_device *adev, struct kgd_mem *mem)
2681+{
2682+ struct kfd_mem_attachment *entry;
2683+
2684+ list_for_each_entry(entry, &mem->attachments, list) {
2685+ if (entry->is_mapped && entry->adev == adev)
2686+ return true;
2687+ }
2688+ return false;
2689+}
drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c+2−0
@@ -1083,6 +1083,7 @@ int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev, · 1082 unmodified lines
10831083 return 0;
10841084 }
10851085
1086+#ifdef CONFIG_DRM_AMDGPU_SI
10861087 int amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device *adev,
10871088 u32 clock,
10881089 bool strobe_mode,
@@ -1503,6 +1504,7 @@ int amdgpu_atombios_init_mc_reg_table(struct amdgpu_device *adev, · 414 unmodified lines
15031504 }
15041505 return -EINVAL;
15051506 }
1507+#endif
15061508
15071509 bool amdgpu_atombios_has_gpu_virtualization_table(struct amdgpu_device *adev)
15081510 {
drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h+12−10
@@ -160,6 +160,7 @@ int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev, · 159 unmodified lines
160160 bool strobe_mode,
161161 struct atom_clock_dividers *dividers);
162162
163+#ifdef CONFIG_DRM_AMDGPU_SI
163164 int amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device *adev,
164165 u32 clock,
165166 bool strobe_mode,
@@ -179,6 +180,17 @@ int amdgpu_atombios_get_voltage_table(struct amdgpu_device *adev, · 13 unmodified lines
179180 int amdgpu_atombios_init_mc_reg_table(struct amdgpu_device *adev,
180181 u8 module_index,
181182 struct atom_mc_reg_table *reg_table);
183+int amdgpu_atombios_get_max_vddc(struct amdgpu_device *adev, u8 voltage_type,
184+ u16 voltage_id, u16 *voltage);
185+int amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(struct amdgpu_device *adev,
186+ u16 *voltage,
187+ u16 leakage_idx);
188+void amdgpu_atombios_get_default_voltages(struct amdgpu_device *adev,
189+ u16 *vddc, u16 *vddci, u16 *mvdd);
190+int amdgpu_atombios_get_svi2_info(struct amdgpu_device *adev,
191+ u8 voltage_type,
192+ u8 *svd_gpio_id, u8 *svc_gpio_id);
193+#endif
182194
183195 bool amdgpu_atombios_has_gpu_virtualization_table(struct amdgpu_device *adev);
184196
@@ -190,21 +202,11 @@ void amdgpu_atombios_scratch_regs_set_backlight_level(struct amdgpu_device *adev · 5 unmodified lines
190202 bool amdgpu_atombios_scratch_need_asic_init(struct amdgpu_device *adev);
191203
192204 void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);
193−int amdgpu_atombios_get_max_vddc(struct amdgpu_device *adev, u8 voltage_type,
194− u16 voltage_id, u16 *voltage);
195−int amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(struct amdgpu_device *adev,
196− u16 *voltage,
197− u16 leakage_idx);
198−void amdgpu_atombios_get_default_voltages(struct amdgpu_device *adev,
199− u16 *vddc, u16 *vddci, u16 *mvdd);
200205 int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev,
201206 u8 clock_type,
202207 u32 clock,
203208 bool strobe_mode,
204209 struct atom_clock_dividers *dividers);
205−int amdgpu_atombios_get_svi2_info(struct amdgpu_device *adev,
206− u8 voltage_type,
207− u8 *svd_gpio_id, u8 *svc_gpio_id);
208210
209211 int amdgpu_atombios_get_data_table(struct amdgpu_device *adev,
210212 uint32_t table,
drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c+38−0
@@ -464,3 +464,41 @@ success: · 463 unmodified lines
464464 adev->is_atom_fw = (adev->asic_type >= CHIP_VEGA10) ? true : false;
465465 return true;
466466 }
467+
468+/* helper function for soc15 and onwards to read bios from rom */
469+bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev,
470+ u8 *bios, u32 length_bytes)
471+{
472+ u32 *dw_ptr;
473+ u32 i, length_dw;
474+ u32 rom_index_offset;
475+ u32 rom_data_offset;
476+
477+ if (bios == NULL)
478+ return false;
479+ if (length_bytes == 0)
480+ return false;
481+ /* APU vbios image is part of sbios image */
482+ if (adev->flags & AMD_IS_APU)
483+ return false;
484+ if (!adev->smuio.funcs ||
485+ !adev->smuio.funcs->get_rom_index_offset ||
486+ !adev->smuio.funcs->get_rom_data_offset)
487+ return false;
488+
489+ dw_ptr = (u32 *)bios;
490+ length_dw = ALIGN(length_bytes, 4) / 4;
491+
492+ rom_index_offset =
493+ adev->smuio.funcs->get_rom_index_offset(adev);
494+ rom_data_offset =
495+ adev->smuio.funcs->get_rom_data_offset(adev);
496+
497+ /* set rom index to 0 */
498+ WREG32(rom_index_offset, 0);
499+ /* read out the rom data */
500+ for (i = 0; i < length_dw; i++)
501+ dw_ptr[i] = RREG32(rom_data_offset);
502+
503+ return true;
504+}
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c+13−6
@@ -127,8 +127,6 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, union drm_amdgpu_cs · 126 unmodified lines
127127 goto free_chunk;
128128 }
129129
130− mutex_lock(&p->ctx->lock);
131−
132130 /* skip guilty context job */
133131 if (atomic_read(&p->ctx->guilty) == 1) {
134132 ret = -ECANCELED;
@@ -314,7 +312,7 @@ static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev, · 179 unmodified lines
314312 }
315313
316314 total_vram = adev->gmc.real_vram_size - atomic64_read(&adev->vram_pin_size);
317− used_vram = amdgpu_vram_mgr_usage(&adev->mman.vram_mgr);
315+ used_vram = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager);
318316 free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram;
319317
320318 spin_lock(&adev->mm_stats.lock);
@@ -585,6 +583,16 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, · 264 unmodified lines
585583 }
586584 }
587585
586+ /* Move fence waiting after getting reservation lock of
587+ * PD root. Then there is no need on a ctx mutex lock.
588+ */
589+ r = amdgpu_ctx_wait_prev_fence(p->ctx, p->entity);
590+ if (unlikely(r != 0)) {
591+ if (r != -ERESTARTSYS)
592+ DRM_ERROR("amdgpu_ctx_wait_prev_fence failed.\n");
593+ goto error_validate;
594+ }
595+
588596 amdgpu_cs_get_threshold_for_moves(p->adev, &p->bytes_moved_threshold,
589597 &p->bytes_moved_vis_threshold);
590598 p->bytes_moved = 0;
@@ -700,7 +708,6 @@ static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, · 109 unmodified lines
700708 dma_fence_put(parser->fence);
701709
702710 if (parser->ctx) {
703− mutex_unlock(&parser->ctx->lock);
704711 amdgpu_ctx_put(parser->ctx);
705712 }
706713 if (parser->bo_list)
@@ -944,7 +951,7 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev, · 237 unmodified lines
944951 if (parser->job->uf_addr && ring->funcs->no_user_fence)
945952 return -EINVAL;
946953
947− return amdgpu_ctx_wait_prev_fence(parser->ctx, parser->entity);
954+ return 0;
948955 }
949956
950957 static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p,
@@ -1360,7 +1367,6 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) · 409 unmodified lines
13601367 goto out;
13611368
13621369 r = amdgpu_cs_submit(&parser, cs);
1363−
13641370 out:
13651371 amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
13661372
@@ -1506,6 +1512,7 @@ int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, · 139 unmodified lines
15061512 return 0;
15071513
15081514 default:
1515+ dma_fence_put(fence);
15091516 return -EINVAL;
15101517 }
15111518 }
drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c+1−1
@@ -98,7 +98,7 @@ int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm, · 97 unmodified lines
9898
9999 if (r) {
100100 DRM_ERROR("failed to do bo_map on static CSA, err=%d\n", r);
101− amdgpu_vm_bo_rmv(adev, *bo_va);
101+ amdgpu_vm_bo_del(adev, *bo_va);
102102 ttm_eu_backoff_reservation(&ticket, &list);
103103 return r;
104104 }
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c+128−4
@@ -230,13 +230,13 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev, · 229 unmodified lines
230230
231231 kref_init(&ctx->refcount);
232232 spin_lock_init(&ctx->ring_lock);
233− mutex_init(&ctx->lock);
234233
235234 ctx->reset_counter = atomic_read(&adev->gpu_reset_counter);
236235 ctx->reset_counter_query = ctx->reset_counter;
237236 ctx->vram_lost_counter = atomic_read(&adev->vram_lost_counter);
238237 ctx->init_priority = priority;
239238 ctx->override_priority = AMDGPU_CTX_PRIORITY_UNSET;
239+ ctx->stable_pstate = AMDGPU_CTX_STABLE_PSTATE_NONE;
240240
241241 return 0;
242242 }
@@ -255,6 +255,86 @@ static void amdgpu_ctx_fini_entity(struct amdgpu_ctx_entity *entity) · 12 unmodified lines
255255 kfree(entity);
256256 }
257257
258+static int amdgpu_ctx_get_stable_pstate(struct amdgpu_ctx *ctx,
259+ u32 *stable_pstate)
260+{
261+ struct amdgpu_device *adev = ctx->adev;
262+ enum amd_dpm_forced_level current_level;
263+
264+ if (!ctx)
265+ return -EINVAL;
266+
267+ current_level = amdgpu_dpm_get_performance_level(adev);
268+
269+ switch (current_level) {
270+ case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
271+ *stable_pstate = AMDGPU_CTX_STABLE_PSTATE_STANDARD;
272+ break;
273+ case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
274+ *stable_pstate = AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK;
275+ break;
276+ case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
277+ *stable_pstate = AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK;
278+ break;
279+ case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
280+ *stable_pstate = AMDGPU_CTX_STABLE_PSTATE_PEAK;
281+ break;
282+ default:
283+ *stable_pstate = AMDGPU_CTX_STABLE_PSTATE_NONE;
284+ break;
285+ }
286+ return 0;
287+}
288+
289+static int amdgpu_ctx_set_stable_pstate(struct amdgpu_ctx *ctx,
290+ u32 stable_pstate)
291+{
292+ struct amdgpu_device *adev = ctx->adev;
293+ enum amd_dpm_forced_level level;
294+ int r;
295+
296+ if (!ctx)
297+ return -EINVAL;
298+
299+ mutex_lock(&adev->pm.stable_pstate_ctx_lock);
300+ if (adev->pm.stable_pstate_ctx && adev->pm.stable_pstate_ctx != ctx) {
301+ r = -EBUSY;
302+ goto done;
303+ }
304+
305+ switch (stable_pstate) {
306+ case AMDGPU_CTX_STABLE_PSTATE_NONE:
307+ level = AMD_DPM_FORCED_LEVEL_AUTO;
308+ break;
309+ case AMDGPU_CTX_STABLE_PSTATE_STANDARD:
310+ level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
311+ break;
312+ case AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK:
313+ level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
314+ break;
315+ case AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK:
316+ level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
317+ break;
318+ case AMDGPU_CTX_STABLE_PSTATE_PEAK:
319+ level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
320+ break;
321+ default:
322+ r = -EINVAL;
323+ goto done;
324+ }
325+
326+ r = amdgpu_dpm_force_performance_level(adev, level);
327+
328+ if (level == AMD_DPM_FORCED_LEVEL_AUTO)
329+ adev->pm.stable_pstate_ctx = NULL;
330+ else
331+ adev->pm.stable_pstate_ctx = ctx;
332+done:
333+ mutex_unlock(&adev->pm.stable_pstate_ctx_lock);
334+
335+ return r;
336+}
337+
258338 static void amdgpu_ctx_fini(struct kref *ref)
259339 {
260340 struct amdgpu_ctx *ctx = container_of(ref, struct amdgpu_ctx, refcount);
@@ -270,8 +350,7 @@ static void amdgpu_ctx_fini(struct kref *ref) · 9 unmodified lines
270350 ctx->entities[i][j] = NULL;
271351 }
272352 }
273−
274− mutex_destroy(&ctx->lock);
353+ amdgpu_ctx_set_stable_pstate(ctx, AMDGPU_CTX_STABLE_PSTATE_NONE);
275354 kfree(ctx);
276355 }
277356
@@ -467,11 +546,41 @@ static int amdgpu_ctx_query2(struct amdgpu_device *adev, · 189 unmodified lines
467546 return 0;
468547 }
469548
549+
550+
551+static int amdgpu_ctx_stable_pstate(struct amdgpu_device *adev,
552+ struct amdgpu_fpriv *fpriv, uint32_t id,
553+ bool set, u32 *stable_pstate)
554+{
555+ struct amdgpu_ctx *ctx;
556+ struct amdgpu_ctx_mgr *mgr;
557+ int r;
558+
559+ if (!fpriv)
560+ return -EINVAL;
561+
562+ mgr = &fpriv->ctx_mgr;
563+ mutex_lock(&mgr->lock);
564+ ctx = idr_find(&mgr->ctx_handles, id);
565+ if (!ctx) {
566+ mutex_unlock(&mgr->lock);
567+ return -EINVAL;
568+ }
569+
570+ if (set)
571+ r = amdgpu_ctx_set_stable_pstate(ctx, *stable_pstate);
572+ else
573+ r = amdgpu_ctx_get_stable_pstate(ctx, stable_pstate);
574+
575+ mutex_unlock(&mgr->lock);
576+ return r;
577+}
578+
470579 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
471580 struct drm_file *filp)
472581 {
473582 int r;
474− uint32_t id;
583+ uint32_t id, stable_pstate;
475584 int32_t priority;
476585
477586 union drm_amdgpu_ctx *args = data;
@@ -500,6 +609,21 @@ int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, · 22 unmodified lines
500609 case AMDGPU_CTX_OP_QUERY_STATE2:
501610 r = amdgpu_ctx_query2(adev, fpriv, id, &args->out);
502611 break;
612+ case AMDGPU_CTX_OP_GET_STABLE_PSTATE:
613+ if (args->in.flags)
614+ return -EINVAL;
615+ r = amdgpu_ctx_stable_pstate(adev, fpriv, id, false, &stable_pstate);
616+ if (!r)
617+ args->out.pstate.flags = stable_pstate;
618+ break;
619+ case AMDGPU_CTX_OP_SET_STABLE_PSTATE:
620+ if (args->in.flags & ~AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK)
621+ return -EINVAL;
622+ stable_pstate = args->in.flags & AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK;
623+ if (stable_pstate > AMDGPU_CTX_STABLE_PSTATE_PEAK)
624+ return -EINVAL;
625+ r = amdgpu_ctx_stable_pstate(adev, fpriv, id, true, &stable_pstate);
626+ break;
503627 default:
504628 return -EINVAL;
505629 }
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h+1−1
@@ -49,10 +49,10 @@ struct amdgpu_ctx { · 48 unmodified lines
4949 bool preamble_presented;
5050 int32_t init_priority;
5151 int32_t override_priority;
52− struct mutex lock;
5352 atomic_t guilty;
5453 unsigned long ras_counter_ce;
5554 unsigned long ras_counter_ue;
55+ uint32_t stable_pstate;
5656 };
5757
5858 struct amdgpu_ctx_mgr {
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c+27−17
@@ -37,6 +37,8 @@ · 36 unmodified lines
3737 #include "amdgpu_fw_attestation.h"
3838 #include "amdgpu_umr.h"
3939
40+#include "amdgpu_reset.h"
41+
4042 #if defined(CONFIG_DEBUG_FS)
4143
4244 /**
@@ -728,7 +730,7 @@ static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf, · 685 unmodified lines
728730 return -ENOMEM;
729731
730732 /* version, increment each time something is added */
731− config[no_regs++] = 3;
733+ config[no_regs++] = 4;
732734 config[no_regs++] = adev->gfx.config.max_shader_engines;
733735 config[no_regs++] = adev->gfx.config.max_tile_pipes;
734736 config[no_regs++] = adev->gfx.config.max_cu_per_sh;
@@ -768,6 +770,9 @@ static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf, · 33 unmodified lines
768770 config[no_regs++] = adev->pdev->subsystem_device;
769771 config[no_regs++] = adev->pdev->subsystem_vendor;
770772
773+ /* rev==4 APU flag */
774+ config[no_regs++] = adev->flags & AMD_IS_APU ? 1 : 0;
775+
771776 while (size && (*pos < no_regs * 4)) {
772777 uint32_t value;
773778
@@ -1120,8 +1125,10 @@ static ssize_t amdgpu_debugfs_gfxoff_read(struct file *f, char __user *buf, · 346 unmodified lines
11201125 return -EINVAL;
11211126
11221127 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
1123− if (r < 0)
1128+ if (r < 0) {
1129+ pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
11241130 return r;
1131+ }
11251132
11261133 while (size) {
11271134 uint32_t value;
@@ -1279,7 +1286,7 @@ static int amdgpu_debugfs_test_ib_show(struct seq_file *m, void *unused) · 151 unmodified lines
12791286 }
12801287
12811288 /* Avoid accidently unparking the sched thread during GPU reset */
1282− r = down_write_killable(&adev->reset_sem);
1289+ r = down_write_killable(&adev->reset_domain->sem);
12831290 if (r)
12841291 return r;
12851292
@@ -1308,7 +1315,7 @@ static int amdgpu_debugfs_test_ib_show(struct seq_file *m, void *unused) · 22 unmodified lines
13081315 kthread_unpark(ring->sched.thread);
13091316 }
13101317
1311− up_write(&adev->reset_sem);
1318+ up_write(&adev->reset_domain->sem);
13121319
13131320 pm_runtime_mark_last_busy(dev->dev);
13141321 pm_runtime_put_autosuspend(dev->dev);
@@ -1517,7 +1524,7 @@ static int amdgpu_debugfs_ib_preempt(void *data, u64 val) · 202 unmodified lines
15171524 return -ENOMEM;
15181525
15191526 /* Avoid accidently unparking the sched thread during GPU reset */
1520− r = down_read_killable(&adev->reset_sem);
1527+ r = down_read_killable(&adev->reset_domain->sem);
15211528 if (r)
15221529 goto pro_end;
15231530
@@ -1560,7 +1567,7 @@ failure: · 36 unmodified lines
15601567 /* restart the scheduler */
15611568 kthread_unpark(ring->sched.thread);
15621569
1563− up_read(&adev->reset_sem);
1570+ up_read(&adev->reset_domain->sem);
15641571
15651572 ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
15661573
@@ -1585,22 +1592,25 @@ static int amdgpu_debugfs_sclk_set(void *data, u64 val) · 18 unmodified lines
15851592 return ret;
15861593 }
15871594
1588− if (is_support_sw_smu(adev)) {
1589− ret = smu_get_dpm_freq_range(&adev->smu, SMU_SCLK, &min_freq, &max_freq);
1590− if (ret || val > max_freq || val < min_freq)
1591− return -EINVAL;
1592− ret = smu_set_soft_freq_range(&adev->smu, SMU_SCLK, (uint32_t)val, (uint32_t)val);
1593− } else {
1594− return 0;
1595+ ret = amdgpu_dpm_get_dpm_freq_range(adev, PP_SCLK, &min_freq, &max_freq);
1596+ if (ret == -EOPNOTSUPP) {
1597+ ret = 0;
1598+ goto out;
1599+ }
1600+ if (ret || val > max_freq || val < min_freq) {
1601+ ret = -EINVAL;
1602+ goto out;
15951603 }
15961604
1605+ ret = amdgpu_dpm_set_soft_freq_range(adev, PP_SCLK, (uint32_t)val, (uint32_t)val);
1606+ if (ret)
1607+ ret = -EINVAL;
1608+
1609+out:
15971610 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
15981611 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
15991612
1600− if (ret)
1601− return -EINVAL;
1602−
1603− return 0;
1613+ return ret;
16041614 }
16051615
16061616 DEFINE_DEBUGFS_ATTRIBUTE(fops_ib_preempt, NULL,
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c+262−143
@@ -31,6 +31,7 @@ · 30 unmodified lines
3131 #include <linux/console.h>
3232 #include <linux/slab.h>
3333 #include <linux/iommu.h>
34+#include <linux/pci.h>
3435
3536 #include <drm/drm_atomic_helper.h>
3637 #include <drm/drm_probe_helper.h>
@@ -55,7 +56,6 @@ · 18 unmodified lines
5556 #include "soc15.h"
5657 #include "nv.h"
5758 #include "bif/bif_4_1_d.h"
58−#include <linux/pci.h>
5959 #include <linux/firmware.h>
6060 #include "amdgpu_vf_error.h"
6161
@@ -88,6 +88,8 @@ MODULE_FIRMWARE("amdgpu/vangogh_gpu_info.bin"); · 26 unmodified lines
8888 MODULE_FIRMWARE("amdgpu/yellow_carp_gpu_info.bin");
8989
9090 #define AMDGPU_RESUME_MS 2000
91+#define AMDGPU_MAX_RETRY_LIMIT 2
92+#define AMDGPU_RETRY_SRIOV_RESET(r) ((r) == -EBUSY || (r) == -ETIMEDOUT || (r) == -EINVAL)
9193
9294 const char *amdgpu_asic_name[] = {
9395 "TAHITI",
@@ -424,10 +426,10 @@ bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev) · 330 unmodified lines
424426 * the lock.
425427 */
426428 if (in_task()) {
427− if (down_read_trylock(&adev->reset_sem))
428− up_read(&adev->reset_sem);
429+ if (down_read_trylock(&adev->reset_domain->sem))
430+ up_read(&adev->reset_domain->sem);
429431 else
430− lockdep_assert_held(&adev->reset_sem);
432+ lockdep_assert_held(&adev->reset_domain->sem);
431433 }
432434 #endif
433435 return false;
@@ -453,9 +455,9 @@ uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, · 19 unmodified lines
453455 if ((reg * 4) < adev->rmmio_size) {
454456 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
455457 amdgpu_sriov_runtime(adev) &&
456− down_read_trylock(&adev->reset_sem)) {
458+ down_read_trylock(&adev->reset_domain->sem)) {
457459 ret = amdgpu_kiq_rreg(adev, reg);
458− up_read(&adev->reset_sem);
460+ up_read(&adev->reset_domain->sem);
459461 } else {
460462 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
461463 }
@@ -538,9 +540,9 @@ void amdgpu_device_wreg(struct amdgpu_device *adev, · 76 unmodified lines
538540 if ((reg * 4) < adev->rmmio_size) {
539541 if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
540542 amdgpu_sriov_runtime(adev) &&
541− down_read_trylock(&adev->reset_sem)) {
543+ down_read_trylock(&adev->reset_domain->sem)) {
542544 amdgpu_kiq_wreg(adev, reg, v);
543− up_read(&adev->reset_sem);
545+ up_read(&adev->reset_domain->sem);
544546 } else {
545547 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
546548 }
@@ -554,7 +556,11 @@ void amdgpu_device_wreg(struct amdgpu_device *adev, · 7 unmodified lines
554556 /**
555557 * amdgpu_mm_wreg_mmio_rlc - write register either with direct/indirect mmio or with RLC path if in range
556558 *
557− * this function is invoked only the debugfs register access
559+ * @adev: amdgpu_device pointer
560+ * @reg: mmio/rlc register
561+ * @v: value to write
562+ *
563+ * this function is invoked only for the debugfs register access
558564 */
559565 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
560566 uint32_t reg, uint32_t v)
@@ -566,7 +572,7 @@ void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, · 5 unmodified lines
566572 adev->gfx.rlc.funcs &&
567573 adev->gfx.rlc.funcs->is_rlcg_access_range) {
568574 if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg))
569− return adev->gfx.rlc.funcs->sriov_wreg(adev, reg, v, 0, 0);
575+ return amdgpu_sriov_wreg(adev, reg, v, 0, 0);
570576 } else if ((reg * 4) >= adev->rmmio_size) {
571577 adev->pcie_wreg(adev, reg * 4, v);
572578 } else {
@@ -1312,6 +1318,31 @@ bool amdgpu_device_need_post(struct amdgpu_device *adev) · 739 unmodified lines
13121318 return true;
13131319 }
13141320
1321+/**
1322+ * amdgpu_device_should_use_aspm - check if the device should program ASPM
1323+ *
1324+ * @adev: amdgpu_device pointer
1325+ *
1326+ * Confirm whether the module parameter and pcie bridge agree that ASPM should
1327+ * be set for this device.
1328+ *
1329+ * Returns true if it should be used or false if not.
1330+ */
1331+bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev)
1332+{
1333+ switch (amdgpu_aspm) {
1334+ case -1:
1335+ break;
1336+ case 0:
1337+ return false;
1338+ case 1:
1339+ return true;
1340+ default:
1341+ return false;
1342+ }
1343+ return pcie_aspm_enabled(adev->pdev);
1344+}
1345+
13151346 /* if we get transitioned to only one device, take VGA back */
13161347 /**
13171348 * amdgpu_device_vga_set_decode - enable/disable vga decode
@@ -1446,7 +1477,8 @@ static int amdgpu_device_init_apu_flags(struct amdgpu_device *adev) · 128 unmodified lines
14461477 case CHIP_YELLOW_CARP:
14471478 break;
14481479 case CHIP_CYAN_SKILLFISH:
1449− if (adev->pdev->device == 0x13FE)
1480+ if ((adev->pdev->device == 0x13FE) ||
1481+ (adev->pdev->device == 0x143F))
14501482 adev->apu_flags |= AMD_APU_IS_CYAN_SKILLFISH2;
14511483 break;
14521484 default:
@@ -2073,6 +2105,8 @@ out: · 620 unmodified lines
20732105 */
20742106 static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
20752107 {
2108+ struct drm_device *dev = adev_to_drm(adev);
2109+ struct pci_dev *parent;
20762110 int i, r;
20772111
20782112 amdgpu_device_enable_virtual_display(adev);
@@ -2137,6 +2171,16 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) · 58 unmodified lines
21372171 break;
21382172 }
21392173
2174+ if (amdgpu_has_atpx() &&
2175+ (amdgpu_is_atpx_hybrid() ||
2176+ amdgpu_has_atpx_dgpu_power_cntl()) &&
2177+ ((adev->flags & AMD_IS_APU) == 0) &&
2178+ !pci_is_thunderbolt_attached(to_pci_dev(dev->dev)))
2179+ adev->flags |= AMD_IS_PX;
2180+
2181+ parent = pci_upstream_bridge(adev->pdev);
2182+ adev->has_pr3 = parent ? pci_pr3_present(parent) : false;
2183+
21402184 amdgpu_amdkfd_device_probe(adev);
21412185
21422186 adev->pm.pp_feature = amdgpu_pp_feature_mask;
@@ -2287,6 +2331,49 @@ static int amdgpu_device_fw_loading(struct amdgpu_device *adev) · 144 unmodified lines
22872331 return r;
22882332 }
22892333
2334+static int amdgpu_device_init_schedulers(struct amdgpu_device *adev)
2335+{
2336+ long timeout;
2337+ int r, i;
2338+
2339+ for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2340+ struct amdgpu_ring *ring = adev->rings[i];
2341+
2342+ /* No need to setup the GPU scheduler for rings that don't need it */
2343+ if (!ring || ring->no_scheduler)
2344+ continue;
2345+
2346+ switch (ring->funcs->type) {
2347+ case AMDGPU_RING_TYPE_GFX:
2348+ timeout = adev->gfx_timeout;
2349+ break;
2350+ case AMDGPU_RING_TYPE_COMPUTE:
2351+ timeout = adev->compute_timeout;
2352+ break;
2353+ case AMDGPU_RING_TYPE_SDMA:
2354+ timeout = adev->sdma_timeout;
2355+ break;
2356+ default:
2357+ timeout = adev->video_timeout;
2358+ break;
2359+ }
2360+
2361+ r = drm_sched_init(&ring->sched, &amdgpu_sched_ops,
2362+ ring->num_hw_submission, amdgpu_job_hang_limit,
2363+ timeout, adev->reset_domain->wq,
2364+ ring->sched_score, ring->name,
2365+ adev->dev);
2366+ if (r) {
2367+ DRM_ERROR("Failed to create scheduler on ring %s.\n",
2368+ ring->name);
2369+ return r;
2370+ }
2371+ }
2372+
2373+ return 0;
2374+}
2375+
2376+
22902377 /**
22912378 * amdgpu_device_ip_init - run init for hardware IPs
22922379 *
@@ -2398,8 +2485,28 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev) · 105 unmodified lines
23982485 if (r)
23992486 goto init_failed;
24002487
2401− if (adev->gmc.xgmi.num_physical_nodes > 1)
2402− amdgpu_xgmi_add_device(adev);
2488+ /**
2489+ * In case of XGMI grab extra reference for reset domain for this device
2490+ */
2491+ if (adev->gmc.xgmi.num_physical_nodes > 1) {
2492+ if (amdgpu_xgmi_add_device(adev) == 0) {
2493+ struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
2494+
2495+ if (!hive->reset_domain ||
2496+ !amdgpu_reset_get_reset_domain(hive->reset_domain)) {
2497+ r = -ENOENT;
2498+ goto init_failed;
2499+ }
2500+
2501+ /* Drop the early temporary reset domain we created for device */
2502+ amdgpu_reset_put_reset_domain(adev->reset_domain);
2503+ adev->reset_domain = hive->reset_domain;
2504+ }
2505+ }
2506+
2507+ r = amdgpu_device_init_schedulers(adev);
2508+ if (r)
2509+ goto init_failed;
24032510
24042511 /* Don't init kfd if whole hive need to be reset during init */
24052512 if (!adev->gmc.xgmi.pending_reset)
@@ -2610,6 +2717,12 @@ static int amdgpu_device_ip_late_init(struct amdgpu_device *adev) · 204 unmodified lines
26102717 adev->ip_blocks[i].status.late_initialized = true;
26112718 }
26122719
2720+ r = amdgpu_ras_late_init(adev);
2721+ if (r) {
2722+ DRM_ERROR("amdgpu_ras_late_init failed %d", r);
2723+ return r;
2724+ }
2725+
26132726 amdgpu_ras_set_error_query_ready(adev, true);
26142727
26152728 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
@@ -2624,7 +2737,7 @@ static int amdgpu_device_ip_late_init(struct amdgpu_device *adev) · 8 unmodified lines
26242737 /* For passthrough configuration on arcturus and aldebaran, enable special handling SBR */
26252738 if (amdgpu_passthrough(adev) && ((adev->asic_type == CHIP_ARCTURUS && adev->gmc.xgmi.num_physical_nodes > 1)||
26262739 adev->asic_type == CHIP_ALDEBARAN ))
2627− smu_handle_passthrough_sbr(&adev->smu, true);
2740+ amdgpu_dpm_handle_passthrough_sbr(adev, true);
26282741
26292742 if (adev->gmc.xgmi.num_physical_nodes > 1) {
26302743 mutex_lock(&mgpu_info.mutex);
@@ -2708,11 +2821,11 @@ static int amdgpu_device_ip_fini_early(struct amdgpu_device *adev) · 77 unmodified lines
27082821 }
27092822 }
27102823
2711− amdgpu_amdkfd_suspend(adev, false);
2712−
27132824 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
27142825 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
27152826
2827+ amdgpu_amdkfd_suspend(adev, false);
2828+
27162829 /* Workaroud for ASICs need to disable SMC first */
27172830 amdgpu_device_smu_fini_early(adev);
27182831
@@ -2881,7 +2994,7 @@ static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev) · 162 unmodified lines
28812994 int i, r;
28822995
28832996 if (adev->in_s0ix)
2884− amdgpu_gfx_state_change_set(adev, sGpuChangeState_D3Entry);
2997+ amdgpu_dpm_gfx_state_change(adev, sGpuChangeState_D3Entry);
28852998
28862999 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
28873000 if (!adev->ip_blocks[i].status.valid)
@@ -3307,9 +3420,9 @@ static void amdgpu_device_xgmi_reset_func(struct work_struct *__work) · 419 unmodified lines
33073420 if (adev->asic_reset_res)
33083421 goto fail;
33093422
3310− if (adev->mmhub.ras_funcs &&
3311− adev->mmhub.ras_funcs->reset_ras_error_count)
3312− adev->mmhub.ras_funcs->reset_ras_error_count(adev);
3423+ if (adev->mmhub.ras && adev->mmhub.ras->ras_block.hw_ops &&
3424+ adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count)
3425+ adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count(adev);
33133426 } else {
33143427
33153428 task_barrier_full(&hive->tb);
@@ -3493,12 +3606,11 @@ int amdgpu_device_init(struct amdgpu_device *adev, · 177 unmodified lines
34933606 mutex_init(&adev->mn_lock);
34943607 mutex_init(&adev->virt.vf_errors.lock);
34953608 hash_init(adev->mn_hash);
3496− atomic_set(&adev->in_gpu_reset, 0);
3497− init_rwsem(&adev->reset_sem);
34983609 mutex_init(&adev->psp.mutex);
34993610 mutex_init(&adev->notifier_lock);
3611+ mutex_init(&adev->pm.stable_pstate_ctx_lock);
35003612
3501− amdgpu_device_init_apu_flags(adev);
3613+ amdgpu_device_init_apu_flags(adev);
35023614
35033615 r = amdgpu_device_check_arguments(adev);
35043616 if (r)
@@ -3519,6 +3631,8 @@ int amdgpu_device_init(struct amdgpu_device *adev, · 14 unmodified lines
35193631
35203632 INIT_LIST_HEAD(&adev->reset_list);
35213633
3634+ INIT_LIST_HEAD(&adev->ras_list);
3635+
35223636 INIT_DELAYED_WORK(&adev->delayed_init_work,
35233637 amdgpu_device_delayed_init_work_handler);
35243638 INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work,
@@ -3577,6 +3691,15 @@ int amdgpu_device_init(struct amdgpu_device *adev, · 52 unmodified lines
35773691 return r;
35783692 }
35793693
3694+ /*
3695+ * Reset domain needs to be present early, before XGMI hive discovered
3696+ * (if any) and intitialized to use reset sem and in_gpu reset flag
3697+ * early on during init.
3698+ */
3699+ adev->reset_domain = amdgpu_reset_create_reset_domain(SINGLE_DEVICE ,"amdgpu-reset-dev");
3700+ if (!adev->reset_domain)
3701+ return -ENOMEM;
3702+
35803703 /* early init functions */
35813704 r = amdgpu_device_ip_early_init(adev);
35823705 if (r)
@@ -3953,6 +4076,9 @@ void amdgpu_device_fini_sw(struct amdgpu_device *adev) · 370 unmodified lines
39534076 if (adev->mman.discovery_bin)
39544077 amdgpu_discovery_fini(adev);
39554078
4079+ amdgpu_reset_put_reset_domain(adev->reset_domain);
4080+ adev->reset_domain = NULL;
4081+
39564082 kfree(adev->pci_state);
39574083
39584084 }
@@ -4044,7 +4170,7 @@ int amdgpu_device_resume(struct drm_device *dev, bool fbcon) · 85 unmodified lines
40444170 return 0;
40454171
40464172 if (adev->in_s0ix)
4047− amdgpu_gfx_state_change_set(adev, sGpuChangeState_D0Entry);
4173+ amdgpu_dpm_gfx_state_change(adev, sGpuChangeState_D0Entry);
40484174
40494175 /* post card */
40504176 if (amdgpu_device_need_post(adev)) {
@@ -4347,7 +4473,9 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device *adev, · 296 unmodified lines
43474473 {
43484474 int r;
43494475 struct amdgpu_hive_info *hive = NULL;
4476+ int retry_limit = 0;
43504477
4478+retry:
43514479 amdgpu_amdkfd_pre_reset(adev);
43524480
43534481 amdgpu_amdkfd_pre_reset(adev);
@@ -4396,6 +4524,14 @@ error: · 42 unmodified lines
43964524 }
43974525 amdgpu_virt_release_full_gpu(adev, true);
43984526
4527+ if (AMDGPU_RETRY_SRIOV_RESET(r)) {
4528+ if (retry_limit < AMDGPU_MAX_RETRY_LIMIT) {
4529+ retry_limit++;
4530+ goto retry;
4531+ } else
4532+ DRM_ERROR("GPU reset retry is beyond the retry limit\n");
4533+ }
4534+
43994535 return r;
44004536 }
44014537
@@ -4645,9 +4781,9 @@ int amdgpu_do_asic_reset(struct list_head *device_list_handle, · 243 unmodified lines
46454781
46464782 if (!r && amdgpu_ras_intr_triggered()) {
46474783 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
4648− if (tmp_adev->mmhub.ras_funcs &&
4649− tmp_adev->mmhub.ras_funcs->reset_ras_error_count)
4650− tmp_adev->mmhub.ras_funcs->reset_ras_error_count(tmp_adev);
4784+ if (tmp_adev->mmhub.ras && tmp_adev->mmhub.ras->ras_block.hw_ops &&
4785+ tmp_adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count)
4786+ tmp_adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count(tmp_adev);
46514787 }
46524788
46534789 amdgpu_ras_intr_cleared();
@@ -4754,17 +4890,8 @@ end: · 100 unmodified lines
47544890 return r;
47554891 }
47564892
4757−static bool amdgpu_device_lock_adev(struct amdgpu_device *adev,
4758− struct amdgpu_hive_info *hive)
4893+static void amdgpu_device_set_mp1_state(struct amdgpu_device *adev)
47594894 {
4760− if (atomic_cmpxchg(&adev->in_gpu_reset, 0, 1) != 0)
4761− return false;
4762−
4763− if (hive) {
4764− down_write_nest_lock(&adev->reset_sem, &hive->hive_lock);
4765− } else {
4766− down_write(&adev->reset_sem);
4767− }
47684895
47694896 switch (amdgpu_asic_reset_method(adev)) {
47704897 case AMD_RESET_METHOD_MODE1:
@@ -4777,56 +4904,12 @@ static bool amdgpu_device_lock_adev(struct amdgpu_device *adev, · 6 unmodified lines
47774904 adev->mp1_state = PP_MP1_STATE_NONE;
47784905 break;
47794906 }
4780−
4781− return true;
47824907 }
47834908
4784−static void amdgpu_device_unlock_adev(struct amdgpu_device *adev)
4909+static void amdgpu_device_unset_mp1_state(struct amdgpu_device *adev)
47854910 {
47864911 amdgpu_vf_error_trans_all(adev);
47874912 adev->mp1_state = PP_MP1_STATE_NONE;
4788− atomic_set(&adev->in_gpu_reset, 0);
4789− up_write(&adev->reset_sem);
4790−}
4791−
4792−/*
4793− * to lockup a list of amdgpu devices in a hive safely, if not a hive
4794− * with multiple nodes, it will be similar as amdgpu_device_lock_adev.
4795− *
4796− * unlock won't require roll back.
4797− */
4798−static int amdgpu_device_lock_hive_adev(struct amdgpu_device *adev, struct amdgpu_hive_info *hive)
4799−{
4800− struct amdgpu_device *tmp_adev = NULL;
4801−
4802− if (!amdgpu_sriov_vf(adev) && (adev->gmc.xgmi.num_physical_nodes > 1)) {
4803− if (!hive) {
4804− dev_err(adev->dev, "Hive is NULL while device has multiple xgmi nodes");
4805− return -ENODEV;
4806− }
4807− list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
4808− if (!amdgpu_device_lock_adev(tmp_adev, hive))
4809− goto roll_back;
4810− }
4811− } else if (!amdgpu_device_lock_adev(adev, hive))
4812− return -EAGAIN;
4813−
4814− return 0;
4815−roll_back:
4816− if (!list_is_first(&tmp_adev->gmc.xgmi.head, &hive->device_list)) {
4817− /*
4818− * if the lockup iteration break in the middle of a hive,
4819− * it may means there may has a race issue,
4820− * or a hive device locked up independently.
4821− * we may be in trouble and may not, so will try to roll back
4822− * the lock and give out a warnning.
4823− */
4824− dev_warn(tmp_adev->dev, "Hive lock iteration broke in the middle. Rolling back to unlock");
4825− list_for_each_entry_continue_reverse(tmp_adev, &hive->device_list, gmc.xgmi.head) {
4826− amdgpu_device_unlock_adev(tmp_adev);
4827− }
4828− }
4829− return -EAGAIN;
48304913 }
48314914
48324915 static void amdgpu_device_resume_display_audio(struct amdgpu_device *adev)
@@ -4960,7 +5043,7 @@ retry: · 127 unmodified lines
49605043 }
49615044
49625045 /**
4963− * amdgpu_device_gpu_recover - reset the asic and recover scheduler
5046+ * amdgpu_device_gpu_recover_imp - reset the asic and recover scheduler
49645047 *
49655048 * @adev: amdgpu_device pointer
49665049 * @job: which job trigger hang
@@ -4970,7 +5053,7 @@ retry: · 3 unmodified lines
49705053 * Returns 0 for success or an error on failure.
49715054 */
49725055
4973−int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
5056+int amdgpu_device_gpu_recover_imp(struct amdgpu_device *adev,
49745057 struct amdgpu_job *job)
49755058 {
49765059 struct list_head device_list, *device_list_handle = NULL;
@@ -5004,26 +5087,10 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, · 27 unmodified lines
50045087 dev_info(adev->dev, "GPU %s begin!\n",
50055088 need_emergency_restart ? "jobs stop":"reset");
50065089
5007− /*
5008− * Here we trylock to avoid chain of resets executing from
5009− * either trigger by jobs on different adevs in XGMI hive or jobs on
5010− * different schedulers for same device while this TO handler is running.
5011− * We always reset all schedulers for device and all devices for XGMI
5012− * hive so that should take care of them too.
5013− */
50145090 if (!amdgpu_sriov_vf(adev))
50155091 hive = amdgpu_get_xgmi_hive(adev);
5016− if (hive) {
5017− if (atomic_cmpxchg(&hive->in_reset, 0, 1) != 0) {
5018− DRM_INFO("Bailing on TDR for s_job:%llx, hive: %llx as another already in progress",
5019− job ? job->base.id : -1, hive->hive_id);
5020− amdgpu_put_xgmi_hive(hive);
5021− if (job && job->vm)
5022− drm_sched_increase_karma(&job->base);
5023− return 0;
5024− }
5092+ if (hive)
50255093 mutex_lock(&hive->hive_lock);
5026− }
50275094
50285095 reset_context.method = AMD_RESET_METHOD_NONE;
50295096 reset_context.reset_req_dev = adev;
@@ -5031,22 +5098,6 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, · 1 unmodified line
50315098 reset_context.hive = hive;
50325099 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
50335100
5034− /*
5035− * lock the device before we try to operate the linked list
5036− * if didn't get the device lock, don't touch the linked list since
5037− * others may iterating it.
5038− */
5039− r = amdgpu_device_lock_hive_adev(adev, hive);
5040− if (r) {
5041− dev_info(adev->dev, "Bailing on TDR for s_job:%llx, as another already in progress",
5042− job ? job->base.id : -1);
5043−
5044− /* even we skipped this reset, still need to set the job to guilty */
5045− if (job && job->vm)
5046− drm_sched_increase_karma(&job->base);
5047− goto skip_recovery;
5048− }
5049−
50505101 /*
50515102 * Build list of devices to reset.
50525103 * In case we are in XGMI hive mode, resort the device list
@@ -5064,8 +5115,16 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, · 11 unmodified lines
50645115 device_list_handle = &device_list;
50655116 }
50665117
5118+ /* We need to lock reset domain only once both for XGMI and single device */
5119+ tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
5120+ reset_list);
5121+ amdgpu_device_lock_reset_domain(tmp_adev->reset_domain);
5122+
50675123 /* block all schedulers and reset given job's ring */
50685124 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5125+
5126+ amdgpu_device_set_mp1_state(tmp_adev);
5127+
50695128 /*
50705129 * Try to put the audio codec into suspend state
50715130 * before gpu reset started.
@@ -5187,6 +5246,9 @@ skip_hw_reset: · 115 unmodified lines
51875246 drm_helper_resume_force_mode(adev_to_drm(tmp_adev));
51885247 }
51895248
5249+ if (tmp_adev->asic_reset_res)
5250+ r = tmp_adev->asic_reset_res;
5251+
51905252 tmp_adev->asic_reset_res = 0;
51915253
51925254 if (r) {
@@ -5214,21 +5276,55 @@ skip_sched_resume: · 21 unmodified lines
52145276
52155277 if (audio_suspended)
52165278 amdgpu_device_resume_display_audio(tmp_adev);
5217− amdgpu_device_unlock_adev(tmp_adev);
5279+
5280+ amdgpu_device_unset_mp1_state(tmp_adev);
52185281 }
52195282
5220−skip_recovery:
5283+ tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
5284+ reset_list);
5285+ amdgpu_device_unlock_reset_domain(tmp_adev->reset_domain);
5286+
52215287 if (hive) {
5222− atomic_set(&hive->in_reset, 0);
52235288 mutex_unlock(&hive->hive_lock);
52245289 amdgpu_put_xgmi_hive(hive);
52255290 }
52265291
5227− if (r && r != -EAGAIN)
5292+ if (r)
52285293 dev_info(adev->dev, "GPU reset end with ret = %d\n", r);
52295294 return r;
52305295 }
52315296
5297+struct amdgpu_recover_work_struct {
5298+ struct work_struct base;
5299+ struct amdgpu_device *adev;
5300+ struct amdgpu_job *job;
5301+ int ret;
5302+};
5303+
5304+static void amdgpu_device_queue_gpu_recover_work(struct work_struct *work)
5305+{
5306+ struct amdgpu_recover_work_struct *recover_work = container_of(work, struct amdgpu_recover_work_struct, base);
5307+
5308+ recover_work->ret = amdgpu_device_gpu_recover_imp(recover_work->adev, recover_work->job);
5309+}
5310+/*
5311+ * Serialize gpu recover into reset domain single threaded wq
5312+ */
5313+int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
5314+ struct amdgpu_job *job)
5315+{
5316+ struct amdgpu_recover_work_struct work = {.adev = adev, .job = job};
5317+
5318+ INIT_WORK(&work.base, amdgpu_device_queue_gpu_recover_work);
5319+
5320+ if (!amdgpu_reset_domain_schedule(adev->reset_domain, &work.base))
5321+ return -EAGAIN;
5322+
5323+ flush_work(&work.base);
5324+
5325+ return work.ret;
5326+}
5327+
52325328 /**
52335329 * amdgpu_device_get_pcie_info - fence pcie info about the PCIE slot
52345330 *
@@ -5416,20 +5512,6 @@ int amdgpu_device_baco_exit(struct drm_device *dev) · 181 unmodified lines
54165512 return 0;
54175513 }
54185514
5419−static void amdgpu_cancel_all_tdr(struct amdgpu_device *adev)
5420−{
5421− int i;
5422−
5423− for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
5424− struct amdgpu_ring *ring = adev->rings[i];
5425−
5426− if (!ring || !ring->sched.thread)
5427− continue;
5428−
5429− cancel_delayed_work_sync(&ring->sched.work_tdr);
5430− }
5431−}
5432−
54335515 /**
54345516 * amdgpu_pci_error_detected - Called when a PCI error is detected.
54355517 * @pdev: PCI device struct
@@ -5460,14 +5542,11 @@ pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, pci_channel_sta · 24 unmodified lines
54605542 /* Fatal error, prepare for slot reset */
54615543 case pci_channel_io_frozen:
54625544 /*
5463− * Cancel and wait for all TDRs in progress if failing to
5464− * set adev->in_gpu_reset in amdgpu_device_lock_adev
5465− *
5466− * Locking adev->reset_sem will prevent any external access
5545+ * Locking adev->reset_domain->sem will prevent any external access
54675546 * to GPU during PCI error recovery
54685547 */
5469− while (!amdgpu_device_lock_adev(adev, NULL))
5470− amdgpu_cancel_all_tdr(adev);
5548+ amdgpu_device_lock_reset_domain(adev->reset_domain);
5549+ amdgpu_device_set_mp1_state(adev);
54715550
54725551 /*
54735552 * Block any work scheduling as we do for regular GPU reset
@@ -5574,7 +5653,8 @@ out: · 100 unmodified lines
55745653 DRM_INFO("PCIe error recovery succeeded\n");
55755654 } else {
55765655 DRM_ERROR("PCIe error recovery failed, err:%d", r);
5577− amdgpu_device_unlock_adev(adev);
5656+ amdgpu_device_unset_mp1_state(adev);
5657+ amdgpu_device_unlock_reset_domain(adev->reset_domain);
55785658 }
55795659
55805660 return r ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
@@ -5611,7 +5691,8 @@ void amdgpu_pci_resume(struct pci_dev *pdev) · 30 unmodified lines
56115691 drm_sched_start(&ring->sched, true);
56125692 }
56135693
5614− amdgpu_device_unlock_adev(adev);
5694+ amdgpu_device_unset_mp1_state(adev);
5695+ amdgpu_device_unlock_reset_domain(adev->reset_domain);
56155696 }
56165697
56175698 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev)
@@ -5688,6 +5769,11 @@ void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, · 70 unmodified lines
56885769 amdgpu_asic_invalidate_hdp(adev, ring);
56895770 }
56905771
5772+int amdgpu_in_reset(struct amdgpu_device *adev)
5773+{
5774+ return atomic_read(&adev->reset_domain->in_gpu_reset);
5775+ }
5776+
56915777 /**
56925778 * amdgpu_device_halt() - bring hardware to some kind of halt state
56935779 *
@@ -5726,3 +5812,36 @@ void amdgpu_device_halt(struct amdgpu_device *adev) · 32 unmodified lines
57265812 pci_disable_device(pdev);
57275813 pci_wait_for_pending_transaction(pdev);
57285814 }
5815+
5816+u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev,
5817+ u32 reg)
5818+{
5819+ unsigned long flags, address, data;
5820+ u32 r;
5821+
5822+ address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
5823+ data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
5824+
5825+ spin_lock_irqsave(&adev->pcie_idx_lock, flags);
5826+ WREG32(address, reg * 4);
5827+ (void)RREG32(address);
5828+ r = RREG32(data);
5829+ spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
5830+ return r;
5831+}
5832+
5833+void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev,
5834+ u32 reg, u32 v)
5835+{
5836+ unsigned long flags, address, data;
5837+
5838+ address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
5839+ data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
5840+
5841+ spin_lock_irqsave(&adev->pcie_idx_lock, flags);
5842+ WREG32(address, reg * 4);
5843+ (void)RREG32(address);
5844+ WREG32(data, v);
5845+ (void)RREG32(data);
5846+ spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
5847+}
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c+544−7
@@ -360,8 +360,11 @@ out: · 359 unmodified lines
360360 return r;
361361 }
362362
363+static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev);
364+
363365 void amdgpu_discovery_fini(struct amdgpu_device *adev)
364366 {
367+ amdgpu_discovery_sysfs_fini(adev);
365368 kfree(adev->mman.discovery_bin);
366369 adev->mman.discovery_bin = NULL;
367370 }
@@ -382,6 +385,497 @@ static int amdgpu_discovery_validate_ip(const struct ip *ip) · 14 unmodified lines
382385 return 0;
383386 }
384387
388+/* ================================================== */
389+
390+struct ip_hw_instance {
391+ struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */
392+
393+ int hw_id;
394+ u8 num_instance;
395+ u8 major, minor, revision;
396+ u8 harvest;
397+
398+ int num_base_addresses;
399+ u32 base_addr[];
400+};
401+
402+struct ip_hw_id {
403+ struct kset hw_id_kset; /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */
404+ int hw_id;
405+};
406+
407+struct ip_die_entry {
408+ struct kset ip_kset; /* ip_discovery/die/#die/, contains ip_hw_id */
409+ u16 num_ips;
410+};
411+
412+/* -------------------------------------------------- */
413+
414+struct ip_hw_instance_attr {
415+ struct attribute attr;
416+ ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf);
417+};
418+
419+static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf)
420+{
421+ return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id);
422+}
423+
424+static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf)
425+{
426+ return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance);
427+}
428+
429+static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf)
430+{
431+ return sysfs_emit(buf, "%d\n", ip_hw_instance->major);
432+}
433+
434+static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf)
435+{
436+ return sysfs_emit(buf, "%d\n", ip_hw_instance->minor);
437+}
438+
439+static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf)
440+{
441+ return sysfs_emit(buf, "%d\n", ip_hw_instance->revision);
442+}
443+
444+static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf)
445+{
446+ return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest);
447+}
448+
449+static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf)
450+{
451+ return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses);
452+}
453+
454+static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf)
455+{
456+ ssize_t res, at;
457+ int ii;
458+
459+ for (res = at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) {
460+ /* Here we satisfy the condition that, at + size <= PAGE_SIZE.
461+ */
462+ if (at + 12 > PAGE_SIZE)
463+ break;
464+ res = sysfs_emit_at(buf, at, "0x%08X\n",
465+ ip_hw_instance->base_addr[ii]);
466+ if (res <= 0)
467+ break;
468+ at += res;
469+ }
470+
471+ return res < 0 ? res : at;
472+}
473+
474+static struct ip_hw_instance_attr ip_hw_attr[] = {
475+ __ATTR_RO(hw_id),
476+ __ATTR_RO(num_instance),
477+ __ATTR_RO(major),
478+ __ATTR_RO(minor),
479+ __ATTR_RO(revision),
480+ __ATTR_RO(harvest),
481+ __ATTR_RO(num_base_addresses),
482+ __ATTR_RO(base_addr),
483+};
484+
485+static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1];
486+ATTRIBUTE_GROUPS(ip_hw_instance);
487+
488+#define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj)
489+#define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr)
490+
491+static ssize_t ip_hw_instance_attr_show(struct kobject *kobj,
492+ struct attribute *attr,
493+ char *buf)
494+{
495+ struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj);
496+ struct ip_hw_instance_attr *ip_hw_attr = to_ip_hw_instance_attr(attr);
497+
498+ if (!ip_hw_attr->show)
499+ return -EIO;
500+
501+ return ip_hw_attr->show(ip_hw_instance, buf);
502+}
503+
504+static const struct sysfs_ops ip_hw_instance_sysfs_ops = {
505+ .show = ip_hw_instance_attr_show,
506+};
507+
508+static void ip_hw_instance_release(struct kobject *kobj)
509+{
510+ struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj);
511+
512+ kfree(ip_hw_instance);
513+}
514+
515+static struct kobj_type ip_hw_instance_ktype = {
516+ .release = ip_hw_instance_release,
517+ .sysfs_ops = &ip_hw_instance_sysfs_ops,
518+ .default_groups = ip_hw_instance_groups,
519+};
520+
521+/* -------------------------------------------------- */
522+
523+#define to_ip_hw_id(x) container_of(to_kset(x), struct ip_hw_id, hw_id_kset)
524+
525+static void ip_hw_id_release(struct kobject *kobj)
526+{
527+ struct ip_hw_id *ip_hw_id = to_ip_hw_id(kobj);
528+
529+ if (!list_empty(&ip_hw_id->hw_id_kset.list))
530+ DRM_ERROR("ip_hw_id->hw_id_kset is not empty");
531+ kfree(ip_hw_id);
532+}
533+
534+static struct kobj_type ip_hw_id_ktype = {
535+ .release = ip_hw_id_release,
536+ .sysfs_ops = &kobj_sysfs_ops,
537+};
538+
539+/* -------------------------------------------------- */
540+
541+static void die_kobj_release(struct kobject *kobj);
542+static void ip_disc_release(struct kobject *kobj);
543+
544+struct ip_die_entry_attribute {
545+ struct attribute attr;
546+ ssize_t (*show)(struct ip_die_entry *ip_die_entry, char *buf);
547+};
548+
549+#define to_ip_die_entry_attr(x) container_of(x, struct ip_die_entry_attribute, attr)
550+
551+static ssize_t num_ips_show(struct ip_die_entry *ip_die_entry, char *buf)
552+{
553+ return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips);
554+}
555+
556+/* If there are more ip_die_entry attrs, other than the number of IPs,
557+ * we can make this intro an array of attrs, and then initialize
558+ * ip_die_entry_attrs in a loop.
559+ */
560+static struct ip_die_entry_attribute num_ips_attr =
561+ __ATTR_RO(num_ips);
562+
563+static struct attribute *ip_die_entry_attrs[] = {
564+ &num_ips_attr.attr,
565+ NULL,
566+};
567+ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */
568+
569+#define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset)
570+
571+static ssize_t ip_die_entry_attr_show(struct kobject *kobj,
572+ struct attribute *attr,
573+ char *buf)
574+{
575+ struct ip_die_entry_attribute *ip_die_entry_attr = to_ip_die_entry_attr(attr);
576+ struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj);
577+
578+ if (!ip_die_entry_attr->show)
579+ return -EIO;
580+
581+ return ip_die_entry_attr->show(ip_die_entry, buf);
582+}
583+
584+static void ip_die_entry_release(struct kobject *kobj)
585+{
586+ struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj);
587+
588+ if (!list_empty(&ip_die_entry->ip_kset.list))
589+ DRM_ERROR("ip_die_entry->ip_kset is not empty");
590+ kfree(ip_die_entry);
591+}
592+
593+static const struct sysfs_ops ip_die_entry_sysfs_ops = {
594+ .show = ip_die_entry_attr_show,
595+};
596+
597+static struct kobj_type ip_die_entry_ktype = {
598+ .release = ip_die_entry_release,
599+ .sysfs_ops = &ip_die_entry_sysfs_ops,
600+ .default_groups = ip_die_entry_groups,
601+};
602+
603+static struct kobj_type die_kobj_ktype = {
604+ .release = die_kobj_release,
605+ .sysfs_ops = &kobj_sysfs_ops,
606+};
607+
608+static struct kobj_type ip_discovery_ktype = {
609+ .release = ip_disc_release,
610+ .sysfs_ops = &kobj_sysfs_ops,
611+};
612+
613+struct ip_discovery_top {
614+ struct kobject kobj; /* ip_discovery/ */
615+ struct kset die_kset; /* ip_discovery/die/, contains ip_die_entry */
616+ struct amdgpu_device *adev;
617+};
618+
619+static void die_kobj_release(struct kobject *kobj)
620+{
621+ struct ip_discovery_top *ip_top = container_of(to_kset(kobj),
622+ struct ip_discovery_top,
623+ die_kset);
624+ if (!list_empty(&ip_top->die_kset.list))
625+ DRM_ERROR("ip_top->die_kset is not empty");
626+}
627+
628+static void ip_disc_release(struct kobject *kobj)
629+{
630+ struct ip_discovery_top *ip_top = container_of(kobj, struct ip_discovery_top,
631+ kobj);
632+ struct amdgpu_device *adev = ip_top->adev;
633+
634+ adev->ip_top = NULL;
635+ kfree(ip_top);
636+}
637+
638+static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev,
639+ struct ip_die_entry *ip_die_entry,
640+ const size_t _ip_offset, const int num_ips)
641+{
642+ int ii, jj, kk, res;
643+
644+ DRM_DEBUG("num_ips:%d", num_ips);
645+
646+ /* Find all IPs of a given HW ID, and add their instance to
647+ * #die/#hw_id/#instance/<attributes>
648+ */
649+ for (ii = 0; ii < HW_ID_MAX; ii++) {
650+ struct ip_hw_id *ip_hw_id = NULL;
651+ size_t ip_offset = _ip_offset;
652+
653+ for (jj = 0; jj < num_ips; jj++) {
654+ struct ip *ip;
655+ struct ip_hw_instance *ip_hw_instance;
656+
657+ ip = (struct ip *)(adev->mman.discovery_bin + ip_offset);
658+ if (amdgpu_discovery_validate_ip(ip) ||
659+ le16_to_cpu(ip->hw_id) != ii)
660+ goto next_ip;
661+
662+ DRM_DEBUG("match:%d @ ip_offset:%zu", ii, ip_offset);
663+
664+ /* We have a hw_id match; register the hw
665+ * block if not yet registered.
666+ */
667+ if (!ip_hw_id) {
668+ ip_hw_id = kzalloc(sizeof(*ip_hw_id), GFP_KERNEL);
669+ if (!ip_hw_id)
670+ return -ENOMEM;
671+ ip_hw_id->hw_id = ii;
672+
673+ kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii);
674+ ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset;
675+ ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype;
676+ res = kset_register(&ip_hw_id->hw_id_kset);
677+ if (res) {
678+ DRM_ERROR("Couldn't register ip_hw_id kset");
679+ kfree(ip_hw_id);
680+ return res;
681+ }
682+ if (hw_id_names[ii]) {
683+ res = sysfs_create_link(&ip_die_entry->ip_kset.kobj,
684+ &ip_hw_id->hw_id_kset.kobj,
685+ hw_id_names[ii]);
686+ if (res) {
687+ DRM_ERROR("Couldn't create IP link %s in IP Die:%s\n",
688+ hw_id_names[ii],
689+ kobject_name(&ip_die_entry->ip_kset.kobj));
690+ }
691+ }
692+ }
693+
694+ /* Now register its instance.
695+ */
696+ ip_hw_instance = kzalloc(struct_size(ip_hw_instance,
697+ base_addr,
698+ ip->num_base_address),
699+ GFP_KERNEL);
700+ if (!ip_hw_instance) {
701+ DRM_ERROR("no memory for ip_hw_instance");
702+ return -ENOMEM;
703+ }
704+ ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */
705+ ip_hw_instance->num_instance = ip->number_instance;
706+ ip_hw_instance->major = ip->major;
707+ ip_hw_instance->minor = ip->minor;
708+ ip_hw_instance->revision = ip->revision;
709+ ip_hw_instance->harvest = ip->harvest;
710+ ip_hw_instance->num_base_addresses = ip->num_base_address;
711+
712+ for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++)
713+ ip_hw_instance->base_addr[kk] = ip->base_address[kk];
714+
715+ kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype);
716+ ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset;
717+ res = kobject_add(&ip_hw_instance->kobj, NULL,
718+ "%d", ip_hw_instance->num_instance);
719+next_ip:
720+ ip_offset += sizeof(*ip) + 4 * (ip->num_base_address - 1);
721+ }
722+ }
723+
724+ return 0;
725+}
726+
727+static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev)
728+{
729+ struct binary_header *bhdr;
730+ struct ip_discovery_header *ihdr;
731+ struct die_header *dhdr;
732+ struct kset *die_kset = &adev->ip_top->die_kset;
733+ u16 num_dies, die_offset, num_ips;
734+ size_t ip_offset;
735+ int ii, res;
736+
737+ bhdr = (struct binary_header *)adev->mman.discovery_bin;
738+ ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
739+ le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
740+ num_dies = le16_to_cpu(ihdr->num_dies);
741+
742+ DRM_DEBUG("number of dies: %d\n", num_dies);
743+
744+ for (ii = 0; ii < num_dies; ii++) {
745+ struct ip_die_entry *ip_die_entry;
746+
747+ die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset);
748+ dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
749+ num_ips = le16_to_cpu(dhdr->num_ips);
750+ ip_offset = die_offset + sizeof(*dhdr);
751+
752+ /* Add the die to the kset.
753+ *
754+ * dhdr->die_id == ii, which was checked in
755+ * amdgpu_discovery_reg_base_init().
756+ */
757+
758+ ip_die_entry = kzalloc(sizeof(*ip_die_entry), GFP_KERNEL);
759+ if (!ip_die_entry)
760+ return -ENOMEM;
761+
762+ ip_die_entry->num_ips = num_ips;
763+
764+ kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id));
765+ ip_die_entry->ip_kset.kobj.kset = die_kset;
766+ ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype;
767+ res = kset_register(&ip_die_entry->ip_kset);
768+ if (res) {
769+ DRM_ERROR("Couldn't register ip_die_entry kset");
770+ kfree(ip_die_entry);
771+ return res;
772+ }
773+
774+ amdgpu_discovery_sysfs_ips(adev, ip_die_entry, ip_offset, num_ips);
775+ }
776+
777+ return 0;
778+}
779+
780+static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev)
781+{
782+ struct kset *die_kset;
783+ int res, ii;
784+
785+ adev->ip_top = kzalloc(sizeof(*adev->ip_top), GFP_KERNEL);
786+ if (!adev->ip_top)
787+ return -ENOMEM;
788+
789+ adev->ip_top->adev = adev;
790+
791+ res = kobject_init_and_add(&adev->ip_top->kobj, &ip_discovery_ktype,
792+ &adev->dev->kobj, "ip_discovery");
793+ if (res) {
794+ DRM_ERROR("Couldn't init and add ip_discovery/");
795+ goto Err;
796+ }
797+
798+ die_kset = &adev->ip_top->die_kset;
799+ kobject_set_name(&die_kset->kobj, "%s", "die");
800+ die_kset->kobj.parent = &adev->ip_top->kobj;
801+ die_kset->kobj.ktype = &die_kobj_ktype;
802+ res = kset_register(&adev->ip_top->die_kset);
803+ if (res) {
804+ DRM_ERROR("Couldn't register die_kset");
805+ goto Err;
806+ }
807+
808+ for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++)
809+ ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr;
810+ ip_hw_instance_attrs[ii] = NULL;
811+
812+ res = amdgpu_discovery_sysfs_recurse(adev);
813+
814+ return res;
815+Err:
816+ kobject_put(&adev->ip_top->kobj);
817+ return res;
818+}
819+
820+/* -------------------------------------------------- */
821+
822+#define list_to_kobj(el) container_of(el, struct kobject, entry)
823+
824+static void amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id *ip_hw_id)
825+{
826+ struct list_head *el, *tmp;
827+ struct kset *hw_id_kset;
828+
829+ hw_id_kset = &ip_hw_id->hw_id_kset;
830+ spin_lock(&hw_id_kset->list_lock);
831+ list_for_each_prev_safe(el, tmp, &hw_id_kset->list) {
832+ list_del_init(el);
833+ spin_unlock(&hw_id_kset->list_lock);
834+ /* kobject is embedded in ip_hw_instance */
835+ kobject_put(list_to_kobj(el));
836+ spin_lock(&hw_id_kset->list_lock);
837+ }
838+ spin_unlock(&hw_id_kset->list_lock);
839+ kobject_put(&ip_hw_id->hw_id_kset.kobj);
840+}
841+
842+static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry)
843+{
844+ struct list_head *el, *tmp;
845+ struct kset *ip_kset;
846+
847+ ip_kset = &ip_die_entry->ip_kset;
848+ spin_lock(&ip_kset->list_lock);
849+ list_for_each_prev_safe(el, tmp, &ip_kset->list) {
850+ list_del_init(el);
851+ spin_unlock(&ip_kset->list_lock);
852+ amdgpu_discovery_sysfs_ip_hw_free(to_ip_hw_id(list_to_kobj(el)));
853+ spin_lock(&ip_kset->list_lock);
854+ }
855+ spin_unlock(&ip_kset->list_lock);
856+ kobject_put(&ip_die_entry->ip_kset.kobj);
857+}
858+
859+static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev)
860+{
861+ struct list_head *el, *tmp;
862+ struct kset *die_kset;
863+
864+ die_kset = &adev->ip_top->die_kset;
865+ spin_lock(&die_kset->list_lock);
866+ list_for_each_prev_safe(el, tmp, &die_kset->list) {
867+ list_del_init(el);
868+ spin_unlock(&die_kset->list_lock);
869+ amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el)));
870+ spin_lock(&die_kset->list_lock);
871+ }
872+ spin_unlock(&die_kset->list_lock);
873+ kobject_put(&adev->ip_top->die_kset.kobj);
874+ kobject_put(&adev->ip_top->kobj);
875+}
876+
877+/* ================================================== */
878+
385879 int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
386880 {
387881 struct binary_header *bhdr;
@@ -492,6 +986,8 @@ next_ip: · 104 unmodified lines
492986 }
493987 }
494988
989+ amdgpu_discovery_sysfs_init(adev);
990+
495991 return 0;
496992 }
497993
@@ -674,12 +1170,15 @@ static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev) · 176 unmodified lines
6741170 case IP_VERSION(10, 1, 1):
6751171 case IP_VERSION(10, 1, 2):
6761172 case IP_VERSION(10, 1, 3):
1173+ case IP_VERSION(10, 1, 4):
6771174 case IP_VERSION(10, 3, 0):
6781175 case IP_VERSION(10, 3, 1):
6791176 case IP_VERSION(10, 3, 2):
6801177 case IP_VERSION(10, 3, 3):
6811178 case IP_VERSION(10, 3, 4):
6821179 case IP_VERSION(10, 3, 5):
1180+ case IP_VERSION(10, 3, 6):
1181+ case IP_VERSION(10, 3, 7):
6831182 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
6841183 break;
6851184 default:
@@ -709,12 +1208,15 @@ static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev) · 23 unmodified lines
7091208 case IP_VERSION(10, 1, 1):
7101209 case IP_VERSION(10, 1, 2):
7111210 case IP_VERSION(10, 1, 3):
1211+ case IP_VERSION(10, 1, 4):
7121212 case IP_VERSION(10, 3, 0):
7131213 case IP_VERSION(10, 3, 1):
7141214 case IP_VERSION(10, 3, 2):
7151215 case IP_VERSION(10, 3, 3):
7161216 case IP_VERSION(10, 3, 4):
7171217 case IP_VERSION(10, 3, 5):
1218+ case IP_VERSION(10, 3, 6):
1219+ case IP_VERSION(10, 3, 7):
7181220 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
7191221 break;
7201222 default:
@@ -790,6 +1292,7 @@ static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev) · 69 unmodified lines
7901292 case IP_VERSION(13, 0, 1):
7911293 case IP_VERSION(13, 0, 2):
7921294 case IP_VERSION(13, 0, 3):
1295+ case IP_VERSION(13, 0, 8):
7931296 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
7941297 break;
7951298 default:
@@ -831,6 +1334,7 @@ static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev) · 35 unmodified lines
8311334 case IP_VERSION(13, 0, 1):
8321335 case IP_VERSION(13, 0, 2):
8331336 case IP_VERSION(13, 0, 3):
1337+ case IP_VERSION(13, 0, 8):
8341338 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
8351339 break;
8361340 default:
@@ -846,8 +1350,14 @@ static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev) · 9 unmodified lines
8461350 {
8471351 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) {
8481352 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
1353+ return 0;
1354+ }
1355+
1356+ if (!amdgpu_device_has_dc_support(adev))
1357+ return 0;
1358+
8491359 #if defined(CONFIG_DRM_AMD_DC)
850− } else if (adev->ip_versions[DCE_HWIP][0]) {
1360+ if (adev->ip_versions[DCE_HWIP][0]) {
8511361 switch (adev->ip_versions[DCE_HWIP][0]) {
8521362 case IP_VERSION(1, 0, 0):
8531363 case IP_VERSION(1, 0, 1):
@@ -861,6 +1371,7 @@ static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev) · 7 unmodified lines
8611371 case IP_VERSION(3, 0, 1):
8621372 case IP_VERSION(3, 1, 2):
8631373 case IP_VERSION(3, 1, 3):
1374+ case IP_VERSION(3, 1, 6):
8641375 amdgpu_device_ip_block_add(adev, &dm_ip_block);
8651376 break;
8661377 default:
@@ -882,8 +1393,8 @@ static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev) · 15 unmodified lines
8821393 adev->ip_versions[DCI_HWIP][0]);
8831394 return -EINVAL;
8841395 }
885−#endif
8861396 }
1397+#endif
8871398 return 0;
8881399 }
8891400
@@ -904,12 +1415,15 @@ static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) · 14 unmodified lines
9041415 case IP_VERSION(10, 1, 2):
9051416 case IP_VERSION(10, 1, 1):
9061417 case IP_VERSION(10, 1, 3):
1418+ case IP_VERSION(10, 1, 4):
9071419 case IP_VERSION(10, 3, 0):
9081420 case IP_VERSION(10, 3, 2):
9091421 case IP_VERSION(10, 3, 1):
9101422 case IP_VERSION(10, 3, 4):
9111423 case IP_VERSION(10, 3, 5):
1424+ case IP_VERSION(10, 3, 6):
9121425 case IP_VERSION(10, 3, 3):
1426+ case IP_VERSION(10, 3, 7):
9131427 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
9141428 break;
9151429 default:
@@ -946,6 +1460,7 @@ static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev) · 30 unmodified lines
9461460 case IP_VERSION(5, 2, 5):
9471461 case IP_VERSION(5, 2, 3):
9481462 case IP_VERSION(5, 2, 1):
1463+ case IP_VERSION(5, 2, 7):
9491464 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
9501465 break;
9511466 default:
@@ -1038,12 +1553,14 @@ static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev) · 86 unmodified lines
10381553 case IP_VERSION(10, 1, 1):
10391554 case IP_VERSION(10, 1, 2):
10401555 case IP_VERSION(10, 1, 3):
1556+ case IP_VERSION(10, 1, 4):
10411557 case IP_VERSION(10, 3, 0):
10421558 case IP_VERSION(10, 3, 1):
10431559 case IP_VERSION(10, 3, 2):
10441560 case IP_VERSION(10, 3, 3):
10451561 case IP_VERSION(10, 3, 4):
10461562 case IP_VERSION(10, 3, 5):
1563+ case IP_VERSION(10, 3, 6):
10471564 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
10481565 break;
10491566 default:
@@ -1217,11 +1734,6 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) · 167 unmodified lines
12171734 return -EINVAL;
12181735
12191736 amdgpu_discovery_harvest_ip(adev);
1220−
1221− if (!adev->mman.discovery_bin) {
1222− DRM_ERROR("ip discovery uninitialized\n");
1223− return -EINVAL;
1224− }
12251737 break;
12261738 }
12271739
@@ -1242,6 +1754,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) · 14 unmodified lines
12421754 case IP_VERSION(10, 1, 1):
12431755 case IP_VERSION(10, 1, 2):
12441756 case IP_VERSION(10, 1, 3):
1757+ case IP_VERSION(10, 1, 4):
12451758 case IP_VERSION(10, 3, 0):
12461759 case IP_VERSION(10, 3, 2):
12471760 case IP_VERSION(10, 3, 4):
@@ -1254,10 +1767,32 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) · 6 unmodified lines
12541767 case IP_VERSION(10, 3, 3):
12551768 adev->family = AMDGPU_FAMILY_YC;
12561769 break;
1770+ case IP_VERSION(10, 3, 6):
1771+ adev->family = AMDGPU_FAMILY_GC_10_3_6;
1772+ break;
1773+ case IP_VERSION(10, 3, 7):
1774+ adev->family = AMDGPU_FAMILY_GC_10_3_7;
1775+ break;
12571776 default:
12581777 return -EINVAL;
12591778 }
12601779
1780+ switch (adev->ip_versions[GC_HWIP][0]) {
1781+ case IP_VERSION(9, 1, 0):
1782+ case IP_VERSION(9, 2, 2):
1783+ case IP_VERSION(9, 3, 0):
1784+ case IP_VERSION(10, 1, 3):
1785+ case IP_VERSION(10, 1, 4):
1786+ case IP_VERSION(10, 3, 1):
1787+ case IP_VERSION(10, 3, 3):
1788+ case IP_VERSION(10, 3, 6):
1789+ case IP_VERSION(10, 3, 7):
1790+ adev->flags |= AMD_IS_APU;
1791+ break;
1792+ default:
1793+ break;
1794+ }
1795+
12611796 if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(4, 8, 0))
12621797 adev->gmc.xgmi.supported = true;
12631798
@@ -1286,6 +1821,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) · 22 unmodified lines
12861821 case IP_VERSION(7, 2, 0):
12871822 case IP_VERSION(7, 2, 1):
12881823 case IP_VERSION(7, 5, 0):
1824+ case IP_VERSION(7, 5, 1):
12891825 adev->nbio.funcs = &nbio_v7_2_funcs;
12901826 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg;
12911827 break;
@@ -1368,6 +1904,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) · 76 unmodified lines
13681904 case IP_VERSION(11, 0, 11):
13691905 case IP_VERSION(11, 5, 0):
13701906 case IP_VERSION(13, 0, 1):
1907+ case IP_VERSION(13, 0, 9):
13711908 adev->smuio.funcs = &smuio_v11_0_6_funcs;
13721909 break;
13731910 case IP_VERSION(13, 0, 2):
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c+20−15
@@ -512,19 +512,24 @@ uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev, · 511 unmodified lines
512512 case CHIP_STONEY:
513513 domain |= AMDGPU_GEM_DOMAIN_GTT;
514514 break;
515− case CHIP_RAVEN:
516− /* enable S/G on PCO and RV2 */
517− if ((adev->apu_flags & AMD_APU_IS_RAVEN2) ||
518− (adev->apu_flags & AMD_APU_IS_PICASSO))
519− domain |= AMDGPU_GEM_DOMAIN_GTT;
520− break;
521− case CHIP_RENOIR:
522− case CHIP_VANGOGH:
523− case CHIP_YELLOW_CARP:
524− domain |= AMDGPU_GEM_DOMAIN_GTT;
525− break;
526−
527515 default:
516+ switch (adev->ip_versions[DCE_HWIP][0]) {
517+ case IP_VERSION(1, 0, 0):
518+ case IP_VERSION(1, 0, 1):
519+ /* enable S/G on PCO and RV2 */
520+ if ((adev->apu_flags & AMD_APU_IS_RAVEN2) ||
521+ (adev->apu_flags & AMD_APU_IS_PICASSO))
522+ domain |= AMDGPU_GEM_DOMAIN_GTT;
523+ break;
524+ case IP_VERSION(2, 1, 0):
525+ case IP_VERSION(3, 0, 1):
526+ case IP_VERSION(3, 1, 2):
527+ case IP_VERSION(3, 1, 3):
528+ domain |= AMDGPU_GEM_DOMAIN_GTT;
529+ break;
530+ default:
531+ break;
532+ }
528533 break;
529534 }
530535 }
@@ -956,7 +961,7 @@ static int amdgpu_display_verify_sizes(struct amdgpu_framebuffer *rfb) · 425 unmodified lines
956961 int ret;
957962 unsigned int i, block_width, block_height, block_size_log2;
958963
959− if (!rfb->base.dev->mode_config.allow_fb_modifiers)
964+ if (rfb->base.dev->mode_config.fb_modifiers_not_supported)
960965 return 0;
961966
962967 for (i = 0; i < format_info->num_planes; ++i) {
@@ -1143,7 +1148,7 @@ int amdgpu_display_framebuffer_init(struct drm_device *dev, · 180 unmodified lines
11431148 if (ret)
11441149 return ret;
11451150
1146− if (!dev->mode_config.allow_fb_modifiers) {
1151+ if (dev->mode_config.fb_modifiers_not_supported) {
11471152 drm_WARN_ONCE(dev, adev->family >= AMDGPU_FAMILY_AI,
11481153 "GFX9+ requires FB check based on format modifier\n");
11491154 ret = check_tiling_flags_gfx6(rfb);
@@ -1151,7 +1156,7 @@ int amdgpu_display_framebuffer_init(struct drm_device *dev, · 1 unmodified line
11511156 return ret;
11521157 }
11531158
1154− if (dev->mode_config.allow_fb_modifiers &&
1159+ if (!dev->mode_config.fb_modifiers_not_supported &&
11551160 !(rfb->base.flags & DRM_MODE_FB_MODIFIERS)) {
11561161 ret = convert_tiling_flags_to_modifier(rfb);
11571162 if (ret) {
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c+87−34
@@ -99,9 +99,10 @@ · 98 unmodified lines
9999 * - 3.42.0 - Add 16bpc fixed point display support
100100 * - 3.43.0 - Add device hot plug/unplug support
101101 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B
102+ * - 3.45.0 - Add context ioctl stable pstate interface
102103 */
103104 #define KMS_DRIVER_MAJOR 3
104−#define KMS_DRIVER_MINOR 44
105+#define KMS_DRIVER_MINOR 45
105106 #define KMS_DRIVER_PATCHLEVEL 0
106107
107108 int amdgpu_vram_limit;
@@ -174,7 +175,6 @@ int amdgpu_mes; · 66 unmodified lines
174175 int amdgpu_noretry = -1;
175176 int amdgpu_force_asic_type = -1;
176177 int amdgpu_tmz = -1; /* auto */
177−uint amdgpu_freesync_vid_mode;
178178 int amdgpu_reset_method = -1; /* auto */
179179 int amdgpu_num_kcq = -1;
180180 int amdgpu_smartshift_bias;
@@ -843,32 +843,6 @@ module_param_named(backlight, amdgpu_backlight, bint, 0444); · 662 unmodified lines
843843 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)");
844844 module_param_named(tmz, amdgpu_tmz, int, 0444);
845845
846−/**
847− * DOC: freesync_video (uint)
848− * Enable the optimization to adjust front porch timing to achieve seamless
849− * mode change experience when setting a freesync supported mode for which full
850− * modeset is not needed.
851− *
852− * The Display Core will add a set of modes derived from the base FreeSync
853− * video mode into the corresponding connector's mode list based on commonly
854− * used refresh rates and VRR range of the connected display, when users enable
855− * this feature. From the userspace perspective, they can see a seamless mode
856− * change experience when the change between different refresh rates under the
857− * same resolution. Additionally, userspace applications such as Video playback
858− * can read this modeset list and change the refresh rate based on the video
859− * frame rate. Finally, the userspace can also derive an appropriate mode for a
860− * particular refresh rate based on the FreeSync Mode and add it to the
861− * connector's mode list.
862− *
863− * Note: This is an experimental feature.
864− *
865− * The default value: 0 (off).
866− */
867−MODULE_PARM_DESC(
868− freesync_video,
869− "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)");
870−module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444);
871−
872846 /**
873847 * DOC: reset_method (int)
874848 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco, 5 = pci)
@@ -1942,13 +1916,14 @@ static const struct pci_device_id pciidlist[] = { · 1067 unmodified lines
19421916 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
19431917
19441918 /* Aldebaran */
1945− {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT},
1946− {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT},
1947− {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT},
1948− {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT},
1919+ {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1920+ {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1921+ {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1922+ {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
19491923
19501924 /* CYAN_SKILLFISH */
19511925 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
1926+ {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
19521927
19531928 /* BEIGE_GOBY */
19541929 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
@@ -1994,6 +1969,28 @@ static bool amdgpu_is_fw_framebuffer(resource_size_t base, · 39 unmodified lines
19941969 return found;
19951970 }
19961971
1972+static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev)
1973+{
1974+ struct pci_dev *p = NULL;
1975+ int i;
1976+
1977+ /* 0 - GPU
1978+ * 1 - audio
1979+ * 2 - USB
1980+ * 3 - UCSI
1981+ */
1982+ for (i = 1; i < 4; i++) {
1983+ p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
1984+ adev->pdev->bus->number, i);
1985+ if (p) {
1986+ pm_runtime_get_sync(&p->dev);
1987+ pm_runtime_mark_last_busy(&p->dev);
1988+ pm_runtime_put_autosuspend(&p->dev);
1989+ pci_dev_put(p);
1990+ }
1991+ }
1992+}
1993+
19971994 static int amdgpu_pci_probe(struct pci_dev *pdev,
19981995 const struct pci_device_id *ent)
19991996 {
@@ -2126,6 +2123,48 @@ retry_init: · 126 unmodified lines
21262123 if (ret)
21272124 DRM_ERROR("Creating debugfs files failed (%d).\n", ret);
21282125
2126+ if (adev->runpm) {
2127+ /* only need to skip on ATPX */
2128+ if (amdgpu_device_supports_px(ddev))
2129+ dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
2130+ /* we want direct complete for BOCO */
2131+ if (amdgpu_device_supports_boco(ddev))
2132+ dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE |
2133+ DPM_FLAG_SMART_SUSPEND |
2134+ DPM_FLAG_MAY_SKIP_RESUME);
2135+ pm_runtime_use_autosuspend(ddev->dev);
2136+ pm_runtime_set_autosuspend_delay(ddev->dev, 5000);
2137+
2138+ pm_runtime_allow(ddev->dev);
2139+
2140+ pm_runtime_mark_last_busy(ddev->dev);
2141+ pm_runtime_put_autosuspend(ddev->dev);
2142+
2143+ /*
2144+ * For runpm implemented via BACO, PMFW will handle the
2145+ * timing for BACO in and out:
2146+ * - put ASIC into BACO state only when both video and
2147+ * audio functions are in D3 state.
2148+ * - pull ASIC out of BACO state when either video or
2149+ * audio function is in D0 state.
2150+ * Also, at startup, PMFW assumes both functions are in
2151+ * D0 state.
2152+ *
2153+ * So if snd driver was loaded prior to amdgpu driver
2154+ * and audio function was put into D3 state, there will
2155+ * be no PMFW-aware D-state transition(D0->D3) on runpm
2156+ * suspend. Thus the BACO will be not correctly kicked in.
2157+ *
2158+ * Via amdgpu_get_secondary_funcs(), the audio dev is put
2159+ * into D0 state. Then there will be a PMFW-aware D-state
2160+ * transition(D0->D3) on runpm suspend.
2161+ */
2162+ if (amdgpu_device_supports_baco(ddev) &&
2163+ !(adev->flags & AMD_IS_APU) &&
2164+ (adev->asic_type >= CHIP_NAVI10))
2165+ amdgpu_get_secondary_funcs(adev);
2166+ }
2167+
21292168 return 0;
21302169
21312170 err_pci:
@@ -2137,8 +2176,15 @@ static void · 5 unmodified lines
21372176 amdgpu_pci_remove(struct pci_dev *pdev)
21382177 {
21392178 struct drm_device *dev = pci_get_drvdata(pdev);
2179+ struct amdgpu_device *adev = drm_to_adev(dev);
21402180
21412181 drm_dev_unplug(dev);
2182+
2183+ if (adev->runpm) {
2184+ pm_runtime_get_sync(dev->dev);
2185+ pm_runtime_forbid(dev->dev);
2186+ }
2187+
21422188 amdgpu_driver_unload_kms(dev);
21432189
21442190 /*
@@ -2246,13 +2292,20 @@ static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) · 101 unmodified lines
22462292 static int amdgpu_pmops_prepare(struct device *dev)
22472293 {
22482294 struct drm_device *drm_dev = dev_get_drvdata(dev);
2295+ struct amdgpu_device *adev = drm_to_adev(drm_dev);
22492296
22502297 /* Return a positive number here so
22512298 * DPM_FLAG_SMART_SUSPEND works properly
22522299 */
22532300 if (amdgpu_device_supports_boco(drm_dev))
2254− return pm_runtime_suspended(dev) &&
2255− pm_suspend_via_firmware();
2301+ return pm_runtime_suspended(dev);
2302+
2303+ /* if we will not support s3 or s2i for the device
2304+ * then skip suspend
2305+ */
2306+ if (!amdgpu_acpi_is_s0ix_active(adev) &&
2307+ !amdgpu_acpi_is_s3_active(adev))
2308+ return 1;
22562309
22572310 return 0;
22582311 }
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c+5−38
@@ -446,24 +446,18 @@ int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, · 445 unmodified lines
446446 * for the requested ring.
447447 *
448448 * @ring: ring to init the fence driver on
449− * @num_hw_submission: number of entries on the hardware queue
450− * @sched_score: optional score atomic shared with other schedulers
451449 *
452450 * Init the fence driver for the requested ring (all asics).
453451 * Helper function for amdgpu_fence_driver_init().
454452 */
455−int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
456− unsigned num_hw_submission,
457− atomic_t *sched_score)
453+int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring)
458454 {
459455 struct amdgpu_device *adev = ring->adev;
460− long timeout;
461− int r;
462456
463457 if (!adev)
464458 return -EINVAL;
465459
466− if (!is_power_of_2(num_hw_submission))
460+ if (!is_power_of_2(ring->num_hw_submission))
467461 return -EINVAL;
468462
469463 ring->fence_drv.cpu_addr = NULL;
@@ -474,41 +468,14 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, · 4 unmodified lines
474468
475469 timer_setup(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback, 0);
476470
477− ring->fence_drv.num_fences_mask = num_hw_submission * 2 - 1;
471+ ring->fence_drv.num_fences_mask = ring->num_hw_submission * 2 - 1;
478472 spin_lock_init(&ring->fence_drv.lock);
479− ring->fence_drv.fences = kcalloc(num_hw_submission * 2, sizeof(void *),
473+ ring->fence_drv.fences = kcalloc(ring->num_hw_submission * 2, sizeof(void *),
480474 GFP_KERNEL);
475+
481476 if (!ring->fence_drv.fences)
482477 return -ENOMEM;
483478
484− /* No need to setup the GPU scheduler for rings that don't need it */
485− if (ring->no_scheduler)
486− return 0;
487−
488− switch (ring->funcs->type) {
489− case AMDGPU_RING_TYPE_GFX:
490− timeout = adev->gfx_timeout;
491− break;
492− case AMDGPU_RING_TYPE_COMPUTE:
493− timeout = adev->compute_timeout;
494− break;
495− case AMDGPU_RING_TYPE_SDMA:
496− timeout = adev->sdma_timeout;
497− break;
498− default:
499− timeout = adev->video_timeout;
500− break;
501− }
502−
503− r = drm_sched_init(&ring->sched, &amdgpu_sched_ops,
504− num_hw_submission, amdgpu_job_hang_limit,
505− timeout, NULL, sched_score, ring->name);
506− if (r) {
507− DRM_ERROR("Failed to create scheduler on ring %s.\n",
508− ring->name);
509− return r;
510− }
511−
512479 return 0;
513480 }
514481
drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c+31−22
@@ -30,7 +30,6 @@ · 29 unmodified lines
3030 #include "amdgpu_eeprom.h"
3131
3232 #define FRU_EEPROM_MADDR 0x60000
33−#define I2C_PRODUCT_INFO_OFFSET 0xC0
3433
3534 static bool is_fru_eeprom_supported(struct amdgpu_device *adev)
3635 {
@@ -40,7 +39,13 @@ static bool is_fru_eeprom_supported(struct amdgpu_device *adev) · 3 unmodified lines
4039 */
4140 struct atom_context *atom_ctx = adev->mode_info.atom_context;
4241
43− /* VBIOS is of the format ###-DXXXYY-##. For SKU identification,
42+ /* The i2c access is blocked on VF
43+ * TODO: Need other way to get the info
44+ */
45+ if (amdgpu_sriov_vf(adev))
46+ return false;
47+
48+ /* VBIOS is of the format ###-DXXXYYYY-##. For SKU identification,
4449 * we can use just the "DXXX" portion. If there were more models, we
4550 * could convert the 3 characters to a hex integer and use a switch
4651 * for ease/speed/readability. For now, 2 string comparisons are
@@ -59,17 +64,24 @@ static bool is_fru_eeprom_supported(struct amdgpu_device *adev) · 12 unmodified lines
5964 case CHIP_ALDEBARAN:
6065 /* All Aldebaran SKUs have the FRU */
6166 return true;
67+ case CHIP_SIENNA_CICHLID:
68+ if (strnstr(atom_ctx->vbios_version, "D603",
69+ sizeof(atom_ctx->vbios_version)))
70+ return true;
71+ else
72+ return false;
6273 default:
6374 return false;
6475 }
6576 }
6677
6778 static int amdgpu_fru_read_eeprom(struct amdgpu_device *adev, uint32_t addrptr,
68− unsigned char *buff)
79+ unsigned char *buf, size_t buf_size)
6980 {
70− int ret, size;
81+ int ret;
82+ u8 size;
7183
72− ret = amdgpu_eeprom_read(&adev->pm.smu_i2c, addrptr, buff, 1);
84+ ret = amdgpu_eeprom_read(adev->pm.fru_eeprom_i2c_bus, addrptr, buf, 1);
7385 if (ret < 1) {
7486 DRM_WARN("FRU: Failed to get size field");
7587 return ret;
@@ -78,9 +90,11 @@ static int amdgpu_fru_read_eeprom(struct amdgpu_device *adev, uint32_t addrptr, · 2 unmodified lines
7890 /* The size returned by the i2c requires subtraction of 0xC0 since the
7991 * size apparently always reports as 0xC0+actual size.
8092 */
81− size = buff[0] - I2C_PRODUCT_INFO_OFFSET;
93+ size = buf[0] & 0x3F;
94+ size = min_t(size_t, size, buf_size);
8295
83− ret = amdgpu_eeprom_read(&adev->pm.smu_i2c, addrptr + 1, buff, size);
96+ ret = amdgpu_eeprom_read(adev->pm.fru_eeprom_i2c_bus, addrptr + 1,
97+ buf, size);
8498 if (ret < 1) {
8599 DRM_WARN("FRU: Failed to get data field");
86100 return ret;
@@ -91,19 +105,15 @@ static int amdgpu_fru_read_eeprom(struct amdgpu_device *adev, uint32_t addrptr, · 4 unmodified lines
91105
92106 int amdgpu_fru_get_product_info(struct amdgpu_device *adev)
93107 {
94− unsigned char buff[AMDGPU_PRODUCT_NAME_LEN+2];
108+ unsigned char buf[AMDGPU_PRODUCT_NAME_LEN];
95109 u32 addrptr;
96110 int size, len;
97− int offset = 2;
98111
99112 if (!is_fru_eeprom_supported(adev))
100113 return 0;
101114
102− if (adev->asic_type == CHIP_ALDEBARAN)
103− offset = 0;
104−
105115 /* If algo exists, it means that the i2c_adapter's initialized */
106− if (!adev->pm.smu_i2c.algo) {
116+ if (!adev->pm.fru_eeprom_i2c_bus || !adev->pm.fru_eeprom_i2c_bus->algo) {
107117 DRM_WARN("Cannot access FRU, EEPROM accessor not initialized");
108118 return -ENODEV;
109119 }
@@ -121,7 +131,7 @@ int amdgpu_fru_get_product_info(struct amdgpu_device *adev) · 11 unmodified lines
121131 * and the language field, so just start from 0xb, manufacturer size
122132 */
123133 addrptr = FRU_EEPROM_MADDR + 0xb;
124− size = amdgpu_fru_read_eeprom(adev, addrptr, buff);
134+ size = amdgpu_fru_read_eeprom(adev, addrptr, buf, sizeof(buf));
125135 if (size < 1) {
126136 DRM_ERROR("Failed to read FRU Manufacturer, ret:%d", size);
127137 return -EINVAL;
@@ -131,7 +141,7 @@ int amdgpu_fru_get_product_info(struct amdgpu_device *adev) · 3 unmodified lines
131141 * size field being 1 byte. This pattern continues below.
132142 */
133143 addrptr += size + 1;
134− size = amdgpu_fru_read_eeprom(adev, addrptr, buff);
144+ size = amdgpu_fru_read_eeprom(adev, addrptr, buf, sizeof(buf));
135145 if (size < 1) {
136146 DRM_ERROR("Failed to read FRU product name, ret:%d", size);
137147 return -EINVAL;
@@ -143,12 +153,11 @@ int amdgpu_fru_get_product_info(struct amdgpu_device *adev) · 5 unmodified lines
143153 AMDGPU_PRODUCT_NAME_LEN);
144154 len = AMDGPU_PRODUCT_NAME_LEN - 1;
145155 }
146− /* Start at 2 due to buff using fields 0 and 1 for the address */
147− memcpy(adev->product_name, &buff[offset], len);
156+ memcpy(adev->product_name, buf, len);
148157 adev->product_name[len] = '\0';
149158
150159 addrptr += size + 1;
151− size = amdgpu_fru_read_eeprom(adev, addrptr, buff);
160+ size = amdgpu_fru_read_eeprom(adev, addrptr, buf, sizeof(buf));
152161 if (size < 1) {
153162 DRM_ERROR("Failed to read FRU product number, ret:%d", size);
154163 return -EINVAL;
@@ -162,11 +171,11 @@ int amdgpu_fru_get_product_info(struct amdgpu_device *adev) · 7 unmodified lines
162171 DRM_WARN("FRU Product Number is larger than 16 characters. This is likely a mistake");
163172 len = sizeof(adev->product_number) - 1;
164173 }
165− memcpy(adev->product_number, &buff[offset], len);
174+ memcpy(adev->product_number, buf, len);
166175 adev->product_number[len] = '\0';
167176
168177 addrptr += size + 1;
169− size = amdgpu_fru_read_eeprom(adev, addrptr, buff);
178+ size = amdgpu_fru_read_eeprom(adev, addrptr, buf, sizeof(buf));
170179
171180 if (size < 1) {
172181 DRM_ERROR("Failed to read FRU product version, ret:%d", size);
@@ -174,7 +183,7 @@ int amdgpu_fru_get_product_info(struct amdgpu_device *adev) · 1 unmodified line
174183 }
175184
176185 addrptr += size + 1;
177− size = amdgpu_fru_read_eeprom(adev, addrptr, buff);
186+ size = amdgpu_fru_read_eeprom(adev, addrptr, buf, sizeof(buf));
178187
179188 if (size < 1) {
180189 DRM_ERROR("Failed to read FRU serial number, ret:%d", size);
@@ -189,7 +198,7 @@ int amdgpu_fru_get_product_info(struct amdgpu_device *adev) · 8 unmodified lines
189198 DRM_WARN("FRU Serial Number is larger than 16 characters. This is likely a mistake");
190199 len = sizeof(adev->serial) - 1;
191200 }
192− memcpy(adev->serial, &buff[offset], len);
201+ memcpy(adev->serial, buf, len);
193202 adev->serial[len] = '\0';
194203
195204 return 0;
drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c+12−24
@@ -150,7 +150,7 @@ void amdgpu_gart_table_vram_free(struct amdgpu_device *adev) · 149 unmodified lines
150150 * replaces them with the dummy page (all asics).
151151 * Returns 0 for success, -EINVAL for failure.
152152 */
153−int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
153+void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
154154 int pages)
155155 {
156156 unsigned t;
@@ -161,13 +161,11 @@ int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, · 4 unmodified lines
161161 uint64_t flags = 0;
162162 int idx;
163163
164− if (!adev->gart.ready) {
165− WARN(1, "trying to unbind memory from uninitialized GART !\n");
166− return -EINVAL;
167− }
164+ if (!adev->gart.ptr)
165+ return;
168166
169167 if (!drm_dev_enter(adev_to_drm(adev), &idx))
170− return 0;
168+ return;
171169
172170 t = offset / AMDGPU_GPU_PAGE_SIZE;
173171 p = t / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
@@ -188,7 +186,6 @@ int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, · 14 unmodified lines
188186 amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
189187
190188 drm_dev_exit(idx);
191− return 0;
192189 }
193190
194191 /**
@@ -204,7 +201,7 @@ int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, · 9 unmodified lines
204201 * Map the dma_addresses into GART entries (all asics).
205202 * Returns 0 for success, -EINVAL for failure.
206203 */
207−int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
204+void amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
208205 int pages, dma_addr_t *dma_addr, uint64_t flags,
209206 void *dst)
210207 {
@@ -212,13 +209,8 @@ int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset, · 1 unmodified line
212209 unsigned i, j, t;
213210 int idx;
214211
215− if (!adev->gart.ready) {
216− WARN(1, "trying to bind memory to uninitialized GART !\n");
217− return -EINVAL;
218− }
219−
220212 if (!drm_dev_enter(adev_to_drm(adev), &idx))
221− return 0;
213+ return;
222214
223215 t = offset / AMDGPU_GPU_PAGE_SIZE;
224216
@@ -230,7 +222,6 @@ int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset, · 5 unmodified lines
230222 }
231223 }
232224 drm_dev_exit(idx);
233− return 0;
234225 }
235226
236227 /**
@@ -246,20 +237,14 @@ int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset, · 9 unmodified lines
246237 * (all asics).
247238 * Returns 0 for success, -EINVAL for failure.
248239 */
249−int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
240+void amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
250241 int pages, dma_addr_t *dma_addr,
251242 uint64_t flags)
252243 {
253− if (!adev->gart.ready) {
254− WARN(1, "trying to bind memory to uninitialized GART !\n");
255− return -EINVAL;
256− }
257−
258244 if (!adev->gart.ptr)
259− return 0;
245+ return;
260246
261− return amdgpu_gart_map(adev, offset, pages, dma_addr, flags,
262− adev->gart.ptr);
247+ amdgpu_gart_map(adev, offset, pages, dma_addr, flags, adev->gart.ptr);
263248 }
264249
265250 /**
@@ -274,6 +259,9 @@ void amdgpu_gart_invalidate_tlb(struct amdgpu_device *adev) · 8 unmodified lines
274259 {
275260 int i;
276261
262+ if (!adev->gart.ptr)
263+ return;
264+
277265 mb();
278266 amdgpu_device_flush_hdp(adev, NULL);
279267 for (i = 0; i < adev->num_vmhubs; i++)
drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h+7−8
@@ -46,7 +46,6 @@ struct amdgpu_gart { · 45 unmodified lines
4646 unsigned num_gpu_pages;
4747 unsigned num_cpu_pages;
4848 unsigned table_size;
49− bool ready;
5049
5150 /* Asic default pte flags */
5251 uint64_t gart_pte_flags;
@@ -58,12 +57,12 @@ int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev); · 5 unmodified lines
5857 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
5958 int amdgpu_gart_init(struct amdgpu_device *adev);
6059 void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev);
61−int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
62− int pages);
63−int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
64− int pages, dma_addr_t *dma_addr, uint64_t flags,
65− void *dst);
66−int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
67− int pages, dma_addr_t *dma_addr, uint64_t flags);
60+void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
61+ int pages);
62+void amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
63+ int pages, dma_addr_t *dma_addr, uint64_t flags,
64+ void *dst);
65+void amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
66+ int pages, dma_addr_t *dma_addr, uint64_t flags);
6867 void amdgpu_gart_invalidate_tlb(struct amdgpu_device *adev);
6968 #endif
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c+1−1
@@ -222,7 +222,7 @@ static void amdgpu_gem_object_close(struct drm_gem_object *obj, · 221 unmodified lines
222222 if (!bo_va || --bo_va->ref_count)
223223 goto out_unlock;
224224
225− amdgpu_vm_bo_rmv(adev, bo_va);
225+ amdgpu_vm_bo_del(adev, bo_va);
226226 if (!amdgpu_vm_ready(vm))
227227 goto out_unlock;
228228
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c+11−59
@@ -615,72 +615,40 @@ int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value) · 614 unmodified lines
615615
616616 mutex_lock(&adev->gfx.gfx_off_mutex);
617617
618− r = smu_get_status_gfxoff(adev, value);
618+ r = amdgpu_dpm_get_status_gfxoff(adev, value);
619619
620620 mutex_unlock(&adev->gfx.gfx_off_mutex);
621621
622622 return r;
623623 }
624624
625−int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev)
625+int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
626626 {
627627 int r;
628− struct ras_fs_if fs_info = {
629− .sysfs_name = "gfx_err_count",
630− };
631− struct ras_ih_if ih_info = {
632− .cb = amdgpu_gfx_process_ras_data_cb,
633− };
634−
635− if (!adev->gfx.ras_if) {
636− adev->gfx.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
637− if (!adev->gfx.ras_if)
638− return -ENOMEM;
639− adev->gfx.ras_if->block = AMDGPU_RAS_BLOCK__GFX;
640− adev->gfx.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
641− adev->gfx.ras_if->sub_block_index = 0;
642− }
643− fs_info.head = ih_info.head = *adev->gfx.ras_if;
644− r = amdgpu_ras_late_init(adev, adev->gfx.ras_if,
645− &fs_info, &ih_info);
628+ r = amdgpu_ras_block_late_init(adev, ras_block);
646629 if (r)
647− goto free;
630+ return r;
648631
649− if (amdgpu_ras_is_supported(adev, adev->gfx.ras_if->block)) {
632+ if (amdgpu_ras_is_supported(adev, ras_block->block)) {
650633 if (!amdgpu_persistent_edc_harvesting_supported(adev))
651634 amdgpu_ras_reset_error_status(adev, AMDGPU_RAS_BLOCK__GFX);
652635
653636 r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
654637 if (r)
655638 goto late_fini;
656− } else {
657− /* free gfx ras_if if ras is not supported */
658− r = 0;
659− goto free;
660639 }
661640
662641 return 0;
663642 late_fini:
664− amdgpu_ras_late_fini(adev, adev->gfx.ras_if, &ih_info);
665−free:
666− kfree(adev->gfx.ras_if);
667− adev->gfx.ras_if = NULL;
643+ amdgpu_ras_block_late_fini(adev, ras_block);
668644 return r;
669645 }
670646
671647 void amdgpu_gfx_ras_fini(struct amdgpu_device *adev)
672648 {
673649 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX) &&
674− adev->gfx.ras_if) {
675− struct ras_common_if *ras_if = adev->gfx.ras_if;
676− struct ras_ih_if ih_info = {
677− .head = *ras_if,
678− .cb = amdgpu_gfx_process_ras_data_cb,
679− };
680−
681− amdgpu_ras_late_fini(adev, ras_if, &ih_info);
682− kfree(ras_if);
683− }
650+ adev->gfx.ras_if)
651+ amdgpu_ras_block_late_fini(adev, adev->gfx.ras_if);
684652 }
685653
686654 int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
@@ -695,9 +663,9 @@ int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev, · 8 unmodified lines
695663 */
696664 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) {
697665 kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
698− if (adev->gfx.ras_funcs &&
699− adev->gfx.ras_funcs->query_ras_error_count)
700− adev->gfx.ras_funcs->query_ras_error_count(adev, err_data);
666+ if (adev->gfx.ras && adev->gfx.ras->ras_block.hw_ops &&
667+ adev->gfx.ras->ras_block.hw_ops->query_ras_error_count)
668+ adev->gfx.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data);
701669 amdgpu_ras_reset_gpu(adev);
702670 }
703671 return AMDGPU_RAS_SUCCESS;
@@ -852,19 +820,3 @@ int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev) · 148 unmodified lines
852820 }
853821 return amdgpu_num_kcq;
854822 }
855−
856−/* amdgpu_gfx_state_change_set - Handle gfx power state change set
857− * @adev: amdgpu_device pointer
858− * @state: gfx power state(1 -sGpuChangeState_D0Entry and 2 -sGpuChangeState_D3Entry)
859− *
860− */
861−
862−void amdgpu_gfx_state_change_set(struct amdgpu_device *adev, enum gfx_change_state state)
863−{
864− mutex_lock(&adev->pm.mutex);
865− if (adev->powerplay.pp_funcs &&
866− adev->powerplay.pp_funcs->gfx_state_change_set)
867− ((adev)->powerplay.pp_funcs->gfx_state_change_set(
868− (adev)->powerplay.pp_handle, state));
869− mutex_unlock(&adev->pm.mutex);
870−}
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h+5−19
@@ -31,6 +31,7 @@ · 30 unmodified lines
3131 #include "amdgpu_ring.h"
3232 #include "amdgpu_rlc.h"
3333 #include "soc15.h"
34+#include "amdgpu_ras.h"
3435
3536 /* GFX current status */
3637 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L
@@ -47,12 +48,6 @@ enum amdgpu_gfx_pipe_priority { · 10 unmodified lines
4748 AMDGPU_GFX_PIPE_PRIO_HIGH = AMDGPU_RING_PRIO_2
4849 };
4950
50−/* Argument for PPSMC_MSG_GpuChangeState */
51−enum gfx_change_state {
52− sGpuChangeState_D0Entry = 1,
53− sGpuChangeState_D3Entry,
54−};
55−
5651 #define AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM 0
5752 #define AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM 15
5853
@@ -204,16 +199,8 @@ struct amdgpu_cu_info { · 145 unmodified lines
204199 uint32_t bitmap[4][4];
205200 };
206201
207−struct amdgpu_gfx_ras_funcs {
208− int (*ras_late_init)(struct amdgpu_device *adev);
209− void (*ras_fini)(struct amdgpu_device *adev);
210− int (*ras_error_inject)(struct amdgpu_device *adev,
211− void *inject_if);
212− int (*query_ras_error_count)(struct amdgpu_device *adev,
213− void *ras_error_status);
214− void (*reset_ras_error_count)(struct amdgpu_device *adev);
215− void (*query_ras_error_status)(struct amdgpu_device *adev);
216− void (*reset_ras_error_status)(struct amdgpu_device *adev);
202+struct amdgpu_gfx_ras {
203+ struct amdgpu_ras_block_object ras_block;
217204 void (*enable_watchdog_timer)(struct amdgpu_device *adev);
218205 };
219206
@@ -337,7 +324,7 @@ struct amdgpu_gfx { · 117 unmodified lines
337324
338325 /*ras */
339326 struct ras_common_if *ras_if;
340− const struct amdgpu_gfx_ras_funcs *ras_funcs;
327+ struct amdgpu_gfx_ras *ras;
341328 };
342329
343330 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
@@ -399,7 +386,7 @@ bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me, · 55 unmodified lines
399386 int pipe, int queue);
400387 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);
401388 int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value);
402−int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev);
389+int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);
403390 void amdgpu_gfx_ras_fini(struct amdgpu_device *adev);
404391 int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
405392 void *err_data,
@@ -410,5 +397,4 @@ int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev, · 4 unmodified lines
410397 uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
411398 void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
412399 int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev);
413−void amdgpu_gfx_state_change_set(struct amdgpu_device *adev, enum gfx_change_state state);
414400 #endif
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c+63−64
@@ -436,82 +436,35 @@ void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev, uint64_t addr, · 435 unmodified lines
436436 } while (fault->timestamp < tmp);
437437 }
438438
439−int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev)
439+int amdgpu_gmc_ras_early_init(struct amdgpu_device *adev)
440440 {
441− int r;
442−
443− if (adev->umc.ras_funcs &&
444− adev->umc.ras_funcs->ras_late_init) {
445− r = adev->umc.ras_funcs->ras_late_init(adev);
446− if (r)
447− return r;
448− }
449−
450− if (adev->mmhub.ras_funcs &&
451− adev->mmhub.ras_funcs->ras_late_init) {
452− r = adev->mmhub.ras_funcs->ras_late_init(adev);
453− if (r)
454− return r;
455− }
456−
457− if (!adev->gmc.xgmi.connected_to_cpu)
458− adev->gmc.xgmi.ras_funcs = &xgmi_ras_funcs;
459−
460− if (adev->gmc.xgmi.ras_funcs &&
461− adev->gmc.xgmi.ras_funcs->ras_late_init) {
462− r = adev->gmc.xgmi.ras_funcs->ras_late_init(adev);
463− if (r)
464− return r;
465− }
466−
467− if (adev->hdp.ras_funcs &&
468− adev->hdp.ras_funcs->ras_late_init) {
469− r = adev->hdp.ras_funcs->ras_late_init(adev);
470− if (r)
471− return r;
472− }
473−
474− if (adev->mca.mp0.ras_funcs &&
475− adev->mca.mp0.ras_funcs->ras_late_init) {
476− r = adev->mca.mp0.ras_funcs->ras_late_init(adev);
477− if (r)
478− return r;
479− }
480−
481− if (adev->mca.mp1.ras_funcs &&
482− adev->mca.mp1.ras_funcs->ras_late_init) {
483− r = adev->mca.mp1.ras_funcs->ras_late_init(adev);
484− if (r)
485− return r;
441+ if (!adev->gmc.xgmi.connected_to_cpu) {
442+ adev->gmc.xgmi.ras = &xgmi_ras;
443+ amdgpu_ras_register_ras_block(adev, &adev->gmc.xgmi.ras->ras_block);
444+ adev->gmc.xgmi.ras_if = &adev->gmc.xgmi.ras->ras_block.ras_comm;
486445 }
487446
488− if (adev->mca.mpio.ras_funcs &&
489− adev->mca.mpio.ras_funcs->ras_late_init) {
490− r = adev->mca.mpio.ras_funcs->ras_late_init(adev);
491− if (r)
492− return r;
493− }
447+ return 0;
448+}
494449
450+int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev)
451+{
495452 return 0;
496453 }
497454
498455 void amdgpu_gmc_ras_fini(struct amdgpu_device *adev)
499456 {
500− if (adev->umc.ras_funcs &&
501− adev->umc.ras_funcs->ras_fini)
502− adev->umc.ras_funcs->ras_fini(adev);
457+ if (adev->umc.ras && adev->umc.ras->ras_block.ras_fini)
458+ adev->umc.ras->ras_block.ras_fini(adev);
503459
504− if (adev->mmhub.ras_funcs &&
505− adev->mmhub.ras_funcs->ras_fini)
506− adev->mmhub.ras_funcs->ras_fini(adev);
460+ if (adev->mmhub.ras && adev->mmhub.ras->ras_block.ras_fini)
461+ adev->mmhub.ras->ras_block.ras_fini(adev);
507462
508− if (adev->gmc.xgmi.ras_funcs &&
509− adev->gmc.xgmi.ras_funcs->ras_fini)
510− adev->gmc.xgmi.ras_funcs->ras_fini(adev);
463+ if (adev->gmc.xgmi.ras && adev->gmc.xgmi.ras->ras_block.ras_fini)
464+ adev->gmc.xgmi.ras->ras_block.ras_fini(adev);
511465
512− if (adev->hdp.ras_funcs &&
513− adev->hdp.ras_funcs->ras_fini)
514− adev->hdp.ras_funcs->ras_fini(adev);
466+ if (adev->hdp.ras && adev->hdp.ras->ras_block.ras_fini)
467+ adev->hdp.ras->ras_block.ras_fini(adev);
515468 }
516469
517470 /*
@@ -831,3 +784,49 @@ void amdgpu_gmc_get_reserved_allocation(struct amdgpu_device *adev) · 313 unmodified lines
831784 break;
832785 }
833786 }
787+
788+int amdgpu_gmc_vram_checking(struct amdgpu_device *adev)
789+{
790+ struct amdgpu_bo *vram_bo = NULL;
791+ uint64_t vram_gpu = 0;
792+ void *vram_ptr = NULL;
793+
794+ int ret, size = 0x100000;
795+ uint8_t cptr[10];
796+
797+ ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,
798+ AMDGPU_GEM_DOMAIN_VRAM,
799+ &vram_bo,
800+ &vram_gpu,
801+ &vram_ptr);
802+ if (ret)
803+ return ret;
804+
805+ memset(vram_ptr, 0x86, size);
806+ memset(cptr, 0x86, 10);
807+
808+ /**
809+ * Check the start, the mid, and the end of the memory if the content of
810+ * each byte is the pattern "0x86". If yes, we suppose the vram bo is
811+ * workable.
812+ *
813+ * Note: If check the each byte of whole 1M bo, it will cost too many
814+ * seconds, so here, we just pick up three parts for emulation.
815+ */
816+ ret = memcmp(vram_ptr, cptr, 10);
817+ if (ret)
818+ return ret;
819+
820+ ret = memcmp(vram_ptr + (size / 2), cptr, 10);
821+ if (ret)
822+ return ret;
823+
824+ ret = memcmp(vram_ptr + size - 10, cptr, 10);
825+ if (ret)
826+ return ret;
827+
828+ amdgpu_bo_free_kernel(&vram_bo, &vram_gpu,
829+ &vram_ptr);
830+
831+ return 0;
832+}
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h+6−7
@@ -29,6 +29,7 @@ · 28 unmodified lines
2929 #include <linux/types.h>
3030
3131 #include "amdgpu_irq.h"
32+#include "amdgpu_ras.h"
3233
3334 /* VA hole for 48bit addresses on Vega10 */
3435 #define AMDGPU_GMC_HOLE_START 0x0000800000000000ULL
@@ -135,12 +136,8 @@ struct amdgpu_gmc_funcs { · 100 unmodified lines
135136 unsigned int (*get_vbios_fb_size)(struct amdgpu_device *adev);
136137 };
137138
138−struct amdgpu_xgmi_ras_funcs {
139− int (*ras_late_init)(struct amdgpu_device *adev);
140− void (*ras_fini)(struct amdgpu_device *adev);
141− int (*query_ras_error_count)(struct amdgpu_device *adev,
142− void *ras_error_status);
143− void (*reset_ras_error_count)(struct amdgpu_device *adev);
139+struct amdgpu_xgmi_ras {
140+ struct amdgpu_ras_block_object ras_block;
144141 };
145142
146143 struct amdgpu_xgmi {
@@ -159,7 +156,7 @@ struct amdgpu_xgmi { · 12 unmodified lines
159156 struct ras_common_if *ras_if;
160157 bool connected_to_cpu;
161158 bool pending_reset;
162− const struct amdgpu_xgmi_ras_funcs *ras_funcs;
159+ struct amdgpu_xgmi_ras *ras;
163160 };
164161
165162 struct amdgpu_gmc {
@@ -321,6 +318,7 @@ bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, · 155 unmodified lines
321318 uint16_t pasid, uint64_t timestamp);
322319 void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev, uint64_t addr,
323320 uint16_t pasid);
321+int amdgpu_gmc_ras_early_init(struct amdgpu_device *adev);
324322 int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev);
325323 void amdgpu_gmc_ras_fini(struct amdgpu_device *adev);
326324 int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev);
@@ -339,4 +337,5 @@ void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev); · 12 unmodified lines
339337 uint64_t amdgpu_gmc_vram_mc2pa(struct amdgpu_device *adev, uint64_t mc_addr);
340338 uint64_t amdgpu_gmc_vram_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo);
341339 uint64_t amdgpu_gmc_vram_cpu_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo);
340+int amdgpu_gmc_vram_checking(struct amdgpu_device *adev);
342341 #endif
drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c+13−45
@@ -60,7 +60,7 @@ static ssize_t amdgpu_mem_info_gtt_total_show(struct device *dev, · 59 unmodified lines
6060 struct ttm_resource_manager *man;
6161
6262 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT);
63− return sysfs_emit(buf, "%llu\n", man->size * PAGE_SIZE);
63+ return sysfs_emit(buf, "%llu\n", man->size);
6464 }
6565
6666 /**
@@ -77,8 +77,9 @@ static ssize_t amdgpu_mem_info_gtt_used_show(struct device *dev, · 10 unmodified lines
7777 {
7878 struct drm_device *ddev = dev_get_drvdata(dev);
7979 struct amdgpu_device *adev = drm_to_adev(ddev);
80+ struct ttm_resource_manager *man = &adev->mman.gtt_mgr.manager;
8081
81− return sysfs_emit(buf, "%llu\n", amdgpu_gtt_mgr_usage(&adev->mman.gtt_mgr));
82+ return sysfs_emit(buf, "%llu\n", ttm_resource_manager_usage(man));
8283 }
8384
8485 static DEVICE_ATTR(mem_info_gtt_total, S_IRUGO,
@@ -130,20 +131,17 @@ static int amdgpu_gtt_mgr_new(struct ttm_resource_manager *man, · 45 unmodified lines
130131 struct amdgpu_gtt_node *node;
131132 int r;
132133
133− if (!(place->flags & TTM_PL_FLAG_TEMPORARY) &&
134− atomic64_add_return(num_pages, &mgr->used) > man->size) {
135− atomic64_sub(num_pages, &mgr->used);
136− return -ENOSPC;
137− }
138−
139134 node = kzalloc(struct_size(node, base.mm_nodes, 1), GFP_KERNEL);
140− if (!node) {
141− r = -ENOMEM;
142− goto err_out;
143− }
135+ if (!node)
136+ return -ENOMEM;
144137
145138 node->tbo = tbo;
146139 ttm_resource_init(tbo, place, &node->base.base);
140+ if (!(place->flags & TTM_PL_FLAG_TEMPORARY) &&
141+ ttm_resource_manager_usage(man) > man->size) {
142+ r = -ENOSPC;
143+ goto err_free;
144+ }
147145
148146 if (place->lpfn) {
149147 spin_lock(&mgr->lock);
@@ -169,11 +167,6 @@ static int amdgpu_gtt_mgr_new(struct ttm_resource_manager *man, · 19 unmodified lines
169167 err_free:
170168 ttm_resource_fini(man, &node->base.base);
171169 kfree(node);
172−
173−err_out:
174− if (!(place->flags & TTM_PL_FLAG_TEMPORARY))
175− atomic64_sub(num_pages, &mgr->used);
176−
177170 return r;
178171 }
179172
@@ -196,25 +189,10 @@ static void amdgpu_gtt_mgr_del(struct ttm_resource_manager *man, · 16 unmodified lines
196189 drm_mm_remove_node(&node->base.mm_nodes[0]);
197190 spin_unlock(&mgr->lock);
198191
199− if (!(res->placement & TTM_PL_FLAG_TEMPORARY))
200− atomic64_sub(res->num_pages, &mgr->used);
201−
202192 ttm_resource_fini(man, res);
203193 kfree(node);
204194 }
205195
206−/**
207− * amdgpu_gtt_mgr_usage - return usage of GTT domain
208− *
209− * @mgr: amdgpu_gtt_mgr pointer
210− *
211− * Return how many bytes are used in the GTT domain
212− */
213−uint64_t amdgpu_gtt_mgr_usage(struct amdgpu_gtt_mgr *mgr)
214−{
215− return atomic64_read(&mgr->used) * PAGE_SIZE;
216−}
217−
218196 /**
219197 * amdgpu_gtt_mgr_recover - re-init gart
220198 *
@@ -222,26 +200,21 @@ uint64_t amdgpu_gtt_mgr_usage(struct amdgpu_gtt_mgr *mgr) · 1 unmodified line
222200 *
223201 * Re-init the gart for each known BO in the GTT.
224202 */
225−int amdgpu_gtt_mgr_recover(struct amdgpu_gtt_mgr *mgr)
203+void amdgpu_gtt_mgr_recover(struct amdgpu_gtt_mgr *mgr)
226204 {
227205 struct amdgpu_gtt_node *node;
228206 struct drm_mm_node *mm_node;
229207 struct amdgpu_device *adev;
230− int r = 0;
231208
232209 adev = container_of(mgr, typeof(*adev), mman.gtt_mgr);
233210 spin_lock(&mgr->lock);
234211 drm_mm_for_each_node(mm_node, &mgr->mm) {
235212 node = container_of(mm_node, typeof(*node), base.mm_nodes[0]);
236− r = amdgpu_ttm_recover_gart(node->tbo);
237− if (r)
238− break;
213+ amdgpu_ttm_recover_gart(node->tbo);
239214 }
240215 spin_unlock(&mgr->lock);
241216
242217 amdgpu_gart_invalidate_tlb(adev);
243−
244− return r;
245218 }
246219
247220 /**
@@ -260,9 +233,6 @@ static void amdgpu_gtt_mgr_debug(struct ttm_resource_manager *man, · 12 unmodified lines
260233 spin_lock(&mgr->lock);
261234 drm_mm_print(&mgr->mm, printer);
262235 spin_unlock(&mgr->lock);
263−
264− drm_printf(printer, "man size:%llu pages, gtt used:%llu pages\n",
265− man->size, atomic64_read(&mgr->used));
266236 }
267237
268238 static const struct ttm_resource_manager_func amdgpu_gtt_mgr_func = {
@@ -288,14 +258,12 @@ int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size) · 19 unmodified lines
288258 man->use_tt = true;
289259 man->func = &amdgpu_gtt_mgr_func;
290260
291− ttm_resource_manager_init(man, &adev->mman.bdev,
292− gtt_size >> PAGE_SHIFT);
261+ ttm_resource_manager_init(man, &adev->mman.bdev, gtt_size);
293262
294263 start = AMDGPU_GTT_MAX_TRANSFER_SIZE * AMDGPU_GTT_NUM_TRANSFER_WINDOWS;
295264 size = (adev->gmc.gart_size >> PAGE_SHIFT) - start;
296265 drm_mm_init(&mgr->mm, start, size);
297266 spin_lock_init(&mgr->lock);
298− atomic64_set(&mgr->used, 0);
299267
300268 ttm_set_driver_manager(&adev->mman.bdev, TTM_PL_TT, &mgr->manager);
301269 ttm_resource_manager_set_used(man, true);
drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c+2−38
@@ -24,45 +24,9 @@ · 23 unmodified lines
2424 #include "amdgpu.h"
2525 #include "amdgpu_ras.h"
2626
27−int amdgpu_hdp_ras_late_init(struct amdgpu_device *adev)
28−{
29− int r;
30− struct ras_ih_if ih_info = {
31− .cb = NULL,
32− };
33− struct ras_fs_if fs_info = {
34− .sysfs_name = "hdp_err_count",
35− };
36−
37− if (!adev->hdp.ras_if) {
38− adev->hdp.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
39− if (!adev->hdp.ras_if)
40− return -ENOMEM;
41− adev->hdp.ras_if->block = AMDGPU_RAS_BLOCK__HDP;
42− adev->hdp.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
43− adev->hdp.ras_if->sub_block_index = 0;
44− }
45− ih_info.head = fs_info.head = *adev->hdp.ras_if;
46− r = amdgpu_ras_late_init(adev, adev->hdp.ras_if,
47− &fs_info, &ih_info);
48− if (r || !amdgpu_ras_is_supported(adev, adev->hdp.ras_if->block)) {
49− kfree(adev->hdp.ras_if);
50− adev->hdp.ras_if = NULL;
51− }
52−
53− return r;
54−}
55−
5627 void amdgpu_hdp_ras_fini(struct amdgpu_device *adev)
5728 {
5829 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP) &&
59− adev->hdp.ras_if) {
60− struct ras_common_if *ras_if = adev->hdp.ras_if;
61− struct ras_ih_if ih_info = {
62− .cb = NULL,
63− };
64−
65− amdgpu_ras_late_fini(adev, ras_if, &ih_info);
66− kfree(ras_if);
67− }
30+ adev->hdp.ras_if)
31+ amdgpu_ras_block_late_fini(adev, adev->hdp.ras_if);
6832 }
drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h+5−8
@@ -22,13 +22,10 @@ · 21 unmodified lines
2222 */
2323 #ifndef __AMDGPU_HDP_H__
2424 #define __AMDGPU_HDP_H__
25+#include "amdgpu_ras.h"
2526
26−struct amdgpu_hdp_ras_funcs {
27− int (*ras_late_init)(struct amdgpu_device *adev);
28− void (*ras_fini)(struct amdgpu_device *adev);
29− void (*query_ras_error_count)(struct amdgpu_device *adev,
30− void *ras_error_status);
31− void (*reset_ras_error_count)(struct amdgpu_device *adev);
27+struct amdgpu_hdp_ras {
28+ struct amdgpu_ras_block_object ras_block;
3229 };
3330
3431 struct amdgpu_hdp_funcs {
@@ -43,9 +40,9 @@ struct amdgpu_hdp_funcs { · 8 unmodified lines
4340 struct amdgpu_hdp {
4441 struct ras_common_if *ras_if;
4542 const struct amdgpu_hdp_funcs *funcs;
46− const struct amdgpu_hdp_ras_funcs *ras_funcs;
43+ struct amdgpu_hdp_ras *ras;
4744 };
4845
49−int amdgpu_hdp_ras_late_init(struct amdgpu_device *adev);
46+int amdgpu_hdp_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);
5047 void amdgpu_hdp_ras_fini(struct amdgpu_device *adev);
5148 #endif /* __AMDGPU_HDP_H__ */
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c+6−6
@@ -199,13 +199,13 @@ static irqreturn_t amdgpu_irq_handler(int irq, void *arg) · 198 unmodified lines
199199 * ack the interrupt if it is there
200200 */
201201 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__PCIE_BIF)) {
202− if (adev->nbio.ras_funcs &&
203− adev->nbio.ras_funcs->handle_ras_controller_intr_no_bifring)
204− adev->nbio.ras_funcs->handle_ras_controller_intr_no_bifring(adev);
202+ if (adev->nbio.ras &&
203+ adev->nbio.ras->handle_ras_controller_intr_no_bifring)
204+ adev->nbio.ras->handle_ras_controller_intr_no_bifring(adev);
205205
206− if (adev->nbio.ras_funcs &&
207− adev->nbio.ras_funcs->handle_ras_err_event_athub_intr_no_bifring)
208− adev->nbio.ras_funcs->handle_ras_err_event_athub_intr_no_bifring(adev);
206+ if (adev->nbio.ras &&
207+ adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring)
208+ adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring(adev);
209209 }
210210
211211 return ret;
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c+4−1
@@ -37,6 +37,7 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job) · 36 unmodified lines
3737 struct amdgpu_task_info ti;
3838 struct amdgpu_device *adev = ring->adev;
3939 int idx;
40+ int r;
4041
4142 if (!drm_dev_enter(adev_to_drm(adev), &idx)) {
4243 DRM_INFO("%s - device unplugged skipping recovery on scheduler:%s",
@@ -63,7 +64,9 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job) · 20 unmodified lines
6364 ti.process_name, ti.tgid, ti.task_name, ti.pid);
6465
6566 if (amdgpu_device_should_recover_gpu(ring->adev)) {
66− amdgpu_device_gpu_recover(ring->adev, job);
67+ r = amdgpu_device_gpu_recover_imp(ring->adev, job);
68+ if (r)
69+ DRM_ERROR("GPU Recovery Failed: %d\n", r);
6770 } else {
6871 drm_sched_suspend_timeout(&ring->sched);
6972 if (amdgpu_sriov_vf(adev))
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c+33−93
@@ -87,11 +87,6 @@ void amdgpu_driver_unload_kms(struct drm_device *dev) · 86 unmodified lines
8787 if (adev->rmmio == NULL)
8888 return;
8989
90− if (adev->runpm) {
91− pm_runtime_get_sync(dev->dev);
92− pm_runtime_forbid(dev->dev);
93− }
94−
9590 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_UNLOAD))
9691 DRM_WARN("smart shift update failed\n");
9792
@@ -124,22 +119,6 @@ void amdgpu_register_gpu_instance(struct amdgpu_device *adev) · 26 unmodified lines
124119 mutex_unlock(&mgpu_info.mutex);
125120 }
126121
127−static void amdgpu_get_audio_func(struct amdgpu_device *adev)
128−{
129− struct pci_dev *p = NULL;
130−
131− p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
132− adev->pdev->bus->number, 1);
133− if (p) {
134− pm_runtime_get_sync(&p->dev);
135−
136− pm_runtime_mark_last_busy(&p->dev);
137− pm_runtime_put_autosuspend(&p->dev);
138−
139− pci_dev_put(p);
140− }
141−}
142−
143122 /**
144123 * amdgpu_driver_load_kms - Main load function for KMS.
145124 *
@@ -152,21 +131,10 @@ static void amdgpu_get_audio_func(struct amdgpu_device *adev) · 6 unmodified lines
152131 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags)
153132 {
154133 struct drm_device *dev;
155− struct pci_dev *parent;
156134 int r, acpi_status;
157135
158136 dev = adev_to_drm(adev);
159137
160− if (amdgpu_has_atpx() &&
161− (amdgpu_is_atpx_hybrid() ||
162− amdgpu_has_atpx_dgpu_power_cntl()) &&
163− ((flags & AMD_IS_APU) == 0) &&
164− !pci_is_thunderbolt_attached(to_pci_dev(dev->dev)))
165− flags |= AMD_IS_PX;
166−
167− parent = pci_upstream_bridge(adev->pdev);
168− adev->has_pr3 = parent ? pci_pr3_present(parent) : false;
169−
170138 /* amdgpu_device_init should report only fatal error
171139 * like memory allocation failure or iomapping failure,
172140 * or memory manager initialization failure, it must
@@ -224,58 +192,12 @@ int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags) · 51 unmodified lines
224192 if (acpi_status)
225193 dev_dbg(dev->dev, "Error during ACPI methods call\n");
226194
227− if (adev->runpm) {
228− /* only need to skip on ATPX */
229− if (amdgpu_device_supports_px(dev))
230− dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
231− /* we want direct complete for BOCO */
232− if (amdgpu_device_supports_boco(dev))
233− dev_pm_set_driver_flags(dev->dev, DPM_FLAG_SMART_PREPARE |
234− DPM_FLAG_SMART_SUSPEND |
235− DPM_FLAG_MAY_SKIP_RESUME);
236− pm_runtime_use_autosuspend(dev->dev);
237− pm_runtime_set_autosuspend_delay(dev->dev, 5000);
238−
239− pm_runtime_allow(dev->dev);
240−
241− pm_runtime_mark_last_busy(dev->dev);
242− pm_runtime_put_autosuspend(dev->dev);
243−
244− /*
245− * For runpm implemented via BACO, PMFW will handle the
246− * timing for BACO in and out:
247− * - put ASIC into BACO state only when both video and
248− * audio functions are in D3 state.
249− * - pull ASIC out of BACO state when either video or
250− * audio function is in D0 state.
251− * Also, at startup, PMFW assumes both functions are in
252− * D0 state.
253− *
254− * So if snd driver was loaded prior to amdgpu driver
255− * and audio function was put into D3 state, there will
256− * be no PMFW-aware D-state transition(D0->D3) on runpm
257− * suspend. Thus the BACO will be not correctly kicked in.
258− *
259− * Via amdgpu_get_audio_func(), the audio dev is put
260− * into D0 state. Then there will be a PMFW-aware D-state
261− * transition(D0->D3) on runpm suspend.
262− */
263− if (amdgpu_device_supports_baco(dev) &&
264− !(adev->flags & AMD_IS_APU) &&
265− (adev->asic_type >= CHIP_NAVI10))
266− amdgpu_get_audio_func(adev);
267− }
268−
269195 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD))
270196 DRM_WARN("smart shift update failed\n");
271197
272198 out:
273− if (r) {
274− /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
275− if (adev->rmmio && adev->runpm)
276− pm_runtime_put_noidle(dev->dev);
199+ if (r)
277200 amdgpu_driver_unload_kms(dev);
278− }
279201
280202 return r;
281203 }
@@ -406,6 +328,10 @@ static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, · 124 unmodified lines
406328 fw_info->ver = adev->psp.toc.fw_version;
407329 fw_info->feature = adev->psp.toc.feature_version;
408330 break;
331+ case AMDGPU_INFO_FW_CAP:
332+ fw_info->ver = adev->psp.cap_fw_version;
333+ fw_info->feature = adev->psp.cap_feature_version;
334+ break;
409335 default:
410336 return -EINVAL;
411337 }
@@ -678,13 +604,13 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) · 266 unmodified lines
678604 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
679605 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
680606 case AMDGPU_INFO_VRAM_USAGE:
681− ui64 = amdgpu_vram_mgr_usage(&adev->mman.vram_mgr);
607+ ui64 = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager);
682608 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
683609 case AMDGPU_INFO_VIS_VRAM_USAGE:
684610 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
685611 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
686612 case AMDGPU_INFO_GTT_USAGE:
687− ui64 = amdgpu_gtt_mgr_usage(&adev->mman.gtt_mgr);
613+ ui64 = ttm_resource_manager_usage(&adev->mman.gtt_mgr.manager);
688614 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
689615 case AMDGPU_INFO_GDS_CONFIG: {
690616 struct drm_amdgpu_info_gds gds_info;
@@ -716,14 +642,17 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) · 25 unmodified lines
716642 case AMDGPU_INFO_MEMORY: {
717643 struct drm_amdgpu_memory_info mem;
718644 struct ttm_resource_manager *gtt_man =
719− ttm_manager_type(&adev->mman.bdev, TTM_PL_TT);
645+ &adev->mman.gtt_mgr.manager;
646+ struct ttm_resource_manager *vram_man =
647+ &adev->mman.vram_mgr.manager;
648+
720649 memset(&mem, 0, sizeof(mem));
721650 mem.vram.total_heap_size = adev->gmc.real_vram_size;
722651 mem.vram.usable_heap_size = adev->gmc.real_vram_size -
723652 atomic64_read(&adev->vram_pin_size) -
724653 AMDGPU_VM_RESERVED_VRAM;
725654 mem.vram.heap_usage =
726− amdgpu_vram_mgr_usage(&adev->mman.vram_mgr);
655+ ttm_resource_manager_usage(vram_man);
727656 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
728657
729658 mem.cpu_accessible_vram.total_heap_size =
@@ -741,8 +670,7 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) · 11 unmodified lines
741670 mem.gtt.total_heap_size *= PAGE_SIZE;
742671 mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
743672 atomic64_read(&adev->gart_pin_size);
744− mem.gtt.heap_usage =
745− amdgpu_gtt_mgr_usage(&adev->mman.gtt_mgr);
673+ mem.gtt.heap_usage = ttm_resource_manager_usage(gtt_man);
746674 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
747675
748676 return copy_to_user(out, &mem,
@@ -1268,18 +1196,20 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev, · 519 unmodified lines
12681196 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL)
12691197 amdgpu_vce_free_handles(adev, file_priv);
12701198
1271− amdgpu_vm_bo_rmv(adev, fpriv->prt_va);
1272−
12731199 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
12741200 /* TODO: how to handle reserve failure */
12751201 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
1276− amdgpu_vm_bo_rmv(adev, fpriv->csa_va);
1202+ amdgpu_vm_bo_del(adev, fpriv->csa_va);
12771203 fpriv->csa_va = NULL;
12781204 amdgpu_bo_unreserve(adev->virt.csa_obj);
12791205 }
12801206
12811207 pasid = fpriv->vm.pasid;
12821208 pd = amdgpu_bo_ref(fpriv->vm.root.bo);
1209+ if (!WARN_ON(amdgpu_bo_reserve(pd, true))) {
1210+ amdgpu_vm_bo_del(adev, fpriv->prt_va);
1211+ amdgpu_bo_unreserve(pd);
1212+ }
12831213
12841214 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
12851215 amdgpu_vm_fini(adev, &fpriv->vm);
@@ -1427,8 +1357,7 @@ static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused) · 141 unmodified lines
14271357 struct drm_amdgpu_info_firmware fw_info;
14281358 struct drm_amdgpu_query_fw query_fw;
14291359 struct atom_context *ctx = adev->mode_info.atom_context;
1430− uint8_t smu_minor, smu_debug;
1431− uint16_t smu_major;
1360+ uint8_t smu_program, smu_major, smu_minor, smu_debug;
14321361 int ret, i;
14331362
14341363 static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = {
@@ -1574,11 +1503,12 @@ static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused) · 139 unmodified lines
15741503 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
15751504 if (ret)
15761505 return ret;
1577− smu_major = (fw_info.ver >> 16) & 0xffff;
1506+ smu_program = (fw_info.ver >> 24) & 0xff;
1507+ smu_major = (fw_info.ver >> 16) & 0xff;
15781508 smu_minor = (fw_info.ver >> 8) & 0xff;
15791509 smu_debug = (fw_info.ver >> 0) & 0xff;
1580− seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x (%d.%d.%d)\n",
1581− fw_info.feature, fw_info.ver, smu_major, smu_minor, smu_debug);
1510+ seq_printf(m, "SMC feature version: %u, program: %d, firmware version: 0x%08x (%d.%d.%d)\n",
1511+ fw_info.feature, smu_program, fw_info.ver, smu_major, smu_minor, smu_debug);
15821512
15831513 /* SDMA */
15841514 query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
@@ -1623,6 +1553,16 @@ static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused) · 38 unmodified lines
16231553 seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n",
16241554 fw_info.feature, fw_info.ver);
16251555
1556+ /* CAP */
1557+ if (adev->psp.cap_fw) {
1558+ query_fw.fw_type = AMDGPU_INFO_FW_CAP;
1559+ ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1560+ if (ret)
1561+ return ret;
1562+ seq_printf(m, "CAP feature version: %u, firmware version: 0x%08x\n",
1563+ fw_info.feature, fw_info.ver);
1564+ }
1565+
16261566 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
16271567
16281568 return 0;
drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c+1−40
@@ -71,47 +71,8 @@ void amdgpu_mca_query_ras_error_count(struct amdgpu_device *adev, · 70 unmodified lines
7171 amdgpu_mca_reset_error_count(adev, mc_status_addr);
7272 }
7373
74−int amdgpu_mca_ras_late_init(struct amdgpu_device *adev,
75− struct amdgpu_mca_ras *mca_dev)
76−{
77− int r;
78− struct ras_ih_if ih_info = {
79− .cb = NULL,
80− };
81− struct ras_fs_if fs_info = {
82− .sysfs_name = mca_dev->ras_funcs->sysfs_name,
83− };
84−
85− if (!mca_dev->ras_if) {
86− mca_dev->ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
87− if (!mca_dev->ras_if)
88− return -ENOMEM;
89− mca_dev->ras_if->block = mca_dev->ras_funcs->ras_block;
90− mca_dev->ras_if->sub_block_index = mca_dev->ras_funcs->ras_sub_block;
91− mca_dev->ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
92− }
93− ih_info.head = fs_info.head = *mca_dev->ras_if;
94− r = amdgpu_ras_late_init(adev, mca_dev->ras_if,
95− &fs_info, &ih_info);
96− if (r || !amdgpu_ras_is_supported(adev, mca_dev->ras_if->block)) {
97− kfree(mca_dev->ras_if);
98− mca_dev->ras_if = NULL;
99− }
100−
101− return r;
102−}
103−
10474 void amdgpu_mca_ras_fini(struct amdgpu_device *adev,
10575 struct amdgpu_mca_ras *mca_dev)
10676 {
107− struct ras_ih_if ih_info = {
108− .cb = NULL,
109− };
110−
111− if (!mca_dev->ras_if)
112− return;
113−
114− amdgpu_ras_late_fini(adev, mca_dev->ras_if, &ih_info);
115− kfree(mca_dev->ras_if);
116− mca_dev->ras_if = NULL;
77+ amdgpu_ras_block_late_fini(adev, mca_dev->ras_if);
11778 }
drivers/gpu/drm/amd/amdgpu/amdgpu_mca.h+3−14
@@ -21,21 +21,13 @@ · 20 unmodified lines
2121 #ifndef __AMDGPU_MCA_H__
2222 #define __AMDGPU_MCA_H__
2323
24−struct amdgpu_mca_ras_funcs {
25− int (*ras_late_init)(struct amdgpu_device *adev);
26− void (*ras_fini)(struct amdgpu_device *adev);
27− void (*query_ras_error_count)(struct amdgpu_device *adev,
28− void *ras_error_status);
29− void (*query_ras_error_address)(struct amdgpu_device *adev,
30− void *ras_error_status);
31− uint32_t ras_block;
32− uint32_t ras_sub_block;
33− const char* sysfs_name;
24+struct amdgpu_mca_ras_block {
25+ struct amdgpu_ras_block_object ras_block;
3426 };
3527
3628 struct amdgpu_mca_ras {
3729 struct ras_common_if *ras_if;
38− const struct amdgpu_mca_ras_funcs *ras_funcs;
30+ struct amdgpu_mca_ras_block *ras;
3931 };
4032
4133 struct amdgpu_mca_funcs {
@@ -64,9 +56,6 @@ void amdgpu_mca_query_ras_error_count(struct amdgpu_device *adev, · 22 unmodified lines
6456 uint64_t mc_status_addr,
6557 void *ras_error_status);
6658
67−int amdgpu_mca_ras_late_init(struct amdgpu_device *adev,
68− struct amdgpu_mca_ras *mca_dev);
69−
7059 void amdgpu_mca_ras_fini(struct amdgpu_device *adev,
7160 struct amdgpu_mca_ras *mca_dev);
7261
drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.c+2−38
@@ -24,45 +24,9 @@ · 23 unmodified lines
2424 #include "amdgpu.h"
2525 #include "amdgpu_ras.h"
2626
27−int amdgpu_mmhub_ras_late_init(struct amdgpu_device *adev)
28−{
29− int r;
30− struct ras_ih_if ih_info = {
31− .cb = NULL,
32− };
33− struct ras_fs_if fs_info = {
34− .sysfs_name = "mmhub_err_count",
35− };
36−
37− if (!adev->mmhub.ras_if) {
38− adev->mmhub.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
39− if (!adev->mmhub.ras_if)
40− return -ENOMEM;
41− adev->mmhub.ras_if->block = AMDGPU_RAS_BLOCK__MMHUB;
42− adev->mmhub.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
43− adev->mmhub.ras_if->sub_block_index = 0;
44− }
45− ih_info.head = fs_info.head = *adev->mmhub.ras_if;
46− r = amdgpu_ras_late_init(adev, adev->mmhub.ras_if,
47− &fs_info, &ih_info);
48− if (r || !amdgpu_ras_is_supported(adev, adev->mmhub.ras_if->block)) {
49− kfree(adev->mmhub.ras_if);
50− adev->mmhub.ras_if = NULL;
51− }
52−
53− return r;
54−}
55−
5627 void amdgpu_mmhub_ras_fini(struct amdgpu_device *adev)
5728 {
5829 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB) &&
59− adev->mmhub.ras_if) {
60− struct ras_common_if *ras_if = adev->mmhub.ras_if;
61− struct ras_ih_if ih_info = {
62− .cb = NULL,
63− };
64−
65− amdgpu_ras_late_fini(adev, ras_if, &ih_info);
66− kfree(ras_if);
67− }
30+ adev->mmhub.ras_if)
31+ amdgpu_ras_block_late_fini(adev, adev->mmhub.ras_if);
6832 }
drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h+3−10
@@ -21,14 +21,8 @@ · 20 unmodified lines
2121 #ifndef __AMDGPU_MMHUB_H__
2222 #define __AMDGPU_MMHUB_H__
2323
24−struct amdgpu_mmhub_ras_funcs {
25− int (*ras_late_init)(struct amdgpu_device *adev);
26− void (*ras_fini)(struct amdgpu_device *adev);
27− void (*query_ras_error_count)(struct amdgpu_device *adev,
28− void *ras_error_status);
29− void (*query_ras_error_status)(struct amdgpu_device *adev);
30− void (*reset_ras_error_count)(struct amdgpu_device *adev);
31− void (*reset_ras_error_status)(struct amdgpu_device *adev);
24+struct amdgpu_mmhub_ras {
25+ struct amdgpu_ras_block_object ras_block;
3226 };
3327
3428 struct amdgpu_mmhub_funcs {
@@ -50,10 +44,9 @@ struct amdgpu_mmhub_funcs { · 15 unmodified lines
5044 struct amdgpu_mmhub {
5145 struct ras_common_if *ras_if;
5246 const struct amdgpu_mmhub_funcs *funcs;
53− const struct amdgpu_mmhub_ras_funcs *ras_funcs;
47+ struct amdgpu_mmhub_ras *ras;
5448 };
5549
56−int amdgpu_mmhub_ras_late_init(struct amdgpu_device *adev);
5750 void amdgpu_mmhub_ras_fini(struct amdgpu_device *adev);
5851 #endif
5952
drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c+7−37
@@ -22,61 +22,31 @@ · 21 unmodified lines
2222 #include "amdgpu.h"
2323 #include "amdgpu_ras.h"
2424
25−int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev)
25+int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
2626 {
2727 int r;
28− struct ras_ih_if ih_info = {
29− .cb = NULL,
30− };
31− struct ras_fs_if fs_info = {
32− .sysfs_name = "pcie_bif_err_count",
33− };
34−
35− if (!adev->nbio.ras_if) {
36− adev->nbio.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
37− if (!adev->nbio.ras_if)
38− return -ENOMEM;
39− adev->nbio.ras_if->block = AMDGPU_RAS_BLOCK__PCIE_BIF;
40− adev->nbio.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
41− adev->nbio.ras_if->sub_block_index = 0;
42− }
43− ih_info.head = fs_info.head = *adev->nbio.ras_if;
44− r = amdgpu_ras_late_init(adev, adev->nbio.ras_if,
45− &fs_info, &ih_info);
28+ r = amdgpu_ras_block_late_init(adev, ras_block);
4629 if (r)
47− goto free;
30+ return r;
4831
49− if (amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
32+ if (amdgpu_ras_is_supported(adev, ras_block->block)) {
5033 r = amdgpu_irq_get(adev, &adev->nbio.ras_controller_irq, 0);
5134 if (r)
5235 goto late_fini;
5336 r = amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0);
5437 if (r)
5538 goto late_fini;
56− } else {
57− r = 0;
58− goto free;
5939 }
6040
6141 return 0;
6242 late_fini:
63− amdgpu_ras_late_fini(adev, adev->nbio.ras_if, &ih_info);
64−free:
65− kfree(adev->nbio.ras_if);
66− adev->nbio.ras_if = NULL;
43+ amdgpu_ras_block_late_fini(adev, ras_block);
6744 return r;
6845 }
6946
7047 void amdgpu_nbio_ras_fini(struct amdgpu_device *adev)
7148 {
7249 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__PCIE_BIF) &&
73− adev->nbio.ras_if) {
74− struct ras_common_if *ras_if = adev->nbio.ras_if;
75− struct ras_ih_if ih_info = {
76− .cb = NULL,
77− };
78−
79− amdgpu_ras_late_fini(adev, ras_if, &ih_info);
80− kfree(ras_if);
81− }
50+ adev->nbio.ras_if)
51+ amdgpu_ras_block_late_fini(adev, adev->nbio.ras_if);
8252 }
drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h+4−7
@@ -47,15 +47,12 @@ struct nbio_hdp_flush_reg { · 46 unmodified lines
4747 u32 ref_and_mask_sdma7;
4848 };
4949
50−struct amdgpu_nbio_ras_funcs {
50+struct amdgpu_nbio_ras {
51+ struct amdgpu_ras_block_object ras_block;
5152 void (*handle_ras_controller_intr_no_bifring)(struct amdgpu_device *adev);
5253 void (*handle_ras_err_event_athub_intr_no_bifring)(struct amdgpu_device *adev);
5354 int (*init_ras_controller_interrupt)(struct amdgpu_device *adev);
5455 int (*init_ras_err_event_athub_interrupt)(struct amdgpu_device *adev);
55− void (*query_ras_error_count)(struct amdgpu_device *adev,
56− void *ras_error_status);
57− int (*ras_late_init)(struct amdgpu_device *adev);
58− void (*ras_fini)(struct amdgpu_device *adev);
5956 };
6057
6158 struct amdgpu_nbio_funcs {
@@ -104,9 +101,9 @@ struct amdgpu_nbio { · 42 unmodified lines
104101 struct amdgpu_irq_src ras_err_event_athub_irq;
105102 struct ras_common_if *ras_if;
106103 const struct amdgpu_nbio_funcs *funcs;
107− const struct amdgpu_nbio_ras_funcs *ras_funcs;
104+ struct amdgpu_nbio_ras *ras;
108105 };
109106
110−int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev);
107+int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);
111108 void amdgpu_nbio_ras_fini(struct amdgpu_device *adev);
112109 #endif
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c+7−3
@@ -451,7 +451,7 @@ static bool amdgpu_bo_validate_size(struct amdgpu_device *adev, · 450 unmodified lines
451451 if (domain & AMDGPU_GEM_DOMAIN_GTT) {
452452 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT);
453453
454− if (size < (man->size << PAGE_SHIFT))
454+ if (size < man->size)
455455 return true;
456456 else
457457 goto fail;
@@ -460,7 +460,7 @@ static bool amdgpu_bo_validate_size(struct amdgpu_device *adev, · 2 unmodified lines
460460 if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
461461 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
462462
463− if (size < (man->size << PAGE_SHIFT))
463+ if (size < man->size)
464464 return true;
465465 else
466466 goto fail;
@@ -575,6 +575,9 @@ int amdgpu_bo_create(struct amdgpu_device *adev, · 108 unmodified lines
575575 if (!amdgpu_bo_support_uswc(bo->flags))
576576 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
577577
578+ if (adev->ras_enabled)
579+ bo->flags |= AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE;
580+
578581 bo->tbo.bdev = &adev->mman.bdev;
579582 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA |
580583 AMDGPU_GEM_DOMAIN_GDS))
@@ -1303,7 +1306,8 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object *bo) · 722 unmodified lines
13031306 !(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE))
13041307 return;
13051308
1306− dma_resv_lock(bo->base.resv, NULL);
1309+ if (WARN_ON_ONCE(!dma_resv_trylock(bo->base.resv)))
1310+ return;
13071311
13081312 r = amdgpu_fill_buffer(abo, AMDGPU_POISON, bo->base.resv, &fence);
13091313 if (!WARN_ON(r)) {
drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.c+5−57
@@ -25,12 +25,6 @@ · 24 unmodified lines
2525
2626 #include "amdgpu.h"
2727
28−static inline struct amdgpu_preempt_mgr *
29−to_preempt_mgr(struct ttm_resource_manager *man)
30−{
31− return container_of(man, struct amdgpu_preempt_mgr, manager);
32−}
33−
3428 /**
3529 * DOC: mem_info_preempt_used
3630 *
@@ -45,10 +39,9 @@ static ssize_t mem_info_preempt_used_show(struct device *dev, · 8 unmodified lines
4539 {
4640 struct drm_device *ddev = dev_get_drvdata(dev);
4741 struct amdgpu_device *adev = drm_to_adev(ddev);
48− struct ttm_resource_manager *man;
42+ struct ttm_resource_manager *man = &adev->mman.preempt_mgr;
4943
50− man = ttm_manager_type(&adev->mman.bdev, AMDGPU_PL_PREEMPT);
51− return sysfs_emit(buf, "%llu\n", amdgpu_preempt_mgr_usage(man));
44+ return sysfs_emit(buf, "%llu\n", ttm_resource_manager_usage(man));
5245 }
5346
5447 static DEVICE_ATTR_RO(mem_info_preempt_used);
@@ -68,16 +61,12 @@ static int amdgpu_preempt_mgr_new(struct ttm_resource_manager *man, · 13 unmodified lines
6861 const struct ttm_place *place,
6962 struct ttm_resource **res)
7063 {
71− struct amdgpu_preempt_mgr *mgr = to_preempt_mgr(man);
72−
7364 *res = kzalloc(sizeof(**res), GFP_KERNEL);
7465 if (!*res)
7566 return -ENOMEM;
7667
7768 ttm_resource_init(tbo, place, *res);
7869 (*res)->start = AMDGPU_BO_INVALID_OFFSET;
79−
80− atomic64_add((*res)->num_pages, &mgr->used);
8170 return 0;
8271 }
8372
@@ -92,49 +81,13 @@ static int amdgpu_preempt_mgr_new(struct ttm_resource_manager *man, · 8 unmodified lines
9281 static void amdgpu_preempt_mgr_del(struct ttm_resource_manager *man,
9382 struct ttm_resource *res)
9483 {
95− struct amdgpu_preempt_mgr *mgr = to_preempt_mgr(man);
96−
97− atomic64_sub(res->num_pages, &mgr->used);
9884 ttm_resource_fini(man, res);
9985 kfree(res);
10086 }
10187
102−/**
103− * amdgpu_preempt_mgr_usage - return usage of PREEMPT domain
104− *
105− * @man: TTM memory type manager
106− *
107− * Return how many bytes are used in the GTT domain
108− */
109−uint64_t amdgpu_preempt_mgr_usage(struct ttm_resource_manager *man)
110−{
111− struct amdgpu_preempt_mgr *mgr = to_preempt_mgr(man);
112− s64 result = atomic64_read(&mgr->used);
113−
114− return (result > 0 ? result : 0) * PAGE_SIZE;
115−}
116−
117−/**
118− * amdgpu_preempt_mgr_debug - dump VRAM table
119− *
120− * @man: TTM memory type manager
121− * @printer: DRM printer to use
122− *
123− * Dump the table content using printk.
124− */
125−static void amdgpu_preempt_mgr_debug(struct ttm_resource_manager *man,
126− struct drm_printer *printer)
127−{
128− struct amdgpu_preempt_mgr *mgr = to_preempt_mgr(man);
129−
130− drm_printf(printer, "man size:%llu pages, preempt used:%lld pages\n",
131− man->size, (u64)atomic64_read(&mgr->used));
132−}
133−
13488 static const struct ttm_resource_manager_func amdgpu_preempt_mgr_func = {
13589 .alloc = amdgpu_preempt_mgr_new,
13690 .free = amdgpu_preempt_mgr_del,
137− .debug = amdgpu_preempt_mgr_debug
13891 };
13992
14093 /**
@@ -146,8 +99,7 @@ static const struct ttm_resource_manager_func amdgpu_preempt_mgr_func = { · 5 unmodified lines
14699 */
147100 int amdgpu_preempt_mgr_init(struct amdgpu_device *adev)
148101 {
149− struct amdgpu_preempt_mgr *mgr = &adev->mman.preempt_mgr;
150− struct ttm_resource_manager *man = &mgr->manager;
102+ struct ttm_resource_manager *man = &adev->mman.preempt_mgr;
151103 int ret;
152104
153105 man->use_tt = true;
@@ -155,16 +107,13 @@ int amdgpu_preempt_mgr_init(struct amdgpu_device *adev) · 1 unmodified line
155107
156108 ttm_resource_manager_init(man, &adev->mman.bdev, (1 << 30));
157109
158− atomic64_set(&mgr->used, 0);
159−
160110 ret = device_create_file(adev->dev, &dev_attr_mem_info_preempt_used);
161111 if (ret) {
162112 DRM_ERROR("Failed to create device file mem_info_preempt_used\n");
163113 return ret;
164114 }
165115
166− ttm_set_driver_manager(&adev->mman.bdev, AMDGPU_PL_PREEMPT,
167− &mgr->manager);
116+ ttm_set_driver_manager(&adev->mman.bdev, AMDGPU_PL_PREEMPT, man);
168117 ttm_resource_manager_set_used(man, true);
169118 return 0;
170119 }
@@ -179,8 +128,7 @@ int amdgpu_preempt_mgr_init(struct amdgpu_device *adev) · 8 unmodified lines
179128 */
180129 void amdgpu_preempt_mgr_fini(struct amdgpu_device *adev)
181130 {
182− struct amdgpu_preempt_mgr *mgr = &adev->mman.preempt_mgr;
183− struct ttm_resource_manager *man = &mgr->manager;
131+ struct ttm_resource_manager *man = &adev->mman.preempt_mgr;
184132 int ret;
185133
186134 ttm_resource_manager_set_used(man, false);
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c+105−19
@@ -133,6 +133,7 @@ static int psp_early_init(void *handle) · 132 unmodified lines
133133 break;
134134 case IP_VERSION(13, 0, 1):
135135 case IP_VERSION(13, 0, 3):
136+ case IP_VERSION(13, 0, 8):
136137 psp_v13_0_set_psp_funcs(psp);
137138 psp->autoload_supported = true;
138139 break;
@@ -259,6 +260,32 @@ static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, · 120 unmodified lines
259260 return ret;
260261 }
261262
263+static int psp_init_sriov_microcode(struct psp_context *psp)
264+{
265+ struct amdgpu_device *adev = psp->adev;
266+ int ret = 0;
267+
268+ switch (adev->ip_versions[MP0_HWIP][0]) {
269+ case IP_VERSION(9, 0, 0):
270+ ret = psp_init_cap_microcode(psp, "vega10");
271+ break;
272+ case IP_VERSION(11, 0, 9):
273+ ret = psp_init_cap_microcode(psp, "navi12");
274+ break;
275+ case IP_VERSION(11, 0, 7):
276+ ret = psp_init_cap_microcode(psp, "sienna_cichlid");
277+ break;
278+ case IP_VERSION(13, 0, 2):
279+ ret = psp_init_ta_microcode(psp, "aldebaran");
280+ break;
281+ default:
282+ BUG();
283+ break;
284+ }
285+
286+ return ret;
287+}
288+
262289 static int psp_sw_init(void *handle)
263290 {
264291 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -273,19 +300,13 @@ static int psp_sw_init(void *handle) · 8 unmodified lines
273300 ret = -ENOMEM;
274301 }
275302
276− if (!amdgpu_sriov_vf(adev)) {
303+ if (amdgpu_sriov_vf(adev))
304+ ret = psp_init_sriov_microcode(psp);
305+ else
277306 ret = psp_init_microcode(psp);
278− if (ret) {
279− DRM_ERROR("Failed to load psp firmware!\n");
280− return ret;
281− }
282− } else if (amdgpu_sriov_vf(adev) &&
283− adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2)) {
284− ret = psp_init_ta_microcode(psp, "aldebaran");
285− if (ret) {
286− DRM_ERROR("Failed to initialize ta microcode!\n");
287− return ret;
288− }
307+ if (ret) {
308+ DRM_ERROR("Failed to load psp firmware!\n");
309+ return ret;
289310 }
290311
291312 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry));
@@ -353,6 +374,10 @@ static int psp_sw_fini(void *handle) · 61 unmodified lines
353374 release_firmware(psp->ta_fw);
354375 psp->ta_fw = NULL;
355376 }
377+ if (adev->psp.cap_fw) {
378+ release_firmware(psp->cap_fw);
379+ psp->cap_fw = NULL;
380+ }
356381
357382 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||
358383 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7))
@@ -491,7 +516,10 @@ psp_cmd_submit_buf(struct psp_context *psp, · 132 unmodified lines
491516 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n",
492517 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id,
493518 psp->cmd_buf_mem->resp.status);
494− if (!timeout) {
519+ /* If we load CAP FW, PSP must return 0 under SRIOV
520+ * also return failure in case of timeout
521+ */
522+ if ((ucode && (ucode->ucode_id == AMDGPU_UCODE_ID_CAP)) || !timeout) {
495523 ret = -EINVAL;
496524 goto exit;
497525 }
@@ -914,19 +942,15 @@ static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, · 416 unmodified lines
914942 static int psp_ta_init_shared_buf(struct psp_context *psp,
915943 struct ta_mem_context *mem_ctx)
916944 {
917− int ret;
918−
919945 /*
920946 * Allocate 16k memory aligned to 4k from Frame Buffer (local
921947 * physical) for ta to host memory
922948 */
923− ret = amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size,
949+ return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size,
924950 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
925951 &mem_ctx->shared_bo,
926952 &mem_ctx->shared_mc_addr,
927953 &mem_ctx->shared_buf);
928−
929− return ret;
930954 }
931955
932956 static void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx)
@@ -1308,6 +1332,11 @@ static void psp_ras_ta_check_status(struct psp_context *psp) · 375 unmodified lines
13081332 break;
13091333 case TA_RAS_STATUS__SUCCESS:
13101334 break;
1335+ case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED:
1336+ if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR)
1337+ dev_warn(psp->adev->dev,
1338+ "RAS WARNING: Inject error to critical region is not allowed\n");
1339+ break;
13111340 default:
13121341 dev_warn(psp->adev->dev,
13131342 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status);
@@ -1520,7 +1549,9 @@ int psp_ras_trigger_error(struct psp_context *psp, · 206 unmodified lines
15201549 if (amdgpu_ras_intr_triggered())
15211550 return 0;
15221551
1523− if (ras_cmd->ras_status)
1552+ if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED)
1553+ return -EACCES;
1554+ else if (ras_cmd->ras_status)
15241555 return -EINVAL;
15251556
15261557 return 0;
@@ -2051,6 +2082,9 @@ static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, · 524 unmodified lines
20512082 enum psp_gfx_fw_type *type)
20522083 {
20532084 switch (ucode->ucode_id) {
2085+ case AMDGPU_UCODE_ID_CAP:
2086+ *type = GFX_FW_TYPE_CAP;
2087+ break;
20542088 case AMDGPU_UCODE_ID_SDMA0:
20552089 *type = GFX_FW_TYPE_SDMA0;
20562090 break;
@@ -3217,6 +3251,58 @@ out: · 1160 unmodified lines
32173251 return err;
32183252 }
32193253
3254+int psp_init_cap_microcode(struct psp_context *psp,
3255+ const char *chip_name)
3256+{
3257+ struct amdgpu_device *adev = psp->adev;
3258+ char fw_name[PSP_FW_NAME_LEN];
3259+ const struct psp_firmware_header_v1_0 *cap_hdr_v1_0;
3260+ struct amdgpu_firmware_info *info = NULL;
3261+ int err = 0;
3262+
3263+ if (!chip_name) {
3264+ dev_err(adev->dev, "invalid chip name for cap microcode\n");
3265+ return -EINVAL;
3266+ }
3267+
3268+ if (!amdgpu_sriov_vf(adev)) {
3269+ dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n");
3270+ return -EINVAL;
3271+ }
3272+
3273+ snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name);
3274+ err = request_firmware(&adev->psp.cap_fw, fw_name, adev->dev);
3275+ if (err) {
3276+ dev_warn(adev->dev, "cap microcode does not exist, skip\n");
3277+ err = 0;
3278+ goto out;
3279+ }
3280+
3281+ err = amdgpu_ucode_validate(adev->psp.cap_fw);
3282+ if (err) {
3283+ dev_err(adev->dev, "fail to initialize cap microcode\n");
3284+ goto out;
3285+ }
3286+
3287+ info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP];
3288+ info->ucode_id = AMDGPU_UCODE_ID_CAP;
3289+ info->fw = adev->psp.cap_fw;
3290+ cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *)
3291+ adev->psp.cap_fw->data;
3292+ adev->firmware.fw_size += ALIGN(
3293+ le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE);
3294+ adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version);
3295+ adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version);
3296+ adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes);
3297+
3298+ return 0;
3299+
3300+out:
3301+ release_firmware(adev->psp.cap_fw);
3302+ adev->psp.cap_fw = NULL;
3303+ return err;
3304+}
3305+
32203306 static int psp_set_clockgating_state(void *handle,
32213307 enum amd_clockgating_state state)
32223308 {
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h+9−0
@@ -306,6 +306,9 @@ struct psp_context · 305 unmodified lines
306306 /* toc firmware */
307307 const struct firmware *toc_fw;
308308
309+ /* cap firmware */
310+ const struct firmware *cap_fw;
311+
309312 /* fence buffer */
310313 struct amdgpu_bo *fence_buf_bo;
311314 uint64_t fence_buf_mc_addr;
@@ -327,6 +330,10 @@ struct psp_context · 15 unmodified lines
327330 const struct firmware *ta_fw;
328331 uint32_t ta_fw_version;
329332
333+ uint32_t cap_fw_version;
334+ uint32_t cap_feature_version;
335+ uint32_t cap_ucode_size;
336+
330337 struct ta_context asd_context;
331338 struct psp_xgmi_context xgmi_context;
332339 struct psp_ras_context ras_context;
@@ -440,6 +447,8 @@ int psp_init_sos_microcode(struct psp_context *psp, · 107 unmodified lines
440447 const char *chip_name);
441448 int psp_init_ta_microcode(struct psp_context *psp,
442449 const char *chip_name);
450+int psp_init_cap_microcode(struct psp_context *psp,
451+ const char *chip_name);
443452 int psp_get_fw_attestation_records_addr(struct psp_context *psp,
444453 uint64_t *output_ptr);
445454
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c+285−240
@@ -75,6 +75,13 @@ const char *ras_mca_block_string[] = { · 74 unmodified lines
7575 "mca_iohc",
7676 };
7777
78+struct amdgpu_ras_block_list {
79+ /* ras block link */
80+ struct list_head node;
81+
82+ struct amdgpu_ras_block_object *ras_obj;
83+};
84+
7885 const char *get_ras_block_str(struct ras_common_if *ras_block)
7986 {
8087 if (!ras_block)
@@ -89,6 +96,9 @@ const char *get_ras_block_str(struct ras_common_if *ras_block) · 8 unmodified lines
8996 return ras_block_string[ras_block->block];
9097 }
9198
99+#define ras_block_str(_BLOCK_) \
100+ (((_BLOCK_) < ARRAY_SIZE(ras_block_string)) ? ras_block_string[_BLOCK_] : "Out Of Range")
101+
92102 #define ras_err_str(i) (ras_error_string[ffs(i)])
93103
94104 #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
@@ -155,14 +165,9 @@ static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t addre · 60 unmodified lines
155165 }
156166
157167 memset(&err_rec, 0x0, sizeof(struct eeprom_table_record));
158−
159− err_rec.address = address;
160− err_rec.retired_page = address >> AMDGPU_GPU_PAGE_SHIFT;
161− err_rec.ts = (uint64_t)ktime_get_real_seconds();
162− err_rec.err_type = AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE;
163−
164168 err_data.err_addr = &err_rec;
165− err_data.err_addr_cnt = 1;
169+ amdgpu_umc_fill_error_record(&err_data, address,
170+ (address >> AMDGPU_GPU_PAGE_SHIFT), 0, 0);
166171
167172 if (amdgpu_bad_page_threshold != 0) {
168173 amdgpu_ras_add_bad_pages(adev, err_data.err_addr,
@@ -452,7 +457,7 @@ static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, · 283 unmodified lines
452457 }
453458
454459 if (ret)
455− return -EINVAL;
460+ return ret;
456461
457462 return size;
458463 }
@@ -866,30 +871,47 @@ static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev, · 407 unmodified lines
866871 }
867872 /* feature ctl end */
868873
874+static int amdgpu_ras_block_match_default(struct amdgpu_ras_block_object *block_obj,
875+ enum amdgpu_ras_block block)
876+{
877+ if (!block_obj)
878+ return -EINVAL;
879+
880+ if (block_obj->ras_comm.block == block)
881+ return 0;
882+
883+ return -EINVAL;
884+}
869885
870−static void amdgpu_ras_mca_query_error_status(struct amdgpu_device *adev,
871− struct ras_common_if *ras_block,
872− struct ras_err_data *err_data)
886+static struct amdgpu_ras_block_object *amdgpu_ras_get_ras_block(struct amdgpu_device *adev,
887+ enum amdgpu_ras_block block, uint32_t sub_block_index)
873888 {
874− switch (ras_block->sub_block_index) {
875− case AMDGPU_RAS_MCA_BLOCK__MP0:
876− if (adev->mca.mp0.ras_funcs &&
877− adev->mca.mp0.ras_funcs->query_ras_error_count)
878− adev->mca.mp0.ras_funcs->query_ras_error_count(adev, &err_data);
879− break;
880− case AMDGPU_RAS_MCA_BLOCK__MP1:
881− if (adev->mca.mp1.ras_funcs &&
882− adev->mca.mp1.ras_funcs->query_ras_error_count)
883− adev->mca.mp1.ras_funcs->query_ras_error_count(adev, &err_data);
884− break;
885− case AMDGPU_RAS_MCA_BLOCK__MPIO:
886− if (adev->mca.mpio.ras_funcs &&
887− adev->mca.mpio.ras_funcs->query_ras_error_count)
888− adev->mca.mpio.ras_funcs->query_ras_error_count(adev, &err_data);
889− break;
890− default:
891− break;
889+ struct amdgpu_ras_block_list *node, *tmp;
890+ struct amdgpu_ras_block_object *obj;
891+
892+ if (block >= AMDGPU_RAS_BLOCK__LAST)
893+ return NULL;
894+
895+ if (!amdgpu_ras_is_supported(adev, block))
896+ return NULL;
897+
898+ list_for_each_entry_safe(node, tmp, &adev->ras_list, node) {
899+ if (!node->ras_obj) {
900+ dev_warn(adev->dev, "Warning: abnormal ras list node.\n");
901+ continue;
902+ }
903+
904+ obj = node->ras_obj;
905+ if (obj->ras_block_match) {
906+ if (obj->ras_block_match(obj, block, sub_block_index) == 0)
907+ return obj;
908+ } else {
909+ if (amdgpu_ras_block_match_default(obj, block) == 0)
910+ return obj;
911+ }
892912 }
913+
914+ return NULL;
893915 }
894916
895917 static void amdgpu_ras_get_ecc_info(struct amdgpu_device *adev, struct ras_err_data *err_data)
@@ -901,26 +923,26 @@ static void amdgpu_ras_get_ecc_info(struct amdgpu_device *adev, struct ras_err_d · 5 unmodified lines
901923 * choosing right query method according to
902924 * whether smu support query error information
903925 */
904− ret = smu_get_ecc_info(&adev->smu, (void *)&(ras->umc_ecc));
926+ ret = amdgpu_dpm_get_ecc_info(adev, (void *)&(ras->umc_ecc));
905927 if (ret == -EOPNOTSUPP) {
906− if (adev->umc.ras_funcs &&
907− adev->umc.ras_funcs->query_ras_error_count)
908− adev->umc.ras_funcs->query_ras_error_count(adev, err_data);
928+ if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
929+ adev->umc.ras->ras_block.hw_ops->query_ras_error_count)
930+ adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data);
909931
910932 /* umc query_ras_error_address is also responsible for clearing
911933 * error status
912934 */
913− if (adev->umc.ras_funcs &&
914− adev->umc.ras_funcs->query_ras_error_address)
915− adev->umc.ras_funcs->query_ras_error_address(adev, err_data);
935+ if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
936+ adev->umc.ras->ras_block.hw_ops->query_ras_error_address)
937+ adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, err_data);
916938 } else if (!ret) {
917− if (adev->umc.ras_funcs &&
918− adev->umc.ras_funcs->ecc_info_query_ras_error_count)
919− adev->umc.ras_funcs->ecc_info_query_ras_error_count(adev, err_data);
939+ if (adev->umc.ras &&
940+ adev->umc.ras->ecc_info_query_ras_error_count)
941+ adev->umc.ras->ecc_info_query_ras_error_count(adev, err_data);
920942
921− if (adev->umc.ras_funcs &&
922− adev->umc.ras_funcs->ecc_info_query_ras_error_address)
923− adev->umc.ras_funcs->ecc_info_query_ras_error_address(adev, err_data);
943+ if (adev->umc.ras &&
944+ adev->umc.ras->ecc_info_query_ras_error_address)
945+ adev->umc.ras->ecc_info_query_ras_error_address(adev, err_data);
924946 }
925947 }
926948
@@ -928,62 +950,32 @@ static void amdgpu_ras_get_ecc_info(struct amdgpu_device *adev, struct ras_err_d · 1 unmodified line
928950 int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
929951 struct ras_query_if *info)
930952 {
953+ struct amdgpu_ras_block_object *block_obj = NULL;
931954 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
932955 struct ras_err_data err_data = {0, 0, 0, NULL};
933− int i;
934956
935957 if (!obj)
936958 return -EINVAL;
937959
938− switch (info->head.block) {
939− case AMDGPU_RAS_BLOCK__UMC:
960+ if (info->head.block == AMDGPU_RAS_BLOCK__UMC) {
940961 amdgpu_ras_get_ecc_info(adev, &err_data);
941− break;
942− case AMDGPU_RAS_BLOCK__SDMA:
943− if (adev->sdma.funcs->query_ras_error_count) {
944− for (i = 0; i < adev->sdma.num_instances; i++)
945− adev->sdma.funcs->query_ras_error_count(adev, i,
946− &err_data);
962+ } else {
963+ block_obj = amdgpu_ras_get_ras_block(adev, info->head.block, 0);
964+ if (!block_obj || !block_obj->hw_ops) {
965+ dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
966+ get_ras_block_str(&info->head));
967+ return -EINVAL;
947968 }
948− break;
949− case AMDGPU_RAS_BLOCK__GFX:
950− if (adev->gfx.ras_funcs &&
951− adev->gfx.ras_funcs->query_ras_error_count)
952− adev->gfx.ras_funcs->query_ras_error_count(adev, &err_data);
953−
954− if (adev->gfx.ras_funcs &&
955− adev->gfx.ras_funcs->query_ras_error_status)
956− adev->gfx.ras_funcs->query_ras_error_status(adev);
957− break;
958− case AMDGPU_RAS_BLOCK__MMHUB:
959− if (adev->mmhub.ras_funcs &&
960− adev->mmhub.ras_funcs->query_ras_error_count)
961− adev->mmhub.ras_funcs->query_ras_error_count(adev, &err_data);
962−
963− if (adev->mmhub.ras_funcs &&
964− adev->mmhub.ras_funcs->query_ras_error_status)
965− adev->mmhub.ras_funcs->query_ras_error_status(adev);
966− break;
967− case AMDGPU_RAS_BLOCK__PCIE_BIF:
968− if (adev->nbio.ras_funcs &&
969− adev->nbio.ras_funcs->query_ras_error_count)
970− adev->nbio.ras_funcs->query_ras_error_count(adev, &err_data);
971− break;
972− case AMDGPU_RAS_BLOCK__XGMI_WAFL:
973− if (adev->gmc.xgmi.ras_funcs &&
974− adev->gmc.xgmi.ras_funcs->query_ras_error_count)
975− adev->gmc.xgmi.ras_funcs->query_ras_error_count(adev, &err_data);
976− break;
977− case AMDGPU_RAS_BLOCK__HDP:
978− if (adev->hdp.ras_funcs &&
979− adev->hdp.ras_funcs->query_ras_error_count)
980− adev->hdp.ras_funcs->query_ras_error_count(adev, &err_data);
981− break;
982− case AMDGPU_RAS_BLOCK__MCA:
983− amdgpu_ras_mca_query_error_status(adev, &info->head, &err_data);
984− break;
985− default:
986− break;
969+
970+ if (block_obj->hw_ops->query_ras_error_count)
971+ block_obj->hw_ops->query_ras_error_count(adev, &err_data);
972+
973+ if ((info->head.block == AMDGPU_RAS_BLOCK__SDMA) ||
974+ (info->head.block == AMDGPU_RAS_BLOCK__GFX) ||
975+ (info->head.block == AMDGPU_RAS_BLOCK__MMHUB)) {
976+ if (block_obj->hw_ops->query_ras_error_status)
977+ block_obj->hw_ops->query_ras_error_status(adev);
978+ }
987979 }
988980
989981 obj->err_data.ue_count += err_data.ue_count;
@@ -1040,68 +1032,27 @@ int amdgpu_ras_query_error_status(struct amdgpu_device *adev, · 50 unmodified lines
10401032 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
10411033 enum amdgpu_ras_block block)
10421034 {
1035+ struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, block, 0);
1036+
10431037 if (!amdgpu_ras_is_supported(adev, block))
10441038 return -EINVAL;
10451039
1046− switch (block) {
1047− case AMDGPU_RAS_BLOCK__GFX:
1048− if (adev->gfx.ras_funcs &&
1049− adev->gfx.ras_funcs->reset_ras_error_count)
1050− adev->gfx.ras_funcs->reset_ras_error_count(adev);
1051−
1052− if (adev->gfx.ras_funcs &&
1053− adev->gfx.ras_funcs->reset_ras_error_status)
1054− adev->gfx.ras_funcs->reset_ras_error_status(adev);
1055− break;
1056− case AMDGPU_RAS_BLOCK__MMHUB:
1057− if (adev->mmhub.ras_funcs &&
1058− adev->mmhub.ras_funcs->reset_ras_error_count)
1059− adev->mmhub.ras_funcs->reset_ras_error_count(adev);
1060−
1061− if (adev->mmhub.ras_funcs &&
1062− adev->mmhub.ras_funcs->reset_ras_error_status)
1063− adev->mmhub.ras_funcs->reset_ras_error_status(adev);
1064− break;
1065− case AMDGPU_RAS_BLOCK__SDMA:
1066− if (adev->sdma.funcs->reset_ras_error_count)
1067− adev->sdma.funcs->reset_ras_error_count(adev);
1068− break;
1069− case AMDGPU_RAS_BLOCK__HDP:
1070− if (adev->hdp.ras_funcs &&
1071− adev->hdp.ras_funcs->reset_ras_error_count)
1072− adev->hdp.ras_funcs->reset_ras_error_count(adev);
1073− break;
1074− default:
1075− break;
1040+ if (!block_obj || !block_obj->hw_ops) {
1041+ dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1042+ ras_block_str(block));
1043+ return -EINVAL;
10761044 }
10771045
1078− return 0;
1079−}
1080−
1081−/* Trigger XGMI/WAFL error */
1082−static int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev,
1083− struct ta_ras_trigger_error_input *block_info)
1084−{
1085− int ret;
1046+ if (block_obj->hw_ops->reset_ras_error_count)
1047+ block_obj->hw_ops->reset_ras_error_count(adev);
10861048
1087− if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))
1088− dev_warn(adev->dev, "Failed to disallow df cstate");
1089−
1090− if (amdgpu_dpm_allow_xgmi_power_down(adev, false))
1091− dev_warn(adev->dev, "Failed to disallow XGMI power down");
1092−
1093− ret = psp_ras_trigger_error(&adev->psp, block_info);
1094−
1095− if (amdgpu_ras_intr_triggered())
1096− return ret;
1097−
1098− if (amdgpu_dpm_allow_xgmi_power_down(adev, true))
1099− dev_warn(adev->dev, "Failed to allow XGMI power down");
1100−
1101− if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_ALLOW))
1102− dev_warn(adev->dev, "Failed to allow df cstate");
1049+ if ((block == AMDGPU_RAS_BLOCK__GFX) ||
1050+ (block == AMDGPU_RAS_BLOCK__MMHUB)) {
1051+ if (block_obj->hw_ops->reset_ras_error_status)
1052+ block_obj->hw_ops->reset_ras_error_status(adev);
1053+ }
11031054
1104− return ret;
1055+ return 0;
11051056 }
11061057
11071058 /* wrapper of psp_ras_trigger_error */
@@ -1116,11 +1067,20 @@ int amdgpu_ras_error_inject(struct amdgpu_device *adev, · 8 unmodified lines
11161067 .address = info->address,
11171068 .value = info->value,
11181069 };
1119− int ret = 0;
1070+ int ret = -EINVAL;
1071+ struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev,
1072+ info->head.block,
1073+ info->head.sub_block_index);
11201074
11211075 if (!obj)
11221076 return -EINVAL;
11231077
1078+ if (!block_obj || !block_obj->hw_ops) {
1079+ dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1080+ get_ras_block_str(&info->head));
1081+ return -EINVAL;
1082+ }
1083+
11241084 /* Calculate XGMI relative offset */
11251085 if (adev->gmc.xgmi.num_physical_nodes > 1) {
11261086 block_info.address =
@@ -1128,28 +1088,15 @@ int amdgpu_ras_error_inject(struct amdgpu_device *adev, · 1 unmodified line
11281088 block_info.address);
11291089 }
11301090
1131− switch (info->head.block) {
1132− case AMDGPU_RAS_BLOCK__GFX:
1133− if (adev->gfx.ras_funcs &&
1134− adev->gfx.ras_funcs->ras_error_inject)
1135− ret = adev->gfx.ras_funcs->ras_error_inject(adev, info);
1136− else
1137− ret = -EINVAL;
1138− break;
1139− case AMDGPU_RAS_BLOCK__UMC:
1140− case AMDGPU_RAS_BLOCK__SDMA:
1141− case AMDGPU_RAS_BLOCK__MMHUB:
1142− case AMDGPU_RAS_BLOCK__PCIE_BIF:
1143− case AMDGPU_RAS_BLOCK__MCA:
1144− ret = psp_ras_trigger_error(&adev->psp, &block_info);
1145− break;
1146− case AMDGPU_RAS_BLOCK__XGMI_WAFL:
1147− ret = amdgpu_ras_error_inject_xgmi(adev, &block_info);
1148− break;
1149− default:
1150− dev_info(adev->dev, "%s error injection is not supported yet\n",
1151− get_ras_block_str(&info->head));
1152− ret = -EINVAL;
1091+ if (info->head.block == AMDGPU_RAS_BLOCK__GFX) {
1092+ if (block_obj->hw_ops->ras_error_inject)
1093+ ret = block_obj->hw_ops->ras_error_inject(adev, info);
1094+ } else {
1095+ /* If defined special ras_error_inject(e.g: xgmi), implement special ras_error_inject */
1096+ if (block_obj->hw_ops->ras_error_inject)
1097+ ret = block_obj->hw_ops->ras_error_inject(adev, &block_info);
1098+ else /*If not defined .ras_error_inject, use default ras_error_inject*/
1099+ ret = psp_ras_trigger_error(&adev->psp, &block_info);
11531100 }
11541101
11551102 if (ret)
@@ -1329,18 +1276,17 @@ static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev) · 173 unmodified lines
13291276 }
13301277
13311278 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
1332− struct ras_fs_if *head)
1279+ struct ras_common_if *head)
13331280 {
1334− struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1281+ struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
13351282
13361283 if (!obj || obj->attr_inuse)
13371284 return -EINVAL;
13381285
13391286 get_obj(obj);
13401287
1341− memcpy(obj->fs_data.sysfs_name,
1342− head->sysfs_name,
1343− sizeof(obj->fs_data.sysfs_name));
1288+ snprintf(obj->fs_data.sysfs_name, sizeof(obj->fs_data.sysfs_name),
1289+ "%s_err_count", head->name);
13441290
13451291 obj->sysfs_attr = (struct device_attribute){
13461292 .attr = {
@@ -1647,9 +1593,9 @@ int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev, · 300 unmodified lines
16471593 }
16481594
16491595 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
1650− struct ras_ih_if *info)
1596+ struct ras_common_if *head)
16511597 {
1652− struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1598+ struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
16531599 struct ras_ih_data *data;
16541600
16551601 if (!obj)
@@ -1669,24 +1615,27 @@ int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev, · 13 unmodified lines
16691615 }
16701616
16711617 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
1672− struct ras_ih_if *info)
1618+ struct ras_common_if *head)
16731619 {
1674− struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1620+ struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
16751621 struct ras_ih_data *data;
1622+ struct amdgpu_ras_block_object *ras_obj;
16761623
16771624 if (!obj) {
16781625 /* in case we registe the IH before enable ras feature */
1679− obj = amdgpu_ras_create_obj(adev, &info->head);
1626+ obj = amdgpu_ras_create_obj(adev, head);
16801627 if (!obj)
16811628 return -EINVAL;
16821629 } else
16831630 get_obj(obj);
16841631
1632+ ras_obj = container_of(head, struct amdgpu_ras_block_object, ras_comm);
1633+
16851634 data = &obj->ih_data;
16861635 /* add the callback.etc */
16871636 *data = (struct ras_ih_data) {
16881637 .inuse = 0,
1689− .cb = info->cb,
1638+ .cb = ras_obj->ras_cb,
16901639 .element_size = sizeof(struct amdgpu_iv_entry),
16911640 .rptr = 0,
16921641 .wptr = 0,
@@ -1715,10 +1664,7 @@ static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev) · 22 unmodified lines
17151664 struct ras_manager *obj, *tmp;
17161665
17171666 list_for_each_entry_safe(obj, tmp, &con->head, node) {
1718− struct ras_ih_if info = {
1719− .head = obj->head,
1720− };
1721− amdgpu_ras_interrupt_remove_handler(adev, &info);
1667+ amdgpu_ras_interrupt_remove_handler(adev, &obj->head);
17221668 }
17231669
17241670 return 0;
@@ -1766,24 +1712,28 @@ static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev) · 41 unmodified lines
17661712 static void amdgpu_ras_error_status_query(struct amdgpu_device *adev,
17671713 struct ras_query_if *info)
17681714 {
1715+ struct amdgpu_ras_block_object *block_obj;
17691716 /*
17701717 * Only two block need to query read/write
17711718 * RspStatus at current state
17721719 */
1773− switch (info->head.block) {
1774− case AMDGPU_RAS_BLOCK__GFX:
1775− if (adev->gfx.ras_funcs &&
1776− adev->gfx.ras_funcs->query_ras_error_status)
1777− adev->gfx.ras_funcs->query_ras_error_status(adev);
1778− break;
1779− case AMDGPU_RAS_BLOCK__MMHUB:
1780− if (adev->mmhub.ras_funcs &&
1781− adev->mmhub.ras_funcs->query_ras_error_status)
1782− adev->mmhub.ras_funcs->query_ras_error_status(adev);
1783− break;
1784− default:
1785− break;
1720+ if ((info->head.block != AMDGPU_RAS_BLOCK__GFX) &&
1721+ (info->head.block != AMDGPU_RAS_BLOCK__MMHUB))
1722+ return;
1723+
1724+ block_obj = amdgpu_ras_get_ras_block(adev,
1725+ info->head.block,
1726+ info->head.sub_block_index);
1727+
1728+ if (!block_obj || !block_obj->hw_ops) {
1729+ dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1730+ get_ras_block_str(&info->head));
1731+ return;
17861732 }
1733+
1734+ if (block_obj->hw_ops->query_ras_error_status)
1735+ block_obj->hw_ops->query_ras_error_status(adev);
1736+
17871737 }
17881738
17891739 static void amdgpu_ras_query_err_status(struct amdgpu_device *adev)
@@ -2141,8 +2091,7 @@ int amdgpu_ras_recovery_init(struct amdgpu_device *adev) · 351 unmodified lines
21412091 if (ret)
21422092 goto free;
21432093
2144− if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->send_hbm_bad_pages_num)
2145− adev->smu.ppt_funcs->send_hbm_bad_pages_num(&adev->smu, con->eeprom_control.ras_num_recs);
2094+ amdgpu_dpm_send_hbm_bad_pages_num(adev, con->eeprom_control.ras_num_recs);
21462095 }
21472096
21482097 #ifdef CONFIG_X86_MCE_AMD
@@ -2348,24 +2297,27 @@ int amdgpu_ras_init(struct amdgpu_device *adev) · 199 unmodified lines
23482297 case CHIP_VEGA20:
23492298 case CHIP_ARCTURUS:
23502299 case CHIP_ALDEBARAN:
2351− if (!adev->gmc.xgmi.connected_to_cpu)
2352− adev->nbio.ras_funcs = &nbio_v7_4_ras_funcs;
2300+ if (!adev->gmc.xgmi.connected_to_cpu) {
2301+ adev->nbio.ras = &nbio_v7_4_ras;
2302+ amdgpu_ras_register_ras_block(adev, &adev->nbio.ras->ras_block);
2303+ adev->nbio.ras_if = &adev->nbio.ras->ras_block.ras_comm;
2304+ }
23532305 break;
23542306 default:
23552307 /* nbio ras is not available */
23562308 break;
23572309 }
23582310
2359− if (adev->nbio.ras_funcs &&
2360− adev->nbio.ras_funcs->init_ras_controller_interrupt) {
2361− r = adev->nbio.ras_funcs->init_ras_controller_interrupt(adev);
2311+ if (adev->nbio.ras &&
2312+ adev->nbio.ras->init_ras_controller_interrupt) {
2313+ r = adev->nbio.ras->init_ras_controller_interrupt(adev);
23622314 if (r)
23632315 goto release_con;
23642316 }
23652317
2366− if (adev->nbio.ras_funcs &&
2367− adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt) {
2368− r = adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt(adev);
2318+ if (adev->nbio.ras &&
2319+ adev->nbio.ras->init_ras_err_event_athub_interrupt) {
2320+ r = adev->nbio.ras->init_ras_err_event_athub_interrupt(adev);
23692321 if (r)
23702322 goto release_con;
23712323 }
@@ -2377,12 +2329,12 @@ int amdgpu_ras_init(struct amdgpu_device *adev) · 5 unmodified lines
23772329 }
23782330 else if (adev->df.funcs &&
23792331 adev->df.funcs->query_ras_poison_mode &&
2380− adev->umc.ras_funcs &&
2381− adev->umc.ras_funcs->query_ras_poison_mode) {
2332+ adev->umc.ras &&
2333+ adev->umc.ras->query_ras_poison_mode) {
23822334 df_poison =
23832335 adev->df.funcs->query_ras_poison_mode(adev);
23842336 umc_poison =
2385− adev->umc.ras_funcs->query_ras_poison_mode(adev);
2337+ adev->umc.ras->query_ras_poison_mode(adev);
23862338 /* Only poison is set in both DF and UMC, we can support it */
23872339 if (df_poison && umc_poison)
23882340 con->poison_supported = true;
@@ -2445,11 +2397,10 @@ bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev) · 56 unmodified lines
24452397 }
24462398
24472399 /* helper function to handle common stuff in ip late init phase */
2448−int amdgpu_ras_late_init(struct amdgpu_device *adev,
2449− struct ras_common_if *ras_block,
2450− struct ras_fs_if *fs_info,
2451− struct ras_ih_if *ih_info)
2400+int amdgpu_ras_block_late_init(struct amdgpu_device *adev,
2401+ struct ras_common_if *ras_block)
24522402 {
2403+ struct amdgpu_ras_block_object *ras_obj;
24532404 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
24542405 unsigned long ue_count, ce_count;
24552406 int r;
@@ -2477,15 +2428,16 @@ int amdgpu_ras_late_init(struct amdgpu_device *adev, · 21 unmodified lines
24772428 if (adev->in_suspend || amdgpu_in_reset(adev))
24782429 return 0;
24792430
2480− if (ih_info->cb) {
2481− r = amdgpu_ras_interrupt_add_handler(adev, ih_info);
2431+ ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm);
2432+ if (ras_obj->ras_cb) {
2433+ r = amdgpu_ras_interrupt_add_handler(adev, ras_block);
24822434 if (r)
2483− goto interrupt;
2435+ goto cleanup;
24842436 }
24852437
2486− r = amdgpu_ras_sysfs_create(adev, fs_info);
2438+ r = amdgpu_ras_sysfs_create(adev, ras_block);
24872439 if (r)
2488− goto sysfs;
2440+ goto interrupt;
24892441
24902442 /* Those are the cached values at init.
24912443 */
@@ -2495,27 +2447,34 @@ int amdgpu_ras_late_init(struct amdgpu_device *adev, · 3 unmodified lines
24952447 }
24962448
24972449 return 0;
2498−cleanup:
2499− amdgpu_ras_sysfs_remove(adev, ras_block);
2500−sysfs:
2501− if (ih_info->cb)
2502− amdgpu_ras_interrupt_remove_handler(adev, ih_info);
2450+
25032451 interrupt:
2452+ if (ras_obj->ras_cb)
2453+ amdgpu_ras_interrupt_remove_handler(adev, ras_block);
2454+cleanup:
25042455 amdgpu_ras_feature_enable(adev, ras_block, 0);
25052456 return r;
25062457 }
25072458
2459+int amdgpu_ras_block_late_init_default(struct amdgpu_device *adev,
2460+ struct ras_common_if *ras_block)
2461+{
2462+ return amdgpu_ras_block_late_init(adev, ras_block);
2463+}
2464+
25082465 /* helper function to remove ras fs node and interrupt handler */
2509−void amdgpu_ras_late_fini(struct amdgpu_device *adev,
2510− struct ras_common_if *ras_block,
2511− struct ras_ih_if *ih_info)
2466+void amdgpu_ras_block_late_fini(struct amdgpu_device *adev,
2467+ struct ras_common_if *ras_block)
25122468 {
2513− if (!ras_block || !ih_info)
2469+ struct amdgpu_ras_block_object *ras_obj;
2470+ if (!ras_block)
25142471 return;
25152472
25162473 amdgpu_ras_sysfs_remove(adev, ras_block);
2517− if (ih_info->cb)
2518− amdgpu_ras_interrupt_remove_handler(adev, ih_info);
2474+
2475+ ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm);
2476+ if (ras_obj->ras_cb)
2477+ amdgpu_ras_interrupt_remove_handler(adev, ras_block);
25192478 }
25202479
25212480 /* do some init work after IP late init as dependence.
@@ -2568,6 +2527,33 @@ void amdgpu_ras_suspend(struct amdgpu_device *adev) · 46 unmodified lines
25682527 amdgpu_ras_disable_all_features(adev, 1);
25692528 }
25702529
2530+int amdgpu_ras_late_init(struct amdgpu_device *adev)
2531+{
2532+ struct amdgpu_ras_block_list *node, *tmp;
2533+ struct amdgpu_ras_block_object *obj;
2534+ int r;
2535+
2536+ list_for_each_entry_safe(node, tmp, &adev->ras_list, node) {
2537+ if (!node->ras_obj) {
2538+ dev_warn(adev->dev, "Warning: abnormal ras list node.\n");
2539+ continue;
2540+ }
2541+
2542+ obj = node->ras_obj;
2543+ if (obj->ras_late_init) {
2544+ r = obj->ras_late_init(adev, &obj->ras_comm);
2545+ if (r) {
2546+ dev_err(adev->dev, "%s failed to execute ras_late_init! ret:%d\n",
2547+ obj->ras_comm.name, r);
2548+ return r;
2549+ }
2550+ } else
2551+ amdgpu_ras_block_late_init_default(adev, &obj->ras_comm);
2552+ }
2553+
2554+ return 0;
2555+}
2556+
25712557 /* do some fini work before IP fini as dependence */
25722558 int amdgpu_ras_pre_fini(struct amdgpu_device *adev)
25732559 {
@@ -2585,6 +2571,7 @@ int amdgpu_ras_pre_fini(struct amdgpu_device *adev) · 11 unmodified lines
25852571
25862572 int amdgpu_ras_fini(struct amdgpu_device *adev)
25872573 {
2574+ struct amdgpu_ras_block_list *ras_node, *tmp;
25882575 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
25892576
25902577 if (!adev->ras_enabled || !con)
@@ -2603,6 +2590,12 @@ int amdgpu_ras_fini(struct amdgpu_device *adev) · 12 unmodified lines
26032590 amdgpu_ras_set_context(adev, NULL);
26042591 kfree(con);
26052592
2593+ /* Clear ras blocks from ras_list and free ras block list node */
2594+ list_for_each_entry_safe(ras_node, tmp, &adev->ras_list, node) {
2595+ list_del(&ras_node->node);
2596+ kfree(ras_node);
2597+ }
2598+
26062599 return 0;
26072600 }
26082601
@@ -2717,8 +2710,6 @@ static int amdgpu_bad_page_notifier(struct notifier_block *nb, · 108 unmodified lines
27172710 dev_info(adev->dev, "Uncorrectable error detected in UMC inst: %d, chan_idx: %d",
27182711 umc_inst, ch_inst);
27192712
2720− memset(&err_rec, 0x0, sizeof(struct eeprom_table_record));
2721−
27222713 /*
27232714 * Translate UMC channel address to Physical address
27242715 */
@@ -2730,16 +2721,10 @@ static int amdgpu_bad_page_notifier(struct notifier_block *nb, · 5 unmodified lines
27302721 ADDR_OF_256B_BLOCK(channel_index) |
27312722 OFFSET_IN_256B_BLOCK(m->addr);
27322723
2733− err_rec.address = m->addr;
2734− err_rec.retired_page = retired_page >> AMDGPU_GPU_PAGE_SHIFT;
2735− err_rec.ts = (uint64_t)ktime_get_real_seconds();
2736− err_rec.err_type = AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE;
2737− err_rec.cu = 0;
2738− err_rec.mem_channel = channel_index;
2739− err_rec.mcumc_id = umc_inst;
2740−
2724+ memset(&err_rec, 0x0, sizeof(struct eeprom_table_record));
27412725 err_data.err_addr = &err_rec;
2742− err_data.err_addr_cnt = 1;
2726+ amdgpu_umc_fill_error_record(&err_data, m->addr,
2727+ retired_page, channel_index, umc_inst);
27432728
27442729 if (amdgpu_bad_page_threshold != 0) {
27452730 amdgpu_ras_add_bad_pages(adev, err_data.err_addr,
@@ -2777,3 +2762,63 @@ static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev) · 31 unmodified lines
27772762 }
27782763 }
27792764 #endif
2765+
2766+struct amdgpu_ras *amdgpu_ras_get_context(struct amdgpu_device *adev)
2767+{
2768+ if (!adev)
2769+ return NULL;
2770+
2771+ return adev->psp.ras_context.ras;
2772+}
2773+
2774+int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con)
2775+{
2776+ if (!adev)
2777+ return -EINVAL;
2778+
2779+ adev->psp.ras_context.ras = ras_con;
2780+ return 0;
2781+}
2782+
2783+/* check if ras is supported on block, say, sdma, gfx */
2784+int amdgpu_ras_is_supported(struct amdgpu_device *adev,
2785+ unsigned int block)
2786+{
2787+ struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
2788+
2789+ if (block >= AMDGPU_RAS_BLOCK_COUNT)
2790+ return 0;
2791+ return ras && (adev->ras_enabled & (1 << block));
2792+}
2793+
2794+int amdgpu_ras_reset_gpu(struct amdgpu_device *adev)
2795+{
2796+ struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
2797+
2798+ if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0)
2799+ schedule_work(&ras->recovery_work);
2800+ return 0;
2801+}
2802+
2803+
2804+/* Register each ip ras block into amdgpu ras */
2805+int amdgpu_ras_register_ras_block(struct amdgpu_device *adev,
2806+ struct amdgpu_ras_block_object *ras_block_obj)
2807+{
2808+ struct amdgpu_ras_block_list *ras_node;
2809+ if (!adev || !ras_block_obj)
2810+ return -EINVAL;
2811+
2812+ if (!amdgpu_ras_asic_supported(adev))
2813+ return 0;
2814+
2815+ ras_node = kzalloc(sizeof(*ras_node), GFP_KERNEL);
2816+ if (!ras_node)
2817+ return -ENOMEM;
2818+
2819+ INIT_LIST_HEAD(&ras_node->node);
2820+ ras_node->ras_obj = ras_block_obj;
2821+ list_add_tail(&ras_node->node, &adev->ras_list);
2822+
2823+ return 0;
2824+}
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h+43−34
@@ -26,11 +26,11 @@ · 25 unmodified lines
2626
2727 #include <linux/debugfs.h>
2828 #include <linux/list.h>
29−#include "amdgpu.h"
30−#include "amdgpu_psp.h"
3129 #include "ta_ras_if.h"
3230 #include "amdgpu_ras_eeprom.h"
3331
32+struct amdgpu_iv_entry;
33+
3434 #define AMDGPU_RAS_FLAG_INIT_BY_VBIOS (0x1 << 0)
3535
3636 enum amdgpu_ras_block {
@@ -484,6 +484,27 @@ struct ras_debug_if { · 447 unmodified lines
484484 };
485485 int op;
486486 };
487+
488+struct amdgpu_ras_block_object {
489+ struct ras_common_if ras_comm;
490+
491+ int (*ras_block_match)(struct amdgpu_ras_block_object *block_obj,
492+ enum amdgpu_ras_block block, uint32_t sub_block_index);
493+ int (*ras_late_init)(struct amdgpu_device *adev, struct ras_common_if *ras_block);
494+ void (*ras_fini)(struct amdgpu_device *adev);
495+ ras_ih_cb ras_cb;
496+ const struct amdgpu_ras_block_hw_ops *hw_ops;
497+};
498+
499+struct amdgpu_ras_block_hw_ops {
500+ int (*ras_error_inject)(struct amdgpu_device *adev, void *inject_if);
501+ void (*query_ras_error_count)(struct amdgpu_device *adev, void *ras_error_status);
502+ void (*query_ras_error_status)(struct amdgpu_device *adev);
503+ void (*query_ras_error_address)(struct amdgpu_device *adev, void *ras_error_status);
504+ void (*reset_ras_error_count)(struct amdgpu_device *adev);
505+ void (*reset_ras_error_status)(struct amdgpu_device *adev);
506+};
507+
487508 /* work flow
488509 * vbios
489510 * 1: ras feature enable (enabled by default)
@@ -498,19 +519,6 @@ struct ras_debug_if { · 8 unmodified lines
498519 * 8: feature disable
499520 */
500521
501−#define amdgpu_ras_get_context(adev) ((adev)->psp.ras_context.ras)
502−#define amdgpu_ras_set_context(adev, ras_con) ((adev)->psp.ras_context.ras = (ras_con))
503−
504−/* check if ras is supported on block, say, sdma, gfx */
505−static inline int amdgpu_ras_is_supported(struct amdgpu_device *adev,
506− unsigned int block)
507−{
508− struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
509−
510− if (block >= AMDGPU_RAS_BLOCK_COUNT)
511− return 0;
512− return ras && (adev->ras_enabled & (1 << block));
513−}
514522
515523 int amdgpu_ras_recovery_init(struct amdgpu_device *adev);
516524
@@ -527,15 +535,6 @@ int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev, · 10 unmodified lines
527535
528536 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev);
529537
530−static inline int amdgpu_ras_reset_gpu(struct amdgpu_device *adev)
531−{
532− struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
533−
534− if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0)
535− schedule_work(&ras->recovery_work);
536− return 0;
537−}
538−
539538 static inline enum ta_ras_block
540539 amdgpu_ras_block_to_ta(enum amdgpu_ras_block block) {
541540 switch (block) {
@@ -596,15 +595,15 @@ amdgpu_ras_error_to_ta(enum amdgpu_ras_error_type error) { · 54 unmodified lines
596595
597596 /* called in ip_init and ip_fini */
598597 int amdgpu_ras_init(struct amdgpu_device *adev);
598+int amdgpu_ras_late_init(struct amdgpu_device *adev);
599599 int amdgpu_ras_fini(struct amdgpu_device *adev);
600600 int amdgpu_ras_pre_fini(struct amdgpu_device *adev);
601−int amdgpu_ras_late_init(struct amdgpu_device *adev,
602− struct ras_common_if *ras_block,
603− struct ras_fs_if *fs_info,
604− struct ras_ih_if *ih_info);
605−void amdgpu_ras_late_fini(struct amdgpu_device *adev,
606− struct ras_common_if *ras_block,
607− struct ras_ih_if *ih_info);
601+
602+int amdgpu_ras_block_late_init(struct amdgpu_device *adev,
603+ struct ras_common_if *ras_block);
604+
605+void amdgpu_ras_block_late_fini(struct amdgpu_device *adev,
606+ struct ras_common_if *ras_block);
608607
609608 int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
610609 struct ras_common_if *head, bool enable);
@@ -613,7 +612,7 @@ int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev, · 2 unmodified lines
613612 struct ras_common_if *head, bool enable);
614613
615614 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
616− struct ras_fs_if *head);
615+ struct ras_common_if *head);
617616
618617 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
619618 struct ras_common_if *head);
@@ -630,10 +629,10 @@ int amdgpu_ras_error_inject(struct amdgpu_device *adev, · 10 unmodified lines
630629 struct ras_inject_if *info);
631630
632631 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
633− struct ras_ih_if *info);
632+ struct ras_common_if *head);
634633
635634 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
636− struct ras_ih_if *info);
635+ struct ras_common_if *head);
637636
638637 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
639638 struct ras_dispatch_if *info);
@@ -667,4 +666,14 @@ const char *get_ras_block_str(struct ras_common_if *ras_block); · 27 unmodified lines
667666
668667 bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev);
669668
669+int amdgpu_ras_is_supported(struct amdgpu_device *adev, unsigned int block);
670+
671+int amdgpu_ras_reset_gpu(struct amdgpu_device *adev);
672+
673+struct amdgpu_ras* amdgpu_ras_get_context(struct amdgpu_device *adev);
674+
675+int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con);
676+
677+int amdgpu_ras_register_ras_block(struct amdgpu_device *adev,
678+ struct amdgpu_ras_block_object *ras_block_obj);
670679 #endif
drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c+20−15
@@ -31,6 +31,8 @@ · 30 unmodified lines
3131 #include <linux/debugfs.h>
3232 #include <linux/uaccess.h>
3333
34+#include "amdgpu_reset.h"
35+
3436 #define EEPROM_I2C_MADDR_VEGA20 0x0
3537 #define EEPROM_I2C_MADDR_ARCTURUS 0x40000
3638 #define EEPROM_I2C_MADDR_ARCTURUS_D342 0x0
@@ -193,12 +195,12 @@ static int __write_table_header(struct amdgpu_ras_eeprom_control *control) · 156 unmodified lines
193195 __encode_table_header_to_buf(&control->tbl_hdr, buf);
194196
195197 /* i2c may be unstable in gpu reset */
196− down_read(&adev->reset_sem);
197− res = amdgpu_eeprom_write(&adev->pm.smu_i2c,
198+ down_read(&adev->reset_domain->sem);
199+ res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus,
198200 control->i2c_address +
199201 control->ras_header_offset,
200202 buf, RAS_TABLE_HEADER_SIZE);
201− up_read(&adev->reset_sem);
203+ up_read(&adev->reset_domain->sem);
202204
203205 if (res < 0) {
204206 DRM_ERROR("Failed to write EEPROM table header:%d", res);
@@ -263,6 +265,7 @@ static int amdgpu_ras_eeprom_correct_header_tag( · 58 unmodified lines
263265 */
264266 int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control)
265267 {
268+ struct amdgpu_device *adev = to_amdgpu_device(control);
266269 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
267270 u8 csum;
268271 int res;
@@ -282,6 +285,8 @@ int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control) · 13 unmodified lines
282285 control->ras_num_recs = 0;
283286 control->ras_fri = 0;
284287
288+ amdgpu_dpm_send_hbm_bad_pages_num(adev, control->ras_num_recs);
289+
285290 amdgpu_ras_debugfs_set_ret_size(control);
286291
287292 mutex_unlock(&control->ras_tbl_mutex);
@@ -387,13 +392,13 @@ static int __amdgpu_ras_eeprom_write(struct amdgpu_ras_eeprom_control *control, · 99 unmodified lines
387392 int res;
388393
389394 /* i2c may be unstable in gpu reset */
390− down_read(&adev->reset_sem);
395+ down_read(&adev->reset_domain->sem);
391396 buf_size = num * RAS_TABLE_RECORD_SIZE;
392− res = amdgpu_eeprom_write(&adev->pm.smu_i2c,
397+ res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus,
393398 control->i2c_address +
394399 RAS_INDEX_TO_OFFSET(control, fri),
395400 buf, buf_size);
396− up_read(&adev->reset_sem);
401+ up_read(&adev->reset_domain->sem);
397402 if (res < 0) {
398403 DRM_ERROR("Writing %d EEPROM table records error:%d",
399404 num, res);
@@ -547,12 +552,12 @@ amdgpu_ras_eeprom_update_header(struct amdgpu_ras_eeprom_control *control) · 147 unmodified lines
547552 goto Out;
548553 }
549554
550− down_read(&adev->reset_sem);
551− res = amdgpu_eeprom_read(&adev->pm.smu_i2c,
555+ down_read(&adev->reset_domain->sem);
556+ res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus,
552557 control->i2c_address +
553558 control->ras_record_offset,
554559 buf, buf_size);
555− up_read(&adev->reset_sem);
560+ up_read(&adev->reset_domain->sem);
556561 if (res < 0) {
557562 DRM_ERROR("EEPROM failed reading records:%d\n",
558563 res);
@@ -642,13 +647,13 @@ static int __amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control, · 83 unmodified lines
642647 int res;
643648
644649 /* i2c may be unstable in gpu reset */
645− down_read(&adev->reset_sem);
650+ down_read(&adev->reset_domain->sem);
646651 buf_size = num * RAS_TABLE_RECORD_SIZE;
647− res = amdgpu_eeprom_read(&adev->pm.smu_i2c,
652+ res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus,
648653 control->i2c_address +
649654 RAS_INDEX_TO_OFFSET(control, fri),
650655 buf, buf_size);
651− up_read(&adev->reset_sem);
656+ up_read(&adev->reset_domain->sem);
652657 if (res < 0) {
653658 DRM_ERROR("Reading %d EEPROM table records error:%d",
654659 num, res);
@@ -1009,7 +1014,7 @@ static int __verify_ras_table_checksum(struct amdgpu_ras_eeprom_control *control · 354 unmodified lines
10091014 return -ENOMEM;
10101015 }
10111016
1012− res = amdgpu_eeprom_read(&adev->pm.smu_i2c,
1017+ res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus,
10131018 control->i2c_address +
10141019 control->ras_header_offset,
10151020 buf, buf_size);
@@ -1045,7 +1050,7 @@ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control, · 29 unmodified lines
10451050 return 0;
10461051
10471052 /* Verify i2c adapter is initialized */
1048− if (!adev->pm.smu_i2c.algo)
1053+ if (!adev->pm.ras_eeprom_i2c_bus || !adev->pm.ras_eeprom_i2c_bus->algo)
10491054 return -ENOENT;
10501055
10511056 if (!__get_eeprom_i2c_addr(adev, control))
@@ -1057,7 +1062,7 @@ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control, · 5 unmodified lines
10571062 mutex_init(&control->ras_tbl_mutex);
10581063
10591064 /* Read the table header from EEPROM address */
1060− res = amdgpu_eeprom_read(&adev->pm.smu_i2c,
1065+ res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus,
10611066 control->i2c_address + control->ras_header_offset,
10621067 buf, RAS_TABLE_HEADER_SIZE);
10631068 if (res < RAS_TABLE_HEADER_SIZE) {
drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c+56−0
@@ -96,3 +96,59 @@ int amdgpu_reset_perform_reset(struct amdgpu_device *adev, · 95 unmodified lines
9696 return reset_handler->restore_hwcontext(adev->reset_cntl,
9797 reset_context);
9898 }
99+
100+
101+void amdgpu_reset_destroy_reset_domain(struct kref *ref)
102+{
103+ struct amdgpu_reset_domain *reset_domain = container_of(ref,
104+ struct amdgpu_reset_domain,
105+ refcount);
106+ if (reset_domain->wq)
107+ destroy_workqueue(reset_domain->wq);
108+
109+ kvfree(reset_domain);
110+}
111+
112+struct amdgpu_reset_domain *amdgpu_reset_create_reset_domain(enum amdgpu_reset_domain_type type,
113+ char *wq_name)
114+{
115+ struct amdgpu_reset_domain *reset_domain;
116+
117+ reset_domain = kvzalloc(sizeof(struct amdgpu_reset_domain), GFP_KERNEL);
118+ if (!reset_domain) {
119+ DRM_ERROR("Failed to allocate amdgpu_reset_domain!");
120+ return NULL;
121+ }
122+
123+ reset_domain->type = type;
124+ kref_init(&reset_domain->refcount);
125+
126+ reset_domain->wq = create_singlethread_workqueue(wq_name);
127+ if (!reset_domain->wq) {
128+ DRM_ERROR("Failed to allocate wq for amdgpu_reset_domain!");
129+ amdgpu_reset_put_reset_domain(reset_domain);
130+ return NULL;
131+
132+ }
133+
134+ atomic_set(&reset_domain->in_gpu_reset, 0);
135+ init_rwsem(&reset_domain->sem);
136+
137+ return reset_domain;
138+}
139+
140+void amdgpu_device_lock_reset_domain(struct amdgpu_reset_domain *reset_domain)
141+{
142+ atomic_set(&reset_domain->in_gpu_reset, 1);
143+ down_write(&reset_domain->sem);
144+}
145+
146+
147+void amdgpu_device_unlock_reset_domain(struct amdgpu_reset_domain *reset_domain)
148+{
149+ atomic_set(&reset_domain->in_gpu_reset, 0);
150+ up_write(&reset_domain->sem);
151+}
152+
153+
154+
drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h+40−0
@@ -70,6 +70,21 @@ struct amdgpu_reset_control { · 69 unmodified lines
7070 void (*async_reset)(struct work_struct *work);
7171 };
7272
73+
74+enum amdgpu_reset_domain_type {
75+ SINGLE_DEVICE,
76+ XGMI_HIVE
77+};
78+
79+struct amdgpu_reset_domain {
80+ struct kref refcount;
81+ struct workqueue_struct *wq;
82+ enum amdgpu_reset_domain_type type;
83+ struct rw_semaphore sem;
84+ atomic_t in_gpu_reset;
85+};
86+
87+
7388 int amdgpu_reset_init(struct amdgpu_device *adev);
7489 int amdgpu_reset_fini(struct amdgpu_device *adev);
7590
@@ -82,4 +97,29 @@ int amdgpu_reset_perform_reset(struct amdgpu_device *adev, · 6 unmodified lines
8297 int amdgpu_reset_add_handler(struct amdgpu_reset_control *reset_ctl,
8398 struct amdgpu_reset_handler *handler);
8499
100+struct amdgpu_reset_domain *amdgpu_reset_create_reset_domain(enum amdgpu_reset_domain_type type,
101+ char *wq_name);
102+
103+void amdgpu_reset_destroy_reset_domain(struct kref *ref);
104+
105+static inline bool amdgpu_reset_get_reset_domain(struct amdgpu_reset_domain *domain)
106+{
107+ return kref_get_unless_zero(&domain->refcount) != 0;
108+}
109+
110+static inline void amdgpu_reset_put_reset_domain(struct amdgpu_reset_domain *domain)
111+{
112+ kref_put(&domain->refcount, amdgpu_reset_destroy_reset_domain);
113+}
114+
115+static inline bool amdgpu_reset_domain_schedule(struct amdgpu_reset_domain *domain,
116+ struct work_struct *work)
117+{
118+ return queue_work(domain->wq, work);
119+}
120+
121+void amdgpu_device_lock_reset_domain(struct amdgpu_reset_domain *reset_domain);
122+
123+void amdgpu_device_unlock_reset_domain(struct amdgpu_reset_domain *reset_domain);
124+
85125 #endif
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c+3−2
@@ -191,8 +191,9 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, · 190 unmodified lines
191191 ring->adev = adev;
192192 ring->idx = adev->num_rings++;
193193 adev->rings[ring->idx] = ring;
194− r = amdgpu_fence_driver_init_ring(ring, sched_hw_submission,
195− sched_score);
194+ ring->num_hw_submission = sched_hw_submission;
195+ ring->sched_score = sched_score;
196+ r = amdgpu_fence_driver_init_ring(ring);
196197 if (r)
197198 return r;
198199 }
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h+3−3
@@ -114,9 +114,7 @@ struct amdgpu_fence_driver { · 113 unmodified lines
114114 void amdgpu_fence_driver_clear_job_fences(struct amdgpu_ring *ring);
115115 void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring);
116116
117−int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
118− unsigned num_hw_submission,
119− atomic_t *sched_score);
117+int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
120118 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
121119 struct amdgpu_irq_src *irq_src,
122120 unsigned irq_type);
@@ -251,6 +249,8 @@ struct amdgpu_ring { · 128 unmodified lines
251249 bool has_compute_vm_bug;
252250 bool no_scheduler;
253251 int hw_prio;
252+ unsigned num_hw_submission;
253+ atomic_t *sched_score;
254254 };
255255
256256 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h+14−2
@@ -127,11 +127,19 @@ struct amdgpu_rlc_funcs { · 126 unmodified lines
127127 void (*reset)(struct amdgpu_device *adev);
128128 void (*start)(struct amdgpu_device *adev);
129129 void (*update_spm_vmid)(struct amdgpu_device *adev, unsigned vmid);
130− void (*sriov_wreg)(struct amdgpu_device *adev, u32 offset, u32 v, u32 acc_flags, u32 hwip);
131− u32 (*sriov_rreg)(struct amdgpu_device *adev, u32 offset, u32 acc_flags, u32 hwip);
132130 bool (*is_rlcg_access_range)(struct amdgpu_device *adev, uint32_t reg);
133131 };
134132
133+struct amdgpu_rlcg_reg_access_ctrl {
134+ uint32_t scratch_reg0;
135+ uint32_t scratch_reg1;
136+ uint32_t scratch_reg2;
137+ uint32_t scratch_reg3;
138+ uint32_t grbm_cntl;
139+ uint32_t grbm_idx;
140+ uint32_t spare_int;
141+};
142+
135143 struct amdgpu_rlc {
136144 /* for power gating */
137145 struct amdgpu_bo *save_restore_obj;
@@ -191,6 +199,10 @@ struct amdgpu_rlc { · 53 unmodified lines
191199 struct amdgpu_bo *rlc_toc_bo;
192200 uint64_t rlc_toc_gpu_addr;
193201 void *rlc_toc_buf;
202+
203+ bool rlcg_reg_access_supported;
204+ /* registers for rlcg indirect reg access */
205+ struct amdgpu_rlcg_reg_access_ctrl reg_access_ctrl;
194206 };
195207
196208 void amdgpu_gfx_rlc_enter_safe_mode(struct amdgpu_device *adev);
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c+7−43
@@ -87,71 +87,35 @@ uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring, · 86 unmodified lines
8787 }
8888
8989 int amdgpu_sdma_ras_late_init(struct amdgpu_device *adev,
90− void *ras_ih_info)
90+ struct ras_common_if *ras_block)
9191 {
9292 int r, i;
93− struct ras_ih_if *ih_info = (struct ras_ih_if *)ras_ih_info;
94− struct ras_fs_if fs_info = {
95− .sysfs_name = "sdma_err_count",
96− };
97−
98− if (!ih_info)
99− return -EINVAL;
10093
101− if (!adev->sdma.ras_if) {
102− adev->sdma.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
103− if (!adev->sdma.ras_if)
104− return -ENOMEM;
105− adev->sdma.ras_if->block = AMDGPU_RAS_BLOCK__SDMA;
106− adev->sdma.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
107− adev->sdma.ras_if->sub_block_index = 0;
108− }
109− fs_info.head = ih_info->head = *adev->sdma.ras_if;
110−
111− r = amdgpu_ras_late_init(adev, adev->sdma.ras_if,
112− &fs_info, ih_info);
94+ r = amdgpu_ras_block_late_init(adev, ras_block);
11395 if (r)
114− goto free;
96+ return r;
11597
116− if (amdgpu_ras_is_supported(adev, adev->sdma.ras_if->block)) {
98+ if (amdgpu_ras_is_supported(adev, ras_block->block)) {
11799 for (i = 0; i < adev->sdma.num_instances; i++) {
118100 r = amdgpu_irq_get(adev, &adev->sdma.ecc_irq,
119101 AMDGPU_SDMA_IRQ_INSTANCE0 + i);
120102 if (r)
121103 goto late_fini;
122104 }
123− } else {
124− r = 0;
125− goto free;
126105 }
127106
128107 return 0;
129108
130109 late_fini:
131− amdgpu_ras_late_fini(adev, adev->sdma.ras_if, ih_info);
132−free:
133− kfree(adev->sdma.ras_if);
134− adev->sdma.ras_if = NULL;
110+ amdgpu_ras_block_late_fini(adev, ras_block);
135111 return r;
136112 }
137113
138114 void amdgpu_sdma_ras_fini(struct amdgpu_device *adev)
139115 {
140116 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA) &&
141− adev->sdma.ras_if) {
142− struct ras_common_if *ras_if = adev->sdma.ras_if;
143− struct ras_ih_if ih_info = {
144− .head = *ras_if,
145− /* the cb member will not be used by
146− * amdgpu_ras_interrupt_remove_handler, init it only
147− * to cheat the check in ras_late_fini
148− */
149− .cb = amdgpu_sdma_process_ras_data_cb,
150− };
151−
152− amdgpu_ras_late_fini(adev, ras_if, &ih_info);
153− kfree(ras_if);
154− }
117+ adev->sdma.ras_if)
118+ amdgpu_ras_block_late_fini(adev, adev->sdma.ras_if);
155119 }
156120
157121 int amdgpu_sdma_process_ras_data_cb(struct amdgpu_device *adev,
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h+5−9
@@ -23,6 +23,7 @@ · 22 unmodified lines
2323
2424 #ifndef __AMDGPU_SDMA_H__
2525 #define __AMDGPU_SDMA_H__
26+#include "amdgpu_ras.h"
2627
2728 /* max number of IP instances */
2829 #define AMDGPU_MAX_SDMA_INSTANCES 8
@@ -50,13 +51,8 @@ struct amdgpu_sdma_instance { · 21 unmodified lines
5051 bool burst_nop;
5152 };
5253
53−struct amdgpu_sdma_ras_funcs {
54− int (*ras_late_init)(struct amdgpu_device *adev,
55− void *ras_ih_info);
56− void (*ras_fini)(struct amdgpu_device *adev);
57− int (*query_ras_error_count)(struct amdgpu_device *adev,
58− uint32_t instance, void *ras_error_status);
59− void (*reset_ras_error_count)(struct amdgpu_device *adev);
54+struct amdgpu_sdma_ras {
55+ struct amdgpu_ras_block_object ras_block;
6056 };
6157
6258 struct amdgpu_sdma {
@@ -73,7 +69,7 @@ struct amdgpu_sdma { · 10 unmodified lines
7369 uint32_t srbm_soft_reset;
7470 bool has_page_queue;
7571 struct ras_common_if *ras_if;
76− const struct amdgpu_sdma_ras_funcs *funcs;
72+ struct amdgpu_sdma_ras *ras;
7773 };
7874
7975 /*
@@ -121,7 +117,7 @@ amdgpu_sdma_get_instance_from_ring(struct amdgpu_ring *ring); · 41 unmodified lines
121117 int amdgpu_sdma_get_index_from_ring(struct amdgpu_ring *ring, uint32_t *index);
122118 uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring, unsigned vmid);
123119 int amdgpu_sdma_ras_late_init(struct amdgpu_device *adev,
124− void *ras_ih_info);
120+ struct ras_common_if *ras_block);
125121 void amdgpu_sdma_ras_fini(struct amdgpu_device *adev);
126122 int amdgpu_sdma_process_ras_data_cb(struct amdgpu_device *adev,
127123 void *err_data,
drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c+2−3
@@ -261,10 +261,9 @@ int amdgpu_sync_resv(struct amdgpu_device *adev, struct amdgpu_sync *sync, · 260 unmodified lines
261261
262262 dma_resv_for_each_fence(&cursor, resv, true, f) {
263263 dma_fence_chain_for_each(f, f) {
264− struct dma_fence_chain *chain = to_dma_fence_chain(f);
264+ struct dma_fence *tmp = dma_fence_chain_contained(f);
265265
266− if (amdgpu_sync_test_fence(adev, mode, owner, chain ?
267− chain->fence : f)) {
266+ if (amdgpu_sync_test_fence(adev, mode, owner, tmp)) {
268267 r = amdgpu_sync_fence(sync, f);
269268 dma_fence_put(f);
270269 if (r)
drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h+2−3
@@ -358,11 +358,10 @@ TRACE_EVENT(amdgpu_vm_update_ptes, · 357 unmodified lines
358358 }
359359 ),
360360 TP_printk("pid:%u vm_ctx:0x%llx start:0x%010llx end:0x%010llx,"
361− " flags:0x%llx, incr:%llu, dst:\n%s%s", __entry->pid,
361+ " flags:0x%llx, incr:%llu, dst:\n%s", __entry->pid,
362362 __entry->vm_ctx, __entry->start, __entry->end,
363363 __entry->flags, __entry->incr, __print_array(
364− __get_dynamic_array(dst), min(__entry->nptes, 32u), 8),
365− __entry->nptes > 32 ? "..." : "")
364+ __get_dynamic_array(dst), __entry->nptes, 8))
366365 );
367366
368367 TRACE_EVENT(amdgpu_vm_set_ptes,
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c+246−165
@@ -50,6 +50,7 @@ · 49 unmodified lines
5050 #include <drm/ttm/ttm_range_manager.h>
5151
5252 #include <drm/amdgpu_drm.h>
53+#include <drm/drm_drv.h>
5354
5455 #include "amdgpu.h"
5556 #include "amdgpu_object.h"
@@ -170,10 +171,10 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo, · 114 unmodified lines
170171 * @bo: buffer object to map
171172 * @mem: memory object to map
172173 * @mm_cur: range to map
173− * @num_pages: number of pages to map
174174 * @window: which GART window to use
175175 * @ring: DMA ring to use for the copy
176176 * @tmz: if we should setup a TMZ enabled mapping
177+ * @size: in number of bytes to map, out number of bytes mapped
177178 * @addr: resulting address inside the MC address space
178179 *
179180 * Setup one of the GART windows to access a specific piece of memory or return
@@ -182,15 +183,14 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo, · 2 unmodified lines
182183 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
183184 struct ttm_resource *mem,
184185 struct amdgpu_res_cursor *mm_cur,
185− unsigned num_pages, unsigned window,
186− struct amdgpu_ring *ring, bool tmz,
187− uint64_t *addr)
186+ unsigned window, struct amdgpu_ring *ring,
187+ bool tmz, uint64_t *size, uint64_t *addr)
188188 {
189189 struct amdgpu_device *adev = ring->adev;
190− struct amdgpu_job *job;
191− unsigned num_dw, num_bytes;
192− struct dma_fence *fence;
190+ unsigned offset, num_pages, num_dw, num_bytes;
193191 uint64_t src_addr, dst_addr;
192+ struct dma_fence *fence;
193+ struct amdgpu_job *job;
194194 void *cpu_addr;
195195 uint64_t flags;
196196 unsigned int i;
@@ -198,7 +198,9 @@ static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo, · 1 unmodified line
198198
199199 BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
200200 AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
201− BUG_ON(mem->mem_type == AMDGPU_PL_PREEMPT);
201+
202+ if (WARN_ON(mem->mem_type == AMDGPU_PL_PREEMPT))
203+ return -EINVAL;
202204
203205 /* Map only what can't be accessed directly */
204206 if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) {
@@ -207,10 +209,22 @@ static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo, · 2 unmodified lines
207209 return 0;
208210 }
209211
212+
213+ /*
214+ * If start begins at an offset inside the page, then adjust the size
215+ * and addr accordingly
216+ */
217+ offset = mm_cur->start & ~PAGE_MASK;
218+
219+ num_pages = PFN_UP(*size + offset);
220+ num_pages = min_t(uint32_t, num_pages, AMDGPU_GTT_MAX_TRANSFER_SIZE);
221+
222+ *size = min(*size, (uint64_t)num_pages * PAGE_SIZE - offset);
223+
210224 *addr = adev->gmc.gart_start;
211225 *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
212226 AMDGPU_GPU_PAGE_SIZE;
213− *addr += mm_cur->start & ~PAGE_MASK;
227+ *addr += offset;
214228
215229 num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
216230 num_bytes = num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE;
@@ -241,10 +255,7 @@ static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo, · 24 unmodified lines
241255 dma_addr_t *dma_addr;
242256
243257 dma_addr = &bo->ttm->dma_address[mm_cur->start >> PAGE_SHIFT];
244− r = amdgpu_gart_map(adev, 0, num_pages, dma_addr, flags,
245− cpu_addr);
246− if (r)
247− goto error_free;
258+ amdgpu_gart_map(adev, 0, num_pages, dma_addr, flags, cpu_addr);
248259 } else {
249260 dma_addr_t dma_address;
250261
@@ -252,11 +263,8 @@ static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo, · 1 unmodified line
252263 dma_address += adev->vm_manager.vram_base_offset;
253264
254265 for (i = 0; i < num_pages; ++i) {
255− r = amdgpu_gart_map(adev, i << PAGE_SHIFT, 1,
256− &dma_address, flags, cpu_addr);
257− if (r)
258− goto error_free;
259−
266+ amdgpu_gart_map(adev, i << PAGE_SHIFT, 1, &dma_address,
267+ flags, cpu_addr);
260268 dma_address += PAGE_SIZE;
261269 }
262270 }
@@ -297,9 +305,6 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, · 34 unmodified lines
297305 struct dma_resv *resv,
298306 struct dma_fence **f)
299307 {
300− const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
301− AMDGPU_GPU_PAGE_SIZE);
302−
303308 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
304309 struct amdgpu_res_cursor src_mm, dst_mm;
305310 struct dma_fence *fence = NULL;
@@ -315,29 +320,20 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, · 9 unmodified lines
315320
316321 mutex_lock(&adev->mman.gtt_window_lock);
317322 while (src_mm.remaining) {
318− uint32_t src_page_offset = src_mm.start & ~PAGE_MASK;
319− uint32_t dst_page_offset = dst_mm.start & ~PAGE_MASK;
323+ uint64_t from, to, cur_size;
320324 struct dma_fence *next;
321− uint32_t cur_size;
322− uint64_t from, to;
323325
324− /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
325− * begins at an offset, then adjust the size accordingly
326− */
327− cur_size = max(src_page_offset, dst_page_offset);
328− cur_size = min(min3(src_mm.size, dst_mm.size, size),
329− (uint64_t)(GTT_MAX_BYTES - cur_size));
326+ /* Never copy more than 256MiB at once to avoid a timeout */
327+ cur_size = min3(src_mm.size, dst_mm.size, 256ULL << 20);
330328
331329 /* Map src to window 0 and dst to window 1. */
332330 r = amdgpu_ttm_map_buffer(src->bo, src->mem, &src_mm,
333− PFN_UP(cur_size + src_page_offset),
334− 0, ring, tmz, &from);
331+ 0, ring, tmz, &cur_size, &from);
335332 if (r)
336333 goto error;
337334
338335 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, &dst_mm,
339− PFN_UP(cur_size + dst_page_offset),
340− 1, ring, tmz, &to);
336+ 1, ring, tmz, &cur_size, &to);
341337 if (r)
342338 goto error;
343339
@@ -396,8 +392,7 @@ static int amdgpu_move_blit(struct ttm_buffer_object *bo, · 52 unmodified lines
396392 (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
397393 struct dma_fence *wipe_fence = NULL;
398394
399− r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON,
400− NULL, &wipe_fence);
395+ r = amdgpu_fill_buffer(abo, AMDGPU_POISON, NULL, &wipe_fence);
401396 if (r) {
402397 goto error;
403398 } else if (wipe_fence) {
@@ -821,14 +816,13 @@ static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device *bdev, · 417 unmodified lines
821816 #endif
822817 }
823818
824−static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
825− struct ttm_buffer_object *tbo,
826− uint64_t flags)
819+static void amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
820+ struct ttm_buffer_object *tbo,
821+ uint64_t flags)
827822 {
828823 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
829824 struct ttm_tt *ttm = tbo->ttm;
830825 struct amdgpu_ttm_tt *gtt = (void *)ttm;
831− int r;
832826
833827 if (amdgpu_bo_encrypted(abo))
834828 flags |= AMDGPU_PTE_TMZ;
@@ -836,10 +830,8 @@ static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev, · 1 unmodified line
836830 if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) {
837831 uint64_t page_idx = 1;
838832
839− r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
840− gtt->ttm.dma_address, flags);
841− if (r)
842− goto gart_bind_fail;
833+ amdgpu_gart_bind(adev, gtt->offset, page_idx,
834+ gtt->ttm.dma_address, flags);
843835
844836 /* The memory type of the first page defaults to UC. Now
845837 * modify the memory type to NC from the second page of
@@ -848,21 +840,13 @@ static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev, · 2 unmodified lines
848840 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
849841 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC);
850842
851− r = amdgpu_gart_bind(adev,
852− gtt->offset + (page_idx << PAGE_SHIFT),
853− ttm->num_pages - page_idx,
854− &(gtt->ttm.dma_address[page_idx]), flags);
843+ amdgpu_gart_bind(adev, gtt->offset + (page_idx << PAGE_SHIFT),
844+ ttm->num_pages - page_idx,
845+ &(gtt->ttm.dma_address[page_idx]), flags);
855846 } else {
856− r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
857− gtt->ttm.dma_address, flags);
847+ amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
848+ gtt->ttm.dma_address, flags);
858849 }
859−
860−gart_bind_fail:
861− if (r)
862− DRM_ERROR("failed to bind %u pages at 0x%08llX\n",
863− ttm->num_pages, gtt->offset);
864−
865− return r;
866850 }
867851
868852 /*
@@ -878,7 +862,7 @@ static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, · 9 unmodified lines
878862 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
879863 struct amdgpu_ttm_tt *gtt = (void*)ttm;
880864 uint64_t flags;
881− int r = 0;
865+ int r;
882866
883867 if (!bo_mem)
884868 return -EINVAL;
@@ -925,14 +909,10 @@ static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, · 40 unmodified lines
925909
926910 /* bind pages into GART page tables */
927911 gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
928− r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
929− gtt->ttm.dma_address, flags);
930−
931− if (r)
932− DRM_ERROR("failed to bind %u pages at 0x%08llX\n",
933− ttm->num_pages, gtt->offset);
912+ amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
913+ gtt->ttm.dma_address, flags);
934914 gtt->bound = true;
935− return r;
915+ return 0;
936916 }
937917
938918 /*
@@ -982,12 +962,7 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo) · 43 unmodified lines
982962
983963 /* Bind pages */
984964 gtt->offset = (u64)tmp->start << PAGE_SHIFT;
985− r = amdgpu_ttm_gart_bind(adev, bo, flags);
986− if (unlikely(r)) {
987− ttm_resource_free(bo, &tmp);
988− return r;
989− }
990−
965+ amdgpu_ttm_gart_bind(adev, bo, flags);
991966 amdgpu_gart_invalidate_tlb(adev);
992967 ttm_resource_free(bo, &bo->resource);
993968 ttm_bo_assign_mem(bo, tmp);
@@ -1001,19 +976,16 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo) · 7 unmodified lines
1001976 * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1002977 * rebind GTT pages during a GPU reset.
1003978 */
1004−int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
979+void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1005980 {
1006981 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1007982 uint64_t flags;
1008− int r;
1009983
1010984 if (!tbo->ttm)
1011− return 0;
985+ return;
1012986
1013987 flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, tbo->resource);
1014− r = amdgpu_ttm_gart_bind(adev, tbo, flags);
1015−
1016− return r;
988+ amdgpu_ttm_gart_bind(adev, tbo, flags);
1017989 }
1018990
1019991 /*
@@ -1027,7 +999,6 @@ static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev, · 7 unmodified lines
1027999 {
10281000 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
10291001 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1030− int r;
10311002
10321003 /* if the pages have userptr pinning then clear that first */
10331004 if (gtt->userptr) {
@@ -1047,10 +1018,7 @@ static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev, · 13 unmodified lines
10471018 return;
10481019
10491020 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1050− r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1051− if (r)
1052− DRM_ERROR("failed to unbind %u pages at 0x%08llX\n",
1053− gtt->ttm.num_pages, gtt->offset);
1021+ amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
10541022 gtt->bound = false;
10551023 }
10561024
@@ -1168,6 +1136,26 @@ static void amdgpu_ttm_tt_unpopulate(struct ttm_device *bdev, · 111 unmodified lines
11681136 return ttm_pool_free(&adev->mman.bdev.pool, ttm);
11691137 }
11701138
1139+/**
1140+ * amdgpu_ttm_tt_get_userptr - Return the userptr GTT ttm_tt for the current
1141+ * task
1142+ *
1143+ * @tbo: The ttm_buffer_object that contains the userptr
1144+ * @user_addr: The returned value
1145+ */
1146+int amdgpu_ttm_tt_get_userptr(const struct ttm_buffer_object *tbo,
1147+ uint64_t *user_addr)
1148+{
1149+ struct amdgpu_ttm_tt *gtt;
1150+
1151+ if (!tbo->ttm)
1152+ return -EINVAL;
1153+
1154+ gtt = (void *)tbo->ttm;
1155+ *user_addr = gtt->userptr;
1156+ return 0;
1157+}
1158+
11711159 /**
11721160 * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
11731161 * task
@@ -1433,6 +1421,63 @@ static void amdgpu_ttm_vram_mm_access(struct amdgpu_device *adev, loff_t pos, · 259 unmodified lines
14331421 }
14341422 }
14351423
1424+static int amdgpu_ttm_access_memory_sdma(struct ttm_buffer_object *bo,
1425+ unsigned long offset, void *buf, int len, int write)
1426+{
1427+ struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1428+ struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1429+ struct amdgpu_res_cursor src_mm;
1430+ struct amdgpu_job *job;
1431+ struct dma_fence *fence;
1432+ uint64_t src_addr, dst_addr;
1433+ unsigned int num_dw;
1434+ int r, idx;
1435+
1436+ if (len != PAGE_SIZE)
1437+ return -EINVAL;
1438+
1439+ if (!adev->mman.sdma_access_ptr)
1440+ return -EACCES;
1441+
1442+ if (!drm_dev_enter(adev_to_drm(adev), &idx))
1443+ return -ENODEV;
1444+
1445+ if (write)
1446+ memcpy(adev->mman.sdma_access_ptr, buf, len);
1447+
1448+ num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
1449+ r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED, &job);
1450+ if (r)
1451+ goto out;
1452+
1453+ amdgpu_res_first(abo->tbo.resource, offset, len, &src_mm);
1454+ src_addr = amdgpu_ttm_domain_start(adev, bo->resource->mem_type) + src_mm.start;
1455+ dst_addr = amdgpu_bo_gpu_offset(adev->mman.sdma_access_bo);
1456+ if (write)
1457+ swap(src_addr, dst_addr);
1458+
1459+ amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, dst_addr, PAGE_SIZE, false);
1460+
1461+ amdgpu_ring_pad_ib(adev->mman.buffer_funcs_ring, &job->ibs[0]);
1462+ WARN_ON(job->ibs[0].length_dw > num_dw);
1463+
1464+ r = amdgpu_job_submit(job, &adev->mman.entity, AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
1465+ if (r) {
1466+ amdgpu_job_free(job);
1467+ goto out;
1468+ }
1469+
1470+ if (!dma_fence_wait_timeout(fence, false, adev->sdma_timeout))
1471+ r = -ETIMEDOUT;
1472+ dma_fence_put(fence);
1473+
1474+ if (!(r || write))
1475+ memcpy(buf, adev->mman.sdma_access_ptr, len);
1476+out:
1477+ drm_dev_exit(idx);
1478+ return r;
1479+}
1480+
14361481 /**
14371482 * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
14381483 *
@@ -1457,6 +1502,10 @@ static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo, · 18 unmodified lines
14571502 if (bo->resource->mem_type != TTM_PL_VRAM)
14581503 return -EIO;
14591504
1505+ if (amdgpu_device_has_timeouts_enabled(adev) &&
1506+ !amdgpu_ttm_access_memory_sdma(bo, offset, buf, len, write))
1507+ return len;
1508+
14601509 amdgpu_res_first(bo->resource, offset, len, &cursor);
14611510 while (cursor.remaining) {
14621511 size_t count, size = cursor.size;
@@ -1797,6 +1846,12 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) · 334 unmodified lines
17971846 return r;
17981847 }
17991848
1849+ if (amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,
1850+ AMDGPU_GEM_DOMAIN_GTT,
1851+ &adev->mman.sdma_access_bo, NULL,
1852+ &adev->mman.sdma_access_ptr))
1853+ DRM_WARN("Debug VRAM access will use slowpath MM access\n");
1854+
18001855 return 0;
18011856 }
18021857
@@ -1818,6 +1873,8 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev) · 15 unmodified lines
18181873 if (adev->mman.stolen_reserved_size)
18191874 amdgpu_bo_free_kernel(&adev->mman.stolen_reserved_memory,
18201875 NULL, NULL);
1876+ amdgpu_bo_free_kernel(&adev->mman.sdma_access_bo, NULL,
1877+ &adev->mman.sdma_access_ptr);
18211878 amdgpu_ttm_fw_reserve_vram_fini(adev);
18221879
18231880 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
@@ -1884,27 +1941,59 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable) · 60 unmodified lines
18841941 size = adev->gmc.real_vram_size;
18851942 else
18861943 size = adev->gmc.visible_vram_size;
1887− man->size = size >> PAGE_SHIFT;
1944+ man->size = size;
18881945 adev->mman.buffer_funcs_enabled = enable;
18891946 }
18901947
1948+static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev,
1949+ bool direct_submit,
1950+ unsigned int num_dw,
1951+ struct dma_resv *resv,
1952+ bool vm_needs_flush,
1953+ struct amdgpu_job **job)
1954+{
1955+ enum amdgpu_ib_pool_type pool = direct_submit ?
1956+ AMDGPU_IB_POOL_DIRECT :
1957+ AMDGPU_IB_POOL_DELAYED;
1958+ int r;
1959+
1960+ r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, job);
1961+ if (r)
1962+ return r;
1963+
1964+ if (vm_needs_flush) {
1965+ (*job)->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo ?
1966+ adev->gmc.pdb0_bo :
1967+ adev->gart.bo);
1968+ (*job)->vm_needs_flush = true;
1969+ }
1970+ if (resv) {
1971+ r = amdgpu_sync_resv(adev, &(*job)->sync, resv,
1972+ AMDGPU_SYNC_ALWAYS,
1973+ AMDGPU_FENCE_OWNER_UNDEFINED);
1974+ if (r) {
1975+ DRM_ERROR("sync failed (%d).\n", r);
1976+ amdgpu_job_free(*job);
1977+ return r;
1978+ }
1979+ }
1980+ return 0;
1981+}
1982+
18911983 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
18921984 uint64_t dst_offset, uint32_t byte_count,
18931985 struct dma_resv *resv,
18941986 struct dma_fence **fence, bool direct_submit,
18951987 bool vm_needs_flush, bool tmz)
18961988 {
1897− enum amdgpu_ib_pool_type pool = direct_submit ? AMDGPU_IB_POOL_DIRECT :
1898− AMDGPU_IB_POOL_DELAYED;
18991989 struct amdgpu_device *adev = ring->adev;
1990+ unsigned num_loops, num_dw;
19001991 struct amdgpu_job *job;
1901−
19021992 uint32_t max_bytes;
1903− unsigned num_loops, num_dw;
19041993 unsigned i;
19051994 int r;
19061995
1907− if (direct_submit && !ring->sched.ready) {
1996+ if (!direct_submit && !ring->sched.ready) {
19081997 DRM_ERROR("Trying to move memory with ring turned off.\n");
19091998 return -EINVAL;
19101999 }
@@ -1912,26 +2001,11 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, · 1 unmodified line
19122001 max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
19132002 num_loops = DIV_ROUND_UP(byte_count, max_bytes);
19142003 num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
1915−
1916− r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, &job);
2004+ r = amdgpu_ttm_prepare_job(adev, direct_submit, num_dw,
2005+ resv, vm_needs_flush, &job);
19172006 if (r)
19182007 return r;
19192008
1920− if (vm_needs_flush) {
1921− job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo ?
1922− adev->gmc.pdb0_bo : adev->gart.bo);
1923− job->vm_needs_flush = true;
1924− }
1925− if (resv) {
1926− r = amdgpu_sync_resv(adev, &job->sync, resv,
1927− AMDGPU_SYNC_ALWAYS,
1928− AMDGPU_FENCE_OWNER_UNDEFINED);
1929− if (r) {
1930− DRM_ERROR("sync failed (%d).\n", r);
1931− goto error_free;
1932− }
1933− }
1934−
19352009 for (i = 0; i < num_loops; i++) {
19362010 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
19372011
@@ -1961,77 +2035,35 @@ error_free: · 23 unmodified lines
19612035 return r;
19622036 }
19632037
1964−int amdgpu_fill_buffer(struct amdgpu_bo *bo,
1965− uint32_t src_data,
1966− struct dma_resv *resv,
1967− struct dma_fence **fence)
2038+static int amdgpu_ttm_fill_mem(struct amdgpu_ring *ring, uint32_t src_data,
2039+ uint64_t dst_addr, uint32_t byte_count,
2040+ struct dma_resv *resv,
2041+ struct dma_fence **fence,
2042+ bool vm_needs_flush)
19682043 {
1969− struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1970− uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
1971− struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
1972−
1973− struct amdgpu_res_cursor cursor;
2044+ struct amdgpu_device *adev = ring->adev;
19742045 unsigned int num_loops, num_dw;
1975− uint64_t num_bytes;
1976−
19772046 struct amdgpu_job *job;
2047+ uint32_t max_bytes;
2048+ unsigned int i;
19782049 int r;
19792050
1980− if (!adev->mman.buffer_funcs_enabled) {
1981− DRM_ERROR("Trying to clear memory with ring turned off.\n");
1982− return -EINVAL;
1983− }
1984−
1985− if (bo->tbo.resource->mem_type == AMDGPU_PL_PREEMPT) {
1986− DRM_ERROR("Trying to clear preemptible memory.\n");
1987− return -EINVAL;
1988− }
1989−
1990− if (bo->tbo.resource->mem_type == TTM_PL_TT) {
1991− r = amdgpu_ttm_alloc_gart(&bo->tbo);
1992− if (r)
1993− return r;
1994− }
1995−
1996− num_bytes = bo->tbo.resource->num_pages << PAGE_SHIFT;
1997− num_loops = 0;
1998−
1999− amdgpu_res_first(bo->tbo.resource, 0, num_bytes, &cursor);
2000− while (cursor.remaining) {
2001− num_loops += DIV_ROUND_UP_ULL(cursor.size, max_bytes);
2002− amdgpu_res_next(&cursor, cursor.size);
2003− }
2004− num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
2005−
2006− /* for IB padding */
2007− num_dw += 64;
2008−
2009− r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED,
2010− &job);
2051+ max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
2052+ num_loops = DIV_ROUND_UP_ULL(byte_count, max_bytes);
2053+ num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->fill_num_dw, 8);
2054+ r = amdgpu_ttm_prepare_job(adev, false, num_dw, resv, vm_needs_flush,
2055+ &job);
20112056 if (r)
20122057 return r;
20132058
2014− if (resv) {
2015− r = amdgpu_sync_resv(adev, &job->sync, resv,
2016− AMDGPU_SYNC_ALWAYS,
2017− AMDGPU_FENCE_OWNER_UNDEFINED);
2018− if (r) {
2019− DRM_ERROR("sync failed (%d).\n", r);
2020− goto error_free;
2021− }
2022− }
2023−
2024− amdgpu_res_first(bo->tbo.resource, 0, num_bytes, &cursor);
2025− while (cursor.remaining) {
2026− uint32_t cur_size = min_t(uint64_t, cursor.size, max_bytes);
2027− uint64_t dst_addr = cursor.start;
2059+ for (i = 0; i < num_loops; i++) {
2060+ uint32_t cur_size = min(byte_count, max_bytes);
20282061
2029− dst_addr += amdgpu_ttm_domain_start(adev,
2030− bo->tbo.resource->mem_type);
20312062 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, dst_addr,
20322063 cur_size);
20332064
2034− amdgpu_res_next(&cursor, cur_size);
2065+ dst_addr += cur_size;
2066+ byte_count -= cur_size;
20352067 }
20362068
20372069 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
@@ -2048,6 +2080,55 @@ error_free: · 10 unmodified lines
20482080 return r;
20492081 }
20502082
2083+int amdgpu_fill_buffer(struct amdgpu_bo *bo,
2084+ uint32_t src_data,
2085+ struct dma_resv *resv,
2086+ struct dma_fence **f)
2087+{
2088+ struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
2089+ struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2090+ struct dma_fence *fence = NULL;
2091+ struct amdgpu_res_cursor dst;
2092+ int r;
2093+
2094+ if (!adev->mman.buffer_funcs_enabled) {
2095+ DRM_ERROR("Trying to clear memory with ring turned off.\n");
2096+ return -EINVAL;
2097+ }
2098+
2099+ amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &dst);
2100+
2101+ mutex_lock(&adev->mman.gtt_window_lock);
2102+ while (dst.remaining) {
2103+ struct dma_fence *next;
2104+ uint64_t cur_size, to;
2105+
2106+ /* Never fill more than 256MiB at once to avoid timeouts */
2107+ cur_size = min(dst.size, 256ULL << 20);
2108+
2109+ r = amdgpu_ttm_map_buffer(&bo->tbo, bo->tbo.resource, &dst,
2110+ 1, ring, false, &cur_size, &to);
2111+ if (r)
2112+ goto error;
2113+
2114+ r = amdgpu_ttm_fill_mem(ring, src_data, to, cur_size, resv,
2115+ &next, true);
2116+ if (r)
2117+ goto error;
2118+
2119+ dma_fence_put(fence);
2120+ fence = next;
2121+
2122+ amdgpu_res_next(&dst, cur_size);
2123+ }
2124+error:
2125+ mutex_unlock(&adev->mman.gtt_window_lock);
2126+ if (f)
2127+ *f = dma_fence_get(fence);
2128+ dma_fence_put(fence);
2129+ return r;
2130+}
2131+
20512132 /**
20522133 * amdgpu_ttm_evict_resources - evict memory buffers
20532134 * @adev: amdgpu device object
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h+9−12
@@ -44,7 +44,6 @@ struct amdgpu_vram_mgr { · 43 unmodified lines
4444 spinlock_t lock;
4545 struct list_head reservations_pending;
4646 struct list_head reserved_pages;
47− atomic64_t usage;
4847 atomic64_t vis_usage;
4948 };
5049
@@ -52,12 +51,6 @@ struct amdgpu_gtt_mgr { · 1 unmodified line
5251 struct ttm_resource_manager manager;
5352 struct drm_mm mm;
5453 spinlock_t lock;
55− atomic64_t used;
56−};
57−
58−struct amdgpu_preempt_mgr {
59− struct ttm_resource_manager manager;
60− atomic64_t used;
6154 };
6255
6356 struct amdgpu_mman {
@@ -76,7 +69,7 @@ struct amdgpu_mman { · 12 unmodified lines
7669
7770 struct amdgpu_vram_mgr vram_mgr;
7871 struct amdgpu_gtt_mgr gtt_mgr;
79− struct amdgpu_preempt_mgr preempt_mgr;
72+ struct ttm_resource_manager preempt_mgr;
8073
8174 uint64_t stolen_vga_size;
8275 struct amdgpu_bo *stolen_vga_memory;
@@ -98,6 +91,10 @@ struct amdgpu_mman { · 15 unmodified lines
9891 u64 fw_vram_usage_size;
9992 struct amdgpu_bo *fw_vram_usage_reserved_bo;
10093 void *fw_vram_usage_va;
94+
95+ /* PAGE_SIZE'd BO for process memory r/w over SDMA. */
96+ struct amdgpu_bo *sdma_access_bo;
97+ void *sdma_access_ptr;
10198 };
10299
103100 struct amdgpu_copy_mem {
@@ -114,8 +111,7 @@ int amdgpu_vram_mgr_init(struct amdgpu_device *adev); · 10 unmodified lines
114111 void amdgpu_vram_mgr_fini(struct amdgpu_device *adev);
115112
116113 bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_resource *mem);
117−uint64_t amdgpu_gtt_mgr_usage(struct amdgpu_gtt_mgr *mgr);
118−int amdgpu_gtt_mgr_recover(struct amdgpu_gtt_mgr *mgr);
114+void amdgpu_gtt_mgr_recover(struct amdgpu_gtt_mgr *mgr);
119115
120116 uint64_t amdgpu_preempt_mgr_usage(struct ttm_resource_manager *man);
121117
@@ -129,7 +125,6 @@ int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev, · 7 unmodified lines
129125 void amdgpu_vram_mgr_free_sgt(struct device *dev,
130126 enum dma_data_direction dir,
131127 struct sg_table *sgt);
132−uint64_t amdgpu_vram_mgr_usage(struct amdgpu_vram_mgr *mgr);
133128 uint64_t amdgpu_vram_mgr_vis_usage(struct amdgpu_vram_mgr *mgr);
134129 int amdgpu_vram_mgr_reserve_range(struct amdgpu_vram_mgr *mgr,
135130 uint64_t start, uint64_t size);
@@ -158,7 +153,7 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo, · 22 unmodified lines
158153 struct dma_fence **fence);
159154
160155 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo);
161−int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo);
156+void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo);
162157 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type);
163158
164159 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
@@ -177,6 +172,8 @@ static inline bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm) · 12 unmodified lines
177172 #endif
178173
179174 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages);
175+int amdgpu_ttm_tt_get_userptr(const struct ttm_buffer_object *tbo,
176+ uint64_t *user_addr);
180177 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,
181178 uint64_t addr, uint32_t flags);
182179 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h+1−0
@@ -378,6 +378,7 @@ enum AMDGPU_UCODE_ID { · 377 unmodified lines
378378 AMDGPU_UCODE_ID_VCN0_RAM,
379379 AMDGPU_UCODE_ID_VCN1_RAM,
380380 AMDGPU_UCODE_ID_DMCUB,
381+ AMDGPU_UCODE_ID_CAP,
381382 AMDGPU_UCODE_ID_MAXIMUM,
382383 };
383384
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c+47−59
@@ -21,7 +21,7 @@ · 20 unmodified lines
2121 *
2222 */
2323
24−#include "amdgpu_ras.h"
24+#include "amdgpu.h"
2525
2626 static int amdgpu_umc_do_page_retirement(struct amdgpu_device *adev,
2727 void *ras_error_status,
@@ -33,14 +33,14 @@ static int amdgpu_umc_do_page_retirement(struct amdgpu_device *adev, · 5 unmodified lines
3333 int ret = 0;
3434
3535 kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
36− ret = smu_get_ecc_info(&adev->smu, (void *)&(con->umc_ecc));
36+ ret = amdgpu_dpm_get_ecc_info(adev, (void *)&(con->umc_ecc));
3737 if (ret == -EOPNOTSUPP) {
38− if (adev->umc.ras_funcs &&
39− adev->umc.ras_funcs->query_ras_error_count)
40− adev->umc.ras_funcs->query_ras_error_count(adev, ras_error_status);
38+ if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
39+ adev->umc.ras->ras_block.hw_ops->query_ras_error_count)
40+ adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, ras_error_status);
4141
42− if (adev->umc.ras_funcs &&
43− adev->umc.ras_funcs->query_ras_error_address &&
42+ if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
43+ adev->umc.ras->ras_block.hw_ops->query_ras_error_address &&
4444 adev->umc.max_ras_err_cnt_per_query) {
4545 err_data->err_addr =
4646 kcalloc(adev->umc.max_ras_err_cnt_per_query,
@@ -56,15 +56,15 @@ static int amdgpu_umc_do_page_retirement(struct amdgpu_device *adev, · 9 unmodified lines
5656 /* umc query_ras_error_address is also responsible for clearing
5757 * error status
5858 */
59− adev->umc.ras_funcs->query_ras_error_address(adev, ras_error_status);
59+ adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, ras_error_status);
6060 }
6161 } else if (!ret) {
62− if (adev->umc.ras_funcs &&
63− adev->umc.ras_funcs->ecc_info_query_ras_error_count)
64− adev->umc.ras_funcs->ecc_info_query_ras_error_count(adev, ras_error_status);
62+ if (adev->umc.ras &&
63+ adev->umc.ras->ecc_info_query_ras_error_count)
64+ adev->umc.ras->ecc_info_query_ras_error_count(adev, ras_error_status);
6565
66− if (adev->umc.ras_funcs &&
67− adev->umc.ras_funcs->ecc_info_query_ras_error_address &&
66+ if (adev->umc.ras &&
67+ adev->umc.ras->ecc_info_query_ras_error_address &&
6868 adev->umc.max_ras_err_cnt_per_query) {
6969 err_data->err_addr =
7070 kcalloc(adev->umc.max_ras_err_cnt_per_query,
@@ -80,7 +80,7 @@ static int amdgpu_umc_do_page_retirement(struct amdgpu_device *adev, · 9 unmodified lines
8080 /* umc query_ras_error_address is also responsible for clearing
8181 * error status
8282 */
83− adev->umc.ras_funcs->ecc_info_query_ras_error_address(adev, ras_error_status);
83+ adev->umc.ras->ecc_info_query_ras_error_address(adev, ras_error_status);
8484 }
8585 }
8686
@@ -96,8 +96,7 @@ static int amdgpu_umc_do_page_retirement(struct amdgpu_device *adev, · 9 unmodified lines
9696 err_data->err_addr_cnt);
9797 amdgpu_ras_save_bad_pages(adev);
9898
99− if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->send_hbm_bad_pages_num)
100− adev->smu.ppt_funcs->send_hbm_bad_pages_num(&adev->smu, con->eeprom_control.ras_num_recs);
99+ amdgpu_dpm_send_hbm_bad_pages_num(adev, con->eeprom_control.ras_num_recs);
101100 }
102101
103102 if (reset)
@@ -130,76 +129,44 @@ int amdgpu_umc_poison_handler(struct amdgpu_device *adev, · 26 unmodified lines
130129 return ret;
131130 }
132131
133−static int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev,
132+int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev,
134133 void *ras_error_status,
135134 struct amdgpu_iv_entry *entry)
136135 {
137136 return amdgpu_umc_do_page_retirement(adev, ras_error_status, entry, true);
138137 }
139138
140−int amdgpu_umc_ras_late_init(struct amdgpu_device *adev)
139+int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
141140 {
142141 int r;
143− struct ras_fs_if fs_info = {
144− .sysfs_name = "umc_err_count",
145− };
146− struct ras_ih_if ih_info = {
147− .cb = amdgpu_umc_process_ras_data_cb,
148− };
149−
150− if (!adev->umc.ras_if) {
151− adev->umc.ras_if =
152− kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
153− if (!adev->umc.ras_if)
154− return -ENOMEM;
155− adev->umc.ras_if->block = AMDGPU_RAS_BLOCK__UMC;
156− adev->umc.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
157− adev->umc.ras_if->sub_block_index = 0;
158− }
159− ih_info.head = fs_info.head = *adev->umc.ras_if;
160142
161− r = amdgpu_ras_late_init(adev, adev->umc.ras_if,
162− &fs_info, &ih_info);
143+ r = amdgpu_ras_block_late_init(adev, ras_block);
163144 if (r)
164− goto free;
145+ return r;
165146
166− if (amdgpu_ras_is_supported(adev, adev->umc.ras_if->block)) {
147+ if (amdgpu_ras_is_supported(adev, ras_block->block)) {
167148 r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0);
168149 if (r)
169150 goto late_fini;
170− } else {
171− r = 0;
172− goto free;
173151 }
174152
175153 /* ras init of specific umc version */
176− if (adev->umc.ras_funcs &&
177− adev->umc.ras_funcs->err_cnt_init)
178− adev->umc.ras_funcs->err_cnt_init(adev);
154+ if (adev->umc.ras &&
155+ adev->umc.ras->err_cnt_init)
156+ adev->umc.ras->err_cnt_init(adev);
179157
180158 return 0;
181159
182160 late_fini:
183− amdgpu_ras_late_fini(adev, adev->umc.ras_if, &ih_info);
184−free:
185− kfree(adev->umc.ras_if);
186− adev->umc.ras_if = NULL;
161+ amdgpu_ras_block_late_fini(adev, ras_block);
187162 return r;
188163 }
189164
190165 void amdgpu_umc_ras_fini(struct amdgpu_device *adev)
191166 {
192167 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC) &&
193− adev->umc.ras_if) {
194− struct ras_common_if *ras_if = adev->umc.ras_if;
195− struct ras_ih_if ih_info = {
196− .head = *ras_if,
197− .cb = amdgpu_umc_process_ras_data_cb,
198− };
199−
200− amdgpu_ras_late_fini(adev, ras_if, &ih_info);
201− kfree(ras_if);
202− }
168+ adev->umc.ras_if)
169+ amdgpu_ras_block_late_fini(adev, adev->umc.ras_if);
203170 }
204171
205172 int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev,
@@ -219,3 +186,24 @@ int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev, · 13 unmodified lines
219186 amdgpu_ras_interrupt_dispatch(adev, &ih_data);
220187 return 0;
221188 }
189+
190+void amdgpu_umc_fill_error_record(struct ras_err_data *err_data,
191+ uint64_t err_addr,
192+ uint64_t retired_page,
193+ uint32_t channel_index,
194+ uint32_t umc_inst)
195+{
196+ struct eeprom_table_record *err_rec =
197+ &err_data->err_addr[err_data->err_addr_cnt];
198+
199+ err_rec->address = err_addr;
200+ /* page frame address is saved */
201+ err_rec->retired_page = retired_page >> AMDGPU_GPU_PAGE_SHIFT;
202+ err_rec->ts = (uint64_t)ktime_get_real_seconds();
203+ err_rec->err_type = AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE;
204+ err_rec->cu = 0;
205+ err_rec->mem_channel = channel_index;
206+ err_rec->mcumc_id = umc_inst;
207+
208+ err_data->err_addr_cnt++;
209+}
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h+14−9
@@ -20,6 +20,7 @@ · 19 unmodified lines
2020 */
2121 #ifndef __AMDGPU_UMC_H__
2222 #define __AMDGPU_UMC_H__
23+#include "amdgpu_ras.h"
2324
2425 /*
2526 * (addr / 256) * 4096, the higher 26 bits in ErrorAddr
@@ -40,14 +41,9 @@ · 14 unmodified lines
4041 #define LOOP_UMC_CH_INST(ch_inst) for ((ch_inst) = 0; (ch_inst) < adev->umc.channel_inst_num; (ch_inst)++)
4142 #define LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) LOOP_UMC_INST((umc_inst)) LOOP_UMC_CH_INST((ch_inst))
4243
43−struct amdgpu_umc_ras_funcs {
44+struct amdgpu_umc_ras {
45+ struct amdgpu_ras_block_object ras_block;
4446 void (*err_cnt_init)(struct amdgpu_device *adev);
45− int (*ras_late_init)(struct amdgpu_device *adev);
46− void (*ras_fini)(struct amdgpu_device *adev);
47− void (*query_ras_error_count)(struct amdgpu_device *adev,
48− void *ras_error_status);
49− void (*query_ras_error_address)(struct amdgpu_device *adev,
50− void *ras_error_status);
5147 bool (*query_ras_poison_mode)(struct amdgpu_device *adev);
5248 void (*ecc_info_query_ras_error_count)(struct amdgpu_device *adev,
5349 void *ras_error_status);
@@ -73,10 +69,10 @@ struct amdgpu_umc { · 19 unmodified lines
7369 struct ras_common_if *ras_if;
7470
7571 const struct amdgpu_umc_funcs *funcs;
76− const struct amdgpu_umc_ras_funcs *ras_funcs;
72+ struct amdgpu_umc_ras *ras;
7773 };
7874
79−int amdgpu_umc_ras_late_init(struct amdgpu_device *adev);
75+int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);
8076 void amdgpu_umc_ras_fini(struct amdgpu_device *adev);
8177 int amdgpu_umc_poison_handler(struct amdgpu_device *adev,
8278 void *ras_error_status,
@@ -84,4 +80,13 @@ int amdgpu_umc_poison_handler(struct amdgpu_device *adev, · 1 unmodified line
8480 int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev,
8581 struct amdgpu_irq_src *source,
8682 struct amdgpu_iv_entry *entry);
83+void amdgpu_umc_fill_error_record(struct ras_err_data *err_data,
84+ uint64_t err_addr,
85+ uint64_t retired_page,
86+ uint32_t channel_index,
87+ uint32_t umc_inst);
88+
89+int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev,
90+ void *ras_error_status,
91+ struct amdgpu_iv_entry *entry);
8792 #endif
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c+2−0
@@ -834,6 +834,7 @@ static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx, · 833 unmodified lines
834834 handle = msg[2];
835835
836836 if (handle == 0) {
837+ amdgpu_bo_kunmap(bo);
837838 DRM_ERROR("Invalid UVD handle!\n");
838839 return -EINVAL;
839840 }
@@ -892,6 +893,7 @@ static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx, · 52 unmodified lines
892893 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
893894 }
894895
896+ amdgpu_bo_kunmap(bo);
895897 return -EINVAL;
896898 }
897899
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c+149−2
@@ -575,8 +575,10 @@ static int amdgpu_virt_write_vf2pf_data(struct amdgpu_device *adev) · 574 unmodified lines
575575 vf2pf_info->driver_cert = 0;
576576 vf2pf_info->os_info.all = 0;
577577
578− vf2pf_info->fb_usage = amdgpu_vram_mgr_usage(&adev->mman.vram_mgr) >> 20;
579− vf2pf_info->fb_vis_usage = amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr) >> 20;
578+ vf2pf_info->fb_usage =
579+ ttm_resource_manager_usage(&adev->mman.vram_mgr.manager) >> 20;
580+ vf2pf_info->fb_vis_usage =
581+ amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr) >> 20;
580582 vf2pf_info->fb_size = adev->gmc.real_vram_size >> 20;
581583 vf2pf_info->fb_vis_size = adev->gmc.visible_vram_size >> 20;
582584
@@ -820,3 +822,148 @@ void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev, · 237 unmodified lines
820822 }
821823 }
822824 }
825+
826+static bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev,
827+ u32 acc_flags, u32 hwip,
828+ bool write, u32 *rlcg_flag)
829+{
830+ bool ret = false;
831+
832+ switch (hwip) {
833+ case GC_HWIP:
834+ if (amdgpu_sriov_reg_indirect_gc(adev)) {
835+ *rlcg_flag =
836+ write ? AMDGPU_RLCG_GC_WRITE : AMDGPU_RLCG_GC_READ;
837+ ret = true;
838+ /* only in new version, AMDGPU_REGS_NO_KIQ and
839+ * AMDGPU_REGS_RLC are enabled simultaneously */
840+ } else if ((acc_flags & AMDGPU_REGS_RLC) &&
841+ !(acc_flags & AMDGPU_REGS_NO_KIQ) && write) {
842+ *rlcg_flag = AMDGPU_RLCG_GC_WRITE_LEGACY;
843+ ret = true;
844+ }
845+ break;
846+ case MMHUB_HWIP:
847+ if (amdgpu_sriov_reg_indirect_mmhub(adev) &&
848+ (acc_flags & AMDGPU_REGS_RLC) && write) {
849+ *rlcg_flag = AMDGPU_RLCG_MMHUB_WRITE;
850+ ret = true;
851+ }
852+ break;
853+ default:
854+ break;
855+ }
856+ return ret;
857+}
858+
859+static u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag)
860+{
861+ struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
862+ uint32_t timeout = 50000;
863+ uint32_t i, tmp;
864+ uint32_t ret = 0;
865+ static void *scratch_reg0;
866+ static void *scratch_reg1;
867+ static void *scratch_reg2;
868+ static void *scratch_reg3;
869+ static void *spare_int;
870+
871+ if (!adev->gfx.rlc.rlcg_reg_access_supported) {
872+ dev_err(adev->dev,
873+ "indirect registers access through rlcg is not available\n");
874+ return 0;
875+ }
876+
877+ reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl;
878+ scratch_reg0 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg0;
879+ scratch_reg1 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg1;
880+ scratch_reg2 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg2;
881+ scratch_reg3 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg3;
882+ if (reg_access_ctrl->spare_int)
883+ spare_int = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->spare_int;
884+
885+ if (offset == reg_access_ctrl->grbm_cntl) {
886+ /* if the target reg offset is grbm_cntl, write to scratch_reg2 */
887+ writel(v, scratch_reg2);
888+ writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));
889+ } else if (offset == reg_access_ctrl->grbm_idx) {
890+ /* if the target reg offset is grbm_idx, write to scratch_reg3 */
891+ writel(v, scratch_reg3);
892+ writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));
893+ } else {
894+ /*
895+ * SCRATCH_REG0 = read/write value
896+ * SCRATCH_REG1[30:28] = command
897+ * SCRATCH_REG1[19:0] = address in dword
898+ * SCRATCH_REG1[26:24] = Error reporting
899+ */
900+ writel(v, scratch_reg0);
901+ writel((offset | flag), scratch_reg1);
902+ if (reg_access_ctrl->spare_int)
903+ writel(1, spare_int);
904+
905+ for (i = 0; i < timeout; i++) {
906+ tmp = readl(scratch_reg1);
907+ if (!(tmp & AMDGPU_RLCG_SCRATCH1_ADDRESS_MASK))
908+ break;
909+ udelay(10);
910+ }
911+
912+ if (i >= timeout) {
913+ if (amdgpu_sriov_rlcg_error_report_enabled(adev)) {
914+ if (tmp & AMDGPU_RLCG_VFGATE_DISABLED) {
915+ dev_err(adev->dev,
916+ "vfgate is disabled, rlcg failed to program reg: 0x%05x\n", offset);
917+ } else if (tmp & AMDGPU_RLCG_WRONG_OPERATION_TYPE) {
918+ dev_err(adev->dev,
919+ "wrong operation type, rlcg failed to program reg: 0x%05x\n", offset);
920+ } else if (tmp & AMDGPU_RLCG_REG_NOT_IN_RANGE) {
921+ dev_err(adev->dev,
922+ "regiser is not in range, rlcg failed to program reg: 0x%05x\n", offset);
923+ } else {
924+ dev_err(adev->dev,
925+ "unknown error type, rlcg failed to program reg: 0x%05x\n", offset);
926+ }
927+ } else {
928+ dev_err(adev->dev,
929+ "timeout: rlcg faled to program reg: 0x%05x\n", offset);
930+ }
931+ }
932+ }
933+
934+ ret = readl(scratch_reg0);
935+ return ret;
936+}
937+
938+void amdgpu_sriov_wreg(struct amdgpu_device *adev,
939+ u32 offset, u32 value,
940+ u32 acc_flags, u32 hwip)
941+{
942+ u32 rlcg_flag;
943+
944+ if (!amdgpu_sriov_runtime(adev) &&
945+ amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, true, &rlcg_flag)) {
946+ amdgpu_virt_rlcg_reg_rw(adev, offset, value, rlcg_flag);
947+ return;
948+ }
949+
950+ if (acc_flags & AMDGPU_REGS_NO_KIQ)
951+ WREG32_NO_KIQ(offset, value);
952+ else
953+ WREG32(offset, value);
954+}
955+
956+u32 amdgpu_sriov_rreg(struct amdgpu_device *adev,
957+ u32 offset, u32 acc_flags, u32 hwip)
958+{
959+ u32 rlcg_flag;
960+
961+ if (!amdgpu_sriov_runtime(adev) &&
962+ amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, false, &rlcg_flag))
963+ return amdgpu_virt_rlcg_reg_rw(adev, offset, 0, rlcg_flag);
964+
965+ if (acc_flags & AMDGPU_REGS_NO_KIQ)
966+ return RREG32_NO_KIQ(offset);
967+ else
968+ return RREG32(offset);
969+}
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h+24−2
@@ -32,6 +32,19 @@ · 31 unmodified lines
3232 #define AMDGPU_PASSTHROUGH_MODE (1 << 3) /* thw whole GPU is pass through for VM */
3333 #define AMDGPU_SRIOV_CAPS_RUNTIME (1 << 4) /* is out of full access mode */
3434
35+/* flags for indirect register access path supported by rlcg for sriov */
36+#define AMDGPU_RLCG_GC_WRITE_LEGACY (0x8 << 28)
37+#define AMDGPU_RLCG_GC_WRITE (0x0 << 28)
38+#define AMDGPU_RLCG_GC_READ (0x1 << 28)
39+#define AMDGPU_RLCG_MMHUB_WRITE (0x2 << 28)
40+
41+/* error code for indirect register access path supported by rlcg for sriov */
42+#define AMDGPU_RLCG_VFGATE_DISABLED 0x4000000
43+#define AMDGPU_RLCG_WRONG_OPERATION_TYPE 0x2000000
44+#define AMDGPU_RLCG_REG_NOT_IN_RANGE 0x1000000
45+
46+#define AMDGPU_RLCG_SCRATCH1_ADDRESS_MASK 0xFFFFF
47+
3548 /* all asic after AI use this offset */
3649 #define mmRCC_IOV_FUNC_IDENTIFIER 0xDE5
3750 /* tonga/fiji use this offset */
@@ -275,13 +288,18 @@ struct amdgpu_video_codec_info; · 237 unmodified lines
275288 (amdgpu_sriov_vf((adev)) && \
276289 ((adev)->virt.reg_access & (AMDGIM_FEATURE_GC_REG_RLC_EN)))
277290
291+#define amdgpu_sriov_rlcg_error_report_enabled(adev) \
292+ (amdgpu_sriov_reg_indirect_mmhub(adev) || amdgpu_sriov_reg_indirect_gc(adev))
293+
278294 #define amdgpu_passthrough(adev) \
279295 ((adev)->virt.caps & AMDGPU_PASSTHROUGH_MODE)
280296
281297 static inline bool is_virtual_machine(void)
282298 {
283−#ifdef CONFIG_X86
299+#if defined(CONFIG_X86)
284300 return boot_cpu_has(X86_FEATURE_HYPERVISOR);
301+#elif defined(CONFIG_ARM64)
302+ return !is_kernel_in_hyp_mode();
285303 #else
286304 return false;
287305 #endif
@@ -293,7 +311,6 @@ static inline bool is_virtual_machine(void) · 5 unmodified lines
293311 ((!amdgpu_in_reset(adev)) && adev->virt.tdr_debug)
294312 #define amdgpu_sriov_is_normal(adev) \
295313 ((!amdgpu_in_reset(adev)) && (!adev->virt.tdr_debug))
296−
297314 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev);
298315 void amdgpu_virt_init_setting(struct amdgpu_device *adev);
299316 void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev,
@@ -321,4 +338,9 @@ enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *ad · 21 unmodified lines
321338 void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev,
322339 struct amdgpu_video_codec_info *encode, uint32_t encode_array_size,
323340 struct amdgpu_video_codec_info *decode, uint32_t decode_array_size);
341+void amdgpu_sriov_wreg(struct amdgpu_device *adev,
342+ u32 offset, u32 value,
343+ u32 acc_flags, u32 hwip);
344+u32 amdgpu_sriov_rreg(struct amdgpu_device *adev,
345+ u32 offset, u32 acc_flags, u32 hwip);
324346 #endif
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c+9−3
@@ -375,6 +375,8 @@ static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base, · 374 unmodified lines
375375 if (bo->tbo.base.resv != vm->root.bo->tbo.base.resv)
376376 return;
377377
378+ dma_resv_assert_held(vm->root.bo->tbo.base.resv);
379+
378380 vm->bulk_moveable = false;
379381 if (bo->tbo.type == ttm_bo_type_kernel && bo->parent)
380382 amdgpu_vm_bo_relocated(base);
@@ -1634,7 +1636,7 @@ static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params *params, · 1253 unmodified lines
16341636 nptes = max(nptes, 1u);
16351637
16361638 trace_amdgpu_vm_update_ptes(params, frag_start, upd_end,
1637− nptes, dst, incr, upd_flags,
1639+ min(nptes, 32u), dst, incr, upd_flags,
16381640 vm->task_info.pid,
16391641 vm->immediate.fence_context);
16401642 amdgpu_vm_update_flags(params, to_amdgpu_bo_vm(pt),
@@ -2257,6 +2259,7 @@ struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, · 616 unmodified lines
22572259 if (!bo)
22582260 return bo_va;
22592261
2262+ dma_resv_assert_held(bo->tbo.base.resv);
22602263 if (amdgpu_dmabuf_is_xgmi_accessible(adev, bo)) {
22612264 bo_va->is_xgmi = true;
22622265 /* Power up XGMI if it can be potentially used */
@@ -2634,7 +2637,7 @@ void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket) · 371 unmodified lines
26342637 }
26352638
26362639 /**
2637− * amdgpu_vm_bo_rmv - remove a bo to a specific vm
2640+ * amdgpu_vm_bo_del - remove a bo from a specific vm
26382641 *
26392642 * @adev: amdgpu_device pointer
26402643 * @bo_va: requested bo_va
@@ -2643,7 +2646,7 @@ void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket) · 2 unmodified lines
26432646 *
26442647 * Object have to be reserved!
26452648 */
2646−void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
2649+void amdgpu_vm_bo_del(struct amdgpu_device *adev,
26472650 struct amdgpu_bo_va *bo_va)
26482651 {
26492652 struct amdgpu_bo_va_mapping *mapping, *next;
@@ -2651,7 +2654,10 @@ void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, · 1 unmodified line
26512654 struct amdgpu_vm *vm = bo_va->base.vm;
26522655 struct amdgpu_vm_bo_base **base;
26532656
2657+ dma_resv_assert_held(vm->root.bo->tbo.base.resv);
2658+
26542659 if (bo) {
2660+ dma_resv_assert_held(bo->tbo.base.resv);
26552661 if (bo->tbo.base.resv == vm->root.bo->tbo.base.resv)
26562662 vm->bulk_moveable = false;
26572663
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h+1−1
@@ -435,7 +435,7 @@ int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, · 434 unmodified lines
435435 struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
436436 uint64_t addr);
437437 void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket);
438−void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
438+void amdgpu_vm_bo_del(struct amdgpu_device *adev,
439439 struct amdgpu_bo_va *bo_va);
440440 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
441441 uint32_t fragment_size_default, unsigned max_level,
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c+22−38
@@ -96,9 +96,9 @@ static ssize_t amdgpu_mem_info_vram_used_show(struct device *dev, · 95 unmodified lines
9696 {
9797 struct drm_device *ddev = dev_get_drvdata(dev);
9898 struct amdgpu_device *adev = drm_to_adev(ddev);
99+ struct ttm_resource_manager *man = &adev->mman.vram_mgr.manager;
99100
100− return sysfs_emit(buf, "%llu\n",
101− amdgpu_vram_mgr_usage(&adev->mman.vram_mgr));
101+ return sysfs_emit(buf, "%llu\n", ttm_resource_manager_usage(man));
102102 }
103103
104104 /**
@@ -253,7 +253,9 @@ static void amdgpu_vram_mgr_do_reserve(struct ttm_resource_manager *man) · 148 unmodified lines
253253
254254 vis_usage = amdgpu_vram_mgr_vis_size(adev, &rsv->mm_node);
255255 atomic64_add(vis_usage, &mgr->vis_usage);
256− atomic64_add(rsv->mm_node.size << PAGE_SHIFT, &mgr->usage);
256+ spin_lock(&man->bdev->lru_lock);
257+ man->usage += rsv->mm_node.size << PAGE_SHIFT;
258+ spin_unlock(&man->bdev->lru_lock);
257259 list_move(&rsv->node, &mgr->reserved_pages);
258260 }
259261 }
@@ -281,7 +283,7 @@ int amdgpu_vram_mgr_reserve_range(struct amdgpu_vram_mgr *mgr, · 21 unmodified lines
281283 rsv->mm_node.size = size >> PAGE_SHIFT;
282284
283285 spin_lock(&mgr->lock);
284− list_add_tail(&mgr->reservations_pending, &rsv->node);
286+ list_add_tail(&rsv->node, &mgr->reservations_pending);
285287 amdgpu_vram_mgr_do_reserve(&mgr->manager);
286288 spin_unlock(&mgr->lock);
287289
@@ -378,19 +380,13 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_manager *man, · 90 unmodified lines
378380
379381 lpfn = place->lpfn;
380382 if (!lpfn)
381− lpfn = man->size;
383+ lpfn = man->size >> PAGE_SHIFT;
382384
383385 max_bytes = adev->gmc.mc_vram_size;
384386 if (tbo->type != ttm_bo_type_kernel)
385387 max_bytes -= AMDGPU_VM_RESERVED_VRAM;
386388
387− /* bail out quickly if there's likely not enough VRAM for this BO */
388389 mem_bytes = tbo->base.size;
389− if (atomic64_add_return(mem_bytes, &mgr->usage) > max_bytes) {
390− r = -ENOSPC;
391− goto error_sub;
392− }
393−
394390 if (place->flags & TTM_PL_FLAG_CONTIGUOUS) {
395391 pages_per_node = ~0ul;
396392 num_nodes = 1;
@@ -408,13 +404,17 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_manager *man, · 11 unmodified lines
408404
409405 node = kvmalloc(struct_size(node, mm_nodes, num_nodes),
410406 GFP_KERNEL | __GFP_ZERO);
411− if (!node) {
412− r = -ENOMEM;
413− goto error_sub;
414− }
407+ if (!node)
408+ return -ENOMEM;
415409
416410 ttm_resource_init(tbo, place, &node->base);
417411
412+ /* bail out quickly if there's likely not enough VRAM for this BO */
413+ if (ttm_resource_manager_usage(man) > max_bytes) {
414+ r = -ENOSPC;
415+ goto error_fini;
416+ }
417+
418418 mode = DRM_MM_INSERT_BEST;
419419 if (place->flags & TTM_PL_FLAG_TOPDOWN)
420420 mode = DRM_MM_INSERT_HIGH;
@@ -472,11 +472,10 @@ error_free: · 51 unmodified lines
472472 while (i--)
473473 drm_mm_remove_node(&node->mm_nodes[i]);
474474 spin_unlock(&mgr->lock);
475+error_fini:
475476 ttm_resource_fini(man, &node->base);
476477 kvfree(node);
477478
478−error_sub:
479− atomic64_sub(mem_bytes, &mgr->usage);
480479 return r;
481480 }
482481
@@ -494,7 +493,7 @@ static void amdgpu_vram_mgr_del(struct ttm_resource_manager *man, · 11 unmodified lines
494493 struct ttm_range_mgr_node *node = to_ttm_range_mgr_node(res);
495494 struct amdgpu_vram_mgr *mgr = to_vram_mgr(man);
496495 struct amdgpu_device *adev = to_amdgpu_device(mgr);
497− uint64_t usage = 0, vis_usage = 0;
496+ uint64_t vis_usage = 0;
498497 unsigned i, pages;
499498
500499 spin_lock(&mgr->lock);
@@ -503,13 +502,11 @@ static void amdgpu_vram_mgr_del(struct ttm_resource_manager *man, · 2 unmodified lines
503502 struct drm_mm_node *mm = &node->mm_nodes[i];
504503
505504 drm_mm_remove_node(mm);
506− usage += mm->size << PAGE_SHIFT;
507505 vis_usage += amdgpu_vram_mgr_vis_size(adev, mm);
508506 }
509507 amdgpu_vram_mgr_do_reserve(man);
510508 spin_unlock(&mgr->lock);
511509
512− atomic64_sub(usage, &mgr->usage);
513510 atomic64_sub(vis_usage, &mgr->vis_usage);
514511
515512 ttm_resource_fini(man, res);
@@ -627,18 +624,6 @@ void amdgpu_vram_mgr_free_sgt(struct device *dev, · 111 unmodified lines
627624 kfree(sgt);
628625 }
629626
630−/**
631− * amdgpu_vram_mgr_usage - how many bytes are used in this domain
632− *
633− * @mgr: amdgpu_vram_mgr pointer
634− *
635− * Returns how many bytes are used in this domain.
636− */
637−uint64_t amdgpu_vram_mgr_usage(struct amdgpu_vram_mgr *mgr)
638−{
639− return atomic64_read(&mgr->usage);
640−}
641−
642627 /**
643628 * amdgpu_vram_mgr_vis_usage - how many bytes are used in the visible part
644629 *
@@ -664,13 +649,12 @@ static void amdgpu_vram_mgr_debug(struct ttm_resource_manager *man, · 19 unmodified lines
664649 {
665650 struct amdgpu_vram_mgr *mgr = to_vram_mgr(man);
666651
652+ drm_printf(printer, " vis usage:%llu\n",
653+ amdgpu_vram_mgr_vis_usage(mgr));
654+
667655 spin_lock(&mgr->lock);
668656 drm_mm_print(&mgr->mm, printer);
669657 spin_unlock(&mgr->lock);
670−
671− drm_printf(printer, "man size:%llu pages, ram usage:%lluMB, vis usage:%lluMB\n",
672− man->size, amdgpu_vram_mgr_usage(mgr) >> 20,
673− amdgpu_vram_mgr_vis_usage(mgr) >> 20);
674658 }
675659
676660 static const struct ttm_resource_manager_func amdgpu_vram_mgr_func = {
@@ -692,11 +676,11 @@ int amdgpu_vram_mgr_init(struct amdgpu_device *adev) · 15 unmodified lines
692676 struct ttm_resource_manager *man = &mgr->manager;
693677
694678 ttm_resource_manager_init(man, &adev->mman.bdev,
695− adev->gmc.real_vram_size >> PAGE_SHIFT);
679+ adev->gmc.real_vram_size);
696680
697681 man->func = &amdgpu_vram_mgr_func;
698682
699− drm_mm_init(&mgr->mm, 0, man->size);
683+ drm_mm_init(&mgr->mm, 0, man->size >> PAGE_SHIFT);
700684 spin_lock_init(&mgr->lock);
701685 INIT_LIST_HEAD(&mgr->reservations_pending);
702686 INIT_LIST_HEAD(&mgr->reserved_pages);
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c+75−44
@@ -32,6 +32,8 @@ · 31 unmodified lines
3232 #include "wafl/wafl2_4_0_0_smn.h"
3333 #include "wafl/wafl2_4_0_0_sh_mask.h"
3434
35+#include "amdgpu_reset.h"
36+
3537 #define smnPCS_XGMI23_PCS_ERROR_STATUS 0x11a01210
3638 #define smnPCS_XGMI3X16_PCS_ERROR_STATUS 0x11a0020c
3739 #define smnPCS_GOPX1_PCS_ERROR_STATUS 0x12200210
@@ -227,6 +229,9 @@ static void amdgpu_xgmi_hive_release(struct kobject *kobj) · 189 unmodified lines
227229 struct amdgpu_hive_info *hive = container_of(
228230 kobj, struct amdgpu_hive_info, kobj);
229231
232+ amdgpu_reset_put_reset_domain(hive->reset_domain);
233+ hive->reset_domain = NULL;
234+
230235 mutex_destroy(&hive->hive_lock);
231236 kfree(hive);
232237 }
@@ -398,15 +403,35 @@ struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev) · 165 unmodified lines
398403 goto pro_end;
399404 }
400405
406+ /**
407+ * Avoid recreating reset domain when hive is reconstructed for the case
408+ * of reset the devices in the XGMI hive during probe for SRIOV
409+ * See https://www.spinics.net/lists/amd-gfx/msg58836.html
410+ */
411+ if (adev->reset_domain->type != XGMI_HIVE) {
412+ hive->reset_domain = amdgpu_reset_create_reset_domain(XGMI_HIVE, "amdgpu-reset-hive");
413+ if (!hive->reset_domain) {
414+ dev_err(adev->dev, "XGMI: failed initializing reset domain for xgmi hive\n");
415+ ret = -ENOMEM;
416+ kobject_put(&hive->kobj);
417+ kfree(hive);
418+ hive = NULL;
419+ goto pro_end;
420+ }
421+ } else {
422+ amdgpu_reset_get_reset_domain(adev->reset_domain);
423+ hive->reset_domain = adev->reset_domain;
424+ }
425+
401426 hive->hive_id = adev->gmc.xgmi.hive_id;
402427 INIT_LIST_HEAD(&hive->device_list);
403428 INIT_LIST_HEAD(&hive->node);
404429 mutex_init(&hive->hive_lock);
405− atomic_set(&hive->in_reset, 0);
406430 atomic_set(&hive->number_devices, 0);
407431 task_barrier_init(&hive->tb);
408432 hive->pstate = AMDGPU_XGMI_PSTATE_UNKNOWN;
409433 hive->hi_req_gpu = NULL;
434+
410435 /*
411436 * hive pstate on boot is high in vega20 so we have to go to low
412437 * pstate on after boot.
@@ -732,53 +757,22 @@ int amdgpu_xgmi_remove_device(struct amdgpu_device *adev) · 319 unmodified lines
732757 return psp_xgmi_terminate(&adev->psp);
733758 }
734759
735−static int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev)
760+static int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
736761 {
737− int r;
738− struct ras_ih_if ih_info = {
739− .cb = NULL,
740− };
741− struct ras_fs_if fs_info = {
742− .sysfs_name = "xgmi_wafl_err_count",
743− };
744−
745762 if (!adev->gmc.xgmi.supported ||
746763 adev->gmc.xgmi.num_physical_nodes == 0)
747764 return 0;
748765
749− adev->gmc.xgmi.ras_funcs->reset_ras_error_count(adev);
750−
751− if (!adev->gmc.xgmi.ras_if) {
752− adev->gmc.xgmi.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
753− if (!adev->gmc.xgmi.ras_if)
754− return -ENOMEM;
755− adev->gmc.xgmi.ras_if->block = AMDGPU_RAS_BLOCK__XGMI_WAFL;
756− adev->gmc.xgmi.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
757− adev->gmc.xgmi.ras_if->sub_block_index = 0;
758− }
759− ih_info.head = fs_info.head = *adev->gmc.xgmi.ras_if;
760− r = amdgpu_ras_late_init(adev, adev->gmc.xgmi.ras_if,
761− &fs_info, &ih_info);
762− if (r || !amdgpu_ras_is_supported(adev, adev->gmc.xgmi.ras_if->block)) {
763− kfree(adev->gmc.xgmi.ras_if);
764− adev->gmc.xgmi.ras_if = NULL;
765− }
766+ adev->gmc.xgmi.ras->ras_block.hw_ops->reset_ras_error_count(adev);
766767
767− return r;
768+ return amdgpu_ras_block_late_init(adev, ras_block);
768769 }
769770
770771 static void amdgpu_xgmi_ras_fini(struct amdgpu_device *adev)
771772 {
772773 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL) &&
773− adev->gmc.xgmi.ras_if) {
774− struct ras_common_if *ras_if = adev->gmc.xgmi.ras_if;
775− struct ras_ih_if ih_info = {
776− .cb = NULL,
777− };
778−
779− amdgpu_ras_late_fini(adev, ras_if, &ih_info);
780− kfree(ras_if);
781− }
774+ adev->gmc.xgmi.ras_if)
775+ amdgpu_ras_block_late_fini(adev, adev->gmc.xgmi.ras_if);
782776 }
783777
784778 uint64_t amdgpu_xgmi_get_relative_phy_addr(struct amdgpu_device *adev,
@@ -865,7 +859,7 @@ static int amdgpu_xgmi_query_pcs_error_status(struct amdgpu_device *adev, · 80 unmodified lines
865859 return 0;
866860 }
867861
868−static int amdgpu_xgmi_query_ras_error_count(struct amdgpu_device *adev,
862+static void amdgpu_xgmi_query_ras_error_count(struct amdgpu_device *adev,
869863 void *ras_error_status)
870864 {
871865 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
@@ -874,7 +868,7 @@ static int amdgpu_xgmi_query_ras_error_count(struct amdgpu_device *adev, · 2 unmodified lines
874868 uint32_t ue_cnt = 0, ce_cnt = 0;
875869
876870 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL))
877− return -EINVAL;
871+ return ;
878872
879873 err_data->ue_count = 0;
880874 err_data->ce_count = 0;
@@ -940,17 +934,54 @@ static int amdgpu_xgmi_query_ras_error_count(struct amdgpu_device *adev, · 59 unmodified lines
940934 break;
941935 }
942936
943− adev->gmc.xgmi.ras_funcs->reset_ras_error_count(adev);
937+ adev->gmc.xgmi.ras->ras_block.hw_ops->reset_ras_error_count(adev);
944938
945939 err_data->ue_count += ue_cnt;
946940 err_data->ce_count += ce_cnt;
941+}
947942
948− return 0;
943+/* Trigger XGMI/WAFL error */
944+static int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev, void *inject_if)
945+{
946+ int ret = 0;
947+ struct ta_ras_trigger_error_input *block_info =
948+ (struct ta_ras_trigger_error_input *)inject_if;
949+
950+ if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))
951+ dev_warn(adev->dev, "Failed to disallow df cstate");
952+
953+ if (amdgpu_dpm_allow_xgmi_power_down(adev, false))
954+ dev_warn(adev->dev, "Failed to disallow XGMI power down");
955+
956+ ret = psp_ras_trigger_error(&adev->psp, block_info);
957+
958+ if (amdgpu_ras_intr_triggered())
959+ return ret;
960+
961+ if (amdgpu_dpm_allow_xgmi_power_down(adev, true))
962+ dev_warn(adev->dev, "Failed to allow XGMI power down");
963+
964+ if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_ALLOW))
965+ dev_warn(adev->dev, "Failed to allow df cstate");
966+
967+ return ret;
949968 }
950969
951−const struct amdgpu_xgmi_ras_funcs xgmi_ras_funcs = {
952− .ras_late_init = amdgpu_xgmi_ras_late_init,
953− .ras_fini = amdgpu_xgmi_ras_fini,
970+struct amdgpu_ras_block_hw_ops xgmi_ras_hw_ops = {
954971 .query_ras_error_count = amdgpu_xgmi_query_ras_error_count,
955972 .reset_ras_error_count = amdgpu_xgmi_reset_ras_error_count,
973+ .ras_error_inject = amdgpu_ras_error_inject_xgmi,
974+};
975+
976+struct amdgpu_xgmi_ras xgmi_ras = {
977+ .ras_block = {
978+ .ras_comm = {
979+ .name = "xgmi_wafl",
980+ .block = AMDGPU_RAS_BLOCK__XGMI_WAFL,
981+ .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
982+ },
983+ .hw_ops = &xgmi_ras_hw_ops,
984+ .ras_late_init = amdgpu_xgmi_ras_late_init,
985+ .ras_fini = amdgpu_xgmi_ras_fini,
986+ },
956987 };
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h+4−3
@@ -24,7 +24,7 @@ · 23 unmodified lines
2424
2525 #include <drm/task_barrier.h>
2626 #include "amdgpu_psp.h"
27−
27+#include "amdgpu_ras.h"
2828
2929 struct amdgpu_hive_info {
3030 struct kobject kobj;
@@ -33,7 +33,6 @@ struct amdgpu_hive_info { · 2 unmodified lines
3333 struct list_head node;
3434 atomic_t number_devices;
3535 struct mutex hive_lock;
36− atomic_t in_reset;
3736 int hi_req_count;
3837 struct amdgpu_device *hi_req_gpu;
3938 struct task_barrier tb;
@@ -42,6 +41,8 @@ struct amdgpu_hive_info { · 2 unmodified lines
4241 AMDGPU_XGMI_PSTATE_MAX_VEGA20,
4342 AMDGPU_XGMI_PSTATE_UNKNOWN
4443 } pstate;
44+
45+ struct amdgpu_reset_domain *reset_domain;
4546 };
4647
4748 struct amdgpu_pcs_ras_field {
@@ -50,7 +51,7 @@ struct amdgpu_pcs_ras_field { · 2 unmodified lines
5051 uint32_t pcs_err_shift;
5152 };
5253
53−extern const struct amdgpu_xgmi_ras_funcs xgmi_ras_funcs;
54+extern struct amdgpu_xgmi_ras xgmi_ras;
5455 struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev);
5556 void amdgpu_put_xgmi_hive(struct amdgpu_hive_info *hive);
5657 int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive, struct amdgpu_device *adev);
drivers/gpu/drm/amd/amdgpu/athub_v1_0.c+7−6
@@ -68,12 +68,13 @@ int athub_v1_0_set_clockgating(struct amdgpu_device *adev, · 67 unmodified lines
6868 if (amdgpu_sriov_vf(adev))
6969 return 0;
7070
71− switch (adev->asic_type) {
72− case CHIP_VEGA10:
73− case CHIP_VEGA12:
74− case CHIP_VEGA20:
75− case CHIP_RAVEN:
76− case CHIP_RENOIR:
71+ switch (adev->ip_versions[ATHUB_HWIP][0]) {
72+ case IP_VERSION(9, 0, 0):
73+ case IP_VERSION(9, 1, 0):
74+ case IP_VERSION(9, 2, 0):
75+ case IP_VERSION(9, 3, 0):
76+ case IP_VERSION(9, 4, 0):
77+ case IP_VERSION(1, 5, 0):
7778 athub_update_medium_grain_clock_gating(adev,
7879 state == AMD_CG_STATE_GATE);
7980 athub_update_medium_grain_light_sleep(adev,
drivers/gpu/drm/amd/amdgpu/athub_v2_0.c+1−0
@@ -78,6 +78,7 @@ int athub_v2_0_set_clockgating(struct amdgpu_device *adev, · 77 unmodified lines
7878 return 0;
7979
8080 switch (adev->ip_versions[ATHUB_HWIP][0]) {
81+ case IP_VERSION(1, 3, 1):
8182 case IP_VERSION(2, 0, 0):
8283 case IP_VERSION(2, 0, 2):
8384 athub_v2_0_update_medium_grain_clock_gating(adev,
drivers/gpu/drm/amd/amdgpu/athub_v2_1.c+1−0
@@ -74,6 +74,7 @@ int athub_v2_1_set_clockgating(struct amdgpu_device *adev, · 73 unmodified lines
7474 case IP_VERSION(2, 1, 0):
7575 case IP_VERSION(2, 1, 1):
7676 case IP_VERSION(2, 1, 2):
77+ case IP_VERSION(2, 4, 0):
7778 athub_v2_1_update_medium_grain_clock_gating(adev, state == AMD_CG_STATE_GATE);
7879 athub_v2_1_update_medium_grain_light_sleep(adev, state == AMD_CG_STATE_GATE);
7980 break;
drivers/gpu/drm/amd/amdgpu/atom.c+3−1
@@ -25,6 +25,8 @@ · 24 unmodified lines
2525 #include <linux/module.h>
2626 #include <linux/sched.h>
2727 #include <linux/slab.h>
28+#include <linux/string_helpers.h>
29+
2830 #include <asm/unaligned.h>
2931
3032 #include <drm/drm_util.h>
@@ -740,7 +742,7 @@ static void atom_op_jump(atom_exec_context *ctx, int *ptr, int arg) · 709 unmodified lines
740742 break;
741743 }
742744 if (arg != ATOM_COND_ALWAYS)
743− SDEBUG(" taken: %s\n", execute ? "yes" : "no");
745+ SDEBUG(" taken: %s\n", str_yes_no(execute));
744746 SDEBUG(" target: 0x%04X\n", target);
745747 if (execute) {
746748 if (ctx->last_jump == (ctx->start + target)) {
drivers/gpu/drm/amd/amdgpu/cik.c+1−1
@@ -1719,7 +1719,7 @@ static void cik_program_aspm(struct amdgpu_device *adev) · 1718 unmodified lines
17191719 bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false;
17201720 bool disable_clkreq = false;
17211721
1722− if (amdgpu_aspm == 0)
1722+ if (!amdgpu_device_should_use_aspm(adev))
17231723 return;
17241724
17251725 if (pci_is_root_bus(adev->pdev->bus))
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c+3−1
@@ -2532,7 +2532,7 @@ static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode) · 2531 unmodified lines
25322532 break;
25332533 }
25342534 /* adjust pm to dpms */
2535− amdgpu_pm_compute_clocks(adev);
2535+ amdgpu_dpm_compute_clocks(adev);
25362536 }
25372537
25382538 static void dce_v10_0_crtc_prepare(struct drm_crtc *crtc)
@@ -2798,6 +2798,8 @@ static int dce_v10_0_sw_init(void *handle) · 259 unmodified lines
27982798 adev_to_drm(adev)->mode_config.preferred_depth = 24;
27992799 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
28002800
2801+ adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true;
2802+
28012803 adev_to_drm(adev)->mode_config.fb_base = adev->gmc.aper_base;
28022804
28032805 r = amdgpu_display_modeset_create_props(adev);
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c+3−1
@@ -2608,7 +2608,7 @@ static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode) · 2607 unmodified lines
26082608 break;
26092609 }
26102610 /* adjust pm to dpms */
2611− amdgpu_pm_compute_clocks(adev);
2611+ amdgpu_dpm_compute_clocks(adev);
26122612 }
26132613
26142614 static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc)
@@ -2916,6 +2916,8 @@ static int dce_v11_0_sw_init(void *handle) · 301 unmodified lines
29162916 adev_to_drm(adev)->mode_config.preferred_depth = 24;
29172917 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
29182918
2919+ adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true;
2920+
29192921 adev_to_drm(adev)->mode_config.fb_base = adev->gmc.aper_base;
29202922
29212923 r = amdgpu_display_modeset_create_props(adev);
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c+2−1
@@ -2424,7 +2424,7 @@ static void dce_v6_0_crtc_dpms(struct drm_crtc *crtc, int mode) · 2423 unmodified lines
24242424 break;
24252425 }
24262426 /* adjust pm to dpms */
2427− amdgpu_pm_compute_clocks(adev);
2427+ amdgpu_dpm_compute_clocks(adev);
24282428 }
24292429
24302430 static void dce_v6_0_crtc_prepare(struct drm_crtc *crtc)
@@ -2674,6 +2674,7 @@ static int dce_v6_0_sw_init(void *handle) · 243 unmodified lines
26742674 adev_to_drm(adev)->mode_config.max_height = 16384;
26752675 adev_to_drm(adev)->mode_config.preferred_depth = 24;
26762676 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
2677+ adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true;
26772678 adev_to_drm(adev)->mode_config.fb_base = adev->gmc.aper_base;
26782679
26792680 r = amdgpu_display_modeset_create_props(adev);
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c+3−1
@@ -2433,7 +2433,7 @@ static void dce_v8_0_crtc_dpms(struct drm_crtc *crtc, int mode) · 2432 unmodified lines
24332433 break;
24342434 }
24352435 /* adjust pm to dpms */
2436− amdgpu_pm_compute_clocks(adev);
2436+ amdgpu_dpm_compute_clocks(adev);
24372437 }
24382438
24392439 static void dce_v8_0_crtc_prepare(struct drm_crtc *crtc)
@@ -2695,6 +2695,8 @@ static int dce_v8_0_sw_init(void *handle) · 255 unmodified lines
26952695 adev_to_drm(adev)->mode_config.preferred_depth = 24;
26962696 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
26972697
2698+ adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true;
2699+
26982700 adev_to_drm(adev)->mode_config.fb_base = adev->gmc.aper_base;
26992701
27002702 r = amdgpu_display_modeset_create_props(adev);
drivers/gpu/drm/amd/amdgpu/df_v3_6.c+3−3
@@ -458,7 +458,7 @@ static int df_v3_6_pmc_add_cntr(struct amdgpu_device *adev, · 457 unmodified lines
458458
459459 #define DEFERRED_ARM_MASK (1 << 31)
460460 static int df_v3_6_pmc_set_deferred(struct amdgpu_device *adev,
461− int counter_idx, uint64_t config,
461+ uint64_t config, int counter_idx,
462462 bool is_deferred)
463463 {
464464
@@ -476,8 +476,8 @@ static int df_v3_6_pmc_set_deferred(struct amdgpu_device *adev, · 11 unmodified lines
476476 }
477477
478478 static bool df_v3_6_pmc_is_deferred(struct amdgpu_device *adev,
479− int counter_idx,
480− uint64_t config)
479+ uint64_t config,
480+ int counter_idx)
481481 {
482482 return (df_v3_6_pmc_has_counter(adev, config, counter_idx) &&
483483 (adev->df_perfmon_config_assign_mask[counter_idx]
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c+177−157
@@ -56,10 +56,6 @@ · 55 unmodified lines
5656 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 1
5757 #define GFX10_MEC_HPD_SIZE 2048
5858
59−#define RLCG_VFGATE_DISABLED 0x4000000
60−#define RLCG_WRONG_OPERATION_TYPE 0x2000000
61−#define RLCG_NOT_IN_RANGE 0x1000000
62−
6359 #define F32_CE_PROGRAM_RAM_SIZE 65536
6460 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
6561
@@ -110,6 +106,12 @@ · 44 unmodified lines
110106 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX 1
111107 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh 0x0026
112108 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX 1
109+
110+#define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6 0x002d
111+#define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6_BASE_IDX 1
112+#define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6 0x002e
113+#define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6_BASE_IDX 1
114+
113115 #define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441
114116 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1
115117 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261
@@ -180,14 +182,6 @@ · 64 unmodified lines
180182 #define mmRLC_SPARE_INT_0_Sienna_Cichlid 0x4ca5
181183 #define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX 1
182184
183−#define GFX_RLCG_GC_WRITE_OLD (0x8 << 28)
184−#define GFX_RLCG_GC_WRITE (0x0 << 28)
185−#define GFX_RLCG_GC_READ (0x1 << 28)
186−#define GFX_RLCG_MMHUB_WRITE (0x2 << 28)
187−
188−#define RLCG_ERROR_REPORT_ENABLED(adev) \
189− (amdgpu_sriov_reg_indirect_mmhub(adev) || amdgpu_sriov_reg_indirect_gc(adev))
190−
191185 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
192186 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
193187 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
@@ -270,6 +264,20 @@ MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin"); · 76 unmodified lines
270264 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin");
271265 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin");
272266
267+MODULE_FIRMWARE("amdgpu/gc_10_3_6_ce.bin");
268+MODULE_FIRMWARE("amdgpu/gc_10_3_6_pfp.bin");
269+MODULE_FIRMWARE("amdgpu/gc_10_3_6_me.bin");
270+MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec.bin");
271+MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec2.bin");
272+MODULE_FIRMWARE("amdgpu/gc_10_3_6_rlc.bin");
273+
274+MODULE_FIRMWARE("amdgpu/gc_10_3_7_ce.bin");
275+MODULE_FIRMWARE("amdgpu/gc_10_3_7_pfp.bin");
276+MODULE_FIRMWARE("amdgpu/gc_10_3_7_me.bin");
277+MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin");
278+MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin");
279+MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin");
280+
273281 static const struct soc15_reg_golden golden_settings_gc_10_1[] =
274282 {
275283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
@@ -1463,143 +1471,6 @@ static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = · 1187 unmodified lines
14631471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000)
14641472 };
14651473
1466−static bool gfx_v10_get_rlcg_flag(struct amdgpu_device *adev, u32 acc_flags, u32 hwip,
1467− int write, u32 *rlcg_flag)
1468−{
1469− switch (hwip) {
1470− case GC_HWIP:
1471− if (amdgpu_sriov_reg_indirect_gc(adev)) {
1472− *rlcg_flag = write ? GFX_RLCG_GC_WRITE : GFX_RLCG_GC_READ;
1473−
1474− return true;
1475− /* only in new version, AMDGPU_REGS_NO_KIQ and AMDGPU_REGS_RLC enabled simultaneously */
1476− } else if ((acc_flags & AMDGPU_REGS_RLC) && !(acc_flags & AMDGPU_REGS_NO_KIQ)) {
1477− *rlcg_flag = GFX_RLCG_GC_WRITE_OLD;
1478−
1479− return true;
1480− }
1481−
1482− break;
1483− case MMHUB_HWIP:
1484− if (amdgpu_sriov_reg_indirect_mmhub(adev) &&
1485− (acc_flags & AMDGPU_REGS_RLC) && write) {
1486− *rlcg_flag = GFX_RLCG_MMHUB_WRITE;
1487− return true;
1488− }
1489−
1490− break;
1491− default:
1492− DRM_DEBUG("Not program register by RLCG\n");
1493− }
1494−
1495− return false;
1496−}
1497−
1498−static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32_t flag)
1499−{
1500− static void *scratch_reg0;
1501− static void *scratch_reg1;
1502− static void *scratch_reg2;
1503− static void *scratch_reg3;
1504− static void *spare_int;
1505− static uint32_t grbm_cntl;
1506− static uint32_t grbm_idx;
1507− uint32_t i = 0;
1508− uint32_t retries = 50000;
1509− u32 ret = 0;
1510− u32 tmp;
1511−
1512− scratch_reg0 = adev->rmmio +
1513− (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0) * 4;
1514− scratch_reg1 = adev->rmmio +
1515− (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1) * 4;
1516− scratch_reg2 = adev->rmmio +
1517− (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG2) * 4;
1518− scratch_reg3 = adev->rmmio +
1519− (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3) * 4;
1520−
1521− if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) {
1522− spare_int = adev->rmmio +
1523− (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX]
1524− + mmRLC_SPARE_INT_0_Sienna_Cichlid) * 4;
1525− } else {
1526− spare_int = adev->rmmio +
1527− (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT) * 4;
1528− }
1529−
1530− grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL;
1531− grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX;
1532−
1533− if (offset == grbm_cntl || offset == grbm_idx) {
1534− if (offset == grbm_cntl)
1535− writel(v, scratch_reg2);
1536− else if (offset == grbm_idx)
1537− writel(v, scratch_reg3);
1538−
1539− writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));
1540− } else {
1541− writel(v, scratch_reg0);
1542− writel(offset | flag, scratch_reg1);
1543− writel(1, spare_int);
1544−
1545− for (i = 0; i < retries; i++) {
1546− tmp = readl(scratch_reg1);
1547− if (!(tmp & flag))
1548− break;
1549−
1550− udelay(10);
1551− }
1552−
1553− if (i >= retries) {
1554− if (RLCG_ERROR_REPORT_ENABLED(adev)) {
1555− if (tmp & RLCG_VFGATE_DISABLED)
1556− pr_err("The vfgate is disabled, program reg:0x%05x failed!\n", offset);
1557− else if (tmp & RLCG_WRONG_OPERATION_TYPE)
1558− pr_err("Wrong operation type, program reg:0x%05x failed!\n", offset);
1559− else if (tmp & RLCG_NOT_IN_RANGE)
1560− pr_err("The register is not in range, program reg:0x%05x failed!\n", offset);
1561− else
1562− pr_err("Unknown error type, program reg:0x%05x failed!\n", offset);
1563− } else
1564− pr_err("timeout: rlcg program reg:0x%05x failed!\n", offset);
1565− }
1566− }
1567−
1568− ret = readl(scratch_reg0);
1569−
1570− return ret;
1571−}
1572−
1573−static void gfx_v10_sriov_wreg(struct amdgpu_device *adev, u32 offset, u32 value, u32 acc_flags, u32 hwip)
1574−{
1575− u32 rlcg_flag;
1576−
1577− if (!amdgpu_sriov_runtime(adev) &&
1578− gfx_v10_get_rlcg_flag(adev, acc_flags, hwip, 1, &rlcg_flag)) {
1579− gfx_v10_rlcg_rw(adev, offset, value, rlcg_flag);
1580− return;
1581− }
1582−
1583− if (acc_flags & AMDGPU_REGS_NO_KIQ)
1584− WREG32_NO_KIQ(offset, value);
1585− else
1586− WREG32(offset, value);
1587−}
1588−
1589−static u32 gfx_v10_sriov_rreg(struct amdgpu_device *adev, u32 offset, u32 acc_flags, u32 hwip)
1590−{
1591− u32 rlcg_flag;
1592−
1593− if (!amdgpu_sriov_runtime(adev) &&
1594− gfx_v10_get_rlcg_flag(adev, acc_flags, hwip, 0, &rlcg_flag))
1595− return gfx_v10_rlcg_rw(adev, offset, 0, rlcg_flag);
1596−
1597− if (acc_flags & AMDGPU_REGS_NO_KIQ)
1598− return RREG32_NO_KIQ(offset);
1599− else
1600− return RREG32(offset);
1601−}
1602−
16031474 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
16041475 {
16051476 /* Pending on emulation bring up */
@@ -3557,6 +3428,57 @@ static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = · 1951 unmodified lines
35573428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000)
35583429 };
35593430
3431+static const struct soc15_reg_golden golden_settings_gc_10_3_6[] =
3432+{
3433+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3434+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x00000044),
3435+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3436+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3437+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3438+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000042),
3439+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1ffff, 0x00000500),
3440+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x00000044),
3441+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3442+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3443+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3444+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3445+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3446+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3447+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3448+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3449+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3450+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3451+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3452+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),
3453+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3454+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3455+};
3456+
3457+static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = {
3458+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3459+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3460+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3461+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3462+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3463+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000041),
3464+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1ffff, 0x00000500),
3465+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3466+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3467+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3468+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),
3469+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),
3470+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3471+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3472+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3473+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf000003f, 0x01200007),
3474+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3475+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3476+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3477+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),
3478+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3479+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3480+};
3481+
35603482 #define DEFAULT_SH_MEM_CONFIG \
35613483 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
35623484 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
@@ -3790,10 +3712,21 @@ static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) · 227 unmodified lines
37903712 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_5));
37913713 break;
37923714 case IP_VERSION(10, 1, 3):
3715+ case IP_VERSION(10, 1, 4):
37933716 soc15_program_register_sequence(adev,
37943717 golden_settings_gc_10_0_cyan_skillfish,
37953718 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish));
37963719 break;
3720+ case IP_VERSION(10, 3, 6):
3721+ soc15_program_register_sequence(adev,
3722+ golden_settings_gc_10_3_6,
3723+ (const u32)ARRAY_SIZE(golden_settings_gc_10_3_6));
3724+ break;
3725+ case IP_VERSION(10, 3, 7):
3726+ soc15_program_register_sequence(adev,
3727+ golden_settings_gc_10_3_7,
3728+ (const u32)ARRAY_SIZE(golden_settings_gc_10_3_7));
3729+ break;
37973730 default:
37983731 break;
37993732 }
@@ -3968,6 +3901,7 @@ static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev) · 168 unmodified lines
39683901 case IP_VERSION(10, 1, 2):
39693902 case IP_VERSION(10, 1, 1):
39703903 case IP_VERSION(10, 1, 3):
3904+ case IP_VERSION(10, 1, 4):
39713905 if ((adev->gfx.me_fw_version >= 0x00000046) &&
39723906 (adev->gfx.me_feature_version >= 27) &&
39733907 (adev->gfx.pfp_fw_version >= 0x00000068) &&
@@ -3981,7 +3915,9 @@ static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev) · 7 unmodified lines
39813915 case IP_VERSION(10, 3, 1):
39823916 case IP_VERSION(10, 3, 4):
39833917 case IP_VERSION(10, 3, 5):
3918+ case IP_VERSION(10, 3, 6):
39843919 case IP_VERSION(10, 3, 3):
3920+ case IP_VERSION(10, 3, 7):
39853921 adev->gfx.cp_fw_write_wait = true;
39863922 break;
39873923 default:
@@ -4102,12 +4038,19 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) · 114 unmodified lines
41024038 case IP_VERSION(10, 3, 3):
41034039 chip_name = "yellow_carp";
41044040 break;
4041+ case IP_VERSION(10, 3, 6):
4042+ chip_name = "gc_10_3_6";
4043+ break;
41054044 case IP_VERSION(10, 1, 3):
4045+ case IP_VERSION(10, 1, 4):
41064046 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2)
41074047 chip_name = "cyan_skillfish2";
41084048 else
41094049 chip_name = "cyan_skillfish";
41104050 break;
4051+ case IP_VERSION(10, 3, 7):
4052+ chip_name = "gc_10_3_7";
4053+ break;
41114054 default:
41124055 BUG();
41134056 }
@@ -4448,6 +4391,30 @@ static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev) · 334 unmodified lines
44484391 (void **)&adev->gfx.rlc.cp_table_ptr);
44494392 }
44504393
4394+static void gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev)
4395+{
4396+ struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
4397+
4398+ reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl;
4399+ reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
4400+ reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1);
4401+ reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2);
4402+ reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3);
4403+ reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL);
4404+ reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX);
4405+ switch (adev->ip_versions[GC_HWIP][0]) {
4406+ case IP_VERSION(10, 3, 0):
4407+ reg_access_ctrl->spare_int =
4408+ SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT_0_Sienna_Cichlid);
4409+ break;
4410+ default:
4411+ reg_access_ctrl->spare_int =
4412+ SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT);
4413+ break;
4414+ }
4415+ adev->gfx.rlc.rlcg_reg_access_supported = true;
4416+}
4417+
44514418 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
44524419 {
44534420 const struct cs_section_def *cs_data;
@@ -4468,6 +4435,7 @@ static int gfx_v10_0_rlc_init(struct amdgpu_device *adev) · 14 unmodified lines
44684435 if (adev->gfx.rlc.funcs->update_spm_vmid)
44694436 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
44704437
4438+
44714439 return 0;
44724440 }
44734441
@@ -4678,7 +4646,9 @@ static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) · 204 unmodified lines
46784646 case IP_VERSION(10, 3, 1):
46794647 case IP_VERSION(10, 3, 4):
46804648 case IP_VERSION(10, 3, 5):
4649+ case IP_VERSION(10, 3, 6):
46814650 case IP_VERSION(10, 3, 3):
4651+ case IP_VERSION(10, 3, 7):
46824652 adev->gfx.config.max_hw_contexts = 8;
46834653 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
46844654 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
@@ -4689,6 +4659,7 @@ static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) · 4 unmodified lines
46894659 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
46904660 break;
46914661 case IP_VERSION(10, 1, 3):
4662+ case IP_VERSION(10, 1, 4):
46924663 adev->gfx.config.max_hw_contexts = 8;
46934664 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
46944665 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
@@ -4801,6 +4772,7 @@ static int gfx_v10_0_sw_init(void *handle) · 106 unmodified lines
48014772 case IP_VERSION(10, 1, 1):
48024773 case IP_VERSION(10, 1, 2):
48034774 case IP_VERSION(10, 1, 3):
4775+ case IP_VERSION(10, 1, 4):
48044776 adev->gfx.me.num_me = 1;
48054777 adev->gfx.me.num_pipe_per_me = 1;
48064778 adev->gfx.me.num_queue_per_pipe = 1;
@@ -4813,7 +4785,9 @@ static int gfx_v10_0_sw_init(void *handle) · 6 unmodified lines
48134785 case IP_VERSION(10, 3, 1):
48144786 case IP_VERSION(10, 3, 4):
48154787 case IP_VERSION(10, 3, 5):
4788+ case IP_VERSION(10, 3, 6):
48164789 case IP_VERSION(10, 3, 3):
4790+ case IP_VERSION(10, 3, 7):
48174791 adev->gfx.me.num_me = 1;
48184792 adev->gfx.me.num_pipe_per_me = 1;
48194793 adev->gfx.me.num_queue_per_pipe = 1;
@@ -4865,10 +4839,14 @@ static int gfx_v10_0_sw_init(void *handle) · 45 unmodified lines
48654839 if (r)
48664840 return r;
48674841
4868− r = gfx_v10_0_rlc_init(adev);
4869− if (r) {
4870− DRM_ERROR("Failed to init rlc BOs!\n");
4871− return r;
4842+ if (adev->gfx.rlc.funcs) {
4843+ if (adev->gfx.rlc.funcs->init) {
4844+ r = adev->gfx.rlc.funcs->init(adev);
4845+ if (r) {
4846+ dev_err(adev->dev, "Failed to init rlc BOs!\n");
4847+ return r;
4848+ }
4849+ }
48724850 }
48734851
48744852 r = gfx_v10_0_mec_init(adev);
@@ -5047,7 +5025,8 @@ static void gfx_v10_0_setup_rb(struct amdgpu_device *adev) · 172 unmodified lines
50475025 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
50485026 bitmap = i * adev->gfx.config.max_sh_per_se + j;
50495027 if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) ||
5050− (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3))) &&
5028+ (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) ||
5029+ (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 6))) &&
50515030 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
50525031 continue;
50535032 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
@@ -6321,7 +6300,9 @@ static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, · 1267 unmodified lines
63216300 case IP_VERSION(10, 3, 1):
63226301 case IP_VERSION(10, 3, 4):
63236302 case IP_VERSION(10, 3, 5):
6303+ case IP_VERSION(10, 3, 6):
63246304 case IP_VERSION(10, 3, 3):
6305+ case IP_VERSION(10, 3, 7):
63256306 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
63266307 DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
63276308 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
@@ -6458,7 +6439,9 @@ static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) · 130 unmodified lines
64586439 case IP_VERSION(10, 3, 1):
64596440 case IP_VERSION(10, 3, 4):
64606441 case IP_VERSION(10, 3, 5):
6442+ case IP_VERSION(10, 3, 6):
64616443 case IP_VERSION(10, 3, 3):
6444+ case IP_VERSION(10, 3, 7):
64626445 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
64636446 break;
64646447 default:
@@ -6472,7 +6455,9 @@ static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) · 7 unmodified lines
64726455 case IP_VERSION(10, 3, 1):
64736456 case IP_VERSION(10, 3, 4):
64746457 case IP_VERSION(10, 3, 5):
6458+ case IP_VERSION(10, 3, 6):
64756459 case IP_VERSION(10, 3, 3):
6460+ case IP_VERSION(10, 3, 7):
64766461 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
64776462 (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
64786463 CP_MEC_CNTL__MEC_ME2_HALT_MASK));
@@ -6570,6 +6555,7 @@ static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring) · 91 unmodified lines
65706555 case IP_VERSION(10, 3, 1):
65716556 case IP_VERSION(10, 3, 4):
65726557 case IP_VERSION(10, 3, 5):
6558+ case IP_VERSION(10, 3, 6):
65736559 case IP_VERSION(10, 3, 3):
65746560 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
65756561 tmp &= 0xffffff00;
@@ -7300,6 +7286,8 @@ static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev) · 724 unmodified lines
73007286 break;
73017287 case IP_VERSION(10, 3, 1):
73027288 case IP_VERSION(10, 3, 3):
7289+ case IP_VERSION(10, 3, 6):
7290+ case IP_VERSION(10, 3, 7):
73037291 return true;
73047292 default:
73057293 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
@@ -7334,7 +7322,9 @@ static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev) · 28 unmodified lines
73347322 case IP_VERSION(10, 3, 1):
73357323 case IP_VERSION(10, 3, 4):
73367324 case IP_VERSION(10, 3, 5):
7325+ case IP_VERSION(10, 3, 6):
73377326 case IP_VERSION(10, 3, 3):
7327+ case IP_VERSION(10, 3, 7):
73387328 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
73397329 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
73407330 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
@@ -7654,6 +7644,7 @@ static int gfx_v10_0_soft_reset(void *handle) · 313 unmodified lines
76547644 case IP_VERSION(10, 3, 1):
76557645 case IP_VERSION(10, 3, 4):
76567646 case IP_VERSION(10, 3, 5):
7647+ case IP_VERSION(10, 3, 6):
76577648 case IP_VERSION(10, 3, 3):
76587649 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
76597650 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
@@ -7721,6 +7712,21 @@ static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev) · 61 unmodified lines
77217712 preempt_enable();
77227713 clock = clock_lo | (clock_hi << 32ULL);
77237714 break;
7715+ case IP_VERSION(10, 3, 6):
7716+ preempt_disable();
7717+ clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);
7718+ clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);
7719+ hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);
7720+ /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7721+ * roughly every 42 seconds.
7722+ */
7723+ if (hi_check != clock_hi) {
7724+ clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);
7725+ clock_hi = hi_check;
7726+ }
7727+ preempt_enable();
7728+ clock = clock_lo | (clock_hi << 32ULL);
7729+ break;
77247730 default:
77257731 preempt_disable();
77267732 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
@@ -7778,6 +7784,7 @@ static int gfx_v10_0_early_init(void *handle) · 51 unmodified lines
77787784 case IP_VERSION(10, 1, 1):
77797785 case IP_VERSION(10, 1, 2):
77807786 case IP_VERSION(10, 1, 3):
7787+ case IP_VERSION(10, 1, 4):
77817788 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
77827789 break;
77837790 case IP_VERSION(10, 3, 0):
@@ -7785,7 +7792,9 @@ static int gfx_v10_0_early_init(void *handle) · 1 unmodified line
77857792 case IP_VERSION(10, 3, 1):
77867793 case IP_VERSION(10, 3, 4):
77877794 case IP_VERSION(10, 3, 5):
7795+ case IP_VERSION(10, 3, 6):
77887796 case IP_VERSION(10, 3, 3):
7797+ case IP_VERSION(10, 3, 7):
77897798 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
77907799 break;
77917800 default:
@@ -7801,6 +7810,9 @@ static int gfx_v10_0_early_init(void *handle) · 9 unmodified lines
78017810 gfx_v10_0_set_gds_init(adev);
78027811 gfx_v10_0_set_rlc_funcs(adev);
78037812
7813+ /* init rlcg reg access ctrl */
7814+ gfx_v10_0_init_rlcg_reg_access_ctrl(adev);
7815+
78047816 return 0;
78057817 }
78067818
@@ -7843,6 +7855,7 @@ static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev) · 36 unmodified lines
78437855 case IP_VERSION(10, 3, 1):
78447856 case IP_VERSION(10, 3, 4):
78457857 case IP_VERSION(10, 3, 5):
7858+ case IP_VERSION(10, 3, 6):
78467859 case IP_VERSION(10, 3, 3):
78477860 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
78487861
@@ -7879,6 +7892,7 @@ static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev) · 30 unmodified lines
78797892 case IP_VERSION(10, 3, 1):
78807893 case IP_VERSION(10, 3, 4):
78817894 case IP_VERSION(10, 3, 5):
7895+ case IP_VERSION(10, 3, 6):
78827896 case IP_VERSION(10, 3, 3):
78837897 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
78847898 break;
@@ -8333,6 +8347,7 @@ static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable) · 448 unmodified lines
83338347 switch (adev->ip_versions[GC_HWIP][0]) {
83348348 case IP_VERSION(10, 3, 1):
83358349 case IP_VERSION(10, 3, 3):
8350+ case IP_VERSION(10, 3, 6):
83368351 data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
83378352 WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
83388353 break;
@@ -8377,8 +8392,6 @@ static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = { · 38 unmodified lines
83778392 .reset = gfx_v10_0_rlc_reset,
83788393 .start = gfx_v10_0_rlc_start,
83798394 .update_spm_vmid = gfx_v10_0_update_spm_vmid,
8380− .sriov_wreg = gfx_v10_sriov_wreg,
8381− .sriov_rreg = gfx_v10_sriov_rreg,
83828395 .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
83838396 };
83848397
@@ -8403,6 +8416,7 @@ static int gfx_v10_0_set_powergating_state(void *handle, · 18 unmodified lines
84038416 break;
84048417 case IP_VERSION(10, 3, 1):
84058418 case IP_VERSION(10, 3, 3):
8419+ case IP_VERSION(10, 3, 6):
84068420 gfx_v10_cntl_pg(adev, enable);
84078421 amdgpu_gfx_off_ctrl(adev, enable);
84088422 break;
@@ -8429,6 +8443,7 @@ static int gfx_v10_0_set_clockgating_state(void *handle, · 20 unmodified lines
84298443 case IP_VERSION(10, 3, 1):
84308444 case IP_VERSION(10, 3, 4):
84318445 case IP_VERSION(10, 3, 5):
8446+ case IP_VERSION(10, 3, 6):
84328447 case IP_VERSION(10, 3, 3):
84338448 gfx_v10_0_update_gfx_clock_gating(adev,
84348449 state == AMD_CG_STATE_GATE);
@@ -9537,11 +9552,14 @@ static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev) · 1102 unmodified lines
95379552 case IP_VERSION(10, 1, 10):
95389553 case IP_VERSION(10, 1, 1):
95399554 case IP_VERSION(10, 1, 3):
9555+ case IP_VERSION(10, 1, 4):
95409556 case IP_VERSION(10, 3, 2):
95419557 case IP_VERSION(10, 3, 1):
95429558 case IP_VERSION(10, 3, 4):
95439559 case IP_VERSION(10, 3, 5):
9560+ case IP_VERSION(10, 3, 6):
95449561 case IP_VERSION(10, 3, 3):
9562+ case IP_VERSION(10, 3, 7):
95459563 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
95469564 break;
95479565 case IP_VERSION(10, 1, 2):
@@ -9634,7 +9652,9 @@ static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, · 86 unmodified lines
96349652 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
96359653 bitmap = i * adev->gfx.config.max_sh_per_se + j;
96369654 if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) ||
9637− (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3))) &&
9655+ (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) ||
9656+ (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 6)) ||
9657+ (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 7))) &&
96389658 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
96399659 continue;
96409660 mask = 1;
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c+72−162
@@ -63,13 +63,6 @@ · 62 unmodified lines
6363 #define mmGCEA_PROBE_MAP 0x070c
6464 #define mmGCEA_PROBE_MAP_BASE_IDX 0
6565
66−#define GFX9_RLCG_GC_WRITE_OLD (0x8 << 28)
67−#define GFX9_RLCG_GC_WRITE (0x0 << 28)
68−#define GFX9_RLCG_GC_READ (0x1 << 28)
69−#define GFX9_RLCG_VFGATE_DISABLED 0x4000000
70−#define GFX9_RLCG_WRONG_OPERATION_TYPE 0x2000000
71−#define GFX9_RLCG_NOT_IN_RANGE 0x1000000
72−
7366 MODULE_FIRMWARE("amdgpu/vega10_ce.bin");
7467 MODULE_FIRMWARE("amdgpu/vega10_pfp.bin");
7568 MODULE_FIRMWARE("amdgpu/vega10_me.bin");
@@ -746,128 +739,6 @@ static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] = · 670 unmodified lines
746739 mmRLC_SRM_INDEX_CNTL_DATA_7 - mmRLC_SRM_INDEX_CNTL_DATA_0,
747740 };
748741
749−static u32 gfx_v9_0_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32_t flag)
750−{
751− static void *scratch_reg0;
752− static void *scratch_reg1;
753− static void *scratch_reg2;
754− static void *scratch_reg3;
755− static void *spare_int;
756− static uint32_t grbm_cntl;
757− static uint32_t grbm_idx;
758− uint32_t i = 0;
759− uint32_t retries = 50000;
760− u32 ret = 0;
761− u32 tmp;
762−
763− scratch_reg0 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0)*4;
764− scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4;
765− scratch_reg2 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG2_BASE_IDX] + mmSCRATCH_REG2)*4;
766− scratch_reg3 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG3_BASE_IDX] + mmSCRATCH_REG3)*4;
767− spare_int = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT)*4;
768−
769− grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL;
770− grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX;
771−
772− if (offset == grbm_cntl || offset == grbm_idx) {
773− if (offset == grbm_cntl)
774− writel(v, scratch_reg2);
775− else if (offset == grbm_idx)
776− writel(v, scratch_reg3);
777−
778− writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));
779− } else {
780− /*
781− * SCRATCH_REG0 = read/write value
782− * SCRATCH_REG1[30:28] = command
783− * SCRATCH_REG1[19:0] = address in dword
784− * SCRATCH_REG1[26:24] = Error reporting
785− */
786− writel(v, scratch_reg0);
787− writel(offset | flag, scratch_reg1);
788− writel(1, spare_int);
789−
790− for (i = 0; i < retries; i++) {
791− tmp = readl(scratch_reg1);
792− if (!(tmp & flag))
793− break;
794−
795− udelay(10);
796− }
797−
798− if (i >= retries) {
799− if (amdgpu_sriov_reg_indirect_gc(adev)) {
800− if (tmp & GFX9_RLCG_VFGATE_DISABLED)
801− pr_err("The vfgate is disabled, program reg:0x%05x failed!\n", offset);
802− else if (tmp & GFX9_RLCG_WRONG_OPERATION_TYPE)
803− pr_err("Wrong operation type, program reg:0x%05x failed!\n", offset);
804− else if (tmp & GFX9_RLCG_NOT_IN_RANGE)
805− pr_err("The register is not in range, program reg:0x%05x failed!\n", offset);
806− else
807− pr_err("Unknown error type, program reg:0x%05x failed!\n", offset);
808− } else
809− pr_err("timeout: rlcg program reg:0x%05x failed!\n", offset);
810− }
811− }
812−
813− ret = readl(scratch_reg0);
814−
815− return ret;
816−}
817−
818−static bool gfx_v9_0_get_rlcg_flag(struct amdgpu_device *adev, u32 acc_flags, u32 hwip,
819− int write, u32 *rlcg_flag)
820−{
821−
822− switch (hwip) {
823− case GC_HWIP:
824− if (amdgpu_sriov_reg_indirect_gc(adev)) {
825− *rlcg_flag = write ? GFX9_RLCG_GC_WRITE : GFX9_RLCG_GC_READ;
826−
827− return true;
828− /* only in new version, AMDGPU_REGS_NO_KIQ and AMDGPU_REGS_RLC enabled simultaneously */
829− } else if ((acc_flags & AMDGPU_REGS_RLC) && !(acc_flags & AMDGPU_REGS_NO_KIQ) && write) {
830− *rlcg_flag = GFX9_RLCG_GC_WRITE_OLD;
831− return true;
832− }
833−
834− break;
835− default:
836− return false;
837− }
838−
839− return false;
840−}
841−
842−static u32 gfx_v9_0_sriov_rreg(struct amdgpu_device *adev, u32 offset, u32 acc_flags, u32 hwip)
843−{
844− u32 rlcg_flag;
845−
846− if (!amdgpu_sriov_runtime(adev) && gfx_v9_0_get_rlcg_flag(adev, acc_flags, hwip, 0, &rlcg_flag))
847− return gfx_v9_0_rlcg_rw(adev, offset, 0, rlcg_flag);
848−
849− if (acc_flags & AMDGPU_REGS_NO_KIQ)
850− return RREG32_NO_KIQ(offset);
851− else
852− return RREG32(offset);
853−}
854−
855−static void gfx_v9_0_sriov_wreg(struct amdgpu_device *adev, u32 offset,
856− u32 value, u32 acc_flags, u32 hwip)
857−{
858− u32 rlcg_flag;
859−
860− if (!amdgpu_sriov_runtime(adev) && gfx_v9_0_get_rlcg_flag(adev, acc_flags, hwip, 1, &rlcg_flag)) {
861− gfx_v9_0_rlcg_rw(adev, offset, value, rlcg_flag);
862− return;
863− }
864−
865− if (acc_flags & AMDGPU_REGS_NO_KIQ)
866− WREG32_NO_KIQ(offset, value);
867− else
868− WREG32(offset, value);
869−}
870−
871742 #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
872743 #define VEGA12_GB_ADDR_CONFIG_GOLDEN 0x24104041
873744 #define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042
@@ -882,7 +753,7 @@ static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, · 8 unmodified lines
882753 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
883754 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring);
884755 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring);
885−static int gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev,
756+static void gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev,
886757 void *ras_error_status);
887758 static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev,
888759 void *inject_if);
@@ -2008,6 +1879,21 @@ static int gfx_v9_0_cp_jump_table_num(struct amdgpu_device *adev) · 1119 unmodified lines
20081879 return 4;
20091880 }
20101881
1882+static void gfx_v9_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev)
1883+{
1884+ struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
1885+
1886+ reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl;
1887+ reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
1888+ reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1);
1889+ reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2);
1890+ reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3);
1891+ reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL);
1892+ reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX);
1893+ reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT);
1894+ adev->gfx.rlc.rlcg_reg_access_supported = true;
1895+}
1896+
20111897 static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
20121898 {
20131899 const struct cs_section_def *cs_data;
@@ -2197,12 +2083,16 @@ static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = { · 183 unmodified lines
21972083 .select_me_pipe_q = &gfx_v9_0_select_me_pipe_q,
21982084 };
21992085
2200−static const struct amdgpu_gfx_ras_funcs gfx_v9_0_ras_funcs = {
2201− .ras_late_init = amdgpu_gfx_ras_late_init,
2202− .ras_fini = amdgpu_gfx_ras_fini,
2203− .ras_error_inject = &gfx_v9_0_ras_error_inject,
2204− .query_ras_error_count = &gfx_v9_0_query_ras_error_count,
2205− .reset_ras_error_count = &gfx_v9_0_reset_ras_error_count,
2086+const struct amdgpu_ras_block_hw_ops gfx_v9_0_ras_ops = {
2087+ .ras_error_inject = &gfx_v9_0_ras_error_inject,
2088+ .query_ras_error_count = &gfx_v9_0_query_ras_error_count,
2089+ .reset_ras_error_count = &gfx_v9_0_reset_ras_error_count,
2090+};
2091+
2092+static struct amdgpu_gfx_ras gfx_v9_0_ras = {
2093+ .ras_block = {
2094+ .hw_ops = &gfx_v9_0_ras_ops,
2095+ },
22062096 };
22072097
22082098 static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
@@ -2231,7 +2121,7 @@ static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev) · 22 unmodified lines
22312121 DRM_INFO("fix gfx.config for vega12\n");
22322122 break;
22332123 case IP_VERSION(9, 4, 0):
2234− adev->gfx.ras_funcs = &gfx_v9_0_ras_funcs;
2124+ adev->gfx.ras = &gfx_v9_0_ras;
22352125 adev->gfx.config.max_hw_contexts = 8;
22362126 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
22372127 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
@@ -2258,7 +2148,7 @@ static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev) · 20 unmodified lines
22582148 gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN;
22592149 break;
22602150 case IP_VERSION(9, 4, 1):
2261− adev->gfx.ras_funcs = &gfx_v9_4_ras_funcs;
2151+ adev->gfx.ras = &gfx_v9_4_ras;
22622152 adev->gfx.config.max_hw_contexts = 8;
22632153 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
22642154 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
@@ -2279,7 +2169,7 @@ static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev) · 14 unmodified lines
22792169 gb_addr_config |= 0x22010042;
22802170 break;
22812171 case IP_VERSION(9, 4, 2):
2282− adev->gfx.ras_funcs = &gfx_v9_4_2_ras_funcs;
2172+ adev->gfx.ras = &gfx_v9_4_2_ras;
22832173 adev->gfx.config.max_hw_contexts = 8;
22842174 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
22852175 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
@@ -2298,6 +2188,31 @@ static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev) · 12 unmodified lines
22982188 break;
22992189 }
23002190
2191+ if (adev->gfx.ras) {
2192+ err = amdgpu_ras_register_ras_block(adev, &adev->gfx.ras->ras_block);
2193+ if (err) {
2194+ DRM_ERROR("Failed to register gfx ras block!\n");
2195+ return err;
2196+ }
2197+
2198+ strcpy(adev->gfx.ras->ras_block.ras_comm.name, "gfx");
2199+ adev->gfx.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__GFX;
2200+ adev->gfx.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
2201+ adev->gfx.ras_if = &adev->gfx.ras->ras_block.ras_comm;
2202+
2203+ /* If not define special ras_late_init function, use gfx default ras_late_init */
2204+ if (!adev->gfx.ras->ras_block.ras_late_init)
2205+ adev->gfx.ras->ras_block.ras_late_init = amdgpu_gfx_ras_late_init;
2206+
2207+ /* If not define special ras_fini function, use gfx default ras_fini */
2208+ if (!adev->gfx.ras->ras_block.ras_fini)
2209+ adev->gfx.ras->ras_block.ras_fini = amdgpu_gfx_ras_fini;
2210+
2211+ /* If not defined special ras_cb function, use default ras_cb */
2212+ if (!adev->gfx.ras->ras_block.ras_cb)
2213+ adev->gfx.ras->ras_block.ras_cb = amdgpu_gfx_process_ras_data_cb;
2214+ }
2215+
23012216 adev->gfx.config.gb_addr_config = gb_addr_config;
23022217
23032218 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
@@ -2434,10 +2349,14 @@ static int gfx_v9_0_sw_init(void *handle) · 130 unmodified lines
24342349 return r;
24352350 }
24362351
2437− r = adev->gfx.rlc.funcs->init(adev);
2438− if (r) {
2439− DRM_ERROR("Failed to init rlc BOs!\n");
2440− return r;
2352+ if (adev->gfx.rlc.funcs) {
2353+ if (adev->gfx.rlc.funcs->init) {
2354+ r = adev->gfx.rlc.funcs->init(adev);
2355+ if (r) {
2356+ dev_err(adev->dev, "Failed to init rlc BOs!\n");
2357+ return r;
2358+ }
2359+ }
24412360 }
24422361
24432362 r = gfx_v9_0_mec_init(adev);
@@ -2513,9 +2432,8 @@ static int gfx_v9_0_sw_fini(void *handle) · 69 unmodified lines
25132432 int i;
25142433 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
25152434
2516− if (adev->gfx.ras_funcs &&
2517− adev->gfx.ras_funcs->ras_fini)
2518− adev->gfx.ras_funcs->ras_fini(adev);
2435+ if (adev->gfx.ras && adev->gfx.ras->ras_block.ras_fini)
2436+ adev->gfx.ras->ras_block.ras_fini(adev);
25192437
25202438 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
25212439 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
@@ -4840,6 +4758,9 @@ static int gfx_v9_0_early_init(void *handle) · 2318 unmodified lines
48404758 gfx_v9_0_set_gds_init(adev);
48414759 gfx_v9_0_set_rlc_funcs(adev);
48424760
4761+ /* init rlcg reg access ctrl */
4762+ gfx_v9_0_init_rlcg_reg_access_ctrl(adev);
4763+
48434764 return 0;
48444765 }
48454766
@@ -4870,16 +4791,9 @@ static int gfx_v9_0_ecc_late_init(void *handle) · 24 unmodified lines
48704791 if (r)
48714792 return r;
48724793
4873− if (adev->gfx.ras_funcs &&
4874− adev->gfx.ras_funcs->ras_late_init) {
4875− r = adev->gfx.ras_funcs->ras_late_init(adev);
4876− if (r)
4877− return r;
4878− }
4879−
4880− if (adev->gfx.ras_funcs &&
4881− adev->gfx.ras_funcs->enable_watchdog_timer)
4882− adev->gfx.ras_funcs->enable_watchdog_timer(adev);
4794+ if (adev->gfx.ras &&
4795+ adev->gfx.ras->enable_watchdog_timer)
4796+ adev->gfx.ras->enable_watchdog_timer(adev);
48834797
48844798 return 0;
48854799 }
@@ -5250,8 +5164,6 @@ static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = { · 364 unmodified lines
52505164 .reset = gfx_v9_0_rlc_reset,
52515165 .start = gfx_v9_0_rlc_start,
52525166 .update_spm_vmid = gfx_v9_0_update_spm_vmid,
5253− .sriov_wreg = gfx_v9_0_sriov_wreg,
5254− .sriov_rreg = gfx_v9_0_sriov_rreg,
52555167 .is_rlcg_access_range = gfx_v9_0_is_rlcg_access_range,
52565168 };
52575169
@@ -6819,7 +6731,7 @@ static void gfx_v9_0_reset_ras_error_count(struct amdgpu_device *adev) · 1561 unmodified lines
68196731 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255);
68206732 }
68216733
6822−static int gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev,
6734+static void gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev,
68236735 void *ras_error_status)
68246736 {
68256737 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
@@ -6828,7 +6740,7 @@ static int gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev, · 2 unmodified lines
68286740 uint32_t reg_value;
68296741
68306742 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
6831− return -EINVAL;
6743+ return;
68326744
68336745 err_data->ue_count = 0;
68346746 err_data->ce_count = 0;
@@ -6857,8 +6769,6 @@ static int gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev, · 22 unmodified lines
68576769 mutex_unlock(&adev->grbm_idx_mutex);
68586770
68596771 gfx_v9_0_query_utc_edc_status(adev, err_data);
6860−
6861− return 0;
68626772 }
68636773
68646774 static void gfx_v9_0_emit_mem_sync(struct amdgpu_ring *ring)
drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c+14−10
@@ -863,7 +863,7 @@ static int gfx_v9_4_ras_error_count(struct amdgpu_device *adev, · 862 unmodified lines
863863 return 0;
864864 }
865865
866−static int gfx_v9_4_query_ras_error_count(struct amdgpu_device *adev,
866+static void gfx_v9_4_query_ras_error_count(struct amdgpu_device *adev,
867867 void *ras_error_status)
868868 {
869869 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
@@ -872,7 +872,7 @@ static int gfx_v9_4_query_ras_error_count(struct amdgpu_device *adev, · 2 unmodified lines
872872 uint32_t reg_value;
873873
874874 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
875− return -EINVAL;
875+ return;
876876
877877 err_data->ue_count = 0;
878878 err_data->ce_count = 0;
@@ -903,7 +903,6 @@ static int gfx_v9_4_query_ras_error_count(struct amdgpu_device *adev, · 24 unmodified lines
903903
904904 gfx_v9_4_query_utc_edc_status(adev, err_data);
905905
906− return 0;
907906 }
908907
909908 static void gfx_v9_4_reset_ras_error_count(struct amdgpu_device *adev)
@@ -1029,11 +1028,16 @@ static void gfx_v9_4_query_ras_error_status(struct amdgpu_device *adev) · 119 unmodified lines
10291028 mutex_unlock(&adev->grbm_idx_mutex);
10301029 }
10311030
1032−const struct amdgpu_gfx_ras_funcs gfx_v9_4_ras_funcs = {
1033− .ras_late_init = amdgpu_gfx_ras_late_init,
1034− .ras_fini = amdgpu_gfx_ras_fini,
1035− .ras_error_inject = &gfx_v9_4_ras_error_inject,
1036− .query_ras_error_count = &gfx_v9_4_query_ras_error_count,
1037− .reset_ras_error_count = &gfx_v9_4_reset_ras_error_count,
1038− .query_ras_error_status = &gfx_v9_4_query_ras_error_status,
1031+
1032+const struct amdgpu_ras_block_hw_ops gfx_v9_4_ras_ops = {
1033+ .ras_error_inject = &gfx_v9_4_ras_error_inject,
1034+ .query_ras_error_count = &gfx_v9_4_query_ras_error_count,
1035+ .reset_ras_error_count = &gfx_v9_4_reset_ras_error_count,
1036+ .query_ras_error_status = &gfx_v9_4_query_ras_error_status,
1037+};
1038+
1039+struct amdgpu_gfx_ras gfx_v9_4_ras = {
1040+ .ras_block = {
1041+ .hw_ops = &gfx_v9_4_ras_ops,
1042+ },
10391043 };
drivers/gpu/drm/amd/amdgpu/gfx_v9_4.h+1−1
@@ -24,6 +24,6 @@ · 23 unmodified lines
2424 #ifndef __GFX_V9_4_H__
2525 #define __GFX_V9_4_H__
2626
27−extern const struct amdgpu_gfx_ras_funcs gfx_v9_4_ras_funcs;
27+extern struct amdgpu_gfx_ras gfx_v9_4_ras;
2828
2929 #endif /* __GFX_V9_4_H__ */
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c+14−11
@@ -1641,14 +1641,14 @@ static int gfx_v9_4_2_query_utc_edc_count(struct amdgpu_device *adev, · 1640 unmodified lines
16411641 return 0;
16421642 }
16431643
1644−static int gfx_v9_4_2_query_ras_error_count(struct amdgpu_device *adev,
1644+static void gfx_v9_4_2_query_ras_error_count(struct amdgpu_device *adev,
16451645 void *ras_error_status)
16461646 {
16471647 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
16481648 uint32_t sec_count = 0, ded_count = 0;
16491649
16501650 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
1651− return -EINVAL;
1651+ return;
16521652
16531653 err_data->ue_count = 0;
16541654 err_data->ce_count = 0;
@@ -1661,7 +1661,6 @@ static int gfx_v9_4_2_query_ras_error_count(struct amdgpu_device *adev, · 6 unmodified lines
16611661 err_data->ce_count += sec_count;
16621662 err_data->ue_count += ded_count;
16631663
1664− return 0;
16651664 }
16661665
16671666 static void gfx_v9_4_2_reset_utc_err_status(struct amdgpu_device *adev)
@@ -1931,13 +1930,17 @@ static void gfx_v9_4_2_reset_sq_timeout_status(struct amdgpu_device *adev) · 263 unmodified lines
19311930 mutex_unlock(&adev->grbm_idx_mutex);
19321931 }
19331932
1934−const struct amdgpu_gfx_ras_funcs gfx_v9_4_2_ras_funcs = {
1935− .ras_late_init = amdgpu_gfx_ras_late_init,
1936− .ras_fini = amdgpu_gfx_ras_fini,
1937− .ras_error_inject = &gfx_v9_4_2_ras_error_inject,
1938− .query_ras_error_count = &gfx_v9_4_2_query_ras_error_count,
1939− .reset_ras_error_count = &gfx_v9_4_2_reset_ras_error_count,
1940− .query_ras_error_status = &gfx_v9_4_2_query_ras_error_status,
1941− .reset_ras_error_status = &gfx_v9_4_2_reset_ras_error_status,
1933+struct amdgpu_ras_block_hw_ops gfx_v9_4_2_ras_ops = {
1934+ .ras_error_inject = &gfx_v9_4_2_ras_error_inject,
1935+ .query_ras_error_count = &gfx_v9_4_2_query_ras_error_count,
1936+ .reset_ras_error_count = &gfx_v9_4_2_reset_ras_error_count,
1937+ .query_ras_error_status = &gfx_v9_4_2_query_ras_error_status,
1938+ .reset_ras_error_status = &gfx_v9_4_2_reset_ras_error_status,
1939+};
1940+
1941+struct amdgpu_gfx_ras gfx_v9_4_2_ras = {
1942+ .ras_block = {
1943+ .hw_ops = &gfx_v9_4_2_ras_ops,
1944+ },
19421945 .enable_watchdog_timer = &gfx_v9_4_2_enable_watchdog_timer,
19431946 };
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.h+1−1
@@ -31,6 +31,6 @@ void gfx_v9_4_2_init_golden_registers(struct amdgpu_device *adev, · 30 unmodified lines
3131 void gfx_v9_4_2_set_power_brake_sequence(struct amdgpu_device *adev);
3232 int gfx_v9_4_2_do_edc_gpr_workarounds(struct amdgpu_device *adev);
3333
34−extern const struct amdgpu_gfx_ras_funcs gfx_v9_4_2_ras_funcs;
34+extern struct amdgpu_gfx_ras gfx_v9_4_2_ras;
3535
3636 #endif /* __GFX_V9_4_2_H__ */
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c+6−1
@@ -543,7 +543,9 @@ static void gfxhub_v2_1_utcl2_harvest(struct amdgpu_device *adev) · 542 unmodified lines
543543 adev->gfx.config.max_sh_per_se *
544544 adev->gfx.config.max_shader_engines);
545545
546− if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) {
546+ switch (adev->ip_versions[GC_HWIP][0]) {
547+ case IP_VERSION(10, 3, 1):
548+ case IP_VERSION(10, 3, 3):
547549 /* Get SA disabled bitmap from eFuse setting */
548550 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
549551 efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
@@ -566,6 +568,9 @@ static void gfxhub_v2_1_utcl2_harvest(struct amdgpu_device *adev) · 16 unmodified lines
566568 disabled_sa = tmp;
567569
568570 WREG32_SOC15(GC, 0, mmGCUTCL2_HARVEST_BYPASS_GROUPS_YELLOW_CARP, disabled_sa);
571+ break;
572+ default:
573+ break;
569574 }
570575 }
571576
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c+47−13
@@ -48,6 +48,8 @@ · 47 unmodified lines
4848 #include "athub_v2_0.h"
4949 #include "athub_v2_1.h"
5050
51+#include "amdgpu_reset.h"
52+
5153 #if 0
5254 static const struct soc15_reg_golden golden_settings_navi10_hdp[] =
5355 {
@@ -328,7 +330,7 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, · 274 unmodified lines
328330 */
329331 if (adev->gfx.kiq.ring.sched.ready &&
330332 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) &&
331− down_read_trylock(&adev->reset_sem)) {
333+ down_read_trylock(&adev->reset_domain->sem)) {
332334 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
333335 const unsigned eng = 17;
334336 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type);
@@ -338,7 +340,7 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, · 3 unmodified lines
338340 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req,
339341 1 << vmid);
340342
341− up_read(&adev->reset_sem);
343+ up_read(&adev->reset_domain->sem);
342344 return;
343345 }
344346
@@ -664,11 +666,31 @@ static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev) · 319 unmodified lines
664666 adev->umc.umc_inst_num = UMC_V8_7_UMC_INSTANCE_NUM;
665667 adev->umc.channel_offs = UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA;
666668 adev->umc.channel_idx_tbl = &umc_v8_7_channel_idx_tbl[0][0];
667− adev->umc.ras_funcs = &umc_v8_7_ras_funcs;
669+ adev->umc.ras = &umc_v8_7_ras;
668670 break;
669671 default:
670672 break;
671673 }
674+ if (adev->umc.ras) {
675+ amdgpu_ras_register_ras_block(adev, &adev->umc.ras->ras_block);
676+
677+ strcpy(adev->umc.ras->ras_block.ras_comm.name, "umc");
678+ adev->umc.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__UMC;
679+ adev->umc.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
680+ adev->umc.ras_if = &adev->umc.ras->ras_block.ras_comm;
681+
682+ /* If don't define special ras_late_init function, use default ras_late_init */
683+ if (!adev->umc.ras->ras_block.ras_late_init)
684+ adev->umc.ras->ras_block.ras_late_init = amdgpu_umc_ras_late_init;
685+
686+ /* If don't define special ras_fini function, use default ras_fini */
687+ if (!adev->umc.ras->ras_block.ras_fini)
688+ adev->umc.ras->ras_block.ras_fini = amdgpu_umc_ras_fini;
689+
690+ /* If not defined special ras_cb function, use default ras_cb */
691+ if (!adev->umc.ras->ras_block.ras_cb)
692+ adev->umc.ras->ras_block.ras_cb = amdgpu_umc_process_ras_data_cb;
693+ }
672694 }
673695
674696
@@ -677,6 +699,7 @@ static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev) · 2 unmodified lines
677699 switch (adev->ip_versions[MMHUB_HWIP][0]) {
678700 case IP_VERSION(2, 3, 0):
679701 case IP_VERSION(2, 4, 0):
702+ case IP_VERSION(2, 4, 1):
680703 adev->mmhub.funcs = &mmhub_v2_3_funcs;
681704 break;
682705 default:
@@ -693,7 +716,9 @@ static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev) · 10 unmodified lines
693716 case IP_VERSION(10, 3, 1):
694717 case IP_VERSION(10, 3, 4):
695718 case IP_VERSION(10, 3, 5):
719+ case IP_VERSION(10, 3, 6):
696720 case IP_VERSION(10, 3, 3):
721+ case IP_VERSION(10, 3, 7):
697722 adev->gfxhub.funcs = &gfxhub_v2_1_funcs;
698723 break;
699724 default:
@@ -705,6 +730,7 @@ static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev) · 5 unmodified lines
705730
706731 static int gmc_v10_0_early_init(void *handle)
707732 {
733+ int r;
708734 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
709735
710736 gmc_v10_0_set_mmhub_funcs(adev);
@@ -720,6 +746,10 @@ static int gmc_v10_0_early_init(void *handle) · 9 unmodified lines
720746 adev->gmc.private_aperture_end =
721747 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
722748
749+ r = amdgpu_gmc_ras_early_init(adev);
750+ if (r)
751+ return r;
752+
723753 return 0;
724754 }
725755
@@ -862,12 +892,15 @@ static int gmc_v10_0_sw_init(void *handle) · 136 unmodified lines
862892 case IP_VERSION(10, 1, 1):
863893 case IP_VERSION(10, 1, 2):
864894 case IP_VERSION(10, 1, 3):
895+ case IP_VERSION(10, 1, 4):
865896 case IP_VERSION(10, 3, 0):
866897 case IP_VERSION(10, 3, 2):
867898 case IP_VERSION(10, 3, 1):
868899 case IP_VERSION(10, 3, 4):
869900 case IP_VERSION(10, 3, 5):
901+ case IP_VERSION(10, 3, 6):
870902 case IP_VERSION(10, 3, 3):
903+ case IP_VERSION(10, 3, 7):
871904 adev->num_vmhubs = 2;
872905 /*
873906 * To fulfill 4-level page support,
@@ -986,14 +1019,7 @@ static int gmc_v10_0_gart_enable(struct amdgpu_device *adev) · 112 unmodified lines
9861019 return -EINVAL;
9871020 }
9881021
989− if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev))
990− goto skip_pin_bo;
991−
992− r = amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);
993− if (r)
994− return r;
995−
996−skip_pin_bo:
1022+ amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);
9971023 r = adev->gfxhub.funcs->gart_enable(adev);
9981024 if (r)
9991025 return r;
@@ -1019,8 +1045,6 @@ skip_pin_bo: · 19 unmodified lines
10191045 (unsigned)(adev->gmc.gart_size >> 20),
10201046 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
10211047
1022− adev->gart.ready = true;
1023−
10241048 return 0;
10251049 }
10261050
@@ -1043,6 +1067,12 @@ static int gmc_v10_0_hw_init(void *handle) · 16 unmodified lines
10431067 if (r)
10441068 return r;
10451069
1070+ if (amdgpu_emu_mode == 1) {
1071+ r = amdgpu_gmc_vram_checking(adev);
1072+ if (r)
1073+ return r;
1074+ }
1075+
10461076 if (adev->umc.funcs && adev->umc.funcs->init_registers)
10471077 adev->umc.funcs->init_registers(adev);
10481078
@@ -1140,6 +1170,10 @@ static void gmc_v10_0_get_clockgating_state(void *handle, u32 *flags) · 91 unmodified lines
11401170 {
11411171 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
11421172
1173+ if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 3) ||
1174+ adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 4))
1175+ return;
1176+
11431177 adev->mmhub.funcs->get_clockgating(adev, flags);
11441178
11451179 if (adev->ip_versions[ATHUB_HWIP][0] >= IP_VERSION(2, 1, 0))
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c+6−6
@@ -469,16 +469,14 @@ static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable) · 468 unmodified lines
469469 static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
470470 {
471471 uint64_t table_addr;
472− int r, i;
473472 u32 field;
473+ int i;
474474
475475 if (adev->gart.bo == NULL) {
476476 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
477477 return -EINVAL;
478478 }
479− r = amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);
480− if (r)
481− return r;
479+ amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);
482480
483481 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
484482
@@ -558,7 +556,6 @@ static int gmc_v6_0_gart_enable(struct amdgpu_device *adev) · 73 unmodified lines
558556 dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n",
559557 (unsigned)(adev->gmc.gart_size >> 20),
560558 (unsigned long long)table_addr);
561− adev->gart.ready = true;
562559 return 0;
563560 }
564561
@@ -922,7 +919,10 @@ static int gmc_v6_0_hw_init(void *handle) · 357 unmodified lines
922919 if (r)
923920 return r;
924921
925− return r;
922+ if (amdgpu_emu_mode == 1)
923+ return amdgpu_gmc_vram_checking(adev);
924+ else
925+ return r;
926926 }
927927
928928 static int gmc_v6_0_hw_fini(void *handle)
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c+6−7
@@ -613,17 +613,14 @@ static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable) · 612 unmodified lines
613613 static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
614614 {
615615 uint64_t table_addr;
616− int r, i;
617616 u32 tmp, field;
617+ int i;
618618
619619 if (adev->gart.bo == NULL) {
620620 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
621621 return -EINVAL;
622622 }
623− r = amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);
624− if (r)
625− return r;
626−
623+ amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);
627624 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
628625
629626 /* Setup TLB control */
@@ -712,7 +709,6 @@ static int gmc_v7_0_gart_enable(struct amdgpu_device *adev) · 82 unmodified lines
712709 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
713710 (unsigned)(adev->gmc.gart_size >> 20),
714711 (unsigned long long)table_addr);
715− adev->gart.ready = true;
716712 return 0;
717713 }
718714
@@ -1111,7 +1107,10 @@ static int gmc_v7_0_hw_init(void *handle) · 392 unmodified lines
11111107 if (r)
11121108 return r;
11131109
1114− return r;
1110+ if (amdgpu_emu_mode == 1)
1111+ return amdgpu_gmc_vram_checking(adev);
1112+ else
1113+ return r;
11151114 }
11161115
11171116 static int gmc_v7_0_hw_fini(void *handle)
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c+6−7
@@ -837,17 +837,14 @@ static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable) · 836 unmodified lines
837837 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
838838 {
839839 uint64_t table_addr;
840− int r, i;
841840 u32 tmp, field;
841+ int i;
842842
843843 if (adev->gart.bo == NULL) {
844844 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
845845 return -EINVAL;
846846 }
847− r = amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);
848− if (r)
849− return r;
850−
847+ amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);
851848 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
852849
853850 /* Setup TLB control */
@@ -953,7 +950,6 @@ static int gmc_v8_0_gart_enable(struct amdgpu_device *adev) · 99 unmodified lines
953950 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
954951 (unsigned)(adev->gmc.gart_size >> 20),
955952 (unsigned long long)table_addr);
956− adev->gart.ready = true;
957953 return 0;
958954 }
959955
@@ -1242,7 +1238,10 @@ static int gmc_v8_0_hw_init(void *handle) · 282 unmodified lines
12421238 if (r)
12431239 return r;
12441240
1245− return r;
1241+ if (amdgpu_emu_mode == 1)
1242+ return amdgpu_gmc_vram_checking(adev);
1243+ else
1244+ return r;
12461245 }
12471246
12481247 static int gmc_v8_0_hw_fini(void *handle)
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c+74−31
@@ -62,6 +62,8 @@ · 61 unmodified lines
6262 #include "amdgpu_ras.h"
6363 #include "amdgpu_xgmi.h"
6464
65+#include "amdgpu_reset.h"
66+
6567 /* add these here since we already include dce12 headers and these are for DCN */
6668 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d
6769 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
@@ -787,13 +789,13 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, · 719 unmodified lines
787789 */
788790 if (adev->gfx.kiq.ring.sched.ready &&
789791 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) &&
790− down_read_trylock(&adev->reset_sem)) {
792+ down_read_trylock(&adev->reset_domain->sem)) {
791793 uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
792794 uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
793795
794796 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req,
795797 1 << vmid);
796− up_read(&adev->reset_sem);
798+ up_read(&adev->reset_domain->sem);
797799 return;
798800 }
799801
@@ -900,7 +902,7 @@ static int gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, · 100 unmodified lines
900902 if (amdgpu_in_reset(adev))
901903 return -EIO;
902904
903− if (ring->sched.ready && down_read_trylock(&adev->reset_sem)) {
905+ if (ring->sched.ready && down_read_trylock(&adev->reset_domain->sem)) {
904906 /* Vega20+XGMI caches PTEs in TC and TLB. Add a
905907 * heavy-weight TLB flush (type 2), which flushes
906908 * both. Due to a race condition with concurrent
@@ -927,7 +929,7 @@ static int gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, · 20 unmodified lines
927929 if (r) {
928930 amdgpu_ring_undo(ring);
929931 spin_unlock(&adev->gfx.kiq.ring_lock);
930− up_read(&adev->reset_sem);
932+ up_read(&adev->reset_domain->sem);
931933 return -ETIME;
932934 }
933935
@@ -936,10 +938,10 @@ static int gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, · 2 unmodified lines
936938 r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
937939 if (r < 1) {
938940 dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r);
939− up_read(&adev->reset_sem);
941+ up_read(&adev->reset_domain->sem);
940942 return -ETIME;
941943 }
942− up_read(&adev->reset_sem);
944+ up_read(&adev->reset_domain->sem);
943945 return 0;
944946 }
945947
@@ -1202,7 +1204,7 @@ static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev) · 256 unmodified lines
12021204 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
12031205 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20;
12041206 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
1205− adev->umc.ras_funcs = &umc_v6_1_ras_funcs;
1207+ adev->umc.ras = &umc_v6_1_ras;
12061208 break;
12071209 case IP_VERSION(6, 1, 2):
12081210 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
@@ -1210,15 +1212,16 @@ static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev) · 1 unmodified line
12101212 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
12111213 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT;
12121214 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
1213− adev->umc.ras_funcs = &umc_v6_1_ras_funcs;
1215+ adev->umc.ras = &umc_v6_1_ras;
12141216 break;
12151217 case IP_VERSION(6, 7, 0):
1216− adev->umc.max_ras_err_cnt_per_query = UMC_V6_7_TOTAL_CHANNEL_NUM;
1218+ adev->umc.max_ras_err_cnt_per_query =
1219+ UMC_V6_7_TOTAL_CHANNEL_NUM * UMC_V6_7_BAD_PAGE_NUM_PER_CHANNEL;
12171220 adev->umc.channel_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM;
12181221 adev->umc.umc_inst_num = UMC_V6_7_UMC_INSTANCE_NUM;
12191222 adev->umc.channel_offs = UMC_V6_7_PER_CHANNEL_OFFSET;
12201223 if (!adev->gmc.xgmi.connected_to_cpu)
1221− adev->umc.ras_funcs = &umc_v6_7_ras_funcs;
1224+ adev->umc.ras = &umc_v6_7_ras;
12221225 if (1 & adev->smuio.funcs->get_die_id(adev))
12231226 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_first[0][0];
12241227 else
@@ -1227,6 +1230,27 @@ static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev) · 2 unmodified lines
12271230 default:
12281231 break;
12291232 }
1233+
1234+ if (adev->umc.ras) {
1235+ amdgpu_ras_register_ras_block(adev, &adev->umc.ras->ras_block);
1236+
1237+ strcpy(adev->umc.ras->ras_block.ras_comm.name, "umc");
1238+ adev->umc.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__UMC;
1239+ adev->umc.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
1240+ adev->umc.ras_if = &adev->umc.ras->ras_block.ras_comm;
1241+
1242+ /* If don't define special ras_late_init function, use default ras_late_init */
1243+ if (!adev->umc.ras->ras_block.ras_late_init)
1244+ adev->umc.ras->ras_block.ras_late_init = amdgpu_umc_ras_late_init;
1245+
1246+ /* If don't define special ras_fini function, use default ras_fini */
1247+ if (!adev->umc.ras->ras_block.ras_fini)
1248+ adev->umc.ras->ras_block.ras_fini = amdgpu_umc_ras_fini;
1249+
1250+ /* If not defined special ras_cb function, use default ras_cb */
1251+ if (!adev->umc.ras->ras_block.ras_cb)
1252+ adev->umc.ras->ras_block.ras_cb = amdgpu_umc_process_ras_data_cb;
1253+ }
12301254 }
12311255
12321256 static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev)
@@ -1248,18 +1272,31 @@ static void gmc_v9_0_set_mmhub_ras_funcs(struct amdgpu_device *adev) · 15 unmodified lines
12481272 {
12491273 switch (adev->ip_versions[MMHUB_HWIP][0]) {
12501274 case IP_VERSION(9, 4, 0):
1251− adev->mmhub.ras_funcs = &mmhub_v1_0_ras_funcs;
1275+ adev->mmhub.ras = &mmhub_v1_0_ras;
12521276 break;
12531277 case IP_VERSION(9, 4, 1):
1254− adev->mmhub.ras_funcs = &mmhub_v9_4_ras_funcs;
1278+ adev->mmhub.ras = &mmhub_v9_4_ras;
12551279 break;
12561280 case IP_VERSION(9, 4, 2):
1257− adev->mmhub.ras_funcs = &mmhub_v1_7_ras_funcs;
1281+ adev->mmhub.ras = &mmhub_v1_7_ras;
12581282 break;
12591283 default:
12601284 /* mmhub ras is not available */
12611285 break;
12621286 }
1287+
1288+ if (adev->mmhub.ras) {
1289+ amdgpu_ras_register_ras_block(adev, &adev->mmhub.ras->ras_block);
1290+
1291+ strcpy(adev->mmhub.ras->ras_block.ras_comm.name, "mmhub");
1292+ adev->mmhub.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__MMHUB;
1293+ adev->mmhub.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
1294+ adev->mmhub.ras_if = &adev->mmhub.ras->ras_block.ras_comm;
1295+
1296+ /* If don't define special ras_fini function, use default ras_fini */
1297+ if (!adev->mmhub.ras->ras_block.ras_fini)
1298+ adev->mmhub.ras->ras_block.ras_fini = amdgpu_mmhub_ras_fini;
1299+ }
12631300 }
12641301
12651302 static void gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device *adev)
@@ -1269,7 +1306,9 @@ static void gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device *adev) · 3 unmodified lines
12691306
12701307 static void gmc_v9_0_set_hdp_ras_funcs(struct amdgpu_device *adev)
12711308 {
1272− adev->hdp.ras_funcs = &hdp_v4_0_ras_funcs;
1309+ adev->hdp.ras = &hdp_v4_0_ras;
1310+ amdgpu_ras_register_ras_block(adev, &adev->hdp.ras->ras_block);
1311+ adev->hdp.ras_if = &adev->hdp.ras->ras_block.ras_comm;
12731312 }
12741313
12751314 static void gmc_v9_0_set_mca_funcs(struct amdgpu_device *adev)
@@ -1287,6 +1326,7 @@ static void gmc_v9_0_set_mca_funcs(struct amdgpu_device *adev) · 11 unmodified lines
12871326
12881327 static int gmc_v9_0_early_init(void *handle)
12891328 {
1329+ int r;
12901330 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
12911331
12921332 /* ARCT and VEGA20 don't have XGMI defined in their IP discovery tables */
@@ -1316,6 +1356,10 @@ static int gmc_v9_0_early_init(void *handle) · 23 unmodified lines
13161356 adev->gmc.private_aperture_end =
13171357 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
13181358
1359+ r = amdgpu_gmc_ras_early_init(adev);
1360+ if (r)
1361+ return r;
1362+
13191363 return 0;
13201364 }
13211365
@@ -1342,13 +1386,13 @@ static int gmc_v9_0_late_init(void *handle) · 20 unmodified lines
13421386 }
13431387
13441388 if (!amdgpu_persistent_edc_harvesting_supported(adev)) {
1345− if (adev->mmhub.ras_funcs &&
1346− adev->mmhub.ras_funcs->reset_ras_error_count)
1347− adev->mmhub.ras_funcs->reset_ras_error_count(adev);
1389+ if (adev->mmhub.ras && adev->mmhub.ras->ras_block.hw_ops &&
1390+ adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count)
1391+ adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count(adev);
13481392
1349− if (adev->hdp.ras_funcs &&
1350− adev->hdp.ras_funcs->reset_ras_error_count)
1351− adev->hdp.ras_funcs->reset_ras_error_count(adev);
1393+ if (adev->hdp.ras && adev->hdp.ras->ras_block.hw_ops &&
1394+ adev->hdp.ras->ras_block.hw_ops->reset_ras_error_count)
1395+ adev->hdp.ras->ras_block.hw_ops->reset_ras_error_count(adev);
13521396 }
13531397
13541398 r = amdgpu_gmc_ras_late_init(adev);
@@ -1752,14 +1796,7 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) · 397 unmodified lines
17521796 return -EINVAL;
17531797 }
17541798
1755− if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev))
1756− goto skip_pin_bo;
1757−
1758− r = amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);
1759− if (r)
1760− return r;
1761−
1762−skip_pin_bo:
1799+ amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);
17631800 r = adev->gfxhub.funcs->gart_enable(adev);
17641801 if (r)
17651802 return r;
@@ -1776,7 +1813,6 @@ skip_pin_bo: · 10 unmodified lines
17761813 DRM_INFO("PTB located at 0x%016llX\n",
17771814 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
17781815
1779− adev->gart.ready = true;
17801816 return 0;
17811817 }
17821818
@@ -1784,7 +1820,7 @@ static int gmc_v9_0_hw_init(void *handle) · 1 unmodified line
17841820 {
17851821 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
17861822 bool value;
1787− int i;
1823+ int i, r;
17881824
17891825 /* The sequence of these two function calls matters.*/
17901826 gmc_v9_0_init_golden_registers(adev);
@@ -1819,7 +1855,14 @@ static int gmc_v9_0_hw_init(void *handle) · 28 unmodified lines
18191855 if (adev->umc.funcs && adev->umc.funcs->init_registers)
18201856 adev->umc.funcs->init_registers(adev);
18211857
1822− return gmc_v9_0_gart_enable(adev);
1858+ r = gmc_v9_0_gart_enable(adev);
1859+ if (r)
1860+ return r;
1861+
1862+ if (amdgpu_emu_mode == 1)
1863+ return amdgpu_gmc_vram_checking(adev);
1864+ else
1865+ return r;
18231866 }
18241867
18251868 /**
drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c+13−3
@@ -150,13 +150,23 @@ static void hdp_v4_0_init_registers(struct amdgpu_device *adev) · 149 unmodified lines
150150 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40));
151151 }
152152
153−const struct amdgpu_hdp_ras_funcs hdp_v4_0_ras_funcs = {
154− .ras_late_init = amdgpu_hdp_ras_late_init,
155− .ras_fini = amdgpu_hdp_ras_fini,
153+struct amdgpu_ras_block_hw_ops hdp_v4_0_ras_hw_ops = {
156154 .query_ras_error_count = hdp_v4_0_query_ras_error_count,
157155 .reset_ras_error_count = hdp_v4_0_reset_ras_error_count,
158156 };
159157
158+struct amdgpu_hdp_ras hdp_v4_0_ras = {
159+ .ras_block = {
160+ .ras_comm = {
161+ .name = "hdp",
162+ .block = AMDGPU_RAS_BLOCK__HDP,
163+ .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
164+ },
165+ .hw_ops = &hdp_v4_0_ras_hw_ops,
166+ .ras_fini = amdgpu_hdp_ras_fini,
167+ },
168+};
169+
160170 const struct amdgpu_hdp_funcs hdp_v4_0_funcs = {
161171 .flush_hdp = hdp_v4_0_flush_hdp,
162172 .invalidate_hdp = hdp_v4_0_invalidate_hdp,
drivers/gpu/drm/amd/amdgpu/hdp_v4_0.h+1−1
@@ -27,6 +27,6 @@ · 26 unmodified lines
2727 #include "soc15_common.h"
2828
2929 extern const struct amdgpu_hdp_funcs hdp_v4_0_funcs;
30−extern const struct amdgpu_hdp_ras_funcs hdp_v4_0_ras_funcs;
30+extern struct amdgpu_hdp_ras hdp_v4_0_ras;
3131
3232 #endif
drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c+7−2
@@ -50,11 +50,16 @@ static int jpeg_v3_0_early_init(void *handle) · 49 unmodified lines
5050 {
5151 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5252
53− if (adev->asic_type != CHIP_YELLOW_CARP) {
54− u32 harvest = RREG32_SOC15(JPEG, 0, mmCC_UVD_HARVESTING);
53+ u32 harvest;
5554
55+ switch (adev->ip_versions[UVD_HWIP][0]) {
56+ case IP_VERSION(3, 1, 1):
57+ break;
58+ default:
59+ harvest = RREG32_SOC15(JPEG, 0, mmCC_UVD_HARVESTING);
5660 if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK)
5761 return -ENOENT;
62+ break;
5863 }
5964
6065 adev->jpeg.num_jpeg_inst = 1;
drivers/gpu/drm/amd/amdgpu/mca_v3_0.c+67−35
@@ -37,24 +37,42 @@ static void mca_v3_0_mp0_query_ras_error_count(struct amdgpu_device *adev, · 36 unmodified lines
3737 ras_error_status);
3838 }
3939
40−static int mca_v3_0_mp0_ras_late_init(struct amdgpu_device *adev)
40+static void mca_v3_0_mp0_ras_fini(struct amdgpu_device *adev)
4141 {
42− return amdgpu_mca_ras_late_init(adev, &adev->mca.mp0);
42+ amdgpu_mca_ras_fini(adev, &adev->mca.mp0);
4343 }
4444
45−static void mca_v3_0_mp0_ras_fini(struct amdgpu_device *adev)
45+static int mca_v3_0_ras_block_match(struct amdgpu_ras_block_object *block_obj,
46+ enum amdgpu_ras_block block, uint32_t sub_block_index)
4647 {
47− amdgpu_mca_ras_fini(adev, &adev->mca.mp0);
48+ if (!block_obj)
49+ return -EINVAL;
50+
51+ if ((block_obj->ras_comm.block == block) &&
52+ (block_obj->ras_comm.sub_block_index == sub_block_index)) {
53+ return 0;
54+ }
55+
56+ return -EINVAL;
4857 }
4958
50−const struct amdgpu_mca_ras_funcs mca_v3_0_mp0_ras_funcs = {
51− .ras_late_init = mca_v3_0_mp0_ras_late_init,
52− .ras_fini = mca_v3_0_mp0_ras_fini,
59+const struct amdgpu_ras_block_hw_ops mca_v3_0_mp0_hw_ops = {
5360 .query_ras_error_count = mca_v3_0_mp0_query_ras_error_count,
5461 .query_ras_error_address = NULL,
55− .ras_block = AMDGPU_RAS_BLOCK__MCA,
56− .ras_sub_block = AMDGPU_RAS_MCA_BLOCK__MP0,
57− .sysfs_name = "mp0_err_count",
62+};
63+
64+struct amdgpu_mca_ras_block mca_v3_0_mp0_ras = {
65+ .ras_block = {
66+ .ras_comm = {
67+ .block = AMDGPU_RAS_BLOCK__MCA,
68+ .sub_block_index = AMDGPU_RAS_MCA_BLOCK__MP0,
69+ .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
70+ .name = "mp0",
71+ },
72+ .hw_ops = &mca_v3_0_mp0_hw_ops,
73+ .ras_block_match = mca_v3_0_ras_block_match,
74+ .ras_fini = mca_v3_0_mp0_ras_fini,
75+ },
5876 };
5977
6078 static void mca_v3_0_mp1_query_ras_error_count(struct amdgpu_device *adev,
@@ -65,24 +83,28 @@ static void mca_v3_0_mp1_query_ras_error_count(struct amdgpu_device *adev, · 4 unmodified lines
6583 ras_error_status);
6684 }
6785
68−static int mca_v3_0_mp1_ras_late_init(struct amdgpu_device *adev)
69−{
70− return amdgpu_mca_ras_late_init(adev, &adev->mca.mp1);
71−}
72−
7386 static void mca_v3_0_mp1_ras_fini(struct amdgpu_device *adev)
7487 {
7588 amdgpu_mca_ras_fini(adev, &adev->mca.mp1);
7689 }
7790
78−const struct amdgpu_mca_ras_funcs mca_v3_0_mp1_ras_funcs = {
79− .ras_late_init = mca_v3_0_mp1_ras_late_init,
80− .ras_fini = mca_v3_0_mp1_ras_fini,
91+const struct amdgpu_ras_block_hw_ops mca_v3_0_mp1_hw_ops = {
8192 .query_ras_error_count = mca_v3_0_mp1_query_ras_error_count,
8293 .query_ras_error_address = NULL,
83− .ras_block = AMDGPU_RAS_BLOCK__MCA,
84− .ras_sub_block = AMDGPU_RAS_MCA_BLOCK__MP1,
85− .sysfs_name = "mp1_err_count",
94+};
95+
96+struct amdgpu_mca_ras_block mca_v3_0_mp1_ras = {
97+ .ras_block = {
98+ .ras_comm = {
99+ .block = AMDGPU_RAS_BLOCK__MCA,
100+ .sub_block_index = AMDGPU_RAS_MCA_BLOCK__MP1,
101+ .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
102+ .name = "mp1",
103+ },
104+ .hw_ops = &mca_v3_0_mp1_hw_ops,
105+ .ras_block_match = mca_v3_0_ras_block_match,
106+ .ras_fini = mca_v3_0_mp1_ras_fini,
107+ },
86108 };
87109
88110 static void mca_v3_0_mpio_query_ras_error_count(struct amdgpu_device *adev,
@@ -93,24 +115,28 @@ static void mca_v3_0_mpio_query_ras_error_count(struct amdgpu_device *adev, · 4 unmodified lines
93115 ras_error_status);
94116 }
95117
96−static int mca_v3_0_mpio_ras_late_init(struct amdgpu_device *adev)
97−{
98− return amdgpu_mca_ras_late_init(adev, &adev->mca.mpio);
99−}
100−
101118 static void mca_v3_0_mpio_ras_fini(struct amdgpu_device *adev)
102119 {
103120 amdgpu_mca_ras_fini(adev, &adev->mca.mpio);
104121 }
105122
106−const struct amdgpu_mca_ras_funcs mca_v3_0_mpio_ras_funcs = {
107− .ras_late_init = mca_v3_0_mpio_ras_late_init,
108− .ras_fini = mca_v3_0_mpio_ras_fini,
123+const struct amdgpu_ras_block_hw_ops mca_v3_0_mpio_hw_ops = {
109124 .query_ras_error_count = mca_v3_0_mpio_query_ras_error_count,
110125 .query_ras_error_address = NULL,
111− .ras_block = AMDGPU_RAS_BLOCK__MCA,
112− .ras_sub_block = AMDGPU_RAS_MCA_BLOCK__MPIO,
113− .sysfs_name = "mpio_err_count",
126+};
127+
128+struct amdgpu_mca_ras_block mca_v3_0_mpio_ras = {
129+ .ras_block = {
130+ .ras_comm = {
131+ .block = AMDGPU_RAS_BLOCK__MCA,
132+ .sub_block_index = AMDGPU_RAS_MCA_BLOCK__MPIO,
133+ .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
134+ .name = "mpio",
135+ },
136+ .hw_ops = &mca_v3_0_mpio_hw_ops,
137+ .ras_block_match = mca_v3_0_ras_block_match,
138+ .ras_fini = mca_v3_0_mpio_ras_fini,
139+ },
114140 };
115141
116142
@@ -118,9 +144,15 @@ static void mca_v3_0_init(struct amdgpu_device *adev) · 1 unmodified line
118144 {
119145 struct amdgpu_mca *mca = &adev->mca;
120146
121− mca->mp0.ras_funcs = &mca_v3_0_mp0_ras_funcs;
122− mca->mp1.ras_funcs = &mca_v3_0_mp1_ras_funcs;
123− mca->mpio.ras_funcs = &mca_v3_0_mpio_ras_funcs;
147+ mca->mp0.ras = &mca_v3_0_mp0_ras;
148+ mca->mp1.ras = &mca_v3_0_mp1_ras;
149+ mca->mpio.ras = &mca_v3_0_mpio_ras;
150+ amdgpu_ras_register_ras_block(adev, &mca->mp0.ras->ras_block);
151+ amdgpu_ras_register_ras_block(adev, &mca->mp1.ras->ras_block);
152+ amdgpu_ras_register_ras_block(adev, &mca->mpio.ras->ras_block);
153+ mca->mp0.ras_if = &mca->mp0.ras->ras_block.ras_comm;
154+ mca->mp1.ras_if = &mca->mp1.ras->ras_block.ras_comm;
155+ mca->mpio.ras_if = &mca->mpio.ras->ras_block.ras_comm;
124156 }
125157
126158 const struct amdgpu_mca_funcs mca_v3_0_funcs = {
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c+7−3
@@ -774,13 +774,17 @@ static void mmhub_v1_0_reset_ras_error_count(struct amdgpu_device *adev) · 773 unmodified lines
774774 }
775775 }
776776
777−const struct amdgpu_mmhub_ras_funcs mmhub_v1_0_ras_funcs = {
778− .ras_late_init = amdgpu_mmhub_ras_late_init,
779− .ras_fini = amdgpu_mmhub_ras_fini,
777+struct amdgpu_ras_block_hw_ops mmhub_v1_0_ras_hw_ops = {
780778 .query_ras_error_count = mmhub_v1_0_query_ras_error_count,
781779 .reset_ras_error_count = mmhub_v1_0_reset_ras_error_count,
782780 };
783781
782+struct amdgpu_mmhub_ras mmhub_v1_0_ras = {
783+ .ras_block = {
784+ .hw_ops = &mmhub_v1_0_ras_hw_ops,
785+ },
786+};
787+
784788 const struct amdgpu_mmhub_funcs mmhub_v1_0_funcs = {
785789 .get_fb_location = mmhub_v1_0_get_fb_location,
786790 .init = mmhub_v1_0_init,
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h+1−1
@@ -24,6 +24,6 @@ · 23 unmodified lines
2424 #define __MMHUB_V1_0_H__
2525
2626 extern const struct amdgpu_mmhub_funcs mmhub_v1_0_funcs;
27−extern const struct amdgpu_mmhub_ras_funcs mmhub_v1_0_ras_funcs;
27+extern struct amdgpu_mmhub_ras mmhub_v1_0_ras;
2828
2929 #endif
drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c+7−3
@@ -1321,15 +1321,19 @@ static void mmhub_v1_7_reset_ras_error_status(struct amdgpu_device *adev) · 1320 unmodified lines
13211321 }
13221322 }
13231323
1324−const struct amdgpu_mmhub_ras_funcs mmhub_v1_7_ras_funcs = {
1325− .ras_late_init = amdgpu_mmhub_ras_late_init,
1326− .ras_fini = amdgpu_mmhub_ras_fini,
1324+struct amdgpu_ras_block_hw_ops mmhub_v1_7_ras_hw_ops = {
13271325 .query_ras_error_count = mmhub_v1_7_query_ras_error_count,
13281326 .reset_ras_error_count = mmhub_v1_7_reset_ras_error_count,
13291327 .query_ras_error_status = mmhub_v1_7_query_ras_error_status,
13301328 .reset_ras_error_status = mmhub_v1_7_reset_ras_error_status,
13311329 };
13321330
1331+struct amdgpu_mmhub_ras mmhub_v1_7_ras = {
1332+ .ras_block = {
1333+ .hw_ops = &mmhub_v1_7_ras_hw_ops,
1334+ },
1335+};
1336+
13331337 const struct amdgpu_mmhub_funcs mmhub_v1_7_funcs = {
13341338 .get_fb_location = mmhub_v1_7_get_fb_location,
13351339 .init = mmhub_v1_7_init,
drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.h+1−1
@@ -24,6 +24,6 @@ · 23 unmodified lines
2424 #define __MMHUB_V1_7_H__
2525
2626 extern const struct amdgpu_mmhub_funcs mmhub_v1_7_funcs;
27−extern const struct amdgpu_mmhub_ras_funcs mmhub_v1_7_ras_funcs;
27+extern struct amdgpu_mmhub_ras mmhub_v1_7_ras;
2828
2929 #endif
drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c+1−0
@@ -93,6 +93,7 @@ mmhub_v2_3_print_l2_protection_fault_status(struct amdgpu_device *adev, · 92 unmodified lines
9393 switch (adev->ip_versions[MMHUB_HWIP][0]) {
9494 case IP_VERSION(2, 3, 0):
9595 case IP_VERSION(2, 4, 0):
96+ case IP_VERSION(2, 4, 1):
9697 mmhub_cid = mmhub_client_ids_vangogh[cid][rw];
9798 break;
9899 default:
drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c+7−3
@@ -1655,14 +1655,18 @@ static void mmhub_v9_4_query_ras_error_status(struct amdgpu_device *adev) · 1654 unmodified lines
16551655 }
16561656 }
16571657
1658−const struct amdgpu_mmhub_ras_funcs mmhub_v9_4_ras_funcs = {
1659− .ras_late_init = amdgpu_mmhub_ras_late_init,
1660− .ras_fini = amdgpu_mmhub_ras_fini,
1658+const struct amdgpu_ras_block_hw_ops mmhub_v9_4_ras_hw_ops = {
16611659 .query_ras_error_count = mmhub_v9_4_query_ras_error_count,
16621660 .reset_ras_error_count = mmhub_v9_4_reset_ras_error_count,
16631661 .query_ras_error_status = mmhub_v9_4_query_ras_error_status,
16641662 };
16651663
1664+struct amdgpu_mmhub_ras mmhub_v9_4_ras = {
1665+ .ras_block = {
1666+ .hw_ops = &mmhub_v9_4_ras_hw_ops,
1667+ },
1668+};
1669+
16661670 const struct amdgpu_mmhub_funcs mmhub_v9_4_funcs = {
16671671 .get_fb_location = mmhub_v9_4_get_fb_location,
16681672 .init = mmhub_v9_4_init,
drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h+1−1
@@ -24,6 +24,6 @@ · 23 unmodified lines
2424 #define __MMHUB_V9_4_H__
2525
2626 extern const struct amdgpu_mmhub_funcs mmhub_v9_4_funcs;
27−extern const struct amdgpu_mmhub_ras_funcs mmhub_v9_4_ras_funcs;
27+extern struct amdgpu_mmhub_ras mmhub_v9_4_ras;
2828
2929 #endif
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c+12−7
@@ -32,6 +32,8 @@ · 31 unmodified lines
3232 #include "soc15_common.h"
3333 #include "mxgpu_ai.h"
3434
35+#include "amdgpu_reset.h"
36+
3537 static void xgpu_ai_mailbox_send_ack(struct amdgpu_device *adev)
3638 {
3739 WREG8(AI_MAIBOX_CONTROL_RCV_OFFSET_BYTE, 2);
@@ -257,10 +259,10 @@ static void xgpu_ai_mailbox_flr_work(struct work_struct *work) · 219 unmodified lines
257259 * otherwise the mailbox msg will be ruined/reseted by
258260 * the VF FLR.
259261 */
260− if (atomic_cmpxchg(&adev->in_gpu_reset, 0, 1) != 0)
262+ if (atomic_cmpxchg(&adev->reset_domain->in_gpu_reset, 0, 1) != 0)
261263 return;
262264
263− down_write(&adev->reset_sem);
265+ down_write(&adev->reset_domain->sem);
264266
265267 amdgpu_virt_fini_data_exchange(adev);
266268
@@ -275,14 +277,14 @@ static void xgpu_ai_mailbox_flr_work(struct work_struct *work) · 8 unmodified lines
275277 } while (timeout > 1);
276278
277279 flr_done:
278− atomic_set(&adev->in_gpu_reset, 0);
279− up_write(&adev->reset_sem);
280+ atomic_set(&adev->reset_domain->in_gpu_reset, 0);
281+ up_write(&adev->reset_domain->sem);
280282
281283 /* Trigger recovery for world switch failure if no TDR */
282284 if (amdgpu_device_should_recover_gpu(adev)
283285 && (!amdgpu_device_has_job_running(adev) ||
284286 adev->sdma_timeout == MAX_SCHEDULE_TIMEOUT))
285− amdgpu_device_gpu_recover(adev, NULL);
287+ amdgpu_device_gpu_recover_imp(adev, NULL);
286288 }
287289
288290 static int xgpu_ai_set_mailbox_rcv_irq(struct amdgpu_device *adev,
@@ -307,8 +309,11 @@ static int xgpu_ai_mailbox_rcv_irq(struct amdgpu_device *adev, · 18 unmodified lines
307309
308310 switch (event) {
309311 case IDH_FLR_NOTIFICATION:
310− if (amdgpu_sriov_runtime(adev))
311− schedule_work(&adev->virt.flr_work);
312+ if (amdgpu_sriov_runtime(adev) && !amdgpu_in_reset(adev))
313+ WARN_ONCE(!amdgpu_reset_domain_schedule(adev->reset_domain,
314+ &adev->virt.flr_work),
315+ "Failed to queue work! at %s",
316+ __func__);
312317 break;
313318 case IDH_QUERY_ALIVE:
314319 xgpu_ai_mailbox_send_ack(adev);
drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c+12−7
@@ -31,6 +31,8 @@ · 30 unmodified lines
3131 #include "soc15_common.h"
3232 #include "mxgpu_nv.h"
3333
34+#include "amdgpu_reset.h"
35+
3436 static void xgpu_nv_mailbox_send_ack(struct amdgpu_device *adev)
3537 {
3638 WREG8(NV_MAIBOX_CONTROL_RCV_OFFSET_BYTE, 2);
@@ -281,10 +283,10 @@ static void xgpu_nv_mailbox_flr_work(struct work_struct *work) · 244 unmodified lines
281283 * otherwise the mailbox msg will be ruined/reseted by
282284 * the VF FLR.
283285 */
284− if (atomic_cmpxchg(&adev->in_gpu_reset, 0, 1) != 0)
286+ if (atomic_cmpxchg(&adev->reset_domain->in_gpu_reset, 0, 1) != 0)
285287 return;
286288
287− down_write(&adev->reset_sem);
289+ down_write(&adev->reset_domain->sem);
288290
289291 amdgpu_virt_fini_data_exchange(adev);
290292
@@ -299,8 +301,8 @@ static void xgpu_nv_mailbox_flr_work(struct work_struct *work) · 8 unmodified lines
299301 } while (timeout > 1);
300302
301303 flr_done:
302− atomic_set(&adev->in_gpu_reset, 0);
303− up_write(&adev->reset_sem);
304+ atomic_set(&adev->reset_domain->in_gpu_reset, 0);
305+ up_write(&adev->reset_domain->sem);
304306
305307 /* Trigger recovery for world switch failure if no TDR */
306308 if (amdgpu_device_should_recover_gpu(adev)
@@ -309,7 +311,7 @@ flr_done: · 2 unmodified lines
309311 adev->gfx_timeout == MAX_SCHEDULE_TIMEOUT ||
310312 adev->compute_timeout == MAX_SCHEDULE_TIMEOUT ||
311313 adev->video_timeout == MAX_SCHEDULE_TIMEOUT))
312− amdgpu_device_gpu_recover(adev, NULL);
314+ amdgpu_device_gpu_recover_imp(adev, NULL);
313315 }
314316
315317 static int xgpu_nv_set_mailbox_rcv_irq(struct amdgpu_device *adev,
@@ -337,8 +339,11 @@ static int xgpu_nv_mailbox_rcv_irq(struct amdgpu_device *adev, · 21 unmodified lines
337339
338340 switch (event) {
339341 case IDH_FLR_NOTIFICATION:
340− if (amdgpu_sriov_runtime(adev))
341− schedule_work(&adev->virt.flr_work);
342+ if (amdgpu_sriov_runtime(adev) && !amdgpu_in_reset(adev))
343+ WARN_ONCE(!amdgpu_reset_domain_schedule(adev->reset_domain,
344+ &adev->virt.flr_work),
345+ "Failed to queue work! at %s",
346+ __func__);
342347 break;
343348 /* READY_TO_ACCESS_GPU is fetched by kernel polling, IRQ can ignore
344349 * it byfar since that polling thread will handle it,
drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c+9−4
@@ -42,6 +42,8 @@ · 41 unmodified lines
4242 #include "smu/smu_7_1_3_d.h"
4343 #include "mxgpu_vi.h"
4444
45+#include "amdgpu_reset.h"
46+
4547 /* VI golden setting */
4648 static const u32 xgpu_fiji_mgcg_cgcg_init[] = {
4749 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
@@ -521,7 +523,7 @@ static void xgpu_vi_mailbox_flr_work(struct work_struct *work) · 473 unmodified lines
521523
522524 /* Trigger recovery due to world switch failure */
523525 if (amdgpu_device_should_recover_gpu(adev))
524− amdgpu_device_gpu_recover(adev, NULL);
526+ amdgpu_device_gpu_recover_imp(adev, NULL);
525527 }
526528
527529 static int xgpu_vi_set_mailbox_rcv_irq(struct amdgpu_device *adev,
@@ -544,14 +546,17 @@ static int xgpu_vi_mailbox_rcv_irq(struct amdgpu_device *adev, · 16 unmodified lines
544546 {
545547 int r;
546548
547− /* trigger gpu-reset by hypervisor only if TDR disbaled */
549+ /* trigger gpu-reset by hypervisor only if TDR disabled */
548550 if (!amdgpu_gpu_recovery) {
549551 /* see what event we get */
550552 r = xgpu_vi_mailbox_rcv_msg(adev, IDH_FLR_NOTIFICATION);
551553
552554 /* only handle FLR_NOTIFY now */
553− if (!r)
554− schedule_work(&adev->virt.flr_work);
555+ if (!r && !amdgpu_in_reset(adev))
556+ WARN_ONCE(!amdgpu_reset_domain_schedule(adev->reset_domain,
557+ &adev->virt.flr_work),
558+ "Failed to queue work! at %s",
559+ __func__);
555560 }
556561
557562 return 0;
drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c+31−13
@@ -59,10 +59,15 @@ static u32 nbio_v7_2_get_rev_id(struct amdgpu_device *adev) · 58 unmodified lines
5959 {
6060 u32 tmp;
6161
62− if (adev->asic_type == CHIP_YELLOW_CARP)
62+ switch (adev->ip_versions[NBIO_HWIP][0]) {
63+ case IP_VERSION(7, 2, 1):
64+ case IP_VERSION(7, 5, 0):
6365 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC);
64− else
66+ break;
67+ default:
6568 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
69+ break;
70+ }
6671
6772 tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
6873 tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
@@ -72,20 +77,25 @@ static u32 nbio_v7_2_get_rev_id(struct amdgpu_device *adev) · 3 unmodified lines
7277
7378 static void nbio_v7_2_mc_access_enable(struct amdgpu_device *adev, bool enable)
7479 {
75− if (enable)
76− if (adev->asic_type == CHIP_YELLOW_CARP)
80+ switch (adev->ip_versions[NBIO_HWIP][0]) {
81+ case IP_VERSION(7, 2, 1):
82+ case IP_VERSION(7, 5, 0):
83+ if (enable)
7784 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN_YC,
7885 BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK |
7986 BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK);
8087 else
88+ WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN_YC, 0);
89+ break;
90+ default:
91+ if (enable)
8192 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN,
8293 BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK |
8394 BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK);
84− else
85− if (adev->asic_type == CHIP_YELLOW_CARP)
86− WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN_YC, 0);
8795 else
8896 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0);
97+ break;
98+ }
8999 }
90100
91101 static u32 nbio_v7_2_get_memsize(struct amdgpu_device *adev)
@@ -250,7 +260,9 @@ static void nbio_v7_2_update_medium_grain_light_sleep(struct amdgpu_device *adev · 158 unmodified lines
250260 {
251261 uint32_t def, data;
252262
253− if (adev->asic_type == CHIP_YELLOW_CARP) {
263+ switch (adev->ip_versions[NBIO_HWIP][0]) {
264+ case IP_VERSION(7, 2, 1):
265+ case IP_VERSION(7, 5, 0):
254266 def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2));
255267 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
256268 data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK;
@@ -260,8 +272,8 @@ static void nbio_v7_2_update_medium_grain_light_sleep(struct amdgpu_device *adev · 3 unmodified lines
260272 if (def != data)
261273 WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data);
262274
263− data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_TX_POWER_CTRL_1));
264− def = data;
275+ def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0,
276+ regBIF1_PCIE_TX_POWER_CTRL_1));
265277 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
266278 data |= (BIF1_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK |
267279 BIF1_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK);
@@ -272,7 +284,8 @@ static void nbio_v7_2_update_medium_grain_light_sleep(struct amdgpu_device *adev · 4 unmodified lines
272284 if (def != data)
273285 WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_TX_POWER_CTRL_1),
274286 data);
275− } else {
287+ break;
288+ default:
276289 def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2));
277290 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
278291 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
@@ -285,6 +298,7 @@ static void nbio_v7_2_update_medium_grain_light_sleep(struct amdgpu_device *adev · 6 unmodified lines
285298
286299 if (def != data)
287300 WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data);
301+ break;
288302 }
289303 }
290304
@@ -352,7 +366,9 @@ const struct nbio_hdp_flush_reg nbio_v7_2_hdp_flush_reg = { · 61 unmodified lines
352366 static void nbio_v7_2_init_registers(struct amdgpu_device *adev)
353367 {
354368 uint32_t def, data;
355− if (adev->asic_type == CHIP_YELLOW_CARP) {
369+ switch (adev->ip_versions[NBIO_HWIP][0]) {
370+ case IP_VERSION(7, 2, 1):
371+ case IP_VERSION(7, 5, 0):
356372 def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_MST_CTRL_3));
357373 data = REG_SET_FIELD(data, BIF1_PCIE_MST_CTRL_3,
358374 CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
@@ -361,7 +377,8 @@ static void nbio_v7_2_init_registers(struct amdgpu_device *adev) · 2 unmodified lines
361377
362378 if (def != data)
363379 WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_MST_CTRL_3), data);
364− } else {
380+ break;
381+ default:
365382 def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL));
366383 data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL,
367384 CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
@@ -370,6 +387,7 @@ static void nbio_v7_2_init_registers(struct amdgpu_device *adev) · 2 unmodified lines
370387
371388 if (def != data)
372389 WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL), data);
390+ break;
373391 }
374392
375393 if (amdgpu_sriov_vf(adev))
drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c+16−4
@@ -658,16 +658,28 @@ static void nbio_v7_4_enable_doorbell_interrupt(struct amdgpu_device *adev, · 657 unmodified lines
658658 DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1);
659659 }
660660
661−const struct amdgpu_nbio_ras_funcs nbio_v7_4_ras_funcs = {
661+const struct amdgpu_ras_block_hw_ops nbio_v7_4_ras_hw_ops = {
662+ .query_ras_error_count = nbio_v7_4_query_ras_error_count,
663+};
664+
665+struct amdgpu_nbio_ras nbio_v7_4_ras = {
666+ .ras_block = {
667+ .ras_comm = {
668+ .name = "pcie_bif",
669+ .block = AMDGPU_RAS_BLOCK__PCIE_BIF,
670+ .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
671+ },
672+ .hw_ops = &nbio_v7_4_ras_hw_ops,
673+ .ras_late_init = amdgpu_nbio_ras_late_init,
674+ .ras_fini = amdgpu_nbio_ras_fini,
675+ },
662676 .handle_ras_controller_intr_no_bifring = nbio_v7_4_handle_ras_controller_intr_no_bifring,
663677 .handle_ras_err_event_athub_intr_no_bifring = nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring,
664678 .init_ras_controller_interrupt = nbio_v7_4_init_ras_controller_interrupt,
665679 .init_ras_err_event_athub_interrupt = nbio_v7_4_init_ras_err_event_athub_interrupt,
666− .query_ras_error_count = nbio_v7_4_query_ras_error_count,
667− .ras_late_init = amdgpu_nbio_ras_late_init,
668− .ras_fini = amdgpu_nbio_ras_fini,
669680 };
670681
682+
671683 static void nbio_v7_4_program_ltr(struct amdgpu_device *adev)
672684 {
673685 uint32_t def, data;
drivers/gpu/drm/amd/amdgpu/nbio_v7_4.h+1−1
@@ -29,6 +29,6 @@ · 28 unmodified lines
2929 extern const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg;
3030 extern const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg_ald;
3131 extern const struct amdgpu_nbio_funcs nbio_v7_4_funcs;
32−extern const struct amdgpu_nbio_ras_funcs nbio_v7_4_ras_funcs;
32+extern struct amdgpu_nbio_ras nbio_v7_4_ras;
3333
3434 #endif
drivers/gpu/drm/amd/amdgpu/nv.c+35−67
@@ -258,21 +258,6 @@ static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg) · 257 unmodified lines
258258 return amdgpu_device_indirect_rreg64(adev, address, data, reg);
259259 }
260260
261−static u32 nv_pcie_port_rreg(struct amdgpu_device *adev, u32 reg)
262−{
263− unsigned long flags, address, data;
264− u32 r;
265− address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
266− data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
267−
268− spin_lock_irqsave(&adev->pcie_idx_lock, flags);
269− WREG32(address, reg * 4);
270− (void)RREG32(address);
271− r = RREG32(data);
272− spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
273− return r;
274−}
275−
276261 static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
277262 {
278263 unsigned long address, data;
@@ -283,21 +268,6 @@ static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) · 4 unmodified lines
283268 amdgpu_device_indirect_wreg64(adev, address, data, reg, v);
284269 }
285270
286−static void nv_pcie_port_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
287−{
288− unsigned long flags, address, data;
289−
290− address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
291− data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
292−
293− spin_lock_irqsave(&adev->pcie_idx_lock, flags);
294− WREG32(address, reg * 4);
295− (void)RREG32(address);
296− WREG32(data, v);
297− (void)RREG32(data);
298− spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
299−}
300−
301271 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg)
302272 {
303273 unsigned long flags, address, data;
@@ -360,38 +330,6 @@ static bool nv_read_disabled_bios(struct amdgpu_device *adev) · 56 unmodified lines
360330 return false;
361331 }
362332
363−static bool nv_read_bios_from_rom(struct amdgpu_device *adev,
364− u8 *bios, u32 length_bytes)
365−{
366− u32 *dw_ptr;
367− u32 i, length_dw;
368− u32 rom_index_offset, rom_data_offset;
369−
370− if (bios == NULL)
371− return false;
372− if (length_bytes == 0)
373− return false;
374− /* APU vbios image is part of sbios image */
375− if (adev->flags & AMD_IS_APU)
376− return false;
377−
378− dw_ptr = (u32 *)bios;
379− length_dw = ALIGN(length_bytes, 4) / 4;
380−
381− rom_index_offset =
382− adev->smuio.funcs->get_rom_index_offset(adev);
383− rom_data_offset =
384− adev->smuio.funcs->get_rom_data_offset(adev);
385−
386− /* set rom index to 0 */
387− WREG32(rom_index_offset, 0);
388− /* read out the rom data */
389− for (i = 0; i < length_dw; i++)
390− dw_ptr[i] = RREG32(rom_data_offset);
391−
392− return true;
393−}
394−
395333 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = {
396334 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
397335 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
@@ -584,7 +522,7 @@ static void nv_pcie_gen3_enable(struct amdgpu_device *adev) · 186 unmodified lines
584522
585523 static void nv_program_aspm(struct amdgpu_device *adev)
586524 {
587− if (!amdgpu_aspm)
525+ if (!amdgpu_device_should_use_aspm(adev))
588526 return;
589527
590528 if (!(adev->flags & AMD_IS_APU) &&
@@ -699,7 +637,8 @@ static int nv_update_umd_stable_pstate(struct amdgpu_device *adev, · 108 unmodified lines
699637 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);
700638
701639 if (!(adev->flags & AMD_IS_APU) &&
702− (adev->nbio.funcs->enable_aspm))
640+ (adev->nbio.funcs->enable_aspm) &&
641+ amdgpu_device_should_use_aspm(adev))
703642 adev->nbio.funcs->enable_aspm(adev, !enter);
704643
705644 return 0;
@@ -708,7 +647,7 @@ static int nv_update_umd_stable_pstate(struct amdgpu_device *adev, · 2 unmodified lines
708647 static const struct amdgpu_asic_funcs nv_asic_funcs =
709648 {
710649 .read_disabled_bios = &nv_read_disabled_bios,
711− .read_bios_from_rom = &nv_read_bios_from_rom,
650+ .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
712651 .read_register = &nv_read_register,
713652 .reset = &nv_asic_reset,
714653 .reset_method = &nv_asic_reset_method,
@@ -742,8 +681,8 @@ static int nv_common_early_init(void *handle) · 27 unmodified lines
742681 adev->pcie_wreg = &nv_pcie_wreg;
743682 adev->pcie_rreg64 = &nv_pcie_rreg64;
744683 adev->pcie_wreg64 = &nv_pcie_wreg64;
745− adev->pciep_rreg = &nv_pcie_port_rreg;
746− adev->pciep_wreg = &nv_pcie_port_wreg;
684+ adev->pciep_rreg = amdgpu_device_pcie_port_rreg;
685+ adev->pciep_wreg = amdgpu_device_pcie_port_wreg;
747686
748687 /* TODO: will add them during VCN v2 implementation */
749688 adev->uvd_ctx_rreg = NULL;
@@ -964,10 +903,39 @@ static int nv_common_early_init(void *handle) · 214 unmodified lines
964903 adev->external_rev_id = adev->rev_id + 0x01;
965904 break;
966905 case IP_VERSION(10, 1, 3):
906+ case IP_VERSION(10, 1, 4):
967907 adev->cg_flags = 0;
968908 adev->pg_flags = 0;
969909 adev->external_rev_id = adev->rev_id + 0x82;
970910 break;
911+ case IP_VERSION(10, 3, 6):
912+ adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
913+ AMD_CG_SUPPORT_GFX_MGLS |
914+ AMD_CG_SUPPORT_GFX_CGCG |
915+ AMD_CG_SUPPORT_GFX_CGLS |
916+ AMD_CG_SUPPORT_GFX_3D_CGCG |
917+ AMD_CG_SUPPORT_GFX_3D_CGLS |
918+ AMD_CG_SUPPORT_GFX_RLC_LS |
919+ AMD_CG_SUPPORT_GFX_CP_LS |
920+ AMD_CG_SUPPORT_GFX_FGCG |
921+ AMD_CG_SUPPORT_MC_MGCG |
922+ AMD_CG_SUPPORT_MC_LS |
923+ AMD_CG_SUPPORT_SDMA_LS |
924+ AMD_CG_SUPPORT_HDP_MGCG |
925+ AMD_CG_SUPPORT_HDP_LS |
926+ AMD_CG_SUPPORT_ATHUB_MGCG |
927+ AMD_CG_SUPPORT_ATHUB_LS |
928+ AMD_CG_SUPPORT_IH_CG;
929+ adev->pg_flags = AMD_PG_SUPPORT_GFX_PG;
930+ adev->external_rev_id = adev->rev_id + 0x01;
931+ break;
932+ case IP_VERSION(10, 3, 7):
933+ adev->cg_flags = 0;
934+ adev->pg_flags = AMD_PG_SUPPORT_VCN |
935+ AMD_PG_SUPPORT_VCN_DPG |
936+ AMD_PG_SUPPORT_JPEG;
937+ adev->external_rev_id = adev->rev_id + 0x01;
938+ break;
971939 default:
972940 /* FIXME: not supported yet */
973941 return -EINVAL;
drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h+1−0
@@ -258,6 +258,7 @@ enum psp_gfx_fw_type { · 257 unmodified lines
258258 GFX_FW_TYPE_SDMA6 = 56, /* SDMA6 MI */
259259 GFX_FW_TYPE_SDMA7 = 57, /* SDMA7 MI */
260260 GFX_FW_TYPE_VCN1 = 58, /* VCN1 MI */
261+ GFX_FW_TYPE_CAP = 62, /* CAP_FW */
261262 GFX_FW_TYPE_REG_LIST = 67, /* REG_LIST MI */
262263 GFX_FW_TYPE_MAX
263264 };
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c+2−2
@@ -53,11 +53,13 @@ MODULE_FIRMWARE("amdgpu/navi14_ta.bin"); · 52 unmodified lines
5353 MODULE_FIRMWARE("amdgpu/navi12_sos.bin");
5454 MODULE_FIRMWARE("amdgpu/navi12_asd.bin");
5555 MODULE_FIRMWARE("amdgpu/navi12_ta.bin");
56+MODULE_FIRMWARE("amdgpu/navi12_cap.bin");
5657 MODULE_FIRMWARE("amdgpu/arcturus_sos.bin");
5758 MODULE_FIRMWARE("amdgpu/arcturus_asd.bin");
5859 MODULE_FIRMWARE("amdgpu/arcturus_ta.bin");
5960 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sos.bin");
6061 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ta.bin");
62+MODULE_FIRMWARE("amdgpu/sienna_cichlid_cap.bin");
6163 MODULE_FIRMWARE("amdgpu/navy_flounder_sos.bin");
6264 MODULE_FIRMWARE("amdgpu/navy_flounder_ta.bin");
6365 MODULE_FIRMWARE("amdgpu/vangogh_asd.bin");
@@ -177,8 +179,6 @@ static int psp_v11_0_init_microcode(struct psp_context *psp) · 113 unmodified lines
177179 err = psp_init_asd_microcode(psp, chip_name);
178180 if (err)
179181 return err;
180− if (amdgpu_sriov_vf(adev))
181− break;
182182 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
183183 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
184184 if (err) {
drivers/gpu/drm/amd/amdgpu/psp_v13_0.c+7−0
@@ -34,6 +34,9 @@ MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin"); · 33 unmodified lines
3434 MODULE_FIRMWARE("amdgpu/yellow_carp_asd.bin");
3535 MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin");
3636 MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin");
37+MODULE_FIRMWARE("amdgpu/psp_13_0_8_asd.bin");
38+MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin");
39+MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin");
3740
3841 /* For large FW files the time to complete can be very long */
3942 #define USBC_PD_POLLING_LIMIT_S 240
@@ -55,6 +58,9 @@ static int psp_v13_0_init_microcode(struct psp_context *psp) · 15 unmodified lines
5558 case IP_VERSION(13, 0, 3):
5659 chip_name = "yellow_carp";
5760 break;
61+ case IP_VERSION(13, 0, 8):
62+ chip_name = "psp_13_0_8";
63+ break;
5864 default:
5965 BUG();
6066 }
@@ -69,6 +75,7 @@ static int psp_v13_0_init_microcode(struct psp_context *psp) · 8 unmodified lines
6975 break;
7076 case IP_VERSION(13, 0, 1):
7177 case IP_VERSION(13, 0, 3):
78+ case IP_VERSION(13, 0, 8):
7279 err = psp_init_asd_microcode(psp, chip_name);
7380 if (err)
7481 return err;
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c+1−0
@@ -44,6 +44,7 @@ · 43 unmodified lines
4444
4545 MODULE_FIRMWARE("amdgpu/vega10_sos.bin");
4646 MODULE_FIRMWARE("amdgpu/vega10_asd.bin");
47+MODULE_FIRMWARE("amdgpu/vega10_cap.bin");
4748 MODULE_FIRMWARE("amdgpu/vega12_sos.bin");
4849 MODULE_FIRMWARE("amdgpu/vega12_asd.bin");
4950
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c+59−18
@@ -1885,22 +1885,16 @@ static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev, · 1884 unmodified lines
18851885 static int sdma_v4_0_late_init(void *handle)
18861886 {
18871887 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1888− struct ras_ih_if ih_info = {
1889− .cb = sdma_v4_0_process_ras_data_cb,
1890− };
18911888
18921889 sdma_v4_0_setup_ulv(adev);
18931890
18941891 if (!amdgpu_persistent_edc_harvesting_supported(adev)) {
1895− if (adev->sdma.funcs &&
1896− adev->sdma.funcs->reset_ras_error_count)
1897− adev->sdma.funcs->reset_ras_error_count(adev);
1892+ if (adev->sdma.ras && adev->sdma.ras->ras_block.hw_ops &&
1893+ adev->sdma.ras->ras_block.hw_ops->reset_ras_error_count)
1894+ adev->sdma.ras->ras_block.hw_ops->reset_ras_error_count(adev);
18981895 }
18991896
1900− if (adev->sdma.funcs && adev->sdma.funcs->ras_late_init)
1901− return adev->sdma.funcs->ras_late_init(adev, &ih_info);
1902− else
1903− return 0;
1897+ return 0;
19041898 }
19051899
19061900 static int sdma_v4_0_sw_init(void *handle)
@@ -2001,8 +1995,9 @@ static int sdma_v4_0_sw_fini(void *handle) · 94 unmodified lines
20011995 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
20021996 int i;
20031997
2004− if (adev->sdma.funcs && adev->sdma.funcs->ras_fini)
2005− adev->sdma.funcs->ras_fini(adev);
1998+ if (adev->sdma.ras && adev->sdma.ras->ras_block.hw_ops &&
1999+ adev->sdma.ras->ras_block.ras_fini)
2000+ adev->sdma.ras->ras_block.ras_fini(adev);
20062001
20072002 for (i = 0; i < adev->sdma.num_instances; i++) {
20082003 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
@@ -2057,6 +2052,10 @@ static int sdma_v4_0_suspend(void *handle) · 48 unmodified lines
20572052 {
20582053 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
20592054
2055+ /* SMU saves SDMA state for us */
2056+ if (adev->in_s0ix)
2057+ return 0;
2058+
20602059 return sdma_v4_0_hw_fini(adev);
20612060 }
20622061
@@ -2064,6 +2063,10 @@ static int sdma_v4_0_resume(void *handle) · 1 unmodified line
20642063 {
20652064 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
20662065
2066+ /* SMU restores SDMA state for us */
2067+ if (adev->in_s0ix)
2068+ return 0;
2069+
20672070 return sdma_v4_0_hw_init(adev);
20682071 }
20692072
@@ -2740,7 +2743,7 @@ static void sdma_v4_0_get_ras_error_count(uint32_t value, · 670 unmodified lines
27402743 }
27412744 }
27422745
2743−static int sdma_v4_0_query_ras_error_count(struct amdgpu_device *adev,
2746+static int sdma_v4_0_query_ras_error_count_by_instance(struct amdgpu_device *adev,
27442747 uint32_t instance, void *ras_error_status)
27452748 {
27462749 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
@@ -2762,6 +2765,18 @@ static int sdma_v4_0_query_ras_error_count(struct amdgpu_device *adev, · 15 unmodified lines
27622765 return 0;
27632766 };
27642767
2768+static void sdma_v4_0_query_ras_error_count(struct amdgpu_device *adev, void *ras_error_status)
2769+{
2770+ int i = 0;
2771+
2772+ for (i = 0; i < adev->sdma.num_instances; i++) {
2773+ if (sdma_v4_0_query_ras_error_count_by_instance(adev, i, ras_error_status)) {
2774+ dev_err(adev->dev, "Query ras error count failed in SDMA%d\n", i);
2775+ return;
2776+ }
2777+ }
2778+}
2779+
27652780 static void sdma_v4_0_reset_ras_error_count(struct amdgpu_device *adev)
27662781 {
27672782 int i;
@@ -2773,26 +2788,52 @@ static void sdma_v4_0_reset_ras_error_count(struct amdgpu_device *adev) · 5 unmodified lines
27732788 }
27742789 }
27752790
2776−static const struct amdgpu_sdma_ras_funcs sdma_v4_0_ras_funcs = {
2777− .ras_late_init = amdgpu_sdma_ras_late_init,
2778− .ras_fini = amdgpu_sdma_ras_fini,
2791+const struct amdgpu_ras_block_hw_ops sdma_v4_0_ras_hw_ops = {
27792792 .query_ras_error_count = sdma_v4_0_query_ras_error_count,
27802793 .reset_ras_error_count = sdma_v4_0_reset_ras_error_count,
27812794 };
27822795
2796+static struct amdgpu_sdma_ras sdma_v4_0_ras = {
2797+ .ras_block = {
2798+ .hw_ops = &sdma_v4_0_ras_hw_ops,
2799+ .ras_cb = sdma_v4_0_process_ras_data_cb,
2800+ },
2801+};
2802+
27832803 static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev)
27842804 {
27852805 switch (adev->ip_versions[SDMA0_HWIP][0]) {
27862806 case IP_VERSION(4, 2, 0):
27872807 case IP_VERSION(4, 2, 2):
2788− adev->sdma.funcs = &sdma_v4_0_ras_funcs;
2808+ adev->sdma.ras = &sdma_v4_0_ras;
27892809 break;
27902810 case IP_VERSION(4, 4, 0):
2791− adev->sdma.funcs = &sdma_v4_4_ras_funcs;
2811+ adev->sdma.ras = &sdma_v4_4_ras;
27922812 break;
27932813 default:
27942814 break;
27952815 }
2816+
2817+ if (adev->sdma.ras) {
2818+ amdgpu_ras_register_ras_block(adev, &adev->sdma.ras->ras_block);
2819+
2820+ strcpy(adev->sdma.ras->ras_block.ras_comm.name, "sdma");
2821+ adev->sdma.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__SDMA;
2822+ adev->sdma.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
2823+ adev->sdma.ras_if = &adev->sdma.ras->ras_block.ras_comm;
2824+
2825+ /* If don't define special ras_late_init function, use default ras_late_init */
2826+ if (!adev->sdma.ras->ras_block.ras_late_init)
2827+ adev->sdma.ras->ras_block.ras_late_init = amdgpu_sdma_ras_late_init;
2828+
2829+ /* If don't define special ras_fini function, use default ras_fini */
2830+ if (!adev->sdma.ras->ras_block.ras_fini)
2831+ adev->sdma.ras->ras_block.ras_fini = amdgpu_sdma_ras_fini;
2832+
2833+ /* If not defined special ras_cb function, use default ras_cb */
2834+ if (!adev->sdma.ras->ras_block.ras_cb)
2835+ adev->sdma.ras->ras_block.ras_cb = amdgpu_sdma_process_ras_data_cb;
2836+ }
27962837 }
27972838
27982839 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = {
drivers/gpu/drm/amd/amdgpu/sdma_v4_4.c+21−4
@@ -188,7 +188,7 @@ static void sdma_v4_4_get_ras_error_count(struct amdgpu_device *adev, · 187 unmodified lines
188188 }
189189 }
190190
191−static int sdma_v4_4_query_ras_error_count(struct amdgpu_device *adev,
191+static int sdma_v4_4_query_ras_error_count_by_instance(struct amdgpu_device *adev,
192192 uint32_t instance,
193193 void *ras_error_status)
194194 {
@@ -245,9 +245,26 @@ static void sdma_v4_4_reset_ras_error_count(struct amdgpu_device *adev) · 50 unmodified lines
245245 }
246246 }
247247
248−const struct amdgpu_sdma_ras_funcs sdma_v4_4_ras_funcs = {
249− .ras_late_init = amdgpu_sdma_ras_late_init,
250− .ras_fini = amdgpu_sdma_ras_fini,
248+static void sdma_v4_4_query_ras_error_count(struct amdgpu_device *adev, void *ras_error_status)
249+{
250+ int i = 0;
251+
252+ for (i = 0; i < adev->sdma.num_instances; i++) {
253+ if (sdma_v4_4_query_ras_error_count_by_instance(adev, i, ras_error_status)) {
254+ dev_err(adev->dev, "Query ras error count failed in SDMA%d\n", i);
255+ return;
256+ }
257+ }
258+
259+}
260+
261+const struct amdgpu_ras_block_hw_ops sdma_v4_4_ras_hw_ops = {
251262 .query_ras_error_count = sdma_v4_4_query_ras_error_count,
252263 .reset_ras_error_count = sdma_v4_4_reset_ras_error_count,
253264 };
265+
266+struct amdgpu_sdma_ras sdma_v4_4_ras = {
267+ .ras_block = {
268+ .hw_ops = &sdma_v4_4_ras_hw_ops,
269+ },
270+};
drivers/gpu/drm/amd/amdgpu/sdma_v4_4.h+1−1
@@ -23,6 +23,6 @@ · 22 unmodified lines
2323 #ifndef __SDMA_V4_4_H__
2424 #define __SDMA_V4_4_H__
2525
26−extern const struct amdgpu_sdma_ras_funcs sdma_v4_4_ras_funcs;
26+extern struct amdgpu_sdma_ras sdma_v4_4_ras;
2727
2828 #endif
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c+12−7
@@ -51,6 +51,7 @@ MODULE_FIRMWARE("amdgpu/beige_goby_sdma.bin"); · 50 unmodified lines
5151
5252 MODULE_FIRMWARE("amdgpu/vangogh_sdma.bin");
5353 MODULE_FIRMWARE("amdgpu/yellow_carp_sdma.bin");
54+MODULE_FIRMWARE("amdgpu/sdma_5_2_7.bin");
5455
5556 #define SDMA1_REG_OFFSET 0x600
5657 #define SDMA3_REG_OFFSET 0x400
@@ -138,28 +139,32 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device *adev) · 81 unmodified lines
138139
139140 switch (adev->ip_versions[SDMA0_HWIP][0]) {
140141 case IP_VERSION(5, 2, 0):
141− chip_name = "sienna_cichlid";
142+ chip_name = "sienna_cichlid_sdma";
142143 break;
143144 case IP_VERSION(5, 2, 2):
144− chip_name = "navy_flounder";
145+ chip_name = "navy_flounder_sdma";
145146 break;
146147 case IP_VERSION(5, 2, 1):
147− chip_name = "vangogh";
148+ chip_name = "vangogh_sdma";
148149 break;
149150 case IP_VERSION(5, 2, 4):
150− chip_name = "dimgrey_cavefish";
151+ chip_name = "dimgrey_cavefish_sdma";
151152 break;
152153 case IP_VERSION(5, 2, 5):
153− chip_name = "beige_goby";
154+ chip_name = "beige_goby_sdma";
154155 break;
155156 case IP_VERSION(5, 2, 3):
156− chip_name = "yellow_carp";
157+ chip_name = "yellow_carp_sdma";
157158 break;
159+ case IP_VERSION(5, 2, 7):
160+ chip_name = "sdma_5_2_7";
161+ break;
162+
158163 default:
159164 BUG();
160165 }
161166
162− snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
167+ snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", chip_name);
163168
164169 err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev);
165170 if (err)
drivers/gpu/drm/amd/amdgpu/si.c+1−1
@@ -2453,7 +2453,7 @@ static void si_program_aspm(struct amdgpu_device *adev) · 2452 unmodified lines
24532453 bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false;
24542454 bool disable_clkreq = false;
24552455
2456− if (amdgpu_aspm == 0)
2456+ if (!amdgpu_device_should_use_aspm(adev))
24572457 return;
24582458
24592459 if (adev->flags & AMD_IS_APU)
drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c+54−27
@@ -26,6 +26,7 @@ · 25 unmodified lines
2626
2727 #include "smu_v11_0_i2c.h"
2828 #include "amdgpu.h"
29+#include "amdgpu_dpm.h"
2930 #include "soc15_common.h"
3031 #include <drm/drm_fixed.h>
3132 #include <drm/drm_drv.h>
@@ -43,11 +44,10 @@ · 11 unmodified lines
4344
4445 #define I2C_X_RESTART BIT(31)
4546
46−#define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
47−
4847 static void smu_v11_0_i2c_set_clock_gating(struct i2c_adapter *control, bool en)
4948 {
50− struct amdgpu_device *adev = to_amdgpu_device(control);
49+ struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control);
50+ struct amdgpu_device *adev = smu_i2c->adev;
5151 uint32_t reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_PWRMGT);
5252
5353 reg = REG_SET_FIELD(reg, SMUIO_PWRMGT, i2c_clk_gate_en, en ? 1 : 0);
@@ -75,7 +75,8 @@ static void smu_v11_0_i2c_set_clock_gating(struct i2c_adapter *control, bool en) · 21 unmodified lines
7575
7676 static int smu_v11_0_i2c_enable(struct i2c_adapter *control, bool enable)
7777 {
78− struct amdgpu_device *adev = to_amdgpu_device(control);
78+ struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control);
79+ struct amdgpu_device *adev = smu_i2c->adev;
7980
8081 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE, enable ? 1 : 0);
8182
@@ -100,7 +101,8 @@ static int smu_v11_0_i2c_enable(struct i2c_adapter *control, bool enable) · 18 unmodified lines
100101
101102 static void smu_v11_0_i2c_clear_status(struct i2c_adapter *control)
102103 {
103− struct amdgpu_device *adev = to_amdgpu_device(control);
104+ struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control);
105+ struct amdgpu_device *adev = smu_i2c->adev;
104106 /* do */
105107 {
106108 RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CLR_INTR);
@@ -110,7 +112,8 @@ static void smu_v11_0_i2c_clear_status(struct i2c_adapter *control) · 3 unmodified lines
110112
111113 static void smu_v11_0_i2c_configure(struct i2c_adapter *control)
112114 {
113− struct amdgpu_device *adev = to_amdgpu_device(control);
115+ struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control);
116+ struct amdgpu_device *adev = smu_i2c->adev;
114117 uint32_t reg = 0;
115118
116119 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_SLAVE_DISABLE, 1);
@@ -131,7 +134,8 @@ static void smu_v11_0_i2c_configure(struct i2c_adapter *control) · 14 unmodified lines
131134
132135 static void smu_v11_0_i2c_set_clock(struct i2c_adapter *control)
133136 {
134− struct amdgpu_device *adev = to_amdgpu_device(control);
137+ struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control);
138+ struct amdgpu_device *adev = smu_i2c->adev;
135139
136140 /*
137141 * Standard mode speed, These values are taken from SMUIO MAS,
@@ -154,7 +158,8 @@ static void smu_v11_0_i2c_set_clock(struct i2c_adapter *control) · 16 unmodified lines
154158
155159 static void smu_v11_0_i2c_set_address(struct i2c_adapter *control, u16 address)
156160 {
157− struct amdgpu_device *adev = to_amdgpu_device(control);
161+ struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control);
162+ struct amdgpu_device *adev = smu_i2c->adev;
158163
159164 /* The IC_TAR::IC_TAR field is 10-bits wide.
160165 * It takes a 7-bit or 10-bit addresses as an address,
@@ -165,7 +170,8 @@ static void smu_v11_0_i2c_set_address(struct i2c_adapter *control, u16 address) · 4 unmodified lines
165170
166171 static uint32_t smu_v11_0_i2c_poll_tx_status(struct i2c_adapter *control)
167172 {
168− struct amdgpu_device *adev = to_amdgpu_device(control);
173+ struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control);
174+ struct amdgpu_device *adev = smu_i2c->adev;
169175 uint32_t ret = I2C_OK;
170176 uint32_t reg, reg_c_tx_abrt_source;
171177
@@ -216,7 +222,8 @@ static uint32_t smu_v11_0_i2c_poll_tx_status(struct i2c_adapter *control) · 44 unmodified lines
216222
217223 static uint32_t smu_v11_0_i2c_poll_rx_status(struct i2c_adapter *control)
218224 {
219− struct amdgpu_device *adev = to_amdgpu_device(control);
225+ struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control);
226+ struct amdgpu_device *adev = smu_i2c->adev;
220227 uint32_t ret = I2C_OK;
221228 uint32_t reg_ic_status, reg_c_tx_abrt_source;
222229
@@ -262,7 +269,8 @@ static uint32_t smu_v11_0_i2c_transmit(struct i2c_adapter *control, · 39 unmodified lines
262269 u16 address, u8 *data,
263270 u32 numbytes, u32 i2c_flag)
264271 {
265− struct amdgpu_device *adev = to_amdgpu_device(control);
272+ struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control);
273+ struct amdgpu_device *adev = smu_i2c->adev;
266274 u32 bytes_sent, reg, ret = I2C_OK;
267275 unsigned long timeout_counter;
268276
@@ -360,7 +368,8 @@ static uint32_t smu_v11_0_i2c_receive(struct i2c_adapter *control, · 91 unmodified lines
360368 u16 address, u8 *data,
361369 u32 numbytes, u32 i2c_flag)
362370 {
363− struct amdgpu_device *adev = to_amdgpu_device(control);
371+ struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control);
372+ struct amdgpu_device *adev = smu_i2c->adev;
364373 uint32_t bytes_received, ret = I2C_OK;
365374
366375 bytes_received = 0;
@@ -431,7 +440,8 @@ static uint32_t smu_v11_0_i2c_receive(struct i2c_adapter *control, · 64 unmodified lines
431440
432441 static void smu_v11_0_i2c_abort(struct i2c_adapter *control)
433442 {
434− struct amdgpu_device *adev = to_amdgpu_device(control);
443+ struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control);
444+ struct amdgpu_device *adev = smu_i2c->adev;
435445 uint32_t reg = 0;
436446
437447 /* Enable I2C engine; */
@@ -447,7 +457,8 @@ static void smu_v11_0_i2c_abort(struct i2c_adapter *control) · 9 unmodified lines
447457
448458 static bool smu_v11_0_i2c_activity_done(struct i2c_adapter *control)
449459 {
450− struct amdgpu_device *adev = to_amdgpu_device(control);
460+ struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control);
461+ struct amdgpu_device *adev = smu_i2c->adev;
451462
452463 const uint32_t IDLE_TIMEOUT = 1024;
453464 uint32_t timeout_count = 0;
@@ -508,7 +519,8 @@ static void smu_v11_0_i2c_init(struct i2c_adapter *control) · 54 unmodified lines
508519
509520 static void smu_v11_0_i2c_fini(struct i2c_adapter *control)
510521 {
511− struct amdgpu_device *adev = to_amdgpu_device(control);
522+ struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control);
523+ struct amdgpu_device *adev = smu_i2c->adev;
512524 u32 status, enable, en_stat;
513525 int res;
514526
@@ -543,7 +555,8 @@ static void smu_v11_0_i2c_fini(struct i2c_adapter *control) · 28 unmodified lines
543555
544556 static bool smu_v11_0_i2c_bus_lock(struct i2c_adapter *control)
545557 {
546− struct amdgpu_device *adev = to_amdgpu_device(control);
558+ struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control);
559+ struct amdgpu_device *adev = smu_i2c->adev;
547560
548561 /* Send PPSMC_MSG_RequestI2CBus */
549562 if (!amdgpu_dpm_smu_i2c_bus_access(adev, true))
@@ -554,7 +567,8 @@ static bool smu_v11_0_i2c_bus_lock(struct i2c_adapter *control) · 4 unmodified lines
554567
555568 static bool smu_v11_0_i2c_bus_unlock(struct i2c_adapter *control)
556569 {
557− struct amdgpu_device *adev = to_amdgpu_device(control);
570+ struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control);
571+ struct amdgpu_device *adev = smu_i2c->adev;
558572
559573 /* Send PPSMC_MSG_ReleaseI2CBus */
560574 if (!amdgpu_dpm_smu_i2c_bus_access(adev, false))
@@ -587,16 +601,17 @@ static uint32_t smu_v11_0_i2c_write_data(struct i2c_adapter *control, · 26 unmodified lines
587601
588602 if (ret != I2C_OK)
589603 DRM_ERROR("WriteI2CData() - I2C error occurred :%x", ret);
590−
604+
591605 return ret;
592606
593607 }
594608
595609 static void lock_bus(struct i2c_adapter *i2c, unsigned int flags)
596610 {
597− struct amdgpu_device *adev = to_amdgpu_device(i2c);
611+ struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c);
612+ struct amdgpu_device *adev = smu_i2c->adev;
598613
599− mutex_lock(&adev->pm.smu_i2c_mutex);
614+ mutex_lock(&smu_i2c->mutex);
600615 if (!smu_v11_0_i2c_bus_lock(i2c))
601616 DRM_ERROR("Failed to lock the bus from SMU");
602617 else
@@ -611,13 +626,14 @@ static int trylock_bus(struct i2c_adapter *i2c, unsigned int flags) · 8 unmodified lines
611626
612627 static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags)
613628 {
614− struct amdgpu_device *adev = to_amdgpu_device(i2c);
629+ struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c);
630+ struct amdgpu_device *adev = smu_i2c->adev;
615631
616632 if (!smu_v11_0_i2c_bus_unlock(i2c))
617633 DRM_ERROR("Failed to unlock the bus from SMU");
618634 else
619635 adev->pm.bus_locked = false;
620− mutex_unlock(&adev->pm.smu_i2c_mutex);
636+ mutex_unlock(&smu_i2c->mutex);
621637 }
622638
623639 static const struct i2c_lock_operations smu_v11_0_i2c_i2c_lock_ops = {
@@ -706,19 +722,26 @@ static const struct i2c_adapter_quirks smu_v11_0_i2c_control_quirks = { · 82 unmodified lines
706722 .flags = I2C_AQ_NO_ZERO_LEN,
707723 };
708724
709−int smu_v11_0_i2c_control_init(struct i2c_adapter *control)
725+int smu_v11_0_i2c_control_init(struct amdgpu_device *adev)
710726 {
711− struct amdgpu_device *adev = to_amdgpu_device(control);
727+ struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[0];
728+ struct i2c_adapter *control = &smu_i2c->adapter;
712729 int res;
713730
714− mutex_init(&adev->pm.smu_i2c_mutex);
731+ smu_i2c->adev = adev;
732+ smu_i2c->port = 0;
733+ mutex_init(&smu_i2c->mutex);
715734 control->owner = THIS_MODULE;
716735 control->class = I2C_CLASS_HWMON;
717736 control->dev.parent = &adev->pdev->dev;
718737 control->algo = &smu_v11_0_i2c_algo;
719− snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
738+ snprintf(control->name, sizeof(control->name), "AMDGPU SMU 0");
720739 control->lock_ops = &smu_v11_0_i2c_i2c_lock_ops;
721740 control->quirks = &smu_v11_0_i2c_control_quirks;
741+ i2c_set_adapdata(control, smu_i2c);
742+
743+ adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
744+ adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
722745
723746 res = i2c_add_adapter(control);
724747 if (res)
@@ -727,9 +750,13 @@ int smu_v11_0_i2c_control_init(struct i2c_adapter *control) · 2 unmodified lines
727750 return res;
728751 }
729752
730−void smu_v11_0_i2c_control_fini(struct i2c_adapter *control)
753+void smu_v11_0_i2c_control_fini(struct amdgpu_device *adev)
731754 {
755+ struct i2c_adapter *control = adev->pm.ras_eeprom_i2c_bus;
756+
732757 i2c_del_adapter(control);
758+ adev->pm.ras_eeprom_i2c_bus = NULL;
759+ adev->pm.fru_eeprom_i2c_bus = NULL;
733760 }
734761
735762 /*
drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.h+3−3
@@ -26,9 +26,9 @@ · 25 unmodified lines
2626
2727 #include <linux/types.h>
2828
29−struct i2c_adapter;
29+struct amdgpu_device;
3030
31−int smu_v11_0_i2c_control_init(struct i2c_adapter *control);
32−void smu_v11_0_i2c_control_fini(struct i2c_adapter *control);
31+int smu_v11_0_i2c_control_init(struct amdgpu_device *adev);
32+void smu_v11_0_i2c_control_fini(struct amdgpu_device *adev);
3333
3434 #endif
drivers/gpu/drm/amd/amdgpu/soc15.c+14−50
@@ -375,39 +375,6 @@ static bool soc15_read_disabled_bios(struct amdgpu_device *adev) · 374 unmodified lines
375375 return false;
376376 }
377377
378−static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
379− u8 *bios, u32 length_bytes)
380−{
381− u32 *dw_ptr;
382− u32 i, length_dw;
383− uint32_t rom_index_offset;
384− uint32_t rom_data_offset;
385−
386− if (bios == NULL)
387− return false;
388− if (length_bytes == 0)
389− return false;
390− /* APU vbios image is part of sbios image */
391− if (adev->flags & AMD_IS_APU)
392− return false;
393−
394− dw_ptr = (u32 *)bios;
395− length_dw = ALIGN(length_bytes, 4) / 4;
396−
397− rom_index_offset =
398− adev->smuio.funcs->get_rom_index_offset(adev);
399− rom_data_offset =
400− adev->smuio.funcs->get_rom_data_offset(adev);
401−
402− /* set rom index to 0 */
403− WREG32(rom_index_offset, 0);
404− /* read out the rom data */
405− for (i = 0; i < length_dw; i++)
406− dw_ptr[i] = RREG32(rom_data_offset);
407−
408− return true;
409−}
410−
411378 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
412379 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
413380 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
@@ -703,7 +670,7 @@ static void soc15_pcie_gen3_enable(struct amdgpu_device *adev) · 289 unmodified lines
703670
704671 static void soc15_program_aspm(struct amdgpu_device *adev)
705672 {
706− if (!amdgpu_aspm)
673+ if (!amdgpu_device_should_use_aspm(adev))
707674 return;
708675
709676 if (!(adev->flags & AMD_IS_APU) &&
@@ -925,7 +892,7 @@ static void soc15_pre_asic_init(struct amdgpu_device *adev) · 215 unmodified lines
925892 static const struct amdgpu_asic_funcs soc15_asic_funcs =
926893 {
927894 .read_disabled_bios = &soc15_read_disabled_bios,
928− .read_bios_from_rom = &soc15_read_bios_from_rom,
895+ .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
929896 .read_register = &soc15_read_register,
930897 .reset = &soc15_asic_reset,
931898 .reset_method = &soc15_asic_reset_method,
@@ -947,7 +914,7 @@ static const struct amdgpu_asic_funcs soc15_asic_funcs = · 15 unmodified lines
947914 static const struct amdgpu_asic_funcs vega20_asic_funcs =
948915 {
949916 .read_disabled_bios = &soc15_read_disabled_bios,
950− .read_bios_from_rom = &soc15_read_bios_from_rom,
917+ .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
951918 .read_register = &soc15_read_register,
952919 .reset = &soc15_asic_reset,
953920 .reset_method = &soc15_asic_reset_method,
@@ -1114,8 +1081,11 @@ static int soc15_common_early_init(void *handle) · 160 unmodified lines
11141081 AMD_CG_SUPPORT_SDMA_LS |
11151082 AMD_CG_SUPPORT_VCN_MGCG;
11161083
1084+ /*
1085+ * MMHUB PG needs to be disabled for Picasso for
1086+ * stability reasons.
1087+ */
11171088 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1118− AMD_PG_SUPPORT_MMHUB |
11191089 AMD_PG_SUPPORT_VCN;
11201090 } else {
11211091 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
@@ -1219,16 +1189,11 @@ static int soc15_common_early_init(void *handle) · 97 unmodified lines
12191189 static int soc15_common_late_init(void *handle)
12201190 {
12211191 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1222− int r = 0;
12231192
12241193 if (amdgpu_sriov_vf(adev))
12251194 xgpu_ai_mailbox_get_irq(adev);
12261195
1227− if (adev->nbio.ras_funcs &&
1228− adev->nbio.ras_funcs->ras_late_init)
1229− r = adev->nbio.ras_funcs->ras_late_init(adev);
1230−
1231− return r;
1196+ return 0;
12321197 }
12331198
12341199 static int soc15_common_sw_init(void *handle)
@@ -1249,9 +1214,8 @@ static int soc15_common_sw_fini(void *handle) · 14 unmodified lines
12491214 {
12501215 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
12511216
1252− if (adev->nbio.ras_funcs &&
1253− adev->nbio.ras_funcs->ras_fini)
1254− adev->nbio.ras_funcs->ras_fini(adev);
1217+ if (adev->nbio.ras && adev->nbio.ras->ras_block.ras_fini)
1218+ adev->nbio.ras->ras_block.ras_fini(adev);
12551219
12561220 if (adev->df.funcs &&
12571221 adev->df.funcs->sw_fini)
@@ -1318,11 +1282,11 @@ static int soc15_common_hw_fini(void *handle) · 60 unmodified lines
13181282
13191283 if (adev->nbio.ras_if &&
13201284 amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
1321− if (adev->nbio.ras_funcs &&
1322− adev->nbio.ras_funcs->init_ras_controller_interrupt)
1285+ if (adev->nbio.ras &&
1286+ adev->nbio.ras->init_ras_controller_interrupt)
13231287 amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0);
1324− if (adev->nbio.ras_funcs &&
1325− adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt)
1288+ if (adev->nbio.ras &&
1289+ adev->nbio.ras->init_ras_err_event_athub_interrupt)
13261290 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);
13271291 }
13281292
drivers/gpu/drm/amd/amdgpu/soc15_common.h+4−4
@@ -28,13 +28,13 @@ · 27 unmodified lines
2828 #define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
2929
3030 #define __WREG32_SOC15_RLC__(reg, value, flag, hwip) \
31− ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.funcs->sriov_wreg) ? \
32− adev->gfx.rlc.funcs->sriov_wreg(adev, reg, value, flag, hwip) : \
31+ ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported) ? \
32+ amdgpu_sriov_wreg(adev, reg, value, flag, hwip) : \
3333 WREG32(reg, value))
3434
3535 #define __RREG32_SOC15_RLC__(reg, flag, hwip) \
36− ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.funcs->sriov_rreg) ? \
37− adev->gfx.rlc.funcs->sriov_rreg(adev, reg, flag, hwip) : \
36+ ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported) ? \
37+ amdgpu_sriov_rreg(adev, reg, flag, hwip) : \
3838 RREG32(reg))
3939
4040 #define WREG32_FIELD15(ip, idx, reg, field, val) \
drivers/gpu/drm/amd/amdgpu/ta_ras_if.h+2−1
@@ -64,7 +64,8 @@ enum ta_ras_status { · 63 unmodified lines
6464 TA_RAS_STATUS__ERROR_PCS_STATE_ERROR = 0xA016,
6565 TA_RAS_STATUS__ERROR_PCS_STATE_HANG = 0xA017,
6666 TA_RAS_STATUS__ERROR_PCS_STATE_UNKNOWN = 0xA018,
67− TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ = 0xA019
67+ TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ = 0xA019,
68+ TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED = 0xA01A
6869 };
6970
7071 enum ta_ras_block {
drivers/gpu/drm/amd/amdgpu/umc_v6_1.c+11−19
@@ -300,7 +300,6 @@ static void umc_v6_1_query_error_address(struct amdgpu_device *adev, · 299 unmodified lines
300300 {
301301 uint32_t lsb, mc_umc_status_addr;
302302 uint64_t mc_umc_status, err_addr, retired_page, mc_umc_addrt0;
303− struct eeprom_table_record *err_rec;
304303 uint32_t channel_index = adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst];
305304
306305 if (adev->asic_type == CHIP_ARCTURUS) {
@@ -328,8 +327,6 @@ static void umc_v6_1_query_error_address(struct amdgpu_device *adev, · 21 unmodified lines
328327 return;
329328 }
330329
331− err_rec = &err_data->err_addr[err_data->err_addr_cnt];
332−
333330 /* calculate error address if ue/ce error is detected */
334331 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
335332 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
@@ -348,18 +345,9 @@ static void umc_v6_1_query_error_address(struct amdgpu_device *adev, · 12 unmodified lines
348345
349346 /* we only save ue error information currently, ce is skipped */
350347 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC)
351− == 1) {
352− err_rec->address = err_addr;
353− /* page frame address is saved */
354− err_rec->retired_page = retired_page >> AMDGPU_GPU_PAGE_SHIFT;
355− err_rec->ts = (uint64_t)ktime_get_real_seconds();
356− err_rec->err_type = AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE;
357− err_rec->cu = 0;
358− err_rec->mem_channel = channel_index;
359− err_rec->mcumc_id = umc_inst;
360−
361− err_data->err_addr_cnt++;
362− }
348+ == 1)
349+ amdgpu_umc_fill_error_record(err_data, err_addr,
350+ retired_page, channel_index, umc_inst);
363351 }
364352
365353 /* clear umc status */
@@ -465,10 +453,14 @@ static void umc_v6_1_err_cnt_init(struct amdgpu_device *adev) · 99 unmodified lines
465453 umc_v6_1_enable_umc_index_mode(adev);
466454 }
467455
468−const struct amdgpu_umc_ras_funcs umc_v6_1_ras_funcs = {
469− .err_cnt_init = umc_v6_1_err_cnt_init,
470− .ras_late_init = amdgpu_umc_ras_late_init,
471− .ras_fini = amdgpu_umc_ras_fini,
456+const struct amdgpu_ras_block_hw_ops umc_v6_1_ras_hw_ops = {
472457 .query_ras_error_count = umc_v6_1_query_ras_error_count,
473458 .query_ras_error_address = umc_v6_1_query_ras_error_address,
474459 };
460+
461+struct amdgpu_umc_ras umc_v6_1_ras = {
462+ .ras_block = {
463+ .hw_ops = &umc_v6_1_ras_hw_ops,
464+ },
465+ .err_cnt_init = umc_v6_1_err_cnt_init,
466+};
drivers/gpu/drm/amd/amdgpu/umc_v6_1.h+1−1
@@ -45,7 +45,7 @@ · 44 unmodified lines
4545 /* umc ce count initial value */
4646 #define UMC_V6_1_CE_CNT_INIT (UMC_V6_1_CE_CNT_MAX - UMC_V6_1_CE_INT_THRESHOLD)
4747
48−extern const struct amdgpu_umc_ras_funcs umc_v6_1_ras_funcs;
48+extern struct amdgpu_umc_ras umc_v6_1_ras;
4949 extern const uint32_t
5050 umc_v6_1_channel_idx_tbl[UMC_V6_1_UMC_INSTANCE_NUM][UMC_V6_1_CHANNEL_INSTANCE_NUM];
5151
drivers/gpu/drm/amd/amdgpu/umc_v6_7.c+142−83
@@ -47,6 +47,13 @@ static inline uint32_t get_umc_v6_7_reg_offset(struct amdgpu_device *adev, · 46 unmodified lines
4747 uint32_t umc_inst,
4848 uint32_t ch_inst)
4949 {
50+ uint32_t index = umc_inst * adev->umc.channel_inst_num + ch_inst;
51+
52+ /* adjust umc and channel index offset,
53+ * the register address is not linear on each umc instace */
54+ umc_inst = index / 4;
55+ ch_inst = index % 4;
56+
5057 return adev->umc.channel_offs * ch_inst + UMC_V6_7_INST_DIST * umc_inst;
5158 }
5259
@@ -58,49 +65,74 @@ static inline uint32_t get_umc_v6_7_channel_index(struct amdgpu_device *adev, · 5 unmodified lines
5865 }
5966
6067 static void umc_v6_7_ecc_info_query_correctable_error_count(struct amdgpu_device *adev,
61− uint32_t channel_index,
68+ uint32_t umc_inst, uint32_t ch_inst,
6269 unsigned long *error_count)
6370 {
64− uint32_t ecc_err_cnt;
6571 uint64_t mc_umc_status;
72+ uint32_t eccinfo_table_idx;
6673 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
6774
68− /*
69− * select the lower chip and check the error count
70− * skip add error count, calc error counter only from mca_umc_status
71− */
72− ecc_err_cnt = ras->umc_ecc.ecc[channel_index].ce_count_lo_chip;
73−
74− /*
75− * select the higher chip and check the err counter
76− * skip add error count, calc error counter only from mca_umc_status
77− */
78− ecc_err_cnt = ras->umc_ecc.ecc[channel_index].ce_count_hi_chip;
79−
75+ eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst;
8076 /* check for SRAM correctable error
8177 MCUMC_STATUS is a 64 bit register */
82− mc_umc_status = ras->umc_ecc.ecc[channel_index].mca_umc_status;
78+ mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status;
8379 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
8480 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)
8581 *error_count += 1;
8682 }
8783
8884 static void umc_v6_7_ecc_info_querry_uncorrectable_error_count(struct amdgpu_device *adev,
89− uint32_t channel_index,
85+ uint32_t umc_inst, uint32_t ch_inst,
9086 unsigned long *error_count)
9187 {
9288 uint64_t mc_umc_status;
89+ uint32_t eccinfo_table_idx;
90+ uint32_t umc_reg_offset;
91+ uint32_t mc_umc_addr;
92+ uint64_t reg_value;
9393 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
9494
95+ umc_reg_offset = get_umc_v6_7_reg_offset(adev,
96+ umc_inst, ch_inst);
97+
98+ eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst;
9599 /* check the MCUMC_STATUS */
96− mc_umc_status = ras->umc_ecc.ecc[channel_index].mca_umc_status;
100+ mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status;
97101 if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &&
98102 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 ||
99103 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
100104 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 ||
101105 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 ||
102− REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1))
106+ REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)) {
103107 *error_count += 1;
108+
109+ if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1)
110+ dev_info(adev->dev, "Deferred error, no user action is needed.\n");
111+
112+ if (mc_umc_status)
113+ dev_info(adev->dev, "MCA STATUS 0x%llx, umc_reg_offset 0x%x\n", mc_umc_status, umc_reg_offset);
114+
115+ /* print IPID registers value */
116+ mc_umc_addr =
117+ SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_IPIDT0);
118+ reg_value = RREG64_PCIE((mc_umc_addr + umc_reg_offset) * 4);
119+ if (reg_value)
120+ dev_info(adev->dev, "MCA IPID 0x%llx, umc_reg_offset 0x%x\n", reg_value, umc_reg_offset);
121+
122+ /* print SYND registers value */
123+ mc_umc_addr =
124+ SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_SYNDT0);
125+ reg_value = RREG64_PCIE((mc_umc_addr + umc_reg_offset) * 4);
126+ if (reg_value)
127+ dev_info(adev->dev, "MCA SYND 0x%llx, umc_reg_offset 0x%x\n", reg_value, umc_reg_offset);
128+
129+ /* print MISC0 registers value */
130+ mc_umc_addr =
131+ SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_MISC0T0);
132+ reg_value = RREG64_PCIE((mc_umc_addr + umc_reg_offset) * 4);
133+ if (reg_value)
134+ dev_info(adev->dev, "MCA MISC0 0x%llx, umc_reg_offset 0x%x\n", reg_value, umc_reg_offset);
135+ }
104136 }
105137
106138 static void umc_v6_7_ecc_info_query_ras_error_count(struct amdgpu_device *adev,
@@ -110,42 +142,34 @@ static void umc_v6_7_ecc_info_query_ras_error_count(struct amdgpu_device *adev, · 3 unmodified lines
110142
111143 uint32_t umc_inst = 0;
112144 uint32_t ch_inst = 0;
113− uint32_t umc_reg_offset = 0;
114− uint32_t channel_index = 0;
115145
116146 /*TODO: driver needs to toggle DF Cstate to ensure
117147 * safe access of UMC registers. Will add the protection */
118148 LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) {
119− umc_reg_offset = get_umc_v6_7_reg_offset(adev,
120− umc_inst,
121− ch_inst);
122− channel_index = get_umc_v6_7_channel_index(adev,
123− umc_inst,
124− ch_inst);
125149 umc_v6_7_ecc_info_query_correctable_error_count(adev,
126− channel_index,
150+ umc_inst, ch_inst,
127151 &(err_data->ce_count));
128152 umc_v6_7_ecc_info_querry_uncorrectable_error_count(adev,
129− channel_index,
153+ umc_inst, ch_inst,
130154 &(err_data->ue_count));
131155 }
132156 }
133157
134158 static void umc_v6_7_ecc_info_query_error_address(struct amdgpu_device *adev,
135159 struct ras_err_data *err_data,
136− uint32_t umc_reg_offset,
137160 uint32_t ch_inst,
138161 uint32_t umc_inst)
139162 {
140− uint64_t mc_umc_status, err_addr, retired_page;
141− struct eeprom_table_record *err_rec;
163+ uint64_t mc_umc_status, err_addr, soc_pa, retired_page, column;
142164 uint32_t channel_index;
165+ uint32_t eccinfo_table_idx;
143166 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
144167
168+ eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst;
145169 channel_index =
146170 adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst];
147171
148− mc_umc_status = ras->umc_ecc.ecc[channel_index].mca_umc_status;
172+ mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status;
149173
150174 if (mc_umc_status == 0)
151175 return;
@@ -153,34 +177,41 @@ static void umc_v6_7_ecc_info_query_error_address(struct amdgpu_device *adev, · 1 unmodified line
153177 if (!err_data->err_addr)
154178 return;
155179
156− err_rec = &err_data->err_addr[err_data->err_addr_cnt];
157−
158180 /* calculate error address if ue/ce error is detected */
159181 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
160182 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
161183 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)) {
162184
163− err_addr = ras->umc_ecc.ecc[channel_index].mca_umc_addr;
185+ err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_addr;
164186 err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);
165187
166188 /* translate umc channel address to soc pa, 3 parts are included */
167− retired_page = ADDR_OF_8KB_BLOCK(err_addr) |
189+ soc_pa = ADDR_OF_8KB_BLOCK(err_addr) |
168190 ADDR_OF_256B_BLOCK(channel_index) |
169191 OFFSET_IN_256B_BLOCK(err_addr);
170192
193+ /* The umc channel bits are not original values, they are hashed */
194+ SET_CHANNEL_HASH(channel_index, soc_pa);
195+
196+ /* clear [C4 C3 C2] in soc physical address */
197+ soc_pa &= ~(0x7ULL << UMC_V6_7_PA_C2_BIT);
198+
171199 /* we only save ue error information currently, ce is skipped */
172200 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC)
173201 == 1) {
174− err_rec->address = err_addr;
175− /* page frame address is saved */
176− err_rec->retired_page = retired_page >> AMDGPU_GPU_PAGE_SHIFT;
177− err_rec->ts = (uint64_t)ktime_get_real_seconds();
178− err_rec->err_type = AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE;
179− err_rec->cu = 0;
180− err_rec->mem_channel = channel_index;
181− err_rec->mcumc_id = umc_inst;
182−
183− err_data->err_addr_cnt++;
202+ /* loop for all possibilities of [C4 C3 C2] */
203+ for (column = 0; column < UMC_V6_7_NA_MAP_PA_NUM; column++) {
204+ retired_page = soc_pa | (column << UMC_V6_7_PA_C2_BIT);
205+ dev_info(adev->dev, "Error Address(PA): 0x%llx\n", retired_page);
206+ amdgpu_umc_fill_error_record(err_data, err_addr,
207+ retired_page, channel_index, umc_inst);
208+
209+ /* shift R14 bit */
210+ retired_page ^= (0x1ULL << UMC_V6_7_PA_R14_BIT);
211+ dev_info(adev->dev, "Error Address(PA): 0x%llx\n", retired_page);
212+ amdgpu_umc_fill_error_record(err_data, err_addr,
213+ retired_page, channel_index, umc_inst);
214+ }
184215 }
185216 }
186217 }
@@ -192,18 +223,13 @@ static void umc_v6_7_ecc_info_query_ras_error_address(struct amdgpu_device *adev · 5 unmodified lines
192223
193224 uint32_t umc_inst = 0;
194225 uint32_t ch_inst = 0;
195− uint32_t umc_reg_offset = 0;
196226
197227 /*TODO: driver needs to toggle DF Cstate to ensure
198228 * safe access of UMC resgisters. Will add the protection
199229 * when firmware interface is ready */
200230 LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) {
201− umc_reg_offset = get_umc_v6_7_reg_offset(adev,
202− umc_inst,
203− ch_inst);
204231 umc_v6_7_ecc_info_query_error_address(adev,
205232 err_data,
206− umc_reg_offset,
207233 ch_inst,
208234 umc_inst);
209235 }
@@ -261,6 +287,8 @@ static void umc_v6_7_querry_uncorrectable_error_count(struct amdgpu_device *adev · 51 unmodified lines
261287 {
262288 uint64_t mc_umc_status;
263289 uint32_t mc_umc_status_addr;
290+ uint32_t mc_umc_addr;
291+ uint64_t reg_value;
264292
265293 mc_umc_status_addr =
266294 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0);
@@ -272,8 +300,36 @@ static void umc_v6_7_querry_uncorrectable_error_count(struct amdgpu_device *adev · 5 unmodified lines
272300 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
273301 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 ||
274302 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 ||
275− REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1))
303+ REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)) {
276304 *error_count += 1;
305+
306+ if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1)
307+ dev_info(adev->dev, "Deferred error, no user action is needed.\n");
308+
309+ if (mc_umc_status)
310+ dev_info(adev->dev, "MCA STATUS 0x%llx, umc_reg_offset 0x%x\n", mc_umc_status, umc_reg_offset);
311+
312+ /* print IPID registers value */
313+ mc_umc_addr =
314+ SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_IPIDT0);
315+ reg_value = RREG64_PCIE((mc_umc_addr + umc_reg_offset) * 4);
316+ if (reg_value)
317+ dev_info(adev->dev, "MCA IPID 0x%llx, umc_reg_offset 0x%x\n", reg_value, umc_reg_offset);
318+
319+ /* print SYND registers value */
320+ mc_umc_addr =
321+ SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_SYNDT0);
322+ reg_value = RREG64_PCIE((mc_umc_addr + umc_reg_offset) * 4);
323+ if (reg_value)
324+ dev_info(adev->dev, "MCA SYND 0x%llx, umc_reg_offset 0x%x\n", reg_value, umc_reg_offset);
325+
326+ /* print MISC0 registers value */
327+ mc_umc_addr =
328+ SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_MISC0T0);
329+ reg_value = RREG64_PCIE((mc_umc_addr + umc_reg_offset) * 4);
330+ if (reg_value)
331+ dev_info(adev->dev, "MCA MISC0 0x%llx, umc_reg_offset 0x%x\n", reg_value, umc_reg_offset);
332+ }
277333 }
278334
279335 static void umc_v6_7_reset_error_count_per_channel(struct amdgpu_device *adev,
@@ -365,9 +421,9 @@ static void umc_v6_7_query_error_address(struct amdgpu_device *adev, · 85 unmodified lines
365421 uint32_t umc_inst)
366422 {
367423 uint32_t mc_umc_status_addr;
368− uint64_t mc_umc_status, err_addr, retired_page, mc_umc_addrt0;
369− struct eeprom_table_record *err_rec;
370424 uint32_t channel_index;
425+ uint64_t mc_umc_status, mc_umc_addrt0;
426+ uint64_t err_addr, soc_pa, retired_page, column;
371427
372428 mc_umc_status_addr =
373429 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0);
@@ -385,8 +441,6 @@ static void umc_v6_7_query_error_address(struct amdgpu_device *adev, · 11 unmodified lines
385441 return;
386442 }
387443
388− err_rec = &err_data->err_addr[err_data->err_addr_cnt];
389−
390444 channel_index =
391445 adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst];
392446
@@ -399,23 +453,32 @@ static void umc_v6_7_query_error_address(struct amdgpu_device *adev, · 6 unmodified lines
399453 err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);
400454
401455 /* translate umc channel address to soc pa, 3 parts are included */
402− retired_page = ADDR_OF_8KB_BLOCK(err_addr) |
456+ soc_pa = ADDR_OF_8KB_BLOCK(err_addr) |
403457 ADDR_OF_256B_BLOCK(channel_index) |
404458 OFFSET_IN_256B_BLOCK(err_addr);
405459
460+ /* The umc channel bits are not original values, they are hashed */
461+ SET_CHANNEL_HASH(channel_index, soc_pa);
462+
463+ /* clear [C4 C3 C2] in soc physical address */
464+ soc_pa &= ~(0x7ULL << UMC_V6_7_PA_C2_BIT);
465+
406466 /* we only save ue error information currently, ce is skipped */
407467 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC)
408468 == 1) {
409− err_rec->address = err_addr;
410− /* page frame address is saved */
411− err_rec->retired_page = retired_page >> AMDGPU_GPU_PAGE_SHIFT;
412− err_rec->ts = (uint64_t)ktime_get_real_seconds();
413− err_rec->err_type = AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE;
414− err_rec->cu = 0;
415− err_rec->mem_channel = channel_index;
416− err_rec->mcumc_id = umc_inst;
417−
418− err_data->err_addr_cnt++;
469+ /* loop for all possibilities of [C4 C3 C2] */
470+ for (column = 0; column < UMC_V6_7_NA_MAP_PA_NUM; column++) {
471+ retired_page = soc_pa | (column << UMC_V6_7_PA_C2_BIT);
472+ dev_info(adev->dev, "Error Address(PA): 0x%llx\n", retired_page);
473+ amdgpu_umc_fill_error_record(err_data, err_addr,
474+ retired_page, channel_index, umc_inst);
475+
476+ /* shift R14 bit */
477+ retired_page ^= (0x1ULL << UMC_V6_7_PA_R14_BIT);
478+ dev_info(adev->dev, "Error Address(PA): 0x%llx\n", retired_page);
479+ amdgpu_umc_fill_error_record(err_data, err_addr,
480+ retired_page, channel_index, umc_inst);
481+ }
419482 }
420483 }
421484
@@ -463,28 +526,24 @@ static uint32_t umc_v6_7_query_ras_poison_mode_per_channel( · 41 unmodified lines
463526
464527 static bool umc_v6_7_query_ras_poison_mode(struct amdgpu_device *adev)
465528 {
466− uint32_t umc_inst = 0;
467− uint32_t ch_inst = 0;
468529 uint32_t umc_reg_offset = 0;
469530
470− LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) {
471− umc_reg_offset = get_umc_v6_7_reg_offset(adev,
472− umc_inst,
473− ch_inst);
474− /* Enabling fatal error in one channel will be considered
475− as fatal error mode */
476− if (umc_v6_7_query_ras_poison_mode_per_channel(adev, umc_reg_offset))
477− return false;
478− }
479−
480− return true;
531+ /* Enabling fatal error in umc instance0 channel0 will be
532+ * considered as fatal error mode
533+ */
534+ umc_reg_offset = get_umc_v6_7_reg_offset(adev, 0, 0);
535+ return !umc_v6_7_query_ras_poison_mode_per_channel(adev, umc_reg_offset);
481536 }
482537
483−const struct amdgpu_umc_ras_funcs umc_v6_7_ras_funcs = {
484− .ras_late_init = amdgpu_umc_ras_late_init,
485− .ras_fini = amdgpu_umc_ras_fini,
538+const struct amdgpu_ras_block_hw_ops umc_v6_7_ras_hw_ops = {
486539 .query_ras_error_count = umc_v6_7_query_ras_error_count,
487540 .query_ras_error_address = umc_v6_7_query_ras_error_address,
541+};
542+
543+struct amdgpu_umc_ras umc_v6_7_ras = {
544+ .ras_block = {
545+ .hw_ops = &umc_v6_7_ras_hw_ops,
546+ },
488547 .query_ras_poison_mode = umc_v6_7_query_ras_poison_mode,
489548 .ecc_info_query_ras_error_count = umc_v6_7_ecc_info_query_ras_error_count,
490549 .ecc_info_query_ras_error_address = umc_v6_7_ecc_info_query_ras_error_address,
drivers/gpu/drm/amd/amdgpu/umc_v6_7.h+24−1
@@ -41,9 +41,32 @@ · 40 unmodified lines
4141 #define UMC_V6_7_CHANNEL_INSTANCE_NUM 8
4242 /* total channel instances in one umc block */
4343 #define UMC_V6_7_TOTAL_CHANNEL_NUM (UMC_V6_7_CHANNEL_INSTANCE_NUM * UMC_V6_7_UMC_INSTANCE_NUM)
44+/* one piece of normalizing address is mapped to 8 pieces of physical address */
45+#define UMC_V6_7_NA_MAP_PA_NUM 8
46+/* R14 bit shift should be considered, double the number */
47+#define UMC_V6_7_BAD_PAGE_NUM_PER_CHANNEL (UMC_V6_7_NA_MAP_PA_NUM * 2)
48+/* The CH4 bit in SOC physical address */
49+#define UMC_V6_7_PA_CH4_BIT 12
50+/* The C2 bit in SOC physical address */
51+#define UMC_V6_7_PA_C2_BIT 17
52+/* The R14 bit in SOC physical address */
53+#define UMC_V6_7_PA_R14_BIT 34
4454 /* UMC regiser per channel offset */
4555 #define UMC_V6_7_PER_CHANNEL_OFFSET 0x400
46−extern const struct amdgpu_umc_ras_funcs umc_v6_7_ras_funcs;
56+
57+/* XOR bit 20, 25, 34 of PA into CH4 bit (bit 12 of PA),
58+ * hash bit is only effective when related setting is enabled
59+ */
60+#define CHANNEL_HASH(channel_idx, pa) (((channel_idx) >> 4) ^ \
61+ (((pa) >> 20) & 0x1ULL & adev->df.hash_status.hash_64k) ^ \
62+ (((pa) >> 25) & 0x1ULL & adev->df.hash_status.hash_2m) ^ \
63+ (((pa) >> 34) & 0x1ULL & adev->df.hash_status.hash_1g))
64+#define SET_CHANNEL_HASH(channel_idx, pa) do { \
65+ (pa) &= ~(0x1ULL << UMC_V6_7_PA_CH4_BIT); \
66+ (pa) |= (CHANNEL_HASH(channel_idx, pa) << UMC_V6_7_PA_CH4_BIT); \
67+ } while (0)
68+
69+extern struct amdgpu_umc_ras umc_v6_7_ras;
4770 extern const uint32_t
4871 umc_v6_7_channel_idx_tbl_second[UMC_V6_7_UMC_INSTANCE_NUM][UMC_V6_7_CHANNEL_INSTANCE_NUM];
4972 extern const uint32_t
drivers/gpu/drm/amd/amdgpu/umc_v8_7.c+149−24
@@ -40,13 +40,144 @@ const uint32_t · 39 unmodified lines
4040 {9, 0}, {15, 6}
4141 };
4242
43−static inline uint32_t get_umc_8_reg_offset(struct amdgpu_device *adev,
43+static inline uint32_t get_umc_v8_7_reg_offset(struct amdgpu_device *adev,
4444 uint32_t umc_inst,
4545 uint32_t ch_inst)
4646 {
4747 return adev->umc.channel_offs*ch_inst + UMC_8_INST_DIST*umc_inst;
4848 }
4949
50+static inline uint32_t get_umc_v8_7_channel_index(struct amdgpu_device *adev,
51+ uint32_t umc_inst,
52+ uint32_t ch_inst)
53+{
54+ return adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst];
55+}
56+
57+static void umc_v8_7_ecc_info_query_correctable_error_count(struct amdgpu_device *adev,
58+ uint32_t umc_inst, uint32_t ch_inst,
59+ unsigned long *error_count)
60+{
61+ uint64_t mc_umc_status;
62+ uint32_t eccinfo_table_idx;
63+ struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
64+
65+ eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst;
66+
67+ /* check for SRAM correctable error
68+ * MCUMC_STATUS is a 64 bit register
69+ */
70+ mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status;
71+ if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
72+ REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)
73+ *error_count += 1;
74+}
75+
76+static void umc_v8_7_ecc_info_querry_uncorrectable_error_count(struct amdgpu_device *adev,
77+ uint32_t umc_inst, uint32_t ch_inst,
78+ unsigned long *error_count)
79+{
80+ uint64_t mc_umc_status;
81+ uint32_t eccinfo_table_idx;
82+ struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
83+
84+ eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst;
85+
86+ /* check the MCUMC_STATUS */
87+ mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status;
88+ if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &&
89+ (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 ||
90+ REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
91+ REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 ||
92+ REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 ||
93+ REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1))
94+ *error_count += 1;
95+}
96+
97+static void umc_v8_7_ecc_info_query_ras_error_count(struct amdgpu_device *adev,
98+ void *ras_error_status)
99+{
100+ struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
101+
102+ uint32_t umc_inst = 0;
103+ uint32_t ch_inst = 0;
104+
105+ /* TODO: driver needs to toggle DF Cstate to ensure
106+ * safe access of UMC registers. Will add the protection
107+ */
108+ LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) {
109+ umc_v8_7_ecc_info_query_correctable_error_count(adev,
110+ umc_inst, ch_inst,
111+ &(err_data->ce_count));
112+ umc_v8_7_ecc_info_querry_uncorrectable_error_count(adev,
113+ umc_inst, ch_inst,
114+ &(err_data->ue_count));
115+ }
116+}
117+
118+static void umc_v8_7_ecc_info_query_error_address(struct amdgpu_device *adev,
119+ struct ras_err_data *err_data,
120+ uint32_t ch_inst,
121+ uint32_t umc_inst)
122+{
123+ uint64_t mc_umc_status, err_addr, retired_page;
124+ uint32_t channel_index;
125+ uint32_t eccinfo_table_idx;
126+ struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
127+
128+ eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst;
129+ channel_index =
130+ adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst];
131+
132+ mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status;
133+
134+ if (mc_umc_status == 0)
135+ return;
136+
137+ if (!err_data->err_addr)
138+ return;
139+
140+ /* calculate error address if ue/ce error is detected */
141+ if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
142+ (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
143+ REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)) {
144+
145+ err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_addr;
146+ err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);
147+
148+ /* translate umc channel address to soc pa, 3 parts are included */
149+ retired_page = ADDR_OF_4KB_BLOCK(err_addr) |
150+ ADDR_OF_256B_BLOCK(channel_index) |
151+ OFFSET_IN_256B_BLOCK(err_addr);
152+
153+ /* we only save ue error information currently, ce is skipped */
154+ if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC)
155+ == 1)
156+ amdgpu_umc_fill_error_record(err_data, err_addr,
157+ retired_page, channel_index, umc_inst);
158+ }
159+}
160+
161+static void umc_v8_7_ecc_info_query_ras_error_address(struct amdgpu_device *adev,
162+ void *ras_error_status)
163+{
164+ struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
165+
166+ uint32_t umc_inst = 0;
167+ uint32_t ch_inst = 0;
168+
169+ /* TODO: driver needs to toggle DF Cstate to ensure
170+ * safe access of UMC resgisters. Will add the protection
171+ * when firmware interface is ready
172+ */
173+ LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) {
174+ umc_v8_7_ecc_info_query_error_address(adev,
175+ err_data,
176+ ch_inst,
177+ umc_inst);
178+ }
179+}
180+
50181 static void umc_v8_7_clear_error_count_per_channel(struct amdgpu_device *adev,
51182 uint32_t umc_reg_offset)
52183 {
@@ -92,7 +223,7 @@ static void umc_v8_7_clear_error_count(struct amdgpu_device *adev) · 39 unmodified lines
92223 uint32_t umc_reg_offset = 0;
93224
94225 LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) {
95− umc_reg_offset = get_umc_8_reg_offset(adev,
226+ umc_reg_offset = get_umc_v8_7_reg_offset(adev,
96227 umc_inst,
97228 ch_inst);
98229
@@ -178,7 +309,7 @@ static void umc_v8_7_query_ras_error_count(struct amdgpu_device *adev, · 79 unmodified lines
178309 uint32_t umc_reg_offset = 0;
179310
180311 LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) {
181− umc_reg_offset = get_umc_8_reg_offset(adev,
312+ umc_reg_offset = get_umc_v8_7_reg_offset(adev,
182313 umc_inst,
183314 ch_inst);
184315
@@ -201,7 +332,6 @@ static void umc_v8_7_query_error_address(struct amdgpu_device *adev, · 16 unmodified lines
201332 {
202333 uint32_t lsb, mc_umc_status_addr;
203334 uint64_t mc_umc_status, err_addr, retired_page, mc_umc_addrt0;
204− struct eeprom_table_record *err_rec;
205335 uint32_t channel_index = adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst];
206336
207337 mc_umc_status_addr =
@@ -220,8 +350,6 @@ static void umc_v8_7_query_error_address(struct amdgpu_device *adev, · 12 unmodified lines
220350 return;
221351 }
222352
223− err_rec = &err_data->err_addr[err_data->err_addr_cnt];
224−
225353 /* calculate error address if ue/ce error is detected */
226354 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
227355 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
@@ -240,18 +368,9 @@ static void umc_v8_7_query_error_address(struct amdgpu_device *adev, · 12 unmodified lines
240368
241369 /* we only save ue error information currently, ce is skipped */
242370 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC)
243− == 1) {
244− err_rec->address = err_addr;
245− /* page frame address is saved */
246− err_rec->retired_page = retired_page >> AMDGPU_GPU_PAGE_SHIFT;
247− err_rec->ts = (uint64_t)ktime_get_real_seconds();
248− err_rec->err_type = AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE;
249− err_rec->cu = 0;
250− err_rec->mem_channel = channel_index;
251− err_rec->mcumc_id = umc_inst;
252−
253− err_data->err_addr_cnt++;
254− }
371+ == 1)
372+ amdgpu_umc_fill_error_record(err_data, err_addr,
373+ retired_page, channel_index, umc_inst);
255374 }
256375
257376 /* clear umc status */
@@ -268,7 +387,7 @@ static void umc_v8_7_query_ras_error_address(struct amdgpu_device *adev, · 10 unmodified lines
268387 uint32_t umc_reg_offset = 0;
269388
270389 LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) {
271− umc_reg_offset = get_umc_8_reg_offset(adev,
390+ umc_reg_offset = get_umc_v8_7_reg_offset(adev,
272391 umc_inst,
273392 ch_inst);
274393
@@ -316,7 +435,7 @@ static void umc_v8_7_err_cnt_init(struct amdgpu_device *adev) · 41 unmodified lines
316435 uint32_t umc_reg_offset = 0;
317436
318437 LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) {
319− umc_reg_offset = get_umc_8_reg_offset(adev,
438+ umc_reg_offset = get_umc_v8_7_reg_offset(adev,
320439 umc_inst,
321440 ch_inst);
322441
@@ -324,10 +443,16 @@ static void umc_v8_7_err_cnt_init(struct amdgpu_device *adev) · 1 unmodified line
324443 }
325444 }
326445
327−const struct amdgpu_umc_ras_funcs umc_v8_7_ras_funcs = {
328− .err_cnt_init = umc_v8_7_err_cnt_init,
329− .ras_late_init = amdgpu_umc_ras_late_init,
330− .ras_fini = amdgpu_umc_ras_fini,
446+const struct amdgpu_ras_block_hw_ops umc_v8_7_ras_hw_ops = {
331447 .query_ras_error_count = umc_v8_7_query_ras_error_count,
332448 .query_ras_error_address = umc_v8_7_query_ras_error_address,
333449 };
450+
451+struct amdgpu_umc_ras umc_v8_7_ras = {
452+ .ras_block = {
453+ .hw_ops = &umc_v8_7_ras_hw_ops,
454+ },
455+ .err_cnt_init = umc_v8_7_err_cnt_init,
456+ .ecc_info_query_ras_error_count = umc_v8_7_ecc_info_query_ras_error_count,
457+ .ecc_info_query_ras_error_address = umc_v8_7_ecc_info_query_ras_error_address,
458+};
drivers/gpu/drm/amd/amdgpu/umc_v8_7.h+1−1
@@ -44,7 +44,7 @@ · 43 unmodified lines
4444 /* umc ce count initial value */
4545 #define UMC_V8_7_CE_CNT_INIT (UMC_V8_7_CE_CNT_MAX - UMC_V8_7_CE_INT_THRESHOLD)
4646
47−extern const struct amdgpu_umc_ras_funcs umc_v8_7_ras_funcs;
47+extern struct amdgpu_umc_ras umc_v8_7_ras;
4848 extern const uint32_t
4949 umc_v8_7_channel_idx_tbl[UMC_V8_7_UMC_INSTANCE_NUM][UMC_V8_7_CHANNEL_INSTANCE_NUM];
5050
drivers/gpu/drm/amd/amdgpu/vi.c+1−1
@@ -1140,7 +1140,7 @@ static void vi_program_aspm(struct amdgpu_device *adev) · 1139 unmodified lines
11401140 bool bL1SS = false;
11411141 bool bClkReqSupport = true;
11421142
1143− if (!amdgpu_aspm)
1143+ if (!amdgpu_device_should_use_aspm(adev))
11441144 return;
11451145
11461146 if (adev->flags & AMD_IS_APU ||
drivers/gpu/drm/amd/amdkfd/Makefile+0−2
@@ -51,8 +51,6 @@ AMDKFD_FILES := $(AMDKFD_PATH)/kfd_module.o \ · 50 unmodified lines
5151 $(AMDKFD_PATH)/kfd_events.o \
5252 $(AMDKFD_PATH)/cik_event_interrupt.o \
5353 $(AMDKFD_PATH)/kfd_int_process_v9.o \
54− $(AMDKFD_PATH)/kfd_dbgdev.o \
55− $(AMDKFD_PATH)/kfd_dbgmgr.o \
5654 $(AMDKFD_PATH)/kfd_smi_events.o \
5755 $(AMDKFD_PATH)/kfd_crat.o
5856
drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c+1−1
@@ -110,7 +110,7 @@ static void cik_event_interrupt_wq(struct kfd_dev *dev, · 109 unmodified lines
110110 struct kfd_vm_fault_info info;
111111
112112 kfd_smi_event_update_vmfault(dev, pasid);
113− kfd_process_vm_fault(dev->dqm, pasid);
113+ kfd_dqm_evict_pasid(dev->dqm, pasid);
114114
115115 memset(&info, 0, sizeof(info));
116116 amdgpu_amdkfd_gpuvm_get_vm_fault_info(dev->adev, &info);
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c+1182−428
@@ -1,5 +1,6 @@
1+// SPDX-License-Identifier: GPL-2.0 OR MIT
12 /*
2− * Copyright 2014 Advanced Micro Devices, Inc.
3+ * Copyright 2014-2022 Advanced Micro Devices, Inc.
34 *
45 * Permission is hereby granted, free of charge, to any person obtaining a
56 * copy of this software and associated documentation files (the "Software"),
@@ -33,14 +34,16 @@ · 27 unmodified lines
3334 #include <linux/time.h>
3435 #include <linux/mm.h>
3536 #include <linux/mman.h>
37+#include <linux/ptrace.h>
3638 #include <linux/dma-buf.h>
37−#include <asm/processor.h>
39+#include <linux/fdtable.h>
40+#include <linux/processor.h>
3841 #include "kfd_priv.h"
3942 #include "kfd_device_queue_manager.h"
40−#include "kfd_dbgmgr.h"
4143 #include "kfd_svm.h"
4244 #include "amdgpu_amdkfd.h"
4345 #include "kfd_smi_events.h"
46+#include "amdgpu_dma_buf.h"
4447
4548 static long kfd_ioctl(struct file *, unsigned int, unsigned long);
4649 static int kfd_open(struct inode *, struct file *);
@@ -292,14 +295,17 @@ static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p, · 245 unmodified lines
292295 return err;
293296
294297 pr_debug("Looking for gpu id 0x%x\n", args->gpu_id);
295− dev = kfd_device_by_id(args->gpu_id);
296− if (!dev) {
297− pr_debug("Could not find gpu id 0x%x\n", args->gpu_id);
298− return -EINVAL;
299− }
300298
301299 mutex_lock(&p->mutex);
302300
301+ pdd = kfd_process_device_data_by_id(p, args->gpu_id);
302+ if (!pdd) {
303+ pr_debug("Could not find gpu id 0x%x\n", args->gpu_id);
304+ err = -EINVAL;
305+ goto err_pdd;
306+ }
307+ dev = pdd->dev;
308+
303309 pdd = kfd_bind_process_to_device(dev, p);
304310 if (IS_ERR(pdd)) {
305311 err = -ESRCH;
@@ -310,7 +316,7 @@ static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p, · 4 unmodified lines
310316 p->pasid,
311317 dev->id);
312318
313− err = pqm_create_queue(&p->pqm, dev, filep, &q_properties, &queue_id,
319+ err = pqm_create_queue(&p->pqm, dev, filep, &q_properties, &queue_id, NULL, NULL, NULL,
314320 &doorbell_offset_in_process);
315321 if (err != 0)
316322 goto err_create_queue;
@@ -344,6 +350,7 @@ static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p, · 27 unmodified lines
344350
345351 err_create_queue:
346352 err_bind_process:
353+err_pdd:
347354 mutex_unlock(&p->mutex);
348355 return err;
349356 }
@@ -490,7 +497,6 @@ static int kfd_ioctl_set_memory_policy(struct file *filep, · 140 unmodified lines
490497 struct kfd_process *p, void *data)
491498 {
492499 struct kfd_ioctl_set_memory_policy_args *args = data;
493− struct kfd_dev *dev;
494500 int err = 0;
495501 struct kfd_process_device *pdd;
496502 enum cache_policy default_policy, alternate_policy;
@@ -505,13 +511,15 @@ static int kfd_ioctl_set_memory_policy(struct file *filep, · 8 unmodified lines
505511 return -EINVAL;
506512 }
507513
508− dev = kfd_device_by_id(args->gpu_id);
509− if (!dev)
510− return -EINVAL;
511−
512514 mutex_lock(&p->mutex);
515+ pdd = kfd_process_device_data_by_id(p, args->gpu_id);
516+ if (!pdd) {
517+ pr_debug("Could not find gpu id 0x%x\n", args->gpu_id);
518+ err = -EINVAL;
519+ goto err_pdd;
520+ }
513521
514− pdd = kfd_bind_process_to_device(dev, p);
522+ pdd = kfd_bind_process_to_device(pdd->dev, p);
515523 if (IS_ERR(pdd)) {
516524 err = -ESRCH;
517525 goto out;
@@ -524,7 +532,7 @@ static int kfd_ioctl_set_memory_policy(struct file *filep, · 6 unmodified lines
524532 (args->alternate_policy == KFD_IOC_CACHE_POLICY_COHERENT)
525533 ? cache_policy_coherent : cache_policy_noncoherent;
526534
527− if (!dev->dqm->ops.set_cache_memory_policy(dev->dqm,
535+ if (!pdd->dev->dqm->ops.set_cache_memory_policy(pdd->dev->dqm,
528536 &pdd->qpd,
529537 default_policy,
530538 alternate_policy,
@@ -533,6 +541,7 @@ static int kfd_ioctl_set_memory_policy(struct file *filep, · 2 unmodified lines
533541 err = -EINVAL;
534542
535543 out:
544+err_pdd:
536545 mutex_unlock(&p->mutex);
537546
538547 return err;
@@ -542,17 +551,18 @@ static int kfd_ioctl_set_trap_handler(struct file *filep, · 3 unmodified lines
542551 struct kfd_process *p, void *data)
543552 {
544553 struct kfd_ioctl_set_trap_handler_args *args = data;
545− struct kfd_dev *dev;
546554 int err = 0;
547555 struct kfd_process_device *pdd;
548556
549− dev = kfd_device_by_id(args->gpu_id);
550− if (!dev)
551− return -EINVAL;
552−
553557 mutex_lock(&p->mutex);
554558
555− pdd = kfd_bind_process_to_device(dev, p);
559+ pdd = kfd_process_device_data_by_id(p, args->gpu_id);
560+ if (!pdd) {
561+ err = -EINVAL;
562+ goto err_pdd;
563+ }
564+
565+ pdd = kfd_bind_process_to_device(pdd->dev, p);
556566 if (IS_ERR(pdd)) {
557567 err = -ESRCH;
558568 goto out;
@@ -561,6 +571,7 @@ static int kfd_ioctl_set_trap_handler(struct file *filep, · 2 unmodified lines
561571 kfd_process_set_trap_handler(&pdd->qpd, args->tba_addr, args->tma_addr);
562572
563573 out:
574+err_pdd:
564575 mutex_unlock(&p->mutex);
565576
566577 return err;
@@ -569,289 +580,40 @@ out: · 2 unmodified lines
569580 static int kfd_ioctl_dbg_register(struct file *filep,
570581 struct kfd_process *p, void *data)
571582 {
572− struct kfd_ioctl_dbg_register_args *args = data;
573− struct kfd_dev *dev;
574− struct kfd_dbgmgr *dbgmgr_ptr;
575− struct kfd_process_device *pdd;
576− bool create_ok;
577− long status = 0;
578−
579− dev = kfd_device_by_id(args->gpu_id);
580− if (!dev)
581− return -EINVAL;
582−
583− if (dev->adev->asic_type == CHIP_CARRIZO) {
584− pr_debug("kfd_ioctl_dbg_register not supported on CZ\n");
585− return -EINVAL;
586− }
587−
588− mutex_lock(&p->mutex);
589− mutex_lock(kfd_get_dbgmgr_mutex());
590−
591− /*
592− * make sure that we have pdd, if this the first queue created for
593− * this process
594− */
595− pdd = kfd_bind_process_to_device(dev, p);
596− if (IS_ERR(pdd)) {
597− status = PTR_ERR(pdd);
598− goto out;
599− }
600−
601− if (!dev->dbgmgr) {
602− /* In case of a legal call, we have no dbgmgr yet */
603− create_ok = kfd_dbgmgr_create(&dbgmgr_ptr, dev);
604− if (create_ok) {
605− status = kfd_dbgmgr_register(dbgmgr_ptr, p);
606− if (status != 0)
607− kfd_dbgmgr_destroy(dbgmgr_ptr);
608− else
609− dev->dbgmgr = dbgmgr_ptr;
610− }
611− } else {
612− pr_debug("debugger already registered\n");
613− status = -EINVAL;
614− }
615−
616−out:
617− mutex_unlock(kfd_get_dbgmgr_mutex());
618− mutex_unlock(&p->mutex);
619−
620− return status;
583+ return -EPERM;
621584 }
622585
623586 static int kfd_ioctl_dbg_unregister(struct file *filep,
624587 struct kfd_process *p, void *data)
625588 {
626− struct kfd_ioctl_dbg_unregister_args *args = data;
627− struct kfd_dev *dev;
628− long status;
629−
630− dev = kfd_device_by_id(args->gpu_id);
631− if (!dev || !dev->dbgmgr)
632− return -EINVAL;
633−
634− if (dev->adev->asic_type == CHIP_CARRIZO) {
635− pr_debug("kfd_ioctl_dbg_unregister not supported on CZ\n");
636− return -EINVAL;
637− }
638−
639− mutex_lock(kfd_get_dbgmgr_mutex());
640−
641− status = kfd_dbgmgr_unregister(dev->dbgmgr, p);
642− if (!status) {
643− kfd_dbgmgr_destroy(dev->dbgmgr);
644− dev->dbgmgr = NULL;
645− }
646−
647− mutex_unlock(kfd_get_dbgmgr_mutex());
648−
649− return status;
589+ return -EPERM;
650590 }
651591
652−/*
653− * Parse and generate variable size data structure for address watch.
654− * Total size of the buffer and # watch points is limited in order
655− * to prevent kernel abuse. (no bearing to the much smaller HW limitation
656− * which is enforced by dbgdev module)
657− * please also note that the watch address itself are not "copied from user",
658− * since it be set into the HW in user mode values.
659− *
660− */
661592 static int kfd_ioctl_dbg_address_watch(struct file *filep,
662593 struct kfd_process *p, void *data)
663594 {
664− struct kfd_ioctl_dbg_address_watch_args *args = data;
665− struct kfd_dev *dev;
666− struct dbg_address_watch_info aw_info;
667− unsigned char *args_buff;
668− long status;
669− void __user *cmd_from_user;
670− uint64_t watch_mask_value = 0;
671− unsigned int args_idx = 0;
672−
673− memset((void *) &aw_info, 0, sizeof(struct dbg_address_watch_info));
674−
675− dev = kfd_device_by_id(args->gpu_id);
676− if (!dev)
677− return -EINVAL;
678−
679− if (dev->adev->asic_type == CHIP_CARRIZO) {
680− pr_debug("kfd_ioctl_dbg_wave_control not supported on CZ\n");
681− return -EINVAL;
682− }
683−
684− cmd_from_user = (void __user *) args->content_ptr;
685−
686− /* Validate arguments */
687−
688− if ((args->buf_size_in_bytes > MAX_ALLOWED_AW_BUFF_SIZE) ||
689− (args->buf_size_in_bytes <= sizeof(*args) + sizeof(int) * 2) ||
690− (cmd_from_user == NULL))
691− return -EINVAL;
692−
693− /* this is the actual buffer to work with */
694− args_buff = memdup_user(cmd_from_user,
695− args->buf_size_in_bytes - sizeof(*args));
696− if (IS_ERR(args_buff))
697− return PTR_ERR(args_buff);
698−
699− aw_info.process = p;
700−
701− aw_info.num_watch_points = *((uint32_t *)(&args_buff[args_idx]));
702− args_idx += sizeof(aw_info.num_watch_points);
703−
704− aw_info.watch_mode = (enum HSA_DBG_WATCH_MODE *) &args_buff[args_idx];
705− args_idx += sizeof(enum HSA_DBG_WATCH_MODE) * aw_info.num_watch_points;
706−
707− /*
708− * set watch address base pointer to point on the array base
709− * within args_buff
710− */
711− aw_info.watch_address = (uint64_t *) &args_buff[args_idx];
712−
713− /* skip over the addresses buffer */
714− args_idx += sizeof(aw_info.watch_address) * aw_info.num_watch_points;
715−
716− if (args_idx >= args->buf_size_in_bytes - sizeof(*args)) {
717− status = -EINVAL;
718− goto out;
719− }
720−
721− watch_mask_value = (uint64_t) args_buff[args_idx];
722−
723− if (watch_mask_value > 0) {
724− /*
725− * There is an array of masks.
726− * set watch mask base pointer to point on the array base
727− * within args_buff
728− */
729− aw_info.watch_mask = (uint64_t *) &args_buff[args_idx];
730−
731− /* skip over the masks buffer */
732− args_idx += sizeof(aw_info.watch_mask) *
733− aw_info.num_watch_points;
734− } else {
735− /* just the NULL mask, set to NULL and skip over it */
736− aw_info.watch_mask = NULL;
737− args_idx += sizeof(aw_info.watch_mask);
738− }
739−
740− if (args_idx >= args->buf_size_in_bytes - sizeof(args)) {
741− status = -EINVAL;
742− goto out;
743− }
744−
745− /* Currently HSA Event is not supported for DBG */
746− aw_info.watch_event = NULL;
747−
748− mutex_lock(kfd_get_dbgmgr_mutex());
749−
750− status = kfd_dbgmgr_address_watch(dev->dbgmgr, &aw_info);
751−
752− mutex_unlock(kfd_get_dbgmgr_mutex());
753−
754−out:
755− kfree(args_buff);
756−
757− return status;
595+ return -EPERM;
758596 }
759597
760598 /* Parse and generate fixed size data structure for wave control */
761599 static int kfd_ioctl_dbg_wave_control(struct file *filep,
762600 struct kfd_process *p, void *data)
763601 {
764− struct kfd_ioctl_dbg_wave_control_args *args = data;
765− struct kfd_dev *dev;
766− struct dbg_wave_control_info wac_info;
767− unsigned char *args_buff;
768− uint32_t computed_buff_size;
769− long status;
770− void __user *cmd_from_user;
771− unsigned int args_idx = 0;
772−
773− memset((void *) &wac_info, 0, sizeof(struct dbg_wave_control_info));
774−
775− /* we use compact form, independent of the packing attribute value */
776− computed_buff_size = sizeof(*args) +
777− sizeof(wac_info.mode) +
778− sizeof(wac_info.operand) +
779− sizeof(wac_info.dbgWave_msg.DbgWaveMsg) +
780− sizeof(wac_info.dbgWave_msg.MemoryVA) +
781− sizeof(wac_info.trapId);
782−
783− dev = kfd_device_by_id(args->gpu_id);
784− if (!dev)
785− return -EINVAL;
786−
787− if (dev->adev->asic_type == CHIP_CARRIZO) {
788− pr_debug("kfd_ioctl_dbg_wave_control not supported on CZ\n");
789− return -EINVAL;
790− }
791−
792− /* input size must match the computed "compact" size */
793− if (args->buf_size_in_bytes != computed_buff_size) {
794− pr_debug("size mismatch, computed : actual %u : %u\n",
795− args->buf_size_in_bytes, computed_buff_size);
796− return -EINVAL;
797− }
798−
799− cmd_from_user = (void __user *) args->content_ptr;
800−
801− if (cmd_from_user == NULL)
802− return -EINVAL;
803−
804− /* copy the entire buffer from user */
805−
806− args_buff = memdup_user(cmd_from_user,
807− args->buf_size_in_bytes - sizeof(*args));
808− if (IS_ERR(args_buff))
809− return PTR_ERR(args_buff);
810−
811− /* move ptr to the start of the "pay-load" area */
812− wac_info.process = p;
813−
814− wac_info.operand = *((enum HSA_DBG_WAVEOP *)(&args_buff[args_idx]));
815− args_idx += sizeof(wac_info.operand);
816−
817− wac_info.mode = *((enum HSA_DBG_WAVEMODE *)(&args_buff[args_idx]));
818− args_idx += sizeof(wac_info.mode);
819−
820− wac_info.trapId = *((uint32_t *)(&args_buff[args_idx]));
821− args_idx += sizeof(wac_info.trapId);
822−
823− wac_info.dbgWave_msg.DbgWaveMsg.WaveMsgInfoGen2.Value =
824− *((uint32_t *)(&args_buff[args_idx]));
825− wac_info.dbgWave_msg.MemoryVA = NULL;
826−
827− mutex_lock(kfd_get_dbgmgr_mutex());
828−
829− pr_debug("Calling dbg manager process %p, operand %u, mode %u, trapId %u, message %u\n",
830− wac_info.process, wac_info.operand,
831− wac_info.mode, wac_info.trapId,
832− wac_info.dbgWave_msg.DbgWaveMsg.WaveMsgInfoGen2.Value);
833−
834− status = kfd_dbgmgr_wave_control(dev->dbgmgr, &wac_info);
835−
836− pr_debug("Returned status of dbg manager is %ld\n", status);
837−
838− mutex_unlock(kfd_get_dbgmgr_mutex());
839−
840− kfree(args_buff);
841−
842− return status;
602+ return -EPERM;
843603 }
844604
845605 static int kfd_ioctl_get_clock_counters(struct file *filep,
846606 struct kfd_process *p, void *data)
847607 {
848608 struct kfd_ioctl_get_clock_counters_args *args = data;
849− struct kfd_dev *dev;
609+ struct kfd_process_device *pdd;
850610
851− dev = kfd_device_by_id(args->gpu_id);
852− if (dev)
611+ mutex_lock(&p->mutex);
612+ pdd = kfd_process_device_data_by_id(p, args->gpu_id);
613+ mutex_unlock(&p->mutex);
614+ if (pdd)
853615 /* Reading GPU clock counter from KGD */
854− args->gpu_clock_counter = amdgpu_amdkfd_get_gpu_clock_counter(dev->adev);
616+ args->gpu_clock_counter = amdgpu_amdkfd_get_gpu_clock_counter(pdd->dev->adev);
855617 else
856618 /* Node without GPU resource */
857619 args->gpu_clock_counter = 0;
@@ -1007,57 +769,11 @@ static int kfd_ioctl_create_event(struct file *filp, struct kfd_process *p, · 149 unmodified lines
1007769 * through the event_page_offset field.
1008770 */
1009771 if (args->event_page_offset) {
1010− struct kfd_dev *kfd;
1011− struct kfd_process_device *pdd;
1012− void *mem, *kern_addr;
1013− uint64_t size;
1014−
1015− kfd = kfd_device_by_id(GET_GPU_ID(args->event_page_offset));
1016− if (!kfd) {
1017− pr_err("Getting device by id failed in %s\n", __func__);
1018− return -EINVAL;
1019− }
1020−
1021772 mutex_lock(&p->mutex);
1022−
1023− if (p->signal_page) {
1024− pr_err("Event page is already set\n");
1025− err = -EINVAL;
1026− goto out_unlock;
1027− }
1028−
1029− pdd = kfd_bind_process_to_device(kfd, p);
1030− if (IS_ERR(pdd)) {
1031− err = PTR_ERR(pdd);
1032− goto out_unlock;
1033− }
1034−
1035− mem = kfd_process_device_translate_handle(pdd,
1036− GET_IDR_HANDLE(args->event_page_offset));
1037− if (!mem) {
1038− pr_err("Can't find BO, offset is 0x%llx\n",
1039− args->event_page_offset);
1040− err = -EINVAL;
1041− goto out_unlock;
1042− }
1043−
1044− err = amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(kfd->adev,
1045− mem, &kern_addr, &size);
1046− if (err) {
1047− pr_err("Failed to map event page to kernel\n");
1048− goto out_unlock;
1049− }
1050−
1051− err = kfd_event_page_set(p, kern_addr, size);
1052− if (err) {
1053− pr_err("Failed to set event page\n");
1054− amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(kfd->adev, mem);
1055− goto out_unlock;
1056− }
1057−
1058− p->signal_handle = args->event_page_offset;
1059−
773+ err = kfd_kmap_event_page(p, args->event_page_offset);
1060774 mutex_unlock(&p->mutex);
775+ if (err)
776+ return err;
1061777 }
1062778
1063779 err = kfd_event_create(filp, p, args->event_type,
@@ -1066,10 +782,7 @@ static int kfd_ioctl_create_event(struct file *filp, struct kfd_process *p, · 2 unmodified lines
1066782 &args->event_page_offset,
1067783 &args->event_slot_index);
1068784
1069− return err;
1070−
1071−out_unlock:
1072− mutex_unlock(&p->mutex);
785+ pr_debug("Created event (id:0x%08x) (%s)\n", args->event_id, __func__);
1073786 return err;
1074787 }
1075788
@@ -1118,11 +831,13 @@ static int kfd_ioctl_set_scratch_backing_va(struct file *filep, · 42 unmodified lines
1118831 struct kfd_dev *dev;
1119832 long err;
1120833
1121− dev = kfd_device_by_id(args->gpu_id);
1122− if (!dev)
1123− return -EINVAL;
1124−
1125834 mutex_lock(&p->mutex);
835+ pdd = kfd_process_device_data_by_id(p, args->gpu_id);
836+ if (!pdd) {
837+ err = -EINVAL;
838+ goto err_pdd;
839+ }
840+ dev = pdd->dev;
1126841
1127842 pdd = kfd_bind_process_to_device(dev, p);
1128843 if (IS_ERR(pdd)) {
@@ -1142,6 +857,7 @@ static int kfd_ioctl_set_scratch_backing_va(struct file *filep, · 13 unmodified lines
1142857 return 0;
1143858
1144859 bind_process_to_device_fail:
860+err_pdd:
1145861 mutex_unlock(&p->mutex);
1146862 return err;
1147863 }
@@ -1150,15 +866,17 @@ static int kfd_ioctl_get_tile_config(struct file *filep, · 2 unmodified lines
1150866 struct kfd_process *p, void *data)
1151867 {
1152868 struct kfd_ioctl_get_tile_config_args *args = data;
1153− struct kfd_dev *dev;
869+ struct kfd_process_device *pdd;
1154870 struct tile_config config;
1155871 int err = 0;
1156872
1157− dev = kfd_device_by_id(args->gpu_id);
1158− if (!dev)
873+ mutex_lock(&p->mutex);
874+ pdd = kfd_process_device_data_by_id(p, args->gpu_id);
875+ mutex_unlock(&p->mutex);
876+ if (!pdd)
1159877 return -EINVAL;
1160878
1161− amdgpu_amdkfd_get_tile_config(dev->adev, &config);
879+ amdgpu_amdkfd_get_tile_config(pdd->dev->adev, &config);
1162880
1163881 args->gb_addr_config = config.gb_addr_config;
1164882 args->num_banks = config.num_banks;
@@ -1193,40 +911,37 @@ static int kfd_ioctl_acquire_vm(struct file *filep, struct kfd_process *p, · 28 unmodified lines
1193911 {
1194912 struct kfd_ioctl_acquire_vm_args *args = data;
1195913 struct kfd_process_device *pdd;
1196− struct kfd_dev *dev;
1197914 struct file *drm_file;
1198915 int ret;
1199916
1200− dev = kfd_device_by_id(args->gpu_id);
1201− if (!dev)
1202− return -EINVAL;
1203−
1204917 drm_file = fget(args->drm_fd);
1205918 if (!drm_file)
1206919 return -EINVAL;
1207920
1208921 mutex_lock(&p->mutex);
1209−
1210− pdd = kfd_get_process_device_data(dev, p);
922+ pdd = kfd_process_device_data_by_id(p, args->gpu_id);
1211923 if (!pdd) {
1212924 ret = -EINVAL;
1213− goto err_unlock;
925+ goto err_pdd;
1214926 }
1215927
1216928 if (pdd->drm_file) {
1217929 ret = pdd->drm_file == drm_file ? 0 : -EBUSY;
1218− goto err_unlock;
930+ goto err_drm_file;
1219931 }
1220932
1221933 ret = kfd_process_device_init_vm(pdd, drm_file);
1222934 if (ret)
1223935 goto err_unlock;
936+
1224937 /* On success, the PDD keeps the drm_file reference */
1225938 mutex_unlock(&p->mutex);
1226939
1227940 return 0;
1228941
1229942 err_unlock:
943+err_pdd:
944+err_drm_file:
1230945 mutex_unlock(&p->mutex);
1231946 fput(drm_file);
1232947 return ret;
@@ -1283,19 +998,23 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, · 50 unmodified lines
1283998 }
1284999 mutex_unlock(&p->svms.lock);
12851000 #endif
1286− dev = kfd_device_by_id(args->gpu_id);
1287− if (!dev)
1288− return -EINVAL;
1001+ mutex_lock(&p->mutex);
1002+ pdd = kfd_process_device_data_by_id(p, args->gpu_id);
1003+ if (!pdd) {
1004+ err = -EINVAL;
1005+ goto err_pdd;
1006+ }
1007+
1008+ dev = pdd->dev;
12891009
12901010 if ((flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC) &&
12911011 (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) &&
12921012 !kfd_dev_is_large_bar(dev)) {
12931013 pr_err("Alloc host visible vram on small bar is not allowed\n");
1294− return -EINVAL;
1014+ err = -EINVAL;
1015+ goto err_large_bar;
12951016 }
12961017
1297− mutex_lock(&p->mutex);
1298−
12991018 pdd = kfd_bind_process_to_device(dev, p);
13001019 if (IS_ERR(pdd)) {
13011020 err = PTR_ERR(pdd);
@@ -1323,7 +1042,7 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, · 21 unmodified lines
13231042 err = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
13241043 dev->adev, args->va_addr, args->size,
13251044 pdd->drm_priv, (struct kgd_mem **) &mem, &offset,
1326− flags);
1045+ flags, false);
13271046
13281047 if (err)
13291048 goto err_unlock;
@@ -1356,6 +1075,8 @@ err_free: · 26 unmodified lines
13561075 amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->adev, (struct kgd_mem *)mem,
13571076 pdd->drm_priv, NULL);
13581077 err_unlock:
1078+err_pdd:
1079+err_large_bar:
13591080 mutex_unlock(&p->mutex);
13601081 return err;
13611082 }
@@ -1366,14 +1087,9 @@ static int kfd_ioctl_free_memory_of_gpu(struct file *filep, · 4 unmodified lines
13661087 struct kfd_ioctl_free_memory_of_gpu_args *args = data;
13671088 struct kfd_process_device *pdd;
13681089 void *mem;
1369− struct kfd_dev *dev;
13701090 int ret;
13711091 uint64_t size = 0;
13721092
1373− dev = kfd_device_by_id(GET_GPU_ID(args->handle));
1374− if (!dev)
1375− return -EINVAL;
1376−
13771093 mutex_lock(&p->mutex);
13781094 /*
13791095 * Safeguard to prevent user space from freeing signal BO.
@@ -1385,11 +1101,11 @@ static int kfd_ioctl_free_memory_of_gpu(struct file *filep, · 5 unmodified lines
13851101 goto err_unlock;
13861102 }
13871103
1388− pdd = kfd_get_process_device_data(dev, p);
1104+ pdd = kfd_process_device_data_by_id(p, GET_GPU_ID(args->handle));
13891105 if (!pdd) {
13901106 pr_err("Process device data doesn't exist\n");
13911107 ret = -EINVAL;
1392− goto err_unlock;
1108+ goto err_pdd;
13931109 }
13941110
13951111 mem = kfd_process_device_translate_handle(
@@ -1399,7 +1115,7 @@ static int kfd_ioctl_free_memory_of_gpu(struct file *filep, · 3 unmodified lines
13991115 goto err_unlock;
14001116 }
14011117
1402− ret = amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->adev,
1118+ ret = amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev,
14031119 (struct kgd_mem *)mem, pdd->drm_priv, &size);
14041120
14051121 /* If freeing the buffer failed, leave the handle in place for
@@ -1412,26 +1128,31 @@ static int kfd_ioctl_free_memory_of_gpu(struct file *filep, · 6 unmodified lines
14121128 WRITE_ONCE(pdd->vram_usage, pdd->vram_usage - size);
14131129
14141130 err_unlock:
1131+err_pdd:
14151132 mutex_unlock(&p->mutex);
14161133 return ret;
14171134 }
14181135
1136+static bool kfd_flush_tlb_after_unmap(struct kfd_dev *dev)
1137+{
1138+ return KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 2) ||
1139+ (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 1) &&
1140+ dev->adev->sdma.instance[0].fw_version >= 18) ||
1141+ KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 0);
1142+}
1143+
14191144 static int kfd_ioctl_map_memory_to_gpu(struct file *filep,
14201145 struct kfd_process *p, void *data)
14211146 {
14221147 struct kfd_ioctl_map_memory_to_gpu_args *args = data;
14231148 struct kfd_process_device *pdd, *peer_pdd;
14241149 void *mem;
1425− struct kfd_dev *dev, *peer;
1150+ struct kfd_dev *dev;
14261151 long err = 0;
14271152 int i;
14281153 uint32_t *devices_arr = NULL;
14291154 bool table_freed = false;
14301155
1431− dev = kfd_device_by_id(GET_GPU_ID(args->handle));
1432− if (!dev)
1433− return -EINVAL;
1434−
14351156 if (!args->n_devices) {
14361157 pr_debug("Device IDs array empty\n");
14371158 return -EINVAL;
@@ -1455,6 +1176,12 @@ static int kfd_ioctl_map_memory_to_gpu(struct file *filep, · 17 unmodified lines
14551176 }
14561177
14571178 mutex_lock(&p->mutex);
1179+ pdd = kfd_process_device_data_by_id(p, GET_GPU_ID(args->handle));
1180+ if (!pdd) {
1181+ err = -EINVAL;
1182+ goto get_process_device_data_failed;
1183+ }
1184+ dev = pdd->dev;
14581185
14591186 pdd = kfd_bind_process_to_device(dev, p);
14601187 if (IS_ERR(pdd)) {
@@ -1470,21 +1197,22 @@ static int kfd_ioctl_map_memory_to_gpu(struct file *filep, · 9 unmodified lines
14701197 }
14711198
14721199 for (i = args->n_success; i < args->n_devices; i++) {
1473− peer = kfd_device_by_id(devices_arr[i]);
1474− if (!peer) {
1200+ peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]);
1201+ if (!peer_pdd) {
14751202 pr_debug("Getting device by id failed for 0x%x\n",
14761203 devices_arr[i]);
14771204 err = -EINVAL;
14781205 goto get_mem_obj_from_handle_failed;
14791206 }
14801207
1481− peer_pdd = kfd_bind_process_to_device(peer, p);
1208+ peer_pdd = kfd_bind_process_to_device(peer_pdd->dev, p);
14821209 if (IS_ERR(peer_pdd)) {
14831210 err = PTR_ERR(peer_pdd);
14841211 goto get_mem_obj_from_handle_failed;
14851212 }
1213+
14861214 err = amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
1487− peer->adev, (struct kgd_mem *)mem,
1215+ peer_pdd->dev->adev, (struct kgd_mem *)mem,
14881216 peer_pdd->drm_priv, &table_freed);
14891217 if (err) {
14901218 pr_err("Failed to map to gpu %d/%d\n",
@@ -1503,12 +1231,9 @@ static int kfd_ioctl_map_memory_to_gpu(struct file *filep, · 12 unmodified lines
15031231 }
15041232
15051233 /* Flush TLBs after waiting for the page table updates to complete */
1506− if (table_freed) {
1234+ if (table_freed || !kfd_flush_tlb_after_unmap(dev)) {
15071235 for (i = 0; i < args->n_devices; i++) {
1508− peer = kfd_device_by_id(devices_arr[i]);
1509− if (WARN_ON_ONCE(!peer))
1510− continue;
1511− peer_pdd = kfd_get_process_device_data(peer, p);
1236+ peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]);
15121237 if (WARN_ON_ONCE(!peer_pdd))
15131238 continue;
15141239 kfd_flush_tlb(peer_pdd, TLB_FLUSH_LEGACY);
@@ -1518,6 +1243,7 @@ static int kfd_ioctl_map_memory_to_gpu(struct file *filep, · 3 unmodified lines
15181243
15191244 return err;
15201245
1246+get_process_device_data_failed:
15211247 bind_process_to_device_failed:
15221248 get_mem_obj_from_handle_failed:
15231249 map_memory_to_gpu_failed:
@@ -1535,14 +1261,9 @@ static int kfd_ioctl_unmap_memory_from_gpu(struct file *filep, · 11 unmodified lines
15351261 struct kfd_ioctl_unmap_memory_from_gpu_args *args = data;
15361262 struct kfd_process_device *pdd, *peer_pdd;
15371263 void *mem;
1538− struct kfd_dev *dev, *peer;
15391264 long err = 0;
15401265 uint32_t *devices_arr = NULL, i;
15411266
1542− dev = kfd_device_by_id(GET_GPU_ID(args->handle));
1543− if (!dev)
1544− return -EINVAL;
1545−
15461267 if (!args->n_devices) {
15471268 pr_debug("Device IDs array empty\n");
15481269 return -EINVAL;
@@ -1566,8 +1287,7 @@ static int kfd_ioctl_unmap_memory_from_gpu(struct file *filep, · 17 unmodified lines
15661287 }
15671288
15681289 mutex_lock(&p->mutex);
1569−
1570− pdd = kfd_get_process_device_data(dev, p);
1290+ pdd = kfd_process_device_data_by_id(p, GET_GPU_ID(args->handle));
15711291 if (!pdd) {
15721292 err = -EINVAL;
15731293 goto bind_process_to_device_failed;
@@ -1581,19 +1301,13 @@ static int kfd_ioctl_unmap_memory_from_gpu(struct file *filep, · 7 unmodified lines
15811301 }
15821302
15831303 for (i = args->n_success; i < args->n_devices; i++) {
1584− peer = kfd_device_by_id(devices_arr[i]);
1585− if (!peer) {
1586− err = -EINVAL;
1587− goto get_mem_obj_from_handle_failed;
1588− }
1589−
1590− peer_pdd = kfd_get_process_device_data(peer, p);
1304+ peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]);
15911305 if (!peer_pdd) {
1592− err = -ENODEV;
1306+ err = -EINVAL;
15931307 goto get_mem_obj_from_handle_failed;
15941308 }
15951309 err = amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
1596− peer->adev, (struct kgd_mem *)mem, peer_pdd->drm_priv);
1310+ peer_pdd->dev->adev, (struct kgd_mem *)mem, peer_pdd->drm_priv);
15971311 if (err) {
15981312 pr_err("Failed to unmap from gpu %d/%d\n",
15991313 i, args->n_devices);
@@ -1603,8 +1317,8 @@ static int kfd_ioctl_unmap_memory_from_gpu(struct file *filep, · 3 unmodified lines
16031317 }
16041318 mutex_unlock(&p->mutex);
16051319
1606− if (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 2)) {
1607− err = amdgpu_amdkfd_gpuvm_sync_memory(dev->adev,
1320+ if (kfd_flush_tlb_after_unmap(pdd->dev)) {
1321+ err = amdgpu_amdkfd_gpuvm_sync_memory(pdd->dev->adev,
16081322 (struct kgd_mem *) mem, true);
16091323 if (err) {
16101324 pr_debug("Sync memory failed, wait interrupted by user signal\n");
@@ -1613,10 +1327,7 @@ static int kfd_ioctl_unmap_memory_from_gpu(struct file *filep, · 2 unmodified lines
16131327
16141328 /* Flush TLBs after waiting for the page table updates to complete */
16151329 for (i = 0; i < args->n_devices; i++) {
1616− peer = kfd_device_by_id(devices_arr[i]);
1617− if (WARN_ON_ONCE(!peer))
1618− continue;
1619− peer_pdd = kfd_get_process_device_data(peer, p);
1330+ peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]);
16201331 if (WARN_ON_ONCE(!peer_pdd))
16211332 continue;
16221333 kfd_flush_tlb(peer_pdd, TLB_FLUSH_HEAVYWEIGHT);
@@ -1736,29 +1447,29 @@ static int kfd_ioctl_import_dmabuf(struct file *filep, · 113 unmodified lines
17361447 struct kfd_ioctl_import_dmabuf_args *args = data;
17371448 struct kfd_process_device *pdd;
17381449 struct dma_buf *dmabuf;
1739− struct kfd_dev *dev;
17401450 int idr_handle;
17411451 uint64_t size;
17421452 void *mem;
17431453 int r;
17441454
1745− dev = kfd_device_by_id(args->gpu_id);
1746− if (!dev)
1747− return -EINVAL;
1748−
17491455 dmabuf = dma_buf_get(args->dmabuf_fd);
17501456 if (IS_ERR(dmabuf))
17511457 return PTR_ERR(dmabuf);
17521458
17531459 mutex_lock(&p->mutex);
1460+ pdd = kfd_process_device_data_by_id(p, args->gpu_id);
1461+ if (!pdd) {
1462+ r = -EINVAL;
1463+ goto err_unlock;
1464+ }
17541465
1755− pdd = kfd_bind_process_to_device(dev, p);
1466+ pdd = kfd_bind_process_to_device(pdd->dev, p);
17561467 if (IS_ERR(pdd)) {
17571468 r = PTR_ERR(pdd);
17581469 goto err_unlock;
17591470 }
17601471
1761− r = amdgpu_amdkfd_gpuvm_import_dmabuf(dev->adev, dmabuf,
1472+ r = amdgpu_amdkfd_gpuvm_import_dmabuf(pdd->dev->adev, dmabuf,
17621473 args->va_addr, pdd->drm_priv,
17631474 (struct kgd_mem **)&mem, &size,
17641475 NULL);
@@ -1779,7 +1490,7 @@ static int kfd_ioctl_import_dmabuf(struct file *filep, · 14 unmodified lines
17791490 return 0;
17801491
17811492 err_free:
1782− amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->adev, (struct kgd_mem *)mem,
1493+ amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, (struct kgd_mem *)mem,
17831494 pdd->drm_priv, NULL);
17841495 err_unlock:
17851496 mutex_unlock(&p->mutex);
@@ -1792,13 +1503,16 @@ static int kfd_ioctl_smi_events(struct file *filep, · 6 unmodified lines
17921503 struct kfd_process *p, void *data)
17931504 {
17941505 struct kfd_ioctl_smi_events_args *args = data;
1795− struct kfd_dev *dev;
1506+ struct kfd_process_device *pdd;
17961507
1797− dev = kfd_device_by_id(args->gpuid);
1798− if (!dev)
1508+ mutex_lock(&p->mutex);
1509+
1510+ pdd = kfd_process_device_data_by_id(p, args->gpuid);
1511+ mutex_unlock(&p->mutex);
1512+ if (!pdd)
17991513 return -EINVAL;
18001514
1801− return kfd_smi_event_open(dev, &args->anon_fd);
1515+ return kfd_smi_event_open(pdd->dev, &args->anon_fd);
18021516 }
18031517
18041518 static int kfd_ioctl_set_xnack_mode(struct file *filep,
@@ -1840,13 +1554,9 @@ static int kfd_ioctl_svm(struct file *filep, struct kfd_process *p, void *data) · 35 unmodified lines
18401554 if (!args->start_addr || !args->size)
18411555 return -EINVAL;
18421556
1843− mutex_lock(&p->mutex);
1844−
18451557 r = svm_ioctl(p, args->op, args->start_addr, args->size, args->nattr,
18461558 args->attrs);
18471559
1848− mutex_unlock(&p->mutex);
1849−
18501560 return r;
18511561 }
18521562 #else
@@ -1856,12 +1566,1030 @@ static int kfd_ioctl_svm(struct file *filep, struct kfd_process *p, void *data) · 3 unmodified lines
18561566 }
18571567 #endif
18581568
1859−#define AMDKFD_IOCTL_DEF(ioctl, _func, _flags) \
1860− [_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, \
1861− .cmd_drv = 0, .name = #ioctl}
1569+static int criu_checkpoint_process(struct kfd_process *p,
1570+ uint8_t __user *user_priv_data,
1571+ uint64_t *priv_offset)
1572+{
1573+ struct kfd_criu_process_priv_data process_priv;
1574+ int ret;
18621575
1863−/** Ioctl table */
1864−static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = {
1576+ memset(&process_priv, 0, sizeof(process_priv));
1577+
1578+ process_priv.version = KFD_CRIU_PRIV_VERSION;
1579+ /* For CR, we don't consider negative xnack mode which is used for
1580+ * querying without changing it, here 0 simply means disabled and 1
1581+ * means enabled so retry for finding a valid PTE.
1582+ */
1583+ process_priv.xnack_mode = p->xnack_enabled ? 1 : 0;
1584+
1585+ ret = copy_to_user(user_priv_data + *priv_offset,
1586+ &process_priv, sizeof(process_priv));
1587+
1588+ if (ret) {
1589+ pr_err("Failed to copy process information to user\n");
1590+ ret = -EFAULT;
1591+ }
1592+
1593+ *priv_offset += sizeof(process_priv);
1594+ return ret;
1595+}
1596+
1597+static int criu_checkpoint_devices(struct kfd_process *p,
1598+ uint32_t num_devices,
1599+ uint8_t __user *user_addr,
1600+ uint8_t __user *user_priv_data,
1601+ uint64_t *priv_offset)
1602+{
1603+ struct kfd_criu_device_priv_data *device_priv = NULL;
1604+ struct kfd_criu_device_bucket *device_buckets = NULL;
1605+ int ret = 0, i;
1606+
1607+ device_buckets = kvzalloc(num_devices * sizeof(*device_buckets), GFP_KERNEL);
1608+ if (!device_buckets) {
1609+ ret = -ENOMEM;
1610+ goto exit;
1611+ }
1612+
1613+ device_priv = kvzalloc(num_devices * sizeof(*device_priv), GFP_KERNEL);
1614+ if (!device_priv) {
1615+ ret = -ENOMEM;
1616+ goto exit;
1617+ }
1618+
1619+ for (i = 0; i < num_devices; i++) {
1620+ struct kfd_process_device *pdd = p->pdds[i];
1621+
1622+ device_buckets[i].user_gpu_id = pdd->user_gpu_id;
1623+ device_buckets[i].actual_gpu_id = pdd->dev->id;
1624+
1625+ /*
1626+ * priv_data does not contain useful information for now and is reserved for
1627+ * future use, so we do not set its contents.
1628+ */
1629+ }
1630+
1631+ ret = copy_to_user(user_addr, device_buckets, num_devices * sizeof(*device_buckets));
1632+ if (ret) {
1633+ pr_err("Failed to copy device information to user\n");
1634+ ret = -EFAULT;
1635+ goto exit;
1636+ }
1637+
1638+ ret = copy_to_user(user_priv_data + *priv_offset,
1639+ device_priv,
1640+ num_devices * sizeof(*device_priv));
1641+ if (ret) {
1642+ pr_err("Failed to copy device information to user\n");
1643+ ret = -EFAULT;
1644+ }
1645+ *priv_offset += num_devices * sizeof(*device_priv);
1646+
1647+exit:
1648+ kvfree(device_buckets);
1649+ kvfree(device_priv);
1650+ return ret;
1651+}
1652+
1653+static uint32_t get_process_num_bos(struct kfd_process *p)
1654+{
1655+ uint32_t num_of_bos = 0;
1656+ int i;
1657+
1658+ /* Run over all PDDs of the process */
1659+ for (i = 0; i < p->n_pdds; i++) {
1660+ struct kfd_process_device *pdd = p->pdds[i];
1661+ void *mem;
1662+ int id;
1663+
1664+ idr_for_each_entry(&pdd->alloc_idr, mem, id) {
1665+ struct kgd_mem *kgd_mem = (struct kgd_mem *)mem;
1666+
1667+ if ((uint64_t)kgd_mem->va > pdd->gpuvm_base)
1668+ num_of_bos++;
1669+ }
1670+ }
1671+ return num_of_bos;
1672+}
1673+
1674+static int criu_get_prime_handle(struct drm_gem_object *gobj, int flags,
1675+ u32 *shared_fd)
1676+{
1677+ struct dma_buf *dmabuf;
1678+ int ret;
1679+
1680+ dmabuf = amdgpu_gem_prime_export(gobj, flags);
1681+ if (IS_ERR(dmabuf)) {
1682+ ret = PTR_ERR(dmabuf);
1683+ pr_err("dmabuf export failed for the BO\n");
1684+ return ret;
1685+ }
1686+
1687+ ret = dma_buf_fd(dmabuf, flags);
1688+ if (ret < 0) {
1689+ pr_err("dmabuf create fd failed, ret:%d\n", ret);
1690+ goto out_free_dmabuf;
1691+ }
1692+
1693+ *shared_fd = ret;
1694+ return 0;
1695+
1696+out_free_dmabuf:
1697+ dma_buf_put(dmabuf);
1698+ return ret;
1699+}
1700+
1701+static int criu_checkpoint_bos(struct kfd_process *p,
1702+ uint32_t num_bos,
1703+ uint8_t __user *user_bos,
1704+ uint8_t __user *user_priv_data,
1705+ uint64_t *priv_offset)
1706+{
1707+ struct kfd_criu_bo_bucket *bo_buckets;
1708+ struct kfd_criu_bo_priv_data *bo_privs;
1709+ int ret = 0, pdd_index, bo_index = 0, id;
1710+ void *mem;
1711+
1712+ bo_buckets = kvzalloc(num_bos * sizeof(*bo_buckets), GFP_KERNEL);
1713+ if (!bo_buckets)
1714+ return -ENOMEM;
1715+
1716+ bo_privs = kvzalloc(num_bos * sizeof(*bo_privs), GFP_KERNEL);
1717+ if (!bo_privs) {
1718+ ret = -ENOMEM;
1719+ goto exit;
1720+ }
1721+
1722+ for (pdd_index = 0; pdd_index < p->n_pdds; pdd_index++) {
1723+ struct kfd_process_device *pdd = p->pdds[pdd_index];
1724+ struct amdgpu_bo *dumper_bo;
1725+ struct kgd_mem *kgd_mem;
1726+
1727+ idr_for_each_entry(&pdd->alloc_idr, mem, id) {
1728+ struct kfd_criu_bo_bucket *bo_bucket;
1729+ struct kfd_criu_bo_priv_data *bo_priv;
1730+ int i, dev_idx = 0;
1731+
1732+ if (!mem) {
1733+ ret = -ENOMEM;
1734+ goto exit;
1735+ }
1736+
1737+ kgd_mem = (struct kgd_mem *)mem;
1738+ dumper_bo = kgd_mem->bo;
1739+
1740+ if ((uint64_t)kgd_mem->va <= pdd->gpuvm_base)
1741+ continue;
1742+
1743+ bo_bucket = &bo_buckets[bo_index];
1744+ bo_priv = &bo_privs[bo_index];
1745+
1746+ bo_bucket->gpu_id = pdd->user_gpu_id;
1747+ bo_bucket->addr = (uint64_t)kgd_mem->va;
1748+ bo_bucket->size = amdgpu_bo_size(dumper_bo);
1749+ bo_bucket->alloc_flags = (uint32_t)kgd_mem->alloc_flags;
1750+ bo_priv->idr_handle = id;
1751+
1752+ if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
1753+ ret = amdgpu_ttm_tt_get_userptr(&dumper_bo->tbo,
1754+ &bo_priv->user_addr);
1755+ if (ret) {
1756+ pr_err("Failed to obtain user address for user-pointer bo\n");
1757+ goto exit;
1758+ }
1759+ }
1760+ if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
1761+ ret = criu_get_prime_handle(&dumper_bo->tbo.base,
1762+ bo_bucket->alloc_flags &
1763+ KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? DRM_RDWR : 0,
1764+ &bo_bucket->dmabuf_fd);
1765+ if (ret)
1766+ goto exit;
1767+ }
1768+ if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL)
1769+ bo_bucket->offset = KFD_MMAP_TYPE_DOORBELL |
1770+ KFD_MMAP_GPU_ID(pdd->dev->id);
1771+ else if (bo_bucket->alloc_flags &
1772+ KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)
1773+ bo_bucket->offset = KFD_MMAP_TYPE_MMIO |
1774+ KFD_MMAP_GPU_ID(pdd->dev->id);
1775+ else
1776+ bo_bucket->offset = amdgpu_bo_mmap_offset(dumper_bo);
1777+
1778+ for (i = 0; i < p->n_pdds; i++) {
1779+ if (amdgpu_amdkfd_bo_mapped_to_dev(p->pdds[i]->dev->adev, kgd_mem))
1780+ bo_priv->mapped_gpuids[dev_idx++] = p->pdds[i]->user_gpu_id;
1781+ }
1782+
1783+ pr_debug("bo_size = 0x%llx, bo_addr = 0x%llx bo_offset = 0x%llx\n"
1784+ "gpu_id = 0x%x alloc_flags = 0x%x idr_handle = 0x%x",
1785+ bo_bucket->size,
1786+ bo_bucket->addr,
1787+ bo_bucket->offset,
1788+ bo_bucket->gpu_id,
1789+ bo_bucket->alloc_flags,
1790+ bo_priv->idr_handle);
1791+ bo_index++;
1792+ }
1793+ }
1794+
1795+ ret = copy_to_user(user_bos, bo_buckets, num_bos * sizeof(*bo_buckets));
1796+ if (ret) {
1797+ pr_err("Failed to copy BO information to user\n");
1798+ ret = -EFAULT;
1799+ goto exit;
1800+ }
1801+
1802+ ret = copy_to_user(user_priv_data + *priv_offset, bo_privs, num_bos * sizeof(*bo_privs));
1803+ if (ret) {
1804+ pr_err("Failed to copy BO priv information to user\n");
1805+ ret = -EFAULT;
1806+ goto exit;
1807+ }
1808+
1809+ *priv_offset += num_bos * sizeof(*bo_privs);
1810+
1811+exit:
1812+ while (ret && bo_index--) {
1813+ if (bo_buckets[bo_index].alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM)
1814+ close_fd(bo_buckets[bo_index].dmabuf_fd);
1815+ }
1816+
1817+ kvfree(bo_buckets);
1818+ kvfree(bo_privs);
1819+ return ret;
1820+}
1821+
1822+static int criu_get_process_object_info(struct kfd_process *p,
1823+ uint32_t *num_devices,
1824+ uint32_t *num_bos,
1825+ uint32_t *num_objects,
1826+ uint64_t *objs_priv_size)
1827+{
1828+ uint64_t queues_priv_data_size, svm_priv_data_size, priv_size;
1829+ uint32_t num_queues, num_events, num_svm_ranges;
1830+ int ret;
1831+
1832+ *num_devices = p->n_pdds;
1833+ *num_bos = get_process_num_bos(p);
1834+
1835+ ret = kfd_process_get_queue_info(p, &num_queues, &queues_priv_data_size);
1836+ if (ret)
1837+ return ret;
1838+
1839+ num_events = kfd_get_num_events(p);
1840+
1841+ ret = svm_range_get_info(p, &num_svm_ranges, &svm_priv_data_size);
1842+ if (ret)
1843+ return ret;
1844+
1845+ *num_objects = num_queues + num_events + num_svm_ranges;
1846+
1847+ if (objs_priv_size) {
1848+ priv_size = sizeof(struct kfd_criu_process_priv_data);
1849+ priv_size += *num_devices * sizeof(struct kfd_criu_device_priv_data);
1850+ priv_size += *num_bos * sizeof(struct kfd_criu_bo_priv_data);
1851+ priv_size += queues_priv_data_size;
1852+ priv_size += num_events * sizeof(struct kfd_criu_event_priv_data);
1853+ priv_size += svm_priv_data_size;
1854+ *objs_priv_size = priv_size;
1855+ }
1856+ return 0;
1857+}
1858+
1859+static int criu_checkpoint(struct file *filep,
1860+ struct kfd_process *p,
1861+ struct kfd_ioctl_criu_args *args)
1862+{
1863+ int ret;
1864+ uint32_t num_devices, num_bos, num_objects;
1865+ uint64_t priv_size, priv_offset = 0;
1866+
1867+ if (!args->devices || !args->bos || !args->priv_data)
1868+ return -EINVAL;
1869+
1870+ mutex_lock(&p->mutex);
1871+
1872+ if (!p->n_pdds) {
1873+ pr_err("No pdd for given process\n");
1874+ ret = -ENODEV;
1875+ goto exit_unlock;
1876+ }
1877+
1878+ /* Confirm all process queues are evicted */
1879+ if (!p->queues_paused) {
1880+ pr_err("Cannot dump process when queues are not in evicted state\n");
1881+ /* CRIU plugin did not call op PROCESS_INFO before checkpointing */
1882+ ret = -EINVAL;
1883+ goto exit_unlock;
1884+ }
1885+
1886+ ret = criu_get_process_object_info(p, &num_devices, &num_bos, &num_objects, &priv_size);
1887+ if (ret)
1888+ goto exit_unlock;
1889+
1890+ if (num_devices != args->num_devices ||
1891+ num_bos != args->num_bos ||
1892+ num_objects != args->num_objects ||
1893+ priv_size != args->priv_data_size) {
1894+
1895+ ret = -EINVAL;
1896+ goto exit_unlock;
1897+ }
1898+
1899+ /* each function will store private data inside priv_data and adjust priv_offset */
1900+ ret = criu_checkpoint_process(p, (uint8_t __user *)args->priv_data, &priv_offset);
1901+ if (ret)
1902+ goto exit_unlock;
1903+
1904+ ret = criu_checkpoint_devices(p, num_devices, (uint8_t __user *)args->devices,
1905+ (uint8_t __user *)args->priv_data, &priv_offset);
1906+ if (ret)
1907+ goto exit_unlock;
1908+
1909+ ret = criu_checkpoint_bos(p, num_bos, (uint8_t __user *)args->bos,
1910+ (uint8_t __user *)args->priv_data, &priv_offset);
1911+ if (ret)
1912+ goto exit_unlock;
1913+
1914+ if (num_objects) {
1915+ ret = kfd_criu_checkpoint_queues(p, (uint8_t __user *)args->priv_data,
1916+ &priv_offset);
1917+ if (ret)
1918+ goto close_bo_fds;
1919+
1920+ ret = kfd_criu_checkpoint_events(p, (uint8_t __user *)args->priv_data,
1921+ &priv_offset);
1922+ if (ret)
1923+ goto close_bo_fds;
1924+
1925+ ret = kfd_criu_checkpoint_svm(p, (uint8_t __user *)args->priv_data, &priv_offset);
1926+ if (ret)
1927+ goto close_bo_fds;
1928+ }
1929+
1930+close_bo_fds:
1931+ if (ret) {
1932+ /* If IOCTL returns err, user assumes all FDs opened in criu_dump_bos are closed */
1933+ uint32_t i;
1934+ struct kfd_criu_bo_bucket *bo_buckets = (struct kfd_criu_bo_bucket *) args->bos;
1935+
1936+ for (i = 0; i < num_bos; i++) {
1937+ if (bo_buckets[i].alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM)
1938+ close_fd(bo_buckets[i].dmabuf_fd);
1939+ }
1940+ }
1941+
1942+exit_unlock:
1943+ mutex_unlock(&p->mutex);
1944+ if (ret)
1945+ pr_err("Failed to dump CRIU ret:%d\n", ret);
1946+ else
1947+ pr_debug("CRIU dump ret:%d\n", ret);
1948+
1949+ return ret;
1950+}
1951+
1952+static int criu_restore_process(struct kfd_process *p,
1953+ struct kfd_ioctl_criu_args *args,
1954+ uint64_t *priv_offset,
1955+ uint64_t max_priv_data_size)
1956+{
1957+ int ret = 0;
1958+ struct kfd_criu_process_priv_data process_priv;
1959+
1960+ if (*priv_offset + sizeof(process_priv) > max_priv_data_size)
1961+ return -EINVAL;
1962+
1963+ ret = copy_from_user(&process_priv,
1964+ (void __user *)(args->priv_data + *priv_offset),
1965+ sizeof(process_priv));
1966+ if (ret) {
1967+ pr_err("Failed to copy process private information from user\n");
1968+ ret = -EFAULT;
1969+ goto exit;
1970+ }
1971+ *priv_offset += sizeof(process_priv);
1972+
1973+ if (process_priv.version != KFD_CRIU_PRIV_VERSION) {
1974+ pr_err("Invalid CRIU API version (checkpointed:%d current:%d)\n",
1975+ process_priv.version, KFD_CRIU_PRIV_VERSION);
1976+ return -EINVAL;
1977+ }
1978+
1979+ pr_debug("Setting XNACK mode\n");
1980+ if (process_priv.xnack_mode && !kfd_process_xnack_mode(p, true)) {
1981+ pr_err("xnack mode cannot be set\n");
1982+ ret = -EPERM;
1983+ goto exit;
1984+ } else {
1985+ pr_debug("set xnack mode: %d\n", process_priv.xnack_mode);
1986+ p->xnack_enabled = process_priv.xnack_mode;
1987+ }
1988+
1989+exit:
1990+ return ret;
1991+}
1992+
1993+static int criu_restore_devices(struct kfd_process *p,
1994+ struct kfd_ioctl_criu_args *args,
1995+ uint64_t *priv_offset,
1996+ uint64_t max_priv_data_size)
1997+{
1998+ struct kfd_criu_device_bucket *device_buckets;
1999+ struct kfd_criu_device_priv_data *device_privs;
2000+ int ret = 0;
2001+ uint32_t i;
2002+
2003+ if (args->num_devices != p->n_pdds)
2004+ return -EINVAL;
2005+
2006+ if (*priv_offset + (args->num_devices * sizeof(*device_privs)) > max_priv_data_size)
2007+ return -EINVAL;
2008+
2009+ device_buckets = kmalloc_array(args->num_devices, sizeof(*device_buckets), GFP_KERNEL);
2010+ if (!device_buckets)
2011+ return -ENOMEM;
2012+
2013+ ret = copy_from_user(device_buckets, (void __user *)args->devices,
2014+ args->num_devices * sizeof(*device_buckets));
2015+ if (ret) {
2016+ pr_err("Failed to copy devices buckets from user\n");
2017+ ret = -EFAULT;
2018+ goto exit;
2019+ }
2020+
2021+ for (i = 0; i < args->num_devices; i++) {
2022+ struct kfd_dev *dev;
2023+ struct kfd_process_device *pdd;
2024+ struct file *drm_file;
2025+
2026+ /* device private data is not currently used */
2027+
2028+ if (!device_buckets[i].user_gpu_id) {
2029+ pr_err("Invalid user gpu_id\n");
2030+ ret = -EINVAL;
2031+ goto exit;
2032+ }
2033+
2034+ dev = kfd_device_by_id(device_buckets[i].actual_gpu_id);
2035+ if (!dev) {
2036+ pr_err("Failed to find device with gpu_id = %x\n",
2037+ device_buckets[i].actual_gpu_id);
2038+ ret = -EINVAL;
2039+ goto exit;
2040+ }
2041+
2042+ pdd = kfd_get_process_device_data(dev, p);
2043+ if (!pdd) {
2044+ pr_err("Failed to get pdd for gpu_id = %x\n",
2045+ device_buckets[i].actual_gpu_id);
2046+ ret = -EINVAL;
2047+ goto exit;
2048+ }
2049+ pdd->user_gpu_id = device_buckets[i].user_gpu_id;
2050+
2051+ drm_file = fget(device_buckets[i].drm_fd);
2052+ if (!drm_file) {
2053+ pr_err("Invalid render node file descriptor sent from plugin (%d)\n",
2054+ device_buckets[i].drm_fd);
2055+ ret = -EINVAL;
2056+ goto exit;
2057+ }
2058+
2059+ if (pdd->drm_file) {
2060+ ret = -EINVAL;
2061+ goto exit;
2062+ }
2063+
2064+ /* create the vm using render nodes for kfd pdd */
2065+ if (kfd_process_device_init_vm(pdd, drm_file)) {
2066+ pr_err("could not init vm for given pdd\n");
2067+ /* On success, the PDD keeps the drm_file reference */
2068+ fput(drm_file);
2069+ ret = -EINVAL;
2070+ goto exit;
2071+ }
2072+ /*
2073+ * pdd now already has the vm bound to render node so below api won't create a new
2074+ * exclusive kfd mapping but use existing one with renderDXXX but is still needed
2075+ * for iommu v2 binding and runtime pm.
2076+ */
2077+ pdd = kfd_bind_process_to_device(dev, p);
2078+ if (IS_ERR(pdd)) {
2079+ ret = PTR_ERR(pdd);
2080+ goto exit;
2081+ }
2082+ }
2083+
2084+ /*
2085+ * We are not copying device private data from user as we are not using the data for now,
2086+ * but we still adjust for its private data.
2087+ */
2088+ *priv_offset += args->num_devices * sizeof(*device_privs);
2089+
2090+exit:
2091+ kfree(device_buckets);
2092+ return ret;
2093+}
2094+
2095+static int criu_restore_bos(struct kfd_process *p,
2096+ struct kfd_ioctl_criu_args *args,
2097+ uint64_t *priv_offset,
2098+ uint64_t max_priv_data_size)
2099+{
2100+ struct kfd_criu_bo_bucket *bo_buckets;
2101+ struct kfd_criu_bo_priv_data *bo_privs;
2102+ const bool criu_resume = true;
2103+ bool flush_tlbs = false;
2104+ int ret = 0, j = 0;
2105+ uint32_t i = 0;
2106+
2107+ if (*priv_offset + (args->num_bos * sizeof(*bo_privs)) > max_priv_data_size)
2108+ return -EINVAL;
2109+
2110+ /* Prevent MMU notifications until stage-4 IOCTL (CRIU_RESUME) is received */
2111+ amdgpu_amdkfd_block_mmu_notifications(p->kgd_process_info);
2112+
2113+ bo_buckets = kvmalloc_array(args->num_bos, sizeof(*bo_buckets), GFP_KERNEL);
2114+ if (!bo_buckets)
2115+ return -ENOMEM;
2116+
2117+ ret = copy_from_user(bo_buckets, (void __user *)args->bos,
2118+ args->num_bos * sizeof(*bo_buckets));
2119+ if (ret) {
2120+ pr_err("Failed to copy BOs information from user\n");
2121+ ret = -EFAULT;
2122+ goto exit;
2123+ }
2124+
2125+ bo_privs = kvmalloc_array(args->num_bos, sizeof(*bo_privs), GFP_KERNEL);
2126+ if (!bo_privs) {
2127+ ret = -ENOMEM;
2128+ goto exit;
2129+ }
2130+
2131+ ret = copy_from_user(bo_privs, (void __user *)args->priv_data + *priv_offset,
2132+ args->num_bos * sizeof(*bo_privs));
2133+ if (ret) {
2134+ pr_err("Failed to copy BOs information from user\n");
2135+ ret = -EFAULT;
2136+ goto exit;
2137+ }
2138+ *priv_offset += args->num_bos * sizeof(*bo_privs);
2139+
2140+ /* Create and map new BOs */
2141+ for (; i < args->num_bos; i++) {
2142+ struct kfd_criu_bo_bucket *bo_bucket;
2143+ struct kfd_criu_bo_priv_data *bo_priv;
2144+ struct kfd_dev *dev;
2145+ struct kfd_process_device *pdd;
2146+ struct kgd_mem *kgd_mem;
2147+ void *mem;
2148+ u64 offset;
2149+ int idr_handle;
2150+
2151+ bo_bucket = &bo_buckets[i];
2152+ bo_priv = &bo_privs[i];
2153+
2154+ pr_debug("kfd restore ioctl - bo_bucket[%d]:\n", i);
2155+ pr_debug("size = 0x%llx, bo_addr = 0x%llx bo_offset = 0x%llx\n"
2156+ "gpu_id = 0x%x alloc_flags = 0x%x\n"
2157+ "idr_handle = 0x%x\n",
2158+ bo_bucket->size,
2159+ bo_bucket->addr,
2160+ bo_bucket->offset,
2161+ bo_bucket->gpu_id,
2162+ bo_bucket->alloc_flags,
2163+ bo_priv->idr_handle);
2164+
2165+ pdd = kfd_process_device_data_by_id(p, bo_bucket->gpu_id);
2166+ if (!pdd) {
2167+ pr_err("Failed to get pdd\n");
2168+ ret = -ENODEV;
2169+ goto exit;
2170+ }
2171+ dev = pdd->dev;
2172+
2173+ if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) {
2174+ pr_debug("restore ioctl: KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL\n");
2175+ if (bo_bucket->size != kfd_doorbell_process_slice(dev)) {
2176+ ret = -EINVAL;
2177+ goto exit;
2178+ }
2179+ offset = kfd_get_process_doorbells(pdd);
2180+ } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) {
2181+ /* MMIO BOs need remapped bus address */
2182+ pr_debug("restore ioctl :KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP\n");
2183+ if (bo_bucket->size != PAGE_SIZE) {
2184+ pr_err("Invalid page size\n");
2185+ ret = -EINVAL;
2186+ goto exit;
2187+ }
2188+ offset = dev->adev->rmmio_remap.bus_addr;
2189+ if (!offset) {
2190+ pr_err("amdgpu_amdkfd_get_mmio_remap_phys_addr failed\n");
2191+ ret = -ENOMEM;
2192+ goto exit;
2193+ }
2194+ } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
2195+ offset = bo_priv->user_addr;
2196+ }
2197+ /* Create the BO */
2198+ ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(dev->adev,
2199+ bo_bucket->addr,
2200+ bo_bucket->size,
2201+ pdd->drm_priv,
2202+ (struct kgd_mem **) &mem,
2203+ &offset,
2204+ bo_bucket->alloc_flags,
2205+ criu_resume);
2206+ if (ret) {
2207+ pr_err("Could not create the BO\n");
2208+ ret = -ENOMEM;
2209+ goto exit;
2210+ }
2211+ pr_debug("New BO created: size = 0x%llx, bo_addr = 0x%llx bo_offset = 0x%llx\n",
2212+ bo_bucket->size, bo_bucket->addr, offset);
2213+
2214+ /* Restore previuos IDR handle */
2215+ pr_debug("Restoring old IDR handle for the BO");
2216+ idr_handle = idr_alloc(&pdd->alloc_idr, mem,
2217+ bo_priv->idr_handle,
2218+ bo_priv->idr_handle + 1, GFP_KERNEL);
2219+
2220+ if (idr_handle < 0) {
2221+ pr_err("Could not allocate idr\n");
2222+ amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->adev,
2223+ (struct kgd_mem *)mem,
2224+ pdd->drm_priv, NULL);
2225+ ret = -ENOMEM;
2226+ goto exit;
2227+ }
2228+
2229+ if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL)
2230+ bo_bucket->restored_offset = KFD_MMAP_TYPE_DOORBELL |
2231+ KFD_MMAP_GPU_ID(pdd->dev->id);
2232+ if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) {
2233+ bo_bucket->restored_offset = KFD_MMAP_TYPE_MMIO |
2234+ KFD_MMAP_GPU_ID(pdd->dev->id);
2235+ } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
2236+ bo_bucket->restored_offset = offset;
2237+ pr_debug("updating offset for GTT\n");
2238+ } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
2239+ bo_bucket->restored_offset = offset;
2240+ /* Update the VRAM usage count */
2241+ WRITE_ONCE(pdd->vram_usage, pdd->vram_usage + bo_bucket->size);
2242+ pr_debug("updating offset for VRAM\n");
2243+ }
2244+
2245+ /* now map these BOs to GPU/s */
2246+ for (j = 0; j < p->n_pdds; j++) {
2247+ struct kfd_dev *peer;
2248+ struct kfd_process_device *peer_pdd;
2249+ bool table_freed = false;
2250+
2251+ if (!bo_priv->mapped_gpuids[j])
2252+ break;
2253+
2254+ peer_pdd = kfd_process_device_data_by_id(p, bo_priv->mapped_gpuids[j]);
2255+ if (!peer_pdd) {
2256+ ret = -EINVAL;
2257+ goto exit;
2258+ }
2259+ peer = peer_pdd->dev;
2260+
2261+ peer_pdd = kfd_bind_process_to_device(peer, p);
2262+ if (IS_ERR(peer_pdd)) {
2263+ ret = PTR_ERR(peer_pdd);
2264+ goto exit;
2265+ }
2266+ pr_debug("map mem in restore ioctl -> 0x%llx\n",
2267+ ((struct kgd_mem *)mem)->va);
2268+ ret = amdgpu_amdkfd_gpuvm_map_memory_to_gpu(peer->adev,
2269+ (struct kgd_mem *)mem, peer_pdd->drm_priv, &table_freed);
2270+ if (ret) {
2271+ pr_err("Failed to map to gpu %d/%d\n", j, p->n_pdds);
2272+ goto exit;
2273+ }
2274+ if (table_freed)
2275+ flush_tlbs = true;
2276+ }
2277+
2278+ ret = amdgpu_amdkfd_gpuvm_sync_memory(dev->adev,
2279+ (struct kgd_mem *) mem, true);
2280+ if (ret) {
2281+ pr_debug("Sync memory failed, wait interrupted by user signal\n");
2282+ goto exit;
2283+ }
2284+
2285+ pr_debug("map memory was successful for the BO\n");
2286+ /* create the dmabuf object and export the bo */
2287+ kgd_mem = (struct kgd_mem *)mem;
2288+ if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
2289+ ret = criu_get_prime_handle(&kgd_mem->bo->tbo.base,
2290+ DRM_RDWR,
2291+ &bo_bucket->dmabuf_fd);
2292+ if (ret)
2293+ goto exit;
2294+ }
2295+ } /* done */
2296+
2297+ if (flush_tlbs) {
2298+ /* Flush TLBs after waiting for the page table updates to complete */
2299+ for (j = 0; j < p->n_pdds; j++) {
2300+ struct kfd_dev *peer;
2301+ struct kfd_process_device *pdd = p->pdds[j];
2302+ struct kfd_process_device *peer_pdd;
2303+
2304+ peer = kfd_device_by_id(pdd->dev->id);
2305+ if (WARN_ON_ONCE(!peer))
2306+ continue;
2307+ peer_pdd = kfd_get_process_device_data(peer, p);
2308+ if (WARN_ON_ONCE(!peer_pdd))
2309+ continue;
2310+ kfd_flush_tlb(peer_pdd, TLB_FLUSH_LEGACY);
2311+ }
2312+ }
2313+
2314+ /* Copy only the buckets back so user can read bo_buckets[N].restored_offset */
2315+ ret = copy_to_user((void __user *)args->bos,
2316+ bo_buckets,
2317+ (args->num_bos * sizeof(*bo_buckets)));
2318+ if (ret)
2319+ ret = -EFAULT;
2320+
2321+exit:
2322+ while (ret && i--) {
2323+ if (bo_buckets[i].alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM)
2324+ close_fd(bo_buckets[i].dmabuf_fd);
2325+ }
2326+ kvfree(bo_buckets);
2327+ kvfree(bo_privs);
2328+ return ret;
2329+}
2330+
2331+static int criu_restore_objects(struct file *filep,
2332+ struct kfd_process *p,
2333+ struct kfd_ioctl_criu_args *args,
2334+ uint64_t *priv_offset,
2335+ uint64_t max_priv_data_size)
2336+{
2337+ int ret = 0;
2338+ uint32_t i;
2339+
2340+ BUILD_BUG_ON(offsetof(struct kfd_criu_queue_priv_data, object_type));
2341+ BUILD_BUG_ON(offsetof(struct kfd_criu_event_priv_data, object_type));
2342+ BUILD_BUG_ON(offsetof(struct kfd_criu_svm_range_priv_data, object_type));
2343+
2344+ for (i = 0; i < args->num_objects; i++) {
2345+ uint32_t object_type;
2346+
2347+ if (*priv_offset + sizeof(object_type) > max_priv_data_size) {
2348+ pr_err("Invalid private data size\n");
2349+ return -EINVAL;
2350+ }
2351+
2352+ ret = get_user(object_type, (uint32_t __user *)(args->priv_data + *priv_offset));
2353+ if (ret) {
2354+ pr_err("Failed to copy private information from user\n");
2355+ goto exit;
2356+ }
2357+
2358+ switch (object_type) {
2359+ case KFD_CRIU_OBJECT_TYPE_QUEUE:
2360+ ret = kfd_criu_restore_queue(p, (uint8_t __user *)args->priv_data,
2361+ priv_offset, max_priv_data_size);
2362+ if (ret)
2363+ goto exit;
2364+ break;
2365+ case KFD_CRIU_OBJECT_TYPE_EVENT:
2366+ ret = kfd_criu_restore_event(filep, p, (uint8_t __user *)args->priv_data,
2367+ priv_offset, max_priv_data_size);
2368+ if (ret)
2369+ goto exit;
2370+ break;
2371+ case KFD_CRIU_OBJECT_TYPE_SVM_RANGE:
2372+ ret = kfd_criu_restore_svm(p, (uint8_t __user *)args->priv_data,
2373+ priv_offset, max_priv_data_size);
2374+ if (ret)
2375+ goto exit;
2376+ break;
2377+ default:
2378+ pr_err("Invalid object type:%u at index:%d\n", object_type, i);
2379+ ret = -EINVAL;
2380+ goto exit;
2381+ }
2382+ }
2383+exit:
2384+ return ret;
2385+}
2386+
2387+static int criu_restore(struct file *filep,
2388+ struct kfd_process *p,
2389+ struct kfd_ioctl_criu_args *args)
2390+{
2391+ uint64_t priv_offset = 0;
2392+ int ret = 0;
2393+
2394+ pr_debug("CRIU restore (num_devices:%u num_bos:%u num_objects:%u priv_data_size:%llu)\n",
2395+ args->num_devices, args->num_bos, args->num_objects, args->priv_data_size);
2396+
2397+ if (!args->bos || !args->devices || !args->priv_data || !args->priv_data_size ||
2398+ !args->num_devices || !args->num_bos)
2399+ return -EINVAL;
2400+
2401+ mutex_lock(&p->mutex);
2402+
2403+ /*
2404+ * Set the process to evicted state to avoid running any new queues before all the memory
2405+ * mappings are ready.
2406+ */
2407+ ret = kfd_process_evict_queues(p);
2408+ if (ret)
2409+ goto exit_unlock;
2410+
2411+ /* Each function will adjust priv_offset based on how many bytes they consumed */
2412+ ret = criu_restore_process(p, args, &priv_offset, args->priv_data_size);
2413+ if (ret)
2414+ goto exit_unlock;
2415+
2416+ ret = criu_restore_devices(p, args, &priv_offset, args->priv_data_size);
2417+ if (ret)
2418+ goto exit_unlock;
2419+
2420+ ret = criu_restore_bos(p, args, &priv_offset, args->priv_data_size);
2421+ if (ret)
2422+ goto exit_unlock;
2423+
2424+ ret = criu_restore_objects(filep, p, args, &priv_offset, args->priv_data_size);
2425+ if (ret)
2426+ goto exit_unlock;
2427+
2428+ if (priv_offset != args->priv_data_size) {
2429+ pr_err("Invalid private data size\n");
2430+ ret = -EINVAL;
2431+ }
2432+
2433+exit_unlock:
2434+ mutex_unlock(&p->mutex);
2435+ if (ret)
2436+ pr_err("Failed to restore CRIU ret:%d\n", ret);
2437+ else
2438+ pr_debug("CRIU restore successful\n");
2439+
2440+ return ret;
2441+}
2442+
2443+static int criu_unpause(struct file *filep,
2444+ struct kfd_process *p,
2445+ struct kfd_ioctl_criu_args *args)
2446+{
2447+ int ret;
2448+
2449+ mutex_lock(&p->mutex);
2450+
2451+ if (!p->queues_paused) {
2452+ mutex_unlock(&p->mutex);
2453+ return -EINVAL;
2454+ }
2455+
2456+ ret = kfd_process_restore_queues(p);
2457+ if (ret)
2458+ pr_err("Failed to unpause queues ret:%d\n", ret);
2459+ else
2460+ p->queues_paused = false;
2461+
2462+ mutex_unlock(&p->mutex);
2463+
2464+ return ret;
2465+}
2466+
2467+static int criu_resume(struct file *filep,
2468+ struct kfd_process *p,
2469+ struct kfd_ioctl_criu_args *args)
2470+{
2471+ struct kfd_process *target = NULL;
2472+ struct pid *pid = NULL;
2473+ int ret = 0;
2474+
2475+ pr_debug("Inside %s, target pid for criu restore: %d\n", __func__,
2476+ args->pid);
2477+
2478+ pid = find_get_pid(args->pid);
2479+ if (!pid) {
2480+ pr_err("Cannot find pid info for %i\n", args->pid);
2481+ return -ESRCH;
2482+ }
2483+
2484+ pr_debug("calling kfd_lookup_process_by_pid\n");
2485+ target = kfd_lookup_process_by_pid(pid);
2486+
2487+ put_pid(pid);
2488+
2489+ if (!target) {
2490+ pr_debug("Cannot find process info for %i\n", args->pid);
2491+ return -ESRCH;
2492+ }
2493+
2494+ mutex_lock(&target->mutex);
2495+ ret = kfd_criu_resume_svm(target);
2496+ if (ret) {
2497+ pr_err("kfd_criu_resume_svm failed for %i\n", args->pid);
2498+ goto exit;
2499+ }
2500+
2501+ ret = amdgpu_amdkfd_criu_resume(target->kgd_process_info);
2502+ if (ret)
2503+ pr_err("amdgpu_amdkfd_criu_resume failed for %i\n", args->pid);
2504+
2505+exit:
2506+ mutex_unlock(&target->mutex);
2507+
2508+ kfd_unref_process(target);
2509+ return ret;
2510+}
2511+
2512+static int criu_process_info(struct file *filep,
2513+ struct kfd_process *p,
2514+ struct kfd_ioctl_criu_args *args)
2515+{
2516+ int ret = 0;
2517+
2518+ mutex_lock(&p->mutex);
2519+
2520+ if (!p->n_pdds) {
2521+ pr_err("No pdd for given process\n");
2522+ ret = -ENODEV;
2523+ goto err_unlock;
2524+ }
2525+
2526+ ret = kfd_process_evict_queues(p);
2527+ if (ret)
2528+ goto err_unlock;
2529+
2530+ p->queues_paused = true;
2531+
2532+ args->pid = task_pid_nr_ns(p->lead_thread,
2533+ task_active_pid_ns(p->lead_thread));
2534+
2535+ ret = criu_get_process_object_info(p, &args->num_devices, &args->num_bos,
2536+ &args->num_objects, &args->priv_data_size);
2537+ if (ret)
2538+ goto err_unlock;
2539+
2540+ dev_dbg(kfd_device, "Num of devices:%u bos:%u objects:%u priv_data_size:%lld\n",
2541+ args->num_devices, args->num_bos, args->num_objects,
2542+ args->priv_data_size);
2543+
2544+err_unlock:
2545+ if (ret) {
2546+ kfd_process_restore_queues(p);
2547+ p->queues_paused = false;
2548+ }
2549+ mutex_unlock(&p->mutex);
2550+ return ret;
2551+}
2552+
2553+static int kfd_ioctl_criu(struct file *filep, struct kfd_process *p, void *data)
2554+{
2555+ struct kfd_ioctl_criu_args *args = data;
2556+ int ret;
2557+
2558+ dev_dbg(kfd_device, "CRIU operation: %d\n", args->op);
2559+ switch (args->op) {
2560+ case KFD_CRIU_OP_PROCESS_INFO:
2561+ ret = criu_process_info(filep, p, args);
2562+ break;
2563+ case KFD_CRIU_OP_CHECKPOINT:
2564+ ret = criu_checkpoint(filep, p, args);
2565+ break;
2566+ case KFD_CRIU_OP_UNPAUSE:
2567+ ret = criu_unpause(filep, p, args);
2568+ break;
2569+ case KFD_CRIU_OP_RESTORE:
2570+ ret = criu_restore(filep, p, args);
2571+ break;
2572+ case KFD_CRIU_OP_RESUME:
2573+ ret = criu_resume(filep, p, args);
2574+ break;
2575+ default:
2576+ dev_dbg(kfd_device, "Unsupported CRIU operation:%d\n", args->op);
2577+ ret = -EINVAL;
2578+ break;
2579+ }
2580+
2581+ if (ret)
2582+ dev_dbg(kfd_device, "CRIU operation:%d err:%d\n", args->op, ret);
2583+
2584+ return ret;
2585+}
2586+
2587+#define AMDKFD_IOCTL_DEF(ioctl, _func, _flags) \
2588+ [_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, \
2589+ .cmd_drv = 0, .name = #ioctl}
2590+
2591+/** Ioctl table */
2592+static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = {
18652593 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_VERSION,
18662594 kfd_ioctl_get_version, 0),
18672595
@@ -1898,16 +2626,16 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { · 30 unmodified lines
18982626 AMDKFD_IOCTL_DEF(AMDKFD_IOC_WAIT_EVENTS,
18992627 kfd_ioctl_wait_events, 0),
19002628
1901− AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_REGISTER,
2629+ AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_REGISTER_DEPRECATED,
19022630 kfd_ioctl_dbg_register, 0),
19032631
1904− AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_UNREGISTER,
2632+ AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_UNREGISTER_DEPRECATED,
19052633 kfd_ioctl_dbg_unregister, 0),
19062634
1907− AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_ADDRESS_WATCH,
2635+ AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_ADDRESS_WATCH_DEPRECATED,
19082636 kfd_ioctl_dbg_address_watch, 0),
19092637
1910− AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_WAVE_CONTROL,
2638+ AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_WAVE_CONTROL_DEPRECATED,
19112639 kfd_ioctl_dbg_wave_control, 0),
19122640
19132641 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_SCRATCH_BACKING_VA,
@@ -1959,6 +2687,10 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { · 45 unmodified lines
19592687
19602688 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_XNACK_MODE,
19612689 kfd_ioctl_set_xnack_mode, 0),
2690+
2691+ AMDKFD_IOCTL_DEF(AMDKFD_IOC_CRIU_OP,
2692+ kfd_ioctl_criu, KFD_IOC_FLAG_CHECKPOINT_RESTORE),
2693+
19622694 };
19632695
19642696 #define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls)
@@ -1973,6 +2705,7 @@ static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) · 8 unmodified lines
19732705 char *kdata = NULL;
19742706 unsigned int usize, asize;
19752707 int retcode = -EINVAL;
2708+ bool ptrace_attached = false;
19762709
19772710 if (nr >= AMDKFD_CORE_IOCTL_COUNT)
19782711 goto err_i1;
@@ -1998,7 +2731,15 @@ static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) · 19 unmodified lines
19982731 * processes need to create their own KFD device context.
19992732 */
20002733 process = filep->private_data;
2001− if (process->lead_thread != current->group_leader) {
2734+
2735+ rcu_read_lock();
2736+ if ((ioctl->flags & KFD_IOC_FLAG_CHECKPOINT_RESTORE) &&
2737+ ptrace_parent(process->lead_thread) == current)
2738+ ptrace_attached = true;
2739+ rcu_read_unlock();
2740+
2741+ if (process->lead_thread != current->group_leader
2742+ && !ptrace_attached) {
20022743 dev_dbg(kfd_device, "Using KFD FD in wrong process\n");
20032744 retcode = -EBADF;
20042745 goto err_i1;
@@ -2013,6 +2754,19 @@ static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) · 8 unmodified lines
20132754 goto err_i1;
20142755 }
20152756
2757+ /*
2758+ * Versions of docker shipped in Ubuntu 18.xx and 20.xx do not support
2759+ * CAP_CHECKPOINT_RESTORE, so we also allow access if CAP_SYS_ADMIN as CAP_SYS_ADMIN is a
2760+ * more priviledged access.
2761+ */
2762+ if (unlikely(ioctl->flags & KFD_IOC_FLAG_CHECKPOINT_RESTORE)) {
2763+ if (!capable(CAP_CHECKPOINT_RESTORE) &&
2764+ !capable(CAP_SYS_ADMIN)) {
2765+ retcode = -EACCES;
2766+ goto err_i1;
2767+ }
2768+ }
2769+
20162770 if (cmd & (IOC_IN | IOC_OUT)) {
20172771 if (asize <= sizeof(stack_kdata)) {
20182772 kdata = stack_kdata;
drivers/gpu/drm/amd/amdkfd/kfd_crat.c+4−2
@@ -1,5 +1,6 @@
1+// SPDX-License-Identifier: GPL-2.0 OR MIT
12 /*
2− * Copyright 2015-2017 Advanced Micro Devices, Inc.
3+ * Copyright 2015-2022 Advanced Micro Devices, Inc.
34 *
45 * Permission is hereby granted, free of charge, to any person obtaining a
56 * copy of this software and associated documentation files (the "Software"),
@@ -1381,7 +1382,7 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev, · 1375 unmodified lines
13811382 num_of_cache_types = ARRAY_SIZE(vegam_cache_info);
13821383 break;
13831384 default:
1384− switch(KFD_GC_VERSION(kdev)) {
1385+ switch (KFD_GC_VERSION(kdev)) {
13851386 case IP_VERSION(9, 0, 1):
13861387 pcache_info = vega10_cache_info;
13871388 num_of_cache_types = ARRAY_SIZE(vega10_cache_info);
@@ -1411,6 +1412,7 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev, · 23 unmodified lines
14111412 case IP_VERSION(10, 1, 10):
14121413 case IP_VERSION(10, 1, 2):
14131414 case IP_VERSION(10, 1, 3):
1415+ case IP_VERSION(10, 1, 4):
14141416 pcache_info = navi10_cache_info;
14151417 num_of_cache_types = ARRAY_SIZE(navi10_cache_info);
14161418 break;
drivers/gpu/drm/amd/amdkfd/kfd_crat.h+3−2
@@ -1,5 +1,6 @@
1+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
12 /*
2− * Copyright 2014 Advanced Micro Devices, Inc.
3+ * Copyright 2014-2022 Advanced Micro Devices, Inc.
34 *
45 * Permission is hereby granted, free of charge, to any person obtaining a
56 * copy of this software and associated documentation files (the "Software"),
@@ -232,7 +233,7 @@ struct crat_subtype_ccompute { · 226 unmodified lines
232233 #define CRAT_IOLINK_FLAGS_NO_ATOMICS_32_BIT (1 << 2)
233234 #define CRAT_IOLINK_FLAGS_NO_ATOMICS_64_BIT (1 << 3)
234235 #define CRAT_IOLINK_FLAGS_NO_PEER_TO_PEER_DMA (1 << 4)
235−#define CRAT_IOLINK_FLAGS_BI_DIRECTIONAL (1 << 31)
236+#define CRAT_IOLINK_FLAGS_BI_DIRECTIONAL (1 << 31)
236237 #define CRAT_IOLINK_FLAGS_RESERVED_MASK 0x7fffffe0
237238
238239 /*
drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c+0−845
@@ -1,845 +0,0 @@
1−/*
2− * Copyright 2014 Advanced Micro Devices, Inc.
3− *
4− * Permission is hereby granted, free of charge, to any person obtaining a
5− * copy of this software and associated documentation files (the "Software"),
6− * to deal in the Software without restriction, including without limitation
7− * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8− * and/or sell copies of the Software, and to permit persons to whom the
9− * Software is furnished to do so, subject to the following conditions:
10− *
11− * The above copyright notice and this permission notice shall be included in
12− * all copies or substantial portions of the Software.
13− *
14− * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15− * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16− * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17− * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18− * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19− * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20− * OTHER DEALINGS IN THE SOFTWARE.
21− *
22− */
23−
24−#include <linux/types.h>
25−#include <linux/kernel.h>
26−#include <linux/log2.h>
27−#include <linux/sched.h>
28−#include <linux/slab.h>
29−#include <linux/mutex.h>
30−#include <linux/device.h>
31−
32−#include "kfd_pm4_headers.h"
33−#include "kfd_pm4_headers_diq.h"
34−#include "kfd_kernel_queue.h"
35−#include "kfd_priv.h"
36−#include "kfd_pm4_opcodes.h"
37−#include "cik_regs.h"
38−#include "kfd_dbgmgr.h"
39−#include "kfd_dbgdev.h"
40−#include "kfd_device_queue_manager.h"
41−
42−static void dbgdev_address_watch_disable_nodiq(struct kfd_dev *dev)
43−{
44− dev->kfd2kgd->address_watch_disable(dev->adev);
45−}
46−
47−static int dbgdev_diq_submit_ib(struct kfd_dbgdev *dbgdev,
48− u32 pasid, uint64_t vmid0_address,
49− uint32_t *packet_buff, size_t size_in_bytes)
50−{
51− struct pm4__release_mem *rm_packet;
52− struct pm4__indirect_buffer_pasid *ib_packet;
53− struct kfd_mem_obj *mem_obj;
54− size_t pq_packets_size_in_bytes;
55− union ULARGE_INTEGER *largep;
56− union ULARGE_INTEGER addr;
57− struct kernel_queue *kq;
58− uint64_t *rm_state;
59− unsigned int *ib_packet_buff;
60− int status;
61−
62− if (WARN_ON(!size_in_bytes))
63− return -EINVAL;
64−
65− kq = dbgdev->kq;
66−
67− pq_packets_size_in_bytes = sizeof(struct pm4__release_mem) +
68− sizeof(struct pm4__indirect_buffer_pasid);
69−
70− /*
71− * We acquire a buffer from DIQ
72− * The receive packet buff will be sitting on the Indirect Buffer
73− * and in the PQ we put the IB packet + sync packet(s).
74− */
75− status = kq_acquire_packet_buffer(kq,
76− pq_packets_size_in_bytes / sizeof(uint32_t),
77− &ib_packet_buff);
78− if (status) {
79− pr_err("kq_acquire_packet_buffer failed\n");
80− return status;
81− }
82−
83− memset(ib_packet_buff, 0, pq_packets_size_in_bytes);
84−
85− ib_packet = (struct pm4__indirect_buffer_pasid *) (ib_packet_buff);
86−
87− ib_packet->header.count = 3;
88− ib_packet->header.opcode = IT_INDIRECT_BUFFER_PASID;
89− ib_packet->header.type = PM4_TYPE_3;
90−
91− largep = (union ULARGE_INTEGER *) &vmid0_address;
92−
93− ib_packet->bitfields2.ib_base_lo = largep->u.low_part >> 2;
94− ib_packet->bitfields3.ib_base_hi = largep->u.high_part;
95−
96− ib_packet->control = (1 << 23) | (1 << 31) |
97− ((size_in_bytes / 4) & 0xfffff);
98−
99− ib_packet->bitfields5.pasid = pasid;
100−
101− /*
102− * for now we use release mem for GPU-CPU synchronization
103− * Consider WaitRegMem + WriteData as a better alternative
104− * we get a GART allocations ( gpu/cpu mapping),
105− * for the sync variable, and wait until:
106− * (a) Sync with HW
107− * (b) Sync var is written by CP to mem.
108− */
109− rm_packet = (struct pm4__release_mem *) (ib_packet_buff +
110− (sizeof(struct pm4__indirect_buffer_pasid) /
111− sizeof(unsigned int)));
112−
113− status = kfd_gtt_sa_allocate(dbgdev->dev, sizeof(uint64_t),
114− &mem_obj);
115−
116− if (status) {
117− pr_err("Failed to allocate GART memory\n");
118− kq_rollback_packet(kq);
119− return status;
120− }
121−
122− rm_state = (uint64_t *) mem_obj->cpu_ptr;
123−
124− *rm_state = QUEUESTATE__ACTIVE_COMPLETION_PENDING;
125−
126− rm_packet->header.opcode = IT_RELEASE_MEM;
127− rm_packet->header.type = PM4_TYPE_3;
128− rm_packet->header.count = sizeof(struct pm4__release_mem) / 4 - 2;
129−
130− rm_packet->bitfields2.event_type = CACHE_FLUSH_AND_INV_TS_EVENT;
131− rm_packet->bitfields2.event_index =
132− event_index___release_mem__end_of_pipe;
133−
134− rm_packet->bitfields2.cache_policy = cache_policy___release_mem__lru;
135− rm_packet->bitfields2.atc = 0;
136− rm_packet->bitfields2.tc_wb_action_ena = 1;
137−
138− addr.quad_part = mem_obj->gpu_addr;
139−
140− rm_packet->bitfields4.address_lo_32b = addr.u.low_part >> 2;
141− rm_packet->address_hi = addr.u.high_part;
142−
143− rm_packet->bitfields3.data_sel =
144− data_sel___release_mem__send_64_bit_data;
145−
146− rm_packet->bitfields3.int_sel =
147− int_sel___release_mem__send_data_after_write_confirm;
148−
149− rm_packet->bitfields3.dst_sel =
150− dst_sel___release_mem__memory_controller;
151−
152− rm_packet->data_lo = QUEUESTATE__ACTIVE;
153−
154− kq_submit_packet(kq);
155−
156− /* Wait till CP writes sync code: */
157− status = amdkfd_fence_wait_timeout(
158− rm_state,
159− QUEUESTATE__ACTIVE, 1500);
160−
161− kfd_gtt_sa_free(dbgdev->dev, mem_obj);
162−
163− return status;
164−}
165−
166−static int dbgdev_register_nodiq(struct kfd_dbgdev *dbgdev)
167−{
168− /*
169− * no action is needed in this case,
170− * just make sure diq will not be used
171− */
172−
173− dbgdev->kq = NULL;
174−
175− return 0;
176−}
177−
178−static int dbgdev_register_diq(struct kfd_dbgdev *dbgdev)
179−{
180− struct queue_properties properties;
181− unsigned int qid;
182− struct kernel_queue *kq = NULL;
183− int status;
184−
185− properties.type = KFD_QUEUE_TYPE_DIQ;
186−
187− status = pqm_create_queue(dbgdev->pqm, dbgdev->dev, NULL,
188− &properties, &qid, NULL);
189−
190− if (status) {
191− pr_err("Failed to create DIQ\n");
192− return status;
193− }
194−
195− pr_debug("DIQ Created with queue id: %d\n", qid);
196−
197− kq = pqm_get_kernel_queue(dbgdev->pqm, qid);
198−
199− if (!kq) {
200− pr_err("Error getting DIQ\n");
201− pqm_destroy_queue(dbgdev->pqm, qid);
202− return -EFAULT;
203− }
204−
205− dbgdev->kq = kq;
206−
207− return status;
208−}
209−
210−static int dbgdev_unregister_nodiq(struct kfd_dbgdev *dbgdev)
211−{
212− /* disable watch address */
213− dbgdev_address_watch_disable_nodiq(dbgdev->dev);
214− return 0;
215−}
216−
217−static int dbgdev_unregister_diq(struct kfd_dbgdev *dbgdev)
218−{
219− /* todo - disable address watch */
220− int status;
221−
222− status = pqm_destroy_queue(dbgdev->pqm,
223− dbgdev->kq->queue->properties.queue_id);
224− dbgdev->kq = NULL;
225−
226− return status;
227−}
228−
229−static void dbgdev_address_watch_set_registers(
230− const struct dbg_address_watch_info *adw_info,
231− union TCP_WATCH_ADDR_H_BITS *addrHi,
232− union TCP_WATCH_ADDR_L_BITS *addrLo,
233− union TCP_WATCH_CNTL_BITS *cntl,
234− unsigned int index, unsigned int vmid)
235−{
236− union ULARGE_INTEGER addr;
237−
238− addr.quad_part = 0;
239− addrHi->u32All = 0;
240− addrLo->u32All = 0;
241− cntl->u32All = 0;
242−
243− if (adw_info->watch_mask)
244− cntl->bitfields.mask =
245− (uint32_t) (adw_info->watch_mask[index] &
246− ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK);
247− else
248− cntl->bitfields.mask = ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK;
249−
250− addr.quad_part = (unsigned long long) adw_info->watch_address[index];
251−
252− addrHi->bitfields.addr = addr.u.high_part &
253− ADDRESS_WATCH_REG_ADDHIGH_MASK;
254− addrLo->bitfields.addr =
255− (addr.u.low_part >> ADDRESS_WATCH_REG_ADDLOW_SHIFT);
256−
257− cntl->bitfields.mode = adw_info->watch_mode[index];
258− cntl->bitfields.vmid = (uint32_t) vmid;
259− /* for now assume it is an ATC address */
260− cntl->u32All |= ADDRESS_WATCH_REG_CNTL_ATC_BIT;
261−
262− pr_debug("\t\t%20s %08x\n", "set reg mask :", cntl->bitfields.mask);
263− pr_debug("\t\t%20s %08x\n", "set reg add high :",
264− addrHi->bitfields.addr);
265− pr_debug("\t\t%20s %08x\n", "set reg add low :",
266− addrLo->bitfields.addr);
267−}
268−
269−static int dbgdev_address_watch_nodiq(struct kfd_dbgdev *dbgdev,
270− struct dbg_address_watch_info *adw_info)
271−{
272− union TCP_WATCH_ADDR_H_BITS addrHi;
273− union TCP_WATCH_ADDR_L_BITS addrLo;
274− union TCP_WATCH_CNTL_BITS cntl;
275− struct kfd_process_device *pdd;
276− unsigned int i;
277−
278− /* taking the vmid for that process on the safe way using pdd */
279− pdd = kfd_get_process_device_data(dbgdev->dev,
280− adw_info->process);
281− if (!pdd) {
282− pr_err("Failed to get pdd for wave control no DIQ\n");
283− return -EFAULT;
284− }
285−
286− addrHi.u32All = 0;
287− addrLo.u32All = 0;
288− cntl.u32All = 0;
289−
290− if ((adw_info->num_watch_points > MAX_WATCH_ADDRESSES) ||
291− (adw_info->num_watch_points == 0)) {
292− pr_err("num_watch_points is invalid\n");
293− return -EINVAL;
294− }
295−
296− if (!adw_info->watch_mode || !adw_info->watch_address) {
297− pr_err("adw_info fields are not valid\n");
298− return -EINVAL;
299− }
300−
301− for (i = 0; i < adw_info->num_watch_points; i++) {
302− dbgdev_address_watch_set_registers(adw_info, &addrHi, &addrLo,
303− &cntl, i, pdd->qpd.vmid);
304−
305− pr_debug("\t\t%30s\n", "* * * * * * * * * * * * * * * * * *");
306− pr_debug("\t\t%20s %08x\n", "register index :", i);
307− pr_debug("\t\t%20s %08x\n", "vmid is :", pdd->qpd.vmid);
308− pr_debug("\t\t%20s %08x\n", "Address Low is :",
309− addrLo.bitfields.addr);
310− pr_debug("\t\t%20s %08x\n", "Address high is :",
311− addrHi.bitfields.addr);
312− pr_debug("\t\t%20s %08x\n", "Address high is :",
313− addrHi.bitfields.addr);
314− pr_debug("\t\t%20s %08x\n", "Control Mask is :",
315− cntl.bitfields.mask);
316− pr_debug("\t\t%20s %08x\n", "Control Mode is :",
317− cntl.bitfields.mode);
318− pr_debug("\t\t%20s %08x\n", "Control Vmid is :",
319− cntl.bitfields.vmid);
320− pr_debug("\t\t%20s %08x\n", "Control atc is :",
321− cntl.bitfields.atc);
322− pr_debug("\t\t%30s\n", "* * * * * * * * * * * * * * * * * *");
323−
324− pdd->dev->kfd2kgd->address_watch_execute(
325− dbgdev->dev->adev,
326− i,
327− cntl.u32All,
328− addrHi.u32All,
329− addrLo.u32All);
330− }
331−
332− return 0;
333−}
334−
335−static int dbgdev_address_watch_diq(struct kfd_dbgdev *dbgdev,
336− struct dbg_address_watch_info *adw_info)
337−{
338− struct pm4__set_config_reg *packets_vec;
339− union TCP_WATCH_ADDR_H_BITS addrHi;
340− union TCP_WATCH_ADDR_L_BITS addrLo;
341− union TCP_WATCH_CNTL_BITS cntl;
342− struct kfd_mem_obj *mem_obj;
343− unsigned int aw_reg_add_dword;
344− uint32_t *packet_buff_uint;
345− unsigned int i;
346− int status;
347− size_t ib_size = sizeof(struct pm4__set_config_reg) * 4;
348− /* we do not control the vmid in DIQ mode, just a place holder */
349− unsigned int vmid = 0;
350−
351− addrHi.u32All = 0;
352− addrLo.u32All = 0;
353− cntl.u32All = 0;
354−
355− if ((adw_info->num_watch_points > MAX_WATCH_ADDRESSES) ||
356− (adw_info->num_watch_points == 0)) {
357− pr_err("num_watch_points is invalid\n");
358− return -EINVAL;
359− }
360−
361− if (!adw_info->watch_mode || !adw_info->watch_address) {
362− pr_err("adw_info fields are not valid\n");
363− return -EINVAL;
364− }
365−
366− status = kfd_gtt_sa_allocate(dbgdev->dev, ib_size, &mem_obj);
367−
368− if (status) {
369− pr_err("Failed to allocate GART memory\n");
370− return status;
371− }
372−
373− packet_buff_uint = mem_obj->cpu_ptr;
374−
375− memset(packet_buff_uint, 0, ib_size);
376−
377− packets_vec = (struct pm4__set_config_reg *) (packet_buff_uint);
378−
379− packets_vec[0].header.count = 1;
380− packets_vec[0].header.opcode = IT_SET_CONFIG_REG;
381− packets_vec[0].header.type = PM4_TYPE_3;
382− packets_vec[0].bitfields2.vmid_shift = ADDRESS_WATCH_CNTL_OFFSET;
383− packets_vec[0].bitfields2.insert_vmid = 1;
384− packets_vec[1].ordinal1 = packets_vec[0].ordinal1;
385− packets_vec[1].bitfields2.insert_vmid = 0;
386− packets_vec[2].ordinal1 = packets_vec[0].ordinal1;
387− packets_vec[2].bitfields2.insert_vmid = 0;
388− packets_vec[3].ordinal1 = packets_vec[0].ordinal1;
389− packets_vec[3].bitfields2.vmid_shift = ADDRESS_WATCH_CNTL_OFFSET;
390− packets_vec[3].bitfields2.insert_vmid = 1;
391−
392− for (i = 0; i < adw_info->num_watch_points; i++) {
393− dbgdev_address_watch_set_registers(adw_info,
394− &addrHi,
395− &addrLo,
396− &cntl,
397− i,
398− vmid);
399−
400− pr_debug("\t\t%30s\n", "* * * * * * * * * * * * * * * * * *");
401− pr_debug("\t\t%20s %08x\n", "register index :", i);
402− pr_debug("\t\t%20s %08x\n", "vmid is :", vmid);
403− pr_debug("\t\t%20s %p\n", "Add ptr is :",
404− adw_info->watch_address);
405− pr_debug("\t\t%20s %08llx\n", "Add is :",
406− adw_info->watch_address[i]);
407− pr_debug("\t\t%20s %08x\n", "Address Low is :",
408− addrLo.bitfields.addr);
409− pr_debug("\t\t%20s %08x\n", "Address high is :",
410− addrHi.bitfields.addr);
411− pr_debug("\t\t%20s %08x\n", "Control Mask is :",
412− cntl.bitfields.mask);
413− pr_debug("\t\t%20s %08x\n", "Control Mode is :",
414− cntl.bitfields.mode);
415− pr_debug("\t\t%20s %08x\n", "Control Vmid is :",
416− cntl.bitfields.vmid);
417− pr_debug("\t\t%20s %08x\n", "Control atc is :",
418− cntl.bitfields.atc);
419− pr_debug("\t\t%30s\n", "* * * * * * * * * * * * * * * * * *");
420−
421− aw_reg_add_dword =
422− dbgdev->dev->kfd2kgd->address_watch_get_offset(
423− dbgdev->dev->adev,
424− i,
425− ADDRESS_WATCH_REG_CNTL);
426−
427− packets_vec[0].bitfields2.reg_offset =
428− aw_reg_add_dword - AMD_CONFIG_REG_BASE;
429−
430− packets_vec[0].reg_data[0] = cntl.u32All;
431−
432− aw_reg_add_dword =
433− dbgdev->dev->kfd2kgd->address_watch_get_offset(
434− dbgdev->dev->adev,
435− i,
436− ADDRESS_WATCH_REG_ADDR_HI);
437−
438− packets_vec[1].bitfields2.reg_offset =
439− aw_reg_add_dword - AMD_CONFIG_REG_BASE;
440− packets_vec[1].reg_data[0] = addrHi.u32All;
441−
442− aw_reg_add_dword =
443− dbgdev->dev->kfd2kgd->address_watch_get_offset(
444− dbgdev->dev->adev,
445− i,
446− ADDRESS_WATCH_REG_ADDR_LO);
447−
448− packets_vec[2].bitfields2.reg_offset =
449− aw_reg_add_dword - AMD_CONFIG_REG_BASE;
450− packets_vec[2].reg_data[0] = addrLo.u32All;
451−
452− /* enable watch flag if address is not zero*/
453− if (adw_info->watch_address[i] > 0)
454− cntl.bitfields.valid = 1;
455− else
456− cntl.bitfields.valid = 0;
457−
458− aw_reg_add_dword =
459− dbgdev->dev->kfd2kgd->address_watch_get_offset(
460− dbgdev->dev->adev,
461− i,
462− ADDRESS_WATCH_REG_CNTL);
463−
464− packets_vec[3].bitfields2.reg_offset =
465− aw_reg_add_dword - AMD_CONFIG_REG_BASE;
466− packets_vec[3].reg_data[0] = cntl.u32All;
467−
468− status = dbgdev_diq_submit_ib(
469− dbgdev,
470− adw_info->process->pasid,
471− mem_obj->gpu_addr,
472− packet_buff_uint,
473− ib_size);
474−
475− if (status) {
476− pr_err("Failed to submit IB to DIQ\n");
477− break;
478− }
479− }
480−
481− kfd_gtt_sa_free(dbgdev->dev, mem_obj);
482− return status;
483−}
484−
485−static int dbgdev_wave_control_set_registers(
486− struct dbg_wave_control_info *wac_info,
487− union SQ_CMD_BITS *in_reg_sq_cmd,
488− union GRBM_GFX_INDEX_BITS *in_reg_gfx_index)
489−{
490− int status = 0;
491− union SQ_CMD_BITS reg_sq_cmd;
492− union GRBM_GFX_INDEX_BITS reg_gfx_index;
493− struct HsaDbgWaveMsgAMDGen2 *pMsg;
494−
495− reg_sq_cmd.u32All = 0;
496− reg_gfx_index.u32All = 0;
497− pMsg = &wac_info->dbgWave_msg.DbgWaveMsg.WaveMsgInfoGen2;
498−
499− switch (wac_info->mode) {
500− /* Send command to single wave */
501− case HSA_DBG_WAVEMODE_SINGLE:
502− /*
503− * Limit access to the process waves only,
504− * by setting vmid check
505− */
506− reg_sq_cmd.bits.check_vmid = 1;
507− reg_sq_cmd.bits.simd_id = pMsg->ui32.SIMD;
508− reg_sq_cmd.bits.wave_id = pMsg->ui32.WaveId;
509− reg_sq_cmd.bits.mode = SQ_IND_CMD_MODE_SINGLE;
510−
511− reg_gfx_index.bits.sh_index = pMsg->ui32.ShaderArray;
512− reg_gfx_index.bits.se_index = pMsg->ui32.ShaderEngine;
513− reg_gfx_index.bits.instance_index = pMsg->ui32.HSACU;
514−
515− break;
516−
517− /* Send command to all waves with matching VMID */
518− case HSA_DBG_WAVEMODE_BROADCAST_PROCESS:
519−
520− reg_gfx_index.bits.sh_broadcast_writes = 1;
521− reg_gfx_index.bits.se_broadcast_writes = 1;
522− reg_gfx_index.bits.instance_broadcast_writes = 1;
523−
524− reg_sq_cmd.bits.mode = SQ_IND_CMD_MODE_BROADCAST;
525−
526− break;
527−
528− /* Send command to all CU waves with matching VMID */
529− case HSA_DBG_WAVEMODE_BROADCAST_PROCESS_CU:
530−
531− reg_sq_cmd.bits.check_vmid = 1;
532− reg_sq_cmd.bits.mode = SQ_IND_CMD_MODE_BROADCAST;
533−
534− reg_gfx_index.bits.sh_index = pMsg->ui32.ShaderArray;
535− reg_gfx_index.bits.se_index = pMsg->ui32.ShaderEngine;
536− reg_gfx_index.bits.instance_index = pMsg->ui32.HSACU;
537−
538− break;
539−
540− default:
541− return -EINVAL;
542− }
543−
544− switch (wac_info->operand) {
545− case HSA_DBG_WAVEOP_HALT:
546− reg_sq_cmd.bits.cmd = SQ_IND_CMD_CMD_HALT;
547− break;
548−
549− case HSA_DBG_WAVEOP_RESUME:
550− reg_sq_cmd.bits.cmd = SQ_IND_CMD_CMD_RESUME;
551− break;
552−
553− case HSA_DBG_WAVEOP_KILL:
554− reg_sq_cmd.bits.cmd = SQ_IND_CMD_CMD_KILL;
555− break;
556−
557− case HSA_DBG_WAVEOP_DEBUG:
558− reg_sq_cmd.bits.cmd = SQ_IND_CMD_CMD_DEBUG;
559− break;
560−
561− case HSA_DBG_WAVEOP_TRAP:
562− if (wac_info->trapId < MAX_TRAPID) {
563− reg_sq_cmd.bits.cmd = SQ_IND_CMD_CMD_TRAP;
564− reg_sq_cmd.bits.trap_id = wac_info->trapId;
565− } else {
566− status = -EINVAL;
567− }
568− break;
569−
570− default:
571− status = -EINVAL;
572− break;
573− }
574−
575− if (status == 0) {
576− *in_reg_sq_cmd = reg_sq_cmd;
577− *in_reg_gfx_index = reg_gfx_index;
578− }
579−
580− return status;
581−}
582−
583−static int dbgdev_wave_control_diq(struct kfd_dbgdev *dbgdev,
584− struct dbg_wave_control_info *wac_info)
585−{
586−
587− int status;
588− union SQ_CMD_BITS reg_sq_cmd;
589− union GRBM_GFX_INDEX_BITS reg_gfx_index;
590− struct kfd_mem_obj *mem_obj;
591− uint32_t *packet_buff_uint;
592− struct pm4__set_config_reg *packets_vec;
593− size_t ib_size = sizeof(struct pm4__set_config_reg) * 3;
594−
595− reg_sq_cmd.u32All = 0;
596−
597− status = dbgdev_wave_control_set_registers(wac_info, &reg_sq_cmd,
598− &reg_gfx_index);
599− if (status) {
600− pr_err("Failed to set wave control registers\n");
601− return status;
602− }
603−
604− /* we do not control the VMID in DIQ, so reset it to a known value */
605− reg_sq_cmd.bits.vm_id = 0;
606−
607− pr_debug("\t\t %30s\n", "* * * * * * * * * * * * * * * * * *");
608−
609− pr_debug("\t\t mode is: %u\n", wac_info->mode);
610− pr_debug("\t\t operand is: %u\n", wac_info->operand);
611− pr_debug("\t\t trap id is: %u\n", wac_info->trapId);
612− pr_debug("\t\t msg value is: %u\n",
613− wac_info->dbgWave_msg.DbgWaveMsg.WaveMsgInfoGen2.Value);
614− pr_debug("\t\t vmid is: N/A\n");
615−
616− pr_debug("\t\t chk_vmid is : %u\n", reg_sq_cmd.bitfields.check_vmid);
617− pr_debug("\t\t command is : %u\n", reg_sq_cmd.bitfields.cmd);
618− pr_debug("\t\t queue id is : %u\n", reg_sq_cmd.bitfields.queue_id);
619− pr_debug("\t\t simd id is : %u\n", reg_sq_cmd.bitfields.simd_id);
620− pr_debug("\t\t mode is : %u\n", reg_sq_cmd.bitfields.mode);
621− pr_debug("\t\t vm_id is : %u\n", reg_sq_cmd.bitfields.vm_id);
622− pr_debug("\t\t wave_id is : %u\n", reg_sq_cmd.bitfields.wave_id);
623−
624− pr_debug("\t\t ibw is : %u\n",
625− reg_gfx_index.bitfields.instance_broadcast_writes);
626− pr_debug("\t\t ii is : %u\n",
627− reg_gfx_index.bitfields.instance_index);
628− pr_debug("\t\t sebw is : %u\n",
629− reg_gfx_index.bitfields.se_broadcast_writes);
630− pr_debug("\t\t se_ind is : %u\n", reg_gfx_index.bitfields.se_index);
631− pr_debug("\t\t sh_ind is : %u\n", reg_gfx_index.bitfields.sh_index);
632− pr_debug("\t\t sbw is : %u\n",
633− reg_gfx_index.bitfields.sh_broadcast_writes);
634−
635− pr_debug("\t\t %30s\n", "* * * * * * * * * * * * * * * * * *");
636−
637− status = kfd_gtt_sa_allocate(dbgdev->dev, ib_size, &mem_obj);
638−
639− if (status != 0) {
640− pr_err("Failed to allocate GART memory\n");
641− return status;
642− }
643−
644− packet_buff_uint = mem_obj->cpu_ptr;
645−
646− memset(packet_buff_uint, 0, ib_size);
647−
648− packets_vec = (struct pm4__set_config_reg *) packet_buff_uint;
649− packets_vec[0].header.count = 1;
650− packets_vec[0].header.opcode = IT_SET_UCONFIG_REG;
651− packets_vec[0].header.type = PM4_TYPE_3;
652− packets_vec[0].bitfields2.reg_offset =
653− GRBM_GFX_INDEX / 4 - USERCONFIG_REG_BASE;
654−
655− packets_vec[0].bitfields2.insert_vmid = 0;
656− packets_vec[0].reg_data[0] = reg_gfx_index.u32All;
657−
658− packets_vec[1].header.count = 1;
659− packets_vec[1].header.opcode = IT_SET_CONFIG_REG;
660− packets_vec[1].header.type = PM4_TYPE_3;
661− packets_vec[1].bitfields2.reg_offset = SQ_CMD / 4 - AMD_CONFIG_REG_BASE;
662−
663− packets_vec[1].bitfields2.vmid_shift = SQ_CMD_VMID_OFFSET;
664− packets_vec[1].bitfields2.insert_vmid = 1;
665− packets_vec[1].reg_data[0] = reg_sq_cmd.u32All;
666−
667− /* Restore the GRBM_GFX_INDEX register */
668−
669− reg_gfx_index.u32All = 0;
670− reg_gfx_index.bits.sh_broadcast_writes = 1;
671− reg_gfx_index.bits.instance_broadcast_writes = 1;
672− reg_gfx_index.bits.se_broadcast_writes = 1;
673−
674−
675− packets_vec[2].ordinal1 = packets_vec[0].ordinal1;
676− packets_vec[2].bitfields2.reg_offset =
677− GRBM_GFX_INDEX / 4 - USERCONFIG_REG_BASE;
678−
679− packets_vec[2].bitfields2.insert_vmid = 0;
680− packets_vec[2].reg_data[0] = reg_gfx_index.u32All;
681−
682− status = dbgdev_diq_submit_ib(
683− dbgdev,
684− wac_info->process->pasid,
685− mem_obj->gpu_addr,
686− packet_buff_uint,
687− ib_size);
688−
689− if (status)
690− pr_err("Failed to submit IB to DIQ\n");
691−
692− kfd_gtt_sa_free(dbgdev->dev, mem_obj);
693−
694− return status;
695−}
696−
697−static int dbgdev_wave_control_nodiq(struct kfd_dbgdev *dbgdev,
698− struct dbg_wave_control_info *wac_info)
699−{
700− int status;
701− union SQ_CMD_BITS reg_sq_cmd;
702− union GRBM_GFX_INDEX_BITS reg_gfx_index;
703− struct kfd_process_device *pdd;
704−
705− reg_sq_cmd.u32All = 0;
706−
707− /* taking the VMID for that process on the safe way using PDD */
708− pdd = kfd_get_process_device_data(dbgdev->dev, wac_info->process);
709−
710− if (!pdd) {
711− pr_err("Failed to get pdd for wave control no DIQ\n");
712− return -EFAULT;
713− }
714− status = dbgdev_wave_control_set_registers(wac_info, &reg_sq_cmd,
715− &reg_gfx_index);
716− if (status) {
717− pr_err("Failed to set wave control registers\n");
718− return status;
719− }
720−
721− /* for non DIQ we need to patch the VMID: */
722−
723− reg_sq_cmd.bits.vm_id = pdd->qpd.vmid;
724−
725− pr_debug("\t\t %30s\n", "* * * * * * * * * * * * * * * * * *");
726−
727− pr_debug("\t\t mode is: %u\n", wac_info->mode);
728− pr_debug("\t\t operand is: %u\n", wac_info->operand);
729− pr_debug("\t\t trap id is: %u\n", wac_info->trapId);
730− pr_debug("\t\t msg value is: %u\n",
731− wac_info->dbgWave_msg.DbgWaveMsg.WaveMsgInfoGen2.Value);
732− pr_debug("\t\t vmid is: %u\n", pdd->qpd.vmid);
733−
734− pr_debug("\t\t chk_vmid is : %u\n", reg_sq_cmd.bitfields.check_vmid);
735− pr_debug("\t\t command is : %u\n", reg_sq_cmd.bitfields.cmd);
736− pr_debug("\t\t queue id is : %u\n", reg_sq_cmd.bitfields.queue_id);
737− pr_debug("\t\t simd id is : %u\n", reg_sq_cmd.bitfields.simd_id);
738− pr_debug("\t\t mode is : %u\n", reg_sq_cmd.bitfields.mode);
739− pr_debug("\t\t vm_id is : %u\n", reg_sq_cmd.bitfields.vm_id);
740− pr_debug("\t\t wave_id is : %u\n", reg_sq_cmd.bitfields.wave_id);
741−
742− pr_debug("\t\t ibw is : %u\n",
743− reg_gfx_index.bitfields.instance_broadcast_writes);
744− pr_debug("\t\t ii is : %u\n",
745− reg_gfx_index.bitfields.instance_index);
746− pr_debug("\t\t sebw is : %u\n",
747− reg_gfx_index.bitfields.se_broadcast_writes);
748− pr_debug("\t\t se_ind is : %u\n", reg_gfx_index.bitfields.se_index);
749− pr_debug("\t\t sh_ind is : %u\n", reg_gfx_index.bitfields.sh_index);
750− pr_debug("\t\t sbw is : %u\n",
751− reg_gfx_index.bitfields.sh_broadcast_writes);
752−
753− pr_debug("\t\t %30s\n", "* * * * * * * * * * * * * * * * * *");
754−
755− return dbgdev->dev->kfd2kgd->wave_control_execute(dbgdev->dev->adev,
756− reg_gfx_index.u32All,
757− reg_sq_cmd.u32All);
758−}
759−
760−int dbgdev_wave_reset_wavefronts(struct kfd_dev *dev, struct kfd_process *p)
761−{
762− int status = 0;
763− unsigned int vmid;
764− uint16_t queried_pasid;
765− union SQ_CMD_BITS reg_sq_cmd;
766− union GRBM_GFX_INDEX_BITS reg_gfx_index;
767− struct kfd_process_device *pdd;
768− struct dbg_wave_control_info wac_info;
769− int first_vmid_to_scan = dev->vm_info.first_vmid_kfd;
770− int last_vmid_to_scan = dev->vm_info.last_vmid_kfd;
771−
772− reg_sq_cmd.u32All = 0;
773− status = 0;
774−
775− wac_info.mode = HSA_DBG_WAVEMODE_BROADCAST_PROCESS;
776− wac_info.operand = HSA_DBG_WAVEOP_KILL;
777−
778− pr_debug("Killing all process wavefronts\n");
779−
780− /* Scan all registers in the range ATC_VMID8_PASID_MAPPING ..
781− * ATC_VMID15_PASID_MAPPING
782− * to check which VMID the current process is mapped to.
783− */
784−
785− for (vmid = first_vmid_to_scan; vmid <= last_vmid_to_scan; vmid++) {
786− status = dev->kfd2kgd->get_atc_vmid_pasid_mapping_info
787− (dev->adev, vmid, &queried_pasid);
788−
789− if (status && queried_pasid == p->pasid) {
790− pr_debug("Killing wave fronts of vmid %d and pasid 0x%x\n",
791− vmid, p->pasid);
792− break;
793− }
794− }
795−
796− if (vmid > last_vmid_to_scan) {
797− pr_err("Didn't find vmid for pasid 0x%x\n", p->pasid);
798− return -EFAULT;
799− }
800−
801− /* taking the VMID for that process on the safe way using PDD */
802− pdd = kfd_get_process_device_data(dev, p);
803− if (!pdd)
804− return -EFAULT;
805−
806− status = dbgdev_wave_control_set_registers(&wac_info, &reg_sq_cmd,
807− &reg_gfx_index);
808− if (status != 0)
809− return -EINVAL;
810−
811− /* for non DIQ we need to patch the VMID: */
812− reg_sq_cmd.bits.vm_id = vmid;
813−
814− dev->kfd2kgd->wave_control_execute(dev->adev,
815− reg_gfx_index.u32All,
816− reg_sq_cmd.u32All);
817−
818− return 0;
819−}
820−
821−void kfd_dbgdev_init(struct kfd_dbgdev *pdbgdev, struct kfd_dev *pdev,
822− enum DBGDEV_TYPE type)
823−{
824− pdbgdev->dev = pdev;
825− pdbgdev->kq = NULL;
826− pdbgdev->type = type;
827− pdbgdev->pqm = NULL;
828−
829− switch (type) {
830− case DBGDEV_TYPE_NODIQ:
831− pdbgdev->dbgdev_register = dbgdev_register_nodiq;
832− pdbgdev->dbgdev_unregister = dbgdev_unregister_nodiq;
833− pdbgdev->dbgdev_wave_control = dbgdev_wave_control_nodiq;
834− pdbgdev->dbgdev_address_watch = dbgdev_address_watch_nodiq;
835− break;
836− case DBGDEV_TYPE_DIQ:
837− default:
838− pdbgdev->dbgdev_register = dbgdev_register_diq;
839− pdbgdev->dbgdev_unregister = dbgdev_unregister_diq;
840− pdbgdev->dbgdev_wave_control = dbgdev_wave_control_diq;
841− pdbgdev->dbgdev_address_watch = dbgdev_address_watch_diq;
842− break;
843− }
844−
845−}
drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.h+0−230
@@ -1,230 +0,0 @@
1−/*
2− * Copyright 2014 Advanced Micro Devices, Inc.
3− *
4− * Permission is hereby granted, free of charge, to any person obtaining a
5− * copy of this software and associated documentation files (the "Software"),
6− * to deal in the Software without restriction, including without limitation
7− * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8− * and/or sell copies of the Software, and to permit persons to whom the
9− * Software is furnished to do so, subject to the following conditions:
10− *
11− * The above copyright notice and this permission notice shall be included in
12− * all copies or substantial portions of the Software.
13− *
14− * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15− * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16− * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17− * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18− * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19− * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20− * OTHER DEALINGS IN THE SOFTWARE.
21− */
22−
23−#ifndef KFD_DBGDEV_H_
24−#define KFD_DBGDEV_H_
25−
26−enum {
27− SQ_CMD_VMID_OFFSET = 28,
28− ADDRESS_WATCH_CNTL_OFFSET = 24
29−};
30−
31−enum {
32− PRIV_QUEUE_SYNC_TIME_MS = 200
33−};
34−
35−/* CONTEXT reg space definition */
36−enum {
37− CONTEXT_REG_BASE = 0xA000,
38− CONTEXT_REG_END = 0xA400,
39− CONTEXT_REG_SIZE = CONTEXT_REG_END - CONTEXT_REG_BASE
40−};
41−
42−/* USER CONFIG reg space definition */
43−enum {
44− USERCONFIG_REG_BASE = 0xC000,
45− USERCONFIG_REG_END = 0x10000,
46− USERCONFIG_REG_SIZE = USERCONFIG_REG_END - USERCONFIG_REG_BASE
47−};
48−
49−/* CONFIG reg space definition */
50−enum {
51− AMD_CONFIG_REG_BASE = 0x2000, /* in dwords */
52− AMD_CONFIG_REG_END = 0x2B00,
53− AMD_CONFIG_REG_SIZE = AMD_CONFIG_REG_END - AMD_CONFIG_REG_BASE
54−};
55−
56−/* SH reg space definition */
57−enum {
58− SH_REG_BASE = 0x2C00,
59− SH_REG_END = 0x3000,
60− SH_REG_SIZE = SH_REG_END - SH_REG_BASE
61−};
62−
63−/* SQ_CMD definitions */
64−#define SQ_CMD 0x8DEC
65−
66−enum SQ_IND_CMD_CMD {
67− SQ_IND_CMD_CMD_NULL = 0x00000000,
68− SQ_IND_CMD_CMD_HALT = 0x00000001,
69− SQ_IND_CMD_CMD_RESUME = 0x00000002,
70− SQ_IND_CMD_CMD_KILL = 0x00000003,
71− SQ_IND_CMD_CMD_DEBUG = 0x00000004,
72− SQ_IND_CMD_CMD_TRAP = 0x00000005,
73−};
74−
75−enum SQ_IND_CMD_MODE {
76− SQ_IND_CMD_MODE_SINGLE = 0x00000000,
77− SQ_IND_CMD_MODE_BROADCAST = 0x00000001,
78− SQ_IND_CMD_MODE_BROADCAST_QUEUE = 0x00000002,
79− SQ_IND_CMD_MODE_BROADCAST_PIPE = 0x00000003,
80− SQ_IND_CMD_MODE_BROADCAST_ME = 0x00000004,
81−};
82−
83−union SQ_IND_INDEX_BITS {
84− struct {
85− uint32_t wave_id:4;
86− uint32_t simd_id:2;
87− uint32_t thread_id:6;
88− uint32_t:1;
89− uint32_t force_read:1;
90− uint32_t read_timeout:1;
91− uint32_t unindexed:1;
92− uint32_t index:16;
93−
94− } bitfields, bits;
95− uint32_t u32All;
96− signed int i32All;
97− float f32All;
98−};
99−
100−union SQ_IND_CMD_BITS {
101− struct {
102− uint32_t data:32;
103− } bitfields, bits;
104− uint32_t u32All;
105− signed int i32All;
106− float f32All;
107−};
108−
109−union SQ_CMD_BITS {
110− struct {
111− uint32_t cmd:3;
112− uint32_t:1;
113− uint32_t mode:3;
114− uint32_t check_vmid:1;
115− uint32_t trap_id:3;
116− uint32_t:5;
117− uint32_t wave_id:4;
118− uint32_t simd_id:2;
119− uint32_t:2;
120− uint32_t queue_id:3;
121− uint32_t:1;
122− uint32_t vm_id:4;
123− } bitfields, bits;
124− uint32_t u32All;
125− signed int i32All;
126− float f32All;
127−};
128−
129−union SQ_IND_DATA_BITS {
130− struct {
131− uint32_t data:32;
132− } bitfields, bits;
133− uint32_t u32All;
134− signed int i32All;
135− float f32All;
136−};
137−
138−union GRBM_GFX_INDEX_BITS {
139− struct {
140− uint32_t instance_index:8;
141− uint32_t sh_index:8;
142− uint32_t se_index:8;
143− uint32_t:5;
144− uint32_t sh_broadcast_writes:1;
145− uint32_t instance_broadcast_writes:1;
146− uint32_t se_broadcast_writes:1;
147− } bitfields, bits;
148− uint32_t u32All;
149− signed int i32All;
150− float f32All;
151−};
152−
153−union TCP_WATCH_ADDR_H_BITS {
154− struct {
155− uint32_t addr:16;
156− uint32_t:16;
157−
158− } bitfields, bits;
159− uint32_t u32All;
160− signed int i32All;
161− float f32All;
162−};
163−
164−union TCP_WATCH_ADDR_L_BITS {
165− struct {
166− uint32_t:6;
167− uint32_t addr:26;
168− } bitfields, bits;
169− uint32_t u32All;
170− signed int i32All;
171− float f32All;
172−};
173−
174−enum {
175− QUEUESTATE__INVALID = 0, /* so by default we'll get invalid state */
176− QUEUESTATE__ACTIVE_COMPLETION_PENDING,
177− QUEUESTATE__ACTIVE
178−};
179−
180−union ULARGE_INTEGER {
181− struct {
182− uint32_t low_part;
183− uint32_t high_part;
184− } u;
185− unsigned long long quad_part;
186−};
187−
188−
189−#define KFD_CIK_VMID_START_OFFSET (8)
190−#define KFD_CIK_VMID_END_OFFSET (KFD_CIK_VMID_START_OFFSET + (8))
191−
192−
193−void kfd_dbgdev_init(struct kfd_dbgdev *pdbgdev, struct kfd_dev *pdev,
194− enum DBGDEV_TYPE type);
195−
196−union TCP_WATCH_CNTL_BITS {
197− struct {
198− uint32_t mask:24;
199− uint32_t vmid:4;
200− uint32_t atc:1;
201− uint32_t mode:2;
202− uint32_t valid:1;
203− } bitfields, bits;
204− uint32_t u32All;
205− signed int i32All;
206− float f32All;
207−};
208−
209−enum {
210− ADDRESS_WATCH_REG_CNTL_ATC_BIT = 0x10000000UL,
211− ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK = 0x00FFFFFF,
212− ADDRESS_WATCH_REG_ADDLOW_MASK_EXTENSION = 0x03000000,
213− /* extend the mask to 26 bits in order to match the low address field */
214− ADDRESS_WATCH_REG_ADDLOW_SHIFT = 6,
215− ADDRESS_WATCH_REG_ADDHIGH_MASK = 0xFFFF
216−};
217−
218−enum {
219− MAX_TRAPID = 8, /* 3 bits in the bitfield. */
220− MAX_WATCH_ADDRESSES = 4
221−};
222−
223−enum {
224− ADDRESS_WATCH_REG_ADDR_HI = 0,
225− ADDRESS_WATCH_REG_ADDR_LO,
226− ADDRESS_WATCH_REG_CNTL,
227− ADDRESS_WATCH_REG_MAX
228−};
229−
230−#endif /* KFD_DBGDEV_H_ */
drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.c+0−158
@@ -1,158 +0,0 @@
1−/*
2− * Copyright 2014 Advanced Micro Devices, Inc.
3− *
4− * Permission is hereby granted, free of charge, to any person obtaining a
5− * copy of this software and associated documentation files (the "Software"),
6− * to deal in the Software without restriction, including without limitation
7− * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8− * and/or sell copies of the Software, and to permit persons to whom the
9− * Software is furnished to do so, subject to the following conditions:
10− *
11− * The above copyright notice and this permission notice shall be included in
12− * all copies or substantial portions of the Software.
13− *
14− * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15− * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16− * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17− * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18− * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19− * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20− * OTHER DEALINGS IN THE SOFTWARE.
21− *
22− */
23−#include <linux/types.h>
24−#include <linux/kernel.h>
25−#include <linux/log2.h>
26−#include <linux/sched.h>
27−#include <linux/slab.h>
28−#include <linux/device.h>
29−
30−#include "kfd_priv.h"
31−#include "cik_regs.h"
32−#include "kfd_pm4_headers.h"
33−#include "kfd_pm4_headers_diq.h"
34−#include "kfd_dbgmgr.h"
35−#include "kfd_dbgdev.h"
36−#include "kfd_device_queue_manager.h"
37−
38−static DEFINE_MUTEX(kfd_dbgmgr_mutex);
39−
40−struct mutex *kfd_get_dbgmgr_mutex(void)
41−{
42− return &kfd_dbgmgr_mutex;
43−}
44−
45−
46−static void kfd_dbgmgr_uninitialize(struct kfd_dbgmgr *pmgr)
47−{
48− kfree(pmgr->dbgdev);
49−
50− pmgr->dbgdev = NULL;
51− pmgr->pasid = 0;
52− pmgr->dev = NULL;
53−}
54−
55−void kfd_dbgmgr_destroy(struct kfd_dbgmgr *pmgr)
56−{
57− if (pmgr) {
58− kfd_dbgmgr_uninitialize(pmgr);
59− kfree(pmgr);
60− }
61−}
62−
63−bool kfd_dbgmgr_create(struct kfd_dbgmgr **ppmgr, struct kfd_dev *pdev)
64−{
65− enum DBGDEV_TYPE type = DBGDEV_TYPE_DIQ;
66− struct kfd_dbgmgr *new_buff;
67−
68− if (WARN_ON(!pdev->init_complete))
69− return false;
70−
71− new_buff = kfd_alloc_struct(new_buff);
72− if (!new_buff) {
73− pr_err("Failed to allocate dbgmgr instance\n");
74− return false;
75− }
76−
77− new_buff->pasid = 0;
78− new_buff->dev = pdev;
79− new_buff->dbgdev = kfd_alloc_struct(new_buff->dbgdev);
80− if (!new_buff->dbgdev) {
81− pr_err("Failed to allocate dbgdev instance\n");
82− kfree(new_buff);
83− return false;
84− }
85−
86− /* get actual type of DBGDevice cpsch or not */
87− if (pdev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS)
88− type = DBGDEV_TYPE_NODIQ;
89−
90− kfd_dbgdev_init(new_buff->dbgdev, pdev, type);
91− *ppmgr = new_buff;
92−
93− return true;
94−}
95−
96−long kfd_dbgmgr_register(struct kfd_dbgmgr *pmgr, struct kfd_process *p)
97−{
98− if (pmgr->pasid != 0) {
99− pr_debug("H/W debugger is already active using pasid 0x%x\n",
100− pmgr->pasid);
101− return -EBUSY;
102− }
103−
104− /* remember pasid */
105− pmgr->pasid = p->pasid;
106−
107− /* provide the pqm for diq generation */
108− pmgr->dbgdev->pqm = &p->pqm;
109−
110− /* activate the actual registering */
111− pmgr->dbgdev->dbgdev_register(pmgr->dbgdev);
112−
113− return 0;
114−}
115−
116−long kfd_dbgmgr_unregister(struct kfd_dbgmgr *pmgr, struct kfd_process *p)
117−{
118− /* Is the requests coming from the already registered process? */
119− if (pmgr->pasid != p->pasid) {
120− pr_debug("H/W debugger is not registered by calling pasid 0x%x\n",
121− p->pasid);
122− return -EINVAL;
123− }
124−
125− pmgr->dbgdev->dbgdev_unregister(pmgr->dbgdev);
126−
127− pmgr->pasid = 0;
128−
129− return 0;
130−}
131−
132−long kfd_dbgmgr_wave_control(struct kfd_dbgmgr *pmgr,
133− struct dbg_wave_control_info *wac_info)
134−{
135− /* Is the requests coming from the already registered process? */
136− if (pmgr->pasid != wac_info->process->pasid) {
137− pr_debug("H/W debugger support was not registered for requester pasid 0x%x\n",
138− wac_info->process->pasid);
139− return -EINVAL;
140− }
141−
142− return (long) pmgr->dbgdev->dbgdev_wave_control(pmgr->dbgdev, wac_info);
143−}
144−
145−long kfd_dbgmgr_address_watch(struct kfd_dbgmgr *pmgr,
146− struct dbg_address_watch_info *adw_info)
147−{
148− /* Is the requests coming from the already registered process? */
149− if (pmgr->pasid != adw_info->process->pasid) {
150− pr_debug("H/W debugger support was not registered for requester pasid 0x%x\n",
151− adw_info->process->pasid);
152− return -EINVAL;
153− }
154−
155− return (long) pmgr->dbgdev->dbgdev_address_watch(pmgr->dbgdev,
156− adw_info);
157−}
158−
drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.h+0−293
@@ -1,293 +0,0 @@
1−/*
2− * Copyright 2014 Advanced Micro Devices, Inc.
3− *
4− * Permission is hereby granted, free of charge, to any person obtaining a
5− * copy of this software and associated documentation files (the "Software"),
6− * to deal in the Software without restriction, including without limitation
7− * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8− * and/or sell copies of the Software, and to permit persons to whom the
9− * Software is furnished to do so, subject to the following conditions:
10− *
11− * The above copyright notice and this permission notice shall be included in
12− * all copies or substantial portions of the Software.
13− *
14− * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15− * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16− * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17− * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18− * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19− * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20− * OTHER DEALINGS IN THE SOFTWARE.
21− *
22− */
23−
24−#ifndef KFD_DBGMGR_H_
25−#define KFD_DBGMGR_H_
26−
27−#include "kfd_priv.h"
28−
29−/* must align with hsakmttypes definition */
30−#pragma pack(push, 4)
31−
32−enum HSA_DBG_WAVEOP {
33− HSA_DBG_WAVEOP_HALT = 1, /* Halts a wavefront */
34− HSA_DBG_WAVEOP_RESUME = 2, /* Resumes a wavefront */
35− HSA_DBG_WAVEOP_KILL = 3, /* Kills a wavefront */
36− HSA_DBG_WAVEOP_DEBUG = 4, /* Causes wavefront to enter dbg mode */
37− HSA_DBG_WAVEOP_TRAP = 5, /* Causes wavefront to take a trap */
38− HSA_DBG_NUM_WAVEOP = 5,
39− HSA_DBG_MAX_WAVEOP = 0xFFFFFFFF
40−};
41−
42−enum HSA_DBG_WAVEMODE {
43− /* send command to a single wave */
44− HSA_DBG_WAVEMODE_SINGLE = 0,
45− /*
46− * Broadcast to all wavefronts of all processes is not
47− * supported for HSA user mode
48− */
49−
50− /* send to waves within current process */
51− HSA_DBG_WAVEMODE_BROADCAST_PROCESS = 2,
52− /* send to waves within current process on CU */
53− HSA_DBG_WAVEMODE_BROADCAST_PROCESS_CU = 3,
54− HSA_DBG_NUM_WAVEMODE = 3,
55− HSA_DBG_MAX_WAVEMODE = 0xFFFFFFFF
56−};
57−
58−enum HSA_DBG_WAVEMSG_TYPE {
59− HSA_DBG_WAVEMSG_AUTO = 0,
60− HSA_DBG_WAVEMSG_USER = 1,
61− HSA_DBG_WAVEMSG_ERROR = 2,
62− HSA_DBG_NUM_WAVEMSG,
63− HSA_DBG_MAX_WAVEMSG = 0xFFFFFFFF
64−};
65−
66−enum HSA_DBG_WATCH_MODE {
67− HSA_DBG_WATCH_READ = 0, /* Read operations only */
68− HSA_DBG_WATCH_NONREAD = 1, /* Write or Atomic operations only */
69− HSA_DBG_WATCH_ATOMIC = 2, /* Atomic Operations only */
70− HSA_DBG_WATCH_ALL = 3, /* Read, Write or Atomic operations */
71− HSA_DBG_WATCH_NUM,
72− HSA_DBG_WATCH_SIZE = 0xFFFFFFFF
73−};
74−
75−/* This structure is hardware specific and may change in the future */
76−struct HsaDbgWaveMsgAMDGen2 {
77− union {
78− struct ui32 {
79− uint32_t UserData:8; /* user data */
80− uint32_t ShaderArray:1; /* Shader array */
81− uint32_t Priv:1; /* Privileged */
82− uint32_t Reserved0:4; /* Reserved, should be 0 */
83− uint32_t WaveId:4; /* wave id */
84− uint32_t SIMD:2; /* SIMD id */
85− uint32_t HSACU:4; /* Compute unit */
86− uint32_t ShaderEngine:2;/* Shader engine */
87− uint32_t MessageType:2; /* see HSA_DBG_WAVEMSG_TYPE */
88− uint32_t Reserved1:4; /* Reserved, should be 0 */
89− } ui32;
90− uint32_t Value;
91− };
92− uint32_t Reserved2;
93−};
94−
95−union HsaDbgWaveMessageAMD {
96− struct HsaDbgWaveMsgAMDGen2 WaveMsgInfoGen2;
97− /* for future HsaDbgWaveMsgAMDGen3; */
98−};
99−
100−struct HsaDbgWaveMessage {
101− void *MemoryVA; /* ptr to associated host-accessible data */
102− union HsaDbgWaveMessageAMD DbgWaveMsg;
103−};
104−
105−/*
106− * TODO: This definitions to be MOVED to kfd_event, once it is implemented.
107− *
108− * HSA sync primitive, Event and HW Exception notification API definitions.
109− * The API functions allow the runtime to define a so-called sync-primitive,
110− * a SW object combining a user-mode provided "syncvar" and a scheduler event
111− * that can be signaled through a defined GPU interrupt. A syncvar is
112− * a process virtual memory location of a certain size that can be accessed
113− * by CPU and GPU shader code within the process to set and query the content
114− * within that memory. The definition of the content is determined by the HSA
115− * runtime and potentially GPU shader code interfacing with the HSA runtime.
116− * The syncvar values may be commonly written through an PM4 WRITE_DATA packet
117− * in the user mode instruction stream. The OS scheduler event is typically
118− * associated and signaled by an interrupt issued by the GPU, but other HSA
119− * system interrupt conditions from other HW (e.g. IOMMUv2) may be surfaced
120− * by the KFD by this mechanism, too.
121− */
122−
123−/* these are the new definitions for events */
124−enum HSA_EVENTTYPE {
125− HSA_EVENTTYPE_SIGNAL = 0, /* user-mode generated GPU signal */
126− HSA_EVENTTYPE_NODECHANGE = 1, /* HSA node change (attach/detach) */
127− HSA_EVENTTYPE_DEVICESTATECHANGE = 2, /* HSA device state change
128− * (start/stop)
129− */
130− HSA_EVENTTYPE_HW_EXCEPTION = 3, /* GPU shader exception event */
131− HSA_EVENTTYPE_SYSTEM_EVENT = 4, /* GPU SYSCALL with parameter info */
132− HSA_EVENTTYPE_DEBUG_EVENT = 5, /* GPU signal for debugging */
133− HSA_EVENTTYPE_PROFILE_EVENT = 6,/* GPU signal for profiling */
134− HSA_EVENTTYPE_QUEUE_EVENT = 7, /* GPU signal queue idle state
135− * (EOP pm4)
136− */
137− /* ... */
138− HSA_EVENTTYPE_MAXID,
139− HSA_EVENTTYPE_TYPE_SIZE = 0xFFFFFFFF
140−};
141−
142−/* Sub-definitions for various event types: Syncvar */
143−struct HsaSyncVar {
144− union SyncVar {
145− void *UserData; /* pointer to user mode data */
146− uint64_t UserDataPtrValue; /* 64bit compatibility of value */
147− } SyncVar;
148− uint64_t SyncVarSize;
149−};
150−
151−/* Sub-definitions for various event types: NodeChange */
152−
153−enum HSA_EVENTTYPE_NODECHANGE_FLAGS {
154− HSA_EVENTTYPE_NODECHANGE_ADD = 0,
155− HSA_EVENTTYPE_NODECHANGE_REMOVE = 1,
156− HSA_EVENTTYPE_NODECHANGE_SIZE = 0xFFFFFFFF
157−};
158−
159−struct HsaNodeChange {
160− /* HSA node added/removed on the platform */
161− enum HSA_EVENTTYPE_NODECHANGE_FLAGS Flags;
162−};
163−
164−/* Sub-definitions for various event types: DeviceStateChange */
165−enum HSA_EVENTTYPE_DEVICESTATECHANGE_FLAGS {
166− /* device started (and available) */
167− HSA_EVENTTYPE_DEVICESTATUSCHANGE_START = 0,
168− /* device stopped (i.e. unavailable) */
169− HSA_EVENTTYPE_DEVICESTATUSCHANGE_STOP = 1,
170− HSA_EVENTTYPE_DEVICESTATUSCHANGE_SIZE = 0xFFFFFFFF
171−};
172−
173−enum HSA_DEVICE {
174− HSA_DEVICE_CPU = 0,
175− HSA_DEVICE_GPU = 1,
176− MAX_HSA_DEVICE = 2
177−};
178−
179−struct HsaDeviceStateChange {
180− uint32_t NodeId; /* F-NUMA node that contains the device */
181− enum HSA_DEVICE Device; /* device type: GPU or CPU */
182− enum HSA_EVENTTYPE_DEVICESTATECHANGE_FLAGS Flags; /* event flags */
183−};
184−
185−struct HsaEventData {
186− enum HSA_EVENTTYPE EventType; /* event type */
187− union EventData {
188− /*
189− * return data associated with HSA_EVENTTYPE_SIGNAL
190− * and other events
191− */
192− struct HsaSyncVar SyncVar;
193−
194− /* data associated with HSA_EVENTTYPE_NODE_CHANGE */
195− struct HsaNodeChange NodeChangeState;
196−
197− /* data associated with HSA_EVENTTYPE_DEVICE_STATE_CHANGE */
198− struct HsaDeviceStateChange DeviceState;
199− } EventData;
200−
201− /* the following data entries are internal to the KFD & thunk itself */
202−
203− /* internal thunk store for Event data (OsEventHandle) */
204− uint64_t HWData1;
205− /* internal thunk store for Event data (HWAddress) */
206− uint64_t HWData2;
207− /* internal thunk store for Event data (HWData) */
208− uint32_t HWData3;
209−};
210−
211−struct HsaEventDescriptor {
212− /* event type to allocate */
213− enum HSA_EVENTTYPE EventType;
214− /* H-NUMA node containing GPU device that is event source */
215− uint32_t NodeId;
216− /* pointer to user mode syncvar data, syncvar->UserDataPtrValue
217− * may be NULL
218− */
219− struct HsaSyncVar SyncVar;
220−};
221−
222−struct HsaEvent {
223− uint32_t EventId;
224− struct HsaEventData EventData;
225−};
226−
227−#pragma pack(pop)
228−
229−enum DBGDEV_TYPE {
230− DBGDEV_TYPE_ILLEGAL = 0,
231− DBGDEV_TYPE_NODIQ = 1,
232− DBGDEV_TYPE_DIQ = 2,
233− DBGDEV_TYPE_TEST = 3
234−};
235−
236−struct dbg_address_watch_info {
237− struct kfd_process *process;
238− enum HSA_DBG_WATCH_MODE *watch_mode;
239− uint64_t *watch_address;
240− uint64_t *watch_mask;
241− struct HsaEvent *watch_event;
242− uint32_t num_watch_points;
243−};
244−
245−struct dbg_wave_control_info {
246− struct kfd_process *process;
247− uint32_t trapId;
248− enum HSA_DBG_WAVEOP operand;
249− enum HSA_DBG_WAVEMODE mode;
250− struct HsaDbgWaveMessage dbgWave_msg;
251−};
252−
253−struct kfd_dbgdev {
254−
255− /* The device that owns this data. */
256− struct kfd_dev *dev;
257−
258− /* kernel queue for DIQ */
259− struct kernel_queue *kq;
260−
261− /* a pointer to the pqm of the calling process */
262− struct process_queue_manager *pqm;
263−
264− /* type of debug device ( DIQ, non DIQ, etc. ) */
265− enum DBGDEV_TYPE type;
266−
267− /* virtualized function pointers to device dbg */
268− int (*dbgdev_register)(struct kfd_dbgdev *dbgdev);
269− int (*dbgdev_unregister)(struct kfd_dbgdev *dbgdev);
270− int (*dbgdev_address_watch)(struct kfd_dbgdev *dbgdev,
271− struct dbg_address_watch_info *adw_info);
272− int (*dbgdev_wave_control)(struct kfd_dbgdev *dbgdev,
273− struct dbg_wave_control_info *wac_info);
274−
275−};
276−
277−struct kfd_dbgmgr {
278− u32 pasid;
279− struct kfd_dev *dev;
280− struct kfd_dbgdev *dbgdev;
281−};
282−
283−/* prototypes for debug manager functions */
284−struct mutex *kfd_get_dbgmgr_mutex(void);
285−void kfd_dbgmgr_destroy(struct kfd_dbgmgr *pmgr);
286−bool kfd_dbgmgr_create(struct kfd_dbgmgr **ppmgr, struct kfd_dev *pdev);
287−long kfd_dbgmgr_register(struct kfd_dbgmgr *pmgr, struct kfd_process *p);
288−long kfd_dbgmgr_unregister(struct kfd_dbgmgr *pmgr, struct kfd_process *p);
289−long kfd_dbgmgr_wave_control(struct kfd_dbgmgr *pmgr,
290− struct dbg_wave_control_info *wac_info);
291−long kfd_dbgmgr_address_watch(struct kfd_dbgmgr *pmgr,
292− struct dbg_address_watch_info *adw_info);
293−#endif /* KFD_DBGMGR_H_ */
drivers/gpu/drm/amd/amdkfd/kfd_debugfs.c+3−2
@@ -1,5 +1,6 @@
1+// SPDX-License-Identifier: GPL-2.0 OR MIT
12 /*
2− * Copyright 2016-2017 Advanced Micro Devices, Inc.
3+ * Copyright 2016-2022 Advanced Micro Devices, Inc.
34 *
45 * Permission is hereby granted, free of charge, to any person obtaining a
56 * copy of this software and associated documentation files (the "Software"),
@@ -35,7 +36,7 @@ static int kfd_debugfs_open(struct inode *inode, struct file *file) · 29 unmodified lines
3536 }
3637 static int kfd_debugfs_hang_hws_read(struct seq_file *m, void *data)
3738 {
38− seq_printf(m, "echo gpu_id > hang_hws\n");
39+ seq_puts(m, "echo gpu_id > hang_hws\n");
3940 return 0;
4041 }
4142
drivers/gpu/drm/amd/amdkfd/kfd_device.c+34−33
@@ -1,5 +1,6 @@
1+// SPDX-License-Identifier: GPL-2.0 OR MIT
12 /*
2− * Copyright 2014 Advanced Micro Devices, Inc.
3+ * Copyright 2014-2022 Advanced Micro Devices, Inc.
34 *
45 * Permission is hereby granted, free of charge, to any person obtaining a
56 * copy of this software and associated documentation files (the "Software"),
@@ -64,34 +65,33 @@ static void kfd_device_info_set_sdma_queue_num(struct kfd_dev *kfd) · 58 unmodified lines
6465 uint32_t sdma_version = kfd->adev->ip_versions[SDMA0_HWIP][0];
6566
6667 switch (sdma_version) {
67− case IP_VERSION(4, 0, 0):/* VEGA10 */
68− case IP_VERSION(4, 0, 1):/* VEGA12 */
69− case IP_VERSION(4, 1, 0):/* RAVEN */
70− case IP_VERSION(4, 1, 1):/* RAVEN */
71− case IP_VERSION(4, 1, 2):/* RENOIR */
72− case IP_VERSION(5, 2, 1):/* VANGOGH */
73− case IP_VERSION(5, 2, 3):/* YELLOW_CARP */
74− kfd->device_info.num_sdma_queues_per_engine = 2;
75− break;
76− case IP_VERSION(4, 2, 0):/* VEGA20 */
77− case IP_VERSION(4, 2, 2):/* ARCTURUS */
78− case IP_VERSION(4, 4, 0):/* ALDEBARAN */
79− case IP_VERSION(5, 0, 0):/* NAVI10 */
80− case IP_VERSION(5, 0, 1):/* CYAN_SKILLFISH */
81− case IP_VERSION(5, 0, 2):/* NAVI14 */
82− case IP_VERSION(5, 0, 5):/* NAVI12 */
83− case IP_VERSION(5, 2, 0):/* SIENNA_CICHLID */
84− case IP_VERSION(5, 2, 2):/* NAVY_FLOUNDER */
85− case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */
86− case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */
87− kfd->device_info.num_sdma_queues_per_engine = 8;
88− break;
89− default:
90− dev_warn(kfd_device,
91− "Default sdma queue per engine(8) is set due to "
92− "mismatch of sdma ip block(SDMA_HWIP:0x%x).\n",
93− sdma_version);
94− kfd->device_info.num_sdma_queues_per_engine = 8;
68+ case IP_VERSION(4, 0, 0):/* VEGA10 */
69+ case IP_VERSION(4, 0, 1):/* VEGA12 */
70+ case IP_VERSION(4, 1, 0):/* RAVEN */
71+ case IP_VERSION(4, 1, 1):/* RAVEN */
72+ case IP_VERSION(4, 1, 2):/* RENOIR */
73+ case IP_VERSION(5, 2, 1):/* VANGOGH */
74+ case IP_VERSION(5, 2, 3):/* YELLOW_CARP */
75+ kfd->device_info.num_sdma_queues_per_engine = 2;
76+ break;
77+ case IP_VERSION(4, 2, 0):/* VEGA20 */
78+ case IP_VERSION(4, 2, 2):/* ARCTURUS */
79+ case IP_VERSION(4, 4, 0):/* ALDEBARAN */
80+ case IP_VERSION(5, 0, 0):/* NAVI10 */
81+ case IP_VERSION(5, 0, 1):/* CYAN_SKILLFISH */
82+ case IP_VERSION(5, 0, 2):/* NAVI14 */
83+ case IP_VERSION(5, 0, 5):/* NAVI12 */
84+ case IP_VERSION(5, 2, 0):/* SIENNA_CICHLID */
85+ case IP_VERSION(5, 2, 2):/* NAVY_FLOUNDER */
86+ case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */
87+ case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */
88+ kfd->device_info.num_sdma_queues_per_engine = 8;
89+ break;
90+ default:
91+ dev_warn(kfd_device,
92+ "Default sdma queue per engine(8) is set due to mismatch of sdma ip block(SDMA_HWIP:0x%x).\n",
93+ sdma_version);
94+ kfd->device_info.num_sdma_queues_per_engine = 8;
9595 }
9696 }
9797
@@ -111,6 +111,7 @@ static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd) · 13 unmodified lines
111111 case IP_VERSION(10, 3, 1): /* VANGOGH */
112112 case IP_VERSION(10, 3, 3): /* YELLOW_CARP */
113113 case IP_VERSION(10, 1, 3): /* CYAN_SKILLFISH */
114+ case IP_VERSION(10, 1, 4):
114115 case IP_VERSION(10, 1, 10): /* NAVI10 */
115116 case IP_VERSION(10, 1, 2): /* NAVI12 */
116117 case IP_VERSION(10, 1, 1): /* NAVI14 */
@@ -308,6 +309,7 @@ struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf) · 191 unmodified lines
308309 break;
309310 /* Cyan Skillfish */
310311 case IP_VERSION(10, 1, 3):
312+ case IP_VERSION(10, 1, 4):
311313 gfx_target_version = 100103;
312314 if (!vf)
313315 f2g = &gfx_v10_kfd2kgd;
@@ -437,7 +439,8 @@ static int kfd_gws_init(struct kfd_dev *kfd) · 123 unmodified lines
437439 return ret;
438440 }
439441
440−static void kfd_smi_init(struct kfd_dev *dev) {
442+static void kfd_smi_init(struct kfd_dev *dev)
443+{
441444 INIT_LIST_HEAD(&dev->smi_clients);
442445 spin_lock_init(&dev->smi_lock);
443446 }
@@ -570,14 +573,12 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, · 126 unmodified lines
570573
571574 svm_migrate_init(kfd->adev);
572575
573− if(kgd2kfd_resume_iommu(kfd))
576+ if (kgd2kfd_resume_iommu(kfd))
574577 goto device_iommu_error;
575578
576579 if (kfd_resume(kfd))
577580 goto kfd_resume_error;
578581
579− kfd->dbgmgr = NULL;
580−
581582 if (kfd_topology_add_device(kfd)) {
582583 dev_err(kfd_device, "Error adding device to topology\n");
583584 goto kfd_topology_add_device_error;
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c+221−48
@@ -1,5 +1,6 @@
1+// SPDX-License-Identifier: GPL-2.0 OR MIT
12 /*
2− * Copyright 2014 Advanced Micro Devices, Inc.
3+ * Copyright 2014-2022 Advanced Micro Devices, Inc.
34 *
45 * Permission is hereby granted, free of charge, to any person obtaining a
56 * copy of this software and associated documentation files (the "Software"),
@@ -58,7 +59,7 @@ static inline void deallocate_hqd(struct device_queue_manager *dqm, · 52 unmodified lines
5859 struct queue *q);
5960 static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q);
6061 static int allocate_sdma_queue(struct device_queue_manager *dqm,
61− struct queue *q);
62+ struct queue *q, const uint32_t *restore_sdma_id);
6263 static void kfd_process_hw_exception(struct work_struct *work);
6364
6465 static inline
@@ -144,7 +145,13 @@ static void decrement_queue_count(struct device_queue_manager *dqm, · 79 unmodified lines
144145 dqm->active_cp_queue_count--;
145146 }
146147
147−static int allocate_doorbell(struct qcm_process_device *qpd, struct queue *q)
148+/*
149+ * Allocate a doorbell ID to this queue.
150+ * If doorbell_id is passed in, make sure requested ID is valid then allocate it.
151+ */
152+static int allocate_doorbell(struct qcm_process_device *qpd,
153+ struct queue *q,
154+ uint32_t const *restore_id)
148155 {
149156 struct kfd_dev *dev = qpd->dqm->dev;
150157
@@ -152,6 +159,10 @@ static int allocate_doorbell(struct qcm_process_device *qpd, struct queue *q) · 1 unmodified line
152159 /* On pre-SOC15 chips we need to use the queue ID to
153160 * preserve the user mode ABI.
154161 */
162+
163+ if (restore_id && *restore_id != q->properties.queue_id)
164+ return -EINVAL;
165+
155166 q->doorbell_id = q->properties.queue_id;
156167 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
157168 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
@@ -160,25 +171,37 @@ static int allocate_doorbell(struct qcm_process_device *qpd, struct queue *q) · 2 unmodified lines
160171 * The doobell index distance between RLC (2*i) and (2*i+1)
161172 * for a SDMA engine is 512.
162173 */
163− uint32_t *idx_offset =
164− dev->shared_resources.sdma_doorbell_idx;
165174
166− q->doorbell_id = idx_offset[q->properties.sdma_engine_id]
167− + (q->properties.sdma_queue_id & 1)
168− * KFD_QUEUE_DOORBELL_MIRROR_OFFSET
169− + (q->properties.sdma_queue_id >> 1);
175+ uint32_t *idx_offset = dev->shared_resources.sdma_doorbell_idx;
176+ uint32_t valid_id = idx_offset[q->properties.sdma_engine_id]
177+ + (q->properties.sdma_queue_id & 1)
178+ * KFD_QUEUE_DOORBELL_MIRROR_OFFSET
179+ + (q->properties.sdma_queue_id >> 1);
180+
181+ if (restore_id && *restore_id != valid_id)
182+ return -EINVAL;
183+ q->doorbell_id = valid_id;
170184 } else {
171− /* For CP queues on SOC15 reserve a free doorbell ID */
172− unsigned int found;
173−
174− found = find_first_zero_bit(qpd->doorbell_bitmap,
175− KFD_MAX_NUM_OF_QUEUES_PER_PROCESS);
176− if (found >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) {
177− pr_debug("No doorbells available");
178− return -EBUSY;
185+ /* For CP queues on SOC15 */
186+ if (restore_id) {
187+ /* make sure that ID is free */
188+ if (__test_and_set_bit(*restore_id, qpd->doorbell_bitmap))
189+ return -EINVAL;
190+
191+ q->doorbell_id = *restore_id;
192+ } else {
193+ /* or reserve a free doorbell ID */
194+ unsigned int found;
195+
196+ found = find_first_zero_bit(qpd->doorbell_bitmap,
197+ KFD_MAX_NUM_OF_QUEUES_PER_PROCESS);
198+ if (found >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) {
199+ pr_debug("No doorbells available");
200+ return -EBUSY;
201+ }
202+ set_bit(found, qpd->doorbell_bitmap);
203+ q->doorbell_id = found;
179204 }
180− set_bit(found, qpd->doorbell_bitmap);
181− q->doorbell_id = found;
182205 }
183206
184207 q->properties.doorbell_off =
@@ -299,7 +322,9 @@ static void deallocate_vmid(struct device_queue_manager *dqm, · 114 unmodified lines
299322
300323 static int create_queue_nocpsch(struct device_queue_manager *dqm,
301324 struct queue *q,
302− struct qcm_process_device *qpd)
325+ struct qcm_process_device *qpd,
326+ const struct kfd_criu_queue_priv_data *qd,
327+ const void *restore_mqd, const void *restore_ctl_stack)
303328 {
304329 struct mqd_manager *mqd_mgr;
305330 int retval;
@@ -339,13 +364,13 @@ static int create_queue_nocpsch(struct device_queue_manager *dqm, · 33 unmodified lines
339364 q->pipe, q->queue);
340365 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
341366 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
342− retval = allocate_sdma_queue(dqm, q);
367+ retval = allocate_sdma_queue(dqm, q, qd ? &qd->sdma_id : NULL);
343368 if (retval)
344369 goto deallocate_vmid;
345370 dqm->asic_ops.init_sdma_vm(dqm, q, qpd);
346371 }
347372
348− retval = allocate_doorbell(qpd, q);
373+ retval = allocate_doorbell(qpd, q, qd ? &qd->doorbell_id : NULL);
349374 if (retval)
350375 goto out_deallocate_hqd;
351376
@@ -358,8 +383,15 @@ static int create_queue_nocpsch(struct device_queue_manager *dqm, · 6 unmodified lines
358383 retval = -ENOMEM;
359384 goto out_deallocate_doorbell;
360385 }
361− mqd_mgr->init_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj,
362− &q->gart_mqd_addr, &q->properties);
386+
387+ if (qd)
388+ mqd_mgr->restore_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj, &q->gart_mqd_addr,
389+ &q->properties, restore_mqd, restore_ctl_stack,
390+ qd->ctl_stack_size);
391+ else
392+ mqd_mgr->init_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj,
393+ &q->gart_mqd_addr, &q->properties);
394+
363395 if (q->properties.is_active) {
364396 if (!dqm->sched_running) {
365397 WARN_ONCE(1, "Load non-HWS mqd while stopped\n");
@@ -449,6 +481,65 @@ static inline void deallocate_hqd(struct device_queue_manager *dqm, · 83 unmodified lines
449481 dqm->allocated_queues[q->pipe] |= (1 << q->queue);
450482 }
451483
484+#define SQ_IND_CMD_CMD_KILL 0x00000003
485+#define SQ_IND_CMD_MODE_BROADCAST 0x00000001
486+
487+static int dbgdev_wave_reset_wavefronts(struct kfd_dev *dev, struct kfd_process *p)
488+{
489+ int status = 0;
490+ unsigned int vmid;
491+ uint16_t queried_pasid;
492+ union SQ_CMD_BITS reg_sq_cmd;
493+ union GRBM_GFX_INDEX_BITS reg_gfx_index;
494+ struct kfd_process_device *pdd;
495+ int first_vmid_to_scan = dev->vm_info.first_vmid_kfd;
496+ int last_vmid_to_scan = dev->vm_info.last_vmid_kfd;
497+
498+ reg_sq_cmd.u32All = 0;
499+ reg_gfx_index.u32All = 0;
500+
501+ pr_debug("Killing all process wavefronts\n");
502+
503+ /* Scan all registers in the range ATC_VMID8_PASID_MAPPING ..
504+ * ATC_VMID15_PASID_MAPPING
505+ * to check which VMID the current process is mapped to.
506+ */
507+
508+ for (vmid = first_vmid_to_scan; vmid <= last_vmid_to_scan; vmid++) {
509+ status = dev->kfd2kgd->get_atc_vmid_pasid_mapping_info
510+ (dev->adev, vmid, &queried_pasid);
511+
512+ if (status && queried_pasid == p->pasid) {
513+ pr_debug("Killing wave fronts of vmid %d and pasid 0x%x\n",
514+ vmid, p->pasid);
515+ break;
516+ }
517+ }
518+
519+ if (vmid > last_vmid_to_scan) {
520+ pr_err("Didn't find vmid for pasid 0x%x\n", p->pasid);
521+ return -EFAULT;

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drivers/gpu/drm/amd/display/dc/dml/calcs/bw_fixed.crenamed from drivers/gpu/drm/amd/display/dc/calcs/bw_fixed.c+0−0

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drivers/gpu/drm/amd/display/dc/dml/calcs/calcs_logger.hrenamed from drivers/gpu/drm/amd/display/dc/calcs/calcs_logger.h+0−0

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drivers/gpu/drm/amd/display/dc/dml/calcs/custom_float.crenamed from drivers/gpu/drm/amd/display/dc/calcs/custom_float.c+0−0

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drivers/gpu/drm/amd/display/dc/dml/calcs/dce_calcs.crenamed from drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c+23−25

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drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.crenamed from drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c+0−0

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drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_auto.hrenamed from drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.h+0−0

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drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calc_math.crenamed from drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c+0−0

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drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.crenamed from drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c+0−0

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drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.c+357−0

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drivers/gpu/drm/amd/display/dc/dml/dcn302/dcn302_fpu.h+32−0

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drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c+26−3

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drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c+24−0

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drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h+3−0

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drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c+1−1

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drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c+2−2

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drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c+2−2

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drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c+1−0

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drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c+1−0

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drivers/gpu/drm/amd/display/dc/inc/core_types.h+1−12

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drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h+44−12

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drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h+2−2

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drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h+0−2

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drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h+2−3

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drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h+4−6

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drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h+0−2

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drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h+0−2

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drivers/gpu/drm/amd/display/dc/inc/link_dpcd.h+1−1

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drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h+3−0

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drivers/gpu/drm/amd/display/dc/inc/link_hwss.h+44−42

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drivers/gpu/drm/amd/display/dc/inc/reg_helper.h+34−0

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drivers/gpu/drm/amd/display/dc/inc/resource.h+6−10

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drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c+2−2

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drivers/gpu/drm/amd/display/dc/link/Makefile+30−0

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drivers/gpu/drm/amd/display/dc/link/link_hwss_dio.c+137−0

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drivers/gpu/drm/amd/display/dc/link/link_hwss_dio.h+53−0

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drivers/gpu/drm/amd/display/dc/link/link_hwss_dpia.c+51−0

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drivers/gpu/drm/amd/display/dc/link/link_hwss_dpia.h+34−0

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drivers/gpu/drm/amd/display/dc/link/link_hwss_hpo_dp.c+254−0

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drivers/gpu/drm/amd/display/dc/link/link_hwss_hpo_dp.h+35−0

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drivers/gpu/drm/amd/display/dc/link/link_hwss_hpo_frl.c+43−0

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drivers/gpu/drm/amd/display/dc/link/link_hwss_hpo_frl.h+34−0

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drivers/gpu/drm/amd/display/dc/virtual/Makefile+1−1

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drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c+2−1

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drivers/gpu/drm/amd/display/dc/virtual/virtual_link_hwss.c+43−0

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drivers/gpu/drm/amd/display/dc/virtual/virtual_link_hwss.h+34−0

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drivers/gpu/drm/amd/display/dmub/dmub_srv.h+1−0

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drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h+8−5

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drivers/gpu/drm/amd/display/dmub/src/Makefile+2−0

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drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c+1−1

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drivers/gpu/drm/amd/display/dmub/src/dmub_dcn316.c+62−0

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drivers/gpu/drm/amd/display/dmub/src/dmub_dcn316.h+33−0

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drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c+4−0

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drivers/gpu/drm/amd/display/include/bios_parser_types.h+0−2

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drivers/gpu/drm/amd/display/include/dal_asic_id.h+6−1

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drivers/gpu/drm/amd/display/include/dal_types.h+1−0

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drivers/gpu/drm/amd/display/include/ddc_service_types.h+5−0

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drivers/gpu/drm/amd/display/include/dpcd_defs.h+0−4

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drivers/gpu/drm/amd/display/include/grph_object_defs.h+0−2

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drivers/gpu/drm/amd/display/include/grph_object_id.h+0−2

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drivers/gpu/drm/amd/display/include/link_service_types.h+0−12

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drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h+2−1

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drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c+13−12

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drivers/gpu/drm/amd/include/amd_shared.h+1−2

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drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_6_offset.h+15682−0

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