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powerpc/book3s: Fix endianess issue for HMI handling on napping cpus.

(NOTE: This patch depends on upstream HMI handling patchset at https://lists.ozlabs.org/pipermail/linuxppc-dev/2014-July/119731.html) The current HMI handling on napping cpus does not take care of endianess issue. On LE host kernel when we wake up from nap due to HMI interrupt we would checkstop while jumping into opal call. There is a similar issue in case of fast sleep wakeup where the code invokes opal_resync_tb opal call without handling LE issue. This patch fixes that as well. With this patch applied, HMIs handling on LE host kernel works fine.

Mahesh Salgaonkar committed 12 years ago

Commit db97eff1 parent bbdb7601 file · +37 −12Browse files

Unified · Split

arch/powerpc/kernel/idle_power7.S+37−12
@@ -135,6 +135,39 @@ _GLOBAL(power7_sleep) · 134 unmodified lines
135135 b power7_powersave_common
136136 /* No return */
137137
138+/*
139+ * Make opal call in realmode. This is a generic function to be called
140+ * from realmode from reset vector. It handles endianess.
141+ *
142+ * r13 - paca pointer
143+ * r1 - stack pointer
144+ * r3 - opal token
145+ */
146+opal_call_realmode:
147+ mflr r12
148+ std r12,_LINK(r1)
149+ ld r2,PACATOC(r13)
150+ /* Set opal return address */
151+ LOAD_REG_ADDR(r0,return_from_opal_call)
152+ mtlr r0
153+ /* Handle endian-ness */
154+ li r0,MSR_LE
155+ mfmsr r12
156+ andc r12,r12,r0
157+ mtspr SPRN_HSRR1,r12
158+ mr r0,r3 /* Move opal token to r0 */
159+ LOAD_REG_ADDR(r11,opal)
160+ ld r12,8(r11)
161+ ld r2,0(r11)
162+ mtspr SPRN_HSRR0,r12
163+ hrfid
164+
165+return_from_opal_call:
166+ FIXUP_ENDIAN
167+ ld r0,_LINK(r1)
168+ mtlr r0
169+ blr
170+
138171 #define CHECK_HMI_INTERRUPT \
139172 mfspr r0,SPRN_SRR1; \
140173 BEGIN_FTR_SECTION_NESTED(66); \
@@ -148,12 +181,8 @@ ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_ARCH_207S, 66); \ · 7 unmodified lines
148181 ld r2,PACATOC(r13); \
149182 ld r1,PACAR1(r13); \
150183 std r3,ORIG_GPR3(r1); /* Save original r3 */ \
151− li r0,OPAL_HANDLE_HMI; \
152− LOAD_REG_ADDR(r11,opal); \
153− ld r12,8(r11); \
154− ld r2,0(r11); \
155− mtctr r12; \
156− bctrl; \
184+ li r3,OPAL_HANDLE_HMI; /* Pass opal token argument*/ \
185+ bl opal_call_realmode; \
157186 ld r3,ORIG_GPR3(r1); /* Restore original r3 */ \
158187 20: nop;
159188
@@ -166,12 +195,8 @@ BEGIN_FTR_SECTION · 6 unmodified lines
166195 CHECK_HMI_INTERRUPT
167196 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
168197 /* Time base re-sync */
169− li r0,OPAL_RESYNC_TIMEBASE
170− LOAD_REG_ADDR(r11,opal);
171− ld r12,8(r11);
172− ld r2,0(r11);
173− mtctr r12
174− bctrl
198+ li r3,OPAL_RESYNC_TIMEBASE
199+ bl opal_call_realmode;
175200
176201 /* TODO: Check r3 for failure */
177202