TXx9 SPI bit rate is calculated by: fBR = (spi-baseclk) / (n + 1) Fix calculation of min_speed_hz, max_speed_hz and n.
Unified · Split
| @@ -29,6 +29,8 @@ · 28 unmodified lines | ||
| 29 | 29 | |
| 30 | 30 | |
| 31 | 31 | #define SPI_FIFO_SIZE 4 |
| 32 | +#define SPI_MAX_DIVIDER 0xff /* Max. value for SPCR1.SER */ | |
| 33 | +#define SPI_MIN_DIVIDER 1 /* Min. value for SPCR1.SER */ | |
| 32 | 34 | |
| 33 | 35 | #define TXx9_SPMCR 0x00 |
| 34 | 36 | #define TXx9_SPCR0 0x04 |
| @@ -193,11 +195,8 @@ static void txx9spi_work_one(struct txx9spi *c, struct spi_message *m) · 158 unmodified lines | ||
| 193 | 195 | |
| 194 | 196 | if (prev_speed_hz != speed_hz |
| 195 | 197 | || prev_bits_per_word != bits_per_word) { |
| 196 | − u32 n = (c->baseclk + speed_hz - 1) / speed_hz; | |
| 197 | − if (n < 1) | |
| 198 | − n = 1; | |
| 199 | − else if (n > 0xff) | |
| 200 | − n = 0xff; | |
| 198 | + int n = DIV_ROUND_UP(c->baseclk, speed_hz) - 1; | |
| 199 | + n = clamp(n, SPI_MIN_DIVIDER, SPI_MAX_DIVIDER); | |
| 201 | 200 | /* enter config mode */ |
| 202 | 201 | txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, |
| 203 | 202 | TXx9_SPMCR); |
| @@ -370,8 +369,8 @@ static int __init txx9spi_probe(struct platform_device *dev) · 166 unmodified lines | ||
| 370 | 369 | goto exit; |
| 371 | 370 | } |
| 372 | 371 | c->baseclk = clk_get_rate(c->clk); |
| 373 | − c->min_speed_hz = (c->baseclk + 0xff - 1) / 0xff; | |
| 374 | − c->max_speed_hz = c->baseclk; | |
| 372 | + c->min_speed_hz = DIV_ROUND_UP(c->baseclk, SPI_MAX_DIVIDER + 1); | |
| 373 | + c->max_speed_hz = c->baseclk / (SPI_MIN_DIVIDER + 1); | |
| 375 | 374 | |
| 376 | 375 | res = platform_get_resource(dev, IORESOURCE_MEM, 0); |
| 377 | 376 | if (!res) |