History

Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (71 commits) MIPS: Lasat: Fix botched changes to sysctl code. RTC: rtc-cmos.c: Fix warning on MIPS MIPS: Cleanup random differences beween lmo and Linus' kernel. MIPS: No longer hardwire CONFIG_EMBEDDED to y MIPS: Fix and enhance built-in kernel command line MIPS: eXcite: Remove platform. MIPS: Loongson: Cleanups of serial port support MIPS: Lemote 2F: Suspend CS5536 MFGPT Timer MIPS: Excite: move iodev_remove to .devexit.text MIPS: Lasat: Convert to proc_fops / seq_file MIPS: Cleanup signal code initialization MIPS: Modularize COP2 handling MIPS: Move EARLY_PRINTK to Kconfig.debug MIPS: Yeeloong 2F: Cleanup reset logic using the new ec_write function MIPS: Yeeloong 2F: Add LID open event as the wakeup event MIPS: Yeeloong 2F: Add basic EC operations MIPS: Move several variables from .bss to .init.data MIPS: Tracing: Make function graph tracer work with -mmcount-ra-address MIPS: Tracing: Reserve $12(t0) for mcount-ra-address of gcc 4.5 MIPS: Tracing: Make ftrace for MIPS work without -fno-omit-frame-pointer ...

Linus Torvalds committed 16 years ago

Commit dbfc9852 parents 7c508e5 606d62f255 files · +18310 −4878Browse files

Unified · Split

255 files
  1. arch/mips/Kconfig +75 −44
  2. arch/mips/Kconfig.debug +55 −4
  3. arch/mips/Makefile +47 −10
  4. arch/mips/ar7/platform.c +1 −1
  5. arch/mips/basler/excite/Kconfig +0 −9
  6. arch/mips/basler/excite/Makefile +0 −8
  7. arch/mips/basler/excite/excite_device.c +0 −403
  8. arch/mips/basler/excite/excite_iodev.c +0 −178
  9. arch/mips/basler/excite/excite_iodev.h +0 −10
  10. arch/mips/basler/excite/excite_irq.c +0 −122
  11. arch/mips/basler/excite/excite_procfs.c +0 −92
  12. arch/mips/basler/excite/excite_prom.c +0 −144
  13. arch/mips/basler/excite/excite_setup.c +0 −302
  14. arch/mips/bcm47xx/prom.c +5 −5
  15. arch/mips/boot/Makefile +2 −6
  16. arch/mips/boot/addinitrd.c +0 −131
  17. arch/mips/boot/compressed/Makefile +100 −0
  18. arch/mips/boot/compressed/dbg.c +37 −0
  19. arch/mips/boot/compressed/decompress.c +126 −0
  20. arch/mips/boot/compressed/dummy.c +4 −0
  21. arch/mips/boot/compressed/head.S +56 −0
  22. arch/mips/boot/compressed/ld.script +150 −0
  23. arch/mips/boot/compressed/uart-16550.c +43 −0
  24. arch/mips/cavium-octeon/Makefile +1 −1
  25. arch/mips/cavium-octeon/cpu.c +52 −0
  26. arch/mips/cavium-octeon/octeon-platform.c +88 −0
  27. arch/mips/configs/ar7_defconfig +2 −2
  28. arch/mips/configs/bcm47xx_defconfig +1 −2
  29. arch/mips/configs/bcm63xx_defconfig +2 −1
  30. arch/mips/configs/bigsur_defconfig +1 −2
  31. arch/mips/configs/capcella_defconfig +2 −1
  32. arch/mips/configs/cavium-octeon_defconfig +1 −3
  33. arch/mips/configs/cobalt_defconfig +1 −2
  34. arch/mips/configs/db1000_defconfig +1 −2
  35. arch/mips/configs/db1100_defconfig +1 −2
  36. arch/mips/configs/db1200_defconfig +2 −1
  37. arch/mips/configs/db1500_defconfig +1 −2
  38. arch/mips/configs/db1550_defconfig +1 −2
  39. arch/mips/configs/decstation_defconfig +1 −2
  40. arch/mips/configs/e55_defconfig +2 −1
  41. arch/mips/configs/excite_defconfig +0 −1335
  42. arch/mips/configs/fuloong2e_defconfig +62 −34
  43. arch/mips/configs/ip22_defconfig +1 −2
  44. arch/mips/configs/ip27_defconfig +1 −2
  45. arch/mips/configs/ip28_defconfig +1 −2
  46. arch/mips/configs/ip32_defconfig +1 −2
  47. arch/mips/configs/jazz_defconfig +1 −2
  48. arch/mips/configs/jmr3927_defconfig +1 −2
  49. arch/mips/configs/lasat_defconfig +1 −2
  50. arch/mips/configs/lemote2f_defconfig +1835 −0
  51. arch/mips/configs/malta_defconfig +1 −2
  52. arch/mips/configs/markeins_defconfig +2 −1
  53. arch/mips/configs/mipssim_defconfig +2 −1
  54. arch/mips/configs/mpc30x_defconfig +2 −1
  55. arch/mips/configs/msp71xx_defconfig +1 −2
  56. arch/mips/configs/mtx1_defconfig +1 −2
  57. arch/mips/configs/pb1100_defconfig +1 −2
  58. arch/mips/configs/pb1500_defconfig +1 −2
  59. arch/mips/configs/pb1550_defconfig +1 −2
  60. arch/mips/configs/pnx8335-stb225_defconfig +1 −2
  61. arch/mips/configs/pnx8550-jbs_defconfig +2 −1
  62. arch/mips/configs/pnx8550-stb810_defconfig +2 −1
  63. arch/mips/configs/powertv_defconfig +1550 −0
  64. arch/mips/configs/rb532_defconfig +1 −2
  65. arch/mips/configs/rbtx49xx_defconfig +1 −3
  66. arch/mips/configs/rm200_defconfig +1 −2
  67. arch/mips/configs/sb1250-swarm_defconfig +1 −2
  68. arch/mips/configs/tb0219_defconfig +2 −1
  69. arch/mips/configs/tb0226_defconfig +2 −1
  70. arch/mips/configs/tb0287_defconfig +2 −1
  71. arch/mips/configs/workpad_defconfig +2 −1
  72. arch/mips/configs/wrppmc_defconfig +2 −1
  73. arch/mips/configs/yosemite_defconfig +1 −2
  74. arch/mips/fw/arc/cmdline.c +0 −5
  75. arch/mips/include/asm/bootinfo.h +4 −4
  76. arch/mips/include/asm/clock.h +64 −0
  77. arch/mips/include/asm/cop2.h +23 −0
  78. arch/mips/include/asm/cpu.h +2 −0
  79. arch/mips/include/asm/fpu.h +0 −8
  80. arch/mips/include/asm/fpu_emulator.h +17 −7
  81. arch/mips/include/asm/ftrace.h +90 −1
  82. arch/mips/include/asm/irq.h +2 −27
  83. arch/mips/include/asm/mach-excite/cpu-feature-overrides.h +0 −48
  84. arch/mips/include/asm/mach-excite/excite.h +0 −154
  85. arch/mips/include/asm/mach-excite/excite_fpga.h +0 −80
  86. arch/mips/include/asm/mach-excite/excite_nandflash.h +0 −7
  87. arch/mips/include/asm/mach-excite/rm9k_eth.h +0 −23
  88. arch/mips/include/asm/mach-excite/rm9k_wdt.h +0 −12
  89. arch/mips/include/asm/mach-excite/rm9k_xicap.h +0 −16
  90. arch/mips/include/asm/mach-loongson/cs5536/cs5536.h +305 −0
  91. arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h +35 −0
  92. arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h +153 −0
  93. arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h +31 −0
  94. arch/mips/include/asm/mach-loongson/dma-coherence.h +4 −0
  95. arch/mips/include/asm/mach-loongson/loongson.h +275 −15
  96. arch/mips/include/asm/mach-loongson/machine.h +7 −2
  97. arch/mips/include/asm/mach-loongson/mem.h +19 −8
  98. arch/mips/include/asm/mach-loongson/pci.h +29 −5
  99. arch/mips/include/asm/mach-powertv/asic.h +107 −0
  100. arch/mips/include/asm/mach-powertv/asic_regs.h +155 −0
  101. arch/mips/include/asm/mach-powertv/dma-coherence.h +119 −0
  102. arch/mips/include/asm/mach-powertv/interrupts.h +254 −0
  103. arch/mips/include/asm/mach-powertv/ioremap.h +90 −0
  104. arch/mips/include/asm/mach-powertv/irq.h +25 −0
  105. arch/mips/include/asm/mach-powertv/powertv-clock.h +29 −0
  106. arch/mips/include/asm/mach-powertv/war.h +11 −8
  107. arch/mips/include/asm/mips-boards/bonito64.h +0 −5
  108. arch/mips/include/asm/mmu_context.h +28 −1
  109. arch/mips/include/asm/octeon/cvmx-agl-defs.h +1194 −0
  110. arch/mips/include/asm/octeon/cvmx-mixx-defs.h +248 −0
  111. arch/mips/include/asm/octeon/cvmx-smix-defs.h +178 −0
  112. arch/mips/include/asm/octeon/octeon.h +1 −0
  113. arch/mips/include/asm/pgtable.h +13 −0
  114. arch/mips/include/asm/sgialib.h +1 −2
  115. arch/mips/include/asm/stackframe.h +22 −18
  116. arch/mips/kernel/Makefile +12 −2
  117. arch/mips/kernel/cpu-probe.c +2 −0
  118. arch/mips/kernel/cpufreq/Kconfig +41 −0
  119. arch/mips/kernel/cpufreq/Makefile +5 −0
  120. arch/mips/kernel/cpufreq/loongson2_clock.c +166 −0
  121. arch/mips/kernel/cpufreq/loongson2_cpufreq.c +227 −0
  122. arch/mips/kernel/csrc-powertv.c +180 −0
  123. arch/mips/kernel/ftrace.c +275 −0
  124. arch/mips/kernel/irq.c +30 −0
  125. arch/mips/kernel/mcount.S +189 −0
  126. arch/mips/kernel/mips_ksyms.c +5 −0
  127. arch/mips/kernel/setup.c +21 −23
  128. arch/mips/kernel/signal.c +46 −0
  129. arch/mips/kernel/signal32.c +24 −0
  130. arch/mips/kernel/smp.c +2 −1
  131. arch/mips/kernel/smtc.c +14 −7
  132. arch/mips/kernel/traps.c +45 −91
  133. arch/mips/kernel/unaligned.c +18 −7
  134. arch/mips/kernel/vmlinux.lds.S +1 −0
  135. arch/mips/lasat/picvue_proc.c +68 −45
  136. arch/mips/lasat/prom.c +2 −2
  137. arch/mips/lasat/sysctl.c +1 −1
  138. arch/mips/loongson/Kconfig +81 −27
  139. arch/mips/loongson/Makefile +6 −0
  140. arch/mips/loongson/common/Makefile +16 −2
  141. arch/mips/loongson/common/bonito-irq.c +8 −5
  142. arch/mips/loongson/common/cmdline.c +3 −1
  143. arch/mips/loongson/common/cs5536/Makefile +13 −0
  144. arch/mips/loongson/common/cs5536/cs5536_acc.c +140 −0
  145. arch/mips/loongson/common/cs5536/cs5536_ehci.c +158 −0
  146. arch/mips/loongson/common/cs5536/cs5536_ide.c +179 −0
  147. arch/mips/loongson/common/cs5536/cs5536_isa.c +316 −0
  148. arch/mips/loongson/common/cs5536/cs5536_mfgpt.c +217 −0
  149. arch/mips/loongson/common/cs5536/cs5536_ohci.c +147 −0
  150. arch/mips/loongson/common/cs5536/cs5536_pci.c +87 −0
  151. arch/mips/loongson/common/early_printk.c +10 −7
  152. arch/mips/loongson/common/env.c +3 −0
  153. arch/mips/loongson/common/init.c +14 −5
  154. arch/mips/loongson/common/irq.c +6 −6
  155. arch/mips/loongson/common/machtype.c +17 −8
  156. arch/mips/loongson/common/mem.c +87 −4
  157. arch/mips/loongson/common/pci.c +14 −6
  158. arch/mips/loongson/common/platform.c +30 −0
  159. arch/mips/loongson/common/pm.c +161 −0
  160. arch/mips/loongson/common/reset.c +1 −1
  161. arch/mips/loongson/common/serial.c +76 −0
  162. arch/mips/loongson/common/time.c +3 −0
  163. arch/mips/loongson/common/uart_base.c +45 −0
  164. arch/mips/loongson/fuloong-2e/irq.c +2 −2
  165. arch/mips/loongson/fuloong-2e/reset.c +2 −2
  166. arch/mips/loongson/lemote-2f/Makefile +11 −0
  167. arch/mips/loongson/lemote-2f/ec_kb3310b.c +130 −0
  168. arch/mips/loongson/lemote-2f/ec_kb3310b.h +188 −0
  169. arch/mips/loongson/lemote-2f/irq.c +134 −0
  170. arch/mips/loongson/lemote-2f/pm.c +149 −0
  171. arch/mips/loongson/lemote-2f/reset.c +159 −0
  172. arch/mips/math-emu/cp1emu.c +61 −41
  173. arch/mips/math-emu/dsemul.c +2 −2
  174. arch/mips/mipssim/Makefile +1 −2
  175. arch/mips/mipssim/sim_setup.c +0 −1
  176. arch/mips/mm/cerr-sb1.c +2 −5
  177. arch/mips/mm/init.c +2 −0
  178. arch/mips/mm/tlbex.c +25 −3
  179. arch/mips/mm/uasm.c +13 −3
  180. arch/mips/mm/uasm.h +7 −0
  181. arch/mips/mti-malta/malta-memory.c +1 −1
  182. arch/mips/nxp/pnx833x/common/interrupts.c +2 −2
  183. arch/mips/oprofile/op_model_loongson2.c +4 −1
  184. arch/mips/pci/Makefile +2 −2
  185. arch/mips/pci/fixup-excite.c +0 −36
  186. arch/mips/pci/fixup-fuloong2e.c +3 −2
  187. arch/mips/pci/fixup-lemote2f.c +160 −0
  188. arch/mips/pci/ops-bonito64.c +0 −7
  189. arch/mips/pci/ops-loongson2.c +208 −0
  190. arch/mips/pci/pci-excite.c +0 −149
  191. arch/mips/powertv/Kconfig +21 −0
  192. arch/mips/powertv/Makefile +28 −0
  193. arch/mips/powertv/asic/Kconfig +28 −0
  194. arch/mips/powertv/asic/Makefile +23 −0
  195. arch/mips/powertv/asic/asic-calliope.c +98 −0
  196. arch/mips/powertv/asic/asic-cronus.c +98 −0
  197. arch/mips/powertv/asic/asic-zeus.c +98 −0
  198. arch/mips/powertv/asic/asic_devices.c +787 −0
  199. arch/mips/powertv/asic/asic_int.c +125 −0
  200. arch/mips/powertv/asic/irq_asic.c +116 −0
  201. arch/mips/powertv/asic/prealloc-calliope.c +620 −0
  202. arch/mips/powertv/asic/prealloc-cronus.c +608 −0
  203. arch/mips/powertv/asic/prealloc-cronuslite.c +290 −0
  204. arch/mips/powertv/asic/prealloc-zeus.c +459 −0
  205. arch/mips/powertv/cmdline.c +52 −0
  206. arch/mips/powertv/init.c +128 −0
  207. arch/mips/powertv/init.h +28 −0
  208. arch/mips/powertv/memory.c +186 −0
  209. arch/mips/powertv/pci/Makefile +21 −0
  210. arch/mips/powertv/pci/fixup-powertv.c +36 −0
  211. arch/mips/powertv/pci/powertv-pci.h +31 −0
  212. arch/mips/powertv/powertv-clock.h +26 −0
  213. arch/mips/powertv/powertv_setup.c +351 −0
  214. arch/mips/powertv/reset.c +65 −0
  215. arch/mips/powertv/reset.h +26 −0
  216. arch/mips/powertv/time.c +13 −8
  217. arch/mips/rb532/prom.c +2 −2
  218. arch/mips/sgi-ip22/ip22-eisa.c +2 −2
  219. arch/mips/sgi-ip22/ip22-int.c +2 −1
  220. arch/mips/sgi-ip22/ip22-setup.c +1 −1
  221. arch/mips/sgi-ip22/ip22-time.c +2 −1
  222. arch/mips/sgi-ip32/ip32-setup.c +1 −1
  223. arch/mips/sibyte/common/cfe.c +2 −2
  224. arch/mips/sni/a20r.c +1 −1
  225. arch/mips/sni/pcimt.c +1 −1
  226. arch/mips/sni/pcit.c +1 −1
  227. arch/mips/sni/rm200.c +1 −1
  228. arch/mips/sni/setup.c +1 −1
  229. arch/mips/txx9/generic/setup.c +2 −2
  230. drivers/mtd/nand/Kconfig +0 −8
  231. drivers/mtd/nand/Makefile +0 −1
  232. drivers/mtd/nand/excite_nandflash.c +0 −248
  233. drivers/net/Kconfig +2 −0
  234. drivers/net/Makefile +2 −0
  235. drivers/net/octeon/Kconfig +10 −0
  236. drivers/net/octeon/Makefile +2 −0
  237. drivers/net/octeon/octeon_mgmt.c +1176 −0
  238. drivers/net/phy/Kconfig +11 −0
  239. drivers/net/phy/Makefile +1 −0
  240. drivers/net/phy/mdio-octeon.c +180 −0
  241. drivers/rtc/rtc-cmos.c +2 −1
  242. drivers/staging/octeon/Kconfig +2 −1
  243. drivers/staging/octeon/ethernet-mdio.c +78 −126
  244. drivers/staging/octeon/ethernet-mdio.h +1 −1
  245. drivers/staging/octeon/ethernet-proc.c +0 −112
  246. drivers/staging/octeon/ethernet-rgmii.c +28 −24
  247. drivers/staging/octeon/ethernet-sgmii.c +1 −1
  248. drivers/staging/octeon/ethernet-xaui.c +1 −1
  249. drivers/staging/octeon/ethernet.c +11 −12
  250. drivers/staging/octeon/octeon-ethernet.h +3 −3
  251. drivers/watchdog/Kconfig +0 −10
  252. drivers/watchdog/Makefile +0 −1
  253. drivers/watchdog/rm9k_wdt.c +0 −419
  254. scripts/Makefile.build +1 −0
  255. scripts/recordmcount.pl +55 −3
arch/mips/Kconfig+75−44
@@ -5,9 +5,12 @@ config MIPS · 4 unmodified lines
55 select HAVE_IDE
66 select HAVE_OPROFILE
77 select HAVE_ARCH_KGDB
8− # Horrible source of confusion. Die, die, die ...
9− select EMBEDDED
10− select RTC_LIB if !LEMOTE_FULOONG2E
8+ select HAVE_FUNCTION_TRACER
9+ select HAVE_FUNCTION_TRACE_MCOUNT_TEST
10+ select HAVE_DYNAMIC_FTRACE
11+ select HAVE_FTRACE_MCOUNT_RECORD
12+ select HAVE_FUNCTION_GRAPH_TRACER
13+ select RTC_LIB if !MACH_LOONGSON
1114
1215 mainmenu "Linux/MIPS Kernel Configuration"
1316
@@ -22,6 +25,7 @@ choice · 8 unmodified lines
2225
2326 config MACH_ALCHEMY
2427 bool "Alchemy processor based machines"
28+ select SYS_SUPPORTS_ZBOOT
2529
2630 config AR7
2731 bool "Texas Instruments AR7"
@@ -36,6 +40,7 @@ config AR7 · 8 unmodified lines
3640 select SYS_HAS_EARLY_PRINTK
3741 select SYS_SUPPORTS_32BIT_KERNEL
3842 select SYS_SUPPORTS_LITTLE_ENDIAN
43+ select SYS_SUPPORTS_ZBOOT_UART16550
3944 select GENERIC_GPIO
4045 select GCD
4146 select VLYNQ
@@ -43,23 +48,6 @@ config AR7 · 1 unmodified line
4348 Support for the Texas Instruments AR7 System-on-a-Chip
4449 family: TNETD7100, 7200 and 7300.
4550
46−config BASLER_EXCITE
47− bool "Basler eXcite smart camera"
48− select CEVT_R4K
49− select CSRC_R4K
50− select DMA_COHERENT
51− select HW_HAS_PCI
52− select IRQ_CPU
53− select IRQ_CPU_RM7K
54− select IRQ_CPU_RM9K
55− select MIPS_RM9122
56− select SYS_HAS_CPU_RM9000
57− select SYS_SUPPORTS_32BIT_KERNEL
58− select SYS_SUPPORTS_BIG_ENDIAN
59− help
60− The eXcite is a smart camera platform manufactured by
61− Basler Vision Technologies AG.
62−
6351 config BCM47XX
6452 bool "BCM47XX based boards"
6553 select CEVT_R4K
@@ -192,6 +180,7 @@ config LASAT · 126 unmodified lines
192180
193181 config MACH_LOONGSON
194182 bool "Loongson family of machines"
183+ select SYS_SUPPORTS_ZBOOT_UART16550
195184 help
196185 This enables the support of Loongson family of machines.
197186
@@ -233,6 +222,7 @@ config MIPS_MALTA · 35 unmodified lines
233222 select SYS_SUPPORTS_MIPS_CMP
234223 select SYS_SUPPORTS_MULTITHREADING
235224 select SYS_SUPPORTS_SMARTMIPS
225+ select SYS_SUPPORTS_ZBOOT
236226 help
237227 This enables support for the MIPS Technologies Malta evaluation
238228 board.
@@ -334,6 +324,24 @@ config PMC_YOSEMITE · 95 unmodified lines
334324 Yosemite is an evaluation board for the RM9000x2 processor
335325 manufactured by PMC-Sierra.
336326
327+config POWERTV
328+ bool "Cisco PowerTV"
329+ select BOOT_ELF32
330+ select CEVT_R4K
331+ select CPU_MIPSR2_IRQ_VI
332+ select CPU_MIPSR2_IRQ_EI
333+ select CSRC_POWERTV
334+ select DMA_NONCOHERENT
335+ select HW_HAS_PCI
336+ select SYS_HAS_EARLY_PRINTK
337+ select SYS_HAS_CPU_MIPS32_R2
338+ select SYS_SUPPORTS_32BIT_KERNEL
339+ select SYS_SUPPORTS_BIG_ENDIAN
340+ select SYS_SUPPORTS_HIGHMEM
341+ select USB_OHCI_LITTLE_ENDIAN
342+ help
343+ This enables support for the Cisco PowerTV Platform.
344+
337345 config SGI_IP22
338346 bool "SGI IP22 (Indy/Indigo2)"
339347 select ARC
@@ -674,11 +682,11 @@ config CAVIUM_OCTEON_REFERENCE_BOARD · 334 unmodified lines
674682 endchoice
675683
676684 source "arch/mips/alchemy/Kconfig"
677−source "arch/mips/basler/excite/Kconfig"
678685 source "arch/mips/bcm63xx/Kconfig"
679686 source "arch/mips/jazz/Kconfig"
680687 source "arch/mips/lasat/Kconfig"
681688 source "arch/mips/pmc-sierra/Kconfig"
689+source "arch/mips/powertv/Kconfig"
682690 source "arch/mips/sgi-ip27/Kconfig"
683691 source "arch/mips/sibyte/Kconfig"
684692 source "arch/mips/txx9/Kconfig"
@@ -778,6 +786,9 @@ config CSRC_BCM1480 · 93 unmodified lines
778786 config CSRC_IOASIC
779787 bool
780788
789+config CSRC_POWERTV
790+ bool
791+
781792 config CSRC_R4K_LIB
782793 bool
783794
@@ -806,20 +817,6 @@ config DMA_NONCOHERENT · 22 unmodified lines
806817 config DMA_NEED_PCI_MAP_STATE
807818 bool
808819
809−config EARLY_PRINTK
810− bool "Early printk" if EMBEDDED && DEBUG_KERNEL
811− depends on SYS_HAS_EARLY_PRINTK
812− default y
813− help
814− This option enables special console drivers which allow the kernel
815− to print messages very early in the bootup process.
816−
817− This is useful for kernel debugging when your machine crashes very
818− early before the console code is initialized. For normal operation,
819− it is not recommended because it looks ugly on some machines and
820− doesn't cooperate with an X server. You should normally say N here,
821− unless you want to debug such a crash.
822−
823820 config SYS_HAS_EARLY_PRINTK
824821 bool
825822
@@ -1069,6 +1066,21 @@ config CPU_LOONGSON2E · 243 unmodified lines
10691066 The Loongson 2E processor implements the MIPS III instruction set
10701067 with many extensions.
10711068
1069+ It has an internal FPGA northbridge, which is compatiable to
1070+ bonito64.
1071+
1072+config CPU_LOONGSON2F
1073+ bool "Loongson 2F"
1074+ depends on SYS_HAS_CPU_LOONGSON2F
1075+ select CPU_LOONGSON2
1076+ help
1077+ The Loongson 2F processor implements the MIPS III instruction set
1078+ with many extensions.
1079+
1080+ Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
1081+ have a similar programming interface with FPGA northbridge used in
1082+ Loongson2E.
1083+
10721084 config CPU_MIPS32_R1
10731085 bool "MIPS32 Release 1"
10741086 depends on SYS_HAS_CPU_MIPS32_R1
@@ -1294,6 +1306,16 @@ config CPU_CAVIUM_OCTEON · 219 unmodified lines
12941306
12951307 endchoice
12961308
1309+config SYS_SUPPORTS_ZBOOT
1310+ bool
1311+ select HAVE_KERNEL_GZIP
1312+ select HAVE_KERNEL_BZIP2
1313+ select HAVE_KERNEL_LZMA
1314+
1315+config SYS_SUPPORTS_ZBOOT_UART16550
1316+ bool
1317+ select SYS_SUPPORTS_ZBOOT
1318+
12971319 config CPU_LOONGSON2
12981320 bool
12991321 select CPU_SUPPORTS_32BIT_KERNEL
@@ -1303,6 +1325,12 @@ config CPU_LOONGSON2 · 3 unmodified lines
13031325 config SYS_HAS_CPU_LOONGSON2E
13041326 bool
13051327
1328+config SYS_HAS_CPU_LOONGSON2F
1329+ bool
1330+ select CPU_SUPPORTS_CPUFREQ
1331+ select CPU_SUPPORTS_ADDRWINCFG if 64BIT
1332+ select CPU_SUPPORTS_UNCACHED_ACCELERATED
1333+
13061334 config SYS_HAS_CPU_MIPS32_R1
13071335 bool
13081336
@@ -1411,8 +1439,17 @@ config CPU_SUPPORTS_32BIT_KERNEL · 102 unmodified lines
14111439 bool
14121440 config CPU_SUPPORTS_64BIT_KERNEL
14131441 bool
1442+config CPU_SUPPORTS_CPUFREQ
1443+ bool
1444+config CPU_SUPPORTS_ADDRWINCFG
1445+ bool
14141446 config CPU_SUPPORTS_HUGEPAGES
14151447 bool
1448+config CPU_SUPPORTS_UNCACHED_ACCELERATED
1449+ bool
1450+config MIPS_PGD_C0_CONTEXT
1451+ bool
1452+ default y if 64BIT && CPU_MIPSR2
14161453
14171454 #
14181455 # Set to y for ptrace access to watch registers.
@@ -2024,15 +2061,6 @@ config STACKTRACE_SUPPORT · 605 unmodified lines
20242061
20252062 source "init/Kconfig"
20262063
2027−config PROBE_INITRD_HEADER
2028− bool "Probe initrd header created by addinitrd"
2029− depends on BLK_DEV_INITRD
2030− help
2031− Probe initrd header at the last page of kernel image.
2032− Say Y here if you are using arch/mips/boot/addinitrd.c to
2033− add initrd or initramfs image to the kernel image.
2034− Otherwise, say N.
2035−
20362064 source "kernel/Kconfig.freezer"
20372065
20382066 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
@@ -2104,6 +2132,7 @@ config MMU · 65 unmodified lines
21042132
21052133 config I8253
21062134 bool
2135+ select MIPS_EXTERNAL_TIMER
21072136
21082137 config ZONE_DMA32
21092138 bool
@@ -2180,6 +2209,8 @@ source "kernel/power/Kconfig" · 70 unmodified lines
21802209
21812210 endmenu
21822211
2212+source "arch/mips/kernel/cpufreq/Kconfig"
2213+
21832214 source "net/Kconfig"
21842215
21852216 source "drivers/Kconfig"
arch/mips/Kconfig.debug+55−4
@@ -6,15 +6,66 @@ config TRACE_IRQFLAGS_SUPPORT · 5 unmodified lines
66
77 source "lib/Kconfig.debug"
88
9+config EARLY_PRINTK
10+ bool "Early printk" if EMBEDDED
11+ depends on SYS_HAS_EARLY_PRINTK
12+ default y
13+ help
14+ This option enables special console drivers which allow the kernel
15+ to print messages very early in the bootup process.
16+
17+ This is useful for kernel debugging when your machine crashes very
18+ early before the console code is initialized. For normal operation,
19+ it is not recommended because it looks ugly on some machines and
20+ doesn't cooperate with an X server. You should normally say N here,
21+ unless you want to debug such a crash.
22+
23+config CMDLINE_BOOL
24+ bool "Built-in kernel command line"
25+ default n
26+ help
27+ For most systems, it is firmware or second stage bootloader that
28+ by default specifies the kernel command line options. However,
29+ it might be necessary or advantageous to either override the
30+ default kernel command line or add a few extra options to it.
31+ For such cases, this option allows you to hardcode your own
32+ command line options directly into the kernel. For that, you
33+ should choose 'Y' here, and fill in the extra boot arguments
34+ in CONFIG_CMDLINE.
35+
36+ The built-in options will be concatenated to the default command
37+ line if CMDLINE_OVERRIDE is set to 'N'. Otherwise, the default
38+ command line will be ignored and replaced by the built-in string.
39+
40+ Most MIPS systems will normally expect 'N' here and rely upon
41+ the command line from the firmware or the second-stage bootloader.
42+
943 config CMDLINE
1044 string "Default kernel command string"
45+ depends on CMDLINE_BOOL
1146 default ""
1247 help
1348 On some platforms, there is currently no way for the boot loader to
14− pass arguments to the kernel. For these platforms, you can supply
15− some command-line options at build time by entering them here. In
16− other cases you can specify kernel args so that you don't have
17− to set them up in board prom initialization routines.
49+ pass arguments to the kernel. For these platforms, and for the cases
50+ when you want to add some extra options to the command line or ignore
51+ the default command line, you can supply some command-line options at
52+ build time by entering them here. In other cases you can specify
53+ kernel args so that you don't have to set them up in board prom
54+ initialization routines.
55+
56+ For more information, see the CMDLINE_BOOL and CMDLINE_OVERRIDE
57+ options.
58+
59+config CMDLINE_OVERRIDE
60+ bool "Built-in command line overrides firware arguments"
61+ default n
62+ depends on CMDLINE_BOOL
63+ help
64+ By setting this option to 'Y' you will have your kernel ignore
65+ command line arguments from firmware or second stage bootloader.
66+ Instead, the built-in command line will be used exclusively.
67+
68+ Normally, you will choose 'N' here.
1869
1970 config DEBUG_STACK_USAGE
2071 bool "Enable stack utilization instrumentation"
arch/mips/Makefile+47−10
@@ -48,7 +48,16 @@ ifneq ($(SUBARCH),$(ARCH)) · 47 unmodified lines
4848 endif
4949 endif
5050
51+ifndef CONFIG_FUNCTION_TRACER
5152 cflags-y := -ffunction-sections
53+endif
54+ifdef CONFIG_FUNCTION_GRAPH_TRACER
55+ ifndef KBUILD_MCOUNT_RA_ADDRESS
56+ ifeq ($(call cc-option-yn,-mmcount-ra-address), y)
57+ cflags-y += -mmcount-ra-address -DKBUILD_MCOUNT_RA_ADDRESS
58+ endif
59+ endif
60+endif
5261 cflags-y += $(call cc-option, -mno-check-zero-division)
5362
5463 ifdef CONFIG_32BIT
@@ -69,6 +78,7 @@ endif · 14 unmodified lines
6978
7079 all-$(CONFIG_BOOT_ELF32) := $(vmlinux-32)
7180 all-$(CONFIG_BOOT_ELF64) := $(vmlinux-64)
81+all-$(CONFIG_SYS_SUPPORTS_ZBOOT)+= vmlinuz
7282
7383 #
7484 # GCC uses -G 0 -mabicalls -fpic as default. We don't want PIC in the kernel
@@ -124,6 +134,8 @@ cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap · 49 unmodified lines
124134 cflags-$(CONFIG_CPU_LOONGSON2) += -Wa,--trap
125135 cflags-$(CONFIG_CPU_LOONGSON2E) += \
126136 $(call cc-option,-march=loongson2e,-march=r4600)
137+cflags-$(CONFIG_CPU_LOONGSON2F) += \
138+ $(call cc-option,-march=loongson2f,-march=r4600)
127139
128140 cflags-$(CONFIG_CPU_MIPS32_R1) += $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
129141 -Wa,-mips32 -Wa,--trap
@@ -324,6 +336,7 @@ core-$(CONFIG_MACH_LOONGSON) +=arch/mips/loongson/ · 194 unmodified lines
324336 cflags-$(CONFIG_MACH_LOONGSON) += -I$(srctree)/arch/mips/include/asm/mach-loongson \
325337 -mno-branch-likely
326338 load-$(CONFIG_LEMOTE_FULOONG2E) +=0xffffffff80100000
339+load-$(CONFIG_LEMOTE_MACH2F) +=0xffffffff80200000
327340
328341 #
329342 # MIPS Malta board
@@ -331,7 +344,7 @@ load-$(CONFIG_LEMOTE_FULOONG2E) +=0xffffffff80100000 · 1 unmodified line
331344 core-$(CONFIG_MIPS_MALTA) += arch/mips/mti-malta/
332345 cflags-$(CONFIG_MIPS_MALTA) += -I$(srctree)/arch/mips/include/asm/mach-malta
333346 load-$(CONFIG_MIPS_MALTA) += 0xffffffff80100000
334−all-$(CONFIG_MIPS_MALTA) := vmlinux.bin
347+all-$(CONFIG_MIPS_MALTA) := vmlinuz.bin
335348
336349 #
337350 # MIPS SIM
@@ -355,13 +368,6 @@ core-$(CONFIG_PMC_YOSEMITE) += arch/mips/pmc-sierra/yosemite/ · 17 unmodified lines
355368 cflags-$(CONFIG_PMC_YOSEMITE) += -I$(srctree)/arch/mips/include/asm/mach-yosemite
356369 load-$(CONFIG_PMC_YOSEMITE) += 0xffffffff80100000
357370
358−#
359−# Basler eXcite
360−#
361−core-$(CONFIG_BASLER_EXCITE) += arch/mips/basler/excite/
362−cflags-$(CONFIG_BASLER_EXCITE) += -I$(srctree)/arch/mips/include/asm/mach-excite
363−load-$(CONFIG_BASLER_EXCITE) += 0x80100000
364−
365371 #
366372 # LASAT platforms
367373 #
@@ -440,6 +446,13 @@ cflags-$(CONFIG_SOC_EMMA2RH) += -I$(srctree)/arch/mips/include/asm/mach-emma2rh · 72 unmodified lines
440446 core-$(CONFIG_NEC_MARKEINS) += arch/mips/emma/markeins/
441447 load-$(CONFIG_NEC_MARKEINS) += 0xffffffff88100000
442448
449+#
450+# Cisco PowerTV Platform
451+#
452+core-$(CONFIG_POWERTV) += arch/mips/powertv/
453+cflags-$(CONFIG_POWERTV) += -I$(srctree)/arch/mips/include/asm/mach-powertv
454+load-$(CONFIG_POWERTV) += 0xffffffff90800000
455+
443456 #
444457 # SGI IP22 (Indy/Indigo2)
445458 #
@@ -581,7 +594,7 @@ load-$(CONFIG_SNI_RM) += 0xffffffff80600000 · 135 unmodified lines
581594 else
582595 load-$(CONFIG_SNI_RM) += 0xffffffff80030000
583596 endif
584−all-$(CONFIG_SNI_RM) := vmlinux.ecoff
597+all-$(CONFIG_SNI_RM) := vmlinuz.ecoff
585598
586599 #
587600 # Common TXx9
@@ -699,9 +712,23 @@ vmlinux.64: vmlinux · 111 unmodified lines
699712 $(OBJCOPY) -O $(64bit-bfd) $(OBJCOPYFLAGS) $< $@
700713
701714 makeboot =$(Q)$(MAKE) $(build)=arch/mips/boot VMLINUX=$(vmlinux-32) $(1)
715+makezboot =$(Q)$(MAKE) $(build)=arch/mips/boot/compressed \
716+ VMLINUX_LOAD_ADDRESS=$(load-y) 32bit-bfd=$(32bit-bfd) $(1)
702717
703718 all: $(all-y)
704719
720+vmlinuz: vmlinux FORCE
721+ +@$(call makezboot,$@)
722+
723+vmlinuz.bin: vmlinux
724+ +@$(call makezboot,$@)
725+
726+vmlinuz.ecoff: vmlinux
727+ +@$(call makezboot,$@)
728+
729+vmlinuz.srec: vmlinux
730+ +@$(call makezboot,$@)
731+
705732 vmlinux.bin: $(vmlinux-32)
706733 +@$(call makeboot,$@)
707734
@@ -726,11 +753,13 @@ endif · 18 unmodified lines
726753
727754 install:
728755 $(Q)install -D -m 755 vmlinux $(INSTALL_PATH)/vmlinux-$(KERNELRELEASE)
756+ $(Q)install -D -m 755 vmlinuz $(INSTALL_PATH)/vmlinuz-$(KERNELRELEASE)
729757 $(Q)install -D -m 644 .config $(INSTALL_PATH)/config-$(KERNELRELEASE)
730758 $(Q)install -D -m 644 System.map $(INSTALL_PATH)/System.map-$(KERNELRELEASE)
731759
732760 archclean:
733761 @$(MAKE) $(clean)=arch/mips/boot
762+ @$(MAKE) $(clean)=arch/mips/boot/compressed
734763 @$(MAKE) $(clean)=arch/mips/lasat
735764
736765 define archhelp
@@ -738,10 +767,18 @@ define archhelp · 1 unmodified line
738767 echo ' vmlinux.ecoff - ECOFF boot image'
739768 echo ' vmlinux.bin - Raw binary boot image'
740769 echo ' vmlinux.srec - SREC boot image'
770+ echo ' vmlinuz - Compressed boot(zboot) image'
771+ echo ' vmlinuz.ecoff - ECOFF zboot image'
772+ echo ' vmlinuz.bin - Raw binary zboot image'
773+ echo ' vmlinuz.srec - SREC zboot image'
741774 echo
742775 echo ' These will be default as apropriate for a configured platform.'
743776 endef
744777
745778 CLEAN_FILES += vmlinux.32 \
746779 vmlinux.64 \
747− vmlinux.ecoff
780+ vmlinux.ecoff \
781+ vmlinuz \
782+ vmlinuz.ecoff \
783+ vmlinuz.bin \
784+ vmlinuz.srec
arch/mips/ar7/platform.c+1−1
@@ -505,7 +505,7 @@ static int __init ar7_register_devices(void) · 504 unmodified lines
505505 int res;
506506 u32 *bootcr, val;
507507 #ifdef CONFIG_SERIAL_8250
508− static struct uart_port uart_port[2];
508+ static struct uart_port uart_port[2] __initdata;
509509
510510 memset(uart_port, 0, sizeof(struct uart_port) * 2);
511511
arch/mips/basler/excite/Kconfig+0−9
@@ -1,9 +0,0 @@
1−config BASLER_EXCITE_PROTOTYPE
2− bool "Support for pre-release units"
3− depends on BASLER_EXCITE
4− default n
5− help
6− Pre-series (prototype) units are different from later ones in
7− some ways. Select this option if you have one of these. Please
8− note that a kernel built with this option selected will not be
9− able to run on normal units.
arch/mips/basler/excite/Makefile+0−8
@@ -1,8 +0,0 @@
1−#
2−# Makefile for Basler eXcite
3−#
4−
5−obj-$(CONFIG_BASLER_EXCITE) += excite_irq.o excite_prom.o excite_setup.o \
6− excite_device.o excite_procfs.o
7−
8−obj-m += excite_iodev.o
arch/mips/basler/excite/excite_device.c+0−403
@@ -1,403 +0,0 @@
1−/*
2− * Copyright (C) 2004 by Basler Vision Technologies AG
3− * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
4− *
5− * This program is free software; you can redistribute it and/or modify
6− * it under the terms of the GNU General Public License as published by
7− * the Free Software Foundation; either version 2 of the License, or
8− * (at your option) any later version.
9− *
10− * This program is distributed in the hope that it will be useful,
11− * but WITHOUT ANY WARRANTY; without even the implied warranty of
12− * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13− * GNU General Public License for more details.
14− *
15− * You should have received a copy of the GNU General Public License
16− * along with this program; if not, write to the Free Software
17− * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18− */
19−
20−#include <linux/kernel.h>
21−#include <linux/init.h>
22−#include <linux/platform_device.h>
23−#include <linux/ioport.h>
24−#include <linux/err.h>
25−#include <linux/jiffies.h>
26−#include <linux/sched.h>
27−#include <asm/types.h>
28−#include <asm/rm9k-ocd.h>
29−
30−#include <excite.h>
31−#include <rm9k_eth.h>
32−#include <rm9k_wdt.h>
33−#include <rm9k_xicap.h>
34−#include <excite_nandflash.h>
35−
36−#include "excite_iodev.h"
37−
38−#define RM9K_GE_UNIT 0
39−#define XICAP_UNIT 0
40−#define NAND_UNIT 0
41−
42−#define DLL_TIMEOUT 3 /* seconds */
43−
44−
45−#define RINIT(__start__, __end__, __name__, __parent__) { \
46− .name = __name__ "_0", \
47− .start = (__start__), \
48− .end = (__end__), \
49− .flags = 0, \
50− .parent = (__parent__) \
51−}
52−
53−#define RINIT_IRQ(__irq__, __name__) { \
54− .name = __name__ "_0", \
55− .start = (__irq__), \
56− .end = (__irq__), \
57− .flags = IORESOURCE_IRQ, \
58− .parent = NULL \
59−}
60−
61−
62−
63−enum {
64− slice_xicap,
65− slice_eth
66−};
67−
68−
69−
70−static struct resource
71− excite_ctr_resource __maybe_unused = {
72− .name = "GPI counters",
73− .start = 0,
74− .end = 5,
75− .flags = 0,
76− .parent = NULL,
77− .sibling = NULL,
78− .child = NULL
79− },
80− excite_gpislice_resource __maybe_unused = {
81− .name = "GPI slices",
82− .start = 0,
83− .end = 1,
84− .flags = 0,
85− .parent = NULL,
86− .sibling = NULL,
87− .child = NULL
88− },
89− excite_mdio_channel_resource __maybe_unused = {
90− .name = "MDIO channels",
91− .start = 0,
92− .end = 1,
93− .flags = 0,
94− .parent = NULL,
95− .sibling = NULL,
96− .child = NULL
97− },
98− excite_fifomem_resource __maybe_unused = {
99− .name = "FIFO memory",
100− .start = 0,
101− .end = 767,
102− .flags = 0,
103− .parent = NULL,
104− .sibling = NULL,
105− .child = NULL
106− },
107− excite_scram_resource __maybe_unused = {
108− .name = "Scratch RAM",
109− .start = EXCITE_PHYS_SCRAM,
110− .end = EXCITE_PHYS_SCRAM + EXCITE_SIZE_SCRAM - 1,
111− .flags = IORESOURCE_MEM,
112− .parent = NULL,
113− .sibling = NULL,
114− .child = NULL
115− },
116− excite_fpga_resource __maybe_unused = {
117− .name = "System FPGA",
118− .start = EXCITE_PHYS_FPGA,
119− .end = EXCITE_PHYS_FPGA + EXCITE_SIZE_FPGA - 1,
120− .flags = IORESOURCE_MEM,
121− .parent = NULL,
122− .sibling = NULL,
123− .child = NULL
124− },
125− excite_nand_resource __maybe_unused = {
126− .name = "NAND flash control",
127− .start = EXCITE_PHYS_NAND,
128− .end = EXCITE_PHYS_NAND + EXCITE_SIZE_NAND - 1,
129− .flags = IORESOURCE_MEM,
130− .parent = NULL,
131− .sibling = NULL,
132− .child = NULL
133− },
134− excite_titan_resource __maybe_unused = {
135− .name = "TITAN registers",
136− .start = EXCITE_PHYS_TITAN,
137− .end = EXCITE_PHYS_TITAN + EXCITE_SIZE_TITAN - 1,
138− .flags = IORESOURCE_MEM,
139− .parent = NULL,
140− .sibling = NULL,
141− .child = NULL
142− };
143−
144−
145−
146−static void adjust_resources(struct resource *res, unsigned int n)
147−{
148− struct resource *p;
149− const unsigned long mask = IORESOURCE_IO | IORESOURCE_MEM
150− | IORESOURCE_IRQ | IORESOURCE_DMA;
151−
152− for (p = res; p < res + n; p++) {
153− const struct resource * const parent = p->parent;
154− if (parent) {
155− p->start += parent->start;
156− p->end += parent->start;
157− p->flags = parent->flags & mask;
158− }
159− }
160−}
161−
162−
163−
164−#if defined(CONFIG_EXCITE_FCAP_GPI) || defined(CONFIG_EXCITE_FCAP_GPI_MODULE)
165−static struct resource xicap_rsrc[] = {
166− RINIT(0x4840, 0x486f, XICAP_RESOURCE_FIFO_RX, &excite_titan_resource),
167− RINIT(0x4940, 0x494b, XICAP_RESOURCE_FIFO_TX, &excite_titan_resource),
168− RINIT(0x5040, 0x5127, XICAP_RESOURCE_XDMA, &excite_titan_resource),
169− RINIT(0x1000, 0x112f, XICAP_RESOURCE_PKTPROC, &excite_titan_resource),
170− RINIT(0x1100, 0x110f, XICAP_RESOURCE_PKT_STREAM, &excite_fpga_resource),
171− RINIT(0x0800, 0x0bff, XICAP_RESOURCE_DMADESC, &excite_scram_resource),
172− RINIT(slice_xicap, slice_xicap, XICAP_RESOURCE_GPI_SLICE, &excite_gpislice_resource),
173− RINIT(0x0100, 0x02ff, XICAP_RESOURCE_FIFO_BLK, &excite_fifomem_resource),
174− RINIT_IRQ(TITAN_IRQ, XICAP_RESOURCE_IRQ)
175−};
176−
177−static struct platform_device xicap_pdev = {
178− .name = XICAP_NAME,
179− .id = XICAP_UNIT,
180− .num_resources = ARRAY_SIZE(xicap_rsrc),
181− .resource = xicap_rsrc
182−};
183−
184−/*
185− * Create a platform device for the GPI port that receives the
186− * image data from the embedded camera.
187− */
188−static int __init xicap_devinit(void)
189−{
190− unsigned long tend;
191− u32 reg;
192− int retval;
193−
194− adjust_resources(xicap_rsrc, ARRAY_SIZE(xicap_rsrc));
195−
196− /* Power up the slice and configure it. */
197− reg = titan_readl(CPTC1R);
198− reg &= ~(0x11100 << slice_xicap);
199− titan_writel(reg, CPTC1R);
200−
201− /* Enable slice & DLL. */
202− reg= titan_readl(CPRR);
203− reg &= ~(0x00030003 << (slice_xicap * 2));
204− titan_writel(reg, CPRR);
205−
206− /* Wait for DLLs to lock */
207− tend = jiffies + DLL_TIMEOUT * HZ;
208− while (time_before(jiffies, tend)) {
209− if (!(~titan_readl(CPDSR) & (0x1 << (slice_xicap * 4))))
210− break;
211− yield();
212− }
213−
214− if (~titan_readl(CPDSR) & (0x1 << (slice_xicap * 4))) {
215− printk(KERN_ERR "%s: DLL not locked after %u seconds\n",
216− xicap_pdev.name, DLL_TIMEOUT);
217− retval = -ETIME;
218− } else {
219− /* Register platform device */
220− retval = platform_device_register(&xicap_pdev);
221− }
222−
223− return retval;
224−}
225−
226−device_initcall(xicap_devinit);
227−#endif /* defined(CONFIG_EXCITE_FCAP_GPI) || defined(CONFIG_EXCITE_FCAP_GPI_MODULE) */
228−
229−
230−
231−#if defined(CONFIG_WDT_RM9K_GPI) || defined(CONFIG_WDT_RM9K_GPI_MODULE)
232−static struct resource wdt_rsrc[] = {
233− RINIT(0, 0, WDT_RESOURCE_COUNTER, &excite_ctr_resource),
234− RINIT(0x0084, 0x008f, WDT_RESOURCE_REGS, &excite_titan_resource),
235− RINIT_IRQ(TITAN_IRQ, WDT_RESOURCE_IRQ)
236−};
237−
238−static struct platform_device wdt_pdev = {
239− .name = WDT_NAME,
240− .id = -1,
241− .num_resources = ARRAY_SIZE(wdt_rsrc),
242− .resource = wdt_rsrc
243−};
244−
245−/*
246− * Create a platform device for the GPI port that receives the
247− * image data from the embedded camera.
248− */
249−static int __init wdt_devinit(void)
250−{
251− adjust_resources(wdt_rsrc, ARRAY_SIZE(wdt_rsrc));
252− return platform_device_register(&wdt_pdev);
253−}
254−
255−device_initcall(wdt_devinit);
256−#endif /* defined(CONFIG_WDT_RM9K_GPI) || defined(CONFIG_WDT_RM9K_GPI_MODULE) */
257−
258−
259−
260−static struct resource excite_nandflash_rsrc[] = {
261− RINIT(0x2000, 0x201f, EXCITE_NANDFLASH_RESOURCE_REGS, &excite_nand_resource)
262−};
263−
264−static struct platform_device excite_nandflash_pdev = {
265− .name = "excite_nand",
266− .id = NAND_UNIT,
267− .num_resources = ARRAY_SIZE(excite_nandflash_rsrc),
268− .resource = excite_nandflash_rsrc
269−};
270−
271−/*
272− * Create a platform device for the access to the nand-flash
273− * port
274− */
275−static int __init excite_nandflash_devinit(void)
276−{
277− adjust_resources(excite_nandflash_rsrc, ARRAY_SIZE(excite_nandflash_rsrc));
278−
279− /* nothing to be done here */
280−
281− /* Register platform device */
282− return platform_device_register(&excite_nandflash_pdev);
283−}
284−
285−device_initcall(excite_nandflash_devinit);
286−
287−
288−
289−static struct resource iodev_rsrc[] = {
290− RINIT_IRQ(FPGA1_IRQ, IODEV_RESOURCE_IRQ)
291−};
292−
293−static struct platform_device io_pdev = {
294− .name = IODEV_NAME,
295− .id = -1,
296− .num_resources = ARRAY_SIZE(iodev_rsrc),
297− .resource = iodev_rsrc
298−};
299−
300−/*
301− * Create a platform device for the external I/O ports.
302− */
303−static int __init io_devinit(void)
304−{
305− adjust_resources(iodev_rsrc, ARRAY_SIZE(iodev_rsrc));
306− return platform_device_register(&io_pdev);
307−}
308−
309−device_initcall(io_devinit);
310−
311−
312−
313−
314−#if defined(CONFIG_RM9K_GE) || defined(CONFIG_RM9K_GE_MODULE)
315−static struct resource rm9k_ge_rsrc[] = {
316− RINIT(0x2200, 0x27ff, RM9K_GE_RESOURCE_MAC, &excite_titan_resource),
317− RINIT(0x1800, 0x1fff, RM9K_GE_RESOURCE_MSTAT, &excite_titan_resource),
318− RINIT(0x2000, 0x212f, RM9K_GE_RESOURCE_PKTPROC, &excite_titan_resource),
319− RINIT(0x5140, 0x5227, RM9K_GE_RESOURCE_XDMA, &excite_titan_resource),
320− RINIT(0x4870, 0x489f, RM9K_GE_RESOURCE_FIFO_RX, &excite_titan_resource),
321− RINIT(0x494c, 0x4957, RM9K_GE_RESOURCE_FIFO_TX, &excite_titan_resource),
322− RINIT(0x0000, 0x007f, RM9K_GE_RESOURCE_FIFOMEM_RX, &excite_fifomem_resource),
323− RINIT(0x0080, 0x00ff, RM9K_GE_RESOURCE_FIFOMEM_TX, &excite_fifomem_resource),
324− RINIT(0x0180, 0x019f, RM9K_GE_RESOURCE_PHY, &excite_titan_resource),
325− RINIT(0x0000, 0x03ff, RM9K_GE_RESOURCE_DMADESC_RX, &excite_scram_resource),
326− RINIT(0x0400, 0x07ff, RM9K_GE_RESOURCE_DMADESC_TX, &excite_scram_resource),
327− RINIT(slice_eth, slice_eth, RM9K_GE_RESOURCE_GPI_SLICE, &excite_gpislice_resource),
328− RINIT(0, 0, RM9K_GE_RESOURCE_MDIO_CHANNEL, &excite_mdio_channel_resource),
329− RINIT_IRQ(TITAN_IRQ, RM9K_GE_RESOURCE_IRQ_MAIN),
330− RINIT_IRQ(PHY_IRQ, RM9K_GE_RESOURCE_IRQ_PHY)
331−};
332−
333−static struct platform_device rm9k_ge_pdev = {
334− .name = RM9K_GE_NAME,
335− .id = RM9K_GE_UNIT,
336− .num_resources = ARRAY_SIZE(rm9k_ge_rsrc),
337− .resource = rm9k_ge_rsrc
338−};
339−
340−
341−
342−/*
343− * Create a platform device for the Ethernet port.
344− */
345−static int __init rm9k_ge_devinit(void)
346−{
347− u32 reg;
348−
349− adjust_resources(rm9k_ge_rsrc, ARRAY_SIZE(rm9k_ge_rsrc));
350−
351− /* Power up the slice and configure it. */
352− reg = titan_readl(CPTC1R);
353− reg &= ~(0x11000 << slice_eth);
354− reg |= 0x100 << slice_eth;
355− titan_writel(reg, CPTC1R);
356−
357− /* Take the MAC out of reset, reset the DLLs. */
358− reg = titan_readl(CPRR);
359− reg &= ~(0x00030000 << (slice_eth * 2));
360− reg |= 0x3 << (slice_eth * 2);
361− titan_writel(reg, CPRR);
362−
363− return platform_device_register(&rm9k_ge_pdev);
364−}
365−
366−device_initcall(rm9k_ge_devinit);
367−#endif /* defined(CONFIG_RM9K_GE) || defined(CONFIG_RM9K_GE_MODULE) */
368−
369−
370−
371−static int __init excite_setup_devs(void)
372−{
373− int res;
374− u32 reg;
375−
376− /* Enable xdma and fifo interrupts */
377− reg = titan_readl(0x0050);
378− titan_writel(reg | 0x18000000, 0x0050);
379−
380− res = request_resource(&iomem_resource, &excite_titan_resource);
381− if (res)
382− return res;
383− res = request_resource(&iomem_resource, &excite_scram_resource);
384− if (res)
385− return res;
386− res = request_resource(&iomem_resource, &excite_fpga_resource);
387− if (res)
388− return res;
389− res = request_resource(&iomem_resource, &excite_nand_resource);
390− if (res)
391− return res;
392− excite_fpga_resource.flags = excite_fpga_resource.parent->flags &
393− ( IORESOURCE_IO | IORESOURCE_MEM
394− | IORESOURCE_IRQ | IORESOURCE_DMA);
395− excite_nand_resource.flags = excite_nand_resource.parent->flags &
396− ( IORESOURCE_IO | IORESOURCE_MEM
397− | IORESOURCE_IRQ | IORESOURCE_DMA);
398−
399− return 0;
400−}
401−
402−arch_initcall(excite_setup_devs);
403−
arch/mips/basler/excite/excite_iodev.c+0−178
@@ -1,178 +0,0 @@
1−/*
2− * Copyright (C) 2005 by Basler Vision Technologies AG
3− * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
4− *
5− * This program is free software; you can redistribute it and/or modify
6− * it under the terms of the GNU General Public License as published by
7− * the Free Software Foundation; either version 2 of the License, or
8− * (at your option) any later version.
9− *
10− * This program is distributed in the hope that it will be useful,
11− * but WITHOUT ANY WARRANTY; without even the implied warranty of
12− * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13− * GNU General Public License for more details.
14− *
15− * You should have received a copy of the GNU General Public License
16− * along with this program; if not, write to the Free Software
17− * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18− */
19−
20−#include <linux/compiler.h>
21−#include <linux/init.h>
22−#include <linux/module.h>
23−#include <linux/sched.h>
24−#include <linux/wait.h>
25−#include <linux/poll.h>
26−#include <linux/interrupt.h>
27−#include <linux/platform_device.h>
28−#include <linux/miscdevice.h>
29−#include <linux/smp_lock.h>
30−
31−#include "excite_iodev.h"
32−
33−
34−
35−static const struct resource *iodev_get_resource(struct platform_device *, const char *, unsigned int);
36−static int __init iodev_probe(struct platform_device *);
37−static int __exit iodev_remove(struct platform_device *);
38−static int iodev_open(struct inode *, struct file *);
39−static int iodev_release(struct inode *, struct file *);
40−static ssize_t iodev_read(struct file *, char __user *, size_t s, loff_t *);
41−static unsigned int iodev_poll(struct file *, struct poll_table_struct *);
42−static irqreturn_t iodev_irqhdl(int, void *);
43−
44−
45−
46−static const char iodev_name[] = "iodev";
47−static unsigned int iodev_irq;
48−static DECLARE_WAIT_QUEUE_HEAD(wq);
49−
50−
51−
52−static const struct file_operations fops =
53−{
54− .owner = THIS_MODULE,
55− .open = iodev_open,
56− .release = iodev_release,
57− .read = iodev_read,
58− .poll = iodev_poll
59−};
60−
61−static struct miscdevice miscdev =
62−{
63− .minor = MISC_DYNAMIC_MINOR,
64− .name = iodev_name,
65− .fops = &fops
66−};
67−
68−static struct platform_driver iodev_driver = {
69− .driver = {
70− .name = iodev_name,
71− .owner = THIS_MODULE,
72− },
73− .probe = iodev_probe,
74− .remove = __devexit_p(iodev_remove),
75−};
76−
77−
78−
79−static const struct resource *
80−iodev_get_resource(struct platform_device *pdv, const char *name,
81− unsigned int type)
82−{
83− char buf[80];
84− if (snprintf(buf, sizeof buf, "%s_0", name) >= sizeof buf)
85− return NULL;
86− return platform_get_resource_byname(pdv, type, buf);
87−}
88−
89−
90−
91−/* No hotplugging on the platform bus - use __init */
92−static int __init iodev_probe(struct platform_device *dev)
93−{
94− const struct resource * const ri =
95− iodev_get_resource(dev, IODEV_RESOURCE_IRQ, IORESOURCE_IRQ);
96−
97− if (unlikely(!ri))
98− return -ENXIO;
99−
100− iodev_irq = ri->start;
101− return misc_register(&miscdev);
102−}
103−
104−
105−
106−static int __exit iodev_remove(struct platform_device *dev)
107−{
108− return misc_deregister(&miscdev);
109−}
110−
111−static int iodev_open(struct inode *i, struct file *f)
112−{
113− int ret;
114−
115− ret = request_irq(iodev_irq, iodev_irqhdl, IRQF_DISABLED,
116− iodev_name, &miscdev);
117−
118− return ret;
119−}
120−
121−static int iodev_release(struct inode *i, struct file *f)
122−{
123− free_irq(iodev_irq, &miscdev);
124− return 0;
125−}
126−
127−
128−
129−
130−static ssize_t
131−iodev_read(struct file *f, char __user *d, size_t s, loff_t *o)
132−{
133− ssize_t ret;
134− DEFINE_WAIT(w);
135−
136− prepare_to_wait(&wq, &w, TASK_INTERRUPTIBLE);
137− if (!signal_pending(current))
138− schedule();
139− ret = signal_pending(current) ? -ERESTARTSYS : 0;
140− finish_wait(&wq, &w);
141− return ret;
142−}
143−
144−
145−static unsigned int iodev_poll(struct file *f, struct poll_table_struct *p)
146−{
147− poll_wait(f, &wq, p);
148− return POLLOUT | POLLWRNORM;
149−}
150−
151−static irqreturn_t iodev_irqhdl(int irq, void *ctxt)
152−{
153− wake_up(&wq);
154−
155− return IRQ_HANDLED;
156−}
157−
158−static int __init iodev_init_module(void)
159−{
160− return platform_driver_register(&iodev_driver);
161−}
162−
163−
164−
165−static void __exit iodev_cleanup_module(void)
166−{
167− platform_driver_unregister(&iodev_driver);
168−}
169−
170−module_init(iodev_init_module);
171−module_exit(iodev_cleanup_module);
172−
173−
174−
175−MODULE_AUTHOR("Thomas Koeller <thomas.koeller@baslerweb.com>");
176−MODULE_DESCRIPTION("Basler eXcite i/o interrupt handler");
177−MODULE_VERSION("0.0");
178−MODULE_LICENSE("GPL");
arch/mips/basler/excite/excite_iodev.h+0−10
@@ -1,10 +0,0 @@
1−#ifndef __EXCITE_IODEV_H__
2−#define __EXCITE_IODEV_H__
3−
4−/* Device name */
5−#define IODEV_NAME "iodev"
6−
7−/* Resource names */
8−#define IODEV_RESOURCE_IRQ "excite_iodev_irq"
9−
10−#endif /* __EXCITE_IODEV_H__ */
arch/mips/basler/excite/excite_irq.c+0−122
@@ -1,122 +0,0 @@
1−/*
2− * Copyright (C) by Basler Vision Technologies AG
3− * Author: Thomas Koeller <thomas.koeller@baslereb.com>
4− *
5− * This program is free software; you can redistribute it and/or modify
6− * it under the terms of the GNU General Public License as published by
7− * the Free Software Foundation; either version 2 of the License, or
8− * (at your option) any later version.
9− *
10− * This program is distributed in the hope that it will be useful,
11− * but WITHOUT ANY WARRANTY; without even the implied warranty of
12− * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13− * GNU General Public License for more details.
14− *
15− * You should have received a copy of the GNU General Public License
16− * along with this program; if not, write to the Free Software
17− * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18− */
19−
20−#include <linux/errno.h>
21−#include <linux/init.h>
22−#include <linux/kernel_stat.h>
23−#include <linux/module.h>
24−#include <linux/signal.h>
25−#include <linux/sched.h>
26−#include <linux/types.h>
27−#include <linux/interrupt.h>
28−#include <linux/ioport.h>
29−#include <linux/timex.h>
30−#include <linux/slab.h>
31−#include <linux/random.h>
32−#include <linux/bitops.h>
33−#include <asm/bootinfo.h>
34−#include <asm/io.h>
35−#include <asm/irq.h>
36−#include <asm/irq_cpu.h>
37−#include <asm/mipsregs.h>
38−#include <asm/system.h>
39−#include <asm/rm9k-ocd.h>
40−
41−#include <excite.h>
42−
43−extern asmlinkage void excite_handle_int(void);
44−
45−/*
46− * Initialize the interrupt handler
47− */
48−void __init arch_init_irq(void)
49−{
50− mips_cpu_irq_init();
51− rm7k_cpu_irq_init();
52− rm9k_cpu_irq_init();
53−}
54−
55−asmlinkage void plat_irq_dispatch(void)
56−{
57− const u32
58− interrupts = read_c0_cause() >> 8,
59− mask = ((read_c0_status() >> 8) & 0x000000ff) |
60− (read_c0_intcontrol() & 0x0000ff00),
61− pending = interrupts & mask;
62− u32 msgintflags, msgintmask, msgint;
63−
64− /* process timer interrupt */
65− if (pending & (1 << TIMER_IRQ)) {
66− do_IRQ(TIMER_IRQ);
67− return;
68− }
69−
70− /* Process PCI interrupts */
71−#if USB_IRQ < 10
72− msgintflags = ocd_readl(INTP0Status0 + (USB_MSGINT / 0x20 * 0x10));
73− msgintmask = ocd_readl(INTP0Mask0 + (USB_MSGINT / 0x20 * 0x10));
74− msgint = msgintflags & msgintmask & (0x1 << (USB_MSGINT % 0x20));
75− if ((pending & (1 << USB_IRQ)) && msgint) {
76−#else
77− if (pending & (1 << USB_IRQ)) {
78−#endif
79− do_IRQ(USB_IRQ);
80− return;
81− }
82−
83− /* Process TITAN interrupts */
84− msgintflags = ocd_readl(INTP0Status0 + (TITAN_MSGINT / 0x20 * 0x10));
85− msgintmask = ocd_readl(INTP0Mask0 + (TITAN_MSGINT / 0x20 * 0x10));
86− msgint = msgintflags & msgintmask & (0x1 << (TITAN_MSGINT % 0x20));
87− if ((pending & (1 << TITAN_IRQ)) && msgint) {
88− ocd_writel(msgint, INTP0Clear0 + (TITAN_MSGINT / 0x20 * 0x10));
89− do_IRQ(TITAN_IRQ);
90− return;
91− }
92−
93− /* Process FPGA line #0 interrupts */
94− msgintflags = ocd_readl(INTP0Status0 + (FPGA0_MSGINT / 0x20 * 0x10));
95− msgintmask = ocd_readl(INTP0Mask0 + (FPGA0_MSGINT / 0x20 * 0x10));
96− msgint = msgintflags & msgintmask & (0x1 << (FPGA0_MSGINT % 0x20));
97− if ((pending & (1 << FPGA0_IRQ)) && msgint) {
98− do_IRQ(FPGA0_IRQ);
99− return;
100− }
101−
102− /* Process FPGA line #1 interrupts */
103− msgintflags = ocd_readl(INTP0Status0 + (FPGA1_MSGINT / 0x20 * 0x10));
104− msgintmask = ocd_readl(INTP0Mask0 + (FPGA1_MSGINT / 0x20 * 0x10));
105− msgint = msgintflags & msgintmask & (0x1 << (FPGA1_MSGINT % 0x20));
106− if ((pending & (1 << FPGA1_IRQ)) && msgint) {
107− do_IRQ(FPGA1_IRQ);
108− return;
109− }
110−
111− /* Process PHY interrupts */
112− msgintflags = ocd_readl(INTP0Status0 + (PHY_MSGINT / 0x20 * 0x10));
113− msgintmask = ocd_readl(INTP0Mask0 + (PHY_MSGINT / 0x20 * 0x10));
114− msgint = msgintflags & msgintmask & (0x1 << (PHY_MSGINT % 0x20));
115− if ((pending & (1 << PHY_IRQ)) && msgint) {
116− do_IRQ(PHY_IRQ);
117− return;
118− }
119−
120− /* Process spurious interrupts */
121− spurious_interrupt();
122−}
arch/mips/basler/excite/excite_procfs.c+0−92
@@ -1,92 +0,0 @@
1−/*
2− * Copyright (C) 2004, 2005 by Basler Vision Technologies AG
3− * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
4− *
5− * Procfs support for Basler eXcite
6− *
7− * This program is free software; you can redistribute it and/or modify
8− * it under the terms of the GNU General Public License as published by
9− * the Free Software Foundation; either version 2 of the License, or
10− * (at your option) any later version.
11− *
12− * This program is distributed in the hope that it will be useful,
13− * but WITHOUT ANY WARRANTY; without even the implied warranty of
14− * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15− * GNU General Public License for more details.
16− *
17− * You should have received a copy of the GNU General Public License
18− * along with this program; if not, write to the Free Software
19− * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20− */
21−#include <linux/module.h>
22−#include <linux/proc_fs.h>
23−#include <linux/seq_file.h>
24−#include <linux/stat.h>
25−#include <asm/page.h>
26−#include <asm/io.h>
27−#include <asm/system.h>
28−#include <asm/rm9k-ocd.h>
29−
30−#include <excite.h>
31−
32−static int excite_unit_id_proc_show(struct seq_file *m, void *v)
33−{
34− seq_printf(m, "%06x", unit_id);
35− return 0;
36−}
37−
38−static int excite_unit_id_proc_open(struct inode *inode, struct file *file)
39−{
40− return single_open(file, excite_unit_id_proc_show, NULL);
41−}
42−
43−static const struct file_operations excite_unit_id_proc_fops = {
44− .owner = THIS_MODULE,
45− .open = excite_unit_id_proc_open,
46− .read = seq_read,
47− .llseek = seq_lseek,
48− .release = single_release,
49−};
50−
51−static int
52−excite_bootrom_read(char *page, char **start, off_t off, int count,
53− int *eof, void *data)
54−{
55− void __iomem * src;
56−
57− if (off >= EXCITE_SIZE_BOOTROM) {
58− *eof = 1;
59− return 0;
60− }
61−
62− if ((off + count) > EXCITE_SIZE_BOOTROM)
63− count = EXCITE_SIZE_BOOTROM - off;
64−
65− src = ioremap(EXCITE_PHYS_BOOTROM + off, count);
66− if (src) {
67− memcpy_fromio(page, src, count);
68− iounmap(src);
69− *start = page;
70− } else {
71− count = -ENOMEM;
72− }
73−
74− return count;
75−}
76−
77−void excite_procfs_init(void)
78−{
79− /* Create & populate /proc/excite */
80− struct proc_dir_entry * const pdir = proc_mkdir("excite", NULL);
81− if (pdir) {
82− struct proc_dir_entry * e;
83−
84− e = proc_create("unit_id", S_IRUGO, pdir,
85− &excite_unit_id_proc_fops);
86− if (e) e->size = 6;
87−
88− e = create_proc_read_entry("bootrom", S_IRUGO, pdir,
89− excite_bootrom_read, NULL);
90− if (e) e->size = EXCITE_SIZE_BOOTROM;
91− }
92−}
arch/mips/basler/excite/excite_prom.c+0−144
@@ -1,144 +0,0 @@
1−/*
2− * Copyright (C) 2004, 2005 by Thomas Koeller (thomas.koeller@baslerweb.com)
3− * Based on the PMC-Sierra Yosemite board support by Ralf Baechle and
4− * Manish Lachwani.
5− *
6− * This program is free software; you can redistribute it and/or modify
7− * it under the terms of the GNU General Public License as published by
8− * the Free Software Foundation; either version 2 of the License, or
9− * (at your option) any later version.
10− *
11− * This program is distributed in the hope that it will be useful,
12− * but WITHOUT ANY WARRANTY; without even the implied warranty of
13− * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14− * GNU General Public License for more details.
15− *
16− * You should have received a copy of the GNU General Public License
17− * along with this program; if not, write to the Free Software
18− * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19− */
20−
21−#include <linux/init.h>
22−#include <linux/sched.h>
23−#include <linux/mm.h>
24−#include <linux/delay.h>
25−#include <linux/smp.h>
26−#include <linux/module.h>
27−#include <asm/io.h>
28−#include <asm/pgtable.h>
29−#include <asm/processor.h>
30−#include <asm/reboot.h>
31−#include <asm/system.h>
32−#include <asm/bootinfo.h>
33−#include <asm/string.h>
34−
35−#include <excite.h>
36−
37−/* This struct is used by Redboot to pass arguments to the kernel */
38−typedef struct
39−{
40− char *name;
41− char *val;
42−} t_env_var;
43−
44−struct parmblock {
45− t_env_var memsize;
46− t_env_var modetty0;
47− t_env_var ethaddr;
48− t_env_var env_end;
49− char *argv[2];
50− char text[0];
51−};
52−
53−static unsigned int prom_argc;
54−static const char ** prom_argv;
55−static const t_env_var * prom_env;
56−
57−static void prom_halt(void) __attribute__((noreturn));
58−static void prom_exit(void) __attribute__((noreturn));
59−
60−
61−
62−const char *get_system_type(void)
63−{
64− return "Basler eXcite";
65−}
66−
67−/*
68− * Halt the system
69− */
70−static void prom_halt(void)
71−{
72− printk(KERN_NOTICE "\n** System halted.\n");
73− while (1)
74− asm volatile (
75− "\t.set\tmips3\n"
76− "\twait\n"
77− "\t.set\tmips0\n"
78− );
79−}
80−
81−/*
82− * Reset the CPU and re-enter Redboot
83− */
84−static void prom_exit(void)
85−{
86− unsigned int i;
87− volatile unsigned char * const flg =
88− (volatile unsigned char *) (EXCITE_ADDR_FPGA + EXCITE_FPGA_DPR);
89−
90− /* Clear the watchdog reset flag, set the reboot flag */
91− *flg &= ~0x01;
92− *flg |= 0x80;
93−
94− for (i = 0; i < 10; i++) {
95− *(volatile unsigned char *) (EXCITE_ADDR_FPGA + EXCITE_FPGA_SYSCTL) = 0x02;
96− iob();
97− mdelay(1000);
98− }
99−
100− printk(KERN_NOTICE "Reset failed\n");
101− prom_halt();
102−}
103−
104−static const char __init *prom_getenv(char *name)
105−{
106− const t_env_var * p;
107− for (p = prom_env; p->name != NULL; p++)
108− if(strcmp(name, p->name) == 0)
109− break;
110− return p->val;
111−}
112−
113−/*
114− * Init routine which accepts the variables from Redboot
115− */
116−void __init prom_init(void)
117−{
118− const struct parmblock * const pb = (struct parmblock *) fw_arg2;
119−
120− prom_argc = fw_arg0;
121− prom_argv = (const char **) fw_arg1;
122− prom_env = &pb->memsize;
123−
124− /* Callbacks for halt, restart */
125− _machine_restart = (void (*)(char *)) prom_exit;
126− _machine_halt = prom_halt;
127−
128−#ifdef CONFIG_32BIT
129− /* copy command line */
130− strcpy(arcs_cmdline, prom_argv[1]);
131− memsize = simple_strtol(prom_getenv("memsize"), NULL, 16);
132− strcpy(modetty, prom_getenv("modetty0"));
133−#endif /* CONFIG_32BIT */
134−
135−#ifdef CONFIG_64BIT
136−# error 64 bit support not implemented
137−#endif /* CONFIG_64BIT */
138−}
139−
140−/* This is called from free_initmem(), so we need to provide it */
141−void __init prom_free_prom_memory(void)
142−{
143− /* Nothing to do */
144−}
arch/mips/basler/excite/excite_setup.c+0−302
@@ -1,302 +0,0 @@
1−/*
2− * Copyright (C) 2004, 2005 by Basler Vision Technologies AG
3− * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
4− * Based on the PMC-Sierra Yosemite board support by Ralf Baechle and
5− * Manish Lachwani.
6− *
7− * This program is free software; you can redistribute it and/or modify
8− * it under the terms of the GNU General Public License as published by
9− * the Free Software Foundation; either version 2 of the License, or
10− * (at your option) any later version.
11− *
12− * This program is distributed in the hope that it will be useful,
13− * but WITHOUT ANY WARRANTY; without even the implied warranty of
14− * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15− * GNU General Public License for more details.
16− *
17− * You should have received a copy of the GNU General Public License
18− * along with this program; if not, write to the Free Software
19− * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20− */
21−
22−#include <linux/types.h>
23−#include <linux/kernel.h>
24−#include <linux/module.h>
25−#include <linux/string.h>
26−#include <linux/tty.h>
27−#include <linux/serial_core.h>
28−#include <linux/serial.h>
29−#include <linux/serial_8250.h>
30−#include <linux/ioport.h>
31−#include <linux/spinlock.h>
32−#include <asm/bootinfo.h>
33−#include <asm/mipsregs.h>
34−#include <asm/pgtable-32.h>
35−#include <asm/io.h>
36−#include <asm/time.h>
37−#include <asm/rm9k-ocd.h>
38−
39−#include <excite.h>
40−
41−#define TITAN_UART_CLK 25000000
42−
43−#if 1
44−/* normal serial port assignment */
45−#define REGBASE_SER0 0x0208
46−#define REGBASE_SER1 0x0238
47−#define MASK_SER0 0x1
48−#define MASK_SER1 0x2
49−#else
50−/* serial ports swapped */
51−#define REGBASE_SER0 0x0238
52−#define REGBASE_SER1 0x0208
53−#define MASK_SER0 0x2
54−#define MASK_SER1 0x1
55−#endif
56−
57−unsigned long memsize;
58−char modetty[30];
59−unsigned int titan_irq = TITAN_IRQ;
60−static void __iomem * ctl_regs;
61−u32 unit_id;
62−
63−volatile void __iomem * const ocd_base = (void *) (EXCITE_ADDR_OCD);
64−volatile void __iomem * const titan_base = (void *) (EXCITE_ADDR_TITAN);
65−
66−/* Protect access to shared GPI registers */
67−DEFINE_SPINLOCK(titan_lock);
68−int titan_irqflags;
69−
70−
71−/*
72− * The eXcite platform uses the alternate timer interrupt
73− *
74− * Fixme: At the time of this writing cevt-r4k.c doesn't yet know about how
75− * to handle the alternate timer interrupt of the RM9000.
76− */
77−void __init plat_time_init(void)
78−{
79− const u32 modebit5 = ocd_readl(0x00e4);
80− unsigned int mult = ((modebit5 >> 11) & 0x1f) + 2;
81− unsigned int div = ((modebit5 >> 16) & 0x1f) + 2;
82−
83− if (div == 33)
84− div = 1;
85− mips_hpt_frequency = EXCITE_CPU_EXT_CLOCK * mult / div / 2;
86−}
87−
88−static int __init excite_init_console(void)
89−{
90−#if defined(CONFIG_SERIAL_8250)
91− static __initdata char serr[] =
92− KERN_ERR "Serial port #%u setup failed\n";
93− struct uart_port up;
94−
95− /* Take the DUART out of reset */
96− titan_writel(0x00ff1cff, CPRR);
97−
98−#if (CONFIG_SERIAL_8250_NR_UARTS > 1)
99− /* Enable both ports */
100− titan_writel(MASK_SER0 | MASK_SER1, UACFG);
101−#else
102− /* Enable port #0 only */
103− titan_writel(MASK_SER0, UACFG);
104−#endif
105−
106− /*
107− * Set up serial port #0. Do not use autodetection; the result is
108− * not what we want.
109− */
110− memset(&up, 0, sizeof(up));
111− up.membase = (char *) titan_addr(REGBASE_SER0);
112− up.irq = TITAN_IRQ;
113− up.uartclk = TITAN_UART_CLK;
114− up.regshift = 0;
115− up.iotype = UPIO_RM9000;
116− up.type = PORT_RM9000;
117− up.flags = UPF_SHARE_IRQ;
118− up.line = 0;
119− if (early_serial_setup(&up))
120− printk(serr, up.line);
121−
122−#if CONFIG_SERIAL_8250_NR_UARTS > 1
123− /* And now for port #1. */
124− up.membase = (char *) titan_addr(REGBASE_SER1);
125− up.line = 1;
126− if (early_serial_setup(&up))
127− printk(serr, up.line);
128−#endif /* CONFIG_SERIAL_8250_NR_UARTS > 1 */
129−#else
130− /* Leave the DUART in reset */
131− titan_writel(0x00ff3cff, CPRR);
132−#endif /* defined(CONFIG_SERIAL_8250) */
133−
134− return 0;
135−}
136−
137−static int __init excite_platform_init(void)
138−{
139− unsigned int i;
140− unsigned char buf[3];
141− u8 reg;
142− void __iomem * dpr;
143−
144− /* BIU buffer allocations */
145− ocd_writel(8, CPURSLMT); /* CPU */
146− titan_writel(4, CPGRWL); /* GPI / Ethernet */
147−
148− /* Map control registers located in FPGA */
149− ctl_regs = ioremap_nocache(EXCITE_PHYS_FPGA + EXCITE_FPGA_SYSCTL, 16);
150− if (!ctl_regs)
151− panic("eXcite: failed to map platform control registers\n");
152− memcpy_fromio(buf, ctl_regs + 2, ARRAY_SIZE(buf));
153− unit_id = buf[0] | (buf[1] << 8) | (buf[2] << 16);
154−
155− /* Clear the reboot flag */
156− dpr = ioremap_nocache(EXCITE_PHYS_FPGA + EXCITE_FPGA_DPR, 1);
157− reg = __raw_readb(dpr);
158− __raw_writeb(reg & 0x7f, dpr);
159− iounmap(dpr);
160−
161− /* Interrupt controller setup */
162− for (i = INTP0Status0; i < INTP0Status0 + 0x80; i += 0x10) {
163− ocd_writel(0x00000000, i + 0x04);
164− ocd_writel(0xffffffff, i + 0x0c);
165− }
166− ocd_writel(0x2, NMICONFIG);
167−
168− ocd_writel(0x1 << (TITAN_MSGINT % 0x20),
169− INTP0Mask0 + (0x10 * (TITAN_MSGINT / 0x20)));
170− ocd_writel((0x1 << (FPGA0_MSGINT % 0x20))
171− | ocd_readl(INTP0Mask0 + (0x10 * (FPGA0_MSGINT / 0x20))),
172− INTP0Mask0 + (0x10 * (FPGA0_MSGINT / 0x20)));
173− ocd_writel((0x1 << (FPGA1_MSGINT % 0x20))
174− | ocd_readl(INTP0Mask0 + (0x10 * (FPGA1_MSGINT / 0x20))),
175− INTP0Mask0 + (0x10 * (FPGA1_MSGINT / 0x20)));
176− ocd_writel((0x1 << (PHY_MSGINT % 0x20))
177− | ocd_readl(INTP0Mask0 + (0x10 * (PHY_MSGINT / 0x20))),
178− INTP0Mask0 + (0x10 * (PHY_MSGINT / 0x20)));
179−#if USB_IRQ < 10
180− ocd_writel((0x1 << (USB_MSGINT % 0x20))
181− | ocd_readl(INTP0Mask0 + (0x10 * (USB_MSGINT / 0x20))),
182− INTP0Mask0 + (0x10 * (USB_MSGINT / 0x20)));
183−#endif
184− /* Enable the packet FIFO, XDMA and XDMA arbiter */
185− titan_writel(0x00ff18ff, CPRR);
186−
187− /*
188− * Set up the PADMUX. Power down all ethernet slices,
189− * they will be powered up and configured at device startup.
190− */
191− titan_writel(0x00878206, CPTC1R);
192− titan_writel(0x00001100, CPTC0R); /* latch PADMUX, enable WCIMODE */
193−
194− /* Reset and enable the FIFO block */
195− titan_writel(0x00000001, SDRXFCIE);
196− titan_writel(0x00000001, SDTXFCIE);
197− titan_writel(0x00000100, SDRXFCIE);
198− titan_writel(0x00000000, SDTXFCIE);
199−
200− /*
201− * Initialize the common interrupt shared by all components of
202− * the GPI/Ethernet subsystem.
203− */
204− titan_writel((EXCITE_PHYS_OCD >> 12), CPCFG0);
205− titan_writel(TITAN_MSGINT, CPCFG1);
206−
207− /*
208− * XDMA configuration.
209− * In order for the XDMA to be sharable among multiple drivers,
210− * the setup must be done here in the platform. The reason is that
211− * this setup can only be done while the XDMA is in reset. If this
212− * were done in a driver, it would interrupt all other drivers
213− * using the XDMA.
214− */
215− titan_writel(0x80021dff, GXCFG); /* XDMA reset */
216− titan_writel(0x00000000, CPXCISRA);
217− titan_writel(0x00000000, CPXCISRB); /* clear pending interrupts */
218−#if defined(CONFIG_HIGHMEM)
219−# error change for HIGHMEM support!
220−#else
221− titan_writel(0x00000000, GXDMADRPFX); /* buffer address prefix */
222−#endif
223− titan_writel(0, GXDMA_DESCADR);
224−
225− for (i = 0x5040; i <= 0x5300; i += 0x0040)
226− titan_writel(0x80080000, i); /* reset channel */
227−
228− titan_writel((0x1 << 29) /* no sparse tx descr. */
229− | (0x1 << 28) /* no sparse rx descr. */
230− | (0x1 << 23) | (0x1 << 24) /* descriptor coherency */
231− | (0x1 << 21) | (0x1 << 22) /* data coherency */
232− | (0x1 << 17)
233− | 0x1dff,
234− GXCFG);
235−
236−#if defined(CONFIG_SMP)
237−# error No SMP support
238−#else
239− /* All interrupts go to core #0 only. */
240− titan_writel(0x1f007fff, CPDST0A);
241− titan_writel(0x00000000, CPDST0B);
242− titan_writel(0x0000ff3f, CPDST1A);
243− titan_writel(0x00000000, CPDST1B);
244− titan_writel(0x00ffffff, CPXDSTA);
245− titan_writel(0x00000000, CPXDSTB);
246−#endif
247−
248− /* Enable DUART interrupts, disable everything else. */
249− titan_writel(0x04000000, CPGIG0ER);
250− titan_writel(0x000000c0, CPGIG1ER);
251−
252− excite_procfs_init();
253− return 0;
254−}
255−
256−void __init plat_mem_setup(void)
257−{
258− volatile u32 * const boot_ocd_base = (u32 *) 0xbf7fc000;
259−
260− /* Announce RAM to system */
261− add_memory_region(0x00000000, memsize, BOOT_MEM_RAM);
262−
263− /* Set up the peripheral address map */
264− *(boot_ocd_base + (LKB9 / sizeof(u32))) = 0;
265− *(boot_ocd_base + (LKB10 / sizeof(u32))) = 0;
266− *(boot_ocd_base + (LKB11 / sizeof(u32))) = 0;
267− *(boot_ocd_base + (LKB12 / sizeof(u32))) = 0;
268− wmb();
269− *(boot_ocd_base + (LKB0 / sizeof(u32))) = EXCITE_PHYS_OCD >> 4;
270− wmb();
271−
272− ocd_writel((EXCITE_PHYS_TITAN >> 4) | 0x1UL, LKB5);
273− ocd_writel(((EXCITE_SIZE_TITAN >> 4) & 0x7fffff00) - 0x100, LKM5);
274− ocd_writel((EXCITE_PHYS_SCRAM >> 4) | 0x1UL, LKB13);
275− ocd_writel(((EXCITE_SIZE_SCRAM >> 4) & 0xffffff00) - 0x100, LKM13);
276−
277− /* Local bus slot #0 */
278− ocd_writel(0x00040510, LDP0);
279− ocd_writel((EXCITE_PHYS_BOOTROM >> 4) | 0x1UL, LKB9);
280− ocd_writel(((EXCITE_SIZE_BOOTROM >> 4) & 0x03ffff00) - 0x100, LKM9);
281−
282− /* Local bus slot #2 */
283− ocd_writel(0x00000330, LDP2);
284− ocd_writel((EXCITE_PHYS_FPGA >> 4) | 0x1, LKB11);
285− ocd_writel(((EXCITE_SIZE_FPGA >> 4) - 0x100) & 0x03ffff00, LKM11);
286−
287− /* Local bus slot #3 */
288− ocd_writel(0x00123413, LDP3);
289− ocd_writel((EXCITE_PHYS_NAND >> 4) | 0x1, LKB12);
290− ocd_writel(((EXCITE_SIZE_NAND >> 4) - 0x100) & 0x03ffff00, LKM12);
291−}
292−
293−
294−
295−console_initcall(excite_init_console);
296−arch_initcall(excite_platform_init);
297−
298−EXPORT_SYMBOL(titan_lock);
299−EXPORT_SYMBOL(titan_irqflags);
300−EXPORT_SYMBOL(titan_irq);
301−EXPORT_SYMBOL(ocd_base);
302−EXPORT_SYMBOL(titan_base);
arch/mips/bcm47xx/prom.c+5−5
@@ -100,11 +100,11 @@ static __init void prom_init_console(void) · 99 unmodified lines
100100
101101 static __init void prom_init_cmdline(void)
102102 {
103− static char buf[CL_SIZE] __initdata;
103+ static char buf[COMMAND_LINE_SIZE] __initdata;
104104
105105 /* Get the kernel command line from CFE */
106− if (cfe_getenv("LINUX_CMDLINE", buf, CL_SIZE) >= 0) {
107− buf[CL_SIZE-1] = 0;
106+ if (cfe_getenv("LINUX_CMDLINE", buf, COMMAND_LINE_SIZE) >= 0) {
107+ buf[COMMAND_LINE_SIZE - 1] = 0;
108108 strcpy(arcs_cmdline, buf);
109109 }
110110
@@ -112,13 +112,13 @@ static __init void prom_init_cmdline(void) · 1 unmodified line
112112 * as CFE is not available anymore later in the boot process. */
113113 if ((strstr(arcs_cmdline, "console=")) == NULL) {
114114 /* Try to read the default serial port used by CFE */
115− if ((cfe_getenv("BOOT_CONSOLE", buf, CL_SIZE) < 0)
115+ if ((cfe_getenv("BOOT_CONSOLE", buf, COMMAND_LINE_SIZE) < 0)
116116 || (strncmp("uart", buf, 4)))
117117 /* Default to uart0 */
118118 strcpy(buf, "uart0");
119119
120120 /* Compute the new command line */
121− snprintf(arcs_cmdline, CL_SIZE, "%s console=ttyS%c,115200",
121+ snprintf(arcs_cmdline, COMMAND_LINE_SIZE, "%s console=ttyS%c,115200",
122122 arcs_cmdline, buf[4]);
123123 }
124124 }
arch/mips/boot/Makefile+2−6
@@ -25,7 +25,7 @@ strip-flags = $(addprefix --remove-section=,$(drop-sections)) · 24 unmodified lines
2525
2626 VMLINUX = vmlinux
2727
28−all: vmlinux.ecoff vmlinux.srec addinitrd
28+all: vmlinux.ecoff vmlinux.srec
2929
3030 vmlinux.ecoff: $(obj)/elf2ecoff $(VMLINUX)
3131 $(obj)/elf2ecoff $(VMLINUX) vmlinux.ecoff $(E2EFLAGS)
@@ -39,11 +39,7 @@ vmlinux.bin: $(VMLINUX) · 7 unmodified lines
3939 vmlinux.srec: $(VMLINUX)
4040 $(OBJCOPY) -S -O srec $(strip-flags) $(VMLINUX) $(obj)/vmlinux.srec
4141
42−$(obj)/addinitrd: $(obj)/addinitrd.c
43− $(HOSTCC) -o $@ $^
44−
45−clean-files += addinitrd \
46− elf2ecoff \
42+clean-files += elf2ecoff \
4743 vmlinux.bin \
4844 vmlinux.ecoff \
4945 vmlinux.srec
arch/mips/boot/addinitrd.c+0−131
@@ -1,131 +0,0 @@
1−/*
2− * addinitrd - program to add a initrd image to an ecoff kernel
3− *
4− * (C) 1999 Thomas Bogendoerfer
5− * minor modifications, cleanup: Guido Guenther <agx@sigxcpu.org>
6− * further cleanup: Maciej W. Rozycki
7− */
8−
9−#include <sys/types.h>
10−#include <sys/stat.h>
11−#include <fcntl.h>
12−#include <unistd.h>
13−#include <stdio.h>
14−#include <netinet/in.h>
15−
16−#include "ecoff.h"
17−
18−#define MIPS_PAGE_SIZE 4096
19−#define MIPS_PAGE_MASK (MIPS_PAGE_SIZE-1)
20−
21−#define swab16(x) \
22− ((unsigned short)( \
23− (((unsigned short)(x) & (unsigned short)0x00ffU) << 8) | \
24− (((unsigned short)(x) & (unsigned short)0xff00U) >> 8) ))
25−
26−#define swab32(x) \
27− ((unsigned int)( \
28− (((unsigned int)(x) & (unsigned int)0x000000ffUL) << 24) | \
29− (((unsigned int)(x) & (unsigned int)0x0000ff00UL) << 8) | \
30− (((unsigned int)(x) & (unsigned int)0x00ff0000UL) >> 8) | \
31− (((unsigned int)(x) & (unsigned int)0xff000000UL) >> 24) ))
32−
33−#define SWAB(a) (swab ? swab32(a) : (a))
34−
35−void die(char *s)
36−{
37− perror(s);
38− exit(1);
39−}
40−
41−int main(int argc, char *argv[])
42−{
43− int fd_vmlinux, fd_initrd, fd_outfile;
44− FILHDR efile;
45− AOUTHDR eaout;
46− SCNHDR esecs[3];
47− struct stat st;
48− char buf[1024];
49− unsigned long loadaddr;
50− unsigned long initrd_header[2];
51− int i, cnt;
52− int swab = 0;
53−
54− if (argc != 4) {
55− printf("Usage: %s <vmlinux> <initrd> <outfile>\n", argv[0]);
56− exit(1);
57− }
58−
59− if ((fd_vmlinux = open (argv[1], O_RDONLY)) < 0)
60− die("open vmlinux");
61− if (read (fd_vmlinux, &efile, sizeof efile) != sizeof efile)
62− die("read file header");
63− if (read (fd_vmlinux, &eaout, sizeof eaout) != sizeof eaout)
64− die("read aout header");
65− if (read (fd_vmlinux, esecs, sizeof esecs) != sizeof esecs)
66− die("read section headers");
67− /*
68− * check whether the file is good for us
69− */
70− /* TBD */
71−
72− /*
73− * check, if we have to swab words
74− */
75− if (ntohs(0xaa55) == 0xaa55) {
76− if (efile.f_magic == swab16(MIPSELMAGIC))
77− swab = 1;
78− } else {
79− if (efile.f_magic == swab16(MIPSEBMAGIC))
80− swab = 1;
81− }
82−
83− /* make sure we have an empty data segment for the initrd */
84− if (eaout.dsize || esecs[1].s_size) {
85− fprintf(stderr, "Data segment not empty. Giving up!\n");
86− exit(1);
87− }
88− if ((fd_initrd = open (argv[2], O_RDONLY)) < 0)
89− die("open initrd");
90− if (fstat (fd_initrd, &st) < 0)
91− die("fstat initrd");
92− loadaddr = ((SWAB(esecs[2].s_vaddr) + SWAB(esecs[2].s_size)
93− + MIPS_PAGE_SIZE-1) & ~MIPS_PAGE_MASK) - 8;
94− if (loadaddr < (SWAB(esecs[2].s_vaddr) + SWAB(esecs[2].s_size)))
95− loadaddr += MIPS_PAGE_SIZE;
96− initrd_header[0] = SWAB(0x494E5244);
97− initrd_header[1] = SWAB(st.st_size);
98− eaout.dsize = esecs[1].s_size = initrd_header[1] = SWAB(st.st_size+8);
99− eaout.data_start = esecs[1].s_vaddr = esecs[1].s_paddr = SWAB(loadaddr);
100−
101− if ((fd_outfile = open (argv[3], O_RDWR|O_CREAT|O_TRUNC, 0666)) < 0)
102− die("open outfile");
103− if (write (fd_outfile, &efile, sizeof efile) != sizeof efile)
104− die("write file header");
105− if (write (fd_outfile, &eaout, sizeof eaout) != sizeof eaout)
106− die("write aout header");
107− if (write (fd_outfile, esecs, sizeof esecs) != sizeof esecs)
108− die("write section headers");
109− /* skip padding */
110− if(lseek(fd_vmlinux, SWAB(esecs[0].s_scnptr), SEEK_SET) == (off_t)-1)
111− die("lseek vmlinux");
112− if(lseek(fd_outfile, SWAB(esecs[0].s_scnptr), SEEK_SET) == (off_t)-1)
113− die("lseek outfile");
114− /* copy text segment */
115− cnt = SWAB(eaout.tsize);
116− while (cnt) {
117− if ((i = read (fd_vmlinux, buf, sizeof buf)) <= 0)
118− die("read vmlinux");
119− if (write (fd_outfile, buf, i) != i)
120− die("write vmlinux");
121− cnt -= i;
122− }
123− if (write (fd_outfile, initrd_header, sizeof initrd_header) != sizeof initrd_header)
124− die("write initrd header");
125− while ((i = read (fd_initrd, buf, sizeof buf)) > 0)
126− if (write (fd_outfile, buf, i) != i)
127− die("write initrd");
128− close(fd_vmlinux);
129− close(fd_initrd);
130− return 0;
131−}
arch/mips/boot/compressed/Makefile+100−0
@@ -0,0 +1,100 @@
1+#
2+# This file is subject to the terms and conditions of the GNU General Public
3+# License.
4+#
5+# Adapted for MIPS Pete Popov, Dan Malek
6+#
7+# Copyright (C) 1994 by Linus Torvalds
8+# Adapted for PowerPC by Gary Thomas
9+# modified by Cort (cort@cs.nmt.edu)
10+#
11+# Copyright (C) 2009 Lemote Inc. & DSLab, Lanzhou University
12+# Author: Wu Zhangjin <wuzj@lemote.com>
13+#
14+
15+# compressed kernel load addr: VMLINUZ_LOAD_ADDRESS > VMLINUX_LOAD_ADDRESS + VMLINUX_SIZE
16+VMLINUX_SIZE := $(shell wc -c $(objtree)/$(KBUILD_IMAGE) 2>/dev/null | cut -d' ' -f1)
17+VMLINUX_SIZE := $(shell [ -n "$(VMLINUX_SIZE)" ] && echo $$(($(VMLINUX_SIZE) + (65536 - $(VMLINUX_SIZE) % 65536))))
18+VMLINUZ_LOAD_ADDRESS := 0x$(shell [ -n "$(VMLINUX_SIZE)" ] && printf %x $$(($(VMLINUX_LOAD_ADDRESS) + $(VMLINUX_SIZE))))
19+
20+# set the default size of the mallocing area for decompressing
21+BOOT_HEAP_SIZE := 0x400000
22+
23+# Disable Function Tracer
24+KBUILD_CFLAGS := $(shell echo $(KBUILD_CFLAGS) | sed -e "s/-pg//")
25+
26+KBUILD_CFLAGS := $(LINUXINCLUDE) $(KBUILD_CFLAGS) -D__KERNEL__ \
27+ -DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) -D"VMLINUX_LOAD_ADDRESS_ULL=$(VMLINUX_LOAD_ADDRESS)ull" \
28+
29+KBUILD_AFLAGS := $(LINUXINCLUDE) $(KBUILD_AFLAGS) -D__ASSEMBLY__ \
30+ -DKERNEL_ENTRY=0x$(shell $(NM) $(objtree)/$(KBUILD_IMAGE) 2>/dev/null | grep " kernel_entry" | cut -f1 -d \ ) \
31+ -DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE)
32+
33+obj-y := $(obj)/head.o $(obj)/decompress.o $(obj)/dbg.o
34+
35+obj-$(CONFIG_SYS_SUPPORTS_ZBOOT_UART16550) += $(obj)/uart-16550.o
36+
37+OBJCOPYFLAGS_vmlinux.bin := $(OBJCOPYFLAGS) -O binary -R .comment -S
38+$(obj)/vmlinux.bin: $(KBUILD_IMAGE)
39+ $(call if_changed,objcopy)
40+
41+suffix_$(CONFIG_KERNEL_GZIP) = gz
42+suffix_$(CONFIG_KERNEL_BZIP2) = bz2
43+suffix_$(CONFIG_KERNEL_LZMA) = lzma
44+tool_$(CONFIG_KERNEL_GZIP) = gzip
45+tool_$(CONFIG_KERNEL_BZIP2) = bzip2
46+tool_$(CONFIG_KERNEL_LZMA) = lzma
47+$(obj)/vmlinux.$(suffix_y): $(obj)/vmlinux.bin
48+ $(call if_changed,$(tool_y))
49+
50+$(obj)/piggy.o: $(obj)/vmlinux.$(suffix_y) $(obj)/dummy.o
51+ $(Q)$(OBJCOPY) $(OBJCOPYFLAGS) \
52+ --add-section=.image=$< \
53+ --set-section-flags=.image=contents,alloc,load,readonly,data \
54+ $(obj)/dummy.o $@
55+
56+LDFLAGS_vmlinuz := $(LDFLAGS) -Ttext $(VMLINUZ_LOAD_ADDRESS) -T
57+vmlinuz: $(src)/ld.script $(obj-y) $(obj)/piggy.o
58+ $(call if_changed,ld)
59+ $(Q)$(OBJCOPY) $(OBJCOPYFLAGS) -R .comment -R .stab -R .stabstr -R .initrd -R .sysmap $@
60+
61+#
62+# Some DECstations need all possible sections of an ECOFF executable
63+#
64+ifdef CONFIG_MACH_DECSTATION
65+ E2EFLAGS = -a
66+else
67+ E2EFLAGS =
68+endif
69+
70+# elf2ecoff can only handle 32bit image
71+
72+ifdef CONFIG_32BIT
73+ VMLINUZ = vmlinuz
74+else
75+ VMLINUZ = vmlinuz.32
76+endif
77+
78+vmlinuz.32: vmlinuz
79+ $(Q)$(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@
80+
81+vmlinuz.ecoff: $(obj)/../elf2ecoff $(VMLINUZ)
82+ $(Q)$(obj)/../elf2ecoff $(VMLINUZ) vmlinuz.ecoff $(E2EFLAGS)
83+
84+$(obj)/../elf2ecoff: $(src)/../elf2ecoff.c
85+ $(Q)$(HOSTCC) -o $@ $^
86+
87+drop-sections = .reginfo .mdebug .comment .note .pdr .options .MIPS.options
88+strip-flags = $(addprefix --remove-section=,$(drop-sections))
89+
90+OBJCOPYFLAGS_vmlinuz.bin := $(OBJCOPYFLAGS) -O binary $(strip-flags)
91+vmlinuz.bin: vmlinuz
92+ $(call if_changed,objcopy)
93+
94+OBJCOPYFLAGS_vmlinuz.srec := $(OBJCOPYFLAGS) -S -O srec $(strip-flags)
95+vmlinuz.srec: vmlinuz
96+ $(call if_changed,objcopy)
97+
98+clean:
99+clean-files += *.o \
100+ vmlinu*
arch/mips/boot/compressed/dbg.c+37−0
@@ -0,0 +1,37 @@
1+/*
2+ * MIPS-specific debug support for pre-boot environment
3+ *
4+ * NOTE: putc() is board specific, if your board have a 16550 compatible uart,
5+ * please select SYS_SUPPORTS_ZBOOT_UART16550 for your machine. othewise, you
6+ * need to implement your own putc().
7+ */
8+
9+#include <linux/init.h>
10+#include <linux/types.h>
11+
12+void __attribute__ ((weak)) putc(char c)
13+{
14+}
15+
16+void puts(const char *s)
17+{
18+ char c;
19+ while ((c = *s++) != '\0') {
20+ putc(c);
21+ if (c == '\n')
22+ putc('\r');
23+ }
24+}
25+
26+void puthex(unsigned long long val)
27+{
28+
29+ unsigned char buf[10];
30+ int i;
31+ for (i = 7; i >= 0; i--) {
32+ buf[i] = "0123456789ABCDEF"[val & 0x0F];
33+ val >>= 4;
34+ }
35+ buf[8] = '\0';
36+ puts(buf);
37+}
arch/mips/boot/compressed/decompress.c+126−0
@@ -0,0 +1,126 @@
1+/*
2+ * Misc. bootloader code for many machines.
3+ *
4+ * Copyright 2001 MontaVista Software Inc.
5+ * Author: Matt Porter <mporter@mvista.com> Derived from
6+ * arch/ppc/boot/prep/misc.c
7+ *
8+ * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology
9+ * Author: Wu Zhangjin <wuzj@lemote.com>
10+ *
11+ * This program is free software; you can redistribute it and/or modify it
12+ * under the terms of the GNU General Public License as published by the
13+ * Free Software Foundation; either version 2 of the License, or (at your
14+ * option) any later version.
15+ */
16+
17+#include <linux/types.h>
18+#include <linux/kernel.h>
19+
20+#include <asm/addrspace.h>
21+
22+/* These two variables specify the free mem region
23+ * that can be used for temporary malloc area
24+ */
25+unsigned long free_mem_ptr;
26+unsigned long free_mem_end_ptr;
27+char *zimage_start;
28+
29+/* The linker tells us where the image is. */
30+extern unsigned char __image_begin, __image_end;
31+extern unsigned char __ramdisk_begin, __ramdisk_end;
32+unsigned long initrd_size;
33+
34+/* debug interfaces */
35+extern void puts(const char *s);
36+extern void puthex(unsigned long long val);
37+
38+void error(char *x)
39+{
40+ puts("\n\n");
41+ puts(x);
42+ puts("\n\n -- System halted");
43+
44+ while (1)
45+ ; /* Halt */
46+}
47+
48+/* activate the code for pre-boot environment */
49+#define STATIC static
50+
51+#ifdef CONFIG_KERNEL_GZIP
52+void *memcpy(void *dest, const void *src, size_t n)
53+{
54+ int i;
55+ const char *s = src;
56+ char *d = dest;
57+
58+ for (i = 0; i < n; i++)
59+ d[i] = s[i];
60+ return dest;
61+}
62+#include "../../../../lib/decompress_inflate.c"
63+#endif
64+
65+#ifdef CONFIG_KERNEL_BZIP2
66+void *memset(void *s, int c, size_t n)
67+{
68+ int i;
69+ char *ss = s;
70+
71+ for (i = 0; i < n; i++)
72+ ss[i] = c;
73+ return s;
74+}
75+#include "../../../../lib/decompress_bunzip2.c"
76+#endif
77+
78+#ifdef CONFIG_KERNEL_LZMA
79+#include "../../../../lib/decompress_unlzma.c"
80+#endif
81+
82+void decompress_kernel(unsigned long boot_heap_start)
83+{
84+ int zimage_size;
85+
86+ /*
87+ * We link ourself to an arbitrary low address. When we run, we
88+ * relocate outself to that address. __image_beign points to
89+ * the part of the image where the zImage is. -- Tom
90+ */
91+ zimage_start = (char *)(unsigned long)(&__image_begin);
92+ zimage_size = (unsigned long)(&__image_end) -
93+ (unsigned long)(&__image_begin);
94+
95+ /*
96+ * The zImage and initrd will be between start and _end, so they've
97+ * already been moved once. We're good to go now. -- Tom
98+ */
99+ puts("zimage at: ");
100+ puthex((unsigned long)zimage_start);
101+ puts(" ");
102+ puthex((unsigned long)(zimage_size + zimage_start));
103+ puts("\n");
104+
105+ if (initrd_size) {
106+ puts("initrd at: ");
107+ puthex((unsigned long)(&__ramdisk_begin));
108+ puts(" ");
109+ puthex((unsigned long)(&__ramdisk_end));
110+ puts("\n");
111+ }
112+
113+ /* this area are prepared for mallocing when decompressing */
114+ free_mem_ptr = boot_heap_start;
115+ free_mem_end_ptr = boot_heap_start + BOOT_HEAP_SIZE;
116+
117+ /* Display standard Linux/MIPS boot prompt for kernel args */
118+ puts("Uncompressing Linux at load address ");
119+ puthex(VMLINUX_LOAD_ADDRESS_ULL);
120+ puts("\n");
121+ /* Decompress the kernel with according algorithm */
122+ decompress(zimage_start, zimage_size, 0, 0,
123+ (void *)VMLINUX_LOAD_ADDRESS_ULL, 0, error);
124+ /* FIXME: is there a need to flush cache here? */
125+ puts("Now, booting the kernel...\n");
126+}
arch/mips/boot/compressed/dummy.c+4−0
@@ -0,0 +1,4 @@
1+int main(void)
2+{
3+ return 0;
4+}
arch/mips/boot/compressed/head.S+56−0
@@ -0,0 +1,56 @@
1+/*
2+ * This file is subject to the terms and conditions of the GNU General Public
3+ * License. See the file "COPYING" in the main directory of this archive
4+ * for more details.
5+ *
6+ * Copyright (C) 1994, 1995 Waldorf Electronics
7+ * Written by Ralf Baechle and Andreas Busse
8+ * Copyright (C) 1995 - 1999 Ralf Baechle
9+ * Copyright (C) 1996 Paul M. Antoine
10+ * Modified for DECStation and hence R3000 support by Paul M. Antoine
11+ * Further modifications by David S. Miller and Harald Koerfgen
12+ * Copyright (C) 1999 Silicon Graphics, Inc.
13+ */
14+
15+#include <asm/asm.h>
16+#include <asm/regdef.h>
17+
18+ .set noreorder
19+ .cprestore
20+ LEAF(start)
21+start:
22+ /* Save boot rom start args */
23+ move s0, a0
24+ move s1, a1
25+ move s2, a2
26+ move s3, a3
27+
28+ /* Clear BSS */
29+ PTR_LA a0, _edata
30+ PTR_LA a2, _end
31+1: sw zero, 0(a0)
32+ bne a2, a0, 1b
33+ addiu a0, a0, 4
34+
35+ PTR_LA a0, (.heap) /* heap address */
36+ PTR_LA sp, (.stack + 8192) /* stack address */
37+
38+ PTR_LA ra, 2f
39+ PTR_LA k0, decompress_kernel
40+ jr k0
41+ nop
42+2:
43+ move a0, s0
44+ move a1, s1
45+ move a2, s2
46+ move a3, s3
47+ PTR_LI k0, KERNEL_ENTRY
48+ jr k0
49+ nop
50+3:
51+ b 3b
52+ nop
53+ END(start)
54+
55+ .comm .heap,BOOT_HEAP_SIZE,4
56+ .comm .stack,4096*2,4
arch/mips/boot/compressed/ld.script+150−0
@@ -0,0 +1,150 @@
1+OUTPUT_ARCH(mips)
2+ENTRY(start)
3+SECTIONS
4+{
5+ /* Read-only sections, merged into text segment: */
6+ .init : { *(.init) } =0
7+ .text :
8+ {
9+ _ftext = . ;
10+ *(.text)
11+ *(.rodata)
12+ *(.rodata1)
13+ /* .gnu.warning sections are handled specially by elf32.em. */
14+ *(.gnu.warning)
15+ } =0
16+ .kstrtab : { *(.kstrtab) }
17+
18+ . = ALIGN(16); /* Exception table */
19+ __start___ex_table = .;
20+ __ex_table : { *(__ex_table) }
21+ __stop___ex_table = .;
22+
23+ __start___dbe_table = .; /* Exception table for data bus errors */
24+ __dbe_table : { *(__dbe_table) }
25+ __stop___dbe_table = .;
26+
27+ __start___ksymtab = .; /* Kernel symbol table */
28+ __ksymtab : { *(__ksymtab) }
29+ __stop___ksymtab = .;
30+
31+ _etext = .;
32+
33+ . = ALIGN(8192);
34+ .data.init_task : { *(.data.init_task) }
35+
36+ /* Startup code */
37+ . = ALIGN(4096);
38+ __init_begin = .;
39+ .text.init : { *(.text.init) }
40+ .data.init : { *(.data.init) }
41+ . = ALIGN(16);
42+ __setup_start = .;
43+ .setup.init : { *(.setup.init) }
44+ __setup_end = .;
45+ __initcall_start = .;
46+ .initcall.init : { *(.initcall.init) }
47+ __initcall_end = .;
48+ . = ALIGN(4096); /* Align double page for init_task_union */
49+ __init_end = .;
50+
51+ . = ALIGN(4096);
52+ .data.page_aligned : { *(.data.idt) }
53+
54+ . = ALIGN(32);
55+ .data.cacheline_aligned : { *(.data.cacheline_aligned) }
56+
57+ .fini : { *(.fini) } =0
58+ .reginfo : { *(.reginfo) }
59+ /* Adjust the address for the data segment. We want to adjust up to
60+ the same address within the page on the next page up. It would
61+ be more correct to do this:
62+ . = .;
63+ The current expression does not correctly handle the case of a
64+ text segment ending precisely at the end of a page; it causes the
65+ data segment to skip a page. The above expression does not have
66+ this problem, but it will currently (2/95) cause BFD to allocate
67+ a single segment, combining both text and data, for this case.
68+ This will prevent the text segment from being shared among
69+ multiple executions of the program; I think that is more
70+ important than losing a page of the virtual address space (note
71+ that no actual memory is lost; the page which is skipped can not
72+ be referenced). */
73+ . = .;
74+ .data :
75+ {
76+ _fdata = . ;
77+ *(.data)
78+
79+ /* Put the compressed image here, so bss is on the end. */
80+ __image_begin = .;
81+ *(.image)
82+ __image_end = .;
83+ /* Align the initial ramdisk image (INITRD) on page boundaries. */
84+ . = ALIGN(4096);
85+ __ramdisk_begin = .;
86+ *(.initrd)
87+ __ramdisk_end = .;
88+ . = ALIGN(4096);
89+
90+ CONSTRUCTORS
91+ }
92+ .data1 : { *(.data1) }
93+ _gp = . + 0x8000;
94+ .lit8 : { *(.lit8) }
95+ .lit4 : { *(.lit4) }
96+ .ctors : { *(.ctors) }
97+ .dtors : { *(.dtors) }
98+ .got : { *(.got.plt) *(.got) }
99+ .dynamic : { *(.dynamic) }
100+ /* We want the small data sections together, so single-instruction offsets
101+ can access them all, and initialized data all before uninitialized, so
102+ we can shorten the on-disk segment size. */
103+ .sdata : { *(.sdata) }
104+ . = ALIGN(4);
105+ _edata = .;
106+ PROVIDE (edata = .);
107+
108+ __bss_start = .;
109+ _fbss = .;
110+ .sbss : { *(.sbss) *(.scommon) }
111+ .bss :
112+ {
113+ *(.dynbss)
114+ *(.bss)
115+ *(COMMON)
116+ . = ALIGN(4);
117+ _end = . ;
118+ PROVIDE (end = .);
119+ }
120+
121+ /* Sections to be discarded */
122+ /DISCARD/ :
123+ {
124+ *(.text.exit)
125+ *(.data.exit)
126+ *(.exitcall.exit)
127+ }
128+
129+ /* This is the MIPS specific mdebug section. */
130+ .mdebug : { *(.mdebug) }
131+ /* These are needed for ELF backends which have not yet been
132+ converted to the new style linker. */
133+ .stab 0 : { *(.stab) }
134+ .stabstr 0 : { *(.stabstr) }
135+ /* DWARF debug sections.
136+ Symbols in the .debug DWARF section are relative to the beginning of the
137+ section so we begin .debug at 0. It's not clear yet what needs to happen
138+ for the others. */
139+ .debug 0 : { *(.debug) }
140+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
141+ .debug_aranges 0 : { *(.debug_aranges) }
142+ .debug_pubnames 0 : { *(.debug_pubnames) }
143+ .debug_sfnames 0 : { *(.debug_sfnames) }
144+ .line 0 : { *(.line) }
145+ /* These must appear regardless of . */
146+ .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }
147+ .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }
148+ .comment : { *(.comment) }
149+ .note : { *(.note) }
150+}
arch/mips/boot/compressed/uart-16550.c+43−0
@@ -0,0 +1,43 @@
1+/*
2+ * 16550 compatible uart based serial debug support for zboot
3+ */
4+
5+#include <linux/types.h>
6+#include <linux/serial_reg.h>
7+#include <linux/init.h>
8+
9+#include <asm/addrspace.h>
10+
11+#if defined(CONFIG_MACH_LOONGSON) || defined(CONFIG_MIPS_MALTA)
12+#define UART_BASE 0x1fd003f8
13+#define PORT(offset) (CKSEG1ADDR(UART_BASE) + (offset))
14+#endif
15+
16+#ifdef CONFIG_AR7
17+#include <ar7.h>
18+#define PORT(offset) (CKSEG1ADDR(AR7_REGS_UART0) + (4 * offset))
19+#endif
20+
21+#ifndef PORT
22+#error please define the serial port address for your own machine
23+#endif
24+
25+static inline unsigned int serial_in(int offset)
26+{
27+ return *((char *)PORT(offset));
28+}
29+
30+static inline void serial_out(int offset, int value)
31+{
32+ *((char *)PORT(offset)) = value;
33+}
34+
35+void putc(char c)
36+{
37+ int timeout = 1024;
38+
39+ while (((serial_in(UART_LSR) & UART_LSR_THRE) == 0) && (timeout-- > 0))
40+ ;
41+
42+ serial_out(UART_TX, c);
43+}
arch/mips/cavium-octeon/Makefile+1−1
@@ -9,7 +9,7 @@ · 8 unmodified lines
99 # Copyright (C) 2005-2009 Cavium Networks
1010 #
1111
12−obj-y := setup.o serial.o octeon-platform.o octeon-irq.o csrc-octeon.o
12+obj-y := cpu.o setup.o serial.o octeon-platform.o octeon-irq.o csrc-octeon.o
1313 obj-y += dma-octeon.o flash_setup.o
1414 obj-y += octeon-memcpy.o
1515
arch/mips/cavium-octeon/cpu.c+52−0
@@ -0,0 +1,52 @@
1+/*
2+ * This file is subject to the terms and conditions of the GNU General Public
3+ * License. See the file "COPYING" in the main directory of this archive
4+ * for more details.
5+ *
6+ * Copyright (C) 2009 Wind River Systems,
7+ * written by Ralf Baechle <ralf@linux-mips.org>
8+ */
9+#include <linux/init.h>
10+#include <linux/irqflags.h>
11+#include <linux/notifier.h>
12+#include <linux/prefetch.h>
13+#include <linux/sched.h>
14+
15+#include <asm/cop2.h>
16+#include <asm/current.h>
17+#include <asm/mipsregs.h>
18+#include <asm/page.h>
19+#include <asm/octeon/octeon.h>
20+
21+static int cnmips_cu2_call(struct notifier_block *nfb, unsigned long action,
22+ void *data)
23+{
24+ unsigned long flags;
25+ unsigned int status;
26+
27+ switch (action) {
28+ case CU2_EXCEPTION:
29+ prefetch(&current->thread.cp2);
30+ local_irq_save(flags);
31+ KSTK_STATUS(current) |= ST0_CU2;
32+ status = read_c0_status();
33+ write_c0_status(status | ST0_CU2);
34+ octeon_cop2_restore(&(current->thread.cp2));
35+ write_c0_status(status & ~ST0_CU2);
36+ local_irq_restore(flags);
37+
38+ return NOTIFY_BAD; /* Don't call default notifier */
39+ }
40+
41+ return NOTIFY_OK; /* Let default notifier send signals */
42+}
43+
44+static struct notifier_block cnmips_cu2_notifier = {
45+ .notifier_call = cnmips_cu2_call,
46+};
47+
48+static int cnmips_cu2_setup(void)
49+{
50+ return register_cu2_notifier(&cnmips_cu2_notifier);
51+}
52+early_initcall(cnmips_cu2_setup);
arch/mips/cavium-octeon/octeon-platform.c+88−0
@@ -159,6 +159,94 @@ out: · 158 unmodified lines
159159 }
160160 device_initcall(octeon_rng_device_init);
161161
162+/* Octeon SMI/MDIO interface. */
163+static int __init octeon_mdiobus_device_init(void)
164+{
165+ struct platform_device *pd;
166+ int ret = 0;
167+
168+ if (octeon_is_simulation())
169+ return 0; /* No mdio in the simulator. */
170+
171+ /* The bus number is the platform_device id. */
172+ pd = platform_device_alloc("mdio-octeon", 0);
173+ if (!pd) {
174+ ret = -ENOMEM;
175+ goto out;
176+ }
177+
178+ ret = platform_device_add(pd);
179+ if (ret)
180+ goto fail;
181+
182+ return ret;
183+fail:
184+ platform_device_put(pd);
185+
186+out:
187+ return ret;
188+
189+}
190+device_initcall(octeon_mdiobus_device_init);
191+
192+/* Octeon mgmt port Ethernet interface. */
193+static int __init octeon_mgmt_device_init(void)
194+{
195+ struct platform_device *pd;
196+ int ret = 0;
197+ int port, num_ports;
198+
199+ struct resource mgmt_port_resource = {
200+ .flags = IORESOURCE_IRQ,
201+ .start = -1,
202+ .end = -1
203+ };
204+
205+ if (!OCTEON_IS_MODEL(OCTEON_CN56XX) && !OCTEON_IS_MODEL(OCTEON_CN52XX))
206+ return 0;
207+
208+ if (OCTEON_IS_MODEL(OCTEON_CN56XX))
209+ num_ports = 1;
210+ else
211+ num_ports = 2;
212+
213+ for (port = 0; port < num_ports; port++) {
214+ pd = platform_device_alloc("octeon_mgmt", port);
215+ if (!pd) {
216+ ret = -ENOMEM;
217+ goto out;
218+ }
219+ switch (port) {
220+ case 0:
221+ mgmt_port_resource.start = OCTEON_IRQ_MII0;
222+ break;
223+ case 1:
224+ mgmt_port_resource.start = OCTEON_IRQ_MII1;
225+ break;
226+ default:
227+ BUG();
228+ }
229+ mgmt_port_resource.end = mgmt_port_resource.start;
230+
231+ ret = platform_device_add_resources(pd, &mgmt_port_resource, 1);
232+
233+ if (ret)
234+ goto fail;
235+
236+ ret = platform_device_add(pd);
237+ if (ret)
238+ goto fail;
239+ }
240+ return ret;
241+fail:
242+ platform_device_put(pd);
243+
244+out:
245+ return ret;
246+
247+}
248+device_initcall(octeon_mgmt_device_init);
249+
162250 MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>");
163251 MODULE_LICENSE("GPL");
164252 MODULE_DESCRIPTION("Platform driver for Octeon SOC");
arch/mips/configs/ar7_defconfig+2−2
@@ -10,7 +10,6 @@ CONFIG_MIPS=y · 9 unmodified lines
1010 #
1111 # CONFIG_MACH_ALCHEMY is not set
1212 CONFIG_AR7=y
13−# CONFIG_BASLER_EXCITE is not set
1413 # CONFIG_BCM47XX is not set
1514 # CONFIG_MIPS_COBALT is not set
1615 # CONFIG_MACH_DECSTATION is not set
@@ -265,7 +264,6 @@ CONFIG_DEFAULT_DEADLINE=y · 248 unmodified lines
265264 # CONFIG_DEFAULT_CFQ is not set
266265 # CONFIG_DEFAULT_NOOP is not set
267266 CONFIG_DEFAULT_IOSCHED="deadline"
268−CONFIG_PROBE_INITRD_HEADER=y
269267 # CONFIG_FREEZER is not set
270268
271269 #
@@ -1053,7 +1051,9 @@ CONFIG_TRACING_SUPPORT=y · 781 unmodified lines
10531051 # CONFIG_DYNAMIC_DEBUG is not set
10541052 # CONFIG_SAMPLES is not set
10551053 CONFIG_HAVE_ARCH_KGDB=y
1054+CONFIG_CMDLINE_BOOL=y
10561055 CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
1056+# CONFIG_CMDLINE_OVERRIDE is not set
10571057
10581058 #
10591059 # Security options
arch/mips/configs/bcm47xx_defconfig+1−2
@@ -9,7 +9,6 @@ CONFIG_MIPS=y · 8 unmodified lines
99 # Machine selection
1010 #
1111 # CONFIG_MACH_ALCHEMY is not set
12−# CONFIG_BASLER_EXCITE is not set
1312 CONFIG_BCM47XX=y
1413 # CONFIG_MIPS_COBALT is not set
1514 # CONFIG_MACH_DECSTATION is not set
@@ -1853,7 +1852,7 @@ CONFIG_DEBUG_FS=y · 1837 unmodified lines
18531852 # CONFIG_HEADERS_CHECK is not set
18541853 # CONFIG_DEBUG_KERNEL is not set
18551854 # CONFIG_SAMPLES is not set
1856−CONFIG_CMDLINE=""
1855+# CONFIG_CMDLINE_BOOL is not set
18571856
18581857 #
18591858 # Security options
arch/mips/configs/bcm63xx_defconfig+2−1
@@ -9,7 +9,6 @@ CONFIG_MIPS=y · 8 unmodified lines
99 # Machine selection
1010 #
1111 # CONFIG_MACH_ALCHEMY is not set
12−# CONFIG_BASLER_EXCITE is not set
1312 # CONFIG_BCM47XX is not set
1413 CONFIG_BCM63XX=y
1514 # CONFIG_MIPS_COBALT is not set
@@ -942,7 +941,9 @@ CONFIG_TRACING_SUPPORT=y · 926 unmodified lines
942941 # CONFIG_BLK_DEV_IO_TRACE is not set
943942 # CONFIG_SAMPLES is not set
944943 CONFIG_HAVE_ARCH_KGDB=y
944+CONFIG_CMDLINE_BOOL=y
945945 CONFIG_CMDLINE="console=ttyS0,115200"
946+# CONFIG_CMDLINE_OVERRIDE is not set
946947
947948 #
948949 # Security options
arch/mips/configs/bigsur_defconfig+1−2
@@ -9,7 +9,6 @@ CONFIG_MIPS=y · 8 unmodified lines
99 # Machine selection
1010 #
1111 # CONFIG_MACH_ALCHEMY is not set
12−# CONFIG_BASLER_EXCITE is not set
1312 # CONFIG_BCM47XX is not set
1413 # CONFIG_MIPS_COBALT is not set
1514 # CONFIG_MACH_DECSTATION is not set
@@ -1237,7 +1236,7 @@ CONFIG_DEBUG_MUTEXES=y · 1221 unmodified lines
12371236 # CONFIG_BACKTRACE_SELF_TEST is not set
12381237 # CONFIG_FAULT_INJECTION is not set
12391238 # CONFIG_SAMPLES is not set
1240−CONFIG_CMDLINE=""
1239+# CONFIG_CMDLINE_BOOL is not set
12411240 # CONFIG_DEBUG_STACK_USAGE is not set
12421241 # CONFIG_SB1XXX_CORELIS is not set
12431242 # CONFIG_RUNTIME_DEBUG is not set
arch/mips/configs/capcella_defconfig+2−1
@@ -9,7 +9,6 @@ CONFIG_MIPS=y · 8 unmodified lines
99 # Machine selection
1010 #
1111 # CONFIG_MACH_ALCHEMY is not set
12−# CONFIG_BASLER_EXCITE is not set
1312 # CONFIG_MIPS_COBALT is not set
1413 # CONFIG_MACH_DECSTATION is not set
1514 # CONFIG_MACH_JAZZ is not set
@@ -783,7 +782,9 @@ CONFIG_ENABLE_MUST_CHECK=y · 767 unmodified lines
783782 # CONFIG_HEADERS_CHECK is not set
784783 # CONFIG_DEBUG_KERNEL is not set
785784 CONFIG_CROSSCOMPILE=y
785+CONFIG_CMDLINE_BOOL=y
786786 CONFIG_CMDLINE="mem=32M console=ttyVR0,38400"
787+# CONFIG_CMDLINE_OVERRIDE is not set
787788
788789 #
789790 # Security options
arch/mips/configs/cavium-octeon_defconfig+1−3
@@ -9,7 +9,6 @@ CONFIG_MIPS=y · 8 unmodified lines
99 # Machine selection
1010 #
1111 # CONFIG_MACH_ALCHEMY is not set
12−# CONFIG_BASLER_EXCITE is not set
1312 # CONFIG_BCM47XX is not set
1413 # CONFIG_MIPS_COBALT is not set
1514 # CONFIG_MACH_DECSTATION is not set
@@ -269,7 +268,6 @@ CONFIG_DEFAULT_CFQ=y · 253 unmodified lines
269268 # CONFIG_DEFAULT_NOOP is not set
270269 CONFIG_DEFAULT_IOSCHED="cfq"
271270 CONFIG_CLASSIC_RCU=y
272−# CONFIG_PROBE_INITRD_HEADER is not set
273271 # CONFIG_FREEZER is not set
274272
275273 #
@@ -822,7 +820,7 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y · 546 unmodified lines
822820 # CONFIG_SAMPLES is not set
823821 CONFIG_HAVE_ARCH_KGDB=y
824822 # CONFIG_KGDB is not set
825−CONFIG_CMDLINE=""
823+# CONFIG_CMDLINE_BOOL is not set
826824 # CONFIG_DEBUG_STACK_USAGE is not set
827825 # CONFIG_RUNTIME_DEBUG is not set
828826
arch/mips/configs/cobalt_defconfig+1−2
@@ -9,7 +9,6 @@ CONFIG_MIPS=y · 8 unmodified lines
99 # Machine selection
1010 #
1111 # CONFIG_MACH_ALCHEMY is not set
12−# CONFIG_BASLER_EXCITE is not set
1312 # CONFIG_BCM47XX is not set
1413 CONFIG_MIPS_COBALT=y
1514 # CONFIG_MACH_DECSTATION is not set
@@ -1126,7 +1125,7 @@ CONFIG_FRAME_WARN=1024 · 1110 unmodified lines
11261125 # CONFIG_SLUB_STATS is not set
11271126 # CONFIG_DEBUG_MEMORY_INIT is not set
11281127 # CONFIG_SAMPLES is not set
1129−CONFIG_CMDLINE=""
1128+# CONFIG_CMDLINE_BOOL is not set
11301129
11311130 #
11321131 # Security options
arch/mips/configs/db1000_defconfig+1−2
@@ -23,7 +23,6 @@ CONFIG_MIPS_DB1000=y · 22 unmodified lines
2323 # CONFIG_MIPS_DB1550 is not set
2424 # CONFIG_MIPS_DB1200 is not set
2525 # CONFIG_MIPS_MIRAGE is not set
26−# CONFIG_BASLER_EXCITE is not set
2726 # CONFIG_MIPS_COBALT is not set
2827 # CONFIG_MACH_DECSTATION is not set
2928 # CONFIG_MACH_JAZZ is not set
@@ -1090,7 +1089,7 @@ CONFIG_ENABLE_MUST_CHECK=y · 1060 unmodified lines
10901089 # CONFIG_DEBUG_KERNEL is not set
10911090 CONFIG_LOG_BUF_SHIFT=14
10921091 CONFIG_CROSSCOMPILE=y
1093−CONFIG_CMDLINE=""
1092+# CONFIG_CMDLINE_BOOL is not set
10941093
10951094 #
10961095 # Security options
arch/mips/configs/db1100_defconfig+1−2
@@ -23,7 +23,6 @@ CONFIG_MIPS_DB1100=y · 22 unmodified lines
2323 # CONFIG_MIPS_DB1550 is not set
2424 # CONFIG_MIPS_DB1200 is not set
2525 # CONFIG_MIPS_MIRAGE is not set
26−# CONFIG_BASLER_EXCITE is not set
2726 # CONFIG_MIPS_COBALT is not set
2827 # CONFIG_MACH_DECSTATION is not set
2928 # CONFIG_MACH_JAZZ is not set
@@ -1090,7 +1089,7 @@ CONFIG_ENABLE_MUST_CHECK=y · 1060 unmodified lines
10901089 # CONFIG_DEBUG_KERNEL is not set
10911090 CONFIG_LOG_BUF_SHIFT=14
10921091 CONFIG_CROSSCOMPILE=y
1093−CONFIG_CMDLINE=""
1092+# CONFIG_CMDLINE_BOOL is not set
10941093
10951094 #
10961095 # Security options
arch/mips/configs/db1200_defconfig+2−1
@@ -23,7 +23,6 @@ CONFIG_MACH_ALCHEMY=y · 22 unmodified lines
2323 # CONFIG_MIPS_DB1550 is not set
2424 CONFIG_MIPS_DB1200=y
2525 # CONFIG_MIPS_MIRAGE is not set
26−# CONFIG_BASLER_EXCITE is not set
2726 # CONFIG_MIPS_COBALT is not set
2827 # CONFIG_MACH_DECSTATION is not set
2928 # CONFIG_MACH_JAZZ is not set
@@ -1172,7 +1171,9 @@ CONFIG_ENABLE_MUST_CHECK=y · 1142 unmodified lines
11721171 # CONFIG_DEBUG_KERNEL is not set
11731172 CONFIG_LOG_BUF_SHIFT=14
11741173 CONFIG_CROSSCOMPILE=y
1174+CONFIG_CMDLINE_BOOL=y
11751175 CONFIG_CMDLINE="mem=48M"
1176+# CONFIG_CMDLINE_OVERRIDE is not set
11761177
11771178 #
11781179 # Security options
arch/mips/configs/db1500_defconfig+1−2
@@ -23,7 +23,6 @@ CONFIG_MIPS_DB1500=y · 22 unmodified lines
2323 # CONFIG_MIPS_DB1550 is not set
2424 # CONFIG_MIPS_DB1200 is not set
2525 # CONFIG_MIPS_MIRAGE is not set
26−# CONFIG_BASLER_EXCITE is not set
2726 # CONFIG_MIPS_COBALT is not set
2827 # CONFIG_MACH_DECSTATION is not set
2928 # CONFIG_MACH_JAZZ is not set
@@ -1390,7 +1389,7 @@ CONFIG_ENABLE_MUST_CHECK=y · 1360 unmodified lines
13901389 # CONFIG_DEBUG_KERNEL is not set
13911390 CONFIG_LOG_BUF_SHIFT=14
13921391 CONFIG_CROSSCOMPILE=y
1393−CONFIG_CMDLINE=""
1392+# CONFIG_CMDLINE_BOOL is not set
13941393
13951394 #
13961395 # Security options
arch/mips/configs/db1550_defconfig+1−2
@@ -23,7 +23,6 @@ CONFIG_MACH_ALCHEMY=y · 22 unmodified lines
2323 CONFIG_MIPS_DB1550=y
2424 # CONFIG_MIPS_DB1200 is not set
2525 # CONFIG_MIPS_MIRAGE is not set
26−# CONFIG_BASLER_EXCITE is not set
2726 # CONFIG_MIPS_COBALT is not set
2827 # CONFIG_MACH_DECSTATION is not set
2928 # CONFIG_MACH_JAZZ is not set
@@ -1207,7 +1206,7 @@ CONFIG_ENABLE_MUST_CHECK=y · 1177 unmodified lines
12071206 # CONFIG_DEBUG_KERNEL is not set
12081207 CONFIG_LOG_BUF_SHIFT=14
12091208 CONFIG_CROSSCOMPILE=y
1210−CONFIG_CMDLINE=""
1209+# CONFIG_CMDLINE_BOOL is not set
12111210
12121211 #
12131212 # Security options
arch/mips/configs/decstation_defconfig+1−2
@@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y · 21 unmodified lines
2222 # CONFIG_MIPS_DB1550 is not set
2323 # CONFIG_MIPS_DB1200 is not set
2424 # CONFIG_MIPS_MIRAGE is not set
25−# CONFIG_BASLER_EXCITE is not set
2625 # CONFIG_MIPS_COBALT is not set
2726 CONFIG_MACH_DECSTATION=y
2827 # CONFIG_MACH_JAZZ is not set
@@ -882,7 +881,7 @@ CONFIG_MAGIC_SYSRQ=y · 853 unmodified lines
882881 # CONFIG_DEBUG_KERNEL is not set
883882 CONFIG_LOG_BUF_SHIFT=14
884883 CONFIG_CROSSCOMPILE=y
885−CONFIG_CMDLINE=""
884+# CONFIG_CMDLINE_BOOL is not set
886885
887886 #
888887 # Security options
arch/mips/configs/e55_defconfig+2−1
@@ -9,7 +9,6 @@ CONFIG_MIPS=y · 8 unmodified lines
99 # Machine selection
1010 #
1111 # CONFIG_MACH_ALCHEMY is not set
12−# CONFIG_BASLER_EXCITE is not set
1312 # CONFIG_MIPS_COBALT is not set
1413 # CONFIG_MACH_DECSTATION is not set
1514 # CONFIG_MACH_JAZZ is not set
@@ -561,7 +560,9 @@ CONFIG_ENABLE_MUST_CHECK=y · 545 unmodified lines
561560 # CONFIG_HEADERS_CHECK is not set
562561 # CONFIG_DEBUG_KERNEL is not set
563562 CONFIG_CROSSCOMPILE=y
563+CONFIG_CMDLINE_BOOL=y
564564 CONFIG_CMDLINE="console=ttyVR0,19200 ide0=0x1f0,0x3f6,40 mem=8M"
565+# CONFIG_CMDLINE_OVERRIDE is not set
565566
566567 #
567568 # Security options
arch/mips/configs/excite_defconfig+0−1335
@@ -1,1335 +0,0 @@
1−#
2−# Automatically generated make config: don't edit
3−# Linux kernel version: 2.6.20
4−# Tue Feb 20 21:47:31 2007
5−#
6−CONFIG_MIPS=y
7−
8−#
9−# Machine selection
10−#
11−CONFIG_ZONE_DMA=y
12−# CONFIG_MIPS_MTX1 is not set
13−# CONFIG_MIPS_BOSPORUS is not set
14−# CONFIG_MIPS_PB1000 is not set
15−# CONFIG_MIPS_PB1100 is not set
16−# CONFIG_MIPS_PB1500 is not set
17−# CONFIG_MIPS_PB1550 is not set
18−# CONFIG_MIPS_PB1200 is not set
19−# CONFIG_MIPS_DB1000 is not set
20−# CONFIG_MIPS_DB1100 is not set
21−# CONFIG_MIPS_DB1500 is not set
22−# CONFIG_MIPS_DB1550 is not set
23−# CONFIG_MIPS_DB1200 is not set
24−# CONFIG_MIPS_MIRAGE is not set
25−CONFIG_BASLER_EXCITE=y
26−# CONFIG_BASLER_EXCITE_PROTOTYPE is not set
27−# CONFIG_MIPS_COBALT is not set
28−# CONFIG_MACH_DECSTATION is not set
29−# CONFIG_MACH_JAZZ is not set
30−# CONFIG_MIPS_MALTA is not set
31−# CONFIG_WR_PPMC is not set
32−# CONFIG_MIPS_SIM is not set
33−# CONFIG_MOMENCO_JAGUAR_ATX is not set
34−# CONFIG_MIPS_XXS1500 is not set
35−# CONFIG_PNX8550_JBS is not set
36−# CONFIG_PNX8550_STB810 is not set
37−# CONFIG_MACH_VR41XX is not set
38−# CONFIG_PMC_YOSEMITE is not set
39−# CONFIG_MARKEINS is not set
40−# CONFIG_SGI_IP22 is not set
41−# CONFIG_SGI_IP27 is not set
42−# CONFIG_SGI_IP32 is not set
43−# CONFIG_SIBYTE_BIGSUR is not set
44−# CONFIG_SIBYTE_SWARM is not set
45−# CONFIG_SIBYTE_SENTOSA is not set
46−# CONFIG_SIBYTE_RHONE is not set
47−# CONFIG_SIBYTE_CARMEL is not set
48−# CONFIG_SIBYTE_LITTLESUR is not set
49−# CONFIG_SIBYTE_CRHINE is not set
50−# CONFIG_SIBYTE_CRHONE is not set
51−# CONFIG_SNI_RM is not set
52−# CONFIG_TOSHIBA_JMR3927 is not set
53−# CONFIG_TOSHIBA_RBTX4927 is not set
54−# CONFIG_TOSHIBA_RBTX4938 is not set
55−CONFIG_RWSEM_GENERIC_SPINLOCK=y
56−# CONFIG_ARCH_HAS_ILOG2_U32 is not set
57−# CONFIG_ARCH_HAS_ILOG2_U64 is not set
58−CONFIG_GENERIC_FIND_NEXT_BIT=y
59−CONFIG_GENERIC_HWEIGHT=y
60−CONFIG_GENERIC_CALIBRATE_DELAY=y
61−CONFIG_GENERIC_TIME=y
62−CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
63−# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
64−CONFIG_DMA_COHERENT=y
65−CONFIG_CPU_BIG_ENDIAN=y
66−# CONFIG_CPU_LITTLE_ENDIAN is not set
67−CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
68−CONFIG_IRQ_CPU=y
69−CONFIG_IRQ_CPU_RM7K=y
70−CONFIG_IRQ_CPU_RM9K=y
71−CONFIG_MIPS_RM9122=y
72−CONFIG_SERIAL_RM9000=y
73−CONFIG_GPI_RM9000=y
74−CONFIG_WDT_RM9000=y
75−CONFIG_MIPS_L1_CACHE_SHIFT=5
76−
77−#
78−# CPU selection
79−#
80−# CONFIG_CPU_MIPS32_R1 is not set
81−# CONFIG_CPU_MIPS32_R2 is not set
82−# CONFIG_CPU_MIPS64_R1 is not set
83−# CONFIG_CPU_MIPS64_R2 is not set
84−# CONFIG_CPU_R3000 is not set
85−# CONFIG_CPU_TX39XX is not set
86−# CONFIG_CPU_VR41XX is not set
87−# CONFIG_CPU_R4300 is not set
88−# CONFIG_CPU_R4X00 is not set
89−# CONFIG_CPU_TX49XX is not set
90−# CONFIG_CPU_R5000 is not set
91−# CONFIG_CPU_R5432 is not set
92−# CONFIG_CPU_R6000 is not set
93−# CONFIG_CPU_NEVADA is not set
94−# CONFIG_CPU_R8000 is not set
95−# CONFIG_CPU_R10000 is not set
96−# CONFIG_CPU_RM7000 is not set
97−CONFIG_CPU_RM9000=y
98−# CONFIG_CPU_SB1 is not set
99−CONFIG_SYS_HAS_CPU_RM9000=y
100−CONFIG_WEAK_ORDERING=y
101−CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
102−CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
103−CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
104−CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
105−
106−#
107−# Kernel type
108−#
109−CONFIG_32BIT=y
110−# CONFIG_64BIT is not set
111−CONFIG_PAGE_SIZE_4KB=y
112−# CONFIG_PAGE_SIZE_8KB is not set
113−# CONFIG_PAGE_SIZE_16KB is not set
114−# CONFIG_PAGE_SIZE_64KB is not set
115−CONFIG_CPU_HAS_PREFETCH=y
116−CONFIG_MIPS_MT_DISABLED=y
117−# CONFIG_MIPS_MT_SMP is not set
118−# CONFIG_MIPS_MT_SMTC is not set
119−# CONFIG_MIPS_VPE_LOADER is not set
120−# CONFIG_64BIT_PHYS_ADDR is not set
121−CONFIG_CPU_HAS_SYNC=y
122−CONFIG_GENERIC_HARDIRQS=y
123−CONFIG_GENERIC_IRQ_PROBE=y
124−CONFIG_CPU_SUPPORTS_HIGHMEM=y
125−CONFIG_ARCH_FLATMEM_ENABLE=y
126−CONFIG_SELECT_MEMORY_MODEL=y
127−CONFIG_FLATMEM_MANUAL=y
128−# CONFIG_DISCONTIGMEM_MANUAL is not set
129−# CONFIG_SPARSEMEM_MANUAL is not set
130−CONFIG_FLATMEM=y
131−CONFIG_FLAT_NODE_MEM_MAP=y
132−# CONFIG_SPARSEMEM_STATIC is not set
133−CONFIG_SPLIT_PTLOCK_CPUS=4
134−# CONFIG_RESOURCES_64BIT is not set
135−CONFIG_ZONE_DMA_FLAG=1
136−# CONFIG_HZ_48 is not set
137−# CONFIG_HZ_100 is not set
138−# CONFIG_HZ_128 is not set
139−# CONFIG_HZ_250 is not set
140−# CONFIG_HZ_256 is not set
141−CONFIG_HZ_1000=y
142−# CONFIG_HZ_1024 is not set
143−CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
144−CONFIG_HZ=1000
145−# CONFIG_PREEMPT_NONE is not set
146−# CONFIG_PREEMPT_VOLUNTARY is not set
147−CONFIG_PREEMPT=y
148−CONFIG_PREEMPT_BKL=y
149−# CONFIG_KEXEC is not set
150−CONFIG_LOCKDEP_SUPPORT=y
151−CONFIG_STACKTRACE_SUPPORT=y
152−CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
153−
154−#
155−# Code maturity level options
156−#
157−CONFIG_EXPERIMENTAL=y
158−CONFIG_BROKEN_ON_SMP=y
159−CONFIG_LOCK_KERNEL=y
160−CONFIG_INIT_ENV_ARG_LIMIT=32
161−
162−#
163−# General setup
164−#
165−CONFIG_LOCALVERSION=""
166−# CONFIG_LOCALVERSION_AUTO is not set
167−CONFIG_SWAP=y
168−CONFIG_SYSVIPC=y
169−# CONFIG_IPC_NS is not set
170−CONFIG_SYSVIPC_SYSCTL=y
171−CONFIG_POSIX_MQUEUE=y
172−# CONFIG_BSD_PROCESS_ACCT is not set
173−# CONFIG_TASKSTATS is not set
174−# CONFIG_UTS_NS is not set
175−# CONFIG_AUDIT is not set
176−# CONFIG_IKCONFIG is not set
177−CONFIG_SYSFS_DEPRECATED=y
178−# CONFIG_RELAY is not set
179−CONFIG_CC_OPTIMIZE_FOR_SIZE=y
180−CONFIG_SYSCTL=y
181−CONFIG_EMBEDDED=y
182−CONFIG_SYSCTL_SYSCALL=y
183−CONFIG_KALLSYMS=y
184−# CONFIG_KALLSYMS_EXTRA_PASS is not set
185−CONFIG_HOTPLUG=y
186−CONFIG_PRINTK=y
187−CONFIG_BUG=y
188−CONFIG_ELF_CORE=y
189−CONFIG_BASE_FULL=y
190−CONFIG_FUTEX=y
191−CONFIG_EPOLL=y
192−CONFIG_SHMEM=y
193−CONFIG_SLAB=y
194−CONFIG_VM_EVENT_COUNTERS=y
195−CONFIG_RT_MUTEXES=y
196−# CONFIG_TINY_SHMEM is not set
197−CONFIG_BASE_SMALL=0
198−# CONFIG_SLOB is not set
199−
200−#
201−# Loadable module support
202−#
203−CONFIG_MODULES=y
204−CONFIG_MODULE_UNLOAD=y
205−# CONFIG_MODULE_FORCE_UNLOAD is not set
206−# CONFIG_MODVERSIONS is not set
207−# CONFIG_MODULE_SRCVERSION_ALL is not set
208−CONFIG_KMOD=y
209−
210−#
211−# Block layer
212−#
213−CONFIG_BLOCK=y
214−# CONFIG_LBD is not set
215−# CONFIG_BLK_DEV_IO_TRACE is not set
216−# CONFIG_LSF is not set
217−
218−#
219−# IO Schedulers
220−#
221−CONFIG_IOSCHED_NOOP=y
222−CONFIG_IOSCHED_AS=y
223−CONFIG_IOSCHED_DEADLINE=y
224−CONFIG_IOSCHED_CFQ=y
225−CONFIG_DEFAULT_AS=y
226−# CONFIG_DEFAULT_DEADLINE is not set
227−# CONFIG_DEFAULT_CFQ is not set
228−# CONFIG_DEFAULT_NOOP is not set
229−CONFIG_DEFAULT_IOSCHED="anticipatory"
230−
231−#
232−# Bus options (PCI, PCMCIA, EISA, ISA, TC)
233−#
234−CONFIG_HW_HAS_PCI=y
235−CONFIG_PCI=y
236−CONFIG_MMU=y
237−
238−#
239−# PCCARD (PCMCIA/CardBus) support
240−#
241−# CONFIG_PCCARD is not set
242−
243−#
244−# PCI Hotplug Support
245−#
246−# CONFIG_HOTPLUG_PCI is not set
247−
248−#
249−# Executable file formats
250−#
251−CONFIG_BINFMT_ELF=y
252−# CONFIG_BINFMT_MISC is not set
253−CONFIG_TRAD_SIGNALS=y
254−
255−#
256−# Power management options
257−#
258−CONFIG_PM=y
259−# CONFIG_PM_LEGACY is not set
260−# CONFIG_PM_DEBUG is not set
261−# CONFIG_PM_SYSFS_DEPRECATED is not set
262−
263−#
264−# Networking
265−#
266−CONFIG_NET=y
267−
268−#
269−# Networking options
270−#
271−# CONFIG_NETDEBUG is not set
272−CONFIG_PACKET=y
273−CONFIG_PACKET_MMAP=y
274−CONFIG_UNIX=y
275−CONFIG_XFRM=y
276−# CONFIG_XFRM_USER is not set
277−# CONFIG_XFRM_SUB_POLICY is not set
278−CONFIG_XFRM_MIGRATE=y
279−# CONFIG_NET_KEY is not set
280−CONFIG_INET=y
281−# CONFIG_IP_MULTICAST is not set
282−# CONFIG_IP_ADVANCED_ROUTER is not set
283−CONFIG_IP_FIB_HASH=y
284−CONFIG_IP_PNP=y
285−CONFIG_IP_PNP_DHCP=y
286−# CONFIG_IP_PNP_BOOTP is not set
287−# CONFIG_IP_PNP_RARP is not set
288−# CONFIG_NET_IPIP is not set
289−# CONFIG_NET_IPGRE is not set
290−# CONFIG_ARPD is not set
291−# CONFIG_SYN_COOKIES is not set
292−# CONFIG_INET_AH is not set
293−# CONFIG_INET_ESP is not set
294−# CONFIG_INET_IPCOMP is not set
295−# CONFIG_INET_XFRM_TUNNEL is not set
296−# CONFIG_INET_TUNNEL is not set
297−CONFIG_INET_XFRM_MODE_TRANSPORT=m
298−CONFIG_INET_XFRM_MODE_TUNNEL=m
299−CONFIG_INET_XFRM_MODE_BEET=m
300−CONFIG_INET_DIAG=y
301−CONFIG_INET_TCP_DIAG=y
302−# CONFIG_TCP_CONG_ADVANCED is not set
303−CONFIG_TCP_CONG_CUBIC=y
304−CONFIG_DEFAULT_TCP_CONG="cubic"
305−CONFIG_TCP_MD5SIG=y
306−# CONFIG_IPV6 is not set
307−# CONFIG_INET6_XFRM_TUNNEL is not set
308−# CONFIG_INET6_TUNNEL is not set
309−CONFIG_NETWORK_SECMARK=y
310−# CONFIG_NETFILTER is not set
311−
312−#
313−# DCCP Configuration (EXPERIMENTAL)
314−#
315−# CONFIG_IP_DCCP is not set
316−
317−#
318−# SCTP Configuration (EXPERIMENTAL)
319−#
320−# CONFIG_IP_SCTP is not set
321−
322−#
323−# TIPC Configuration (EXPERIMENTAL)
324−#
325−# CONFIG_TIPC is not set
326−# CONFIG_ATM is not set
327−# CONFIG_BRIDGE is not set
328−# CONFIG_VLAN_8021Q is not set
329−# CONFIG_DECNET is not set
330−# CONFIG_LLC2 is not set
331−# CONFIG_IPX is not set
332−# CONFIG_ATALK is not set
333−# CONFIG_X25 is not set
334−# CONFIG_LAPB is not set
335−# CONFIG_ECONET is not set
336−# CONFIG_WAN_ROUTER is not set
337−
338−#
339−# QoS and/or fair queueing
340−#
341−# CONFIG_NET_SCHED is not set
342−
343−#
344−# Network testing
345−#
346−# CONFIG_NET_PKTGEN is not set
347−# CONFIG_HAMRADIO is not set
348−# CONFIG_IRDA is not set
349−# CONFIG_BT is not set
350−# CONFIG_IEEE80211 is not set
351−
352−#
353−# Device Drivers
354−#
355−
356−#
357−# Generic Driver Options
358−#
359−CONFIG_STANDALONE=y
360−CONFIG_PREVENT_FIRMWARE_BUILD=y
361−CONFIG_FW_LOADER=m
362−# CONFIG_SYS_HYPERVISOR is not set
363−
364−#
365−# Connector - unified userspace <-> kernelspace linker
366−#
367−# CONFIG_CONNECTOR is not set
368−
369−#
370−# Memory Technology Devices (MTD)
371−#
372−CONFIG_MTD=y
373−# CONFIG_MTD_DEBUG is not set
374−# CONFIG_MTD_CONCAT is not set
375−CONFIG_MTD_PARTITIONS=y
376−# CONFIG_MTD_REDBOOT_PARTS is not set
377−# CONFIG_MTD_CMDLINE_PARTS is not set
378−
379−#
380−# User Modules And Translation Layers
381−#
382−CONFIG_MTD_CHAR=y
383−CONFIG_MTD_BLKDEVS=y
384−CONFIG_MTD_BLOCK=y
385−# CONFIG_FTL is not set
386−# CONFIG_NFTL is not set
387−# CONFIG_INFTL is not set
388−# CONFIG_RFD_FTL is not set
389−# CONFIG_SSFDC is not set
390−
391−#
392−# RAM/ROM/Flash chip drivers
393−#
394−# CONFIG_MTD_CFI is not set
395−# CONFIG_MTD_JEDECPROBE is not set
396−CONFIG_MTD_MAP_BANK_WIDTH_1=y
397−CONFIG_MTD_MAP_BANK_WIDTH_2=y
398−CONFIG_MTD_MAP_BANK_WIDTH_4=y
399−# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
400−# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
401−# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
402−CONFIG_MTD_CFI_I1=y
403−CONFIG_MTD_CFI_I2=y
404−# CONFIG_MTD_CFI_I4 is not set
405−# CONFIG_MTD_CFI_I8 is not set
406−# CONFIG_MTD_RAM is not set
407−# CONFIG_MTD_ROM is not set
408−# CONFIG_MTD_ABSENT is not set
409−# CONFIG_MTD_OBSOLETE_CHIPS is not set
410−
411−#
412−# Mapping drivers for chip access
413−#
414−# CONFIG_MTD_COMPLEX_MAPPINGS is not set
415−# CONFIG_MTD_PLATRAM is not set
416−
417−#
418−# Self-contained MTD device drivers
419−#
420−# CONFIG_MTD_PMC551 is not set
421−# CONFIG_MTD_SLRAM is not set
422−# CONFIG_MTD_PHRAM is not set
423−# CONFIG_MTD_MTDRAM is not set
424−# CONFIG_MTD_BLOCK2MTD is not set
425−
426−#
427−# Disk-On-Chip Device Drivers
428−#
429−# CONFIG_MTD_DOC2000 is not set
430−# CONFIG_MTD_DOC2001 is not set
431−# CONFIG_MTD_DOC2001PLUS is not set
432−
433−#
434−# NAND Flash Device Drivers
435−#
436−CONFIG_MTD_NAND=y
437−CONFIG_MTD_NAND_VERIFY_WRITE=y
438−# CONFIG_MTD_NAND_ECC_SMC is not set
439−CONFIG_MTD_NAND_IDS=y
440−# CONFIG_MTD_NAND_DISKONCHIP is not set
441−# CONFIG_MTD_NAND_BASLER_EXCITE is not set
442−# CONFIG_MTD_NAND_CAFE is not set
443−# CONFIG_MTD_NAND_NANDSIM is not set
444−
445−#
446−# OneNAND Flash Device Drivers
447−#
448−# CONFIG_MTD_ONENAND is not set
449−
450−#
451−# Parallel port support
452−#
453−# CONFIG_PARPORT is not set
454−
455−#
456−# Plug and Play support
457−#
458−# CONFIG_PNPACPI is not set
459−
460−#
461−# Block devices
462−#
463−# CONFIG_BLK_CPQ_DA is not set
464−# CONFIG_BLK_CPQ_CISS_DA is not set
465−# CONFIG_BLK_DEV_DAC960 is not set
466−# CONFIG_BLK_DEV_UMEM is not set
467−# CONFIG_BLK_DEV_COW_COMMON is not set
468−CONFIG_BLK_DEV_LOOP=m
469−# CONFIG_BLK_DEV_CRYPTOLOOP is not set
470−# CONFIG_BLK_DEV_NBD is not set
471−# CONFIG_BLK_DEV_SX8 is not set
472−# CONFIG_BLK_DEV_UB is not set
473−# CONFIG_BLK_DEV_RAM is not set
474−# CONFIG_BLK_DEV_INITRD is not set
475−# CONFIG_CDROM_PKTCDVD is not set
476−# CONFIG_ATA_OVER_ETH is not set
477−
478−#
479−# Misc devices
480−#
481−CONFIG_SGI_IOC4=m
482−# CONFIG_TIFM_CORE is not set
483−
484−#
485−# ATA/ATAPI/MFM/RLL support
486−#
487−# CONFIG_IDE is not set
488−
489−#
490−# SCSI device support
491−#
492−# CONFIG_RAID_ATTRS is not set
493−CONFIG_SCSI=y
494−CONFIG_SCSI_TGT=m
495−# CONFIG_SCSI_NETLINK is not set
496−# CONFIG_SCSI_PROC_FS is not set
497−
498−#
499−# SCSI support type (disk, tape, CD-ROM)
500−#
501−CONFIG_BLK_DEV_SD=y
502−# CONFIG_CHR_DEV_ST is not set
503−# CONFIG_CHR_DEV_OSST is not set
504−# CONFIG_BLK_DEV_SR is not set
505−# CONFIG_CHR_DEV_SG is not set
506−# CONFIG_CHR_DEV_SCH is not set
507−
508−#
509−# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
510−#
511−# CONFIG_SCSI_MULTI_LUN is not set
512−# CONFIG_SCSI_CONSTANTS is not set
513−# CONFIG_SCSI_LOGGING is not set
514−CONFIG_SCSI_SCAN_ASYNC=y
515−
516−#
517−# SCSI Transports
518−#
519−# CONFIG_SCSI_SPI_ATTRS is not set
520−# CONFIG_SCSI_FC_ATTRS is not set
521−# CONFIG_SCSI_ISCSI_ATTRS is not set
522−CONFIG_SCSI_SAS_ATTRS=m
523−CONFIG_SCSI_SAS_LIBSAS=m
524−# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
525−
526−#
527−# SCSI low-level drivers
528−#
529−# CONFIG_ISCSI_TCP is not set
530−# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
531−# CONFIG_SCSI_3W_9XXX is not set
532−# CONFIG_SCSI_ACARD is not set
533−# CONFIG_SCSI_AACRAID is not set
534−# CONFIG_SCSI_AIC7XXX is not set
535−# CONFIG_SCSI_AIC7XXX_OLD is not set
536−# CONFIG_SCSI_AIC79XX is not set
537−CONFIG_SCSI_AIC94XX=m
538−# CONFIG_AIC94XX_DEBUG is not set
539−# CONFIG_SCSI_DPT_I2O is not set
540−# CONFIG_SCSI_ARCMSR is not set
541−# CONFIG_MEGARAID_NEWGEN is not set
542−# CONFIG_MEGARAID_LEGACY is not set
543−# CONFIG_MEGARAID_SAS is not set
544−# CONFIG_SCSI_HPTIOP is not set
545−# CONFIG_SCSI_DMX3191D is not set
546−# CONFIG_SCSI_FUTURE_DOMAIN is not set
547−# CONFIG_SCSI_IPS is not set
548−# CONFIG_SCSI_INITIO is not set
549−# CONFIG_SCSI_INIA100 is not set
550−# CONFIG_SCSI_STEX is not set
551−# CONFIG_SCSI_SYM53C8XX_2 is not set
552−# CONFIG_SCSI_QLOGIC_1280 is not set
553−# CONFIG_SCSI_QLA_FC is not set
554−# CONFIG_SCSI_QLA_ISCSI is not set
555−# CONFIG_SCSI_LPFC is not set
556−# CONFIG_SCSI_DC395x is not set
557−# CONFIG_SCSI_DC390T is not set
558−# CONFIG_SCSI_NSP32 is not set
559−# CONFIG_SCSI_DEBUG is not set
560−# CONFIG_SCSI_SRP is not set
561−
562−#
563−# Serial ATA (prod) and Parallel ATA (experimental) drivers
564−#
565−# CONFIG_ATA is not set
566−
567−#
568−# Multi-device support (RAID and LVM)
569−#
570−# CONFIG_MD is not set
571−
572−#
573−# Fusion MPT device support
574−#
575−# CONFIG_FUSION is not set
576−# CONFIG_FUSION_SPI is not set
577−# CONFIG_FUSION_FC is not set
578−# CONFIG_FUSION_SAS is not set
579−
580−#
581−# IEEE 1394 (FireWire) support
582−#
583−# CONFIG_IEEE1394 is not set
584−
585−#
586−# I2O device support
587−#
588−# CONFIG_I2O is not set
589−
590−#
591−# Network device support
592−#
593−CONFIG_NETDEVICES=y
594−# CONFIG_DUMMY is not set
595−# CONFIG_BONDING is not set
596−# CONFIG_EQUALIZER is not set
597−# CONFIG_TUN is not set
598−
599−#
600−# ARCnet devices
601−#
602−# CONFIG_ARCNET is not set
603−
604−#
605−# PHY device support
606−#
607−
608−#
609−# Ethernet (10 or 100Mbit)
610−#
611−# CONFIG_NET_ETHERNET is not set
612−
613−#
614−# Ethernet (1000 Mbit)
615−#
616−# CONFIG_ACENIC is not set
617−# CONFIG_DL2K is not set
618−# CONFIG_E1000 is not set
619−# CONFIG_NS83820 is not set
620−# CONFIG_HAMACHI is not set
621−# CONFIG_YELLOWFIN is not set
622−# CONFIG_R8169 is not set
623−# CONFIG_SIS190 is not set
624−# CONFIG_SKGE is not set
625−# CONFIG_SKY2 is not set
626−# CONFIG_SK98LIN is not set
627−# CONFIG_TIGON3 is not set
628−# CONFIG_BNX2 is not set
629−CONFIG_QLA3XXX=m
630−# CONFIG_ATL1 is not set
631−
632−#
633−# Ethernet (10000 Mbit)
634−#
635−# CONFIG_CHELSIO_T1 is not set
636−CONFIG_CHELSIO_T3=m
637−# CONFIG_IXGB is not set
638−# CONFIG_S2IO is not set
639−# CONFIG_MYRI10GE is not set
640−CONFIG_NETXEN_NIC=m
641−
642−#
643−# Token Ring devices
644−#
645−# CONFIG_TR is not set
646−
647−#
648−# Wireless LAN (non-hamradio)
649−#
650−# CONFIG_NET_RADIO is not set
651−
652−#
653−# Wan interfaces
654−#
655−# CONFIG_WAN is not set
656−# CONFIG_FDDI is not set
657−# CONFIG_HIPPI is not set
658−# CONFIG_PPP is not set
659−# CONFIG_SLIP is not set
660−# CONFIG_NET_FC is not set
661−# CONFIG_SHAPER is not set
662−# CONFIG_NETCONSOLE is not set
663−# CONFIG_NETPOLL is not set
664−# CONFIG_NET_POLL_CONTROLLER is not set
665−
666−#
667−# ISDN subsystem
668−#
669−# CONFIG_ISDN is not set
670−
671−#
672−# Telephony Support
673−#
674−# CONFIG_PHONE is not set
675−
676−#
677−# Input device support
678−#
679−CONFIG_INPUT=y
680−# CONFIG_INPUT_FF_MEMLESS is not set
681−
682−#
683−# Userland interfaces
684−#
685−CONFIG_INPUT_MOUSEDEV=m
686−CONFIG_INPUT_MOUSEDEV_PSAUX=y
687−CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
688−CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
689−# CONFIG_INPUT_JOYDEV is not set
690−# CONFIG_INPUT_TSDEV is not set
691−CONFIG_INPUT_EVDEV=m
692−# CONFIG_INPUT_EVBUG is not set
693−
694−#
695−# Input Device Drivers
696−#
697−# CONFIG_INPUT_KEYBOARD is not set
698−# CONFIG_INPUT_MOUSE is not set
699−# CONFIG_INPUT_JOYSTICK is not set
700−# CONFIG_INPUT_TOUCHSCREEN is not set
701−# CONFIG_INPUT_MISC is not set
702−
703−#
704−# Hardware I/O ports
705−#
706−# CONFIG_SERIO is not set
707−# CONFIG_GAMEPORT is not set
708−
709−#
710−# Character devices
711−#
712−CONFIG_VT=y
713−CONFIG_VT_CONSOLE=y
714−CONFIG_HW_CONSOLE=y
715−CONFIG_VT_HW_CONSOLE_BINDING=y
716−# CONFIG_SERIAL_NONSTANDARD is not set
717−
718−#
719−# Serial drivers
720−#
721−CONFIG_SERIAL_8250=y
722−CONFIG_SERIAL_8250_CONSOLE=y
723−CONFIG_SERIAL_8250_PCI=y
724−CONFIG_SERIAL_8250_NR_UARTS=2
725−CONFIG_SERIAL_8250_RUNTIME_UARTS=2
726−CONFIG_SERIAL_8250_EXTENDED=y
727−# CONFIG_SERIAL_8250_MANY_PORTS is not set
728−CONFIG_SERIAL_8250_SHARE_IRQ=y
729−# CONFIG_SERIAL_8250_DETECT_IRQ is not set
730−# CONFIG_SERIAL_8250_RSA is not set
731−
732−#
733−# Non-8250 serial port support
734−#
735−CONFIG_SERIAL_CORE=y
736−CONFIG_SERIAL_CORE_CONSOLE=y
737−# CONFIG_SERIAL_JSM is not set
738−CONFIG_UNIX98_PTYS=y
739−# CONFIG_LEGACY_PTYS is not set
740−
741−#
742−# IPMI
743−#
744−# CONFIG_IPMI_HANDLER is not set
745−
746−#
747−# Watchdog Cards
748−#
749−CONFIG_WATCHDOG=y
750−# CONFIG_WATCHDOG_NOWAYOUT is not set
751−
752−#
753−# Watchdog Device Drivers
754−#
755−# CONFIG_SOFT_WATCHDOG is not set
756−CONFIG_WDT_RM9K_GPI=m
757−
758−#
759−# PCI-based Watchdog Cards
760−#
761−# CONFIG_PCIPCWATCHDOG is not set
762−# CONFIG_WDTPCI is not set
763−
764−#
765−# USB-based Watchdog Cards
766−#
767−# CONFIG_USBPCWATCHDOG is not set
768−# CONFIG_HW_RANDOM is not set
769−# CONFIG_RTC is not set
770−# CONFIG_GEN_RTC is not set
771−# CONFIG_DTLK is not set
772−# CONFIG_R3964 is not set
773−# CONFIG_APPLICOM is not set
774−# CONFIG_DRM is not set
775−# CONFIG_RAW_DRIVER is not set
776−
777−#
778−# TPM devices
779−#
780−# CONFIG_TCG_TPM is not set
781−
782−#
783−# I2C support
784−#
785−# CONFIG_I2C is not set
786−
787−#
788−# SPI support
789−#
790−# CONFIG_SPI is not set
791−# CONFIG_SPI_MASTER is not set
792−
793−#
794−# Dallas's 1-wire bus
795−#
796−# CONFIG_W1 is not set
797−
798−#
799−# Hardware Monitoring support
800−#
801−# CONFIG_HWMON is not set
802−# CONFIG_HWMON_VID is not set
803−
804−#
805−# Multimedia devices
806−#
807−# CONFIG_VIDEO_DEV is not set
808−
809−#
810−# Digital Video Broadcasting Devices
811−#
812−# CONFIG_DVB is not set
813−# CONFIG_USB_DABUSB is not set
814−
815−#
816−# Graphics support
817−#
818−# CONFIG_FIRMWARE_EDID is not set
819−CONFIG_FB=y
820−# CONFIG_FB_CFB_FILLRECT is not set
821−# CONFIG_FB_CFB_COPYAREA is not set
822−# CONFIG_FB_CFB_IMAGEBLIT is not set
823−# CONFIG_FB_SVGALIB is not set
824−# CONFIG_FB_MACMODES is not set
825−# CONFIG_FB_BACKLIGHT is not set
826−# CONFIG_FB_MODE_HELPERS is not set
827−# CONFIG_FB_TILEBLITTING is not set
828−# CONFIG_FB_CIRRUS is not set
829−# CONFIG_FB_PM2 is not set
830−# CONFIG_FB_CYBER2000 is not set
831−# CONFIG_FB_ASILIANT is not set
832−# CONFIG_FB_IMSTT is not set
833−# CONFIG_FB_S1D13XXX is not set
834−# CONFIG_FB_NVIDIA is not set
835−# CONFIG_FB_RIVA is not set
836−# CONFIG_FB_MATROX is not set
837−# CONFIG_FB_RADEON is not set
838−# CONFIG_FB_ATY128 is not set
839−# CONFIG_FB_ATY is not set
840−# CONFIG_FB_S3 is not set
841−# CONFIG_FB_SAVAGE is not set
842−# CONFIG_FB_SIS is not set
843−# CONFIG_FB_NEOMAGIC is not set
844−# CONFIG_FB_KYRO is not set
845−# CONFIG_FB_3DFX is not set
846−# CONFIG_FB_VOODOO1 is not set
847−# CONFIG_FB_SMIVGX is not set
848−# CONFIG_FB_TRIDENT is not set
849−# CONFIG_FB_VIRTUAL is not set
850−
851−#
852−# Console display driver support
853−#
854−# CONFIG_VGA_CONSOLE is not set
855−CONFIG_DUMMY_CONSOLE=y
856−CONFIG_FRAMEBUFFER_CONSOLE=m
857−# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
858−# CONFIG_FONTS is not set
859−CONFIG_FONT_8x8=y
860−CONFIG_FONT_8x16=y
861−
862−#
863−# Logo configuration
864−#
865−# CONFIG_LOGO is not set
866−# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
867−
868−#
869−# Sound
870−#
871−# CONFIG_SOUND is not set
872−
873−#
874−# HID Devices
875−#
876−CONFIG_HID=y
877−# CONFIG_HID_DEBUG is not set
878−
879−#
880−# USB support
881−#
882−CONFIG_USB_ARCH_HAS_HCD=y
883−CONFIG_USB_ARCH_HAS_OHCI=y
884−CONFIG_USB_ARCH_HAS_EHCI=y
885−CONFIG_USB=y
886−# CONFIG_USB_DEBUG is not set
887−
888−#
889−# Miscellaneous USB options
890−#
891−CONFIG_USB_DEVICEFS=y
892−# CONFIG_USB_DYNAMIC_MINORS is not set
893−# CONFIG_USB_SUSPEND is not set
894−# CONFIG_USB_OTG is not set
895−
896−#
897−# USB Host Controller Drivers
898−#
899−CONFIG_USB_EHCI_HCD=y
900−# CONFIG_USB_EHCI_SPLIT_ISO is not set
901−# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
902−# CONFIG_USB_EHCI_TT_NEWSCHED is not set
903−# CONFIG_USB_EHCI_BIG_ENDIAN_MMIO is not set
904−# CONFIG_USB_ISP116X_HCD is not set
905−CONFIG_USB_OHCI_HCD=y
906−# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
907−# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
908−CONFIG_USB_OHCI_LITTLE_ENDIAN=y
909−# CONFIG_USB_UHCI_HCD is not set
910−# CONFIG_USB_SL811_HCD is not set
911−
912−#
913−# USB Device Class drivers
914−#
915−# CONFIG_USB_ACM is not set
916−# CONFIG_USB_PRINTER is not set
917−
918−#
919−# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
920−#
921−
922−#
923−# may also be needed; see USB_STORAGE Help for more information
924−#
925−CONFIG_USB_STORAGE=y
926−# CONFIG_USB_STORAGE_DEBUG is not set
927−# CONFIG_USB_STORAGE_DATAFAB is not set
928−# CONFIG_USB_STORAGE_FREECOM is not set
929−# CONFIG_USB_STORAGE_DPCM is not set
930−# CONFIG_USB_STORAGE_USBAT is not set
931−# CONFIG_USB_STORAGE_SDDR09 is not set
932−# CONFIG_USB_STORAGE_SDDR55 is not set
933−# CONFIG_USB_STORAGE_JUMPSHOT is not set
934−# CONFIG_USB_STORAGE_ALAUDA is not set
935−# CONFIG_USB_STORAGE_KARMA is not set
936−# CONFIG_USB_LIBUSUAL is not set
937−
938−#
939−# USB Input Devices
940−#
941−CONFIG_USB_HID=m
942−# CONFIG_USB_HIDINPUT_POWERBOOK is not set
943−# CONFIG_HID_FF is not set
944−# CONFIG_USB_HIDDEV is not set
945−
946−#
947−# USB HID Boot Protocol drivers
948−#
949−# CONFIG_USB_KBD is not set
950−# CONFIG_USB_MOUSE is not set
951−# CONFIG_USB_AIPTEK is not set
952−# CONFIG_USB_WACOM is not set
953−# CONFIG_USB_ACECAD is not set
954−# CONFIG_USB_KBTAB is not set
955−# CONFIG_USB_POWERMATE is not set
956−# CONFIG_USB_TOUCHSCREEN is not set
957−# CONFIG_USB_YEALINK is not set
958−# CONFIG_USB_XPAD is not set
959−# CONFIG_USB_ATI_REMOTE is not set
960−# CONFIG_USB_ATI_REMOTE2 is not set
961−# CONFIG_USB_KEYSPAN_REMOTE is not set
962−# CONFIG_USB_APPLETOUCH is not set
963−# CONFIG_USB_GTCO is not set
964−
965−#
966−# USB Imaging devices
967−#
968−# CONFIG_USB_MDC800 is not set
969−# CONFIG_USB_MICROTEK is not set
970−
971−#
972−# USB Network Adapters
973−#
974−# CONFIG_USB_CATC is not set
975−# CONFIG_USB_KAWETH is not set
976−# CONFIG_USB_PEGASUS is not set
977−# CONFIG_USB_RTL8150 is not set
978−# CONFIG_USB_USBNET_MII is not set
979−# CONFIG_USB_USBNET is not set
980−# CONFIG_USB_MON is not set
981−
982−#
983−# USB port drivers
984−#
985−
986−#
987−# USB Serial Converter support
988−#
989−# CONFIG_USB_SERIAL is not set
990−
991−#
992−# USB Miscellaneous drivers
993−#
994−# CONFIG_USB_EMI62 is not set
995−# CONFIG_USB_EMI26 is not set
996−# CONFIG_USB_ADUTUX is not set
997−# CONFIG_USB_AUERSWALD is not set
998−# CONFIG_USB_RIO500 is not set
999−# CONFIG_USB_LEGOTOWER is not set
1000−# CONFIG_USB_LCD is not set
1001−# CONFIG_USB_BERRY_CHARGE is not set
1002−# CONFIG_USB_LED is not set
1003−# CONFIG_USB_CYPRESS_CY7C63 is not set
1004−# CONFIG_USB_CYTHERM is not set
1005−# CONFIG_USB_PHIDGET is not set
1006−# CONFIG_USB_IDMOUSE is not set
1007−# CONFIG_USB_FTDI_ELAN is not set
1008−# CONFIG_USB_APPLEDISPLAY is not set
1009−# CONFIG_USB_SISUSBVGA is not set
1010−# CONFIG_USB_LD is not set
1011−# CONFIG_USB_TRANCEVIBRATOR is not set
1012−# CONFIG_USB_TEST is not set
1013−
1014−#
1015−# USB DSL modem support
1016−#
1017−
1018−#
1019−# USB Gadget Support
1020−#
1021−# CONFIG_USB_GADGET is not set
1022−
1023−#
1024−# MMC/SD Card support
1025−#
1026−# CONFIG_MMC is not set
1027−
1028−#
1029−# LED devices
1030−#
1031−# CONFIG_NEW_LEDS is not set
1032−
1033−#
1034−# LED drivers
1035−#
1036−
1037−#
1038−# LED Triggers
1039−#
1040−
1041−#
1042−# InfiniBand support
1043−#
1044−# CONFIG_INFINIBAND is not set
1045−
1046−#
1047−# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
1048−#
1049−
1050−#
1051−# Real Time Clock
1052−#
1053−# CONFIG_RTC_CLASS is not set
1054−
1055−#
1056−# DMA Engine support
1057−#
1058−# CONFIG_DMA_ENGINE is not set
1059−
1060−#
1061−# DMA Clients
1062−#
1063−
1064−#
1065−# DMA Devices
1066−#
1067−
1068−#
1069−# Auxiliary Display support
1070−#
1071−
1072−#
1073−# Virtualization
1074−#
1075−
1076−#
1077−# File systems
1078−#
1079−CONFIG_EXT2_FS=y
1080−# CONFIG_EXT2_FS_XATTR is not set
1081−# CONFIG_EXT2_FS_XIP is not set
1082−# CONFIG_EXT3_FS is not set
1083−# CONFIG_EXT4DEV_FS is not set
1084−# CONFIG_REISERFS_FS is not set
1085−# CONFIG_JFS_FS is not set
1086−CONFIG_FS_POSIX_ACL=y
1087−# CONFIG_XFS_FS is not set
1088−# CONFIG_GFS2_FS is not set
1089−# CONFIG_OCFS2_FS is not set
1090−# CONFIG_MINIX_FS is not set
1091−# CONFIG_ROMFS_FS is not set
1092−CONFIG_INOTIFY=y
1093−CONFIG_INOTIFY_USER=y
1094−# CONFIG_QUOTA is not set
1095−# CONFIG_DNOTIFY is not set
1096−# CONFIG_AUTOFS_FS is not set
1097−# CONFIG_AUTOFS4_FS is not set
1098−# CONFIG_FUSE_FS is not set
1099−CONFIG_GENERIC_ACL=y
1100−
1101−#
1102−# CD-ROM/DVD Filesystems
1103−#
1104−# CONFIG_ISO9660_FS is not set
1105−# CONFIG_UDF_FS is not set
1106−
1107−#
1108−# DOS/FAT/NT Filesystems
1109−#
1110−CONFIG_FAT_FS=m
1111−CONFIG_MSDOS_FS=m
1112−CONFIG_VFAT_FS=m
1113−CONFIG_FAT_DEFAULT_CODEPAGE=437
1114−CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1115−# CONFIG_NTFS_FS is not set
1116−
1117−#
1118−# Pseudo filesystems
1119−#
1120−CONFIG_PROC_FS=y
1121−CONFIG_PROC_KCORE=y
1122−CONFIG_PROC_SYSCTL=y
1123−CONFIG_SYSFS=y
1124−CONFIG_TMPFS=y
1125−CONFIG_TMPFS_POSIX_ACL=y
1126−# CONFIG_HUGETLB_PAGE is not set
1127−CONFIG_RAMFS=y
1128−CONFIG_CONFIGFS_FS=m
1129−
1130−#
1131−# Miscellaneous filesystems
1132−#
1133−# CONFIG_ADFS_FS is not set
1134−# CONFIG_AFFS_FS is not set
1135−# CONFIG_HFS_FS is not set
1136−# CONFIG_HFSPLUS_FS is not set
1137−# CONFIG_BEFS_FS is not set
1138−# CONFIG_BFS_FS is not set
1139−# CONFIG_EFS_FS is not set
1140−CONFIG_JFFS2_FS=y
1141−CONFIG_JFFS2_FS_DEBUG=0
1142−CONFIG_JFFS2_FS_WRITEBUFFER=y
1143−# CONFIG_JFFS2_SUMMARY is not set
1144−# CONFIG_JFFS2_FS_XATTR is not set
1145−# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
1146−CONFIG_JFFS2_ZLIB=y
1147−CONFIG_JFFS2_RTIME=y
1148−# CONFIG_JFFS2_RUBIN is not set
1149−# CONFIG_CRAMFS is not set
1150−# CONFIG_VXFS_FS is not set
1151−# CONFIG_HPFS_FS is not set
1152−# CONFIG_QNX4FS_FS is not set
1153−# CONFIG_SYSV_FS is not set
1154−# CONFIG_UFS_FS is not set
1155−
1156−#
1157−# Network File Systems
1158−#
1159−CONFIG_NFS_FS=y
1160−CONFIG_NFS_V3=y
1161−# CONFIG_NFS_V3_ACL is not set
1162−# CONFIG_NFS_V4 is not set
1163−# CONFIG_NFS_DIRECTIO is not set
1164−# CONFIG_NFSD is not set
1165−CONFIG_ROOT_NFS=y
1166−CONFIG_LOCKD=y
1167−CONFIG_LOCKD_V4=y
1168−CONFIG_NFS_COMMON=y
1169−CONFIG_SUNRPC=y
1170−# CONFIG_RPCSEC_GSS_KRB5 is not set
1171−# CONFIG_RPCSEC_GSS_SPKM3 is not set
1172−# CONFIG_SMB_FS is not set
1173−# CONFIG_CIFS is not set
1174−# CONFIG_NCP_FS is not set
1175−# CONFIG_CODA_FS is not set
1176−# CONFIG_AFS_FS is not set
1177−# CONFIG_9P_FS is not set
1178−
1179−#
1180−# Partition Types
1181−#
1182−CONFIG_PARTITION_ADVANCED=y
1183−# CONFIG_ACORN_PARTITION is not set
1184−# CONFIG_OSF_PARTITION is not set
1185−# CONFIG_AMIGA_PARTITION is not set
1186−# CONFIG_ATARI_PARTITION is not set
1187−# CONFIG_MAC_PARTITION is not set
1188−CONFIG_MSDOS_PARTITION=y
1189−# CONFIG_BSD_DISKLABEL is not set
1190−# CONFIG_MINIX_SUBPARTITION is not set
1191−# CONFIG_SOLARIS_X86_PARTITION is not set
1192−# CONFIG_UNIXWARE_DISKLABEL is not set
1193−# CONFIG_LDM_PARTITION is not set
1194−# CONFIG_SGI_PARTITION is not set
1195−# CONFIG_ULTRIX_PARTITION is not set
1196−# CONFIG_SUN_PARTITION is not set
1197−# CONFIG_KARMA_PARTITION is not set
1198−# CONFIG_EFI_PARTITION is not set
1199−
1200−#
1201−# Native Language Support
1202−#
1203−CONFIG_NLS=y
1204−CONFIG_NLS_DEFAULT="iso8859-1"
1205−CONFIG_NLS_CODEPAGE_437=m
1206−# CONFIG_NLS_CODEPAGE_737 is not set
1207−# CONFIG_NLS_CODEPAGE_775 is not set
1208−CONFIG_NLS_CODEPAGE_850=m
1209−# CONFIG_NLS_CODEPAGE_852 is not set
1210−# CONFIG_NLS_CODEPAGE_855 is not set
1211−# CONFIG_NLS_CODEPAGE_857 is not set
1212−# CONFIG_NLS_CODEPAGE_860 is not set
1213−# CONFIG_NLS_CODEPAGE_861 is not set
1214−# CONFIG_NLS_CODEPAGE_862 is not set
1215−# CONFIG_NLS_CODEPAGE_863 is not set
1216−# CONFIG_NLS_CODEPAGE_864 is not set
1217−# CONFIG_NLS_CODEPAGE_865 is not set
1218−# CONFIG_NLS_CODEPAGE_866 is not set
1219−# CONFIG_NLS_CODEPAGE_869 is not set
1220−# CONFIG_NLS_CODEPAGE_936 is not set
1221−# CONFIG_NLS_CODEPAGE_950 is not set
1222−# CONFIG_NLS_CODEPAGE_932 is not set
1223−# CONFIG_NLS_CODEPAGE_949 is not set
1224−# CONFIG_NLS_CODEPAGE_874 is not set
1225−# CONFIG_NLS_ISO8859_8 is not set
1226−# CONFIG_NLS_CODEPAGE_1250 is not set
1227−# CONFIG_NLS_CODEPAGE_1251 is not set
1228−# CONFIG_NLS_ASCII is not set
1229−CONFIG_NLS_ISO8859_1=m
1230−# CONFIG_NLS_ISO8859_2 is not set
1231−# CONFIG_NLS_ISO8859_3 is not set
1232−# CONFIG_NLS_ISO8859_4 is not set
1233−# CONFIG_NLS_ISO8859_5 is not set
1234−# CONFIG_NLS_ISO8859_6 is not set
1235−# CONFIG_NLS_ISO8859_7 is not set
1236−# CONFIG_NLS_ISO8859_9 is not set
1237−# CONFIG_NLS_ISO8859_13 is not set
1238−# CONFIG_NLS_ISO8859_14 is not set
1239−# CONFIG_NLS_ISO8859_15 is not set
1240−# CONFIG_NLS_KOI8_R is not set
1241−# CONFIG_NLS_KOI8_U is not set
1242−# CONFIG_NLS_UTF8 is not set
1243−
1244−#
1245−# Distributed Lock Manager
1246−#
1247−CONFIG_DLM=m
1248−CONFIG_DLM_TCP=y
1249−# CONFIG_DLM_SCTP is not set
1250−# CONFIG_DLM_DEBUG is not set
1251−
1252−#
1253−# Profiling support
1254−#
1255−# CONFIG_PROFILING is not set
1256−
1257−#
1258−# Kernel hacking
1259−#
1260−CONFIG_TRACE_IRQFLAGS_SUPPORT=y
1261−# CONFIG_PRINTK_TIME is not set
1262−CONFIG_ENABLE_MUST_CHECK=y
1263−# CONFIG_MAGIC_SYSRQ is not set
1264−# CONFIG_UNUSED_SYMBOLS is not set
1265−# CONFIG_DEBUG_FS is not set
1266−# CONFIG_HEADERS_CHECK is not set
1267−# CONFIG_DEBUG_KERNEL is not set
1268−CONFIG_LOG_BUF_SHIFT=14
1269−CONFIG_CROSSCOMPILE=y
1270−CONFIG_CMDLINE=""
1271−
1272−#
1273−# Security options
1274−#
1275−# CONFIG_KEYS is not set
1276−# CONFIG_SECURITY is not set
1277−
1278−#
1279−# Cryptographic options
1280−#
1281−CONFIG_CRYPTO=y
1282−CONFIG_CRYPTO_ALGAPI=y
1283−CONFIG_CRYPTO_BLKCIPHER=m
1284−CONFIG_CRYPTO_HASH=m
1285−CONFIG_CRYPTO_MANAGER=m
1286−# CONFIG_CRYPTO_HMAC is not set
1287−CONFIG_CRYPTO_XCBC=m
1288−# CONFIG_CRYPTO_NULL is not set
1289−# CONFIG_CRYPTO_MD4 is not set
1290−CONFIG_CRYPTO_MD5=y
1291−# CONFIG_CRYPTO_SHA1 is not set
1292−# CONFIG_CRYPTO_SHA256 is not set
1293−# CONFIG_CRYPTO_SHA512 is not set
1294−# CONFIG_CRYPTO_WP512 is not set
1295−# CONFIG_CRYPTO_TGR192 is not set
1296−CONFIG_CRYPTO_GF128MUL=m
1297−CONFIG_CRYPTO_ECB=m
1298−CONFIG_CRYPTO_CBC=m
1299−CONFIG_CRYPTO_PCBC=m
1300−CONFIG_CRYPTO_LRW=m
1301−# CONFIG_CRYPTO_DES is not set
1302−CONFIG_CRYPTO_FCRYPT=m
1303−# CONFIG_CRYPTO_BLOWFISH is not set
1304−# CONFIG_CRYPTO_TWOFISH is not set
1305−# CONFIG_CRYPTO_SERPENT is not set
1306−# CONFIG_CRYPTO_AES is not set
1307−# CONFIG_CRYPTO_CAST5 is not set
1308−# CONFIG_CRYPTO_CAST6 is not set
1309−# CONFIG_CRYPTO_TEA is not set
1310−# CONFIG_CRYPTO_ARC4 is not set
1311−# CONFIG_CRYPTO_KHAZAD is not set
1312−# CONFIG_CRYPTO_ANUBIS is not set
1313−# CONFIG_CRYPTO_DEFLATE is not set
1314−# CONFIG_CRYPTO_MICHAEL_MIC is not set
1315−# CONFIG_CRYPTO_CRC32C is not set
1316−CONFIG_CRYPTO_CAMELLIA=m
1317−# CONFIG_CRYPTO_TEST is not set
1318−
1319−#
1320−# Hardware crypto devices
1321−#
1322−
1323−#
1324−# Library routines
1325−#
1326−CONFIG_BITREVERSE=y
1327−# CONFIG_CRC_CCITT is not set
1328−# CONFIG_CRC16 is not set
1329−CONFIG_CRC32=y
1330−# CONFIG_LIBCRC32C is not set
1331−CONFIG_ZLIB_INFLATE=y
1332−CONFIG_ZLIB_DEFLATE=y
1333−CONFIG_PLIST=y
1334−CONFIG_HAS_IOMEM=y
1335−CONFIG_HAS_IOPORT=y
arch/mips/configs/fuloong2e_defconfig+62−34
@@ -1,7 +1,7 @@
11 #
22 # Automatically generated make config: don't edit
3−# Linux kernel version: 2.6.31-rc1
4−# Thu Jul 2 22:37:00 2009
3+# Linux kernel version: 2.6.32-rc4
4+# Fri Oct 16 13:18:01 2009
55 #
66 CONFIG_MIPS=y
77
@@ -10,8 +10,8 @@ CONFIG_MIPS=y · 2 unmodified lines
1010 #
1111 # CONFIG_MACH_ALCHEMY is not set
1212 # CONFIG_AR7 is not set
13−# CONFIG_BASLER_EXCITE is not set
1413 # CONFIG_BCM47XX is not set
14+# CONFIG_BCM63XX is not set
1515 # CONFIG_MIPS_COBALT is not set
1616 # CONFIG_MACH_DECSTATION is not set
1717 # CONFIG_MACH_JAZZ is not set
@@ -105,6 +105,8 @@ CONFIG_CPU_LOONGSON2E=y · 87 unmodified lines
105105 # CONFIG_CPU_RM9000 is not set
106106 # CONFIG_CPU_SB1 is not set
107107 # CONFIG_CPU_CAVIUM_OCTEON is not set
108+CONFIG_SYS_SUPPORTS_ZBOOT=y
109+CONFIG_SYS_SUPPORTS_ZBOOT_UART16550=y
108110 CONFIG_CPU_LOONGSON2=y
109111 CONFIG_SYS_HAS_CPU_LOONGSON2E=y
110112 CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
@@ -135,12 +137,16 @@ CONFIG_SYS_SUPPORTS_HIGHMEM=y · 24 unmodified lines
135137 CONFIG_ARCH_FLATMEM_ENABLE=y
136138 CONFIG_ARCH_POPULATES_NODE_MAP=y
137139 CONFIG_SELECT_MEMORY_MODEL=y
138−CONFIG_FLATMEM_MANUAL=y
140+# CONFIG_FLATMEM_MANUAL is not set
139141 # CONFIG_DISCONTIGMEM_MANUAL is not set
140−# CONFIG_SPARSEMEM_MANUAL is not set
141−CONFIG_FLATMEM=y
142−CONFIG_FLAT_NODE_MEM_MAP=y
142+CONFIG_SPARSEMEM_MANUAL=y
143+CONFIG_SPARSEMEM=y
144+CONFIG_HAVE_MEMORY_PRESENT=y
143145 CONFIG_SPARSEMEM_STATIC=y
146+
147+#
148+# Memory hotplug is currently incompatible with Software Suspend
149+#
144150 CONFIG_PAGEFLAGS_EXTENDED=y
145151 CONFIG_SPLIT_PTLOCK_CPUS=4
146152 CONFIG_PHYS_ADDR_T_64BIT=y
@@ -148,6 +154,7 @@ CONFIG_ZONE_DMA_FLAG=0 · 1 unmodified line
148154 CONFIG_VIRT_TO_BUS=y
149155 CONFIG_HAVE_MLOCK=y
150156 CONFIG_HAVE_MLOCKED_PAGE_BIT=y
157+# CONFIG_KSM is not set
151158 CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
152159 CONFIG_TICK_ONESHOT=y
153160 CONFIG_NO_HZ=y
@@ -180,6 +187,12 @@ CONFIG_BROKEN_ON_SMP=y · 26 unmodified lines
180187 CONFIG_INIT_ENV_ARG_LIMIT=32
181188 CONFIG_LOCALVERSION="-fuloong2e"
182189 # CONFIG_LOCALVERSION_AUTO is not set
190+CONFIG_HAVE_KERNEL_GZIP=y
191+CONFIG_HAVE_KERNEL_BZIP2=y
192+CONFIG_HAVE_KERNEL_LZMA=y
193+CONFIG_KERNEL_GZIP=y
194+# CONFIG_KERNEL_BZIP2 is not set
195+# CONFIG_KERNEL_LZMA is not set
183196 CONFIG_SWAP=y
184197 CONFIG_SYSVIPC=y
185198 CONFIG_SYSVIPC_SYSCTL=y
@@ -193,11 +206,12 @@ CONFIG_BSD_PROCESS_ACCT=y · 7 unmodified lines
193206 #
194207 # RCU Subsystem
195208 #
196−CONFIG_CLASSIC_RCU=y
197−# CONFIG_TREE_RCU is not set
198−# CONFIG_PREEMPT_RCU is not set
209+CONFIG_TREE_RCU=y
210+# CONFIG_TREE_PREEMPT_RCU is not set
211+# CONFIG_RCU_TRACE is not set
212+CONFIG_RCU_FANOUT=64
213+# CONFIG_RCU_FANOUT_EXACT is not set
199214 # CONFIG_TREE_RCU_TRACE is not set
200−# CONFIG_PREEMPT_RCU_TRACE is not set
201215 CONFIG_IKCONFIG=y
202216 CONFIG_IKCONFIG_PROC=y
203217 CONFIG_LOG_BUF_SHIFT=14
@@ -235,18 +249,16 @@ CONFIG_SHMEM=y · 31 unmodified lines
235249 CONFIG_AIO=y
236250
237251 #
238−# Performance Counters
252+# Kernel Performance Events And Counters
239253 #
240254 CONFIG_VM_EVENT_COUNTERS=y
241255 CONFIG_PCI_QUIRKS=y
242−# CONFIG_STRIP_ASM_SYMS is not set
243256 # CONFIG_COMPAT_BRK is not set
244257 CONFIG_SLAB=y
245258 # CONFIG_SLUB is not set
246259 # CONFIG_SLOB is not set
247260 CONFIG_PROFILING=y
248261 CONFIG_TRACEPOINTS=y
249−CONFIG_MARKERS=y
250262 CONFIG_OPROFILE=m
251263 CONFIG_HAVE_OPROFILE=y
252264 CONFIG_HAVE_SYSCALL_WRAPPERS=y
@@ -255,8 +267,8 @@ CONFIG_HAVE_SYSCALL_WRAPPERS=y · 2 unmodified lines
255267 # GCOV-based kernel profiling
256268 #
257269 # CONFIG_GCOV_KERNEL is not set
258−# CONFIG_SLOW_WORK is not set
259−# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
270+CONFIG_SLOW_WORK=y
271+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
260272 CONFIG_SLABINFO=y
261273 CONFIG_RT_MUTEXES=y
262274 CONFIG_BASE_SMALL=0
@@ -283,7 +295,7 @@ CONFIG_IOSCHED_CFQ=y · 20 unmodified lines
283295 CONFIG_DEFAULT_CFQ=y
284296 # CONFIG_DEFAULT_NOOP is not set
285297 CONFIG_DEFAULT_IOSCHED="cfq"
286−# CONFIG_FREEZER is not set
298+CONFIG_FREEZER=y
287299
288300 #
289301 # Bus options (PCI, PCMCIA, EISA, ISA, TC)
@@ -321,9 +333,14 @@ CONFIG_ARCH_HIBERNATION_POSSIBLE=y · 31 unmodified lines
321333 CONFIG_ARCH_SUSPEND_POSSIBLE=y
322334 CONFIG_PM=y
323335 # CONFIG_PM_DEBUG is not set
336+CONFIG_PM_SLEEP=y
324337 # CONFIG_SUSPEND is not set
325−# CONFIG_HIBERNATION is not set
338+CONFIG_HIBERNATION_NVS=y
339+CONFIG_HIBERNATION=y
340+CONFIG_PM_STD_PARTITION="/dev/hda3"
341+# CONFIG_PM_RUNTIME is not set
326342 CONFIG_NET=y
343+CONFIG_COMPAT_NETLINK_MESSAGES=y
327344
328345 #
329346 # Networking options
@@ -442,6 +459,7 @@ CONFIG_IP_NF_ARPFILTER=m · 112 unmodified lines
442459 CONFIG_IP_NF_ARP_MANGLE=m
443460 # CONFIG_IP_DCCP is not set
444461 # CONFIG_IP_SCTP is not set
462+# CONFIG_RDS is not set
445463 # CONFIG_TIPC is not set
446464 # CONFIG_ATM is not set
447465 # CONFIG_BRIDGE is not set
@@ -473,6 +491,7 @@ CONFIG_NET_CLS_ROUTE=y · 25 unmodified lines
473491 # CONFIG_AF_RXRPC is not set
474492 CONFIG_WIRELESS=y
475493 # CONFIG_CFG80211 is not set
494+CONFIG_CFG80211_DEFAULT_PS_VALUE=0
476495 CONFIG_WIRELESS_OLD_REGULATORY=y
477496 CONFIG_WIRELESS_EXT=y
478497 CONFIG_WIRELESS_EXT_SYSFS=y
@@ -481,7 +500,6 @@ CONFIG_WIRELESS_EXT_SYSFS=y · 2 unmodified lines
481500 #
482501 # CFG80211 needs to be enabled for MAC80211
483502 #
484−CONFIG_MAC80211_DEFAULT_PS_VALUE=0
485503 # CONFIG_WIMAX is not set
486504 # CONFIG_RFKILL is not set
487505 CONFIG_NET_9P=m
@@ -495,6 +513,7 @@ CONFIG_NET_9P=m · 7 unmodified lines
495513 # Generic Driver Options
496514 #
497515 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
516+# CONFIG_DEVTMPFS is not set
498517 CONFIG_STANDALONE=y
499518 CONFIG_PREVENT_FIRMWARE_BUILD=y
500519 CONFIG_FW_LOADER=m
@@ -504,9 +523,9 @@ CONFIG_EXTRA_FIRMWARE="" · 3 unmodified lines
504523 # CONFIG_CONNECTOR is not set
505524 CONFIG_MTD=m
506525 # CONFIG_MTD_DEBUG is not set
526+# CONFIG_MTD_TESTS is not set
507527 # CONFIG_MTD_CONCAT is not set
508528 # CONFIG_MTD_PARTITIONS is not set
509−# CONFIG_MTD_TESTS is not set
510529
511530 #
512531 # User Modules And Translation Layers
@@ -820,6 +839,7 @@ CONFIG_8139TOO=y · 307 unmodified lines
820839 # CONFIG_SUNDANCE is not set
821840 # CONFIG_TLAN is not set
822841 # CONFIG_KS8842 is not set
842+# CONFIG_KS8851_MLL is not set
823843 # CONFIG_VIA_RHINE is not set
824844 # CONFIG_SC92031 is not set
825845 # CONFIG_ATL2 is not set
@@ -867,10 +887,7 @@ CONFIG_CHELSIO_T3_DEPENDS=y · 41 unmodified lines
867887 # CONFIG_SFC is not set
868888 # CONFIG_BE2NET is not set
869889 # CONFIG_TR is not set
870−
871−#
872−# Wireless LAN
873−#
890+CONFIG_WLAN=y
874891 # CONFIG_WLAN_PRE80211 is not set
875892 # CONFIG_WLAN_80211 is not set
876893
@@ -886,6 +903,7 @@ CONFIG_CHELSIO_T3_DEPENDS=y · 9 unmodified lines
886903 # CONFIG_USB_PEGASUS is not set
887904 # CONFIG_USB_RTL8150 is not set
888905 # CONFIG_USB_USBNET is not set
906+# CONFIG_USB_CDC_PHONET is not set
889907 # CONFIG_WAN is not set
890908 # CONFIG_FDDI is not set
891909 # CONFIG_HIPPI is not set
@@ -933,12 +951,16 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 · 41 unmodified lines
933951 # Input Device Drivers
934952 #
935953 CONFIG_INPUT_KEYBOARD=y
954+# CONFIG_KEYBOARD_ADP5588 is not set
936955 CONFIG_KEYBOARD_ATKBD=y
937−# CONFIG_KEYBOARD_SUNKBD is not set
956+# CONFIG_QT2160 is not set
938957 # CONFIG_KEYBOARD_LKKBD is not set
939−# CONFIG_KEYBOARD_XTKBD is not set
958+# CONFIG_KEYBOARD_MAX7359 is not set
940959 # CONFIG_KEYBOARD_NEWTON is not set
960+# CONFIG_KEYBOARD_OPENCORES is not set
941961 # CONFIG_KEYBOARD_STOWAWAY is not set
962+# CONFIG_KEYBOARD_SUNKBD is not set
963+# CONFIG_KEYBOARD_XTKBD is not set
942964 CONFIG_INPUT_MOUSE=y
943965 CONFIG_MOUSE_PS2=y
944966 CONFIG_MOUSE_PS2_ALPS=y
@@ -946,6 +968,7 @@ CONFIG_MOUSE_PS2_LOGIPS2PP=y · 1 unmodified line
946968 CONFIG_MOUSE_PS2_SYNAPTICS=y
947969 CONFIG_MOUSE_PS2_TRACKPOINT=y
948970 # CONFIG_MOUSE_PS2_ELANTECH is not set
971+# CONFIG_MOUSE_PS2_SENTELIC is not set
949972 # CONFIG_MOUSE_PS2_TOUCHKIT is not set
950973 CONFIG_MOUSE_SERIAL=y
951974 # CONFIG_MOUSE_APPLETOUCH is not set
@@ -1015,6 +1038,7 @@ CONFIG_RTC=y · 63 unmodified lines
10151038 CONFIG_DEVPORT=y
10161039 CONFIG_I2C=m
10171040 CONFIG_I2C_BOARDINFO=y
1041+CONFIG_I2C_COMPAT=y
10181042 CONFIG_I2C_CHARDEV=m
10191043 CONFIG_I2C_HELPER_AUTO=y
10201044
@@ -1070,9 +1094,6 @@ CONFIG_I2C_VIAPRO=m · 49 unmodified lines
10701094 # Miscellaneous I2C Chip support
10711095 #
10721096 # CONFIG_DS1682 is not set
1073−# CONFIG_SENSORS_PCF8574 is not set
1074−# CONFIG_PCF8575 is not set
1075−# CONFIG_SENSORS_PCA9539 is not set
10761097 # CONFIG_SENSORS_TSL2550 is not set
10771098 # CONFIG_I2C_DEBUG_CORE is not set
10781099 # CONFIG_I2C_DEBUG_ALGO is not set
@@ -1088,7 +1109,6 @@ CONFIG_I2C_VIAPRO=m · 9 unmodified lines
10881109 # CONFIG_POWER_SUPPLY is not set
10891110 # CONFIG_HWMON is not set
10901111 # CONFIG_THERMAL is not set
1091−# CONFIG_THERMAL_HWMON is not set
10921112 # CONFIG_WATCHDOG is not set
10931113 CONFIG_SSB_POSSIBLE=y
10941114
@@ -1105,6 +1125,7 @@ CONFIG_SSB_POSSIBLE=y · 10 unmodified lines
11051125 # CONFIG_HTC_PASIC3 is not set
11061126 # CONFIG_MFD_TMIO is not set
11071127 # CONFIG_MFD_WM8400 is not set
1128+# CONFIG_MFD_WM831X is not set
11081129 # CONFIG_MFD_WM8350_I2C is not set
11091130 # CONFIG_MFD_PCF50633 is not set
11101131 # CONFIG_AB3100_CORE is not set
@@ -1114,6 +1135,7 @@ CONFIG_SSB_POSSIBLE=y · 3 unmodified lines
11141135 #
11151136 # Graphics support
11161137 #
1138+CONFIG_VGA_ARB=y
11171139 # CONFIG_DRM is not set
11181140 # CONFIG_VGASTATE is not set
11191141 CONFIG_VIDEO_OUTPUT_CONTROL=m
@@ -1198,6 +1220,7 @@ CONFIG_FONT_8x16=y · 78 unmodified lines
11981220 # CONFIG_LOGO is not set
11991221 CONFIG_SOUND=y
12001222 CONFIG_SOUND_OSS_CORE=y
1223+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
12011224 CONFIG_SND=m
12021225 CONFIG_SND_TIMER=m
12031226 CONFIG_SND_PCM=m
@@ -1304,7 +1327,6 @@ CONFIG_SND_USB=y · 100 unmodified lines
13041327 CONFIG_AC97_BUS=m
13051328 CONFIG_HID_SUPPORT=y
13061329 CONFIG_HID=y
1307−# CONFIG_HID_DEBUG is not set
13081330 CONFIG_HIDRAW=y
13091331
13101332 #
@@ -1356,6 +1378,7 @@ CONFIG_USB_EHCI_TT_NEWSCHED=y · 45 unmodified lines
13561378 # CONFIG_USB_OXU210HP_HCD is not set
13571379 # CONFIG_USB_ISP116X_HCD is not set
13581380 CONFIG_USB_ISP1760_HCD=m
1381+# CONFIG_USB_ISP1362_HCD is not set
13591382 CONFIG_USB_OHCI_HCD=y
13601383 # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
13611384 # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
@@ -1453,6 +1476,7 @@ CONFIG_UIO_CIF=m · 91 unmodified lines
14531476 # CONFIG_UIO_SMX is not set
14541477 # CONFIG_UIO_AEC is not set
14551478 # CONFIG_UIO_SERCOS3 is not set
1479+# CONFIG_UIO_PCI_GENERIC is not set
14561480
14571481 #
14581482 # TI VLYNQ
@@ -1469,10 +1493,10 @@ CONFIG_EXT3_FS=y · 10 unmodified lines
14691493 # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
14701494 # CONFIG_EXT3_FS_XATTR is not set
14711495 CONFIG_EXT4_FS=m
1472−CONFIG_EXT4DEV_COMPAT=y
14731496 CONFIG_EXT4_FS_XATTR=y
14741497 CONFIG_EXT4_FS_POSIX_ACL=y
14751498 CONFIG_EXT4_FS_SECURITY=y
1499+# CONFIG_EXT4_DEBUG is not set
14761500 CONFIG_FS_XIP=y
14771501 CONFIG_JBD=y
14781502 # CONFIG_JBD_DEBUG is not set
@@ -1489,6 +1513,7 @@ CONFIG_FS_POSIX_ACL=y · 10 unmodified lines
14891513 # CONFIG_GFS2_FS is not set
14901514 # CONFIG_OCFS2_FS is not set
14911515 # CONFIG_BTRFS_FS is not set
1516+# CONFIG_NILFS2_FS is not set
14921517 CONFIG_FILE_LOCKING=y
14931518 CONFIG_FSNOTIFY=y
14941519 CONFIG_DNOTIFY=y
@@ -1557,7 +1582,6 @@ CONFIG_OMFS_FS=m · 62 unmodified lines
15571582 # CONFIG_ROMFS_FS is not set
15581583 # CONFIG_SYSV_FS is not set
15591584 # CONFIG_UFS_FS is not set
1560−# CONFIG_NILFS2_FS is not set
15611585 CONFIG_NETWORK_FILESYSTEMS=y
15621586 CONFIG_NFS_FS=m
15631587 CONFIG_NFS_V3=y
@@ -1666,6 +1690,7 @@ CONFIG_ENABLE_WARN_DEPRECATED=y · 102 unmodified lines
16661690 # CONFIG_ENABLE_MUST_CHECK is not set
16671691 CONFIG_FRAME_WARN=2048
16681692 # CONFIG_MAGIC_SYSRQ is not set
1693+# CONFIG_STRIP_ASM_SYMS is not set
16691694 # CONFIG_UNUSED_SYMBOLS is not set
16701695 CONFIG_DEBUG_FS=y
16711696 # CONFIG_HEADERS_CHECK is not set
@@ -1678,13 +1703,14 @@ CONFIG_NOP_TRACER=y · 6 unmodified lines
16781703 CONFIG_RING_BUFFER=y
16791704 CONFIG_EVENT_TRACING=y
16801705 CONFIG_CONTEXT_SWITCH_TRACER=y
1706+CONFIG_RING_BUFFER_ALLOW_SWAP=y
16811707 CONFIG_TRACING=y
16821708 CONFIG_TRACING_SUPPORT=y
16831709 # CONFIG_FTRACE is not set
16841710 # CONFIG_DYNAMIC_DEBUG is not set
16851711 # CONFIG_SAMPLES is not set
16861712 CONFIG_HAVE_ARCH_KGDB=y
1687−CONFIG_CMDLINE=""
1713+# CONFIG_CMDLINE_BOOL is not set
16881714
16891715 #
16901716 # Security options
@@ -1742,11 +1768,13 @@ CONFIG_CRYPTO_XTS=m · 51 unmodified lines
17421768 #
17431769 CONFIG_CRYPTO_HMAC=y
17441770 # CONFIG_CRYPTO_XCBC is not set
1771+# CONFIG_CRYPTO_VMAC is not set
17451772
17461773 #
17471774 # Digest
17481775 #
17491776 # CONFIG_CRYPTO_CRC32C is not set
1777+CONFIG_CRYPTO_GHASH=m
17501778 # CONFIG_CRYPTO_MD4 is not set
17511779 CONFIG_CRYPTO_MD5=m
17521780 # CONFIG_CRYPTO_MICHAEL_MIC is not set
arch/mips/configs/ip22_defconfig+1−2
@@ -9,7 +9,6 @@ CONFIG_MIPS=y · 8 unmodified lines
99 # Machine selection
1010 #
1111 # CONFIG_MACH_ALCHEMY is not set
12−# CONFIG_BASLER_EXCITE is not set
1312 # CONFIG_BCM47XX is not set
1413 # CONFIG_MIPS_COBALT is not set
1514 # CONFIG_MACH_DECSTATION is not set
@@ -1188,7 +1187,7 @@ CONFIG_DEBUG_MEMORY_INIT=y · 1172 unmodified lines
11881187 CONFIG_DYNAMIC_PRINTK_DEBUG=y
11891188 # CONFIG_SAMPLES is not set
11901189 CONFIG_HAVE_ARCH_KGDB=y
1191−CONFIG_CMDLINE=""
1190+# CONFIG_CMDLINE_BOOL is not set
11921191
11931192 #
11941193 # Security options
arch/mips/configs/ip27_defconfig+1−2
@@ -9,7 +9,6 @@ CONFIG_MIPS=y · 8 unmodified lines
99 # Machine selection
1010 #
1111 # CONFIG_MACH_ALCHEMY is not set
12−# CONFIG_BASLER_EXCITE is not set
1312 # CONFIG_MIPS_COBALT is not set
1413 # CONFIG_MACH_DECSTATION is not set
1514 # CONFIG_MACH_JAZZ is not set
@@ -940,7 +939,7 @@ CONFIG_ENABLE_MUST_CHECK=y · 924 unmodified lines
940939 # CONFIG_HEADERS_CHECK is not set
941940 # CONFIG_DEBUG_KERNEL is not set
942941 CONFIG_CROSSCOMPILE=y
943−CONFIG_CMDLINE=""
942+# CONFIG_CMDLINE_BOOL is not set
944943
945944 #
946945 # Security options
arch/mips/configs/ip28_defconfig+1−2
@@ -9,7 +9,6 @@ CONFIG_MIPS=y · 8 unmodified lines
99 # Machine selection
1010 #
1111 # CONFIG_MACH_ALCHEMY is not set
12−# CONFIG_BASLER_EXCITE is not set
1312 # CONFIG_BCM47XX is not set
1413 # CONFIG_MIPS_COBALT is not set
1514 # CONFIG_MACH_DECSTATION is not set
@@ -816,7 +815,7 @@ CONFIG_MAGIC_SYSRQ=y · 800 unmodified lines
816815 # CONFIG_HEADERS_CHECK is not set
817816 # CONFIG_DEBUG_KERNEL is not set
818817 # CONFIG_SAMPLES is not set
819−CONFIG_CMDLINE=""
818+# CONFIG_CMDLINE_BOOL is not set
820819
821820 #
822821 # Security options
arch/mips/configs/ip32_defconfig+1−2
@@ -9,7 +9,6 @@ CONFIG_MIPS=y · 8 unmodified lines
99 # Machine selection
1010 #
1111 # CONFIG_MACH_ALCHEMY is not set
12−# CONFIG_BASLER_EXCITE is not set
1312 # CONFIG_BCM47XX is not set
1413 # CONFIG_MIPS_COBALT is not set
1514 # CONFIG_MACH_DECSTATION is not set
@@ -1126,7 +1125,7 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y · 1110 unmodified lines
11261125 # CONFIG_DYNAMIC_PRINTK_DEBUG is not set
11271126 # CONFIG_SAMPLES is not set
11281127 CONFIG_HAVE_ARCH_KGDB=y
1129−CONFIG_CMDLINE=""
1128+# CONFIG_CMDLINE_BOOL is not set
11301129
11311130 #
11321131 # Security options
arch/mips/configs/jazz_defconfig+1−2
@@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y · 21 unmodified lines
2222 # CONFIG_MIPS_DB1550 is not set
2323 # CONFIG_MIPS_DB1200 is not set
2424 # CONFIG_MIPS_MIRAGE is not set
25−# CONFIG_BASLER_EXCITE is not set
2625 # CONFIG_MIPS_COBALT is not set
2726 # CONFIG_MACH_DECSTATION is not set
2827 CONFIG_MACH_JAZZ=y
@@ -1374,7 +1373,7 @@ CONFIG_ENABLE_MUST_CHECK=y · 1345 unmodified lines
13741373 # CONFIG_DEBUG_KERNEL is not set
13751374 CONFIG_LOG_BUF_SHIFT=14
13761375 CONFIG_CROSSCOMPILE=y
1377−CONFIG_CMDLINE=""
1376+# CONFIG_CMDLINE_BOOL is not set
13781377
13791378 #
13801379 # Security options
arch/mips/configs/jmr3927_defconfig+1−2
@@ -9,7 +9,6 @@ CONFIG_MIPS=y · 8 unmodified lines
99 # Machine selection
1010 #
1111 # CONFIG_MACH_ALCHEMY is not set
12−# CONFIG_BASLER_EXCITE is not set
1312 # CONFIG_BCM47XX is not set
1413 # CONFIG_MIPS_COBALT is not set
1514 # CONFIG_MACH_DECSTATION is not set
@@ -835,7 +834,7 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y · 819 unmodified lines
835834 # CONFIG_DYNAMIC_PRINTK_DEBUG is not set
836835 # CONFIG_SAMPLES is not set
837836 CONFIG_HAVE_ARCH_KGDB=y
838−CONFIG_CMDLINE=""
837+# CONFIG_CMDLINE_BOOL is not set
839838
840839 #
841840 # Security options
arch/mips/configs/lasat_defconfig+1−2
@@ -9,7 +9,6 @@ CONFIG_MIPS=y · 8 unmodified lines
99 # Machine selection
1010 #
1111 # CONFIG_MACH_ALCHEMY is not set
12−# CONFIG_BASLER_EXCITE is not set
1312 # CONFIG_MIPS_COBALT is not set
1413 # CONFIG_MACH_DECSTATION is not set
1514 # CONFIG_MACH_JAZZ is not set
@@ -798,7 +797,7 @@ CONFIG_MAGIC_SYSRQ=y · 782 unmodified lines
798797 # CONFIG_HEADERS_CHECK is not set
799798 # CONFIG_DEBUG_KERNEL is not set
800799 CONFIG_CROSSCOMPILE=y
801−CONFIG_CMDLINE=""
800+# CONFIG_CMDLINE_BOOL is not set
802801
803802 #
804803 # Security options
arch/mips/configs/lemote2f_defconfig+1835−0
@@ -0,0 +1,1835 @@
1+#
2+# Automatically generated make config: don't edit
3+# Linux kernel version: 2.6.32-rc6
4+# Mon Nov 9 23:42:42 2009
5+#
6+CONFIG_MIPS=y
7+
8+#
9+# Machine selection
10+#
11+# CONFIG_MACH_ALCHEMY is not set
12+# CONFIG_AR7 is not set
13+# CONFIG_BCM47XX is not set
14+# CONFIG_BCM63XX is not set
15+# CONFIG_MIPS_COBALT is not set
16+# CONFIG_MACH_DECSTATION is not set
17+# CONFIG_MACH_JAZZ is not set
18+# CONFIG_LASAT is not set
19+CONFIG_MACH_LOONGSON=y
20+# CONFIG_MIPS_MALTA is not set
21+# CONFIG_MIPS_SIM is not set
22+# CONFIG_NEC_MARKEINS is not set
23+# CONFIG_MACH_VR41XX is not set
24+# CONFIG_NXP_STB220 is not set
25+# CONFIG_NXP_STB225 is not set
26+# CONFIG_PNX8550_JBS is not set
27+# CONFIG_PNX8550_STB810 is not set
28+# CONFIG_PMC_MSP is not set
29+# CONFIG_PMC_YOSEMITE is not set
30+# CONFIG_SGI_IP22 is not set
31+# CONFIG_SGI_IP27 is not set
32+# CONFIG_SGI_IP28 is not set
33+# CONFIG_SGI_IP32 is not set
34+# CONFIG_SIBYTE_CRHINE is not set
35+# CONFIG_SIBYTE_CARMEL is not set
36+# CONFIG_SIBYTE_CRHONE is not set
37+# CONFIG_SIBYTE_RHONE is not set
38+# CONFIG_SIBYTE_SWARM is not set
39+# CONFIG_SIBYTE_LITTLESUR is not set
40+# CONFIG_SIBYTE_SENTOSA is not set
41+# CONFIG_SIBYTE_BIGSUR is not set
42+# CONFIG_SNI_RM is not set
43+# CONFIG_MACH_TX39XX is not set
44+# CONFIG_MACH_TX49XX is not set
45+# CONFIG_MIKROTIK_RB532 is not set
46+# CONFIG_WR_PPMC is not set
47+# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
48+# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
49+# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
50+CONFIG_ARCH_SPARSEMEM_ENABLE=y
51+# CONFIG_LEMOTE_FULOONG2E is not set
52+CONFIG_LEMOTE_MACH2F=y
53+CONFIG_CS5536=y
54+CONFIG_RWSEM_GENERIC_SPINLOCK=y
55+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
56+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
57+CONFIG_ARCH_SUPPORTS_OPROFILE=y
58+CONFIG_GENERIC_FIND_NEXT_BIT=y
59+CONFIG_GENERIC_HWEIGHT=y
60+CONFIG_GENERIC_CALIBRATE_DELAY=y
61+CONFIG_GENERIC_CLOCKEVENTS=y
62+CONFIG_GENERIC_TIME=y
63+CONFIG_GENERIC_CMOS_UPDATE=y
64+CONFIG_SCHED_OMIT_FRAME_POINTER=y
65+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
66+CONFIG_CEVT_R4K_LIB=y
67+CONFIG_CEVT_R4K=y
68+CONFIG_CSRC_R4K_LIB=y
69+CONFIG_CSRC_R4K=y
70+CONFIG_DMA_NONCOHERENT=y
71+CONFIG_DMA_NEED_PCI_MAP_STATE=y
72+CONFIG_EARLY_PRINTK=y
73+CONFIG_SYS_HAS_EARLY_PRINTK=y
74+CONFIG_I8259=y
75+# CONFIG_NO_IOPORT is not set
76+CONFIG_GENERIC_ISA_DMA=y
77+CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN=y
78+# CONFIG_CPU_BIG_ENDIAN is not set
79+CONFIG_CPU_LITTLE_ENDIAN=y
80+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
81+CONFIG_IRQ_CPU=y
82+CONFIG_BOOT_ELF32=y
83+CONFIG_MIPS_L1_CACHE_SHIFT=5
84+
85+#
86+# CPU selection
87+#
88+# CONFIG_CPU_LOONGSON2E is not set
89+CONFIG_CPU_LOONGSON2F=y
90+# CONFIG_CPU_MIPS32_R1 is not set
91+# CONFIG_CPU_MIPS32_R2 is not set
92+# CONFIG_CPU_MIPS64_R1 is not set
93+# CONFIG_CPU_MIPS64_R2 is not set
94+# CONFIG_CPU_R3000 is not set
95+# CONFIG_CPU_TX39XX is not set
96+# CONFIG_CPU_VR41XX is not set
97+# CONFIG_CPU_R4300 is not set
98+# CONFIG_CPU_R4X00 is not set
99+# CONFIG_CPU_TX49XX is not set
100+# CONFIG_CPU_R5000 is not set
101+# CONFIG_CPU_R5432 is not set
102+# CONFIG_CPU_R5500 is not set
103+# CONFIG_CPU_R6000 is not set
104+# CONFIG_CPU_NEVADA is not set
105+# CONFIG_CPU_R8000 is not set
106+# CONFIG_CPU_R10000 is not set
107+# CONFIG_CPU_RM7000 is not set
108+# CONFIG_CPU_RM9000 is not set
109+# CONFIG_CPU_SB1 is not set
110+# CONFIG_CPU_CAVIUM_OCTEON is not set
111+CONFIG_SYS_SUPPORTS_ZBOOT=y
112+CONFIG_SYS_SUPPORTS_ZBOOT_UART16550=y
113+CONFIG_CPU_LOONGSON2=y
114+CONFIG_SYS_HAS_CPU_LOONGSON2F=y
115+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
116+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
117+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
118+CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
119+
120+#
121+# Kernel type
122+#
123+# CONFIG_32BIT is not set
124+CONFIG_64BIT=y
125+# CONFIG_PAGE_SIZE_4KB is not set
126+# CONFIG_PAGE_SIZE_8KB is not set
127+CONFIG_PAGE_SIZE_16KB=y
128+# CONFIG_PAGE_SIZE_32KB is not set
129+# CONFIG_PAGE_SIZE_64KB is not set
130+CONFIG_BOARD_SCACHE=y
131+CONFIG_MIPS_MT_DISABLED=y
132+# CONFIG_MIPS_MT_SMP is not set
133+# CONFIG_MIPS_MT_SMTC is not set
134+CONFIG_CPU_HAS_WB=y
135+CONFIG_CPU_HAS_SYNC=y
136+CONFIG_GENERIC_HARDIRQS=y
137+CONFIG_GENERIC_IRQ_PROBE=y
138+CONFIG_CPU_SUPPORTS_HIGHMEM=y
139+CONFIG_SYS_SUPPORTS_HIGHMEM=y
140+CONFIG_ARCH_FLATMEM_ENABLE=y
141+CONFIG_ARCH_POPULATES_NODE_MAP=y
142+CONFIG_SELECT_MEMORY_MODEL=y
143+# CONFIG_FLATMEM_MANUAL is not set
144+# CONFIG_DISCONTIGMEM_MANUAL is not set
145+CONFIG_SPARSEMEM_MANUAL=y
146+CONFIG_SPARSEMEM=y
147+CONFIG_HAVE_MEMORY_PRESENT=y
148+CONFIG_SPARSEMEM_STATIC=y
149+
150+#
151+# Memory hotplug is currently incompatible with Software Suspend
152+#
153+CONFIG_PAGEFLAGS_EXTENDED=y
154+CONFIG_SPLIT_PTLOCK_CPUS=4
155+CONFIG_PHYS_ADDR_T_64BIT=y
156+CONFIG_ZONE_DMA_FLAG=0
157+CONFIG_VIRT_TO_BUS=y
158+CONFIG_HAVE_MLOCK=y
159+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
160+# CONFIG_KSM is not set
161+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
162+CONFIG_TICK_ONESHOT=y
163+CONFIG_NO_HZ=y
164+CONFIG_HIGH_RES_TIMERS=y
165+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
166+# CONFIG_HZ_48 is not set
167+# CONFIG_HZ_100 is not set
168+# CONFIG_HZ_128 is not set
169+CONFIG_HZ_250=y
170+# CONFIG_HZ_256 is not set
171+# CONFIG_HZ_1000 is not set
172+# CONFIG_HZ_1024 is not set
173+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
174+CONFIG_HZ=250
175+# CONFIG_PREEMPT_NONE is not set
176+# CONFIG_PREEMPT_VOLUNTARY is not set
177+CONFIG_PREEMPT=y
178+# CONFIG_KEXEC is not set
179+# CONFIG_SECCOMP is not set
180+CONFIG_LOCKDEP_SUPPORT=y
181+CONFIG_STACKTRACE_SUPPORT=y
182+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
183+CONFIG_CONSTRUCTORS=y
184+
185+#
186+# General setup
187+#
188+CONFIG_EXPERIMENTAL=y
189+CONFIG_BROKEN_ON_SMP=y
190+CONFIG_LOCK_KERNEL=y
191+CONFIG_INIT_ENV_ARG_LIMIT=32
192+CONFIG_LOCALVERSION=""
193+# CONFIG_LOCALVERSION_AUTO is not set
194+CONFIG_HAVE_KERNEL_GZIP=y
195+CONFIG_HAVE_KERNEL_BZIP2=y
196+CONFIG_HAVE_KERNEL_LZMA=y
197+# CONFIG_KERNEL_GZIP is not set
198+# CONFIG_KERNEL_BZIP2 is not set
199+CONFIG_KERNEL_LZMA=y
200+CONFIG_SWAP=y
201+CONFIG_SYSVIPC=y
202+CONFIG_SYSVIPC_SYSCTL=y
203+# CONFIG_POSIX_MQUEUE is not set
204+CONFIG_BSD_PROCESS_ACCT=y
205+CONFIG_BSD_PROCESS_ACCT_V3=y
206+# CONFIG_TASKSTATS is not set
207+CONFIG_AUDIT=y
208+
209+#
210+# RCU Subsystem
211+#
212+CONFIG_TREE_RCU=y
213+# CONFIG_TREE_PREEMPT_RCU is not set
214+# CONFIG_RCU_TRACE is not set
215+CONFIG_RCU_FANOUT=64
216+# CONFIG_RCU_FANOUT_EXACT is not set
217+# CONFIG_TREE_RCU_TRACE is not set
218+CONFIG_IKCONFIG=y
219+CONFIG_IKCONFIG_PROC=y
220+CONFIG_LOG_BUF_SHIFT=15
221+# CONFIG_GROUP_SCHED is not set
222+# CONFIG_CGROUPS is not set
223+CONFIG_SYSFS_DEPRECATED=y
224+CONFIG_SYSFS_DEPRECATED_V2=y
225+# CONFIG_RELAY is not set
226+# CONFIG_NAMESPACES is not set
227+# CONFIG_BLK_DEV_INITRD is not set
228+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
229+CONFIG_SYSCTL=y
230+CONFIG_ANON_INODES=y
231+CONFIG_EMBEDDED=y
232+CONFIG_SYSCTL_SYSCALL=y
233+CONFIG_KALLSYMS=y
234+# CONFIG_KALLSYMS_EXTRA_PASS is not set
235+CONFIG_HOTPLUG=y
236+CONFIG_PRINTK=y
237+CONFIG_BUG=y
238+CONFIG_ELF_CORE=y
239+CONFIG_PCSPKR_PLATFORM=y
240+CONFIG_BASE_FULL=y
241+CONFIG_FUTEX=y
242+CONFIG_EPOLL=y
243+CONFIG_SIGNALFD=y
244+CONFIG_TIMERFD=y
245+CONFIG_EVENTFD=y
246+CONFIG_SHMEM=y
247+CONFIG_AIO=y
248+
249+#
250+# Kernel Performance Events And Counters
251+#
252+CONFIG_VM_EVENT_COUNTERS=y
253+CONFIG_PCI_QUIRKS=y
254+CONFIG_SLUB_DEBUG=y
255+CONFIG_COMPAT_BRK=y
256+# CONFIG_SLAB is not set
257+CONFIG_SLUB=y
258+# CONFIG_SLOB is not set
259+# CONFIG_PROFILING is not set
260+CONFIG_HAVE_OPROFILE=y
261+CONFIG_HAVE_SYSCALL_WRAPPERS=y
262+
263+#
264+# GCOV-based kernel profiling
265+#
266+# CONFIG_SLOW_WORK is not set
267+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
268+CONFIG_SLABINFO=y
269+CONFIG_RT_MUTEXES=y
270+CONFIG_BASE_SMALL=0
271+CONFIG_MODULES=y
272+# CONFIG_MODULE_FORCE_LOAD is not set
273+CONFIG_MODULE_UNLOAD=y
274+# CONFIG_MODULE_FORCE_UNLOAD is not set
275+CONFIG_MODVERSIONS=y
276+# CONFIG_MODULE_SRCVERSION_ALL is not set
277+CONFIG_BLOCK=y
278+CONFIG_BLK_DEV_BSG=y
279+CONFIG_BLK_DEV_INTEGRITY=y
280+CONFIG_BLOCK_COMPAT=y
281+
282+#
283+# IO Schedulers
284+#
285+CONFIG_IOSCHED_NOOP=y
286+CONFIG_IOSCHED_AS=y
287+CONFIG_IOSCHED_DEADLINE=y
288+CONFIG_IOSCHED_CFQ=y
289+# CONFIG_DEFAULT_AS is not set
290+# CONFIG_DEFAULT_DEADLINE is not set
291+CONFIG_DEFAULT_CFQ=y
292+# CONFIG_DEFAULT_NOOP is not set
293+CONFIG_DEFAULT_IOSCHED="cfq"
294+CONFIG_FREEZER=y
295+
296+#
297+# Bus options (PCI, PCMCIA, EISA, ISA, TC)
298+#
299+CONFIG_HW_HAS_PCI=y
300+CONFIG_PCI=y
301+CONFIG_PCI_DOMAINS=y
302+# CONFIG_ARCH_SUPPORTS_MSI is not set
303+CONFIG_PCI_LEGACY=y
304+# CONFIG_PCI_STUB is not set
305+# CONFIG_PCI_IOV is not set
306+CONFIG_ISA=y
307+CONFIG_MMU=y
308+# CONFIG_PCCARD is not set
309+# CONFIG_HOTPLUG_PCI is not set
310+
311+#
312+# Executable file formats
313+#
314+CONFIG_BINFMT_ELF=y
315+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
316+# CONFIG_HAVE_AOUT is not set
317+# CONFIG_BINFMT_MISC is not set
318+CONFIG_MIPS32_COMPAT=y
319+CONFIG_COMPAT=y
320+CONFIG_SYSVIPC_COMPAT=y
321+CONFIG_MIPS32_O32=y
322+CONFIG_MIPS32_N32=y
323+CONFIG_BINFMT_ELF32=y
324+
325+#
326+# Power management options
327+#
328+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
329+CONFIG_ARCH_SUSPEND_POSSIBLE=y
330+CONFIG_PM=y
331+# CONFIG_PM_DEBUG is not set
332+CONFIG_PM_SLEEP=y
333+CONFIG_SUSPEND=y
334+CONFIG_SUSPEND_FREEZER=y
335+CONFIG_HIBERNATION_NVS=y
336+CONFIG_HIBERNATION=y
337+CONFIG_PM_STD_PARTITION="/dev/hda3"
338+# CONFIG_PM_RUNTIME is not set
339+CONFIG_NET=y
340+CONFIG_COMPAT_NETLINK_MESSAGES=y
341+
342+#
343+# Networking options
344+#
345+CONFIG_PACKET=y
346+CONFIG_PACKET_MMAP=y
347+CONFIG_UNIX=y
348+CONFIG_XFRM=y
349+# CONFIG_XFRM_USER is not set
350+# CONFIG_XFRM_SUB_POLICY is not set
351+# CONFIG_XFRM_MIGRATE is not set
352+# CONFIG_XFRM_STATISTICS is not set
353+# CONFIG_NET_KEY is not set
354+CONFIG_INET=y
355+CONFIG_IP_MULTICAST=y
356+CONFIG_IP_ADVANCED_ROUTER=y
357+CONFIG_ASK_IP_FIB_HASH=y
358+# CONFIG_IP_FIB_TRIE is not set
359+CONFIG_IP_FIB_HASH=y
360+CONFIG_IP_MULTIPLE_TABLES=y
361+CONFIG_IP_ROUTE_MULTIPATH=y
362+CONFIG_IP_ROUTE_VERBOSE=y
363+# CONFIG_IP_PNP is not set
364+# CONFIG_NET_IPIP is not set
365+# CONFIG_NET_IPGRE is not set
366+CONFIG_IP_MROUTE=y
367+CONFIG_IP_PIMSM_V1=y
368+CONFIG_IP_PIMSM_V2=y
369+# CONFIG_ARPD is not set
370+CONFIG_SYN_COOKIES=y
371+# CONFIG_INET_AH is not set
372+# CONFIG_INET_ESP is not set
373+# CONFIG_INET_IPCOMP is not set
374+# CONFIG_INET_XFRM_TUNNEL is not set
375+CONFIG_INET_TUNNEL=m
376+CONFIG_INET_XFRM_MODE_TRANSPORT=m
377+CONFIG_INET_XFRM_MODE_TUNNEL=m
378+CONFIG_INET_XFRM_MODE_BEET=m
379+CONFIG_INET_LRO=y
380+CONFIG_INET_DIAG=y
381+CONFIG_INET_TCP_DIAG=y
382+CONFIG_TCP_CONG_ADVANCED=y
383+CONFIG_TCP_CONG_BIC=y
384+CONFIG_TCP_CONG_CUBIC=y
385+CONFIG_TCP_CONG_WESTWOOD=m
386+CONFIG_TCP_CONG_HTCP=m
387+# CONFIG_TCP_CONG_HSTCP is not set
388+# CONFIG_TCP_CONG_HYBLA is not set
389+# CONFIG_TCP_CONG_VEGAS is not set
390+# CONFIG_TCP_CONG_SCALABLE is not set
391+# CONFIG_TCP_CONG_LP is not set
392+# CONFIG_TCP_CONG_VENO is not set
393+# CONFIG_TCP_CONG_YEAH is not set
394+# CONFIG_TCP_CONG_ILLINOIS is not set
395+CONFIG_DEFAULT_BIC=y
396+# CONFIG_DEFAULT_CUBIC is not set
397+# CONFIG_DEFAULT_HTCP is not set
398+# CONFIG_DEFAULT_VEGAS is not set
399+# CONFIG_DEFAULT_WESTWOOD is not set
400+# CONFIG_DEFAULT_RENO is not set
401+CONFIG_DEFAULT_TCP_CONG="bic"
402+# CONFIG_TCP_MD5SIG is not set
403+CONFIG_IPV6=m
404+CONFIG_IPV6_PRIVACY=y
405+# CONFIG_IPV6_ROUTER_PREF is not set
406+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
407+# CONFIG_INET6_AH is not set
408+# CONFIG_INET6_ESP is not set
409+# CONFIG_INET6_IPCOMP is not set
410+# CONFIG_IPV6_MIP6 is not set
411+# CONFIG_INET6_XFRM_TUNNEL is not set
412+# CONFIG_INET6_TUNNEL is not set
413+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
414+CONFIG_INET6_XFRM_MODE_TUNNEL=m
415+CONFIG_INET6_XFRM_MODE_BEET=m
416+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
417+CONFIG_IPV6_SIT=m
418+CONFIG_IPV6_NDISC_NODETYPE=y
419+# CONFIG_IPV6_TUNNEL is not set
420+# CONFIG_IPV6_MULTIPLE_TABLES is not set
421+# CONFIG_IPV6_MROUTE is not set
422+CONFIG_NETWORK_SECMARK=y
423+CONFIG_NETFILTER=y
424+# CONFIG_NETFILTER_DEBUG is not set
425+CONFIG_NETFILTER_ADVANCED=y
426+
427+#
428+# Core Netfilter Configuration
429+#
430+# CONFIG_NETFILTER_NETLINK_QUEUE is not set
431+# CONFIG_NETFILTER_NETLINK_LOG is not set
432+# CONFIG_NF_CONNTRACK is not set
433+# CONFIG_NETFILTER_XTABLES is not set
434+# CONFIG_IP_VS is not set
435+
436+#
437+# IP: Netfilter Configuration
438+#
439+# CONFIG_NF_DEFRAG_IPV4 is not set
440+# CONFIG_IP_NF_QUEUE is not set
441+# CONFIG_IP_NF_IPTABLES is not set
442+# CONFIG_IP_NF_ARPTABLES is not set
443+
444+#
445+# IPv6: Netfilter Configuration
446+#
447+# CONFIG_IP6_NF_QUEUE is not set
448+# CONFIG_IP6_NF_IPTABLES is not set
449+# CONFIG_IP_DCCP is not set
450+# CONFIG_IP_SCTP is not set
451+# CONFIG_RDS is not set
452+# CONFIG_TIPC is not set
453+# CONFIG_ATM is not set
454+# CONFIG_BRIDGE is not set
455+# CONFIG_NET_DSA is not set
456+# CONFIG_VLAN_8021Q is not set
457+# CONFIG_DECNET is not set
458+# CONFIG_LLC2 is not set
459+# CONFIG_IPX is not set
460+# CONFIG_ATALK is not set
461+# CONFIG_X25 is not set
462+# CONFIG_LAPB is not set
463+# CONFIG_ECONET is not set
464+# CONFIG_WAN_ROUTER is not set
465+# CONFIG_PHONET is not set
466+# CONFIG_IEEE802154 is not set
467+CONFIG_NET_SCHED=y
468+
469+#
470+# Queueing/Scheduling
471+#
472+# CONFIG_NET_SCH_CBQ is not set
473+# CONFIG_NET_SCH_HTB is not set
474+# CONFIG_NET_SCH_HFSC is not set
475+# CONFIG_NET_SCH_PRIO is not set
476+# CONFIG_NET_SCH_MULTIQ is not set
477+# CONFIG_NET_SCH_RED is not set
478+# CONFIG_NET_SCH_SFQ is not set
479+# CONFIG_NET_SCH_TEQL is not set
480+# CONFIG_NET_SCH_TBF is not set
481+# CONFIG_NET_SCH_GRED is not set
482+# CONFIG_NET_SCH_DSMARK is not set
483+# CONFIG_NET_SCH_NETEM is not set
484+# CONFIG_NET_SCH_DRR is not set
485+# CONFIG_NET_SCH_INGRESS is not set
486+
487+#
488+# Classification
489+#
490+CONFIG_NET_CLS=y
491+# CONFIG_NET_CLS_BASIC is not set
492+# CONFIG_NET_CLS_TCINDEX is not set
493+# CONFIG_NET_CLS_ROUTE4 is not set
494+# CONFIG_NET_CLS_FW is not set
495+# CONFIG_NET_CLS_U32 is not set
496+# CONFIG_NET_CLS_RSVP is not set
497+# CONFIG_NET_CLS_RSVP6 is not set
498+# CONFIG_NET_CLS_FLOW is not set
499+CONFIG_NET_EMATCH=y
500+CONFIG_NET_EMATCH_STACK=32
501+# CONFIG_NET_EMATCH_CMP is not set
502+# CONFIG_NET_EMATCH_NBYTE is not set
503+# CONFIG_NET_EMATCH_U32 is not set
504+# CONFIG_NET_EMATCH_META is not set
505+# CONFIG_NET_EMATCH_TEXT is not set
506+CONFIG_NET_CLS_ACT=y
507+# CONFIG_NET_ACT_POLICE is not set
508+# CONFIG_NET_ACT_GACT is not set
509+# CONFIG_NET_ACT_MIRRED is not set
510+# CONFIG_NET_ACT_NAT is not set
511+# CONFIG_NET_ACT_PEDIT is not set
512+# CONFIG_NET_ACT_SIMP is not set
513+# CONFIG_NET_ACT_SKBEDIT is not set
514+CONFIG_NET_SCH_FIFO=y
515+# CONFIG_DCB is not set
516+
517+#
518+# Network testing
519+#
520+# CONFIG_NET_PKTGEN is not set
521+# CONFIG_HAMRADIO is not set
522+# CONFIG_CAN is not set
523+# CONFIG_IRDA is not set
524+# CONFIG_BT is not set
525+# CONFIG_AF_RXRPC is not set
526+CONFIG_FIB_RULES=y
527+CONFIG_WIRELESS=y
528+# CONFIG_CFG80211 is not set
529+CONFIG_CFG80211_DEFAULT_PS_VALUE=0
530+# CONFIG_WIRELESS_OLD_REGULATORY is not set
531+CONFIG_WIRELESS_EXT=y
532+CONFIG_WIRELESS_EXT_SYSFS=y
533+# CONFIG_LIB80211 is not set
534+
535+#
536+# CFG80211 needs to be enabled for MAC80211
537+#
538+# CONFIG_WIMAX is not set
539+CONFIG_RFKILL=m
540+# CONFIG_RFKILL_INPUT is not set
541+# CONFIG_NET_9P is not set
542+
543+#
544+# Device Drivers
545+#
546+
547+#
548+# Generic Driver Options
549+#
550+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
551+# CONFIG_DEVTMPFS is not set
552+CONFIG_STANDALONE=y
553+CONFIG_PREVENT_FIRMWARE_BUILD=y
554+CONFIG_FW_LOADER=y
555+CONFIG_FIRMWARE_IN_KERNEL=y
556+CONFIG_EXTRA_FIRMWARE=""
557+# CONFIG_SYS_HYPERVISOR is not set
558+# CONFIG_CONNECTOR is not set
559+# CONFIG_MTD is not set
560+# CONFIG_PARPORT is not set
561+# CONFIG_PNP is not set
562+CONFIG_BLK_DEV=y
563+# CONFIG_BLK_CPQ_DA is not set
564+# CONFIG_BLK_CPQ_CISS_DA is not set
565+# CONFIG_BLK_DEV_DAC960 is not set
566+# CONFIG_BLK_DEV_UMEM is not set
567+# CONFIG_BLK_DEV_COW_COMMON is not set
568+CONFIG_BLK_DEV_LOOP=y
569+CONFIG_BLK_DEV_CRYPTOLOOP=y
570+# CONFIG_BLK_DEV_NBD is not set
571+# CONFIG_BLK_DEV_SX8 is not set
572+# CONFIG_BLK_DEV_UB is not set
573+CONFIG_BLK_DEV_RAM=y
574+CONFIG_BLK_DEV_RAM_COUNT=16
575+CONFIG_BLK_DEV_RAM_SIZE=8192
576+# CONFIG_BLK_DEV_XIP is not set
577+# CONFIG_CDROM_PKTCDVD is not set
578+# CONFIG_ATA_OVER_ETH is not set
579+# CONFIG_BLK_DEV_HD is not set
580+CONFIG_MISC_DEVICES=y
581+# CONFIG_PHANTOM is not set
582+# CONFIG_SGI_IOC4 is not set
583+# CONFIG_TIFM_CORE is not set
584+# CONFIG_ENCLOSURE_SERVICES is not set
585+# CONFIG_HP_ILO is not set
586+# CONFIG_C2PORT is not set
587+
588+#
589+# EEPROM support
590+#
591+# CONFIG_EEPROM_93CX6 is not set
592+# CONFIG_CB710_CORE is not set
593+CONFIG_HAVE_IDE=y
594+CONFIG_IDE=y
595+
596+#
597+# Please see Documentation/ide/ide.txt for help/info on IDE drives
598+#
599+CONFIG_IDE_XFER_MODE=y
600+CONFIG_IDE_TIMINGS=y
601+# CONFIG_BLK_DEV_IDE_SATA is not set
602+CONFIG_IDE_GD=y
603+CONFIG_IDE_GD_ATA=y
604+# CONFIG_IDE_GD_ATAPI is not set
605+# CONFIG_BLK_DEV_IDECD is not set
606+# CONFIG_BLK_DEV_IDETAPE is not set
607+CONFIG_IDE_TASK_IOCTL=y
608+CONFIG_IDE_PROC_FS=y
609+
610+#
611+# IDE chipset support/bugfixes
612+#
613+# CONFIG_IDE_GENERIC is not set
614+# CONFIG_BLK_DEV_PLATFORM is not set
615+CONFIG_BLK_DEV_IDEDMA_SFF=y
616+
617+#
618+# PCI IDE chipsets support
619+#
620+CONFIG_BLK_DEV_IDEPCI=y
621+# CONFIG_IDEPCI_PCIBUS_ORDER is not set
622+# CONFIG_BLK_DEV_OFFBOARD is not set
623+CONFIG_BLK_DEV_GENERIC=y
624+# CONFIG_BLK_DEV_OPTI621 is not set
625+CONFIG_BLK_DEV_IDEDMA_PCI=y
626+# CONFIG_BLK_DEV_AEC62XX is not set
627+# CONFIG_BLK_DEV_ALI15X3 is not set
628+CONFIG_BLK_DEV_AMD74XX=y
629+# CONFIG_BLK_DEV_CMD64X is not set
630+# CONFIG_BLK_DEV_TRIFLEX is not set
631+# CONFIG_BLK_DEV_CS5520 is not set
632+# CONFIG_BLK_DEV_CS5530 is not set
633+# CONFIG_BLK_DEV_HPT366 is not set
634+# CONFIG_BLK_DEV_JMICRON is not set
635+# CONFIG_BLK_DEV_SC1200 is not set
636+# CONFIG_BLK_DEV_PIIX is not set
637+# CONFIG_BLK_DEV_IT8172 is not set
638+# CONFIG_BLK_DEV_IT8213 is not set
639+# CONFIG_BLK_DEV_IT821X is not set
640+# CONFIG_BLK_DEV_NS87415 is not set
641+# CONFIG_BLK_DEV_PDC202XX_OLD is not set
642+# CONFIG_BLK_DEV_PDC202XX_NEW is not set
643+# CONFIG_BLK_DEV_SVWKS is not set
644+# CONFIG_BLK_DEV_SIIMAGE is not set
645+# CONFIG_BLK_DEV_SLC90E66 is not set
646+# CONFIG_BLK_DEV_TRM290 is not set
647+# CONFIG_BLK_DEV_VIA82CXXX is not set
648+# CONFIG_BLK_DEV_TC86C001 is not set
649+
650+#
651+# Other IDE chipsets support
652+#
653+
654+#
655+# Note: most of these also require special kernel boot parameters
656+#
657+# CONFIG_BLK_DEV_4DRIVES is not set
658+# CONFIG_BLK_DEV_ALI14XX is not set
659+# CONFIG_BLK_DEV_DTC2278 is not set
660+# CONFIG_BLK_DEV_HT6560B is not set
661+# CONFIG_BLK_DEV_QD65XX is not set
662+# CONFIG_BLK_DEV_UMC8672 is not set
663+CONFIG_BLK_DEV_IDEDMA=y
664+
665+#
666+# SCSI device support
667+#
668+# CONFIG_RAID_ATTRS is not set
669+CONFIG_SCSI=m
670+CONFIG_SCSI_DMA=y
671+# CONFIG_SCSI_TGT is not set
672+# CONFIG_SCSI_NETLINK is not set
673+CONFIG_SCSI_PROC_FS=y
674+
675+#
676+# SCSI support type (disk, tape, CD-ROM)
677+#
678+CONFIG_BLK_DEV_SD=m
679+# CONFIG_CHR_DEV_ST is not set
680+# CONFIG_CHR_DEV_OSST is not set
681+# CONFIG_BLK_DEV_SR is not set
682+CONFIG_CHR_DEV_SG=m
683+# CONFIG_CHR_DEV_SCH is not set
684+CONFIG_SCSI_MULTI_LUN=y
685+# CONFIG_SCSI_CONSTANTS is not set
686+# CONFIG_SCSI_LOGGING is not set
687+# CONFIG_SCSI_SCAN_ASYNC is not set
688+CONFIG_SCSI_WAIT_SCAN=m
689+
690+#
691+# SCSI Transports
692+#
693+# CONFIG_SCSI_SPI_ATTRS is not set
694+# CONFIG_SCSI_FC_ATTRS is not set
695+# CONFIG_SCSI_ISCSI_ATTRS is not set
696+# CONFIG_SCSI_SAS_ATTRS is not set
697+# CONFIG_SCSI_SAS_LIBSAS is not set
698+# CONFIG_SCSI_SRP_ATTRS is not set
699+# CONFIG_SCSI_LOWLEVEL is not set
700+# CONFIG_SCSI_DH is not set
701+# CONFIG_SCSI_OSD_INITIATOR is not set
702+# CONFIG_ATA is not set
703+# CONFIG_MD is not set
704+# CONFIG_FUSION is not set
705+
706+#
707+# IEEE 1394 (FireWire) support
708+#
709+
710+#
711+# You can enable one or both FireWire driver stacks.
712+#
713+
714+#
715+# See the help texts for more information.
716+#
717+# CONFIG_FIREWIRE is not set
718+# CONFIG_IEEE1394 is not set
719+# CONFIG_I2O is not set
720+CONFIG_NETDEVICES=y
721+# CONFIG_IFB is not set
722+# CONFIG_DUMMY is not set
723+# CONFIG_BONDING is not set
724+# CONFIG_MACVLAN is not set
725+# CONFIG_EQUALIZER is not set
726+# CONFIG_TUN is not set
727+# CONFIG_VETH is not set
728+# CONFIG_ARCNET is not set
729+# CONFIG_PHYLIB is not set
730+CONFIG_NET_ETHERNET=y
731+CONFIG_MII=y
732+# CONFIG_AX88796 is not set
733+# CONFIG_HAPPYMEAL is not set
734+# CONFIG_SUNGEM is not set
735+# CONFIG_CASSINI is not set
736+# CONFIG_NET_VENDOR_3COM is not set
737+# CONFIG_NET_VENDOR_SMC is not set
738+# CONFIG_SMC91X is not set
739+# CONFIG_DM9000 is not set
740+# CONFIG_ETHOC is not set
741+# CONFIG_NET_VENDOR_RACAL is not set
742+# CONFIG_DNET is not set
743+# CONFIG_NET_TULIP is not set
744+# CONFIG_AT1700 is not set
745+# CONFIG_DEPCA is not set
746+# CONFIG_HP100 is not set
747+# CONFIG_NET_ISA is not set
748+# CONFIG_IBM_NEW_EMAC_ZMII is not set
749+# CONFIG_IBM_NEW_EMAC_RGMII is not set
750+# CONFIG_IBM_NEW_EMAC_TAH is not set
751+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
752+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
753+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
754+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
755+CONFIG_NET_PCI=y
756+# CONFIG_PCNET32 is not set
757+# CONFIG_AMD8111_ETH is not set
758+# CONFIG_ADAPTEC_STARFIRE is not set
759+# CONFIG_AC3200 is not set
760+# CONFIG_APRICOT is not set
761+# CONFIG_B44 is not set
762+# CONFIG_FORCEDETH is not set
763+# CONFIG_CS89x0 is not set
764+# CONFIG_TC35815 is not set
765+# CONFIG_E100 is not set
766+# CONFIG_FEALNX is not set
767+# CONFIG_NATSEMI is not set
768+# CONFIG_NE2K_PCI is not set
769+# CONFIG_8139CP is not set
770+CONFIG_8139TOO=y
771+# CONFIG_8139TOO_PIO is not set
772+CONFIG_8139TOO_TUNE_TWISTER=y
773+# CONFIG_8139TOO_8129 is not set
774+# CONFIG_8139_OLD_RX_RESET is not set
775+# CONFIG_R6040 is not set
776+# CONFIG_SIS900 is not set
777+# CONFIG_EPIC100 is not set
778+# CONFIG_SMSC9420 is not set
779+# CONFIG_SUNDANCE is not set
780+# CONFIG_TLAN is not set
781+# CONFIG_KS8842 is not set
782+# CONFIG_KS8851_MLL is not set
783+# CONFIG_VIA_RHINE is not set
784+# CONFIG_SC92031 is not set
785+# CONFIG_ATL2 is not set
786+CONFIG_NETDEV_1000=y
787+# CONFIG_ACENIC is not set
788+# CONFIG_DL2K is not set
789+# CONFIG_E1000 is not set
790+# CONFIG_E1000E is not set
791+# CONFIG_IP1000 is not set
792+# CONFIG_IGB is not set
793+# CONFIG_IGBVF is not set
794+# CONFIG_NS83820 is not set
795+# CONFIG_HAMACHI is not set
796+# CONFIG_YELLOWFIN is not set
797+CONFIG_R8169=y
798+# CONFIG_SIS190 is not set
799+# CONFIG_SKGE is not set
800+# CONFIG_SKY2 is not set
801+# CONFIG_VIA_VELOCITY is not set
802+# CONFIG_TIGON3 is not set
803+# CONFIG_BNX2 is not set
804+# CONFIG_CNIC is not set
805+# CONFIG_QLA3XXX is not set
806+# CONFIG_ATL1 is not set
807+# CONFIG_ATL1E is not set
808+# CONFIG_ATL1C is not set
809+# CONFIG_JME is not set
810+# CONFIG_NETDEV_10000 is not set
811+# CONFIG_TR is not set
812+CONFIG_WLAN=y
813+CONFIG_WLAN_PRE80211=y
814+# CONFIG_STRIP is not set
815+# CONFIG_WAVELAN is not set
816+CONFIG_WLAN_80211=y
817+# CONFIG_LIBERTAS is not set
818+# CONFIG_ATMEL is not set
819+# CONFIG_PRISM54 is not set
820+# CONFIG_USB_ZD1201 is not set
821+# CONFIG_HOSTAP is not set
822+
823+#
824+# Enable WiMAX (Networking options) to see the WiMAX drivers
825+#
826+
827+#
828+# USB Network Adapters
829+#
830+# CONFIG_USB_CATC is not set
831+# CONFIG_USB_KAWETH is not set
832+# CONFIG_USB_PEGASUS is not set
833+# CONFIG_USB_RTL8150 is not set
834+# CONFIG_USB_USBNET is not set
835+# CONFIG_USB_HSO is not set
836+# CONFIG_WAN is not set
837+# CONFIG_FDDI is not set
838+# CONFIG_HIPPI is not set
839+# CONFIG_PPP is not set
840+# CONFIG_SLIP is not set
841+# CONFIG_NET_FC is not set
842+# CONFIG_NETCONSOLE is not set
843+# CONFIG_NETPOLL is not set
844+# CONFIG_NET_POLL_CONTROLLER is not set
845+# CONFIG_ISDN is not set
846+# CONFIG_PHONE is not set
847+
848+#
849+# Input device support
850+#
851+CONFIG_INPUT=y
852+# CONFIG_INPUT_FF_MEMLESS is not set
853+# CONFIG_INPUT_POLLDEV is not set
854+
855+#
856+# Userland interfaces
857+#
858+CONFIG_INPUT_MOUSEDEV=y
859+CONFIG_INPUT_MOUSEDEV_PSAUX=y
860+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
861+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
862+# CONFIG_INPUT_JOYDEV is not set
863+CONFIG_INPUT_EVDEV=y
864+# CONFIG_INPUT_EVBUG is not set
865+
866+#
867+# Input Device Drivers
868+#
869+CONFIG_INPUT_KEYBOARD=y
870+CONFIG_KEYBOARD_ATKBD=y
871+# CONFIG_KEYBOARD_LKKBD is not set
872+# CONFIG_KEYBOARD_NEWTON is not set
873+# CONFIG_KEYBOARD_OPENCORES is not set
874+# CONFIG_KEYBOARD_STOWAWAY is not set
875+# CONFIG_KEYBOARD_SUNKBD is not set
876+# CONFIG_KEYBOARD_XTKBD is not set
877+CONFIG_INPUT_MOUSE=y
878+CONFIG_MOUSE_PS2=y
879+# CONFIG_MOUSE_PS2_ALPS is not set
880+# CONFIG_MOUSE_PS2_LOGIPS2PP is not set
881+CONFIG_MOUSE_PS2_SYNAPTICS=y
882+# CONFIG_MOUSE_PS2_TRACKPOINT is not set
883+# CONFIG_MOUSE_PS2_ELANTECH is not set
884+# CONFIG_MOUSE_PS2_SENTELIC is not set
885+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
886+# CONFIG_MOUSE_SERIAL is not set
887+# CONFIG_MOUSE_APPLETOUCH is not set
888+# CONFIG_MOUSE_BCM5974 is not set
889+# CONFIG_MOUSE_INPORT is not set
890+# CONFIG_MOUSE_LOGIBM is not set
891+# CONFIG_MOUSE_PC110PAD is not set
892+# CONFIG_MOUSE_VSXXXAA is not set
893+# CONFIG_INPUT_JOYSTICK is not set
894+# CONFIG_INPUT_TABLET is not set
895+# CONFIG_INPUT_TOUCHSCREEN is not set
896+# CONFIG_INPUT_MISC is not set
897+
898+#
899+# Hardware I/O ports
900+#
901+CONFIG_SERIO=y
902+CONFIG_SERIO_I8042=y
903+# CONFIG_SERIO_SERPORT is not set
904+# CONFIG_SERIO_PCIPS2 is not set
905+CONFIG_SERIO_LIBPS2=y
906+# CONFIG_SERIO_RAW is not set
907+# CONFIG_GAMEPORT is not set
908+
909+#
910+# Character devices
911+#
912+CONFIG_VT=y
913+CONFIG_CONSOLE_TRANSLATIONS=y
914+CONFIG_VT_CONSOLE=y
915+CONFIG_HW_CONSOLE=y
916+# CONFIG_VT_HW_CONSOLE_BINDING is not set
917+CONFIG_DEVKMEM=y
918+CONFIG_SERIAL_NONSTANDARD=y
919+# CONFIG_COMPUTONE is not set
920+# CONFIG_ROCKETPORT is not set
921+# CONFIG_CYCLADES is not set
922+# CONFIG_DIGIEPCA is not set
923+# CONFIG_MOXA_INTELLIO is not set
924+# CONFIG_MOXA_SMARTIO is not set
925+# CONFIG_ISI is not set
926+# CONFIG_SYNCLINKMP is not set
927+# CONFIG_SYNCLINK_GT is not set
928+# CONFIG_N_HDLC is not set
929+# CONFIG_RISCOM8 is not set
930+# CONFIG_SPECIALIX is not set
931+# CONFIG_STALDRV is not set
932+# CONFIG_NOZOMI is not set
933+
934+#
935+# Serial drivers
936+#
937+CONFIG_SERIAL_8250=y
938+CONFIG_SERIAL_8250_CONSOLE=y
939+# CONFIG_SERIAL_8250_PCI is not set
940+CONFIG_SERIAL_8250_NR_UARTS=16
941+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
942+CONFIG_SERIAL_8250_EXTENDED=y
943+CONFIG_SERIAL_8250_MANY_PORTS=y
944+CONFIG_SERIAL_8250_FOURPORT=y
945+# CONFIG_SERIAL_8250_ACCENT is not set
946+# CONFIG_SERIAL_8250_BOCA is not set
947+# CONFIG_SERIAL_8250_EXAR_ST16C554 is not set
948+# CONFIG_SERIAL_8250_HUB6 is not set
949+# CONFIG_SERIAL_8250_SHARE_IRQ is not set
950+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
951+# CONFIG_SERIAL_8250_RSA is not set
952+
953+#
954+# Non-8250 serial port support
955+#
956+CONFIG_SERIAL_CORE=y
957+CONFIG_SERIAL_CORE_CONSOLE=y
958+# CONFIG_SERIAL_JSM is not set
959+CONFIG_UNIX98_PTYS=y
960+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
961+CONFIG_LEGACY_PTYS=y
962+CONFIG_LEGACY_PTY_COUNT=16
963+# CONFIG_IPMI_HANDLER is not set
964+CONFIG_HW_RANDOM=y
965+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
966+CONFIG_RTC=y
967+# CONFIG_DTLK is not set
968+# CONFIG_R3964 is not set
969+# CONFIG_APPLICOM is not set
970+# CONFIG_RAW_DRIVER is not set
971+# CONFIG_TCG_TPM is not set
972+CONFIG_DEVPORT=y
973+# CONFIG_I2C is not set
974+# CONFIG_SPI is not set
975+
976+#
977+# PPS support
978+#
979+# CONFIG_PPS is not set
980+# CONFIG_W1 is not set
981+# CONFIG_POWER_SUPPLY is not set
982+CONFIG_HWMON=y
983+# CONFIG_HWMON_VID is not set
984+# CONFIG_HWMON_DEBUG_CHIP is not set
985+
986+#
987+# Native drivers
988+#
989+# CONFIG_SENSORS_I5K_AMB is not set
990+# CONFIG_SENSORS_F71805F is not set
991+# CONFIG_SENSORS_F71882FG is not set
992+# CONFIG_SENSORS_IT87 is not set
993+# CONFIG_SENSORS_PC87360 is not set
994+# CONFIG_SENSORS_PC87427 is not set
995+# CONFIG_SENSORS_SIS5595 is not set
996+# CONFIG_SENSORS_SMSC47M1 is not set
997+# CONFIG_SENSORS_SMSC47B397 is not set
998+# CONFIG_SENSORS_VIA686A is not set
999+# CONFIG_SENSORS_VT1211 is not set
1000+# CONFIG_SENSORS_VT8231 is not set
1001+# CONFIG_SENSORS_W83627HF is not set
1002+# CONFIG_SENSORS_W83627EHF is not set
1003+CONFIG_THERMAL=y
1004+# CONFIG_THERMAL_HWMON is not set
1005+# CONFIG_WATCHDOG is not set
1006+CONFIG_SSB_POSSIBLE=y
1007+
1008+#
1009+# Sonics Silicon Backplane
1010+#
1011+# CONFIG_SSB is not set
1012+
1013+#
1014+# Multifunction device drivers
1015+#
1016+# CONFIG_MFD_CORE is not set
1017+# CONFIG_MFD_SM501 is not set
1018+# CONFIG_HTC_PASIC3 is not set
1019+# CONFIG_MFD_TMIO is not set
1020+# CONFIG_REGULATOR is not set
1021+CONFIG_MEDIA_SUPPORT=m
1022+
1023+#
1024+# Multimedia core support
1025+#
1026+CONFIG_VIDEO_DEV=m
1027+CONFIG_VIDEO_V4L2_COMMON=m
1028+CONFIG_VIDEO_ALLOW_V4L1=y
1029+CONFIG_VIDEO_V4L1_COMPAT=y
1030+# CONFIG_DVB_CORE is not set
1031+CONFIG_VIDEO_MEDIA=m
1032+
1033+#
1034+# Multimedia drivers
1035+#
1036+# CONFIG_MEDIA_ATTACH is not set
1037+CONFIG_VIDEO_V4L2=m
1038+CONFIG_VIDEO_V4L1=m
1039+CONFIG_VIDEO_CAPTURE_DRIVERS=y
1040+# CONFIG_VIDEO_ADV_DEBUG is not set
1041+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
1042+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
1043+# CONFIG_VIDEO_VIVI is not set
1044+# CONFIG_VIDEO_PMS is not set
1045+# CONFIG_VIDEO_CPIA is not set
1046+# CONFIG_VIDEO_CPIA2 is not set
1047+# CONFIG_VIDEO_STRADIS is not set
1048+CONFIG_V4L_USB_DRIVERS=y
1049+CONFIG_USB_VIDEO_CLASS=m
1050+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
1051+CONFIG_USB_GSPCA=m
1052+# CONFIG_USB_M5602 is not set
1053+# CONFIG_USB_STV06XX is not set
1054+# CONFIG_USB_GL860 is not set
1055+# CONFIG_USB_GSPCA_CONEX is not set
1056+# CONFIG_USB_GSPCA_ETOMS is not set
1057+# CONFIG_USB_GSPCA_FINEPIX is not set
1058+# CONFIG_USB_GSPCA_JEILINJ is not set
1059+# CONFIG_USB_GSPCA_MARS is not set
1060+# CONFIG_USB_GSPCA_MR97310A is not set
1061+# CONFIG_USB_GSPCA_OV519 is not set
1062+# CONFIG_USB_GSPCA_OV534 is not set
1063+# CONFIG_USB_GSPCA_PAC207 is not set
1064+# CONFIG_USB_GSPCA_PAC7311 is not set
1065+# CONFIG_USB_GSPCA_SN9C20X is not set
1066+# CONFIG_USB_GSPCA_SONIXB is not set
1067+# CONFIG_USB_GSPCA_SONIXJ is not set
1068+# CONFIG_USB_GSPCA_SPCA500 is not set
1069+# CONFIG_USB_GSPCA_SPCA501 is not set
1070+# CONFIG_USB_GSPCA_SPCA505 is not set
1071+# CONFIG_USB_GSPCA_SPCA506 is not set
1072+# CONFIG_USB_GSPCA_SPCA508 is not set
1073+# CONFIG_USB_GSPCA_SPCA561 is not set
1074+# CONFIG_USB_GSPCA_SQ905 is not set
1075+# CONFIG_USB_GSPCA_SQ905C is not set
1076+# CONFIG_USB_GSPCA_STK014 is not set
1077+# CONFIG_USB_GSPCA_SUNPLUS is not set
1078+# CONFIG_USB_GSPCA_T613 is not set
1079+# CONFIG_USB_GSPCA_TV8532 is not set
1080+# CONFIG_USB_GSPCA_VC032X is not set
1081+# CONFIG_USB_GSPCA_ZC3XX is not set
1082+# CONFIG_VIDEO_HDPVR is not set
1083+# CONFIG_USB_VICAM is not set
1084+# CONFIG_USB_IBMCAM is not set
1085+# CONFIG_USB_KONICAWC is not set
1086+# CONFIG_USB_QUICKCAM_MESSENGER is not set
1087+# CONFIG_USB_ET61X251 is not set
1088+# CONFIG_USB_OV511 is not set
1089+# CONFIG_USB_SE401 is not set
1090+# CONFIG_USB_SN9C102 is not set
1091+# CONFIG_USB_STV680 is not set
1092+# CONFIG_USB_ZC0301 is not set
1093+# CONFIG_USB_PWC is not set
1094+CONFIG_USB_PWC_INPUT_EVDEV=y
1095+# CONFIG_USB_ZR364XX is not set
1096+# CONFIG_USB_STKWEBCAM is not set
1097+# CONFIG_USB_S2255 is not set
1098+# CONFIG_RADIO_ADAPTERS is not set
1099+# CONFIG_DAB is not set
1100+
1101+#
1102+# Graphics support
1103+#
1104+CONFIG_VGA_ARB=y
1105+# CONFIG_DRM is not set
1106+# CONFIG_VGASTATE is not set
1107+CONFIG_VIDEO_OUTPUT_CONTROL=y
1108+CONFIG_FB=y
1109+CONFIG_FIRMWARE_EDID=y
1110+# CONFIG_FB_DDC is not set
1111+CONFIG_FB_BOOT_VESA_SUPPORT=y
1112+CONFIG_FB_CFB_FILLRECT=y
1113+CONFIG_FB_CFB_COPYAREA=y
1114+CONFIG_FB_CFB_IMAGEBLIT=y
1115+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
1116+# CONFIG_FB_SYS_FILLRECT is not set
1117+# CONFIG_FB_SYS_COPYAREA is not set
1118+# CONFIG_FB_SYS_IMAGEBLIT is not set
1119+# CONFIG_FB_FOREIGN_ENDIAN is not set
1120+# CONFIG_FB_SYS_FOPS is not set
1121+# CONFIG_FB_SVGALIB is not set
1122+# CONFIG_FB_MACMODES is not set
1123+# CONFIG_FB_BACKLIGHT is not set
1124+CONFIG_FB_MODE_HELPERS=y
1125+CONFIG_FB_TILEBLITTING=y
1126+
1127+#
1128+# Frame buffer hardware drivers
1129+#
1130+# CONFIG_FB_CIRRUS is not set
1131+# CONFIG_FB_PM2 is not set
1132+# CONFIG_FB_CYBER2000 is not set
1133+# CONFIG_FB_ASILIANT is not set
1134+# CONFIG_FB_IMSTT is not set
1135+# CONFIG_FB_S1D13XXX is not set
1136+# CONFIG_FB_NVIDIA is not set
1137+# CONFIG_FB_RIVA is not set
1138+# CONFIG_FB_MATROX is not set
1139+# CONFIG_FB_RADEON is not set
1140+# CONFIG_FB_ATY128 is not set
1141+# CONFIG_FB_ATY is not set
1142+# CONFIG_FB_S3 is not set
1143+# CONFIG_FB_SAVAGE is not set
1144+CONFIG_FB_SIS=y
1145+CONFIG_FB_SIS_300=y
1146+CONFIG_FB_SIS_315=y
1147+# CONFIG_FB_VIA is not set
1148+# CONFIG_FB_NEOMAGIC is not set
1149+# CONFIG_FB_KYRO is not set
1150+# CONFIG_FB_3DFX is not set
1151+# CONFIG_FB_VOODOO1 is not set
1152+# CONFIG_FB_VT8623 is not set
1153+# CONFIG_FB_TRIDENT is not set
1154+# CONFIG_FB_ARK is not set
1155+# CONFIG_FB_PM3 is not set
1156+# CONFIG_FB_CARMINE is not set
1157+# CONFIG_FB_VIRTUAL is not set
1158+# CONFIG_FB_METRONOME is not set
1159+# CONFIG_FB_MB862XX is not set
1160+# CONFIG_FB_BROADSHEET is not set
1161+CONFIG_BACKLIGHT_LCD_SUPPORT=y
1162+# CONFIG_LCD_CLASS_DEVICE is not set
1163+CONFIG_BACKLIGHT_CLASS_DEVICE=y
1164+CONFIG_BACKLIGHT_GENERIC=y
1165+
1166+#
1167+# Display device support
1168+#
1169+# CONFIG_DISPLAY_SUPPORT is not set
1170+
1171+#
1172+# Console display driver support
1173+#
1174+# CONFIG_VGA_CONSOLE is not set
1175+# CONFIG_MDA_CONSOLE is not set
1176+CONFIG_DUMMY_CONSOLE=y
1177+CONFIG_FRAMEBUFFER_CONSOLE=y
1178+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
1179+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
1180+CONFIG_FONTS=y
1181+CONFIG_FONT_8x8=y
1182+CONFIG_FONT_8x16=y
1183+CONFIG_FONT_6x11=y
1184+CONFIG_FONT_7x14=y
1185+CONFIG_FONT_PEARL_8x8=y
1186+CONFIG_FONT_ACORN_8x8=y
1187+CONFIG_FONT_MINI_4x6=y
1188+CONFIG_FONT_SUN8x16=y
1189+CONFIG_FONT_SUN12x22=y
1190+CONFIG_FONT_10x18=y
1191+CONFIG_LOGO=y
1192+# CONFIG_LOGO_LINUX_MONO is not set
1193+# CONFIG_LOGO_LINUX_VGA16 is not set
1194+CONFIG_LOGO_LINUX_CLUT224=y
1195+CONFIG_SOUND=m
1196+# CONFIG_SOUND_OSS_CORE is not set
1197+CONFIG_SND=m
1198+CONFIG_SND_TIMER=m
1199+CONFIG_SND_PCM=m
1200+# CONFIG_SND_SEQUENCER is not set
1201+# CONFIG_SND_MIXER_OSS is not set
1202+# CONFIG_SND_PCM_OSS is not set
1203+# CONFIG_SND_HRTIMER is not set
1204+# CONFIG_SND_RTCTIMER is not set
1205+# CONFIG_SND_DYNAMIC_MINORS is not set
1206+# CONFIG_SND_SUPPORT_OLD_API is not set
1207+# CONFIG_SND_VERBOSE_PROCFS is not set
1208+# CONFIG_SND_VERBOSE_PRINTK is not set
1209+# CONFIG_SND_DEBUG is not set
1210+CONFIG_SND_VMASTER=y
1211+# CONFIG_SND_RAWMIDI_SEQ is not set
1212+# CONFIG_SND_OPL3_LIB_SEQ is not set
1213+# CONFIG_SND_OPL4_LIB_SEQ is not set
1214+# CONFIG_SND_SBAWE_SEQ is not set
1215+# CONFIG_SND_EMU10K1_SEQ is not set
1216+CONFIG_SND_AC97_CODEC=m
1217+# CONFIG_SND_DRIVERS is not set
1218+CONFIG_SND_PCI=y
1219+# CONFIG_SND_AD1889 is not set
1220+# CONFIG_SND_ALS300 is not set
1221+# CONFIG_SND_ALI5451 is not set
1222+# CONFIG_SND_ATIIXP is not set
1223+# CONFIG_SND_ATIIXP_MODEM is not set
1224+# CONFIG_SND_AU8810 is not set
1225+# CONFIG_SND_AU8820 is not set
1226+# CONFIG_SND_AU8830 is not set
1227+# CONFIG_SND_AW2 is not set
1228+# CONFIG_SND_AZT3328 is not set
1229+# CONFIG_SND_BT87X is not set
1230+# CONFIG_SND_CA0106 is not set
1231+# CONFIG_SND_CMIPCI is not set
1232+# CONFIG_SND_OXYGEN is not set
1233+# CONFIG_SND_CS4281 is not set
1234+# CONFIG_SND_CS46XX is not set
1235+CONFIG_SND_CS5535AUDIO=m
1236+# CONFIG_SND_CTXFI is not set
1237+# CONFIG_SND_DARLA20 is not set
1238+# CONFIG_SND_GINA20 is not set
1239+# CONFIG_SND_LAYLA20 is not set
1240+# CONFIG_SND_DARLA24 is not set
1241+# CONFIG_SND_GINA24 is not set
1242+# CONFIG_SND_LAYLA24 is not set
1243+# CONFIG_SND_MONA is not set
1244+# CONFIG_SND_MIA is not set
1245+# CONFIG_SND_ECHO3G is not set
1246+# CONFIG_SND_INDIGO is not set
1247+# CONFIG_SND_INDIGOIO is not set
1248+# CONFIG_SND_INDIGODJ is not set
1249+# CONFIG_SND_INDIGOIOX is not set
1250+# CONFIG_SND_INDIGODJX is not set
1251+# CONFIG_SND_EMU10K1 is not set
1252+# CONFIG_SND_EMU10K1X is not set
1253+# CONFIG_SND_ENS1370 is not set
1254+# CONFIG_SND_ENS1371 is not set
1255+# CONFIG_SND_ES1938 is not set
1256+# CONFIG_SND_ES1968 is not set
1257+# CONFIG_SND_FM801 is not set
1258+# CONFIG_SND_HDA_INTEL is not set
1259+# CONFIG_SND_HDSP is not set
1260+# CONFIG_SND_HDSPM is not set
1261+# CONFIG_SND_HIFIER is not set
1262+# CONFIG_SND_ICE1712 is not set
1263+# CONFIG_SND_ICE1724 is not set
1264+# CONFIG_SND_INTEL8X0 is not set
1265+# CONFIG_SND_INTEL8X0M is not set
1266+# CONFIG_SND_KORG1212 is not set
1267+# CONFIG_SND_LX6464ES is not set
1268+# CONFIG_SND_MAESTRO3 is not set
1269+# CONFIG_SND_MIXART is not set
1270+# CONFIG_SND_NM256 is not set
1271+# CONFIG_SND_PCXHR is not set
1272+# CONFIG_SND_RIPTIDE is not set
1273+# CONFIG_SND_RME32 is not set
1274+# CONFIG_SND_RME96 is not set
1275+# CONFIG_SND_RME9652 is not set
1276+# CONFIG_SND_SONICVIBES is not set
1277+# CONFIG_SND_TRIDENT is not set
1278+# CONFIG_SND_VIA82XX is not set
1279+# CONFIG_SND_VIA82XX_MODEM is not set
1280+# CONFIG_SND_VIRTUOSO is not set
1281+# CONFIG_SND_VX222 is not set
1282+# CONFIG_SND_YMFPCI is not set
1283+# CONFIG_SND_MIPS is not set
1284+# CONFIG_SND_USB is not set
1285+# CONFIG_SND_SOC is not set
1286+# CONFIG_SOUND_PRIME is not set
1287+CONFIG_AC97_BUS=m
1288+CONFIG_HID_SUPPORT=y
1289+CONFIG_HID=y
1290+CONFIG_HIDRAW=y
1291+
1292+#
1293+# USB Input Devices
1294+#
1295+CONFIG_USB_HID=y
1296+# CONFIG_HID_PID is not set
1297+CONFIG_USB_HIDDEV=y
1298+
1299+#
1300+# Special HID drivers
1301+#
1302+# CONFIG_HID_A4TECH is not set
1303+# CONFIG_HID_APPLE is not set
1304+# CONFIG_HID_BELKIN is not set
1305+# CONFIG_HID_CHERRY is not set
1306+# CONFIG_HID_CHICONY is not set
1307+# CONFIG_HID_CYPRESS is not set
1308+# CONFIG_HID_DRAGONRISE is not set
1309+# CONFIG_HID_EZKEY is not set
1310+# CONFIG_HID_KYE is not set
1311+# CONFIG_HID_GYRATION is not set
1312+# CONFIG_HID_TWINHAN is not set
1313+# CONFIG_HID_KENSINGTON is not set
1314+# CONFIG_HID_LOGITECH is not set
1315+# CONFIG_HID_MICROSOFT is not set
1316+# CONFIG_HID_MONTEREY is not set
1317+# CONFIG_HID_NTRIG is not set
1318+# CONFIG_HID_PANTHERLORD is not set
1319+# CONFIG_HID_PETALYNX is not set
1320+# CONFIG_HID_SAMSUNG is not set
1321+# CONFIG_HID_SONY is not set
1322+# CONFIG_HID_SUNPLUS is not set
1323+# CONFIG_HID_GREENASIA is not set
1324+# CONFIG_HID_SMARTJOYPLUS is not set
1325+# CONFIG_HID_TOPSEED is not set
1326+# CONFIG_HID_THRUSTMASTER is not set
1327+# CONFIG_HID_ZEROPLUS is not set
1328+CONFIG_USB_SUPPORT=y
1329+CONFIG_USB_ARCH_HAS_HCD=y
1330+CONFIG_USB_ARCH_HAS_OHCI=y
1331+CONFIG_USB_ARCH_HAS_EHCI=y
1332+CONFIG_USB=y
1333+# CONFIG_USB_DEBUG is not set
1334+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
1335+
1336+#
1337+# Miscellaneous USB options
1338+#
1339+CONFIG_USB_DEVICEFS=y
1340+# CONFIG_USB_DEVICE_CLASS is not set
1341+CONFIG_USB_DYNAMIC_MINORS=y
1342+CONFIG_USB_SUSPEND=y
1343+# CONFIG_USB_OTG is not set
1344+CONFIG_USB_OTG_WHITELIST=y
1345+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
1346+CONFIG_USB_MON=y
1347+# CONFIG_USB_WUSB is not set
1348+# CONFIG_USB_WUSB_CBAF is not set
1349+
1350+#
1351+# USB Host Controller Drivers
1352+#
1353+# CONFIG_USB_C67X00_HCD is not set
1354+# CONFIG_USB_XHCI_HCD is not set
1355+CONFIG_USB_EHCI_HCD=y
1356+CONFIG_USB_EHCI_ROOT_HUB_TT=y
1357+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
1358+# CONFIG_USB_OXU210HP_HCD is not set
1359+# CONFIG_USB_ISP116X_HCD is not set
1360+# CONFIG_USB_ISP1760_HCD is not set
1361+# CONFIG_USB_ISP1362_HCD is not set
1362+CONFIG_USB_OHCI_HCD=y
1363+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
1364+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
1365+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
1366+CONFIG_USB_UHCI_HCD=m
1367+# CONFIG_USB_SL811_HCD is not set
1368+# CONFIG_USB_R8A66597_HCD is not set
1369+# CONFIG_USB_WHCI_HCD is not set
1370+# CONFIG_USB_HWA_HCD is not set
1371+
1372+#
1373+# USB Device Class drivers
1374+#
1375+CONFIG_USB_ACM=m
1376+# CONFIG_USB_PRINTER is not set
1377+CONFIG_USB_WDM=m
1378+# CONFIG_USB_TMC is not set
1379+
1380+#
1381+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
1382+#
1383+
1384+#
1385+# also be needed; see USB_STORAGE Help for more info
1386+#
1387+CONFIG_USB_STORAGE=m
1388+# CONFIG_USB_STORAGE_DEBUG is not set
1389+CONFIG_USB_STORAGE_DATAFAB=m
1390+CONFIG_USB_STORAGE_FREECOM=m
1391+CONFIG_USB_STORAGE_ISD200=m
1392+CONFIG_USB_STORAGE_USBAT=m
1393+CONFIG_USB_STORAGE_SDDR09=m
1394+CONFIG_USB_STORAGE_SDDR55=m
1395+CONFIG_USB_STORAGE_JUMPSHOT=m
1396+CONFIG_USB_STORAGE_ALAUDA=m
1397+# CONFIG_USB_STORAGE_ONETOUCH is not set
1398+# CONFIG_USB_STORAGE_KARMA is not set
1399+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
1400+# CONFIG_USB_LIBUSUAL is not set
1401+
1402+#
1403+# USB Imaging devices
1404+#
1405+# CONFIG_USB_MDC800 is not set
1406+# CONFIG_USB_MICROTEK is not set
1407+
1408+#
1409+# USB port drivers
1410+#
1411+CONFIG_USB_SERIAL=m
1412+# CONFIG_USB_EZUSB is not set
1413+CONFIG_USB_SERIAL_GENERIC=y
1414+# CONFIG_USB_SERIAL_AIRCABLE is not set
1415+# CONFIG_USB_SERIAL_ARK3116 is not set
1416+# CONFIG_USB_SERIAL_BELKIN is not set
1417+# CONFIG_USB_SERIAL_CH341 is not set
1418+# CONFIG_USB_SERIAL_WHITEHEAT is not set
1419+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
1420+# CONFIG_USB_SERIAL_CP210X is not set
1421+# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
1422+# CONFIG_USB_SERIAL_EMPEG is not set
1423+# CONFIG_USB_SERIAL_FTDI_SIO is not set
1424+# CONFIG_USB_SERIAL_FUNSOFT is not set
1425+# CONFIG_USB_SERIAL_VISOR is not set
1426+# CONFIG_USB_SERIAL_IPAQ is not set
1427+# CONFIG_USB_SERIAL_IR is not set
1428+# CONFIG_USB_SERIAL_EDGEPORT is not set
1429+# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
1430+# CONFIG_USB_SERIAL_GARMIN is not set
1431+# CONFIG_USB_SERIAL_IPW is not set
1432+# CONFIG_USB_SERIAL_IUU is not set
1433+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
1434+# CONFIG_USB_SERIAL_KEYSPAN is not set
1435+# CONFIG_USB_SERIAL_KLSI is not set
1436+# CONFIG_USB_SERIAL_KOBIL_SCT is not set
1437+# CONFIG_USB_SERIAL_MCT_U232 is not set
1438+# CONFIG_USB_SERIAL_MOS7720 is not set
1439+# CONFIG_USB_SERIAL_MOS7840 is not set
1440+# CONFIG_USB_SERIAL_MOTOROLA is not set
1441+# CONFIG_USB_SERIAL_NAVMAN is not set
1442+# CONFIG_USB_SERIAL_PL2303 is not set
1443+# CONFIG_USB_SERIAL_OTI6858 is not set
1444+# CONFIG_USB_SERIAL_QUALCOMM is not set
1445+# CONFIG_USB_SERIAL_SPCP8X5 is not set
1446+# CONFIG_USB_SERIAL_HP4X is not set
1447+# CONFIG_USB_SERIAL_SAFE is not set
1448+# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
1449+# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
1450+# CONFIG_USB_SERIAL_SYMBOL is not set
1451+# CONFIG_USB_SERIAL_TI is not set
1452+# CONFIG_USB_SERIAL_CYBERJACK is not set
1453+# CONFIG_USB_SERIAL_XIRCOM is not set
1454+# CONFIG_USB_SERIAL_OPTION is not set
1455+# CONFIG_USB_SERIAL_OMNINET is not set
1456+# CONFIG_USB_SERIAL_OPTICON is not set
1457+# CONFIG_USB_SERIAL_DEBUG is not set
1458+
1459+#
1460+# USB Miscellaneous drivers
1461+#
1462+# CONFIG_USB_EMI62 is not set
1463+# CONFIG_USB_EMI26 is not set
1464+# CONFIG_USB_ADUTUX is not set
1465+# CONFIG_USB_SEVSEG is not set
1466+# CONFIG_USB_RIO500 is not set
1467+# CONFIG_USB_LEGOTOWER is not set
1468+# CONFIG_USB_LCD is not set
1469+# CONFIG_USB_BERRY_CHARGE is not set
1470+# CONFIG_USB_LED is not set
1471+# CONFIG_USB_CYPRESS_CY7C63 is not set
1472+# CONFIG_USB_CYTHERM is not set
1473+# CONFIG_USB_IDMOUSE is not set
1474+# CONFIG_USB_FTDI_ELAN is not set
1475+# CONFIG_USB_APPLEDISPLAY is not set
1476+# CONFIG_USB_SISUSBVGA is not set
1477+# CONFIG_USB_LD is not set
1478+# CONFIG_USB_TRANCEVIBRATOR is not set
1479+# CONFIG_USB_IOWARRIOR is not set
1480+# CONFIG_USB_TEST is not set
1481+# CONFIG_USB_ISIGHTFW is not set
1482+# CONFIG_USB_VST is not set
1483+# CONFIG_USB_GADGET is not set
1484+
1485+#
1486+# OTG and related infrastructure
1487+#
1488+# CONFIG_NOP_USB_XCEIV is not set
1489+# CONFIG_UWB is not set
1490+# CONFIG_MMC is not set
1491+# CONFIG_MEMSTICK is not set
1492+# CONFIG_NEW_LEDS is not set
1493+# CONFIG_ACCESSIBILITY is not set
1494+# CONFIG_INFINIBAND is not set
1495+# CONFIG_RTC_CLASS is not set
1496+# CONFIG_DMADEVICES is not set
1497+# CONFIG_AUXDISPLAY is not set
1498+# CONFIG_UIO is not set
1499+
1500+#
1501+# TI VLYNQ
1502+#
1503+CONFIG_STAGING=y
1504+# CONFIG_STAGING_EXCLUDE_BUILD is not set
1505+# CONFIG_ET131X is not set
1506+# CONFIG_USB_IP_COMMON is not set
1507+# CONFIG_PRISM2_USB is not set
1508+# CONFIG_ECHO is not set
1509+# CONFIG_COMEDI is not set
1510+# CONFIG_ASUS_OLED is not set
1511+# CONFIG_ALTERA_PCIE_CHDMA is not set
1512+# CONFIG_RTL8187SE is not set
1513+# CONFIG_RTL8192SU is not set
1514+# CONFIG_RTL8192E is not set
1515+# CONFIG_INPUT_MIMIO is not set
1516+# CONFIG_TRANZPORT is not set
1517+
1518+#
1519+# Android
1520+#
1521+
1522+#
1523+# Qualcomm MSM Camera And Video
1524+#
1525+
1526+#
1527+# Camera Sensor Selection
1528+#
1529+# CONFIG_INPUT_GPIO is not set
1530+# CONFIG_DST is not set
1531+# CONFIG_POHMELFS is not set
1532+# CONFIG_B3DFG is not set
1533+# CONFIG_PLAN9AUTH is not set
1534+# CONFIG_LINE6_USB is not set
1535+# CONFIG_USB_SERIAL_QUATECH2 is not set
1536+# CONFIG_USB_SERIAL_QUATECH_USB2 is not set
1537+# CONFIG_VT6655 is not set
1538+# CONFIG_VT6656 is not set
1539+# CONFIG_FB_UDL is not set
1540+# CONFIG_VME_BUS is not set
1541+
1542+#
1543+# RAR Register Driver
1544+#
1545+# CONFIG_RAR_REGISTER is not set
1546+# CONFIG_IIO is not set
1547+CONFIG_FB_SM7XX=y
1548+CONFIG_FB_SM7XX_ACCEL=y
1549+
1550+#
1551+# File systems
1552+#
1553+# CONFIG_EXT2_FS is not set
1554+CONFIG_EXT3_FS=y
1555+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
1556+CONFIG_EXT3_FS_XATTR=y
1557+CONFIG_EXT3_FS_POSIX_ACL=y
1558+CONFIG_EXT3_FS_SECURITY=y
1559+# CONFIG_EXT4_FS is not set
1560+CONFIG_JBD=y
1561+CONFIG_FS_MBCACHE=y
1562+# CONFIG_REISERFS_FS is not set
1563+# CONFIG_JFS_FS is not set
1564+CONFIG_FS_POSIX_ACL=y
1565+# CONFIG_XFS_FS is not set
1566+# CONFIG_GFS2_FS is not set
1567+# CONFIG_OCFS2_FS is not set
1568+# CONFIG_BTRFS_FS is not set
1569+# CONFIG_NILFS2_FS is not set
1570+CONFIG_FILE_LOCKING=y
1571+CONFIG_FSNOTIFY=y
1572+CONFIG_DNOTIFY=y
1573+CONFIG_INOTIFY=y
1574+CONFIG_INOTIFY_USER=y
1575+CONFIG_QUOTA=y
1576+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
1577+CONFIG_PRINT_QUOTA_WARNING=y
1578+# CONFIG_QFMT_V1 is not set
1579+# CONFIG_QFMT_V2 is not set
1580+CONFIG_QUOTACTL=y
1581+# CONFIG_AUTOFS_FS is not set
1582+# CONFIG_AUTOFS4_FS is not set
1583+# CONFIG_FUSE_FS is not set
1584+
1585+#
1586+# Caches
1587+#
1588+# CONFIG_FSCACHE is not set
1589+
1590+#
1591+# CD-ROM/DVD Filesystems
1592+#
1593+CONFIG_ISO9660_FS=m
1594+CONFIG_JOLIET=y
1595+CONFIG_ZISOFS=y
1596+# CONFIG_UDF_FS is not set
1597+
1598+#
1599+# DOS/FAT/NT Filesystems
1600+#
1601+CONFIG_FAT_FS=m
1602+# CONFIG_MSDOS_FS is not set
1603+CONFIG_VFAT_FS=m
1604+CONFIG_FAT_DEFAULT_CODEPAGE=437
1605+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1606+# CONFIG_NTFS_FS is not set
1607+
1608+#
1609+# Pseudo filesystems
1610+#
1611+CONFIG_PROC_FS=y
1612+CONFIG_PROC_KCORE=y
1613+CONFIG_PROC_SYSCTL=y
1614+CONFIG_PROC_PAGE_MONITOR=y
1615+CONFIG_SYSFS=y
1616+CONFIG_TMPFS=y
1617+# CONFIG_TMPFS_POSIX_ACL is not set
1618+# CONFIG_HUGETLB_PAGE is not set
1619+# CONFIG_CONFIGFS_FS is not set
1620+# CONFIG_MISC_FILESYSTEMS is not set
1621+CONFIG_NETWORK_FILESYSTEMS=y
1622+CONFIG_NFS_FS=m
1623+CONFIG_NFS_V3=y
1624+CONFIG_NFS_V3_ACL=y
1625+# CONFIG_NFS_V4 is not set
1626+# CONFIG_NFSD is not set
1627+CONFIG_LOCKD=m
1628+CONFIG_LOCKD_V4=y
1629+CONFIG_NFS_ACL_SUPPORT=m
1630+CONFIG_NFS_COMMON=y
1631+CONFIG_SUNRPC=m
1632+# CONFIG_RPCSEC_GSS_KRB5 is not set
1633+# CONFIG_RPCSEC_GSS_SPKM3 is not set
1634+# CONFIG_SMB_FS is not set
1635+# CONFIG_CIFS is not set
1636+# CONFIG_NCP_FS is not set
1637+# CONFIG_CODA_FS is not set
1638+# CONFIG_AFS_FS is not set
1639+
1640+#
1641+# Partition Types
1642+#
1643+# CONFIG_PARTITION_ADVANCED is not set
1644+CONFIG_MSDOS_PARTITION=y
1645+CONFIG_NLS=y
1646+CONFIG_NLS_DEFAULT="utf-8"
1647+# CONFIG_NLS_CODEPAGE_437 is not set
1648+# CONFIG_NLS_CODEPAGE_737 is not set
1649+# CONFIG_NLS_CODEPAGE_775 is not set
1650+# CONFIG_NLS_CODEPAGE_850 is not set
1651+# CONFIG_NLS_CODEPAGE_852 is not set
1652+# CONFIG_NLS_CODEPAGE_855 is not set
1653+# CONFIG_NLS_CODEPAGE_857 is not set
1654+# CONFIG_NLS_CODEPAGE_860 is not set
1655+# CONFIG_NLS_CODEPAGE_861 is not set
1656+# CONFIG_NLS_CODEPAGE_862 is not set
1657+# CONFIG_NLS_CODEPAGE_863 is not set
1658+# CONFIG_NLS_CODEPAGE_864 is not set
1659+# CONFIG_NLS_CODEPAGE_865 is not set
1660+# CONFIG_NLS_CODEPAGE_866 is not set
1661+# CONFIG_NLS_CODEPAGE_869 is not set
1662+# CONFIG_NLS_CODEPAGE_936 is not set
1663+# CONFIG_NLS_CODEPAGE_950 is not set
1664+# CONFIG_NLS_CODEPAGE_932 is not set
1665+# CONFIG_NLS_CODEPAGE_949 is not set
1666+# CONFIG_NLS_CODEPAGE_874 is not set
1667+# CONFIG_NLS_ISO8859_8 is not set
1668+# CONFIG_NLS_CODEPAGE_1250 is not set
1669+# CONFIG_NLS_CODEPAGE_1251 is not set
1670+# CONFIG_NLS_ASCII is not set
1671+# CONFIG_NLS_ISO8859_1 is not set
1672+# CONFIG_NLS_ISO8859_2 is not set
1673+# CONFIG_NLS_ISO8859_3 is not set
1674+# CONFIG_NLS_ISO8859_4 is not set
1675+# CONFIG_NLS_ISO8859_5 is not set
1676+# CONFIG_NLS_ISO8859_6 is not set
1677+# CONFIG_NLS_ISO8859_7 is not set
1678+# CONFIG_NLS_ISO8859_9 is not set
1679+# CONFIG_NLS_ISO8859_13 is not set
1680+# CONFIG_NLS_ISO8859_14 is not set
1681+# CONFIG_NLS_ISO8859_15 is not set
1682+# CONFIG_NLS_KOI8_R is not set
1683+# CONFIG_NLS_KOI8_U is not set
1684+# CONFIG_NLS_UTF8 is not set
1685+# CONFIG_DLM is not set
1686+
1687+#
1688+# Kernel hacking
1689+#
1690+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
1691+CONFIG_PRINTK_TIME=y
1692+CONFIG_ENABLE_WARN_DEPRECATED=y
1693+CONFIG_ENABLE_MUST_CHECK=y
1694+CONFIG_FRAME_WARN=1024
1695+# CONFIG_MAGIC_SYSRQ is not set
1696+CONFIG_STRIP_ASM_SYMS=y
1697+# CONFIG_UNUSED_SYMBOLS is not set
1698+# CONFIG_DEBUG_FS is not set
1699+# CONFIG_HEADERS_CHECK is not set
1700+# CONFIG_DEBUG_KERNEL is not set
1701+# CONFIG_SLUB_DEBUG_ON is not set
1702+# CONFIG_SLUB_STATS is not set
1703+# CONFIG_DEBUG_MEMORY_INIT is not set
1704+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1705+CONFIG_SYSCTL_SYSCALL_CHECK=y
1706+CONFIG_TRACING_SUPPORT=y
1707+# CONFIG_FTRACE is not set
1708+# CONFIG_SAMPLES is not set
1709+CONFIG_HAVE_ARCH_KGDB=y
1710+# CONFIG_CMDLINE_BOOL is not set
1711+
1712+#
1713+# Security options
1714+#
1715+# CONFIG_KEYS is not set
1716+# CONFIG_SECURITY is not set
1717+# CONFIG_SECURITYFS is not set
1718+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1719+CONFIG_CRYPTO=y
1720+
1721+#
1722+# Crypto core or helper
1723+#
1724+CONFIG_CRYPTO_ALGAPI=y
1725+CONFIG_CRYPTO_ALGAPI2=y
1726+CONFIG_CRYPTO_AEAD2=y
1727+CONFIG_CRYPTO_BLKCIPHER=y
1728+CONFIG_CRYPTO_BLKCIPHER2=y
1729+CONFIG_CRYPTO_HASH2=y
1730+CONFIG_CRYPTO_RNG2=y
1731+CONFIG_CRYPTO_PCOMP=y
1732+CONFIG_CRYPTO_MANAGER=y
1733+CONFIG_CRYPTO_MANAGER2=y
1734+# CONFIG_CRYPTO_GF128MUL is not set
1735+# CONFIG_CRYPTO_NULL is not set
1736+CONFIG_CRYPTO_WORKQUEUE=y
1737+# CONFIG_CRYPTO_CRYPTD is not set
1738+# CONFIG_CRYPTO_AUTHENC is not set
1739+# CONFIG_CRYPTO_TEST is not set
1740+
1741+#
1742+# Authenticated Encryption with Associated Data
1743+#
1744+# CONFIG_CRYPTO_CCM is not set
1745+# CONFIG_CRYPTO_GCM is not set
1746+# CONFIG_CRYPTO_SEQIV is not set
1747+
1748+#
1749+# Block modes
1750+#
1751+CONFIG_CRYPTO_CBC=y
1752+# CONFIG_CRYPTO_CTR is not set
1753+# CONFIG_CRYPTO_CTS is not set
1754+# CONFIG_CRYPTO_ECB is not set
1755+# CONFIG_CRYPTO_LRW is not set
1756+# CONFIG_CRYPTO_PCBC is not set
1757+# CONFIG_CRYPTO_XTS is not set
1758+
1759+#
1760+# Hash modes
1761+#
1762+# CONFIG_CRYPTO_HMAC is not set
1763+# CONFIG_CRYPTO_XCBC is not set
1764+# CONFIG_CRYPTO_VMAC is not set
1765+
1766+#
1767+# Digest
1768+#
1769+# CONFIG_CRYPTO_CRC32C is not set
1770+# CONFIG_CRYPTO_GHASH is not set
1771+# CONFIG_CRYPTO_MD4 is not set
1772+# CONFIG_CRYPTO_MD5 is not set
1773+# CONFIG_CRYPTO_MICHAEL_MIC is not set
1774+# CONFIG_CRYPTO_RMD128 is not set
1775+# CONFIG_CRYPTO_RMD160 is not set
1776+# CONFIG_CRYPTO_RMD256 is not set
1777+# CONFIG_CRYPTO_RMD320 is not set
1778+# CONFIG_CRYPTO_SHA1 is not set
1779+# CONFIG_CRYPTO_SHA256 is not set
1780+# CONFIG_CRYPTO_SHA512 is not set
1781+# CONFIG_CRYPTO_TGR192 is not set
1782+# CONFIG_CRYPTO_WP512 is not set
1783+
1784+#
1785+# Ciphers
1786+#
1787+# CONFIG_CRYPTO_AES is not set
1788+# CONFIG_CRYPTO_ANUBIS is not set
1789+# CONFIG_CRYPTO_ARC4 is not set
1790+# CONFIG_CRYPTO_BLOWFISH is not set
1791+# CONFIG_CRYPTO_CAMELLIA is not set
1792+# CONFIG_CRYPTO_CAST5 is not set
1793+# CONFIG_CRYPTO_CAST6 is not set
1794+# CONFIG_CRYPTO_DES is not set
1795+# CONFIG_CRYPTO_FCRYPT is not set
1796+# CONFIG_CRYPTO_KHAZAD is not set
1797+# CONFIG_CRYPTO_SALSA20 is not set
1798+# CONFIG_CRYPTO_SEED is not set
1799+# CONFIG_CRYPTO_SERPENT is not set
1800+# CONFIG_CRYPTO_TEA is not set
1801+# CONFIG_CRYPTO_TWOFISH is not set
1802+
1803+#
1804+# Compression
1805+#
1806+# CONFIG_CRYPTO_DEFLATE is not set
1807+# CONFIG_CRYPTO_ZLIB is not set
1808+# CONFIG_CRYPTO_LZO is not set
1809+
1810+#
1811+# Random Number Generation
1812+#
1813+# CONFIG_CRYPTO_ANSI_CPRNG is not set
1814+CONFIG_CRYPTO_HW=y
1815+# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1816+# CONFIG_BINARY_PRINTF is not set
1817+
1818+#
1819+# Library routines
1820+#
1821+CONFIG_BITREVERSE=y
1822+CONFIG_GENERIC_FIND_LAST_BIT=y
1823+# CONFIG_CRC_CCITT is not set
1824+# CONFIG_CRC16 is not set
1825+CONFIG_CRC_T10DIF=y
1826+# CONFIG_CRC_ITU_T is not set
1827+CONFIG_CRC32=y
1828+# CONFIG_CRC7 is not set
1829+# CONFIG_LIBCRC32C is not set
1830+CONFIG_AUDIT_GENERIC=y
1831+CONFIG_ZLIB_INFLATE=m
1832+CONFIG_HAS_IOMEM=y
1833+CONFIG_HAS_IOPORT=y
1834+CONFIG_HAS_DMA=y
1835+CONFIG_NLATTR=y
arch/mips/configs/malta_defconfig+1−2
@@ -10,7 +10,6 @@ CONFIG_MIPS=y · 9 unmodified lines
1010 #
1111 CONFIG_ZONE_DMA=y
1212 # CONFIG_MACH_ALCHEMY is not set
13−# CONFIG_BASLER_EXCITE is not set
1413 # CONFIG_BCM47XX is not set
1514 # CONFIG_MIPS_COBALT is not set
1615 # CONFIG_MACH_DECSTATION is not set
@@ -1591,7 +1590,7 @@ CONFIG_FRAME_WARN=1024 · 1574 unmodified lines
15911590 # CONFIG_DYNAMIC_PRINTK_DEBUG is not set
15921591 # CONFIG_SAMPLES is not set
15931592 CONFIG_HAVE_ARCH_KGDB=y
1594−CONFIG_CMDLINE=""
1593+# CONFIG_CMDLINE_BOOL is not set
15951594
15961595 #
15971596 # Security options
arch/mips/configs/markeins_defconfig+2−1
@@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y · 21 unmodified lines
2222 # CONFIG_MIPS_DB1550 is not set
2323 # CONFIG_MIPS_DB1200 is not set
2424 # CONFIG_MIPS_MIRAGE is not set
25−# CONFIG_BASLER_EXCITE is not set
2625 # CONFIG_MIPS_COBALT is not set
2726 # CONFIG_MACH_DECSTATION is not set
2827 # CONFIG_MACH_JAZZ is not set
@@ -1366,7 +1365,9 @@ CONFIG_ENABLE_MUST_CHECK=y · 1337 unmodified lines
13661365 # CONFIG_DEBUG_KERNEL is not set
13671366 CONFIG_LOG_BUF_SHIFT=14
13681367 CONFIG_CROSSCOMPILE=y
1368+CONFIG_CMDLINE_BOOL=y
13691369 CONFIG_CMDLINE="console=ttyS0,115200 mem=192m ip=bootp root=/dev/nfs rw"
1370+# CONFIG_CMDLINE_OVERRIDE is not set
13701371
13711372 #
13721373 # Security options
arch/mips/configs/mipssim_defconfig+2−1
@@ -9,7 +9,6 @@ CONFIG_MIPS=y · 8 unmodified lines
99 # Machine selection
1010 #
1111 # CONFIG_MACH_ALCHEMY is not set
12−# CONFIG_BASLER_EXCITE is not set
1312 # CONFIG_BCM47XX is not set
1413 # CONFIG_MIPS_COBALT is not set
1514 # CONFIG_MACH_DECSTATION is not set
@@ -635,7 +634,9 @@ CONFIG_FORCED_INLINING=y · 619 unmodified lines
635634 # CONFIG_RCU_TORTURE_TEST is not set
636635 # CONFIG_FAULT_INJECTION is not set
637636 CONFIG_CROSSCOMPILE=y
637+CONFIG_CMDLINE_BOOL=y
638638 CONFIG_CMDLINE="nfsroot=192.168.192.169:/u1/mipsel,timeo=20 ip=dhcp"
639+# CONFIG_CMDLINE_OVERRIDE is not set
639640 # CONFIG_DEBUG_STACK_USAGE is not set
640641 # CONFIG_RUNTIME_DEBUG is not set
641642
arch/mips/configs/mpc30x_defconfig+2−1
@@ -9,7 +9,6 @@ CONFIG_MIPS=y · 8 unmodified lines
99 # Machine selection
1010 #
1111 # CONFIG_MACH_ALCHEMY is not set
12−# CONFIG_BASLER_EXCITE is not set
1312 # CONFIG_MIPS_COBALT is not set
1413 # CONFIG_MACH_DECSTATION is not set
1514 # CONFIG_MACH_JAZZ is not set
@@ -817,7 +816,9 @@ CONFIG_ENABLE_MUST_CHECK=y · 801 unmodified lines
817816 # CONFIG_HEADERS_CHECK is not set
818817 # CONFIG_DEBUG_KERNEL is not set
819818 CONFIG_CROSSCOMPILE=y
819+CONFIG_CMDLINE_BOOL=y
820820 CONFIG_CMDLINE="mem=32M console=ttyVR0,19200 ide0=0x170,0x376,73"
821+# CONFIG_CMDLINE_OVERRIDE is not set
821822
822823 #
823824 # Security options
arch/mips/configs/msp71xx_defconfig+1−2
@@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y · 21 unmodified lines
2222 # CONFIG_MIPS_DB1550 is not set
2323 # CONFIG_MIPS_DB1200 is not set
2424 # CONFIG_MIPS_MIRAGE is not set
25−# CONFIG_BASLER_EXCITE is not set
2625 # CONFIG_MIPS_COBALT is not set
2726 # CONFIG_MACH_DECSTATION is not set
2827 # CONFIG_MACH_JAZZ is not set
@@ -1412,7 +1411,7 @@ CONFIG_FORCED_INLINING=y · 1383 unmodified lines
14121411 # CONFIG_RCU_TORTURE_TEST is not set
14131412 # CONFIG_FAULT_INJECTION is not set
14141413 CONFIG_CROSSCOMPILE=y
1415−CONFIG_CMDLINE=""
1414+# CONFIG_CMDLINE_BOOL is not set
14161415 # CONFIG_DEBUG_STACK_USAGE is not set
14171416 # CONFIG_RUNTIME_DEBUG is not set
14181417 # CONFIG_MIPS_UNCACHED is not set
arch/mips/configs/mtx1_defconfig+1−2
@@ -9,7 +9,6 @@ CONFIG_MIPS=y · 8 unmodified lines
99 # Machine selection
1010 #
1111 CONFIG_MACH_ALCHEMY=y
12−# CONFIG_BASLER_EXCITE is not set
1312 # CONFIG_MIPS_COBALT is not set
1413 # CONFIG_MACH_DECSTATION is not set
1514 # CONFIG_MACH_JAZZ is not set
@@ -3018,7 +3017,7 @@ CONFIG_MAGIC_SYSRQ=y · 3002 unmodified lines
30183017 # CONFIG_HEADERS_CHECK is not set
30193018 # CONFIG_DEBUG_KERNEL is not set
30203019 CONFIG_CROSSCOMPILE=y
3021−CONFIG_CMDLINE=""
3020+# CONFIG_CMDLINE_BOOL is not set
30223021
30233022 #
30243023 # Security options
arch/mips/configs/pb1100_defconfig+1−2
@@ -23,7 +23,6 @@ CONFIG_MIPS_PB1100=y · 22 unmodified lines
2323 # CONFIG_MIPS_DB1550 is not set
2424 # CONFIG_MIPS_DB1200 is not set
2525 # CONFIG_MIPS_MIRAGE is not set
26−# CONFIG_BASLER_EXCITE is not set
2726 # CONFIG_MIPS_COBALT is not set
2827 # CONFIG_MACH_DECSTATION is not set
2928 # CONFIG_MACH_JAZZ is not set
@@ -1083,7 +1082,7 @@ CONFIG_ENABLE_MUST_CHECK=y · 1053 unmodified lines
10831082 # CONFIG_DEBUG_KERNEL is not set
10841083 CONFIG_LOG_BUF_SHIFT=14
10851084 CONFIG_CROSSCOMPILE=y
1086−CONFIG_CMDLINE=""
1085+# CONFIG_CMDLINE_BOOL is not set
10871086
10881087 #
10891088 # Security options
arch/mips/configs/pb1500_defconfig+1−2
@@ -23,7 +23,6 @@ CONFIG_MIPS_PB1500=y · 22 unmodified lines
2323 # CONFIG_MIPS_DB1550 is not set
2424 # CONFIG_MIPS_DB1200 is not set
2525 # CONFIG_MIPS_MIRAGE is not set
26−# CONFIG_BASLER_EXCITE is not set
2726 # CONFIG_MIPS_COBALT is not set
2827 # CONFIG_MACH_DECSTATION is not set
2928 # CONFIG_MACH_JAZZ is not set
@@ -1200,7 +1199,7 @@ CONFIG_ENABLE_MUST_CHECK=y · 1170 unmodified lines
12001199 # CONFIG_DEBUG_KERNEL is not set
12011200 CONFIG_LOG_BUF_SHIFT=14
12021201 CONFIG_CROSSCOMPILE=y
1203−CONFIG_CMDLINE=""
1202+# CONFIG_CMDLINE_BOOL is not set
12041203
12051204 #
12061205 # Security options
arch/mips/configs/pb1550_defconfig+1−2
@@ -23,7 +23,6 @@ CONFIG_MIPS_PB1550=y · 22 unmodified lines
2323 # CONFIG_MIPS_DB1550 is not set
2424 # CONFIG_MIPS_DB1200 is not set
2525 # CONFIG_MIPS_MIRAGE is not set
26−# CONFIG_BASLER_EXCITE is not set
2726 # CONFIG_MIPS_COBALT is not set
2827 # CONFIG_MACH_DECSTATION is not set
2928 # CONFIG_MACH_JAZZ is not set
@@ -1193,7 +1192,7 @@ CONFIG_ENABLE_MUST_CHECK=y · 1163 unmodified lines
11931192 # CONFIG_DEBUG_KERNEL is not set
11941193 CONFIG_LOG_BUF_SHIFT=14
11951194 CONFIG_CROSSCOMPILE=y
1196−CONFIG_CMDLINE=""
1195+# CONFIG_CMDLINE_BOOL is not set
11971196
11981197 #
11991198 # Security options
arch/mips/configs/pnx8335-stb225_defconfig+1−2
@@ -9,7 +9,6 @@ CONFIG_MIPS=y · 8 unmodified lines
99 # Machine selection
1010 #
1111 # CONFIG_MACH_ALCHEMY is not set
12−# CONFIG_BASLER_EXCITE is not set
1312 # CONFIG_BCM47XX is not set
1413 # CONFIG_MIPS_COBALT is not set
1514 # CONFIG_MACH_DECSTATION is not set
@@ -1034,7 +1033,7 @@ CONFIG_FRAME_WARN=1024 · 1018 unmodified lines
10341033 # CONFIG_DEBUG_KERNEL is not set
10351034 # CONFIG_SAMPLES is not set
10361035 # CONFIG_KERNEL_TESTS is not set
1037−CONFIG_CMDLINE=""
1036+# CONFIG_CMDLINE_BOOL is not set
10381037
10391038 #
10401039 # Security options
arch/mips/configs/pnx8550-jbs_defconfig+2−1
@@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y · 21 unmodified lines
2222 # CONFIG_MIPS_DB1550 is not set
2323 # CONFIG_MIPS_DB1200 is not set
2424 # CONFIG_MIPS_MIRAGE is not set
25−# CONFIG_BASLER_EXCITE is not set
2625 # CONFIG_MIPS_COBALT is not set
2726 # CONFIG_MACH_DECSTATION is not set
2827 # CONFIG_MACH_JAZZ is not set
@@ -1215,7 +1214,9 @@ CONFIG_DEBUG_MUTEXES=y · 1186 unmodified lines
12151214 CONFIG_FORCED_INLINING=y
12161215 # CONFIG_RCU_TORTURE_TEST is not set
12171216 CONFIG_CROSSCOMPILE=y
1217+CONFIG_CMDLINE_BOOL=y
12181218 CONFIG_CMDLINE="console=ttyS1,38400n8 root=/dev/nfs ip=bootp"
1219+# CONFIG_CMDLINE_OVERRIDE is not set
12191220 # CONFIG_DEBUG_STACK_USAGE is not set
12201221 # CONFIG_RUNTIME_DEBUG is not set
12211222
arch/mips/configs/pnx8550-stb810_defconfig+2−1
@@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y · 21 unmodified lines
2222 # CONFIG_MIPS_DB1550 is not set
2323 # CONFIG_MIPS_DB1200 is not set
2424 # CONFIG_MIPS_MIRAGE is not set
25−# CONFIG_BASLER_EXCITE is not set
2625 # CONFIG_MIPS_COBALT is not set
2726 # CONFIG_MACH_DECSTATION is not set
2827 # CONFIG_MACH_JAZZ is not set
@@ -1205,7 +1204,9 @@ CONFIG_DEBUG_SLAB=y · 1176 unmodified lines
12051204 CONFIG_FORCED_INLINING=y
12061205 # CONFIG_RCU_TORTURE_TEST is not set
12071206 CONFIG_CROSSCOMPILE=y
1207+CONFIG_CMDLINE_BOOL=y
12081208 CONFIG_CMDLINE="console=ttyS1,38400n8 root=/dev/nfs ip=bootp"
1209+# CONFIG_CMDLINE_OVERRIDE is not set
12091210 # CONFIG_DEBUG_STACK_USAGE is not set
12101211 # CONFIG_RUNTIME_DEBUG is not set
12111212
arch/mips/configs/powertv_defconfig+1550−0
@@ -0,0 +1,1550 @@
1+#
2+# Automatically generated make config: don't edit
3+# Linux kernel version: 2.6.31-rc5
4+# Fri Aug 28 14:49:33 2009
5+#
6+CONFIG_MIPS=y
7+
8+#
9+# Machine selection
10+#
11+# CONFIG_MACH_ALCHEMY is not set
12+# CONFIG_AR7 is not set
13+# CONFIG_BCM47XX is not set
14+# CONFIG_MIPS_COBALT is not set
15+# CONFIG_MACH_DECSTATION is not set
16+# CONFIG_MACH_JAZZ is not set
17+# CONFIG_LASAT is not set
18+# CONFIG_LEMOTE_FULONG is not set
19+# CONFIG_MIPS_MALTA is not set
20+# CONFIG_MIPS_SIM is not set
21+# CONFIG_NEC_MARKEINS is not set
22+# CONFIG_MACH_VR41XX is not set
23+# CONFIG_NXP_STB220 is not set
24+# CONFIG_NXP_STB225 is not set
25+# CONFIG_PNX8550_JBS is not set
26+# CONFIG_PNX8550_STB810 is not set
27+# CONFIG_PMC_MSP is not set
28+# CONFIG_PMC_YOSEMITE is not set
29+CONFIG_POWERTV=y
30+# CONFIG_SGI_IP22 is not set
31+# CONFIG_SGI_IP27 is not set
32+# CONFIG_SGI_IP28 is not set
33+# CONFIG_SGI_IP32 is not set
34+# CONFIG_SIBYTE_CRHINE is not set
35+# CONFIG_SIBYTE_CARMEL is not set
36+# CONFIG_SIBYTE_CRHONE is not set
37+# CONFIG_SIBYTE_RHONE is not set
38+# CONFIG_SIBYTE_SWARM is not set
39+# CONFIG_SIBYTE_LITTLESUR is not set
40+# CONFIG_SIBYTE_SENTOSA is not set
41+# CONFIG_SIBYTE_BIGSUR is not set
42+# CONFIG_SNI_RM is not set
43+# CONFIG_MACH_TX39XX is not set
44+# CONFIG_MACH_TX49XX is not set
45+# CONFIG_MIKROTIK_RB532 is not set
46+# CONFIG_WR_PPMC is not set
47+# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
48+# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
49+# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
50+# CONFIG_MIN_RUNTIME_RESOURCES is not set
51+# CONFIG_BOOTLOADER_DRIVER is not set
52+CONFIG_BOOTLOADER_FAMILY="R2"
53+CONFIG_CSRC_POWERTV=y
54+CONFIG_RWSEM_GENERIC_SPINLOCK=y
55+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
56+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
57+CONFIG_ARCH_SUPPORTS_OPROFILE=y
58+CONFIG_GENERIC_FIND_NEXT_BIT=y
59+CONFIG_GENERIC_HWEIGHT=y
60+CONFIG_GENERIC_CALIBRATE_DELAY=y
61+CONFIG_GENERIC_CLOCKEVENTS=y
62+CONFIG_GENERIC_TIME=y
63+CONFIG_GENERIC_CMOS_UPDATE=y
64+CONFIG_SCHED_OMIT_FRAME_POINTER=y
65+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
66+CONFIG_CEVT_R4K_LIB=y
67+CONFIG_CEVT_R4K=y
68+CONFIG_DMA_NONCOHERENT=y
69+CONFIG_DMA_NEED_PCI_MAP_STATE=y
70+# CONFIG_EARLY_PRINTK is not set
71+CONFIG_SYS_HAS_EARLY_PRINTK=y
72+# CONFIG_NO_IOPORT is not set
73+CONFIG_CPU_BIG_ENDIAN=y
74+# CONFIG_CPU_LITTLE_ENDIAN is not set
75+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
76+CONFIG_BOOT_ELF32=y
77+CONFIG_MIPS_L1_CACHE_SHIFT=5
78+
79+#
80+# CPU selection
81+#
82+# CONFIG_CPU_LOONGSON2 is not set
83+# CONFIG_CPU_MIPS32_R1 is not set
84+CONFIG_CPU_MIPS32_R2=y
85+# CONFIG_CPU_MIPS64_R1 is not set
86+# CONFIG_CPU_MIPS64_R2 is not set
87+# CONFIG_CPU_R3000 is not set
88+# CONFIG_CPU_TX39XX is not set
89+# CONFIG_CPU_VR41XX is not set
90+# CONFIG_CPU_R4300 is not set
91+# CONFIG_CPU_R4X00 is not set
92+# CONFIG_CPU_TX49XX is not set
93+# CONFIG_CPU_R5000 is not set
94+# CONFIG_CPU_R5432 is not set
95+# CONFIG_CPU_R5500 is not set
96+# CONFIG_CPU_R6000 is not set
97+# CONFIG_CPU_NEVADA is not set
98+# CONFIG_CPU_R8000 is not set
99+# CONFIG_CPU_R10000 is not set
100+# CONFIG_CPU_RM7000 is not set
101+# CONFIG_CPU_RM9000 is not set
102+# CONFIG_CPU_SB1 is not set
103+# CONFIG_CPU_CAVIUM_OCTEON is not set
104+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
105+CONFIG_CPU_MIPS32=y
106+CONFIG_CPU_MIPSR2=y
107+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
108+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
109+CONFIG_HARDWARE_WATCHPOINTS=y
110+
111+#
112+# Kernel type
113+#
114+CONFIG_32BIT=y
115+# CONFIG_64BIT is not set
116+CONFIG_PAGE_SIZE_4KB=y
117+# CONFIG_PAGE_SIZE_8KB is not set
118+# CONFIG_PAGE_SIZE_16KB is not set
119+# CONFIG_PAGE_SIZE_32KB is not set
120+# CONFIG_PAGE_SIZE_64KB is not set
121+CONFIG_CPU_HAS_PREFETCH=y
122+CONFIG_MIPS_MT_DISABLED=y
123+# CONFIG_MIPS_MT_SMP is not set
124+# CONFIG_MIPS_MT_SMTC is not set
125+CONFIG_CPU_HAS_LLSC=y
126+CONFIG_CPU_MIPSR2_IRQ_VI=y
127+CONFIG_CPU_MIPSR2_IRQ_EI=y
128+CONFIG_CPU_HAS_SYNC=y
129+CONFIG_GENERIC_HARDIRQS=y
130+CONFIG_GENERIC_IRQ_PROBE=y
131+# CONFIG_HIGHMEM is not set
132+CONFIG_CPU_SUPPORTS_HIGHMEM=y
133+CONFIG_SYS_SUPPORTS_HIGHMEM=y
134+CONFIG_ARCH_FLATMEM_ENABLE=y
135+CONFIG_ARCH_POPULATES_NODE_MAP=y
136+CONFIG_SELECT_MEMORY_MODEL=y
137+CONFIG_FLATMEM_MANUAL=y
138+# CONFIG_DISCONTIGMEM_MANUAL is not set
139+# CONFIG_SPARSEMEM_MANUAL is not set
140+CONFIG_FLATMEM=y
141+CONFIG_FLAT_NODE_MEM_MAP=y
142+CONFIG_PAGEFLAGS_EXTENDED=y
143+CONFIG_SPLIT_PTLOCK_CPUS=4
144+# CONFIG_PHYS_ADDR_T_64BIT is not set
145+CONFIG_ZONE_DMA_FLAG=0
146+CONFIG_VIRT_TO_BUS=y
147+CONFIG_HAVE_MLOCK=y
148+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
149+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
150+CONFIG_TICK_ONESHOT=y
151+CONFIG_NO_HZ=y
152+CONFIG_HIGH_RES_TIMERS=y
153+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
154+# CONFIG_HZ_48 is not set
155+# CONFIG_HZ_100 is not set
156+# CONFIG_HZ_128 is not set
157+# CONFIG_HZ_250 is not set
158+# CONFIG_HZ_256 is not set
159+CONFIG_HZ_1000=y
160+# CONFIG_HZ_1024 is not set
161+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
162+CONFIG_HZ=1000
163+# CONFIG_PREEMPT_NONE is not set
164+# CONFIG_PREEMPT_VOLUNTARY is not set
165+CONFIG_PREEMPT=y
166+# CONFIG_KEXEC is not set
167+# CONFIG_SECCOMP is not set
168+CONFIG_LOCKDEP_SUPPORT=y
169+CONFIG_STACKTRACE_SUPPORT=y
170+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
171+CONFIG_CONSTRUCTORS=y
172+
173+#
174+# General setup
175+#
176+CONFIG_EXPERIMENTAL=y
177+CONFIG_BROKEN_ON_SMP=y
178+CONFIG_LOCK_KERNEL=y
179+CONFIG_INIT_ENV_ARG_LIMIT=32
180+CONFIG_LOCALVERSION=""
181+CONFIG_LOCALVERSION_AUTO=y
182+# CONFIG_SWAP is not set
183+CONFIG_SYSVIPC=y
184+CONFIG_SYSVIPC_SYSCTL=y
185+# CONFIG_POSIX_MQUEUE is not set
186+# CONFIG_BSD_PROCESS_ACCT is not set
187+# CONFIG_TASKSTATS is not set
188+# CONFIG_AUDIT is not set
189+
190+#
191+# RCU Subsystem
192+#
193+CONFIG_CLASSIC_RCU=y
194+# CONFIG_TREE_RCU is not set
195+# CONFIG_PREEMPT_RCU is not set
196+# CONFIG_TREE_RCU_TRACE is not set
197+# CONFIG_PREEMPT_RCU_TRACE is not set
198+# CONFIG_IKCONFIG is not set
199+CONFIG_LOG_BUF_SHIFT=16
200+CONFIG_GROUP_SCHED=y
201+CONFIG_FAIR_GROUP_SCHED=y
202+# CONFIG_RT_GROUP_SCHED is not set
203+CONFIG_USER_SCHED=y
204+# CONFIG_CGROUP_SCHED is not set
205+# CONFIG_CGROUPS is not set
206+# CONFIG_SYSFS_DEPRECATED_V2 is not set
207+CONFIG_RELAY=y
208+# CONFIG_NAMESPACES is not set
209+CONFIG_BLK_DEV_INITRD=y
210+CONFIG_INITRAMFS_SOURCE=""
211+# CONFIG_RD_GZIP is not set
212+# CONFIG_RD_BZIP2 is not set
213+# CONFIG_RD_LZMA is not set
214+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
215+CONFIG_SYSCTL=y
216+CONFIG_ANON_INODES=y
217+CONFIG_EMBEDDED=y
218+# CONFIG_SYSCTL_SYSCALL is not set
219+CONFIG_KALLSYMS=y
220+CONFIG_KALLSYMS_ALL=y
221+# CONFIG_KALLSYMS_EXTRA_PASS is not set
222+CONFIG_HOTPLUG=y
223+CONFIG_PRINTK=y
224+CONFIG_BUG=y
225+CONFIG_ELF_CORE=y
226+# CONFIG_PCSPKR_PLATFORM is not set
227+CONFIG_BASE_FULL=y
228+CONFIG_FUTEX=y
229+# CONFIG_EPOLL is not set
230+# CONFIG_SIGNALFD is not set
231+CONFIG_TIMERFD=y
232+# CONFIG_EVENTFD is not set
233+CONFIG_SHMEM=y
234+CONFIG_AIO=y
235+
236+#
237+# Performance Counters
238+#
239+# CONFIG_VM_EVENT_COUNTERS is not set
240+CONFIG_PCI_QUIRKS=y
241+# CONFIG_SLUB_DEBUG is not set
242+# CONFIG_STRIP_ASM_SYMS is not set
243+CONFIG_COMPAT_BRK=y
244+# CONFIG_SLAB is not set
245+CONFIG_SLUB=y
246+# CONFIG_SLOB is not set
247+# CONFIG_PROFILING is not set
248+# CONFIG_MARKERS is not set
249+CONFIG_HAVE_OPROFILE=y
250+
251+#
252+# GCOV-based kernel profiling
253+#
254+# CONFIG_GCOV_KERNEL is not set
255+# CONFIG_SLOW_WORK is not set
256+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
257+CONFIG_RT_MUTEXES=y
258+CONFIG_BASE_SMALL=0
259+CONFIG_MODULES=y
260+# CONFIG_MODULE_FORCE_LOAD is not set
261+CONFIG_MODULE_UNLOAD=y
262+# CONFIG_MODULE_FORCE_UNLOAD is not set
263+CONFIG_MODVERSIONS=y
264+CONFIG_MODULE_SRCVERSION_ALL=y
265+CONFIG_BLOCK=y
266+CONFIG_LBDAF=y
267+# CONFIG_BLK_DEV_BSG is not set
268+# CONFIG_BLK_DEV_INTEGRITY is not set
269+
270+#
271+# IO Schedulers
272+#
273+CONFIG_IOSCHED_NOOP=y
274+# CONFIG_IOSCHED_AS is not set
275+# CONFIG_IOSCHED_DEADLINE is not set
276+# CONFIG_IOSCHED_CFQ is not set
277+# CONFIG_DEFAULT_AS is not set
278+# CONFIG_DEFAULT_DEADLINE is not set
279+# CONFIG_DEFAULT_CFQ is not set
280+CONFIG_DEFAULT_NOOP=y
281+CONFIG_DEFAULT_IOSCHED="noop"
282+# CONFIG_PROBE_INITRD_HEADER is not set
283+# CONFIG_FREEZER is not set
284+
285+#
286+# Bus options (PCI, PCMCIA, EISA, ISA, TC)
287+#
288+CONFIG_HW_HAS_PCI=y
289+CONFIG_PCI=y
290+CONFIG_PCI_DOMAINS=y
291+# CONFIG_ARCH_SUPPORTS_MSI is not set
292+# CONFIG_PCI_LEGACY is not set
293+# CONFIG_PCI_DEBUG is not set
294+# CONFIG_PCI_STUB is not set
295+# CONFIG_PCI_IOV is not set
296+CONFIG_MMU=y
297+# CONFIG_PCCARD is not set
298+# CONFIG_HOTPLUG_PCI is not set
299+
300+#
301+# Executable file formats
302+#
303+CONFIG_BINFMT_ELF=y
304+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
305+# CONFIG_HAVE_AOUT is not set
306+# CONFIG_BINFMT_MISC is not set
307+CONFIG_TRAD_SIGNALS=y
308+
309+#
310+# Power management options
311+#
312+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
313+CONFIG_ARCH_SUSPEND_POSSIBLE=y
314+# CONFIG_PM is not set
315+CONFIG_NET=y
316+
317+#
318+# Networking options
319+#
320+CONFIG_PACKET=y
321+CONFIG_PACKET_MMAP=y
322+CONFIG_UNIX=y
323+CONFIG_XFRM=y
324+# CONFIG_XFRM_USER is not set
325+# CONFIG_XFRM_SUB_POLICY is not set
326+# CONFIG_XFRM_MIGRATE is not set
327+# CONFIG_XFRM_STATISTICS is not set
328+CONFIG_XFRM_IPCOMP=y
329+# CONFIG_NET_KEY is not set
330+CONFIG_INET=y
331+CONFIG_IP_MULTICAST=y
332+CONFIG_IP_ADVANCED_ROUTER=y
333+CONFIG_ASK_IP_FIB_HASH=y
334+# CONFIG_IP_FIB_TRIE is not set
335+CONFIG_IP_FIB_HASH=y
336+# CONFIG_IP_MULTIPLE_TABLES is not set
337+# CONFIG_IP_ROUTE_MULTIPATH is not set
338+# CONFIG_IP_ROUTE_VERBOSE is not set
339+CONFIG_IP_PNP=y
340+# CONFIG_IP_PNP_DHCP is not set
341+# CONFIG_IP_PNP_BOOTP is not set
342+# CONFIG_IP_PNP_RARP is not set
343+# CONFIG_NET_IPIP is not set
344+# CONFIG_NET_IPGRE is not set
345+# CONFIG_IP_MROUTE is not set
346+# CONFIG_ARPD is not set
347+CONFIG_SYN_COOKIES=y
348+# CONFIG_INET_AH is not set
349+# CONFIG_INET_ESP is not set
350+# CONFIG_INET_IPCOMP is not set
351+# CONFIG_INET_XFRM_TUNNEL is not set
352+# CONFIG_INET_TUNNEL is not set
353+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
354+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
355+# CONFIG_INET_XFRM_MODE_BEET is not set
356+# CONFIG_INET_LRO is not set
357+# CONFIG_INET_DIAG is not set
358+# CONFIG_TCP_CONG_ADVANCED is not set
359+CONFIG_TCP_CONG_CUBIC=y
360+CONFIG_DEFAULT_TCP_CONG="cubic"
361+# CONFIG_TCP_MD5SIG is not set
362+CONFIG_IPV6=y
363+CONFIG_IPV6_PRIVACY=y
364+# CONFIG_IPV6_ROUTER_PREF is not set
365+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
366+CONFIG_INET6_AH=y
367+CONFIG_INET6_ESP=y
368+CONFIG_INET6_IPCOMP=y
369+# CONFIG_IPV6_MIP6 is not set
370+CONFIG_INET6_XFRM_TUNNEL=y
371+CONFIG_INET6_TUNNEL=y
372+# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
373+# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
374+# CONFIG_INET6_XFRM_MODE_BEET is not set
375+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
376+# CONFIG_IPV6_SIT is not set
377+CONFIG_IPV6_TUNNEL=y
378+# CONFIG_IPV6_MULTIPLE_TABLES is not set
379+# CONFIG_IPV6_MROUTE is not set
380+# CONFIG_NETWORK_SECMARK is not set
381+CONFIG_NETFILTER=y
382+# CONFIG_NETFILTER_DEBUG is not set
383+CONFIG_NETFILTER_ADVANCED=y
384+# CONFIG_BRIDGE_NETFILTER is not set
385+
386+#
387+# Core Netfilter Configuration
388+#
389+# CONFIG_NETFILTER_NETLINK_QUEUE is not set
390+# CONFIG_NETFILTER_NETLINK_LOG is not set
391+# CONFIG_NF_CONNTRACK is not set
392+CONFIG_NETFILTER_XTABLES=y
393+# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set
394+# CONFIG_NETFILTER_XT_TARGET_MARK is not set
395+# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
396+# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set
397+# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
398+# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
399+# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
400+# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
401+# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
402+# CONFIG_NETFILTER_XT_MATCH_ESP is not set
403+# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
404+# CONFIG_NETFILTER_XT_MATCH_HL is not set
405+# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
406+# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set
407+# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set
408+# CONFIG_NETFILTER_XT_MATCH_MAC is not set
409+# CONFIG_NETFILTER_XT_MATCH_MARK is not set
410+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
411+# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
412+# CONFIG_NETFILTER_XT_MATCH_POLICY is not set
413+# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set
414+# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
415+# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
416+# CONFIG_NETFILTER_XT_MATCH_REALM is not set
417+# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
418+# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
419+# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
420+# CONFIG_NETFILTER_XT_MATCH_STRING is not set
421+# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
422+# CONFIG_NETFILTER_XT_MATCH_TIME is not set
423+# CONFIG_NETFILTER_XT_MATCH_U32 is not set
424+# CONFIG_IP_VS is not set
425+
426+#
427+# IP: Netfilter Configuration
428+#
429+# CONFIG_NF_DEFRAG_IPV4 is not set
430+# CONFIG_IP_NF_QUEUE is not set
431+CONFIG_IP_NF_IPTABLES=y
432+# CONFIG_IP_NF_MATCH_ADDRTYPE is not set
433+# CONFIG_IP_NF_MATCH_AH is not set
434+# CONFIG_IP_NF_MATCH_ECN is not set
435+# CONFIG_IP_NF_MATCH_TTL is not set
436+CONFIG_IP_NF_FILTER=y
437+# CONFIG_IP_NF_TARGET_REJECT is not set
438+# CONFIG_IP_NF_TARGET_LOG is not set
439+# CONFIG_IP_NF_TARGET_ULOG is not set
440+# CONFIG_IP_NF_MANGLE is not set
441+# CONFIG_IP_NF_TARGET_TTL is not set
442+# CONFIG_IP_NF_RAW is not set
443+CONFIG_IP_NF_ARPTABLES=y
444+CONFIG_IP_NF_ARPFILTER=y
445+# CONFIG_IP_NF_ARP_MANGLE is not set
446+
447+#
448+# IPv6: Netfilter Configuration
449+#
450+# CONFIG_IP6_NF_QUEUE is not set
451+CONFIG_IP6_NF_IPTABLES=y
452+# CONFIG_IP6_NF_MATCH_AH is not set
453+# CONFIG_IP6_NF_MATCH_EUI64 is not set
454+# CONFIG_IP6_NF_MATCH_FRAG is not set
455+# CONFIG_IP6_NF_MATCH_OPTS is not set
456+# CONFIG_IP6_NF_MATCH_HL is not set
457+# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set
458+# CONFIG_IP6_NF_MATCH_MH is not set
459+# CONFIG_IP6_NF_MATCH_RT is not set
460+# CONFIG_IP6_NF_TARGET_HL is not set
461+# CONFIG_IP6_NF_TARGET_LOG is not set
462+CONFIG_IP6_NF_FILTER=y
463+# CONFIG_IP6_NF_TARGET_REJECT is not set
464+# CONFIG_IP6_NF_MANGLE is not set
465+# CONFIG_IP6_NF_RAW is not set
466+# CONFIG_IP_DCCP is not set
467+# CONFIG_IP_SCTP is not set
468+# CONFIG_TIPC is not set
469+# CONFIG_ATM is not set
470+CONFIG_STP=y
471+CONFIG_BRIDGE=y
472+# CONFIG_NET_DSA is not set
473+# CONFIG_VLAN_8021Q is not set
474+# CONFIG_DECNET is not set
475+CONFIG_LLC=y
476+# CONFIG_LLC2 is not set
477+# CONFIG_IPX is not set
478+# CONFIG_ATALK is not set
479+# CONFIG_X25 is not set
480+# CONFIG_LAPB is not set
481+# CONFIG_ECONET is not set
482+# CONFIG_WAN_ROUTER is not set
483+# CONFIG_PHONET is not set
484+# CONFIG_IEEE802154 is not set
485+CONFIG_NET_SCHED=y
486+
487+#
488+# Queueing/Scheduling
489+#
490+# CONFIG_NET_SCH_CBQ is not set
491+# CONFIG_NET_SCH_HTB is not set
492+# CONFIG_NET_SCH_HFSC is not set
493+# CONFIG_NET_SCH_PRIO is not set
494+# CONFIG_NET_SCH_MULTIQ is not set
495+# CONFIG_NET_SCH_RED is not set
496+# CONFIG_NET_SCH_SFQ is not set
497+# CONFIG_NET_SCH_TEQL is not set
498+CONFIG_NET_SCH_TBF=y
499+# CONFIG_NET_SCH_GRED is not set
500+# CONFIG_NET_SCH_DSMARK is not set
501+# CONFIG_NET_SCH_NETEM is not set
502+# CONFIG_NET_SCH_DRR is not set
503+
504+#
505+# Classification
506+#
507+# CONFIG_NET_CLS_BASIC is not set
508+# CONFIG_NET_CLS_TCINDEX is not set
509+# CONFIG_NET_CLS_ROUTE4 is not set
510+# CONFIG_NET_CLS_FW is not set
511+# CONFIG_NET_CLS_U32 is not set
512+# CONFIG_NET_CLS_RSVP is not set
513+# CONFIG_NET_CLS_RSVP6 is not set
514+# CONFIG_NET_CLS_FLOW is not set
515+# CONFIG_NET_EMATCH is not set
516+# CONFIG_NET_CLS_ACT is not set
517+CONFIG_NET_SCH_FIFO=y
518+# CONFIG_DCB is not set
519+
520+#
521+# Network testing
522+#
523+# CONFIG_NET_PKTGEN is not set
524+# CONFIG_HAMRADIO is not set
525+# CONFIG_CAN is not set
526+# CONFIG_IRDA is not set
527+# CONFIG_BT is not set
528+# CONFIG_AF_RXRPC is not set
529+# CONFIG_WIRELESS is not set
530+# CONFIG_WIMAX is not set
531+# CONFIG_RFKILL is not set
532+# CONFIG_NET_9P is not set
533+
534+#
535+# Device Drivers
536+#
537+
538+#
539+# Generic Driver Options
540+#
541+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
542+CONFIG_STANDALONE=y
543+CONFIG_PREVENT_FIRMWARE_BUILD=y
544+CONFIG_FW_LOADER=y
545+CONFIG_FIRMWARE_IN_KERNEL=y
546+CONFIG_EXTRA_FIRMWARE=""
547+# CONFIG_DEBUG_DRIVER is not set
548+# CONFIG_DEBUG_DEVRES is not set
549+# CONFIG_SYS_HYPERVISOR is not set
550+# CONFIG_CONNECTOR is not set
551+CONFIG_MTD=y
552+# CONFIG_MTD_DEBUG is not set
553+# CONFIG_MTD_CONCAT is not set
554+CONFIG_MTD_PARTITIONS=y
555+# CONFIG_MTD_TESTS is not set
556+# CONFIG_MTD_REDBOOT_PARTS is not set
557+CONFIG_MTD_CMDLINE_PARTS=y
558+# CONFIG_MTD_AR7_PARTS is not set
559+
560+#
561+# User Modules And Translation Layers
562+#
563+CONFIG_MTD_CHAR=y
564+CONFIG_MTD_BLKDEVS=y
565+CONFIG_MTD_BLOCK=y
566+# CONFIG_FTL is not set
567+# CONFIG_NFTL is not set
568+# CONFIG_INFTL is not set
569+# CONFIG_RFD_FTL is not set
570+# CONFIG_SSFDC is not set
571+# CONFIG_MTD_OOPS is not set
572+
573+#
574+# RAM/ROM/Flash chip drivers
575+#
576+# CONFIG_MTD_CFI is not set
577+# CONFIG_MTD_JEDECPROBE is not set
578+CONFIG_MTD_MAP_BANK_WIDTH_1=y
579+CONFIG_MTD_MAP_BANK_WIDTH_2=y
580+CONFIG_MTD_MAP_BANK_WIDTH_4=y
581+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
582+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
583+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
584+CONFIG_MTD_CFI_I1=y
585+CONFIG_MTD_CFI_I2=y
586+# CONFIG_MTD_CFI_I4 is not set
587+# CONFIG_MTD_CFI_I8 is not set
588+# CONFIG_MTD_RAM is not set
589+# CONFIG_MTD_ROM is not set
590+# CONFIG_MTD_ABSENT is not set
591+
592+#
593+# Mapping drivers for chip access
594+#
595+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
596+# CONFIG_MTD_INTEL_VR_NOR is not set
597+# CONFIG_MTD_PLATRAM is not set
598+
599+#
600+# Self-contained MTD device drivers
601+#
602+# CONFIG_MTD_PMC551 is not set
603+# CONFIG_MTD_SLRAM is not set
604+# CONFIG_MTD_PHRAM is not set
605+# CONFIG_MTD_MTDRAM is not set
606+# CONFIG_MTD_BLOCK2MTD is not set
607+
608+#
609+# Disk-On-Chip Device Drivers
610+#
611+# CONFIG_MTD_DOC2000 is not set
612+# CONFIG_MTD_DOC2001 is not set
613+# CONFIG_MTD_DOC2001PLUS is not set
614+CONFIG_MTD_NAND=y
615+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
616+# CONFIG_MTD_NAND_ECC_SMC is not set
617+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
618+CONFIG_MTD_NAND_IDS=y
619+# CONFIG_MTD_NAND_DISKONCHIP is not set
620+# CONFIG_MTD_NAND_CAFE is not set
621+# CONFIG_MTD_NAND_NANDSIM is not set
622+# CONFIG_MTD_NAND_PLATFORM is not set
623+# CONFIG_MTD_ALAUDA is not set
624+# CONFIG_MTD_ONENAND is not set
625+
626+#
627+# LPDDR flash memory drivers
628+#
629+# CONFIG_MTD_LPDDR is not set
630+
631+#
632+# UBI - Unsorted block images
633+#
634+# CONFIG_MTD_UBI is not set
635+# CONFIG_PARPORT is not set
636+CONFIG_BLK_DEV=y
637+# CONFIG_BLK_CPQ_DA is not set
638+# CONFIG_BLK_CPQ_CISS_DA is not set
639+# CONFIG_BLK_DEV_DAC960 is not set
640+# CONFIG_BLK_DEV_UMEM is not set
641+# CONFIG_BLK_DEV_COW_COMMON is not set
642+CONFIG_BLK_DEV_LOOP=y
643+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
644+# CONFIG_BLK_DEV_NBD is not set
645+# CONFIG_BLK_DEV_SX8 is not set
646+# CONFIG_BLK_DEV_UB is not set
647+CONFIG_BLK_DEV_RAM=y
648+CONFIG_BLK_DEV_RAM_COUNT=16
649+CONFIG_BLK_DEV_RAM_SIZE=32768
650+# CONFIG_BLK_DEV_XIP is not set
651+# CONFIG_CDROM_PKTCDVD is not set
652+# CONFIG_ATA_OVER_ETH is not set
653+# CONFIG_BLK_DEV_HD is not set
654+# CONFIG_MISC_DEVICES is not set
655+CONFIG_HAVE_IDE=y
656+# CONFIG_IDE is not set
657+
658+#
659+# SCSI device support
660+#
661+# CONFIG_RAID_ATTRS is not set
662+CONFIG_SCSI=y
663+CONFIG_SCSI_DMA=y
664+# CONFIG_SCSI_TGT is not set
665+# CONFIG_SCSI_NETLINK is not set
666+# CONFIG_SCSI_PROC_FS is not set
667+
668+#
669+# SCSI support type (disk, tape, CD-ROM)
670+#
671+CONFIG_BLK_DEV_SD=y
672+# CONFIG_CHR_DEV_ST is not set
673+# CONFIG_CHR_DEV_OSST is not set
674+# CONFIG_BLK_DEV_SR is not set
675+# CONFIG_CHR_DEV_SG is not set
676+# CONFIG_CHR_DEV_SCH is not set
677+# CONFIG_SCSI_MULTI_LUN is not set
678+# CONFIG_SCSI_CONSTANTS is not set
679+# CONFIG_SCSI_LOGGING is not set
680+# CONFIG_SCSI_SCAN_ASYNC is not set
681+CONFIG_SCSI_WAIT_SCAN=m
682+
683+#
684+# SCSI Transports
685+#
686+# CONFIG_SCSI_SPI_ATTRS is not set
687+# CONFIG_SCSI_FC_ATTRS is not set
688+# CONFIG_SCSI_ISCSI_ATTRS is not set
689+# CONFIG_SCSI_SAS_LIBSAS is not set
690+# CONFIG_SCSI_SRP_ATTRS is not set
691+# CONFIG_SCSI_LOWLEVEL is not set
692+# CONFIG_SCSI_DH is not set
693+# CONFIG_SCSI_OSD_INITIATOR is not set
694+CONFIG_ATA=y
695+# CONFIG_ATA_NONSTANDARD is not set
696+CONFIG_SATA_PMP=y
697+# CONFIG_SATA_AHCI is not set
698+# CONFIG_SATA_SIL24 is not set
699+CONFIG_ATA_SFF=y
700+# CONFIG_SATA_SVW is not set
701+# CONFIG_ATA_PIIX is not set
702+# CONFIG_SATA_MV is not set
703+# CONFIG_SATA_NV is not set
704+# CONFIG_PDC_ADMA is not set
705+# CONFIG_SATA_QSTOR is not set
706+# CONFIG_SATA_PROMISE is not set
707+# CONFIG_SATA_SX4 is not set
708+# CONFIG_SATA_SIL is not set
709+# CONFIG_SATA_SIS is not set
710+# CONFIG_SATA_ULI is not set
711+# CONFIG_SATA_VIA is not set
712+# CONFIG_SATA_VITESSE is not set
713+# CONFIG_SATA_INIC162X is not set
714+# CONFIG_PATA_ALI is not set
715+# CONFIG_PATA_AMD is not set
716+# CONFIG_PATA_ARTOP is not set
717+# CONFIG_PATA_ATIIXP is not set
718+# CONFIG_PATA_CMD640_PCI is not set
719+# CONFIG_PATA_CMD64X is not set
720+# CONFIG_PATA_CS5520 is not set
721+# CONFIG_PATA_CS5530 is not set
722+# CONFIG_PATA_CYPRESS is not set
723+# CONFIG_PATA_EFAR is not set
724+# CONFIG_ATA_GENERIC is not set
725+# CONFIG_PATA_HPT366 is not set
726+# CONFIG_PATA_HPT37X is not set
727+# CONFIG_PATA_HPT3X2N is not set
728+# CONFIG_PATA_HPT3X3 is not set
729+# CONFIG_PATA_IT821X is not set
730+# CONFIG_PATA_IT8213 is not set
731+# CONFIG_PATA_JMICRON is not set
732+# CONFIG_PATA_TRIFLEX is not set
733+# CONFIG_PATA_MARVELL is not set
734+# CONFIG_PATA_MPIIX is not set
735+# CONFIG_PATA_OLDPIIX is not set
736+# CONFIG_PATA_NETCELL is not set
737+# CONFIG_PATA_NINJA32 is not set
738+# CONFIG_PATA_NS87410 is not set
739+# CONFIG_PATA_NS87415 is not set
740+# CONFIG_PATA_OPTI is not set
741+# CONFIG_PATA_OPTIDMA is not set
742+# CONFIG_PATA_PDC_OLD is not set
743+# CONFIG_PATA_RADISYS is not set
744+# CONFIG_PATA_RZ1000 is not set
745+# CONFIG_PATA_SC1200 is not set
746+# CONFIG_PATA_SERVERWORKS is not set
747+# CONFIG_PATA_PDC2027X is not set
748+# CONFIG_PATA_SIL680 is not set
749+# CONFIG_PATA_SIS is not set
750+# CONFIG_PATA_VIA is not set
751+# CONFIG_PATA_WINBOND is not set
752+# CONFIG_PATA_PLATFORM is not set
753+# CONFIG_PATA_SCH is not set
754+# CONFIG_MD is not set
755+# CONFIG_FUSION is not set
756+
757+#
758+# IEEE 1394 (FireWire) support
759+#
760+
761+#
762+# You can enable one or both FireWire driver stacks.
763+#
764+
765+#
766+# See the help texts for more information.
767+#
768+# CONFIG_FIREWIRE is not set
769+# CONFIG_IEEE1394 is not set
770+# CONFIG_I2O is not set
771+CONFIG_NETDEVICES=y
772+# CONFIG_DUMMY is not set
773+# CONFIG_BONDING is not set
774+# CONFIG_MACVLAN is not set
775+# CONFIG_EQUALIZER is not set
776+# CONFIG_TUN is not set
777+# CONFIG_VETH is not set
778+# CONFIG_ARCNET is not set
779+# CONFIG_PHYLIB is not set
780+CONFIG_NET_ETHERNET=y
781+CONFIG_MII=y
782+# CONFIG_AX88796 is not set
783+# CONFIG_HAPPYMEAL is not set
784+# CONFIG_SUNGEM is not set
785+# CONFIG_CASSINI is not set
786+# CONFIG_NET_VENDOR_3COM is not set
787+# CONFIG_SMC91X is not set
788+# CONFIG_DM9000 is not set
789+# CONFIG_ETHOC is not set
790+# CONFIG_DNET is not set
791+# CONFIG_NET_TULIP is not set
792+# CONFIG_HP100 is not set
793+# CONFIG_IBM_NEW_EMAC_ZMII is not set
794+# CONFIG_IBM_NEW_EMAC_RGMII is not set
795+# CONFIG_IBM_NEW_EMAC_TAH is not set
796+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
797+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
798+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
799+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
800+# CONFIG_NET_PCI is not set
801+# CONFIG_B44 is not set
802+# CONFIG_KS8842 is not set
803+# CONFIG_ATL2 is not set
804+CONFIG_NETDEV_1000=y
805+# CONFIG_ACENIC is not set
806+# CONFIG_DL2K is not set
807+# CONFIG_E1000 is not set
808+# CONFIG_E1000E is not set
809+# CONFIG_IP1000 is not set
810+# CONFIG_IGB is not set
811+# CONFIG_IGBVF is not set
812+# CONFIG_NS83820 is not set
813+# CONFIG_HAMACHI is not set
814+# CONFIG_YELLOWFIN is not set
815+# CONFIG_R8169 is not set
816+# CONFIG_SIS190 is not set
817+# CONFIG_SKGE is not set
818+# CONFIG_SKY2 is not set
819+# CONFIG_VIA_VELOCITY is not set
820+# CONFIG_TIGON3 is not set
821+# CONFIG_BNX2 is not set
822+# CONFIG_CNIC is not set
823+# CONFIG_QLA3XXX is not set
824+# CONFIG_ATL1 is not set
825+# CONFIG_ATL1E is not set
826+# CONFIG_ATL1C is not set
827+# CONFIG_JME is not set
828+CONFIG_NETDEV_10000=y
829+# CONFIG_CHELSIO_T1 is not set
830+CONFIG_CHELSIO_T3_DEPENDS=y
831+# CONFIG_CHELSIO_T3 is not set
832+# CONFIG_ENIC is not set
833+# CONFIG_IXGBE is not set
834+# CONFIG_IXGB is not set
835+# CONFIG_S2IO is not set
836+# CONFIG_VXGE is not set
837+# CONFIG_MYRI10GE is not set
838+# CONFIG_NETXEN_NIC is not set
839+# CONFIG_NIU is not set
840+# CONFIG_MLX4_EN is not set
841+# CONFIG_MLX4_CORE is not set
842+# CONFIG_TEHUTI is not set
843+# CONFIG_BNX2X is not set
844+# CONFIG_QLGE is not set
845+# CONFIG_SFC is not set
846+# CONFIG_BE2NET is not set
847+# CONFIG_TR is not set
848+
849+#
850+# Wireless LAN
851+#
852+# CONFIG_WLAN_PRE80211 is not set
853+# CONFIG_WLAN_80211 is not set
854+
855+#
856+# Enable WiMAX (Networking options) to see the WiMAX drivers
857+#
858+
859+#
860+# USB Network Adapters
861+#
862+# CONFIG_USB_CATC is not set
863+# CONFIG_USB_KAWETH is not set
864+# CONFIG_USB_PEGASUS is not set
865+CONFIG_USB_RTL8150=y
866+# CONFIG_USB_USBNET is not set
867+# CONFIG_WAN is not set
868+# CONFIG_FDDI is not set
869+# CONFIG_HIPPI is not set
870+# CONFIG_PPP is not set
871+# CONFIG_SLIP is not set
872+# CONFIG_NET_FC is not set
873+# CONFIG_NETCONSOLE is not set
874+# CONFIG_NETPOLL is not set
875+# CONFIG_NET_POLL_CONTROLLER is not set
876+# CONFIG_ISDN is not set
877+# CONFIG_PHONE is not set
878+
879+#
880+# Input device support
881+#
882+CONFIG_INPUT=y
883+# CONFIG_INPUT_FF_MEMLESS is not set
884+# CONFIG_INPUT_POLLDEV is not set
885+
886+#
887+# Userland interfaces
888+#
889+# CONFIG_INPUT_MOUSEDEV is not set
890+# CONFIG_INPUT_JOYDEV is not set
891+CONFIG_INPUT_EVDEV=y
892+# CONFIG_INPUT_EVBUG is not set
893+
894+#
895+# Input Device Drivers
896+#
897+# CONFIG_INPUT_KEYBOARD is not set
898+# CONFIG_INPUT_MOUSE is not set
899+# CONFIG_INPUT_JOYSTICK is not set
900+# CONFIG_INPUT_TABLET is not set
901+# CONFIG_INPUT_TOUCHSCREEN is not set
902+# CONFIG_INPUT_MISC is not set
903+
904+#
905+# Hardware I/O ports
906+#
907+# CONFIG_SERIO is not set
908+# CONFIG_GAMEPORT is not set
909+
910+#
911+# Character devices
912+#
913+# CONFIG_VT is not set
914+# CONFIG_DEVKMEM is not set
915+# CONFIG_SERIAL_NONSTANDARD is not set
916+# CONFIG_NOZOMI is not set
917+
918+#
919+# Serial drivers
920+#
921+# CONFIG_SERIAL_8250 is not set
922+
923+#
924+# Non-8250 serial port support
925+#
926+# CONFIG_SERIAL_JSM is not set
927+CONFIG_UNIX98_PTYS=y
928+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
929+# CONFIG_LEGACY_PTYS is not set
930+# CONFIG_IPMI_HANDLER is not set
931+# CONFIG_HW_RANDOM is not set
932+# CONFIG_R3964 is not set
933+# CONFIG_APPLICOM is not set
934+# CONFIG_RAW_DRIVER is not set
935+# CONFIG_TCG_TPM is not set
936+CONFIG_DEVPORT=y
937+# CONFIG_I2C is not set
938+# CONFIG_SPI is not set
939+
940+#
941+# PPS support
942+#
943+# CONFIG_PPS is not set
944+# CONFIG_W1 is not set
945+# CONFIG_POWER_SUPPLY is not set
946+# CONFIG_HWMON is not set
947+# CONFIG_THERMAL is not set
948+# CONFIG_THERMAL_HWMON is not set
949+# CONFIG_WATCHDOG is not set
950+CONFIG_SSB_POSSIBLE=y
951+
952+#
953+# Sonics Silicon Backplane
954+#
955+# CONFIG_SSB is not set
956+
957+#
958+# Multifunction device drivers
959+#
960+# CONFIG_MFD_CORE is not set
961+# CONFIG_MFD_SM501 is not set
962+# CONFIG_HTC_PASIC3 is not set
963+# CONFIG_MFD_TMIO is not set
964+# CONFIG_REGULATOR is not set
965+# CONFIG_MEDIA_SUPPORT is not set
966+
967+#
968+# Graphics support
969+#
970+# CONFIG_DRM is not set
971+# CONFIG_VGASTATE is not set
972+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
973+# CONFIG_FB is not set
974+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
975+
976+#
977+# Display device support
978+#
979+# CONFIG_DISPLAY_SUPPORT is not set
980+# CONFIG_SOUND is not set
981+CONFIG_HID_SUPPORT=y
982+CONFIG_HID=y
983+# CONFIG_HID_DEBUG is not set
984+# CONFIG_HIDRAW is not set
985+
986+#
987+# USB Input Devices
988+#
989+CONFIG_USB_HID=y
990+# CONFIG_HID_PID is not set
991+CONFIG_USB_HIDDEV=y
992+
993+#
994+# Special HID drivers
995+#
996+# CONFIG_HID_A4TECH is not set
997+# CONFIG_HID_APPLE is not set
998+# CONFIG_HID_BELKIN is not set
999+# CONFIG_HID_CHERRY is not set
1000+# CONFIG_HID_CHICONY is not set
1001+# CONFIG_HID_CYPRESS is not set
1002+# CONFIG_HID_DRAGONRISE is not set
1003+# CONFIG_HID_EZKEY is not set
1004+# CONFIG_HID_KYE is not set
1005+# CONFIG_HID_GYRATION is not set
1006+# CONFIG_HID_KENSINGTON is not set
1007+# CONFIG_HID_LOGITECH is not set
1008+# CONFIG_HID_MICROSOFT is not set
1009+# CONFIG_HID_MONTEREY is not set
1010+# CONFIG_HID_NTRIG is not set
1011+# CONFIG_HID_PANTHERLORD is not set
1012+# CONFIG_HID_PETALYNX is not set
1013+# CONFIG_HID_SAMSUNG is not set
1014+# CONFIG_HID_SONY is not set
1015+# CONFIG_HID_SUNPLUS is not set
1016+# CONFIG_HID_GREENASIA is not set
1017+# CONFIG_HID_SMARTJOYPLUS is not set
1018+# CONFIG_HID_TOPSEED is not set
1019+# CONFIG_HID_THRUSTMASTER is not set
1020+# CONFIG_HID_ZEROPLUS is not set
1021+CONFIG_USB_SUPPORT=y
1022+CONFIG_USB_ARCH_HAS_HCD=y
1023+CONFIG_USB_ARCH_HAS_OHCI=y
1024+CONFIG_USB_ARCH_HAS_EHCI=y
1025+CONFIG_USB=y
1026+# CONFIG_USB_DEBUG is not set
1027+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
1028+
1029+#
1030+# Miscellaneous USB options
1031+#
1032+CONFIG_USB_DEVICEFS=y
1033+# CONFIG_USB_DEVICE_CLASS is not set
1034+# CONFIG_USB_DYNAMIC_MINORS is not set
1035+# CONFIG_USB_OTG is not set
1036+# CONFIG_USB_OTG_WHITELIST is not set
1037+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
1038+# CONFIG_USB_MON is not set
1039+# CONFIG_USB_WUSB is not set
1040+# CONFIG_USB_WUSB_CBAF is not set
1041+
1042+#
1043+# USB Host Controller Drivers
1044+#
1045+# CONFIG_USB_C67X00_HCD is not set
1046+# CONFIG_USB_XHCI_HCD is not set
1047+CONFIG_USB_EHCI_HCD=y
1048+# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
1049+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
1050+# CONFIG_USB_OXU210HP_HCD is not set
1051+# CONFIG_USB_ISP116X_HCD is not set
1052+# CONFIG_USB_ISP1760_HCD is not set
1053+CONFIG_USB_OHCI_HCD=y
1054+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
1055+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
1056+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
1057+# CONFIG_USB_UHCI_HCD is not set
1058+# CONFIG_USB_SL811_HCD is not set
1059+# CONFIG_USB_R8A66597_HCD is not set
1060+# CONFIG_USB_WHCI_HCD is not set
1061+# CONFIG_USB_HWA_HCD is not set
1062+
1063+#
1064+# USB Device Class drivers
1065+#
1066+# CONFIG_USB_ACM is not set
1067+# CONFIG_USB_PRINTER is not set
1068+# CONFIG_USB_WDM is not set
1069+# CONFIG_USB_TMC is not set
1070+
1071+#
1072+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
1073+#
1074+
1075+#
1076+# also be needed; see USB_STORAGE Help for more info
1077+#
1078+CONFIG_USB_STORAGE=y
1079+# CONFIG_USB_STORAGE_DEBUG is not set
1080+# CONFIG_USB_STORAGE_DATAFAB is not set
1081+# CONFIG_USB_STORAGE_FREECOM is not set
1082+# CONFIG_USB_STORAGE_ISD200 is not set
1083+# CONFIG_USB_STORAGE_USBAT is not set
1084+# CONFIG_USB_STORAGE_SDDR09 is not set
1085+# CONFIG_USB_STORAGE_SDDR55 is not set
1086+# CONFIG_USB_STORAGE_JUMPSHOT is not set
1087+# CONFIG_USB_STORAGE_ALAUDA is not set
1088+# CONFIG_USB_STORAGE_ONETOUCH is not set
1089+# CONFIG_USB_STORAGE_KARMA is not set
1090+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
1091+# CONFIG_USB_LIBUSUAL is not set
1092+
1093+#
1094+# USB Imaging devices
1095+#
1096+# CONFIG_USB_MDC800 is not set
1097+# CONFIG_USB_MICROTEK is not set
1098+
1099+#
1100+# USB port drivers
1101+#
1102+CONFIG_USB_SERIAL=y
1103+CONFIG_USB_SERIAL_CONSOLE=y
1104+# CONFIG_USB_EZUSB is not set
1105+# CONFIG_USB_SERIAL_GENERIC is not set
1106+# CONFIG_USB_SERIAL_AIRCABLE is not set
1107+# CONFIG_USB_SERIAL_ARK3116 is not set
1108+# CONFIG_USB_SERIAL_BELKIN is not set
1109+# CONFIG_USB_SERIAL_CH341 is not set
1110+# CONFIG_USB_SERIAL_WHITEHEAT is not set
1111+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
1112+CONFIG_USB_SERIAL_CP210X=y
1113+# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
1114+# CONFIG_USB_SERIAL_EMPEG is not set
1115+# CONFIG_USB_SERIAL_FTDI_SIO is not set
1116+# CONFIG_USB_SERIAL_FUNSOFT is not set
1117+# CONFIG_USB_SERIAL_VISOR is not set
1118+# CONFIG_USB_SERIAL_IPAQ is not set
1119+# CONFIG_USB_SERIAL_IR is not set
1120+# CONFIG_USB_SERIAL_EDGEPORT is not set
1121+# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
1122+# CONFIG_USB_SERIAL_GARMIN is not set
1123+# CONFIG_USB_SERIAL_IPW is not set
1124+# CONFIG_USB_SERIAL_IUU is not set
1125+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
1126+# CONFIG_USB_SERIAL_KEYSPAN is not set
1127+# CONFIG_USB_SERIAL_KLSI is not set
1128+# CONFIG_USB_SERIAL_KOBIL_SCT is not set
1129+# CONFIG_USB_SERIAL_MCT_U232 is not set
1130+# CONFIG_USB_SERIAL_MOS7720 is not set
1131+# CONFIG_USB_SERIAL_MOS7840 is not set
1132+# CONFIG_USB_SERIAL_MOTOROLA is not set
1133+# CONFIG_USB_SERIAL_NAVMAN is not set
1134+# CONFIG_USB_SERIAL_PL2303 is not set
1135+# CONFIG_USB_SERIAL_OTI6858 is not set
1136+# CONFIG_USB_SERIAL_QUALCOMM is not set
1137+# CONFIG_USB_SERIAL_SPCP8X5 is not set
1138+# CONFIG_USB_SERIAL_HP4X is not set
1139+# CONFIG_USB_SERIAL_SAFE is not set
1140+# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
1141+# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
1142+# CONFIG_USB_SERIAL_SYMBOL is not set
1143+# CONFIG_USB_SERIAL_TI is not set
1144+# CONFIG_USB_SERIAL_CYBERJACK is not set
1145+# CONFIG_USB_SERIAL_XIRCOM is not set
1146+# CONFIG_USB_SERIAL_OPTION is not set
1147+# CONFIG_USB_SERIAL_OMNINET is not set
1148+# CONFIG_USB_SERIAL_OPTICON is not set
1149+# CONFIG_USB_SERIAL_DEBUG is not set
1150+
1151+#
1152+# USB Miscellaneous drivers
1153+#
1154+# CONFIG_USB_EMI62 is not set
1155+# CONFIG_USB_EMI26 is not set
1156+# CONFIG_USB_ADUTUX is not set
1157+# CONFIG_USB_SEVSEG is not set
1158+# CONFIG_USB_RIO500 is not set
1159+# CONFIG_USB_LEGOTOWER is not set
1160+# CONFIG_USB_LCD is not set
1161+# CONFIG_USB_BERRY_CHARGE is not set
1162+# CONFIG_USB_LED is not set
1163+# CONFIG_USB_CYPRESS_CY7C63 is not set
1164+# CONFIG_USB_CYTHERM is not set
1165+# CONFIG_USB_IDMOUSE is not set
1166+# CONFIG_USB_FTDI_ELAN is not set
1167+# CONFIG_USB_APPLEDISPLAY is not set
1168+# CONFIG_USB_SISUSBVGA is not set
1169+# CONFIG_USB_LD is not set
1170+# CONFIG_USB_TRANCEVIBRATOR is not set
1171+# CONFIG_USB_IOWARRIOR is not set
1172+# CONFIG_USB_TEST is not set
1173+# CONFIG_USB_ISIGHTFW is not set
1174+# CONFIG_USB_VST is not set
1175+# CONFIG_USB_GADGET is not set
1176+
1177+#
1178+# OTG and related infrastructure
1179+#
1180+# CONFIG_NOP_USB_XCEIV is not set
1181+# CONFIG_UWB is not set
1182+# CONFIG_MMC is not set
1183+# CONFIG_MEMSTICK is not set
1184+# CONFIG_NEW_LEDS is not set
1185+# CONFIG_ACCESSIBILITY is not set
1186+# CONFIG_INFINIBAND is not set
1187+CONFIG_RTC_LIB=y
1188+# CONFIG_RTC_CLASS is not set
1189+# CONFIG_DMADEVICES is not set
1190+# CONFIG_AUXDISPLAY is not set
1191+# CONFIG_UIO is not set
1192+
1193+#
1194+# TI VLYNQ
1195+#
1196+# CONFIG_STAGING is not set
1197+
1198+#
1199+# File systems
1200+#
1201+CONFIG_EXT2_FS=y
1202+# CONFIG_EXT2_FS_XATTR is not set
1203+# CONFIG_EXT2_FS_XIP is not set
1204+CONFIG_EXT3_FS=y
1205+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
1206+# CONFIG_EXT3_FS_XATTR is not set
1207+# CONFIG_EXT4_FS is not set
1208+CONFIG_JBD=y
1209+# CONFIG_JBD_DEBUG is not set
1210+# CONFIG_REISERFS_FS is not set
1211+# CONFIG_JFS_FS is not set
1212+# CONFIG_FS_POSIX_ACL is not set
1213+# CONFIG_XFS_FS is not set
1214+# CONFIG_GFS2_FS is not set
1215+# CONFIG_OCFS2_FS is not set
1216+# CONFIG_BTRFS_FS is not set
1217+CONFIG_FILE_LOCKING=y
1218+CONFIG_FSNOTIFY=y
1219+# CONFIG_DNOTIFY is not set
1220+CONFIG_INOTIFY=y
1221+CONFIG_INOTIFY_USER=y
1222+# CONFIG_QUOTA is not set
1223+# CONFIG_AUTOFS_FS is not set
1224+# CONFIG_AUTOFS4_FS is not set
1225+CONFIG_FUSE_FS=y
1226+# CONFIG_CUSE is not set
1227+
1228+#
1229+# Caches
1230+#
1231+# CONFIG_FSCACHE is not set
1232+
1233+#
1234+# CD-ROM/DVD Filesystems
1235+#
1236+# CONFIG_ISO9660_FS is not set
1237+# CONFIG_UDF_FS is not set
1238+
1239+#
1240+# DOS/FAT/NT Filesystems
1241+#
1242+# CONFIG_MSDOS_FS is not set
1243+# CONFIG_VFAT_FS is not set
1244+# CONFIG_NTFS_FS is not set
1245+
1246+#
1247+# Pseudo filesystems
1248+#
1249+CONFIG_PROC_FS=y
1250+CONFIG_PROC_KCORE=y
1251+CONFIG_PROC_SYSCTL=y
1252+CONFIG_PROC_PAGE_MONITOR=y
1253+CONFIG_SYSFS=y
1254+CONFIG_TMPFS=y
1255+# CONFIG_TMPFS_POSIX_ACL is not set
1256+# CONFIG_HUGETLB_PAGE is not set
1257+# CONFIG_CONFIGFS_FS is not set
1258+CONFIG_MISC_FILESYSTEMS=y
1259+# CONFIG_ADFS_FS is not set
1260+# CONFIG_AFFS_FS is not set
1261+# CONFIG_HFS_FS is not set
1262+# CONFIG_HFSPLUS_FS is not set
1263+# CONFIG_BEFS_FS is not set
1264+# CONFIG_BFS_FS is not set
1265+# CONFIG_EFS_FS is not set
1266+CONFIG_JFFS2_FS=y
1267+CONFIG_JFFS2_FS_DEBUG=0
1268+CONFIG_JFFS2_FS_WRITEBUFFER=y
1269+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
1270+# CONFIG_JFFS2_SUMMARY is not set
1271+# CONFIG_JFFS2_FS_XATTR is not set
1272+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
1273+CONFIG_JFFS2_ZLIB=y
1274+# CONFIG_JFFS2_LZO is not set
1275+CONFIG_JFFS2_RTIME=y
1276+# CONFIG_JFFS2_RUBIN is not set
1277+CONFIG_CRAMFS=y
1278+# CONFIG_SQUASHFS is not set
1279+# CONFIG_VXFS_FS is not set
1280+# CONFIG_MINIX_FS is not set
1281+# CONFIG_OMFS_FS is not set
1282+# CONFIG_HPFS_FS is not set
1283+# CONFIG_QNX4FS_FS is not set
1284+# CONFIG_ROMFS_FS is not set
1285+# CONFIG_SYSV_FS is not set
1286+# CONFIG_UFS_FS is not set
1287+# CONFIG_NILFS2_FS is not set
1288+CONFIG_NETWORK_FILESYSTEMS=y
1289+CONFIG_NFS_FS=y
1290+CONFIG_NFS_V3=y
1291+# CONFIG_NFS_V3_ACL is not set
1292+# CONFIG_NFS_V4 is not set
1293+CONFIG_ROOT_NFS=y
1294+# CONFIG_NFSD is not set
1295+CONFIG_LOCKD=y
1296+CONFIG_LOCKD_V4=y
1297+CONFIG_NFS_COMMON=y
1298+CONFIG_SUNRPC=y
1299+# CONFIG_RPCSEC_GSS_KRB5 is not set
1300+# CONFIG_RPCSEC_GSS_SPKM3 is not set
1301+# CONFIG_SMB_FS is not set
1302+# CONFIG_CIFS is not set
1303+# CONFIG_NCP_FS is not set
1304+# CONFIG_CODA_FS is not set
1305+# CONFIG_AFS_FS is not set
1306+
1307+#
1308+# Partition Types
1309+#
1310+# CONFIG_PARTITION_ADVANCED is not set
1311+CONFIG_MSDOS_PARTITION=y
1312+CONFIG_NLS=y
1313+CONFIG_NLS_DEFAULT="iso8859-1"
1314+# CONFIG_NLS_CODEPAGE_437 is not set
1315+# CONFIG_NLS_CODEPAGE_737 is not set
1316+# CONFIG_NLS_CODEPAGE_775 is not set
1317+# CONFIG_NLS_CODEPAGE_850 is not set
1318+# CONFIG_NLS_CODEPAGE_852 is not set
1319+# CONFIG_NLS_CODEPAGE_855 is not set
1320+# CONFIG_NLS_CODEPAGE_857 is not set
1321+# CONFIG_NLS_CODEPAGE_860 is not set
1322+# CONFIG_NLS_CODEPAGE_861 is not set
1323+# CONFIG_NLS_CODEPAGE_862 is not set
1324+# CONFIG_NLS_CODEPAGE_863 is not set
1325+# CONFIG_NLS_CODEPAGE_864 is not set
1326+# CONFIG_NLS_CODEPAGE_865 is not set
1327+# CONFIG_NLS_CODEPAGE_866 is not set
1328+# CONFIG_NLS_CODEPAGE_869 is not set
1329+# CONFIG_NLS_CODEPAGE_936 is not set
1330+# CONFIG_NLS_CODEPAGE_950 is not set
1331+# CONFIG_NLS_CODEPAGE_932 is not set
1332+# CONFIG_NLS_CODEPAGE_949 is not set
1333+# CONFIG_NLS_CODEPAGE_874 is not set
1334+# CONFIG_NLS_ISO8859_8 is not set
1335+# CONFIG_NLS_CODEPAGE_1250 is not set
1336+# CONFIG_NLS_CODEPAGE_1251 is not set
1337+# CONFIG_NLS_ASCII is not set
1338+# CONFIG_NLS_ISO8859_1 is not set
1339+# CONFIG_NLS_ISO8859_2 is not set
1340+# CONFIG_NLS_ISO8859_3 is not set
1341+# CONFIG_NLS_ISO8859_4 is not set
1342+# CONFIG_NLS_ISO8859_5 is not set
1343+# CONFIG_NLS_ISO8859_6 is not set
1344+# CONFIG_NLS_ISO8859_7 is not set
1345+# CONFIG_NLS_ISO8859_9 is not set
1346+# CONFIG_NLS_ISO8859_13 is not set
1347+# CONFIG_NLS_ISO8859_14 is not set
1348+# CONFIG_NLS_ISO8859_15 is not set
1349+# CONFIG_NLS_KOI8_R is not set
1350+# CONFIG_NLS_KOI8_U is not set
1351+# CONFIG_NLS_UTF8 is not set
1352+# CONFIG_DLM is not set
1353+
1354+#
1355+# Kernel hacking
1356+#
1357+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
1358+CONFIG_PRINTK_TIME=y
1359+CONFIG_ENABLE_WARN_DEPRECATED=y
1360+CONFIG_ENABLE_MUST_CHECK=y
1361+CONFIG_FRAME_WARN=1024
1362+# CONFIG_MAGIC_SYSRQ is not set
1363+# CONFIG_UNUSED_SYMBOLS is not set
1364+CONFIG_DEBUG_FS=y
1365+# CONFIG_HEADERS_CHECK is not set
1366+CONFIG_DEBUG_KERNEL=y
1367+# CONFIG_DEBUG_SHIRQ is not set
1368+CONFIG_DETECT_SOFTLOCKUP=y
1369+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1370+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1371+CONFIG_DETECT_HUNG_TASK=y
1372+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
1373+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
1374+# CONFIG_SCHED_DEBUG is not set
1375+# CONFIG_SCHEDSTATS is not set
1376+# CONFIG_TIMER_STATS is not set
1377+# CONFIG_DEBUG_OBJECTS is not set
1378+# CONFIG_DEBUG_PREEMPT is not set
1379+# CONFIG_DEBUG_RT_MUTEXES is not set
1380+# CONFIG_RT_MUTEX_TESTER is not set
1381+# CONFIG_DEBUG_SPINLOCK is not set
1382+# CONFIG_DEBUG_MUTEXES is not set
1383+# CONFIG_DEBUG_LOCK_ALLOC is not set
1384+# CONFIG_PROVE_LOCKING is not set
1385+# CONFIG_LOCK_STAT is not set
1386+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1387+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1388+# CONFIG_DEBUG_KOBJECT is not set
1389+CONFIG_DEBUG_INFO=y
1390+# CONFIG_DEBUG_VM is not set
1391+# CONFIG_DEBUG_WRITECOUNT is not set
1392+# CONFIG_DEBUG_MEMORY_INIT is not set
1393+# CONFIG_DEBUG_LIST is not set
1394+# CONFIG_DEBUG_SG is not set
1395+# CONFIG_DEBUG_NOTIFIERS is not set
1396+# CONFIG_BOOT_PRINTK_DELAY is not set
1397+# CONFIG_RCU_TORTURE_TEST is not set
1398+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1399+# CONFIG_BACKTRACE_SELF_TEST is not set
1400+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
1401+# CONFIG_FAULT_INJECTION is not set
1402+# CONFIG_PAGE_POISONING is not set
1403+CONFIG_TRACING_SUPPORT=y
1404+CONFIG_FTRACE=y
1405+# CONFIG_IRQSOFF_TRACER is not set
1406+# CONFIG_PREEMPT_TRACER is not set
1407+# CONFIG_SCHED_TRACER is not set
1408+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
1409+# CONFIG_BOOT_TRACER is not set
1410+CONFIG_BRANCH_PROFILE_NONE=y
1411+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
1412+# CONFIG_PROFILE_ALL_BRANCHES is not set
1413+# CONFIG_KMEMTRACE is not set
1414+# CONFIG_WORKQUEUE_TRACER is not set
1415+# CONFIG_BLK_DEV_IO_TRACE is not set
1416+# CONFIG_DYNAMIC_DEBUG is not set
1417+# CONFIG_SAMPLES is not set
1418+CONFIG_HAVE_ARCH_KGDB=y
1419+# CONFIG_KGDB is not set
1420+# CONFIG_KMEMCHECK is not set
1421+CONFIG_CMDLINE_BOOL=y
1422+CONFIG_CMDLINE="rw dhash_entries=1024 ihash_entries=1024 ip=10.0.1.3:10.0.1.1:10.0.1.1:255.255.255.0:zeus:eth0: root=/dev/nfs nfsroot=/nfsroot/cramfs,wsize=512,rsize=512,tcp nokgdb console=ttyUSB0,115200 memsize=252M"
1423+# CONFIG_CMDLINE_OVERRIDE is not set
1424+# CONFIG_DEBUG_STACK_USAGE is not set
1425+# CONFIG_RUNTIME_DEBUG is not set
1426+
1427+#
1428+# Security options
1429+#
1430+# CONFIG_KEYS is not set
1431+# CONFIG_SECURITY is not set
1432+# CONFIG_SECURITYFS is not set
1433+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1434+CONFIG_CRYPTO=y
1435+
1436+#
1437+# Crypto core or helper
1438+#
1439+# CONFIG_CRYPTO_FIPS is not set
1440+CONFIG_CRYPTO_ALGAPI=y
1441+CONFIG_CRYPTO_ALGAPI2=y
1442+CONFIG_CRYPTO_AEAD=y
1443+CONFIG_CRYPTO_AEAD2=y
1444+CONFIG_CRYPTO_BLKCIPHER=y
1445+CONFIG_CRYPTO_BLKCIPHER2=y
1446+CONFIG_CRYPTO_HASH=y
1447+CONFIG_CRYPTO_HASH2=y
1448+CONFIG_CRYPTO_RNG2=y
1449+CONFIG_CRYPTO_PCOMP=y
1450+CONFIG_CRYPTO_MANAGER=y
1451+CONFIG_CRYPTO_MANAGER2=y
1452+# CONFIG_CRYPTO_GF128MUL is not set
1453+# CONFIG_CRYPTO_NULL is not set
1454+CONFIG_CRYPTO_WORKQUEUE=y
1455+# CONFIG_CRYPTO_CRYPTD is not set
1456+CONFIG_CRYPTO_AUTHENC=y
1457+# CONFIG_CRYPTO_TEST is not set
1458+
1459+#
1460+# Authenticated Encryption with Associated Data
1461+#
1462+# CONFIG_CRYPTO_CCM is not set
1463+# CONFIG_CRYPTO_GCM is not set
1464+# CONFIG_CRYPTO_SEQIV is not set
1465+
1466+#
1467+# Block modes
1468+#
1469+CONFIG_CRYPTO_CBC=y
1470+# CONFIG_CRYPTO_CTR is not set
1471+# CONFIG_CRYPTO_CTS is not set
1472+# CONFIG_CRYPTO_ECB is not set
1473+# CONFIG_CRYPTO_LRW is not set
1474+# CONFIG_CRYPTO_PCBC is not set
1475+# CONFIG_CRYPTO_XTS is not set
1476+
1477+#
1478+# Hash modes
1479+#
1480+CONFIG_CRYPTO_HMAC=y
1481+# CONFIG_CRYPTO_XCBC is not set
1482+
1483+#
1484+# Digest
1485+#
1486+# CONFIG_CRYPTO_CRC32C is not set
1487+# CONFIG_CRYPTO_MD4 is not set
1488+CONFIG_CRYPTO_MD5=y
1489+# CONFIG_CRYPTO_MICHAEL_MIC is not set
1490+# CONFIG_CRYPTO_RMD128 is not set
1491+# CONFIG_CRYPTO_RMD160 is not set
1492+# CONFIG_CRYPTO_RMD256 is not set
1493+# CONFIG_CRYPTO_RMD320 is not set
1494+CONFIG_CRYPTO_SHA1=y
1495+# CONFIG_CRYPTO_SHA256 is not set
1496+# CONFIG_CRYPTO_SHA512 is not set
1497+# CONFIG_CRYPTO_TGR192 is not set
1498+# CONFIG_CRYPTO_WP512 is not set
1499+
1500+#
1501+# Ciphers
1502+#
1503+# CONFIG_CRYPTO_AES is not set
1504+# CONFIG_CRYPTO_ANUBIS is not set
1505+# CONFIG_CRYPTO_ARC4 is not set
1506+# CONFIG_CRYPTO_BLOWFISH is not set
1507+# CONFIG_CRYPTO_CAMELLIA is not set
1508+# CONFIG_CRYPTO_CAST5 is not set
1509+# CONFIG_CRYPTO_CAST6 is not set
1510+CONFIG_CRYPTO_DES=y
1511+# CONFIG_CRYPTO_FCRYPT is not set
1512+# CONFIG_CRYPTO_KHAZAD is not set
1513+# CONFIG_CRYPTO_SALSA20 is not set
1514+# CONFIG_CRYPTO_SEED is not set
1515+# CONFIG_CRYPTO_SERPENT is not set
1516+# CONFIG_CRYPTO_TEA is not set
1517+# CONFIG_CRYPTO_TWOFISH is not set
1518+
1519+#
1520+# Compression
1521+#
1522+CONFIG_CRYPTO_DEFLATE=y
1523+# CONFIG_CRYPTO_ZLIB is not set
1524+# CONFIG_CRYPTO_LZO is not set
1525+
1526+#
1527+# Random Number Generation
1528+#
1529+# CONFIG_CRYPTO_ANSI_CPRNG is not set
1530+# CONFIG_CRYPTO_HW is not set
1531+# CONFIG_BINARY_PRINTF is not set
1532+
1533+#
1534+# Library routines
1535+#
1536+CONFIG_BITREVERSE=y
1537+CONFIG_GENERIC_FIND_LAST_BIT=y
1538+# CONFIG_CRC_CCITT is not set
1539+# CONFIG_CRC16 is not set
1540+# CONFIG_CRC_T10DIF is not set
1541+# CONFIG_CRC_ITU_T is not set
1542+CONFIG_CRC32=y
1543+# CONFIG_CRC7 is not set
1544+# CONFIG_LIBCRC32C is not set
1545+CONFIG_ZLIB_INFLATE=y
1546+CONFIG_ZLIB_DEFLATE=y
1547+CONFIG_HAS_IOMEM=y
1548+CONFIG_HAS_IOPORT=y
1549+CONFIG_HAS_DMA=y
1550+CONFIG_NLATTR=y
arch/mips/configs/rb532_defconfig+1−2
@@ -9,7 +9,6 @@ CONFIG_MIPS=y · 8 unmodified lines
99 # Machine selection
1010 #
1111 # CONFIG_MACH_ALCHEMY is not set
12−# CONFIG_BASLER_EXCITE is not set
1312 # CONFIG_BCM47XX is not set
1413 # CONFIG_MIPS_COBALT is not set
1514 # CONFIG_MACH_DECSTATION is not set
@@ -1204,7 +1203,7 @@ CONFIG_FRAME_WARN=1024 · 1188 unmodified lines
12041203 # CONFIG_HEADERS_CHECK is not set
12051204 # CONFIG_DEBUG_KERNEL is not set
12061205 # CONFIG_SAMPLES is not set
1207−CONFIG_CMDLINE=""
1206+# CONFIG_CMDLINE_BOOL is not set
12081207
12091208 #
12101209 # Security options
arch/mips/configs/rbtx49xx_defconfig+1−3
@@ -10,7 +10,6 @@ CONFIG_MIPS=y · 9 unmodified lines
1010 #
1111 # CONFIG_MACH_ALCHEMY is not set
1212 # CONFIG_AR7 is not set
13−# CONFIG_BASLER_EXCITE is not set
1413 # CONFIG_BCM47XX is not set
1514 # CONFIG_BCM63XX is not set
1615 # CONFIG_MIPS_COBALT is not set
@@ -284,7 +283,6 @@ CONFIG_DEFAULT_AS=y · 267 unmodified lines
284283 # CONFIG_DEFAULT_CFQ is not set
285284 # CONFIG_DEFAULT_NOOP is not set
286285 CONFIG_DEFAULT_IOSCHED="anticipatory"
287−# CONFIG_PROBE_INITRD_HEADER is not set
288286 # CONFIG_FREEZER is not set
289287
290288 #
@@ -1063,7 +1061,7 @@ CONFIG_TRACING_SUPPORT=y · 772 unmodified lines
10631061 # CONFIG_DYNAMIC_DEBUG is not set
10641062 # CONFIG_SAMPLES is not set
10651063 CONFIG_HAVE_ARCH_KGDB=y
1066−CONFIG_CMDLINE=""
1064+# CONFIG_CMDLINE_BOOL is not set
10671065
10681066 #
10691067 # Security options
arch/mips/configs/rm200_defconfig+1−2
@@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y · 21 unmodified lines
2222 # CONFIG_MIPS_DB1550 is not set
2323 # CONFIG_MIPS_DB1200 is not set
2424 # CONFIG_MIPS_MIRAGE is not set
25−# CONFIG_BASLER_EXCITE is not set
2625 # CONFIG_MIPS_COBALT is not set
2726 # CONFIG_MACH_DECSTATION is not set
2827 # CONFIG_MACH_JAZZ is not set
@@ -1694,7 +1693,7 @@ CONFIG_ENABLE_MUST_CHECK=y · 1665 unmodified lines
16941693 # CONFIG_DEBUG_KERNEL is not set
16951694 CONFIG_LOG_BUF_SHIFT=14
16961695 CONFIG_CROSSCOMPILE=y
1697−CONFIG_CMDLINE=""
1696+# CONFIG_CMDLINE_BOOL is not set
16981697
16991698 #
17001699 # Security options
arch/mips/configs/sb1250-swarm_defconfig+1−2
@@ -9,7 +9,6 @@ CONFIG_MIPS=y · 8 unmodified lines
99 # Machine selection
1010 #
1111 # CONFIG_MACH_ALCHEMY is not set
12−# CONFIG_BASLER_EXCITE is not set
1312 # CONFIG_BCM47XX is not set
1413 # CONFIG_MIPS_COBALT is not set
1514 # CONFIG_MACH_DECSTATION is not set
@@ -961,7 +960,7 @@ CONFIG_ENABLE_MUST_CHECK=y · 945 unmodified lines
961960 # CONFIG_HEADERS_CHECK is not set
962961 # CONFIG_DEBUG_KERNEL is not set
963962 # CONFIG_SAMPLES is not set
964−CONFIG_CMDLINE=""
963+# CONFIG_CMDLINE_BOOL is not set
965964 # CONFIG_SB1XXX_CORELIS is not set
966965
967966 #
arch/mips/configs/tb0219_defconfig+2−1
@@ -9,7 +9,6 @@ CONFIG_MIPS=y · 8 unmodified lines
99 # Machine selection
1010 #
1111 # CONFIG_MACH_ALCHEMY is not set
12−# CONFIG_BASLER_EXCITE is not set
1312 # CONFIG_BCM47XX is not set
1413 # CONFIG_MIPS_COBALT is not set
1514 # CONFIG_MACH_DECSTATION is not set
@@ -892,7 +891,9 @@ CONFIG_FRAME_WARN=1024 · 876 unmodified lines
892891 # CONFIG_HEADERS_CHECK is not set
893892 # CONFIG_DEBUG_KERNEL is not set
894893 # CONFIG_SAMPLES is not set
894+CONFIG_CMDLINE_BOOL=y
895895 CONFIG_CMDLINE="cca=3 mem=64M console=ttyVR0,115200 ip=any root=/dev/nfs"
896+# CONFIG_CMDLINE_OVERRIDE is not set
896897
897898 #
898899 # Security options
arch/mips/configs/tb0226_defconfig+2−1
@@ -9,7 +9,6 @@ CONFIG_MIPS=y · 8 unmodified lines
99 # Machine selection
1010 #
1111 # CONFIG_MACH_ALCHEMY is not set
12−# CONFIG_BASLER_EXCITE is not set
1312 # CONFIG_BCM47XX is not set
1413 # CONFIG_MIPS_COBALT is not set
1514 # CONFIG_MACH_DECSTATION is not set
@@ -895,7 +894,9 @@ CONFIG_FRAME_WARN=1024 · 879 unmodified lines
895894 # CONFIG_HEADERS_CHECK is not set
896895 # CONFIG_DEBUG_KERNEL is not set
897896 # CONFIG_SAMPLES is not set
897+CONFIG_CMDLINE_BOOL=y
898898 CONFIG_CMDLINE="cca=3 mem=32M console=ttyVR0,115200"
899+# CONFIG_CMDLINE_OVERRIDE is not set
899900
900901 #
901902 # Security options
arch/mips/configs/tb0287_defconfig+2−1
@@ -9,7 +9,6 @@ CONFIG_MIPS=y · 8 unmodified lines
99 # Machine selection
1010 #
1111 # CONFIG_MACH_ALCHEMY is not set
12−# CONFIG_BASLER_EXCITE is not set
1312 # CONFIG_BCM47XX is not set
1413 # CONFIG_MIPS_COBALT is not set
1514 # CONFIG_MACH_DECSTATION is not set
@@ -1077,7 +1076,9 @@ CONFIG_FRAME_WARN=1024 · 1061 unmodified lines
10771076 # CONFIG_HEADERS_CHECK is not set
10781077 # CONFIG_DEBUG_KERNEL is not set
10791078 # CONFIG_SAMPLES is not set
1079+CONFIG_CMDLINE_BOOL=y
10801080 CONFIG_CMDLINE="cca=3 mem=64M console=ttyVR0,115200 ip=any root=/dev/nfs"
1081+# CONFIG_CMDLINE_OVERRIDE is not set
10811082
10821083 #
10831084 # Security options
arch/mips/configs/workpad_defconfig+2−1
@@ -9,7 +9,6 @@ CONFIG_MIPS=y · 8 unmodified lines
99 # Machine selection
1010 #
1111 # CONFIG_MACH_ALCHEMY is not set
12−# CONFIG_BASLER_EXCITE is not set
1312 # CONFIG_MIPS_COBALT is not set
1413 # CONFIG_MACH_DECSTATION is not set
1514 # CONFIG_MACH_JAZZ is not set
@@ -755,7 +754,9 @@ CONFIG_ENABLE_MUST_CHECK=y · 739 unmodified lines
755754 # CONFIG_HEADERS_CHECK is not set
756755 # CONFIG_DEBUG_KERNEL is not set
757756 CONFIG_CROSSCOMPILE=y
757+CONFIG_CMDLINE_BOOL=y
758758 CONFIG_CMDLINE="console=ttyVR0,19200 ide0=0x170,0x376,49 mem=16M"
759+# CONFIG_CMDLINE_OVERRIDE is not set
759760
760761 #
761762 # Security options
arch/mips/configs/wrppmc_defconfig+2−1
@@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y · 21 unmodified lines
2222 # CONFIG_MIPS_DB1550 is not set
2323 # CONFIG_MIPS_DB1200 is not set
2424 # CONFIG_MIPS_MIRAGE is not set
25−# CONFIG_BASLER_EXCITE is not set
2625 # CONFIG_MIPS_COBALT is not set
2726 # CONFIG_MACH_DECSTATION is not set
2827 # CONFIG_MACH_JAZZ is not set
@@ -887,7 +886,9 @@ CONFIG_ENABLE_MUST_CHECK=y · 858 unmodified lines
887886 # CONFIG_DEBUG_KERNEL is not set
888887 CONFIG_LOG_BUF_SHIFT=14
889888 CONFIG_CROSSCOMPILE=y
889+CONFIG_CMDLINE_BOOL=y
890890 CONFIG_CMDLINE="console=ttyS0,115200n8"
891+# CONFIG_CMDLINE_OVERRIDE is not set
891892
892893 #
893894 # Security options
arch/mips/configs/yosemite_defconfig+1−2
@@ -22,7 +22,6 @@ CONFIG_ZONE_DMA=y · 21 unmodified lines
2222 # CONFIG_MIPS_DB1550 is not set
2323 # CONFIG_MIPS_DB1200 is not set
2424 # CONFIG_MIPS_MIRAGE is not set
25−# CONFIG_BASLER_EXCITE is not set
2625 # CONFIG_MIPS_COBALT is not set
2726 # CONFIG_MACH_DECSTATION is not set
2827 # CONFIG_MACH_JAZZ is not set
@@ -824,7 +823,7 @@ CONFIG_DEBUG_MUTEXES=y · 795 unmodified lines
824823 CONFIG_FORCED_INLINING=y
825824 # CONFIG_RCU_TORTURE_TEST is not set
826825 CONFIG_CROSSCOMPILE=y
827−CONFIG_CMDLINE=""
826+# CONFIG_CMDLINE_BOOL is not set
828827 # CONFIG_DEBUG_STACK_USAGE is not set
829828 # CONFIG_RUNTIME_DEBUG is not set
830829
arch/mips/fw/arc/cmdline.c+0−5
@@ -16,11 +16,6 @@ · 15 unmodified lines
1616
1717 #undef DEBUG_CMDLINE
1818
19−char * __init prom_getcmdline(void)
20−{
21− return arcs_cmdline;
22−}
23−
2419 static char *ignored[] = {
2520 "ConsoleIn=",
2621 "ConsoleOut=",
arch/mips/include/asm/bootinfo.h+4−4
@@ -67,9 +67,9 @@ · 66 unmodified lines
6767 #define MACH_LEMOTE_ML2F7 3
6868 #define MACH_LEMOTE_YL2F89 4
6969 #define MACH_DEXXON_GDIUM2F10 5
70−#define MACH_LOONGSON_END 6
71−
72−#define CL_SIZE COMMAND_LINE_SIZE
70+#define MACH_LEMOTE_NAS 6
71+#define MACH_LEMOTE_LL2F 7
72+#define MACH_LOONGSON_END 8
7373
7474 extern char *system_type;
7575 const char *get_system_type(void);
@@ -107,7 +107,7 @@ extern void free_init_pages(const char *what, · 31 unmodified lines
107107 /*
108108 * Initial kernel command line, usually setup by prom_init()
109109 */
110−extern char arcs_cmdline[CL_SIZE];
110+extern char arcs_cmdline[COMMAND_LINE_SIZE];
111111
112112 /*
113113 * Registers a0, a1, a3 and a4 as passed to the kernel entry by firmware
arch/mips/include/asm/clock.h+64−0
@@ -0,0 +1,64 @@
1+#ifndef __ASM_MIPS_CLOCK_H
2+#define __ASM_MIPS_CLOCK_H
3+
4+#include <linux/kref.h>
5+#include <linux/list.h>
6+#include <linux/seq_file.h>
7+#include <linux/clk.h>
8+
9+extern void (*cpu_wait) (void);
10+
11+struct clk;
12+
13+struct clk_ops {
14+ void (*init) (struct clk *clk);
15+ void (*enable) (struct clk *clk);
16+ void (*disable) (struct clk *clk);
17+ void (*recalc) (struct clk *clk);
18+ int (*set_rate) (struct clk *clk, unsigned long rate, int algo_id);
19+ long (*round_rate) (struct clk *clk, unsigned long rate);
20+};
21+
22+struct clk {
23+ struct list_head node;
24+ const char *name;
25+ int id;
26+ struct module *owner;
27+
28+ struct clk *parent;
29+ struct clk_ops *ops;
30+
31+ struct kref kref;
32+
33+ unsigned long rate;
34+ unsigned long flags;
35+};
36+
37+#define CLK_ALWAYS_ENABLED (1 << 0)
38+#define CLK_RATE_PROPAGATES (1 << 1)
39+
40+/* Should be defined by processor-specific code */
41+void arch_init_clk_ops(struct clk_ops **, int type);
42+
43+int clk_init(void);
44+
45+int __clk_enable(struct clk *);
46+void __clk_disable(struct clk *);
47+
48+void clk_recalc_rate(struct clk *);
49+
50+int clk_register(struct clk *);
51+void clk_unregister(struct clk *);
52+
53+/* the exported API, in addition to clk_set_rate */
54+/**
55+ * clk_set_rate_ex - set the clock rate for a clock source, with additional parameter
56+ * @clk: clock source
57+ * @rate: desired clock rate in Hz
58+ * @algo_id: algorithm id to be passed down to ops->set_rate
59+ *
60+ * Returns success (0) or negative errno.
61+ */
62+int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id);
63+
64+#endif /* __ASM_MIPS_CLOCK_H */
arch/mips/include/asm/cop2.h+23−0
@@ -0,0 +1,23 @@
1+/*
2+ * This file is subject to the terms and conditions of the GNU General Public
3+ * License. See the file "COPYING" in the main directory of this archive
4+ * for more details.
5+ *
6+ * Copyright (C) 2009 Wind River Systems,
7+ * written by Ralf Baechle <ralf@linux-mips.org>
8+ */
9+#ifndef __ASM_COP2_H
10+#define __ASM_COP2_H
11+
12+enum cu2_ops {
13+ CU2_EXCEPTION,
14+ CU2_LWC2_OP,
15+ CU2_LDC2_OP,
16+ CU2_SWC2_OP,
17+ CU2_SDC2_OP,
18+};
19+
20+extern int register_cu2_notifier(struct notifier_block *nb);
21+extern int cu2_notifier_call_chain(unsigned long val, void *v);
22+
23+#endif /* __ASM_COP2_H */
arch/mips/include/asm/cpu.h+2−0
@@ -154,6 +154,8 @@ · 153 unmodified lines
154154 #define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */
155155 #define PRID_REV_VR4130 0x0080
156156 #define PRID_REV_34K_V1_0_2 0x0022
157+#define PRID_REV_LOONGSON2E 0x0002
158+#define PRID_REV_LOONGSON2F 0x0003
157159
158160 /*
159161 * Older processors used to encode processor version and revision in two
arch/mips/include/asm/fpu.h+0−8
@@ -28,15 +28,7 @@ · 27 unmodified lines
2828 struct sigcontext;
2929 struct sigcontext32;
3030
31−extern asmlinkage int (*save_fp_context)(struct sigcontext __user *sc);
32−extern asmlinkage int (*restore_fp_context)(struct sigcontext __user *sc);
33−
34−extern asmlinkage int (*save_fp_context32)(struct sigcontext32 __user *sc);
35−extern asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc);
36−
3731 extern void fpu_emulator_init_fpu(void);
38−extern int fpu_emulator_save_context(struct sigcontext __user *sc);
39−extern int fpu_emulator_restore_context(struct sigcontext __user *sc);
4032 extern void _init_fpu(void);
4133 extern void _save_fp(struct task_struct *);
4234 extern void _restore_fp(struct task_struct *);
arch/mips/include/asm/fpu_emulator.h+17−7
@@ -25,17 +25,27 @@ · 24 unmodified lines
2525
2626 #include <asm/break.h>
2727 #include <asm/inst.h>
28+#include <asm/local.h>
29+
30+#ifdef CONFIG_DEBUG_FS
2831
2932 struct mips_fpu_emulator_stats {
30− unsigned int emulated;
31− unsigned int loads;
32− unsigned int stores;
33− unsigned int cp1ops;
34− unsigned int cp1xops;
35− unsigned int errors;
33+ local_t emulated;
34+ local_t loads;
35+ local_t stores;
36+ local_t cp1ops;
37+ local_t cp1xops;
38+ local_t errors;
3639 };
3740
38−extern struct mips_fpu_emulator_stats fpuemustats;
41+DECLARE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats);
42+
43+#define MIPS_FPU_EMU_INC_STATS(M) \
44+ cpu_local_wrap(__local_inc(&__get_cpu_var(fpuemustats).M))
45+
46+#else
47+#define MIPS_FPU_EMU_INC_STATS(M) do { } while (0)
48+#endif /* CONFIG_DEBUG_FS */
3949
4050 extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir,
4151 unsigned long cpc);
arch/mips/include/asm/ftrace.h+90−1
@@ -1 +1,90 @@
1−/* empty */
1+/*
2+ * This file is subject to the terms and conditions of the GNU General Public
3+ * License. See the file "COPYING" in the main directory of this archive for
4+ * more details.
5+ *
6+ * Copyright (C) 2009 DSLab, Lanzhou University, China
7+ * Author: Wu Zhangjin <wuzj@lemote.com>
8+ */
9+
10+#ifndef _ASM_MIPS_FTRACE_H
11+#define _ASM_MIPS_FTRACE_H
12+
13+#ifdef CONFIG_FUNCTION_TRACER
14+
15+#define MCOUNT_ADDR ((unsigned long)(_mcount))
16+#define MCOUNT_INSN_SIZE 4 /* sizeof mcount call */
17+
18+#ifndef __ASSEMBLY__
19+extern void _mcount(void);
20+#define mcount _mcount
21+
22+#define safe_load(load, src, dst, error) \
23+do { \
24+ asm volatile ( \
25+ "1: " load " %[" STR(dst) "], 0(%[" STR(src) "])\n"\
26+ " li %[" STR(error) "], 0\n" \
27+ "2:\n" \
28+ \
29+ ".section .fixup, \"ax\"\n" \
30+ "3: li %[" STR(error) "], 1\n" \
31+ " j 2b\n" \
32+ ".previous\n" \
33+ \
34+ ".section\t__ex_table,\"a\"\n\t" \
35+ STR(PTR) "\t1b, 3b\n\t" \
36+ ".previous\n" \
37+ \
38+ : [dst] "=&r" (dst), [error] "=r" (error)\
39+ : [src] "r" (src) \
40+ : "memory" \
41+ ); \
42+} while (0)
43+
44+#define safe_store(store, src, dst, error) \
45+do { \
46+ asm volatile ( \
47+ "1: " store " %[" STR(src) "], 0(%[" STR(dst) "])\n"\
48+ " li %[" STR(error) "], 0\n" \
49+ "2:\n" \
50+ \
51+ ".section .fixup, \"ax\"\n" \
52+ "3: li %[" STR(error) "], 1\n" \
53+ " j 2b\n" \
54+ ".previous\n" \
55+ \
56+ ".section\t__ex_table,\"a\"\n\t"\
57+ STR(PTR) "\t1b, 3b\n\t" \
58+ ".previous\n" \
59+ \
60+ : [error] "=r" (error) \
61+ : [dst] "r" (dst), [src] "r" (src)\
62+ : "memory" \
63+ ); \
64+} while (0)
65+
66+#define safe_load_code(dst, src, error) \
67+ safe_load(STR(lw), src, dst, error)
68+#define safe_store_code(src, dst, error) \
69+ safe_store(STR(sw), src, dst, error)
70+
71+#define safe_load_stack(dst, src, error) \
72+ safe_load(STR(PTR_L), src, dst, error)
73+
74+#define safe_store_stack(src, dst, error) \
75+ safe_store(STR(PTR_S), src, dst, error)
76+
77+
78+#ifdef CONFIG_DYNAMIC_FTRACE
79+static inline unsigned long ftrace_call_adjust(unsigned long addr)
80+{
81+ return addr;
82+}
83+
84+struct dyn_arch_ftrace {
85+};
86+
87+#endif /* CONFIG_DYNAMIC_FTRACE */
88+#endif /* __ASSEMBLY__ */
89+#endif /* CONFIG_FUNCTION_TRACER */
90+#endif /* _ASM_MIPS_FTRACE_H */
arch/mips/include/asm/irq.h+2−27
@@ -113,36 +113,11 @@ do { \ · 112 unmodified lines
113113
114114 #endif
115115
116−/*
117− * do_IRQ handles all normal device IRQ's (the special
118− * SMP cross-CPU interrupts have their own specific
119− * handlers).
120− *
121− * Ideally there should be away to get this into kernel/irq/handle.c to
122− * avoid the overhead of a call for just a tiny function ...
123− */
124−#define do_IRQ(irq) \
125−do { \
126− irq_enter(); \
127− __DO_IRQ_SMTC_HOOK(irq); \
128− generic_handle_irq(irq); \
129− irq_exit(); \
130−} while (0)
116+extern void do_IRQ(unsigned int irq);
131117
132118 #ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
133−/*
134− * To avoid inefficient and in some cases pathological re-checking of
135− * IRQ affinity, we have this variant that skips the affinity check.
136− */
137−
138119
139−#define do_IRQ_no_affinity(irq) \
140−do { \
141− irq_enter(); \
142− __NO_AFFINITY_IRQ_SMTC_HOOK(irq); \
143− generic_handle_irq(irq); \
144− irq_exit(); \
145−} while (0)
120+extern void do_IRQ_no_affinity(unsigned int irq);
146121
147122 #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
148123
arch/mips/include/asm/mach-excite/cpu-feature-overrides.h+0−48
@@ -1,48 +0,0 @@
1−/*
2− * This file is subject to the terms and conditions of the GNU General Public
3− * License. See the file "COPYING" in the main directory of this archive
4− * for more details.
5− *
6− * Copyright (C) 2004 Thomas Koeller <thomas.koeller@baslerweb.com>
7− * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
8− */
9−#ifndef __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H
10−#define __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H
11−
12−/*
13− * Basler eXcite has an RM9122 processor.
14− */
15−#define cpu_has_watch 1
16−#define cpu_has_mips16 0
17−#define cpu_has_divec 0
18−#define cpu_has_vce 0
19−#define cpu_has_cache_cdex_p 0
20−#define cpu_has_cache_cdex_s 0
21−#define cpu_has_prefetch 1
22−#define cpu_has_mcheck 0
23−#define cpu_has_ejtag 0
24−
25−#define cpu_has_llsc 1
26−#define cpu_has_vtag_icache 0
27−#define cpu_has_dc_aliases 0
28−#define cpu_has_ic_fills_f_dc 0
29−#define cpu_has_dsp 0
30−#define cpu_icache_snoops_remote_store 0
31−#define cpu_has_mipsmt 0
32−#define cpu_has_userlocal 0
33−
34−#define cpu_has_nofpuex 0
35−#define cpu_has_64bits 1
36−
37−#define cpu_has_mips32r1 0
38−#define cpu_has_mips32r2 0
39−#define cpu_has_mips64r1 0
40−#define cpu_has_mips64r2 0
41−
42−#define cpu_has_inclusive_pcaches 0
43−
44−#define cpu_dcache_line_size() 32
45−#define cpu_icache_line_size() 32
46−#define cpu_scache_line_size() 32
47−
48−#endif /* __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H */
arch/mips/include/asm/mach-excite/excite.h+0−154
@@ -1,154 +0,0 @@
1−#ifndef __EXCITE_H__
2−#define __EXCITE_H__
3−
4−#include <linux/init.h>
5−#include <asm/addrspace.h>
6−#include <asm/types.h>
7−
8−#define EXCITE_CPU_EXT_CLOCK 100000000
9−
10−#if !defined(__ASSEMBLY__)
11−void __init excite_kgdb_init(void);
12−void excite_procfs_init(void);
13−extern unsigned long memsize;
14−extern char modetty[];
15−extern u32 unit_id;
16−#endif
17−
18−/* Base name for XICAP devices */
19−#define XICAP_NAME "xicap_gpi"
20−
21−/* OCD register offsets */
22−#define LKB0 0x0038
23−#define LKB5 0x0128
24−#define LKM5 0x012C
25−#define LKB7 0x0138
26−#define LKM7 0x013c
27−#define LKB8 0x0140
28−#define LKM8 0x0144
29−#define LKB9 0x0148
30−#define LKM9 0x014c
31−#define LKB10 0x0150
32−#define LKM10 0x0154
33−#define LKB11 0x0158
34−#define LKM11 0x015c
35−#define LKB12 0x0160
36−#define LKM12 0x0164
37−#define LKB13 0x0168
38−#define LKM13 0x016c
39−#define LDP0 0x0200
40−#define LDP1 0x0210
41−#define LDP2 0x0220
42−#define LDP3 0x0230
43−#define INTPIN0 0x0A40
44−#define INTPIN1 0x0A44
45−#define INTPIN2 0x0A48
46−#define INTPIN3 0x0A4C
47−#define INTPIN4 0x0A50
48−#define INTPIN5 0x0A54
49−#define INTPIN6 0x0A58
50−#define INTPIN7 0x0A5C
51−
52−
53−
54−
55−/* TITAN register offsets */
56−#define CPRR 0x0004
57−#define CPDSR 0x0008
58−#define CPTC0R 0x000c
59−#define CPTC1R 0x0010
60−#define CPCFG0 0x0020
61−#define CPCFG1 0x0024
62−#define CPDST0A 0x0028
63−#define CPDST0B 0x002c
64−#define CPDST1A 0x0030
65−#define CPDST1B 0x0034
66−#define CPXDSTA 0x0038
67−#define CPXDSTB 0x003c
68−#define CPXCISRA 0x0048
69−#define CPXCISRB 0x004c
70−#define CPGIG0ER 0x0050
71−#define CPGIG1ER 0x0054
72−#define CPGRWL 0x0068
73−#define CPURSLMT 0x00f8
74−#define UACFG 0x0200
75−#define UAINTS 0x0204
76−#define SDRXFCIE 0x4828
77−#define SDTXFCIE 0x4928
78−#define INTP0Status0 0x1B00
79−#define INTP0Mask0 0x1B04
80−#define INTP0Set0 0x1B08
81−#define INTP0Clear0 0x1B0C
82−#define GXCFG 0x5000
83−#define GXDMADRPFX 0x5018
84−#define GXDMA_DESCADR 0x501c
85−#define GXCH0TDESSTRT 0x5054
86−
87−/* IRQ definitions */
88−#define NMICONFIG 0xac0
89−#define TITAN_MSGINT 0xc4
90−#define TITAN_IRQ ((TITAN_MSGINT / 0x20) + 2)
91−#define FPGA0_MSGINT 0x5a
92−#define FPGA0_IRQ ((FPGA0_MSGINT / 0x20) + 2)
93−#define FPGA1_MSGINT 0x7b
94−#define FPGA1_IRQ ((FPGA1_MSGINT / 0x20) + 2)
95−#define PHY_MSGINT 0x9c
96−#define PHY_IRQ ((PHY_MSGINT / 0x20) + 2)
97−
98−#if defined(CONFIG_BASLER_EXCITE_PROTOTYPE)
99−/* Pre-release units used interrupt pin #9 */
100−#define USB_IRQ 11
101−#else
102−/* Re-designed units use interrupt pin #1 */
103−#define USB_MSGINT 0x39
104−#define USB_IRQ ((USB_MSGINT / 0x20) + 2)
105−#endif
106−#define TIMER_IRQ 12
107−
108−
109−/* Device address ranges */
110−#define EXCITE_OFFS_OCD 0x1fffc000
111−#define EXCITE_SIZE_OCD (16 * 1024)
112−#define EXCITE_PHYS_OCD CPHYSADDR(EXCITE_OFFS_OCD)
113−#define EXCITE_ADDR_OCD CKSEG1ADDR(EXCITE_OFFS_OCD)
114−
115−#define EXCITE_OFFS_SCRAM 0x1fffa000
116−#define EXCITE_SIZE_SCRAM (8 << 10)
117−#define EXCITE_PHYS_SCRAM CPHYSADDR(EXCITE_OFFS_SCRAM)
118−#define EXCITE_ADDR_SCRAM CKSEG1ADDR(EXCITE_OFFS_SCRAM)
119−
120−#define EXCITE_OFFS_PCI_IO 0x1fff8000
121−#define EXCITE_SIZE_PCI_IO (8 << 10)
122−#define EXCITE_PHYS_PCI_IO CPHYSADDR(EXCITE_OFFS_PCI_IO)
123−#define EXCITE_ADDR_PCI_IO CKSEG1ADDR(EXCITE_OFFS_PCI_IO)
124−
125−#define EXCITE_OFFS_TITAN 0x1fff0000
126−#define EXCITE_SIZE_TITAN (32 << 10)
127−#define EXCITE_PHYS_TITAN CPHYSADDR(EXCITE_OFFS_TITAN)
128−#define EXCITE_ADDR_TITAN CKSEG1ADDR(EXCITE_OFFS_TITAN)
129−
130−#define EXCITE_OFFS_PCI_MEM 0x1ffe0000
131−#define EXCITE_SIZE_PCI_MEM (64 << 10)
132−#define EXCITE_PHYS_PCI_MEM CPHYSADDR(EXCITE_OFFS_PCI_MEM)
133−#define EXCITE_ADDR_PCI_MEM CKSEG1ADDR(EXCITE_OFFS_PCI_MEM)
134−
135−#define EXCITE_OFFS_FPGA 0x1ffdc000
136−#define EXCITE_SIZE_FPGA (16 << 10)
137−#define EXCITE_PHYS_FPGA CPHYSADDR(EXCITE_OFFS_FPGA)
138−#define EXCITE_ADDR_FPGA CKSEG1ADDR(EXCITE_OFFS_FPGA)
139−
140−#define EXCITE_OFFS_NAND 0x1ffd8000
141−#define EXCITE_SIZE_NAND (16 << 10)
142−#define EXCITE_PHYS_NAND CPHYSADDR(EXCITE_OFFS_NAND)
143−#define EXCITE_ADDR_NAND CKSEG1ADDR(EXCITE_OFFS_NAND)
144−
145−#define EXCITE_OFFS_BOOTROM 0x1f000000
146−#define EXCITE_SIZE_BOOTROM (8 << 20)
147−#define EXCITE_PHYS_BOOTROM CPHYSADDR(EXCITE_OFFS_BOOTROM)
148−#define EXCITE_ADDR_BOOTROM CKSEG1ADDR(EXCITE_OFFS_BOOTROM)
149−
150−/* FPGA address offsets */
151−#define EXCITE_FPGA_DPR 0x0104 /* dual-ported ram */
152−#define EXCITE_FPGA_SYSCTL 0x0200 /* system control register block */
153−
154−#endif /* __EXCITE_H__ */
arch/mips/include/asm/mach-excite/excite_fpga.h+0−80
@@ -1,80 +0,0 @@
1−#ifndef EXCITE_FPGA_H_INCLUDED
2−#define EXCITE_FPGA_H_INCLUDED
3−
4−
5−/**
6− * Address alignment of the individual FPGA bytes.
7− * The address arrangement of the individual bytes of the FPGA is two
8− * byte aligned at the embedded MK2 platform.
9− */
10−#ifdef EXCITE_CCI_FPGA_MK2
11−typedef unsigned char excite_cci_fpga_align_t __attribute__ ((aligned(2)));
12−#else
13−typedef unsigned char excite_cci_fpga_align_t;
14−#endif
15−
16−
17−/**
18− * Size of Dual Ported RAM.
19− */
20−#define EXCITE_DPR_SIZE 263
21−
22−
23−/**
24− * Size of Reserved Status Fields in Dual Ported RAM.
25− */
26−#define EXCITE_DPR_STATUS_SIZE 7
27−
28−
29−
30−/**
31− * FPGA.
32− * Hardware register layout of the FPGA interface. The FPGA must accessed
33− * byte wise solely.
34− * @see EXCITE_CCI_DPR_MK2
35− */
36−typedef struct excite_fpga {
37−
38− /**
39− * Dual Ported RAM.
40− */
41− excite_cci_fpga_align_t dpr[EXCITE_DPR_SIZE];
42−
43− /**
44− * Status.
45− */
46− excite_cci_fpga_align_t status[EXCITE_DPR_STATUS_SIZE];
47−
48−#ifdef EXCITE_CCI_FPGA_MK2
49− /**
50− * RM9000 Interrupt.
51− * Write access initiates interrupt at the RM9000 (MIPS) processor of the eXcite.
52− */
53− excite_cci_fpga_align_t rm9k_int;
54−#else
55− /**
56− * MK2 Interrupt.
57− * Write access initiates interrupt at the ARM processor of the MK2.
58− */
59− excite_cci_fpga_align_t mk2_int;
60−
61− excite_cci_fpga_align_t gap[0x1000-0x10f];
62−
63− /**
64− * IRQ Source/Acknowledge.
65− */
66− excite_cci_fpga_align_t rm9k_irq_src;
67−
68− /**
69− * IRQ Mask.
70− * Set bits enable the related interrupt.
71− */
72− excite_cci_fpga_align_t rm9k_irq_mask;
73−#endif
74−
75−
76−} excite_fpga;
77−
78−
79−
80−#endif /* ndef EXCITE_FPGA_H_INCLUDED */
arch/mips/include/asm/mach-excite/excite_nandflash.h+0−7
@@ -1,7 +0,0 @@
1−#ifndef __EXCITE_NANDFLASH_H__
2−#define __EXCITE_NANDFLASH_H__
3−
4−/* Resource names */
5−#define EXCITE_NANDFLASH_RESOURCE_REGS "excite_nandflash_regs"
6−
7−#endif /* __EXCITE_NANDFLASH_H__ */
arch/mips/include/asm/mach-excite/rm9k_eth.h+0−23
@@ -1,23 +0,0 @@
1−#if !defined(__RM9K_ETH_H__)
2−#define __RM9K_ETH_H__
3−
4−#define RM9K_GE_NAME "rm9k_ge"
5−
6−/* Resource names */
7−#define RM9K_GE_RESOURCE_MAC "rm9k_ge_mac"
8−#define RM9K_GE_RESOURCE_MSTAT "rm9k_ge_mstat"
9−#define RM9K_GE_RESOURCE_PKTPROC "rm9k_ge_pktproc"
10−#define RM9K_GE_RESOURCE_XDMA "rm9k_ge_xdma"
11−#define RM9K_GE_RESOURCE_FIFO_RX "rm9k_ge_fifo_rx"
12−#define RM9K_GE_RESOURCE_FIFO_TX "rm9k_ge_fifo_tx"
13−#define RM9K_GE_RESOURCE_FIFOMEM_RX "rm9k_ge_fifo_memory_rx"
14−#define RM9K_GE_RESOURCE_FIFOMEM_TX "rm9k_ge_fifo_memory_tx"
15−#define RM9K_GE_RESOURCE_PHY "rm9k_ge_phy"
16−#define RM9K_GE_RESOURCE_DMADESC_RX "rm9k_ge_dmadesc_rx"
17−#define RM9K_GE_RESOURCE_DMADESC_TX "rm9k_ge_dmadesc_tx"
18−#define RM9K_GE_RESOURCE_IRQ_MAIN "rm9k_ge_irq_main"
19−#define RM9K_GE_RESOURCE_IRQ_PHY "rm9k_ge_irq_phy"
20−#define RM9K_GE_RESOURCE_GPI_SLICE "rm9k_ge_gpi_slice"
21−#define RM9K_GE_RESOURCE_MDIO_CHANNEL "rm9k_ge_mdio_channel"
22−
23−#endif /* !defined(__RM9K_ETH_H__) */
arch/mips/include/asm/mach-excite/rm9k_wdt.h+0−12
@@ -1,12 +0,0 @@
1−#ifndef __RM9K_WDT_H__
2−#define __RM9K_WDT_H__
3−
4−/* Device name */
5−#define WDT_NAME "wdt_gpi"
6−
7−/* Resource names */
8−#define WDT_RESOURCE_REGS "excite_watchdog_regs"
9−#define WDT_RESOURCE_IRQ "excite_watchdog_irq"
10−#define WDT_RESOURCE_COUNTER "excite_watchdog_counter"
11−
12−#endif /* __RM9K_WDT_H__ */
arch/mips/include/asm/mach-excite/rm9k_xicap.h+0−16
@@ -1,16 +0,0 @@
1−#ifndef __EXCITE_XICAP_H__
2−#define __EXCITE_XICAP_H__
3−
4−
5−/* Resource names */
6−#define XICAP_RESOURCE_FIFO_RX "xicap_fifo_rx"
7−#define XICAP_RESOURCE_FIFO_TX "xicap_fifo_tx"
8−#define XICAP_RESOURCE_XDMA "xicap_xdma"
9−#define XICAP_RESOURCE_DMADESC "xicap_dmadesc"
10−#define XICAP_RESOURCE_PKTPROC "xicap_pktproc"
11−#define XICAP_RESOURCE_IRQ "xicap_irq"
12−#define XICAP_RESOURCE_GPI_SLICE "xicap_gpi_slice"
13−#define XICAP_RESOURCE_FIFO_BLK "xicap_fifo_blocks"
14−#define XICAP_RESOURCE_PKT_STREAM "xicap_pkt_stream"
15−
16−#endif /* __EXCITE_XICAP_H__ */
arch/mips/include/asm/mach-loongson/cs5536/cs5536.h+305−0
@@ -0,0 +1,305 @@
1+/*
2+ * The header file of cs5536 sourth bridge.
3+ *
4+ * Copyright (C) 2007 Lemote, Inc.
5+ * Author : jlliu <liujl@lemote.com>
6+ */
7+
8+#ifndef _CS5536_H
9+#define _CS5536_H
10+
11+#include <linux/types.h>
12+
13+extern void _rdmsr(u32 msr, u32 *hi, u32 *lo);
14+extern void _wrmsr(u32 msr, u32 hi, u32 lo);
15+
16+/*
17+ * MSR module base
18+ */
19+#define CS5536_SB_MSR_BASE (0x00000000)
20+#define CS5536_GLIU_MSR_BASE (0x10000000)
21+#define CS5536_ILLEGAL_MSR_BASE (0x20000000)
22+#define CS5536_USB_MSR_BASE (0x40000000)
23+#define CS5536_IDE_MSR_BASE (0x60000000)
24+#define CS5536_DIVIL_MSR_BASE (0x80000000)
25+#define CS5536_ACC_MSR_BASE (0xa0000000)
26+#define CS5536_UNUSED_MSR_BASE (0xc0000000)
27+#define CS5536_GLCP_MSR_BASE (0xe0000000)
28+
29+#define SB_MSR_REG(offset) (CS5536_SB_MSR_BASE | (offset))
30+#define GLIU_MSR_REG(offset) (CS5536_GLIU_MSR_BASE | (offset))
31+#define ILLEGAL_MSR_REG(offset) (CS5536_ILLEGAL_MSR_BASE | (offset))
32+#define USB_MSR_REG(offset) (CS5536_USB_MSR_BASE | (offset))
33+#define IDE_MSR_REG(offset) (CS5536_IDE_MSR_BASE | (offset))
34+#define DIVIL_MSR_REG(offset) (CS5536_DIVIL_MSR_BASE | (offset))
35+#define ACC_MSR_REG(offset) (CS5536_ACC_MSR_BASE | (offset))
36+#define UNUSED_MSR_REG(offset) (CS5536_UNUSED_MSR_BASE | (offset))
37+#define GLCP_MSR_REG(offset) (CS5536_GLCP_MSR_BASE | (offset))
38+
39+/*
40+ * BAR SPACE OF VIRTUAL PCI :
41+ * range for pci probe use, length is the actual size.
42+ */
43+/* IO space for all DIVIL modules */
44+#define CS5536_IRQ_RANGE 0xffffffe0 /* USERD FOR PCI PROBE */
45+#define CS5536_IRQ_LENGTH 0x20 /* THE REGS ACTUAL LENGTH */
46+#define CS5536_SMB_RANGE 0xfffffff8
47+#define CS5536_SMB_LENGTH 0x08
48+#define CS5536_GPIO_RANGE 0xffffff00
49+#define CS5536_GPIO_LENGTH 0x100
50+#define CS5536_MFGPT_RANGE 0xffffffc0
51+#define CS5536_MFGPT_LENGTH 0x40
52+#define CS5536_ACPI_RANGE 0xffffffe0
53+#define CS5536_ACPI_LENGTH 0x20
54+#define CS5536_PMS_RANGE 0xffffff80
55+#define CS5536_PMS_LENGTH 0x80
56+/* IO space for IDE */
57+#define CS5536_IDE_RANGE 0xfffffff0
58+#define CS5536_IDE_LENGTH 0x10
59+/* IO space for ACC */
60+#define CS5536_ACC_RANGE 0xffffff80
61+#define CS5536_ACC_LENGTH 0x80
62+/* MEM space for ALL USB modules */
63+#define CS5536_OHCI_RANGE 0xfffff000
64+#define CS5536_OHCI_LENGTH 0x1000
65+#define CS5536_EHCI_RANGE 0xfffff000
66+#define CS5536_EHCI_LENGTH 0x1000
67+
68+/*
69+ * PCI MSR ACCESS
70+ */
71+#define PCI_MSR_CTRL 0xF0
72+#define PCI_MSR_ADDR 0xF4
73+#define PCI_MSR_DATA_LO 0xF8
74+#define PCI_MSR_DATA_HI 0xFC
75+
76+/**************** MSR *****************************/
77+
78+/*
79+ * GLIU STANDARD MSR
80+ */
81+#define GLIU_CAP 0x00
82+#define GLIU_CONFIG 0x01
83+#define GLIU_SMI 0x02
84+#define GLIU_ERROR 0x03
85+#define GLIU_PM 0x04
86+#define GLIU_DIAG 0x05
87+
88+/*
89+ * GLIU SPEC. MSR
90+ */
91+#define GLIU_P2D_BM0 0x20
92+#define GLIU_P2D_BM1 0x21
93+#define GLIU_P2D_BM2 0x22
94+#define GLIU_P2D_BMK0 0x23
95+#define GLIU_P2D_BMK1 0x24
96+#define GLIU_P2D_BM3 0x25
97+#define GLIU_P2D_BM4 0x26
98+#define GLIU_COH 0x80
99+#define GLIU_PAE 0x81
100+#define GLIU_ARB 0x82
101+#define GLIU_ASMI 0x83
102+#define GLIU_AERR 0x84
103+#define GLIU_DEBUG 0x85
104+#define GLIU_PHY_CAP 0x86
105+#define GLIU_NOUT_RESP 0x87
106+#define GLIU_NOUT_WDATA 0x88
107+#define GLIU_WHOAMI 0x8B
108+#define GLIU_SLV_DIS 0x8C
109+#define GLIU_IOD_BM0 0xE0
110+#define GLIU_IOD_BM1 0xE1
111+#define GLIU_IOD_BM2 0xE2
112+#define GLIU_IOD_BM3 0xE3
113+#define GLIU_IOD_BM4 0xE4
114+#define GLIU_IOD_BM5 0xE5
115+#define GLIU_IOD_BM6 0xE6
116+#define GLIU_IOD_BM7 0xE7
117+#define GLIU_IOD_BM8 0xE8
118+#define GLIU_IOD_BM9 0xE9
119+#define GLIU_IOD_SC0 0xEA
120+#define GLIU_IOD_SC1 0xEB
121+#define GLIU_IOD_SC2 0xEC
122+#define GLIU_IOD_SC3 0xED
123+#define GLIU_IOD_SC4 0xEE
124+#define GLIU_IOD_SC5 0xEF
125+#define GLIU_IOD_SC6 0xF0
126+#define GLIU_IOD_SC7 0xF1
127+
128+/*
129+ * SB STANDARD
130+ */
131+#define SB_CAP 0x00
132+#define SB_CONFIG 0x01
133+#define SB_SMI 0x02
134+#define SB_ERROR 0x03
135+#define SB_MAR_ERR_EN 0x00000001
136+#define SB_TAR_ERR_EN 0x00000002
137+#define SB_RSVD_BIT1 0x00000004
138+#define SB_EXCEP_ERR_EN 0x00000008
139+#define SB_SYSE_ERR_EN 0x00000010
140+#define SB_PARE_ERR_EN 0x00000020
141+#define SB_TAS_ERR_EN 0x00000040
142+#define SB_MAR_ERR_FLAG 0x00010000
143+#define SB_TAR_ERR_FLAG 0x00020000
144+#define SB_RSVD_BIT2 0x00040000
145+#define SB_EXCEP_ERR_FLAG 0x00080000
146+#define SB_SYSE_ERR_FLAG 0x00100000
147+#define SB_PARE_ERR_FLAG 0x00200000
148+#define SB_TAS_ERR_FLAG 0x00400000
149+#define SB_PM 0x04
150+#define SB_DIAG 0x05
151+
152+/*
153+ * SB SPEC.
154+ */
155+#define SB_CTRL 0x10
156+#define SB_R0 0x20
157+#define SB_R1 0x21
158+#define SB_R2 0x22
159+#define SB_R3 0x23
160+#define SB_R4 0x24
161+#define SB_R5 0x25
162+#define SB_R6 0x26
163+#define SB_R7 0x27
164+#define SB_R8 0x28
165+#define SB_R9 0x29
166+#define SB_R10 0x2A
167+#define SB_R11 0x2B
168+#define SB_R12 0x2C
169+#define SB_R13 0x2D
170+#define SB_R14 0x2E
171+#define SB_R15 0x2F
172+
173+/*
174+ * GLCP STANDARD
175+ */
176+#define GLCP_CAP 0x00
177+#define GLCP_CONFIG 0x01
178+#define GLCP_SMI 0x02
179+#define GLCP_ERROR 0x03
180+#define GLCP_PM 0x04
181+#define GLCP_DIAG 0x05
182+
183+/*
184+ * GLCP SPEC.
185+ */
186+#define GLCP_CLK_DIS_DELAY 0x08
187+#define GLCP_PM_CLK_DISABLE 0x09
188+#define GLCP_GLB_PM 0x0B
189+#define GLCP_DBG_OUT 0x0C
190+#define GLCP_RSVD1 0x0D
191+#define GLCP_SOFT_COM 0x0E
192+#define SOFT_BAR_SMB_FLAG 0x00000001
193+#define SOFT_BAR_GPIO_FLAG 0x00000002
194+#define SOFT_BAR_MFGPT_FLAG 0x00000004
195+#define SOFT_BAR_IRQ_FLAG 0x00000008
196+#define SOFT_BAR_PMS_FLAG 0x00000010
197+#define SOFT_BAR_ACPI_FLAG 0x00000020
198+#define SOFT_BAR_IDE_FLAG 0x00000400
199+#define SOFT_BAR_ACC_FLAG 0x00000800
200+#define SOFT_BAR_OHCI_FLAG 0x00001000
201+#define SOFT_BAR_EHCI_FLAG 0x00002000
202+#define GLCP_RSVD2 0x0F
203+#define GLCP_CLK_OFF 0x10
204+#define GLCP_CLK_ACTIVE 0x11
205+#define GLCP_CLK_DISABLE 0x12
206+#define GLCP_CLK4ACK 0x13
207+#define GLCP_SYS_RST 0x14
208+#define GLCP_RSVD3 0x15
209+#define GLCP_DBG_CLK_CTRL 0x16
210+#define GLCP_CHIP_REV_ID 0x17
211+
212+/* PIC */
213+#define PIC_YSEL_LOW 0x20
214+#define PIC_YSEL_LOW_USB_SHIFT 8
215+#define PIC_YSEL_LOW_ACC_SHIFT 16
216+#define PIC_YSEL_LOW_FLASH_SHIFT 24
217+#define PIC_YSEL_HIGH 0x21
218+#define PIC_ZSEL_LOW 0x22
219+#define PIC_ZSEL_HIGH 0x23
220+#define PIC_IRQM_PRIM 0x24
221+#define PIC_IRQM_LPC 0x25
222+#define PIC_XIRR_STS_LOW 0x26
223+#define PIC_XIRR_STS_HIGH 0x27
224+#define PCI_SHDW 0x34
225+
226+/*
227+ * DIVIL STANDARD
228+ */
229+#define DIVIL_CAP 0x00
230+#define DIVIL_CONFIG 0x01
231+#define DIVIL_SMI 0x02
232+#define DIVIL_ERROR 0x03
233+#define DIVIL_PM 0x04
234+#define DIVIL_DIAG 0x05
235+
236+/*
237+ * DIVIL SPEC.
238+ */
239+#define DIVIL_LBAR_IRQ 0x08
240+#define DIVIL_LBAR_KEL 0x09
241+#define DIVIL_LBAR_SMB 0x0B
242+#define DIVIL_LBAR_GPIO 0x0C
243+#define DIVIL_LBAR_MFGPT 0x0D
244+#define DIVIL_LBAR_ACPI 0x0E
245+#define DIVIL_LBAR_PMS 0x0F
246+#define DIVIL_LEG_IO 0x14
247+#define DIVIL_BALL_OPTS 0x15
248+#define DIVIL_SOFT_IRQ 0x16
249+#define DIVIL_SOFT_RESET 0x17
250+
251+/* MFGPT */
252+#define MFGPT_IRQ 0x28
253+
254+/*
255+ * IDE STANDARD
256+ */
257+#define IDE_CAP 0x00
258+#define IDE_CONFIG 0x01
259+#define IDE_SMI 0x02
260+#define IDE_ERROR 0x03
261+#define IDE_PM 0x04
262+#define IDE_DIAG 0x05
263+
264+/*
265+ * IDE SPEC.
266+ */
267+#define IDE_IO_BAR 0x08
268+#define IDE_CFG 0x10
269+#define IDE_DTC 0x12
270+#define IDE_CAST 0x13
271+#define IDE_ETC 0x14
272+#define IDE_INTERNAL_PM 0x15
273+
274+/*
275+ * ACC STANDARD
276+ */
277+#define ACC_CAP 0x00
278+#define ACC_CONFIG 0x01
279+#define ACC_SMI 0x02
280+#define ACC_ERROR 0x03
281+#define ACC_PM 0x04
282+#define ACC_DIAG 0x05
283+
284+/*
285+ * USB STANDARD
286+ */
287+#define USB_CAP 0x00
288+#define USB_CONFIG 0x01
289+#define USB_SMI 0x02
290+#define USB_ERROR 0x03
291+#define USB_PM 0x04
292+#define USB_DIAG 0x05
293+
294+/*
295+ * USB SPEC.
296+ */
297+#define USB_OHCI 0x08
298+#define USB_EHCI 0x09
299+
300+/****************** NATIVE ***************************/
301+/* GPIO : I/O SPACE; REG : 32BITS */
302+#define GPIOL_OUT_VAL 0x00
303+#define GPIOL_OUT_EN 0x04
304+
305+#endif /* _CS5536_H */
arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h+35−0
@@ -0,0 +1,35 @@
1+/*
2+ * cs5536 mfgpt header file
3+ */
4+
5+#ifndef _CS5536_MFGPT_H
6+#define _CS5536_MFGPT_H
7+
8+#include <cs5536/cs5536.h>
9+#include <cs5536/cs5536_pci.h>
10+
11+#ifdef CONFIG_CS5536_MFGPT
12+extern void setup_mfgpt0_timer(void);
13+extern void disable_mfgpt0_counter(void);
14+extern void enable_mfgpt0_counter(void);
15+#else
16+static inline void __maybe_unused setup_mfgpt0_timer(void)
17+{
18+}
19+static inline void __maybe_unused disable_mfgpt0_counter(void)
20+{
21+}
22+static inline void __maybe_unused enable_mfgpt0_counter(void)
23+{
24+}
25+#endif
26+
27+#define MFGPT_TICK_RATE 14318000
28+#define COMPARE ((MFGPT_TICK_RATE + HZ/2) / HZ)
29+
30+#define MFGPT_BASE mfgpt_base
31+#define MFGPT0_CMP2 (MFGPT_BASE + 2)
32+#define MFGPT0_CNT (MFGPT_BASE + 4)
33+#define MFGPT0_SETUP (MFGPT_BASE + 6)
34+
35+#endif /*!_CS5536_MFGPT_H */
arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h+153−0
@@ -0,0 +1,153 @@
1+/*
2+ * the definition file of cs5536 Virtual Support Module(VSM).
3+ * pci configuration space can be accessed through the VSM, so
4+ * there is no need of the MSR read/write now, except the spec.
5+ * MSR registers which are not implemented yet.
6+ *
7+ * Copyright (C) 2007 Lemote Inc.
8+ * Author : jlliu, liujl@lemote.com
9+ */
10+
11+#ifndef _CS5536_PCI_H
12+#define _CS5536_PCI_H
13+
14+#include <linux/types.h>
15+#include <linux/pci_regs.h>
16+
17+extern void cs5536_pci_conf_write4(int function, int reg, u32 value);
18+extern u32 cs5536_pci_conf_read4(int function, int reg);
19+
20+#define CS5536_ACC_INTR 9
21+#define CS5536_IDE_INTR 14
22+#define CS5536_USB_INTR 11
23+#define CS5536_MFGPT_INTR 5
24+#define CS5536_UART1_INTR 4
25+#define CS5536_UART2_INTR 3
26+
27+/************** PCI BUS DEVICE FUNCTION ***************/
28+
29+/*
30+ * PCI bus device function
31+ */
32+#define PCI_BUS_CS5536 0
33+#define PCI_IDSEL_CS5536 14
34+
35+/********** STANDARD PCI-2.2 EXPANSION ****************/
36+
37+/*
38+ * PCI configuration space
39+ * we have to virtualize the PCI configure space head, so we should
40+ * define the necessary IDs and some others.
41+ */
42+
43+/* CONFIG of PCI VENDOR ID*/
44+#define CFG_PCI_VENDOR_ID(mod_dev_id, sys_vendor_id) \
45+ (((mod_dev_id) << 16) | (sys_vendor_id))
46+
47+/* VENDOR ID */
48+#define CS5536_VENDOR_ID 0x1022
49+
50+/* DEVICE ID */
51+#define CS5536_ISA_DEVICE_ID 0x2090
52+#define CS5536_IDE_DEVICE_ID 0x209a
53+#define CS5536_ACC_DEVICE_ID 0x2093
54+#define CS5536_OHCI_DEVICE_ID 0x2094
55+#define CS5536_EHCI_DEVICE_ID 0x2095
56+
57+/* CLASS CODE : CLASS SUB-CLASS INTERFACE */
58+#define CS5536_ISA_CLASS_CODE 0x060100
59+#define CS5536_IDE_CLASS_CODE 0x010180
60+#define CS5536_ACC_CLASS_CODE 0x040100
61+#define CS5536_OHCI_CLASS_CODE 0x0C0310
62+#define CS5536_EHCI_CLASS_CODE 0x0C0320
63+
64+/* BHLC : BIST HEADER-TYPE LATENCY-TIMER CACHE-LINE-SIZE */
65+
66+#define CFG_PCI_CACHE_LINE_SIZE(header_type, latency_timer) \
67+ ((PCI_NONE_BIST << 24) | ((header_type) << 16) \
68+ | ((latency_timer) << 8) | PCI_NORMAL_CACHE_LINE_SIZE);
69+
70+#define PCI_NONE_BIST 0x00 /* RO not implemented yet. */
71+#define PCI_BRIDGE_HEADER_TYPE 0x80 /* RO */
72+#define PCI_NORMAL_HEADER_TYPE 0x00
73+#define PCI_NORMAL_LATENCY_TIMER 0x00
74+#define PCI_NORMAL_CACHE_LINE_SIZE 0x08 /* RW */
75+
76+/* BAR */
77+#define PCI_BAR0_REG 0x10
78+#define PCI_BAR1_REG 0x14
79+#define PCI_BAR2_REG 0x18
80+#define PCI_BAR3_REG 0x1c
81+#define PCI_BAR4_REG 0x20
82+#define PCI_BAR5_REG 0x24
83+#define PCI_BAR_COUNT 6
84+#define PCI_BAR_RANGE_MASK 0xFFFFFFFF
85+
86+/* CARDBUS CIS POINTER */
87+#define PCI_CARDBUS_CIS_POINTER 0x00000000
88+
89+/* SUBSYSTEM VENDOR ID */
90+#define CS5536_SUB_VENDOR_ID CS5536_VENDOR_ID
91+
92+/* SUBSYSTEM ID */
93+#define CS5536_ISA_SUB_ID CS5536_ISA_DEVICE_ID
94+#define CS5536_IDE_SUB_ID CS5536_IDE_DEVICE_ID
95+#define CS5536_ACC_SUB_ID CS5536_ACC_DEVICE_ID
96+#define CS5536_OHCI_SUB_ID CS5536_OHCI_DEVICE_ID
97+#define CS5536_EHCI_SUB_ID CS5536_EHCI_DEVICE_ID
98+
99+/* EXPANSION ROM BAR */
100+#define PCI_EXPANSION_ROM_BAR 0x00000000
101+
102+/* CAPABILITIES POINTER */
103+#define PCI_CAPLIST_POINTER 0x00000000
104+#define PCI_CAPLIST_USB_POINTER 0x40
105+/* INTERRUPT */
106+
107+#define CFG_PCI_INTERRUPT_LINE(pin, mod_intr) \
108+ ((PCI_MAX_LATENCY << 24) | (PCI_MIN_GRANT << 16) | \
109+ ((pin) << 8) | (mod_intr))
110+
111+#define PCI_MAX_LATENCY 0x40
112+#define PCI_MIN_GRANT 0x00
113+#define PCI_DEFAULT_PIN 0x01
114+
115+/*********** EXPANSION PCI REG ************************/
116+
117+/*
118+ * ISA EXPANSION
119+ */
120+#define PCI_UART1_INT_REG 0x50
121+#define PCI_UART2_INT_REG 0x54
122+#define PCI_ISA_FIXUP_REG 0x58
123+
124+/*
125+ * IDE EXPANSION
126+ */
127+#define PCI_IDE_CFG_REG 0x40
128+#define CS5536_IDE_FLASH_SIGNATURE 0xDEADBEEF
129+#define PCI_IDE_DTC_REG 0x48
130+#define PCI_IDE_CAST_REG 0x4C
131+#define PCI_IDE_ETC_REG 0x50
132+#define PCI_IDE_PM_REG 0x54
133+#define PCI_IDE_INT_REG 0x60
134+
135+/*
136+ * ACC EXPANSION
137+ */
138+#define PCI_ACC_INT_REG 0x50
139+
140+/*
141+ * OHCI EXPANSION : INTTERUPT IS IMPLEMENTED BY THE OHCI
142+ */
143+#define PCI_OHCI_PM_REG 0x40
144+#define PCI_OHCI_INT_REG 0x50
145+
146+/*
147+ * EHCI EXPANSION
148+ */
149+#define PCI_EHCI_LEGSMIEN_REG 0x50
150+#define PCI_EHCI_LEGSMISTS_REG 0x54
151+#define PCI_EHCI_FLADJ_REG 0x60
152+
153+#endif /* _CS5536_PCI_H_ */
arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h+31−0
@@ -0,0 +1,31 @@
1+/*
2+ * the read/write interfaces for Virtual Support Module(VSM)
3+ *
4+ * Copyright (C) 2009 Lemote, Inc.
5+ * Author: Wu Zhangjin <wuzj@lemote.com>
6+ */
7+
8+#ifndef _CS5536_VSM_H
9+#define _CS5536_VSM_H
10+
11+#include <linux/types.h>
12+
13+typedef void (*cs5536_pci_vsm_write)(int reg, u32 value);
14+typedef u32 (*cs5536_pci_vsm_read)(int reg);
15+
16+#define DECLARE_CS5536_MODULE(name) \
17+extern void pci_##name##_write_reg(int reg, u32 value); \
18+extern u32 pci_##name##_read_reg(int reg);
19+
20+/* ide module */
21+DECLARE_CS5536_MODULE(ide)
22+/* acc module */
23+DECLARE_CS5536_MODULE(acc)
24+/* ohci module */
25+DECLARE_CS5536_MODULE(ohci)
26+/* isa module */
27+DECLARE_CS5536_MODULE(isa)
28+/* ehci module */
29+DECLARE_CS5536_MODULE(ehci)
30+
31+#endif /* _CS5536_VSM_H */
arch/mips/include/asm/mach-loongson/dma-coherence.h+4−0
@@ -28,7 +28,11 @@ static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, · 27 unmodified lines
2828 static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
2929 dma_addr_t dma_addr)
3030 {
31+#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT)
32+ return (dma_addr > 0x8fffffff) ? dma_addr : (dma_addr & 0x0fffffff);
33+#else
3134 return dma_addr & 0x7fffffff;
35+#endif
3236 }
3337
3438 static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
arch/mips/include/asm/mach-loongson/loongson.h+275−15
@@ -1,5 +1,5 @@
11 /*
2− * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology
2+ * Copyright (C) 2009 Lemote, Inc.
33 * Author: Wu Zhangjin <wuzj@lemote.com>
44 *
55 * This program is free software; you can redistribute it and/or modify it
@@ -15,9 +15,6 @@ · 9 unmodified lines
1515 #include <linux/io.h>
1616 #include <linux/init.h>
1717
18−/* there is an internal bonito64-compatiable northbridge in loongson2e/2f */
19−#include <asm/mips-boards/bonito64.h>
20−
2118 /* loongson internal northbridge initialization */
2219 extern void bonito_irq_init(void);
2320
@@ -32,7 +29,19 @@ extern unsigned long memsize, highmemsize; · 8 unmodified lines
3229 /* loongson-specific command line, env and memory initialization */
3330 extern void __init prom_init_memory(void);
3431 extern void __init prom_init_cmdline(void);
32+extern void __init prom_init_machtype(void);
3533 extern void __init prom_init_env(void);
34+#ifdef CONFIG_LOONGSON_UART_BASE
35+extern unsigned long _loongson_uart_base, loongson_uart_base;
36+extern void prom_init_loongson_uart_base(void);
37+#endif
38+
39+static inline void prom_init_uart_base(void)
40+{
41+#ifdef CONFIG_LOONGSON_UART_BASE
42+ prom_init_loongson_uart_base();
43+#endif
44+}
3645
3746 /* irq operation functions */
3847 extern void bonito_irqdispatch(void);
@@ -40,25 +49,276 @@ extern void __init bonito_irq_init(void); · 1 unmodified line
4049 extern void __init set_irq_trigger_mode(void);
4150 extern void __init mach_init_irq(void);
4251 extern void mach_irq_dispatch(unsigned int pending);
52+extern int mach_i8259_irq(void);
53+
54+/* We need this in some places... */
55+#define delay() ({ \
56+ int x; \
57+ for (x = 0; x < 100000; x++) \
58+ __asm__ __volatile__(""); \
59+})
60+
61+#define LOONGSON_REG(x) \
62+ (*(volatile u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x)))
63+
64+#define LOONGSON_IRQ_BASE 32
65+#define LOONGSON2_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */
66+
67+#define LOONGSON_FLASH_BASE 0x1c000000
68+#define LOONGSON_FLASH_SIZE 0x02000000 /* 32M */
69+#define LOONGSON_FLASH_TOP (LOONGSON_FLASH_BASE+LOONGSON_FLASH_SIZE-1)
70+
71+#define LOONGSON_LIO0_BASE 0x1e000000
72+#define LOONGSON_LIO0_SIZE 0x01C00000 /* 28M */
73+#define LOONGSON_LIO0_TOP (LOONGSON_LIO0_BASE+LOONGSON_LIO0_SIZE-1)
74+
75+#define LOONGSON_BOOT_BASE 0x1fc00000
76+#define LOONGSON_BOOT_SIZE 0x00100000 /* 1M */
77+#define LOONGSON_BOOT_TOP (LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1)
78+#define LOONGSON_REG_BASE 0x1fe00000
79+#define LOONGSON_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */
80+#define LOONGSON_REG_TOP (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1)
81+
82+#define LOONGSON_LIO1_BASE 0x1ff00000
83+#define LOONGSON_LIO1_SIZE 0x00100000 /* 1M */
84+#define LOONGSON_LIO1_TOP (LOONGSON_LIO1_BASE+LOONGSON_LIO1_SIZE-1)
85+
86+#define LOONGSON_PCILO0_BASE 0x10000000
87+#define LOONGSON_PCILO1_BASE 0x14000000
88+#define LOONGSON_PCILO2_BASE 0x18000000
89+#define LOONGSON_PCILO_BASE LOONGSON_PCILO0_BASE
90+#define LOONGSON_PCILO_SIZE 0x0c000000 /* 64M * 3 */
91+#define LOONGSON_PCILO_TOP (LOONGSON_PCILO0_BASE+LOONGSON_PCILO_SIZE-1)
92+
93+#define LOONGSON_PCICFG_BASE 0x1fe80000
94+#define LOONGSON_PCICFG_SIZE 0x00000800 /* 2K */
95+#define LOONGSON_PCICFG_TOP (LOONGSON_PCICFG_BASE+LOONGSON_PCICFG_SIZE-1)
96+#define LOONGSON_PCIIO_BASE 0x1fd00000
97+#define LOONGSON_PCIIO_SIZE 0x00100000 /* 1M */
98+#define LOONGSON_PCIIO_TOP (LOONGSON_PCIIO_BASE+LOONGSON_PCIIO_SIZE-1)
99+
100+/* Loongson Register Bases */
101+
102+#define LOONGSON_PCICONFIGBASE 0x00
103+#define LOONGSON_REGBASE 0x100
43104
44105 /* PCI Configuration Registers */
45−#define LOONGSON_PCI_ISR4C BONITO_PCI_REG(0x4c)
106+
107+#define LOONGSON_PCI_REG(x) LOONGSON_REG(LOONGSON_PCICONFIGBASE + (x))
108+#define LOONGSON_PCIDID LOONGSON_PCI_REG(0x00)
109+#define LOONGSON_PCICMD LOONGSON_PCI_REG(0x04)
110+#define LOONGSON_PCICLASS LOONGSON_PCI_REG(0x08)
111+#define LOONGSON_PCILTIMER LOONGSON_PCI_REG(0x0c)
112+#define LOONGSON_PCIBASE0 LOONGSON_PCI_REG(0x10)
113+#define LOONGSON_PCIBASE1 LOONGSON_PCI_REG(0x14)
114+#define LOONGSON_PCIBASE2 LOONGSON_PCI_REG(0x18)
115+#define LOONGSON_PCIBASE3 LOONGSON_PCI_REG(0x1c)
116+#define LOONGSON_PCIBASE4 LOONGSON_PCI_REG(0x20)
117+#define LOONGSON_PCIEXPRBASE LOONGSON_PCI_REG(0x30)
118+#define LOONGSON_PCIINT LOONGSON_PCI_REG(0x3c)
119+
120+#define LOONGSON_PCI_ISR4C LOONGSON_PCI_REG(0x4c)
121+
122+#define LOONGSON_PCICMD_PERR_CLR 0x80000000
123+#define LOONGSON_PCICMD_SERR_CLR 0x40000000
124+#define LOONGSON_PCICMD_MABORT_CLR 0x20000000
125+#define LOONGSON_PCICMD_MTABORT_CLR 0x10000000
126+#define LOONGSON_PCICMD_TABORT_CLR 0x08000000
127+#define LOONGSON_PCICMD_MPERR_CLR 0x01000000
128+#define LOONGSON_PCICMD_PERRRESPEN 0x00000040
129+#define LOONGSON_PCICMD_ASTEPEN 0x00000080
130+#define LOONGSON_PCICMD_SERREN 0x00000100
131+#define LOONGSON_PCILTIMER_BUSLATENCY 0x0000ff00
132+#define LOONGSON_PCILTIMER_BUSLATENCY_SHIFT 8
133+
134+/* Loongson h/w Configuration */
135+
136+#define LOONGSON_GENCFG_OFFSET 0x4
137+#define LOONGSON_GENCFG LOONGSON_REG(LOONGSON_REGBASE + LOONGSON_GENCFG_OFFSET)
138+
139+#define LOONGSON_GENCFG_DEBUGMODE 0x00000001
140+#define LOONGSON_GENCFG_SNOOPEN 0x00000002
141+#define LOONGSON_GENCFG_CPUSELFRESET 0x00000004
142+
143+#define LOONGSON_GENCFG_FORCE_IRQA 0x00000008
144+#define LOONGSON_GENCFG_IRQA_ISOUT 0x00000010
145+#define LOONGSON_GENCFG_IRQA_FROM_INT1 0x00000020
146+#define LOONGSON_GENCFG_BYTESWAP 0x00000040
147+
148+#define LOONGSON_GENCFG_UNCACHED 0x00000080
149+#define LOONGSON_GENCFG_PREFETCHEN 0x00000100
150+#define LOONGSON_GENCFG_WBEHINDEN 0x00000200
151+#define LOONGSON_GENCFG_CACHEALG 0x00000c00
152+#define LOONGSON_GENCFG_CACHEALG_SHIFT 10
153+#define LOONGSON_GENCFG_PCIQUEUE 0x00001000
154+#define LOONGSON_GENCFG_CACHESTOP 0x00002000
155+#define LOONGSON_GENCFG_MSTRBYTESWAP 0x00004000
156+#define LOONGSON_GENCFG_BUSERREN 0x00008000
157+#define LOONGSON_GENCFG_NORETRYTIMEOUT 0x00010000
158+#define LOONGSON_GENCFG_SHORTCOPYTIMEOUT 0x00020000
159+
160+/* PCI address map control */
161+
162+#define LOONGSON_PCIMAP LOONGSON_REG(LOONGSON_REGBASE + 0x10)
163+#define LOONGSON_PCIMEMBASECFG LOONGSON_REG(LOONGSON_REGBASE + 0x14)
164+#define LOONGSON_PCIMAP_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x18)
165+
166+/* GPIO Regs - r/w */
167+
168+#define LOONGSON_GPIODATA LOONGSON_REG(LOONGSON_REGBASE + 0x1c)
169+#define LOONGSON_GPIOIE LOONGSON_REG(LOONGSON_REGBASE + 0x20)
170+
171+/* ICU Configuration Regs - r/w */
172+
173+#define LOONGSON_INTEDGE LOONGSON_REG(LOONGSON_REGBASE + 0x24)
174+#define LOONGSON_INTSTEER LOONGSON_REG(LOONGSON_REGBASE + 0x28)
175+#define LOONGSON_INTPOL LOONGSON_REG(LOONGSON_REGBASE + 0x2c)
176+
177+/* ICU Enable Regs - IntEn & IntISR are r/o. */
178+
179+#define LOONGSON_INTENSET LOONGSON_REG(LOONGSON_REGBASE + 0x30)
180+#define LOONGSON_INTENCLR LOONGSON_REG(LOONGSON_REGBASE + 0x34)
181+#define LOONGSON_INTEN LOONGSON_REG(LOONGSON_REGBASE + 0x38)
182+#define LOONGSON_INTISR LOONGSON_REG(LOONGSON_REGBASE + 0x3c)
183+
184+/* ICU */
185+#define LOONGSON_ICU_MBOXES 0x0000000f
186+#define LOONGSON_ICU_MBOXES_SHIFT 0
187+#define LOONGSON_ICU_DMARDY 0x00000010
188+#define LOONGSON_ICU_DMAEMPTY 0x00000020
189+#define LOONGSON_ICU_COPYRDY 0x00000040
190+#define LOONGSON_ICU_COPYEMPTY 0x00000080
191+#define LOONGSON_ICU_COPYERR 0x00000100
192+#define LOONGSON_ICU_PCIIRQ 0x00000200
193+#define LOONGSON_ICU_MASTERERR 0x00000400
194+#define LOONGSON_ICU_SYSTEMERR 0x00000800
195+#define LOONGSON_ICU_DRAMPERR 0x00001000
196+#define LOONGSON_ICU_RETRYERR 0x00002000
197+#define LOONGSON_ICU_GPIOS 0x01ff0000
198+#define LOONGSON_ICU_GPIOS_SHIFT 16
199+#define LOONGSON_ICU_GPINS 0x7e000000
200+#define LOONGSON_ICU_GPINS_SHIFT 25
201+#define LOONGSON_ICU_MBOX(N) (1<<(LOONGSON_ICU_MBOXES_SHIFT+(N)))
202+#define LOONGSON_ICU_GPIO(N) (1<<(LOONGSON_ICU_GPIOS_SHIFT+(N)))
203+#define LOONGSON_ICU_GPIN(N) (1<<(LOONGSON_ICU_GPINS_SHIFT+(N)))
204+
205+/* PCI prefetch window base & mask */
206+
207+#define LOONGSON_MEM_WIN_BASE_L LOONGSON_REG(LOONGSON_REGBASE + 0x40)
208+#define LOONGSON_MEM_WIN_BASE_H LOONGSON_REG(LOONGSON_REGBASE + 0x44)
209+#define LOONGSON_MEM_WIN_MASK_L LOONGSON_REG(LOONGSON_REGBASE + 0x48)
210+#define LOONGSON_MEM_WIN_MASK_H LOONGSON_REG(LOONGSON_REGBASE + 0x4c)
46211
47212 /* PCI_Hit*_Sel_* */
48213
49−#define LOONGSON_PCI_HIT0_SEL_L BONITO(BONITO_REGBASE + 0x50)
50−#define LOONGSON_PCI_HIT0_SEL_H BONITO(BONITO_REGBASE + 0x54)
51−#define LOONGSON_PCI_HIT1_SEL_L BONITO(BONITO_REGBASE + 0x58)
52−#define LOONGSON_PCI_HIT1_SEL_H BONITO(BONITO_REGBASE + 0x5c)
53−#define LOONGSON_PCI_HIT2_SEL_L BONITO(BONITO_REGBASE + 0x60)
54−#define LOONGSON_PCI_HIT2_SEL_H BONITO(BONITO_REGBASE + 0x64)
214+#define LOONGSON_PCI_HIT0_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x50)
215+#define LOONGSON_PCI_HIT0_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x54)
216+#define LOONGSON_PCI_HIT1_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x58)
217+#define LOONGSON_PCI_HIT1_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x5c)
218+#define LOONGSON_PCI_HIT2_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x60)
219+#define LOONGSON_PCI_HIT2_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x64)
55220
56221 /* PXArb Config & Status */
57222
58−#define LOONGSON_PXARB_CFG BONITO(BONITO_REGBASE + 0x68)
59−#define LOONGSON_PXARB_STATUS BONITO(BONITO_REGBASE + 0x6c)
223+#define LOONGSON_PXARB_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x68)
224+#define LOONGSON_PXARB_STATUS LOONGSON_REG(LOONGSON_REGBASE + 0x6c)
225+
226+/* pcimap */
227+
228+#define LOONGSON_PCIMAP_PCIMAP_LO0 0x0000003f
229+#define LOONGSON_PCIMAP_PCIMAP_LO0_SHIFT 0
230+#define LOONGSON_PCIMAP_PCIMAP_LO1 0x00000fc0
231+#define LOONGSON_PCIMAP_PCIMAP_LO1_SHIFT 6
232+#define LOONGSON_PCIMAP_PCIMAP_LO2 0x0003f000
233+#define LOONGSON_PCIMAP_PCIMAP_LO2_SHIFT 12
234+#define LOONGSON_PCIMAP_PCIMAP_2 0x00040000
235+#define LOONGSON_PCIMAP_WIN(WIN, ADDR) \
236+ ((((ADDR)>>26) & LOONGSON_PCIMAP_PCIMAP_LO0) << ((WIN)*6))
237+
238+#ifdef CONFIG_CPU_SUPPORTS_CPUFREQ
239+#include <linux/cpufreq.h>
240+extern void loongson2_cpu_wait(void);
241+extern struct cpufreq_frequency_table loongson2_clockmod_table[];
242+
243+/* Chip Config */
244+#define LOONGSON_CHIPCFG0 LOONGSON_REG(LOONGSON_REGBASE + 0x80)
245+#endif
246+
247+/*
248+ * address windows configuration module
249+ *
250+ * loongson2e do not have this module
251+ */
252+#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
253+
254+/* address window config module base address */
255+#define LOONGSON_ADDRWINCFG_BASE 0x3ff00000ul
256+#define LOONGSON_ADDRWINCFG_SIZE 0x180
257+
258+extern unsigned long _loongson_addrwincfg_base;
259+#define LOONGSON_ADDRWINCFG(offset) \
260+ (*(volatile u64 *)(_loongson_addrwincfg_base + (offset)))
261+
262+#define CPU_WIN0_BASE LOONGSON_ADDRWINCFG(0x00)
263+#define CPU_WIN1_BASE LOONGSON_ADDRWINCFG(0x08)
264+#define CPU_WIN2_BASE LOONGSON_ADDRWINCFG(0x10)
265+#define CPU_WIN3_BASE LOONGSON_ADDRWINCFG(0x18)
266+
267+#define CPU_WIN0_MASK LOONGSON_ADDRWINCFG(0x20)
268+#define CPU_WIN1_MASK LOONGSON_ADDRWINCFG(0x28)
269+#define CPU_WIN2_MASK LOONGSON_ADDRWINCFG(0x30)
270+#define CPU_WIN3_MASK LOONGSON_ADDRWINCFG(0x38)
271+
272+#define CPU_WIN0_MMAP LOONGSON_ADDRWINCFG(0x40)
273+#define CPU_WIN1_MMAP LOONGSON_ADDRWINCFG(0x48)
274+#define CPU_WIN2_MMAP LOONGSON_ADDRWINCFG(0x50)
275+#define CPU_WIN3_MMAP LOONGSON_ADDRWINCFG(0x58)
276+
277+#define PCIDMA_WIN0_BASE LOONGSON_ADDRWINCFG(0x60)
278+#define PCIDMA_WIN1_BASE LOONGSON_ADDRWINCFG(0x68)
279+#define PCIDMA_WIN2_BASE LOONGSON_ADDRWINCFG(0x70)
280+#define PCIDMA_WIN3_BASE LOONGSON_ADDRWINCFG(0x78)
281+
282+#define PCIDMA_WIN0_MASK LOONGSON_ADDRWINCFG(0x80)
283+#define PCIDMA_WIN1_MASK LOONGSON_ADDRWINCFG(0x88)
284+#define PCIDMA_WIN2_MASK LOONGSON_ADDRWINCFG(0x90)
285+#define PCIDMA_WIN3_MASK LOONGSON_ADDRWINCFG(0x98)
286+
287+#define PCIDMA_WIN0_MMAP LOONGSON_ADDRWINCFG(0xa0)
288+#define PCIDMA_WIN1_MMAP LOONGSON_ADDRWINCFG(0xa8)
289+#define PCIDMA_WIN2_MMAP LOONGSON_ADDRWINCFG(0xb0)
290+#define PCIDMA_WIN3_MMAP LOONGSON_ADDRWINCFG(0xb8)
291+
292+#define ADDRWIN_WIN0 0
293+#define ADDRWIN_WIN1 1
294+#define ADDRWIN_WIN2 2
295+#define ADDRWIN_WIN3 3
296+
297+#define ADDRWIN_MAP_DST_DDR 0
298+#define ADDRWIN_MAP_DST_PCI 1
299+#define ADDRWIN_MAP_DST_LIO 1
300+
301+/*
302+ * s: CPU, PCIDMA
303+ * d: DDR, PCI, LIO
304+ * win: 0, 1, 2, 3
305+ * src: map source
306+ * dst: map destination
307+ * size: ~mask + 1
308+ */
309+#define LOONGSON_ADDRWIN_CFG(s, d, w, src, dst, size) do {\
310+ s##_WIN##w##_BASE = (src); \
311+ s##_WIN##w##_MMAP = (src) | ADDRWIN_MAP_DST_##d; \
312+ s##_WIN##w##_MASK = ~(size-1); \
313+} while (0)
314+
315+#define LOONGSON_ADDRWIN_CPUTOPCI(win, src, dst, size) \
316+ LOONGSON_ADDRWIN_CFG(CPU, PCI, win, src, dst, size)
317+#define LOONGSON_ADDRWIN_CPUTODDR(win, src, dst, size) \
318+ LOONGSON_ADDRWIN_CFG(CPU, DDR, win, src, dst, size)
319+#define LOONGSON_ADDRWIN_PCITODDR(win, src, dst, size) \
320+ LOONGSON_ADDRWIN_CFG(PCIDMA, DDR, win, src, dst, size)
60321
61−/* loongson2-specific perf counter IRQ */
62−#define LOONGSON2_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6)
322+#endif /* ! CONFIG_CPU_SUPPORTS_ADDRWINCFG */
63323
64324 #endif /* __ASM_MACH_LOONGSON_LOONGSON_H */
arch/mips/include/asm/mach-loongson/machine.h+7−2
@@ -13,10 +13,15 @@ · 12 unmodified lines
1313
1414 #ifdef CONFIG_LEMOTE_FULOONG2E
1515
16−#define LOONGSON_UART_BASE (BONITO_PCIIO_BASE + 0x3f8)
17−
1816 #define LOONGSON_MACHTYPE MACH_LEMOTE_FL2E
1917
2018 #endif
2119
20+/* use fuloong2f as the default machine of LEMOTE_MACH2F */
21+#ifdef CONFIG_LEMOTE_MACH2F
22+
23+#define LOONGSON_MACHTYPE MACH_LEMOTE_FL2F
24+
25+#endif
26+
2227 #endif /* __ASM_MACH_LOONGSON_MACHINE_H */
arch/mips/include/asm/mach-loongson/mem.h+19−8
@@ -1,5 +1,5 @@
11 /*
2− * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology
2+ * Copyright (C) 2009 Lemote, Inc.
33 * Author: Wu Zhangjin <wuzj@lemote.com>
44 *
55 * This program is free software; you can redistribute it and/or modify it
@@ -12,19 +12,30 @@ · 6 unmodified lines
1212 #define __ASM_MACH_LOONGSON_MEM_H
1313
1414 /*
15− * On Lemote Loongson 2e
15+ * high memory space
1616 *
17− * the high memory space starts from 512M.
18− * the peripheral registers reside between 0x1000:0000 and 0x2000:0000.
17+ * in loongson2e, starts from 512M
18+ * in loongson2f, starts from 2G 256M
1919 */
20+#ifdef CONFIG_CPU_LOONGSON2E
21+#define LOONGSON_HIGHMEM_START 0x20000000
22+#else
23+#define LOONGSON_HIGHMEM_START 0x90000000
24+#endif
2025
21−#ifdef CONFIG_LEMOTE_FULOONG2E
22−
23−#define LOONGSON_HIGHMEM_START 0x20000000
26+/*
27+ * the peripheral registers(MMIO):
28+ *
29+ * On the Lemote Loongson 2e system, reside between 0x1000:0000 and 0x2000:0000.
30+ * On the Lemote Loongson 2f system, reside between 0x1000:0000 and 0x8000:0000.
31+ */
2432
2533 #define LOONGSON_MMIO_MEM_START 0x10000000
26−#define LOONGSON_MMIO_MEM_END 0x20000000
2734
35+#ifdef CONFIG_CPU_LOONGSON2E
36+#define LOONGSON_MMIO_MEM_END 0x20000000
37+#else
38+#define LOONGSON_MMIO_MEM_END 0x80000000
2839 #endif
2940
3041 #endif /* __ASM_MACH_LOONGSON_MEM_H */
arch/mips/include/asm/mach-loongson/pci.h+29−5
@@ -1,5 +1,6 @@
11 /*
22 * Copyright (c) 2008 Zhang Le <r0bertz@gentoo.org>
3+ * Copyright (c) 2009 Wu Zhangjin <wuzj@lemote.com>
34 *
45 * This program is free software; you can redistribute it
56 * and/or modify it under the terms of the GNU General
@@ -22,16 +23,39 @@ · 16 unmodified lines
2223 #ifndef __ASM_MACH_LOONGSON_PCI_H_
2324 #define __ASM_MACH_LOONGSON_PCI_H_
2425
25−extern struct pci_ops bonito64_pci_ops;
26+extern struct pci_ops loongson_pci_ops;
2627
27−#ifdef CONFIG_LEMOTE_FULOONG2E
28+/* this is an offset from mips_io_port_base */
29+#define LOONGSON_PCI_IO_START 0x00004000UL
30+
31+#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
32+
33+/*
34+ * we use address window2 to map cpu address space to pci space
35+ * window2: cpu [1G, 2G] -> pci [1G, 2G]
36+ * why not use window 0 & 1? because they are used by cpu when booting.
37+ * window0: cpu [0, 256M] -> ddr [0, 256M]
38+ * window1: cpu [256M, 512M] -> pci [256M, 512M]
39+ */
40+
41+/* the smallest LOONGSON_CPU_MEM_SRC can be 512M */
42+#define LOONGSON_CPU_MEM_SRC 0x40000000ul /* 1G */
43+#define LOONGSON_PCI_MEM_DST LOONGSON_CPU_MEM_SRC
44+
45+#define LOONGSON_PCI_MEM_START LOONGSON_PCI_MEM_DST
46+#define LOONGSON_PCI_MEM_END (0x80000000ul-1) /* 2G */
47+
48+#define MMAP_CPUTOPCI_SIZE (LOONGSON_PCI_MEM_END - \
49+ LOONGSON_PCI_MEM_START + 1)
50+
51+#else /* loongson2f/32bit & loongson2e */
2852
2953 /* this pci memory space is mapped by pcimap in pci.c */
30−#define LOONGSON_PCI_MEM_START BONITO_PCILO1_BASE
31−#define LOONGSON_PCI_MEM_END (BONITO_PCILO1_BASE + 0x04000000 * 2)
54+#define LOONGSON_PCI_MEM_START LOONGSON_PCILO1_BASE
55+#define LOONGSON_PCI_MEM_END (LOONGSON_PCILO1_BASE + 0x04000000 * 2)
3256 /* this is an offset from mips_io_port_base */
3357 #define LOONGSON_PCI_IO_START 0x00004000UL
3458
35−#endif
59+#endif /* !CONFIG_CPU_SUPPORTS_ADDRWINCFG */
3660
3761 #endif /* !__ASM_MACH_LOONGSON_PCI_H_ */
arch/mips/include/asm/mach-powertv/asic.h+107−0
@@ -0,0 +1,107 @@
1+/*
2+ * Copyright (C) 2009 Cisco Systems, Inc.
3+ *
4+ * This program is free software; you can redistribute it and/or modify
5+ * it under the terms of the GNU General Public License as published by
6+ * the Free Software Foundation; either version 2 of the License, or
7+ * (at your option) any later version.
8+ *
9+ * This program is distributed in the hope that it will be useful,
10+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
11+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12+ * GNU General Public License for more details.
13+ *
14+ * You should have received a copy of the GNU General Public License
15+ * along with this program; if not, write to the Free Software
16+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17+ */
18+
19+#ifndef _ASM_MACH_POWERTV_ASIC_H
20+#define _ASM_MACH_POWERTV_ASIC_H
21+
22+#include <linux/ioport.h>
23+#include <asm/mach-powertv/asic_regs.h>
24+
25+#define DVR_CAPABLE (1<<0)
26+#define PCIE_CAPABLE (1<<1)
27+#define FFS_CAPABLE (1<<2)
28+#define DISPLAY_CAPABLE (1<<3)
29+
30+/* Platform Family types
31+ * For compitability, the new value must be added in the end */
32+enum family_type {
33+ FAMILY_8500,
34+ FAMILY_8500RNG,
35+ FAMILY_4500,
36+ FAMILY_1500,
37+ FAMILY_8600,
38+ FAMILY_4600,
39+ FAMILY_4600VZA,
40+ FAMILY_8600VZB,
41+ FAMILY_1500VZE,
42+ FAMILY_1500VZF,
43+ FAMILIES
44+};
45+
46+/* Register maps for each ASIC */
47+extern const struct register_map calliope_register_map;
48+extern const struct register_map cronus_register_map;
49+extern const struct register_map zeus_register_map;
50+
51+extern struct resource dvr_cronus_resources[];
52+extern struct resource dvr_zeus_resources[];
53+extern struct resource non_dvr_calliope_resources[];
54+extern struct resource non_dvr_cronus_resources[];
55+extern struct resource non_dvr_cronuslite_resources[];
56+extern struct resource non_dvr_vz_calliope_resources[];
57+extern struct resource non_dvr_vze_calliope_resources[];
58+extern struct resource non_dvr_vzf_calliope_resources[];
59+extern struct resource non_dvr_zeus_resources[];
60+
61+extern void powertv_platform_init(void);
62+extern void platform_alloc_bootmem(void);
63+extern enum asic_type platform_get_asic(void);
64+extern enum family_type platform_get_family(void);
65+extern int platform_supports_dvr(void);
66+extern int platform_supports_ffs(void);
67+extern int platform_supports_pcie(void);
68+extern int platform_supports_display(void);
69+extern void configure_platform(void);
70+extern void platform_configure_usb_ehci(void);
71+extern void platform_unconfigure_usb_ehci(void);
72+extern void platform_configure_usb_ohci(void);
73+extern void platform_unconfigure_usb_ohci(void);
74+
75+/* Platform Resources */
76+#define ASIC_RESOURCE_GET_EXISTS 1
77+extern struct resource *asic_resource_get(const char *name);
78+extern void platform_release_memory(void *baddr, int size);
79+
80+/* Reboot Cause */
81+extern void set_reboot_cause(char code, unsigned int data, unsigned int data2);
82+extern void set_locked_reboot_cause(char code, unsigned int data,
83+ unsigned int data2);
84+
85+enum sys_reboot_type {
86+ sys_unknown_reboot = 0x00, /* Unknown reboot cause */
87+ sys_davic_change = 0x01, /* Reboot due to change in DAVIC
88+ * mode */
89+ sys_user_reboot = 0x02, /* Reboot initiated by user */
90+ sys_system_reboot = 0x03, /* Reboot initiated by OS */
91+ sys_trap_reboot = 0x04, /* Reboot due to a CPU trap */
92+ sys_silent_reboot = 0x05, /* Silent reboot */
93+ sys_boot_ldr_reboot = 0x06, /* Bootloader reboot */
94+ sys_power_up_reboot = 0x07, /* Power on bootup. Older
95+ * drivers may report as
96+ * userReboot. */
97+ sys_code_change = 0x08, /* Reboot to take code change.
98+ * Older drivers may report as
99+ * userReboot. */
100+ sys_hardware_reset = 0x09, /* HW watchdog or front-panel
101+ * reset button reset. Older
102+ * drivers may report as
103+ * userReboot. */
104+ sys_watchdogInterrupt = 0x0A /* Pre-watchdog interrupt */
105+};
106+
107+#endif /* _ASM_MACH_POWERTV_ASIC_H */
arch/mips/include/asm/mach-powertv/asic_regs.h+155−0
@@ -0,0 +1,155 @@
1+/*
2+ * Copyright (C) 2009 Cisco Systems, Inc.
3+ *
4+ * This program is free software; you can redistribute it and/or modify
5+ * it under the terms of the GNU General Public License as published by
6+ * the Free Software Foundation; either version 2 of the License, or
7+ * (at your option) any later version.
8+ *
9+ * This program is distributed in the hope that it will be useful,
10+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
11+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12+ * GNU General Public License for more details.
13+ *
14+ * You should have received a copy of the GNU General Public License
15+ * along with this program; if not, write to the Free Software
16+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17+ */
18+
19+#ifndef __ASM_MACH_POWERTV_ASIC_H_
20+#define __ASM_MACH_POWERTV_ASIC_H_
21+#include <linux/io.h>
22+
23+/* ASIC types */
24+enum asic_type {
25+ ASIC_UNKNOWN,
26+ ASIC_ZEUS,
27+ ASIC_CALLIOPE,
28+ ASIC_CRONUS,
29+ ASIC_CRONUSLITE,
30+ ASICS
31+};
32+
33+/* hardcoded values read from Chip Version registers */
34+#define CRONUS_10 0x0B4C1C20
35+#define CRONUS_11 0x0B4C1C21
36+#define CRONUSLITE_10 0x0B4C1C40
37+
38+#define NAND_FLASH_BASE 0x03000000
39+#define ZEUS_IO_BASE 0x09000000
40+#define CALLIOPE_IO_BASE 0x08000000
41+#define CRONUS_IO_BASE 0x09000000
42+#define ASIC_IO_SIZE 0x01000000
43+
44+/* Definitions for backward compatibility */
45+#define UART1_INTSTAT uart1_intstat
46+#define UART1_INTEN uart1_inten
47+#define UART1_CONFIG1 uart1_config1
48+#define UART1_CONFIG2 uart1_config2
49+#define UART1_DIVISORHI uart1_divisorhi
50+#define UART1_DIVISORLO uart1_divisorlo
51+#define UART1_DATA uart1_data
52+#define UART1_STATUS uart1_status
53+
54+/* ASIC register enumeration */
55+struct register_map {
56+ u32 eic_slow0_strt_add;
57+ u32 eic_cfg_bits;
58+ u32 eic_ready_status;
59+
60+ u32 chipver3;
61+ u32 chipver2;
62+ u32 chipver1;
63+ u32 chipver0;
64+
65+ u32 uart1_intstat;
66+ u32 uart1_inten;
67+ u32 uart1_config1;
68+ u32 uart1_config2;
69+ u32 uart1_divisorhi;
70+ u32 uart1_divisorlo;
71+ u32 uart1_data;
72+ u32 uart1_status;
73+
74+ u32 int_stat_3;
75+ u32 int_stat_2;
76+ u32 int_stat_1;
77+ u32 int_stat_0;
78+ u32 int_config;
79+ u32 int_int_scan;
80+ u32 ien_int_3;
81+ u32 ien_int_2;
82+ u32 ien_int_1;
83+ u32 ien_int_0;
84+ u32 int_level_3_3;
85+ u32 int_level_3_2;
86+ u32 int_level_3_1;
87+ u32 int_level_3_0;
88+ u32 int_level_2_3;
89+ u32 int_level_2_2;
90+ u32 int_level_2_1;
91+ u32 int_level_2_0;
92+ u32 int_level_1_3;
93+ u32 int_level_1_2;
94+ u32 int_level_1_1;
95+ u32 int_level_1_0;
96+ u32 int_level_0_3;
97+ u32 int_level_0_2;
98+ u32 int_level_0_1;
99+ u32 int_level_0_0;
100+ u32 int_docsis_en;
101+
102+ u32 mips_pll_setup;
103+ u32 usb_fs;
104+ u32 test_bus;
105+ u32 crt_spare;
106+ u32 usb2_ohci_int_mask;
107+ u32 usb2_strap;
108+ u32 ehci_hcapbase;
109+ u32 ohci_hc_revision;
110+ u32 bcm1_bs_lmi_steer;
111+ u32 usb2_control;
112+ u32 usb2_stbus_obc;
113+ u32 usb2_stbus_mess_size;
114+ u32 usb2_stbus_chunk_size;
115+
116+ u32 pcie_regs;
117+ u32 tim_ch;
118+ u32 tim_cl;
119+ u32 gpio_dout;
120+ u32 gpio_din;
121+ u32 gpio_dir;
122+ u32 watchdog;
123+ u32 front_panel;
124+
125+ u32 register_maps;
126+};
127+
128+extern enum asic_type asic;
129+extern const struct register_map *register_map;
130+extern unsigned long asic_phy_base; /* Physical address of ASIC */
131+extern unsigned long asic_base; /* Virtual address of ASIC */
132+
133+/*
134+ * Macros to interface to registers through their ioremapped address
135+ * asic_reg_offset Returns the offset of a given register from the start
136+ * of the ASIC address space
137+ * asic_reg_phys_addr Returns the physical address of the given register
138+ * asic_reg_addr Returns the iomapped virtual address of the given
139+ * register.
140+ */
141+#define asic_reg_offset(x) (register_map->x)
142+#define asic_reg_phys_addr(x) (asic_phy_base + asic_reg_offset(x))
143+#define asic_reg_addr(x) \
144+ ((unsigned int *) (asic_base + asic_reg_offset(x)))
145+
146+/*
147+ * The asic_reg macro is gone. It should be replaced by either asic_read or
148+ * asic_write, as appropriate.
149+ */
150+
151+#define asic_read(x) readl(asic_reg_addr(x))
152+#define asic_write(v, x) writel(v, asic_reg_addr(x))
153+
154+extern void asic_irq_init(void);
155+#endif
arch/mips/include/asm/mach-powertv/dma-coherence.h+119−0
@@ -0,0 +1,119 @@
1+/*
2+ * This file is subject to the terms and conditions of the GNU General Public
3+ * License. See the file "COPYING" in the main directory of this archive
4+ * for more details.
5+ *
6+ * Version from mach-generic modified to support PowerTV port
7+ * Portions Copyright (C) 2009 Cisco Systems, Inc.
8+ * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
9+ *
10+ */
11+
12+#ifndef __ASM_MACH_POWERTV_DMA_COHERENCE_H
13+#define __ASM_MACH_POWERTV_DMA_COHERENCE_H
14+
15+#include <linux/sched.h>
16+#include <linux/version.h>
17+#include <linux/device.h>
18+#include <asm/mach-powertv/asic.h>
19+
20+static inline bool is_kseg2(void *addr)
21+{
22+ return (unsigned long)addr >= KSEG2;
23+}
24+
25+static inline unsigned long virt_to_phys_from_pte(void *addr)
26+{
27+ pgd_t *pgd;
28+ pud_t *pud;
29+ pmd_t *pmd;
30+ pte_t *ptep, pte;
31+
32+ unsigned long virt_addr = (unsigned long)addr;
33+ unsigned long phys_addr = 0UL;
34+
35+ /* get the page global directory. */
36+ pgd = pgd_offset_k(virt_addr);
37+
38+ if (!pgd_none(*pgd)) {
39+ /* get the page upper directory */
40+ pud = pud_offset(pgd, virt_addr);
41+ if (!pud_none(*pud)) {
42+ /* get the page middle directory */
43+ pmd = pmd_offset(pud, virt_addr);
44+ if (!pmd_none(*pmd)) {
45+ /* get a pointer to the page table entry */
46+ ptep = pte_offset(pmd, virt_addr);
47+ pte = *ptep;
48+ /* check for a valid page */
49+ if (pte_present(pte)) {
50+ /* get the physical address the page is
51+ * refering to */
52+ phys_addr = (unsigned long)
53+ page_to_phys(pte_page(pte));
54+ /* add the offset within the page */
55+ phys_addr |= (virt_addr & ~PAGE_MASK);
56+ }
57+ }
58+ }
59+ }
60+
61+ return phys_addr;
62+}
63+
64+static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
65+ size_t size)
66+{
67+ if (is_kseg2(addr))
68+ return phys_to_bus(virt_to_phys_from_pte(addr));
69+ else
70+ return phys_to_bus(virt_to_phys(addr));
71+}
72+
73+static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
74+ struct page *page)
75+{
76+ return phys_to_bus(page_to_phys(page));
77+}
78+
79+static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
80+ dma_addr_t dma_addr)
81+{
82+ return bus_to_phys(dma_addr);
83+}
84+
85+static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
86+ size_t size, enum dma_data_direction direction)
87+{
88+}
89+
90+static inline int plat_dma_supported(struct device *dev, u64 mask)
91+{
92+ /*
93+ * we fall back to GFP_DMA when the mask isn't all 1s,
94+ * so we can't guarantee allocations that must be
95+ * within a tighter range than GFP_DMA..
96+ */
97+ if (mask < DMA_BIT_MASK(24))
98+ return 0;
99+
100+ return 1;
101+}
102+
103+static inline void plat_extra_sync_for_device(struct device *dev)
104+{
105+ return;
106+}
107+
108+static inline int plat_dma_mapping_error(struct device *dev,
109+ dma_addr_t dma_addr)
110+{
111+ return 0;
112+}
113+
114+static inline int plat_device_is_coherent(struct device *dev)
115+{
116+ return 0;
117+}
118+
119+#endif /* __ASM_MACH_POWERTV_DMA_COHERENCE_H */
arch/mips/include/asm/mach-powertv/interrupts.h+254−0
@@ -0,0 +1,254 @@
1+/*
2+ * Copyright (C) 2009 Cisco Systems, Inc.
3+ *
4+ * This program is free software; you can redistribute it and/or modify
5+ * it under the terms of the GNU General Public License as published by
6+ * the Free Software Foundation; either version 2 of the License, or
7+ * (at your option) any later version.
8+ *
9+ * This program is distributed in the hope that it will be useful,
10+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
11+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12+ * GNU General Public License for more details.
13+ *
14+ * You should have received a copy of the GNU General Public License
15+ * along with this program; if not, write to the Free Software
16+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17+ */
18+
19+#ifndef _ASM_MACH_POWERTV_INTERRUPTS_H_
20+#define _ASM_MACH_POWERTV_INTERRUPTS_H_
21+
22+/*
23+ * Defines for all of the interrupt lines
24+ */
25+
26+/* Definitions for backward compatibility */
27+#define kIrq_Uart1 irq_uart1
28+
29+#define ibase 0
30+
31+/*------------- Register: int_stat_3 */
32+/* 126 unused (bit 31) */
33+#define irq_asc2video (ibase+126) /* ASC 2 Video Interrupt */
34+#define irq_asc1video (ibase+125) /* ASC 1 Video Interrupt */
35+#define irq_comms_block_wd (ibase+124) /* ASC 1 Video Interrupt */
36+#define irq_fdma_mailbox (ibase+123) /* FDMA Mailbox Output */
37+#define irq_fdma_gp (ibase+122) /* FDMA GP Output */
38+#define irq_mips_pic (ibase+121) /* MIPS Performance Counter
39+ * Interrupt */
40+#define irq_mips_timer (ibase+120) /* MIPS Timer Interrupt */
41+#define irq_memory_protect (ibase+119) /* Memory Protection Interrupt
42+ * -- Ored by glue logic inside
43+ * SPARC ILC (see
44+ * INT_MEM_PROT_STAT, below,
45+ * for individual interrupts)
46+ */
47+/* 118 unused (bit 22) */
48+#define irq_sbag (ibase+117) /* SBAG Interrupt -- Ored by
49+ * glue logic inside SPARC ILC
50+ * (see INT_SBAG_STAT, below,
51+ * for individual interrupts) */
52+#define irq_qam_b_fec (ibase+116) /* QAM B FEC Interrupt */
53+#define irq_qam_a_fec (ibase+115) /* QAM A FEC Interrupt */
54+/* 114 unused (bit 18) */
55+#define irq_mailbox (ibase+113) /* Mailbox Debug Interrupt --
56+ * Ored by glue logic inside
57+ * SPARC ILC (see
58+ * INT_MAILBOX_STAT, below, for
59+ * individual interrupts) */
60+#define irq_fuse_stat1 (ibase+112) /* Fuse Status 1 */
61+#define irq_fuse_stat2 (ibase+111) /* Fuse Status 2 */
62+#define irq_fuse_stat3 (ibase+110) /* Blitter Interrupt / Fuse
63+ * Status 3 */
64+#define irq_blitter (ibase+110) /* Blitter Interrupt / Fuse
65+ * Status 3 */
66+#define irq_avc1_pp0 (ibase+109) /* AVC Decoder #1 PP0
67+ * Interrupt */
68+#define irq_avc1_pp1 (ibase+108) /* AVC Decoder #1 PP1
69+ * Interrupt */
70+#define irq_avc1_mbe (ibase+107) /* AVC Decoder #1 MBE
71+ * Interrupt */
72+#define irq_avc2_pp0 (ibase+106) /* AVC Decoder #2 PP0
73+ * Interrupt */
74+#define irq_avc2_pp1 (ibase+105) /* AVC Decoder #2 PP1
75+ * Interrupt */
76+#define irq_avc2_mbe (ibase+104) /* AVC Decoder #2 MBE
77+ * Interrupt */
78+#define irq_zbug_spi (ibase+103) /* Zbug SPI Slave Interrupt */
79+#define irq_qam_mod2 (ibase+102) /* QAM Modulator 2 DMA
80+ * Interrupt */
81+#define irq_ir_rx (ibase+101) /* IR RX 2 Interrupt */
82+#define irq_aud_dsp2 (ibase+100) /* Audio DSP #2 Interrupt */
83+#define irq_aud_dsp1 (ibase+99) /* Audio DSP #1 Interrupt */
84+#define irq_docsis (ibase+98) /* DOCSIS Debug Interrupt */
85+#define irq_sd_dvp1 (ibase+97) /* SD DVP #1 Interrupt */
86+#define irq_sd_dvp2 (ibase+96) /* SD DVP #2 Interrupt */
87+/*------------- Register: int_stat_2 */
88+#define irq_hd_dvp (ibase+95) /* HD DVP Interrupt */
89+#define kIrq_Prewatchdog (ibase+94) /* watchdog Pre-Interrupt */
90+#define irq_timer2 (ibase+93) /* Programmable Timer
91+ * Interrupt 2 */
92+#define irq_1394 (ibase+92) /* 1394 Firewire Interrupt */
93+#define irq_usbohci (ibase+91) /* USB 2.0 OHCI Interrupt */
94+#define irq_usbehci (ibase+90) /* USB 2.0 EHCI Interrupt */
95+#define irq_pciexp (ibase+89) /* PCI Express 0 Interrupt */
96+#define irq_pciexp0 (ibase+89) /* PCI Express 0 Interrupt */
97+#define irq_afe1 (ibase+88) /* AFE 1 Interrupt */
98+#define irq_sata (ibase+87) /* SATA 1 Interrupt */
99+#define irq_sata1 (ibase+87) /* SATA 1 Interrupt */
100+#define irq_dtcp (ibase+86) /* DTCP Interrupt */
101+#define irq_pciexp1 (ibase+85) /* PCI Express 1 Interrupt */
102+/* 84 unused (bit 20) */
103+/* 83 unused (bit 19) */
104+/* 82 unused (bit 18) */
105+#define irq_sata2 (ibase+81) /* SATA2 Interrupt */
106+#define irq_uart2 (ibase+80) /* UART2 Interrupt */
107+#define irq_legacy_usb (ibase+79) /* Legacy USB Host ISR (1.1
108+ * Host module) */
109+#define irq_pod (ibase+78) /* POD Interrupt */
110+#define irq_slave_usb (ibase+77) /* Slave USB */
111+#define irq_denc1 (ibase+76) /* DENC #1 VTG Interrupt */
112+#define irq_vbi_vtg (ibase+75) /* VBI VTG Interrupt */
113+#define irq_afe2 (ibase+74) /* AFE 2 Interrupt */
114+#define irq_denc2 (ibase+73) /* DENC #2 VTG Interrupt */
115+#define irq_asc2 (ibase+72) /* ASC #2 Interrupt */
116+#define irq_asc1 (ibase+71) /* ASC #1 Interrupt */
117+#define irq_mod_dma (ibase+70) /* Modulator DMA Interrupt */
118+#define irq_byte_eng1 (ibase+69) /* Byte Engine Interrupt [1] */
119+#define irq_byte_eng0 (ibase+68) /* Byte Engine Interrupt [0] */
120+/* 67 unused (bit 03) */
121+/* 66 unused (bit 02) */
122+/* 65 unused (bit 01) */
123+/* 64 unused (bit 00) */
124+/*------------- Register: int_stat_1 */
125+/* 63 unused (bit 31) */
126+/* 62 unused (bit 30) */
127+/* 61 unused (bit 29) */
128+/* 60 unused (bit 28) */
129+/* 59 unused (bit 27) */
130+/* 58 unused (bit 26) */
131+/* 57 unused (bit 25) */
132+/* 56 unused (bit 24) */
133+#define irq_buf_dma_mem2mem (ibase+55) /* BufDMA Memory to Memory
134+ * Interrupt */
135+#define irq_buf_dma_usbtransmit (ibase+54) /* BufDMA USB Transmit
136+ * Interrupt */
137+#define irq_buf_dma_qpskpodtransmit (ibase+53) /* BufDMA QPSK/POD Tramsit
138+ * Interrupt */
139+#define irq_buf_dma_transmit_error (ibase+52) /* BufDMA Transmit Error
140+ * Interrupt */
141+#define irq_buf_dma_usbrecv (ibase+51) /* BufDMA USB Receive
142+ * Interrupt */
143+#define irq_buf_dma_qpskpodrecv (ibase+50) /* BufDMA QPSK/POD Receive
144+ * Interrupt */
145+#define irq_buf_dma_recv_error (ibase+49) /* BufDMA Receive Error
146+ * Interrupt */
147+#define irq_qamdma_transmit_play (ibase+48) /* QAMDMA Transmit/Play
148+ * Interrupt */
149+#define irq_qamdma_transmit_error (ibase+47) /* QAMDMA Transmit Error
150+ * Interrupt */
151+#define irq_qamdma_recv2high (ibase+46) /* QAMDMA Receive 2 High
152+ * (Chans 63-32) */
153+#define irq_qamdma_recv2low (ibase+45) /* QAMDMA Receive 2 Low
154+ * (Chans 31-0) */
155+#define irq_qamdma_recv1high (ibase+44) /* QAMDMA Receive 1 High
156+ * (Chans 63-32) */
157+#define irq_qamdma_recv1low (ibase+43) /* QAMDMA Receive 1 Low
158+ * (Chans 31-0) */
159+#define irq_qamdma_recv_error (ibase+42) /* QAMDMA Receive Error
160+ * Interrupt */
161+#define irq_mpegsplice (ibase+41) /* MPEG Splice Interrupt */
162+#define irq_deinterlace_rdy (ibase+40) /* Deinterlacer Frame Ready
163+ * Interrupt */
164+#define irq_ext_in0 (ibase+39) /* External Interrupt irq_in0 */
165+#define irq_gpio3 (ibase+38) /* GP I/O IRQ 3 - From GP I/O
166+ * Module */
167+#define irq_gpio2 (ibase+37) /* GP I/O IRQ 2 - From GP I/O
168+ * Module (ABE_intN) */
169+#define irq_pcrcmplt1 (ibase+36) /* PCR Capture Complete or
170+ * Discontinuity 1 */
171+#define irq_pcrcmplt2 (ibase+35) /* PCR Capture Complete or
172+ * Discontinuity 2 */
173+#define irq_parse_peierr (ibase+34) /* PID Parser Error Detect
174+ * (PEI) */
175+#define irq_parse_cont_err (ibase+33) /* PID Parser continuity error
176+ * detect */
177+#define irq_ds1framer (ibase+32) /* DS1 Framer Interrupt */
178+/*------------- Register: int_stat_0 */
179+#define irq_gpio1 (ibase+31) /* GP I/O IRQ 1 - From GP I/O
180+ * Module */
181+#define irq_gpio0 (ibase+30) /* GP I/O IRQ 0 - From GP I/O
182+ * Module */
183+#define irq_qpsk_out_aloha (ibase+29) /* QPSK Output Slotted Aloha
184+ * (chan 3) Transmission
185+ * Completed OK */
186+#define irq_qpsk_out_tdma (ibase+28) /* QPSK Output TDMA (chan 2)
187+ * Transmission Completed OK */
188+#define irq_qpsk_out_reserve (ibase+27) /* QPSK Output Reservation
189+ * (chan 1) Transmission
190+ * Completed OK */
191+#define irq_qpsk_out_aloha_err (ibase+26) /* QPSK Output Slotted Aloha
192+ * (chan 3)Transmission
193+ * completed with Errors. */
194+#define irq_qpsk_out_tdma_err (ibase+25) /* QPSK Output TDMA (chan 2)
195+ * Transmission completed with
196+ * Errors. */
197+#define irq_qpsk_out_rsrv_err (ibase+24) /* QPSK Output Reservation
198+ * (chan 1) Transmission
199+ * completed with Errors */
200+#define irq_aloha_fail (ibase+23) /* Unsuccessful Resend of Aloha
201+ * for N times. Aloha retry
202+ * timeout for channel 3. */
203+#define irq_timer1 (ibase+22) /* Programmable Timer
204+ * Interrupt */
205+#define irq_keyboard (ibase+21) /* Keyboard Module Interrupt */
206+#define irq_i2c (ibase+20) /* I2C Module Interrupt */
207+#define irq_spi (ibase+19) /* SPI Module Interrupt */
208+#define irq_irblaster (ibase+18) /* IR Blaster Interrupt */
209+#define irq_splice_detect (ibase+17) /* PID Key Change Interrupt or
210+ * Splice Detect Interrupt */
211+#define irq_se_micro (ibase+16) /* Secure Micro I/F Module
212+ * Interrupt */
213+#define irq_uart1 (ibase+15) /* UART Interrupt */
214+#define irq_irrecv (ibase+14) /* IR Receiver Interrupt */
215+#define irq_host_int1 (ibase+13) /* Host-to-Host Interrupt 1 */
216+#define irq_host_int0 (ibase+12) /* Host-to-Host Interrupt 0 */
217+#define irq_qpsk_hecerr (ibase+11) /* QPSK HEC Error Interrupt */
218+#define irq_qpsk_crcerr (ibase+10) /* QPSK AAL-5 CRC Error
219+ * Interrupt */
220+/* 9 unused (bit 09) */
221+/* 8 unused (bit 08) */
222+#define irq_psicrcerr (ibase+7) /* QAM PSI CRC Error
223+ * Interrupt */
224+#define irq_psilength_err (ibase+6) /* QAM PSI Length Error
225+ * Interrupt */
226+#define irq_esfforward (ibase+5) /* ESF Interrupt Mark From
227+ * Forward Path Reference -
228+ * every 3ms when forward Mbits
229+ * and forward slot control
230+ * bytes are updated. */
231+#define irq_esfreverse (ibase+4) /* ESF Interrupt Mark from
232+ * Reverse Path Reference -
233+ * delayed from forward mark by
234+ * the ranging delay plus a
235+ * fixed amount. When reverse
236+ * Mbits and reverse slot
237+ * control bytes are updated.
238+ * Occurs every 3ms for 3.0M and
239+ * 1.554 M upstream rates and
240+ * every 6 ms for 256K upstream
241+ * rate. */
242+#define irq_aloha_timeout (ibase+3) /* Slotted-Aloha timeout on
243+ * Channel 1. */
244+#define irq_reservation (ibase+2) /* Partial (or Incremental)
245+ * Reservation Message Completed
246+ * or Slotted aloha verify for
247+ * channel 1. */
248+#define irq_aloha3 (ibase+1) /* Slotted-Aloha Message Verify
249+ * Interrupt or Reservation
250+ * increment completed for
251+ * channel 3. */
252+#define irq_mpeg_d (ibase+0) /* MPEG Decoder Interrupt */
253+#endif /* _ASM_MACH_POWERTV_INTERRUPTS_H_ */
254+
arch/mips/include/asm/mach-powertv/ioremap.h+90−0
@@ -0,0 +1,90 @@
1+/*
2+ * This program is free software; you can redistribute it and/or
3+ * modify it under the terms of the GNU General Public License
4+ * as published by the Free Software Foundation; either version
5+ * 2 of the License, or (at your option) any later version.
6+ *
7+ * Portions Copyright (C) Cisco Systems, Inc.
8+ */
9+#ifndef __ASM_MACH_POWERTV_IOREMAP_H
10+#define __ASM_MACH_POWERTV_IOREMAP_H
11+
12+#include <linux/types.h>
13+
14+#define LOW_MEM_BOUNDARY_PHYS 0x20000000
15+#define LOW_MEM_BOUNDARY_MASK (~(LOW_MEM_BOUNDARY_PHYS - 1))
16+
17+/*
18+ * The bus addresses are different than the physical addresses that
19+ * the processor sees by an offset. This offset varies by ASIC
20+ * version. Define a variable to hold the offset and some macros to
21+ * make the conversion simpler. */
22+extern unsigned long phys_to_bus_offset;
23+
24+#ifdef CONFIG_HIGHMEM
25+#define MEM_GAP_PHYS 0x60000000
26+/*
27+ * TODO: We will use the hard code for conversion between physical and
28+ * bus until the bootloader releases their device tree to us.
29+ */
30+#define phys_to_bus(x) (((x) < LOW_MEM_BOUNDARY_PHYS) ? \
31+ ((x) + phys_to_bus_offset) : (x))
32+#define bus_to_phys(x) (((x) < MEM_GAP_PHYS_ADDR) ? \
33+ ((x) - phys_to_bus_offset) : (x))
34+#else
35+#define phys_to_bus(x) ((x) + phys_to_bus_offset)
36+#define bus_to_phys(x) ((x) - phys_to_bus_offset)
37+#endif
38+
39+/*
40+ * Determine whether the address we are given is for an ASIC device
41+ * Params: addr Address to check
42+ * Returns: Zero if the address is not for ASIC devices, non-zero
43+ * if it is.
44+ */
45+static inline int asic_is_device_addr(phys_t addr)
46+{
47+ return !((phys_t)addr & (phys_t) LOW_MEM_BOUNDARY_MASK);
48+}
49+
50+/*
51+ * Determine whether the address we are given is external RAM mappable
52+ * into KSEG1.
53+ * Params: addr Address to check
54+ * Returns: Zero if the address is not for external RAM and
55+ */
56+static inline int asic_is_lowmem_ram_addr(phys_t addr)
57+{
58+ /*
59+ * The RAM always starts at the following address in the processor's
60+ * physical address space
61+ */
62+ static const phys_t phys_ram_base = 0x10000000;
63+ phys_t bus_ram_base;
64+
65+ bus_ram_base = phys_to_bus_offset + phys_ram_base;
66+
67+ return addr >= bus_ram_base &&
68+ addr < (bus_ram_base + (LOW_MEM_BOUNDARY_PHYS - phys_ram_base));
69+}
70+
71+/*
72+ * Allow physical addresses to be fixed up to help peripherals located
73+ * outside the low 32-bit range -- generic pass-through version.
74+ */
75+static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
76+{
77+ return phys_addr;
78+}
79+
80+static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
81+ unsigned long flags)
82+{
83+ return NULL;
84+}
85+
86+static inline int plat_iounmap(const volatile void __iomem *addr)
87+{
88+ return 0;
89+}
90+#endif /* __ASM_MACH_POWERTV_IOREMAP_H */
arch/mips/include/asm/mach-powertv/irq.h+25−0
@@ -0,0 +1,25 @@
1+/*
2+ * Copyright (C) 2009 Cisco Systems, Inc.
3+ *
4+ * This program is free software; you can redistribute it and/or modify
5+ * it under the terms of the GNU General Public License as published by
6+ * the Free Software Foundation; either version 2 of the License, or
7+ * (at your option) any later version.
8+ *
9+ * This program is distributed in the hope that it will be useful,
10+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
11+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12+ * GNU General Public License for more details.
13+ *
14+ * You should have received a copy of the GNU General Public License
15+ * along with this program; if not, write to the Free Software
16+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17+ */
18+
19+#ifndef _ASM_MACH_POWERTV_IRQ_H
20+#define _ASM_MACH_POWERTV_IRQ_H
21+#include <asm/mach-powertv/interrupts.h>
22+
23+#define MIPS_CPU_IRQ_BASE ibase
24+#define NR_IRQS 127
25+#endif
arch/mips/include/asm/mach-powertv/powertv-clock.h+29−0
@@ -0,0 +1,29 @@
1+/*
2+ * Copyright (C) 2009 Cisco Systems, Inc.
3+ *
4+ * This program is free software; you can redistribute it and/or modify
5+ * it under the terms of the GNU General Public License as published by
6+ * the Free Software Foundation; either version 2 of the License, or
7+ * (at your option) any later version.
8+ *
9+ * This program is distributed in the hope that it will be useful,
10+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
11+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12+ * GNU General Public License for more details.
13+ *
14+ * You should have received a copy of the GNU General Public License
15+ * along with this program; if not, write to the Free Software
16+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17+ */
18+/*
19+ * Local definitions for the powertv PCI code
20+ */
21+
22+#ifndef _POWERTV_PCI_POWERTV_PCI_H_
23+#define _POWERTV_PCI_POWERTV_PCI_H_
24+extern int asic_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
25+extern int asic_pcie_init(void);
26+extern int asic_pcie_init(void);
27+
28+extern int log_level;
29+#endif
arch/mips/include/asm/mach-powertv/war.hrenamed from arch/mips/include/asm/mach-excite/war.h+11−8
@@ -3,10 +3,13 @@ · 2 unmodified lines
33 * License. See the file "COPYING" in the main directory of this archive
44 * for more details.
55 *
6+ * This version for the PowerTV platform copied from the Malta version.
7+ *
68 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
9+ * Portions copyright (C) 2009 Cisco Systems, Inc.
710 */
8−#ifndef __ASM_MIPS_MACH_EXCITE_WAR_H
9−#define __ASM_MIPS_MACH_EXCITE_WAR_H
11+#ifndef __ASM_MACH_POWERTV_WAR_H
12+#define __ASM_MACH_POWERTV_WAR_H
1013
1114 #define R4600_V1_INDEX_ICACHEOP_WAR 0
1215 #define R4600_V1_HIT_CACHEOP_WAR 0
@@ -14,12 +17,12 @@ · 1 unmodified line
1417 #define R5432_CP0_INTERRUPT_WAR 0
1518 #define BCM1250_M3_WAR 0
1619 #define SIBYTE_1956_WAR 0
17−#define MIPS4K_ICACHE_REFILL_WAR 0
18−#define MIPS_CACHE_SYNC_WAR 0
20+#define MIPS4K_ICACHE_REFILL_WAR 1
21+#define MIPS_CACHE_SYNC_WAR 1
1922 #define TX49XX_ICACHE_INDEX_INV_WAR 0
20−#define RM9000_CDEX_SMP_WAR 1
21−#define ICACHE_REFILLS_WORKAROUND_WAR 1
23+#define RM9000_CDEX_SMP_WAR 0
24+#define ICACHE_REFILLS_WORKAROUND_WAR 1
2225 #define R10000_LLSC_WAR 0
23−#define MIPS34K_MISSED_ITLB_WAR 0
26+#define MIPS34K_MISSED_ITLB_WAR 0
2427
25−#endif /* __ASM_MIPS_MACH_EXCITE_WAR_H */
28+#endif /* __ASM_MACH_POWERTV_WAR_H */
arch/mips/include/asm/mips-boards/bonito64.h+0−5
@@ -26,11 +26,6 @@ · 25 unmodified lines
2626 /* offsets from base register */
2727 #define BONITO(x) (x)
2828
29−#elif defined(CONFIG_LEMOTE_FULOONG2E)
30−
31−#define BONITO(x) (*(volatile u32 *)((char *)CKSEG1ADDR(BONITO_REG_BASE) + (x)))
32−#define BONITO_IRQ_BASE 32
33−
3429 #else
3530
3631 /*
arch/mips/include/asm/mmu_context.h+28−1
@@ -24,6 +24,33 @@ · 23 unmodified lines
2424 #endif /* SMTC */
2525 #include <asm-generic/mm_hooks.h>
2626
27+#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
28+
29+#define TLBMISS_HANDLER_SETUP_PGD(pgd) \
30+ tlbmiss_handler_setup_pgd((unsigned long)(pgd))
31+
32+static inline void tlbmiss_handler_setup_pgd(unsigned long pgd)
33+{
34+ /* Check for swapper_pg_dir and convert to physical address. */
35+ if ((pgd & CKSEG3) == CKSEG0)
36+ pgd = CPHYSADDR(pgd);
37+ write_c0_context(pgd << 11);
38+}
39+
40+#define TLBMISS_HANDLER_SETUP() \
41+ do { \
42+ TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \
43+ write_c0_xcontext((unsigned long) smp_processor_id() << 51); \
44+ } while (0)
45+
46+
47+static inline unsigned long get_current_pgd(void)
48+{
49+ return PHYS_TO_XKSEG_CACHED((read_c0_context() >> 11) & ~0xfffUL);
50+}
51+
52+#else /* CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/
53+
2754 /*
2855 * For the fast tlb miss handlers, we keep a per cpu array of pointers
2956 * to the current pgd for each processor. Also, the proc. id is stuffed
@@ -46,7 +73,7 @@ extern unsigned long pgd_current[]; · 16 unmodified lines
4673 back_to_back_c0_hazard(); \
4774 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
4875 #endif
49−
76+#endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/
5077 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
5178
5279 #define ASID_INC 0x40
arch/mips/include/asm/octeon/cvmx-agl-defs.h+1194−0
@@ -0,0 +1,1194 @@
1+/***********************license start***************
2+ * Author: Cavium Networks
3+ *
4+ * Contact: support@caviumnetworks.com
5+ * This file is part of the OCTEON SDK
6+ *
7+ * Copyright (c) 2003-2008 Cavium Networks
8+ *
9+ * This file is free software; you can redistribute it and/or modify
10+ * it under the terms of the GNU General Public License, Version 2, as
11+ * published by the Free Software Foundation.
12+ *
13+ * This file is distributed in the hope that it will be useful, but
14+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16+ * NONINFRINGEMENT. See the GNU General Public License for more
17+ * details.
18+ *
19+ * You should have received a copy of the GNU General Public License
20+ * along with this file; if not, write to the Free Software
21+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22+ * or visit http://www.gnu.org/licenses/.
23+ *
24+ * This file may also be available under a different license from Cavium.
25+ * Contact Cavium Networks for more information
26+ ***********************license end**************************************/
27+
28+#ifndef __CVMX_AGL_DEFS_H__
29+#define __CVMX_AGL_DEFS_H__
30+
31+#define CVMX_AGL_GMX_BAD_REG \
32+ CVMX_ADD_IO_SEG(0x00011800E0000518ull)
33+#define CVMX_AGL_GMX_BIST \
34+ CVMX_ADD_IO_SEG(0x00011800E0000400ull)
35+#define CVMX_AGL_GMX_DRV_CTL \
36+ CVMX_ADD_IO_SEG(0x00011800E00007F0ull)
37+#define CVMX_AGL_GMX_INF_MODE \
38+ CVMX_ADD_IO_SEG(0x00011800E00007F8ull)
39+#define CVMX_AGL_GMX_PRTX_CFG(offset) \
40+ CVMX_ADD_IO_SEG(0x00011800E0000010ull + (((offset) & 1) * 2048))
41+#define CVMX_AGL_GMX_RXX_ADR_CAM0(offset) \
42+ CVMX_ADD_IO_SEG(0x00011800E0000180ull + (((offset) & 1) * 2048))
43+#define CVMX_AGL_GMX_RXX_ADR_CAM1(offset) \
44+ CVMX_ADD_IO_SEG(0x00011800E0000188ull + (((offset) & 1) * 2048))
45+#define CVMX_AGL_GMX_RXX_ADR_CAM2(offset) \
46+ CVMX_ADD_IO_SEG(0x00011800E0000190ull + (((offset) & 1) * 2048))
47+#define CVMX_AGL_GMX_RXX_ADR_CAM3(offset) \
48+ CVMX_ADD_IO_SEG(0x00011800E0000198ull + (((offset) & 1) * 2048))
49+#define CVMX_AGL_GMX_RXX_ADR_CAM4(offset) \
50+ CVMX_ADD_IO_SEG(0x00011800E00001A0ull + (((offset) & 1) * 2048))
51+#define CVMX_AGL_GMX_RXX_ADR_CAM5(offset) \
52+ CVMX_ADD_IO_SEG(0x00011800E00001A8ull + (((offset) & 1) * 2048))
53+#define CVMX_AGL_GMX_RXX_ADR_CAM_EN(offset) \
54+ CVMX_ADD_IO_SEG(0x00011800E0000108ull + (((offset) & 1) * 2048))
55+#define CVMX_AGL_GMX_RXX_ADR_CTL(offset) \
56+ CVMX_ADD_IO_SEG(0x00011800E0000100ull + (((offset) & 1) * 2048))
57+#define CVMX_AGL_GMX_RXX_DECISION(offset) \
58+ CVMX_ADD_IO_SEG(0x00011800E0000040ull + (((offset) & 1) * 2048))
59+#define CVMX_AGL_GMX_RXX_FRM_CHK(offset) \
60+ CVMX_ADD_IO_SEG(0x00011800E0000020ull + (((offset) & 1) * 2048))
61+#define CVMX_AGL_GMX_RXX_FRM_CTL(offset) \
62+ CVMX_ADD_IO_SEG(0x00011800E0000018ull + (((offset) & 1) * 2048))
63+#define CVMX_AGL_GMX_RXX_FRM_MAX(offset) \
64+ CVMX_ADD_IO_SEG(0x00011800E0000030ull + (((offset) & 1) * 2048))
65+#define CVMX_AGL_GMX_RXX_FRM_MIN(offset) \
66+ CVMX_ADD_IO_SEG(0x00011800E0000028ull + (((offset) & 1) * 2048))
67+#define CVMX_AGL_GMX_RXX_IFG(offset) \
68+ CVMX_ADD_IO_SEG(0x00011800E0000058ull + (((offset) & 1) * 2048))
69+#define CVMX_AGL_GMX_RXX_INT_EN(offset) \
70+ CVMX_ADD_IO_SEG(0x00011800E0000008ull + (((offset) & 1) * 2048))
71+#define CVMX_AGL_GMX_RXX_INT_REG(offset) \
72+ CVMX_ADD_IO_SEG(0x00011800E0000000ull + (((offset) & 1) * 2048))
73+#define CVMX_AGL_GMX_RXX_JABBER(offset) \
74+ CVMX_ADD_IO_SEG(0x00011800E0000038ull + (((offset) & 1) * 2048))
75+#define CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(offset) \
76+ CVMX_ADD_IO_SEG(0x00011800E0000068ull + (((offset) & 1) * 2048))
77+#define CVMX_AGL_GMX_RXX_STATS_CTL(offset) \
78+ CVMX_ADD_IO_SEG(0x00011800E0000050ull + (((offset) & 1) * 2048))
79+#define CVMX_AGL_GMX_RXX_STATS_OCTS(offset) \
80+ CVMX_ADD_IO_SEG(0x00011800E0000088ull + (((offset) & 1) * 2048))
81+#define CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(offset) \
82+ CVMX_ADD_IO_SEG(0x00011800E0000098ull + (((offset) & 1) * 2048))
83+#define CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(offset) \
84+ CVMX_ADD_IO_SEG(0x00011800E00000A8ull + (((offset) & 1) * 2048))
85+#define CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(offset) \
86+ CVMX_ADD_IO_SEG(0x00011800E00000B8ull + (((offset) & 1) * 2048))
87+#define CVMX_AGL_GMX_RXX_STATS_PKTS(offset) \
88+ CVMX_ADD_IO_SEG(0x00011800E0000080ull + (((offset) & 1) * 2048))
89+#define CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(offset) \
90+ CVMX_ADD_IO_SEG(0x00011800E00000C0ull + (((offset) & 1) * 2048))
91+#define CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(offset) \
92+ CVMX_ADD_IO_SEG(0x00011800E0000090ull + (((offset) & 1) * 2048))
93+#define CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(offset) \
94+ CVMX_ADD_IO_SEG(0x00011800E00000A0ull + (((offset) & 1) * 2048))
95+#define CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(offset) \
96+ CVMX_ADD_IO_SEG(0x00011800E00000B0ull + (((offset) & 1) * 2048))
97+#define CVMX_AGL_GMX_RXX_UDD_SKP(offset) \
98+ CVMX_ADD_IO_SEG(0x00011800E0000048ull + (((offset) & 1) * 2048))
99+#define CVMX_AGL_GMX_RX_BP_DROPX(offset) \
100+ CVMX_ADD_IO_SEG(0x00011800E0000420ull + (((offset) & 1) * 8))
101+#define CVMX_AGL_GMX_RX_BP_OFFX(offset) \
102+ CVMX_ADD_IO_SEG(0x00011800E0000460ull + (((offset) & 1) * 8))
103+#define CVMX_AGL_GMX_RX_BP_ONX(offset) \
104+ CVMX_ADD_IO_SEG(0x00011800E0000440ull + (((offset) & 1) * 8))
105+#define CVMX_AGL_GMX_RX_PRT_INFO \
106+ CVMX_ADD_IO_SEG(0x00011800E00004E8ull)
107+#define CVMX_AGL_GMX_RX_TX_STATUS \
108+ CVMX_ADD_IO_SEG(0x00011800E00007E8ull)
109+#define CVMX_AGL_GMX_SMACX(offset) \
110+ CVMX_ADD_IO_SEG(0x00011800E0000230ull + (((offset) & 1) * 2048))
111+#define CVMX_AGL_GMX_STAT_BP \
112+ CVMX_ADD_IO_SEG(0x00011800E0000520ull)
113+#define CVMX_AGL_GMX_TXX_APPEND(offset) \
114+ CVMX_ADD_IO_SEG(0x00011800E0000218ull + (((offset) & 1) * 2048))
115+#define CVMX_AGL_GMX_TXX_CTL(offset) \
116+ CVMX_ADD_IO_SEG(0x00011800E0000270ull + (((offset) & 1) * 2048))
117+#define CVMX_AGL_GMX_TXX_MIN_PKT(offset) \
118+ CVMX_ADD_IO_SEG(0x00011800E0000240ull + (((offset) & 1) * 2048))
119+#define CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(offset) \
120+ CVMX_ADD_IO_SEG(0x00011800E0000248ull + (((offset) & 1) * 2048))
121+#define CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(offset) \
122+ CVMX_ADD_IO_SEG(0x00011800E0000238ull + (((offset) & 1) * 2048))
123+#define CVMX_AGL_GMX_TXX_PAUSE_TOGO(offset) \
124+ CVMX_ADD_IO_SEG(0x00011800E0000258ull + (((offset) & 1) * 2048))
125+#define CVMX_AGL_GMX_TXX_PAUSE_ZERO(offset) \
126+ CVMX_ADD_IO_SEG(0x00011800E0000260ull + (((offset) & 1) * 2048))
127+#define CVMX_AGL_GMX_TXX_SOFT_PAUSE(offset) \
128+ CVMX_ADD_IO_SEG(0x00011800E0000250ull + (((offset) & 1) * 2048))
129+#define CVMX_AGL_GMX_TXX_STAT0(offset) \
130+ CVMX_ADD_IO_SEG(0x00011800E0000280ull + (((offset) & 1) * 2048))
131+#define CVMX_AGL_GMX_TXX_STAT1(offset) \
132+ CVMX_ADD_IO_SEG(0x00011800E0000288ull + (((offset) & 1) * 2048))
133+#define CVMX_AGL_GMX_TXX_STAT2(offset) \
134+ CVMX_ADD_IO_SEG(0x00011800E0000290ull + (((offset) & 1) * 2048))
135+#define CVMX_AGL_GMX_TXX_STAT3(offset) \
136+ CVMX_ADD_IO_SEG(0x00011800E0000298ull + (((offset) & 1) * 2048))
137+#define CVMX_AGL_GMX_TXX_STAT4(offset) \
138+ CVMX_ADD_IO_SEG(0x00011800E00002A0ull + (((offset) & 1) * 2048))
139+#define CVMX_AGL_GMX_TXX_STAT5(offset) \
140+ CVMX_ADD_IO_SEG(0x00011800E00002A8ull + (((offset) & 1) * 2048))
141+#define CVMX_AGL_GMX_TXX_STAT6(offset) \
142+ CVMX_ADD_IO_SEG(0x00011800E00002B0ull + (((offset) & 1) * 2048))
143+#define CVMX_AGL_GMX_TXX_STAT7(offset) \
144+ CVMX_ADD_IO_SEG(0x00011800E00002B8ull + (((offset) & 1) * 2048))
145+#define CVMX_AGL_GMX_TXX_STAT8(offset) \
146+ CVMX_ADD_IO_SEG(0x00011800E00002C0ull + (((offset) & 1) * 2048))
147+#define CVMX_AGL_GMX_TXX_STAT9(offset) \
148+ CVMX_ADD_IO_SEG(0x00011800E00002C8ull + (((offset) & 1) * 2048))
149+#define CVMX_AGL_GMX_TXX_STATS_CTL(offset) \
150+ CVMX_ADD_IO_SEG(0x00011800E0000268ull + (((offset) & 1) * 2048))
151+#define CVMX_AGL_GMX_TXX_THRESH(offset) \
152+ CVMX_ADD_IO_SEG(0x00011800E0000210ull + (((offset) & 1) * 2048))
153+#define CVMX_AGL_GMX_TX_BP \
154+ CVMX_ADD_IO_SEG(0x00011800E00004D0ull)
155+#define CVMX_AGL_GMX_TX_COL_ATTEMPT \
156+ CVMX_ADD_IO_SEG(0x00011800E0000498ull)
157+#define CVMX_AGL_GMX_TX_IFG \
158+ CVMX_ADD_IO_SEG(0x00011800E0000488ull)
159+#define CVMX_AGL_GMX_TX_INT_EN \
160+ CVMX_ADD_IO_SEG(0x00011800E0000508ull)
161+#define CVMX_AGL_GMX_TX_INT_REG \
162+ CVMX_ADD_IO_SEG(0x00011800E0000500ull)
163+#define CVMX_AGL_GMX_TX_JAM \
164+ CVMX_ADD_IO_SEG(0x00011800E0000490ull)
165+#define CVMX_AGL_GMX_TX_LFSR \
166+ CVMX_ADD_IO_SEG(0x00011800E00004F8ull)
167+#define CVMX_AGL_GMX_TX_OVR_BP \
168+ CVMX_ADD_IO_SEG(0x00011800E00004C8ull)
169+#define CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC \
170+ CVMX_ADD_IO_SEG(0x00011800E00004A0ull)
171+#define CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE \
172+ CVMX_ADD_IO_SEG(0x00011800E00004A8ull)
173+
174+union cvmx_agl_gmx_bad_reg {
175+ uint64_t u64;
176+ struct cvmx_agl_gmx_bad_reg_s {
177+ uint64_t reserved_38_63:26;
178+ uint64_t txpsh1:1;
179+ uint64_t txpop1:1;
180+ uint64_t ovrflw1:1;
181+ uint64_t txpsh:1;
182+ uint64_t txpop:1;
183+ uint64_t ovrflw:1;
184+ uint64_t reserved_27_31:5;
185+ uint64_t statovr:1;
186+ uint64_t reserved_23_25:3;
187+ uint64_t loststat:1;
188+ uint64_t reserved_4_21:18;
189+ uint64_t out_ovr:2;
190+ uint64_t reserved_0_1:2;
191+ } s;
192+ struct cvmx_agl_gmx_bad_reg_s cn52xx;
193+ struct cvmx_agl_gmx_bad_reg_s cn52xxp1;
194+ struct cvmx_agl_gmx_bad_reg_cn56xx {
195+ uint64_t reserved_35_63:29;
196+ uint64_t txpsh:1;
197+ uint64_t txpop:1;
198+ uint64_t ovrflw:1;
199+ uint64_t reserved_27_31:5;
200+ uint64_t statovr:1;
201+ uint64_t reserved_23_25:3;
202+ uint64_t loststat:1;
203+ uint64_t reserved_3_21:19;
204+ uint64_t out_ovr:1;
205+ uint64_t reserved_0_1:2;
206+ } cn56xx;
207+ struct cvmx_agl_gmx_bad_reg_cn56xx cn56xxp1;
208+};
209+
210+union cvmx_agl_gmx_bist {
211+ uint64_t u64;
212+ struct cvmx_agl_gmx_bist_s {
213+ uint64_t reserved_10_63:54;
214+ uint64_t status:10;
215+ } s;
216+ struct cvmx_agl_gmx_bist_s cn52xx;
217+ struct cvmx_agl_gmx_bist_s cn52xxp1;
218+ struct cvmx_agl_gmx_bist_s cn56xx;
219+ struct cvmx_agl_gmx_bist_s cn56xxp1;
220+};
221+
222+union cvmx_agl_gmx_drv_ctl {
223+ uint64_t u64;
224+ struct cvmx_agl_gmx_drv_ctl_s {
225+ uint64_t reserved_49_63:15;
226+ uint64_t byp_en1:1;
227+ uint64_t reserved_45_47:3;
228+ uint64_t pctl1:5;
229+ uint64_t reserved_37_39:3;
230+ uint64_t nctl1:5;
231+ uint64_t reserved_17_31:15;
232+ uint64_t byp_en:1;
233+ uint64_t reserved_13_15:3;
234+ uint64_t pctl:5;
235+ uint64_t reserved_5_7:3;
236+ uint64_t nctl:5;
237+ } s;
238+ struct cvmx_agl_gmx_drv_ctl_s cn52xx;
239+ struct cvmx_agl_gmx_drv_ctl_s cn52xxp1;
240+ struct cvmx_agl_gmx_drv_ctl_cn56xx {
241+ uint64_t reserved_17_63:47;
242+ uint64_t byp_en:1;
243+ uint64_t reserved_13_15:3;
244+ uint64_t pctl:5;
245+ uint64_t reserved_5_7:3;
246+ uint64_t nctl:5;
247+ } cn56xx;
248+ struct cvmx_agl_gmx_drv_ctl_cn56xx cn56xxp1;
249+};
250+
251+union cvmx_agl_gmx_inf_mode {
252+ uint64_t u64;
253+ struct cvmx_agl_gmx_inf_mode_s {
254+ uint64_t reserved_2_63:62;
255+ uint64_t en:1;
256+ uint64_t reserved_0_0:1;
257+ } s;
258+ struct cvmx_agl_gmx_inf_mode_s cn52xx;
259+ struct cvmx_agl_gmx_inf_mode_s cn52xxp1;
260+ struct cvmx_agl_gmx_inf_mode_s cn56xx;
261+ struct cvmx_agl_gmx_inf_mode_s cn56xxp1;
262+};
263+
264+union cvmx_agl_gmx_prtx_cfg {
265+ uint64_t u64;
266+ struct cvmx_agl_gmx_prtx_cfg_s {
267+ uint64_t reserved_6_63:58;
268+ uint64_t tx_en:1;
269+ uint64_t rx_en:1;
270+ uint64_t slottime:1;
271+ uint64_t duplex:1;
272+ uint64_t speed:1;
273+ uint64_t en:1;
274+ } s;
275+ struct cvmx_agl_gmx_prtx_cfg_s cn52xx;
276+ struct cvmx_agl_gmx_prtx_cfg_s cn52xxp1;
277+ struct cvmx_agl_gmx_prtx_cfg_s cn56xx;
278+ struct cvmx_agl_gmx_prtx_cfg_s cn56xxp1;
279+};
280+
281+union cvmx_agl_gmx_rxx_adr_cam0 {
282+ uint64_t u64;
283+ struct cvmx_agl_gmx_rxx_adr_cam0_s {
284+ uint64_t adr:64;
285+ } s;
286+ struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xx;
287+ struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xxp1;
288+ struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xx;
289+ struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xxp1;
290+};
291+
292+union cvmx_agl_gmx_rxx_adr_cam1 {
293+ uint64_t u64;
294+ struct cvmx_agl_gmx_rxx_adr_cam1_s {
295+ uint64_t adr:64;
296+ } s;
297+ struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xx;
298+ struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xxp1;
299+ struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xx;
300+ struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xxp1;
301+};
302+
303+union cvmx_agl_gmx_rxx_adr_cam2 {
304+ uint64_t u64;
305+ struct cvmx_agl_gmx_rxx_adr_cam2_s {
306+ uint64_t adr:64;
307+ } s;
308+ struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xx;
309+ struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xxp1;
310+ struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xx;
311+ struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xxp1;
312+};
313+
314+union cvmx_agl_gmx_rxx_adr_cam3 {
315+ uint64_t u64;
316+ struct cvmx_agl_gmx_rxx_adr_cam3_s {
317+ uint64_t adr:64;
318+ } s;
319+ struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xx;
320+ struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xxp1;
321+ struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xx;
322+ struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xxp1;
323+};
324+
325+union cvmx_agl_gmx_rxx_adr_cam4 {
326+ uint64_t u64;
327+ struct cvmx_agl_gmx_rxx_adr_cam4_s {
328+ uint64_t adr:64;
329+ } s;
330+ struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xx;
331+ struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xxp1;
332+ struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xx;
333+ struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xxp1;
334+};
335+
336+union cvmx_agl_gmx_rxx_adr_cam5 {
337+ uint64_t u64;
338+ struct cvmx_agl_gmx_rxx_adr_cam5_s {
339+ uint64_t adr:64;
340+ } s;
341+ struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xx;
342+ struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xxp1;
343+ struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xx;
344+ struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xxp1;
345+};
346+
347+union cvmx_agl_gmx_rxx_adr_cam_en {
348+ uint64_t u64;
349+ struct cvmx_agl_gmx_rxx_adr_cam_en_s {
350+ uint64_t reserved_8_63:56;
351+ uint64_t en:8;
352+ } s;
353+ struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xx;
354+ struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xxp1;
355+ struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xx;
356+ struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xxp1;
357+};
358+
359+union cvmx_agl_gmx_rxx_adr_ctl {
360+ uint64_t u64;
361+ struct cvmx_agl_gmx_rxx_adr_ctl_s {
362+ uint64_t reserved_4_63:60;
363+ uint64_t cam_mode:1;
364+ uint64_t mcst:2;
365+ uint64_t bcst:1;
366+ } s;
367+ struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xx;
368+ struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xxp1;
369+ struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xx;
370+ struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xxp1;
371+};
372+
373+union cvmx_agl_gmx_rxx_decision {
374+ uint64_t u64;
375+ struct cvmx_agl_gmx_rxx_decision_s {
376+ uint64_t reserved_5_63:59;
377+ uint64_t cnt:5;
378+ } s;
379+ struct cvmx_agl_gmx_rxx_decision_s cn52xx;
380+ struct cvmx_agl_gmx_rxx_decision_s cn52xxp1;
381+ struct cvmx_agl_gmx_rxx_decision_s cn56xx;
382+ struct cvmx_agl_gmx_rxx_decision_s cn56xxp1;
383+};
384+
385+union cvmx_agl_gmx_rxx_frm_chk {
386+ uint64_t u64;
387+ struct cvmx_agl_gmx_rxx_frm_chk_s {
388+ uint64_t reserved_9_63:55;
389+ uint64_t skperr:1;
390+ uint64_t rcverr:1;
391+ uint64_t lenerr:1;
392+ uint64_t alnerr:1;
393+ uint64_t fcserr:1;
394+ uint64_t jabber:1;
395+ uint64_t maxerr:1;
396+ uint64_t reserved_1_1:1;
397+ uint64_t minerr:1;
398+ } s;
399+ struct cvmx_agl_gmx_rxx_frm_chk_s cn52xx;
400+ struct cvmx_agl_gmx_rxx_frm_chk_s cn52xxp1;
401+ struct cvmx_agl_gmx_rxx_frm_chk_s cn56xx;
402+ struct cvmx_agl_gmx_rxx_frm_chk_s cn56xxp1;
403+};
404+
405+union cvmx_agl_gmx_rxx_frm_ctl {
406+ uint64_t u64;
407+ struct cvmx_agl_gmx_rxx_frm_ctl_s {
408+ uint64_t reserved_10_63:54;
409+ uint64_t pre_align:1;
410+ uint64_t pad_len:1;
411+ uint64_t vlan_len:1;
412+ uint64_t pre_free:1;
413+ uint64_t ctl_smac:1;
414+ uint64_t ctl_mcst:1;
415+ uint64_t ctl_bck:1;
416+ uint64_t ctl_drp:1;
417+ uint64_t pre_strp:1;
418+ uint64_t pre_chk:1;
419+ } s;
420+ struct cvmx_agl_gmx_rxx_frm_ctl_s cn52xx;
421+ struct cvmx_agl_gmx_rxx_frm_ctl_s cn52xxp1;
422+ struct cvmx_agl_gmx_rxx_frm_ctl_s cn56xx;
423+ struct cvmx_agl_gmx_rxx_frm_ctl_s cn56xxp1;
424+};
425+
426+union cvmx_agl_gmx_rxx_frm_max {
427+ uint64_t u64;
428+ struct cvmx_agl_gmx_rxx_frm_max_s {
429+ uint64_t reserved_16_63:48;
430+ uint64_t len:16;
431+ } s;
432+ struct cvmx_agl_gmx_rxx_frm_max_s cn52xx;
433+ struct cvmx_agl_gmx_rxx_frm_max_s cn52xxp1;
434+ struct cvmx_agl_gmx_rxx_frm_max_s cn56xx;
435+ struct cvmx_agl_gmx_rxx_frm_max_s cn56xxp1;
436+};
437+
438+union cvmx_agl_gmx_rxx_frm_min {
439+ uint64_t u64;
440+ struct cvmx_agl_gmx_rxx_frm_min_s {
441+ uint64_t reserved_16_63:48;
442+ uint64_t len:16;
443+ } s;
444+ struct cvmx_agl_gmx_rxx_frm_min_s cn52xx;
445+ struct cvmx_agl_gmx_rxx_frm_min_s cn52xxp1;
446+ struct cvmx_agl_gmx_rxx_frm_min_s cn56xx;
447+ struct cvmx_agl_gmx_rxx_frm_min_s cn56xxp1;
448+};
449+
450+union cvmx_agl_gmx_rxx_ifg {
451+ uint64_t u64;
452+ struct cvmx_agl_gmx_rxx_ifg_s {
453+ uint64_t reserved_4_63:60;
454+ uint64_t ifg:4;
455+ } s;
456+ struct cvmx_agl_gmx_rxx_ifg_s cn52xx;
457+ struct cvmx_agl_gmx_rxx_ifg_s cn52xxp1;
458+ struct cvmx_agl_gmx_rxx_ifg_s cn56xx;
459+ struct cvmx_agl_gmx_rxx_ifg_s cn56xxp1;
460+};
461+
462+union cvmx_agl_gmx_rxx_int_en {
463+ uint64_t u64;
464+ struct cvmx_agl_gmx_rxx_int_en_s {
465+ uint64_t reserved_20_63:44;
466+ uint64_t pause_drp:1;
467+ uint64_t reserved_16_18:3;
468+ uint64_t ifgerr:1;
469+ uint64_t coldet:1;
470+ uint64_t falerr:1;
471+ uint64_t rsverr:1;
472+ uint64_t pcterr:1;
473+ uint64_t ovrerr:1;
474+ uint64_t reserved_9_9:1;
475+ uint64_t skperr:1;
476+ uint64_t rcverr:1;
477+ uint64_t lenerr:1;
478+ uint64_t alnerr:1;
479+ uint64_t fcserr:1;
480+ uint64_t jabber:1;
481+ uint64_t maxerr:1;
482+ uint64_t reserved_1_1:1;
483+ uint64_t minerr:1;
484+ } s;
485+ struct cvmx_agl_gmx_rxx_int_en_s cn52xx;
486+ struct cvmx_agl_gmx_rxx_int_en_s cn52xxp1;
487+ struct cvmx_agl_gmx_rxx_int_en_s cn56xx;
488+ struct cvmx_agl_gmx_rxx_int_en_s cn56xxp1;
489+};
490+
491+union cvmx_agl_gmx_rxx_int_reg {
492+ uint64_t u64;
493+ struct cvmx_agl_gmx_rxx_int_reg_s {
494+ uint64_t reserved_20_63:44;
495+ uint64_t pause_drp:1;
496+ uint64_t reserved_16_18:3;
497+ uint64_t ifgerr:1;
498+ uint64_t coldet:1;
499+ uint64_t falerr:1;
500+ uint64_t rsverr:1;
501+ uint64_t pcterr:1;
502+ uint64_t ovrerr:1;
503+ uint64_t reserved_9_9:1;
504+ uint64_t skperr:1;
505+ uint64_t rcverr:1;
506+ uint64_t lenerr:1;
507+ uint64_t alnerr:1;
508+ uint64_t fcserr:1;
509+ uint64_t jabber:1;
510+ uint64_t maxerr:1;
511+ uint64_t reserved_1_1:1;
512+ uint64_t minerr:1;
513+ } s;
514+ struct cvmx_agl_gmx_rxx_int_reg_s cn52xx;
515+ struct cvmx_agl_gmx_rxx_int_reg_s cn52xxp1;
516+ struct cvmx_agl_gmx_rxx_int_reg_s cn56xx;
517+ struct cvmx_agl_gmx_rxx_int_reg_s cn56xxp1;
518+};
519+
520+union cvmx_agl_gmx_rxx_jabber {
521+ uint64_t u64;
522+ struct cvmx_agl_gmx_rxx_jabber_s {
523+ uint64_t reserved_16_63:48;
524+ uint64_t cnt:16;
525+ } s;
526+ struct cvmx_agl_gmx_rxx_jabber_s cn52xx;
527+ struct cvmx_agl_gmx_rxx_jabber_s cn52xxp1;
528+ struct cvmx_agl_gmx_rxx_jabber_s cn56xx;
529+ struct cvmx_agl_gmx_rxx_jabber_s cn56xxp1;
530+};
531+
532+union cvmx_agl_gmx_rxx_pause_drop_time {
533+ uint64_t u64;
534+ struct cvmx_agl_gmx_rxx_pause_drop_time_s {
535+ uint64_t reserved_16_63:48;
536+ uint64_t status:16;
537+ } s;
538+ struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xx;
539+ struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xxp1;
540+ struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xx;
541+ struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xxp1;
542+};
543+
544+union cvmx_agl_gmx_rxx_stats_ctl {
545+ uint64_t u64;
546+ struct cvmx_agl_gmx_rxx_stats_ctl_s {
547+ uint64_t reserved_1_63:63;
548+ uint64_t rd_clr:1;
549+ } s;
550+ struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xx;
551+ struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xxp1;
552+ struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xx;
553+ struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xxp1;
554+};
555+
556+union cvmx_agl_gmx_rxx_stats_octs {
557+ uint64_t u64;
558+ struct cvmx_agl_gmx_rxx_stats_octs_s {
559+ uint64_t reserved_48_63:16;
560+ uint64_t cnt:48;
561+ } s;
562+ struct cvmx_agl_gmx_rxx_stats_octs_s cn52xx;
563+ struct cvmx_agl_gmx_rxx_stats_octs_s cn52xxp1;
564+ struct cvmx_agl_gmx_rxx_stats_octs_s cn56xx;
565+ struct cvmx_agl_gmx_rxx_stats_octs_s cn56xxp1;
566+};
567+
568+union cvmx_agl_gmx_rxx_stats_octs_ctl {
569+ uint64_t u64;
570+ struct cvmx_agl_gmx_rxx_stats_octs_ctl_s {
571+ uint64_t reserved_48_63:16;
572+ uint64_t cnt:48;
573+ } s;
574+ struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xx;
575+ struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xxp1;
576+ struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xx;
577+ struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xxp1;
578+};
579+
580+union cvmx_agl_gmx_rxx_stats_octs_dmac {
581+ uint64_t u64;
582+ struct cvmx_agl_gmx_rxx_stats_octs_dmac_s {
583+ uint64_t reserved_48_63:16;
584+ uint64_t cnt:48;
585+ } s;
586+ struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xx;
587+ struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xxp1;
588+ struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xx;
589+ struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xxp1;
590+};
591+
592+union cvmx_agl_gmx_rxx_stats_octs_drp {
593+ uint64_t u64;
594+ struct cvmx_agl_gmx_rxx_stats_octs_drp_s {
595+ uint64_t reserved_48_63:16;
596+ uint64_t cnt:48;
597+ } s;
598+ struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xx;
599+ struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xxp1;
600+ struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xx;
601+ struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xxp1;
602+};
603+
604+union cvmx_agl_gmx_rxx_stats_pkts {
605+ uint64_t u64;
606+ struct cvmx_agl_gmx_rxx_stats_pkts_s {
607+ uint64_t reserved_32_63:32;
608+ uint64_t cnt:32;
609+ } s;
610+ struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xx;
611+ struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xxp1;
612+ struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xx;
613+ struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xxp1;
614+};
615+
616+union cvmx_agl_gmx_rxx_stats_pkts_bad {
617+ uint64_t u64;
618+ struct cvmx_agl_gmx_rxx_stats_pkts_bad_s {
619+ uint64_t reserved_32_63:32;
620+ uint64_t cnt:32;
621+ } s;
622+ struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xx;
623+ struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xxp1;
624+ struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xx;
625+ struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xxp1;
626+};
627+
628+union cvmx_agl_gmx_rxx_stats_pkts_ctl {
629+ uint64_t u64;
630+ struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s {
631+ uint64_t reserved_32_63:32;
632+ uint64_t cnt:32;
633+ } s;
634+ struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xx;
635+ struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xxp1;
636+ struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xx;
637+ struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xxp1;
638+};
639+
640+union cvmx_agl_gmx_rxx_stats_pkts_dmac {
641+ uint64_t u64;
642+ struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s {
643+ uint64_t reserved_32_63:32;
644+ uint64_t cnt:32;
645+ } s;
646+ struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xx;
647+ struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xxp1;
648+ struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xx;
649+ struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xxp1;
650+};
651+
652+union cvmx_agl_gmx_rxx_stats_pkts_drp {
653+ uint64_t u64;
654+ struct cvmx_agl_gmx_rxx_stats_pkts_drp_s {
655+ uint64_t reserved_32_63:32;
656+ uint64_t cnt:32;
657+ } s;
658+ struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xx;
659+ struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xxp1;
660+ struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xx;
661+ struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xxp1;
662+};
663+
664+union cvmx_agl_gmx_rxx_udd_skp {
665+ uint64_t u64;
666+ struct cvmx_agl_gmx_rxx_udd_skp_s {
667+ uint64_t reserved_9_63:55;
668+ uint64_t fcssel:1;
669+ uint64_t reserved_7_7:1;
670+ uint64_t len:7;
671+ } s;
672+ struct cvmx_agl_gmx_rxx_udd_skp_s cn52xx;
673+ struct cvmx_agl_gmx_rxx_udd_skp_s cn52xxp1;
674+ struct cvmx_agl_gmx_rxx_udd_skp_s cn56xx;
675+ struct cvmx_agl_gmx_rxx_udd_skp_s cn56xxp1;
676+};
677+
678+union cvmx_agl_gmx_rx_bp_dropx {
679+ uint64_t u64;
680+ struct cvmx_agl_gmx_rx_bp_dropx_s {
681+ uint64_t reserved_6_63:58;
682+ uint64_t mark:6;
683+ } s;
684+ struct cvmx_agl_gmx_rx_bp_dropx_s cn52xx;
685+ struct cvmx_agl_gmx_rx_bp_dropx_s cn52xxp1;
686+ struct cvmx_agl_gmx_rx_bp_dropx_s cn56xx;
687+ struct cvmx_agl_gmx_rx_bp_dropx_s cn56xxp1;
688+};
689+
690+union cvmx_agl_gmx_rx_bp_offx {
691+ uint64_t u64;
692+ struct cvmx_agl_gmx_rx_bp_offx_s {
693+ uint64_t reserved_6_63:58;
694+ uint64_t mark:6;
695+ } s;
696+ struct cvmx_agl_gmx_rx_bp_offx_s cn52xx;
697+ struct cvmx_agl_gmx_rx_bp_offx_s cn52xxp1;
698+ struct cvmx_agl_gmx_rx_bp_offx_s cn56xx;
699+ struct cvmx_agl_gmx_rx_bp_offx_s cn56xxp1;
700+};
701+
702+union cvmx_agl_gmx_rx_bp_onx {
703+ uint64_t u64;
704+ struct cvmx_agl_gmx_rx_bp_onx_s {
705+ uint64_t reserved_9_63:55;
706+ uint64_t mark:9;
707+ } s;
708+ struct cvmx_agl_gmx_rx_bp_onx_s cn52xx;
709+ struct cvmx_agl_gmx_rx_bp_onx_s cn52xxp1;
710+ struct cvmx_agl_gmx_rx_bp_onx_s cn56xx;
711+ struct cvmx_agl_gmx_rx_bp_onx_s cn56xxp1;
712+};
713+
714+union cvmx_agl_gmx_rx_prt_info {
715+ uint64_t u64;
716+ struct cvmx_agl_gmx_rx_prt_info_s {
717+ uint64_t reserved_18_63:46;
718+ uint64_t drop:2;
719+ uint64_t reserved_2_15:14;
720+ uint64_t commit:2;
721+ } s;
722+ struct cvmx_agl_gmx_rx_prt_info_s cn52xx;
723+ struct cvmx_agl_gmx_rx_prt_info_s cn52xxp1;
724+ struct cvmx_agl_gmx_rx_prt_info_cn56xx {
725+ uint64_t reserved_17_63:47;
726+ uint64_t drop:1;
727+ uint64_t reserved_1_15:15;
728+ uint64_t commit:1;
729+ } cn56xx;
730+ struct cvmx_agl_gmx_rx_prt_info_cn56xx cn56xxp1;
731+};
732+
733+union cvmx_agl_gmx_rx_tx_status {
734+ uint64_t u64;
735+ struct cvmx_agl_gmx_rx_tx_status_s {
736+ uint64_t reserved_6_63:58;
737+ uint64_t tx:2;
738+ uint64_t reserved_2_3:2;
739+ uint64_t rx:2;
740+ } s;
741+ struct cvmx_agl_gmx_rx_tx_status_s cn52xx;
742+ struct cvmx_agl_gmx_rx_tx_status_s cn52xxp1;
743+ struct cvmx_agl_gmx_rx_tx_status_cn56xx {
744+ uint64_t reserved_5_63:59;
745+ uint64_t tx:1;
746+ uint64_t reserved_1_3:3;
747+ uint64_t rx:1;
748+ } cn56xx;
749+ struct cvmx_agl_gmx_rx_tx_status_cn56xx cn56xxp1;
750+};
751+
752+union cvmx_agl_gmx_smacx {
753+ uint64_t u64;
754+ struct cvmx_agl_gmx_smacx_s {
755+ uint64_t reserved_48_63:16;
756+ uint64_t smac:48;
757+ } s;
758+ struct cvmx_agl_gmx_smacx_s cn52xx;
759+ struct cvmx_agl_gmx_smacx_s cn52xxp1;
760+ struct cvmx_agl_gmx_smacx_s cn56xx;
761+ struct cvmx_agl_gmx_smacx_s cn56xxp1;
762+};
763+
764+union cvmx_agl_gmx_stat_bp {
765+ uint64_t u64;
766+ struct cvmx_agl_gmx_stat_bp_s {
767+ uint64_t reserved_17_63:47;
768+ uint64_t bp:1;
769+ uint64_t cnt:16;
770+ } s;
771+ struct cvmx_agl_gmx_stat_bp_s cn52xx;
772+ struct cvmx_agl_gmx_stat_bp_s cn52xxp1;
773+ struct cvmx_agl_gmx_stat_bp_s cn56xx;
774+ struct cvmx_agl_gmx_stat_bp_s cn56xxp1;
775+};
776+
777+union cvmx_agl_gmx_txx_append {
778+ uint64_t u64;
779+ struct cvmx_agl_gmx_txx_append_s {
780+ uint64_t reserved_4_63:60;
781+ uint64_t force_fcs:1;
782+ uint64_t fcs:1;
783+ uint64_t pad:1;
784+ uint64_t preamble:1;
785+ } s;
786+ struct cvmx_agl_gmx_txx_append_s cn52xx;
787+ struct cvmx_agl_gmx_txx_append_s cn52xxp1;
788+ struct cvmx_agl_gmx_txx_append_s cn56xx;
789+ struct cvmx_agl_gmx_txx_append_s cn56xxp1;
790+};
791+
792+union cvmx_agl_gmx_txx_ctl {
793+ uint64_t u64;
794+ struct cvmx_agl_gmx_txx_ctl_s {
795+ uint64_t reserved_2_63:62;
796+ uint64_t xsdef_en:1;
797+ uint64_t xscol_en:1;
798+ } s;
799+ struct cvmx_agl_gmx_txx_ctl_s cn52xx;
800+ struct cvmx_agl_gmx_txx_ctl_s cn52xxp1;
801+ struct cvmx_agl_gmx_txx_ctl_s cn56xx;
802+ struct cvmx_agl_gmx_txx_ctl_s cn56xxp1;
803+};
804+
805+union cvmx_agl_gmx_txx_min_pkt {
806+ uint64_t u64;
807+ struct cvmx_agl_gmx_txx_min_pkt_s {
808+ uint64_t reserved_8_63:56;
809+ uint64_t min_size:8;
810+ } s;
811+ struct cvmx_agl_gmx_txx_min_pkt_s cn52xx;
812+ struct cvmx_agl_gmx_txx_min_pkt_s cn52xxp1;
813+ struct cvmx_agl_gmx_txx_min_pkt_s cn56xx;
814+ struct cvmx_agl_gmx_txx_min_pkt_s cn56xxp1;
815+};
816+
817+union cvmx_agl_gmx_txx_pause_pkt_interval {
818+ uint64_t u64;
819+ struct cvmx_agl_gmx_txx_pause_pkt_interval_s {
820+ uint64_t reserved_16_63:48;
821+ uint64_t interval:16;
822+ } s;
823+ struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xx;
824+ struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xxp1;
825+ struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xx;
826+ struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xxp1;
827+};
828+
829+union cvmx_agl_gmx_txx_pause_pkt_time {
830+ uint64_t u64;
831+ struct cvmx_agl_gmx_txx_pause_pkt_time_s {
832+ uint64_t reserved_16_63:48;
833+ uint64_t time:16;
834+ } s;
835+ struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xx;
836+ struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xxp1;
837+ struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xx;
838+ struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xxp1;
839+};
840+
841+union cvmx_agl_gmx_txx_pause_togo {
842+ uint64_t u64;
843+ struct cvmx_agl_gmx_txx_pause_togo_s {
844+ uint64_t reserved_16_63:48;
845+ uint64_t time:16;
846+ } s;
847+ struct cvmx_agl_gmx_txx_pause_togo_s cn52xx;
848+ struct cvmx_agl_gmx_txx_pause_togo_s cn52xxp1;
849+ struct cvmx_agl_gmx_txx_pause_togo_s cn56xx;
850+ struct cvmx_agl_gmx_txx_pause_togo_s cn56xxp1;
851+};
852+
853+union cvmx_agl_gmx_txx_pause_zero {
854+ uint64_t u64;
855+ struct cvmx_agl_gmx_txx_pause_zero_s {
856+ uint64_t reserved_1_63:63;
857+ uint64_t send:1;
858+ } s;
859+ struct cvmx_agl_gmx_txx_pause_zero_s cn52xx;
860+ struct cvmx_agl_gmx_txx_pause_zero_s cn52xxp1;
861+ struct cvmx_agl_gmx_txx_pause_zero_s cn56xx;
862+ struct cvmx_agl_gmx_txx_pause_zero_s cn56xxp1;
863+};
864+
865+union cvmx_agl_gmx_txx_soft_pause {
866+ uint64_t u64;
867+ struct cvmx_agl_gmx_txx_soft_pause_s {
868+ uint64_t reserved_16_63:48;
869+ uint64_t time:16;
870+ } s;
871+ struct cvmx_agl_gmx_txx_soft_pause_s cn52xx;
872+ struct cvmx_agl_gmx_txx_soft_pause_s cn52xxp1;
873+ struct cvmx_agl_gmx_txx_soft_pause_s cn56xx;
874+ struct cvmx_agl_gmx_txx_soft_pause_s cn56xxp1;
875+};
876+
877+union cvmx_agl_gmx_txx_stat0 {
878+ uint64_t u64;
879+ struct cvmx_agl_gmx_txx_stat0_s {
880+ uint64_t xsdef:32;
881+ uint64_t xscol:32;
882+ } s;
883+ struct cvmx_agl_gmx_txx_stat0_s cn52xx;
884+ struct cvmx_agl_gmx_txx_stat0_s cn52xxp1;
885+ struct cvmx_agl_gmx_txx_stat0_s cn56xx;
886+ struct cvmx_agl_gmx_txx_stat0_s cn56xxp1;
887+};
888+
889+union cvmx_agl_gmx_txx_stat1 {
890+ uint64_t u64;
891+ struct cvmx_agl_gmx_txx_stat1_s {
892+ uint64_t scol:32;
893+ uint64_t mcol:32;
894+ } s;
895+ struct cvmx_agl_gmx_txx_stat1_s cn52xx;
896+ struct cvmx_agl_gmx_txx_stat1_s cn52xxp1;
897+ struct cvmx_agl_gmx_txx_stat1_s cn56xx;
898+ struct cvmx_agl_gmx_txx_stat1_s cn56xxp1;
899+};
900+
901+union cvmx_agl_gmx_txx_stat2 {
902+ uint64_t u64;
903+ struct cvmx_agl_gmx_txx_stat2_s {
904+ uint64_t reserved_48_63:16;
905+ uint64_t octs:48;
906+ } s;
907+ struct cvmx_agl_gmx_txx_stat2_s cn52xx;
908+ struct cvmx_agl_gmx_txx_stat2_s cn52xxp1;
909+ struct cvmx_agl_gmx_txx_stat2_s cn56xx;
910+ struct cvmx_agl_gmx_txx_stat2_s cn56xxp1;
911+};
912+
913+union cvmx_agl_gmx_txx_stat3 {
914+ uint64_t u64;
915+ struct cvmx_agl_gmx_txx_stat3_s {
916+ uint64_t reserved_32_63:32;
917+ uint64_t pkts:32;
918+ } s;
919+ struct cvmx_agl_gmx_txx_stat3_s cn52xx;
920+ struct cvmx_agl_gmx_txx_stat3_s cn52xxp1;
921+ struct cvmx_agl_gmx_txx_stat3_s cn56xx;
922+ struct cvmx_agl_gmx_txx_stat3_s cn56xxp1;
923+};
924+
925+union cvmx_agl_gmx_txx_stat4 {
926+ uint64_t u64;
927+ struct cvmx_agl_gmx_txx_stat4_s {
928+ uint64_t hist1:32;
929+ uint64_t hist0:32;
930+ } s;
931+ struct cvmx_agl_gmx_txx_stat4_s cn52xx;
932+ struct cvmx_agl_gmx_txx_stat4_s cn52xxp1;
933+ struct cvmx_agl_gmx_txx_stat4_s cn56xx;
934+ struct cvmx_agl_gmx_txx_stat4_s cn56xxp1;
935+};
936+
937+union cvmx_agl_gmx_txx_stat5 {
938+ uint64_t u64;
939+ struct cvmx_agl_gmx_txx_stat5_s {
940+ uint64_t hist3:32;
941+ uint64_t hist2:32;
942+ } s;
943+ struct cvmx_agl_gmx_txx_stat5_s cn52xx;
944+ struct cvmx_agl_gmx_txx_stat5_s cn52xxp1;
945+ struct cvmx_agl_gmx_txx_stat5_s cn56xx;
946+ struct cvmx_agl_gmx_txx_stat5_s cn56xxp1;
947+};
948+
949+union cvmx_agl_gmx_txx_stat6 {
950+ uint64_t u64;
951+ struct cvmx_agl_gmx_txx_stat6_s {
952+ uint64_t hist5:32;
953+ uint64_t hist4:32;
954+ } s;
955+ struct cvmx_agl_gmx_txx_stat6_s cn52xx;
956+ struct cvmx_agl_gmx_txx_stat6_s cn52xxp1;
957+ struct cvmx_agl_gmx_txx_stat6_s cn56xx;
958+ struct cvmx_agl_gmx_txx_stat6_s cn56xxp1;
959+};
960+
961+union cvmx_agl_gmx_txx_stat7 {
962+ uint64_t u64;
963+ struct cvmx_agl_gmx_txx_stat7_s {
964+ uint64_t hist7:32;
965+ uint64_t hist6:32;
966+ } s;
967+ struct cvmx_agl_gmx_txx_stat7_s cn52xx;
968+ struct cvmx_agl_gmx_txx_stat7_s cn52xxp1;
969+ struct cvmx_agl_gmx_txx_stat7_s cn56xx;
970+ struct cvmx_agl_gmx_txx_stat7_s cn56xxp1;
971+};
972+
973+union cvmx_agl_gmx_txx_stat8 {
974+ uint64_t u64;
975+ struct cvmx_agl_gmx_txx_stat8_s {
976+ uint64_t mcst:32;
977+ uint64_t bcst:32;
978+ } s;
979+ struct cvmx_agl_gmx_txx_stat8_s cn52xx;
980+ struct cvmx_agl_gmx_txx_stat8_s cn52xxp1;
981+ struct cvmx_agl_gmx_txx_stat8_s cn56xx;
982+ struct cvmx_agl_gmx_txx_stat8_s cn56xxp1;
983+};
984+
985+union cvmx_agl_gmx_txx_stat9 {
986+ uint64_t u64;
987+ struct cvmx_agl_gmx_txx_stat9_s {
988+ uint64_t undflw:32;
989+ uint64_t ctl:32;
990+ } s;
991+ struct cvmx_agl_gmx_txx_stat9_s cn52xx;
992+ struct cvmx_agl_gmx_txx_stat9_s cn52xxp1;
993+ struct cvmx_agl_gmx_txx_stat9_s cn56xx;
994+ struct cvmx_agl_gmx_txx_stat9_s cn56xxp1;
995+};
996+
997+union cvmx_agl_gmx_txx_stats_ctl {
998+ uint64_t u64;
999+ struct cvmx_agl_gmx_txx_stats_ctl_s {
1000+ uint64_t reserved_1_63:63;
1001+ uint64_t rd_clr:1;
1002+ } s;
1003+ struct cvmx_agl_gmx_txx_stats_ctl_s cn52xx;
1004+ struct cvmx_agl_gmx_txx_stats_ctl_s cn52xxp1;
1005+ struct cvmx_agl_gmx_txx_stats_ctl_s cn56xx;
1006+ struct cvmx_agl_gmx_txx_stats_ctl_s cn56xxp1;
1007+};
1008+
1009+union cvmx_agl_gmx_txx_thresh {
1010+ uint64_t u64;
1011+ struct cvmx_agl_gmx_txx_thresh_s {
1012+ uint64_t reserved_6_63:58;
1013+ uint64_t cnt:6;
1014+ } s;
1015+ struct cvmx_agl_gmx_txx_thresh_s cn52xx;
1016+ struct cvmx_agl_gmx_txx_thresh_s cn52xxp1;
1017+ struct cvmx_agl_gmx_txx_thresh_s cn56xx;
1018+ struct cvmx_agl_gmx_txx_thresh_s cn56xxp1;
1019+};
1020+
1021+union cvmx_agl_gmx_tx_bp {
1022+ uint64_t u64;
1023+ struct cvmx_agl_gmx_tx_bp_s {
1024+ uint64_t reserved_2_63:62;
1025+ uint64_t bp:2;
1026+ } s;
1027+ struct cvmx_agl_gmx_tx_bp_s cn52xx;
1028+ struct cvmx_agl_gmx_tx_bp_s cn52xxp1;
1029+ struct cvmx_agl_gmx_tx_bp_cn56xx {
1030+ uint64_t reserved_1_63:63;
1031+ uint64_t bp:1;
1032+ } cn56xx;
1033+ struct cvmx_agl_gmx_tx_bp_cn56xx cn56xxp1;
1034+};
1035+
1036+union cvmx_agl_gmx_tx_col_attempt {
1037+ uint64_t u64;
1038+ struct cvmx_agl_gmx_tx_col_attempt_s {
1039+ uint64_t reserved_5_63:59;
1040+ uint64_t limit:5;
1041+ } s;
1042+ struct cvmx_agl_gmx_tx_col_attempt_s cn52xx;
1043+ struct cvmx_agl_gmx_tx_col_attempt_s cn52xxp1;
1044+ struct cvmx_agl_gmx_tx_col_attempt_s cn56xx;
1045+ struct cvmx_agl_gmx_tx_col_attempt_s cn56xxp1;
1046+};
1047+
1048+union cvmx_agl_gmx_tx_ifg {
1049+ uint64_t u64;
1050+ struct cvmx_agl_gmx_tx_ifg_s {
1051+ uint64_t reserved_8_63:56;
1052+ uint64_t ifg2:4;
1053+ uint64_t ifg1:4;
1054+ } s;
1055+ struct cvmx_agl_gmx_tx_ifg_s cn52xx;
1056+ struct cvmx_agl_gmx_tx_ifg_s cn52xxp1;
1057+ struct cvmx_agl_gmx_tx_ifg_s cn56xx;
1058+ struct cvmx_agl_gmx_tx_ifg_s cn56xxp1;
1059+};
1060+
1061+union cvmx_agl_gmx_tx_int_en {
1062+ uint64_t u64;
1063+ struct cvmx_agl_gmx_tx_int_en_s {
1064+ uint64_t reserved_18_63:46;
1065+ uint64_t late_col:2;
1066+ uint64_t reserved_14_15:2;
1067+ uint64_t xsdef:2;
1068+ uint64_t reserved_10_11:2;
1069+ uint64_t xscol:2;
1070+ uint64_t reserved_4_7:4;
1071+ uint64_t undflw:2;
1072+ uint64_t reserved_1_1:1;
1073+ uint64_t pko_nxa:1;
1074+ } s;
1075+ struct cvmx_agl_gmx_tx_int_en_s cn52xx;
1076+ struct cvmx_agl_gmx_tx_int_en_s cn52xxp1;
1077+ struct cvmx_agl_gmx_tx_int_en_cn56xx {
1078+ uint64_t reserved_17_63:47;
1079+ uint64_t late_col:1;
1080+ uint64_t reserved_13_15:3;
1081+ uint64_t xsdef:1;
1082+ uint64_t reserved_9_11:3;
1083+ uint64_t xscol:1;
1084+ uint64_t reserved_3_7:5;
1085+ uint64_t undflw:1;
1086+ uint64_t reserved_1_1:1;
1087+ uint64_t pko_nxa:1;
1088+ } cn56xx;
1089+ struct cvmx_agl_gmx_tx_int_en_cn56xx cn56xxp1;
1090+};
1091+
1092+union cvmx_agl_gmx_tx_int_reg {
1093+ uint64_t u64;
1094+ struct cvmx_agl_gmx_tx_int_reg_s {
1095+ uint64_t reserved_18_63:46;
1096+ uint64_t late_col:2;
1097+ uint64_t reserved_14_15:2;
1098+ uint64_t xsdef:2;
1099+ uint64_t reserved_10_11:2;
1100+ uint64_t xscol:2;
1101+ uint64_t reserved_4_7:4;
1102+ uint64_t undflw:2;
1103+ uint64_t reserved_1_1:1;
1104+ uint64_t pko_nxa:1;
1105+ } s;
1106+ struct cvmx_agl_gmx_tx_int_reg_s cn52xx;
1107+ struct cvmx_agl_gmx_tx_int_reg_s cn52xxp1;
1108+ struct cvmx_agl_gmx_tx_int_reg_cn56xx {
1109+ uint64_t reserved_17_63:47;
1110+ uint64_t late_col:1;
1111+ uint64_t reserved_13_15:3;
1112+ uint64_t xsdef:1;
1113+ uint64_t reserved_9_11:3;
1114+ uint64_t xscol:1;
1115+ uint64_t reserved_3_7:5;
1116+ uint64_t undflw:1;
1117+ uint64_t reserved_1_1:1;
1118+ uint64_t pko_nxa:1;
1119+ } cn56xx;
1120+ struct cvmx_agl_gmx_tx_int_reg_cn56xx cn56xxp1;
1121+};
1122+
1123+union cvmx_agl_gmx_tx_jam {
1124+ uint64_t u64;
1125+ struct cvmx_agl_gmx_tx_jam_s {
1126+ uint64_t reserved_8_63:56;
1127+ uint64_t jam:8;
1128+ } s;
1129+ struct cvmx_agl_gmx_tx_jam_s cn52xx;
1130+ struct cvmx_agl_gmx_tx_jam_s cn52xxp1;
1131+ struct cvmx_agl_gmx_tx_jam_s cn56xx;
1132+ struct cvmx_agl_gmx_tx_jam_s cn56xxp1;
1133+};
1134+
1135+union cvmx_agl_gmx_tx_lfsr {
1136+ uint64_t u64;
1137+ struct cvmx_agl_gmx_tx_lfsr_s {
1138+ uint64_t reserved_16_63:48;
1139+ uint64_t lfsr:16;
1140+ } s;
1141+ struct cvmx_agl_gmx_tx_lfsr_s cn52xx;
1142+ struct cvmx_agl_gmx_tx_lfsr_s cn52xxp1;
1143+ struct cvmx_agl_gmx_tx_lfsr_s cn56xx;
1144+ struct cvmx_agl_gmx_tx_lfsr_s cn56xxp1;
1145+};
1146+
1147+union cvmx_agl_gmx_tx_ovr_bp {
1148+ uint64_t u64;
1149+ struct cvmx_agl_gmx_tx_ovr_bp_s {
1150+ uint64_t reserved_10_63:54;
1151+ uint64_t en:2;
1152+ uint64_t reserved_6_7:2;
1153+ uint64_t bp:2;
1154+ uint64_t reserved_2_3:2;
1155+ uint64_t ign_full:2;
1156+ } s;
1157+ struct cvmx_agl_gmx_tx_ovr_bp_s cn52xx;
1158+ struct cvmx_agl_gmx_tx_ovr_bp_s cn52xxp1;
1159+ struct cvmx_agl_gmx_tx_ovr_bp_cn56xx {
1160+ uint64_t reserved_9_63:55;
1161+ uint64_t en:1;
1162+ uint64_t reserved_5_7:3;
1163+ uint64_t bp:1;
1164+ uint64_t reserved_1_3:3;
1165+ uint64_t ign_full:1;
1166+ } cn56xx;
1167+ struct cvmx_agl_gmx_tx_ovr_bp_cn56xx cn56xxp1;
1168+};
1169+
1170+union cvmx_agl_gmx_tx_pause_pkt_dmac {
1171+ uint64_t u64;
1172+ struct cvmx_agl_gmx_tx_pause_pkt_dmac_s {
1173+ uint64_t reserved_48_63:16;
1174+ uint64_t dmac:48;
1175+ } s;
1176+ struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xx;
1177+ struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xxp1;
1178+ struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xx;
1179+ struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xxp1;
1180+};
1181+
1182+union cvmx_agl_gmx_tx_pause_pkt_type {
1183+ uint64_t u64;
1184+ struct cvmx_agl_gmx_tx_pause_pkt_type_s {
1185+ uint64_t reserved_16_63:48;
1186+ uint64_t type:16;
1187+ } s;
1188+ struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xx;
1189+ struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xxp1;
1190+ struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xx;
1191+ struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xxp1;
1192+};
1193+
1194+#endif
arch/mips/include/asm/octeon/cvmx-mixx-defs.h+248−0
@@ -0,0 +1,248 @@
1+/***********************license start***************
2+ * Author: Cavium Networks
3+ *
4+ * Contact: support@caviumnetworks.com
5+ * This file is part of the OCTEON SDK
6+ *
7+ * Copyright (c) 2003-2008 Cavium Networks
8+ *
9+ * This file is free software; you can redistribute it and/or modify
10+ * it under the terms of the GNU General Public License, Version 2, as
11+ * published by the Free Software Foundation.
12+ *
13+ * This file is distributed in the hope that it will be useful, but
14+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16+ * NONINFRINGEMENT. See the GNU General Public License for more
17+ * details.
18+ *
19+ * You should have received a copy of the GNU General Public License
20+ * along with this file; if not, write to the Free Software
21+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22+ * or visit http://www.gnu.org/licenses/.
23+ *
24+ * This file may also be available under a different license from Cavium.
25+ * Contact Cavium Networks for more information
26+ ***********************license end**************************************/
27+
28+#ifndef __CVMX_MIXX_DEFS_H__
29+#define __CVMX_MIXX_DEFS_H__
30+
31+#define CVMX_MIXX_BIST(offset) \
32+ CVMX_ADD_IO_SEG(0x0001070000100078ull + (((offset) & 1) * 2048))
33+#define CVMX_MIXX_CTL(offset) \
34+ CVMX_ADD_IO_SEG(0x0001070000100020ull + (((offset) & 1) * 2048))
35+#define CVMX_MIXX_INTENA(offset) \
36+ CVMX_ADD_IO_SEG(0x0001070000100050ull + (((offset) & 1) * 2048))
37+#define CVMX_MIXX_IRCNT(offset) \
38+ CVMX_ADD_IO_SEG(0x0001070000100030ull + (((offset) & 1) * 2048))
39+#define CVMX_MIXX_IRHWM(offset) \
40+ CVMX_ADD_IO_SEG(0x0001070000100028ull + (((offset) & 1) * 2048))
41+#define CVMX_MIXX_IRING1(offset) \
42+ CVMX_ADD_IO_SEG(0x0001070000100010ull + (((offset) & 1) * 2048))
43+#define CVMX_MIXX_IRING2(offset) \
44+ CVMX_ADD_IO_SEG(0x0001070000100018ull + (((offset) & 1) * 2048))
45+#define CVMX_MIXX_ISR(offset) \
46+ CVMX_ADD_IO_SEG(0x0001070000100048ull + (((offset) & 1) * 2048))
47+#define CVMX_MIXX_ORCNT(offset) \
48+ CVMX_ADD_IO_SEG(0x0001070000100040ull + (((offset) & 1) * 2048))
49+#define CVMX_MIXX_ORHWM(offset) \
50+ CVMX_ADD_IO_SEG(0x0001070000100038ull + (((offset) & 1) * 2048))
51+#define CVMX_MIXX_ORING1(offset) \
52+ CVMX_ADD_IO_SEG(0x0001070000100000ull + (((offset) & 1) * 2048))
53+#define CVMX_MIXX_ORING2(offset) \
54+ CVMX_ADD_IO_SEG(0x0001070000100008ull + (((offset) & 1) * 2048))
55+#define CVMX_MIXX_REMCNT(offset) \
56+ CVMX_ADD_IO_SEG(0x0001070000100058ull + (((offset) & 1) * 2048))
57+
58+union cvmx_mixx_bist {
59+ uint64_t u64;
60+ struct cvmx_mixx_bist_s {
61+ uint64_t reserved_4_63:60;
62+ uint64_t mrqdat:1;
63+ uint64_t ipfdat:1;
64+ uint64_t irfdat:1;
65+ uint64_t orfdat:1;
66+ } s;
67+ struct cvmx_mixx_bist_s cn52xx;
68+ struct cvmx_mixx_bist_s cn52xxp1;
69+ struct cvmx_mixx_bist_s cn56xx;
70+ struct cvmx_mixx_bist_s cn56xxp1;
71+};
72+
73+union cvmx_mixx_ctl {
74+ uint64_t u64;
75+ struct cvmx_mixx_ctl_s {
76+ uint64_t reserved_8_63:56;
77+ uint64_t crc_strip:1;
78+ uint64_t busy:1;
79+ uint64_t en:1;
80+ uint64_t reset:1;
81+ uint64_t lendian:1;
82+ uint64_t nbtarb:1;
83+ uint64_t mrq_hwm:2;
84+ } s;
85+ struct cvmx_mixx_ctl_s cn52xx;
86+ struct cvmx_mixx_ctl_s cn52xxp1;
87+ struct cvmx_mixx_ctl_s cn56xx;
88+ struct cvmx_mixx_ctl_s cn56xxp1;
89+};
90+
91+union cvmx_mixx_intena {
92+ uint64_t u64;
93+ struct cvmx_mixx_intena_s {
94+ uint64_t reserved_7_63:57;
95+ uint64_t orunena:1;
96+ uint64_t irunena:1;
97+ uint64_t data_drpena:1;
98+ uint64_t ithena:1;
99+ uint64_t othena:1;
100+ uint64_t ivfena:1;
101+ uint64_t ovfena:1;
102+ } s;
103+ struct cvmx_mixx_intena_s cn52xx;
104+ struct cvmx_mixx_intena_s cn52xxp1;
105+ struct cvmx_mixx_intena_s cn56xx;
106+ struct cvmx_mixx_intena_s cn56xxp1;
107+};
108+
109+union cvmx_mixx_ircnt {
110+ uint64_t u64;
111+ struct cvmx_mixx_ircnt_s {
112+ uint64_t reserved_20_63:44;
113+ uint64_t ircnt:20;
114+ } s;
115+ struct cvmx_mixx_ircnt_s cn52xx;
116+ struct cvmx_mixx_ircnt_s cn52xxp1;
117+ struct cvmx_mixx_ircnt_s cn56xx;
118+ struct cvmx_mixx_ircnt_s cn56xxp1;
119+};
120+
121+union cvmx_mixx_irhwm {
122+ uint64_t u64;
123+ struct cvmx_mixx_irhwm_s {
124+ uint64_t reserved_40_63:24;
125+ uint64_t ibplwm:20;
126+ uint64_t irhwm:20;
127+ } s;
128+ struct cvmx_mixx_irhwm_s cn52xx;
129+ struct cvmx_mixx_irhwm_s cn52xxp1;
130+ struct cvmx_mixx_irhwm_s cn56xx;
131+ struct cvmx_mixx_irhwm_s cn56xxp1;
132+};
133+
134+union cvmx_mixx_iring1 {
135+ uint64_t u64;
136+ struct cvmx_mixx_iring1_s {
137+ uint64_t reserved_60_63:4;
138+ uint64_t isize:20;
139+ uint64_t reserved_36_39:4;
140+ uint64_t ibase:33;
141+ uint64_t reserved_0_2:3;
142+ } s;
143+ struct cvmx_mixx_iring1_s cn52xx;
144+ struct cvmx_mixx_iring1_s cn52xxp1;
145+ struct cvmx_mixx_iring1_s cn56xx;
146+ struct cvmx_mixx_iring1_s cn56xxp1;
147+};
148+
149+union cvmx_mixx_iring2 {
150+ uint64_t u64;
151+ struct cvmx_mixx_iring2_s {
152+ uint64_t reserved_52_63:12;
153+ uint64_t itlptr:20;
154+ uint64_t reserved_20_31:12;
155+ uint64_t idbell:20;
156+ } s;
157+ struct cvmx_mixx_iring2_s cn52xx;
158+ struct cvmx_mixx_iring2_s cn52xxp1;
159+ struct cvmx_mixx_iring2_s cn56xx;
160+ struct cvmx_mixx_iring2_s cn56xxp1;
161+};
162+
163+union cvmx_mixx_isr {
164+ uint64_t u64;
165+ struct cvmx_mixx_isr_s {
166+ uint64_t reserved_7_63:57;
167+ uint64_t orun:1;
168+ uint64_t irun:1;
169+ uint64_t data_drp:1;
170+ uint64_t irthresh:1;
171+ uint64_t orthresh:1;
172+ uint64_t idblovf:1;
173+ uint64_t odblovf:1;
174+ } s;
175+ struct cvmx_mixx_isr_s cn52xx;
176+ struct cvmx_mixx_isr_s cn52xxp1;
177+ struct cvmx_mixx_isr_s cn56xx;
178+ struct cvmx_mixx_isr_s cn56xxp1;
179+};
180+
181+union cvmx_mixx_orcnt {
182+ uint64_t u64;
183+ struct cvmx_mixx_orcnt_s {
184+ uint64_t reserved_20_63:44;
185+ uint64_t orcnt:20;
186+ } s;
187+ struct cvmx_mixx_orcnt_s cn52xx;
188+ struct cvmx_mixx_orcnt_s cn52xxp1;
189+ struct cvmx_mixx_orcnt_s cn56xx;
190+ struct cvmx_mixx_orcnt_s cn56xxp1;
191+};
192+
193+union cvmx_mixx_orhwm {
194+ uint64_t u64;
195+ struct cvmx_mixx_orhwm_s {
196+ uint64_t reserved_20_63:44;
197+ uint64_t orhwm:20;
198+ } s;
199+ struct cvmx_mixx_orhwm_s cn52xx;
200+ struct cvmx_mixx_orhwm_s cn52xxp1;
201+ struct cvmx_mixx_orhwm_s cn56xx;
202+ struct cvmx_mixx_orhwm_s cn56xxp1;
203+};
204+
205+union cvmx_mixx_oring1 {
206+ uint64_t u64;
207+ struct cvmx_mixx_oring1_s {
208+ uint64_t reserved_60_63:4;
209+ uint64_t osize:20;
210+ uint64_t reserved_36_39:4;
211+ uint64_t obase:33;
212+ uint64_t reserved_0_2:3;
213+ } s;
214+ struct cvmx_mixx_oring1_s cn52xx;
215+ struct cvmx_mixx_oring1_s cn52xxp1;
216+ struct cvmx_mixx_oring1_s cn56xx;
217+ struct cvmx_mixx_oring1_s cn56xxp1;
218+};
219+
220+union cvmx_mixx_oring2 {
221+ uint64_t u64;
222+ struct cvmx_mixx_oring2_s {
223+ uint64_t reserved_52_63:12;
224+ uint64_t otlptr:20;
225+ uint64_t reserved_20_31:12;
226+ uint64_t odbell:20;
227+ } s;
228+ struct cvmx_mixx_oring2_s cn52xx;
229+ struct cvmx_mixx_oring2_s cn52xxp1;
230+ struct cvmx_mixx_oring2_s cn56xx;
231+ struct cvmx_mixx_oring2_s cn56xxp1;
232+};
233+
234+union cvmx_mixx_remcnt {
235+ uint64_t u64;
236+ struct cvmx_mixx_remcnt_s {
237+ uint64_t reserved_52_63:12;
238+ uint64_t iremcnt:20;
239+ uint64_t reserved_20_31:12;
240+ uint64_t oremcnt:20;
241+ } s;
242+ struct cvmx_mixx_remcnt_s cn52xx;
243+ struct cvmx_mixx_remcnt_s cn52xxp1;
244+ struct cvmx_mixx_remcnt_s cn56xx;
245+ struct cvmx_mixx_remcnt_s cn56xxp1;
246+};
247+
248+#endif
arch/mips/include/asm/octeon/cvmx-smix-defs.h+178−0
@@ -0,0 +1,178 @@
1+/***********************license start***************
2+ * Author: Cavium Networks
3+ *
4+ * Contact: support@caviumnetworks.com
5+ * This file is part of the OCTEON SDK
6+ *
7+ * Copyright (c) 2003-2008 Cavium Networks
8+ *
9+ * This file is free software; you can redistribute it and/or modify
10+ * it under the terms of the GNU General Public License, Version 2, as
11+ * published by the Free Software Foundation.
12+ *
13+ * This file is distributed in the hope that it will be useful, but
14+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16+ * NONINFRINGEMENT. See the GNU General Public License for more
17+ * details.
18+ *
19+ * You should have received a copy of the GNU General Public License
20+ * along with this file; if not, write to the Free Software
21+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22+ * or visit http://www.gnu.org/licenses/.
23+ *
24+ * This file may also be available under a different license from Cavium.
25+ * Contact Cavium Networks for more information
26+ ***********************license end**************************************/
27+
28+#ifndef __CVMX_SMIX_DEFS_H__
29+#define __CVMX_SMIX_DEFS_H__
30+
31+#define CVMX_SMIX_CLK(offset) \
32+ CVMX_ADD_IO_SEG(0x0001180000001818ull + (((offset) & 1) * 256))
33+#define CVMX_SMIX_CMD(offset) \
34+ CVMX_ADD_IO_SEG(0x0001180000001800ull + (((offset) & 1) * 256))
35+#define CVMX_SMIX_EN(offset) \
36+ CVMX_ADD_IO_SEG(0x0001180000001820ull + (((offset) & 1) * 256))
37+#define CVMX_SMIX_RD_DAT(offset) \
38+ CVMX_ADD_IO_SEG(0x0001180000001810ull + (((offset) & 1) * 256))
39+#define CVMX_SMIX_WR_DAT(offset) \
40+ CVMX_ADD_IO_SEG(0x0001180000001808ull + (((offset) & 1) * 256))
41+
42+union cvmx_smix_clk {
43+ uint64_t u64;
44+ struct cvmx_smix_clk_s {
45+ uint64_t reserved_25_63:39;
46+ uint64_t mode:1;
47+ uint64_t reserved_21_23:3;
48+ uint64_t sample_hi:5;
49+ uint64_t sample_mode:1;
50+ uint64_t reserved_14_14:1;
51+ uint64_t clk_idle:1;
52+ uint64_t preamble:1;
53+ uint64_t sample:4;
54+ uint64_t phase:8;
55+ } s;
56+ struct cvmx_smix_clk_cn30xx {
57+ uint64_t reserved_21_63:43;
58+ uint64_t sample_hi:5;
59+ uint64_t reserved_14_15:2;
60+ uint64_t clk_idle:1;
61+ uint64_t preamble:1;
62+ uint64_t sample:4;
63+ uint64_t phase:8;
64+ } cn30xx;
65+ struct cvmx_smix_clk_cn30xx cn31xx;
66+ struct cvmx_smix_clk_cn30xx cn38xx;
67+ struct cvmx_smix_clk_cn30xx cn38xxp2;
68+ struct cvmx_smix_clk_cn50xx {
69+ uint64_t reserved_25_63:39;
70+ uint64_t mode:1;
71+ uint64_t reserved_21_23:3;
72+ uint64_t sample_hi:5;
73+ uint64_t reserved_14_15:2;
74+ uint64_t clk_idle:1;
75+ uint64_t preamble:1;
76+ uint64_t sample:4;
77+ uint64_t phase:8;
78+ } cn50xx;
79+ struct cvmx_smix_clk_s cn52xx;
80+ struct cvmx_smix_clk_cn50xx cn52xxp1;
81+ struct cvmx_smix_clk_s cn56xx;
82+ struct cvmx_smix_clk_cn50xx cn56xxp1;
83+ struct cvmx_smix_clk_cn30xx cn58xx;
84+ struct cvmx_smix_clk_cn30xx cn58xxp1;
85+};
86+
87+union cvmx_smix_cmd {
88+ uint64_t u64;
89+ struct cvmx_smix_cmd_s {
90+ uint64_t reserved_18_63:46;
91+ uint64_t phy_op:2;
92+ uint64_t reserved_13_15:3;
93+ uint64_t phy_adr:5;
94+ uint64_t reserved_5_7:3;
95+ uint64_t reg_adr:5;
96+ } s;
97+ struct cvmx_smix_cmd_cn30xx {
98+ uint64_t reserved_17_63:47;
99+ uint64_t phy_op:1;
100+ uint64_t reserved_13_15:3;
101+ uint64_t phy_adr:5;
102+ uint64_t reserved_5_7:3;
103+ uint64_t reg_adr:5;
104+ } cn30xx;
105+ struct cvmx_smix_cmd_cn30xx cn31xx;
106+ struct cvmx_smix_cmd_cn30xx cn38xx;
107+ struct cvmx_smix_cmd_cn30xx cn38xxp2;
108+ struct cvmx_smix_cmd_s cn50xx;
109+ struct cvmx_smix_cmd_s cn52xx;
110+ struct cvmx_smix_cmd_s cn52xxp1;
111+ struct cvmx_smix_cmd_s cn56xx;
112+ struct cvmx_smix_cmd_s cn56xxp1;
113+ struct cvmx_smix_cmd_cn30xx cn58xx;
114+ struct cvmx_smix_cmd_cn30xx cn58xxp1;
115+};
116+
117+union cvmx_smix_en {
118+ uint64_t u64;
119+ struct cvmx_smix_en_s {
120+ uint64_t reserved_1_63:63;
121+ uint64_t en:1;
122+ } s;
123+ struct cvmx_smix_en_s cn30xx;
124+ struct cvmx_smix_en_s cn31xx;
125+ struct cvmx_smix_en_s cn38xx;
126+ struct cvmx_smix_en_s cn38xxp2;
127+ struct cvmx_smix_en_s cn50xx;
128+ struct cvmx_smix_en_s cn52xx;
129+ struct cvmx_smix_en_s cn52xxp1;
130+ struct cvmx_smix_en_s cn56xx;
131+ struct cvmx_smix_en_s cn56xxp1;
132+ struct cvmx_smix_en_s cn58xx;
133+ struct cvmx_smix_en_s cn58xxp1;
134+};
135+
136+union cvmx_smix_rd_dat {
137+ uint64_t u64;
138+ struct cvmx_smix_rd_dat_s {
139+ uint64_t reserved_18_63:46;
140+ uint64_t pending:1;
141+ uint64_t val:1;
142+ uint64_t dat:16;
143+ } s;
144+ struct cvmx_smix_rd_dat_s cn30xx;
145+ struct cvmx_smix_rd_dat_s cn31xx;
146+ struct cvmx_smix_rd_dat_s cn38xx;
147+ struct cvmx_smix_rd_dat_s cn38xxp2;
148+ struct cvmx_smix_rd_dat_s cn50xx;
149+ struct cvmx_smix_rd_dat_s cn52xx;
150+ struct cvmx_smix_rd_dat_s cn52xxp1;
151+ struct cvmx_smix_rd_dat_s cn56xx;
152+ struct cvmx_smix_rd_dat_s cn56xxp1;
153+ struct cvmx_smix_rd_dat_s cn58xx;
154+ struct cvmx_smix_rd_dat_s cn58xxp1;
155+};
156+
157+union cvmx_smix_wr_dat {
158+ uint64_t u64;
159+ struct cvmx_smix_wr_dat_s {
160+ uint64_t reserved_18_63:46;
161+ uint64_t pending:1;
162+ uint64_t val:1;
163+ uint64_t dat:16;
164+ } s;
165+ struct cvmx_smix_wr_dat_s cn30xx;
166+ struct cvmx_smix_wr_dat_s cn31xx;
167+ struct cvmx_smix_wr_dat_s cn38xx;
168+ struct cvmx_smix_wr_dat_s cn38xxp2;
169+ struct cvmx_smix_wr_dat_s cn50xx;
170+ struct cvmx_smix_wr_dat_s cn52xx;
171+ struct cvmx_smix_wr_dat_s cn52xxp1;
172+ struct cvmx_smix_wr_dat_s cn56xx;
173+ struct cvmx_smix_wr_dat_s cn56xxp1;
174+ struct cvmx_smix_wr_dat_s cn58xx;
175+ struct cvmx_smix_wr_dat_s cn58xxp1;
176+};
177+
178+#endif
arch/mips/include/asm/octeon/octeon.h+1−0
@@ -47,6 +47,7 @@ struct octeon_cop2_state; · 46 unmodified lines
4747 extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *state);
4848 extern void octeon_crypto_disable(struct octeon_cop2_state *state,
4949 unsigned long flags);
50+extern asmlinkage void octeon_cop2_restore(struct octeon_cop2_state *task);
5051
5152 extern void octeon_init_cvmcount(void);
5253
arch/mips/include/asm/pgtable.h+13−0
@@ -389,6 +389,19 @@ static inline int io_remap_pfn_range(struct vm_area_struct *vma, · 388 unmodified lines
389389
390390 #include <asm-generic/pgtable.h>
391391
392+/*
393+ * uncached accelerated TLB map for video memory access
394+ */
395+#ifdef CONFIG_CPU_SUPPORTS_UNCACHED_ACCELERATED
396+#define __HAVE_PHYS_MEM_ACCESS_PROT
397+
398+struct file;
399+pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
400+ unsigned long size, pgprot_t vma_prot);
401+int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn,
402+ unsigned long size, pgprot_t *vma_prot);
403+#endif
404+
392405 /*
393406 * We provide our own get_unmapped area to cope with the virtual aliasing
394407 * constraints placed on us by the cache architecture.
arch/mips/include/asm/sgialib.h+1−2
@@ -85,8 +85,7 @@ extern void prom_identify_arch(void); · 84 unmodified lines
8585 extern PCHAR ArcGetEnvironmentVariable(PCHAR name);
8686 extern LONG ArcSetEnvironmentVariable(PCHAR name, PCHAR value);
8787
88−/* ARCS command line acquisition and parsing. */
89−extern char *prom_getcmdline(void);
88+/* ARCS command line parsing. */
9089 extern void prom_init_cmdline(void);
9190
9291 /* Acquiring info about the current time, etc. */
arch/mips/include/asm/stackframe.h+22−18
@@ -51,9 +51,6 @@ · 50 unmodified lines
5151 LONG_S v1, PT_ACX(sp)
5252 #else
5353 mfhi v1
54− LONG_S v1, PT_HI(sp)
55− mflo v1
56− LONG_S v1, PT_LO(sp)
5754 #endif
5855 #ifdef CONFIG_32BIT
5956 LONG_S $8, PT_R8(sp)
@@ -62,10 +59,17 @@ · 2 unmodified lines
6259 LONG_S $10, PT_R10(sp)
6360 LONG_S $11, PT_R11(sp)
6461 LONG_S $12, PT_R12(sp)
62+#ifndef CONFIG_CPU_HAS_SMARTMIPS
63+ LONG_S v1, PT_HI(sp)
64+ mflo v1
65+#endif
6566 LONG_S $13, PT_R13(sp)
6667 LONG_S $14, PT_R14(sp)
6768 LONG_S $15, PT_R15(sp)
6869 LONG_S $24, PT_R24(sp)
70+#ifndef CONFIG_CPU_HAS_SMARTMIPS
71+ LONG_S v1, PT_LO(sp)
72+#endif
6973 .endm
7074
7175 .macro SAVE_STATIC
@@ -83,15 +87,19 @@ · 11 unmodified lines
8387 #ifdef CONFIG_SMP
8488 #ifdef CONFIG_MIPS_MT_SMTC
8589 #define PTEBASE_SHIFT 19 /* TCBIND */
90+#define CPU_ID_REG CP0_TCBIND
91+#define CPU_ID_MFC0 mfc0
92+#elif defined(CONFIG_MIPS_PGD_C0_CONTEXT)
93+#define PTEBASE_SHIFT 48 /* XCONTEXT */
94+#define CPU_ID_REG CP0_XCONTEXT
95+#define CPU_ID_MFC0 MFC0
8696 #else
8797 #define PTEBASE_SHIFT 23 /* CONTEXT */
98+#define CPU_ID_REG CP0_CONTEXT
99+#define CPU_ID_MFC0 MFC0
88100 #endif
89101 .macro get_saved_sp /* SMP variation */
90−#ifdef CONFIG_MIPS_MT_SMTC
91− mfc0 k0, CP0_TCBIND
92−#else
93− MFC0 k0, CP0_CONTEXT
94−#endif
102+ CPU_ID_MFC0 k0, CPU_ID_REG
95103 #if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
96104 lui k1, %hi(kernelsp)
97105 #else
@@ -107,11 +115,7 @@ · 9 unmodified lines
107115 .endm
108116
109117 .macro set_saved_sp stackp temp temp2
110−#ifdef CONFIG_MIPS_MT_SMTC
111− mfc0 \temp, CP0_TCBIND
112−#else
113− MFC0 \temp, CP0_CONTEXT
114−#endif
118+ CPU_ID_MFC0 \temp, CPU_ID_REG
115119 LONG_SRL \temp, PTEBASE_SHIFT
116120 LONG_S \stackp, kernelsp(\temp)
117121 .endm
@@ -166,7 +170,6 @@ · 48 unmodified lines
166170 LONG_S $0, PT_R0(sp)
167171 mfc0 v1, CP0_STATUS
168172 LONG_S $2, PT_R2(sp)
169− LONG_S v1, PT_STATUS(sp)
170173 #ifdef CONFIG_MIPS_MT_SMTC
171174 /*
172175 * Ideally, these instructions would be shuffled in
@@ -178,20 +181,21 @@ · 5 unmodified lines
178181 LONG_S v1, PT_TCSTATUS(sp)
179182 #endif /* CONFIG_MIPS_MT_SMTC */
180183 LONG_S $4, PT_R4(sp)
181− mfc0 v1, CP0_CAUSE
182184 LONG_S $5, PT_R5(sp)
183− LONG_S v1, PT_CAUSE(sp)
185+ LONG_S v1, PT_STATUS(sp)
186+ mfc0 v1, CP0_CAUSE
184187 LONG_S $6, PT_R6(sp)
185− MFC0 v1, CP0_EPC
186188 LONG_S $7, PT_R7(sp)
189+ LONG_S v1, PT_CAUSE(sp)
190+ MFC0 v1, CP0_EPC
187191 #ifdef CONFIG_64BIT
188192 LONG_S $8, PT_R8(sp)
189193 LONG_S $9, PT_R9(sp)
190194 #endif
191− LONG_S v1, PT_EPC(sp)
192195 LONG_S $25, PT_R25(sp)
193196 LONG_S $28, PT_R28(sp)
194197 LONG_S $31, PT_R31(sp)
198+ LONG_S v1, PT_EPC(sp)
195199 ori $28, sp, _THREAD_MASK
196200 xori $28, _THREAD_MASK
197201 #ifdef CONFIG_CPU_CAVIUM_OCTEON
arch/mips/kernel/Makefile+12−2
@@ -2,14 +2,17 @@ · 1 unmodified line
22 # Makefile for the Linux/MIPS kernel.
33 #
44
5−CPPFLAGS_vmlinux.lds := $(KBUILD_CFLAGS)
6−
75 extra-y := head.o init_task.o vmlinux.lds
86
97 obj-y += cpu-probe.o branch.o entry.o genex.o irq.o process.o \
108 ptrace.o reset.o setup.o signal.o syscall.o \
119 time.o topology.o traps.o unaligned.o watch.o
1210
11+ifdef CONFIG_FUNCTION_TRACER
12+CFLAGS_REMOVE_ftrace.o = -pg
13+CFLAGS_REMOVE_early_printk.o = -pg
14+endif
15+
1316 obj-$(CONFIG_CEVT_BCM1480) += cevt-bcm1480.o
1417 obj-$(CONFIG_CEVT_R4K_LIB) += cevt-r4k.o
1518 obj-$(CONFIG_MIPS_MT_SMTC) += cevt-smtc.o
@@ -19,6 +22,7 @@ obj-$(CONFIG_CEVT_SB1250) += cevt-sb1250.o · 3 unmodified lines
1922 obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o
2023 obj-$(CONFIG_CSRC_BCM1480) += csrc-bcm1480.o
2124 obj-$(CONFIG_CSRC_IOASIC) += csrc-ioasic.o
25+obj-$(CONFIG_CSRC_POWERTV) += csrc-powertv.o
2226 obj-$(CONFIG_CSRC_R4K_LIB) += csrc-r4k.o
2327 obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o
2428 obj-$(CONFIG_SYNC_R4K) += sync-r4k.o
@@ -26,6 +30,8 @@ obj-$(CONFIG_SYNC_R4K) += sync-r4k.o · 1 unmodified line
2630 obj-$(CONFIG_STACKTRACE) += stacktrace.o
2731 obj-$(CONFIG_MODULES) += mips_ksyms.o module.o
2832
33+obj-$(CONFIG_FUNCTION_TRACER) += mcount.o ftrace.o
34+
2935 obj-$(CONFIG_CPU_LOONGSON2) += r4k_fpu.o r4k_switch.o
3036 obj-$(CONFIG_CPU_MIPS32) += r4k_fpu.o r4k_switch.o
3137 obj-$(CONFIG_CPU_MIPS64) += r4k_fpu.o r4k_switch.o
@@ -92,4 +98,8 @@ CFLAGS_cpu-bugs64.o = $(shell if $(CC) $(KBUILD_CFLAGS) -Wa,-mdaddi -c -o /dev/n · 60 unmodified lines
9298
9399 obj-$(CONFIG_HAVE_STD_PC_SERIAL_PORT) += 8250-platform.o
94100
101+obj-$(CONFIG_MIPS_CPUFREQ) += cpufreq/
102+
95103 EXTRA_CFLAGS += -Werror
104+
105+CPPFLAGS_vmlinux.lds := $(KBUILD_CFLAGS)
arch/mips/kernel/cpu-probe.c+2−0
@@ -16,6 +16,7 @@ · 15 unmodified lines
1616 #include <linux/ptrace.h>
1717 #include <linux/smp.h>
1818 #include <linux/stddef.h>
19+#include <linux/module.h>
1920
2021 #include <asm/bugs.h>
2122 #include <asm/cpu.h>
@@ -32,6 +33,7 @@ · 10 unmodified lines
3233 * the CPU very much.
3334 */
3435 void (*cpu_wait)(void);
36+EXPORT_SYMBOL(cpu_wait);
3537
3638 static void r3081_wait(void)
3739 {
arch/mips/kernel/cpufreq/Kconfig+41−0
@@ -0,0 +1,41 @@
1+#
2+# CPU Frequency scaling
3+#
4+
5+config MIPS_EXTERNAL_TIMER
6+ bool
7+
8+config MIPS_CPUFREQ
9+ bool
10+ default y
11+ depends on CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
12+
13+if MIPS_CPUFREQ
14+
15+menu "CPU Frequency scaling"
16+
17+source "drivers/cpufreq/Kconfig"
18+
19+if CPU_FREQ
20+
21+comment "CPUFreq processor drivers"
22+
23+config LOONGSON2_CPUFREQ
24+ tristate "Loongson2 CPUFreq Driver"
25+ select CPU_FREQ_TABLE
26+ depends on MIPS_CPUFREQ
27+ help
28+ This option adds a CPUFreq driver for loongson processors which
29+ support software configurable cpu frequency.
30+
31+ Loongson2F and it's successors support this feature.
32+
33+ For details, take a look at <file:Documentation/cpu-freq/>.
34+
35+ If in doubt, say N.
36+
37+endif # CPU_FREQ
38+
39+endmenu
40+
41+endif # MIPS_CPUFREQ
arch/mips/kernel/cpufreq/Makefile+5−0
@@ -0,0 +1,5 @@
1+#
2+# Makefile for the Linux/MIPS cpufreq.
3+#
4+
5+obj-$(CONFIG_LOONGSON2_CPUFREQ) += loongson2_cpufreq.o loongson2_clock.o
arch/mips/kernel/cpufreq/loongson2_clock.c+166−0
@@ -0,0 +1,166 @@
1+/*
2+ * Copyright (C) 2006 - 2008 Lemote Inc. & Insititute of Computing Technology
3+ * Author: Yanhua, yanh@lemote.com
4+ *
5+ * This file is subject to the terms and conditions of the GNU General Public
6+ * License. See the file "COPYING" in the main directory of this archive
7+ * for more details.
8+ */
9+
10+#include <linux/cpufreq.h>
11+#include <linux/platform_device.h>
12+
13+#include <asm/clock.h>
14+
15+#include <loongson.h>
16+
17+static LIST_HEAD(clock_list);
18+static DEFINE_SPINLOCK(clock_lock);
19+static DEFINE_MUTEX(clock_list_sem);
20+
21+/* Minimum CLK support */
22+enum {
23+ DC_ZERO, DC_25PT = 2, DC_37PT, DC_50PT, DC_62PT, DC_75PT,
24+ DC_87PT, DC_DISABLE, DC_RESV
25+};
26+
27+struct cpufreq_frequency_table loongson2_clockmod_table[] = {
28+ {DC_RESV, CPUFREQ_ENTRY_INVALID},
29+ {DC_ZERO, CPUFREQ_ENTRY_INVALID},
30+ {DC_25PT, 0},
31+ {DC_37PT, 0},
32+ {DC_50PT, 0},
33+ {DC_62PT, 0},
34+ {DC_75PT, 0},
35+ {DC_87PT, 0},
36+ {DC_DISABLE, 0},
37+ {DC_RESV, CPUFREQ_TABLE_END},
38+};
39+EXPORT_SYMBOL_GPL(loongson2_clockmod_table);
40+
41+static struct clk cpu_clk = {
42+ .name = "cpu_clk",
43+ .flags = CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES,
44+ .rate = 800000000,
45+};
46+
47+struct clk *clk_get(struct device *dev, const char *id)
48+{
49+ return &cpu_clk;
50+}
51+EXPORT_SYMBOL(clk_get);
52+
53+static void propagate_rate(struct clk *clk)
54+{
55+ struct clk *clkp;
56+
57+ list_for_each_entry(clkp, &clock_list, node) {
58+ if (likely(clkp->parent != clk))
59+ continue;
60+ if (likely(clkp->ops && clkp->ops->recalc))
61+ clkp->ops->recalc(clkp);
62+ if (unlikely(clkp->flags & CLK_RATE_PROPAGATES))
63+ propagate_rate(clkp);
64+ }
65+}
66+
67+int clk_enable(struct clk *clk)
68+{
69+ return 0;
70+}
71+EXPORT_SYMBOL(clk_enable);
72+
73+void clk_disable(struct clk *clk)
74+{
75+}
76+EXPORT_SYMBOL(clk_disable);
77+
78+unsigned long clk_get_rate(struct clk *clk)
79+{
80+ return (unsigned long)clk->rate;
81+}
82+EXPORT_SYMBOL(clk_get_rate);
83+
84+void clk_put(struct clk *clk)
85+{
86+}
87+EXPORT_SYMBOL(clk_put);
88+
89+int clk_set_rate(struct clk *clk, unsigned long rate)
90+{
91+ return clk_set_rate_ex(clk, rate, 0);
92+}
93+EXPORT_SYMBOL_GPL(clk_set_rate);
94+
95+int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id)
96+{
97+ int ret = 0;
98+ int regval;
99+ int i;
100+
101+ if (likely(clk->ops && clk->ops->set_rate)) {
102+ unsigned long flags;
103+
104+ spin_lock_irqsave(&clock_lock, flags);
105+ ret = clk->ops->set_rate(clk, rate, algo_id);
106+ spin_unlock_irqrestore(&clock_lock, flags);
107+ }
108+
109+ if (unlikely(clk->flags & CLK_RATE_PROPAGATES))
110+ propagate_rate(clk);
111+
112+ for (i = 0; loongson2_clockmod_table[i].frequency != CPUFREQ_TABLE_END;
113+ i++) {
114+ if (loongson2_clockmod_table[i].frequency ==
115+ CPUFREQ_ENTRY_INVALID)
116+ continue;
117+ if (rate == loongson2_clockmod_table[i].frequency)
118+ break;
119+ }
120+ if (rate != loongson2_clockmod_table[i].frequency)
121+ return -ENOTSUPP;
122+
123+ clk->rate = rate;
124+
125+ regval = LOONGSON_CHIPCFG0;
126+ regval = (regval & ~0x7) | (loongson2_clockmod_table[i].index - 1);
127+ LOONGSON_CHIPCFG0 = regval;
128+
129+ return ret;
130+}
131+EXPORT_SYMBOL_GPL(clk_set_rate_ex);
132+
133+long clk_round_rate(struct clk *clk, unsigned long rate)
134+{
135+ if (likely(clk->ops && clk->ops->round_rate)) {
136+ unsigned long flags, rounded;
137+
138+ spin_lock_irqsave(&clock_lock, flags);
139+ rounded = clk->ops->round_rate(clk, rate);
140+ spin_unlock_irqrestore(&clock_lock, flags);
141+
142+ return rounded;
143+ }
144+
145+ return rate;
146+}
147+EXPORT_SYMBOL_GPL(clk_round_rate);
148+
149+/*
150+ * This is the simple version of Loongson-2 wait, Maybe we need do this in
151+ * interrupt disabled content
152+ */
153+
154+DEFINE_SPINLOCK(loongson2_wait_lock);
155+void loongson2_cpu_wait(void)
156+{
157+ u32 cpu_freq;
158+ unsigned long flags;
159+
160+ spin_lock_irqsave(&loongson2_wait_lock, flags);
161+ cpu_freq = LOONGSON_CHIPCFG0;
162+ LOONGSON_CHIPCFG0 &= ~0x7; /* Put CPU into wait mode */
163+ LOONGSON_CHIPCFG0 = cpu_freq; /* Restore CPU state */
164+ spin_unlock_irqrestore(&loongson2_wait_lock, flags);
165+}
166+EXPORT_SYMBOL_GPL(loongson2_cpu_wait);
arch/mips/kernel/cpufreq/loongson2_cpufreq.c+227−0
@@ -0,0 +1,227 @@
1+/*
2+ * Cpufreq driver for the loongson-2 processors
3+ *
4+ * The 2E revision of loongson processor not support this feature.
5+ *
6+ * Copyright (C) 2006 - 2008 Lemote Inc. & Insititute of Computing Technology
7+ * Author: Yanhua, yanh@lemote.com
8+ *
9+ * This file is subject to the terms and conditions of the GNU General Public
10+ * License. See the file "COPYING" in the main directory of this archive
11+ * for more details.
12+ */
13+#include <linux/cpufreq.h>
14+#include <linux/module.h>
15+#include <linux/err.h>
16+#include <linux/sched.h> /* set_cpus_allowed() */
17+#include <linux/delay.h>
18+#include <linux/platform_device.h>
19+
20+#include <asm/clock.h>
21+
22+#include <loongson.h>
23+
24+static uint nowait;
25+
26+static struct clk *cpuclk;
27+
28+static void (*saved_cpu_wait) (void);
29+
30+static int loongson2_cpu_freq_notifier(struct notifier_block *nb,
31+ unsigned long val, void *data);
32+
33+static struct notifier_block loongson2_cpufreq_notifier_block = {
34+ .notifier_call = loongson2_cpu_freq_notifier
35+};
36+
37+static int loongson2_cpu_freq_notifier(struct notifier_block *nb,
38+ unsigned long val, void *data)
39+{
40+ if (val == CPUFREQ_POSTCHANGE)
41+ current_cpu_data.udelay_val = loops_per_jiffy;
42+
43+ return 0;
44+}
45+
46+static unsigned int loongson2_cpufreq_get(unsigned int cpu)
47+{
48+ return clk_get_rate(cpuclk);
49+}
50+
51+/*
52+ * Here we notify other drivers of the proposed change and the final change.
53+ */
54+static int loongson2_cpufreq_target(struct cpufreq_policy *policy,
55+ unsigned int target_freq,
56+ unsigned int relation)
57+{
58+ unsigned int cpu = policy->cpu;
59+ unsigned int newstate = 0;
60+ cpumask_t cpus_allowed;
61+ struct cpufreq_freqs freqs;
62+ unsigned int freq;
63+
64+ if (!cpu_online(cpu))
65+ return -ENODEV;
66+
67+ cpus_allowed = current->cpus_allowed;
68+ set_cpus_allowed(current, cpumask_of_cpu(cpu));
69+
70+ if (cpufreq_frequency_table_target
71+ (policy, &loongson2_clockmod_table[0], target_freq, relation,
72+ &newstate))
73+ return -EINVAL;
74+
75+ freq =
76+ ((cpu_clock_freq / 1000) *
77+ loongson2_clockmod_table[newstate].index) / 8;
78+ if (freq < policy->min || freq > policy->max)
79+ return -EINVAL;
80+
81+ pr_debug("cpufreq: requested frequency %u Hz\n", target_freq * 1000);
82+
83+ freqs.cpu = cpu;
84+ freqs.old = loongson2_cpufreq_get(cpu);
85+ freqs.new = freq;
86+ freqs.flags = 0;
87+
88+ if (freqs.new == freqs.old)
89+ return 0;
90+
91+ /* notifiers */
92+ cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
93+
94+ set_cpus_allowed(current, cpus_allowed);
95+
96+ /* setting the cpu frequency */
97+ clk_set_rate(cpuclk, freq);
98+
99+ /* notifiers */
100+ cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
101+
102+ pr_debug("cpufreq: set frequency %u kHz\n", freq);
103+
104+ return 0;
105+}
106+
107+static int loongson2_cpufreq_cpu_init(struct cpufreq_policy *policy)
108+{
109+ int i;
110+
111+ if (!cpu_online(policy->cpu))
112+ return -ENODEV;
113+
114+ cpuclk = clk_get(NULL, "cpu_clk");
115+ if (IS_ERR(cpuclk)) {
116+ printk(KERN_ERR "cpufreq: couldn't get CPU clk\n");
117+ return PTR_ERR(cpuclk);
118+ }
119+
120+ cpuclk->rate = cpu_clock_freq / 1000;
121+ if (!cpuclk->rate)
122+ return -EINVAL;
123+
124+ /* clock table init */
125+ for (i = 2;
126+ (loongson2_clockmod_table[i].frequency != CPUFREQ_TABLE_END);
127+ i++)
128+ loongson2_clockmod_table[i].frequency = (cpuclk->rate * i) / 8;
129+
130+ policy->cur = loongson2_cpufreq_get(policy->cpu);
131+
132+ cpufreq_frequency_table_get_attr(&loongson2_clockmod_table[0],
133+ policy->cpu);
134+
135+ return cpufreq_frequency_table_cpuinfo(policy,
136+ &loongson2_clockmod_table[0]);
137+}
138+
139+static int loongson2_cpufreq_verify(struct cpufreq_policy *policy)
140+{
141+ return cpufreq_frequency_table_verify(policy,
142+ &loongson2_clockmod_table[0]);
143+}
144+
145+static int loongson2_cpufreq_exit(struct cpufreq_policy *policy)
146+{
147+ clk_put(cpuclk);
148+ return 0;
149+}
150+
151+static struct freq_attr *loongson2_table_attr[] = {
152+ &cpufreq_freq_attr_scaling_available_freqs,
153+ NULL,
154+};
155+
156+static struct cpufreq_driver loongson2_cpufreq_driver = {
157+ .owner = THIS_MODULE,
158+ .name = "loongson2",
159+ .init = loongson2_cpufreq_cpu_init,
160+ .verify = loongson2_cpufreq_verify,
161+ .target = loongson2_cpufreq_target,
162+ .get = loongson2_cpufreq_get,
163+ .exit = loongson2_cpufreq_exit,
164+ .attr = loongson2_table_attr,
165+};
166+
167+static struct platform_device_id platform_device_ids[] = {
168+ {
169+ .name = "loongson2_cpufreq",
170+ },
171+ {}
172+};
173+
174+MODULE_DEVICE_TABLE(platform, platform_device_ids);
175+
176+static struct platform_driver platform_driver = {
177+ .driver = {
178+ .name = "loongson2_cpufreq",
179+ .owner = THIS_MODULE,
180+ },
181+ .id_table = platform_device_ids,
182+};
183+
184+static int __init cpufreq_init(void)
185+{
186+ int ret;
187+
188+ /* Register platform stuff */
189+ ret = platform_driver_register(&platform_driver);
190+ if (ret)
191+ return ret;
192+
193+ pr_info("cpufreq: Loongson-2F CPU frequency driver.\n");
194+
195+ cpufreq_register_notifier(&loongson2_cpufreq_notifier_block,
196+ CPUFREQ_TRANSITION_NOTIFIER);
197+
198+ ret = cpufreq_register_driver(&loongson2_cpufreq_driver);
199+
200+ if (!ret && !nowait) {
201+ saved_cpu_wait = cpu_wait;
202+ cpu_wait = loongson2_cpu_wait;
203+ }
204+
205+ return ret;
206+}
207+
208+static void __exit cpufreq_exit(void)
209+{
210+ if (!nowait && saved_cpu_wait)
211+ cpu_wait = saved_cpu_wait;
212+ cpufreq_unregister_driver(&loongson2_cpufreq_driver);
213+ cpufreq_unregister_notifier(&loongson2_cpufreq_notifier_block,
214+ CPUFREQ_TRANSITION_NOTIFIER);
215+
216+ platform_driver_unregister(&platform_driver);
217+}
218+
219+module_init(cpufreq_init);
220+module_exit(cpufreq_exit);
221+
222+module_param(nowait, uint, 0644);
223+MODULE_PARM_DESC(nowait, "Disable Loongson-2F specific wait");
224+
225+MODULE_AUTHOR("Yanhua <yanh@lemote.com>");
226+MODULE_DESCRIPTION("cpufreq driver for Loongson2F");
227+MODULE_LICENSE("GPL");
arch/mips/kernel/csrc-powertv.c+180−0
@@ -0,0 +1,180 @@
1+/*
2+ * Copyright (C) 2008 Scientific-Atlanta, Inc.
3+ *
4+ * This program is free software; you can redistribute it and/or
5+ * modify it under the terms of the GNU General Public License
6+ * as published by the Free Software Foundation; either version 2
7+ * of the License, or (at your option) any later version.
8+ *
9+ * This program is distributed in the hope that it will be useful,
10+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
11+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12+ * GNU General Public License for more details.
13+ *
14+ * You should have received a copy of the GNU General Public License
15+ * along with this program; if not, write to the Free Software
16+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17+ */
18+/*
19+ * The file comes from kernel/csrc-r4k.c
20+ */
21+#include <linux/clocksource.h>
22+#include <linux/init.h>
23+
24+#include <asm/time.h> /* Not included in linux/time.h */
25+
26+#include <asm/mach-powertv/asic_regs.h>
27+#include "powertv-clock.h"
28+
29+/* MIPS PLL Register Definitions */
30+#define PLL_GET_M(x) (((x) >> 8) & 0x000000FF)
31+#define PLL_GET_N(x) (((x) >> 16) & 0x000000FF)
32+#define PLL_GET_P(x) (((x) >> 24) & 0x00000007)
33+
34+/*
35+ * returns: Clock frequency in kHz
36+ */
37+unsigned int __init mips_get_pll_freq(void)
38+{
39+ unsigned int pll_reg, m, n, p;
40+ unsigned int fin = 54000; /* Base frequency in kHz */
41+ unsigned int fout;
42+
43+ /* Read PLL register setting */
44+ pll_reg = asic_read(mips_pll_setup);
45+ m = PLL_GET_M(pll_reg);
46+ n = PLL_GET_N(pll_reg);
47+ p = PLL_GET_P(pll_reg);
48+ pr_info("MIPS PLL Register:0x%x M=%d N=%d P=%d\n", pll_reg, m, n, p);
49+
50+ /* Calculate clock frequency = (2 * N * 54MHz) / (M * (2**P)) */
51+ fout = ((2 * n * fin) / (m * (0x01 << p)));
52+
53+ pr_info("MIPS Clock Freq=%d kHz\n", fout);
54+
55+ return fout;
56+}
57+
58+static cycle_t c0_hpt_read(struct clocksource *cs)
59+{
60+ return read_c0_count();
61+}
62+
63+static struct clocksource clocksource_mips = {
64+ .name = "powertv-counter",
65+ .read = c0_hpt_read,
66+ .mask = CLOCKSOURCE_MASK(32),
67+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
68+};
69+
70+static void __init powertv_c0_hpt_clocksource_init(void)
71+{
72+ unsigned int pll_freq = mips_get_pll_freq();
73+
74+ pr_info("CPU frequency %d.%02d MHz\n", pll_freq / 1000,
75+ (pll_freq % 1000) * 100 / 1000);
76+
77+ mips_hpt_frequency = pll_freq / 2 * 1000;
78+
79+ clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000;
80+
81+ clocksource_set_clock(&clocksource_mips, mips_hpt_frequency);
82+
83+ clocksource_register(&clocksource_mips);
84+}
85+
86+/**
87+ * struct tim_c - free running counter
88+ * @hi: High 16 bits of the counter
89+ * @lo: Low 32 bits of the counter
90+ *
91+ * Lays out the structure of the free running counter in memory. This counter
92+ * increments at a rate of 27 MHz/8 on all platforms.
93+ */
94+struct tim_c {
95+ unsigned int hi;
96+ unsigned int lo;
97+};
98+
99+static struct tim_c *tim_c;
100+
101+static cycle_t tim_c_read(struct clocksource *cs)
102+{
103+ unsigned int hi;
104+ unsigned int next_hi;
105+ unsigned int lo;
106+
107+ hi = readl(&tim_c->hi);
108+
109+ for (;;) {
110+ lo = readl(&tim_c->lo);
111+ next_hi = readl(&tim_c->hi);
112+ if (next_hi == hi)
113+ break;
114+ hi = next_hi;
115+ }
116+
117+pr_crit("%s: read %llx\n", __func__, ((u64) hi << 32) | lo);
118+ return ((u64) hi << 32) | lo;
119+}
120+
121+#define TIM_C_SIZE 48 /* # bits in the timer */
122+
123+static struct clocksource clocksource_tim_c = {
124+ .name = "powertv-tim_c",
125+ .read = tim_c_read,
126+ .mask = CLOCKSOURCE_MASK(TIM_C_SIZE),
127+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
128+};
129+
130+/**
131+ * powertv_tim_c_clocksource_init - set up a clock source for the TIM_C clock
132+ *
133+ * The hard part here is coming up with a constant k and shift s such that
134+ * the 48-bit TIM_C value multiplied by k doesn't overflow and that value,
135+ * when shifted right by s, yields the corresponding number of nanoseconds.
136+ * We know that TIM_C counts at 27 MHz/8, so each cycle corresponds to
137+ * 1 / (27,000,000/8) seconds. Multiply that by a billion and you get the
138+ * number of nanoseconds. Since the TIM_C value has 48 bits and the math is
139+ * done in 64 bits, avoiding an overflow means that k must be less than
140+ * 64 - 48 = 16 bits.
141+ */
142+static void __init powertv_tim_c_clocksource_init(void)
143+{
144+ int prescale;
145+ unsigned long dividend;
146+ unsigned long k;
147+ int s;
148+ const int max_k_bits = (64 - 48) - 1;
149+ const unsigned long billion = 1000000000;
150+ const unsigned long counts_per_second = 27000000 / 8;
151+
152+ prescale = BITS_PER_LONG - ilog2(billion) - 1;
153+ dividend = billion << prescale;
154+ k = dividend / counts_per_second;
155+ s = ilog2(k) - max_k_bits;
156+
157+ if (s < 0)
158+ s = prescale;
159+
160+ else {
161+ k >>= s;
162+ s += prescale;
163+ }
164+
165+ clocksource_tim_c.mult = k;
166+ clocksource_tim_c.shift = s;
167+ clocksource_tim_c.rating = 200;
168+
169+ clocksource_register(&clocksource_tim_c);
170+ tim_c = (struct tim_c *) asic_reg_addr(tim_ch);
171+}
172+
173+/**
174+ powertv_clocksource_init - initialize all clocksources
175+ */
176+void __init powertv_clocksource_init(void)
177+{
178+ powertv_c0_hpt_clocksource_init();
179+ powertv_tim_c_clocksource_init();
180+}
arch/mips/kernel/ftrace.c+275−0
@@ -0,0 +1,275 @@
1+/*
2+ * Code for replacing ftrace calls with jumps.
3+ *
4+ * Copyright (C) 2007-2008 Steven Rostedt <srostedt@redhat.com>
5+ * Copyright (C) 2009 DSLab, Lanzhou University, China
6+ * Author: Wu Zhangjin <wuzj@lemote.com>
7+ *
8+ * Thanks goes to Steven Rostedt for writing the original x86 version.
9+ */
10+
11+#include <linux/uaccess.h>
12+#include <linux/init.h>
13+#include <linux/ftrace.h>
14+
15+#include <asm/cacheflush.h>
16+#include <asm/asm.h>
17+#include <asm/asm-offsets.h>
18+
19+#ifdef CONFIG_DYNAMIC_FTRACE
20+
21+#define JAL 0x0c000000 /* jump & link: ip --> ra, jump to target */
22+#define ADDR_MASK 0x03ffffff /* op_code|addr : 31...26|25 ....0 */
23+#define jump_insn_encode(op_code, addr) \
24+ ((unsigned int)((op_code) | (((addr) >> 2) & ADDR_MASK)))
25+
26+static unsigned int ftrace_nop = 0x00000000;
27+
28+static int ftrace_modify_code(unsigned long ip, unsigned int new_code)
29+{
30+ int faulted;
31+
32+ /* *(unsigned int *)ip = new_code; */
33+ safe_store_code(new_code, ip, faulted);
34+
35+ if (unlikely(faulted))
36+ return -EFAULT;
37+
38+ flush_icache_range(ip, ip + 8);
39+
40+ return 0;
41+}
42+
43+static int lui_v1;
44+static int jal_mcount;
45+
46+int ftrace_make_nop(struct module *mod,
47+ struct dyn_ftrace *rec, unsigned long addr)
48+{
49+ unsigned int new;
50+ int faulted;
51+ unsigned long ip = rec->ip;
52+
53+ /* We have compiled module with -mlong-calls, but compiled the kernel
54+ * without it, we need to cope with them respectively. */
55+ if (ip & 0x40000000) {
56+ /* record it for ftrace_make_call */
57+ if (lui_v1 == 0) {
58+ /* lui_v1 = *(unsigned int *)ip; */
59+ safe_load_code(lui_v1, ip, faulted);
60+
61+ if (unlikely(faulted))
62+ return -EFAULT;
63+ }
64+
65+ /* lui v1, hi_16bit_of_mcount --> b 1f (0x10000004)
66+ * addiu v1, v1, low_16bit_of_mcount
67+ * move at, ra
68+ * jalr v1
69+ * nop
70+ * 1f: (ip + 12)
71+ */
72+ new = 0x10000004;
73+ } else {
74+ /* record/calculate it for ftrace_make_call */
75+ if (jal_mcount == 0) {
76+ /* We can record it directly like this:
77+ * jal_mcount = *(unsigned int *)ip;
78+ * Herein, jump over the first two nop instructions */
79+ jal_mcount = jump_insn_encode(JAL, (MCOUNT_ADDR + 8));
80+ }
81+
82+ /* move at, ra
83+ * jalr v1 --> nop
84+ */
85+ new = ftrace_nop;
86+ }
87+ return ftrace_modify_code(ip, new);
88+}
89+
90+static int modified; /* initialized as 0 by default */
91+
92+int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr)
93+{
94+ unsigned int new;
95+ unsigned long ip = rec->ip;
96+
97+ /* We just need to remove the "b ftrace_stub" at the fist time! */
98+ if (modified == 0) {
99+ modified = 1;
100+ ftrace_modify_code(addr, ftrace_nop);
101+ }
102+ /* ip, module: 0xc0000000, kernel: 0x80000000 */
103+ new = (ip & 0x40000000) ? lui_v1 : jal_mcount;
104+
105+ return ftrace_modify_code(ip, new);
106+}
107+
108+#define FTRACE_CALL_IP ((unsigned long)(&ftrace_call))
109+
110+int ftrace_update_ftrace_func(ftrace_func_t func)
111+{
112+ unsigned int new;
113+
114+ new = jump_insn_encode(JAL, (unsigned long)func);
115+
116+ return ftrace_modify_code(FTRACE_CALL_IP, new);
117+}
118+
119+int __init ftrace_dyn_arch_init(void *data)
120+{
121+ /* The return code is retured via data */
122+ *(unsigned long *)data = 0;
123+
124+ return 0;
125+}
126+#endif /* CONFIG_DYNAMIC_FTRACE */
127+
128+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
129+
130+#ifdef CONFIG_DYNAMIC_FTRACE
131+
132+extern void ftrace_graph_call(void);
133+#define JMP 0x08000000 /* jump to target directly */
134+#define CALL_FTRACE_GRAPH_CALLER \
135+ jump_insn_encode(JMP, (unsigned long)(&ftrace_graph_caller))
136+#define FTRACE_GRAPH_CALL_IP ((unsigned long)(&ftrace_graph_call))
137+
138+int ftrace_enable_ftrace_graph_caller(void)
139+{
140+ return ftrace_modify_code(FTRACE_GRAPH_CALL_IP,
141+ CALL_FTRACE_GRAPH_CALLER);
142+}
143+
144+int ftrace_disable_ftrace_graph_caller(void)
145+{
146+ return ftrace_modify_code(FTRACE_GRAPH_CALL_IP, ftrace_nop);
147+}
148+
149+#endif /* !CONFIG_DYNAMIC_FTRACE */
150+
151+#ifndef KBUILD_MCOUNT_RA_ADDRESS
152+#define S_RA_SP (0xafbf << 16) /* s{d,w} ra, offset(sp) */
153+#define S_R_SP (0xafb0 << 16) /* s{d,w} R, offset(sp) */
154+#define OFFSET_MASK 0xffff /* stack offset range: 0 ~ PT_SIZE */
155+
156+unsigned long ftrace_get_parent_addr(unsigned long self_addr,
157+ unsigned long parent,
158+ unsigned long parent_addr,
159+ unsigned long fp)
160+{
161+ unsigned long sp, ip, ra;
162+ unsigned int code;
163+ int faulted;
164+
165+ /* in module or kernel? */
166+ if (self_addr & 0x40000000) {
167+ /* module: move to the instruction "lui v1, HI_16BIT_OF_MCOUNT" */
168+ ip = self_addr - 20;
169+ } else {
170+ /* kernel: move to the instruction "move ra, at" */
171+ ip = self_addr - 12;
172+ }
173+
174+ /* search the text until finding the non-store instruction or "s{d,w}
175+ * ra, offset(sp)" instruction */
176+ do {
177+ ip -= 4;
178+
179+ /* get the code at "ip": code = *(unsigned int *)ip; */
180+ safe_load_code(code, ip, faulted);
181+
182+ if (unlikely(faulted))
183+ return 0;
184+
185+ /* If we hit the non-store instruction before finding where the
186+ * ra is stored, then this is a leaf function and it does not
187+ * store the ra on the stack. */
188+ if ((code & S_R_SP) != S_R_SP)
189+ return parent_addr;
190+
191+ } while (((code & S_RA_SP) != S_RA_SP));
192+
193+ sp = fp + (code & OFFSET_MASK);
194+
195+ /* ra = *(unsigned long *)sp; */
196+ safe_load_stack(ra, sp, faulted);
197+ if (unlikely(faulted))
198+ return 0;
199+
200+ if (ra == parent)
201+ return sp;
202+ return 0;
203+}
204+
205+#endif
206+
207+/*
208+ * Hook the return address and push it in the stack of return addrs
209+ * in current thread info.
210+ */
211+void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr,
212+ unsigned long fp)
213+{
214+ unsigned long old;
215+ struct ftrace_graph_ent trace;
216+ unsigned long return_hooker = (unsigned long)
217+ &return_to_handler;
218+ int faulted;
219+
220+ if (unlikely(atomic_read(&current->tracing_graph_pause)))
221+ return;
222+
223+ /* "parent" is the stack address saved the return address of the caller
224+ * of _mcount.
225+ *
226+ * if the gcc < 4.5, a leaf function does not save the return address
227+ * in the stack address, so, we "emulate" one in _mcount's stack space,
228+ * and hijack it directly, but for a non-leaf function, it save the
229+ * return address to the its own stack space, we can not hijack it
230+ * directly, but need to find the real stack address,
231+ * ftrace_get_parent_addr() does it!
232+ *
233+ * if gcc>= 4.5, with the new -mmcount-ra-address option, for a
234+ * non-leaf function, the location of the return address will be saved
235+ * to $12 for us, and for a leaf function, only put a zero into $12. we
236+ * do it in ftrace_graph_caller of mcount.S.
237+ */
238+
239+ /* old = *parent; */
240+ safe_load_stack(old, parent, faulted);
241+ if (unlikely(faulted))
242+ goto out;
243+#ifndef KBUILD_MCOUNT_RA_ADDRESS
244+ parent = (unsigned long *)ftrace_get_parent_addr(self_addr, old,
245+ (unsigned long)parent,
246+ fp);
247+ /* If fails when getting the stack address of the non-leaf function's
248+ * ra, stop function graph tracer and return */
249+ if (parent == 0)
250+ goto out;
251+#endif
252+ /* *parent = return_hooker; */
253+ safe_store_stack(return_hooker, parent, faulted);
254+ if (unlikely(faulted))
255+ goto out;
256+
257+ if (ftrace_push_return_trace(old, self_addr, &trace.depth, fp) ==
258+ -EBUSY) {
259+ *parent = old;
260+ return;
261+ }
262+
263+ trace.func = self_addr;
264+
265+ /* Only trace if the calling function expects to */
266+ if (!ftrace_graph_entry(&trace)) {
267+ current->curr_ret_stack--;
268+ *parent = old;
269+ }
270+ return;
271+out:
272+ ftrace_graph_stop();
273+ WARN_ON(1);
274+}
275+#endif /* CONFIG_FUNCTION_GRAPH_TRACER */
arch/mips/kernel/irq.c+30−0
@@ -22,6 +22,7 @@ · 21 unmodified lines
2222 #include <linux/seq_file.h>
2323 #include <linux/kallsyms.h>
2424 #include <linux/kgdb.h>
25+#include <linux/ftrace.h>
2526
2627 #include <asm/atomic.h>
2728 #include <asm/system.h>
@@ -150,3 +151,32 @@ void __init init_IRQ(void) · 122 unmodified lines
150151 kgdb_early_setup = 1;
151152 #endif
152153 }
154+
155+/*
156+ * do_IRQ handles all normal device IRQ's (the special
157+ * SMP cross-CPU interrupts have their own specific
158+ * handlers).
159+ */
160+void __irq_entry do_IRQ(unsigned int irq)
161+{
162+ irq_enter();
163+ __DO_IRQ_SMTC_HOOK(irq);
164+ generic_handle_irq(irq);
165+ irq_exit();
166+}
167+
168+#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
169+/*
170+ * To avoid inefficient and in some cases pathological re-checking of
171+ * IRQ affinity, we have this variant that skips the affinity check.
172+ */
173+
174+void __irq_entry do_IRQ_no_affinity(unsigned int irq)
175+{
176+ irq_enter();
177+ __NO_AFFINITY_IRQ_SMTC_HOOK(irq);
178+ generic_handle_irq(irq);
179+ irq_exit();
180+}
181+
182+#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
arch/mips/kernel/mcount.S+189−0
@@ -0,0 +1,189 @@
1+/*
2+ * MIPS specific _mcount support
3+ *
4+ * This file is subject to the terms and conditions of the GNU General Public
5+ * License. See the file "COPYING" in the main directory of this archive for
6+ * more details.
7+ *
8+ * Copyright (C) 2009 Lemote Inc. & DSLab, Lanzhou University, China
9+ * Author: Wu Zhangjin <wuzj@lemote.com>
10+ */
11+
12+#include <asm/regdef.h>
13+#include <asm/stackframe.h>
14+#include <asm/ftrace.h>
15+
16+ .text
17+ .set noreorder
18+ .set noat
19+
20+ .macro MCOUNT_SAVE_REGS
21+ PTR_SUBU sp, PT_SIZE
22+ PTR_S ra, PT_R31(sp)
23+ PTR_S AT, PT_R1(sp)
24+ PTR_S a0, PT_R4(sp)
25+ PTR_S a1, PT_R5(sp)
26+ PTR_S a2, PT_R6(sp)
27+ PTR_S a3, PT_R7(sp)
28+#ifdef CONFIG_64BIT
29+ PTR_S a4, PT_R8(sp)
30+ PTR_S a5, PT_R9(sp)
31+ PTR_S a6, PT_R10(sp)
32+ PTR_S a7, PT_R11(sp)
33+#endif
34+ .endm
35+
36+ .macro MCOUNT_RESTORE_REGS
37+ PTR_L ra, PT_R31(sp)
38+ PTR_L AT, PT_R1(sp)
39+ PTR_L a0, PT_R4(sp)
40+ PTR_L a1, PT_R5(sp)
41+ PTR_L a2, PT_R6(sp)
42+ PTR_L a3, PT_R7(sp)
43+#ifdef CONFIG_64BIT
44+ PTR_L a4, PT_R8(sp)
45+ PTR_L a5, PT_R9(sp)
46+ PTR_L a6, PT_R10(sp)
47+ PTR_L a7, PT_R11(sp)
48+#endif
49+#ifdef CONFIG_64BIT
50+ PTR_ADDIU sp, PT_SIZE
51+#else
52+ PTR_ADDIU sp, (PT_SIZE + 8)
53+#endif
54+.endm
55+
56+ .macro RETURN_BACK
57+ jr ra
58+ move ra, AT
59+ .endm
60+
61+#ifdef CONFIG_DYNAMIC_FTRACE
62+
63+NESTED(ftrace_caller, PT_SIZE, ra)
64+ .globl _mcount
65+_mcount:
66+ b ftrace_stub
67+ nop
68+ lw t1, function_trace_stop
69+ bnez t1, ftrace_stub
70+ nop
71+
72+ MCOUNT_SAVE_REGS
73+#ifdef KBUILD_MCOUNT_RA_ADDRESS
74+ PTR_S t0, PT_R12(sp) /* t0 saved the location of the return address(at) by -mmcount-ra-address */
75+#endif
76+
77+ move a0, ra /* arg1: next ip, selfaddr */
78+ .globl ftrace_call
79+ftrace_call:
80+ nop /* a placeholder for the call to a real tracing function */
81+ move a1, AT /* arg2: the caller's next ip, parent */
82+
83+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
84+ .globl ftrace_graph_call
85+ftrace_graph_call:
86+ nop
87+ nop
88+#endif
89+
90+ MCOUNT_RESTORE_REGS
91+ .globl ftrace_stub
92+ftrace_stub:
93+ RETURN_BACK
94+ END(ftrace_caller)
95+
96+#else /* ! CONFIG_DYNAMIC_FTRACE */
97+
98+NESTED(_mcount, PT_SIZE, ra)
99+ lw t1, function_trace_stop
100+ bnez t1, ftrace_stub
101+ nop
102+ PTR_LA t1, ftrace_stub
103+ PTR_L t2, ftrace_trace_function /* Prepare t2 for (1) */
104+ bne t1, t2, static_trace
105+ nop
106+
107+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
108+ PTR_L t3, ftrace_graph_return
109+ bne t1, t3, ftrace_graph_caller
110+ nop
111+ PTR_LA t1, ftrace_graph_entry_stub
112+ PTR_L t3, ftrace_graph_entry
113+ bne t1, t3, ftrace_graph_caller
114+ nop
115+#endif
116+ b ftrace_stub
117+ nop
118+
119+static_trace:
120+ MCOUNT_SAVE_REGS
121+
122+ move a0, ra /* arg1: next ip, selfaddr */
123+ jalr t2 /* (1) call *ftrace_trace_function */
124+ move a1, AT /* arg2: the caller's next ip, parent */
125+
126+ MCOUNT_RESTORE_REGS
127+ .globl ftrace_stub
128+ftrace_stub:
129+ RETURN_BACK
130+ END(_mcount)
131+
132+#endif /* ! CONFIG_DYNAMIC_FTRACE */
133+
134+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
135+
136+NESTED(ftrace_graph_caller, PT_SIZE, ra)
137+#ifdef CONFIG_DYNAMIC_FTRACE
138+ PTR_L a1, PT_R31(sp) /* load the original ra from the stack */
139+#ifdef KBUILD_MCOUNT_RA_ADDRESS
140+ PTR_L t0, PT_R12(sp) /* load the original t0 from the stack */
141+#endif
142+#else
143+ MCOUNT_SAVE_REGS
144+ move a1, ra /* arg2: next ip, selfaddr */
145+#endif
146+
147+#ifdef KBUILD_MCOUNT_RA_ADDRESS
148+ bnez t0, 1f /* non-leaf func: t0 saved the location of the return address */
149+ nop
150+ PTR_LA t0, PT_R1(sp) /* leaf func: get the location of at(old ra) from our own stack */
151+1: move a0, t0 /* arg1: the location of the return address */
152+#else
153+ PTR_LA a0, PT_R1(sp) /* arg1: &AT -> a0 */
154+#endif
155+ jal prepare_ftrace_return
156+#ifdef CONFIG_FRAME_POINTER
157+ move a2, fp /* arg3: frame pointer */
158+#else
159+#ifdef CONFIG_64BIT
160+ PTR_LA a2, PT_SIZE(sp)
161+#else
162+ PTR_LA a2, (PT_SIZE+8)(sp)
163+#endif
164+#endif
165+
166+ MCOUNT_RESTORE_REGS
167+ RETURN_BACK
168+ END(ftrace_graph_caller)
169+
170+ .align 2
171+ .globl return_to_handler
172+return_to_handler:
173+ PTR_SUBU sp, PT_SIZE
174+ PTR_S v0, PT_R2(sp)
175+
176+ jal ftrace_return_to_handler
177+ PTR_S v1, PT_R3(sp)
178+
179+ /* restore the real parent address: v0 -> ra */
180+ move ra, v0
181+
182+ PTR_L v0, PT_R2(sp)
183+ PTR_L v1, PT_R3(sp)
184+ jr ra
185+ PTR_ADDIU sp, PT_SIZE
186+#endif /* CONFIG_FUNCTION_GRAPH_TRACER */
187+
188+ .set at
189+ .set reorder
arch/mips/kernel/mips_ksyms.c+5−0
@@ -13,6 +13,7 @@ · 12 unmodified lines
1313 #include <asm/checksum.h>
1414 #include <asm/pgtable.h>
1515 #include <asm/uaccess.h>
16+#include <asm/ftrace.h>
1617
1718 extern void *__bzero(void *__s, size_t __count);
1819 extern long __strncpy_from_user_nocheck_asm(char *__to,
@@ -51,3 +52,7 @@ EXPORT_SYMBOL(csum_partial_copy_nocheck); · 32 unmodified lines
5152 EXPORT_SYMBOL(__csum_partial_copy_user);
5253
5354 EXPORT_SYMBOL(invalid_pte_table);
55+#ifdef CONFIG_FUNCTION_TRACER
56+/* _mcount is defined in arch/mips/kernel/mcount.S */
57+EXPORT_SYMBOL(_mcount);
58+#endif
arch/mips/kernel/setup.c+21−23
@@ -58,8 +58,12 @@ EXPORT_SYMBOL(mips_machtype); · 57 unmodified lines
5858
5959 struct boot_mem_map boot_mem_map;
6060
61−static char command_line[CL_SIZE];
62− char arcs_cmdline[CL_SIZE]=CONFIG_CMDLINE;
61+static char __initdata command_line[COMMAND_LINE_SIZE];
62+char __initdata arcs_cmdline[COMMAND_LINE_SIZE];
63+
64+#ifdef CONFIG_CMDLINE_BOOL
65+static char __initdata builtin_cmdline[COMMAND_LINE_SIZE] = CONFIG_CMDLINE;
66+#endif
6367
6468 /*
6569 * mips_io_port_base is the begin of the address space to which x86 style
@@ -166,26 +170,8 @@ static unsigned long __init init_initrd(void) · 100 unmodified lines
166170 * already set up initrd_start and initrd_end. In these cases
167171 * perfom sanity checks and use them if all looks good.
168172 */
169− if (!initrd_start || initrd_end <= initrd_start) {
170−#ifdef CONFIG_PROBE_INITRD_HEADER
171− u32 *initrd_header;
172−
173− /*
174− * See if initrd has been added to the kernel image by
175− * arch/mips/boot/addinitrd.c. In that case a header is
176− * prepended to initrd and is made up by 8 bytes. The first
177− * word is a magic number and the second one is the size of
178− * initrd. Initrd start must be page aligned in any cases.
179− */
180− initrd_header = __va(PAGE_ALIGN(__pa_symbol(&_end) + 8)) - 8;
181− if (initrd_header[0] != 0x494E5244)
182− goto disable;
183− initrd_start = (unsigned long)(initrd_header + 2);
184− initrd_end = initrd_start + initrd_header[1];
185−#else
173+ if (!initrd_start || initrd_end <= initrd_start)
186174 goto disable;
187−#endif
188− }
189175
190176 if (initrd_start & ~PAGE_MASK) {
191177 pr_err("initrd start must be page aligned\n");
@@ -476,8 +462,20 @@ static void __init arch_mem_init(char **cmdline_p) · 284 unmodified lines
476462 pr_info("Determined physical RAM map:\n");
477463 print_memory_map();
478464
479− strlcpy(command_line, arcs_cmdline, sizeof(command_line));
480− strlcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
465+#ifdef CONFIG_CMDLINE_BOOL
466+#ifdef CONFIG_CMDLINE_OVERRIDE
467+ strlcpy(boot_command_line, builtin_cmdline, COMMAND_LINE_SIZE);
468+#else
469+ if (builtin_cmdline[0]) {
470+ strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE);
471+ strlcat(arcs_cmdline, builtin_cmdline, COMMAND_LINE_SIZE);
472+ }
473+ strlcpy(boot_command_line, arcs_cmdline, COMMAND_LINE_SIZE);
474+#endif
475+#else
476+ strlcpy(boot_command_line, arcs_cmdline, COMMAND_LINE_SIZE);
477+#endif
478+ strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
481479
482480 *cmdline_p = command_line;
483481
arch/mips/kernel/signal.c+46−0
@@ -35,6 +35,15 @@ · 34 unmodified lines
3535
3636 #include "signal-common.h"
3737
38+static int (*save_fp_context)(struct sigcontext __user *sc);
39+static int (*restore_fp_context)(struct sigcontext __user *sc);
40+
41+extern asmlinkage int _save_fp_context(struct sigcontext __user *sc);
42+extern asmlinkage int _restore_fp_context(struct sigcontext __user *sc);
43+
44+extern asmlinkage int fpu_emulator_save_context(struct sigcontext __user *sc);
45+extern asmlinkage int fpu_emulator_restore_context(struct sigcontext __user *sc);
46+
3847 /*
3948 * Horribly complicated - with the bloody RM9000 workarounds enabled
4049 * the signal trampolines is moving to the end of the structure so we can
@@ -709,3 +718,40 @@ asmlinkage void do_notify_resume(struct pt_regs *regs, void *unused, · 668 unmodified lines
709718 key_replace_session_keyring();
710719 }
711720 }
721+
722+#ifdef CONFIG_SMP
723+static int smp_save_fp_context(struct sigcontext __user *sc)
724+{
725+ return raw_cpu_has_fpu
726+ ? _save_fp_context(sc)
727+ : fpu_emulator_save_context(sc);
728+}
729+
730+static int smp_restore_fp_context(struct sigcontext __user *sc)
731+{
732+ return raw_cpu_has_fpu
733+ ? _restore_fp_context(sc)
734+ : fpu_emulator_restore_context(sc);
735+}
736+#endif
737+
738+static int signal_setup(void)
739+{
740+#ifdef CONFIG_SMP
741+ /* For now just do the cpu_has_fpu check when the functions are invoked */
742+ save_fp_context = smp_save_fp_context;
743+ restore_fp_context = smp_restore_fp_context;
744+#else
745+ if (cpu_has_fpu) {
746+ save_fp_context = _save_fp_context;
747+ restore_fp_context = _restore_fp_context;
748+ } else {
749+ save_fp_context = fpu_emulator_save_context;
750+ restore_fp_context = fpu_emulator_restore_context;
751+ }
752+#endif
753+
754+ return 0;
755+}
756+
757+arch_initcall(signal_setup);
arch/mips/kernel/signal32.c+24−0
@@ -35,6 +35,15 @@ · 34 unmodified lines
3535
3636 #include "signal-common.h"
3737
38+static int (*save_fp_context32)(struct sigcontext32 __user *sc);
39+static int (*restore_fp_context32)(struct sigcontext32 __user *sc);
40+
41+extern asmlinkage int _save_fp_context32(struct sigcontext32 __user *sc);
42+extern asmlinkage int _restore_fp_context32(struct sigcontext32 __user *sc);
43+
44+extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 __user *sc);
45+extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 __user *sc);
46+
3847 /*
3948 * Including <asm/unistd.h> would give use the 64-bit syscall numbers ...
4049 */
@@ -828,3 +837,18 @@ SYSCALL_DEFINE5(32_waitid, int, which, compat_pid_t, pid, · 787 unmodified lines
828837 info.si_code |= __SI_CHLD;
829838 return copy_siginfo_to_user32(uinfo, &info);
830839 }
840+
841+static int signal32_init(void)
842+{
843+ if (cpu_has_fpu) {
844+ save_fp_context32 = _save_fp_context32;
845+ restore_fp_context32 = _restore_fp_context32;
846+ } else {
847+ save_fp_context32 = fpu_emulator_save_context32;
848+ restore_fp_context32 = fpu_emulator_restore_context32;
849+ }
850+
851+ return 0;
852+}
853+
854+arch_initcall(signal32_init);
arch/mips/kernel/smp.c+2−1
@@ -32,6 +32,7 @@ · 31 unmodified lines
3232 #include <linux/cpumask.h>
3333 #include <linux/cpu.h>
3434 #include <linux/err.h>
35+#include <linux/ftrace.h>
3536
3637 #include <asm/atomic.h>
3738 #include <asm/cpu.h>
@@ -130,7 +131,7 @@ asmlinkage __cpuinit void start_secondary(void) · 92 unmodified lines
130131 /*
131132 * Call into both interrupt handlers, as we share the IPI for them
132133 */
133−void smp_call_function_interrupt(void)
134+void __irq_entry smp_call_function_interrupt(void)
134135 {
135136 irq_enter();
136137 generic_smp_call_function_single_interrupt();
arch/mips/kernel/smtc.c+14−7
@@ -25,6 +25,7 @@ · 24 unmodified lines
2525 #include <linux/interrupt.h>
2626 #include <linux/kernel_stat.h>
2727 #include <linux/module.h>
28+#include <linux/ftrace.h>
2829
2930 #include <asm/cpu.h>
3031 #include <asm/processor.h>
@@ -939,23 +940,29 @@ static void ipi_call_interrupt(void) · 908 unmodified lines
939940
940941 DECLARE_PER_CPU(struct clock_event_device, mips_clockevent_device);
941942
942−void ipi_decode(struct smtc_ipi *pipi)
943+static void __irq_entry smtc_clock_tick_interrupt(void)
943944 {
944945 unsigned int cpu = smp_processor_id();
945946 struct clock_event_device *cd;
947+ int irq = MIPS_CPU_IRQ_BASE + 1;
948+
949+ irq_enter();
950+ kstat_incr_irqs_this_cpu(irq, irq_to_desc(irq));
951+ cd = &per_cpu(mips_clockevent_device, cpu);
952+ cd->event_handler(cd);
953+ irq_exit();
954+}
955+
956+void ipi_decode(struct smtc_ipi *pipi)
957+{
946958 void *arg_copy = pipi->arg;
947959 int type_copy = pipi->type;
948− int irq = MIPS_CPU_IRQ_BASE + 1;
949960
950961 smtc_ipi_nq(&freeIPIq, pipi);
951962
952963 switch (type_copy) {
953964 case SMTC_CLOCK_TICK:
954− irq_enter();
955− kstat_incr_irqs_this_cpu(irq, irq_to_desc(irq));
956− cd = &per_cpu(mips_clockevent_device, cpu);
957− cd->event_handler(cd);
958− irq_exit();
965+ smtc_clock_tick_interrupt();
959966 break;
960967
961968 case LINUX_SMP_IPI:
arch/mips/kernel/traps.c+45−91
@@ -25,10 +25,12 @@ · 24 unmodified lines
2525 #include <linux/ptrace.h>
2626 #include <linux/kgdb.h>
2727 #include <linux/kdebug.h>
28+#include <linux/notifier.h>
2829
2930 #include <asm/bootinfo.h>
3031 #include <asm/branch.h>
3132 #include <asm/break.h>
33+#include <asm/cop2.h>
3234 #include <asm/cpu.h>
3335 #include <asm/dsp.h>
3436 #include <asm/fpu.h>
@@ -79,10 +81,6 @@ extern asmlinkage void handle_reserved(void); · 44 unmodified lines
7981 extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
8082 struct mips_fpu_struct *ctx, int has_fpu);
8183
82−#ifdef CONFIG_CPU_CAVIUM_OCTEON
83−extern asmlinkage void octeon_cop2_restore(struct octeon_cop2_state *task);
84−#endif
85−
8684 void (*board_be_init)(void);
8785 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
8886 void (*board_nmi_handler_setup)(void);
@@ -857,6 +855,44 @@ static void mt_ase_fp_affinity(void) · 768 unmodified lines
857855 #endif /* CONFIG_MIPS_MT_FPAFF */
858856 }
859857
858+/*
859+ * No lock; only written during early bootup by CPU 0.
860+ */
861+static RAW_NOTIFIER_HEAD(cu2_chain);
862+
863+int __ref register_cu2_notifier(struct notifier_block *nb)
864+{
865+ return raw_notifier_chain_register(&cu2_chain, nb);
866+}
867+
868+int cu2_notifier_call_chain(unsigned long val, void *v)
869+{
870+ return raw_notifier_call_chain(&cu2_chain, val, v);
871+}
872+
873+static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
874+ void *data)
875+{
876+ struct pt_regs *regs = data;
877+
878+ switch (action) {
879+ default:
880+ die_if_kernel("Unhandled kernel unaligned access or invalid "
881+ "instruction", regs);
882+ /* Fall through */
883+
884+ case CU2_EXCEPTION:
885+ force_sig(SIGILL, current);
886+ }
887+
888+ return NOTIFY_OK;
889+}
890+
891+static struct notifier_block default_cu2_notifier = {
892+ .notifier_call = default_cu2_call,
893+ .priority = 0x80000000, /* Run last */
894+};
895+
860896 asmlinkage void do_cpu(struct pt_regs *regs)
861897 {
862898 unsigned int __user *epc;
@@ -920,17 +956,9 @@ asmlinkage void do_cpu(struct pt_regs *regs) · 57 unmodified lines
920956 return;
921957
922958 case 2:
923−#ifdef CONFIG_CPU_CAVIUM_OCTEON
924− prefetch(&current->thread.cp2);
925− local_irq_save(flags);
926− KSTK_STATUS(current) |= ST0_CU2;
927− status = read_c0_status();
928− write_c0_status(status | ST0_CU2);
929− octeon_cop2_restore(&(current->thread.cp2));
930− write_c0_status(status & ~ST0_CU2);
931− local_irq_restore(flags);
932− return;
933−#endif
959+ raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
960+ break;
961+
934962 case 3:
935963 break;
936964 }
@@ -1367,77 +1395,6 @@ void *set_vi_handler(int n, vi_handler_t addr) · 430 unmodified lines
13671395 return set_vi_srs_handler(n, addr, 0);
13681396 }
13691397
1370−/*
1371− * This is used by native signal handling
1372− */
1373−asmlinkage int (*save_fp_context)(struct sigcontext __user *sc);
1374−asmlinkage int (*restore_fp_context)(struct sigcontext __user *sc);
1375−
1376−extern asmlinkage int _save_fp_context(struct sigcontext __user *sc);
1377−extern asmlinkage int _restore_fp_context(struct sigcontext __user *sc);
1378−
1379−extern asmlinkage int fpu_emulator_save_context(struct sigcontext __user *sc);
1380−extern asmlinkage int fpu_emulator_restore_context(struct sigcontext __user *sc);
1381−
1382−#ifdef CONFIG_SMP
1383−static int smp_save_fp_context(struct sigcontext __user *sc)
1384−{
1385− return raw_cpu_has_fpu
1386− ? _save_fp_context(sc)
1387− : fpu_emulator_save_context(sc);
1388−}
1389−
1390−static int smp_restore_fp_context(struct sigcontext __user *sc)
1391−{
1392− return raw_cpu_has_fpu
1393− ? _restore_fp_context(sc)
1394− : fpu_emulator_restore_context(sc);
1395−}
1396−#endif
1397−
1398−static inline void signal_init(void)
1399−{
1400−#ifdef CONFIG_SMP
1401− /* For now just do the cpu_has_fpu check when the functions are invoked */
1402− save_fp_context = smp_save_fp_context;
1403− restore_fp_context = smp_restore_fp_context;
1404−#else
1405− if (cpu_has_fpu) {
1406− save_fp_context = _save_fp_context;
1407− restore_fp_context = _restore_fp_context;
1408− } else {
1409− save_fp_context = fpu_emulator_save_context;
1410− restore_fp_context = fpu_emulator_restore_context;
1411− }
1412−#endif
1413−}
1414−
1415−#ifdef CONFIG_MIPS32_COMPAT
1416−
1417−/*
1418− * This is used by 32-bit signal stuff on the 64-bit kernel
1419− */
1420−asmlinkage int (*save_fp_context32)(struct sigcontext32 __user *sc);
1421−asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc);
1422−
1423−extern asmlinkage int _save_fp_context32(struct sigcontext32 __user *sc);
1424−extern asmlinkage int _restore_fp_context32(struct sigcontext32 __user *sc);
1425−
1426−extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 __user *sc);
1427−extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 __user *sc);
1428−
1429−static inline void signal32_init(void)
1430−{
1431− if (cpu_has_fpu) {
1432− save_fp_context32 = _save_fp_context32;
1433− restore_fp_context32 = _restore_fp_context32;
1434− } else {
1435− save_fp_context32 = fpu_emulator_save_context32;
1436− restore_fp_context32 = fpu_emulator_restore_context32;
1437− }
1438−}
1439−#endif
1440−
14411398 extern void cpu_cache_init(void);
14421399 extern void tlb_init(void);
14431400 extern void flush_tlb_handlers(void);
@@ -1751,13 +1708,10 @@ void __init trap_init(void) · 307 unmodified lines
17511708 else
17521709 memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80);
17531710
1754− signal_init();
1755−#ifdef CONFIG_MIPS32_COMPAT
1756− signal32_init();
1757−#endif
1758−
17591711 local_flush_icache_range(ebase, ebase + 0x400);
17601712 flush_tlb_handlers();
17611713
17621714 sort_extable(__start___dbe_table, __stop___dbe_table);
1715+
1716+ register_cu2_notifier(&default_cu2_notifier);
17631717 }
arch/mips/kernel/unaligned.c+18−7
@@ -81,6 +81,7 @@ · 80 unmodified lines
8181 #include <asm/asm.h>
8282 #include <asm/branch.h>
8383 #include <asm/byteorder.h>
84+#include <asm/cop2.h>
8485 #include <asm/inst.h>
8586 #include <asm/uaccess.h>
8687 #include <asm/system.h>
@@ -451,17 +452,27 @@ static void emulate_load_store_insn(struct pt_regs *regs, · 364 unmodified lines
451452 */
452453 goto sigbus;
453454
455+ /*
456+ * COP2 is available to implementor for application specific use.
457+ * It's up to applications to register a notifier chain and do
458+ * whatever they have to do, including possible sending of signals.
459+ */
454460 case lwc2_op:
461+ cu2_notifier_call_chain(CU2_LWC2_OP, regs);
462+ break;
463+
455464 case ldc2_op:
465+ cu2_notifier_call_chain(CU2_LDC2_OP, regs);
466+ break;
467+
456468 case swc2_op:
469+ cu2_notifier_call_chain(CU2_SWC2_OP, regs);
470+ break;
471+
457472 case sdc2_op:
458− /*
459− * These are the coprocessor 2 load/stores. The current
460− * implementations don't use cp2 and cp2 should always be
461− * disabled in c0_status. So send SIGILL.
462− * (No longer true: The Sony Praystation uses cp2 for
463− * 3D matrix operations. Dunno if that thingy has a MMU ...)
464− */
473+ cu2_notifier_call_chain(CU2_SDC2_OP, regs);
474+ break;
475+
465476 default:
466477 /*
467478 * Pheeee... We encountered an yet unknown instruction or
arch/mips/kernel/vmlinux.lds.S+1−0
@@ -46,6 +46,7 @@ SECTIONS · 45 unmodified lines
4646 SCHED_TEXT
4747 LOCK_TEXT
4848 KPROBES_TEXT
49+ IRQENTRY_TEXT
4950 *(.text.*)
5051 *(.fixup)
5152 *(.gnu.warning)
arch/mips/lasat/picvue_proc.c+68−45
@@ -4,12 +4,14 @@ · 3 unmodified lines
44 * Brian Murphy <brian.murphy@eicon.com>
55 *
66 */
7+#include <linux/bug.h>
78 #include <linux/kernel.h>
89 #include <linux/module.h>
910 #include <linux/init.h>
1011 #include <linux/errno.h>
1112
1213 #include <linux/proc_fs.h>
14+#include <linux/seq_file.h>
1315 #include <linux/interrupt.h>
1416
1517 #include <linux/timer.h>
@@ -38,12 +40,9 @@ static void pvc_display(unsigned long data) · 22 unmodified lines
3840
3941 static DECLARE_TASKLET(pvc_display_tasklet, &pvc_display, 0);
4042
41−static int pvc_proc_read_line(char *page, char **start,
42− off_t off, int count,
43− int *eof, void *data)
43+static int pvc_line_proc_show(struct seq_file *m, void *v)
4444 {
45− char *origpage = page;
46− int lineno = *(int *)data;
45+ int lineno = *(int *)m->private;
4746
4847 if (lineno < 0 || lineno > PVC_NLINES) {
4948 printk(KERN_WARNING "proc_read_line: invalid lineno %d\n", lineno);
@@ -51,45 +50,66 @@ static int pvc_proc_read_line(char *page, char **start, · 1 unmodified line
5150 }
5251
5352 mutex_lock(&pvc_mutex);
54− page += sprintf(page, "%s\n", pvc_lines[lineno]);
53+ seq_printf(m, "%s\n", pvc_lines[lineno]);
5554 mutex_unlock(&pvc_mutex);
5655
57− return page - origpage;
56+ return 0;
5857 }
5958
60−static int pvc_proc_write_line(struct file *file, const char *buffer,
61− unsigned long count, void *data)
59+static int pvc_line_proc_open(struct inode *inode, struct file *file)
6260 {
63− int origcount = count;
64− int lineno = *(int *)data;
61+ return single_open(file, pvc_line_proc_show, PDE(inode)->data);
62+}
6563
66− if (lineno < 0 || lineno > PVC_NLINES) {
67− printk(KERN_WARNING "proc_write_line: invalid lineno %d\n",
68− lineno);
69− return origcount;
70− }
64+static ssize_t pvc_line_proc_write(struct file *file, const char __user *buf,
65+ size_t count, loff_t *pos)
66+{
67+ int lineno = *(int *)PDE(file->f_path.dentry->d_inode)->data;
68+ char kbuf[PVC_LINELEN];
69+ size_t len;
70+
71+ BUG_ON(lineno < 0 || lineno > PVC_NLINES);
7172
72− if (count > PVC_LINELEN)
73− count = PVC_LINELEN;
73+ len = min(count, sizeof(kbuf) - 1);
74+ if (copy_from_user(kbuf, buf, len))
75+ return -EFAULT;
76+ kbuf[len] = '\0';
7477
75− if (buffer[count-1] == '\n')
76− count--;
78+ if (len > 0 && kbuf[len - 1] == '\n')
79+ len--;
7780
7881 mutex_lock(&pvc_mutex);
79− strncpy(pvc_lines[lineno], buffer, count);
80− pvc_lines[lineno][count] = '\0';
82+ strncpy(pvc_lines[lineno], kbuf, len);
83+ pvc_lines[lineno][len] = '\0';
8184 mutex_unlock(&pvc_mutex);
8285
8386 tasklet_schedule(&pvc_display_tasklet);
8487
85− return origcount;
88+ return count;
8689 }
8790
88−static int pvc_proc_write_scroll(struct file *file, const char *buffer,
89− unsigned long count, void *data)
91+static const struct file_operations pvc_line_proc_fops = {
92+ .owner = THIS_MODULE,
93+ .open = pvc_line_proc_open,
94+ .read = seq_read,
95+ .llseek = seq_lseek,
96+ .release = single_release,
97+ .write = pvc_line_proc_write,
98+};
99+
100+static ssize_t pvc_scroll_proc_write(struct file *file, const char __user *buf,
101+ size_t count, loff_t *pos)
90102 {
91− int origcount = count;
92− int cmd = simple_strtol(buffer, NULL, 10);
103+ char kbuf[42];
104+ size_t len;
105+ int cmd;
106+
107+ len = min(count, sizeof(kbuf) - 1);
108+ if (copy_from_user(kbuf, buf, len))
109+ return -EFAULT;
110+ kbuf[len] = '\0';
111+
112+ cmd = simple_strtol(kbuf, NULL, 10);
93113
94114 mutex_lock(&pvc_mutex);
95115 if (scroll_interval != 0)
@@ -110,22 +130,31 @@ static int pvc_proc_write_scroll(struct file *file, const char *buffer, · 14 unmodified lines
110130 }
111131 mutex_unlock(&pvc_mutex);
112132
113− return origcount;
133+ return count;
114134 }
115135
116−static int pvc_proc_read_scroll(char *page, char **start,
117− off_t off, int count,
118− int *eof, void *data)
136+static int pvc_scroll_proc_show(struct seq_file *m, void *v)
119137 {
120− char *origpage = page;
121−
122138 mutex_lock(&pvc_mutex);
123− page += sprintf(page, "%d\n", scroll_dir * scroll_interval);
139+ seq_printf(m, "%d\n", scroll_dir * scroll_interval);
124140 mutex_unlock(&pvc_mutex);
125141
126− return page - origpage;
142+ return 0;
127143 }
128144
145+static int pvc_scroll_proc_open(struct inode *inode, struct file *file)
146+{
147+ return single_open(file, pvc_scroll_proc_show, NULL);
148+}
149+
150+static const struct file_operations pvc_scroll_proc_fops = {
151+ .owner = THIS_MODULE,
152+ .open = pvc_scroll_proc_open,
153+ .read = seq_read,
154+ .llseek = seq_lseek,
155+ .release = single_release,
156+ .write = pvc_scroll_proc_write,
157+};
129158
130159 void pvc_proc_timerfunc(unsigned long data)
131160 {
@@ -163,22 +192,16 @@ static int __init pvc_proc_init(void) · 31 unmodified lines
163192 pvc_linedata[i] = i;
164193 }
165194 for (i = 0; i < PVC_NLINES; i++) {
166− proc_entry = create_proc_entry(pvc_linename[i], 0644,
167− pvc_display_dir);
195+ proc_entry = proc_create_data(pvc_linename[i], 0644, pvc_display_dir,
196+ &pvc_line_proc_fops, &pvc_linedata[i]);
168197 if (proc_entry == NULL)
169198 goto error;
170−
171− proc_entry->read_proc = pvc_proc_read_line;
172− proc_entry->write_proc = pvc_proc_write_line;
173− proc_entry->data = &pvc_linedata[i];
174199 }
175− proc_entry = create_proc_entry("scroll", 0644, pvc_display_dir);
200+ proc_entry = proc_create("scroll", 0644, pvc_display_dir,
201+ &pvc_scroll_proc_fops);
176202 if (proc_entry == NULL)
177203 goto error;
178204
179− proc_entry->write_proc = pvc_proc_write_scroll;
180− proc_entry->read_proc = pvc_proc_read_scroll;
181−
182205 init_timer(&timer);
183206 timer.function = pvc_proc_timerfunc;
184207
arch/mips/lasat/prom.c+2−2
@@ -100,8 +100,8 @@ void __init prom_init(void) · 99 unmodified lines
100100
101101 /* Get the command line */
102102 if (argc > 0) {
103− strncpy(arcs_cmdline, argv[0], CL_SIZE-1);
104− arcs_cmdline[CL_SIZE-1] = '\0';
103+ strncpy(arcs_cmdline, argv[0], COMMAND_LINE_SIZE-1);
104+ arcs_cmdline[COMMAND_LINE_SIZE-1] = '\0';
105105 }
106106
107107 /* Set the I/O base address */
arch/mips/lasat/sysctl.c+1−1
@@ -204,7 +204,7 @@ static ctl_table lasat_table[] = { · 203 unmodified lines
204204 .maxlen = sizeof(int),
205205 .mode = 0644,
206206 .proc_handler = proc_lasat_prid,
207−. },
207+ },
208208 #ifdef CONFIG_INET
209209 {
210210 .procname = "ipaddr",
arch/mips/loongson/Kconfig+81−27
@@ -1,31 +1,85 @@
11 choice
2− prompt "Machine Type"
3− depends on MACH_LOONGSON
2+ prompt "Machine Type"
3+ depends on MACH_LOONGSON
44
55 config LEMOTE_FULOONG2E
6− bool "Lemote Fuloong(2e) mini-PC"
7− select ARCH_SPARSEMEM_ENABLE
8− select CEVT_R4K
9− select CSRC_R4K
10− select SYS_HAS_CPU_LOONGSON2E
11− select DMA_NONCOHERENT
12− select BOOT_ELF32
13− select BOARD_SCACHE
14− select HW_HAS_PCI
15− select I8259
16− select ISA
17− select IRQ_CPU
18− select SYS_SUPPORTS_32BIT_KERNEL
19− select SYS_SUPPORTS_64BIT_KERNEL
20− select SYS_SUPPORTS_LITTLE_ENDIAN
21− select SYS_SUPPORTS_HIGHMEM
22− select SYS_HAS_EARLY_PRINTK
23− select GENERIC_HARDIRQS_NO__DO_IRQ
24− select GENERIC_ISA_DMA_SUPPORT_BROKEN
25− select CPU_HAS_WB
26− help
27− Lemote Fuloong(2e) mini-PC board based on the Chinese Loongson-2E CPU and
28− an FPGA northbridge
29−
30− Lemote Fuloong(2e) mini PC have a VIA686B south bridge.
6+ bool "Lemote Fuloong(2e) mini-PC"
7+ select ARCH_SPARSEMEM_ENABLE
8+ select CEVT_R4K
9+ select CSRC_R4K
10+ select SYS_HAS_CPU_LOONGSON2E
11+ select DMA_NONCOHERENT
12+ select BOOT_ELF32
13+ select BOARD_SCACHE
14+ select HW_HAS_PCI
15+ select I8259
16+ select ISA
17+ select IRQ_CPU
18+ select SYS_SUPPORTS_32BIT_KERNEL
19+ select SYS_SUPPORTS_64BIT_KERNEL
20+ select SYS_SUPPORTS_LITTLE_ENDIAN
21+ select SYS_SUPPORTS_HIGHMEM
22+ select SYS_HAS_EARLY_PRINTK
23+ select GENERIC_HARDIRQS_NO__DO_IRQ
24+ select GENERIC_ISA_DMA_SUPPORT_BROKEN
25+ select CPU_HAS_WB
26+ help
27+ Lemote Fuloong(2e) mini-PC board based on the Chinese Loongson-2E CPU and
28+ an FPGA northbridge
29+
30+ Lemote Fuloong(2e) mini PC have a VIA686B south bridge.
31+
32+config LEMOTE_MACH2F
33+ bool "Lemote Loongson 2F family machines"
34+ select ARCH_SPARSEMEM_ENABLE
35+ select BOARD_SCACHE
36+ select BOOT_ELF32
37+ select CEVT_R4K if ! MIPS_EXTERNAL_TIMER
38+ select CPU_HAS_WB
39+ select CS5536
40+ select CSRC_R4K if ! MIPS_EXTERNAL_TIMER
41+ select DMA_NONCOHERENT
42+ select GENERIC_HARDIRQS_NO__DO_IRQ
43+ select GENERIC_ISA_DMA_SUPPORT_BROKEN
44+ select HW_HAS_PCI
45+ select I8259
46+ select IRQ_CPU
47+ select ISA
48+ select SYS_HAS_CPU_LOONGSON2F
49+ select SYS_HAS_EARLY_PRINTK
50+ select SYS_SUPPORTS_32BIT_KERNEL
51+ select SYS_SUPPORTS_64BIT_KERNEL
52+ select SYS_SUPPORTS_HIGHMEM
53+ select SYS_SUPPORTS_LITTLE_ENDIAN
54+ help
55+ Lemote Loongson 2F family machines utilize the 2F revision of
56+ Loongson processor and the AMD CS5536 south bridge.
57+
58+ These family machines include fuloong2f mini PC, yeeloong2f notebook,
59+ LingLoong allinone PC and so forth.
3160 endchoice
61+
62+config CS5536
63+ bool
64+
65+config CS5536_MFGPT
66+ bool "CS5536 MFGPT Timer"
67+ depends on CS5536
68+ select MIPS_EXTERNAL_TIMER
69+ help
70+ This option enables the mfgpt0 timer of AMD CS5536.
71+
72+ If you want to enable the Loongson2 CPUFreq Driver, Please enable
73+ this option at first, otherwise, You will get wrong system time.
74+
75+ If unsure, say Yes.
76+
77+config LOONGSON_SUSPEND
78+ bool
79+ default y
80+ depends on CPU_SUPPORTS_CPUFREQ && SUSPEND
81+
82+config LOONGSON_UART_BASE
83+ bool
84+ default y
85+ depends on EARLY_PRINTK || SERIAL_8250
arch/mips/loongson/Makefile+6−0
@@ -9,3 +9,9 @@ obj-$(CONFIG_MACH_LOONGSON) += common/ · 8 unmodified lines
99 #
1010
1111 obj-$(CONFIG_LEMOTE_FULOONG2E) += fuloong-2e/
12+
13+#
14+# Lemote loongson2f family machines
15+#
16+
17+obj-$(CONFIG_LEMOTE_MACH2F) += lemote-2f/
arch/mips/loongson/common/Makefile+16−2
@@ -3,9 +3,23 @@ · 2 unmodified lines
33 #
44
55 obj-y += setup.o init.o cmdline.o env.o time.o reset.o irq.o \
6− pci.o bonito-irq.o mem.o machtype.o
6+ pci.o bonito-irq.o mem.o machtype.o platform.o
77
88 #
9−# Early printk support
9+# Serial port support
1010 #
1111 obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
12+obj-$(CONFIG_SERIAL_8250) += serial.o
13+obj-$(CONFIG_LOONGSON_UART_BASE) += uart_base.o
14+
15+#
16+# Enable CS5536 Virtual Support Module(VSM) to virtulize the PCI configure
17+# space
18+#
19+obj-$(CONFIG_CS5536) += cs5536/
20+
21+#
22+# Suspend Support
23+#
24+
25+obj-$(CONFIG_LOONGSON_SUSPEND) += pm.o
arch/mips/loongson/common/bonito-irq.c+8−5
@@ -12,18 +12,19 @@ · 11 unmodified lines
1212 * option) any later version.
1313 */
1414 #include <linux/interrupt.h>
15+#include <linux/compiler.h>
1516
1617 #include <loongson.h>
1718
1819 static inline void bonito_irq_enable(unsigned int irq)
1920 {
20− BONITO_INTENSET = (1 << (irq - BONITO_IRQ_BASE));
21+ LOONGSON_INTENSET = (1 << (irq - LOONGSON_IRQ_BASE));
2122 mmiowb();
2223 }
2324
2425 static inline void bonito_irq_disable(unsigned int irq)
2526 {
26− BONITO_INTENCLR = (1 << (irq - BONITO_IRQ_BASE));
27+ LOONGSON_INTENCLR = (1 << (irq - LOONGSON_IRQ_BASE));
2728 mmiowb();
2829 }
2930
@@ -35,7 +36,7 @@ static struct irq_chip bonito_irq_type = { · 5 unmodified lines
3536 .unmask = bonito_irq_enable,
3637 };
3738
38−static struct irqaction dma_timeout_irqaction = {
39+static struct irqaction __maybe_unused dma_timeout_irqaction = {
3940 .handler = no_action,
4041 .name = "dma_timeout",
4142 };
@@ -44,8 +45,10 @@ void bonito_irq_init(void) · 2 unmodified lines
4445 {
4546 u32 i;
4647
47− for (i = BONITO_IRQ_BASE; i < BONITO_IRQ_BASE + 32; i++)
48+ for (i = LOONGSON_IRQ_BASE; i < LOONGSON_IRQ_BASE + 32; i++)
4849 set_irq_chip_and_handler(i, &bonito_irq_type, handle_level_irq);
4950
50− setup_irq(BONITO_IRQ_BASE + 10, &dma_timeout_irqaction);
51+#ifdef CONFIG_CPU_LOONGSON2E
52+ setup_irq(LOONGSON_IRQ_BASE + 10, &dma_timeout_irqaction);
53+#endif
5154 }
arch/mips/loongson/common/cmdline.c+3−1
@@ -9,7 +9,7 @@ · 8 unmodified lines
99 * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
1010 * Author: Fuxin Zhang, zhangfx@lemote.com
1111 *
12− * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology
12+ * Copyright (C) 2009 Lemote Inc.
1313 * Author: Wu Zhangjin, wuzj@lemote.com
1414 *
1515 * This program is free software; you can redistribute it and/or modify it
@@ -49,4 +49,6 @@ void __init prom_init_cmdline(void) · 33 unmodified lines
4949 strcat(arcs_cmdline, " console=ttyS0,115200");
5050 if ((strstr(arcs_cmdline, "root=")) == NULL)
5151 strcat(arcs_cmdline, " root=/dev/hda1");
52+
53+ prom_init_machtype();
5254 }
arch/mips/loongson/common/cs5536/Makefile+13−0
@@ -0,0 +1,13 @@
1+#
2+# Makefile for CS5536 support.
3+#
4+
5+obj-$(CONFIG_CS5536) += cs5536_pci.o cs5536_ide.o cs5536_acc.o cs5536_ohci.o \
6+ cs5536_isa.o cs5536_ehci.o
7+
8+#
9+# Enable cs5536 mfgpt Timer
10+#
11+obj-$(CONFIG_CS5536_MFGPT) += cs5536_mfgpt.o
12+
13+EXTRA_CFLAGS += -Werror
arch/mips/loongson/common/cs5536/cs5536_acc.c+140−0
@@ -0,0 +1,140 @@
1+/*
2+ * the ACC Virtual Support Module of AMD CS5536
3+ *
4+ * Copyright (C) 2007 Lemote, Inc.
5+ * Author : jlliu, liujl@lemote.com
6+ *
7+ * Copyright (C) 2009 Lemote, Inc.
8+ * Author: Wu Zhangjin, wuzj@lemote.com
9+ *
10+ * This program is free software; you can redistribute it and/or modify it
11+ * under the terms of the GNU General Public License as published by the
12+ * Free Software Foundation; either version 2 of the License, or (at your
13+ * option) any later version.
14+ */
15+
16+#include <cs5536/cs5536.h>
17+#include <cs5536/cs5536_pci.h>
18+
19+void pci_acc_write_reg(int reg, u32 value)
20+{
21+ u32 hi = 0, lo = value;
22+
23+ switch (reg) {
24+ case PCI_COMMAND:
25+ _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
26+ if (value & PCI_COMMAND_MASTER)
27+ lo |= (0x03 << 8);
28+ else
29+ lo &= ~(0x03 << 8);
30+ _wrmsr(GLIU_MSR_REG(GLIU_PAE), hi, lo);
31+ break;
32+ case PCI_STATUS:
33+ if (value & PCI_STATUS_PARITY) {
34+ _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
35+ if (lo & SB_PARE_ERR_FLAG) {
36+ lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
37+ _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
38+ }
39+ }
40+ break;
41+ case PCI_BAR0_REG:
42+ if (value == PCI_BAR_RANGE_MASK) {
43+ _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
44+ lo |= SOFT_BAR_ACC_FLAG;
45+ _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
46+ } else if (value & 0x01) {
47+ value &= 0xfffffffc;
48+ hi = 0xA0000000 | ((value & 0x000ff000) >> 12);
49+ lo = 0x000fff80 | ((value & 0x00000fff) << 20);
50+ _wrmsr(GLIU_MSR_REG(GLIU_IOD_BM1), hi, lo);
51+ }
52+ break;
53+ case PCI_ACC_INT_REG:
54+ _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo);
55+ /* disable all the usb interrupt in PIC */
56+ lo &= ~(0xf << PIC_YSEL_LOW_ACC_SHIFT);
57+ if (value) /* enable all the acc interrupt in PIC */
58+ lo |= (CS5536_ACC_INTR << PIC_YSEL_LOW_ACC_SHIFT);
59+ _wrmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), hi, lo);
60+ break;
61+ default:
62+ break;
63+ }
64+}
65+
66+u32 pci_acc_read_reg(int reg)
67+{
68+ u32 hi, lo;
69+ u32 conf_data = 0;
70+
71+ switch (reg) {
72+ case PCI_VENDOR_ID:
73+ conf_data =
74+ CFG_PCI_VENDOR_ID(CS5536_ACC_DEVICE_ID, CS5536_VENDOR_ID);
75+ break;
76+ case PCI_COMMAND:
77+ _rdmsr(GLIU_MSR_REG(GLIU_IOD_BM1), &hi, &lo);
78+ if (((lo & 0xfff00000) || (hi & 0x000000ff))
79+ && ((hi & 0xf0000000) == 0xa0000000))
80+ conf_data |= PCI_COMMAND_IO;
81+ _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
82+ if ((lo & 0x300) == 0x300)
83+ conf_data |= PCI_COMMAND_MASTER;
84+ break;
85+ case PCI_STATUS:
86+ conf_data |= PCI_STATUS_66MHZ;
87+ conf_data |= PCI_STATUS_FAST_BACK;
88+ _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
89+ if (lo & SB_PARE_ERR_FLAG)
90+ conf_data |= PCI_STATUS_PARITY;
91+ conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
92+ break;
93+ case PCI_CLASS_REVISION:
94+ _rdmsr(ACC_MSR_REG(ACC_CAP), &hi, &lo);
95+ conf_data = lo & 0x000000ff;
96+ conf_data |= (CS5536_ACC_CLASS_CODE << 8);
97+ break;
98+ case PCI_CACHE_LINE_SIZE:
99+ conf_data =
100+ CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE,
101+ PCI_NORMAL_LATENCY_TIMER);
102+ break;
103+ case PCI_BAR0_REG:
104+ _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
105+ if (lo & SOFT_BAR_ACC_FLAG) {
106+ conf_data = CS5536_ACC_RANGE |
107+ PCI_BASE_ADDRESS_SPACE_IO;
108+ lo &= ~SOFT_BAR_ACC_FLAG;
109+ _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
110+ } else {
111+ _rdmsr(GLIU_MSR_REG(GLIU_IOD_BM1), &hi, &lo);
112+ conf_data = (hi & 0x000000ff) << 12;
113+ conf_data |= (lo & 0xfff00000) >> 20;
114+ conf_data |= 0x01;
115+ conf_data &= ~0x02;
116+ }
117+ break;
118+ case PCI_CARDBUS_CIS:
119+ conf_data = PCI_CARDBUS_CIS_POINTER;
120+ break;
121+ case PCI_SUBSYSTEM_VENDOR_ID:
122+ conf_data =
123+ CFG_PCI_VENDOR_ID(CS5536_ACC_SUB_ID, CS5536_SUB_VENDOR_ID);
124+ break;
125+ case PCI_ROM_ADDRESS:
126+ conf_data = PCI_EXPANSION_ROM_BAR;
127+ break;
128+ case PCI_CAPABILITY_LIST:
129+ conf_data = PCI_CAPLIST_USB_POINTER;
130+ break;
131+ case PCI_INTERRUPT_LINE:
132+ conf_data =
133+ CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_ACC_INTR);
134+ break;
135+ default:
136+ break;
137+ }
138+
139+ return conf_data;
140+}
arch/mips/loongson/common/cs5536/cs5536_ehci.c+158−0
@@ -0,0 +1,158 @@
1+/*
2+ * the EHCI Virtual Support Module of AMD CS5536
3+ *
4+ * Copyright (C) 2007 Lemote, Inc.
5+ * Author : jlliu, liujl@lemote.com
6+ *
7+ * Copyright (C) 2009 Lemote, Inc.
8+ * Author: Wu Zhangjin, wuzj@lemote.com
9+ *
10+ * This program is free software; you can redistribute it and/or modify it
11+ * under the terms of the GNU General Public License as published by the
12+ * Free Software Foundation; either version 2 of the License, or (at your
13+ * option) any later version.
14+ */
15+
16+#include <cs5536/cs5536.h>
17+#include <cs5536/cs5536_pci.h>
18+
19+void pci_ehci_write_reg(int reg, u32 value)
20+{
21+ u32 hi = 0, lo = value;
22+
23+ switch (reg) {
24+ case PCI_COMMAND:
25+ _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
26+ if (value & PCI_COMMAND_MASTER)
27+ hi |= PCI_COMMAND_MASTER;
28+ else
29+ hi &= ~PCI_COMMAND_MASTER;
30+
31+ if (value & PCI_COMMAND_MEMORY)
32+ hi |= PCI_COMMAND_MEMORY;
33+ else
34+ hi &= ~PCI_COMMAND_MEMORY;
35+ _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
36+ break;
37+ case PCI_STATUS:
38+ if (value & PCI_STATUS_PARITY) {
39+ _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
40+ if (lo & SB_PARE_ERR_FLAG) {
41+ lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
42+ _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
43+ }
44+ }
45+ break;
46+ case PCI_BAR0_REG:
47+ if (value == PCI_BAR_RANGE_MASK) {
48+ _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
49+ lo |= SOFT_BAR_EHCI_FLAG;
50+ _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
51+ } else if ((value & 0x01) == 0x00) {
52+ _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
53+
54+ value &= 0xfffffff0;
55+ hi = 0x40000000 | ((value & 0xff000000) >> 24);
56+ lo = 0x000fffff | ((value & 0x00fff000) << 8);
57+ _wrmsr(GLIU_MSR_REG(GLIU_P2D_BM4), hi, lo);
58+ }
59+ break;
60+ case PCI_EHCI_LEGSMIEN_REG:
61+ _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
62+ hi &= 0x003f0000;
63+ hi |= (value & 0x3f) << 16;
64+ _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
65+ break;
66+ case PCI_EHCI_FLADJ_REG:
67+ _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
68+ hi &= ~0x00003f00;
69+ hi |= value & 0x00003f00;
70+ _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo);
71+ break;
72+ default:
73+ break;
74+ }
75+}
76+
77+u32 pci_ehci_read_reg(int reg)
78+{
79+ u32 conf_data = 0;
80+ u32 hi, lo;
81+
82+ switch (reg) {
83+ case PCI_VENDOR_ID:
84+ conf_data =
85+ CFG_PCI_VENDOR_ID(CS5536_EHCI_DEVICE_ID, CS5536_VENDOR_ID);
86+ break;
87+ case PCI_COMMAND:
88+ _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
89+ if (hi & PCI_COMMAND_MASTER)
90+ conf_data |= PCI_COMMAND_MASTER;
91+ if (hi & PCI_COMMAND_MEMORY)
92+ conf_data |= PCI_COMMAND_MEMORY;
93+ break;
94+ case PCI_STATUS:
95+ conf_data |= PCI_STATUS_66MHZ;
96+ conf_data |= PCI_STATUS_FAST_BACK;
97+ _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
98+ if (lo & SB_PARE_ERR_FLAG)
99+ conf_data |= PCI_STATUS_PARITY;
100+ conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
101+ break;
102+ case PCI_CLASS_REVISION:
103+ _rdmsr(USB_MSR_REG(USB_CAP), &hi, &lo);
104+ conf_data = lo & 0x000000ff;
105+ conf_data |= (CS5536_EHCI_CLASS_CODE << 8);
106+ break;
107+ case PCI_CACHE_LINE_SIZE:
108+ conf_data =
109+ CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE,
110+ PCI_NORMAL_LATENCY_TIMER);
111+ break;
112+ case PCI_BAR0_REG:
113+ _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
114+ if (lo & SOFT_BAR_EHCI_FLAG) {
115+ conf_data = CS5536_EHCI_RANGE |
116+ PCI_BASE_ADDRESS_SPACE_MEMORY;
117+ lo &= ~SOFT_BAR_EHCI_FLAG;
118+ _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
119+ } else {
120+ _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
121+ conf_data = lo & 0xfffff000;
122+ }
123+ break;
124+ case PCI_CARDBUS_CIS:
125+ conf_data = PCI_CARDBUS_CIS_POINTER;
126+ break;
127+ case PCI_SUBSYSTEM_VENDOR_ID:
128+ conf_data =
129+ CFG_PCI_VENDOR_ID(CS5536_EHCI_SUB_ID, CS5536_SUB_VENDOR_ID);
130+ break;
131+ case PCI_ROM_ADDRESS:
132+ conf_data = PCI_EXPANSION_ROM_BAR;
133+ break;
134+ case PCI_CAPABILITY_LIST:
135+ conf_data = PCI_CAPLIST_USB_POINTER;
136+ break;
137+ case PCI_INTERRUPT_LINE:
138+ conf_data =
139+ CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR);
140+ break;
141+ case PCI_EHCI_LEGSMIEN_REG:
142+ _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
143+ conf_data = (hi & 0x003f0000) >> 16;
144+ break;
145+ case PCI_EHCI_LEGSMISTS_REG:
146+ _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
147+ conf_data = (hi & 0x3f000000) >> 24;
148+ break;
149+ case PCI_EHCI_FLADJ_REG:
150+ _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo);
151+ conf_data = hi & 0x00003f00;
152+ break;
153+ default:
154+ break;
155+ }
156+
157+ return conf_data;
158+}
arch/mips/loongson/common/cs5536/cs5536_ide.c+179−0
@@ -0,0 +1,179 @@
1+/*
2+ * the IDE Virtual Support Module of AMD CS5536
3+ *
4+ * Copyright (C) 2007 Lemote, Inc.
5+ * Author : jlliu, liujl@lemote.com
6+ *
7+ * Copyright (C) 2009 Lemote, Inc.
8+ * Author: Wu Zhangjin, wuzj@lemote.com
9+ *
10+ * This program is free software; you can redistribute it and/or modify it
11+ * under the terms of the GNU General Public License as published by the
12+ * Free Software Foundation; either version 2 of the License, or (at your
13+ * option) any later version.
14+ */
15+
16+#include <cs5536/cs5536.h>
17+#include <cs5536/cs5536_pci.h>
18+
19+void pci_ide_write_reg(int reg, u32 value)
20+{
21+ u32 hi = 0, lo = value;
22+
23+ switch (reg) {
24+ case PCI_COMMAND:
25+ _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
26+ if (value & PCI_COMMAND_MASTER)
27+ lo |= (0x03 << 4);
28+ else
29+ lo &= ~(0x03 << 4);
30+ _wrmsr(GLIU_MSR_REG(GLIU_PAE), hi, lo);
31+ break;
32+ case PCI_STATUS:
33+ if (value & PCI_STATUS_PARITY) {
34+ _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
35+ if (lo & SB_PARE_ERR_FLAG) {
36+ lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
37+ _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
38+ }
39+ }
40+ break;
41+ case PCI_CACHE_LINE_SIZE:
42+ value &= 0x0000ff00;
43+ _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);
44+ hi &= 0xffffff00;
45+ hi |= (value >> 8);
46+ _wrmsr(SB_MSR_REG(SB_CTRL), hi, lo);
47+ break;
48+ case PCI_BAR4_REG:
49+ if (value == PCI_BAR_RANGE_MASK) {
50+ _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
51+ lo |= SOFT_BAR_IDE_FLAG;
52+ _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
53+ } else if (value & 0x01) {
54+ lo = (value & 0xfffffff0) | 0x1;
55+ _wrmsr(IDE_MSR_REG(IDE_IO_BAR), hi, lo);
56+
57+ value &= 0xfffffffc;
58+ hi = 0x60000000 | ((value & 0x000ff000) >> 12);
59+ lo = 0x000ffff0 | ((value & 0x00000fff) << 20);
60+ _wrmsr(GLIU_MSR_REG(GLIU_IOD_BM2), hi, lo);
61+ }
62+ break;
63+ case PCI_IDE_CFG_REG:
64+ if (value == CS5536_IDE_FLASH_SIGNATURE) {
65+ _rdmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), &hi, &lo);
66+ lo |= 0x01;
67+ _wrmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), hi, lo);
68+ } else
69+ _wrmsr(IDE_MSR_REG(IDE_CFG), hi, lo);
70+ break;
71+ case PCI_IDE_DTC_REG:
72+ _wrmsr(IDE_MSR_REG(IDE_DTC), hi, lo);
73+ break;
74+ case PCI_IDE_CAST_REG:
75+ _wrmsr(IDE_MSR_REG(IDE_CAST), hi, lo);
76+ break;
77+ case PCI_IDE_ETC_REG:
78+ _wrmsr(IDE_MSR_REG(IDE_ETC), hi, lo);
79+ break;
80+ case PCI_IDE_PM_REG:
81+ _wrmsr(IDE_MSR_REG(IDE_INTERNAL_PM), hi, lo);
82+ break;
83+ default:
84+ break;
85+ }
86+}
87+
88+u32 pci_ide_read_reg(int reg)
89+{
90+ u32 conf_data = 0;
91+ u32 hi, lo;
92+
93+ switch (reg) {
94+ case PCI_VENDOR_ID:
95+ conf_data =
96+ CFG_PCI_VENDOR_ID(CS5536_IDE_DEVICE_ID, CS5536_VENDOR_ID);
97+ break;
98+ case PCI_COMMAND:
99+ _rdmsr(IDE_MSR_REG(IDE_IO_BAR), &hi, &lo);
100+ if (lo & 0xfffffff0)
101+ conf_data |= PCI_COMMAND_IO;
102+ _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo);
103+ if ((lo & 0x30) == 0x30)
104+ conf_data |= PCI_COMMAND_MASTER;
105+ break;
106+ case PCI_STATUS:
107+ conf_data |= PCI_STATUS_66MHZ;
108+ conf_data |= PCI_STATUS_FAST_BACK;
109+ _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
110+ if (lo & SB_PARE_ERR_FLAG)
111+ conf_data |= PCI_STATUS_PARITY;
112+ conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
113+ break;
114+ case PCI_CLASS_REVISION:
115+ _rdmsr(IDE_MSR_REG(IDE_CAP), &hi, &lo);
116+ conf_data = lo & 0x000000ff;
117+ conf_data |= (CS5536_IDE_CLASS_CODE << 8);
118+ break;
119+ case PCI_CACHE_LINE_SIZE:
120+ _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);
121+ hi &= 0x000000f8;
122+ conf_data = CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, hi);
123+ break;
124+ case PCI_BAR4_REG:
125+ _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
126+ if (lo & SOFT_BAR_IDE_FLAG) {
127+ conf_data = CS5536_IDE_RANGE |
128+ PCI_BASE_ADDRESS_SPACE_IO;
129+ lo &= ~SOFT_BAR_IDE_FLAG;
130+ _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
131+ } else {
132+ _rdmsr(IDE_MSR_REG(IDE_IO_BAR), &hi, &lo);
133+ conf_data = lo & 0xfffffff0;
134+ conf_data |= 0x01;
135+ conf_data &= ~0x02;
136+ }
137+ break;
138+ case PCI_CARDBUS_CIS:
139+ conf_data = PCI_CARDBUS_CIS_POINTER;
140+ break;
141+ case PCI_SUBSYSTEM_VENDOR_ID:
142+ conf_data =
143+ CFG_PCI_VENDOR_ID(CS5536_IDE_SUB_ID, CS5536_SUB_VENDOR_ID);
144+ break;
145+ case PCI_ROM_ADDRESS:
146+ conf_data = PCI_EXPANSION_ROM_BAR;
147+ break;
148+ case PCI_CAPABILITY_LIST:
149+ conf_data = PCI_CAPLIST_POINTER;
150+ break;
151+ case PCI_INTERRUPT_LINE:
152+ conf_data =
153+ CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_IDE_INTR);
154+ break;
155+ case PCI_IDE_CFG_REG:
156+ _rdmsr(IDE_MSR_REG(IDE_CFG), &hi, &lo);
157+ conf_data = lo;
158+ break;
159+ case PCI_IDE_DTC_REG:
160+ _rdmsr(IDE_MSR_REG(IDE_DTC), &hi, &lo);
161+ conf_data = lo;
162+ break;
163+ case PCI_IDE_CAST_REG:
164+ _rdmsr(IDE_MSR_REG(IDE_CAST), &hi, &lo);
165+ conf_data = lo;
166+ break;
167+ case PCI_IDE_ETC_REG:
168+ _rdmsr(IDE_MSR_REG(IDE_ETC), &hi, &lo);
169+ conf_data = lo;
170+ case PCI_IDE_PM_REG:
171+ _rdmsr(IDE_MSR_REG(IDE_INTERNAL_PM), &hi, &lo);
172+ conf_data = lo;
173+ break;
174+ default:
175+ break;
176+ }
177+
178+ return conf_data;
179+}
arch/mips/loongson/common/cs5536/cs5536_isa.c+316−0
@@ -0,0 +1,316 @@
1+/*
2+ * the ISA Virtual Support Module of AMD CS5536
3+ *
4+ * Copyright (C) 2007 Lemote, Inc.
5+ * Author : jlliu, liujl@lemote.com
6+ *
7+ * Copyright (C) 2009 Lemote, Inc.
8+ * Author: Wu Zhangjin, wuzj@lemote.com
9+ *
10+ * This program is free software; you can redistribute it and/or modify it
11+ * under the terms of the GNU General Public License as published by the
12+ * Free Software Foundation; either version 2 of the License, or (at your
13+ * option) any later version.
14+ */
15+
16+#include <cs5536/cs5536.h>
17+#include <cs5536/cs5536_pci.h>
18+
19+/* common variables for PCI_ISA_READ/WRITE_BAR */
20+static const u32 divil_msr_reg[6] = {
21+ DIVIL_MSR_REG(DIVIL_LBAR_SMB), DIVIL_MSR_REG(DIVIL_LBAR_GPIO),
22+ DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), DIVIL_MSR_REG(DIVIL_LBAR_IRQ),
23+ DIVIL_MSR_REG(DIVIL_LBAR_PMS), DIVIL_MSR_REG(DIVIL_LBAR_ACPI),
24+};
25+
26+static const u32 soft_bar_flag[6] = {
27+ SOFT_BAR_SMB_FLAG, SOFT_BAR_GPIO_FLAG, SOFT_BAR_MFGPT_FLAG,
28+ SOFT_BAR_IRQ_FLAG, SOFT_BAR_PMS_FLAG, SOFT_BAR_ACPI_FLAG,
29+};
30+
31+static const u32 sb_msr_reg[6] = {
32+ SB_MSR_REG(SB_R0), SB_MSR_REG(SB_R1), SB_MSR_REG(SB_R2),
33+ SB_MSR_REG(SB_R3), SB_MSR_REG(SB_R4), SB_MSR_REG(SB_R5),
34+};
35+
36+static const u32 bar_space_range[6] = {
37+ CS5536_SMB_RANGE, CS5536_GPIO_RANGE, CS5536_MFGPT_RANGE,
38+ CS5536_IRQ_RANGE, CS5536_PMS_RANGE, CS5536_ACPI_RANGE,
39+};
40+
41+static const int bar_space_len[6] = {
42+ CS5536_SMB_LENGTH, CS5536_GPIO_LENGTH, CS5536_MFGPT_LENGTH,
43+ CS5536_IRQ_LENGTH, CS5536_PMS_LENGTH, CS5536_ACPI_LENGTH,
44+};
45+
46+/*
47+ * enable the divil module bar space.
48+ *
49+ * For all the DIVIL module LBAR, you should control the DIVIL LBAR reg
50+ * and the RCONFx(0~5) reg to use the modules.
51+ */
52+static void divil_lbar_enable(void)
53+{
54+ u32 hi, lo;
55+ int offset;
56+
57+ /*
58+ * The DIVIL IRQ is not used yet. and make the RCONF0 reserved.
59+ */
60+
61+ for (offset = DIVIL_LBAR_SMB; offset <= DIVIL_LBAR_PMS; offset++) {
62+ _rdmsr(DIVIL_MSR_REG(offset), &hi, &lo);
63+ hi |= 0x01;
64+ _wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), hi, lo);
65+ }
66+}
67+
68+/*
69+ * disable the divil module bar space.
70+ */
71+static void divil_lbar_disable(void)
72+{
73+ u32 hi, lo;
74+ int offset;
75+
76+ for (offset = DIVIL_LBAR_SMB; offset <= DIVIL_LBAR_PMS; offset++) {
77+ _rdmsr(DIVIL_MSR_REG(offset), &hi, &lo);
78+ hi &= ~0x01;
79+ _wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), hi, lo);
80+ }
81+}
82+
83+/*
84+ * BAR write: write value to the n BAR
85+ */
86+
87+void pci_isa_write_bar(int n, u32 value)
88+{
89+ u32 hi = 0, lo = value;
90+
91+ if (value == PCI_BAR_RANGE_MASK) {
92+ _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
93+ lo |= soft_bar_flag[n];
94+ _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
95+ } else if (value & 0x01) {
96+ /* NATIVE reg */
97+ hi = 0x0000f001;
98+ lo &= bar_space_range[n];
99+ _wrmsr(divil_msr_reg[n], hi, lo);
100+
101+ /* RCONFx is 4bytes in units for I/O space */
102+ hi = ((value & 0x000ffffc) << 12) |
103+ ((bar_space_len[n] - 4) << 12) | 0x01;
104+ lo = ((value & 0x000ffffc) << 12) | 0x01;
105+ _wrmsr(sb_msr_reg[n], hi, lo);
106+ }
107+}
108+
109+/*
110+ * BAR read: read the n BAR
111+ */
112+
113+u32 pci_isa_read_bar(int n)
114+{
115+ u32 conf_data = 0;
116+ u32 hi, lo;
117+
118+ _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
119+ if (lo & soft_bar_flag[n]) {
120+ conf_data = bar_space_range[n] | PCI_BASE_ADDRESS_SPACE_IO;
121+ lo &= ~soft_bar_flag[n];
122+ _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
123+ } else {
124+ _rdmsr(divil_msr_reg[n], &hi, &lo);
125+ conf_data = lo & bar_space_range[n];
126+ conf_data |= 0x01;
127+ conf_data &= ~0x02;
128+ }
129+ return conf_data;
130+}
131+
132+/*
133+ * isa_write: ISA write transfer
134+ *
135+ * We assume that this is not a bus master transfer.
136+ */
137+void pci_isa_write_reg(int reg, u32 value)
138+{
139+ u32 hi = 0, lo = value;
140+ u32 temp;
141+
142+ switch (reg) {
143+ case PCI_COMMAND:
144+ if (value & PCI_COMMAND_IO)
145+ divil_lbar_enable();
146+ else
147+ divil_lbar_disable();
148+ break;
149+ case PCI_STATUS:
150+ _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
151+ temp = lo & 0x0000ffff;
152+ if ((value & PCI_STATUS_SIG_TARGET_ABORT) &&
153+ (lo & SB_TAS_ERR_EN))
154+ temp |= SB_TAS_ERR_FLAG;
155+
156+ if ((value & PCI_STATUS_REC_TARGET_ABORT) &&
157+ (lo & SB_TAR_ERR_EN))
158+ temp |= SB_TAR_ERR_FLAG;
159+
160+ if ((value & PCI_STATUS_REC_MASTER_ABORT)
161+ && (lo & SB_MAR_ERR_EN))
162+ temp |= SB_MAR_ERR_FLAG;
163+
164+ if ((value & PCI_STATUS_DETECTED_PARITY)
165+ && (lo & SB_PARE_ERR_EN))
166+ temp |= SB_PARE_ERR_FLAG;
167+
168+ lo = temp;
169+ _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
170+ break;
171+ case PCI_CACHE_LINE_SIZE:
172+ value &= 0x0000ff00;
173+ _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);
174+ hi &= 0xffffff00;
175+ hi |= (value >> 8);
176+ _wrmsr(SB_MSR_REG(SB_CTRL), hi, lo);
177+ break;
178+ case PCI_BAR0_REG:
179+ pci_isa_write_bar(0, value);
180+ break;
181+ case PCI_BAR1_REG:
182+ pci_isa_write_bar(1, value);
183+ break;
184+ case PCI_BAR2_REG:
185+ pci_isa_write_bar(2, value);
186+ break;
187+ case PCI_BAR3_REG:
188+ pci_isa_write_bar(3, value);
189+ break;
190+ case PCI_BAR4_REG:
191+ pci_isa_write_bar(4, value);
192+ break;
193+ case PCI_BAR5_REG:
194+ pci_isa_write_bar(5, value);
195+ break;
196+ case PCI_UART1_INT_REG:
197+ _rdmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), &hi, &lo);
198+ /* disable uart1 interrupt in PIC */
199+ lo &= ~(0xf << 24);
200+ if (value) /* enable uart1 interrupt in PIC */
201+ lo |= (CS5536_UART1_INTR << 24);
202+ _wrmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), hi, lo);
203+ break;
204+ case PCI_UART2_INT_REG:
205+ _rdmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), &hi, &lo);
206+ /* disable uart2 interrupt in PIC */
207+ lo &= ~(0xf << 28);
208+ if (value) /* enable uart2 interrupt in PIC */
209+ lo |= (CS5536_UART2_INTR << 28);
210+ _wrmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), hi, lo);
211+ break;
212+ case PCI_ISA_FIXUP_REG:
213+ if (value) {
214+ /* enable the TARGET ABORT/MASTER ABORT etc. */
215+ _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
216+ lo |= 0x00000063;
217+ _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
218+ }
219+
220+ default:
221+ /* ALL OTHER PCI CONFIG SPACE HEADER IS NOT IMPLEMENTED. */
222+ break;
223+ }
224+}
225+
226+/*
227+ * isa_read: ISA read transfers
228+ *
229+ * We assume that this is not a bus master transfer.
230+ */
231+u32 pci_isa_read_reg(int reg)
232+{
233+ u32 conf_data = 0;
234+ u32 hi, lo;
235+
236+ switch (reg) {
237+ case PCI_VENDOR_ID:
238+ conf_data =
239+ CFG_PCI_VENDOR_ID(CS5536_ISA_DEVICE_ID, CS5536_VENDOR_ID);
240+ break;
241+ case PCI_COMMAND:
242+ /* we just check the first LBAR for the IO enable bit, */
243+ /* maybe we should changed later. */
244+ _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), &hi, &lo);
245+ if (hi & 0x01)
246+ conf_data |= PCI_COMMAND_IO;
247+ break;
248+ case PCI_STATUS:
249+ conf_data |= PCI_STATUS_66MHZ;
250+ conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
251+ conf_data |= PCI_STATUS_FAST_BACK;
252+
253+ _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
254+ if (lo & SB_TAS_ERR_FLAG)
255+ conf_data |= PCI_STATUS_SIG_TARGET_ABORT;
256+ if (lo & SB_TAR_ERR_FLAG)
257+ conf_data |= PCI_STATUS_REC_TARGET_ABORT;
258+ if (lo & SB_MAR_ERR_FLAG)
259+ conf_data |= PCI_STATUS_REC_MASTER_ABORT;
260+ if (lo & SB_PARE_ERR_FLAG)
261+ conf_data |= PCI_STATUS_DETECTED_PARITY;
262+ break;
263+ case PCI_CLASS_REVISION:
264+ _rdmsr(GLCP_MSR_REG(GLCP_CHIP_REV_ID), &hi, &lo);
265+ conf_data = lo & 0x000000ff;
266+ conf_data |= (CS5536_ISA_CLASS_CODE << 8);
267+ break;
268+ case PCI_CACHE_LINE_SIZE:
269+ _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo);
270+ hi &= 0x000000f8;
271+ conf_data = CFG_PCI_CACHE_LINE_SIZE(PCI_BRIDGE_HEADER_TYPE, hi);
272+ break;
273+ /*
274+ * we only use the LBAR of DIVIL, no RCONF used.
275+ * all of them are IO space.
276+ */
277+ case PCI_BAR0_REG:
278+ return pci_isa_read_bar(0);
279+ break;
280+ case PCI_BAR1_REG:
281+ return pci_isa_read_bar(1);
282+ break;
283+ case PCI_BAR2_REG:
284+ return pci_isa_read_bar(2);
285+ break;
286+ case PCI_BAR3_REG:
287+ break;
288+ case PCI_BAR4_REG:
289+ return pci_isa_read_bar(4);
290+ break;
291+ case PCI_BAR5_REG:
292+ return pci_isa_read_bar(5);
293+ break;
294+ case PCI_CARDBUS_CIS:
295+ conf_data = PCI_CARDBUS_CIS_POINTER;
296+ break;
297+ case PCI_SUBSYSTEM_VENDOR_ID:
298+ conf_data =
299+ CFG_PCI_VENDOR_ID(CS5536_ISA_SUB_ID, CS5536_SUB_VENDOR_ID);
300+ break;
301+ case PCI_ROM_ADDRESS:
302+ conf_data = PCI_EXPANSION_ROM_BAR;
303+ break;
304+ case PCI_CAPABILITY_LIST:
305+ conf_data = PCI_CAPLIST_POINTER;
306+ break;
307+ case PCI_INTERRUPT_LINE:
308+ /* no interrupt used here */
309+ conf_data = CFG_PCI_INTERRUPT_LINE(0x00, 0x00);
310+ break;
311+ default:
312+ break;
313+ }
314+
315+ return conf_data;
316+}
arch/mips/loongson/common/cs5536/cs5536_mfgpt.c+217−0
@@ -0,0 +1,217 @@
1+/*
2+ * CS5536 General timer functions
3+ *
4+ * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
5+ * Author: Yanhua, yanh@lemote.com
6+ *
7+ * Copyright (C) 2009 Lemote Inc.
8+ * Author: Wu zhangjin, wuzj@lemote.com
9+ *
10+ * Reference: AMD Geode(TM) CS5536 Companion Device Data Book
11+ *
12+ * This program is free software; you can redistribute it and/or modify it
13+ * under the terms of the GNU General Public License as published by the
14+ * Free Software Foundation; either version 2 of the License, or (at your
15+ * option) any later version.
16+ */
17+
18+#include <linux/io.h>
19+#include <linux/init.h>
20+#include <linux/module.h>
21+#include <linux/jiffies.h>
22+#include <linux/spinlock.h>
23+#include <linux/interrupt.h>
24+#include <linux/clockchips.h>
25+
26+#include <asm/time.h>
27+
28+#include <cs5536/cs5536_mfgpt.h>
29+
30+DEFINE_SPINLOCK(mfgpt_lock);
31+EXPORT_SYMBOL(mfgpt_lock);
32+
33+static u32 mfgpt_base;
34+
35+/*
36+ * Initialize the MFGPT timer.
37+ *
38+ * This is also called after resume to bring the MFGPT into operation again.
39+ */
40+
41+/* disable counter */
42+void disable_mfgpt0_counter(void)
43+{
44+ outw(inw(MFGPT0_SETUP) & 0x7fff, MFGPT0_SETUP);
45+}
46+EXPORT_SYMBOL(disable_mfgpt0_counter);
47+
48+/* enable counter, comparator2 to event mode, 14.318MHz clock */
49+void enable_mfgpt0_counter(void)
50+{
51+ outw(0xe310, MFGPT0_SETUP);
52+}
53+EXPORT_SYMBOL(enable_mfgpt0_counter);
54+
55+static void init_mfgpt_timer(enum clock_event_mode mode,
56+ struct clock_event_device *evt)
57+{
58+ spin_lock(&mfgpt_lock);
59+
60+ switch (mode) {
61+ case CLOCK_EVT_MODE_PERIODIC:
62+ outw(COMPARE, MFGPT0_CMP2); /* set comparator2 */
63+ outw(0, MFGPT0_CNT); /* set counter to 0 */
64+ enable_mfgpt0_counter();
65+ break;
66+
67+ case CLOCK_EVT_MODE_SHUTDOWN:
68+ case CLOCK_EVT_MODE_UNUSED:
69+ if (evt->mode == CLOCK_EVT_MODE_PERIODIC ||
70+ evt->mode == CLOCK_EVT_MODE_ONESHOT)
71+ disable_mfgpt0_counter();
72+ break;
73+
74+ case CLOCK_EVT_MODE_ONESHOT:
75+ /* The oneshot mode have very high deviation, Not use it! */
76+ break;
77+
78+ case CLOCK_EVT_MODE_RESUME:
79+ /* Nothing to do here */
80+ break;
81+ }
82+ spin_unlock(&mfgpt_lock);
83+}
84+
85+static struct clock_event_device mfgpt_clockevent = {
86+ .name = "mfgpt",
87+ .features = CLOCK_EVT_FEAT_PERIODIC,
88+ .set_mode = init_mfgpt_timer,
89+ .irq = CS5536_MFGPT_INTR,
90+};
91+
92+static irqreturn_t timer_interrupt(int irq, void *dev_id)
93+{
94+ u32 basehi;
95+
96+ /*
97+ * get MFGPT base address
98+ *
99+ * NOTE: do not remove me, it's need for the value of mfgpt_base is
100+ * variable
101+ */
102+ _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), &basehi, &mfgpt_base);
103+
104+ /* ack */
105+ outw(inw(MFGPT0_SETUP) | 0x4000, MFGPT0_SETUP);
106+
107+ mfgpt_clockevent.event_handler(&mfgpt_clockevent);
108+
109+ return IRQ_HANDLED;
110+}
111+
112+static struct irqaction irq5 = {
113+ .handler = timer_interrupt,
114+ .flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_TIMER,
115+ .name = "timer"
116+};
117+
118+/*
119+ * Initialize the conversion factor and the min/max deltas of the clock event
120+ * structure and register the clock event source with the framework.
121+ */
122+void __init setup_mfgpt0_timer(void)
123+{
124+ u32 basehi;
125+ struct clock_event_device *cd = &mfgpt_clockevent;
126+ unsigned int cpu = smp_processor_id();
127+
128+ cd->cpumask = cpumask_of(cpu);
129+ clockevent_set_clock(cd, MFGPT_TICK_RATE);
130+ cd->max_delta_ns = clockevent_delta2ns(0xffff, cd);
131+ cd->min_delta_ns = clockevent_delta2ns(0xf, cd);
132+
133+ /* Enable MFGPT0 Comparator 2 Output to the Interrupt Mapper */
134+ _wrmsr(DIVIL_MSR_REG(MFGPT_IRQ), 0, 0x100);
135+
136+ /* Enable Interrupt Gate 5 */
137+ _wrmsr(DIVIL_MSR_REG(PIC_ZSEL_LOW), 0, 0x50000);
138+
139+ /* get MFGPT base address */
140+ _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), &basehi, &mfgpt_base);
141+
142+ clockevents_register_device(cd);
143+
144+ setup_irq(CS5536_MFGPT_INTR, &irq5);
145+}
146+
147+/*
148+ * Since the MFGPT overflows every tick, its not very useful
149+ * to just read by itself. So use jiffies to emulate a free
150+ * running counter:
151+ */
152+static cycle_t mfgpt_read(struct clocksource *cs)
153+{
154+ unsigned long flags;
155+ int count;
156+ u32 jifs;
157+ static int old_count;
158+ static u32 old_jifs;
159+
160+ spin_lock_irqsave(&mfgpt_lock, flags);
161+ /*
162+ * Although our caller may have the read side of xtime_lock,
163+ * this is now a seqlock, and we are cheating in this routine
164+ * by having side effects on state that we cannot undo if
165+ * there is a collision on the seqlock and our caller has to
166+ * retry. (Namely, old_jifs and old_count.) So we must treat
167+ * jiffies as volatile despite the lock. We read jiffies
168+ * before latching the timer count to guarantee that although
169+ * the jiffies value might be older than the count (that is,
170+ * the counter may underflow between the last point where
171+ * jiffies was incremented and the point where we latch the
172+ * count), it cannot be newer.
173+ */
174+ jifs = jiffies;
175+ /* read the count */
176+ count = inw(MFGPT0_CNT);
177+
178+ /*
179+ * It's possible for count to appear to go the wrong way for this
180+ * reason:
181+ *
182+ * The timer counter underflows, but we haven't handled the resulting
183+ * interrupt and incremented jiffies yet.
184+ *
185+ * Previous attempts to handle these cases intelligently were buggy, so
186+ * we just do the simple thing now.
187+ */
188+ if (count < old_count && jifs == old_jifs)
189+ count = old_count;
190+
191+ old_count = count;
192+ old_jifs = jifs;
193+
194+ spin_unlock_irqrestore(&mfgpt_lock, flags);
195+
196+ return (cycle_t) (jifs * COMPARE) + count;
197+}
198+
199+static struct clocksource clocksource_mfgpt = {
200+ .name = "mfgpt",
201+ .rating = 120, /* Functional for real use, but not desired */
202+ .read = mfgpt_read,
203+ .mask = CLOCKSOURCE_MASK(32),
204+ .mult = 0,
205+ .shift = 22,
206+};
207+
208+int __init init_mfgpt_clocksource(void)
209+{
210+ if (num_possible_cpus() > 1) /* MFGPT does not scale! */
211+ return 0;
212+
213+ clocksource_mfgpt.mult = clocksource_hz2mult(MFGPT_TICK_RATE, 22);
214+ return clocksource_register(&clocksource_mfgpt);
215+}
216+
217+arch_initcall(init_mfgpt_clocksource);
arch/mips/loongson/common/cs5536/cs5536_ohci.c+147−0
@@ -0,0 +1,147 @@
1+/*
2+ * the OHCI Virtual Support Module of AMD CS5536
3+ *
4+ * Copyright (C) 2007 Lemote, Inc.
5+ * Author : jlliu, liujl@lemote.com
6+ *
7+ * Copyright (C) 2009 Lemote, Inc.
8+ * Author: Wu Zhangjin, wuzj@lemote.com
9+ *
10+ * This program is free software; you can redistribute it and/or modify it
11+ * under the terms of the GNU General Public License as published by the
12+ * Free Software Foundation; either version 2 of the License, or (at your
13+ * option) any later version.
14+ */
15+
16+#include <cs5536/cs5536.h>
17+#include <cs5536/cs5536_pci.h>
18+
19+void pci_ohci_write_reg(int reg, u32 value)
20+{
21+ u32 hi = 0, lo = value;
22+
23+ switch (reg) {
24+ case PCI_COMMAND:
25+ _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
26+ if (value & PCI_COMMAND_MASTER)
27+ hi |= PCI_COMMAND_MASTER;
28+ else
29+ hi &= ~PCI_COMMAND_MASTER;
30+
31+ if (value & PCI_COMMAND_MEMORY)
32+ hi |= PCI_COMMAND_MEMORY;
33+ else
34+ hi &= ~PCI_COMMAND_MEMORY;
35+ _wrmsr(USB_MSR_REG(USB_OHCI), hi, lo);
36+ break;
37+ case PCI_STATUS:
38+ if (value & PCI_STATUS_PARITY) {
39+ _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
40+ if (lo & SB_PARE_ERR_FLAG) {
41+ lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
42+ _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
43+ }
44+ }
45+ break;
46+ case PCI_BAR0_REG:
47+ if (value == PCI_BAR_RANGE_MASK) {
48+ _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
49+ lo |= SOFT_BAR_OHCI_FLAG;
50+ _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
51+ } else if ((value & 0x01) == 0x00) {
52+ _wrmsr(USB_MSR_REG(USB_OHCI), hi, lo);
53+
54+ value &= 0xfffffff0;
55+ hi = 0x40000000 | ((value & 0xff000000) >> 24);
56+ lo = 0x000fffff | ((value & 0x00fff000) << 8);
57+ _wrmsr(GLIU_MSR_REG(GLIU_P2D_BM3), hi, lo);
58+ }
59+ break;
60+ case PCI_OHCI_INT_REG:
61+ _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo);
62+ lo &= ~(0xf << PIC_YSEL_LOW_USB_SHIFT);
63+ if (value) /* enable all the usb interrupt in PIC */
64+ lo |= (CS5536_USB_INTR << PIC_YSEL_LOW_USB_SHIFT);
65+ _wrmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), hi, lo);
66+ break;
67+ default:
68+ break;
69+ }
70+}
71+
72+u32 pci_ohci_read_reg(int reg)
73+{
74+ u32 conf_data = 0;
75+ u32 hi, lo;
76+
77+ switch (reg) {
78+ case PCI_VENDOR_ID:
79+ conf_data =
80+ CFG_PCI_VENDOR_ID(CS5536_OHCI_DEVICE_ID, CS5536_VENDOR_ID);
81+ break;
82+ case PCI_COMMAND:
83+ _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
84+ if (hi & PCI_COMMAND_MASTER)
85+ conf_data |= PCI_COMMAND_MASTER;
86+ if (hi & PCI_COMMAND_MEMORY)
87+ conf_data |= PCI_COMMAND_MEMORY;
88+ break;
89+ case PCI_STATUS:
90+ conf_data |= PCI_STATUS_66MHZ;
91+ conf_data |= PCI_STATUS_FAST_BACK;
92+ _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
93+ if (lo & SB_PARE_ERR_FLAG)
94+ conf_data |= PCI_STATUS_PARITY;
95+ conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
96+ break;
97+ case PCI_CLASS_REVISION:
98+ _rdmsr(USB_MSR_REG(USB_CAP), &hi, &lo);
99+ conf_data = lo & 0x000000ff;
100+ conf_data |= (CS5536_OHCI_CLASS_CODE << 8);
101+ break;
102+ case PCI_CACHE_LINE_SIZE:
103+ conf_data =
104+ CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE,
105+ PCI_NORMAL_LATENCY_TIMER);
106+ break;
107+ case PCI_BAR0_REG:
108+ _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
109+ if (lo & SOFT_BAR_OHCI_FLAG) {
110+ conf_data = CS5536_OHCI_RANGE |
111+ PCI_BASE_ADDRESS_SPACE_MEMORY;
112+ lo &= ~SOFT_BAR_OHCI_FLAG;
113+ _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
114+ } else {
115+ _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
116+ conf_data = lo & 0xffffff00;
117+ conf_data &= ~0x0000000f; /* 32bit mem */
118+ }
119+ break;
120+ case PCI_CARDBUS_CIS:
121+ conf_data = PCI_CARDBUS_CIS_POINTER;
122+ break;
123+ case PCI_SUBSYSTEM_VENDOR_ID:
124+ conf_data =
125+ CFG_PCI_VENDOR_ID(CS5536_OHCI_SUB_ID, CS5536_SUB_VENDOR_ID);
126+ break;
127+ case PCI_ROM_ADDRESS:
128+ conf_data = PCI_EXPANSION_ROM_BAR;
129+ break;
130+ case PCI_CAPABILITY_LIST:
131+ conf_data = PCI_CAPLIST_USB_POINTER;
132+ break;
133+ case PCI_INTERRUPT_LINE:
134+ conf_data =
135+ CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR);
136+ break;
137+ case PCI_OHCI_INT_REG:
138+ _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo);
139+ if ((lo & 0x00000f00) == CS5536_USB_INTR)
140+ conf_data = 1;
141+ break;
142+ default:
143+ break;
144+ }
145+
146+ return conf_data;
147+}
arch/mips/loongson/common/cs5536/cs5536_pci.c+87−0
@@ -0,0 +1,87 @@
1+/*
2+ * read/write operation to the PCI config space of CS5536
3+ *
4+ * Copyright (C) 2007 Lemote, Inc.
5+ * Author : jlliu, liujl@lemote.com
6+ *
7+ * Copyright (C) 2009 Lemote, Inc.
8+ * Author: Wu Zhangjin, wuzj@lemote.com
9+ *
10+ * This program is free software; you can redistribute it and/or modify it
11+ * under the terms of the GNU General Public License as published by the
12+ * Free Software Foundation; either version 2 of the License, or (at your
13+ * option) any later version.
14+ *
15+ * the Virtual Support Module(VSM) for virtulizing the PCI
16+ * configure space are defined in cs5536_modulename.c respectively,
17+ *
18+ * after this virtulizing, user can access the PCI configure space
19+ * directly as a normal multi-function PCI device which follows
20+ * the PCI-2.2 spec.
21+ */
22+
23+#include <linux/types.h>
24+#include <cs5536/cs5536_vsm.h>
25+
26+enum {
27+ CS5536_FUNC_START = -1,
28+ CS5536_ISA_FUNC,
29+ reserved_func,
30+ CS5536_IDE_FUNC,
31+ CS5536_ACC_FUNC,
32+ CS5536_OHCI_FUNC,
33+ CS5536_EHCI_FUNC,
34+ CS5536_FUNC_END,
35+};
36+
37+static const cs5536_pci_vsm_write vsm_conf_write[] = {
38+ [CS5536_ISA_FUNC] pci_isa_write_reg,
39+ [reserved_func] NULL,
40+ [CS5536_IDE_FUNC] pci_ide_write_reg,
41+ [CS5536_ACC_FUNC] pci_acc_write_reg,
42+ [CS5536_OHCI_FUNC] pci_ohci_write_reg,
43+ [CS5536_EHCI_FUNC] pci_ehci_write_reg,
44+};
45+
46+static const cs5536_pci_vsm_read vsm_conf_read[] = {
47+ [CS5536_ISA_FUNC] pci_isa_read_reg,
48+ [reserved_func] NULL,
49+ [CS5536_IDE_FUNC] pci_ide_read_reg,
50+ [CS5536_ACC_FUNC] pci_acc_read_reg,
51+ [CS5536_OHCI_FUNC] pci_ohci_read_reg,
52+ [CS5536_EHCI_FUNC] pci_ehci_read_reg,
53+};
54+
55+/*
56+ * write to PCI config space and transfer it to MSR write.
57+ */
58+void cs5536_pci_conf_write4(int function, int reg, u32 value)
59+{
60+ if ((function <= CS5536_FUNC_START) || (function >= CS5536_FUNC_END))
61+ return;
62+ if ((reg < 0) || (reg > 0x100) || ((reg & 0x03) != 0))
63+ return;
64+
65+ if (vsm_conf_write[function] != NULL)
66+ vsm_conf_write[function](reg, value);
67+}
68+
69+/*
70+ * read PCI config space and transfer it to MSR access.
71+ */
72+u32 cs5536_pci_conf_read4(int function, int reg)
73+{
74+ u32 data = 0;
75+
76+ if ((function <= CS5536_FUNC_START) || (function >= CS5536_FUNC_END))
77+ return 0;
78+ if ((reg < 0) || ((reg & 0x03) != 0))
79+ return 0;
80+ if (reg > 0x100)
81+ return 0xffffffff;
82+
83+ if (vsm_conf_read[function] != NULL)
84+ data = vsm_conf_read[function](reg);
85+
86+ return data;
87+}
arch/mips/loongson/common/early_printk.c+10−7
@@ -1,7 +1,7 @@
11 /* early printk support
22 *
33 * Copyright (c) 2009 Philippe Vachon <philippe@cowpig.ca>
4− * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology
4+ * Copyright (c) 2009 Lemote Inc.
55 * Author: Wu Zhangjin, wuzj@lemote.com
66 *
77 * This program is free software; you can redistribute it and/or modify it
@@ -12,26 +12,29 @@ · 4 unmodified lines
1212 #include <linux/serial_reg.h>
1313
1414 #include <loongson.h>
15−#include <machine.h>
1615
1716 #define PORT(base, offset) (u8 *)(base + offset)
1817
19−static inline unsigned int serial_in(phys_addr_t base, int offset)
18+static inline unsigned int serial_in(unsigned char *base, int offset)
2019 {
2120 return readb(PORT(base, offset));
2221 }
2322
24−static inline void serial_out(phys_addr_t base, int offset, int value)
23+static inline void serial_out(unsigned char *base, int offset, int value)
2524 {
2625 writeb(value, PORT(base, offset));
2726 }
2827
2928 void prom_putchar(char c)
3029 {
31− phys_addr_t uart_base =
32− (phys_addr_t) ioremap_nocache(LOONGSON_UART_BASE, 8);
30+ int timeout;
31+ unsigned char *uart_base;
3332
34− while ((serial_in(uart_base, UART_LSR) & UART_LSR_THRE) == 0)
33+ uart_base = (unsigned char *)_loongson_uart_base;
34+ timeout = 1024;
35+
36+ while (((serial_in(uart_base, UART_LSR) & UART_LSR_THRE) == 0) &&
37+ (timeout-- > 0))
3538 ;
3639
3740 serial_out(uart_base, UART_TX, c);
arch/mips/loongson/common/env.c+3−0
@@ -17,11 +17,14 @@ · 16 unmodified lines
1717 * Free Software Foundation; either version 2 of the License, or (at your
1818 * option) any later version.
1919 */
20+#include <linux/module.h>
21+
2022 #include <asm/bootinfo.h>
2123
2224 #include <loongson.h>
2325
2426 unsigned long bus_clock, cpu_clock_freq;
27+EXPORT_SYMBOL(cpu_clock_freq);
2528 unsigned long memsize, highmemsize;
2629
2730 /* pmon passes arguments in 32bit pointers */
arch/mips/loongson/common/init.c+14−5
@@ -1,5 +1,5 @@
11 /*
2− * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology
2+ * Copyright (C) 2009 Lemote Inc.
33 * Author: Wu Zhangjin, wuzj@lemote.com
44 *
55 * This program is free software; you can redistribute it and/or modify it
@@ -10,19 +10,28 @@ · 4 unmodified lines
1010
1111 #include <linux/bootmem.h>
1212
13−#include <asm/bootinfo.h>
14−
1513 #include <loongson.h>
1614
15+/* Loongson CPU address windows config space base address */
16+unsigned long __maybe_unused _loongson_addrwincfg_base;
17+
1718 void __init prom_init(void)
1819 {
19− /* init base address of io space */
20+ /* init base address of io space */
2021 set_io_port_base((unsigned long)
21− ioremap(BONITO_PCIIO_BASE, BONITO_PCIIO_SIZE));
22+ ioremap(LOONGSON_PCIIO_BASE, LOONGSON_PCIIO_SIZE));
23+
24+#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
25+ _loongson_addrwincfg_base = (unsigned long)
26+ ioremap(LOONGSON_ADDRWINCFG_BASE, LOONGSON_ADDRWINCFG_SIZE);
27+#endif
2228
2329 prom_init_cmdline();
2430 prom_init_env();
2531 prom_init_memory();
32+
33+ /*init the uart base address */
34+ prom_init_uart_base();
2635 }
2736
2837 void __init prom_free_prom_memory(void)
arch/mips/loongson/common/irq.c+6−6
@@ -20,21 +20,21 @@ void bonito_irqdispatch(void) · 19 unmodified lines
2020 int i;
2121
2222 /* workaround the IO dma problem: let cpu looping to allow DMA finish */
23− int_status = BONITO_INTISR;
23+ int_status = LOONGSON_INTISR;
2424 if (int_status & (1 << 10)) {
2525 while (int_status & (1 << 10)) {
2626 udelay(1);
27− int_status = BONITO_INTISR;
27+ int_status = LOONGSON_INTISR;
2828 }
2929 }
3030
3131 /* Get pending sources, masked by current enables */
32− int_status = BONITO_INTISR & BONITO_INTEN;
32+ int_status = LOONGSON_INTISR & LOONGSON_INTEN;
3333
3434 if (int_status != 0) {
3535 i = __ffs(int_status);
3636 int_status &= ~(1 << i);
37− do_IRQ(BONITO_IRQ_BASE + i);
37+ do_IRQ(LOONGSON_IRQ_BASE + i);
3838 }
3939 }
4040
@@ -60,13 +60,13 @@ void __init arch_init_irq(void) · 19 unmodified lines
6060 set_irq_trigger_mode();
6161
6262 /* no steer */
63− BONITO_INTSTEER = 0;
63+ LOONGSON_INTSTEER = 0;
6464
6565 /*
6666 * Mask out all interrupt by writing "1" to all bit position in
6767 * the interrupt reset reg.
6868 */
69− BONITO_INTENCLR = ~0;
69+ LOONGSON_INTENCLR = ~0;
7070
7171 /* machine specific irq init */
7272 mach_init_irq();
arch/mips/loongson/common/machtype.c+17−8
@@ -15,6 +15,9 @@ · 14 unmodified lines
1515 #include <loongson.h>
1616 #include <machine.h>
1717
18+/* please ensure the length of the machtype string is less than 50 */
19+#define MACHTYPE_LEN 50
20+
1821 static const char *system_types[] = {
1922 [MACH_LOONGSON_UNKNOWN] "unknown loongson machine",
2023 [MACH_LEMOTE_FL2E] "lemote-fuloong-2e-box",
@@ -22,29 +25,35 @@ static const char *system_types[] = { · 1 unmodified line
2225 [MACH_LEMOTE_ML2F7] "lemote-mengloong-2f-7inches",
2326 [MACH_LEMOTE_YL2F89] "lemote-yeeloong-2f-8.9inches",
2427 [MACH_DEXXON_GDIUM2F10] "dexxon-gidum-2f-10inches",
28+ [MACH_LEMOTE_NAS] "lemote-nas-2f",
29+ [MACH_LEMOTE_LL2F] "lemote-lynloong-2f",
2530 [MACH_LOONGSON_END] NULL,
2631 };
2732
2833 const char *get_system_type(void)
2934 {
30− if (mips_machtype == MACH_UNKNOWN)
31− mips_machtype = LOONGSON_MACHTYPE;
32−
3335 return system_types[mips_machtype];
3436 }
3537
36−static __init int machtype_setup(char *str)
38+void __init prom_init_machtype(void)
3739 {
40+ char *p, str[MACHTYPE_LEN];
3841 int machtype = MACH_LEMOTE_FL2E;
3942
40− if (!str)
41− return -EINVAL;
43+ mips_machtype = LOONGSON_MACHTYPE;
44+
45+ p = strstr(arcs_cmdline, "machtype=");
46+ if (!p)
47+ return;
48+ p += strlen("machtype=");
49+ strncpy(str, p, MACHTYPE_LEN);
50+ p = strstr(str, " ");
51+ if (p)
52+ *p = '\0';
4253
4354 for (; system_types[machtype]; machtype++)
4455 if (strstr(system_types[machtype], str)) {
4556 mips_machtype = machtype;
4657 break;
4758 }
48− return 0;
4959 }
50−__setup("machtype=", machtype_setup);
arch/mips/loongson/common/mem.c+87−4
@@ -12,15 +12,40 @@ · 11 unmodified lines
1212
1313 #include <loongson.h>
1414 #include <mem.h>
15+#include <pci.h>
1516
1617 void __init prom_init_memory(void)
1718 {
1819 add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM);
20+
21+ add_memory_region(memsize << 20, LOONGSON_PCI_MEM_START - (memsize <<
22+ 20), BOOT_MEM_RESERVED);
23+#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
24+ {
25+ int bit;
26+
27+ bit = fls(memsize + highmemsize);
28+ if (bit != ffs(memsize + highmemsize))
29+ bit += 20;
30+ else
31+ bit = bit + 20 - 1;
32+
33+ /* set cpu window3 to map CPU to DDR: 2G -> 2G */
34+ LOONGSON_ADDRWIN_CPUTODDR(ADDRWIN_WIN3, 0x80000000ul,
35+ 0x80000000ul, (1 << bit));
36+ mmiowb();
37+ }
38+#endif /* !CONFIG_CPU_SUPPORTS_ADDRWINCFG */
39+
1940 #ifdef CONFIG_64BIT
20− if (highmemsize > 0)
21− add_memory_region(LOONGSON_HIGHMEM_START,
22− highmemsize << 20, BOOT_MEM_RAM);
23−#endif /* CONFIG_64BIT */
41+ if (highmemsize > 0)
42+ add_memory_region(LOONGSON_HIGHMEM_START,
43+ highmemsize << 20, BOOT_MEM_RAM);
44+
45+ add_memory_region(LOONGSON_PCI_MEM_END + 1, LOONGSON_HIGHMEM_START -
46+ LOONGSON_PCI_MEM_END - 1, BOOT_MEM_RESERVED);
47+
48+#endif /* !CONFIG_64BIT */
2449 }
2550
2651 /* override of arch/mips/mm/cache.c: __uncached_access */
@@ -33,3 +58,61 @@ int __uncached_access(struct file *file, unsigned long addr) · 6 unmodified lines
3358 ((addr >= LOONGSON_MMIO_MEM_START) &&
3459 (addr < LOONGSON_MMIO_MEM_END));
3560 }
61+
62+#ifdef CONFIG_CPU_SUPPORTS_UNCACHED_ACCELERATED
63+
64+#include <linux/pci.h>
65+#include <linux/sched.h>
66+#include <asm/current.h>
67+
68+static unsigned long uca_start, uca_end;
69+
70+pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
71+ unsigned long size, pgprot_t vma_prot)
72+{
73+ unsigned long offset = pfn << PAGE_SHIFT;
74+ unsigned long end = offset + size;
75+
76+ if (__uncached_access(file, offset)) {
77+ if (((uca_start && offset) >= uca_start) &&
78+ (end <= uca_end))
79+ return __pgprot((pgprot_val(vma_prot) &
80+ ~_CACHE_MASK) |
81+ _CACHE_UNCACHED_ACCELERATED);
82+ else
83+ return pgprot_noncached(vma_prot);
84+ }
85+ return vma_prot;
86+}
87+
88+static int __init find_vga_mem_init(void)
89+{
90+ struct pci_dev *dev = 0;
91+ struct resource *r;
92+ int idx;
93+
94+ if (uca_start)
95+ return 0;
96+
97+ for_each_pci_dev(dev) {
98+ if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) {
99+ for (idx = 0; idx < PCI_NUM_RESOURCES; idx++) {
100+ r = &dev->resource[idx];
101+ if (!r->start && r->end)
102+ continue;
103+ if (r->flags & IORESOURCE_IO)
104+ continue;
105+ if (r->flags & IORESOURCE_MEM) {
106+ uca_start = r->start;
107+ uca_end = r->end;
108+ return 0;
109+ }
110+ }
111+ }
112+ }
113+
114+ return 0;
115+}
116+
117+late_initcall(find_vga_mem_init);
118+#endif /* !CONFIG_CPU_SUPPORTS_UNCACHED_ACCELERATED */
arch/mips/loongson/common/pci.c+14−6
@@ -27,7 +27,7 @@ static struct resource loongson_pci_io_resource = { · 26 unmodified lines
2727 };
2828
2929 static struct pci_controller loongson_pci_controller = {
30− .pci_ops = &bonito64_pci_ops,
30+ .pci_ops = &loongson_pci_ops,
3131 .io_resource = &loongson_pci_io_resource,
3232 .mem_resource = &loongson_pci_mem_resource,
3333 .mem_offset = 0x00000000UL,
@@ -44,15 +44,15 @@ static void __init setup_pcimap(void) · 10 unmodified lines
4444 * pcimap: PCI_MAP2 PCI_Mem_Lo2 PCI_Mem_Lo1 PCI_Mem_Lo0
4545 * [<2G] [384M,448M] [320M,384M] [0M,64M]
4646 */
47− BONITO_PCIMAP = BONITO_PCIMAP_PCIMAP_2 |
48− BONITO_PCIMAP_WIN(2, BONITO_PCILO2_BASE) |
49− BONITO_PCIMAP_WIN(1, BONITO_PCILO1_BASE) |
50− BONITO_PCIMAP_WIN(0, 0);
47+ LOONGSON_PCIMAP = LOONGSON_PCIMAP_PCIMAP_2 |
48+ LOONGSON_PCIMAP_WIN(2, LOONGSON_PCILO2_BASE) |
49+ LOONGSON_PCIMAP_WIN(1, LOONGSON_PCILO1_BASE) |
50+ LOONGSON_PCIMAP_WIN(0, 0);
5151
5252 /*
5353 * PCI-DMA to local mapping: [2G,2G+256M] -> [0M,256M]
5454 */
55− BONITO_PCIBASE0 = 0x80000000ul; /* base: 2G -> mmap: 0M */
55+ LOONGSON_PCIBASE0 = 0x80000000ul; /* base: 2G -> mmap: 0M */
5656 /* size: 256M, burst transmission, pre-fetch enable, 64bit */
5757 LOONGSON_PCI_HIT0_SEL_L = 0xc000000cul;
5858 LOONGSON_PCI_HIT0_SEL_H = 0xfffffffful;
@@ -67,6 +67,14 @@ static void __init setup_pcimap(void) · 8 unmodified lines
6767 /* can not change gnt to break pci transfer when device's gnt not
6868 deassert for some broken device */
6969 LOONGSON_PXARB_CFG = 0x00fe0105ul;
70+
71+#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
72+ /*
73+ * set cpu addr window2 to map CPU address space to PCI address space
74+ */
75+ LOONGSON_ADDRWIN_CPUTOPCI(ADDRWIN_WIN2, LOONGSON_CPU_MEM_SRC,
76+ LOONGSON_PCI_MEM_DST, MMAP_CPUTOPCI_SIZE);
77+#endif
7078 }
7179
7280 static int __init pcibios_init(void)
arch/mips/loongson/common/platform.c+30−0
@@ -0,0 +1,30 @@
1+/*
2+ * Copyright (C) 2009 Lemote Inc.
3+ * Author: Wu Zhangjin, wuzj@lemote.com
4+ *
5+ * This program is free software; you can redistribute it and/or modify it
6+ * under the terms of the GNU General Public License as published by the
7+ * Free Software Foundation; either version 2 of the License, or (at your
8+ * option) any later version.
9+ */
10+
11+#include <linux/err.h>
12+#include <linux/platform_device.h>
13+
14+static struct platform_device loongson2_cpufreq_device = {
15+ .name = "loongson2_cpufreq",
16+ .id = -1,
17+};
18+
19+static int __init loongson2_cpufreq_init(void)
20+{
21+ struct cpuinfo_mips *c = &current_cpu_data;
22+
23+ /* Only 2F revision and it's successors support CPUFreq */
24+ if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_LOONGSON2F)
25+ return platform_device_register(&loongson2_cpufreq_device);
26+
27+ return -ENODEV;
28+}
29+
30+arch_initcall(loongson2_cpufreq_init);
arch/mips/loongson/common/pm.c+161−0
@@ -0,0 +1,161 @@
1+/*
2+ * loongson-specific suspend support
3+ *
4+ * Copyright (C) 2009 Lemote Inc.
5+ * Author: Wu Zhangjin <wuzj@lemote.com>
6+ *
7+ * This program is free software; you can redistribute it and/or modify
8+ * it under the terms of the GNU General Public License as published by
9+ * the Free Software Foundation; either version 2 of the License, or
10+ * (at your option) any later version.
11+ */
12+#include <linux/suspend.h>
13+#include <linux/interrupt.h>
14+#include <linux/pm.h>
15+
16+#include <asm/i8259.h>
17+#include <asm/mipsregs.h>
18+
19+#include <loongson.h>
20+
21+static unsigned int __maybe_unused cached_master_mask; /* i8259A */
22+static unsigned int __maybe_unused cached_slave_mask;
23+static unsigned int __maybe_unused cached_bonito_irq_mask; /* bonito */
24+
25+void arch_suspend_disable_irqs(void)
26+{
27+ /* disable all mips events */
28+ local_irq_disable();
29+
30+#ifdef CONFIG_I8259
31+ /* disable all events of i8259A */
32+ cached_slave_mask = inb(PIC_SLAVE_IMR);
33+ cached_master_mask = inb(PIC_MASTER_IMR);
34+
35+ outb(0xff, PIC_SLAVE_IMR);
36+ inb(PIC_SLAVE_IMR);
37+ outb(0xff, PIC_MASTER_IMR);
38+ inb(PIC_MASTER_IMR);
39+#endif
40+ /* disable all events of bonito */
41+ cached_bonito_irq_mask = LOONGSON_INTEN;
42+ LOONGSON_INTENCLR = 0xffff;
43+ (void)LOONGSON_INTENCLR;
44+}
45+
46+void arch_suspend_enable_irqs(void)
47+{
48+ /* enable all mips events */
49+ local_irq_enable();
50+#ifdef CONFIG_I8259
51+ /* only enable the cached events of i8259A */
52+ outb(cached_slave_mask, PIC_SLAVE_IMR);
53+ outb(cached_master_mask, PIC_MASTER_IMR);
54+#endif
55+ /* enable all cached events of bonito */
56+ LOONGSON_INTENSET = cached_bonito_irq_mask;
57+ (void)LOONGSON_INTENSET;
58+}
59+
60+/*
61+ * Setup the board-specific events for waking up loongson from wait mode
62+ */
63+void __weak setup_wakeup_events(void)
64+{
65+}
66+
67+/*
68+ * Check wakeup events
69+ */
70+int __weak wakeup_loongson(void)
71+{
72+ return 1;
73+}
74+
75+/*
76+ * If the events are really what we want to wakeup the CPU, wake it up
77+ * otherwise put the CPU asleep again.
78+ */
79+static void wait_for_wakeup_events(void)
80+{
81+ while (!wakeup_loongson())
82+ LOONGSON_CHIPCFG0 &= ~0x7;
83+}
84+
85+/*
86+ * Stop all perf counters
87+ *
88+ * $24 is the control register of Loongson perf counter
89+ */
90+static inline void stop_perf_counters(void)
91+{
92+ __write_64bit_c0_register($24, 0, 0);
93+}
94+
95+
96+static void loongson_suspend_enter(void)
97+{
98+ static unsigned int cached_cpu_freq;
99+
100+ /* setup wakeup events via enabling the IRQs */
101+ setup_wakeup_events();
102+
103+ stop_perf_counters();
104+
105+ cached_cpu_freq = LOONGSON_CHIPCFG0;
106+
107+ /* Put CPU into wait mode */
108+ LOONGSON_CHIPCFG0 &= ~0x7;
109+
110+ /* wait for the given events to wakeup cpu from wait mode */
111+ wait_for_wakeup_events();
112+
113+ LOONGSON_CHIPCFG0 = cached_cpu_freq;
114+ mmiowb();
115+}
116+
117+void __weak mach_suspend(void)
118+{
119+}
120+
121+void __weak mach_resume(void)
122+{
123+}
124+
125+static int loongson_pm_enter(suspend_state_t state)
126+{
127+ mach_suspend();
128+
129+ /* processor specific suspend */
130+ loongson_suspend_enter();
131+
132+ mach_resume();
133+
134+ return 0;
135+}
136+
137+static int loongson_pm_valid_state(suspend_state_t state)
138+{
139+ switch (state) {
140+ case PM_SUSPEND_ON:
141+ case PM_SUSPEND_STANDBY:
142+ case PM_SUSPEND_MEM:
143+ return 1;
144+
145+ default:
146+ return 0;
147+ }
148+}
149+
150+static struct platform_suspend_ops loongson_pm_ops = {
151+ .valid = loongson_pm_valid_state,
152+ .enter = loongson_pm_enter,
153+};
154+
155+static int __init loongson_pm_init(void)
156+{
157+ suspend_set_ops(&loongson_pm_ops);
158+
159+ return 0;
160+}
161+arch_initcall(loongson_pm_init);
arch/mips/loongson/common/reset.c+1−1
@@ -22,7 +22,7 @@ static void loongson_restart(char *command) · 21 unmodified lines
2222 mach_prepare_reboot();
2323
2424 /* reboot via jumping to boot base address */
25− ((void (*)(void))ioremap_nocache(BONITO_BOOT_BASE, 4)) ();
25+ ((void (*)(void))ioremap_nocache(LOONGSON_BOOT_BASE, 4)) ();
2626 }
2727
2828 static void loongson_halt(void)
arch/mips/loongson/common/serial.c+76−0
@@ -0,0 +1,76 @@
1+/*
2+ * This file is subject to the terms and conditions of the GNU General Public
3+ * License. See the file "COPYING" in the main directory of this archive
4+ * for more details.
5+ *
6+ * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
7+ *
8+ * Copyright (C) 2009 Lemote, Inc.
9+ * Author: Yan hua (yanhua@lemote.com)
10+ * Author: Wu Zhangjin (wuzj@lemote.com)
11+ */
12+
13+#include <linux/io.h>
14+#include <linux/init.h>
15+#include <linux/serial_8250.h>
16+
17+#include <asm/bootinfo.h>
18+
19+#include <loongson.h>
20+#include <machine.h>
21+
22+#define PORT(int) \
23+{ \
24+ .irq = int, \
25+ .uartclk = 1843200, \
26+ .iotype = UPIO_PORT, \
27+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, \
28+ .regshift = 0, \
29+}
30+
31+#define PORT_M(int) \
32+{ \
33+ .irq = MIPS_CPU_IRQ_BASE + (int), \
34+ .uartclk = 3686400, \
35+ .iotype = UPIO_MEM, \
36+ .membase = (void __iomem *)NULL, \
37+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, \
38+ .regshift = 0, \
39+}
40+
41+static struct plat_serial8250_port uart8250_data[][2] = {
42+ [MACH_LOONGSON_UNKNOWN] {},
43+ [MACH_LEMOTE_FL2E] {PORT(4), {} },
44+ [MACH_LEMOTE_FL2F] {PORT(3), {} },
45+ [MACH_LEMOTE_ML2F7] {PORT_M(3), {} },
46+ [MACH_LEMOTE_YL2F89] {PORT_M(3), {} },
47+ [MACH_DEXXON_GDIUM2F10] {PORT_M(3), {} },
48+ [MACH_LEMOTE_NAS] {PORT_M(3), {} },
49+ [MACH_LEMOTE_LL2F] {PORT(3), {} },
50+ [MACH_LOONGSON_END] {},
51+};
52+
53+static struct platform_device uart8250_device = {
54+ .name = "serial8250",
55+ .id = PLAT8250_DEV_PLATFORM,
56+};
57+
58+static int __init serial_init(void)
59+{
60+ unsigned char iotype;
61+
62+ iotype = uart8250_data[mips_machtype][0].iotype;
63+
64+ if (UPIO_MEM == iotype)
65+ uart8250_data[mips_machtype][0].membase =
66+ (void __iomem *)_loongson_uart_base;
67+ else if (UPIO_PORT == iotype)
68+ uart8250_data[mips_machtype][0].iobase =
69+ loongson_uart_base - LOONGSON_PCIIO_BASE;
70+
71+ uart8250_device.dev.platform_data = uart8250_data[mips_machtype];
72+
73+ return platform_device_register(&uart8250_device);
74+}
75+
76+device_initcall(serial_init);
arch/mips/loongson/common/time.c+3−0
@@ -14,11 +14,14 @@ · 13 unmodified lines
1414 #include <asm/time.h>
1515
1616 #include <loongson.h>
17+#include <cs5536/cs5536_mfgpt.h>
1718
1819 void __init plat_time_init(void)
1920 {
2021 /* setup mips r4k timer */
2122 mips_hpt_frequency = cpu_clock_freq / 2;
23+
24+ setup_mfgpt0_timer();
2225 }
2326
2427 void read_persistent_clock(struct timespec *ts)
arch/mips/loongson/common/uart_base.c+45−0
@@ -0,0 +1,45 @@
1+/*
2+ * Copyright (C) 2009 Lemote Inc.
3+ * Author: Wu Zhangjin, wuzj@lemote.com
4+ *
5+ * This program is free software; you can redistribute it and/or modify it
6+ * under the terms of the GNU General Public License as published by the
7+ * Free Software Foundation; either version 2 of the License, or (at your
8+ * option) any later version.
9+ */
10+
11+#include <linux/module.h>
12+#include <asm/bootinfo.h>
13+
14+#include <loongson.h>
15+
16+/* ioremapped */
17+unsigned long _loongson_uart_base;
18+EXPORT_SYMBOL(_loongson_uart_base);
19+/* raw */
20+unsigned long loongson_uart_base;
21+EXPORT_SYMBOL(loongson_uart_base);
22+
23+void prom_init_loongson_uart_base(void)
24+{
25+ switch (mips_machtype) {
26+ case MACH_LEMOTE_FL2E:
27+ loongson_uart_base = LOONGSON_PCIIO_BASE + 0x3f8;
28+ break;
29+ case MACH_LEMOTE_FL2F:
30+ case MACH_LEMOTE_LL2F:
31+ loongson_uart_base = LOONGSON_PCIIO_BASE + 0x2f8;
32+ break;
33+ case MACH_LEMOTE_ML2F7:
34+ case MACH_LEMOTE_YL2F89:
35+ case MACH_DEXXON_GDIUM2F10:
36+ case MACH_LEMOTE_NAS:
37+ default:
38+ /* The CPU provided serial port */
39+ loongson_uart_base = LOONGSON_LIO1_BASE + 0x3f8;
40+ break;
41+ }
42+
43+ _loongson_uart_base =
44+ (unsigned long)ioremap_nocache(loongson_uart_base, 8);
45+}
arch/mips/loongson/fuloong-2e/irq.c+2−2
@@ -47,8 +47,8 @@ static struct irqaction cascade_irqaction = { · 46 unmodified lines
4747 void __init set_irq_trigger_mode(void)
4848 {
4949 /* most bonito irq should be level triggered */
50− BONITO_INTEDGE = BONITO_ICU_SYSTEMERR | BONITO_ICU_MASTERERR |
51− BONITO_ICU_RETRYERR | BONITO_ICU_MBOXES;
50+ LOONGSON_INTEDGE = LOONGSON_ICU_SYSTEMERR | LOONGSON_ICU_MASTERERR |
51+ LOONGSON_ICU_RETRYERR | LOONGSON_ICU_MBOXES;
5252 }
5353
5454 void __init mach_init_irq(void)
arch/mips/loongson/fuloong-2e/reset.c+2−2
@@ -14,8 +14,8 @@ · 13 unmodified lines
1414
1515 void mach_prepare_reboot(void)
1616 {
17− BONITO_BONGENCFG &= ~(1 << 2);
18− BONITO_BONGENCFG |= (1 << 2);
17+ LOONGSON_GENCFG &= ~(1 << 2);
18+ LOONGSON_GENCFG |= (1 << 2);
1919 }
2020
2121 void mach_prepare_shutdown(void)
arch/mips/loongson/lemote-2f/Makefile+11−0
@@ -0,0 +1,11 @@
1+#
2+# Makefile for lemote loongson2f family machines
3+#
4+
5+obj-y += irq.o reset.o ec_kb3310b.o
6+
7+#
8+# Suspend Support
9+#
10+
11+obj-$(CONFIG_LOONGSON_SUSPEND) += pm.o
arch/mips/loongson/lemote-2f/ec_kb3310b.c+130−0
@@ -0,0 +1,130 @@
1+/*
2+ * Basic KB3310B Embedded Controller support for the YeeLoong 2F netbook
3+ *
4+ * Copyright (C) 2008 Lemote Inc.
5+ * Author: liujl <liujl@lemote.com>, 2008-04-20
6+ *
7+ * This program is free software; you can redistribute it and/or modify
8+ * it under the terms of the GNU General Public License as published by
9+ * the Free Software Foundation; either version 2 of the License, or
10+ * (at your option) any later version.
11+ */
12+
13+#include <linux/module.h>
14+#include <linux/spinlock.h>
15+#include <linux/delay.h>
16+
17+#include "ec_kb3310b.h"
18+
19+static DEFINE_SPINLOCK(index_access_lock);
20+static DEFINE_SPINLOCK(port_access_lock);
21+
22+unsigned char ec_read(unsigned short addr)
23+{
24+ unsigned char value;
25+ unsigned long flags;
26+
27+ spin_lock_irqsave(&index_access_lock, flags);
28+ outb((addr & 0xff00) >> 8, EC_IO_PORT_HIGH);
29+ outb((addr & 0x00ff), EC_IO_PORT_LOW);
30+ value = inb(EC_IO_PORT_DATA);
31+ spin_unlock_irqrestore(&index_access_lock, flags);
32+
33+ return value;
34+}
35+EXPORT_SYMBOL_GPL(ec_read);
36+
37+void ec_write(unsigned short addr, unsigned char val)
38+{
39+ unsigned long flags;
40+
41+ spin_lock_irqsave(&index_access_lock, flags);
42+ outb((addr & 0xff00) >> 8, EC_IO_PORT_HIGH);
43+ outb((addr & 0x00ff), EC_IO_PORT_LOW);
44+ outb(val, EC_IO_PORT_DATA);
45+ /* flush the write action */
46+ inb(EC_IO_PORT_DATA);
47+ spin_unlock_irqrestore(&index_access_lock, flags);
48+
49+ return;
50+}
51+EXPORT_SYMBOL_GPL(ec_write);
52+
53+/*
54+ * This function is used for EC command writes and corresponding status queries.
55+ */
56+int ec_query_seq(unsigned char cmd)
57+{
58+ int timeout;
59+ unsigned char status;
60+ unsigned long flags;
61+ int ret = 0;
62+
63+ spin_lock_irqsave(&port_access_lock, flags);
64+
65+ /* make chip goto reset mode */
66+ udelay(EC_REG_DELAY);
67+ outb(cmd, EC_CMD_PORT);
68+ udelay(EC_REG_DELAY);
69+
70+ /* check if the command is received by ec */
71+ timeout = EC_CMD_TIMEOUT;
72+ status = inb(EC_STS_PORT);
73+ while (timeout-- && (status & (1 << 1))) {
74+ status = inb(EC_STS_PORT);
75+ udelay(EC_REG_DELAY);
76+ }
77+
78+ if (timeout <= 0) {
79+ printk(KERN_ERR "%s: deadable error : timeout...\n", __func__);
80+ ret = -EINVAL;
81+ } else
82+ printk(KERN_INFO
83+ "(%x/%d)ec issued command %d status : 0x%x\n",
84+ timeout, EC_CMD_TIMEOUT - timeout, cmd, status);
85+
86+ spin_unlock_irqrestore(&port_access_lock, flags);
87+
88+ return ret;
89+}
90+EXPORT_SYMBOL_GPL(ec_query_seq);
91+
92+/*
93+ * Send query command to EC to get the proper event number
94+ */
95+int ec_query_event_num(void)
96+{
97+ return ec_query_seq(CMD_GET_EVENT_NUM);
98+}
99+EXPORT_SYMBOL(ec_query_event_num);
100+
101+/*
102+ * Get event number from EC
103+ *
104+ * NOTE: This routine must follow the query_event_num function in the
105+ * interrupt.
106+ */
107+int ec_get_event_num(void)
108+{
109+ int timeout = 100;
110+ unsigned char value;
111+ unsigned char status;
112+
113+ udelay(EC_REG_DELAY);
114+ status = inb(EC_STS_PORT);
115+ udelay(EC_REG_DELAY);
116+ while (timeout-- && !(status & (1 << 0))) {
117+ status = inb(EC_STS_PORT);
118+ udelay(EC_REG_DELAY);
119+ }
120+ if (timeout <= 0) {
121+ pr_info("%s: get event number timeout.\n", __func__);
122+
123+ return -EINVAL;
124+ }
125+ value = inb(EC_DAT_PORT);
126+ udelay(EC_REG_DELAY);
127+
128+ return value;
129+}
130+EXPORT_SYMBOL(ec_get_event_num);
arch/mips/loongson/lemote-2f/ec_kb3310b.h+188−0
@@ -0,0 +1,188 @@
1+/*
2+ * KB3310B Embedded Controller
3+ *
4+ * Copyright (C) 2008 Lemote Inc.
5+ * Author: liujl <liujl@lemote.com>, 2008-03-14
6+ *
7+ * This program is free software; you can redistribute it and/or modify
8+ * it under the terms of the GNU General Public License as published by
9+ * the Free Software Foundation; either version 2 of the License, or
10+ * (at your option) any later version.
11+ */
12+
13+#ifndef _EC_KB3310B_H
14+#define _EC_KB3310B_H
15+
16+extern unsigned char ec_read(unsigned short addr);
17+extern void ec_write(unsigned short addr, unsigned char val);
18+extern int ec_query_seq(unsigned char cmd);
19+extern int ec_query_event_num(void);
20+extern int ec_get_event_num(void);
21+
22+typedef int (*sci_handler) (int status);
23+extern sci_handler yeeloong_report_lid_status;
24+
25+#define SCI_IRQ_NUM 0x0A
26+
27+/*
28+ * The following registers are determined by the EC index configuration.
29+ * 1, fill the PORT_HIGH as EC register high part.
30+ * 2, fill the PORT_LOW as EC register low part.
31+ * 3, fill the PORT_DATA as EC register write data or get the data from it.
32+ */
33+#define EC_IO_PORT_HIGH 0x0381
34+#define EC_IO_PORT_LOW 0x0382
35+#define EC_IO_PORT_DATA 0x0383
36+
37+/*
38+ * EC delay time is 500us for register and status access
39+ */
40+#define EC_REG_DELAY 500 /* unit : us */
41+#define EC_CMD_TIMEOUT 0x1000
42+
43+/*
44+ * EC access port for SCI communication
45+ */
46+#define EC_CMD_PORT 0x66
47+#define EC_STS_PORT 0x66
48+#define EC_DAT_PORT 0x62
49+#define CMD_INIT_IDLE_MODE 0xdd
50+#define CMD_EXIT_IDLE_MODE 0xdf
51+#define CMD_INIT_RESET_MODE 0xd8
52+#define CMD_REBOOT_SYSTEM 0x8c
53+#define CMD_GET_EVENT_NUM 0x84
54+#define CMD_PROGRAM_PIECE 0xda
55+
56+/* temperature & fan registers */
57+#define REG_TEMPERATURE_VALUE 0xF458
58+#define REG_FAN_AUTO_MAN_SWITCH 0xF459
59+#define BIT_FAN_AUTO 0
60+#define BIT_FAN_MANUAL 1
61+#define REG_FAN_CONTROL 0xF4D2
62+#define BIT_FAN_CONTROL_ON (1 << 0)
63+#define BIT_FAN_CONTROL_OFF (0 << 0)
64+#define REG_FAN_STATUS 0xF4DA
65+#define BIT_FAN_STATUS_ON (1 << 0)
66+#define BIT_FAN_STATUS_OFF (0 << 0)
67+#define REG_FAN_SPEED_HIGH 0xFE22
68+#define REG_FAN_SPEED_LOW 0xFE23
69+#define REG_FAN_SPEED_LEVEL 0xF4CC
70+/* fan speed divider */
71+#define FAN_SPEED_DIVIDER 480000 /* (60*1000*1000/62.5/2)*/
72+
73+/* battery registers */
74+#define REG_BAT_DESIGN_CAP_HIGH 0xF77D
75+#define REG_BAT_DESIGN_CAP_LOW 0xF77E
76+#define REG_BAT_FULLCHG_CAP_HIGH 0xF780
77+#define REG_BAT_FULLCHG_CAP_LOW 0xF781
78+#define REG_BAT_DESIGN_VOL_HIGH 0xF782
79+#define REG_BAT_DESIGN_VOL_LOW 0xF783
80+#define REG_BAT_CURRENT_HIGH 0xF784
81+#define REG_BAT_CURRENT_LOW 0xF785
82+#define REG_BAT_VOLTAGE_HIGH 0xF786
83+#define REG_BAT_VOLTAGE_LOW 0xF787
84+#define REG_BAT_TEMPERATURE_HIGH 0xF788
85+#define REG_BAT_TEMPERATURE_LOW 0xF789
86+#define REG_BAT_RELATIVE_CAP_HIGH 0xF492
87+#define REG_BAT_RELATIVE_CAP_LOW 0xF493
88+#define REG_BAT_VENDOR 0xF4C4
89+#define FLAG_BAT_VENDOR_SANYO 0x01
90+#define FLAG_BAT_VENDOR_SIMPLO 0x02
91+#define REG_BAT_CELL_COUNT 0xF4C6
92+#define FLAG_BAT_CELL_3S1P 0x03
93+#define FLAG_BAT_CELL_3S2P 0x06
94+#define REG_BAT_CHARGE 0xF4A2
95+#define FLAG_BAT_CHARGE_DISCHARGE 0x01
96+#define FLAG_BAT_CHARGE_CHARGE 0x02
97+#define FLAG_BAT_CHARGE_ACPOWER 0x00
98+#define REG_BAT_STATUS 0xF4B0
99+#define BIT_BAT_STATUS_LOW (1 << 5)
100+#define BIT_BAT_STATUS_DESTROY (1 << 2)
101+#define BIT_BAT_STATUS_FULL (1 << 1)
102+#define BIT_BAT_STATUS_IN (1 << 0)
103+#define REG_BAT_CHARGE_STATUS 0xF4B1
104+#define BIT_BAT_CHARGE_STATUS_OVERTEMP (1 << 2)
105+#define BIT_BAT_CHARGE_STATUS_PRECHG (1 << 1)
106+#define REG_BAT_STATE 0xF482
107+#define BIT_BAT_STATE_CHARGING (1 << 1)
108+#define BIT_BAT_STATE_DISCHARGING (1 << 0)
109+#define REG_BAT_POWER 0xF440
110+#define BIT_BAT_POWER_S3 (1 << 2)
111+#define BIT_BAT_POWER_ON (1 << 1)
112+#define BIT_BAT_POWER_ACIN (1 << 0)
113+
114+/* other registers */
115+/* Audio: rd/wr */
116+#define REG_AUDIO_VOLUME 0xF46C
117+#define REG_AUDIO_MUTE 0xF4E7
118+#define REG_AUDIO_BEEP 0xF4D0
119+/* USB port power or not: rd/wr */
120+#define REG_USB0_FLAG 0xF461
121+#define REG_USB1_FLAG 0xF462
122+#define REG_USB2_FLAG 0xF463
123+#define BIT_USB_FLAG_ON 1
124+#define BIT_USB_FLAG_OFF 0
125+/* LID */
126+#define REG_LID_DETECT 0xF4BD
127+#define BIT_LID_DETECT_ON 1
128+#define BIT_LID_DETECT_OFF 0
129+/* CRT */
130+#define REG_CRT_DETECT 0xF4AD
131+#define BIT_CRT_DETECT_PLUG 1
132+#define BIT_CRT_DETECT_UNPLUG 0
133+/* LCD backlight brightness adjust: 9 levels */
134+#define REG_DISPLAY_BRIGHTNESS 0xF4F5
135+/* Black screen Status */
136+#define BIT_DISPLAY_LCD_ON 1
137+#define BIT_DISPLAY_LCD_OFF 0
138+/* LCD backlight control: off/restore */
139+#define REG_BACKLIGHT_CTRL 0xF7BD
140+#define BIT_BACKLIGHT_ON 1
141+#define BIT_BACKLIGHT_OFF 0
142+/* Reset the machine auto-clear: rd/wr */
143+#define REG_RESET 0xF4EC
144+#define BIT_RESET_ON 1
145+/* Light the led: rd/wr */
146+#define REG_LED 0xF4C8
147+#define BIT_LED_RED_POWER (1 << 0)
148+#define BIT_LED_ORANGE_POWER (1 << 1)
149+#define BIT_LED_GREEN_CHARGE (1 << 2)
150+#define BIT_LED_RED_CHARGE (1 << 3)
151+#define BIT_LED_NUMLOCK (1 << 4)
152+/* Test led mode, all led on/off */
153+#define REG_LED_TEST 0xF4C2
154+#define BIT_LED_TEST_IN 1
155+#define BIT_LED_TEST_OUT 0
156+/* Camera on/off */
157+#define REG_CAMERA_STATUS 0xF46A
158+#define BIT_CAMERA_STATUS_ON 1
159+#define BIT_CAMERA_STATUS_OFF 0
160+#define REG_CAMERA_CONTROL 0xF7B7
161+#define BIT_CAMERA_CONTROL_OFF 0
162+#define BIT_CAMERA_CONTROL_ON 1
163+/* Wlan Status */
164+#define REG_WLAN 0xF4FA
165+#define BIT_WLAN_ON 1
166+#define BIT_WLAN_OFF 0
167+#define REG_DISPLAY_LCD 0xF79F
168+
169+/* SCI Event Number from EC */
170+enum {
171+ EVENT_LID = 0x23, /* LID open/close */
172+ EVENT_DISPLAY_TOGGLE, /* Fn+F3 for display switch */
173+ EVENT_SLEEP, /* Fn+F1 for entering sleep mode */
174+ EVENT_OVERTEMP, /* Over-temperature happened */
175+ EVENT_CRT_DETECT, /* CRT is connected */
176+ EVENT_CAMERA, /* Camera on/off */
177+ EVENT_USB_OC2, /* USB2 Over Current occurred */
178+ EVENT_USB_OC0, /* USB0 Over Current occurred */
179+ EVENT_BLACK_SCREEN, /* Turn on/off backlight */
180+ EVENT_AUDIO_MUTE, /* Mute on/off */
181+ EVENT_DISPLAY_BRIGHTNESS,/* LCD backlight brightness adjust */
182+ EVENT_AC_BAT, /* AC & Battery relative issue */
183+ EVENT_AUDIO_VOLUME, /* Volume adjust */
184+ EVENT_WLAN, /* Wlan on/off */
185+ EVENT_END
186+};
187+
188+#endif /* !_EC_KB3310B_H */
arch/mips/loongson/lemote-2f/irq.c+134−0
@@ -0,0 +1,134 @@
1+/*
2+ * Copyright (C) 2007 Lemote Inc.
3+ * Author: Fuxin Zhang, zhangfx@lemote.com
4+ *
5+ * This program is free software; you can redistribute it and/or modify it
6+ * under the terms of the GNU General Public License as published by the
7+ * Free Software Foundation; either version 2 of the License, or (at your
8+ * option) any later version.
9+ */
10+
11+#include <linux/interrupt.h>
12+#include <linux/module.h>
13+
14+#include <asm/irq_cpu.h>
15+#include <asm/i8259.h>
16+#include <asm/mipsregs.h>
17+
18+#include <loongson.h>
19+#include <machine.h>
20+
21+#define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* cpu timer */
22+#define LOONGSON_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */
23+#define LOONGSON_NORTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 6) /* bonito */
24+#define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 3) /* cpu serial port */
25+#define LOONGSON_SOUTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 2) /* i8259 */
26+
27+#define LOONGSON_INT_BIT_INT0 (1 << 11)
28+#define LOONGSON_INT_BIT_INT1 (1 << 12)
29+
30+/*
31+ * The generic i8259_irq() make the kernel hang on booting. Since we cannot
32+ * get the irq via the IRR directly, we access the ISR instead.
33+ */
34+int mach_i8259_irq(void)
35+{
36+ int irq, isr;
37+
38+ irq = -1;
39+
40+ if ((LOONGSON_INTISR & LOONGSON_INTEN) & LOONGSON_INT_BIT_INT0) {
41+ spin_lock(&i8259A_lock);
42+ isr = inb(PIC_MASTER_CMD) &
43+ ~inb(PIC_MASTER_IMR) & ~(1 << PIC_CASCADE_IR);
44+ if (!isr)
45+ isr = (inb(PIC_SLAVE_CMD) & ~inb(PIC_SLAVE_IMR)) << 8;
46+ irq = ffs(isr) - 1;
47+ if (unlikely(irq == 7)) {
48+ /*
49+ * This may be a spurious interrupt.
50+ *
51+ * Read the interrupt status register (ISR). If the most
52+ * significant bit is not set then there is no valid
53+ * interrupt.
54+ */
55+ outb(0x0B, PIC_MASTER_ISR); /* ISR register */
56+ if (~inb(PIC_MASTER_ISR) & 0x80)
57+ irq = -1;
58+ }
59+ spin_unlock(&i8259A_lock);
60+ }
61+
62+ return irq;
63+}
64+EXPORT_SYMBOL(mach_i8259_irq);
65+
66+static void i8259_irqdispatch(void)
67+{
68+ int irq;
69+
70+ irq = mach_i8259_irq();
71+ if (irq >= 0)
72+ do_IRQ(irq);
73+ else
74+ spurious_interrupt();
75+}
76+
77+void mach_irq_dispatch(unsigned int pending)
78+{
79+ if (pending & CAUSEF_IP7)
80+ do_IRQ(LOONGSON_TIMER_IRQ);
81+ else if (pending & CAUSEF_IP6) { /* North Bridge, Perf counter */
82+#ifdef CONFIG_OPROFILE
83+ do_IRQ(LOONGSON2_PERFCNT_IRQ);
84+#endif
85+ bonito_irqdispatch();
86+ } else if (pending & CAUSEF_IP3) /* CPU UART */
87+ do_IRQ(LOONGSON_UART_IRQ);
88+ else if (pending & CAUSEF_IP2) /* South Bridge */
89+ i8259_irqdispatch();
90+ else
91+ spurious_interrupt();
92+}
93+
94+void __init set_irq_trigger_mode(void)
95+{
96+ /* setup cs5536 as high level trigger */
97+ LOONGSON_INTPOL = LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1;
98+ LOONGSON_INTEDGE &= ~(LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1);
99+}
100+
101+static irqreturn_t ip6_action(int cpl, void *dev_id)
102+{
103+ return IRQ_HANDLED;
104+}
105+
106+struct irqaction ip6_irqaction = {
107+ .handler = ip6_action,
108+ .name = "cascade",
109+ .flags = IRQF_SHARED,
110+};
111+
112+struct irqaction cascade_irqaction = {
113+ .handler = no_action,
114+ .name = "cascade",
115+};
116+
117+void __init mach_init_irq(void)
118+{
119+ /* init all controller
120+ * 0-15 ------> i8259 interrupt
121+ * 16-23 ------> mips cpu interrupt
122+ * 32-63 ------> bonito irq
123+ */
124+
125+ /* Sets the first-level interrupt dispatcher. */
126+ mips_cpu_irq_init();
127+ init_i8259_irqs();
128+ bonito_irq_init();
129+
130+ /* setup north bridge irq (bonito) */
131+ setup_irq(LOONGSON_NORTH_BRIDGE_IRQ, &ip6_irqaction);
132+ /* setup source bridge irq (i8259) */
133+ setup_irq(LOONGSON_SOUTH_BRIDGE_IRQ, &cascade_irqaction);
134+}
arch/mips/loongson/lemote-2f/pm.c+149−0
@@ -0,0 +1,149 @@
1+/*
2+ * Lemote loongson2f family machines' specific suspend support
3+ *
4+ * Copyright (C) 2009 Lemote Inc.
5+ * Author: Wu Zhangjin <wuzj@lemote.com>
6+ *
7+ * This program is free software; you can redistribute it and/or modify
8+ * it under the terms of the GNU General Public License as published by
9+ * the Free Software Foundation; either version 2 of the License, or
10+ * (at your option) any later version.
11+ */
12+
13+#include <linux/suspend.h>
14+#include <linux/interrupt.h>
15+#include <linux/pm.h>
16+#include <linux/i8042.h>
17+#include <linux/module.h>
18+
19+#include <asm/i8259.h>
20+#include <asm/mipsregs.h>
21+#include <asm/bootinfo.h>
22+
23+#include <loongson.h>
24+
25+#include <cs5536/cs5536_mfgpt.h>
26+#include "ec_kb3310b.h"
27+
28+#define I8042_KBD_IRQ 1
29+#define I8042_CTR_KBDINT 0x01
30+#define I8042_CTR_KBDDIS 0x10
31+
32+static unsigned char i8042_ctr;
33+
34+static int i8042_enable_kbd_port(void)
35+{
36+ if (i8042_command(&i8042_ctr, I8042_CMD_CTL_RCTR)) {
37+ pr_err("i8042.c: Can't read CTR while enabling i8042 kbd port."
38+ "\n");
39+ return -EIO;
40+ }
41+
42+ i8042_ctr &= ~I8042_CTR_KBDDIS;
43+ i8042_ctr |= I8042_CTR_KBDINT;
44+
45+ if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
46+ i8042_ctr &= ~I8042_CTR_KBDINT;
47+ i8042_ctr |= I8042_CTR_KBDDIS;
48+ pr_err("i8042.c: Failed to enable KBD port.\n");
49+
50+ return -EIO;
51+ }
52+
53+ return 0;
54+}
55+
56+void setup_wakeup_events(void)
57+{
58+ int irq_mask;
59+
60+ switch (mips_machtype) {
61+ case MACH_LEMOTE_ML2F7:
62+ case MACH_LEMOTE_YL2F89:
63+ /* open the keyboard irq in i8259A */
64+ outb((0xff & ~(1 << I8042_KBD_IRQ)), PIC_MASTER_IMR);
65+ irq_mask = inb(PIC_MASTER_IMR);
66+
67+ /* enable keyboard port */
68+ i8042_enable_kbd_port();
69+
70+ /* Wakeup CPU via SCI lid open event */
71+ outb(irq_mask & ~(1 << PIC_CASCADE_IR), PIC_MASTER_IMR);
72+ inb(PIC_MASTER_IMR);
73+ outb(0xff & ~(1 << (SCI_IRQ_NUM - 8)), PIC_SLAVE_IMR);
74+ inb(PIC_SLAVE_IMR);
75+
76+ break;
77+
78+ default:
79+ break;
80+ }
81+}
82+
83+static struct delayed_work lid_task;
84+static int initialized;
85+/* yeeloong_report_lid_status will be implemented in yeeloong_laptop.c */
86+sci_handler yeeloong_report_lid_status;
87+EXPORT_SYMBOL(yeeloong_report_lid_status);
88+static void yeeloong_lid_update_task(struct work_struct *work)
89+{
90+ if (yeeloong_report_lid_status)
91+ yeeloong_report_lid_status(BIT_LID_DETECT_ON);
92+}
93+
94+int wakeup_loongson(void)
95+{
96+ int irq;
97+
98+ /* query the interrupt number */
99+ irq = mach_i8259_irq();
100+ if (irq < 0)
101+ return 0;
102+
103+ printk(KERN_INFO "%s: irq = %d\n", __func__, irq);
104+
105+ if (irq == I8042_KBD_IRQ)
106+ return 1;
107+ else if (irq == SCI_IRQ_NUM) {
108+ int ret, sci_event;
109+ /* query the event number */
110+ ret = ec_query_seq(CMD_GET_EVENT_NUM);
111+ if (ret < 0)
112+ return 0;
113+ sci_event = ec_get_event_num();
114+ if (sci_event < 0)
115+ return 0;
116+ if (sci_event == EVENT_LID) {
117+ int lid_status;
118+ /* check the LID status */
119+ lid_status = ec_read(REG_LID_DETECT);
120+ /* wakeup cpu when people open the LID */
121+ if (lid_status == BIT_LID_DETECT_ON) {
122+ /* If we call it directly here, the WARNING
123+ * will be sent out by getnstimeofday
124+ * via "WARN_ON(timekeeping_suspended);"
125+ * because we can not schedule in suspend mode.
126+ */
127+ if (initialized == 0) {
128+ INIT_DELAYED_WORK(&lid_task,
129+ yeeloong_lid_update_task);
130+ initialized = 1;
131+ }
132+ schedule_delayed_work(&lid_task, 1);
133+ return 1;
134+ }
135+ }
136+ }
137+
138+ return 0;
139+}
140+
141+void __weak mach_suspend(void)
142+{
143+ disable_mfgpt0_counter();
144+}
145+
146+void __weak mach_resume(void)
147+{
148+ enable_mfgpt0_counter();
149+}
arch/mips/loongson/lemote-2f/reset.c+159−0
@@ -0,0 +1,159 @@
1+/* Board-specific reboot/shutdown routines
2+ *
3+ * Copyright (c) 2009 Philippe Vachon <philippe@cowpig.ca>
4+ *
5+ * Copyright (C) 2009 Lemote Inc.
6+ * Author: Wu Zhangjin, wuzj@lemote.com
7+ *
8+ * This program is free software; you can redistribute it and/or modify it
9+ * under the terms of the GNU General Public License as published by the
10+ * Free Software Foundation; either version 2 of the License, or (at your
11+ * option) any later version.
12+ */
13+
14+#include <linux/io.h>
15+#include <linux/delay.h>
16+#include <linux/types.h>
17+
18+#include <asm/bootinfo.h>
19+
20+#include <loongson.h>
21+
22+#include <cs5536/cs5536.h>
23+#include "ec_kb3310b.h"
24+
25+static void reset_cpu(void)
26+{
27+ /*
28+ * reset cpu to full speed, this is needed when enabling cpu frequency
29+ * scalling
30+ */
31+ LOONGSON_CHIPCFG0 |= 0x7;
32+}
33+
34+/* reset support for fuloong2f */
35+
36+static void fl2f_reboot(void)
37+{
38+ reset_cpu();
39+
40+ /* send a reset signal to south bridge.
41+ *
42+ * NOTE: if enable "Power Management" in kernel, rtl8169 will not reset
43+ * normally with this reset operation and it will not work in PMON, but
44+ * you can type halt command and then reboot, seems the hardware reset
45+ * logic not work normally.
46+ */
47+ {
48+ u32 hi, lo;
49+ _rdmsr(DIVIL_MSR_REG(DIVIL_SOFT_RESET), &hi, &lo);
50+ lo |= 0x00000001;
51+ _wrmsr(DIVIL_MSR_REG(DIVIL_SOFT_RESET), hi, lo);
52+ }
53+}
54+
55+static void fl2f_shutdown(void)
56+{
57+ u32 hi, lo, val;
58+ int gpio_base;
59+
60+ /* get gpio base */
61+ _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_GPIO), &hi, &lo);
62+ gpio_base = lo & 0xff00;
63+
64+ /* make cs5536 gpio13 output enable */
65+ val = inl(gpio_base + GPIOL_OUT_EN);
66+ val &= ~(1 << (16 + 13));
67+ val |= (1 << 13);
68+ outl(val, gpio_base + GPIOL_OUT_EN);
69+ mmiowb();
70+ /* make cs5536 gpio13 output low level voltage. */
71+ val = inl(gpio_base + GPIOL_OUT_VAL) & ~(1 << (13));
72+ val |= (1 << (16 + 13));
73+ outl(val, gpio_base + GPIOL_OUT_VAL);
74+ mmiowb();
75+}
76+
77+/* reset support for yeeloong2f and mengloong2f notebook */
78+
79+void ml2f_reboot(void)
80+{
81+ reset_cpu();
82+
83+ /* sending an reset signal to EC(embedded controller) */
84+ ec_write(REG_RESET, BIT_RESET_ON);
85+}
86+
87+#define yl2f89_reboot ml2f_reboot
88+
89+/* menglong(7inches) laptop has different shutdown logic from 8.9inches */
90+#define EC_SHUTDOWN_IO_PORT_HIGH 0xff2d
91+#define EC_SHUTDOWN_IO_PORT_LOW 0xff2e
92+#define EC_SHUTDOWN_IO_PORT_DATA 0xff2f
93+#define REG_SHUTDOWN_HIGH 0xFC
94+#define REG_SHUTDOWN_LOW 0x29
95+#define BIT_SHUTDOWN_ON (1 << 1)
96+
97+static void ml2f_shutdown(void)
98+{
99+ u8 val;
100+ u64 i;
101+
102+ outb(REG_SHUTDOWN_HIGH, EC_SHUTDOWN_IO_PORT_HIGH);
103+ outb(REG_SHUTDOWN_LOW, EC_SHUTDOWN_IO_PORT_LOW);
104+ mmiowb();
105+ val = inb(EC_SHUTDOWN_IO_PORT_DATA);
106+ outb(val & (~BIT_SHUTDOWN_ON), EC_SHUTDOWN_IO_PORT_DATA);
107+ mmiowb();
108+ /* need enough wait here... how many microseconds needs? */
109+ for (i = 0; i < 0x10000; i++)
110+ delay();
111+ outb(val | BIT_SHUTDOWN_ON, EC_SHUTDOWN_IO_PORT_DATA);
112+ mmiowb();
113+}
114+
115+static void yl2f89_shutdown(void)
116+{
117+ /* cpu-gpio0 output low */
118+ LOONGSON_GPIODATA &= ~0x00000001;
119+ /* cpu-gpio0 as output */
120+ LOONGSON_GPIOIE &= ~0x00000001;
121+}
122+
123+void mach_prepare_reboot(void)
124+{
125+ switch (mips_machtype) {
126+ case MACH_LEMOTE_FL2F:
127+ case MACH_LEMOTE_NAS:
128+ case MACH_LEMOTE_LL2F:
129+ fl2f_reboot();
130+ break;
131+ case MACH_LEMOTE_ML2F7:
132+ ml2f_reboot();
133+ break;
134+ case MACH_LEMOTE_YL2F89:
135+ yl2f89_reboot();
136+ break;
137+ default:
138+ break;
139+ }
140+}
141+
142+void mach_prepare_shutdown(void)
143+{
144+ switch (mips_machtype) {
145+ case MACH_LEMOTE_FL2F:
146+ case MACH_LEMOTE_NAS:
147+ case MACH_LEMOTE_LL2F:
148+ fl2f_shutdown();
149+ break;
150+ case MACH_LEMOTE_ML2F7:
151+ ml2f_shutdown();
152+ break;
153+ case MACH_LEMOTE_YL2F89:
154+ yl2f89_shutdown();
155+ break;
156+ default:
157+ break;
158+ }
159+}
arch/mips/math-emu/cp1emu.c+61−41
@@ -35,6 +35,7 @@ · 34 unmodified lines
3535 * better performance by compiling with -msoft-float!
3636 */
3737 #include <linux/sched.h>
38+#include <linux/module.h>
3839 #include <linux/debugfs.h>
3940
4041 #include <asm/inst.h>
@@ -68,7 +69,9 @@ static int fpux_emu(struct pt_regs *, · 27 unmodified lines
6869
6970 /* Further private data for which no space exists in mips_fpu_struct */
7071
71−struct mips_fpu_emulator_stats fpuemustats;
72+#ifdef CONFIG_DEBUG_FS
73+DEFINE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats);
74+#endif
7275
7376 /* Control registers */
7477
@@ -209,7 +212,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx) · 134 unmodified lines
209212 unsigned int cond;
210213
211214 if (get_user(ir, (mips_instruction __user *) xcp->cp0_epc)) {
212− fpuemustats.errors++;
215+ MIPS_FPU_EMU_INC_STATS(errors);
213216 return SIGBUS;
214217 }
215218
@@ -240,7 +243,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx) · 24 unmodified lines
240243 return SIGILL;
241244 }
242245 if (get_user(ir, (mips_instruction __user *) emulpc)) {
243− fpuemustats.errors++;
246+ MIPS_FPU_EMU_INC_STATS(errors);
244247 return SIGBUS;
245248 }
246249 /* __compute_return_epc() will have updated cp0_epc */
@@ -253,16 +256,16 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx) · 6 unmodified lines
253256 }
254257
255258 emul:
256− fpuemustats.emulated++;
259+ MIPS_FPU_EMU_INC_STATS(emulated);
257260 switch (MIPSInst_OPCODE(ir)) {
258261 case ldc1_op:{
259262 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
260263 MIPSInst_SIMM(ir));
261264 u64 val;
262265
263− fpuemustats.loads++;
266+ MIPS_FPU_EMU_INC_STATS(loads);
264267 if (get_user(val, va)) {
265− fpuemustats.errors++;
268+ MIPS_FPU_EMU_INC_STATS(errors);
266269 return SIGBUS;
267270 }
268271 DITOREG(val, MIPSInst_RT(ir));
@@ -274,10 +277,10 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx) · 5 unmodified lines
274277 MIPSInst_SIMM(ir));
275278 u64 val;
276279
277− fpuemustats.stores++;
280+ MIPS_FPU_EMU_INC_STATS(stores);
278281 DIFROMREG(val, MIPSInst_RT(ir));
279282 if (put_user(val, va)) {
280− fpuemustats.errors++;
283+ MIPS_FPU_EMU_INC_STATS(errors);
281284 return SIGBUS;
282285 }
283286 break;
@@ -288,9 +291,9 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx) · 4 unmodified lines
288291 MIPSInst_SIMM(ir));
289292 u32 val;
290293
291− fpuemustats.loads++;
294+ MIPS_FPU_EMU_INC_STATS(loads);
292295 if (get_user(val, va)) {
293− fpuemustats.errors++;
296+ MIPS_FPU_EMU_INC_STATS(errors);
294297 return SIGBUS;
295298 }
296299 SITOREG(val, MIPSInst_RT(ir));
@@ -302,10 +305,10 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx) · 5 unmodified lines
302305 MIPSInst_SIMM(ir));
303306 u32 val;
304307
305− fpuemustats.stores++;
308+ MIPS_FPU_EMU_INC_STATS(stores);
306309 SIFROMREG(val, MIPSInst_RT(ir));
307310 if (put_user(val, va)) {
308− fpuemustats.errors++;
311+ MIPS_FPU_EMU_INC_STATS(errors);
309312 return SIGBUS;
310313 }
311314 break;
@@ -429,7 +432,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx) · 117 unmodified lines
429432
430433 if (get_user(ir,
431434 (mips_instruction __user *) xcp->cp0_epc)) {
432− fpuemustats.errors++;
435+ MIPS_FPU_EMU_INC_STATS(errors);
433436 return SIGBUS;
434437 }
435438
@@ -595,7 +598,7 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, · 159 unmodified lines
595598 {
596599 unsigned rcsr = 0; /* resulting csr */
597600
598− fpuemustats.cp1xops++;
601+ MIPS_FPU_EMU_INC_STATS(cp1xops);
599602
600603 switch (MIPSInst_FMA_FFMT(ir)) {
601604 case s_fmt:{ /* 0 */
@@ -610,9 +613,9 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, · 8 unmodified lines
610613 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
611614 xcp->regs[MIPSInst_FT(ir)]);
612615
613− fpuemustats.loads++;
616+ MIPS_FPU_EMU_INC_STATS(loads);
614617 if (get_user(val, va)) {
615− fpuemustats.errors++;
618+ MIPS_FPU_EMU_INC_STATS(errors);
616619 return SIGBUS;
617620 }
618621 SITOREG(val, MIPSInst_FD(ir));
@@ -622,11 +625,11 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, · 3 unmodified lines
622625 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
623626 xcp->regs[MIPSInst_FT(ir)]);
624627
625− fpuemustats.stores++;
628+ MIPS_FPU_EMU_INC_STATS(stores);
626629
627630 SIFROMREG(val, MIPSInst_FS(ir));
628631 if (put_user(val, va)) {
629− fpuemustats.errors++;
632+ MIPS_FPU_EMU_INC_STATS(errors);
630633 return SIGBUS;
631634 }
632635 break;
@@ -687,9 +690,9 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, · 54 unmodified lines
687690 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
688691 xcp->regs[MIPSInst_FT(ir)]);
689692
690− fpuemustats.loads++;
693+ MIPS_FPU_EMU_INC_STATS(loads);
691694 if (get_user(val, va)) {
692− fpuemustats.errors++;
695+ MIPS_FPU_EMU_INC_STATS(errors);
693696 return SIGBUS;
694697 }
695698 DITOREG(val, MIPSInst_FD(ir));
@@ -699,10 +702,10 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, · 3 unmodified lines
699702 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
700703 xcp->regs[MIPSInst_FT(ir)]);
701704
702− fpuemustats.stores++;
705+ MIPS_FPU_EMU_INC_STATS(stores);
703706 DIFROMREG(val, MIPSInst_FS(ir));
704707 if (put_user(val, va)) {
705− fpuemustats.errors++;
708+ MIPS_FPU_EMU_INC_STATS(errors);
706709 return SIGBUS;
707710 }
708711 break;
@@ -769,7 +772,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, · 60 unmodified lines
769772 #endif
770773 } rv; /* resulting value */
771774
772− fpuemustats.cp1ops++;
775+ MIPS_FPU_EMU_INC_STATS(cp1ops);
773776 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
774777 case s_fmt:{ /* 0 */
775778 union {
@@ -1240,7 +1243,7 @@ int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, · 464 unmodified lines
12401243 prevepc = xcp->cp0_epc;
12411244
12421245 if (get_user(insn, (mips_instruction __user *) xcp->cp0_epc)) {
1243− fpuemustats.errors++;
1246+ MIPS_FPU_EMU_INC_STATS(errors);
12441247 return SIGBUS;
12451248 }
12461249 if (insn == 0)
@@ -1276,33 +1279,50 @@ int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, · 29 unmodified lines
12761279 }
12771280
12781281 #ifdef CONFIG_DEBUG_FS
1282+
1283+static int fpuemu_stat_get(void *data, u64 *val)
1284+{
1285+ int cpu;
1286+ unsigned long sum = 0;
1287+ for_each_online_cpu(cpu) {
1288+ struct mips_fpu_emulator_stats *ps;
1289+ local_t *pv;
1290+ ps = &per_cpu(fpuemustats, cpu);
1291+ pv = (void *)ps + (unsigned long)data;
1292+ sum += local_read(pv);
1293+ }
1294+ *val = sum;
1295+ return 0;
1296+}
1297+DEFINE_SIMPLE_ATTRIBUTE(fops_fpuemu_stat, fpuemu_stat_get, NULL, "%llu\n");
1298+
12791299 extern struct dentry *mips_debugfs_dir;
12801300 static int __init debugfs_fpuemu(void)
12811301 {
12821302 struct dentry *d, *dir;
1283− int i;
1284− static struct {
1285− const char *name;
1286− unsigned int *v;
1287− } vars[] __initdata = {
1288− { "emulated", &fpuemustats.emulated },
1289− { "loads", &fpuemustats.loads },
1290− { "stores", &fpuemustats.stores },
1291− { "cp1ops", &fpuemustats.cp1ops },
1292− { "cp1xops", &fpuemustats.cp1xops },
1293− { "errors", &fpuemustats.errors },
1294− };
12951303
12961304 if (!mips_debugfs_dir)
12971305 return -ENODEV;
12981306 dir = debugfs_create_dir("fpuemustats", mips_debugfs_dir);
12991307 if (!dir)
13001308 return -ENOMEM;
1301− for (i = 0; i < ARRAY_SIZE(vars); i++) {
1302− d = debugfs_create_u32(vars[i].name, S_IRUGO, dir, vars[i].v);
1303− if (!d)
1304− return -ENOMEM;
1305− }
1309+
1310+#define FPU_STAT_CREATE(M) \
1311+ do { \
1312+ d = debugfs_create_file(#M , S_IRUGO, dir, \
1313+ (void *)offsetof(struct mips_fpu_emulator_stats, M), \
1314+ &fops_fpuemu_stat); \
1315+ if (!d) \
1316+ return -ENOMEM; \
1317+ } while (0)
1318+
1319+ FPU_STAT_CREATE(emulated);
1320+ FPU_STAT_CREATE(loads);
1321+ FPU_STAT_CREATE(stores);
1322+ FPU_STAT_CREATE(cp1ops);
1323+ FPU_STAT_CREATE(cp1xops);
1324+ FPU_STAT_CREATE(errors);
1325+
13061326 return 0;
13071327 }
13081328 __initcall(debugfs_fpuemu);
arch/mips/math-emu/dsemul.c+2−2
@@ -98,7 +98,7 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc) · 97 unmodified lines
9898 err |= __put_user(cpc, &fr->epc);
9999
100100 if (unlikely(err)) {
101− fpuemustats.errors++;
101+ MIPS_FPU_EMU_INC_STATS(errors);
102102 return SIGBUS;
103103 }
104104
@@ -136,7 +136,7 @@ int do_dsemulret(struct pt_regs *xcp) · 31 unmodified lines
136136 err |= __get_user(cookie, &fr->cookie);
137137
138138 if (unlikely(err || (insn != BREAK_MATH) || (cookie != BD_COOKIE))) {
139− fpuemustats.errors++;
139+ MIPS_FPU_EMU_INC_STATS(errors);
140140 return 0;
141141 }
142142
arch/mips/mipssim/Makefile+1−2
@@ -17,8 +17,7 @@ · 16 unmodified lines
1717 # 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1818 #
1919
20−obj-y := sim_platform.o sim_setup.o sim_mem.o sim_time.o sim_int.o \
21− sim_cmdline.o
20+obj-y := sim_platform.o sim_setup.o sim_mem.o sim_time.o sim_int.o
2221
2322 obj-$(CONFIG_EARLY_PRINTK) += sim_console.o
2423 obj-$(CONFIG_MIPS_MT_SMTC) += sim_smtc.o
arch/mips/mipssim/sim_setup.c+0−1
@@ -61,7 +61,6 @@ void __init prom_init(void) · 60 unmodified lines
6161 set_io_port_base(0xbfd00000);
6262
6363 pr_info("\nLINUX started...\n");
64− prom_init_cmdline();
6564 prom_meminit();
6665
6766 #ifdef CONFIG_MIPS_MT_SMP
arch/mips/mm/cerr-sb1.c+2−5
@@ -567,13 +567,10 @@ static uint32_t extract_dc(unsigned short addr, int data) · 566 unmodified lines
567567 datalo = ((unsigned long long)datalohi << 32) | datalolo;
568568 ecc = dc_ecc(datalo);
569569 if (ecc != datahi) {
570− int bits = 0;
570+ int bits;
571571 bad_ecc |= 1 << (3-offset);
572572 ecc ^= datahi;
573− while (ecc) {
574− if (ecc & 1) bits++;
575− ecc >>= 1;
576− }
573+ bits = hweight8(ecc);
577574 res |= (bits == 1) ? CP0_CERRD_DATA_SBE : CP0_CERRD_DATA_DBE;
578575 }
579576 printk(" %02X-%016llX", datahi, datalo);
arch/mips/mm/init.c+2−0
@@ -462,7 +462,9 @@ void __init_refok free_initmem(void) · 461 unmodified lines
462462 __pa_symbol(&__init_end));
463463 }
464464
465+#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
465466 unsigned long pgd_current[NR_CPUS];
467+#endif
466468 /*
467469 * On 64-bit we've got three-level pagetables with a slightly
468470 * different layout ...
arch/mips/mm/tlbex.c+25−3
@@ -160,6 +160,12 @@ static u32 tlb_handler[128] __cpuinitdata; · 159 unmodified lines
160160 static struct uasm_label labels[128] __cpuinitdata;
161161 static struct uasm_reloc relocs[128] __cpuinitdata;
162162
163+#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
164+/*
165+ * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current,
166+ * we cannot do r3000 under these circumstances.
167+ */
168+
163169 /*
164170 * The R3000 TLB handler is simple.
165171 */
@@ -199,6 +205,7 @@ static void __cpuinit build_r3000_tlb_refill_handler(void) · 33 unmodified lines
199205
200206 dump_handler((u32 *)ebase, 32);
201207 }
208+#endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
202209
203210 /*
204211 * The R4000 TLB handler is much more complicated. We have two
@@ -497,8 +504,9 @@ static void __cpuinit · 292 unmodified lines
497504 build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
498505 unsigned int tmp, unsigned int ptr)
499506 {
507+#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
500508 long pgdc = (long)pgd_current;
501−
509+#endif
502510 /*
503511 * The vmalloc handling is not in the hotpath.
504512 */
@@ -506,7 +514,15 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, · 1 unmodified line
506514 uasm_il_bltz(p, r, tmp, label_vmalloc);
507515 /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */
508516
509−#ifdef CONFIG_SMP
517+#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
518+ /*
519+ * &pgd << 11 stored in CONTEXT [23..63].
520+ */
521+ UASM_i_MFC0(p, ptr, C0_CONTEXT);
522+ uasm_i_dins(p, ptr, 0, 0, 23); /* Clear lower 23 bits of context. */
523+ uasm_i_ori(p, ptr, ptr, 0x540); /* 1 0 1 0 1 << 6 xkphys cached */
524+ uasm_i_drotr(p, ptr, ptr, 11);
525+#elif defined(CONFIG_SMP)
510526 # ifdef CONFIG_MIPS_MT_SMTC
511527 /*
512528 * SMTC uses TCBind value as "CPU" index
@@ -520,7 +536,7 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, · 7 unmodified lines
520536 */
521537 uasm_i_dmfc0(p, ptr, C0_CONTEXT);
522538 uasm_i_dsrl(p, ptr, ptr, 23);
523−#endif
539+# endif
524540 UASM_i_LA_mostly(p, tmp, pgdc);
525541 uasm_i_daddu(p, ptr, ptr, tmp);
526542 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
@@ -1033,6 +1049,7 @@ build_pte_modifiable(u32 **p, struct uasm_reloc **r, · 506 unmodified lines
10331049 iPTE_LW(p, pte, ptr);
10341050 }
10351051
1052+#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
10361053 /*
10371054 * R3000 style TLB load/store/modify handlers.
10381055 */
@@ -1184,6 +1201,7 @@ static void __cpuinit build_r3000_tlb_modify_handler(void) · 145 unmodified lines
11841201
11851202 dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm));
11861203 }
1204+#endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
11871205
11881206 /*
11891207 * R4000 style TLB load/store/modify handlers.
@@ -1400,6 +1418,7 @@ void __cpuinit build_tlb_refill_handler(void) · 210 unmodified lines
14001418 case CPU_TX3912:
14011419 case CPU_TX3922:
14021420 case CPU_TX3927:
1421+#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
14031422 build_r3000_tlb_refill_handler();
14041423 if (!run_once) {
14051424 build_r3000_tlb_load_handler();
@@ -1407,6 +1426,9 @@ void __cpuinit build_tlb_refill_handler(void) · 1 unmodified line
14071426 build_r3000_tlb_modify_handler();
14081427 run_once++;
14091428 }
1429+#else
1430+ panic("No R3000 TLB refill handler");
1431+#endif
14101432 break;
14111433
14121434 case CPU_R6000:
arch/mips/mm/uasm.c+13−3
@@ -60,11 +60,11 @@ enum opcode { · 59 unmodified lines
6060 insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
6161 insn_bne, insn_cache, insn_daddu, insn_daddiu, insn_dmfc0,
6262 insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl,
63− insn_dsrl32, insn_dsubu, insn_eret, insn_j, insn_jal, insn_jr,
64− insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0,
63+ insn_dsrl32, insn_drotr, insn_dsubu, insn_eret, insn_j, insn_jal,
64+ insn_jr, insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0,
6565 insn_mtc0, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd,
6666 insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw,
67− insn_tlbp, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori
67+ insn_tlbp, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori, insn_dins
6868 };
6969
7070 struct insn {
@@ -104,6 +104,7 @@ static struct insn insn_table[] __cpuinitdata = { · 33 unmodified lines
104104 { insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE },
105105 { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE },
106106 { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE },
107+ { insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE },
107108 { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD },
108109 { insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 },
109110 { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM },
@@ -132,6 +133,7 @@ static struct insn insn_table[] __cpuinitdata = { · 22 unmodified lines
132133 { insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 },
133134 { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD },
134135 { insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
136+ { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE },
135137 { insn_invalid, 0, 0 }
136138 };
137139
@@ -304,6 +306,12 @@ Ip_u2u1s3(op) \ · 166 unmodified lines
304306 build_insn(buf, insn##op, b, a, c); \
305307 }
306308
309+#define I_u2u1msbu3(op) \
310+Ip_u2u1msbu3(op) \
311+{ \
312+ build_insn(buf, insn##op, b, a, c+d-1, c); \
313+}
314+
307315 #define I_u1u2(op) \
308316 Ip_u1u2(op) \
309317 { \
@@ -349,6 +357,7 @@ I_u2u1u3(_dsll32) · 39 unmodified lines
349357 I_u2u1u3(_dsra)
350358 I_u2u1u3(_dsrl)
351359 I_u2u1u3(_dsrl32)
360+I_u2u1u3(_drotr)
352361 I_u3u1u2(_dsubu)
353362 I_0(_eret)
354363 I_u1(_j)
@@ -377,6 +386,7 @@ I_0(_tlbwi) · 22 unmodified lines
377386 I_0(_tlbwr)
378387 I_u3u1u2(_xor)
379388 I_u2u1u3(_xori)
389+I_u2u1msbu3(_dins);
380390
381391 /* Handle labels. */
382392 void __cpuinit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid)
arch/mips/mm/uasm.h+7−0
@@ -34,6 +34,11 @@ uasm_i##op(u32 **buf, unsigned int a, signed int b, unsigned int c) · 33 unmodified lines
3434 void __cpuinit \
3535 uasm_i##op(u32 **buf, unsigned int a, unsigned int b, signed int c)
3636
37+#define Ip_u2u1msbu3(op) \
38+void __cpuinit \
39+uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c, \
40+ unsigned int d)
41+
3742 #define Ip_u1u2(op) \
3843 void __cpuinit uasm_i##op(u32 **buf, unsigned int a, unsigned int b)
3944
@@ -65,6 +70,7 @@ Ip_u2u1u3(_dsll32); · 25 unmodified lines
6570 Ip_u2u1u3(_dsra);
6671 Ip_u2u1u3(_dsrl);
6772 Ip_u2u1u3(_dsrl32);
73+Ip_u2u1u3(_drotr);
6874 Ip_u3u1u2(_dsubu);
6975 Ip_0(_eret);
7076 Ip_u1(_j);
@@ -93,6 +99,7 @@ Ip_0(_tlbwi); · 22 unmodified lines
9399 Ip_0(_tlbwr);
94100 Ip_u3u1u2(_xor);
95101 Ip_u2u1u3(_xori);
102+Ip_u2u1msbu3(_dins);
96103
97104 /* Handle labels. */
98105 struct uasm_label {
arch/mips/mti-malta/malta-memory.c+1−1
@@ -55,7 +55,7 @@ static struct prom_pmemblock * __init prom_getmdesc(void) · 54 unmodified lines
5555 char *memsize_str;
5656 unsigned int memsize;
5757 char *ptr;
58− static char cmdline[CL_SIZE] __initdata;
58+ static char cmdline[COMMAND_LINE_SIZE] __initdata;
5959
6060 /* otherwise look in the environment */
6161 memsize_str = prom_getenv("memsize");
arch/mips/nxp/pnx833x/common/interrupts.c+2−2
@@ -295,7 +295,7 @@ static int pnx833x_set_type_gpio_irq(unsigned int irq, unsigned int flow_type) · 294 unmodified lines
295295 }
296296
297297 static struct irq_chip pnx833x_pic_irq_type = {
298− .typename = "PNX-PIC",
298+ .name = "PNX-PIC",
299299 .startup = pnx833x_startup_pic_irq,
300300 .shutdown = pnx833x_shutdown_pic_irq,
301301 .enable = pnx833x_enable_pic_irq,
@@ -305,7 +305,7 @@ static struct irq_chip pnx833x_pic_irq_type = { · 3 unmodified lines
305305 };
306306
307307 static struct irq_chip pnx833x_gpio_irq_type = {
308− .typename = "PNX-GPIO",
308+ .name = "PNX-GPIO",
309309 .startup = pnx833x_startup_gpio_irq,
310310 .shutdown = pnx833x_disable_gpio_irq,
311311 .enable = pnx833x_enable_gpio_irq,
arch/mips/oprofile/op_model_loongson2.c+4−1
@@ -1,7 +1,7 @@
11 /*
22 * Loongson2 performance counter driver for oprofile
33 *
4− * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology
4+ * Copyright (C) 2009 Lemote Inc.
55 * Author: Yanhua <yanh@lemote.com>
66 * Author: Wu Zhangjin <wuzj@lemote.com>
77 *
@@ -125,6 +125,9 @@ static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id) · 117 unmodified lines
125125 */
126126
127127 /* Check whether the irq belongs to me */
128+ enabled = read_c0_perfcnt() & LOONGSON2_PERFCNT_INT_EN;
129+ if (!enabled)
130+ return IRQ_NONE;
128131 enabled = reg.cnt1_enabled | reg.cnt2_enabled;
129132 if (!enabled)
130133 return IRQ_NONE;
arch/mips/pci/Makefile+2−2
@@ -22,13 +22,13 @@ obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \ · 21 unmodified lines
2222 #
2323 # These are still pretty much in the old state, watch, go blind.
2424 #
25−obj-$(CONFIG_BASLER_EXCITE) += ops-titan.o pci-excite.o fixup-excite.o
2625 obj-$(CONFIG_LASAT) += pci-lasat.o
2726 obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o
2827 obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o
2928 obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o
3029 obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o
31−obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-bonito64.o
30+obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-loongson2.o
31+obj-$(CONFIG_LEMOTE_MACH2F) += fixup-lemote2f.o ops-loongson2.o
3232 obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o
3333 obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o
3434 obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o
arch/mips/pci/fixup-excite.c+0−36
@@ -1,36 +0,0 @@
1−/*
2− * Copyright (C) 2004 by Basler Vision Technologies AG
3− * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
4− *
5− * This program is free software; you can redistribute it and/or modify
6− * it under the terms of the GNU General Public License as published by
7− * the Free Software Foundation; either version 2 of the License, or
8− * (at your option) any later version.
9− *
10− * This program is distributed in the hope that it will be useful,
11− * but WITHOUT ANY WARRANTY; without even the implied warranty of
12− * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13− * GNU General Public License for more details.
14− *
15− * You should have received a copy of the GNU General Public License
16− * along with this program; if not, write to the Free Software
17− * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18− */
19−#include <linux/kernel.h>
20−#include <linux/init.h>
21−#include <linux/pci.h>
22−#include <excite.h>
23−
24−int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
25−{
26− if (pin == 0)
27− return -1;
28−
29− return USB_IRQ; /* USB controller is the only PCI device */
30−}
31−
32−/* Do platform specific device initialization at pci_enable_device() time */
33−int pcibios_plat_dev_init(struct pci_dev *dev)
34−{
35− return 0;
36−}
arch/mips/pci/fixup-fuloong2e.c+3−2
@@ -13,7 +13,8 @@ · 12 unmodified lines
1313 */
1414 #include <linux/init.h>
1515 #include <linux/pci.h>
16−#include <asm/mips-boards/bonito64.h>
16+
17+#include <loongson.h>
1718
1819 /* South bridge slot number is set by the pci probe process */
1920 static u8 sb_slot = 5;
@@ -35,7 +36,7 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) · 15 unmodified lines
3536 break;
3637 }
3738 } else {
38− irq = BONITO_IRQ_BASE + 25 + pin;
39+ irq = LOONGSON_IRQ_BASE + 25 + pin;
3940 }
4041 return irq;
4142
arch/mips/pci/fixup-lemote2f.c+160−0
@@ -0,0 +1,160 @@
1+/*
2+ * Copyright (C) 2008 Lemote Technology
3+ * Copyright (C) 2004 ICT CAS
4+ * Author: Li xiaoyu, lixy@ict.ac.cn
5+ *
6+ * Copyright (C) 2007 Lemote, Inc.
7+ * Author: Fuxin Zhang, zhangfx@lemote.com
8+ *
9+ * This program is free software; you can redistribute it and/or modify it
10+ * under the terms of the GNU General Public License as published by the
11+ * Free Software Foundation; either version 2 of the License, or (at your
12+ * option) any later version.
13+ */
14+#include <linux/init.h>
15+#include <linux/pci.h>
16+
17+#include <loongson.h>
18+#include <cs5536/cs5536.h>
19+#include <cs5536/cs5536_pci.h>
20+
21+/* PCI interrupt pins
22+ *
23+ * These should not be changed, or you should consider loongson2f interrupt
24+ * register and your pci card dispatch
25+ */
26+
27+#define PCIA 4
28+#define PCIB 5
29+#define PCIC 6
30+#define PCID 7
31+
32+/* all the pci device has the PCIA pin, check the datasheet. */
33+static char irq_tab[][5] __initdata = {
34+ /* INTA INTB INTC INTD */
35+ {0, 0, 0, 0, 0}, /* 11: Unused */
36+ {0, 0, 0, 0, 0}, /* 12: Unused */
37+ {0, 0, 0, 0, 0}, /* 13: Unused */
38+ {0, 0, 0, 0, 0}, /* 14: Unused */
39+ {0, 0, 0, 0, 0}, /* 15: Unused */
40+ {0, 0, 0, 0, 0}, /* 16: Unused */
41+ {0, PCIA, 0, 0, 0}, /* 17: RTL8110-0 */
42+ {0, PCIB, 0, 0, 0}, /* 18: RTL8110-1 */
43+ {0, PCIC, 0, 0, 0}, /* 19: SiI3114 */
44+ {0, PCID, 0, 0, 0}, /* 20: 3-ports nec usb */
45+ {0, PCIA, PCIB, PCIC, PCID}, /* 21: PCI-SLOT */
46+ {0, 0, 0, 0, 0}, /* 22: Unused */
47+ {0, 0, 0, 0, 0}, /* 23: Unused */
48+ {0, 0, 0, 0, 0}, /* 24: Unused */
49+ {0, 0, 0, 0, 0}, /* 25: Unused */
50+ {0, 0, 0, 0, 0}, /* 26: Unused */
51+ {0, 0, 0, 0, 0}, /* 27: Unused */
52+};
53+
54+int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
55+{
56+ int virq;
57+
58+ if ((PCI_SLOT(dev->devfn) != PCI_IDSEL_CS5536)
59+ && (PCI_SLOT(dev->devfn) < 32)) {
60+ virq = irq_tab[slot][pin];
61+ printk(KERN_INFO "slot: %d, pin: %d, irq: %d\n", slot, pin,
62+ virq + LOONGSON_IRQ_BASE);
63+ if (virq != 0)
64+ return LOONGSON_IRQ_BASE + virq;
65+ else
66+ return 0;
67+ } else if (PCI_SLOT(dev->devfn) == PCI_IDSEL_CS5536) { /* cs5536 */
68+ switch (PCI_FUNC(dev->devfn)) {
69+ case 2:
70+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
71+ CS5536_IDE_INTR);
72+ return CS5536_IDE_INTR; /* for IDE */
73+ case 3:
74+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
75+ CS5536_ACC_INTR);
76+ return CS5536_ACC_INTR; /* for AUDIO */
77+ case 4: /* for OHCI */
78+ case 5: /* for EHCI */
79+ case 6: /* for UDC */
80+ case 7: /* for OTG */
81+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
82+ CS5536_USB_INTR);
83+ return CS5536_USB_INTR;
84+ }
85+ return dev->irq;
86+ } else {
87+ printk(KERN_INFO " strange pci slot number.\n");
88+ return 0;
89+ }
90+}
91+
92+/* Do platform specific device initialization at pci_enable_device() time */
93+int pcibios_plat_dev_init(struct pci_dev *dev)
94+{
95+ return 0;
96+}
97+
98+/* CS5536 SPEC. fixup */
99+static void __init loongson_cs5536_isa_fixup(struct pci_dev *pdev)
100+{
101+ /* the uart1 and uart2 interrupt in PIC is enabled as default */
102+ pci_write_config_dword(pdev, PCI_UART1_INT_REG, 1);
103+ pci_write_config_dword(pdev, PCI_UART2_INT_REG, 1);
104+}
105+
106+static void __init loongson_cs5536_ide_fixup(struct pci_dev *pdev)
107+{
108+ /* setting the mutex pin as IDE function */
109+ pci_write_config_dword(pdev, PCI_IDE_CFG_REG,
110+ CS5536_IDE_FLASH_SIGNATURE);
111+}
112+
113+static void __init loongson_cs5536_acc_fixup(struct pci_dev *pdev)
114+{
115+ /* enable the AUDIO interrupt in PIC */
116+ pci_write_config_dword(pdev, PCI_ACC_INT_REG, 1);
117+
118+ pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xc0);
119+}
120+
121+static void __init loongson_cs5536_ohci_fixup(struct pci_dev *pdev)
122+{
123+ /* enable the OHCI interrupt in PIC */
124+ /* THE OHCI, EHCI, UDC, OTG are shared with interrupt in PIC */
125+ pci_write_config_dword(pdev, PCI_OHCI_INT_REG, 1);
126+}
127+
128+static void __init loongson_cs5536_ehci_fixup(struct pci_dev *pdev)
129+{
130+ u32 hi, lo;
131+
132+ /* Serial short detect enable */
133+ _rdmsr(USB_MSR_REG(USB_CONFIG), &hi, &lo);
134+ _wrmsr(USB_MSR_REG(USB_CONFIG), (1 << 1) | (1 << 2) | (1 << 3), lo);
135+
136+ /* setting the USB2.0 micro frame length */
137+ pci_write_config_dword(pdev, PCI_EHCI_FLADJ_REG, 0x2000);
138+}
139+
140+static void __init loongson_nec_fixup(struct pci_dev *pdev)
141+{
142+ unsigned int val;
143+
144+ pci_read_config_dword(pdev, 0xe0, &val);
145+ /* Only 2 port be used */
146+ pci_write_config_dword(pdev, 0xe0, (val & ~3) | 0x2);
147+}
148+
149+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA,
150+ loongson_cs5536_isa_fixup);
151+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_OHC,
152+ loongson_cs5536_ohci_fixup);
153+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_EHC,
154+ loongson_cs5536_ehci_fixup);
155+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_AUDIO,
156+ loongson_cs5536_acc_fixup);
157+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_IDE,
158+ loongson_cs5536_ide_fixup);
159+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB,
160+ loongson_nec_fixup);
arch/mips/pci/ops-bonito64.c+0−7
@@ -29,13 +29,8 @@ · 28 unmodified lines
2929 #define PCI_ACCESS_READ 0
3030 #define PCI_ACCESS_WRITE 1
3131
32−#ifdef CONFIG_LEMOTE_FULOONG2E
33−#define CFG_SPACE_REG(offset) (void *)CKSEG1ADDR(BONITO_PCICFG_BASE | (offset))
34−#define ID_SEL_BEGIN 11
35−#else
3632 #define CFG_SPACE_REG(offset) (void *)CKSEG1ADDR(_pcictrl_bonito_pcicfg + (offset))
3733 #define ID_SEL_BEGIN 10
38−#endif
3934 #define MAX_DEV_NUM (31 - ID_SEL_BEGIN)
4035
4136
@@ -77,10 +72,8 @@ static int bonito64_pcibios_config_access(unsigned char access_type, · 35 unmodified lines
7772 addrp = CFG_SPACE_REG(addr & 0xffff);
7873 if (access_type == PCI_ACCESS_WRITE) {
7974 writel(cpu_to_le32(*data), addrp);
80−#ifndef CONFIG_LEMOTE_FULOONG2E
8175 /* Wait till done */
8276 while (BONITO_PCIMSTAT & 0xF);
83−#endif
8477 } else {
8578 *data = le32_to_cpu(readl(addrp));
8679 }
arch/mips/pci/ops-loongson2.c+208−0
@@ -0,0 +1,208 @@
1+/*
2+ * fuloong2e specific PCI support.
3+ *
4+ * Copyright (C) 1999, 2000, 2004 MIPS Technologies, Inc.
5+ * All rights reserved.
6+ * Authors: Carsten Langgaard <carstenl@mips.com>
7+ * Maciej W. Rozycki <macro@mips.com>
8+ *
9+ * Copyright (C) 2009 Lemote Inc.
10+ * Author: Wu Zhangjin <wuzj@lemote.com>
11+ *
12+ * This program is free software; you can distribute it and/or modify it
13+ * under the terms of the GNU General Public License (Version 2) as
14+ * published by the Free Software Foundation.
15+ */
16+#include <linux/types.h>
17+#include <linux/pci.h>
18+#include <linux/kernel.h>
19+#include <linux/init.h>
20+
21+#include <loongson.h>
22+
23+#ifdef CONFIG_CS5536
24+#include <cs5536/cs5536_pci.h>
25+#include <cs5536/cs5536.h>
26+#endif
27+
28+#define PCI_ACCESS_READ 0
29+#define PCI_ACCESS_WRITE 1
30+
31+#define CFG_SPACE_REG(offset) \
32+ (void *)CKSEG1ADDR(LOONGSON_PCICFG_BASE | (offset))
33+#define ID_SEL_BEGIN 11
34+#define MAX_DEV_NUM (31 - ID_SEL_BEGIN)
35+
36+
37+static int loongson_pcibios_config_access(unsigned char access_type,
38+ struct pci_bus *bus,
39+ unsigned int devfn, int where,
40+ u32 *data)
41+{
42+ u32 busnum = bus->number;
43+ u32 addr, type;
44+ u32 dummy;
45+ void *addrp;
46+ int device = PCI_SLOT(devfn);
47+ int function = PCI_FUNC(devfn);
48+ int reg = where & ~3;
49+
50+ if (busnum == 0) {
51+ /* board-specific part,currently,only fuloong2f,yeeloong2f
52+ * use CS5536, fuloong2e use via686b, gdium has no
53+ * south bridge
54+ */
55+#ifdef CONFIG_CS5536
56+ /* cs5536_pci_conf_read4/write4() will call _rdmsr/_wrmsr() to
57+ * access the regsters PCI_MSR_ADDR, PCI_MSR_DATA_LO,
58+ * PCI_MSR_DATA_HI, which is bigger than PCI_MSR_CTRL, so, it
59+ * will not go this branch, but the others. so, no calling dead
60+ * loop here.
61+ */
62+ if ((PCI_IDSEL_CS5536 == device) && (reg < PCI_MSR_CTRL)) {
63+ switch (access_type) {
64+ case PCI_ACCESS_READ:
65+ *data = cs5536_pci_conf_read4(function, reg);
66+ break;
67+ case PCI_ACCESS_WRITE:
68+ cs5536_pci_conf_write4(function, reg, *data);
69+ break;
70+ }
71+ return 0;
72+ }
73+#endif
74+ /* Type 0 configuration for onboard PCI bus */
75+ if (device > MAX_DEV_NUM)
76+ return -1;
77+
78+ addr = (1 << (device + ID_SEL_BEGIN)) | (function << 8) | reg;
79+ type = 0;
80+ } else {
81+ /* Type 1 configuration for offboard PCI bus */
82+ addr = (busnum << 16) | (device << 11) | (function << 8) | reg;
83+ type = 0x10000;
84+ }
85+
86+ /* Clear aborts */
87+ LOONGSON_PCICMD |= LOONGSON_PCICMD_MABORT_CLR | \
88+ LOONGSON_PCICMD_MTABORT_CLR;
89+
90+ LOONGSON_PCIMAP_CFG = (addr >> 16) | type;
91+
92+ /* Flush Bonito register block */
93+ dummy = LOONGSON_PCIMAP_CFG;
94+ mmiowb();
95+
96+ addrp = CFG_SPACE_REG(addr & 0xffff);
97+ if (access_type == PCI_ACCESS_WRITE)
98+ writel(cpu_to_le32(*data), addrp);
99+ else
100+ *data = le32_to_cpu(readl(addrp));
101+
102+ /* Detect Master/Target abort */
103+ if (LOONGSON_PCICMD & (LOONGSON_PCICMD_MABORT_CLR |
104+ LOONGSON_PCICMD_MTABORT_CLR)) {
105+ /* Error occurred */
106+
107+ /* Clear bits */
108+ LOONGSON_PCICMD |= (LOONGSON_PCICMD_MABORT_CLR |
109+ LOONGSON_PCICMD_MTABORT_CLR);
110+
111+ return -1;
112+ }
113+
114+ return 0;
115+
116+}
117+
118+
119+/*
120+ * We can't address 8 and 16 bit words directly. Instead we have to
121+ * read/write a 32bit word and mask/modify the data we actually want.
122+ */
123+static int loongson_pcibios_read(struct pci_bus *bus, unsigned int devfn,
124+ int where, int size, u32 *val)
125+{
126+ u32 data = 0;
127+
128+ if ((size == 2) && (where & 1))
129+ return PCIBIOS_BAD_REGISTER_NUMBER;
130+ else if ((size == 4) && (where & 3))
131+ return PCIBIOS_BAD_REGISTER_NUMBER;
132+
133+ if (loongson_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where,
134+ &data))
135+ return -1;
136+
137+ if (size == 1)
138+ *val = (data >> ((where & 3) << 3)) & 0xff;
139+ else if (size == 2)
140+ *val = (data >> ((where & 3) << 3)) & 0xffff;
141+ else
142+ *val = data;
143+
144+ return PCIBIOS_SUCCESSFUL;
145+}
146+
147+static int loongson_pcibios_write(struct pci_bus *bus, unsigned int devfn,
148+ int where, int size, u32 val)
149+{
150+ u32 data = 0;
151+
152+ if ((size == 2) && (where & 1))
153+ return PCIBIOS_BAD_REGISTER_NUMBER;
154+ else if ((size == 4) && (where & 3))
155+ return PCIBIOS_BAD_REGISTER_NUMBER;
156+
157+ if (size == 4)
158+ data = val;
159+ else {
160+ if (loongson_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
161+ where, &data))
162+ return -1;
163+
164+ if (size == 1)
165+ data = (data & ~(0xff << ((where & 3) << 3))) |
166+ (val << ((where & 3) << 3));
167+ else if (size == 2)
168+ data = (data & ~(0xffff << ((where & 3) << 3))) |
169+ (val << ((where & 3) << 3));
170+ }
171+
172+ if (loongson_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn, where,
173+ &data))
174+ return -1;
175+
176+ return PCIBIOS_SUCCESSFUL;
177+}
178+
179+struct pci_ops loongson_pci_ops = {
180+ .read = loongson_pcibios_read,
181+ .write = loongson_pcibios_write
182+};
183+
184+#ifdef CONFIG_CS5536
185+void _rdmsr(u32 msr, u32 *hi, u32 *lo)
186+{
187+ struct pci_bus bus = {
188+ .number = PCI_BUS_CS5536
189+ };
190+ u32 devfn = PCI_DEVFN(PCI_IDSEL_CS5536, 0);
191+ loongson_pcibios_write(&bus, devfn, PCI_MSR_ADDR, 4, msr);
192+ loongson_pcibios_read(&bus, devfn, PCI_MSR_DATA_LO, 4, lo);
193+ loongson_pcibios_read(&bus, devfn, PCI_MSR_DATA_HI, 4, hi);
194+}
195+EXPORT_SYMBOL(_rdmsr);
196+
197+void _wrmsr(u32 msr, u32 hi, u32 lo)
198+{
199+ struct pci_bus bus = {
200+ .number = PCI_BUS_CS5536
201+ };
202+ u32 devfn = PCI_DEVFN(PCI_IDSEL_CS5536, 0);
203+ loongson_pcibios_write(&bus, devfn, PCI_MSR_ADDR, 4, msr);
204+ loongson_pcibios_write(&bus, devfn, PCI_MSR_DATA_LO, 4, lo);
205+ loongson_pcibios_write(&bus, devfn, PCI_MSR_DATA_HI, 4, hi);
206+}
207+EXPORT_SYMBOL(_wrmsr);
208+#endif
arch/mips/pci/pci-excite.c+0−149
@@ -1,149 +0,0 @@
1−/*
2− * Copyright (C) 2004 by Basler Vision Technologies AG
3− * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
4− * Based on the PMC-Sierra Yosemite board support by Ralf Baechle.
5− *
6− * This program is free software; you can redistribute it and/or modify
7− * it under the terms of the GNU General Public License as published by
8− * the Free Software Foundation; either version 2 of the License, or
9− * (at your option) any later version.
10− *
11− * This program is distributed in the hope that it will be useful,
12− * but WITHOUT ANY WARRANTY; without even the implied warranty of
13− * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14− * GNU General Public License for more details.
15− *
16− * You should have received a copy of the GNU General Public License
17− * along with this program; if not, write to the Free Software
18− * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19− */
20−#include <linux/init.h>
21−#include <linux/kernel.h>
22−#include <linux/types.h>
23−#include <linux/pci.h>
24−#include <linux/bitops.h>
25−#include <asm/rm9k-ocd.h>
26−#include <excite.h>
27−
28−
29−extern struct pci_ops titan_pci_ops;
30−
31−
32−static struct resource
33− mem_resource = {
34− .name = "PCI memory",
35− .start = EXCITE_PHYS_PCI_MEM,
36− .end = EXCITE_PHYS_PCI_MEM + EXCITE_SIZE_PCI_MEM - 1,
37− .flags = IORESOURCE_MEM
38− },
39− io_resource = {
40− .name = "PCI I/O",
41− .start = EXCITE_PHYS_PCI_IO,
42− .end = EXCITE_PHYS_PCI_IO + EXCITE_SIZE_PCI_IO - 1,
43− .flags = IORESOURCE_IO
44− };
45−
46−
47−static struct pci_controller bx_controller = {
48− .pci_ops = &titan_pci_ops,
49− .mem_resource = &mem_resource,
50− .mem_offset = 0x00000000UL,
51− .io_resource = &io_resource,
52− .io_offset = 0x00000000UL
53−};
54−
55−
56−static char
57− iopage_failed[] __initdata = "Cannot allocate PCI I/O page",
58− modebits_no_pci[] __initdata = "PCI is not configured in mode bits";
59−
60−#define RM9000x2_OCD_HTSC 0x0604
61−#define RM9000x2_OCD_HTBHL 0x060c
62−#define RM9000x2_OCD_PCIHRST 0x078c
63−
64−#define RM9K_OCD_MODEBIT1 0x00d4 /* (MODEBIT1) Mode Bit 1 */
65−#define RM9K_OCD_CPHDCR 0x00f4 /* CPU-PCI/HT Data Control. */
66−
67−#define PCISC_FB2B 0x00000200
68−#define PCISC_MWICG 0x00000010
69−#define PCISC_EMC 0x00000004
70−#define PCISC_ERMA 0x00000002
71−
72−
73−
74−static int __init basler_excite_pci_setup(void)
75−{
76− const unsigned int fullbars = memsize / (256 << 20);
77− unsigned int i;
78−
79− /* Check modebits to see if PCI is really enabled. */
80− if (!((ocd_readl(RM9K_OCD_MODEBIT1) >> (47-32)) & 0x1))
81− panic(modebits_no_pci);
82−
83− if (NULL == request_mem_region(EXCITE_PHYS_PCI_IO, EXCITE_SIZE_PCI_IO,
84− "Memory-mapped PCI I/O page"))
85− panic(iopage_failed);
86−
87− /* Enable PCI 0 as master for config cycles */
88− ocd_writel(PCISC_EMC | PCISC_ERMA, RM9000x2_OCD_HTSC);
89−
90−
91− /* Set up latency timer */
92− ocd_writel(0x8008, RM9000x2_OCD_HTBHL);
93−
94− /* Setup host IO and Memory space */
95− ocd_writel((EXCITE_PHYS_PCI_IO >> 4) | 1, LKB7);
96− ocd_writel(((EXCITE_SIZE_PCI_IO >> 4) & 0x7fffff00) - 0x100, LKM7);
97− ocd_writel((EXCITE_PHYS_PCI_MEM >> 4) | 1, LKB8);
98− ocd_writel(((EXCITE_SIZE_PCI_MEM >> 4) & 0x7fffff00) - 0x100, LKM8);
99−
100− /* Set up PCI BARs to map all installed memory */
101− for (i = 0; i < 6; i++) {
102− const unsigned int bar = 0x610 + i * 4;
103−
104− if (i < fullbars) {
105− ocd_writel(0x10000000 * i, bar);
106− ocd_writel(0x01000000 * i, bar + 0x140);
107− ocd_writel(0x0ffff029, bar + 0x100);
108− continue;
109− }
110−
111− if (i == fullbars) {
112− int o;
113− u32 mask;
114−
115− const unsigned long rem = memsize - i * 0x10000000;
116− if (!rem) {
117− ocd_writel(0x00000000, bar + 0x100);
118− continue;
119− }
120−
121− o = ffs(rem) - 1;
122− if (rem & ~(0x1 << o))
123− o++;
124− mask = ((0x1 << o) & 0x0ffff000) - 0x1000;
125− ocd_writel(0x10000000 * i, bar);
126− ocd_writel(0x01000000 * i, bar + 0x140);
127− ocd_writel(0x00000029 | mask, bar + 0x100);
128− continue;
129− }
130−
131− ocd_writel(0x00000000, bar + 0x100);
132− }
133−
134− /* Finally, enable the PCI interrupt */
135−#if USB_IRQ > 7
136− set_c0_intcontrol(1 << USB_IRQ);
137−#else
138− set_c0_status(1 << (USB_IRQ + 8));
139−#endif
140−
141− ioport_resource.start = EXCITE_PHYS_PCI_IO;
142− ioport_resource.end = EXCITE_PHYS_PCI_IO + EXCITE_SIZE_PCI_IO - 1;
143− set_io_port_base((unsigned long) ioremap_nocache(EXCITE_PHYS_PCI_IO, EXCITE_SIZE_PCI_IO));
144− register_pci_controller(&bx_controller);
145− return 0;
146−}
147−
148−
149−arch_initcall(basler_excite_pci_setup);
arch/mips/powertv/Kconfig+21−0
@@ -0,0 +1,21 @@
1+source "arch/mips/powertv/asic/Kconfig"
2+
3+config BOOTLOADER_DRIVER
4+ bool "PowerTV Bootloader Driver Support"
5+ default n
6+ depends on POWERTV
7+ help
8+ Use this option if you want to load bootloader driver.
9+
10+config BOOTLOADER_FAMILY
11+ string "POWERTV Bootloader Family string"
12+ default "85"
13+ depends on POWERTV && !BOOTLOADER_DRIVER
14+ help
15+ This value should be specified when the bootloader driver is disabled
16+ and must be exactly two characters long. Families supported are:
17+ R1 - RNG-100 R2 - RNG-200
18+ A1 - Class A B1 - Class B
19+ E1 - Class E F1 - Class F
20+ 44 - 45xx 46 - 46xx
21+ 85 - 85xx 86 - 86xx
arch/mips/powertv/Makefile+28−0
@@ -0,0 +1,28 @@
1+#
2+# Carsten Langgaard, carstenl@mips.com
3+# Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4+#
5+# Carsten Langgaard, carstenl@mips.com
6+# Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
7+# Portions copyright (C) 2009 Cisco Systems, Inc.
8+#
9+# This program is free software; you can distribute it and/or modify it
10+# under the terms of the GNU General Public License (Version 2) as
11+# published by the Free Software Foundation.
12+#
13+# This program is distributed in the hope it will be useful, but WITHOUT
14+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16+# for more details.
17+#
18+# You should have received a copy of the GNU General Public License along
19+# with this program; if not, write to the Free Software Foundation, Inc.,
20+# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
21+#
22+# Makefile for the Cisco PowerTV-specific kernel interface routines
23+# under Linux.
24+#
25+
26+obj-y += cmdline.o init.o memory.o reset.o time.o powertv_setup.o asic/ pci/
27+
28+EXTRA_CFLAGS += -Wall -Werror
arch/mips/powertv/asic/Kconfig+28−0
@@ -0,0 +1,28 @@
1+config MIN_RUNTIME_RESOURCES
2+ bool "Support for minimum runtime resources"
3+ default n
4+ depends on POWERTV
5+ help
6+ Enables support for minimizing the number of (SA asic) runtime
7+ resources that are preallocated by the kernel.
8+
9+config MIN_RUNTIME_DOCSIS
10+ bool "Support for minimum DOCSIS resource"
11+ default y
12+ depends on MIN_RUNTIME_RESOURCES
13+ help
14+ Enables support for the preallocated DOCSIS resource.
15+
16+config MIN_RUNTIME_PMEM
17+ bool "Support for minimum PMEM resource"
18+ default y
19+ depends on MIN_RUNTIME_RESOURCES
20+ help
21+ Enables support for the preallocated Memory resource.
22+
23+config MIN_RUNTIME_TFTP
24+ bool "Support for minimum TFTP resource"
25+ default y
26+ depends on MIN_RUNTIME_RESOURCES
27+ help
28+ Enables support for the preallocated TFTP resource.
arch/mips/powertv/asic/Makefile+23−0
@@ -0,0 +1,23 @@
1+#
2+# Copyright (C) 2009 Scientific-Atlanta, Inc.
3+#
4+# This program is free software; you can redistribute it and/or modify
5+# it under the terms of the GNU General Public License as published by
6+# the Free Software Foundation; either version 2 of the License, or
7+# (at your option) any later version.
8+#
9+# This program is distributed in the hope that it will be useful,
10+# but WITHOUT ANY WARRANTY; without even the implied warranty of
11+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12+# GNU General Public License for more details.
13+#
14+# You should have received a copy of the GNU General Public License
15+# along with this program; if not, write to the Free Software
16+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17+#
18+
19+obj-y += asic-calliope.o asic-cronus.o asic-zeus.o asic_devices.o asic_int.o \
20+ irq_asic.o prealloc-calliope.o prealloc-cronus.o \
21+ prealloc-cronuslite.o prealloc-zeus.o
22+
23+EXTRA_CFLAGS += -Wall -Werror
arch/mips/powertv/asic/asic-calliope.c+98−0
@@ -0,0 +1,98 @@
1+/*
2+ * Locations of devices in the Calliope ASIC.
3+ *
4+ * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
5+ *
6+ * This program is free software; you can redistribute it and/or modify
7+ * it under the terms of the GNU General Public License as published by
8+ * the Free Software Foundation; either version 2 of the License, or
9+ * (at your option) any later version.
10+ *
11+ * This program is distributed in the hope that it will be useful,
12+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
13+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14+ * GNU General Public License for more details.
15+ *
16+ * You should have received a copy of the GNU General Public License
17+ * along with this program; if not, write to the Free Software
18+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19+ *
20+ * Author: Ken Eppinett
21+ * David Schleef <ds@schleef.org>
22+ *
23+ * Description: Defines the platform resources for the SA settop.
24+ */
25+
26+#include <asm/mach-powertv/asic.h>
27+
28+const struct register_map calliope_register_map = {
29+ .eic_slow0_strt_add = 0x800000,
30+ .eic_cfg_bits = 0x800038,
31+ .eic_ready_status = 0x80004c,
32+
33+ .chipver3 = 0xA00800,
34+ .chipver2 = 0xA00804,
35+ .chipver1 = 0xA00808,
36+ .chipver0 = 0xA0080c,
37+
38+ /* The registers of IRBlaster */
39+ .uart1_intstat = 0xA01800,
40+ .uart1_inten = 0xA01804,
41+ .uart1_config1 = 0xA01808,
42+ .uart1_config2 = 0xA0180C,
43+ .uart1_divisorhi = 0xA01810,
44+ .uart1_divisorlo = 0xA01814,
45+ .uart1_data = 0xA01818,
46+ .uart1_status = 0xA0181C,
47+
48+ .int_stat_3 = 0xA02800,
49+ .int_stat_2 = 0xA02804,
50+ .int_stat_1 = 0xA02808,
51+ .int_stat_0 = 0xA0280c,
52+ .int_config = 0xA02810,
53+ .int_int_scan = 0xA02818,
54+ .ien_int_3 = 0xA02830,
55+ .ien_int_2 = 0xA02834,
56+ .ien_int_1 = 0xA02838,
57+ .ien_int_0 = 0xA0283c,
58+ .int_level_3_3 = 0xA02880,
59+ .int_level_3_2 = 0xA02884,
60+ .int_level_3_1 = 0xA02888,
61+ .int_level_3_0 = 0xA0288c,
62+ .int_level_2_3 = 0xA02890,
63+ .int_level_2_2 = 0xA02894,
64+ .int_level_2_1 = 0xA02898,
65+ .int_level_2_0 = 0xA0289c,
66+ .int_level_1_3 = 0xA028a0,
67+ .int_level_1_2 = 0xA028a4,
68+ .int_level_1_1 = 0xA028a8,
69+ .int_level_1_0 = 0xA028ac,
70+ .int_level_0_3 = 0xA028b0,
71+ .int_level_0_2 = 0xA028b4,
72+ .int_level_0_1 = 0xA028b8,
73+ .int_level_0_0 = 0xA028bc,
74+ .int_docsis_en = 0xA028F4,
75+
76+ .mips_pll_setup = 0x980000,
77+ .usb_fs = 0x980030, /* -default 72800028- */
78+ .test_bus = 0x9800CC,
79+ .crt_spare = 0x9800d4,
80+ .usb2_ohci_int_mask = 0x9A000c,
81+ .usb2_strap = 0x9A0014,
82+ .ehci_hcapbase = 0x9BFE00,
83+ .ohci_hc_revision = 0x9BFC00,
84+ .bcm1_bs_lmi_steer = 0x9E0004,
85+ .usb2_control = 0x9E0054,
86+ .usb2_stbus_obc = 0x9BFF00,
87+ .usb2_stbus_mess_size = 0x9BFF04,
88+ .usb2_stbus_chunk_size = 0x9BFF08,
89+
90+ .pcie_regs = 0x000000, /* -doesn't exist- */
91+ .tim_ch = 0xA02C10,
92+ .tim_cl = 0xA02C14,
93+ .gpio_dout = 0xA02c20,
94+ .gpio_din = 0xA02c24,
95+ .gpio_dir = 0xA02c2C,
96+ .watchdog = 0xA02c30,
97+ .front_panel = 0x000000, /* -not used- */
98+};
arch/mips/powertv/asic/asic-cronus.c+98−0
@@ -0,0 +1,98 @@
1+/*
2+ * Locations of devices in the Cronus ASIC
3+ *
4+ * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
5+ *
6+ * This program is free software; you can redistribute it and/or modify
7+ * it under the terms of the GNU General Public License as published by
8+ * the Free Software Foundation; either version 2 of the License, or
9+ * (at your option) any later version.
10+ *
11+ * This program is distributed in the hope that it will be useful,
12+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
13+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14+ * GNU General Public License for more details.
15+ *
16+ * You should have received a copy of the GNU General Public License
17+ * along with this program; if not, write to the Free Software
18+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19+ *
20+ * Author: Ken Eppinett
21+ * David Schleef <ds@schleef.org>
22+ *
23+ * Description: Defines the platform resources for the SA settop.
24+ */
25+
26+#include <asm/mach-powertv/asic.h>
27+
28+const struct register_map cronus_register_map = {
29+ .eic_slow0_strt_add = 0x000000,
30+ .eic_cfg_bits = 0x000038,
31+ .eic_ready_status = 0x00004C,
32+
33+ .chipver3 = 0x2A0800,
34+ .chipver2 = 0x2A0804,
35+ .chipver1 = 0x2A0808,
36+ .chipver0 = 0x2A080C,
37+
38+ /* The registers of IRBlaster */
39+ .uart1_intstat = 0x2A1800,
40+ .uart1_inten = 0x2A1804,
41+ .uart1_config1 = 0x2A1808,
42+ .uart1_config2 = 0x2A180C,
43+ .uart1_divisorhi = 0x2A1810,
44+ .uart1_divisorlo = 0x2A1814,
45+ .uart1_data = 0x2A1818,
46+ .uart1_status = 0x2A181C,
47+
48+ .int_stat_3 = 0x2A2800,
49+ .int_stat_2 = 0x2A2804,
50+ .int_stat_1 = 0x2A2808,
51+ .int_stat_0 = 0x2A280C,
52+ .int_config = 0x2A2810,
53+ .int_int_scan = 0x2A2818,
54+ .ien_int_3 = 0x2A2830,
55+ .ien_int_2 = 0x2A2834,
56+ .ien_int_1 = 0x2A2838,
57+ .ien_int_0 = 0x2A283C,
58+ .int_level_3_3 = 0x2A2880,
59+ .int_level_3_2 = 0x2A2884,
60+ .int_level_3_1 = 0x2A2888,
61+ .int_level_3_0 = 0x2A288C,
62+ .int_level_2_3 = 0x2A2890,
63+ .int_level_2_2 = 0x2A2894,
64+ .int_level_2_1 = 0x2A2898,
65+ .int_level_2_0 = 0x2A289C,
66+ .int_level_1_3 = 0x2A28A0,
67+ .int_level_1_2 = 0x2A28A4,
68+ .int_level_1_1 = 0x2A28A8,
69+ .int_level_1_0 = 0x2A28AC,
70+ .int_level_0_3 = 0x2A28B0,
71+ .int_level_0_2 = 0x2A28B4,
72+ .int_level_0_1 = 0x2A28B8,
73+ .int_level_0_0 = 0x2A28BC,
74+ .int_docsis_en = 0x2A28F4,
75+
76+ .mips_pll_setup = 0x1C0000,
77+ .usb_fs = 0x1C0018,
78+ .test_bus = 0x1C00CC,
79+ .crt_spare = 0x1c00d4,
80+ .usb2_ohci_int_mask = 0x20000C,
81+ .usb2_strap = 0x200014,
82+ .ehci_hcapbase = 0x21FE00,
83+ .ohci_hc_revision = 0x1E0000,
84+ .bcm1_bs_lmi_steer = 0x2E0008,
85+ .usb2_control = 0x2E004C,
86+ .usb2_stbus_obc = 0x21FF00,
87+ .usb2_stbus_mess_size = 0x21FF04,
88+ .usb2_stbus_chunk_size = 0x21FF08,
89+
90+ .pcie_regs = 0x220000,
91+ .tim_ch = 0x2A2C10,
92+ .tim_cl = 0x2A2C14,
93+ .gpio_dout = 0x2A2C20,
94+ .gpio_din = 0x2A2C24,
95+ .gpio_dir = 0x2A2C2C,
96+ .watchdog = 0x2A2C30,
97+ .front_panel = 0x2A3800,
98+};
arch/mips/powertv/asic/asic-zeus.c+98−0
@@ -0,0 +1,98 @@
1+/*
2+ * Locations of devices in the Zeus ASIC
3+ *
4+ * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
5+ *
6+ * This program is free software; you can redistribute it and/or modify
7+ * it under the terms of the GNU General Public License as published by
8+ * the Free Software Foundation; either version 2 of the License, or
9+ * (at your option) any later version.
10+ *
11+ * This program is distributed in the hope that it will be useful,
12+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
13+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14+ * GNU General Public License for more details.
15+ *
16+ * You should have received a copy of the GNU General Public License
17+ * along with this program; if not, write to the Free Software
18+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19+ *
20+ * Author: Ken Eppinett
21+ * David Schleef <ds@schleef.org>
22+ *
23+ * Description: Defines the platform resources for the SA settop.
24+ */
25+
26+#include <asm/mach-powertv/asic.h>
27+
28+const struct register_map zeus_register_map = {
29+ .eic_slow0_strt_add = 0x000000,
30+ .eic_cfg_bits = 0x000038,
31+ .eic_ready_status = 0x00004c,
32+
33+ .chipver3 = 0x280800,
34+ .chipver2 = 0x280804,
35+ .chipver1 = 0x280808,
36+ .chipver0 = 0x28080c,
37+
38+ /* The registers of IRBlaster */
39+ .uart1_intstat = 0x281800,
40+ .uart1_inten = 0x281804,
41+ .uart1_config1 = 0x281808,
42+ .uart1_config2 = 0x28180C,
43+ .uart1_divisorhi = 0x281810,
44+ .uart1_divisorlo = 0x281814,
45+ .uart1_data = 0x281818,
46+ .uart1_status = 0x28181C,
47+
48+ .int_stat_3 = 0x282800,
49+ .int_stat_2 = 0x282804,
50+ .int_stat_1 = 0x282808,
51+ .int_stat_0 = 0x28280c,
52+ .int_config = 0x282810,
53+ .int_int_scan = 0x282818,
54+ .ien_int_3 = 0x282830,
55+ .ien_int_2 = 0x282834,
56+ .ien_int_1 = 0x282838,
57+ .ien_int_0 = 0x28283c,
58+ .int_level_3_3 = 0x282880,
59+ .int_level_3_2 = 0x282884,
60+ .int_level_3_1 = 0x282888,
61+ .int_level_3_0 = 0x28288c,
62+ .int_level_2_3 = 0x282890,
63+ .int_level_2_2 = 0x282894,
64+ .int_level_2_1 = 0x282898,
65+ .int_level_2_0 = 0x28289c,
66+ .int_level_1_3 = 0x2828a0,
67+ .int_level_1_2 = 0x2828a4,
68+ .int_level_1_1 = 0x2828a8,
69+ .int_level_1_0 = 0x2828ac,
70+ .int_level_0_3 = 0x2828b0,
71+ .int_level_0_2 = 0x2828b4,
72+ .int_level_0_1 = 0x2828b8,
73+ .int_level_0_0 = 0x2828bc,
74+ .int_docsis_en = 0x2828F4,
75+
76+ .mips_pll_setup = 0x1a0000,
77+ .usb_fs = 0x1a0018,
78+ .test_bus = 0x1a0238,
79+ .crt_spare = 0x1a0090,
80+ .usb2_ohci_int_mask = 0x1e000c,
81+ .usb2_strap = 0x1e0014,
82+ .ehci_hcapbase = 0x1FFE00,
83+ .ohci_hc_revision = 0x1FFC00,
84+ .bcm1_bs_lmi_steer = 0x2C0008,
85+ .usb2_control = 0x2c01a0,
86+ .usb2_stbus_obc = 0x1FFF00,
87+ .usb2_stbus_mess_size = 0x1FFF04,
88+ .usb2_stbus_chunk_size = 0x1FFF08,
89+
90+ .pcie_regs = 0x200000,
91+ .tim_ch = 0x282C10,
92+ .tim_cl = 0x282C14,
93+ .gpio_dout = 0x282c20,
94+ .gpio_din = 0x282c24,
95+ .gpio_dir = 0x282c2C,
96+ .watchdog = 0x282c30,
97+ .front_panel = 0x283800,
98+};
arch/mips/powertv/asic/asic_devices.c+787−0
@@ -0,0 +1,787 @@
1+/*
2+ * ASIC Device List Intialization
3+ *
4+ * Description: Defines the platform resources for the SA settop.
5+ *
6+ * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
7+ *
8+ * This program is free software; you can redistribute it and/or modify
9+ * it under the terms of the GNU General Public License as published by
10+ * the Free Software Foundation; either version 2 of the License, or
11+ * (at your option) any later version.
12+ *
13+ * This program is distributed in the hope that it will be useful,
14+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
15+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16+ * GNU General Public License for more details.
17+ *
18+ * You should have received a copy of the GNU General Public License
19+ * along with this program; if not, write to the Free Software
20+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21+ *
22+ * Author: Ken Eppinett
23+ * David Schleef <ds@schleef.org>
24+ *
25+ * Description: Defines the platform resources for the SA settop.
26+ *
27+ * NOTE: The bootloader allocates persistent memory at an address which is
28+ * 16 MiB below the end of the highest address in KSEG0. All fixed
29+ * address memory reservations must avoid this region.
30+ */
31+
32+#include <linux/device.h>
33+#include <linux/kernel.h>
34+#include <linux/init.h>
35+#include <linux/resource.h>
36+#include <linux/serial_reg.h>
37+#include <linux/io.h>
38+#include <linux/bootmem.h>
39+#include <linux/mm.h>
40+#include <linux/platform_device.h>
41+#include <linux/module.h>
42+#include <asm/page.h>
43+#include <linux/swap.h>
44+#include <linux/highmem.h>
45+#include <linux/dma-mapping.h>
46+
47+#include <asm/mach-powertv/asic.h>
48+#include <asm/mach-powertv/asic_regs.h>
49+#include <asm/mach-powertv/interrupts.h>
50+
51+#ifdef CONFIG_BOOTLOADER_DRIVER
52+#include <asm/mach-powertv/kbldr.h>
53+#endif
54+#include <asm/bootinfo.h>
55+
56+#define BOOTLDRFAMILY(byte1, byte0) (((byte1) << 8) | (byte0))
57+
58+/*
59+ * Forward Prototypes
60+ */
61+static void pmem_setup_resource(void);
62+
63+/*
64+ * Global Variables
65+ */
66+enum asic_type asic;
67+
68+unsigned int platform_features;
69+unsigned int platform_family;
70+const struct register_map *register_map;
71+EXPORT_SYMBOL(register_map); /* Exported for testing */
72+unsigned long asic_phy_base;
73+unsigned long asic_base;
74+EXPORT_SYMBOL(asic_base); /* Exported for testing */
75+struct resource *gp_resources;
76+static bool usb_configured;
77+
78+/*
79+ * Don't recommend to use it directly, it is usually used by kernel internally.
80+ * Portable code should be using interfaces such as ioremp, dma_map_single, etc.
81+ */
82+unsigned long phys_to_bus_offset;
83+EXPORT_SYMBOL(phys_to_bus_offset);
84+
85+/*
86+ *
87+ * IO Resource Definition
88+ *
89+ */
90+
91+struct resource asic_resource = {
92+ .name = "ASIC Resource",
93+ .start = 0,
94+ .end = ASIC_IO_SIZE,
95+ .flags = IORESOURCE_MEM,
96+};
97+
98+/*
99+ *
100+ * USB Host Resource Definition
101+ *
102+ */
103+
104+static struct resource ehci_resources[] = {
105+ {
106+ .parent = &asic_resource,
107+ .start = 0,
108+ .end = 0xff,
109+ .flags = IORESOURCE_MEM,
110+ },
111+ {
112+ .start = irq_usbehci,
113+ .end = irq_usbehci,
114+ .flags = IORESOURCE_IRQ,
115+ },
116+};
117+
118+static u64 ehci_dmamask = DMA_BIT_MASK(32);
119+
120+static struct platform_device ehci_device = {
121+ .name = "powertv-ehci",
122+ .id = 0,
123+ .num_resources = 2,
124+ .resource = ehci_resources,
125+ .dev = {
126+ .dma_mask = &ehci_dmamask,
127+ .coherent_dma_mask = DMA_BIT_MASK(32),
128+ },
129+};
130+
131+static struct resource ohci_resources[] = {
132+ {
133+ .parent = &asic_resource,
134+ .start = 0,
135+ .end = 0xff,
136+ .flags = IORESOURCE_MEM,
137+ },
138+ {
139+ .start = irq_usbohci,
140+ .end = irq_usbohci,
141+ .flags = IORESOURCE_IRQ,
142+ },
143+};
144+
145+static u64 ohci_dmamask = DMA_BIT_MASK(32);
146+
147+static struct platform_device ohci_device = {
148+ .name = "powertv-ohci",
149+ .id = 0,
150+ .num_resources = 2,
151+ .resource = ohci_resources,
152+ .dev = {
153+ .dma_mask = &ohci_dmamask,
154+ .coherent_dma_mask = DMA_BIT_MASK(32),
155+ },
156+};
157+
158+static struct platform_device *platform_devices[] = {
159+ &ehci_device,
160+ &ohci_device,
161+};
162+
163+/*
164+ *
165+ * Platform Configuration and Device Initialization
166+ *
167+ */
168+static void __init fs_update(int pe, int md, int sdiv, int disable_div_by_3)
169+{
170+ int en_prg, byp, pwr, nsb, val;
171+ int sout;
172+
173+ sout = 1;
174+ en_prg = 1;
175+ byp = 0;
176+ nsb = 1;
177+ pwr = 1;
178+
179+ val = ((sdiv << 29) | (md << 24) | (pe<<8) | (sout<<3) | (byp<<2) |
180+ (nsb<<1) | (disable_div_by_3<<5));
181+
182+ asic_write(val, usb_fs);
183+ asic_write(val | (en_prg<<4), usb_fs);
184+ asic_write(val | (en_prg<<4) | pwr, usb_fs);
185+}
186+
187+/*
188+ * Allow override of bootloader-specified model
189+ */
190+static char __initdata cmdline[COMMAND_LINE_SIZE];
191+
192+#define FORCEFAMILY_PARAM "forcefamily"
193+
194+static __init int check_forcefamily(unsigned char forced_family[2])
195+{
196+ const char *p;
197+
198+ forced_family[0] = '\0';
199+ forced_family[1] = '\0';
200+
201+ /* Check the command line for a forcefamily directive */
202+ strncpy(cmdline, arcs_cmdline, COMMAND_LINE_SIZE - 1);
203+ p = strstr(cmdline, FORCEFAMILY_PARAM);
204+ if (p && (p != cmdline) && (*(p - 1) != ' '))
205+ p = strstr(p, " " FORCEFAMILY_PARAM "=");
206+
207+ if (p) {
208+ p += strlen(FORCEFAMILY_PARAM "=");
209+
210+ if (*p == '\0' || *(p + 1) == '\0' ||
211+ (*(p + 2) != '\0' && *(p + 2) != ' '))
212+ pr_err(FORCEFAMILY_PARAM " must be exactly two "
213+ "characters long, ignoring value\n");
214+
215+ else {
216+ forced_family[0] = *p;
217+ forced_family[1] = *(p + 1);
218+ }
219+ }
220+
221+ return 0;
222+}
223+
224+/*
225+ * platform_set_family - determine major platform family type.
226+ *
227+ * Returns family type; -1 if none
228+ * Returns the family type; -1 if none
229+ *
230+ */
231+static __init noinline void platform_set_family(void)
232+{
233+#define BOOTLDRFAMILY(byte1, byte0) (((byte1) << 8) | (byte0))
234+
235+ unsigned char forced_family[2];
236+ unsigned short bootldr_family;
237+
238+ check_forcefamily(forced_family);
239+
240+ if (forced_family[0] != '\0' && forced_family[1] != '\0')
241+ bootldr_family = BOOTLDRFAMILY(forced_family[0],
242+ forced_family[1]);
243+ else {
244+
245+#ifdef CONFIG_BOOTLOADER_DRIVER
246+ bootldr_family = (unsigned short) kbldr_GetSWFamily();
247+#else
248+#if defined(CONFIG_BOOTLOADER_FAMILY)
249+ bootldr_family = (unsigned short) BOOTLDRFAMILY(
250+ CONFIG_BOOTLOADER_FAMILY[0],
251+ CONFIG_BOOTLOADER_FAMILY[1]);
252+#else
253+#error "Unknown Bootloader Family"
254+#endif
255+#endif
256+ }
257+
258+ pr_info("Bootloader Family = 0x%04X\n", bootldr_family);
259+
260+ switch (bootldr_family) {
261+ case BOOTLDRFAMILY('R', '1'):
262+ platform_family = FAMILY_1500;
263+ break;
264+ case BOOTLDRFAMILY('4', '4'):
265+ platform_family = FAMILY_4500;
266+ break;
267+ case BOOTLDRFAMILY('4', '6'):
268+ platform_family = FAMILY_4600;
269+ break;
270+ case BOOTLDRFAMILY('A', '1'):
271+ platform_family = FAMILY_4600VZA;
272+ break;
273+ case BOOTLDRFAMILY('8', '5'):
274+ platform_family = FAMILY_8500;
275+ break;
276+ case BOOTLDRFAMILY('R', '2'):
277+ platform_family = FAMILY_8500RNG;
278+ break;
279+ case BOOTLDRFAMILY('8', '6'):
280+ platform_family = FAMILY_8600;
281+ break;
282+ case BOOTLDRFAMILY('B', '1'):
283+ platform_family = FAMILY_8600VZB;
284+ break;
285+ case BOOTLDRFAMILY('E', '1'):
286+ platform_family = FAMILY_1500VZE;
287+ break;
288+ case BOOTLDRFAMILY('F', '1'):
289+ platform_family = FAMILY_1500VZF;
290+ break;
291+ default:
292+ platform_family = -1;
293+ }
294+}
295+
296+unsigned int platform_get_family(void)
297+{
298+ return platform_family;
299+}
300+EXPORT_SYMBOL(platform_get_family);
301+
302+/*
303+ * \brief usb_eye_configure() for optimizing the USB eye on Calliope.
304+ *
305+ * \param unsigned int value saved to the register.
306+ *
307+ * \return none
308+ *
309+ */
310+static void __init usb_eye_configure(unsigned int value)
311+{
312+ asic_write(asic_read(crt_spare) | value, crt_spare);
313+}
314+
315+/*
316+ * platform_get_asic - determine the ASIC type.
317+ *
318+ * \param none
319+ *
320+ * \return ASIC type; ASIC_UNKNOWN if none
321+ *
322+ */
323+enum asic_type platform_get_asic(void)
324+{
325+ return asic;
326+}
327+EXPORT_SYMBOL(platform_get_asic);
328+
329+/*
330+ * platform_configure_usb - usb configuration based on platform type.
331+ * @bcm1_usb2_ctl: value for the BCM1_USB2_CTL register, which is
332+ * quirky
333+ */
334+static void __init platform_configure_usb(void)
335+{
336+ u32 bcm1_usb2_ctl;
337+
338+ if (usb_configured)
339+ return;
340+
341+ switch (asic) {
342+ case ASIC_ZEUS:
343+ fs_update(0x0000, 0x11, 0x02, 0);
344+ bcm1_usb2_ctl = 0x803;
345+ break;
346+
347+ case ASIC_CRONUS:
348+ case ASIC_CRONUSLITE:
349+ fs_update(0x0000, 0x11, 0x02, 0);
350+ bcm1_usb2_ctl = 0x803;
351+ break;
352+
353+ case ASIC_CALLIOPE:
354+ fs_update(0x0000, 0x11, 0x02, 1);
355+
356+ switch (platform_family) {
357+ case FAMILY_1500VZE:
358+ break;
359+
360+ case FAMILY_1500VZF:
361+ usb_eye_configure(0x003c0000);
362+ break;
363+
364+ default:
365+ usb_eye_configure(0x00300000);
366+ break;
367+ }
368+
369+ bcm1_usb2_ctl = 0x803;
370+ break;
371+
372+ default:
373+ pr_err("Unknown ASIC type: %d\n", asic);
374+ break;
375+ }
376+
377+ /* turn on USB power */
378+ asic_write(0, usb2_strap);
379+ /* Enable all OHCI interrupts */
380+ asic_write(bcm1_usb2_ctl, usb2_control);
381+ /* USB2_STBUS_OBC store32/load32 */
382+ asic_write(3, usb2_stbus_obc);
383+ /* USB2_STBUS_MESS_SIZE 2 packets */
384+ asic_write(1, usb2_stbus_mess_size);
385+ /* USB2_STBUS_CHUNK_SIZE 2 packets */
386+ asic_write(1, usb2_stbus_chunk_size);
387+
388+ usb_configured = true;
389+}
390+
391+/*
392+ * Set up the USB EHCI interface
393+ */
394+void platform_configure_usb_ehci()
395+{
396+ platform_configure_usb();
397+}
398+
399+/*
400+ * Set up the USB OHCI interface
401+ */
402+void platform_configure_usb_ohci()
403+{
404+ platform_configure_usb();
405+}
406+
407+/*
408+ * Shut the USB EHCI interface down--currently a NOP
409+ */
410+void platform_unconfigure_usb_ehci()
411+{
412+}
413+
414+/*
415+ * Shut the USB OHCI interface down--currently a NOP
416+ */
417+void platform_unconfigure_usb_ohci()
418+{
419+}
420+
421+/**
422+ * configure_platform - configuration based on platform type.
423+ */
424+void __init configure_platform(void)
425+{
426+ platform_set_family();
427+
428+ switch (platform_family) {
429+ case FAMILY_1500:
430+ case FAMILY_1500VZE:
431+ case FAMILY_1500VZF:
432+ platform_features = FFS_CAPABLE;
433+ asic = ASIC_CALLIOPE;
434+ asic_phy_base = CALLIOPE_IO_BASE;
435+ register_map = &calliope_register_map;
436+ asic_base = (unsigned long)ioremap_nocache(asic_phy_base,
437+ ASIC_IO_SIZE);
438+
439+ if (platform_family == FAMILY_1500VZE) {
440+ gp_resources = non_dvr_vze_calliope_resources;
441+ pr_info("Platform: 1500/Vz Class E - "
442+ "CALLIOPE, NON_DVR_CAPABLE\n");
443+ } else if (platform_family == FAMILY_1500VZF) {
444+ gp_resources = non_dvr_vzf_calliope_resources;
445+ pr_info("Platform: 1500/Vz Class F - "
446+ "CALLIOPE, NON_DVR_CAPABLE\n");
447+ } else {
448+ gp_resources = non_dvr_calliope_resources;
449+ pr_info("Platform: 1500/RNG100 - CALLIOPE, "
450+ "NON_DVR_CAPABLE\n");
451+ }
452+ break;
453+
454+ case FAMILY_4500:
455+ platform_features = FFS_CAPABLE | PCIE_CAPABLE |
456+ DISPLAY_CAPABLE;
457+ asic = ASIC_ZEUS;
458+ asic_phy_base = ZEUS_IO_BASE;
459+ register_map = &zeus_register_map;
460+ asic_base = (unsigned long)ioremap_nocache(asic_phy_base,
461+ ASIC_IO_SIZE);
462+ gp_resources = non_dvr_zeus_resources;
463+
464+ pr_info("Platform: 4500 - ZEUS, NON_DVR_CAPABLE\n");
465+ break;
466+
467+ case FAMILY_4600:
468+ {
469+ unsigned int chipversion = 0;
470+
471+ /* The settop has PCIE but it isn't used, so don't advertise
472+ * it*/
473+ platform_features = FFS_CAPABLE | DISPLAY_CAPABLE;
474+ asic_phy_base = CRONUS_IO_BASE; /* same as Cronus */
475+ register_map = &cronus_register_map; /* same as Cronus */
476+ asic_base = (unsigned long)ioremap_nocache(asic_phy_base,
477+ ASIC_IO_SIZE);
478+ gp_resources = non_dvr_cronuslite_resources;
479+
480+ /* ASIC version will determine if this is a real CronusLite or
481+ * Castrati(Cronus) */
482+ chipversion = asic_read(chipver3) << 24;
483+ chipversion |= asic_read(chipver2) << 16;
484+ chipversion |= asic_read(chipver1) << 8;
485+ chipversion |= asic_read(chipver0);
486+
487+ if ((chipversion == CRONUS_10) || (chipversion == CRONUS_11))
488+ asic = ASIC_CRONUS;
489+ else
490+ asic = ASIC_CRONUSLITE;
491+
492+ pr_info("Platform: 4600 - %s, NON_DVR_CAPABLE, "
493+ "chipversion=0x%08X\n",
494+ (asic == ASIC_CRONUS) ? "CRONUS" : "CRONUS LITE",
495+ chipversion);
496+ break;
497+ }
498+ case FAMILY_4600VZA:
499+ platform_features = FFS_CAPABLE | DISPLAY_CAPABLE;
500+ asic = ASIC_CRONUS;
501+ asic_phy_base = CRONUS_IO_BASE;
502+ register_map = &cronus_register_map;
503+ asic_base = (unsigned long)ioremap_nocache(asic_phy_base,
504+ ASIC_IO_SIZE);
505+ gp_resources = non_dvr_cronus_resources;
506+
507+ pr_info("Platform: Vz Class A - CRONUS, NON_DVR_CAPABLE\n");
508+ break;
509+
510+ case FAMILY_8500:
511+ case FAMILY_8500RNG:
512+ platform_features = DVR_CAPABLE | PCIE_CAPABLE |
513+ DISPLAY_CAPABLE;
514+ asic = ASIC_ZEUS;
515+ asic_phy_base = ZEUS_IO_BASE;
516+ register_map = &zeus_register_map;
517+ asic_base = (unsigned long)ioremap_nocache(asic_phy_base,
518+ ASIC_IO_SIZE);
519+ gp_resources = dvr_zeus_resources;
520+
521+ pr_info("Platform: 8500/RNG200 - ZEUS, DVR_CAPABLE\n");
522+ break;
523+
524+ case FAMILY_8600:
525+ case FAMILY_8600VZB:
526+ platform_features = DVR_CAPABLE | PCIE_CAPABLE |
527+ DISPLAY_CAPABLE;
528+ asic = ASIC_CRONUS;
529+ asic_phy_base = CRONUS_IO_BASE;
530+ register_map = &cronus_register_map;
531+ asic_base = (unsigned long)ioremap_nocache(asic_phy_base,
532+ ASIC_IO_SIZE);
533+ gp_resources = dvr_cronus_resources;
534+
535+ pr_info("Platform: 8600/Vz Class B - CRONUS, "
536+ "DVR_CAPABLE\n");
537+ break;
538+
539+ default:
540+ pr_crit("Platform: UNKNOWN PLATFORM\n");
541+ break;
542+ }
543+
544+ switch (asic) {
545+ case ASIC_ZEUS:
546+ phys_to_bus_offset = 0x30000000;
547+ break;
548+ case ASIC_CALLIOPE:
549+ phys_to_bus_offset = 0x10000000;
550+ break;
551+ case ASIC_CRONUSLITE:
552+ /* Fall through */
553+ case ASIC_CRONUS:
554+ /*
555+ * TODO: We suppose 0x10000000 aliases into 0x20000000-
556+ * 0x2XXXXXXX. If 0x10000000 aliases into 0x60000000-
557+ * 0x6XXXXXXX, the offset should be 0x50000000, not 0x10000000.
558+ */
559+ phys_to_bus_offset = 0x10000000;
560+ break;
561+ default:
562+ phys_to_bus_offset = 0x00000000;
563+ break;
564+ }
565+}
566+
567+/**
568+ * platform_devices_init - sets up USB device resourse.
569+ */
570+static int __init platform_devices_init(void)
571+{
572+ pr_notice("%s: ----- Initializing USB resources -----\n", __func__);
573+
574+ asic_resource.start = asic_phy_base;
575+ asic_resource.end += asic_resource.start;
576+
577+ ehci_resources[0].start = asic_reg_phys_addr(ehci_hcapbase);
578+ ehci_resources[0].end += ehci_resources[0].start;
579+
580+ ohci_resources[0].start = asic_reg_phys_addr(ohci_hc_revision);
581+ ohci_resources[0].end += ohci_resources[0].start;
582+
583+ set_io_port_base(0);
584+
585+ platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
586+
587+ return 0;
588+}
589+
590+arch_initcall(platform_devices_init);
591+
592+/*
593+ *
594+ * BOOTMEM ALLOCATION
595+ *
596+ */
597+/*
598+ * Allocates/reserves the Platform memory resources early in the boot process.
599+ * This ignores any resources that are designated IORESOURCE_IO
600+ */
601+void __init platform_alloc_bootmem(void)
602+{
603+ int i;
604+ int total = 0;
605+
606+ /* Get persistent memory data from command line before allocating
607+ * resources. This need to happen before normal command line parsing
608+ * has been done */
609+ pmem_setup_resource();
610+
611+ /* Loop through looking for resources that want a particular address */
612+ for (i = 0; gp_resources[i].flags != 0; i++) {
613+ int size = gp_resources[i].end - gp_resources[i].start + 1;
614+ if ((gp_resources[i].start != 0) &&
615+ ((gp_resources[i].flags & IORESOURCE_MEM) != 0)) {
616+ reserve_bootmem(bus_to_phys(gp_resources[i].start),
617+ size, 0);
618+ total += gp_resources[i].end -
619+ gp_resources[i].start + 1;
620+ pr_info("reserve resource %s at %08x (%u bytes)\n",
621+ gp_resources[i].name, gp_resources[i].start,
622+ gp_resources[i].end -
623+ gp_resources[i].start + 1);
624+ }
625+ }
626+
627+ /* Loop through assigning addresses for those that are left */
628+ for (i = 0; gp_resources[i].flags != 0; i++) {
629+ int size = gp_resources[i].end - gp_resources[i].start + 1;
630+ if ((gp_resources[i].start == 0) &&
631+ ((gp_resources[i].flags & IORESOURCE_MEM) != 0)) {
632+ void *mem = alloc_bootmem_pages(size);
633+
634+ if (mem == NULL)
635+ pr_err("Unable to allocate bootmem pages "
636+ "for %s\n", gp_resources[i].name);
637+
638+ else {
639+ gp_resources[i].start =
640+ phys_to_bus(virt_to_phys(mem));
641+ gp_resources[i].end =
642+ gp_resources[i].start + size - 1;
643+ total += size;
644+ pr_info("allocate resource %s at %08x "
645+ "(%u bytes)\n",
646+ gp_resources[i].name,
647+ gp_resources[i].start, size);
648+ }
649+ }
650+ }
651+
652+ pr_info("Total Platform driver memory allocation: 0x%08x\n", total);
653+
654+ /* indicate resources that are platform I/O related */
655+ for (i = 0; gp_resources[i].flags != 0; i++) {
656+ if ((gp_resources[i].start != 0) &&
657+ ((gp_resources[i].flags & IORESOURCE_IO) != 0)) {
658+ pr_info("reserved platform resource %s at %08x\n",
659+ gp_resources[i].name, gp_resources[i].start);
660+ }
661+ }
662+}
663+
664+/*
665+ *
666+ * PERSISTENT MEMORY (PMEM) CONFIGURATION
667+ *
668+ */
669+static unsigned long pmemaddr __initdata;
670+
671+static int __init early_param_pmemaddr(char *p)
672+{
673+ pmemaddr = (unsigned long)simple_strtoul(p, NULL, 0);
674+ return 0;
675+}
676+early_param("pmemaddr", early_param_pmemaddr);
677+
678+static long pmemlen __initdata;
679+
680+static int __init early_param_pmemlen(char *p)
681+{
682+/* TODO: we can use this code when and if the bootloader ever changes this */
683+#if 0
684+ pmemlen = (unsigned long)simple_strtoul(p, NULL, 0);
685+#else
686+ pmemlen = 0x20000;
687+#endif
688+ return 0;
689+}
690+early_param("pmemlen", early_param_pmemlen);
691+
692+/*
693+ * Set up persistent memory. If we were given values, we patch the array of
694+ * resources. Otherwise, persistent memory may be allocated anywhere at all.
695+ */
696+static void __init pmem_setup_resource(void)
697+{
698+ struct resource *resource;
699+ resource = asic_resource_get("DiagPersistentMemory");
700+
701+ if (resource && pmemaddr && pmemlen) {
702+ /* The address provided by bootloader is in kseg0. Convert to
703+ * a bus address. */
704+ resource->start = phys_to_bus(pmemaddr - 0x80000000);
705+ resource->end = resource->start + pmemlen - 1;
706+
707+ pr_info("persistent memory: start=0x%x end=0x%x\n",
708+ resource->start, resource->end);
709+ }
710+}
711+
712+/*
713+ *
714+ * RESOURCE ACCESS FUNCTIONS
715+ *
716+ */
717+
718+/**
719+ * asic_resource_get - retrieves parameters for a platform resource.
720+ * @name: string to match resource
721+ *
722+ * Returns a pointer to a struct resource corresponding to the given name.
723+ *
724+ * CANNOT BE NAMED platform_resource_get, which would be the obvious choice,
725+ * as this function name is already declared
726+ */
727+struct resource *asic_resource_get(const char *name)
728+{
729+ int i;
730+
731+ for (i = 0; gp_resources[i].flags != 0; i++) {
732+ if (strcmp(gp_resources[i].name, name) == 0)
733+ return &gp_resources[i];
734+ }
735+
736+ return NULL;
737+}
738+EXPORT_SYMBOL(asic_resource_get);
739+
740+/**
741+ * platform_release_memory - release pre-allocated memory
742+ * @ptr: pointer to memory to release
743+ * @size: size of resource
744+ *
745+ * This must only be called for memory allocated or reserved via the boot
746+ * memory allocator.
747+ */
748+void platform_release_memory(void *ptr, int size)
749+{
750+ unsigned long addr;
751+ unsigned long end;
752+
753+ addr = ((unsigned long)ptr + (PAGE_SIZE - 1)) & PAGE_MASK;
754+ end = ((unsigned long)ptr + size) & PAGE_MASK;
755+
756+ for (; addr < end; addr += PAGE_SIZE) {
757+ ClearPageReserved(virt_to_page(__va(addr)));
758+ init_page_count(virt_to_page(__va(addr)));
759+ free_page((unsigned long)__va(addr));
760+ }
761+}
762+EXPORT_SYMBOL(platform_release_memory);
763+
764+/*
765+ *
766+ * FEATURE AVAILABILITY FUNCTIONS
767+ *
768+ */
769+int platform_supports_dvr(void)
770+{
771+ return (platform_features & DVR_CAPABLE) != 0;
772+}
773+
774+int platform_supports_ffs(void)
775+{
776+ return (platform_features & FFS_CAPABLE) != 0;
777+}
778+
779+int platform_supports_pcie(void)
780+{
781+ return (platform_features & PCIE_CAPABLE) != 0;
782+}
783+
784+int platform_supports_display(void)
785+{
786+ return (platform_features & DISPLAY_CAPABLE) != 0;
787+}
arch/mips/powertv/asic/asic_int.c+125−0
@@ -0,0 +1,125 @@
1+/*
2+ * Carsten Langgaard, carstenl@mips.com
3+ * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc.
4+ * Copyright (C) 2001 Ralf Baechle
5+ * Portions copyright (C) 2009 Cisco Systems, Inc.
6+ *
7+ * This program is free software; you can distribute it and/or modify it
8+ * under the terms of the GNU General Public License (Version 2) as
9+ * published by the Free Software Foundation.
10+ *
11+ * This program is distributed in the hope it will be useful, but WITHOUT
12+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14+ * for more details.
15+ *
16+ * You should have received a copy of the GNU General Public License along
17+ * with this program; if not, write to the Free Software Foundation, Inc.,
18+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19+ *
20+ * Routines for generic manipulation of the interrupts found on the PowerTV
21+ * platform.
22+ *
23+ * The interrupt controller is located in the South Bridge a PIIX4 device
24+ * with two internal 82C95 interrupt controllers.
25+ */
26+#include <linux/init.h>
27+#include <linux/irq.h>
28+#include <linux/sched.h>
29+#include <linux/slab.h>
30+#include <linux/interrupt.h>
31+#include <linux/kernel_stat.h>
32+#include <linux/kernel.h>
33+#include <linux/random.h>
34+
35+#include <asm/irq_cpu.h>
36+#include <linux/io.h>
37+#include <asm/irq_regs.h>
38+#include <asm/mips-boards/generic.h>
39+
40+#include <asm/mach-powertv/asic_regs.h>
41+
42+static DEFINE_SPINLOCK(asic_irq_lock);
43+
44+static inline int get_int(void)
45+{
46+ unsigned long flags;
47+ int irq;
48+
49+ spin_lock_irqsave(&asic_irq_lock, flags);
50+
51+ irq = (asic_read(int_int_scan) >> 4) - 1;
52+
53+ if (irq == 0 || irq >= NR_IRQS)
54+ irq = -1;
55+
56+ spin_unlock_irqrestore(&asic_irq_lock, flags);
57+
58+ return irq;
59+}

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