Newer asics with 4 SEs are not able to fit the entire bitmask in the original field, use an array instead. v2: keep cu_ao_mask for backward compatibility.
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| @@ -764,6 +764,7 @@ struct drm_amdgpu_info_device { · 763 unmodified lines | |||
| 764 | __u64 max_memory_clock; | 764 | __u64 max_memory_clock; |
| 765 | /* cu information */ | 765 | /* cu information */ |
| 766 | __u32 cu_active_number; | 766 | __u32 cu_active_number; |
| 767 | /* NOTE: cu_ao_mask is INVALID, DON'T use it */ | ||
| 767 | __u32 cu_ao_mask; | 768 | __u32 cu_ao_mask; |
| 768 | __u32 cu_bitmap[4][4]; | 769 | __u32 cu_bitmap[4][4]; |
| 769 | /** Render backend pipe mask. One render backend is CB+DB. */ | 770 | /** Render backend pipe mask. One render backend is CB+DB. */ |
| @@ -818,6 +819,8 @@ struct drm_amdgpu_info_device { · 48 unmodified lines | |||
| 818 | /* max gs wavefront per vgt*/ | 819 | /* max gs wavefront per vgt*/ |
| 819 | __u32 max_gs_waves_per_vgt; | 820 | __u32 max_gs_waves_per_vgt; |
| 820 | __u32 _pad1; | 821 | __u32 _pad1; |
| 822 | /* always on cu bitmap */ | ||
| 823 | __u32 cu_ao_bitmap[4][4]; | ||
| 821 | }; | 824 | }; |
| 822 | 825 | ||
| 823 | struct drm_amdgpu_info_hw_ip { | 826 | struct drm_amdgpu_info_hw_ip { |