Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC-related driver updates from Olof Johansson: "Various driver updates for platforms and a couple of the small driver subsystems we merge through our tree: Among the larger pieces: - Power management improvements for TI am335x and am437x (RTC suspend/wake) - Misc new additions for Amlogic (socinfo updates) - ZynqMP FPGA manager - Nvidia improvements for reset/powergate handling - PMIC wrapper for Mediatek MT8516 - Misc fixes/improvements for ARM SCMI, TEE, NXP i.MX SCU drivers" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (57 commits) soc: aspeed: fix Kconfig soc: add aspeed folder and misc drivers spi: zynqmp: Fix build break soc: imx: Add generic i.MX8 SoC driver MAINTAINERS: Update email for Qualcomm SoC maintainer memory: tegra: Fix a typos for "fdcdwr2" mc client Revert "ARM: tegra: Restore memory arbitration on resume from LP1 on Tegra30+" memory: tegra: Replace readl-writel with mc_readl-mc_writel memory: tegra: Fix integer overflow on tick value calculation memory: tegra: Fix missed registers values latching ARM: tegra: cpuidle: Handle tick broadcasting within cpuidle core on Tegra20/30 optee: allow to work without static shared memory soc/tegra: pmc: Move powergate initialisation to probe soc/tegra: pmc: Remove reset sysfs entries on error soc/tegra: pmc: Fix reset sources and levels soc: amlogic: meson-gx-pwrc-vpu: Add support for G12A soc: amlogic: meson-gx-pwrc-vpu: Fix power on/off register bitmask fpga manager: Adding FPGA Manager support for Xilinx zynqmp dt-bindings: fpga: Add bindings for ZynqMP fpga driver firmware: xilinx: Add fpga API's ...

Linus Torvalds committed 7 years ago

Commit dc413a92 parents e8a1d70 80d0c6471 files · +1717 −434Browse files

Unified · Split

71 files

Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt +25 −0
Documentation/devicetree/bindings/soc/mediatek/pwrap.txt +1 −0
Documentation/xilinx/eemi.txt +2 −2
MAINTAINERS +1 −1
arch/arm/mach-omap2/pm33xx-core.c +75 −1
arch/arm/mach-omap2/sleep43xx.S +3 −0
arch/arm/mach-tegra/Kconfig +1 −0
arch/arm/mach-tegra/cpuidle-tegra20.c +2 −9
arch/arm/mach-tegra/cpuidle-tegra30.c +1 −8
arch/arm/mach-tegra/iomap.h +0 −9
arch/arm/mach-tegra/sleep-tegra30.S +0 −21
drivers/bus/tegra-aconnect.c +46 −20
drivers/clk/zynqmp/clkc.c +2 −2
drivers/firmware/arm_scmi/driver.c +4 −4
drivers/firmware/imx/Makefile +1 −1
drivers/firmware/imx/imx-scu-irq.c +168 −0
drivers/firmware/imx/imx-scu.c +6 −0
drivers/firmware/imx/scu-pd.c +64 −57
drivers/firmware/xilinx/zynqmp-debug.c +4 −14
drivers/firmware/xilinx/zynqmp.c +55 −1
drivers/fpga/Kconfig +9 −0
drivers/fpga/Makefile +1 −0
drivers/fpga/zynqmp-fpga.c +159 −0
drivers/memory/emif.h +4 −0
drivers/memory/tegra/mc.c +20 −14
drivers/memory/tegra/mc.h +1 −1
drivers/memory/tegra/tegra114.c +2 −2
drivers/memory/tegra/tegra124.c +2 −2
drivers/memory/tegra/tegra20.c +14 −14
drivers/memory/tegra/tegra210.c +1 −1
drivers/memory/tegra/tegra30.c +2 −2
drivers/memory/ti-emif-pm.c +3 −0
drivers/memory/ti-emif-sram-pm.S +41 −0
drivers/misc/Kconfig +0 −24
drivers/misc/Makefile +0 −3
drivers/nvmem/zynqmp_nvmem.c +7 −3
drivers/reset/reset-zynqmp.c +4 −4
drivers/rtc/rtc-omap.c +41 −8
drivers/soc/Kconfig +1 −0
drivers/soc/Makefile +1 −0
drivers/soc/amlogic/meson-gx-pwrc-vpu.c +144 −16
drivers/soc/amlogic/meson-gx-socinfo.c +27 −16
drivers/soc/aspeed/Kconfig +31 −0
drivers/soc/aspeed/Makefile +3 −0
drivers/soc/aspeed/aspeed-lpc-ctrl.c +0 −0
drivers/soc/aspeed/aspeed-lpc-snoop.c +0 −0
drivers/soc/aspeed/aspeed-p2a-ctrl.c +0 −0
drivers/soc/imx/Makefile +1 −0
drivers/soc/imx/gpc.c +1 −3
drivers/soc/imx/gpcv2.c +15 −28
drivers/soc/imx/soc-imx8.c +115 −0
drivers/soc/mediatek/mtk-pmic-wrap.c +109 −2
drivers/soc/qcom/cmd-db.c +2 −2
drivers/soc/qcom/qmi_interface.c +2 −5
drivers/soc/qcom/rmtfs_mem.c +21 −0
drivers/soc/qcom/rpmh-rsc.c +1 −1
drivers/soc/renesas/renesas-soc.c +3 −0
drivers/soc/rockchip/grf.c +2 −0
drivers/soc/tegra/pmc.c +134 −37
drivers/soc/ti/Kconfig +3 −2
drivers/soc/ti/pm33xx.c +223 −50
drivers/soc/xilinx/zynqmp_pm_domains.c +10 −8
drivers/soc/xilinx/zynqmp_power.c +6 −4
drivers/spi/spi-zynqmp-gqspi.c +6 −0
drivers/tee/optee/core.c +49 −31
include/linux/firmware/imx/sci.h +5 −0
include/linux/firmware/xlnx-zynqmp.h +13 −1
include/linux/platform_data/pm33xx.h +5 −0
include/linux/reset.h +2 −0
include/linux/rtc/rtc-omap.h +7 −0
include/linux/ti-emif-sram.h +3 −0

Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt+25−0

@@ -0,0 +1,25 @@
	1	+Devicetree bindings for Zynq Ultrascale MPSoC FPGA Manager.
	2	+The ZynqMP SoC uses the PCAP (Processor configuration Port) to configure the
	3	+Programmable Logic (PL). The configuration uses the firmware interface.
	4	+
	5	+Required properties:
	6	+- compatible: should contain "xlnx,zynqmp-pcap-fpga"
	7	+
	8	+Example for full FPGA configuration:
	9	+
	10	+ fpga-region0 {
	11	+ compatible = "fpga-region";
	12	+ fpga-mgr = <&zynqmp_pcap>;
	13	+ #address-cells = <0x1>;
	14	+ #size-cells = <0x1>;
	15	+ };
	16	+
	17	+ firmware {
	18	+ zynqmp_firmware: zynqmp-firmware {
	19	+ compatible = "xlnx,zynqmp-firmware";
	20	+ method = "smc";
	21	+ zynqmp_pcap: pcap {
	22	+ compatible = "xlnx,zynqmp-pcap-fpga";
	23	+ };
	24	+ };
	25	+ };

Documentation/devicetree/bindings/soc/mediatek/pwrap.txt+1−0

@@ -25,6 +25,7 @@ Required properties in pwrap device node. · 24 unmodified lines
25	25	"mediatek,mt8135-pwrap" for MT8135 SoCs
26	26	"mediatek,mt8173-pwrap" for MT8173 SoCs
27	27	"mediatek,mt8183-pwrap" for MT8183 SoCs
	28	+ "mediatek,mt8516-pwrap" for MT8516 SoCs
28	29	- interrupts: IRQ for pwrap in SOC
29	30	- reg-names: Must include the following entries:
30	31	"pwrap": Main registers base

Documentation/xilinx/eemi.txt+2−2

@@ -41,8 +41,8 @@ Example of EEMI ops usage: · 40 unmodified lines
41	41	int ret;
42	42
43	43	eemi_ops = zynqmp_pm_get_eemi_ops();
44		− if (!eemi_ops)
45		− return -ENXIO;
	44	+ if (IS_ERR(eemi_ops))
	45	+ return PTR_ERR(eemi_ops);
46	46
47	47	ret = eemi_ops->query_data(qdata, ret_payload);
48	48

MAINTAINERS+1−1

@@ -2043,7 +2043,7 @@ W: http://www.armlinux.org.uk/ · 2042 unmodified lines
2043	2043	S: Maintained
2044	2044
2045	2045	ARM/QUALCOMM SUPPORT
2046		−M: Andy Gross <andy.gross@linaro.org>
	2046	+M: Andy Gross <agross@kernel.org>
2047	2047	M: David Brown <david.brown@linaro.org>
2048	2048	L: linux-arm-msm@vger.kernel.org
2049	2049	S: Maintained

arch/arm/mach-omap2/pm33xx-core.c+75−1

@@ -10,6 +10,12 @@ · 9 unmodified lines
10	10	#include <asm/suspend.h>
11	11	#include <linux/errno.h>
12	12	#include <linux/platform_data/pm33xx.h>
	13	+#include <linux/clk.h>
	14	+#include <linux/platform_data/gpio-omap.h>
	15	+#include <linux/pinctrl/pinmux.h>
	16	+#include <linux/wkup_m3_ipc.h>
	17	+#include <linux/of.h>
	18	+#include <linux/rtc.h>
13	19
14	20	#include "cm33xx.h"
15	21	#include "common.h"
@@ -38,6 +44,29 @@ static int am43xx_map_scu(void) · 22 unmodified lines
38	44	return 0;
39	45	}
40	46
	47	+static int am33xx_check_off_mode_enable(void)
	48	+{
	49	+ if (enable_off_mode)
	50	+ pr_warn("WARNING: This platform does not support off-mode, entering DeepSleep suspend.\n");
	51	+
	52	+ /* off mode not supported on am335x so return 0 always */
	53	+ return 0;
	54	+}
	55	+
	56	+static int am43xx_check_off_mode_enable(void)
	57	+{
	58	+ /*
	59	+ * Check for am437x-gp-evm which has the right Hardware design to
	60	+ * support this mode reliably.
	61	+ */
	62	+ if (of_machine_is_compatible("ti,am437x-gp-evm") && enable_off_mode)
	63	+ return enable_off_mode;
	64	+ else if (enable_off_mode)
	65	+ pr_warn("WARNING: This platform does not support off-mode, entering DeepSleep suspend.\n");
	66	+
	67	+ return 0;
	68	+}
	69	+
41	70	static int amx3_common_init(void)
42	71	{
43	72	gfx_pwrdm = pwrdm_lookup("gfx_pwrdm");
@@ -141,7 +170,9 @@ static int am43xx_suspend(unsigned int state, int (*fn)(unsigned long), · 97 unmodified lines
141	170	scu_power_mode(scu_base, SCU_PM_POWEROFF);
142	171	ret = cpu_suspend(args, fn);
143	172	scu_power_mode(scu_base, SCU_PM_NORMAL);
144		− amx3_post_suspend_common();
	173	+
	174	+ if (!am43xx_check_off_mode_enable())
	175	+ amx3_post_suspend_common();
145	176
146	177	return ret;
147	178	}
@@ -163,10 +194,48 @@ void __iomem *am43xx_get_rtc_base_addr(void) · 15 unmodified lines
163	194	return omap_hwmod_get_mpu_rt_va(rtc_oh);
164	195	}
165	196
	197	+static void am43xx_save_context(void)
	198	+{
	199	+}
	200	+
	201	+static void am33xx_save_context(void)
	202	+{
	203	+ omap_intc_save_context();
	204	+}
	205	+
	206	+static void am33xx_restore_context(void)
	207	+{
	208	+ omap_intc_restore_context();
	209	+}
	210	+
	211	+static void am43xx_restore_context(void)
	212	+{
	213	+ /*
	214	+ * HACK: restore dpll_per_clkdcoldo register contents, to avoid
	215	+ * breaking suspend-resume
	216	+ */
	217	+ writel_relaxed(0x0, AM33XX_L4_WK_IO_ADDRESS(0x44df2e14));
	218	+}
	219	+
	220	+static void am43xx_prepare_rtc_suspend(void)
	221	+{
	222	+ omap_hwmod_enable(rtc_oh);
	223	+}
	224	+
	225	+static void am43xx_prepare_rtc_resume(void)
	226	+{
	227	+ omap_hwmod_idle(rtc_oh);
	228	+}
	229	+
166	230	static struct am33xx_pm_platform_data am33xx_ops = {
167	231	.init = am33xx_suspend_init,
168	232	.soc_suspend = am33xx_suspend,
169	233	.get_sram_addrs = amx3_get_sram_addrs,
	234	+ .save_context = am33xx_save_context,
	235	+ .restore_context = am33xx_restore_context,
	236	+ .prepare_rtc_suspend = am43xx_prepare_rtc_suspend,
	237	+ .prepare_rtc_resume = am43xx_prepare_rtc_resume,
	238	+ .check_off_mode_enable = am33xx_check_off_mode_enable,
170	239	.get_rtc_base_addr = am43xx_get_rtc_base_addr,
171	240	};
172	241
@@ -174,6 +243,11 @@ static struct am33xx_pm_platform_data am43xx_ops = { · 1 unmodified line
174	243	.init = am43xx_suspend_init,
175	244	.soc_suspend = am43xx_suspend,
176	245	.get_sram_addrs = amx3_get_sram_addrs,
	246	+ .save_context = am43xx_save_context,
	247	+ .restore_context = am43xx_restore_context,
	248	+ .prepare_rtc_suspend = am43xx_prepare_rtc_suspend,
	249	+ .prepare_rtc_resume = am43xx_prepare_rtc_resume,
	250	+ .check_off_mode_enable = am43xx_check_off_mode_enable,
177	251	.get_rtc_base_addr = am43xx_get_rtc_base_addr,
178	252	};
179	253

arch/arm/mach-omap2/sleep43xx.S+3−0

@@ -368,6 +368,9 @@ wait_emif_enable1: · 367 unmodified lines
368	368	mov r1, #AM43XX_EMIF_POWEROFF_DISABLE
369	369	str r1, [r2, #0x0]
370	370
	371	+ ldr r1, [r9, #EMIF_PM_RUN_HW_LEVELING]
	372	+ blx r1
	373	+
371	374	#ifdef CONFIG_CACHE_L2X0
372	375	ldr r2, l2_cache_base
373	376	ldr r0, [r2, #L2X0_CTRL]

arch/arm/mach-tegra/Kconfig+1−0

@@ -10,6 +10,7 @@ menuconfig ARCH_TEGRA · 9 unmodified lines
10	10	select HAVE_ARM_SCU if SMP
11	11	select HAVE_ARM_TWD if SMP
12	12	select PINCTRL
	13	+ select PM
13	14	select PM_OPP
14	15	select RESET_CONTROLLER
15	16	select SOC_BUS

arch/arm/mach-tegra/cpuidle-tegra20.c+2−9

@@ -61,7 +61,8 @@ static struct cpuidle_driver tegra_idle_driver = { · 60 unmodified lines
61	61	.exit_latency = 5000,
62	62	.target_residency = 10000,
63	63	.power_usage = 0,
64		− .flags = CPUIDLE_FLAG_COUPLED,
	64	+ .flags = CPUIDLE_FLAG_COUPLED \|
	65	+ CPUIDLE_FLAG_TIMER_STOP,
65	66	.name = "powered-down",
66	67	.desc = "CPU power gated",
67	68	},
@@ -136,12 +137,8 @@ static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev, · 68 unmodified lines
136	137	if (tegra20_reset_cpu_1() \|\| !tegra_cpu_rail_off_ready())
137	138	return false;
138	139
139		− tick_broadcast_enter();
140		−
141	140	tegra_idle_lp2_last();
142	141
143		− tick_broadcast_exit();
144		−
145	142	if (cpu_online(1))
146	143	tegra20_wake_cpu1_from_reset();
147	144
@@ -153,14 +150,10 @@ static bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev, · 5 unmodified lines
153	150	struct cpuidle_driver *drv,
154	151	int index)
155	152	{
156		− tick_broadcast_enter();
157		−
158	153	cpu_suspend(0, tegra20_sleep_cpu_secondary_finish);
159	154
160	155	tegra20_cpu_clear_resettable();
161	156
162		− tick_broadcast_exit();
163		−
164	157	return true;
165	158	}
166	159	#else

arch/arm/mach-tegra/cpuidle-tegra30.c+1−8

@@ -56,6 +56,7 @@ static struct cpuidle_driver tegra_idle_driver = { · 55 unmodified lines
56	56	.exit_latency = 2000,
57	57	.target_residency = 2200,
58	58	.power_usage = 0,
	59	+ .flags = CPUIDLE_FLAG_TIMER_STOP,
59	60	.name = "powered-down",
60	61	.desc = "CPU power gated",
61	62	},
@@ -76,12 +77,8 @@ static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev, · 14 unmodified lines
76	77	return false;
77	78	}
78	79
79		− tick_broadcast_enter();
80		−
81	80	tegra_idle_lp2_last();
82	81
83		− tick_broadcast_exit();
84		−
85	82	return true;
86	83	}
87	84
@@ -90,14 +87,10 @@ static bool tegra30_cpu_core_power_down(struct cpuidle_device *dev, · 2 unmodified lines
90	87	struct cpuidle_driver *drv,
91	88	int index)
92	89	{
93		− tick_broadcast_enter();
94		−
95	90	smp_wmb();
96	91
97	92	cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
98	93
99		− tick_broadcast_exit();
100		−
101	94	return true;
102	95	}
103	96	#else

arch/arm/mach-tegra/iomap.h+0−9

@@ -79,24 +79,15 @@ · 78 unmodified lines
79	79	#define TEGRA_PMC_BASE 0x7000E400
80	80	#define TEGRA_PMC_SIZE SZ_256
81	81
82		−#define TEGRA_MC_BASE 0x7000F000
83		−#define TEGRA_MC_SIZE SZ_1K
84		−
85	82	#define TEGRA_EMC_BASE 0x7000F400
86	83	#define TEGRA_EMC_SIZE SZ_1K
87	84
88		−#define TEGRA114_MC_BASE 0x70019000
89		−#define TEGRA114_MC_SIZE SZ_4K
90		−
91	85	#define TEGRA_EMC0_BASE 0x7001A000
92	86	#define TEGRA_EMC0_SIZE SZ_2K
93	87
94	88	#define TEGRA_EMC1_BASE 0x7001A800
95	89	#define TEGRA_EMC1_SIZE SZ_2K
96	90
97		−#define TEGRA124_MC_BASE 0x70019000
98		−#define TEGRA124_MC_SIZE SZ_4K
99		−
100	91	#define TEGRA124_EMC_BASE 0x7001B000
101	92	#define TEGRA124_EMC_SIZE SZ_2K
102	93

arch/arm/mach-tegra/sleep-tegra30.S+0−21

@@ -44,8 +44,6 @@ · 43 unmodified lines
44	44	#define EMC_XM2VTTGENPADCTRL 0x310
45	45	#define EMC_XM2VTTGENPADCTRL2 0x314
46	46
47		−#define MC_EMEM_ARB_CFG 0x90
48		−
49	47	#define PMC_CTRL 0x0
50	48	#define PMC_CTRL_SIDE_EFFECT_LP0 (1 << 14) /* enter LP0 when CPU pwr gated */
51	49
@@ -420,22 +418,6 @@ _pll_m_c_x_done: · 368 unmodified lines
420	418	movweq r0, #:lower16:TEGRA124_EMC_BASE
421	419	movteq r0, #:upper16:TEGRA124_EMC_BASE
422	420
423		− cmp r10, #TEGRA30
424		− moveq r2, #0x20
425		− movweq r4, #:lower16:TEGRA_MC_BASE
426		− movteq r4, #:upper16:TEGRA_MC_BASE
427		− cmp r10, #TEGRA114
428		− moveq r2, #0x34
429		− movweq r4, #:lower16:TEGRA114_MC_BASE
430		− movteq r4, #:upper16:TEGRA114_MC_BASE
431		− cmp r10, #TEGRA124
432		− moveq r2, #0x20
433		− movweq r4, #:lower16:TEGRA124_MC_BASE
434		− movteq r4, #:upper16:TEGRA124_MC_BASE
435		−
436		− ldr r1, [r5, r2] @ restore MC_EMEM_ARB_CFG
437		− str r1, [r4, #MC_EMEM_ARB_CFG]
438		−
439	421	exit_self_refresh:
440	422	ldr r1, [r5, #0xC] @ restore EMC_XM2VTTGENPADCTRL
441	423	str r1, [r0, #EMC_XM2VTTGENPADCTRL]
@@ -564,7 +546,6 @@ tegra30_sdram_pad_address: · 122 unmodified lines
564	546	.word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14
565	547	.word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18
566	548	.word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c
567		− .word TEGRA_MC_BASE + MC_EMEM_ARB_CFG @0x20
568	549	tegra30_sdram_pad_address_end:
569	550
570	551	tegra114_sdram_pad_address:
@@ -581,7 +562,6 @@ tegra114_sdram_pad_address: · 10 unmodified lines
581	562	.word TEGRA_EMC1_BASE + EMC_AUTO_CAL_INTERVAL @0x28
582	563	.word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL @0x2c
583	564	.word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2 @0x30
584		− .word TEGRA114_MC_BASE + MC_EMEM_ARB_CFG @0x34
585	565	tegra114_sdram_pad_adress_end:
586	566
587	567	tegra124_sdram_pad_address:
@@ -593,7 +573,6 @@ tegra124_sdram_pad_address: · 5 unmodified lines
593	573	.word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14
594	574	.word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18
595	575	.word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c
596		− .word TEGRA124_MC_BASE + MC_EMEM_ARB_CFG @0x20
597	576	tegra124_sdram_pad_address_end:
598	577
599	578	tegra30_sdram_pad_size:

drivers/bus/tegra-aconnect.c+46−20

@@ -12,28 +12,38 @@ · 11 unmodified lines
12	12	#include <linux/module.h>
13	13	#include <linux/of_platform.h>
14	14	#include <linux/platform_device.h>
15		−#include <linux/pm_clock.h>
16	15	#include <linux/pm_runtime.h>
17	16
	17	+struct tegra_aconnect {
	18	+ struct clk *ape_clk;
	19	+ struct clk *apb2ape_clk;
	20	+};
	21	+
18	22	static int tegra_aconnect_probe(struct platform_device *pdev)
19	23	{
20		− int ret;
	24	+ struct tegra_aconnect *aconnect;
21	25
22	26	if (!pdev->dev.of_node)
23	27	return -EINVAL;
24	28
25		− ret = pm_clk_create(&pdev->dev);
26		− if (ret)
27		− return ret;
	29	+ aconnect = devm_kzalloc(&pdev->dev, sizeof(struct tegra_aconnect),
	30	+ GFP_KERNEL);
	31	+ if (!aconnect)
	32	+ return -ENOMEM;
28	33
29		− ret = of_pm_clk_add_clk(&pdev->dev, "ape");
30		− if (ret)
31		− goto clk_destroy;
	34	+ aconnect->ape_clk = devm_clk_get(&pdev->dev, "ape");
	35	+ if (IS_ERR(aconnect->ape_clk)) {
	36	+ dev_err(&pdev->dev, "Can't retrieve ape clock\n");
	37	+ return PTR_ERR(aconnect->ape_clk);
	38	+ }
32	39
33		− ret = of_pm_clk_add_clk(&pdev->dev, "apb2ape");
34		− if (ret)
35		− goto clk_destroy;
	40	+ aconnect->apb2ape_clk = devm_clk_get(&pdev->dev, "apb2ape");
	41	+ if (IS_ERR(aconnect->apb2ape_clk)) {
	42	+ dev_err(&pdev->dev, "Can't retrieve apb2ape clock\n");
	43	+ return PTR_ERR(aconnect->apb2ape_clk);
	44	+ }
36	45
	46	+ dev_set_drvdata(&pdev->dev, aconnect);
37	47	pm_runtime_enable(&pdev->dev);
38	48
39	49	of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
@@ -41,35 +51,51 @@ static int tegra_aconnect_probe(struct platform_device *pdev) · 1 unmodified line
41	51	dev_info(&pdev->dev, "Tegra ACONNECT bus registered\n");
42	52
43	53	return 0;
44		−
45		−clk_destroy:
46		− pm_clk_destroy(&pdev->dev);
47		−
48		− return ret;
49	54	}
50	55
51	56	static int tegra_aconnect_remove(struct platform_device *pdev)
52	57	{
53	58	pm_runtime_disable(&pdev->dev);
54	59
55		− pm_clk_destroy(&pdev->dev);
56		−
57	60	return 0;
58	61	}
59	62
60	63	static int tegra_aconnect_runtime_resume(struct device *dev)
61	64	{
62		− return pm_clk_resume(dev);
	65	+ struct tegra_aconnect *aconnect = dev_get_drvdata(dev);
	66	+ int ret;
	67	+
	68	+ ret = clk_prepare_enable(aconnect->ape_clk);
	69	+ if (ret) {
	70	+ dev_err(dev, "ape clk_enable failed: %d\n", ret);
	71	+ return ret;
	72	+ }
	73	+
	74	+ ret = clk_prepare_enable(aconnect->apb2ape_clk);
	75	+ if (ret) {
	76	+ clk_disable_unprepare(aconnect->ape_clk);
	77	+ dev_err(dev, "apb2ape clk_enable failed: %d\n", ret);
	78	+ return ret;
	79	+ }
	80	+
	81	+ return 0;
63	82	}
64	83
65	84	static int tegra_aconnect_runtime_suspend(struct device *dev)
66	85	{
67		− return pm_clk_suspend(dev);
	86	+ struct tegra_aconnect *aconnect = dev_get_drvdata(dev);
	87	+
	88	+ clk_disable_unprepare(aconnect->ape_clk);
	89	+ clk_disable_unprepare(aconnect->apb2ape_clk);
	90	+
	91	+ return 0;
68	92	}
69	93
70	94	static const struct dev_pm_ops tegra_aconnect_pm_ops = {
71	95	SET_RUNTIME_PM_OPS(tegra_aconnect_runtime_suspend,
72	96	tegra_aconnect_runtime_resume, NULL)
	97	+ SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
	98	+ pm_runtime_force_resume)
73	99	};
74	100
75	101	static const struct of_device_id tegra_aconnect_of_match[] = {

drivers/clk/zynqmp/clkc.c+2−2

@@ -739,8 +739,8 @@ static int zynqmp_clock_probe(struct platform_device *pdev) · 738 unmodified lines
739	739	struct device *dev = &pdev->dev;
740	740
741	741	eemi_ops = zynqmp_pm_get_eemi_ops();
742		− if (!eemi_ops)
743		− return -ENXIO;
	742	+ if (IS_ERR(eemi_ops))
	743	+ return PTR_ERR(eemi_ops);
744	744
745	745	ret = zynqmp_clk_setup(dev->of_node);
746	746

drivers/firmware/arm_scmi/driver.c+4−4

@@ -654,9 +654,7 @@ static int scmi_xfer_info_init(struct scmi_info *sinfo) · 653 unmodified lines
654	654
655	655	static int scmi_mailbox_check(struct device_node *np)
656	656	{
657		− struct of_phandle_args arg;
658		−
659		− return of_parse_phandle_with_args(np, "mboxes", "#mbox-cells", 0, &arg);
	657	+ return of_parse_phandle_with_args(np, "mboxes", "#mbox-cells", 0, NULL);
660	658	}
661	659
662	660	static int scmi_mbox_free_channel(int id, void p, void data)
@@ -798,7 +796,9 @@ static int scmi_probe(struct platform_device *pdev) · 135 unmodified lines
798	796	return -EINVAL;
799	797	}
800	798
801		− desc = of_match_device(scmi_of_match, dev)->data;
	799	+ desc = of_device_get_match_data(dev);
	800	+ if (!desc)
	801	+ return -EINVAL;
802	802
803	803	info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
804	804	if (!info)

drivers/firmware/imx/Makefile+1−1

@@ -1,3 +1,3 @@
1	1	# SPDX-License-Identifier: GPL-2.0
2		−obj-$(CONFIG_IMX_SCU) += imx-scu.o misc.o
	2	+obj-$(CONFIG_IMX_SCU) += imx-scu.o misc.o imx-scu-irq.o
3	3	obj-$(CONFIG_IMX_SCU_PD) += scu-pd.o

drivers/firmware/imx/imx-scu-irq.c+168−0

@@ -0,0 +1,168 @@
	1	+// SPDX-License-Identifier: GPL-2.0+
	2	+/*
	3	+ * Copyright 2019 NXP
	4	+ *
	5	+ * Implementation of the SCU IRQ functions using MU.
	6	+ *
	7	+ */
	8	+
	9	+#include <dt-bindings/firmware/imx/rsrc.h>
	10	+#include <linux/firmware/imx/ipc.h>
	11	+#include <linux/mailbox_client.h>
	12	+
	13	+#define IMX_SC_IRQ_FUNC_ENABLE 1
	14	+#define IMX_SC_IRQ_FUNC_STATUS 2
	15	+#define IMX_SC_IRQ_NUM_GROUP 4
	16	+
	17	+static u32 mu_resource_id;
	18	+
	19	+struct imx_sc_msg_irq_get_status {
	20	+ struct imx_sc_rpc_msg hdr;
	21	+ union {
	22	+ struct {
	23	+ u16 resource;
	24	+ u8 group;
	25	+ u8 reserved;
	26	+ } __packed req;
	27	+ struct {
	28	+ u32 status;
	29	+ } resp;
	30	+ } data;
	31	+};
	32	+
	33	+struct imx_sc_msg_irq_enable {
	34	+ struct imx_sc_rpc_msg hdr;
	35	+ u32 mask;
	36	+ u16 resource;
	37	+ u8 group;
	38	+ u8 enable;
	39	+} __packed;
	40	+
	41	+static struct imx_sc_ipc *imx_sc_irq_ipc_handle;
	42	+static struct work_struct imx_sc_irq_work;
	43	+static ATOMIC_NOTIFIER_HEAD(imx_scu_irq_notifier_chain);
	44	+
	45	+int imx_scu_irq_register_notifier(struct notifier_block *nb)
	46	+{
	47	+ return atomic_notifier_chain_register(
	48	+ &imx_scu_irq_notifier_chain, nb);
	49	+}
	50	+EXPORT_SYMBOL(imx_scu_irq_register_notifier);
	51	+
	52	+int imx_scu_irq_unregister_notifier(struct notifier_block *nb)
	53	+{
	54	+ return atomic_notifier_chain_unregister(
	55	+ &imx_scu_irq_notifier_chain, nb);
	56	+}
	57	+EXPORT_SYMBOL(imx_scu_irq_unregister_notifier);
	58	+
	59	+static int imx_scu_irq_notifier_call_chain(unsigned long status, u8 *group)
	60	+{
	61	+ return atomic_notifier_call_chain(&imx_scu_irq_notifier_chain,
	62	+ status, (void *)group);
	63	+}
	64	+
	65	+static void imx_scu_irq_work_handler(struct work_struct *work)
	66	+{
	67	+ struct imx_sc_msg_irq_get_status msg;
	68	+ struct imx_sc_rpc_msg *hdr = &msg.hdr;
	69	+ u32 irq_status;
	70	+ int ret;
	71	+ u8 i;
	72	+
	73	+ for (i = 0; i < IMX_SC_IRQ_NUM_GROUP; i++) {
	74	+ hdr->ver = IMX_SC_RPC_VERSION;
	75	+ hdr->svc = IMX_SC_RPC_SVC_IRQ;
	76	+ hdr->func = IMX_SC_IRQ_FUNC_STATUS;
	77	+ hdr->size = 2;
	78	+
	79	+ msg.data.req.resource = mu_resource_id;
	80	+ msg.data.req.group = i;
	81	+
	82	+ ret = imx_scu_call_rpc(imx_sc_irq_ipc_handle, &msg, true);
	83	+ if (ret) {
	84	+ pr_err("get irq group %d status failed, ret %d\n",
	85	+ i, ret);
	86	+ return;
	87	+ }
	88	+
	89	+ irq_status = msg.data.resp.status;
	90	+ if (!irq_status)
	91	+ continue;
	92	+
	93	+ imx_scu_irq_notifier_call_chain(irq_status, &i);
	94	+ }
	95	+}
	96	+
	97	+int imx_scu_irq_group_enable(u8 group, u32 mask, u8 enable)
	98	+{
	99	+ struct imx_sc_msg_irq_enable msg;
	100	+ struct imx_sc_rpc_msg *hdr = &msg.hdr;
	101	+ int ret;
	102	+
	103	+ hdr->ver = IMX_SC_RPC_VERSION;
	104	+ hdr->svc = IMX_SC_RPC_SVC_IRQ;
	105	+ hdr->func = IMX_SC_IRQ_FUNC_ENABLE;
	106	+ hdr->size = 3;
	107	+
	108	+ msg.resource = mu_resource_id;
	109	+ msg.group = group;
	110	+ msg.mask = mask;
	111	+ msg.enable = enable;
	112	+
	113	+ ret = imx_scu_call_rpc(imx_sc_irq_ipc_handle, &msg, true);
	114	+ if (ret)
	115	+ pr_err("enable irq failed, group %d, mask %d, ret %d\n",
	116	+ group, mask, ret);
	117	+
	118	+ return ret;
	119	+}
	120	+EXPORT_SYMBOL(imx_scu_irq_group_enable);
	121	+
	122	+static void imx_scu_irq_callback(struct mbox_client c, void msg)
	123	+{
	124	+ schedule_work(&imx_sc_irq_work);
	125	+}
	126	+
	127	+int imx_scu_enable_general_irq_channel(struct device *dev)
	128	+{
	129	+ struct of_phandle_args spec;
	130	+ struct mbox_client *cl;
	131	+ struct mbox_chan *ch;
	132	+ int ret = 0, i = 0;
	133	+
	134	+ ret = imx_scu_get_handle(&imx_sc_irq_ipc_handle);
	135	+ if (ret)
	136	+ return ret;
	137	+
	138	+ cl = devm_kzalloc(dev, sizeof(*cl), GFP_KERNEL);
	139	+ if (!cl)
	140	+ return -ENOMEM;
	141	+
	142	+ cl->dev = dev;
	143	+ cl->rx_callback = imx_scu_irq_callback;
	144	+
	145	+ /* SCU general IRQ uses general interrupt channel 3 */
	146	+ ch = mbox_request_channel_byname(cl, "gip3");
	147	+ if (IS_ERR(ch)) {
	148	+ ret = PTR_ERR(ch);
	149	+ dev_err(dev, "failed to request mbox chan gip3, ret %d\n", ret);
	150	+ devm_kfree(dev, cl);
	151	+ return ret;
	152	+ }
	153	+
	154	+ INIT_WORK(&imx_sc_irq_work, imx_scu_irq_work_handler);
	155	+
	156	+ if (!of_parse_phandle_with_args(dev->of_node, "mboxes",
	157	+ "#mbox-cells", 0, &spec))
	158	+ i = of_alias_get_id(spec.np, "mu");
	159	+
	160	+ /* use mu1 as general mu irq channel if failed */
	161	+ if (i < 0)
	162	+ i = 1;
	163	+
	164	+ mu_resource_id = IMX_SC_R_MU_0A + i;
	165	+
	166	+ return ret;
	167	+}
	168	+EXPORT_SYMBOL(imx_scu_enable_general_irq_channel);

drivers/firmware/imx/imx-scu.c+6−0

@@ -10,6 +10,7 @@ · 9 unmodified lines
10	10	#include <linux/err.h>
11	11	#include <linux/firmware/imx/types.h>
12	12	#include <linux/firmware/imx/ipc.h>
	13	+#include <linux/firmware/imx/sci.h>
13	14	#include <linux/interrupt.h>
14	15	#include <linux/irq.h>
15	16	#include <linux/kernel.h>
@@ -246,6 +247,11 @@ static int imx_scu_probe(struct platform_device *pdev) · 230 unmodified lines
246	247
247	248	imx_sc_ipc_handle = sc_ipc;
248	249
	250	+ ret = imx_scu_enable_general_irq_channel(dev);
	251	+ if (ret)
	252	+ dev_warn(dev,
	253	+ "failed to enable general irq channel: %d\n", ret);
	254	+
249	255	dev_info(dev, "NXP i.MX SCU Initialized\n");
250	256
251	257	return devm_of_platform_populate(dev);

drivers/firmware/imx/scu-pd.c+64−57

@@ -74,7 +74,10 @@ struct imx_sc_pd_range { · 73 unmodified lines
74	74	char *name;
75	75	u32 rsrc;
76	76	u8 num;
	77	+
	78	+ /* add domain index */
77	79	bool postfix;
	80	+ u8 start_from;
78	81	};
79	82
80	83	struct imx_sc_pd_soc {
@@ -84,71 +87,75 @@ struct imx_sc_pd_soc { · 3 unmodified lines
84	87
85	88	static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = {
86	89	/* LSIO SS */
87		− { "lsio-pwm", IMX_SC_R_PWM_0, 8, 1 },
88		− { "lsio-gpio", IMX_SC_R_GPIO_0, 8, 1 },
89		− { "lsio-gpt", IMX_SC_R_GPT_0, 5, 1 },
90		− { "lsio-kpp", IMX_SC_R_KPP, 1, 0 },
91		− { "lsio-fspi", IMX_SC_R_FSPI_0, 2, 1 },
92		− { "lsio-mu", IMX_SC_R_MU_0A, 14, 1 },
	90	+ { "pwm", IMX_SC_R_PWM_0, 8, true, 0 },
	91	+ { "gpio", IMX_SC_R_GPIO_0, 8, true, 0 },
	92	+ { "gpt", IMX_SC_R_GPT_0, 5, true, 0 },
	93	+ { "kpp", IMX_SC_R_KPP, 1, false, 0 },
	94	+ { "fspi", IMX_SC_R_FSPI_0, 2, true, 0 },
	95	+ { "mu", IMX_SC_R_MU_0A, 14, true, 0 },
93	96
94	97	/* CONN SS */
95		− { "con-usb", IMX_SC_R_USB_0, 2, 1 },
96		− { "con-usb0phy", IMX_SC_R_USB_0_PHY, 1, 0 },
97		− { "con-usb2", IMX_SC_R_USB_2, 1, 0 },
98		− { "con-usb2phy", IMX_SC_R_USB_2_PHY, 1, 0 },
99		− { "con-sdhc", IMX_SC_R_SDHC_0, 3, 1 },
100		− { "con-enet", IMX_SC_R_ENET_0, 2, 1 },
101		− { "con-nand", IMX_SC_R_NAND, 1, 0 },
102		− { "con-mlb", IMX_SC_R_MLB_0, 1, 1 },
103		−
104		− /* Audio DMA SS */
105		− { "adma-audio-pll0", IMX_SC_R_AUDIO_PLL_0, 1, 0 },
106		− { "adma-audio-pll1", IMX_SC_R_AUDIO_PLL_1, 1, 0 },
107		− { "adma-audio-clk-0", IMX_SC_R_AUDIO_CLK_0, 1, 0 },
108		− { "adma-dma0-ch", IMX_SC_R_DMA_0_CH0, 16, 1 },
109		− { "adma-dma1-ch", IMX_SC_R_DMA_1_CH0, 16, 1 },
110		− { "adma-dma2-ch", IMX_SC_R_DMA_2_CH0, 5, 1 },
111		− { "adma-asrc0", IMX_SC_R_ASRC_0, 1, 0 },
112		− { "adma-asrc1", IMX_SC_R_ASRC_1, 1, 0 },
113		− { "adma-esai0", IMX_SC_R_ESAI_0, 1, 0 },
114		− { "adma-spdif0", IMX_SC_R_SPDIF_0, 1, 0 },
115		− { "adma-sai", IMX_SC_R_SAI_0, 3, 1 },
116		− { "adma-amix", IMX_SC_R_AMIX, 1, 0 },
117		− { "adma-mqs0", IMX_SC_R_MQS_0, 1, 0 },
118		− { "adma-dsp", IMX_SC_R_DSP, 1, 0 },
119		− { "adma-dsp-ram", IMX_SC_R_DSP_RAM, 1, 0 },
120		− { "adma-can", IMX_SC_R_CAN_0, 3, 1 },
121		− { "adma-ftm", IMX_SC_R_FTM_0, 2, 1 },
122		− { "adma-lpi2c", IMX_SC_R_I2C_0, 4, 1 },
123		− { "adma-adc", IMX_SC_R_ADC_0, 1, 1 },
124		− { "adma-lcd", IMX_SC_R_LCD_0, 1, 1 },
125		− { "adma-lcd0-pwm", IMX_SC_R_LCD_0_PWM_0, 1, 1 },
126		− { "adma-lpuart", IMX_SC_R_UART_0, 4, 1 },
127		− { "adma-lpspi", IMX_SC_R_SPI_0, 4, 1 },
128		−
129		− /* VPU SS */
130		− { "vpu", IMX_SC_R_VPU, 1, 0 },
131		− { "vpu-pid", IMX_SC_R_VPU_PID0, 8, 1 },
132		− { "vpu-dec0", IMX_SC_R_VPU_DEC_0, 1, 0 },
133		− { "vpu-enc0", IMX_SC_R_VPU_ENC_0, 1, 0 },
	98	+ { "usb", IMX_SC_R_USB_0, 2, true, 0 },
	99	+ { "usb0phy", IMX_SC_R_USB_0_PHY, 1, false, 0 },
	100	+ { "usb2", IMX_SC_R_USB_2, 1, false, 0 },
	101	+ { "usb2phy", IMX_SC_R_USB_2_PHY, 1, false, 0 },
	102	+ { "sdhc", IMX_SC_R_SDHC_0, 3, true, 0 },
	103	+ { "enet", IMX_SC_R_ENET_0, 2, true, 0 },
	104	+ { "nand", IMX_SC_R_NAND, 1, false, 0 },
	105	+ { "mlb", IMX_SC_R_MLB_0, 1, true, 0 },
	106	+
	107	+ /* AUDIO SS */
	108	+ { "audio-pll0", IMX_SC_R_AUDIO_PLL_0, 1, false, 0 },
	109	+ { "audio-pll1", IMX_SC_R_AUDIO_PLL_1, 1, false, 0 },
	110	+ { "audio-clk-0", IMX_SC_R_AUDIO_CLK_0, 1, false, 0 },
	111	+ { "dma0-ch", IMX_SC_R_DMA_0_CH0, 16, true, 0 },
	112	+ { "dma1-ch", IMX_SC_R_DMA_1_CH0, 16, true, 0 },
	113	+ { "dma2-ch", IMX_SC_R_DMA_2_CH0, 5, true, 0 },
	114	+ { "asrc0", IMX_SC_R_ASRC_0, 1, false, 0 },
	115	+ { "asrc1", IMX_SC_R_ASRC_1, 1, false, 0 },
	116	+ { "esai0", IMX_SC_R_ESAI_0, 1, false, 0 },
	117	+ { "spdif0", IMX_SC_R_SPDIF_0, 1, false, 0 },
	118	+ { "sai", IMX_SC_R_SAI_0, 3, true, 0 },
	119	+ { "amix", IMX_SC_R_AMIX, 1, false, 0 },
	120	+ { "mqs0", IMX_SC_R_MQS_0, 1, false, 0 },
	121	+ { "dsp", IMX_SC_R_DSP, 1, false, 0 },
	122	+ { "dsp-ram", IMX_SC_R_DSP_RAM, 1, false, 0 },
	123	+
	124	+ /* DMA SS */
	125	+ { "can", IMX_SC_R_CAN_0, 3, true, 0 },
	126	+ { "ftm", IMX_SC_R_FTM_0, 2, true, 0 },
	127	+ { "lpi2c", IMX_SC_R_I2C_0, 4, true, 0 },
	128	+ { "adc", IMX_SC_R_ADC_0, 1, true, 0 },
	129	+ { "lcd", IMX_SC_R_LCD_0, 1, true, 0 },
	130	+ { "lcd0-pwm", IMX_SC_R_LCD_0_PWM_0, 1, true, 0 },
	131	+ { "lpuart", IMX_SC_R_UART_0, 4, true, 0 },
	132	+ { "lpspi", IMX_SC_R_SPI_0, 4, true, 0 },
	133	+
	134	+ /* VPU SS */
	135	+ { "vpu", IMX_SC_R_VPU, 1, false, 0 },
	136	+ { "vpu-pid", IMX_SC_R_VPU_PID0, 8, true, 0 },
	137	+ { "vpu-dec0", IMX_SC_R_VPU_DEC_0, 1, false, 0 },
	138	+ { "vpu-enc0", IMX_SC_R_VPU_ENC_0, 1, false, 0 },
134	139
135	140	/* GPU SS */
136		− { "gpu0-pid", IMX_SC_R_GPU_0_PID0, 4, 1 },
	141	+ { "gpu0-pid", IMX_SC_R_GPU_0_PID0, 4, true, 0 },
137	142
138	143	/* HSIO SS */
139		− { "hsio-pcie-b", IMX_SC_R_PCIE_B, 1, 0 },
140		− { "hsio-serdes-1", IMX_SC_R_SERDES_1, 1, 0 },
141		− { "hsio-gpio", IMX_SC_R_HSIO_GPIO, 1, 0 },
	144	+ { "pcie-b", IMX_SC_R_PCIE_B, 1, false, 0 },
	145	+ { "serdes-1", IMX_SC_R_SERDES_1, 1, false, 0 },
	146	+ { "hsio-gpio", IMX_SC_R_HSIO_GPIO, 1, false, 0 },
	147	+
	148	+ /* MIPI SS */
	149	+ { "mipi0", IMX_SC_R_MIPI_0, 1, false, 0 },
	150	+ { "mipi0-pwm0", IMX_SC_R_MIPI_0_PWM_0, 1, false, 0 },
	151	+ { "mipi0-i2c", IMX_SC_R_MIPI_0_I2C_0, 2, true, 0 },
142	152
143		− /* MIPI/LVDS SS */
144		− { "mipi0", IMX_SC_R_MIPI_0, 1, 0 },
145		− { "mipi0-pwm0", IMX_SC_R_MIPI_0_PWM_0, 1, 0 },
146		− { "mipi0-i2c", IMX_SC_R_MIPI_0_I2C_0, 2, 1 },
147		− { "lvds0", IMX_SC_R_LVDS_0, 1, 0 },
	153	+ /* LVDS SS */
	154	+ { "lvds0", IMX_SC_R_LVDS_0, 1, false, 0 },
148	155
149	156	/* DC SS */
150		− { "dc0", IMX_SC_R_DC_0, 1, 0 },
151		− { "dc0-pll", IMX_SC_R_DC_0_PLL_0, 2, 1 },
	157	+ { "dc0", IMX_SC_R_DC_0, 1, false, 0 },
	158	+ { "dc0-pll", IMX_SC_R_DC_0_PLL_0, 2, true, 0 },
152	159	};
153	160
154	161	static const struct imx_sc_pd_soc imx8qxp_scu_pd = {
@@ -236,7 +243,7 @@ imx_scu_add_pm_domain(struct device *dev, int idx, · 81 unmodified lines
236	243
237	244	if (pd_ranges->postfix)
238	245	snprintf(sc_pd->name, sizeof(sc_pd->name),
239		− "%s%i", pd_ranges->name, idx);
	246	+ "%s%i", pd_ranges->name, pd_ranges->start_from + idx);
240	247	else
241	248	snprintf(sc_pd->name, sizeof(sc_pd->name),
242	249	"%s", pd_ranges->name);

drivers/firmware/xilinx/zynqmp-debug.c+4−14

@@ -90,9 +90,6 @@ static int process_api_request(u32 pm_id, u64 pm_api_arg, u32 pm_api_ret) · 89 unmodified lines
90	90	int ret;
91	91	struct zynqmp_pm_query_data qdata = {0};
92	92
93		− if (!eemi_ops)
94		− return -ENXIO;
95		−
96	93	switch (pm_id) {
97	94	case PM_GET_API_VERSION:
98	95	ret = eemi_ops->get_api_version(&pm_api_version);
@@ -163,21 +160,14 @@ static ssize_t zynqmp_pm_debugfs_api_write(struct file *file, · 64 unmodified lines
163	160
164	161	strcpy(debugfs_buf, "");
165	162
166		− if (*off != 0 \|\| len == 0)
	163	+ if (*off != 0 \|\| len <= 1 \|\| len > PAGE_SIZE - 1)
167	164	return -EINVAL;
168	165
169		− kern_buff = kzalloc(len, GFP_KERNEL);
170		− if (!kern_buff)
171		− return -ENOMEM;
172		−
	166	+ kern_buff = memdup_user_nul(ptr, len);
	167	+ if (IS_ERR(kern_buff))
	168	+ return PTR_ERR(kern_buff);
173	169	tmp_buff = kern_buff;
174	170
175		− ret = strncpy_from_user(kern_buff, ptr, len);
176		− if (ret < 0) {
177		− ret = -EFAULT;
178		− goto err;
179		− }
180		−
181	171	/* Read the API name from a user request */
182	172	pm_api_req = strsep(&kern_buff, " ");
183	173

drivers/firmware/xilinx/zynqmp.c+55−1

@@ -24,6 +24,8 @@ · 23 unmodified lines
24	24	#include <linux/firmware/xlnx-zynqmp.h>
25	25	#include "zynqmp-debug.h"
26	26
	27	+static const struct zynqmp_eemi_ops *eemi_ops_tbl;
	28	+
27	29	static const struct mfd_cell firmware_devs[] = {
28	30	{
29	31	.name = "zynqmp_power_controller",
@@ -537,6 +539,49 @@ static int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, · 507 unmodified lines
537	539	return ret;
538	540	}
539	541
	542	+/**
	543	+ * zynqmp_pm_fpga_load - Perform the fpga load
	544	+ * @address: Address to write to
	545	+ * @size: pl bitstream size
	546	+ * @flags: Bitstream type
	547	+ * -XILINX_ZYNQMP_PM_FPGA_FULL: FPGA full reconfiguration
	548	+ * -XILINX_ZYNQMP_PM_FPGA_PARTIAL: FPGA partial reconfiguration
	549	+ *
	550	+ * This function provides access to pmufw. To transfer
	551	+ * the required bitstream into PL.
	552	+ *
	553	+ * Return: Returns status, either success or error+reason
	554	+ */
	555	+static int zynqmp_pm_fpga_load(const u64 address, const u32 size,
	556	+ const u32 flags)
	557	+{
	558	+ return zynqmp_pm_invoke_fn(PM_FPGA_LOAD, lower_32_bits(address),
	559	+ upper_32_bits(address), size, flags, NULL);
	560	+}
	561	+
	562	+/**
	563	+ * zynqmp_pm_fpga_get_status - Read value from PCAP status register
	564	+ * @value: Value to read
	565	+ *
	566	+ * This function provides access to the pmufw to get the PCAP
	567	+ * status
	568	+ *
	569	+ * Return: Returns status, either success or error+reason
	570	+ */
	571	+static int zynqmp_pm_fpga_get_status(u32 *value)
	572	+{
	573	+ u32 ret_payload[PAYLOAD_ARG_CNT];
	574	+ int ret;
	575	+
	576	+ if (!value)
	577	+ return -EINVAL;
	578	+
	579	+ ret = zynqmp_pm_invoke_fn(PM_FPGA_GET_STATUS, 0, 0, 0, 0, ret_payload);
	580	+ *value = ret_payload[1];
	581	+
	582	+ return ret;
	583	+}
	584	+
540	585	/**
541	586	* zynqmp_pm_init_finalize() - PM call to inform firmware that the caller
542	587	* master has initialized its own power management
@@ -640,6 +685,8 @@ static const struct zynqmp_eemi_ops eemi_ops = { · 97 unmodified lines
640	685	.request_node = zynqmp_pm_request_node,
641	686	.release_node = zynqmp_pm_release_node,
642	687	.set_requirement = zynqmp_pm_set_requirement,
	688	+ .fpga_load = zynqmp_pm_fpga_load,
	689	+ .fpga_get_status = zynqmp_pm_fpga_get_status,
643	690	};
644	691
645	692	/**
@@ -649,7 +696,11 @@ static const struct zynqmp_eemi_ops eemi_ops = { · 3 unmodified lines
649	696	*/
650	697	const struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void)
651	698	{
652		− return &eemi_ops;
	699	+ if (eemi_ops_tbl)
	700	+ return eemi_ops_tbl;
	701	+ else
	702	+ return ERR_PTR(-EPROBE_DEFER);
	703	+
653	704	}
654	705	EXPORT_SYMBOL_GPL(zynqmp_pm_get_eemi_ops);
655	706
@@ -694,6 +745,9 @@ static int zynqmp_firmware_probe(struct platform_device *pdev) · 38 unmodified lines
694	745	pr_info("%s Trustzone version v%d.%d\n", __func__,
695	746	pm_tz_version >> 16, pm_tz_version & 0xFFFF);
696	747
	748	+ /* Assign eemi_ops_table */
	749	+ eemi_ops_tbl = &eemi_ops;
	750	+
697	751	zynqmp_pm_api_debugfs_init();
698	752
699	753	ret = mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, firmware_devs,

drivers/fpga/Kconfig+9−0

@@ -204,4 +204,13 @@ config FPGA_DFL_PCI · 203 unmodified lines
204	204
205	205	To compile this as a module, choose M here.
206	206
	207	+config FPGA_MGR_ZYNQMP_FPGA
	208	+ tristate "Xilinx ZynqMP FPGA"
	209	+ depends on ARCH_ZYNQMP \|\| COMPILE_TEST
	210	+ help
	211	+ FPGA manager driver support for Xilinx ZynqMP FPGAs.
	212	+ This driver uses the processor configuration port(PCAP)
	213	+ to configure the programmable logic(PL) through PS
	214	+ on ZynqMP SoC.
	215	+
207	216	endif # FPGA

drivers/fpga/Makefile+1−0

@@ -17,6 +17,7 @@ obj-$(CONFIG_FPGA_MGR_STRATIX10_SOC) += stratix10-soc.o · 16 unmodified lines
17	17	obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o
18	18	obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o
19	19	obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o
	20	+obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o
20	21	obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o
21	22	obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o
22	23

drivers/fpga/zynqmp-fpga.c+159−0

@@ -0,0 +1,159 @@
	1	+// SPDX-License-Identifier: GPL-2.0+
	2	+/*
	3	+ * Copyright (C) 2019 Xilinx, Inc.
	4	+ */
	5	+
	6	+#include <linux/dma-mapping.h>
	7	+#include <linux/fpga/fpga-mgr.h>
	8	+#include <linux/io.h>
	9	+#include <linux/kernel.h>
	10	+#include <linux/module.h>
	11	+#include <linux/of_address.h>
	12	+#include <linux/string.h>
	13	+#include <linux/firmware/xlnx-zynqmp.h>
	14	+
	15	+/* Constant Definitions */
	16	+#define IXR_FPGA_DONE_MASK BIT(3)
	17	+
	18	+/**
	19	+ * struct zynqmp_fpga_priv - Private data structure
	20	+ * @dev: Device data structure
	21	+ * @flags: flags which is used to identify the bitfile type
	22	+ */
	23	+struct zynqmp_fpga_priv {
	24	+ struct device *dev;
	25	+ u32 flags;
	26	+};
	27	+
	28	+static int zynqmp_fpga_ops_write_init(struct fpga_manager *mgr,
	29	+ struct fpga_image_info *info,
	30	+ const char *buf, size_t size)
	31	+{
	32	+ struct zynqmp_fpga_priv *priv;
	33	+
	34	+ priv = mgr->priv;
	35	+ priv->flags = info->flags;
	36	+
	37	+ return 0;
	38	+}
	39	+
	40	+static int zynqmp_fpga_ops_write(struct fpga_manager *mgr,
	41	+ const char *buf, size_t size)
	42	+{
	43	+ const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
	44	+ struct zynqmp_fpga_priv *priv;
	45	+ dma_addr_t dma_addr;
	46	+ u32 eemi_flags = 0;
	47	+ char *kbuf;
	48	+ int ret;
	49	+
	50	+ if (!eemi_ops \|\| !eemi_ops->fpga_load)
	51	+ return -ENXIO;
	52	+
	53	+ priv = mgr->priv;
	54	+
	55	+ kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr, GFP_KERNEL);
	56	+ if (!kbuf)
	57	+ return -ENOMEM;
	58	+
	59	+ memcpy(kbuf, buf, size);
	60	+
	61	+ wmb(); /* ensure all writes are done before initiate FW call */
	62	+
	63	+ if (priv->flags & FPGA_MGR_PARTIAL_RECONFIG)
	64	+ eemi_flags \|= XILINX_ZYNQMP_PM_FPGA_PARTIAL;
	65	+
	66	+ ret = eemi_ops->fpga_load(dma_addr, size, eemi_flags);
	67	+
	68	+ dma_free_coherent(priv->dev, size, kbuf, dma_addr);
	69	+
	70	+ return ret;
	71	+}
	72	+
	73	+static int zynqmp_fpga_ops_write_complete(struct fpga_manager *mgr,
	74	+ struct fpga_image_info *info)
	75	+{
	76	+ return 0;
	77	+}
	78	+
	79	+static enum fpga_mgr_states zynqmp_fpga_ops_state(struct fpga_manager *mgr)
	80	+{
	81	+ const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
	82	+ u32 status;
	83	+
	84	+ if (!eemi_ops \|\| !eemi_ops->fpga_get_status)
	85	+ return FPGA_MGR_STATE_UNKNOWN;
	86	+
	87	+ eemi_ops->fpga_get_status(&status);
	88	+ if (status & IXR_FPGA_DONE_MASK)
	89	+ return FPGA_MGR_STATE_OPERATING;
	90	+
	91	+ return FPGA_MGR_STATE_UNKNOWN;
	92	+}
	93	+
	94	+static const struct fpga_manager_ops zynqmp_fpga_ops = {
	95	+ .state = zynqmp_fpga_ops_state,
	96	+ .write_init = zynqmp_fpga_ops_write_init,
	97	+ .write = zynqmp_fpga_ops_write,
	98	+ .write_complete = zynqmp_fpga_ops_write_complete,
	99	+};
	100	+
	101	+static int zynqmp_fpga_probe(struct platform_device *pdev)
	102	+{
	103	+ struct device *dev = &pdev->dev;
	104	+ struct zynqmp_fpga_priv *priv;
	105	+ struct fpga_manager *mgr;
	106	+ int ret;
	107	+
	108	+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	109	+ if (!priv)
	110	+ return -ENOMEM;
	111	+
	112	+ priv->dev = dev;
	113	+
	114	+ mgr = devm_fpga_mgr_create(dev, "Xilinx ZynqMP FPGA Manager",
	115	+ &zynqmp_fpga_ops, priv);
	116	+ if (!mgr)
	117	+ return -ENOMEM;
	118	+
	119	+ platform_set_drvdata(pdev, mgr);
	120	+
	121	+ ret = fpga_mgr_register(mgr);
	122	+ if (ret) {
	123	+ dev_err(dev, "unable to register FPGA manager");
	124	+ return ret;
	125	+ }
	126	+
	127	+ return 0;
	128	+}
	129	+
	130	+static int zynqmp_fpga_remove(struct platform_device *pdev)
	131	+{
	132	+ struct fpga_manager *mgr = platform_get_drvdata(pdev);
	133	+
	134	+ fpga_mgr_unregister(mgr);
	135	+
	136	+ return 0;
	137	+}
	138	+
	139	+static const struct of_device_id zynqmp_fpga_of_match[] = {
	140	+ { .compatible = "xlnx,zynqmp-pcap-fpga", },
	141	+ {},
	142	+};
	143	+
	144	+MODULE_DEVICE_TABLE(of, zynqmp_fpga_of_match);
	145	+
	146	+static struct platform_driver zynqmp_fpga_driver = {
	147	+ .probe = zynqmp_fpga_probe,
	148	+ .remove = zynqmp_fpga_remove,
	149	+ .driver = {
	150	+ .name = "zynqmp_fpga_manager",
	151	+ .of_match_table = of_match_ptr(zynqmp_fpga_of_match),
	152	+ },
	153	+};
	154	+
	155	+module_platform_driver(zynqmp_fpga_driver);
	156	+
	157	+MODULE_AUTHOR("Nava kishore Manne <navam@xilinx.com>");
	158	+MODULE_DESCRIPTION("Xilinx ZynqMp FPGA Manager");
	159	+MODULE_LICENSE("GPL");

drivers/memory/emif.h+4−0

@@ -537,6 +537,9 @@ · 536 unmodified lines
537	537	#define MCONNID_SHIFT 0
538	538	#define MCONNID_MASK (0xff << 0)
539	539
	540	+/* READ_WRITE_LEVELING_CONTROL */
	541	+#define RDWRLVLFULL_START 0x80000000
	542	+
540	543	/* DDR_PHY_CTRL_1 - EMIF4D */
541	544	#define DLL_SLAVE_DLY_CTRL_SHIFT_4D 4
542	545	#define DLL_SLAVE_DLY_CTRL_MASK_4D (0xFF << 4)
@@ -598,6 +601,7 @@ extern struct emif_regs_amx3 ti_emif_regs_amx3; · 55 unmodified lines
598	601
599	602	void ti_emif_save_context(void);
600	603	void ti_emif_restore_context(void);
	604	+void ti_emif_run_hw_leveling(void);
601	605	void ti_emif_enter_sr(void);
602	606	void ti_emif_exit_sr(void);
603	607	void ti_emif_abort_sr(void);

drivers/memory/tegra/mc.c+20−14

@@ -51,6 +51,9 @@ · 50 unmodified lines
51	51	#define MC_EMEM_ADR_CFG 0x54
52	52	#define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0)
53	53
	54	+#define MC_TIMING_CONTROL 0xfc
	55	+#define MC_TIMING_UPDATE BIT(0)
	56	+
54	57	static const struct of_device_id tegra_mc_of_match[] = {
55	58	#ifdef CONFIG_ARCH_TEGRA_2x_SOC
56	59	{ .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc },
@@ -74,7 +77,7 @@ static const struct of_device_id tegra_mc_of_match[] = { · 17 unmodified lines
74	77	};
75	78	MODULE_DEVICE_TABLE(of, tegra_mc_of_match);
76	79
77		−static int terga_mc_block_dma_common(struct tegra_mc *mc,
	80	+static int tegra_mc_block_dma_common(struct tegra_mc *mc,
78	81	const struct tegra_mc_reset *rst)
79	82	{
80	83	unsigned long flags;
@@ -90,13 +93,13 @@ static int terga_mc_block_dma_common(struct tegra_mc *mc, · 9 unmodified lines
90	93	return 0;
91	94	}
92	95
93		−static bool terga_mc_dma_idling_common(struct tegra_mc *mc,
	96	+static bool tegra_mc_dma_idling_common(struct tegra_mc *mc,
94	97	const struct tegra_mc_reset *rst)
95	98	{
96	99	return (mc_readl(mc, rst->status) & BIT(rst->bit)) != 0;
97	100	}
98	101
99		−static int terga_mc_unblock_dma_common(struct tegra_mc *mc,
	102	+static int tegra_mc_unblock_dma_common(struct tegra_mc *mc,
100	103	const struct tegra_mc_reset *rst)
101	104	{
102	105	unsigned long flags;
@@ -112,17 +115,17 @@ static int terga_mc_unblock_dma_common(struct tegra_mc *mc, · 9 unmodified lines
112	115	return 0;
113	116	}
114	117
115		−static int terga_mc_reset_status_common(struct tegra_mc *mc,
	118	+static int tegra_mc_reset_status_common(struct tegra_mc *mc,
116	119	const struct tegra_mc_reset *rst)
117	120	{
118	121	return (mc_readl(mc, rst->control) & BIT(rst->bit)) != 0;
119	122	}
120	123
121		−const struct tegra_mc_reset_ops terga_mc_reset_ops_common = {
122		− .block_dma = terga_mc_block_dma_common,
123		− .dma_idling = terga_mc_dma_idling_common,
124		− .unblock_dma = terga_mc_unblock_dma_common,
125		− .reset_status = terga_mc_reset_status_common,
	124	+const struct tegra_mc_reset_ops tegra_mc_reset_ops_common = {
	125	+ .block_dma = tegra_mc_block_dma_common,
	126	+ .dma_idling = tegra_mc_dma_idling_common,
	127	+ .unblock_dma = tegra_mc_unblock_dma_common,
	128	+ .reset_status = tegra_mc_reset_status_common,
126	129	};
127	130
128	131	static inline struct tegra_mc reset_to_mc(struct reset_controller_dev rcdev)
@@ -282,25 +285,28 @@ static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc) · 153 unmodified lines
282	285	u32 value;
283	286
284	287	/* compute the number of MC clock cycles per tick */
285		− tick = mc->tick * clk_get_rate(mc->clk);
	288	+ tick = (unsigned long long)mc->tick * clk_get_rate(mc->clk);
286	289	do_div(tick, NSEC_PER_SEC);
287	290
288		− value = readl(mc->regs + MC_EMEM_ARB_CFG);
	291	+ value = mc_readl(mc, MC_EMEM_ARB_CFG);
289	292	value &= ~MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK;
290	293	value \|= MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(tick);
291		− writel(value, mc->regs + MC_EMEM_ARB_CFG);
	294	+ mc_writel(mc, value, MC_EMEM_ARB_CFG);
292	295
293	296	/* write latency allowance defaults */
294	297	for (i = 0; i < mc->soc->num_clients; i++) {
295	298	const struct tegra_mc_la *la = &mc->soc->clients[i].la;
296	299	u32 value;
297	300
298		− value = readl(mc->regs + la->reg);
	301	+ value = mc_readl(mc, la->reg);
299	302	value &= ~(la->mask << la->shift);
300	303	value \|= (la->def & la->mask) << la->shift;
301		− writel(value, mc->regs + la->reg);
	304	+ mc_writel(mc, value, la->reg);
302	305	}
303	306
	307	+ /* latch new values */
	308	+ mc_writel(mc, MC_TIMING_UPDATE, MC_TIMING_CONTROL);
	309	+
304	310	return 0;
305	311	}
306	312

drivers/memory/tegra/mc.h+1−1

@@ -35,7 +35,7 @@ static inline void mc_writel(struct tegra_mc *mc, u32 value, · 34 unmodified lines
35	35	writel_relaxed(value, mc->regs + offset);
36	36	}
37	37
38		−extern const struct tegra_mc_reset_ops terga_mc_reset_ops_common;
	38	+extern const struct tegra_mc_reset_ops tegra_mc_reset_ops_common;
39	39
40	40	#ifdef CONFIG_ARCH_TEGRA_2x_SOC
41	41	extern const struct tegra_mc_soc tegra20_mc_soc;

drivers/memory/tegra/tegra114.c+2−2

@@ -572,7 +572,7 @@ static const struct tegra_mc_client tegra114_mc_clients[] = { · 571 unmodified lines
572	572	},
573	573	}, {
574	574	.id = 0x34,
575		− .name = "fdcwr2",
	575	+ .name = "fdcdwr2",
576	576	.swgroup = TEGRA_SWGROUP_NV,
577	577	.smmu = {
578	578	.reg = 0x22c,
@@ -975,7 +975,7 @@ const struct tegra_mc_soc tegra114_mc_soc = { · 396 unmodified lines
975	975	.smmu = &tegra114_smmu_soc,
976	976	.intmask = MC_INT_INVALID_SMMU_PAGE \| MC_INT_SECURITY_VIOLATION \|
977	977	MC_INT_DECERR_EMEM,
978		− .reset_ops = &terga_mc_reset_ops_common,
	978	+ .reset_ops = &tegra_mc_reset_ops_common,
979	979	.resets = tegra114_mc_resets,
980	980	.num_resets = ARRAY_SIZE(tegra114_mc_resets),
981	981	};

drivers/memory/tegra/tegra124.c+2−2

@@ -1074,7 +1074,7 @@ const struct tegra_mc_soc tegra124_mc_soc = { · 1073 unmodified lines
1074	1074	.intmask = MC_INT_DECERR_MTS \| MC_INT_SECERR_SEC \| MC_INT_DECERR_VPR \|
1075	1075	MC_INT_INVALID_APB_ASID_UPDATE \| MC_INT_INVALID_SMMU_PAGE \|
1076	1076	MC_INT_SECURITY_VIOLATION \| MC_INT_DECERR_EMEM,
1077		− .reset_ops = &terga_mc_reset_ops_common,
	1077	+ .reset_ops = &tegra_mc_reset_ops_common,
1078	1078	.resets = tegra124_mc_resets,
1079	1079	.num_resets = ARRAY_SIZE(tegra124_mc_resets),
1080	1080	};
@@ -1104,7 +1104,7 @@ const struct tegra_mc_soc tegra132_mc_soc = { · 23 unmodified lines
1104	1104	.intmask = MC_INT_DECERR_MTS \| MC_INT_SECERR_SEC \| MC_INT_DECERR_VPR \|
1105	1105	MC_INT_INVALID_APB_ASID_UPDATE \| MC_INT_INVALID_SMMU_PAGE \|
1106	1106	MC_INT_SECURITY_VIOLATION \| MC_INT_DECERR_EMEM,
1107		− .reset_ops = &terga_mc_reset_ops_common,
	1107	+ .reset_ops = &tegra_mc_reset_ops_common,
1108	1108	.resets = tegra124_mc_resets,
1109	1109	.num_resets = ARRAY_SIZE(tegra124_mc_resets),
1110	1110	};

drivers/memory/tegra/tegra20.c+14−14

@@ -198,7 +198,7 @@ static const struct tegra_mc_reset tegra20_mc_resets[] = { · 197 unmodified lines
198	198	TEGRA20_MC_RESET(VI, 0x100, 0x178, 0x104, 14),
199	199	};
200	200
201		−static int terga20_mc_hotreset_assert(struct tegra_mc *mc,
	201	+static int tegra20_mc_hotreset_assert(struct tegra_mc *mc,
202	202	const struct tegra_mc_reset *rst)
203	203	{
204	204	unsigned long flags;
@@ -214,7 +214,7 @@ static int terga20_mc_hotreset_assert(struct tegra_mc *mc, · 9 unmodified lines
214	214	return 0;
215	215	}
216	216
217		−static int terga20_mc_hotreset_deassert(struct tegra_mc *mc,
	217	+static int tegra20_mc_hotreset_deassert(struct tegra_mc *mc,
218	218	const struct tegra_mc_reset *rst)
219	219	{
220	220	unsigned long flags;
@@ -230,7 +230,7 @@ static int terga20_mc_hotreset_deassert(struct tegra_mc *mc, · 9 unmodified lines
230	230	return 0;
231	231	}
232	232
233		−static int terga20_mc_block_dma(struct tegra_mc *mc,
	233	+static int tegra20_mc_block_dma(struct tegra_mc *mc,
234	234	const struct tegra_mc_reset *rst)
235	235	{
236	236	unsigned long flags;
@@ -246,19 +246,19 @@ static int terga20_mc_block_dma(struct tegra_mc *mc, · 9 unmodified lines
246	246	return 0;
247	247	}
248	248
249		−static bool terga20_mc_dma_idling(struct tegra_mc *mc,
	249	+static bool tegra20_mc_dma_idling(struct tegra_mc *mc,
250	250	const struct tegra_mc_reset *rst)
251	251	{
252	252	return mc_readl(mc, rst->status) == 0;
253	253	}
254	254
255		−static int terga20_mc_reset_status(struct tegra_mc *mc,
	255	+static int tegra20_mc_reset_status(struct tegra_mc *mc,
256	256	const struct tegra_mc_reset *rst)
257	257	{
258	258	return (mc_readl(mc, rst->reset) & BIT(rst->bit)) == 0;
259	259	}
260	260
261		−static int terga20_mc_unblock_dma(struct tegra_mc *mc,
	261	+static int tegra20_mc_unblock_dma(struct tegra_mc *mc,
262	262	const struct tegra_mc_reset *rst)
263	263	{
264	264	unsigned long flags;
@@ -274,13 +274,13 @@ static int terga20_mc_unblock_dma(struct tegra_mc *mc, · 9 unmodified lines
274	274	return 0;
275	275	}
276	276
277		−const struct tegra_mc_reset_ops terga20_mc_reset_ops = {
278		− .hotreset_assert = terga20_mc_hotreset_assert,
279		− .hotreset_deassert = terga20_mc_hotreset_deassert,
280		− .block_dma = terga20_mc_block_dma,
281		− .dma_idling = terga20_mc_dma_idling,
282		− .unblock_dma = terga20_mc_unblock_dma,
283		− .reset_status = terga20_mc_reset_status,
	277	+static const struct tegra_mc_reset_ops tegra20_mc_reset_ops = {
	278	+ .hotreset_assert = tegra20_mc_hotreset_assert,
	279	+ .hotreset_deassert = tegra20_mc_hotreset_deassert,
	280	+ .block_dma = tegra20_mc_block_dma,
	281	+ .dma_idling = tegra20_mc_dma_idling,
	282	+ .unblock_dma = tegra20_mc_unblock_dma,
	283	+ .reset_status = tegra20_mc_reset_status,
284	284	};
285	285
286	286	const struct tegra_mc_soc tegra20_mc_soc = {
@@ -290,7 +290,7 @@ const struct tegra_mc_soc tegra20_mc_soc = { · 3 unmodified lines
290	290	.client_id_mask = 0x3f,
291	291	.intmask = MC_INT_SECURITY_VIOLATION \| MC_INT_INVALID_GART_PAGE \|
292	292	MC_INT_DECERR_EMEM,
293		− .reset_ops = &terga20_mc_reset_ops,
	293	+ .reset_ops = &tegra20_mc_reset_ops,
294	294	.resets = tegra20_mc_resets,
295	295	.num_resets = ARRAY_SIZE(tegra20_mc_resets),
296	296	};

drivers/memory/tegra/tegra210.c+1−1

@@ -1132,7 +1132,7 @@ const struct tegra_mc_soc tegra210_mc_soc = { · 1131 unmodified lines
1132	1132	.intmask = MC_INT_DECERR_MTS \| MC_INT_SECERR_SEC \| MC_INT_DECERR_VPR \|
1133	1133	MC_INT_INVALID_APB_ASID_UPDATE \| MC_INT_INVALID_SMMU_PAGE \|
1134	1134	MC_INT_SECURITY_VIOLATION \| MC_INT_DECERR_EMEM,
1135		− .reset_ops = &terga_mc_reset_ops_common,
	1135	+ .reset_ops = &tegra_mc_reset_ops_common,
1136	1136	.resets = tegra210_mc_resets,
1137	1137	.num_resets = ARRAY_SIZE(tegra210_mc_resets),
1138	1138	};

drivers/memory/tegra/tegra30.c+2−2

@@ -726,7 +726,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { · 725 unmodified lines
726	726	},
727	727	}, {
728	728	.id = 0x34,
729		− .name = "fdcwr2",
	729	+ .name = "fdcdwr2",
730	730	.swgroup = TEGRA_SWGROUP_NV2,
731	731	.smmu = {
732	732	.reg = 0x22c,
@@ -999,7 +999,7 @@ const struct tegra_mc_soc tegra30_mc_soc = { · 266 unmodified lines
999	999	.smmu = &tegra30_smmu_soc,
1000	1000	.intmask = MC_INT_INVALID_SMMU_PAGE \| MC_INT_SECURITY_VIOLATION \|
1001	1001	MC_INT_DECERR_EMEM,
1002		− .reset_ops = &terga_mc_reset_ops_common,
	1002	+ .reset_ops = &tegra_mc_reset_ops_common,
1003	1003	.resets = tegra30_mc_resets,
1004	1004	.num_resets = ARRAY_SIZE(tegra30_mc_resets),
1005	1005	};

drivers/memory/ti-emif-pm.c+3−0

@@ -138,6 +138,9 @@ static int ti_emif_alloc_sram(struct device *dev, · 137 unmodified lines
138	138	emif_data->pm_functions.exit_sr =
139	139	sram_resume_address(emif_data,
140	140	(unsigned long)ti_emif_exit_sr);
	141	+ emif_data->pm_functions.run_hw_leveling =
	142	+ sram_resume_address(emif_data,
	143	+ (unsigned long)ti_emif_run_hw_leveling);
141	144
142	145	emif_data->pm_data.regs_virt =
143	146	(struct emif_regs_amx3 *)emif_data->ti_emif_sram_data_virt;

drivers/memory/ti-emif-sram-pm.S+41−0

@@ -27,6 +27,7 @@ · 26 unmodified lines
27	27	#define EMIF_POWER_MGMT_SELF_REFRESH_MODE_MASK 0x0700
28	28
29	29	#define EMIF_SDCFG_TYPE_DDR2 0x2 << SDRAM_TYPE_SHIFT
	30	+#define EMIF_SDCFG_TYPE_DDR3 0x3 << SDRAM_TYPE_SHIFT
30	31	#define EMIF_STATUS_READY 0x4
31	32
32	33	#define AM43XX_EMIF_PHY_CTRL_REG_COUNT 0x120
@@ -244,6 +245,46 @@ emif_skip_restore_extra_regs: · 211 unmodified lines
244	245	mov pc, lr
245	246	ENDPROC(ti_emif_restore_context)
246	247
	248	+/*
	249	+ * void ti_emif_run_hw_leveling(void)
	250	+ *
	251	+ * Used during resume to run hardware leveling again and restore the
	252	+ * configuration of the EMIF PHY, only for DDR3.
	253	+ */
	254	+ENTRY(ti_emif_run_hw_leveling)
	255	+ adr r4, ti_emif_pm_sram_data
	256	+ ldr r0, [r4, #EMIF_PM_BASE_ADDR_PHYS_OFFSET]
	257	+
	258	+ ldr r3, [r0, #EMIF_READ_WRITE_LEVELING_CONTROL]
	259	+ orr r3, r3, #RDWRLVLFULL_START
	260	+ ldr r2, [r0, #EMIF_SDRAM_CONFIG]
	261	+ and r2, r2, #SDRAM_TYPE_MASK
	262	+ cmp r2, #EMIF_SDCFG_TYPE_DDR3
	263	+ bne skip_hwlvl
	264	+
	265	+ str r3, [r0, #EMIF_READ_WRITE_LEVELING_CONTROL]
	266	+
	267	+ /*
	268	+ * If EMIF registers are touched during initial stage of HW
	269	+ * leveling sequence there will be an L3 NOC timeout error issued
	270	+ * as the EMIF will not respond, which is not fatal, but it is
	271	+ * avoidable. This small wait loop is enough time for this condition
	272	+ * to clear, even at worst case of CPU running at max speed of 1Ghz.
	273	+ */
	274	+ mov r2, #0x2000
	275	+1:
	276	+ subs r2, r2, #0x1
	277	+ bne 1b
	278	+
	279	+ /* Bit clears when operation is complete */
	280	+2: ldr r1, [r0, #EMIF_READ_WRITE_LEVELING_CONTROL]
	281	+ tst r1, #RDWRLVLFULL_START
	282	+ bne 2b
	283	+
	284	+skip_hwlvl:
	285	+ mov pc, lr
	286	+ENDPROC(ti_emif_run_hw_leveling)
	287	+
247	288	/*
248	289	* void ti_emif_enter_sr(void)
249	290	*

drivers/misc/Kconfig+0−24

@@ -496,30 +496,6 @@ config VEXPRESS_SYSCFG · 495 unmodified lines
496	496	bus. System Configuration interface is one of the possible means
497	497	of generating transactions on this bus.
498	498
499		−config ASPEED_P2A_CTRL
500		− depends on (ARCH_ASPEED \|\| COMPILE_TEST) && REGMAP && MFD_SYSCON
501		− tristate "Aspeed ast2400/2500 HOST P2A VGA MMIO to BMC bridge control"
502		− help
503		− Control Aspeed ast2400/2500 HOST P2A VGA MMIO to BMC mappings through
504		− ioctl()s, the driver also provides an interface for userspace mappings to
505		− a pre-defined region.
506		−
507		−config ASPEED_LPC_CTRL
508		− depends on (ARCH_ASPEED \|\| COMPILE_TEST) && REGMAP && MFD_SYSCON
509		− tristate "Aspeed ast2400/2500 HOST LPC to BMC bridge control"
510		− ---help---
511		− Control Aspeed ast2400/2500 HOST LPC to BMC mappings through
512		− ioctl()s, the driver also provides a read/write interface to a BMC ram
513		− region where the host LPC read/write region can be buffered.
514		−
515		−config ASPEED_LPC_SNOOP
516		− tristate "Aspeed ast2500 HOST LPC snoop support"
517		− depends on (ARCH_ASPEED \|\| COMPILE_TEST) && REGMAP && MFD_SYSCON
518		− help
519		− Provides a driver to control the LPC snoop interface which
520		− allows the BMC to listen on and save the data written by
521		− the host to an arbitrary LPC I/O port.
522		−
523	499	config PCI_ENDPOINT_TEST
524	500	depends on PCI
525	501	select CRC32

drivers/misc/Makefile+0−3

@@ -54,9 +54,6 @@ obj-$(CONFIG_GENWQE) += genwqe/ · 53 unmodified lines
54	54	obj-$(CONFIG_ECHO) += echo/
55	55	obj-$(CONFIG_VEXPRESS_SYSCFG) += vexpress-syscfg.o
56	56	obj-$(CONFIG_CXL_BASE) += cxl/
57		−obj-$(CONFIG_ASPEED_LPC_CTRL) += aspeed-lpc-ctrl.o
58		−obj-$(CONFIG_ASPEED_LPC_SNOOP) += aspeed-lpc-snoop.o
59		−obj-$(CONFIG_ASPEED_P2A_CTRL) += aspeed-p2a-ctrl.o
60	57	obj-$(CONFIG_PCI_ENDPOINT_TEST) += pci_endpoint_test.o
61	58	obj-$(CONFIG_OCXL) += ocxl/
62	59	obj-y += cardreader/

drivers/nvmem/zynqmp_nvmem.c+7−3

@@ -16,6 +16,8 @@ struct zynqmp_nvmem_data { · 15 unmodified lines
16	16	struct nvmem_device *nvmem;
17	17	};
18	18
	19	+static const struct zynqmp_eemi_ops *eemi_ops;
	20	+
19	21	static int zynqmp_nvmem_read(void *context, unsigned int offset,
20	22	void *val, size_t bytes)
21	23	{
@@ -23,9 +25,7 @@ static int zynqmp_nvmem_read(void *context, unsigned int offset, · 1 unmodified line
23	25	int idcode, version;
24	26	struct zynqmp_nvmem_data *priv = context;
25	27
26		− const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
27		−
28		− if (!eemi_ops \|\| !eemi_ops->get_chipid)
	28	+ if (!eemi_ops->get_chipid)
29	29	return -ENXIO;
30	30
31	31	ret = eemi_ops->get_chipid(&idcode, &version);
@@ -61,6 +61,10 @@ static int zynqmp_nvmem_probe(struct platform_device *pdev) · 29 unmodified lines
61	61	if (!priv)
62	62	return -ENOMEM;
63	63
	64	+ eemi_ops = zynqmp_pm_get_eemi_ops();
	65	+ if (IS_ERR(eemi_ops))
	66	+ return PTR_ERR(eemi_ops);
	67	+
64	68	priv->dev = dev;
65	69	econfig.dev = dev;
66	70	econfig.reg_read = zynqmp_nvmem_read;

drivers/reset/reset-zynqmp.c+4−4

@@ -79,11 +79,11 @@ static int zynqmp_reset_probe(struct platform_device *pdev) · 78 unmodified lines
79	79	if (!priv)
80	80	return -ENOMEM;
81	81
82		− platform_set_drvdata(pdev, priv);
83		−
84	82	priv->eemi_ops = zynqmp_pm_get_eemi_ops();
85		− if (!priv->eemi_ops)
86		− return -ENXIO;
	83	+ if (IS_ERR(priv->eemi_ops))
	84	+ return PTR_ERR(priv->eemi_ops);
	85	+
	86	+ platform_set_drvdata(pdev, priv);
87	87
88	88	priv->rcdev.ops = &zynqmp_reset_ops;
89	89	priv->rcdev.owner = THIS_MODULE;

drivers/rtc/rtc-omap.c+41−8

@@ -403,15 +403,12 @@ static int omap_rtc_set_alarm(struct device dev, struct rtc_wkalrm alm) · 402 unmodified lines
403	403
404	404	static struct omap_rtc *omap_rtc_power_off_rtc;
405	405
406		−/*
407		− * omap_rtc_poweroff: RTC-controlled power off
408		− *
409		− * The RTC can be used to control an external PMIC via the pmic_power_en pin,
410		− * which can be configured to transition to OFF on ALARM2 events.
411		− *
412		− * Called with local interrupts disabled.
	406	+/**
	407	+ * omap_rtc_power_off_program: Set the pmic power off sequence. The RTC
	408	+ * generates pmic_pwr_enable control, which can be used to control an external
	409	+ * PMIC.
413	410	*/
414		−static void omap_rtc_power_off(void)
	411	+int omap_rtc_power_off_program(struct device *dev)
415	412	{
416	413	struct omap_rtc *rtc = omap_rtc_power_off_rtc;
417	414	struct rtc_time tm;
@@ -425,6 +422,9 @@ static void omap_rtc_power_off(void) · 7 unmodified lines
425	422	rtc_writel(rtc, OMAP_RTC_PMIC_REG, val \| OMAP_RTC_PMIC_POWER_EN_EN);
426	423
427	424	again:
	425	+ /* Clear any existing ALARM2 event */
	426	+ rtc_writel(rtc, OMAP_RTC_STATUS_REG, OMAP_RTC_STATUS_ALARM2);
	427	+
428	428	/* set alarm one second from now */
429	429	omap_rtc_read_time_raw(rtc, &tm);
430	430	seconds = tm.tm_sec;
@@ -461,6 +461,39 @@ again: · 30 unmodified lines
461	461
462	462	rtc->type->lock(rtc);
463	463
	464	+ return 0;
	465	+}
	466	+EXPORT_SYMBOL(omap_rtc_power_off_program);
	467	+
	468	+/*
	469	+ * omap_rtc_poweroff: RTC-controlled power off
	470	+ *
	471	+ * The RTC can be used to control an external PMIC via the pmic_power_en pin,
	472	+ * which can be configured to transition to OFF on ALARM2 events.
	473	+ *
	474	+ * Notes:
	475	+ * The one-second alarm offset is the shortest offset possible as the alarm
	476	+ * registers must be set before the next timer update and the offset
	477	+ * calculation is too heavy for everything to be done within a single access
	478	+ * period (~15 us).
	479	+ *
	480	+ * Called with local interrupts disabled.
	481	+ */
	482	+static void omap_rtc_power_off(void)
	483	+{
	484	+ struct rtc_device *rtc = omap_rtc_power_off_rtc->rtc;
	485	+ u32 val;
	486	+
	487	+ omap_rtc_power_off_program(rtc->dev.parent);
	488	+
	489	+ /* Set PMIC power enable and EXT_WAKEUP in case PB power on is used */
	490	+ omap_rtc_power_off_rtc->type->unlock(omap_rtc_power_off_rtc);
	491	+ val = rtc_readl(omap_rtc_power_off_rtc, OMAP_RTC_PMIC_REG);
	492	+ val \|= OMAP_RTC_PMIC_POWER_EN_EN \| OMAP_RTC_PMIC_EXT_WKUP_POL(0) \|
	493	+ OMAP_RTC_PMIC_EXT_WKUP_EN(0);
	494	+ rtc_writel(omap_rtc_power_off_rtc, OMAP_RTC_PMIC_REG, val);
	495	+ omap_rtc_power_off_rtc->type->lock(omap_rtc_power_off_rtc);
	496	+
464	497	/*
465	498	* Wait for alarm to trigger (within one second) and external PMIC to
466	499	* power off the system. Add a 500 ms margin for external latencies

drivers/soc/Kconfig+1−0

@@ -2,6 +2,7 @@ menu "SOC (System On Chip) specific Drivers" · 1 unmodified line
2	2
3	3	source "drivers/soc/actions/Kconfig"
4	4	source "drivers/soc/amlogic/Kconfig"
	5	+source "drivers/soc/aspeed/Kconfig"
5	6	source "drivers/soc/atmel/Kconfig"
6	7	source "drivers/soc/bcm/Kconfig"
7	8	source "drivers/soc/fsl/Kconfig"

drivers/soc/Makefile+1−0

@@ -4,6 +4,7 @@ · 3 unmodified lines
4	4	#
5	5
6	6	obj-$(CONFIG_ARCH_ACTIONS) += actions/
	7	+obj-$(CONFIG_SOC_ASPEED) += aspeed/
7	8	obj-$(CONFIG_ARCH_AT91) += atmel/
8	9	obj-y += bcm/
9	10	obj-$(CONFIG_ARCH_DOVE) += dove/

drivers/soc/amlogic/meson-gx-pwrc-vpu.c+144−16

@@ -11,6 +11,7 @@ · 10 unmodified lines
11	11	#include <linux/bitfield.h>
12	12	#include <linux/regmap.h>
13	13	#include <linux/mfd/syscon.h>
	14	+#include <linux/of_device.h>
14	15	#include <linux/reset.h>
15	16	#include <linux/clk.h>
16	17
@@ -26,6 +27,7 @@ · 9 unmodified lines
26	27	#define HHI_MEM_PD_REG0 (0x40 << 2)
27	28	#define HHI_VPU_MEM_PD_REG0 (0x41 << 2)
28	29	#define HHI_VPU_MEM_PD_REG1 (0x42 << 2)
	30	+#define HHI_VPU_MEM_PD_REG2 (0x4d << 2)
29	31
30	32	struct meson_gx_pwrc_vpu {
31	33	struct generic_pm_domain genpd;
@@ -54,12 +56,55 @@ static int meson_gx_pwrc_vpu_power_off(struct generic_pm_domain *genpd) · 22 unmodified lines
54	56	/* Power Down Memories */
55	57	for (i = 0; i < 32; i += 2) {
56	58	regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0,
57		− 0x2 << i, 0x3 << i);
	59	+ 0x3 << i, 0x3 << i);
58	60	udelay(5);
59	61	}
60	62	for (i = 0; i < 32; i += 2) {
61	63	regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG1,
62		− 0x2 << i, 0x3 << i);
	64	+ 0x3 << i, 0x3 << i);
	65	+ udelay(5);
	66	+ }
	67	+ for (i = 8; i < 16; i++) {
	68	+ regmap_update_bits(pd->regmap_hhi, HHI_MEM_PD_REG0,
	69	+ BIT(i), BIT(i));
	70	+ udelay(5);
	71	+ }
	72	+ udelay(20);
	73	+
	74	+ regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
	75	+ GEN_PWR_VPU_HDMI, GEN_PWR_VPU_HDMI);
	76	+
	77	+ msleep(20);
	78	+
	79	+ clk_disable_unprepare(pd->vpu_clk);
	80	+ clk_disable_unprepare(pd->vapb_clk);
	81	+
	82	+ return 0;
	83	+}
	84	+
	85	+static int meson_g12a_pwrc_vpu_power_off(struct generic_pm_domain *genpd)
	86	+{
	87	+ struct meson_gx_pwrc_vpu *pd = genpd_to_pd(genpd);
	88	+ int i;
	89	+
	90	+ regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
	91	+ GEN_PWR_VPU_HDMI_ISO, GEN_PWR_VPU_HDMI_ISO);
	92	+ udelay(20);
	93	+
	94	+ /* Power Down Memories */
	95	+ for (i = 0; i < 32; i += 2) {
	96	+ regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0,
	97	+ 0x3 << i, 0x3 << i);
	98	+ udelay(5);
	99	+ }
	100	+ for (i = 0; i < 32; i += 2) {
	101	+ regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG1,
	102	+ 0x3 << i, 0x3 << i);
	103	+ udelay(5);
	104	+ }
	105	+ for (i = 0; i < 32; i += 2) {
	106	+ regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG2,
	107	+ 0x3 << i, 0x3 << i);
63	108	udelay(5);
64	109	}
65	110	for (i = 8; i < 16; i++) {
@@ -108,13 +153,67 @@ static int meson_gx_pwrc_vpu_power_on(struct generic_pm_domain *genpd) · 42 unmodified lines
108	153	/* Power Up Memories */
109	154	for (i = 0; i < 32; i += 2) {
110	155	regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0,
111		− 0x2 << i, 0);
	156	+ 0x3 << i, 0);
	157	+ udelay(5);
	158	+ }
	159	+
	160	+ for (i = 0; i < 32; i += 2) {
	161	+ regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG1,
	162	+ 0x3 << i, 0);
	163	+ udelay(5);
	164	+ }
	165	+
	166	+ for (i = 8; i < 16; i++) {
	167	+ regmap_update_bits(pd->regmap_hhi, HHI_MEM_PD_REG0,
	168	+ BIT(i), 0);
	169	+ udelay(5);
	170	+ }
	171	+ udelay(20);
	172	+
	173	+ ret = reset_control_assert(pd->rstc);
	174	+ if (ret)
	175	+ return ret;
	176	+
	177	+ regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
	178	+ GEN_PWR_VPU_HDMI_ISO, 0);
	179	+
	180	+ ret = reset_control_deassert(pd->rstc);
	181	+ if (ret)
	182	+ return ret;
	183	+
	184	+ ret = meson_gx_pwrc_vpu_setup_clk(pd);
	185	+ if (ret)
	186	+ return ret;
	187	+
	188	+ return 0;
	189	+}
	190	+
	191	+static int meson_g12a_pwrc_vpu_power_on(struct generic_pm_domain *genpd)
	192	+{
	193	+ struct meson_gx_pwrc_vpu *pd = genpd_to_pd(genpd);
	194	+ int ret;
	195	+ int i;
	196	+
	197	+ regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
	198	+ GEN_PWR_VPU_HDMI, 0);
	199	+ udelay(20);
	200	+
	201	+ /* Power Up Memories */
	202	+ for (i = 0; i < 32; i += 2) {
	203	+ regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0,
	204	+ 0x3 << i, 0);
112	205	udelay(5);
113	206	}
114	207
115	208	for (i = 0; i < 32; i += 2) {
116	209	regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG1,
117		− 0x2 << i, 0);
	210	+ 0x3 << i, 0);
	211	+ udelay(5);
	212	+ }
	213	+
	214	+ for (i = 0; i < 32; i += 2) {
	215	+ regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG2,
	216	+ 0x3 << i, 0);
118	217	udelay(5);
119	218	}
120	219
@@ -160,15 +259,37 @@ static struct meson_gx_pwrc_vpu vpu_hdmi_pd = { · 39 unmodified lines
160	259	},
161	260	};
162	261
	262	+static struct meson_gx_pwrc_vpu vpu_hdmi_pd_g12a = {
	263	+ .genpd = {
	264	+ .name = "vpu_hdmi",
	265	+ .power_off = meson_g12a_pwrc_vpu_power_off,
	266	+ .power_on = meson_g12a_pwrc_vpu_power_on,
	267	+ },
	268	+};
	269	+
163	270	static int meson_gx_pwrc_vpu_probe(struct platform_device *pdev)
164	271	{
	272	+ const struct meson_gx_pwrc_vpu *vpu_pd_match;
165	273	struct regmap regmap_ao, regmap_hhi;
	274	+ struct meson_gx_pwrc_vpu *vpu_pd;
166	275	struct reset_control *rstc;
167	276	struct clk *vpu_clk;
168	277	struct clk *vapb_clk;
169	278	bool powered_off;
170	279	int ret;
171	280
	281	+ vpu_pd_match = of_device_get_match_data(&pdev->dev);
	282	+ if (!vpu_pd_match) {
	283	+ dev_err(&pdev->dev, "failed to get match data\n");
	284	+ return -ENODEV;
	285	+ }
	286	+
	287	+ vpu_pd = devm_kzalloc(&pdev->dev, sizeof(*vpu_pd), GFP_KERNEL);
	288	+ if (!vpu_pd)
	289	+ return -ENOMEM;
	290	+
	291	+ memcpy(vpu_pd, vpu_pd_match, sizeof(*vpu_pd));
	292	+
172	293	regmap_ao = syscon_node_to_regmap(of_get_parent(pdev->dev.of_node));
173	294	if (IS_ERR(regmap_ao)) {
174	295	dev_err(&pdev->dev, "failed to get regmap\n");
@@ -201,39 +322,46 @@ static int meson_gx_pwrc_vpu_probe(struct platform_device *pdev) · 26 unmodified lines
201	322	return PTR_ERR(vapb_clk);
202	323	}
203	324
204		− vpu_hdmi_pd.regmap_ao = regmap_ao;
205		− vpu_hdmi_pd.regmap_hhi = regmap_hhi;
206		− vpu_hdmi_pd.rstc = rstc;
207		− vpu_hdmi_pd.vpu_clk = vpu_clk;
208		− vpu_hdmi_pd.vapb_clk = vapb_clk;
	325	+ vpu_pd->regmap_ao = regmap_ao;
	326	+ vpu_pd->regmap_hhi = regmap_hhi;
	327	+ vpu_pd->rstc = rstc;
	328	+ vpu_pd->vpu_clk = vpu_clk;
	329	+ vpu_pd->vapb_clk = vapb_clk;
	330	+
	331	+ platform_set_drvdata(pdev, vpu_pd);
209	332
210		− powered_off = meson_gx_pwrc_vpu_get_power(&vpu_hdmi_pd);
	333	+ powered_off = meson_gx_pwrc_vpu_get_power(vpu_pd);
211	334
212	335	/* If already powered, sync the clock states */
213	336	if (!powered_off) {
214		− ret = meson_gx_pwrc_vpu_setup_clk(&vpu_hdmi_pd);
	337	+ ret = meson_gx_pwrc_vpu_setup_clk(vpu_pd);
215	338	if (ret)
216	339	return ret;
217	340	}
218	341
219		− pm_genpd_init(&vpu_hdmi_pd.genpd, &pm_domain_always_on_gov,
	342	+ pm_genpd_init(&vpu_pd->genpd, &pm_domain_always_on_gov,
220	343	powered_off);
221	344
222	345	return of_genpd_add_provider_simple(pdev->dev.of_node,
223		− &vpu_hdmi_pd.genpd);
	346	+ &vpu_pd->genpd);
224	347	}
225	348
226	349	static void meson_gx_pwrc_vpu_shutdown(struct platform_device *pdev)
227	350	{
	351	+ struct meson_gx_pwrc_vpu *vpu_pd = platform_get_drvdata(pdev);
228	352	bool powered_off;
229	353
230		− powered_off = meson_gx_pwrc_vpu_get_power(&vpu_hdmi_pd);
	354	+ powered_off = meson_gx_pwrc_vpu_get_power(vpu_pd);
231	355	if (!powered_off)
232		− meson_gx_pwrc_vpu_power_off(&vpu_hdmi_pd.genpd);
	356	+ vpu_pd->genpd.power_off(&vpu_pd->genpd);
233	357	}
234	358
235	359	static const struct of_device_id meson_gx_pwrc_vpu_match_table[] = {
236		− { .compatible = "amlogic,meson-gx-pwrc-vpu" },
	360	+ { .compatible = "amlogic,meson-gx-pwrc-vpu", .data = &vpu_hdmi_pd },
	361	+ {
	362	+ .compatible = "amlogic,meson-g12a-pwrc-vpu",
	363	+ .data = &vpu_hdmi_pd_g12a
	364	+ },
237	365	{ /* sentinel */ }
238	366	};
239	367

drivers/soc/amlogic/meson-gx-socinfo.c+27−16

@@ -37,26 +37,34 @@ static const struct meson_gx_soc_id { · 36 unmodified lines
37	37	{ "AXG", 0x25 },
38	38	{ "GXLX", 0x26 },
39	39	{ "TXHD", 0x27 },
	40	+ { "G12A", 0x28 },
	41	+ { "G12B", 0x29 },
40	42	};
41	43
42	44	static const struct meson_gx_package_id {
43	45	const char *name;
44	46	unsigned int major_id;
45	47	unsigned int pack_id;
	48	+ unsigned int pack_mask;
46	49	} soc_packages[] = {
47		− { "S905", 0x1f, 0 },
48		− { "S905H", 0x1f, 0x13 },
49		− { "S905M", 0x1f, 0x20 },
50		− { "S905D", 0x21, 0 },
51		− { "S905X", 0x21, 0x80 },
52		− { "S905W", 0x21, 0xa0 },
53		− { "S905L", 0x21, 0xc0 },
54		− { "S905M2", 0x21, 0xe0 },
55		− { "S912", 0x22, 0 },
56		− { "962X", 0x24, 0x10 },
57		− { "962E", 0x24, 0x20 },
58		− { "A113X", 0x25, 0x37 },
59		− { "A113D", 0x25, 0x22 },
	50	+ { "S905", 0x1f, 0, 0x20 }, /* pack_id != 0x20 */
	51	+ { "S905H", 0x1f, 0x3, 0xf }, /* pack_id & 0xf == 0x3 */
	52	+ { "S905M", 0x1f, 0x20, 0xf0 }, /* pack_id == 0x20 */
	53	+ { "S905D", 0x21, 0, 0xf0 },
	54	+ { "S905X", 0x21, 0x80, 0xf0 },
	55	+ { "S905W", 0x21, 0xa0, 0xf0 },
	56	+ { "S905L", 0x21, 0xc0, 0xf0 },
	57	+ { "S905M2", 0x21, 0xe0, 0xf0 },
	58	+ { "S805X", 0x21, 0x30, 0xf0 },
	59	+ { "S805Y", 0x21, 0xb0, 0xf0 },
	60	+ { "S912", 0x22, 0, 0x0 }, /* Only S912 is known for GXM */
	61	+ { "962X", 0x24, 0x10, 0xf0 },
	62	+ { "962E", 0x24, 0x20, 0xf0 },
	63	+ { "A113X", 0x25, 0x37, 0xff },
	64	+ { "A113D", 0x25, 0x22, 0xff },
	65	+ { "S905D2", 0x28, 0x10, 0xf0 },
	66	+ { "S905X2", 0x28, 0x40, 0xf0 },
	67	+ { "S922X", 0x29, 0x40, 0xf0 },
60	68	};
61	69
62	70	static inline unsigned int socinfo_to_major(u32 socinfo)
@@ -81,13 +89,14 @@ static inline unsigned int socinfo_to_misc(u32 socinfo) · 18 unmodified lines
81	89
82	90	static const char *socinfo_to_package_id(u32 socinfo)
83	91	{
84		− unsigned int pack = socinfo_to_pack(socinfo) & 0xf0;
	92	+ unsigned int pack = socinfo_to_pack(socinfo);
85	93	unsigned int major = socinfo_to_major(socinfo);
86	94	int i;
87	95
88	96	for (i = 0 ; i < ARRAY_SIZE(soc_packages) ; ++i) {
89	97	if (soc_packages[i].major_id == major &&
90		− soc_packages[i].pack_id == pack)
	98	+ soc_packages[i].pack_id ==
	99	+ (pack & soc_packages[i].pack_mask))
91	100	return soc_packages[i].name;
92	101	}
93	102
@@ -123,8 +132,10 @@ static int __init meson_gx_socinfo_init(void) · 29 unmodified lines
123	132	return -ENODEV;
124	133
125	134	/* check if interface is enabled */
126		− if (!of_device_is_available(np))
	135	+ if (!of_device_is_available(np)) {
	136	+ of_node_put(np);
127	137	return -ENODEV;
	138	+ }
128	139
129	140	/* check if chip-id is available */
130	141	if (!of_property_read_bool(np, "amlogic,has-chip-id"))

drivers/soc/aspeed/Kconfig+31−0

@@ -0,0 +1,31 @@
	1	+menu "Aspeed SoC drivers"
	2	+
	3	+config SOC_ASPEED
	4	+ def_bool y
	5	+ depends on ARCH_ASPEED \|\| COMPILE_TEST
	6	+
	7	+config ASPEED_LPC_CTRL
	8	+ depends on SOC_ASPEED && REGMAP && MFD_SYSCON
	9	+ tristate "Aspeed ast2400/2500 HOST LPC to BMC bridge control"
	10	+ ---help---
	11	+ Control Aspeed ast2400/2500 HOST LPC to BMC mappings through
	12	+ ioctl()s, the driver also provides a read/write interface to a BMC ram
	13	+ region where the host LPC read/write region can be buffered.
	14	+
	15	+config ASPEED_LPC_SNOOP
	16	+ tristate "Aspeed ast2500 HOST LPC snoop support"
	17	+ depends on SOC_ASPEED && REGMAP && MFD_SYSCON
	18	+ help
	19	+ Provides a driver to control the LPC snoop interface which
	20	+ allows the BMC to listen on and save the data written by
	21	+ the host to an arbitrary LPC I/O port.
	22	+
	23	+config ASPEED_P2A_CTRL
	24	+ depends on SOC_ASPEED && REGMAP && MFD_SYSCON
	25	+ tristate "Aspeed ast2400/2500 HOST P2A VGA MMIO to BMC bridge control"
	26	+ help
	27	+ Control Aspeed ast2400/2500 HOST P2A VGA MMIO to BMC mappings through
	28	+ ioctl()s, the driver also provides an interface for userspace mappings to
	29	+ a pre-defined region.
	30	+
	31	+endmenu

drivers/soc/aspeed/Makefile+3−0

@@ -0,0 +1,3 @@
	1	+obj-$(CONFIG_ASPEED_LPC_CTRL) += aspeed-lpc-ctrl.o
	2	+obj-$(CONFIG_ASPEED_LPC_SNOOP) += aspeed-lpc-snoop.o
	3	+obj-$(CONFIG_ASPEED_P2A_CTRL) += aspeed-p2a-ctrl.o

drivers/soc/aspeed/aspeed-lpc-ctrl.crenamed from drivers/misc/aspeed-lpc-ctrl.c+0−0

File renamed without changes.

drivers/soc/aspeed/aspeed-lpc-snoop.crenamed from drivers/misc/aspeed-lpc-snoop.c+0−0

File renamed without changes.

drivers/soc/aspeed/aspeed-p2a-ctrl.crenamed from drivers/misc/aspeed-p2a-ctrl.c+0−0

File renamed without changes.

drivers/soc/imx/Makefile+1−0

@@ -1,2 +1,3 @@
1	1	obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
2	2	obj-$(CONFIG_IMX_GPCV2_PM_DOMAINS) += gpcv2.o
	3	+obj-$(CONFIG_ARCH_MXC) += soc-imx8.o

drivers/soc/imx/gpc.c+1−3

@@ -406,7 +406,6 @@ static int imx_gpc_probe(struct platform_device *pdev) · 405 unmodified lines
406	406	const struct imx_gpc_dt_data *of_id_data = of_id->data;
407	407	struct device_node *pgc_node;
408	408	struct regmap *regmap;
409		− struct resource *res;
410	409	void __iomem *base;
411	410	int ret;
412	411
@@ -417,8 +416,7 @@ static int imx_gpc_probe(struct platform_device *pdev) · 4 unmodified lines
417	416	!pgc_node)
418	417	return 0;
419	418
420		− res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
421		− base = devm_ioremap_resource(&pdev->dev, res);
	419	+ base = devm_platform_ioremap_resource(pdev, 0);
422	420	if (IS_ERR(base))
423	421	return PTR_ERR(base);
424	422

drivers/soc/imx/gpcv2.c+15−28

@@ -136,8 +136,8 @@ static int imx_gpc_pu_pgc_sw_pxx_req(struct generic_pm_domain *genpd, · 135 unmodified lines
136	136	GPC_PU_PGC_SW_PUP_REQ : GPC_PU_PGC_SW_PDN_REQ;
137	137	const bool enable_power_control = !on;
138	138	const bool has_regulator = !IS_ERR(domain->regulator);
139		− unsigned long deadline;
140	139	int i, ret = 0;
	140	+ u32 pxx_req;
141	141
142	142	regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
143	143	domain->bits.map, domain->bits.map);
@@ -169,30 +169,19 @@ static int imx_gpc_pu_pgc_sw_pxx_req(struct generic_pm_domain *genpd, · 25 unmodified lines
169	169	* As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
170	170	* for PUP_REQ/PDN_REQ bit to be cleared
171	171	*/
172		− deadline = jiffies + msecs_to_jiffies(1);
173		− while (true) {
174		− u32 pxx_req;
175		−
176		− regmap_read(domain->regmap, offset, &pxx_req);
177		−
178		− if (!(pxx_req & domain->bits.pxx))
179		− break;
180		−
181		− if (time_after(jiffies, deadline)) {
182		− dev_err(domain->dev, "falied to command PGC\n");
183		− ret = -ETIMEDOUT;
184		− /*
185		− * If we were in a process of enabling a
186		− * domain and failed we might as well disable
187		− * the regulator we just enabled. And if it
188		− * was the opposite situation and we failed to
189		− * power down -- keep the regulator on
190		− */
191		− on = !on;
192		− break;
193		− }
194		−
195		− cpu_relax();
	172	+ ret = regmap_read_poll_timeout(domain->regmap, offset, pxx_req,
	173	+ !(pxx_req & domain->bits.pxx),
	174	+ 0, USEC_PER_MSEC);
	175	+ if (ret) {
	176	+ dev_err(domain->dev, "failed to command PGC\n");
	177	+ /*
	178	+ * If we were in a process of enabling a
	179	+ * domain and failed we might as well disable
	180	+ * the regulator we just enabled. And if it
	181	+ * was the opposite situation and we failed to
	182	+ * power down -- keep the regulator on
	183	+ */
	184	+ on = !on;
196	185	}
197	186
198	187	if (enable_power_control)
@@ -574,7 +563,6 @@ static int imx_gpcv2_probe(struct platform_device *pdev) · 375 unmodified lines
574	563	struct device *dev = &pdev->dev;
575	564	struct device_node pgc_np, np;
576	565	struct regmap *regmap;
577		− struct resource *res;
578	566	void __iomem *base;
579	567	int ret;
580	568
@@ -584,8 +572,7 @@ static int imx_gpcv2_probe(struct platform_device *pdev) · 3 unmodified lines
584	572	return -EINVAL;
585	573	}
586	574
587		− res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
588		− base = devm_ioremap_resource(dev, res);
	575	+ base = devm_platform_ioremap_resource(pdev, 0);
589	576	if (IS_ERR(base))
590	577	return PTR_ERR(base);
591	578

drivers/soc/imx/soc-imx8.c+115−0

@@ -0,0 +1,115 @@
	1	+// SPDX-License-Identifier: GPL-2.0
	2	+/*
	3	+ * Copyright 2019 NXP.
	4	+ */
	5	+
	6	+#include <linux/init.h>
	7	+#include <linux/io.h>
	8	+#include <linux/of_address.h>
	9	+#include <linux/slab.h>
	10	+#include <linux/sys_soc.h>
	11	+#include <linux/platform_device.h>
	12	+#include <linux/of.h>
	13	+
	14	+#define REV_B1 0x21
	15	+
	16	+#define IMX8MQ_SW_INFO_B1 0x40
	17	+#define IMX8MQ_SW_MAGIC_B1 0xff0055aa
	18	+
	19	+struct imx8_soc_data {
	20	+ char *name;
	21	+ u32 (*soc_revision)(void);
	22	+};
	23	+
	24	+static u32 __init imx8mq_soc_revision(void)
	25	+{
	26	+ struct device_node *np;
	27	+ void __iomem *ocotp_base;
	28	+ u32 magic;
	29	+ u32 rev = 0;
	30	+
	31	+ np = of_find_compatible_node(NULL, NULL, "fsl,imx8mq-ocotp");
	32	+ if (!np)
	33	+ goto out;
	34	+
	35	+ ocotp_base = of_iomap(np, 0);
	36	+ WARN_ON(!ocotp_base);
	37	+
	38	+ magic = readl_relaxed(ocotp_base + IMX8MQ_SW_INFO_B1);
	39	+ if (magic == IMX8MQ_SW_MAGIC_B1)
	40	+ rev = REV_B1;
	41	+
	42	+ iounmap(ocotp_base);
	43	+
	44	+out:
	45	+ of_node_put(np);
	46	+ return rev;
	47	+}
	48	+
	49	+static const struct imx8_soc_data imx8mq_soc_data = {
	50	+ .name = "i.MX8MQ",
	51	+ .soc_revision = imx8mq_soc_revision,
	52	+};
	53	+
	54	+static const struct of_device_id imx8_soc_match[] = {
	55	+ { .compatible = "fsl,imx8mq", .data = &imx8mq_soc_data, },
	56	+ { }
	57	+};
	58	+
	59	+#define imx8_revision(soc_rev) \
	60	+ soc_rev ? \
	61	+ kasprintf(GFP_KERNEL, "%d.%d", (soc_rev >> 4) & 0xf, soc_rev & 0xf) : \
	62	+ "unknown"
	63	+
	64	+static int __init imx8_soc_init(void)
	65	+{
	66	+ struct soc_device_attribute *soc_dev_attr;
	67	+ struct soc_device *soc_dev;
	68	+ struct device_node *root;
	69	+ const struct of_device_id *id;
	70	+ u32 soc_rev = 0;
	71	+ const struct imx8_soc_data *data;
	72	+ int ret;
	73	+
	74	+ soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
	75	+ if (!soc_dev_attr)
	76	+ return -ENODEV;
	77	+
	78	+ soc_dev_attr->family = "Freescale i.MX";
	79	+
	80	+ root = of_find_node_by_path("/");
	81	+ ret = of_property_read_string(root, "model", &soc_dev_attr->machine);
	82	+ if (ret)
	83	+ goto free_soc;
	84	+
	85	+ id = of_match_node(imx8_soc_match, root);
	86	+ if (!id)
	87	+ goto free_soc;
	88	+
	89	+ of_node_put(root);
	90	+
	91	+ data = id->data;
	92	+ if (data) {
	93	+ soc_dev_attr->soc_id = data->name;
	94	+ if (data->soc_revision)
	95	+ soc_rev = data->soc_revision();
	96	+ }
	97	+
	98	+ soc_dev_attr->revision = imx8_revision(soc_rev);
	99	+ if (!soc_dev_attr->revision)
	100	+ goto free_soc;
	101	+
	102	+ soc_dev = soc_device_register(soc_dev_attr);
	103	+ if (IS_ERR(soc_dev))
	104	+ goto free_rev;
	105	+
	106	+ return 0;
	107	+
	108	+free_rev:
	109	+ kfree(soc_dev_attr->revision);
	110	+free_soc:
	111	+ kfree(soc_dev_attr);
	112	+ of_node_put(root);
	113	+ return -ENODEV;
	114	+}
	115	+device_initcall(imx8_soc_init);

drivers/soc/mediatek/mtk-pmic-wrap.c+109−2

@@ -381,6 +381,10 @@ enum pwrap_regs { · 380 unmodified lines
381	381	PWRAP_EXT_GPS_AUXADC_RDATA_ADDR,
382	382	PWRAP_GPSINF_0_STA,
383	383	PWRAP_GPSINF_1_STA,
	384	+
	385	+ /* MT8516 only regs */
	386	+ PWRAP_OP_TYPE,
	387	+ PWRAP_MSB_FIRST,
384	388	};
385	389
386	390	static int mt2701_regs[] = {
@@ -852,6 +856,91 @@ static int mt8183_regs[] = { · 465 unmodified lines
852	856	[PWRAP_WACS2_VLDCLR] = 0xC28,
853	857	};
854	858
	859	+static int mt8516_regs[] = {
	860	+ [PWRAP_MUX_SEL] = 0x0,
	861	+ [PWRAP_WRAP_EN] = 0x4,
	862	+ [PWRAP_DIO_EN] = 0x8,
	863	+ [PWRAP_SIDLY] = 0xc,
	864	+ [PWRAP_RDDMY] = 0x10,
	865	+ [PWRAP_SI_CK_CON] = 0x14,
	866	+ [PWRAP_CSHEXT_WRITE] = 0x18,
	867	+ [PWRAP_CSHEXT_READ] = 0x1c,
	868	+ [PWRAP_CSLEXT_START] = 0x20,
	869	+ [PWRAP_CSLEXT_END] = 0x24,
	870	+ [PWRAP_STAUPD_PRD] = 0x28,
	871	+ [PWRAP_STAUPD_GRPEN] = 0x2c,
	872	+ [PWRAP_STAUPD_MAN_TRIG] = 0x40,
	873	+ [PWRAP_STAUPD_STA] = 0x44,
	874	+ [PWRAP_WRAP_STA] = 0x48,
	875	+ [PWRAP_HARB_INIT] = 0x4c,
	876	+ [PWRAP_HARB_HPRIO] = 0x50,
	877	+ [PWRAP_HIPRIO_ARB_EN] = 0x54,
	878	+ [PWRAP_HARB_STA0] = 0x58,
	879	+ [PWRAP_HARB_STA1] = 0x5c,
	880	+ [PWRAP_MAN_EN] = 0x60,
	881	+ [PWRAP_MAN_CMD] = 0x64,
	882	+ [PWRAP_MAN_RDATA] = 0x68,
	883	+ [PWRAP_MAN_VLDCLR] = 0x6c,
	884	+ [PWRAP_WACS0_EN] = 0x70,
	885	+ [PWRAP_INIT_DONE0] = 0x74,
	886	+ [PWRAP_WACS0_CMD] = 0x78,
	887	+ [PWRAP_WACS0_RDATA] = 0x7c,
	888	+ [PWRAP_WACS0_VLDCLR] = 0x80,
	889	+ [PWRAP_WACS1_EN] = 0x84,
	890	+ [PWRAP_INIT_DONE1] = 0x88,
	891	+ [PWRAP_WACS1_CMD] = 0x8c,
	892	+ [PWRAP_WACS1_RDATA] = 0x90,
	893	+ [PWRAP_WACS1_VLDCLR] = 0x94,
	894	+ [PWRAP_WACS2_EN] = 0x98,
	895	+ [PWRAP_INIT_DONE2] = 0x9c,
	896	+ [PWRAP_WACS2_CMD] = 0xa0,
	897	+ [PWRAP_WACS2_RDATA] = 0xa4,
	898	+ [PWRAP_WACS2_VLDCLR] = 0xa8,
	899	+ [PWRAP_INT_EN] = 0xac,
	900	+ [PWRAP_INT_FLG_RAW] = 0xb0,
	901	+ [PWRAP_INT_FLG] = 0xb4,
	902	+ [PWRAP_INT_CLR] = 0xb8,
	903	+ [PWRAP_SIG_ADR] = 0xbc,
	904	+ [PWRAP_SIG_MODE] = 0xc0,
	905	+ [PWRAP_SIG_VALUE] = 0xc4,
	906	+ [PWRAP_SIG_ERRVAL] = 0xc8,
	907	+ [PWRAP_CRC_EN] = 0xcc,
	908	+ [PWRAP_TIMER_EN] = 0xd0,
	909	+ [PWRAP_TIMER_STA] = 0xd4,
	910	+ [PWRAP_WDT_UNIT] = 0xd8,
	911	+ [PWRAP_WDT_SRC_EN] = 0xdc,
	912	+ [PWRAP_WDT_FLG] = 0xe0,
	913	+ [PWRAP_DEBUG_INT_SEL] = 0xe4,
	914	+ [PWRAP_DVFS_ADR0] = 0xe8,
	915	+ [PWRAP_DVFS_WDATA0] = 0xec,
	916	+ [PWRAP_DVFS_ADR1] = 0xf0,
	917	+ [PWRAP_DVFS_WDATA1] = 0xf4,
	918	+ [PWRAP_DVFS_ADR2] = 0xf8,
	919	+ [PWRAP_DVFS_WDATA2] = 0xfc,
	920	+ [PWRAP_DVFS_ADR3] = 0x100,
	921	+ [PWRAP_DVFS_WDATA3] = 0x104,
	922	+ [PWRAP_DVFS_ADR4] = 0x108,
	923	+ [PWRAP_DVFS_WDATA4] = 0x10c,
	924	+ [PWRAP_DVFS_ADR5] = 0x110,
	925	+ [PWRAP_DVFS_WDATA5] = 0x114,
	926	+ [PWRAP_DVFS_ADR6] = 0x118,
	927	+ [PWRAP_DVFS_WDATA6] = 0x11c,
	928	+ [PWRAP_DVFS_ADR7] = 0x120,
	929	+ [PWRAP_DVFS_WDATA7] = 0x124,
	930	+ [PWRAP_SPMINF_STA] = 0x128,
	931	+ [PWRAP_CIPHER_KEY_SEL] = 0x12c,
	932	+ [PWRAP_CIPHER_IV_SEL] = 0x130,
	933	+ [PWRAP_CIPHER_EN] = 0x134,
	934	+ [PWRAP_CIPHER_RDY] = 0x138,
	935	+ [PWRAP_CIPHER_MODE] = 0x13c,
	936	+ [PWRAP_CIPHER_SWRST] = 0x140,
	937	+ [PWRAP_DCM_EN] = 0x144,
	938	+ [PWRAP_DCM_DBC_PRD] = 0x148,
	939	+ [PWRAP_SW_RST] = 0x168,
	940	+ [PWRAP_OP_TYPE] = 0x16c,
	941	+ [PWRAP_MSB_FIRST] = 0x170,
	942	+};
	943	+
855	944	enum pmic_type {
856	945	PMIC_MT6323,
857	946	PMIC_MT6351,
@@ -869,6 +958,7 @@ enum pwrap_type { · 11 unmodified lines
869	958	PWRAP_MT8135,
870	959	PWRAP_MT8173,
871	960	PWRAP_MT8183,
	961	+ PWRAP_MT8516,
872	962	};
873	963
874	964	struct pmic_wrapper;
@@ -1281,7 +1371,7 @@ static bool pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp) · 406 unmodified lines
1281	1371	static int pwrap_init_cipher(struct pmic_wrapper *wrp)
1282	1372	{
1283	1373	int ret;
1284		− u32 rdata;
	1374	+ u32 rdata = 0;
1285	1375
1286	1376	pwrap_writel(wrp, 0x1, PWRAP_CIPHER_SWRST);
1287	1377	pwrap_writel(wrp, 0x0, PWRAP_CIPHER_SWRST);
@@ -1297,6 +1387,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp) · 9 unmodified lines
1297	1387	case PWRAP_MT6765:
1298	1388	case PWRAP_MT6797:
1299	1389	case PWRAP_MT8173:
	1390	+ case PWRAP_MT8516:
1300	1391	pwrap_writel(wrp, 1, PWRAP_CIPHER_EN);
1301	1392	break;
1302	1393	case PWRAP_MT7622:
@@ -1478,7 +1569,8 @@ static int pwrap_init(struct pmic_wrapper *wrp) · 175 unmodified lines
1478	1569	{
1479	1570	int ret;
1480	1571
1481		− reset_control_reset(wrp->rstc);
	1572	+ if (wrp->rstc)
	1573	+ reset_control_reset(wrp->rstc);
1482	1574	if (wrp->rstc_bridge)
1483	1575	reset_control_reset(wrp->rstc_bridge);
1484	1576
@@ -1764,6 +1856,18 @@ static const struct pmic_wrapper_type pwrap_mt8183 = { · 279 unmodified lines
1764	1856	.init_soc_specific = pwrap_mt8183_init_soc_specific,
1765	1857	};
1766	1858
	1859	+static struct pmic_wrapper_type pwrap_mt8516 = {
	1860	+ .regs = mt8516_regs,
	1861	+ .type = PWRAP_MT8516,
	1862	+ .arb_en_all = 0xff,
	1863	+ .int_en_all = ~(u32)(BIT(31) \| BIT(2)),
	1864	+ .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
	1865	+ .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
	1866	+ .caps = PWRAP_CAP_DCM,
	1867	+ .init_reg_clock = pwrap_mt2701_init_reg_clock,
	1868	+ .init_soc_specific = NULL,
	1869	+};
	1870	+
1767	1871	static const struct of_device_id of_pwrap_match_tbl[] = {
1768	1872	{
1769	1873	.compatible = "mediatek,mt2701-pwrap",
@@ -1786,6 +1890,9 @@ static const struct of_device_id of_pwrap_match_tbl[] = { · 16 unmodified lines
1786	1890	}, {
1787	1891	.compatible = "mediatek,mt8183-pwrap",
1788	1892	.data = &pwrap_mt8183,
	1893	+ }, {
	1894	+ .compatible = "mediatek,mt8516-pwrap",
	1895	+ .data = &pwrap_mt8516,
1789	1896	}, {
1790	1897	/* sentinel */
1791	1898	}

drivers/soc/qcom/cmd-db.c+2−2

@@ -248,8 +248,8 @@ static int cmd_db_dev_probe(struct platform_device *pdev) · 247 unmodified lines
248	248	}
249	249
250	250	cmd_db_header = memremap(rmem->base, rmem->size, MEMREMAP_WB);
251		− if (IS_ERR_OR_NULL(cmd_db_header)) {
252		− ret = PTR_ERR(cmd_db_header);
	251	+ if (!cmd_db_header) {
	252	+ ret = -ENOMEM;
253	253	cmd_db_header = NULL;
254	254	return ret;
255	255	}

drivers/soc/qcom/qmi_interface.c+2−5

@@ -345,8 +345,7 @@ int qmi_txn_wait(struct qmi_txn *txn, unsigned long timeout) · 344 unmodified lines
345	345	struct qmi_handle *qmi = txn->qmi;
346	346	int ret;
347	347
348		− ret = wait_for_completion_interruptible_timeout(&txn->completion,
349		− timeout);
	348	+ ret = wait_for_completion_timeout(&txn->completion, timeout);
350	349
351	350	mutex_lock(&qmi->txn_lock);
352	351	mutex_lock(&txn->lock);
@@ -354,9 +353,7 @@ int qmi_txn_wait(struct qmi_txn *txn, unsigned long timeout) · 1 unmodified line
354	353	mutex_unlock(&txn->lock);
355	354	mutex_unlock(&qmi->txn_lock);
356	355
357		− if (ret < 0)
358		− return ret;
359		− else if (ret == 0)
	356	+ if (ret == 0)
360	357	return -ETIMEDOUT;
361	358	else
362	359	return txn->result;

drivers/soc/qcom/rmtfs_mem.c+21−0

@@ -137,6 +137,26 @@ static struct class rmtfs_class = { · 136 unmodified lines
137	137	.name = "rmtfs",
138	138	};
139	139
	140	+static int qcom_rmtfs_mem_mmap(struct file filep, struct vm_area_struct vma)
	141	+{
	142	+ struct qcom_rmtfs_mem *rmtfs_mem = filep->private_data;
	143	+
	144	+ if (vma->vm_end - vma->vm_start > rmtfs_mem->size) {
	145	+ dev_dbg(&rmtfs_mem->dev,
	146	+ "vm_end[%lu] - vm_start[%lu] [%lu] > mem->size[%pa]\n",
	147	+ vma->vm_end, vma->vm_start,
	148	+ (vma->vm_end - vma->vm_start), &rmtfs_mem->size);
	149	+ return -EINVAL;
	150	+ }
	151	+
	152	+ vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
	153	+ return remap_pfn_range(vma,
	154	+ vma->vm_start,
	155	+ rmtfs_mem->addr >> PAGE_SHIFT,
	156	+ vma->vm_end - vma->vm_start,
	157	+ vma->vm_page_prot);
	158	+}
	159	+
140	160	static const struct file_operations qcom_rmtfs_mem_fops = {
141	161	.owner = THIS_MODULE,
142	162	.open = qcom_rmtfs_mem_open,
@@ -144,6 +164,7 @@ static const struct file_operations qcom_rmtfs_mem_fops = { · 1 unmodified line
144	164	.write = qcom_rmtfs_mem_write,
145	165	.release = qcom_rmtfs_mem_release,
146	166	.llseek = default_llseek,
	167	+ .mmap = qcom_rmtfs_mem_mmap,
147	168	};
148	169
149	170	static void qcom_rmtfs_mem_release_device(struct device *dev)

drivers/soc/qcom/rpmh-rsc.c+1−1

@@ -459,7 +459,7 @@ static int find_slots(struct tcs_group tcs, const struct tcs_request msg, · 458 unmodified lines
459	459	do {
460	460	slot = bitmap_find_next_zero_area(tcs->slots, MAX_TCS_SLOTS,
461	461	i, msg->num_cmds, 0);
462		− if (slot == tcs->num_tcs * tcs->ncpt)
	462	+ if (slot >= tcs->num_tcs * tcs->ncpt)
463	463	return -ENOMEM;
464	464	i += tcs->ncpt;
465	465	} while (slot + msg->num_cmds - 1 >= i);

drivers/soc/renesas/renesas-soc.c+3−0

@@ -335,6 +335,9 @@ static int __init renesas_soc_init(void) · 334 unmodified lines
335	335	/* R-Car M3-W ES1.1 incorrectly identifies as ES2.0 */
336	336	if ((product & 0x7fff) == 0x5210)
337	337	product ^= 0x11;
	338	+ /* R-Car M3-W ES1.3 incorrectly identifies as ES2.1 */
	339	+ if ((product & 0x7fff) == 0x5211)
	340	+ product ^= 0x12;
338	341	if (soc->id && ((product >> 8) & 0xff) != soc->id) {
339	342	pr_warn("SoC mismatch (product = 0x%x)\n", product);
340	343	return -ENODEV;

drivers/soc/rockchip/grf.c+2−0

@@ -66,9 +66,11 @@ static const struct rockchip_grf_info rk3228_grf __initconst = { · 65 unmodified lines
66	66	};
67	67
68	68	#define RK3288_GRF_SOC_CON0 0x244
	69	+#define RK3288_GRF_SOC_CON2 0x24c
69	70
70	71	static const struct rockchip_grf_value rk3288_defaults[] __initconst = {
71	72	{ "jtag switching", RK3288_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 12) },
	73	+ { "pwm select", RK3288_GRF_SOC_CON2, HIWORD_UPDATE(1, 1, 0) },
72	74	};
73	75
74	76	static const struct rockchip_grf_info rk3288_grf __initconst = {

drivers/soc/tegra/pmc.c+134−37

@@ -268,6 +268,14 @@ static const char * const tegra186_reset_levels[] = { · 267 unmodified lines
268	268	};
269	269
270	270	static const char * const tegra30_reset_sources[] = {
	271	+ "POWER_ON_RESET",
	272	+ "WATCHDOG",
	273	+ "SENSOR",
	274	+ "SW_MAIN",
	275	+ "LP0"
	276	+};
	277	+
	278	+static const char * const tegra210_reset_sources[] = {
271	279	"POWER_ON_RESET",
272	280	"WATCHDOG",
273	281	"SENSOR",
@@ -656,10 +664,15 @@ static int tegra_genpd_power_on(struct generic_pm_domain *domain) · 382 unmodified lines
656	664	int err;
657	665
658	666	err = tegra_powergate_power_up(pg, true);
659		− if (err)
	667	+ if (err) {
660	668	dev_err(dev, "failed to turn on PM domain %s: %d\n",
661	669	pg->genpd.name, err);
	670	+ goto out;
	671	+ }
	672	+
	673	+ reset_control_release(pg->reset);
662	674
	675	+out:
663	676	return err;
664	677	}
665	678
@@ -669,10 +682,18 @@ static int tegra_genpd_power_off(struct generic_pm_domain *domain) · 3 unmodified lines
669	682	struct device *dev = pg->pmc->dev;
670	683	int err;
671	684
	685	+ err = reset_control_acquire(pg->reset);
	686	+ if (err < 0) {
	687	+ pr_err("failed to acquire resets: %d\n", err);
	688	+ return err;
	689	+ }
	690	+
672	691	err = tegra_powergate_power_down(pg);
673		− if (err)
	692	+ if (err) {
674	693	dev_err(dev, "failed to turn off PM domain %s: %d\n",
675	694	pg->genpd.name, err);
	695	+ reset_control_release(pg->reset);
	696	+ }
676	697
677	698	return err;
678	699	}
@@ -937,38 +958,53 @@ static int tegra_powergate_of_get_resets(struct tegra_powergate *pg, · 258 unmodified lines
937	958	struct device *dev = pg->pmc->dev;
938	959	int err;
939	960
940		− pg->reset = of_reset_control_array_get_exclusive(np);
	961	+ pg->reset = of_reset_control_array_get_exclusive_released(np);
941	962	if (IS_ERR(pg->reset)) {
942	963	err = PTR_ERR(pg->reset);
943	964	dev_err(dev, "failed to get device resets: %d\n", err);
944	965	return err;
945	966	}
946	967
947		− if (off)
	968	+ err = reset_control_acquire(pg->reset);
	969	+ if (err < 0) {
	970	+ pr_err("failed to acquire resets: %d\n", err);
	971	+ goto out;
	972	+ }
	973	+
	974	+ if (off) {
948	975	err = reset_control_assert(pg->reset);
949		− else
	976	+ } else {
950	977	err = reset_control_deassert(pg->reset);
	978	+ if (err < 0)
	979	+ goto out;
951	980
952		− if (err)
	981	+ reset_control_release(pg->reset);
	982	+ }
	983	+
	984	+out:
	985	+ if (err) {
	986	+ reset_control_release(pg->reset);
953	987	reset_control_put(pg->reset);
	988	+ }
954	989
955	990	return err;
956	991	}
957	992
958		−static void tegra_powergate_add(struct tegra_pmc pmc, struct device_node np)
	993	+static int tegra_powergate_add(struct tegra_pmc pmc, struct device_node np)
959	994	{
960	995	struct device *dev = pmc->dev;
961	996	struct tegra_powergate *pg;
962		− int id, err;
	997	+ int id, err = 0;
963	998	bool off;
964	999
965	1000	pg = kzalloc(sizeof(*pg), GFP_KERNEL);
966	1001	if (!pg)
967		− return;
	1002	+ return -ENOMEM;
968	1003
969	1004	id = tegra_powergate_lookup(pmc, np->name);
970	1005	if (id < 0) {
971	1006	dev_err(dev, "powergate lookup failed for %pOFn: %d\n", np, id);
	1007	+ err = -ENODEV;
972	1008	goto free_mem;
973	1009	}
974	1010
@@ -1021,7 +1057,7 @@ static void tegra_powergate_add(struct tegra_pmc pmc, struct device_node np) · 46 unmodified lines
1021	1057
1022	1058	dev_dbg(dev, "added PM domain %s\n", pg->genpd.name);
1023	1059
1024		− return;
	1060	+ return 0;
1025	1061
1026	1062	remove_genpd:
1027	1063	pm_genpd_remove(&pg->genpd);
@@ -1040,25 +1076,67 @@ set_available: · 12 unmodified lines
1040	1076
1041	1077	free_mem:
1042	1078	kfree(pg);
	1079	+
	1080	+ return err;
1043	1081	}
1044	1082
1045		−static void tegra_powergate_init(struct tegra_pmc *pmc,
1046		− struct device_node *parent)
	1083	+static int tegra_powergate_init(struct tegra_pmc *pmc,
	1084	+ struct device_node *parent)
1047	1085	{
1048	1086	struct device_node np, child;
1049		− unsigned int i;
	1087	+ int err = 0;
	1088	+
	1089	+ np = of_get_child_by_name(parent, "powergates");
	1090	+ if (!np)
	1091	+ return 0;
	1092	+
	1093	+ for_each_child_of_node(np, child) {
	1094	+ err = tegra_powergate_add(pmc, child);
	1095	+ if (err < 0) {
	1096	+ of_node_put(child);
	1097	+ break;
	1098	+ }
	1099	+ }
	1100	+
	1101	+ of_node_put(np);
	1102	+
	1103	+ return err;
	1104	+}
	1105	+
	1106	+static void tegra_powergate_remove(struct generic_pm_domain *genpd)
	1107	+{
	1108	+ struct tegra_powergate *pg = to_powergate(genpd);
	1109	+
	1110	+ reset_control_put(pg->reset);
	1111	+
	1112	+ while (pg->num_clks--)
	1113	+ clk_put(pg->clks[pg->num_clks]);
	1114	+
	1115	+ kfree(pg->clks);
1050	1116
1051		− /* Create a bitmap of the available and valid partitions */
1052		− for (i = 0; i < pmc->soc->num_powergates; i++)
1053		− if (pmc->soc->powergates[i])
1054		− set_bit(i, pmc->powergates_available);
	1117	+ set_bit(pg->id, pmc->powergates_available);
	1118	+
	1119	+ kfree(pg);
	1120	+}
	1121	+
	1122	+static void tegra_powergate_remove_all(struct device_node *parent)
	1123	+{
	1124	+ struct generic_pm_domain *genpd;
	1125	+ struct device_node np, child;
1055	1126
1056	1127	np = of_get_child_by_name(parent, "powergates");
1057	1128	if (!np)
1058	1129	return;
1059	1130
1060		− for_each_child_of_node(np, child)
1061		− tegra_powergate_add(pmc, child);
	1131	+ for_each_child_of_node(np, child) {
	1132	+ of_genpd_del_provider(child);
	1133	+
	1134	+ genpd = of_genpd_remove_last(child);
	1135	+ if (IS_ERR(genpd))
	1136	+ continue;
	1137	+
	1138	+ tegra_powergate_remove(genpd);
	1139	+ }
1062	1140
1063	1141	of_node_put(np);
1064	1142	}
@@ -1709,13 +1787,16 @@ static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc) · 644 unmodified lines
1709	1787	static ssize_t reset_reason_show(struct device *dev,
1710	1788	struct device_attribute attr, char buf)
1711	1789	{
1712		− u32 value, rst_src;
	1790	+ u32 value;
1713	1791
1714	1792	value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
1715		− rst_src = (value & pmc->soc->regs->rst_source_mask) >>
1716		− pmc->soc->regs->rst_source_shift;
	1793	+ value &= pmc->soc->regs->rst_source_mask;
	1794	+ value >>= pmc->soc->regs->rst_source_shift;
	1795	+
	1796	+ if (WARN_ON(value >= pmc->soc->num_reset_sources))
	1797	+ return sprintf(buf, "%s\n", "UNKNOWN");
1717	1798
1718		− return sprintf(buf, "%s\n", pmc->soc->reset_sources[rst_src]);
	1799	+ return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]);
1719	1800	}
1720	1801
1721	1802	static DEVICE_ATTR_RO(reset_reason);
@@ -1723,13 +1804,16 @@ static DEVICE_ATTR_RO(reset_reason); · 1 unmodified line
1723	1804	static ssize_t reset_level_show(struct device *dev,
1724	1805	struct device_attribute attr, char buf)
1725	1806	{
1726		− u32 value, rst_lvl;
	1807	+ u32 value;
1727	1808
1728	1809	value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
1729		− rst_lvl = (value & pmc->soc->regs->rst_level_mask) >>
1730		− pmc->soc->regs->rst_level_shift;
	1810	+ value &= pmc->soc->regs->rst_level_mask;
	1811	+ value >>= pmc->soc->regs->rst_level_shift;
1731	1812
1732		− return sprintf(buf, "%s\n", pmc->soc->reset_levels[rst_lvl]);
	1813	+ if (WARN_ON(value >= pmc->soc->num_reset_levels))
	1814	+ return sprintf(buf, "%s\n", "UNKNOWN");
	1815	+
	1816	+ return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]);
1733	1817	}
1734	1818
1735	1819	static DEVICE_ATTR_RO(reset_level);
@@ -1999,7 +2083,7 @@ static int tegra_pmc_probe(struct platform_device *pdev) · 263 unmodified lines
1999	2083	if (IS_ENABLED(CONFIG_DEBUG_FS)) {
2000	2084	err = tegra_powergate_debugfs_init();
2001	2085	if (err < 0)
2002		− return err;
	2086	+ goto cleanup_sysfs;
2003	2087	}
2004	2088
2005	2089	err = register_restart_handler(&tegra_pmc_restart_handler);
@@ -2013,9 +2097,13 @@ static int tegra_pmc_probe(struct platform_device *pdev) · 7 unmodified lines
2013	2097	if (err)
2014	2098	goto cleanup_restart_handler;
2015	2099
	2100	+ err = tegra_powergate_init(pmc, pdev->dev.of_node);
	2101	+ if (err < 0)
	2102	+ goto cleanup_powergates;
	2103	+
2016	2104	err = tegra_pmc_irq_init(pmc);
2017	2105	if (err < 0)
2018		− goto cleanup_restart_handler;
	2106	+ goto cleanup_powergates;
2019	2107
2020	2108	mutex_lock(&pmc->powergates_lock);
2021	2109	iounmap(pmc->base);
@@ -2026,10 +2114,15 @@ static int tegra_pmc_probe(struct platform_device *pdev) · 4 unmodified lines
2026	2114
2027	2115	return 0;
2028	2116
	2117	+cleanup_powergates:
	2118	+ tegra_powergate_remove_all(pdev->dev.of_node);
2029	2119	cleanup_restart_handler:
2030	2120	unregister_restart_handler(&tegra_pmc_restart_handler);
2031	2121	cleanup_debugfs:
2032	2122	debugfs_remove(pmc->debugfs);
	2123	+cleanup_sysfs:
	2124	+ device_remove_file(&pdev->dev, &dev_attr_reset_reason);
	2125	+ device_remove_file(&pdev->dev, &dev_attr_reset_level);
2033	2126	return err;
2034	2127	}
2035	2128
@@ -2185,7 +2278,7 @@ static const struct tegra_pmc_soc tegra30_pmc_soc = { · 149 unmodified lines
2185	2278	.init = tegra20_pmc_init,
2186	2279	.setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
2187	2280	.reset_sources = tegra30_reset_sources,
2188		− .num_reset_sources = 5,
	2281	+ .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
2189	2282	.reset_levels = NULL,
2190	2283	.num_reset_levels = 0,
2191	2284	};
@@ -2236,7 +2329,7 @@ static const struct tegra_pmc_soc tegra114_pmc_soc = { · 44 unmodified lines
2236	2329	.init = tegra20_pmc_init,
2237	2330	.setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
2238	2331	.reset_sources = tegra30_reset_sources,
2239		− .num_reset_sources = 5,
	2332	+ .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
2240	2333	.reset_levels = NULL,
2241	2334	.num_reset_levels = 0,
2242	2335	};
@@ -2347,7 +2440,7 @@ static const struct tegra_pmc_soc tegra124_pmc_soc = { · 104 unmodified lines
2347	2440	.init = tegra20_pmc_init,
2348	2441	.setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
2349	2442	.reset_sources = tegra30_reset_sources,
2350		− .num_reset_sources = 5,
	2443	+ .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
2351	2444	.reset_levels = NULL,
2352	2445	.num_reset_levels = 0,
2353	2446	};
@@ -2452,8 +2545,8 @@ static const struct tegra_pmc_soc tegra210_pmc_soc = { · 98 unmodified lines
2452	2545	.regs = &tegra20_pmc_regs,
2453	2546	.init = tegra20_pmc_init,
2454	2547	.setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
2455		− .reset_sources = tegra30_reset_sources,
2456		− .num_reset_sources = 5,
	2548	+ .reset_sources = tegra210_reset_sources,
	2549	+ .num_reset_sources = ARRAY_SIZE(tegra210_reset_sources),
2457	2550	.reset_levels = NULL,
2458	2551	.num_reset_levels = 0,
2459	2552	};
@@ -2578,9 +2671,9 @@ static const struct tegra_pmc_soc tegra186_pmc_soc = { · 118 unmodified lines
2578	2671	.init = NULL,
2579	2672	.setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
2580	2673	.reset_sources = tegra186_reset_sources,
2581		− .num_reset_sources = 14,
	2674	+ .num_reset_sources = ARRAY_SIZE(tegra186_reset_sources),
2582	2675	.reset_levels = tegra186_reset_levels,
2583		− .num_reset_levels = 3,
	2676	+ .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
2584	2677	.num_wake_events = ARRAY_SIZE(tegra186_wake_events),
2585	2678	.wake_events = tegra186_wake_events,
2586	2679	};
@@ -2719,6 +2812,7 @@ static int __init tegra_pmc_early_init(void) · 132 unmodified lines
2719	2812	const struct of_device_id *match;
2720	2813	struct device_node *np;
2721	2814	struct resource regs;
	2815	+ unsigned int i;
2722	2816	bool invert;
2723	2817
2724	2818	mutex_init(&pmc->powergates_lock);
@@ -2775,7 +2869,10 @@ static int __init tegra_pmc_early_init(void) · 50 unmodified lines
2775	2869	if (pmc->soc->maybe_tz_only)
2776	2870	pmc->tz_only = tegra_pmc_detect_tz_only(pmc);
2777	2871
2778		− tegra_powergate_init(pmc, np);
	2872	+ /* Create a bitmap of the available and valid partitions */
	2873	+ for (i = 0; i < pmc->soc->num_powergates; i++)
	2874	+ if (pmc->soc->powergates[i])
	2875	+ set_bit(i, pmc->powergates_available);
2779	2876
2780	2877	/*
2781	2878	* Invert the interrupt polarity if a PMC device tree node

drivers/soc/ti/Kconfig+3−2

@@ -45,11 +45,12 @@ config KEYSTONE_NAVIGATOR_DMA · 44 unmodified lines
45	45	config AMX3_PM
46	46	tristate "AMx3 Power Management"
47	47	depends on SOC_AM33XX \|\| SOC_AM43XX
48		− depends on WKUP_M3_IPC && TI_EMIF_SRAM && SRAM
	48	+ depends on WKUP_M3_IPC && TI_EMIF_SRAM && SRAM && RTC_DRV_OMAP
49	49	help
50	50	Enable power management on AM335x and AM437x. Required for suspend to mem
51	51	and standby states on both AM335x and AM437x platforms and for deeper cpuidle
52		− c-states on AM335x.
	52	+ c-states on AM335x. Also required for rtc and ddr in self-refresh low
	53	+ power mode on AM437x platforms.
53	54
54	55	config WKUP_M3_IPC
55	56	tristate "TI AMx3 Wkup-M3 IPC Driver"

drivers/soc/ti/pm33xx.c+223−50

@@ -6,6 +6,7 @@ · 5 unmodified lines
6	6	* Vaibhav Bedia, Dave Gerlach
7	7	*/
8	8
	9	+#include <linux/clk.h>
9	10	#include <linux/cpu.h>
10	11	#include <linux/err.h>
11	12	#include <linux/genalloc.h>
@@ -13,9 +14,12 @@ · 1 unmodified line
13	14	#include <linux/init.h>
14	15	#include <linux/io.h>
15	16	#include <linux/module.h>
	17	+#include <linux/nvmem-consumer.h>
16	18	#include <linux/of.h>
17	19	#include <linux/platform_data/pm33xx.h>
18	20	#include <linux/platform_device.h>
	21	+#include <linux/rtc.h>
	22	+#include <linux/rtc/rtc-omap.h>
19	23	#include <linux/sizes.h>
20	24	#include <linux/sram.h>
21	25	#include <linux/suspend.h>
@@ -29,33 +33,162 @@ · 7 unmodified lines
29	33	#define AMX3_PM_SRAM_SYMBOL_OFFSET(sym) ((unsigned long)(sym) - \
30	34	(unsigned long)pm_sram->do_wfi)
31	35
	36	+#define RTC_SCRATCH_RESUME_REG 0
	37	+#define RTC_SCRATCH_MAGIC_REG 1
	38	+#define RTC_REG_BOOT_MAGIC 0x8cd0 /* RTC */
	39	+#define GIC_INT_SET_PENDING_BASE 0x200
	40	+#define AM43XX_GIC_DIST_BASE 0x48241000
	41	+
	42	+static u32 rtc_magic_val;
	43	+
32	44	static int (*am33xx_do_wfi_sram)(unsigned long unused);
33	45	static phys_addr_t am33xx_do_wfi_sram_phys;
34	46
35	47	static struct gen_pool sram_pool, sram_pool_data;
36	48	static unsigned long ocmcram_location, ocmcram_location_data;
37	49
	50	+static struct rtc_device *omap_rtc;
	51	+static void __iomem *gic_dist_base;
	52	+
38	53	static struct am33xx_pm_platform_data *pm_ops;
39	54	static struct am33xx_pm_sram_addr *pm_sram;
40	55
41	56	static struct device *pm33xx_dev;
42	57	static struct wkup_m3_ipc *m3_ipc;
43	58
	59	+#ifdef CONFIG_SUSPEND
	60	+static int rtc_only_idle;
	61	+static int retrigger_irq;
44	62	static unsigned long suspend_wfi_flags;
45	63
	64	+static struct wkup_m3_wakeup_src wakeup_src = {.irq_nr = 0,
	65	+ .src = "Unknown",
	66	+};
	67	+
	68	+static struct wkup_m3_wakeup_src rtc_alarm_wakeup = {
	69	+ .irq_nr = 108, .src = "RTC Alarm",
	70	+};
	71	+
	72	+static struct wkup_m3_wakeup_src rtc_ext_wakeup = {
	73	+ .irq_nr = 0, .src = "Ext wakeup",
	74	+};
	75	+#endif
	76	+
46	77	static u32 sram_suspend_address(unsigned long addr)
47	78	{
48	79	return ((unsigned long)am33xx_do_wfi_sram +
49	80	AMX3_PM_SRAM_SYMBOL_OFFSET(addr));
50	81	}
51	82
	83	+static int am33xx_push_sram_idle(void)
	84	+{
	85	+ struct am33xx_pm_ro_sram_data ro_sram_data;
	86	+ int ret;
	87	+ u32 table_addr, ro_data_addr;
	88	+ void *copy_addr;
	89	+
	90	+ ro_sram_data.amx3_pm_sram_data_virt = ocmcram_location_data;
	91	+ ro_sram_data.amx3_pm_sram_data_phys =
	92	+ gen_pool_virt_to_phys(sram_pool_data, ocmcram_location_data);
	93	+ ro_sram_data.rtc_base_virt = pm_ops->get_rtc_base_addr();
	94	+
	95	+ /* Save physical address to calculate resume offset during pm init */
	96	+ am33xx_do_wfi_sram_phys = gen_pool_virt_to_phys(sram_pool,
	97	+ ocmcram_location);
	98	+
	99	+ am33xx_do_wfi_sram = sram_exec_copy(sram_pool, (void *)ocmcram_location,
	100	+ pm_sram->do_wfi,
	101	+ *pm_sram->do_wfi_sz);
	102	+ if (!am33xx_do_wfi_sram) {
	103	+ dev_err(pm33xx_dev,
	104	+ "PM: %s: am33xx_do_wfi copy to sram failed\n",
	105	+ __func__);
	106	+ return -ENODEV;
	107	+ }
	108	+
	109	+ table_addr =
	110	+ sram_suspend_address((unsigned long)pm_sram->emif_sram_table);
	111	+ ret = ti_emif_copy_pm_function_table(sram_pool, (void *)table_addr);
	112	+ if (ret) {
	113	+ dev_dbg(pm33xx_dev,
	114	+ "PM: %s: EMIF function copy failed\n", __func__);
	115	+ return -EPROBE_DEFER;
	116	+ }
	117	+
	118	+ ro_data_addr =
	119	+ sram_suspend_address((unsigned long)pm_sram->ro_sram_data);
	120	+ copy_addr = sram_exec_copy(sram_pool, (void *)ro_data_addr,
	121	+ &ro_sram_data,
	122	+ sizeof(ro_sram_data));
	123	+ if (!copy_addr) {
	124	+ dev_err(pm33xx_dev,
	125	+ "PM: %s: ro_sram_data copy to sram failed\n",
	126	+ __func__);
	127	+ return -ENODEV;
	128	+ }
	129	+
	130	+ return 0;
	131	+}
	132	+
	133	+static int __init am43xx_map_gic(void)
	134	+{
	135	+ gic_dist_base = ioremap(AM43XX_GIC_DIST_BASE, SZ_4K);
	136	+
	137	+ if (!gic_dist_base)
	138	+ return -ENOMEM;
	139	+
	140	+ return 0;
	141	+}
	142	+
52	143	#ifdef CONFIG_SUSPEND
	144	+struct wkup_m3_wakeup_src rtc_wake_src(void)
	145	+{
	146	+ u32 i;
	147	+
	148	+ i = __raw_readl(pm_ops->get_rtc_base_addr() + 0x44) & 0x40;
	149	+
	150	+ if (i) {
	151	+ retrigger_irq = rtc_alarm_wakeup.irq_nr;
	152	+ return rtc_alarm_wakeup;
	153	+ }
	154	+
	155	+ retrigger_irq = rtc_ext_wakeup.irq_nr;
	156	+
	157	+ return rtc_ext_wakeup;
	158	+}
	159	+
	160	+int am33xx_rtc_only_idle(unsigned long wfi_flags)
	161	+{
	162	+ omap_rtc_power_off_program(&omap_rtc->dev);
	163	+ am33xx_do_wfi_sram(wfi_flags);
	164	+ return 0;
	165	+}
	166	+
53	167	static int am33xx_pm_suspend(suspend_state_t suspend_state)
54	168	{
55	169	int i, ret = 0;
56	170
57		− ret = pm_ops->soc_suspend((unsigned long)suspend_state,
58		− am33xx_do_wfi_sram, suspend_wfi_flags);
	171	+ if (suspend_state == PM_SUSPEND_MEM &&
	172	+ pm_ops->check_off_mode_enable()) {
	173	+ pm_ops->prepare_rtc_suspend();
	174	+ pm_ops->save_context();
	175	+ suspend_wfi_flags \|= WFI_FLAG_RTC_ONLY;
	176	+ clk_save_context();
	177	+ ret = pm_ops->soc_suspend(suspend_state, am33xx_rtc_only_idle,
	178	+ suspend_wfi_flags);
	179	+
	180	+ suspend_wfi_flags &= ~WFI_FLAG_RTC_ONLY;
	181	+
	182	+ if (!ret) {
	183	+ clk_restore_context();
	184	+ pm_ops->restore_context();
	185	+ m3_ipc->ops->set_rtc_only(m3_ipc);
	186	+ am33xx_push_sram_idle();
	187	+ }
	188	+ } else {
	189	+ ret = pm_ops->soc_suspend(suspend_state, am33xx_do_wfi_sram,
	190	+ suspend_wfi_flags);
	191	+ }
59	192
60	193	if (ret) {
61	194	dev_err(pm33xx_dev, "PM: Kernel suspend failure\n");
@@ -77,8 +210,20 @@ static int am33xx_pm_suspend(suspend_state_t suspend_state) · 15 unmodified lines
77	210	"PM: CM3 returned unknown result = %d\n", i);
78	211	ret = -1;
79	212	}
	213	+
	214	+ /* print the wakeup reason */
	215	+ if (rtc_only_idle) {
	216	+ wakeup_src = rtc_wake_src();
	217	+ pr_info("PM: Wakeup source %s\n", wakeup_src.src);
	218	+ } else {
	219	+ pr_info("PM: Wakeup source %s\n",
	220	+ m3_ipc->ops->request_wake_src(m3_ipc));
	221	+ }
80	222	}
81	223
	224	+ if (suspend_state == PM_SUSPEND_MEM && pm_ops->check_off_mode_enable())
	225	+ pm_ops->prepare_rtc_resume();
	226	+
82	227	return ret;
83	228	}
84	229
@@ -101,6 +246,18 @@ static int am33xx_pm_enter(suspend_state_t suspend_state) · 16 unmodified lines
101	246	static int am33xx_pm_begin(suspend_state_t state)
102	247	{
103	248	int ret = -EINVAL;
	249	+ struct nvmem_device *nvmem;
	250	+
	251	+ if (state == PM_SUSPEND_MEM && pm_ops->check_off_mode_enable()) {
	252	+ nvmem = devm_nvmem_device_get(&omap_rtc->dev,
	253	+ "omap_rtc_scratch0");
	254	+ if (nvmem)
	255	+ nvmem_device_write(nvmem, RTC_SCRATCH_MAGIC_REG * 4, 4,
	256	+ (void *)&rtc_magic_val);
	257	+ rtc_only_idle = 1;
	258	+ } else {
	259	+ rtc_only_idle = 0;
	260	+ }
104	261
105	262	switch (state) {
106	263	case PM_SUSPEND_MEM:
@@ -116,7 +273,28 @@ static int am33xx_pm_begin(suspend_state_t state) · 9 unmodified lines
116	273
117	274	static void am33xx_pm_end(void)
118	275	{
	276	+ u32 val = 0;
	277	+ struct nvmem_device *nvmem;
	278	+
	279	+ nvmem = devm_nvmem_device_get(&omap_rtc->dev, "omap_rtc_scratch0");
119	280	m3_ipc->ops->finish_low_power(m3_ipc);
	281	+ if (rtc_only_idle) {
	282	+ if (retrigger_irq)
	283	+ /*
	284	+ * 32 bits of Interrupt Set-Pending correspond to 32
	285	+ * 32 interrupts. Compute the bit offset of the
	286	+ * Interrupt and set that particular bit
	287	+ * Compute the register offset by dividing interrupt
	288	+ * number by 32 and mutiplying by 4
	289	+ */
	290	+ writel_relaxed(1 << (retrigger_irq & 31),
	291	+ gic_dist_base + GIC_INT_SET_PENDING_BASE
	292	+ + retrigger_irq / 32 * 4);
	293	+ nvmem_device_write(nvmem, RTC_SCRATCH_MAGIC_REG * 4, 4,
	294	+ (void *)&val);
	295	+ }
	296	+
	297	+ rtc_only_idle = 0;
120	298	}
121	299
122	300	static int am33xx_pm_valid(suspend_state_t state)
@@ -219,51 +397,37 @@ mpu_put_node: · 96 unmodified lines
219	397	return ret;
220	398	}
221	399
222		−static int am33xx_push_sram_idle(void)
	400	+static int am33xx_pm_rtc_setup(void)
223	401	{
224		− struct am33xx_pm_ro_sram_data ro_sram_data;
225		− int ret;
226		− u32 table_addr, ro_data_addr;
227		− void *copy_addr;
228		−
229		− ro_sram_data.amx3_pm_sram_data_virt = ocmcram_location_data;
230		− ro_sram_data.amx3_pm_sram_data_phys =
231		− gen_pool_virt_to_phys(sram_pool_data, ocmcram_location_data);
232		− ro_sram_data.rtc_base_virt = pm_ops->get_rtc_base_addr();
	402	+ struct device_node *np;
	403	+ unsigned long val = 0;
	404	+ struct nvmem_device *nvmem;
233	405
234		− /* Save physical address to calculate resume offset during pm init */
235		− am33xx_do_wfi_sram_phys = gen_pool_virt_to_phys(sram_pool,
236		− ocmcram_location);
	406	+ np = of_find_node_by_name(NULL, "rtc");
237	407
238		− am33xx_do_wfi_sram = sram_exec_copy(sram_pool, (void *)ocmcram_location,
239		− pm_sram->do_wfi,
240		− *pm_sram->do_wfi_sz);
241		− if (!am33xx_do_wfi_sram) {
242		− dev_err(pm33xx_dev,
243		− "PM: %s: am33xx_do_wfi copy to sram failed\n",
244		− __func__);
245		− return -ENODEV;
246		− }
247		−
248		− table_addr =
249		− sram_suspend_address((unsigned long)pm_sram->emif_sram_table);
250		− ret = ti_emif_copy_pm_function_table(sram_pool, (void *)table_addr);
251		− if (ret) {
252		− dev_dbg(pm33xx_dev,
253		− "PM: %s: EMIF function copy failed\n", __func__);
254		− return -EPROBE_DEFER;
255		− }
	408	+ if (of_device_is_available(np)) {
	409	+ omap_rtc = rtc_class_open("rtc0");
	410	+ if (!omap_rtc) {
	411	+ pr_warn("PM: rtc0 not available");
	412	+ return -EPROBE_DEFER;
	413	+ }
256	414
257		− ro_data_addr =
258		− sram_suspend_address((unsigned long)pm_sram->ro_sram_data);
259		− copy_addr = sram_exec_copy(sram_pool, (void *)ro_data_addr,
260		− &ro_sram_data,
261		− sizeof(ro_sram_data));
262		− if (!copy_addr) {
263		− dev_err(pm33xx_dev,
264		− "PM: %s: ro_sram_data copy to sram failed\n",
265		− __func__);
266		− return -ENODEV;
	415	+ nvmem = devm_nvmem_device_get(&omap_rtc->dev,
	416	+ "omap_rtc_scratch0");
	417	+ if (nvmem) {
	418	+ nvmem_device_read(nvmem, RTC_SCRATCH_MAGIC_REG * 4,
	419	+ 4, (void *)&rtc_magic_val);
	420	+ if ((rtc_magic_val & 0xffff) != RTC_REG_BOOT_MAGIC)
	421	+ pr_warn("PM: bootloader does not support rtc-only!\n");
	422	+
	423	+ nvmem_device_write(nvmem, RTC_SCRATCH_MAGIC_REG * 4,
	424	+ 4, (void *)&val);
	425	+ val = pm_sram->resume_address;
	426	+ nvmem_device_write(nvmem, RTC_SCRATCH_RESUME_REG * 4,
	427	+ 4, (void *)&val);
	428	+ }
	429	+ } else {
	430	+ pr_warn("PM: no-rtc available, rtc-only mode disabled.\n");
267	431	}
268	432
269	433	return 0;
@@ -284,34 +448,42 @@ static int am33xx_pm_probe(struct platform_device *pdev) · 14 unmodified lines
284	448	return -ENODEV;
285	449	}
286	450
	451	+ ret = am43xx_map_gic();
	452	+ if (ret) {
	453	+ pr_err("PM: Could not ioremap GIC base\n");
	454	+ return ret;
	455	+ }
	456	+
287	457	pm_sram = pm_ops->get_sram_addrs();
288	458	if (!pm_sram) {
289	459	dev_err(dev, "PM: Cannot get PM asm function addresses!!\n");
290	460	return -ENODEV;
291	461	}
292	462
	463	+ m3_ipc = wkup_m3_ipc_get();
	464	+ if (!m3_ipc) {
	465	+ pr_err("PM: Cannot get wkup_m3_ipc handle\n");
	466	+ return -EPROBE_DEFER;
	467	+ }
	468	+
293	469	pm33xx_dev = dev;
294	470
295	471	ret = am33xx_pm_alloc_sram();
296	472	if (ret)
297	473	return ret;
298	474
299		− ret = am33xx_push_sram_idle();
	475	+ ret = am33xx_pm_rtc_setup();
300	476	if (ret)
301	477	goto err_free_sram;
302	478
303		− m3_ipc = wkup_m3_ipc_get();
304		− if (!m3_ipc) {
305		− dev_dbg(dev, "PM: Cannot get wkup_m3_ipc handle\n");
306		− ret = -EPROBE_DEFER;
	479	+ ret = am33xx_push_sram_idle();
	480	+ if (ret)
307	481	goto err_free_sram;
308		− }
309	482
310	483	am33xx_pm_set_ipc_ops();
311	484
312	485	#ifdef CONFIG_SUSPEND
313	486	suspend_set_ops(&am33xx_pm_ops);
314		−#endif /* CONFIG_SUSPEND */
315	487
316	488	/*
317	489	* For a system suspend we must flush the caches, we want
@@ -323,6 +495,7 @@ static int am33xx_pm_probe(struct platform_device *pdev) · 5 unmodified lines
323	495	suspend_wfi_flags \|= WFI_FLAG_SELF_REFRESH;
324	496	suspend_wfi_flags \|= WFI_FLAG_SAVE_EMIF;
325	497	suspend_wfi_flags \|= WFI_FLAG_WAKE_M3;
	498	+#endif /* CONFIG_SUSPEND */
326	499
327	500	ret = pm_ops->init();
328	501	if (ret) {

drivers/soc/xilinx/zynqmp_pm_domains.c+10−8

@@ -23,6 +23,8 @@ · 22 unmodified lines
23	23	/* Flag stating if PM nodes mapped to the PM domain has been requested */
24	24	#define ZYNQMP_PM_DOMAIN_REQUESTED BIT(0)
25	25
	26	+static const struct zynqmp_eemi_ops *eemi_ops;
	27	+
26	28	/**
27	29	* struct zynqmp_pm_domain - Wrapper around struct generic_pm_domain
28	30	* @gpd: Generic power domain
@@ -71,9 +73,8 @@ static int zynqmp_gpd_power_on(struct generic_pm_domain *domain) · 42 unmodified lines
71	73	{
72	74	int ret;
73	75	struct zynqmp_pm_domain *pd;
74		− const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
75	76
76		− if (!eemi_ops \|\| !eemi_ops->set_requirement)
	77	+ if (!eemi_ops->set_requirement)
77	78	return -ENXIO;
78	79
79	80	pd = container_of(domain, struct zynqmp_pm_domain, gpd);
@@ -107,9 +108,8 @@ static int zynqmp_gpd_power_off(struct generic_pm_domain *domain) · 27 unmodified lines
107	108	struct zynqmp_pm_domain *pd;
108	109	u32 capabilities = 0;
109	110	bool may_wakeup;
110		− const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
111	111
112		− if (!eemi_ops \|\| !eemi_ops->set_requirement)
	112	+ if (!eemi_ops->set_requirement)
113	113	return -ENXIO;
114	114
115	115	pd = container_of(domain, struct zynqmp_pm_domain, gpd);
@@ -160,9 +160,8 @@ static int zynqmp_gpd_attach_dev(struct generic_pm_domain *domain, · 44 unmodified lines
160	160	{
161	161	int ret;
162	162	struct zynqmp_pm_domain *pd;
163		− const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
164	163
165		− if (!eemi_ops \|\| !eemi_ops->request_node)
	164	+ if (!eemi_ops->request_node)
166	165	return -ENXIO;
167	166
168	167	pd = container_of(domain, struct zynqmp_pm_domain, gpd);
@@ -197,9 +196,8 @@ static void zynqmp_gpd_detach_dev(struct generic_pm_domain *domain, · 28 unmodified lines
197	196	{
198	197	int ret;
199	198	struct zynqmp_pm_domain *pd;
200		− const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
201	199
202		− if (!eemi_ops \|\| !eemi_ops->release_node)
	200	+ if (!eemi_ops->release_node)
203	201	return;
204	202
205	203	pd = container_of(domain, struct zynqmp_pm_domain, gpd);
@@ -266,6 +264,10 @@ static int zynqmp_gpd_probe(struct platform_device *pdev) · 60 unmodified lines
266	264	struct zynqmp_pm_domain *pd;
267	265	struct device *dev = &pdev->dev;
268	266
	267	+ eemi_ops = zynqmp_pm_get_eemi_ops();
	268	+ if (IS_ERR(eemi_ops))
	269	+ return PTR_ERR(eemi_ops);
	270	+
269	271	pd = devm_kcalloc(dev, ZYNQMP_NUM_DOMAINS, sizeof(*pd), GFP_KERNEL);
270	272	if (!pd)
271	273	return -ENOMEM;

drivers/soc/xilinx/zynqmp_power.c+6−4

@@ -31,6 +31,7 @@ static const char *const suspend_modes[] = { · 30 unmodified lines
31	31	};
32	32
33	33	static enum pm_suspend_mode suspend_mode = PM_SUSPEND_MODE_STD;
	34	+static const struct zynqmp_eemi_ops *eemi_ops;
34	35
35	36	enum pm_api_cb_id {
36	37	PM_INIT_SUSPEND_CB = 30,
@@ -92,9 +93,8 @@ static ssize_t suspend_mode_store(struct device *dev, · 55 unmodified lines
92	93	const char *buf, size_t count)
93	94	{
94	95	int md, ret = -EINVAL;
95		− const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
96	96
97		− if (!eemi_ops \|\| !eemi_ops->set_suspend_mode)
	97	+ if (!eemi_ops->set_suspend_mode)
98	98	return ret;
99	99
100	100	for (md = PM_SUSPEND_MODE_FIRST; md < ARRAY_SIZE(suspend_modes); md++)
@@ -120,9 +120,11 @@ static int zynqmp_pm_probe(struct platform_device *pdev) · 19 unmodified lines
120	120	int ret, irq;
121	121	u32 pm_api_version;
122	122
123		− const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
	123	+ eemi_ops = zynqmp_pm_get_eemi_ops();
	124	+ if (IS_ERR(eemi_ops))
	125	+ return PTR_ERR(eemi_ops);
124	126
125		− if (!eemi_ops \|\| !eemi_ops->get_api_version \|\| !eemi_ops->init_finalize)
	127	+ if (!eemi_ops->get_api_version \|\| !eemi_ops->init_finalize)
126	128	return -ENXIO;
127	129
128	130	eemi_ops->init_finalize();

drivers/spi/spi-zynqmp-gqspi.c+6−0

@@ -14,6 +14,7 @@ · 13 unmodified lines
14	14	#include <linux/delay.h>
15	15	#include <linux/dma-mapping.h>
16	16	#include <linux/dmaengine.h>
	17	+#include <linux/firmware/xlnx-zynqmp.h>
17	18	#include <linux/interrupt.h>
18	19	#include <linux/io.h>
19	20	#include <linux/module.h>
@@ -138,6 +139,7 @@ · 118 unmodified lines
138	139
139	140	#define SPI_AUTOSUSPEND_TIMEOUT 3000
140	141	enum mode_type {GQSPI_MODE_IO, GQSPI_MODE_DMA};
	142	+static const struct zynqmp_eemi_ops *eemi_ops;
141	143
142	144	/**
143	145	* struct zynqmp_qspi - Defines qspi driver instance
@@ -1021,6 +1023,10 @@ static int zynqmp_qspi_probe(struct platform_device *pdev) · 877 unmodified lines
1021	1023	struct resource *res;
1022	1024	struct device *dev = &pdev->dev;
1023	1025
	1026	+ eemi_ops = zynqmp_pm_get_eemi_ops();
	1027	+ if (IS_ERR(eemi_ops))
	1028	+ return PTR_ERR(eemi_ops);
	1029	+
1024	1030	master = spi_alloc_master(&pdev->dev, sizeof(*xqspi));
1025	1031	if (!master)
1026	1032	return -ENOMEM;

drivers/tee/optee/core.c+49−31

@@ -419,9 +419,35 @@ static bool optee_msg_exchange_capabilities(optee_invoke_fn *invoke_fn, · 418 unmodified lines
419	419	return true;
420	420	}
421	421
	422	+static struct tee_shm_pool *optee_config_dyn_shm(void)
	423	+{
	424	+ struct tee_shm_pool_mgr *priv_mgr;
	425	+ struct tee_shm_pool_mgr *dmabuf_mgr;
	426	+ void *rc;
	427	+
	428	+ rc = optee_shm_pool_alloc_pages();
	429	+ if (IS_ERR(rc))
	430	+ return rc;
	431	+ priv_mgr = rc;
	432	+
	433	+ rc = optee_shm_pool_alloc_pages();
	434	+ if (IS_ERR(rc)) {
	435	+ tee_shm_pool_mgr_destroy(priv_mgr);
	436	+ return rc;
	437	+ }
	438	+ dmabuf_mgr = rc;
	439	+
	440	+ rc = tee_shm_pool_alloc(priv_mgr, dmabuf_mgr);
	441	+ if (IS_ERR(rc)) {
	442	+ tee_shm_pool_mgr_destroy(priv_mgr);
	443	+ tee_shm_pool_mgr_destroy(dmabuf_mgr);
	444	+ }
	445	+
	446	+ return rc;
	447	+}
	448	+
422	449	static struct tee_shm_pool *
423		−optee_config_shm_memremap(optee_invoke_fn invoke_fn, void *memremaped_shm,
424		− u32 sec_caps)
	450	+optee_config_shm_memremap(optee_invoke_fn invoke_fn, void *memremaped_shm)
425	451	{
426	452	union {
427	453	struct arm_smccc_res smccc;
@@ -436,10 +462,11 @@ optee_config_shm_memremap(optee_invoke_fn invoke_fn, void *memremaped_shm, · 8 unmodified lines
436	462	struct tee_shm_pool_mgr *priv_mgr;
437	463	struct tee_shm_pool_mgr *dmabuf_mgr;
438	464	void *rc;
	465	+ const int sz = OPTEE_SHM_NUM_PRIV_PAGES * PAGE_SIZE;
439	466
440	467	invoke_fn(OPTEE_SMC_GET_SHM_CONFIG, 0, 0, 0, 0, 0, 0, 0, &res.smccc);
441	468	if (res.result.status != OPTEE_SMC_RETURN_OK) {
442		− pr_info("shm service not available\n");
	469	+ pr_err("static shm service not available\n");
443	470	return ERR_PTR(-ENOENT);
444	471	}
445	472
@@ -465,28 +492,15 @@ optee_config_shm_memremap(optee_invoke_fn invoke_fn, void *memremaped_shm, · 19 unmodified lines
465	492	}
466	493	vaddr = (unsigned long)va;
467	494
468		− /*
469		− * If OP-TEE can work with unregistered SHM, we will use own pool
470		− * for private shm
471		− */
472		− if (sec_caps & OPTEE_SMC_SEC_CAP_DYNAMIC_SHM) {
473		− rc = optee_shm_pool_alloc_pages();
474		− if (IS_ERR(rc))
475		− goto err_memunmap;
476		− priv_mgr = rc;
477		− } else {
478		− const size_t sz = OPTEE_SHM_NUM_PRIV_PAGES * PAGE_SIZE;
479		−
480		− rc = tee_shm_pool_mgr_alloc_res_mem(vaddr, paddr, sz,
481		− 3 /* 8 bytes aligned */);
482		− if (IS_ERR(rc))
483		− goto err_memunmap;
484		− priv_mgr = rc;
485		−
486		− vaddr += sz;
487		− paddr += sz;
488		− size -= sz;
489		− }
	495	+ rc = tee_shm_pool_mgr_alloc_res_mem(vaddr, paddr, sz,
	496	+ 3 /* 8 bytes aligned */);
	497	+ if (IS_ERR(rc))
	498	+ goto err_memunmap;
	499	+ priv_mgr = rc;
	500	+
	501	+ vaddr += sz;
	502	+ paddr += sz;
	503	+ size -= sz;
490	504
491	505	rc = tee_shm_pool_mgr_alloc_res_mem(vaddr, paddr, size, PAGE_SHIFT);
492	506	if (IS_ERR(rc))
@@ -552,7 +566,7 @@ static optee_invoke_fn get_invoke_func(struct device_node np) · 59 unmodified lines
552	566	static struct optee optee_probe(struct device_node np)
553	567	{
554	568	optee_invoke_fn *invoke_fn;
555		− struct tee_shm_pool *pool;
	569	+ struct tee_shm_pool *pool = ERR_PTR(-EINVAL);
556	570	struct optee *optee = NULL;
557	571	void *memremaped_shm = NULL;
558	572	struct tee_device *teedev;
@@ -581,13 +595,17 @@ static struct optee optee_probe(struct device_node np) · 22 unmodified lines
581	595	}
582	596
583	597	/*
584		− * We have no other option for shared memory, if secure world
585		− * doesn't have any reserved memory we can use we can't continue.
	598	+ * Try to use dynamic shared memory if possible
586	599	*/
587		− if (!(sec_caps & OPTEE_SMC_SEC_CAP_HAVE_RESERVED_SHM))
588		− return ERR_PTR(-EINVAL);
	600	+ if (sec_caps & OPTEE_SMC_SEC_CAP_DYNAMIC_SHM)
	601	+ pool = optee_config_dyn_shm();
	602	+
	603	+ /*
	604	+ * If dynamic shared memory is not available or failed - try static one
	605	+ */
	606	+ if (IS_ERR(pool) && (sec_caps & OPTEE_SMC_SEC_CAP_HAVE_RESERVED_SHM))
	607	+ pool = optee_config_shm_memremap(invoke_fn, &memremaped_shm);
589	608
590		− pool = optee_config_shm_memremap(invoke_fn, &memremaped_shm, sec_caps);
591	609	if (IS_ERR(pool))
592	610	return (void *)pool;
593	611

include/linux/firmware/imx/sci.h+5−0

@@ -15,4 +15,9 @@ · 14 unmodified lines
15	15
16	16	#include <linux/firmware/imx/svc/misc.h>
17	17	#include <linux/firmware/imx/svc/pm.h>
	18	+
	19	+int imx_scu_enable_general_irq_channel(struct device *dev);
	20	+int imx_scu_irq_register_notifier(struct notifier_block *nb);
	21	+int imx_scu_irq_unregister_notifier(struct notifier_block *nb);
	22	+int imx_scu_irq_group_enable(u8 group, u32 mask, u8 enable);
18	23	#endif /* _SC_SCI_H */

include/linux/firmware/xlnx-zynqmp.h+13−1

@@ -48,6 +48,14 @@ · 47 unmodified lines
48	48	#define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U
49	49	#define ZYNQMP_PM_CAPABILITY_POWER 0x8U
50	50
	51	+/*
	52	+ * Firmware FPGA Manager flags
	53	+ * XILINX_ZYNQMP_PM_FPGA_FULL: FPGA full reconfiguration
	54	+ * XILINX_ZYNQMP_PM_FPGA_PARTIAL: FPGA partial reconfiguration
	55	+ */
	56	+#define XILINX_ZYNQMP_PM_FPGA_FULL 0x0U
	57	+#define XILINX_ZYNQMP_PM_FPGA_PARTIAL BIT(0)
	58	+
51	59	enum pm_api_id {
52	60	PM_GET_API_VERSION = 1,
53	61	PM_REQUEST_NODE = 13,
@@ -56,6 +64,8 @@ enum pm_api_id { · 2 unmodified lines
56	64	PM_RESET_ASSERT = 17,
57	65	PM_RESET_GET_STATUS,
58	66	PM_PM_INIT_FINALIZE = 21,
	67	+ PM_FPGA_LOAD,
	68	+ PM_FPGA_GET_STATUS,
59	69	PM_GET_CHIPID = 24,
60	70	PM_IOCTL = 34,
61	71	PM_QUERY_DATA,
@@ -258,6 +268,8 @@ struct zynqmp_pm_query_data { · 196 unmodified lines
258	268	struct zynqmp_eemi_ops {
259	269	int (get_api_version)(u32 version);
260	270	int (get_chipid)(u32 idcode, u32 *version);
	271	+ int (*fpga_load)(const u64 address, const u32 size, const u32 flags);
	272	+ int (fpga_get_status)(u32 value);
261	273	int (query_data)(struct zynqmp_pm_query_data qdata, u32 out);
262	274	int (*clock_enable)(u32 clock_id);
263	275	int (*clock_disable)(u32 clock_id);
@@ -293,7 +305,7 @@ const struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void); · 29 unmodified lines
293	305	#else
294	306	static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void)
295	307	{
296		− return NULL;
	308	+ return ERR_PTR(-ENODEV);
297	309	}
298	310	#endif
299	311

include/linux/platform_data/pm33xx.h+5−0

@@ -51,6 +51,11 @@ struct am33xx_pm_platform_data { · 50 unmodified lines
51	51	unsigned long args);
52	52	struct am33xx_pm_sram_addr (get_sram_addrs)(void);
53	53	void __iomem (get_rtc_base_addr)(void);
	54	+ void (*save_context)(void);
	55	+ void (*restore_context)(void);
	56	+ void (*prepare_rtc_suspend)(void);
	57	+ void (*prepare_rtc_resume)(void);
	58	+ int (*check_off_mode_enable)(void);
54	59	};
55	60
56	61	struct am33xx_pm_sram_data {

include/linux/reset.h+2−0

@@ -2,6 +2,8 @@ · 1 unmodified line
2	2	#ifndef _LINUX_RESET_H_
3	3	#define _LINUX_RESET_H_
4	4
	5	+#include <linux/err.h>
	6	+#include <linux/errno.h>
5	7	#include <linux/types.h>
6	8
7	9	struct device;

include/linux/rtc/rtc-omap.h+7−0

@@ -0,0 +1,7 @@
	1	+/* SPDX-License-Identifier: GPL-2.0 */
	2	+
	3	+#ifndef _LINUX_RTCOMAP_H_
	4	+#define _LINUX_RTCOMAP_H_
	5	+
	6	+int omap_rtc_power_off_program(struct device *dev);
	7	+#endif /* _LINUX_RTCOMAP_H_ */

include/linux/ti-emif-sram.h+3−0

@@ -55,6 +55,7 @@ struct ti_emif_pm_data { · 54 unmodified lines
55	55	struct ti_emif_pm_functions {
56	56	u32 save_context;
57	57	u32 restore_context;
	58	+ u32 run_hw_leveling;
58	59	u32 enter_sr;
59	60	u32 exit_sr;
60	61	u32 abort_sr;
@@ -126,6 +127,8 @@ static inline void ti_emif_asm_offsets(void) · 65 unmodified lines
126	127	offsetof(struct ti_emif_pm_functions, save_context));
127	128	DEFINE(EMIF_PM_RESTORE_CONTEXT_OFFSET,
128	129	offsetof(struct ti_emif_pm_functions, restore_context));
	130	+ DEFINE(EMIF_PM_RUN_HW_LEVELING,
	131	+ offsetof(struct ti_emif_pm_functions, run_hw_leveling));
129	132	DEFINE(EMIF_PM_ENTER_SR_OFFSET,
130	133	offsetof(struct ti_emif_pm_functions, enter_sr));
131	134	DEFINE(EMIF_PM_EXIT_SR_OFFSET,

Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

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