Merge tag 'pinctrl-v5.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for v5.5. It is pretty much business as usual, the most interesting thing I think is the pin controller for a new Intel chip called Lightning Mountain, which is according to news reports some kind of embedded network processor and what is surprising about it is that Intel have decided to use device tree to describe the system rather than ACPI that they have traditionally favored. Core changes: - Avoid taking direct references to device tree-supplied device names: these may changed at runtime under certain circumstances to kstrdup them. GPIO related: - Work is ongoing to move to passing the irqchip along as a templated struct gpio_irq_chip when adding a standard gpiolib-based irqchip to a GPIO controller, a few patches in this cycle switches a few pin control drivers over to using this method. New hardware support: - Intel Lightning Mountain SoC pin controller and GPIO support, a first Intel platform to use device tree rather than ACPI to configure the system. News reports says that this SoC is a network processor. - Qualcomm MSM8976 and MSM8956 - Qualcomm PMIC GPIO now also supports PM6150 and PM6150L - Qualcomm SPMI MPP and SPMI GPIO for PM8950 and PMI8950 - Rockchip RK3308 - Renesas R8A77961 - Allwinner Meson-A1 Driver improvements: - get_multiple and set_multiple support for the AT91-PIO4 driver. - Convert Qualcomm SSBI GPIO to use the hierarchical IRQ helpers in the GPIOlib irqchip" * tag 'pinctrl-v5.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (93 commits) pinctrl: ingenic: Add OTG VBUS pin for the JZ4770 pinctrl: ingenic: Handle PIN_CONFIG_OUTPUT config pinctrl: Fix Kconfig indentation pinctrl: lewisburg: Update pin list according to v1.1v6 MAINTAINERS: Replace my email by one @kernel.org pinctrl: armada-37xx: Fix irq mask access in armada_37xx_irq_set_type() dt-bindings: pinctrl: intel: Add for new SoC pinctrl: Add pinmux & GPIO controller driver for a new SoC pinctrl: rza1: remove unnecessary static inline function pinctrl: meson: add pinctrl driver support for Meson-A1 SoC pinctrl: meson: add a new callback for SoCs fixup pinctrl: nomadik: db8500: Add mc0_a_2 pin group without direction control dt-bindings: pinctrl: Convert generic pin mux and config properties to schema pinctrl: cherryview: Missed type change to unsigned int pinctrl: intel: Missed type change to unsigned int pinctrl: use devm_platform_ioremap_resource() to simplify code pinctrl: just return if no valid maps dt-bindings: pinctrl: qcom-pmic-mpp: Add support for PM/PMI8950 pinctrl: qcom: spmi-mpp: Add PM/PMI8950 compatible strings dt-bindings: pinctrl: qcom-pmic-gpio: Add support for PM/PMI8950 ...

Linus Torvalds committed 6 years ago

Commit dc5fa462 parents 3d9e350 ae75b53113 files · +6407 −1655Browse files

Unified · Split

113 files

Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml +243 −0
Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt +0 −164
Documentation/devicetree/bindings/pinctrl/intel,lgm-pinctrl.yaml +116 −0
Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt +1 −0
Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml +140 −0
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt +2 −190
Documentation/devicetree/bindings/pinctrl/pinmux-node.yaml +132 −0
Documentation/devicetree/bindings/pinctrl/qcom,msm8976-pinctrl.txt +183 −0
Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt +8 −0
Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt +4 −0
Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt +3 −1
Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt +1 −0
MAINTAINERS +1 −1
arch/sh/include/cpu-sh4/cpu/sh7734.h +1 −1
drivers/pinctrl/Kconfig +27 −9
drivers/pinctrl/Makefile +1 −0
drivers/pinctrl/actions/pinctrl-owl.c +1 −3
drivers/pinctrl/bcm/pinctrl-bcm281xx.c +1 −3
drivers/pinctrl/bcm/pinctrl-cygnus-mux.c +2 −5
drivers/pinctrl/bcm/pinctrl-iproc-gpio.c +2 −3
drivers/pinctrl/bcm/pinctrl-ns2-mux.c +2 −4
drivers/pinctrl/bcm/pinctrl-nsp-gpio.c +56 −63
drivers/pinctrl/bcm/pinctrl-nsp-mux.c +2 −4
drivers/pinctrl/devicetree.c +30 −20
drivers/pinctrl/devicetree.h +0 −7
drivers/pinctrl/freescale/Kconfig +6 −6
drivers/pinctrl/intel/Kconfig +7 −0
drivers/pinctrl/intel/Makefile +1 −0
drivers/pinctrl/intel/pinctrl-cherryview.c +3 −3
drivers/pinctrl/intel/pinctrl-intel.c +63 −56
drivers/pinctrl/intel/pinctrl-lewisburg.c +86 −85
drivers/pinctrl/intel/pinctrl-tigerlake.c +454 −0
drivers/pinctrl/mediatek/pinctrl-mtk-common.c +1 −3
drivers/pinctrl/meson/Kconfig +6 −0
drivers/pinctrl/meson/Makefile +1 −0
drivers/pinctrl/meson/pinctrl-meson-a1.c +942 −0
drivers/pinctrl/meson/pinctrl-meson-axg.c +1 −0
drivers/pinctrl/meson/pinctrl-meson-g12a.c +9 −0
drivers/pinctrl/meson/pinctrl-meson-gxbb.c +1 −0
drivers/pinctrl/meson/pinctrl-meson-gxl.c +1 −0
drivers/pinctrl/meson/pinctrl-meson.c +29 −9
drivers/pinctrl/meson/pinctrl-meson.h +7 −0
drivers/pinctrl/meson/pinctrl-meson8.c +1 −0
drivers/pinctrl/meson/pinctrl-meson8b.c +1 −0
drivers/pinctrl/mvebu/Kconfig +5 −5
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +22 −18
drivers/pinctrl/mvebu/pinctrl-mvebu.c +1 −3
drivers/pinctrl/mvebu/pinctrl-orion.c +2 −5
drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c +11 −1
drivers/pinctrl/nomadik/pinctrl-nomadik.c +22 −59
drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c +16 −16
drivers/pinctrl/pinctrl-amd.c +2 −1
drivers/pinctrl/pinctrl-artpec6.c +1 −3
drivers/pinctrl/pinctrl-at91-pio4.c +63 −2
drivers/pinctrl/pinctrl-at91.c +25 −30
drivers/pinctrl/pinctrl-bm1880.c +1 −3
drivers/pinctrl/pinctrl-coh901.c +24 −30
drivers/pinctrl/pinctrl-da850-pupd.c +1 −3
drivers/pinctrl/pinctrl-digicolor.c +1 −3
drivers/pinctrl/pinctrl-equilibrium.c +944 −0
drivers/pinctrl/pinctrl-equilibrium.h +144 −0
drivers/pinctrl/pinctrl-ingenic.c +41 −9
drivers/pinctrl/pinctrl-lpc18xx.c +1 −3
drivers/pinctrl/pinctrl-ocelot.c +14 −9
drivers/pinctrl/pinctrl-oxnas.c +14 −15
drivers/pinctrl/pinctrl-pic32.c +13 −16
drivers/pinctrl/pinctrl-pistachio.c +17 −13
drivers/pinctrl/pinctrl-rockchip.c +381 −1
drivers/pinctrl/pinctrl-rza1.c +1 −7
drivers/pinctrl/pinctrl-rza2.c +3 −5
drivers/pinctrl/pinctrl-rzn1.c +1 −1
drivers/pinctrl/pinctrl-st.c +32 −21
drivers/pinctrl/pinctrl-stmfx.c +21 −0
drivers/pinctrl/pinctrl-tb10x.c +1 −3
drivers/pinctrl/pinctrl-u300.c +1 −3
drivers/pinctrl/pinctrl-xway.c +1 −3
drivers/pinctrl/pxa/pinctrl-pxa25x.c +4 −9
drivers/pinctrl/pxa/pinctrl-pxa27x.c +4 −9
drivers/pinctrl/qcom/Kconfig +56 −45
drivers/pinctrl/qcom/Makefile +1 −0
drivers/pinctrl/qcom/pinctrl-msm.c +1 −2
drivers/pinctrl/qcom/pinctrl-msm8976.c +1127 −0
drivers/pinctrl/qcom/pinctrl-sc7180.c +10 −8
drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +5 −0
drivers/pinctrl/qcom/pinctrl-spmi-mpp.c +2 −0
drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c +33 −88
drivers/pinctrl/samsung/pinctrl-exynos.c +11 −3
drivers/pinctrl/samsung/pinctrl-s3c24xx.c +5 −1
drivers/pinctrl/samsung/pinctrl-s3c64xx.c +5 −1
drivers/pinctrl/samsung/pinctrl-samsung.c +8 −2
drivers/pinctrl/sh-pfc/Kconfig +10 −2
drivers/pinctrl/sh-pfc/Makefile +3 −1
drivers/pinctrl/sh-pfc/core.c +20 −12
drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c +1 −1
drivers/pinctrl/sh-pfc/pfc-r8a7795.c +1 −1
drivers/pinctrl/sh-pfc/pfc-r8a7796.c +31 −4
drivers/pinctrl/sh-pfc/pfc-r8a77965.c +453 −410
drivers/pinctrl/sh-pfc/pfc-r8a77990.c +30 −27
drivers/pinctrl/sh-pfc/pfc-sh7734.c +2 −2
drivers/pinctrl/sh-pfc/sh_pfc.h +5 −3
drivers/pinctrl/sirf/pinctrl-atlas7.c +21 −20
drivers/pinctrl/sirf/pinctrl-sirf.c +20 −23
drivers/pinctrl/spear/pinctrl-plgpio.c +22 −29
drivers/pinctrl/spear/pinctrl-spear.c +1 −3
drivers/pinctrl/sprd/pinctrl-sprd.c +22 −1
drivers/pinctrl/sunxi/pinctrl-sunxi.c +1 −3
drivers/pinctrl/tegra/pinctrl-tegra-xusb.c +7 −3
drivers/pinctrl/tegra/pinctrl-tegra.c +1 −2
drivers/pinctrl/ti/pinctrl-ti-iodelay.c +1 −1
drivers/pinctrl/vt8500/pinctrl-wmt.c +1 −3
drivers/pinctrl/zte/pinctrl-zx.c +1 −3
include/dt-bindings/gpio/meson-a1-gpio.h +73 −0
include/dt-bindings/pinctrl/at91.h +2 −2

Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml+243−0

@@ -0,0 +1,243 @@
	1	+# SPDX-License-Identifier: GPL-2.0
	2	+%YAML 1.2
	3	+---
	4	+$id: http://devicetree.org/schemas/pinctrl/allwinner,sun4i-a10-pinctrl.yaml#
	5	+$schema: http://devicetree.org/meta-schemas/core.yaml#
	6	+
	7	+title: Allwinner A10 Pin Controller Device Tree Bindings
	8	+
	9	+maintainers:
	10	+ - Chen-Yu Tsai <wens@csie.org>
	11	+ - Maxime Ripard <maxime.ripard@bootlin.com>
	12	+
	13	+properties:
	14	+ "#gpio-cells":
	15	+ const: 3
	16	+ description:
	17	+ GPIO consumers must use three arguments, first the number of the
	18	+ bank, then the pin number inside that bank, and finally the GPIO
	19	+ flags.
	20	+
	21	+ "#interrupt-cells":
	22	+ const: 3
	23	+ description:
	24	+ Interrupts consumers must use three arguments, first the number
	25	+ of the bank, then the pin number inside that bank, and finally
	26	+ the interrupts flags.
	27	+
	28	+ compatible:
	29	+ enum:
	30	+ - allwinner,sun4i-a10-pinctrl
	31	+ - allwinner,sun5i-a10s-pinctrl
	32	+ - allwinner,sun5i-a13-pinctrl
	33	+ - allwinner,sun6i-a31-pinctrl
	34	+ - allwinner,sun6i-a31-r-pinctrl
	35	+ - allwinner,sun6i-a31s-pinctrl
	36	+ - allwinner,sun7i-a20-pinctrl
	37	+ - allwinner,sun8i-a23-pinctrl
	38	+ - allwinner,sun8i-a23-r-pinctrl
	39	+ - allwinner,sun8i-a33-pinctrl
	40	+ - allwinner,sun8i-a83t-pinctrl
	41	+ - allwinner,sun8i-a83t-r-pinctrl
	42	+ - allwinner,sun8i-h3-pinctrl
	43	+ - allwinner,sun8i-h3-r-pinctrl
	44	+ - allwinner,sun8i-r40-pinctrl
	45	+ - allwinner,sun8i-v3-pinctrl
	46	+ - allwinner,sun8i-v3s-pinctrl
	47	+ - allwinner,sun9i-a80-pinctrl
	48	+ - allwinner,sun9i-a80-r-pinctrl
	49	+ - allwinner,sun50i-a64-pinctrl
	50	+ - allwinner,sun50i-a64-r-pinctrl
	51	+ - allwinner,sun50i-h5-pinctrl
	52	+ - allwinner,sun50i-h6-pinctrl
	53	+ - allwinner,sun50i-h6-r-pinctrl
	54	+ - allwinner,suniv-f1c100s-pinctrl
	55	+ - nextthing,gr8-pinctrl
	56	+
	57	+ reg:
	58	+ maxItems: 1
	59	+
	60	+ interrupts:
	61	+ minItems: 1
	62	+ maxItems: 5
	63	+ description:
	64	+ One interrupt per external interrupt bank supported on the
	65	+ controller, sorted by bank number ascending order.
	66	+
	67	+ clocks:
	68	+ items:
	69	+ - description: Bus Clock
	70	+ - description: High Frequency Oscillator
	71	+ - description: Low Frequency Oscillator
	72	+
	73	+ clock-names:
	74	+ items:
	75	+ - const: apb
	76	+ - const: hosc
	77	+ - const: losc
	78	+
	79	+ resets:
	80	+ maxItems: 1
	81	+
	82	+ gpio-controller: true
	83	+ interrupt-controller: true
	84	+ gpio-line-names: true
	85	+
	86	+ input-debounce:
	87	+ allOf:
	88	+ - $ref: /schemas/types.yaml#/definitions/uint32-array
	89	+ - minItems: 1
	90	+ maxItems: 5
	91	+ description:
	92	+ Debouncing periods in microseconds, one period per interrupt
	93	+ bank found in the controller
	94	+
	95	+patternProperties:
	96	+ # It's pretty scary, but the basic idea is that:
	97	+ # - One node name can start with either s- or r- for PRCM nodes,
	98	+ # - Then, the name itself can be any repetition of <string>- (to
	99	+ # accomodate with nodes like uart4-rts-cts-pins), where each
	100	+ # string can be either starting with 'p' but in a string longer
	101	+ # than 3, or something that doesn't start with 'p',
	102	+ # - Then, the bank name is optional and will be between pa and pg,
	103	+ # pl or pm. Some pins groups that have several options will have
	104	+ # the pin numbers then,
	105	+ # - Finally, the name will end with either -pin or pins.
	106	+
	107	+ "^([rs]-)?(([a-z0-9]{3,}\|[a-oq-z][a-z0-9]?)?-)+?(p[a-ilm][0-9]?-)??pins?$":
	108	+ type: object
	109	+
	110	+ properties:
	111	+ pins: true
	112	+ function: true
	113	+ bias-disable: true
	114	+ bias-pull-up: true
	115	+ bias-pull-down: true
	116	+
	117	+ drive-strength:
	118	+ allOf:
	119	+ - $ref: /schemas/types.yaml#/definitions/uint32
	120	+ - enum: [ 10, 20, 30, 40 ]
	121	+
	122	+ required:
	123	+ - pins
	124	+ - function
	125	+
	126	+ additionalProperties: false
	127	+
	128	+ "^vcc-p[a-hlm]-supply$":
	129	+ description:
	130	+ Power supplies for pin banks.
	131	+
	132	+required:
	133	+ - "#gpio-cells"
	134	+ - "#interrupt-cells"
	135	+ - compatible
	136	+ - reg
	137	+ - interrupts
	138	+ - clocks
	139	+ - clock-names
	140	+ - gpio-controller
	141	+ - interrupt-controller
	142	+
	143	+allOf:
	144	+ # FIXME: We should have the pin bank supplies here, but not a lot of
	145	+ # boards are defining it at the moment so it would generate a lot of
	146	+ # warnings.
	147	+
	148	+ - if:
	149	+ properties:
	150	+ compatible:
	151	+ enum:
	152	+ - allwinner,sun9i-a80-pinctrl
	153	+
	154	+ then:
	155	+ properties:
	156	+ interrupts:
	157	+ minItems: 5
	158	+ maxItems: 5
	159	+
	160	+ else:
	161	+ if:
	162	+ properties:
	163	+ compatible:
	164	+ enum:
	165	+ - allwinner,sun6i-a31-pinctrl
	166	+ - allwinner,sun6i-a31s-pinctrl
	167	+ - allwinner,sun50i-h6-pinctrl
	168	+
	169	+ then:
	170	+ properties:
	171	+ interrupts:
	172	+ minItems: 4
	173	+ maxItems: 4
	174	+
	175	+ else:
	176	+ if:
	177	+ properties:
	178	+ compatible:
	179	+ enum:
	180	+ - allwinner,sun8i-a23-pinctrl
	181	+ - allwinner,sun8i-a83t-pinctrl
	182	+ - allwinner,sun50i-a64-pinctrl
	183	+ - allwinner,sun50i-h5-pinctrl
	184	+ - allwinner,suniv-f1c100s-pinctrl
	185	+
	186	+ then:
	187	+ properties:
	188	+ interrupts:
	189	+ minItems: 3
	190	+ maxItems: 3
	191	+
	192	+ else:
	193	+ if:
	194	+ properties:
	195	+ compatible:
	196	+ enum:
	197	+ - allwinner,sun6i-a31-r-pinctrl
	198	+ - allwinner,sun8i-a33-pinctrl
	199	+ - allwinner,sun8i-h3-pinctrl
	200	+ - allwinner,sun8i-v3-pinctrl
	201	+ - allwinner,sun8i-v3s-pinctrl
	202	+ - allwinner,sun9i-a80-r-pinctrl
	203	+ - allwinner,sun50i-h6-r-pinctrl
	204	+
	205	+ then:
	206	+ properties:
	207	+ interrupts:
	208	+ minItems: 2
	209	+ maxItems: 2
	210	+
	211	+ else:
	212	+ properties:
	213	+ interrupts:
	214	+ minItems: 1
	215	+ maxItems: 1
	216	+
	217	+additionalProperties: false
	218	+
	219	+examples:
	220	+ - \|
	221	+ #include <dt-bindings/clock/sun5i-ccu.h>
	222	+
	223	+ pio: pinctrl@1c20800 {
	224	+ compatible = "allwinner,sun5i-a13-pinctrl";
	225	+ reg = <0x01c20800 0x400>;
	226	+ interrupts = <28>;
	227	+ clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
	228	+ clock-names = "apb", "hosc", "losc";
	229	+ gpio-controller;
	230	+ interrupt-controller;
	231	+ #interrupt-cells = <3>;
	232	+ #gpio-cells = <3>;
	233	+
	234	+ uart1_pe_pins: uart1-pe-pins {
	235	+ pins = "PE10", "PE11";
	236	+ function = "uart1";
	237	+ };
	238	+
	239	+ uart1_pg_pins: uart1-pg-pins {
	240	+ pins = "PG3", "PG4";
	241	+ function = "uart1";
	242	+ };
	243	+ };

Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt+0−164

@@ -1,164 +0,0 @@
1		−* Allwinner A1X Pin Controller
2		−
3		−The pins controlled by sunXi pin controller are organized in banks,
4		−each bank has 32 pins. Each pin has 7 multiplexing functions, with
5		−the first two functions being GPIO in and out. The configuration on
6		−the pins includes drive strength and pull-up.
7		−
8		−Required properties:
9		−- compatible: Should be one of the following (depending on your SoC):
10		− "allwinner,sun4i-a10-pinctrl"
11		− "allwinner,sun5i-a10s-pinctrl"
12		− "allwinner,sun5i-a13-pinctrl"
13		− "allwinner,sun6i-a31-pinctrl"
14		− "allwinner,sun6i-a31s-pinctrl"
15		− "allwinner,sun6i-a31-r-pinctrl"
16		− "allwinner,sun7i-a20-pinctrl"
17		− "allwinner,sun8i-a23-pinctrl"
18		− "allwinner,sun8i-a23-r-pinctrl"
19		− "allwinner,sun8i-a33-pinctrl"
20		− "allwinner,sun9i-a80-pinctrl"
21		− "allwinner,sun9i-a80-r-pinctrl"
22		− "allwinner,sun8i-a83t-pinctrl"
23		− "allwinner,sun8i-a83t-r-pinctrl"
24		− "allwinner,sun8i-h3-pinctrl"
25		− "allwinner,sun8i-h3-r-pinctrl"
26		− "allwinner,sun8i-r40-pinctrl"
27		− "allwinner,sun8i-v3-pinctrl"
28		− "allwinner,sun8i-v3s-pinctrl"
29		− "allwinner,sun50i-a64-pinctrl"
30		− "allwinner,sun50i-a64-r-pinctrl"
31		− "allwinner,sun50i-h5-pinctrl"
32		− "allwinner,sun50i-h6-pinctrl"
33		− "allwinner,sun50i-h6-r-pinctrl"
34		− "allwinner,suniv-f1c100s-pinctrl"
35		− "nextthing,gr8-pinctrl"
36		−
37		−- reg: Should contain the register physical address and length for the
38		− pin controller.
39		−
40		−- clocks: phandle to the clocks feeding the pin controller:
41		− - "apb": the gated APB parent clock
42		− - "hosc": the high frequency oscillator in the system
43		− - "losc": the low frequency oscillator in the system
44		−
45		−Note: For backward compatibility reasons, the hosc and losc clocks are only
46		−required if you need to use the optional input-debounce property. Any new
47		−device tree should set them.
48		−
49		−Each pin bank, depending on the SoC, can have an associated regulator:
50		−
51		−- vcc-pa-supply: for the A10, A20, A31, A31s, A80 and R40 SoCs
52		−- vcc-pb-supply: for the A31, A31s, A80 and V3s SoCs
53		−- vcc-pc-supply: for the A10, A20, A31, A31s, A64, A80, H5, R40 and V3s SoCs
54		−- vcc-pd-supply: for the A23, A31, A31s, A64, A80, A83t, H3, H5 and R40 SoCs
55		−- vcc-pe-supply: for the A10, A20, A31, A31s, A64, A80, R40 and V3s SoCs
56		−- vcc-pf-supply: for the A10, A20, A31, A31s, A80, R40 and V3s SoCs
57		−- vcc-pg-supply: for the A10, A20, A31, A31s, A64, A80, H3, H5, R40 and V3s SoCs
58		−- vcc-ph-supply: for the A31, A31s and A80 SoCs
59		−- vcc-pl-supply: for the r-pinctrl of the A64, A80 and A83t SoCs
60		−- vcc-pm-supply: for the r-pinctrl of the A31, A31s and A80 SoCs
61		−
62		−Optional properties:
63		− - input-debounce: Array of debouncing periods in microseconds. One period per
64		− irq bank found in the controller. 0 if no setup required.
65		−
66		−
67		−Please refer to pinctrl-bindings.txt in this directory for details of the
68		−common pinctrl bindings used by client devices.
69		−
70		−A pinctrl node should contain at least one subnodes representing the
71		−pinctrl groups available on the machine. Each subnode will list the
72		−pins it needs, and how they should be configured, with regard to muxer
73		−configuration, drive strength and pullups. If one of these options is
74		−not set, its actual value will be unspecified.
75		−
76		−Allwinner A1X Pin Controller supports the generic pin multiplexing and
77		−configuration bindings. For details on each properties, you can refer to
78		− ./pinctrl-bindings.txt.
79		−
80		−Required sub-node properties:
81		− - pins
82		− - function
83		−
84		−Optional sub-node properties:
85		− - bias-disable
86		− - bias-pull-up
87		− - bias-pull-down
88		− - drive-strength
89		−
90		−*** Deprecated pin configuration and multiplexing binding
91		−
92		−Required subnode-properties:
93		−
94		−- allwinner,pins: List of strings containing the pin name.
95		−- allwinner,function: Function to mux the pins listed above to.
96		−
97		−Optional subnode-properties:
98		−- allwinner,drive: Integer. Represents the current sent to the pin
99		− 0: 10 mA
100		− 1: 20 mA
101		− 2: 30 mA
102		− 3: 40 mA
103		−- allwinner,pull: Integer.
104		− 0: No resistor
105		− 1: Pull-up resistor
106		− 2: Pull-down resistor
107		−
108		−Examples:
109		−
110		−pio: pinctrl@1c20800 {
111		− compatible = "allwinner,sun5i-a13-pinctrl";
112		− reg = <0x01c20800 0x400>;
113		− #address-cells = <1>;
114		− #size-cells = <0>;
115		−
116		− uart1_pins_a: uart1@0 {
117		− allwinner,pins = "PE10", "PE11";
118		− allwinner,function = "uart1";
119		− allwinner,drive = <0>;
120		− allwinner,pull = <0>;
121		− };
122		−
123		− uart1_pins_b: uart1@1 {
124		− allwinner,pins = "PG3", "PG4";
125		− allwinner,function = "uart1";
126		− allwinner,drive = <0>;
127		− allwinner,pull = <0>;
128		− };
129		−};
130		−
131		−
132		−GPIO and interrupt controller
133		−-----------------------------
134		−
135		−This hardware also acts as a GPIO controller and an interrupt
136		−controller.
137		−
138		−Consumers that would want to refer to one or the other (or both)
139		−should provide through the usual *-gpios and interrupts properties a
140		−cell with 3 arguments, first the number of the bank, then the pin
141		−inside that bank, and finally the flags for the GPIO/interrupts.
142		−
143		−Example:
144		−
145		−xio: gpio@38 {
146		− compatible = "nxp,pcf8574a";
147		− reg = <0x38>;
148		−
149		− gpio-controller;
150		− #gpio-cells = <2>;
151		−
152		− interrupt-parent = <&pio>;
153		− interrupts = <6 0 IRQ_TYPE_EDGE_FALLING>;
154		− interrupt-controller;
155		− #interrupt-cells = <2>;
156		−};
157		−
158		−reg_usb1_vbus: usb1-vbus {
159		− compatible = "regulator-fixed";
160		− regulator-name = "usb1-vbus";
161		− regulator-min-microvolt = <5000000>;
162		− regulator-max-microvolt = <5000000>;
163		− gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>;
164		−};

Documentation/devicetree/bindings/pinctrl/intel,lgm-pinctrl.yaml+116−0

@@ -0,0 +1,116 @@
	1	+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	2	+%YAML 1.2
	3	+---
	4	+$id: http://devicetree.org/schemas/bindings/pinctrl/intel,lgm-pinctrl.yaml#
	5	+$schema: http://devicetree.org/meta-schemas/core.yaml#
	6	+
	7	+title: Intel Lightning Mountain SoC pinmux & GPIO controller binding
	8	+
	9	+maintainers:
	10	+ - Rahul Tanwar <rahul.tanwar@linux.intel.com>
	11	+
	12	+description: \|
	13	+ Pinmux & GPIO controller controls pin multiplexing & configuration including
	14	+ GPIO function selection & GPIO attributes configuration.
	15	+
	16	+ Please refer to [1] for details of the common pinctrl bindings used by the
	17	+ client devices.
	18	+
	19	+ [1] Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
	20	+
	21	+properties:
	22	+ compatible:
	23	+ const: intel,lgm-io
	24	+
	25	+ reg:
	26	+ maxItems: 1
	27	+
	28	+# Client device subnode's properties
	29	+patternProperties:
	30	+ '-pins$':
	31	+ type: object
	32	+ description:
	33	+ Pinctrl node's client devices use subnodes for desired pin configuration.
	34	+ Client device subnodes use below standard properties.
	35	+
	36	+ properties:
	37	+ function:
	38	+ $ref: /schemas/types.yaml#/definitions/string
	39	+ description:
	40	+ A string containing the name of the function to mux to the group.
	41	+
	42	+ groups:
	43	+ $ref: /schemas/types.yaml#/definitions/string-array
	44	+ description:
	45	+ An array of strings identifying the list of groups.
	46	+
	47	+ pins:
	48	+ $ref: /schemas/types.yaml#/definitions/uint32-array
	49	+ description:
	50	+ List of pins to select with this function.
	51	+
	52	+ pinmux:
	53	+ description: The applicable mux group.
	54	+ allOf:
	55	+ - $ref: "/schemas/types.yaml#/definitions/uint32-array"
	56	+
	57	+ bias-pull-up:
	58	+ type: boolean
	59	+
	60	+ bias-pull-down:
	61	+ type: boolean
	62	+
	63	+ drive-strength:
	64	+ description: \|
	65	+ Selects the drive strength for the specified pins in mA.
	66	+ 0: 2 mA
	67	+ 1: 4 mA
	68	+ 2: 8 mA
	69	+ 3: 12 mA
	70	+ allOf:
	71	+ - $ref: /schemas/types.yaml#/definitions/uint32
	72	+ - enum: [0, 1, 2, 3]
	73	+
	74	+ slew-rate:
	75	+ type: boolean
	76	+ description: \|
	77	+ Sets slew rate for specified pins.
	78	+ 0: slow slew
	79	+ 1: fast slew
	80	+
	81	+ drive-open-drain:
	82	+ type: boolean
	83	+
	84	+ output-enable:
	85	+ type: boolean
	86	+
	87	+ required:
	88	+ - function
	89	+ - groups
	90	+
	91	+ additionalProperties: false
	92	+
	93	+required:
	94	+ - compatible
	95	+ - reg
	96	+
	97	+additionalProperties: false
	98	+
	99	+examples:
	100	+ # Pinmux controller node
	101	+ - \|
	102	+ pinctrl: pinctrl@e2880000 {
	103	+ compatible = "intel,lgm-pinctrl";
	104	+ reg = <0xe2880000 0x100000>;
	105	+
	106	+ uart0-pins {
	107	+ pins = <64>, /* UART_RX0 */
	108	+ <65>; /* UART_TX0 */
	109	+ function = "CONSOLE_UART0";
	110	+ pinmux = <1>,
	111	+ <1>;
	112	+ groups = "CONSOLE_UART0";
	113	+ };
	114	+ };
	115	+
	116	+...

Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt+1−0

@@ -15,6 +15,7 @@ Required properties for the root node: · 14 unmodified lines
15	15	"amlogic,meson-axg-aobus-pinctrl"
16	16	"amlogic,meson-g12a-periphs-pinctrl"
17	17	"amlogic,meson-g12a-aobus-pinctrl"
	18	+ "amlogic,meson-a1-periphs-pinctrl"
18	19	- reg: address and size of registers controlling irq functionality
19	20
20	21	=== GPIO sub-nodes ===

Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml+140−0

@@ -0,0 +1,140 @@
	1	+# SPDX-License-Identifier: GPL-2.0-only
	2	+%YAML 1.2
	3	+---
	4	+$id: http://devicetree.org/schemas/pinctrl/pincfg-node.yaml#
	5	+$schema: http://devicetree.org/meta-schemas/core.yaml#
	6	+
	7	+title: Generic pin configuration node schema
	8	+
	9	+maintainers:
	10	+ - Linus Walleij <linus.walleij@linaro.org>
	11	+
	12	+description:
	13	+ Many data items that are represented in a pin configuration node are common
	14	+ and generic. Pin control bindings should use the properties defined below
	15	+ where they are applicable; not all of these properties are relevant or useful
	16	+ for all hardware or binding structures. Each individual binding document
	17	+ should state which of these generic properties, if any, are used, and the
	18	+ structure of the DT nodes that contain these properties.
	19	+
	20	+properties:
	21	+ bias-disable:
	22	+ type: boolean
	23	+ description: disable any pin bias
	24	+
	25	+ bias-high-impedance:
	26	+ type: boolean
	27	+ description: high impedance mode ("third-state", "floating")
	28	+
	29	+ bias-bus-hold:
	30	+ type: boolean
	31	+ description: latch weakly
	32	+
	33	+ bias-pull-up:
	34	+ oneOf:
	35	+ - type: boolean
	36	+ - $ref: /schemas/types.yaml#/definitions/uint32
	37	+ description: pull up the pin. Takes as optional argument on hardware
	38	+ supporting it the pull strength in Ohm.
	39	+
	40	+ bias-pull-down:
	41	+ oneOf:
	42	+ - type: boolean
	43	+ - $ref: /schemas/types.yaml#/definitions/uint32
	44	+ description: pull down the pin. Takes as optional argument on hardware
	45	+ supporting it the pull strength in Ohm.
	46	+
	47	+ bias-pull-pin-default:
	48	+ oneOf:
	49	+ - type: boolean
	50	+ - $ref: /schemas/types.yaml#/definitions/uint32
	51	+ description: use pin-default pull state. Takes as optional argument on
	52	+ hardware supporting it the pull strength in Ohm.
	53	+
	54	+ drive-push-pull:
	55	+ type: boolean
	56	+ description: drive actively high and low
	57	+
	58	+ drive-open-drain:
	59	+ type: boolean
	60	+ description: drive with open drain
	61	+
	62	+ drive-open-source:
	63	+ type: boolean
	64	+ description: drive with open source
	65	+
	66	+ drive-strength:
	67	+ $ref: /schemas/types.yaml#/definitions/uint32
	68	+ description: sink or source at most X mA
	69	+
	70	+ drive-strength-microamp:
	71	+ description: sink or source at most X uA
	72	+
	73	+ input-enable:
	74	+ type: boolean
	75	+ description: enable input on pin (no effect on output, such as
	76	+ enabling an input buffer)
	77	+
	78	+ input-disable:
	79	+ type: boolean
	80	+ description: disable input on pin (no effect on output, such as
	81	+ disabling an input buffer)
	82	+
	83	+ input-schmitt-enable:
	84	+ type: boolean
	85	+ description: enable schmitt-trigger mode
	86	+
	87	+ input-schmitt-disable:
	88	+ type: boolean
	89	+ description: disable schmitt-trigger mode
	90	+
	91	+ input-debounce:
	92	+ $ref: /schemas/types.yaml#/definitions/uint32
	93	+ description: Takes the debounce time in usec as argument or 0 to disable
	94	+ debouncing
	95	+
	96	+ power-source:
	97	+ $ref: /schemas/types.yaml#/definitions/uint32
	98	+ description: select between different power supplies
	99	+
	100	+ low-power-enable:
	101	+ type: boolean
	102	+ description: enable low power mode
	103	+
	104	+ low-power-disable:
	105	+ type: boolean
	106	+ description: disable low power mode
	107	+
	108	+ output-disable:
	109	+ type: boolean
	110	+ description: disable output on a pin (such as disable an output buffer)
	111	+
	112	+ output-enable:
	113	+ type: boolean
	114	+ description: enable output on a pin without actively driving it
	115	+ (such as enabling an output buffer)
	116	+
	117	+ output-low:
	118	+ type: boolean
	119	+ description: set the pin to output mode with low level
	120	+
	121	+ output-high:
	122	+ type: boolean
	123	+ description: set the pin to output mode with high level
	124	+
	125	+ sleep-hardware-state:
	126	+ type: boolean
	127	+ description: indicate this is sleep related state which will be
	128	+ programmed into the registers for the sleep state.
	129	+
	130	+ slew-rate:
	131	+ $ref: /schemas/types.yaml#/definitions/uint32
	132	+ description: set the slew rate
	133	+
	134	+ skew-delay:
	135	+ $ref: /schemas/types.yaml#/definitions/uint32
	136	+ description:
	137	+ this affects the expected clock skew on input pins
	138	+ and the delay before latching a value to an output
	139	+ pin. Typically indicates how many double-inverters are
	140	+ used to delay the signal.

Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt+2−190

@@ -141,196 +141,8 @@ controller device. · 140 unmodified lines
141	141
142	142	== Generic pin multiplexing node content ==
143	143
144		−pin multiplexing nodes:
145		−
146		−function - the mux function to select
147		−groups - the list of groups to select with this function
148		− (either this or "pins" must be specified)
149		−pins - the list of pins to select with this function (either
150		− this or "groups" must be specified)
151		−
152		−Example:
153		−
154		−state_0_node_a {
155		− uart0 {
156		− function = "uart0";
157		− groups = "u0rxtx", "u0rtscts";
158		− };
159		−};
160		−state_1_node_a {
161		− spi0 {
162		− function = "spi0";
163		− groups = "spi0pins";
164		− };
165		−};
166		−state_2_node_a {
167		− function = "i2c0";
168		− pins = "mfio29", "mfio30";
169		−};
170		−
171		−Optionally an alternative binding can be used if more suitable depending on the
172		−pin controller hardware. For hardware where there is a large number of identical
173		−pin controller instances, naming each pin and function can easily become
174		−unmaintainable. This is especially the case if the same controller is used for
175		−different pins and functions depending on the SoC revision and packaging.
176		−
177		−For cases like this, the pin controller driver may use pinctrl-pin-array helper
178		−binding with a hardware based index and a number of pin configuration values:
179		−
180		−pincontroller {
181		− ... /* Standard DT properties for the device itself elided */
182		− #pinctrl-cells = <2>;
183		−
184		− state_0_node_a {
185		− pinctrl-pin-array = <
186		− 0 A_DELAY_PS(0) G_DELAY_PS(120)
187		− 4 A_DELAY_PS(0) G_DELAY_PS(360)
188		− ...
189		− >;
190		− };
191		− ...
192		−};
193		−
194		−Above #pinctrl-cells specifies the number of value cells in addition to the
195		−index of the registers. This is similar to the interrupts-extended binding with
196		−one exception. There is no need to specify the phandle for each entry as that
197		−is already known as the defined pins are always children of the pin controller
198		−node. Further having the phandle pointing to another pin controller would not
199		−currently work as the pinctrl framework uses named modes to group pins for each
200		−pin control device.
201		−
202		−The index for pinctrl-pin-array must relate to the hardware for the pinctrl
203		−registers, and must not be a virtual index of pin instances. The reason for
204		−this is to avoid mapping of the index in the dts files and the pin controller
205		−driver as it can change.
206		−
207		−For hardware where pin multiplexing configurations have to be specified for
208		−each single pin the number of required sub-nodes containing "pin" and
209		−"function" properties can quickly escalate and become hard to write and
210		−maintain.
211		−
212		−For cases like this, the pin controller driver may use the pinmux helper
213		−property, where the pin identifier is provided with mux configuration settings
214		−in a pinmux group. A pinmux group consists of the pin identifier and mux
215		−settings represented as a single integer or an array of integers.
216		−
217		−The pinmux property accepts an array of pinmux groups, each of them describing
218		−a single pin multiplexing configuration.
219		−
220		−pincontroller {
221		− state_0_node_a {
222		− pinmux = <PINMUX_GROUP>, <PINMUX_GROUP>, ...;
223		− };
224		−};
225		−
226		−Each individual pin controller driver bindings documentation shall specify
227		−how pin IDs and pin multiplexing configuration are defined and assembled
228		−together in a pinmux group.
	144	+See pinmux-node.yaml
229	145
230	146	== Generic pin configuration node content ==
231	147
232		−Many data items that are represented in a pin configuration node are common
233		−and generic. Pin control bindings should use the properties defined below
234		−where they are applicable; not all of these properties are relevant or useful
235		−for all hardware or binding structures. Each individual binding document
236		−should state which of these generic properties, if any, are used, and the
237		−structure of the DT nodes that contain these properties.
238		−
239		−Supported generic properties are:
240		−
241		−pins - the list of pins that properties in the node
242		− apply to (either this, "group" or "pinmux" has to be
243		− specified)
244		−group - the group to apply the properties to, if the driver
245		− supports configuration of whole groups rather than
246		− individual pins (either this, "pins" or "pinmux" has
247		− to be specified)
248		−pinmux - the list of numeric pin ids and their mux settings
249		− that properties in the node apply to (either this,
250		− "pins" or "groups" have to be specified)
251		−bias-disable - disable any pin bias
252		−bias-high-impedance - high impedance mode ("third-state", "floating")
253		−bias-bus-hold - latch weakly
254		−bias-pull-up - pull up the pin
255		−bias-pull-down - pull down the pin
256		−bias-pull-pin-default - use pin-default pull state
257		−drive-push-pull - drive actively high and low
258		−drive-open-drain - drive with open drain
259		−drive-open-source - drive with open source
260		−drive-strength - sink or source at most X mA
261		−drive-strength-microamp - sink or source at most X uA
262		−input-enable - enable input on pin (no effect on output, such as
263		− enabling an input buffer)
264		−input-disable - disable input on pin (no effect on output, such as
265		− disabling an input buffer)
266		−input-schmitt-enable - enable schmitt-trigger mode
267		−input-schmitt-disable - disable schmitt-trigger mode
268		−input-debounce - debounce mode with debound time X
269		−power-source - select between different power supplies
270		−low-power-enable - enable low power mode
271		−low-power-disable - disable low power mode
272		−output-disable - disable output on a pin (such as disable an output
273		− buffer)
274		−output-enable - enable output on a pin without actively driving it
275		− (such as enabling an output buffer)
276		−output-low - set the pin to output mode with low level
277		−output-high - set the pin to output mode with high level
278		−sleep-hardware-state - indicate this is sleep related state which will be programmed
279		− into the registers for the sleep state.
280		−slew-rate - set the slew rate
281		−skew-delay - this affects the expected clock skew on input pins
282		− and the delay before latching a value to an output
283		− pin. Typically indicates how many double-inverters are
284		− used to delay the signal.
285		−
286		−For example:
287		−
288		−state_0_node_a {
289		− cts_rxd {
290		− pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
291		− bias-pull-up;
292		− };
293		−};
294		−state_1_node_a {
295		− rts_txd {
296		− pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */
297		− output-high;
298		− };
299		−};
300		−state_2_node_a {
301		− foo {
302		− group = "foo-group";
303		− bias-pull-up;
304		− };
305		−};
306		−state_3_node_a {
307		− mux {
308		− pinmux = <GPIOx_PINm_MUXn>, <GPIOx_PINj_MUXk)>;
309		− input-enable;
310		− };
311		−};
312		−
313		−Some of the generic properties take arguments. For those that do, the
314		−arguments are described below.
315		−
316		−- pins takes a list of pin names or IDs as a required argument. The specific
317		− binding for the hardware defines:
318		− - Whether the entries are integers or strings, and their meaning.
319		−
320		−- pinmux takes a list of pin IDs and mux settings as required argument. The
321		− specific bindings for the hardware defines:
322		− - How pin IDs and mux settings are defined and assembled together in a single
323		− integer or an array of integers.
324		−
325		−- bias-pull-up, -down and -pin-default take as optional argument on hardware
326		− supporting it the pull strength in Ohm. bias-disable will disable the pull.
327		−
328		−- drive-strength takes as argument the target strength in mA.
329		−
330		−- drive-strength-microamp takes as argument the target strength in uA.
331		−
332		−- input-debounce takes the debounce time in usec as argument
333		− or 0 to disable debouncing
334		−
335		−More in-depth documentation on these parameters can be found in
336		−<include/linux/pinctrl/pinconf-generic.h>
	148	+See pincfg-node.yaml

Documentation/devicetree/bindings/pinctrl/pinmux-node.yaml+132−0

@@ -0,0 +1,132 @@
	1	+# SPDX-License-Identifier: GPL-2.0-only
	2	+%YAML 1.2
	3	+---
	4	+$id: http://devicetree.org/schemas/pinctrl/pinmux-node.yaml#
	5	+$schema: http://devicetree.org/meta-schemas/core.yaml#
	6	+
	7	+title: Generic pin multiplexing node schema
	8	+
	9	+maintainers:
	10	+ - Linus Walleij <linus.walleij@linaro.org>
	11	+
	12	+description: \|
	13	+ The contents of the pin configuration child nodes are defined by the binding
	14	+ for the individual pin controller device. The pin configuration nodes need not
	15	+ be direct children of the pin controller device; they may be grandchildren,
	16	+ for example. Whether this is legal, and whether there is any interaction
	17	+ between the child and intermediate parent nodes, is again defined entirely by
	18	+ the binding for the individual pin controller device.
	19	+
	20	+ While not required to be used, there are 3 generic forms of pin muxing nodes
	21	+ which pin controller devices can use.
	22	+
	23	+ pin multiplexing nodes:
	24	+
	25	+ Example:
	26	+
	27	+ state_0_node_a {
	28	+ uart0 {
	29	+ function = "uart0";
	30	+ groups = "u0rxtx", "u0rtscts";
	31	+ };
	32	+ };
	33	+ state_1_node_a {
	34	+ spi0 {
	35	+ function = "spi0";
	36	+ groups = "spi0pins";
	37	+ };
	38	+ };
	39	+ state_2_node_a {
	40	+ function = "i2c0";
	41	+ pins = "mfio29", "mfio30";
	42	+ };
	43	+
	44	+ Optionally an alternative binding can be used if more suitable depending on the
	45	+ pin controller hardware. For hardware where there is a large number of identical
	46	+ pin controller instances, naming each pin and function can easily become
	47	+ unmaintainable. This is especially the case if the same controller is used for
	48	+ different pins and functions depending on the SoC revision and packaging.
	49	+
	50	+ For cases like this, the pin controller driver may use pinctrl-pin-array helper
	51	+ binding with a hardware based index and a number of pin configuration values:
	52	+
	53	+ pincontroller {
	54	+ ... /* Standard DT properties for the device itself elided */
	55	+ #pinctrl-cells = <2>;
	56	+
	57	+ state_0_node_a {
	58	+ pinctrl-pin-array = <
	59	+ 0 A_DELAY_PS(0) G_DELAY_PS(120)
	60	+ 4 A_DELAY_PS(0) G_DELAY_PS(360)
	61	+ ...
	62	+ >;
	63	+ };
	64	+ ...
	65	+ };
	66	+
	67	+ Above #pinctrl-cells specifies the number of value cells in addition to the
	68	+ index of the registers. This is similar to the interrupts-extended binding with
	69	+ one exception. There is no need to specify the phandle for each entry as that
	70	+ is already known as the defined pins are always children of the pin controller
	71	+ node. Further having the phandle pointing to another pin controller would not
	72	+ currently work as the pinctrl framework uses named modes to group pins for each
	73	+ pin control device.
	74	+
	75	+ The index for pinctrl-pin-array must relate to the hardware for the pinctrl
	76	+ registers, and must not be a virtual index of pin instances. The reason for
	77	+ this is to avoid mapping of the index in the dts files and the pin controller
	78	+ driver as it can change.
	79	+
	80	+ For hardware where pin multiplexing configurations have to be specified for
	81	+ each single pin the number of required sub-nodes containing "pin" and
	82	+ "function" properties can quickly escalate and become hard to write and
	83	+ maintain.
	84	+
	85	+ For cases like this, the pin controller driver may use the pinmux helper
	86	+ property, where the pin identifier is provided with mux configuration settings
	87	+ in a pinmux group. A pinmux group consists of the pin identifier and mux
	88	+ settings represented as a single integer or an array of integers.
	89	+
	90	+ The pinmux property accepts an array of pinmux groups, each of them describing
	91	+ a single pin multiplexing configuration.
	92	+
	93	+ pincontroller {
	94	+ state_0_node_a {
	95	+ pinmux = <PINMUX_GROUP>, <PINMUX_GROUP>, ...;
	96	+ };
	97	+ };
	98	+
	99	+ Each individual pin controller driver bindings documentation shall specify
	100	+ how pin IDs and pin multiplexing configuration are defined and assembled
	101	+ together in a pinmux group.
	102	+
	103	+properties:
	104	+ function:
	105	+ $ref: /schemas/types.yaml#/definitions/string
	106	+ description: The mux function to select
	107	+
	108	+ pins:
	109	+ oneOf:
	110	+ - $ref: /schemas/types.yaml#/definitions/uint32-array
	111	+ - $ref: /schemas/types.yaml#/definitions/string-array
	112	+ description:
	113	+ The list of pin identifiers that properties in the node apply to. The
	114	+ specific binding for the hardware defines whether the entries are integers
	115	+ or strings, and their meaning.
	116	+
	117	+ group:
	118	+ $ref: /schemas/types.yaml#/definitions/string-array
	119	+ description:
	120	+ the group to apply the properties to, if the driver supports
	121	+ configuration of whole groups rather than individual pins (either
	122	+ this, "pins" or "pinmux" has to be specified)
	123	+
	124	+ pinmux:
	125	+ allOf:
	126	+ - $ref: /schemas/types.yaml#/definitions/uint32-array
	127	+ description:
	128	+ The list of numeric pin ids and their mux settings that properties in the
	129	+ node apply to (either this, "pins" or "groups" have to be specified)
	130	+
	131	+ pinctrl-pin-array:
	132	+ $ref: /schemas/types.yaml#/definitions/uint32-array

Documentation/devicetree/bindings/pinctrl/qcom,msm8976-pinctrl.txt+183−0

@@ -0,0 +1,183 @@
	1	+Qualcomm MSM8976 TLMM block
	2	+
	3	+This binding describes the Top Level Mode Multiplexer block found in the
	4	+MSM8956 and MSM8976 platforms.
	5	+
	6	+- compatible:
	7	+ Usage: required
	8	+ Value type: <string>
	9	+ Definition: must be "qcom,msm8976-pinctrl"
	10	+
	11	+- reg:
	12	+ Usage: required
	13	+ Value type: <prop-encoded-array>
	14	+ Definition: the base address and size of the TLMM register space.
	15	+
	16	+- interrupts:
	17	+ Usage: required
	18	+ Value type: <prop-encoded-array>
	19	+ Definition: should specify the TLMM summary IRQ.
	20	+
	21	+- interrupt-controller:
	22	+ Usage: required
	23	+ Value type: <none>
	24	+ Definition: identifies this node as an interrupt controller
	25	+
	26	+- #interrupt-cells:
	27	+ Usage: required
	28	+ Value type: <u32>
	29	+ Definition: must be 2. Specifying the pin number and flags, as defined
	30	+ in <dt-bindings/interrupt-controller/irq.h>
	31	+
	32	+- gpio-controller:
	33	+ Usage: required
	34	+ Value type: <none>
	35	+ Definition: identifies this node as a gpio controller
	36	+
	37	+- #gpio-cells:
	38	+ Usage: required
	39	+ Value type: <u32>
	40	+ Definition: must be 2. Specifying the pin number and flags, as defined
	41	+ in <dt-bindings/gpio/gpio.h>
	42	+
	43	+- gpio-ranges:
	44	+ Usage: required
	45	+ Definition: see ../gpio/gpio.txt
	46	+
	47	+- gpio-reserved-ranges:
	48	+ Usage: optional
	49	+ Definition: see ../gpio/gpio.txt
	50	+
	51	+Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
	52	+a general description of GPIO and interrupt bindings.
	53	+
	54	+Please refer to pinctrl-bindings.txt in this directory for details of the
	55	+common pinctrl bindings used by client devices, including the meaning of the
	56	+phrase "pin configuration node".
	57	+
	58	+The pin configuration nodes act as a container for an arbitrary number of
	59	+subnodes. Each of these subnodes represents some desired configuration for a
	60	+pin, a group, or a list of pins or groups. This configuration can include the
	61	+mux function to select on those pin(s)/group(s), and various pin configuration
	62	+parameters, such as pull-up, drive strength, etc.
	63	+
	64	+
	65	+PIN CONFIGURATION NODES:
	66	+
	67	+The name of each subnode is not important; all subnodes should be enumerated
	68	+and processed purely based on their content.
	69	+
	70	+Each subnode only affects those parameters that are explicitly listed. In
	71	+other words, a subnode that lists a mux function but no pin configuration
	72	+parameters implies no information about any pin configuration parameters.
	73	+Similarly, a pin subnode that describes a pullup parameter implies no
	74	+information about e.g. the mux function.
	75	+
	76	+
	77	+The following generic properties as defined in pinctrl-bindings.txt are valid
	78	+to specify in a pin configuration subnode:
	79	+
	80	+- pins:
	81	+ Usage: required
	82	+ Value type: <string-array>
	83	+ Definition: List of gpio pins affected by the properties specified in
	84	+ this subnode.
	85	+
	86	+ Valid pins are:
	87	+ gpio0-gpio145
	88	+ Supports mux, bias and drive-strength
	89	+
	90	+ sdc1_clk, sdc1_cmd, sdc1_data,
	91	+ sdc2_clk, sdc2_cmd, sdc2_data,
	92	+ sdc3_clk, sdc3_cmd, sdc3_data
	93	+ Supports bias and drive-strength
	94	+
	95	+- function:
	96	+ Usage: required
	97	+ Value type: <string>
	98	+ Definition: Specify the alternative function to be configured for the
	99	+ specified pins. Functions are only valid for gpio pins.
	100	+ Valid values are:
	101	+
	102	+ gpio, blsp_uart1, blsp_spi1, smb_int, blsp_i2c1, blsp_spi2,
	103	+ blsp_uart2, blsp_i2c2, gcc_gp1_clk_b, blsp_spi3,
	104	+ qdss_tracedata_b, blsp_i2c3, gcc_gp2_clk_b, gcc_gp3_clk_b,
	105	+ blsp_spi4, cap_int, blsp_i2c4, blsp_spi5, blsp_uart5,
	106	+ qdss_traceclk_a, m_voc, blsp_i2c5, qdss_tracectl_a,
	107	+ qdss_tracedata_a, blsp_spi6, blsp_uart6, qdss_tracectl_b,
	108	+ blsp_i2c6, qdss_traceclk_b, mdp_vsync, pri_mi2s_mclk_a,
	109	+ sec_mi2s_mclk_a, cam_mclk, cci0_i2c, cci1_i2c, blsp1_spi,
	110	+ blsp3_spi, gcc_gp1_clk_a, gcc_gp2_clk_a, gcc_gp3_clk_a,
	111	+ uim_batt, sd_write, uim1_data, uim1_clk, uim1_reset,
	112	+ uim1_present, uim2_data, uim2_clk, uim2_reset,
	113	+ uim2_present, ts_xvdd, mipi_dsi0, us_euro, ts_resout,
	114	+ ts_sample, sec_mi2s_mclk_b, pri_mi2s, codec_reset,
	115	+ cdc_pdm0, us_emitter, pri_mi2s_mclk_b, pri_mi2s_mclk_c,
	116	+ lpass_slimbus, lpass_slimbus0, lpass_slimbus1, codec_int1,
	117	+ codec_int2, wcss_bt, sdc3, wcss_wlan2, wcss_wlan1,
	118	+ wcss_wlan0, wcss_wlan, wcss_fm, key_volp, key_snapshot,
	119	+ key_focus, key_home, pwr_down, dmic0_clk, hdmi_int,
	120	+ dmic0_data, wsa_vi, wsa_en, blsp_spi8, wsa_irq, blsp_i2c8,
	121	+ pa_indicator, modem_tsync, ssbi_wtr1, gsm1_tx, gsm0_tx,
	122	+ sdcard_det, sec_mi2s, ss_switch,
	123	+
	124	+- bias-disable:
	125	+ Usage: optional
	126	+ Value type: <none>
	127	+ Definition: The specified pins should be configured as no pull.
	128	+
	129	+- bias-pull-down:
	130	+ Usage: optional
	131	+ Value type: <none>
	132	+ Definition: The specified pins should be configured as pull down.
	133	+
	134	+- bias-pull-up:
	135	+ Usage: optional
	136	+ Value type: <none>
	137	+ Definition: The specified pins should be configured as pull up.
	138	+
	139	+- output-high:
	140	+ Usage: optional
	141	+ Value type: <none>
	142	+ Definition: The specified pins are configured in output mode, driven
	143	+ high.
	144	+ Not valid for sdc pins.
	145	+
	146	+- output-low:
	147	+ Usage: optional
	148	+ Value type: <none>
	149	+ Definition: The specified pins are configured in output mode, driven
	150	+ low.
	151	+ Not valid for sdc pins.
	152	+
	153	+- drive-strength:
	154	+ Usage: optional
	155	+ Value type: <u32>
	156	+ Definition: Selects the drive strength for the specified pins, in mA.
	157	+ Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
	158	+
	159	+Example:
	160	+
	161	+ tlmm: pinctrl@1000000 {
	162	+ compatible = "qcom,msm8976-pinctrl";
	163	+ reg = <0x1000000 0x300000>;
	164	+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
	165	+ gpio-controller;
	166	+ #gpio-cells = <2>;
	167	+ gpio-ranges = <&tlmm 0 0 145>;
	168	+ interrupt-controller;
	169	+ #interrupt-cells = <2>;
	170	+
	171	+ blsp1_uart2_active: blsp1_uart2_active {
	172	+ mux {
	173	+ pins = "gpio4", "gpio5", "gpio6", "gpio7";
	174	+ function = "blsp_uart2";
	175	+ };
	176	+
	177	+ config {
	178	+ pins = "gpio4", "gpio5", "gpio6", "gpio7";
	179	+ drive-strength = <2>;
	180	+ bias-disable;
	181	+ };
	182	+ };
	183	+ };

Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt+8−0

@@ -15,14 +15,18 @@ PMIC's from Qualcomm. · 14 unmodified lines
15	15	"qcom,pm8917-gpio"
16	16	"qcom,pm8921-gpio"
17	17	"qcom,pm8941-gpio"
	18	+ "qcom,pm8950-gpio"
18	19	"qcom,pm8994-gpio"
19	20	"qcom,pm8998-gpio"
20	21	"qcom,pma8084-gpio"
	22	+ "qcom,pmi8950-gpio"
21	23	"qcom,pmi8994-gpio"
22	24	"qcom,pmi8998-gpio"
23	25	"qcom,pms405-gpio"
24	26	"qcom,pm8150-gpio"
25	27	"qcom,pm8150b-gpio"
	28	+ "qcom,pm6150-gpio"
	29	+ "qcom,pm6150l-gpio"
26	30
27	31	And must contain either "qcom,spmi-gpio" or "qcom,ssbi-gpio"
28	32	if the device is on an spmi bus or an ssbi bus respectively
@@ -91,15 +95,19 @@ to specify in a pin configuration subnode: · 62 unmodified lines
91	95	gpio1-gpio38 for pm8917
92	96	gpio1-gpio44 for pm8921
93	97	gpio1-gpio36 for pm8941
	98	+ gpio1-gpio8 for pm8950 (hole on gpio3)
94	99	gpio1-gpio22 for pm8994
95	100	gpio1-gpio26 for pm8998
96	101	gpio1-gpio22 for pma8084
	102	+ gpio1-gpio2 for pmi8950
97	103	gpio1-gpio10 for pmi8994
98	104	gpio1-gpio12 for pms405 (holes on gpio1, gpio9 and gpio10)
99	105	gpio1-gpio10 for pm8150 (holes on gpio2, gpio5, gpio7
100	106	and gpio8)
101	107	gpio1-gpio12 for pm8150b (holes on gpio3, gpio4, gpio7)
102	108	gpio1-gpio12 for pm8150l (hole on gpio7)
	109	+ gpio1-gpio10 for pm6150
	110	+ gpio1-gpio12 for pm6150l
103	111
104	112	- function:
105	113	Usage: required

Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt+4−0

@@ -16,6 +16,8 @@ of PMIC's from Qualcomm. · 15 unmodified lines
16	16	"qcom,pm8917-mpp",
17	17	"qcom,pm8921-mpp",
18	18	"qcom,pm8941-mpp",
	19	+ "qcom,pm8950-mpp",
	20	+ "qcom,pmi8950-mpp",
19	21	"qcom,pm8994-mpp",
20	22	"qcom,pma8084-mpp",
21	23
@@ -80,6 +82,8 @@ to specify in a pin configuration subnode: · 58 unmodified lines
80	82	mpp1-mpp4 for pm8841
81	83	mpp1-mpp4 for pm8916
82	84	mpp1-mpp8 for pm8941
	85	+ mpp1-mpp4 for pm8950
	86	+ mpp1-mpp4 for pmi8950
83	87	mpp1-mpp4 for pma8084
84	88
85	89	- function:

Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt+3−1

@@ -18,6 +18,7 @@ Required Properties: · 17 unmodified lines
18	18	- "renesas,pfc-r8a7745": for R8A7745 (RZ/G1E) compatible pin-controller.
19	19	- "renesas,pfc-r8a77470": for R8A77470 (RZ/G1C) compatible pin-controller.
20	20	- "renesas,pfc-r8a774a1": for R8A774A1 (RZ/G2M) compatible pin-controller.
	21	+ - "renesas,pfc-r8a774b1": for R8A774B1 (RZ/G2N) compatible pin-controller.
21	22	- "renesas,pfc-r8a774c0": for R8A774C0 (RZ/G2E) compatible pin-controller.
22	23	- "renesas,pfc-r8a7778": for R8A7778 (R-Car M1) compatible pin-controller.
23	24	- "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller.
@@ -27,7 +28,8 @@ Required Properties: · 3 unmodified lines
27	28	- "renesas,pfc-r8a7793": for R8A7793 (R-Car M2-N) compatible pin-controller.
28	29	- "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller.
29	30	- "renesas,pfc-r8a7795": for R8A7795 (R-Car H3) compatible pin-controller.
30		− - "renesas,pfc-r8a7796": for R8A7796 (R-Car M3-W) compatible pin-controller.
	31	+ - "renesas,pfc-r8a7796": for R8A77960 (R-Car M3-W) compatible pin-controller.
	32	+ - "renesas,pfc-r8a77961": for R8A77961 (R-Car M3-W+) compatible pin-controller.
31	33	- "renesas,pfc-r8a77965": for R8A77965 (R-Car M3-N) compatible pin-controller.
32	34	- "renesas,pfc-r8a77970": for R8A77970 (R-Car V3M) compatible pin-controller.
33	35	- "renesas,pfc-r8a77980": for R8A77980 (R-Car V3H) compatible pin-controller.

Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt+1−0

@@ -29,6 +29,7 @@ Required properties for iomux controller: · 28 unmodified lines
29	29	"rockchip,rk3188-pinctrl": for Rockchip RK3188
30	30	"rockchip,rk3228-pinctrl": for Rockchip RK3228
31	31	"rockchip,rk3288-pinctrl": for Rockchip RK3288
	32	+ "rockchip,rk3308-pinctrl": for Rockchip RK3308
32	33	"rockchip,rk3328-pinctrl": for Rockchip RK3328
33	34	"rockchip,rk3368-pinctrl": for Rockchip RK3368
34	35	"rockchip,rk3399-pinctrl": for Rockchip RK3399

MAINTAINERS+1−1

@@ -12975,7 +12975,7 @@ F: Documentation/devicetree/bindings/pinctrl/fsl,* · 12974 unmodified lines
12975	12975
12976	12976	PIN CONTROLLER - INTEL
12977	12977	M: Mika Westerberg <mika.westerberg@linux.intel.com>
12978		−M: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
	12978	+M: Andy Shevchenko <andy@kernel.org>
12979	12979	T: git git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel.git
12980	12980	S: Maintained
12981	12981	F: drivers/pinctrl/intel/

arch/sh/include/cpu-sh4/cpu/sh7734.h+1−1

@@ -134,7 +134,7 @@ enum { · 133 unmodified lines
134	134	GPIO_FN_EX_WAIT1, GPIO_FN_SD1_DAT0_A, GPIO_FN_DREQ2, GPIO_FN_CAN1_TX_C,
135	135	GPIO_FN_ET0_LINK_C, GPIO_FN_ET0_ETXD5_A,
136	136	GPIO_FN_EX_WAIT0, GPIO_FN_TCLK1_B,
137		− GPIO_FN_RD_WR, GPIO_FN_TCLK0,
	137	+ GPIO_FN_RD_WR, GPIO_FN_TCLK0, GPIO_FN_CAN_CLK_B, GPIO_FN_ET0_ETXD4,
138	138	GPIO_FN_EX_CS5, GPIO_FN_SD1_CMD_A, GPIO_FN_ATADIR, GPIO_FN_QSSL_B,
139	139	GPIO_FN_ET0_ETXD3_A,
140	140	GPIO_FN_EX_CS4, GPIO_FN_SD1_WP_A, GPIO_FN_ATAWR, GPIO_FN_QMI_QIO1_B,

drivers/pinctrl/Kconfig+27−9

@@ -32,15 +32,15 @@ config DEBUG_PINCTRL · 31 unmodified lines
32	32	Say Y here to add some extra checks and diagnostics to PINCTRL calls.
33	33
34	34	config PINCTRL_ARTPEC6
35		− bool "Axis ARTPEC-6 pin controller driver"
36		− depends on MACH_ARTPEC6
37		− select PINMUX
38		− select GENERIC_PINCONF
39		− help
40		− This is the driver for the Axis ARTPEC-6 pin controller. This driver
41		− supports pin function multiplexing as well as pin bias and drive
42		− strength configuration. Device tree integration instructions can be
43		− found in Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt
	35	+ bool "Axis ARTPEC-6 pin controller driver"
	36	+ depends on MACH_ARTPEC6
	37	+ select PINMUX
	38	+ select GENERIC_PINCONF
	39	+ help
	40	+ This is the driver for the Axis ARTPEC-6 pin controller. This driver
	41	+ supports pin function multiplexing as well as pin bias and drive
	42	+ strength configuration. Device tree integration instructions can be
	43	+ found in Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt
44	44
45	45	config PINCTRL_AS3722
46	46	tristate "Pinctrl and GPIO driver for ams AS3722 PMIC"
@@ -420,4 +420,22 @@ config PINCTRL_TB10X · 373 unmodified lines
420	420	depends on OF && ARC_PLAT_TB10X
421	421	select GPIOLIB
422	422
	423	+config PINCTRL_EQUILIBRIUM
	424	+ tristate "Generic pinctrl and GPIO driver for Intel Lightning Mountain SoC"
	425	+ select PINMUX
	426	+ select PINCONF
	427	+ select GPIOLIB
	428	+ select GPIO_GENERIC
	429	+ select GPIOLIB_IRQCHIP
	430	+ select GENERIC_PINCONF
	431	+ select GENERIC_PINCTRL_GROUPS
	432	+ select GENERIC_PINMUX_FUNCTIONS
	433	+
	434	+ help
	435	+ Equilibrium pinctrl driver is a pinctrl & GPIO driver for Intel Lightning
	436	+ Mountain network processor SoC that supports both the linux GPIO and pin
	437	+ control frameworks. It provides interfaces to setup pinmux, assign desired
	438	+ pin functions, configure GPIO attributes for LGM SoC pins. Pinmux and
	439	+ pinconf settings are retrieved from device tree.
	440	+
423	441	endif

drivers/pinctrl/Makefile+1−0

@@ -46,6 +46,7 @@ obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o · 45 unmodified lines
46	46	obj-$(CONFIG_PINCTRL_INGENIC) += pinctrl-ingenic.o
47	47	obj-$(CONFIG_PINCTRL_RK805) += pinctrl-rk805.o
48	48	obj-$(CONFIG_PINCTRL_OCELOT) += pinctrl-ocelot.o
	49	+obj-$(CONFIG_PINCTRL_EQUILIBRIUM) += pinctrl-equilibrium.o
49	50
50	51	obj-y += actions/
51	52	obj-$(CONFIG_ARCH_ASPEED) += aspeed/

drivers/pinctrl/actions/pinctrl-owl.c+1−3

@@ -915,7 +915,6 @@ static int owl_gpio_init(struct owl_pinctrl *pctrl) · 914 unmodified lines
915	915	int owl_pinctrl_probe(struct platform_device *pdev,
916	916	struct owl_pinctrl_soc_data *soc_data)
917	917	{
918		− struct resource *res;
919	918	struct owl_pinctrl *pctrl;
920	919	int ret, i;
921	920
@@ -923,8 +922,7 @@ int owl_pinctrl_probe(struct platform_device *pdev, · 1 unmodified line
923	922	if (!pctrl)
924	923	return -ENOMEM;
925	924
926		− res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
927		− pctrl->base = devm_ioremap_resource(&pdev->dev, res);
	925	+ pctrl->base = devm_platform_ioremap_resource(pdev, 0);
928	926	if (IS_ERR(pctrl->base))
929	927	return PTR_ERR(pctrl->base);
930	928

drivers/pinctrl/bcm/pinctrl-bcm281xx.c+1−3

@@ -1400,12 +1400,10 @@ static struct pinctrl_desc bcm281xx_pinctrl_desc = { · 1399 unmodified lines
1400	1400	static int __init bcm281xx_pinctrl_probe(struct platform_device *pdev)
1401	1401	{
1402	1402	struct bcm281xx_pinctrl_data *pdata = &bcm281xx_pinctrl;
1403		− struct resource *res;
1404	1403	struct pinctrl_dev *pctl;
1405	1404
1406	1405	/* So far We can assume there is only 1 bank of registers */
1407		− res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1408		− pdata->reg_base = devm_ioremap_resource(&pdev->dev, res);
	1406	+ pdata->reg_base = devm_platform_ioremap_resource(pdev, 0);
1409	1407	if (IS_ERR(pdata->reg_base)) {
1410	1408	dev_err(&pdev->dev, "Failed to ioremap MEM resource\n");
1411	1409	return -ENODEV;

drivers/pinctrl/bcm/pinctrl-cygnus-mux.c+2−5

@@ -940,7 +940,6 @@ static int cygnus_mux_log_init(struct cygnus_pinctrl *pinctrl) · 939 unmodified lines
940	940	static int cygnus_pinmux_probe(struct platform_device *pdev)
941	941	{
942	942	struct cygnus_pinctrl *pinctrl;
943		− struct resource *res;
944	943	int i, ret;
945	944	struct pinctrl_pin_desc *pins;
946	945	unsigned num_pins = ARRAY_SIZE(cygnus_pins);
@@ -953,15 +952,13 @@ static int cygnus_pinmux_probe(struct platform_device *pdev) · 6 unmodified lines
953	952	platform_set_drvdata(pdev, pinctrl);
954	953	spin_lock_init(&pinctrl->lock);
955	954
956		− res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
957		− pinctrl->base0 = devm_ioremap_resource(&pdev->dev, res);
	955	+ pinctrl->base0 = devm_platform_ioremap_resource(pdev, 0);
958	956	if (IS_ERR(pinctrl->base0)) {
959	957	dev_err(&pdev->dev, "unable to map I/O space\n");
960	958	return PTR_ERR(pinctrl->base0);
961	959	}
962	960
963		− res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
964		− pinctrl->base1 = devm_ioremap_resource(&pdev->dev, res);
	961	+ pinctrl->base1 = devm_platform_ioremap_resource(pdev, 1);
965	962	if (IS_ERR(pinctrl->base1)) {
966	963	dev_err(&pdev->dev, "unable to map I/O space\n");
967	964	return PTR_ERR(pinctrl->base1);

drivers/pinctrl/bcm/pinctrl-iproc-gpio.c+2−3

@@ -795,8 +795,7 @@ static int iproc_gpio_probe(struct platform_device *pdev) · 794 unmodified lines
795	795	chip->dev = dev;
796	796	platform_set_drvdata(pdev, chip);
797	797
798		− res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
799		− chip->base = devm_ioremap_resource(dev, res);
	798	+ chip->base = devm_platform_ioremap_resource(pdev, 0);
800	799	if (IS_ERR(chip->base)) {
801	800	dev_err(dev, "unable to map I/O memory\n");
802	801	return PTR_ERR(chip->base);
@@ -850,7 +849,7 @@ static int iproc_gpio_probe(struct platform_device *pdev) · 47 unmodified lines
850	849	struct gpio_irq_chip *girq;
851	850
852	851	irqc = &chip->irqchip;
853		− irqc->name = "bcm-iproc-gpio";
	852	+ irqc->name = dev_name(dev);
854	853	irqc->irq_ack = iproc_gpio_irq_ack;
855	854	irqc->irq_mask = iproc_gpio_irq_mask;
856	855	irqc->irq_unmask = iproc_gpio_irq_unmask;

drivers/pinctrl/bcm/pinctrl-ns2-mux.c+2−4

@@ -1042,8 +1042,7 @@ static int ns2_pinmux_probe(struct platform_device *pdev) · 1041 unmodified lines
1042	1042	platform_set_drvdata(pdev, pinctrl);
1043	1043	spin_lock_init(&pinctrl->lock);
1044	1044
1045		− res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1046		− pinctrl->base0 = devm_ioremap_resource(&pdev->dev, res);
	1045	+ pinctrl->base0 = devm_platform_ioremap_resource(pdev, 0);
1047	1046	if (IS_ERR(pinctrl->base0))
1048	1047	return PTR_ERR(pinctrl->base0);
1049	1048
@@ -1057,8 +1056,7 @@ static int ns2_pinmux_probe(struct platform_device *pdev) · 7 unmodified lines
1057	1056	return -ENOMEM;
1058	1057	}
1059	1058
1060		− res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1061		− pinctrl->pinconf_base = devm_ioremap_resource(&pdev->dev, res);
	1059	+ pinctrl->pinconf_base = devm_platform_ioremap_resource(pdev, 2);
1062	1060	if (IS_ERR(pinctrl->pinconf_base))
1063	1061	return PTR_ERR(pinctrl->pinconf_base);
1064	1062

drivers/pinctrl/bcm/pinctrl-nsp-gpio.c+56−63

@@ -64,17 +64,16 @@ · 63 unmodified lines
64	64	* @gc: GPIO chip
65	65	* @pctl: pointer to pinctrl_dev
66	66	* @pctldesc: pinctrl descriptor
67		− * @irq_domain: pointer to irq domain
68	67	* @lock: lock to protect access to I/O registers
69	68	*/
70	69	struct nsp_gpio {
71	70	struct device *dev;
72	71	void __iomem *base;
73	72	void __iomem *io_ctrl;
	73	+ struct irq_chip irqchip;
74	74	struct gpio_chip gc;
75	75	struct pinctrl_dev *pctl;
76	76	struct pinctrl_desc pctldesc;
77		− struct irq_domain *irq_domain;
78	77	raw_spinlock_t lock;
79	78	};
80	79
@@ -136,8 +135,8 @@ static inline bool nsp_get_bit(struct nsp_gpio *chip, enum base_type address, · 55 unmodified lines
136	135
137	136	static irqreturn_t nsp_gpio_irq_handler(int irq, void *data)
138	137	{
139		− struct nsp_gpio chip = (struct nsp_gpio )data;
140		− struct gpio_chip gc = chip->gc;
	138	+ struct gpio_chip gc = (struct gpio_chip )data;
	139	+ struct nsp_gpio *chip = gpiochip_get_data(gc);
141	140	int bit;
142	141	unsigned long int_bits = 0;
143	142	u32 int_status;
@@ -155,14 +154,14 @@ static irqreturn_t nsp_gpio_irq_handler(int irq, void *data) · 11 unmodified lines
155	154	level &= readl(chip->base + NSP_GPIO_INT_MASK);
156	155	int_bits = level \| event;
157	156
158		− for_each_set_bit(bit, &int_bits, gc.ngpio) {
	157	+ for_each_set_bit(bit, &int_bits, gc->ngpio) {
159	158	/*
160	159	* Clear the interrupt before invoking the
161	160	* handler, so we do not leave any window
162	161	*/
163	162	writel(BIT(bit), chip->base + NSP_GPIO_EVENT);
164	163	generic_handle_irq(
165		− irq_linear_revmap(chip->irq_domain, bit));
	164	+ irq_linear_revmap(gc->irq.domain, bit));
166	165	}
167	166	}
168	167
@@ -171,7 +170,8 @@ static irqreturn_t nsp_gpio_irq_handler(int irq, void *data) · 2 unmodified lines
171	170
172	171	static void nsp_gpio_irq_ack(struct irq_data *d)
173	172	{
174		− struct nsp_gpio *chip = irq_data_get_irq_chip_data(d);
	173	+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	174	+ struct nsp_gpio *chip = gpiochip_get_data(gc);
175	175	unsigned gpio = d->hwirq;
176	176	u32 val = BIT(gpio);
177	177	u32 trigger_type;
@@ -189,7 +189,8 @@ static void nsp_gpio_irq_ack(struct irq_data *d) · 11 unmodified lines
189	189	*/
190	190	static void nsp_gpio_irq_set_mask(struct irq_data *d, bool unmask)
191	191	{
192		− struct nsp_gpio *chip = irq_data_get_irq_chip_data(d);
	192	+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	193	+ struct nsp_gpio *chip = gpiochip_get_data(gc);
193	194	unsigned gpio = d->hwirq;
194	195	u32 trigger_type;
195	196
@@ -202,7 +203,8 @@ static void nsp_gpio_irq_set_mask(struct irq_data *d, bool unmask) · 6 unmodified lines
202	203
203	204	static void nsp_gpio_irq_mask(struct irq_data *d)
204	205	{
205		− struct nsp_gpio *chip = irq_data_get_irq_chip_data(d);
	206	+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	207	+ struct nsp_gpio *chip = gpiochip_get_data(gc);
206	208	unsigned long flags;
207	209
208	210	raw_spin_lock_irqsave(&chip->lock, flags);
@@ -212,7 +214,8 @@ static void nsp_gpio_irq_mask(struct irq_data *d) · 3 unmodified lines
212	214
213	215	static void nsp_gpio_irq_unmask(struct irq_data *d)
214	216	{
215		− struct nsp_gpio *chip = irq_data_get_irq_chip_data(d);
	217	+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	218	+ struct nsp_gpio *chip = gpiochip_get_data(gc);
216	219	unsigned long flags;
217	220
218	221	raw_spin_lock_irqsave(&chip->lock, flags);
@@ -222,7 +225,8 @@ static void nsp_gpio_irq_unmask(struct irq_data *d) · 3 unmodified lines
222	225
223	226	static int nsp_gpio_irq_set_type(struct irq_data *d, unsigned int type)
224	227	{
225		− struct nsp_gpio *chip = irq_data_get_irq_chip_data(d);
	228	+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	229	+ struct nsp_gpio *chip = gpiochip_get_data(gc);
226	230	unsigned gpio = d->hwirq;
227	231	bool level_low;
228	232	bool falling;
@@ -265,16 +269,6 @@ static int nsp_gpio_irq_set_type(struct irq_data *d, unsigned int type) · 36 unmodified lines
265	269	return 0;
266	270	}
267	271
268		−static struct irq_chip nsp_gpio_irq_chip = {
269		− .name = "gpio-a",
270		− .irq_enable = nsp_gpio_irq_unmask,
271		− .irq_disable = nsp_gpio_irq_mask,
272		− .irq_ack = nsp_gpio_irq_ack,
273		− .irq_mask = nsp_gpio_irq_mask,
274		− .irq_unmask = nsp_gpio_irq_unmask,
275		− .irq_set_type = nsp_gpio_irq_set_type,
276		−};
277		−
278	272	static int nsp_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
279	273	{
280	274	struct nsp_gpio *chip = gpiochip_get_data(gc);
@@ -303,30 +297,36 @@ static int nsp_gpio_direction_output(struct gpio_chip *gc, unsigned gpio, · 22 unmodified lines
303	297	return 0;
304	298	}
305	299
306		−static void nsp_gpio_set(struct gpio_chip *gc, unsigned gpio, int val)
	300	+static int nsp_gpio_get_direction(struct gpio_chip *gc, unsigned gpio)
307	301	{
308	302	struct nsp_gpio *chip = gpiochip_get_data(gc);
309	303	unsigned long flags;
	304	+ int val;
310	305
311	306	raw_spin_lock_irqsave(&chip->lock, flags);
312		− nsp_set_bit(chip, REG, NSP_GPIO_DATA_OUT, gpio, !!(val));
	307	+ val = nsp_get_bit(chip, REG, NSP_GPIO_OUT_EN, gpio);
313	308	raw_spin_unlock_irqrestore(&chip->lock, flags);
314	309
315		− dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val);
	310	+ return !val;
316	311	}
317	312
318		−static int nsp_gpio_get(struct gpio_chip *gc, unsigned gpio)
	313	+static void nsp_gpio_set(struct gpio_chip *gc, unsigned gpio, int val)
319	314	{
320	315	struct nsp_gpio *chip = gpiochip_get_data(gc);
	316	+ unsigned long flags;
321	317
322		− return !!(readl(chip->base + NSP_GPIO_DATA_IN) & BIT(gpio));
	318	+ raw_spin_lock_irqsave(&chip->lock, flags);
	319	+ nsp_set_bit(chip, REG, NSP_GPIO_DATA_OUT, gpio, !!(val));
	320	+ raw_spin_unlock_irqrestore(&chip->lock, flags);
	321	+
	322	+ dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val);
323	323	}
324	324
325		−static int nsp_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
	325	+static int nsp_gpio_get(struct gpio_chip *gc, unsigned gpio)
326	326	{
327	327	struct nsp_gpio *chip = gpiochip_get_data(gc);
328	328
329		− return irq_linear_revmap(chip->irq_domain, offset);
	329	+ return !!(readl(chip->base + NSP_GPIO_DATA_IN) & BIT(gpio));
330	330	}
331	331
332	332	static int nsp_get_groups_count(struct pinctrl_dev *pctldev)
@@ -613,10 +613,9 @@ static const struct of_device_id nsp_gpio_of_match[] = { · 280 unmodified lines
613	613	static int nsp_gpio_probe(struct platform_device *pdev)
614	614	{
615	615	struct device *dev = &pdev->dev;
616		− struct resource *res;
617	616	struct nsp_gpio *chip;
618	617	struct gpio_chip *gc;
619		− u32 val, count;
	618	+ u32 val;
620	619	int irq, ret;
621	620
622	621	if (of_property_read_u32(pdev->dev.of_node, "ngpios", &val)) {
@@ -631,15 +630,13 @@ static int nsp_gpio_probe(struct platform_device *pdev) · 8 unmodified lines
631	630	chip->dev = dev;
632	631	platform_set_drvdata(pdev, chip);
633	632
634		− res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
635		− chip->base = devm_ioremap_resource(dev, res);
	633	+ chip->base = devm_platform_ioremap_resource(pdev, 0);
636	634	if (IS_ERR(chip->base)) {
637	635	dev_err(dev, "unable to map I/O memory\n");
638	636	return PTR_ERR(chip->base);
639	637	}
640	638
641		− res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
642		− chip->io_ctrl = devm_ioremap_resource(dev, res);
	639	+ chip->io_ctrl = devm_platform_ioremap_resource(pdev, 1);
643	640	if (IS_ERR(chip->io_ctrl)) {
644	641	dev_err(dev, "unable to map I/O memory\n");
645	642	return PTR_ERR(chip->io_ctrl);
@@ -657,46 +654,47 @@ static int nsp_gpio_probe(struct platform_device *pdev) · 11 unmodified lines
657	654	gc->free = gpiochip_generic_free;
658	655	gc->direction_input = nsp_gpio_direction_input;
659	656	gc->direction_output = nsp_gpio_direction_output;
	657	+ gc->get_direction = nsp_gpio_get_direction;
660	658	gc->set = nsp_gpio_set;
661	659	gc->get = nsp_gpio_get;
662		− gc->to_irq = nsp_gpio_to_irq;
663	660
664	661	/* optional GPIO interrupt support */
665	662	irq = platform_get_irq(pdev, 0);
666	663	if (irq > 0) {
667		− /* Create irq domain so that each pin can be assigned an IRQ.*/
668		− chip->irq_domain = irq_domain_add_linear(gc->of_node, gc->ngpio,
669		− &irq_domain_simple_ops,
670		− chip);
671		− if (!chip->irq_domain) {
672		− dev_err(&pdev->dev, "Couldn't allocate IRQ domain\n");
673		− return -ENXIO;
674		− }
	664	+ struct gpio_irq_chip *girq;
	665	+ struct irq_chip *irqc;
675	666
676		− /* Map each gpio to an IRQ and set the handler for gpiolib. */
677		− for (count = 0; count < gc->ngpio; count++) {
678		− int irq = irq_create_mapping(chip->irq_domain, count);
	667	+ irqc = &chip->irqchip;
	668	+ irqc->name = "gpio-a";
	669	+ irqc->irq_ack = nsp_gpio_irq_ack;
	670	+ irqc->irq_mask = nsp_gpio_irq_mask;
	671	+ irqc->irq_unmask = nsp_gpio_irq_unmask;
	672	+ irqc->irq_set_type = nsp_gpio_irq_set_type;
679	673
680		− irq_set_chip_and_handler(irq, &nsp_gpio_irq_chip,
681		− handle_simple_irq);
682		− irq_set_chip_data(irq, chip);
683		− }
	674	+ val = readl(chip->base + NSP_CHIP_A_INT_MASK);
	675	+ val = val \| NSP_CHIP_A_GPIO_INT_BIT;
	676	+ writel(val, (chip->base + NSP_CHIP_A_INT_MASK));
684	677
685	678	/* Install ISR for this GPIO controller. */
686		− ret = devm_request_irq(&pdev->dev, irq, nsp_gpio_irq_handler,
687		− IRQF_SHARED, "gpio-a", chip);
	679	+ ret = devm_request_irq(dev, irq, nsp_gpio_irq_handler,
	680	+ IRQF_SHARED, "gpio-a", &chip->gc);
688	681	if (ret) {
689	682	dev_err(&pdev->dev, "Unable to request IRQ%d: %d\n",
690	683	irq, ret);
691		− goto err_rm_gpiochip;
	684	+ return ret;
692	685	}
693	686
694		− val = readl(chip->base + NSP_CHIP_A_INT_MASK);
695		− val = val \| NSP_CHIP_A_GPIO_INT_BIT;
696		− writel(val, (chip->base + NSP_CHIP_A_INT_MASK));
	687	+ girq = &chip->gc.irq;
	688	+ girq->chip = irqc;
	689	+ /* This will let us handle the parent IRQ in the driver */
	690	+ girq->parent_handler = NULL;
	691	+ girq->num_parents = 0;
	692	+ girq->parents = NULL;
	693	+ girq->default_type = IRQ_TYPE_NONE;
	694	+ girq->handler = handle_simple_irq;
697	695	}
698	696
699		− ret = gpiochip_add_data(gc, chip);
	697	+ ret = devm_gpiochip_add_data(dev, gc, chip);
700	698	if (ret < 0) {
701	699	dev_err(dev, "unable to add GPIO chip\n");
702	700	return ret;
@@ -705,15 +703,10 @@ static int nsp_gpio_probe(struct platform_device *pdev) · 2 unmodified lines
705	703	ret = nsp_gpio_register_pinconf(chip);
706	704	if (ret) {
707	705	dev_err(dev, "unable to register pinconf\n");
708		− goto err_rm_gpiochip;
	706	+ return ret;
709	707	}
710	708
711	709	return 0;
712		−
713		−err_rm_gpiochip:
714		− gpiochip_remove(gc);
715		−
716		− return ret;
717	710	}
718	711
719	712	static struct platform_driver nsp_gpio_driver = {

drivers/pinctrl/bcm/pinctrl-nsp-mux.c+2−4

@@ -571,8 +571,7 @@ static int nsp_pinmux_probe(struct platform_device *pdev) · 570 unmodified lines
571	571	platform_set_drvdata(pdev, pinctrl);
572	572	spin_lock_init(&pinctrl->lock);
573	573
574		− res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
575		− pinctrl->base0 = devm_ioremap_resource(&pdev->dev, res);
	574	+ pinctrl->base0 = devm_platform_ioremap_resource(pdev, 0);
576	575	if (IS_ERR(pinctrl->base0))
577	576	return PTR_ERR(pinctrl->base0);
578	577
@@ -586,8 +585,7 @@ static int nsp_pinmux_probe(struct platform_device *pdev) · 7 unmodified lines
586	585	return -ENOMEM;
587	586	}
588	587
589		− res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
590		− pinctrl->base2 = devm_ioremap_resource(&pdev->dev, res);
	588	+ pinctrl->base2 = devm_platform_ioremap_resource(pdev, 2);
591	589	if (IS_ERR(pinctrl->base2))
592	590	return PTR_ERR(pinctrl->base2);
593	591

drivers/pinctrl/devicetree.c+30−20

@@ -29,6 +29,13 @@ struct pinctrl_dt_map { · 28 unmodified lines
29	29	static void dt_free_map(struct pinctrl_dev *pctldev,
30	30	struct pinctrl_map *map, unsigned num_maps)
31	31	{
	32	+ int i;
	33	+
	34	+ for (i = 0; i < num_maps; ++i) {
	35	+ kfree_const(map[i].dev_name);
	36	+ map[i].dev_name = NULL;
	37	+ }
	38	+
32	39	if (pctldev) {
33	40	const struct pinctrl_ops *ops = pctldev->desc->pctlops;
34	41	if (ops->dt_free_map)
@@ -63,7 +70,13 @@ static int dt_remember_or_free_map(struct pinctrl p, const char statename, · 28 unmodified lines
63	70
64	71	/* Initialize common mapping table entry fields */
65	72	for (i = 0; i < num_maps; i++) {
66		− map[i].dev_name = dev_name(p->dev);
	73	+ const char *devname;
	74	+
	75	+ devname = kstrdup_const(dev_name(p->dev), GFP_KERNEL);
	76	+ if (!devname)
	77	+ goto err_free_map;
	78	+
	79	+ map[i].dev_name = devname;
67	80	map[i].name = statename;
68	81	if (pctldev)
69	82	map[i].ctrl_dev_name = dev_name(pctldev->dev);
@@ -71,10 +84,8 @@ static int dt_remember_or_free_map(struct pinctrl p, const char statename, · 1 unmodified line
71	84
72	85	/* Remember the converted mapping table entries */
73	86	dt_map = kzalloc(sizeof(*dt_map), GFP_KERNEL);
74		− if (!dt_map) {
75		− dt_free_map(pctldev, map, num_maps);
76		− return -ENOMEM;
77		− }
	87	+ if (!dt_map)
	88	+ goto err_free_map;
78	89
79	90	dt_map->pctldev = pctldev;
80	91	dt_map->map = map;
@@ -82,6 +93,10 @@ static int dt_remember_or_free_map(struct pinctrl p, const char statename, · 1 unmodified line
82	93	list_add_tail(&dt_map->node, &p->dt_maps);
83	94
84	95	return pinctrl_register_map(map, num_maps, false);
	96	+
	97	+err_free_map:
	98	+ dt_free_map(pctldev, map, num_maps);
	99	+ return -ENOMEM;
85	100	}
86	101
87	102	struct pinctrl_dev of_pinctrl_get(struct device_node np)
@@ -147,6 +162,16 @@ static int dt_to_map_one_config(struct pinctrl *p, · 59 unmodified lines
147	162	ret = ops->dt_node_to_map(pctldev, np_config, &map, &num_maps);
148	163	if (ret < 0)
149	164	return ret;
	165	+ else if (num_maps == 0) {
	166	+ /*
	167	+ * If we have no valid maps (maybe caused by empty pinctrl node
	168	+ * or typing error) ther is no need remember this, so just
	169	+ * return.
	170	+ */
	171	+ dev_info(p->dev,
	172	+ "there is not valid maps for state %s\n", statename);
	173	+ return 0;
	174	+ }
150	175
151	176	/* Stash the mapping table chunk away for later use */
152	177	return dt_remember_or_free_map(p, statename, pctldev, map, num_maps);
@@ -166,21 +191,6 @@ static int dt_remember_dummy_state(struct pinctrl p, const char statename) · 13 unmodified lines
166	191	return dt_remember_or_free_map(p, statename, NULL, map, 1);
167	192	}
168	193
169		−bool pinctrl_dt_has_hogs(struct pinctrl_dev *pctldev)
170		−{
171		− struct device_node *np;
172		− struct property *prop;
173		− int size;
174		−
175		− np = pctldev->dev->of_node;
176		− if (!np)
177		− return false;
178		−
179		− prop = of_find_property(np, "pinctrl-0", &size);
180		−
181		− return prop ? true : false;
182		−}
183		−
184	194	int pinctrl_dt_to_map(struct pinctrl p, struct pinctrl_dev pctldev)
185	195	{
186	196	struct device_node *np = p->dev->of_node;

drivers/pinctrl/devicetree.h+0−7

@@ -9,8 +9,6 @@ struct of_phandle_args; · 8 unmodified lines
9	9
10	10	#ifdef CONFIG_OF
11	11
12		−bool pinctrl_dt_has_hogs(struct pinctrl_dev *pctldev);
13		−
14	12	void pinctrl_dt_free_maps(struct pinctrl *p);
15	13	int pinctrl_dt_to_map(struct pinctrl p, struct pinctrl_dev pctldev);
16	14
@@ -23,11 +21,6 @@ int pinctrl_parse_index_with_args(const struct device_node *np, · 6 unmodified lines
23	21
24	22	#else
25	23
26		−static inline bool pinctrl_dt_has_hogs(struct pinctrl_dev *pctldev)
27		−{
28		− return false;
29		−}
30		−
31	24	static inline int pinctrl_dt_to_map(struct pinctrl *p,
32	25	struct pinctrl_dev *pctldev)
33	26	{

drivers/pinctrl/freescale/Kconfig+6−6

@@ -39,12 +39,12 @@ config PINCTRL_IMX27 · 38 unmodified lines
39	39
40	40
41	41	config PINCTRL_IMX25
42		− bool "IMX25 pinctrl driver"
43		− depends on OF
44		− depends on SOC_IMX25
45		− select PINCTRL_IMX
46		− help
47		− Say Y here to enable the imx25 pinctrl driver
	42	+ bool "IMX25 pinctrl driver"
	43	+ depends on OF
	44	+ depends on SOC_IMX25
	45	+ select PINCTRL_IMX
	46	+ help
	47	+ Say Y here to enable the imx25 pinctrl driver
48	48
49	49	config PINCTRL_IMX35
50	50	bool "IMX35 pinctrl driver"

drivers/pinctrl/intel/Kconfig+7−0

@@ -115,4 +115,11 @@ config PINCTRL_SUNRISEPOINT · 114 unmodified lines
115	115	provides an interface that allows configuring of PCH pins and
116	116	using them as GPIOs.
117	117
	118	+config PINCTRL_TIGERLAKE
	119	+ tristate "Intel Tiger Lake pinctrl and GPIO driver"
	120	+ depends on ACPI
	121	+ select PINCTRL_INTEL
	122	+ help
	123	+ This pinctrl driver provides an interface that allows configuring
	124	+ of Intel Tiger Lake PCH pins and using them as GPIOs.
118	125	endif

drivers/pinctrl/intel/Makefile+1−0

@@ -13,3 +13,4 @@ obj-$(CONFIG_PINCTRL_GEMINILAKE) += pinctrl-geminilake.o · 12 unmodified lines
13	13	obj-$(CONFIG_PINCTRL_ICELAKE) += pinctrl-icelake.o
14	14	obj-$(CONFIG_PINCTRL_LEWISBURG) += pinctrl-lewisburg.o
15	15	obj-$(CONFIG_PINCTRL_SUNRISEPOINT) += pinctrl-sunrisepoint.o
	16	+obj-$(CONFIG_PINCTRL_TIGERLAKE) += pinctrl-tigerlake.o

drivers/pinctrl/intel/pinctrl-cherryview.c+3−3

@@ -165,7 +165,7 @@ struct chv_pinctrl { · 164 unmodified lines
165	165	struct gpio_chip chip;
166	166	struct irq_chip irqchip;
167	167	void __iomem *regs;
168		− unsigned intr_lines[16];
	168	+ unsigned int intr_lines[16];
169	169	const struct chv_community *community;
170	170	u32 saved_intmask;
171	171	struct chv_pin_context *saved_pin_context;
@@ -379,7 +379,7 @@ static const struct chv_community southwest_community = { · 207 unmodified lines
379	379	.gpio_ranges = southwest_gpio_ranges,
380	380	.ngpio_ranges = ARRAY_SIZE(southwest_gpio_ranges),
381	381	/*
382		− * Southwest community can benerate GPIO interrupts only for the
	382	+ * Southwest community can generate GPIO interrupts only for the
383	383	* first 8 interrupts. The upper half (8-15) can only be used to
384	384	* trigger GPEs.
385	385	*/
@@ -1480,7 +1480,7 @@ static void chv_gpio_irq_handler(struct irq_desc *desc) · 1094 unmodified lines
1480	1480
1481	1481	pending = readl(pctrl->regs + CHV_INTSTAT);
1482	1482	for_each_set_bit(intr_line, &pending, pctrl->community->nirqs) {
1483		− unsigned irq, offset;
	1483	+ unsigned int irq, offset;
1484	1484
1485	1485	offset = pctrl->intr_lines[intr_line];
1486	1486	irq = irq_find_mapping(gc->irq.domain, offset);

drivers/pinctrl/intel/pinctrl-intel.c+63−56

@@ -1131,7 +1131,7 @@ static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl, · 1130 unmodified lines
1131	1131	pending &= enabled;
1132	1132
1133	1133	for_each_set_bit(gpp_offset, &pending, padgrp->size) {
1134		− unsigned irq;
	1134	+ unsigned int irq;
1135	1135
1136	1136	irq = irq_find_mapping(gc->irq.domain,
1137	1137	padgrp->gpio_base + gpp_offset);
@@ -1181,7 +1181,7 @@ static int intel_gpio_add_pin_ranges(struct intel_pinctrl *pctrl, · 43 unmodified lines
1181	1181	return ret;
1182	1182	}
1183	1183
1184		−static unsigned intel_gpio_ngpio(const struct intel_pinctrl *pctrl)
	1184	+static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl)
1185	1185	{
1186	1186	const struct intel_community *community;
1187	1187	unsigned int ngpio = 0;
@@ -1595,16 +1595,65 @@ intel_gpio_is_requested(struct gpio_chip *chip, int base, unsigned int size) · 407 unmodified lines
1595	1595	return requested;
1596	1596	}
1597	1597
1598		−static u32
1599		−intel_gpio_update_pad_mode(void __iomem *hostown, u32 mask, u32 value)
	1598	+static bool intel_gpio_update_reg(void __iomem *reg, u32 mask, u32 value)
1600	1599	{
1601	1600	u32 curr, updated;
1602	1601
1603		− curr = readl(hostown);
	1602	+ curr = readl(reg);
	1603	+
1604	1604	updated = (curr & ~mask) \| (value & mask);
1605		− writel(updated, hostown);
	1605	+ if (curr == updated)
	1606	+ return false;
	1607	+
	1608	+ writel(updated, reg);
	1609	+ return true;
	1610	+}
	1611	+
	1612	+static void intel_restore_hostown(struct intel_pinctrl *pctrl, unsigned int c,
	1613	+ void __iomem *base, unsigned int gpp, u32 saved)
	1614	+{
	1615	+ const struct intel_community *community = &pctrl->communities[c];
	1616	+ const struct intel_padgroup *padgrp = &community->gpps[gpp];
	1617	+ struct device *dev = pctrl->dev;
	1618	+ u32 requested;
	1619	+
	1620	+ if (padgrp->gpio_base < 0)
	1621	+ return;
1606	1622
1607		− return curr;
	1623	+ requested = intel_gpio_is_requested(&pctrl->chip, padgrp->gpio_base, padgrp->size);
	1624	+ if (!intel_gpio_update_reg(base + gpp * 4, requested, saved))
	1625	+ return;
	1626	+
	1627	+ dev_dbg(dev, "restored hostown %u/%u %#08x\n", c, gpp, readl(base + gpp * 4));
	1628	+}
	1629	+
	1630	+static void intel_restore_intmask(struct intel_pinctrl *pctrl, unsigned int c,
	1631	+ void __iomem *base, unsigned int gpp, u32 saved)
	1632	+{
	1633	+ struct device *dev = pctrl->dev;
	1634	+
	1635	+ if (!intel_gpio_update_reg(base + gpp * 4, ~0U, saved))
	1636	+ return;
	1637	+
	1638	+ dev_dbg(dev, "restored mask %u/%u %#08x\n", c, gpp, readl(base + gpp * 4));
	1639	+}
	1640	+
	1641	+static void intel_restore_padcfg(struct intel_pinctrl *pctrl, unsigned int pin,
	1642	+ unsigned int reg, u32 saved)
	1643	+{
	1644	+ u32 mask = (reg == PADCFG0) ? PADCFG0_GPIORXSTATE : 0;
	1645	+ unsigned int n = reg / sizeof(u32);
	1646	+ struct device *dev = pctrl->dev;
	1647	+ void __iomem *padcfg;
	1648	+
	1649	+ padcfg = intel_get_padcfg(pctrl, pin, reg);
	1650	+ if (!padcfg)
	1651	+ return;
	1652	+
	1653	+ if (!intel_gpio_update_reg(padcfg, ~mask, saved))
	1654	+ return;
	1655	+
	1656	+ dev_dbg(dev, "restored pin %u padcfg%u %#08x\n", pin, n, readl(padcfg));
1608	1657	}
1609	1658
1610	1659	int intel_pinctrl_resume_noirq(struct device *dev)
@@ -1620,37 +1669,13 @@ int intel_pinctrl_resume_noirq(struct device *dev) · 9 unmodified lines
1620	1669	pads = pctrl->context.pads;
1621	1670	for (i = 0; i < pctrl->soc->npins; i++) {
1622	1671	const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1623		− void __iomem *padcfg;
1624		− u32 val;
1625	1672
1626	1673	if (!intel_pinctrl_should_save(pctrl, desc->number))
1627	1674	continue;
1628	1675
1629		− padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0);
1630		− val = readl(padcfg) & ~PADCFG0_GPIORXSTATE;
1631		− if (val != pads[i].padcfg0) {
1632		− writel(pads[i].padcfg0, padcfg);
1633		− dev_dbg(dev, "restored pin %u padcfg0 %#08x\n",
1634		− desc->number, readl(padcfg));
1635		− }
1636		−
1637		− padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1);
1638		− val = readl(padcfg);
1639		− if (val != pads[i].padcfg1) {
1640		− writel(pads[i].padcfg1, padcfg);
1641		− dev_dbg(dev, "restored pin %u padcfg1 %#08x\n",
1642		− desc->number, readl(padcfg));
1643		− }
1644		−
1645		− padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1646		− if (padcfg) {
1647		− val = readl(padcfg);
1648		− if (val != pads[i].padcfg2) {
1649		− writel(pads[i].padcfg2, padcfg);
1650		− dev_dbg(dev, "restored pin %u padcfg2 %#08x\n",
1651		− desc->number, readl(padcfg));
1652		− }
1653		− }
	1676	+ intel_restore_padcfg(pctrl, desc->number, PADCFG0, pads[i].padcfg0);
	1677	+ intel_restore_padcfg(pctrl, desc->number, PADCFG1, pads[i].padcfg1);
	1678	+ intel_restore_padcfg(pctrl, desc->number, PADCFG2, pads[i].padcfg2);
1654	1679	}
1655	1680
1656	1681	communities = pctrl->context.communities;
@@ -1660,30 +1685,12 @@ int intel_pinctrl_resume_noirq(struct device *dev) · 3 unmodified lines
1660	1685	unsigned int gpp;
1661	1686
1662	1687	base = community->regs + community->ie_offset;
1663		− for (gpp = 0; gpp < community->ngpps; gpp++) {
1664		− writel(communities[i].intmask[gpp], base + gpp * 4);
1665		− dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp,
1666		− readl(base + gpp * 4));
1667		− }
	1688	+ for (gpp = 0; gpp < community->ngpps; gpp++)
	1689	+ intel_restore_intmask(pctrl, i, base, gpp, communities[i].intmask[gpp]);
1668	1690
1669	1691	base = community->regs + community->hostown_offset;
1670		− for (gpp = 0; gpp < community->ngpps; gpp++) {
1671		− const struct intel_padgroup *padgrp = &community->gpps[gpp];
1672		− u32 requested = 0, value = 0;
1673		− u32 saved = communities[i].hostown[gpp];
1674		−
1675		− if (padgrp->gpio_base < 0)
1676		− continue;
1677		−
1678		− requested = intel_gpio_is_requested(&pctrl->chip,
1679		− padgrp->gpio_base, padgrp->size);
1680		− value = intel_gpio_update_pad_mode(base + gpp * 4,
1681		− requested, saved);
1682		− if ((value ^ saved) & requested) {
1683		− dev_warn(dev, "restore hostown %d/%u %#8x->%#8x\n",
1684		− i, gpp, value, saved);
1685		− }
1686		− }
	1692	+ for (gpp = 0; gpp < community->ngpps; gpp++)
	1693	+ intel_restore_hostown(pctrl, i, base, gpp, communities[i].hostown[gpp]);
1687	1694	}
1688	1695
1689	1696	return 0;

drivers/pinctrl/intel/pinctrl-lewisburg.c+86−85

@@ -33,6 +33,7 @@ · 32 unmodified lines
33	33	.npins = ((e) - (s) + 1), \
34	34	}
35	35
	36	+/* Lewisburg */
36	37	static const struct pinctrl_pin_desc lbg_pins[] = {
37	38	/* GPP_A */
38	39	PINCTRL_PIN(0, "RCINB"),
@@ -72,7 +73,7 @@ static const struct pinctrl_pin_desc lbg_pins[] = { · 33 unmodified lines
72	73	PINCTRL_PIN(33, "SRCCLKREQB_4"),
73	74	PINCTRL_PIN(34, "SRCCLKREQB_5"),
74	75	PINCTRL_PIN(35, "GPP_B_11"),
75		− PINCTRL_PIN(36, "GLB_RST_WARN_N"),
	76	+ PINCTRL_PIN(36, "SLP_S0B"),
76	77	PINCTRL_PIN(37, "PLTRSTB"),
77	78	PINCTRL_PIN(38, "SPKR"),
78	79	PINCTRL_PIN(39, "GPP_B_15"),
@@ -185,96 +186,96 @@ static const struct pinctrl_pin_desc lbg_pins[] = { · 106 unmodified lines
185	186	PINCTRL_PIN(141, "GBE_PCI_DIS"),
186	187	PINCTRL_PIN(142, "GBE_LAN_DIS"),
187	188	PINCTRL_PIN(143, "GPP_I_10"),
188		− PINCTRL_PIN(144, "GPIO_RCOMP_3P3"),
189	189	/* GPP_J */
190		− PINCTRL_PIN(145, "GBE_LED_0_0"),
191		− PINCTRL_PIN(146, "GBE_LED_0_1"),
192		− PINCTRL_PIN(147, "GBE_LED_1_0"),
193		− PINCTRL_PIN(148, "GBE_LED_1_1"),
194		− PINCTRL_PIN(149, "GBE_LED_2_0"),
195		− PINCTRL_PIN(150, "GBE_LED_2_1"),
196		− PINCTRL_PIN(151, "GBE_LED_3_0"),
197		− PINCTRL_PIN(152, "GBE_LED_3_1"),
198		− PINCTRL_PIN(153, "GBE_SCL_0"),
199		− PINCTRL_PIN(154, "GBE_SDA_0"),
200		− PINCTRL_PIN(155, "GBE_SCL_1"),
201		− PINCTRL_PIN(156, "GBE_SDA_1"),
202		− PINCTRL_PIN(157, "GBE_SCL_2"),
203		− PINCTRL_PIN(158, "GBE_SDA_2"),
204		− PINCTRL_PIN(159, "GBE_SCL_3"),
205		− PINCTRL_PIN(160, "GBE_SDA_3"),
206		− PINCTRL_PIN(161, "GBE_SDP_0_0"),
207		− PINCTRL_PIN(162, "GBE_SDP_0_1"),
208		− PINCTRL_PIN(163, "GBE_SDP_1_0"),
209		− PINCTRL_PIN(164, "GBE_SDP_1_1"),
210		− PINCTRL_PIN(165, "GBE_SDP_2_0"),
211		− PINCTRL_PIN(166, "GBE_SDP_2_1"),
212		− PINCTRL_PIN(167, "GBE_SDP_3_0"),
213		− PINCTRL_PIN(168, "GBE_SDP_3_1"),
	190	+ PINCTRL_PIN(144, "GBE_LED_0_0"),
	191	+ PINCTRL_PIN(145, "GBE_LED_0_1"),
	192	+ PINCTRL_PIN(146, "GBE_LED_1_0"),
	193	+ PINCTRL_PIN(147, "GBE_LED_1_1"),
	194	+ PINCTRL_PIN(148, "GBE_LED_2_0"),
	195	+ PINCTRL_PIN(149, "GBE_LED_2_1"),
	196	+ PINCTRL_PIN(150, "GBE_LED_3_0"),
	197	+ PINCTRL_PIN(151, "GBE_LED_3_1"),
	198	+ PINCTRL_PIN(152, "GBE_SCL_0"),
	199	+ PINCTRL_PIN(153, "GBE_SDA_0"),
	200	+ PINCTRL_PIN(154, "GBE_SCL_1"),
	201	+ PINCTRL_PIN(155, "GBE_SDA_1"),
	202	+ PINCTRL_PIN(156, "GBE_SCL_2"),
	203	+ PINCTRL_PIN(157, "GBE_SDA_2"),
	204	+ PINCTRL_PIN(158, "GBE_SCL_3"),
	205	+ PINCTRL_PIN(159, "GBE_SDA_3"),
	206	+ PINCTRL_PIN(160, "GBE_SDP_0_0"),
	207	+ PINCTRL_PIN(161, "GBE_SDP_0_1"),
	208	+ PINCTRL_PIN(162, "GBE_SDP_1_0"),
	209	+ PINCTRL_PIN(163, "GBE_SDP_1_1"),
	210	+ PINCTRL_PIN(164, "GBE_SDP_2_0"),
	211	+ PINCTRL_PIN(165, "GBE_SDP_2_1"),
	212	+ PINCTRL_PIN(166, "GBE_SDP_3_0"),
	213	+ PINCTRL_PIN(167, "GBE_SDP_3_1"),
214	214	/* GPP_K */
215		− PINCTRL_PIN(169, "GBE_RMIICLK"),
216		− PINCTRL_PIN(170, "GBE_RMII_TXD_0"),
217		− PINCTRL_PIN(171, "GBE_RMII_TXD_1"),
	215	+ PINCTRL_PIN(168, "GBE_RMIICLK"),
	216	+ PINCTRL_PIN(169, "GBE_RMII_RXD_0"),
	217	+ PINCTRL_PIN(170, "GBE_RMII_RXD_1"),
	218	+ PINCTRL_PIN(171, "GBE_RMII_CRS_DV"),
218	219	PINCTRL_PIN(172, "GBE_RMII_TX_EN"),
219		− PINCTRL_PIN(173, "GBE_RMII_CRS_DV"),
220		− PINCTRL_PIN(174, "GBE_RMII_RXD_0"),
221		− PINCTRL_PIN(175, "GBE_RMII_RXD_1"),
222		− PINCTRL_PIN(176, "GBE_RMII_RX_ER"),
223		− PINCTRL_PIN(177, "GBE_RMII_ARBIN"),
224		− PINCTRL_PIN(178, "GBE_RMII_ARB_OUT"),
225		− PINCTRL_PIN(179, "PE_RST_N"),
226		− PINCTRL_PIN(180, "GPIO_RCOMP_1P8_3P3"),
	220	+ PINCTRL_PIN(173, "GBE_RMII_TXD_0"),
	221	+ PINCTRL_PIN(174, "GBE_RMII_TXD_1"),
	222	+ PINCTRL_PIN(175, "GBE_RMII_RX_ER"),
	223	+ PINCTRL_PIN(176, "GBE_RMII_ARBIN"),
	224	+ PINCTRL_PIN(177, "GBE_RMII_ARB_OUT"),
	225	+ PINCTRL_PIN(178, "PE_RST_N"),
227	226	/* GPP_G */
228		− PINCTRL_PIN(181, "FAN_TACH_0"),
229		− PINCTRL_PIN(182, "FAN_TACH_1"),
230		− PINCTRL_PIN(183, "FAN_TACH_2"),
231		− PINCTRL_PIN(184, "FAN_TACH_3"),
232		− PINCTRL_PIN(185, "FAN_TACH_4"),
233		− PINCTRL_PIN(186, "FAN_TACH_5"),
234		− PINCTRL_PIN(187, "FAN_TACH_6"),
235		− PINCTRL_PIN(188, "FAN_TACH_7"),
236		− PINCTRL_PIN(189, "FAN_PWM_0"),
237		− PINCTRL_PIN(190, "FAN_PWM_1"),
238		− PINCTRL_PIN(191, "FAN_PWM_2"),
239		− PINCTRL_PIN(192, "FAN_PWM_3"),
240		− PINCTRL_PIN(193, "GSXDOUT"),
241		− PINCTRL_PIN(194, "GSXSLOAD"),
242		− PINCTRL_PIN(195, "GSXDIN"),
243		− PINCTRL_PIN(196, "GSXSRESETB"),
244		− PINCTRL_PIN(197, "GSXCLK"),
245		− PINCTRL_PIN(198, "ADR_COMPLETE"),
246		− PINCTRL_PIN(199, "NMIB"),
247		− PINCTRL_PIN(200, "SMIB"),
248		− PINCTRL_PIN(201, "SSATA_DEVSLP_0"),
249		− PINCTRL_PIN(202, "SSATA_DEVSLP_1"),
250		− PINCTRL_PIN(203, "SSATA_DEVSLP_2"),
251		− PINCTRL_PIN(204, "SSATAXPCIE0_SSATAGP0"),
	227	+ PINCTRL_PIN(179, "FAN_TACH_0"),
	228	+ PINCTRL_PIN(180, "FAN_TACH_1"),
	229	+ PINCTRL_PIN(181, "FAN_TACH_2"),
	230	+ PINCTRL_PIN(182, "FAN_TACH_3"),
	231	+ PINCTRL_PIN(183, "FAN_TACH_4"),
	232	+ PINCTRL_PIN(184, "FAN_TACH_5"),
	233	+ PINCTRL_PIN(185, "FAN_TACH_6"),
	234	+ PINCTRL_PIN(186, "FAN_TACH_7"),
	235	+ PINCTRL_PIN(187, "FAN_PWM_0"),
	236	+ PINCTRL_PIN(188, "FAN_PWM_1"),
	237	+ PINCTRL_PIN(189, "FAN_PWM_2"),
	238	+ PINCTRL_PIN(190, "FAN_PWM_3"),
	239	+ PINCTRL_PIN(191, "GSXDOUT"),
	240	+ PINCTRL_PIN(192, "GSXSLOAD"),
	241	+ PINCTRL_PIN(193, "GSXDIN"),
	242	+ PINCTRL_PIN(194, "GSXSRESETB"),
	243	+ PINCTRL_PIN(195, "GSXCLK"),
	244	+ PINCTRL_PIN(196, "ADR_COMPLETE"),
	245	+ PINCTRL_PIN(197, "NMIB"),
	246	+ PINCTRL_PIN(198, "SMIB"),
	247	+ PINCTRL_PIN(199, "SSATA_DEVSLP_0"),
	248	+ PINCTRL_PIN(200, "SSATA_DEVSLP_1"),
	249	+ PINCTRL_PIN(201, "SSATA_DEVSLP_2"),
	250	+ PINCTRL_PIN(202, "SSATAXPCIE0_SSATAGP0"),
252	251	/* GPP_H */
253		− PINCTRL_PIN(205, "SRCCLKREQB_6"),
254		− PINCTRL_PIN(206, "SRCCLKREQB_7"),
255		− PINCTRL_PIN(207, "SRCCLKREQB_8"),
256		− PINCTRL_PIN(208, "SRCCLKREQB_9"),
257		− PINCTRL_PIN(209, "SRCCLKREQB_10"),
258		− PINCTRL_PIN(210, "SRCCLKREQB_11"),
259		− PINCTRL_PIN(211, "SRCCLKREQB_12"),
260		− PINCTRL_PIN(212, "SRCCLKREQB_13"),
261		− PINCTRL_PIN(213, "SRCCLKREQB_14"),
262		− PINCTRL_PIN(214, "SRCCLKREQB_15"),
263		− PINCTRL_PIN(215, "SML2CLK"),
264		− PINCTRL_PIN(216, "SML2DATA"),
265		− PINCTRL_PIN(217, "SML2ALERTB"),
266		− PINCTRL_PIN(218, "SML3CLK"),
267		− PINCTRL_PIN(219, "SML3DATA"),
268		− PINCTRL_PIN(220, "SML3ALERTB"),
269		− PINCTRL_PIN(221, "SML4CLK"),
270		− PINCTRL_PIN(222, "SML4DATA"),
271		− PINCTRL_PIN(223, "SML4ALERTB"),
272		− PINCTRL_PIN(224, "SSATAXPCIE1_SSATAGP1"),
273		− PINCTRL_PIN(225, "SSATAXPCIE2_SSATAGP2"),
274		− PINCTRL_PIN(226, "SSATAXPCIE3_SSATAGP3"),
275		− PINCTRL_PIN(227, "SSATAXPCIE4_SSATAGP4"),
276		− PINCTRL_PIN(228, "SSATAXPCIE5_SSATAGP5"),
	252	+ PINCTRL_PIN(203, "SRCCLKREQB_6"),
	253	+ PINCTRL_PIN(204, "SRCCLKREQB_7"),
	254	+ PINCTRL_PIN(205, "SRCCLKREQB_8"),
	255	+ PINCTRL_PIN(206, "SRCCLKREQB_9"),
	256	+ PINCTRL_PIN(207, "SRCCLKREQB_10"),
	257	+ PINCTRL_PIN(208, "SRCCLKREQB_11"),
	258	+ PINCTRL_PIN(209, "SRCCLKREQB_12"),
	259	+ PINCTRL_PIN(210, "SRCCLKREQB_13"),
	260	+ PINCTRL_PIN(211, "SRCCLKREQB_14"),
	261	+ PINCTRL_PIN(212, "SRCCLKREQB_15"),
	262	+ PINCTRL_PIN(213, "SML2CLK"),
	263	+ PINCTRL_PIN(214, "SML2DATA"),
	264	+ PINCTRL_PIN(215, "SML2ALERTB"),
	265	+ PINCTRL_PIN(216, "SML3CLK"),
	266	+ PINCTRL_PIN(217, "SML3DATA"),
	267	+ PINCTRL_PIN(218, "SML3ALERTB"),
	268	+ PINCTRL_PIN(219, "SML4CLK"),
	269	+ PINCTRL_PIN(220, "SML4DATA"),
	270	+ PINCTRL_PIN(221, "SML4ALERTB"),
	271	+ PINCTRL_PIN(222, "SSATAXPCIE1_SSATAGP1"),
	272	+ PINCTRL_PIN(223, "SSATAXPCIE2_SSATAGP2"),
	273	+ PINCTRL_PIN(224, "SSATAXPCIE3_SSATAGP3"),
	274	+ PINCTRL_PIN(225, "SSATAXPCIE4_SSATAGP4"),
	275	+ PINCTRL_PIN(226, "SSATAXPCIE5_SSATAGP5"),
277	276	/* GPP_L */
	277	+ PINCTRL_PIN(227, "GPP_L_0"),
	278	+ PINCTRL_PIN(228, "EC_CSME_INTR_OUT"),
278	279	PINCTRL_PIN(229, "VISA2CH0_D0"),
279	280	PINCTRL_PIN(230, "VISA2CH0_D1"),
280	281	PINCTRL_PIN(231, "VISA2CH0_D2"),

drivers/pinctrl/intel/pinctrl-tigerlake.c+454−0

@@ -0,0 +1,454 @@
	1	+// SPDX-License-Identifier: GPL-2.0
	2	+/*
	3	+ * Intel Tiger Lake PCH pinctrl/GPIO driver
	4	+ *
	5	+ * Copyright (C) 2019, Intel Corporation
	6	+ * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
	7	+ * Mika Westerberg <mika.westerberg@linux.intel.com>
	8	+ */
	9	+
	10	+#include <linux/mod_devicetable.h>
	11	+#include <linux/module.h>
	12	+#include <linux/platform_device.h>
	13	+
	14	+#include <linux/pinctrl/pinctrl.h>
	15	+
	16	+#include "pinctrl-intel.h"
	17	+
	18	+#define TGL_PAD_OWN 0x020
	19	+#define TGL_PADCFGLOCK 0x080
	20	+#define TGL_HOSTSW_OWN 0x0b0
	21	+#define TGL_GPI_IS 0x100
	22	+#define TGL_GPI_IE 0x120
	23	+
	24	+#define TGL_GPP(r, s, e) \
	25	+ { \
	26	+ .reg_num = (r), \
	27	+ .base = (s), \
	28	+ .size = ((e) - (s) + 1), \
	29	+ }
	30	+
	31	+#define TGL_COMMUNITY(s, e, g) \
	32	+ { \
	33	+ .padown_offset = TGL_PAD_OWN, \
	34	+ .padcfglock_offset = TGL_PADCFGLOCK, \
	35	+ .hostown_offset = TGL_HOSTSW_OWN, \
	36	+ .is_offset = TGL_GPI_IS, \
	37	+ .ie_offset = TGL_GPI_IE, \
	38	+ .pin_base = (s), \
	39	+ .npins = ((e) - (s) + 1), \
	40	+ .gpps = (g), \
	41	+ .ngpps = ARRAY_SIZE(g), \
	42	+ }
	43	+
	44	+/* Tiger Lake-LP */
	45	+static const struct pinctrl_pin_desc tgllp_community0_pins[] = {
	46	+ /* GPP_B */
	47	+ PINCTRL_PIN(0, "CORE_VID_0"),
	48	+ PINCTRL_PIN(1, "CORE_VID_1"),
	49	+ PINCTRL_PIN(2, "VRALERTB"),
	50	+ PINCTRL_PIN(3, "CPU_GP_2"),
	51	+ PINCTRL_PIN(4, "CPU_GP_3"),
	52	+ PINCTRL_PIN(5, "ISH_I2C0_SDA"),
	53	+ PINCTRL_PIN(6, "ISH_I2C0_SCL"),
	54	+ PINCTRL_PIN(7, "ISH_I2C1_SDA"),
	55	+ PINCTRL_PIN(8, "ISH_I2C1_SCL"),
	56	+ PINCTRL_PIN(9, "I2C5_SDA"),
	57	+ PINCTRL_PIN(10, "I2C5_SCL"),
	58	+ PINCTRL_PIN(11, "PMCALERTB"),
	59	+ PINCTRL_PIN(12, "SLP_S0B"),
	60	+ PINCTRL_PIN(13, "PLTRSTB"),
	61	+ PINCTRL_PIN(14, "SPKR"),
	62	+ PINCTRL_PIN(15, "GSPI0_CS0B"),
	63	+ PINCTRL_PIN(16, "GSPI0_CLK"),
	64	+ PINCTRL_PIN(17, "GSPI0_MISO"),
	65	+ PINCTRL_PIN(18, "GSPI0_MOSI"),
	66	+ PINCTRL_PIN(19, "GSPI1_CS0B"),
	67	+ PINCTRL_PIN(20, "GSPI1_CLK"),
	68	+ PINCTRL_PIN(21, "GSPI1_MISO"),
	69	+ PINCTRL_PIN(22, "GSPI1_MOSI"),
	70	+ PINCTRL_PIN(23, "SML1ALERTB"),
	71	+ PINCTRL_PIN(24, "GSPI0_CLK_LOOPBK"),
	72	+ PINCTRL_PIN(25, "GSPI1_CLK_LOOPBK"),
	73	+ /* GPP_T */
	74	+ PINCTRL_PIN(26, "I2C6_SDA"),
	75	+ PINCTRL_PIN(27, "I2C6_SCL"),
	76	+ PINCTRL_PIN(28, "I2C7_SDA"),
	77	+ PINCTRL_PIN(29, "I2C7_SCL"),
	78	+ PINCTRL_PIN(30, "UART4_RXD"),
	79	+ PINCTRL_PIN(31, "UART4_TXD"),
	80	+ PINCTRL_PIN(32, "UART4_RTSB"),
	81	+ PINCTRL_PIN(33, "UART4_CTSB"),
	82	+ PINCTRL_PIN(34, "UART5_RXD"),
	83	+ PINCTRL_PIN(35, "UART5_TXD"),
	84	+ PINCTRL_PIN(36, "UART5_RTSB"),
	85	+ PINCTRL_PIN(37, "UART5_CTSB"),
	86	+ PINCTRL_PIN(38, "UART6_RXD"),
	87	+ PINCTRL_PIN(39, "UART6_TXD"),
	88	+ PINCTRL_PIN(40, "UART6_RTSB"),
	89	+ PINCTRL_PIN(41, "UART6_CTSB"),
	90	+ /* GPP_A */
	91	+ PINCTRL_PIN(42, "ESPI_IO_0"),
	92	+ PINCTRL_PIN(43, "ESPI_IO_1"),
	93	+ PINCTRL_PIN(44, "ESPI_IO_2"),
	94	+ PINCTRL_PIN(45, "ESPI_IO_3"),
	95	+ PINCTRL_PIN(46, "ESPI_CSB"),
	96	+ PINCTRL_PIN(47, "ESPI_CLK"),
	97	+ PINCTRL_PIN(48, "ESPI_RESETB"),
	98	+ PINCTRL_PIN(49, "I2S2_SCLK"),
	99	+ PINCTRL_PIN(50, "I2S2_SFRM"),
	100	+ PINCTRL_PIN(51, "I2S2_TXD"),
	101	+ PINCTRL_PIN(52, "I2S2_RXD"),
	102	+ PINCTRL_PIN(53, "PMC_I2C_SDA"),
	103	+ PINCTRL_PIN(54, "SATAXPCIE_1"),
	104	+ PINCTRL_PIN(55, "PMC_I2C_SCL"),
	105	+ PINCTRL_PIN(56, "USB2_OCB_1"),
	106	+ PINCTRL_PIN(57, "USB2_OCB_2"),
	107	+ PINCTRL_PIN(58, "USB2_OCB_3"),
	108	+ PINCTRL_PIN(59, "DDSP_HPD_C"),
	109	+ PINCTRL_PIN(60, "DDSP_HPD_B"),
	110	+ PINCTRL_PIN(61, "DDSP_HPD_1"),
	111	+ PINCTRL_PIN(62, "DDSP_HPD_2"),
	112	+ PINCTRL_PIN(63, "GPPC_A_21"),
	113	+ PINCTRL_PIN(64, "GPPC_A_22"),
	114	+ PINCTRL_PIN(65, "I2S1_SCLK"),
	115	+ PINCTRL_PIN(66, "ESPI_CLK_LOOPBK"),
	116	+};
	117	+
	118	+static const struct intel_padgroup tgllp_community0_gpps[] = {
	119	+ TGL_GPP(0, 0, 25), /* GPP_B */
	120	+ TGL_GPP(1, 26, 41), /* GPP_T */
	121	+ TGL_GPP(2, 42, 66), /* GPP_A */
	122	+};
	123	+
	124	+static const struct intel_community tgllp_community0[] = {
	125	+ TGL_COMMUNITY(0, 66, tgllp_community0_gpps),
	126	+};
	127	+
	128	+static const struct intel_pinctrl_soc_data tgllp_community0_soc_data = {
	129	+ .uid = "0",
	130	+ .pins = tgllp_community0_pins,
	131	+ .npins = ARRAY_SIZE(tgllp_community0_pins),
	132	+ .communities = tgllp_community0,
	133	+ .ncommunities = ARRAY_SIZE(tgllp_community0),
	134	+};
	135	+
	136	+static const struct pinctrl_pin_desc tgllp_community1_pins[] = {
	137	+ /* GPP_S */
	138	+ PINCTRL_PIN(0, "SNDW0_CLK"),
	139	+ PINCTRL_PIN(1, "SNDW0_DATA"),
	140	+ PINCTRL_PIN(2, "SNDW1_CLK"),
	141	+ PINCTRL_PIN(3, "SNDW1_DATA"),
	142	+ PINCTRL_PIN(4, "SNDW2_CLK"),
	143	+ PINCTRL_PIN(5, "SNDW2_DATA"),
	144	+ PINCTRL_PIN(6, "SNDW3_CLK"),
	145	+ PINCTRL_PIN(7, "SNDW3_DATA"),
	146	+ /* GPP_H */
	147	+ PINCTRL_PIN(8, "GPPC_H_0"),
	148	+ PINCTRL_PIN(9, "GPPC_H_1"),
	149	+ PINCTRL_PIN(10, "GPPC_H_2"),
	150	+ PINCTRL_PIN(11, "SX_EXIT_HOLDOFFB"),
	151	+ PINCTRL_PIN(12, "I2C2_SDA"),
	152	+ PINCTRL_PIN(13, "I2C2_SCL"),
	153	+ PINCTRL_PIN(14, "I2C3_SDA"),
	154	+ PINCTRL_PIN(15, "I2C3_SCL"),
	155	+ PINCTRL_PIN(16, "I2C4_SDA"),
	156	+ PINCTRL_PIN(17, "I2C4_SCL"),
	157	+ PINCTRL_PIN(18, "SRCCLKREQB_4"),
	158	+ PINCTRL_PIN(19, "SRCCLKREQB_5"),
	159	+ PINCTRL_PIN(20, "M2_SKT2_CFG_0"),
	160	+ PINCTRL_PIN(21, "M2_SKT2_CFG_1"),
	161	+ PINCTRL_PIN(22, "M2_SKT2_CFG_2"),
	162	+ PINCTRL_PIN(23, "M2_SKT2_CFG_3"),
	163	+ PINCTRL_PIN(24, "DDPB_CTRLCLK"),
	164	+ PINCTRL_PIN(25, "DDPB_CTRLDATA"),
	165	+ PINCTRL_PIN(26, "CPU_C10_GATEB"),
	166	+ PINCTRL_PIN(27, "TIME_SYNC_0"),
	167	+ PINCTRL_PIN(28, "IMGCLKOUT_1"),
	168	+ PINCTRL_PIN(29, "IMGCLKOUT_2"),
	169	+ PINCTRL_PIN(30, "IMGCLKOUT_3"),
	170	+ PINCTRL_PIN(31, "IMGCLKOUT_4"),
	171	+ /* GPP_D */
	172	+ PINCTRL_PIN(32, "ISH_GP_0"),
	173	+ PINCTRL_PIN(33, "ISH_GP_1"),
	174	+ PINCTRL_PIN(34, "ISH_GP_2"),
	175	+ PINCTRL_PIN(35, "ISH_GP_3"),
	176	+ PINCTRL_PIN(36, "IMGCLKOUT_0"),
	177	+ PINCTRL_PIN(37, "SRCCLKREQB_0"),
	178	+ PINCTRL_PIN(38, "SRCCLKREQB_1"),
	179	+ PINCTRL_PIN(39, "SRCCLKREQB_2"),
	180	+ PINCTRL_PIN(40, "SRCCLKREQB_3"),
	181	+ PINCTRL_PIN(41, "ISH_SPI_CSB"),
	182	+ PINCTRL_PIN(42, "ISH_SPI_CLK"),
	183	+ PINCTRL_PIN(43, "ISH_SPI_MISO"),
	184	+ PINCTRL_PIN(44, "ISH_SPI_MOSI"),
	185	+ PINCTRL_PIN(45, "ISH_UART0_RXD"),
	186	+ PINCTRL_PIN(46, "ISH_UART0_TXD"),
	187	+ PINCTRL_PIN(47, "ISH_UART0_RTSB"),
	188	+ PINCTRL_PIN(48, "ISH_UART0_CTSB"),
	189	+ PINCTRL_PIN(49, "ISH_GP_4"),
	190	+ PINCTRL_PIN(50, "ISH_GP_5"),
	191	+ PINCTRL_PIN(51, "I2S_MCLK1_OUT"),
	192	+ PINCTRL_PIN(52, "GSPI2_CLK_LOOPBK"),
	193	+ /* GPP_U */
	194	+ PINCTRL_PIN(53, "UART3_RXD"),
	195	+ PINCTRL_PIN(54, "UART3_TXD"),
	196	+ PINCTRL_PIN(55, "UART3_RTSB"),
	197	+ PINCTRL_PIN(56, "UART3_CTSB"),
	198	+ PINCTRL_PIN(57, "GSPI3_CS0B"),
	199	+ PINCTRL_PIN(58, "GSPI3_CLK"),
	200	+ PINCTRL_PIN(59, "GSPI3_MISO"),
	201	+ PINCTRL_PIN(60, "GSPI3_MOSI"),
	202	+ PINCTRL_PIN(61, "GSPI4_CS0B"),
	203	+ PINCTRL_PIN(62, "GSPI4_CLK"),
	204	+ PINCTRL_PIN(63, "GSPI4_MISO"),
	205	+ PINCTRL_PIN(64, "GSPI4_MOSI"),
	206	+ PINCTRL_PIN(65, "GSPI5_CS0B"),
	207	+ PINCTRL_PIN(66, "GSPI5_CLK"),
	208	+ PINCTRL_PIN(67, "GSPI5_MISO"),
	209	+ PINCTRL_PIN(68, "GSPI5_MOSI"),
	210	+ PINCTRL_PIN(69, "GSPI6_CS0B"),
	211	+ PINCTRL_PIN(70, "GSPI6_CLK"),
	212	+ PINCTRL_PIN(71, "GSPI6_MISO"),
	213	+ PINCTRL_PIN(72, "GSPI6_MOSI"),
	214	+ PINCTRL_PIN(73, "GSPI3_CLK_LOOPBK"),
	215	+ PINCTRL_PIN(74, "GSPI4_CLK_LOOPBK"),
	216	+ PINCTRL_PIN(75, "GSPI5_CLK_LOOPBK"),
	217	+ PINCTRL_PIN(76, "GSPI6_CLK_LOOPBK"),
	218	+ /* vGPIO */
	219	+ PINCTRL_PIN(77, "CNV_BTEN"),
	220	+ PINCTRL_PIN(78, "CNV_BT_HOST_WAKEB"),
	221	+ PINCTRL_PIN(79, "CNV_BT_IF_SELECT"),
	222	+ PINCTRL_PIN(80, "vCNV_BT_UART_TXD"),
	223	+ PINCTRL_PIN(81, "vCNV_BT_UART_RXD"),
	224	+ PINCTRL_PIN(82, "vCNV_BT_UART_CTS_B"),
	225	+ PINCTRL_PIN(83, "vCNV_BT_UART_RTS_B"),
	226	+ PINCTRL_PIN(84, "vCNV_MFUART1_TXD"),
	227	+ PINCTRL_PIN(85, "vCNV_MFUART1_RXD"),
	228	+ PINCTRL_PIN(86, "vCNV_MFUART1_CTS_B"),
	229	+ PINCTRL_PIN(87, "vCNV_MFUART1_RTS_B"),
	230	+ PINCTRL_PIN(88, "vUART0_TXD"),
	231	+ PINCTRL_PIN(89, "vUART0_RXD"),
	232	+ PINCTRL_PIN(90, "vUART0_CTS_B"),
	233	+ PINCTRL_PIN(91, "vUART0_RTS_B"),
	234	+ PINCTRL_PIN(92, "vISH_UART0_TXD"),
	235	+ PINCTRL_PIN(93, "vISH_UART0_RXD"),
	236	+ PINCTRL_PIN(94, "vISH_UART0_CTS_B"),
	237	+ PINCTRL_PIN(95, "vISH_UART0_RTS_B"),
	238	+ PINCTRL_PIN(96, "vCNV_BT_I2S_BCLK"),
	239	+ PINCTRL_PIN(97, "vCNV_BT_I2S_WS_SYNC"),
	240	+ PINCTRL_PIN(98, "vCNV_BT_I2S_SDO"),
	241	+ PINCTRL_PIN(99, "vCNV_BT_I2S_SDI"),
	242	+ PINCTRL_PIN(100, "vI2S2_SCLK"),
	243	+ PINCTRL_PIN(101, "vI2S2_SFRM"),
	244	+ PINCTRL_PIN(102, "vI2S2_TXD"),
	245	+ PINCTRL_PIN(103, "vI2S2_RXD"),
	246	+};
	247	+
	248	+static const struct intel_padgroup tgllp_community1_gpps[] = {
	249	+ TGL_GPP(0, 0, 7), /* GPP_S */
	250	+ TGL_GPP(1, 8, 31), /* GPP_H */
	251	+ TGL_GPP(2, 32, 52), /* GPP_D */
	252	+ TGL_GPP(3, 53, 76), /* GPP_U */
	253	+ TGL_GPP(4, 77, 103), /* vGPIO */
	254	+};
	255	+
	256	+static const struct intel_community tgllp_community1[] = {
	257	+ TGL_COMMUNITY(0, 103, tgllp_community1_gpps),
	258	+};
	259	+
	260	+static const struct intel_pinctrl_soc_data tgllp_community1_soc_data = {
	261	+ .uid = "1",
	262	+ .pins = tgllp_community1_pins,
	263	+ .npins = ARRAY_SIZE(tgllp_community1_pins),
	264	+ .communities = tgllp_community1,
	265	+ .ncommunities = ARRAY_SIZE(tgllp_community1),
	266	+};
	267	+
	268	+static const struct pinctrl_pin_desc tgllp_community4_pins[] = {
	269	+ /* GPP_C */
	270	+ PINCTRL_PIN(0, "SMBCLK"),
	271	+ PINCTRL_PIN(1, "SMBDATA"),
	272	+ PINCTRL_PIN(2, "SMBALERTB"),
	273	+ PINCTRL_PIN(3, "SML0CLK"),
	274	+ PINCTRL_PIN(4, "SML0DATA"),
	275	+ PINCTRL_PIN(5, "SML0ALERTB"),
	276	+ PINCTRL_PIN(6, "SML1CLK"),
	277	+ PINCTRL_PIN(7, "SML1DATA"),
	278	+ PINCTRL_PIN(8, "UART0_RXD"),
	279	+ PINCTRL_PIN(9, "UART0_TXD"),
	280	+ PINCTRL_PIN(10, "UART0_RTSB"),
	281	+ PINCTRL_PIN(11, "UART0_CTSB"),
	282	+ PINCTRL_PIN(12, "UART1_RXD"),
	283	+ PINCTRL_PIN(13, "UART1_TXD"),
	284	+ PINCTRL_PIN(14, "UART1_RTSB"),
	285	+ PINCTRL_PIN(15, "UART1_CTSB"),
	286	+ PINCTRL_PIN(16, "I2C0_SDA"),
	287	+ PINCTRL_PIN(17, "I2C0_SCL"),
	288	+ PINCTRL_PIN(18, "I2C1_SDA"),
	289	+ PINCTRL_PIN(19, "I2C1_SCL"),
	290	+ PINCTRL_PIN(20, "UART2_RXD"),
	291	+ PINCTRL_PIN(21, "UART2_TXD"),
	292	+ PINCTRL_PIN(22, "UART2_RTSB"),
	293	+ PINCTRL_PIN(23, "UART2_CTSB"),
	294	+ /* GPP_F */
	295	+ PINCTRL_PIN(24, "CNV_BRI_DT"),
	296	+ PINCTRL_PIN(25, "CNV_BRI_RSP"),
	297	+ PINCTRL_PIN(26, "CNV_RGI_DT"),
	298	+ PINCTRL_PIN(27, "CNV_RGI_RSP"),
	299	+ PINCTRL_PIN(28, "CNV_RF_RESET_B"),
	300	+ PINCTRL_PIN(29, "GPPC_F_5"),
	301	+ PINCTRL_PIN(30, "CNV_PA_BLANKING"),
	302	+ PINCTRL_PIN(31, "GPPC_F_7"),
	303	+ PINCTRL_PIN(32, "I2S_MCLK2_INOUT"),
	304	+ PINCTRL_PIN(33, "BOOTMPC"),
	305	+ PINCTRL_PIN(34, "GPPC_F_10"),
	306	+ PINCTRL_PIN(35, "GPPC_F_11"),
	307	+ PINCTRL_PIN(36, "GSXDOUT"),
	308	+ PINCTRL_PIN(37, "GSXSLOAD"),
	309	+ PINCTRL_PIN(38, "GSXDIN"),
	310	+ PINCTRL_PIN(39, "GSXSRESETB"),
	311	+ PINCTRL_PIN(40, "GSXCLK"),
	312	+ PINCTRL_PIN(41, "GMII_MDC"),
	313	+ PINCTRL_PIN(42, "GMII_MDIO"),
	314	+ PINCTRL_PIN(43, "SRCCLKREQB_6"),
	315	+ PINCTRL_PIN(44, "EXT_PWR_GATEB"),
	316	+ PINCTRL_PIN(45, "EXT_PWR_GATE2B"),
	317	+ PINCTRL_PIN(46, "VNN_CTRL"),
	318	+ PINCTRL_PIN(47, "V1P05_CTRL"),
	319	+ PINCTRL_PIN(48, "GPPF_CLK_LOOPBACK"),
	320	+ /* HVCMOS */
	321	+ PINCTRL_PIN(49, "L_BKLTEN"),
	322	+ PINCTRL_PIN(50, "L_BKLTCTL"),
	323	+ PINCTRL_PIN(51, "L_VDDEN"),
	324	+ PINCTRL_PIN(52, "SYS_PWROK"),
	325	+ PINCTRL_PIN(53, "SYS_RESETB"),
	326	+ PINCTRL_PIN(54, "MLK_RSTB"),
	327	+ /* GPP_E */
	328	+ PINCTRL_PIN(55, "SATAXPCIE_0"),
	329	+ PINCTRL_PIN(56, "SPI1_IO_2"),
	330	+ PINCTRL_PIN(57, "SPI1_IO_3"),
	331	+ PINCTRL_PIN(58, "CPU_GP_0"),
	332	+ PINCTRL_PIN(59, "SATA_DEVSLP_0"),
	333	+ PINCTRL_PIN(60, "SATA_DEVSLP_1"),
	334	+ PINCTRL_PIN(61, "GPPC_E_6"),
	335	+ PINCTRL_PIN(62, "CPU_GP_1"),
	336	+ PINCTRL_PIN(63, "SPI1_CS1B"),
	337	+ PINCTRL_PIN(64, "USB2_OCB_0"),
	338	+ PINCTRL_PIN(65, "SPI1_CSB"),
	339	+ PINCTRL_PIN(66, "SPI1_CLK"),
	340	+ PINCTRL_PIN(67, "SPI1_MISO_IO_1"),
	341	+ PINCTRL_PIN(68, "SPI1_MOSI_IO_0"),
	342	+ PINCTRL_PIN(69, "DDSP_HPD_A"),
	343	+ PINCTRL_PIN(70, "ISH_GP_6"),
	344	+ PINCTRL_PIN(71, "ISH_GP_7"),
	345	+ PINCTRL_PIN(72, "GPPC_E_17"),
	346	+ PINCTRL_PIN(73, "DDP1_CTRLCLK"),
	347	+ PINCTRL_PIN(74, "DDP1_CTRLDATA"),
	348	+ PINCTRL_PIN(75, "DDP2_CTRLCLK"),
	349	+ PINCTRL_PIN(76, "DDP2_CTRLDATA"),
	350	+ PINCTRL_PIN(77, "DDPA_CTRLCLK"),
	351	+ PINCTRL_PIN(78, "DDPA_CTRLDATA"),
	352	+ PINCTRL_PIN(79, "SPI1_CLK_LOOPBK"),
	353	+ /* JTAG */
	354	+ PINCTRL_PIN(80, "JTAG_TDO"),
	355	+ PINCTRL_PIN(81, "JTAGX"),
	356	+ PINCTRL_PIN(82, "PRDYB"),
	357	+ PINCTRL_PIN(83, "PREQB"),
	358	+ PINCTRL_PIN(84, "CPU_TRSTB"),
	359	+ PINCTRL_PIN(85, "JTAG_TDI"),
	360	+ PINCTRL_PIN(86, "JTAG_TMS"),
	361	+ PINCTRL_PIN(87, "JTAG_TCK"),
	362	+ PINCTRL_PIN(88, "DBG_PMODE"),
	363	+};
	364	+
	365	+static const struct intel_padgroup tgllp_community4_gpps[] = {
	366	+ TGL_GPP(0, 0, 23), /* GPP_C */
	367	+ TGL_GPP(1, 24, 48), /* GPP_F */
	368	+ TGL_GPP(2, 49, 54), /* HVCMOS */
	369	+ TGL_GPP(3, 55, 79), /* GPP_E */
	370	+ TGL_GPP(4, 80, 88), /* JTAG */
	371	+};
	372	+
	373	+static const struct intel_community tgllp_community4[] = {
	374	+ TGL_COMMUNITY(0, 88, tgllp_community4_gpps),
	375	+};
	376	+
	377	+static const struct intel_pinctrl_soc_data tgllp_community4_soc_data = {
	378	+ .uid = "4",
	379	+ .pins = tgllp_community4_pins,
	380	+ .npins = ARRAY_SIZE(tgllp_community4_pins),
	381	+ .communities = tgllp_community4,
	382	+ .ncommunities = ARRAY_SIZE(tgllp_community4),
	383	+};
	384	+
	385	+static const struct pinctrl_pin_desc tgllp_community5_pins[] = {
	386	+ /* GPP_R */
	387	+ PINCTRL_PIN(0, "HDA_BCLK"),
	388	+ PINCTRL_PIN(1, "HDA_SYNC"),
	389	+ PINCTRL_PIN(2, "HDA_SDO"),
	390	+ PINCTRL_PIN(3, "HDA_SDI_0"),
	391	+ PINCTRL_PIN(4, "HDA_RSTB"),
	392	+ PINCTRL_PIN(5, "HDA_SDI_1"),
	393	+ PINCTRL_PIN(6, "GPP_R_6"),
	394	+ PINCTRL_PIN(7, "GPP_R_7"),
	395	+ /* SPI */
	396	+ PINCTRL_PIN(8, "SPI0_IO_2"),
	397	+ PINCTRL_PIN(9, "SPI0_IO_3"),
	398	+ PINCTRL_PIN(10, "SPI0_MOSI_IO_0"),
	399	+ PINCTRL_PIN(11, "SPI0_MISO_IO_1"),
	400	+ PINCTRL_PIN(12, "SPI0_TPM_CSB"),
	401	+ PINCTRL_PIN(13, "SPI0_FLASH_0_CSB"),
	402	+ PINCTRL_PIN(14, "SPI0_FLASH_1_CSB"),
	403	+ PINCTRL_PIN(15, "SPI0_CLK"),
	404	+ PINCTRL_PIN(16, "SPI0_CLK_LOOPBK"),
	405	+};
	406	+
	407	+static const struct intel_padgroup tgllp_community5_gpps[] = {
	408	+ TGL_GPP(0, 0, 7), /* GPP_R */
	409	+ TGL_GPP(1, 8, 16), /* SPI */
	410	+};
	411	+
	412	+static const struct intel_community tgllp_community5[] = {
	413	+ TGL_COMMUNITY(0, 16, tgllp_community5_gpps),
	414	+};
	415	+
	416	+static const struct intel_pinctrl_soc_data tgllp_community5_soc_data = {
	417	+ .uid = "5",
	418	+ .pins = tgllp_community5_pins,
	419	+ .npins = ARRAY_SIZE(tgllp_community5_pins),
	420	+ .communities = tgllp_community5,
	421	+ .ncommunities = ARRAY_SIZE(tgllp_community5),
	422	+};
	423	+
	424	+static const struct intel_pinctrl_soc_data *tgllp_soc_data_array[] = {
	425	+ &tgllp_community0_soc_data,
	426	+ &tgllp_community1_soc_data,
	427	+ &tgllp_community4_soc_data,
	428	+ &tgllp_community5_soc_data,
	429	+ NULL
	430	+};
	431	+
	432	+static const struct acpi_device_id tgl_pinctrl_acpi_match[] = {
	433	+ { "INT34C5", (kernel_ulong_t)tgllp_soc_data_array },
	434	+ { }
	435	+};
	436	+MODULE_DEVICE_TABLE(acpi, tgl_pinctrl_acpi_match);
	437	+
	438	+static INTEL_PINCTRL_PM_OPS(tgl_pinctrl_pm_ops);
	439	+
	440	+static struct platform_driver tgl_pinctrl_driver = {
	441	+ .probe = intel_pinctrl_probe_by_uid,
	442	+ .driver = {
	443	+ .name = "tigerlake-pinctrl",
	444	+ .acpi_match_table = tgl_pinctrl_acpi_match,
	445	+ .pm = &tgl_pinctrl_pm_ops,
	446	+ },
	447	+};
	448	+
	449	+module_platform_driver(tgl_pinctrl_driver);
	450	+
	451	+MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
	452	+MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
	453	+MODULE_DESCRIPTION("Intel Tiger Lake PCH pinctrl/GPIO driver");
	454	+MODULE_LICENSE("GPL v2");

drivers/pinctrl/mediatek/pinctrl-mtk-common.c+1−3

@@ -982,7 +982,6 @@ static const struct mtk_eint_xt mtk_eint_xt = { · 981 unmodified lines
982	982	static int mtk_eint_init(struct mtk_pinctrl pctl, struct platform_device pdev)
983	983	{
984	984	struct device_node *np = pdev->dev.of_node;
985		− struct resource *res;
986	985
987	986	if (!of_property_read_bool(np, "interrupt-controller"))
988	987	return -ENODEV;
@@ -991,8 +990,7 @@ static int mtk_eint_init(struct mtk_pinctrl pctl, struct platform_device pdev) · 2 unmodified lines
991	990	if (!pctl->eint)
992	991	return -ENOMEM;
993	992
994		− res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
995		− pctl->eint->base = devm_ioremap_resource(&pdev->dev, res);
	993	+ pctl->eint->base = devm_platform_ioremap_resource(pdev, 0);
996	994	if (IS_ERR(pctl->eint->base))
997	995	return PTR_ERR(pctl->eint->base);
998	996

drivers/pinctrl/meson/Kconfig+6−0

@@ -54,4 +54,10 @@ config PINCTRL_MESON_G12A · 53 unmodified lines
54	54	select PINCTRL_MESON_AXG_PMX
55	55	default y
56	56
	57	+config PINCTRL_MESON_A1
	58	+ bool "Meson a1 Soc pinctrl driver"
	59	+ depends on ARM64
	60	+ select PINCTRL_MESON_AXG_PMX
	61	+ default y
	62	+
57	63	endif

drivers/pinctrl/meson/Makefile+1−0

@@ -8,3 +8,4 @@ obj-$(CONFIG_PINCTRL_MESON_GXL) += pinctrl-meson-gxl.o · 7 unmodified lines
8	8	obj-$(CONFIG_PINCTRL_MESON_AXG_PMX) += pinctrl-meson-axg-pmx.o
9	9	obj-$(CONFIG_PINCTRL_MESON_AXG) += pinctrl-meson-axg.o
10	10	obj-$(CONFIG_PINCTRL_MESON_G12A) += pinctrl-meson-g12a.o
	11	+obj-$(CONFIG_PINCTRL_MESON_A1) += pinctrl-meson-a1.o

drivers/pinctrl/meson/pinctrl-meson-a1.c+942−0

@@ -0,0 +1,942 @@
	1	+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	2	+/*
	3	+ * Pin controller and GPIO driver for Amlogic Meson A1 SoC.
	4	+ *
	5	+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
	6	+ * Author: Qianggui Song <qianggui.song@amlogic.com>
	7	+ */
	8	+
	9	+#include <dt-bindings/gpio/meson-a1-gpio.h>
	10	+#include "pinctrl-meson.h"
	11	+#include "pinctrl-meson-axg-pmx.h"
	12	+
	13	+static const struct pinctrl_pin_desc meson_a1_periphs_pins[] = {
	14	+ MESON_PIN(GPIOP_0),
	15	+ MESON_PIN(GPIOP_1),
	16	+ MESON_PIN(GPIOP_2),
	17	+ MESON_PIN(GPIOP_3),
	18	+ MESON_PIN(GPIOP_4),
	19	+ MESON_PIN(GPIOP_5),
	20	+ MESON_PIN(GPIOP_6),
	21	+ MESON_PIN(GPIOP_7),
	22	+ MESON_PIN(GPIOP_8),
	23	+ MESON_PIN(GPIOP_9),
	24	+ MESON_PIN(GPIOP_10),
	25	+ MESON_PIN(GPIOP_11),
	26	+ MESON_PIN(GPIOP_12),
	27	+ MESON_PIN(GPIOB_0),
	28	+ MESON_PIN(GPIOB_1),
	29	+ MESON_PIN(GPIOB_2),
	30	+ MESON_PIN(GPIOB_3),
	31	+ MESON_PIN(GPIOB_4),
	32	+ MESON_PIN(GPIOB_5),
	33	+ MESON_PIN(GPIOB_6),
	34	+ MESON_PIN(GPIOX_0),
	35	+ MESON_PIN(GPIOX_1),
	36	+ MESON_PIN(GPIOX_2),
	37	+ MESON_PIN(GPIOX_3),
	38	+ MESON_PIN(GPIOX_4),
	39	+ MESON_PIN(GPIOX_5),
	40	+ MESON_PIN(GPIOX_6),
	41	+ MESON_PIN(GPIOX_7),
	42	+ MESON_PIN(GPIOX_8),
	43	+ MESON_PIN(GPIOX_9),
	44	+ MESON_PIN(GPIOX_10),
	45	+ MESON_PIN(GPIOX_11),
	46	+ MESON_PIN(GPIOX_12),
	47	+ MESON_PIN(GPIOX_13),
	48	+ MESON_PIN(GPIOX_14),
	49	+ MESON_PIN(GPIOX_15),
	50	+ MESON_PIN(GPIOX_16),
	51	+ MESON_PIN(GPIOF_0),
	52	+ MESON_PIN(GPIOF_1),
	53	+ MESON_PIN(GPIOF_2),
	54	+ MESON_PIN(GPIOF_3),
	55	+ MESON_PIN(GPIOF_4),
	56	+ MESON_PIN(GPIOF_5),
	57	+ MESON_PIN(GPIOF_6),
	58	+ MESON_PIN(GPIOF_7),
	59	+ MESON_PIN(GPIOF_8),
	60	+ MESON_PIN(GPIOF_9),
	61	+ MESON_PIN(GPIOF_10),
	62	+ MESON_PIN(GPIOF_11),
	63	+ MESON_PIN(GPIOF_12),
	64	+ MESON_PIN(GPIOA_0),
	65	+ MESON_PIN(GPIOA_1),
	66	+ MESON_PIN(GPIOA_2),
	67	+ MESON_PIN(GPIOA_3),
	68	+ MESON_PIN(GPIOA_4),
	69	+ MESON_PIN(GPIOA_5),
	70	+ MESON_PIN(GPIOA_6),
	71	+ MESON_PIN(GPIOA_7),
	72	+ MESON_PIN(GPIOA_8),
	73	+ MESON_PIN(GPIOA_9),
	74	+ MESON_PIN(GPIOA_10),
	75	+ MESON_PIN(GPIOA_11),
	76	+};
	77	+
	78	+/* psram */
	79	+static const unsigned int psram_clkn_pins[] = { GPIOP_0 };
	80	+static const unsigned int psram_clkp_pins[] = { GPIOP_1 };
	81	+static const unsigned int psram_ce_n_pins[] = { GPIOP_2 };
	82	+static const unsigned int psram_rst_n_pins[] = { GPIOP_3 };
	83	+static const unsigned int psram_adq0_pins[] = { GPIOP_4 };
	84	+static const unsigned int psram_adq1_pins[] = { GPIOP_5 };
	85	+static const unsigned int psram_adq2_pins[] = { GPIOP_6 };
	86	+static const unsigned int psram_adq3_pins[] = { GPIOP_7 };
	87	+static const unsigned int psram_adq4_pins[] = { GPIOP_8 };
	88	+static const unsigned int psram_adq5_pins[] = { GPIOP_9 };
	89	+static const unsigned int psram_adq6_pins[] = { GPIOP_10 };
	90	+static const unsigned int psram_adq7_pins[] = { GPIOP_11 };
	91	+static const unsigned int psram_dqs_dm_pins[] = { GPIOP_12 };
	92	+
	93	+/* sdcard */
	94	+static const unsigned int sdcard_d0_b_pins[] = { GPIOB_0 };
	95	+static const unsigned int sdcard_d1_b_pins[] = { GPIOB_1 };
	96	+static const unsigned int sdcard_d2_b_pins[] = { GPIOB_2 };
	97	+static const unsigned int sdcard_d3_b_pins[] = { GPIOB_3 };
	98	+static const unsigned int sdcard_clk_b_pins[] = { GPIOB_4 };
	99	+static const unsigned int sdcard_cmd_b_pins[] = { GPIOB_5 };
	100	+
	101	+static const unsigned int sdcard_d0_x_pins[] = { GPIOX_0 };
	102	+static const unsigned int sdcard_d1_x_pins[] = { GPIOX_1 };
	103	+static const unsigned int sdcard_d2_x_pins[] = { GPIOX_2 };
	104	+static const unsigned int sdcard_d3_x_pins[] = { GPIOX_3 };
	105	+static const unsigned int sdcard_clk_x_pins[] = { GPIOX_4 };
	106	+static const unsigned int sdcard_cmd_x_pins[] = { GPIOX_5 };
	107	+
	108	+/* spif */
	109	+static const unsigned int spif_mo_pins[] = { GPIOB_0 };
	110	+static const unsigned int spif_mi_pins[] = { GPIOB_1 };
	111	+static const unsigned int spif_wp_n_pins[] = { GPIOB_2 };
	112	+static const unsigned int spif_hold_n_pins[] = { GPIOB_3 };
	113	+static const unsigned int spif_clk_pins[] = { GPIOB_4 };
	114	+static const unsigned int spif_cs_pins[] = { GPIOB_5 };
	115	+
	116	+/* i2c0 */
	117	+static const unsigned int i2c0_sck_f9_pins[] = { GPIOF_9 };
	118	+static const unsigned int i2c0_sda_f10_pins[] = { GPIOF_10 };
	119	+static const unsigned int i2c0_sck_f11_pins[] = { GPIOF_11 };
	120	+static const unsigned int i2c0_sda_f12_pins[] = { GPIOF_12 };
	121	+
	122	+/* i2c1 */
	123	+static const unsigned int i2c1_sda_x_pins[] = { GPIOX_9 };
	124	+static const unsigned int i2c1_sck_x_pins[] = { GPIOX_10 };
	125	+static const unsigned int i2c1_sda_a_pins[] = { GPIOA_10 };
	126	+static const unsigned int i2c1_sck_a_pins[] = { GPIOA_11 };
	127	+
	128	+/* i2c2 */
	129	+static const unsigned int i2c2_sck_x0_pins[] = { GPIOX_0 };
	130	+static const unsigned int i2c2_sda_x1_pins[] = { GPIOX_1 };
	131	+static const unsigned int i2c2_sck_x15_pins[] = { GPIOX_15 };
	132	+static const unsigned int i2c2_sda_x16_pins[] = { GPIOX_16 };
	133	+static const unsigned int i2c2_sck_a4_pins[] = { GPIOA_4 };
	134	+static const unsigned int i2c2_sda_a5_pins[] = { GPIOA_5 };
	135	+static const unsigned int i2c2_sck_a8_pins[] = { GPIOA_8 };
	136	+static const unsigned int i2c2_sda_a9_pins[] = { GPIOA_9 };
	137	+
	138	+/* i2c3 */
	139	+static const unsigned int i2c3_sck_f_pins[] = { GPIOF_4 };
	140	+static const unsigned int i2c3_sda_f_pins[] = { GPIOF_5 };
	141	+static const unsigned int i2c3_sck_x_pins[] = { GPIOX_11 };
	142	+static const unsigned int i2c3_sda_x_pins[] = { GPIOX_12 };
	143	+
	144	+/* i2c slave */
	145	+static const unsigned int i2c_slave_sck_a_pins[] = { GPIOA_10 };
	146	+static const unsigned int i2c_slave_sda_a_pins[] = { GPIOA_11 };
	147	+static const unsigned int i2c_slave_sck_f_pins[] = { GPIOF_11 };
	148	+static const unsigned int i2c_slave_sda_f_pins[] = { GPIOF_12 };
	149	+
	150	+/* uart_a */
	151	+static const unsigned int uart_a_tx_pins[] = { GPIOX_11 };
	152	+static const unsigned int uart_a_rx_pins[] = { GPIOX_12 };
	153	+static const unsigned int uart_a_cts_pins[] = { GPIOX_13 };
	154	+static const unsigned int uart_a_rts_pins[] = { GPIOX_14 };
	155	+
	156	+/* uart_b */
	157	+static const unsigned int uart_b_tx_x_pins[] = { GPIOX_7 };
	158	+static const unsigned int uart_b_rx_x_pins[] = { GPIOX_8 };
	159	+static const unsigned int uart_b_tx_f_pins[] = { GPIOF_0 };
	160	+static const unsigned int uart_b_rx_f_pins[] = { GPIOF_1 };
	161	+
	162	+/* uart_c */
	163	+static const unsigned int uart_c_tx_x0_pins[] = { GPIOX_0 };
	164	+static const unsigned int uart_c_rx_x1_pins[] = { GPIOX_1 };
	165	+static const unsigned int uart_c_cts_pins[] = { GPIOX_2 };
	166	+static const unsigned int uart_c_rts_pins[] = { GPIOX_3 };
	167	+static const unsigned int uart_c_tx_x15_pins[] = { GPIOX_15 };
	168	+static const unsigned int uart_c_rx_x16_pins[] = { GPIOX_16 };
	169	+
	170	+/* pmw_a */
	171	+static const unsigned int pwm_a_x6_pins[] = { GPIOX_6 };
	172	+static const unsigned int pwm_a_x7_pins[] = { GPIOX_7 };
	173	+static const unsigned int pwm_a_f6_pins[] = { GPIOF_6 };
	174	+static const unsigned int pwm_a_f10_pins[] = { GPIOF_10 };
	175	+static const unsigned int pwm_a_a_pins[] = { GPIOA_5 };
	176	+
	177	+/* pmw_b */
	178	+static const unsigned int pwm_b_x_pins[] = { GPIOX_8 };
	179	+static const unsigned int pwm_b_f_pins[] = { GPIOF_7 };
	180	+static const unsigned int pwm_b_a_pins[] = { GPIOA_11 };
	181	+
	182	+/* pmw_c */
	183	+static const unsigned int pwm_c_x_pins[] = { GPIOX_9 };
	184	+static const unsigned int pwm_c_f3_pins[] = { GPIOF_3 };
	185	+static const unsigned int pwm_c_f8_pins[] = { GPIOF_8 };
	186	+static const unsigned int pwm_c_a_pins[] = { GPIOA_10 };
	187	+
	188	+/* pwm_d */
	189	+static const unsigned int pwm_d_x10_pins[] = { GPIOX_10 };
	190	+static const unsigned int pwm_d_x13_pins[] = { GPIOX_13 };
	191	+static const unsigned int pwm_d_x15_pins[] = { GPIOX_15 };
	192	+static const unsigned int pwm_d_f_pins[] = { GPIOF_11 };
	193	+
	194	+/* pwm_e */
	195	+static const unsigned int pwm_e_p_pins[] = { GPIOP_3 };
	196	+static const unsigned int pwm_e_x2_pins[] = { GPIOX_2 };
	197	+static const unsigned int pwm_e_x14_pins[] = { GPIOX_14 };
	198	+static const unsigned int pwm_e_x16_pins[] = { GPIOX_16 };
	199	+static const unsigned int pwm_e_f_pins[] = { GPIOF_3 };
	200	+static const unsigned int pwm_e_a_pins[] = { GPIOA_0 };
	201	+
	202	+/* pwm_f */
	203	+static const unsigned int pwm_f_b_pins[] = { GPIOB_6 };
	204	+static const unsigned int pwm_f_x_pins[] = { GPIOX_3 };
	205	+static const unsigned int pwm_f_f4_pins[] = { GPIOF_4 };
	206	+static const unsigned int pwm_f_f12_pins[] = { GPIOF_12 };
	207	+
	208	+/* pwm_a_hiz */
	209	+static const unsigned int pwm_a_hiz_f8_pins[] = { GPIOF_8 };
	210	+static const unsigned int pwm_a_hiz_f10_pins[] = { GPIOF_10 };
	211	+static const unsigned int pmw_a_hiz_f6_pins[] = { GPIOF_6 };
	212	+
	213	+/* pwm_b_hiz */
	214	+static const unsigned int pwm_b_hiz_pins[] = { GPIOF_7 };
	215	+
	216	+/* pmw_c_hiz */
	217	+static const unsigned int pwm_c_hiz_pins[] = { GPIOF_8 };
	218	+
	219	+/* tdm_a */
	220	+static const unsigned int tdm_a_dout1_pins[] = { GPIOX_7 };
	221	+static const unsigned int tdm_a_dout0_pins[] = { GPIOX_8 };
	222	+static const unsigned int tdm_a_fs_pins[] = { GPIOX_9 };
	223	+static const unsigned int tdm_a_sclk_pins[] = { GPIOX_10 };
	224	+static const unsigned int tdm_a_din1_pins[] = { GPIOX_7 };
	225	+static const unsigned int tdm_a_din0_pins[] = { GPIOX_8 };
	226	+static const unsigned int tdm_a_slv_fs_pins[] = { GPIOX_9 };
	227	+static const unsigned int tdm_a_slv_sclk_pins[] = { GPIOX_10 };
	228	+
	229	+/* spi_a */
	230	+static const unsigned int spi_a_mosi_x2_pins[] = { GPIOX_2 };
	231	+static const unsigned int spi_a_ss0_x3_pins[] = { GPIOX_3 };
	232	+static const unsigned int spi_a_sclk_x4_pins[] = { GPIOX_4 };
	233	+static const unsigned int spi_a_miso_x5_pins[] = { GPIOX_5 };
	234	+static const unsigned int spi_a_mosi_x7_pins[] = { GPIOX_7 };
	235	+static const unsigned int spi_a_miso_x8_pins[] = { GPIOX_8 };
	236	+static const unsigned int spi_a_ss0_x9_pins[] = { GPIOX_9 };
	237	+static const unsigned int spi_a_sclk_x10_pins[] = { GPIOX_10 };
	238	+
	239	+static const unsigned int spi_a_mosi_a_pins[] = { GPIOA_6 };
	240	+static const unsigned int spi_a_miso_a_pins[] = { GPIOA_7 };
	241	+static const unsigned int spi_a_ss0_a_pins[] = { GPIOA_8 };
	242	+static const unsigned int spi_a_sclk_a_pins[] = { GPIOA_9 };
	243	+
	244	+/* pdm */
	245	+static const unsigned int pdm_din0_x_pins[] = { GPIOX_7 };
	246	+static const unsigned int pdm_din1_x_pins[] = { GPIOX_8 };
	247	+static const unsigned int pdm_din2_x_pins[] = { GPIOX_9 };
	248	+static const unsigned int pdm_dclk_x_pins[] = { GPIOX_10 };
	249	+
	250	+static const unsigned int pdm_din2_a_pins[] = { GPIOA_6 };
	251	+static const unsigned int pdm_din1_a_pins[] = { GPIOA_7 };
	252	+static const unsigned int pdm_din0_a_pins[] = { GPIOA_8 };
	253	+static const unsigned int pdm_dclk_pins[] = { GPIOA_9 };
	254	+
	255	+/* gen_clk */
	256	+static const unsigned int gen_clk_x_pins[] = { GPIOX_7 };
	257	+static const unsigned int gen_clk_f8_pins[] = { GPIOF_8 };
	258	+static const unsigned int gen_clk_f10_pins[] = { GPIOF_10 };
	259	+static const unsigned int gen_clk_a_pins[] = { GPIOA_11 };
	260	+
	261	+/* jtag_a */
	262	+static const unsigned int jtag_a_clk_pins[] = { GPIOF_4 };
	263	+static const unsigned int jtag_a_tms_pins[] = { GPIOF_5 };
	264	+static const unsigned int jtag_a_tdi_pins[] = { GPIOF_6 };
	265	+static const unsigned int jtag_a_tdo_pins[] = { GPIOF_7 };
	266	+
	267	+/* clk_32_in */
	268	+static const unsigned int clk_32k_in_pins[] = { GPIOF_2 };
	269	+
	270	+/* ir in */
	271	+static const unsigned int remote_input_f_pins[] = { GPIOF_3 };
	272	+static const unsigned int remote_input_a_pins[] = { GPIOA_11 };
	273	+
	274	+/* ir out */
	275	+static const unsigned int remote_out_pins[] = { GPIOF_5 };
	276	+
	277	+/* spdif */
	278	+static const unsigned int spdif_in_f6_pins[] = { GPIOF_6 };
	279	+static const unsigned int spdif_in_f7_pins[] = { GPIOF_7 };
	280	+
	281	+/* sw */
	282	+static const unsigned int swclk_pins[] = { GPIOF_4 };
	283	+static const unsigned int swdio_pins[] = { GPIOF_5 };
	284	+
	285	+/* clk_25 */
	286	+static const unsigned int clk25_pins[] = { GPIOF_10 };
	287	+
	288	+/* cec_a */
	289	+static const unsigned int cec_a_pins[] = { GPIOF_2 };
	290	+
	291	+/* cec_b */
	292	+static const unsigned int cec_b_pins[] = { GPIOF_2 };
	293	+
	294	+/* clk12_24 */
	295	+static const unsigned int clk12_24_pins[] = { GPIOF_10 };
	296	+
	297	+/* mclk_0 */
	298	+static const unsigned int mclk_0_pins[] = { GPIOA_0 };
	299	+
	300	+/* tdm_b */
	301	+static const unsigned int tdm_b_sclk_pins[] = { GPIOA_1 };
	302	+static const unsigned int tdm_b_fs_pins[] = { GPIOA_2 };
	303	+static const unsigned int tdm_b_dout0_pins[] = { GPIOA_3 };
	304	+static const unsigned int tdm_b_dout1_pins[] = { GPIOA_4 };
	305	+static const unsigned int tdm_b_dout2_pins[] = { GPIOA_5 };
	306	+static const unsigned int tdm_b_dout3_pins[] = { GPIOA_6 };
	307	+static const unsigned int tdm_b_dout4_pins[] = { GPIOA_7 };
	308	+static const unsigned int tdm_b_dout5_pins[] = { GPIOA_8 };
	309	+static const unsigned int tdm_b_slv_sclk_pins[] = { GPIOA_5 };
	310	+static const unsigned int tdm_b_slv_fs_pins[] = { GPIOA_6 };
	311	+static const unsigned int tdm_b_din0_pins[] = { GPIOA_7 };
	312	+static const unsigned int tdm_b_din1_pins[] = { GPIOA_8 };
	313	+static const unsigned int tdm_b_din2_pins[] = { GPIOA_9 };
	314	+
	315	+/* mclk_vad */
	316	+static const unsigned int mclk_vad_pins[] = { GPIOA_0 };
	317	+
	318	+/* tdm_vad */
	319	+static const unsigned int tdm_vad_sclk_a1_pins[] = { GPIOA_1 };
	320	+static const unsigned int tdm_vad_fs_a2_pins[] = { GPIOA_2 };
	321	+static const unsigned int tdm_vad_sclk_a5_pins[] = { GPIOA_5 };
	322	+static const unsigned int tdm_vad_fs_a6_pins[] = { GPIOA_6 };
	323	+
	324	+/* tst_out */
	325	+static const unsigned int tst_out0_pins[] = { GPIOA_0 };
	326	+static const unsigned int tst_out1_pins[] = { GPIOA_1 };
	327	+static const unsigned int tst_out2_pins[] = { GPIOA_2 };
	328	+static const unsigned int tst_out3_pins[] = { GPIOA_3 };
	329	+static const unsigned int tst_out4_pins[] = { GPIOA_4 };
	330	+static const unsigned int tst_out5_pins[] = { GPIOA_5 };
	331	+static const unsigned int tst_out6_pins[] = { GPIOA_6 };
	332	+static const unsigned int tst_out7_pins[] = { GPIOA_7 };
	333	+static const unsigned int tst_out8_pins[] = { GPIOA_8 };
	334	+static const unsigned int tst_out9_pins[] = { GPIOA_9 };
	335	+static const unsigned int tst_out10_pins[] = { GPIOA_10 };
	336	+static const unsigned int tst_out11_pins[] = { GPIOA_11 };
	337	+
	338	+/* mute */
	339	+static const unsigned int mute_key_pins[] = { GPIOA_4 };
	340	+static const unsigned int mute_en_pins[] = { GPIOA_5 };
	341	+
	342	+static struct meson_pmx_group meson_a1_periphs_groups[] = {
	343	+ GPIO_GROUP(GPIOP_0),
	344	+ GPIO_GROUP(GPIOP_1),
	345	+ GPIO_GROUP(GPIOP_2),
	346	+ GPIO_GROUP(GPIOP_3),
	347	+ GPIO_GROUP(GPIOP_4),
	348	+ GPIO_GROUP(GPIOP_5),
	349	+ GPIO_GROUP(GPIOP_6),
	350	+ GPIO_GROUP(GPIOP_7),
	351	+ GPIO_GROUP(GPIOP_8),
	352	+ GPIO_GROUP(GPIOP_9),
	353	+ GPIO_GROUP(GPIOP_10),
	354	+ GPIO_GROUP(GPIOP_11),
	355	+ GPIO_GROUP(GPIOP_12),
	356	+ GPIO_GROUP(GPIOB_0),
	357	+ GPIO_GROUP(GPIOB_1),
	358	+ GPIO_GROUP(GPIOB_2),
	359	+ GPIO_GROUP(GPIOB_3),
	360	+ GPIO_GROUP(GPIOB_4),
	361	+ GPIO_GROUP(GPIOB_5),
	362	+ GPIO_GROUP(GPIOB_6),
	363	+ GPIO_GROUP(GPIOX_0),
	364	+ GPIO_GROUP(GPIOX_1),
	365	+ GPIO_GROUP(GPIOX_2),
	366	+ GPIO_GROUP(GPIOX_3),
	367	+ GPIO_GROUP(GPIOX_4),
	368	+ GPIO_GROUP(GPIOX_5),
	369	+ GPIO_GROUP(GPIOX_6),
	370	+ GPIO_GROUP(GPIOX_7),
	371	+ GPIO_GROUP(GPIOX_8),
	372	+ GPIO_GROUP(GPIOX_9),
	373	+ GPIO_GROUP(GPIOX_10),
	374	+ GPIO_GROUP(GPIOX_11),
	375	+ GPIO_GROUP(GPIOX_12),
	376	+ GPIO_GROUP(GPIOX_13),
	377	+ GPIO_GROUP(GPIOX_14),
	378	+ GPIO_GROUP(GPIOX_15),
	379	+ GPIO_GROUP(GPIOX_16),
	380	+ GPIO_GROUP(GPIOF_0),
	381	+ GPIO_GROUP(GPIOF_1),
	382	+ GPIO_GROUP(GPIOF_2),
	383	+ GPIO_GROUP(GPIOF_3),
	384	+ GPIO_GROUP(GPIOF_4),
	385	+ GPIO_GROUP(GPIOF_5),
	386	+ GPIO_GROUP(GPIOF_6),
	387	+ GPIO_GROUP(GPIOF_7),
	388	+ GPIO_GROUP(GPIOF_8),
	389	+ GPIO_GROUP(GPIOF_9),
	390	+ GPIO_GROUP(GPIOF_10),
	391	+ GPIO_GROUP(GPIOF_11),
	392	+ GPIO_GROUP(GPIOF_12),
	393	+ GPIO_GROUP(GPIOA_0),
	394	+ GPIO_GROUP(GPIOA_1),
	395	+ GPIO_GROUP(GPIOA_2),
	396	+ GPIO_GROUP(GPIOA_3),
	397	+ GPIO_GROUP(GPIOA_4),
	398	+ GPIO_GROUP(GPIOA_5),
	399	+ GPIO_GROUP(GPIOA_6),
	400	+ GPIO_GROUP(GPIOA_7),
	401	+ GPIO_GROUP(GPIOA_8),
	402	+ GPIO_GROUP(GPIOA_9),
	403	+ GPIO_GROUP(GPIOA_10),
	404	+ GPIO_GROUP(GPIOA_11),
	405	+
	406	+ /* bank P func1 */
	407	+ GROUP(psram_clkn, 1),
	408	+ GROUP(psram_clkp, 1),
	409	+ GROUP(psram_ce_n, 1),
	410	+ GROUP(psram_rst_n, 1),
	411	+ GROUP(psram_adq0, 1),
	412	+ GROUP(psram_adq1, 1),
	413	+ GROUP(psram_adq2, 1),
	414	+ GROUP(psram_adq3, 1),
	415	+ GROUP(psram_adq4, 1),
	416	+ GROUP(psram_adq5, 1),
	417	+ GROUP(psram_adq6, 1),
	418	+ GROUP(psram_adq7, 1),
	419	+ GROUP(psram_dqs_dm, 1),
	420	+
	421	+ /bank P func2 /
	422	+ GROUP(pwm_e_p, 2),
	423	+
	424	+ /bank B func1 /
	425	+ GROUP(spif_mo, 1),
	426	+ GROUP(spif_mi, 1),
	427	+ GROUP(spif_wp_n, 1),
	428	+ GROUP(spif_hold_n, 1),
	429	+ GROUP(spif_clk, 1),
	430	+ GROUP(spif_cs, 1),
	431	+ GROUP(pwm_f_b, 1),
	432	+
	433	+ /bank B func2 /
	434	+ GROUP(sdcard_d0_b, 2),
	435	+ GROUP(sdcard_d1_b, 2),
	436	+ GROUP(sdcard_d2_b, 2),
	437	+ GROUP(sdcard_d3_b, 2),
	438	+ GROUP(sdcard_clk_b, 2),
	439	+ GROUP(sdcard_cmd_b, 2),
	440	+
	441	+ /bank X func1 /
	442	+ GROUP(sdcard_d0_x, 1),
	443	+ GROUP(sdcard_d1_x, 1),
	444	+ GROUP(sdcard_d2_x, 1),
	445	+ GROUP(sdcard_d3_x, 1),
	446	+ GROUP(sdcard_clk_x, 1),
	447	+ GROUP(sdcard_cmd_x, 1),
	448	+ GROUP(pwm_a_x6, 1),
	449	+ GROUP(tdm_a_dout1, 1),
	450	+ GROUP(tdm_a_dout0, 1),
	451	+ GROUP(tdm_a_fs, 1),
	452	+ GROUP(tdm_a_sclk, 1),
	453	+ GROUP(uart_a_tx, 1),
	454	+ GROUP(uart_a_rx, 1),
	455	+ GROUP(uart_a_cts, 1),
	456	+ GROUP(uart_a_rts, 1),
	457	+ GROUP(pwm_d_x15, 1),
	458	+ GROUP(pwm_e_x16, 1),
	459	+
	460	+ /bank X func2 /
	461	+ GROUP(i2c2_sck_x0, 2),
	462	+ GROUP(i2c2_sda_x1, 2),
	463	+ GROUP(spi_a_mosi_x2, 2),
	464	+ GROUP(spi_a_ss0_x3, 2),
	465	+ GROUP(spi_a_sclk_x4, 2),
	466	+ GROUP(spi_a_miso_x5, 2),
	467	+ GROUP(tdm_a_din1, 2),
	468	+ GROUP(tdm_a_din0, 2),
	469	+ GROUP(tdm_a_slv_fs, 2),
	470	+ GROUP(tdm_a_slv_sclk, 2),
	471	+ GROUP(i2c3_sck_x, 2),
	472	+ GROUP(i2c3_sda_x, 2),
	473	+ GROUP(pwm_d_x13, 2),
	474	+ GROUP(pwm_e_x14, 2),
	475	+ GROUP(i2c2_sck_x15, 2),
	476	+ GROUP(i2c2_sda_x16, 2),
	477	+
	478	+ /bank X func3 /
	479	+ GROUP(uart_c_tx_x0, 3),
	480	+ GROUP(uart_c_rx_x1, 3),
	481	+ GROUP(uart_c_cts, 3),
	482	+ GROUP(uart_c_rts, 3),
	483	+ GROUP(pdm_din0_x, 3),
	484	+ GROUP(pdm_din1_x, 3),
	485	+ GROUP(pdm_din2_x, 3),
	486	+ GROUP(pdm_dclk_x, 3),
	487	+ GROUP(uart_c_tx_x15, 3),
	488	+ GROUP(uart_c_rx_x16, 3),
	489	+
	490	+ /bank X func4 /
	491	+ GROUP(pwm_e_x2, 4),
	492	+ GROUP(pwm_f_x, 4),
	493	+ GROUP(spi_a_mosi_x7, 4),
	494	+ GROUP(spi_a_miso_x8, 4),
	495	+ GROUP(spi_a_ss0_x9, 4),
	496	+ GROUP(spi_a_sclk_x10, 4),
	497	+
	498	+ /bank X func5 /
	499	+ GROUP(uart_b_tx_x, 5),
	500	+ GROUP(uart_b_rx_x, 5),
	501	+ GROUP(i2c1_sda_x, 5),
	502	+ GROUP(i2c1_sck_x, 5),
	503	+
	504	+ /bank X func6 /
	505	+ GROUP(pwm_a_x7, 6),
	506	+ GROUP(pwm_b_x, 6),
	507	+ GROUP(pwm_c_x, 6),
	508	+ GROUP(pwm_d_x10, 6),
	509	+
	510	+ /bank X func7 /
	511	+ GROUP(gen_clk_x, 7),
	512	+
	513	+ /bank F func1 /
	514	+ GROUP(uart_b_tx_f, 1),
	515	+ GROUP(uart_b_rx_f, 1),
	516	+ GROUP(remote_input_f, 1),
	517	+ GROUP(jtag_a_clk, 1),
	518	+ GROUP(jtag_a_tms, 1),
	519	+ GROUP(jtag_a_tdi, 1),
	520	+ GROUP(jtag_a_tdo, 1),
	521	+ GROUP(gen_clk_f8, 1),
	522	+ GROUP(pwm_a_f10, 1),
	523	+ GROUP(i2c0_sck_f11, 1),
	524	+ GROUP(i2c0_sda_f12, 1),
	525	+
	526	+ /bank F func2 /
	527	+ GROUP(clk_32k_in, 2),
	528	+ GROUP(pwm_e_f, 2),
	529	+ GROUP(pwm_f_f4, 2),
	530	+ GROUP(remote_out, 2),
	531	+ GROUP(spdif_in_f6, 2),
	532	+ GROUP(spdif_in_f7, 2),
	533	+ GROUP(pwm_a_hiz_f8, 2),
	534	+ GROUP(pwm_a_hiz_f10, 2),
	535	+ GROUP(pwm_d_f, 2),
	536	+ GROUP(pwm_f_f12, 2),
	537	+
	538	+ /bank F func3 /
	539	+ GROUP(pwm_c_f3, 3),
	540	+ GROUP(swclk, 3),
	541	+ GROUP(swdio, 3),
	542	+ GROUP(pwm_a_f6, 3),
	543	+ GROUP(pwm_b_f, 3),
	544	+ GROUP(pwm_c_f8, 3),
	545	+ GROUP(clk25, 3),
	546	+ GROUP(i2c_slave_sck_f, 3),
	547	+ GROUP(i2c_slave_sda_f, 3),
	548	+
	549	+ /bank F func4 /
	550	+ GROUP(cec_a, 4),
	551	+ GROUP(i2c3_sck_f, 4),
	552	+ GROUP(i2c3_sda_f, 4),
	553	+ GROUP(pmw_a_hiz_f6, 4),
	554	+ GROUP(pwm_b_hiz, 4),
	555	+ GROUP(pwm_c_hiz, 4),
	556	+ GROUP(i2c0_sck_f9, 4),
	557	+ GROUP(i2c0_sda_f10, 4),
	558	+
	559	+ /bank F func5 /
	560	+ GROUP(cec_b, 5),
	561	+ GROUP(clk12_24, 5),
	562	+
	563	+ /bank F func7 /
	564	+ GROUP(gen_clk_f10, 7),
	565	+
	566	+ /bank A func1 /
	567	+ GROUP(mclk_0, 1),
	568	+ GROUP(tdm_b_sclk, 1),
	569	+ GROUP(tdm_b_fs, 1),
	570	+ GROUP(tdm_b_dout0, 1),
	571	+ GROUP(tdm_b_dout1, 1),
	572	+ GROUP(tdm_b_dout2, 1),
	573	+ GROUP(tdm_b_dout3, 1),
	574	+ GROUP(tdm_b_dout4, 1),
	575	+ GROUP(tdm_b_dout5, 1),
	576	+ GROUP(remote_input_a, 1),
	577	+
	578	+ /bank A func2 /
	579	+ GROUP(pwm_e_a, 2),
	580	+ GROUP(tdm_b_slv_sclk, 2),
	581	+ GROUP(tdm_b_slv_fs, 2),
	582	+ GROUP(tdm_b_din0, 2),
	583	+ GROUP(tdm_b_din1, 2),
	584	+ GROUP(tdm_b_din2, 2),
	585	+ GROUP(i2c1_sda_a, 2),
	586	+ GROUP(i2c1_sck_a, 2),
	587	+
	588	+ /bank A func3 /
	589	+ GROUP(i2c2_sck_a4, 3),
	590	+ GROUP(i2c2_sda_a5, 3),
	591	+ GROUP(pdm_din2_a, 3),
	592	+ GROUP(pdm_din1_a, 3),
	593	+ GROUP(pdm_din0_a, 3),
	594	+ GROUP(pdm_dclk, 3),
	595	+ GROUP(pwm_c_a, 3),
	596	+ GROUP(pwm_b_a, 3),
	597	+
	598	+ /bank A func4 /
	599	+ GROUP(pwm_a_a, 4),
	600	+ GROUP(spi_a_mosi_a, 4),
	601	+ GROUP(spi_a_miso_a, 4),
	602	+ GROUP(spi_a_ss0_a, 4),
	603	+ GROUP(spi_a_sclk_a, 4),
	604	+ GROUP(i2c_slave_sck_a, 4),
	605	+ GROUP(i2c_slave_sda_a, 4),
	606	+
	607	+ /bank A func5 /
	608	+ GROUP(mclk_vad, 5),
	609	+ GROUP(tdm_vad_sclk_a1, 5),
	610	+ GROUP(tdm_vad_fs_a2, 5),
	611	+ GROUP(tdm_vad_sclk_a5, 5),
	612	+ GROUP(tdm_vad_fs_a6, 5),
	613	+ GROUP(i2c2_sck_a8, 5),
	614	+ GROUP(i2c2_sda_a9, 5),
	615	+
	616	+ /bank A func6 /
	617	+ GROUP(tst_out0, 6),
	618	+ GROUP(tst_out1, 6),
	619	+ GROUP(tst_out2, 6),
	620	+ GROUP(tst_out3, 6),
	621	+ GROUP(tst_out4, 6),
	622	+ GROUP(tst_out5, 6),
	623	+ GROUP(tst_out6, 6),
	624	+ GROUP(tst_out7, 6),
	625	+ GROUP(tst_out8, 6),
	626	+ GROUP(tst_out9, 6),
	627	+ GROUP(tst_out10, 6),
	628	+ GROUP(tst_out11, 6),
	629	+
	630	+ /bank A func7 /
	631	+ GROUP(mute_key, 7),
	632	+ GROUP(mute_en, 7),
	633	+ GROUP(gen_clk_a, 7),
	634	+};
	635	+
	636	+static const char * const gpio_periphs_groups[] = {
	637	+ "GPIOP_0", "GPIOP_1", "GPIOP_2", "GPIOP_3", "GPIOP_4",
	638	+ "GPIOP_5", "GPIOP_6", "GPIOP_7", "GPIOP_8", "GPIOP_9",
	639	+ "GPIOP_10", "GPIOP_11", "GPIOP_12",
	640	+
	641	+ "GPIOB_0", "GPIOB_1", "GPIOB_2", "GPIOB_3", "GPIOB_4",
	642	+ "GPIOB_5", "GPIOB_6",
	643	+
	644	+ "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4",
	645	+ "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9",
	646	+ "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14",
	647	+ "GPIOX_15", "GPIOX_16",
	648	+
	649	+ "GPIOF_0", "GPIOF_1", "GPIOF_2", "GPIOF_3", "GPIOF_4",
	650	+ "GPIOF_5", "GPIOF_6", "GPIOF_7", "GPIOF_8", "GPIOF_9",
	651	+ "GPIOF_10", "GPIOF_11", "GPIOF_12",
	652	+
	653	+ "GPIOA_0", "GPIOA_1", "GPIOA_2", "GPIOA_3", "GPIOA_4",
	654	+ "GPIOA_5", "GPIOA_6", "GPIOA_7", "GPIOA_8", "GPIOA_9",
	655	+ "GPIOA_10", "GPIOA_11",
	656	+};
	657	+
	658	+static const char * const psram_groups[] = {
	659	+ "psram_clkn", "psram_clkp", "psram_ce_n", "psram_rst_n", "psram_adq0",
	660	+ "psram_adq1", "psram_adq2", "psram_adq3", "psram_adq4", "psram_adq5",
	661	+ "psram_adq6", "psram_adq7", "psram_dqs_dm",
	662	+};
	663	+
	664	+static const char * const pwm_a_groups[] = {
	665	+ "pwm_a_x6", "pwm_a_x7", "pwm_a_f10", "pwm_a_f6", "pwm_a_a",
	666	+};
	667	+
	668	+static const char * const pwm_b_groups[] = {
	669	+ "pwm_b_x", "pwm_b_f", "pwm_b_a",
	670	+};
	671	+
	672	+static const char * const pwm_c_groups[] = {
	673	+ "pwm_c_x", "pwm_c_f3", "pwm_c_f8", "pwm_c_a",
	674	+};
	675	+
	676	+static const char * const pwm_d_groups[] = {
	677	+ "pwm_d_x15", "pwm_d_x13", "pwm_d_x10", "pwm_d_f",
	678	+};
	679	+
	680	+static const char * const pwm_e_groups[] = {
	681	+ "pwm_e_p", "pwm_e_x16", "pwm_e_x14", "pwm_e_x2", "pwm_e_f",
	682	+ "pwm_e_a",
	683	+};
	684	+
	685	+static const char * const pwm_f_groups[] = {
	686	+ "pwm_f_b", "pwm_f_x", "pwm_f_f4", "pwm_f_f12",
	687	+};
	688	+
	689	+static const char * const pwm_a_hiz_groups[] = {
	690	+ "pwm_a_hiz_f8", "pwm_a_hiz_f10", "pwm_a_hiz_f6",
	691	+};
	692	+
	693	+static const char * const pwm_b_hiz_groups[] = {
	694	+ "pwm_b_hiz",
	695	+};
	696	+
	697	+static const char * const pwm_c_hiz_groups[] = {
	698	+ "pwm_c_hiz",
	699	+};
	700	+
	701	+static const char * const spif_groups[] = {
	702	+ "spif_mo", "spif_mi", "spif_wp_n", "spif_hold_n", "spif_clk",
	703	+ "spif_cs",
	704	+};
	705	+
	706	+static const char * const sdcard_groups[] = {
	707	+ "sdcard_d0_b", "sdcard_d1_b", "sdcard_d2_b", "sdcard_d3_b",
	708	+ "sdcard_clk_b", "sdcard_cmd_b",
	709	+
	710	+ "sdcard_d0_x", "sdcard_d1_x", "sdcard_d2_x", "sdcard_d3_x",
	711	+ "sdcard_clk_x", "sdcard_cmd_x",
	712	+};
	713	+
	714	+static const char * const tdm_a_groups[] = {
	715	+ "tdm_a_din0", "tdm_a_din1", "tdm_a_fs", "tdm_a_sclk",
	716	+ "tdm_a_slv_fs", "tdm_a_slv_sclk", "tdm_a_dout0", "tdm_a_dout1",
	717	+};
	718	+
	719	+static const char * const uart_a_groups[] = {
	720	+ "uart_a_tx", "uart_a_rx", "uart_a_cts", "uart_a_rts",
	721	+};
	722	+
	723	+static const char * const uart_b_groups[] = {
	724	+ "uart_b_tx_x", "uart_b_rx_x", "uart_b_tx_f", "uart_b_rx_f",
	725	+};
	726	+
	727	+static const char * const uart_c_groups[] = {
	728	+ "uart_c_tx_x0", "uart_c_rx_x1", "uart_c_cts", "uart_c_rts",
	729	+ "uart_c_tx_x15", "uart_c_rx_x16",
	730	+};
	731	+
	732	+static const char * const i2c0_groups[] = {
	733	+ "i2c0_sck_f11", "i2c0_sda_f12", "i2c0_sck_f9", "i2c0_sda_f10",
	734	+};
	735	+
	736	+static const char * const i2c1_groups[] = {
	737	+ "i2c1_sda_x", "i2c1_sck_x", "i2c1_sda_a", "i2c1_sck_a",
	738	+};
	739	+
	740	+static const char * const i2c2_groups[] = {
	741	+ "i2c2_sck_x0", "i2c2_sda_x1", "i2c2_sck_x15", "i2c2_sda_x16",
	742	+ "i2c2_sck_a4", "i2c2_sda_a5", "i2c2_sck_a8", "i2c2_sda_a9",
	743	+};
	744	+
	745	+static const char * const i2c3_groups[] = {
	746	+ "i2c3_sck_x", "i2c3_sda_x", "i2c3_sck_f", "i2c3_sda_f",
	747	+};
	748	+
	749	+static const char * const i2c_slave_groups[] = {
	750	+ "i2c_slave_sda_a", "i2c_slave_sck_a",
	751	+ "i2c_slave_sda_f", "i2c_slave_sck_f",
	752	+};
	753	+
	754	+static const char * const spi_a_groups[] = {
	755	+ "spi_a_mosi_x2", "spi_a_ss0_x3", "spi_a_sclk_x4", "spi_a_miso_x5",
	756	+ "spi_a_mosi_x7", "spi_a_miso_x8", "spi_a_ss0_x9", "spi_a_sclk_x10",
	757	+
	758	+ "spi_a_mosi_a", "spi_a_miso_a", "spi_a_ss0_a", "spi_a_sclk_a",
	759	+};
	760	+
	761	+static const char * const pdm_groups[] = {
	762	+ "pdm_din0_x", "pdm_din1_x", "pdm_din2_x", "pdm_dclk_x", "pdm_din2_a",
	763	+ "pdm_din1_a", "pdm_din0_a", "pdm_dclk",
	764	+};
	765	+
	766	+static const char * const gen_clk_groups[] = {
	767	+ "gen_clk_x", "gen_clk_f8", "gen_clk_f10", "gen_clk_a",
	768	+};
	769	+
	770	+static const char * const remote_input_groups[] = {
	771	+ "remote_input_f",
	772	+ "remote_input_a",
	773	+};
	774	+
	775	+static const char * const jtag_a_groups[] = {
	776	+ "jtag_a_clk", "jtag_a_tms", "jtag_a_tdi", "jtag_a_tdo",
	777	+};
	778	+
	779	+static const char * const clk_32k_in_groups[] = {
	780	+ "clk_32k_in",
	781	+};
	782	+
	783	+static const char * const remote_out_groups[] = {
	784	+ "remote_out",
	785	+};
	786	+
	787	+static const char * const spdif_in_groups[] = {
	788	+ "spdif_in_f6", "spdif_in_f7",
	789	+};
	790	+
	791	+static const char * const sw_groups[] = {
	792	+ "swclk", "swdio",
	793	+};
	794	+
	795	+static const char * const clk25_groups[] = {
	796	+ "clk_25",
	797	+};
	798	+
	799	+static const char * const cec_a_groups[] = {
	800	+ "cec_a",
	801	+};
	802	+
	803	+static const char * const cec_b_groups[] = {
	804	+ "cec_b",
	805	+};
	806	+
	807	+static const char * const clk12_24_groups[] = {
	808	+ "clk12_24",
	809	+};
	810	+
	811	+static const char * const mclk_0_groups[] = {
	812	+ "mclk_0",
	813	+};
	814	+
	815	+static const char * const tdm_b_groups[] = {
	816	+ "tdm_b_din0", "tdm_b_din1", "tdm_b_din2",
	817	+ "tdm_b_sclk", "tdm_b_fs", "tdm_b_dout0", "tdm_b_dout1",
	818	+ "tdm_b_dout2", "tdm_b_dout3", "tdm_b_dout4", "tdm_b_dout5",
	819	+ "tdm_b_slv_sclk", "tdm_b_slv_fs",
	820	+};
	821	+
	822	+static const char * const mclk_vad_groups[] = {
	823	+ "mclk_vad",
	824	+};
	825	+
	826	+static const char * const tdm_vad_groups[] = {
	827	+ "tdm_vad_sclk_a1", "tdm_vad_fs_a2", "tdm_vad_sclk_a5", "tdm_vad_fs_a6",
	828	+};
	829	+
	830	+static const char * const tst_out_groups[] = {
	831	+ "tst_out0", "tst_out1", "tst_out2", "tst_out3",
	832	+ "tst_out4", "tst_out5", "tst_out6", "tst_out7",
	833	+ "tst_out8", "tst_out9", "tst_out10", "tst_out11",
	834	+};
	835	+
	836	+static const char * const mute_groups[] = {
	837	+ "mute_key", "mute_en",
	838	+};
	839	+
	840	+static struct meson_pmx_func meson_a1_periphs_functions[] = {
	841	+ FUNCTION(gpio_periphs),
	842	+ FUNCTION(psram),
	843	+ FUNCTION(pwm_a),
	844	+ FUNCTION(pwm_b),
	845	+ FUNCTION(pwm_c),
	846	+ FUNCTION(pwm_d),
	847	+ FUNCTION(pwm_e),
	848	+ FUNCTION(pwm_f),
	849	+ FUNCTION(pwm_a_hiz),
	850	+ FUNCTION(pwm_b_hiz),
	851	+ FUNCTION(pwm_c_hiz),
	852	+ FUNCTION(spif),
	853	+ FUNCTION(sdcard),
	854	+ FUNCTION(tdm_a),
	855	+ FUNCTION(uart_a),
	856	+ FUNCTION(uart_b),
	857	+ FUNCTION(uart_c),
	858	+ FUNCTION(i2c0),
	859	+ FUNCTION(i2c1),
	860	+ FUNCTION(i2c2),
	861	+ FUNCTION(i2c3),
	862	+ FUNCTION(spi_a),
	863	+ FUNCTION(pdm),
	864	+ FUNCTION(gen_clk),
	865	+ FUNCTION(remote_input),
	866	+ FUNCTION(jtag_a),
	867	+ FUNCTION(clk_32k_in),
	868	+ FUNCTION(remote_out),
	869	+ FUNCTION(spdif_in),
	870	+ FUNCTION(sw),
	871	+ FUNCTION(clk25),
	872	+ FUNCTION(cec_a),
	873	+ FUNCTION(cec_b),
	874	+ FUNCTION(clk12_24),
	875	+ FUNCTION(mclk_0),
	876	+ FUNCTION(tdm_b),
	877	+ FUNCTION(mclk_vad),
	878	+ FUNCTION(tdm_vad),
	879	+ FUNCTION(tst_out),
	880	+ FUNCTION(mute),
	881	+};
	882	+
	883	+static struct meson_bank meson_a1_periphs_banks[] = {
	884	+ /* name first last irq pullen pull dir out in ds*/
	885	+ BANK_DS("P", GPIOP_0, GPIOP_12, 0, 12, 0x3, 0, 0x4, 0,
	886	+ 0x2, 0, 0x1, 0, 0x0, 0, 0x5, 0),
	887	+ BANK_DS("B", GPIOB_0, GPIOB_6, 13, 19, 0x13, 0, 0x14, 0,
	888	+ 0x12, 0, 0x11, 0, 0x10, 0, 0x15, 0),
	889	+ BANK_DS("X", GPIOX_0, GPIOX_16, 20, 36, 0x23, 0, 0x24, 0,
	890	+ 0x22, 0, 0x21, 0, 0x20, 0, 0x25, 0),
	891	+ BANK_DS("F", GPIOF_0, GPIOF_12, 37, 49, 0x33, 0, 0x34, 0,
	892	+ 0x32, 0, 0x31, 0, 0x30, 0, 0x35, 0),
	893	+ BANK_DS("A", GPIOA_0, GPIOA_11, 50, 61, 0x43, 0, 0x44, 0,
	894	+ 0x42, 0, 0x41, 0, 0x40, 0, 0x45, 0),
	895	+};
	896	+
	897	+static struct meson_pmx_bank meson_a1_periphs_pmx_banks[] = {
	898	+ /* name first lask reg offset */
	899	+ BANK_PMX("P", GPIOP_0, GPIOP_12, 0x0, 0),
	900	+ BANK_PMX("B", GPIOB_0, GPIOB_6, 0x2, 0),
	901	+ BANK_PMX("X", GPIOX_0, GPIOX_16, 0x3, 0),
	902	+ BANK_PMX("F", GPIOF_0, GPIOF_12, 0x6, 0),
	903	+ BANK_PMX("A", GPIOA_0, GPIOA_11, 0x8, 0),
	904	+};
	905	+
	906	+static struct meson_axg_pmx_data meson_a1_periphs_pmx_banks_data = {
	907	+ .pmx_banks = meson_a1_periphs_pmx_banks,
	908	+ .num_pmx_banks = ARRAY_SIZE(meson_a1_periphs_pmx_banks),
	909	+};
	910	+
	911	+static struct meson_pinctrl_data meson_a1_periphs_pinctrl_data = {
	912	+ .name = "periphs-banks",
	913	+ .pins = meson_a1_periphs_pins,
	914	+ .groups = meson_a1_periphs_groups,
	915	+ .funcs = meson_a1_periphs_functions,
	916	+ .banks = meson_a1_periphs_banks,
	917	+ .num_pins = ARRAY_SIZE(meson_a1_periphs_pins),
	918	+ .num_groups = ARRAY_SIZE(meson_a1_periphs_groups),
	919	+ .num_funcs = ARRAY_SIZE(meson_a1_periphs_functions),
	920	+ .num_banks = ARRAY_SIZE(meson_a1_periphs_banks),
	921	+ .pmx_ops = &meson_axg_pmx_ops,
	922	+ .pmx_data = &meson_a1_periphs_pmx_banks_data,
	923	+ .parse_dt = &meson_a1_parse_dt_extra,
	924	+};
	925	+
	926	+static const struct of_device_id meson_a1_pinctrl_dt_match[] = {
	927	+ {
	928	+ .compatible = "amlogic,meson-a1-periphs-pinctrl",
	929	+ .data = &meson_a1_periphs_pinctrl_data,
	930	+ },
	931	+ { },
	932	+};
	933	+
	934	+static struct platform_driver meson_a1_pinctrl_driver = {
	935	+ .probe = meson_pinctrl_probe,
	936	+ .driver = {
	937	+ .name = "meson-a1-pinctrl",
	938	+ .of_match_table = meson_a1_pinctrl_dt_match,
	939	+ },
	940	+};
	941	+
	942	+builtin_platform_driver(meson_a1_pinctrl_driver);

drivers/pinctrl/meson/pinctrl-meson-axg.c+1−0

@@ -1066,6 +1066,7 @@ static struct meson_pinctrl_data meson_axg_aobus_pinctrl_data = { · 1065 unmodified lines
1066	1066	.num_banks = ARRAY_SIZE(meson_axg_aobus_banks),
1067	1067	.pmx_ops = &meson_axg_pmx_ops,
1068	1068	.pmx_data = &meson_axg_aobus_pmx_banks_data,
	1069	+ .parse_dt = meson8_aobus_parse_dt_extra,
1069	1070	};
1070	1071
1071	1072	static const struct of_device_id meson_axg_pinctrl_dt_match[] = {

drivers/pinctrl/meson/pinctrl-meson-g12a.c+9−0

@@ -1362,6 +1362,14 @@ static struct meson_axg_pmx_data meson_g12a_aobus_pmx_banks_data = { · 1361 unmodified lines
1362	1362	.num_pmx_banks = ARRAY_SIZE(meson_g12a_aobus_pmx_banks),
1363	1363	};
1364	1364
	1365	+static int meson_g12a_aobus_parse_dt_extra(struct meson_pinctrl *pc)
	1366	+{
	1367	+ pc->reg_pull = pc->reg_gpio;
	1368	+ pc->reg_pullen = pc->reg_gpio;
	1369	+
	1370	+ return 0;
	1371	+}
	1372	+
1365	1373	static struct meson_pinctrl_data meson_g12a_periphs_pinctrl_data = {
1366	1374	.name = "periphs-banks",
1367	1375	.pins = meson_g12a_periphs_pins,
@@ -1388,6 +1396,7 @@ static struct meson_pinctrl_data meson_g12a_aobus_pinctrl_data = { · 20 unmodified lines
1388	1396	.num_banks = ARRAY_SIZE(meson_g12a_aobus_banks),
1389	1397	.pmx_ops = &meson_axg_pmx_ops,
1390	1398	.pmx_data = &meson_g12a_aobus_pmx_banks_data,
	1399	+ .parse_dt = meson_g12a_aobus_parse_dt_extra,
1391	1400	};
1392	1401
1393	1402	static const struct of_device_id meson_g12a_pinctrl_dt_match[] = {

drivers/pinctrl/meson/pinctrl-meson-gxbb.c+1−0

@@ -851,6 +851,7 @@ static struct meson_pinctrl_data meson_gxbb_aobus_pinctrl_data = { · 850 unmodified lines
851	851	.num_funcs = ARRAY_SIZE(meson_gxbb_aobus_functions),
852	852	.num_banks = ARRAY_SIZE(meson_gxbb_aobus_banks),
853	853	.pmx_ops = &meson8_pmx_ops,
	854	+ .parse_dt = meson8_aobus_parse_dt_extra,
854	855	};
855	856
856	857	static const struct of_device_id meson_gxbb_pinctrl_dt_match[] = {

drivers/pinctrl/meson/pinctrl-meson-gxl.c+1−0

@@ -820,6 +820,7 @@ static struct meson_pinctrl_data meson_gxl_aobus_pinctrl_data = { · 819 unmodified lines
820	820	.num_funcs = ARRAY_SIZE(meson_gxl_aobus_functions),
821	821	.num_banks = ARRAY_SIZE(meson_gxl_aobus_banks),
822	822	.pmx_ops = &meson8_pmx_ops,
	823	+ .parse_dt = meson8_aobus_parse_dt_extra,
823	824	};
824	825
825	826	static const struct of_device_id meson_gxl_pinctrl_dt_match[] = {

drivers/pinctrl/meson/pinctrl-meson.c+29−9

@@ -625,7 +625,7 @@ static struct regmap meson_map_resource(struct meson_pinctrl pc, · 624 unmodified lines
625	625
626	626	i = of_property_match_string(node, "reg-names", name);
627	627	if (of_address_to_resource(node, i, &res))
628		− return ERR_PTR(-ENOENT);
	628	+ return NULL;
629	629
630	630	base = devm_ioremap_resource(pc->dev, &res);
631	631	if (IS_ERR(base))
@@ -665,26 +665,24 @@ static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc, · 33 unmodified lines
665	665	pc->of_node = gpio_np;
666	666
667	667	pc->reg_mux = meson_map_resource(pc, gpio_np, "mux");
668		− if (IS_ERR(pc->reg_mux)) {
	668	+ if (IS_ERR_OR_NULL(pc->reg_mux)) {
669	669	dev_err(pc->dev, "mux registers not found\n");
670		− return PTR_ERR(pc->reg_mux);
	670	+ return pc->reg_mux ? PTR_ERR(pc->reg_mux) : -ENOENT;
671	671	}
672	672
673	673	pc->reg_gpio = meson_map_resource(pc, gpio_np, "gpio");
674		− if (IS_ERR(pc->reg_gpio)) {
	674	+ if (IS_ERR_OR_NULL(pc->reg_gpio)) {
675	675	dev_err(pc->dev, "gpio registers not found\n");
676		− return PTR_ERR(pc->reg_gpio);
	676	+ return pc->reg_gpio ? PTR_ERR(pc->reg_gpio) : -ENOENT;
677	677	}
678	678
679	679	pc->reg_pull = meson_map_resource(pc, gpio_np, "pull");
680		− /* Use gpio region if pull one is not present */
681	680	if (IS_ERR(pc->reg_pull))
682		− pc->reg_pull = pc->reg_gpio;
	681	+ pc->reg_pull = NULL;
683	682
684	683	pc->reg_pullen = meson_map_resource(pc, gpio_np, "pull-enable");
685		− /* Use pull region if pull-enable one is not present */
686	684	if (IS_ERR(pc->reg_pullen))
687		− pc->reg_pullen = pc->reg_pull;
	685	+ pc->reg_pullen = NULL;
688	686
689	687	pc->reg_ds = meson_map_resource(pc, gpio_np, "ds");
690	688	if (IS_ERR(pc->reg_ds)) {
@@ -692,6 +690,28 @@ static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc, · 1 unmodified line
692	690	pc->reg_ds = NULL;
693	691	}
694	692
	693	+ if (pc->data->parse_dt)
	694	+ return pc->data->parse_dt(pc);
	695	+
	696	+ return 0;
	697	+}
	698	+
	699	+int meson8_aobus_parse_dt_extra(struct meson_pinctrl *pc)
	700	+{
	701	+ if (!pc->reg_pull)
	702	+ return -EINVAL;
	703	+
	704	+ pc->reg_pullen = pc->reg_pull;
	705	+
	706	+ return 0;
	707	+}
	708	+
	709	+int meson_a1_parse_dt_extra(struct meson_pinctrl *pc)
	710	+{
	711	+ pc->reg_pull = pc->reg_gpio;
	712	+ pc->reg_pullen = pc->reg_gpio;
	713	+ pc->reg_ds = pc->reg_gpio;
	714	+
695	715	return 0;
696	716	}
697	717

drivers/pinctrl/meson/pinctrl-meson.h+7−0

@@ -11,6 +11,8 @@ · 10 unmodified lines
11	11	#include <linux/regmap.h>
12	12	#include <linux/types.h>
13	13
	14	+struct meson_pinctrl;
	15	+
14	16	/**
15	17	* struct meson_pmx_group - a pinmux group
16	18	*
@@ -114,6 +116,7 @@ struct meson_pinctrl_data { · 97 unmodified lines
114	116	unsigned int num_banks;
115	117	const struct pinmux_ops *pmx_ops;
116	118	void *pmx_data;
	119	+ int (parse_dt)(struct meson_pinctrl pc);
117	120	};
118	121
119	122	struct meson_pinctrl {
@@ -171,3 +174,7 @@ int meson_pmx_get_groups(struct pinctrl_dev *pcdev, · 51 unmodified lines
171	174
172	175	/* Common probe function */
173	176	int meson_pinctrl_probe(struct platform_device *pdev);
	177	+/* Common ao groups extra dt parse function for SoCs before g12a */
	178	+int meson8_aobus_parse_dt_extra(struct meson_pinctrl *pc);
	179	+/* Common extra dt parse function for SoCs like A1 */
	180	+int meson_a1_parse_dt_extra(struct meson_pinctrl *pc);

drivers/pinctrl/meson/pinctrl-meson8.c+1−0

@@ -1103,6 +1103,7 @@ static struct meson_pinctrl_data meson8_aobus_pinctrl_data = { · 1102 unmodified lines
1103	1103	.num_funcs = ARRAY_SIZE(meson8_aobus_functions),
1104	1104	.num_banks = ARRAY_SIZE(meson8_aobus_banks),
1105	1105	.pmx_ops = &meson8_pmx_ops,
	1106	+ .parse_dt = &meson8_aobus_parse_dt_extra,
1106	1107	};
1107	1108
1108	1109	static const struct of_device_id meson8_pinctrl_dt_match[] = {

drivers/pinctrl/meson/pinctrl-meson8b.c+1−0

@@ -962,6 +962,7 @@ static struct meson_pinctrl_data meson8b_aobus_pinctrl_data = { · 961 unmodified lines
962	962	.num_funcs = ARRAY_SIZE(meson8b_aobus_functions),
963	963	.num_banks = ARRAY_SIZE(meson8b_aobus_banks),
964	964	.pmx_ops = &meson8_pmx_ops,
	965	+ .parse_dt = &meson8_aobus_parse_dt_extra,
965	966	};
966	967
967	968	static const struct of_device_id meson8b_pinctrl_dt_match[] = {

drivers/pinctrl/mvebu/Kconfig+5−5

@@ -46,8 +46,8 @@ config PINCTRL_ORION · 45 unmodified lines
46	46	select PINCTRL_MVEBU
47	47
48	48	config PINCTRL_ARMADA_37XX
49		− bool
50		− select GENERIC_PINCONF
51		− select MFD_SYSCON
52		− select PINCONF
53		− select PINMUX
	49	+ bool
	50	+ select GENERIC_PINCONF
	51	+ select MFD_SYSCON
	52	+ select PINCONF
	53	+ select PINMUX

drivers/pinctrl/mvebu/pinctrl-armada-37xx.c+22−18

@@ -595,10 +595,10 @@ static int armada_37xx_irq_set_type(struct irq_data *d, unsigned int type) · 594 unmodified lines
595	595	regmap_read(info->regmap, in_reg, &in_val);
596	596
597	597	/* Set initial polarity based on current input level. */
598		− if (in_val & d->mask)
599		− val \|= d->mask; /* falling */
	598	+ if (in_val & BIT(d->hwirq % GPIO_PER_REG))
	599	+ val \|= BIT(d->hwirq % GPIO_PER_REG); /* falling */
600	600	else
601		− val &= ~d->mask; /* rising */
	601	+ val &= ~(BIT(d->hwirq % GPIO_PER_REG)); /* rising */
602	602	break;
603	603	}
604	604	default:
@@ -722,6 +722,8 @@ static int armada_37xx_irqchip_register(struct platform_device *pdev, · 117 unmodified lines
722	722	struct device_node *np = info->dev->of_node;
723	723	struct gpio_chip *gc = &info->gpio_chip;
724	724	struct irq_chip *irqchip = &info->irq_chip;
	725	+ struct gpio_irq_chip *girq = &gc->irq;
	726	+ struct device *dev = &pdev->dev;
725	727	struct resource res;
726	728	int ret = -ENODEV, i, nr_irq_parent;
727	729
@@ -732,19 +734,21 @@ static int armada_37xx_irqchip_register(struct platform_device *pdev, · 4 unmodified lines
732	734	break;
733	735	}
734	736	};
735		− if (ret)
	737	+ if (ret) {
	738	+ dev_err(dev, "no gpio-controller child node\n");
736	739	return ret;
	740	+ }
737	741
738	742	nr_irq_parent = of_irq_count(np);
739	743	spin_lock_init(&info->irq_lock);
740	744
741	745	if (!nr_irq_parent) {
742		− dev_err(&pdev->dev, "Invalid or no IRQ\n");
	746	+ dev_err(dev, "invalid or no IRQ\n");
743	747	return 0;
744	748	}
745	749
746	750	if (of_address_to_resource(info->dev->of_node, 1, &res)) {
747		− dev_err(info->dev, "cannot find IO resource\n");
	751	+ dev_err(dev, "cannot find IO resource\n");
748	752	return -ENOENT;
749	753	}
750	754
@@ -759,27 +763,27 @@ static int armada_37xx_irqchip_register(struct platform_device *pdev, · 8 unmodified lines
759	763	irqchip->irq_set_type = armada_37xx_irq_set_type;
760	764	irqchip->irq_startup = armada_37xx_irq_startup;
761	765	irqchip->name = info->data->name;
762		− ret = gpiochip_irqchip_add(gc, irqchip, 0,
763		− handle_edge_irq, IRQ_TYPE_NONE);
764		− if (ret) {
765		− dev_info(&pdev->dev, "could not add irqchip\n");
766		− return ret;
767		− }
768		−
	766	+ girq->chip = irqchip;
	767	+ girq->parent_handler = armada_37xx_irq_handler;
769	768	/*
770	769	* Many interrupts are connected to the parent interrupt
771	770	* controller. But we do not take advantage of this and use
772	771	* the chained irq with all of them.
773	772	*/
	773	+ girq->num_parents = nr_irq_parent;
	774	+ girq->parents = devm_kcalloc(&pdev->dev, nr_irq_parent,
	775	+ sizeof(*girq->parents), GFP_KERNEL);
	776	+ if (!girq->parents)
	777	+ return -ENOMEM;
774	778	for (i = 0; i < nr_irq_parent; i++) {
775	779	int irq = irq_of_parse_and_map(np, i);
776	780
777	781	if (irq < 0)
778	782	continue;
779		−
780		− gpiochip_set_chained_irqchip(gc, irqchip, irq,
781		− armada_37xx_irq_handler);
	783	+ girq->parents[i] = irq;
782	784	}
	785	+ girq->default_type = IRQ_TYPE_NONE;
	786	+ girq->handler = handle_edge_irq;
783	787
784	788	return 0;
785	789	}
@@ -809,10 +813,10 @@ static int armada_37xx_gpiochip_register(struct platform_device *pdev, · 23 unmodified lines
809	813	gc->of_node = np;
810	814	gc->label = info->data->name;
811	815
812		− ret = devm_gpiochip_add_data(&pdev->dev, gc, info);
	816	+ ret = armada_37xx_irqchip_register(pdev, info);
813	817	if (ret)
814	818	return ret;
815		− ret = armada_37xx_irqchip_register(pdev, info);
	819	+ ret = devm_gpiochip_add_data(&pdev->dev, gc, info);
816	820	if (ret)
817	821	return ret;
818	822

drivers/pinctrl/mvebu/pinctrl-mvebu.c+1−3

@@ -759,12 +759,10 @@ int mvebu_pinctrl_simple_mmio_probe(struct platform_device *pdev) · 758 unmodified lines
759	759	{
760	760	struct mvebu_pinctrl_soc_info *soc = dev_get_platdata(&pdev->dev);
761	761	struct mvebu_mpp_ctrl_data *mpp_data;
762		− struct resource *res;
763	762	void __iomem *base;
764	763	int i;
765	764
766		− res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
767		− base = devm_ioremap_resource(&pdev->dev, res);
	765	+ base = devm_platform_ioremap_resource(pdev, 0);
768	766	if (IS_ERR(base))
769	767	return PTR_ERR(base);
770	768

drivers/pinctrl/mvebu/pinctrl-orion.c+2−5

@@ -220,17 +220,14 @@ static int orion_pinctrl_probe(struct platform_device *pdev) · 219 unmodified lines
220	220	{
221	221	const struct of_device_id *match =
222	222	of_match_device(orion_pinctrl_of_match, &pdev->dev);
223		− struct resource *res;
224	223
225	224	pdev->dev.platform_data = (void*)match->data;
226	225
227		− res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
228		− mpp_base = devm_ioremap_resource(&pdev->dev, res);
	226	+ mpp_base = devm_platform_ioremap_resource(pdev, 0);
229	227	if (IS_ERR(mpp_base))
230	228	return PTR_ERR(mpp_base);
231	229
232		− res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
233		− high_mpp_base = devm_ioremap_resource(&pdev->dev, res);
	230	+ high_mpp_base = devm_platform_ioremap_resource(pdev, 1);
234	231	if (IS_ERR(high_mpp_base))
235	232	return PTR_ERR(high_mpp_base);
236	233

drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c+11−1

@@ -391,6 +391,15 @@ static const unsigned mc0_a_1_pins[] = { DB8500_PIN_AC2, /* MC0_CMDDIR */ · 390 unmodified lines
391	391	DB8500_PIN_AA2, /* MC0_DAT2 */
392	392	DB8500_PIN_AA1 /* MC0_DAT3 */
393	393	};
	394	+/* MMC/SD card 0 interface without CMD/DAT0/DAT2 direction control */
	395	+static const unsigned mc0_a_2_pins[] = { DB8500_PIN_AA3, /* MC0_FBCLK */
	396	+ DB8500_PIN_AA4, /* MC0_CLK */
	397	+ DB8500_PIN_AB2, /* MC0_CMD */
	398	+ DB8500_PIN_Y4, /* MC0_DAT0 */
	399	+ DB8500_PIN_Y2, /* MC0_DAT1 */
	400	+ DB8500_PIN_AA2, /* MC0_DAT2 */
	401	+ DB8500_PIN_AA1 /* MC0_DAT3 */
	402	+};
394	403	/* Often only 4 bits are used, then these are not needed (only used for MMC) */
395	404	static const unsigned mc0_dat47_a_1_pins[] = { DB8500_PIN_W2, /* MC0_DAT4 */
396	405	DB8500_PIN_W3, /* MC0_DAT5 */
@@ -670,6 +679,7 @@ static const struct nmk_pingroup nmk_db8500_groups[] = { · 273 unmodified lines
670	679	DB8500_PIN_GROUP(msp0tfstck_a_1, NMK_GPIO_ALT_A),
671	680	DB8500_PIN_GROUP(msp0rfsrck_a_1, NMK_GPIO_ALT_A),
672	681	DB8500_PIN_GROUP(mc0_a_1, NMK_GPIO_ALT_A),
	682	+ DB8500_PIN_GROUP(mc0_a_2, NMK_GPIO_ALT_A),
673	683	DB8500_PIN_GROUP(mc0_dat47_a_1, NMK_GPIO_ALT_A),
674	684	DB8500_PIN_GROUP(mc0dat31dir_a_1, NMK_GPIO_ALT_A),
675	685	DB8500_PIN_GROUP(msp1txrx_a_1, NMK_GPIO_ALT_A),
@@ -828,7 +838,7 @@ DB8500_FUNC_GROUPS(ipi2c, "ipi2c_a_1", "ipi2c_a_2"); · 152 unmodified lines
828	838	*/
829	839	DB8500_FUNC_GROUPS(msp0, "msp0txrx_a_1", "msp0tfstck_a_1", "msp0rfstck_a_1",
830	840	"msp0txrx_b_1", "msp0sck_b_1");
831		−DB8500_FUNC_GROUPS(mc0, "mc0_a_1", "mc0_dat47_a_1", "mc0dat31dir_a_1");
	841	+DB8500_FUNC_GROUPS(mc0, "mc0_a_1", "mc0_a_2", "mc0_dat47_a_1", "mc0dat31dir_a_1");
832	842	/* MSP0 can swap RX/TX like MSP0 but has no SCK pin available */
833	843	DB8500_FUNC_GROUPS(msp1, "msp1txrx_a_1", "msp1_a_1", "msp1txrx_b_1");
834	844	DB8500_FUNC_GROUPS(lcdb, "lcdb_a_1");

drivers/pinctrl/nomadik/pinctrl-nomadik.c+22−59

@@ -248,9 +248,6 @@ struct nmk_gpio_chip { · 247 unmodified lines
248	248	void __iomem *addr;
249	249	struct clk *clk;
250	250	unsigned int bank;
251		− unsigned int parent_irq;
252		− int latent_parent_irq;
253		− u32 (*get_latent_status)(unsigned int bank);
254	251	void (*set_ioforce)(bool enable);
255	252	spinlock_t lock;
256	253	bool sleepmode;
@@ -802,13 +799,19 @@ static void nmk_gpio_irq_shutdown(struct irq_data *d) · 545 unmodified lines
802	799	clk_disable(nmk_chip->clk);
803	800	}
804	801
805		−static void __nmk_gpio_irq_handler(struct irq_desc *desc, u32 status)
	802	+static void nmk_gpio_irq_handler(struct irq_desc *desc)
806	803	{
807	804	struct irq_chip *host_chip = irq_desc_get_chip(desc);
808	805	struct gpio_chip *chip = irq_desc_get_handler_data(desc);
	806	+ struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
	807	+ u32 status;
809	808
810	809	chained_irq_enter(host_chip, desc);
811	810
	811	+ clk_enable(nmk_chip->clk);
	812	+ status = readl(nmk_chip->addr + NMK_GPIO_IS);
	813	+ clk_disable(nmk_chip->clk);
	814	+
812	815	while (status) {
813	816	int bit = __ffs(status);
814	817
@@ -819,28 +822,6 @@ static void __nmk_gpio_irq_handler(struct irq_desc *desc, u32 status) · 4 unmodified lines
819	822	chained_irq_exit(host_chip, desc);
820	823	}
821	824
822		−static void nmk_gpio_irq_handler(struct irq_desc *desc)
823		−{
824		− struct gpio_chip *chip = irq_desc_get_handler_data(desc);
825		− struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
826		− u32 status;
827		−
828		− clk_enable(nmk_chip->clk);
829		− status = readl(nmk_chip->addr + NMK_GPIO_IS);
830		− clk_disable(nmk_chip->clk);
831		−
832		− __nmk_gpio_irq_handler(desc, status);
833		−}
834		−
835		−static void nmk_gpio_latent_irq_handler(struct irq_desc *desc)
836		−{
837		− struct gpio_chip *chip = irq_desc_get_handler_data(desc);
838		− struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
839		− u32 status = nmk_chip->get_latent_status(nmk_chip->bank);
840		−
841		− __nmk_gpio_irq_handler(desc, status);
842		−}
843		−
844	825	/* I/O Functions */
845	826
846	827	static int nmk_gpio_get_dir(struct gpio_chip *chip, unsigned offset)
@@ -1103,8 +1084,8 @@ static int nmk_gpio_probe(struct platform_device *dev) · 256 unmodified lines
1103	1084	struct device_node *np = dev->dev.of_node;
1104	1085	struct nmk_gpio_chip *nmk_chip;
1105	1086	struct gpio_chip *chip;
	1087	+ struct gpio_irq_chip *girq;
1106	1088	struct irq_chip *irqchip;
1107		− int latent_irq;
1108	1089	bool supports_sleepmode;
1109	1090	int irq;
1110	1091	int ret;
@@ -1125,15 +1106,10 @@ static int nmk_gpio_probe(struct platform_device *dev) · 14 unmodified lines
1125	1106	if (irq < 0)
1126	1107	return irq;
1127	1108
1128		− /* It's OK for this IRQ not to be present */
1129		− latent_irq = platform_get_irq(dev, 1);
1130		−
1131	1109	/*
1132	1110	* The virt address in nmk_chip->addr is in the nomadik register space,
1133	1111	* so we can simply convert the resource address, without remapping
1134	1112	*/
1135		− nmk_chip->parent_irq = irq;
1136		− nmk_chip->latent_parent_irq = latent_irq;
1137	1113	nmk_chip->sleepmode = supports_sleepmode;
1138	1114	spin_lock_init(&nmk_chip->lock);
1139	1115
@@ -1163,6 +1139,19 @@ static int nmk_gpio_probe(struct platform_device *dev) · 23 unmodified lines
1163	1139	chip->base,
1164	1140	chip->base + chip->ngpio - 1);
1165	1141
	1142	+ girq = &chip->irq;
	1143	+ girq->chip = irqchip;
	1144	+ girq->parent_handler = nmk_gpio_irq_handler;
	1145	+ girq->num_parents = 1;
	1146	+ girq->parents = devm_kcalloc(&dev->dev, 1,
	1147	+ sizeof(*girq->parents),
	1148	+ GFP_KERNEL);
	1149	+ if (!girq->parents)
	1150	+ return -ENOMEM;
	1151	+ girq->parents[0] = irq;
	1152	+ girq->default_type = IRQ_TYPE_NONE;
	1153	+ girq->handler = handle_edge_irq;
	1154	+
1166	1155	clk_enable(nmk_chip->clk);
1167	1156	nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
1168	1157	clk_disable(nmk_chip->clk);
@@ -1174,33 +1163,7 @@ static int nmk_gpio_probe(struct platform_device *dev) · 5 unmodified lines
1174	1163
1175	1164	platform_set_drvdata(dev, nmk_chip);
1176	1165
1177		− /*
1178		− * Let the generic code handle this edge IRQ, the the chained
1179		− * handler will perform the actual work of handling the parent
1180		− * interrupt.
1181		− */
1182		− ret = gpiochip_irqchip_add(chip,
1183		− irqchip,
1184		− 0,
1185		− handle_edge_irq,
1186		− IRQ_TYPE_NONE);
1187		− if (ret) {
1188		− dev_err(&dev->dev, "could not add irqchip\n");
1189		− gpiochip_remove(&nmk_chip->chip);
1190		− return -ENODEV;
1191		− }
1192		− /* Then register the chain on the parent IRQ */
1193		− gpiochip_set_chained_irqchip(chip,
1194		− irqchip,
1195		− nmk_chip->parent_irq,
1196		− nmk_gpio_irq_handler);
1197		− if (nmk_chip->latent_parent_irq > 0)
1198		− gpiochip_set_chained_irqchip(chip,
1199		− irqchip,
1200		− nmk_chip->latent_parent_irq,
1201		− nmk_gpio_latent_irq_handler);
1202		−
1203		− dev_info(&dev->dev, "at address %p\n", nmk_chip->addr);
	1166	+ dev_info(&dev->dev, "chip registered\n");
1204	1167
1205	1168	return 0;
1206	1169	}

drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c+16−16

@@ -1954,6 +1954,22 @@ static int npcm7xx_gpio_register(struct npcm7xx_pinctrl *pctrl) · 1953 unmodified lines
1954	1954	int ret, id;
1955	1955
1956	1956	for (id = 0 ; id < pctrl->bank_num ; id++) {
	1957	+ struct gpio_irq_chip *girq;
	1958	+
	1959	+ girq = &pctrl->gpio_bank[id].gc.irq;
	1960	+ girq->chip = &pctrl->gpio_bank[id].irq_chip;
	1961	+ girq->parent_handler = npcmgpio_irq_handler;
	1962	+ girq->num_parents = 1;
	1963	+ girq->parents = devm_kcalloc(pctrl->dev, 1,
	1964	+ sizeof(*girq->parents),
	1965	+ GFP_KERNEL);
	1966	+ if (!girq->parents) {
	1967	+ ret = -ENOMEM;
	1968	+ goto err_register;
	1969	+ }
	1970	+ girq->parents[0] = pctrl->gpio_bank[id].irq;
	1971	+ girq->default_type = IRQ_TYPE_NONE;
	1972	+ girq->handler = handle_level_irq;
1957	1973	ret = devm_gpiochip_add_data(pctrl->dev,
1958	1974	&pctrl->gpio_bank[id].gc,
1959	1975	&pctrl->gpio_bank[id]);
@@ -1972,22 +1988,6 @@ static int npcm7xx_gpio_register(struct npcm7xx_pinctrl *pctrl) · 12 unmodified lines
1972	1988	gpiochip_remove(&pctrl->gpio_bank[id].gc);
1973	1989	goto err_register;
1974	1990	}
1975		−
1976		− ret = gpiochip_irqchip_add(&pctrl->gpio_bank[id].gc,
1977		− &pctrl->gpio_bank[id].irq_chip,
1978		− 0, handle_level_irq,
1979		− IRQ_TYPE_NONE);
1980		− if (ret < 0) {
1981		− dev_err(pctrl->dev,
1982		− "Failed to add IRQ chip %u\n", id);
1983		− gpiochip_remove(&pctrl->gpio_bank[id].gc);
1984		− goto err_register;
1985		− }
1986		−
1987		− gpiochip_set_chained_irqchip(&pctrl->gpio_bank[id].gc,
1988		− &pctrl->gpio_bank[id].irq_chip,
1989		− pctrl->gpio_bank[id].irq,
1990		− npcmgpio_irq_handler);
1991	1991	}
1992	1992
1993	1993	return 0;

drivers/pinctrl/pinctrl-amd.c+2−1

@@ -540,7 +540,8 @@ static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id) · 539 unmodified lines
540	540	irqreturn_t ret = IRQ_NONE;
541	541	unsigned int i, irqnr;
542	542	unsigned long flags;
543		− u32 *regs, regval;
	543	+ u32 __iomem *regs;
	544	+ u32 regval;
544	545	u64 status, mask;
545	546
546	547	/* Read the wake status */

drivers/pinctrl/pinctrl-artpec6.c+1−3

@@ -936,7 +936,6 @@ static void artpec6_pmx_reset(struct artpec6_pmx *pmx) · 935 unmodified lines
936	936	static int artpec6_pmx_probe(struct platform_device *pdev)
937	937	{
938	938	struct artpec6_pmx *pmx;
939		− struct resource *res;
940	939
941	940	pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
942	941	if (!pmx)
@@ -944,8 +943,7 @@ static int artpec6_pmx_probe(struct platform_device *pdev) · 1 unmodified line
944	943
945	944	pmx->dev = &pdev->dev;
946	945
947		− res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
948		− pmx->base = devm_ioremap_resource(&pdev->dev, res);
	946	+ pmx->base = devm_platform_ioremap_resource(pdev, 0);
949	947
950	948	if (IS_ERR(pmx->base))
951	949	return PTR_ERR(pmx->base);

drivers/pinctrl/pinctrl-at91-pio4.c+63−2

@@ -328,6 +328,33 @@ static int atmel_gpio_get(struct gpio_chip *chip, unsigned offset) · 327 unmodified lines
328	328	return !!(reg & BIT(pin->line));
329	329	}
330	330
	331	+static int atmel_gpio_get_multiple(struct gpio_chip chip, unsigned long mask,
	332	+ unsigned long *bits)
	333	+{
	334	+ struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
	335	+ unsigned int bank;
	336	+
	337	+ bitmap_zero(bits, atmel_pioctrl->npins);
	338	+
	339	+ for (bank = 0; bank < atmel_pioctrl->nbanks; bank++) {
	340	+ unsigned int word = bank;
	341	+ unsigned int offset = 0;
	342	+ unsigned int reg;
	343	+
	344	+#if ATMEL_PIO_NPINS_PER_BANK != BITS_PER_LONG
	345	+ word = BIT_WORD(bank * ATMEL_PIO_NPINS_PER_BANK);
	346	+ offset = bank * ATMEL_PIO_NPINS_PER_BANK % BITS_PER_LONG;
	347	+#endif
	348	+ if (!mask[word])
	349	+ continue;
	350	+
	351	+ reg = atmel_gpio_read(atmel_pioctrl, bank, ATMEL_PIO_PDSR);
	352	+ bits[word] \|= mask[word] & (reg << offset);
	353	+ }
	354	+
	355	+ return 0;
	356	+}
	357	+
331	358	static int atmel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
332	359	int value)
333	360	{
@@ -358,11 +385,46 @@ static void atmel_gpio_set(struct gpio_chip *chip, unsigned offset, int val) · 24 unmodified lines
358	385	BIT(pin->line));
359	386	}
360	387
	388	+static void atmel_gpio_set_multiple(struct gpio_chip chip, unsigned long mask,
	389	+ unsigned long *bits)
	390	+{
	391	+ struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
	392	+ unsigned int bank;
	393	+
	394	+ for (bank = 0; bank < atmel_pioctrl->nbanks; bank++) {
	395	+ unsigned int bitmask;
	396	+ unsigned int word = bank;
	397	+
	398	+/*
	399	+ * On a 64-bit platform, BITS_PER_LONG is 64 so it is necessary to iterate over
	400	+ * two 32bit words to handle the whole bitmask
	401	+ */
	402	+#if ATMEL_PIO_NPINS_PER_BANK != BITS_PER_LONG
	403	+ word = BIT_WORD(bank * ATMEL_PIO_NPINS_PER_BANK);
	404	+#endif
	405	+ if (!mask[word])
	406	+ continue;
	407	+
	408	+ bitmask = mask[word] & bits[word];
	409	+ atmel_gpio_write(atmel_pioctrl, bank, ATMEL_PIO_SODR, bitmask);
	410	+
	411	+ bitmask = mask[word] & ~bits[word];
	412	+ atmel_gpio_write(atmel_pioctrl, bank, ATMEL_PIO_CODR, bitmask);
	413	+
	414	+#if ATMEL_PIO_NPINS_PER_BANK != BITS_PER_LONG
	415	+ mask[word] >>= ATMEL_PIO_NPINS_PER_BANK;
	416	+ bits[word] >>= ATMEL_PIO_NPINS_PER_BANK;
	417	+#endif
	418	+ }
	419	+}
	420	+
361	421	static struct gpio_chip atmel_gpio_chip = {
362	422	.direction_input = atmel_gpio_direction_input,
363	423	.get = atmel_gpio_get,
	424	+ .get_multiple = atmel_gpio_get_multiple,
364	425	.direction_output = atmel_gpio_direction_output,
365	426	.set = atmel_gpio_set,
	427	+ .set_multiple = atmel_gpio_set_multiple,
366	428	.to_irq = atmel_gpio_to_irq,
367	429	.base = 0,
368	430	};
@@ -955,8 +1017,7 @@ static int atmel_pinctrl_probe(struct platform_device *pdev) · 586 unmodified lines
955	1017	atmel_pioctrl->nbanks = atmel_pioctrl_data->nbanks;
956	1018	atmel_pioctrl->npins = atmel_pioctrl->nbanks * ATMEL_PIO_NPINS_PER_BANK;
957	1019
958		− res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
959		− atmel_pioctrl->reg_base = devm_ioremap_resource(dev, res);
	1020	+ atmel_pioctrl->reg_base = devm_platform_ioremap_resource(pdev, 0);
960	1021	if (IS_ERR(atmel_pioctrl->reg_base))
961	1022	return -EINVAL;
962	1023

drivers/pinctrl/pinctrl-at91.c+25−30

@@ -85,8 +85,8 @@ enum drive_strength_bit { · 84 unmodified lines
85	85	DRIVE_STRENGTH_SHIFT)
86	86
87	87	enum slewrate_bit {
88		− SLEWRATE_BIT_DIS,
89	88	SLEWRATE_BIT_ENA,
	89	+ SLEWRATE_BIT_DIS,
90	90	};
91	91
92	92	#define SLEWRATE_BIT_MSK(name) (SLEWRATE_BIT_##name << SLEWRATE_SHIFT)
@@ -669,7 +669,7 @@ static void at91_mux_sam9x60_set_slewrate(void __iomem *pio, unsigned pin, · 576 unmodified lines
669	669	{
670	670	unsigned int tmp;
671	671
672		− if (setting < SLEWRATE_BIT_DIS \|\| setting > SLEWRATE_BIT_ENA)
	672	+ if (setting < SLEWRATE_BIT_ENA \|\| setting > SLEWRATE_BIT_DIS)
673	673	return;
674	674
675	675	tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR);
@@ -1723,9 +1723,11 @@ static int at91_gpio_of_irq_setup(struct platform_device *pdev, · 1047 unmodified lines
1723	1723	struct at91_gpio_chip *prev = NULL;
1724	1724	struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq);
1725	1725	struct irq_chip *gpio_irqchip;
1726		− int ret, i;
	1726	+ struct gpio_irq_chip *girq;
	1727	+ int i;
1727	1728
1728		− gpio_irqchip = devm_kzalloc(&pdev->dev, sizeof(*gpio_irqchip), GFP_KERNEL);
	1729	+ gpio_irqchip = devm_kzalloc(&pdev->dev, sizeof(*gpio_irqchip),
	1730	+ GFP_KERNEL);
1729	1731	if (!gpio_irqchip)
1730	1732	return -ENOMEM;
1731	1733
@@ -1747,33 +1749,30 @@ static int at91_gpio_of_irq_setup(struct platform_device *pdev, · 15 unmodified lines
1747	1749	* handler will perform the actual work of handling the parent
1748	1750	* interrupt.
1749	1751	*/
1750		− ret = gpiochip_irqchip_add(&at91_gpio->chip,
1751		− gpio_irqchip,
1752		− 0,
1753		− handle_edge_irq,
1754		− IRQ_TYPE_NONE);
1755		− if (ret) {
1756		− dev_err(&pdev->dev, "at91_gpio.%d: Couldn't add irqchip to gpiochip.\n",
1757		− at91_gpio->pioc_idx);
1758		− return ret;
1759		− }
	1752	+ girq = &at91_gpio->chip.irq;
	1753	+ girq->chip = gpio_irqchip;
	1754	+ girq->default_type = IRQ_TYPE_NONE;
	1755	+ girq->handler = handle_edge_irq;
1760	1756
1761		− /* The top level handler handles one bank of GPIOs, except
	1757	+ /*
	1758	+ * The top level handler handles one bank of GPIOs, except
1762	1759	* on some SoC it can handle up to three...
1763	1760	* We only set up the handler for the first of the list.
1764	1761	*/
1765	1762	gpiochip_prev = irq_get_handler_data(at91_gpio->pioc_virq);
1766	1763	if (!gpiochip_prev) {
1767		− /* Then register the chain on the parent IRQ */
1768		− gpiochip_set_chained_irqchip(&at91_gpio->chip,
1769		− gpio_irqchip,
1770		− at91_gpio->pioc_virq,
1771		− gpio_irq_handler);
	1764	+ girq->parent_handler = gpio_irq_handler;
	1765	+ girq->num_parents = 1;
	1766	+ girq->parents = devm_kcalloc(&pdev->dev, 1,
	1767	+ sizeof(*girq->parents),
	1768	+ GFP_KERNEL);
	1769	+ if (!girq->parents)
	1770	+ return -ENOMEM;
	1771	+ girq->parents[0] = at91_gpio->pioc_virq;
1772	1772	return 0;
1773	1773	}
1774	1774
1775	1775	prev = gpiochip_get_data(gpiochip_prev);
1776		−
1777	1776	/* we can only have 2 banks before */
1778	1777	for (i = 0; i < 2; i++) {
1779	1778	if (prev->next) {
@@ -1812,7 +1811,6 @@ static const struct of_device_id at91_gpio_of_match[] = { · 32 unmodified lines
1812	1811	static int at91_gpio_probe(struct platform_device *pdev)
1813	1812	{
1814	1813	struct device_node *np = pdev->dev.of_node;
1815		− struct resource *res;
1816	1814	struct at91_gpio_chip *at91_chip = NULL;
1817	1815	struct gpio_chip *chip;
1818	1816	struct pinctrl_gpio_range *range;
@@ -1840,8 +1838,7 @@ static int at91_gpio_probe(struct platform_device *pdev) · 21 unmodified lines
1840	1838	goto err;
1841	1839	}
1842	1840
1843		− res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1844		− at91_chip->regbase = devm_ioremap_resource(&pdev->dev, res);
	1841	+ at91_chip->regbase = devm_platform_ioremap_resource(pdev, 0);
1845	1842	if (IS_ERR(at91_chip->regbase)) {
1846	1843	ret = PTR_ERR(at91_chip->regbase);
1847	1844	goto err;
@@ -1903,6 +1900,10 @@ static int at91_gpio_probe(struct platform_device *pdev) · 55 unmodified lines
1903	1900	range->npins = chip->ngpio;
1904	1901	range->gc = chip;
1905	1902
	1903	+ ret = at91_gpio_of_irq_setup(pdev, at91_chip);
	1904	+ if (ret)
	1905	+ goto gpiochip_add_err;
	1906	+
1906	1907	ret = gpiochip_add_data(chip, at91_chip);
1907	1908	if (ret)
1908	1909	goto gpiochip_add_err;
@@ -1910,16 +1911,10 @@ static int at91_gpio_probe(struct platform_device *pdev) · 1 unmodified line
1910	1911	gpio_chips[alias_idx] = at91_chip;
1911	1912	gpio_banks = max(gpio_banks, alias_idx + 1);
1912	1913
1913		− ret = at91_gpio_of_irq_setup(pdev, at91_chip);
1914		− if (ret)
1915		− goto irq_setup_err;
1916		−
1917	1914	dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase);
1918	1915
1919	1916	return 0;
1920	1917
1921		−irq_setup_err:
1922		− gpiochip_remove(chip);
1923	1918	gpiochip_add_err:
1924	1919	clk_enable_err:
1925	1920	clk_disable_unprepare(at91_chip->clock);

drivers/pinctrl/pinctrl-bm1880.c+1−3

@@ -1308,15 +1308,13 @@ static struct pinctrl_desc bm1880_desc = { · 1307 unmodified lines
1308	1308	static int bm1880_pinctrl_probe(struct platform_device *pdev)
1309	1309
1310	1310	{
1311		− struct resource *res;
1312	1311	struct bm1880_pinctrl *pctrl;
1313	1312
1314	1313	pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1315	1314	if (!pctrl)
1316	1315	return -ENOMEM;
1317	1316
1318		− res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1319		− pctrl->base = devm_ioremap_resource(&pdev->dev, res);
	1317	+ pctrl->base = devm_platform_ioremap_resource(pdev, 0);
1320	1318	if (IS_ERR(pctrl->base))
1321	1319	return PTR_ERR(pctrl->base);
1322	1320

drivers/pinctrl/pinctrl-coh901.c+24−30

@@ -615,7 +615,7 @@ static struct coh901_pinpair coh901_pintable[] = { · 614 unmodified lines
615	615	static int __init u300_gpio_probe(struct platform_device *pdev)
616	616	{
617	617	struct u300_gpio *gpio;
618		− struct resource *memres;
	618	+ struct gpio_irq_chip *girq;
619	619	int err = 0;
620	620	int portno;
621	621	u32 val;
@@ -632,8 +632,7 @@ static int __init u300_gpio_probe(struct platform_device *pdev) · 10 unmodified lines
632	632	gpio->chip.base = 0;
633	633	gpio->dev = &pdev->dev;
634	634
635		− memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
636		− gpio->base = devm_ioremap_resource(&pdev->dev, memres);
	635	+ gpio->base = devm_platform_ioremap_resource(pdev, 0);
637	636	if (IS_ERR(gpio->base))
638	637	return PTR_ERR(gpio->base);
639	638
@@ -672,26 +671,17 @@ static int __init u300_gpio_probe(struct platform_device *pdev) · 32 unmodified lines
672	671	gpio->base + U300_GPIO_CR);
673	672	u300_gpio_init_coh901571(gpio);
674	673
675		−#ifdef CONFIG_OF_GPIO
676		− gpio->chip.of_node = pdev->dev.of_node;
677		−#endif
678		− err = gpiochip_add_data(&gpio->chip, gpio);
679		− if (err) {
680		− dev_err(gpio->dev, "unable to add gpiochip: %d\n", err);
681		− goto err_no_chip;
682		− }
683		−
684		− err = gpiochip_irqchip_add(&gpio->chip,
685		− &u300_gpio_irqchip,
686		− 0,
687		− handle_simple_irq,
688		− IRQ_TYPE_EDGE_FALLING);
689		− if (err) {
690		− dev_err(gpio->dev, "no GPIO irqchip\n");
691		− goto err_no_irqchip;
	674	+ girq = &gpio->chip.irq;
	675	+ girq->chip = &u300_gpio_irqchip;
	676	+ girq->parent_handler = u300_gpio_irq_handler;
	677	+ girq->num_parents = U300_GPIO_NUM_PORTS;
	678	+ girq->parents = devm_kcalloc(gpio->dev, U300_GPIO_NUM_PORTS,
	679	+ sizeof(*girq->parents),
	680	+ GFP_KERNEL);
	681	+ if (!girq->parents) {
	682	+ err = -ENOMEM;
	683	+ goto err_dis_clk;
692	684	}
693		−
694		− /* Add each port with its IRQ separately */
695	685	for (portno = 0 ; portno < U300_GPIO_NUM_PORTS; portno++) {
696	686	struct u300_gpio_port *port = &gpio->ports[portno];
697	687
@@ -700,16 +690,21 @@ static int __init u300_gpio_probe(struct platform_device *pdev) · 2 unmodified lines
700	690	port->gpio = gpio;
701	691
702	692	port->irq = platform_get_irq(pdev, portno);
703		−
704		− gpiochip_set_chained_irqchip(&gpio->chip,
705		− &u300_gpio_irqchip,
706		− port->irq,
707		− u300_gpio_irq_handler);
	693	+ girq->parents[portno] = port->irq;
708	694
709	695	/* Turns off irq force (test register) for this port */
710	696	writel(0x0, gpio->base + portno * gpio->stride + ifr);
711	697	}
712		− dev_dbg(gpio->dev, "initialized %d GPIO ports\n", portno);
	698	+ girq->default_type = IRQ_TYPE_EDGE_FALLING;
	699	+ girq->handler = handle_simple_irq;
	700	+#ifdef CONFIG_OF_GPIO
	701	+ gpio->chip.of_node = pdev->dev.of_node;
	702	+#endif
	703	+ err = gpiochip_add_data(&gpio->chip, gpio);
	704	+ if (err) {
	705	+ dev_err(gpio->dev, "unable to add gpiochip: %d\n", err);
	706	+ goto err_dis_clk;
	707	+ }
713	708
714	709	/*
715	710	* Add pinctrl pin ranges, the pin controller must be registered
@@ -729,9 +724,8 @@ static int __init u300_gpio_probe(struct platform_device *pdev) · 13 unmodified lines
729	724	return 0;
730	725
731	726	err_no_range:
732		−err_no_irqchip:
733	727	gpiochip_remove(&gpio->chip);
734		−err_no_chip:
	728	+err_dis_clk:
735	729	clk_disable_unprepare(gpio->clk);
736	730	dev_err(&pdev->dev, "module ERROR:%d\n", err);
737	731	return err;

drivers/pinctrl/pinctrl-da850-pupd.c+1−3

@@ -146,14 +146,12 @@ static int da850_pupd_probe(struct platform_device *pdev) · 145 unmodified lines
146	146	{
147	147	struct device *dev = &pdev->dev;
148	148	struct da850_pupd_data *data;
149		− struct resource *res;
150	149
151	150	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
152	151	if (!data)
153	152	return -ENOMEM;
154	153
155		− res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
156		− data->base = devm_ioremap_resource(dev, res);
	154	+ data->base = devm_platform_ioremap_resource(pdev, 0);
157	155	if (IS_ERR(data->base)) {
158	156	dev_err(dev, "Could not map resource\n");
159	157	return PTR_ERR(data->base);

drivers/pinctrl/pinctrl-digicolor.c+1−3

@@ -270,7 +270,6 @@ static int dc_gpiochip_add(struct dc_pinmap pmap, struct device_node np) · 269 unmodified lines
270	270	static int dc_pinctrl_probe(struct platform_device *pdev)
271	271	{
272	272	struct dc_pinmap *pmap;
273		− struct resource *r;
274	273	struct pinctrl_pin_desc *pins;
275	274	struct pinctrl_desc *pctl_desc;
276	275	char *pin_names;
@@ -281,8 +280,7 @@ static int dc_pinctrl_probe(struct platform_device *pdev) · 4 unmodified lines
281	280	if (!pmap)
282	281	return -ENOMEM;
283	282
284		− r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
285		− pmap->regs = devm_ioremap_resource(&pdev->dev, r);
	283	+ pmap->regs = devm_platform_ioremap_resource(pdev, 0);
286	284	if (IS_ERR(pmap->regs))
287	285	return PTR_ERR(pmap->regs);
288	286

drivers/pinctrl/pinctrl-equilibrium.c+944−0

@@ -0,0 +1,944 @@
	1	+// SPDX-License-Identifier: GPL-2.0
	2	+/* Copyright (C) 2019 Intel Corporation */
	3	+
	4	+#include <linux/gpio/driver.h>
	5	+#include <linux/module.h>
	6	+#include <linux/of.h>
	7	+#include <linux/of_address.h>
	8	+#include <linux/of_irq.h>
	9	+#include <linux/pinctrl/pinctrl.h>
	10	+#include <linux/pinctrl/pinconf.h>
	11	+#include <linux/pinctrl/pinconf-generic.h>
	12	+#include <linux/pinctrl/pinmux.h>
	13	+#include <linux/platform_device.h>
	14	+
	15	+#include "core.h"
	16	+#include "pinconf.h"
	17	+#include "pinmux.h"
	18	+#include "pinctrl-equilibrium.h"
	19	+
	20	+#define PIN_NAME_FMT "io-%d"
	21	+#define PIN_NAME_LEN 10
	22	+#define PAD_REG_OFF 0x100
	23	+
	24	+static void eqbr_gpio_disable_irq(struct irq_data *d)
	25	+{
	26	+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	27	+ struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc);
	28	+ unsigned int offset = irqd_to_hwirq(d);
	29	+ unsigned long flags;
	30	+
	31	+ raw_spin_lock_irqsave(&gctrl->lock, flags);
	32	+ writel(BIT(offset), gctrl->membase + GPIO_IRNENCLR);
	33	+ raw_spin_unlock_irqrestore(&gctrl->lock, flags);
	34	+}
	35	+
	36	+static void eqbr_gpio_enable_irq(struct irq_data *d)
	37	+{
	38	+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	39	+ struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc);
	40	+ unsigned int offset = irqd_to_hwirq(d);
	41	+ unsigned long flags;
	42	+
	43	+ gc->direction_input(gc, offset);
	44	+ raw_spin_lock_irqsave(&gctrl->lock, flags);
	45	+ writel(BIT(offset), gctrl->membase + GPIO_IRNRNSET);
	46	+ raw_spin_unlock_irqrestore(&gctrl->lock, flags);
	47	+}
	48	+
	49	+static void eqbr_gpio_ack_irq(struct irq_data *d)
	50	+{
	51	+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	52	+ struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc);
	53	+ unsigned int offset = irqd_to_hwirq(d);
	54	+ unsigned long flags;
	55	+
	56	+ raw_spin_lock_irqsave(&gctrl->lock, flags);
	57	+ writel(BIT(offset), gctrl->membase + GPIO_IRNCR);
	58	+ raw_spin_unlock_irqrestore(&gctrl->lock, flags);
	59	+}
	60	+
	61	+static void eqbr_gpio_mask_ack_irq(struct irq_data *d)
	62	+{
	63	+ eqbr_gpio_disable_irq(d);
	64	+ eqbr_gpio_ack_irq(d);
	65	+}
	66	+
	67	+static inline void eqbr_cfg_bit(void __iomem *addr,
	68	+ unsigned int offset, unsigned int set)
	69	+{
	70	+ if (set)
	71	+ writel(readl(addr) \| BIT(offset), addr);
	72	+ else
	73	+ writel(readl(addr) & ~BIT(offset), addr);
	74	+}
	75	+
	76	+static int eqbr_irq_type_cfg(struct gpio_irq_type *type,
	77	+ struct eqbr_gpio_ctrl *gctrl,
	78	+ unsigned int offset)
	79	+{
	80	+ unsigned long flags;
	81	+
	82	+ raw_spin_lock_irqsave(&gctrl->lock, flags);
	83	+ eqbr_cfg_bit(gctrl->membase + GPIO_IRNCFG, offset, type->trig_type);
	84	+ eqbr_cfg_bit(gctrl->membase + GPIO_EXINTCR1, offset, type->trig_type);
	85	+ eqbr_cfg_bit(gctrl->membase + GPIO_EXINTCR0, offset, type->logic_type);
	86	+ raw_spin_unlock_irqrestore(&gctrl->lock, flags);
	87	+
	88	+ return 0;
	89	+}
	90	+
	91	+static int eqbr_gpio_set_irq_type(struct irq_data *d, unsigned int type)
	92	+{
	93	+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	94	+ struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc);
	95	+ unsigned int offset = irqd_to_hwirq(d);
	96	+ struct gpio_irq_type it;
	97	+
	98	+ memset(&it, 0, sizeof(it));
	99	+
	100	+ if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_NONE)
	101	+ return 0;
	102	+
	103	+ switch (type) {
	104	+ case IRQ_TYPE_EDGE_RISING:
	105	+ it.trig_type = GPIO_EDGE_TRIG;
	106	+ it.edge_type = GPIO_SINGLE_EDGE;
	107	+ it.logic_type = GPIO_POSITIVE_TRIG;
	108	+ break;
	109	+
	110	+ case IRQ_TYPE_EDGE_FALLING:
	111	+ it.trig_type = GPIO_EDGE_TRIG;
	112	+ it.edge_type = GPIO_SINGLE_EDGE;
	113	+ it.logic_type = GPIO_NEGATIVE_TRIG;
	114	+ break;
	115	+
	116	+ case IRQ_TYPE_EDGE_BOTH:
	117	+ it.trig_type = GPIO_EDGE_TRIG;
	118	+ it.edge_type = GPIO_BOTH_EDGE;
	119	+ it.logic_type = GPIO_POSITIVE_TRIG;
	120	+ break;
	121	+
	122	+ case IRQ_TYPE_LEVEL_HIGH:
	123	+ it.trig_type = GPIO_LEVEL_TRIG;
	124	+ it.edge_type = GPIO_SINGLE_EDGE;
	125	+ it.logic_type = GPIO_POSITIVE_TRIG;
	126	+ break;
	127	+
	128	+ case IRQ_TYPE_LEVEL_LOW:
	129	+ it.trig_type = GPIO_LEVEL_TRIG;
	130	+ it.edge_type = GPIO_SINGLE_EDGE;
	131	+ it.logic_type = GPIO_NEGATIVE_TRIG;
	132	+ break;
	133	+
	134	+ default:
	135	+ return -EINVAL;
	136	+ }
	137	+
	138	+ eqbr_irq_type_cfg(&it, gctrl, offset);
	139	+ if (it.trig_type == GPIO_EDGE_TRIG)
	140	+ irq_set_handler_locked(d, handle_edge_irq);
	141	+ else
	142	+ irq_set_handler_locked(d, handle_level_irq);
	143	+
	144	+ return 0;
	145	+}
	146	+
	147	+static void eqbr_irq_handler(struct irq_desc *desc)
	148	+{
	149	+ struct gpio_chip *gc = irq_desc_get_handler_data(desc);
	150	+ struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc);
	151	+ struct irq_chip *ic = irq_desc_get_chip(desc);
	152	+ unsigned long pins, offset;
	153	+
	154	+ chained_irq_enter(ic, desc);
	155	+ pins = readl(gctrl->membase + GPIO_IRNCR);
	156	+
	157	+ for_each_set_bit(offset, &pins, gc->ngpio)
	158	+ generic_handle_irq(irq_find_mapping(gc->irq.domain, offset));
	159	+
	160	+ chained_irq_exit(ic, desc);
	161	+}
	162	+
	163	+static int gpiochip_setup(struct device dev, struct eqbr_gpio_ctrl gctrl)
	164	+{
	165	+ struct gpio_irq_chip *girq;
	166	+ struct gpio_chip *gc;
	167	+
	168	+ gc = &gctrl->chip;
	169	+ gc->label = gctrl->name;
	170	+#if defined(CONFIG_OF_GPIO)
	171	+ gc->of_node = gctrl->node;
	172	+#endif
	173	+
	174	+ if (!of_property_read_bool(gctrl->node, "interrupt-controller")) {
	175	+ dev_dbg(dev, "gc %s: doesn't act as interrupt controller!\n",
	176	+ gctrl->name);
	177	+ return 0;
	178	+ }
	179	+
	180	+ gctrl->ic.name = "gpio_irq";
	181	+ gctrl->ic.irq_mask = eqbr_gpio_disable_irq;
	182	+ gctrl->ic.irq_unmask = eqbr_gpio_enable_irq;
	183	+ gctrl->ic.irq_ack = eqbr_gpio_ack_irq;
	184	+ gctrl->ic.irq_mask_ack = eqbr_gpio_mask_ack_irq;
	185	+ gctrl->ic.irq_set_type = eqbr_gpio_set_irq_type;
	186	+
	187	+ girq = &gctrl->chip.irq;
	188	+ girq->chip = &gctrl->ic;
	189	+ girq->parent_handler = eqbr_irq_handler;
	190	+ girq->num_parents = 1;
	191	+ girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), GFP_KERNEL);
	192	+ if (!girq->parents)
	193	+ return -ENOMEM;
	194	+
	195	+ girq->default_type = IRQ_TYPE_NONE;
	196	+ girq->handler = handle_bad_irq;
	197	+ girq->parents[0] = gctrl->virq;
	198	+
	199	+ return 0;
	200	+}
	201	+
	202	+static int gpiolib_reg(struct eqbr_pinctrl_drv_data *drvdata)
	203	+{
	204	+ struct device *dev = drvdata->dev;
	205	+ struct eqbr_gpio_ctrl *gctrl;
	206	+ struct device_node *np;
	207	+ struct resource res;
	208	+ int i, ret;
	209	+
	210	+ for (i = 0; i < drvdata->nr_gpio_ctrls; i++) {
	211	+ gctrl = drvdata->gpio_ctrls + i;
	212	+ np = gctrl->node;
	213	+
	214	+ gctrl->name = devm_kasprintf(dev, GFP_KERNEL, "gpiochip%d", i);
	215	+ if (!gctrl->name)
	216	+ return -ENOMEM;
	217	+
	218	+ if (of_address_to_resource(np, 0, &res)) {
	219	+ dev_err(dev, "Failed to get GPIO register address\n");
	220	+ return -ENXIO;
	221	+ }
	222	+
	223	+ gctrl->membase = devm_ioremap_resource(dev, &res);
	224	+ if (IS_ERR(gctrl->membase))
	225	+ return PTR_ERR(gctrl->membase);
	226	+
	227	+ gctrl->virq = irq_of_parse_and_map(np, 0);
	228	+ if (!gctrl->virq) {
	229	+ dev_err(dev, "%s: failed to parse and map irq\n",
	230	+ gctrl->name);
	231	+ return -ENXIO;
	232	+ }
	233	+ raw_spin_lock_init(&gctrl->lock);
	234	+
	235	+ ret = bgpio_init(&gctrl->chip, dev, gctrl->bank->nr_pins / 8,
	236	+ gctrl->membase + GPIO_IN,
	237	+ gctrl->membase + GPIO_OUTSET,
	238	+ gctrl->membase + GPIO_OUTCLR,
	239	+ gctrl->membase + GPIO_DIR,
	240	+ NULL, 0);
	241	+ if (ret) {
	242	+ dev_err(dev, "unable to init generic GPIO\n");
	243	+ return ret;
	244	+ }
	245	+
	246	+ ret = gpiochip_setup(dev, gctrl);
	247	+ if (ret)
	248	+ return ret;
	249	+
	250	+ ret = devm_gpiochip_add_data(dev, &gctrl->chip, gctrl);
	251	+ if (ret)
	252	+ return ret;
	253	+ }
	254	+
	255	+ return 0;
	256	+}
	257	+
	258	+static inline struct eqbr_pin_bank
	259	+find_pinbank_via_pin(struct eqbr_pinctrl_drv_data pctl, unsigned int pin)
	260	+{
	261	+ struct eqbr_pin_bank *bank;
	262	+ int i;
	263	+
	264	+ for (i = 0; i < pctl->nr_banks; i++) {
	265	+ bank = &pctl->pin_banks[i];
	266	+ if (pin >= bank->pin_base &&
	267	+ (pin - bank->pin_base) < bank->nr_pins)
	268	+ return bank;
	269	+ }
	270	+
	271	+ return NULL;
	272	+}
	273	+
	274	+static const struct pinctrl_ops eqbr_pctl_ops = {
	275	+ .get_groups_count = pinctrl_generic_get_group_count,
	276	+ .get_group_name = pinctrl_generic_get_group_name,
	277	+ .get_group_pins = pinctrl_generic_get_group_pins,
	278	+ .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
	279	+ .dt_free_map = pinconf_generic_dt_free_map,
	280	+};
	281	+
	282	+static int eqbr_set_pin_mux(struct eqbr_pinctrl_drv_data *pctl,
	283	+ unsigned int pmx, unsigned int pin)
	284	+{
	285	+ struct eqbr_pin_bank *bank;
	286	+ unsigned long flags;
	287	+ unsigned int offset;
	288	+ void __iomem *mem;
	289	+
	290	+ bank = find_pinbank_via_pin(pctl, pin);
	291	+ if (!bank) {
	292	+ dev_err(pctl->dev, "Couldn't find pin bank for pin %u\n", pin);
	293	+ return -ENODEV;
	294	+ }
	295	+ mem = bank->membase;
	296	+ offset = pin - bank->pin_base;
	297	+
	298	+ if (!(bank->aval_pinmap & BIT(offset))) {
	299	+ dev_err(pctl->dev,
	300	+ "PIN: %u is not valid, pinbase: %u, bitmap: %u\n",
	301	+ pin, bank->pin_base, bank->aval_pinmap);
	302	+ return -ENODEV;
	303	+ }
	304	+
	305	+ raw_spin_lock_irqsave(&pctl->lock, flags);
	306	+ writel(pmx, mem + (offset * 4));
	307	+ raw_spin_unlock_irqrestore(&pctl->lock, flags);
	308	+ return 0;
	309	+}
	310	+
	311	+static int eqbr_pinmux_set_mux(struct pinctrl_dev *pctldev,
	312	+ unsigned int selector, unsigned int group)
	313	+{
	314	+ struct eqbr_pinctrl_drv_data *pctl = pinctrl_dev_get_drvdata(pctldev);
	315	+ struct function_desc *func;
	316	+ struct group_desc *grp;
	317	+ unsigned int *pinmux;
	318	+ int i;
	319	+
	320	+ func = pinmux_generic_get_function(pctldev, selector);
	321	+ if (!func)
	322	+ return -EINVAL;
	323	+
	324	+ grp = pinctrl_generic_get_group(pctldev, group);
	325	+ if (!grp)
	326	+ return -EINVAL;
	327	+
	328	+ pinmux = grp->data;
	329	+ for (i = 0; i < grp->num_pins; i++)
	330	+ eqbr_set_pin_mux(pctl, pinmux[i], grp->pins[i]);
	331	+
	332	+ return 0;
	333	+}
	334	+
	335	+static int eqbr_pinmux_gpio_request(struct pinctrl_dev *pctldev,
	336	+ struct pinctrl_gpio_range *range,
	337	+ unsigned int pin)
	338	+{
	339	+ struct eqbr_pinctrl_drv_data *pctl = pinctrl_dev_get_drvdata(pctldev);
	340	+
	341	+ return eqbr_set_pin_mux(pctl, EQBR_GPIO_MODE, pin);
	342	+}
	343	+
	344	+static const struct pinmux_ops eqbr_pinmux_ops = {
	345	+ .get_functions_count = pinmux_generic_get_function_count,
	346	+ .get_function_name = pinmux_generic_get_function_name,
	347	+ .get_function_groups = pinmux_generic_get_function_groups,
	348	+ .set_mux = eqbr_pinmux_set_mux,
	349	+ .gpio_request_enable = eqbr_pinmux_gpio_request,
	350	+ .strict = true,
	351	+};
	352	+
	353	+static int get_drv_cur(void __iomem *mem, unsigned int offset)
	354	+{
	355	+ unsigned int idx = offset / DRV_CUR_PINS; /* 0-15, 16-31 per register*/
	356	+ unsigned int pin_offset = offset % DRV_CUR_PINS;
	357	+
	358	+ return PARSE_DRV_CURRENT(readl(mem + REG_DRCC(idx)), pin_offset);
	359	+}
	360	+
	361	+static struct eqbr_gpio_ctrl
	362	+get_gpio_ctrls_via_bank(struct eqbr_pinctrl_drv_data pctl,
	363	+ struct eqbr_pin_bank *bank)
	364	+{
	365	+ int i;
	366	+
	367	+ for (i = 0; i < pctl->nr_gpio_ctrls; i++) {
	368	+ if (pctl->gpio_ctrls[i].bank == bank)
	369	+ return &pctl->gpio_ctrls[i];
	370	+ }
	371	+
	372	+ return NULL;
	373	+}
	374	+
	375	+static int eqbr_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
	376	+ unsigned long *config)
	377	+{
	378	+ struct eqbr_pinctrl_drv_data *pctl = pinctrl_dev_get_drvdata(pctldev);
	379	+ enum pin_config_param param = pinconf_to_config_param(*config);
	380	+ struct eqbr_gpio_ctrl *gctrl;
	381	+ struct eqbr_pin_bank *bank;
	382	+ unsigned long flags;
	383	+ unsigned int offset;
	384	+ void __iomem *mem;
	385	+ u32 val;
	386	+
	387	+ bank = find_pinbank_via_pin(pctl, pin);
	388	+ if (!bank) {
	389	+ dev_err(pctl->dev, "Couldn't find pin bank for pin %u\n", pin);
	390	+ return -ENODEV;
	391	+ }
	392	+ mem = bank->membase;
	393	+ offset = pin - bank->pin_base;
	394	+
	395	+ if (!(bank->aval_pinmap & BIT(offset))) {
	396	+ dev_err(pctl->dev,
	397	+ "PIN: %u is not valid, pinbase: %u, bitmap: %u\n",
	398	+ pin, bank->pin_base, bank->aval_pinmap);
	399	+ return -ENODEV;
	400	+ }
	401	+
	402	+ raw_spin_lock_irqsave(&pctl->lock, flags);
	403	+ switch (param) {
	404	+ case PIN_CONFIG_BIAS_PULL_UP:
	405	+ val = !!(readl(mem + REG_PUEN) & BIT(offset));
	406	+ break;
	407	+ case PIN_CONFIG_BIAS_PULL_DOWN:
	408	+ val = !!(readl(mem + REG_PDEN) & BIT(offset));
	409	+ break;
	410	+ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
	411	+ val = !!(readl(mem + REG_OD) & BIT(offset));
	412	+ break;
	413	+ case PIN_CONFIG_DRIVE_STRENGTH:
	414	+ val = get_drv_cur(mem, offset);
	415	+ break;
	416	+ case PIN_CONFIG_SLEW_RATE:
	417	+ val = !!(readl(mem + REG_SRC) & BIT(offset));
	418	+ break;
	419	+ case PIN_CONFIG_OUTPUT_ENABLE:
	420	+ gctrl = get_gpio_ctrls_via_bank(pctl, bank);
	421	+ if (!gctrl) {
	422	+ dev_err(pctl->dev, "Failed to find gpio via bank pinbase: %u, pin: %u\n",
	423	+ bank->pin_base, pin);
	424	+ raw_spin_unlock_irqrestore(&pctl->lock, flags);
	425	+ return -ENODEV;
	426	+ }
	427	+ val = !!(readl(gctrl->membase + GPIO_DIR) & BIT(offset));
	428	+ break;
	429	+ default:
	430	+ raw_spin_unlock_irqrestore(&pctl->lock, flags);
	431	+ return -ENOTSUPP;
	432	+ }
	433	+ raw_spin_unlock_irqrestore(&pctl->lock, flags);
	434	+ *config = pinconf_to_config_packed(param, val);
	435	+;
	436	+ return 0;
	437	+}
	438	+
	439	+static int eqbr_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
	440	+ unsigned long *configs, unsigned int num_configs)
	441	+{
	442	+ struct eqbr_pinctrl_drv_data *pctl = pinctrl_dev_get_drvdata(pctldev);
	443	+ struct eqbr_gpio_ctrl *gctrl;
	444	+ enum pin_config_param param;
	445	+ struct eqbr_pin_bank *bank;
	446	+ unsigned int val, offset;
	447	+ struct gpio_chip *gc;
	448	+ unsigned long flags;
	449	+ void __iomem *mem;
	450	+ u32 regval, mask;
	451	+ int i;
	452	+
	453	+ for (i = 0; i < num_configs; i++) {
	454	+ param = pinconf_to_config_param(configs[i]);
	455	+ val = pinconf_to_config_argument(configs[i]);
	456	+
	457	+ bank = find_pinbank_via_pin(pctl, pin);
	458	+ if (!bank) {
	459	+ dev_err(pctl->dev,
	460	+ "Couldn't find pin bank for pin %u\n", pin);
	461	+ return -ENODEV;
	462	+ }
	463	+ mem = bank->membase;
	464	+ offset = pin - bank->pin_base;
	465	+
	466	+ switch (param) {
	467	+ case PIN_CONFIG_BIAS_PULL_UP:
	468	+ mem += REG_PUEN;
	469	+ mask = BIT(offset);
	470	+ break;
	471	+ case PIN_CONFIG_BIAS_PULL_DOWN:
	472	+ mem += REG_PDEN;
	473	+ mask = BIT(offset);
	474	+ break;
	475	+ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
	476	+ mem += REG_OD;
	477	+ mask = BIT(offset);
	478	+ break;
	479	+ case PIN_CONFIG_DRIVE_STRENGTH:
	480	+ mem += REG_DRCC(offset / DRV_CUR_PINS);
	481	+ offset = (offset % DRV_CUR_PINS) * 2;
	482	+ mask = GENMASK(1, 0) << offset;
	483	+ break;
	484	+ case PIN_CONFIG_SLEW_RATE:
	485	+ mem += REG_SRC;
	486	+ mask = BIT(offset);
	487	+ break;
	488	+ case PIN_CONFIG_OUTPUT_ENABLE:
	489	+ gctrl = get_gpio_ctrls_via_bank(pctl, bank);
	490	+ if (!gctrl) {
	491	+ dev_err(pctl->dev, "Failed to find gpio via bank pinbase: %u, pin: %u\n",
	492	+ bank->pin_base, pin);
	493	+ return -ENODEV;
	494	+ }
	495	+ gc = &gctrl->chip;
	496	+ gc->direction_output(gc, offset, 0);
	497	+ continue;
	498	+ default:
	499	+ return -ENOTSUPP;
	500	+ }
	501	+
	502	+ raw_spin_lock_irqsave(&pctl->lock, flags);
	503	+ regval = readl(mem);
	504	+ regval = (regval & ~mask) \| ((val << offset) & mask);
	505	+ writel(regval, mem);
	506	+ raw_spin_unlock_irqrestore(&pctl->lock, flags);
	507	+ }
	508	+
	509	+ return 0;
	510	+}
	511	+
	512	+static int eqbr_pinconf_group_get(struct pinctrl_dev *pctldev,
	513	+ unsigned int group, unsigned long *config)
	514	+{
	515	+ unsigned int i, npins, old = 0;
	516	+ const unsigned int *pins;
	517	+ int ret;
	518	+
	519	+ ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
	520	+ if (ret)
	521	+ return ret;
	522	+
	523	+ for (i = 0; i < npins; i++) {
	524	+ if (eqbr_pinconf_get(pctldev, pins[i], config))
	525	+ return -ENOTSUPP;
	526	+
	527	+ if (i && old != *config)
	528	+ return -ENOTSUPP;
	529	+
	530	+ old = *config;
	531	+ }
	532	+ return 0;
	533	+}
	534	+
	535	+static int eqbr_pinconf_group_set(struct pinctrl_dev *pctldev,
	536	+ unsigned int group, unsigned long *configs,
	537	+ unsigned int num_configs)
	538	+{
	539	+ const unsigned int *pins;
	540	+ unsigned int i, npins;
	541	+ int ret;
	542	+
	543	+ ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
	544	+ if (ret)
	545	+ return ret;
	546	+
	547	+ for (i = 0; i < npins; i++) {
	548	+ ret = eqbr_pinconf_set(pctldev, pins[i], configs, num_configs);
	549	+ if (ret)
	550	+ return ret;
	551	+ }
	552	+ return 0;
	553	+}
	554	+
	555	+static const struct pinconf_ops eqbr_pinconf_ops = {
	556	+ .is_generic = true,
	557	+ .pin_config_get = eqbr_pinconf_get,
	558	+ .pin_config_set = eqbr_pinconf_set,
	559	+ .pin_config_group_get = eqbr_pinconf_group_get,
	560	+ .pin_config_group_set = eqbr_pinconf_group_set,
	561	+ .pin_config_config_dbg_show = pinconf_generic_dump_config,
	562	+};
	563	+
	564	+static bool is_func_exist(struct eqbr_pmx_func funcs, const char name,
	565	+ unsigned int nr_funcs, unsigned int *idx)
	566	+{
	567	+ int i;
	568	+
	569	+ if (!funcs)
	570	+ return false;
	571	+
	572	+ for (i = 0; i < nr_funcs; i++) {
	573	+ if (funcs[i].name && !strcmp(funcs[i].name, name)) {
	574	+ *idx = i;
	575	+ return true;
	576	+ }
	577	+ }
	578	+
	579	+ return false;
	580	+}
	581	+
	582	+static int funcs_utils(struct device dev, struct eqbr_pmx_func funcs,
	583	+ unsigned int *nr_funcs, funcs_util_ops op)
	584	+{
	585	+ struct device_node *node = dev->of_node;
	586	+ struct device_node *np;
	587	+ struct property *prop;
	588	+ const char *fn_name;
	589	+ unsigned int fid;
	590	+ int i, j;
	591	+
	592	+ i = 0;
	593	+ for_each_child_of_node(node, np) {
	594	+ prop = of_find_property(np, "groups", NULL);
	595	+ if (!prop)
	596	+ continue;
	597	+
	598	+ if (of_property_read_string(np, "function", &fn_name)) {
	599	+ /* some groups may not have function, it's OK */
	600	+ dev_dbg(dev, "Group %s: not function binded!\n",
	601	+ (char *)prop->value);
	602	+ continue;
	603	+ }
	604	+
	605	+ switch (op) {
	606	+ case OP_COUNT_NR_FUNCS:
	607	+ if (!is_func_exist(funcs, fn_name, *nr_funcs, &fid))
	608	+ nr_funcs = nr_funcs + 1;
	609	+ break;
	610	+
	611	+ case OP_ADD_FUNCS:
	612	+ if (!is_func_exist(funcs, fn_name, *nr_funcs, &fid))
	613	+ funcs[i].name = fn_name;
	614	+ break;
	615	+
	616	+ case OP_COUNT_NR_FUNC_GRPS:
	617	+ if (is_func_exist(funcs, fn_name, *nr_funcs, &fid))
	618	+ funcs[fid].nr_groups++;
	619	+ break;
	620	+
	621	+ case OP_ADD_FUNC_GRPS:
	622	+ if (is_func_exist(funcs, fn_name, *nr_funcs, &fid)) {
	623	+ for (j = 0; j < funcs[fid].nr_groups; j++)
	624	+ if (!funcs[fid].groups[j])
	625	+ break;
	626	+ funcs[fid].groups[j] = prop->value;
	627	+ }
	628	+ break;
	629	+
	630	+ default:
	631	+ return -EINVAL;
	632	+ }
	633	+ i++;
	634	+ }
	635	+
	636	+ return 0;
	637	+}
	638	+
	639	+static int eqbr_build_functions(struct eqbr_pinctrl_drv_data *drvdata)
	640	+{
	641	+ struct device *dev = drvdata->dev;
	642	+ struct eqbr_pmx_func *funcs = NULL;
	643	+ unsigned int nr_funcs = 0;
	644	+ int i, ret;
	645	+
	646	+ ret = funcs_utils(dev, funcs, &nr_funcs, OP_COUNT_NR_FUNCS);
	647	+ if (ret)
	648	+ return ret;
	649	+
	650	+ funcs = devm_kcalloc(dev, nr_funcs, sizeof(*funcs), GFP_KERNEL);
	651	+ if (!funcs)
	652	+ return -ENOMEM;
	653	+
	654	+ ret = funcs_utils(dev, funcs, &nr_funcs, OP_ADD_FUNCS);
	655	+ if (ret)
	656	+ return ret;
	657	+
	658	+ ret = funcs_utils(dev, funcs, &nr_funcs, OP_COUNT_NR_FUNC_GRPS);
	659	+ if (ret)
	660	+ return ret;
	661	+
	662	+ for (i = 0; i < nr_funcs; i++) {
	663	+ if (!funcs[i].nr_groups)
	664	+ continue;
	665	+ funcs[i].groups = devm_kcalloc(dev, funcs[i].nr_groups,
	666	+ sizeof(*(funcs[i].groups)),
	667	+ GFP_KERNEL);
	668	+ if (!funcs[i].groups)
	669	+ return -ENOMEM;
	670	+ }
	671	+
	672	+ ret = funcs_utils(dev, funcs, &nr_funcs, OP_ADD_FUNC_GRPS);
	673	+ if (ret)
	674	+ return ret;
	675	+
	676	+ for (i = 0; i < nr_funcs; i++) {
	677	+ ret = pinmux_generic_add_function(drvdata->pctl_dev,
	678	+ funcs[i].name,
	679	+ funcs[i].groups,
	680	+ funcs[i].nr_groups,
	681	+ drvdata);
	682	+ if (ret < 0) {
	683	+ dev_err(dev, "Failed to register function %s\n",
	684	+ funcs[i].name);
	685	+ return ret;
	686	+ }
	687	+ }
	688	+
	689	+ return 0;
	690	+}
	691	+
	692	+static int eqbr_build_groups(struct eqbr_pinctrl_drv_data *drvdata)
	693	+{
	694	+ struct device *dev = drvdata->dev;
	695	+ struct device_node *node = dev->of_node;
	696	+ unsigned int *pinmux, pin_id, pinmux_id;
	697	+ struct group_desc group;
	698	+ struct device_node *np;
	699	+ struct property *prop;
	700	+ int j, err;
	701	+
	702	+ for_each_child_of_node(node, np) {
	703	+ prop = of_find_property(np, "groups", NULL);
	704	+ if (!prop)
	705	+ continue;
	706	+
	707	+ group.num_pins = of_property_count_u32_elems(np, "pins");
	708	+ if (group.num_pins < 0) {
	709	+ dev_err(dev, "No pins in the group: %s\n", prop->name);
	710	+ return -EINVAL;
	711	+ }
	712	+ group.name = prop->value;
	713	+ group.pins = devm_kcalloc(dev, group.num_pins,
	714	+ sizeof(*(group.pins)), GFP_KERNEL);
	715	+ if (!group.pins)
	716	+ return -ENOMEM;
	717	+
	718	+ pinmux = devm_kcalloc(dev, group.num_pins, sizeof(*pinmux),
	719	+ GFP_KERNEL);
	720	+ if (!pinmux)
	721	+ return -ENOMEM;
	722	+
	723	+ for (j = 0; j < group.num_pins; j++) {
	724	+ if (of_property_read_u32_index(np, "pins", j, &pin_id)) {
	725	+ dev_err(dev, "Group %s: Read intel pins id failed\n",
	726	+ group.name);
	727	+ return -EINVAL;
	728	+ }
	729	+ if (pin_id >= drvdata->pctl_desc.npins) {
	730	+ dev_err(dev, "Group %s: Invalid pin ID, idx: %d, pin %u\n",
	731	+ group.name, j, pin_id);
	732	+ return -EINVAL;
	733	+ }
	734	+ group.pins[j] = pin_id;
	735	+ if (of_property_read_u32_index(np, "pinmux", j, &pinmux_id)) {
	736	+ dev_err(dev, "Group %s: Read intel pinmux id failed\n",
	737	+ group.name);
	738	+ return -EINVAL;
	739	+ }
	740	+ pinmux[j] = pinmux_id;
	741	+ }
	742	+
	743	+ err = pinctrl_generic_add_group(drvdata->pctl_dev, group.name,
	744	+ group.pins, group.num_pins,
	745	+ pinmux);
	746	+ if (err < 0) {
	747	+ dev_err(dev, "Failed to register group %s\n", group.name);
	748	+ return err;
	749	+ }
	750	+ memset(&group, 0, sizeof(group));
	751	+ pinmux = NULL;
	752	+ }
	753	+
	754	+ return 0;
	755	+}
	756	+
	757	+static int pinctrl_reg(struct eqbr_pinctrl_drv_data *drvdata)
	758	+{
	759	+ struct pinctrl_desc *pctl_desc;
	760	+ struct pinctrl_pin_desc *pdesc;
	761	+ struct device *dev;
	762	+ unsigned int nr_pins;
	763	+ char *pin_names;
	764	+ int i, ret;
	765	+
	766	+ dev = drvdata->dev;
	767	+ pctl_desc = &drvdata->pctl_desc;
	768	+ pctl_desc->name = "eqbr-pinctrl";
	769	+ pctl_desc->owner = THIS_MODULE;
	770	+ pctl_desc->pctlops = &eqbr_pctl_ops;
	771	+ pctl_desc->pmxops = &eqbr_pinmux_ops;
	772	+ pctl_desc->confops = &eqbr_pinconf_ops;
	773	+ raw_spin_lock_init(&drvdata->lock);
	774	+
	775	+ for (i = 0, nr_pins = 0; i < drvdata->nr_banks; i++)
	776	+ nr_pins += drvdata->pin_banks[i].nr_pins;
	777	+
	778	+ pdesc = devm_kcalloc(dev, nr_pins, sizeof(*pdesc), GFP_KERNEL);
	779	+ if (!pdesc)
	780	+ return -ENOMEM;
	781	+ pin_names = devm_kcalloc(dev, nr_pins, PIN_NAME_LEN, GFP_KERNEL);
	782	+ if (!pin_names)
	783	+ return -ENOMEM;
	784	+
	785	+ for (i = 0; i < nr_pins; i++) {
	786	+ sprintf(pin_names, PIN_NAME_FMT, i);
	787	+ pdesc[i].number = i;
	788	+ pdesc[i].name = pin_names;
	789	+ pin_names += PIN_NAME_LEN;
	790	+ }
	791	+ pctl_desc->pins = pdesc;
	792	+ pctl_desc->npins = nr_pins;
	793	+ dev_dbg(dev, "pinctrl total pin number: %u\n", nr_pins);
	794	+
	795	+ ret = devm_pinctrl_register_and_init(dev, pctl_desc, drvdata,
	796	+ &drvdata->pctl_dev);
	797	+ if (ret)
	798	+ return ret;
	799	+
	800	+ ret = eqbr_build_groups(drvdata);
	801	+ if (ret) {
	802	+ dev_err(dev, "Failed to build groups\n");
	803	+ return ret;
	804	+ }
	805	+
	806	+ ret = eqbr_build_functions(drvdata);
	807	+ if (ret) {
	808	+ dev_err(dev, "Failed to build groups\n");
	809	+ return ret;
	810	+ }
	811	+
	812	+ return pinctrl_enable(drvdata->pctl_dev);
	813	+}
	814	+
	815	+static int pinbank_init(struct device_node *np,
	816	+ struct eqbr_pinctrl_drv_data *drvdata,
	817	+ struct eqbr_pin_bank *bank, unsigned int id)
	818	+{
	819	+ struct device *dev = drvdata->dev;
	820	+ struct of_phandle_args spec;
	821	+ int ret;
	822	+
	823	+ bank->membase = drvdata->membase + id * PAD_REG_OFF;
	824	+
	825	+ ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &spec);
	826	+ if (ret) {
	827	+ dev_err(dev, "gpio-range not available!\n");
	828	+ return ret;
	829	+ }
	830	+
	831	+ bank->pin_base = spec.args[1];
	832	+ bank->nr_pins = spec.args[2];
	833	+
	834	+ bank->aval_pinmap = readl(bank->membase + REG_AVAIL);
	835	+ bank->id = id;
	836	+
	837	+ dev_dbg(dev, "pinbank id: %d, reg: %px, pinbase: %u, pin number: %u, pinmap: 0x%x\n",
	838	+ id, bank->membase, bank->pin_base,
	839	+ bank->nr_pins, bank->aval_pinmap);
	840	+
	841	+ return ret;
	842	+}
	843	+
	844	+static int pinbank_probe(struct eqbr_pinctrl_drv_data *drvdata)
	845	+{
	846	+ struct device *dev = drvdata->dev;
	847	+ struct device_node *np_gpio;
	848	+ struct eqbr_gpio_ctrl *gctrls;
	849	+ struct eqbr_pin_bank *banks;
	850	+ int i, nr_gpio;
	851	+
	852	+ /* Count gpio bank number */
	853	+ nr_gpio = 0;
	854	+ for_each_node_by_name(np_gpio, "gpio") {
	855	+ if (of_device_is_available(np_gpio))
	856	+ nr_gpio++;
	857	+ }
	858	+
	859	+ if (!nr_gpio) {
	860	+ dev_err(dev, "NO pin bank available!\n");
	861	+ return -ENODEV;
	862	+ }
	863	+
	864	+ /* Count pin bank number and gpio controller number */
	865	+ banks = devm_kcalloc(dev, nr_gpio, sizeof(*banks), GFP_KERNEL);
	866	+ if (!banks)
	867	+ return -ENOMEM;
	868	+
	869	+ gctrls = devm_kcalloc(dev, nr_gpio, sizeof(*gctrls), GFP_KERNEL);
	870	+ if (!gctrls)
	871	+ return -ENOMEM;
	872	+
	873	+ dev_dbg(dev, "found %d gpio controller!\n", nr_gpio);
	874	+
	875	+ /* Initialize Pin bank */
	876	+ i = 0;
	877	+ for_each_node_by_name(np_gpio, "gpio") {
	878	+ if (!of_device_is_available(np_gpio))
	879	+ continue;
	880	+
	881	+ pinbank_init(np_gpio, drvdata, banks + i, i);
	882	+
	883	+ gctrls[i].node = np_gpio;
	884	+ gctrls[i].bank = banks + i;
	885	+ i++;
	886	+ }
	887	+
	888	+ drvdata->pin_banks = banks;
	889	+ drvdata->nr_banks = nr_gpio;
	890	+ drvdata->gpio_ctrls = gctrls;
	891	+ drvdata->nr_gpio_ctrls = nr_gpio;
	892	+
	893	+ return 0;
	894	+}
	895	+
	896	+static int eqbr_pinctrl_probe(struct platform_device *pdev)
	897	+{
	898	+ struct eqbr_pinctrl_drv_data *drvdata;
	899	+ struct device *dev = &pdev->dev;
	900	+ int ret;
	901	+
	902	+ drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
	903	+ if (!drvdata)
	904	+ return -ENOMEM;
	905	+
	906	+ drvdata->dev = dev;
	907	+
	908	+ drvdata->membase = devm_platform_ioremap_resource(pdev, 0);
	909	+ if (IS_ERR(drvdata->membase))
	910	+ return PTR_ERR(drvdata->membase);
	911	+
	912	+ ret = pinbank_probe(drvdata);
	913	+ if (ret)
	914	+ return ret;
	915	+
	916	+ ret = pinctrl_reg(drvdata);
	917	+ if (ret)
	918	+ return ret;
	919	+
	920	+ ret = gpiolib_reg(drvdata);
	921	+ if (ret)
	922	+ return ret;
	923	+
	924	+ platform_set_drvdata(pdev, drvdata);
	925	+ return 0;
	926	+}
	927	+
	928	+static const struct of_device_id eqbr_pinctrl_dt_match[] = {
	929	+ { .compatible = "intel,lgm-io" },
	930	+ {}
	931	+};
	932	+
	933	+static struct platform_driver eqbr_pinctrl_driver = {
	934	+ .probe = eqbr_pinctrl_probe,
	935	+ .driver = {
	936	+ .name = "eqbr-pinctrl",
	937	+ .of_match_table = eqbr_pinctrl_dt_match,
	938	+ },
	939	+};
	940	+
	941	+module_platform_driver(eqbr_pinctrl_driver);
	942	+
	943	+MODULE_AUTHOR("Zhu Yixin <yixin.zhu@intel.com>, Rahul Tanwar <rahul.tanwar@intel.com>");
	944	+MODULE_DESCRIPTION("Pinctrl Driver for LGM SoC (Equilibrium)");

drivers/pinctrl/pinctrl-equilibrium.h+144−0

@@ -0,0 +1,144 @@
	1	+/* SPDX-License-Identifier: GPL-2.0 */
	2	+/*
	3	+ * Copyright(c) 2019 Intel Corporation.
	4	+ */
	5	+
	6	+#ifndef __PINCTRL_EQUILIBRIUM_H
	7	+#define __PINCTRL_EQUILIBRIUM_H
	8	+
	9	+/* PINPAD register offset */
	10	+#define REG_PMX_BASE 0x0 /* Port Multiplexer Control Register */
	11	+#define REG_PUEN 0x80 /* PULL UP Enable Register */
	12	+#define REG_PDEN 0x84 /* PULL DOWN Enable Register */
	13	+#define REG_SRC 0x88 /* Slew Rate Control Register */
	14	+#define REG_DCC0 0x8C /* Drive Current Control Register 0 */
	15	+#define REG_DCC1 0x90 /* Drive Current Control Register 1 */
	16	+#define REG_OD 0x94 /* Open Drain Enable Register */
	17	+#define REG_AVAIL 0x98 /* Pad Control Availability Register */
	18	+#define DRV_CUR_PINS 16 /* Drive Current pin number per register */
	19	+#define REG_DRCC(x) (REG_DCC0 + (x) * 4) /* Driver current macro */
	20	+
	21	+/* GPIO register offset */
	22	+#define GPIO_OUT 0x0 /* Data Output Register */
	23	+#define GPIO_IN 0x4 /* Data Input Register */
	24	+#define GPIO_DIR 0x8 /* Direction Register */
	25	+#define GPIO_EXINTCR0 0x18 /* External Interrupt Control Register 0 */
	26	+#define GPIO_EXINTCR1 0x1C /* External Interrupt Control Register 1 */
	27	+#define GPIO_IRNCR 0x20 /* IRN Capture Register */
	28	+#define GPIO_IRNICR 0x24 /* IRN Interrupt Control Register */
	29	+#define GPIO_IRNEN 0x28 /* IRN Interrupt Enable Register */
	30	+#define GPIO_IRNCFG 0x2C /* IRN Interrupt Configuration Register */
	31	+#define GPIO_IRNRNSET 0x30 /* IRN Interrupt Enable Set Register */
	32	+#define GPIO_IRNENCLR 0x34 /* IRN Interrupt Enable Clear Register */
	33	+#define GPIO_OUTSET 0x40 /* Output Set Register */
	34	+#define GPIO_OUTCLR 0x44 /* Output Clear Register */
	35	+#define GPIO_DIRSET 0x48 /* Direction Set Register */
	36	+#define GPIO_DIRCLR 0x4C /* Direction Clear Register */
	37	+
	38	+/* parse given pin's driver current value */
	39	+#define PARSE_DRV_CURRENT(val, pin) (((val) >> ((pin) * 2)) & 0x3)
	40	+
	41	+#define GPIO_EDGE_TRIG 0
	42	+#define GPIO_LEVEL_TRIG 1
	43	+#define GPIO_SINGLE_EDGE 0
	44	+#define GPIO_BOTH_EDGE 1
	45	+#define GPIO_POSITIVE_TRIG 0
	46	+#define GPIO_NEGATIVE_TRIG 1
	47	+
	48	+#define EQBR_GPIO_MODE 0
	49	+
	50	+typedef enum {
	51	+ OP_COUNT_NR_FUNCS,
	52	+ OP_ADD_FUNCS,
	53	+ OP_COUNT_NR_FUNC_GRPS,
	54	+ OP_ADD_FUNC_GRPS,
	55	+ OP_NONE,
	56	+} funcs_util_ops;
	57	+
	58	+/**
	59	+ * struct gpio_irq_type: gpio irq configuration
	60	+ * @trig_type: level trigger or edge trigger
	61	+ * @edge_type: sigle edge or both edge
	62	+ * @logic_type: positive trigger or negative trigger
	63	+ */
	64	+struct gpio_irq_type {
	65	+ unsigned int trig_type;
	66	+ unsigned int edge_type;
	67	+ unsigned int logic_type;
	68	+};
	69	+
	70	+/**
	71	+ * struct eqbr_pmx_func: represent a pin function.
	72	+ * @name: name of the pin function, used to lookup the function.
	73	+ * @groups: one or more names of pin groups that provide this function.
	74	+ * @nr_groups: number of groups included in @groups.
	75	+ */
	76	+struct eqbr_pmx_func {
	77	+ const char *name;
	78	+ const char **groups;
	79	+ unsigned int nr_groups;
	80	+};
	81	+
	82	+/**
	83	+ * struct eqbr_pin_bank: represent a pin bank.
	84	+ * @membase: base address of the pin bank register.
	85	+ * @id: bank id, to idenify the unique bank.
	86	+ * @pin_base: starting pin number of the pin bank.
	87	+ * @nr_pins: number of the pins of the pin bank.
	88	+ * @aval_pinmap: available pin bitmap of the pin bank.
	89	+ */
	90	+struct eqbr_pin_bank {
	91	+ void __iomem *membase;
	92	+ unsigned int id;
	93	+ unsigned int pin_base;
	94	+ unsigned int nr_pins;
	95	+ u32 aval_pinmap;
	96	+};
	97	+
	98	+/**
	99	+ * struct eqbr_gpio_ctrl: represent a gpio controller.
	100	+ * @node: device node of gpio controller.
	101	+ * @bank: pointer to corresponding pin bank.
	102	+ * @membase: base address of the gpio controller.
	103	+ * @chip: gpio chip.
	104	+ * @ic: irq chip.
	105	+ * @name: gpio chip name.
	106	+ * @virq: irq number of the gpio chip to parent's irq domain.
	107	+ * @lock: spin lock to protect gpio register write.
	108	+ */
	109	+struct eqbr_gpio_ctrl {
	110	+ struct device_node *node;
	111	+ struct eqbr_pin_bank *bank;
	112	+ void __iomem *membase;
	113	+ struct gpio_chip chip;
	114	+ struct irq_chip ic;
	115	+ const char *name;
	116	+ unsigned int virq;
	117	+ raw_spinlock_t lock; /* protect gpio register */
	118	+};
	119	+
	120	+/**
	121	+ * struct eqbr_pinctrl_drv_data:
	122	+ * @dev: device instance representing the controller.
	123	+ * @pctl_desc: pin controller descriptor.
	124	+ * @pctl_dev: pin control class device
	125	+ * @membase: base address of pin controller
	126	+ * @pin_banks: list of pin banks of the driver.
	127	+ * @nr_banks: number of pin banks.
	128	+ * @gpio_ctrls: list of gpio controllers.
	129	+ * @nr_gpio_ctrls: number of gpio controllers.
	130	+ * @lock: protect pinctrl register write
	131	+ */
	132	+struct eqbr_pinctrl_drv_data {
	133	+ struct device *dev;
	134	+ struct pinctrl_desc pctl_desc;
	135	+ struct pinctrl_dev *pctl_dev;
	136	+ void __iomem *membase;
	137	+ struct eqbr_pin_bank *pin_banks;
	138	+ unsigned int nr_banks;
	139	+ struct eqbr_gpio_ctrl *gpio_ctrls;
	140	+ unsigned int nr_gpio_ctrls;
	141	+ raw_spinlock_t lock; /* protect pinpad register */
	142	+};
	143	+
	144	+#endif /* __PINCTRL_EQUILIBRIUM_H */

drivers/pinctrl/pinctrl-ingenic.c+41−9

@@ -686,6 +686,7 @@ static int jz4770_mac_rmii_pins[] = { · 685 unmodified lines
686	686	0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8,
687	687	};
688	688	static int jz4770_mac_mii_pins[] = { 0xa7, 0xaf, };
	689	+static int jz4770_otg_pins[] = { 0x8a, };
689	690
690	691	static int jz4770_uart0_data_funcs[] = { 0, 0, };
691	692	static int jz4770_uart0_hwflow_funcs[] = { 0, 0, };
@@ -744,6 +745,7 @@ static int jz4770_pwm_pwm6_funcs[] = { 0, }; · 52 unmodified lines
744	745	static int jz4770_pwm_pwm7_funcs[] = { 0, };
745	746	static int jz4770_mac_rmii_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
746	747	static int jz4770_mac_mii_funcs[] = { 0, 0, };
	748	+static int jz4770_otg_funcs[] = { 0, };
747	749
748	750	static const struct group_desc jz4770_groups[] = {
749	751	INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data),
@@ -799,6 +801,7 @@ static const struct group_desc jz4770_groups[] = { · 49 unmodified lines
799	801	INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7),
800	802	INGENIC_PIN_GROUP("mac-rmii", jz4770_mac_rmii),
801	803	INGENIC_PIN_GROUP("mac-mii", jz4770_mac_mii),
	804	+ INGENIC_PIN_GROUP("otg-vbus", jz4770_otg),
802	805	};
803	806
804	807	static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
@@ -841,6 +844,7 @@ static const char *jz4770_pwm5_groups[] = { "pwm5", }; · 36 unmodified lines
841	844	static const char *jz4770_pwm6_groups[] = { "pwm6", };
842	845	static const char *jz4770_pwm7_groups[] = { "pwm7", };
843	846	static const char *jz4770_mac_groups[] = { "mac-rmii", "mac-mii", };
	847	+static const char *jz4770_otg_groups[] = { "otg-vbus", };
844	848
845	849	static const struct function_desc jz4770_functions[] = {
846	850	{ "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
@@ -871,6 +875,7 @@ static const struct function_desc jz4770_functions[] = { · 24 unmodified lines
871	875	{ "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), },
872	876	{ "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), },
873	877	{ "mac", jz4770_mac_groups, ARRAY_SIZE(jz4770_mac_groups), },
	878	+ { "otg", jz4770_otg_groups, ARRAY_SIZE(jz4770_otg_groups), },
874	879	};
875	880
876	881	static const struct ingenic_chip_info jz4770_chip_info = {
@@ -1801,19 +1806,30 @@ static void ingenic_set_bias(struct ingenic_pinctrl *jzpc, · 924 unmodified lines
1801	1806	ingenic_config_pin(jzpc, pin, JZ4740_GPIO_PULL_DIS, !enabled);
1802	1807	}
1803	1808
	1809	+static void ingenic_set_output_level(struct ingenic_pinctrl *jzpc,
	1810	+ unsigned int pin, bool high)
	1811	+{
	1812	+ if (jzpc->version >= ID_JZ4770)
	1813	+ ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, high);
	1814	+ else
	1815	+ ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DATA, high);
	1816	+}
	1817	+
1804	1818	static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1805	1819	unsigned long *configs, unsigned int num_configs)
1806	1820	{
1807	1821	struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
1808	1822	unsigned int idx = pin % PINS_PER_GPIO_CHIP;
1809	1823	unsigned int offt = pin / PINS_PER_GPIO_CHIP;
1810		− unsigned int cfg;
	1824	+ unsigned int cfg, arg;
	1825	+ int ret;
1811	1826
1812	1827	for (cfg = 0; cfg < num_configs; cfg++) {
1813	1828	switch (pinconf_to_config_param(configs[cfg])) {
1814	1829	case PIN_CONFIG_BIAS_DISABLE:
1815	1830	case PIN_CONFIG_BIAS_PULL_UP:
1816	1831	case PIN_CONFIG_BIAS_PULL_DOWN:
	1832	+ case PIN_CONFIG_OUTPUT:
1817	1833	continue;
1818	1834	default:
1819	1835	return -ENOTSUPP;
@@ -1821,6 +1837,8 @@ static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, · 1 unmodified line
1821	1837	}
1822	1838
1823	1839	for (cfg = 0; cfg < num_configs; cfg++) {
	1840	+ arg = pinconf_to_config_argument(configs[cfg]);
	1841	+
1824	1842	switch (pinconf_to_config_param(configs[cfg])) {
1825	1843	case PIN_CONFIG_BIAS_DISABLE:
1826	1844	dev_dbg(jzpc->dev, "disable pull-over for pin P%c%u\n",
@@ -1844,6 +1862,14 @@ static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, · 17 unmodified lines
1844	1862	ingenic_set_bias(jzpc, pin, true);
1845	1863	break;
1846	1864
	1865	+ case PIN_CONFIG_OUTPUT:
	1866	+ ret = pinctrl_gpio_direction_output(pin);
	1867	+ if (ret)
	1868	+ return ret;
	1869	+
	1870	+ ingenic_set_output_level(jzpc, pin, arg);
	1871	+ break;
	1872	+
1847	1873	default:
1848	1874	unreachable();
1849	1875	}
@@ -1940,6 +1966,7 @@ static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc, · 90 unmodified lines
1940	1966	{
1941	1967	struct ingenic_gpio_chip *jzgc;
1942	1968	struct device *dev = jzpc->dev;
	1969	+ struct gpio_irq_chip *girq;
1943	1970	unsigned int bank;
1944	1971	int err;
1945	1972
@@ -1982,10 +2009,6 @@ static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc, · 36 unmodified lines
1982	2009	jzgc->gc.free = gpiochip_generic_free;
1983	2010	}
1984	2011
1985		− err = devm_gpiochip_add_data(dev, &jzgc->gc, jzgc);
1986		− if (err)
1987		− return err;
1988		−
1989	2012	jzgc->irq = irq_of_parse_and_map(node, 0);
1990	2013	if (!jzgc->irq)
1991	2014	return -EINVAL;
@@ -2000,13 +2023,22 @@ static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc, · 8 unmodified lines
2000	2023	jzgc->irq_chip.irq_set_wake = ingenic_gpio_irq_set_wake;
2001	2024	jzgc->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND;
2002	2025
2003		− err = gpiochip_irqchip_add(&jzgc->gc, &jzgc->irq_chip, 0,
2004		− handle_level_irq, IRQ_TYPE_NONE);
	2026	+ girq = &jzgc->gc.irq;
	2027	+ girq->chip = &jzgc->irq_chip;
	2028	+ girq->parent_handler = ingenic_gpio_irq_handler;
	2029	+ girq->num_parents = 1;
	2030	+ girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
	2031	+ GFP_KERNEL);
	2032	+ if (!girq->parents)
	2033	+ return -ENOMEM;
	2034	+ girq->parents[0] = jzgc->irq;
	2035	+ girq->default_type = IRQ_TYPE_NONE;
	2036	+ girq->handler = handle_level_irq;
	2037	+
	2038	+ err = devm_gpiochip_add_data(dev, &jzgc->gc, jzgc);
2005	2039	if (err)
2006	2040	return err;
2007	2041
2008		− gpiochip_set_chained_irqchip(&jzgc->gc, &jzgc->irq_chip,
2009		− jzgc->irq, ingenic_gpio_irq_handler);
2010	2042	return 0;
2011	2043	}
2012	2044

drivers/pinctrl/pinctrl-lpc18xx.c+1−3

@@ -1324,15 +1324,13 @@ static int lpc18xx_create_group_func_map(struct device *dev, · 1323 unmodified lines
1324	1324	static int lpc18xx_scu_probe(struct platform_device *pdev)
1325	1325	{
1326	1326	struct lpc18xx_scu_data *scu;
1327		− struct resource *res;
1328	1327	int ret;
1329	1328
1330	1329	scu = devm_kzalloc(&pdev->dev, sizeof(*scu), GFP_KERNEL);
1331	1330	if (!scu)
1332	1331	return -ENOMEM;
1333	1332
1334		− res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1335		− scu->base = devm_ioremap_resource(&pdev->dev, res);
	1333	+ scu->base = devm_platform_ioremap_resource(pdev, 0);
1336	1334	if (IS_ERR(scu->base))
1337	1335	return PTR_ERR(scu->base);
1338	1336

drivers/pinctrl/pinctrl-ocelot.c+14−9

@@ -736,6 +736,7 @@ static int ocelot_gpiochip_register(struct platform_device *pdev, · 735 unmodified lines
736	736	struct ocelot_pinctrl *info)
737	737	{
738	738	struct gpio_chip *gc;
	739	+ struct gpio_irq_chip *girq;
739	740	int ret, irq;
740	741
741	742	info->gpio_chip = ocelot_gpiolib_chip;
@@ -747,22 +748,26 @@ static int ocelot_gpiochip_register(struct platform_device *pdev, · 5 unmodified lines
747	748	gc->of_node = info->dev->of_node;
748	749	gc->label = "ocelot-gpio";
749	750
750		− ret = devm_gpiochip_add_data(&pdev->dev, gc, info);
751		− if (ret)
752		− return ret;
753		−
754	751	irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
755	752	if (irq <= 0)
756	753	return irq;
757	754
758		− ret = gpiochip_irqchip_add(gc, &ocelot_irqchip, 0, handle_edge_irq,
759		− IRQ_TYPE_NONE);
	755	+ girq = &gc->irq;
	756	+ girq->chip = &ocelot_irqchip;
	757	+ girq->parent_handler = ocelot_irq_handler;
	758	+ girq->num_parents = 1;
	759	+ girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents),
	760	+ GFP_KERNEL);
	761	+ if (!girq->parents)
	762	+ return -ENOMEM;
	763	+ girq->parents[0] = irq;
	764	+ girq->default_type = IRQ_TYPE_NONE;
	765	+ girq->handler = handle_edge_irq;
	766	+
	767	+ ret = devm_gpiochip_add_data(&pdev->dev, gc, info);
760	768	if (ret)
761	769	return ret;
762	770
763		− gpiochip_set_chained_irqchip(gc, &ocelot_irqchip, irq,
764		− ocelot_irq_handler);
765		−
766	771	return 0;
767	772	}
768	773

drivers/pinctrl/pinctrl-oxnas.c+14−15

@@ -1196,7 +1196,7 @@ static int oxnas_gpio_probe(struct platform_device *pdev) · 1195 unmodified lines
1196	1196	struct oxnas_gpio_bank *bank;
1197	1197	unsigned int id, ngpios;
1198	1198	int irq, ret;
1199		− struct resource *res;
	1199	+ struct gpio_irq_chip *girq;
1200	1200
1201	1201	if (of_parse_phandle_with_fixed_args(np, "gpio-ranges",
1202	1202	3, 0, &pinspec)) {
@@ -1219,8 +1219,7 @@ static int oxnas_gpio_probe(struct platform_device *pdev) · 16 unmodified lines
1219	1219
1220	1220	bank = &oxnas_gpio_banks[id];
1221	1221
1222		− res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1223		− bank->reg_base = devm_ioremap_resource(&pdev->dev, res);
	1222	+ bank->reg_base = devm_platform_ioremap_resource(pdev, 0);
1224	1223	if (IS_ERR(bank->reg_base))
1225	1224	return PTR_ERR(bank->reg_base);
1226	1225
@@ -1232,6 +1231,18 @@ static int oxnas_gpio_probe(struct platform_device *pdev) · 5 unmodified lines
1232	1231	bank->gpio_chip.parent = &pdev->dev;
1233	1232	bank->gpio_chip.of_node = np;
1234	1233	bank->gpio_chip.ngpio = ngpios;
	1234	+ girq = &bank->gpio_chip.irq;
	1235	+ girq->chip = &bank->irq_chip;
	1236	+ girq->parent_handler = oxnas_gpio_irq_handler;
	1237	+ girq->num_parents = 1;
	1238	+ girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents),
	1239	+ GFP_KERNEL);
	1240	+ if (!girq->parents)
	1241	+ return -ENOMEM;
	1242	+ girq->parents[0] = irq;
	1243	+ girq->default_type = IRQ_TYPE_NONE;
	1244	+ girq->handler = handle_level_irq;
	1245	+
1235	1246	ret = gpiochip_add_data(&bank->gpio_chip, bank);
1236	1247	if (ret < 0) {
1237	1248	dev_err(&pdev->dev, "Failed to add GPIO chip %u: %d\n",
@@ -1239,18 +1250,6 @@ static int oxnas_gpio_probe(struct platform_device *pdev) · 1 unmodified line
1239	1250	return ret;
1240	1251	}
1241	1252
1242		− ret = gpiochip_irqchip_add(&bank->gpio_chip, &bank->irq_chip,
1243		− 0, handle_level_irq, IRQ_TYPE_NONE);
1244		− if (ret < 0) {
1245		− dev_err(&pdev->dev, "Failed to add IRQ chip %u: %d\n",
1246		− id, ret);
1247		− gpiochip_remove(&bank->gpio_chip);
1248		− return ret;
1249		− }
1250		−
1251		− gpiochip_set_chained_irqchip(&bank->gpio_chip, &bank->irq_chip,
1252		− irq, oxnas_gpio_irq_handler);
1253		−
1254	1253	return 0;
1255	1254	}
1256	1255

drivers/pinctrl/pinctrl-pic32.c+13−16

@@ -2202,7 +2202,7 @@ static int pic32_gpio_probe(struct platform_device *pdev) · 2201 unmodified lines
2202	2202	struct pic32_gpio_bank *bank;
2203	2203	u32 id;
2204	2204	int irq, ret;
2205		− struct resource *res;
	2205	+ struct gpio_irq_chip *girq;
2206	2206
2207	2207	if (of_property_read_u32(np, "microchip,gpio-bank", &id)) {
2208	2208	dev_err(&pdev->dev, "microchip,gpio-bank property not found\n");
@@ -2216,8 +2216,7 @@ static int pic32_gpio_probe(struct platform_device *pdev) · 7 unmodified lines
2216	2216
2217	2217	bank = &pic32_gpio_banks[id];
2218	2218
2219		− res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2220		− bank->reg_base = devm_ioremap_resource(&pdev->dev, res);
	2219	+ bank->reg_base = devm_platform_ioremap_resource(pdev, 0);
2221	2220	if (IS_ERR(bank->reg_base))
2222	2221	return PTR_ERR(bank->reg_base);
2223	2222
@@ -2240,25 +2239,23 @@ static int pic32_gpio_probe(struct platform_device *pdev) · 16 unmodified lines
2240	2239
2241	2240	bank->gpio_chip.parent = &pdev->dev;
2242	2241	bank->gpio_chip.of_node = np;
	2242	+ girq = &bank->gpio_chip.irq;
	2243	+ girq->chip = &bank->irq_chip;
	2244	+ girq->parent_handler = pic32_gpio_irq_handler;
	2245	+ girq->num_parents = 1;
	2246	+ girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents),
	2247	+ GFP_KERNEL);
	2248	+ if (!girq->parents)
	2249	+ return -ENOMEM;
	2250	+ girq->default_type = IRQ_TYPE_NONE;
	2251	+ girq->handler = handle_level_irq;
	2252	+ girq->parents[0] = irq;
2243	2253	ret = gpiochip_add_data(&bank->gpio_chip, bank);
2244	2254	if (ret < 0) {
2245	2255	dev_err(&pdev->dev, "Failed to add GPIO chip %u: %d\n",
2246	2256	id, ret);
2247	2257	return ret;
2248	2258	}
2249		−
2250		− ret = gpiochip_irqchip_add(&bank->gpio_chip, &bank->irq_chip,
2251		− 0, handle_level_irq, IRQ_TYPE_NONE);
2252		− if (ret < 0) {
2253		− dev_err(&pdev->dev, "Failed to add IRQ chip %u: %d\n",
2254		− id, ret);
2255		− gpiochip_remove(&bank->gpio_chip);
2256		− return ret;
2257		− }
2258		−
2259		− gpiochip_set_chained_irqchip(&bank->gpio_chip, &bank->irq_chip,
2260		− irq, pic32_gpio_irq_handler);
2261		−
2262	2259	return 0;
2263	2260	}
2264	2261

drivers/pinctrl/pinctrl-pistachio.c+17−13

@@ -1352,6 +1352,7 @@ static int pistachio_gpio_register(struct pistachio_pinctrl *pctl) · 1351 unmodified lines
1352	1352	for (i = 0; i < pctl->nbanks; i++) {
1353	1353	char child_name[sizeof("gpioXX")];
1354	1354	struct device_node *child;
	1355	+ struct gpio_irq_chip *girq;
1355	1356
1356	1357	snprintf(child_name, sizeof(child_name), "gpio%d", i);
1357	1358	child = of_get_child_by_name(node, child_name);
@@ -1383,23 +1384,28 @@ static int pistachio_gpio_register(struct pistachio_pinctrl *pctl) · 25 unmodified lines
1383	1384
1384	1385	bank->gpio_chip.parent = pctl->dev;
1385	1386	bank->gpio_chip.of_node = child;
1386		− ret = gpiochip_add_data(&bank->gpio_chip, bank);
1387		− if (ret < 0) {
1388		− dev_err(pctl->dev, "Failed to add GPIO chip %u: %d\n",
1389		− i, ret);
	1387	+
	1388	+ girq = &bank->gpio_chip.irq;
	1389	+ girq->chip = &bank->irq_chip;
	1390	+ girq->parent_handler = pistachio_gpio_irq_handler;
	1391	+ girq->num_parents = 1;
	1392	+ girq->parents = devm_kcalloc(pctl->dev, 1,
	1393	+ sizeof(*girq->parents),
	1394	+ GFP_KERNEL);
	1395	+ if (!girq->parents) {
	1396	+ ret = -ENOMEM;
1390	1397	goto err;
1391	1398	}
	1399	+ girq->parents[0] = irq;
	1400	+ girq->default_type = IRQ_TYPE_NONE;
	1401	+ girq->handler = handle_level_irq;
1392	1402
1393		− ret = gpiochip_irqchip_add(&bank->gpio_chip, &bank->irq_chip,
1394		− 0, handle_level_irq, IRQ_TYPE_NONE);
	1403	+ ret = gpiochip_add_data(&bank->gpio_chip, bank);
1395	1404	if (ret < 0) {
1396		− dev_err(pctl->dev, "Failed to add IRQ chip %u: %d\n",
	1405	+ dev_err(pctl->dev, "Failed to add GPIO chip %u: %d\n",
1397	1406	i, ret);
1398		− gpiochip_remove(&bank->gpio_chip);
1399	1407	goto err;
1400	1408	}
1401		− gpiochip_set_chained_irqchip(&bank->gpio_chip, &bank->irq_chip,
1402		− irq, pistachio_gpio_irq_handler);
1403	1409
1404	1410	ret = gpiochip_add_pin_range(&bank->gpio_chip,
1405	1411	dev_name(pctl->dev), 0,
@@ -1429,7 +1435,6 @@ static const struct of_device_id pistachio_pinctrl_of_match[] = { · 23 unmodified lines
1429	1435	static int pistachio_pinctrl_probe(struct platform_device *pdev)
1430	1436	{
1431	1437	struct pistachio_pinctrl *pctl;
1432		− struct resource *res;
1433	1438
1434	1439	pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
1435	1440	if (!pctl)
@@ -1437,8 +1442,7 @@ static int pistachio_pinctrl_probe(struct platform_device *pdev) · 1 unmodified line
1437	1442	pctl->dev = &pdev->dev;
1438	1443	dev_set_drvdata(&pdev->dev, pctl);
1439	1444
1440		− res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1441		− pctl->base = devm_ioremap_resource(&pdev->dev, res);
	1445	+ pctl->base = devm_platform_ioremap_resource(pdev, 0);
1442	1446	if (IS_ERR(pctl->base))
1443	1447	return PTR_ERR(pctl->base);
1444	1448

drivers/pinctrl/pinctrl-rockchip.c+381−1

@@ -58,6 +58,7 @@ enum rockchip_pinctrl_type { · 57 unmodified lines
58	58	RK3128,
59	59	RK3188,
60	60	RK3288,
	61	+ RK3308,
61	62	RK3368,
62	63	RK3399,
63	64	};
@@ -70,6 +71,7 @@ enum rockchip_pinctrl_type { · 6 unmodified lines
70	71	#define IOMUX_SOURCE_PMU BIT(2)
71	72	#define IOMUX_UNROUTED BIT(3)
72	73	#define IOMUX_WIDTH_3BIT BIT(4)
	74	+#define IOMUX_WIDTH_2BIT BIT(5)
73	75
74	76	/**
75	77	* @type: iomux variant using IOMUX_* constants
@@ -656,6 +658,100 @@ static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { · 580 unmodified lines
656	658	},
657	659	};
658	660
	661	+static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
	662	+ {
	663	+ .num = 1,
	664	+ .pin = 14,
	665	+ .reg = 0x28,
	666	+ .bit = 12,
	667	+ .mask = 0xf
	668	+ }, {
	669	+ .num = 1,
	670	+ .pin = 15,
	671	+ .reg = 0x2c,
	672	+ .bit = 0,
	673	+ .mask = 0x3
	674	+ }, {
	675	+ .num = 1,
	676	+ .pin = 18,
	677	+ .reg = 0x30,
	678	+ .bit = 4,
	679	+ .mask = 0xf
	680	+ }, {
	681	+ .num = 1,
	682	+ .pin = 19,
	683	+ .reg = 0x30,
	684	+ .bit = 8,
	685	+ .mask = 0xf
	686	+ }, {
	687	+ .num = 1,
	688	+ .pin = 20,
	689	+ .reg = 0x30,
	690	+ .bit = 12,
	691	+ .mask = 0xf
	692	+ }, {
	693	+ .num = 1,
	694	+ .pin = 21,
	695	+ .reg = 0x34,
	696	+ .bit = 0,
	697	+ .mask = 0xf
	698	+ }, {
	699	+ .num = 1,
	700	+ .pin = 22,
	701	+ .reg = 0x34,
	702	+ .bit = 4,
	703	+ .mask = 0xf
	704	+ }, {
	705	+ .num = 1,
	706	+ .pin = 23,
	707	+ .reg = 0x34,
	708	+ .bit = 8,
	709	+ .mask = 0xf
	710	+ }, {
	711	+ .num = 3,
	712	+ .pin = 12,
	713	+ .reg = 0x68,
	714	+ .bit = 8,
	715	+ .mask = 0xf
	716	+ }, {
	717	+ .num = 3,
	718	+ .pin = 13,
	719	+ .reg = 0x68,
	720	+ .bit = 12,
	721	+ .mask = 0xf
	722	+ }, {
	723	+ .num = 2,
	724	+ .pin = 2,
	725	+ .reg = 0x608,
	726	+ .bit = 0,
	727	+ .mask = 0x7
	728	+ }, {
	729	+ .num = 2,
	730	+ .pin = 3,
	731	+ .reg = 0x608,
	732	+ .bit = 4,
	733	+ .mask = 0x7
	734	+ }, {
	735	+ .num = 2,
	736	+ .pin = 16,
	737	+ .reg = 0x610,
	738	+ .bit = 8,
	739	+ .mask = 0x7
	740	+ }, {
	741	+ .num = 3,
	742	+ .pin = 10,
	743	+ .reg = 0x610,
	744	+ .bit = 0,
	745	+ .mask = 0x7
	746	+ }, {
	747	+ .num = 3,
	748	+ .pin = 11,
	749	+ .reg = 0x610,
	750	+ .bit = 4,
	751	+ .mask = 0x7
	752	+ },
	753	+};
	754	+
659	755	static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
660	756	{
661	757	.num = 2,
@@ -982,6 +1078,192 @@ static struct rockchip_mux_route_data rk3288_mux_route_data[] = { · 320 unmodified lines
982	1078	},
983	1079	};
984	1080
	1081	+static struct rockchip_mux_route_data rk3308_mux_route_data[] = {
	1082	+ {
	1083	+ /* rtc_clk */
	1084	+ .bank_num = 0,
	1085	+ .pin = 19,
	1086	+ .func = 1,
	1087	+ .route_offset = 0x314,
	1088	+ .route_val = BIT(16 + 0) \| BIT(0),
	1089	+ }, {
	1090	+ /* uart2_rxm0 */
	1091	+ .bank_num = 1,
	1092	+ .pin = 22,
	1093	+ .func = 2,
	1094	+ .route_offset = 0x314,
	1095	+ .route_val = BIT(16 + 2) \| BIT(16 + 3),
	1096	+ }, {
	1097	+ /* uart2_rxm1 */
	1098	+ .bank_num = 4,
	1099	+ .pin = 26,
	1100	+ .func = 2,
	1101	+ .route_offset = 0x314,
	1102	+ .route_val = BIT(16 + 2) \| BIT(16 + 3) \| BIT(2),
	1103	+ }, {
	1104	+ /* i2c3_sdam0 */
	1105	+ .bank_num = 0,
	1106	+ .pin = 15,
	1107	+ .func = 2,
	1108	+ .route_offset = 0x608,
	1109	+ .route_val = BIT(16 + 8) \| BIT(16 + 9),
	1110	+ }, {
	1111	+ /* i2c3_sdam1 */
	1112	+ .bank_num = 3,
	1113	+ .pin = 12,
	1114	+ .func = 2,
	1115	+ .route_offset = 0x608,
	1116	+ .route_val = BIT(16 + 8) \| BIT(16 + 9) \| BIT(8),
	1117	+ }, {
	1118	+ /* i2c3_sdam2 */
	1119	+ .bank_num = 2,
	1120	+ .pin = 0,
	1121	+ .func = 3,
	1122	+ .route_offset = 0x608,
	1123	+ .route_val = BIT(16 + 8) \| BIT(16 + 9) \| BIT(9),
	1124	+ }, {
	1125	+ /* i2s-8ch-1-sclktxm0 */
	1126	+ .bank_num = 1,
	1127	+ .pin = 3,
	1128	+ .func = 2,
	1129	+ .route_offset = 0x308,
	1130	+ .route_val = BIT(16 + 3),
	1131	+ }, {
	1132	+ /* i2s-8ch-1-sclkrxm0 */
	1133	+ .bank_num = 1,
	1134	+ .pin = 4,
	1135	+ .func = 2,
	1136	+ .route_offset = 0x308,
	1137	+ .route_val = BIT(16 + 3),
	1138	+ }, {
	1139	+ /* i2s-8ch-1-sclktxm1 */
	1140	+ .bank_num = 1,
	1141	+ .pin = 13,
	1142	+ .func = 2,
	1143	+ .route_offset = 0x308,
	1144	+ .route_val = BIT(16 + 3) \| BIT(3),
	1145	+ }, {
	1146	+ /* i2s-8ch-1-sclkrxm1 */
	1147	+ .bank_num = 1,
	1148	+ .pin = 14,
	1149	+ .func = 2,
	1150	+ .route_offset = 0x308,
	1151	+ .route_val = BIT(16 + 3) \| BIT(3),
	1152	+ }, {
	1153	+ /* pdm-clkm0 */
	1154	+ .bank_num = 1,
	1155	+ .pin = 4,
	1156	+ .func = 3,
	1157	+ .route_offset = 0x308,
	1158	+ .route_val = BIT(16 + 12) \| BIT(16 + 13),
	1159	+ }, {
	1160	+ /* pdm-clkm1 */
	1161	+ .bank_num = 1,
	1162	+ .pin = 14,
	1163	+ .func = 4,
	1164	+ .route_offset = 0x308,
	1165	+ .route_val = BIT(16 + 12) \| BIT(16 + 13) \| BIT(12),
	1166	+ }, {
	1167	+ /* pdm-clkm2 */
	1168	+ .bank_num = 2,
	1169	+ .pin = 6,
	1170	+ .func = 2,
	1171	+ .route_offset = 0x308,
	1172	+ .route_val = BIT(16 + 12) \| BIT(16 + 13) \| BIT(13),
	1173	+ }, {
	1174	+ /* pdm-clkm-m2 */
	1175	+ .bank_num = 2,
	1176	+ .pin = 4,
	1177	+ .func = 3,
	1178	+ .route_offset = 0x600,
	1179	+ .route_val = BIT(16 + 2) \| BIT(2),
	1180	+ }, {
	1181	+ /* spi1_miso */
	1182	+ .bank_num = 3,
	1183	+ .pin = 10,
	1184	+ .func = 3,
	1185	+ .route_offset = 0x314,
	1186	+ .route_val = BIT(16 + 9),
	1187	+ }, {
	1188	+ /* spi1_miso_m1 */
	1189	+ .bank_num = 2,
	1190	+ .pin = 4,
	1191	+ .func = 2,
	1192	+ .route_offset = 0x314,
	1193	+ .route_val = BIT(16 + 9) \| BIT(9),
	1194	+ }, {
	1195	+ /* owire_m0 */
	1196	+ .bank_num = 0,
	1197	+ .pin = 11,
	1198	+ .func = 3,
	1199	+ .route_offset = 0x314,
	1200	+ .route_val = BIT(16 + 10) \| BIT(16 + 11),
	1201	+ }, {
	1202	+ /* owire_m1 */
	1203	+ .bank_num = 1,
	1204	+ .pin = 22,
	1205	+ .func = 7,
	1206	+ .route_offset = 0x314,
	1207	+ .route_val = BIT(16 + 10) \| BIT(16 + 11) \| BIT(10),
	1208	+ }, {
	1209	+ /* owire_m2 */
	1210	+ .bank_num = 2,
	1211	+ .pin = 2,
	1212	+ .func = 5,
	1213	+ .route_offset = 0x314,
	1214	+ .route_val = BIT(16 + 10) \| BIT(16 + 11) \| BIT(11),
	1215	+ }, {
	1216	+ /* can_rxd_m0 */
	1217	+ .bank_num = 0,
	1218	+ .pin = 11,
	1219	+ .func = 2,
	1220	+ .route_offset = 0x314,
	1221	+ .route_val = BIT(16 + 12) \| BIT(16 + 13),
	1222	+ }, {
	1223	+ /* can_rxd_m1 */
	1224	+ .bank_num = 1,
	1225	+ .pin = 22,
	1226	+ .func = 5,
	1227	+ .route_offset = 0x314,
	1228	+ .route_val = BIT(16 + 12) \| BIT(16 + 13) \| BIT(12),
	1229	+ }, {
	1230	+ /* can_rxd_m2 */
	1231	+ .bank_num = 2,
	1232	+ .pin = 2,
	1233	+ .func = 4,
	1234	+ .route_offset = 0x314,
	1235	+ .route_val = BIT(16 + 12) \| BIT(16 + 13) \| BIT(13),
	1236	+ }, {
	1237	+ /* mac_rxd0_m0 */
	1238	+ .bank_num = 1,
	1239	+ .pin = 20,
	1240	+ .func = 3,
	1241	+ .route_offset = 0x314,
	1242	+ .route_val = BIT(16 + 14),
	1243	+ }, {
	1244	+ /* mac_rxd0_m1 */
	1245	+ .bank_num = 4,
	1246	+ .pin = 2,
	1247	+ .func = 2,
	1248	+ .route_offset = 0x314,
	1249	+ .route_val = BIT(16 + 14) \| BIT(14),
	1250	+ }, {
	1251	+ /* uart3_rx */
	1252	+ .bank_num = 3,
	1253	+ .pin = 12,
	1254	+ .func = 4,
	1255	+ .route_offset = 0x314,
	1256	+ .route_val = BIT(16 + 15),
	1257	+ }, {
	1258	+ /* uart3_rx_m1 */
	1259	+ .bank_num = 0,
	1260	+ .pin = 17,
	1261	+ .func = 3,
	1262	+ .route_offset = 0x314,
	1263	+ .route_val = BIT(16 + 15) \| BIT(15),
	1264	+ },
	1265	+};
	1266	+
985	1267	static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
986	1268	{
987	1269	/* uart2dbg_rxm0 */
@@ -1475,6 +1757,26 @@ static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, · 487 unmodified lines
1475	1757	return 0;
1476	1758	}
1477	1759
	1760	+#define RK3308_SCHMITT_PINS_PER_REG 8
	1761	+#define RK3308_SCHMITT_BANK_STRIDE 16
	1762	+#define RK3308_SCHMITT_GRF_OFFSET 0x1a0
	1763	+
	1764	+static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
	1765	+ int pin_num, struct regmap **regmap,
	1766	+ int reg, u8 bit)
	1767	+{
	1768	+ struct rockchip_pinctrl *info = bank->drvdata;
	1769	+
	1770	+ *regmap = info->regmap_base;
	1771	+ *reg = RK3308_SCHMITT_GRF_OFFSET;
	1772	+
	1773	+ reg += bank->bank_num RK3308_SCHMITT_BANK_STRIDE;
	1774	+ reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) 4);
	1775	+ *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG;
	1776	+
	1777	+ return 0;
	1778	+}
	1779	+
1478	1780	#define RK2928_PULL_OFFSET 0x118
1479	1781	#define RK2928_PULL_PINS_PER_REG 16
1480	1782	#define RK2928_PULL_BANK_STRIDE 8
@@ -1646,6 +1948,40 @@ static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, · 165 unmodified lines
1646	1948	bit = RK3288_DRV_BITS_PER_PIN;
1647	1949	}
1648	1950
	1951	+#define RK3308_PULL_OFFSET 0xa0
	1952	+
	1953	+static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
	1954	+ int pin_num, struct regmap **regmap,
	1955	+ int reg, u8 bit)
	1956	+{
	1957	+ struct rockchip_pinctrl *info = bank->drvdata;
	1958	+
	1959	+ *regmap = info->regmap_base;
	1960	+ *reg = RK3308_PULL_OFFSET;
	1961	+ reg += bank->bank_num RK3188_PULL_BANK_STRIDE;
	1962	+ reg += ((pin_num / RK3188_PULL_PINS_PER_REG) 4);
	1963	+
	1964	+ *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
	1965	+ bit = RK3188_PULL_BITS_PER_PIN;
	1966	+}
	1967	+
	1968	+#define RK3308_DRV_GRF_OFFSET 0x100
	1969	+
	1970	+static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
	1971	+ int pin_num, struct regmap **regmap,
	1972	+ int reg, u8 bit)
	1973	+{
	1974	+ struct rockchip_pinctrl *info = bank->drvdata;
	1975	+
	1976	+ *regmap = info->regmap_base;
	1977	+ *reg = RK3308_DRV_GRF_OFFSET;
	1978	+ reg += bank->bank_num RK3288_DRV_BANK_STRIDE;
	1979	+ reg += ((pin_num / RK3288_DRV_PINS_PER_REG) 4);
	1980	+
	1981	+ *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
	1982	+ bit = RK3288_DRV_BITS_PER_PIN;
	1983	+}
	1984	+
1649	1985	#define RK3368_PULL_GRF_OFFSET 0x100
1650	1986	#define RK3368_PULL_PMU_OFFSET 0x10
1651	1987
@@ -1986,6 +2322,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) · 334 unmodified lines
1986	2322	case RV1108:
1987	2323	case RK3188:
1988	2324	case RK3288:
	2325	+ case RK3308:
1989	2326	case RK3368:
1990	2327	case RK3399:
1991	2328	pull_type = bank->pull_type[pin_num / 8];
@@ -2030,6 +2367,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, · 38 unmodified lines
2030	2367	case RV1108:
2031	2368	case RK3188:
2032	2369	case RK3288:
	2370	+ case RK3308:
2033	2371	case RK3368:
2034	2372	case RK3399:
2035	2373	pull_type = bank->pull_type[pin_num / 8];
@@ -2293,6 +2631,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, · 257 unmodified lines
2293	2631	case RV1108:
2294	2632	case RK3188:
2295	2633	case RK3288:
	2634	+ case RK3308:
2296	2635	case RK3368:
2297	2636	case RK3399:
2298	2637	return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
@@ -3303,7 +3642,8 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( · 1004 unmodified lines
3303	3642	* 4bit iomux'es are spread over two registers.
3304	3643	*/
3305	3644	inc = (iom->type & (IOMUX_WIDTH_4BIT \|
3306		− IOMUX_WIDTH_3BIT)) ? 8 : 4;
	3645	+ IOMUX_WIDTH_3BIT \|
	3646	+ IOMUX_WIDTH_2BIT)) ? 8 : 4;
3307	3647	if (iom->type & IOMUX_SOURCE_PMU)
3308	3648	pmu_offs += inc;
3309	3649	else
@@ -3709,6 +4049,44 @@ static struct rockchip_pin_ctrl rk3288_pin_ctrl = { · 399 unmodified lines
3709	4049	.drv_calc_reg = rk3288_calc_drv_reg_and_bit,
3710	4050	};
3711	4051
	4052	+static struct rockchip_pin_bank rk3308_pin_banks[] = {
	4053	+ PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT,
	4054	+ IOMUX_WIDTH_2BIT,
	4055	+ IOMUX_WIDTH_2BIT,
	4056	+ IOMUX_WIDTH_2BIT),
	4057	+ PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_2BIT,
	4058	+ IOMUX_WIDTH_2BIT,
	4059	+ IOMUX_WIDTH_2BIT,
	4060	+ IOMUX_WIDTH_2BIT),
	4061	+ PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_2BIT,
	4062	+ IOMUX_WIDTH_2BIT,
	4063	+ IOMUX_WIDTH_2BIT,
	4064	+ IOMUX_WIDTH_2BIT),
	4065	+ PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_2BIT,
	4066	+ IOMUX_WIDTH_2BIT,
	4067	+ IOMUX_WIDTH_2BIT,
	4068	+ IOMUX_WIDTH_2BIT),
	4069	+ PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_2BIT,
	4070	+ IOMUX_WIDTH_2BIT,
	4071	+ IOMUX_WIDTH_2BIT,
	4072	+ IOMUX_WIDTH_2BIT),
	4073	+};
	4074	+
	4075	+static struct rockchip_pin_ctrl rk3308_pin_ctrl = {
	4076	+ .pin_banks = rk3308_pin_banks,
	4077	+ .nr_banks = ARRAY_SIZE(rk3308_pin_banks),
	4078	+ .label = "RK3308-GPIO",
	4079	+ .type = RK3308,
	4080	+ .grf_mux_offset = 0x0,
	4081	+ .iomux_recalced = rk3308_mux_recalced_data,
	4082	+ .niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data),
	4083	+ .iomux_routes = rk3308_mux_route_data,
	4084	+ .niomux_routes = ARRAY_SIZE(rk3308_mux_route_data),
	4085	+ .pull_calc_reg = rk3308_calc_pull_reg_and_bit,
	4086	+ .drv_calc_reg = rk3308_calc_drv_reg_and_bit,
	4087	+ .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit,
	4088	+};
	4089	+
3712	4090	static struct rockchip_pin_bank rk3328_pin_banks[] = {
3713	4091	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
3714	4092	PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
@@ -3849,6 +4227,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = { · 134 unmodified lines
3849	4227	.data = &rk3228_pin_ctrl },
3850	4228	{ .compatible = "rockchip,rk3288-pinctrl",
3851	4229	.data = &rk3288_pin_ctrl },
	4230	+ { .compatible = "rockchip,rk3308-pinctrl",
	4231	+ .data = &rk3308_pin_ctrl },
3852	4232	{ .compatible = "rockchip,rk3328-pinctrl",
3853	4233	.data = &rk3328_pin_ctrl },
3854	4234	{ .compatible = "rockchip,rk3368-pinctrl",

drivers/pinctrl/pinctrl-rza1.c+1−7

@@ -617,12 +617,6 @@ static void rza1_pin_reset(struct rza1_port *port, unsigned int pin) · 616 unmodified lines
617	617	spin_unlock_irqrestore(&port->lock, irqflags);
618	618	}
619	619
620		−static inline int rza1_pin_get_direction(struct rza1_port *port,
621		− unsigned int pin)
622		−{
623		− return !!rza1_get_bit(port, RZA1_PM_REG, pin);
624		−}
625		−
626	620	/**
627	621	* rza1_pin_set_direction() - set I/O direction on a pin in port mode
628	622	*
@@ -783,7 +777,7 @@ static int rza1_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio) · 154 unmodified lines
783	777	{
784	778	struct rza1_port *port = gpiochip_get_data(chip);
785	779
786		− return rza1_pin_get_direction(port, gpio);
	780	+ return !!rza1_get_bit(port, RZA1_PM_REG, gpio);
787	781	}
788	782
789	783	static int rza1_gpio_direction_input(struct gpio_chip *chip,

drivers/pinctrl/pinctrl-rza2.c+3−5

@@ -213,8 +213,8 @@ static const char * const rza2_gpio_names[] = { · 212 unmodified lines
213	213	"PC_0", "PC_1", "PC_2", "PC_3", "PC_4", "PC_5", "PC_6", "PC_7",
214	214	"PD_0", "PD_1", "PD_2", "PD_3", "PD_4", "PD_5", "PD_6", "PD_7",
215	215	"PE_0", "PE_1", "PE_2", "PE_3", "PE_4", "PE_5", "PE_6", "PE_7",
216		− "PF_0", "PF_1", "PF_2", "PF_3", "P0_4", "PF_5", "PF_6", "PF_7",
217		− "PG_0", "PG_1", "PG_2", "P0_3", "PG_4", "PG_5", "PG_6", "PG_7",
	216	+ "PF_0", "PF_1", "PF_2", "PF_3", "PF_4", "PF_5", "PF_6", "PF_7",
	217	+ "PG_0", "PG_1", "PG_2", "PG_3", "PG_4", "PG_5", "PG_6", "PG_7",
218	218	"PH_0", "PH_1", "PH_2", "PH_3", "PH_4", "PH_5", "PH_6", "PH_7",
219	219	/* port I does not exist */
220	220	"PJ_0", "PJ_1", "PJ_2", "PJ_3", "PJ_4", "PJ_5", "PJ_6", "PJ_7",
@@ -462,7 +462,6 @@ static const struct pinmux_ops rza2_pinmux_ops = { · 241 unmodified lines
462	462	static int rza2_pinctrl_probe(struct platform_device *pdev)
463	463	{
464	464	struct rza2_pinctrl_priv *priv;
465		− struct resource *res;
466	465	int ret;
467	466
468	467	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
@@ -471,8 +470,7 @@ static int rza2_pinctrl_probe(struct platform_device *pdev) · 2 unmodified lines
471	470
472	471	priv->dev = &pdev->dev;
473	472
474		− res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
475		− priv->base = devm_ioremap_resource(&pdev->dev, res);
	473	+ priv->base = devm_platform_ioremap_resource(pdev, 0);
476	474	if (IS_ERR(priv->base))
477	475	return PTR_ERR(priv->base);
478	476

drivers/pinctrl/pinctrl-rzn1.c+1−1

@@ -487,7 +487,7 @@ static int rzn1_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, · 486 unmodified lines
487	487	{
488	488	struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
489	489	enum pin_config_param param = pinconf_to_config_param(*config);
490		− const u32 reg_drive[4] = { 4, 6, 8, 12 };
	490	+ static const u32 reg_drive[4] = { 4, 6, 8, 12 };
491	491	u32 pull, drive, l1mux;
492	492	u32 l1, l2, arg = 0;
493	493

drivers/pinctrl/pinctrl-st.c+32−21

@@ -1477,7 +1477,7 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info, · 1476 unmodified lines
1477	1477	struct device *dev = info->dev;
1478	1478	int bank_num = of_alias_get_id(np, "gpio");
1479	1479	struct resource res, irq_res;
1480		− int gpio_irq = 0, err;
	1480	+ int err;
1481	1481
1482	1482	if (of_address_to_resource(np, 0, &res))
1483	1483	return -ENODEV;
@@ -1500,12 +1500,6 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info, · 16 unmodified lines
1500	1500	range->pin_base = range->base = range->id * ST_GPIO_PINS_PER_BANK;
1501	1501	range->npins = bank->gpio_chip.ngpio;
1502	1502	range->gc = &bank->gpio_chip;
1503		− err = gpiochip_add_data(&bank->gpio_chip, bank);
1504		− if (err) {
1505		− dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_num);
1506		− return err;
1507		− }
1508		− dev_info(dev, "%s bank added.\n", range->name);
1509	1503
1510	1504	/**
1511	1505	* GPIO bank can have one of the two possible types of
@@ -1527,23 +1521,40 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info, · 15 unmodified lines
1527	1521	*/
1528	1522
1529	1523	if (of_irq_to_resource(np, 0, &irq_res) > 0) {
1530		− gpio_irq = irq_res.start;
1531		− gpiochip_set_chained_irqchip(&bank->gpio_chip, &st_gpio_irqchip,
1532		− gpio_irq, st_gpio_irq_handler);
1533		− }
	1524	+ struct gpio_irq_chip *girq;
	1525	+ int gpio_irq = irq_res.start;
1534	1526
1535		− if (info->irqmux_base \|\| gpio_irq > 0) {
1536		− err = gpiochip_irqchip_add(&bank->gpio_chip, &st_gpio_irqchip,
1537		− 0, handle_simple_irq,
1538		− IRQ_TYPE_NONE);
1539		− if (err) {
1540		− gpiochip_remove(&bank->gpio_chip);
1541		− dev_info(dev, "could not add irqchip\n");
1542		− return err;
	1527	+ /* This is not a valid IRQ */
	1528	+ if (gpio_irq <= 0) {
	1529	+ dev_err(dev, "invalid IRQ for %pOF bank\n", np);
	1530	+ goto skip_irq;
1543	1531	}
1544		− } else {
1545		− dev_info(dev, "No IRQ support for %pOF bank\n", np);
	1532	+ /* We need to have a mux as well */
	1533	+ if (!info->irqmux_base) {
	1534	+ dev_err(dev, "no irqmux for %pOF bank\n", np);
	1535	+ goto skip_irq;
	1536	+ }
	1537	+
	1538	+ girq = &bank->gpio_chip.irq;
	1539	+ girq->chip = &st_gpio_irqchip;
	1540	+ girq->parent_handler = st_gpio_irq_handler;
	1541	+ girq->num_parents = 1;
	1542	+ girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
	1543	+ GFP_KERNEL);
	1544	+ if (!girq->parents)
	1545	+ return -ENOMEM;
	1546	+ girq->parents[0] = gpio_irq;
	1547	+ girq->default_type = IRQ_TYPE_NONE;
	1548	+ girq->handler = handle_simple_irq;
	1549	+ }
	1550	+
	1551	+skip_irq:
	1552	+ err = gpiochip_add_data(&bank->gpio_chip, bank);
	1553	+ if (err) {
	1554	+ dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_num);
	1555	+ return err;
1546	1556	}
	1557	+ dev_info(dev, "%s bank added.\n", range->name);
1547	1558
1548	1559	return 0;
1549	1560	}

drivers/pinctrl/pinctrl-stmfx.c+21−0

@@ -505,6 +505,25 @@ static void stmfx_pinctrl_irq_bus_sync_unlock(struct irq_data *data) · 504 unmodified lines
505	505	mutex_unlock(&pctl->lock);
506	506	}
507	507
	508	+static int stmfx_gpio_irq_request_resources(struct irq_data *data)
	509	+{
	510	+ struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
	511	+ int ret;
	512	+
	513	+ ret = stmfx_gpio_direction_input(gpio_chip, data->hwirq);
	514	+ if (ret)
	515	+ return ret;
	516	+
	517	+ return gpiochip_reqres_irq(gpio_chip, data->hwirq);
	518	+}
	519	+
	520	+static void stmfx_gpio_irq_release_resources(struct irq_data *data)
	521	+{
	522	+ struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
	523	+
	524	+ return gpiochip_relres_irq(gpio_chip, data->hwirq);
	525	+}
	526	+
508	527	static void stmfx_pinctrl_irq_toggle_trigger(struct stmfx_pinctrl *pctl,
509	528	unsigned int offset)
510	529	{
@@ -664,6 +683,8 @@ static int stmfx_pinctrl_probe(struct platform_device *pdev) · 153 unmodified lines
664	683	pctl->irq_chip.irq_set_type = stmfx_pinctrl_irq_set_type;
665	684	pctl->irq_chip.irq_bus_lock = stmfx_pinctrl_irq_bus_lock;
666	685	pctl->irq_chip.irq_bus_sync_unlock = stmfx_pinctrl_irq_bus_sync_unlock;
	686	+ pctl->irq_chip.irq_request_resources = stmfx_gpio_irq_request_resources;
	687	+ pctl->irq_chip.irq_release_resources = stmfx_gpio_irq_release_resources;
667	688
668	689	ret = gpiochip_irqchip_add_nested(&pctl->gpio_chip, &pctl->irq_chip,
669	690	0, handle_bad_irq, IRQ_TYPE_NONE);

drivers/pinctrl/pinctrl-tb10x.c+1−3

@@ -747,7 +747,6 @@ static struct pinctrl_desc tb10x_pindesc = { · 746 unmodified lines
747	747	static int tb10x_pinctrl_probe(struct platform_device *pdev)
748	748	{
749	749	int ret = -EINVAL;
750		− struct resource *mem;
751	750	struct device *dev = &pdev->dev;
752	751	struct device_node *of_node = dev->of_node;
753	752	struct device_node *child;
@@ -768,8 +767,7 @@ static int tb10x_pinctrl_probe(struct platform_device *pdev) · 14 unmodified lines
768	767	platform_set_drvdata(pdev, state);
769	768	mutex_init(&state->mutex);
770	769
771		− mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
772		− state->base = devm_ioremap_resource(dev, mem);
	770	+ state->base = devm_platform_ioremap_resource(pdev, 0);
773	771	if (IS_ERR(state->base)) {
774	772	ret = PTR_ERR(state->base);
775	773	goto fail;

drivers/pinctrl/pinctrl-u300.c+1−3

@@ -1055,7 +1055,6 @@ static struct pinctrl_desc u300_pmx_desc = { · 1054 unmodified lines
1055	1055	static int u300_pmx_probe(struct platform_device *pdev)
1056	1056	{
1057	1057	struct u300_pmx *upmx;
1058		− struct resource *res;
1059	1058
1060	1059	/* Create state holders etc for this driver */
1061	1060	upmx = devm_kzalloc(&pdev->dev, sizeof(*upmx), GFP_KERNEL);
@@ -1064,8 +1063,7 @@ static int u300_pmx_probe(struct platform_device *pdev) · 2 unmodified lines
1064	1063
1065	1064	upmx->dev = &pdev->dev;
1066	1065
1067		− res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1068		− upmx->virtbase = devm_ioremap_resource(&pdev->dev, res);
	1066	+ upmx->virtbase = devm_platform_ioremap_resource(pdev, 0);
1069	1067	if (IS_ERR(upmx->virtbase))
1070	1068	return PTR_ERR(upmx->virtbase);
1071	1069

drivers/pinctrl/pinctrl-xway.c+1−3

@@ -1705,12 +1705,10 @@ static int pinmux_xway_probe(struct platform_device *pdev) · 1704 unmodified lines
1705	1705	{
1706	1706	const struct of_device_id *match;
1707	1707	const struct pinctrl_xway_soc *xway_soc;
1708		− struct resource *res;
1709	1708	int ret, i;
1710	1709
1711	1710	/* get and remap our register range */
1712		− res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1713		− xway_info.membase[0] = devm_ioremap_resource(&pdev->dev, res);
	1711	+ xway_info.membase[0] = devm_platform_ioremap_resource(pdev, 0);
1714	1712	if (IS_ERR(xway_info.membase[0]))
1715	1713	return PTR_ERR(xway_info.membase[0]);
1716	1714

drivers/pinctrl/pxa/pinctrl-pxa25x.c+4−9

@@ -216,25 +216,20 @@ static int pxa25x_pinctrl_probe(struct platform_device *pdev) · 215 unmodified lines
216	216	void __iomem *base_af[8];
217	217	void __iomem *base_dir[4];
218	218	void __iomem *base_sleep[4];
219		− struct resource *res;
220	219
221		− res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
222		− base_af[0] = devm_ioremap_resource(&pdev->dev, res);
	220	+ base_af[0] = devm_platform_ioremap_resource(pdev, 0);
223	221	if (IS_ERR(base_af[0]))
224	222	return PTR_ERR(base_af[0]);
225	223
226		− res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
227		− base_dir[0] = devm_ioremap_resource(&pdev->dev, res);
	224	+ base_dir[0] = devm_platform_ioremap_resource(pdev, 1);
228	225	if (IS_ERR(base_dir[0]))
229	226	return PTR_ERR(base_dir[0]);
230	227
231		− res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
232		− base_dir[3] = devm_ioremap_resource(&pdev->dev, res);
	228	+ base_dir[3] = devm_platform_ioremap_resource(pdev, 2);
233	229	if (IS_ERR(base_dir[3]))
234	230	return PTR_ERR(base_dir[3]);
235	231
236		− res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
237		− base_sleep[0] = devm_ioremap_resource(&pdev->dev, res);
	232	+ base_sleep[0] = devm_platform_ioremap_resource(pdev, 3);
238	233	if (IS_ERR(base_sleep[0]))
239	234	return PTR_ERR(base_sleep[0]);
240	235

drivers/pinctrl/pxa/pinctrl-pxa27x.c+4−9

@@ -508,25 +508,20 @@ static int pxa27x_pinctrl_probe(struct platform_device *pdev) · 507 unmodified lines
508	508	void __iomem *base_af[8];
509	509	void __iomem *base_dir[4];
510	510	void __iomem *base_sleep[4];
511		− struct resource *res;
512	511
513		− res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
514		− base_af[0] = devm_ioremap_resource(&pdev->dev, res);
	512	+ base_af[0] = devm_platform_ioremap_resource(pdev, 0);
515	513	if (IS_ERR(base_af[0]))
516	514	return PTR_ERR(base_af[0]);
517	515
518		− res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
519		− base_dir[0] = devm_ioremap_resource(&pdev->dev, res);
	516	+ base_dir[0] = devm_platform_ioremap_resource(pdev, 1);
520	517	if (IS_ERR(base_dir[0]))
521	518	return PTR_ERR(base_dir[0]);
522	519
523		− res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
524		− base_dir[3] = devm_ioremap_resource(&pdev->dev, res);
	520	+ base_dir[3] = devm_platform_ioremap_resource(pdev, 2);
525	521	if (IS_ERR(base_dir[3]))
526	522	return PTR_ERR(base_dir[3]);
527	523
528		− res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
529		− base_sleep[0] = devm_ioremap_resource(&pdev->dev, res);
	524	+ base_sleep[0] = devm_platform_ioremap_resource(pdev, 3);
530	525	if (IS_ERR(base_sleep[0]))
531	526	return PTR_ERR(base_sleep[0]);
532	527

drivers/pinctrl/qcom/Kconfig+56−45

@@ -90,6 +90,16 @@ config PINCTRL_MSM8916 · 89 unmodified lines
90	90	This is the pinctrl, pinmux, pinconf and gpiolib driver for the
91	91	Qualcomm TLMM block found on the Qualcomm 8916 platform.
92	92
	93	+config PINCTRL_MSM8976
	94	+ tristate "Qualcomm 8976 pin controller driver"
	95	+ depends on GPIOLIB && OF
	96	+ select PINCTRL_MSM
	97	+ help
	98	+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
	99	+ Qualcomm TLMM block found on the Qualcomm MSM8976 platform.
	100	+ The Qualcomm MSM8956, APQ8056, APQ8076 platforms are also
	101	+ supported by this driver.
	102	+
93	103	config PINCTRL_MSM8994
94	104	tristate "Qualcomm 8994 pin controller driver"
95	105	depends on GPIOLIB && OF
@@ -132,32 +142,33 @@ config PINCTRL_QDF2XXX · 36 unmodified lines
132	142	Qualcomm Technologies QDF2xxx SOCs.
133	143
134	144	config PINCTRL_QCOM_SPMI_PMIC
135		− tristate "Qualcomm SPMI PMIC pin controller driver"
136		− depends on GPIOLIB && OF && SPMI
137		− select REGMAP_SPMI
138		− select PINMUX
139		− select PINCONF
140		− select GENERIC_PINCONF
141		− select GPIOLIB_IRQCHIP
142		− select IRQ_DOMAIN_HIERARCHY
143		− help
144		− This is the pinctrl, pinmux, pinconf and gpiolib driver for the
145		− Qualcomm GPIO and MPP blocks found in the Qualcomm PMIC's chips,
146		− which are using SPMI for communication with SoC. Example PMIC's
147		− devices are pm8841, pm8941 and pma8084.
	145	+ tristate "Qualcomm SPMI PMIC pin controller driver"
	146	+ depends on GPIOLIB && OF && SPMI
	147	+ select REGMAP_SPMI
	148	+ select PINMUX
	149	+ select PINCONF
	150	+ select GENERIC_PINCONF
	151	+ select GPIOLIB_IRQCHIP
	152	+ select IRQ_DOMAIN_HIERARCHY
	153	+ help
	154	+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
	155	+ Qualcomm GPIO and MPP blocks found in the Qualcomm PMIC's chips,
	156	+ which are using SPMI for communication with SoC. Example PMIC's
	157	+ devices are pm8841, pm8941 and pma8084.
148	158
149	159	config PINCTRL_QCOM_SSBI_PMIC
150		− tristate "Qualcomm SSBI PMIC pin controller driver"
151		− depends on GPIOLIB && OF
152		− select PINMUX
153		− select PINCONF
154		− select GENERIC_PINCONF
155		− select IRQ_DOMAIN_HIERARCHY
156		− help
157		− This is the pinctrl, pinmux, pinconf and gpiolib driver for the
158		− Qualcomm GPIO and MPP blocks found in the Qualcomm PMIC's chips,
159		− which are using SSBI for communication with SoC. Example PMIC's
160		− devices are pm8058 and pm8921.
	160	+ tristate "Qualcomm SSBI PMIC pin controller driver"
	161	+ depends on GPIOLIB && OF
	162	+ select PINMUX
	163	+ select PINCONF
	164	+ select GENERIC_PINCONF
	165	+ select GPIOLIB_IRQCHIP
	166	+ select IRQ_DOMAIN_HIERARCHY
	167	+ help
	168	+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
	169	+ Qualcomm GPIO and MPP blocks found in the Qualcomm PMIC's chips,
	170	+ which are using SSBI for communication with SoC. Example PMIC's
	171	+ devices are pm8058 and pm8921.
161	172
162	173	config PINCTRL_SC7180
163	174	tristate "Qualcomm Technologies Inc SC7180 pin controller driver"
@@ -169,30 +180,30 @@ config PINCTRL_SC7180 · 5 unmodified lines
169	180	Technologies Inc SC7180 platform.
170	181
171	182	config PINCTRL_SDM660
172		− tristate "Qualcomm Technologies Inc SDM660 pin controller driver"
173		− depends on GPIOLIB && OF
174		− select PINCTRL_MSM
175		− help
176		− This is the pinctrl, pinmux, pinconf and gpiolib driver for the
177		− Qualcomm Technologies Inc TLMM block found on the Qualcomm
178		− Technologies Inc SDM660 platform.
	183	+ tristate "Qualcomm Technologies Inc SDM660 pin controller driver"
	184	+ depends on GPIOLIB && OF
	185	+ select PINCTRL_MSM
	186	+ help
	187	+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
	188	+ Qualcomm Technologies Inc TLMM block found on the Qualcomm
	189	+ Technologies Inc SDM660 platform.
179	190
180	191	config PINCTRL_SDM845
181		− tristate "Qualcomm Technologies Inc SDM845 pin controller driver"
182		− depends on GPIOLIB && (OF \|\| ACPI)
183		− select PINCTRL_MSM
184		− help
185		− This is the pinctrl, pinmux, pinconf and gpiolib driver for the
186		− Qualcomm Technologies Inc TLMM block found on the Qualcomm
187		− Technologies Inc SDM845 platform.
	192	+ tristate "Qualcomm Technologies Inc SDM845 pin controller driver"
	193	+ depends on GPIOLIB && (OF \|\| ACPI)
	194	+ select PINCTRL_MSM
	195	+ help
	196	+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
	197	+ Qualcomm Technologies Inc TLMM block found on the Qualcomm
	198	+ Technologies Inc SDM845 platform.
188	199
189	200	config PINCTRL_SM8150
190		− tristate "Qualcomm Technologies Inc SM8150 pin controller driver"
191		− depends on GPIOLIB && OF
192		− select PINCTRL_MSM
193		− help
194		− This is the pinctrl, pinmux, pinconf and gpiolib driver for the
195		− Qualcomm Technologies Inc TLMM block found on the Qualcomm
196		− Technologies Inc SM8150 platform.
	201	+ tristate "Qualcomm Technologies Inc SM8150 pin controller driver"
	202	+ depends on GPIOLIB && OF
	203	+ select PINCTRL_MSM
	204	+ help
	205	+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
	206	+ Qualcomm Technologies Inc TLMM block found on the Qualcomm
	207	+ Technologies Inc SM8150 platform.
197	208
198	209	endif

drivers/pinctrl/qcom/Makefile+1−0

@@ -10,6 +10,7 @@ obj-$(CONFIG_PINCTRL_MSM8660) += pinctrl-msm8660.o · 9 unmodified lines
10	10	obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o
11	11	obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o
12	12	obj-$(CONFIG_PINCTRL_MSM8916) += pinctrl-msm8916.o
	13	+obj-$(CONFIG_PINCTRL_MSM8976) += pinctrl-msm8976.o
13	14	obj-$(CONFIG_PINCTRL_MSM8994) += pinctrl-msm8994.o
14	15	obj-$(CONFIG_PINCTRL_MSM8996) += pinctrl-msm8996.o
15	16	obj-$(CONFIG_PINCTRL_MSM8998) += pinctrl-msm8998.o

drivers/pinctrl/qcom/pinctrl-msm.c+1−2

@@ -1150,8 +1150,7 @@ int msm_pinctrl_probe(struct platform_device *pdev, · 1149 unmodified lines
1150	1150	return PTR_ERR(pctrl->regs[i]);
1151	1151	}
1152	1152	} else {
1153		− res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1154		− pctrl->regs[0] = devm_ioremap_resource(&pdev->dev, res);
	1153	+ pctrl->regs[0] = devm_platform_ioremap_resource(pdev, 0);
1155	1154	if (IS_ERR(pctrl->regs[0]))
1156	1155	return PTR_ERR(pctrl->regs[0]);
1157	1156	}

drivers/pinctrl/qcom/pinctrl-msm8976.c+1127−0

@@ -0,0 +1,1127 @@
	1	+// SPDX-License-Identifier: GPL-2.0
	2	+/*
	3	+ * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
	4	+ *
	5	+ * Copyright (c) 2016, AngeloGioacchino Del Regno <kholk11@gmail.com>
	6	+ */
	7	+
	8	+#include <linux/module.h>
	9	+#include <linux/of.h>
	10	+#include <linux/platform_device.h>
	11	+#include <linux/pinctrl/pinctrl.h>
	12	+
	13	+#include "pinctrl-msm.h"
	14	+
	15	+#define FUNCTION(fname) \
	16	+ [msm_mux_##fname] = { \
	17	+ .name = #fname, \
	18	+ .groups = fname##_groups, \
	19	+ .ngroups = ARRAY_SIZE(fname##_groups), \
	20	+ }
	21	+
	22	+#define REG_BASE 0x0
	23	+#define REG_SIZE 0x1000
	24	+#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
	25	+ { \
	26	+ .name = "gpio" #id, \
	27	+ .pins = gpio##id##_pins, \
	28	+ .npins = ARRAY_SIZE(gpio##id##_pins), \
	29	+ .funcs = (int[]){ \
	30	+ msm_mux_gpio, /* gpio mode */ \
	31	+ msm_mux_##f1, \
	32	+ msm_mux_##f2, \
	33	+ msm_mux_##f3, \
	34	+ msm_mux_##f4, \
	35	+ msm_mux_##f5, \
	36	+ msm_mux_##f6, \
	37	+ msm_mux_##f7, \
	38	+ msm_mux_##f8, \
	39	+ msm_mux_##f9 \
	40	+ }, \
	41	+ .nfuncs = 10, \
	42	+ .ctl_reg = REG_BASE + REG_SIZE * id, \
	43	+ .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \
	44	+ .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
	45	+ .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \
	46	+ .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
	47	+ .mux_bit = 2, \
	48	+ .pull_bit = 0, \
	49	+ .drv_bit = 6, \
	50	+ .oe_bit = 9, \
	51	+ .in_bit = 0, \
	52	+ .out_bit = 1, \
	53	+ .intr_enable_bit = 0, \
	54	+ .intr_status_bit = 0, \
	55	+ .intr_target_bit = 5, \
	56	+ .intr_target_kpss_val = 4, \
	57	+ .intr_raw_status_bit = 4, \
	58	+ .intr_polarity_bit = 1, \
	59	+ .intr_detection_bit = 2, \
	60	+ .intr_detection_width = 2, \
	61	+ }
	62	+
	63	+#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
	64	+ { \
	65	+ .name = #pg_name, \
	66	+ .pins = pg_name##_pins, \
	67	+ .npins = ARRAY_SIZE(pg_name##_pins), \
	68	+ .ctl_reg = ctl, \
	69	+ .io_reg = 0, \
	70	+ .intr_cfg_reg = 0, \
	71	+ .intr_status_reg = 0, \
	72	+ .intr_target_reg = 0, \
	73	+ .mux_bit = -1, \
	74	+ .pull_bit = pull, \
	75	+ .drv_bit = drv, \
	76	+ .oe_bit = -1, \
	77	+ .in_bit = -1, \
	78	+ .out_bit = -1, \
	79	+ .intr_enable_bit = -1, \
	80	+ .intr_status_bit = -1, \
	81	+ .intr_target_bit = -1, \
	82	+ .intr_raw_status_bit = -1, \
	83	+ .intr_polarity_bit = -1, \
	84	+ .intr_detection_bit = -1, \
	85	+ .intr_detection_width = -1, \
	86	+ }
	87	+static const struct pinctrl_pin_desc msm8976_pins[] = {
	88	+ PINCTRL_PIN(0, "GPIO_0"),
	89	+ PINCTRL_PIN(1, "GPIO_1"),
	90	+ PINCTRL_PIN(2, "GPIO_2"),
	91	+ PINCTRL_PIN(3, "GPIO_3"),
	92	+ PINCTRL_PIN(4, "GPIO_4"),
	93	+ PINCTRL_PIN(5, "GPIO_5"),
	94	+ PINCTRL_PIN(6, "GPIO_6"),
	95	+ PINCTRL_PIN(7, "GPIO_7"),
	96	+ PINCTRL_PIN(8, "GPIO_8"),
	97	+ PINCTRL_PIN(9, "GPIO_9"),
	98	+ PINCTRL_PIN(10, "GPIO_10"),
	99	+ PINCTRL_PIN(11, "GPIO_11"),
	100	+ PINCTRL_PIN(12, "GPIO_12"),
	101	+ PINCTRL_PIN(13, "GPIO_13"),
	102	+ PINCTRL_PIN(14, "GPIO_14"),
	103	+ PINCTRL_PIN(15, "GPIO_15"),
	104	+ PINCTRL_PIN(16, "GPIO_16"),
	105	+ PINCTRL_PIN(17, "GPIO_17"),
	106	+ PINCTRL_PIN(18, "GPIO_18"),
	107	+ PINCTRL_PIN(19, "GPIO_19"),
	108	+ PINCTRL_PIN(20, "GPIO_20"),
	109	+ PINCTRL_PIN(21, "GPIO_21"),
	110	+ PINCTRL_PIN(22, "GPIO_22"),
	111	+ PINCTRL_PIN(23, "GPIO_23"),
	112	+ PINCTRL_PIN(24, "GPIO_24"),
	113	+ PINCTRL_PIN(25, "GPIO_25"),
	114	+ PINCTRL_PIN(26, "GPIO_26"),
	115	+ PINCTRL_PIN(27, "GPIO_27"),
	116	+ PINCTRL_PIN(28, "GPIO_28"),
	117	+ PINCTRL_PIN(29, "GPIO_29"),
	118	+ PINCTRL_PIN(30, "GPIO_30"),
	119	+ PINCTRL_PIN(31, "GPIO_31"),
	120	+ PINCTRL_PIN(32, "GPIO_32"),
	121	+ PINCTRL_PIN(33, "GPIO_33"),
	122	+ PINCTRL_PIN(34, "GPIO_34"),
	123	+ PINCTRL_PIN(35, "GPIO_35"),
	124	+ PINCTRL_PIN(36, "GPIO_36"),
	125	+ PINCTRL_PIN(37, "GPIO_37"),
	126	+ PINCTRL_PIN(38, "GPIO_38"),
	127	+ PINCTRL_PIN(39, "GPIO_39"),
	128	+ PINCTRL_PIN(40, "GPIO_40"),
	129	+ PINCTRL_PIN(41, "GPIO_41"),
	130	+ PINCTRL_PIN(42, "GPIO_42"),
	131	+ PINCTRL_PIN(43, "GPIO_43"),
	132	+ PINCTRL_PIN(44, "GPIO_44"),
	133	+ PINCTRL_PIN(45, "GPIO_45"),
	134	+ PINCTRL_PIN(46, "GPIO_46"),
	135	+ PINCTRL_PIN(47, "GPIO_47"),
	136	+ PINCTRL_PIN(48, "GPIO_48"),
	137	+ PINCTRL_PIN(49, "GPIO_49"),
	138	+ PINCTRL_PIN(50, "GPIO_50"),
	139	+ PINCTRL_PIN(51, "GPIO_51"),
	140	+ PINCTRL_PIN(52, "GPIO_52"),
	141	+ PINCTRL_PIN(53, "GPIO_53"),
	142	+ PINCTRL_PIN(54, "GPIO_54"),
	143	+ PINCTRL_PIN(55, "GPIO_55"),
	144	+ PINCTRL_PIN(56, "GPIO_56"),
	145	+ PINCTRL_PIN(57, "GPIO_57"),
	146	+ PINCTRL_PIN(58, "GPIO_58"),
	147	+ PINCTRL_PIN(59, "GPIO_59"),
	148	+ PINCTRL_PIN(60, "GPIO_60"),
	149	+ PINCTRL_PIN(61, "GPIO_61"),
	150	+ PINCTRL_PIN(62, "GPIO_62"),
	151	+ PINCTRL_PIN(63, "GPIO_63"),
	152	+ PINCTRL_PIN(64, "GPIO_64"),
	153	+ PINCTRL_PIN(65, "GPIO_65"),
	154	+ PINCTRL_PIN(66, "GPIO_66"),
	155	+ PINCTRL_PIN(67, "GPIO_67"),
	156	+ PINCTRL_PIN(68, "GPIO_68"),
	157	+ PINCTRL_PIN(69, "GPIO_69"),
	158	+ PINCTRL_PIN(70, "GPIO_70"),
	159	+ PINCTRL_PIN(71, "GPIO_71"),
	160	+ PINCTRL_PIN(72, "GPIO_72"),
	161	+ PINCTRL_PIN(73, "GPIO_73"),
	162	+ PINCTRL_PIN(74, "GPIO_74"),
	163	+ PINCTRL_PIN(75, "GPIO_75"),
	164	+ PINCTRL_PIN(76, "GPIO_76"),
	165	+ PINCTRL_PIN(77, "GPIO_77"),
	166	+ PINCTRL_PIN(78, "GPIO_78"),
	167	+ PINCTRL_PIN(79, "GPIO_79"),
	168	+ PINCTRL_PIN(80, "GPIO_80"),
	169	+ PINCTRL_PIN(81, "GPIO_81"),
	170	+ PINCTRL_PIN(82, "GPIO_82"),
	171	+ PINCTRL_PIN(83, "GPIO_83"),
	172	+ PINCTRL_PIN(84, "GPIO_84"),
	173	+ PINCTRL_PIN(85, "GPIO_85"),
	174	+ PINCTRL_PIN(86, "GPIO_86"),
	175	+ PINCTRL_PIN(87, "GPIO_87"),
	176	+ PINCTRL_PIN(88, "GPIO_88"),
	177	+ PINCTRL_PIN(89, "GPIO_89"),
	178	+ PINCTRL_PIN(90, "GPIO_90"),
	179	+ PINCTRL_PIN(91, "GPIO_91"),
	180	+ PINCTRL_PIN(92, "GPIO_92"),
	181	+ PINCTRL_PIN(93, "GPIO_93"),
	182	+ PINCTRL_PIN(94, "GPIO_94"),
	183	+ PINCTRL_PIN(95, "GPIO_95"),
	184	+ PINCTRL_PIN(96, "GPIO_96"),
	185	+ PINCTRL_PIN(97, "GPIO_97"),
	186	+ PINCTRL_PIN(98, "GPIO_98"),
	187	+ PINCTRL_PIN(99, "GPIO_99"),
	188	+ PINCTRL_PIN(100, "GPIO_100"),
	189	+ PINCTRL_PIN(101, "GPIO_101"),
	190	+ PINCTRL_PIN(102, "GPIO_102"),
	191	+ PINCTRL_PIN(103, "GPIO_103"),
	192	+ PINCTRL_PIN(104, "GPIO_104"),
	193	+ PINCTRL_PIN(105, "GPIO_105"),
	194	+ PINCTRL_PIN(106, "GPIO_106"),
	195	+ PINCTRL_PIN(107, "GPIO_107"),
	196	+ PINCTRL_PIN(108, "GPIO_108"),
	197	+ PINCTRL_PIN(109, "GPIO_109"),
	198	+ PINCTRL_PIN(110, "GPIO_110"),
	199	+ PINCTRL_PIN(111, "GPIO_111"),
	200	+ PINCTRL_PIN(112, "GPIO_112"),
	201	+ PINCTRL_PIN(113, "GPIO_113"),
	202	+ PINCTRL_PIN(114, "GPIO_114"),
	203	+ PINCTRL_PIN(115, "GPIO_115"),
	204	+ PINCTRL_PIN(116, "GPIO_116"),
	205	+ PINCTRL_PIN(117, "GPIO_117"),
	206	+ PINCTRL_PIN(118, "GPIO_118"),
	207	+ PINCTRL_PIN(119, "GPIO_119"),
	208	+ PINCTRL_PIN(120, "GPIO_120"),
	209	+ PINCTRL_PIN(121, "GPIO_121"),
	210	+ PINCTRL_PIN(122, "GPIO_122"),
	211	+ PINCTRL_PIN(123, "GPIO_123"),
	212	+ PINCTRL_PIN(124, "GPIO_124"),
	213	+ PINCTRL_PIN(125, "GPIO_125"),
	214	+ PINCTRL_PIN(126, "GPIO_126"),
	215	+ PINCTRL_PIN(127, "GPIO_127"),
	216	+ PINCTRL_PIN(128, "GPIO_128"),
	217	+ PINCTRL_PIN(129, "GPIO_129"),
	218	+ PINCTRL_PIN(130, "GPIO_130"),
	219	+ PINCTRL_PIN(131, "GPIO_131"),
	220	+ PINCTRL_PIN(132, "GPIO_132"),
	221	+ PINCTRL_PIN(133, "GPIO_133"),
	222	+ PINCTRL_PIN(134, "GPIO_134"),
	223	+ PINCTRL_PIN(135, "GPIO_135"),
	224	+ PINCTRL_PIN(136, "GPIO_136"),
	225	+ PINCTRL_PIN(137, "GPIO_137"),
	226	+ PINCTRL_PIN(138, "GPIO_138"),
	227	+ PINCTRL_PIN(139, "GPIO_139"),
	228	+ PINCTRL_PIN(140, "GPIO_140"),
	229	+ PINCTRL_PIN(141, "GPIO_141"),
	230	+ PINCTRL_PIN(142, "GPIO_142"),
	231	+ PINCTRL_PIN(143, "GPIO_143"),
	232	+ PINCTRL_PIN(144, "GPIO_144"),
	233	+ PINCTRL_PIN(145, "SDC1_CLK"),
	234	+ PINCTRL_PIN(146, "SDC1_CMD"),
	235	+ PINCTRL_PIN(147, "SDC1_DATA"),
	236	+ PINCTRL_PIN(148, "SDC1_RCLK"),
	237	+ PINCTRL_PIN(149, "SDC2_CLK"),
	238	+ PINCTRL_PIN(150, "SDC2_CMD"),
	239	+ PINCTRL_PIN(151, "SDC2_DATA"),
	240	+ PINCTRL_PIN(152, "QDSD_CLK"),
	241	+ PINCTRL_PIN(153, "QDSD_CMD"),
	242	+ PINCTRL_PIN(154, "QDSD_DATA0"),
	243	+ PINCTRL_PIN(155, "QDSD_DATA1"),
	244	+ PINCTRL_PIN(156, "QDSD_DATA2"),
	245	+ PINCTRL_PIN(157, "QDSD_DATA3"),
	246	+};
	247	+
	248	+#define DECLARE_MSM_GPIO_PINS(pin) \
	249	+ static const unsigned int gpio##pin##_pins[] = { pin }
	250	+DECLARE_MSM_GPIO_PINS(0);
	251	+DECLARE_MSM_GPIO_PINS(1);
	252	+DECLARE_MSM_GPIO_PINS(2);
	253	+DECLARE_MSM_GPIO_PINS(3);
	254	+DECLARE_MSM_GPIO_PINS(4);
	255	+DECLARE_MSM_GPIO_PINS(5);
	256	+DECLARE_MSM_GPIO_PINS(6);
	257	+DECLARE_MSM_GPIO_PINS(7);
	258	+DECLARE_MSM_GPIO_PINS(8);
	259	+DECLARE_MSM_GPIO_PINS(9);
	260	+DECLARE_MSM_GPIO_PINS(10);
	261	+DECLARE_MSM_GPIO_PINS(11);
	262	+DECLARE_MSM_GPIO_PINS(12);
	263	+DECLARE_MSM_GPIO_PINS(13);
	264	+DECLARE_MSM_GPIO_PINS(14);
	265	+DECLARE_MSM_GPIO_PINS(15);
	266	+DECLARE_MSM_GPIO_PINS(16);
	267	+DECLARE_MSM_GPIO_PINS(17);
	268	+DECLARE_MSM_GPIO_PINS(18);
	269	+DECLARE_MSM_GPIO_PINS(19);
	270	+DECLARE_MSM_GPIO_PINS(20);
	271	+DECLARE_MSM_GPIO_PINS(21);
	272	+DECLARE_MSM_GPIO_PINS(22);
	273	+DECLARE_MSM_GPIO_PINS(23);
	274	+DECLARE_MSM_GPIO_PINS(24);
	275	+DECLARE_MSM_GPIO_PINS(25);
	276	+DECLARE_MSM_GPIO_PINS(26);
	277	+DECLARE_MSM_GPIO_PINS(27);
	278	+DECLARE_MSM_GPIO_PINS(28);
	279	+DECLARE_MSM_GPIO_PINS(29);
	280	+DECLARE_MSM_GPIO_PINS(30);
	281	+DECLARE_MSM_GPIO_PINS(31);
	282	+DECLARE_MSM_GPIO_PINS(32);
	283	+DECLARE_MSM_GPIO_PINS(33);
	284	+DECLARE_MSM_GPIO_PINS(34);
	285	+DECLARE_MSM_GPIO_PINS(35);
	286	+DECLARE_MSM_GPIO_PINS(36);
	287	+DECLARE_MSM_GPIO_PINS(37);
	288	+DECLARE_MSM_GPIO_PINS(38);
	289	+DECLARE_MSM_GPIO_PINS(39);
	290	+DECLARE_MSM_GPIO_PINS(40);
	291	+DECLARE_MSM_GPIO_PINS(41);
	292	+DECLARE_MSM_GPIO_PINS(42);
	293	+DECLARE_MSM_GPIO_PINS(43);
	294	+DECLARE_MSM_GPIO_PINS(44);
	295	+DECLARE_MSM_GPIO_PINS(45);
	296	+DECLARE_MSM_GPIO_PINS(46);
	297	+DECLARE_MSM_GPIO_PINS(47);
	298	+DECLARE_MSM_GPIO_PINS(48);
	299	+DECLARE_MSM_GPIO_PINS(49);
	300	+DECLARE_MSM_GPIO_PINS(50);
	301	+DECLARE_MSM_GPIO_PINS(51);
	302	+DECLARE_MSM_GPIO_PINS(52);
	303	+DECLARE_MSM_GPIO_PINS(53);
	304	+DECLARE_MSM_GPIO_PINS(54);
	305	+DECLARE_MSM_GPIO_PINS(55);
	306	+DECLARE_MSM_GPIO_PINS(56);
	307	+DECLARE_MSM_GPIO_PINS(57);
	308	+DECLARE_MSM_GPIO_PINS(58);
	309	+DECLARE_MSM_GPIO_PINS(59);
	310	+DECLARE_MSM_GPIO_PINS(60);
	311	+DECLARE_MSM_GPIO_PINS(61);
	312	+DECLARE_MSM_GPIO_PINS(62);
	313	+DECLARE_MSM_GPIO_PINS(63);
	314	+DECLARE_MSM_GPIO_PINS(64);
	315	+DECLARE_MSM_GPIO_PINS(65);
	316	+DECLARE_MSM_GPIO_PINS(66);
	317	+DECLARE_MSM_GPIO_PINS(67);
	318	+DECLARE_MSM_GPIO_PINS(68);
	319	+DECLARE_MSM_GPIO_PINS(69);
	320	+DECLARE_MSM_GPIO_PINS(70);
	321	+DECLARE_MSM_GPIO_PINS(71);
	322	+DECLARE_MSM_GPIO_PINS(72);
	323	+DECLARE_MSM_GPIO_PINS(73);
	324	+DECLARE_MSM_GPIO_PINS(74);
	325	+DECLARE_MSM_GPIO_PINS(75);
	326	+DECLARE_MSM_GPIO_PINS(76);
	327	+DECLARE_MSM_GPIO_PINS(77);
	328	+DECLARE_MSM_GPIO_PINS(78);
	329	+DECLARE_MSM_GPIO_PINS(79);
	330	+DECLARE_MSM_GPIO_PINS(80);
	331	+DECLARE_MSM_GPIO_PINS(81);
	332	+DECLARE_MSM_GPIO_PINS(82);
	333	+DECLARE_MSM_GPIO_PINS(83);
	334	+DECLARE_MSM_GPIO_PINS(84);
	335	+DECLARE_MSM_GPIO_PINS(85);
	336	+DECLARE_MSM_GPIO_PINS(86);
	337	+DECLARE_MSM_GPIO_PINS(87);
	338	+DECLARE_MSM_GPIO_PINS(88);
	339	+DECLARE_MSM_GPIO_PINS(89);
	340	+DECLARE_MSM_GPIO_PINS(90);
	341	+DECLARE_MSM_GPIO_PINS(91);
	342	+DECLARE_MSM_GPIO_PINS(92);
	343	+DECLARE_MSM_GPIO_PINS(93);
	344	+DECLARE_MSM_GPIO_PINS(94);
	345	+DECLARE_MSM_GPIO_PINS(95);
	346	+DECLARE_MSM_GPIO_PINS(96);
	347	+DECLARE_MSM_GPIO_PINS(97);
	348	+DECLARE_MSM_GPIO_PINS(98);
	349	+DECLARE_MSM_GPIO_PINS(99);
	350	+DECLARE_MSM_GPIO_PINS(100);
	351	+DECLARE_MSM_GPIO_PINS(101);
	352	+DECLARE_MSM_GPIO_PINS(102);
	353	+DECLARE_MSM_GPIO_PINS(103);
	354	+DECLARE_MSM_GPIO_PINS(104);
	355	+DECLARE_MSM_GPIO_PINS(105);
	356	+DECLARE_MSM_GPIO_PINS(106);
	357	+DECLARE_MSM_GPIO_PINS(107);
	358	+DECLARE_MSM_GPIO_PINS(108);
	359	+DECLARE_MSM_GPIO_PINS(109);
	360	+DECLARE_MSM_GPIO_PINS(110);
	361	+DECLARE_MSM_GPIO_PINS(111);
	362	+DECLARE_MSM_GPIO_PINS(112);
	363	+DECLARE_MSM_GPIO_PINS(113);
	364	+DECLARE_MSM_GPIO_PINS(114);
	365	+DECLARE_MSM_GPIO_PINS(115);
	366	+DECLARE_MSM_GPIO_PINS(116);
	367	+DECLARE_MSM_GPIO_PINS(117);
	368	+DECLARE_MSM_GPIO_PINS(118);
	369	+DECLARE_MSM_GPIO_PINS(119);
	370	+DECLARE_MSM_GPIO_PINS(120);
	371	+DECLARE_MSM_GPIO_PINS(121);
	372	+DECLARE_MSM_GPIO_PINS(122);
	373	+DECLARE_MSM_GPIO_PINS(123);
	374	+DECLARE_MSM_GPIO_PINS(124);
	375	+DECLARE_MSM_GPIO_PINS(125);
	376	+DECLARE_MSM_GPIO_PINS(126);
	377	+DECLARE_MSM_GPIO_PINS(127);
	378	+DECLARE_MSM_GPIO_PINS(128);
	379	+DECLARE_MSM_GPIO_PINS(129);
	380	+DECLARE_MSM_GPIO_PINS(130);
	381	+DECLARE_MSM_GPIO_PINS(131);
	382	+DECLARE_MSM_GPIO_PINS(132);
	383	+DECLARE_MSM_GPIO_PINS(133);
	384	+DECLARE_MSM_GPIO_PINS(134);
	385	+DECLARE_MSM_GPIO_PINS(135);
	386	+DECLARE_MSM_GPIO_PINS(136);
	387	+DECLARE_MSM_GPIO_PINS(137);
	388	+DECLARE_MSM_GPIO_PINS(138);
	389	+DECLARE_MSM_GPIO_PINS(139);
	390	+DECLARE_MSM_GPIO_PINS(140);
	391	+DECLARE_MSM_GPIO_PINS(141);
	392	+DECLARE_MSM_GPIO_PINS(142);
	393	+DECLARE_MSM_GPIO_PINS(143);
	394	+DECLARE_MSM_GPIO_PINS(144);
	395	+
	396	+static const unsigned int sdc1_clk_pins[] = { 145 };
	397	+static const unsigned int sdc1_cmd_pins[] = { 146 };
	398	+static const unsigned int sdc1_data_pins[] = { 147 };
	399	+static const unsigned int sdc1_rclk_pins[] = { 148 };
	400	+static const unsigned int sdc2_clk_pins[] = { 149 };
	401	+static const unsigned int sdc2_cmd_pins[] = { 150 };
	402	+static const unsigned int sdc2_data_pins[] = { 151 };
	403	+static const unsigned int qdsd_clk_pins[] = { 152 };
	404	+static const unsigned int qdsd_cmd_pins[] = { 153 };
	405	+static const unsigned int qdsd_data0_pins[] = { 154 };
	406	+static const unsigned int qdsd_data1_pins[] = { 155 };
	407	+static const unsigned int qdsd_data2_pins[] = { 156 };
	408	+static const unsigned int qdsd_data3_pins[] = { 157 };
	409	+
	410	+enum msm8976_functions {
	411	+ msm_mux_gpio,
	412	+ msm_mux_blsp_uart1,
	413	+ msm_mux_blsp_spi1,
	414	+ msm_mux_smb_int,
	415	+ msm_mux_blsp_i2c1,
	416	+ msm_mux_blsp_spi2,
	417	+ msm_mux_blsp_uart2,
	418	+ msm_mux_blsp_i2c2,
	419	+ msm_mux_gcc_gp1_clk_b,
	420	+ msm_mux_blsp_spi3,
	421	+ msm_mux_qdss_tracedata_b,
	422	+ msm_mux_blsp_i2c3,
	423	+ msm_mux_gcc_gp2_clk_b,
	424	+ msm_mux_gcc_gp3_clk_b,
	425	+ msm_mux_blsp_spi4,
	426	+ msm_mux_cap_int,
	427	+ msm_mux_blsp_i2c4,
	428	+ msm_mux_blsp_spi5,
	429	+ msm_mux_blsp_uart5,
	430	+ msm_mux_qdss_traceclk_a,
	431	+ msm_mux_m_voc,
	432	+ msm_mux_blsp_i2c5,
	433	+ msm_mux_qdss_tracectl_a,
	434	+ msm_mux_qdss_tracedata_a,
	435	+ msm_mux_blsp_spi6,
	436	+ msm_mux_blsp_uart6,
	437	+ msm_mux_qdss_tracectl_b,
	438	+ msm_mux_blsp_i2c6,
	439	+ msm_mux_qdss_traceclk_b,
	440	+ msm_mux_mdp_vsync,
	441	+ msm_mux_pri_mi2s_mclk_a,
	442	+ msm_mux_sec_mi2s_mclk_a,
	443	+ msm_mux_cam_mclk,
	444	+ msm_mux_cci0_i2c,
	445	+ msm_mux_cci1_i2c,
	446	+ msm_mux_blsp1_spi,
	447	+ msm_mux_blsp3_spi,
	448	+ msm_mux_gcc_gp1_clk_a,
	449	+ msm_mux_gcc_gp2_clk_a,
	450	+ msm_mux_gcc_gp3_clk_a,
	451	+ msm_mux_uim_batt,
	452	+ msm_mux_sd_write,
	453	+ msm_mux_uim1_data,
	454	+ msm_mux_uim1_clk,
	455	+ msm_mux_uim1_reset,
	456	+ msm_mux_uim1_present,
	457	+ msm_mux_uim2_data,
	458	+ msm_mux_uim2_clk,
	459	+ msm_mux_uim2_reset,
	460	+ msm_mux_uim2_present,
	461	+ msm_mux_ts_xvdd,
	462	+ msm_mux_mipi_dsi0,
	463	+ msm_mux_us_euro,
	464	+ msm_mux_ts_resout,
	465	+ msm_mux_ts_sample,
	466	+ msm_mux_sec_mi2s_mclk_b,
	467	+ msm_mux_pri_mi2s,
	468	+ msm_mux_codec_reset,
	469	+ msm_mux_cdc_pdm0,
	470	+ msm_mux_us_emitter,
	471	+ msm_mux_pri_mi2s_mclk_b,
	472	+ msm_mux_pri_mi2s_mclk_c,
	473	+ msm_mux_lpass_slimbus,
	474	+ msm_mux_lpass_slimbus0,
	475	+ msm_mux_lpass_slimbus1,
	476	+ msm_mux_codec_int1,
	477	+ msm_mux_codec_int2,
	478	+ msm_mux_wcss_bt,
	479	+ msm_mux_sdc3,
	480	+ msm_mux_wcss_wlan2,
	481	+ msm_mux_wcss_wlan1,
	482	+ msm_mux_wcss_wlan0,
	483	+ msm_mux_wcss_wlan,
	484	+ msm_mux_wcss_fm,
	485	+ msm_mux_key_volp,
	486	+ msm_mux_key_snapshot,
	487	+ msm_mux_key_focus,
	488	+ msm_mux_key_home,
	489	+ msm_mux_pwr_down,
	490	+ msm_mux_dmic0_clk,
	491	+ msm_mux_hdmi_int,
	492	+ msm_mux_dmic0_data,
	493	+ msm_mux_wsa_vi,
	494	+ msm_mux_wsa_en,
	495	+ msm_mux_blsp_spi8,
	496	+ msm_mux_wsa_irq,
	497	+ msm_mux_blsp_i2c8,
	498	+ msm_mux_pa_indicator,
	499	+ msm_mux_modem_tsync,
	500	+ msm_mux_ssbi_wtr1,
	501	+ msm_mux_gsm1_tx,
	502	+ msm_mux_gsm0_tx,
	503	+ msm_mux_sdcard_det,
	504	+ msm_mux_sec_mi2s,
	505	+ msm_mux_ss_switch,
	506	+ msm_mux_NA,
	507	+};
	508	+
	509	+static const char * const gpio_groups[] = {
	510	+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
	511	+ "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
	512	+ "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
	513	+ "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
	514	+ "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
	515	+ "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
	516	+ "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
	517	+ "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
	518	+ "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
	519	+ "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
	520	+ "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
	521	+ "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
	522	+ "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
	523	+ "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
	524	+ "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
	525	+ "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
	526	+ "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
	527	+ "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
	528	+ "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
	529	+ "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
	530	+ "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
	531	+ "gpio141", "gpio142", "gpio143", "gpio144",
	532	+};
	533	+static const char * const blsp_uart1_groups[] = {
	534	+ "gpio0", "gpio1", "gpio2", "gpio3",
	535	+};
	536	+static const char * const blsp_spi1_groups[] = {
	537	+ "gpio0", "gpio1", "gpio2", "gpio3",
	538	+};
	539	+static const char * const smb_int_groups[] = {
	540	+ "gpio1",
	541	+};
	542	+static const char * const blsp_i2c1_groups[] = {
	543	+ "gpio2", "gpio3",
	544	+};
	545	+static const char * const blsp_spi2_groups[] = {
	546	+ "gpio4", "gpio5", "gpio6", "gpio7",
	547	+};
	548	+static const char * const blsp_uart2_groups[] = {
	549	+ "gpio4", "gpio5", "gpio6", "gpio7",
	550	+};
	551	+static const char * const blsp_i2c2_groups[] = {
	552	+ "gpio6", "gpio7",
	553	+};
	554	+static const char * const gcc_gp1_clk_b_groups[] = {
	555	+ "gpio105",
	556	+};
	557	+static const char * const blsp_spi3_groups[] = {
	558	+ "gpio8", "gpio9", "gpio10", "gpio11",
	559	+};
	560	+static const char * const qdss_tracedata_b_groups[] = {
	561	+ "gpio26", "gpio27", "gpio28", "gpio29", "gpio30",
	562	+ "gpio31", "gpio33", "gpio34", "gpio35", "gpio36", "gpio37", "gpio38",
	563	+ "gpio116", "gpio126", "gpio128", "gpio129",
	564	+};
	565	+static const char * const blsp_i2c3_groups[] = {
	566	+ "gpio10", "gpio11",
	567	+};
	568	+static const char * const gcc_gp2_clk_b_groups[] = {
	569	+ "gpio12",
	570	+};
	571	+static const char * const gcc_gp3_clk_b_groups[] = {
	572	+ "gpio13",
	573	+};
	574	+static const char * const blsp_spi4_groups[] = {
	575	+ "gpio12", "gpio13", "gpio14", "gpio15",
	576	+};
	577	+static const char * const cap_int_groups[] = {
	578	+ "gpio13",
	579	+};
	580	+static const char * const blsp_i2c4_groups[] = {
	581	+ "gpio14", "gpio15",
	582	+};
	583	+static const char * const blsp_spi5_groups[] = {
	584	+ "gpio134", "gpio135", "gpio136", "gpio137",
	585	+};
	586	+static const char * const blsp_uart5_groups[] = {
	587	+ "gpio134", "gpio135", "gpio136", "gpio137",
	588	+};
	589	+static const char * const qdss_traceclk_a_groups[] = {
	590	+ "gpio46",
	591	+};
	592	+const char * const m_voc_groups[] = {
	593	+ "gpio123", "gpio124",
	594	+};
	595	+static const char * const blsp_i2c5_groups[] = {
	596	+ "gpio136", "gpio137",
	597	+};
	598	+static const char * const qdss_tracectl_a_groups[] = {
	599	+ "gpio45",
	600	+};
	601	+static const char * const qdss_tracedata_a_groups[] = {
	602	+ "gpio8", "gpio9", "gpio10", "gpio39", "gpio40", "gpio41", "gpio42",
	603	+ "gpio43", "gpio44", "gpio47", "gpio48", "gpio62", "gpio69", "gpio120",
	604	+ "gpio121", "gpio130", "gpio131",
	605	+};
	606	+static const char * const blsp_spi6_groups[] = {
	607	+ "gpio20", "gpio21", "gpio22", "gpio23",
	608	+};
	609	+static const char * const blsp_uart6_groups[] = {
	610	+ "gpio20", "gpio21", "gpio22", "gpio23",
	611	+};
	612	+static const char * const qdss_tracectl_b_groups[] = {
	613	+ "gpio5",
	614	+};
	615	+static const char * const blsp_i2c6_groups[] = {
	616	+ "gpio22", "gpio23",
	617	+};
	618	+static const char * const qdss_traceclk_b_groups[] = {
	619	+ "gpio5",
	620	+};
	621	+static const char * const mdp_vsync_groups[] = {
	622	+ "gpio24", "gpio25",
	623	+};
	624	+static const char * const pri_mi2s_mclk_a_groups[] = {
	625	+ "gpio126",
	626	+};
	627	+static const char * const sec_mi2s_mclk_a_groups[] = {
	628	+ "gpio62",
	629	+};
	630	+static const char * const cam_mclk_groups[] = {
	631	+ "gpio26", "gpio27", "gpio28",
	632	+};
	633	+static const char * const cci0_i2c_groups[] = {
	634	+ "gpio30", "gpio29",
	635	+};
	636	+static const char * const cci1_i2c_groups[] = {
	637	+ "gpio104", "gpio103",
	638	+};
	639	+static const char * const blsp1_spi_groups[] = {
	640	+ "gpio101",
	641	+};
	642	+static const char * const blsp3_spi_groups[] = {
	643	+ "gpio106", "gpio107",
	644	+};
	645	+static const char * const gcc_gp1_clk_a_groups[] = {
	646	+ "gpio49",
	647	+};
	648	+static const char * const gcc_gp2_clk_a_groups[] = {
	649	+ "gpio50",
	650	+};
	651	+static const char * const gcc_gp3_clk_a_groups[] = {
	652	+ "gpio51",
	653	+};
	654	+static const char * const uim_batt_groups[] = {
	655	+ "gpio61",
	656	+};
	657	+static const char * const sd_write_groups[] = {
	658	+ "gpio50",
	659	+};
	660	+static const char * const uim2_data_groups[] = {
	661	+ "gpio51",
	662	+};
	663	+static const char * const uim2_clk_groups[] = {
	664	+ "gpio52",
	665	+};
	666	+static const char * const uim2_reset_groups[] = {
	667	+ "gpio53",
	668	+};
	669	+static const char * const uim2_present_groups[] = {
	670	+ "gpio54",
	671	+};
	672	+static const char * const uim1_data_groups[] = {
	673	+ "gpio55",
	674	+};
	675	+static const char * const uim1_clk_groups[] = {
	676	+ "gpio56",
	677	+};
	678	+static const char * const uim1_reset_groups[] = {
	679	+ "gpio57",
	680	+};
	681	+static const char * const uim1_present_groups[] = {
	682	+ "gpio58",
	683	+};
	684	+static const char * const ts_xvdd_groups[] = {
	685	+ "gpio60",
	686	+};
	687	+static const char * const mipi_dsi0_groups[] = {
	688	+ "gpio61",
	689	+};
	690	+static const char * const us_euro_groups[] = {
	691	+ "gpio63",
	692	+};
	693	+static const char * const ts_resout_groups[] = {
	694	+ "gpio64",
	695	+};
	696	+static const char * const ts_sample_groups[] = {
	697	+ "gpio65",
	698	+};
	699	+static const char * const sec_mi2s_mclk_b_groups[] = {
	700	+ "gpio66",
	701	+};
	702	+static const char * const pri_mi2s_groups[] = {
	703	+ "gpio122", "gpio123", "gpio124", "gpio125", "gpio127",
	704	+};
	705	+static const char * const codec_reset_groups[] = {
	706	+ "gpio67",
	707	+};
	708	+static const char * const cdc_pdm0_groups[] = {
	709	+ "gpio116", "gpio117", "gpio118", "gpio119", "gpio120", "gpio121",
	710	+};
	711	+static const char * const us_emitter_groups[] = {
	712	+ "gpio68",
	713	+};
	714	+static const char * const pri_mi2s_mclk_b_groups[] = {
	715	+ "gpio62",
	716	+};
	717	+static const char * const pri_mi2s_mclk_c_groups[] = {
	718	+ "gpio116",
	719	+};
	720	+static const char * const lpass_slimbus_groups[] = {
	721	+ "gpio117",
	722	+};
	723	+static const char * const lpass_slimbus0_groups[] = {
	724	+ "gpio118",
	725	+};
	726	+static const char * const lpass_slimbus1_groups[] = {
	727	+ "gpio119",
	728	+};
	729	+static const char * const codec_int1_groups[] = {
	730	+ "gpio73",
	731	+};
	732	+static const char * const codec_int2_groups[] = {
	733	+ "gpio74",
	734	+};
	735	+static const char * const wcss_bt_groups[] = {
	736	+ "gpio39", "gpio47", "gpio88",
	737	+};
	738	+static const char * const sdc3_groups[] = {
	739	+ "gpio39", "gpio40", "gpio41",
	740	+ "gpio42", "gpio43", "gpio44",
	741	+};
	742	+static const char * const wcss_wlan2_groups[] = {
	743	+ "gpio40",
	744	+};
	745	+static const char * const wcss_wlan1_groups[] = {
	746	+ "gpio41",
	747	+};
	748	+static const char * const wcss_wlan0_groups[] = {
	749	+ "gpio42",
	750	+};
	751	+static const char * const wcss_wlan_groups[] = {
	752	+ "gpio43", "gpio44",
	753	+};
	754	+static const char * const wcss_fm_groups[] = {
	755	+ "gpio45", "gpio46",
	756	+};
	757	+static const char * const key_volp_groups[] = {
	758	+ "gpio85",
	759	+};
	760	+static const char * const key_snapshot_groups[] = {
	761	+ "gpio86",
	762	+};
	763	+static const char * const key_focus_groups[] = {
	764	+ "gpio87",
	765	+};
	766	+static const char * const key_home_groups[] = {
	767	+ "gpio88",
	768	+};
	769	+static const char * const pwr_down_groups[] = {
	770	+ "gpio89",
	771	+};
	772	+static const char * const dmic0_clk_groups[] = {
	773	+ "gpio66",
	774	+};
	775	+static const char * const hdmi_int_groups[] = {
	776	+ "gpio90",
	777	+};
	778	+static const char * const dmic0_data_groups[] = {
	779	+ "gpio67",
	780	+};
	781	+static const char * const wsa_vi_groups[] = {
	782	+ "gpio108", "gpio109",
	783	+};
	784	+static const char * const wsa_en_groups[] = {
	785	+ "gpio96",
	786	+};
	787	+static const char * const blsp_spi8_groups[] = {
	788	+ "gpio16", "gpio17", "gpio18", "gpio19",
	789	+};
	790	+static const char * const wsa_irq_groups[] = {
	791	+ "gpio97",
	792	+};
	793	+static const char * const blsp_i2c8_groups[] = {
	794	+ "gpio18", "gpio19",
	795	+};
	796	+static const char * const pa_indicator_groups[] = {
	797	+ "gpio92",
	798	+};
	799	+static const char * const modem_tsync_groups[] = {
	800	+ "gpio93",
	801	+};
	802	+static const char * const nav_tsync_groups[] = {
	803	+ "gpio93",
	804	+};
	805	+static const char * const ssbi_wtr1_groups[] = {
	806	+ "gpio79", "gpio94",
	807	+};
	808	+static const char * const gsm1_tx_groups[] = {
	809	+ "gpio95",
	810	+};
	811	+static const char * const gsm0_tx_groups[] = {
	812	+ "gpio99",
	813	+};
	814	+static const char * const sdcard_det_groups[] = {
	815	+ "gpio133",
	816	+};
	817	+static const char * const sec_mi2s_groups[] = {
	818	+ "gpio102", "gpio105", "gpio134", "gpio135",
	819	+};
	820	+
	821	+static const char * const ss_switch_groups[] = {
	822	+ "gpio139",
	823	+};
	824	+
	825	+static const struct msm_function msm8976_functions[] = {
	826	+ FUNCTION(gpio),
	827	+ FUNCTION(blsp_spi1),
	828	+ FUNCTION(smb_int),
	829	+ FUNCTION(blsp_i2c1),
	830	+ FUNCTION(blsp_spi2),
	831	+ FUNCTION(blsp_uart1),
	832	+ FUNCTION(blsp_uart2),
	833	+ FUNCTION(blsp_i2c2),
	834	+ FUNCTION(gcc_gp1_clk_b),
	835	+ FUNCTION(blsp_spi3),
	836	+ FUNCTION(qdss_tracedata_b),
	837	+ FUNCTION(blsp_i2c3),
	838	+ FUNCTION(gcc_gp2_clk_b),
	839	+ FUNCTION(gcc_gp3_clk_b),
	840	+ FUNCTION(blsp_spi4),
	841	+ FUNCTION(cap_int),
	842	+ FUNCTION(blsp_i2c4),
	843	+ FUNCTION(blsp_spi5),
	844	+ FUNCTION(blsp_uart5),
	845	+ FUNCTION(qdss_traceclk_a),
	846	+ FUNCTION(m_voc),
	847	+ FUNCTION(blsp_i2c5),
	848	+ FUNCTION(qdss_tracectl_a),
	849	+ FUNCTION(qdss_tracedata_a),
	850	+ FUNCTION(blsp_spi6),
	851	+ FUNCTION(blsp_uart6),
	852	+ FUNCTION(qdss_tracectl_b),
	853	+ FUNCTION(blsp_i2c6),
	854	+ FUNCTION(qdss_traceclk_b),
	855	+ FUNCTION(mdp_vsync),
	856	+ FUNCTION(pri_mi2s_mclk_a),
	857	+ FUNCTION(sec_mi2s_mclk_a),
	858	+ FUNCTION(cam_mclk),
	859	+ FUNCTION(cci0_i2c),
	860	+ FUNCTION(cci1_i2c),
	861	+ FUNCTION(blsp1_spi),
	862	+ FUNCTION(blsp3_spi),
	863	+ FUNCTION(gcc_gp1_clk_a),
	864	+ FUNCTION(gcc_gp2_clk_a),
	865	+ FUNCTION(gcc_gp3_clk_a),
	866	+ FUNCTION(uim_batt),
	867	+ FUNCTION(sd_write),
	868	+ FUNCTION(uim1_data),
	869	+ FUNCTION(uim1_clk),
	870	+ FUNCTION(uim1_reset),
	871	+ FUNCTION(uim1_present),
	872	+ FUNCTION(uim2_data),
	873	+ FUNCTION(uim2_clk),
	874	+ FUNCTION(uim2_reset),
	875	+ FUNCTION(uim2_present),
	876	+ FUNCTION(ts_xvdd),
	877	+ FUNCTION(mipi_dsi0),
	878	+ FUNCTION(us_euro),
	879	+ FUNCTION(ts_resout),
	880	+ FUNCTION(ts_sample),
	881	+ FUNCTION(sec_mi2s_mclk_b),
	882	+ FUNCTION(pri_mi2s),
	883	+ FUNCTION(codec_reset),
	884	+ FUNCTION(cdc_pdm0),
	885	+ FUNCTION(us_emitter),
	886	+ FUNCTION(pri_mi2s_mclk_b),
	887	+ FUNCTION(pri_mi2s_mclk_c),
	888	+ FUNCTION(lpass_slimbus),
	889	+ FUNCTION(lpass_slimbus0),
	890	+ FUNCTION(lpass_slimbus1),
	891	+ FUNCTION(codec_int1),
	892	+ FUNCTION(codec_int2),
	893	+ FUNCTION(wcss_bt),
	894	+ FUNCTION(sdc3),
	895	+ FUNCTION(wcss_wlan2),
	896	+ FUNCTION(wcss_wlan1),
	897	+ FUNCTION(wcss_wlan0),
	898	+ FUNCTION(wcss_wlan),
	899	+ FUNCTION(wcss_fm),
	900	+ FUNCTION(key_volp),
	901	+ FUNCTION(key_snapshot),
	902	+ FUNCTION(key_focus),
	903	+ FUNCTION(key_home),
	904	+ FUNCTION(pwr_down),
	905	+ FUNCTION(dmic0_clk),
	906	+ FUNCTION(hdmi_int),
	907	+ FUNCTION(dmic0_data),
	908	+ FUNCTION(wsa_vi),
	909	+ FUNCTION(wsa_en),
	910	+ FUNCTION(blsp_spi8),
	911	+ FUNCTION(wsa_irq),
	912	+ FUNCTION(blsp_i2c8),
	913	+ FUNCTION(pa_indicator),
	914	+ FUNCTION(modem_tsync),
	915	+ FUNCTION(ssbi_wtr1),
	916	+ FUNCTION(gsm1_tx),
	917	+ FUNCTION(gsm0_tx),
	918	+ FUNCTION(sdcard_det),
	919	+ FUNCTION(sec_mi2s),
	920	+ FUNCTION(ss_switch),
	921	+};
	922	+
	923	+static const struct msm_pingroup msm8976_groups[] = {
	924	+ PINGROUP(0, blsp_spi1, blsp_uart1, NA, NA, NA, NA, NA, NA, NA),
	925	+ PINGROUP(1, blsp_spi1, blsp_uart1, NA, NA, NA, NA, NA, NA, NA),
	926	+ PINGROUP(2, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA, NA, NA),
	927	+ PINGROUP(3, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA, NA, NA),
	928	+ PINGROUP(4, blsp_spi2, blsp_uart2, NA, NA, NA, qdss_tracectl_b, NA, NA, NA),
	929	+ PINGROUP(5, blsp_spi2, blsp_uart2, NA, NA, NA, qdss_traceclk_b, NA, NA, NA),
	930	+ PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA, NA, NA),
	931	+ PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA, NA, NA),
	932	+ PINGROUP(8, blsp_spi3, NA, NA, NA, NA, qdss_tracedata_a, NA, NA, NA),
	933	+ PINGROUP(9, blsp_spi3, NA, NA, NA, qdss_tracedata_a, NA, NA, NA, NA),
	934	+ PINGROUP(10, blsp_spi3, NA, blsp_i2c3, NA, NA, qdss_tracedata_a, NA, NA, NA),
	935	+ PINGROUP(11, blsp_spi3, NA, blsp_i2c3, NA, NA, NA, NA, NA, NA),
	936	+ PINGROUP(12, blsp_spi4, NA, gcc_gp2_clk_b, NA, NA, NA, NA, NA, NA),
	937	+ PINGROUP(13, blsp_spi4, NA, gcc_gp3_clk_b, NA, NA, NA, NA, NA, NA),
	938	+ PINGROUP(14, blsp_spi4, NA, blsp_i2c4, NA, NA, NA, NA, NA, NA),
	939	+ PINGROUP(15, blsp_spi4, NA, blsp_i2c4, NA, NA, NA, NA, NA, NA),
	940	+ PINGROUP(16, blsp_spi8, NA, NA, NA, NA, NA, NA, NA, NA),
	941	+ PINGROUP(17, blsp_spi8, NA, NA, NA, NA, NA, NA, NA, NA),
	942	+ PINGROUP(18, blsp_spi8, NA, blsp_i2c8, NA, NA, NA, NA, NA, NA),
	943	+ PINGROUP(19, blsp_spi8, NA, blsp_i2c8, NA, NA, NA, NA, NA, NA),
	944	+ PINGROUP(20, blsp_spi6, blsp_uart6, NA, NA, NA, NA, NA, NA, NA),
	945	+ PINGROUP(21, blsp_spi6, blsp_uart6, NA, NA, NA, NA, NA, NA, NA),
	946	+ PINGROUP(22, blsp_spi6, blsp_uart6, blsp_i2c6, NA, NA, NA, NA, NA, NA),
	947	+ PINGROUP(23, blsp_spi6, blsp_uart6, blsp_i2c6, NA, NA, NA, NA, NA, NA),
	948	+ PINGROUP(24, mdp_vsync, NA, NA, NA, NA, NA, NA, NA, NA),
	949	+ PINGROUP(25, mdp_vsync, NA, NA, NA, NA, NA, NA, NA, NA),
	950	+ PINGROUP(26, cam_mclk, NA, NA, NA, NA, qdss_tracedata_b, NA, NA, NA),
	951	+ PINGROUP(27, cam_mclk, NA, NA, NA, NA, NA, qdss_tracedata_b, NA, NA),
	952	+ PINGROUP(28, cam_mclk, NA, NA, NA, NA, qdss_tracedata_b, NA, NA, NA),
	953	+ PINGROUP(29, cci0_i2c, NA, NA, NA, NA, qdss_tracedata_b, NA, NA, NA),
	954	+ PINGROUP(30, cci0_i2c, NA, NA, NA, NA, NA, qdss_tracedata_b, NA, NA),
	955	+ PINGROUP(31, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b, NA),
	956	+ PINGROUP(32, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	957	+ PINGROUP(33, NA, NA, NA, NA, NA, NA, qdss_tracedata_b, NA, NA),
	958	+ PINGROUP(34, NA, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b),
	959	+ PINGROUP(35, NA, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b),
	960	+ PINGROUP(36, NA, NA, NA, NA, NA, NA, qdss_tracedata_b, NA, NA),
	961	+ PINGROUP(37, NA, NA, NA, qdss_tracedata_b, NA, NA, NA, NA, NA),
	962	+ PINGROUP(38, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b, NA),
	963	+ PINGROUP(39, wcss_bt, sdc3, NA, qdss_tracedata_a, NA, NA, NA, NA, NA),
	964	+ PINGROUP(40, wcss_wlan, sdc3, NA, qdss_tracedata_a, NA, NA, NA, NA, NA),
	965	+ PINGROUP(41, wcss_wlan, sdc3, NA, qdss_tracedata_a, NA, NA, NA, NA, NA),
	966	+ PINGROUP(42, wcss_wlan, sdc3, NA, qdss_tracedata_a, NA, NA, NA, NA, NA),
	967	+ PINGROUP(43, wcss_wlan, sdc3, NA, NA, qdss_tracedata_a, NA, NA, NA, NA),
	968	+ PINGROUP(44, wcss_wlan, sdc3, NA, NA, NA, NA, NA, NA, NA),
	969	+ PINGROUP(45, wcss_fm, NA, qdss_tracectl_a, NA, NA, NA, NA, NA, NA),
	970	+ PINGROUP(46, wcss_fm, NA, NA, qdss_traceclk_a, NA, NA, NA, NA, NA),
	971	+ PINGROUP(47, wcss_bt, NA, qdss_tracedata_a, NA, NA, NA, NA, NA, NA),
	972	+ PINGROUP(48, wcss_bt, NA, qdss_tracedata_a, NA, NA, NA, NA, NA, NA),
	973	+ PINGROUP(49, NA, NA, gcc_gp1_clk_a, NA, NA, NA, NA, NA, NA),
	974	+ PINGROUP(50, NA, sd_write, gcc_gp2_clk_a, NA, NA, NA, NA, NA, NA),
	975	+ PINGROUP(51, uim2_data, gcc_gp3_clk_a, NA, NA, NA, NA, NA, NA, NA),
	976	+ PINGROUP(52, uim2_clk, NA, NA, NA, NA, NA, NA, NA, NA),
	977	+ PINGROUP(53, uim2_reset, NA, NA, NA, NA, NA, NA, NA, NA),
	978	+ PINGROUP(54, uim2_present, NA, NA, NA, NA, NA, NA, NA, NA),
	979	+ PINGROUP(55, uim1_data, NA, NA, NA, NA, NA, NA, NA, NA),
	980	+ PINGROUP(56, uim1_clk, NA, NA, NA, NA, NA, NA, NA, NA),
	981	+ PINGROUP(57, uim1_reset, NA, NA, NA, NA, NA, NA, NA, NA),
	982	+ PINGROUP(58, uim1_present, NA, NA, NA, NA, NA, NA, NA, NA),
	983	+ PINGROUP(59, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	984	+ PINGROUP(60, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	985	+ PINGROUP(61, uim_batt, NA, NA, NA, NA, NA, NA, NA, NA),
	986	+ PINGROUP(62, sec_mi2s_mclk_a, pri_mi2s_mclk_b, qdss_tracedata_a, NA, NA, NA, NA, NA, NA),
	987	+ PINGROUP(63, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	988	+ PINGROUP(64, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	989	+ PINGROUP(65, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	990	+ PINGROUP(66, dmic0_clk, NA, NA, NA, NA, NA, NA, NA, NA),
	991	+ PINGROUP(67, dmic0_data, NA, NA, NA, NA, NA, NA, NA, NA),
	992	+ PINGROUP(68, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	993	+ PINGROUP(69, qdss_tracedata_a, NA, NA, NA, NA, NA, NA, NA, NA),
	994	+ PINGROUP(70, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	995	+ PINGROUP(71, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	996	+ PINGROUP(72, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	997	+ PINGROUP(73, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	998	+ PINGROUP(74, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	999	+ PINGROUP(75, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	1000	+ PINGROUP(76, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	1001	+ PINGROUP(77, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	1002	+ PINGROUP(78, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	1003	+ PINGROUP(79, NA, ssbi_wtr1, NA, NA, NA, NA, NA, NA, NA),
	1004	+ PINGROUP(80, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	1005	+ PINGROUP(81, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	1006	+ PINGROUP(82, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	1007	+ PINGROUP(83, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	1008	+ PINGROUP(84, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	1009	+ PINGROUP(85, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	1010	+ PINGROUP(86, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	1011	+ PINGROUP(87, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	1012	+ PINGROUP(88, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	1013	+ PINGROUP(89, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	1014	+ PINGROUP(90, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	1015	+ PINGROUP(91, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	1016	+ PINGROUP(92, NA, NA, pa_indicator, NA, NA, NA, NA, NA, NA),
	1017	+ PINGROUP(93, NA, modem_tsync, NA, NA, NA, NA, NA, NA, NA),
	1018	+ PINGROUP(94, NA, ssbi_wtr1, NA, NA, NA, NA, NA, NA, NA),
	1019	+ PINGROUP(95, NA, gsm1_tx, NA, NA, NA, NA, NA, NA, NA),
	1020	+ PINGROUP(96, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	1021	+ PINGROUP(97, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	1022	+ PINGROUP(98, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	1023	+ PINGROUP(99, gsm0_tx, NA, NA, NA, NA, NA, NA, NA, NA),
	1024	+ PINGROUP(100, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	1025	+ PINGROUP(101, blsp1_spi, NA, NA, NA, NA, NA, NA, NA, NA),
	1026	+ PINGROUP(102, sec_mi2s, NA, NA, NA, NA, NA, NA, NA, NA),
	1027	+ PINGROUP(103, cci1_i2c, NA, NA, NA, NA, NA, NA, NA, NA),
	1028	+ PINGROUP(104, cci1_i2c, NA, NA, NA, NA, NA, NA, NA, NA),
	1029	+ PINGROUP(105, sec_mi2s, gcc_gp1_clk_b, NA, NA, NA, NA, NA, NA, NA),
	1030	+ PINGROUP(106, blsp3_spi, NA, NA, NA, NA, NA, NA, NA, NA),
	1031	+ PINGROUP(107, blsp3_spi, NA, NA, NA, NA, NA, NA, NA, NA),
	1032	+ PINGROUP(108, wsa_vi, NA, NA, NA, NA, NA, NA, NA, NA),
	1033	+ PINGROUP(109, wsa_vi, NA, NA, NA, NA, NA, NA, NA, NA),
	1034	+ PINGROUP(110, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	1035	+ PINGROUP(111, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	1036	+ PINGROUP(112, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	1037	+ PINGROUP(113, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	1038	+ PINGROUP(114, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	1039	+ PINGROUP(115, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	1040	+ PINGROUP(116, pri_mi2s_mclk_c, cdc_pdm0, NA, NA, NA, qdss_tracedata_b, NA, NA, NA),
	1041	+ PINGROUP(117, lpass_slimbus, cdc_pdm0, NA, NA, NA, NA, NA, NA, NA),
	1042	+ PINGROUP(118, lpass_slimbus0, cdc_pdm0, NA, NA, NA, NA, NA, NA, NA),
	1043	+ PINGROUP(119, lpass_slimbus1, cdc_pdm0, NA, NA, NA, NA, NA, NA, NA),
	1044	+ PINGROUP(120, cdc_pdm0, NA, NA, NA, NA, NA, NA, qdss_tracedata_a, NA),
	1045	+ PINGROUP(121, cdc_pdm0, NA, NA, NA, NA, NA, NA, qdss_tracedata_a, NA),
	1046	+ PINGROUP(122, pri_mi2s, NA, NA, NA, NA, NA, NA, NA, NA),
	1047	+ PINGROUP(123, pri_mi2s, m_voc, NA, NA, NA, NA, NA, NA, NA),
	1048	+ PINGROUP(124, pri_mi2s, m_voc, NA, NA, NA, NA, NA, NA, NA),
	1049	+ PINGROUP(125, pri_mi2s, NA, NA, NA, NA, NA, NA, NA, NA),
	1050	+ PINGROUP(126, pri_mi2s_mclk_a, sec_mi2s_mclk_b, NA, NA, NA, NA, NA, NA, qdss_tracedata_b),
	1051	+ PINGROUP(127, pri_mi2s, NA, NA, NA, NA, NA, NA, NA, NA),
	1052	+ PINGROUP(128, NA, NA, NA, NA, NA, NA, qdss_tracedata_b, NA, NA),
	1053	+ PINGROUP(129, qdss_tracedata_b, NA, NA, NA, NA, NA, NA, NA, NA),
	1054	+ PINGROUP(130, qdss_tracedata_a, NA, NA, NA, NA, NA, NA, NA, NA),
	1055	+ PINGROUP(131, qdss_tracedata_a, NA, NA, NA, NA, NA, NA, NA, NA),
	1056	+ PINGROUP(132, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	1057	+ PINGROUP(133, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	1058	+ PINGROUP(134, blsp_spi5, blsp_uart5, sec_mi2s, NA, NA, NA, NA, NA, NA),
	1059	+ PINGROUP(135, blsp_spi5, blsp_uart5, sec_mi2s, NA, NA, NA, NA, NA, NA),
	1060	+ PINGROUP(136, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA, NA, NA, NA),
	1061	+ PINGROUP(137, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA, NA, NA, NA),
	1062	+ PINGROUP(138, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	1063	+ PINGROUP(139, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	1064	+ PINGROUP(140, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	1065	+ PINGROUP(141, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	1066	+ PINGROUP(142, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	1067	+ PINGROUP(143, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	1068	+ PINGROUP(144, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	1069	+ SDC_QDSD_PINGROUP(sdc1_clk, 0x10a000, 13, 6),
	1070	+ SDC_QDSD_PINGROUP(sdc1_cmd, 0x10a000, 11, 3),
	1071	+ SDC_QDSD_PINGROUP(sdc1_data, 0x10a000, 9, 0),
	1072	+ SDC_QDSD_PINGROUP(sdc1_rclk, 0x10a000, 15, 0),
	1073	+ SDC_QDSD_PINGROUP(sdc2_clk, 0x109000, 14, 6),
	1074	+ SDC_QDSD_PINGROUP(sdc2_cmd, 0x109000, 11, 3),
	1075	+ SDC_QDSD_PINGROUP(sdc2_data, 0x109000, 9, 0),
	1076	+ SDC_QDSD_PINGROUP(qdsd_clk, 0x19c000, 3, 0),
	1077	+ SDC_QDSD_PINGROUP(qdsd_cmd, 0x19c000, 8, 5),
	1078	+ SDC_QDSD_PINGROUP(qdsd_data0, 0x19c000, 13, 10),
	1079	+ SDC_QDSD_PINGROUP(qdsd_data1, 0x19c000, 18, 15),
	1080	+ SDC_QDSD_PINGROUP(qdsd_data2, 0x19c000, 23, 20),
	1081	+ SDC_QDSD_PINGROUP(qdsd_data3, 0x19c000, 28, 25),
	1082	+};
	1083	+
	1084	+static const struct msm_pinctrl_soc_data msm8976_pinctrl = {
	1085	+ .pins = msm8976_pins,
	1086	+ .npins = ARRAY_SIZE(msm8976_pins),
	1087	+ .functions = msm8976_functions,
	1088	+ .nfunctions = ARRAY_SIZE(msm8976_functions),
	1089	+ .groups = msm8976_groups,
	1090	+ .ngroups = ARRAY_SIZE(msm8976_groups),
	1091	+ .ngpios = 145,
	1092	+};
	1093	+
	1094	+static int msm8976_pinctrl_probe(struct platform_device *pdev)
	1095	+{
	1096	+ return msm_pinctrl_probe(pdev, &msm8976_pinctrl);
	1097	+}
	1098	+
	1099	+static const struct of_device_id msm8976_pinctrl_of_match[] = {
	1100	+ { .compatible = "qcom,msm8976-pinctrl", },
	1101	+ { },
	1102	+};
	1103	+
	1104	+static struct platform_driver msm8976_pinctrl_driver = {
	1105	+ .driver = {
	1106	+ .name = "msm8976-pinctrl",
	1107	+ .of_match_table = msm8976_pinctrl_of_match,
	1108	+ },
	1109	+ .probe = msm8976_pinctrl_probe,
	1110	+ .remove = msm_pinctrl_remove,
	1111	+};
	1112	+
	1113	+static int __init msm8976_pinctrl_init(void)
	1114	+{
	1115	+ return platform_driver_register(&msm8976_pinctrl_driver);
	1116	+}
	1117	+arch_initcall(msm8976_pinctrl_init);
	1118	+
	1119	+static void __exit msm8976_pinctrl_exit(void)
	1120	+{
	1121	+ platform_driver_unregister(&msm8976_pinctrl_driver);
	1122	+}
	1123	+module_exit(msm8976_pinctrl_exit);
	1124	+
	1125	+MODULE_DESCRIPTION("Qualcomm msm8976 pinctrl driver");
	1126	+MODULE_LICENSE("GPL v2");
	1127	+MODULE_DEVICE_TABLE(of, msm8976_pinctrl_of_match);

drivers/pinctrl/qcom/pinctrl-sc7180.c+10−8

@@ -77,6 +77,7 @@ enum { · 76 unmodified lines
77	77	.intr_cfg_reg = 0, \
78	78	.intr_status_reg = 0, \
79	79	.intr_target_reg = 0, \
	80	+ .tile = SOUTH, \
80	81	.mux_bit = -1, \
81	82	.pull_bit = pull, \
82	83	.drv_bit = drv, \
@@ -102,6 +103,7 @@ enum { · 19 unmodified lines
102	103	.intr_cfg_reg = 0, \
103	104	.intr_status_reg = 0, \
104	105	.intr_target_reg = 0, \
	106	+ .tile = SOUTH, \
105	107	.mux_bit = -1, \
106	108	.pull_bit = 3, \
107	109	.drv_bit = 0, \
@@ -1087,14 +1089,14 @@ static const struct msm_pingroup sc7180_groups[] = { · 979 unmodified lines
1087	1089	[116] = PINGROUP(116, WEST, qup04, qup04, _, _, _, _, _, _, _),
1088	1090	[117] = PINGROUP(117, WEST, dp_hot, _, _, _, _, _, _, _, _),
1089	1091	[118] = PINGROUP(118, WEST, _, _, _, _, _, _, _, _, _),
1090		− [119] = UFS_RESET(ufs_reset, 0x97f000),
1091		− [120] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x97a000, 15, 0),
1092		− [121] = SDC_QDSD_PINGROUP(sdc1_clk, 0x97a000, 13, 6),
1093		− [122] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x97a000, 11, 3),
1094		− [123] = SDC_QDSD_PINGROUP(sdc1_data, 0x97a000, 9, 0),
1095		− [124] = SDC_QDSD_PINGROUP(sdc2_clk, 0x97b000, 14, 6),
1096		− [125] = SDC_QDSD_PINGROUP(sdc2_cmd, 0x97b000, 11, 3),
1097		− [126] = SDC_QDSD_PINGROUP(sdc2_data, 0x97b000, 9, 0),
	1092	+ [119] = UFS_RESET(ufs_reset, 0x7f000),
	1093	+ [120] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x7a000, 15, 0),
	1094	+ [121] = SDC_QDSD_PINGROUP(sdc1_clk, 0x7a000, 13, 6),
	1095	+ [122] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x7a000, 11, 3),
	1096	+ [123] = SDC_QDSD_PINGROUP(sdc1_data, 0x7a000, 9, 0),
	1097	+ [124] = SDC_QDSD_PINGROUP(sdc2_clk, 0x7b000, 14, 6),
	1098	+ [125] = SDC_QDSD_PINGROUP(sdc2_cmd, 0x7b000, 11, 3),
	1099	+ [126] = SDC_QDSD_PINGROUP(sdc2_data, 0x7b000, 9, 0),
1098	1100	};
1099	1101
1100	1102	static const struct msm_pinctrl_soc_data sc7180_pinctrl = {

drivers/pinctrl/qcom/pinctrl-spmi-gpio.c+5−0

@@ -1108,6 +1108,9 @@ static const struct of_device_id pmic_gpio_of_match[] = { · 1107 unmodified lines
1108	1108	{ .compatible = "qcom,pm8005-gpio", .data = (void *) 4 },
1109	1109	{ .compatible = "qcom,pm8916-gpio", .data = (void *) 4 },
1110	1110	{ .compatible = "qcom,pm8941-gpio", .data = (void *) 36 },
	1111	+ /* pm8950 has 8 GPIOs with holes on 3 */
	1112	+ { .compatible = "qcom,pm8950-gpio", .data = (void *) 8 },
	1113	+ { .compatible = "qcom,pmi8950-gpio", .data = (void *) 2 },
1111	1114	{ .compatible = "qcom,pm8994-gpio", .data = (void *) 22 },
1112	1115	{ .compatible = "qcom,pmi8994-gpio", .data = (void *) 10 },
1113	1116	{ .compatible = "qcom,pm8998-gpio", .data = (void *) 26 },
@@ -1121,6 +1124,8 @@ static const struct of_device_id pmic_gpio_of_match[] = { · 7 unmodified lines
1121	1124	{ .compatible = "qcom,pm8150b-gpio", .data = (void *) 12 },
1122	1125	/* pm8150l has 12 GPIOs with holes on 7 */
1123	1126	{ .compatible = "qcom,pm8150l-gpio", .data = (void *) 12 },
	1127	+ { .compatible = "qcom,pm6150-gpio", .data = (void *) 10 },
	1128	+ { .compatible = "qcom,pm6150l-gpio", .data = (void *) 12 },
1124	1129	{ },
1125	1130	};
1126	1131

drivers/pinctrl/qcom/pinctrl-spmi-mpp.c+2−0

@@ -915,6 +915,8 @@ static const struct of_device_id pmic_mpp_of_match[] = { · 914 unmodified lines
915	915	{ .compatible = "qcom,pm8841-mpp" }, /* 4 MPP's */
916	916	{ .compatible = "qcom,pm8916-mpp" }, /* 4 MPP's */
917	917	{ .compatible = "qcom,pm8941-mpp" }, /* 8 MPP's */
	918	+ { .compatible = "qcom,pm8950-mpp" }, /* 4 MPP's */
	919	+ { .compatible = "qcom,pmi8950-mpp" }, /* 4 MPP's */
918	920	{ .compatible = "qcom,pm8994-mpp" }, /* 8 MPP's */
919	921	{ .compatible = "qcom,pma8084-mpp" }, /* 8 MPP's */
920	922	{ .compatible = "qcom,spmi-mpp" }, /* Generic */

drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c+33−88

@@ -56,7 +56,6 @@ · 55 unmodified lines
56	56	/**
57	57	* struct pm8xxx_pin_data - dynamic configuration for a pin
58	58	* @reg: address of the control register
59		− * @irq: IRQ from the PMIC interrupt controller
60	59	* @power_source: logical selected voltage source, mapping in static data
61	60	* is used translate to register values
62	61	* @mode: operating mode for the pin (input/output)
@@ -72,7 +71,6 @@ · 9 unmodified lines
72	71	*/
73	72	struct pm8xxx_pin_data {
74	73	unsigned reg;
75		− int irq;
76	74	u8 power_source;
77	75	u8 mode;
78	76	bool open_drain;
@@ -93,9 +91,6 @@ struct pm8xxx_gpio { · 14 unmodified lines
93	91
94	92	struct pinctrl_desc desc;
95	93	unsigned npins;
96		−
97		− struct fwnode_handle *fwnode;
98		− struct irq_domain *domain;
99	94	};
100	95
101	96	static const struct pinconf_generic_params pm8xxx_gpio_bindings[] = {
@@ -491,13 +486,16 @@ static int pm8xxx_gpio_get(struct gpio_chip *chip, unsigned offset) · 389 unmodified lines
491	486	{
492	487	struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
493	488	struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
	489	+ int ret, irq;
494	490	bool state;
495		− int ret;
496	491
497		− if (pin->mode == PM8XXX_GPIO_MODE_OUTPUT) {
498		− ret = pin->output_value;
499		− } else if (pin->irq >= 0) {
500		− ret = irq_get_irqchip_state(pin->irq, IRQCHIP_STATE_LINE_LEVEL, &state);
	492	+ if (pin->mode == PM8XXX_GPIO_MODE_OUTPUT)
	493	+ return pin->output_value;
	494	+
	495	+ irq = chip->to_irq(chip, offset);
	496	+ if (irq >= 0) {
	497	+ ret = irq_get_irqchip_state(irq, IRQCHIP_STATE_LINE_LEVEL,
	498	+ &state);
501	499	if (!ret)
502	500	ret = !!state;
503	501	} else
@@ -535,37 +533,6 @@ static int pm8xxx_gpio_of_xlate(struct gpio_chip *chip, · 31 unmodified lines
535	533	}
536	534
537	535
538		−static int pm8xxx_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
539		−{
540		− struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
541		− struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
542		− struct irq_fwspec fwspec;
543		− int ret;
544		−
545		− fwspec.fwnode = pctrl->fwnode;
546		− fwspec.param_count = 2;
547		− fwspec.param[0] = offset + PM8XXX_GPIO_PHYSICAL_OFFSET;
548		− fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
549		−
550		− ret = irq_create_fwspec_mapping(&fwspec);
551		−
552		− /*
553		− * Cache the IRQ since pm8xxx_gpio_get() needs this to get determine the
554		− * line level.
555		− */
556		− pin->irq = ret;
557		−
558		− return ret;
559		−}
560		−
561		−static void pm8xxx_gpio_free(struct gpio_chip *chip, unsigned int offset)
562		−{
563		− struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
564		− struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
565		−
566		− pin->irq = -1;
567		−}
568		−
569	536	#ifdef CONFIG_DEBUG_FS
570	537	#include <linux/seq_file.h>
571	538
@@ -624,13 +591,11 @@ static void pm8xxx_gpio_dbg_show(struct seq_file s, struct gpio_chip chip) · 52 unmodified lines
624	591	#endif
625	592
626	593	static const struct gpio_chip pm8xxx_gpio_template = {
627		− .free = pm8xxx_gpio_free,
628	594	.direction_input = pm8xxx_gpio_direction_input,
629	595	.direction_output = pm8xxx_gpio_direction_output,
630	596	.get = pm8xxx_gpio_get,
631	597	.set = pm8xxx_gpio_set,
632	598	.of_xlate = pm8xxx_gpio_of_xlate,
633		− .to_irq = pm8xxx_gpio_to_irq,
634	599	.dbg_show = pm8xxx_gpio_dbg_show,
635	600	.owner = THIS_MODULE,
636	601	};
@@ -712,43 +677,24 @@ static int pm8xxx_domain_translate(struct irq_domain *domain, · 75 unmodified lines
712	677	return 0;
713	678	}
714	679
715		−static int pm8xxx_domain_alloc(struct irq_domain *domain, unsigned int virq,
716		− unsigned int nr_irqs, void *data)
	680	+static unsigned int pm8xxx_child_offset_to_irq(struct gpio_chip *chip,
	681	+ unsigned int offset)
717	682	{
718		− struct pm8xxx_gpio *pctrl = container_of(domain->host_data,
719		− struct pm8xxx_gpio, chip);
720		− struct irq_fwspec *fwspec = data;
721		− struct irq_fwspec parent_fwspec;
722		− irq_hw_number_t hwirq;
723		− unsigned int type;
724		− int ret, i;
725		−
726		− ret = pm8xxx_domain_translate(domain, fwspec, &hwirq, &type);
727		− if (ret)
728		− return ret;
729		−
730		− for (i = 0; i < nr_irqs; i++)
731		− irq_domain_set_info(domain, virq + i, hwirq + i,
732		− &pm8xxx_irq_chip, pctrl, handle_level_irq,
733		− NULL, NULL);
	683	+ return offset + PM8XXX_GPIO_PHYSICAL_OFFSET;
	684	+}
734	685
735		− parent_fwspec.fwnode = domain->parent->fwnode;
736		− parent_fwspec.param_count = 2;
737		− parent_fwspec.param[0] = hwirq + 0xc0;
738		− parent_fwspec.param[1] = fwspec->param[1];
	686	+static int pm8xxx_child_to_parent_hwirq(struct gpio_chip *chip,
	687	+ unsigned int child_hwirq,
	688	+ unsigned int child_type,
	689	+ unsigned int *parent_hwirq,
	690	+ unsigned int *parent_type)
	691	+{
	692	+ *parent_hwirq = child_hwirq + 0xc0;
	693	+ *parent_type = child_type;
739	694
740		− return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
741		− &parent_fwspec);
	695	+ return 0;
742	696	}
743	697
744		−static const struct irq_domain_ops pm8xxx_domain_ops = {
745		− .activate = gpiochip_irq_domain_activate,
746		− .alloc = pm8xxx_domain_alloc,
747		− .deactivate = gpiochip_irq_domain_deactivate,
748		− .free = irq_domain_free_irqs_common,
749		− .translate = pm8xxx_domain_translate,
750		−};
751		−
752	698	static const struct of_device_id pm8xxx_gpio_of_match[] = {
753	699	{ .compatible = "qcom,pm8018-gpio", .data = (void *) 6 },
754	700	{ .compatible = "qcom,pm8038-gpio", .data = (void *) 12 },
@@ -765,6 +711,7 @@ static int pm8xxx_gpio_probe(struct platform_device *pdev) · 10 unmodified lines
765	711	struct irq_domain *parent_domain;
766	712	struct device_node *parent_node;
767	713	struct pinctrl_pin_desc *pins;
	714	+ struct gpio_irq_chip *girq;
768	715	struct pm8xxx_gpio *pctrl;
769	716	int ret, i;
770	717
@@ -800,7 +747,6 @@ static int pm8xxx_gpio_probe(struct platform_device *pdev) · 29 unmodified lines
800	747
801	748	for (i = 0; i < pctrl->desc.npins; i++) {
802	749	pin_data[i].reg = SSBI_REG_ADDR_GPIO(i);
803		− pin_data[i].irq = -1;
804	750
805	751	ret = pm8xxx_pin_populate(pctrl, &pin_data[i]);
806	752	if (ret)
@@ -841,19 +787,21 @@ static int pm8xxx_gpio_probe(struct platform_device *pdev) · 34 unmodified lines
841	787	if (!parent_domain)
842	788	return -ENXIO;
843	789
844		− pctrl->fwnode = of_node_to_fwnode(pctrl->dev->of_node);
845		− pctrl->domain = irq_domain_create_hierarchy(parent_domain, 0,
846		− pctrl->chip.ngpio,
847		− pctrl->fwnode,
848		− &pm8xxx_domain_ops,
849		− &pctrl->chip);
850		− if (!pctrl->domain)
851		− return -ENODEV;
	790	+ girq = &pctrl->chip.irq;
	791	+ girq->chip = &pm8xxx_irq_chip;
	792	+ girq->default_type = IRQ_TYPE_NONE;
	793	+ girq->handler = handle_level_irq;
	794	+ girq->fwnode = of_node_to_fwnode(pctrl->dev->of_node);
	795	+ girq->parent_domain = parent_domain;
	796	+ girq->child_to_parent_hwirq = pm8xxx_child_to_parent_hwirq;
	797	+ girq->populate_parent_fwspec = gpiochip_populate_parent_fwspec_fourcell;
	798	+ girq->child_offset_to_irq = pm8xxx_child_offset_to_irq;
	799	+ girq->child_irq_domain_ops.translate = pm8xxx_domain_translate;
852	800
853	801	ret = gpiochip_add_data(&pctrl->chip, pctrl);
854	802	if (ret) {
855	803	dev_err(&pdev->dev, "failed register gpiochip\n");
856		− goto err_chip_add_data;
	804	+ return ret;
857	805	}
858	806
859	807	/*
@@ -883,8 +831,6 @@ static int pm8xxx_gpio_probe(struct platform_device *pdev) · 23 unmodified lines
883	831
884	832	unregister_gpiochip:
885	833	gpiochip_remove(&pctrl->chip);
886		−err_chip_add_data:
887		− irq_domain_remove(pctrl->domain);
888	834
889	835	return ret;
890	836	}
@@ -894,7 +840,6 @@ static int pm8xxx_gpio_remove(struct platform_device *pdev) · 3 unmodified lines
894	840	struct pm8xxx_gpio *pctrl = platform_get_drvdata(pdev);
895	841
896	842	gpiochip_remove(&pctrl->chip);
897		− irq_domain_remove(pctrl->domain);
898	843
899	844	return 0;
900	845	}

drivers/pinctrl/samsung/pinctrl-exynos.c+11−3

@@ -486,8 +486,10 @@ int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d) · 485 unmodified lines
486	486	if (match) {
487	487	irq_chip = kmemdup(match->data,
488	488	sizeof(*irq_chip), GFP_KERNEL);
489		− if (!irq_chip)
	489	+ if (!irq_chip) {
	490	+ of_node_put(np);
490	491	return -ENOMEM;
	492	+ }
491	493	wkup_np = np;
492	494	break;
493	495	}
@@ -504,6 +506,7 @@ int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d) · 10 unmodified lines
504	506	bank->nr_pins, &exynos_eint_irqd_ops, bank);
505	507	if (!bank->irq_domain) {
506	508	dev_err(dev, "wkup irq domain add failed\n");
	509	+ of_node_put(wkup_np);
507	510	return -ENXIO;
508	511	}
509	512
@@ -518,8 +521,10 @@ int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d) · 8 unmodified lines
518	521	weint_data = devm_kcalloc(dev,
519	522	bank->nr_pins, sizeof(*weint_data),
520	523	GFP_KERNEL);
521		− if (!weint_data)
	524	+ if (!weint_data) {
	525	+ of_node_put(wkup_np);
522	526	return -ENOMEM;
	527	+ }
523	528
524	529	for (idx = 0; idx < bank->nr_pins; ++idx) {
525	530	irq = irq_of_parse_and_map(bank->of_node, idx);
@@ -536,10 +541,13 @@ int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d) · 10 unmodified lines
536	541	}
537	542	}
538	543
539		− if (!muxed_banks)
	544	+ if (!muxed_banks) {
	545	+ of_node_put(wkup_np);
540	546	return 0;
	547	+ }
541	548
542	549	irq = irq_of_parse_and_map(wkup_np, 0);
	550	+ of_node_put(wkup_np);
543	551	if (!irq) {
544	552	dev_err(dev, "irq number for muxed EINTs not found\n");
545	553	return 0;

drivers/pinctrl/samsung/pinctrl-s3c24xx.c+5−1

@@ -490,8 +490,10 @@ static int s3c24xx_eint_init(struct samsung_pinctrl_drv_data *d) · 489 unmodified lines
490	490	return -ENODEV;
491	491
492	492	eint_data = devm_kzalloc(dev, sizeof(*eint_data), GFP_KERNEL);
493		− if (!eint_data)
	493	+ if (!eint_data) {
	494	+ of_node_put(eint_np);
494	495	return -ENOMEM;
	496	+ }
495	497
496	498	eint_data->drvdata = d;
497	499
@@ -503,12 +505,14 @@ static int s3c24xx_eint_init(struct samsung_pinctrl_drv_data *d) · 5 unmodified lines
503	505	irq = irq_of_parse_and_map(eint_np, i);
504	506	if (!irq) {
505	507	dev_err(dev, "failed to get wakeup EINT IRQ %d\n", i);
	508	+ of_node_put(eint_np);
506	509	return -ENXIO;
507	510	}
508	511
509	512	eint_data->parents[i] = irq;
510	513	irq_set_chained_handler_and_data(irq, handlers[i], eint_data);
511	514	}
	515	+ of_node_put(eint_np);
512	516
513	517	bank = d->pin_banks;
514	518	for (i = 0; i < d->nr_banks; ++i, ++bank) {

drivers/pinctrl/samsung/pinctrl-s3c64xx.c+5−1

@@ -704,8 +704,10 @@ static int s3c64xx_eint_eint0_init(struct samsung_pinctrl_drv_data *d) · 703 unmodified lines
704	704	return -ENODEV;
705	705
706	706	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
707		− if (!data)
	707	+ if (!data) {
	708	+ of_node_put(eint0_np);
708	709	return -ENOMEM;
	710	+ }
709	711	data->drvdata = d;
710	712
711	713	for (i = 0; i < NUM_EINT0_IRQ; ++i) {
@@ -714,6 +716,7 @@ static int s3c64xx_eint_eint0_init(struct samsung_pinctrl_drv_data *d) · 2 unmodified lines
714	716	irq = irq_of_parse_and_map(eint0_np, i);
715	717	if (!irq) {
716	718	dev_err(dev, "failed to get wakeup EINT IRQ %d\n", i);
	719	+ of_node_put(eint0_np);
717	720	return -ENXIO;
718	721	}
719	722
@@ -721,6 +724,7 @@ static int s3c64xx_eint_eint0_init(struct samsung_pinctrl_drv_data *d) · 1 unmodified line
721	724	s3c64xx_eint0_handlers[i],
722	725	data);
723	726	}
	727	+ of_node_put(eint0_np);
724	728
725	729	bank = d->pin_banks;
726	730	for (i = 0; i < d->nr_banks; ++i, ++bank) {

drivers/pinctrl/samsung/pinctrl-samsung.c+8−2

@@ -272,6 +272,7 @@ static int samsung_dt_node_to_map(struct pinctrl_dev *pctldev, · 271 unmodified lines
272	272	&reserved_maps, num_maps);
273	273	if (ret < 0) {
274	274	samsung_dt_free_map(pctldev, map, num_maps);
	275	+ of_node_put(np);
275	276	return ret;
276	277	}
277	278	}
@@ -785,8 +786,10 @@ static struct samsung_pmx_func *samsung_pinctrl_create_functions( · 507 unmodified lines
785	786	if (!of_get_child_count(cfg_np)) {
786	787	ret = samsung_pinctrl_create_function(dev, drvdata,
787	788	cfg_np, func);
788		− if (ret < 0)
	789	+ if (ret < 0) {
	790	+ of_node_put(cfg_np);
789	791	return ERR_PTR(ret);
	792	+ }
790	793	if (ret > 0) {
791	794	++func;
792	795	++func_cnt;
@@ -797,8 +800,11 @@ static struct samsung_pmx_func *samsung_pinctrl_create_functions( · 4 unmodified lines
797	800	for_each_child_of_node(cfg_np, func_np) {
798	801	ret = samsung_pinctrl_create_function(dev, drvdata,
799	802	func_np, func);
800		− if (ret < 0)
	803	+ if (ret < 0) {
	804	+ of_node_put(func_np);
	805	+ of_node_put(cfg_np);
801	806	return ERR_PTR(ret);
	807	+ }
802	808	if (ret > 0) {
803	809	++func;
804	810	++func_cnt;

drivers/pinctrl/sh-pfc/Kconfig+10−2

@@ -17,6 +17,7 @@ config PINCTRL_SH_PFC · 16 unmodified lines
17	17	select PINCTRL_PFC_R8A7745 if ARCH_R8A7745
18	18	select PINCTRL_PFC_R8A77470 if ARCH_R8A77470
19	19	select PINCTRL_PFC_R8A774A1 if ARCH_R8A774A1
	20	+ select PINCTRL_PFC_R8A774B1 if ARCH_R8A774B1
20	21	select PINCTRL_PFC_R8A774C0 if ARCH_R8A774C0
21	22	select PINCTRL_PFC_R8A7778 if ARCH_R8A7778
22	23	select PINCTRL_PFC_R8A7779 if ARCH_R8A7779
@@ -26,7 +27,8 @@ config PINCTRL_SH_PFC · 3 unmodified lines
26	27	select PINCTRL_PFC_R8A7793 if ARCH_R8A7793
27	28	select PINCTRL_PFC_R8A7794 if ARCH_R8A7794
28	29	select PINCTRL_PFC_R8A7795 if ARCH_R8A7795
29		− select PINCTRL_PFC_R8A7796 if ARCH_R8A7796
	30	+ select PINCTRL_PFC_R8A77960 if ARCH_R8A77960 \|\| ARCH_R8A7796
	31	+ select PINCTRL_PFC_R8A77961 if ARCH_R8A77961
30	32	select PINCTRL_PFC_R8A77965 if ARCH_R8A77965
31	33	select PINCTRL_PFC_R8A77970 if ARCH_R8A77970
32	34	select PINCTRL_PFC_R8A77980 if ARCH_R8A77980
@@ -86,6 +88,9 @@ config PINCTRL_PFC_R8A77470 · 53 unmodified lines
86	88	config PINCTRL_PFC_R8A774A1
87	89	bool "RZ/G2M pin control support" if COMPILE_TEST
88	90
	91	+config PINCTRL_PFC_R8A774B1
	92	+ bool "RZ/G2N pin control support" if COMPILE_TEST
	93	+
89	94	config PINCTRL_PFC_R8A774C0
90	95	bool "RZ/G2E pin control support" if COMPILE_TEST
91	96
@@ -113,9 +118,12 @@ config PINCTRL_PFC_R8A7794 · 21 unmodified lines
113	118	config PINCTRL_PFC_R8A7795
114	119	bool "R-Car H3 pin control support" if COMPILE_TEST
115	120
116		−config PINCTRL_PFC_R8A7796
	121	+config PINCTRL_PFC_R8A77960
117	122	bool "R-Car M3-W pin control support" if COMPILE_TEST
118	123
	124	+config PINCTRL_PFC_R8A77961
	125	+ bool "R-Car M3-W+ pin control support" if COMPILE_TEST
	126	+
119	127	config PINCTRL_PFC_R8A77965
120	128	bool "R-Car M3-N pin control support" if COMPILE_TEST
121	129

drivers/pinctrl/sh-pfc/Makefile+3−1

@@ -9,6 +9,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7744) += pfc-r8a7791.o · 8 unmodified lines
9	9	obj-$(CONFIG_PINCTRL_PFC_R8A7745) += pfc-r8a7794.o
10	10	obj-$(CONFIG_PINCTRL_PFC_R8A77470) += pfc-r8a77470.o
11	11	obj-$(CONFIG_PINCTRL_PFC_R8A774A1) += pfc-r8a7796.o
	12	+obj-$(CONFIG_PINCTRL_PFC_R8A774B1) += pfc-r8a77965.o
12	13	obj-$(CONFIG_PINCTRL_PFC_R8A774C0) += pfc-r8a77990.o
13	14	obj-$(CONFIG_PINCTRL_PFC_R8A7778) += pfc-r8a7778.o
14	15	obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o
@@ -19,7 +20,8 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7793) += pfc-r8a7791.o · 4 unmodified lines
19	20	obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o
20	21	obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o
21	22	obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795-es1.o
22		−obj-$(CONFIG_PINCTRL_PFC_R8A7796) += pfc-r8a7796.o
	23	+obj-$(CONFIG_PINCTRL_PFC_R8A77960) += pfc-r8a7796.o
	24	+obj-$(CONFIG_PINCTRL_PFC_R8A77961) += pfc-r8a7796.o
23	25	obj-$(CONFIG_PINCTRL_PFC_R8A77965) += pfc-r8a77965.o
24	26	obj-$(CONFIG_PINCTRL_PFC_R8A77970) += pfc-r8a77970.o
25	27	obj-$(CONFIG_PINCTRL_PFC_R8A77980) += pfc-r8a77980.o

drivers/pinctrl/sh-pfc/core.c+20−12

@@ -29,12 +29,12 @@ · 28 unmodified lines
29	29	static int sh_pfc_map_resources(struct sh_pfc *pfc,
30	30	struct platform_device *pdev)
31	31	{
32		− unsigned int num_windows, num_irqs;
33	32	struct sh_pfc_window *windows;
34	33	unsigned int *irqs = NULL;
	34	+ unsigned int num_windows;
35	35	struct resource *res;
36	36	unsigned int i;
37		− int irq;
	37	+ int num_irqs;
38	38
39	39	/* Count the MEM and IRQ resources. */
40	40	for (num_windows = 0;; num_windows++) {
@@ -42,17 +42,13 @@ static int sh_pfc_map_resources(struct sh_pfc *pfc, · 1 unmodified line
42	42	if (!res)
43	43	break;
44	44	}
45		− for (num_irqs = 0;; num_irqs++) {
46		− irq = platform_get_irq(pdev, num_irqs);
47		− if (irq == -EPROBE_DEFER)
48		− return irq;
49		− if (irq < 0)
50		− break;
51		− }
52		−
53	45	if (num_windows == 0)
54	46	return -EINVAL;
55	47
	48	+ num_irqs = platform_irq_count(pdev);
	49	+ if (num_irqs < 0)
	50	+ return num_irqs;
	51	+
56	52	/* Allocate memory windows and IRQs arrays. */
57	53	windows = devm_kcalloc(pfc->dev, num_windows, sizeof(*windows),
58	54	GFP_KERNEL);
@@ -518,6 +514,12 @@ static const struct of_device_id sh_pfc_of_table[] = { · 459 unmodified lines
518	514	.data = &r8a774a1_pinmux_info,
519	515	},
520	516	#endif
	517	+#ifdef CONFIG_PINCTRL_PFC_R8A774B1
	518	+ {
	519	+ .compatible = "renesas,pfc-r8a774b1",
	520	+ .data = &r8a774b1_pinmux_info,
	521	+ },
	522	+#endif
521	523	#ifdef CONFIG_PINCTRL_PFC_R8A774C0
522	524	{
523	525	.compatible = "renesas,pfc-r8a774c0",
@@ -579,10 +581,16 @@ static const struct of_device_id sh_pfc_of_table[] = { · 55 unmodified lines
579	581	},
580	582	#endif /* DEBUG */
581	583	#endif
582		−#ifdef CONFIG_PINCTRL_PFC_R8A7796
	584	+#ifdef CONFIG_PINCTRL_PFC_R8A77960
583	585	{
584	586	.compatible = "renesas,pfc-r8a7796",
585		− .data = &r8a7796_pinmux_info,
	587	+ .data = &r8a77960_pinmux_info,
	588	+ },
	589	+#endif
	590	+#ifdef CONFIG_PINCTRL_PFC_R8A77961
	591	+ {
	592	+ .compatible = "renesas,pfc-r8a77961",
	593	+ .data = &r8a77961_pinmux_info,
586	594	},
587	595	#endif
588	596	#ifdef CONFIG_PINCTRL_PFC_R8A77965

drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c+1−1

@@ -718,7 +718,7 @@ static const u16 pinmux_data[] = { · 717 unmodified lines
718	718	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
719	719	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
720	720	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
721		− PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1),
	721	+ PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1),
722	722
723	723	PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
724	724	PINMUX_IPSR_MSEL(IP1_27_24, A20, I2C_SEL_3_0),

drivers/pinctrl/sh-pfc/pfc-r8a7795.c+1−1

@@ -726,7 +726,7 @@ static const u16 pinmux_data[] = { · 725 unmodified lines
726	726	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
727	727	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
728	728	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
729		− PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1),
	729	+ PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1),
730	730
731	731	PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
732	732	PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),

drivers/pinctrl/sh-pfc/pfc-r8a7796.c+31−4

@@ -1,6 +1,6 @@
1	1	// SPDX-License-Identifier: GPL-2.0
2	2	/*
3		− * R8A7796 processor support - PFC hardware block.
	3	+ * R8A7796 (R-Car M3-W/W+) support - PFC hardware block.
4	4	*
5	5	* Copyright (C) 2016-2019 Renesas Electronics Corp.
6	6	*
@@ -729,7 +729,7 @@ static const u16 pinmux_data[] = { · 722 unmodified lines
729	729	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
730	730	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
731	731	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
732		− PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1),
	732	+ PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1),
733	733
734	734	PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
735	735	PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
@@ -6210,8 +6210,8 @@ const struct sh_pfc_soc_info r8a774a1_pinmux_info = { · 5474 unmodified lines
6210	6210	};
6211	6211	#endif
6212	6212
6213		−#ifdef CONFIG_PINCTRL_PFC_R8A7796
6214		−const struct sh_pfc_soc_info r8a7796_pinmux_info = {
	6213	+#ifdef CONFIG_PINCTRL_PFC_R8A77960
	6214	+const struct sh_pfc_soc_info r8a77960_pinmux_info = {
6215	6215	.name = "r8a77960_pfc",
6216	6216	.ops = &r8a7796_pinmux_ops,
6217	6217	.unlock_reg = 0xe6060000, /* PMMR */
@@ -6236,3 +6236,30 @@ const struct sh_pfc_soc_info r8a7796_pinmux_info = { · 18 unmodified lines
6236	6236	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
6237	6237	};
6238	6238	#endif
	6239	+
	6240	+#ifdef CONFIG_PINCTRL_PFC_R8A77961
	6241	+const struct sh_pfc_soc_info r8a77961_pinmux_info = {
	6242	+ .name = "r8a77961_pfc",
	6243	+ .ops = &r8a7796_pinmux_ops,
	6244	+ .unlock_reg = 0xe6060000, /* PMMR */
	6245	+
	6246	+ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
	6247	+
	6248	+ .pins = pinmux_pins,
	6249	+ .nr_pins = ARRAY_SIZE(pinmux_pins),
	6250	+ .groups = pinmux_groups.common,
	6251	+ .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
	6252	+ ARRAY_SIZE(pinmux_groups.automotive),
	6253	+ .functions = pinmux_functions.common,
	6254	+ .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
	6255	+ ARRAY_SIZE(pinmux_functions.automotive),
	6256	+
	6257	+ .cfg_regs = pinmux_config_regs,
	6258	+ .drive_regs = pinmux_drive_regs,
	6259	+ .bias_regs = pinmux_bias_regs,
	6260	+ .ioctrl_regs = pinmux_ioctrl_regs,
	6261	+
	6262	+ .pinmux_data = pinmux_data,
	6263	+ .pinmux_data_size = ARRAY_SIZE(pinmux_data),
	6264	+};
	6265	+#endif

drivers/pinctrl/sh-pfc/pfc-r8a77965.c+453−410

@@ -732,7 +732,7 @@ static const u16 pinmux_data[] = { · 731 unmodified lines
732	732	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
733	733	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
734	734	PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
735		− PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1),
	735	+ PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1),
736	736
737	737	PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
738	738	PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
@@ -4378,355 +4378,362 @@ static const unsigned int vin5_clk_mux[] = { · 3639 unmodified lines
4378	4378	VI5_CLK_MARK,
4379	4379	};
4380	4380
4381		−static const struct sh_pfc_pin_group pinmux_groups[] = {
4382		− SH_PFC_PIN_GROUP(audio_clk_a_a),
4383		− SH_PFC_PIN_GROUP(audio_clk_a_b),
4384		− SH_PFC_PIN_GROUP(audio_clk_a_c),
4385		− SH_PFC_PIN_GROUP(audio_clk_b_a),
4386		− SH_PFC_PIN_GROUP(audio_clk_b_b),
4387		− SH_PFC_PIN_GROUP(audio_clk_c_a),
4388		− SH_PFC_PIN_GROUP(audio_clk_c_b),
4389		− SH_PFC_PIN_GROUP(audio_clkout_a),
4390		− SH_PFC_PIN_GROUP(audio_clkout_b),
4391		− SH_PFC_PIN_GROUP(audio_clkout_c),
4392		− SH_PFC_PIN_GROUP(audio_clkout_d),
4393		− SH_PFC_PIN_GROUP(audio_clkout1_a),
4394		− SH_PFC_PIN_GROUP(audio_clkout1_b),
4395		− SH_PFC_PIN_GROUP(audio_clkout2_a),
4396		− SH_PFC_PIN_GROUP(audio_clkout2_b),
4397		− SH_PFC_PIN_GROUP(audio_clkout3_a),
4398		− SH_PFC_PIN_GROUP(audio_clkout3_b),
4399		− SH_PFC_PIN_GROUP(avb_link),
4400		− SH_PFC_PIN_GROUP(avb_magic),
4401		− SH_PFC_PIN_GROUP(avb_phy_int),
4402		− SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
4403		− SH_PFC_PIN_GROUP(avb_mdio),
4404		− SH_PFC_PIN_GROUP(avb_mii),
4405		− SH_PFC_PIN_GROUP(avb_avtp_pps),
4406		− SH_PFC_PIN_GROUP(avb_avtp_match_a),
4407		− SH_PFC_PIN_GROUP(avb_avtp_capture_a),
4408		− SH_PFC_PIN_GROUP(avb_avtp_match_b),
4409		− SH_PFC_PIN_GROUP(avb_avtp_capture_b),
4410		− SH_PFC_PIN_GROUP(can0_data_a),
4411		− SH_PFC_PIN_GROUP(can0_data_b),
4412		− SH_PFC_PIN_GROUP(can1_data),
4413		− SH_PFC_PIN_GROUP(can_clk),
4414		− SH_PFC_PIN_GROUP(canfd0_data_a),
4415		− SH_PFC_PIN_GROUP(canfd0_data_b),
4416		− SH_PFC_PIN_GROUP(canfd1_data),
4417		− SH_PFC_PIN_GROUP(drif0_ctrl_a),
4418		− SH_PFC_PIN_GROUP(drif0_data0_a),
4419		− SH_PFC_PIN_GROUP(drif0_data1_a),
4420		− SH_PFC_PIN_GROUP(drif0_ctrl_b),
4421		− SH_PFC_PIN_GROUP(drif0_data0_b),
4422		− SH_PFC_PIN_GROUP(drif0_data1_b),
4423		− SH_PFC_PIN_GROUP(drif0_ctrl_c),
4424		− SH_PFC_PIN_GROUP(drif0_data0_c),
4425		− SH_PFC_PIN_GROUP(drif0_data1_c),
4426		− SH_PFC_PIN_GROUP(drif1_ctrl_a),
4427		− SH_PFC_PIN_GROUP(drif1_data0_a),
4428		− SH_PFC_PIN_GROUP(drif1_data1_a),
4429		− SH_PFC_PIN_GROUP(drif1_ctrl_b),
4430		− SH_PFC_PIN_GROUP(drif1_data0_b),
4431		− SH_PFC_PIN_GROUP(drif1_data1_b),
4432		− SH_PFC_PIN_GROUP(drif1_ctrl_c),
4433		− SH_PFC_PIN_GROUP(drif1_data0_c),
4434		− SH_PFC_PIN_GROUP(drif1_data1_c),
4435		− SH_PFC_PIN_GROUP(drif2_ctrl_a),
4436		− SH_PFC_PIN_GROUP(drif2_data0_a),
4437		− SH_PFC_PIN_GROUP(drif2_data1_a),
4438		− SH_PFC_PIN_GROUP(drif2_ctrl_b),
4439		− SH_PFC_PIN_GROUP(drif2_data0_b),
4440		− SH_PFC_PIN_GROUP(drif2_data1_b),
4441		− SH_PFC_PIN_GROUP(drif3_ctrl_a),
4442		− SH_PFC_PIN_GROUP(drif3_data0_a),
4443		− SH_PFC_PIN_GROUP(drif3_data1_a),
4444		− SH_PFC_PIN_GROUP(drif3_ctrl_b),
4445		− SH_PFC_PIN_GROUP(drif3_data0_b),
4446		− SH_PFC_PIN_GROUP(drif3_data1_b),
4447		− SH_PFC_PIN_GROUP(du_rgb666),
4448		− SH_PFC_PIN_GROUP(du_rgb888),
4449		− SH_PFC_PIN_GROUP(du_clk_out_0),
4450		− SH_PFC_PIN_GROUP(du_clk_out_1),
4451		− SH_PFC_PIN_GROUP(du_sync),
4452		− SH_PFC_PIN_GROUP(du_oddf),
4453		− SH_PFC_PIN_GROUP(du_cde),
4454		− SH_PFC_PIN_GROUP(du_disp),
4455		− SH_PFC_PIN_GROUP(hscif0_data),
4456		− SH_PFC_PIN_GROUP(hscif0_clk),
4457		− SH_PFC_PIN_GROUP(hscif0_ctrl),
4458		− SH_PFC_PIN_GROUP(hscif1_data_a),
4459		− SH_PFC_PIN_GROUP(hscif1_clk_a),
4460		− SH_PFC_PIN_GROUP(hscif1_ctrl_a),
4461		− SH_PFC_PIN_GROUP(hscif1_data_b),
4462		− SH_PFC_PIN_GROUP(hscif1_clk_b),
4463		− SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4464		− SH_PFC_PIN_GROUP(hscif2_data_a),
4465		− SH_PFC_PIN_GROUP(hscif2_clk_a),
4466		− SH_PFC_PIN_GROUP(hscif2_ctrl_a),
4467		− SH_PFC_PIN_GROUP(hscif2_data_b),
4468		− SH_PFC_PIN_GROUP(hscif2_clk_b),
4469		− SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4470		− SH_PFC_PIN_GROUP(hscif2_data_c),
4471		− SH_PFC_PIN_GROUP(hscif2_clk_c),
4472		− SH_PFC_PIN_GROUP(hscif2_ctrl_c),
4473		− SH_PFC_PIN_GROUP(hscif3_data_a),
4474		− SH_PFC_PIN_GROUP(hscif3_clk),
4475		− SH_PFC_PIN_GROUP(hscif3_ctrl),
4476		− SH_PFC_PIN_GROUP(hscif3_data_b),
4477		− SH_PFC_PIN_GROUP(hscif3_data_c),
4478		− SH_PFC_PIN_GROUP(hscif3_data_d),
4479		− SH_PFC_PIN_GROUP(hscif4_data_a),
4480		− SH_PFC_PIN_GROUP(hscif4_clk),
4481		− SH_PFC_PIN_GROUP(hscif4_ctrl),
4482		− SH_PFC_PIN_GROUP(hscif4_data_b),
4483		− SH_PFC_PIN_GROUP(i2c0),
4484		− SH_PFC_PIN_GROUP(i2c1_a),
4485		− SH_PFC_PIN_GROUP(i2c1_b),
4486		− SH_PFC_PIN_GROUP(i2c2_a),
4487		− SH_PFC_PIN_GROUP(i2c2_b),
4488		− SH_PFC_PIN_GROUP(i2c3),
4489		− SH_PFC_PIN_GROUP(i2c5),
4490		− SH_PFC_PIN_GROUP(i2c6_a),
4491		− SH_PFC_PIN_GROUP(i2c6_b),
4492		− SH_PFC_PIN_GROUP(i2c6_c),
4493		− SH_PFC_PIN_GROUP(intc_ex_irq0),
4494		− SH_PFC_PIN_GROUP(intc_ex_irq1),
4495		− SH_PFC_PIN_GROUP(intc_ex_irq2),
4496		− SH_PFC_PIN_GROUP(intc_ex_irq3),
4497		− SH_PFC_PIN_GROUP(intc_ex_irq4),
4498		− SH_PFC_PIN_GROUP(intc_ex_irq5),
4499		− SH_PFC_PIN_GROUP(msiof0_clk),
4500		− SH_PFC_PIN_GROUP(msiof0_sync),
4501		− SH_PFC_PIN_GROUP(msiof0_ss1),
4502		− SH_PFC_PIN_GROUP(msiof0_ss2),
4503		− SH_PFC_PIN_GROUP(msiof0_txd),
4504		− SH_PFC_PIN_GROUP(msiof0_rxd),
4505		− SH_PFC_PIN_GROUP(msiof1_clk_a),
4506		− SH_PFC_PIN_GROUP(msiof1_sync_a),
4507		− SH_PFC_PIN_GROUP(msiof1_ss1_a),
4508		− SH_PFC_PIN_GROUP(msiof1_ss2_a),
4509		− SH_PFC_PIN_GROUP(msiof1_txd_a),
4510		− SH_PFC_PIN_GROUP(msiof1_rxd_a),
4511		− SH_PFC_PIN_GROUP(msiof1_clk_b),
4512		− SH_PFC_PIN_GROUP(msiof1_sync_b),
4513		− SH_PFC_PIN_GROUP(msiof1_ss1_b),
4514		− SH_PFC_PIN_GROUP(msiof1_ss2_b),
4515		− SH_PFC_PIN_GROUP(msiof1_txd_b),
4516		− SH_PFC_PIN_GROUP(msiof1_rxd_b),
4517		− SH_PFC_PIN_GROUP(msiof1_clk_c),
4518		− SH_PFC_PIN_GROUP(msiof1_sync_c),
4519		− SH_PFC_PIN_GROUP(msiof1_ss1_c),
4520		− SH_PFC_PIN_GROUP(msiof1_ss2_c),
4521		− SH_PFC_PIN_GROUP(msiof1_txd_c),
4522		− SH_PFC_PIN_GROUP(msiof1_rxd_c),
4523		− SH_PFC_PIN_GROUP(msiof1_clk_d),
4524		− SH_PFC_PIN_GROUP(msiof1_sync_d),
4525		− SH_PFC_PIN_GROUP(msiof1_ss1_d),
4526		− SH_PFC_PIN_GROUP(msiof1_ss2_d),
4527		− SH_PFC_PIN_GROUP(msiof1_txd_d),
4528		− SH_PFC_PIN_GROUP(msiof1_rxd_d),
4529		− SH_PFC_PIN_GROUP(msiof1_clk_e),
4530		− SH_PFC_PIN_GROUP(msiof1_sync_e),
4531		− SH_PFC_PIN_GROUP(msiof1_ss1_e),
4532		− SH_PFC_PIN_GROUP(msiof1_ss2_e),
4533		− SH_PFC_PIN_GROUP(msiof1_txd_e),
4534		− SH_PFC_PIN_GROUP(msiof1_rxd_e),
4535		− SH_PFC_PIN_GROUP(msiof1_clk_f),
4536		− SH_PFC_PIN_GROUP(msiof1_sync_f),
4537		− SH_PFC_PIN_GROUP(msiof1_ss1_f),
4538		− SH_PFC_PIN_GROUP(msiof1_ss2_f),
4539		− SH_PFC_PIN_GROUP(msiof1_txd_f),
4540		− SH_PFC_PIN_GROUP(msiof1_rxd_f),
4541		− SH_PFC_PIN_GROUP(msiof1_clk_g),
4542		− SH_PFC_PIN_GROUP(msiof1_sync_g),
4543		− SH_PFC_PIN_GROUP(msiof1_ss1_g),
4544		− SH_PFC_PIN_GROUP(msiof1_ss2_g),
4545		− SH_PFC_PIN_GROUP(msiof1_txd_g),
4546		− SH_PFC_PIN_GROUP(msiof1_rxd_g),
4547		− SH_PFC_PIN_GROUP(msiof2_clk_a),
4548		− SH_PFC_PIN_GROUP(msiof2_sync_a),
4549		− SH_PFC_PIN_GROUP(msiof2_ss1_a),
4550		− SH_PFC_PIN_GROUP(msiof2_ss2_a),
4551		− SH_PFC_PIN_GROUP(msiof2_txd_a),
4552		− SH_PFC_PIN_GROUP(msiof2_rxd_a),
4553		− SH_PFC_PIN_GROUP(msiof2_clk_b),
4554		− SH_PFC_PIN_GROUP(msiof2_sync_b),
4555		− SH_PFC_PIN_GROUP(msiof2_ss1_b),
4556		− SH_PFC_PIN_GROUP(msiof2_ss2_b),
4557		− SH_PFC_PIN_GROUP(msiof2_txd_b),
4558		− SH_PFC_PIN_GROUP(msiof2_rxd_b),
4559		− SH_PFC_PIN_GROUP(msiof2_clk_c),
4560		− SH_PFC_PIN_GROUP(msiof2_sync_c),
4561		− SH_PFC_PIN_GROUP(msiof2_ss1_c),
4562		− SH_PFC_PIN_GROUP(msiof2_ss2_c),
4563		− SH_PFC_PIN_GROUP(msiof2_txd_c),
4564		− SH_PFC_PIN_GROUP(msiof2_rxd_c),
4565		− SH_PFC_PIN_GROUP(msiof2_clk_d),
4566		− SH_PFC_PIN_GROUP(msiof2_sync_d),
4567		− SH_PFC_PIN_GROUP(msiof2_ss1_d),
4568		− SH_PFC_PIN_GROUP(msiof2_ss2_d),
4569		− SH_PFC_PIN_GROUP(msiof2_txd_d),
4570		− SH_PFC_PIN_GROUP(msiof2_rxd_d),
4571		− SH_PFC_PIN_GROUP(msiof3_clk_a),
4572		− SH_PFC_PIN_GROUP(msiof3_sync_a),
4573		− SH_PFC_PIN_GROUP(msiof3_ss1_a),
4574		− SH_PFC_PIN_GROUP(msiof3_ss2_a),
4575		− SH_PFC_PIN_GROUP(msiof3_txd_a),
4576		− SH_PFC_PIN_GROUP(msiof3_rxd_a),
4577		− SH_PFC_PIN_GROUP(msiof3_clk_b),
4578		− SH_PFC_PIN_GROUP(msiof3_sync_b),
4579		− SH_PFC_PIN_GROUP(msiof3_ss1_b),
4580		− SH_PFC_PIN_GROUP(msiof3_ss2_b),
4581		− SH_PFC_PIN_GROUP(msiof3_txd_b),
4582		− SH_PFC_PIN_GROUP(msiof3_rxd_b),
4583		− SH_PFC_PIN_GROUP(msiof3_clk_c),
4584		− SH_PFC_PIN_GROUP(msiof3_sync_c),
4585		− SH_PFC_PIN_GROUP(msiof3_txd_c),
4586		− SH_PFC_PIN_GROUP(msiof3_rxd_c),
4587		− SH_PFC_PIN_GROUP(msiof3_clk_d),
4588		− SH_PFC_PIN_GROUP(msiof3_sync_d),
4589		− SH_PFC_PIN_GROUP(msiof3_ss1_d),
4590		− SH_PFC_PIN_GROUP(msiof3_txd_d),
4591		− SH_PFC_PIN_GROUP(msiof3_rxd_d),
4592		− SH_PFC_PIN_GROUP(msiof3_clk_e),
4593		− SH_PFC_PIN_GROUP(msiof3_sync_e),
4594		− SH_PFC_PIN_GROUP(msiof3_ss1_e),
4595		− SH_PFC_PIN_GROUP(msiof3_ss2_e),
4596		− SH_PFC_PIN_GROUP(msiof3_txd_e),
4597		− SH_PFC_PIN_GROUP(msiof3_rxd_e),
4598		− SH_PFC_PIN_GROUP(pwm0),
4599		− SH_PFC_PIN_GROUP(pwm1_a),
4600		− SH_PFC_PIN_GROUP(pwm1_b),
4601		− SH_PFC_PIN_GROUP(pwm2_a),
4602		− SH_PFC_PIN_GROUP(pwm2_b),
4603		− SH_PFC_PIN_GROUP(pwm3_a),
4604		− SH_PFC_PIN_GROUP(pwm3_b),
4605		− SH_PFC_PIN_GROUP(pwm4_a),
4606		− SH_PFC_PIN_GROUP(pwm4_b),
4607		− SH_PFC_PIN_GROUP(pwm5_a),
4608		− SH_PFC_PIN_GROUP(pwm5_b),
4609		− SH_PFC_PIN_GROUP(pwm6_a),
4610		− SH_PFC_PIN_GROUP(pwm6_b),
4611		− SH_PFC_PIN_GROUP(sata0_devslp_a),
4612		− SH_PFC_PIN_GROUP(sata0_devslp_b),
4613		− SH_PFC_PIN_GROUP(scif0_data),
4614		− SH_PFC_PIN_GROUP(scif0_clk),
4615		− SH_PFC_PIN_GROUP(scif0_ctrl),
4616		− SH_PFC_PIN_GROUP(scif1_data_a),
4617		− SH_PFC_PIN_GROUP(scif1_clk),
4618		− SH_PFC_PIN_GROUP(scif1_ctrl),
4619		− SH_PFC_PIN_GROUP(scif1_data_b),
4620		− SH_PFC_PIN_GROUP(scif2_data_a),
4621		− SH_PFC_PIN_GROUP(scif2_clk),
4622		− SH_PFC_PIN_GROUP(scif2_data_b),
4623		− SH_PFC_PIN_GROUP(scif3_data_a),
4624		− SH_PFC_PIN_GROUP(scif3_clk),
4625		− SH_PFC_PIN_GROUP(scif3_ctrl),
4626		− SH_PFC_PIN_GROUP(scif3_data_b),
4627		− SH_PFC_PIN_GROUP(scif4_data_a),
4628		− SH_PFC_PIN_GROUP(scif4_clk_a),
4629		− SH_PFC_PIN_GROUP(scif4_ctrl_a),
4630		− SH_PFC_PIN_GROUP(scif4_data_b),
4631		− SH_PFC_PIN_GROUP(scif4_clk_b),
4632		− SH_PFC_PIN_GROUP(scif4_ctrl_b),
4633		− SH_PFC_PIN_GROUP(scif4_data_c),
4634		− SH_PFC_PIN_GROUP(scif4_clk_c),
4635		− SH_PFC_PIN_GROUP(scif4_ctrl_c),
4636		− SH_PFC_PIN_GROUP(scif5_data_a),
4637		− SH_PFC_PIN_GROUP(scif5_clk_a),
4638		− SH_PFC_PIN_GROUP(scif5_data_b),
4639		− SH_PFC_PIN_GROUP(scif5_clk_b),
4640		− SH_PFC_PIN_GROUP(scif_clk_a),
4641		− SH_PFC_PIN_GROUP(scif_clk_b),
4642		− SH_PFC_PIN_GROUP(sdhi0_data1),
4643		− SH_PFC_PIN_GROUP(sdhi0_data4),
4644		− SH_PFC_PIN_GROUP(sdhi0_ctrl),
4645		− SH_PFC_PIN_GROUP(sdhi0_cd),
4646		− SH_PFC_PIN_GROUP(sdhi0_wp),
4647		− SH_PFC_PIN_GROUP(sdhi1_data1),
4648		− SH_PFC_PIN_GROUP(sdhi1_data4),
4649		− SH_PFC_PIN_GROUP(sdhi1_ctrl),
4650		− SH_PFC_PIN_GROUP(sdhi1_cd),
4651		− SH_PFC_PIN_GROUP(sdhi1_wp),
4652		− SH_PFC_PIN_GROUP(sdhi2_data1),
4653		− SH_PFC_PIN_GROUP(sdhi2_data4),
4654		− SH_PFC_PIN_GROUP(sdhi2_data8),
4655		− SH_PFC_PIN_GROUP(sdhi2_ctrl),
4656		− SH_PFC_PIN_GROUP(sdhi2_cd_a),
4657		− SH_PFC_PIN_GROUP(sdhi2_wp_a),
4658		− SH_PFC_PIN_GROUP(sdhi2_cd_b),
4659		− SH_PFC_PIN_GROUP(sdhi2_wp_b),
4660		− SH_PFC_PIN_GROUP(sdhi2_ds),
4661		− SH_PFC_PIN_GROUP(sdhi3_data1),
4662		− SH_PFC_PIN_GROUP(sdhi3_data4),
4663		− SH_PFC_PIN_GROUP(sdhi3_data8),
4664		− SH_PFC_PIN_GROUP(sdhi3_ctrl),
4665		− SH_PFC_PIN_GROUP(sdhi3_cd),
4666		− SH_PFC_PIN_GROUP(sdhi3_wp),
4667		− SH_PFC_PIN_GROUP(sdhi3_ds),
4668		− SH_PFC_PIN_GROUP(ssi0_data),
4669		− SH_PFC_PIN_GROUP(ssi01239_ctrl),
4670		− SH_PFC_PIN_GROUP(ssi1_data_a),
4671		− SH_PFC_PIN_GROUP(ssi1_data_b),
4672		− SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4673		− SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4674		− SH_PFC_PIN_GROUP(ssi2_data_a),
4675		− SH_PFC_PIN_GROUP(ssi2_data_b),
4676		− SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4677		− SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4678		− SH_PFC_PIN_GROUP(ssi3_data),
4679		− SH_PFC_PIN_GROUP(ssi349_ctrl),
4680		− SH_PFC_PIN_GROUP(ssi4_data),
4681		− SH_PFC_PIN_GROUP(ssi4_ctrl),
4682		− SH_PFC_PIN_GROUP(ssi5_data),
4683		− SH_PFC_PIN_GROUP(ssi5_ctrl),
4684		− SH_PFC_PIN_GROUP(ssi6_data),
4685		− SH_PFC_PIN_GROUP(ssi6_ctrl),
4686		− SH_PFC_PIN_GROUP(ssi7_data),
4687		− SH_PFC_PIN_GROUP(ssi78_ctrl),
4688		− SH_PFC_PIN_GROUP(ssi8_data),
4689		− SH_PFC_PIN_GROUP(ssi9_data_a),
4690		− SH_PFC_PIN_GROUP(ssi9_data_b),
4691		− SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4692		− SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4693		− SH_PFC_PIN_GROUP(tmu_tclk1_a),
4694		− SH_PFC_PIN_GROUP(tmu_tclk1_b),
4695		− SH_PFC_PIN_GROUP(tmu_tclk2_a),
4696		− SH_PFC_PIN_GROUP(tmu_tclk2_b),
4697		− SH_PFC_PIN_GROUP(tpu_to0),
4698		− SH_PFC_PIN_GROUP(tpu_to1),
4699		− SH_PFC_PIN_GROUP(tpu_to2),
4700		− SH_PFC_PIN_GROUP(tpu_to3),
4701		− SH_PFC_PIN_GROUP(usb0),
4702		− SH_PFC_PIN_GROUP(usb1),
4703		− SH_PFC_PIN_GROUP(usb30),
4704		− VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
4705		− VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
4706		− VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
4707		− VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
4708		− SH_PFC_PIN_GROUP(vin4_data18_a),
4709		− VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
4710		− VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
4711		− VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
4712		− VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
4713		− VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
4714		− VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
4715		− SH_PFC_PIN_GROUP(vin4_data18_b),
4716		− VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
4717		− VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
4718		− SH_PFC_PIN_GROUP(vin4_sync),
4719		− SH_PFC_PIN_GROUP(vin4_field),
4720		− SH_PFC_PIN_GROUP(vin4_clkenb),
4721		− SH_PFC_PIN_GROUP(vin4_clk),
4722		− VIN_DATA_PIN_GROUP(vin5_data, 8),
4723		− VIN_DATA_PIN_GROUP(vin5_data, 10),
4724		− VIN_DATA_PIN_GROUP(vin5_data, 12),
4725		− VIN_DATA_PIN_GROUP(vin5_data, 16),
4726		− SH_PFC_PIN_GROUP(vin5_sync),
4727		− SH_PFC_PIN_GROUP(vin5_field),
4728		− SH_PFC_PIN_GROUP(vin5_clkenb),
4729		− SH_PFC_PIN_GROUP(vin5_clk),
	4381	+static const struct {
	4382	+ struct sh_pfc_pin_group common[318];
	4383	+ struct sh_pfc_pin_group automotive[30];
	4384	+} pinmux_groups = {
	4385	+ .common = {
	4386	+ SH_PFC_PIN_GROUP(audio_clk_a_a),
	4387	+ SH_PFC_PIN_GROUP(audio_clk_a_b),
	4388	+ SH_PFC_PIN_GROUP(audio_clk_a_c),
	4389	+ SH_PFC_PIN_GROUP(audio_clk_b_a),
	4390	+ SH_PFC_PIN_GROUP(audio_clk_b_b),
	4391	+ SH_PFC_PIN_GROUP(audio_clk_c_a),
	4392	+ SH_PFC_PIN_GROUP(audio_clk_c_b),
	4393	+ SH_PFC_PIN_GROUP(audio_clkout_a),
	4394	+ SH_PFC_PIN_GROUP(audio_clkout_b),
	4395	+ SH_PFC_PIN_GROUP(audio_clkout_c),
	4396	+ SH_PFC_PIN_GROUP(audio_clkout_d),
	4397	+ SH_PFC_PIN_GROUP(audio_clkout1_a),
	4398	+ SH_PFC_PIN_GROUP(audio_clkout1_b),
	4399	+ SH_PFC_PIN_GROUP(audio_clkout2_a),
	4400	+ SH_PFC_PIN_GROUP(audio_clkout2_b),
	4401	+ SH_PFC_PIN_GROUP(audio_clkout3_a),
	4402	+ SH_PFC_PIN_GROUP(audio_clkout3_b),
	4403	+ SH_PFC_PIN_GROUP(avb_link),
	4404	+ SH_PFC_PIN_GROUP(avb_magic),
	4405	+ SH_PFC_PIN_GROUP(avb_phy_int),
	4406	+ SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
	4407	+ SH_PFC_PIN_GROUP(avb_mdio),
	4408	+ SH_PFC_PIN_GROUP(avb_mii),
	4409	+ SH_PFC_PIN_GROUP(avb_avtp_pps),
	4410	+ SH_PFC_PIN_GROUP(avb_avtp_match_a),
	4411	+ SH_PFC_PIN_GROUP(avb_avtp_capture_a),
	4412	+ SH_PFC_PIN_GROUP(avb_avtp_match_b),
	4413	+ SH_PFC_PIN_GROUP(avb_avtp_capture_b),
	4414	+ SH_PFC_PIN_GROUP(can0_data_a),
	4415	+ SH_PFC_PIN_GROUP(can0_data_b),
	4416	+ SH_PFC_PIN_GROUP(can1_data),
	4417	+ SH_PFC_PIN_GROUP(can_clk),
	4418	+ SH_PFC_PIN_GROUP(canfd0_data_a),
	4419	+ SH_PFC_PIN_GROUP(canfd0_data_b),
	4420	+ SH_PFC_PIN_GROUP(canfd1_data),
	4421	+ SH_PFC_PIN_GROUP(du_rgb666),
	4422	+ SH_PFC_PIN_GROUP(du_rgb888),
	4423	+ SH_PFC_PIN_GROUP(du_clk_out_0),
	4424	+ SH_PFC_PIN_GROUP(du_clk_out_1),
	4425	+ SH_PFC_PIN_GROUP(du_sync),
	4426	+ SH_PFC_PIN_GROUP(du_oddf),
	4427	+ SH_PFC_PIN_GROUP(du_cde),
	4428	+ SH_PFC_PIN_GROUP(du_disp),
	4429	+ SH_PFC_PIN_GROUP(hscif0_data),
	4430	+ SH_PFC_PIN_GROUP(hscif0_clk),
	4431	+ SH_PFC_PIN_GROUP(hscif0_ctrl),
	4432	+ SH_PFC_PIN_GROUP(hscif1_data_a),
	4433	+ SH_PFC_PIN_GROUP(hscif1_clk_a),
	4434	+ SH_PFC_PIN_GROUP(hscif1_ctrl_a),
	4435	+ SH_PFC_PIN_GROUP(hscif1_data_b),
	4436	+ SH_PFC_PIN_GROUP(hscif1_clk_b),
	4437	+ SH_PFC_PIN_GROUP(hscif1_ctrl_b),
	4438	+ SH_PFC_PIN_GROUP(hscif2_data_a),
	4439	+ SH_PFC_PIN_GROUP(hscif2_clk_a),
	4440	+ SH_PFC_PIN_GROUP(hscif2_ctrl_a),
	4441	+ SH_PFC_PIN_GROUP(hscif2_data_b),
	4442	+ SH_PFC_PIN_GROUP(hscif2_clk_b),
	4443	+ SH_PFC_PIN_GROUP(hscif2_ctrl_b),
	4444	+ SH_PFC_PIN_GROUP(hscif2_data_c),
	4445	+ SH_PFC_PIN_GROUP(hscif2_clk_c),
	4446	+ SH_PFC_PIN_GROUP(hscif2_ctrl_c),
	4447	+ SH_PFC_PIN_GROUP(hscif3_data_a),
	4448	+ SH_PFC_PIN_GROUP(hscif3_clk),
	4449	+ SH_PFC_PIN_GROUP(hscif3_ctrl),
	4450	+ SH_PFC_PIN_GROUP(hscif3_data_b),
	4451	+ SH_PFC_PIN_GROUP(hscif3_data_c),
	4452	+ SH_PFC_PIN_GROUP(hscif3_data_d),
	4453	+ SH_PFC_PIN_GROUP(hscif4_data_a),
	4454	+ SH_PFC_PIN_GROUP(hscif4_clk),
	4455	+ SH_PFC_PIN_GROUP(hscif4_ctrl),
	4456	+ SH_PFC_PIN_GROUP(hscif4_data_b),
	4457	+ SH_PFC_PIN_GROUP(i2c0),
	4458	+ SH_PFC_PIN_GROUP(i2c1_a),
	4459	+ SH_PFC_PIN_GROUP(i2c1_b),
	4460	+ SH_PFC_PIN_GROUP(i2c2_a),
	4461	+ SH_PFC_PIN_GROUP(i2c2_b),
	4462	+ SH_PFC_PIN_GROUP(i2c3),
	4463	+ SH_PFC_PIN_GROUP(i2c5),
	4464	+ SH_PFC_PIN_GROUP(i2c6_a),
	4465	+ SH_PFC_PIN_GROUP(i2c6_b),
	4466	+ SH_PFC_PIN_GROUP(i2c6_c),
	4467	+ SH_PFC_PIN_GROUP(intc_ex_irq0),
	4468	+ SH_PFC_PIN_GROUP(intc_ex_irq1),
	4469	+ SH_PFC_PIN_GROUP(intc_ex_irq2),
	4470	+ SH_PFC_PIN_GROUP(intc_ex_irq3),
	4471	+ SH_PFC_PIN_GROUP(intc_ex_irq4),
	4472	+ SH_PFC_PIN_GROUP(intc_ex_irq5),
	4473	+ SH_PFC_PIN_GROUP(msiof0_clk),
	4474	+ SH_PFC_PIN_GROUP(msiof0_sync),
	4475	+ SH_PFC_PIN_GROUP(msiof0_ss1),
	4476	+ SH_PFC_PIN_GROUP(msiof0_ss2),
	4477	+ SH_PFC_PIN_GROUP(msiof0_txd),
	4478	+ SH_PFC_PIN_GROUP(msiof0_rxd),
	4479	+ SH_PFC_PIN_GROUP(msiof1_clk_a),
	4480	+ SH_PFC_PIN_GROUP(msiof1_sync_a),
	4481	+ SH_PFC_PIN_GROUP(msiof1_ss1_a),
	4482	+ SH_PFC_PIN_GROUP(msiof1_ss2_a),
	4483	+ SH_PFC_PIN_GROUP(msiof1_txd_a),
	4484	+ SH_PFC_PIN_GROUP(msiof1_rxd_a),
	4485	+ SH_PFC_PIN_GROUP(msiof1_clk_b),
	4486	+ SH_PFC_PIN_GROUP(msiof1_sync_b),
	4487	+ SH_PFC_PIN_GROUP(msiof1_ss1_b),
	4488	+ SH_PFC_PIN_GROUP(msiof1_ss2_b),
	4489	+ SH_PFC_PIN_GROUP(msiof1_txd_b),
	4490	+ SH_PFC_PIN_GROUP(msiof1_rxd_b),
	4491	+ SH_PFC_PIN_GROUP(msiof1_clk_c),
	4492	+ SH_PFC_PIN_GROUP(msiof1_sync_c),
	4493	+ SH_PFC_PIN_GROUP(msiof1_ss1_c),
	4494	+ SH_PFC_PIN_GROUP(msiof1_ss2_c),
	4495	+ SH_PFC_PIN_GROUP(msiof1_txd_c),
	4496	+ SH_PFC_PIN_GROUP(msiof1_rxd_c),
	4497	+ SH_PFC_PIN_GROUP(msiof1_clk_d),
	4498	+ SH_PFC_PIN_GROUP(msiof1_sync_d),
	4499	+ SH_PFC_PIN_GROUP(msiof1_ss1_d),
	4500	+ SH_PFC_PIN_GROUP(msiof1_ss2_d),
	4501	+ SH_PFC_PIN_GROUP(msiof1_txd_d),
	4502	+ SH_PFC_PIN_GROUP(msiof1_rxd_d),
	4503	+ SH_PFC_PIN_GROUP(msiof1_clk_e),
	4504	+ SH_PFC_PIN_GROUP(msiof1_sync_e),
	4505	+ SH_PFC_PIN_GROUP(msiof1_ss1_e),
	4506	+ SH_PFC_PIN_GROUP(msiof1_ss2_e),
	4507	+ SH_PFC_PIN_GROUP(msiof1_txd_e),
	4508	+ SH_PFC_PIN_GROUP(msiof1_rxd_e),
	4509	+ SH_PFC_PIN_GROUP(msiof1_clk_f),
	4510	+ SH_PFC_PIN_GROUP(msiof1_sync_f),
	4511	+ SH_PFC_PIN_GROUP(msiof1_ss1_f),
	4512	+ SH_PFC_PIN_GROUP(msiof1_ss2_f),
	4513	+ SH_PFC_PIN_GROUP(msiof1_txd_f),
	4514	+ SH_PFC_PIN_GROUP(msiof1_rxd_f),
	4515	+ SH_PFC_PIN_GROUP(msiof1_clk_g),
	4516	+ SH_PFC_PIN_GROUP(msiof1_sync_g),
	4517	+ SH_PFC_PIN_GROUP(msiof1_ss1_g),
	4518	+ SH_PFC_PIN_GROUP(msiof1_ss2_g),
	4519	+ SH_PFC_PIN_GROUP(msiof1_txd_g),
	4520	+ SH_PFC_PIN_GROUP(msiof1_rxd_g),
	4521	+ SH_PFC_PIN_GROUP(msiof2_clk_a),
	4522	+ SH_PFC_PIN_GROUP(msiof2_sync_a),
	4523	+ SH_PFC_PIN_GROUP(msiof2_ss1_a),
	4524	+ SH_PFC_PIN_GROUP(msiof2_ss2_a),
	4525	+ SH_PFC_PIN_GROUP(msiof2_txd_a),
	4526	+ SH_PFC_PIN_GROUP(msiof2_rxd_a),
	4527	+ SH_PFC_PIN_GROUP(msiof2_clk_b),
	4528	+ SH_PFC_PIN_GROUP(msiof2_sync_b),
	4529	+ SH_PFC_PIN_GROUP(msiof2_ss1_b),
	4530	+ SH_PFC_PIN_GROUP(msiof2_ss2_b),
	4531	+ SH_PFC_PIN_GROUP(msiof2_txd_b),
	4532	+ SH_PFC_PIN_GROUP(msiof2_rxd_b),
	4533	+ SH_PFC_PIN_GROUP(msiof2_clk_c),
	4534	+ SH_PFC_PIN_GROUP(msiof2_sync_c),
	4535	+ SH_PFC_PIN_GROUP(msiof2_ss1_c),
	4536	+ SH_PFC_PIN_GROUP(msiof2_ss2_c),
	4537	+ SH_PFC_PIN_GROUP(msiof2_txd_c),
	4538	+ SH_PFC_PIN_GROUP(msiof2_rxd_c),
	4539	+ SH_PFC_PIN_GROUP(msiof2_clk_d),
	4540	+ SH_PFC_PIN_GROUP(msiof2_sync_d),
	4541	+ SH_PFC_PIN_GROUP(msiof2_ss1_d),
	4542	+ SH_PFC_PIN_GROUP(msiof2_ss2_d),
	4543	+ SH_PFC_PIN_GROUP(msiof2_txd_d),
	4544	+ SH_PFC_PIN_GROUP(msiof2_rxd_d),
	4545	+ SH_PFC_PIN_GROUP(msiof3_clk_a),
	4546	+ SH_PFC_PIN_GROUP(msiof3_sync_a),
	4547	+ SH_PFC_PIN_GROUP(msiof3_ss1_a),
	4548	+ SH_PFC_PIN_GROUP(msiof3_ss2_a),
	4549	+ SH_PFC_PIN_GROUP(msiof3_txd_a),
	4550	+ SH_PFC_PIN_GROUP(msiof3_rxd_a),
	4551	+ SH_PFC_PIN_GROUP(msiof3_clk_b),
	4552	+ SH_PFC_PIN_GROUP(msiof3_sync_b),
	4553	+ SH_PFC_PIN_GROUP(msiof3_ss1_b),
	4554	+ SH_PFC_PIN_GROUP(msiof3_ss2_b),
	4555	+ SH_PFC_PIN_GROUP(msiof3_txd_b),
	4556	+ SH_PFC_PIN_GROUP(msiof3_rxd_b),
	4557	+ SH_PFC_PIN_GROUP(msiof3_clk_c),
	4558	+ SH_PFC_PIN_GROUP(msiof3_sync_c),
	4559	+ SH_PFC_PIN_GROUP(msiof3_txd_c),
	4560	+ SH_PFC_PIN_GROUP(msiof3_rxd_c),
	4561	+ SH_PFC_PIN_GROUP(msiof3_clk_d),
	4562	+ SH_PFC_PIN_GROUP(msiof3_sync_d),
	4563	+ SH_PFC_PIN_GROUP(msiof3_ss1_d),
	4564	+ SH_PFC_PIN_GROUP(msiof3_txd_d),
	4565	+ SH_PFC_PIN_GROUP(msiof3_rxd_d),
	4566	+ SH_PFC_PIN_GROUP(msiof3_clk_e),
	4567	+ SH_PFC_PIN_GROUP(msiof3_sync_e),
	4568	+ SH_PFC_PIN_GROUP(msiof3_ss1_e),
	4569	+ SH_PFC_PIN_GROUP(msiof3_ss2_e),
	4570	+ SH_PFC_PIN_GROUP(msiof3_txd_e),
	4571	+ SH_PFC_PIN_GROUP(msiof3_rxd_e),
	4572	+ SH_PFC_PIN_GROUP(pwm0),
	4573	+ SH_PFC_PIN_GROUP(pwm1_a),
	4574	+ SH_PFC_PIN_GROUP(pwm1_b),
	4575	+ SH_PFC_PIN_GROUP(pwm2_a),
	4576	+ SH_PFC_PIN_GROUP(pwm2_b),
	4577	+ SH_PFC_PIN_GROUP(pwm3_a),
	4578	+ SH_PFC_PIN_GROUP(pwm3_b),
	4579	+ SH_PFC_PIN_GROUP(pwm4_a),
	4580	+ SH_PFC_PIN_GROUP(pwm4_b),
	4581	+ SH_PFC_PIN_GROUP(pwm5_a),
	4582	+ SH_PFC_PIN_GROUP(pwm5_b),
	4583	+ SH_PFC_PIN_GROUP(pwm6_a),
	4584	+ SH_PFC_PIN_GROUP(pwm6_b),
	4585	+ SH_PFC_PIN_GROUP(sata0_devslp_a),
	4586	+ SH_PFC_PIN_GROUP(sata0_devslp_b),
	4587	+ SH_PFC_PIN_GROUP(scif0_data),
	4588	+ SH_PFC_PIN_GROUP(scif0_clk),
	4589	+ SH_PFC_PIN_GROUP(scif0_ctrl),
	4590	+ SH_PFC_PIN_GROUP(scif1_data_a),
	4591	+ SH_PFC_PIN_GROUP(scif1_clk),
	4592	+ SH_PFC_PIN_GROUP(scif1_ctrl),
	4593	+ SH_PFC_PIN_GROUP(scif1_data_b),
	4594	+ SH_PFC_PIN_GROUP(scif2_data_a),
	4595	+ SH_PFC_PIN_GROUP(scif2_clk),
	4596	+ SH_PFC_PIN_GROUP(scif2_data_b),
	4597	+ SH_PFC_PIN_GROUP(scif3_data_a),
	4598	+ SH_PFC_PIN_GROUP(scif3_clk),
	4599	+ SH_PFC_PIN_GROUP(scif3_ctrl),
	4600	+ SH_PFC_PIN_GROUP(scif3_data_b),
	4601	+ SH_PFC_PIN_GROUP(scif4_data_a),
	4602	+ SH_PFC_PIN_GROUP(scif4_clk_a),
	4603	+ SH_PFC_PIN_GROUP(scif4_ctrl_a),
	4604	+ SH_PFC_PIN_GROUP(scif4_data_b),
	4605	+ SH_PFC_PIN_GROUP(scif4_clk_b),
	4606	+ SH_PFC_PIN_GROUP(scif4_ctrl_b),
	4607	+ SH_PFC_PIN_GROUP(scif4_data_c),
	4608	+ SH_PFC_PIN_GROUP(scif4_clk_c),
	4609	+ SH_PFC_PIN_GROUP(scif4_ctrl_c),
	4610	+ SH_PFC_PIN_GROUP(scif5_data_a),
	4611	+ SH_PFC_PIN_GROUP(scif5_clk_a),
	4612	+ SH_PFC_PIN_GROUP(scif5_data_b),
	4613	+ SH_PFC_PIN_GROUP(scif5_clk_b),
	4614	+ SH_PFC_PIN_GROUP(scif_clk_a),
	4615	+ SH_PFC_PIN_GROUP(scif_clk_b),
	4616	+ SH_PFC_PIN_GROUP(sdhi0_data1),
	4617	+ SH_PFC_PIN_GROUP(sdhi0_data4),
	4618	+ SH_PFC_PIN_GROUP(sdhi0_ctrl),
	4619	+ SH_PFC_PIN_GROUP(sdhi0_cd),
	4620	+ SH_PFC_PIN_GROUP(sdhi0_wp),
	4621	+ SH_PFC_PIN_GROUP(sdhi1_data1),
	4622	+ SH_PFC_PIN_GROUP(sdhi1_data4),
	4623	+ SH_PFC_PIN_GROUP(sdhi1_ctrl),
	4624	+ SH_PFC_PIN_GROUP(sdhi1_cd),
	4625	+ SH_PFC_PIN_GROUP(sdhi1_wp),
	4626	+ SH_PFC_PIN_GROUP(sdhi2_data1),
	4627	+ SH_PFC_PIN_GROUP(sdhi2_data4),
	4628	+ SH_PFC_PIN_GROUP(sdhi2_data8),
	4629	+ SH_PFC_PIN_GROUP(sdhi2_ctrl),
	4630	+ SH_PFC_PIN_GROUP(sdhi2_cd_a),
	4631	+ SH_PFC_PIN_GROUP(sdhi2_wp_a),
	4632	+ SH_PFC_PIN_GROUP(sdhi2_cd_b),
	4633	+ SH_PFC_PIN_GROUP(sdhi2_wp_b),
	4634	+ SH_PFC_PIN_GROUP(sdhi2_ds),
	4635	+ SH_PFC_PIN_GROUP(sdhi3_data1),
	4636	+ SH_PFC_PIN_GROUP(sdhi3_data4),
	4637	+ SH_PFC_PIN_GROUP(sdhi3_data8),
	4638	+ SH_PFC_PIN_GROUP(sdhi3_ctrl),
	4639	+ SH_PFC_PIN_GROUP(sdhi3_cd),
	4640	+ SH_PFC_PIN_GROUP(sdhi3_wp),
	4641	+ SH_PFC_PIN_GROUP(sdhi3_ds),
	4642	+ SH_PFC_PIN_GROUP(ssi0_data),
	4643	+ SH_PFC_PIN_GROUP(ssi01239_ctrl),
	4644	+ SH_PFC_PIN_GROUP(ssi1_data_a),
	4645	+ SH_PFC_PIN_GROUP(ssi1_data_b),
	4646	+ SH_PFC_PIN_GROUP(ssi1_ctrl_a),
	4647	+ SH_PFC_PIN_GROUP(ssi1_ctrl_b),
	4648	+ SH_PFC_PIN_GROUP(ssi2_data_a),
	4649	+ SH_PFC_PIN_GROUP(ssi2_data_b),
	4650	+ SH_PFC_PIN_GROUP(ssi2_ctrl_a),
	4651	+ SH_PFC_PIN_GROUP(ssi2_ctrl_b),
	4652	+ SH_PFC_PIN_GROUP(ssi3_data),
	4653	+ SH_PFC_PIN_GROUP(ssi349_ctrl),
	4654	+ SH_PFC_PIN_GROUP(ssi4_data),
	4655	+ SH_PFC_PIN_GROUP(ssi4_ctrl),
	4656	+ SH_PFC_PIN_GROUP(ssi5_data),
	4657	+ SH_PFC_PIN_GROUP(ssi5_ctrl),
	4658	+ SH_PFC_PIN_GROUP(ssi6_data),
	4659	+ SH_PFC_PIN_GROUP(ssi6_ctrl),
	4660	+ SH_PFC_PIN_GROUP(ssi7_data),
	4661	+ SH_PFC_PIN_GROUP(ssi78_ctrl),
	4662	+ SH_PFC_PIN_GROUP(ssi8_data),
	4663	+ SH_PFC_PIN_GROUP(ssi9_data_a),
	4664	+ SH_PFC_PIN_GROUP(ssi9_data_b),
	4665	+ SH_PFC_PIN_GROUP(ssi9_ctrl_a),
	4666	+ SH_PFC_PIN_GROUP(ssi9_ctrl_b),
	4667	+ SH_PFC_PIN_GROUP(tmu_tclk1_a),
	4668	+ SH_PFC_PIN_GROUP(tmu_tclk1_b),
	4669	+ SH_PFC_PIN_GROUP(tmu_tclk2_a),
	4670	+ SH_PFC_PIN_GROUP(tmu_tclk2_b),
	4671	+ SH_PFC_PIN_GROUP(tpu_to0),
	4672	+ SH_PFC_PIN_GROUP(tpu_to1),
	4673	+ SH_PFC_PIN_GROUP(tpu_to2),
	4674	+ SH_PFC_PIN_GROUP(tpu_to3),
	4675	+ SH_PFC_PIN_GROUP(usb0),
	4676	+ SH_PFC_PIN_GROUP(usb1),
	4677	+ SH_PFC_PIN_GROUP(usb30),
	4678	+ VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
	4679	+ VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
	4680	+ VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
	4681	+ VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
	4682	+ SH_PFC_PIN_GROUP(vin4_data18_a),
	4683	+ VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
	4684	+ VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
	4685	+ VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
	4686	+ VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
	4687	+ VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
	4688	+ VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
	4689	+ SH_PFC_PIN_GROUP(vin4_data18_b),
	4690	+ VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
	4691	+ VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
	4692	+ SH_PFC_PIN_GROUP(vin4_sync),
	4693	+ SH_PFC_PIN_GROUP(vin4_field),
	4694	+ SH_PFC_PIN_GROUP(vin4_clkenb),
	4695	+ SH_PFC_PIN_GROUP(vin4_clk),
	4696	+ VIN_DATA_PIN_GROUP(vin5_data, 8),
	4697	+ VIN_DATA_PIN_GROUP(vin5_data, 10),
	4698	+ VIN_DATA_PIN_GROUP(vin5_data, 12),
	4699	+ VIN_DATA_PIN_GROUP(vin5_data, 16),
	4700	+ SH_PFC_PIN_GROUP(vin5_sync),
	4701	+ SH_PFC_PIN_GROUP(vin5_field),
	4702	+ SH_PFC_PIN_GROUP(vin5_clkenb),
	4703	+ SH_PFC_PIN_GROUP(vin5_clk),
	4704	+ },
	4705	+ .automotive = {
	4706	+ SH_PFC_PIN_GROUP(drif0_ctrl_a),
	4707	+ SH_PFC_PIN_GROUP(drif0_data0_a),
	4708	+ SH_PFC_PIN_GROUP(drif0_data1_a),
	4709	+ SH_PFC_PIN_GROUP(drif0_ctrl_b),
	4710	+ SH_PFC_PIN_GROUP(drif0_data0_b),
	4711	+ SH_PFC_PIN_GROUP(drif0_data1_b),
	4712	+ SH_PFC_PIN_GROUP(drif0_ctrl_c),
	4713	+ SH_PFC_PIN_GROUP(drif0_data0_c),
	4714	+ SH_PFC_PIN_GROUP(drif0_data1_c),
	4715	+ SH_PFC_PIN_GROUP(drif1_ctrl_a),
	4716	+ SH_PFC_PIN_GROUP(drif1_data0_a),
	4717	+ SH_PFC_PIN_GROUP(drif1_data1_a),
	4718	+ SH_PFC_PIN_GROUP(drif1_ctrl_b),
	4719	+ SH_PFC_PIN_GROUP(drif1_data0_b),
	4720	+ SH_PFC_PIN_GROUP(drif1_data1_b),
	4721	+ SH_PFC_PIN_GROUP(drif1_ctrl_c),
	4722	+ SH_PFC_PIN_GROUP(drif1_data0_c),
	4723	+ SH_PFC_PIN_GROUP(drif1_data1_c),
	4724	+ SH_PFC_PIN_GROUP(drif2_ctrl_a),
	4725	+ SH_PFC_PIN_GROUP(drif2_data0_a),
	4726	+ SH_PFC_PIN_GROUP(drif2_data1_a),
	4727	+ SH_PFC_PIN_GROUP(drif2_ctrl_b),
	4728	+ SH_PFC_PIN_GROUP(drif2_data0_b),
	4729	+ SH_PFC_PIN_GROUP(drif2_data1_b),
	4730	+ SH_PFC_PIN_GROUP(drif3_ctrl_a),
	4731	+ SH_PFC_PIN_GROUP(drif3_data0_a),
	4732	+ SH_PFC_PIN_GROUP(drif3_data1_a),
	4733	+ SH_PFC_PIN_GROUP(drif3_ctrl_b),
	4734	+ SH_PFC_PIN_GROUP(drif3_data0_b),
	4735	+ SH_PFC_PIN_GROUP(drif3_data1_b),
	4736	+ }
4730	4737	};
4731	4738
4732	4739	static const char * const audio_clk_groups[] = {
@@ -5241,62 +5248,69 @@ static const char * const vin5_groups[] = { · 508 unmodified lines
5241	5248	"vin5_clk",
5242	5249	};
5243	5250
5244		−static const struct sh_pfc_function pinmux_functions[] = {
5245		− SH_PFC_FUNCTION(audio_clk),
5246		− SH_PFC_FUNCTION(avb),
5247		− SH_PFC_FUNCTION(can0),
5248		− SH_PFC_FUNCTION(can1),
5249		− SH_PFC_FUNCTION(can_clk),
5250		− SH_PFC_FUNCTION(canfd0),
5251		− SH_PFC_FUNCTION(canfd1),
5252		− SH_PFC_FUNCTION(drif0),
5253		− SH_PFC_FUNCTION(drif1),
5254		− SH_PFC_FUNCTION(drif2),
5255		− SH_PFC_FUNCTION(drif3),
5256		− SH_PFC_FUNCTION(du),
5257		− SH_PFC_FUNCTION(hscif0),
5258		− SH_PFC_FUNCTION(hscif1),
5259		− SH_PFC_FUNCTION(hscif2),
5260		− SH_PFC_FUNCTION(hscif3),
5261		− SH_PFC_FUNCTION(hscif4),
5262		− SH_PFC_FUNCTION(i2c0),
5263		− SH_PFC_FUNCTION(i2c1),
5264		− SH_PFC_FUNCTION(i2c2),
5265		− SH_PFC_FUNCTION(i2c3),
5266		− SH_PFC_FUNCTION(i2c5),
5267		− SH_PFC_FUNCTION(i2c6),
5268		− SH_PFC_FUNCTION(intc_ex),
5269		− SH_PFC_FUNCTION(msiof0),
5270		− SH_PFC_FUNCTION(msiof1),
5271		− SH_PFC_FUNCTION(msiof2),
5272		− SH_PFC_FUNCTION(msiof3),
5273		− SH_PFC_FUNCTION(pwm0),
5274		− SH_PFC_FUNCTION(pwm1),
5275		− SH_PFC_FUNCTION(pwm2),
5276		− SH_PFC_FUNCTION(pwm3),
5277		− SH_PFC_FUNCTION(pwm4),
5278		− SH_PFC_FUNCTION(pwm5),
5279		− SH_PFC_FUNCTION(pwm6),
5280		− SH_PFC_FUNCTION(sata0),
5281		− SH_PFC_FUNCTION(scif0),
5282		− SH_PFC_FUNCTION(scif1),
5283		− SH_PFC_FUNCTION(scif2),
5284		− SH_PFC_FUNCTION(scif3),
5285		− SH_PFC_FUNCTION(scif4),
5286		− SH_PFC_FUNCTION(scif5),
5287		− SH_PFC_FUNCTION(scif_clk),
5288		− SH_PFC_FUNCTION(sdhi0),
5289		− SH_PFC_FUNCTION(sdhi1),
5290		− SH_PFC_FUNCTION(sdhi2),
5291		− SH_PFC_FUNCTION(sdhi3),
5292		− SH_PFC_FUNCTION(ssi),
5293		− SH_PFC_FUNCTION(tmu),
5294		− SH_PFC_FUNCTION(tpu),
5295		− SH_PFC_FUNCTION(usb0),
5296		− SH_PFC_FUNCTION(usb1),
5297		− SH_PFC_FUNCTION(usb30),
5298		− SH_PFC_FUNCTION(vin4),
5299		− SH_PFC_FUNCTION(vin5),
	5251	+static const struct {
	5252	+ struct sh_pfc_function common[51];
	5253	+ struct sh_pfc_function automotive[4];
	5254	+} pinmux_functions = {
	5255	+ .common = {
	5256	+ SH_PFC_FUNCTION(audio_clk),
	5257	+ SH_PFC_FUNCTION(avb),
	5258	+ SH_PFC_FUNCTION(can0),
	5259	+ SH_PFC_FUNCTION(can1),
	5260	+ SH_PFC_FUNCTION(can_clk),
	5261	+ SH_PFC_FUNCTION(canfd0),
	5262	+ SH_PFC_FUNCTION(canfd1),
	5263	+ SH_PFC_FUNCTION(du),
	5264	+ SH_PFC_FUNCTION(hscif0),
	5265	+ SH_PFC_FUNCTION(hscif1),
	5266	+ SH_PFC_FUNCTION(hscif2),
	5267	+ SH_PFC_FUNCTION(hscif3),
	5268	+ SH_PFC_FUNCTION(hscif4),
	5269	+ SH_PFC_FUNCTION(i2c0),
	5270	+ SH_PFC_FUNCTION(i2c1),
	5271	+ SH_PFC_FUNCTION(i2c2),
	5272	+ SH_PFC_FUNCTION(i2c3),
	5273	+ SH_PFC_FUNCTION(i2c5),
	5274	+ SH_PFC_FUNCTION(i2c6),
	5275	+ SH_PFC_FUNCTION(intc_ex),
	5276	+ SH_PFC_FUNCTION(msiof0),
	5277	+ SH_PFC_FUNCTION(msiof1),
	5278	+ SH_PFC_FUNCTION(msiof2),
	5279	+ SH_PFC_FUNCTION(msiof3),
	5280	+ SH_PFC_FUNCTION(pwm0),
	5281	+ SH_PFC_FUNCTION(pwm1),
	5282	+ SH_PFC_FUNCTION(pwm2),
	5283	+ SH_PFC_FUNCTION(pwm3),
	5284	+ SH_PFC_FUNCTION(pwm4),
	5285	+ SH_PFC_FUNCTION(pwm5),
	5286	+ SH_PFC_FUNCTION(pwm6),
	5287	+ SH_PFC_FUNCTION(sata0),
	5288	+ SH_PFC_FUNCTION(scif0),
	5289	+ SH_PFC_FUNCTION(scif1),
	5290	+ SH_PFC_FUNCTION(scif2),
	5291	+ SH_PFC_FUNCTION(scif3),
	5292	+ SH_PFC_FUNCTION(scif4),
	5293	+ SH_PFC_FUNCTION(scif5),
	5294	+ SH_PFC_FUNCTION(scif_clk),
	5295	+ SH_PFC_FUNCTION(sdhi0),
	5296	+ SH_PFC_FUNCTION(sdhi1),
	5297	+ SH_PFC_FUNCTION(sdhi2),
	5298	+ SH_PFC_FUNCTION(sdhi3),
	5299	+ SH_PFC_FUNCTION(ssi),
	5300	+ SH_PFC_FUNCTION(tmu),
	5301	+ SH_PFC_FUNCTION(tpu),
	5302	+ SH_PFC_FUNCTION(usb0),
	5303	+ SH_PFC_FUNCTION(usb1),
	5304	+ SH_PFC_FUNCTION(usb30),
	5305	+ SH_PFC_FUNCTION(vin4),
	5306	+ SH_PFC_FUNCTION(vin5),
	5307	+ },
	5308	+ .automotive = {
	5309	+ SH_PFC_FUNCTION(drif0),
	5310	+ SH_PFC_FUNCTION(drif1),
	5311	+ SH_PFC_FUNCTION(drif2),
	5312	+ SH_PFC_FUNCTION(drif3),
	5313	+ }
5300	5314	};
5301	5315
5302	5316	static const struct pinmux_cfg_reg pinmux_config_regs[] = {
@@ -6425,6 +6439,32 @@ static const struct sh_pfc_soc_operations r8a77965_pinmux_ops = { · 1122 unmodified lines
6425	6439	.set_bias = r8a77965_pinmux_set_bias,
6426	6440	};
6427	6441
	6442	+#ifdef CONFIG_PINCTRL_PFC_R8A774B1
	6443	+const struct sh_pfc_soc_info r8a774b1_pinmux_info = {
	6444	+ .name = "r8a774b1_pfc",
	6445	+ .ops = &r8a77965_pinmux_ops,
	6446	+ .unlock_reg = 0xe6060000, /* PMMR */
	6447	+
	6448	+ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
	6449	+
	6450	+ .pins = pinmux_pins,
	6451	+ .nr_pins = ARRAY_SIZE(pinmux_pins),
	6452	+ .groups = pinmux_groups.common,
	6453	+ .nr_groups = ARRAY_SIZE(pinmux_groups.common),
	6454	+ .functions = pinmux_functions.common,
	6455	+ .nr_functions = ARRAY_SIZE(pinmux_functions.common),
	6456	+
	6457	+ .cfg_regs = pinmux_config_regs,
	6458	+ .drive_regs = pinmux_drive_regs,
	6459	+ .bias_regs = pinmux_bias_regs,
	6460	+ .ioctrl_regs = pinmux_ioctrl_regs,
	6461	+
	6462	+ .pinmux_data = pinmux_data,
	6463	+ .pinmux_data_size = ARRAY_SIZE(pinmux_data),
	6464	+};
	6465	+#endif
	6466	+
	6467	+#ifdef CONFIG_PINCTRL_PFC_R8A77965
6428	6468	const struct sh_pfc_soc_info r8a77965_pinmux_info = {
6429	6469	.name = "r8a77965_pfc",
6430	6470	.ops = &r8a77965_pinmux_ops,
@@ -6434,10 +6474,12 @@ const struct sh_pfc_soc_info r8a77965_pinmux_info = { · 3 unmodified lines
6434	6474
6435	6475	.pins = pinmux_pins,
6436	6476	.nr_pins = ARRAY_SIZE(pinmux_pins),
6437		− .groups = pinmux_groups,
6438		− .nr_groups = ARRAY_SIZE(pinmux_groups),
6439		− .functions = pinmux_functions,
6440		− .nr_functions = ARRAY_SIZE(pinmux_functions),
	6477	+ .groups = pinmux_groups.common,
	6478	+ .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
	6479	+ ARRAY_SIZE(pinmux_groups.automotive),
	6480	+ .functions = pinmux_functions.common,
	6481	+ .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
	6482	+ ARRAY_SIZE(pinmux_functions.automotive),
6441	6483
6442	6484	.cfg_regs = pinmux_config_regs,
6443	6485	.drive_regs = pinmux_drive_regs,
@@ -6447,3 +6489,4 @@ const struct sh_pfc_soc_info r8a77965_pinmux_info = { · 3 unmodified lines
6447	6489	.pinmux_data = pinmux_data,
6448	6490	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
6449	6491	};
	6492	+#endif

drivers/pinctrl/sh-pfc/pfc-r8a77990.c+30−27

@@ -232,8 +232,8 @@ · 231 unmodified lines
232	232	#define IP2_11_8 FM(AVB_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233	233	#define IP2_15_12 FM(BS_N) FM(PWM0_A) FM(AVB_MAGIC) FM(VI4_CLK) F_(0, 0) FM(TX3_C) F_(0, 0) FM(VI5_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234	234	#define IP2_19_16 FM(RD_N) FM(PWM1_A) FM(AVB_LINK) FM(VI4_FIELD) F_(0, 0) FM(RX3_C) FM(FSCLKST2_N_A) FM(VI5_DATA0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235		−#define IP2_23_20 FM(RD_WR_N) FM(SCL7_A) FM(AVB_AVTP_MATCH_A) FM(VI4_VSYNC_N) FM(TX5_B) FM(SCK3_C) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236		−#define IP2_27_24 FM(EX_WAIT0) FM(SDA7_A) FM(AVB_AVTP_CAPTURE_A) FM(VI4_HSYNC_N) FM(RX5_B) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	235	+#define IP2_23_20 FM(RD_WR_N) FM(SCL7_A) FM(AVB_AVTP_MATCH) FM(VI4_VSYNC_N) FM(TX5_B) FM(SCK3_C) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
	236	+#define IP2_27_24 FM(EX_WAIT0) FM(SDA7_A) FM(AVB_AVTP_CAPTURE) FM(VI4_HSYNC_N) FM(RX5_B) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237	237	#define IP2_31_28 FM(A0) FM(IRQ0) FM(PWM2_A) FM(MSIOF3_SS1_B) FM(VI5_CLK_A) FM(DU_CDE) FM(HRX3_D) FM(IERX) FM(QSTB_QHE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238	238	#define IP3_3_0 FM(A1) FM(IRQ1) FM(PWM3_A) FM(DU_DOTCLKIN1) FM(VI5_DATA0_A) FM(DU_DISP_CDE) FM(SDA6_B) FM(IETX) FM(QCPV_QDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239	239	#define IP3_7_4 FM(A2) FM(IRQ2) FM(AVB_AVTP_PPS) FM(VI4_CLKENB) FM(VI5_DATA1_A) FM(DU_DISP) FM(SCL6_B) F_(0, 0) FM(QSTVB_QVE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -448,6 +448,8 @@ FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM · 208 unmodified lines
448	448	#define MOD_SEL0_1_0 REV4(FM(SEL_SPEED_PULSE_IF_0), FM(SEL_SPEED_PULSE_IF_1), FM(SEL_SPEED_PULSE_IF_2), F_(0, 0))
449	449
450	450	/* MOD_SEL1 / / 0 / / 1 / / 2 / / 3 / / 4 / / 5 / / 6 / / 7 */
	451	+#define MOD_SEL1_31 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1)
	452	+#define MOD_SEL1_30 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
451	453	#define MOD_SEL1_29 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
452	454	#define MOD_SEL1_28 FM(SEL_USB_20_CH0_0) FM(SEL_USB_20_CH0_1)
453	455	#define MOD_SEL1_26 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
@@ -468,7 +470,8 @@ FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM · 14 unmodified lines
468	470
469	471	#define PINMUX_MOD_SELS \
470	472	\
471		−MOD_SEL0_30_29 \
	473	+ MOD_SEL1_31 \
	474	+MOD_SEL0_30_29 MOD_SEL1_30 \
472	475	MOD_SEL1_29 \
473	476	MOD_SEL0_28 MOD_SEL1_28 \
474	477	MOD_SEL0_27_26 \
@@ -634,7 +637,7 @@ static const u16 pinmux_data[] = { · 159 unmodified lines
634	637
635	638	PINMUX_IPSR_GPSR(IP2_23_20, RD_WR_N),
636	639	PINMUX_IPSR_MSEL(IP2_23_20, SCL7_A, SEL_I2C7_0),
637		− PINMUX_IPSR_GPSR(IP2_23_20, AVB_AVTP_MATCH_A),
	640	+ PINMUX_IPSR_GPSR(IP2_23_20, AVB_AVTP_MATCH),
638	641	PINMUX_IPSR_GPSR(IP2_23_20, VI4_VSYNC_N),
639	642	PINMUX_IPSR_GPSR(IP2_23_20, TX5_B),
640	643	PINMUX_IPSR_MSEL(IP2_23_20, SCK3_C, SEL_SCIF3_2),
@@ -642,7 +645,7 @@ static const u16 pinmux_data[] = { · 1 unmodified line
642	645
643	646	PINMUX_IPSR_GPSR(IP2_27_24, EX_WAIT0),
644	647	PINMUX_IPSR_MSEL(IP2_27_24, SDA7_A, SEL_I2C7_0),
645		− PINMUX_IPSR_GPSR(IP2_27_24, AVB_AVTP_CAPTURE_A),
	648	+ PINMUX_IPSR_GPSR(IP2_27_24, AVB_AVTP_CAPTURE),
646	649	PINMUX_IPSR_GPSR(IP2_27_24, VI4_HSYNC_N),
647	650	PINMUX_IPSR_MSEL(IP2_27_24, RX5_B, SEL_SCIF5_1),
648	651	PINMUX_IPSR_MSEL(IP2_27_24, PWM6_A, SEL_PWM6_0),
@@ -1058,7 +1061,7 @@ static const u16 pinmux_data[] = { · 409 unmodified lines
1058	1061	PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1059	1062	PINMUX_IPSR_MSEL(IP10_27_24, SCL2_B, SEL_I2C2_1),
1060	1063	PINMUX_IPSR_MSEL(IP10_27_24, TCLK1_A, SEL_TIMER_TMU_0),
1061		− PINMUX_IPSR_GPSR(IP10_27_24, SSI_SCK2_B),
	1064	+ PINMUX_IPSR_MSEL(IP10_27_24, SSI_SCK2_B, SEL_SSI2_1),
1062	1065	PINMUX_IPSR_GPSR(IP10_27_24, TS_SCK0),
1063	1066
1064	1067	PINMUX_IPSR_GPSR(IP10_31_28, SD0_WP),
@@ -1067,7 +1070,7 @@ static const u16 pinmux_data[] = { · 2 unmodified lines
1067	1070	PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1),
1068	1071	PINMUX_IPSR_MSEL(IP10_31_28, SDA2_B, SEL_I2C2_1),
1069	1072	PINMUX_IPSR_MSEL(IP10_31_28, TCLK2_A, SEL_TIMER_TMU_0),
1070		− PINMUX_IPSR_GPSR(IP10_31_28, SSI_WS2_B),
	1073	+ PINMUX_IPSR_MSEL(IP10_31_28, SSI_WS2_B, SEL_SSI2_1),
1071	1074	PINMUX_IPSR_GPSR(IP10_31_28, TS_SDAT0),
1072	1075
1073	1076	/* IPSR11 */
@@ -1085,13 +1088,13 @@ static const u16 pinmux_data[] = { · 11 unmodified lines
1085	1088
1086	1089	PINMUX_IPSR_MSEL(IP11_11_8, RX0_A, SEL_SCIF0_0),
1087	1090	PINMUX_IPSR_MSEL(IP11_11_8, HRX1_A, SEL_HSCIF1_0),
1088		− PINMUX_IPSR_GPSR(IP11_11_8, SSI_SCK2_A),
	1091	+ PINMUX_IPSR_MSEL(IP11_11_8, SSI_SCK2_A, SEL_SSI2_0),
1089	1092	PINMUX_IPSR_GPSR(IP11_11_8, RIF1_SYNC),
1090	1093	PINMUX_IPSR_GPSR(IP11_11_8, TS_SCK1),
1091	1094
1092	1095	PINMUX_IPSR_MSEL(IP11_15_12, TX0_A, SEL_SCIF0_0),
1093	1096	PINMUX_IPSR_GPSR(IP11_15_12, HTX1_A),
1094		− PINMUX_IPSR_GPSR(IP11_15_12, SSI_WS2_A),
	1097	+ PINMUX_IPSR_MSEL(IP11_15_12, SSI_WS2_A, SEL_SSI2_0),
1095	1098	PINMUX_IPSR_GPSR(IP11_15_12, RIF1_D0),
1096	1099	PINMUX_IPSR_GPSR(IP11_15_12, TS_SDAT1),
1097	1100
@@ -1196,7 +1199,7 @@ static const u16 pinmux_data[] = { · 98 unmodified lines
1196	1199	PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_A, SEL_DRIF0_0),
1197	1200	PINMUX_IPSR_MSEL(IP13_19_16, SDA1_B, SEL_I2C1_1),
1198	1201	PINMUX_IPSR_MSEL(IP13_19_16, TCLK2_B, SEL_TIMER_TMU_1),
1199		− PINMUX_IPSR_GPSR(IP13_19_16, SIM0_D_A),
	1202	+ PINMUX_IPSR_MSEL(IP13_19_16, SIM0_D_A, SEL_SIMCARD_0),
1200	1203
1201	1204	PINMUX_IPSR_GPSR(IP13_23_20, MLB_DAT),
1202	1205	PINMUX_IPSR_MSEL(IP13_23_20, TX0_B, SEL_SCIF0_1),
@@ -1264,7 +1267,7 @@ static const u16 pinmux_data[] = { · 61 unmodified lines
1264	1267	PINMUX_IPSR_GPSR(IP15_15_12, TPU0TO2),
1265	1268	PINMUX_IPSR_MSEL(IP15_15_12, SDA1_D, SEL_I2C1_3),
1266	1269	PINMUX_IPSR_MSEL(IP15_15_12, FSO_CFE_1_N_B, SEL_FSO_1),
1267		− PINMUX_IPSR_GPSR(IP15_15_12, SIM0_D_B),
	1270	+ PINMUX_IPSR_MSEL(IP15_15_12, SIM0_D_B, SEL_SIMCARD_1),
1268	1271
1269	1272	PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA6),
1270	1273	PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
@@ -1524,22 +1527,22 @@ static const unsigned int avb_avtp_pps_mux[] = { · 253 unmodified lines
1524	1527	AVB_AVTP_PPS_MARK,
1525	1528	};
1526	1529
1527		−static const unsigned int avb_avtp_match_a_pins[] = {
1528		− /* AVB_AVTP_MATCH_A */
	1530	+static const unsigned int avb_avtp_match_pins[] = {
	1531	+ /* AVB_AVTP_MATCH */
1529	1532	RCAR_GP_PIN(2, 24),
1530	1533	};
1531	1534
1532		−static const unsigned int avb_avtp_match_a_mux[] = {
1533		− AVB_AVTP_MATCH_A_MARK,
	1535	+static const unsigned int avb_avtp_match_mux[] = {
	1536	+ AVB_AVTP_MATCH_MARK,
1534	1537	};
1535	1538
1536		−static const unsigned int avb_avtp_capture_a_pins[] = {
1537		− /* AVB_AVTP_CAPTURE_A */
	1539	+static const unsigned int avb_avtp_capture_pins[] = {
	1540	+ /* AVB_AVTP_CAPTURE */
1538	1541	RCAR_GP_PIN(2, 25),
1539	1542	};
1540	1543
1541		−static const unsigned int avb_avtp_capture_a_mux[] = {
1542		− AVB_AVTP_CAPTURE_A_MARK,
	1544	+static const unsigned int avb_avtp_capture_mux[] = {
	1545	+ AVB_AVTP_CAPTURE_MARK,
1543	1546	};
1544	1547
1545	1548	/* - CAN ------------------------------------------------------------------ */
@@ -3784,8 +3787,8 @@ static const struct { · 2238 unmodified lines
3784	3787	SH_PFC_PIN_GROUP(avb_phy_int),
3785	3788	SH_PFC_PIN_GROUP(avb_mii),
3786	3789	SH_PFC_PIN_GROUP(avb_avtp_pps),
3787		− SH_PFC_PIN_GROUP(avb_avtp_match_a),
3788		− SH_PFC_PIN_GROUP(avb_avtp_capture_a),
	3790	+ SH_PFC_PIN_GROUP(avb_avtp_match),
	3791	+ SH_PFC_PIN_GROUP(avb_avtp_capture),
3789	3792	SH_PFC_PIN_GROUP(can0_data),
3790	3793	SH_PFC_PIN_GROUP(can1_data),
3791	3794	SH_PFC_PIN_GROUP(can_clk),
@@ -4061,8 +4064,8 @@ static const char * const avb_groups[] = { · 269 unmodified lines
4061	4064	"avb_phy_int",
4062	4065	"avb_mii",
4063	4066	"avb_avtp_pps",
4064		− "avb_avtp_match_a",
4065		− "avb_avtp_capture_a",
	4067	+ "avb_avtp_match",
	4068	+ "avb_avtp_capture",
4066	4069	};
4067	4070
4068	4071	static const char * const can0_groups[] = {
@@ -4957,11 +4960,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { · 888 unmodified lines
4957	4960	MOD_SEL0_1_0 ))
4958	4961	},
4959	4962	{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
4960		− GROUP(2, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1, 1,
4961		− 2, 2, 2, 1, 1, 2, 1, 4),
	4963	+ GROUP(1, 1, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1,
	4964	+ 1, 2, 2, 2, 1, 1, 2, 1, 4),
4962	4965	GROUP(
4963		− /* RESERVED 31, 30 */
4964		− 0, 0, 0, 0,
	4966	+ MOD_SEL1_31
	4967	+ MOD_SEL1_30
4965	4968	MOD_SEL1_29
4966	4969	MOD_SEL1_28
4967	4970	/* RESERVED 27 */

drivers/pinctrl/sh-pfc/pfc-sh7734.c+2−2

@@ -1450,7 +1450,7 @@ static const struct pinmux_func pinmux_func_gpios[] = { · 1449 unmodified lines
1450	1450	GPIO_FN(ET0_ETXD2_A),
1451	1451	GPIO_FN(EX_CS5), GPIO_FN(SD1_CMD_A), GPIO_FN(ATADIR), GPIO_FN(QSSL_B),
1452	1452	GPIO_FN(ET0_ETXD3_A),
1453		− GPIO_FN(RD_WR), GPIO_FN(TCLK1_B),
	1453	+ GPIO_FN(RD_WR), GPIO_FN(TCLK0), GPIO_FN(CAN_CLK_B), GPIO_FN(ET0_ETXD4),
1454	1454	GPIO_FN(EX_WAIT0), GPIO_FN(TCLK1_B),
1455	1455	GPIO_FN(EX_WAIT1), GPIO_FN(SD1_DAT0_A), GPIO_FN(DREQ2),
1456	1456	GPIO_FN(CAN1_TX_C), GPIO_FN(ET0_LINK_C), GPIO_FN(ET0_ETXD5_A),
@@ -1949,7 +1949,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { · 492 unmodified lines
1949	1949	/* IP3_20 [1] */
1950	1950	FN_EX_WAIT0, FN_TCLK1_B,
1951	1951	/* IP3_19_18 [2] */
1952		− FN_RD_WR, FN_TCLK1_B, 0, 0,
	1952	+ FN_RD_WR, FN_TCLK0, FN_CAN_CLK_B, FN_ET0_ETXD4,
1953	1953	/* IP3_17_15 [3] */
1954	1954	FN_EX_CS5, FN_SD1_CMD_A, FN_ATADIR, FN_QSSL_B,
1955	1955	FN_ET0_ETXD3_A, 0, 0, 0,

drivers/pinctrl/sh-pfc/sh_pfc.h+5−3

@@ -309,6 +309,7 @@ extern const struct sh_pfc_soc_info r8a7744_pinmux_info; · 308 unmodified lines
309	309	extern const struct sh_pfc_soc_info r8a7745_pinmux_info;
310	310	extern const struct sh_pfc_soc_info r8a77470_pinmux_info;
311	311	extern const struct sh_pfc_soc_info r8a774a1_pinmux_info;
	312	+extern const struct sh_pfc_soc_info r8a774b1_pinmux_info;
312	313	extern const struct sh_pfc_soc_info r8a774c0_pinmux_info;
313	314	extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
314	315	extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
@@ -319,7 +320,8 @@ extern const struct sh_pfc_soc_info r8a7793_pinmux_info; · 4 unmodified lines
319	320	extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
320	321	extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
321	322	extern const struct sh_pfc_soc_info r8a7795es1_pinmux_info;
322		−extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
	323	+extern const struct sh_pfc_soc_info r8a77960_pinmux_info;
	324	+extern const struct sh_pfc_soc_info r8a77961_pinmux_info;
323	325	extern const struct sh_pfc_soc_info r8a77965_pinmux_info;
324	326	extern const struct sh_pfc_soc_info r8a77970_pinmux_info;
325	327	extern const struct sh_pfc_soc_info r8a77980_pinmux_info;
@@ -422,12 +424,12 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info; · 96 unmodified lines
422	424	/*
423	425	* Describe a pinmux configuration in which a pin is physically multiplexed
424	426	* with other pins.
425		− * - ipsr: IPSR field (unused, for documentation purposes only)
	427	+ * - ipsr: IPSR field
426	428	* - fn: Function name
427	429	* - psel: Physical multiplexing selector
428	430	*/
429	431	#define PINMUX_IPSR_PHYS(ipsr, fn, psel) \
430		− PINMUX_DATA(fn##_MARK, FN_##psel)
	432	+ PINMUX_DATA(fn##_MARK, FN_##psel, FN_##ipsr)
431	433
432	434	/*
433	435	* Describe a pinmux configuration for a single-function pin with GPIO

drivers/pinctrl/sirf/pinctrl-atlas7.c+21−20

@@ -5996,6 +5996,7 @@ static int atlas7_gpio_probe(struct platform_device *pdev) · 5995 unmodified lines
5996	5996	struct gpio_chip *chip;
5997	5997	u32 nbank;
5998	5998	int ret, idx;
	5999	+ struct gpio_irq_chip *girq;
5999	6000
6000	6001	ret = of_property_read_u32(np, "gpio-banks", &nbank);
6001	6002	if (ret) {
@@ -6048,24 +6049,15 @@ static int atlas7_gpio_probe(struct platform_device *pdev) · 46 unmodified lines
6048	6049	chip->of_gpio_n_cells = 2;
6049	6050	chip->parent = &pdev->dev;
6050	6051
6051		− /* Add gpio chip to system */
6052		− ret = gpiochip_add_data(chip, a7gc);
6053		− if (ret) {
6054		− dev_err(&pdev->dev,
6055		− "%pOF: error in probe function with status %d\n",
6056		− np, ret);
6057		− goto failed;
6058		− }
6059		−
6060		− /* Add gpio chip to irq subsystem */
6061		− ret = gpiochip_irqchip_add(chip, &atlas7_gpio_irq_chip,
6062		− 0, handle_level_irq, IRQ_TYPE_NONE);
6063		− if (ret) {
6064		− dev_err(&pdev->dev,
6065		− "could not connect irqchip to gpiochip\n");
6066		− goto failed;
6067		− }
6068		−
	6052	+ girq = &chip->irq;
	6053	+ girq->chip = &atlas7_gpio_irq_chip;
	6054	+ girq->parent_handler = atlas7_gpio_handle_irq;
	6055	+ girq->num_parents = nbank;
	6056	+ girq->parents = devm_kcalloc(&pdev->dev, nbank,
	6057	+ sizeof(*girq->parents),
	6058	+ GFP_KERNEL);
	6059	+ if (!girq->parents)
	6060	+ return -ENOMEM;
6069	6061	for (idx = 0; idx < nbank; idx++) {
6070	6062	struct atlas7_gpio_bank *bank;
6071	6063
@@ -6084,9 +6076,18 @@ static int atlas7_gpio_probe(struct platform_device *pdev) · 12 unmodified lines
6084	6076	goto failed;
6085	6077	}
6086	6078	bank->irq = ret;
	6079	+ girq->parents[idx] = ret;
	6080	+ }
	6081	+ girq->default_type = IRQ_TYPE_NONE;
	6082	+ girq->handler = handle_level_irq;
6087	6083
6088		− gpiochip_set_chained_irqchip(chip, &atlas7_gpio_irq_chip,
6089		− bank->irq, atlas7_gpio_handle_irq);
	6084	+ /* Add gpio chip to system */
	6085	+ ret = gpiochip_add_data(chip, a7gc);
	6086	+ if (ret) {
	6087	+ dev_err(&pdev->dev,
	6088	+ "%pOF: error in probe function with status %d\n",
	6089	+ np, ret);
	6090	+ goto failed;
6090	6091	}
6091	6092
6092	6093	platform_set_drvdata(pdev, a7gc);

drivers/pinctrl/sirf/pinctrl-sirf.c+20−23

@@ -785,6 +785,7 @@ static int sirfsoc_gpio_probe(struct device_node *np) · 784 unmodified lines
785	785	struct sirfsoc_gpio_bank *bank;
786	786	void __iomem *regs;
787	787	struct platform_device *pdev;
	788	+ struct gpio_irq_chip *girq;
788	789
789	790	u32 pullups[SIRFSOC_GPIO_NO_OF_BANKS], pulldowns[SIRFSOC_GPIO_NO_OF_BANKS];
790	791
@@ -816,36 +817,33 @@ static int sirfsoc_gpio_probe(struct device_node *np) · 25 unmodified lines
816	817	sgpio->chip.gc.parent = &pdev->dev;
817	818	sgpio->chip.regs = regs;
818	819
819		− err = gpiochip_add_data(&sgpio->chip.gc, sgpio);
820		− if (err) {
821		− dev_err(&pdev->dev, "%pOF: error in probe function with status %d\n",
822		− np, err);
823		− goto out;
824		− }
825		−
826		− err = gpiochip_irqchip_add(&sgpio->chip.gc,
827		− &sirfsoc_irq_chip,
828		− 0, handle_level_irq,
829		− IRQ_TYPE_NONE);
830		− if (err) {
831		− dev_err(&pdev->dev,
832		− "could not connect irqchip to gpiochip\n");
833		− goto out_banks;
834		− }
835		−
	820	+ girq = &sgpio->chip.gc.irq;
	821	+ girq->chip = &sirfsoc_irq_chip;
	822	+ girq->parent_handler = sirfsoc_gpio_handle_irq;
	823	+ girq->num_parents = SIRFSOC_GPIO_NO_OF_BANKS;
	824	+ girq->parents = devm_kcalloc(&pdev->dev, SIRFSOC_GPIO_NO_OF_BANKS,
	825	+ sizeof(*girq->parents),
	826	+ GFP_KERNEL);
	827	+ if (!girq->parents)
	828	+ return -ENOMEM;
836	829	for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
837	830	bank = &sgpio->sgpio_bank[i];
838	831	spin_lock_init(&bank->lock);
839	832	bank->parent_irq = platform_get_irq(pdev, i);
840	833	if (bank->parent_irq < 0) {
841	834	err = bank->parent_irq;
842		− goto out_banks;
	835	+ goto out;
843	836	}
	837	+ girq->parents[i] = bank->parent_irq;
	838	+ }
	839	+ girq->default_type = IRQ_TYPE_NONE;
	840	+ girq->handler = handle_level_irq;
844	841
845		− gpiochip_set_chained_irqchip(&sgpio->chip.gc,
846		− &sirfsoc_irq_chip,
847		− bank->parent_irq,
848		− sirfsoc_gpio_handle_irq);
	842	+ err = gpiochip_add_data(&sgpio->chip.gc, sgpio);
	843	+ if (err) {
	844	+ dev_err(&pdev->dev, "%pOF: error in probe function with status %d\n",
	845	+ np, err);
	846	+ goto out;
849	847	}
850	848
851	849	err = gpiochip_add_pin_range(&sgpio->chip.gc, dev_name(&pdev->dev),
@@ -867,7 +865,6 @@ static int sirfsoc_gpio_probe(struct device_node *np) · 15 unmodified lines
867	865	return 0;
868	866
869	867	out_no_range:
870		−out_banks:
871	868	gpiochip_remove(&sgpio->chip.gc);
872	869	out:
873	870	iounmap(regs);

drivers/pinctrl/spear/pinctrl-plgpio.c+22−29

@@ -515,15 +515,13 @@ end: · 514 unmodified lines
515	515	static int plgpio_probe(struct platform_device *pdev)
516	516	{
517	517	struct plgpio *plgpio;
518		− struct resource *res;
519	518	int ret, irq;
520	519
521	520	plgpio = devm_kzalloc(&pdev->dev, sizeof(*plgpio), GFP_KERNEL);
522	521	if (!plgpio)
523	522	return -ENOMEM;
524	523
525		− res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
526		− plgpio->base = devm_ioremap_resource(&pdev->dev, res);
	524	+ plgpio->base = devm_platform_ioremap_resource(pdev, 0);
527	525	if (IS_ERR(plgpio->base))
528	526	return PTR_ERR(plgpio->base);
529	527
@@ -569,40 +567,35 @@ static int plgpio_probe(struct platform_device *pdev) · 39 unmodified lines
569	567	}
570	568	}
571	569
572		− ret = gpiochip_add_data(&plgpio->chip, plgpio);
573		− if (ret) {
574		− dev_err(&pdev->dev, "unable to add gpio chip\n");
575		− goto unprepare_clk;
576		− }
577		−
578	570	irq = platform_get_irq(pdev, 0);
579		− if (irq < 0) {
580		− dev_info(&pdev->dev, "PLGPIO registered without IRQs\n");
581		− return 0;
	571	+ if (irq > 0) {
	572	+ struct gpio_irq_chip *girq;
	573	+
	574	+ girq = &plgpio->chip.irq;
	575	+ girq->chip = &plgpio_irqchip;
	576	+ girq->parent_handler = plgpio_irq_handler;
	577	+ girq->num_parents = 1;
	578	+ girq->parents = devm_kcalloc(&pdev->dev, 1,
	579	+ sizeof(*girq->parents),
	580	+ GFP_KERNEL);
	581	+ if (!girq->parents)
	582	+ return -ENOMEM;
	583	+ girq->parents[0] = irq;
	584	+ girq->default_type = IRQ_TYPE_NONE;
	585	+ girq->handler = handle_simple_irq;
	586	+ dev_info(&pdev->dev, "PLGPIO registering with IRQs\n");
	587	+ } else {
	588	+ dev_info(&pdev->dev, "PLGPIO registering without IRQs\n");
582	589	}
583	590
584		− ret = gpiochip_irqchip_add(&plgpio->chip,
585		− &plgpio_irqchip,
586		− 0,
587		− handle_simple_irq,
588		− IRQ_TYPE_NONE);
	591	+ ret = gpiochip_add_data(&plgpio->chip, plgpio);
589	592	if (ret) {
590		− dev_err(&pdev->dev, "failed to add irqchip to gpiochip\n");
591		− goto remove_gpiochip;
	593	+ dev_err(&pdev->dev, "unable to add gpio chip\n");
	594	+ goto unprepare_clk;
592	595	}
593	596
594		− gpiochip_set_chained_irqchip(&plgpio->chip,
595		− &plgpio_irqchip,
596		− irq,
597		− plgpio_irq_handler);
598		−
599		− dev_info(&pdev->dev, "PLGPIO registered with IRQs\n");
600		−
601	597	return 0;
602	598
603		−remove_gpiochip:
604		− dev_info(&pdev->dev, "Remove gpiochip\n");
605		− gpiochip_remove(&plgpio->chip);
606	599	unprepare_clk:
607	600	if (!IS_ERR(plgpio->clk))
608	601	clk_unprepare(plgpio->clk);

drivers/pinctrl/spear/pinctrl-spear.c+1−3

@@ -358,7 +358,6 @@ int spear_pinctrl_probe(struct platform_device *pdev, · 357 unmodified lines
358	358	struct spear_pinctrl_machdata *machdata)
359	359	{
360	360	struct device_node *np = pdev->dev.of_node;
361		− struct resource *res;
362	361	struct spear_pmx *pmx;
363	362
364	363	if (!machdata)
@@ -368,8 +367,7 @@ int spear_pinctrl_probe(struct platform_device *pdev, · 3 unmodified lines
368	367	if (!pmx)
369	368	return -ENOMEM;
370	369
371		− res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
372		− pmx->vbase = devm_ioremap_resource(&pdev->dev, res);
	370	+ pmx->vbase = devm_platform_ioremap_resource(pdev, 0);
373	371	if (IS_ERR(pmx->vbase))
374	372	return PTR_ERR(pmx->vbase);
375	373

drivers/pinctrl/sprd/pinctrl-sprd.c+22−1

@@ -41,7 +41,8 @@ · 40 unmodified lines
41	41	#define PUBCP_SLEEP_MODE BIT(14)
42	42	#define TGLDSP_SLEEP_MODE BIT(15)
43	43	#define AGDSP_SLEEP_MODE BIT(16)
44		−#define SLEEP_MODE_MASK GENMASK(3, 0)
	44	+#define CM4_SLEEP_MODE BIT(17)
	45	+#define SLEEP_MODE_MASK GENMASK(5, 0)
45	46	#define SLEEP_MODE_SHIFT 13
46	47
47	48	#define SLEEP_INPUT BIT(1)
@@ -81,6 +82,7 @@ enum pin_sleep_mode { · 33 unmodified lines
81	82	PUBCP_SLEEP = BIT(1),
82	83	TGLDSP_SLEEP = BIT(2),
83	84	AGDSP_SLEEP = BIT(3),
	85	+ CM4_SLEEP = BIT(4),
84	86	};
85	87
86	88	enum pin_func_sel {
@@ -484,6 +486,13 @@ static int sprd_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin_id, · 397 unmodified lines
484	486	SLEEP_PULL_UP_MASK) << 16;
485	487	arg \|= (reg >> PULL_UP_SHIFT) & PULL_UP_MASK;
486	488	break;
	489	+ case PIN_CONFIG_BIAS_DISABLE:
	490	+ if ((reg & (SLEEP_PULL_DOWN \| SLEEP_PULL_UP)) \|\|
	491	+ (reg & (PULL_DOWN \| PULL_UP_4_7K \| PULL_UP_20K)))
	492	+ return -EINVAL;
	493	+
	494	+ arg = 1;
	495	+ break;
487	496	case PIN_CONFIG_SLEEP_HARDWARE_STATE:
488	497	arg = 0;
489	498	break;
@@ -609,6 +618,8 @@ static int sprd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin_id, · 119 unmodified lines
609	618	val \|= TGLDSP_SLEEP_MODE;
610	619	if (arg & AGDSP_SLEEP)
611	620	val \|= AGDSP_SLEEP_MODE;
	621	+ if (arg & CM4_SLEEP)
	622	+ val \|= CM4_SLEEP_MODE;
612	623
613	624	mask = SLEEP_MODE_MASK;
614	625	shift = SLEEP_MODE_SHIFT;
@@ -674,6 +685,16 @@ static int sprd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin_id, · 59 unmodified lines
674	685	shift = PULL_UP_SHIFT;
675	686	}
676	687	break;
	688	+ case PIN_CONFIG_BIAS_DISABLE:
	689	+ if (is_sleep_config == true) {
	690	+ val = shift = 0;
	691	+ mask = SLEEP_PULL_DOWN \| SLEEP_PULL_UP;
	692	+ } else {
	693	+ val = shift = 0;
	694	+ mask = PULL_DOWN \| PULL_UP_20K \|
	695	+ PULL_UP_4_7K;
	696	+ }
	697	+ break;
677	698	case PIN_CONFIG_SLEEP_HARDWARE_STATE:
678	699	continue;
679	700	default:

drivers/pinctrl/sunxi/pinctrl-sunxi.c+1−3

@@ -1385,7 +1385,6 @@ int sunxi_pinctrl_init_with_variant(struct platform_device *pdev, · 1384 unmodified lines
1385	1385	struct pinctrl_pin_desc *pins;
1386	1386	struct sunxi_pinctrl *pctl;
1387	1387	struct pinmux_ops *pmxops;
1388		− struct resource *res;
1389	1388	int i, ret, last_pin, pin_idx;
1390	1389	struct clk *clk;
1391	1390
@@ -1396,8 +1395,7 @@ int sunxi_pinctrl_init_with_variant(struct platform_device *pdev, · 4 unmodified lines
1396	1395
1397	1396	raw_spin_lock_init(&pctl->lock);
1398	1397
1399		− res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1400		− pctl->membase = devm_ioremap_resource(&pdev->dev, res);
	1398	+ pctl->membase = devm_platform_ioremap_resource(pdev, 0);
1401	1399	if (IS_ERR(pctl->membase))
1402	1400	return PTR_ERR(pctl->membase);
1403	1401

drivers/pinctrl/tegra/pinctrl-tegra-xusb.c+7−3

@@ -873,7 +873,6 @@ int tegra_xusb_padctl_legacy_probe(struct platform_device *pdev) · 872 unmodified lines
873	873	{
874	874	struct tegra_xusb_padctl *padctl;
875	875	const struct of_device_id *match;
876		− struct resource *res;
877	876	struct phy *phy;
878	877	int err;
879	878
@@ -885,11 +884,16 @@ int tegra_xusb_padctl_legacy_probe(struct platform_device *pdev) · 5 unmodified lines
885	884	mutex_init(&padctl->lock);
886	885	padctl->dev = &pdev->dev;
887	886
	887	+ /*
	888	+ * Note that we can't replace this by of_device_get_match_data()
	889	+ * because we need the separate matching table for this legacy code on
	890	+ * Tegra124. of_device_get_match_data() would attempt to use the table
	891	+ * from the updated driver and fail.
	892	+ */
888	893	match = of_match_node(tegra_xusb_padctl_of_match, pdev->dev.of_node);
889	894	padctl->soc = match->data;
890	895
891		− res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
892		− padctl->regs = devm_ioremap_resource(&pdev->dev, res);
	896	+ padctl->regs = devm_platform_ioremap_resource(pdev, 0);
893	897	if (IS_ERR(padctl->regs))
894	898	return PTR_ERR(padctl->regs);
895	899

drivers/pinctrl/tegra/pinctrl-tegra.c+1−2

@@ -781,8 +781,7 @@ int tegra_pinctrl_probe(struct platform_device *pdev, · 780 unmodified lines
781	781	return -ENOMEM;
782	782
783	783	for (i = 0; i < pmx->nbanks; i++) {
784		− res = platform_get_resource(pdev, IORESOURCE_MEM, i);
785		− pmx->regs[i] = devm_ioremap_resource(&pdev->dev, res);
	784	+ pmx->regs[i] = devm_platform_ioremap_resource(pdev, i);
786	785	if (IS_ERR(pmx->regs[i]))
787	786	return PTR_ERR(pmx->regs[i]);
788	787	}

drivers/pinctrl/ti/pinctrl-ti-iodelay.c+1−1

@@ -496,7 +496,7 @@ static int ti_iodelay_dt_node_to_map(struct pinctrl_dev *pctldev, · 495 unmodified lines
496	496	return -EINVAL;
497	497
498	498	rows = pinctrl_count_index_with_args(np, name);
499		− if (rows == -EINVAL)
	499	+ if (rows < 0)
500	500	return rows;
501	501
502	502	map = devm_kzalloc(iod->dev, sizeof(*map), GFP_KERNEL);

drivers/pinctrl/vt8500/pinctrl-wmt.c+1−3

@@ -553,10 +553,8 @@ int wmt_pinctrl_probe(struct platform_device *pdev, · 552 unmodified lines
553	553	struct wmt_pinctrl_data *data)
554	554	{
555	555	int err;
556		− struct resource *res;
557	556
558		− res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
559		− data->base = devm_ioremap_resource(&pdev->dev, res);
	557	+ data->base = devm_platform_ioremap_resource(pdev, 0);
560	558	if (IS_ERR(data->base))
561	559	return PTR_ERR(data->base);
562	560

drivers/pinctrl/zte/pinctrl-zx.c+1−3

@@ -387,7 +387,6 @@ int zx_pinctrl_init(struct platform_device *pdev, · 386 unmodified lines
387	387	struct pinctrl_desc *pctldesc;
388	388	struct zx_pinctrl *zpctl;
389	389	struct device_node *np;
390		− struct resource *res;
391	390	int ret;
392	391
393	392	zpctl = devm_kzalloc(&pdev->dev, sizeof(*zpctl), GFP_KERNEL);
@@ -396,8 +395,7 @@ int zx_pinctrl_init(struct platform_device *pdev, · 2 unmodified lines
396	395
397	396	spin_lock_init(&zpctl->lock);
398	397
399		− res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
400		− zpctl->base = devm_ioremap_resource(&pdev->dev, res);
	398	+ zpctl->base = devm_platform_ioremap_resource(pdev, 0);
401	399	if (IS_ERR(zpctl->base))
402	400	return PTR_ERR(zpctl->base);
403	401

include/dt-bindings/gpio/meson-a1-gpio.h+73−0

@@ -0,0 +1,73 @@
	1	+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
	2	+/*
	3	+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
	4	+ * Author: Qianggui Song <qianggui.song@amlogic.com>
	5	+ */
	6	+
	7	+#ifndef _DT_BINDINGS_MESON_A1_GPIO_H
	8	+#define _DT_BINDINGS_MESON_A1_GPIO_H
	9	+
	10	+#define GPIOP_0 0
	11	+#define GPIOP_1 1
	12	+#define GPIOP_2 2
	13	+#define GPIOP_3 3
	14	+#define GPIOP_4 4
	15	+#define GPIOP_5 5
	16	+#define GPIOP_6 6
	17	+#define GPIOP_7 7
	18	+#define GPIOP_8 8
	19	+#define GPIOP_9 9
	20	+#define GPIOP_10 10
	21	+#define GPIOP_11 11
	22	+#define GPIOP_12 12
	23	+#define GPIOB_0 13
	24	+#define GPIOB_1 14
	25	+#define GPIOB_2 15
	26	+#define GPIOB_3 16
	27	+#define GPIOB_4 17
	28	+#define GPIOB_5 18
	29	+#define GPIOB_6 19
	30	+#define GPIOX_0 20
	31	+#define GPIOX_1 21
	32	+#define GPIOX_2 22
	33	+#define GPIOX_3 23
	34	+#define GPIOX_4 24
	35	+#define GPIOX_5 25
	36	+#define GPIOX_6 26
	37	+#define GPIOX_7 27
	38	+#define GPIOX_8 28
	39	+#define GPIOX_9 29
	40	+#define GPIOX_10 30
	41	+#define GPIOX_11 31
	42	+#define GPIOX_12 32
	43	+#define GPIOX_13 33
	44	+#define GPIOX_14 34
	45	+#define GPIOX_15 35
	46	+#define GPIOX_16 36
	47	+#define GPIOF_0 37
	48	+#define GPIOF_1 38
	49	+#define GPIOF_2 39
	50	+#define GPIOF_3 40
	51	+#define GPIOF_4 41
	52	+#define GPIOF_5 42
	53	+#define GPIOF_6 43
	54	+#define GPIOF_7 44
	55	+#define GPIOF_8 45
	56	+#define GPIOF_9 46
	57	+#define GPIOF_10 47
	58	+#define GPIOF_11 48
	59	+#define GPIOF_12 49
	60	+#define GPIOA_0 50
	61	+#define GPIOA_1 51
	62	+#define GPIOA_2 52
	63	+#define GPIOA_3 53
	64	+#define GPIOA_4 54
	65	+#define GPIOA_5 55
	66	+#define GPIOA_6 56
	67	+#define GPIOA_7 57
	68	+#define GPIOA_8 58
	69	+#define GPIOA_9 59
	70	+#define GPIOA_10 60
	71	+#define GPIOA_11 61
	72	+
	73	+#endif /* _DT_BINDINGS_MESON_A1_GPIO_H */

include/dt-bindings/pinctrl/at91.h+2−2

@@ -27,8 +27,8 @@ · 26 unmodified lines
27	27	#define AT91_PINCTRL_DRIVE_STRENGTH_MED (0x2 << 5)
28	28	#define AT91_PINCTRL_DRIVE_STRENGTH_HI (0x3 << 5)
29	29
30		−#define AT91_PINCTRL_SLEWRATE_DIS (0x0 << 9)
31		−#define AT91_PINCTRL_SLEWRATE_ENA (0x1 << 9)
	30	+#define AT91_PINCTRL_SLEWRATE_ENA (0x0 << 9)
	31	+#define AT91_PINCTRL_SLEWRATE_DIS (0x1 << 9)
32	32
33	33	#define AT91_PIOA 0
34	34	#define AT91_PIOB 1

Merge tag 'pinctrl-v5.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

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