lael-labs/linux

Documentation/gpu/i915.rst+10−10

 GuC
 ===
+Firmware Layout
+-------------------
+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
+   :doc: Firmware Layout
 GuC-specific firmware loader
 ----------------------------
-.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_fw.c
+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
    :internal:
 GuC-based command submission
 ----------------------------
-.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_submission.c
+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
    :doc: GuC-based command submission
-.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_submission.c
+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
    :internal:
-GuC Firmware Layout
--------------------
-.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_fwif.h
-   :doc: GuC Firmware Layout
 GuC Address Space
 -----------------
-.. kernel-doc:: drivers/gpu/drm/i915/intel_guc.c
+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c
    :doc: GuC Address Space
 Tracing

arch/x86/kernel/early-quirks.c+1−0

@@ -549,6 +549,7 @@ static const struct pci_device_id intel_early_ids[] __initconst = { · 548 unmodified lines
549	INTEL_CNL_IDS(&gen9_early_ops),	549	INTEL_CNL_IDS(&gen9_early_ops),
550	INTEL_ICL_11_IDS(&gen11_early_ops),	550	INTEL_ICL_11_IDS(&gen11_early_ops),
551	INTEL_EHL_IDS(&gen11_early_ops),	551	INTEL_EHL_IDS(&gen11_early_ops),
		552	INTEL_TGL_12_IDS(&gen11_early_ops),
552	};	553	};
553		554
554	struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0, 0);	555	struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0, 0);

drivers/gpu/drm/i915/Kconfig.debug+15−0

@@ -7,6 +7,7 @@ config DRM_I915_WERROR · 6 unmodified lines
7	# We use the dependency on !COMPILE_TEST to not be enabled in	7	# We use the dependency on !COMPILE_TEST to not be enabled in
8	# allmodconfig or allyesconfig configurations	8	# allmodconfig or allyesconfig configurations
9	depends on !COMPILE_TEST	9	depends on !COMPILE_TEST
		10	select HEADER_TEST
10	default n	11	default n
11	help	12	help
12	Add -Werror to the build flags for (and only for) i915.ko.	13	Add -Werror to the build flags for (and only for) i915.ko.
@@ -94,6 +95,20 @@ config DRM_I915_TRACE_GEM · 81 unmodified lines
94		95
95	If in doubt, say "N".	96	If in doubt, say "N".
96		97
		98	config DRM_I915_TRACE_GTT
		99	bool "Insert extra ftrace output from the GTT internals"
		100	depends on DRM_I915_DEBUG_GEM
		101	select TRACING
		102	default n
		103	help
		104	Enable additional and verbose debugging output that will spam
		105	ordinary tests, but may be vital for post-mortem debugging when
		106	used with /proc/sys/kernel/ftrace_dump_on_oops
		107
		108	Recommended for driver developers only.
		109
		110	If in doubt, say "N".
		111
97	config DRM_I915_SW_FENCE_DEBUG_OBJECTS	112	config DRM_I915_SW_FENCE_DEBUG_OBJECTS
98	bool "Enable additional driver debugging for fence objects"	113	bool "Enable additional driver debugging for fence objects"
99	depends on DRM_I915	114	depends on DRM_I915

drivers/gpu/drm/i915/Makefile+43−38

@@ -32,9 +32,9 @@ subdir-ccflags-y += \ · 31 unmodified lines
32	$(call as-instr,movntdqa (%eax)$(comma)%xmm0,-DCONFIG_AS_MOVNTDQA)	32	$(call as-instr,movntdqa (%eax)$(comma)%xmm0,-DCONFIG_AS_MOVNTDQA)
33		33
34	# Extra header tests	34	# Extra header tests
35	include $(src)/Makefile.header-test	35	header-test-pattern-$(CONFIG_DRM_I915_WERROR) := *.h
36		36
37	subdir-ccflags-y += -I$(src)	37	subdir-ccflags-y += -I$(srctree)/$(src)
38		38
39	# Please keep these build lists sorted!	39	# Please keep these build lists sorted!
40		40
@@ -73,14 +73,23 @@ gt-y += \ · 32 unmodified lines
73	gt/intel_context.o \	73	gt/intel_context.o \
74	gt/intel_engine_cs.o \	74	gt/intel_engine_cs.o \
75	gt/intel_engine_pm.o \	75	gt/intel_engine_pm.o \
		76	gt/intel_gt.o \
76	gt/intel_gt_pm.o \	77	gt/intel_gt_pm.o \
77	gt/intel_hangcheck.o \	78	gt/intel_hangcheck.o \
78	gt/intel_lrc.o \	79	gt/intel_lrc.o \
		80	gt/intel_renderstate.o \
79	gt/intel_reset.o \	81	gt/intel_reset.o \
80	gt/intel_ringbuffer.o \	82	gt/intel_ringbuffer.o \
81	gt/intel_mocs.o \	83	gt/intel_mocs.o \
82	gt/intel_sseu.o \	84	gt/intel_sseu.o \
		85	gt/intel_timeline.o \
83	gt/intel_workarounds.o	86	gt/intel_workarounds.o
		87	# autogenerated null render state
		88	gt-y += \
		89	gt/gen6_renderstate.o \
		90	gt/gen7_renderstate.o \
		91	gt/gen8_renderstate.o \
		92	gt/gen9_renderstate.o
84	gt-$(CONFIG_DRM_I915_SELFTEST) += \	93	gt-$(CONFIG_DRM_I915_SELFTEST) += \
85	gt/mock_engine.o	94	gt/mock_engine.o
86	i915-y += $(gt-y)	95	i915-y += $(gt-y)
@@ -120,33 +129,26 @@ i915-y += \ · 33 unmodified lines
120	i915_gem_fence_reg.o \	129	i915_gem_fence_reg.o \
121	i915_gem_gtt.o \	130	i915_gem_gtt.o \
122	i915_gem.o \	131	i915_gem.o \
123	i915_gem_render_state.o \
124	i915_globals.o \	132	i915_globals.o \
125	i915_query.o \	133	i915_query.o \
126	i915_request.o \	134	i915_request.o \
127	i915_scheduler.o \	135	i915_scheduler.o \
128	i915_timeline.o \
129	i915_trace_points.o \	136	i915_trace_points.o \
130	i915_vma.o \	137	i915_vma.o \
131	intel_wopcm.o	138	intel_wopcm.o
132		139
133	# general-purpose microcontroller (GuC) support	140	# general-purpose microcontroller (GuC) support
134	i915-y += intel_uc.o \	141	obj-y += gt/uc/
135	intel_uc_fw.o \	142	i915-y += gt/uc/intel_uc.o \
136	intel_guc.o \	143	gt/uc/intel_uc_fw.o \
137	intel_guc_ads.o \	144	gt/uc/intel_guc.o \
138	intel_guc_ct.o \	145	gt/uc/intel_guc_ads.o \
139	intel_guc_fw.o \	146	gt/uc/intel_guc_ct.o \
140	intel_guc_log.o \	147	gt/uc/intel_guc_fw.o \
141	intel_guc_submission.o \	148	gt/uc/intel_guc_log.o \
142	intel_huc.o \	149	gt/uc/intel_guc_submission.o \
143	intel_huc_fw.o	150	gt/uc/intel_huc.o \
144		151	gt/uc/intel_huc_fw.o
145	# autogenerated null render state
146	i915-y += intel_renderstate_gen6.o \
147	intel_renderstate_gen7.o \
148	intel_renderstate_gen8.o \
149	intel_renderstate_gen9.o
150		152
151	# modesetting core code	153	# modesetting core code
152	obj-y += display/	154	obj-y += display/
@@ -173,7 +175,8 @@ i915-y += \ · 20 unmodified lines
173	display/intel_overlay.o \	175	display/intel_overlay.o \
174	display/intel_psr.o \	176	display/intel_psr.o \
175	display/intel_quirks.o \	177	display/intel_quirks.o \
176	display/intel_sprite.o	178	display/intel_sprite.o \
		179	display/intel_tc.o
177	i915-$(CONFIG_ACPI) += \	180	i915-$(CONFIG_ACPI) += \
178	display/intel_acpi.o \	181	display/intel_acpi.o \
179	display/intel_opregion.o	182	display/intel_opregion.o
@@ -210,6 +213,25 @@ i915-y += \ · 30 unmodified lines
210	display/vlv_dsi.o \	213	display/vlv_dsi.o \
211	display/vlv_dsi_pll.o	214	display/vlv_dsi_pll.o
212		215
		216	# perf code
		217	obj-y += oa/
		218	i915-y += \
		219	oa/i915_oa_hsw.o \
		220	oa/i915_oa_bdw.o \
		221	oa/i915_oa_chv.o \
		222	oa/i915_oa_sklgt2.o \
		223	oa/i915_oa_sklgt3.o \
		224	oa/i915_oa_sklgt4.o \
		225	oa/i915_oa_bxt.o \
		226	oa/i915_oa_kblgt2.o \
		227	oa/i915_oa_kblgt3.o \
		228	oa/i915_oa_glk.o \
		229	oa/i915_oa_cflgt2.o \
		230	oa/i915_oa_cflgt3.o \
		231	oa/i915_oa_cnl.o \
		232	oa/i915_oa_icl.o
		233	i915-y += i915_perf.o
		234
213	# Post-mortem debug and GPU hang state capture	235	# Post-mortem debug and GPU hang state capture
214	i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o	236	i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
215	i915-$(CONFIG_DRM_I915_SELFTEST) += \	237	i915-$(CONFIG_DRM_I915_SELFTEST) += \
@@ -224,23 +246,6 @@ i915-$(CONFIG_DRM_I915_SELFTEST) += \ · 8 unmodified lines
224	# virtual gpu code	246	# virtual gpu code
225	i915-y += i915_vgpu.o	247	i915-y += i915_vgpu.o
226		248
227	# perf code
228	i915-y += i915_perf.o \
229	i915_oa_hsw.o \
230	i915_oa_bdw.o \
231	i915_oa_chv.o \
232	i915_oa_sklgt2.o \
233	i915_oa_sklgt3.o \
234	i915_oa_sklgt4.o \
235	i915_oa_bxt.o \
236	i915_oa_kblgt2.o \
237	i915_oa_kblgt3.o \
238	i915_oa_glk.o \
239	i915_oa_cflgt2.o \
240	i915_oa_cflgt3.o \
241	i915_oa_cnl.o \
242	i915_oa_icl.o
243
244	ifeq ($(CONFIG_DRM_I915_GVT),y)	249	ifeq ($(CONFIG_DRM_I915_GVT),y)
245	i915-y += intel_gvt.o	250	i915-y += intel_gvt.o
246	include $(src)/gvt/Makefile	251	include $(src)/gvt/Makefile

drivers/gpu/drm/i915/Makefile.header-test+0−22

@@ -1,22 +0,0 @@
1	# SPDX-License-Identifier: MIT
2	# Copyright © 2019 Intel Corporation
3
4	# Test the headers are compilable as standalone units
5	header-test-$(CONFIG_DRM_I915_WERROR) := \
6	i915_active_types.h \
7	i915_debugfs.h \
8	i915_drv.h \
9	i915_irq.h \
10	i915_params.h \
11	i915_priolist_types.h \
12	i915_reg.h \
13	i915_scheduler_types.h \
14	i915_timeline_types.h \
15	i915_utils.h \
16	intel_csr.h \
17	intel_drv.h \
18	intel_pm.h \
19	intel_runtime_pm.h \
20	intel_sideband.h \
21	intel_uncore.h \
22	intel_wakeref.h

drivers/gpu/drm/i915/display/Makefile+5−1

@@ -1,2 +1,6 @@
		1	# For building individual subdir files on the command line
		2	subdir-ccflags-y += -I$(srctree)/$(src)/..
		3
1	# Extra header tests	4	# Extra header tests
2	include $(src)/Makefile.header-test	5	header-test-pattern-$(CONFIG_DRM_I915_WERROR) := *.h
		6	header-test- := intel_vbt_defs.h

drivers/gpu/drm/i915/display/Makefile.header-test+0−16

@@ -1,16 +0,0 @@
1	# SPDX-License-Identifier: MIT
2	# Copyright © 2019 Intel Corporation
3
4	# Test the headers are compilable as standalone units
5	header_test := $(notdir $(filter-out %/intel_vbt_defs.h,$(wildcard $(src)/*.h)))
6
7	quiet_cmd_header_test = HDRTEST $@
8	cmd_header_test = echo "\#include \"$(<F)\"" > $@
9
10	header_test_%.c: %.h
11	$(call cmd,header_test)
12
13	extra-$(CONFIG_DRM_I915_WERROR) += \
14	$(foreach h,$(header_test),$(patsubst %.h,header_test_%.o,$(h)))
15
16	clean-files += $(foreach h,$(header_test),$(patsubst %.h,header_test_%.c,$(h)))

drivers/gpu/drm/i915/display/icl_dsi.c+112−73

 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
-	enum port port;
+	enum phy phy;
 	u32 tmp;
 	int lane;
-	for_each_dsi_port(port, intel_dsi->ports) {
+	for_each_dsi_phy(phy, intel_dsi->phys) {
 		/*
 		 * Program voltage swing and pre-emphasis level values as per
 		 * table in BSPEC under DDI buffer programing
 		 */
-		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
+		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
 		tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK);
 		tmp |= SCALING_MODE_SEL(0x2);
 		tmp |= TAP2_DISABLE | TAP3_DISABLE;
 		tmp |= RTERM_SELECT(0x6);
-		I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
+		I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), tmp);
-		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
+		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy));
 		tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK);
 		tmp |= SCALING_MODE_SEL(0x2);
 		tmp |= TAP2_DISABLE | TAP3_DISABLE;
 		tmp |= RTERM_SELECT(0x6);
-		I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
+		I915_WRITE(ICL_PORT_TX_DW5_AUX(phy), tmp);
-		tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port));
+		tmp = I915_READ(ICL_PORT_TX_DW2_LN0(phy));
 		tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
 			 RCOMP_SCALAR_MASK);
 		tmp |= SWING_SEL_UPPER(0x2);
 		tmp |= SWING_SEL_LOWER(0x2);
 		tmp |= RCOMP_SCALAR(0x98);
-		I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
+		I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), tmp);
-		tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port));
+		tmp = I915_READ(ICL_PORT_TX_DW2_AUX(phy));
 		tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
 			 RCOMP_SCALAR_MASK);
 		tmp |= SWING_SEL_UPPER(0x2);
 		tmp |= SWING_SEL_LOWER(0x2);
 		tmp |= RCOMP_SCALAR(0x98);
-		I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp);
+		I915_WRITE(ICL_PORT_TX_DW2_AUX(phy), tmp);
-		tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port));
+		tmp = I915_READ(ICL_PORT_TX_DW4_AUX(phy));
 		tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
 			 CURSOR_COEFF_MASK);
 		tmp |= POST_CURSOR_1(0x0);
 		tmp |= POST_CURSOR_2(0x0);
 		tmp |= CURSOR_COEFF(0x3f);
-		I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp);
+		I915_WRITE(ICL_PORT_TX_DW4_AUX(phy), tmp);
 		for (lane = 0; lane <= 3; lane++) {
 			/* Bspec: must not use GRP register for write */
-			tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, port));
+			tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, phy));
 			tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
 				 CURSOR_COEFF_MASK);
 			tmp |= POST_CURSOR_1(0x0);
 			tmp |= POST_CURSOR_2(0x0);
 			tmp |= CURSOR_COEFF(0x3f);
-			I915_WRITE(ICL_PORT_TX_DW4_LN(lane, port), tmp);
+			I915_WRITE(ICL_PORT_TX_DW4_LN(lane, phy), tmp);
 		}
 	}
 }
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
-	enum port port;
+	enum phy phy;
-	for_each_dsi_port(port, intel_dsi->ports)
+	for_each_dsi_phy(phy, intel_dsi->phys)
-		intel_combo_phy_power_up_lanes(dev_priv, port, true,
+		intel_combo_phy_power_up_lanes(dev_priv, phy, true,
 					       intel_dsi->lane_count, false);
 }
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
-	enum port port;
+	enum phy phy;
 	u32 tmp;
 	int lane;
 	/* Step 4b(i) set loadgen select for transmit and aux lanes */
-	for_each_dsi_port(port, intel_dsi->ports) {
+	for_each_dsi_phy(phy, intel_dsi->phys) {
-		tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port));
+		tmp = I915_READ(ICL_PORT_TX_DW4_AUX(phy));
 		tmp &= ~LOADGEN_SELECT;
-		I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp);
+		I915_WRITE(ICL_PORT_TX_DW4_AUX(phy), tmp);
 		for (lane = 0; lane <= 3; lane++) {
-			tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, port));
+			tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, phy));
 			tmp &= ~LOADGEN_SELECT;
 			if (lane != 2)
 				tmp |= LOADGEN_SELECT;
-			I915_WRITE(ICL_PORT_TX_DW4_LN(lane, port), tmp);
+			I915_WRITE(ICL_PORT_TX_DW4_LN(lane, phy), tmp);
 		}
 	}
 	/* Step 4b(ii) set latency optimization for transmit and aux lanes */
-	for_each_dsi_port(port, intel_dsi->ports) {
+	for_each_dsi_phy(phy, intel_dsi->phys) {
-		tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port));
+		tmp = I915_READ(ICL_PORT_TX_DW2_AUX(phy));
 		tmp &= ~FRC_LATENCY_OPTIM_MASK;
 		tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
-		I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp);
+		I915_WRITE(ICL_PORT_TX_DW2_AUX(phy), tmp);
-		tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port));
+		tmp = I915_READ(ICL_PORT_TX_DW2_LN0(phy));
 		tmp &= ~FRC_LATENCY_OPTIM_MASK;
 		tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
-		I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
+		I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), tmp);
+		/* For EHL set latency optimization for PCS_DW1 lanes */
+		if (IS_ELKHARTLAKE(dev_priv)) {
+			tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(phy));
+			tmp &= ~LATENCY_OPTIM_MASK;
+			tmp |= LATENCY_OPTIM_VAL(0);
+			I915_WRITE(ICL_PORT_PCS_DW1_AUX(phy), tmp);
+			tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(phy));
+			tmp &= ~LATENCY_OPTIM_MASK;
+			tmp |= LATENCY_OPTIM_VAL(0x1);
+			I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), tmp);
+		}
 	}
 }
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	u32 tmp;
-	enum port port;
+	enum phy phy;
 	/* clear common keeper enable bit */
-	for_each_dsi_port(port, intel_dsi->ports) {
+	for_each_dsi_phy(phy, intel_dsi->phys) {
-		tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
+		tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(phy));
 		tmp &= ~COMMON_KEEPER_EN;
-		I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), tmp);
+		I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), tmp);
-		tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(port));
+		tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(phy));
 		tmp &= ~COMMON_KEEPER_EN;
-		I915_WRITE(ICL_PORT_PCS_DW1_AUX(port), tmp);
+		I915_WRITE(ICL_PORT_PCS_DW1_AUX(phy), tmp);
 	}
 	/*
 	 * Note: loadgen select program is done
 	 * as part of lane phy sequence configuration
 	 */
-	for_each_dsi_port(port, intel_dsi->ports) {
+	for_each_dsi_phy(phy, intel_dsi->phys) {
-		tmp = I915_READ(ICL_PORT_CL_DW5(port));
+		tmp = I915_READ(ICL_PORT_CL_DW5(phy));
 		tmp |= SUS_CLOCK_CONFIG;
-		I915_WRITE(ICL_PORT_CL_DW5(port), tmp);
+		I915_WRITE(ICL_PORT_CL_DW5(phy), tmp);
 	}
 	/* Clear training enable to change swing values */
-	for_each_dsi_port(port, intel_dsi->ports) {
+	for_each_dsi_phy(phy, intel_dsi->phys) {
-		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
+		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
 		tmp &= ~TX_TRAINING_EN;
-		I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
+		I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), tmp);
-		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
+		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy));
 		tmp &= ~TX_TRAINING_EN;
-		I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
+		I915_WRITE(ICL_PORT_TX_DW5_AUX(phy), tmp);
 	}
 	/* Program swing and de-emphasis */
 	dsi_program_swing_and_deemphasis(encoder);
 	/* Set training enable to trigger update */
-	for_each_dsi_port(port, intel_dsi->ports) {
+	for_each_dsi_phy(phy, intel_dsi->phys) {
-		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
+		tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
 		tmp |= TX_TRAINING_EN;
-		I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
+		I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), tmp);
-		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
+		tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy));
 		tmp |= TX_TRAINING_EN;
-		I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
+		I915_WRITE(ICL_PORT_TX_DW5_AUX(phy), tmp);
 	}
 }
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	u32 tmp;
 	enum port port;
+	enum phy phy;
 	/* Program T-INIT master registers */
 	for_each_dsi_port(port, intel_dsi->ports) {
 			I915_WRITE(DSI_TA_TIMING_PARAM(port), tmp);
 		}
 	}
+	if (IS_ELKHARTLAKE(dev_priv)) {
+		for_each_dsi_phy(phy, intel_dsi->phys) {
+			tmp = I915_READ(ICL_DPHY_CHKN(phy));
+			tmp |= ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP;
+			I915_WRITE(ICL_DPHY_CHKN(phy), tmp);
+		}
+	}
 }
 static void gen11_dsi_gate_clocks(struct intel_encoder *encoder)
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	u32 tmp;
-	enum port port;
+	enum phy phy;
 	mutex_lock(&dev_priv->dpll_lock);
-	tmp = I915_READ(DPCLKA_CFGCR0_ICL);
+	tmp = I915_READ(ICL_DPCLKA_CFGCR0);
-	for_each_dsi_port(port, intel_dsi->ports) {
+	for_each_dsi_phy(phy, intel_dsi->phys)
-		tmp |= DPCLKA_CFGCR0_DDI_CLK_OFF(port);
+		tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
-	}
-	I915_WRITE(DPCLKA_CFGCR0_ICL, tmp);
+	I915_WRITE(ICL_DPCLKA_CFGCR0, tmp);
 	mutex_unlock(&dev_priv->dpll_lock);
 }
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	u32 tmp;
-	enum port port;
+	enum phy phy;
 	mutex_lock(&dev_priv->dpll_lock);
-	tmp = I915_READ(DPCLKA_CFGCR0_ICL);
+	tmp = I915_READ(ICL_DPCLKA_CFGCR0);
-	for_each_dsi_port(port, intel_dsi->ports) {
+	for_each_dsi_phy(phy, intel_dsi->phys)
-		tmp &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
+		tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
-	}
-	I915_WRITE(DPCLKA_CFGCR0_ICL, tmp);
+	I915_WRITE(ICL_DPCLKA_CFGCR0, tmp);
 	mutex_unlock(&dev_priv->dpll_lock);
 }
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
-	enum port port;
+	enum phy phy;
 	u32 val;
 	mutex_lock(&dev_priv->dpll_lock);
-	val = I915_READ(DPCLKA_CFGCR0_ICL);
+	val = I915_READ(ICL_DPCLKA_CFGCR0);
-	for_each_dsi_port(port, intel_dsi->ports) {
+	for_each_dsi_phy(phy, intel_dsi->phys) {
-		val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
+		val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
-		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
+		val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
 	}
-	I915_WRITE(DPCLKA_CFGCR0_ICL, val);
+	I915_WRITE(ICL_DPCLKA_CFGCR0, val);
-	for_each_dsi_port(port, intel_dsi->ports) {
+	for_each_dsi_phy(phy, intel_dsi->phys) {
-		val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
+		val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
 	}
-	I915_WRITE(DPCLKA_CFGCR0_ICL, val);
+	I915_WRITE(ICL_DPCLKA_CFGCR0, val);
-	POSTING_READ(DPCLKA_CFGCR0_ICL);
+	POSTING_READ(ICL_DPCLKA_CFGCR0);
 	mutex_unlock(&dev_priv->dpll_lock);
 }
 	enum transcoder dsi_trans;
 	/* horizontal timings */
 	u16 htotal, hactive, hsync_start, hsync_end, hsync_size;
-	u16 hfront_porch, hback_porch;
+	u16 hback_porch;
 	/* vertical timings */
 	u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift;
 	hsync_start = adjusted_mode->crtc_hsync_start;
 	hsync_end = adjusted_mode->crtc_hsync_end;
 	hsync_size  = hsync_end - hsync_start;
-	hfront_porch = (adjusted_mode->crtc_hsync_start -
-			adjusted_mode->crtc_hdisplay);
 	hback_porch = (adjusted_mode->crtc_htotal -
 		       adjusted_mode->crtc_hsync_end);
 	vactive = adjusted_mode->crtc_vdisplay;
 	intel_dsi_log_params(intel_dsi);
 }
+static void icl_dsi_add_properties(struct intel_connector *connector)
+{
+	u32 allowed_scalers;
+	allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) |
+			   BIT(DRM_MODE_SCALE_FULLSCREEN) |
+			   BIT(DRM_MODE_SCALE_CENTER);
+	drm_connector_attach_scaling_mode_property(&connector->base,
+						   allowed_scalers);
+	connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT;
+	connector->base.display_info.panel_orientation =
+			intel_dsi_get_panel_orientation(connector);
+	drm_connector_init_panel_orientation_property(&connector->base,
+				connector->panel.fixed_mode->hdisplay,
+				connector->panel.fixed_mode->vdisplay);
+}
 void icl_dsi_init(struct drm_i915_private *dev_priv)
 {
 	struct drm_device *dev = &dev_priv->drm;
 	}
 	icl_dphy_param_init(intel_dsi);
+	icl_dsi_add_properties(intel_connector);
 	return;
 err:

drivers/gpu/drm/i915/display/intel_atomic_plane.c+36−20

@@ -176,33 +176,49 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_ · 175 unmodified lines
176	new_crtc_state->data_rate[plane->id] =	176	new_crtc_state->data_rate[plane->id] =
177	intel_plane_data_rate(new_crtc_state, new_plane_state);	177	intel_plane_data_rate(new_crtc_state, new_plane_state);
178		178
179	return intel_plane_atomic_calc_changes(old_crtc_state,	179	return intel_plane_atomic_calc_changes(old_crtc_state, new_crtc_state,
180	&new_crtc_state->base,	180	old_plane_state, new_plane_state);
181	old_plane_state,
182	&new_plane_state->base);
183	}	181	}
184		182
185	static int intel_plane_atomic_check(struct drm_plane *plane,	183	static struct intel_crtc *
186	struct drm_plane_state *new_plane_state)	184	get_crtc_from_states(const struct intel_plane_state *old_plane_state,
		185	const struct intel_plane_state *new_plane_state)
187	{	186	{
188	struct drm_atomic_state *state = new_plane_state->state;	187	if (new_plane_state->base.crtc)
189	const struct drm_plane_state *old_plane_state =	188	return to_intel_crtc(new_plane_state->base.crtc);
190	drm_atomic_get_old_plane_state(state, plane);	189
191	struct drm_crtc *crtc = new_plane_state->crtc ?: old_plane_state->crtc;	190	if (old_plane_state->base.crtc)
192	const struct drm_crtc_state *old_crtc_state;	191	return to_intel_crtc(old_plane_state->base.crtc);
193	struct drm_crtc_state *new_crtc_state;	192
194		193	return NULL;
195	new_plane_state->visible = false;	194	}
		195
		196	static int intel_plane_atomic_check(struct drm_plane *_plane,
		197	struct drm_plane_state *_new_plane_state)
		198	{
		199	struct intel_plane *plane = to_intel_plane(_plane);
		200	struct intel_atomic_state *state =
		201	to_intel_atomic_state(_new_plane_state->state);
		202	struct intel_plane_state *new_plane_state =
		203	to_intel_plane_state(_new_plane_state);
		204	const struct intel_plane_state *old_plane_state =
		205	intel_atomic_get_old_plane_state(state, plane);
		206	struct intel_crtc *crtc =
		207	get_crtc_from_states(old_plane_state, new_plane_state);
		208	const struct intel_crtc_state *old_crtc_state;
		209	struct intel_crtc_state *new_crtc_state;
		210
		211	new_plane_state->base.visible = false;
196	if (!crtc)	212	if (!crtc)
197	return 0;	213	return 0;
198		214
199	old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc);	215	old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
200	new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);	216	new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
201		217
202	return intel_plane_atomic_check_with_state(to_intel_crtc_state(old_crtc_state),	218	return intel_plane_atomic_check_with_state(old_crtc_state,
203	to_intel_crtc_state(new_crtc_state),	219	new_crtc_state,
204	to_intel_plane_state(old_plane_state),	220	old_plane_state,
205	to_intel_plane_state(new_plane_state));	221	new_plane_state);
206	}	222	}
207		223
208	static struct intel_plane *	224	static struct intel_plane *

drivers/gpu/drm/i915/display/intel_atomic_plane.h+2−3

 #include <linux/types.h>
-struct drm_crtc_state;
 struct drm_plane;
 struct drm_property;
 struct intel_atomic_state;
 					const struct intel_plane_state *old_plane_state,
 					struct intel_plane_state *intel_state);
 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
-				    struct drm_crtc_state *crtc_state,
+				    struct intel_crtc_state *crtc_state,
 				    const struct intel_plane_state *old_plane_state,
-				    struct drm_plane_state *plane_state);
+				    struct intel_plane_state *plane_state);
 #endif /* __INTEL_ATOMIC_PLANE_H__ */

drivers/gpu/drm/i915/display/intel_audio.c+68−13

@@ -72,6 +72,13 @@ struct dp_aud_n_m { · 71 unmodified lines
72	u16 n;	72	u16 n;
73	};	73	};
74		74
		75	struct hdmi_aud_ncts {
		76	int sample_rate;
		77	int clock;
		78	int n;
		79	int cts;
		80	};
		81
75	/* Values according to DP 1.4 Table 2-104 */	82	/* Values according to DP 1.4 Table 2-104 */
76	static const struct dp_aud_n_m dp_aud_n_m[] = {	83	static const struct dp_aud_n_m dp_aud_n_m[] = {
77	{ 32000, LC_162M, 1024, 10125 },	84	{ 32000, LC_162M, 1024, 10125 },
@@ -148,12 +155,7 @@ static const struct { · 70 unmodified lines
148	#define TMDS_594M 594000	155	#define TMDS_594M 594000
149	#define TMDS_593M 593407	156	#define TMDS_593M 593407
150		157
151	static const struct {	158	static const struct hdmi_aud_ncts hdmi_aud_ncts_24bpp[] = {
152	int sample_rate;
153	int clock;
154	int n;
155	int cts;
156	} hdmi_aud_ncts[] = {
157	{ 32000, TMDS_296M, 5824, 421875 },	159	{ 32000, TMDS_296M, 5824, 421875 },
158	{ 32000, TMDS_297M, 3072, 222750 },	160	{ 32000, TMDS_297M, 3072, 222750 },
159	{ 32000, TMDS_593M, 5824, 843750 },	161	{ 32000, TMDS_593M, 5824, 843750 },
@@ -184,6 +186,49 @@ static const struct { · 24 unmodified lines
184	{ 192000, TMDS_594M, 24576, 594000 },	186	{ 192000, TMDS_594M, 24576, 594000 },
185	};	187	};
186		188
		189	/* Appendix C - N & CTS values for deep color from HDMI 2.0 spec*/
		190	/* HDMI N/CTS table for 10 bit deep color(30 bpp)*/
		191	#define TMDS_371M 371250
		192	#define TMDS_370M 370878
		193
		194	static const struct hdmi_aud_ncts hdmi_aud_ncts_30bpp[] = {
		195	{ 32000, TMDS_370M, 5824, 527344 },
		196	{ 32000, TMDS_371M, 6144, 556875 },
		197	{ 44100, TMDS_370M, 8918, 585938 },
		198	{ 44100, TMDS_371M, 4704, 309375 },
		199	{ 88200, TMDS_370M, 17836, 585938 },
		200	{ 88200, TMDS_371M, 9408, 309375 },
		201	{ 176400, TMDS_370M, 35672, 585938 },
		202	{ 176400, TMDS_371M, 18816, 309375 },
		203	{ 48000, TMDS_370M, 11648, 703125 },
		204	{ 48000, TMDS_371M, 5120, 309375 },
		205	{ 96000, TMDS_370M, 23296, 703125 },
		206	{ 96000, TMDS_371M, 10240, 309375 },
		207	{ 192000, TMDS_370M, 46592, 703125 },
		208	{ 192000, TMDS_371M, 20480, 309375 },
		209	};
		210
		211	/* HDMI N/CTS table for 12 bit deep color(36 bpp)*/
		212	#define TMDS_445_5M 445500
		213	#define TMDS_445M 445054
		214
		215	static const struct hdmi_aud_ncts hdmi_aud_ncts_36bpp[] = {
		216	{ 32000, TMDS_445M, 5824, 632813 },
		217	{ 32000, TMDS_445_5M, 4096, 445500 },
		218	{ 44100, TMDS_445M, 8918, 703125 },
		219	{ 44100, TMDS_445_5M, 4704, 371250 },
		220	{ 88200, TMDS_445M, 17836, 703125 },
		221	{ 88200, TMDS_445_5M, 9408, 371250 },
		222	{ 176400, TMDS_445M, 35672, 703125 },
		223	{ 176400, TMDS_445_5M, 18816, 371250 },
		224	{ 48000, TMDS_445M, 5824, 421875 },
		225	{ 48000, TMDS_445_5M, 5120, 371250 },
		226	{ 96000, TMDS_445M, 11648, 421875 },
		227	{ 96000, TMDS_445_5M, 10240, 371250 },
		228	{ 192000, TMDS_445M, 23296, 421875 },
		229	{ 192000, TMDS_445_5M, 20480, 371250 },
		230	};
		231
187	/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */	232	/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
188	static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state)	233	static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state)
189	{	234	{
@@ -212,14 +257,24 @@ static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_sta · 22 unmodified lines
212	static int audio_config_hdmi_get_n(const struct intel_crtc_state *crtc_state,	257	static int audio_config_hdmi_get_n(const struct intel_crtc_state *crtc_state,
213	int rate)	258	int rate)
214	{	259	{
215	const struct drm_display_mode *adjusted_mode =	260	const struct hdmi_aud_ncts *hdmi_ncts_table;
216	&crtc_state->base.adjusted_mode;	261	int i, size;
217	int i;	262
		263	if (crtc_state->pipe_bpp == 36) {
		264	hdmi_ncts_table = hdmi_aud_ncts_36bpp;
		265	size = ARRAY_SIZE(hdmi_aud_ncts_36bpp);
		266	} else if (crtc_state->pipe_bpp == 30) {
		267	hdmi_ncts_table = hdmi_aud_ncts_30bpp;
		268	size = ARRAY_SIZE(hdmi_aud_ncts_30bpp);
		269	} else {
		270	hdmi_ncts_table = hdmi_aud_ncts_24bpp;
		271	size = ARRAY_SIZE(hdmi_aud_ncts_24bpp);
		272	}
218		273
219	for (i = 0; i < ARRAY_SIZE(hdmi_aud_ncts); i++) {	274	for (i = 0; i < size; i++) {
220	if (rate == hdmi_aud_ncts[i].sample_rate &&	275	if (rate == hdmi_ncts_table[i].sample_rate &&
221	adjusted_mode->crtc_clock == hdmi_aud_ncts[i].clock) {	276	crtc_state->port_clock == hdmi_ncts_table[i].clock) {
222	return hdmi_aud_ncts[i].n;	277	return hdmi_ncts_table[i].n;
223	}	278	}
224	}	279	}
225	return 0;	280	return 0;

drivers/gpu/drm/i915/display/intel_bios.c+24−4

 #include <drm/drm_dp_helper.h>
 #include <drm/i915_drm.h>
+#include "display/intel_display.h"
 #include "display/intel_gmbus.h"
 #include "i915_drv.h"
 	[MCC_DDC_BUS_DDI_C] = GMBUS_PIN_9_TC1_ICP,
 };
+static const u8 tgp_ddc_pin_map[] = {
+	[ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,
+	[ICL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT,
+	[TGL_DDC_BUS_DDI_C] = GMBUS_PIN_3_BXT,
+	[ICL_DDC_BUS_PORT_1] = GMBUS_PIN_9_TC1_ICP,
+	[ICL_DDC_BUS_PORT_2] = GMBUS_PIN_10_TC2_ICP,
+	[ICL_DDC_BUS_PORT_3] = GMBUS_PIN_11_TC3_ICP,
+	[ICL_DDC_BUS_PORT_4] = GMBUS_PIN_12_TC4_ICP,
+	[TGL_DDC_BUS_PORT_5] = GMBUS_PIN_13_TC5_TGP,
+	[TGL_DDC_BUS_PORT_6] = GMBUS_PIN_14_TC6_TGP,
+};
 static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
 {
 	const u8 *ddc_pin_map;
 	int n_entries;
-	if (HAS_PCH_MCC(dev_priv)) {
+	if (HAS_PCH_TGP(dev_priv)) {
+		ddc_pin_map = tgp_ddc_pin_map;
+		n_entries = ARRAY_SIZE(tgp_ddc_pin_map);
+	} else if (HAS_PCH_MCC(dev_priv)) {
 		ddc_pin_map = mcc_ddc_pin_map;
 		n_entries = ARRAY_SIZE(mcc_ddc_pin_map);
 	} else if (HAS_PCH_ICP(dev_priv)) {
 		if (!child->device_type)
 			continue;
+		DRM_DEBUG_KMS("Found VBT child device with type 0x%x\n",
+			      child->device_type);
 		/*
 		 * Copy as much as we know (sizeof) and is available
 		 * (child_dev_size) of the child device. Accessing the data must
 	for (port = PORT_A; port < I915_MAX_PORTS; port++) {
 		struct ddi_vbt_port_info *info =
 			&dev_priv->vbt.ddi_port_info[port];
+		enum phy phy = intel_port_to_phy(dev_priv, port);
 		/*
 		 * VBT has the TypeC mode (native,TBT/USB) and we don't want
 		 * to detect it.
 		 */
-		if (intel_port_is_tc(dev_priv, port))
+		if (intel_phy_is_tc(dev_priv, phy))
 			continue;
 		info->supports_dvi = (port != PORT_A && port != PORT_E);
 }
 /**
- * intel_bios_cleanup - Free any resources allocated by intel_bios_init()
+ * intel_bios_driver_remove - Free any resources allocated by intel_bios_init()
  * @dev_priv: i915 device instance
  */
-void intel_bios_cleanup(struct drm_i915_private *dev_priv)
+void intel_bios_driver_remove(struct drm_i915_private *dev_priv)
 {
 	kfree(dev_priv->vbt.child_dev);
 	dev_priv->vbt.child_dev = NULL;

drivers/gpu/drm/i915/display/intel_bios.h+2−1

 	INTEL_BACKLIGHT_DISPLAY_DDI,
 	INTEL_BACKLIGHT_DSI_DCS,
 	INTEL_BACKLIGHT_PANEL_DRIVER_INTERFACE,
+	INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE,
 };
 struct edp_power_seq {
 } __packed;
 void intel_bios_init(struct drm_i915_private *dev_priv);
-void intel_bios_cleanup(struct drm_i915_private *dev_priv);
+void intel_bios_driver_remove(struct drm_i915_private *dev_priv);
 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);

drivers/gpu/drm/i915/display/intel_bw.c+1−1

@@ -65,7 +65,7 @@ static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv, · 64 unmodified lines
65	struct intel_qgv_point *sp,	65	struct intel_qgv_point *sp,
66	int point)	66	int point)
67	{	67	{
68	u32 val = 0, val2;	68	u32 val = 0, val2 = 0;
69	int ret;	69	int ret;
70		70
71	ret = sandybridge_pcode_read(dev_priv,	71	ret = sandybridge_pcode_read(dev_priv,

drivers/gpu/drm/i915/display/intel_cdclk.c+56−28

@@ -545,10 +545,10 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv, · 544 unmodified lines
545	/* There are cases where we can end up here with power domains	545	/* There are cases where we can end up here with power domains
546	* off and a CDCLK frequency other than the minimum, like when	546	* off and a CDCLK frequency other than the minimum, like when
547	* issuing a modeset without actually changing any display after	547	* issuing a modeset without actually changing any display after
548	* a system suspend. So grab the PIPE-A domain, which covers	548	* a system suspend. So grab the display core domain, which covers
549	* the HW blocks needed for the following programming.	549	* the HW blocks needed for the following programming.
550	*/	550	*/
551	wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);	551	wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
552		552
553	vlv_iosf_sb_get(dev_priv,	553	vlv_iosf_sb_get(dev_priv,
554	BIT(VLV_IOSF_SB_CCK) \|	554	BIT(VLV_IOSF_SB_CCK) \|
@@ -606,7 +606,7 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv, · 51 unmodified lines
606		606
607	vlv_program_pfi_credits(dev_priv);	607	vlv_program_pfi_credits(dev_priv);
608		608
609	intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A, wakeref);	609	intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
610	}	610	}
611		611
612	static void chv_set_cdclk(struct drm_i915_private *dev_priv,	612	static void chv_set_cdclk(struct drm_i915_private *dev_priv,
@@ -631,10 +631,10 @@ static void chv_set_cdclk(struct drm_i915_private *dev_priv, · 18 unmodified lines
631	/* There are cases where we can end up here with power domains	631	/* There are cases where we can end up here with power domains
632	* off and a CDCLK frequency other than the minimum, like when	632	* off and a CDCLK frequency other than the minimum, like when
633	* issuing a modeset without actually changing any display after	633	* issuing a modeset without actually changing any display after
634	* a system suspend. So grab the PIPE-A domain, which covers	634	* a system suspend. So grab the display core domain, which covers
635	* the HW blocks needed for the following programming.	635	* the HW blocks needed for the following programming.
636	*/	636	*/
637	wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);	637	wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
638		638
639	vlv_punit_get(dev_priv);	639	vlv_punit_get(dev_priv);
640	val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);	640	val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
@@ -653,7 +653,7 @@ static void chv_set_cdclk(struct drm_i915_private *dev_priv, · 12 unmodified lines
653		653
654	vlv_program_pfi_credits(dev_priv);	654	vlv_program_pfi_credits(dev_priv);
655		655
656	intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A, wakeref);	656	intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
657	}	657	}
658		658
659	static int bdw_calc_cdclk(int min_cdclk)	659	static int bdw_calc_cdclk(int min_cdclk)
@@ -1756,9 +1756,10 @@ sanitize: · 1096 unmodified lines
1756		1756
1757	static int icl_calc_cdclk(int min_cdclk, unsigned int ref)	1757	static int icl_calc_cdclk(int min_cdclk, unsigned int ref)
1758	{	1758	{
1759	int ranges_24[] = { 312000, 552000, 648000 };	1759	static const int ranges_24[] = { 180000, 192000, 312000, 552000, 648000 };
1760	int ranges_19_38[] = { 307200, 556800, 652800 };	1760	static const int ranges_19_38[] = { 172800, 192000, 307200, 556800, 652800 };
1761	int *ranges;	1761	const int *ranges;
		1762	int len, i;
1762		1763
1763	switch (ref) {	1764	switch (ref) {
1764	default:	1765	default:
@@ -1766,19 +1767,22 @@ static int icl_calc_cdclk(int min_cdclk, unsigned int ref) · 1 unmodified line
1766	/* fall through */	1767	/* fall through */
1767	case 24000:	1768	case 24000:
1768	ranges = ranges_24;	1769	ranges = ranges_24;
		1770	len = ARRAY_SIZE(ranges_24);
1769	break;	1771	break;
1770	case 19200:	1772	case 19200:
1771	case 38400:	1773	case 38400:
1772	ranges = ranges_19_38;	1774	ranges = ranges_19_38;
		1775	len = ARRAY_SIZE(ranges_19_38);
1773	break;	1776	break;
1774	}	1777	}
1775		1778
1776	if (min_cdclk > ranges[1])	1779	for (i = 0; i < len; i++) {
1777	return ranges[2];	1780	if (min_cdclk <= ranges[i])
1778	else if (min_cdclk > ranges[0])	1781	return ranges[i];
1779	return ranges[1];	1782	}
1780	else	1783
1781	return ranges[0];	1784	WARN_ON(min_cdclk > ranges[len - 1]);
		1785	return ranges[len - 1];
1782	}	1786	}
1783		1787
1784	static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)	1788	static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
@@ -1792,16 +1796,24 @@ static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk) · 7 unmodified lines
1792	default:	1796	default:
1793	MISSING_CASE(cdclk);	1797	MISSING_CASE(cdclk);
1794	/* fall through */	1798	/* fall through */
		1799	case 172800:
1795	case 307200:	1800	case 307200:
1796	case 556800:	1801	case 556800:
1797	case 652800:	1802	case 652800:
1798	WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&	1803	WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
1799	dev_priv->cdclk.hw.ref != 38400);	1804	dev_priv->cdclk.hw.ref != 38400);
1800	break;	1805	break;
		1806	case 180000:
1801	case 312000:	1807	case 312000:
1802	case 552000:	1808	case 552000:
1803	case 648000:	1809	case 648000:
1804	WARN_ON(dev_priv->cdclk.hw.ref != 24000);	1810	WARN_ON(dev_priv->cdclk.hw.ref != 24000);
		1811	break;
		1812	case 192000:
		1813	WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
		1814	dev_priv->cdclk.hw.ref != 38400 &&
		1815	dev_priv->cdclk.hw.ref != 24000);
		1816	break;
1805	}	1817	}
1806		1818
1807	ratio = cdclk / (dev_priv->cdclk.hw.ref / 2);	1819	ratio = cdclk / (dev_priv->cdclk.hw.ref / 2);
@@ -1854,14 +1866,23 @@ static void icl_set_cdclk(struct drm_i915_private *dev_priv, · 46 unmodified lines
1854	dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level;	1866	dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level;
1855	}	1867	}
1856		1868
1857	static u8 icl_calc_voltage_level(int cdclk)	1869	static u8 icl_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk)
1858	{	1870	{
1859	if (cdclk > 556800)	1871	if (IS_ELKHARTLAKE(dev_priv)) {
1860	return 2;	1872	if (cdclk > 312000)
1861	else if (cdclk > 312000)	1873	return 2;
1862	return 1;	1874	else if (cdclk > 180000)
1863	else	1875	return 1;
1864	return 0;	1876	else
		1877	return 0;
		1878	} else {
		1879	if (cdclk > 556800)
		1880	return 2;
		1881	else if (cdclk > 312000)
		1882	return 1;
		1883	else
		1884	return 0;
		1885	}
1865	}	1886	}
1866		1887
1867	static void icl_get_cdclk(struct drm_i915_private *dev_priv,	1888	static void icl_get_cdclk(struct drm_i915_private *dev_priv,
@@ -1912,7 +1933,7 @@ out: · 44 unmodified lines
1912	* at least what the CDCLK frequency requires.	1933	* at least what the CDCLK frequency requires.
1913	*/	1934	*/
1914	cdclk_state->voltage_level =	1935	cdclk_state->voltage_level =
1915	icl_calc_voltage_level(cdclk_state->cdclk);	1936	icl_calc_voltage_level(dev_priv, cdclk_state->cdclk);
1916	}	1937	}
1917		1938
1918	static void icl_init_cdclk(struct drm_i915_private *dev_priv)	1939	static void icl_init_cdclk(struct drm_i915_private *dev_priv)
@@ -1947,7 +1968,8 @@ sanitize: · 28 unmodified lines
1947	sanitized_state.vco = icl_calc_cdclk_pll_vco(dev_priv,	1968	sanitized_state.vco = icl_calc_cdclk_pll_vco(dev_priv,
1948	sanitized_state.cdclk);	1969	sanitized_state.cdclk);
1949	sanitized_state.voltage_level =	1970	sanitized_state.voltage_level =
1950	icl_calc_voltage_level(sanitized_state.cdclk);	1971	icl_calc_voltage_level(dev_priv,
		1972	sanitized_state.cdclk);
1951		1973
1952	icl_set_cdclk(dev_priv, &sanitized_state, INVALID_PIPE);	1974	icl_set_cdclk(dev_priv, &sanitized_state, INVALID_PIPE);
1953	}	1975	}
@@ -1958,7 +1980,8 @@ static void icl_uninit_cdclk(struct drm_i915_private *dev_priv) · 4 unmodified lines
1958		1980
1959	cdclk_state.cdclk = cdclk_state.bypass;	1981	cdclk_state.cdclk = cdclk_state.bypass;
1960	cdclk_state.vco = 0;	1982	cdclk_state.vco = 0;
1961	cdclk_state.voltage_level = icl_calc_voltage_level(cdclk_state.cdclk);	1983	cdclk_state.voltage_level = icl_calc_voltage_level(dev_priv,
		1984	cdclk_state.cdclk);
1962		1985
1963	icl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);	1986	icl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
1964	}	1987	}
@@ -2560,7 +2583,7 @@ static int icl_modeset_calc_cdclk(struct intel_atomic_state *state) · 595 unmodified lines
2560	state->cdclk.logical.vco = vco;	2583	state->cdclk.logical.vco = vco;
2561	state->cdclk.logical.cdclk = cdclk;	2584	state->cdclk.logical.cdclk = cdclk;
2562	state->cdclk.logical.voltage_level =	2585	state->cdclk.logical.voltage_level =
2563	max(icl_calc_voltage_level(cdclk),	2586	max(icl_calc_voltage_level(dev_priv, cdclk),
2564	cnl_compute_min_voltage_level(state));	2587	cnl_compute_min_voltage_level(state));
2565		2588
2566	if (!state->active_crtcs) {	2589	if (!state->active_crtcs) {
@@ -2570,7 +2593,7 @@ static int icl_modeset_calc_cdclk(struct intel_atomic_state *state) · 3 unmodified lines
2570	state->cdclk.actual.vco = vco;	2593	state->cdclk.actual.vco = vco;
2571	state->cdclk.actual.cdclk = cdclk;	2594	state->cdclk.actual.cdclk = cdclk;
2572	state->cdclk.actual.voltage_level =	2595	state->cdclk.actual.voltage_level =
2573	icl_calc_voltage_level(cdclk);	2596	icl_calc_voltage_level(dev_priv, cdclk);
2574	} else {	2597	} else {
2575	state->cdclk.actual = state->cdclk.logical;	2598	state->cdclk.actual = state->cdclk.logical;
2576	}	2599	}
@@ -2605,7 +2628,12 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) · 28 unmodified lines
2605	*/	2628	*/
2606	void intel_update_max_cdclk(struct drm_i915_private *dev_priv)	2629	void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
2607	{	2630	{
2608	if (INTEL_GEN(dev_priv) >= 11) {	2631	if (IS_ELKHARTLAKE(dev_priv)) {
		2632	if (dev_priv->cdclk.hw.ref == 24000)
		2633	dev_priv->max_cdclk_freq = 552000;
		2634	else
		2635	dev_priv->max_cdclk_freq = 556800;
		2636	} else if (INTEL_GEN(dev_priv) >= 11) {
2609	if (dev_priv->cdclk.hw.ref == 24000)	2637	if (dev_priv->cdclk.hw.ref == 24000)
2610	dev_priv->max_cdclk_freq = 648000;	2638	dev_priv->max_cdclk_freq = 648000;
2611	else	2639	else

drivers/gpu/drm/i915/display/intel_combo_phy.c+125−68

 #include "intel_combo_phy.h"
 #include "intel_drv.h"
-#define for_each_combo_port(__dev_priv, __port) \
+#define for_each_combo_phy(__dev_priv, __phy) \
-	for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)	\
+	for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++)	\
-		for_each_if(intel_port_is_combophy(__dev_priv, __port))
+		for_each_if(intel_phy_is_combo(__dev_priv, __phy))
-#define for_each_combo_port_reverse(__dev_priv, __port) \
+#define for_each_combo_phy_reverse(__dev_priv, __phy) \
-	for ((__port) = I915_MAX_PORTS; (__port)-- > PORT_A;) \
+	for ((__phy) = I915_MAX_PHYS; (__phy)-- > PHY_A;) \
-		for_each_if(intel_port_is_combophy(__dev_priv, __port))
+		for_each_if(intel_phy_is_combo(__dev_priv, __phy))
 enum {
 	PROCMON_0_85V_DOT_0,
 };
 /*
- * CNL has just one set of registers, while ICL has two sets: one for port A and
+ * CNL has just one set of registers, while gen11 has a set for each combo PHY.
- * the other for port B. The CNL registers are equivalent to the ICL port A
+ * The CNL registers are equivalent to the gen11 PHY A registers, that's why we
- * registers, that's why we call the ICL macros even though the function has CNL
+ * call the ICL macros even though the function has CNL on its name.
- * on its name.
  */
 static const struct cnl_procmon *
-cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum port port)
+cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy)
 {
 	const struct cnl_procmon *procmon;
 	u32 val;
-	val = I915_READ(ICL_PORT_COMP_DW3(port));
+	val = I915_READ(ICL_PORT_COMP_DW3(phy));
 	switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) {
 	default:
 		MISSING_CASE(val);
 }
 static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv,
-				       enum port port)
+				       enum phy phy)
 {
 	const struct cnl_procmon *procmon;
 	u32 val;
-	procmon = cnl_get_procmon_ref_values(dev_priv, port);
+	procmon = cnl_get_procmon_ref_values(dev_priv, phy);
-	val = I915_READ(ICL_PORT_COMP_DW1(port));
+	val = I915_READ(ICL_PORT_COMP_DW1(phy));
 	val &= ~((0xff << 16) | 0xff);
 	val |= procmon->dw1;
-	I915_WRITE(ICL_PORT_COMP_DW1(port), val);
+	I915_WRITE(ICL_PORT_COMP_DW1(phy), val);
-	I915_WRITE(ICL_PORT_COMP_DW9(port), procmon->dw9);
+	I915_WRITE(ICL_PORT_COMP_DW9(phy), procmon->dw9);
-	I915_WRITE(ICL_PORT_COMP_DW10(port), procmon->dw10);
+	I915_WRITE(ICL_PORT_COMP_DW10(phy), procmon->dw10);
 }
 static bool check_phy_reg(struct drm_i915_private *dev_priv,
-			  enum port port, i915_reg_t reg, u32 mask,
+			  enum phy phy, i915_reg_t reg, u32 mask,
 			  u32 expected_val)
 {
 	u32 val = I915_READ(reg);
 	if ((val & mask) != expected_val) {
-		DRM_DEBUG_DRIVER("Port %c combo PHY reg %08x state mismatch: "
+		DRM_DEBUG_DRIVER("Combo PHY %c reg %08x state mismatch: "
 				 "current %08x mask %08x expected %08x\n",
-				 port_name(port),
+				 phy_name(phy),
 				 reg.reg, val, mask, expected_val);
 		return false;
 	}
 }
 static bool cnl_verify_procmon_ref_values(struct drm_i915_private *dev_priv,
-					  enum port port)
+					  enum phy phy)
 {
 	const struct cnl_procmon *procmon;
 	bool ret;
-	procmon = cnl_get_procmon_ref_values(dev_priv, port);
+	procmon = cnl_get_procmon_ref_values(dev_priv, phy);
-	ret = check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW1(port),
+	ret = check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW1(phy),
 			    (0xff << 16) | 0xff, procmon->dw1);
-	ret &= check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW9(port),
+	ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW9(phy),
 			     -1U, procmon->dw9);
-	ret &= check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW10(port),
+	ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW10(phy),
 			     -1U, procmon->dw10);
 	return ret;
 static bool cnl_combo_phy_verify_state(struct drm_i915_private *dev_priv)
 {
-	enum port port = PORT_A;
+	enum phy phy = PHY_A;
 	bool ret;
 	if (!cnl_combo_phy_enabled(dev_priv))
 		return false;
-	ret = cnl_verify_procmon_ref_values(dev_priv, port);
+	ret = cnl_verify_procmon_ref_values(dev_priv, phy);
-	ret &= check_phy_reg(dev_priv, port, CNL_PORT_CL1CM_DW5,
+	ret &= check_phy_reg(dev_priv, phy, CNL_PORT_CL1CM_DW5,
 			     CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE);
 	return ret;
 	I915_WRITE(CHICKEN_MISC_2, val);
 	/* Dummy PORT_A to get the correct CNL register from the ICL macro */
-	cnl_set_procmon_ref_values(dev_priv, PORT_A);
+	cnl_set_procmon_ref_values(dev_priv, PHY_A);
 	val = I915_READ(CNL_PORT_COMP_DW0);
 	val |= COMP_INIT;
 }
 static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv,
-				  enum port port)
+				  enum phy phy)
 {
-	return !(I915_READ(ICL_PHY_MISC(port)) &
+	/* The PHY C added by EHL has no PHY_MISC register */
-		 ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) &&
+	if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C)
-		(I915_READ(ICL_PORT_COMP_DW0(port)) & COMP_INIT);
+		return I915_READ(ICL_PORT_COMP_DW0(phy)) & COMP_INIT;
+	else
+		return !(I915_READ(ICL_PHY_MISC(phy)) &
+			 ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) &&
+			(I915_READ(ICL_PORT_COMP_DW0(phy)) & COMP_INIT);
 }
 static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
-				       enum port port)
+				       enum phy phy)
 {
 	bool ret;
-	if (!icl_combo_phy_enabled(dev_priv, port))
+	if (!icl_combo_phy_enabled(dev_priv, phy))
 		return false;
-	ret = cnl_verify_procmon_ref_values(dev_priv, port);
+	ret = cnl_verify_procmon_ref_values(dev_priv, phy);
-	if (port == PORT_A)
+	if (phy == PHY_A)
-		ret &= check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW8(port),
+		ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy),
 				     IREFGEN, IREFGEN);
-	ret &= check_phy_reg(dev_priv, port, ICL_PORT_CL_DW5(port),
+	ret &= check_phy_reg(dev_priv, phy, ICL_PORT_CL_DW5(phy),
 			     CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE);
 	return ret;
 }
 void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv,
-				    enum port port, bool is_dsi,
+				    enum phy phy, bool is_dsi,
 				    int lane_count, bool lane_reversal)
 {
 	u8 lane_mask;
 		}
 	}
-	val = I915_READ(ICL_PORT_CL_DW10(port));
+	val = I915_READ(ICL_PORT_CL_DW10(phy));
 	val &= ~PWR_DOWN_LN_MASK;
 	val |= lane_mask << PWR_DOWN_LN_SHIFT;
-	I915_WRITE(ICL_PORT_CL_DW10(port), val);
+	I915_WRITE(ICL_PORT_CL_DW10(phy), val);
+}
+static u32 ehl_combo_phy_a_mux(struct drm_i915_private *i915, u32 val)
+{
+	bool ddi_a_present = i915->vbt.ddi_port_info[PORT_A].child != NULL;
+	bool ddi_d_present = i915->vbt.ddi_port_info[PORT_D].child != NULL;
+	bool dsi_present = intel_bios_is_dsi_present(i915, NULL);
+	/*
+	 * VBT's 'dvo port' field for child devices references the DDI, not
+	 * the PHY.  So if combo PHY A is wired up to drive an external
+	 * display, we should see a child device present on PORT_D and
+	 * nothing on PORT_A and no DSI.
+	 */
+	if (ddi_d_present && !ddi_a_present && !dsi_present)
+		return val | ICL_PHY_MISC_MUX_DDID;
+	/*
+	 * If we encounter a VBT that claims to have an external display on
+	 * DDI-D _and_ an internal display on DDI-A/DSI leave an error message
+	 * in the log and let the internal display win.
+	 */
+	if (ddi_d_present)
+		DRM_ERROR("VBT claims to have both internal and external displays on PHY A.  Configuring for internal.\n");
+	return val & ~ICL_PHY_MISC_MUX_DDID;
 }
 static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
 {
-	enum port port;
+	enum phy phy;
-	for_each_combo_port(dev_priv, port) {
+	for_each_combo_phy(dev_priv, phy) {
 		u32 val;
-		if (icl_combo_phy_verify_state(dev_priv, port)) {
+		if (icl_combo_phy_verify_state(dev_priv, phy)) {
-			DRM_DEBUG_DRIVER("Port %c combo PHY already enabled, won't reprogram it.\n",
+			DRM_DEBUG_DRIVER("Combo PHY %c already enabled, won't reprogram it.\n",
-					 port_name(port));
+					 phy_name(phy));
 			continue;
 		}
-		val = I915_READ(ICL_PHY_MISC(port));
+		/*
+		 * Although EHL adds a combo PHY C, there's no PHY_MISC
+		 * register for it and no need to program the
+		 * DE_IO_COMP_PWR_DOWN setting on PHY C.
+		 */
+		if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C)
+			goto skip_phy_misc;
+		/*
+		 * EHL's combo PHY A can be hooked up to either an external
+		 * display (via DDI-D) or an internal display (via DDI-A or
+		 * the DSI DPHY).  This is a motherboard design decision that
+		 * can't be changed on the fly, so initialize the PHY's mux
+		 * based on whether our VBT indicates the presence of any
+		 * "internal" child devices.
+		 */
+		val = I915_READ(ICL_PHY_MISC(phy));
+		if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_A)
+			val = ehl_combo_phy_a_mux(dev_priv, val);
 		val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
-		I915_WRITE(ICL_PHY_MISC(port), val);
+		I915_WRITE(ICL_PHY_MISC(phy), val);
-		cnl_set_procmon_ref_values(dev_priv, port);
+skip_phy_misc:
+		cnl_set_procmon_ref_values(dev_priv, phy);
-		if (port == PORT_A) {
+		if (phy == PHY_A) {
-			val = I915_READ(ICL_PORT_COMP_DW8(port));
+			val = I915_READ(ICL_PORT_COMP_DW8(phy));
 			val |= IREFGEN;
-			I915_WRITE(ICL_PORT_COMP_DW8(port), val);
+			I915_WRITE(ICL_PORT_COMP_DW8(phy), val);
 		}
-		val = I915_READ(ICL_PORT_COMP_DW0(port));
+		val = I915_READ(ICL_PORT_COMP_DW0(phy));
 		val |= COMP_INIT;
-		I915_WRITE(ICL_PORT_COMP_DW0(port), val);
+		I915_WRITE(ICL_PORT_COMP_DW0(phy), val);
-		val = I915_READ(ICL_PORT_CL_DW5(port));
+		val = I915_READ(ICL_PORT_CL_DW5(phy));
 		val |= CL_POWER_DOWN_ENABLE;
-		I915_WRITE(ICL_PORT_CL_DW5(port), val);
+		I915_WRITE(ICL_PORT_CL_DW5(phy), val);
 	}
 }
 static void icl_combo_phys_uninit(struct drm_i915_private *dev_priv)
 {
-	enum port port;
+	enum phy phy;
-	for_each_combo_port_reverse(dev_priv, port) {
+	for_each_combo_phy_reverse(dev_priv, phy) {
 		u32 val;
-		if (port == PORT_A &&
+		if (phy == PHY_A &&
-		    !icl_combo_phy_verify_state(dev_priv, port))
+		    !icl_combo_phy_verify_state(dev_priv, phy))
-			DRM_WARN("Port %c combo PHY HW state changed unexpectedly\n",
+			DRM_WARN("Combo PHY %c HW state changed unexpectedly\n",
-				 port_name(port));
+				 phy_name(phy));
+		/*
+		 * Although EHL adds a combo PHY C, there's no PHY_MISC
+		 * register for it and no need to program the
+		 * DE_IO_COMP_PWR_DOWN setting on PHY C.
+		 */
+		if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C)
+			goto skip_phy_misc;
-		val = I915_READ(ICL_PHY_MISC(port));
+		val = I915_READ(ICL_PHY_MISC(phy));
 		val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
-		I915_WRITE(ICL_PHY_MISC(port), val);
+		I915_WRITE(ICL_PHY_MISC(phy), val);
-		val = I915_READ(ICL_PORT_COMP_DW0(port));
+skip_phy_misc:
+		val = I915_READ(ICL_PORT_COMP_DW0(phy));
 		val &= ~COMP_INIT;
-		I915_WRITE(ICL_PORT_COMP_DW0(port), val);
+		I915_WRITE(ICL_PORT_COMP_DW0(phy), val);
 	}
 }

drivers/gpu/drm/i915/display/intel_combo_phy.h+2−2

 #define __INTEL_COMBO_PHY_H__
 #include <linux/types.h>
-#include <drm/i915_drm.h>
 struct drm_i915_private;
+enum phy;
 void intel_combo_phy_init(struct drm_i915_private *dev_priv);
 void intel_combo_phy_uninit(struct drm_i915_private *dev_priv);
 void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv,
-				    enum port port, bool is_dsi,
+				    enum phy phy, bool is_dsi,
 				    int lane_count, bool lane_reversal);
 #endif /* __INTEL_COMBO_PHY_H__ */

drivers/gpu/drm/i915/display/intel_connector.c+1−1

@@ -118,7 +118,7 @@ int intel_connector_register(struct drm_connector *connector) · 117 unmodified lines
118	if (ret)	118	if (ret)
119	goto err;	119	goto err;
120		120
121	if (i915_inject_load_failure()) {	121	if (i915_inject_probe_failure()) {
122	ret = -EFAULT;	122	ret = -EFAULT;
123	goto err_backlight;	123	goto err_backlight;
124	}	124	}

drivers/gpu/drm/i915/display/intel_ddi.c+229−174

@@ -45,6 +45,7 @@ · 44 unmodified lines
45	#include "intel_lspcon.h"	45	#include "intel_lspcon.h"
46	#include "intel_panel.h"	46	#include "intel_panel.h"
47	#include "intel_psr.h"	47	#include "intel_psr.h"
		48	#include "intel_tc.h"
48	#include "intel_vdsc.h"	49	#include "intel_vdsc.h"
49		50
50	struct ddi_buf_trans {	51	struct ddi_buf_trans {
@@ -846,8 +847,8 @@ cnl_get_buf_trans_edp(struct drm_i915_private dev_priv, int n_entries) · 795 unmodified lines
846	}	847	}
847		848
848	static const struct cnl_ddi_buf_trans *	849	static const struct cnl_ddi_buf_trans *
849	icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,	850	icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
850	int type, int rate, int *n_entries)	851	int *n_entries)
851	{	852	{
852	if (type == INTEL_OUTPUT_HDMI) {	853	if (type == INTEL_OUTPUT_HDMI) {
853	*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);	854	*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
@@ -867,12 +868,13 @@ icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port, · 13 unmodified lines
867	static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)	868	static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
868	{	869	{
869	int n_entries, level, default_entry;	870	int n_entries, level, default_entry;
		871	enum phy phy = intel_port_to_phy(dev_priv, port);
870		872
871	level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;	873	level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
872		874
873	if (INTEL_GEN(dev_priv) >= 11) {	875	if (INTEL_GEN(dev_priv) >= 11) {
874	if (intel_port_is_combophy(dev_priv, port))	876	if (intel_phy_is_combo(dev_priv, phy))
875	icl_get_combo_buf_trans(dev_priv, port, INTEL_OUTPUT_HDMI,	877	icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
876	0, &n_entries);	878	0, &n_entries);
877	else	879	else
878	n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);	880	n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
@@ -1486,9 +1488,10 @@ static void icl_ddi_clock_get(struct intel_encoder *encoder, · 607 unmodified lines
1486	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);	1488	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1487	struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;	1489	struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
1488	enum port port = encoder->port;	1490	enum port port = encoder->port;
		1491	enum phy phy = intel_port_to_phy(dev_priv, port);
1489	int link_clock;	1492	int link_clock;
1490		1493
1491	if (intel_port_is_combophy(dev_priv, port)) {	1494	if (intel_phy_is_combo(dev_priv, phy)) {
1492	link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);	1495	link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
1493	} else {	1496	} else {
1494	enum intel_dpll_id pll_id = intel_get_shared_dpll_id(dev_priv,	1497	enum intel_dpll_id pll_id = intel_get_shared_dpll_id(dev_priv,
@@ -1770,7 +1773,10 @@ void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state) · 275 unmodified lines
1770		1773
1771	/* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */	1774	/* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1772	temp = TRANS_DDI_FUNC_ENABLE;	1775	temp = TRANS_DDI_FUNC_ENABLE;
1773	temp \|= TRANS_DDI_SELECT_PORT(port);	1776	if (INTEL_GEN(dev_priv) >= 12)
		1777	temp \|= TGL_TRANS_DDI_SELECT_PORT(port);
		1778	else
		1779	temp \|= TRANS_DDI_SELECT_PORT(port);
1774		1780
1775	switch (crtc_state->pipe_bpp) {	1781	switch (crtc_state->pipe_bpp) {
1776	case 18:	1782	case 18:
@@ -1850,8 +1856,13 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state · 73 unmodified lines
1850	i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);	1856	i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1851	u32 val = I915_READ(reg);	1857	u32 val = I915_READ(reg);
1852		1858
1853	val &= ~(TRANS_DDI_FUNC_ENABLE \| TRANS_DDI_PORT_MASK \| TRANS_DDI_DP_VC_PAYLOAD_ALLOC);	1859	if (INTEL_GEN(dev_priv) >= 12) {
1854	val \|= TRANS_DDI_PORT_NONE;	1860	val &= ~(TRANS_DDI_FUNC_ENABLE \| TGL_TRANS_DDI_PORT_MASK \|
		1861	TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
		1862	} else {
		1863	val &= ~(TRANS_DDI_FUNC_ENABLE \| TRANS_DDI_PORT_MASK \|
		1864	TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
		1865	}
1855	I915_WRITE(reg, val);	1866	I915_WRITE(reg, val);
1856		1867
1857	if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&	1868	if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
@@ -2003,10 +2014,19 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, · 145 unmodified lines
2003	mst_pipe_mask = 0;	2014	mst_pipe_mask = 0;
2004	for_each_pipe(dev_priv, p) {	2015	for_each_pipe(dev_priv, p) {
2005	enum transcoder cpu_transcoder = (enum transcoder)p;	2016	enum transcoder cpu_transcoder = (enum transcoder)p;
		2017	unsigned int port_mask, ddi_select;
		2018
		2019	if (INTEL_GEN(dev_priv) >= 12) {
		2020	port_mask = TGL_TRANS_DDI_PORT_MASK;
		2021	ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
		2022	} else {
		2023	port_mask = TRANS_DDI_PORT_MASK;
		2024	ddi_select = TRANS_DDI_SELECT_PORT(port);
		2025	}
2006		2026
2007	tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));	2027	tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2008		2028
2009	if ((tmp & TRANS_DDI_PORT_MASK) != TRANS_DDI_SELECT_PORT(port))	2029	if ((tmp & port_mask) != ddi_select)
2010	continue;	2030	continue;
2011		2031
2012	if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==	2032	if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
@@ -2085,6 +2105,7 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder, · 72 unmodified lines
2085	{	2105	{
2086	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);	2106	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2087	struct intel_digital_port *dig_port;	2107	struct intel_digital_port *dig_port;
		2108	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2088		2109
2089	/*	2110	/*
2090	* TODO: Add support for MST encoders. Atm, the following should never	2111	* TODO: Add support for MST encoders. Atm, the following should never
@@ -2102,7 +2123,7 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder, · 11 unmodified lines
2102	* ports.	2123	* ports.
2103	*/	2124	*/
2104	if (intel_crtc_has_dp_encoder(crtc_state) \|\|	2125	if (intel_crtc_has_dp_encoder(crtc_state) \|\|
2105	intel_port_is_tc(dev_priv, encoder->port))	2126	intel_phy_is_tc(dev_priv, phy))
2106	intel_display_power_get(dev_priv,	2127	intel_display_power_get(dev_priv,
2107	intel_ddi_main_link_aux_domain(dig_port));	2128	intel_ddi_main_link_aux_domain(dig_port));
2108		2129
@@ -2122,9 +2143,14 @@ void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state) · 13 unmodified lines
2122	enum port port = encoder->port;	2143	enum port port = encoder->port;
2123	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;	2144	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2124		2145
2125	if (cpu_transcoder != TRANSCODER_EDP)	2146	if (cpu_transcoder != TRANSCODER_EDP) {
2126	I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),	2147	if (INTEL_GEN(dev_priv) >= 12)
2127	TRANS_CLK_SEL_PORT(port));	2148	I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
		2149	TGL_TRANS_CLK_SEL_PORT(port));
		2150	else
		2151	I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
		2152	TRANS_CLK_SEL_PORT(port));
		2153	}
2128	}	2154	}
2129		2155
2130	void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)	2156	void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
@@ -2132,9 +2158,14 @@ void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state) · 1 unmodified line
2132	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);	2158	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2133	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;	2159	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2134		2160
2135	if (cpu_transcoder != TRANSCODER_EDP)	2161	if (cpu_transcoder != TRANSCODER_EDP) {
2136	I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),	2162	if (INTEL_GEN(dev_priv) >= 12)
2137	TRANS_CLK_SEL_DISABLED);	2163	I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
		2164	TGL_TRANS_CLK_SEL_DISABLED);
		2165	else
		2166	I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
		2167	TRANS_CLK_SEL_DISABLED);
		2168	}
2138	}	2169	}
2139		2170
2140	static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,	2171	static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
@@ -2227,11 +2258,12 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder) · 86 unmodified lines
2227	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);	2258	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2228	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);	2259	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2229	enum port port = encoder->port;	2260	enum port port = encoder->port;
		2261	enum phy phy = intel_port_to_phy(dev_priv, port);
2230	int n_entries;	2262	int n_entries;
2231		2263
2232	if (INTEL_GEN(dev_priv) >= 11) {	2264	if (INTEL_GEN(dev_priv) >= 11) {
2233	if (intel_port_is_combophy(dev_priv, port))	2265	if (intel_phy_is_combo(dev_priv, phy))
2234	icl_get_combo_buf_trans(dev_priv, port, encoder->type,	2266	icl_get_combo_buf_trans(dev_priv, encoder->type,
2235	intel_dp->link_rate, &n_entries);	2267	intel_dp->link_rate, &n_entries);
2236	else	2268	else
2237	n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);	2269	n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
@@ -2413,15 +2445,15 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, · 175 unmodified lines
2413	}	2445	}
2414		2446
2415	static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,	2447	static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
2416	u32 level, enum port port, int type,	2448	u32 level, enum phy phy, int type,
2417	int rate)	2449	int rate)
2418	{	2450	{
2419	const struct cnl_ddi_buf_trans *ddi_translations = NULL;	2451	const struct cnl_ddi_buf_trans *ddi_translations = NULL;
2420	u32 n_entries, val;	2452	u32 n_entries, val;
2421	int ln;	2453	int ln;
2422		2454
2423	ddi_translations = icl_get_combo_buf_trans(dev_priv, port, type,	2455	ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate,
2424	rate, &n_entries);	2456	&n_entries);
2425	if (!ddi_translations)	2457	if (!ddi_translations)
2426	return;	2458	return;
2427		2459
@@ -2431,41 +2463,41 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, · 3 unmodified lines
2431	}	2463	}
2432		2464
2433	/* Set PORT_TX_DW5 */	2465	/* Set PORT_TX_DW5 */
2434	val = I915_READ(ICL_PORT_TX_DW5_LN0(port));	2466	val = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
2435	val &= ~(SCALING_MODE_SEL_MASK \| RTERM_SELECT_MASK \|	2467	val &= ~(SCALING_MODE_SEL_MASK \| RTERM_SELECT_MASK \|
2436	TAP2_DISABLE \| TAP3_DISABLE);	2468	TAP2_DISABLE \| TAP3_DISABLE);
2437	val \|= SCALING_MODE_SEL(0x2);	2469	val \|= SCALING_MODE_SEL(0x2);
2438	val \|= RTERM_SELECT(0x6);	2470	val \|= RTERM_SELECT(0x6);
2439	val \|= TAP3_DISABLE;	2471	val \|= TAP3_DISABLE;
2440	I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);	2472	I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val);
2441		2473
2442	/* Program PORT_TX_DW2 */	2474	/* Program PORT_TX_DW2 */
2443	val = I915_READ(ICL_PORT_TX_DW2_LN0(port));	2475	val = I915_READ(ICL_PORT_TX_DW2_LN0(phy));
2444	val &= ~(SWING_SEL_LOWER_MASK \| SWING_SEL_UPPER_MASK \|	2476	val &= ~(SWING_SEL_LOWER_MASK \| SWING_SEL_UPPER_MASK \|
2445	RCOMP_SCALAR_MASK);	2477	RCOMP_SCALAR_MASK);
2446	val \|= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);	2478	val \|= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2447	val \|= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);	2479	val \|= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2448	/* Program Rcomp scalar for every table entry */	2480	/* Program Rcomp scalar for every table entry */
2449	val \|= RCOMP_SCALAR(0x98);	2481	val \|= RCOMP_SCALAR(0x98);
2450	I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);	2482	I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), val);
2451		2483
2452	/* Program PORT_TX_DW4 */	2484	/* Program PORT_TX_DW4 */
2453	/* We cannot write to GRP. It would overwrite individual loadgen. */	2485	/* We cannot write to GRP. It would overwrite individual loadgen. */
2454	for (ln = 0; ln <= 3; ln++) {	2486	for (ln = 0; ln <= 3; ln++) {
2455	val = I915_READ(ICL_PORT_TX_DW4_LN(ln, port));	2487	val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy));
2456	val &= ~(POST_CURSOR_1_MASK \| POST_CURSOR_2_MASK \|	2488	val &= ~(POST_CURSOR_1_MASK \| POST_CURSOR_2_MASK \|
2457	CURSOR_COEFF_MASK);	2489	CURSOR_COEFF_MASK);
2458	val \|= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);	2490	val \|= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2459	val \|= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);	2491	val \|= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2460	val \|= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);	2492	val \|= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2461	I915_WRITE(ICL_PORT_TX_DW4_LN(ln, port), val);	2493	I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val);
2462	}	2494	}
2463		2495
2464	/* Program PORT_TX_DW7 */	2496	/* Program PORT_TX_DW7 */
2465	val = I915_READ(ICL_PORT_TX_DW7_LN0(port));	2497	val = I915_READ(ICL_PORT_TX_DW7_LN0(phy));
2466	val &= ~N_SCALAR_MASK;	2498	val &= ~N_SCALAR_MASK;
2467	val \|= N_SCALAR(ddi_translations[level].dw7_n_scalar);	2499	val \|= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2468	I915_WRITE(ICL_PORT_TX_DW7_GRP(port), val);	2500	I915_WRITE(ICL_PORT_TX_DW7_GRP(phy), val);
2469	}	2501	}
2470		2502
2471	static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,	2503	static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
@@ -2473,7 +2505,7 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, · 1 unmodified line
2473	enum intel_output_type type)	2505	enum intel_output_type type)
2474	{	2506	{
2475	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);	2507	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2476	enum port port = encoder->port;	2508	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2477	int width = 0;	2509	int width = 0;
2478	int rate = 0;	2510	int rate = 0;
2479	u32 val;	2511	u32 val;
@@ -2494,12 +2526,12 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, · 14 unmodified lines
2494	* set PORT_PCS_DW1 cmnkeeper_enable to 1b,	2526	* set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2495	* else clear to 0b.	2527	* else clear to 0b.
2496	*/	2528	*/
2497	val = I915_READ(ICL_PORT_PCS_DW1_LN0(port));	2529	val = I915_READ(ICL_PORT_PCS_DW1_LN0(phy));
2498	if (type == INTEL_OUTPUT_HDMI)	2530	if (type == INTEL_OUTPUT_HDMI)
2499	val &= ~COMMON_KEEPER_EN;	2531	val &= ~COMMON_KEEPER_EN;
2500	else	2532	else
2501	val \|= COMMON_KEEPER_EN;	2533	val \|= COMMON_KEEPER_EN;
2502	I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), val);	2534	I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), val);
2503		2535
2504	/* 2. Program loadgen select */	2536	/* 2. Program loadgen select */
2505	/*	2537	/*
@@ -2509,33 +2541,33 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, · 3 unmodified lines
2509	* > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)	2541	* > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2510	*/	2542	*/
2511	for (ln = 0; ln <= 3; ln++) {	2543	for (ln = 0; ln <= 3; ln++) {
2512	val = I915_READ(ICL_PORT_TX_DW4_LN(ln, port));	2544	val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy));
2513	val &= ~LOADGEN_SELECT;	2545	val &= ~LOADGEN_SELECT;
2514		2546
2515	if ((rate <= 600000 && width == 4 && ln >= 1) \|\|	2547	if ((rate <= 600000 && width == 4 && ln >= 1) \|\|
2516	(rate <= 600000 && width < 4 && (ln == 1 \|\| ln == 2))) {	2548	(rate <= 600000 && width < 4 && (ln == 1 \|\| ln == 2))) {
2517	val \|= LOADGEN_SELECT;	2549	val \|= LOADGEN_SELECT;
2518	}	2550	}
2519	I915_WRITE(ICL_PORT_TX_DW4_LN(ln, port), val);	2551	I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val);
2520	}	2552	}
2521		2553
2522	/* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */	2554	/* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2523	val = I915_READ(ICL_PORT_CL_DW5(port));	2555	val = I915_READ(ICL_PORT_CL_DW5(phy));
2524	val \|= SUS_CLOCK_CONFIG;	2556	val \|= SUS_CLOCK_CONFIG;
2525	I915_WRITE(ICL_PORT_CL_DW5(port), val);	2557	I915_WRITE(ICL_PORT_CL_DW5(phy), val);
2526		2558
2527	/* 4. Clear training enable to change swing values */	2559	/* 4. Clear training enable to change swing values */
2528	val = I915_READ(ICL_PORT_TX_DW5_LN0(port));	2560	val = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
2529	val &= ~TX_TRAINING_EN;	2561	val &= ~TX_TRAINING_EN;
2530	I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);	2562	I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val);
2531		2563
2532	/* 5. Program swing and de-emphasis */	2564	/* 5. Program swing and de-emphasis */
2533	icl_ddi_combo_vswing_program(dev_priv, level, port, type, rate);	2565	icl_ddi_combo_vswing_program(dev_priv, level, phy, type, rate);
2534		2566
2535	/* 6. Set training enable to trigger update */	2567	/* 6. Set training enable to trigger update */
2536	val = I915_READ(ICL_PORT_TX_DW5_LN0(port));	2568	val = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
2537	val \|= TX_TRAINING_EN;	2569	val \|= TX_TRAINING_EN;
2538	I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);	2570	I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val);
2539	}	2571	}
2540		2572
2541	static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,	2573	static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
@@ -2663,9 +2695,9 @@ static void icl_ddi_vswing_sequence(struct intel_encoder *encoder, · 121 unmodified lines
2663	enum intel_output_type type)	2695	enum intel_output_type type)
2664	{	2696	{
2665	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);	2697	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2666	enum port port = encoder->port;	2698	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2667		2699
2668	if (intel_port_is_combophy(dev_priv, port))	2700	if (intel_phy_is_combo(dev_priv, phy))
2669	icl_combo_phy_ddi_vswing_sequence(encoder, level, type);	2701	icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2670	else	2702	else
2671	icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);	2703	icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
@@ -2728,12 +2760,13 @@ u32 ddi_signal_levels(struct intel_dp *intel_dp) · 56 unmodified lines
2728		2760
2729	static inline	2761	static inline
2730	u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,	2762	u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
2731	enum port port)	2763	enum phy phy)
2732	{	2764	{
2733	if (intel_port_is_combophy(dev_priv, port)) {	2765	if (intel_phy_is_combo(dev_priv, phy)) {
2734	return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);	2766	return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
2735	} else if (intel_port_is_tc(dev_priv, port)) {	2767	} else if (intel_phy_is_tc(dev_priv, phy)) {
2736	enum tc_port tc_port = intel_port_to_tc(dev_priv, port);	2768	enum tc_port tc_port = intel_port_to_tc(dev_priv,
		2769	(enum port)phy);
2737		2770
2738	return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);	2771	return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
2739	}	2772	}
@@ -2746,23 +2779,33 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder, · 6 unmodified lines
2746	{	2779	{
2747	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);	2780	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2748	struct intel_shared_dpll *pll = crtc_state->shared_dpll;	2781	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2749	enum port port = encoder->port;	2782	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2750	u32 val;	2783	u32 val;
2751		2784
2752	mutex_lock(&dev_priv->dpll_lock);	2785	mutex_lock(&dev_priv->dpll_lock);
2753		2786
2754	val = I915_READ(DPCLKA_CFGCR0_ICL);	2787	val = I915_READ(ICL_DPCLKA_CFGCR0);
2755	WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0);	2788	WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
2756		2789
2757	if (intel_port_is_combophy(dev_priv, port)) {	2790	if (intel_phy_is_combo(dev_priv, phy)) {
2758	val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);	2791	/*
2759	val \|= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);	2792	* Even though this register references DDIs, note that we
2760	I915_WRITE(DPCLKA_CFGCR0_ICL, val);	2793	* want to pass the PHY rather than the port (DDI). For
2761	POSTING_READ(DPCLKA_CFGCR0_ICL);	2794	* ICL, port=phy in all cases so it doesn't matter, but for
		2795	* EHL the bspec notes the following:
		2796	*
		2797	* "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA
		2798	* Clock Select chooses the PLL for both DDIA and DDID and
		2799	* drives port A in all cases."
		2800	*/
		2801	val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
		2802	val \|= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
		2803	I915_WRITE(ICL_DPCLKA_CFGCR0, val);
		2804	POSTING_READ(ICL_DPCLKA_CFGCR0);
2762	}	2805	}
2763		2806
2764	val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);	2807	val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2765	I915_WRITE(DPCLKA_CFGCR0_ICL, val);	2808	I915_WRITE(ICL_DPCLKA_CFGCR0, val);
2766		2809
2767	mutex_unlock(&dev_priv->dpll_lock);	2810	mutex_unlock(&dev_priv->dpll_lock);
2768	}	2811	}
@@ -2770,14 +2813,14 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder, · 1 unmodified line
2770	static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)	2813	static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
2771	{	2814	{
2772	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);	2815	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2773	enum port port = encoder->port;	2816	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2774	u32 val;	2817	u32 val;
2775		2818
2776	mutex_lock(&dev_priv->dpll_lock);	2819	mutex_lock(&dev_priv->dpll_lock);
2777		2820
2778	val = I915_READ(DPCLKA_CFGCR0_ICL);	2821	val = I915_READ(ICL_DPCLKA_CFGCR0);
2779	val \|= icl_dpclka_cfgcr0_clk_off(dev_priv, port);	2822	val \|= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2780	I915_WRITE(DPCLKA_CFGCR0_ICL, val);	2823	I915_WRITE(ICL_DPCLKA_CFGCR0, val);
2781		2824
2782	mutex_unlock(&dev_priv->dpll_lock);	2825	mutex_unlock(&dev_priv->dpll_lock);
2783	}	2826	}
@@ -2835,11 +2878,13 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) · 51 unmodified lines
2835	ddi_clk_needed = false;	2878	ddi_clk_needed = false;
2836	}	2879	}
2837		2880
2838	val = I915_READ(DPCLKA_CFGCR0_ICL);	2881	val = I915_READ(ICL_DPCLKA_CFGCR0);
2839	for_each_port_masked(port, port_mask) {	2882	for_each_port_masked(port, port_mask) {
		2883	enum phy phy = intel_port_to_phy(dev_priv, port);
		2884
2840	bool ddi_clk_ungated = !(val &	2885	bool ddi_clk_ungated = !(val &
2841	icl_dpclka_cfgcr0_clk_off(dev_priv,	2886	icl_dpclka_cfgcr0_clk_off(dev_priv,
2842	port));	2887	phy));
2843		2888
2844	if (ddi_clk_needed == ddi_clk_ungated)	2889	if (ddi_clk_needed == ddi_clk_ungated)
2845	continue;	2890	continue;
@@ -2851,10 +2896,10 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) · 5 unmodified lines
2851	if (WARN_ON(ddi_clk_needed))	2896	if (WARN_ON(ddi_clk_needed))
2852	continue;	2897	continue;
2853		2898
2854	DRM_NOTE("Port %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",	2899	DRM_NOTE("PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
2855	port_name(port));	2900	phy_name(port));
2856	val \|= icl_dpclka_cfgcr0_clk_off(dev_priv, port);	2901	val \|= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2857	I915_WRITE(DPCLKA_CFGCR0_ICL, val);	2902	I915_WRITE(ICL_DPCLKA_CFGCR0, val);
2858	}	2903	}
2859	}	2904	}
2860		2905
@@ -2863,6 +2908,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder, · 2 unmodified lines
2863	{	2908	{
2864	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);	2909	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2865	enum port port = encoder->port;	2910	enum port port = encoder->port;
		2911	enum phy phy = intel_port_to_phy(dev_priv, port);
2866	u32 val;	2912	u32 val;
2867	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;	2913	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2868		2914
@@ -2872,7 +2918,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder, · 3 unmodified lines
2872	mutex_lock(&dev_priv->dpll_lock);	2918	mutex_lock(&dev_priv->dpll_lock);
2873		2919
2874	if (INTEL_GEN(dev_priv) >= 11) {	2920	if (INTEL_GEN(dev_priv) >= 11) {
2875	if (!intel_port_is_combophy(dev_priv, port))	2921	if (!intel_phy_is_combo(dev_priv, phy))
2876	I915_WRITE(DDI_CLK_SEL(port),	2922	I915_WRITE(DDI_CLK_SEL(port),
2877	icl_pll_to_ddi_clk_sel(encoder, crtc_state));	2923	icl_pll_to_ddi_clk_sel(encoder, crtc_state));
2878	} else if (IS_CANNONLAKE(dev_priv)) {	2924	} else if (IS_CANNONLAKE(dev_priv)) {
@@ -2912,9 +2958,10 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder) · 33 unmodified lines
2912	{	2958	{
2913	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);	2959	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2914	enum port port = encoder->port;	2960	enum port port = encoder->port;
		2961	enum phy phy = intel_port_to_phy(dev_priv, port);
2915		2962
2916	if (INTEL_GEN(dev_priv) >= 11) {	2963	if (INTEL_GEN(dev_priv) >= 11) {
2917	if (!intel_port_is_combophy(dev_priv, port))	2964	if (!intel_phy_is_combo(dev_priv, phy))
2918	I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);	2965	I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
2919	} else if (IS_CANNONLAKE(dev_priv)) {	2966	} else if (IS_CANNONLAKE(dev_priv)) {
2920	I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) \|	2967	I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) \|
@@ -2995,25 +3042,22 @@ static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port) · 74 unmodified lines
2995	{	3042	{
2996	struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);	3043	struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
2997	enum port port = intel_dig_port->base.port;	3044	enum port port = intel_dig_port->base.port;
2998	enum tc_port tc_port = intel_port_to_tc(dev_priv, port);	3045	u32 ln0, ln1, lane_mask;
2999	u32 ln0, ln1, lane_info;
3000		3046
3001	if (tc_port == PORT_TC_NONE \|\| intel_dig_port->tc_type == TC_PORT_TBT)	3047	if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
3002	return;	3048	return;
3003		3049
3004	ln0 = I915_READ(MG_DP_MODE(0, port));	3050	ln0 = I915_READ(MG_DP_MODE(0, port));
3005	ln1 = I915_READ(MG_DP_MODE(1, port));	3051	ln1 = I915_READ(MG_DP_MODE(1, port));
3006		3052
3007	switch (intel_dig_port->tc_type) {	3053	switch (intel_dig_port->tc_mode) {
3008	case TC_PORT_TYPEC:	3054	case TC_PORT_DP_ALT:
3009	ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE \| MG_DP_MODE_CFG_DP_X2_MODE);	3055	ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE \| MG_DP_MODE_CFG_DP_X2_MODE);
3010	ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE \| MG_DP_MODE_CFG_DP_X2_MODE);	3056	ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE \| MG_DP_MODE_CFG_DP_X2_MODE);
3011		3057
3012	lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &	3058	lane_mask = intel_tc_port_get_lane_mask(intel_dig_port);
3013	DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
3014	DP_LANE_ASSIGNMENT_SHIFT(tc_port);
3015		3059
3016	switch (lane_info) {	3060	switch (lane_mask) {
3017	case 0x1:	3061	case 0x1:
3018	case 0x4:	3062	case 0x4:
3019	break;	3063	break;
@@ -3038,7 +3082,7 @@ static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port) · 18 unmodified lines
3038	MG_DP_MODE_CFG_DP_X2_MODE;	3082	MG_DP_MODE_CFG_DP_X2_MODE;
3039	break;	3083	break;
3040	default:	3084	default:
3041	MISSING_CASE(lane_info);	3085	MISSING_CASE(lane_mask);
3042	}	3086	}
3043	break;	3087	break;
3044		3088
@@ -3048,7 +3092,7 @@ static void icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port) · 3 unmodified lines
3048	break;	3092	break;
3049		3093
3050	default:	3094	default:
3051	MISSING_CASE(intel_dig_port->tc_type);	3095	MISSING_CASE(intel_dig_port->tc_mode);
3052	return;	3096	return;
3053	}	3097	}
3054		3098
@@ -3110,6 +3154,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, · 55 unmodified lines
3110	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);	3154	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3111	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);	3155	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3112	enum port port = encoder->port;	3156	enum port port = encoder->port;
		3157	enum phy phy = intel_port_to_phy(dev_priv, port);
3113	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);	3158	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3114	bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);	3159	bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
3115	int level = intel_ddi_dp_level(intel_dp);	3160	int level = intel_ddi_dp_level(intel_dp);
@@ -3123,7 +3168,10 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, · 7 unmodified lines
3123		3168
3124	intel_ddi_clk_select(encoder, crtc_state);	3169	intel_ddi_clk_select(encoder, crtc_state);
3125		3170
3126	intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);	3171	if (!intel_phy_is_tc(dev_priv, phy) \|\|
		3172	dig_port->tc_mode != TC_PORT_TBT_ALT)
		3173	intel_display_power_get(dev_priv,
		3174	dig_port->ddi_io_power_domain);
3127		3175
3128	icl_program_mg_dp_mode(dig_port);	3176	icl_program_mg_dp_mode(dig_port);
3129	icl_disable_phy_clock_gating(dig_port);	3177	icl_disable_phy_clock_gating(dig_port);
@@ -3138,11 +3186,11 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, · 8 unmodified lines
3138	else	3186	else
3139	intel_prepare_dp_ddi_buffers(encoder, crtc_state);	3187	intel_prepare_dp_ddi_buffers(encoder, crtc_state);
3140		3188
3141	if (intel_port_is_combophy(dev_priv, port)) {	3189	if (intel_phy_is_combo(dev_priv, phy)) {
3142	bool lane_reversal =	3190	bool lane_reversal =
3143	dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;	3191	dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3144		3192
3145	intel_combo_phy_power_up_lanes(dev_priv, port, false,	3193	intel_combo_phy_power_up_lanes(dev_priv, phy, false,
3146	crtc_state->lane_count,	3194	crtc_state->lane_count,
3147	lane_reversal);	3195	lane_reversal);
3148	}	3196	}
@@ -3290,6 +3338,7 @@ static void intel_ddi_post_disable_dp(struct intel_encoder *encoder, · 141 unmodified lines
3290	struct intel_dp *intel_dp = &dig_port->dp;	3338	struct intel_dp *intel_dp = &dig_port->dp;
3291	bool is_mst = intel_crtc_has_type(old_crtc_state,	3339	bool is_mst = intel_crtc_has_type(old_crtc_state,
3292	INTEL_OUTPUT_DP_MST);	3340	INTEL_OUTPUT_DP_MST);
		3341	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3293		3342
3294	if (!is_mst) {	3343	if (!is_mst) {
3295	intel_ddi_disable_pipe_clock(old_crtc_state);	3344	intel_ddi_disable_pipe_clock(old_crtc_state);
@@ -3305,8 +3354,10 @@ static void intel_ddi_post_disable_dp(struct intel_encoder *encoder, · 9 unmodified lines
3305	intel_edp_panel_vdd_on(intel_dp);	3354	intel_edp_panel_vdd_on(intel_dp);
3306	intel_edp_panel_off(intel_dp);	3355	intel_edp_panel_off(intel_dp);
3307		3356
3308	intel_display_power_put_unchecked(dev_priv,	3357	if (!intel_phy_is_tc(dev_priv, phy) \|\|
3309	dig_port->ddi_io_power_domain);	3358	dig_port->tc_mode != TC_PORT_TBT_ALT)
		3359	intel_display_power_put_unchecked(dev_priv,
		3360	dig_port->ddi_io_power_domain);
3310		3361
3311	intel_ddi_clk_disable(encoder);	3362	intel_ddi_clk_disable(encoder);
3312	}	3363	}
@@ -3591,33 +3642,28 @@ static void intel_ddi_update_pipe(struct intel_encoder *encoder, · 278 unmodified lines
3591	intel_hdcp_disable(to_intel_connector(conn_state->connector));	3642	intel_hdcp_disable(to_intel_connector(conn_state->connector));
3592	}	3643	}
3593		3644
3594	static void intel_ddi_set_fia_lane_count(struct intel_encoder *encoder,	3645	static void
3595	const struct intel_crtc_state *pipe_config,	3646	intel_ddi_update_prepare(struct intel_atomic_state *state,
3596	enum port port)	3647	struct intel_encoder *encoder,
		3648	struct intel_crtc *crtc)
3597	{	3649	{
3598	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);	3650	struct intel_crtc_state *crtc_state =
3599	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);	3651	crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL;
3600	enum tc_port tc_port = intel_port_to_tc(dev_priv, port);	3652	int required_lanes = crtc_state ? crtc_state->lane_count : 1;
3601	u32 val = I915_READ(PORT_TX_DFLEXDPMLE1);	3653
3602	bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;	3654	WARN_ON(crtc && crtc->active);
3603		3655
3604	val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);	3656	intel_tc_port_get_link(enc_to_dig_port(&encoder->base), required_lanes);
3605	switch (pipe_config->lane_count) {	3657	if (crtc_state && crtc_state->base.active)
3606	case 1:	3658	intel_update_active_dpll(state, crtc, encoder);
3607	val \|= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3(tc_port) :	3659	}
3608	DFLEXDPMLE1_DPMLETC_ML0(tc_port);	3660
3609	break;	3661	static void
3610	case 2:	3662	intel_ddi_update_complete(struct intel_atomic_state *state,
3611	val \|= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) :	3663	struct intel_encoder *encoder,
3612	DFLEXDPMLE1_DPMLETC_ML1_0(tc_port);	3664	struct intel_crtc *crtc)
3613	break;	3665	{
3614	case 4:	3666	intel_tc_port_put_link(enc_to_dig_port(&encoder->base));
3615	val \|= DFLEXDPMLE1_DPMLETC_ML3_0(tc_port);
3616	break;
3617	default:
3618	MISSING_CASE(pipe_config->lane_count);
3619	}
3620	I915_WRITE(PORT_TX_DFLEXDPMLE1, val);
3621	}	3667	}
3622		3668
3623	static void	3669	static void
@@ -3627,26 +3673,25 @@ intel_ddi_pre_pll_enable(struct intel_encoder *encoder, · 3 unmodified lines
3627	{	3673	{
3628	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);	3674	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3629	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);	3675	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3630	enum port port = encoder->port;	3676	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
		3677	bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
3631		3678
3632	if (intel_crtc_has_dp_encoder(crtc_state) \|\|	3679	if (is_tc_port)
3633	intel_port_is_tc(dev_priv, encoder->port))	3680	intel_tc_port_get_link(dig_port, crtc_state->lane_count);
		3681
		3682	if (intel_crtc_has_dp_encoder(crtc_state) \|\| is_tc_port)
3634	intel_display_power_get(dev_priv,	3683	intel_display_power_get(dev_priv,
3635	intel_ddi_main_link_aux_domain(dig_port));	3684	intel_ddi_main_link_aux_domain(dig_port));
3636		3685
3637	if (IS_GEN9_LP(dev_priv))	3686	if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT)
		3687	/*
		3688	* Program the lane count for static/dynamic connections on
		3689	* Type-C ports. Skip this step for TBT.
		3690	*/
		3691	intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count);
		3692	else if (IS_GEN9_LP(dev_priv))
3638	bxt_ddi_phy_set_lane_optim_mask(encoder,	3693	bxt_ddi_phy_set_lane_optim_mask(encoder,
3639	crtc_state->lane_lat_optim_mask);	3694	crtc_state->lane_lat_optim_mask);
3640
3641	/*
3642	* Program the lane count for static/dynamic connections on Type-C ports.
3643	* Skip this step for TBT.
3644	*/
3645	if (dig_port->tc_type == TC_PORT_UNKNOWN \|\|
3646	dig_port->tc_type == TC_PORT_TBT)
3647	return;
3648
3649	intel_ddi_set_fia_lane_count(encoder, crtc_state, port);
3650	}	3695	}
3651		3696
3652	static void	3697	static void
@@ -3656,11 +3701,15 @@ intel_ddi_post_pll_disable(struct intel_encoder *encoder, · 3 unmodified lines
3656	{	3701	{
3657	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);	3702	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3658	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);	3703	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
		3704	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
		3705	bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
3659		3706
3660	if (intel_crtc_has_dp_encoder(crtc_state) \|\|	3707	if (intel_crtc_has_dp_encoder(crtc_state) \|\| is_tc_port)
3661	intel_port_is_tc(dev_priv, encoder->port))
3662	intel_display_power_put_unchecked(dev_priv,	3708	intel_display_power_put_unchecked(dev_priv,
3663	intel_ddi_main_link_aux_domain(dig_port));	3709	intel_ddi_main_link_aux_domain(dig_port));
		3710
		3711	if (is_tc_port)
		3712	intel_tc_port_put_link(dig_port);
3664	}	3713	}
3665		3714
3666	static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)	3715	static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
@@ -3737,7 +3786,6 @@ void intel_ddi_get_config(struct intel_encoder *encoder, · 70 unmodified lines
3737	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);	3786	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3738	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);	3787	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
3739	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;	3788	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3740	struct intel_digital_port *intel_dig_port;
3741	u32 temp, flags = 0;	3789	u32 temp, flags = 0;
3742		3790
3743	/* XXX: DSI transcoder paranoia */	3791	/* XXX: DSI transcoder paranoia */
@@ -3776,7 +3824,6 @@ void intel_ddi_get_config(struct intel_encoder *encoder, · 32 unmodified lines
3776	switch (temp & TRANS_DDI_MODE_SELECT_MASK) {	3824	switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3777	case TRANS_DDI_MODE_SELECT_HDMI:	3825	case TRANS_DDI_MODE_SELECT_HDMI:
3778	pipe_config->has_hdmi_sink = true;	3826	pipe_config->has_hdmi_sink = true;
3779	intel_dig_port = enc_to_dig_port(&encoder->base);
3780		3827
3781	pipe_config->infoframes.enable \|=	3828	pipe_config->infoframes.enable \|=
3782	intel_hdmi_infoframes_enabled(encoder, pipe_config);	3829	intel_hdmi_infoframes_enabled(encoder, pipe_config);
@@ -3914,49 +3961,18 @@ static int intel_ddi_compute_config(struct intel_encoder *encoder, · 131 unmodified lines
3914	return 0;	3961	return 0;
3915	}	3962	}
3916		3963
3917	static void intel_ddi_encoder_suspend(struct intel_encoder *encoder)
3918	{
3919	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
3920	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3921
3922	intel_dp_encoder_suspend(encoder);
3923
3924	/*
3925	* TODO: disconnect also from USB DP alternate mode once we have a
3926	* way to handle the modeset restore in that mode during resume
3927	* even if the sink has disappeared while being suspended.
3928	*/
3929	if (dig_port->tc_legacy_port)
3930	icl_tc_phy_disconnect(i915, dig_port);
3931	}
3932
3933	static void intel_ddi_encoder_reset(struct drm_encoder *drm_encoder)
3934	{
3935	struct intel_digital_port *dig_port = enc_to_dig_port(drm_encoder);
3936	struct drm_i915_private *i915 = to_i915(drm_encoder->dev);
3937
3938	if (intel_port_is_tc(i915, dig_port->base.port))
3939	intel_digital_port_connected(&dig_port->base);
3940
3941	intel_dp_encoder_reset(drm_encoder);
3942	}
3943
3944	static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)	3964	static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
3945	{	3965	{
3946	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);	3966	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3947	struct drm_i915_private *i915 = to_i915(encoder->dev);
3948		3967
3949	intel_dp_encoder_flush_work(encoder);	3968	intel_dp_encoder_flush_work(encoder);
3950		3969
3951	if (intel_port_is_tc(i915, dig_port->base.port))
3952	icl_tc_phy_disconnect(i915, dig_port);
3953
3954	drm_encoder_cleanup(encoder);	3970	drm_encoder_cleanup(encoder);
3955	kfree(dig_port);	3971	kfree(dig_port);
3956	}	3972	}
3957		3973
3958	static const struct drm_encoder_funcs intel_ddi_funcs = {	3974	static const struct drm_encoder_funcs intel_ddi_funcs = {
3959	.reset = intel_ddi_encoder_reset,	3975	.reset = intel_dp_encoder_reset,
3960	.destroy = intel_ddi_encoder_destroy,	3976	.destroy = intel_ddi_encoder_destroy,
3961	};	3977	};
3962		3978
@@ -4081,14 +4097,17 @@ static int intel_hdmi_reset_link(struct intel_encoder *encoder, · 118 unmodified lines
4081	return modeset_pipe(&crtc->base, ctx);	4097	return modeset_pipe(&crtc->base, ctx);
4082	}	4098	}
4083		4099
4084	static bool intel_ddi_hotplug(struct intel_encoder *encoder,	4100	static enum intel_hotplug_state
4085	struct intel_connector *connector)	4101	intel_ddi_hotplug(struct intel_encoder *encoder,
		4102	struct intel_connector *connector,
		4103	bool irq_received)
4086	{	4104	{
		4105	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
4087	struct drm_modeset_acquire_ctx ctx;	4106	struct drm_modeset_acquire_ctx ctx;
4088	bool changed;	4107	enum intel_hotplug_state state;
4089	int ret;	4108	int ret;
4090		4109
4091	changed = intel_encoder_hotplug(encoder, connector);	4110	state = intel_encoder_hotplug(encoder, connector, irq_received);
4092		4111
4093	drm_modeset_acquire_init(&ctx, 0);	4112	drm_modeset_acquire_init(&ctx, 0);
4094		4113
@@ -4110,7 +4129,27 @@ static bool intel_ddi_hotplug(struct intel_encoder *encoder, · 15 unmodified lines
4110	drm_modeset_acquire_fini(&ctx);	4129	drm_modeset_acquire_fini(&ctx);
4111	WARN(ret, "Acquiring modeset locks failed with %i\n", ret);	4130	WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4112		4131
4113	return changed;	4132	/*
		4133	* Unpowered type-c dongles can take some time to boot and be
		4134	* responsible, so here giving some time to those dongles to power up
		4135	* and then retrying the probe.
		4136	*
		4137	* On many platforms the HDMI live state signal is known to be
		4138	* unreliable, so we can't use it to detect if a sink is connected or
		4139	* not. Instead we detect if it's connected based on whether we can
		4140	* read the EDID or not. That in turn has a problem during disconnect,
		4141	* since the HPD interrupt may be raised before the DDC lines get
		4142	* disconnected (due to how the required length of DDC vs. HPD
		4143	* connector pins are specified) and so we'll still be able to get a
		4144	* valid EDID. To solve this schedule another detection cycle if this
		4145	* time around we didn't detect any change in the sink's connection
		4146	* status.
		4147	*/
		4148	if (state == INTEL_HOTPLUG_UNCHANGED && irq_received &&
		4149	!dig_port->dp.is_mst)
		4150	state = INTEL_HOTPLUG_RETRY;
		4151
		4152	return state;
4114	}	4153	}
4115		4154
4116	static struct intel_connector *	4155	static struct intel_connector *
@@ -4198,6 +4237,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) · 81 unmodified lines
4198	struct drm_encoder *encoder;	4237	struct drm_encoder *encoder;
4199	bool init_hdmi, init_dp, init_lspcon = false;	4238	bool init_hdmi, init_dp, init_lspcon = false;
4200	enum pipe pipe;	4239	enum pipe pipe;
		4240	enum phy phy = intel_port_to_phy(dev_priv, port);
4201		4241
4202	init_hdmi = port_info->supports_dvi \|\| port_info->supports_hdmi;	4242	init_hdmi = port_info->supports_dvi \|\| port_info->supports_hdmi;
4203	init_dp = port_info->supports_dp;	4243	init_dp = port_info->supports_dp;
@@ -4242,7 +4282,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) · 38 unmodified lines
4242	intel_encoder->update_pipe = intel_ddi_update_pipe;	4282	intel_encoder->update_pipe = intel_ddi_update_pipe;
4243	intel_encoder->get_hw_state = intel_ddi_get_hw_state;	4283	intel_encoder->get_hw_state = intel_ddi_get_hw_state;
4244	intel_encoder->get_config = intel_ddi_get_config;	4284	intel_encoder->get_config = intel_ddi_get_config;
4245	intel_encoder->suspend = intel_ddi_encoder_suspend;	4285	intel_encoder->suspend = intel_dp_encoder_suspend;
4246	intel_encoder->get_power_domains = intel_ddi_get_power_domains;	4286	intel_encoder->get_power_domains = intel_ddi_get_power_domains;
4247	intel_encoder->type = INTEL_OUTPUT_DDI;	4287	intel_encoder->type = INTEL_OUTPUT_DDI;
4248	intel_encoder->power_domain = intel_port_to_power_domain(port);	4288	intel_encoder->power_domain = intel_port_to_power_domain(port);
@@ -4261,9 +4301,15 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) · 12 unmodified lines
4261	intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);	4301	intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
4262	intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);	4302	intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
4263		4303
4264	intel_dig_port->tc_legacy_port = intel_port_is_tc(dev_priv, port) &&	4304	if (intel_phy_is_tc(dev_priv, phy)) {
4265	!port_info->supports_typec_usb &&	4305	bool is_legacy = !port_info->supports_typec_usb &&
4266	!port_info->supports_tbt;	4306	!port_info->supports_tbt;
		4307
		4308	intel_tc_port_init(intel_dig_port, is_legacy);
		4309
		4310	intel_encoder->update_prepare = intel_ddi_update_prepare;
		4311	intel_encoder->update_complete = intel_ddi_update_complete;
		4312	}
4267		4313
4268	switch (port) {	4314	switch (port) {
4269	case PORT_A:	4315	case PORT_A:
@@ -4290,6 +4336,18 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) · 20 unmodified lines
4290	intel_dig_port->ddi_io_power_domain =	4336	intel_dig_port->ddi_io_power_domain =
4291	POWER_DOMAIN_PORT_DDI_F_IO;	4337	POWER_DOMAIN_PORT_DDI_F_IO;
4292	break;	4338	break;
		4339	case PORT_G:
		4340	intel_dig_port->ddi_io_power_domain =
		4341	POWER_DOMAIN_PORT_DDI_G_IO;
		4342	break;
		4343	case PORT_H:
		4344	intel_dig_port->ddi_io_power_domain =
		4345	POWER_DOMAIN_PORT_DDI_H_IO;
		4346	break;
		4347	case PORT_I:
		4348	intel_dig_port->ddi_io_power_domain =
		4349	POWER_DOMAIN_PORT_DDI_I_IO;
		4350	break;
4293	default:	4351	default:
4294	MISSING_CASE(port);	4352	MISSING_CASE(port);
4295	}	4353	}
@@ -4324,9 +4382,6 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) · 28 unmodified lines
4324		4382
4325	intel_infoframe_init(intel_dig_port);	4383	intel_infoframe_init(intel_dig_port);
4326		4384
4327	if (intel_port_is_tc(dev_priv, port))
4328	intel_digital_port_connected(intel_encoder);
4329
4330	return;	4385	return;
4331		4386
4332	err:	4387	err:

drivers/gpu/drm/i915/display/intel_display.c+734−511

@@ -78,6 +78,7 @@ · 77 unmodified lines
78	#include "intel_quirks.h"	78	#include "intel_quirks.h"
79	#include "intel_sideband.h"	79	#include "intel_sideband.h"
80	#include "intel_sprite.h"	80	#include "intel_sprite.h"
		81	#include "intel_tc.h"
81		82
82	/* Primary plane formats for gen <= 3 */	83	/* Primary plane formats for gen <= 3 */
83	static const u32 i8xx_primary_formats[] = {	84	static const u32 i8xx_primary_formats[] = {
@@ -515,9 +516,9 @@ icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, · 431 unmodified lines
515	}	516	}
516		517
517	static bool	518	static bool
518	needs_modeset(const struct drm_crtc_state *state)	519	needs_modeset(const struct intel_crtc_state *state)
519	{	520	{
520	return drm_atomic_crtc_needs_modeset(state);	521	return drm_atomic_crtc_needs_modeset(&state->base);
521	}	522	}
522		523
523	/*	524	/*
@@ -3715,10 +3716,27 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state) · 3191 unmodified lines
3715	return 0;	3716	return 0;
3716	}	3717	}
3717		3718
		3719	static bool i9xx_plane_has_windowing(struct intel_plane *plane)
		3720	{
		3721	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
		3722	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
		3723
		3724	if (IS_CHERRYVIEW(dev_priv))
		3725	return i9xx_plane == PLANE_B;
		3726	else if (INTEL_GEN(dev_priv) >= 5 \|\| IS_G4X(dev_priv))
		3727	return false;
		3728	else if (IS_GEN(dev_priv, 4))
		3729	return i9xx_plane == PLANE_C;
		3730	else
		3731	return i9xx_plane == PLANE_B \|\|
		3732	i9xx_plane == PLANE_C;
		3733	}
		3734
3718	static int	3735	static int
3719	i9xx_plane_check(struct intel_crtc_state *crtc_state,	3736	i9xx_plane_check(struct intel_crtc_state *crtc_state,
3720	struct intel_plane_state *plane_state)	3737	struct intel_plane_state *plane_state)
3721	{	3738	{
		3739	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
3722	int ret;	3740	int ret;
3723		3741
3724	ret = chv_plane_check_rotation(plane_state);	3742	ret = chv_plane_check_rotation(plane_state);
@@ -3729,7 +3747,8 @@ i9xx_plane_check(struct intel_crtc_state *crtc_state, · 4 unmodified lines
3729	&crtc_state->base,	3747	&crtc_state->base,
3730	DRM_PLANE_HELPER_NO_SCALING,	3748	DRM_PLANE_HELPER_NO_SCALING,
3731	DRM_PLANE_HELPER_NO_SCALING,	3749	DRM_PLANE_HELPER_NO_SCALING,
3732	false, true);	3750	i9xx_plane_has_windowing(plane),
		3751	true);
3733	if (ret)	3752	if (ret)
3734	return ret;	3753	return ret;
3735		3754
@@ -3758,6 +3777,10 @@ static void i9xx_update_plane(struct intel_plane *plane, · 22 unmodified lines
3758	u32 linear_offset;	3777	u32 linear_offset;
3759	int x = plane_state->color_plane[0].x;	3778	int x = plane_state->color_plane[0].x;
3760	int y = plane_state->color_plane[0].y;	3779	int y = plane_state->color_plane[0].y;
		3780	int crtc_x = plane_state->base.dst.x1;
		3781	int crtc_y = plane_state->base.dst.y1;
		3782	int crtc_w = drm_rect_width(&plane_state->base.dst);
		3783	int crtc_h = drm_rect_height(&plane_state->base.dst);
3761	unsigned long irqflags;	3784	unsigned long irqflags;
3762	u32 dspaddr_offset;	3785	u32 dspaddr_offset;
3763	u32 dspcntr;	3786	u32 dspcntr;
@@ -3776,18 +3799,18 @@ static void i9xx_update_plane(struct intel_plane *plane, · 12 unmodified lines
3776	I915_WRITE_FW(DSPSTRIDE(i9xx_plane), plane_state->color_plane[0].stride);	3799	I915_WRITE_FW(DSPSTRIDE(i9xx_plane), plane_state->color_plane[0].stride);
3777		3800
3778	if (INTEL_GEN(dev_priv) < 4) {	3801	if (INTEL_GEN(dev_priv) < 4) {
3779	/* pipesrc and dspsize control the size that is scaled from,	3802	/*
3780	* which should always be the user's requested size.	3803	* PLANE_A doesn't actually have a full window
		3804	* generator but let's assume we still need to
		3805	* program whatever is there.
3781	*/	3806	*/
3782	I915_WRITE_FW(DSPPOS(i9xx_plane), 0);	3807	I915_WRITE_FW(DSPPOS(i9xx_plane), (crtc_y << 16) \| crtc_x);
3783	I915_WRITE_FW(DSPSIZE(i9xx_plane),	3808	I915_WRITE_FW(DSPSIZE(i9xx_plane),
3784	((crtc_state->pipe_src_h - 1) << 16) \|	3809	((crtc_h - 1) << 16) \| (crtc_w - 1));
3785	(crtc_state->pipe_src_w - 1));
3786	} else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {	3810	} else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
3787	I915_WRITE_FW(PRIMPOS(i9xx_plane), 0);	3811	I915_WRITE_FW(PRIMPOS(i9xx_plane), (crtc_y << 16) \| crtc_x);
3788	I915_WRITE_FW(PRIMSIZE(i9xx_plane),	3812	I915_WRITE_FW(PRIMSIZE(i9xx_plane),
3789	((crtc_state->pipe_src_h - 1) << 16) \|	3813	((crtc_h - 1) << 16) \| (crtc_w - 1));
3790	(crtc_state->pipe_src_w - 1));
3791	I915_WRITE_FW(PRIMCNSTALPHA(i9xx_plane), 0);	3814	I915_WRITE_FW(PRIMCNSTALPHA(i9xx_plane), 0);
3792	}	3815	}
3793		3816
@@ -3950,10 +3973,10 @@ static u32 skl_plane_ctl_format(u32 pixel_format) · 156 unmodified lines
3950	case DRM_FORMAT_XRGB8888:	3973	case DRM_FORMAT_XRGB8888:
3951	case DRM_FORMAT_ARGB8888:	3974	case DRM_FORMAT_ARGB8888:
3952	return PLANE_CTL_FORMAT_XRGB_8888;	3975	return PLANE_CTL_FORMAT_XRGB_8888;
		3976	case DRM_FORMAT_XBGR2101010:
		3977	return PLANE_CTL_FORMAT_XRGB_2101010 \| PLANE_CTL_ORDER_RGBX;
3953	case DRM_FORMAT_XRGB2101010:	3978	case DRM_FORMAT_XRGB2101010:
3954	return PLANE_CTL_FORMAT_XRGB_2101010;	3979	return PLANE_CTL_FORMAT_XRGB_2101010;
3955	case DRM_FORMAT_XBGR2101010:
3956	return PLANE_CTL_ORDER_RGBX \| PLANE_CTL_FORMAT_XRGB_2101010;
3957	case DRM_FORMAT_XBGR16161616F:	3980	case DRM_FORMAT_XBGR16161616F:
3958	case DRM_FORMAT_ABGR16161616F:	3981	case DRM_FORMAT_ABGR16161616F:
3959	return PLANE_CTL_FORMAT_XRGB_16161616F \| PLANE_CTL_ORDER_RGBX;	3982	return PLANE_CTL_FORMAT_XRGB_16161616F \| PLANE_CTL_ORDER_RGBX;
@@ -4248,12 +4271,13 @@ void intel_prepare_reset(struct drm_i915_private *dev_priv) · 288 unmodified lines
4248	return;	4271	return;
4249		4272
4250	/* We have a modeset vs reset deadlock, defensively unbreak it. */	4273	/* We have a modeset vs reset deadlock, defensively unbreak it. */
4251	set_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);	4274	set_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
4252	wake_up_all(&dev_priv->gpu_error.wait_queue);	4275	smp_mb__after_atomic();
		4276	wake_up_bit(&dev_priv->gt.reset.flags, I915_RESET_MODESET);
4253		4277
4254	if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {	4278	if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) {
4255	DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n");	4279	DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n");
4256	i915_gem_set_wedged(dev_priv);	4280	intel_gt_set_wedged(&dev_priv->gt);
4257	}	4281	}
4258		4282
4259	/*	4283	/*
@@ -4299,7 +4323,7 @@ void intel_finish_reset(struct drm_i915_private *dev_priv) · 39 unmodified lines
4299	int ret;	4323	int ret;
4300		4324
4301	/* reset doesn't touch the display */	4325	/* reset doesn't touch the display */
4302	if (!test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags))	4326	if (!test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
4303	return;	4327	return;
4304		4328
4305	state = fetch_and_zero(&dev_priv->modeset_restore_state);	4329	state = fetch_and_zero(&dev_priv->modeset_restore_state);
@@ -4339,7 +4363,7 @@ unlock: · 33 unmodified lines
4339	drm_modeset_acquire_fini(ctx);	4363	drm_modeset_acquire_fini(ctx);
4340	mutex_unlock(&dev->mode_config.mutex);	4364	mutex_unlock(&dev->mode_config.mutex);
4341		4365
4342	clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags);	4366	clear_bit_unlock(I915_RESET_MODESET, &dev_priv->gt.reset.flags);
4343	}	4367	}
4344		4368
4345	static void icl_set_pipe_chicken(struct intel_crtc *crtc)	4369	static void icl_set_pipe_chicken(struct intel_crtc *crtc)
@@ -5796,7 +5820,7 @@ static bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_s · 1450 unmodified lines
5796	if (!old_crtc_state->ips_enabled)	5820	if (!old_crtc_state->ips_enabled)
5797	return false;	5821	return false;
5798		5822
5799	if (needs_modeset(&new_crtc_state->base))	5823	if (needs_modeset(new_crtc_state))
5800	return true;	5824	return true;
5801		5825
5802	/*	5826	/*
@@ -5823,7 +5847,7 @@ static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_s · 20 unmodified lines
5823	if (!new_crtc_state->ips_enabled)	5847	if (!new_crtc_state->ips_enabled)
5824	return false;	5848	return false;
5825		5849
5826	if (needs_modeset(&new_crtc_state->base))	5850	if (needs_modeset(new_crtc_state))
5827	return true;	5851	return true;
5828		5852
5829	/*	5853	/*
@@ -5877,13 +5901,13 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) · 47 unmodified lines
5877	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);	5901	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5878	struct drm_device *dev = crtc->base.dev;	5902	struct drm_device *dev = crtc->base.dev;
5879	struct drm_i915_private *dev_priv = to_i915(dev);	5903	struct drm_i915_private *dev_priv = to_i915(dev);
5880	struct drm_atomic_state *old_state = old_crtc_state->base.state;	5904	struct drm_atomic_state *state = old_crtc_state->base.state;
5881	struct intel_crtc_state *pipe_config =	5905	struct intel_crtc_state *pipe_config =
5882	intel_atomic_get_new_crtc_state(to_intel_atomic_state(old_state),	5906	intel_atomic_get_new_crtc_state(to_intel_atomic_state(state),
5883	crtc);	5907	crtc);
5884	struct drm_plane *primary = crtc->base.primary;	5908	struct drm_plane *primary = crtc->base.primary;
5885	struct drm_plane_state *old_primary_state =	5909	struct drm_plane_state *old_primary_state =
5886	drm_atomic_get_old_plane_state(old_state, primary);	5910	drm_atomic_get_old_plane_state(state, primary);
5887		5911
5888	intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);	5912	intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5889		5913
@@ -5895,12 +5919,12 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) · 5 unmodified lines
5895		5919
5896	if (old_primary_state) {	5920	if (old_primary_state) {
5897	struct drm_plane_state *new_primary_state =	5921	struct drm_plane_state *new_primary_state =
5898	drm_atomic_get_new_plane_state(old_state, primary);	5922	drm_atomic_get_new_plane_state(state, primary);
5899		5923
5900	intel_fbc_post_update(crtc);	5924	intel_fbc_post_update(crtc);
5901		5925
5902	if (new_primary_state->visible &&	5926	if (new_primary_state->visible &&
5903	(needs_modeset(&pipe_config->base) \|\|	5927	(needs_modeset(pipe_config) \|\|
5904	!old_primary_state->visible))	5928	!old_primary_state->visible))
5905	intel_post_enable_primary(&crtc->base, pipe_config);	5929	intel_post_enable_primary(&crtc->base, pipe_config);
5906	}	5930	}
@@ -5920,20 +5944,20 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state, · 13 unmodified lines
5920	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);	5944	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5921	struct drm_device *dev = crtc->base.dev;	5945	struct drm_device *dev = crtc->base.dev;
5922	struct drm_i915_private *dev_priv = to_i915(dev);	5946	struct drm_i915_private *dev_priv = to_i915(dev);
5923	struct drm_atomic_state *old_state = old_crtc_state->base.state;	5947	struct drm_atomic_state *state = old_crtc_state->base.state;
5924	struct drm_plane *primary = crtc->base.primary;	5948	struct drm_plane *primary = crtc->base.primary;
5925	struct drm_plane_state *old_primary_state =	5949	struct drm_plane_state *old_primary_state =
5926	drm_atomic_get_old_plane_state(old_state, primary);	5950	drm_atomic_get_old_plane_state(state, primary);
5927	bool modeset = needs_modeset(&pipe_config->base);	5951	bool modeset = needs_modeset(pipe_config);
5928	struct intel_atomic_state *old_intel_state =	5952	struct intel_atomic_state *intel_state =
5929	to_intel_atomic_state(old_state);	5953	to_intel_atomic_state(state);
5930		5954
5931	if (hsw_pre_update_disable_ips(old_crtc_state, pipe_config))	5955	if (hsw_pre_update_disable_ips(old_crtc_state, pipe_config))
5932	hsw_disable_ips(old_crtc_state);	5956	hsw_disable_ips(old_crtc_state);
5933		5957
5934	if (old_primary_state) {	5958	if (old_primary_state) {
5935	struct intel_plane_state *new_primary_state =	5959	struct intel_plane_state *new_primary_state =
5936	intel_atomic_get_new_plane_state(old_intel_state,	5960	intel_atomic_get_new_plane_state(intel_state,
5937	to_intel_plane(primary));	5961	to_intel_plane(primary));
5938		5962
5939	intel_fbc_pre_update(crtc, pipe_config, new_primary_state);	5963	intel_fbc_pre_update(crtc, pipe_config, new_primary_state);
@@ -5984,7 +6008,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state, · 44 unmodified lines
5984	* If we're doing a modeset, we're done. No need to do any pre-vblank	6008	* If we're doing a modeset, we're done. No need to do any pre-vblank
5985	* watermark programming here.	6009	* watermark programming here.
5986	*/	6010	*/
5987	if (needs_modeset(&pipe_config->base))	6011	if (needs_modeset(pipe_config))
5988	return;	6012	return;
5989		6013
5990	/*	6014	/*
@@ -6002,7 +6026,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state, · 11 unmodified lines
6002	* us to.	6026	* us to.
6003	*/	6027	*/
6004	if (dev_priv->display.initial_watermarks != NULL)	6028	if (dev_priv->display.initial_watermarks != NULL)
6005	dev_priv->display.initial_watermarks(old_intel_state,	6029	dev_priv->display.initial_watermarks(intel_state,
6006	pipe_config);	6030	pipe_config);
6007	else if (pipe_config->update_wm_pre)	6031	else if (pipe_config->update_wm_pre)
6008	intel_update_watermarks(crtc);	6032	intel_update_watermarks(crtc);
@@ -6036,19 +6060,111 @@ static void intel_crtc_disable_planes(struct intel_atomic_state *state, · 27 unmodified lines
6036	intel_frontbuffer_flip(dev_priv, fb_bits);	6060	intel_frontbuffer_flip(dev_priv, fb_bits);
6037	}	6061	}
6038		6062
6039	static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,	6063	/*
		6064	* intel_connector_primary_encoder - get the primary encoder for a connector
		6065	* @connector: connector for which to return the encoder
		6066	*
		6067	* Returns the primary encoder for a connector. There is a 1:1 mapping from
		6068	* all connectors to their encoder, except for DP-MST connectors which have
		6069	* both a virtual and a primary encoder. These DP-MST primary encoders can be
		6070	* pointed to by as many DP-MST connectors as there are pipes.
		6071	*/
		6072	static struct intel_encoder *
		6073	intel_connector_primary_encoder(struct intel_connector *connector)
		6074	{
		6075	struct intel_encoder *encoder;
		6076
		6077	if (connector->mst_port)
		6078	return &dp_to_dig_port(connector->mst_port)->base;
		6079
		6080	encoder = intel_attached_encoder(&connector->base);
		6081	WARN_ON(!encoder);
		6082
		6083	return encoder;
		6084	}
		6085
		6086	static bool
		6087	intel_connector_needs_modeset(struct intel_atomic_state *state,
		6088	const struct drm_connector_state *old_conn_state,
		6089	const struct drm_connector_state *new_conn_state)
		6090	{
		6091	struct intel_crtc *old_crtc = old_conn_state->crtc ?
		6092	to_intel_crtc(old_conn_state->crtc) : NULL;
		6093	struct intel_crtc *new_crtc = new_conn_state->crtc ?
		6094	to_intel_crtc(new_conn_state->crtc) : NULL;
		6095
		6096	return new_crtc != old_crtc \|\|
		6097	(new_crtc &&
		6098	needs_modeset(intel_atomic_get_new_crtc_state(state, new_crtc)));
		6099	}
		6100
		6101	static void intel_encoders_update_prepare(struct intel_atomic_state *state)
		6102	{
		6103	struct drm_connector_state *old_conn_state;
		6104	struct drm_connector_state *new_conn_state;
		6105	struct drm_connector *conn;
		6106	int i;
		6107
		6108	for_each_oldnew_connector_in_state(&state->base, conn,
		6109	old_conn_state, new_conn_state, i) {
		6110	struct intel_encoder *encoder;
		6111	struct intel_crtc *crtc;
		6112
		6113	if (!intel_connector_needs_modeset(state,
		6114	old_conn_state,
		6115	new_conn_state))
		6116	continue;
		6117
		6118	encoder = intel_connector_primary_encoder(to_intel_connector(conn));
		6119	if (!encoder->update_prepare)
		6120	continue;
		6121
		6122	crtc = new_conn_state->crtc ?
		6123	to_intel_crtc(new_conn_state->crtc) : NULL;
		6124	encoder->update_prepare(state, encoder, crtc);
		6125	}
		6126	}
		6127
		6128	static void intel_encoders_update_complete(struct intel_atomic_state *state)
		6129	{
		6130	struct drm_connector_state *old_conn_state;
		6131	struct drm_connector_state *new_conn_state;
		6132	struct drm_connector *conn;
		6133	int i;
		6134
		6135	for_each_oldnew_connector_in_state(&state->base, conn,
		6136	old_conn_state, new_conn_state, i) {
		6137	struct intel_encoder *encoder;
		6138	struct intel_crtc *crtc;
		6139
		6140	if (!intel_connector_needs_modeset(state,
		6141	old_conn_state,
		6142	new_conn_state))
		6143	continue;
		6144
		6145	encoder = intel_connector_primary_encoder(to_intel_connector(conn));
		6146	if (!encoder->update_complete)
		6147	continue;
		6148
		6149	crtc = new_conn_state->crtc ?
		6150	to_intel_crtc(new_conn_state->crtc) : NULL;
		6151	encoder->update_complete(state, encoder, crtc);
		6152	}
		6153	}
		6154
		6155	static void intel_encoders_pre_pll_enable(struct intel_crtc *crtc,
6040	struct intel_crtc_state *crtc_state,	6156	struct intel_crtc_state *crtc_state,
6041	struct drm_atomic_state *old_state)	6157	struct intel_atomic_state *state)
6042	{	6158	{
6043	struct drm_connector_state *conn_state;	6159	struct drm_connector_state *conn_state;
6044	struct drm_connector *conn;	6160	struct drm_connector *conn;
6045	int i;	6161	int i;
6046		6162
6047	for_each_new_connector_in_state(old_state, conn, conn_state, i) {	6163	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6048	struct intel_encoder *encoder =	6164	struct intel_encoder *encoder =
6049	to_intel_encoder(conn_state->best_encoder);	6165	to_intel_encoder(conn_state->best_encoder);
6050		6166
6051	if (conn_state->crtc != crtc)	6167	if (conn_state->crtc != &crtc->base)
6052	continue;	6168	continue;
6053		6169
6054	if (encoder->pre_pll_enable)	6170	if (encoder->pre_pll_enable)
@@ -6056,19 +6172,19 @@ static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc, · 1 unmodified line
6056	}	6172	}
6057	}	6173	}
6058		6174
6059	static void intel_encoders_pre_enable(struct drm_crtc *crtc,	6175	static void intel_encoders_pre_enable(struct intel_crtc *crtc,
6060	struct intel_crtc_state *crtc_state,	6176	struct intel_crtc_state *crtc_state,
6061	struct drm_atomic_state *old_state)	6177	struct intel_atomic_state *state)
6062	{	6178	{
6063	struct drm_connector_state *conn_state;	6179	struct drm_connector_state *conn_state;
6064	struct drm_connector *conn;	6180	struct drm_connector *conn;
6065	int i;	6181	int i;
6066		6182
6067	for_each_new_connector_in_state(old_state, conn, conn_state, i) {	6183	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6068	struct intel_encoder *encoder =	6184	struct intel_encoder *encoder =
6069	to_intel_encoder(conn_state->best_encoder);	6185	to_intel_encoder(conn_state->best_encoder);
6070		6186
6071	if (conn_state->crtc != crtc)	6187	if (conn_state->crtc != &crtc->base)
6072	continue;	6188	continue;
6073		6189
6074	if (encoder->pre_enable)	6190	if (encoder->pre_enable)
@@ -6076,19 +6192,19 @@ static void intel_encoders_pre_enable(struct drm_crtc *crtc, · 1 unmodified line
6076	}	6192	}
6077	}	6193	}
6078		6194
6079	static void intel_encoders_enable(struct drm_crtc *crtc,	6195	static void intel_encoders_enable(struct intel_crtc *crtc,
6080	struct intel_crtc_state *crtc_state,	6196	struct intel_crtc_state *crtc_state,
6081	struct drm_atomic_state *old_state)	6197	struct intel_atomic_state *state)
6082	{	6198	{
6083	struct drm_connector_state *conn_state;	6199	struct drm_connector_state *conn_state;
6084	struct drm_connector *conn;	6200	struct drm_connector *conn;
6085	int i;	6201	int i;
6086		6202
6087	for_each_new_connector_in_state(old_state, conn, conn_state, i) {	6203	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6088	struct intel_encoder *encoder =	6204	struct intel_encoder *encoder =
6089	to_intel_encoder(conn_state->best_encoder);	6205	to_intel_encoder(conn_state->best_encoder);
6090		6206
6091	if (conn_state->crtc != crtc)	6207	if (conn_state->crtc != &crtc->base)
6092	continue;	6208	continue;
6093		6209
6094	if (encoder->enable)	6210	if (encoder->enable)
@@ -6097,19 +6213,19 @@ static void intel_encoders_enable(struct drm_crtc *crtc, · 2 unmodified lines
6097	}	6213	}
6098	}	6214	}
6099		6215
6100	static void intel_encoders_disable(struct drm_crtc *crtc,	6216	static void intel_encoders_disable(struct intel_crtc *crtc,
6101	struct intel_crtc_state *old_crtc_state,	6217	struct intel_crtc_state *old_crtc_state,
6102	struct drm_atomic_state *old_state)	6218	struct intel_atomic_state *state)
6103	{	6219	{
6104	struct drm_connector_state *old_conn_state;	6220	struct drm_connector_state *old_conn_state;
6105	struct drm_connector *conn;	6221	struct drm_connector *conn;
6106	int i;	6222	int i;
6107		6223
6108	for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {	6224	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6109	struct intel_encoder *encoder =	6225	struct intel_encoder *encoder =
6110	to_intel_encoder(old_conn_state->best_encoder);	6226	to_intel_encoder(old_conn_state->best_encoder);
6111		6227
6112	if (old_conn_state->crtc != crtc)	6228	if (old_conn_state->crtc != &crtc->base)
6113	continue;	6229	continue;
6114		6230
6115	intel_opregion_notify_encoder(encoder, false);	6231	intel_opregion_notify_encoder(encoder, false);
@@ -6118,19 +6234,19 @@ static void intel_encoders_disable(struct drm_crtc *crtc, · 2 unmodified lines
6118	}	6234	}
6119	}	6235	}
6120		6236
6121	static void intel_encoders_post_disable(struct drm_crtc *crtc,	6237	static void intel_encoders_post_disable(struct intel_crtc *crtc,
6122	struct intel_crtc_state *old_crtc_state,	6238	struct intel_crtc_state *old_crtc_state,
6123	struct drm_atomic_state *old_state)	6239	struct intel_atomic_state *state)
6124	{	6240	{
6125	struct drm_connector_state *old_conn_state;	6241	struct drm_connector_state *old_conn_state;
6126	struct drm_connector *conn;	6242	struct drm_connector *conn;
6127	int i;	6243	int i;
6128		6244
6129	for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {	6245	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6130	struct intel_encoder *encoder =	6246	struct intel_encoder *encoder =
6131	to_intel_encoder(old_conn_state->best_encoder);	6247	to_intel_encoder(old_conn_state->best_encoder);
6132		6248
6133	if (old_conn_state->crtc != crtc)	6249	if (old_conn_state->crtc != &crtc->base)
6134	continue;	6250	continue;
6135		6251
6136	if (encoder->post_disable)	6252	if (encoder->post_disable)
@@ -6138,19 +6254,19 @@ static void intel_encoders_post_disable(struct drm_crtc *crtc, · 1 unmodified line
6138	}	6254	}
6139	}	6255	}
6140		6256
6141	static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,	6257	static void intel_encoders_post_pll_disable(struct intel_crtc *crtc,
6142	struct intel_crtc_state *old_crtc_state,	6258	struct intel_crtc_state *old_crtc_state,
6143	struct drm_atomic_state *old_state)	6259	struct intel_atomic_state *state)
6144	{	6260	{
6145	struct drm_connector_state *old_conn_state;	6261	struct drm_connector_state *old_conn_state;
6146	struct drm_connector *conn;	6262	struct drm_connector *conn;
6147	int i;	6263	int i;
6148		6264
6149	for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {	6265	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
6150	struct intel_encoder *encoder =	6266	struct intel_encoder *encoder =
6151	to_intel_encoder(old_conn_state->best_encoder);	6267	to_intel_encoder(old_conn_state->best_encoder);
6152		6268
6153	if (old_conn_state->crtc != crtc)	6269	if (old_conn_state->crtc != &crtc->base)
6154	continue;	6270	continue;
6155		6271
6156	if (encoder->post_pll_disable)	6272	if (encoder->post_pll_disable)
@@ -6158,19 +6274,19 @@ static void intel_encoders_post_pll_disable(struct drm_crtc *crtc, · 1 unmodified line
6158	}	6274	}
6159	}	6275	}
6160		6276
6161	static void intel_encoders_update_pipe(struct drm_crtc *crtc,	6277	static void intel_encoders_update_pipe(struct intel_crtc *crtc,
6162	struct intel_crtc_state *crtc_state,	6278	struct intel_crtc_state *crtc_state,
6163	struct drm_atomic_state *old_state)	6279	struct intel_atomic_state *state)
6164	{	6280	{
6165	struct drm_connector_state *conn_state;	6281	struct drm_connector_state *conn_state;
6166	struct drm_connector *conn;	6282	struct drm_connector *conn;
6167	int i;	6283	int i;
6168		6284
6169	for_each_new_connector_in_state(old_state, conn, conn_state, i) {	6285	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
6170	struct intel_encoder *encoder =	6286	struct intel_encoder *encoder =
6171	to_intel_encoder(conn_state->best_encoder);	6287	to_intel_encoder(conn_state->best_encoder);
6172		6288
6173	if (conn_state->crtc != crtc)	6289	if (conn_state->crtc != &crtc->base)
6174	continue;	6290	continue;
6175		6291
6176	if (encoder->update_pipe)	6292	if (encoder->update_pipe)
@@ -6187,15 +6303,13 @@ static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_stat · 10 unmodified lines
6187	}	6303	}
6188		6304
6189	static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,	6305	static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
6190	struct drm_atomic_state *old_state)	6306	struct intel_atomic_state *state)
6191	{	6307	{
6192	struct drm_crtc *crtc = pipe_config->base.crtc;	6308	struct drm_crtc *crtc = pipe_config->base.crtc;
6193	struct drm_device *dev = crtc->dev;	6309	struct drm_device *dev = crtc->dev;
6194	struct drm_i915_private *dev_priv = to_i915(dev);	6310	struct drm_i915_private *dev_priv = to_i915(dev);
6195	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	6311	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6196	int pipe = intel_crtc->pipe;	6312	int pipe = intel_crtc->pipe;
6197	struct intel_atomic_state *old_intel_state =
6198	to_intel_atomic_state(old_state);
6199		6313
6200	if (WARN_ON(intel_crtc->active))	6314	if (WARN_ON(intel_crtc->active))
6201	return;	6315	return;
@@ -6231,7 +6345,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config, · 29 unmodified lines
6231		6345
6232	intel_crtc->active = true;	6346	intel_crtc->active = true;
6233		6347
6234	intel_encoders_pre_enable(crtc, pipe_config, old_state);	6348	intel_encoders_pre_enable(intel_crtc, pipe_config, state);
6235		6349
6236	if (pipe_config->has_pch_encoder) {	6350	if (pipe_config->has_pch_encoder) {
6237	/* Note: FDI PLL enabling _must_ be done before we enable the	6351	/* Note: FDI PLL enabling _must_ be done before we enable the
@@ -6255,16 +6369,16 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config, · 17 unmodified lines
6255	intel_disable_primary_plane(pipe_config);	6369	intel_disable_primary_plane(pipe_config);
6256		6370
6257	if (dev_priv->display.initial_watermarks != NULL)	6371	if (dev_priv->display.initial_watermarks != NULL)
6258	dev_priv->display.initial_watermarks(old_intel_state, pipe_config);	6372	dev_priv->display.initial_watermarks(state, pipe_config);
6259	intel_enable_pipe(pipe_config);	6373	intel_enable_pipe(pipe_config);
6260		6374
6261	if (pipe_config->has_pch_encoder)	6375	if (pipe_config->has_pch_encoder)
6262	ironlake_pch_enable(old_intel_state, pipe_config);	6376	ironlake_pch_enable(state, pipe_config);
6263		6377
6264	assert_vblank_disabled(crtc);	6378	assert_vblank_disabled(crtc);
6265	intel_crtc_vblank_on(pipe_config);	6379	intel_crtc_vblank_on(pipe_config);
6266		6380
6267	intel_encoders_enable(crtc, pipe_config, old_state);	6381	intel_encoders_enable(intel_crtc, pipe_config, state);
6268		6382
6269	if (HAS_PCH_CPT(dev_priv))	6383	if (HAS_PCH_CPT(dev_priv))
6270	cpt_verify_modeset(dev, intel_crtc->pipe);	6384	cpt_verify_modeset(dev, intel_crtc->pipe);
@@ -6310,33 +6424,37 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc) · 39 unmodified lines
6310	u32 val;	6424	u32 val;
6311		6425
6312	val = MBUS_DBOX_A_CREDIT(2);	6426	val = MBUS_DBOX_A_CREDIT(2);
6313	val \|= MBUS_DBOX_BW_CREDIT(1);	6427
6314	val \|= MBUS_DBOX_B_CREDIT(8);	6428	if (INTEL_GEN(dev_priv) >= 12) {
		6429	val \|= MBUS_DBOX_BW_CREDIT(2);
		6430	val \|= MBUS_DBOX_B_CREDIT(12);
		6431	} else {
		6432	val \|= MBUS_DBOX_BW_CREDIT(1);
		6433	val \|= MBUS_DBOX_B_CREDIT(8);
		6434	}
6315		6435
6316	I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);	6436	I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
6317	}	6437	}
6318		6438
6319	static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,	6439	static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
6320	struct drm_atomic_state *old_state)	6440	struct intel_atomic_state *state)
6321	{	6441	{
6322	struct drm_crtc *crtc = pipe_config->base.crtc;	6442	struct drm_crtc *crtc = pipe_config->base.crtc;
6323	struct drm_i915_private *dev_priv = to_i915(crtc->dev);	6443	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6324	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	6444	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6325	int pipe = intel_crtc->pipe, hsw_workaround_pipe;	6445	int pipe = intel_crtc->pipe, hsw_workaround_pipe;
6326	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;	6446	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6327	struct intel_atomic_state *old_intel_state =
6328	to_intel_atomic_state(old_state);
6329	bool psl_clkgate_wa;	6447	bool psl_clkgate_wa;
6330		6448
6331	if (WARN_ON(intel_crtc->active))	6449	if (WARN_ON(intel_crtc->active))
6332	return;	6450	return;
6333		6451
6334	intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);	6452	intel_encoders_pre_pll_enable(intel_crtc, pipe_config, state);
6335		6453
6336	if (pipe_config->shared_dpll)	6454	if (pipe_config->shared_dpll)
6337	intel_enable_shared_dpll(pipe_config);	6455	intel_enable_shared_dpll(pipe_config);
6338		6456
6339	intel_encoders_pre_enable(crtc, pipe_config, old_state);	6457	intel_encoders_pre_enable(intel_crtc, pipe_config, state);
6340		6458
6341	if (intel_crtc_has_dp_encoder(pipe_config))	6459	if (intel_crtc_has_dp_encoder(pipe_config))
6342	intel_dp_set_m_n(pipe_config, M1_N1);	6460	intel_dp_set_m_n(pipe_config, M1_N1);
@@ -6394,7 +6512,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, · 51 unmodified lines
6394	intel_ddi_enable_transcoder_func(pipe_config);	6512	intel_ddi_enable_transcoder_func(pipe_config);
6395		6513
6396	if (dev_priv->display.initial_watermarks != NULL)	6514	if (dev_priv->display.initial_watermarks != NULL)
6397	dev_priv->display.initial_watermarks(old_intel_state, pipe_config);	6515	dev_priv->display.initial_watermarks(state, pipe_config);
6398		6516
6399	if (INTEL_GEN(dev_priv) >= 11)	6517	if (INTEL_GEN(dev_priv) >= 11)
6400	icl_pipe_mbus_enable(intel_crtc);	6518	icl_pipe_mbus_enable(intel_crtc);
@@ -6404,7 +6522,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, · 3 unmodified lines
6404	intel_enable_pipe(pipe_config);	6522	intel_enable_pipe(pipe_config);
6405		6523
6406	if (pipe_config->has_pch_encoder)	6524	if (pipe_config->has_pch_encoder)
6407	lpt_pch_enable(old_intel_state, pipe_config);	6525	lpt_pch_enable(state, pipe_config);
6408		6526
6409	if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))	6527	if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))
6410	intel_ddi_set_vc_payload_alloc(pipe_config, true);	6528	intel_ddi_set_vc_payload_alloc(pipe_config, true);
@@ -6412,7 +6530,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, · 1 unmodified line
6412	assert_vblank_disabled(crtc);	6530	assert_vblank_disabled(crtc);
6413	intel_crtc_vblank_on(pipe_config);	6531	intel_crtc_vblank_on(pipe_config);
6414		6532
6415	intel_encoders_enable(crtc, pipe_config, old_state);	6533	intel_encoders_enable(intel_crtc, pipe_config, state);
6416		6534
6417	if (psl_clkgate_wa) {	6535	if (psl_clkgate_wa) {
6418	intel_wait_for_vblank(dev_priv, pipe);	6536	intel_wait_for_vblank(dev_priv, pipe);
@@ -6444,7 +6562,7 @@ static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state) · 25 unmodified lines
6444	}	6562	}
6445		6563
6446	static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,	6564	static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
6447	struct drm_atomic_state *old_state)	6565	struct intel_atomic_state *state)
6448	{	6566	{
6449	struct drm_crtc *crtc = old_crtc_state->base.crtc;	6567	struct drm_crtc *crtc = old_crtc_state->base.crtc;
6450	struct drm_device *dev = crtc->dev;	6568	struct drm_device *dev = crtc->dev;
@@ -6460,7 +6578,7 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state, · 9 unmodified lines
6460	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);	6578	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6461	intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);	6579	intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
6462		6580
6463	intel_encoders_disable(crtc, old_crtc_state, old_state);	6581	intel_encoders_disable(intel_crtc, old_crtc_state, state);
6464		6582
6465	drm_crtc_vblank_off(crtc);	6583	drm_crtc_vblank_off(crtc);
6466	assert_vblank_disabled(crtc);	6584	assert_vblank_disabled(crtc);
@@ -6472,7 +6590,7 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state, · 5 unmodified lines
6472	if (old_crtc_state->has_pch_encoder)	6590	if (old_crtc_state->has_pch_encoder)
6473	ironlake_fdi_disable(crtc);	6591	ironlake_fdi_disable(crtc);
6474		6592
6475	intel_encoders_post_disable(crtc, old_crtc_state, old_state);	6593	intel_encoders_post_disable(intel_crtc, old_crtc_state, state);
6476		6594
6477	if (old_crtc_state->has_pch_encoder) {	6595	if (old_crtc_state->has_pch_encoder) {
6478	ironlake_disable_pch_transcoder(dev_priv, pipe);	6596	ironlake_disable_pch_transcoder(dev_priv, pipe);
@@ -6503,14 +6621,14 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state, · 24 unmodified lines
6503	}	6621	}
6504		6622
6505	static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,	6623	static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
6506	struct drm_atomic_state *old_state)	6624	struct intel_atomic_state *state)
6507	{	6625	{
6508	struct drm_crtc *crtc = old_crtc_state->base.crtc;	6626	struct drm_crtc *crtc = old_crtc_state->base.crtc;
6509	struct drm_i915_private *dev_priv = to_i915(crtc->dev);	6627	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6510	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	6628	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6511	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;	6629	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
6512		6630
6513	intel_encoders_disable(crtc, old_crtc_state, old_state);	6631	intel_encoders_disable(intel_crtc, old_crtc_state, state);
6514		6632
6515	drm_crtc_vblank_off(crtc);	6633	drm_crtc_vblank_off(crtc);
6516	assert_vblank_disabled(crtc);	6634	assert_vblank_disabled(crtc);
@@ -6532,9 +6650,9 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state, · 15 unmodified lines
6532	else	6650	else
6533	ironlake_pfit_disable(old_crtc_state);	6651	ironlake_pfit_disable(old_crtc_state);
6534		6652
6535	intel_encoders_post_disable(crtc, old_crtc_state, old_state);	6653	intel_encoders_post_disable(intel_crtc, old_crtc_state, state);
6536		6654
6537	intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);	6655	intel_encoders_post_pll_disable(intel_crtc, old_crtc_state, state);
6538	}	6656	}
6539		6657
6540	static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)	6658	static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
@@ -6560,33 +6678,47 @@ static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state) · 19 unmodified lines
6560	I915_WRITE(BCLRPAT(crtc->pipe), 0);	6678	I915_WRITE(BCLRPAT(crtc->pipe), 0);
6561	}	6679	}
6562		6680
6563	bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)	6681	bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
6564	{	6682	{
6565	if (port == PORT_NONE)	6683	if (phy == PHY_NONE)
6566	return false;	6684	return false;
6567		6685
6568	if (IS_ELKHARTLAKE(dev_priv))	6686	if (IS_ELKHARTLAKE(dev_priv) \|\| INTEL_GEN(dev_priv) >= 12)
6569	return port <= PORT_C;	6687	return phy <= PHY_C;
6570		6688
6571	if (INTEL_GEN(dev_priv) >= 11)	6689	if (INTEL_GEN(dev_priv) >= 11)
6572	return port <= PORT_B;	6690	return phy <= PHY_B;
6573		6691
6574	return false;	6692	return false;
6575	}	6693	}
6576		6694
6577	bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)	6695	bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
6578	{	6696	{
		6697	if (INTEL_GEN(dev_priv) >= 12)
		6698	return phy >= PHY_D && phy <= PHY_I;
		6699
6579	if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))	6700	if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
6580	return port >= PORT_C && port <= PORT_F;	6701	return phy >= PHY_C && phy <= PHY_F;
6581		6702
6582	return false;	6703	return false;
6583	}	6704	}
6584		6705
		6706	enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
		6707	{
		6708	if (IS_ELKHARTLAKE(i915) && port == PORT_D)
		6709	return PHY_A;
		6710
		6711	return (enum phy)port;
		6712	}
		6713
6585	enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)	6714	enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
6586	{	6715	{
6587	if (!intel_port_is_tc(dev_priv, port))	6716	if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
6588	return PORT_TC_NONE;	6717	return PORT_TC_NONE;
6589		6718
		6719	if (INTEL_GEN(dev_priv) >= 12)
		6720	return port - PORT_D;
		6721
6590	return port - PORT_C;	6722	return port - PORT_C;
6591	}	6723	}
6592		6724
@@ -6614,6 +6746,26 @@ enum intel_display_power_domain intel_port_to_power_domain(enum port port) · 21 unmodified lines
6614	enum intel_display_power_domain	6746	enum intel_display_power_domain
6615	intel_aux_power_domain(struct intel_digital_port *dig_port)	6747	intel_aux_power_domain(struct intel_digital_port *dig_port)
6616	{	6748	{
		6749	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
		6750	enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
		6751
		6752	if (intel_phy_is_tc(dev_priv, phy) &&
		6753	dig_port->tc_mode == TC_PORT_TBT_ALT) {
		6754	switch (dig_port->aux_ch) {
		6755	case AUX_CH_C:
		6756	return POWER_DOMAIN_AUX_TBT1;
		6757	case AUX_CH_D:
		6758	return POWER_DOMAIN_AUX_TBT2;
		6759	case AUX_CH_E:
		6760	return POWER_DOMAIN_AUX_TBT3;
		6761	case AUX_CH_F:
		6762	return POWER_DOMAIN_AUX_TBT4;
		6763	default:
		6764	MISSING_CASE(dig_port->aux_ch);
		6765	return POWER_DOMAIN_AUX_TBT1;
		6766	}
		6767	}
		6768
6617	switch (dig_port->aux_ch) {	6769	switch (dig_port->aux_ch) {
6618	case AUX_CH_A:	6770	case AUX_CH_A:
6619	return POWER_DOMAIN_AUX_A;	6771	return POWER_DOMAIN_AUX_A;
@@ -6633,14 +6785,12 @@ intel_aux_power_domain(struct intel_digital_port *dig_port) · 13 unmodified lines
6633	}	6785	}
6634	}	6786	}
6635		6787
6636	static u64 get_crtc_power_domains(struct drm_crtc *crtc,	6788	static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
6637	struct intel_crtc_state *crtc_state)
6638	{	6789	{
6639	struct drm_device *dev = crtc->dev;	6790	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
6640	struct drm_i915_private *dev_priv = to_i915(dev);	6791	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6641	struct drm_encoder *encoder;	6792	struct drm_encoder *encoder;
6642	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	6793	enum pipe pipe = crtc->pipe;
6643	enum pipe pipe = intel_crtc->pipe;
6644	u64 mask;	6794	u64 mask;
6645	enum transcoder transcoder = crtc_state->cpu_transcoder;	6795	enum transcoder transcoder = crtc_state->cpu_transcoder;
6646		6796
@@ -6653,7 +6803,8 @@ static u64 get_crtc_power_domains(struct drm_crtc *crtc, · 6 unmodified lines
6653	crtc_state->pch_pfit.force_thru)	6803	crtc_state->pch_pfit.force_thru)
6654	mask \|= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));	6804	mask \|= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
6655		6805
6656	drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {	6806	drm_for_each_encoder_mask(encoder, &dev_priv->drm,
		6807	crtc_state->base.encoder_mask) {
6657	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);	6808	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6658		6809
6659	mask \|= BIT_ULL(intel_encoder->power_domain);	6810	mask \|= BIT_ULL(intel_encoder->power_domain);
@@ -6669,17 +6820,16 @@ static u64 get_crtc_power_domains(struct drm_crtc *crtc, · 9 unmodified lines
6669	}	6820	}
6670		6821
6671	static u64	6822	static u64
6672	modeset_get_crtc_power_domains(struct drm_crtc *crtc,	6823	modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state)
6673	struct intel_crtc_state *crtc_state)
6674	{	6824	{
6675	struct drm_i915_private *dev_priv = to_i915(crtc->dev);	6825	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
6676	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	6826	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6677	enum intel_display_power_domain domain;	6827	enum intel_display_power_domain domain;
6678	u64 domains, new_domains, old_domains;	6828	u64 domains, new_domains, old_domains;
6679		6829
6680	old_domains = intel_crtc->enabled_power_domains;	6830	old_domains = crtc->enabled_power_domains;
6681	intel_crtc->enabled_power_domains = new_domains =	6831	crtc->enabled_power_domains = new_domains =
6682	get_crtc_power_domains(crtc, crtc_state);	6832	get_crtc_power_domains(crtc_state);
6683		6833
6684	domains = new_domains & ~old_domains;	6834	domains = new_domains & ~old_domains;
6685		6835
@@ -6699,10 +6849,8 @@ static void modeset_put_power_domains(struct drm_i915_private *dev_priv, · 13 unmodified lines
6699	}	6849	}
6700		6850
6701	static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,	6851	static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
6702	struct drm_atomic_state *old_state)	6852	struct intel_atomic_state *state)
6703	{	6853	{
6704	struct intel_atomic_state *old_intel_state =
6705	to_intel_atomic_state(old_state);
6706	struct drm_crtc *crtc = pipe_config->base.crtc;	6854	struct drm_crtc *crtc = pipe_config->base.crtc;
6707	struct drm_device *dev = crtc->dev;	6855	struct drm_device *dev = crtc->dev;
6708	struct drm_i915_private *dev_priv = to_i915(dev);	6856	struct drm_i915_private *dev_priv = to_i915(dev);
@@ -6729,7 +6877,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config, · 20 unmodified lines
6729		6877
6730	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);	6878	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6731		6879
6732	intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);	6880	intel_encoders_pre_pll_enable(intel_crtc, pipe_config, state);
6733		6881
6734	if (IS_CHERRYVIEW(dev_priv)) {	6882	if (IS_CHERRYVIEW(dev_priv)) {
6735	chv_prepare_pll(intel_crtc, pipe_config);	6883	chv_prepare_pll(intel_crtc, pipe_config);
@@ -6739,7 +6887,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config, · 3 unmodified lines
6739	vlv_enable_pll(intel_crtc, pipe_config);	6887	vlv_enable_pll(intel_crtc, pipe_config);
6740	}	6888	}
6741		6889
6742	intel_encoders_pre_enable(crtc, pipe_config, old_state);	6890	intel_encoders_pre_enable(intel_crtc, pipe_config, state);
6743		6891
6744	i9xx_pfit_enable(pipe_config);	6892	i9xx_pfit_enable(pipe_config);
6745		6893
@@ -6748,14 +6896,13 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config, · 2 unmodified lines
6748	/* update DSPCNTR to configure gamma for pipe bottom color */	6896	/* update DSPCNTR to configure gamma for pipe bottom color */
6749	intel_disable_primary_plane(pipe_config);	6897	intel_disable_primary_plane(pipe_config);
6750		6898
6751	dev_priv->display.initial_watermarks(old_intel_state,	6899	dev_priv->display.initial_watermarks(state, pipe_config);
6752	pipe_config);
6753	intel_enable_pipe(pipe_config);	6900	intel_enable_pipe(pipe_config);
6754		6901
6755	assert_vblank_disabled(crtc);	6902	assert_vblank_disabled(crtc);
6756	intel_crtc_vblank_on(pipe_config);	6903	intel_crtc_vblank_on(pipe_config);
6757		6904
6758	intel_encoders_enable(crtc, pipe_config, old_state);	6905	intel_encoders_enable(intel_crtc, pipe_config, state);
6759	}	6906	}
6760		6907
6761	static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)	6908	static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
@@ -6768,10 +6915,8 @@ static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state) · 6 unmodified lines
6768	}	6915	}
6769		6916
6770	static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,	6917	static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
6771	struct drm_atomic_state *old_state)	6918	struct intel_atomic_state *state)
6772	{	6919	{
6773	struct intel_atomic_state *old_intel_state =
6774	to_intel_atomic_state(old_state);
6775	struct drm_crtc *crtc = pipe_config->base.crtc;	6920	struct drm_crtc *crtc = pipe_config->base.crtc;
6776	struct drm_device *dev = crtc->dev;	6921	struct drm_device *dev = crtc->dev;
6777	struct drm_i915_private *dev_priv = to_i915(dev);	6922	struct drm_i915_private *dev_priv = to_i915(dev);
@@ -6796,7 +6941,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config, · 18 unmodified lines
6796	if (!IS_GEN(dev_priv, 2))	6941	if (!IS_GEN(dev_priv, 2))
6797	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);	6942	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6798		6943
6799	intel_encoders_pre_enable(crtc, pipe_config, old_state);	6944	intel_encoders_pre_enable(intel_crtc, pipe_config, state);
6800		6945
6801	i9xx_enable_pll(intel_crtc, pipe_config);	6946	i9xx_enable_pll(intel_crtc, pipe_config);
6802		6947
@@ -6808,7 +6953,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config, · 5 unmodified lines
6808	intel_disable_primary_plane(pipe_config);	6953	intel_disable_primary_plane(pipe_config);
6809		6954
6810	if (dev_priv->display.initial_watermarks != NULL)	6955	if (dev_priv->display.initial_watermarks != NULL)
6811	dev_priv->display.initial_watermarks(old_intel_state,	6956	dev_priv->display.initial_watermarks(state,
6812	pipe_config);	6957	pipe_config);
6813	else	6958	else
6814	intel_update_watermarks(intel_crtc);	6959	intel_update_watermarks(intel_crtc);
@@ -6817,7 +6962,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config, · 2 unmodified lines
6817	assert_vblank_disabled(crtc);	6962	assert_vblank_disabled(crtc);
6818	intel_crtc_vblank_on(pipe_config);	6963	intel_crtc_vblank_on(pipe_config);
6819		6964
6820	intel_encoders_enable(crtc, pipe_config, old_state);	6965	intel_encoders_enable(intel_crtc, pipe_config, state);
6821	}	6966	}
6822		6967
6823	static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)	6968	static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
@@ -6836,7 +6981,7 @@ static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state) · 12 unmodified lines
6836	}	6981	}
6837		6982
6838	static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,	6983	static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
6839	struct drm_atomic_state *old_state)	6984	struct intel_atomic_state *state)
6840	{	6985	{
6841	struct drm_crtc *crtc = old_crtc_state->base.crtc;	6986	struct drm_crtc *crtc = old_crtc_state->base.crtc;
6842	struct drm_device *dev = crtc->dev;	6987	struct drm_device *dev = crtc->dev;
@@ -6851,7 +6996,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state, · 8 unmodified lines
6851	if (IS_GEN(dev_priv, 2))	6996	if (IS_GEN(dev_priv, 2))
6852	intel_wait_for_vblank(dev_priv, pipe);	6997	intel_wait_for_vblank(dev_priv, pipe);
6853		6998
6854	intel_encoders_disable(crtc, old_crtc_state, old_state);	6999	intel_encoders_disable(intel_crtc, old_crtc_state, state);
6855		7000
6856	drm_crtc_vblank_off(crtc);	7001	drm_crtc_vblank_off(crtc);
6857	assert_vblank_disabled(crtc);	7002	assert_vblank_disabled(crtc);
@@ -6860,7 +7005,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state, · 2 unmodified lines
6860		7005
6861	i9xx_pfit_disable(old_crtc_state);	7006	i9xx_pfit_disable(old_crtc_state);
6862		7007
6863	intel_encoders_post_disable(crtc, old_crtc_state, old_state);	7008	intel_encoders_post_disable(intel_crtc, old_crtc_state, state);
6864		7009
6865	if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {	7010	if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
6866	if (IS_CHERRYVIEW(dev_priv))	7011	if (IS_CHERRYVIEW(dev_priv))
@@ -6871,7 +7016,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state, · 4 unmodified lines
6871	i9xx_disable_pll(old_crtc_state);	7016	i9xx_disable_pll(old_crtc_state);
6872	}	7017	}
6873		7018
6874	intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);	7019	intel_encoders_post_pll_disable(intel_crtc, old_crtc_state, state);
6875		7020
6876	if (!IS_GEN(dev_priv, 2))	7021	if (!IS_GEN(dev_priv, 2))
6877	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);	7022	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
@@ -6925,7 +7070,7 @@ static void intel_crtc_disable_noatomic(struct drm_crtc *crtc, · 47 unmodified lines
6925		7070
6926	WARN_ON(IS_ERR(crtc_state) \|\| ret);	7071	WARN_ON(IS_ERR(crtc_state) \|\| ret);
6927		7072
6928	dev_priv->display.crtc_disable(crtc_state, state);	7073	dev_priv->display.crtc_disable(crtc_state, to_intel_atomic_state(state));
6929		7074
6930	drm_atomic_state_put(state);	7075	drm_atomic_state_put(state);
6931		7076
@@ -6988,7 +7133,7 @@ void intel_encoder_destroy(struct drm_encoder *encoder) · 56 unmodified lines
6988		7133
6989	/* Cross check the actual hw state with our own modeset state tracking (and it's	7134	/* Cross check the actual hw state with our own modeset state tracking (and it's
6990	* internal consistency). */	7135	* internal consistency). */
6991	static void intel_connector_verify_state(struct drm_crtc_state *crtc_state,	7136	static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
6992	struct drm_connector_state *conn_state)	7137	struct drm_connector_state *conn_state)
6993	{	7138	{
6994	struct intel_connector *connector = to_intel_connector(conn_state->connector);	7139	struct intel_connector *connector = to_intel_connector(conn_state->connector);
@@ -7006,7 +7151,7 @@ static void intel_connector_verify_state(struct drm_crtc_state *crtc_state, · 11 unmodified lines
7006	if (!crtc_state)	7151	if (!crtc_state)
7007	return;	7152	return;
7008		7153
7009	I915_STATE_WARN(!crtc_state->active,	7154	I915_STATE_WARN(!crtc_state->base.active,
7010	"connector is active, but attached crtc isn't\n");	7155	"connector is active, but attached crtc isn't\n");
7011		7156
7012	if (!encoder \|\| encoder->type == INTEL_OUTPUT_DP_MST)	7157	if (!encoder \|\| encoder->type == INTEL_OUTPUT_DP_MST)
@@ -7018,7 +7163,7 @@ static void intel_connector_verify_state(struct drm_crtc_state *crtc_state, · 5 unmodified lines
7018	I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,	7163	I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
7019	"attached encoder crtc differs from connector crtc\n");	7164	"attached encoder crtc differs from connector crtc\n");
7020	} else {	7165	} else {
7021	I915_STATE_WARN(crtc_state && crtc_state->active,	7166	I915_STATE_WARN(crtc_state && crtc_state->base.active,
7022	"attached crtc is active, but connector isn't\n");	7167	"attached crtc is active, but connector isn't\n");
7023	I915_STATE_WARN(!crtc_state && conn_state->best_encoder,	7168	I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
7024	"best encoder set without crtc!\n");	7169	"best encoder set without crtc!\n");
@@ -9484,6 +9629,8 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, · 2459 unmodified lines
9484	struct intel_crtc_state *crtc_state)	9629	struct intel_crtc_state *crtc_state)
9485	{	9630	{
9486	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);	9631	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
		9632	struct intel_atomic_state *state =
		9633	to_intel_atomic_state(crtc_state->base.state);
9487	const struct intel_limit *limit;	9634	const struct intel_limit *limit;
9488	int refclk = 120000;	9635	int refclk = 120000;
9489		9636
@@ -9525,7 +9672,7 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, · 35 unmodified lines
9525		9672
9526	ironlake_compute_dpll(crtc, crtc_state, NULL);	9673	ironlake_compute_dpll(crtc, crtc_state, NULL);
9527		9674
9528	if (!intel_get_shared_dpll(crtc_state, NULL)) {	9675	if (!intel_reserve_shared_dplls(state, crtc, NULL)) {
9529	DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",	9676	DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",
9530	pipe_name(crtc->pipe));	9677	pipe_name(crtc->pipe));
9531	return -EINVAL;	9678	return -EINVAL;
@@ -9906,7 +10053,7 @@ static int haswell_crtc_compute_clock(struct intel_crtc *crtc, · 374 unmodified lines
9906	struct intel_encoder *encoder =	10053	struct intel_encoder *encoder =
9907	intel_get_crtc_new_encoder(state, crtc_state);	10054	intel_get_crtc_new_encoder(state, crtc_state);
9908		10055
9909	if (!intel_get_shared_dpll(crtc_state, encoder)) {	10056	if (!intel_reserve_shared_dplls(state, crtc, encoder)) {
9910	DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",	10057	DRM_DEBUG_KMS("failed to find PLL for pipe %c\n",
9911	pipe_name(crtc->pipe));	10058	pipe_name(crtc->pipe));
9912	return -EINVAL;	10059	return -EINVAL;
@@ -9936,22 +10083,37 @@ static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv, · 23 unmodified lines
9936	enum port port,	10083	enum port port,
9937	struct intel_crtc_state *pipe_config)	10084	struct intel_crtc_state *pipe_config)
9938	{	10085	{
		10086	enum phy phy = intel_port_to_phy(dev_priv, port);
		10087	enum icl_port_dpll_id port_dpll_id;
9939	enum intel_dpll_id id;	10088	enum intel_dpll_id id;
9940	u32 temp;	10089	u32 temp;
9941		10090
9942	/* TODO: TBT pll not implemented. */	10091	if (intel_phy_is_combo(dev_priv, phy)) {
9943	if (intel_port_is_combophy(dev_priv, port)) {	10092	temp = I915_READ(ICL_DPCLKA_CFGCR0) &
9944	temp = I915_READ(DPCLKA_CFGCR0_ICL) &	10093	ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
9945	DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);	10094	id = temp >> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
9946	id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);	10095	port_dpll_id = ICL_PORT_DPLL_DEFAULT;
9947	} else if (intel_port_is_tc(dev_priv, port)) {	10096	} else if (intel_phy_is_tc(dev_priv, phy)) {
9948	id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv, port));	10097	u32 clk_sel = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
		10098
		10099	if (clk_sel == DDI_CLK_SEL_MG) {
		10100	id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv,
		10101	port));
		10102	port_dpll_id = ICL_PORT_DPLL_MG_PHY;
		10103	} else {
		10104	WARN_ON(clk_sel < DDI_CLK_SEL_TBT_162);
		10105	id = DPLL_ID_ICL_TBTPLL;
		10106	port_dpll_id = ICL_PORT_DPLL_DEFAULT;
		10107	}
9949	} else {	10108	} else {
9950	WARN(1, "Invalid port %x\n", port);	10109	WARN(1, "Invalid port %x\n", port);
9951	return;	10110	return;
9952	}	10111	}
9953		10112
9954	pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);	10113	pipe_config->icl_port_dplls[port_dpll_id].pll =
		10114	intel_get_shared_dpll_by_id(dev_priv, id);
		10115
		10116	icl_set_active_port_dpll(pipe_config, port_dpll_id);
9955	}	10117	}
9956		10118
9957	static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,	10119	static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
@@ -10191,7 +10353,11 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc, · 233 unmodified lines
10191		10353
10192	tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));	10354	tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
10193		10355
10194	port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;	10356	if (INTEL_GEN(dev_priv) >= 12)
		10357	port = (tmp & TGL_TRANS_DDI_PORT_MASK) >>
		10358	TGL_TRANS_DDI_PORT_SHIFT;
		10359	else
		10360	port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
10195		10361
10196	if (INTEL_GEN(dev_priv) >= 11)	10362	if (INTEL_GEN(dev_priv) >= 11)
10197	icelake_get_ddi_pll(dev_priv, port, pipe_config);	10363	icelake_get_ddi_pll(dev_priv, port, pipe_config);
@@ -11297,7 +11463,7 @@ static void intel_crtc_destroy(struct drm_crtc *crtc) · 1099 unmodified lines
11297	*	11463	*
11298	* Returns true or false.	11464	* Returns true or false.
11299	*/	11465	*/
11300	static bool intel_wm_need_update(struct intel_plane_state *cur,	11466	static bool intel_wm_need_update(const struct intel_plane_state *cur,
11301	struct intel_plane_state *new)	11467	struct intel_plane_state *new)
11302	{	11468	{
11303	/* Update watermarks on tiling or size changes. */	11469	/* Update watermarks on tiling or size changes. */
@@ -11329,33 +11495,28 @@ static bool needs_scaling(const struct intel_plane_state *state) · 25 unmodified lines
11329	}	11495	}
11330		11496
11331	int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,	11497	int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
11332	struct drm_crtc_state *crtc_state,	11498	struct intel_crtc_state *crtc_state,
11333	const struct intel_plane_state *old_plane_state,	11499	const struct intel_plane_state *old_plane_state,
11334	struct drm_plane_state *plane_state)	11500	struct intel_plane_state *plane_state)
11335	{	11501	{
11336	struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);	11502	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
11337	struct drm_crtc *crtc = crtc_state->crtc;	11503	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
11338	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	11504	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11339	struct intel_plane *plane = to_intel_plane(plane_state->plane);
11340	struct drm_device *dev = crtc->dev;
11341	struct drm_i915_private *dev_priv = to_i915(dev);
11342	bool mode_changed = needs_modeset(crtc_state);	11505	bool mode_changed = needs_modeset(crtc_state);
11343	bool was_crtc_enabled = old_crtc_state->base.active;	11506	bool was_crtc_enabled = old_crtc_state->base.active;
11344	bool is_crtc_enabled = crtc_state->active;	11507	bool is_crtc_enabled = crtc_state->base.active;
11345	bool turn_off, turn_on, visible, was_visible;	11508	bool turn_off, turn_on, visible, was_visible;
11346	struct drm_framebuffer *fb = plane_state->fb;	11509	struct drm_framebuffer *fb = plane_state->base.fb;
11347	int ret;	11510	int ret;
11348		11511
11349	if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {	11512	if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
11350	ret = skl_update_scaler_plane(	11513	ret = skl_update_scaler_plane(crtc_state, plane_state);
11351	to_intel_crtc_state(crtc_state),
11352	to_intel_plane_state(plane_state));
11353	if (ret)	11514	if (ret)
11354	return ret;	11515	return ret;
11355	}	11516	}
11356		11517
11357	was_visible = old_plane_state->base.visible;	11518	was_visible = old_plane_state->base.visible;
11358	visible = plane_state->visible;	11519	visible = plane_state->base.visible;
11359		11520
11360	if (!was_crtc_enabled && WARN_ON(was_visible))	11521	if (!was_crtc_enabled && WARN_ON(was_visible))
11361	was_visible = false;	11522	was_visible = false;
@@ -11371,22 +11532,22 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat · 9 unmodified lines
11371	* only combine the results from all planes in the current place?	11532	* only combine the results from all planes in the current place?
11372	*/	11533	*/
11373	if (!is_crtc_enabled) {	11534	if (!is_crtc_enabled) {
11374	plane_state->visible = visible = false;	11535	plane_state->base.visible = visible = false;
11375	to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);	11536	crtc_state->active_planes &= ~BIT(plane->id);
11376	to_intel_crtc_state(crtc_state)->data_rate[plane->id] = 0;	11537	crtc_state->data_rate[plane->id] = 0;
11377	}	11538	}
11378		11539
11379	if (!was_visible && !visible)	11540	if (!was_visible && !visible)
11380	return 0;	11541	return 0;
11381		11542
11382	if (fb != old_plane_state->base.fb)	11543	if (fb != old_plane_state->base.fb)
11383	pipe_config->fb_changed = true;	11544	crtc_state->fb_changed = true;
11384		11545
11385	turn_off = was_visible && (!visible \|\| mode_changed);	11546	turn_off = was_visible && (!visible \|\| mode_changed);
11386	turn_on = visible && (!was_visible \|\| mode_changed);	11547	turn_on = visible && (!was_visible \|\| mode_changed);
11387		11548
11388	DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",	11549	DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
11389	intel_crtc->base.base.id, intel_crtc->base.name,	11550	crtc->base.base.id, crtc->base.name,
11390	plane->base.base.id, plane->base.name,	11551	plane->base.base.id, plane->base.name,
11391	fb ? fb->base.id : -1);	11552	fb ? fb->base.id : -1);
11392		11553
@@ -11397,29 +11558,28 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat · 4 unmodified lines
11397		11558
11398	if (turn_on) {	11559	if (turn_on) {
11399	if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))	11560	if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11400	pipe_config->update_wm_pre = true;	11561	crtc_state->update_wm_pre = true;
11401		11562
11402	/* must disable cxsr around plane enable/disable */	11563	/* must disable cxsr around plane enable/disable */
11403	if (plane->id != PLANE_CURSOR)	11564	if (plane->id != PLANE_CURSOR)
11404	pipe_config->disable_cxsr = true;	11565	crtc_state->disable_cxsr = true;
11405	} else if (turn_off) {	11566	} else if (turn_off) {
11406	if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))	11567	if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
11407	pipe_config->update_wm_post = true;	11568	crtc_state->update_wm_post = true;
11408		11569
11409	/* must disable cxsr around plane enable/disable */	11570	/* must disable cxsr around plane enable/disable */
11410	if (plane->id != PLANE_CURSOR)	11571	if (plane->id != PLANE_CURSOR)
11411	pipe_config->disable_cxsr = true;	11572	crtc_state->disable_cxsr = true;
11412	} else if (intel_wm_need_update(to_intel_plane_state(plane->base.state),	11573	} else if (intel_wm_need_update(old_plane_state, plane_state)) {
11413	to_intel_plane_state(plane_state))) {
11414	if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {	11574	if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) {
11415	/* FIXME bollocks */	11575	/* FIXME bollocks */
11416	pipe_config->update_wm_pre = true;	11576	crtc_state->update_wm_pre = true;
11417	pipe_config->update_wm_post = true;	11577	crtc_state->update_wm_post = true;
11418	}	11578	}
11419	}	11579	}
11420		11580
11421	if (visible \|\| was_visible)	11581	if (visible \|\| was_visible)
11422	pipe_config->fb_bits \|= plane->frontbuffer_bit;	11582	crtc_state->fb_bits \|= plane->frontbuffer_bit;
11423		11583
11424	/*	11584	/*
11425	* ILK/SNB DVSACNTR/Sprite Enable	11585	* ILK/SNB DVSACNTR/Sprite Enable
@@ -11458,8 +11618,8 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat · 32 unmodified lines
11458	(IS_GEN_RANGE(dev_priv, 5, 6) \|\|	11618	(IS_GEN_RANGE(dev_priv, 5, 6) \|\|
11459	IS_IVYBRIDGE(dev_priv)) &&	11619	IS_IVYBRIDGE(dev_priv)) &&
11460	(turn_on \|\| (!needs_scaling(old_plane_state) &&	11620	(turn_on \|\| (!needs_scaling(old_plane_state) &&
11461	needs_scaling(to_intel_plane_state(plane_state)))))	11621	needs_scaling(plane_state))))
11462	pipe_config->disable_lp_wm = true;	11622	crtc_state->disable_lp_wm = true;
11463		11623
11464	return 0;	11624	return 0;
11465	}	11625	}
@@ -11608,7 +11768,7 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc, · 142 unmodified lines
11608	struct intel_crtc_state *pipe_config =	11768	struct intel_crtc_state *pipe_config =
11609	to_intel_crtc_state(crtc_state);	11769	to_intel_crtc_state(crtc_state);
11610	int ret;	11770	int ret;
11611	bool mode_changed = needs_modeset(crtc_state);	11771	bool mode_changed = needs_modeset(pipe_config);
11612		11772
11613	if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) &&	11773	if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) &&
11614	mode_changed && !crtc_state->active)	11774	mode_changed && !crtc_state->active)
@@ -12090,6 +12250,8 @@ clear_intel_crtc_state(struct intel_crtc_state *crtc_state) · 475 unmodified lines
12090	saved_state->scaler_state = crtc_state->scaler_state;	12250	saved_state->scaler_state = crtc_state->scaler_state;
12091	saved_state->shared_dpll = crtc_state->shared_dpll;	12251	saved_state->shared_dpll = crtc_state->shared_dpll;
12092	saved_state->dpll_hw_state = crtc_state->dpll_hw_state;	12252	saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
		12253	memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
		12254	sizeof(saved_state->icl_port_dplls));
12093	saved_state->crc_enabled = crtc_state->crc_enabled;	12255	saved_state->crc_enabled = crtc_state->crc_enabled;
12094	if (IS_G4X(dev_priv) \|\|	12256	if (IS_G4X(dev_priv) \|\|
12095	IS_VALLEYVIEW(dev_priv) \|\| IS_CHERRYVIEW(dev_priv))	12257	IS_VALLEYVIEW(dev_priv) \|\| IS_CHERRYVIEW(dev_priv))
@@ -12706,10 +12868,10 @@ static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, · 610 unmodified lines
12706	}	12868	}
12707	}	12869	}
12708		12870
12709	static void verify_wm_state(struct drm_crtc *crtc,	12871	static void verify_wm_state(struct intel_crtc *crtc,
12710	struct drm_crtc_state *new_state)	12872	struct intel_crtc_state *new_crtc_state)
12711	{	12873	{
12712	struct drm_i915_private *dev_priv = to_i915(crtc->dev);	12874	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12713	struct skl_hw_state {	12875	struct skl_hw_state {
12714	struct skl_ddb_entry ddb_y[I915_MAX_PLANES];	12876	struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
12715	struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];	12877	struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];
@@ -12719,21 +12881,20 @@ static void verify_wm_state(struct drm_crtc *crtc, · 3 unmodified lines
12719	struct skl_ddb_allocation *sw_ddb;	12881	struct skl_ddb_allocation *sw_ddb;
12720	struct skl_pipe_wm *sw_wm;	12882	struct skl_pipe_wm *sw_wm;
12721	struct skl_ddb_entry hw_ddb_entry, sw_ddb_entry;	12883	struct skl_ddb_entry hw_ddb_entry, sw_ddb_entry;
12722	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	12884	const enum pipe pipe = crtc->pipe;
12723	const enum pipe pipe = intel_crtc->pipe;
12724	int plane, level, max_level = ilk_wm_max_level(dev_priv);	12885	int plane, level, max_level = ilk_wm_max_level(dev_priv);
12725		12886
12726	if (INTEL_GEN(dev_priv) < 9 \|\| !new_state->active)	12887	if (INTEL_GEN(dev_priv) < 9 \|\| !new_crtc_state->base.active)
12727	return;	12888	return;
12728		12889
12729	hw = kzalloc(sizeof(*hw), GFP_KERNEL);	12890	hw = kzalloc(sizeof(*hw), GFP_KERNEL);
12730	if (!hw)	12891	if (!hw)
12731	return;	12892	return;
12732		12893
12733	skl_pipe_wm_get_hw_state(intel_crtc, &hw->wm);	12894	skl_pipe_wm_get_hw_state(crtc, &hw->wm);
12734	sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;	12895	sw_wm = &new_crtc_state->wm.skl.optimal;
12735		12896
12736	skl_pipe_ddb_get_hw_state(intel_crtc, hw->ddb_y, hw->ddb_uv);	12897	skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);
12737		12898
12738	skl_ddb_get_hw_state(dev_priv, &hw->ddb);	12899	skl_ddb_get_hw_state(dev_priv, &hw->ddb);
12739	sw_ddb = &dev_priv->wm.skl_hw.ddb;	12900	sw_ddb = &dev_priv->wm.skl_hw.ddb;
@@ -12781,7 +12942,7 @@ static void verify_wm_state(struct drm_crtc *crtc, · 41 unmodified lines
12781		12942
12782	/* DDB */	12943	/* DDB */
12783	hw_ddb_entry = &hw->ddb_y[plane];	12944	hw_ddb_entry = &hw->ddb_y[plane];
12784	sw_ddb_entry = &to_intel_crtc_state(new_state)->wm.skl.plane_ddb_y[plane];	12945	sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane];
12785		12946
12786	if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {	12947	if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
12787	DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",	12948	DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
@@ -12833,7 +12994,7 @@ static void verify_wm_state(struct drm_crtc *crtc, · 45 unmodified lines
12833		12994
12834	/* DDB */	12995	/* DDB */
12835	hw_ddb_entry = &hw->ddb_y[PLANE_CURSOR];	12996	hw_ddb_entry = &hw->ddb_y[PLANE_CURSOR];
12836	sw_ddb_entry = &to_intel_crtc_state(new_state)->wm.skl.plane_ddb_y[PLANE_CURSOR];	12997	sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR];
12837		12998
12838	if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {	12999	if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
12839	DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",	13000	DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
@@ -12847,23 +13008,22 @@ static void verify_wm_state(struct drm_crtc *crtc, · 7 unmodified lines
12847	}	13008	}
12848		13009
12849	static void	13010	static void
12850	verify_connector_state(struct drm_device *dev,	13011	verify_connector_state(struct intel_atomic_state *state,
12851	struct drm_atomic_state *state,	13012	struct intel_crtc *crtc)
12852	struct drm_crtc *crtc)
12853	{	13013	{
12854	struct drm_connector *connector;	13014	struct drm_connector *connector;
12855	struct drm_connector_state *new_conn_state;	13015	struct drm_connector_state *new_conn_state;
12856	int i;	13016	int i;
12857		13017
12858	for_each_new_connector_in_state(state, connector, new_conn_state, i) {	13018	for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) {
12859	struct drm_encoder *encoder = connector->encoder;	13019	struct drm_encoder *encoder = connector->encoder;
12860	struct drm_crtc_state *crtc_state = NULL;	13020	struct intel_crtc_state *crtc_state = NULL;
12861		13021
12862	if (new_conn_state->crtc != crtc)	13022	if (new_conn_state->crtc != &crtc->base)
12863	continue;	13023	continue;
12864		13024
12865	if (crtc)	13025	if (crtc)
12866	crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);	13026	crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
12867		13027
12868	intel_connector_verify_state(crtc_state, new_conn_state);	13028	intel_connector_verify_state(crtc_state, new_conn_state);
12869		13029
@@ -12873,14 +13033,14 @@ verify_connector_state(struct drm_device *dev, · 3 unmodified lines
12873	}	13033	}
12874		13034
12875	static void	13035	static void
12876	verify_encoder_state(struct drm_device dev, struct drm_atomic_state state)	13036	verify_encoder_state(struct drm_i915_private dev_priv, struct intel_atomic_state state)
12877	{	13037	{
12878	struct intel_encoder *encoder;	13038	struct intel_encoder *encoder;
12879	struct drm_connector *connector;	13039	struct drm_connector *connector;
12880	struct drm_connector_state old_conn_state, new_conn_state;	13040	struct drm_connector_state old_conn_state, new_conn_state;
12881	int i;	13041	int i;
12882		13042
12883	for_each_intel_encoder(dev, encoder) {	13043	for_each_intel_encoder(&dev_priv->drm, encoder) {
12884	bool enabled = false, found = false;	13044	bool enabled = false, found = false;
12885	enum pipe pipe;	13045	enum pipe pipe;
12886		13046
@@ -12888,7 +13048,7 @@ verify_encoder_state(struct drm_device dev, struct drm_atomic_state state) · 1 unmodified line
12888	encoder->base.base.id,	13048	encoder->base.base.id,
12889	encoder->base.name);	13049	encoder->base.name);
12890		13050
12891	for_each_oldnew_connector_in_state(state, connector, old_conn_state,	13051	for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state,
12892	new_conn_state, i) {	13052	new_conn_state, i) {
12893	if (old_conn_state->best_encoder == &encoder->base)	13053	if (old_conn_state->best_encoder == &encoder->base)
12894	found = true;	13054	found = true;
@@ -12922,50 +13082,49 @@ verify_encoder_state(struct drm_device dev, struct drm_atomic_state state) · 27 unmodified lines
12922	}	13082	}
12923		13083
12924	static void	13084	static void
12925	verify_crtc_state(struct drm_crtc *crtc,	13085	verify_crtc_state(struct intel_crtc *crtc,
12926	struct drm_crtc_state *old_crtc_state,	13086	struct intel_crtc_state *old_crtc_state,
12927	struct drm_crtc_state *new_crtc_state)	13087	struct intel_crtc_state *new_crtc_state)
12928	{	13088	{
12929	struct drm_device *dev = crtc->dev;	13089	struct drm_device *dev = crtc->base.dev;
12930	struct drm_i915_private *dev_priv = to_i915(dev);	13090	struct drm_i915_private *dev_priv = to_i915(dev);
12931	struct intel_encoder *encoder;	13091	struct intel_encoder *encoder;
12932	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);	13092	struct intel_crtc_state *pipe_config;
12933	struct intel_crtc_state pipe_config, sw_config;	13093	struct drm_atomic_state *state;
12934	struct drm_atomic_state *old_state;
12935	bool active;	13094	bool active;
12936		13095
12937	old_state = old_crtc_state->state;	13096	state = old_crtc_state->base.state;
12938	__drm_atomic_helper_crtc_destroy_state(old_crtc_state);	13097	__drm_atomic_helper_crtc_destroy_state(&old_crtc_state->base);
12939	pipe_config = to_intel_crtc_state(old_crtc_state);	13098	pipe_config = old_crtc_state;
12940	memset(pipe_config, 0, sizeof(*pipe_config));	13099	memset(pipe_config, 0, sizeof(*pipe_config));
12941	pipe_config->base.crtc = crtc;	13100	pipe_config->base.crtc = &crtc->base;
12942	pipe_config->base.state = old_state;	13101	pipe_config->base.state = state;
12943		13102
12944	DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);	13103	DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.base.id, crtc->base.name);
12945		13104
12946	active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);	13105	active = dev_priv->display.get_pipe_config(crtc, pipe_config);
12947		13106
12948	/* we keep both pipes enabled on 830 */	13107	/* we keep both pipes enabled on 830 */
12949	if (IS_I830(dev_priv))	13108	if (IS_I830(dev_priv))
12950	active = new_crtc_state->active;	13109	active = new_crtc_state->base.active;
12951		13110
12952	I915_STATE_WARN(new_crtc_state->active != active,	13111	I915_STATE_WARN(new_crtc_state->base.active != active,
12953	"crtc active state doesn't match with hw state "	13112	"crtc active state doesn't match with hw state "
12954	"(expected %i, found %i)\n", new_crtc_state->active, active);	13113	"(expected %i, found %i)\n", new_crtc_state->base.active, active);
12955		13114
12956	I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,	13115	I915_STATE_WARN(crtc->active != new_crtc_state->base.active,
12957	"transitional active state does not match atomic hw state "	13116	"transitional active state does not match atomic hw state "
12958	"(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);	13117	"(expected %i, found %i)\n", new_crtc_state->base.active, crtc->active);
12959		13118
12960	for_each_encoder_on_crtc(dev, crtc, encoder) {	13119	for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
12961	enum pipe pipe;	13120	enum pipe pipe;
12962		13121
12963	active = encoder->get_hw_state(encoder, &pipe);	13122	active = encoder->get_hw_state(encoder, &pipe);
12964	I915_STATE_WARN(active != new_crtc_state->active,	13123	I915_STATE_WARN(active != new_crtc_state->base.active,
12965	"[ENCODER:%i] active %i with crtc active %i\n",	13124	"[ENCODER:%i] active %i with crtc active %i\n",
12966	encoder->base.base.id, active, new_crtc_state->active);	13125	encoder->base.base.id, active, new_crtc_state->base.active);
12967		13126
12968	I915_STATE_WARN(active && intel_crtc->pipe != pipe,	13127	I915_STATE_WARN(active && crtc->pipe != pipe,
12969	"Encoder connected to wrong pipe %c\n",	13128	"Encoder connected to wrong pipe %c\n",
12970	pipe_name(pipe));	13129	pipe_name(pipe));
12971		13130
@@ -12975,16 +13134,16 @@ verify_crtc_state(struct drm_crtc *crtc, · 3 unmodified lines
12975		13134
12976	intel_crtc_compute_pixel_rate(pipe_config);	13135	intel_crtc_compute_pixel_rate(pipe_config);
12977		13136
12978	if (!new_crtc_state->active)	13137	if (!new_crtc_state->base.active)
12979	return;	13138	return;
12980		13139
12981	intel_pipe_config_sanity_check(dev_priv, pipe_config);	13140	intel_pipe_config_sanity_check(dev_priv, pipe_config);
12982		13141
12983	sw_config = to_intel_crtc_state(new_crtc_state);	13142	if (!intel_pipe_config_compare(new_crtc_state,
12984	if (!intel_pipe_config_compare(sw_config, pipe_config, false)) {	13143	pipe_config, false)) {
12985	I915_STATE_WARN(1, "pipe state doesn't match!\n");	13144	I915_STATE_WARN(1, "pipe state doesn't match!\n");
12986	intel_dump_pipe_config(pipe_config, NULL, "[hw state]");	13145	intel_dump_pipe_config(pipe_config, NULL, "[hw state]");
12987	intel_dump_pipe_config(sw_config, NULL, "[sw state]");	13146	intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]");
12988	}	13147	}
12989	}	13148	}
12990		13149
@@ -13004,8 +13163,8 @@ intel_verify_planes(struct intel_atomic_state *state) · 13 unmodified lines
13004	static void	13163	static void
13005	verify_single_dpll_state(struct drm_i915_private *dev_priv,	13164	verify_single_dpll_state(struct drm_i915_private *dev_priv,
13006	struct intel_shared_dpll *pll,	13165	struct intel_shared_dpll *pll,
13007	struct drm_crtc *crtc,	13166	struct intel_crtc *crtc,
13008	struct drm_crtc_state *new_state)	13167	struct intel_crtc_state *new_crtc_state)
13009	{	13168	{
13010	struct intel_dpll_hw_state dpll_hw_state;	13169	struct intel_dpll_hw_state dpll_hw_state;
13011	unsigned int crtc_mask;	13170	unsigned int crtc_mask;
@@ -13035,16 +13194,16 @@ verify_single_dpll_state(struct drm_i915_private *dev_priv, · 23 unmodified lines
13035	return;	13194	return;
13036	}	13195	}
13037		13196
13038	crtc_mask = drm_crtc_mask(crtc);	13197	crtc_mask = drm_crtc_mask(&crtc->base);
13039		13198
13040	if (new_state->active)	13199	if (new_crtc_state->base.active)
13041	I915_STATE_WARN(!(pll->active_mask & crtc_mask),	13200	I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13042	"pll active mismatch (expected pipe %c in active mask 0x%02x)\n",	13201	"pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13043	pipe_name(drm_crtc_index(crtc)), pll->active_mask);	13202	pipe_name(drm_crtc_index(&crtc->base)), pll->active_mask);
13044	else	13203	else
13045	I915_STATE_WARN(pll->active_mask & crtc_mask,	13204	I915_STATE_WARN(pll->active_mask & crtc_mask,
13046	"pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",	13205	"pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13047	pipe_name(drm_crtc_index(crtc)), pll->active_mask);	13206	pipe_name(drm_crtc_index(&crtc->base)), pll->active_mask);
13048		13207
13049	I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),	13208	I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
13050	"pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",	13209	"pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
@@ -13057,51 +13216,47 @@ verify_single_dpll_state(struct drm_i915_private *dev_priv, · 6 unmodified lines
13057	}	13216	}
13058		13217
13059	static void	13218	static void
13060	verify_shared_dpll_state(struct drm_device dev, struct drm_crtc crtc,	13219	verify_shared_dpll_state(struct intel_crtc *crtc,
13061	struct drm_crtc_state *old_crtc_state,	13220	struct intel_crtc_state *old_crtc_state,
13062	struct drm_crtc_state *new_crtc_state)	13221	struct intel_crtc_state *new_crtc_state)
13063	{	13222	{
13064	struct drm_i915_private *dev_priv = to_i915(dev);	13223	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13065	struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
13066	struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
13067		13224
13068	if (new_state->shared_dpll)	13225	if (new_crtc_state->shared_dpll)
13069	verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);	13226	verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state);
13070		13227
13071	if (old_state->shared_dpll &&	13228	if (old_crtc_state->shared_dpll &&
13072	old_state->shared_dpll != new_state->shared_dpll) {	13229	old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) {
13073	unsigned int crtc_mask = drm_crtc_mask(crtc);	13230	unsigned int crtc_mask = drm_crtc_mask(&crtc->base);
13074	struct intel_shared_dpll *pll = old_state->shared_dpll;	13231	struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
13075		13232
13076	I915_STATE_WARN(pll->active_mask & crtc_mask,	13233	I915_STATE_WARN(pll->active_mask & crtc_mask,
13077	"pll active mismatch (didn't expect pipe %c in active mask)\n",	13234	"pll active mismatch (didn't expect pipe %c in active mask)\n",
13078	pipe_name(drm_crtc_index(crtc)));	13235	pipe_name(drm_crtc_index(&crtc->base)));
13079	I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,	13236	I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
13080	"pll enabled crtcs mismatch (found %x in enabled mask)\n",	13237	"pll enabled crtcs mismatch (found %x in enabled mask)\n",
13081	pipe_name(drm_crtc_index(crtc)));	13238	pipe_name(drm_crtc_index(&crtc->base)));
13082	}	13239	}
13083	}	13240	}
13084		13241
13085	static void	13242	static void
13086	intel_modeset_verify_crtc(struct drm_crtc *crtc,	13243	intel_modeset_verify_crtc(struct intel_crtc *crtc,
13087	struct drm_atomic_state *state,	13244	struct intel_atomic_state *state,
13088	struct drm_crtc_state *old_state,	13245	struct intel_crtc_state *old_crtc_state,
13089	struct drm_crtc_state *new_state)	13246	struct intel_crtc_state *new_crtc_state)
13090	{	13247	{
13091	if (!needs_modeset(new_state) &&	13248	if (!needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe)
13092	!to_intel_crtc_state(new_state)->update_pipe)
13093	return;	13249	return;
13094		13250
13095	verify_wm_state(crtc, new_state);	13251	verify_wm_state(crtc, new_crtc_state);
13096	verify_connector_state(crtc->dev, state, crtc);	13252	verify_connector_state(state, crtc);
13097	verify_crtc_state(crtc, old_state, new_state);	13253	verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
13098	verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);	13254	verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state);
13099	}	13255	}
13100		13256
13101	static void	13257	static void
13102	verify_disabled_dpll_state(struct drm_device *dev)	13258	verify_disabled_dpll_state(struct drm_i915_private *dev_priv)
13103	{	13259	{
13104	struct drm_i915_private *dev_priv = to_i915(dev);
13105	int i;	13260	int i;
13106		13261
13107	for (i = 0; i < dev_priv->num_shared_dpll; i++)	13262	for (i = 0; i < dev_priv->num_shared_dpll; i++)
@@ -13109,12 +13264,12 @@ verify_disabled_dpll_state(struct drm_device *dev) · 1 unmodified line
13109	}	13264	}
13110		13265
13111	static void	13266	static void
13112	intel_modeset_verify_disabled(struct drm_device *dev,	13267	intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
13113	struct drm_atomic_state *state)	13268	struct intel_atomic_state *state)
13114	{	13269	{
13115	verify_encoder_state(dev, state);	13270	verify_encoder_state(dev_priv, state);
13116	verify_connector_state(dev, state, NULL);	13271	verify_connector_state(state, NULL);
13117	verify_disabled_dpll_state(dev);	13272	verify_disabled_dpll_state(dev_priv);
13118	}	13273	}
13119		13274
13120	static void update_scanline_offset(const struct intel_crtc_state *crtc_state)	13275	static void update_scanline_offset(const struct intel_crtc_state *crtc_state)
@@ -13168,27 +13323,18 @@ static void update_scanline_offset(const struct intel_crtc_state *crtc_state) · 47 unmodified lines
13168	static void intel_modeset_clear_plls(struct intel_atomic_state *state)	13323	static void intel_modeset_clear_plls(struct intel_atomic_state *state)
13169	{	13324	{
13170	struct drm_i915_private *dev_priv = to_i915(state->base.dev);	13325	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
13171	struct intel_crtc_state old_crtc_state, new_crtc_state;	13326	struct intel_crtc_state *new_crtc_state;
13172	struct intel_crtc *crtc;	13327	struct intel_crtc *crtc;
13173	int i;	13328	int i;
13174		13329
13175	if (!dev_priv->display.crtc_compute_clock)	13330	if (!dev_priv->display.crtc_compute_clock)
13176	return;	13331	return;
13177		13332
13178	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,	13333	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
13179	new_crtc_state, i) {	13334	if (!needs_modeset(new_crtc_state))
13180	struct intel_shared_dpll *old_dpll =
13181	old_crtc_state->shared_dpll;
13182
13183	if (!needs_modeset(&new_crtc_state->base))
13184	continue;
13185
13186	new_crtc_state->shared_dpll = NULL;
13187
13188	if (!old_dpll)
13189	continue;	13335	continue;
13190		13336
13191	intel_release_shared_dpll(old_dpll, crtc, &state->base);	13337	intel_release_shared_dplls(state, crtc);
13192	}	13338	}
13193	}	13339	}
13194		13340
@@ -13210,7 +13356,7 @@ static int haswell_mode_set_planes_workaround(struct intel_atomic_state *state) · 15 unmodified lines
13210	/* look at all crtc's that are going to be enabled in during modeset */	13356	/* look at all crtc's that are going to be enabled in during modeset */
13211	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {	13357	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
13212	if (!crtc_state->base.active \|\|	13358	if (!crtc_state->base.active \|\|
13213	!needs_modeset(&crtc_state->base))	13359	!needs_modeset(crtc_state))
13214	continue;	13360	continue;
13215		13361
13216	if (first_crtc_state) {	13362	if (first_crtc_state) {
@@ -13235,7 +13381,7 @@ static int haswell_mode_set_planes_workaround(struct intel_atomic_state *state) · 18 unmodified lines
13235	crtc_state->hsw_workaround_pipe = INVALID_PIPE;	13381	crtc_state->hsw_workaround_pipe = INVALID_PIPE;
13236		13382
13237	if (!crtc_state->base.active \|\|	13383	if (!crtc_state->base.active \|\|
13238	needs_modeset(&crtc_state->base))	13384	needs_modeset(crtc_state))
13239	continue;	13385	continue;
13240		13386
13241	/* 2 or more enabled crtcs means no need for w/a */	13387	/* 2 or more enabled crtcs means no need for w/a */
@@ -13253,15 +13399,16 @@ static int haswell_mode_set_planes_workaround(struct intel_atomic_state *state) · 11 unmodified lines
13253	return 0;	13399	return 0;
13254	}	13400	}
13255		13401
13256	static int intel_lock_all_pipes(struct drm_atomic_state *state)	13402	static int intel_lock_all_pipes(struct intel_atomic_state *state)
13257	{	13403	{
13258	struct drm_crtc *crtc;	13404	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
		13405	struct intel_crtc *crtc;
13259		13406
13260	/* Add all pipes to the state */	13407	/* Add all pipes to the state */
13261	for_each_crtc(state->dev, crtc) {	13408	for_each_intel_crtc(&dev_priv->drm, crtc) {
13262	struct drm_crtc_state *crtc_state;	13409	struct intel_crtc_state *crtc_state;
13263		13410
13264	crtc_state = drm_atomic_get_crtc_state(state, crtc);	13411	crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
13265	if (IS_ERR(crtc_state))	13412	if (IS_ERR(crtc_state))
13266	return PTR_ERR(crtc_state);	13413	return PTR_ERR(crtc_state);
13267	}	13414	}
@@ -13269,32 +13416,35 @@ static int intel_lock_all_pipes(struct drm_atomic_state *state) · 1 unmodified line
13269	return 0;	13416	return 0;
13270	}	13417	}
13271		13418
13272	static int intel_modeset_all_pipes(struct drm_atomic_state *state)	13419	static int intel_modeset_all_pipes(struct intel_atomic_state *state)
13273	{	13420	{
13274	struct drm_crtc *crtc;	13421	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
		13422	struct intel_crtc *crtc;
13275		13423
13276	/*	13424	/*
13277	* Add all pipes to the state, and force	13425	* Add all pipes to the state, and force
13278	* a modeset on all the active ones.	13426	* a modeset on all the active ones.
13279	*/	13427	*/
13280	for_each_crtc(state->dev, crtc) {	13428	for_each_intel_crtc(&dev_priv->drm, crtc) {
13281	struct drm_crtc_state *crtc_state;	13429	struct intel_crtc_state *crtc_state;
13282	int ret;	13430	int ret;
13283		13431
13284	crtc_state = drm_atomic_get_crtc_state(state, crtc);	13432	crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
13285	if (IS_ERR(crtc_state))	13433	if (IS_ERR(crtc_state))
13286	return PTR_ERR(crtc_state);	13434	return PTR_ERR(crtc_state);
13287		13435
13288	if (!crtc_state->active \|\| needs_modeset(crtc_state))	13436	if (!crtc_state->base.active \|\| needs_modeset(crtc_state))
13289	continue;	13437	continue;
13290		13438
13291	crtc_state->mode_changed = true;	13439	crtc_state->base.mode_changed = true;
13292		13440
13293	ret = drm_atomic_add_affected_connectors(state, crtc);	13441	ret = drm_atomic_add_affected_connectors(&state->base,
		13442	&crtc->base);
13294	if (ret)	13443	if (ret)
13295	return ret;	13444	return ret;
13296		13445
13297	ret = drm_atomic_add_affected_planes(state, crtc);	13446	ret = drm_atomic_add_affected_planes(&state->base,
		13447	&crtc->base);
13298	if (ret)	13448	if (ret)
13299	return ret;	13449	return ret;
13300	}	13450	}
@@ -13356,18 +13506,18 @@ static int intel_modeset_checks(struct intel_atomic_state *state) · 55 unmodified lines
13356	*/	13506	*/
13357	if (intel_cdclk_changed(&dev_priv->cdclk.logical,	13507	if (intel_cdclk_changed(&dev_priv->cdclk.logical,
13358	&state->cdclk.logical)) {	13508	&state->cdclk.logical)) {
13359	ret = intel_lock_all_pipes(&state->base);	13509	ret = intel_lock_all_pipes(state);
13360	if (ret < 0)	13510	if (ret < 0)
13361	return ret;	13511	return ret;
13362	}	13512	}
13363		13513
13364	if (is_power_of_2(state->active_crtcs)) {	13514	if (is_power_of_2(state->active_crtcs)) {
13365	struct drm_crtc *crtc;	13515	struct intel_crtc *crtc;
13366	struct drm_crtc_state *crtc_state;	13516	struct intel_crtc_state *crtc_state;
13367		13517
13368	pipe = ilog2(state->active_crtcs);	13518	pipe = ilog2(state->active_crtcs);
13369	crtc = &intel_get_crtc_for_pipe(dev_priv, pipe)->base;	13519	crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
13370	crtc_state = drm_atomic_get_new_crtc_state(&state->base, crtc);	13520	crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
13371	if (crtc_state && needs_modeset(crtc_state))	13521	if (crtc_state && needs_modeset(crtc_state))
13372	pipe = INVALID_PIPE;	13522	pipe = INVALID_PIPE;
13373	} else {	13523	} else {
@@ -13379,14 +13529,14 @@ static int intel_modeset_checks(struct intel_atomic_state *state) · 5 unmodified lines
13379	intel_cdclk_needs_cd2x_update(dev_priv,	13529	intel_cdclk_needs_cd2x_update(dev_priv,
13380	&dev_priv->cdclk.actual,	13530	&dev_priv->cdclk.actual,
13381	&state->cdclk.actual)) {	13531	&state->cdclk.actual)) {
13382	ret = intel_lock_all_pipes(&state->base);	13532	ret = intel_lock_all_pipes(state);
13383	if (ret < 0)	13533	if (ret < 0)
13384	return ret;	13534	return ret;
13385		13535
13386	state->cdclk.pipe = pipe;	13536	state->cdclk.pipe = pipe;
13387	} else if (intel_cdclk_needs_modeset(&dev_priv->cdclk.actual,	13537	} else if (intel_cdclk_needs_modeset(&dev_priv->cdclk.actual,
13388	&state->cdclk.actual)) {	13538	&state->cdclk.actual)) {
13389	ret = intel_modeset_all_pipes(&state->base);	13539	ret = intel_modeset_all_pipes(state);
13390	if (ret < 0)	13540	if (ret < 0)
13391	return ret;	13541	return ret;
13392		13542
@@ -13478,7 +13628,7 @@ static int intel_atomic_check(struct drm_device *dev, · 85 unmodified lines
13478		13628
13479	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,	13629	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
13480	new_crtc_state, i) {	13630	new_crtc_state, i) {
13481	if (!needs_modeset(&new_crtc_state->base))	13631	if (!needs_modeset(new_crtc_state))
13482	continue;	13632	continue;
13483		13633
13484	if (!new_crtc_state->base.enable) {	13634	if (!new_crtc_state->base.enable) {
@@ -13492,7 +13642,7 @@ static int intel_atomic_check(struct drm_device *dev, · 7 unmodified lines
13492		13642
13493	intel_crtc_check_fastset(old_crtc_state, new_crtc_state);	13643	intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
13494		13644
13495	if (needs_modeset(&new_crtc_state->base))	13645	if (needs_modeset(new_crtc_state))
13496	any_ms = true;	13646	any_ms = true;
13497	}	13647	}
13498		13648
@@ -13527,12 +13677,12 @@ static int intel_atomic_check(struct drm_device *dev, · 28 unmodified lines
13527		13677
13528	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,	13678	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
13529	new_crtc_state, i) {	13679	new_crtc_state, i) {
13530	if (!needs_modeset(&new_crtc_state->base) &&	13680	if (!needs_modeset(new_crtc_state) &&
13531	!new_crtc_state->update_pipe)	13681	!new_crtc_state->update_pipe)
13532	continue;	13682	continue;
13533		13683
13534	intel_dump_pipe_config(new_crtc_state, state,	13684	intel_dump_pipe_config(new_crtc_state, state,
13535	needs_modeset(&new_crtc_state->base) ?	13685	needs_modeset(new_crtc_state) ?
13536	"[modeset]" : "[fastset]");	13686	"[modeset]" : "[fastset]");
13537	}	13687	}
13538		13688
@@ -13553,10 +13703,10 @@ static int intel_atomic_check(struct drm_device *dev, · 14 unmodified lines
13553	return ret;	13703	return ret;
13554	}	13704	}
13555		13705
13556	static int intel_atomic_prepare_commit(struct drm_device *dev,	13706	static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
13557	struct drm_atomic_state *state)
13558	{	13707	{
13559	return drm_atomic_helper_prepare_planes(dev, state);	13708	return drm_atomic_helper_prepare_planes(state->base.dev,
		13709	&state->base);
13560	}	13710	}
13561		13711
13562	u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)	13712	u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
@@ -13567,60 +13717,57 @@ u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc) · 4 unmodified lines
13567	if (!vblank->max_vblank_count)	13717	if (!vblank->max_vblank_count)
13568	return (u32)drm_crtc_accurate_vblank_count(&crtc->base);	13718	return (u32)drm_crtc_accurate_vblank_count(&crtc->base);
13569		13719
13570	return dev->driver->get_vblank_counter(dev, crtc->pipe);	13720	return crtc->base.funcs->get_vblank_counter(&crtc->base);
13571	}	13721	}
13572		13722
13573	static void intel_update_crtc(struct drm_crtc *crtc,	13723	static void intel_update_crtc(struct intel_crtc *crtc,
13574	struct drm_atomic_state *state,	13724	struct intel_atomic_state *state,
13575	struct drm_crtc_state *old_crtc_state,	13725	struct intel_crtc_state *old_crtc_state,
13576	struct drm_crtc_state *new_crtc_state)	13726	struct intel_crtc_state *new_crtc_state)
13577	{	13727	{
13578	struct drm_device *dev = crtc->dev;	13728	struct drm_device *dev = state->base.dev;
13579	struct drm_i915_private *dev_priv = to_i915(dev);	13729	struct drm_i915_private *dev_priv = to_i915(dev);
13580	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13581	struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
13582	bool modeset = needs_modeset(new_crtc_state);	13730	bool modeset = needs_modeset(new_crtc_state);
13583	struct intel_plane_state *new_plane_state =	13731	struct intel_plane_state *new_plane_state =
13584	intel_atomic_get_new_plane_state(to_intel_atomic_state(state),	13732	intel_atomic_get_new_plane_state(state,
13585	to_intel_plane(crtc->primary));	13733	to_intel_plane(crtc->base.primary));
13586		13734
13587	if (modeset) {	13735	if (modeset) {
13588	update_scanline_offset(pipe_config);	13736	update_scanline_offset(new_crtc_state);
13589	dev_priv->display.crtc_enable(pipe_config, state);	13737	dev_priv->display.crtc_enable(new_crtc_state, state);
13590		13738
13591	/* vblanks work again, re-enable pipe CRC. */	13739	/* vblanks work again, re-enable pipe CRC. */
13592	intel_crtc_enable_pipe_crc(intel_crtc);	13740	intel_crtc_enable_pipe_crc(crtc);
13593	} else {	13741	} else {
13594	intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),	13742	intel_pre_plane_update(old_crtc_state, new_crtc_state);
13595	pipe_config);
13596		13743
13597	if (pipe_config->update_pipe)	13744	if (new_crtc_state->update_pipe)
13598	intel_encoders_update_pipe(crtc, pipe_config, state);	13745	intel_encoders_update_pipe(crtc, new_crtc_state, state);
13599	}	13746	}
13600		13747
13601	if (pipe_config->update_pipe && !pipe_config->enable_fbc)	13748	if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
13602	intel_fbc_disable(intel_crtc);	13749	intel_fbc_disable(crtc);
13603	else if (new_plane_state)	13750	else if (new_plane_state)
13604	intel_fbc_enable(intel_crtc, pipe_config, new_plane_state);	13751	intel_fbc_enable(crtc, new_crtc_state, new_plane_state);
13605		13752
13606	intel_begin_crtc_commit(to_intel_atomic_state(state), intel_crtc);	13753	intel_begin_crtc_commit(state, crtc);
13607		13754
13608	if (INTEL_GEN(dev_priv) >= 9)	13755	if (INTEL_GEN(dev_priv) >= 9)
13609	skl_update_planes_on_crtc(to_intel_atomic_state(state), intel_crtc);	13756	skl_update_planes_on_crtc(state, crtc);
13610	else	13757	else
13611	i9xx_update_planes_on_crtc(to_intel_atomic_state(state), intel_crtc);	13758	i9xx_update_planes_on_crtc(state, crtc);
13612		13759
13613	intel_finish_crtc_commit(to_intel_atomic_state(state), intel_crtc);	13760	intel_finish_crtc_commit(state, crtc);
13614	}	13761	}
13615		13762
13616	static void intel_update_crtcs(struct drm_atomic_state *state)	13763	static void intel_update_crtcs(struct intel_atomic_state *state)
13617	{	13764	{
13618	struct drm_crtc *crtc;	13765	struct intel_crtc *crtc;
13619	struct drm_crtc_state old_crtc_state, new_crtc_state;	13766	struct intel_crtc_state old_crtc_state, new_crtc_state;
13620	int i;	13767	int i;
13621		13768
13622	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {	13769	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
13623	if (!new_crtc_state->active)	13770	if (!new_crtc_state->base.active)
13624	continue;	13771	continue;
13625		13772
13626	intel_update_crtc(crtc, state, old_crtc_state,	13773	intel_update_crtc(crtc, state, old_crtc_state,
@@ -13628,26 +13775,23 @@ static void intel_update_crtcs(struct drm_atomic_state *state) · 1 unmodified line
13628	}	13775	}
13629	}	13776	}
13630		13777
13631	static void skl_update_crtcs(struct drm_atomic_state *state)	13778	static void skl_update_crtcs(struct intel_atomic_state *state)
13632	{	13779	{
13633	struct drm_i915_private *dev_priv = to_i915(state->dev);	13780	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
13634	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);	13781	struct intel_crtc *crtc;
13635	struct drm_crtc *crtc;	13782	struct intel_crtc_state old_crtc_state, new_crtc_state;
13636	struct intel_crtc *intel_crtc;
13637	struct drm_crtc_state old_crtc_state, new_crtc_state;
13638	struct intel_crtc_state *cstate;
13639	unsigned int updated = 0;	13783	unsigned int updated = 0;
13640	bool progress;	13784	bool progress;
13641	enum pipe pipe;	13785	enum pipe pipe;
13642	int i;	13786	int i;
13643	u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;	13787	u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
13644	u8 required_slices = intel_state->wm_results.ddb.enabled_slices;	13788	u8 required_slices = state->wm_results.ddb.enabled_slices;
13645	struct skl_ddb_entry entries[I915_MAX_PIPES] = {};	13789	struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
13646		13790
13647	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)	13791	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
13648	/* ignore allocations for crtc's that have been turned off. */	13792	/* ignore allocations for crtc's that have been turned off. */
13649	if (new_crtc_state->active)	13793	if (new_crtc_state->base.active)
13650	entries[i] = to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;	13794	entries[i] = old_crtc_state->wm.skl.ddb;
13651		13795
13652	/* If 2nd DBuf slice required, enable it here */	13796	/* If 2nd DBuf slice required, enable it here */
13653	if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)	13797	if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
@@ -13662,24 +13806,22 @@ static void skl_update_crtcs(struct drm_atomic_state *state) · 8 unmodified lines
13662	do {	13806	do {
13663	progress = false;	13807	progress = false;
13664		13808
13665	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {	13809	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
13666	bool vbl_wait = false;	13810	bool vbl_wait = false;
13667	unsigned int cmask = drm_crtc_mask(crtc);	13811	unsigned int cmask = drm_crtc_mask(&crtc->base);
13668		13812
13669	intel_crtc = to_intel_crtc(crtc);	13813	pipe = crtc->pipe;
13670	cstate = to_intel_crtc_state(new_crtc_state);
13671	pipe = intel_crtc->pipe;
13672		13814
13673	if (updated & cmask \|\| !cstate->base.active)	13815	if (updated & cmask \|\| !new_crtc_state->base.active)
13674	continue;	13816	continue;
13675		13817
13676	if (skl_ddb_allocation_overlaps(&cstate->wm.skl.ddb,	13818	if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
13677	entries,	13819	entries,
13678	INTEL_INFO(dev_priv)->num_pipes, i))	13820	INTEL_INFO(dev_priv)->num_pipes, i))
13679	continue;	13821	continue;
13680		13822
13681	updated \|= cmask;	13823	updated \|= cmask;
13682	entries[i] = cstate->wm.skl.ddb;	13824	entries[i] = new_crtc_state->wm.skl.ddb;
13683		13825
13684	/*	13826	/*
13685	* If this is an already active pipe, it's DDB changed,	13827	* If this is an already active pipe, it's DDB changed,
@@ -13687,10 +13829,10 @@ static void skl_update_crtcs(struct drm_atomic_state *state) · 1 unmodified line
13687	* then we need to wait for a vblank to pass for the	13829	* then we need to wait for a vblank to pass for the
13688	* new ddb allocation to take effect.	13830	* new ddb allocation to take effect.
13689	*/	13831	*/
13690	if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,	13832	if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
13691	&to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&	13833	&old_crtc_state->wm.skl.ddb) &&
13692	!new_crtc_state->active_changed &&	13834	!new_crtc_state->base.active_changed &&
13693	intel_state->wm_results.dirty_pipes != updated)	13835	state->wm_results.dirty_pipes != updated)
13694	vbl_wait = true;	13836	vbl_wait = true;
13695		13837
13696	intel_update_crtc(crtc, state, old_crtc_state,	13838	intel_update_crtc(crtc, state, old_crtc_state,
@@ -13736,18 +13878,21 @@ static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_stat · 39 unmodified lines
13736	for (;;) {	13878	for (;;) {
13737	prepare_to_wait(&intel_state->commit_ready.wait,	13879	prepare_to_wait(&intel_state->commit_ready.wait,
13738	&wait_fence, TASK_UNINTERRUPTIBLE);	13880	&wait_fence, TASK_UNINTERRUPTIBLE);
13739	prepare_to_wait(&dev_priv->gpu_error.wait_queue,	13881	prepare_to_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
		13882	I915_RESET_MODESET),
13740	&wait_reset, TASK_UNINTERRUPTIBLE);	13883	&wait_reset, TASK_UNINTERRUPTIBLE);
13741		13884
13742		13885
13743	if (i915_sw_fence_done(&intel_state->commit_ready)	13886	if (i915_sw_fence_done(&intel_state->commit_ready) \|\|
13744	\|\| test_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags))	13887	test_bit(I915_RESET_MODESET, &dev_priv->gt.reset.flags))
13745	break;	13888	break;
13746		13889
13747	schedule();	13890	schedule();
13748	}	13891	}
13749	finish_wait(&intel_state->commit_ready.wait, &wait_fence);	13892	finish_wait(&intel_state->commit_ready.wait, &wait_fence);
13750	finish_wait(&dev_priv->gpu_error.wait_queue, &wait_reset);	13893	finish_wait(bit_waitqueue(&dev_priv->gt.reset.flags,
		13894	I915_RESET_MODESET),
		13895	&wait_reset);
13751	}	13896	}
13752		13897
13753	static void intel_atomic_cleanup_work(struct work_struct *work)	13898	static void intel_atomic_cleanup_work(struct work_struct *work)
@@ -13763,57 +13908,49 @@ static void intel_atomic_cleanup_work(struct work_struct *work) · 9 unmodified lines
13763	intel_atomic_helper_free_state(i915);	13908	intel_atomic_helper_free_state(i915);
13764	}	13909	}
13765		13910
13766	static void intel_atomic_commit_tail(struct drm_atomic_state *state)	13911	static void intel_atomic_commit_tail(struct intel_atomic_state *state)
13767	{	13912	{
13768	struct drm_device *dev = state->dev;	13913	struct drm_device *dev = state->base.dev;
13769	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13770	struct drm_i915_private *dev_priv = to_i915(dev);	13914	struct drm_i915_private *dev_priv = to_i915(dev);
13771	struct drm_crtc_state old_crtc_state, new_crtc_state;	13915	struct intel_crtc_state new_crtc_state, old_crtc_state;
13772	struct intel_crtc_state new_intel_crtc_state, old_intel_crtc_state;	13916	struct intel_crtc *crtc;
13773	struct drm_crtc *crtc;
13774	struct intel_crtc *intel_crtc;
13775	u64 put_domains[I915_MAX_PIPES] = {};	13917	u64 put_domains[I915_MAX_PIPES] = {};
13776	intel_wakeref_t wakeref = 0;	13918	intel_wakeref_t wakeref = 0;
13777	int i;	13919	int i;
13778		13920
13779	intel_atomic_commit_fence_wait(intel_state);	13921	intel_atomic_commit_fence_wait(state);
13780		13922
13781	drm_atomic_helper_wait_for_dependencies(state);	13923	drm_atomic_helper_wait_for_dependencies(&state->base);
13782		13924
13783	if (intel_state->modeset)	13925	if (state->modeset)
13784	wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);	13926	wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13785		13927
13786	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {	13928	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
13787	old_intel_crtc_state = to_intel_crtc_state(old_crtc_state);
13788	new_intel_crtc_state = to_intel_crtc_state(new_crtc_state);
13789	intel_crtc = to_intel_crtc(crtc);
13790
13791	if (needs_modeset(new_crtc_state) \|\|	13929	if (needs_modeset(new_crtc_state) \|\|
13792	to_intel_crtc_state(new_crtc_state)->update_pipe) {	13930	new_crtc_state->update_pipe) {
13793		13931
13794	put_domains[intel_crtc->pipe] =	13932	put_domains[crtc->pipe] =
13795	modeset_get_crtc_power_domains(crtc,	13933	modeset_get_crtc_power_domains(new_crtc_state);
13796	new_intel_crtc_state);
13797	}	13934	}
13798		13935
13799	if (!needs_modeset(new_crtc_state))	13936	if (!needs_modeset(new_crtc_state))
13800	continue;	13937	continue;
13801		13938
13802	intel_pre_plane_update(old_intel_crtc_state, new_intel_crtc_state);	13939	intel_pre_plane_update(old_crtc_state, new_crtc_state);
13803		13940
13804	if (old_crtc_state->active) {	13941	if (old_crtc_state->base.active) {
13805	intel_crtc_disable_planes(intel_state, intel_crtc);	13942	intel_crtc_disable_planes(state, crtc);
13806		13943
13807	/*	13944	/*
13808	* We need to disable pipe CRC before disabling the pipe,	13945	* We need to disable pipe CRC before disabling the pipe,
13809	* or we race against vblank off.	13946	* or we race against vblank off.
13810	*/	13947	*/
13811	intel_crtc_disable_pipe_crc(intel_crtc);	13948	intel_crtc_disable_pipe_crc(crtc);
13812		13949
13813	dev_priv->display.crtc_disable(old_intel_crtc_state, state);	13950	dev_priv->display.crtc_disable(old_crtc_state, state);
13814	intel_crtc->active = false;	13951	crtc->active = false;
13815	intel_fbc_disable(intel_crtc);	13952	intel_fbc_disable(crtc);
13816	intel_disable_shared_dpll(old_intel_crtc_state);	13953	intel_disable_shared_dpll(old_crtc_state);
13817		13954
13818	/*	13955	/*
13819	* Underruns don't always raise	13956	* Underruns don't always raise
@@ -13823,25 +13960,25 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state) · 3 unmodified lines
13823	intel_check_pch_fifo_underruns(dev_priv);	13960	intel_check_pch_fifo_underruns(dev_priv);
13824		13961
13825	/* FIXME unify this for all platforms */	13962	/* FIXME unify this for all platforms */
13826	if (!new_crtc_state->active &&	13963	if (!new_crtc_state->base.active &&
13827	!HAS_GMCH(dev_priv) &&	13964	!HAS_GMCH(dev_priv) &&
13828	dev_priv->display.initial_watermarks)	13965	dev_priv->display.initial_watermarks)
13829	dev_priv->display.initial_watermarks(intel_state,	13966	dev_priv->display.initial_watermarks(state,
13830	new_intel_crtc_state);	13967	new_crtc_state);
13831	}	13968	}
13832	}	13969	}
13833		13970
13834	/* FIXME: Eventually get rid of our intel_crtc->config pointer */	13971	/* FIXME: Eventually get rid of our crtc->config pointer */
13835	for_each_new_crtc_in_state(state, crtc, new_crtc_state, i)	13972	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
13836	to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state);	13973	crtc->config = new_crtc_state;
13837		13974
13838	if (intel_state->modeset) {	13975	if (state->modeset) {
13839	drm_atomic_helper_update_legacy_modeset_state(state->dev, state);	13976	drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
13840		13977
13841	intel_set_cdclk_pre_plane_update(dev_priv,	13978	intel_set_cdclk_pre_plane_update(dev_priv,
13842	&intel_state->cdclk.actual,	13979	&state->cdclk.actual,
13843	&dev_priv->cdclk.actual,	13980	&dev_priv->cdclk.actual,
13844	intel_state->cdclk.pipe);	13981	state->cdclk.pipe);
13845		13982
13846	/*	13983	/*
13847	* SKL workaround: bspec recommends we disable the SAGV when we	13984	* SKL workaround: bspec recommends we disable the SAGV when we
@@ -13850,31 +13987,37 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state) · 2 unmodified lines
13850	if (!intel_can_enable_sagv(state))	13987	if (!intel_can_enable_sagv(state))
13851	intel_disable_sagv(dev_priv);	13988	intel_disable_sagv(dev_priv);
13852		13989
13853	intel_modeset_verify_disabled(dev, state);	13990	intel_modeset_verify_disabled(dev_priv, state);
13854	}	13991	}
13855		13992
13856	/* Complete the events for pipes that have now been disabled */	13993	/* Complete the events for pipes that have now been disabled */
13857	for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {	13994	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
13858	bool modeset = needs_modeset(new_crtc_state);	13995	bool modeset = needs_modeset(new_crtc_state);
13859		13996
13860	/* Complete events for now disable pipes here. */	13997	/* Complete events for now disable pipes here. */
13861	if (modeset && !new_crtc_state->active && new_crtc_state->event) {	13998	if (modeset && !new_crtc_state->base.active && new_crtc_state->base.event) {
13862	spin_lock_irq(&dev->event_lock);	13999	spin_lock_irq(&dev->event_lock);
13863	drm_crtc_send_vblank_event(crtc, new_crtc_state->event);	14000	drm_crtc_send_vblank_event(&crtc->base, new_crtc_state->base.event);
13864	spin_unlock_irq(&dev->event_lock);	14001	spin_unlock_irq(&dev->event_lock);
13865		14002
13866	new_crtc_state->event = NULL;	14003	new_crtc_state->base.event = NULL;
13867	}	14004	}
13868	}	14005	}
13869		14006
		14007	if (state->modeset)
		14008	intel_encoders_update_prepare(state);
		14009
13870	/* Now enable the clocks, plane, pipe, and connectors that we set up. */	14010	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
13871	dev_priv->display.update_crtcs(state);	14011	dev_priv->display.update_crtcs(state);
13872		14012
13873	if (intel_state->modeset)	14013	if (state->modeset) {
		14014	intel_encoders_update_complete(state);
		14015
13874	intel_set_cdclk_post_plane_update(dev_priv,	14016	intel_set_cdclk_post_plane_update(dev_priv,
13875	&intel_state->cdclk.actual,	14017	&state->cdclk.actual,
13876	&dev_priv->cdclk.actual,	14018	&dev_priv->cdclk.actual,
13877	intel_state->cdclk.pipe);	14019	state->cdclk.pipe);
		14020	}
13878		14021
13879	/* FIXME: We should call drm_atomic_helper_commit_hw_done() here	14022	/* FIXME: We should call drm_atomic_helper_commit_hw_done() here
13880	* already, but still need the state for the delayed optimization. To	14023	* already, but still need the state for the delayed optimization. To
@@ -13885,16 +14028,14 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state) · 4 unmodified lines
13885	* - switch over to the vblank wait helper in the core after that since	14028	* - switch over to the vblank wait helper in the core after that since
13886	* we don't need out special handling any more.	14029	* we don't need out special handling any more.
13887	*/	14030	*/
13888	drm_atomic_helper_wait_for_flip_done(dev, state);	14031	drm_atomic_helper_wait_for_flip_done(dev, &state->base);
13889		14032
13890	for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {	14033	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
13891	new_intel_crtc_state = to_intel_crtc_state(new_crtc_state);	14034	if (new_crtc_state->base.active &&
13892
13893	if (new_crtc_state->active &&
13894	!needs_modeset(new_crtc_state) &&	14035	!needs_modeset(new_crtc_state) &&
13895	(new_intel_crtc_state->base.color_mgmt_changed \|\|	14036	(new_crtc_state->base.color_mgmt_changed \|\|
13896	new_intel_crtc_state->update_pipe))	14037	new_crtc_state->update_pipe))
13897	intel_color_load_luts(new_intel_crtc_state);	14038	intel_color_load_luts(new_crtc_state);
13898	}	14039	}
13899		14040
13900	/*	14041	/*
@@ -13904,16 +14045,14 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state) · 3 unmodified lines
13904	*	14045	*
13905	* TODO: Move this (and other cleanup) to an async worker eventually.	14046	* TODO: Move this (and other cleanup) to an async worker eventually.
13906	*/	14047	*/
13907	for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {	14048	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
13908	new_intel_crtc_state = to_intel_crtc_state(new_crtc_state);
13909
13910	if (dev_priv->display.optimize_watermarks)	14049	if (dev_priv->display.optimize_watermarks)
13911	dev_priv->display.optimize_watermarks(intel_state,	14050	dev_priv->display.optimize_watermarks(state,
13912	new_intel_crtc_state);	14051	new_crtc_state);
13913	}	14052	}
13914		14053
13915	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {	14054	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
13916	intel_post_plane_update(to_intel_crtc_state(old_crtc_state));	14055	intel_post_plane_update(old_crtc_state);
13917		14056
13918	if (put_domains[i])	14057	if (put_domains[i])
13919	modeset_put_power_domains(dev_priv, put_domains[i]);	14058	modeset_put_power_domains(dev_priv, put_domains[i]);
@@ -13921,15 +14060,15 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state) · 1 unmodified line
13921	intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);	14060	intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
13922	}	14061	}
13923		14062
13924	if (intel_state->modeset)	14063	if (state->modeset)
13925	intel_verify_planes(intel_state);	14064	intel_verify_planes(state);
13926		14065
13927	if (intel_state->modeset && intel_can_enable_sagv(state))	14066	if (state->modeset && intel_can_enable_sagv(state))
13928	intel_enable_sagv(dev_priv);	14067	intel_enable_sagv(dev_priv);
13929		14068
13930	drm_atomic_helper_commit_hw_done(state);	14069	drm_atomic_helper_commit_hw_done(&state->base);
13931		14070
13932	if (intel_state->modeset) {	14071	if (state->modeset) {
13933	/* As one of the primary mmio accessors, KMS has a high	14072	/* As one of the primary mmio accessors, KMS has a high
13934	* likelihood of triggering bugs in unclaimed access. After we	14073	* likelihood of triggering bugs in unclaimed access. After we
13935	* finish modesetting, see if an error has been flagged, and if	14074	* finish modesetting, see if an error has been flagged, and if
@@ -13939,7 +14078,7 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state) · 3 unmodified lines
13939	intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);	14078	intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
13940	intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref);	14079	intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref);
13941	}	14080	}
13942	intel_runtime_pm_put(&dev_priv->runtime_pm, intel_state->wakeref);	14081	intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
13943		14082
13944	/*	14083	/*
13945	* Defer the cleanup of the old state to a separate worker to not	14084	* Defer the cleanup of the old state to a separate worker to not
@@ -13949,14 +14088,14 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state) · 3 unmodified lines
13949	* schedule point (cond_resched()) here anyway to keep latencies	14088	* schedule point (cond_resched()) here anyway to keep latencies
13950	* down.	14089	* down.
13951	*/	14090	*/
13952	INIT_WORK(&state->commit_work, intel_atomic_cleanup_work);	14091	INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work);
13953	queue_work(system_highpri_wq, &state->commit_work);	14092	queue_work(system_highpri_wq, &state->base.commit_work);
13954	}	14093	}
13955		14094
13956	static void intel_atomic_commit_work(struct work_struct *work)	14095	static void intel_atomic_commit_work(struct work_struct *work)
13957	{	14096	{
13958	struct drm_atomic_state *state =	14097	struct intel_atomic_state *state =
13959	container_of(work, struct drm_atomic_state, commit_work);	14098	container_of(work, struct intel_atomic_state, base.commit_work);
13960		14099
13961	intel_atomic_commit_tail(state);	14100	intel_atomic_commit_tail(state);
13962	}	14101	}
@@ -13986,42 +14125,31 @@ intel_atomic_commit_ready(struct i915_sw_fence *fence, · 23 unmodified lines
13986	return NOTIFY_DONE;	14125	return NOTIFY_DONE;
13987	}	14126	}
13988		14127
13989	static void intel_atomic_track_fbs(struct drm_atomic_state *state)	14128	static void intel_atomic_track_fbs(struct intel_atomic_state *state)
13990	{	14129	{
13991	struct drm_plane_state old_plane_state, new_plane_state;	14130	struct intel_plane_state old_plane_state, new_plane_state;
13992	struct drm_plane *plane;	14131	struct intel_plane *plane;
13993	int i;	14132	int i;
13994		14133
13995	for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)	14134	for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
13996	i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),	14135	new_plane_state, i)
13997	intel_fb_obj(new_plane_state->fb),	14136	i915_gem_track_fb(intel_fb_obj(old_plane_state->base.fb),
13998	to_intel_plane(plane)->frontbuffer_bit);	14137	intel_fb_obj(new_plane_state->base.fb),
		14138	plane->frontbuffer_bit);
13999	}	14139	}
14000		14140
14001	/**
14002	* intel_atomic_commit - commit validated state object
14003	* @dev: DRM device
14004	* @state: the top-level driver state object
14005	* @nonblock: nonblocking commit
14006	*
14007	* This function commits a top-level state object that has been validated
14008	* with drm_atomic_helper_check().
14009	*
14010	* RETURNS
14011	* Zero for success or -errno.
14012	*/
14013	static int intel_atomic_commit(struct drm_device *dev,	14141	static int intel_atomic_commit(struct drm_device *dev,
14014	struct drm_atomic_state *state,	14142	struct drm_atomic_state *_state,
14015	bool nonblock)	14143	bool nonblock)
14016	{	14144	{
14017	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);	14145	struct intel_atomic_state *state = to_intel_atomic_state(_state);
14018	struct drm_i915_private *dev_priv = to_i915(dev);	14146	struct drm_i915_private *dev_priv = to_i915(dev);
14019	int ret = 0;	14147	int ret = 0;
14020		14148
14021	intel_state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);	14149	state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
14022		14150
14023	drm_atomic_state_get(state);	14151	drm_atomic_state_get(&state->base);
14024	i915_sw_fence_init(&intel_state->commit_ready,	14152	i915_sw_fence_init(&state->commit_ready,
14025	intel_atomic_commit_ready);	14153	intel_atomic_commit_ready);
14026		14154
14027	/*	14155	/*
@@ -14041,63 +14169,61 @@ static int intel_atomic_commit(struct drm_device *dev, · 13 unmodified lines
14041	* FIXME doing watermarks and fb cleanup from a vblank worker	14169	* FIXME doing watermarks and fb cleanup from a vblank worker
14042	* (assuming we had any) would solve these problems.	14170	* (assuming we had any) would solve these problems.
14043	*/	14171	*/
14044	if (INTEL_GEN(dev_priv) < 9 && state->legacy_cursor_update) {	14172	if (INTEL_GEN(dev_priv) < 9 && state->base.legacy_cursor_update) {
14045	struct intel_crtc_state *new_crtc_state;	14173	struct intel_crtc_state *new_crtc_state;
14046	struct intel_crtc *crtc;	14174	struct intel_crtc *crtc;
14047	int i;	14175	int i;
14048		14176
14049	for_each_new_intel_crtc_in_state(intel_state, crtc, new_crtc_state, i)	14177	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
14050	if (new_crtc_state->wm.need_postvbl_update \|\|	14178	if (new_crtc_state->wm.need_postvbl_update \|\|
14051	new_crtc_state->update_wm_post)	14179	new_crtc_state->update_wm_post)
14052	state->legacy_cursor_update = false;	14180	state->base.legacy_cursor_update = false;
14053	}	14181	}
14054		14182
14055	ret = intel_atomic_prepare_commit(dev, state);	14183	ret = intel_atomic_prepare_commit(state);
14056	if (ret) {	14184	if (ret) {
14057	DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);	14185	DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
14058	i915_sw_fence_commit(&intel_state->commit_ready);	14186	i915_sw_fence_commit(&state->commit_ready);
14059	intel_runtime_pm_put(&dev_priv->runtime_pm, intel_state->wakeref);	14187	intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
14060	return ret;	14188	return ret;
14061	}	14189	}
14062		14190
14063	ret = drm_atomic_helper_setup_commit(state, nonblock);	14191	ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
14064	if (!ret)	14192	if (!ret)
14065	ret = drm_atomic_helper_swap_state(state, true);	14193	ret = drm_atomic_helper_swap_state(&state->base, true);
14066		14194
14067	if (ret) {	14195	if (ret) {
14068	i915_sw_fence_commit(&intel_state->commit_ready);	14196	i915_sw_fence_commit(&state->commit_ready);
14069		14197
14070	drm_atomic_helper_cleanup_planes(dev, state);	14198	drm_atomic_helper_cleanup_planes(dev, &state->base);
14071	intel_runtime_pm_put(&dev_priv->runtime_pm, intel_state->wakeref);	14199	intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
14072	return ret;	14200	return ret;
14073	}	14201	}
14074	dev_priv->wm.distrust_bios_wm = false;	14202	dev_priv->wm.distrust_bios_wm = false;
14075	intel_shared_dpll_swap_state(state);	14203	intel_shared_dpll_swap_state(state);
14076	intel_atomic_track_fbs(state);	14204	intel_atomic_track_fbs(state);
14077		14205
14078	if (intel_state->modeset) {	14206	if (state->modeset) {
14079	memcpy(dev_priv->min_cdclk, intel_state->min_cdclk,	14207	memcpy(dev_priv->min_cdclk, state->min_cdclk,
14080	sizeof(intel_state->min_cdclk));	14208	sizeof(state->min_cdclk));
14081	memcpy(dev_priv->min_voltage_level,	14209	memcpy(dev_priv->min_voltage_level, state->min_voltage_level,
14082	intel_state->min_voltage_level,	14210	sizeof(state->min_voltage_level));
14083	sizeof(intel_state->min_voltage_level));	14211	dev_priv->active_crtcs = state->active_crtcs;
14084	dev_priv->active_crtcs = intel_state->active_crtcs;	14212	dev_priv->cdclk.force_min_cdclk = state->cdclk.force_min_cdclk;
14085	dev_priv->cdclk.force_min_cdclk =
14086	intel_state->cdclk.force_min_cdclk;
14087		14213
14088	intel_cdclk_swap_state(intel_state);	14214	intel_cdclk_swap_state(state);
14089	}	14215	}
14090		14216
14091	drm_atomic_state_get(state);	14217	drm_atomic_state_get(&state->base);
14092	INIT_WORK(&state->commit_work, intel_atomic_commit_work);	14218	INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
14093		14219
14094	i915_sw_fence_commit(&intel_state->commit_ready);	14220	i915_sw_fence_commit(&state->commit_ready);
14095	if (nonblock && intel_state->modeset) {	14221	if (nonblock && state->modeset) {
14096	queue_work(dev_priv->modeset_wq, &state->commit_work);	14222	queue_work(dev_priv->modeset_wq, &state->base.commit_work);
14097	} else if (nonblock) {	14223	} else if (nonblock) {
14098	queue_work(system_unbound_wq, &state->commit_work);	14224	queue_work(system_unbound_wq, &state->base.commit_work);
14099	} else {	14225	} else {
14100	if (intel_state->modeset)	14226	if (state->modeset)
14101	flush_workqueue(dev_priv->modeset_wq);	14227	flush_workqueue(dev_priv->modeset_wq);
14102	intel_atomic_commit_tail(state);	14228	intel_atomic_commit_tail(state);
14103	}	14229	}
@@ -14105,18 +14231,6 @@ static int intel_atomic_commit(struct drm_device *dev, · 1 unmodified line
14105	return 0;	14231	return 0;
14106	}	14232	}
14107		14233
14108	static const struct drm_crtc_funcs intel_crtc_funcs = {
14109	.gamma_set = drm_atomic_helper_legacy_gamma_set,
14110	.set_config = drm_atomic_helper_set_config,
14111	.destroy = intel_crtc_destroy,
14112	.page_flip = drm_atomic_helper_page_flip,
14113	.atomic_duplicate_state = intel_crtc_duplicate_state,
14114	.atomic_destroy_state = intel_crtc_destroy_state,
14115	.set_crc_source = intel_crtc_set_crc_source,
14116	.verify_crc_source = intel_crtc_verify_crc_source,
14117	.get_crc_sources = intel_crtc_get_crc_sources,
14118	};
14119
14120	struct wait_rps_boost {	14234	struct wait_rps_boost {
14121	struct wait_queue_entry wait;	14235	struct wait_queue_entry wait;
14122		14236
@@ -14250,9 +14364,9 @@ intel_prepare_plane_fb(struct drm_plane *plane, · 127 unmodified lines
14250	int ret;	14364	int ret;
14251		14365
14252	if (old_obj) {	14366	if (old_obj) {
14253	struct drm_crtc_state *crtc_state =	14367	struct intel_crtc_state *crtc_state =
14254	drm_atomic_get_new_crtc_state(new_state->state,	14368	intel_atomic_get_new_crtc_state(intel_state,
14255	plane->state->crtc);	14369	to_intel_crtc(plane->state->crtc));
14256		14370
14257	/* Big Hammer, we also need to ensure that any pending	14371	/* Big Hammer, we also need to ensure that any pending
14258	* MI_WAIT_FOR_EVENT inside a user batch buffer on the	14372	* MI_WAIT_FOR_EVENT inside a user batch buffer on the
@@ -14413,7 +14527,7 @@ static void intel_begin_crtc_commit(struct intel_atomic_state *state, · 154 unmodified lines
14413	intel_atomic_get_old_crtc_state(state, crtc);	14527	intel_atomic_get_old_crtc_state(state, crtc);
14414	struct intel_crtc_state *new_crtc_state =	14528	struct intel_crtc_state *new_crtc_state =
14415	intel_atomic_get_new_crtc_state(state, crtc);	14529	intel_atomic_get_new_crtc_state(state, crtc);
14416	bool modeset = needs_modeset(&new_crtc_state->base);	14530	bool modeset = needs_modeset(new_crtc_state);
14417		14531
14418	/* Perform vblank evasion around commit operation */	14532	/* Perform vblank evasion around commit operation */
14419	intel_pipe_update_start(new_crtc_state);	14533	intel_pipe_update_start(new_crtc_state);
@@ -14466,7 +14580,7 @@ static void intel_finish_crtc_commit(struct intel_atomic_state *state, · 46 unmodified lines
14466	intel_pipe_update_end(new_crtc_state);	14580	intel_pipe_update_end(new_crtc_state);
14467		14581
14468	if (new_crtc_state->update_pipe &&	14582	if (new_crtc_state->update_pipe &&
14469	!needs_modeset(&new_crtc_state->base) &&	14583	!needs_modeset(new_crtc_state) &&
14470	old_crtc_state->base.mode.private_flags & I915_MODE_FLAG_INHERITED)	14584	old_crtc_state->base.mode.private_flags & I915_MODE_FLAG_INHERITED)
14471	intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);	14585	intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
14472	}	14586	}
@@ -14580,7 +14694,7 @@ intel_legacy_cursor_update(struct drm_plane *plane, · 107 unmodified lines
14580	* When crtc is inactive or there is a modeset pending,	14694	* When crtc is inactive or there is a modeset pending,
14581	* wait for it to complete in the slowpath	14695	* wait for it to complete in the slowpath
14582	*/	14696	*/
14583	if (!crtc_state->base.active \|\| needs_modeset(&crtc_state->base) \|\|	14697	if (!crtc_state->base.active \|\| needs_modeset(crtc_state) \|\|
14584	crtc_state->update_pipe)	14698	crtc_state->update_pipe)
14585	goto slow;	14699	goto slow;
14586		14700
@@ -14910,8 +15024,76 @@ static void intel_crtc_init_scalers(struct intel_crtc *crtc, · 323 unmodified lines
14910	scaler_state->scaler_id = -1;	15024	scaler_state->scaler_id = -1;
14911	}	15025	}
14912		15026
		15027	#define INTEL_CRTC_FUNCS \
		15028	.gamma_set = drm_atomic_helper_legacy_gamma_set, \
		15029	.set_config = drm_atomic_helper_set_config, \
		15030	.destroy = intel_crtc_destroy, \
		15031	.page_flip = drm_atomic_helper_page_flip, \
		15032	.atomic_duplicate_state = intel_crtc_duplicate_state, \
		15033	.atomic_destroy_state = intel_crtc_destroy_state, \
		15034	.set_crc_source = intel_crtc_set_crc_source, \
		15035	.verify_crc_source = intel_crtc_verify_crc_source, \
		15036	.get_crc_sources = intel_crtc_get_crc_sources
		15037
		15038	static const struct drm_crtc_funcs bdw_crtc_funcs = {
		15039	INTEL_CRTC_FUNCS,
		15040
		15041	.get_vblank_counter = g4x_get_vblank_counter,
		15042	.enable_vblank = bdw_enable_vblank,
		15043	.disable_vblank = bdw_disable_vblank,
		15044	};
		15045
		15046	static const struct drm_crtc_funcs ilk_crtc_funcs = {
		15047	INTEL_CRTC_FUNCS,
		15048
		15049	.get_vblank_counter = g4x_get_vblank_counter,
		15050	.enable_vblank = ilk_enable_vblank,
		15051	.disable_vblank = ilk_disable_vblank,
		15052	};
		15053
		15054	static const struct drm_crtc_funcs g4x_crtc_funcs = {
		15055	INTEL_CRTC_FUNCS,
		15056
		15057	.get_vblank_counter = g4x_get_vblank_counter,
		15058	.enable_vblank = i965_enable_vblank,
		15059	.disable_vblank = i965_disable_vblank,
		15060	};
		15061
		15062	static const struct drm_crtc_funcs i965_crtc_funcs = {
		15063	INTEL_CRTC_FUNCS,
		15064
		15065	.get_vblank_counter = i915_get_vblank_counter,
		15066	.enable_vblank = i965_enable_vblank,
		15067	.disable_vblank = i965_disable_vblank,
		15068	};
		15069
		15070	static const struct drm_crtc_funcs i945gm_crtc_funcs = {
		15071	INTEL_CRTC_FUNCS,
		15072
		15073	.get_vblank_counter = i915_get_vblank_counter,
		15074	.enable_vblank = i945gm_enable_vblank,
		15075	.disable_vblank = i945gm_disable_vblank,
		15076	};
		15077
		15078	static const struct drm_crtc_funcs i915_crtc_funcs = {
		15079	INTEL_CRTC_FUNCS,
		15080
		15081	.get_vblank_counter = i915_get_vblank_counter,
		15082	.enable_vblank = i8xx_enable_vblank,
		15083	.disable_vblank = i8xx_disable_vblank,
		15084	};
		15085
		15086	static const struct drm_crtc_funcs i8xx_crtc_funcs = {
		15087	INTEL_CRTC_FUNCS,
		15088
		15089	/* no hw vblank counter */
		15090	.enable_vblank = i8xx_enable_vblank,
		15091	.disable_vblank = i8xx_disable_vblank,
		15092	};
		15093
14913	static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)	15094	static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
14914	{	15095	{
		15096	const struct drm_crtc_funcs *funcs;
14915	struct intel_crtc *intel_crtc;	15097	struct intel_crtc *intel_crtc;
14916	struct intel_crtc_state *crtc_state = NULL;	15098	struct intel_crtc_state *crtc_state = NULL;
14917	struct intel_plane *primary = NULL;	15099	struct intel_plane *primary = NULL;
@@ -14955,10 +15137,28 @@ static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) · 37 unmodified lines
14955	}	15137	}
14956	intel_crtc->plane_ids_mask \|= BIT(cursor->id);	15138	intel_crtc->plane_ids_mask \|= BIT(cursor->id);
14957		15139
		15140	if (HAS_GMCH(dev_priv)) {
		15141	if (IS_CHERRYVIEW(dev_priv) \|\|
		15142	IS_VALLEYVIEW(dev_priv) \|\| IS_G4X(dev_priv))
		15143	funcs = &g4x_crtc_funcs;
		15144	else if (IS_GEN(dev_priv, 4))
		15145	funcs = &i965_crtc_funcs;
		15146	else if (IS_I945GM(dev_priv))
		15147	funcs = &i945gm_crtc_funcs;
		15148	else if (IS_GEN(dev_priv, 3))
		15149	funcs = &i915_crtc_funcs;
		15150	else
		15151	funcs = &i8xx_crtc_funcs;
		15152	} else {
		15153	if (INTEL_GEN(dev_priv) >= 8)
		15154	funcs = &bdw_crtc_funcs;
		15155	else
		15156	funcs = &ilk_crtc_funcs;
		15157	}
		15158
14958	ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,	15159	ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
14959	&primary->base, &cursor->base,	15160	&primary->base, &cursor->base,
14960	&intel_crtc_funcs,	15161	funcs, "pipe %c", pipe_name(pipe));
14961	"pipe %c", pipe_name(pipe));
14962	if (ret)	15162	if (ret)
14963	goto fail;	15163	goto fail;
14964		15164
@@ -15114,12 +15314,18 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) · 149 unmodified lines
15114	if (!HAS_DISPLAY(dev_priv))	15314	if (!HAS_DISPLAY(dev_priv))
15115	return;	15315	return;
15116		15316
15117	if (IS_ELKHARTLAKE(dev_priv)) {	15317	if (INTEL_GEN(dev_priv) >= 12) {
		15318	/* TODO: initialize TC ports as well */
		15319	intel_ddi_init(dev_priv, PORT_A);
		15320	intel_ddi_init(dev_priv, PORT_B);
		15321	intel_ddi_init(dev_priv, PORT_C);
		15322	} else if (IS_ELKHARTLAKE(dev_priv)) {
15118	intel_ddi_init(dev_priv, PORT_A);	15323	intel_ddi_init(dev_priv, PORT_A);
15119	intel_ddi_init(dev_priv, PORT_B);	15324	intel_ddi_init(dev_priv, PORT_B);
15120	intel_ddi_init(dev_priv, PORT_C);	15325	intel_ddi_init(dev_priv, PORT_C);
		15326	intel_ddi_init(dev_priv, PORT_D);
15121	icl_dsi_init(dev_priv);	15327	icl_dsi_init(dev_priv);
15122	} else if (INTEL_GEN(dev_priv) >= 11) {	15328	} else if (IS_GEN(dev_priv, 11)) {
15123	intel_ddi_init(dev_priv, PORT_A);	15329	intel_ddi_init(dev_priv, PORT_A);
15124	intel_ddi_init(dev_priv, PORT_B);	15330	intel_ddi_init(dev_priv, PORT_B);
15125	intel_ddi_init(dev_priv, PORT_C);	15331	intel_ddi_init(dev_priv, PORT_C);
@@ -15775,8 +15981,8 @@ static void sanitize_watermarks(struct drm_device *dev) · 649 unmodified lines
15775	struct drm_i915_private *dev_priv = to_i915(dev);	15981	struct drm_i915_private *dev_priv = to_i915(dev);
15776	struct drm_atomic_state *state;	15982	struct drm_atomic_state *state;
15777	struct intel_atomic_state *intel_state;	15983	struct intel_atomic_state *intel_state;
15778	struct drm_crtc *crtc;	15984	struct intel_crtc *crtc;
15779	struct drm_crtc_state *cstate;	15985	struct intel_crtc_state *crtc_state;
15780	struct drm_modeset_acquire_ctx ctx;	15986	struct drm_modeset_acquire_ctx ctx;
15781	int ret;	15987	int ret;
15782	int i;	15988	int i;
@@ -15831,13 +16037,11 @@ retry: · 48 unmodified lines
15831	}	16037	}
15832		16038
15833	/* Write calculated watermark values back */	16039	/* Write calculated watermark values back */
15834	for_each_new_crtc_in_state(state, crtc, cstate, i) {	16040	for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
15835	struct intel_crtc_state *cs = to_intel_crtc_state(cstate);	16041	crtc_state->wm.need_postvbl_update = true;
15836		16042	dev_priv->display.optimize_watermarks(intel_state, crtc_state);
15837	cs->wm.need_postvbl_update = true;
15838	dev_priv->display.optimize_watermarks(intel_state, cs);
15839		16043
15840	to_intel_crtc_state(crtc->state)->wm = cs->wm;	16044	to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
15841	}	16045	}
15842		16046
15843	put_state:	16047	put_state:
@@ -16495,6 +16699,13 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) · 651 unmodified lines
16495		16699
16496	pll->on = pll->info->funcs->get_hw_state(dev_priv, pll,	16700	pll->on = pll->info->funcs->get_hw_state(dev_priv, pll,
16497	&pll->state.hw_state);	16701	&pll->state.hw_state);
		16702
		16703	if (IS_ELKHARTLAKE(dev_priv) && pll->on &&
		16704	pll->info->id == DPLL_ID_EHL_DPLL4) {
		16705	pll->wakeref = intel_display_power_get(dev_priv,
		16706	POWER_DOMAIN_DPLL_DC_OFF);
		16707	}
		16708
16498	pll->state.crtc_mask = 0;	16709	pll->state.crtc_mask = 0;
16499	for_each_intel_crtc(dev, crtc) {	16710	for_each_intel_crtc(dev, crtc) {
16500	struct intel_crtc_state *crtc_state =	16711	struct intel_crtc_state *crtc_state =
@@ -16744,6 +16955,17 @@ intel_modeset_setup_hw_state(struct drm_device *dev, · 243 unmodified lines
16744	intel_modeset_readout_hw_state(dev);	16955	intel_modeset_readout_hw_state(dev);
16745		16956
16746	/* HW state is read out, now we need to sanitize this mess. */	16957	/* HW state is read out, now we need to sanitize this mess. */
		16958
		16959	/* Sanitize the TypeC port mode upfront, encoders depend on this */
		16960	for_each_intel_encoder(dev, encoder) {
		16961	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
		16962
		16963	/* We need to sanitize only the MST primary port. */
		16964	if (encoder->type != INTEL_OUTPUT_DP_MST &&
		16965	intel_phy_is_tc(dev_priv, phy))
		16966	intel_tc_port_sanitize(enc_to_dig_port(&encoder->base));
		16967	}
		16968
16747	get_encoder_power_domains(dev_priv);	16969	get_encoder_power_domains(dev_priv);
16748		16970
16749	if (HAS_PCH_IBX(dev_priv))	16971	if (HAS_PCH_IBX(dev_priv))
@@ -16804,7 +17026,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev, · 54 unmodified lines
16804	u64 put_domains;	17026	u64 put_domains;
16805		17027
16806	crtc_state = to_intel_crtc_state(crtc->base.state);	17028	crtc_state = to_intel_crtc_state(crtc->base.state);
16807	put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc_state);	17029	put_domains = modeset_get_crtc_power_domains(crtc_state);
16808	if (WARN_ON(put_domains))	17030	if (WARN_ON(put_domains))
16809	modeset_put_power_domains(dev_priv, put_domains);	17031	modeset_put_power_domains(dev_priv, put_domains);
16810	}	17032	}
@@ -16866,7 +17088,7 @@ static void intel_hpd_poll_fini(struct drm_device *dev) · 55 unmodified lines
16866	drm_connector_list_iter_end(&conn_iter);	17088	drm_connector_list_iter_end(&conn_iter);
16867	}	17089	}
16868		17090
16869	void intel_modeset_cleanup(struct drm_device *dev)	17091	void intel_modeset_driver_remove(struct drm_device *dev)
16870	{	17092	{
16871	struct drm_i915_private *dev_priv = to_i915(dev);	17093	struct drm_i915_private *dev_priv = to_i915(dev);
16872		17094
@@ -16982,7 +17204,7 @@ struct intel_display_error_state { · 109 unmodified lines
16982	u32 vtotal;	17204	u32 vtotal;
16983	u32 vblank;	17205	u32 vblank;
16984	u32 vsync;	17206	u32 vsync;
16985	} transcoder[4];	17207	} transcoder[5];
16986	};	17208	};
16987		17209
16988	struct intel_display_error_state *	17210	struct intel_display_error_state *
@@ -16993,6 +17215,7 @@ intel_display_capture_error_state(struct drm_i915_private *dev_priv) · 4 unmodified lines
16993	TRANSCODER_A,	17215	TRANSCODER_A,
16994	TRANSCODER_B,	17216	TRANSCODER_B,
16995	TRANSCODER_C,	17217	TRANSCODER_C,
		17218	TRANSCODER_D,
16996	TRANSCODER_EDP,	17219	TRANSCODER_EDP,
16997	};	17220	};
16998	int i;	17221	int i;

drivers/gpu/drm/i915/display/intel_display.h+46−4

 	GPIOK,
 	GPIOL,
 	GPIOM,
+	GPION,
+	GPIOO,
 };
 /*
 	PIPE_A = 0,
 	PIPE_B,
 	PIPE_C,
+	PIPE_D,
 	_PIPE_EDP,
 	I915_MAX_PIPES = _PIPE_EDP
 	TRANSCODER_A = PIPE_A,
 	TRANSCODER_B = PIPE_B,
 	TRANSCODER_C = PIPE_C,
+	TRANSCODER_D = PIPE_D,
 	/*
 	 * The following transcoders can map to any pipe, their enum value
 		return "B";
 	case TRANSCODER_C:
 		return "C";
+	case TRANSCODER_D:
+		return "D";
 	case TRANSCODER_EDP:
 		return "EDP";
 	case TRANSCODER_DSI_A:
 		return "Port E";
 	case PORT_F:
 		return "Port F";
+	case PORT_G:
+		return "Port G";
+	case PORT_H:
+		return "Port H";
+	case PORT_I:
+		return "Port I";
 	default:
 		return "<invalid>";
 	}
 	PORT_TC2,
 	PORT_TC3,
 	PORT_TC4,
+	PORT_TC5,
+	PORT_TC6,
 	I915_MAX_TC_PORTS
 };
-enum tc_port_type {
+enum tc_port_mode {
-	TC_PORT_UNKNOWN = 0,
+	TC_PORT_TBT_ALT,
-	TC_PORT_TYPEC,
+	TC_PORT_DP_ALT,
-	TC_PORT_TBT,
 	TC_PORT_LEGACY,
 };
 	u32 link_n;
 };
+enum phy {
+	PHY_NONE = -1,
+	PHY_A = 0,
+	PHY_B,
+	PHY_C,
+	PHY_D,
+	PHY_E,
+	PHY_F,
+	PHY_G,
+	PHY_H,
+	PHY_I,
+	I915_MAX_PHYS
+};
+#define phy_name(a) ((a) + 'A')
+enum phy_fia {
+	FIA1,
+	FIA2,
+	FIA3,
+};
 #define for_each_pipe(__dev_priv, __p) \
 	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
 	for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)	\
 		for_each_if((__ports_mask) & BIT(__port))
+#define for_each_phy_masked(__phy, __phys_mask) \
+	for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++)	\
+		for_each_if((__phys_mask) & BIT(__phy))
 #define for_each_crtc(dev, crtc) \
 	list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
 			      u32 pixel_format, u64 modifier);
 bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
+enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
 #endif

drivers/gpu/drm/i915/display/intel_display_power.c+614−44

@@ -17,13 +17,17 @@ · 16 unmodified lines
17	#include "intel_drv.h"	17	#include "intel_drv.h"
18	#include "intel_hotplug.h"	18	#include "intel_hotplug.h"
19	#include "intel_sideband.h"	19	#include "intel_sideband.h"
		20	#include "intel_tc.h"
20		21
21	bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,	22	bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
22	enum i915_power_well_id power_well_id);	23	enum i915_power_well_id power_well_id);
23		24
24	const char *	25	const char *
25	intel_display_power_domain_str(enum intel_display_power_domain domain)	26	intel_display_power_domain_str(struct drm_i915_private *i915,
		27	enum intel_display_power_domain domain)
26	{	28	{
		29	bool ddi_tc_ports = IS_GEN(i915, 12);
		30
27	switch (domain) {	31	switch (domain) {
28	case POWER_DOMAIN_DISPLAY_CORE:	32	case POWER_DOMAIN_DISPLAY_CORE:
29	return "DISPLAY_CORE";	33	return "DISPLAY_CORE";
@@ -33,22 +37,28 @@ intel_display_power_domain_str(enum intel_display_power_domain domain) · 3 unmodified lines
33	return "PIPE_B";	37	return "PIPE_B";
34	case POWER_DOMAIN_PIPE_C:	38	case POWER_DOMAIN_PIPE_C:
35	return "PIPE_C";	39	return "PIPE_C";
		40	case POWER_DOMAIN_PIPE_D:
		41	return "PIPE_D";
36	case POWER_DOMAIN_PIPE_A_PANEL_FITTER:	42	case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
37	return "PIPE_A_PANEL_FITTER";	43	return "PIPE_A_PANEL_FITTER";
38	case POWER_DOMAIN_PIPE_B_PANEL_FITTER:	44	case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
39	return "PIPE_B_PANEL_FITTER";	45	return "PIPE_B_PANEL_FITTER";
40	case POWER_DOMAIN_PIPE_C_PANEL_FITTER:	46	case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
41	return "PIPE_C_PANEL_FITTER";	47	return "PIPE_C_PANEL_FITTER";
		48	case POWER_DOMAIN_PIPE_D_PANEL_FITTER:
		49	return "PIPE_D_PANEL_FITTER";
42	case POWER_DOMAIN_TRANSCODER_A:	50	case POWER_DOMAIN_TRANSCODER_A:
43	return "TRANSCODER_A";	51	return "TRANSCODER_A";
44	case POWER_DOMAIN_TRANSCODER_B:	52	case POWER_DOMAIN_TRANSCODER_B:
45	return "TRANSCODER_B";	53	return "TRANSCODER_B";
46	case POWER_DOMAIN_TRANSCODER_C:	54	case POWER_DOMAIN_TRANSCODER_C:
47	return "TRANSCODER_C";	55	return "TRANSCODER_C";
		56	case POWER_DOMAIN_TRANSCODER_D:
		57	return "TRANSCODER_D";
48	case POWER_DOMAIN_TRANSCODER_EDP:	58	case POWER_DOMAIN_TRANSCODER_EDP:
49	return "TRANSCODER_EDP";	59	return "TRANSCODER_EDP";
50	case POWER_DOMAIN_TRANSCODER_EDP_VDSC:	60	case POWER_DOMAIN_TRANSCODER_VDSC_PW2:
51	return "TRANSCODER_EDP_VDSC";	61	return "TRANSCODER_VDSC_PW2";
52	case POWER_DOMAIN_TRANSCODER_DSI_A:	62	case POWER_DOMAIN_TRANSCODER_DSI_A:
53	return "TRANSCODER_DSI_A";	63	return "TRANSCODER_DSI_A";
54	case POWER_DOMAIN_TRANSCODER_DSI_C:	64	case POWER_DOMAIN_TRANSCODER_DSI_C:
@@ -60,11 +70,23 @@ intel_display_power_domain_str(enum intel_display_power_domain domain) · 5 unmodified lines
60	case POWER_DOMAIN_PORT_DDI_C_LANES:	70	case POWER_DOMAIN_PORT_DDI_C_LANES:
61	return "PORT_DDI_C_LANES";	71	return "PORT_DDI_C_LANES";
62	case POWER_DOMAIN_PORT_DDI_D_LANES:	72	case POWER_DOMAIN_PORT_DDI_D_LANES:
63	return "PORT_DDI_D_LANES";	73	BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_D_LANES !=
		74	POWER_DOMAIN_PORT_DDI_TC1_LANES);
		75	return ddi_tc_ports ? "PORT_DDI_TC1_LANES" : "PORT_DDI_D_LANES";
64	case POWER_DOMAIN_PORT_DDI_E_LANES:	76	case POWER_DOMAIN_PORT_DDI_E_LANES:
65	return "PORT_DDI_E_LANES";	77	BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_E_LANES !=
		78	POWER_DOMAIN_PORT_DDI_TC2_LANES);
		79	return ddi_tc_ports ? "PORT_DDI_TC2_LANES" : "PORT_DDI_E_LANES";
66	case POWER_DOMAIN_PORT_DDI_F_LANES:	80	case POWER_DOMAIN_PORT_DDI_F_LANES:
67	return "PORT_DDI_F_LANES";	81	BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_F_LANES !=
		82	POWER_DOMAIN_PORT_DDI_TC3_LANES);
		83	return ddi_tc_ports ? "PORT_DDI_TC3_LANES" : "PORT_DDI_F_LANES";
		84	case POWER_DOMAIN_PORT_DDI_TC4_LANES:
		85	return "PORT_DDI_TC4_LANES";
		86	case POWER_DOMAIN_PORT_DDI_TC5_LANES:
		87	return "PORT_DDI_TC5_LANES";
		88	case POWER_DOMAIN_PORT_DDI_TC6_LANES:
		89	return "PORT_DDI_TC6_LANES";
68	case POWER_DOMAIN_PORT_DDI_A_IO:	90	case POWER_DOMAIN_PORT_DDI_A_IO:
69	return "PORT_DDI_A_IO";	91	return "PORT_DDI_A_IO";
70	case POWER_DOMAIN_PORT_DDI_B_IO:	92	case POWER_DOMAIN_PORT_DDI_B_IO:
@@ -72,11 +94,23 @@ intel_display_power_domain_str(enum intel_display_power_domain domain) · 1 unmodified line
72	case POWER_DOMAIN_PORT_DDI_C_IO:	94	case POWER_DOMAIN_PORT_DDI_C_IO:
73	return "PORT_DDI_C_IO";	95	return "PORT_DDI_C_IO";
74	case POWER_DOMAIN_PORT_DDI_D_IO:	96	case POWER_DOMAIN_PORT_DDI_D_IO:
75	return "PORT_DDI_D_IO";	97	BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_D_IO !=
		98	POWER_DOMAIN_PORT_DDI_TC1_IO);
		99	return ddi_tc_ports ? "PORT_DDI_TC1_IO" : "PORT_DDI_D_IO";
76	case POWER_DOMAIN_PORT_DDI_E_IO:	100	case POWER_DOMAIN_PORT_DDI_E_IO:
77	return "PORT_DDI_E_IO";	101	BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_E_IO !=
		102	POWER_DOMAIN_PORT_DDI_TC2_IO);
		103	return ddi_tc_ports ? "PORT_DDI_TC2_IO" : "PORT_DDI_E_IO";
78	case POWER_DOMAIN_PORT_DDI_F_IO:	104	case POWER_DOMAIN_PORT_DDI_F_IO:
79	return "PORT_DDI_F_IO";	105	BUILD_BUG_ON(POWER_DOMAIN_PORT_DDI_F_IO !=
		106	POWER_DOMAIN_PORT_DDI_TC3_IO);
		107	return ddi_tc_ports ? "PORT_DDI_TC3_IO" : "PORT_DDI_F_IO";
		108	case POWER_DOMAIN_PORT_DDI_TC4_IO:
		109	return "PORT_DDI_TC4_IO";
		110	case POWER_DOMAIN_PORT_DDI_TC5_IO:
		111	return "PORT_DDI_TC5_IO";
		112	case POWER_DOMAIN_PORT_DDI_TC6_IO:
		113	return "PORT_DDI_TC6_IO";
80	case POWER_DOMAIN_PORT_DSI:	114	case POWER_DOMAIN_PORT_DSI:
81	return "PORT_DSI";	115	return "PORT_DSI";
82	case POWER_DOMAIN_PORT_CRT:	116	case POWER_DOMAIN_PORT_CRT:
@@ -94,11 +128,20 @@ intel_display_power_domain_str(enum intel_display_power_domain domain) · 11 unmodified lines
94	case POWER_DOMAIN_AUX_C:	128	case POWER_DOMAIN_AUX_C:
95	return "AUX_C";	129	return "AUX_C";
96	case POWER_DOMAIN_AUX_D:	130	case POWER_DOMAIN_AUX_D:
97	return "AUX_D";	131	BUILD_BUG_ON(POWER_DOMAIN_AUX_D != POWER_DOMAIN_AUX_TC1);
		132	return ddi_tc_ports ? "AUX_TC1" : "AUX_D";
98	case POWER_DOMAIN_AUX_E:	133	case POWER_DOMAIN_AUX_E:
99	return "AUX_E";	134	BUILD_BUG_ON(POWER_DOMAIN_AUX_E != POWER_DOMAIN_AUX_TC2);
		135	return ddi_tc_ports ? "AUX_TC2" : "AUX_E";
100	case POWER_DOMAIN_AUX_F:	136	case POWER_DOMAIN_AUX_F:
101	return "AUX_F";	137	BUILD_BUG_ON(POWER_DOMAIN_AUX_F != POWER_DOMAIN_AUX_TC3);
		138	return ddi_tc_ports ? "AUX_TC3" : "AUX_F";
		139	case POWER_DOMAIN_AUX_TC4:
		140	return "AUX_TC4";
		141	case POWER_DOMAIN_AUX_TC5:
		142	return "AUX_TC5";
		143	case POWER_DOMAIN_AUX_TC6:
		144	return "AUX_TC6";
102	case POWER_DOMAIN_AUX_IO_A:	145	case POWER_DOMAIN_AUX_IO_A:
103	return "AUX_IO_A";	146	return "AUX_IO_A";
104	case POWER_DOMAIN_AUX_TBT1:	147	case POWER_DOMAIN_AUX_TBT1:
@@ -109,6 +152,10 @@ intel_display_power_domain_str(enum intel_display_power_domain domain) · 4 unmodified lines
109	return "AUX_TBT3";	152	return "AUX_TBT3";
110	case POWER_DOMAIN_AUX_TBT4:	153	case POWER_DOMAIN_AUX_TBT4:
111	return "AUX_TBT4";	154	return "AUX_TBT4";
		155	case POWER_DOMAIN_AUX_TBT5:
		156	return "AUX_TBT5";
		157	case POWER_DOMAIN_AUX_TBT6:
		158	return "AUX_TBT6";
112	case POWER_DOMAIN_GMBUS:	159	case POWER_DOMAIN_GMBUS:
113	return "GMBUS";	160	return "GMBUS";
114	case POWER_DOMAIN_INIT:	161	case POWER_DOMAIN_INIT:
@@ -117,6 +164,8 @@ intel_display_power_domain_str(enum intel_display_power_domain domain) · 2 unmodified lines
117	return "MODESET";	164	return "MODESET";
118	case POWER_DOMAIN_GT_IRQ:	165	case POWER_DOMAIN_GT_IRQ:
119	return "GT_IRQ";	166	return "GT_IRQ";
		167	case POWER_DOMAIN_DPLL_DC_OFF:
		168	return "DPLL_DC_OFF";
120	default:	169	default:
121	MISSING_CASE(domain);	170	MISSING_CASE(domain);
122	return "?";	171	return "?";
@@ -269,11 +318,17 @@ static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv, · 146 unmodified lines
269	int pw_idx = power_well->desc->hsw.idx;	318	int pw_idx = power_well->desc->hsw.idx;
270		319
271	/* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */	320	/* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */
272	WARN_ON(intel_wait_for_register(&dev_priv->uncore,	321	if (intel_wait_for_register(&dev_priv->uncore,
273	regs->driver,	322	regs->driver,
274	HSW_PWR_WELL_CTL_STATE(pw_idx),	323	HSW_PWR_WELL_CTL_STATE(pw_idx),
275	HSW_PWR_WELL_CTL_STATE(pw_idx),	324	HSW_PWR_WELL_CTL_STATE(pw_idx),
276	1));	325	1)) {
		326	DRM_DEBUG_KMS("%s power well enable timeout\n",
		327	power_well->desc->name);
		328
		329	/* An AUX timeout is expected if the TBT DP tunnel is down. */
		330	WARN_ON(!power_well->desc->hsw.is_tc_tbt);
		331	}
277	}	332	}
278		333
279	static u32 hsw_power_well_requesters(struct drm_i915_private *dev_priv,	334	static u32 hsw_power_well_requesters(struct drm_i915_private *dev_priv,
@@ -388,7 +443,7 @@ static void hsw_power_well_disable(struct drm_i915_private *dev_priv, · 108 unmodified lines
388	hsw_wait_for_power_well_disable(dev_priv, power_well);	443	hsw_wait_for_power_well_disable(dev_priv, power_well);
389	}	444	}
390		445
391	#define ICL_AUX_PW_TO_PORT(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A)	446	#define ICL_AUX_PW_TO_PHY(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
392		447
393	static void	448	static void
394	icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,	449	icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
@@ -396,21 +451,29 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv, · 1 unmodified line
396	{	451	{
397	const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;	452	const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
398	int pw_idx = power_well->desc->hsw.idx;	453	int pw_idx = power_well->desc->hsw.idx;
399	enum port port = ICL_AUX_PW_TO_PORT(pw_idx);	454	enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx);
400	u32 val;	455	u32 val;
		456	int wa_idx_max;
401		457
402	val = I915_READ(regs->driver);	458	val = I915_READ(regs->driver);
403	I915_WRITE(regs->driver, val \| HSW_PWR_WELL_CTL_REQ(pw_idx));	459	I915_WRITE(regs->driver, val \| HSW_PWR_WELL_CTL_REQ(pw_idx));
404		460
405	val = I915_READ(ICL_PORT_CL_DW12(port));	461	if (INTEL_GEN(dev_priv) < 12) {
406	I915_WRITE(ICL_PORT_CL_DW12(port), val \| ICL_LANE_ENABLE_AUX);	462	val = I915_READ(ICL_PORT_CL_DW12(phy));
		463	I915_WRITE(ICL_PORT_CL_DW12(phy), val \| ICL_LANE_ENABLE_AUX);
		464	}
407		465
408	hsw_wait_for_power_well_enable(dev_priv, power_well);	466	hsw_wait_for_power_well_enable(dev_priv, power_well);
409		467
410	/* Display WA #1178: icl */	468	/* Display WA #1178: icl, tgl */
411	if (IS_ICELAKE(dev_priv) &&	469	if (IS_TIGERLAKE(dev_priv))
412	pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B &&	470	wa_idx_max = ICL_PW_CTL_IDX_AUX_C;
413	!intel_bios_is_port_edp(dev_priv, port)) {	471	else
		472	wa_idx_max = ICL_PW_CTL_IDX_AUX_B;
		473
		474	if (!IS_ELKHARTLAKE(dev_priv) &&
		475	pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= wa_idx_max &&
		476	!intel_bios_is_port_edp(dev_priv, (enum port)phy)) {
414	val = I915_READ(ICL_AUX_ANAOVRD1(pw_idx));	477	val = I915_READ(ICL_AUX_ANAOVRD1(pw_idx));
415	val \|= ICL_AUX_ANAOVRD1_ENABLE \| ICL_AUX_ANAOVRD1_LDO_BYPASS;	478	val \|= ICL_AUX_ANAOVRD1_ENABLE \| ICL_AUX_ANAOVRD1_LDO_BYPASS;
416	I915_WRITE(ICL_AUX_ANAOVRD1(pw_idx), val);	479	I915_WRITE(ICL_AUX_ANAOVRD1(pw_idx), val);
@@ -423,11 +486,13 @@ icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv, · 6 unmodified lines
423	{	486	{
424	const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;	487	const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
425	int pw_idx = power_well->desc->hsw.idx;	488	int pw_idx = power_well->desc->hsw.idx;
426	enum port port = ICL_AUX_PW_TO_PORT(pw_idx);	489	enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx);
427	u32 val;	490	u32 val;
428		491
429	val = I915_READ(ICL_PORT_CL_DW12(port));	492	if (INTEL_GEN(dev_priv) < 12) {
430	I915_WRITE(ICL_PORT_CL_DW12(port), val & ~ICL_LANE_ENABLE_AUX);	493	val = I915_READ(ICL_PORT_CL_DW12(phy));
		494	I915_WRITE(ICL_PORT_CL_DW12(phy), val & ~ICL_LANE_ENABLE_AUX);
		495	}
431		496
432	val = I915_READ(regs->driver);	497	val = I915_READ(regs->driver);
433	I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));	498	I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
@@ -441,26 +506,108 @@ icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv, · 7 unmodified lines
441	#define ICL_TBT_AUX_PW_TO_CH(pw_idx) \	506	#define ICL_TBT_AUX_PW_TO_CH(pw_idx) \
442	((pw_idx) - ICL_PW_CTL_IDX_AUX_TBT1 + AUX_CH_C)	507	((pw_idx) - ICL_PW_CTL_IDX_AUX_TBT1 + AUX_CH_C)
443		508
		509	static enum aux_ch icl_tc_phy_aux_ch(struct drm_i915_private *dev_priv,
		510	struct i915_power_well *power_well)
		511	{
		512	int pw_idx = power_well->desc->hsw.idx;
		513
		514	return power_well->desc->hsw.is_tc_tbt ? ICL_TBT_AUX_PW_TO_CH(pw_idx) :
		515	ICL_AUX_PW_TO_CH(pw_idx);
		516	}
		517
		518	#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
		519
		520	static u64 async_put_domains_mask(struct i915_power_domains *power_domains);
		521
		522	static int power_well_async_ref_count(struct drm_i915_private *dev_priv,
		523	struct i915_power_well *power_well)
		524	{
		525	int refs = hweight64(power_well->desc->domains &
		526	async_put_domains_mask(&dev_priv->power_domains));
		527
		528	WARN_ON(refs > power_well->count);
		529
		530	return refs;
		531	}
		532
		533	static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
		534	struct i915_power_well *power_well)
		535	{
		536	enum aux_ch aux_ch = icl_tc_phy_aux_ch(dev_priv, power_well);
		537	struct intel_digital_port *dig_port = NULL;
		538	struct intel_encoder *encoder;
		539
		540	/* Bypass the check if all references are released asynchronously */
		541	if (power_well_async_ref_count(dev_priv, power_well) ==
		542	power_well->count)
		543	return;
		544
		545	aux_ch = icl_tc_phy_aux_ch(dev_priv, power_well);
		546
		547	for_each_intel_encoder(&dev_priv->drm, encoder) {
		548	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
		549
		550	if (!intel_phy_is_tc(dev_priv, phy))
		551	continue;
		552
		553	/* We'll check the MST primary port */
		554	if (encoder->type == INTEL_OUTPUT_DP_MST)
		555	continue;
		556
		557	dig_port = enc_to_dig_port(&encoder->base);
		558	if (WARN_ON(!dig_port))
		559	continue;
		560
		561	if (dig_port->aux_ch != aux_ch) {
		562	dig_port = NULL;
		563	continue;
		564	}
		565
		566	break;
		567	}
		568
		569	if (WARN_ON(!dig_port))
		570	return;
		571
		572	WARN_ON(!intel_tc_port_ref_held(dig_port));
		573	}
		574
		575	#else
		576
		577	static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
		578	struct i915_power_well *power_well)
		579	{
		580	}
		581
		582	#endif
		583
444	static void	584	static void
445	icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,	585	icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
446	struct i915_power_well *power_well)	586	struct i915_power_well *power_well)
447	{	587	{
448	int pw_idx = power_well->desc->hsw.idx;	588	enum aux_ch aux_ch = icl_tc_phy_aux_ch(dev_priv, power_well);
449	bool is_tbt = power_well->desc->hsw.is_tc_tbt;
450	enum aux_ch aux_ch;
451	u32 val;	589	u32 val;
452		590
453	aux_ch = is_tbt ? ICL_TBT_AUX_PW_TO_CH(pw_idx) :	591	icl_tc_port_assert_ref_held(dev_priv, power_well);
454	ICL_AUX_PW_TO_CH(pw_idx);	592
455	val = I915_READ(DP_AUX_CH_CTL(aux_ch));	593	val = I915_READ(DP_AUX_CH_CTL(aux_ch));
456	val &= ~DP_AUX_CH_CTL_TBT_IO;	594	val &= ~DP_AUX_CH_CTL_TBT_IO;
457	if (is_tbt)	595	if (power_well->desc->hsw.is_tc_tbt)
458	val \|= DP_AUX_CH_CTL_TBT_IO;	596	val \|= DP_AUX_CH_CTL_TBT_IO;
459	I915_WRITE(DP_AUX_CH_CTL(aux_ch), val);	597	I915_WRITE(DP_AUX_CH_CTL(aux_ch), val);
460		598
461	hsw_power_well_enable(dev_priv, power_well);	599	hsw_power_well_enable(dev_priv, power_well);
462	}	600	}
463		601
		602	static void
		603	icl_tc_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
		604	struct i915_power_well *power_well)
		605	{
		606	icl_tc_port_assert_ref_held(dev_priv, power_well);
		607
		608	hsw_power_well_disable(dev_priv, power_well);
		609	}
		610
464	/*	611	/*
465	* We should only use the power well if we explicitly asked the hardware to	612	* We should only use the power well if we explicitly asked the hardware to
466	* enable it, so check if it's enabled and also check if we've requested it to	613	* enable it, so check if it's enabled and also check if we've requested it to
@@ -1071,7 +1218,7 @@ static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv) · 604 unmodified lines
1071	spin_unlock_irq(&dev_priv->irq_lock);	1218	spin_unlock_irq(&dev_priv->irq_lock);
1072		1219
1073	/* make sure we're done processing display irqs */	1220	/* make sure we're done processing display irqs */
1074	synchronize_irq(dev_priv->drm.irq);	1221	intel_synchronize_irq(dev_priv);
1075		1222
1076	intel_power_sequencer_reset(dev_priv);	1223	intel_power_sequencer_reset(dev_priv);
1077		1224
@@ -1575,12 +1722,15 @@ __async_put_domains_state_ok(struct i915_power_domains *power_domains) · 497 unmodified lines
1575	static void print_power_domains(struct i915_power_domains *power_domains,	1722	static void print_power_domains(struct i915_power_domains *power_domains,
1576	const char *prefix, u64 mask)	1723	const char *prefix, u64 mask)
1577	{	1724	{
		1725	struct drm_i915_private *i915 =
		1726	container_of(power_domains, struct drm_i915_private,
		1727	power_domains);
1578	enum intel_display_power_domain domain;	1728	enum intel_display_power_domain domain;
1579		1729
1580	DRM_DEBUG_DRIVER("%s (%lu):\n", prefix, hweight64(mask));	1730	DRM_DEBUG_DRIVER("%s (%lu):\n", prefix, hweight64(mask));
1581	for_each_power_domain(domain, mask)	1731	for_each_power_domain(domain, mask)
1582	DRM_DEBUG_DRIVER("%s use_count %d\n",	1732	DRM_DEBUG_DRIVER("%s use_count %d\n",
1583	intel_display_power_domain_str(domain),	1733	intel_display_power_domain_str(i915, domain),
1584	power_domains->domain_use_count[domain]);	1734	power_domains->domain_use_count[domain]);
1585	}	1735	}
1586		1736
@@ -1750,7 +1900,7 @@ __intel_display_power_put_domain(struct drm_i915_private *dev_priv, · 163 unmodified lines
1750	{	1900	{
1751	struct i915_power_domains *power_domains;	1901	struct i915_power_domains *power_domains;
1752	struct i915_power_well *power_well;	1902	struct i915_power_well *power_well;
1753	const char *name = intel_display_power_domain_str(domain);	1903	const char *name = intel_display_power_domain_str(dev_priv, domain);
1754		1904
1755	power_domains = &dev_priv->power_domains;	1905	power_domains = &dev_priv->power_domains;
1756		1906
@@ -2359,7 +2509,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, · 602 unmodified lines
2359	*/	2509	*/
2360	#define ICL_PW_2_POWER_DOMAINS ( \	2510	#define ICL_PW_2_POWER_DOMAINS ( \
2361	ICL_PW_3_POWER_DOMAINS \| \	2511	ICL_PW_3_POWER_DOMAINS \| \
2362	BIT_ULL(POWER_DOMAIN_TRANSCODER_EDP_VDSC) \| \	2512	BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) \| \
2363	BIT_ULL(POWER_DOMAIN_INIT))	2513	BIT_ULL(POWER_DOMAIN_INIT))
2364	/*	2514	/*
2365	* - KVMR (HW control)	2515	* - KVMR (HW control)
@@ -2368,6 +2518,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, · 2 unmodified lines
2368	ICL_PW_2_POWER_DOMAINS \| \	2518	ICL_PW_2_POWER_DOMAINS \| \
2369	BIT_ULL(POWER_DOMAIN_MODESET) \| \	2519	BIT_ULL(POWER_DOMAIN_MODESET) \| \
2370	BIT_ULL(POWER_DOMAIN_AUX_A) \| \	2520	BIT_ULL(POWER_DOMAIN_AUX_A) \| \
		2521	BIT_ULL(POWER_DOMAIN_DPLL_DC_OFF) \| \
2371	BIT_ULL(POWER_DOMAIN_INIT))	2522	BIT_ULL(POWER_DOMAIN_INIT))
2372		2523
2373	#define ICL_DDI_IO_A_POWER_DOMAINS ( \	2524	#define ICL_DDI_IO_A_POWER_DOMAINS ( \
@@ -2405,6 +2556,93 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, · 31 unmodified lines
2405	#define ICL_AUX_TBT4_IO_POWER_DOMAINS ( \	2556	#define ICL_AUX_TBT4_IO_POWER_DOMAINS ( \
2406	BIT_ULL(POWER_DOMAIN_AUX_TBT4))	2557	BIT_ULL(POWER_DOMAIN_AUX_TBT4))
2407		2558
		2559	#define TGL_PW_5_POWER_DOMAINS ( \
		2560	BIT_ULL(POWER_DOMAIN_PIPE_D) \| \
		2561	BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) \| \
		2562	BIT_ULL(POWER_DOMAIN_INIT))
		2563
		2564	#define TGL_PW_4_POWER_DOMAINS ( \
		2565	TGL_PW_5_POWER_DOMAINS \| \
		2566	BIT_ULL(POWER_DOMAIN_PIPE_C) \| \
		2567	BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) \| \
		2568	BIT_ULL(POWER_DOMAIN_INIT))
		2569
		2570	#define TGL_PW_3_POWER_DOMAINS ( \
		2571	TGL_PW_4_POWER_DOMAINS \| \
		2572	BIT_ULL(POWER_DOMAIN_PIPE_B) \| \
		2573	BIT_ULL(POWER_DOMAIN_TRANSCODER_B) \| \
		2574	BIT_ULL(POWER_DOMAIN_TRANSCODER_C) \| \
		2575	BIT_ULL(POWER_DOMAIN_TRANSCODER_D) \| \
		2576	BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) \| \
		2577	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_LANES) \| \
		2578	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_IO) \| \
		2579	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC2_LANES) \| \
		2580	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC2_IO) \| \
		2581	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC3_LANES) \| \
		2582	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC3_IO) \| \
		2583	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC4_LANES) \| \
		2584	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC4_IO) \| \
		2585	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC5_LANES) \| \
		2586	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC5_IO) \| \
		2587	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC6_LANES) \| \
		2588	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC6_IO) \| \
		2589	BIT_ULL(POWER_DOMAIN_AUX_TC1) \| \
		2590	BIT_ULL(POWER_DOMAIN_AUX_TC2) \| \
		2591	BIT_ULL(POWER_DOMAIN_AUX_TC3) \| \
		2592	BIT_ULL(POWER_DOMAIN_AUX_TC4) \| \
		2593	BIT_ULL(POWER_DOMAIN_AUX_TC5) \| \
		2594	BIT_ULL(POWER_DOMAIN_AUX_TC6) \| \
		2595	BIT_ULL(POWER_DOMAIN_AUX_TBT1) \| \
		2596	BIT_ULL(POWER_DOMAIN_AUX_TBT2) \| \
		2597	BIT_ULL(POWER_DOMAIN_AUX_TBT3) \| \
		2598	BIT_ULL(POWER_DOMAIN_AUX_TBT4) \| \
		2599	BIT_ULL(POWER_DOMAIN_AUX_TBT5) \| \
		2600	BIT_ULL(POWER_DOMAIN_AUX_TBT6) \| \
		2601	BIT_ULL(POWER_DOMAIN_VGA) \| \
		2602	BIT_ULL(POWER_DOMAIN_AUDIO) \| \
		2603	BIT_ULL(POWER_DOMAIN_INIT))
		2604
		2605	#define TGL_PW_2_POWER_DOMAINS ( \
		2606	TGL_PW_3_POWER_DOMAINS \| \
		2607	BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) \| \
		2608	BIT_ULL(POWER_DOMAIN_INIT))
		2609
		2610	#define TGL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
		2611	TGL_PW_2_POWER_DOMAINS \| \
		2612	BIT_ULL(POWER_DOMAIN_MODESET) \| \
		2613	BIT_ULL(POWER_DOMAIN_AUX_A) \| \
		2614	BIT_ULL(POWER_DOMAIN_INIT))
		2615
		2616	#define TGL_DDI_IO_TC1_POWER_DOMAINS ( \
		2617	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_IO))
		2618	#define TGL_DDI_IO_TC2_POWER_DOMAINS ( \
		2619	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC2_IO))
		2620	#define TGL_DDI_IO_TC3_POWER_DOMAINS ( \
		2621	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC3_IO))
		2622	#define TGL_DDI_IO_TC4_POWER_DOMAINS ( \
		2623	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC4_IO))
		2624	#define TGL_DDI_IO_TC5_POWER_DOMAINS ( \
		2625	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC5_IO))
		2626	#define TGL_DDI_IO_TC6_POWER_DOMAINS ( \
		2627	BIT_ULL(POWER_DOMAIN_PORT_DDI_TC6_IO))
		2628
		2629	#define TGL_AUX_TC1_IO_POWER_DOMAINS ( \
		2630	BIT_ULL(POWER_DOMAIN_AUX_TC1))
		2631	#define TGL_AUX_TC2_IO_POWER_DOMAINS ( \
		2632	BIT_ULL(POWER_DOMAIN_AUX_TC2))
		2633	#define TGL_AUX_TC3_IO_POWER_DOMAINS ( \
		2634	BIT_ULL(POWER_DOMAIN_AUX_TC3))
		2635	#define TGL_AUX_TC4_IO_POWER_DOMAINS ( \
		2636	BIT_ULL(POWER_DOMAIN_AUX_TC4))
		2637	#define TGL_AUX_TC5_IO_POWER_DOMAINS ( \
		2638	BIT_ULL(POWER_DOMAIN_AUX_TC5))
		2639	#define TGL_AUX_TC6_IO_POWER_DOMAINS ( \
		2640	BIT_ULL(POWER_DOMAIN_AUX_TC6))
		2641	#define TGL_AUX_TBT5_IO_POWER_DOMAINS ( \
		2642	BIT_ULL(POWER_DOMAIN_AUX_TBT5))
		2643	#define TGL_AUX_TBT6_IO_POWER_DOMAINS ( \
		2644	BIT_ULL(POWER_DOMAIN_AUX_TBT6))
		2645
2408	static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {	2646	static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
2409	.sync_hw = i9xx_power_well_sync_hw_noop,	2647	.sync_hw = i9xx_power_well_sync_hw_noop,
2410	.enable = i9xx_always_on_power_well_noop,	2648	.enable = i9xx_always_on_power_well_noop,
@@ -3113,7 +3351,7 @@ static const struct i915_power_well_ops icl_combo_phy_aux_power_well_ops = { · 702 unmodified lines
3113	static const struct i915_power_well_ops icl_tc_phy_aux_power_well_ops = {	3351	static const struct i915_power_well_ops icl_tc_phy_aux_power_well_ops = {
3114	.sync_hw = hsw_power_well_sync_hw,	3352	.sync_hw = hsw_power_well_sync_hw,
3115	.enable = icl_tc_phy_aux_power_well_enable,	3353	.enable = icl_tc_phy_aux_power_well_enable,
3116	.disable = hsw_power_well_disable,	3354	.disable = icl_tc_phy_aux_power_well_disable,
3117	.is_enabled = hsw_power_well_enabled,	3355	.is_enabled = hsw_power_well_enabled,
3118	};	3356	};
3119		3357
@@ -3362,6 +3600,335 @@ static const struct i915_power_well_desc icl_power_wells[] = { · 242 unmodified lines
3362	},	3600	},
3363	};	3601	};
3364		3602
		3603	static const struct i915_power_well_desc tgl_power_wells[] = {
		3604	{
		3605	.name = "always-on",
		3606	.always_on = true,
		3607	.domains = POWER_DOMAIN_MASK,
		3608	.ops = &i9xx_always_on_power_well_ops,
		3609	.id = DISP_PW_ID_NONE,
		3610	},
		3611	{
		3612	.name = "power well 1",
		3613	/* Handled by the DMC firmware */
		3614	.always_on = true,
		3615	.domains = 0,
		3616	.ops = &hsw_power_well_ops,
		3617	.id = SKL_DISP_PW_1,
		3618	{
		3619	.hsw.regs = &hsw_power_well_regs,
		3620	.hsw.idx = ICL_PW_CTL_IDX_PW_1,
		3621	.hsw.has_fuses = true,
		3622	},
		3623	},
		3624	{
		3625	.name = "DC off",
		3626	.domains = TGL_DISPLAY_DC_OFF_POWER_DOMAINS,
		3627	.ops = &gen9_dc_off_power_well_ops,
		3628	.id = DISP_PW_ID_NONE,
		3629	},
		3630	{
		3631	.name = "power well 2",
		3632	.domains = TGL_PW_2_POWER_DOMAINS,
		3633	.ops = &hsw_power_well_ops,
		3634	.id = SKL_DISP_PW_2,
		3635	{
		3636	.hsw.regs = &hsw_power_well_regs,
		3637	.hsw.idx = ICL_PW_CTL_IDX_PW_2,
		3638	.hsw.has_fuses = true,
		3639	},
		3640	},
		3641	{
		3642	.name = "power well 3",
		3643	.domains = TGL_PW_3_POWER_DOMAINS,
		3644	.ops = &hsw_power_well_ops,
		3645	.id = DISP_PW_ID_NONE,
		3646	{
		3647	.hsw.regs = &hsw_power_well_regs,
		3648	.hsw.idx = ICL_PW_CTL_IDX_PW_3,
		3649	.hsw.irq_pipe_mask = BIT(PIPE_B),
		3650	.hsw.has_vga = true,
		3651	.hsw.has_fuses = true,
		3652	},
		3653	},
		3654	{
		3655	.name = "DDI A IO",
		3656	.domains = ICL_DDI_IO_A_POWER_DOMAINS,
		3657	.ops = &hsw_power_well_ops,
		3658	.id = DISP_PW_ID_NONE,
		3659	{
		3660	.hsw.regs = &icl_ddi_power_well_regs,
		3661	.hsw.idx = ICL_PW_CTL_IDX_DDI_A,
		3662	}
		3663	},
		3664	{
		3665	.name = "DDI B IO",
		3666	.domains = ICL_DDI_IO_B_POWER_DOMAINS,
		3667	.ops = &hsw_power_well_ops,
		3668	.id = DISP_PW_ID_NONE,
		3669	{
		3670	.hsw.regs = &icl_ddi_power_well_regs,
		3671	.hsw.idx = ICL_PW_CTL_IDX_DDI_B,
		3672	}
		3673	},
		3674	{
		3675	.name = "DDI C IO",
		3676	.domains = ICL_DDI_IO_C_POWER_DOMAINS,
		3677	.ops = &hsw_power_well_ops,
		3678	.id = DISP_PW_ID_NONE,
		3679	{
		3680	.hsw.regs = &icl_ddi_power_well_regs,
		3681	.hsw.idx = ICL_PW_CTL_IDX_DDI_C,
		3682	}
		3683	},
		3684	{
		3685	.name = "DDI TC1 IO",
		3686	.domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
		3687	.ops = &hsw_power_well_ops,
		3688	.id = DISP_PW_ID_NONE,
		3689	{
		3690	.hsw.regs = &icl_ddi_power_well_regs,
		3691	.hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
		3692	},
		3693	},
		3694	{
		3695	.name = "DDI TC2 IO",
		3696	.domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
		3697	.ops = &hsw_power_well_ops,
		3698	.id = DISP_PW_ID_NONE,
		3699	{
		3700	.hsw.regs = &icl_ddi_power_well_regs,
		3701	.hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
		3702	},
		3703	},
		3704	{
		3705	.name = "DDI TC3 IO",
		3706	.domains = TGL_DDI_IO_TC3_POWER_DOMAINS,
		3707	.ops = &hsw_power_well_ops,
		3708	.id = DISP_PW_ID_NONE,
		3709	{
		3710	.hsw.regs = &icl_ddi_power_well_regs,
		3711	.hsw.idx = TGL_PW_CTL_IDX_DDI_TC3,
		3712	},
		3713	},
		3714	{
		3715	.name = "DDI TC4 IO",
		3716	.domains = TGL_DDI_IO_TC4_POWER_DOMAINS,
		3717	.ops = &hsw_power_well_ops,
		3718	.id = DISP_PW_ID_NONE,
		3719	{
		3720	.hsw.regs = &icl_ddi_power_well_regs,
		3721	.hsw.idx = TGL_PW_CTL_IDX_DDI_TC4,
		3722	},
		3723	},
		3724	{
		3725	.name = "DDI TC5 IO",
		3726	.domains = TGL_DDI_IO_TC5_POWER_DOMAINS,
		3727	.ops = &hsw_power_well_ops,
		3728	.id = DISP_PW_ID_NONE,
		3729	{
		3730	.hsw.regs = &icl_ddi_power_well_regs,
		3731	.hsw.idx = TGL_PW_CTL_IDX_DDI_TC5,
		3732	},
		3733	},
		3734	{
		3735	.name = "DDI TC6 IO",
		3736	.domains = TGL_DDI_IO_TC6_POWER_DOMAINS,
		3737	.ops = &hsw_power_well_ops,
		3738	.id = DISP_PW_ID_NONE,
		3739	{
		3740	.hsw.regs = &icl_ddi_power_well_regs,
		3741	.hsw.idx = TGL_PW_CTL_IDX_DDI_TC6,
		3742	},
		3743	},
		3744	{
		3745	.name = "AUX A",
		3746	.domains = ICL_AUX_A_IO_POWER_DOMAINS,
		3747	.ops = &icl_combo_phy_aux_power_well_ops,
		3748	.id = DISP_PW_ID_NONE,
		3749	{
		3750	.hsw.regs = &icl_aux_power_well_regs,
		3751	.hsw.idx = ICL_PW_CTL_IDX_AUX_A,
		3752	},
		3753	},
		3754	{
		3755	.name = "AUX B",
		3756	.domains = ICL_AUX_B_IO_POWER_DOMAINS,
		3757	.ops = &icl_combo_phy_aux_power_well_ops,
		3758	.id = DISP_PW_ID_NONE,
		3759	{
		3760	.hsw.regs = &icl_aux_power_well_regs,
		3761	.hsw.idx = ICL_PW_CTL_IDX_AUX_B,
		3762	},
		3763	},
		3764	{
		3765	.name = "AUX C",
		3766	.domains = ICL_AUX_C_IO_POWER_DOMAINS,
		3767	.ops = &icl_combo_phy_aux_power_well_ops,
		3768	.id = DISP_PW_ID_NONE,
		3769	{
		3770	.hsw.regs = &icl_aux_power_well_regs,
		3771	.hsw.idx = ICL_PW_CTL_IDX_AUX_C,
		3772	},
		3773	},
		3774	{
		3775	.name = "AUX TC1",
		3776	.domains = TGL_AUX_TC1_IO_POWER_DOMAINS,
		3777	.ops = &icl_tc_phy_aux_power_well_ops,
		3778	.id = DISP_PW_ID_NONE,
		3779	{
		3780	.hsw.regs = &icl_aux_power_well_regs,
		3781	.hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
		3782	.hsw.is_tc_tbt = false,
		3783	},
		3784	},
		3785	{
		3786	.name = "AUX TC2",
		3787	.domains = TGL_AUX_TC2_IO_POWER_DOMAINS,
		3788	.ops = &icl_tc_phy_aux_power_well_ops,
		3789	.id = DISP_PW_ID_NONE,
		3790	{
		3791	.hsw.regs = &icl_aux_power_well_regs,
		3792	.hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
		3793	.hsw.is_tc_tbt = false,
		3794	},
		3795	},
		3796	{
		3797	.name = "AUX TC3",
		3798	.domains = TGL_AUX_TC3_IO_POWER_DOMAINS,
		3799	.ops = &icl_tc_phy_aux_power_well_ops,
		3800	.id = DISP_PW_ID_NONE,
		3801	{
		3802	.hsw.regs = &icl_aux_power_well_regs,
		3803	.hsw.idx = TGL_PW_CTL_IDX_AUX_TC3,
		3804	.hsw.is_tc_tbt = false,
		3805	},
		3806	},
		3807	{
		3808	.name = "AUX TC4",
		3809	.domains = TGL_AUX_TC4_IO_POWER_DOMAINS,
		3810	.ops = &icl_tc_phy_aux_power_well_ops,
		3811	.id = DISP_PW_ID_NONE,
		3812	{
		3813	.hsw.regs = &icl_aux_power_well_regs,
		3814	.hsw.idx = TGL_PW_CTL_IDX_AUX_TC4,
		3815	.hsw.is_tc_tbt = false,
		3816	},
		3817	},
		3818	{
		3819	.name = "AUX TC5",
		3820	.domains = TGL_AUX_TC5_IO_POWER_DOMAINS,
		3821	.ops = &icl_tc_phy_aux_power_well_ops,
		3822	.id = DISP_PW_ID_NONE,
		3823	{
		3824	.hsw.regs = &icl_aux_power_well_regs,
		3825	.hsw.idx = TGL_PW_CTL_IDX_AUX_TC5,
		3826	.hsw.is_tc_tbt = false,
		3827	},
		3828	},
		3829	{
		3830	.name = "AUX TC6",
		3831	.domains = TGL_AUX_TC6_IO_POWER_DOMAINS,
		3832	.ops = &icl_tc_phy_aux_power_well_ops,
		3833	.id = DISP_PW_ID_NONE,
		3834	{
		3835	.hsw.regs = &icl_aux_power_well_regs,
		3836	.hsw.idx = TGL_PW_CTL_IDX_AUX_TC6,
		3837	.hsw.is_tc_tbt = false,
		3838	},
		3839	},
		3840	{
		3841	.name = "AUX TBT1",
		3842	.domains = ICL_AUX_TBT1_IO_POWER_DOMAINS,
		3843	.ops = &hsw_power_well_ops,
		3844	.id = DISP_PW_ID_NONE,
		3845	{
		3846	.hsw.regs = &icl_aux_power_well_regs,
		3847	.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1,
		3848	.hsw.is_tc_tbt = true,
		3849	},
		3850	},
		3851	{
		3852	.name = "AUX TBT2",
		3853	.domains = ICL_AUX_TBT2_IO_POWER_DOMAINS,
		3854	.ops = &hsw_power_well_ops,
		3855	.id = DISP_PW_ID_NONE,
		3856	{
		3857	.hsw.regs = &icl_aux_power_well_regs,
		3858	.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2,
		3859	.hsw.is_tc_tbt = true,
		3860	},
		3861	},
		3862	{
		3863	.name = "AUX TBT3",
		3864	.domains = ICL_AUX_TBT3_IO_POWER_DOMAINS,
		3865	.ops = &hsw_power_well_ops,
		3866	.id = DISP_PW_ID_NONE,
		3867	{
		3868	.hsw.regs = &icl_aux_power_well_regs,
		3869	.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3,
		3870	.hsw.is_tc_tbt = true,
		3871	},
		3872	},
		3873	{
		3874	.name = "AUX TBT4",
		3875	.domains = ICL_AUX_TBT4_IO_POWER_DOMAINS,
		3876	.ops = &hsw_power_well_ops,
		3877	.id = DISP_PW_ID_NONE,
		3878	{
		3879	.hsw.regs = &icl_aux_power_well_regs,
		3880	.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4,
		3881	.hsw.is_tc_tbt = true,
		3882	},
		3883	},
		3884	{
		3885	.name = "AUX TBT5",
		3886	.domains = TGL_AUX_TBT5_IO_POWER_DOMAINS,
		3887	.ops = &hsw_power_well_ops,
		3888	.id = DISP_PW_ID_NONE,
		3889	{
		3890	.hsw.regs = &icl_aux_power_well_regs,
		3891	.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT5,
		3892	.hsw.is_tc_tbt = true,
		3893	},
		3894	},
		3895	{
		3896	.name = "AUX TBT6",
		3897	.domains = TGL_AUX_TBT6_IO_POWER_DOMAINS,
		3898	.ops = &hsw_power_well_ops,
		3899	.id = DISP_PW_ID_NONE,
		3900	{
		3901	.hsw.regs = &icl_aux_power_well_regs,
		3902	.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT6,
		3903	.hsw.is_tc_tbt = true,
		3904	},
		3905	},
		3906	{
		3907	.name = "power well 4",
		3908	.domains = TGL_PW_4_POWER_DOMAINS,
		3909	.ops = &hsw_power_well_ops,
		3910	.id = DISP_PW_ID_NONE,
		3911	{
		3912	.hsw.regs = &hsw_power_well_regs,
		3913	.hsw.idx = ICL_PW_CTL_IDX_PW_4,
		3914	.hsw.has_fuses = true,
		3915	.hsw.irq_pipe_mask = BIT(PIPE_C),
		3916	}
		3917	},
		3918	{
		3919	.name = "power well 5",
		3920	.domains = TGL_PW_5_POWER_DOMAINS,
		3921	.ops = &hsw_power_well_ops,
		3922	.id = DISP_PW_ID_NONE,
		3923	{
		3924	.hsw.regs = &hsw_power_well_regs,
		3925	.hsw.idx = TGL_PW_CTL_IDX_PW_5,
		3926	.hsw.has_fuses = true,
		3927	.hsw.irq_pipe_mask = BIT(PIPE_D),
		3928	},
		3929	},
		3930	};
		3931
3365	static int	3932	static int
3366	sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,	3933	sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
3367	int disable_power_well)	3934	int disable_power_well)
@@ -3489,7 +4056,9 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv) · 121 unmodified lines
3489	* The enabling order will be from lower to higher indexed wells,	4056	* The enabling order will be from lower to higher indexed wells,
3490	* the disabling order is reversed.	4057	* the disabling order is reversed.
3491	*/	4058	*/
3492	if (IS_GEN(dev_priv, 11)) {	4059	if (IS_GEN(dev_priv, 12)) {
		4060	err = set_power_wells(power_domains, tgl_power_wells);
		4061	} else if (IS_GEN(dev_priv, 11)) {
3493	err = set_power_wells(power_domains, icl_power_wells);	4062	err = set_power_wells(power_domains, icl_power_wells);
3494	} else if (IS_CANNONLAKE(dev_priv)) {	4063	} else if (IS_CANNONLAKE(dev_priv)) {
3495	err = set_power_wells(power_domains, cnl_power_wells);	4064	err = set_power_wells(power_domains, cnl_power_wells);
@@ -4337,7 +4906,7 @@ static void intel_power_domains_verify_state(struct drm_i915_private *dev_priv); · 841 unmodified lines
4337	*	4906	*
4338	* It will return with power domains disabled (to be enabled later by	4907	* It will return with power domains disabled (to be enabled later by
4339	* intel_power_domains_enable()) and must be paired with	4908	* intel_power_domains_enable()) and must be paired with
4340	* intel_power_domains_fini_hw().	4909	* intel_power_domains_driver_remove().
4341	*/	4910	*/
4342	void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)	4911	void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
4343	{	4912	{
@@ -4389,7 +4958,7 @@ void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume) · 45 unmodified lines
4389	}	4958	}
4390		4959
4391	/**	4960	/**
4392	* intel_power_domains_fini_hw - deinitialize hw power domain state	4961	* intel_power_domains_driver_remove - deinitialize hw power domain state
4393	* @i915: i915 device instance	4962	* @i915: i915 device instance
4394	*	4963	*
4395	* De-initializes the display power domain HW state. It also ensures that the	4964	* De-initializes the display power domain HW state. It also ensures that the
@@ -4399,7 +4968,7 @@ void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume) · 3 unmodified lines
4399	* intel_power_domains_disable()) and must be paired with	4968	* intel_power_domains_disable()) and must be paired with
4400	* intel_power_domains_init_hw().	4969	* intel_power_domains_init_hw().
4401	*/	4970	*/
4402	void intel_power_domains_fini_hw(struct drm_i915_private *i915)	4971	void intel_power_domains_driver_remove(struct drm_i915_private *i915)
4403	{	4972	{
4404	intel_wakeref_t wakeref __maybe_unused =	4973	intel_wakeref_t wakeref __maybe_unused =
4405	fetch_and_zero(&i915->power_domains.wakeref);	4974	fetch_and_zero(&i915->power_domains.wakeref);
@@ -4553,7 +5122,8 @@ static void intel_power_domains_dump_info(struct drm_i915_private *i915) · 147 unmodified lines
4553		5122
4554	for_each_power_domain(domain, power_well->desc->domains)	5123	for_each_power_domain(domain, power_well->desc->domains)
4555	DRM_DEBUG_DRIVER(" %-23s %d\n",	5124	DRM_DEBUG_DRIVER(" %-23s %d\n",
4556	intel_display_power_domain_str(domain),	5125	intel_display_power_domain_str(i915,
		5126	domain),
4557	power_domains->domain_use_count[domain]);	5127	power_domains->domain_use_count[domain]);
4558	}	5128	}
4559	}	5129	}

drivers/gpu/drm/i915/display/intel_display_power.h+32−3

 	POWER_DOMAIN_PIPE_A,
 	POWER_DOMAIN_PIPE_B,
 	POWER_DOMAIN_PIPE_C,
+	POWER_DOMAIN_PIPE_D,
 	POWER_DOMAIN_PIPE_A_PANEL_FITTER,
 	POWER_DOMAIN_PIPE_B_PANEL_FITTER,
 	POWER_DOMAIN_PIPE_C_PANEL_FITTER,
+	POWER_DOMAIN_PIPE_D_PANEL_FITTER,
 	POWER_DOMAIN_TRANSCODER_A,
 	POWER_DOMAIN_TRANSCODER_B,
 	POWER_DOMAIN_TRANSCODER_C,
+	POWER_DOMAIN_TRANSCODER_D,
 	POWER_DOMAIN_TRANSCODER_EDP,
-	POWER_DOMAIN_TRANSCODER_EDP_VDSC,
+	/* VDSC/joining for TRANSCODER_EDP (ICL) or TRANSCODER_A (TGL) */
+	POWER_DOMAIN_TRANSCODER_VDSC_PW2,
 	POWER_DOMAIN_TRANSCODER_DSI_A,
 	POWER_DOMAIN_TRANSCODER_DSI_C,
 	POWER_DOMAIN_PORT_DDI_A_LANES,
 	POWER_DOMAIN_PORT_DDI_B_LANES,
 	POWER_DOMAIN_PORT_DDI_C_LANES,
 	POWER_DOMAIN_PORT_DDI_D_LANES,
+	POWER_DOMAIN_PORT_DDI_TC1_LANES = POWER_DOMAIN_PORT_DDI_D_LANES,
 	POWER_DOMAIN_PORT_DDI_E_LANES,
+	POWER_DOMAIN_PORT_DDI_TC2_LANES = POWER_DOMAIN_PORT_DDI_E_LANES,
 	POWER_DOMAIN_PORT_DDI_F_LANES,
+	POWER_DOMAIN_PORT_DDI_TC3_LANES = POWER_DOMAIN_PORT_DDI_F_LANES,
+	POWER_DOMAIN_PORT_DDI_TC4_LANES,
+	POWER_DOMAIN_PORT_DDI_TC5_LANES,
+	POWER_DOMAIN_PORT_DDI_TC6_LANES,
 	POWER_DOMAIN_PORT_DDI_A_IO,
 	POWER_DOMAIN_PORT_DDI_B_IO,
 	POWER_DOMAIN_PORT_DDI_C_IO,
 	POWER_DOMAIN_PORT_DDI_D_IO,
+	POWER_DOMAIN_PORT_DDI_TC1_IO = POWER_DOMAIN_PORT_DDI_D_IO,
 	POWER_DOMAIN_PORT_DDI_E_IO,
+	POWER_DOMAIN_PORT_DDI_TC2_IO = POWER_DOMAIN_PORT_DDI_E_IO,
 	POWER_DOMAIN_PORT_DDI_F_IO,
+	POWER_DOMAIN_PORT_DDI_TC3_IO = POWER_DOMAIN_PORT_DDI_F_IO,
+	POWER_DOMAIN_PORT_DDI_G_IO,
+	POWER_DOMAIN_PORT_DDI_TC4_IO = POWER_DOMAIN_PORT_DDI_G_IO,
+	POWER_DOMAIN_PORT_DDI_H_IO,
+	POWER_DOMAIN_PORT_DDI_TC5_IO = POWER_DOMAIN_PORT_DDI_H_IO,
+	POWER_DOMAIN_PORT_DDI_I_IO,
+	POWER_DOMAIN_PORT_DDI_TC6_IO = POWER_DOMAIN_PORT_DDI_I_IO,
 	POWER_DOMAIN_PORT_DSI,
 	POWER_DOMAIN_PORT_CRT,
 	POWER_DOMAIN_PORT_OTHER,
 	POWER_DOMAIN_AUX_B,
 	POWER_DOMAIN_AUX_C,
 	POWER_DOMAIN_AUX_D,
+	POWER_DOMAIN_AUX_TC1 = POWER_DOMAIN_AUX_D,
 	POWER_DOMAIN_AUX_E,
+	POWER_DOMAIN_AUX_TC2 = POWER_DOMAIN_AUX_E,
 	POWER_DOMAIN_AUX_F,
+	POWER_DOMAIN_AUX_TC3 = POWER_DOMAIN_AUX_F,
+	POWER_DOMAIN_AUX_TC4,
+	POWER_DOMAIN_AUX_TC5,
+	POWER_DOMAIN_AUX_TC6,
 	POWER_DOMAIN_AUX_IO_A,
 	POWER_DOMAIN_AUX_TBT1,
 	POWER_DOMAIN_AUX_TBT2,
 	POWER_DOMAIN_AUX_TBT3,
 	POWER_DOMAIN_AUX_TBT4,
+	POWER_DOMAIN_AUX_TBT5,
+	POWER_DOMAIN_AUX_TBT6,
 	POWER_DOMAIN_GMBUS,
 	POWER_DOMAIN_MODESET,
 	POWER_DOMAIN_GT_IRQ,
+	POWER_DOMAIN_DPLL_DC_OFF,
 	POWER_DOMAIN_INIT,
 	POWER_DOMAIN_NUM,
 int intel_power_domains_init(struct drm_i915_private *dev_priv);
 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
-void intel_power_domains_fini_hw(struct drm_i915_private *dev_priv);
+void intel_power_domains_driver_remove(struct drm_i915_private *dev_priv);
 void icl_display_core_init(struct drm_i915_private *dev_priv, bool resume);
 void icl_display_core_uninit(struct drm_i915_private *dev_priv);
 void intel_power_domains_enable(struct drm_i915_private *dev_priv);
 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
 const char *
-intel_display_power_domain_str(enum intel_display_power_domain domain);
+intel_display_power_domain_str(struct drm_i915_private *i915,
+			       enum intel_display_power_domain domain);
 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 				    enum intel_display_power_domain domain);

drivers/gpu/drm/i915/display/intel_dp.c+45−247

@@ -62,6 +62,7 @@ · 61 unmodified lines
62	#include "intel_panel.h"	62	#include "intel_panel.h"
63	#include "intel_psr.h"	63	#include "intel_psr.h"
64	#include "intel_sideband.h"	64	#include "intel_sideband.h"
		65	#include "intel_tc.h"
65	#include "intel_vdsc.h"	66	#include "intel_vdsc.h"
66		67
67	#define DP_DPRX_ESI_LEN 14	68	#define DP_DPRX_ESI_LEN 14
@@ -211,47 +212,13 @@ static int intel_dp_max_common_rate(struct intel_dp *intel_dp) · 143 unmodified lines
211	return intel_dp->common_rates[intel_dp->num_common_rates - 1];	212	return intel_dp->common_rates[intel_dp->num_common_rates - 1];
212	}	213	}
213		214
214	static int intel_dp_get_fia_supported_lane_count(struct intel_dp *intel_dp)
215	{
216	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
217	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
218	enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
219	intel_wakeref_t wakeref;
220	u32 lane_info;
221
222	if (tc_port == PORT_TC_NONE \|\| dig_port->tc_type != TC_PORT_TYPEC)
223	return 4;
224
225	lane_info = 0;
226	with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
227	lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
228	DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
229	DP_LANE_ASSIGNMENT_SHIFT(tc_port);
230
231	switch (lane_info) {
232	default:
233	MISSING_CASE(lane_info);
234	/* fall through */
235	case 1:
236	case 2:
237	case 4:
238	case 8:
239	return 1;
240	case 3:
241	case 12:
242	return 2;
243	case 15:
244	return 4;
245	}
246	}
247
248	/* Theoretical max between source and sink */	215	/* Theoretical max between source and sink */
249	static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)	216	static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
250	{	217	{
251	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);	218	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
252	int source_max = intel_dig_port->max_lanes;	219	int source_max = intel_dig_port->max_lanes;
253	int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);	220	int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
254	int fia_max = intel_dp_get_fia_supported_lane_count(intel_dp);	221	int fia_max = intel_tc_port_fia_max_lane_count(intel_dig_port);
255		222
256	return min3(source_max, sink_max, fia_max);	223	return min3(source_max, sink_max, fia_max);
257	}	224	}
@@ -330,9 +297,9 @@ static int icl_max_source_rate(struct intel_dp *intel_dp) · 72 unmodified lines
330	{	297	{
331	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);	298	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
332	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);	299	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
333	enum port port = dig_port->base.port;	300	enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
334		301
335	if (intel_port_is_combophy(dev_priv, port) &&	302	if (intel_phy_is_combo(dev_priv, phy) &&
336	!IS_ELKHARTLAKE(dev_priv) &&	303	!IS_ELKHARTLAKE(dev_priv) &&
337	!intel_dp_is_edp(intel_dp))	304	!intel_dp_is_edp(intel_dp))
338	return 540000;	305	return 540000;
@@ -1209,7 +1176,7 @@ static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp, · 870 unmodified lines
1209	DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) \|	1176	DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) \|
1210	DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);	1177	DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1211		1178
1212	if (intel_dig_port->tc_type == TC_PORT_TBT)	1179	if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
1213	ret \|= DP_AUX_CH_CTL_TBT_IO;	1180	ret \|= DP_AUX_CH_CTL_TBT_IO;
1214		1181
1215	return ret;	1182	return ret;
@@ -1225,6 +1192,8 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp, · 9 unmodified lines
1225	struct drm_i915_private *i915 =	1192	struct drm_i915_private *i915 =
1226	to_i915(intel_dig_port->base.base.dev);	1193	to_i915(intel_dig_port->base.base.dev);
1227	struct intel_uncore *uncore = &i915->uncore;	1194	struct intel_uncore *uncore = &i915->uncore;
		1195	enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port);
		1196	bool is_tc_port = intel_phy_is_tc(i915, phy);
1228	i915_reg_t ch_ctl, ch_data[5];	1197	i915_reg_t ch_ctl, ch_data[5];
1229	u32 aux_clock_divider;	1198	u32 aux_clock_divider;
1230	enum intel_display_power_domain aux_domain =	1199	enum intel_display_power_domain aux_domain =
@@ -1240,6 +1209,9 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp, · 9 unmodified lines
1240	for (i = 0; i < ARRAY_SIZE(ch_data); i++)	1209	for (i = 0; i < ARRAY_SIZE(ch_data); i++)
1241	ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);	1210	ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
1242		1211
		1212	if (is_tc_port)
		1213	intel_tc_port_lock(intel_dig_port);
		1214
1243	aux_wakeref = intel_display_power_get(i915, aux_domain);	1215	aux_wakeref = intel_display_power_get(i915, aux_domain);
1244	pps_wakeref = pps_lock(intel_dp);	1216	pps_wakeref = pps_lock(intel_dp);
1245		1217
@@ -1392,6 +1364,9 @@ out: · 146 unmodified lines
1392	pps_unlock(intel_dp, pps_wakeref);	1364	pps_unlock(intel_dp, pps_wakeref);
1393	intel_display_power_put_async(i915, aux_domain, aux_wakeref);	1365	intel_display_power_put_async(i915, aux_domain, aux_wakeref);
1394		1366
		1367	if (is_tc_port)
		1368	intel_tc_port_unlock(intel_dig_port);
		1369
1395	return ret;	1370	return ret;
1396	}	1371	}
1397		1372
@@ -1879,8 +1854,10 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, · 481 unmodified lines
1879	int mode_rate, link_clock, link_avail;	1854	int mode_rate, link_clock, link_avail;
1880		1855
1881	for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {	1856	for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
		1857	int output_bpp = intel_dp_output_bpp(pipe_config, bpp);
		1858
1882	mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,	1859	mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1883	bpp);	1860	output_bpp);
1884		1861
1885	for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {	1862	for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1886	for (lane_count = limits->min_lane_count;	1863	for (lane_count = limits->min_lane_count;
@@ -4244,8 +4221,14 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp) · 2357 unmodified lines
4244	if (!intel_dp_read_dpcd(intel_dp))	4221	if (!intel_dp_read_dpcd(intel_dp))
4245	return false;	4222	return false;
4246		4223
4247	/* Don't clobber cached eDP rates. */	4224	/*
		4225	* Don't clobber cached eDP rates. Also skip re-reading
		4226	* the OUI/ID since we know it won't change.
		4227	*/
4248	if (!intel_dp_is_edp(intel_dp)) {	4228	if (!intel_dp_is_edp(intel_dp)) {
		4229	drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
		4230	drm_dp_is_branch(intel_dp->dpcd));
		4231
4249	intel_dp_set_sink_rates(intel_dp);	4232	intel_dp_set_sink_rates(intel_dp);
4250	intel_dp_set_common_rates(intel_dp);	4233	intel_dp_set_common_rates(intel_dp);
4251	}	4234	}
@@ -4254,7 +4237,8 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp) · 2 unmodified lines
4254	* Some eDP panels do not set a valid value for sink count, that is why	4237	* Some eDP panels do not set a valid value for sink count, that is why
4255	* it don't care about read it here and in intel_edp_init_dpcd().	4238	* it don't care about read it here and in intel_edp_init_dpcd().
4256	*/	4239	*/
4257	if (!intel_dp_is_edp(intel_dp)) {	4240	if (!intel_dp_is_edp(intel_dp) &&
		4241	!drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_SINK_COUNT)) {
4258	u8 count;	4242	u8 count;
4259	ssize_t r;	4243	ssize_t r;
4260		4244
@@ -4879,14 +4863,16 @@ int intel_dp_retrain_link(struct intel_encoder *encoder, · 618 unmodified lines
4879	* retrain the link to get a picture. That's in case no	4863	* retrain the link to get a picture. That's in case no
4880	* userspace component reacted to intermittent HPD dip.	4864	* userspace component reacted to intermittent HPD dip.
4881	*/	4865	*/
4882	static bool intel_dp_hotplug(struct intel_encoder *encoder,	4866	static enum intel_hotplug_state
4883	struct intel_connector *connector)	4867	intel_dp_hotplug(struct intel_encoder *encoder,
		4868	struct intel_connector *connector,
		4869	bool irq_received)
4884	{	4870	{
4885	struct drm_modeset_acquire_ctx ctx;	4871	struct drm_modeset_acquire_ctx ctx;
4886	bool changed;	4872	enum intel_hotplug_state state;
4887	int ret;	4873	int ret;
4888		4874
4889	changed = intel_encoder_hotplug(encoder, connector);	4875	state = intel_encoder_hotplug(encoder, connector, irq_received);
4890		4876
4891	drm_modeset_acquire_init(&ctx, 0);	4877	drm_modeset_acquire_init(&ctx, 0);
4892		4878
@@ -4905,7 +4891,14 @@ static bool intel_dp_hotplug(struct intel_encoder *encoder, · 12 unmodified lines
4905	drm_modeset_acquire_fini(&ctx);	4891	drm_modeset_acquire_fini(&ctx);
4906	WARN(ret, "Acquiring modeset locks failed with %i\n", ret);	4892	WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4907		4893
4908	return changed;	4894	/*
		4895	* Keeping it consistent with intel_ddi_hotplug() and
		4896	* intel_hdmi_hotplug().
		4897	*/
		4898	if (state == INTEL_HOTPLUG_UNCHANGED && irq_received)
		4899	state = INTEL_HOTPLUG_RETRY;
		4900
		4901	return state;
4909	}	4902	}
4910		4903
4911	static void intel_dp_check_service_irq(struct intel_dp *intel_dp)	4904	static void intel_dp_check_service_irq(struct intel_dp *intel_dp)
@@ -5233,204 +5226,16 @@ static bool icl_combo_port_connected(struct drm_i915_private *dev_priv, · 321 unmodified lines
5233	return I915_READ(SDEISR) & SDE_DDI_HOTPLUG_ICP(port);	5226	return I915_READ(SDEISR) & SDE_DDI_HOTPLUG_ICP(port);
5234	}	5227	}
5235		5228
5236	static const char *tc_type_name(enum tc_port_type type)
5237	{
5238	static const char * const names[] = {
5239	[TC_PORT_UNKNOWN] = "unknown",
5240	[TC_PORT_LEGACY] = "legacy",
5241	[TC_PORT_TYPEC] = "typec",
5242	[TC_PORT_TBT] = "tbt",
5243	};
5244
5245	if (WARN_ON(type >= ARRAY_SIZE(names)))
5246	type = TC_PORT_UNKNOWN;
5247
5248	return names[type];
5249	}
5250
5251	static void icl_update_tc_port_type(struct drm_i915_private *dev_priv,
5252	struct intel_digital_port *intel_dig_port,
5253	bool is_legacy, bool is_typec, bool is_tbt)
5254	{
5255	enum port port = intel_dig_port->base.port;
5256	enum tc_port_type old_type = intel_dig_port->tc_type;
5257
5258	WARN_ON(is_legacy + is_typec + is_tbt != 1);
5259
5260	if (is_legacy)
5261	intel_dig_port->tc_type = TC_PORT_LEGACY;
5262	else if (is_typec)
5263	intel_dig_port->tc_type = TC_PORT_TYPEC;
5264	else if (is_tbt)
5265	intel_dig_port->tc_type = TC_PORT_TBT;
5266	else
5267	return;
5268
5269	/* Types are not supposed to be changed at runtime. */
5270	WARN_ON(old_type != TC_PORT_UNKNOWN &&
5271	old_type != intel_dig_port->tc_type);
5272
5273	if (old_type != intel_dig_port->tc_type)
5274	DRM_DEBUG_KMS("Port %c has TC type %s\n", port_name(port),
5275	tc_type_name(intel_dig_port->tc_type));
5276	}
5277
5278	/*
5279	* This function implements the first part of the Connect Flow described by our
5280	* specification, Gen11 TypeC Programming chapter. The rest of the flow (reading
5281	* lanes, EDID, etc) is done as needed in the typical places.
5282	*
5283	* Unlike the other ports, type-C ports are not available to use as soon as we
5284	* get a hotplug. The type-C PHYs can be shared between multiple controllers:
5285	* display, USB, etc. As a result, handshaking through FIA is required around
5286	* connect and disconnect to cleanly transfer ownership with the controller and
5287	* set the type-C power state.
5288	*
5289	* We could opt to only do the connect flow when we actually try to use the AUX
5290	* channels or do a modeset, then immediately run the disconnect flow after
5291	* usage, but there are some implications on this for a dynamic environment:
5292	* things may go away or change behind our backs. So for now our driver is
5293	* always trying to acquire ownership of the controller as soon as it gets an
5294	* interrupt (or polls state and sees a port is connected) and only gives it
5295	* back when it sees a disconnect. Implementation of a more fine-grained model
5296	* will require a lot of coordination with user space and thorough testing for
5297	* the extra possible cases.
5298	*/
5299	static bool icl_tc_phy_connect(struct drm_i915_private *dev_priv,
5300	struct intel_digital_port *dig_port)
5301	{
5302	enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
5303	u32 val;
5304
5305	if (dig_port->tc_type != TC_PORT_LEGACY &&
5306	dig_port->tc_type != TC_PORT_TYPEC)
5307	return true;
5308
5309	val = I915_READ(PORT_TX_DFLEXDPPMS);
5310	if (!(val & DP_PHY_MODE_STATUS_COMPLETED(tc_port))) {
5311	DRM_DEBUG_KMS("DP PHY for TC port %d not ready\n", tc_port);
5312	WARN_ON(dig_port->tc_legacy_port);
5313	return false;
5314	}
5315
5316	/*
5317	* This function may be called many times in a row without an HPD event
5318	* in between, so try to avoid the write when we can.
5319	*/
5320	val = I915_READ(PORT_TX_DFLEXDPCSSS);
5321	if (!(val & DP_PHY_MODE_STATUS_NOT_SAFE(tc_port))) {
5322	val \|= DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
5323	I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
5324	}
5325
5326	/*
5327	* Now we have to re-check the live state, in case the port recently
5328	* became disconnected. Not necessary for legacy mode.
5329	*/
5330	if (dig_port->tc_type == TC_PORT_TYPEC &&
5331	!(I915_READ(PORT_TX_DFLEXDPSP) & TC_LIVE_STATE_TC(tc_port))) {
5332	DRM_DEBUG_KMS("TC PHY %d sudden disconnect.\n", tc_port);
5333	icl_tc_phy_disconnect(dev_priv, dig_port);
5334	return false;
5335	}
5336
5337	return true;
5338	}
5339
5340	/*
5341	* See the comment at the connect function. This implements the Disconnect
5342	* Flow.
5343	*/
5344	void icl_tc_phy_disconnect(struct drm_i915_private *dev_priv,
5345	struct intel_digital_port *dig_port)
5346	{
5347	enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
5348
5349	if (dig_port->tc_type == TC_PORT_UNKNOWN)
5350	return;
5351
5352	/*
5353	* TBT disconnection flow is read the live status, what was done in
5354	* caller.
5355	*/
5356	if (dig_port->tc_type == TC_PORT_TYPEC \|\|
5357	dig_port->tc_type == TC_PORT_LEGACY) {
5358	u32 val;
5359
5360	val = I915_READ(PORT_TX_DFLEXDPCSSS);
5361	val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
5362	I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
5363	}
5364
5365	DRM_DEBUG_KMS("Port %c TC type %s disconnected\n",
5366	port_name(dig_port->base.port),
5367	tc_type_name(dig_port->tc_type));
5368
5369	dig_port->tc_type = TC_PORT_UNKNOWN;
5370	}
5371
5372	/*
5373	* The type-C ports are different because even when they are connected, they may
5374	* not be available/usable by the graphics driver: see the comment on
5375	* icl_tc_phy_connect(). So in our driver instead of adding the additional
5376	* concept of "usable" and make everything check for "connected and usable" we
5377	* define a port as "connected" when it is not only connected, but also when it
5378	* is usable by the rest of the driver. That maintains the old assumption that
5379	* connected ports are usable, and avoids exposing to the users objects they
5380	* can't really use.
5381	*/
5382	static bool icl_tc_port_connected(struct drm_i915_private *dev_priv,
5383	struct intel_digital_port *intel_dig_port)
5384	{
5385	enum port port = intel_dig_port->base.port;
5386	enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
5387	bool is_legacy, is_typec, is_tbt;
5388	u32 dpsp;
5389
5390	/*
5391	* Complain if we got a legacy port HPD, but VBT didn't mark the port as
5392	* legacy. Treat the port as legacy from now on.
5393	*/
5394	if (!intel_dig_port->tc_legacy_port &&
5395	I915_READ(SDEISR) & SDE_TC_HOTPLUG_ICP(tc_port)) {
5396	DRM_ERROR("VBT incorrectly claims port %c is not TypeC legacy\n",
5397	port_name(port));
5398	intel_dig_port->tc_legacy_port = true;
5399	}
5400	is_legacy = intel_dig_port->tc_legacy_port;
5401
5402	/*
5403	* The spec says we shouldn't be using the ISR bits for detecting
5404	* between TC and TBT. We should use DFLEXDPSP.
5405	*/
5406	dpsp = I915_READ(PORT_TX_DFLEXDPSP);
5407	is_typec = dpsp & TC_LIVE_STATE_TC(tc_port);
5408	is_tbt = dpsp & TC_LIVE_STATE_TBT(tc_port);
5409
5410	if (!is_legacy && !is_typec && !is_tbt) {
5411	icl_tc_phy_disconnect(dev_priv, intel_dig_port);
5412
5413	return false;
5414	}
5415
5416	icl_update_tc_port_type(dev_priv, intel_dig_port, is_legacy, is_typec,
5417	is_tbt);
5418
5419	if (!icl_tc_phy_connect(dev_priv, intel_dig_port))
5420	return false;
5421
5422	return true;
5423	}
5424
5425	static bool icl_digital_port_connected(struct intel_encoder *encoder)	5229	static bool icl_digital_port_connected(struct intel_encoder *encoder)
5426	{	5230	{
5427	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);	5231	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5428	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);	5232	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
		5233	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
5429		5234
5430	if (intel_port_is_combophy(dev_priv, encoder->port))	5235	if (intel_phy_is_combo(dev_priv, phy))
5431	return icl_combo_port_connected(dev_priv, dig_port);	5236	return icl_combo_port_connected(dev_priv, dig_port);
5432	else if (intel_port_is_tc(dev_priv, encoder->port))	5237	else if (intel_phy_is_tc(dev_priv, phy))
5433	return icl_tc_port_connected(dev_priv, dig_port);	5238	return intel_tc_port_connected(dig_port);
5434	else	5239	else
5435	MISSING_CASE(encoder->hpd_pin);	5240	MISSING_CASE(encoder->hpd_pin);
5436		5241
@@ -5588,9 +5393,6 @@ intel_dp_detect(struct drm_connector *connector, · 151 unmodified lines
5588	if (INTEL_GEN(dev_priv) >= 11)	5393	if (INTEL_GEN(dev_priv) >= 11)
5589	intel_dp_get_dsc_sink_cap(intel_dp);	5394	intel_dp_get_dsc_sink_cap(intel_dp);
5590		5395
5591	drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
5592	drm_dp_is_branch(intel_dp->dpcd));
5593
5594	intel_dp_configure_mst(intel_dp);	5396	intel_dp_configure_mst(intel_dp);
5595		5397
5596	if (intel_dp->is_mst) {	5398	if (intel_dp->is_mst) {
@@ -6835,8 +6637,6 @@ static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv, · 1238 unmodified lines
6835	const struct intel_crtc_state *crtc_state,	6637	const struct intel_crtc_state *crtc_state,
6836	int refresh_rate)	6638	int refresh_rate)
6837	{	6639	{
6838	struct intel_encoder *encoder;
6839	struct intel_digital_port *dig_port = NULL;
6840	struct intel_dp *intel_dp = dev_priv->drrs.dp;	6640	struct intel_dp *intel_dp = dev_priv->drrs.dp;
6841	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);	6641	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
6842	enum drrs_refresh_rate_type index = DRRS_HIGH_RR;	6642	enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
@@ -6851,9 +6651,6 @@ static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv, · 8 unmodified lines
6851	return;	6651	return;
6852	}	6652	}
6853		6653
6854	dig_port = dp_to_dig_port(intel_dp);
6855	encoder = &dig_port->base;
6856
6857	if (!intel_crtc) {	6654	if (!intel_crtc) {
6858	DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");	6655	DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
6859	return;	6656	return;
@@ -7333,6 +7130,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, · 473 unmodified lines
7333	struct drm_device *dev = intel_encoder->base.dev;	7130	struct drm_device *dev = intel_encoder->base.dev;
7334	struct drm_i915_private *dev_priv = to_i915(dev);	7131	struct drm_i915_private *dev_priv = to_i915(dev);
7335	enum port port = intel_encoder->port;	7132	enum port port = intel_encoder->port;
		7133	enum phy phy = intel_port_to_phy(dev_priv, port);
7336	int type;	7134	int type;
7337		7135
7338	/* Initialize the work for modeset in case of link train failure */	7136	/* Initialize the work for modeset in case of link train failure */
@@ -7359,7 +7157,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, · 20 unmodified lines
7359	* Currently we don't support eDP on TypeC ports, although in	7157	* Currently we don't support eDP on TypeC ports, although in
7360	* theory it could work on TypeC legacy ports.	7158	* theory it could work on TypeC legacy ports.
7361	*/	7159	*/
7362	WARN_ON(intel_port_is_tc(dev_priv, port));	7160	WARN_ON(intel_phy_is_tc(dev_priv, phy));
7363	type = DRM_MODE_CONNECTOR_eDP;	7161	type = DRM_MODE_CONNECTOR_eDP;
7364	} else {	7162	} else {
7365	type = DRM_MODE_CONNECTOR_DisplayPort;	7163	type = DRM_MODE_CONNECTOR_DisplayPort;

drivers/gpu/drm/i915/display/intel_dp.h+0−2

@@ -112,8 +112,6 @@ bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp); · 111 unmodified lines
112	int intel_dp_link_required(int pixel_clock, int bpp);	112	int intel_dp_link_required(int pixel_clock, int bpp);
113	int intel_dp_max_data_rate(int max_link_clock, int max_lanes);	113	int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
114	bool intel_digital_port_connected(struct intel_encoder *encoder);	114	bool intel_digital_port_connected(struct intel_encoder *encoder);
115	void icl_tc_phy_disconnect(struct drm_i915_private *dev_priv,
116	struct intel_digital_port *dig_port);
117		115
118	static inline unsigned int intel_dp_unused_lane_mask(int lane_count)	116	static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
119	{	117	{

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c+4−1

 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector)
 {
 	struct intel_panel *panel = &intel_connector->panel;
+	struct drm_i915_private *dev_priv = to_i915(intel_connector->base.dev);
-	if (!i915_modparams.enable_dpcd_backlight)
+	if (i915_modparams.enable_dpcd_backlight == 0 ||
+	    (i915_modparams.enable_dpcd_backlight == -1 &&
+	    dev_priv->vbt.backlight.type != INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE))
 		return -ENODEV;
 	if (!intel_dp_aux_display_control_capable(intel_connector))

drivers/gpu/drm/i915/display/intel_dp_mst.h+7−1

 #ifndef __INTEL_DP_MST_H__
 #define __INTEL_DP_MST_H__
-struct intel_digital_port;
+#include "intel_drv.h"
 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
+static inline int
+intel_dp_mst_encoder_active_links(struct intel_digital_port *intel_dig_port)
+{
+	return intel_dig_port->dp.active_mst_links;
+}
 #endif /* __INTEL_DP_MST_H__ */

drivers/gpu/drm/i915/display/intel_dpll_mgr.c+478−174

@@ -36,9 +36,10 @@ · 35 unmodified lines
36	* This file provides an abstraction over display PLLs. The function	36	* This file provides an abstraction over display PLLs. The function
37	* intel_shared_dpll_init() initializes the PLLs for the given platform. The	37	* intel_shared_dpll_init() initializes the PLLs for the given platform. The
38	* users of a PLL are tracked and that tracking is integrated with the atomic	38	* users of a PLL are tracked and that tracking is integrated with the atomic
39	* modest interface. During an atomic operation, a PLL can be requested for a	39	* modset interface. During an atomic operation, required PLLs can be reserved
40	* given CRTC and encoder configuration by calling intel_get_shared_dpll() and	40	* for a given CRTC and encoder configuration by calling
41	* a previously used PLL can be released with intel_release_shared_dpll().	41	* intel_reserve_shared_dplls() and previously reserved PLLs can be released
		42	* with intel_release_shared_dplls().
42	* Changes to the users are first staged in the atomic state, and then made	43	* Changes to the users are first staged in the atomic state, and then made
43	* effective by calling intel_shared_dpll_swap_state() during the atomic	44	* effective by calling intel_shared_dpll_swap_state() during the atomic
44	* commit phase.	45	* commit phase.
@@ -243,17 +244,18 @@ out: · 198 unmodified lines
243	}	244	}
244		245
245	static struct intel_shared_dpll *	246	static struct intel_shared_dpll *
246	intel_find_shared_dpll(struct intel_crtc_state *crtc_state,	247	intel_find_shared_dpll(struct intel_atomic_state *state,
		248	const struct intel_crtc *crtc,
		249	const struct intel_dpll_hw_state *pll_state,
247	enum intel_dpll_id range_min,	250	enum intel_dpll_id range_min,
248	enum intel_dpll_id range_max)	251	enum intel_dpll_id range_max)
249	{	252	{
250	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
251	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);	253	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
252	struct intel_shared_dpll pll, unused_pll = NULL;	254	struct intel_shared_dpll pll, unused_pll = NULL;
253	struct intel_shared_dpll_state *shared_dpll;	255	struct intel_shared_dpll_state *shared_dpll;
254	enum intel_dpll_id i;	256	enum intel_dpll_id i;
255		257
256	shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);	258	shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
257		259
258	for (i = range_min; i <= range_max; i++) {	260	for (i = range_min; i <= range_max; i++) {
259	pll = &dev_priv->shared_dplls[i];	261	pll = &dev_priv->shared_dplls[i];
@@ -265,9 +267,9 @@ intel_find_shared_dpll(struct intel_crtc_state *crtc_state, · 5 unmodified lines
265	continue;	267	continue;
266	}	268	}
267		269
268	if (memcmp(&crtc_state->dpll_hw_state,	270	if (memcmp(pll_state,
269	&shared_dpll[i].hw_state,	271	&shared_dpll[i].hw_state,
270	sizeof(crtc_state->dpll_hw_state)) == 0) {	272	sizeof(*pll_state)) == 0) {
271	DRM_DEBUG_KMS("[CRTC:%d:%s] sharing existing %s (crtc mask 0x%08x, active %x)\n",	273	DRM_DEBUG_KMS("[CRTC:%d:%s] sharing existing %s (crtc mask 0x%08x, active %x)\n",
272	crtc->base.base.id, crtc->base.name,	274	crtc->base.base.id, crtc->base.name,
273	pll->info->name,	275	pll->info->name,
@@ -289,26 +291,51 @@ intel_find_shared_dpll(struct intel_crtc_state *crtc_state, · 15 unmodified lines
289	}	291	}
290		292
291	static void	293	static void
292	intel_reference_shared_dpll(struct intel_shared_dpll *pll,	294	intel_reference_shared_dpll(struct intel_atomic_state *state,
293	struct intel_crtc_state *crtc_state)	295	const struct intel_crtc *crtc,
		296	const struct intel_shared_dpll *pll,
		297	const struct intel_dpll_hw_state *pll_state)
294	{	298	{
295	struct intel_shared_dpll_state *shared_dpll;	299	struct intel_shared_dpll_state *shared_dpll;
296	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
297	const enum intel_dpll_id id = pll->info->id;	300	const enum intel_dpll_id id = pll->info->id;
298		301
299	shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);	302	shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
300		303
301	if (shared_dpll[id].crtc_mask == 0)	304	if (shared_dpll[id].crtc_mask == 0)
302	shared_dpll[id].hw_state =	305	shared_dpll[id].hw_state = *pll_state;
303	crtc_state->dpll_hw_state;
304		306
305	crtc_state->shared_dpll = pll;
306	DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->info->name,	307	DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->info->name,
307	pipe_name(crtc->pipe));	308	pipe_name(crtc->pipe));
308		309
309	shared_dpll[id].crtc_mask \|= 1 << crtc->pipe;	310	shared_dpll[id].crtc_mask \|= 1 << crtc->pipe;
310	}	311	}
311		312
		313	static void intel_unreference_shared_dpll(struct intel_atomic_state *state,
		314	const struct intel_crtc *crtc,
		315	const struct intel_shared_dpll *pll)
		316	{
		317	struct intel_shared_dpll_state *shared_dpll;
		318
		319	shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
		320	shared_dpll[pll->info->id].crtc_mask &= ~(1 << crtc->pipe);
		321	}
		322
		323	static void intel_put_dpll(struct intel_atomic_state *state,
		324	struct intel_crtc *crtc)
		325	{
		326	const struct intel_crtc_state *old_crtc_state =
		327	intel_atomic_get_old_crtc_state(state, crtc);
		328	struct intel_crtc_state *new_crtc_state =
		329	intel_atomic_get_new_crtc_state(state, crtc);
		330
		331	new_crtc_state->shared_dpll = NULL;
		332
		333	if (!old_crtc_state->shared_dpll)
		334	return;
		335
		336	intel_unreference_shared_dpll(state, crtc, old_crtc_state->shared_dpll);
		337	}
		338
312	/**	339	/**
313	* intel_shared_dpll_swap_state - make atomic DPLL configuration effective	340	* intel_shared_dpll_swap_state - make atomic DPLL configuration effective
314	* @state: atomic state	341	* @state: atomic state
@@ -320,25 +347,20 @@ intel_reference_shared_dpll(struct intel_shared_dpll *pll, · 5 unmodified lines
320	* i.e. it also puts the current state into @state, even though there is no	347	* i.e. it also puts the current state into @state, even though there is no
321	* need for that at this moment.	348	* need for that at this moment.
322	*/	349	*/
323	void intel_shared_dpll_swap_state(struct drm_atomic_state *state)	350	void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
324	{	351	{
325	struct drm_i915_private *dev_priv = to_i915(state->dev);	352	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
326	struct intel_shared_dpll_state *shared_dpll;	353	struct intel_shared_dpll_state *shared_dpll = state->shared_dpll;
327	struct intel_shared_dpll *pll;
328	enum intel_dpll_id i;	354	enum intel_dpll_id i;
329		355
330	if (!to_intel_atomic_state(state)->dpll_set)	356	if (!state->dpll_set)
331	return;	357	return;
332		358
333	shared_dpll = to_intel_atomic_state(state)->shared_dpll;
334	for (i = 0; i < dev_priv->num_shared_dpll; i++) {	359	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
335	struct intel_shared_dpll_state tmp;	360	struct intel_shared_dpll *pll =
		361	&dev_priv->shared_dplls[i];
336		362
337	pll = &dev_priv->shared_dplls[i];	363	swap(pll->state, shared_dpll[i]);
338
339	tmp = pll->state;
340	pll->state = shared_dpll[i];
341	shared_dpll[i] = tmp;
342	}	364	}
343	}	365	}
344		366
@@ -421,11 +443,12 @@ static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, · 76 unmodified lines
421	udelay(200);	443	udelay(200);
422	}	444	}
423		445
424	static struct intel_shared_dpll *	446	static bool ibx_get_dpll(struct intel_atomic_state *state,
425	ibx_get_dpll(struct intel_crtc_state *crtc_state,	447	struct intel_crtc *crtc,
426	struct intel_encoder *encoder)	448	struct intel_encoder *encoder)
427	{	449	{
428	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);	450	struct intel_crtc_state *crtc_state =
		451	intel_atomic_get_new_crtc_state(state, crtc);
429	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);	452	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
430	struct intel_shared_dpll *pll;	453	struct intel_shared_dpll *pll;
431	enum intel_dpll_id i;	454	enum intel_dpll_id i;
@@ -439,18 +462,22 @@ ibx_get_dpll(struct intel_crtc_state *crtc_state, · 7 unmodified lines
439	crtc->base.base.id, crtc->base.name,	462	crtc->base.base.id, crtc->base.name,
440	pll->info->name);	463	pll->info->name);
441	} else {	464	} else {
442	pll = intel_find_shared_dpll(crtc_state,	465	pll = intel_find_shared_dpll(state, crtc,
		466	&crtc_state->dpll_hw_state,
443	DPLL_ID_PCH_PLL_A,	467	DPLL_ID_PCH_PLL_A,
444	DPLL_ID_PCH_PLL_B);	468	DPLL_ID_PCH_PLL_B);
445	}	469	}
446		470
447	if (!pll)	471	if (!pll)
448	return NULL;	472	return false;
449		473
450	/* reference the pll */	474	/* reference the pll */
451	intel_reference_shared_dpll(pll, crtc_state);	475	intel_reference_shared_dpll(state, crtc,
		476	pll, &crtc_state->dpll_hw_state);
452		477
453	return pll;	478	crtc_state->shared_dpll = pll;
		479
		480	return true;
454	}	481	}
455		482
456	static void ibx_dump_hw_state(struct drm_i915_private *dev_priv,	483	static void ibx_dump_hw_state(struct drm_i915_private *dev_priv,
@@ -767,8 +794,12 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */, · 310 unmodified lines
767	*r2_out = best.r2;	794	*r2_out = best.r2;
768	}	795	}
769		796
770	static struct intel_shared_dpll hsw_ddi_hdmi_get_dpll(struct intel_crtc_state crtc_state)	797	static struct intel_shared_dpll *
		798	hsw_ddi_hdmi_get_dpll(struct intel_atomic_state *state,
		799	struct intel_crtc *crtc)
771	{	800	{
		801	struct intel_crtc_state *crtc_state =
		802	intel_atomic_get_new_crtc_state(state, crtc);
772	struct intel_shared_dpll *pll;	803	struct intel_shared_dpll *pll;
773	u32 val;	804	u32 val;
774	unsigned int p, n2, r2;	805	unsigned int p, n2, r2;
@@ -781,7 +812,8 @@ static struct intel_shared_dpll hsw_ddi_hdmi_get_dpll(struct intel_crtc_state · 6 unmodified lines
781		812
782	crtc_state->dpll_hw_state.wrpll = val;	813	crtc_state->dpll_hw_state.wrpll = val;
783		814
784	pll = intel_find_shared_dpll(crtc_state,	815	pll = intel_find_shared_dpll(state, crtc,
		816	&crtc_state->dpll_hw_state,
785	DPLL_ID_WRPLL1, DPLL_ID_WRPLL2);	817	DPLL_ID_WRPLL1, DPLL_ID_WRPLL2);
786		818
787	if (!pll)	819	if (!pll)
@@ -821,38 +853,44 @@ hsw_ddi_dp_get_dpll(struct intel_crtc_state *crtc_state) · 33 unmodified lines
821	return pll;	853	return pll;
822	}	854	}
823		855
824	static struct intel_shared_dpll *	856	static bool hsw_get_dpll(struct intel_atomic_state *state,
825	hsw_get_dpll(struct intel_crtc_state *crtc_state,	857	struct intel_crtc *crtc,
826	struct intel_encoder *encoder)	858	struct intel_encoder *encoder)
827	{	859	{
		860	struct intel_crtc_state *crtc_state =
		861	intel_atomic_get_new_crtc_state(state, crtc);
828	struct intel_shared_dpll *pll;	862	struct intel_shared_dpll *pll;
829		863
830	memset(&crtc_state->dpll_hw_state, 0,	864	memset(&crtc_state->dpll_hw_state, 0,
831	sizeof(crtc_state->dpll_hw_state));	865	sizeof(crtc_state->dpll_hw_state));
832		866
833	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {	867	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
834	pll = hsw_ddi_hdmi_get_dpll(crtc_state);	868	pll = hsw_ddi_hdmi_get_dpll(state, crtc);
835	} else if (intel_crtc_has_dp_encoder(crtc_state)) {	869	} else if (intel_crtc_has_dp_encoder(crtc_state)) {
836	pll = hsw_ddi_dp_get_dpll(crtc_state);	870	pll = hsw_ddi_dp_get_dpll(crtc_state);
837	} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {	871	} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
838	if (WARN_ON(crtc_state->port_clock / 2 != 135000))	872	if (WARN_ON(crtc_state->port_clock / 2 != 135000))
839	return NULL;	873	return false;
840		874
841	crtc_state->dpll_hw_state.spll =	875	crtc_state->dpll_hw_state.spll =
842	SPLL_PLL_ENABLE \| SPLL_FREQ_1350MHz \| SPLL_REF_MUXED_SSC;	876	SPLL_PLL_ENABLE \| SPLL_FREQ_1350MHz \| SPLL_REF_MUXED_SSC;
843		877
844	pll = intel_find_shared_dpll(crtc_state,	878	pll = intel_find_shared_dpll(state, crtc,
		879	&crtc_state->dpll_hw_state,
845	DPLL_ID_SPLL, DPLL_ID_SPLL);	880	DPLL_ID_SPLL, DPLL_ID_SPLL);
846	} else {	881	} else {
847	return NULL;	882	return false;
848	}	883	}
849		884
850	if (!pll)	885	if (!pll)
851	return NULL;	886	return false;
852		887
853	intel_reference_shared_dpll(pll, crtc_state);	888	intel_reference_shared_dpll(state, crtc,
		889	pll, &crtc_state->dpll_hw_state);
854		890
855	return pll;	891	crtc_state->shared_dpll = pll;
		892
		893	return true;
856	}	894	}
857		895
858	static void hsw_dump_hw_state(struct drm_i915_private *dev_priv,	896	static void hsw_dump_hw_state(struct drm_i915_private *dev_priv,
@@ -1385,10 +1423,12 @@ skl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state) · 526 unmodified lines
1385	return true;	1423	return true;
1386	}	1424	}
1387		1425
1388	static struct intel_shared_dpll *	1426	static bool skl_get_dpll(struct intel_atomic_state *state,
1389	skl_get_dpll(struct intel_crtc_state *crtc_state,	1427	struct intel_crtc *crtc,
1390	struct intel_encoder *encoder)	1428	struct intel_encoder *encoder)
1391	{	1429	{
		1430	struct intel_crtc_state *crtc_state =
		1431	intel_atomic_get_new_crtc_state(state, crtc);
1392	struct intel_shared_dpll *pll;	1432	struct intel_shared_dpll *pll;
1393	bool bret;	1433	bool bret;
1394		1434
@@ -1396,32 +1436,37 @@ skl_get_dpll(struct intel_crtc_state *crtc_state, · 1 unmodified line
1396	bret = skl_ddi_hdmi_pll_dividers(crtc_state);	1436	bret = skl_ddi_hdmi_pll_dividers(crtc_state);
1397	if (!bret) {	1437	if (!bret) {
1398	DRM_DEBUG_KMS("Could not get HDMI pll dividers.\n");	1438	DRM_DEBUG_KMS("Could not get HDMI pll dividers.\n");
1399	return NULL;	1439	return false;
1400	}	1440	}
1401	} else if (intel_crtc_has_dp_encoder(crtc_state)) {	1441	} else if (intel_crtc_has_dp_encoder(crtc_state)) {
1402	bret = skl_ddi_dp_set_dpll_hw_state(crtc_state);	1442	bret = skl_ddi_dp_set_dpll_hw_state(crtc_state);
1403	if (!bret) {	1443	if (!bret) {
1404	DRM_DEBUG_KMS("Could not set DP dpll HW state.\n");	1444	DRM_DEBUG_KMS("Could not set DP dpll HW state.\n");
1405	return NULL;	1445	return false;
1406	}	1446	}
1407	} else {	1447	} else {
1408	return NULL;	1448	return false;
1409	}	1449	}
1410		1450
1411	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))	1451	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1412	pll = intel_find_shared_dpll(crtc_state,	1452	pll = intel_find_shared_dpll(state, crtc,
		1453	&crtc_state->dpll_hw_state,
1413	DPLL_ID_SKL_DPLL0,	1454	DPLL_ID_SKL_DPLL0,
1414	DPLL_ID_SKL_DPLL0);	1455	DPLL_ID_SKL_DPLL0);
1415	else	1456	else
1416	pll = intel_find_shared_dpll(crtc_state,	1457	pll = intel_find_shared_dpll(state, crtc,
		1458	&crtc_state->dpll_hw_state,
1417	DPLL_ID_SKL_DPLL1,	1459	DPLL_ID_SKL_DPLL1,
1418	DPLL_ID_SKL_DPLL3);	1460	DPLL_ID_SKL_DPLL3);
1419	if (!pll)	1461	if (!pll)
1420	return NULL;	1462	return false;
1421		1463
1422	intel_reference_shared_dpll(pll, crtc_state);	1464	intel_reference_shared_dpll(state, crtc,
		1465	pll, &crtc_state->dpll_hw_state);
1423		1466
1424	return pll;	1467	crtc_state->shared_dpll = pll;
		1468
		1469	return true;
1425	}	1470	}
1426		1471
1427	static void skl_dump_hw_state(struct drm_i915_private *dev_priv,	1472	static void skl_dump_hw_state(struct drm_i915_private *dev_priv,
@@ -1827,22 +1872,23 @@ bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state) · 399 unmodified lines
1827	return bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div);	1872	return bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div);
1828	}	1873	}
1829		1874
1830	static struct intel_shared_dpll *	1875	static bool bxt_get_dpll(struct intel_atomic_state *state,
1831	bxt_get_dpll(struct intel_crtc_state *crtc_state,	1876	struct intel_crtc *crtc,
1832	struct intel_encoder *encoder)	1877	struct intel_encoder *encoder)
1833	{	1878	{
1834	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);	1879	struct intel_crtc_state *crtc_state =
		1880	intel_atomic_get_new_crtc_state(state, crtc);
1835	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);	1881	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1836	struct intel_shared_dpll *pll;	1882	struct intel_shared_dpll *pll;
1837	enum intel_dpll_id id;	1883	enum intel_dpll_id id;
1838		1884
1839	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&	1885	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
1840	!bxt_ddi_hdmi_set_dpll_hw_state(crtc_state))	1886	!bxt_ddi_hdmi_set_dpll_hw_state(crtc_state))
1841	return NULL;	1887	return false;
1842		1888
1843	if (intel_crtc_has_dp_encoder(crtc_state) &&	1889	if (intel_crtc_has_dp_encoder(crtc_state) &&
1844	!bxt_ddi_dp_set_dpll_hw_state(crtc_state))	1890	!bxt_ddi_dp_set_dpll_hw_state(crtc_state))
1845	return NULL;	1891	return false;
1846		1892
1847	/* 1:1 mapping between ports and PLLs */	1893	/* 1:1 mapping between ports and PLLs */
1848	id = (enum intel_dpll_id) encoder->port;	1894	id = (enum intel_dpll_id) encoder->port;
@@ -1851,9 +1897,12 @@ bxt_get_dpll(struct intel_crtc_state *crtc_state, · 2 unmodified lines
1851	DRM_DEBUG_KMS("[CRTC:%d:%s] using pre-allocated %s\n",	1897	DRM_DEBUG_KMS("[CRTC:%d:%s] using pre-allocated %s\n",
1852	crtc->base.base.id, crtc->base.name, pll->info->name);	1898	crtc->base.base.id, crtc->base.name, pll->info->name);
1853		1899
1854	intel_reference_shared_dpll(pll, crtc_state);	1900	intel_reference_shared_dpll(state, crtc,
		1901	pll, &crtc_state->dpll_hw_state);
1855		1902
1856	return pll;	1903	crtc_state->shared_dpll = pll;
		1904
		1905	return true;
1857	}	1906	}
1858		1907
1859	static void bxt_dump_hw_state(struct drm_i915_private *dev_priv,	1908	static void bxt_dump_hw_state(struct drm_i915_private *dev_priv,
@@ -1884,9 +1933,14 @@ static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = { · 24 unmodified lines
1884	struct intel_dpll_mgr {	1933	struct intel_dpll_mgr {
1885	const struct dpll_info *dpll_info;	1934	const struct dpll_info *dpll_info;
1886		1935
1887	struct intel_shared_dpll (get_dpll)(struct intel_crtc_state *crtc_state,	1936	bool (get_dplls)(struct intel_atomic_state state,
1888	struct intel_encoder *encoder);	1937	struct intel_crtc *crtc,
1889		1938	struct intel_encoder *encoder);
		1939	void (put_dplls)(struct intel_atomic_state state,
		1940	struct intel_crtc *crtc);
		1941	void (update_active_dpll)(struct intel_atomic_state state,
		1942	struct intel_crtc *crtc,
		1943	struct intel_encoder *encoder);
1890	void (dump_hw_state)(struct drm_i915_private dev_priv,	1944	void (dump_hw_state)(struct drm_i915_private dev_priv,
1891	const struct intel_dpll_hw_state *hw_state);	1945	const struct intel_dpll_hw_state *hw_state);
1892	};	1946	};
@@ -1899,7 +1953,8 @@ static const struct dpll_info pch_plls[] = { · 6 unmodified lines
1899		1953
1900	static const struct intel_dpll_mgr pch_pll_mgr = {	1954	static const struct intel_dpll_mgr pch_pll_mgr = {
1901	.dpll_info = pch_plls,	1955	.dpll_info = pch_plls,
1902	.get_dpll = ibx_get_dpll,	1956	.get_dplls = ibx_get_dpll,
		1957	.put_dplls = intel_put_dpll,
1903	.dump_hw_state = ibx_dump_hw_state,	1958	.dump_hw_state = ibx_dump_hw_state,
1904	};	1959	};
1905		1960
@@ -1915,7 +1970,8 @@ static const struct dpll_info hsw_plls[] = { · 9 unmodified lines
1915		1970
1916	static const struct intel_dpll_mgr hsw_pll_mgr = {	1971	static const struct intel_dpll_mgr hsw_pll_mgr = {
1917	.dpll_info = hsw_plls,	1972	.dpll_info = hsw_plls,
1918	.get_dpll = hsw_get_dpll,	1973	.get_dplls = hsw_get_dpll,
		1974	.put_dplls = intel_put_dpll,
1919	.dump_hw_state = hsw_dump_hw_state,	1975	.dump_hw_state = hsw_dump_hw_state,
1920	};	1976	};
1921		1977
@@ -1929,7 +1985,8 @@ static const struct dpll_info skl_plls[] = { · 7 unmodified lines
1929		1985
1930	static const struct intel_dpll_mgr skl_pll_mgr = {	1986	static const struct intel_dpll_mgr skl_pll_mgr = {
1931	.dpll_info = skl_plls,	1987	.dpll_info = skl_plls,
1932	.get_dpll = skl_get_dpll,	1988	.get_dplls = skl_get_dpll,
		1989	.put_dplls = intel_put_dpll,
1933	.dump_hw_state = skl_dump_hw_state,	1990	.dump_hw_state = skl_dump_hw_state,
1934	};	1991	};
1935		1992
@@ -1942,7 +1999,8 @@ static const struct dpll_info bxt_plls[] = { · 6 unmodified lines
1942		1999
1943	static const struct intel_dpll_mgr bxt_pll_mgr = {	2000	static const struct intel_dpll_mgr bxt_pll_mgr = {
1944	.dpll_info = bxt_plls,	2001	.dpll_info = bxt_plls,
1945	.get_dpll = bxt_get_dpll,	2002	.get_dplls = bxt_get_dpll,
		2003	.put_dplls = intel_put_dpll,
1946	.dump_hw_state = bxt_dump_hw_state,	2004	.dump_hw_state = bxt_dump_hw_state,
1947	};	2005	};
1948		2006
@@ -2332,10 +2390,12 @@ cnl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state) · 383 unmodified lines
2332	return true;	2390	return true;
2333	}	2391	}
2334		2392
2335	static struct intel_shared_dpll *	2393	static bool cnl_get_dpll(struct intel_atomic_state *state,
2336	cnl_get_dpll(struct intel_crtc_state *crtc_state,	2394	struct intel_crtc *crtc,
2337	struct intel_encoder *encoder)	2395	struct intel_encoder *encoder)
2338	{	2396	{
		2397	struct intel_crtc_state *crtc_state =
		2398	intel_atomic_get_new_crtc_state(state, crtc);
2339	struct intel_shared_dpll *pll;	2399	struct intel_shared_dpll *pll;
2340	bool bret;	2400	bool bret;
2341		2401
@@ -2343,31 +2403,35 @@ cnl_get_dpll(struct intel_crtc_state *crtc_state, · 1 unmodified line
2343	bret = cnl_ddi_hdmi_pll_dividers(crtc_state);	2403	bret = cnl_ddi_hdmi_pll_dividers(crtc_state);
2344	if (!bret) {	2404	if (!bret) {
2345	DRM_DEBUG_KMS("Could not get HDMI pll dividers.\n");	2405	DRM_DEBUG_KMS("Could not get HDMI pll dividers.\n");
2346	return NULL;	2406	return false;
2347	}	2407	}
2348	} else if (intel_crtc_has_dp_encoder(crtc_state)) {	2408	} else if (intel_crtc_has_dp_encoder(crtc_state)) {
2349	bret = cnl_ddi_dp_set_dpll_hw_state(crtc_state);	2409	bret = cnl_ddi_dp_set_dpll_hw_state(crtc_state);
2350	if (!bret) {	2410	if (!bret) {
2351	DRM_DEBUG_KMS("Could not set DP dpll HW state.\n");	2411	DRM_DEBUG_KMS("Could not set DP dpll HW state.\n");
2352	return NULL;	2412	return false;
2353	}	2413	}
2354	} else {	2414	} else {
2355	DRM_DEBUG_KMS("Skip DPLL setup for output_types 0x%x\n",	2415	DRM_DEBUG_KMS("Skip DPLL setup for output_types 0x%x\n",
2356	crtc_state->output_types);	2416	crtc_state->output_types);
2357	return NULL;	2417	return false;
2358	}	2418	}
2359		2419
2360	pll = intel_find_shared_dpll(crtc_state,	2420	pll = intel_find_shared_dpll(state, crtc,
		2421	&crtc_state->dpll_hw_state,
2361	DPLL_ID_SKL_DPLL0,	2422	DPLL_ID_SKL_DPLL0,
2362	DPLL_ID_SKL_DPLL2);	2423	DPLL_ID_SKL_DPLL2);
2363	if (!pll) {	2424	if (!pll) {
2364	DRM_DEBUG_KMS("No PLL selected\n");	2425	DRM_DEBUG_KMS("No PLL selected\n");
2365	return NULL;	2426	return false;
2366	}	2427	}
2367		2428
2368	intel_reference_shared_dpll(pll, crtc_state);	2429	intel_reference_shared_dpll(state, crtc,
		2430	pll, &crtc_state->dpll_hw_state);
2369		2431
2370	return pll;	2432	crtc_state->shared_dpll = pll;
		2433
		2434	return true;
2371	}	2435	}
2372		2436
2373	static void cnl_dump_hw_state(struct drm_i915_private *dev_priv,	2437	static void cnl_dump_hw_state(struct drm_i915_private *dev_priv,
@@ -2394,7 +2458,8 @@ static const struct dpll_info cnl_plls[] = { · 20 unmodified lines
2394		2458
2395	static const struct intel_dpll_mgr cnl_pll_mgr = {	2459	static const struct intel_dpll_mgr cnl_pll_mgr = {
2396	.dpll_info = cnl_plls,	2460	.dpll_info = cnl_plls,
2397	.get_dpll = cnl_get_dpll,	2461	.get_dplls = cnl_get_dpll,
		2462	.put_dplls = intel_put_dpll,
2398	.dump_hw_state = cnl_dump_hw_state,	2463	.dump_hw_state = cnl_dump_hw_state,
2399	};	2464	};
2400		2465
@@ -2506,14 +2571,16 @@ static bool icl_calc_tbt_pll(struct intel_crtc_state *crtc_state, · 105 unmodified lines
2506	}	2571	}
2507		2572
2508	static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,	2573	static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
2509	struct intel_encoder *encoder)	2574	struct intel_encoder *encoder,
		2575	struct intel_dpll_hw_state *pll_state)
2510	{	2576	{
2511	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);	2577	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2512	u32 cfgcr0, cfgcr1;	2578	u32 cfgcr0, cfgcr1;
2513	struct skl_wrpll_params pll_params = { 0 };	2579	struct skl_wrpll_params pll_params = { 0 };
2514	bool ret;	2580	bool ret;
2515		2581
2516	if (intel_port_is_tc(dev_priv, encoder->port))	2582	if (intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv,
		2583	encoder->port)))
2517	ret = icl_calc_tbt_pll(crtc_state, &pll_params);	2584	ret = icl_calc_tbt_pll(crtc_state, &pll_params);
2518	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) \|\|	2585	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) \|\|
2519	intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))	2586	intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
@@ -2530,14 +2597,17 @@ static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state, · 10 unmodified lines
2530	cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params.qdiv_ratio) \|	2597	cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params.qdiv_ratio) \|
2531	DPLL_CFGCR1_QDIV_MODE(pll_params.qdiv_mode) \|	2598	DPLL_CFGCR1_QDIV_MODE(pll_params.qdiv_mode) \|
2532	DPLL_CFGCR1_KDIV(pll_params.kdiv) \|	2599	DPLL_CFGCR1_KDIV(pll_params.kdiv) \|
2533	DPLL_CFGCR1_PDIV(pll_params.pdiv) \|	2600	DPLL_CFGCR1_PDIV(pll_params.pdiv);
2534	DPLL_CFGCR1_CENTRAL_FREQ_8400;
2535		2601
2536	memset(&crtc_state->dpll_hw_state, 0,	2602	if (INTEL_GEN(dev_priv) >= 12)
2537	sizeof(crtc_state->dpll_hw_state));	2603	cfgcr1 \|= TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL;
		2604	else
		2605	cfgcr1 \|= DPLL_CFGCR1_CENTRAL_FREQ_8400;
2538		2606
2539	crtc_state->dpll_hw_state.cfgcr0 = cfgcr0;	2607	memset(pll_state, 0, sizeof(*pll_state));
2540	crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;	2608
		2609	pll_state->cfgcr0 = cfgcr0;
		2610	pll_state->cfgcr1 = cfgcr1;
2541		2611
2542	return true;	2612	return true;
2543	}	2613	}
@@ -2627,10 +2697,10 @@ static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc, · 83 unmodified lines
2627	* The specification for this function uses real numbers, so the math had to be	2697	* The specification for this function uses real numbers, so the math had to be
2628	* adapted to integer-only calculation, that's why it looks so different.	2698	* adapted to integer-only calculation, that's why it looks so different.
2629	*/	2699	*/
2630	static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state)	2700	static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
		2701	struct intel_dpll_hw_state *pll_state)
2631	{	2702	{
2632	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);	2703	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
2633	struct intel_dpll_hw_state *pll_state = &crtc_state->dpll_hw_state;
2634	int refclk_khz = dev_priv->cdclk.hw.ref;	2704	int refclk_khz = dev_priv->cdclk.hw.ref;
2635	int clock = crtc_state->port_clock;	2705	int clock = crtc_state->port_clock;
2636	u32 dco_khz, m1div, m2div_int, m2div_rem, m2div_frac;	2706	u32 dco_khz, m1div, m2div_int, m2div_rem, m2div_frac;
@@ -2792,63 +2862,184 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state) · 155 unmodified lines
2792	return true;	2862	return true;
2793	}	2863	}
2794		2864
2795	static struct intel_shared_dpll *	2865	/**
2796	icl_get_dpll(struct intel_crtc_state *crtc_state,	2866	* icl_set_active_port_dpll - select the active port DPLL for a given CRTC
2797	struct intel_encoder *encoder)	2867	* @crtc_state: state for the CRTC to select the DPLL for
		2868	* @port_dpll_id: the active @port_dpll_id to select
		2869	*
		2870	* Select the given @port_dpll_id instance from the DPLLs reserved for the
		2871	* CRTC.
		2872	*/
		2873	void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
		2874	enum icl_port_dpll_id port_dpll_id)
2798	{	2875	{
2799	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);	2876	struct icl_port_dpll *port_dpll =
2800	struct intel_digital_port *intel_dig_port;	2877	&crtc_state->icl_port_dplls[port_dpll_id];
2801	struct intel_shared_dpll *pll;	2878
		2879	crtc_state->shared_dpll = port_dpll->pll;
		2880	crtc_state->dpll_hw_state = port_dpll->hw_state;
		2881	}
		2882
		2883	static void icl_update_active_dpll(struct intel_atomic_state *state,
		2884	struct intel_crtc *crtc,
		2885	struct intel_encoder *encoder)
		2886	{
		2887	struct intel_crtc_state *crtc_state =
		2888	intel_atomic_get_new_crtc_state(state, crtc);
		2889	struct intel_digital_port *primary_port;
		2890	enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
		2891
		2892	primary_port = encoder->type == INTEL_OUTPUT_DP_MST ?
		2893	enc_to_mst(&encoder->base)->primary :
		2894	enc_to_dig_port(&encoder->base);
		2895
		2896	if (primary_port &&
		2897	(primary_port->tc_mode == TC_PORT_DP_ALT \|\|
		2898	primary_port->tc_mode == TC_PORT_LEGACY))
		2899	port_dpll_id = ICL_PORT_DPLL_MG_PHY;
		2900
		2901	icl_set_active_port_dpll(crtc_state, port_dpll_id);
		2902	}
		2903
		2904	static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state,
		2905	struct intel_crtc *crtc,
		2906	struct intel_encoder *encoder)
		2907	{
		2908	struct intel_crtc_state *crtc_state =
		2909	intel_atomic_get_new_crtc_state(state, crtc);
		2910	struct icl_port_dpll *port_dpll =
		2911	&crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
		2912	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2802	enum port port = encoder->port;	2913	enum port port = encoder->port;
2803	enum intel_dpll_id min, max;	2914	bool has_dpll4 = false;
2804	bool ret;
2805		2915
2806	if (intel_port_is_combophy(dev_priv, port)) {	2916	if (!icl_calc_dpll_state(crtc_state, encoder, &port_dpll->hw_state)) {
2807	min = DPLL_ID_ICL_DPLL0;	2917	DRM_DEBUG_KMS("Could not calculate combo PHY PLL state.\n");
2808	max = DPLL_ID_ICL_DPLL1;
2809	ret = icl_calc_dpll_state(crtc_state, encoder);
2810	} else if (intel_port_is_tc(dev_priv, port)) {
2811	if (encoder->type == INTEL_OUTPUT_DP_MST) {
2812	struct intel_dp_mst_encoder *mst_encoder;
2813		2918
2814	mst_encoder = enc_to_mst(&encoder->base);	2919	return false;
2815	intel_dig_port = mst_encoder->primary;	2920	}
2816	} else {
2817	intel_dig_port = enc_to_dig_port(&encoder->base);
2818	}
2819		2921
2820	if (intel_dig_port->tc_type == TC_PORT_TBT) {	2922	if (IS_ELKHARTLAKE(dev_priv) && port != PORT_A)
2821	min = DPLL_ID_ICL_TBTPLL;	2923	has_dpll4 = true;
2822	max = min;	2924
2823	ret = icl_calc_dpll_state(crtc_state, encoder);	2925	port_dpll->pll = intel_find_shared_dpll(state, crtc,
2824	} else {	2926	&port_dpll->hw_state,
2825	enum tc_port tc_port;	2927	DPLL_ID_ICL_DPLL0,
		2928	has_dpll4 ? DPLL_ID_EHL_DPLL4
		2929	: DPLL_ID_ICL_DPLL1);
		2930	if (!port_dpll->pll) {
		2931	DRM_DEBUG_KMS("No combo PHY PLL found for port %c\n",
		2932	port_name(encoder->port));
		2933	return false;
		2934	}
2826		2935
2827	tc_port = intel_port_to_tc(dev_priv, port);	2936	intel_reference_shared_dpll(state, crtc,
2828	min = icl_tc_port_to_pll_id(tc_port);	2937	port_dpll->pll, &port_dpll->hw_state);
2829	max = min;	2938
2830	ret = icl_calc_mg_pll_state(crtc_state);	2939	icl_update_active_dpll(state, crtc, encoder);
2831	}	2940
2832	} else {	2941	return true;
2833	MISSING_CASE(port);	2942	}
2834	return NULL;	2943
		2944	static bool icl_get_tc_phy_dplls(struct intel_atomic_state *state,
		2945	struct intel_crtc *crtc,
		2946	struct intel_encoder *encoder)
		2947	{
		2948	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
		2949	struct intel_crtc_state *crtc_state =
		2950	intel_atomic_get_new_crtc_state(state, crtc);
		2951	struct icl_port_dpll *port_dpll;
		2952	enum intel_dpll_id dpll_id;
		2953
		2954	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
		2955	if (!icl_calc_dpll_state(crtc_state, encoder, &port_dpll->hw_state)) {
		2956	DRM_DEBUG_KMS("Could not calculate TBT PLL state.\n");
		2957	return false;
2835	}	2958	}
2836		2959
2837	if (!ret) {	2960	port_dpll->pll = intel_find_shared_dpll(state, crtc,
2838	DRM_DEBUG_KMS("Could not calculate PLL state.\n");	2961	&port_dpll->hw_state,
2839	return NULL;	2962	DPLL_ID_ICL_TBTPLL,
		2963	DPLL_ID_ICL_TBTPLL);
		2964	if (!port_dpll->pll) {
		2965	DRM_DEBUG_KMS("No TBT-ALT PLL found\n");
		2966	return false;
2840	}	2967	}
		2968	intel_reference_shared_dpll(state, crtc,
		2969	port_dpll->pll, &port_dpll->hw_state);
2841		2970
2842		2971
2843	pll = intel_find_shared_dpll(crtc_state, min, max);	2972	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
2844	if (!pll) {	2973	if (!icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state)) {
2845	DRM_DEBUG_KMS("No PLL selected\n");	2974	DRM_DEBUG_KMS("Could not calculate MG PHY PLL state.\n");
2846	return NULL;	2975	goto err_unreference_tbt_pll;
2847	}	2976	}
2848		2977
2849	intel_reference_shared_dpll(pll, crtc_state);	2978	dpll_id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv,
		2979	encoder->port));
		2980	port_dpll->pll = intel_find_shared_dpll(state, crtc,
		2981	&port_dpll->hw_state,
		2982	dpll_id,
		2983	dpll_id);
		2984	if (!port_dpll->pll) {
		2985	DRM_DEBUG_KMS("No MG PHY PLL found\n");
		2986	goto err_unreference_tbt_pll;
		2987	}
		2988	intel_reference_shared_dpll(state, crtc,
		2989	port_dpll->pll, &port_dpll->hw_state);
2850		2990
2851	return pll;	2991	icl_update_active_dpll(state, crtc, encoder);
		2992
		2993	return true;
		2994
		2995	err_unreference_tbt_pll:
		2996	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
		2997	intel_unreference_shared_dpll(state, crtc, port_dpll->pll);
		2998
		2999	return false;
		3000	}
		3001
		3002	static bool icl_get_dplls(struct intel_atomic_state *state,
		3003	struct intel_crtc *crtc,
		3004	struct intel_encoder *encoder)
		3005	{
		3006	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
		3007	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
		3008
		3009	if (intel_phy_is_combo(dev_priv, phy))
		3010	return icl_get_combo_phy_dpll(state, crtc, encoder);
		3011	else if (intel_phy_is_tc(dev_priv, phy))
		3012	return icl_get_tc_phy_dplls(state, crtc, encoder);
		3013
		3014	MISSING_CASE(phy);
		3015
		3016	return false;
		3017	}
		3018
		3019	static void icl_put_dplls(struct intel_atomic_state *state,
		3020	struct intel_crtc *crtc)
		3021	{
		3022	const struct intel_crtc_state *old_crtc_state =
		3023	intel_atomic_get_old_crtc_state(state, crtc);
		3024	struct intel_crtc_state *new_crtc_state =
		3025	intel_atomic_get_new_crtc_state(state, crtc);
		3026	enum icl_port_dpll_id id;
		3027
		3028	new_crtc_state->shared_dpll = NULL;
		3029
		3030	for (id = ICL_PORT_DPLL_DEFAULT; id < ICL_PORT_DPLL_COUNT; id++) {
		3031	const struct icl_port_dpll *old_port_dpll =
		3032	&old_crtc_state->icl_port_dplls[id];
		3033	struct icl_port_dpll *new_port_dpll =
		3034	&new_crtc_state->icl_port_dplls[id];
		3035
		3036	new_port_dpll->pll = NULL;
		3037
		3038	if (!old_port_dpll->pll)
		3039	continue;
		3040
		3041	intel_unreference_shared_dpll(state, crtc, old_port_dpll->pll);
		3042	}
2852	}	3043	}
2853		3044
2854	static bool mg_pll_get_hw_state(struct drm_i915_private *dev_priv,	3045	static bool mg_pll_get_hw_state(struct drm_i915_private *dev_priv,
@@ -2932,8 +3123,18 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv, · 77 unmodified lines
2932	if (!(val & PLL_ENABLE))	3123	if (!(val & PLL_ENABLE))
2933	goto out;	3124	goto out;
2934		3125
2935	hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));	3126	if (INTEL_GEN(dev_priv) >= 12) {
2936	hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));	3127	hw_state->cfgcr0 = I915_READ(TGL_DPLL_CFGCR0(id));
		3128	hw_state->cfgcr1 = I915_READ(TGL_DPLL_CFGCR1(id));
		3129	} else {
		3130	if (IS_ELKHARTLAKE(dev_priv) && id == DPLL_ID_EHL_DPLL4) {
		3131	hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(4));
		3132	hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(4));
		3133	} else {
		3134	hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
		3135	hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
		3136	}
		3137	}
2937		3138
2938	ret = true;	3139	ret = true;
2939	out:	3140	out:
@@ -2945,8 +3146,14 @@ static bool combo_pll_get_hw_state(struct drm_i915_private *dev_priv, · 5 unmodified lines
2945	struct intel_shared_dpll *pll,	3146	struct intel_shared_dpll *pll,
2946	struct intel_dpll_hw_state *hw_state)	3147	struct intel_dpll_hw_state *hw_state)
2947	{	3148	{
2948	return icl_pll_get_hw_state(dev_priv, pll, hw_state,	3149	i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
2949	CNL_DPLL_ENABLE(pll->info->id));	3150
		3151	if (IS_ELKHARTLAKE(dev_priv) &&
		3152	pll->info->id == DPLL_ID_EHL_DPLL4) {
		3153	enable_reg = MG_PLL_ENABLE(0);
		3154	}
		3155
		3156	return icl_pll_get_hw_state(dev_priv, pll, hw_state, enable_reg);
2950	}	3157	}
2951		3158
2952	static bool tbt_pll_get_hw_state(struct drm_i915_private *dev_priv,	3159	static bool tbt_pll_get_hw_state(struct drm_i915_private *dev_priv,
@@ -2961,10 +3168,24 @@ static void icl_dpll_write(struct drm_i915_private *dev_priv, · 8 unmodified lines
2961	{	3168	{
2962	struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;	3169	struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
2963	const enum intel_dpll_id id = pll->info->id;	3170	const enum intel_dpll_id id = pll->info->id;
		3171	i915_reg_t cfgcr0_reg, cfgcr1_reg;
2964		3172
2965	I915_WRITE(ICL_DPLL_CFGCR0(id), hw_state->cfgcr0);	3173	if (INTEL_GEN(dev_priv) >= 12) {
2966	I915_WRITE(ICL_DPLL_CFGCR1(id), hw_state->cfgcr1);	3174	cfgcr0_reg = TGL_DPLL_CFGCR0(id);
2967	POSTING_READ(ICL_DPLL_CFGCR1(id));	3175	cfgcr1_reg = TGL_DPLL_CFGCR1(id);
		3176	} else {
		3177	if (IS_ELKHARTLAKE(dev_priv) && id == DPLL_ID_EHL_DPLL4) {
		3178	cfgcr0_reg = ICL_DPLL_CFGCR0(4);
		3179	cfgcr1_reg = ICL_DPLL_CFGCR1(4);
		3180	} else {
		3181	cfgcr0_reg = ICL_DPLL_CFGCR0(id);
		3182	cfgcr1_reg = ICL_DPLL_CFGCR1(id);
		3183	}
		3184	}
		3185
		3186	I915_WRITE(cfgcr0_reg, hw_state->cfgcr0);
		3187	I915_WRITE(cfgcr1_reg, hw_state->cfgcr1);
		3188	POSTING_READ(cfgcr1_reg);
2968	}	3189	}
2969		3190
2970	static void icl_mg_pll_write(struct drm_i915_private *dev_priv,	3191	static void icl_mg_pll_write(struct drm_i915_private *dev_priv,
@@ -3057,6 +3278,19 @@ static void combo_pll_enable(struct drm_i915_private *dev_priv, · 86 unmodified lines
3057	{	3278	{
3058	i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);	3279	i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
3059		3280
		3281	if (IS_ELKHARTLAKE(dev_priv) &&
		3282	pll->info->id == DPLL_ID_EHL_DPLL4) {
		3283	enable_reg = MG_PLL_ENABLE(0);
		3284
		3285	/*
		3286	* We need to disable DC states when this DPLL is enabled.
		3287	* This can be done by taking a reference on DPLL4 power
		3288	* domain.
		3289	*/
		3290	pll->wakeref = intel_display_power_get(dev_priv,
		3291	POWER_DOMAIN_DPLL_DC_OFF);
		3292	}
		3293
3060	icl_pll_power_enable(dev_priv, pll, enable_reg);	3294	icl_pll_power_enable(dev_priv, pll, enable_reg);
3061		3295
3062	icl_dpll_write(dev_priv, pll);	3296	icl_dpll_write(dev_priv, pll);
@@ -3152,7 +3386,19 @@ static void icl_pll_disable(struct drm_i915_private *dev_priv, · 89 unmodified lines
3152	static void combo_pll_disable(struct drm_i915_private *dev_priv,	3386	static void combo_pll_disable(struct drm_i915_private *dev_priv,
3153	struct intel_shared_dpll *pll)	3387	struct intel_shared_dpll *pll)
3154	{	3388	{
3155	icl_pll_disable(dev_priv, pll, CNL_DPLL_ENABLE(pll->info->id));	3389	i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
		3390
		3391	if (IS_ELKHARTLAKE(dev_priv) &&
		3392	pll->info->id == DPLL_ID_EHL_DPLL4) {
		3393	enable_reg = MG_PLL_ENABLE(0);
		3394	icl_pll_disable(dev_priv, pll, enable_reg);
		3395
		3396	intel_display_power_put(dev_priv, POWER_DOMAIN_DPLL_DC_OFF,
		3397	pll->wakeref);
		3398	return;
		3399	}
		3400
		3401	icl_pll_disable(dev_priv, pll, enable_reg);
3156	}	3402	}
3157		3403
3158	static void tbt_pll_disable(struct drm_i915_private *dev_priv,	3404	static void tbt_pll_disable(struct drm_i915_private *dev_priv,
@@ -3223,19 +3469,38 @@ static const struct dpll_info icl_plls[] = { · 64 unmodified lines
3223		3469
3224	static const struct intel_dpll_mgr icl_pll_mgr = {	3470	static const struct intel_dpll_mgr icl_pll_mgr = {
3225	.dpll_info = icl_plls,	3471	.dpll_info = icl_plls,
3226	.get_dpll = icl_get_dpll,	3472	.get_dplls = icl_get_dplls,
		3473	.put_dplls = icl_put_dplls,
		3474	.update_active_dpll = icl_update_active_dpll,
3227	.dump_hw_state = icl_dump_hw_state,	3475	.dump_hw_state = icl_dump_hw_state,
3228	};	3476	};
3229		3477
3230	static const struct dpll_info ehl_plls[] = {	3478	static const struct dpll_info ehl_plls[] = {
3231	{ "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },	3479	{ "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
3232	{ "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },	3480	{ "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
		3481	{ "DPLL 4", &combo_pll_funcs, DPLL_ID_EHL_DPLL4, 0 },
3233	{ },	3482	{ },
3234	};	3483	};
3235		3484
3236	static const struct intel_dpll_mgr ehl_pll_mgr = {	3485	static const struct intel_dpll_mgr ehl_pll_mgr = {
3237	.dpll_info = ehl_plls,	3486	.dpll_info = ehl_plls,
3238	.get_dpll = icl_get_dpll,	3487	.get_dplls = icl_get_dplls,
		3488	.put_dplls = icl_put_dplls,
		3489	.dump_hw_state = icl_dump_hw_state,
		3490	};
		3491
		3492	static const struct dpll_info tgl_plls[] = {
		3493	{ "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
		3494	{ "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
		3495	{ "TBT PLL", &tbt_pll_funcs, DPLL_ID_ICL_TBTPLL, 0 },
		3496	/* TODO: Add typeC plls */
		3497	{ },
		3498	};
		3499
		3500	static const struct intel_dpll_mgr tgl_pll_mgr = {
		3501	.dpll_info = tgl_plls,
		3502	.get_dplls = icl_get_dplls,
		3503	.put_dplls = icl_put_dplls,
3239	.dump_hw_state = icl_dump_hw_state,	3504	.dump_hw_state = icl_dump_hw_state,
3240	};	3505	};
3241		3506
@@ -3252,7 +3517,9 @@ void intel_shared_dpll_init(struct drm_device *dev) · 10 unmodified lines
3252	const struct dpll_info *dpll_info;	3517	const struct dpll_info *dpll_info;
3253	int i;	3518	int i;
3254		3519
3255	if (IS_ELKHARTLAKE(dev_priv))	3520	if (INTEL_GEN(dev_priv) >= 12)
		3521	dpll_mgr = &tgl_pll_mgr;
		3522	else if (IS_ELKHARTLAKE(dev_priv))
3256	dpll_mgr = &ehl_pll_mgr;	3523	dpll_mgr = &ehl_pll_mgr;
3257	else if (INTEL_GEN(dev_priv) >= 11)	3524	else if (INTEL_GEN(dev_priv) >= 11)
3258	dpll_mgr = &icl_pll_mgr;	3525	dpll_mgr = &icl_pll_mgr;
@@ -3287,50 +3554,87 @@ void intel_shared_dpll_init(struct drm_device *dev) · 28 unmodified lines
3287	}	3554	}
3288		3555
3289	/**	3556	/**
3290	* intel_get_shared_dpll - get a shared DPLL for CRTC and encoder combination	3557	* intel_reserve_shared_dplls - reserve DPLLs for CRTC and encoder combination
3291	* @crtc_state: atomic state for the crtc	3558	* @state: atomic state
		3559	* @crtc: CRTC to reserve DPLLs for
3292	* @encoder: encoder	3560	* @encoder: encoder
3293	*	3561	*
3294	* Find an appropriate DPLL for the given CRTC and encoder combination. A	3562	* This function reserves all required DPLLs for the given CRTC and encoder
3295	* reference from the @crtc_state to the returned pll is registered in the	3563	* combination in the current atomic commit @state and the new @crtc atomic
3296	* atomic state. That configuration is made effective by calling	3564	* state.
3297	* intel_shared_dpll_swap_state(). The reference should be released by calling	3565	*
3298	* intel_release_shared_dpll().	3566	* The new configuration in the atomic commit @state is made effective by
		3567	* calling intel_shared_dpll_swap_state().
		3568	*
		3569	* The reserved DPLLs should be released by calling
		3570	* intel_release_shared_dplls().
3299	*	3571	*
3300	* Returns:	3572	* Returns:
3301	* A shared DPLL to be used by @crtc_state and @encoder.	3573	* True if all required DPLLs were successfully reserved.
3302	*/	3574	*/
3303	struct intel_shared_dpll *	3575	bool intel_reserve_shared_dplls(struct intel_atomic_state *state,
3304	intel_get_shared_dpll(struct intel_crtc_state *crtc_state,	3576	struct intel_crtc *crtc,
3305	struct intel_encoder *encoder)	3577	struct intel_encoder *encoder)
3306	{	3578	{
3307	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);	3579	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
3308	const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll_mgr;	3580	const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll_mgr;
3309		3581
3310	if (WARN_ON(!dpll_mgr))	3582	if (WARN_ON(!dpll_mgr))
3311	return NULL;	3583	return false;
3312		3584
3313	return dpll_mgr->get_dpll(crtc_state, encoder);	3585	return dpll_mgr->get_dplls(state, crtc, encoder);
3314	}	3586	}
3315		3587
3316	/**	3588	/**
3317	* intel_release_shared_dpll - end use of DPLL by CRTC in atomic state	3589	* intel_release_shared_dplls - end use of DPLLs by CRTC in atomic state
3318	* @dpll: dpll in use by @crtc
3319	* @crtc: crtc
3320	* @state: atomic state	3590	* @state: atomic state
		3591	* @crtc: crtc from which the DPLLs are to be released
3321	*	3592	*
3322	* This function releases the reference from @crtc to @dpll from the	3593	* This function releases all DPLLs reserved by intel_reserve_shared_dplls()
3323	* atomic @state. The new configuration is made effective by calling	3594	* from the current atomic commit @state and the old @crtc atomic state.
3324	* intel_shared_dpll_swap_state().	3595	*
		3596	* The new configuration in the atomic commit @state is made effective by
		3597	* calling intel_shared_dpll_swap_state().
3325	*/	3598	*/
3326	void intel_release_shared_dpll(struct intel_shared_dpll *dpll,	3599	void intel_release_shared_dplls(struct intel_atomic_state *state,
3327	struct intel_crtc *crtc,	3600	struct intel_crtc *crtc)
3328	struct drm_atomic_state *state)
3329	{	3601	{
3330	struct intel_shared_dpll_state *shared_dpll_state;	3602	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
		3603	const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll_mgr;
		3604
		3605	/*
		3606	* FIXME: this function is called for every platform having a
		3607	* compute_clock hook, even though the platform doesn't yet support
		3608	* the shared DPLL framework and intel_reserve_shared_dplls() is not
		3609	* called on those.
		3610	*/
		3611	if (!dpll_mgr)
		3612	return;
		3613
		3614	dpll_mgr->put_dplls(state, crtc);
		3615	}
		3616
		3617	/**
		3618	* intel_update_active_dpll - update the active DPLL for a CRTC/encoder
		3619	* @state: atomic state
		3620	* @crtc: the CRTC for which to update the active DPLL
		3621	* @encoder: encoder determining the type of port DPLL
		3622	*
		3623	* Update the active DPLL for the given @crtc/@encoder in @crtc's atomic state,
		3624	* from the port DPLLs reserved previously by intel_reserve_shared_dplls(). The
		3625	* DPLL selected will be based on the current mode of the encoder's port.
		3626	*/
		3627	void intel_update_active_dpll(struct intel_atomic_state *state,
		3628	struct intel_crtc *crtc,
		3629	struct intel_encoder *encoder)
		3630	{
		3631	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
		3632	const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll_mgr;
		3633
		3634	if (WARN_ON(!dpll_mgr))
		3635	return;
3331		3636
3332	shared_dpll_state = intel_atomic_get_shared_dpll_state(state);	3637	dpll_mgr->update_active_dpll(state, crtc, encoder);
3333	shared_dpll_state[dpll->info->id].crtc_mask &= ~(1 << crtc->pipe);
3334	}	3638	}
3335		3639
3336	/**	3640	/**

drivers/gpu/drm/i915/display/intel_dpll_mgr.h+44−13

 #include <linux/types.h>
 #include "intel_display.h"
+#include "intel_wakeref.h"
 /*FIXME: Move this to a more appropriate place. */
 #define abs_diff(a, b) ({			\
 	(void) (&__a == &__b);			\
 	__a > __b ? (__a - __b) : (__b - __a); })
-struct drm_atomic_state;
 struct drm_device;
 struct drm_i915_private;
+struct intel_atomic_state;
 struct intel_crtc;
 struct intel_crtc_state;
 struct intel_encoder;
 	/**
-	 * @DPLL_ID_ICL_DPLL0: ICL combo PHY DPLL0
+	 * @DPLL_ID_ICL_DPLL0: ICL/TGL combo PHY DPLL0
 	 */
 	DPLL_ID_ICL_DPLL0 = 0,
 	/**
-	 * @DPLL_ID_ICL_DPLL1: ICL combo PHY DPLL1
+	 * @DPLL_ID_ICL_DPLL1: ICL/TGL combo PHY DPLL1
 	 */
 	DPLL_ID_ICL_DPLL1 = 1,
 	/**
-	 * @DPLL_ID_ICL_TBTPLL: ICL TBT PLL
+	 * @DPLL_ID_EHL_DPLL4: EHL combo PHY DPLL4
+	 */
+	DPLL_ID_EHL_DPLL4 = 2,
+	/**
+	 * @DPLL_ID_ICL_TBTPLL: ICL/TGL TBT PLL
 	 */
 	DPLL_ID_ICL_TBTPLL = 2,
 	/**
-	 * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C)
+	 * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C),
+	 *                      TGL TC PLL 1 port 1 (TC1)
 	 */
 	DPLL_ID_ICL_MGPLL1 = 3,
 	/**
 	 * @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D)
+	 *                      TGL TC PLL 1 port 2 (TC2)
 	 */
 	DPLL_ID_ICL_MGPLL2 = 4,
 	/**
 	 * @DPLL_ID_ICL_MGPLL3: ICL MG PLL 1 port 3 (E)
+	 *                      TGL TC PLL 1 port 3 (TC3)
 	 */
 	DPLL_ID_ICL_MGPLL3 = 5,
 	/**
 	 * @DPLL_ID_ICL_MGPLL4: ICL MG PLL 1 port 4 (F)
+	 *                      TGL TC PLL 1 port 4 (TC4)
 	 */
 	DPLL_ID_ICL_MGPLL4 = 6,
+	/**
+	 * @DPLL_ID_TGL_TCPLL5: TGL TC PLL port 5 (TC5)
+	 */
+	DPLL_ID_TGL_MGPLL5 = 7,
+	/**
+	 * @DPLL_ID_TGL_TCPLL6: TGL TC PLL port 6 (TC6)
+	 */
+	DPLL_ID_TGL_MGPLL6 = 8,
+};
+#define I915_NUM_PLLS 9
+enum icl_port_dpll_id {
+	ICL_PORT_DPLL_DEFAULT,
+	ICL_PORT_DPLL_MG_PHY,
+	ICL_PORT_DPLL_COUNT,
 };
-#define I915_NUM_PLLS 7
 struct intel_dpll_hw_state {
 	/* i9xx, pch plls */
  * future state which would be applied by an atomic mode set (stored in
  * a struct &intel_atomic_state).
  *
- * See also intel_get_shared_dpll() and intel_release_shared_dpll().
+ * See also intel_reserve_shared_dplls() and intel_release_shared_dplls().
  */
 struct intel_shared_dpll_state {
 	/**
 	 * @info: platform specific info
 	 */
 	const struct dpll_info *info;
+	intel_wakeref_t wakeref;
 };
 #define SKL_DPLL0 0
 			bool state);
 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
-struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc_state *state,
+bool intel_reserve_shared_dplls(struct intel_atomic_state *state,
-						struct intel_encoder *encoder);
+				struct intel_crtc *crtc,
-void intel_release_shared_dpll(struct intel_shared_dpll *dpll,
+				struct intel_encoder *encoder);
-			       struct intel_crtc *crtc,
+void intel_release_shared_dplls(struct intel_atomic_state *state,
-			       struct drm_atomic_state *state);
+				struct intel_crtc *crtc);
+void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
+			      enum icl_port_dpll_id port_dpll_id);
+void intel_update_active_dpll(struct intel_atomic_state *state,
+			      struct intel_crtc *crtc,
+			      struct intel_encoder *encoder);
 void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state);
 void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
 void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
-void intel_shared_dpll_swap_state(struct drm_atomic_state *state);
+void intel_shared_dpll_swap_state(struct intel_atomic_state *state);
 void intel_shared_dpll_init(struct drm_device *dev);
 void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,

drivers/gpu/drm/i915/display/intel_dsi.h+9−3

 	struct intel_connector *attached_connector;
-	/* bit mask of ports being driven */
+	/* bit mask of ports (vlv dsi) or phys (icl dsi) being driven */
-	u16 ports;
+	union {
+		u16 ports;	/* VLV DSI */
+		u16 phys;	/* ICL DSI */
+	};
 	/* if true, use HS mode, otherwise LP */
 	bool hs;
 	return container_of(h, struct intel_dsi_host, base);
 }
-#define for_each_dsi_port(__port, __ports_mask) for_each_port_masked(__port, __ports_mask)
+#define for_each_dsi_port(__port, __ports_mask) \
+	for_each_port_masked(__port, __ports_mask)
+#define for_each_dsi_phy(__phy, __phys_mask) \
+	for_each_phy_masked(__phy, __phys_mask)
 static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
 {

drivers/gpu/drm/i915/display/intel_gmbus.c+18−2

 	[GMBUS_PIN_9_TC1_ICP] = { "dpc", GPIOJ },
 };
+static const struct gmbus_pin gmbus_pins_tgp[] = {
+	[GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
+	[GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
+	[GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
+	[GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
+	[GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
+	[GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
+	[GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
+	[GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION },
+	[GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO },
+};
 /* pin is expected to be valid */
 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
 					     unsigned int pin)
 {
-	if (HAS_PCH_MCC(dev_priv))
+	if (HAS_PCH_TGP(dev_priv))
+		return &gmbus_pins_tgp[pin];
+	else if (HAS_PCH_MCC(dev_priv))
 		return &gmbus_pins_mcc[pin];
 	else if (HAS_PCH_ICP(dev_priv))
 		return &gmbus_pins_icp[pin];
 {
 	unsigned int size;
-	if (HAS_PCH_MCC(dev_priv))
+	if (HAS_PCH_TGP(dev_priv))
+		size = ARRAY_SIZE(gmbus_pins_tgp);
+	else if (HAS_PCH_MCC(dev_priv))
 		size = ARRAY_SIZE(gmbus_pins_mcc);
 	else if (HAS_PCH_ICP(dev_priv))
 		size = ARRAY_SIZE(gmbus_pins_icp);

drivers/gpu/drm/i915/display/intel_hdcp.c+9−3

 	 * authentication.
 	 */
 	num_downstream = DRM_HDCP_NUM_DOWNSTREAM(bstatus[0]);
-	if (num_downstream == 0)
+	if (num_downstream == 0) {
+		DRM_DEBUG_KMS("Repeater with zero downstream devices\n");
 		return -EINVAL;
+	}
 	ksv_fifo = kcalloc(DRM_HDCP_KSV_LEN, num_downstream, GFP_KERNEL);
-	if (!ksv_fifo)
+	if (!ksv_fifo) {
+		DRM_DEBUG_KMS("Out of mem: ksv_fifo\n");
 		return -ENOMEM;
+	}
 	ret = shim->read_ksv_fifo(intel_dig_port, num_downstream, ksv_fifo);
 	if (ret)
 	if (ret < 0)
 		return ret;
-	if (msgs.send_cert.rx_caps[0] != HDCP_2_2_RX_CAPS_VERSION_VAL)
+	if (msgs.send_cert.rx_caps[0] != HDCP_2_2_RX_CAPS_VERSION_VAL) {
+		DRM_DEBUG_KMS("cert.rx_caps dont claim HDCP2.2\n");
 		return -EINVAL;
+	}
 	hdcp->is_repeater = HDCP_2_2_RX_REPEATER(msgs.send_cert.rx_caps[2]);

drivers/gpu/drm/i915/display/intel_hdmi.c+42−33

@@ -2930,51 +2930,34 @@ static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv, · 2929 unmodified lines
2930		2930
2931	static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)	2931	static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2932	{	2932	{
2933	u8 ddc_pin;	2933	enum phy phy = intel_port_to_phy(dev_priv, port);
2934		2934
2935	switch (port) {	2935	if (intel_phy_is_combo(dev_priv, phy))
2936	case PORT_A:	2936	return GMBUS_PIN_1_BXT + port;
2937	ddc_pin = GMBUS_PIN_1_BXT;	2937	else if (intel_phy_is_tc(dev_priv, phy))
2938	break;	2938	return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port);
2939	case PORT_B:	2939
2940	ddc_pin = GMBUS_PIN_2_BXT;	2940	WARN(1, "Unknown port:%c\n", port_name(port));
2941	break;	2941	return GMBUS_PIN_2_BXT;
2942	case PORT_C:
2943	ddc_pin = GMBUS_PIN_9_TC1_ICP;
2944	break;
2945	case PORT_D:
2946	ddc_pin = GMBUS_PIN_10_TC2_ICP;
2947	break;
2948	case PORT_E:
2949	ddc_pin = GMBUS_PIN_11_TC3_ICP;
2950	break;
2951	case PORT_F:
2952	ddc_pin = GMBUS_PIN_12_TC4_ICP;
2953	break;
2954	default:
2955	MISSING_CASE(port);
2956	ddc_pin = GMBUS_PIN_2_BXT;
2957	break;
2958	}
2959	return ddc_pin;
2960	}	2942	}
2961		2943
2962	static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)	2944	static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2963	{	2945	{
		2946	enum phy phy = intel_port_to_phy(dev_priv, port);
2964	u8 ddc_pin;	2947	u8 ddc_pin;
2965		2948
2966	switch (port) {	2949	switch (phy) {
2967	case PORT_A:	2950	case PHY_A:
2968	ddc_pin = GMBUS_PIN_1_BXT;	2951	ddc_pin = GMBUS_PIN_1_BXT;
2969	break;	2952	break;
2970	case PORT_B:	2953	case PHY_B:
2971	ddc_pin = GMBUS_PIN_2_BXT;	2954	ddc_pin = GMBUS_PIN_2_BXT;
2972	break;	2955	break;
2973	case PORT_C:	2956	case PHY_C:
2974	ddc_pin = GMBUS_PIN_9_TC1_ICP;	2957	ddc_pin = GMBUS_PIN_9_TC1_ICP;
2975	break;	2958	break;
2976	default:	2959	default:
2977	MISSING_CASE(port);	2960	MISSING_CASE(phy);
2978	ddc_pin = GMBUS_PIN_1_BXT;	2961	ddc_pin = GMBUS_PIN_1_BXT;
2979	break;	2962	break;
2980	}	2963	}
@@ -3019,7 +3002,7 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv, · 38 unmodified lines
3019		3002
3020	if (HAS_PCH_MCC(dev_priv))	3003	if (HAS_PCH_MCC(dev_priv))
3021	ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);	3004	ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
3022	else if (HAS_PCH_ICP(dev_priv))	3005	else if (HAS_PCH_TGP(dev_priv) \|\| HAS_PCH_ICP(dev_priv))
3023	ddc_pin = icl_port_to_ddc_pin(dev_priv, port);	3006	ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
3024	else if (HAS_PCH_CNP(dev_priv))	3007	else if (HAS_PCH_CNP(dev_priv))
3025	ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);	3008	ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
@@ -3143,6 +3126,32 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, · 117 unmodified lines
3143	DRM_DEBUG_KMS("CEC notifier get failed\n");	3126	DRM_DEBUG_KMS("CEC notifier get failed\n");
3144	}	3127	}
3145		3128
		3129	static enum intel_hotplug_state
		3130	intel_hdmi_hotplug(struct intel_encoder *encoder,
		3131	struct intel_connector *connector, bool irq_received)
		3132	{
		3133	enum intel_hotplug_state state;
		3134
		3135	state = intel_encoder_hotplug(encoder, connector, irq_received);
		3136
		3137	/*
		3138	* On many platforms the HDMI live state signal is known to be
		3139	* unreliable, so we can't use it to detect if a sink is connected or
		3140	* not. Instead we detect if it's connected based on whether we can
		3141	* read the EDID or not. That in turn has a problem during disconnect,
		3142	* since the HPD interrupt may be raised before the DDC lines get
		3143	* disconnected (due to how the required length of DDC vs. HPD
		3144	* connector pins are specified) and so we'll still be able to get a
		3145	* valid EDID. To solve this schedule another detection cycle if this
		3146	* time around we didn't detect any change in the sink's connection
		3147	* status.
		3148	*/
		3149	if (state == INTEL_HOTPLUG_UNCHANGED && irq_received)
		3150	state = INTEL_HOTPLUG_RETRY;
		3151
		3152	return state;
		3153	}
		3154
3146	void intel_hdmi_init(struct drm_i915_private *dev_priv,	3155	void intel_hdmi_init(struct drm_i915_private *dev_priv,
3147	i915_reg_t hdmi_reg, enum port port)	3156	i915_reg_t hdmi_reg, enum port port)
3148	{	3157	{
@@ -3166,7 +3175,7 @@ void intel_hdmi_init(struct drm_i915_private *dev_priv, · 17 unmodified lines
3166	&intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,	3175	&intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
3167	"HDMI %c", port_name(port));	3176	"HDMI %c", port_name(port));
3168		3177
3169	intel_encoder->hotplug = intel_encoder_hotplug;	3178	intel_encoder->hotplug = intel_hdmi_hotplug;
3170	intel_encoder->compute_config = intel_hdmi_compute_config;	3179	intel_encoder->compute_config = intel_hdmi_compute_config;
3171	if (HAS_PCH_SPLIT(dev_priv)) {	3180	if (HAS_PCH_SPLIT(dev_priv)) {
3172	intel_encoder->disable = pch_disable_hdmi;	3181	intel_encoder->disable = pch_disable_hdmi;

drivers/gpu/drm/i915/display/intel_hotplug.c+46−13

 #define HPD_STORM_DETECT_PERIOD		1000
 #define HPD_STORM_REENABLE_DELAY	(2 * 60 * 1000)
+#define HPD_RETRY_DELAY			1000
 /**
  * intel_hpd_irq_storm_detect - gather stats and detect HPD IRQ storm on a pin
 	intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
 }
-bool intel_encoder_hotplug(struct intel_encoder *encoder,
+enum intel_hotplug_state
-			   struct intel_connector *connector)
+intel_encoder_hotplug(struct intel_encoder *encoder,
+		      struct intel_connector *connector,
+		      bool irq_received)
 {
 	struct drm_device *dev = connector->base.dev;
 	enum drm_connector_status old_status;
 		drm_helper_probe_detect(&connector->base, NULL, false);
 	if (old_status == connector->base.status)
-		return false;
+		return INTEL_HOTPLUG_UNCHANGED;
 	DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
 		      connector->base.base.id,
 		      drm_get_connector_status_name(old_status),
 		      drm_get_connector_status_name(connector->base.status));
-	return true;
+	return INTEL_HOTPLUG_CHANGED;
 }
 static bool intel_encoder_has_hpd_pulse(struct intel_encoder *encoder)
 		spin_lock_irq(&dev_priv->irq_lock);
 		dev_priv->hotplug.event_bits |= old_bits;
 		spin_unlock_irq(&dev_priv->irq_lock);
-		schedule_work(&dev_priv->hotplug.hotplug_work);
+		queue_delayed_work(system_wq, &dev_priv->hotplug.hotplug_work, 0);
 	}
 }
 static void i915_hotplug_work_func(struct work_struct *work)
 {
 	struct drm_i915_private *dev_priv =
-		container_of(work, struct drm_i915_private, hotplug.hotplug_work);
+		container_of(work, struct drm_i915_private,
+			     hotplug.hotplug_work.work);
 	struct drm_device *dev = &dev_priv->drm;
 	struct intel_connector *intel_connector;
 	struct intel_encoder *intel_encoder;
 	struct drm_connector *connector;
 	struct drm_connector_list_iter conn_iter;
-	bool changed = false;
+	u32 changed = 0, retry = 0;
 	u32 hpd_event_bits;
+	u32 hpd_retry_bits;
 	mutex_lock(&dev->mode_config.mutex);
 	DRM_DEBUG_KMS("running encoder hotplug functions\n");
 	hpd_event_bits = dev_priv->hotplug.event_bits;
 	dev_priv->hotplug.event_bits = 0;
+	hpd_retry_bits = dev_priv->hotplug.retry_bits;
+	dev_priv->hotplug.retry_bits = 0;
 	/* Enable polling for connectors which had HPD IRQ storms */
 	intel_hpd_irq_storm_switch_to_polling(dev_priv);
 	drm_connector_list_iter_begin(dev, &conn_iter);
 	drm_for_each_connector_iter(connector, &conn_iter) {
+		u32 hpd_bit;
 		intel_connector = to_intel_connector(connector);
 		if (!intel_connector->encoder)
 			continue;
 		intel_encoder = intel_connector->encoder;
-		if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
+		hpd_bit = BIT(intel_encoder->hpd_pin);
+		if ((hpd_event_bits | hpd_retry_bits) & hpd_bit) {
 			DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
 				      connector->name, intel_encoder->hpd_pin);
-			changed |= intel_encoder->hotplug(intel_encoder,
+			switch (intel_encoder->hotplug(intel_encoder,
-							  intel_connector);
+						       intel_connector,
+						       hpd_event_bits & hpd_bit)) {
+			case INTEL_HOTPLUG_UNCHANGED:
+				break;
+			case INTEL_HOTPLUG_CHANGED:
+				changed |= hpd_bit;
+				break;
+			case INTEL_HOTPLUG_RETRY:
+				retry |= hpd_bit;
+				break;
+			}
 		}
 	}
 	drm_connector_list_iter_end(&conn_iter);
 	if (changed)
 		drm_kms_helper_hotplug_event(dev);
+	/* Remove shared HPD pins that have changed */
+	retry &= ~changed;
+	if (retry) {
+		spin_lock_irq(&dev_priv->irq_lock);
+		dev_priv->hotplug.retry_bits |= retry;
+		spin_unlock_irq(&dev_priv->irq_lock);
+		mod_delayed_work(system_wq, &dev_priv->hotplug.hotplug_work,
+				 msecs_to_jiffies(HPD_RETRY_DELAY));
+	}
 }
 	if (queue_dig)
 		queue_work(dev_priv->hotplug.dp_wq, &dev_priv->hotplug.dig_port_work);
 	if (queue_hp)
-		schedule_work(&dev_priv->hotplug.hotplug_work);
+		queue_delayed_work(system_wq, &dev_priv->hotplug.hotplug_work, 0);
 }
 /**
 void intel_hpd_init_work(struct drm_i915_private *dev_priv)
 {
-	INIT_WORK(&dev_priv->hotplug.hotplug_work, i915_hotplug_work_func);
+	INIT_DELAYED_WORK(&dev_priv->hotplug.hotplug_work,
+			  i915_hotplug_work_func);
 	INIT_WORK(&dev_priv->hotplug.dig_port_work, i915_digport_work_func);
 	INIT_WORK(&dev_priv->hotplug.poll_init_work, i915_hpd_poll_init_work);
 	INIT_DELAYED_WORK(&dev_priv->hotplug.reenable_work,
 	dev_priv->hotplug.long_port_mask = 0;
 	dev_priv->hotplug.short_port_mask = 0;
 	dev_priv->hotplug.event_bits = 0;
+	dev_priv->hotplug.retry_bits = 0;
 	spin_unlock_irq(&dev_priv->irq_lock);
 	cancel_work_sync(&dev_priv->hotplug.dig_port_work);
-	cancel_work_sync(&dev_priv->hotplug.hotplug_work);
+	cancel_delayed_work_sync(&dev_priv->hotplug.hotplug_work);
 	cancel_work_sync(&dev_priv->hotplug.poll_init_work);
 	cancel_delayed_work_sync(&dev_priv->hotplug.reenable_work);
 }

drivers/gpu/drm/i915/display/intel_hotplug.h+3−2

 struct intel_encoder;
 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
-bool intel_encoder_hotplug(struct intel_encoder *encoder,
+enum intel_hotplug_state intel_encoder_hotplug(struct intel_encoder *encoder,
-			   struct intel_connector *connector);
+					       struct intel_connector *connector,
+					       bool irq_received);
 void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
 			   u32 pin_mask, u32 long_mask);
 void intel_hpd_init(struct drm_i915_private *dev_priv);

drivers/gpu/drm/i915/display/intel_overlay.c+7−3

 struct intel_overlay {
 	struct drm_i915_private *i915;
+	struct intel_context *context;
 	struct intel_crtc *crtc;
 	struct i915_vma *vma;
 	struct i915_vma *old_vma;
 static struct i915_request *alloc_request(struct intel_overlay *overlay)
 {
-	struct intel_engine_cs *engine = overlay->i915->engine[RCS0];
+	return i915_request_create(overlay->context);
-	return i915_request_create(engine->kernel_context);
 }
 /* overlay needs to be disable in OCMD reg */
 	if (!HAS_OVERLAY(dev_priv))
 		return;
+	if (!HAS_ENGINE(dev_priv, RCS0))
+		return;
 	overlay = kzalloc(sizeof(*overlay), GFP_KERNEL);
 	if (!overlay)
 		return;
 	overlay->i915 = dev_priv;
+	overlay->context = dev_priv->engine[RCS0]->kernel_context;
+	GEM_BUG_ON(!overlay->context);
 	overlay->color_key = 0x0101fe;
 	overlay->color_key_enabled = true;

drivers/gpu/drm/i915/display/intel_pipe_crc.c+1−1

@@ -667,5 +667,5 @@ void intel_crtc_disable_pipe_crc(struct intel_crtc *intel_crtc) · 666 unmodified lines
667		667
668	I915_WRITE(PIPE_CRC_CTL(crtc->index), 0);	668	I915_WRITE(PIPE_CRC_CTL(crtc->index), 0);
669	POSTING_READ(PIPE_CRC_CTL(crtc->index));	669	POSTING_READ(PIPE_CRC_CTL(crtc->index));
670	synchronize_irq(dev_priv->drm.irq);	670	intel_synchronize_irq(dev_priv);
671	}	671	}

drivers/gpu/drm/i915/display/intel_sdvo.c+172−142

@@ -274,130 +274,145 @@ static bool intel_sdvo_read_byte(struct intel_sdvo intel_sdvo, u8 addr, u8 ch) · 273 unmodified lines
274	return false;	274	return false;
275	}	275	}
276		276
277	#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}	277	#define SDVO_CMD_NAME_ENTRY(cmd_) { .cmd = SDVO_CMD_ ## cmd_, .name = #cmd_ }
		278
278	/** Mapping of command numbers to names, for debug output */	279	/** Mapping of command numbers to names, for debug output */
279	static const struct _sdvo_cmd_name {	280	static const struct {
280	u8 cmd;	281	u8 cmd;
281	const char *name;	282	const char *name;
282	} __attribute__ ((packed)) sdvo_cmd_names[] = {	283	} __attribute__ ((packed)) sdvo_cmd_names[] = {
283	SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),	284	SDVO_CMD_NAME_ENTRY(RESET),
284	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),	285	SDVO_CMD_NAME_ENTRY(GET_DEVICE_CAPS),
285	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),	286	SDVO_CMD_NAME_ENTRY(GET_FIRMWARE_REV),
286	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),	287	SDVO_CMD_NAME_ENTRY(GET_TRAINED_INPUTS),
287	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),	288	SDVO_CMD_NAME_ENTRY(GET_ACTIVE_OUTPUTS),
288	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),	289	SDVO_CMD_NAME_ENTRY(SET_ACTIVE_OUTPUTS),
289	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),	290	SDVO_CMD_NAME_ENTRY(GET_IN_OUT_MAP),
290	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),	291	SDVO_CMD_NAME_ENTRY(SET_IN_OUT_MAP),
291	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),	292	SDVO_CMD_NAME_ENTRY(GET_ATTACHED_DISPLAYS),
292	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),	293	SDVO_CMD_NAME_ENTRY(GET_HOT_PLUG_SUPPORT),
293	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),	294	SDVO_CMD_NAME_ENTRY(SET_ACTIVE_HOT_PLUG),
294	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),	295	SDVO_CMD_NAME_ENTRY(GET_ACTIVE_HOT_PLUG),
295	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),	296	SDVO_CMD_NAME_ENTRY(GET_INTERRUPT_EVENT_SOURCE),
296	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),	297	SDVO_CMD_NAME_ENTRY(SET_TARGET_INPUT),
297	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),	298	SDVO_CMD_NAME_ENTRY(SET_TARGET_OUTPUT),
298	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),	299	SDVO_CMD_NAME_ENTRY(GET_INPUT_TIMINGS_PART1),
299	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),	300	SDVO_CMD_NAME_ENTRY(GET_INPUT_TIMINGS_PART2),
300	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),	301	SDVO_CMD_NAME_ENTRY(SET_INPUT_TIMINGS_PART1),
301	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),	302	SDVO_CMD_NAME_ENTRY(SET_INPUT_TIMINGS_PART2),
302	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),	303	SDVO_CMD_NAME_ENTRY(SET_OUTPUT_TIMINGS_PART1),
303	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),	304	SDVO_CMD_NAME_ENTRY(SET_OUTPUT_TIMINGS_PART2),
304	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),	305	SDVO_CMD_NAME_ENTRY(GET_OUTPUT_TIMINGS_PART1),
305	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),	306	SDVO_CMD_NAME_ENTRY(GET_OUTPUT_TIMINGS_PART2),
306	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),	307	SDVO_CMD_NAME_ENTRY(CREATE_PREFERRED_INPUT_TIMING),
307	SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),	308	SDVO_CMD_NAME_ENTRY(GET_PREFERRED_INPUT_TIMING_PART1),
308	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),	309	SDVO_CMD_NAME_ENTRY(GET_PREFERRED_INPUT_TIMING_PART2),
309	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),	310	SDVO_CMD_NAME_ENTRY(GET_INPUT_PIXEL_CLOCK_RANGE),
310	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),	311	SDVO_CMD_NAME_ENTRY(GET_OUTPUT_PIXEL_CLOCK_RANGE),
311	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),	312	SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_CLOCK_RATE_MULTS),
312	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),	313	SDVO_CMD_NAME_ENTRY(GET_CLOCK_RATE_MULT),
313	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),	314	SDVO_CMD_NAME_ENTRY(SET_CLOCK_RATE_MULT),
314	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),	315	SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_TV_FORMATS),
315	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),	316	SDVO_CMD_NAME_ENTRY(GET_TV_FORMAT),
316	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),	317	SDVO_CMD_NAME_ENTRY(SET_TV_FORMAT),
317	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),	318	SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_POWER_STATES),
318	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),	319	SDVO_CMD_NAME_ENTRY(GET_POWER_STATE),
319	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),	320	SDVO_CMD_NAME_ENTRY(SET_ENCODER_POWER_STATE),
320	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),	321	SDVO_CMD_NAME_ENTRY(SET_DISPLAY_POWER_STATE),
321	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),	322	SDVO_CMD_NAME_ENTRY(SET_CONTROL_BUS_SWITCH),
322	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),	323	SDVO_CMD_NAME_ENTRY(GET_SDTV_RESOLUTION_SUPPORT),
323	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),	324	SDVO_CMD_NAME_ENTRY(GET_SCALED_HDTV_RESOLUTION_SUPPORT),
324	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),	325	SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_ENHANCEMENTS),
325	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
326		326
327	/* Add the op code for SDVO enhancements */	327	/* Add the op code for SDVO enhancements */
328	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),	328	SDVO_CMD_NAME_ENTRY(GET_MAX_HPOS),
329	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),	329	SDVO_CMD_NAME_ENTRY(GET_HPOS),
330	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),	330	SDVO_CMD_NAME_ENTRY(SET_HPOS),
331	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),	331	SDVO_CMD_NAME_ENTRY(GET_MAX_VPOS),
332	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),	332	SDVO_CMD_NAME_ENTRY(GET_VPOS),
333	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),	333	SDVO_CMD_NAME_ENTRY(SET_VPOS),
334	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),	334	SDVO_CMD_NAME_ENTRY(GET_MAX_SATURATION),
335	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),	335	SDVO_CMD_NAME_ENTRY(GET_SATURATION),
336	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),	336	SDVO_CMD_NAME_ENTRY(SET_SATURATION),
337	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),	337	SDVO_CMD_NAME_ENTRY(GET_MAX_HUE),
338	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),	338	SDVO_CMD_NAME_ENTRY(GET_HUE),
339	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),	339	SDVO_CMD_NAME_ENTRY(SET_HUE),
340	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),	340	SDVO_CMD_NAME_ENTRY(GET_MAX_CONTRAST),
341	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),	341	SDVO_CMD_NAME_ENTRY(GET_CONTRAST),
342	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),	342	SDVO_CMD_NAME_ENTRY(SET_CONTRAST),
343	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),	343	SDVO_CMD_NAME_ENTRY(GET_MAX_BRIGHTNESS),
344	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),	344	SDVO_CMD_NAME_ENTRY(GET_BRIGHTNESS),
345	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),	345	SDVO_CMD_NAME_ENTRY(SET_BRIGHTNESS),
346	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),	346	SDVO_CMD_NAME_ENTRY(GET_MAX_OVERSCAN_H),
347	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),	347	SDVO_CMD_NAME_ENTRY(GET_OVERSCAN_H),
348	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),	348	SDVO_CMD_NAME_ENTRY(SET_OVERSCAN_H),
349	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),	349	SDVO_CMD_NAME_ENTRY(GET_MAX_OVERSCAN_V),
350	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),	350	SDVO_CMD_NAME_ENTRY(GET_OVERSCAN_V),
351	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),	351	SDVO_CMD_NAME_ENTRY(SET_OVERSCAN_V),
352	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),	352	SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER),
353	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),	353	SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER),
354	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),	354	SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER),
355	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),	355	SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER_ADAPTIVE),
356	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),	356	SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER_ADAPTIVE),
357	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),	357	SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER_ADAPTIVE),
358	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),	358	SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER_2D),
359	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),	359	SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER_2D),
360	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),	360	SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER_2D),
361	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),	361	SDVO_CMD_NAME_ENTRY(GET_MAX_SHARPNESS),
362	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),	362	SDVO_CMD_NAME_ENTRY(GET_SHARPNESS),
363	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),	363	SDVO_CMD_NAME_ENTRY(SET_SHARPNESS),
364	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),	364	SDVO_CMD_NAME_ENTRY(GET_DOT_CRAWL),
365	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),	365	SDVO_CMD_NAME_ENTRY(SET_DOT_CRAWL),
366	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),	366	SDVO_CMD_NAME_ENTRY(GET_MAX_TV_CHROMA_FILTER),
367	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),	367	SDVO_CMD_NAME_ENTRY(GET_TV_CHROMA_FILTER),
368	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),	368	SDVO_CMD_NAME_ENTRY(SET_TV_CHROMA_FILTER),
369	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),	369	SDVO_CMD_NAME_ENTRY(GET_MAX_TV_LUMA_FILTER),
370	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),	370	SDVO_CMD_NAME_ENTRY(GET_TV_LUMA_FILTER),
371	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),	371	SDVO_CMD_NAME_ENTRY(SET_TV_LUMA_FILTER),
372		372
373	/* HDMI op code */	373	/* HDMI op code */
374	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),	374	SDVO_CMD_NAME_ENTRY(GET_SUPP_ENCODE),
375	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),	375	SDVO_CMD_NAME_ENTRY(GET_ENCODE),
376	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),	376	SDVO_CMD_NAME_ENTRY(SET_ENCODE),
377	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),	377	SDVO_CMD_NAME_ENTRY(SET_PIXEL_REPLI),
378	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),	378	SDVO_CMD_NAME_ENTRY(GET_PIXEL_REPLI),
379	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),	379	SDVO_CMD_NAME_ENTRY(GET_COLORIMETRY_CAP),
380	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),	380	SDVO_CMD_NAME_ENTRY(SET_COLORIMETRY),
381	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),	381	SDVO_CMD_NAME_ENTRY(GET_COLORIMETRY),
382	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),	382	SDVO_CMD_NAME_ENTRY(GET_AUDIO_ENCRYPT_PREFER),
383	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),	383	SDVO_CMD_NAME_ENTRY(SET_AUDIO_STAT),
384	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),	384	SDVO_CMD_NAME_ENTRY(GET_AUDIO_STAT),
385	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),	385	SDVO_CMD_NAME_ENTRY(GET_HBUF_INDEX),
386	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),	386	SDVO_CMD_NAME_ENTRY(SET_HBUF_INDEX),
387	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),	387	SDVO_CMD_NAME_ENTRY(GET_HBUF_INFO),
388	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),	388	SDVO_CMD_NAME_ENTRY(GET_HBUF_AV_SPLIT),
389	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),	389	SDVO_CMD_NAME_ENTRY(SET_HBUF_AV_SPLIT),
390	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),	390	SDVO_CMD_NAME_ENTRY(GET_HBUF_TXRATE),
391	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),	391	SDVO_CMD_NAME_ENTRY(SET_HBUF_TXRATE),
392	SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),	392	SDVO_CMD_NAME_ENTRY(SET_HBUF_DATA),
393	SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),	393	SDVO_CMD_NAME_ENTRY(GET_HBUF_DATA),
394	};	394	};
395		395
		396	#undef SDVO_CMD_NAME_ENTRY
		397
		398	static const char *sdvo_cmd_name(u8 cmd)
		399	{
		400	int i;
		401
		402	for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
		403	if (cmd == sdvo_cmd_names[i].cmd)
		404	return sdvo_cmd_names[i].name;
		405	}
		406
		407	return NULL;
		408	}
		409
396	#define SDVO_NAME(svdo) ((svdo)->port == PORT_B ? "SDVOB" : "SDVOC")	410	#define SDVO_NAME(svdo) ((svdo)->port == PORT_B ? "SDVOB" : "SDVOC")
397		411
398	static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,	412	static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
399	const void *args, int args_len)	413	const void *args, int args_len)
400	{	414	{
		415	const char *cmd_name;
401	int i, pos = 0;	416	int i, pos = 0;
402	#define BUF_LEN 256	417	#define BUF_LEN 256
403	char buffer[BUF_LEN];	418	char buffer[BUF_LEN];
@@ -412,15 +427,12 @@ static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd, · 8 unmodified lines
412	for (; i < 8; i++) {	427	for (; i < 8; i++) {
413	BUF_PRINT(" ");	428	BUF_PRINT(" ");
414	}	429	}
415	for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {	430
416	if (cmd == sdvo_cmd_names[i].cmd) {	431	cmd_name = sdvo_cmd_name(cmd);
417	BUF_PRINT("(%s)", sdvo_cmd_names[i].name);	432	if (cmd_name)
418	break;	433	BUF_PRINT("(%s)", cmd_name);
419	}	434	else
420	}
421	if (i == ARRAY_SIZE(sdvo_cmd_names)) {
422	BUF_PRINT("(%02X)", cmd);	435	BUF_PRINT("(%02X)", cmd);
423	}
424	BUG_ON(pos >= BUF_LEN - 1);	436	BUG_ON(pos >= BUF_LEN - 1);
425	#undef BUF_PRINT	437	#undef BUF_PRINT
426	#undef BUF_LEN	438	#undef BUF_LEN
@@ -429,15 +441,23 @@ static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd, · 2 unmodified lines
429	}	441	}
430		442
431	static const char * const cmd_status_names[] = {	443	static const char * const cmd_status_names[] = {
432	"Power on",	444	[SDVO_CMD_STATUS_POWER_ON] = "Power on",
433	"Success",	445	[SDVO_CMD_STATUS_SUCCESS] = "Success",
434	"Not supported",	446	[SDVO_CMD_STATUS_NOTSUPP] = "Not supported",
435	"Invalid arg",	447	[SDVO_CMD_STATUS_INVALID_ARG] = "Invalid arg",
436	"Pending",	448	[SDVO_CMD_STATUS_PENDING] = "Pending",
437	"Target not specified",	449	[SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED] = "Target not specified",
438	"Scaling not supported"	450	[SDVO_CMD_STATUS_SCALING_NOT_SUPP] = "Scaling not supported",
439	};	451	};
440		452
		453	static const char *sdvo_cmd_status(u8 status)
		454	{
		455	if (status < ARRAY_SIZE(cmd_status_names))
		456	return cmd_status_names[status];
		457	else
		458	return NULL;
		459	}
		460
441	static bool __intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,	461	static bool __intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
442	const void *args, int args_len,	462	const void *args, int args_len,
443	bool unlocked)	463	bool unlocked)
@@ -516,6 +536,7 @@ static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, · 72 unmodified lines
516	static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,	536	static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
517	void *response, int response_len)	537	void *response, int response_len)
518	{	538	{
		539	const char *cmd_status;
519	u8 retry = 15; /* 5 quick checks, followed by 10 long checks */	540	u8 retry = 15; /* 5 quick checks, followed by 10 long checks */
520	u8 status;	541	u8 status;
521	int i, pos = 0;	542	int i, pos = 0;
@@ -562,8 +583,9 @@ static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, · 40 unmodified lines
562	#define BUF_PRINT(args...) \	583	#define BUF_PRINT(args...) \
563	pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args)	584	pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args)
564		585
565	if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)	586	cmd_status = sdvo_cmd_status(status);
566	BUF_PRINT("(%s)", cmd_status_names[status]);	587	if (cmd_status)
		588	BUF_PRINT("(%s)", cmd_status);
567	else	589	else
568	BUF_PRINT("(??? %d)", status);	590	BUF_PRINT("(??? %d)", status);
569		591
@@ -929,6 +951,20 @@ static bool intel_sdvo_set_audio_state(struct intel_sdvo *intel_sdvo, · 359 unmodified lines
929	&audio_state, 1);	951	&audio_state, 1);
930	}	952	}
931		953
		954	static bool intel_sdvo_get_hbuf_size(struct intel_sdvo *intel_sdvo,
		955	u8 *hbuf_size)
		956	{
		957	if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
		958	hbuf_size, 1))
		959	return false;
		960
		961	/* Buffer size is 0 based, hooray! However zero means zero. */
		962	if (*hbuf_size)
		963	(*hbuf_size)++;
		964
		965	return true;
		966	}
		967
932	#if 0	968	#if 0
933	static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)	969	static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
934	{	970	{
@@ -972,14 +1008,10 @@ static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo, · 37 unmodified lines
972	set_buf_index, 2))	1008	set_buf_index, 2))
973	return false;	1009	return false;
974		1010
975	if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,	1011	if (!intel_sdvo_get_hbuf_size(intel_sdvo, &hbuf_size))
976	&hbuf_size, 1))
977	return false;	1012	return false;
978		1013
979	/* Buffer size is 0 based, hooray! */	1014	DRM_DEBUG_KMS("writing sdvo hbuf: %i, length %u, hbuf_size: %i\n",
980	hbuf_size++;
981
982	DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",
983	if_index, length, hbuf_size);	1015	if_index, length, hbuf_size);
984		1016
985	if (hbuf_size < length)	1017	if (hbuf_size < length)
@@ -1030,14 +1062,10 @@ static ssize_t intel_sdvo_read_infoframe(struct intel_sdvo *intel_sdvo, · 44 unmodified lines
1030	if (tx_rate == SDVO_HBUF_TX_DISABLED)	1062	if (tx_rate == SDVO_HBUF_TX_DISABLED)
1031	return 0;	1063	return 0;
1032		1064
1033	if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,	1065	if (!intel_sdvo_get_hbuf_size(intel_sdvo, &hbuf_size))
1034	&hbuf_size, 1))	1066	return false;
1035	return -ENXIO;
1036
1037	/* Buffer size is 0 based, hooray! */
1038	hbuf_size++;
1039		1067
1040	DRM_DEBUG_KMS("reading sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",	1068	DRM_DEBUG_KMS("reading sdvo hbuf: %i, length %u, hbuf_size: %i\n",
1041	if_index, length, hbuf_size);	1069	if_index, length, hbuf_size);
1042		1070
1043	hbuf_size = min_t(unsigned int, length, hbuf_size);	1071	hbuf_size = min_t(unsigned int, length, hbuf_size);
@@ -1893,12 +1921,14 @@ static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder) · 849 unmodified lines
1893	&intel_sdvo->hotplug_active, 2);	1921	&intel_sdvo->hotplug_active, 2);
1894	}	1922	}
1895		1923
1896	static bool intel_sdvo_hotplug(struct intel_encoder *encoder,	1924	static enum intel_hotplug_state
1897	struct intel_connector *connector)	1925	intel_sdvo_hotplug(struct intel_encoder *encoder,
		1926	struct intel_connector *connector,
		1927	bool irq_received)
1898	{	1928	{
1899	intel_sdvo_enable_hotplug(encoder);	1929	intel_sdvo_enable_hotplug(encoder);
1900		1930
1901	return intel_encoder_hotplug(encoder, connector);	1931	return intel_encoder_hotplug(encoder, connector, irq_received);
1902	}	1932	}
1903		1933
1904	static bool	1934	static bool

drivers/gpu/drm/i915/display/intel_sprite.c+252−83

 		 */
 		[DRM_COLOR_YCBCR_BT709] = {
 			0x7C98, 0x7800, 0x0,
-			0x9EF8, 0x7800, 0xABF8,
+			0x9EF8, 0x7800, 0xAC00,
 			0x0, 0x7800,  0x7ED8,
 		},
+		/*
+		 * BT.2020 full range YCbCr -> full range RGB
+		 * The matrix required is :
+		 * [1.000, 0.000, 1.474,
+		 *  1.000, -0.1645, -0.5713,
+		 *  1.000, 1.8814, 0.0000]
+		 */
+		[DRM_COLOR_YCBCR_BT2020] = {
+			0x7BC8, 0x7800, 0x0,
+			0x8928, 0x7800, 0xAA88,
+			0x0, 0x7800, 0x7F10,
+		},
 	};
 	/* Matrix for Limited Range to Full Range Conversion */
 		/*
 		 * BT.601 Limted range YCbCr -> full range RGB
 		 * The matrix required is :
-		 * [1.164384, 0.000, 1.596370,
+		 * [1.164384, 0.000, 1.596027,
-		 *  1.138393, -0.382500, -0.794598,
+		 *  1.164384, -0.39175, -0.812813,
-		 *  1.138393, 1.971696, 0.0000]
+		 *  1.164384, 2.017232, 0.0000]
 		 */
 		[DRM_COLOR_YCBCR_BT601] = {
 			0x7CC8, 0x7950, 0x0,
-			0x8CB8, 0x7918, 0x9C40,
+			0x8D00, 0x7950, 0x9C88,
-			0x0, 0x7918, 0x7FC8,
+			0x0, 0x7950, 0x6810,
 		},
 		/*
 		 * BT.709 Limited range YCbCr -> full range RGB
 		 * The matrix required is :
-		 * [1.164, 0.000, 1.833671,
+		 * [1.164384, 0.000, 1.792741,
-		 *  1.138393, -0.213249, -0.532909,
+		 *  1.164384, -0.213249, -0.532909,
-		 *  1.138393, 2.112402, 0.0000]
+		 *  1.164384, 2.112402, 0.0000]
 		 */
 		[DRM_COLOR_YCBCR_BT709] = {
-			0x7EA8, 0x7950, 0x0,
+			0x7E58, 0x7950, 0x0,
-			0x8888, 0x7918, 0xADA8,
+			0x8888, 0x7950, 0xADA8,
-			0x0, 0x7918,  0x6870,
+			0x0, 0x7950,  0x6870,
+		},
+		/*
+		 * BT.2020 Limited range YCbCr -> full range RGB
+		 * The matrix required is :
+		 * [1.164, 0.000, 1.678,
+		 *  1.164, -0.1873, -0.6504,
+		 *  1.164, 2.1417, 0.0000]
+		 */
+		[DRM_COLOR_YCBCR_BT2020] = {
+			0x7D70, 0x7950, 0x0,
+			0x8A68, 0x7950, 0xAC00,
+			0x0, 0x7950, 0x6890,
 		},
 	};
 	const u16 *csc;
 	I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 0),
 		      PREOFF_YUV_TO_RGB_HI);
-	I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1),
+	if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
-		      PREOFF_YUV_TO_RGB_ME);
+		I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1), 0);
+	else
+		I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1),
+			      PREOFF_YUV_TO_RGB_ME);
 	I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 2),
 		      PREOFF_YUV_TO_RGB_LO);
 	I915_WRITE_FW(PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 0), 0x0);
 	return ret;
 }
+static void i9xx_plane_linear_gamma(u16 gamma[8])
+{
+	/* The points are not evenly spaced. */
+	static const u8 in[8] = { 0, 1, 2, 4, 8, 16, 24, 32 };
+	int i;
+	for (i = 0; i < 8; i++)
+		gamma[i] = (in[i] << 8) / 32;
+}
 static void
 chv_update_csc(const struct intel_plane_state *plane_state)
 {
 	return sprctl;
 }
+static void vlv_update_gamma(const struct intel_plane_state *plane_state)
+{
+	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+	const struct drm_framebuffer *fb = plane_state->base.fb;
+	enum pipe pipe = plane->pipe;
+	enum plane_id plane_id = plane->id;
+	u16 gamma[8];
+	int i;
+	/* Seems RGB data bypasses the gamma always */
+	if (!fb->format->is_yuv)
+		return;
+	i9xx_plane_linear_gamma(gamma);
+	/* FIXME these register are single buffered :( */
+	/* The two end points are implicit (0.0 and 1.0) */
+	for (i = 1; i < 8 - 1; i++)
+		I915_WRITE_FW(SPGAMC(pipe, plane_id, i - 1),
+			      gamma[i] << 16 |
+			      gamma[i] << 8 |
+			      gamma[i]);
+}
 static void
 vlv_update_plane(struct intel_plane *plane,
 		 const struct intel_crtc_state *crtc_state,
 		      intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
 	vlv_update_clrc(plane_state);
+	vlv_update_gamma(plane_state);
 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 }
 		return 0;
 	}
+	sprctl |= SPRITE_INT_GAMMA_DISABLE;
 	if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
 		sprctl |= SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709;
 	return sprctl;
 }
+static void ivb_sprite_linear_gamma(u16 gamma[18])
+{
+	int i;
+	for (i = 0; i < 17; i++)
+		gamma[i] = (i << 10) / 16;
+	gamma[i] = 3 << 10;
+	i++;
+}
+static void ivb_update_gamma(const struct intel_plane_state *plane_state)
+{
+	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+	enum pipe pipe = plane->pipe;
+	u16 gamma[18];
+	int i;
+	ivb_sprite_linear_gamma(gamma);
+	/* FIXME these register are single buffered :( */
+	for (i = 0; i < 16; i++)
+		I915_WRITE_FW(SPRGAMC(pipe, i),
+			      gamma[i] << 20 |
+			      gamma[i] << 10 |
+			      gamma[i]);
+	I915_WRITE_FW(SPRGAMC16(pipe, 0), gamma[i]);
+	I915_WRITE_FW(SPRGAMC16(pipe, 1), gamma[i]);
+	I915_WRITE_FW(SPRGAMC16(pipe, 2), gamma[i]);
+	i++;
+	I915_WRITE_FW(SPRGAMC17(pipe, 0), gamma[i]);
+	I915_WRITE_FW(SPRGAMC17(pipe, 1), gamma[i]);
+	I915_WRITE_FW(SPRGAMC17(pipe, 2), gamma[i]);
+	i++;
+}
 static void
 ivb_update_plane(struct intel_plane *plane,
 		 const struct intel_crtc_state *crtc_state,
 	I915_WRITE_FW(SPRSURF(pipe),
 		      intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
+	ivb_update_gamma(plane_state);
 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 }
 	return dvscntr;
 }
+static void g4x_update_gamma(const struct intel_plane_state *plane_state)
+{
+	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+	const struct drm_framebuffer *fb = plane_state->base.fb;
+	enum pipe pipe = plane->pipe;
+	u16 gamma[8];
+	int i;
+	/* Seems RGB data bypasses the gamma always */
+	if (!fb->format->is_yuv)
+		return;
+	i9xx_plane_linear_gamma(gamma);
+	/* FIXME these register are single buffered :( */
+	/* The two end points are implicit (0.0 and 1.0) */
+	for (i = 1; i < 8 - 1; i++)
+		I915_WRITE_FW(DVSGAMC_G4X(pipe, i - 1),
+			      gamma[i] << 16 |
+			      gamma[i] << 8 |
+			      gamma[i]);
+}
+static void ilk_sprite_linear_gamma(u16 gamma[17])
+{
+	int i;
+	for (i = 0; i < 17; i++)
+		gamma[i] = (i << 10) / 16;
+}
+static void ilk_update_gamma(const struct intel_plane_state *plane_state)
+{
+	struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+	const struct drm_framebuffer *fb = plane_state->base.fb;
+	enum pipe pipe = plane->pipe;
+	u16 gamma[17];
+	int i;
+	/* Seems RGB data bypasses the gamma always */
+	if (!fb->format->is_yuv)
+		return;
+	ilk_sprite_linear_gamma(gamma);
+	/* FIXME these register are single buffered :( */
+	for (i = 0; i < 16; i++)
+		I915_WRITE_FW(DVSGAMC_ILK(pipe, i),
+			      gamma[i] << 20 |
+			      gamma[i] << 10 |
+			      gamma[i]);
+	I915_WRITE_FW(DVSGAMCMAX_ILK(pipe, 0), gamma[i]);
+	I915_WRITE_FW(DVSGAMCMAX_ILK(pipe, 1), gamma[i]);
+	I915_WRITE_FW(DVSGAMCMAX_ILK(pipe, 2), gamma[i]);
+	i++;
+}
 static void
 g4x_update_plane(struct intel_plane *plane,
 		 const struct intel_crtc_state *crtc_state,
 	I915_WRITE_FW(DVSSURF(pipe),
 		      intel_plane_ggtt_offset(plane_state) + dvssurf_offset);
+	if (IS_G4X(dev_priv))
+		g4x_update_gamma(plane_state);
+	else
+		ilk_update_gamma(plane_state);
 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 }
 	const struct drm_framebuffer *fb = plane_state->base.fb;
 	const struct drm_rect *src = &plane_state->base.src;
 	const struct drm_rect *dst = &plane_state->base.dst;
-	int src_x, src_y, src_w, src_h, crtc_w, crtc_h;
+	int src_x, src_w, src_h, crtc_w, crtc_h;
 	const struct drm_display_mode *adjusted_mode =
 		&crtc_state->base.adjusted_mode;
 	unsigned int cpp = fb->format->cpp[0];
 	crtc_h = drm_rect_height(dst);
 	src_x = src->x1 >> 16;
-	src_y = src->y1 >> 16;
 	src_w = drm_rect_width(src) >> 16;
 	src_h = drm_rect_height(src) >> 16;
 	DRM_FORMAT_VYUY,
 };
-static const u32 icl_plane_formats[] = {
+static const u32 skl_planar_formats[] = {
-	DRM_FORMAT_C8,
-	DRM_FORMAT_RGB565,
-	DRM_FORMAT_XRGB8888,
-	DRM_FORMAT_XBGR8888,
-	DRM_FORMAT_ARGB8888,
-	DRM_FORMAT_ABGR8888,
-	DRM_FORMAT_XRGB2101010,
-	DRM_FORMAT_XBGR2101010,
-	DRM_FORMAT_YUYV,
-	DRM_FORMAT_YVYU,
-	DRM_FORMAT_UYVY,
-	DRM_FORMAT_VYUY,
-	DRM_FORMAT_Y210,
-	DRM_FORMAT_Y212,
-	DRM_FORMAT_Y216,
-	DRM_FORMAT_XVYU2101010,
-	DRM_FORMAT_XVYU12_16161616,
-	DRM_FORMAT_XVYU16161616,
-};
-static const u32 icl_hdr_plane_formats[] = {
 	DRM_FORMAT_C8,
 	DRM_FORMAT_RGB565,
 	DRM_FORMAT_XRGB8888,
 	DRM_FORMAT_ABGR8888,
 	DRM_FORMAT_XRGB2101010,
 	DRM_FORMAT_XBGR2101010,
-	DRM_FORMAT_XRGB16161616F,
-	DRM_FORMAT_XBGR16161616F,
-	DRM_FORMAT_ARGB16161616F,
-	DRM_FORMAT_ABGR16161616F,
 	DRM_FORMAT_YUYV,
 	DRM_FORMAT_YVYU,
 	DRM_FORMAT_UYVY,
 	DRM_FORMAT_VYUY,
-	DRM_FORMAT_Y210,
+	DRM_FORMAT_NV12,
-	DRM_FORMAT_Y212,
-	DRM_FORMAT_Y216,
-	DRM_FORMAT_XVYU2101010,
-	DRM_FORMAT_XVYU12_16161616,
-	DRM_FORMAT_XVYU16161616,
 };
-static const u32 skl_planar_formats[] = {
+static const u32 glk_planar_formats[] = {
 	DRM_FORMAT_C8,
 	DRM_FORMAT_RGB565,
 	DRM_FORMAT_XRGB8888,
 	DRM_FORMAT_UYVY,
 	DRM_FORMAT_VYUY,
 	DRM_FORMAT_NV12,
+	DRM_FORMAT_P010,
+	DRM_FORMAT_P012,
+	DRM_FORMAT_P016,
 };
-static const u32 glk_planar_formats[] = {
+static const u32 icl_sdr_y_plane_formats[] = {
 	DRM_FORMAT_C8,
 	DRM_FORMAT_RGB565,
 	DRM_FORMAT_XRGB8888,
 	DRM_FORMAT_YVYU,
 	DRM_FORMAT_UYVY,
 	DRM_FORMAT_VYUY,
-	DRM_FORMAT_NV12,
+	DRM_FORMAT_Y210,
-	DRM_FORMAT_P010,
+	DRM_FORMAT_Y212,
-	DRM_FORMAT_P012,
+	DRM_FORMAT_Y216,
-	DRM_FORMAT_P016,
+	DRM_FORMAT_XVYU2101010,
+	DRM_FORMAT_XVYU12_16161616,
+	DRM_FORMAT_XVYU16161616,
 };
-static const u32 icl_planar_formats[] = {
+static const u32 icl_sdr_uv_plane_formats[] = {
 	DRM_FORMAT_C8,
 	DRM_FORMAT_RGB565,
 	DRM_FORMAT_XRGB8888,
 	DRM_FORMAT_XVYU16161616,
 };
-static const u32 icl_hdr_planar_formats[] = {
+static const u32 icl_hdr_plane_formats[] = {
 	DRM_FORMAT_C8,
 	DRM_FORMAT_RGB565,
 	DRM_FORMAT_XRGB8888,
 static bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
 				 enum pipe pipe, enum plane_id plane_id)
 {
-	if (INTEL_GEN(dev_priv) >= 11)
-		return plane_id <= PLANE_SPRITE3;
 	/* Display WA #0870: skl, bxt */
 	if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
 		return false;
 	return true;
 }
+static const u32 *skl_get_plane_formats(struct drm_i915_private *dev_priv,
+					enum pipe pipe, enum plane_id plane_id,
+					int *num_formats)
+{
+	if (skl_plane_has_planar(dev_priv, pipe, plane_id)) {
+		*num_formats = ARRAY_SIZE(skl_planar_formats);
+		return skl_planar_formats;
+	} else {
+		*num_formats = ARRAY_SIZE(skl_plane_formats);
+		return skl_plane_formats;
+	}
+}
+static const u32 *glk_get_plane_formats(struct drm_i915_private *dev_priv,
+					enum pipe pipe, enum plane_id plane_id,
+					int *num_formats)
+{
+	if (skl_plane_has_planar(dev_priv, pipe, plane_id)) {
+		*num_formats = ARRAY_SIZE(glk_planar_formats);
+		return glk_planar_formats;
+	} else {
+		*num_formats = ARRAY_SIZE(skl_plane_formats);
+		return skl_plane_formats;
+	}
+}
+static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv,
+					enum pipe pipe, enum plane_id plane_id,
+					int *num_formats)
+{
+	if (icl_is_hdr_plane(dev_priv, plane_id)) {
+		*num_formats = ARRAY_SIZE(icl_hdr_plane_formats);
+		return icl_hdr_plane_formats;
+	} else if (icl_is_nv12_y_plane(plane_id)) {
+		*num_formats = ARRAY_SIZE(icl_sdr_y_plane_formats);
+		return icl_sdr_y_plane_formats;
+	} else {
+		*num_formats = ARRAY_SIZE(icl_sdr_uv_plane_formats);
+		return icl_sdr_uv_plane_formats;
+	}
+}
 static bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
 			      enum pipe pipe, enum plane_id plane_id)
 {
 	if (icl_is_nv12_y_plane(plane_id))
 		plane->update_slave = icl_update_slave;
-	if (skl_plane_has_planar(dev_priv, pipe, plane_id)) {
+	if (INTEL_GEN(dev_priv) >= 11)
-		if (icl_is_hdr_plane(dev_priv, plane_id)) {
+		formats = icl_get_plane_formats(dev_priv, pipe,
-			formats = icl_hdr_planar_formats;
+						plane_id, &num_formats);
-			num_formats = ARRAY_SIZE(icl_hdr_planar_formats);
+	else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
-		} else if (INTEL_GEN(dev_priv) >= 11) {
+		formats = glk_get_plane_formats(dev_priv, pipe,
-			formats = icl_planar_formats;
+						plane_id, &num_formats);
-			num_formats = ARRAY_SIZE(icl_planar_formats);
+	else
-		} else if (INTEL_GEN(dev_priv) == 10 || IS_GEMINILAKE(dev_priv)) {
+		formats = skl_get_plane_formats(dev_priv, pipe,
-			formats = glk_planar_formats;
+						plane_id, &num_formats);
-			num_formats = ARRAY_SIZE(glk_planar_formats);
-		} else {
-			formats = skl_planar_formats;
-			num_formats = ARRAY_SIZE(skl_planar_formats);
-		}
-	} else if (icl_is_hdr_plane(dev_priv, plane_id)) {
-		formats = icl_hdr_plane_formats;
-		num_formats = ARRAY_SIZE(icl_hdr_plane_formats);
-	} else if (INTEL_GEN(dev_priv) >= 11) {
-		formats = icl_plane_formats;
-		num_formats = ARRAY_SIZE(icl_plane_formats);
-	} else {
-		formats = skl_plane_formats;
-		num_formats = ARRAY_SIZE(skl_plane_formats);
-	}
 	plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
 	if (plane->has_ccs)

drivers/gpu/drm/i915/display/intel_tc.c+537−0

@@ -0,0 +1,537 @@
	1	// SPDX-License-Identifier: MIT
	2	/*
	3	* Copyright © 2019 Intel Corporation
	4	*/
	5
	6	#include "i915_drv.h"
	7	#include "intel_display.h"
	8	#include "intel_dp_mst.h"
	9	#include "intel_tc.h"
	10
	11	static const char *tc_port_mode_name(enum tc_port_mode mode)
	12	{
	13	static const char * const names[] = {
	14	[TC_PORT_TBT_ALT] = "tbt-alt",
	15	[TC_PORT_DP_ALT] = "dp-alt",
	16	[TC_PORT_LEGACY] = "legacy",
	17	};
	18
	19	if (WARN_ON(mode >= ARRAY_SIZE(names)))
	20	mode = TC_PORT_TBT_ALT;
	21
	22	return names[mode];
	23	}
	24
	25	static bool has_modular_fia(struct drm_i915_private *i915)
	26	{
	27	if (!INTEL_INFO(i915)->display.has_modular_fia)
	28	return false;
	29
	30	return intel_uncore_read(&i915->uncore,
	31	PORT_TX_DFLEXDPSP(FIA1)) & MODULAR_FIA_MASK;
	32	}
	33
	34	static enum phy_fia tc_port_to_fia(struct drm_i915_private *i915,
	35	enum tc_port tc_port)
	36	{
	37	if (!has_modular_fia(i915))
	38	return FIA1;
	39
	40	/*
	41	* Each Modular FIA instance houses 2 TC ports. In SOC that has more
	42	* than two TC ports, there are multiple instances of Modular FIA.
	43	*/
	44	return tc_port / 2;
	45	}
	46
	47	u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
	48	{
	49	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
	50	enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
	51	struct intel_uncore *uncore = &i915->uncore;
	52	u32 lane_mask;
	53
	54	lane_mask = intel_uncore_read(uncore,
	55	PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
	56
	57	WARN_ON(lane_mask == 0xffffffff);
	58
	59	return (lane_mask & DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
	60	DP_LANE_ASSIGNMENT_SHIFT(tc_port);
	61	}
	62
	63	int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
	64	{
	65	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
	66	intel_wakeref_t wakeref;
	67	u32 lane_mask;
	68
	69	if (dig_port->tc_mode != TC_PORT_DP_ALT)
	70	return 4;
	71
	72	lane_mask = 0;
	73	with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
	74	lane_mask = intel_tc_port_get_lane_mask(dig_port);
	75
	76	switch (lane_mask) {
	77	default:
	78	MISSING_CASE(lane_mask);
	79	/* fall-through */
	80	case 0x1:
	81	case 0x2:
	82	case 0x4:
	83	case 0x8:
	84	return 1;
	85	case 0x3:
	86	case 0xc:
	87	return 2;
	88	case 0xf:
	89	return 4;
	90	}
	91	}
	92
	93	void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
	94	int required_lanes)
	95	{
	96	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
	97	enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
	98	bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
	99	struct intel_uncore *uncore = &i915->uncore;
	100	u32 val;
	101
	102	WARN_ON(lane_reversal && dig_port->tc_mode != TC_PORT_LEGACY);
	103
	104	val = intel_uncore_read(uncore,
	105	PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia));
	106	val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
	107
	108	switch (required_lanes) {
	109	case 1:
	110	val \|= lane_reversal ? DFLEXDPMLE1_DPMLETC_ML3(tc_port) :
	111	DFLEXDPMLE1_DPMLETC_ML0(tc_port);
	112	break;
	113	case 2:
	114	val \|= lane_reversal ? DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) :
	115	DFLEXDPMLE1_DPMLETC_ML1_0(tc_port);
	116	break;
	117	case 4:
	118	val \|= DFLEXDPMLE1_DPMLETC_ML3_0(tc_port);
	119	break;
	120	default:
	121	MISSING_CASE(required_lanes);
	122	}
	123
	124	intel_uncore_write(uncore,
	125	PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia), val);
	126	}
	127
	128	static void tc_port_fixup_legacy_flag(struct intel_digital_port *dig_port,
	129	u32 live_status_mask)
	130	{
	131	u32 valid_hpd_mask;
	132
	133	if (dig_port->tc_legacy_port)
	134	valid_hpd_mask = BIT(TC_PORT_LEGACY);
	135	else
	136	valid_hpd_mask = BIT(TC_PORT_DP_ALT) \|
	137	BIT(TC_PORT_TBT_ALT);
	138
	139	if (!(live_status_mask & ~valid_hpd_mask))
	140	return;
	141
	142	/* If live status mismatches the VBT flag, trust the live status. */
	143	DRM_ERROR("Port %s: live status %08x mismatches the legacy port flag, fix flag\n",
	144	dig_port->tc_port_name, live_status_mask);
	145
	146	dig_port->tc_legacy_port = !dig_port->tc_legacy_port;
	147	}
	148
	149	static u32 tc_port_live_status_mask(struct intel_digital_port *dig_port)
	150	{
	151	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
	152	enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
	153	struct intel_uncore *uncore = &i915->uncore;
	154	u32 mask = 0;
	155	u32 val;
	156
	157	val = intel_uncore_read(uncore,
	158	PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
	159
	160	if (val == 0xffffffff) {
	161	DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, nothing connected\n",
	162	dig_port->tc_port_name);
	163	return mask;
	164	}
	165
	166	if (val & TC_LIVE_STATE_TBT(tc_port))
	167	mask \|= BIT(TC_PORT_TBT_ALT);
	168	if (val & TC_LIVE_STATE_TC(tc_port))
	169	mask \|= BIT(TC_PORT_DP_ALT);
	170
	171	if (intel_uncore_read(uncore, SDEISR) & SDE_TC_HOTPLUG_ICP(tc_port))
	172	mask \|= BIT(TC_PORT_LEGACY);
	173
	174	/* The sink can be connected only in a single mode. */
	175	if (!WARN_ON(hweight32(mask) > 1))
	176	tc_port_fixup_legacy_flag(dig_port, mask);
	177
	178	return mask;
	179	}
	180
	181	static bool icl_tc_phy_status_complete(struct intel_digital_port *dig_port)
	182	{
	183	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
	184	enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
	185	struct intel_uncore *uncore = &i915->uncore;
	186	u32 val;
	187
	188	val = intel_uncore_read(uncore,
	189	PORT_TX_DFLEXDPPMS(dig_port->tc_phy_fia));
	190	if (val == 0xffffffff) {
	191	DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, assuming not complete\n",
	192	dig_port->tc_port_name);
	193	return false;
	194	}
	195
	196	return val & DP_PHY_MODE_STATUS_COMPLETED(tc_port);
	197	}
	198
	199	static bool icl_tc_phy_set_safe_mode(struct intel_digital_port *dig_port,
	200	bool enable)
	201	{
	202	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
	203	enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
	204	struct intel_uncore *uncore = &i915->uncore;
	205	u32 val;
	206
	207	val = intel_uncore_read(uncore,
	208	PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia));
	209	if (val == 0xffffffff) {
	210	DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, can't set safe-mode to %s\n",
	211	dig_port->tc_port_name,
	212	enableddisabled(enable));
	213
	214	return false;
	215	}
	216
	217	val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
	218	if (!enable)
	219	val \|= DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
	220
	221	intel_uncore_write(uncore,
	222	PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia), val);
	223
	224	if (enable && wait_for(!icl_tc_phy_status_complete(dig_port), 10))
	225	DRM_DEBUG_KMS("Port %s: PHY complete clear timed out\n",
	226	dig_port->tc_port_name);
	227
	228	return true;
	229	}
	230
	231	static bool icl_tc_phy_is_in_safe_mode(struct intel_digital_port *dig_port)
	232	{
	233	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
	234	enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
	235	struct intel_uncore *uncore = &i915->uncore;
	236	u32 val;
	237
	238	val = intel_uncore_read(uncore,
	239	PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia));
	240	if (val == 0xffffffff) {
	241	DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, assume safe mode\n",
	242	dig_port->tc_port_name);
	243	return true;
	244	}
	245
	246	return !(val & DP_PHY_MODE_STATUS_NOT_SAFE(tc_port));
	247	}
	248
	249	/*
	250	* This function implements the first part of the Connect Flow described by our
	251	* specification, Gen11 TypeC Programming chapter. The rest of the flow (reading
	252	* lanes, EDID, etc) is done as needed in the typical places.
	253	*
	254	* Unlike the other ports, type-C ports are not available to use as soon as we
	255	* get a hotplug. The type-C PHYs can be shared between multiple controllers:
	256	* display, USB, etc. As a result, handshaking through FIA is required around
	257	* connect and disconnect to cleanly transfer ownership with the controller and
	258	* set the type-C power state.
	259	*/
	260	static void icl_tc_phy_connect(struct intel_digital_port *dig_port,
	261	int required_lanes)
	262	{
	263	int max_lanes;
	264
	265	if (!icl_tc_phy_status_complete(dig_port)) {
	266	DRM_DEBUG_KMS("Port %s: PHY not ready\n",
	267	dig_port->tc_port_name);
	268	goto out_set_tbt_alt_mode;
	269	}
	270
	271	if (!icl_tc_phy_set_safe_mode(dig_port, false) &&
	272	!WARN_ON(dig_port->tc_legacy_port))
	273	goto out_set_tbt_alt_mode;
	274
	275	max_lanes = intel_tc_port_fia_max_lane_count(dig_port);
	276	if (dig_port->tc_legacy_port) {
	277	WARN_ON(max_lanes != 4);
	278	dig_port->tc_mode = TC_PORT_LEGACY;
	279
	280	return;
	281	}
	282
	283	/*
	284	* Now we have to re-check the live state, in case the port recently
	285	* became disconnected. Not necessary for legacy mode.
	286	*/
	287	if (!(tc_port_live_status_mask(dig_port) & BIT(TC_PORT_DP_ALT))) {
	288	DRM_DEBUG_KMS("Port %s: PHY sudden disconnect\n",
	289	dig_port->tc_port_name);
	290	goto out_set_safe_mode;
	291	}
	292
	293	if (max_lanes < required_lanes) {
	294	DRM_DEBUG_KMS("Port %s: PHY max lanes %d < required lanes %d\n",
	295	dig_port->tc_port_name,
	296	max_lanes, required_lanes);
	297	goto out_set_safe_mode;
	298	}
	299
	300	dig_port->tc_mode = TC_PORT_DP_ALT;
	301
	302	return;
	303
	304	out_set_safe_mode:
	305	icl_tc_phy_set_safe_mode(dig_port, true);
	306	out_set_tbt_alt_mode:
	307	dig_port->tc_mode = TC_PORT_TBT_ALT;
	308	}
	309
	310	/*
	311	* See the comment at the connect function. This implements the Disconnect
	312	* Flow.
	313	*/
	314	static void icl_tc_phy_disconnect(struct intel_digital_port *dig_port)
	315	{
	316	switch (dig_port->tc_mode) {
	317	case TC_PORT_LEGACY:
	318	/* Nothing to do, we never disconnect from legacy mode */
	319	break;
	320	case TC_PORT_DP_ALT:
	321	icl_tc_phy_set_safe_mode(dig_port, true);
	322	dig_port->tc_mode = TC_PORT_TBT_ALT;
	323	break;
	324	case TC_PORT_TBT_ALT:
	325	/* Nothing to do, we stay in TBT-alt mode */
	326	break;
	327	default:
	328	MISSING_CASE(dig_port->tc_mode);
	329	}
	330	}
	331
	332	static bool icl_tc_phy_is_connected(struct intel_digital_port *dig_port)
	333	{
	334	if (!icl_tc_phy_status_complete(dig_port)) {
	335	DRM_DEBUG_KMS("Port %s: PHY status not complete\n",
	336	dig_port->tc_port_name);
	337	return dig_port->tc_mode == TC_PORT_TBT_ALT;
	338	}
	339
	340	if (icl_tc_phy_is_in_safe_mode(dig_port)) {
	341	DRM_DEBUG_KMS("Port %s: PHY still in safe mode\n",
	342	dig_port->tc_port_name);
	343
	344	return false;
	345	}
	346
	347	return dig_port->tc_mode == TC_PORT_DP_ALT \|\|
	348	dig_port->tc_mode == TC_PORT_LEGACY;
	349	}
	350
	351	static enum tc_port_mode
	352	intel_tc_port_get_current_mode(struct intel_digital_port *dig_port)
	353	{
	354	u32 live_status_mask = tc_port_live_status_mask(dig_port);
	355	bool in_safe_mode = icl_tc_phy_is_in_safe_mode(dig_port);
	356	enum tc_port_mode mode;
	357
	358	if (in_safe_mode \|\| WARN_ON(!icl_tc_phy_status_complete(dig_port)))
	359	return TC_PORT_TBT_ALT;
	360
	361	mode = dig_port->tc_legacy_port ? TC_PORT_LEGACY : TC_PORT_DP_ALT;
	362	if (live_status_mask) {
	363	enum tc_port_mode live_mode = fls(live_status_mask) - 1;
	364
	365	if (!WARN_ON(live_mode == TC_PORT_TBT_ALT))
	366	mode = live_mode;
	367	}
	368
	369	return mode;
	370	}
	371
	372	static enum tc_port_mode
	373	intel_tc_port_get_target_mode(struct intel_digital_port *dig_port)
	374	{
	375	u32 live_status_mask = tc_port_live_status_mask(dig_port);
	376
	377	if (live_status_mask)
	378	return fls(live_status_mask) - 1;
	379
	380	return icl_tc_phy_status_complete(dig_port) &&
	381	dig_port->tc_legacy_port ? TC_PORT_LEGACY :
	382	TC_PORT_TBT_ALT;
	383	}
	384
	385	static void intel_tc_port_reset_mode(struct intel_digital_port *dig_port,
	386	int required_lanes)
	387	{
	388	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
	389	enum tc_port_mode old_tc_mode = dig_port->tc_mode;
	390
	391	intel_display_power_flush_work(i915);
	392	WARN_ON(intel_display_power_is_enabled(i915,
	393	intel_aux_power_domain(dig_port)));
	394
	395	icl_tc_phy_disconnect(dig_port);
	396	icl_tc_phy_connect(dig_port, required_lanes);
	397
	398	DRM_DEBUG_KMS("Port %s: TC port mode reset (%s -> %s)\n",
	399	dig_port->tc_port_name,
	400	tc_port_mode_name(old_tc_mode),
	401	tc_port_mode_name(dig_port->tc_mode));
	402	}
	403
	404	static void
	405	intel_tc_port_link_init_refcount(struct intel_digital_port *dig_port,
	406	int refcount)
	407	{
	408	WARN_ON(dig_port->tc_link_refcount);
	409	dig_port->tc_link_refcount = refcount;
	410	}
	411
	412	void intel_tc_port_sanitize(struct intel_digital_port *dig_port)
	413	{
	414	struct intel_encoder *encoder = &dig_port->base;
	415	int active_links = 0;
	416
	417	mutex_lock(&dig_port->tc_lock);
	418
	419	dig_port->tc_mode = intel_tc_port_get_current_mode(dig_port);
	420	if (dig_port->dp.is_mst)
	421	active_links = intel_dp_mst_encoder_active_links(dig_port);
	422	else if (encoder->base.crtc)
	423	active_links = to_intel_crtc(encoder->base.crtc)->active;
	424
	425	if (active_links) {
	426	if (!icl_tc_phy_is_connected(dig_port))
	427	DRM_DEBUG_KMS("Port %s: PHY disconnected with %d active link(s)\n",
	428	dig_port->tc_port_name, active_links);
	429	intel_tc_port_link_init_refcount(dig_port, active_links);
	430
	431	goto out;
	432	}
	433
	434	if (dig_port->tc_legacy_port)
	435	icl_tc_phy_connect(dig_port, 1);
	436
	437	out:
	438	DRM_DEBUG_KMS("Port %s: sanitize mode (%s)\n",
	439	dig_port->tc_port_name,
	440	tc_port_mode_name(dig_port->tc_mode));
	441
	442	mutex_unlock(&dig_port->tc_lock);
	443	}
	444
	445	static bool intel_tc_port_needs_reset(struct intel_digital_port *dig_port)
	446	{
	447	return intel_tc_port_get_target_mode(dig_port) != dig_port->tc_mode;
	448	}
	449
	450	/*
	451	* The type-C ports are different because even when they are connected, they may
	452	* not be available/usable by the graphics driver: see the comment on
	453	* icl_tc_phy_connect(). So in our driver instead of adding the additional
	454	* concept of "usable" and make everything check for "connected and usable" we
	455	* define a port as "connected" when it is not only connected, but also when it
	456	* is usable by the rest of the driver. That maintains the old assumption that
	457	* connected ports are usable, and avoids exposing to the users objects they
	458	* can't really use.
	459	*/
	460	bool intel_tc_port_connected(struct intel_digital_port *dig_port)
	461	{
	462	bool is_connected;
	463
	464	intel_tc_port_lock(dig_port);
	465	is_connected = tc_port_live_status_mask(dig_port) &
	466	BIT(dig_port->tc_mode);
	467	intel_tc_port_unlock(dig_port);
	468
	469	return is_connected;
	470	}
	471
	472	static void __intel_tc_port_lock(struct intel_digital_port *dig_port,
	473	int required_lanes)
	474	{
	475	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
	476	intel_wakeref_t wakeref;
	477
	478	wakeref = intel_display_power_get(i915, POWER_DOMAIN_DISPLAY_CORE);
	479
	480	mutex_lock(&dig_port->tc_lock);
	481
	482	if (!dig_port->tc_link_refcount &&
	483	intel_tc_port_needs_reset(dig_port))
	484	intel_tc_port_reset_mode(dig_port, required_lanes);
	485
	486	WARN_ON(dig_port->tc_lock_wakeref);
	487	dig_port->tc_lock_wakeref = wakeref;
	488	}
	489
	490	void intel_tc_port_lock(struct intel_digital_port *dig_port)
	491	{
	492	__intel_tc_port_lock(dig_port, 1);
	493	}
	494
	495	void intel_tc_port_unlock(struct intel_digital_port *dig_port)
	496	{
	497	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
	498	intel_wakeref_t wakeref = fetch_and_zero(&dig_port->tc_lock_wakeref);
	499
	500	mutex_unlock(&dig_port->tc_lock);
	501
	502	intel_display_power_put_async(i915, POWER_DOMAIN_DISPLAY_CORE,
	503	wakeref);
	504	}
	505
	506	void intel_tc_port_get_link(struct intel_digital_port *dig_port,
	507	int required_lanes)
	508	{
	509	__intel_tc_port_lock(dig_port, required_lanes);
	510	dig_port->tc_link_refcount++;
	511	intel_tc_port_unlock(dig_port);
	512	}
	513
	514	void intel_tc_port_put_link(struct intel_digital_port *dig_port)
	515	{
	516	mutex_lock(&dig_port->tc_lock);
	517	dig_port->tc_link_refcount--;
	518	mutex_unlock(&dig_port->tc_lock);
	519	}
	520
	521	void intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy)
	522	{
	523	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
	524	enum port port = dig_port->base.port;
	525	enum tc_port tc_port = intel_port_to_tc(i915, port);
	526
	527	if (WARN_ON(tc_port == PORT_TC_NONE))
	528	return;
	529
	530	snprintf(dig_port->tc_port_name, sizeof(dig_port->tc_port_name),
	531	"%c/TC#%d", port_name(port), tc_port + 1);
	532
	533	mutex_init(&dig_port->tc_lock);
	534	dig_port->tc_legacy_port = is_legacy;
	535	dig_port->tc_link_refcount = 0;
	536	dig_port->tc_phy_fia = tc_port_to_fia(i915, tc_port);
	537	}

drivers/gpu/drm/i915/display/intel_tc.h+35−0

@@ -0,0 +1,35 @@
	1	/* SPDX-License-Identifier: MIT */
	2	/*
	3	* Copyright © 2019 Intel Corporation
	4	*/
	5
	6	#ifndef __INTEL_TC_H__
	7	#define __INTEL_TC_H__
	8
	9	#include <linux/mutex.h>
	10	#include <linux/types.h>
	11
	12	#include "intel_drv.h"
	13
	14	bool intel_tc_port_connected(struct intel_digital_port *dig_port);
	15	u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port);
	16	int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port);
	17	void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
	18	int required_lanes);
	19
	20	void intel_tc_port_sanitize(struct intel_digital_port *dig_port);
	21	void intel_tc_port_lock(struct intel_digital_port *dig_port);
	22	void intel_tc_port_unlock(struct intel_digital_port *dig_port);
	23	void intel_tc_port_get_link(struct intel_digital_port *dig_port,
	24	int required_lanes);
	25	void intel_tc_port_put_link(struct intel_digital_port *dig_port);
	26
	27	static inline int intel_tc_port_ref_held(struct intel_digital_port *dig_port)
	28	{
	29	return mutex_is_locked(&dig_port->tc_lock) \|\|
	30	dig_port->tc_link_refcount;
	31	}
	32
	33	void intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy);
	34
	35	#endif /* __INTEL_TC_H__ */

drivers/gpu/drm/i915/display/intel_vbt_defs.h+3−0

 	DDC_BUS_DDI_F,
 	ICL_DDC_BUS_DDI_A = 0x1,
 	ICL_DDC_BUS_DDI_B,
+	TGL_DDC_BUS_DDI_C,
 	ICL_DDC_BUS_PORT_1 = 0x4,
 	ICL_DDC_BUS_PORT_2,
 	ICL_DDC_BUS_PORT_3,
 	ICL_DDC_BUS_PORT_4,
+	TGL_DDC_BUS_PORT_5,
+	TGL_DDC_BUS_PORT_6,
 	MCC_DDC_BUS_DDI_A = 0x1,
 	MCC_DDC_BUS_DDI_B,
 	MCC_DDC_BUS_DDI_C = 0x4,

drivers/gpu/drm/i915/display/intel_vdsc.c+10−4

 enum intel_display_power_domain
 intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
 {
+	struct drm_i915_private *i915 = to_i915(crtc_state->base.crtc->dev);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 	/*
-	 * On ICL VDSC/joining for eDP transcoder uses a separate power well PW2
+	 * On ICL VDSC/joining for eDP transcoder uses a separate power well,
-	 * This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power domain.
+	 * PW2. This requires POWER_DOMAIN_TRANSCODER_VDSC_PW2 power domain.
 	 * For any other transcoder, VDSC/joining uses the power well associated
 	 * with the pipe/transcoder in use. Hence another reference on the
 	 * transcoder power domain will suffice.
+	 *
+	 * On TGL we have the same mapping, but for transcoder A (the special
+	 * TRANSCODER_EDP is gone).
 	 */
-	if (cpu_transcoder == TRANSCODER_EDP)
+	if (INTEL_GEN(i915) >= 12 && cpu_transcoder == TRANSCODER_A)
-		return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
+		return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
+	else if (cpu_transcoder == TRANSCODER_EDP)
+		return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
 	else
 		return POWER_DOMAIN_TRANSCODER(cpu_transcoder);
 }

drivers/gpu/drm/i915/display/vlv_dsi.c+2−2

@@ -1644,7 +1644,7 @@ vlv_dsi_get_panel_orientation(struct intel_connector *connector) · 1643 unmodified lines
1644	return intel_dsi_get_panel_orientation(connector);	1644	return intel_dsi_get_panel_orientation(connector);
1645	}	1645	}
1646		1646
1647	static void intel_dsi_add_properties(struct intel_connector *connector)	1647	static void vlv_dsi_add_properties(struct intel_connector *connector)
1648	{	1648	{
1649	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);	1649	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1650		1650
@@ -1983,7 +1983,7 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv) · 332 unmodified lines
1983	intel_panel_init(&intel_connector->panel, fixed_mode, NULL);	1983	intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
1984	intel_panel_setup_backlight(connector, INVALID_PIPE);	1984	intel_panel_setup_backlight(connector, INVALID_PIPE);
1985		1985
1986	intel_dsi_add_properties(intel_connector);	1986	vlv_dsi_add_properties(intel_connector);
1987		1987
1988	return;	1988	return;
1989		1989

drivers/gpu/drm/i915/gem/Makefile+5−1

@@ -1 +1,5 @@
1	include $(src)/Makefile.header-test # Extra header tests	1	# For building individual subdir files on the command line
		2	subdir-ccflags-y += -I$(srctree)/$(src)/..
		3
		4	# Extra header tests
		5	header-test-pattern-$(CONFIG_DRM_I915_WERROR) := *.h

drivers/gpu/drm/i915/gem/Makefile.header-test+0−16

@@ -1,16 +0,0 @@
1	# SPDX-License-Identifier: MIT
2	# Copyright © 2019 Intel Corporation
3
4	# Test the headers are compilable as standalone units
5	header_test := $(notdir $(wildcard $(src)/*.h))
6
7	quiet_cmd_header_test = HDRTEST $@
8	cmd_header_test = echo "\#include \"$(<F)\"" > $@
9
10	header_test_%.c: %.h
11	$(call cmd,header_test)
12
13	extra-$(CONFIG_DRM_I915_WERROR) += \
14	$(foreach h,$(header_test),$(patsubst %.h,header_test_%.o,$(h)))
15
16	clean-files += $(foreach h,$(header_test),$(patsubst %.h,header_test_%.c,$(h)))

drivers/gpu/drm/i915/gem/i915_gem_client_blt.c+10−11

 	vma->ops = &proxy_vma_ops;
 	sleeve->vma = vma;
-	sleeve->obj = i915_gem_object_get(obj);
 	sleeve->pages = pages;
 	sleeve->page_sizes = *page_sizes;
 static void destroy_sleeve(struct i915_sleeve *sleeve)
 {
-	i915_gem_object_put(sleeve->obj);
 	kfree(sleeve);
 }
 {
 	struct clear_pages_work *w = container_of(work, typeof(*w), work);
 	struct drm_i915_private *i915 = w->ce->gem_context->i915;
-	struct drm_i915_gem_object *obj = w->sleeve->obj;
+	struct drm_i915_gem_object *obj = w->sleeve->vma->obj;
 	struct i915_vma *vma = w->sleeve->vma;
 	struct i915_request *rq;
 	int err = w->dma.error;
 		goto out_signal;
 	if (obj->cache_dirty) {
-		obj->write_domain = 0;
 		if (i915_gem_object_has_struct_page(obj))
 			drm_clflush_sg(w->sleeve->pages);
 		obj->cache_dirty = false;
 	}
+	obj->read_domains = I915_GEM_GPU_DOMAINS;
+	obj->write_domain = 0;
 	/* XXX: we need to kill this */
 	mutex_lock(&i915->drm.struct_mutex);
 			goto out_request;
 	}
-	/* XXX: more feverish nightmares await */
+	/*
-	i915_vma_lock(vma);
+	 * w->dma is already exported via (vma|obj)->resv we need only
-	err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
+	 * keep track of the GPU activity within this vma/request, and
-	i915_vma_unlock(vma);
+	 * propagate the signal from the request to w->dma.
+	 */
+	err = i915_active_ref(&vma->active, rq->fence.context, rq);
 	if (err)
 		goto out_request;
 				     u32 value)
 {
 	struct drm_i915_private *i915 = to_i915(obj->base.dev);
-	struct i915_gem_context *ctx = ce->gem_context;
-	struct i915_address_space *vm = ctx->vm ?: &i915->ggtt.vm;
 	struct clear_pages_work *work;
 	struct i915_sleeve *sleeve;
 	int err;
-	sleeve = create_sleeve(vm, obj, pages, page_sizes);
+	sleeve = create_sleeve(ce->vm, obj, pages, page_sizes);
 	if (IS_ERR(sleeve))
 		return PTR_ERR(sleeve);

drivers/gpu/drm/i915/gem/i915_gem_context.c+30−53

 	mutex_destroy(&ctx->engines_mutex);
 	if (ctx->timeline)
-		i915_timeline_put(ctx->timeline);
+		intel_timeline_put(ctx->timeline);
 	kfree(ctx->name);
 	put_pid(ctx->pid);
 	i915_gem_context_set_recoverable(ctx);
 	ctx->ring_size = 4 * PAGE_SIZE;
-	ctx->desc_template =
+	ctx->desc_template = default_desc_template(i915, NULL);
-		default_desc_template(i915, &i915->mm.aliasing_ppgtt->vm);
 	for (i = 0; i < ARRAY_SIZE(ctx->hang_timestamp); i++)
 		ctx->hang_timestamp[i] = jiffies - CONTEXT_FAST_HANG_JIFFIES;
 __set_ppgtt(struct i915_gem_context *ctx, struct i915_address_space *vm)
 {
 	struct i915_address_space *old = ctx->vm;
+	struct i915_gem_engines_iter it;
+	struct intel_context *ce;
 	ctx->vm = i915_vm_get(vm);
 	ctx->desc_template = default_desc_template(ctx->i915, vm);
+	for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
+		i915_vm_put(ce->vm);
+		ce->vm = i915_vm_get(vm);
+	}
+	i915_gem_context_unlock_engines(ctx);
 	return old;
 }
 	}
 	if (flags & I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE) {
-		struct i915_timeline *timeline;
+		struct intel_timeline *timeline;
-		timeline = i915_timeline_create(dev_priv, NULL);
+		timeline = intel_timeline_create(&dev_priv->gt, NULL);
 		if (IS_ERR(timeline)) {
 			context_close(ctx);
 			return ERR_CAST(timeline);
 	init_llist_head(&i915->contexts.free_list);
 }
-static bool needs_preempt_context(struct drm_i915_private *i915)
-{
-	return HAS_EXECLISTS(i915);
-}
 int i915_gem_contexts_init(struct drm_i915_private *dev_priv)
 {
 	struct i915_gem_context *ctx;
 	/* Reassure ourselves we are only called once */
 	GEM_BUG_ON(dev_priv->kernel_context);
-	GEM_BUG_ON(dev_priv->preempt_context);
-	intel_engine_init_ctx_wa(dev_priv->engine[RCS0]);
 	init_contexts(dev_priv);
 	/* lowest priority; idle task */
 	GEM_BUG_ON(!atomic_read(&ctx->hw_id_pin_count));
 	dev_priv->kernel_context = ctx;
-	/* highest priority; preempting task */
-	if (needs_preempt_context(dev_priv)) {
-		ctx = i915_gem_context_create_kernel(dev_priv, INT_MAX);
-		if (!IS_ERR(ctx))
-			dev_priv->preempt_context = ctx;
-		else
-			DRM_ERROR("Failed to create preempt context; disabling preemption\n");
-	}
 	DRM_DEBUG_DRIVER("%s context support initialized\n",
 			 DRIVER_CAPS(dev_priv)->has_logical_contexts ?
 			 "logical" : "fake");
 {
 	lockdep_assert_held(&i915->drm.struct_mutex);
-	if (i915->preempt_context)
-		destroy_kernel_context(&i915->preempt_context);
 	destroy_kernel_context(&i915->kernel_context);
 	/* Must free all deferred contexts (via flush_workqueue) first */
 	if (!cb)
 		return -ENOMEM;
-	i915_active_init(i915, &cb->base, cb_retire);
+	i915_active_init(i915, &cb->base, NULL, cb_retire);
-	i915_active_acquire(&cb->base);
+	err = i915_active_acquire(&cb->base);
+	if (err) {
+		kfree(cb);
+		return err;
+	}
 	for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
 		struct i915_request *rq;
 static int emit_ppgtt_update(struct i915_request *rq, void *data)
 {
-	struct i915_address_space *vm = rq->gem_context->vm;
+	struct i915_address_space *vm = rq->hw_context->vm;
 	struct intel_engine_cs *engine = rq->engine;
 	u32 base = engine->mmio_base;
 	u32 *cs;
 				   set_ppgtt_barrier,
 				   old);
 	if (err) {
-		ctx->vm = old;
+		i915_vm_put(__set_ppgtt(ctx, old));
-		ctx->desc_template = default_desc_template(ctx->i915, old);
+		i915_vm_put(old);
-		i915_vm_put(vm);
 	}
 unlock:
 	if (IS_ERR(rq))
 		return PTR_ERR(rq);
-	/* Queue this switch after all other activity by this context. */
+	/* Serialise with the remote context */
-	ret = i915_active_request_set(&ce->ring->timeline->last_request, rq);
+	ret = intel_context_prepare_remote_request(ce, rq);
-	if (ret)
+	if (ret == 0)
-		goto out_add;
+		ret = gen8_emit_rpcs_config(rq, ce, sseu);
-	/*
-	 * Guarantee context image and the timeline remains pinned until the
-	 * modifying request is retired by setting the ce activity tracker.
-	 *
-	 * But we only need to take one pin on the account of it. Or in other
-	 * words transfer the pinned ce object to tracked active request.
-	 */
-	GEM_BUG_ON(i915_active_is_idle(&ce->active));
-	ret = i915_active_ref(&ce->active, rq->fence.context, rq);
-	if (ret)
-		goto out_add;
-	ret = gen8_emit_rpcs_config(rq, ce, sseu);
-out_add:
 	i915_request_add(rq);
 	return ret;
 }
 		GEM_BUG_ON(src->timeline == dst->timeline);
 		if (dst->timeline)
-			i915_timeline_put(dst->timeline);
+			intel_timeline_put(dst->timeline);
-		dst->timeline = i915_timeline_get(src->timeline);
+		dst->timeline = intel_timeline_get(src->timeline);
 	}
 	return 0;
 	if (args->flags & I915_CONTEXT_CREATE_FLAGS_UNKNOWN)
 		return -EINVAL;
-	ret = i915_terminally_wedged(i915);
+	ret = intel_gt_terminally_wedged(&i915->gt);
 	if (ret)
 		return ret;
 		args->size = 0;
 		if (ctx->vm)
 			args->value = ctx->vm->total;
-		else if (to_i915(dev)->mm.aliasing_ppgtt)
+		else if (to_i915(dev)->ggtt.alias)
-			args->value = to_i915(dev)->mm.aliasing_ppgtt->vm.total;
+			args->value = to_i915(dev)->ggtt.alias->vm.total;
 		else
 			args->value = to_i915(dev)->ggtt.vm.total;
 		break;

drivers/gpu/drm/i915/gem/i915_gem_context.h+0−6

 	mutex_unlock(&ctx->engines_mutex);
 }
-static inline struct intel_context *
-i915_gem_context_lookup_engine(struct i915_gem_context *ctx, unsigned int idx)
-{
-	return i915_gem_context_engines(ctx)->engines[idx];
-}
 static inline struct intel_context *
 i915_gem_context_get_engine(struct i915_gem_context *ctx, unsigned int idx)
 {

drivers/gpu/drm/i915/gem/i915_gem_context_types.h+2−2

@@ -26,7 +26,7 @@ struct pid; · 25 unmodified lines
26	struct drm_i915_private;	26	struct drm_i915_private;
27	struct drm_i915_file_private;	27	struct drm_i915_file_private;
28	struct i915_address_space;	28	struct i915_address_space;
29	struct i915_timeline;	29	struct intel_timeline;
30	struct intel_ring;	30	struct intel_ring;
31		31
32	struct i915_gem_engines {	32	struct i915_gem_engines {
@@ -77,7 +77,7 @@ struct i915_gem_context { · 44 unmodified lines
77	struct i915_gem_engines __rcu *engines;	77	struct i915_gem_engines __rcu *engines;
78	struct mutex engines_mutex; /* guards writes to engines */	78	struct mutex engines_mutex; /* guards writes to engines */
79		79
80	struct i915_timeline *timeline;	80	struct intel_timeline *timeline;
81		81
82	/**	82	/**
83	* @vm: unique address space (GTT)	83	* @vm: unique address space (GTT)

drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c+9−13

 #include "gem/i915_gem_ioctls.h"
 #include "gt/intel_context.h"
+#include "gt/intel_gt.h"
 #include "gt/intel_gt_pm.h"
 #include "i915_gem_ioctls.h"
 	struct intel_engine_cs *engine; /** engine to queue the request to */
 	struct intel_context *context; /* logical state for the request */
 	struct i915_gem_context *gem_context; /** caller's context */
-	struct i915_address_space *vm; /** GTT and vma for the request */
 	struct i915_request *request; /** our request to build */
 	struct i915_vma *batch; /** identity of the batch obj/vma */
 		case 1:
 			/* Too fragmented, unbind everything and retry */
-			err = i915_gem_evict_vm(eb->vm);
+			err = i915_gem_evict_vm(eb->context->vm);
 			if (err)
 				return err;
 			break;
 		return -ENOENT;
 	eb->gem_context = ctx;
-	if (ctx->vm) {
+	if (ctx->vm)
-		eb->vm = ctx->vm;
 		eb->invalid_flags |= EXEC_OBJECT_NEEDS_GTT;
-	} else {
-		eb->vm = &eb->i915->ggtt.vm;
-	}
 	eb->context_flags = 0;
 	if (test_bit(UCONTEXT_NO_ZEROMAP, &ctx->user_flags))
 			goto err_vma;
 		}
-		vma = i915_vma_instance(obj, eb->vm, NULL);
+		vma = i915_vma_instance(obj, eb->context->vm, NULL);
 		if (IS_ERR(vma)) {
 			err = PTR_ERR(vma);
 			goto err_obj;
 	__i915_gem_object_flush_map(cache->rq->batch->obj, 0, cache->rq_size);
 	i915_gem_object_unpin_map(cache->rq->batch->obj);
-	i915_gem_chipset_flush(cache->rq->i915);
+	intel_gt_chipset_flush(cache->rq->engine->gt);
 	i915_request_add(cache->rq);
 	cache->rq = NULL;
 	eb->exec = NULL;
 	/* Unconditionally flush any chipset caches (for streaming writes). */
-	i915_gem_chipset_flush(eb->i915);
+	intel_gt_chipset_flush(eb->engine->gt);
 	return 0;
 err_skip:
 	 * ABI: Before userspace accesses the GPU (e.g. execbuffer), report
 	 * EIO if the GPU is already wedged.
 	 */
-	err = i915_terminally_wedged(eb->i915);
+	err = intel_gt_terminally_wedged(ce->engine->gt);
 	if (err)
 		return err;
 	 * wakeref that we hold until the GPU has been idle for at least
 	 * 100ms.
 	 */
-	intel_gt_pm_get(eb.i915);
+	intel_gt_pm_get(&eb.i915->gt);
 	err = i915_mutex_lock_interruptible(dev);
 	if (err)
 err_unlock:
 	mutex_unlock(&dev->struct_mutex);
 err_rpm:
-	intel_gt_pm_put(eb.i915);
+	intel_gt_pm_put(&eb.i915->gt);
 	i915_gem_context_put(eb.gem_context);
 err_destroy:
 	eb_destroy(&eb);

drivers/gpu/drm/i915/gem/i915_gem_mman.c+5−3

 #include <linux/mman.h>
 #include <linux/sizes.h>
+#include "gt/intel_gt.h"
 #include "i915_drv.h"
 #include "i915_gem_gtt.h"
 #include "i915_gem_ioctls.h"
 	wakeref = intel_runtime_pm_get(rpm);
-	srcu = i915_reset_trylock(i915);
+	srcu = intel_gt_reset_trylock(ggtt->vm.gt);
 	if (srcu < 0) {
 		ret = srcu;
 		goto err_rpm;
 err_unlock:
 	mutex_unlock(&dev->struct_mutex);
 err_reset:
-	i915_reset_unlock(i915, srcu);
+	intel_gt_reset_unlock(ggtt->vm.gt, srcu);
 err_rpm:
 	intel_runtime_pm_put(rpm, wakeref);
 	i915_gem_object_unpin_pages(obj);
 		 * fail). But any other -EIO isn't ours (e.g. swap in failure)
 		 * and so needs to be reported.
 		 */
-		if (!i915_terminally_wedged(i915))
+		if (!intel_gt_is_wedged(ggtt->vm.gt))
 			return VM_FAULT_SIGBUS;
 		/* else, fall through */
 	case -EAGAIN:

drivers/gpu/drm/i915/gem/i915_gem_object.c+46−51

@@ -23,7 +23,7 @@ · 22 unmodified lines
23	*/	23	*/
24		24
25	#include "display/intel_frontbuffer.h"	25	#include "display/intel_frontbuffer.h"
26		26	#include "gt/intel_gt.h"
27	#include "i915_drv.h"	27	#include "i915_drv.h"
28	#include "i915_gem_clflush.h"	28	#include "i915_gem_clflush.h"
29	#include "i915_gem_context.h"	29	#include "i915_gem_context.h"
@@ -146,6 +146,19 @@ void i915_gem_close_object(struct drm_gem_object gem, struct drm_file file) · 116 unmodified lines
146	}	146	}
147	}	147	}
148		148
		149	static void __i915_gem_free_object_rcu(struct rcu_head *head)
		150	{
		151	struct drm_i915_gem_object *obj =
		152	container_of(head, typeof(*obj), rcu);
		153	struct drm_i915_private *i915 = to_i915(obj->base.dev);
		154
		155	reservation_object_fini(&obj->base._resv);
		156	i915_gem_object_free(obj);
		157
		158	GEM_BUG_ON(!atomic_read(&i915->mm.free_count));
		159	atomic_dec(&i915->mm.free_count);
		160	}
		161
149	static void __i915_gem_free_objects(struct drm_i915_private *i915,	162	static void __i915_gem_free_objects(struct drm_i915_private *i915,
150	struct llist_node *freed)	163	struct llist_node *freed)
151	{	164	{
@@ -160,7 +173,6 @@ static void __i915_gem_free_objects(struct drm_i915_private *i915, · 8 unmodified lines
160		173
161	mutex_lock(&i915->drm.struct_mutex);	174	mutex_lock(&i915->drm.struct_mutex);
162		175
163	GEM_BUG_ON(i915_gem_object_is_active(obj));
164	list_for_each_entry_safe(vma, vn, &obj->vma.list, obj_link) {	176	list_for_each_entry_safe(vma, vn, &obj->vma.list, obj_link) {
165	GEM_BUG_ON(i915_vma_is_active(vma));	177	GEM_BUG_ON(i915_vma_is_active(vma));
166	vma->flags &= ~I915_VMA_PIN_MASK;	178	vma->flags &= ~I915_VMA_PIN_MASK;
@@ -169,22 +181,6 @@ static void __i915_gem_free_objects(struct drm_i915_private *i915, · 2 unmodified lines
169	GEM_BUG_ON(!list_empty(&obj->vma.list));	181	GEM_BUG_ON(!list_empty(&obj->vma.list));
170	GEM_BUG_ON(!RB_EMPTY_ROOT(&obj->vma.tree));	182	GEM_BUG_ON(!RB_EMPTY_ROOT(&obj->vma.tree));
171		183
172	/*
173	* This serializes freeing with the shrinker. Since the free
174	* is delayed, first by RCU then by the workqueue, we want the
175	* shrinker to be able to free pages of unreferenced objects,
176	* or else we may oom whilst there are plenty of deferred
177	* freed objects.
178	*/
179	if (i915_gem_object_has_pages(obj) &&
180	i915_gem_object_is_shrinkable(obj)) {
181	unsigned long flags;
182
183	spin_lock_irqsave(&i915->mm.obj_lock, flags);
184	list_del_init(&obj->mm.link);
185	spin_unlock_irqrestore(&i915->mm.obj_lock, flags);
186	}
187
188	mutex_unlock(&i915->drm.struct_mutex);	184	mutex_unlock(&i915->drm.struct_mutex);
189		185
190	GEM_BUG_ON(atomic_read(&obj->bind_count));	186	GEM_BUG_ON(atomic_read(&obj->bind_count));
@@ -192,25 +188,21 @@ static void __i915_gem_free_objects(struct drm_i915_private *i915, · 1 unmodified line
192	GEM_BUG_ON(atomic_read(&obj->frontbuffer_bits));	188	GEM_BUG_ON(atomic_read(&obj->frontbuffer_bits));
193	GEM_BUG_ON(!list_empty(&obj->lut_list));	189	GEM_BUG_ON(!list_empty(&obj->lut_list));
194		190
195	if (obj->ops->release)
196	obj->ops->release(obj);
197
198	atomic_set(&obj->mm.pages_pin_count, 0);	191	atomic_set(&obj->mm.pages_pin_count, 0);
199	__i915_gem_object_put_pages(obj, I915_MM_NORMAL);	192	__i915_gem_object_put_pages(obj, I915_MM_NORMAL);
200	GEM_BUG_ON(i915_gem_object_has_pages(obj));	193	GEM_BUG_ON(i915_gem_object_has_pages(obj));
		194	bitmap_free(obj->bit_17);
201		195
202	if (obj->base.import_attach)	196	if (obj->base.import_attach)
203	drm_prime_gem_destroy(&obj->base, NULL);	197	drm_prime_gem_destroy(&obj->base, NULL);
204		198
205	drm_gem_object_release(&obj->base);	199	drm_gem_free_mmap_offset(&obj->base);
206		200
207	bitmap_free(obj->bit_17);	201	if (obj->ops->release)
208	i915_gem_object_free(obj);	202	obj->ops->release(obj);
209
210	GEM_BUG_ON(!atomic_read(&i915->mm.free_count));
211	atomic_dec(&i915->mm.free_count);
212		203
213	cond_resched();	204	/* But keep the pointer alive for RCU-protected lookups */
		205	call_rcu(&obj->rcu, __i915_gem_free_object_rcu);
214	}	206	}
215	intel_runtime_pm_put(&i915->runtime_pm, wakeref);	207	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
216	}	208	}
@@ -261,18 +253,34 @@ static void __i915_gem_free_work(struct work_struct *work) · 44 unmodified lines
261	spin_unlock(&i915->mm.free_lock);	253	spin_unlock(&i915->mm.free_lock);
262	}	254	}
263		255
264	static void __i915_gem_free_object_rcu(struct rcu_head *head)	256	void i915_gem_free_object(struct drm_gem_object *gem_obj)
265	{	257	{
266	struct drm_i915_gem_object *obj =	258	struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
267	container_of(head, typeof(*obj), rcu);
268	struct drm_i915_private *i915 = to_i915(obj->base.dev);	259	struct drm_i915_private *i915 = to_i915(obj->base.dev);
269		260
270	/*	261	/*
271	* We reuse obj->rcu for the freed list, so we had better not treat	262	* Before we free the object, make sure any pure RCU-only
272	* it like a rcu_head from this point forwards. And we expect all	263	* read-side critical sections are complete, e.g.
273	* objects to be freed via this path.	264	* i915_gem_busy_ioctl(). For the corresponding synchronized
		265	* lookup see i915_gem_object_lookup_rcu().
274	*/	266	*/
275	destroy_rcu_head(&obj->rcu);	267	atomic_inc(&i915->mm.free_count);
		268
		269	/*
		270	* This serializes freeing with the shrinker. Since the free
		271	* is delayed, first by RCU then by the workqueue, we want the
		272	* shrinker to be able to free pages of unreferenced objects,
		273	* or else we may oom whilst there are plenty of deferred
		274	* freed objects.
		275	*/
		276	if (i915_gem_object_has_pages(obj) &&
		277	i915_gem_object_is_shrinkable(obj)) {
		278	unsigned long flags;
		279
		280	spin_lock_irqsave(&i915->mm.obj_lock, flags);
		281	list_del_init(&obj->mm.link);
		282	spin_unlock_irqrestore(&i915->mm.obj_lock, flags);
		283	}
276		284
277	/*	285	/*
278	* Since we require blocking on struct_mutex to unbind the freed	286	* Since we require blocking on struct_mutex to unbind the freed
@@ -288,20 +296,6 @@ static void __i915_gem_free_object_rcu(struct rcu_head *head) · 9 unmodified lines
288	queue_work(i915->wq, &i915->mm.free_work);	296	queue_work(i915->wq, &i915->mm.free_work);
289	}	297	}
290		298
291	void i915_gem_free_object(struct drm_gem_object *gem_obj)
292	{
293	struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
294
295	/*
296	* Before we free the object, make sure any pure RCU-only
297	* read-side critical sections are complete, e.g.
298	* i915_gem_busy_ioctl(). For the corresponding synchronized
299	* lookup see i915_gem_object_lookup_rcu().
300	*/
301	atomic_inc(&to_i915(obj->base.dev)->mm.free_count);
302	call_rcu(&obj->rcu, __i915_gem_free_object_rcu);
303	}
304
305	static inline enum fb_op_origin	299	static inline enum fb_op_origin
306	fb_write_origin(struct drm_i915_gem_object *obj, unsigned int domain)	300	fb_write_origin(struct drm_i915_gem_object *obj, unsigned int domain)
307	{	301	{
@@ -319,7 +313,6 @@ void · 11 unmodified lines
319	i915_gem_object_flush_write_domain(struct drm_i915_gem_object *obj,	313	i915_gem_object_flush_write_domain(struct drm_i915_gem_object *obj,
320	unsigned int flush_domains)	314	unsigned int flush_domains)
321	{	315	{
322	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
323	struct i915_vma *vma;	316	struct i915_vma *vma;
324		317
325	assert_object_held(obj);	318	assert_object_held(obj);
@@ -329,7 +322,8 @@ i915_gem_object_flush_write_domain(struct drm_i915_gem_object *obj, · 3 unmodified lines
329		322
330	switch (obj->write_domain) {	323	switch (obj->write_domain) {
331	case I915_GEM_DOMAIN_GTT:	324	case I915_GEM_DOMAIN_GTT:
332	i915_gem_flush_ggtt_writes(dev_priv);	325	for_each_ggtt_vma(vma, obj)
		326	intel_gt_flush_ggtt_writes(vma->vm->gt);
333		327
334	intel_fb_obj_flush(obj,	328	intel_fb_obj_flush(obj,
335	fb_write_origin(obj, I915_GEM_DOMAIN_GTT));	329	fb_write_origin(obj, I915_GEM_DOMAIN_GTT));
@@ -340,6 +334,7 @@ i915_gem_object_flush_write_domain(struct drm_i915_gem_object *obj, · 4 unmodified lines
340		334
341	i915_vma_unset_ggtt_write(vma);	335	i915_vma_unset_ggtt_write(vma);
342	}	336	}
		337
343	break;	338	break;
344		339
345	case I915_GEM_DOMAIN_WC:	340	case I915_GEM_DOMAIN_WC:

drivers/gpu/drm/i915/gem/i915_gem_object.h+1−7

 }
 __deprecated
-extern struct drm_gem_object *
+struct drm_gem_object *
 drm_gem_object_lookup(struct drm_file *file, u32 handle);
 __attribute__((nonnull))
 	return obj->ops->flags & I915_GEM_OBJECT_ASYNC_CANCEL;
 }
-static inline bool
-i915_gem_object_is_active(const struct drm_i915_gem_object *obj)
-{
-	return READ_ONCE(obj->active_count);
-}
 static inline bool
 i915_gem_object_is_framebuffer(const struct drm_i915_gem_object *obj)
 {

drivers/gpu/drm/i915/gem/i915_gem_object_blt.c+1−5

 			     struct intel_context *ce,
 			     u32 value)
 {
-	struct drm_i915_private *i915 = to_i915(obj->base.dev);
-	struct i915_gem_context *ctx = ce->gem_context;
-	struct i915_address_space *vm = ctx->vm ?: &i915->ggtt.vm;
 	struct i915_request *rq;
 	struct i915_vma *vma;
 	int err;
-	/* XXX: ce->vm please */
+	vma = i915_vma_instance(obj, ce->vm, NULL);
-	vma = i915_vma_instance(obj, vm, NULL);
 	if (IS_ERR(vma))
 		return PTR_ERR(vma);

drivers/gpu/drm/i915/gem/i915_gem_object_types.h+0−1

@@ -154,7 +154,6 @@ struct drm_i915_gem_object { · 153 unmodified lines
154		154
155	/** Count of VMA actually bound by this object */	155	/** Count of VMA actually bound by this object */
156	atomic_t bind_count;	156	atomic_t bind_count;
157	unsigned int active_count;
158	/** Count of how many global VMA are currently pinned for use by HW */	157	/** Count of how many global VMA are currently pinned for use by HW */
159	unsigned int pin_global;	158	unsigned int pin_global;
160		159

drivers/gpu/drm/i915/gem/i915_gem_phys.c+3−9

 #include <drm/drm_legacy.h> /* for drm_pci.h! */
 #include <drm/drm_pci.h>
+#include "gt/intel_gt.h"
 #include "i915_drv.h"
 #include "i915_gem_object.h"
 #include "i915_scatterlist.h"
 		vaddr += PAGE_SIZE;
 	}
-	i915_gem_chipset_flush(to_i915(obj->base.dev));
+	intel_gt_chipset_flush(&to_i915(obj->base.dev)->gt);
 	st = kmalloc(sizeof(*st), GFP_KERNEL);
 	if (!st) {
 	drm_pci_free(obj->base.dev, obj->phys_handle);
 }
-static void
-i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
-{
-	i915_gem_object_unpin_pages(obj);
-}
 static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
 	.get_pages = i915_gem_object_get_pages_phys,
 	.put_pages = i915_gem_object_put_pages_phys,
-	.release = i915_gem_object_release_phys,
 };
 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, int align)
 	if (obj->ops != &i915_gem_shmem_ops)
 		return -EINVAL;
-	err = i915_gem_object_unbind(obj);
+	err = i915_gem_object_unbind(obj, I915_GEM_OBJECT_UNBIND_ACTIVE);
 	if (err)
 		return err;

drivers/gpu/drm/i915/gem/i915_gem_pm.c+19−18

  */
 #include "gem/i915_gem_pm.h"
+#include "gt/intel_gt.h"
 #include "gt/intel_gt_pm.h"
 #include "i915_drv.h"
 		i915_gem_batch_pool_fini(&engine->batch_pool);
 	}
-	i915_timelines_park(i915);
+	intel_timelines_park(i915);
 	i915_vma_parked(i915);
 	i915_globals_park();
 	mutex_lock(&i915->drm.struct_mutex);
 	intel_wakeref_lock(&i915->gt.wakeref);
-	park = !intel_wakeref_active(&i915->gt.wakeref) && !work_pending(work);
+	park = (!intel_wakeref_is_active(&i915->gt.wakeref) &&
+		!work_pending(work));
 	intel_wakeref_unlock(&i915->gt.wakeref);
 	if (park)
 		i915_gem_park(i915);
 	return NOTIFY_OK;
 }
-static bool switch_to_kernel_context_sync(struct drm_i915_private *i915)
+static bool switch_to_kernel_context_sync(struct intel_gt *gt)
 {
-	bool result = !i915_terminally_wedged(i915);
+	bool result = !intel_gt_is_wedged(gt);
 	do {
-		if (i915_gem_wait_for_idle(i915,
+		if (i915_gem_wait_for_idle(gt->i915,
 					   I915_WAIT_LOCKED |
 					   I915_WAIT_FOR_IDLE_BOOST,
 					   I915_GEM_IDLE_TIMEOUT) == -ETIME) {
 			/* XXX hide warning from gem_eio */
 			if (i915_modparams.reset) {
-				dev_err(i915->drm.dev,
+				dev_err(gt->i915->drm.dev,
 					"Failed to idle engines, declaring wedged!\n");
 				GEM_TRACE_DUMP();
 			}
 			 * Forcibly cancel outstanding work and leave
 			 * the gpu quiet.
 			 */
-			i915_gem_set_wedged(i915);
+			intel_gt_set_wedged(gt);
 			result = false;
 		}
-	} while (i915_retire_requests(i915) && result);
+	} while (i915_retire_requests(gt->i915) && result);
-	GEM_BUG_ON(i915->gt.awake);
+	GEM_BUG_ON(gt->awake);
 	return result;
 }
 bool i915_gem_load_power_context(struct drm_i915_private *i915)
 {
-	return switch_to_kernel_context_sync(i915);
+	return switch_to_kernel_context_sync(&i915->gt);
 }
 void i915_gem_suspend(struct drm_i915_private *i915)
 	 * state. Fortunately, the kernel_context is disposable and we do
 	 * not rely on its state.
 	 */
-	switch_to_kernel_context_sync(i915);
+	switch_to_kernel_context_sync(&i915->gt);
 	mutex_unlock(&i915->drm.struct_mutex);
 	GEM_BUG_ON(i915->gt.awake);
 	flush_work(&i915->gem.idle_work);
-	cancel_delayed_work_sync(&i915->gpu_error.hangcheck_work);
+	cancel_delayed_work_sync(&i915->gt.hangcheck.work);
 	i915_gem_drain_freed_objects(i915);
-	intel_uc_suspend(i915);
+	intel_uc_suspend(&i915->gt.uc);
 }
 static struct drm_i915_gem_object *first_mm_object(struct list_head *list)
 	}
 	spin_unlock_irqrestore(&i915->mm.obj_lock, flags);
-	intel_uc_sanitize(i915);
 	i915_gem_sanitize(i915);
 }
 	 * guarantee that the context image is complete. So let's just reset
 	 * it and start again.
 	 */
-	if (intel_gt_resume(i915))
+	if (intel_gt_resume(&i915->gt))
 		goto err_wedged;
-	intel_uc_resume(i915);
+	intel_uc_resume(&i915->gt.uc);
 	/* Always reload a context for powersaving. */
 	if (!i915_gem_load_power_context(i915))
 	return;
 err_wedged:
-	if (!i915_reset_failed(i915)) {
+	if (!intel_gt_is_wedged(&i915->gt)) {
 		dev_err(i915->drm.dev,
 			"Failed to re-initialize GPU, declaring it wedged!\n");
-		i915_gem_set_wedged(i915);
+		intel_gt_set_wedged(&i915->gt);
 	}
 	goto out_unlock;
 }

drivers/gpu/drm/i915/gem/i915_gem_shmem.c+7−0

 	return 0;
 }
+static void shmem_release(struct drm_i915_gem_object *obj)
+{
+	fput(obj->base.filp);
+}
 const struct drm_i915_gem_object_ops i915_gem_shmem_ops = {
 	.flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE |
 		 I915_GEM_OBJECT_IS_SHRINKABLE,
 	.writeback = shmem_writeback,
 	.pwrite = shmem_pwrite,
+	.release = shmem_release,
 };
 static int create_shmem(struct drm_i915_private *i915,

drivers/gpu/drm/i915/gem/i915_gem_shrinker.c+12−15

 	return swap_available() || obj->mm.madv == I915_MADV_DONTNEED;
 }
-static bool unsafe_drop_pages(struct drm_i915_gem_object *obj)
+static bool unsafe_drop_pages(struct drm_i915_gem_object *obj,
+			      unsigned long shrink)
 {
-	if (i915_gem_object_unbind(obj) == 0)
+	unsigned long flags;
+	flags = 0;
+	if (shrink & I915_SHRINK_ACTIVE)
+		flags = I915_GEM_OBJECT_UNBIND_ACTIVE;
+	if (i915_gem_object_unbind(obj, flags) == 0)
 		__i915_gem_object_put_pages(obj, I915_MM_SHRINKER);
 	return !i915_gem_object_has_pages(obj);
 }
 	 */
 	trace_i915_gem_shrink(i915, target, shrink);
-	i915_retire_requests(i915);
 	/*
 	 * Unbinding of objects will require HW access; Let us not wake the
 				continue;
 			if (!(shrink & I915_SHRINK_ACTIVE) &&
-			    (i915_gem_object_is_active(obj) ||
+			    i915_gem_object_is_framebuffer(obj))
-			     i915_gem_object_is_framebuffer(obj)))
 				continue;
 			if (!(shrink & I915_SHRINK_BOUND) &&
 			spin_unlock_irqrestore(&i915->mm.obj_lock, flags);
-			if (unsafe_drop_pages(obj)) {
+			if (unsafe_drop_pages(obj, shrink)) {
 				/* May arrive from get_pages on another bo */
 				mutex_lock_nested(&obj->mm.lock,
 						  I915_MM_SHRINKER);
 	if (shrink & I915_SHRINK_BOUND)
 		intel_runtime_pm_put(&i915->runtime_pm, wakeref);
-	i915_retire_requests(i915);
 	shrinker_unlock(i915, unlock);
 	if (nr_scanned)
 	if (!shrinker_lock(i915, 0, &unlock))
 		return NOTIFY_DONE;
-	/* Force everything onto the inactive lists */
-	if (i915_gem_wait_for_idle(i915,
-				   I915_WAIT_LOCKED,
-				   MAX_SCHEDULE_TIMEOUT))
-		goto out;
 	with_intel_runtime_pm(&i915->runtime_pm, wakeref)
 		freed_pages += i915_gem_shrink(i915, -1UL, NULL,
 					       I915_SHRINK_BOUND |
 	}
 	mutex_unlock(&i915->ggtt.vm.mutex);
-out:
 	shrinker_unlock(i915, unlock);
 	*(unsigned long *)ptr += freed_pages;

drivers/gpu/drm/i915/gem/i915_gem_stolen.c+0−2

@@ -529,8 +529,6 @@ i915_gem_object_release_stolen(struct drm_i915_gem_object *obj) · 528 unmodified lines
529		529
530	GEM_BUG_ON(!stolen);	530	GEM_BUG_ON(!stolen);
531		531
532	__i915_gem_object_unpin_pages(obj);
533
534	i915_gem_stolen_remove_node(dev_priv, stolen);	532	i915_gem_stolen_remove_node(dev_priv, stolen);
535	kfree(stolen);	533	kfree(stolen);
536	}	534	}

drivers/gpu/drm/i915/gem/i915_gem_throttle.c+1−1

@@ -41,7 +41,7 @@ i915_gem_throttle_ioctl(struct drm_device dev, void data, · 40 unmodified lines
41	long ret;	41	long ret;
42		42
43	/* ABI: return -EIO if already wedged */	43	/* ABI: return -EIO if already wedged */
44	ret = i915_terminally_wedged(to_i915(dev));	44	ret = intel_gt_terminally_wedged(&to_i915(dev)->gt);
45	if (ret)	45	if (ret)
46	return ret;	46	return ret;
47		47

drivers/gpu/drm/i915/gem/i915_gem_userptr.c+10−1

 			}
 		}
-		ret = i915_gem_object_unbind(obj);
+		ret = i915_gem_object_unbind(obj,
+					     I915_GEM_OBJECT_UNBIND_ACTIVE);
 		if (ret == 0)
 			ret = __i915_gem_object_put_pages(obj, I915_MM_SHRINKER);
 		i915_gem_object_put(obj);
 	__i915_gem_object_release_shmem(obj, pages, true);
 	i915_gem_gtt_finish_pages(obj, pages);
+	/*
+	 * We always mark objects as dirty when they are used by the GPU,
+	 * just in case. However, if we set the vma as being read-only we know
+	 * that the object will never have been written to.
+	 */
+	if (i915_gem_object_is_readonly(obj))
+		obj->mm.dirty = false;
 	for_each_sgt_page(page, sgt_iter, pages) {
 		if (obj->mm.dirty)
 			/*

drivers/gpu/drm/i915/gem/selftests/huge_pages.c+48−21

 #include "gem/i915_gem_pm.h"
+#include "gt/intel_gt.h"
 #include "igt_gem_utils.h"
 #include "mock_context.h"
 	}
 	*cmd = MI_BATCH_BUFFER_END;
-	i915_gem_chipset_flush(i915);
+	intel_gt_chipset_flush(vma->vm->gt);
 	i915_gem_object_unpin_map(obj);
 			    u64 size, u64 offset,
 			    u32 dword, u32 val)
 {
-	struct drm_i915_private *i915 = to_i915(obj->base.dev);
+	struct i915_address_space *vm = ctx->vm ?: &engine->gt->ggtt->vm;
-	struct i915_address_space *vm = ctx->vm ?: &i915->ggtt.vm;
 	unsigned int flags = PIN_USER | PIN_OFFSET_FIXED;
 	struct i915_vma *vma;
 	int err;
 	struct drm_i915_gem_object *obj;
 	struct i915_vma *vma;
 	unsigned int flags = PIN_USER | PIN_OFFSET_FIXED;
+	struct intel_engine_cs *engine;
+	enum intel_engine_id id;
+	unsigned int n;
 	int first, last;
 	int err;
 	 * land in the now stale 2M page.
 	 */
-	err = gpu_write(vma, ctx, dev_priv->engine[RCS0], 0, 0xdeadbeaf);
+	n = 0;
-	if (err)
+	for_each_engine(engine, dev_priv, id) {
-		goto out_unpin;
+		if (!intel_engine_can_store_dword(engine))
+			continue;
-	err = cpu_check(obj, 0, 0xdeadbeaf);
+		err = gpu_write(vma, ctx, engine, n++, 0xdeadbeaf);
+		if (err)
+			goto out_unpin;
+	}
+	while (n--) {
+		err = cpu_check(obj, n, 0xdeadbeaf);
+		if (err)
+			goto out_unpin;
+	}
 out_unpin:
 	i915_vma_unpin(vma);
 	struct drm_i915_private *i915 = ctx->i915;
 	struct i915_address_space *vm = ctx->vm ?: &i915->ggtt.vm;
 	struct drm_i915_gem_object *obj;
+	struct intel_engine_cs *engine;
+	enum intel_engine_id id;
 	struct i915_vma *vma;
 	unsigned int flags = PIN_USER;
+	unsigned int n;
 	int err;
 	/*
 	if (err)
 		goto out_unpin;
-	err = gpu_write(vma, ctx, i915->engine[RCS0], 0, 0xdeadbeaf);
+	n = 0;
-	if (err)
+	for_each_engine(engine, i915, id) {
-		goto out_unpin;
+		if (!intel_engine_can_store_dword(engine))
+			continue;
+		err = gpu_write(vma, ctx, engine, n++, 0xdeadbeaf);
+		if (err)
+			goto out_unpin;
+	}
 	i915_vma_unpin(vma);
 	if (err)
 		goto out_close;
-	err = cpu_check(obj, 0, 0xdeadbeaf);
+	while (n--) {
+		err = cpu_check(obj, n, 0xdeadbeaf);
+		if (err)
+			goto out_unpin;
+	}
 out_unpin:
 	i915_vma_unpin(vma);
 	return err;
 }
-int i915_gem_huge_page_live_selftests(struct drm_i915_private *dev_priv)
+int i915_gem_huge_page_live_selftests(struct drm_i915_private *i915)
 {
 	static const struct i915_subtest tests[] = {
 		SUBTEST(igt_shrink_thp),
 	intel_wakeref_t wakeref;
 	int err;
-	if (!HAS_PPGTT(dev_priv)) {
+	if (!HAS_PPGTT(i915)) {
 		pr_info("PPGTT not supported, skipping live-selftests\n");
 		return 0;
 	}
-	if (i915_terminally_wedged(dev_priv))
+	if (intel_gt_is_wedged(&i915->gt))
 		return 0;
-	file = mock_file(dev_priv);
+	file = mock_file(i915);
 	if (IS_ERR(file))
 		return PTR_ERR(file);
-	mutex_lock(&dev_priv->drm.struct_mutex);
+	mutex_lock(&i915->drm.struct_mutex);
-	wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
+	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
-	ctx = live_context(dev_priv, file);
+	ctx = live_context(i915, file);
 	if (IS_ERR(ctx)) {
 		err = PTR_ERR(ctx);
 		goto out_unlock;
 	err = i915_subtests(tests, ctx);
 out_unlock:
-	intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
+	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
-	mutex_unlock(&dev_priv->drm.struct_mutex);
+	mutex_unlock(&i915->drm.struct_mutex);
-	mock_file_free(dev_priv, file);
+	mock_file_free(i915, file);
 	return err;
 }

drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c+6−20

 #include "i915_selftest.h"
+#include "gt/intel_gt.h"
 #include "selftests/igt_flush_test.h"
 #include "selftests/mock_drm.h"
 #include "mock_context.h"
 static int igt_client_fill(void *arg)
 {
-	struct intel_context *ce = arg;
+	struct drm_i915_private *i915 = arg;
-	struct drm_i915_private *i915 = ce->gem_context->i915;
+	struct intel_context *ce = i915->engine[BCS0]->kernel_context;
 	struct drm_i915_gem_object *obj;
 	struct rnd_state prng;
 	IGT_TIMEOUT(end);
 		if (err)
 			goto err_unpin;
-		/*
-		 * XXX: For now do the wait without the object resv lock to
-		 * ensure we don't deadlock.
-		 */
-		err = i915_gem_object_wait(obj,
-					   I915_WAIT_INTERRUPTIBLE |
-					   I915_WAIT_ALL,
-					   MAX_SCHEDULE_TIMEOUT);
-		if (err)
-			goto err_unpin;
 		i915_gem_object_lock(obj);
 		err = i915_gem_object_set_to_cpu_domain(obj, false);
 		i915_gem_object_unlock(obj);
 err_put:
 	i915_gem_object_put(obj);
 err_flush:
-	mutex_lock(&i915->drm.struct_mutex);
-	if (igt_flush_test(i915, I915_WAIT_LOCKED))
-		err = -EIO;
-	mutex_unlock(&i915->drm.struct_mutex);
 	if (err == -ENOMEM)
 		err = 0;
 		SUBTEST(igt_client_fill),
 	};
-	if (i915_terminally_wedged(i915))
+	if (intel_gt_is_wedged(&i915->gt))
 		return 0;
 	if (!HAS_ENGINE(i915, BCS0))
 		return 0;
-	return i915_subtests(tests, i915->engine[BCS0]->kernel_context);
+	return i915_live_subtests(tests, i915);
 }

drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c+7−2

 #include <linux/prime_numbers.h>
+#include "gt/intel_gt.h"
 #include "i915_selftest.h"
 #include "selftests/i915_random.h"
 static bool needs_fence_registers(struct drm_i915_private *i915)
 {
-	return !i915_terminally_wedged(i915);
+	return !intel_gt_is_wedged(&i915->gt);
 }
 static bool needs_mi_store_dword(struct drm_i915_private *i915)
 {
-	if (i915_terminally_wedged(i915))
+	if (intel_gt_is_wedged(&i915->gt))
+		return false;
+	if (!HAS_ENGINE(i915, RCS0))
 		return false;
 	return intel_engine_can_store_dword(i915->engine[RCS0]);

drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c+36−49

 #include <linux/prime_numbers.h>
 #include "gem/i915_gem_pm.h"
+#include "gt/intel_gt.h"
 #include "gt/intel_reset.h"
 #include "i915_selftest.h"
 	struct intel_engine_cs *engine;
 	struct i915_gem_context **ctx;
 	enum intel_engine_id id;
-	intel_wakeref_t wakeref;
 	struct igt_live_test t;
 	struct drm_file *file;
 	unsigned long n;
 		return PTR_ERR(file);
 	mutex_lock(&i915->drm.struct_mutex);
-	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
 	ctx = kcalloc(nctx, sizeof(*ctx), GFP_KERNEL);
 	if (!ctx) {
 		}
 		if (i915_request_wait(rq, 0, HZ / 5) < 0) {
 			pr_err("Failed to populated %d contexts\n", nctx);
-			i915_gem_set_wedged(i915);
+			intel_gt_set_wedged(&i915->gt);
 			err = -EIO;
 			goto out_unlock;
 		}
 			if (i915_request_wait(rq, 0, HZ / 5) < 0) {
 				pr_err("Switching between %ld contexts timed out\n",
 				       prime);
-				i915_gem_set_wedged(i915);
+				intel_gt_set_wedged(&i915->gt);
 				break;
 			}
 	}
 out_unlock:
-	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
 	mutex_unlock(&i915->drm.struct_mutex);
 	mock_file_free(i915, file);
 	return err;
 		    struct intel_engine_cs *engine,
 		    unsigned int dw)
 {
-	struct drm_i915_private *i915 = to_i915(obj->base.dev);
+	struct i915_address_space *vm = ctx->vm ?: &engine->gt->ggtt->vm;
-	struct i915_address_space *vm = ctx->vm ?: &i915->ggtt.vm;
 	struct i915_request *rq;
 	struct i915_vma *vma;
 	struct i915_vma *batch;
 	u64 size;
 	int err;
+	/* Keep in GEM's good graces */
+	i915_retire_requests(ctx->i915);
 	size = min(vm->total / 2, 1024ull * DW_PER_PAGE * PAGE_SIZE);
 	size = round_down(size, DW_PER_PAGE * PAGE_SIZE);
 		dw = 0;
 		while (!time_after(jiffies, end_time)) {
 			struct i915_gem_context *ctx;
-			intel_wakeref_t wakeref;
 			ctx = live_context(i915, file);
 			if (IS_ERR(ctx)) {
 				}
 			}
-			with_intel_runtime_pm(&i915->runtime_pm, wakeref)
+			err = gpu_fill(obj, ctx, engine, dw);
-				err = gpu_fill(obj, ctx, engine, dw);
 			if (err) {
 				pr_err("Failed to fill dword %lu [%lu/%lu] with gpu (%s) in ctx %u [full-ppgtt? %s], err=%d\n",
 				       ndwords, dw, max_dwords(obj),
 		mock_file_free(i915, file);
 		if (err)
 			return err;
+		i915_gem_drain_freed_objects(i915);
 	}
 	return 0;
 		ncontexts = 0;
 		while (!time_after(jiffies, end_time)) {
 			struct i915_gem_context *ctx;
-			intel_wakeref_t wakeref;
 			ctx = kernel_context(i915);
 			if (IS_ERR(ctx)) {
 				}
 			}
-			err = 0;
+			err = gpu_fill(obj, ctx, engine, dw);
-			with_intel_runtime_pm(&i915->runtime_pm, wakeref)
-				err = gpu_fill(obj, ctx, engine, dw);
 			if (err) {
 				pr_err("Failed to fill dword %lu [%lu/%lu] with gpu (%s) in ctx %u [full-ppgtt? %s], err=%d\n",
 				       ndwords, dw, max_dwords(obj),
 			dw += rem;
 		}
+		mutex_unlock(&i915->drm.struct_mutex);
+		i915_gem_drain_freed_objects(i915);
+		mutex_lock(&i915->drm.struct_mutex);
 	}
 out_test:
 	if (igt_live_test_end(&t))
 	GEM_BUG_ON(!intel_engine_can_store_dword(ce->engine));
-	vma = i915_vma_instance(obj, ce->gem_context->vm, NULL);
+	vma = i915_vma_instance(obj, ce->vm, NULL);
 	if (IS_ERR(vma))
 		return PTR_ERR(vma);
 	int ret = 0;
 	if (flags & TEST_RESET) {
-		ret = i915_reset_engine(ce->engine, "sseu");
+		ret = intel_engine_reset(ce->engine, "sseu");
 		if (ret)
 			goto out;
 	}
 	       unsigned int flags)
 {
 	struct intel_engine_cs *engine = i915->engine[RCS0];
-	struct intel_sseu default_sseu = engine->sseu;
 	struct drm_i915_gem_object *obj;
 	struct i915_gem_context *ctx;
 	struct intel_context *ce;
 	struct intel_sseu pg_sseu;
-	intel_wakeref_t wakeref;
 	struct drm_file *file;
 	int ret;
-	if (INTEL_GEN(i915) < 9)
+	if (INTEL_GEN(i915) < 9 || !engine)
 		return 0;
 	if (!RUNTIME_INFO(i915)->sseu.has_slice_pg)
 		return 0;
-	if (hweight32(default_sseu.slice_mask) < 2)
+	if (hweight32(engine->sseu.slice_mask) < 2)
 		return 0;
 	/*
 	 * Gen11 VME friendly power-gated configuration with half enabled
 	 * sub-slices.
 	 */
-	pg_sseu = default_sseu;
+	pg_sseu = engine->sseu;
 	pg_sseu.slice_mask = 1;
 	pg_sseu.subslice_mask =
-		~(~0 << (hweight32(default_sseu.subslice_mask) / 2));
+		~(~0 << (hweight32(engine->sseu.subslice_mask) / 2));
 	pr_info("SSEU subtest '%s', flags=%x, def_slices=%u, pg_slices=%u\n",
-		name, flags, hweight32(default_sseu.slice_mask),
+		name, flags, hweight32(engine->sseu.slice_mask),
 		hweight32(pg_sseu.slice_mask));
 	file = mock_file(i915);
 		return PTR_ERR(file);
 	if (flags & TEST_RESET)
-		igt_global_reset_lock(i915);
+		igt_global_reset_lock(&i915->gt);
 	mutex_lock(&i915->drm.struct_mutex);
 		goto out_unlock;
 	}
-	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
 	ce = i915_gem_context_get_engine(ctx, RCS0);
 	if (IS_ERR(ce)) {
 		ret = PTR_ERR(ce);
-		goto out_rpm;
+		goto out_put;
 	}
 	ret = intel_context_pin(ce);
 		goto out_context;
 	/* First set the default mask. */
-	ret = __sseu_test(i915, name, flags, ce, obj, default_sseu);
+	ret = __sseu_test(i915, name, flags, ce, obj, engine->sseu);
 	if (ret)
 		goto out_fail;
 		goto out_fail;
 	/* Back to defaults. */
-	ret = __sseu_test(i915, name, flags, ce, obj, default_sseu);
+	ret = __sseu_test(i915, name, flags, ce, obj, engine->sseu);
 	if (ret)
 		goto out_fail;
 	intel_context_unpin(ce);
 out_context:
 	intel_context_put(ce);
-out_rpm:
+out_put:
-	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
 	i915_gem_object_put(obj);
 out_unlock:
 	mutex_unlock(&i915->drm.struct_mutex);
 	if (flags & TEST_RESET)
-		igt_global_reset_unlock(i915);
+		igt_global_reset_unlock(&i915->gt);
 	mock_file_free(i915, file);
 		goto out_unlock;
 	}
-	vm = ctx->vm ?: &i915->mm.aliasing_ppgtt->vm;
+	vm = ctx->vm ?: &i915->ggtt.alias->vm;
 	if (!vm || !vm->has_read_only) {
 		err = 0;
 		goto out_unlock;
 		unsigned int id;
 		for_each_engine(engine, i915, id) {
-			intel_wakeref_t wakeref;
 			if (!intel_engine_can_store_dword(engine))
 				continue;
 					i915_gem_object_set_readonly(obj);
 			}
-			err = 0;
+			err = gpu_fill(obj, ctx, engine, dw);
-			with_intel_runtime_pm(&i915->runtime_pm, wakeref)
-				err = gpu_fill(obj, ctx, engine, dw);
 			if (err) {
 				pr_err("Failed to fill dword %lu [%lu/%lu] with gpu (%s) in ctx %u [full-ppgtt? %s], err=%d\n",
 				       ndwords, dw, max_dwords(obj),
 	struct drm_i915_private *i915 = arg;
 	struct i915_gem_context *ctx_a, *ctx_b;
 	struct intel_engine_cs *engine;
-	intel_wakeref_t wakeref;
 	struct igt_live_test t;
 	struct drm_file *file;
 	I915_RND_STATE(prng);
 	GEM_BUG_ON(ctx_b->vm->total != vm_total);
 	vm_total -= I915_GTT_PAGE_SIZE;
-	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
 	count = 0;
 	for_each_engine(engine, i915, id) {
 		IGT_TIMEOUT(end_time);
 			div64_u64_rem(i915_prandom_u64_state(&prng),
 				      vm_total, &offset);
-			offset &= -sizeof(u32);
+			offset = round_down(offset, alignof_dword);
 			offset += I915_GTT_PAGE_SIZE;
 			err = write_to_scratch(ctx_a, engine,
 				err = read_from_scratch(ctx_b, engine,
 							offset, &value);
 			if (err)
-				goto out_rpm;
+				goto out_unlock;
 			if (value) {
 				pr_err("%s: Read %08x from scratch (offset 0x%08x_%08x), after %lu reads!\n",
 				       lower_32_bits(offset),
 				       this);
 				err = -EINVAL;
-				goto out_rpm;
+				goto out_unlock;
 			}
 			this++;
 	pr_info("Checked %lu scratch offsets across %d engines\n",
 		count, RUNTIME_INFO(i915)->num_engines);
-out_rpm:
-	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
 out_unlock:
 	if (igt_live_test_end(&t))
 		err = -EIO;
 	return err;
 }
-int i915_gem_context_live_selftests(struct drm_i915_private *dev_priv)
+int i915_gem_context_live_selftests(struct drm_i915_private *i915)
 {
 	static const struct i915_subtest tests[] = {
 		SUBTEST(live_nop_switch),
 		SUBTEST(igt_vm_isolation),
 	};
-	if (i915_terminally_wedged(dev_priv))
+	if (intel_gt_is_wedged(&i915->gt))
 		return 0;
-	return i915_subtests(tests, dev_priv);
+	return i915_live_subtests(tests, i915);
 }

drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c+36−23

@@ -6,6 +6,7 @@ · 5 unmodified lines
6		6
7	#include <linux/prime_numbers.h>	7	#include <linux/prime_numbers.h>
8		8
		9	#include "gt/intel_gt.h"
9	#include "gt/intel_gt_pm.h"	10	#include "gt/intel_gt_pm.h"
10	#include "huge_gem_object.h"	11	#include "huge_gem_object.h"
11	#include "i915_selftest.h"	12	#include "i915_selftest.h"
@@ -143,7 +144,7 @@ static int check_partial_mapping(struct drm_i915_gem_object *obj, · 131 unmodified lines
143	if (offset >= obj->base.size)	144	if (offset >= obj->base.size)
144	continue;	145	continue;
145		146
146	i915_gem_flush_ggtt_writes(to_i915(obj->base.dev));	147	intel_gt_flush_ggtt_writes(&to_i915(obj->base.dev)->gt);
147		148
148	p = i915_gem_object_get_page(obj, offset >> PAGE_SHIFT);	149	p = i915_gem_object_get_page(obj, offset >> PAGE_SHIFT);
149	cpu = kmap(p) + offset_in_page(offset);	150	cpu = kmap(p) + offset_in_page(offset);
@@ -327,7 +328,8 @@ out: · 177 unmodified lines
327	static int make_obj_busy(struct drm_i915_gem_object *obj)	328	static int make_obj_busy(struct drm_i915_gem_object *obj)
328	{	329	{
329	struct drm_i915_private *i915 = to_i915(obj->base.dev);	330	struct drm_i915_private *i915 = to_i915(obj->base.dev);
330	struct i915_request *rq;	331	struct intel_engine_cs *engine;
		332	enum intel_engine_id id;
331	struct i915_vma *vma;	333	struct i915_vma *vma;
332	int err;	334	int err;
333		335
@@ -339,17 +341,21 @@ static int make_obj_busy(struct drm_i915_gem_object *obj) · 5 unmodified lines
339	if (err)	341	if (err)
340	return err;	342	return err;
341		343
342	rq = i915_request_create(i915->engine[RCS0]->kernel_context);	344	for_each_engine(engine, i915, id) {
343	if (IS_ERR(rq)) {	345	struct i915_request *rq;
344	i915_vma_unpin(vma);	346
345	return PTR_ERR(rq);	347	rq = i915_request_create(engine->kernel_context);
346	}	348	if (IS_ERR(rq)) {
		349	i915_vma_unpin(vma);
		350	return PTR_ERR(rq);
		351	}
347		352
348	i915_vma_lock(vma);	353	i915_vma_lock(vma);
349	err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);	354	err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
350	i915_vma_unlock(vma);	355	i915_vma_unlock(vma);
351		356
352	i915_request_add(rq);	357	i915_request_add(rq);
		358	}
353		359
354	i915_vma_unpin(vma);	360	i915_vma_unpin(vma);
355	i915_gem_object_put(obj); /* leave it only alive via its active ref */	361	i915_gem_object_put(obj); /* leave it only alive via its active ref */
@@ -378,7 +384,7 @@ static void disable_retire_worker(struct drm_i915_private *i915) · 22 unmodified lines
378	{	384	{
379	i915_gem_shrinker_unregister(i915);	385	i915_gem_shrinker_unregister(i915);
380		386
381	intel_gt_pm_get(i915);	387	intel_gt_pm_get(&i915->gt);
382		388
383	cancel_delayed_work_sync(&i915->gem.retire_work);	389	cancel_delayed_work_sync(&i915->gem.retire_work);
384	flush_work(&i915->gem.idle_work);	390	flush_work(&i915->gem.idle_work);
@@ -386,7 +392,7 @@ static void disable_retire_worker(struct drm_i915_private *i915) · 1 unmodified line
386		392
387	static void restore_retire_worker(struct drm_i915_private *i915)	393	static void restore_retire_worker(struct drm_i915_private *i915)
388	{	394	{
389	intel_gt_pm_put(i915);	395	intel_gt_pm_put(&i915->gt);
390		396
391	mutex_lock(&i915->drm.struct_mutex);	397	mutex_lock(&i915->drm.struct_mutex);
392	igt_flush_test(i915, I915_WAIT_LOCKED);	398	igt_flush_test(i915, I915_WAIT_LOCKED);
@@ -395,6 +401,18 @@ static void restore_retire_worker(struct drm_i915_private *i915) · 2 unmodified lines
395	i915_gem_shrinker_register(i915);	401	i915_gem_shrinker_register(i915);
396	}	402	}
397		403
		404	static void mmap_offset_lock(struct drm_i915_private *i915)
		405	__acquires(&i915->drm.vma_offset_manager->vm_lock)
		406	{
		407	write_lock(&i915->drm.vma_offset_manager->vm_lock);
		408	}
		409
		410	static void mmap_offset_unlock(struct drm_i915_private *i915)
		411	__releases(&i915->drm.vma_offset_manager->vm_lock)
		412	{
		413	write_unlock(&i915->drm.vma_offset_manager->vm_lock);
		414	}
		415
398	static int igt_mmap_offset_exhaustion(void *arg)	416	static int igt_mmap_offset_exhaustion(void *arg)
399	{	417	{
400	struct drm_i915_private *i915 = arg;	418	struct drm_i915_private *i915 = arg;
@@ -413,7 +431,9 @@ static int igt_mmap_offset_exhaustion(void *arg) · 12 unmodified lines
413	drm_mm_for_each_hole(hole, mm, hole_start, hole_end) {	431	drm_mm_for_each_hole(hole, mm, hole_start, hole_end) {
414	resv.start = hole_start;	432	resv.start = hole_start;
415	resv.size = hole_end - hole_start - 1; /* PAGE_SIZE units */	433	resv.size = hole_end - hole_start - 1; /* PAGE_SIZE units */
		434	mmap_offset_lock(i915);
416	err = drm_mm_reserve_node(mm, &resv);	435	err = drm_mm_reserve_node(mm, &resv);
		436	mmap_offset_unlock(i915);
417	if (err) {	437	if (err) {
418	pr_err("Failed to trim VMA manager, err=%d\n", err);	438	pr_err("Failed to trim VMA manager, err=%d\n", err);
419	goto out_park;	439	goto out_park;
@@ -458,7 +478,7 @@ static int igt_mmap_offset_exhaustion(void *arg) · 38 unmodified lines
458		478
459	/* Now fill with busy dead objects that we expect to reap */	479	/* Now fill with busy dead objects that we expect to reap */
460	for (loop = 0; loop < 3; loop++) {	480	for (loop = 0; loop < 3; loop++) {
461	if (i915_terminally_wedged(i915))	481	if (intel_gt_is_wedged(&i915->gt))
462	break;	482	break;
463		483
464	obj = i915_gem_object_create_internal(i915, PAGE_SIZE);	484	obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
@@ -474,19 +494,12 @@ static int igt_mmap_offset_exhaustion(void *arg) · 9 unmodified lines
474	pr_err("[loop %d] Failed to busy the object\n", loop);	494	pr_err("[loop %d] Failed to busy the object\n", loop);
475	goto err_obj;	495	goto err_obj;
476	}	496	}
477
478	/* NB we rely on the _active_ reference to access obj now */
479	GEM_BUG_ON(!i915_gem_object_is_active(obj));
480	err = create_mmap_offset(obj);
481	if (err) {
482	pr_err("[loop %d] create_mmap_offset failed with err=%d\n",
483	loop, err);
484	goto out;
485	}
486	}	497	}
487		498
488	out:	499	out:
		500	mmap_offset_lock(i915);
489	drm_mm_remove_node(&resv);	501	drm_mm_remove_node(&resv);
		502	mmap_offset_unlock(i915);
490	out_park:	503	out_park:
491	restore_retire_worker(i915);	504	restore_retire_worker(i915);
492	return err;	505	return err;

drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c+6−9

  * Copyright © 2019 Intel Corporation
  */
+#include "gt/intel_gt.h"
 #include "i915_selftest.h"
 #include "selftests/igt_flush_test.h"
 static int igt_fill_blt(void *arg)
 {
-	struct intel_context *ce = arg;
+	struct drm_i915_private *i915 = arg;
-	struct drm_i915_private *i915 = ce->gem_context->i915;
+	struct intel_context *ce = i915->engine[BCS0]->kernel_context;
 	struct drm_i915_gem_object *obj;
 	struct rnd_state prng;
 	IGT_TIMEOUT(end);
 err_put:
 	i915_gem_object_put(obj);
 err_flush:
-	mutex_lock(&i915->drm.struct_mutex);
-	if (igt_flush_test(i915, I915_WAIT_LOCKED))
-		err = -EIO;
-	mutex_unlock(&i915->drm.struct_mutex);
 	if (err == -ENOMEM)
 		err = 0;
 		SUBTEST(igt_fill_blt),
 	};
-	if (i915_terminally_wedged(i915))
+	if (intel_gt_is_wedged(&i915->gt))
 		return 0;
 	if (!HAS_ENGINE(i915, BCS0))
 		return 0;
-	return i915_subtests(tests, i915->engine[BCS0]->kernel_context);
+	return i915_live_subtests(tests, i915);
 }

drivers/gpu/drm/i915/gt/Makefile+4−1

@@ -1,2 +1,5 @@
		1	# For building individual subdir files on the command line
		2	subdir-ccflags-y += -I$(srctree)/$(src)/..
		3
1	# Extra header tests	4	# Extra header tests
2	include $(src)/Makefile.header-test	5	header-test-pattern-$(CONFIG_DRM_I915_WERROR) := *.h

drivers/gpu/drm/i915/gt/Makefile.header-test+0−16

@@ -1,16 +0,0 @@
1	# SPDX-License-Identifier: MIT
2	# Copyright © 2019 Intel Corporation
3
4	# Test the headers are compilable as standalone units
5	header_test := $(notdir $(wildcard $(src)/*.h))
6
7	quiet_cmd_header_test = HDRTEST $@
8	cmd_header_test = echo "\#include \"$(<F)\"" > $@
9
10	header_test_%.c: %.h
11	$(call cmd,header_test)
12
13	extra-$(CONFIG_DRM_I915_WERROR) += \
14	$(foreach h,$(header_test),$(patsubst %.h,header_test_%.o,$(h)))
15
16	clean-files += $(foreach h,$(header_test),$(patsubst %.h,header_test_%.c,$(h)))

drivers/gpu/drm/i915/gt/gen6_renderstate.crenamed from drivers/gpu/drm/i915/intel_renderstate_gen6.c+0−0

File renamed without changes.

drivers/gpu/drm/i915/gt/gen7_renderstate.crenamed from drivers/gpu/drm/i915/intel_renderstate_gen7.c+0−0

File renamed without changes.

drivers/gpu/drm/i915/gt/gen8_renderstate.crenamed from drivers/gpu/drm/i915/intel_renderstate_gen8.c+0−0

File renamed without changes.

drivers/gpu/drm/i915/gt/gen9_renderstate.crenamed from drivers/gpu/drm/i915/intel_renderstate_gen9.c+0−0

File renamed without changes.

drivers/gpu/drm/i915/gt/intel_context.c+88−35

@@ -59,6 +59,10 @@ int __intel_context_do_pin(struct intel_context *ce) · 58 unmodified lines
59	if (err)	59	if (err)
60	goto err;	60	goto err;
61		61
		62	GEM_TRACE("%s context:%llx pin ring:{head:%04x, tail:%04x}\n",
		63	ce->engine->name, ce->ring->timeline->fence_context,
		64	ce->ring->head, ce->ring->tail);
		65
62	i915_gem_context_get(ce->gem_context); /* for ctx->ppgtt */	66	i915_gem_context_get(ce->gem_context); /* for ctx->ppgtt */
63		67
64	smp_mb__before_atomic(); /* flush pin before it is visible */	68	smp_mb__before_atomic(); /* flush pin before it is visible */
@@ -85,6 +89,9 @@ void intel_context_unpin(struct intel_context *ce) · 20 unmodified lines
85	mutex_lock_nested(&ce->pin_mutex, SINGLE_DEPTH_NESTING);	89	mutex_lock_nested(&ce->pin_mutex, SINGLE_DEPTH_NESTING);
86		90
87	if (likely(atomic_dec_and_test(&ce->pin_count))) {	91	if (likely(atomic_dec_and_test(&ce->pin_count))) {
		92	GEM_TRACE("%s context:%llx retire\n",
		93	ce->engine->name, ce->ring->timeline->fence_context);
		94
88	ce->ops->unpin(ce);	95	ce->ops->unpin(ce);
89		96
90	i915_gem_context_put(ce->gem_context);	97	i915_gem_context_put(ce->gem_context);
@@ -95,11 +102,15 @@ void intel_context_unpin(struct intel_context *ce) · 4 unmodified lines
95	intel_context_put(ce);	102	intel_context_put(ce);
96	}	103	}
97		104
98	static int __context_pin_state(struct i915_vma *vma, unsigned long flags)	105	static int __context_pin_state(struct i915_vma *vma)
99	{	106	{
		107	u64 flags;
100	int err;	108	int err;
101		109
102	err = i915_vma_pin(vma, 0, 0, flags \| PIN_GLOBAL);	110	flags = i915_ggtt_pin_bias(vma) \| PIN_OFFSET_BIAS;
		111	flags \|= PIN_HIGH \| PIN_GLOBAL;
		112
		113	err = i915_vma_pin(vma, 0, 0, flags);
103	if (err)	114	if (err)
104	return err;	115	return err;
105		116
@@ -119,10 +130,13 @@ static void __context_unpin_state(struct i915_vma *vma) · 13 unmodified lines
119	__i915_vma_unpin(vma);	130	__i915_vma_unpin(vma);
120	}	131	}
121		132
122	static void intel_context_retire(struct i915_active *active)	133	static void __intel_context_retire(struct i915_active *active)
123	{	134	{
124	struct intel_context ce = container_of(active, typeof(ce), active);	135	struct intel_context ce = container_of(active, typeof(ce), active);
125		136
		137	GEM_TRACE("%s context:%llx retire\n",
		138	ce->engine->name, ce->ring->timeline->fence_context);
		139
126	if (ce->state)	140	if (ce->state)
127	__context_unpin_state(ce->state);	141	__context_unpin_state(ce->state);
128		142
@@ -130,35 +144,11 @@ static void intel_context_retire(struct i915_active *active) · 1 unmodified line
130	intel_context_put(ce);	144	intel_context_put(ce);
131	}	145	}
132		146
133	void	147	static int __intel_context_active(struct i915_active *active)
134	intel_context_init(struct intel_context *ce,
135	struct i915_gem_context *ctx,
136	struct intel_engine_cs *engine)
137	{
138	GEM_BUG_ON(!engine->cops);
139
140	kref_init(&ce->ref);
141
142	ce->gem_context = ctx;
143	ce->engine = engine;
144	ce->ops = engine->cops;
145	ce->sseu = engine->sseu;
146
147	INIT_LIST_HEAD(&ce->signal_link);
148	INIT_LIST_HEAD(&ce->signals);
149
150	mutex_init(&ce->pin_mutex);
151
152	i915_active_init(ctx->i915, &ce->active, intel_context_retire);
153	}
154
155	int intel_context_active_acquire(struct intel_context *ce, unsigned long flags)
156	{	148	{
		149	struct intel_context ce = container_of(active, typeof(ce), active);
157	int err;	150	int err;
158		151
159	if (!i915_active_acquire(&ce->active))
160	return 0;
161
162	intel_context_get(ce);	152	intel_context_get(ce);
163		153
164	err = intel_ring_pin(ce->ring);	154	err = intel_ring_pin(ce->ring);
@@ -168,7 +158,7 @@ int intel_context_active_acquire(struct intel_context *ce, unsigned long flags) · 3 unmodified lines
168	if (!ce->state)	158	if (!ce->state)
169	return 0;	159	return 0;
170		160
171	err = __context_pin_state(ce->state, flags);	161	err = __context_pin_state(ce->state);
172	if (err)	162	if (err)
173	goto err_ring;	163	goto err_ring;
174		164
@@ -188,15 +178,40 @@ err_ring: · 13 unmodified lines
188	intel_ring_unpin(ce->ring);	178	intel_ring_unpin(ce->ring);
189	err_put:	179	err_put:
190	intel_context_put(ce);	180	intel_context_put(ce);
191	i915_active_cancel(&ce->active);
192	return err;	181	return err;
193	}	182	}
194		183
195	void intel_context_active_release(struct intel_context *ce)	184	void
		185	intel_context_init(struct intel_context *ce,
		186	struct i915_gem_context *ctx,
		187	struct intel_engine_cs *engine)
		188	{
		189	GEM_BUG_ON(!engine->cops);
		190
		191	kref_init(&ce->ref);
		192
		193	ce->gem_context = ctx;
		194	ce->vm = i915_vm_get(ctx->vm ?: &engine->gt->ggtt->vm);
		195
		196	ce->engine = engine;
		197	ce->ops = engine->cops;
		198	ce->sseu = engine->sseu;
		199
		200	INIT_LIST_HEAD(&ce->signal_link);
		201	INIT_LIST_HEAD(&ce->signals);
		202
		203	mutex_init(&ce->pin_mutex);
		204
		205	i915_active_init(ctx->i915, &ce->active,
		206	__intel_context_active, __intel_context_retire);
		207	}
		208
		209	void intel_context_fini(struct intel_context *ce)
196	{	210	{
197	/* Nodes preallocated in intel_context_active() */	211	i915_vm_put(ce->vm);
198	i915_active_acquire_barrier(&ce->active);	212
199	i915_active_release(&ce->active);	213	mutex_destroy(&ce->pin_mutex);
		214	i915_active_fini(&ce->active);
200	}	215	}
201		216
202	static void i915_global_context_shrink(void)	217	static void i915_global_context_shrink(void)
@@ -234,6 +249,44 @@ void intel_context_exit_engine(struct intel_context *ce) · 31 unmodified lines
234	intel_engine_pm_put(ce->engine);	249	intel_engine_pm_put(ce->engine);
235	}	250	}
236		251
		252	int intel_context_prepare_remote_request(struct intel_context *ce,
		253	struct i915_request *rq)
		254	{
		255	struct intel_timeline *tl = ce->ring->timeline;
		256	int err;
		257
		258	/* Only suitable for use in remotely modifying this context */
		259	GEM_BUG_ON(rq->hw_context == ce);
		260
		261	if (rq->timeline != tl) { /* beware timeline sharing */
		262	err = mutex_lock_interruptible_nested(&tl->mutex,
		263	SINGLE_DEPTH_NESTING);
		264	if (err)
		265	return err;
		266
		267	/* Queue this switch after current activity by this context. */
		268	err = i915_active_request_set(&tl->last_request, rq);
		269	if (err)
		270	goto unlock;
		271	}
		272	lockdep_assert_held(&tl->mutex);
		273
		274	/*
		275	* Guarantee context image and the timeline remains pinned until the
		276	* modifying request is retired by setting the ce activity tracker.
		277	*
		278	* But we only need to take one pin on the account of it. Or in other
		279	* words transfer the pinned ce object to tracked active request.
		280	*/
		281	GEM_BUG_ON(i915_active_is_idle(&ce->active));
		282	err = i915_active_ref(&ce->active, rq->fence.context, rq);
		283
		284	unlock:
		285	if (rq->timeline != tl)
		286	mutex_unlock(&tl->mutex);
		287	return err;
		288	}
		289
237	struct i915_request intel_context_create_request(struct intel_context ce)	290	struct i915_request intel_context_create_request(struct intel_context ce)
238	{	291	{
239	struct i915_request *rq;	292	struct i915_request *rq;

drivers/gpu/drm/i915/gt/intel_context.h+16−2

 #include <linux/lockdep.h>
+#include "i915_active.h"
 #include "intel_context_types.h"
 #include "intel_engine_types.h"
 void intel_context_init(struct intel_context *ce,
 			struct i915_gem_context *ctx,
 			struct intel_engine_cs *engine);
+void intel_context_fini(struct intel_context *ce);
 struct intel_context *
 intel_context_create(struct i915_gem_context *ctx,
 		ce->ops->exit(ce);
 }
-int intel_context_active_acquire(struct intel_context *ce, unsigned long flags);
+static inline int intel_context_active_acquire(struct intel_context *ce)
-void intel_context_active_release(struct intel_context *ce);
+{
+	return i915_active_acquire(&ce->active);
+}
+static inline void intel_context_active_release(struct intel_context *ce)
+{
+	/* Nodes preallocated in intel_context_active() */
+	i915_active_acquire_barrier(&ce->active);
+	i915_active_release(&ce->active);
+}
 static inline struct intel_context *intel_context_get(struct intel_context *ce)
 {
 	mutex_unlock(&ce->ring->timeline->mutex);
 }
+int intel_context_prepare_remote_request(struct intel_context *ce,
+					 struct i915_request *rq);
 struct i915_request *intel_context_create_request(struct intel_context *ce);
 #endif /* __INTEL_CONTEXT_H__ */

drivers/gpu/drm/i915/gt/intel_context_types.h+8−1

 #include <linux/types.h>
 #include "i915_active_types.h"
+#include "i915_utils.h"
 #include "intel_engine_types.h"
 #include "intel_sseu.h"
 struct intel_context {
 	struct kref ref;
-	struct i915_gem_context *gem_context;
 	struct intel_engine_cs *engine;
 	struct intel_engine_cs *inflight;
+#define intel_context_inflight(ce) ptr_mask_bits((ce)->inflight, 2)
+#define intel_context_inflight_count(ce)  ptr_unmask_bits((ce)->inflight, 2)
+#define intel_context_inflight_inc(ce) ptr_count_inc(&(ce)->inflight)
+#define intel_context_inflight_dec(ce) ptr_count_dec(&(ce)->inflight)
+	struct i915_address_space *vm;
+	struct i915_gem_context *gem_context;
 	struct list_head signal_link;
 	struct list_head signals;

drivers/gpu/drm/i915/gt/intel_engine.h+15−60

 #include "i915_reg.h"
 #include "i915_request.h"
 #include "i915_selftest.h"
-#include "i915_timeline.h"
+#include "gt/intel_timeline.h"
 #include "intel_engine_types.h"
 #include "intel_gpu_commands.h"
 #include "intel_workarounds.h"
 #define ENGINE_READ16(...)	__ENGINE_READ_OP(read16, __VA_ARGS__)
 #define ENGINE_READ(...)	__ENGINE_READ_OP(read, __VA_ARGS__)
 #define ENGINE_READ_FW(...)	__ENGINE_READ_OP(read_fw, __VA_ARGS__)
-#define ENGINE_POSTING_READ(...) __ENGINE_READ_OP(posting_read, __VA_ARGS__)
+#define ENGINE_POSTING_READ(...) __ENGINE_READ_OP(posting_read_fw, __VA_ARGS__)
 #define ENGINE_POSTING_READ16(...) __ENGINE_READ_OP(posting_read16, __VA_ARGS__)
 #define ENGINE_READ64(engine__, lower_reg__, upper_reg__) \
 void intel_engines_set_scheduler_caps(struct drm_i915_private *i915);
-static inline void
+static inline unsigned int
-execlists_set_active(struct intel_engine_execlists *execlists,
+execlists_num_ports(const struct intel_engine_execlists * const execlists)
-		     unsigned int bit)
-{
-	__set_bit(bit, (unsigned long *)&execlists->active);
-}
-static inline bool
-execlists_set_active_once(struct intel_engine_execlists *execlists,
-			  unsigned int bit)
-{
-	return !__test_and_set_bit(bit, (unsigned long *)&execlists->active);
-}
-static inline void
-execlists_clear_active(struct intel_engine_execlists *execlists,
-		       unsigned int bit)
-{
-	__clear_bit(bit, (unsigned long *)&execlists->active);
-}
-static inline void
-execlists_clear_all_active(struct intel_engine_execlists *execlists)
 {
-	execlists->active = 0;
+	return execlists->port_mask + 1;
 }
-static inline bool
+static inline struct i915_request *
-execlists_is_active(const struct intel_engine_execlists *execlists,
+execlists_active(const struct intel_engine_execlists *execlists)
-		    unsigned int bit)
 {
-	return test_bit(bit, (unsigned long *)&execlists->active);
+	GEM_BUG_ON(execlists->active - execlists->inflight >
+		   execlists_num_ports(execlists));
+	return READ_ONCE(*execlists->active);
 }
-void execlists_user_begin(struct intel_engine_execlists *execlists,
-			  const struct execlist_port *port);
-void execlists_user_end(struct intel_engine_execlists *execlists);
 void
 execlists_cancel_port_requests(struct intel_engine_execlists * const execlists);
 struct i915_request *
 execlists_unwind_incomplete_requests(struct intel_engine_execlists *execlists);
-static inline unsigned int
-execlists_num_ports(const struct intel_engine_execlists * const execlists)
-{
-	return execlists->port_mask + 1;
-}
-static inline struct execlist_port *
-execlists_port_complete(struct intel_engine_execlists * const execlists,
-			struct execlist_port * const port)
-{
-	const unsigned int m = execlists->port_mask;
-	GEM_BUG_ON(port_index(port, execlists) != 0);
-	GEM_BUG_ON(!execlists_is_active(execlists, EXECLISTS_ACTIVE_USER));
-	memmove(port, port + 1, m * sizeof(struct execlist_port));
-	memset(port + m, 0, sizeof(struct execlist_port));
-	return port;
-}
 static inline u32
 intel_read_status_page(const struct intel_engine_cs *engine, int reg)
 {
 struct intel_ring *
 intel_engine_create_ring(struct intel_engine_cs *engine,
-			 struct i915_timeline *timeline,
+			 struct intel_timeline *timeline,
 			 int size);
 int intel_ring_pin(struct intel_ring *ring);
 void intel_ring_reset(struct intel_ring *ring, u32 tail);
 	return cs;
 }
-static inline void intel_engine_reset(struct intel_engine_cs *engine,
+static inline void __intel_engine_reset(struct intel_engine_cs *engine,
-				      bool stalled)
+					bool stalled)
 {
 	if (engine->reset.reset)
 		engine->reset.reset(engine, stalled);
 }
 bool intel_engine_is_idle(struct intel_engine_cs *engine);
-bool intel_engines_are_idle(struct drm_i915_private *dev_priv);
+bool intel_engines_are_idle(struct intel_gt *gt);
-void intel_engines_reset_default_submission(struct drm_i915_private *i915);
+void intel_engines_reset_default_submission(struct intel_gt *gt);
 unsigned int intel_engines_has_context_isolation(struct drm_i915_private *i915);
 bool intel_engine_can_store_dword(struct intel_engine_cs *engine);

drivers/gpu/drm/i915/gt/intel_engine_cs.c+85−118

@@ -28,6 +28,8 @@ · 27 unmodified lines
28		28
29	#include "i915_drv.h"	29	#include "i915_drv.h"
30		30
		31	#include "gt/intel_gt.h"
		32
31	#include "intel_engine.h"	33	#include "intel_engine.h"
32	#include "intel_engine_pm.h"	34	#include "intel_engine_pm.h"
33	#include "intel_context.h"	35	#include "intel_context.h"
@@ -314,6 +316,7 @@ intel_engine_setup(struct drm_i915_private *dev_priv, · 280 unmodified lines
314	engine->id = id;	316	engine->id = id;
315	engine->mask = BIT(id);	317	engine->mask = BIT(id);
316	engine->i915 = dev_priv;	318	engine->i915 = dev_priv;
		319	engine->gt = &dev_priv->gt;
317	engine->uncore = &dev_priv->uncore;	320	engine->uncore = &dev_priv->uncore;
318	__sprint_engine_name(engine->name, info);	321	__sprint_engine_name(engine->name, info);
319	engine->hw_id = engine->guc_id = info->hw_id;	322	engine->hw_id = engine->guc_id = info->hw_id;
@@ -423,7 +426,7 @@ int intel_engines_init_mmio(struct drm_i915_private *i915) · 103 unmodified lines
423	WARN_ON(engine_mask &	426	WARN_ON(engine_mask &
424	GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES));	427	GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES));
425		428
426	if (i915_inject_load_failure())	429	if (i915_inject_probe_failure())
427	return -ENODEV;	430	return -ENODEV;
428		431
429	for (i = 0; i < ARRAY_SIZE(intel_engines); i++) {	432	for (i = 0; i < ARRAY_SIZE(intel_engines); i++) {
@@ -445,15 +448,9 @@ int intel_engines_init_mmio(struct drm_i915_private *i915) · 15 unmodified lines
445	if (WARN_ON(mask != engine_mask))	448	if (WARN_ON(mask != engine_mask))
446	device_info->engine_mask = mask;	449	device_info->engine_mask = mask;
447		450
448	/* We always presume we have at least RCS available for later probing */
449	if (WARN_ON(!HAS_ENGINE(i915, RCS0))) {
450	err = -ENODEV;
451	goto cleanup;
452	}
453
454	RUNTIME_INFO(i915)->num_engines = hweight32(mask);	451	RUNTIME_INFO(i915)->num_engines = hweight32(mask);
455		452
456	i915_check_and_clear_faults(i915);	453	intel_gt_check_and_clear_faults(&i915->gt);
457		454
458	intel_setup_engine_capabilities(i915);	455	intel_setup_engine_capabilities(i915);
459		456
@@ -508,6 +505,10 @@ void intel_engine_init_execlists(struct intel_engine_cs *engine) · 48 unmodified lines
508	GEM_BUG_ON(!is_power_of_2(execlists_num_ports(execlists)));	505	GEM_BUG_ON(!is_power_of_2(execlists_num_ports(execlists)));
509	GEM_BUG_ON(execlists_num_ports(execlists) > EXECLIST_MAX_PORTS);	506	GEM_BUG_ON(execlists_num_ports(execlists) > EXECLIST_MAX_PORTS);
510		507
		508	memset(execlists->pending, 0, sizeof(execlists->pending));
		509	execlists->active =
		510	memset(execlists->inflight, 0, sizeof(execlists->inflight));
		511
511	execlists->queue_priority_hint = INT_MIN;	512	execlists->queue_priority_hint = INT_MIN;
512	execlists->queue = RB_ROOT_CACHED;	513	execlists->queue = RB_ROOT_CACHED;
513	}	514	}
@@ -577,7 +578,7 @@ static int init_status_page(struct intel_engine_cs *engine) · 63 unmodified lines
577		578
578	i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC);	579	i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC);
579		580
580	vma = i915_vma_instance(obj, &engine->i915->ggtt.vm, NULL);	581	vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
581	if (IS_ERR(vma)) {	582	if (IS_ERR(vma)) {
582	ret = PTR_ERR(vma);	583	ret = PTR_ERR(vma);
583	goto err;	584	goto err;
@@ -629,6 +630,10 @@ static int intel_engine_setup_common(struct intel_engine_cs *engine) · 45 unmodified lines
629	engine->sseu =	630	engine->sseu =
630	intel_sseu_from_device_info(&RUNTIME_INFO(engine->i915)->sseu);	631	intel_sseu_from_device_info(&RUNTIME_INFO(engine->i915)->sseu);
631		632
		633	intel_engine_init_workarounds(engine);
		634	intel_engine_init_whitelist(engine);
		635	intel_engine_init_ctx_wa(engine);
		636
632	return 0;	637	return 0;
633	}	638	}
634		639
@@ -681,9 +686,10 @@ void intel_engines_set_scheduler_caps(struct drm_i915_private *i915) · 46 unmodified lines
681	u8 engine;	686	u8 engine;
682	u8 sched;	687	u8 sched;
683	} map[] = {	688	} map[] = {
684	#define MAP(x, y) { ilog2(I915_ENGINE_HAS_##x), ilog2(I915_SCHEDULER_CAP_##y) }	689	#define MAP(x, y) { ilog2(I915_ENGINE_##x), ilog2(I915_SCHEDULER_CAP_##y) }
685	MAP(PREEMPTION, PREEMPTION),	690	MAP(HAS_PREEMPTION, PREEMPTION),
686	MAP(SEMAPHORES, SEMAPHORES),	691	MAP(HAS_SEMAPHORES, SEMAPHORES),
		692	MAP(SUPPORTS_STATS, ENGINE_BUSY_STATS),
687	#undef MAP	693	#undef MAP
688	};	694	};
689	struct intel_engine_cs *engine;	695	struct intel_engine_cs *engine;
@@ -717,7 +723,7 @@ void intel_engines_set_scheduler_caps(struct drm_i915_private *i915) · 27 unmodified lines
717		723
718	struct measure_breadcrumb {	724	struct measure_breadcrumb {
719	struct i915_request rq;	725	struct i915_request rq;
720	struct i915_timeline timeline;	726	struct intel_timeline timeline;
721	struct intel_ring ring;	727	struct intel_ring ring;
722	u32 cs[1024];	728	u32 cs[1024];
723	};	729	};
@@ -727,15 +733,15 @@ static int measure_breadcrumb_dw(struct intel_engine_cs *engine) · 3 unmodified lines
727	struct measure_breadcrumb *frame;	733	struct measure_breadcrumb *frame;
728	int dw = -ENOMEM;	734	int dw = -ENOMEM;
729		735
730	GEM_BUG_ON(!engine->i915->gt.scratch);	736	GEM_BUG_ON(!engine->gt->scratch);
731		737
732	frame = kzalloc(sizeof(*frame), GFP_KERNEL);	738	frame = kzalloc(sizeof(*frame), GFP_KERNEL);
733	if (!frame)	739	if (!frame)
734	return -ENOMEM;	740	return -ENOMEM;
735		741
736	if (i915_timeline_init(engine->i915,	742	if (intel_timeline_init(&frame->timeline,
737	&frame->timeline,	743	engine->gt,
738	engine->status_page.vma))	744	engine->status_page.vma))
739	goto out_frame;	745	goto out_frame;
740		746
741	INIT_LIST_HEAD(&frame->ring.request_list);	747	INIT_LIST_HEAD(&frame->ring.request_list);
@@ -750,17 +756,17 @@ static int measure_breadcrumb_dw(struct intel_engine_cs *engine) · 8 unmodified lines
750	frame->rq.ring = &frame->ring;	756	frame->rq.ring = &frame->ring;
751	frame->rq.timeline = &frame->timeline;	757	frame->rq.timeline = &frame->timeline;
752		758
753	dw = i915_timeline_pin(&frame->timeline);	759	dw = intel_timeline_pin(&frame->timeline);
754	if (dw < 0)	760	if (dw < 0)
755	goto out_timeline;	761	goto out_timeline;
756		762
757	dw = engine->emit_fini_breadcrumb(&frame->rq, frame->cs) - frame->cs;	763	dw = engine->emit_fini_breadcrumb(&frame->rq, frame->cs) - frame->cs;
758	GEM_BUG_ON(dw & 1); /* RING_TAIL must be qword aligned */	764	GEM_BUG_ON(dw & 1); /* RING_TAIL must be qword aligned */
759		765
760	i915_timeline_unpin(&frame->timeline);	766	intel_timeline_unpin(&frame->timeline);
761		767
762	out_timeline:	768	out_timeline:
763	i915_timeline_fini(&frame->timeline);	769	intel_timeline_fini(&frame->timeline);
764	out_frame:	770	out_frame:
765	kfree(frame);	771	kfree(frame);
766	return dw;	772	return dw;
@@ -823,6 +829,8 @@ int intel_engine_init_common(struct intel_engine_cs *engine) · 56 unmodified lines
823	struct drm_i915_private *i915 = engine->i915;	829	struct drm_i915_private *i915 = engine->i915;
824	int ret;	830	int ret;
825		831
		832	engine->set_default_submission(engine);
		833
826	/* We may need to do things with the shrinker which	834	/* We may need to do things with the shrinker which
827	* require us to immediately switch back to the default	835	* require us to immediately switch back to the default
828	* context. This can cause a problem as pinning the	836	* context. This can cause a problem as pinning the
@@ -835,28 +843,15 @@ int intel_engine_init_common(struct intel_engine_cs *engine) · 6 unmodified lines
835	if (ret)	843	if (ret)
836	return ret;	844	return ret;
837		845
838	/*
839	* Similarly the preempt context must always be available so that
840	* we can interrupt the engine at any time. However, as preemption
841	* is optional, we allow it to fail.
842	*/
843	if (i915->preempt_context)
844	pin_context(i915->preempt_context, engine,
845	&engine->preempt_context);
846
847	ret = measure_breadcrumb_dw(engine);	846	ret = measure_breadcrumb_dw(engine);
848	if (ret < 0)	847	if (ret < 0)
849	goto err_unpin;	848	goto err_unpin;
850		849
851	engine->emit_fini_breadcrumb_dw = ret;	850	engine->emit_fini_breadcrumb_dw = ret;
852		851
853	engine->set_default_submission(engine);
854
855	return 0;	852	return 0;
856		853
857	err_unpin:	854	err_unpin:
858	if (engine->preempt_context)
859	intel_context_unpin(engine->preempt_context);
860	intel_context_unpin(engine->kernel_context);	855	intel_context_unpin(engine->kernel_context);
861	return ret;	856	return ret;
862	}	857	}
@@ -881,8 +876,6 @@ void intel_engine_cleanup_common(struct intel_engine_cs *engine) · 18 unmodified lines
881	if (engine->default_state)	876	if (engine->default_state)
882	i915_gem_object_put(engine->default_state);	877	i915_gem_object_put(engine->default_state);
883		878
884	if (engine->preempt_context)
885	intel_context_unpin(engine->preempt_context);
886	intel_context_unpin(engine->kernel_context);	879	intel_context_unpin(engine->kernel_context);
887	GEM_BUG_ON(!llist_empty(&engine->barrier_tasks));	880	GEM_BUG_ON(!llist_empty(&engine->barrier_tasks));
888		881
@@ -966,57 +959,23 @@ const char i915_cache_level_str(struct drm_i915_private i915, int type) · 77 unmodified lines
966	}	959	}
967	}	960	}
968		961
969	u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv)
970	{
971	const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
972	unsigned int slice = fls(sseu->slice_mask) - 1;
973	unsigned int subslice;
974	u32 mcr_s_ss_select;
975
976	GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
977	subslice = fls(sseu->subslice_mask[slice]);
978	GEM_BUG_ON(!subslice);
979	subslice--;
980
981	if (IS_GEN(dev_priv, 10))
982	mcr_s_ss_select = GEN8_MCR_SLICE(slice) \|
983	GEN8_MCR_SUBSLICE(subslice);
984	else if (INTEL_GEN(dev_priv) >= 11)
985	mcr_s_ss_select = GEN11_MCR_SLICE(slice) \|
986	GEN11_MCR_SUBSLICE(subslice);
987	else
988	mcr_s_ss_select = 0;
989
990	return mcr_s_ss_select;
991	}
992
993	static u32	962	static u32
994	read_subslice_reg(struct intel_engine_cs *engine, int slice, int subslice,	963	read_subslice_reg(struct intel_engine_cs *engine, int slice, int subslice,
995	i915_reg_t reg)	964	i915_reg_t reg)
996	{	965	{
997	struct drm_i915_private *i915 = engine->i915;	966	struct drm_i915_private *i915 = engine->i915;
998	struct intel_uncore *uncore = engine->uncore;	967	struct intel_uncore *uncore = engine->uncore;
999	u32 mcr_slice_subslice_mask;	968	u32 mcr_mask, mcr_ss, mcr, old_mcr, val;
1000	u32 mcr_slice_subslice_select;
1001	u32 default_mcr_s_ss_select;
1002	u32 mcr;
1003	u32 ret;
1004	enum forcewake_domains fw_domains;	969	enum forcewake_domains fw_domains;
1005		970
1006	if (INTEL_GEN(i915) >= 11) {	971	if (INTEL_GEN(i915) >= 11) {
1007	mcr_slice_subslice_mask = GEN11_MCR_SLICE_MASK \|	972	mcr_mask = GEN11_MCR_SLICE_MASK \| GEN11_MCR_SUBSLICE_MASK;
1008	GEN11_MCR_SUBSLICE_MASK;	973	mcr_ss = GEN11_MCR_SLICE(slice) \| GEN11_MCR_SUBSLICE(subslice);
1009	mcr_slice_subslice_select = GEN11_MCR_SLICE(slice) \|
1010	GEN11_MCR_SUBSLICE(subslice);
1011	} else {	974	} else {
1012	mcr_slice_subslice_mask = GEN8_MCR_SLICE_MASK \|	975	mcr_mask = GEN8_MCR_SLICE_MASK \| GEN8_MCR_SUBSLICE_MASK;
1013	GEN8_MCR_SUBSLICE_MASK;	976	mcr_ss = GEN8_MCR_SLICE(slice) \| GEN8_MCR_SUBSLICE(subslice);
1014	mcr_slice_subslice_select = GEN8_MCR_SLICE(slice) \|
1015	GEN8_MCR_SUBSLICE(subslice);
1016	}	977	}
1017		978
1018	default_mcr_s_ss_select = intel_calculate_mcr_s_ss_select(i915);
1019
1020	fw_domains = intel_uncore_forcewake_for_reg(uncore, reg,	979	fw_domains = intel_uncore_forcewake_for_reg(uncore, reg,
1021	FW_REG_READ);	980	FW_REG_READ);
1022	fw_domains \|= intel_uncore_forcewake_for_reg(uncore,	981	fw_domains \|= intel_uncore_forcewake_for_reg(uncore,
@@ -1026,26 +985,23 @@ read_subslice_reg(struct intel_engine_cs *engine, int slice, int subslice, · 3 unmodified lines
1026	spin_lock_irq(&uncore->lock);	985	spin_lock_irq(&uncore->lock);
1027	intel_uncore_forcewake_get__locked(uncore, fw_domains);	986	intel_uncore_forcewake_get__locked(uncore, fw_domains);
1028		987
1029	mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR);	988	old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR);
1030
1031	WARN_ON_ONCE((mcr & mcr_slice_subslice_mask) !=
1032	default_mcr_s_ss_select);
1033		989
1034	mcr &= ~mcr_slice_subslice_mask;	990	mcr &= ~mcr_mask;
1035	mcr \|= mcr_slice_subslice_select;	991	mcr \|= mcr_ss;
1036	intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);	992	intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
1037		993
1038	ret = intel_uncore_read_fw(uncore, reg);	994	val = intel_uncore_read_fw(uncore, reg);
1039		995
1040	mcr &= ~mcr_slice_subslice_mask;	996	mcr &= ~mcr_mask;
1041	mcr \|= default_mcr_s_ss_select;	997	mcr \|= old_mcr & mcr_mask;
1042		998
1043	intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);	999	intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
1044		1000
1045	intel_uncore_forcewake_put__locked(uncore, fw_domains);	1001	intel_uncore_forcewake_put__locked(uncore, fw_domains);
1046	spin_unlock_irq(&uncore->lock);	1002	spin_unlock_irq(&uncore->lock);
1047		1003
1048	return ret;	1004	return val;
1049	}	1005	}
1050		1006
1051	/* NB: please notice the memset */	1007	/* NB: please notice the memset */
@@ -1150,17 +1106,17 @@ static bool ring_is_idle(struct intel_engine_cs *engine) · 98 unmodified lines
1150	bool intel_engine_is_idle(struct intel_engine_cs *engine)	1106	bool intel_engine_is_idle(struct intel_engine_cs *engine)
1151	{	1107	{
1152	/* More white lies, if wedged, hw state is inconsistent */	1108	/* More white lies, if wedged, hw state is inconsistent */
1153	if (i915_reset_failed(engine->i915))	1109	if (intel_gt_is_wedged(engine->gt))
1154	return true;	1110	return true;
1155		1111
1156	if (!intel_wakeref_active(&engine->wakeref))	1112	if (!intel_engine_pm_is_awake(engine))
1157	return true;	1113	return true;
1158		1114
1159	/* Waiting to drain ELSP? */	1115	/* Waiting to drain ELSP? */
1160	if (READ_ONCE(engine->execlists.active)) {	1116	if (execlists_active(&engine->execlists)) {
1161	struct tasklet_struct *t = &engine->execlists.tasklet;	1117	struct tasklet_struct *t = &engine->execlists.tasklet;
1162		1118
1163	synchronize_hardirq(engine->i915->drm.irq);	1119	synchronize_hardirq(engine->i915->drm.pdev->irq);
1164		1120
1165	local_bh_disable();	1121	local_bh_disable();
1166	if (tasklet_trylock(t)) {	1122	if (tasklet_trylock(t)) {
@@ -1174,7 +1130,7 @@ bool intel_engine_is_idle(struct intel_engine_cs *engine) · 7 unmodified lines
1174	/* Otherwise flush the tasklet if it was on another cpu */	1130	/* Otherwise flush the tasklet if it was on another cpu */
1175	tasklet_unlock_wait(t);	1131	tasklet_unlock_wait(t);
1176		1132
1177	if (READ_ONCE(engine->execlists.active))	1133	if (execlists_active(&engine->execlists))
1178	return false;	1134	return false;
1179	}	1135	}
1180		1136
@@ -1186,7 +1142,7 @@ bool intel_engine_is_idle(struct intel_engine_cs *engine) · 5 unmodified lines
1186	return ring_is_idle(engine);	1142	return ring_is_idle(engine);
1187	}	1143	}
1188		1144
1189	bool intel_engines_are_idle(struct drm_i915_private *i915)	1145	bool intel_engines_are_idle(struct intel_gt *gt)
1190	{	1146	{
1191	struct intel_engine_cs *engine;	1147	struct intel_engine_cs *engine;
1192	enum intel_engine_id id;	1148	enum intel_engine_id id;
@@ -1195,14 +1151,14 @@ bool intel_engines_are_idle(struct drm_i915_private *i915) · 2 unmodified lines
1195	* If the driver is wedged, HW state may be very inconsistent and	1151	* If the driver is wedged, HW state may be very inconsistent and
1196	* report that it is still busy, even though we have stopped using it.	1152	* report that it is still busy, even though we have stopped using it.
1197	*/	1153	*/
1198	if (i915_reset_failed(i915))	1154	if (intel_gt_is_wedged(gt))
1199	return true;	1155	return true;
1200		1156
1201	/* Already parked (and passed an idleness test); must still be idle */	1157	/* Already parked (and passed an idleness test); must still be idle */
1202	if (!READ_ONCE(i915->gt.awake))	1158	if (!READ_ONCE(gt->awake))
1203	return true;	1159	return true;
1204		1160
1205	for_each_engine(engine, i915, id) {	1161	for_each_engine(engine, gt->i915, id) {
1206	if (!intel_engine_is_idle(engine))	1162	if (!intel_engine_is_idle(engine))
1207	return false;	1163	return false;
1208	}	1164	}
@@ -1210,12 +1166,12 @@ bool intel_engines_are_idle(struct drm_i915_private *i915) · 1 unmodified line
1210	return true;	1166	return true;
1211	}	1167	}
1212		1168
1213	void intel_engines_reset_default_submission(struct drm_i915_private *i915)	1169	void intel_engines_reset_default_submission(struct intel_gt *gt)
1214	{	1170	{
1215	struct intel_engine_cs *engine;	1171	struct intel_engine_cs *engine;
1216	enum intel_engine_id id;	1172	enum intel_engine_id id;
1217		1173
1218	for_each_engine(engine, i915, id)	1174	for_each_engine(engine, gt->i915, id)
1219	engine->set_default_submission(engine);	1175	engine->set_default_submission(engine);
1220	}	1176	}
1221		1177
@@ -1372,6 +1328,7 @@ static void intel_engine_print_registers(struct intel_engine_cs *engine, · 150 unmodified lines
1372	}	1328	}
1373		1329
1374	if (HAS_EXECLISTS(dev_priv)) {	1330	if (HAS_EXECLISTS(dev_priv)) {
		1331	struct i915_request * const port, rq;
1375	const u32 *hws =	1332	const u32 *hws =
1376	&engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX];	1333	&engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX];
1377	const u8 num_entries = execlists->csb_size;	1334	const u8 num_entries = execlists->csb_size;
@@ -1404,27 +1361,33 @@ static void intel_engine_print_registers(struct intel_engine_cs *engine, · 26 unmodified lines
1404	}	1361	}
1405		1362
1406	spin_lock_irqsave(&engine->active.lock, flags);	1363	spin_lock_irqsave(&engine->active.lock, flags);
1407	for (idx = 0; idx < execlists_num_ports(execlists); idx++) {	1364	for (port = execlists->active; (rq = *port); port++) {
1408	struct i915_request *rq;	1365	char hdr[80];
1409	unsigned int count;	1366	int len;
		1367
		1368	len = snprintf(hdr, sizeof(hdr),
		1369	"\t\tActive[%d: ",
		1370	(int)(port - execlists->active));
		1371	if (!i915_request_signaled(rq))
		1372	len += snprintf(hdr + len, sizeof(hdr) - len,
		1373	"ring:{start:%08x, hwsp:%08x, seqno:%08x}, ",
		1374	i915_ggtt_offset(rq->ring->vma),
		1375	rq->timeline->hwsp_offset,
		1376	hwsp_seqno(rq));
		1377	snprintf(hdr + len, sizeof(hdr) - len, "rq: ");
		1378	print_request(m, rq, hdr);
		1379	}
		1380	for (port = execlists->pending; (rq = *port); port++) {
1410	char hdr[80];	1381	char hdr[80];
1411		1382
1412	rq = port_unpack(&execlists->port[idx], &count);	1383	snprintf(hdr, sizeof(hdr),
1413	if (!rq) {	1384	"\t\tPending[%d] ring:{start:%08x, hwsp:%08x, seqno:%08x}, rq: ",
1414	drm_printf(m, "\t\tELSP[%d] idle\n", idx);	1385	(int)(port - execlists->pending),
1415	} else if (!i915_request_signaled(rq)) {	1386	i915_ggtt_offset(rq->ring->vma),
1416	snprintf(hdr, sizeof(hdr),	1387	rq->timeline->hwsp_offset,
1417	"\t\tELSP[%d] count=%d, ring:{start:%08x, hwsp:%08x, seqno:%08x}, rq: ",	1388	hwsp_seqno(rq));
1418	idx, count,	1389	print_request(m, rq, hdr);
1419	i915_ggtt_offset(rq->ring->vma),
1420	rq->timeline->hwsp_offset,
1421	hwsp_seqno(rq));
1422	print_request(m, rq, hdr);
1423	} else {
1424	print_request(m, rq, "\t\tELSP[%d] rq: ");
1425	}
1426	}	1390	}
1427	drm_printf(m, "\t\tHW active? 0x%x\n", execlists->active);
1428	spin_unlock_irqrestore(&engine->active.lock, flags);	1391	spin_unlock_irqrestore(&engine->active.lock, flags);
1429	} else if (INTEL_GEN(dev_priv) > 6) {	1392	} else if (INTEL_GEN(dev_priv) > 6) {
1430	drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n",	1393	drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
@@ -1486,7 +1449,7 @@ void intel_engine_dump(struct intel_engine_cs *engine, · 55 unmodified lines
1486	va_end(ap);	1449	va_end(ap);
1487	}	1450	}
1488		1451
1489	if (i915_reset_failed(engine->i915))	1452	if (intel_gt_is_wedged(engine->gt))
1490	drm_printf(m, "* WEDGED *\n");	1453	drm_printf(m, "* WEDGED *\n");
1491		1454
1492	drm_printf(m, "\tAwake? %d\n", atomic_read(&engine->wakeref.count));	1455	drm_printf(m, "\tAwake? %d\n", atomic_read(&engine->wakeref.count));
@@ -1587,15 +1550,19 @@ int intel_enable_engine_stats(struct intel_engine_cs *engine) · 94 unmodified lines
1587	}	1550	}
1588		1551
1589	if (engine->stats.enabled++ == 0) {	1552	if (engine->stats.enabled++ == 0) {
1590	const struct execlist_port *port = execlists->port;	1553	struct i915_request * const *port;
1591	unsigned int num_ports = execlists_num_ports(execlists);	1554	struct i915_request *rq;
1592		1555
1593	engine->stats.enabled_at = ktime_get();	1556	engine->stats.enabled_at = ktime_get();
1594		1557
1595	/* XXX submission method oblivious? */	1558	/* XXX submission method oblivious? */
1596	while (num_ports-- && port_isset(port)) {	1559	for (port = execlists->active; (rq = *port); port++)
1597	engine->stats.active++;	1560	engine->stats.active++;
1598	port++;	1561
		1562	for (port = execlists->pending; (rq = *port); port++) {
		1563	/* Exclude any contexts already counted in active */
		1564	if (intel_context_inflight_count(rq->hw_context) == 1)
		1565	engine->stats.active++;
1599	}	1566	}
1600		1567
1601	if (engine->stats.active)	1568	if (engine->stats.active)

drivers/gpu/drm/i915/gt/intel_engine_pm.c+4−3

 #include "intel_engine.h"
 #include "intel_engine_pm.h"
+#include "intel_gt.h"
 #include "intel_gt_pm.h"
 static int __engine_unpark(struct intel_wakeref *wf)
 	GEM_TRACE("%s\n", engine->name);
-	intel_gt_pm_get(engine->i915);
+	intel_gt_pm_get(engine->gt);
 	/* Pin the default state for fast resets from atomic context. */
 	map = NULL;
 		return true;
 	/* GPU is pointing to the void, as good as in the kernel context. */
-	if (i915_reset_failed(engine->i915))
+	if (intel_gt_is_wedged(engine->gt))
 		return true;
 	/*
 	engine->execlists.no_priolist = false;
-	intel_gt_pm_put(engine->i915);
+	intel_gt_pm_put(engine->gt);
 	return 0;
 }

drivers/gpu/drm/i915/gt/intel_engine_pm.h+6−0

 void intel_engine_pm_get(struct intel_engine_cs *engine);
 void intel_engine_pm_put(struct intel_engine_cs *engine);
+static inline bool
+intel_engine_pm_is_awake(const struct intel_engine_cs *engine)
+{
+	return intel_wakeref_is_active(&engine->wakeref);
+}
 static inline bool
 intel_engine_pm_get_if_awake(struct intel_engine_cs *engine)
 {

drivers/gpu/drm/i915/gt/intel_engine_types.h+26−48

 #include <linux/kref.h>
 #include <linux/list.h>
 #include <linux/llist.h>
+#include <linux/timer.h>
 #include <linux/types.h>
 #include "i915_gem.h"
 #include "i915_pmu.h"
 #include "i915_priolist_types.h"
 #include "i915_selftest.h"
-#include "i915_timeline_types.h"
+#include "gt/intel_timeline_types.h"
 #include "intel_sseu.h"
 #include "intel_wakeref.h"
 #include "intel_workarounds_types.h"
 struct i915_gem_context;
 struct i915_request;
 struct i915_sched_attr;
+struct intel_gt;
 struct intel_uncore;
 typedef u8 intel_engine_mask_t;
 	struct i915_vma *vma;
 	void *vaddr;
-	struct i915_timeline *timeline;
+	struct intel_timeline *timeline;
 	struct list_head request_list;
 	struct list_head active_link;
 	 */
 	struct tasklet_struct tasklet;
+	/**
+	 * @timer: kick the current context if its timeslice expires
+	 */
+	struct timer_list timer;
 	/**
 	 * @default_priolist: priority list for I915_PRIORITY_NORMAL
 	 */
 	 */
 	u32 __iomem *ctrl_reg;
+#define EXECLIST_MAX_PORTS 2
 	/**
-	 * @port: execlist port states
+	 * @active: the currently known context executing on HW
+	 */
+	struct i915_request * const *active;
+	/**
+	 * @inflight: the set of contexts submitted and acknowleged by HW
 	 *
-	 * For each hardware ELSP (ExecList Submission Port) we keep
+	 * The set of inflight contexts is managed by reading CS events
-	 * track of the last request and the number of times we submitted
+	 * from the HW. On a context-switch event (not preemption), we
-	 * that port to hw. We then count the number of times the hw reports
+	 * know the HW has transitioned from port0 to port1, and we
-	 * a context completion or preemption. As only one context can
+	 * advance our inflight/active tracking accordingly.
-	 * be active on hw, we limit resubmission of context to port[0]. This
-	 * is called Lite Restore, of the context.
 	 */
-	struct execlist_port {
+	struct i915_request *inflight[EXECLIST_MAX_PORTS + 1 /* sentinel */];
-		/**
-		 * @request_count: combined request and submission count
-		 */
-		struct i915_request *request_count;
-#define EXECLIST_COUNT_BITS 2
-#define port_request(p) ptr_mask_bits((p)->request_count, EXECLIST_COUNT_BITS)
-#define port_count(p) ptr_unmask_bits((p)->request_count, EXECLIST_COUNT_BITS)
-#define port_pack(rq, count) ptr_pack_bits(rq, count, EXECLIST_COUNT_BITS)
-#define port_unpack(p, count) ptr_unpack_bits((p)->request_count, count, EXECLIST_COUNT_BITS)
-#define port_set(p, packed) ((p)->request_count = (packed))
-#define port_isset(p) ((p)->request_count)
-#define port_index(p, execlists) ((p) - (execlists)->port)
-		/**
-		 * @context_id: context ID for port
-		 */
-		GEM_DEBUG_DECL(u32 context_id);
-#define EXECLIST_MAX_PORTS 2
-	} port[EXECLIST_MAX_PORTS];
 	/**
-	 * @active: is the HW active? We consider the HW as active after
+	 * @pending: the next set of contexts submitted to ELSP
-	 * submitting any context for execution and until we have seen the
-	 * last context completion event. After that, we do not expect any
-	 * more events until we submit, and so can park the HW.
 	 *
-	 * As we have a small number of different sources from which we feed
+	 * We store the array of contexts that we submit to HW (via ELSP) and
-	 * the HW, we track the state of each inside a single bitfield.
+	 * promote them to the inflight array once HW has signaled the
+	 * preemption or idle-to-active event.
 	 */
-	unsigned int active;
+	struct i915_request *pending[EXECLIST_MAX_PORTS + 1];
-#define EXECLISTS_ACTIVE_USER 0
-#define EXECLISTS_ACTIVE_PREEMPT 1
-#define EXECLISTS_ACTIVE_HWACK 2
 	/**
 	 * @port_mask: number of execlist ports - 1
 	 */
 	u32 *csb_status;
-	/**
-	 * @preempt_complete_status: expected CSB upon completing preemption
-	 */
-	u32 preempt_complete_status;
 	/**
 	 * @csb_size: context status buffer FIFO size
 	 */
 struct intel_engine_cs {
 	struct drm_i915_private *i915;
+	struct intel_gt *gt;
 	struct intel_uncore *uncore;
 	char name[INTEL_ENGINE_CS_MAX_NAME];
 	struct llist_head barrier_tasks;
 	struct intel_context *kernel_context; /* pinned */
-	struct intel_context *preempt_context; /* pinned; optional */
 	intel_engine_mask_t saturated; /* submitting semaphores too late? */
 	const struct intel_context_ops *cops;
 	int		(*request_alloc)(struct i915_request *rq);
-	int		(*init_context)(struct i915_request *rq);
 	int		(*emit_flush)(struct i915_request *request, u32 mode);
 #define EMIT_INVALIDATE	BIT(0)

drivers/gpu/drm/i915/gt/intel_gpu_commands.h+7−0

@@ -7,6 +7,13 @@ · 6 unmodified lines
7	#ifndef _INTEL_GPU_COMMANDS_H_	7	#ifndef _INTEL_GPU_COMMANDS_H_
8	#define _INTEL_GPU_COMMANDS_H_	8	#define _INTEL_GPU_COMMANDS_H_
9		9
		10	/*
		11	* Target address alignments required for GPU access e.g.
		12	* MI_STORE_DWORD_IMM.
		13	*/
		14	#define alignof_dword 4
		15	#define alignof_qword 8
		16
10	/*	17	/*
11	* Instruction field definitions used by the command parser	18	* Instruction field definitions used by the command parser
12	*/	19	*/

drivers/gpu/drm/i915/gt/intel_gt.c+250−0

@@ -0,0 +1,250 @@
	1	// SPDX-License-Identifier: MIT
	2	/*
	3	* Copyright © 2019 Intel Corporation
	4	*/
	5
	6	#include "i915_drv.h"
	7
	8	#include "intel_gt.h"
	9	#include "intel_gt_pm.h"
	10	#include "intel_uncore.h"
	11
	12	void intel_gt_init_early(struct intel_gt gt, struct drm_i915_private i915)
	13	{
	14	gt->i915 = i915;
	15	gt->uncore = &i915->uncore;
	16
	17	INIT_LIST_HEAD(&gt->active_rings);
	18	INIT_LIST_HEAD(&gt->closed_vma);
	19
	20	spin_lock_init(&gt->closed_lock);
	21
	22	intel_gt_init_hangcheck(gt);
	23	intel_gt_init_reset(gt);
	24	intel_gt_pm_init_early(gt);
	25	}
	26
	27	void intel_gt_init_hw(struct drm_i915_private *i915)
	28	{
	29	i915->gt.ggtt = &i915->ggtt;
	30	}
	31
	32	static void rmw_set(struct intel_uncore *uncore, i915_reg_t reg, u32 set)
	33	{
	34	intel_uncore_rmw(uncore, reg, 0, set);
	35	}
	36
	37	static void rmw_clear(struct intel_uncore *uncore, i915_reg_t reg, u32 clr)
	38	{
	39	intel_uncore_rmw(uncore, reg, clr, 0);
	40	}
	41
	42	static void clear_register(struct intel_uncore *uncore, i915_reg_t reg)
	43	{
	44	intel_uncore_rmw(uncore, reg, 0, 0);
	45	}
	46
	47	static void gen8_clear_engine_error_register(struct intel_engine_cs *engine)
	48	{
	49	GEN6_RING_FAULT_REG_RMW(engine, RING_FAULT_VALID, 0);
	50	GEN6_RING_FAULT_REG_POSTING_READ(engine);
	51	}
	52
	53	void
	54	intel_gt_clear_error_registers(struct intel_gt *gt,
	55	intel_engine_mask_t engine_mask)
	56	{
	57	struct drm_i915_private *i915 = gt->i915;
	58	struct intel_uncore *uncore = gt->uncore;
	59	u32 eir;
	60
	61	if (!IS_GEN(i915, 2))
	62	clear_register(uncore, PGTBL_ER);
	63
	64	if (INTEL_GEN(i915) < 4)
	65	clear_register(uncore, IPEIR(RENDER_RING_BASE));
	66	else
	67	clear_register(uncore, IPEIR_I965);
	68
	69	clear_register(uncore, EIR);
	70	eir = intel_uncore_read(uncore, EIR);
	71	if (eir) {
	72	/*
	73	* some errors might have become stuck,
	74	* mask them.
	75	*/
	76	DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir);
	77	rmw_set(uncore, EMR, eir);
	78	intel_uncore_write(uncore, GEN2_IIR,
	79	I915_MASTER_ERROR_INTERRUPT);
	80	}
	81
	82	if (INTEL_GEN(i915) >= 8) {
	83	rmw_clear(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID);
	84	intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG);
	85	} else if (INTEL_GEN(i915) >= 6) {
	86	struct intel_engine_cs *engine;
	87	enum intel_engine_id id;
	88
	89	for_each_engine_masked(engine, i915, engine_mask, id)
	90	gen8_clear_engine_error_register(engine);
	91	}
	92	}
	93
	94	static void gen6_check_faults(struct intel_gt *gt)
	95	{
	96	struct intel_engine_cs *engine;
	97	enum intel_engine_id id;
	98	u32 fault;
	99
	100	for_each_engine(engine, gt->i915, id) {
	101	fault = GEN6_RING_FAULT_REG_READ(engine);
	102	if (fault & RING_FAULT_VALID) {
	103	DRM_DEBUG_DRIVER("Unexpected fault\n"
	104	"\tAddr: 0x%08lx\n"
	105	"\tAddress space: %s\n"
	106	"\tSource ID: %d\n"
	107	"\tType: %d\n",
	108	fault & PAGE_MASK,
	109	fault & RING_FAULT_GTTSEL_MASK ?
	110	"GGTT" : "PPGTT",
	111	RING_FAULT_SRCID(fault),
	112	RING_FAULT_FAULT_TYPE(fault));
	113	}
	114	}
	115	}
	116
	117	static void gen8_check_faults(struct intel_gt *gt)
	118	{
	119	struct intel_uncore *uncore = gt->uncore;
	120	u32 fault = intel_uncore_read(uncore, GEN8_RING_FAULT_REG);
	121
	122	if (fault & RING_FAULT_VALID) {
	123	u32 fault_data0, fault_data1;
	124	u64 fault_addr;
	125
	126	fault_data0 = intel_uncore_read(uncore, GEN8_FAULT_TLB_DATA0);
	127	fault_data1 = intel_uncore_read(uncore, GEN8_FAULT_TLB_DATA1);
	128	fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) \|
	129	((u64)fault_data0 << 12);
	130
	131	DRM_DEBUG_DRIVER("Unexpected fault\n"
	132	"\tAddr: 0x%08x_%08x\n"
	133	"\tAddress space: %s\n"
	134	"\tEngine ID: %d\n"
	135	"\tSource ID: %d\n"
	136	"\tType: %d\n",
	137	upper_32_bits(fault_addr),
	138	lower_32_bits(fault_addr),
	139	fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
	140	GEN8_RING_FAULT_ENGINE_ID(fault),
	141	RING_FAULT_SRCID(fault),
	142	RING_FAULT_FAULT_TYPE(fault));
	143	}
	144	}
	145
	146	void intel_gt_check_and_clear_faults(struct intel_gt *gt)
	147	{
	148	struct drm_i915_private *i915 = gt->i915;
	149
	150	/* From GEN8 onwards we only have one 'All Engine Fault Register' */
	151	if (INTEL_GEN(i915) >= 8)
	152	gen8_check_faults(gt);
	153	else if (INTEL_GEN(i915) >= 6)
	154	gen6_check_faults(gt);
	155	else
	156	return;
	157
	158	intel_gt_clear_error_registers(gt, ALL_ENGINES);
	159	}
	160
	161	void intel_gt_flush_ggtt_writes(struct intel_gt *gt)
	162	{
	163	struct drm_i915_private *i915 = gt->i915;
	164	intel_wakeref_t wakeref;
	165
	166	/*
	167	* No actual flushing is required for the GTT write domain for reads
	168	* from the GTT domain. Writes to it "immediately" go to main memory
	169	* as far as we know, so there's no chipset flush. It also doesn't
	170	* land in the GPU render cache.
	171	*
	172	* However, we do have to enforce the order so that all writes through
	173	* the GTT land before any writes to the device, such as updates to
	174	* the GATT itself.
	175	*
	176	* We also have to wait a bit for the writes to land from the GTT.
	177	* An uncached read (i.e. mmio) seems to be ideal for the round-trip
	178	* timing. This issue has only been observed when switching quickly
	179	* between GTT writes and CPU reads from inside the kernel on recent hw,
	180	* and it appears to only affect discrete GTT blocks (i.e. on LLC
	181	* system agents we cannot reproduce this behaviour, until Cannonlake
	182	* that was!).
	183	*/
	184
	185	wmb();
	186
	187	if (INTEL_INFO(i915)->has_coherent_ggtt)
	188	return;
	189
	190	intel_gt_chipset_flush(gt);
	191
	192	with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
	193	struct intel_uncore *uncore = gt->uncore;
	194
	195	spin_lock_irq(&uncore->lock);
	196	intel_uncore_posting_read_fw(uncore,
	197	RING_HEAD(RENDER_RING_BASE));
	198	spin_unlock_irq(&uncore->lock);
	199	}
	200	}
	201
	202	void intel_gt_chipset_flush(struct intel_gt *gt)
	203	{
	204	wmb();
	205	if (INTEL_GEN(gt->i915) < 6)
	206	intel_gtt_chipset_flush();
	207	}
	208
	209	int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size)
	210	{
	211	struct drm_i915_private *i915 = gt->i915;
	212	struct drm_i915_gem_object *obj;
	213	struct i915_vma *vma;
	214	int ret;
	215
	216	obj = i915_gem_object_create_stolen(i915, size);
	217	if (!obj)
	218	obj = i915_gem_object_create_internal(i915, size);
	219	if (IS_ERR(obj)) {
	220	DRM_ERROR("Failed to allocate scratch page\n");
	221	return PTR_ERR(obj);
	222	}
	223
	224	vma = i915_vma_instance(obj, &gt->ggtt->vm, NULL);
	225	if (IS_ERR(vma)) {
	226	ret = PTR_ERR(vma);
	227	goto err_unref;
	228	}
	229
	230	ret = i915_vma_pin(vma, 0, 0, PIN_GLOBAL \| PIN_HIGH);
	231	if (ret)
	232	goto err_unref;
	233
	234	gt->scratch = vma;
	235	return 0;
	236
	237	err_unref:
	238	i915_gem_object_put(obj);
	239	return ret;
	240	}
	241
	242	void intel_gt_fini_scratch(struct intel_gt *gt)
	243	{
	244	i915_vma_unpin_and_release(&gt->scratch, 0);
	245	}
	246
	247	void intel_gt_cleanup_early(struct intel_gt *gt)
	248	{
	249	intel_gt_fini_reset(gt);
	250	}

drivers/gpu/drm/i915/gt/intel_gt.h+60−0

@@ -0,0 +1,60 @@
	1	/* SPDX-License-Identifier: MIT */
	2	/*
	3	* Copyright © 2019 Intel Corporation
	4	*/
	5
	6	#ifndef __INTEL_GT__
	7	#define __INTEL_GT__
	8
	9	#include "intel_engine_types.h"
	10	#include "intel_gt_types.h"
	11	#include "intel_reset.h"
	12
	13	struct drm_i915_private;
	14
	15	static inline struct intel_gt uc_to_gt(struct intel_uc uc)
	16	{
	17	return container_of(uc, struct intel_gt, uc);
	18	}
	19
	20	static inline struct intel_gt guc_to_gt(struct intel_guc guc)
	21	{
	22	return container_of(guc, struct intel_gt, uc.guc);
	23	}
	24
	25	static inline struct intel_gt huc_to_gt(struct intel_huc huc)
	26	{
	27	return container_of(huc, struct intel_gt, uc.huc);
	28	}
	29
	30	void intel_gt_init_early(struct intel_gt gt, struct drm_i915_private i915);
	31	void intel_gt_init_hw(struct drm_i915_private *i915);
	32
	33	void intel_gt_cleanup_early(struct intel_gt *gt);
	34
	35	void intel_gt_check_and_clear_faults(struct intel_gt *gt);
	36	void intel_gt_clear_error_registers(struct intel_gt *gt,
	37	intel_engine_mask_t engine_mask);
	38
	39	void intel_gt_flush_ggtt_writes(struct intel_gt *gt);
	40	void intel_gt_chipset_flush(struct intel_gt *gt);
	41
	42	void intel_gt_init_hangcheck(struct intel_gt *gt);
	43
	44	int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size);
	45	void intel_gt_fini_scratch(struct intel_gt *gt);
	46
	47	static inline u32 intel_gt_scratch_offset(const struct intel_gt *gt,
	48	enum intel_gt_scratch_field field)
	49	{
	50	return i915_ggtt_offset(gt->scratch) + field;
	51	}
	52
	53	static inline bool intel_gt_is_wedged(struct intel_gt *gt)
	54	{
	55	return __intel_reset_failed(&gt->reset);
	56	}
	57
	58	void intel_gt_queue_hangcheck(struct intel_gt *gt);
	59
	60	#endif /* __INTEL_GT_H__ */

drivers/gpu/drm/i915/gt/intel_gt_pm.c+33−29

  */
 #include "i915_drv.h"
+#include "i915_params.h"
 #include "intel_engine_pm.h"
+#include "intel_gt.h"
 #include "intel_gt_pm.h"
 #include "intel_pm.h"
 #include "intel_wakeref.h"
 static int intel_gt_unpark(struct intel_wakeref *wf)
 {
-	struct drm_i915_private *i915 =
+	struct intel_gt *gt = container_of(wf, typeof(*gt), wakeref);
-		container_of(wf, typeof(*i915), gt.wakeref);
+	struct drm_i915_private *i915 = gt->i915;
 	GEM_TRACE("\n");
 	 * Work around it by grabbing a GT IRQ power domain whilst there is any
 	 * GT activity, preventing any DC state transitions.
 	 */
-	i915->gt.awake = intel_display_power_get(i915, POWER_DOMAIN_GT_IRQ);
+	gt->awake = intel_display_power_get(i915, POWER_DOMAIN_GT_IRQ);
-	GEM_BUG_ON(!i915->gt.awake);
+	GEM_BUG_ON(!gt->awake);
 	intel_enable_gt_powersave(i915);
 	i915_pmu_gt_unparked(i915);
-	i915_queue_hangcheck(i915);
+	intel_gt_queue_hangcheck(gt);
 	pm_notify(i915, INTEL_GT_UNPARK);
 	return 0;
 }
-void intel_gt_pm_get(struct drm_i915_private *i915)
+void intel_gt_pm_get(struct intel_gt *gt)
 {
-	intel_wakeref_get(&i915->runtime_pm, &i915->gt.wakeref, intel_gt_unpark);
+	struct intel_runtime_pm *rpm = &gt->i915->runtime_pm;
+	intel_wakeref_get(rpm, &gt->wakeref, intel_gt_unpark);
 }
 static int intel_gt_park(struct intel_wakeref *wf)
 	return 0;
 }
-void intel_gt_pm_put(struct drm_i915_private *i915)
+void intel_gt_pm_put(struct intel_gt *gt)
 {
-	intel_wakeref_put(&i915->runtime_pm, &i915->gt.wakeref, intel_gt_park);
+	struct intel_runtime_pm *rpm = &gt->i915->runtime_pm;
+	intel_wakeref_put(rpm, &gt->wakeref, intel_gt_park);
 }
-void intel_gt_pm_init(struct drm_i915_private *i915)
+void intel_gt_pm_init_early(struct intel_gt *gt)
 {
-	intel_wakeref_init(&i915->gt.wakeref);
+	intel_wakeref_init(&gt->wakeref);
-	BLOCKING_INIT_NOTIFIER_HEAD(&i915->gt.pm_notifications);
+	BLOCKING_INIT_NOTIFIER_HEAD(&gt->pm_notifications);
 }
-static bool reset_engines(struct drm_i915_private *i915)
+static bool reset_engines(struct intel_gt *gt)
 {
-	if (INTEL_INFO(i915)->gpu_reset_clobbers_display)
+	if (INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
 		return false;
-	return intel_gpu_reset(i915, ALL_ENGINES) == 0;
+	return __intel_gt_reset(gt, ALL_ENGINES) == 0;
 }
 /**
  * intel_gt_sanitize: called after the GPU has lost power
- * @i915: the i915 device
+ * @gt: the i915 GT container
  * @force: ignore a failed reset and sanitize engine state anyway
  *
  * Anytime we reset the GPU, either with an explicit GPU reset or through a
  * to match. Note that calling intel_gt_sanitize() if the GPU has not
  * been reset results in much confusion!
  */
-void intel_gt_sanitize(struct drm_i915_private *i915, bool force)
+void intel_gt_sanitize(struct intel_gt *gt, bool force)
 {
 	struct intel_engine_cs *engine;
 	enum intel_engine_id id;
 	GEM_TRACE("\n");
-	if (!reset_engines(i915) && !force)
+	intel_uc_sanitize(&gt->uc);
+	if (!reset_engines(gt) && !force)
 		return;
-	for_each_engine(engine, i915, id)
+	for_each_engine(engine, gt->i915, id)
-		intel_engine_reset(engine, false);
+		__intel_engine_reset(engine, false);
 }
-int intel_gt_resume(struct drm_i915_private *i915)
+int intel_gt_resume(struct intel_gt *gt)
 {
 	struct intel_engine_cs *engine;
 	enum intel_engine_id id;
 	 * Only the kernel contexts should remain pinned over suspend,
 	 * allowing us to fixup the user contexts on their first pin.
 	 */
-	intel_gt_pm_get(i915);
+	intel_gt_pm_get(gt);
-	for_each_engine(engine, i915, id) {
+	for_each_engine(engine, gt->i915, id) {
 		struct intel_context *ce;
 		intel_engine_pm_get(engine);
 		if (ce)
 			ce->ops->reset(ce);
-		ce = engine->preempt_context;
-		if (ce)
-			ce->ops->reset(ce);
 		engine->serial++; /* kernel context lost */
 		err = engine->resume(engine);
 		intel_engine_pm_put(engine);
 		if (err) {
-			dev_err(i915->drm.dev,
+			dev_err(gt->i915->drm.dev,
 				"Failed to restart %s (%d)\n",
 				engine->name, err);
 			break;
 		}
 	}
-	intel_gt_pm_put(i915);
+	intel_gt_pm_put(gt);
 	return err;
 }

drivers/gpu/drm/i915/gt/intel_gt_pm.h+6−6

@@ -9,19 +9,19 @@ · 8 unmodified lines
9		9
10	#include <linux/types.h>	10	#include <linux/types.h>
11		11
12	struct drm_i915_private;	12	struct intel_gt;
13		13
14	enum {	14	enum {
15	INTEL_GT_UNPARK,	15	INTEL_GT_UNPARK,
16	INTEL_GT_PARK,	16	INTEL_GT_PARK,
17	};	17	};
18		18
19	void intel_gt_pm_get(struct drm_i915_private *i915);	19	void intel_gt_pm_get(struct intel_gt *gt);
20	void intel_gt_pm_put(struct drm_i915_private *i915);	20	void intel_gt_pm_put(struct intel_gt *gt);
21		21
22	void intel_gt_pm_init(struct drm_i915_private *i915);	22	void intel_gt_pm_init_early(struct intel_gt *gt);
23		23
24	void intel_gt_sanitize(struct drm_i915_private *i915, bool force);	24	void intel_gt_sanitize(struct intel_gt *gt, bool force);
25	int intel_gt_resume(struct drm_i915_private *i915);	25	int intel_gt_resume(struct intel_gt *gt);
26		26
27	#endif /* INTEL_GT_PM_H */	27	#endif /* INTEL_GT_PM_H */

drivers/gpu/drm/i915/gt/intel_gt_types.h+96−0

@@ -0,0 +1,96 @@
	1	/* SPDX-License-Identifier: MIT */
	2	/*
	3	* Copyright © 2019 Intel Corporation
	4	*/
	5
	6	#ifndef __INTEL_GT_TYPES__
	7	#define __INTEL_GT_TYPES__
	8
	9	#include <linux/ktime.h>
	10	#include <linux/list.h>
	11	#include <linux/mutex.h>
	12	#include <linux/notifier.h>
	13	#include <linux/spinlock.h>
	14	#include <linux/types.h>
	15
	16	#include "uc/intel_uc.h"
	17
	18	#include "i915_vma.h"
	19	#include "intel_reset_types.h"
	20	#include "intel_wakeref.h"
	21
	22	struct drm_i915_private;
	23	struct i915_ggtt;
	24	struct intel_uncore;
	25
	26	struct intel_hangcheck {
	27	/* For hangcheck timer */
	28	#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
	29	#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
	30
	31	struct delayed_work work;
	32	};
	33
	34	struct intel_gt {
	35	struct drm_i915_private *i915;
	36	struct intel_uncore *uncore;
	37	struct i915_ggtt *ggtt;
	38
	39	struct intel_uc uc;
	40
	41	struct intel_gt_timelines {
	42	struct mutex mutex; /* protects list */
	43	struct list_head active_list;
	44
	45	/* Pack multiple timelines' seqnos into the same page */
	46	spinlock_t hwsp_lock;
	47	struct list_head hwsp_free_list;
	48	} timelines;
	49
	50	struct list_head active_rings;
	51
	52	struct intel_wakeref wakeref;
	53
	54	struct list_head closed_vma;
	55	spinlock_t closed_lock; /* guards the list of closed_vma */
	56
	57	struct intel_hangcheck hangcheck;
	58	struct intel_reset reset;
	59
	60	/**
	61	* Is the GPU currently considered idle, or busy executing
	62	* userspace requests? Whilst idle, we allow runtime power
	63	* management to power down the hardware and display clocks.
	64	* In order to reduce the effect on performance, there
	65	* is a slight delay before we do so.
	66	*/
	67	intel_wakeref_t awake;
	68
	69	struct blocking_notifier_head pm_notifications;
	70
	71	ktime_t last_init_time;
	72
	73	struct i915_vma *scratch;
	74
	75	u32 pm_imr;
	76	u32 pm_ier;
	77
	78	u32 pm_guc_events;
	79	};
	80
	81	enum intel_gt_scratch_field {
	82	/* 8 bytes */
	83	INTEL_GT_SCRATCH_FIELD_DEFAULT = 0,
	84
	85	/* 8 bytes */
	86	INTEL_GT_SCRATCH_FIELD_CLEAR_SLM_WA = 128,
	87
	88	/* 8 bytes */
	89	INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH = 128,
	90
	91	/* 8 bytes */
	92	INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA = 256,
	93
	94	};
	95
	96	#endif /* __INTEL_GT_TYPES_H__ */

drivers/gpu/drm/i915/gt/intel_hangcheck.c+42−29

  *
  */
-#include "intel_reset.h"
 #include "i915_drv.h"
+#include "intel_engine.h"
+#include "intel_gt.h"
+#include "intel_reset.h"
 struct hangcheck {
 	u64 acthd;
 	int slice;
 	int subslice;
-	if (engine->id != RCS0)
-		return true;
 	intel_engine_get_instdone(engine, &instdone);
 	/* There might be unstable subunit states even when
 static enum intel_engine_hangcheck_action
 engine_stuck(struct intel_engine_cs *engine, u64 acthd)
 {
-	struct drm_i915_private *dev_priv = engine->i915;
 	enum intel_engine_hangcheck_action ha;
 	u32 tmp;
 	if (ha != ENGINE_DEAD)
 		return ha;
-	if (IS_GEN(dev_priv, 2))
+	if (IS_GEN(engine->i915, 2))
 		return ENGINE_DEAD;
 	/* Is the chip hanging on a WAIT_FOR_EVENT?
 	 */
 	tmp = ENGINE_READ(engine, RING_CTL);
 	if (tmp & RING_WAIT) {
-		i915_handle_error(dev_priv, engine->mask, 0,
+		intel_gt_handle_error(engine->gt, engine->mask, 0,
-				  "stuck wait on %s", engine->name);
+				      "stuck wait on %s", engine->name);
 		ENGINE_WRITE(engine, RING_CTL, tmp);
 		return ENGINE_WAIT_KICK;
 	}
 				 I915_ENGINE_WEDGED_TIMEOUT);
 }
-static void hangcheck_declare_hang(struct drm_i915_private *i915,
+static void hangcheck_declare_hang(struct intel_gt *gt,
 				   intel_engine_mask_t hung,
 				   intel_engine_mask_t stuck)
 {
 		hung &= ~stuck;
 	len = scnprintf(msg, sizeof(msg),
 			"%s on ", stuck == hung ? "no progress" : "hang");
-	for_each_engine_masked(engine, i915, hung, tmp)
+	for_each_engine_masked(engine, gt->i915, hung, tmp)
 		len += scnprintf(msg + len, sizeof(msg) - len,
 				 "%s, ", engine->name);
 	msg[len-2] = '\0';
-	return i915_handle_error(i915, hung, I915_ERROR_CAPTURE, "%s", msg);
+	return intel_gt_handle_error(gt, hung, I915_ERROR_CAPTURE, "%s", msg);
 }
 /*
  * we kick the ring. If we see no progress on three subsequent calls
  * we assume chip is wedged and try to fix it by resetting the chip.
  */
-static void i915_hangcheck_elapsed(struct work_struct *work)
+static void hangcheck_elapsed(struct work_struct *work)
 {
-	struct drm_i915_private *dev_priv =
+	struct intel_gt *gt =
-		container_of(work, typeof(*dev_priv),
+		container_of(work, typeof(*gt), hangcheck.work.work);
-			     gpu_error.hangcheck_work.work);
 	intel_engine_mask_t hung = 0, stuck = 0, wedged = 0;
 	struct intel_engine_cs *engine;
 	enum intel_engine_id id;
 	if (!i915_modparams.enable_hangcheck)
 		return;
-	if (!READ_ONCE(dev_priv->gt.awake))
+	if (!READ_ONCE(gt->awake))
 		return;
-	if (i915_terminally_wedged(dev_priv))
+	if (intel_gt_is_wedged(gt))
 		return;
-	wakeref = intel_runtime_pm_get_if_in_use(&dev_priv->runtime_pm);
+	wakeref = intel_runtime_pm_get_if_in_use(&gt->i915->runtime_pm);
 	if (!wakeref)
 		return;
 	 * periodically arm the mmio checker to see if we are triggering
 	 * any invalid access.
 	 */
-	intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
+	intel_uncore_arm_unclaimed_mmio_detection(gt->uncore);
-	for_each_engine(engine, dev_priv, id) {
+	for_each_engine(engine, gt->i915, id) {
 		struct hangcheck hc;
 		intel_engine_signal_breadcrumbs(engine);
 	if (GEM_SHOW_DEBUG() && (hung | stuck)) {
 		struct drm_printer p = drm_debug_printer("hangcheck");
-		for_each_engine(engine, dev_priv, id) {
+		for_each_engine(engine, gt->i915, id) {
 			if (intel_engine_is_idle(engine))
 				continue;
 	}
 	if (wedged) {
-		dev_err(dev_priv->drm.dev,
+		dev_err(gt->i915->drm.dev,
 			"GPU recovery timed out,"
 			" cancelling all in-flight rendering.\n");
 		GEM_TRACE_DUMP();
-		i915_gem_set_wedged(dev_priv);
+		intel_gt_set_wedged(gt);
 	}
 	if (hung)
-		hangcheck_declare_hang(dev_priv, hung, stuck);
+		hangcheck_declare_hang(gt, hung, stuck);
-	intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
+	intel_runtime_pm_put(&gt->i915->runtime_pm, wakeref);
 	/* Reset timer in case GPU hangs without another request being added */
-	i915_queue_hangcheck(dev_priv);
+	intel_gt_queue_hangcheck(gt);
+}
+void intel_gt_queue_hangcheck(struct intel_gt *gt)
+{
+	unsigned long delay;
+	if (unlikely(!i915_modparams.enable_hangcheck))
+		return;
+	/*
+	 * Don't continually defer the hangcheck so that it is always run at
+	 * least once after work has been scheduled on any ring. Otherwise,
+	 * we will ignore a hung ring if a second ring is kept busy.
+	 */
+	delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
+	queue_delayed_work(system_long_wq, &gt->hangcheck.work, delay);
 }
 void intel_engine_init_hangcheck(struct intel_engine_cs *engine)
 	engine->hangcheck.action_timestamp = jiffies;
 }
-void intel_hangcheck_init(struct drm_i915_private *i915)
+void intel_gt_init_hangcheck(struct intel_gt *gt)
 {
-	INIT_DELAYED_WORK(&i915->gpu_error.hangcheck_work,
+	INIT_DELAYED_WORK(&gt->hangcheck.work, hangcheck_elapsed);
-			  i915_hangcheck_elapsed);
 }
 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)

drivers/gpu/drm/i915/gt/intel_lrc.c+580−437

@@ -136,9 +136,9 @@ · 135 unmodified lines
136	#include "gem/i915_gem_context.h"	136	#include "gem/i915_gem_context.h"
137		137
138	#include "i915_drv.h"	138	#include "i915_drv.h"
139	#include "i915_gem_render_state.h"
140	#include "i915_vgpu.h"	139	#include "i915_vgpu.h"
141	#include "intel_engine_pm.h"	140	#include "intel_engine_pm.h"
		141	#include "intel_gt.h"
142	#include "intel_lrc_reg.h"	142	#include "intel_lrc_reg.h"
143	#include "intel_mocs.h"	143	#include "intel_mocs.h"
144	#include "intel_reset.h"	144	#include "intel_reset.h"
@@ -161,6 +161,8 @@ · 16 unmodified lines
161	#define GEN8_CTX_STATUS_COMPLETED_MASK \	161	#define GEN8_CTX_STATUS_COMPLETED_MASK \
162	(GEN8_CTX_STATUS_COMPLETE \| GEN8_CTX_STATUS_PREEMPTED)	162	(GEN8_CTX_STATUS_COMPLETE \| GEN8_CTX_STATUS_PREEMPTED)
163		163
		164	#define CTX_DESC_FORCE_RESTORE BIT_ULL(2)
		165
164	/* Typical size of the average request (2 pipecontrols and a MI_BB) */	166	/* Typical size of the average request (2 pipecontrols and a MI_BB) */
165	#define EXECLISTS_REQUEST_SIZE 64 /* bytes */	167	#define EXECLISTS_REQUEST_SIZE 64 /* bytes */
166	#define WA_TAIL_DWORDS 2	168	#define WA_TAIL_DWORDS 2
@@ -221,6 +223,26 @@ static void execlists_init_reg_state(u32 *reg_state, · 54 unmodified lines
221	struct intel_engine_cs *engine,	223	struct intel_engine_cs *engine,
222	struct intel_ring *ring);	224	struct intel_ring *ring);
223		225
		226	static inline u32 intel_hws_preempt_address(struct intel_engine_cs *engine)
		227	{
		228	return (i915_ggtt_offset(engine->status_page.vma) +
		229	I915_GEM_HWS_PREEMPT_ADDR);
		230	}
		231
		232	static inline void
		233	ring_set_paused(const struct intel_engine_cs *engine, int state)
		234	{
		235	/*
		236	* We inspect HWS_PREEMPT with a semaphore inside
		237	* engine->emit_fini_breadcrumb. If the dword is true,
		238	* the ring is paused as the semaphore will busywait
		239	* until the dword is false.
		240	*/
		241	engine->status_page.addr[I915_GEM_HWS_PREEMPT] = state;
		242	if (state)
		243	wmb();
		244	}
		245
224	static inline struct i915_priolist to_priolist(struct rb_node rb)	246	static inline struct i915_priolist to_priolist(struct rb_node rb)
225	{	247	{
226	return rb_entry(rb, struct i915_priolist, node);	248	return rb_entry(rb, struct i915_priolist, node);
@@ -235,6 +257,17 @@ static int effective_prio(const struct i915_request *rq) · 8 unmodified lines
235	{	257	{
236	int prio = rq_prio(rq);	258	int prio = rq_prio(rq);
237		259
		260	/*
		261	* If this request is special and must not be interrupted at any
		262	* cost, so be it. Note we are only checking the most recent request
		263	* in the context and so may be masking an earlier vip request. It
		264	* is hoped that under the conditions where nopreempt is used, this
		265	* will not matter (i.e. all requests to that context will be
		266	* nopreempt for as long as desired).
		267	*/
		268	if (i915_request_has_nopreempt(rq))
		269	prio = I915_PRIORITY_UNPREEMPTABLE;
		270
238	/*	271	/*
239	* On unwinding the active request, we give it a priority bump	272	* On unwinding the active request, we give it a priority bump
240	* if it has completed waiting on any semaphore. If we know that	273	* if it has completed waiting on any semaphore. If we know that
@@ -245,6 +278,7 @@ static int effective_prio(const struct i915_request *rq) · 4 unmodified lines
245	prio \|= I915_PRIORITY_NOSEMAPHORE;	278	prio \|= I915_PRIORITY_NOSEMAPHORE;
246		279
247	/* Restrict mere WAIT boosts from triggering preemption */	280	/* Restrict mere WAIT boosts from triggering preemption */
		281	BUILD_BUG_ON(__NO_PREEMPTION & ~I915_PRIORITY_MASK); /* only internal */
248	return prio \| __NO_PREEMPTION;	282	return prio \| __NO_PREEMPTION;
249	}	283	}
250		284
@@ -271,10 +305,7 @@ static inline bool need_preempt(const struct intel_engine_cs *engine, · 20 unmodified lines
271	{	305	{
272	int last_prio;	306	int last_prio;
273		307
274	if (!engine->preempt_context)	308	if (!intel_engine_has_semaphores(engine))
275	return false;
276
277	if (i915_request_completed(rq))
278	return false;	309	return false;
279		310
280	/*	311	/*
@@ -338,9 +369,6 @@ __maybe_unused static inline bool · 57 unmodified lines
338	assert_priority_queue(const struct i915_request *prev,	369	assert_priority_queue(const struct i915_request *prev,
339	const struct i915_request *next)	370	const struct i915_request *next)
340	{	371	{
341	const struct intel_engine_execlists *execlists =
342	&prev->engine->execlists;
343
344	/*	372	/*
345	* Without preemption, the prev may refer to the still active element	373	* Without preemption, the prev may refer to the still active element
346	* which we refuse to let go.	374	* which we refuse to let go.
@@ -348,7 +376,7 @@ assert_priority_queue(const struct i915_request *prev, · 1 unmodified line
348	* Even with preemption, there are times when we think it is better not	376	* Even with preemption, there are times when we think it is better not
349	* to preempt and leave an ostensibly lower priority request in flight.	377	* to preempt and leave an ostensibly lower priority request in flight.
350	*/	378	*/
351	if (port_request(execlists->port) == prev)	379	if (i915_request_is_active(prev))
352	return true;	380	return true;
353		381
354	return rq_prio(prev) >= rq_prio(next);	382	return rq_prio(prev) >= rq_prio(next);
@@ -442,13 +470,11 @@ __unwind_incomplete_requests(struct intel_engine_cs *engine) · 87 unmodified lines
442	struct intel_engine_cs *owner;	470	struct intel_engine_cs *owner;
443		471
444	if (i915_request_completed(rq))	472	if (i915_request_completed(rq))
445	break;	473	continue; /* XXX */
446		474
447	__i915_request_unsubmit(rq);	475	__i915_request_unsubmit(rq);
448	unwind_wa_tail(rq);	476	unwind_wa_tail(rq);
449		477
450	GEM_BUG_ON(rq->hw_context->inflight);
451
452	/*	478	/*
453	* Push the request back into the queue for later resubmission.	479	* Push the request back into the queue for later resubmission.
454	* If this request is not native to this physical engine (i.e.	480	* If this request is not native to this physical engine (i.e.
@@ -468,6 +494,19 @@ __unwind_incomplete_requests(struct intel_engine_cs *engine) · 13 unmodified lines
468	list_move(&rq->sched.link, pl);	494	list_move(&rq->sched.link, pl);
469	active = rq;	495	active = rq;
470	} else {	496	} else {
		497	/*
		498	* Decouple the virtual breadcrumb before moving it
		499	* back to the virtual engine -- we don't want the
		500	* request to complete in the background and try
		501	* and cancel the breadcrumb on the virtual engine
		502	* (instead of the old engine where it is linked)!
		503	*/
		504	if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
		505	&rq->fence.flags)) {
		506	spin_lock(&rq->lock);
		507	i915_request_cancel_breadcrumb(rq);
		508	spin_unlock(&rq->lock);
		509	}
471	rq->engine = owner;	510	rq->engine = owner;
472	owner->submit_request(rq);	511	owner->submit_request(rq);
473	active = NULL;	512	active = NULL;
@@ -500,32 +539,32 @@ execlists_context_status_change(struct i915_request *rq, unsigned long status) · 26 unmodified lines
500	status, rq);	539	status, rq);
501	}	540	}
502		541
503	inline void	542	static inline struct i915_request *
504	execlists_user_begin(struct intel_engine_execlists *execlists,	543	execlists_schedule_in(struct i915_request *rq, int idx)
505	const struct execlist_port *port)
506	{	544	{
507	execlists_set_active_once(execlists, EXECLISTS_ACTIVE_USER);	545	struct intel_context *ce = rq->hw_context;
508	}	546	int count;
509		547
510	inline void	548	trace_i915_request_in(rq, idx);
511	execlists_user_end(struct intel_engine_execlists *execlists)
512	{
513	execlists_clear_active(execlists, EXECLISTS_ACTIVE_USER);
514	}
515		549
516	static inline void	550	count = intel_context_inflight_count(ce);
517	execlists_context_schedule_in(struct i915_request *rq)	551	if (!count) {
518	{	552	intel_context_get(ce);
519	GEM_BUG_ON(rq->hw_context->inflight);	553	ce->inflight = rq->engine;
		554
		555	execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN);
		556	intel_engine_context_in(ce->inflight);
		557	}
		558
		559	intel_context_inflight_inc(ce);
		560	GEM_BUG_ON(intel_context_inflight(ce) != rq->engine);
520		561
521	execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN);	562	return i915_request_get(rq);
522	intel_engine_context_in(rq->engine);
523	rq->hw_context->inflight = rq->engine;
524	}	563	}
525		564
526	static void kick_siblings(struct i915_request *rq)	565	static void kick_siblings(struct i915_request rq, struct intel_context ce)
527	{	566	{
528	struct virtual_engine *ve = to_virtual_engine(rq->hw_context->engine);	567	struct virtual_engine ve = container_of(ce, typeof(ve), context);
529	struct i915_request *next = READ_ONCE(ve->request);	568	struct i915_request *next = READ_ONCE(ve->request);
530		569
531	if (next && next->execution_mask & ~rq->execution_mask)	570	if (next && next->execution_mask & ~rq->execution_mask)
@@ -533,29 +572,42 @@ static void kick_siblings(struct i915_request *rq) · 1 unmodified line
533	}	572	}
534		573
535	static inline void	574	static inline void
536	execlists_context_schedule_out(struct i915_request *rq, unsigned long status)	575	execlists_schedule_out(struct i915_request *rq)
537	{	576	{
538	rq->hw_context->inflight = NULL;	577	struct intel_context *ce = rq->hw_context;
539	intel_engine_context_out(rq->engine);	578
540	execlists_context_status_change(rq, status);	579	GEM_BUG_ON(!intel_context_inflight_count(ce));
		580
541	trace_i915_request_out(rq);	581	trace_i915_request_out(rq);
542		582
543	/*	583	intel_context_inflight_dec(ce);
544	* If this is part of a virtual engine, its next request may have	584	if (!intel_context_inflight_count(ce)) {
545	* been blocked waiting for access to the active context. We have	585	intel_engine_context_out(ce->inflight);
546	* to kick all the siblings again in case we need to switch (e.g.	586	execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_OUT);
547	* the next request is not runnable on this engine). Hopefully,	587
548	* we will already have submitted the next request before the	588	/*
549	* tasklet runs and do not need to rebuild each virtual tree	589	* If this is part of a virtual engine, its next request may
550	* and kick everyone again.	590	* have been blocked waiting for access to the active context.
551	*/	591	* We have to kick all the siblings again in case we need to
552	if (rq->engine != rq->hw_context->engine)	592	* switch (e.g. the next request is not runnable on this
553	kick_siblings(rq);	593	* engine). Hopefully, we will already have submitted the next
		594	* request before the tasklet runs and do not need to rebuild
		595	* each virtual tree and kick everyone again.
		596	*/
		597	ce->inflight = NULL;
		598	if (rq->engine != ce->engine)
		599	kick_siblings(rq, ce);
		600
		601	intel_context_put(ce);
		602	}
		603
		604	i915_request_put(rq);
554	}	605	}
555		606
556	static u64 execlists_update_context(struct i915_request *rq)	607	static u64 execlists_update_context(const struct i915_request *rq)
557	{	608	{
558	struct intel_context *ce = rq->hw_context;	609	struct intel_context *ce = rq->hw_context;
		610	u64 desc;
559		611
560	ce->lrc_reg_state[CTX_RING_TAIL + 1] =	612	ce->lrc_reg_state[CTX_RING_TAIL + 1] =
561	intel_ring_set_tail(rq->ring, rq->tail);	613	intel_ring_set_tail(rq->ring, rq->tail);
@@ -576,7 +628,11 @@ static u64 execlists_update_context(struct i915_request *rq) · 14 unmodified lines
576	* wmb).	628	* wmb).
577	*/	629	*/
578	mb();	630	mb();
579	return ce->lrc_desc;	631
		632	desc = ce->lrc_desc;
		633	ce->lrc_desc &= ~CTX_DESC_FORCE_RESTORE;
		634
		635	return desc;
580	}	636	}
581		637
582	static inline void write_desc(struct intel_engine_execlists *execlists, u64 desc, u32 port)	638	static inline void write_desc(struct intel_engine_execlists *execlists, u64 desc, u32 port)
@@ -590,12 +646,62 @@ static inline void write_desc(struct intel_engine_execlists *execlists, u64 desc · 7 unmodified lines
590	}	646	}
591	}	647	}
592		648
		649	static __maybe_unused void
		650	trace_ports(const struct intel_engine_execlists *execlists,
		651	const char *msg,
		652	struct i915_request * const *ports)
		653	{
		654	const struct intel_engine_cs *engine =
		655	container_of(execlists, typeof(*engine), execlists);
		656
		657	GEM_TRACE("%s: %s { %llx:%lld%s, %llx:%lld }\n",
		658	engine->name, msg,
		659	ports[0]->fence.context,
		660	ports[0]->fence.seqno,
		661	i915_request_completed(ports[0]) ? "!" :
		662	i915_request_started(ports[0]) ? "*" :
		663	"",
		664	ports[1] ? ports[1]->fence.context : 0,
		665	ports[1] ? ports[1]->fence.seqno : 0);
		666	}
		667
		668	static __maybe_unused bool
		669	assert_pending_valid(const struct intel_engine_execlists *execlists,
		670	const char *msg)
		671	{
		672	struct i915_request * const port, rq;
		673	struct intel_context *ce = NULL;
		674
		675	trace_ports(execlists, msg, execlists->pending);
		676
		677	if (execlists->pending[execlists_num_ports(execlists)])
		678	return false;
		679
		680	for (port = execlists->pending; (rq = *port); port++) {
		681	if (ce == rq->hw_context)
		682	return false;
		683
		684	ce = rq->hw_context;
		685	if (i915_request_completed(rq))
		686	continue;
		687
		688	if (i915_active_is_idle(&ce->active))
		689	return false;
		690
		691	if (!i915_vma_is_pinned(ce->state))
		692	return false;
		693	}
		694
		695	return ce;
		696	}
		697
593	static void execlists_submit_ports(struct intel_engine_cs *engine)	698	static void execlists_submit_ports(struct intel_engine_cs *engine)
594	{	699	{
595	struct intel_engine_execlists *execlists = &engine->execlists;	700	struct intel_engine_execlists *execlists = &engine->execlists;
596	struct execlist_port *port = execlists->port;
597	unsigned int n;	701	unsigned int n;
598		702
		703	GEM_BUG_ON(!assert_pending_valid(execlists, "submit"));
		704
599	/*	705	/*
600	* We can skip acquiring intel_runtime_pm_get() here as it was taken	706	* We can skip acquiring intel_runtime_pm_get() here as it was taken
601	* on our behalf by the request (see i915_gem_mark_busy()) and it will	707	* on our behalf by the request (see i915_gem_mark_busy()) and it will
@@ -604,7 +710,7 @@ static void execlists_submit_ports(struct intel_engine_cs *engine) · 2 unmodified lines
604	* that all ELSP are drained i.e. we have processed the CSB,	710	* that all ELSP are drained i.e. we have processed the CSB,
605	* before allowing ourselves to idle and calling intel_runtime_pm_put().	711	* before allowing ourselves to idle and calling intel_runtime_pm_put().
606	*/	712	*/
607	GEM_BUG_ON(!intel_wakeref_active(&engine->wakeref));	713	GEM_BUG_ON(!intel_engine_pm_is_awake(engine));
608		714
609	/*	715	/*
610	* ELSQ note: the submit queue is not cleared after being submitted	716	* ELSQ note: the submit queue is not cleared after being submitted
@@ -613,38 +719,16 @@ static void execlists_submit_ports(struct intel_engine_cs *engine) · 2 unmodified lines
613	* of elsq entries, keep this in mind before changing the loop below.	719	* of elsq entries, keep this in mind before changing the loop below.
614	*/	720	*/
615	for (n = execlists_num_ports(execlists); n--; ) {	721	for (n = execlists_num_ports(execlists); n--; ) {
616	struct i915_request *rq;	722	struct i915_request *rq = execlists->pending[n];
617	unsigned int count;
618	u64 desc;
619		723
620	rq = port_unpack(&port[n], &count);	724	write_desc(execlists,
621	if (rq) {	725	rq ? execlists_update_context(rq) : 0,
622	GEM_BUG_ON(count > !n);	726	n);
623	if (!count++)
624	execlists_context_schedule_in(rq);
625	port_set(&port[n], port_pack(rq, count));
626	desc = execlists_update_context(rq);
627	GEM_DEBUG_EXEC(port[n].context_id = upper_32_bits(desc));
628
629	GEM_TRACE("%s in[%d]: ctx=%d.%d, fence %llx:%lld (current %d), prio=%d\n",
630	engine->name, n,
631	port[n].context_id, count,
632	rq->fence.context, rq->fence.seqno,
633	hwsp_seqno(rq),
634	rq_prio(rq));
635	} else {
636	GEM_BUG_ON(!n);
637	desc = 0;
638	}
639
640	write_desc(execlists, desc, n);
641	}	727	}
642		728
643	/* we need to manually load the submit queue */	729	/* we need to manually load the submit queue */
644	if (execlists->ctrl_reg)	730	if (execlists->ctrl_reg)
645	writel(EL_CTRL_LOAD, execlists->ctrl_reg);	731	writel(EL_CTRL_LOAD, execlists->ctrl_reg);
646
647	execlists_clear_active(execlists, EXECLISTS_ACTIVE_HWACK);
648	}	732	}
649		733
650	static bool ctx_single_port_submission(const struct intel_context *ce)	734	static bool ctx_single_port_submission(const struct intel_context *ce)
@@ -668,6 +752,7 @@ static bool can_merge_ctx(const struct intel_context *prev, · 17 unmodified lines
668	static bool can_merge_rq(const struct i915_request *prev,	752	static bool can_merge_rq(const struct i915_request *prev,
669	const struct i915_request *next)	753	const struct i915_request *next)
670	{	754	{
		755	GEM_BUG_ON(prev == next);
671	GEM_BUG_ON(!assert_priority_queue(prev, next));	756	GEM_BUG_ON(!assert_priority_queue(prev, next));
672		757
673	if (!can_merge_ctx(prev->hw_context, next->hw_context))	758	if (!can_merge_ctx(prev->hw_context, next->hw_context))
@@ -676,58 +761,6 @@ static bool can_merge_rq(const struct i915_request *prev, · 2 unmodified lines
676	return true;	761	return true;
677	}	762	}
678		763
679	static void port_assign(struct execlist_port port, struct i915_request rq)
680	{
681	GEM_BUG_ON(rq == port_request(port));
682
683	if (port_isset(port))
684	i915_request_put(port_request(port));
685
686	port_set(port, port_pack(i915_request_get(rq), port_count(port)));
687	}
688
689	static void inject_preempt_context(struct intel_engine_cs *engine)
690	{
691	struct intel_engine_execlists *execlists = &engine->execlists;
692	struct intel_context *ce = engine->preempt_context;
693	unsigned int n;
694
695	GEM_BUG_ON(execlists->preempt_complete_status !=
696	upper_32_bits(ce->lrc_desc));
697
698	/*
699	* Switch to our empty preempt context so
700	* the state of the GPU is known (idle).
701	*/
702	GEM_TRACE("%s\n", engine->name);
703	for (n = execlists_num_ports(execlists); --n; )
704	write_desc(execlists, 0, n);
705
706	write_desc(execlists, ce->lrc_desc, n);
707
708	/* we need to manually load the submit queue */
709	if (execlists->ctrl_reg)
710	writel(EL_CTRL_LOAD, execlists->ctrl_reg);
711
712	execlists_clear_active(execlists, EXECLISTS_ACTIVE_HWACK);
713	execlists_set_active(execlists, EXECLISTS_ACTIVE_PREEMPT);
714
715	(void)I915_SELFTEST_ONLY(execlists->preempt_hang.count++);
716	}
717
718	static void complete_preempt_context(struct intel_engine_execlists *execlists)
719	{
720	GEM_BUG_ON(!execlists_is_active(execlists, EXECLISTS_ACTIVE_PREEMPT));
721
722	if (inject_preempt_hang(execlists))
723	return;
724
725	execlists_cancel_port_requests(execlists);
726	__unwind_incomplete_requests(container_of(execlists,
727	struct intel_engine_cs,
728	execlists));
729	}
730
731	static void virtual_update_register_offsets(u32 *regs,	764	static void virtual_update_register_offsets(u32 *regs,
732	struct intel_engine_cs *engine)	765	struct intel_engine_cs *engine)
733	{	766	{
@@ -792,7 +825,7 @@ static bool virtual_matches(const struct virtual_engine *ve, · 58 unmodified lines
792	* we reuse the register offsets). This is a very small	825	* we reuse the register offsets). This is a very small
793	* hystersis on the greedy seelction algorithm.	826	* hystersis on the greedy seelction algorithm.
794	*/	827	*/
795	inflight = READ_ONCE(ve->context.inflight);	828	inflight = intel_context_inflight(&ve->context);
796	if (inflight && inflight != engine)	829	if (inflight && inflight != engine)
797	return false;	830	return false;
798		831
@@ -815,13 +848,108 @@ static void virtual_xfer_breadcrumbs(struct virtual_engine *ve, · 16 unmodified lines
815	spin_unlock(&old->breadcrumbs.irq_lock);	848	spin_unlock(&old->breadcrumbs.irq_lock);
816	}	849	}
817		850
		851	static struct i915_request *
		852	last_active(const struct intel_engine_execlists *execlists)
		853	{
		854	struct i915_request * const *last = execlists->active;
		855
		856	while (last && i915_request_completed(last))
		857	last++;
		858
		859	return *last;
		860	}
		861
		862	static void defer_request(struct i915_request rq, struct list_head const pl)
		863	{
		864	LIST_HEAD(list);
		865
		866	/*
		867	* We want to move the interrupted request to the back of
		868	* the round-robin list (i.e. its priority level), but
		869	* in doing so, we must then move all requests that were in
		870	* flight and were waiting for the interrupted request to
		871	* be run after it again.
		872	*/
		873	do {
		874	struct i915_dependency *p;
		875
		876	GEM_BUG_ON(i915_request_is_active(rq));
		877	list_move_tail(&rq->sched.link, pl);
		878
		879	list_for_each_entry(p, &rq->sched.waiters_list, wait_link) {
		880	struct i915_request *w =
		881	container_of(p->waiter, typeof(*w), sched);
		882
		883	/* Leave semaphores spinning on the other engines */
		884	if (w->engine != rq->engine)
		885	continue;
		886
		887	/* No waiter should start before its signaler */
		888	GEM_BUG_ON(i915_request_started(w) &&
		889	!i915_request_completed(rq));
		890
		891	GEM_BUG_ON(i915_request_is_active(w));
		892	if (list_empty(&w->sched.link))
		893	continue; /* Not yet submitted; unready */
		894
		895	if (rq_prio(w) < rq_prio(rq))
		896	continue;
		897
		898	GEM_BUG_ON(rq_prio(w) > rq_prio(rq));
		899	list_move_tail(&w->sched.link, &list);
		900	}
		901
		902	rq = list_first_entry_or_null(&list, typeof(*rq), sched.link);
		903	} while (rq);
		904	}
		905
		906	static void defer_active(struct intel_engine_cs *engine)
		907	{
		908	struct i915_request *rq;
		909
		910	rq = __unwind_incomplete_requests(engine);
		911	if (!rq)
		912	return;
		913
		914	defer_request(rq, i915_sched_lookup_priolist(engine, rq_prio(rq)));
		915	}
		916
		917	static bool
		918	need_timeslice(struct intel_engine_cs engine, const struct i915_request rq)
		919	{
		920	int hint;
		921
		922	if (!intel_engine_has_semaphores(engine))
		923	return false;
		924
		925	if (list_is_last(&rq->sched.link, &engine->active.requests))
		926	return false;
		927
		928	hint = max(rq_prio(list_next_entry(rq, sched.link)),
		929	engine->execlists.queue_priority_hint);
		930
		931	return hint >= effective_prio(rq);
		932	}
		933
		934	static bool
		935	enable_timeslice(struct intel_engine_cs *engine)
		936	{
		937	struct i915_request *last = last_active(&engine->execlists);
		938
		939	return last && need_timeslice(engine, last);
		940	}
		941
		942	static void record_preemption(struct intel_engine_execlists *execlists)
		943	{
		944	(void)I915_SELFTEST_ONLY(execlists->preempt_hang.count++);
		945	}
		946
818	static void execlists_dequeue(struct intel_engine_cs *engine)	947	static void execlists_dequeue(struct intel_engine_cs *engine)
819	{	948	{
820	struct intel_engine_execlists * const execlists = &engine->execlists;	949	struct intel_engine_execlists * const execlists = &engine->execlists;
821	struct execlist_port *port = execlists->port;	950	struct i915_request **port = execlists->pending;
822	const struct execlist_port * const last_port =	951	struct i915_request ** const last_port = port + execlists->port_mask;
823	&execlists->port[execlists->port_mask];	952	struct i915_request *last;
824	struct i915_request *last = port_request(port);
825	struct rb_node *rb;	953	struct rb_node *rb;
826	bool submit = false;	954	bool submit = false;
827		955
@@ -867,65 +995,100 @@ static void execlists_dequeue(struct intel_engine_cs *engine) · 39 unmodified lines
867	break;	995	break;
868	}	996	}
869		997
		998	/*
		999	* If the queue is higher priority than the last
		1000	* request in the currently active context, submit afresh.
		1001	* We will resubmit again afterwards in case we need to split
		1002	* the active context to interject the preemption request,
		1003	* i.e. we will retrigger preemption following the ack in case
		1004	* of trouble.
		1005	*/
		1006	last = last_active(execlists);
870	if (last) {	1007	if (last) {
871	/*	1008	if (need_preempt(engine, last, rb)) {
872	* Don't resubmit or switch until all outstanding	1009	GEM_TRACE("%s: preempting last=%llx:%lld, prio=%d, hint=%d\n",
873	* preemptions (lite-restore) are seen. Then we	1010	engine->name,
874	* know the next preemption status we see corresponds	1011	last->fence.context,
875	* to this ELSP update.	1012	last->fence.seqno,
876	*/	1013	last->sched.attr.priority,
877	GEM_BUG_ON(!execlists_is_active(execlists,	1014	execlists->queue_priority_hint);
878	EXECLISTS_ACTIVE_USER));	1015	record_preemption(execlists);
879	GEM_BUG_ON(!port_count(&port[0]));
880		1016
881	/*	1017	/*
882	* If we write to ELSP a second time before the HW has had	1018	* Don't let the RING_HEAD advance past the breadcrumb
883	* a chance to respond to the previous write, we can confuse	1019	* as we unwind (and until we resubmit) so that we do
884	* the HW and hit "undefined behaviour". After writing to ELSP,	1020	* not accidentally tell it to go backwards.
885	* we must then wait until we see a context-switch event from	1021	*/
886	* the HW to indicate that it has had a chance to respond.	1022	ring_set_paused(engine, 1);
887	*/
888	if (!execlists_is_active(execlists, EXECLISTS_ACTIVE_HWACK))
889	return;
890		1023
891	if (need_preempt(engine, last, rb)) {	1024	/*
892	inject_preempt_context(engine);	1025	* Note that we have not stopped the GPU at this point,
893	return;	1026	* so we are unwinding the incomplete requests as they
894	}	1027	* remain inflight and so by the time we do complete
		1028	* the preemption, some of the unwound requests may
		1029	* complete!
		1030	*/
		1031	__unwind_incomplete_requests(engine);
895		1032
896	/*	1033	/*
897	* In theory, we could coalesce more requests onto	1034	* If we need to return to the preempted context, we
898	* the second port (the first port is active, with	1035	* need to skip the lite-restore and force it to
899	* no preemptions pending). However, that means we	1036	* reload the RING_TAIL. Otherwise, the HW has a
900	* then have to deal with the possible lite-restore	1037	* tendency to ignore us rewinding the TAIL to the
901	* of the second port (as we submit the ELSP, there	1038	* end of an earlier request.
902	* may be a context-switch) but also we may complete	1039	*/
903	* the resubmission before the context-switch. Ergo,	1040	last->hw_context->lrc_desc \|= CTX_DESC_FORCE_RESTORE;
904	* coalescing onto the second port will cause a	1041	last = NULL;
905	* preemption event, but we cannot predict whether	1042	} else if (need_timeslice(engine, last) &&
906	* that will affect port[0] or port[1].	1043	!timer_pending(&engine->execlists.timer)) {
907	*	1044	GEM_TRACE("%s: expired last=%llx:%lld, prio=%d, hint=%d\n",
908	* If the second port is already active, we can wait	1045	engine->name,
909	* until the next context-switch before contemplating	1046	last->fence.context,
910	* new requests. The GPU will be busy and we should be	1047	last->fence.seqno,
911	* able to resubmit the new ELSP before it idles,	1048	last->sched.attr.priority,
912	* avoiding pipeline bubbles (momentary pauses where	1049	execlists->queue_priority_hint);
913	* the driver is unable to keep up the supply of new
914	* work). However, we have to double check that the
915	* priorities of the ports haven't been switch.
916	*/
917	if (port_count(&port[1]))
918	return;
919		1050
920	/*	1051	ring_set_paused(engine, 1);
921	* WaIdleLiteRestore:bdw,skl	1052	defer_active(engine);
922	* Apply the wa NOOPs to prevent	1053
923	* ring:HEAD == rq:TAIL as we resubmit the	1054	/*
924	* request. See gen8_emit_fini_breadcrumb() for	1055	* Unlike for preemption, if we rewind and continue
925	* where we prepare the padding after the	1056	* executing the same context as previously active,
926	* end of the request.	1057	* the order of execution will remain the same and
927	*/	1058	* the tail will only advance. We do not need to
928	last->tail = last->wa_tail;	1059	* force a full context restore, as a lite-restore
		1060	* is sufficient to resample the monotonic TAIL.
		1061	*
		1062	* If we switch to any other context, similarly we
		1063	* will not rewind TAIL of current context, and
		1064	* normal save/restore will preserve state and allow
		1065	* us to later continue executing the same request.
		1066	*/
		1067	last = NULL;
		1068	} else {
		1069	/*
		1070	* Otherwise if we already have a request pending
		1071	* for execution after the current one, we can
		1072	* just wait until the next CS event before
		1073	* queuing more. In either case we will force a
		1074	* lite-restore preemption event, but if we wait
		1075	* we hopefully coalesce several updates into a single
		1076	* submission.
		1077	*/
		1078	if (!list_is_last(&last->sched.link,
		1079	&engine->active.requests))
		1080	return;
		1081
		1082	/*
		1083	* WaIdleLiteRestore:bdw,skl
		1084	* Apply the wa NOOPs to prevent
		1085	* ring:HEAD == rq:TAIL as we resubmit the
		1086	* request. See gen8_emit_fini_breadcrumb() for
		1087	* where we prepare the padding after the
		1088	* end of the request.
		1089	*/
		1090	last->tail = last->wa_tail;
		1091	}
929	}	1092	}
930		1093
931	while (rb) { /* XXX virtual is always taking precedence */	1094	while (rb) { /* XXX virtual is always taking precedence */
@@ -955,9 +1118,24 @@ static void execlists_dequeue(struct intel_engine_cs *engine) · 23 unmodified lines
955	continue;	1118	continue;
956	}	1119	}
957		1120
		1121	if (i915_request_completed(rq)) {
		1122	ve->request = NULL;
		1123	ve->base.execlists.queue_priority_hint = INT_MIN;
		1124	rb_erase_cached(rb, &execlists->virtual);
		1125	RB_CLEAR_NODE(rb);
		1126
		1127	rq->engine = engine;
		1128	__i915_request_submit(rq);
		1129
		1130	spin_unlock(&ve->base.active.lock);
		1131
		1132	rb = rb_first_cached(&execlists->virtual);
		1133	continue;
		1134	}
		1135
958	if (last && !can_merge_rq(last, rq)) {	1136	if (last && !can_merge_rq(last, rq)) {
959	spin_unlock(&ve->base.active.lock);	1137	spin_unlock(&ve->base.active.lock);
960	return; /* leave this rq for another engine */	1138	return; /* leave this for another */
961	}	1139	}
962		1140
963	GEM_TRACE("%s: virtual rq=%llx:%lld%s, new engine? %s\n",	1141	GEM_TRACE("%s: virtual rq=%llx:%lld%s, new engine? %s\n",
@@ -1006,9 +1184,10 @@ static void execlists_dequeue(struct intel_engine_cs *engine) · 42 unmodified lines
1006	}	1184	}
1007		1185
1008	__i915_request_submit(rq);	1186	__i915_request_submit(rq);
1009	trace_i915_request_in(rq, port_index(port, execlists));	1187	if (!i915_request_completed(rq)) {
1010	submit = true;	1188	submit = true;
1011	last = rq;	1189	last = rq;
		1190	}
1012	}	1191	}
1013		1192
1014	spin_unlock(&ve->base.active.lock);	1193	spin_unlock(&ve->base.active.lock);
@@ -1021,6 +1200,9 @@ static void execlists_dequeue(struct intel_engine_cs *engine) · 6 unmodified lines
1021	int i;	1200	int i;
1022		1201
1023	priolist_for_each_request_consume(rq, rn, p, i) {	1202	priolist_for_each_request_consume(rq, rn, p, i) {
		1203	if (i915_request_completed(rq))
		1204	goto skip;
		1205
1024	/*	1206	/*
1025	* Can we combine this request with the current port?	1207	* Can we combine this request with the current port?
1026	* It has to be the same context/ringbuffer and not	1208	* It has to be the same context/ringbuffer and not
@@ -1060,19 +1242,14 @@ static void execlists_dequeue(struct intel_engine_cs *engine) · 33 unmodified lines
1060	ctx_single_port_submission(rq->hw_context))	1242	ctx_single_port_submission(rq->hw_context))
1061	goto done;	1243	goto done;
1062		1244
1063		1245	*port = execlists_schedule_in(last, port - execlists->pending);
1064	if (submit)
1065	port_assign(port, last);
1066	port++;	1246	port++;
1067
1068	GEM_BUG_ON(port_isset(port));
1069	}	1247	}
1070		1248
1071	__i915_request_submit(rq);
1072	trace_i915_request_in(rq, port_index(port, execlists));
1073
1074	last = rq;	1249	last = rq;
1075	submit = true;	1250	submit = true;
		1251	skip:
		1252	__i915_request_submit(rq);
1076	}	1253	}
1077		1254
1078	rb_erase_cached(&p->node, &execlists->queue);	1255	rb_erase_cached(&p->node, &execlists->queue);
@@ -1097,54 +1274,32 @@ done: · 18 unmodified lines
1097	* interrupt for secondary ports).	1274	* interrupt for secondary ports).
1098	*/	1275	*/
1099	execlists->queue_priority_hint = queue_prio(execlists);	1276	execlists->queue_priority_hint = queue_prio(execlists);
		1277	GEM_TRACE("%s: queue_priority_hint:%d, submit:%s\n",
		1278	engine->name, execlists->queue_priority_hint,
		1279	yesno(submit));
1100		1280
1101	if (submit) {	1281	if (submit) {
1102	port_assign(port, last);	1282	*port = execlists_schedule_in(last, port - execlists->pending);
		1283	memset(port + 1, 0, (last_port - port) * sizeof(*port));
1103	execlists_submit_ports(engine);	1284	execlists_submit_ports(engine);
		1285	} else {
		1286	ring_set_paused(engine, 0);
1104	}	1287	}
1105
1106	/* We must always keep the beast fed if we have work piled up */
1107	GEM_BUG_ON(rb_first_cached(&execlists->queue) &&
1108	!port_isset(execlists->port));
1109
1110	/* Re-evaluate the executing context setup after each preemptive kick */
1111	if (last)
1112	execlists_user_begin(execlists, execlists->port);
1113
1114	/* If the engine is now idle, so should be the flag; and vice versa. */
1115	GEM_BUG_ON(execlists_is_active(&engine->execlists,
1116	EXECLISTS_ACTIVE_USER) ==
1117	!port_isset(engine->execlists.port));
1118	}	1288	}
1119		1289
1120	void	1290	void
1121	execlists_cancel_port_requests(struct intel_engine_execlists * const execlists)	1291	execlists_cancel_port_requests(struct intel_engine_execlists * const execlists)
1122	{	1292	{
1123	struct execlist_port *port = execlists->port;	1293	struct i915_request * const port, rq;
1124	unsigned int num_ports = execlists_num_ports(execlists);
1125		1294
1126	while (num_ports-- && port_isset(port)) {	1295	for (port = execlists->pending; (rq = *port); port++)
1127	struct i915_request *rq = port_request(port);	1296	execlists_schedule_out(rq);
		1297	memset(execlists->pending, 0, sizeof(execlists->pending));
1128		1298
1129	GEM_TRACE("%s:port%u fence %llx:%lld, (current %d)\n",	1299	for (port = execlists->active; (rq = *port); port++)
1130	rq->engine->name,	1300	execlists_schedule_out(rq);
1131	(unsigned int)(port - execlists->port),	1301	execlists->active =
1132	rq->fence.context, rq->fence.seqno,	1302	memset(execlists->inflight, 0, sizeof(execlists->inflight));
1133	hwsp_seqno(rq));
1134
1135	GEM_BUG_ON(!execlists->active);
1136	execlists_context_schedule_out(rq,
1137	i915_request_completed(rq) ?
1138	INTEL_CONTEXT_SCHEDULE_OUT :
1139	INTEL_CONTEXT_SCHEDULE_PREEMPTED);
1140
1141	i915_request_put(rq);
1142
1143	memset(port, 0, sizeof(*port));
1144	port++;
1145	}
1146
1147	execlists_clear_all_active(execlists);
1148	}	1303	}
1149		1304
1150	static inline void	1305	static inline void
@@ -1160,10 +1315,33 @@ reset_in_progress(const struct intel_engine_execlists *execlists) · 9 unmodified lines
1160	return unlikely(!__tasklet_is_enabled(&execlists->tasklet));	1315	return unlikely(!__tasklet_is_enabled(&execlists->tasklet));
1161	}	1316	}
1162		1317
		1318	enum csb_step {
		1319	CSB_NOP,
		1320	CSB_PROMOTE,
		1321	CSB_PREEMPT,
		1322	CSB_COMPLETE,
		1323	};
		1324
		1325	static inline enum csb_step
		1326	csb_parse(const struct intel_engine_execlists execlists, const u32 csb)
		1327	{
		1328	unsigned int status = *csb;
		1329
		1330	if (status & GEN8_CTX_STATUS_IDLE_ACTIVE)
		1331	return CSB_PROMOTE;
		1332
		1333	if (status & GEN8_CTX_STATUS_PREEMPTED)
		1334	return CSB_PREEMPT;
		1335
		1336	if (*execlists->active)
		1337	return CSB_COMPLETE;
		1338
		1339	return CSB_NOP;
		1340	}
		1341
1163	static void process_csb(struct intel_engine_cs *engine)	1342	static void process_csb(struct intel_engine_cs *engine)
1164	{	1343	{
1165	struct intel_engine_execlists * const execlists = &engine->execlists;	1344	struct intel_engine_execlists * const execlists = &engine->execlists;
1166	struct execlist_port *port = execlists->port;
1167	const u32 * const buf = execlists->csb_status;	1345	const u32 * const buf = execlists->csb_status;
1168	const u8 num_entries = execlists->csb_size;	1346	const u8 num_entries = execlists->csb_size;
1169	u8 head, tail;	1347	u8 head, tail;
@@ -1198,10 +1376,6 @@ static void process_csb(struct intel_engine_cs *engine) · 28 unmodified lines
1198	rmb();	1376	rmb();
1199		1377
1200	do {	1378	do {
1201	struct i915_request *rq;
1202	unsigned int status;
1203	unsigned int count;
1204
1205	if (++head == num_entries)	1379	if (++head == num_entries)
1206	head = 0;	1380	head = 0;
1207		1381
@@ -1223,68 +1397,39 @@ static void process_csb(struct intel_engine_cs *engine) · 15 unmodified lines
1223	* status notifier.	1397	* status notifier.
1224	*/	1398	*/
1225		1399
1226	GEM_TRACE("%s csb[%d]: status=0x%08x:0x%08x, active=0x%x\n",	1400	GEM_TRACE("%s csb[%d]: status=0x%08x:0x%08x\n",
1227	engine->name, head,	1401	engine->name, head,
1228	buf[2 * head + 0], buf[2 * head + 1],	1402	buf[2 * head + 0], buf[2 * head + 1]);
1229	execlists->active);
1230
1231	status = buf[2 * head];
1232	if (status & (GEN8_CTX_STATUS_IDLE_ACTIVE \|
1233	GEN8_CTX_STATUS_PREEMPTED))
1234	execlists_set_active(execlists,
1235	EXECLISTS_ACTIVE_HWACK);
1236	if (status & GEN8_CTX_STATUS_ACTIVE_IDLE)
1237	execlists_clear_active(execlists,
1238	EXECLISTS_ACTIVE_HWACK);
1239
1240	if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK))
1241	continue;
1242		1403
1243	/* We should never get a COMPLETED \| IDLE_ACTIVE! */	1404	switch (csb_parse(execlists, buf + 2 * head)) {
1244	GEM_BUG_ON(status & GEN8_CTX_STATUS_IDLE_ACTIVE);	1405	case CSB_PREEMPT: /* cancel old inflight, prepare for switch */
		1406	trace_ports(execlists, "preempted", execlists->active);
1245		1407
1246	if (status & GEN8_CTX_STATUS_COMPLETE &&	1408	while (*execlists->active)
1247	buf[2*head + 1] == execlists->preempt_complete_status) {	1409	execlists_schedule_out(*execlists->active++);
1248	GEM_TRACE("%s preempt-idle\n", engine->name);
1249	complete_preempt_context(execlists);
1250	continue;
1251	}
1252		1410
1253	if (status & GEN8_CTX_STATUS_PREEMPTED &&	1411	/* fallthrough */
1254	execlists_is_active(execlists,	1412	case CSB_PROMOTE: /* switch pending to inflight */
1255	EXECLISTS_ACTIVE_PREEMPT))	1413	GEM_BUG_ON(*execlists->active);
1256	continue;	1414	GEM_BUG_ON(!assert_pending_valid(execlists, "promote"));
		1415	execlists->active =
		1416	memcpy(execlists->inflight,
		1417	execlists->pending,
		1418	execlists_num_ports(execlists) *
		1419	sizeof(*execlists->pending));
		1420	execlists->pending[0] = NULL;
1257		1421
1258	GEM_BUG_ON(!execlists_is_active(execlists,	1422	trace_ports(execlists, "promoted", execlists->active);
1259	EXECLISTS_ACTIVE_USER));
1260		1423
1261	rq = port_unpack(port, &count);	1424	if (enable_timeslice(engine))
1262	GEM_TRACE("%s out[0]: ctx=%d.%d, fence %llx:%lld (current %d), prio=%d\n",	1425	mod_timer(&execlists->timer, jiffies + 1);
1263	engine->name,
1264	port->context_id, count,
1265	rq ? rq->fence.context : 0,
1266	rq ? rq->fence.seqno : 0,
1267	rq ? hwsp_seqno(rq) : 0,
1268	rq ? rq_prio(rq) : 0);
1269		1426
1270	/* Check the context/desc id for this event matches */	1427	if (!inject_preempt_hang(execlists))
1271	GEM_DEBUG_BUG_ON(buf[2 * head + 1] != port->context_id);	1428	ring_set_paused(engine, 0);
		1429	break;
1272		1430
1273	GEM_BUG_ON(count == 0);	1431	case CSB_COMPLETE: /* port0 completed, advanced to port1 */
1274	if (--count == 0) {	1432	trace_ports(execlists, "completed", execlists->active);
1275	/*
1276	* On the final event corresponding to the
1277	* submission of this context, we expect either
1278	* an element-switch event or a completion
1279	* event (and on completion, the active-idle
1280	* marker). No more preemptions, lite-restore
1281	* or otherwise.
1282	*/
1283	GEM_BUG_ON(status & GEN8_CTX_STATUS_PREEMPTED);
1284	GEM_BUG_ON(port_isset(&port[1]) &&
1285	!(status & GEN8_CTX_STATUS_ELEMENT_SWITCH));
1286	GEM_BUG_ON(!port_isset(&port[1]) &&
1287	!(status & GEN8_CTX_STATUS_ACTIVE_IDLE));
1288		1433
1289	/*	1434	/*
1290	* We rely on the hardware being strongly	1435	* We rely on the hardware being strongly
@@ -1292,22 +1437,16 @@ static void process_csb(struct intel_engine_cs *engine) · 1 unmodified line
1292	* coherent (visible from the CPU) before the	1437	* coherent (visible from the CPU) before the
1293	* user interrupt and CSB is processed.	1438	* user interrupt and CSB is processed.
1294	*/	1439	*/
1295	GEM_BUG_ON(!i915_request_completed(rq));	1440	GEM_BUG_ON(!i915_request_completed(*execlists->active) &&
		1441	!reset_in_progress(execlists));
		1442	execlists_schedule_out(*execlists->active++);
1296		1443
1297	execlists_context_schedule_out(rq,	1444	GEM_BUG_ON(execlists->active - execlists->inflight >
1298	INTEL_CONTEXT_SCHEDULE_OUT);	1445	execlists_num_ports(execlists));
1299	i915_request_put(rq);	1446	break;
1300
1301	GEM_TRACE("%s completed ctx=%d\n",
1302	engine->name, port->context_id);
1303		1447
1304	port = execlists_port_complete(execlists, port);	1448	case CSB_NOP:
1305	if (port_isset(port))	1449	break;
1306	execlists_user_begin(execlists, port);
1307	else
1308	execlists_user_end(execlists);
1309	} else {
1310	port_set(port, port_pack(rq, count));
1311	}	1450	}
1312	} while (head != tail);	1451	} while (head != tail);
1313		1452
@@ -1332,7 +1471,7 @@ static void __execlists_submission_tasklet(struct intel_engine_cs *const engine) · 18 unmodified lines
1332	lockdep_assert_held(&engine->active.lock);	1471	lockdep_assert_held(&engine->active.lock);
1333		1472
1334	process_csb(engine);	1473	process_csb(engine);
1335	if (!execlists_is_active(&engine->execlists, EXECLISTS_ACTIVE_PREEMPT))	1474	if (!engine->execlists.pending[0])
1336	execlists_dequeue(engine);	1475	execlists_dequeue(engine);
1337	}	1476	}
1338		1477
@@ -1345,16 +1484,20 @@ static void execlists_submission_tasklet(unsigned long data) · 6 unmodified lines
1345	struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;	1484	struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
1346	unsigned long flags;	1485	unsigned long flags;
1347		1486
1348	GEM_TRACE("%s awake?=%d, active=%x\n",
1349	engine->name,
1350	!!intel_wakeref_active(&engine->wakeref),
1351	engine->execlists.active);
1352
1353	spin_lock_irqsave(&engine->active.lock, flags);	1487	spin_lock_irqsave(&engine->active.lock, flags);
1354	__execlists_submission_tasklet(engine);	1488	__execlists_submission_tasklet(engine);
1355	spin_unlock_irqrestore(&engine->active.lock, flags);	1489	spin_unlock_irqrestore(&engine->active.lock, flags);
1356	}	1490	}
1357		1491
		1492	static void execlists_submission_timer(struct timer_list *timer)
		1493	{
		1494	struct intel_engine_cs *engine =
		1495	from_timer(engine, timer, execlists.timer);
		1496
		1497	/* Kick the tasklet for some interrupt coalescing and reset handling */
		1498	tasklet_hi_schedule(&engine->execlists.tasklet);
		1499	}
		1500
1358	static void queue_request(struct intel_engine_cs *engine,	1501	static void queue_request(struct intel_engine_cs *engine,
1359	struct i915_sched_node *node,	1502	struct i915_sched_node *node,
1360	int prio)	1503	int prio)
@@ -1376,12 +1519,16 @@ static void __submit_queue_imm(struct intel_engine_cs *engine) · 15 unmodified lines
1376	tasklet_hi_schedule(&execlists->tasklet);	1519	tasklet_hi_schedule(&execlists->tasklet);
1377	}	1520	}
1378		1521
1379	static void submit_queue(struct intel_engine_cs *engine, int prio)	1522	static void submit_queue(struct intel_engine_cs *engine,
		1523	const struct i915_request *rq)
1380	{	1524	{
1381	if (prio > engine->execlists.queue_priority_hint) {	1525	struct intel_engine_execlists *execlists = &engine->execlists;
1382	engine->execlists.queue_priority_hint = prio;	1526
1383	__submit_queue_imm(engine);	1527	if (rq_prio(rq) <= execlists->queue_priority_hint)
1384	}	1528	return;
		1529
		1530	execlists->queue_priority_hint = rq_prio(rq);
		1531	__submit_queue_imm(engine);
1385	}	1532	}
1386		1533
1387	static void execlists_submit_request(struct i915_request *request)	1534	static void execlists_submit_request(struct i915_request *request)
@@ -1397,7 +1544,7 @@ static void execlists_submit_request(struct i915_request *request) · 9 unmodified lines
1397	GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root));	1544	GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root));
1398	GEM_BUG_ON(list_empty(&request->sched.link));	1545	GEM_BUG_ON(list_empty(&request->sched.link));
1399		1546
1400	submit_queue(engine, rq_prio(request));	1547	submit_queue(engine, request);
1401		1548
1402	spin_unlock_irqrestore(&engine->active.lock, flags);	1549	spin_unlock_irqrestore(&engine->active.lock, flags);
1403	}	1550	}
@@ -1405,9 +1552,7 @@ static void execlists_submit_request(struct i915_request *request) · 1 unmodified line
1405	static void __execlists_context_fini(struct intel_context *ce)	1552	static void __execlists_context_fini(struct intel_context *ce)
1406	{	1553	{
1407	intel_ring_put(ce->ring);	1554	intel_ring_put(ce->ring);
1408		1555	i915_vma_put(ce->state);
1409	GEM_BUG_ON(i915_gem_object_is_active(ce->state->obj));
1410	i915_gem_object_put(ce->state->obj);
1411	}	1556	}
1412		1557
1413	static void execlists_context_destroy(struct kref *kref)	1558	static void execlists_context_destroy(struct kref *kref)
@@ -1420,6 +1565,7 @@ static void execlists_context_destroy(struct kref *kref) · 6 unmodified lines
1420	if (ce->state)	1565	if (ce->state)
1421	__execlists_context_fini(ce);	1566	__execlists_context_fini(ce);
1422		1567
		1568	intel_context_fini(ce);
1423	intel_context_free(ce);	1569	intel_context_free(ce);
1424	}	1570	}
1425		1571
@@ -1444,9 +1590,12 @@ __execlists_update_reg_state(struct intel_context *ce, · 18 unmodified lines
1444	regs[CTX_RING_TAIL + 1] = ring->tail;	1590	regs[CTX_RING_TAIL + 1] = ring->tail;
1445		1591
1446	/* RPCS */	1592	/* RPCS */
1447	if (engine->class == RENDER_CLASS)	1593	if (engine->class == RENDER_CLASS) {
1448	regs[CTX_R_PWR_CLK_STATE + 1] =	1594	regs[CTX_R_PWR_CLK_STATE + 1] =
1449	intel_sseu_make_rpcs(engine->i915, &ce->sseu);	1595	intel_sseu_make_rpcs(engine->i915, &ce->sseu);
		1596
		1597	i915_oa_init_reg_state(engine, ce, regs);
		1598	}
1450	}	1599	}
1451		1600
1452	static int	1601	static int
@@ -1456,19 +1605,15 @@ __execlists_context_pin(struct intel_context *ce, · 3 unmodified lines
1456	void *vaddr;	1605	void *vaddr;
1457	int ret;	1606	int ret;
1458		1607
1459	GEM_BUG_ON(!ce->gem_context->vm);
1460
1461	ret = execlists_context_deferred_alloc(ce, engine);	1608	ret = execlists_context_deferred_alloc(ce, engine);
1462	if (ret)	1609	if (ret)
1463	goto err;	1610	goto err;
1464	GEM_BUG_ON(!ce->state);	1611	GEM_BUG_ON(!ce->state);
1465		1612
1466	ret = intel_context_active_acquire(ce,	1613	ret = intel_context_active_acquire(ce);
1467	engine->i915->ggtt.pin_bias \|
1468	PIN_OFFSET_BIAS \|
1469	PIN_HIGH);
1470	if (ret)	1614	if (ret)
1471	goto err;	1615	goto err;
		1616	GEM_BUG_ON(!i915_vma_is_pinned(ce->state));
1472		1617
1473	vaddr = i915_gem_object_pin_map(ce->state->obj,	1618	vaddr = i915_gem_object_pin_map(ce->state->obj,
1474	i915_coherent_map_type(engine->i915) \|	1619	i915_coherent_map_type(engine->i915) \|
@@ -1569,8 +1714,7 @@ static int gen8_emit_init_breadcrumb(struct i915_request *rq) · 94 unmodified lines
1569	static int emit_pdps(struct i915_request *rq)	1714	static int emit_pdps(struct i915_request *rq)
1570	{	1715	{
1571	const struct intel_engine_cs * const engine = rq->engine;	1716	const struct intel_engine_cs * const engine = rq->engine;
1572	struct i915_ppgtt * const ppgtt =	1717	struct i915_ppgtt * const ppgtt = i915_vm_to_ppgtt(rq->hw_context->vm);
1573	i915_vm_to_ppgtt(rq->gem_context->vm);
1574	int err, i;	1718	int err, i;
1575	u32 *cs;	1719	u32 *cs;
1576		1720
@@ -1643,7 +1787,7 @@ static int execlists_request_alloc(struct i915_request *request) · 66 unmodified lines
1643	*/	1787	*/
1644		1788
1645	/* Unconditionally invalidate GPU caches and TLBs. */	1789	/* Unconditionally invalidate GPU caches and TLBs. */
1646	if (i915_vm_is_4lvl(request->gem_context->vm))	1790	if (i915_vm_is_4lvl(request->hw_context->vm))
1647	ret = request->engine->emit_flush(request, EMIT_INVALIDATE);	1791	ret = request->engine->emit_flush(request, EMIT_INVALIDATE);
1648	else	1792	else
1649	ret = emit_pdps(request);	1793	ret = emit_pdps(request);
@@ -1676,7 +1820,8 @@ gen8_emit_flush_coherentl3_wa(struct intel_engine_cs engine, u32 batch) · 26 unmodified lines
1676	/* NB no one else is allowed to scribble over scratch + 256! */	1820	/* NB no one else is allowed to scribble over scratch + 256! */
1677	*batch++ = MI_STORE_REGISTER_MEM_GEN8 \| MI_SRM_LRM_GLOBAL_GTT;	1821	*batch++ = MI_STORE_REGISTER_MEM_GEN8 \| MI_SRM_LRM_GLOBAL_GTT;
1678	*batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);	1822	*batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
1679	*batch++ = i915_scratch_offset(engine->i915) + 256;	1823	*batch++ = intel_gt_scratch_offset(engine->gt,
		1824	INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA);
1680	*batch++ = 0;	1825	*batch++ = 0;
1681		1826
1682	*batch++ = MI_LOAD_REGISTER_IMM(1);	1827	*batch++ = MI_LOAD_REGISTER_IMM(1);
@@ -1690,12 +1835,19 @@ gen8_emit_flush_coherentl3_wa(struct intel_engine_cs engine, u32 batch) · 7 unmodified lines
1690		1835
1691	*batch++ = MI_LOAD_REGISTER_MEM_GEN8 \| MI_SRM_LRM_GLOBAL_GTT;	1836	*batch++ = MI_LOAD_REGISTER_MEM_GEN8 \| MI_SRM_LRM_GLOBAL_GTT;
1692	*batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);	1837	*batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
1693	*batch++ = i915_scratch_offset(engine->i915) + 256;	1838	*batch++ = intel_gt_scratch_offset(engine->gt,
		1839	INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA);
1694	*batch++ = 0;	1840	*batch++ = 0;
1695		1841
1696	return batch;	1842	return batch;
1697	}	1843	}
1698		1844
		1845	static u32 slm_offset(struct intel_engine_cs *engine)
		1846	{
		1847	return intel_gt_scratch_offset(engine->gt,
		1848	INTEL_GT_SCRATCH_FIELD_CLEAR_SLM_WA);
		1849	}
		1850
1699	/*	1851	/*
1700	* Typically we only have one indirect_ctx and per_ctx batch buffer which are	1852	* Typically we only have one indirect_ctx and per_ctx batch buffer which are
1701	* initialized at the beginning and shared across all contexts but this field	1853	* initialized at the beginning and shared across all contexts but this field
@@ -1727,8 +1879,7 @@ static u32 gen8_init_indirectctx_bb(struct intel_engine_cs engine, u32 *batch) · 25 unmodified lines
1727	PIPE_CONTROL_GLOBAL_GTT_IVB \|	1879	PIPE_CONTROL_GLOBAL_GTT_IVB \|
1728	PIPE_CONTROL_CS_STALL \|	1880	PIPE_CONTROL_CS_STALL \|
1729	PIPE_CONTROL_QW_WRITE,	1881	PIPE_CONTROL_QW_WRITE,
1730	i915_scratch_offset(engine->i915) +	1882	slm_offset(engine));
1731	2 * CACHELINE_BYTES);
1732		1883
1733	*batch++ = MI_ARB_ON_OFF \| MI_ARB_ENABLE;	1884	*batch++ = MI_ARB_ON_OFF \| MI_ARB_ENABLE;
1734		1885
@@ -1874,7 +2025,7 @@ static int lrc_setup_wa_ctx(struct intel_engine_cs *engine) · 139 unmodified lines
1874	if (IS_ERR(obj))	2025	if (IS_ERR(obj))
1875	return PTR_ERR(obj);	2026	return PTR_ERR(obj);
1876		2027
1877	vma = i915_vma_instance(obj, &engine->i915->ggtt.vm, NULL);	2028	vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
1878	if (IS_ERR(vma)) {	2029	if (IS_ERR(vma)) {
1879	err = PTR_ERR(vma);	2030	err = PTR_ERR(vma);
1880	goto err;	2031	goto err;
@@ -1970,22 +2121,23 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine) · 89 unmodified lines
1970		2121
1971	static void enable_execlists(struct intel_engine_cs *engine)	2122	static void enable_execlists(struct intel_engine_cs *engine)
1972	{	2123	{
		2124	u32 mode;
		2125
		2126	assert_forcewakes_active(engine->uncore, FORCEWAKE_ALL);
		2127
1973	intel_engine_set_hwsp_writemask(engine, ~0u); /* HWSTAM */	2128	intel_engine_set_hwsp_writemask(engine, ~0u); /* HWSTAM */
1974		2129
1975	if (INTEL_GEN(engine->i915) >= 11)	2130	if (INTEL_GEN(engine->i915) >= 11)
1976	ENGINE_WRITE(engine,	2131	mode = _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE);
1977	RING_MODE_GEN7,
1978	_MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE));
1979	else	2132	else
1980	ENGINE_WRITE(engine,	2133	mode = _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE);
1981	RING_MODE_GEN7,	2134	ENGINE_WRITE_FW(engine, RING_MODE_GEN7, mode);
1982	_MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1983		2135
1984	ENGINE_WRITE(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));	2136	ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
1985		2137
1986	ENGINE_WRITE(engine,	2138	ENGINE_WRITE_FW(engine,
1987	RING_HWS_PGA,	2139	RING_HWS_PGA,
1988	i915_ggtt_offset(engine->status_page.vma));	2140	i915_ggtt_offset(engine->status_page.vma));
1989	ENGINE_POSTING_READ(engine, RING_HWS_PGA);	2141	ENGINE_POSTING_READ(engine, RING_HWS_PGA);
1990	}	2142	}
1991		2143
@@ -1993,7 +2145,7 @@ static bool unexpected_starting_state(struct intel_engine_cs *engine) · 1 unmodified line
1993	{	2145	{
1994	bool unexpected = false;	2146	bool unexpected = false;
1995		2147
1996	if (ENGINE_READ(engine, RING_MI_MODE) & STOP_RING) {	2148	if (ENGINE_READ_FW(engine, RING_MI_MODE) & STOP_RING) {
1997	DRM_DEBUG_DRIVER("STOP_RING still set in RING_MI_MODE\n");	2149	DRM_DEBUG_DRIVER("STOP_RING still set in RING_MI_MODE\n");
1998	unexpected = true;	2150	unexpected = true;
1999	}	2151	}
@@ -2041,34 +2193,32 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine) · 41 unmodified lines
2041	__tasklet_disable_sync_once(&execlists->tasklet);	2193	__tasklet_disable_sync_once(&execlists->tasklet);
2042	GEM_BUG_ON(!reset_in_progress(execlists));	2194	GEM_BUG_ON(!reset_in_progress(execlists));
2043		2195
2044	intel_engine_stop_cs(engine);
2045
2046	/* And flush any current direct submission. */	2196	/* And flush any current direct submission. */
2047	spin_lock_irqsave(&engine->active.lock, flags);	2197	spin_lock_irqsave(&engine->active.lock, flags);
2048	spin_unlock_irqrestore(&engine->active.lock, flags);	2198	spin_unlock_irqrestore(&engine->active.lock, flags);
2049	}
2050
2051	static bool lrc_regs_ok(const struct i915_request *rq)
2052	{
2053	const struct intel_ring *ring = rq->ring;
2054	const u32 *regs = rq->hw_context->lrc_reg_state;
2055
2056	/* Quick spot check for the common signs of context corruption */
2057		2199
2058	if (regs[CTX_RING_BUFFER_CONTROL + 1] !=	2200	/*
2059	(RING_CTL_SIZE(ring->size) \| RING_VALID))	2201	* We stop engines, otherwise we might get failed reset and a
2060	return false;	2202	* dead gpu (on elk). Also as modern gpu as kbl can suffer
2061		2203	* from system hang if batchbuffer is progressing when
2062	if (regs[CTX_RING_BUFFER_START + 1] != i915_ggtt_offset(ring->vma))	2204	* the reset is issued, regardless of READY_TO_RESET ack.
2063	return false;	2205	* Thus assume it is best to stop engines on all gens
2064		2206	* where we have a gpu reset.
2065	return true;	2207	*
		2208	* WaKBLVECSSemaphoreWaitPoll:kbl (on ALL_ENGINES)
		2209	*
		2210	* FIXME: Wa for more modern gens needs to be validated
		2211	*/
		2212	intel_engine_stop_cs(engine);
2066	}	2213	}
2067		2214
2068	static void reset_csb_pointers(struct intel_engine_execlists *execlists)	2215	static void reset_csb_pointers(struct intel_engine_cs *engine)
2069	{	2216	{
		2217	struct intel_engine_execlists * const execlists = &engine->execlists;
2070	const unsigned int reset_value = execlists->csb_size - 1;	2218	const unsigned int reset_value = execlists->csb_size - 1;
2071		2219
		2220	ring_set_paused(engine, 0);
		2221
2072	/*	2222	/*
2073	* After a reset, the HW starts writing into CSB entry [0]. We	2223	* After a reset, the HW starts writing into CSB entry [0]. We
2074	* therefore have to set our HEAD pointer back one entry so that	2224	* therefore have to set our HEAD pointer back one entry so that
@@ -2115,18 +2265,21 @@ static void __execlists_reset(struct intel_engine_cs *engine, bool stalled) · 40 unmodified lines
2115	process_csb(engine); /* drain preemption events */	2265	process_csb(engine); /* drain preemption events */
2116		2266
2117	/* Following the reset, we need to reload the CSB read/write pointers */	2267	/* Following the reset, we need to reload the CSB read/write pointers */
2118	reset_csb_pointers(&engine->execlists);	2268	reset_csb_pointers(engine);
2119		2269
2120	/*	2270	/*
2121	* Save the currently executing context, even if we completed	2271	* Save the currently executing context, even if we completed
2122	* its request, it was still running at the time of the	2272	* its request, it was still running at the time of the
2123	* reset and will have been clobbered.	2273	* reset and will have been clobbered.
2124	*/	2274	*/
2125	if (!port_isset(execlists->port))	2275	rq = execlists_active(execlists);
2126	goto out_clear;	2276	if (!rq)
		2277	goto unwind;
2127		2278
2128	rq = port_request(execlists->port);
2129	ce = rq->hw_context;	2279	ce = rq->hw_context;
		2280	GEM_BUG_ON(i915_active_is_idle(&ce->active));
		2281	GEM_BUG_ON(!i915_vma_is_pinned(ce->state));
		2282	rq = active_request(rq);
2130		2283
2131	/*	2284	/*
2132	* Catch up with any missed context-switch interrupts.	2285	* Catch up with any missed context-switch interrupts.
@@ -2139,9 +2292,12 @@ static void __execlists_reset(struct intel_engine_cs *engine, bool stalled) · 6 unmodified lines
2139	*/	2292	*/
2140	execlists_cancel_port_requests(execlists);	2293	execlists_cancel_port_requests(execlists);
2141		2294
2142	rq = active_request(rq);	2295	if (!rq) {
2143	if (!rq)	2296	ce->ring->head = ce->ring->tail;
2144	goto out_replay;	2297	goto out_replay;
		2298	}
		2299
		2300	ce->ring->head = intel_ring_wrap(ce->ring, rq->head);
2145		2301
2146	/*	2302	/*
2147	* If this request hasn't started yet, e.g. it is waiting on a	2303	* If this request hasn't started yet, e.g. it is waiting on a
@@ -2155,7 +2311,7 @@ static void __execlists_reset(struct intel_engine_cs *engine, bool stalled) · 7 unmodified lines
2155	* Otherwise, if we have not started yet, the request should replay	2311	* Otherwise, if we have not started yet, the request should replay
2156	* perfectly and we do not need to flag the result as being erroneous.	2312	* perfectly and we do not need to flag the result as being erroneous.
2157	*/	2313	*/
2158	if (!i915_request_started(rq) && lrc_regs_ok(rq))	2314	if (!i915_request_started(rq))
2159	goto out_replay;	2315	goto out_replay;
2160		2316
2161	/*	2317	/*
@@ -2169,8 +2325,8 @@ static void __execlists_reset(struct intel_engine_cs *engine, bool stalled) · 7 unmodified lines
2169	* and have to at least restore the RING register in the context	2325	* and have to at least restore the RING register in the context
2170	* image back to the expected values to skip over the guilty request.	2326	* image back to the expected values to skip over the guilty request.
2171	*/	2327	*/
2172	i915_reset_request(rq, stalled);	2328	__i915_request_reset(rq, stalled);
2173	if (!stalled && lrc_regs_ok(rq))	2329	if (!stalled)
2174	goto out_replay;	2330	goto out_replay;
2175		2331
2176	/*	2332	/*
@@ -2190,17 +2346,14 @@ static void __execlists_reset(struct intel_engine_cs *engine, bool stalled) · 13 unmodified lines
2190	execlists_init_reg_state(regs, ce, engine, ce->ring);	2346	execlists_init_reg_state(regs, ce, engine, ce->ring);
2191		2347
2192	out_replay:	2348	out_replay:
2193	/* Rerun the request; its payload has been neutered (if guilty). */	2349	GEM_TRACE("%s replay {head:%04x, tail:%04x\n",
2194	ce->ring->head =	2350	engine->name, ce->ring->head, ce->ring->tail);
2195	rq ? intel_ring_wrap(ce->ring, rq->head) : ce->ring->tail;
2196	intel_ring_update_space(ce->ring);	2351	intel_ring_update_space(ce->ring);
2197	__execlists_update_reg_state(ce, engine);	2352	__execlists_update_reg_state(ce, engine);
2198		2353
		2354	unwind:
2199	/* Push back any incomplete requests for replay after the reset. */	2355	/* Push back any incomplete requests for replay after the reset. */
2200	__unwind_incomplete_requests(engine);	2356	__unwind_incomplete_requests(engine);
2201
2202	out_clear:
2203	execlists_clear_all_active(execlists);
2204	}	2357	}
2205		2358
2206	static void execlists_reset(struct intel_engine_cs *engine, bool stalled)	2359	static void execlists_reset(struct intel_engine_cs *engine, bool stalled)
@@ -2296,7 +2449,6 @@ static void execlists_cancel_requests(struct intel_engine_cs *engine) · 89 unmodified lines
2296		2449
2297	execlists->queue_priority_hint = INT_MIN;	2450	execlists->queue_priority_hint = INT_MIN;
2298	execlists->queue = RB_ROOT_CACHED;	2451	execlists->queue = RB_ROOT_CACHED;
2299	GEM_BUG_ON(port_isset(execlists->port));
2300		2452
2301	GEM_BUG_ON(__tasklet_is_enabled(&execlists->tasklet));	2453	GEM_BUG_ON(__tasklet_is_enabled(&execlists->tasklet));
2302	execlists->tasklet.func = nop_submission_tasklet;	2454	execlists->tasklet.func = nop_submission_tasklet;
@@ -2434,7 +2586,8 @@ static int gen8_emit_flush_render(struct i915_request *request, · 131 unmodified lines
2434	{	2586	{
2435	struct intel_engine_cs *engine = request->engine;	2587	struct intel_engine_cs *engine = request->engine;
2436	u32 scratch_addr =	2588	u32 scratch_addr =
2437	i915_scratch_offset(engine->i915) + 2 * CACHELINE_BYTES;	2589	intel_gt_scratch_offset(engine->gt,
		2590	INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH);
2438	bool vf_flush_wa = false, dc_flush_wa = false;	2591	bool vf_flush_wa = false, dc_flush_wa = false;
2439	u32 *cs, flags = 0;	2592	u32 *cs, flags = 0;
2440	int len;	2593	int len;
@@ -2514,15 +2667,30 @@ static u32 gen8_emit_wa_tail(struct i915_request request, u32 *cs) · 73 unmodified lines
2514	return cs;	2667	return cs;
2515	}	2668	}
2516		2669
		2670	static u32 emit_preempt_busywait(struct i915_request request, u32 *cs)
		2671	{
		2672	*cs++ = MI_SEMAPHORE_WAIT \|
		2673	MI_SEMAPHORE_GLOBAL_GTT \|
		2674	MI_SEMAPHORE_POLL \|
		2675	MI_SEMAPHORE_SAD_EQ_SDD;
		2676	*cs++ = 0;
		2677	*cs++ = intel_hws_preempt_address(request->engine);
		2678	*cs++ = 0;
		2679
		2680	return cs;
		2681	}
		2682
2517	static u32 gen8_emit_fini_breadcrumb(struct i915_request request, u32 *cs)	2683	static u32 gen8_emit_fini_breadcrumb(struct i915_request request, u32 *cs)
2518	{	2684	{
2519	cs = gen8_emit_ggtt_write(cs,	2685	cs = gen8_emit_ggtt_write(cs,
2520	request->fence.seqno,	2686	request->fence.seqno,
2521	request->timeline->hwsp_offset,	2687	request->timeline->hwsp_offset,
2522	0);	2688	0);
2523
2524	*cs++ = MI_USER_INTERRUPT;	2689	*cs++ = MI_USER_INTERRUPT;
		2690
2525	*cs++ = MI_ARB_ON_OFF \| MI_ARB_ENABLE;	2691	*cs++ = MI_ARB_ON_OFF \| MI_ARB_ENABLE;
		2692	if (intel_engine_has_semaphores(request->engine))
		2693	cs = emit_preempt_busywait(request, cs);
2526		2694
2527	request->tail = intel_ring_offset(request, cs);	2695	request->tail = intel_ring_offset(request, cs);
2528	assert_ring_tail_valid(request->ring, request->tail);	2696	assert_ring_tail_valid(request->ring, request->tail);
@@ -2543,9 +2711,11 @@ static u32 gen8_emit_fini_breadcrumb_rcs(struct i915_request request, u32 *cs) · 14 unmodified lines
2543	PIPE_CONTROL_FLUSH_ENABLE \|	2711	PIPE_CONTROL_FLUSH_ENABLE \|
2544	PIPE_CONTROL_CS_STALL,	2712	PIPE_CONTROL_CS_STALL,
2545	0);	2713	0);
2546
2547	*cs++ = MI_USER_INTERRUPT;	2714	*cs++ = MI_USER_INTERRUPT;
		2715
2548	*cs++ = MI_ARB_ON_OFF \| MI_ARB_ENABLE;	2716	*cs++ = MI_ARB_ON_OFF \| MI_ARB_ENABLE;
		2717	if (intel_engine_has_semaphores(request->engine))
		2718	cs = emit_preempt_busywait(request, cs);
2549		2719
2550	request->tail = intel_ring_offset(request, cs);	2720	request->tail = intel_ring_offset(request, cs);
2551	assert_ring_tail_valid(request->ring, request->tail);	2721	assert_ring_tail_valid(request->ring, request->tail);
@@ -2553,27 +2723,9 @@ static u32 gen8_emit_fini_breadcrumb_rcs(struct i915_request request, u32 *cs) · 1 unmodified line
2553	return gen8_emit_wa_tail(request, cs);	2723	return gen8_emit_wa_tail(request, cs);
2554	}	2724	}
2555		2725
2556	static int gen8_init_rcs_context(struct i915_request *rq)
2557	{
2558	int ret;
2559
2560	ret = intel_engine_emit_ctx_wa(rq);
2561	if (ret)
2562	return ret;
2563
2564	ret = intel_rcs_context_init_mocs(rq);
2565	/*
2566	* Failing to program the MOCS is non-fatal.The system will not
2567	* run at peak performance. So generate an error and carry on.
2568	*/
2569	if (ret)
2570	DRM_ERROR("MOCS failed to program: expect performance issues.\n");
2571
2572	return i915_gem_render_state_emit(rq);
2573	}
2574
2575	static void execlists_park(struct intel_engine_cs *engine)	2726	static void execlists_park(struct intel_engine_cs *engine)
2576	{	2727	{
		2728	del_timer_sync(&engine->execlists.timer);
2577	intel_engine_park(engine);	2729	intel_engine_park(engine);
2578	}	2730	}
2579		2731
@@ -2592,11 +2744,11 @@ void intel_execlists_set_default_submission(struct intel_engine_cs *engine) · 12 unmodified lines
2592	engine->unpark = NULL;	2744	engine->unpark = NULL;
2593		2745
2594	engine->flags \|= I915_ENGINE_SUPPORTS_STATS;	2746	engine->flags \|= I915_ENGINE_SUPPORTS_STATS;
2595	if (!intel_vgpu_active(engine->i915))	2747	if (!intel_vgpu_active(engine->i915)) {
2596	engine->flags \|= I915_ENGINE_HAS_SEMAPHORES;	2748	engine->flags \|= I915_ENGINE_HAS_SEMAPHORES;
2597	if (engine->preempt_context &&	2749	if (HAS_LOGICAL_RING_PREEMPTION(engine->i915))
2598	HAS_LOGICAL_RING_PREEMPTION(engine->i915))	2750	engine->flags \|= I915_ENGINE_HAS_PREEMPTION;
2599	engine->flags \|= I915_ENGINE_HAS_PREEMPTION;	2751	}
2600	}	2752	}
2601		2753
2602	static void execlists_destroy(struct intel_engine_cs *engine)	2754	static void execlists_destroy(struct intel_engine_cs *engine)
@@ -2672,12 +2824,12 @@ int intel_execlists_submission_setup(struct intel_engine_cs *engine) · 69 unmodified lines
2672		2824
2673	tasklet_init(&engine->execlists.tasklet,	2825	tasklet_init(&engine->execlists.tasklet,
2674	execlists_submission_tasklet, (unsigned long)engine);	2826	execlists_submission_tasklet, (unsigned long)engine);
		2827	timer_setup(&engine->execlists.timer, execlists_submission_timer, 0);
2675		2828
2676	logical_ring_default_vfuncs(engine);	2829	logical_ring_default_vfuncs(engine);
2677	logical_ring_default_irqs(engine);	2830	logical_ring_default_irqs(engine);
2678		2831
2679	if (engine->class == RENDER_CLASS) {	2832	if (engine->class == RENDER_CLASS) {
2680	engine->init_context = gen8_init_rcs_context;
2681	engine->emit_flush = gen8_emit_flush_render;	2833	engine->emit_flush = gen8_emit_flush_render;
2682	engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_rcs;	2834	engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_rcs;
2683	}	2835	}
@@ -2697,9 +2849,6 @@ int intel_execlists_submission_init(struct intel_engine_cs *engine) · 13 unmodified lines
2697	if (ret)	2849	if (ret)
2698	return ret;	2850	return ret;
2699		2851
2700	intel_engine_init_workarounds(engine);
2701	intel_engine_init_whitelist(engine);
2702
2703	if (intel_init_workaround_bb(engine))	2852	if (intel_init_workaround_bb(engine))
2704	/*	2853	/*
2705	* We continue even if we fail to initialize WA batch	2854	* We continue even if we fail to initialize WA batch
@@ -2718,11 +2867,6 @@ int intel_execlists_submission_init(struct intel_engine_cs *engine) · 12 unmodified lines
2718	i915_mmio_reg_offset(RING_ELSP(base));	2867	i915_mmio_reg_offset(RING_ELSP(base));
2719	}	2868	}
2720		2869
2721	execlists->preempt_complete_status = ~0u;
2722	if (engine->preempt_context)
2723	execlists->preempt_complete_status =
2724	upper_32_bits(engine->preempt_context->lrc_desc);
2725
2726	execlists->csb_status =	2870	execlists->csb_status =
2727	&engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX];	2871	&engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX];
2728		2872
@@ -2734,7 +2878,7 @@ int intel_execlists_submission_init(struct intel_engine_cs *engine) · 5 unmodified lines
2734	else	2878	else
2735	execlists->csb_size = GEN11_CSB_ENTRIES;	2879	execlists->csb_size = GEN11_CSB_ENTRIES;
2736		2880
2737	reset_csb_pointers(execlists);	2881	reset_csb_pointers(engine);
2738		2882
2739	return 0;	2883	return 0;
2740	}	2884	}
@@ -2773,7 +2917,7 @@ static void execlists_init_reg_state(u32 *regs, · 32 unmodified lines
2773	struct intel_engine_cs *engine,	2917	struct intel_engine_cs *engine,
2774	struct intel_ring *ring)	2918	struct intel_ring *ring)
2775	{	2919	{
2776	struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(ce->gem_context->vm);	2920	struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(ce->vm);
2777	bool rcs = engine->class == RENDER_CLASS;	2921	bool rcs = engine->class == RENDER_CLASS;
2778	u32 base = engine->mmio_base;	2922	u32 base = engine->mmio_base;
2779		2923
@@ -2864,8 +3008,6 @@ static void execlists_init_reg_state(u32 *regs, · 84 unmodified lines
2864	if (rcs) {	3008	if (rcs) {
2865	regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);	3009	regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
2866	CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, 0);	3010	CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, 0);
2867
2868	i915_oa_init_reg_state(engine, ce, regs);
2869	}	3011	}
2870		3012
2871	regs[CTX_END] = MI_BATCH_BUFFER_END;	3013	regs[CTX_END] = MI_BATCH_BUFFER_END;
@@ -2917,11 +3059,6 @@ populate_lr_context(struct intel_context *ce, · 45 unmodified lines
2917	if (!engine->default_state)	3059	if (!engine->default_state)
2918	regs[CTX_CONTEXT_CONTROL + 1] \|=	3060	regs[CTX_CONTEXT_CONTROL + 1] \|=
2919	_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);	3061	_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
2920	if (ce->gem_context == engine->i915->preempt_context &&
2921	INTEL_GEN(engine->i915) < 11)
2922	regs[CTX_CONTEXT_CONTROL + 1] \|=
2923	_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT \|
2924	CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT);
2925		3062
2926	ret = 0;	3063	ret = 0;
2927	err_unpin_ctx:	3064	err_unpin_ctx:
@@ -2932,12 +3069,13 @@ err_unpin_ctx: · 4 unmodified lines
2932	return ret;	3069	return ret;
2933	}	3070	}
2934		3071
2935	static struct i915_timeline get_timeline(struct i915_gem_context ctx)	3072	static struct intel_timeline *
		3073	get_timeline(struct i915_gem_context ctx, struct intel_gt gt)
2936	{	3074	{
2937	if (ctx->timeline)	3075	if (ctx->timeline)
2938	return i915_timeline_get(ctx->timeline);	3076	return intel_timeline_get(ctx->timeline);
2939	else	3077	else
2940	return i915_timeline_create(ctx->i915, NULL);	3078	return intel_timeline_create(gt, NULL);
2941	}	3079	}
2942		3080
2943	static int execlists_context_deferred_alloc(struct intel_context *ce,	3081	static int execlists_context_deferred_alloc(struct intel_context *ce,
@@ -2947,7 +3085,7 @@ static int execlists_context_deferred_alloc(struct intel_context *ce, · 3 unmodified lines
2947	struct i915_vma *vma;	3085	struct i915_vma *vma;
2948	u32 context_size;	3086	u32 context_size;
2949	struct intel_ring *ring;	3087	struct intel_ring *ring;
2950	struct i915_timeline *timeline;	3088	struct intel_timeline *timeline;
2951	int ret;	3089	int ret;
2952		3090
2953	if (ce->state)	3091	if (ce->state)
@@ -2965,13 +3103,13 @@ static int execlists_context_deferred_alloc(struct intel_context *ce, · 11 unmodified lines
2965	if (IS_ERR(ctx_obj))	3103	if (IS_ERR(ctx_obj))
2966	return PTR_ERR(ctx_obj);	3104	return PTR_ERR(ctx_obj);
2967		3105
2968	vma = i915_vma_instance(ctx_obj, &engine->i915->ggtt.vm, NULL);	3106	vma = i915_vma_instance(ctx_obj, &engine->gt->ggtt->vm, NULL);
2969	if (IS_ERR(vma)) {	3107	if (IS_ERR(vma)) {
2970	ret = PTR_ERR(vma);	3108	ret = PTR_ERR(vma);
2971	goto error_deref_obj;	3109	goto error_deref_obj;
2972	}	3110	}
2973		3111
2974	timeline = get_timeline(ce->gem_context);	3112	timeline = get_timeline(ce->gem_context, engine->gt);
2975	if (IS_ERR(timeline)) {	3113	if (IS_ERR(timeline)) {
2976	ret = PTR_ERR(timeline);	3114	ret = PTR_ERR(timeline);
2977	goto error_deref_obj;	3115	goto error_deref_obj;
@@ -2980,7 +3118,7 @@ static int execlists_context_deferred_alloc(struct intel_context *ce, · 2 unmodified lines
2980	ring = intel_engine_create_ring(engine,	3118	ring = intel_engine_create_ring(engine,
2981	timeline,	3119	timeline,
2982	ce->gem_context->ring_size);	3120	ce->gem_context->ring_size);
2983	i915_timeline_put(timeline);	3121	intel_timeline_put(timeline);
2984	if (IS_ERR(ring)) {	3122	if (IS_ERR(ring)) {
2985	ret = PTR_ERR(ring);	3123	ret = PTR_ERR(ring);
2986	goto error_deref_obj;	3124	goto error_deref_obj;
@@ -3038,6 +3176,7 @@ static void virtual_context_destroy(struct kref *kref) · 51 unmodified lines
3038		3176
3039	if (ve->context.state)	3177	if (ve->context.state)
3040	__execlists_context_fini(&ve->context);	3178	__execlists_context_fini(&ve->context);
		3179	intel_context_fini(&ve->context);
3041		3180
3042	kfree(ve->bonds);	3181	kfree(ve->bonds);
3043	kfree(ve);	3182	kfree(ve);
@@ -3290,11 +3429,11 @@ intel_execlists_create_virtual(struct i915_gem_context *ctx, · 246 unmodified lines
3290	return ERR_PTR(-ENOMEM);	3429	return ERR_PTR(-ENOMEM);
3291		3430
3292	ve->base.i915 = ctx->i915;	3431	ve->base.i915 = ctx->i915;
		3432	ve->base.gt = siblings[0]->gt;
3293	ve->base.id = -1;	3433	ve->base.id = -1;
3294	ve->base.class = OTHER_CLASS;	3434	ve->base.class = OTHER_CLASS;
3295	ve->base.uabi_class = I915_ENGINE_CLASS_INVALID;	3435	ve->base.uabi_class = I915_ENGINE_CLASS_INVALID;
3296	ve->base.instance = I915_ENGINE_CLASS_INVALID_VIRTUAL;	3436	ve->base.instance = I915_ENGINE_CLASS_INVALID_VIRTUAL;
3297	ve->base.flags = I915_ENGINE_IS_VIRTUAL;
3298		3437
3299	/*	3438	/*
3300	* The decision on whether to submit a request using semaphores	3439	* The decision on whether to submit a request using semaphores
@@ -3391,8 +3530,12 @@ intel_execlists_create_virtual(struct i915_gem_context *ctx, · 90 unmodified lines
3391	ve->base.emit_fini_breadcrumb = sibling->emit_fini_breadcrumb;	3530	ve->base.emit_fini_breadcrumb = sibling->emit_fini_breadcrumb;
3392	ve->base.emit_fini_breadcrumb_dw =	3531	ve->base.emit_fini_breadcrumb_dw =
3393	sibling->emit_fini_breadcrumb_dw;	3532	sibling->emit_fini_breadcrumb_dw;
		3533
		3534	ve->base.flags = sibling->flags;
3394	}	3535	}
3395		3536
		3537	ve->base.flags \|= I915_ENGINE_IS_VIRTUAL;
		3538
3396	return &ve->context;	3539	return &ve->context;
3397		3540
3398	err_put:	3541	err_put:

drivers/gpu/drm/i915/gt/intel_mocs.c+40−22

 #include "i915_drv.h"
 #include "intel_engine.h"
+#include "intel_gt.h"
 #include "intel_mocs.h"
 #include "intel_lrc.h"
 /**
  * get_mocs_settings()
- * @dev_priv:	i915 device.
+ * @gt:		gt device
  * @table:      Output table that will be made to point at appropriate
  *	      MOCS values for the device.
  *
  *
  * Return: true if there are applicable MOCS settings for the device.
  */
-static bool get_mocs_settings(struct drm_i915_private *dev_priv,
+static bool get_mocs_settings(struct intel_gt *gt,
 			      struct drm_i915_mocs_table *table)
 {
+	struct drm_i915_private *i915 = gt->i915;
 	bool result = false;
-	if (INTEL_GEN(dev_priv) >= 11) {
+	if (INTEL_GEN(i915) >= 11) {
 		table->size  = ARRAY_SIZE(icelake_mocs_table);
 		table->table = icelake_mocs_table;
 		table->n_entries = GEN11_NUM_MOCS_ENTRIES;
 		result = true;
-	} else if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
+	} else if (IS_GEN9_BC(i915) || IS_CANNONLAKE(i915)) {
 		table->size  = ARRAY_SIZE(skylake_mocs_table);
 		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
 		table->table = skylake_mocs_table;
 		result = true;
-	} else if (IS_GEN9_LP(dev_priv)) {
+	} else if (IS_GEN9_LP(i915)) {
 		table->size  = ARRAY_SIZE(broxton_mocs_table);
 		table->n_entries = GEN9_NUM_MOCS_ENTRIES;
 		table->table = broxton_mocs_table;
 		result = true;
 	} else {
-		WARN_ONCE(INTEL_GEN(dev_priv) >= 9,
+		WARN_ONCE(INTEL_GEN(i915) >= 9,
 			  "Platform that should have a MOCS table does not.\n");
 	}
 	/* WaDisableSkipCaching:skl,bxt,kbl,glk */
-	if (IS_GEN(dev_priv, 9)) {
+	if (IS_GEN(i915, 9)) {
 		int i;
 		for (i = 0; i < table->size; i++)
  */
 void intel_mocs_init_engine(struct intel_engine_cs *engine)
 {
-	struct drm_i915_private *dev_priv = engine->i915;
+	struct intel_gt *gt = engine->gt;
+	struct intel_uncore *uncore = gt->uncore;
 	struct drm_i915_mocs_table table;
 	unsigned int index;
 	u32 unused_value;
-	if (!get_mocs_settings(dev_priv, &table))
+	/* Called under a blanket forcewake */
+	assert_forcewakes_active(uncore, FORCEWAKE_ALL);
+	if (!get_mocs_settings(gt, &table))
 		return;
 	/* Set unused values to PTE */
 	for (index = 0; index < table.size; index++) {
 		u32 value = get_entry_control(&table, index);
-		I915_WRITE(mocs_register(engine->id, index), value);
+		intel_uncore_write_fw(uncore,
+				      mocs_register(engine->id, index),
+				      value);
 	}
 	/* All remaining entries are also unused */
 	for (; index < table.n_entries; index++)
-		I915_WRITE(mocs_register(engine->id, index), unused_value);
+		intel_uncore_write_fw(uncore,
+				      mocs_register(engine->id, index),
+				      unused_value);
 }
 /**
 /**
  * intel_mocs_init_l3cc_table() - program the mocs control table
- * @dev_priv:      i915 device private
+ * @gt: the intel_gt container
  *
  * This function simply programs the mocs registers for the given table
  * starting at the given address. This register set is  programmed in pairs.
  *
  * Return: Nothing.
  */
-void intel_mocs_init_l3cc_table(struct drm_i915_private *dev_priv)
+void intel_mocs_init_l3cc_table(struct intel_gt *gt)
 {
+	struct intel_uncore *uncore = gt->uncore;
 	struct drm_i915_mocs_table table;
 	unsigned int i;
 	u16 unused_value;
-	if (!get_mocs_settings(dev_priv, &table))
+	if (!get_mocs_settings(gt, &table))
 		return;
 	/* Set unused values to PTE */
 		u16 low = get_entry_l3cc(&table, 2 * i);
 		u16 high = get_entry_l3cc(&table, 2 * i + 1);
-		I915_WRITE(GEN9_LNCFCMOCS(i),
+		intel_uncore_write(uncore,
-			   l3cc_combine(&table, low, high));
+				   GEN9_LNCFCMOCS(i),
+				   l3cc_combine(&table, low, high));
 	}
 	/* Odd table size - 1 left over */
 	if (table.size & 0x01) {
 		u16 low = get_entry_l3cc(&table, 2 * i);
-		I915_WRITE(GEN9_LNCFCMOCS(i),
+		intel_uncore_write(uncore,
-			   l3cc_combine(&table, low, unused_value));
+				   GEN9_LNCFCMOCS(i),
+				   l3cc_combine(&table, low, unused_value));
 		i++;
 	}
 	/* All remaining entries are also unused */
 	for (; i < table.n_entries / 2; i++)
-		I915_WRITE(GEN9_LNCFCMOCS(i),
+		intel_uncore_write(uncore,
-			   l3cc_combine(&table, unused_value, unused_value));
+				   GEN9_LNCFCMOCS(i),
+				   l3cc_combine(&table, unused_value,
+						unused_value));
 }
 /**
  *
  * Return: 0 on success, otherwise the error status.
  */
-int intel_rcs_context_init_mocs(struct i915_request *rq)
+int intel_mocs_emit(struct i915_request *rq)
 {
 	struct drm_i915_mocs_table t;
 	int ret;
-	if (get_mocs_settings(rq->i915, &t)) {
+	if (rq->engine->class != RENDER_CLASS)
+		return 0;
+	if (get_mocs_settings(rq->engine->gt, &t)) {
 		/* Program the RCS control registers */
 		ret = emit_mocs_control_table(rq, &t);
 		if (ret)

drivers/gpu/drm/i915/gt/intel_mocs.h+4−2

 struct drm_i915_private;
 struct i915_request;
 struct intel_engine_cs;
+struct intel_gt;
-int intel_rcs_context_init_mocs(struct i915_request *rq);
+void intel_mocs_init_l3cc_table(struct intel_gt *gt);
-void intel_mocs_init_l3cc_table(struct drm_i915_private *dev_priv);
 void intel_mocs_init_engine(struct intel_engine_cs *engine);
+int intel_mocs_emit(struct i915_request *rq);
 #endif

drivers/gpu/drm/i915/gt/intel_renderstate.crenamed from drivers/gpu/drm/i915/i915_gem_render_state.c+6−7

  */
 #include "i915_drv.h"
-#include "i915_gem_render_state.h"
 #include "intel_renderstate.h"
-struct intel_render_state {
+struct intel_renderstate {
 	const struct intel_renderstate_rodata *rodata;
 	struct drm_i915_gem_object *obj;
 	struct i915_vma *vma;
 static const struct intel_renderstate_rodata *
 render_state_get_rodata(const struct intel_engine_cs *engine)
 {
-	if (engine->id != RCS0)
+	if (engine->class != RENDER_CLASS)
 		return NULL;
 	switch (INTEL_GEN(engine->i915)) {
 		(batch)[(i)++] = (val);				\
 	} while(0)
-static int render_state_setup(struct intel_render_state *so,
+static int render_state_setup(struct intel_renderstate *so,
 			      struct drm_i915_private *i915)
 {
 	const struct intel_renderstate_rodata *rodata = so->rodata;
 #undef OUT_BATCH
-int i915_gem_render_state_emit(struct i915_request *rq)
+int intel_renderstate_emit(struct i915_request *rq)
 {
 	struct intel_engine_cs *engine = rq->engine;
-	struct intel_render_state so = {}; /* keep the compiler happy */
+	struct intel_renderstate so = {}; /* keep the compiler happy */
 	int err;
 	so.rodata = render_state_get_rodata(engine);
 	if (IS_ERR(so.obj))
 		return PTR_ERR(so.obj);
-	so.vma = i915_vma_instance(so.obj, &engine->i915->ggtt.vm, NULL);
+	so.vma = i915_vma_instance(so.obj, &engine->gt->ggtt->vm, NULL);
 	if (IS_ERR(so.vma)) {
 		err = PTR_ERR(so.vma);
 		goto err_obj;

drivers/gpu/drm/i915/gt/intel_renderstate.hrenamed from drivers/gpu/drm/i915/intel_renderstate.h+7−3

  * DEALINGS IN THE SOFTWARE.
  */
-#ifndef _INTEL_RENDERSTATE_H
+#ifndef _INTEL_RENDERSTATE_H_
-#define _INTEL_RENDERSTATE_H
+#define _INTEL_RENDERSTATE_H_
 #include <linux/types.h>
+struct i915_request;
 struct intel_renderstate_rodata {
 	const u32 *reloc;
 	const u32 *batch;
 extern const struct intel_renderstate_rodata gen8_null_state;
 extern const struct intel_renderstate_rodata gen9_null_state;
-#endif /* INTEL_RENDERSTATE_H */
+int intel_renderstate_emit(struct i915_request *rq);
+#endif /* _INTEL_RENDERSTATE_H_ */

drivers/gpu/drm/i915/gt/intel_reset.c+218−406

@@ -15,26 +15,17 @@ · 14 unmodified lines
15	#include "i915_gpu_error.h"	15	#include "i915_gpu_error.h"
16	#include "i915_irq.h"	16	#include "i915_irq.h"
17	#include "intel_engine_pm.h"	17	#include "intel_engine_pm.h"
		18	#include "intel_gt.h"
18	#include "intel_gt_pm.h"	19	#include "intel_gt_pm.h"
19	#include "intel_reset.h"	20	#include "intel_reset.h"
20		21
21	#include "intel_guc.h"	22	#include "uc/intel_guc.h"
22		23
23	#define RESET_MAX_RETRIES 3	24	#define RESET_MAX_RETRIES 3
24		25
25	/* XXX How to handle concurrent GGTT updates using tiling registers? */	26	/* XXX How to handle concurrent GGTT updates using tiling registers? */
26	#define RESET_UNDER_STOP_MACHINE 0	27	#define RESET_UNDER_STOP_MACHINE 0
27		28
28	static void rmw_set(struct intel_uncore *uncore, i915_reg_t reg, u32 set)
29	{
30	intel_uncore_rmw(uncore, reg, 0, set);
31	}
32
33	static void rmw_clear(struct intel_uncore *uncore, i915_reg_t reg, u32 clr)
34	{
35	intel_uncore_rmw(uncore, reg, clr, 0);
36	}
37
38	static void rmw_set_fw(struct intel_uncore *uncore, i915_reg_t reg, u32 set)	29	static void rmw_set_fw(struct intel_uncore *uncore, i915_reg_t reg, u32 set)
39	{	30	{
40	intel_uncore_rmw_fw(uncore, reg, 0, set);	31	intel_uncore_rmw_fw(uncore, reg, 0, set);
@@ -123,7 +114,7 @@ static void context_mark_innocent(struct i915_gem_context *ctx) · 82 unmodified lines
123	atomic_inc(&ctx->active_count);	114	atomic_inc(&ctx->active_count);
124	}	115	}
125		116
126	void i915_reset_request(struct i915_request *rq, bool guilty)	117	void __i915_request_reset(struct i915_request *rq, bool guilty)
127	{	118	{
128	GEM_TRACE("%s rq=%llx:%lld, guilty? %s\n",	119	GEM_TRACE("%s rq=%llx:%lld, guilty? %s\n",
129	rq->engine->name,	120	rq->engine->name,
@@ -144,48 +135,6 @@ void i915_reset_request(struct i915_request *rq, bool guilty) · 14 unmodified lines
144	}	135	}
145	}	136	}
146		137
147	static void gen3_stop_engine(struct intel_engine_cs *engine)
148	{
149	struct intel_uncore *uncore = engine->uncore;
150	const u32 base = engine->mmio_base;
151
152	GEM_TRACE("%s\n", engine->name);
153
154	if (intel_engine_stop_cs(engine))
155	GEM_TRACE("%s: timed out on STOP_RING\n", engine->name);
156
157	intel_uncore_write_fw(uncore,
158	RING_HEAD(base),
159	intel_uncore_read_fw(uncore, RING_TAIL(base)));
160	intel_uncore_posting_read_fw(uncore, RING_HEAD(base)); /* paranoia */
161
162	intel_uncore_write_fw(uncore, RING_HEAD(base), 0);
163	intel_uncore_write_fw(uncore, RING_TAIL(base), 0);
164	intel_uncore_posting_read_fw(uncore, RING_TAIL(base));
165
166	/* The ring must be empty before it is disabled */
167	intel_uncore_write_fw(uncore, RING_CTL(base), 0);
168
169	/* Check acts as a post */
170	if (intel_uncore_read_fw(uncore, RING_HEAD(base)))
171	GEM_TRACE("%s: ring head [%x] not parked\n",
172	engine->name,
173	intel_uncore_read_fw(uncore, RING_HEAD(base)));
174	}
175
176	static void i915_stop_engines(struct drm_i915_private *i915,
177	intel_engine_mask_t engine_mask)
178	{
179	struct intel_engine_cs *engine;
180	intel_engine_mask_t tmp;
181
182	if (INTEL_GEN(i915) < 3)
183	return;
184
185	for_each_engine_masked(engine, i915, engine_mask, tmp)
186	gen3_stop_engine(engine);
187	}
188
189	static bool i915_in_reset(struct pci_dev *pdev)	138	static bool i915_in_reset(struct pci_dev *pdev)
190	{	139	{
191	u8 gdrst;	140	u8 gdrst;
@@ -194,11 +143,11 @@ static bool i915_in_reset(struct pci_dev *pdev) · 2 unmodified lines
194	return gdrst & GRDOM_RESET_STATUS;	143	return gdrst & GRDOM_RESET_STATUS;
195	}	144	}
196		145
197	static int i915_do_reset(struct drm_i915_private *i915,	146	static int i915_do_reset(struct intel_gt *gt,
198	intel_engine_mask_t engine_mask,	147	intel_engine_mask_t engine_mask,
199	unsigned int retry)	148	unsigned int retry)
200	{	149	{
201	struct pci_dev *pdev = i915->drm.pdev;	150	struct pci_dev *pdev = gt->i915->drm.pdev;
202	int err;	151	int err;
203		152
204	/* Assert reset for at least 20 usec, and wait for acknowledgement. */	153	/* Assert reset for at least 20 usec, and wait for acknowledgement. */
@@ -223,22 +172,22 @@ static bool g4x_reset_complete(struct pci_dev *pdev) · 18 unmodified lines
223	return (gdrst & GRDOM_RESET_ENABLE) == 0;	172	return (gdrst & GRDOM_RESET_ENABLE) == 0;
224	}	173	}
225		174
226	static int g33_do_reset(struct drm_i915_private *i915,	175	static int g33_do_reset(struct intel_gt *gt,
227	intel_engine_mask_t engine_mask,	176	intel_engine_mask_t engine_mask,
228	unsigned int retry)	177	unsigned int retry)
229	{	178	{
230	struct pci_dev *pdev = i915->drm.pdev;	179	struct pci_dev *pdev = gt->i915->drm.pdev;
231		180
232	pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);	181	pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
233	return wait_for_atomic(g4x_reset_complete(pdev), 50);	182	return wait_for_atomic(g4x_reset_complete(pdev), 50);
234	}	183	}
235		184
236	static int g4x_do_reset(struct drm_i915_private *i915,	185	static int g4x_do_reset(struct intel_gt *gt,
237	intel_engine_mask_t engine_mask,	186	intel_engine_mask_t engine_mask,
238	unsigned int retry)	187	unsigned int retry)
239	{	188	{
240	struct pci_dev *pdev = i915->drm.pdev;	189	struct pci_dev *pdev = gt->i915->drm.pdev;
241	struct intel_uncore *uncore = &i915->uncore;	190	struct intel_uncore *uncore = gt->uncore;
242	int ret;	191	int ret;
243		192
244	/* WaVcpClkGateDisableForMediaReset:ctg,elk */	193	/* WaVcpClkGateDisableForMediaReset:ctg,elk */
@@ -270,11 +219,11 @@ out: · 25 unmodified lines
270	return ret;	219	return ret;
271	}	220	}
272		221
273	static int ironlake_do_reset(struct drm_i915_private *i915,	222	static int ironlake_do_reset(struct intel_gt *gt,
274	intel_engine_mask_t engine_mask,	223	intel_engine_mask_t engine_mask,
275	unsigned int retry)	224	unsigned int retry)
276	{	225	{
277	struct intel_uncore *uncore = &i915->uncore;	226	struct intel_uncore *uncore = gt->uncore;
278	int ret;	227	int ret;
279		228
280	intel_uncore_write_fw(uncore, ILK_GDSR,	229	intel_uncore_write_fw(uncore, ILK_GDSR,
@@ -306,10 +255,9 @@ out: · 25 unmodified lines
306	}	255	}
307		256
308	/* Reset the hardware domains (GENX_GRDOM_) specified by mask /	257	/* Reset the hardware domains (GENX_GRDOM_) specified by mask /
309	static int gen6_hw_domain_reset(struct drm_i915_private *i915,	258	static int gen6_hw_domain_reset(struct intel_gt *gt, u32 hw_domain_mask)
310	u32 hw_domain_mask)
311	{	259	{
312	struct intel_uncore *uncore = &i915->uncore;	260	struct intel_uncore *uncore = gt->uncore;
313	int err;	261	int err;
314		262
315	/*	263	/*
@@ -331,7 +279,7 @@ static int gen6_hw_domain_reset(struct drm_i915_private *i915, · 15 unmodified lines
331	return err;	279	return err;
332	}	280	}
333		281
334	static int gen6_reset_engines(struct drm_i915_private *i915,	282	static int gen6_reset_engines(struct intel_gt *gt,
335	intel_engine_mask_t engine_mask,	283	intel_engine_mask_t engine_mask,
336	unsigned int retry)	284	unsigned int retry)
337	{	285	{
@@ -351,13 +299,13 @@ static int gen6_reset_engines(struct drm_i915_private *i915, · 13 unmodified lines
351	intel_engine_mask_t tmp;	299	intel_engine_mask_t tmp;
352		300
353	hw_mask = 0;	301	hw_mask = 0;
354	for_each_engine_masked(engine, i915, engine_mask, tmp) {	302	for_each_engine_masked(engine, gt->i915, engine_mask, tmp) {
355	GEM_BUG_ON(engine->id >= ARRAY_SIZE(hw_engine_mask));	303	GEM_BUG_ON(engine->id >= ARRAY_SIZE(hw_engine_mask));
356	hw_mask \|= hw_engine_mask[engine->id];	304	hw_mask \|= hw_engine_mask[engine->id];
357	}	305	}
358	}	306	}
359		307
360	return gen6_hw_domain_reset(i915, hw_mask);	308	return gen6_hw_domain_reset(gt, hw_mask);
361	}	309	}
362		310
363	static u32 gen11_lock_sfc(struct intel_engine_cs *engine)	311	static u32 gen11_lock_sfc(struct intel_engine_cs *engine)
@@ -455,7 +403,7 @@ static void gen11_unlock_sfc(struct intel_engine_cs *engine) · 91 unmodified lines
455	rmw_clear_fw(uncore, sfc_forced_lock, sfc_forced_lock_bit);	403	rmw_clear_fw(uncore, sfc_forced_lock, sfc_forced_lock_bit);
456	}	404	}
457		405
458	static int gen11_reset_engines(struct drm_i915_private *i915,	406	static int gen11_reset_engines(struct intel_gt *gt,
459	intel_engine_mask_t engine_mask,	407	intel_engine_mask_t engine_mask,
460	unsigned int retry)	408	unsigned int retry)
461	{	409	{
@@ -478,17 +426,17 @@ static int gen11_reset_engines(struct drm_i915_private *i915, · 16 unmodified lines
478	hw_mask = GEN11_GRDOM_FULL;	426	hw_mask = GEN11_GRDOM_FULL;
479	} else {	427	} else {
480	hw_mask = 0;	428	hw_mask = 0;
481	for_each_engine_masked(engine, i915, engine_mask, tmp) {	429	for_each_engine_masked(engine, gt->i915, engine_mask, tmp) {
482	GEM_BUG_ON(engine->id >= ARRAY_SIZE(hw_engine_mask));	430	GEM_BUG_ON(engine->id >= ARRAY_SIZE(hw_engine_mask));
483	hw_mask \|= hw_engine_mask[engine->id];	431	hw_mask \|= hw_engine_mask[engine->id];
484	hw_mask \|= gen11_lock_sfc(engine);	432	hw_mask \|= gen11_lock_sfc(engine);
485	}	433	}
486	}	434	}
487		435
488	ret = gen6_hw_domain_reset(i915, hw_mask);	436	ret = gen6_hw_domain_reset(gt, hw_mask);
489		437
490	if (engine_mask != ALL_ENGINES)	438	if (engine_mask != ALL_ENGINES)
491	for_each_engine_masked(engine, i915, engine_mask, tmp)	439	for_each_engine_masked(engine, gt->i915, engine_mask, tmp)
492	gen11_unlock_sfc(engine);	440	gen11_unlock_sfc(engine);
493		441
494	return ret;	442	return ret;
@@ -538,7 +486,7 @@ static void gen8_engine_reset_cancel(struct intel_engine_cs *engine) · 43 unmodified lines
538	_MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));	486	_MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));
539	}	487	}
540		488
541	static int gen8_reset_engines(struct drm_i915_private *i915,	489	static int gen8_reset_engines(struct intel_gt *gt,
542	intel_engine_mask_t engine_mask,	490	intel_engine_mask_t engine_mask,
543	unsigned int retry)	491	unsigned int retry)
544	{	492	{
@@ -547,7 +495,7 @@ static int gen8_reset_engines(struct drm_i915_private *i915, · 2 unmodified lines
547	intel_engine_mask_t tmp;	495	intel_engine_mask_t tmp;
548	int ret;	496	int ret;
549		497
550	for_each_engine_masked(engine, i915, engine_mask, tmp) {	498	for_each_engine_masked(engine, gt->i915, engine_mask, tmp) {
551	ret = gen8_engine_reset_prepare(engine);	499	ret = gen8_engine_reset_prepare(engine);
552	if (ret && !reset_non_ready)	500	if (ret && !reset_non_ready)
553	goto skip_reset;	501	goto skip_reset;
@@ -563,23 +511,23 @@ static int gen8_reset_engines(struct drm_i915_private *i915, · 9 unmodified lines
563	* We rather take context corruption instead of	511	* We rather take context corruption instead of
564	* failed reset with a wedged driver/gpu. And	512	* failed reset with a wedged driver/gpu. And
565	* active bb execution case should be covered by	513	* active bb execution case should be covered by
566	* i915_stop_engines we have before the reset.	514	* stop_engines() we have before the reset.
567	*/	515	*/
568	}	516	}
569		517
570	if (INTEL_GEN(i915) >= 11)	518	if (INTEL_GEN(gt->i915) >= 11)
571	ret = gen11_reset_engines(i915, engine_mask, retry);	519	ret = gen11_reset_engines(gt, engine_mask, retry);
572	else	520	else
573	ret = gen6_reset_engines(i915, engine_mask, retry);	521	ret = gen6_reset_engines(gt, engine_mask, retry);
574		522
575	skip_reset:	523	skip_reset:
576	for_each_engine_masked(engine, i915, engine_mask, tmp)	524	for_each_engine_masked(engine, gt->i915, engine_mask, tmp)
577	gen8_engine_reset_cancel(engine);	525	gen8_engine_reset_cancel(engine);
578		526
579	return ret;	527	return ret;
580	}	528	}
581		529
582	typedef int (reset_func)(struct drm_i915_private ,	530	typedef int (reset_func)(struct intel_gt ,
583	intel_engine_mask_t engine_mask,	531	intel_engine_mask_t engine_mask,
584	unsigned int retry);	532	unsigned int retry);
585		533
@@ -601,15 +549,14 @@ static reset_func intel_get_gpu_reset(struct drm_i915_private *i915) · 15 unmodified lines
601	return NULL;	549	return NULL;
602	}	550	}
603		551
604	int intel_gpu_reset(struct drm_i915_private *i915,	552	int __intel_gt_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask)
605	intel_engine_mask_t engine_mask)
606	{	553	{
607	const int retries = engine_mask == ALL_ENGINES ? RESET_MAX_RETRIES : 1;	554	const int retries = engine_mask == ALL_ENGINES ? RESET_MAX_RETRIES : 1;
608	reset_func reset;	555	reset_func reset;
609	int ret = -ETIMEDOUT;	556	int ret = -ETIMEDOUT;
610	int retry;	557	int retry;
611		558
612	reset = intel_get_gpu_reset(i915);	559	reset = intel_get_gpu_reset(gt->i915);
613	if (!reset)	560	if (!reset)
614	return -ENODEV;	561	return -ENODEV;
615		562
@@ -617,31 +564,14 @@ int intel_gpu_reset(struct drm_i915_private *i915, · 1 unmodified line
617	* If the power well sleeps during the reset, the reset	564	* If the power well sleeps during the reset, the reset
618	* request may be dropped and never completes (causing -EIO).	565	* request may be dropped and never completes (causing -EIO).
619	*/	566	*/
620	intel_uncore_forcewake_get(&i915->uncore, FORCEWAKE_ALL);	567	intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
621	for (retry = 0; ret == -ETIMEDOUT && retry < retries; retry++) {	568	for (retry = 0; ret == -ETIMEDOUT && retry < retries; retry++) {
622	/*
623	* We stop engines, otherwise we might get failed reset and a
624	* dead gpu (on elk). Also as modern gpu as kbl can suffer
625	* from system hang if batchbuffer is progressing when
626	* the reset is issued, regardless of READY_TO_RESET ack.
627	* Thus assume it is best to stop engines on all gens
628	* where we have a gpu reset.
629	*
630	* WaKBLVECSSemaphoreWaitPoll:kbl (on ALL_ENGINES)
631	*
632	* WaMediaResetMainRingCleanup:ctg,elk (presumably)
633	*
634	* FIXME: Wa for more modern gens needs to be validated
635	*/
636	if (retry)
637	i915_stop_engines(i915, engine_mask);
638
639	GEM_TRACE("engine_mask=%x\n", engine_mask);	569	GEM_TRACE("engine_mask=%x\n", engine_mask);
640	preempt_disable();	570	preempt_disable();
641	ret = reset(i915, engine_mask, retry);	571	ret = reset(gt, engine_mask, retry);
642	preempt_enable();	572	preempt_enable();
643	}	573	}
644	intel_uncore_forcewake_put(&i915->uncore, FORCEWAKE_ALL);	574	intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
645		575
646	return ret;	576	return ret;
647	}	577	}
@@ -659,17 +589,17 @@ bool intel_has_reset_engine(struct drm_i915_private *i915) · 11 unmodified lines
659	return INTEL_INFO(i915)->has_reset_engine && i915_modparams.reset >= 2;	589	return INTEL_INFO(i915)->has_reset_engine && i915_modparams.reset >= 2;
660	}	590	}
661		591
662	int intel_reset_guc(struct drm_i915_private *i915)	592	int intel_reset_guc(struct intel_gt *gt)
663	{	593	{
664	u32 guc_domain =	594	u32 guc_domain =
665	INTEL_GEN(i915) >= 11 ? GEN11_GRDOM_GUC : GEN9_GRDOM_GUC;	595	INTEL_GEN(gt->i915) >= 11 ? GEN11_GRDOM_GUC : GEN9_GRDOM_GUC;
666	int ret;	596	int ret;
667		597
668	GEM_BUG_ON(!HAS_GUC(i915));	598	GEM_BUG_ON(!HAS_GT_UC(gt->i915));
669		599
670	intel_uncore_forcewake_get(&i915->uncore, FORCEWAKE_ALL);	600	intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
671	ret = gen6_hw_domain_reset(i915, guc_domain);	601	ret = gen6_hw_domain_reset(gt, guc_domain);
672	intel_uncore_forcewake_put(&i915->uncore, FORCEWAKE_ALL);	602	intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
673		603
674	return ret;	604	return ret;
675	}	605	}
@@ -691,56 +621,55 @@ static void reset_prepare_engine(struct intel_engine_cs *engine) · 15 unmodified lines
691	engine->reset.prepare(engine);	621	engine->reset.prepare(engine);
692	}	622	}
693		623
694	static void revoke_mmaps(struct drm_i915_private *i915)	624	static void revoke_mmaps(struct intel_gt *gt)
695	{	625	{
696	int i;	626	int i;
697		627
698	for (i = 0; i < i915->ggtt.num_fences; i++) {	628	for (i = 0; i < gt->ggtt->num_fences; i++) {
699	struct drm_vma_offset_node *node;	629	struct drm_vma_offset_node *node;
700	struct i915_vma *vma;	630	struct i915_vma *vma;
701	u64 vma_offset;	631	u64 vma_offset;
702		632
703	vma = READ_ONCE(i915->ggtt.fence_regs[i].vma);	633	vma = READ_ONCE(gt->ggtt->fence_regs[i].vma);
704	if (!vma)	634	if (!vma)
705	continue;	635	continue;
706		636
707	if (!i915_vma_has_userfault(vma))	637	if (!i915_vma_has_userfault(vma))
708	continue;	638	continue;
709		639
710	GEM_BUG_ON(vma->fence != &i915->ggtt.fence_regs[i]);	640	GEM_BUG_ON(vma->fence != &gt->ggtt->fence_regs[i]);
711	node = &vma->obj->base.vma_node;	641	node = &vma->obj->base.vma_node;
712	vma_offset = vma->ggtt_view.partial.offset << PAGE_SHIFT;	642	vma_offset = vma->ggtt_view.partial.offset << PAGE_SHIFT;
713	unmap_mapping_range(i915->drm.anon_inode->i_mapping,	643	unmap_mapping_range(gt->i915->drm.anon_inode->i_mapping,
714	drm_vma_node_offset_addr(node) + vma_offset,	644	drm_vma_node_offset_addr(node) + vma_offset,
715	vma->size,	645	vma->size,
716	1);	646	1);
717	}	647	}
718	}	648	}
719		649
720	static intel_engine_mask_t reset_prepare(struct drm_i915_private *i915)	650	static intel_engine_mask_t reset_prepare(struct intel_gt *gt)
721	{	651	{
722	struct intel_engine_cs *engine;	652	struct intel_engine_cs *engine;
723	intel_engine_mask_t awake = 0;	653	intel_engine_mask_t awake = 0;
724	enum intel_engine_id id;	654	enum intel_engine_id id;
725		655
726	for_each_engine(engine, i915, id) {	656	for_each_engine(engine, gt->i915, id) {
727	if (intel_engine_pm_get_if_awake(engine))	657	if (intel_engine_pm_get_if_awake(engine))
728	awake \|= engine->mask;	658	awake \|= engine->mask;
729	reset_prepare_engine(engine);	659	reset_prepare_engine(engine);
730	}	660	}
731		661
732	intel_uc_reset_prepare(i915);	662	intel_uc_reset_prepare(&gt->uc);
733		663
734	return awake;	664	return awake;
735	}	665	}
736		666
737	static void gt_revoke(struct drm_i915_private *i915)	667	static void gt_revoke(struct intel_gt *gt)
738	{	668	{
739	revoke_mmaps(i915);	669	revoke_mmaps(gt);
740	}	670	}
741		671
742	static int gt_reset(struct drm_i915_private *i915,	672	static int gt_reset(struct intel_gt *gt, intel_engine_mask_t stalled_mask)
743	intel_engine_mask_t stalled_mask)
744	{	673	{
745	struct intel_engine_cs *engine;	674	struct intel_engine_cs *engine;
746	enum intel_engine_id id;	675	enum intel_engine_id id;
@@ -750,14 +679,14 @@ static int gt_reset(struct drm_i915_private *i915, · 3 unmodified lines
750	* Everything depends on having the GTT running, so we need to start	679	* Everything depends on having the GTT running, so we need to start
751	* there.	680	* there.
752	*/	681	*/
753	err = i915_ggtt_enable_hw(i915);	682	err = i915_ggtt_enable_hw(gt->i915);
754	if (err)	683	if (err)
755	return err;	684	return err;
756		685
757	for_each_engine(engine, i915, id)	686	for_each_engine(engine, gt->i915, id)
758	intel_engine_reset(engine, stalled_mask & engine->mask);	687	__intel_engine_reset(engine, stalled_mask & engine->mask);
759		688
760	i915_gem_restore_fences(i915);	689	i915_gem_restore_fences(gt->i915);
761		690
762	return err;	691	return err;
763	}	692	}
@@ -770,13 +699,12 @@ static void reset_finish_engine(struct intel_engine_cs *engine) · 6 unmodified lines
770	intel_engine_signal_breadcrumbs(engine);	699	intel_engine_signal_breadcrumbs(engine);
771	}	700	}
772		701
773	static void reset_finish(struct drm_i915_private *i915,	702	static void reset_finish(struct intel_gt *gt, intel_engine_mask_t awake)
774	intel_engine_mask_t awake)
775	{	703	{
776	struct intel_engine_cs *engine;	704	struct intel_engine_cs *engine;
777	enum intel_engine_id id;	705	enum intel_engine_id id;
778		706
779	for_each_engine(engine, i915, id) {	707	for_each_engine(engine, gt->i915, id) {
780	reset_finish_engine(engine);	708	reset_finish_engine(engine);
781	if (awake & engine->mask)	709	if (awake & engine->mask)
782	intel_engine_pm_put(engine);	710	intel_engine_pm_put(engine);
@@ -800,20 +728,19 @@ static void nop_submit_request(struct i915_request *request) · 17 unmodified lines
800	intel_engine_queue_breadcrumbs(engine);	728	intel_engine_queue_breadcrumbs(engine);
801	}	729	}
802		730
803	static void __i915_gem_set_wedged(struct drm_i915_private *i915)	731	static void __intel_gt_set_wedged(struct intel_gt *gt)
804	{	732	{
805	struct i915_gpu_error *error = &i915->gpu_error;
806	struct intel_engine_cs *engine;	733	struct intel_engine_cs *engine;
807	intel_engine_mask_t awake;	734	intel_engine_mask_t awake;
808	enum intel_engine_id id;	735	enum intel_engine_id id;
809		736
810	if (test_bit(I915_WEDGED, &error->flags))	737	if (test_bit(I915_WEDGED, &gt->reset.flags))
811	return;	738	return;
812		739
813	if (GEM_SHOW_DEBUG() && !intel_engines_are_idle(i915)) {	740	if (GEM_SHOW_DEBUG() && !intel_engines_are_idle(gt)) {
814	struct drm_printer p = drm_debug_printer(__func__);	741	struct drm_printer p = drm_debug_printer(__func__);
815		742
816	for_each_engine(engine, i915, id)	743	for_each_engine(engine, gt->i915, id)
817	intel_engine_dump(engine, &p, "%s\n", engine->name);	744	intel_engine_dump(engine, &p, "%s\n", engine->name);
818	}	745	}
819		746
@@ -824,17 +751,17 @@ static void __i915_gem_set_wedged(struct drm_i915_private *i915) · 4 unmodified lines
824	* rolling the global seqno forward (since this would complete requests	751	* rolling the global seqno forward (since this would complete requests
825	* for which we haven't set the fence error to EIO yet).	752	* for which we haven't set the fence error to EIO yet).
826	*/	753	*/
827	awake = reset_prepare(i915);	754	awake = reset_prepare(gt);
828		755
829	/* Even if the GPU reset fails, it should still stop the engines */	756	/* Even if the GPU reset fails, it should still stop the engines */
830	if (!INTEL_INFO(i915)->gpu_reset_clobbers_display)	757	if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
831	intel_gpu_reset(i915, ALL_ENGINES);	758	__intel_gt_reset(gt, ALL_ENGINES);
832		759
833	for_each_engine(engine, i915, id) {	760	for_each_engine(engine, gt->i915, id) {
834	engine->submit_request = nop_submit_request;	761	engine->submit_request = nop_submit_request;
835	engine->schedule = NULL;	762	engine->schedule = NULL;
836	}	763	}
837	i915->caps.scheduler = 0;	764	gt->i915->caps.scheduler = 0;
838		765
839	/*	766	/*
840	* Make sure no request can slip through without getting completed by	767	* Make sure no request can slip through without getting completed by
@@ -842,37 +769,36 @@ static void __i915_gem_set_wedged(struct drm_i915_private *i915) · 1 unmodified line
842	* in nop_submit_request.	769	* in nop_submit_request.
843	*/	770	*/
844	synchronize_rcu_expedited();	771	synchronize_rcu_expedited();
845	set_bit(I915_WEDGED, &error->flags);	772	set_bit(I915_WEDGED, &gt->reset.flags);
846		773
847	/* Mark all executing requests as skipped */	774	/* Mark all executing requests as skipped */
848	for_each_engine(engine, i915, id)	775	for_each_engine(engine, gt->i915, id)
849	engine->cancel_requests(engine);	776	engine->cancel_requests(engine);
850		777
851	reset_finish(i915, awake);	778	reset_finish(gt, awake);
852		779
853	GEM_TRACE("end\n");	780	GEM_TRACE("end\n");
854	}	781	}
855		782
856	void i915_gem_set_wedged(struct drm_i915_private *i915)	783	void intel_gt_set_wedged(struct intel_gt *gt)
857	{	784	{
858	struct i915_gpu_error *error = &i915->gpu_error;
859	intel_wakeref_t wakeref;	785	intel_wakeref_t wakeref;
860		786
861	mutex_lock(&error->wedge_mutex);	787	mutex_lock(&gt->reset.mutex);
862	with_intel_runtime_pm(&i915->runtime_pm, wakeref)	788	with_intel_runtime_pm(&gt->i915->runtime_pm, wakeref)
863	__i915_gem_set_wedged(i915);	789	__intel_gt_set_wedged(gt);
864	mutex_unlock(&error->wedge_mutex);	790	mutex_unlock(&gt->reset.mutex);
865	}	791	}
866		792
867	static bool __i915_gem_unset_wedged(struct drm_i915_private *i915)	793	static bool __intel_gt_unset_wedged(struct intel_gt *gt)
868	{	794	{
869	struct i915_gpu_error *error = &i915->gpu_error;	795	struct intel_gt_timelines *timelines = &gt->timelines;
870	struct i915_timeline *tl;	796	struct intel_timeline *tl;
871		797
872	if (!test_bit(I915_WEDGED, &error->flags))	798	if (!test_bit(I915_WEDGED, &gt->reset.flags))
873	return true;	799	return true;
874		800
875	if (!i915->gt.scratch) /* Never full initialised, recovery impossible */	801	if (!gt->scratch) /* Never full initialised, recovery impossible */
876	return false;	802	return false;
877		803
878	GEM_TRACE("start\n");	804	GEM_TRACE("start\n");
@@ -887,8 +813,8 @@ static bool __i915_gem_unset_wedged(struct drm_i915_private *i915) · 8 unmodified lines
887	*	813	*
888	* No more can be submitted until we reset the wedged bit.	814	* No more can be submitted until we reset the wedged bit.
889	*/	815	*/
890	mutex_lock(&i915->gt.timelines.mutex);	816	mutex_lock(&timelines->mutex);
891	list_for_each_entry(tl, &i915->gt.timelines.active_list, link) {	817	list_for_each_entry(tl, &timelines->active_list, link) {
892	struct i915_request *rq;	818	struct i915_request *rq;
893		819
894	rq = i915_active_request_get_unlocked(&tl->last_request);	820	rq = i915_active_request_get_unlocked(&tl->last_request);
@@ -905,9 +831,9 @@ static bool __i915_gem_unset_wedged(struct drm_i915_private *i915) · 10 unmodified lines
905	dma_fence_default_wait(&rq->fence, false, MAX_SCHEDULE_TIMEOUT);	831	dma_fence_default_wait(&rq->fence, false, MAX_SCHEDULE_TIMEOUT);
906	i915_request_put(rq);	832	i915_request_put(rq);
907	}	833	}
908	mutex_unlock(&i915->gt.timelines.mutex);	834	mutex_unlock(&timelines->mutex);
909		835
910	intel_gt_sanitize(i915, false);	836	intel_gt_sanitize(gt, false);
911		837
912	/*	838	/*
913	* Undo nop_submit_request. We prevent all new i915 requests from	839	* Undo nop_submit_request. We prevent all new i915 requests from
@@ -918,53 +844,51 @@ static bool __i915_gem_unset_wedged(struct drm_i915_private *i915) · 4 unmodified lines
918	* the nop_submit_request on reset, we can do this from normal	844	* the nop_submit_request on reset, we can do this from normal
919	* context and do not require stop_machine().	845	* context and do not require stop_machine().
920	*/	846	*/
921	intel_engines_reset_default_submission(i915);	847	intel_engines_reset_default_submission(gt);
922		848
923	GEM_TRACE("end\n");	849	GEM_TRACE("end\n");
924		850
925	smp_mb__before_atomic(); /* complete takeover before enabling execbuf */	851	smp_mb__before_atomic(); /* complete takeover before enabling execbuf */
926	clear_bit(I915_WEDGED, &i915->gpu_error.flags);	852	clear_bit(I915_WEDGED, &gt->reset.flags);
927		853
928	return true;	854	return true;
929	}	855	}
930		856
931	bool i915_gem_unset_wedged(struct drm_i915_private *i915)	857	bool intel_gt_unset_wedged(struct intel_gt *gt)
932	{	858	{
933	struct i915_gpu_error *error = &i915->gpu_error;
934	bool result;	859	bool result;
935		860
936	mutex_lock(&error->wedge_mutex);	861	mutex_lock(&gt->reset.mutex);
937	result = __i915_gem_unset_wedged(i915);	862	result = __intel_gt_unset_wedged(gt);
938	mutex_unlock(&error->wedge_mutex);	863	mutex_unlock(&gt->reset.mutex);
939		864
940	return result;	865	return result;
941	}	866	}
942		867
943	static int do_reset(struct drm_i915_private *i915,	868	static int do_reset(struct intel_gt *gt, intel_engine_mask_t stalled_mask)
944	intel_engine_mask_t stalled_mask)
945	{	869	{
946	int err, i;	870	int err, i;
947		871
948	gt_revoke(i915);	872	gt_revoke(gt);
949		873
950	err = intel_gpu_reset(i915, ALL_ENGINES);	874	err = __intel_gt_reset(gt, ALL_ENGINES);
951	for (i = 0; err && i < RESET_MAX_RETRIES; i++) {	875	for (i = 0; err && i < RESET_MAX_RETRIES; i++) {
952	msleep(10 * (i + 1));	876	msleep(10 * (i + 1));
953	err = intel_gpu_reset(i915, ALL_ENGINES);	877	err = __intel_gt_reset(gt, ALL_ENGINES);
954	}	878	}
955	if (err)	879	if (err)
956	return err;	880	return err;
957		881
958	return gt_reset(i915, stalled_mask);	882	return gt_reset(gt, stalled_mask);
959	}	883	}
960		884
961	static int resume(struct drm_i915_private *i915)	885	static int resume(struct intel_gt *gt)
962	{	886	{
963	struct intel_engine_cs *engine;	887	struct intel_engine_cs *engine;
964	enum intel_engine_id id;	888	enum intel_engine_id id;
965	int ret;	889	int ret;
966		890
967	for_each_engine(engine, i915, id) {	891	for_each_engine(engine, gt->i915, id) {
968	ret = engine->resume(engine);	892	ret = engine->resume(engine);
969	if (ret)	893	if (ret)
970	return ret;	894	return ret;
@@ -974,8 +898,8 @@ static int resume(struct drm_i915_private *i915) · 3 unmodified lines
974	}	898	}
975		899
976	/**	900	/**
977	* i915_reset - reset chip after a hang	901	* intel_gt_reset - reset chip after a hang
978	* @i915: #drm_i915_private to reset	902	* @gt: #intel_gt to reset
979	* @stalled_mask: mask of the stalled engines with the guilty requests	903	* @stalled_mask: mask of the stalled engines with the guilty requests
980	* @reason: user error message for why we are resetting	904	* @reason: user error message for why we are resetting
981	*	905	*
@@ -990,50 +914,50 @@ static int resume(struct drm_i915_private *i915) · 8 unmodified lines
990	* - re-init interrupt state	914	* - re-init interrupt state
991	* - re-init display	915	* - re-init display
992	*/	916	*/
993	void i915_reset(struct drm_i915_private *i915,	917	void intel_gt_reset(struct intel_gt *gt,
994	intel_engine_mask_t stalled_mask,	918	intel_engine_mask_t stalled_mask,
995	const char *reason)	919	const char *reason)
996	{	920	{
997	struct i915_gpu_error *error = &i915->gpu_error;
998	intel_engine_mask_t awake;	921	intel_engine_mask_t awake;
999	int ret;	922	int ret;
1000		923
1001	GEM_TRACE("flags=%lx\n", error->flags);	924	GEM_TRACE("flags=%lx\n", gt->reset.flags);
1002		925
1003	might_sleep();	926	might_sleep();
1004	GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &error->flags));	927	GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &gt->reset.flags));
1005	mutex_lock(&error->wedge_mutex);	928	mutex_lock(&gt->reset.mutex);
1006		929
1007	/* Clear any previous failed attempts at recovery. Time to try again. */	930	/* Clear any previous failed attempts at recovery. Time to try again. */
1008	if (!__i915_gem_unset_wedged(i915))	931	if (!__intel_gt_unset_wedged(gt))
1009	goto unlock;	932	goto unlock;
1010		933
1011	if (reason)	934	if (reason)
1012	dev_notice(i915->drm.dev, "Resetting chip for %s\n", reason);	935	dev_notice(gt->i915->drm.dev,
1013	error->reset_count++;	936	"Resetting chip for %s\n", reason);
		937	atomic_inc(&gt->i915->gpu_error.reset_count);
1014		938
1015	awake = reset_prepare(i915);	939	awake = reset_prepare(gt);
1016		940
1017	if (!intel_has_gpu_reset(i915)) {	941	if (!intel_has_gpu_reset(gt->i915)) {
1018	if (i915_modparams.reset)	942	if (i915_modparams.reset)
1019	dev_err(i915->drm.dev, "GPU reset not supported\n");	943	dev_err(gt->i915->drm.dev, "GPU reset not supported\n");
1020	else	944	else
1021	DRM_DEBUG_DRIVER("GPU reset disabled\n");	945	DRM_DEBUG_DRIVER("GPU reset disabled\n");
1022	goto error;	946	goto error;
1023	}	947	}
1024		948
1025	if (INTEL_INFO(i915)->gpu_reset_clobbers_display)	949	if (INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
1026	intel_runtime_pm_disable_interrupts(i915);	950	intel_runtime_pm_disable_interrupts(gt->i915);
1027		951
1028	if (do_reset(i915, stalled_mask)) {	952	if (do_reset(gt, stalled_mask)) {
1029	dev_err(i915->drm.dev, "Failed to reset chip\n");	953	dev_err(gt->i915->drm.dev, "Failed to reset chip\n");
1030	goto taint;	954	goto taint;
1031	}	955	}
1032		956
1033	if (INTEL_INFO(i915)->gpu_reset_clobbers_display)	957	if (INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
1034	intel_runtime_pm_enable_interrupts(i915);	958	intel_runtime_pm_enable_interrupts(gt->i915);
1035		959
1036	intel_overlay_reset(i915);	960	intel_overlay_reset(gt->i915);
1037		961
1038	/*	962	/*
1039	* Next we need to restore the context, but we don't use those	963	* Next we need to restore the context, but we don't use those
@@ -1043,23 +967,23 @@ void i915_reset(struct drm_i915_private *i915, · 3 unmodified lines
1043	* was running at the time of the reset (i.e. we weren't VT	967	* was running at the time of the reset (i.e. we weren't VT
1044	* switched away).	968	* switched away).
1045	*/	969	*/
1046	ret = i915_gem_init_hw(i915);	970	ret = i915_gem_init_hw(gt->i915);
1047	if (ret) {	971	if (ret) {
1048	DRM_ERROR("Failed to initialise HW following reset (%d)\n",	972	DRM_ERROR("Failed to initialise HW following reset (%d)\n",
1049	ret);	973	ret);
1050	goto taint;	974	goto taint;
1051	}	975	}
1052		976
1053	ret = resume(i915);	977	ret = resume(gt);
1054	if (ret)	978	if (ret)
1055	goto taint;	979	goto taint;
1056		980
1057	i915_queue_hangcheck(i915);	981	intel_gt_queue_hangcheck(gt);
1058		982
1059	finish:	983	finish:
1060	reset_finish(i915, awake);	984	reset_finish(gt, awake);
1061	unlock:	985	unlock:
1062	mutex_unlock(&error->wedge_mutex);	986	mutex_unlock(&gt->reset.mutex);
1063	return;	987	return;
1064		988
1065	taint:	989	taint:
@@ -1077,18 +1001,17 @@ taint: · 11 unmodified lines
1077	*/	1001	*/
1078	add_taint_for_CI(TAINT_WARN);	1002	add_taint_for_CI(TAINT_WARN);
1079	error:	1003	error:
1080	__i915_gem_set_wedged(i915);	1004	__intel_gt_set_wedged(gt);
1081	goto finish;	1005	goto finish;
1082	}	1006	}
1083		1007
1084	static inline int intel_gt_reset_engine(struct drm_i915_private *i915,	1008	static inline int intel_gt_reset_engine(struct intel_engine_cs *engine)
1085	struct intel_engine_cs *engine)
1086	{	1009	{
1087	return intel_gpu_reset(i915, engine->mask);	1010	return __intel_gt_reset(engine->gt, engine->mask);
1088	}	1011	}
1089		1012
1090	/**	1013	/**
1091	* i915_reset_engine - reset GPU engine to recover from a hang	1014	* intel_engine_reset - reset GPU engine to recover from a hang
1092	* @engine: engine to reset	1015	* @engine: engine to reset
1093	* @msg: reason for GPU reset; or NULL for no dev_notice()	1016	* @msg: reason for GPU reset; or NULL for no dev_notice()
1094	*	1017	*
@@ -1100,13 +1023,13 @@ static inline int intel_gt_reset_engine(struct drm_i915_private *i915, · 5 unmodified lines
1100	* - reset engine (which will force the engine to idle)	1023	* - reset engine (which will force the engine to idle)
1101	* - re-init/configure engine	1024	* - re-init/configure engine
1102	*/	1025	*/
1103	int i915_reset_engine(struct intel_engine_cs engine, const char msg)	1026	int intel_engine_reset(struct intel_engine_cs engine, const char msg)
1104	{	1027	{
1105	struct i915_gpu_error *error = &engine->i915->gpu_error;	1028	struct intel_gt *gt = engine->gt;
1106	int ret;	1029	int ret;
1107		1030
1108	GEM_TRACE("%s flags=%lx\n", engine->name, error->flags);	1031	GEM_TRACE("%s flags=%lx\n", engine->name, gt->reset.flags);
1109	GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags));	1032	GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &gt->reset.flags));
1110		1033
1111	if (!intel_engine_pm_get_if_awake(engine))	1034	if (!intel_engine_pm_get_if_awake(engine))
1112	return 0;	1035	return 0;
@@ -1116,16 +1039,16 @@ int i915_reset_engine(struct intel_engine_cs engine, const char msg) · 3 unmodified lines
1116	if (msg)	1039	if (msg)
1117	dev_notice(engine->i915->drm.dev,	1040	dev_notice(engine->i915->drm.dev,
1118	"Resetting %s for %s\n", engine->name, msg);	1041	"Resetting %s for %s\n", engine->name, msg);
1119	error->reset_engine_count[engine->id]++;	1042	atomic_inc(&engine->i915->gpu_error.reset_engine_count[engine->uabi_class]);
1120		1043
1121	if (!engine->i915->guc.execbuf_client)	1044	if (!engine->gt->uc.guc.execbuf_client)
1122	ret = intel_gt_reset_engine(engine->i915, engine);	1045	ret = intel_gt_reset_engine(engine);
1123	else	1046	else
1124	ret = intel_guc_reset_engine(&engine->i915->guc, engine);	1047	ret = intel_guc_reset_engine(&engine->gt->uc.guc, engine);
1125	if (ret) {	1048	if (ret) {
1126	/* If we fail here, we expect to fallback to a global reset */	1049	/* If we fail here, we expect to fallback to a global reset */
1127	DRM_DEBUG_DRIVER("%sFailed to reset %s, ret=%d\n",	1050	DRM_DEBUG_DRIVER("%sFailed to reset %s, ret=%d\n",
1128	engine->i915->guc.execbuf_client ? "GuC " : "",	1051	engine->gt->uc.guc.execbuf_client ? "GuC " : "",
1129	engine->name, ret);	1052	engine->name, ret);
1130	goto out;	1053	goto out;
1131	}	1054	}
@@ -1135,7 +1058,7 @@ int i915_reset_engine(struct intel_engine_cs engine, const char msg) · 3 unmodified lines
1135	* active request and can drop it, adjust head to skip the offending	1058	* active request and can drop it, adjust head to skip the offending
1136	* request to resume executing remaining requests in the queue.	1059	* request to resume executing remaining requests in the queue.
1137	*/	1060	*/
1138	intel_engine_reset(engine, true);	1061	__intel_engine_reset(engine, true);
1139		1062
1140	/*	1063	/*
1141	* The engine and its registers (and workarounds in case of render)	1064	* The engine and its registers (and workarounds in case of render)
@@ -1151,16 +1074,15 @@ out: · 9 unmodified lines
1151	return ret;	1074	return ret;
1152	}	1075	}
1153		1076
1154	static void i915_reset_device(struct drm_i915_private *i915,	1077	static void intel_gt_reset_global(struct intel_gt *gt,
1155	u32 engine_mask,	1078	u32 engine_mask,
1156	const char *reason)	1079	const char *reason)
1157	{	1080	{
1158	struct i915_gpu_error *error = &i915->gpu_error;	1081	struct kobject *kobj = &gt->i915->drm.primary->kdev->kobj;
1159	struct kobject *kobj = &i915->drm.primary->kdev->kobj;
1160	char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };	1082	char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
1161	char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };	1083	char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
1162	char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };	1084	char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
1163	struct i915_wedge_me w;	1085	struct intel_wedge_me w;
1164		1086
1165	kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);	1087	kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
1166		1088
@@ -1168,137 +1090,24 @@ static void i915_reset_device(struct drm_i915_private *i915, · 1 unmodified line
1168	kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);	1090	kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
1169		1091
1170	/* Use a watchdog to ensure that our reset completes */	1092	/* Use a watchdog to ensure that our reset completes */
1171	i915_wedge_on_timeout(&w, i915, 5 * HZ) {	1093	intel_wedge_on_timeout(&w, gt, 5 * HZ) {
1172	intel_prepare_reset(i915);	1094	intel_prepare_reset(gt->i915);
1173		1095
1174	/* Flush everyone using a resource about to be clobbered */	1096	/* Flush everyone using a resource about to be clobbered */
1175	synchronize_srcu_expedited(&error->reset_backoff_srcu);	1097	synchronize_srcu_expedited(&gt->reset.backoff_srcu);
1176		1098
1177	i915_reset(i915, engine_mask, reason);	1099	intel_gt_reset(gt, engine_mask, reason);
1178		1100
1179	intel_finish_reset(i915);	1101	intel_finish_reset(gt->i915);
1180	}	1102	}
1181		1103
1182	if (!test_bit(I915_WEDGED, &error->flags))	1104	if (!test_bit(I915_WEDGED, &gt->reset.flags))
1183	kobject_uevent_env(kobj, KOBJ_CHANGE, reset_done_event);	1105	kobject_uevent_env(kobj, KOBJ_CHANGE, reset_done_event);
1184	}	1106	}
1185		1107
1186	static void clear_register(struct intel_uncore *uncore, i915_reg_t reg)
1187	{
1188	intel_uncore_rmw(uncore, reg, 0, 0);
1189	}
1190
1191	static void gen8_clear_engine_error_register(struct intel_engine_cs *engine)
1192	{
1193	GEN6_RING_FAULT_REG_RMW(engine, RING_FAULT_VALID, 0);
1194	GEN6_RING_FAULT_REG_POSTING_READ(engine);
1195	}
1196
1197	static void clear_error_registers(struct drm_i915_private *i915,
1198	intel_engine_mask_t engine_mask)
1199	{
1200	struct intel_uncore *uncore = &i915->uncore;
1201	u32 eir;
1202
1203	if (!IS_GEN(i915, 2))
1204	clear_register(uncore, PGTBL_ER);
1205
1206	if (INTEL_GEN(i915) < 4)
1207	clear_register(uncore, IPEIR(RENDER_RING_BASE));
1208	else
1209	clear_register(uncore, IPEIR_I965);
1210
1211	clear_register(uncore, EIR);
1212	eir = intel_uncore_read(uncore, EIR);
1213	if (eir) {
1214	/*
1215	* some errors might have become stuck,
1216	* mask them.
1217	*/
1218	DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir);
1219	rmw_set(uncore, EMR, eir);
1220	intel_uncore_write(uncore, GEN2_IIR,
1221	I915_MASTER_ERROR_INTERRUPT);
1222	}
1223
1224	if (INTEL_GEN(i915) >= 8) {
1225	rmw_clear(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID);
1226	intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG);
1227	} else if (INTEL_GEN(i915) >= 6) {
1228	struct intel_engine_cs *engine;
1229	enum intel_engine_id id;
1230
1231	for_each_engine_masked(engine, i915, engine_mask, id)
1232	gen8_clear_engine_error_register(engine);
1233	}
1234	}
1235
1236	static void gen6_check_faults(struct drm_i915_private *dev_priv)
1237	{
1238	struct intel_engine_cs *engine;
1239	enum intel_engine_id id;
1240	u32 fault;
1241
1242	for_each_engine(engine, dev_priv, id) {
1243	fault = GEN6_RING_FAULT_REG_READ(engine);
1244	if (fault & RING_FAULT_VALID) {
1245	DRM_DEBUG_DRIVER("Unexpected fault\n"
1246	"\tAddr: 0x%08lx\n"
1247	"\tAddress space: %s\n"
1248	"\tSource ID: %d\n"
1249	"\tType: %d\n",
1250	fault & PAGE_MASK,
1251	fault & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
1252	RING_FAULT_SRCID(fault),
1253	RING_FAULT_FAULT_TYPE(fault));
1254	}
1255	}
1256	}
1257
1258	static void gen8_check_faults(struct drm_i915_private *dev_priv)
1259	{
1260	u32 fault = I915_READ(GEN8_RING_FAULT_REG);
1261
1262	if (fault & RING_FAULT_VALID) {
1263	u32 fault_data0, fault_data1;
1264	u64 fault_addr;
1265
1266	fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
1267	fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
1268	fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) \|
1269	((u64)fault_data0 << 12);
1270
1271	DRM_DEBUG_DRIVER("Unexpected fault\n"
1272	"\tAddr: 0x%08x_%08x\n"
1273	"\tAddress space: %s\n"
1274	"\tEngine ID: %d\n"
1275	"\tSource ID: %d\n"
1276	"\tType: %d\n",
1277	upper_32_bits(fault_addr),
1278	lower_32_bits(fault_addr),
1279	fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
1280	GEN8_RING_FAULT_ENGINE_ID(fault),
1281	RING_FAULT_SRCID(fault),
1282	RING_FAULT_FAULT_TYPE(fault));
1283	}
1284	}
1285
1286	void i915_check_and_clear_faults(struct drm_i915_private *i915)
1287	{
1288	/* From GEN8 onwards we only have one 'All Engine Fault Register' */
1289	if (INTEL_GEN(i915) >= 8)
1290	gen8_check_faults(i915);
1291	else if (INTEL_GEN(i915) >= 6)
1292	gen6_check_faults(i915);
1293	else
1294	return;
1295
1296	clear_error_registers(i915, ALL_ENGINES);
1297	}
1298
1299	/**	1108	/**
1300	* i915_handle_error - handle a gpu error	1109	* intel_gt_handle_error - handle a gpu error
1301	* @i915: i915 device private	1110	* @gt: the intel_gt
1302	* @engine_mask: mask representing engines that are hung	1111	* @engine_mask: mask representing engines that are hung
1303	* @flags: control flags	1112	* @flags: control flags
1304	* @fmt: Error message format string	1113	* @fmt: Error message format string
@@ -1309,12 +1118,11 @@ void i915_check_and_clear_faults(struct drm_i915_private *i915) · 4 unmodified lines
1309	* so userspace knows something bad happened (should trigger collection	1118	* so userspace knows something bad happened (should trigger collection
1310	* of a ring dump etc.).	1119	* of a ring dump etc.).
1311	*/	1120	*/
1312	void i915_handle_error(struct drm_i915_private *i915,	1121	void intel_gt_handle_error(struct intel_gt *gt,
1313	intel_engine_mask_t engine_mask,	1122	intel_engine_mask_t engine_mask,
1314	unsigned long flags,	1123	unsigned long flags,
1315	const char *fmt, ...)	1124	const char *fmt, ...)
1316	{	1125	{
1317	struct i915_gpu_error *error = &i915->gpu_error;
1318	struct intel_engine_cs *engine;	1126	struct intel_engine_cs *engine;
1319	intel_wakeref_t wakeref;	1127	intel_wakeref_t wakeref;
1320	intel_engine_mask_t tmp;	1128	intel_engine_mask_t tmp;
@@ -1338,33 +1146,31 @@ void i915_handle_error(struct drm_i915_private *i915, · 17 unmodified lines
1338	* isn't the case at least when we get here by doing a	1146	* isn't the case at least when we get here by doing a
1339	* simulated reset via debugfs, so get an RPM reference.	1147	* simulated reset via debugfs, so get an RPM reference.
1340	*/	1148	*/
1341	wakeref = intel_runtime_pm_get(&i915->runtime_pm);	1149	wakeref = intel_runtime_pm_get(&gt->i915->runtime_pm);
1342		1150
1343	engine_mask &= INTEL_INFO(i915)->engine_mask;	1151	engine_mask &= INTEL_INFO(gt->i915)->engine_mask;
1344		1152
1345	if (flags & I915_ERROR_CAPTURE) {	1153	if (flags & I915_ERROR_CAPTURE) {
1346	i915_capture_error_state(i915, engine_mask, msg);	1154	i915_capture_error_state(gt->i915, engine_mask, msg);
1347	clear_error_registers(i915, engine_mask);	1155	intel_gt_clear_error_registers(gt, engine_mask);
1348	}	1156	}
1349		1157
1350	/*	1158	/*
1351	* Try engine reset when available. We fall back to full reset if	1159	* Try engine reset when available. We fall back to full reset if
1352	* single reset fails.	1160	* single reset fails.
1353	*/	1161	*/
1354	if (intel_has_reset_engine(i915) && !__i915_wedged(error)) {	1162	if (intel_has_reset_engine(gt->i915) && !intel_gt_is_wedged(gt)) {
1355	for_each_engine_masked(engine, i915, engine_mask, tmp) {	1163	for_each_engine_masked(engine, gt->i915, engine_mask, tmp) {
1356	BUILD_BUG_ON(I915_RESET_MODESET >= I915_RESET_ENGINE);	1164	BUILD_BUG_ON(I915_RESET_MODESET >= I915_RESET_ENGINE);
1357	if (test_and_set_bit(I915_RESET_ENGINE + engine->id,	1165	if (test_and_set_bit(I915_RESET_ENGINE + engine->id,
1358	&error->flags))	1166	&gt->reset.flags))
1359	continue;	1167	continue;
1360		1168
1361	if (i915_reset_engine(engine, msg) == 0)	1169	if (intel_engine_reset(engine, msg) == 0)
1362	engine_mask &= ~engine->mask;	1170	engine_mask &= ~engine->mask;
1363		1171
1364	clear_bit(I915_RESET_ENGINE + engine->id,	1172	clear_and_wake_up_bit(I915_RESET_ENGINE + engine->id,
1365	&error->flags);	1173	&gt->reset.flags);
1366	wake_up_bit(&error->flags,
1367	I915_RESET_ENGINE + engine->id);
1368	}	1174	}
1369	}	1175	}
1370		1176
@@ -1372,9 +1178,9 @@ void i915_handle_error(struct drm_i915_private *i915, · 1 unmodified line
1372	goto out;	1178	goto out;
1373		1179
1374	/* Full reset needs the mutex, stop any other user trying to do so. */	1180	/* Full reset needs the mutex, stop any other user trying to do so. */
1375	if (test_and_set_bit(I915_RESET_BACKOFF, &error->flags)) {	1181	if (test_and_set_bit(I915_RESET_BACKOFF, &gt->reset.flags)) {
1376	wait_event(error->reset_queue,	1182	wait_event(gt->reset.queue,
1377	!test_bit(I915_RESET_BACKOFF, &error->flags));	1183	!test_bit(I915_RESET_BACKOFF, &gt->reset.flags));
1378	goto out; /* piggy-back on the other reset */	1184	goto out; /* piggy-back on the other reset */
1379	}	1185	}
1380		1186
@@ -1382,113 +1188,119 @@ void i915_handle_error(struct drm_i915_private *i915, · 1 unmodified line
1382	synchronize_rcu_expedited();	1188	synchronize_rcu_expedited();
1383		1189
1384	/* Prevent any other reset-engine attempt. */	1190	/* Prevent any other reset-engine attempt. */
1385	for_each_engine(engine, i915, tmp) {	1191	for_each_engine(engine, gt->i915, tmp) {
1386	while (test_and_set_bit(I915_RESET_ENGINE + engine->id,	1192	while (test_and_set_bit(I915_RESET_ENGINE + engine->id,
1387	&error->flags))	1193	&gt->reset.flags))
1388	wait_on_bit(&error->flags,	1194	wait_on_bit(&gt->reset.flags,
1389	I915_RESET_ENGINE + engine->id,	1195	I915_RESET_ENGINE + engine->id,
1390	TASK_UNINTERRUPTIBLE);	1196	TASK_UNINTERRUPTIBLE);
1391	}	1197	}
1392		1198
1393	i915_reset_device(i915, engine_mask, msg);	1199	intel_gt_reset_global(gt, engine_mask, msg);
1394		1200
1395	for_each_engine(engine, i915, tmp) {	1201	for_each_engine(engine, gt->i915, tmp)
1396	clear_bit(I915_RESET_ENGINE + engine->id,	1202	clear_bit_unlock(I915_RESET_ENGINE + engine->id,
1397	&error->flags);	1203	&gt->reset.flags);
1398	}	1204	clear_bit_unlock(I915_RESET_BACKOFF, &gt->reset.flags);
1399		1205	smp_mb__after_atomic();
1400	clear_bit(I915_RESET_BACKOFF, &error->flags);	1206	wake_up_all(&gt->reset.queue);
1401	wake_up_all(&error->reset_queue);
1402		1207
1403	out:	1208	out:
1404	intel_runtime_pm_put(&i915->runtime_pm, wakeref);	1209	intel_runtime_pm_put(&gt->i915->runtime_pm, wakeref);
1405	}	1210	}
1406		1211
1407	int i915_reset_trylock(struct drm_i915_private *i915)	1212	int intel_gt_reset_trylock(struct intel_gt *gt)
1408	{	1213	{
1409	struct i915_gpu_error *error = &i915->gpu_error;
1410	int srcu;	1214	int srcu;
1411		1215
1412	might_lock(&error->reset_backoff_srcu);	1216	might_lock(&gt->reset.backoff_srcu);
1413	might_sleep();	1217	might_sleep();
1414		1218
1415	rcu_read_lock();	1219	rcu_read_lock();
1416	while (test_bit(I915_RESET_BACKOFF, &error->flags)) {	1220	while (test_bit(I915_RESET_BACKOFF, &gt->reset.flags)) {
1417	rcu_read_unlock();	1221	rcu_read_unlock();
1418		1222
1419	if (wait_event_interruptible(error->reset_queue,	1223	if (wait_event_interruptible(gt->reset.queue,
1420	!test_bit(I915_RESET_BACKOFF,	1224	!test_bit(I915_RESET_BACKOFF,
1421	&error->flags)))	1225	&gt->reset.flags)))
1422	return -EINTR;	1226	return -EINTR;
1423		1227
1424	rcu_read_lock();	1228	rcu_read_lock();
1425	}	1229	}
1426	srcu = srcu_read_lock(&error->reset_backoff_srcu);	1230	srcu = srcu_read_lock(&gt->reset.backoff_srcu);
1427	rcu_read_unlock();	1231	rcu_read_unlock();
1428		1232
1429	return srcu;	1233	return srcu;
1430	}	1234	}
1431		1235
1432	void i915_reset_unlock(struct drm_i915_private *i915, int tag)	1236	void intel_gt_reset_unlock(struct intel_gt *gt, int tag)
1433	__releases(&i915->gpu_error.reset_backoff_srcu)	1237	__releases(&gt->reset.backoff_srcu)
1434	{	1238	{
1435	struct i915_gpu_error *error = &i915->gpu_error;	1239	srcu_read_unlock(&gt->reset.backoff_srcu, tag);
1436
1437	srcu_read_unlock(&error->reset_backoff_srcu, tag);
1438	}	1240	}
1439		1241
1440	int i915_terminally_wedged(struct drm_i915_private *i915)	1242	int intel_gt_terminally_wedged(struct intel_gt *gt)
1441	{	1243	{
1442	struct i915_gpu_error *error = &i915->gpu_error;
1443
1444	might_sleep();	1244	might_sleep();
1445		1245
1446	if (!__i915_wedged(error))	1246	if (!intel_gt_is_wedged(gt))
1447	return 0;	1247	return 0;
1448		1248
1449	/* Reset still in progress? Maybe we will recover? */	1249	/* Reset still in progress? Maybe we will recover? */
1450	if (!test_bit(I915_RESET_BACKOFF, &error->flags))	1250	if (!test_bit(I915_RESET_BACKOFF, &gt->reset.flags))
1451	return -EIO;	1251	return -EIO;
1452		1252
1453	/* XXX intel_reset_finish() still takes struct_mutex!!! */	1253	/* XXX intel_reset_finish() still takes struct_mutex!!! */
1454	if (mutex_is_locked(&i915->drm.struct_mutex))	1254	if (mutex_is_locked(&gt->i915->drm.struct_mutex))
1455	return -EAGAIN;	1255	return -EAGAIN;
1456		1256
1457	if (wait_event_interruptible(error->reset_queue,	1257	if (wait_event_interruptible(gt->reset.queue,
1458	!test_bit(I915_RESET_BACKOFF,	1258	!test_bit(I915_RESET_BACKOFF,
1459	&error->flags)))	1259	&gt->reset.flags)))
1460	return -EINTR;	1260	return -EINTR;
1461		1261
1462	return __i915_wedged(error) ? -EIO : 0;	1262	return intel_gt_is_wedged(gt) ? -EIO : 0;
		1263	}
		1264
		1265	void intel_gt_init_reset(struct intel_gt *gt)
		1266	{
		1267	init_waitqueue_head(&gt->reset.queue);
		1268	mutex_init(&gt->reset.mutex);
		1269	init_srcu_struct(&gt->reset.backoff_srcu);
		1270	}
		1271
		1272	void intel_gt_fini_reset(struct intel_gt *gt)
		1273	{
		1274	cleanup_srcu_struct(&gt->reset.backoff_srcu);
1463	}	1275	}
1464		1276
1465	static void i915_wedge_me(struct work_struct *work)	1277	static void intel_wedge_me(struct work_struct *work)
1466	{	1278	{
1467	struct i915_wedge_me w = container_of(work, typeof(w), work.work);	1279	struct intel_wedge_me w = container_of(work, typeof(w), work.work);
1468		1280
1469	dev_err(w->i915->drm.dev,	1281	dev_err(w->gt->i915->drm.dev,
1470	"%s timed out, cancelling all in-flight rendering.\n",	1282	"%s timed out, cancelling all in-flight rendering.\n",
1471	w->name);	1283	w->name);
1472	i915_gem_set_wedged(w->i915);	1284	intel_gt_set_wedged(w->gt);
1473	}	1285	}
1474		1286
1475	void __i915_init_wedge(struct i915_wedge_me *w,	1287	void __intel_init_wedge(struct intel_wedge_me *w,
1476	struct drm_i915_private *i915,	1288	struct intel_gt *gt,
1477	long timeout,	1289	long timeout,
1478	const char *name)	1290	const char *name)
1479	{	1291	{
1480	w->i915 = i915;	1292	w->gt = gt;
1481	w->name = name;	1293	w->name = name;
1482		1294
1483	INIT_DELAYED_WORK_ONSTACK(&w->work, i915_wedge_me);	1295	INIT_DELAYED_WORK_ONSTACK(&w->work, intel_wedge_me);
1484	schedule_delayed_work(&w->work, timeout);	1296	schedule_delayed_work(&w->work, timeout);
1485	}	1297	}
1486		1298
1487	void __i915_fini_wedge(struct i915_wedge_me *w)	1299	void __intel_fini_wedge(struct intel_wedge_me *w)
1488	{	1300	{
1489	cancel_delayed_work_sync(&w->work);	1301	cancel_delayed_work_sync(&w->work);
1490	destroy_delayed_work_on_stack(&w->work);	1302	destroy_delayed_work_on_stack(&w->work);
1491	w->i915 = NULL;	1303	w->gt = NULL;
1492	}	1304	}
1493		1305
1494	#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)	1306	#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)

drivers/gpu/drm/i915/gt/intel_reset.h+42−33

@@ -11,58 +11,67 @@ · 10 unmodified lines
11	#include <linux/types.h>	11	#include <linux/types.h>
12	#include <linux/srcu.h>	12	#include <linux/srcu.h>
13		13
14	#include "gt/intel_engine_types.h"	14	#include "intel_engine_types.h"
		15	#include "intel_reset_types.h"
15		16
16	struct drm_i915_private;	17	struct drm_i915_private;
17	struct i915_request;	18	struct i915_request;
18	struct intel_engine_cs;	19	struct intel_engine_cs;
		20	struct intel_gt;
19	struct intel_guc;	21	struct intel_guc;
20		22
		23	void intel_gt_init_reset(struct intel_gt *gt);
		24	void intel_gt_fini_reset(struct intel_gt *gt);
		25
21	__printf(4, 5)	26	__printf(4, 5)
22	void i915_handle_error(struct drm_i915_private *i915,	27	void intel_gt_handle_error(struct intel_gt *gt,
23	intel_engine_mask_t engine_mask,	28	intel_engine_mask_t engine_mask,
24	unsigned long flags,	29	unsigned long flags,
25	const char *fmt, ...);	30	const char *fmt, ...);
26	#define I915_ERROR_CAPTURE BIT(0)	31	#define I915_ERROR_CAPTURE BIT(0)
27		32
28	void i915_check_and_clear_faults(struct drm_i915_private *i915);	33	void intel_gt_reset(struct intel_gt *gt,
29		34	intel_engine_mask_t stalled_mask,
30	void i915_reset(struct drm_i915_private *i915,	35	const char *reason);
31	intel_engine_mask_t stalled_mask,	36	int intel_engine_reset(struct intel_engine_cs *engine,
32	const char *reason);	37	const char *reason);
33	int i915_reset_engine(struct intel_engine_cs *engine,
34	const char *reason);
35
36	void i915_reset_request(struct i915_request *rq, bool guilty);
37		38
38	int __must_check i915_reset_trylock(struct drm_i915_private *i915);	39	void __i915_request_reset(struct i915_request *rq, bool guilty);
39	void i915_reset_unlock(struct drm_i915_private *i915, int tag);
40		40
41	int i915_terminally_wedged(struct drm_i915_private *i915);	41	int __must_check intel_gt_reset_trylock(struct intel_gt *gt);
		42	void intel_gt_reset_unlock(struct intel_gt *gt, int tag);
42		43
43	bool intel_has_gpu_reset(struct drm_i915_private *i915);	44	void intel_gt_set_wedged(struct intel_gt *gt);
44	bool intel_has_reset_engine(struct drm_i915_private *i915);	45	bool intel_gt_unset_wedged(struct intel_gt *gt);
		46	int intel_gt_terminally_wedged(struct intel_gt *gt);
45		47
46	int intel_gpu_reset(struct drm_i915_private *i915,	48	int __intel_gt_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask);
47	intel_engine_mask_t engine_mask);
48		49
49	int intel_reset_guc(struct drm_i915_private *i915);	50	int intel_reset_guc(struct intel_gt *gt);
50		51
51	struct i915_wedge_me {	52	struct intel_wedge_me {
52	struct delayed_work work;	53	struct delayed_work work;
53	struct drm_i915_private *i915;	54	struct intel_gt *gt;
54	const char *name;	55	const char *name;
55	};	56	};
56		57
57	void __i915_init_wedge(struct i915_wedge_me *w,	58	void __intel_init_wedge(struct intel_wedge_me *w,
58	struct drm_i915_private *i915,	59	struct intel_gt *gt,
59	long timeout,	60	long timeout,
60	const char *name);	61	const char *name);
61	void __i915_fini_wedge(struct i915_wedge_me *w);	62	void __intel_fini_wedge(struct intel_wedge_me *w);
62		63
63	#define i915_wedge_on_timeout(W, DEV, TIMEOUT) \	64	#define intel_wedge_on_timeout(W, GT, TIMEOUT) \
64	for (__i915_init_wedge((W), (DEV), (TIMEOUT), __func__); \	65	for (__intel_init_wedge((W), (GT), (TIMEOUT), __func__); \
65	(W)->i915; \	66	(W)->gt; \
66	__i915_fini_wedge((W)))	67	__intel_fini_wedge((W)))
		68
		69	static inline bool __intel_reset_failed(const struct intel_reset *reset)
		70	{
		71	return unlikely(test_bit(I915_WEDGED, &reset->flags));
		72	}
		73
		74	bool intel_has_gpu_reset(struct drm_i915_private *i915);
		75	bool intel_has_reset_engine(struct drm_i915_private *i915);
67		76
68	#endif /* I915_RESET_H */	77	#endif /* I915_RESET_H */

drivers/gpu/drm/i915/gt/intel_reset_types.h+50−0

@@ -0,0 +1,50 @@
	1	/* SPDX-License-Identifier: MIT */
	2	/*
	3	* Copyright © 2019 Intel Corporation
	4	*/
	5
	6	#ifndef __INTEL_RESET_TYPES_H_
	7	#define __INTEL_RESET_TYPES_H_
	8
	9	#include <linux/mutex.h>
	10	#include <linux/wait.h>
	11	#include <linux/srcu.h>
	12
	13	struct intel_reset {
	14	/**
	15	* flags: Control various stages of the GPU reset
	16	*
	17	* #I915_RESET_BACKOFF - When we start a global reset, we need to
	18	* serialise with any other users attempting to do the same, and
	19	* any global resources that may be clobber by the reset (such as
	20	* FENCE registers).
	21	*
	22	* #I915_RESET_ENGINE[num_engines] - Since the driver doesn't need to
	23	* acquire the struct_mutex to reset an engine, we need an explicit
	24	* flag to prevent two concurrent reset attempts in the same engine.
	25	* As the number of engines continues to grow, allocate the flags from
	26	* the most significant bits.
	27	*
	28	* #I915_WEDGED - If reset fails and we can no longer use the GPU,
	29	* we set the #I915_WEDGED bit. Prior to command submission, e.g.
	30	* i915_request_alloc(), this bit is checked and the sequence
	31	* aborted (with -EIO reported to userspace) if set.
	32	*/
	33	unsigned long flags;
	34	#define I915_RESET_BACKOFF 0
	35	#define I915_RESET_MODESET 1
	36	#define I915_RESET_ENGINE 2
	37	#define I915_WEDGED (BITS_PER_LONG - 1)
	38
	39	struct mutex mutex; /* serialises wedging/unwedging */
	40
	41	/**
	42	* Waitqueue to signal when the reset has completed. Used by clients
	43	* that wait for dev_priv->mm.wedged to settle.
	44	*/
	45	wait_queue_head_t queue;
	46
	47	struct srcu_struct backoff_srcu;
	48	};
	49
	50	#endif /* _INTEL_RESET_TYPES_H_ */

drivers/gpu/drm/i915/gt/intel_ringbuffer.c+141−77

 #include "gem/i915_gem_context.h"
 #include "i915_drv.h"
-#include "i915_gem_render_state.h"
 #include "i915_trace.h"
 #include "intel_context.h"
+#include "intel_gt.h"
 #include "intel_reset.h"
 #include "intel_workarounds.h"
 	*cs++ = cmd;
 	while (num_store_dw--) {
 		*cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
-		*cs++ = i915_scratch_offset(rq->i915);
+		*cs++ = intel_gt_scratch_offset(rq->engine->gt,
+						INTEL_GT_SCRATCH_FIELD_DEFAULT);
 		*cs++ = 0;
 	}
 	*cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH;
 	 */
 	if (mode & EMIT_INVALIDATE) {
 		*cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE;
-		*cs++ = i915_scratch_offset(rq->i915) | PIPE_CONTROL_GLOBAL_GTT;
+		*cs++ = intel_gt_scratch_offset(rq->engine->gt,
+						INTEL_GT_SCRATCH_FIELD_DEFAULT) |
+			PIPE_CONTROL_GLOBAL_GTT;
 		*cs++ = 0;
 		*cs++ = 0;
 			*cs++ = MI_FLUSH;
 		*cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE;
-		*cs++ = i915_scratch_offset(rq->i915) | PIPE_CONTROL_GLOBAL_GTT;
+		*cs++ = intel_gt_scratch_offset(rq->engine->gt,
+						INTEL_GT_SCRATCH_FIELD_DEFAULT) |
+			PIPE_CONTROL_GLOBAL_GTT;
 		*cs++ = 0;
 		*cs++ = 0;
 	}
 static int
 gen6_emit_post_sync_nonzero_flush(struct i915_request *rq)
 {
-	u32 scratch_addr = i915_scratch_offset(rq->i915) + 2 * CACHELINE_BYTES;
+	u32 scratch_addr =
+		intel_gt_scratch_offset(rq->engine->gt,
+					INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH);
 	u32 *cs;
 	cs = intel_ring_begin(rq, 6);
 static int
 gen6_render_ring_flush(struct i915_request *rq, u32 mode)
 {
-	u32 scratch_addr = i915_scratch_offset(rq->i915) + 2 * CACHELINE_BYTES;
+	u32 scratch_addr =
+		intel_gt_scratch_offset(rq->engine->gt,
+					INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH);
 	u32 *cs, flags = 0;
 	int ret;
 	*cs++ = GFX_OP_PIPE_CONTROL(4);
 	*cs++ = PIPE_CONTROL_QW_WRITE;
-	*cs++ = i915_scratch_offset(rq->i915) | PIPE_CONTROL_GLOBAL_GTT;
+	*cs++ = intel_gt_scratch_offset(rq->engine->gt,
+					INTEL_GT_SCRATCH_FIELD_DEFAULT) |
+		PIPE_CONTROL_GLOBAL_GTT;
 	*cs++ = 0;
 	/* Finally we can flush and with it emit the breadcrumb */
 static int
 gen7_render_ring_flush(struct i915_request *rq, u32 mode)
 {
-	u32 scratch_addr = i915_scratch_offset(rq->i915) + 2 * CACHELINE_BYTES;
+	u32 scratch_addr =
+		intel_gt_scratch_offset(rq->engine->gt,
+					INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH);
 	u32 *cs, flags = 0;
 	/*
 static void reset_prepare(struct intel_engine_cs *engine)
 {
-	intel_engine_stop_cs(engine);
+	struct intel_uncore *uncore = engine->uncore;
+	const u32 base = engine->mmio_base;
+	/*
+	 * We stop engines, otherwise we might get failed reset and a
+	 * dead gpu (on elk). Also as modern gpu as kbl can suffer
+	 * from system hang if batchbuffer is progressing when
+	 * the reset is issued, regardless of READY_TO_RESET ack.
+	 * Thus assume it is best to stop engines on all gens
+	 * where we have a gpu reset.
+	 *
+	 * WaKBLVECSSemaphoreWaitPoll:kbl (on ALL_ENGINES)
+	 *
+	 * WaMediaResetMainRingCleanup:ctg,elk (presumably)
+	 *
+	 * FIXME: Wa for more modern gens needs to be validated
+	 */
+	GEM_TRACE("%s\n", engine->name);
+	if (intel_engine_stop_cs(engine))
+		GEM_TRACE("%s: timed out on STOP_RING\n", engine->name);
+	intel_uncore_write_fw(uncore,
+			      RING_HEAD(base),
+			      intel_uncore_read_fw(uncore, RING_TAIL(base)));
+	intel_uncore_posting_read_fw(uncore, RING_HEAD(base)); /* paranoia */
+	intel_uncore_write_fw(uncore, RING_HEAD(base), 0);
+	intel_uncore_write_fw(uncore, RING_TAIL(base), 0);
+	intel_uncore_posting_read_fw(uncore, RING_TAIL(base));
+	/* The ring must be empty before it is disabled */
+	intel_uncore_write_fw(uncore, RING_CTL(base), 0);
+	/* Check acts as a post */
+	if (intel_uncore_read_fw(uncore, RING_HEAD(base)))
+		GEM_TRACE("%s: ring head [%x] not parked\n",
+			  engine->name,
+			  intel_uncore_read_fw(uncore, RING_HEAD(base)));
 }
 static void reset_ring(struct intel_engine_cs *engine, bool stalled)
 		 * If the request was innocent, we try to replay the request
 		 * with the restored context.
 		 */
-		i915_reset_request(rq, stalled);
+		__i915_request_reset(rq, stalled);
 		GEM_BUG_ON(rq->ring != engine->buffer);
 		head = rq->head;
 {
 }
-static int intel_rcs_ctx_init(struct i915_request *rq)
-{
-	int ret;
-	ret = intel_engine_emit_ctx_wa(rq);
-	if (ret != 0)
-		return ret;
-	ret = i915_gem_render_state_emit(rq);
-	if (ret)
-		return ret;
-	return 0;
-}
 static int rcs_resume(struct intel_engine_cs *engine)
 {
 	struct drm_i915_private *dev_priv = engine->i915;
 	/* Flush/delay to ensure the RING_IMR is active before the GT IMR */
 	ENGINE_POSTING_READ(engine, RING_IMR);
-	gen6_unmask_pm_irq(engine->i915, engine->irq_enable_mask);
+	gen6_unmask_pm_irq(engine->gt, engine->irq_enable_mask);
 }
 static void
 hsw_vebox_irq_disable(struct intel_engine_cs *engine)
 {
 	ENGINE_WRITE(engine, RING_IMR, ~0);
-	gen6_mask_pm_irq(engine->i915, engine->irq_enable_mask);
+	gen6_mask_pm_irq(engine->gt, engine->irq_enable_mask);
 }
 static int
 		   u64 offset, u32 len,
 		   unsigned int dispatch_flags)
 {
-	u32 *cs, cs_offset = i915_scratch_offset(rq->i915);
+	u32 *cs, cs_offset =
+		intel_gt_scratch_offset(rq->engine->gt,
+					INTEL_GT_SCRATCH_FIELD_DEFAULT);
-	GEM_BUG_ON(rq->i915->gt.scratch->size < I830_WA_SIZE);
+	GEM_BUG_ON(rq->engine->gt->scratch->size < I830_WA_SIZE);
 	cs = intel_ring_begin(rq, 6);
 	if (IS_ERR(cs))
 	if (atomic_fetch_inc(&ring->pin_count))
 		return 0;
-	ret = i915_timeline_pin(ring->timeline);
+	ret = intel_timeline_pin(ring->timeline);
 	if (ret)
 		goto err_unpin;
 	GEM_BUG_ON(ring->vaddr);
 	ring->vaddr = addr;
+	GEM_TRACE("ring:%llx pin\n", ring->timeline->fence_context);
 	return 0;
 err_ring:
 	i915_vma_unpin(vma);
 err_timeline:
-	i915_timeline_unpin(ring->timeline);
+	intel_timeline_unpin(ring->timeline);
 err_unpin:
 	atomic_dec(&ring->pin_count);
 	return ret;
 	if (!atomic_dec_and_test(&ring->pin_count))
 		return;
+	GEM_TRACE("ring:%llx unpin\n", ring->timeline->fence_context);
 	/* Discard any unused bytes beyond that submitted to hw. */
 	intel_ring_reset(ring, ring->tail);
 	GEM_BUG_ON(!ring->vma);
+	i915_vma_unset_ggtt_write(ring->vma);
 	if (i915_vma_is_map_and_fenceable(ring->vma))
 		i915_vma_unpin_iomap(ring->vma);
 	else
 	ring->vma->obj->pin_global--;
 	i915_vma_unpin(ring->vma);
-	i915_timeline_unpin(ring->timeline);
+	intel_timeline_unpin(ring->timeline);
 }
-static struct i915_vma *
+static struct i915_vma *create_ring_vma(struct i915_ggtt *ggtt, int size)
-intel_ring_create_vma(struct drm_i915_private *dev_priv, int size)
 {
-	struct i915_address_space *vm = &dev_priv->ggtt.vm;
+	struct i915_address_space *vm = &ggtt->vm;
+	struct drm_i915_private *i915 = vm->i915;
 	struct drm_i915_gem_object *obj;
 	struct i915_vma *vma;
-	obj = i915_gem_object_create_stolen(dev_priv, size);
+	obj = i915_gem_object_create_stolen(i915, size);
 	if (!obj)
-		obj = i915_gem_object_create_internal(dev_priv, size);
+		obj = i915_gem_object_create_internal(i915, size);
 	if (IS_ERR(obj))
 		return ERR_CAST(obj);
 struct intel_ring *
 intel_engine_create_ring(struct intel_engine_cs *engine,
-			 struct i915_timeline *timeline,
+			 struct intel_timeline *timeline,
 			 int size)
 {
+	struct drm_i915_private *i915 = engine->i915;
 	struct intel_ring *ring;
 	struct i915_vma *vma;
 	kref_init(&ring->ref);
 	INIT_LIST_HEAD(&ring->request_list);
-	ring->timeline = i915_timeline_get(timeline);
+	ring->timeline = intel_timeline_get(timeline);
 	ring->size = size;
 	/* Workaround an erratum on the i830 which causes a hang if
 	 * of the buffer.
 	 */
 	ring->effective_size = size;
-	if (IS_I830(engine->i915) || IS_I845G(engine->i915))
+	if (IS_I830(i915) || IS_I845G(i915))
 		ring->effective_size -= 2 * CACHELINE_BYTES;
 	intel_ring_update_space(ring);
-	vma = intel_ring_create_vma(engine->i915, size);
+	vma = create_ring_vma(engine->gt->ggtt, size);
 	if (IS_ERR(vma)) {
 		kfree(ring);
 		return ERR_CAST(vma);
 	i915_vma_close(ring->vma);
 	i915_vma_put(ring->vma);
-	i915_timeline_put(ring->timeline);
+	intel_timeline_put(ring->timeline);
 	kfree(ring);
 }
 static void __ring_context_fini(struct intel_context *ce)
 {
-	GEM_BUG_ON(i915_gem_object_is_active(ce->state->obj));
 	i915_gem_object_put(ce->state->obj);
 }
 	if (ce->state)
 		__ring_context_fini(ce);
+	intel_context_fini(ce);
 	intel_context_free(ce);
 }
-static int __context_pin_ppgtt(struct i915_gem_context *ctx)
+static struct i915_address_space *vm_alias(struct intel_context *ce)
+{
+	struct i915_address_space *vm;
+	vm = ce->vm;
+	if (i915_is_ggtt(vm))
+		vm = &i915_vm_to_ggtt(vm)->alias->vm;
+	return vm;
+}
+static int __context_pin_ppgtt(struct intel_context *ce)
 {
 	struct i915_address_space *vm;
 	int err = 0;
-	vm = ctx->vm ?: &ctx->i915->mm.aliasing_ppgtt->vm;
+	vm = vm_alias(ce);
 	if (vm)
 		err = gen6_ppgtt_pin(i915_vm_to_ppgtt((vm)));
 	return err;
 }
-static void __context_unpin_ppgtt(struct i915_gem_context *ctx)
+static void __context_unpin_ppgtt(struct intel_context *ce)
 {
 	struct i915_address_space *vm;
-	vm = ctx->vm ?: &ctx->i915->mm.aliasing_ppgtt->vm;
+	vm = vm_alias(ce);
 	if (vm)
 		gen6_ppgtt_unpin(i915_vm_to_ppgtt(vm));
 }
 static void ring_context_unpin(struct intel_context *ce)
 {
-	__context_unpin_ppgtt(ce->gem_context);
+	__context_unpin_ppgtt(ce);
 }
 static struct i915_vma *
 		i915_gem_object_unpin_map(obj);
 	}
-	vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
+	vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
 	if (IS_ERR(vma)) {
 		err = PTR_ERR(vma);
 		goto err_obj;
 		ce->state = vma;
 	}
-	err = intel_context_active_acquire(ce, PIN_HIGH);
+	err = intel_context_active_acquire(ce);
 	if (err)
 		return err;
-	err = __context_pin_ppgtt(ce->gem_context);
+	err = __context_pin_ppgtt(ce);
 	if (err)
 		goto err_active;
 	*cs++ = MI_LOAD_REGISTER_IMM(1);
 	*cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));
-	*cs++ = ppgtt->pd->base.ggtt_offset << 10;
+	*cs++ = px_base(ppgtt->pd)->ggtt_offset << 10;
 	intel_ring_advance(rq, cs);
 	/* Stall until the page table load is complete */
 	*cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
 	*cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));
-	*cs++ = i915_scratch_offset(rq->i915);
+	*cs++ = intel_gt_scratch_offset(rq->engine->gt,
+					INTEL_GT_SCRATCH_FIELD_DEFAULT);
 	*cs++ = MI_NOOP;
 	intel_ring_advance(rq, cs);
 			/* Insert a delay before the next switch! */
 			*cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
 			*cs++ = i915_mmio_reg_offset(last_reg);
-			*cs++ = i915_scratch_offset(rq->i915);
+			*cs++ = intel_gt_scratch_offset(rq->engine->gt,
+							INTEL_GT_SCRATCH_FIELD_DEFAULT);
 			*cs++ = MI_NOOP;
 		}
 		*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
 	return 0;
 }
-static int remap_l3(struct i915_request *rq, int slice)
+static int remap_l3_slice(struct i915_request *rq, int slice)
 {
 	u32 *cs, *remap_info = rq->i915->l3_parity.remap_info[slice];
 	int i;
 	return 0;
 }
+static int remap_l3(struct i915_request *rq)
+{
+	struct i915_gem_context *ctx = rq->gem_context;
+	int i, err;
+	if (!ctx->remap_slice)
+		return 0;
+	for (i = 0; i < MAX_L3_SLICES; i++) {
+		if (!(ctx->remap_slice & BIT(i)))
+			continue;
+		err = remap_l3_slice(rq, i);
+		if (err)
+			return err;
+	}
+	ctx->remap_slice = 0;
+	return 0;
+}
 static int switch_context(struct i915_request *rq)
 {
 	struct intel_engine_cs *engine = rq->engine;
-	struct i915_gem_context *ctx = rq->gem_context;
+	struct i915_address_space *vm = vm_alias(rq->hw_context);
-	struct i915_address_space *vm =
-		ctx->vm ?: &rq->i915->mm.aliasing_ppgtt->vm;
 	unsigned int unwind_mm = 0;
 	u32 hw_flags = 0;
-	int ret, i;
+	int ret;
 	GEM_BUG_ON(HAS_EXECLISTS(rq->i915));
 		 * as nothing actually executes using the kernel context; it
 		 * is purely used for flushing user contexts.
 		 */
-		if (i915_gem_context_is_kernel(ctx))
+		if (i915_gem_context_is_kernel(rq->gem_context))
 			hw_flags = MI_RESTORE_INHIBIT;
 		ret = mi_set_context(rq, hw_flags);
 			goto err_mm;
 	}
-	if (ctx->remap_slice) {
+	ret = remap_l3(rq);
-		for (i = 0; i < MAX_L3_SLICES; i++) {
+	if (ret)
-			if (!(ctx->remap_slice & BIT(i)))
+		goto err_mm;
-				continue;
-			ret = remap_l3(rq, i);
-			if (ret)
-				goto err_mm;
-		}
-		ctx->remap_slice = 0;
-	}
 	return 0;
 	engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
 	if (INTEL_GEN(i915) >= 7) {
-		engine->init_context = intel_rcs_ctx_init;
 		engine->emit_flush = gen7_render_ring_flush;
 		engine->emit_fini_breadcrumb = gen7_rcs_emit_breadcrumb;
 	} else if (IS_GEN(i915, 6)) {
-		engine->init_context = intel_rcs_ctx_init;
 		engine->emit_flush = gen6_render_ring_flush;
 		engine->emit_fini_breadcrumb = gen6_rcs_emit_breadcrumb;
 	} else if (IS_GEN(i915, 5)) {
 int intel_ring_submission_init(struct intel_engine_cs *engine)
 {
-	struct i915_timeline *timeline;
+	struct intel_timeline *timeline;
 	struct intel_ring *ring;
 	int err;
-	timeline = i915_timeline_create(engine->i915, engine->status_page.vma);
+	timeline = intel_timeline_create(engine->gt, engine->status_page.vma);
 	if (IS_ERR(timeline)) {
 		err = PTR_ERR(timeline);
 		goto err;
 	GEM_BUG_ON(timeline->has_initial_breadcrumb);
 	ring = intel_engine_create_ring(engine, timeline, 32 * PAGE_SIZE);
-	i915_timeline_put(timeline);
+	intel_timeline_put(timeline);
 	if (IS_ERR(ring)) {
 		err = PTR_ERR(ring);
 		goto err;

drivers/gpu/drm/i915/gt/intel_timeline.crenamed from drivers/gpu/drm/i915/i915_timeline.c+120−110

  * Copyright © 2016-2018 Intel Corporation
  */
+#include "gt/intel_gt_types.h"
 #include "i915_drv.h"
 #include "i915_active.h"
 #include "i915_syncmap.h"
-#include "i915_timeline.h"
+#include "gt/intel_timeline.h"
 #define ptr_set_bit(ptr, bit) ((typeof(ptr))((unsigned long)(ptr) | BIT(bit)))
 #define ptr_test_bit(ptr, bit) ((unsigned long)(ptr) & BIT(bit))
-struct i915_timeline_hwsp {
+struct intel_timeline_hwsp {
-	struct i915_gt_timelines *gt;
+	struct intel_gt *gt;
+	struct intel_gt_timelines *gt_timelines;
 	struct list_head free_link;
 	struct i915_vma *vma;
 	u64 free_bitmap;
 };
-struct i915_timeline_cacheline {
+struct intel_timeline_cacheline {
 	struct i915_active active;
-	struct i915_timeline_hwsp *hwsp;
+	struct intel_timeline_hwsp *hwsp;
 	void *vaddr;
 #define CACHELINE_BITS 6
 #define CACHELINE_FREE CACHELINE_BITS
 };
-static inline struct drm_i915_private *
+static struct i915_vma *__hwsp_alloc(struct intel_gt *gt)
-hwsp_to_i915(struct i915_timeline_hwsp *hwsp)
-{
-	return container_of(hwsp->gt, struct drm_i915_private, gt.timelines);
-}
-static struct i915_vma *__hwsp_alloc(struct drm_i915_private *i915)
 {
+	struct drm_i915_private *i915 = gt->i915;
 	struct drm_i915_gem_object *obj;
 	struct i915_vma *vma;
 	i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC);
-	vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
+	vma = i915_vma_instance(obj, &gt->ggtt->vm, NULL);
 	if (IS_ERR(vma))
 		i915_gem_object_put(obj);
 }
 static struct i915_vma *
-hwsp_alloc(struct i915_timeline *timeline, unsigned int *cacheline)
+hwsp_alloc(struct intel_timeline *timeline, unsigned int *cacheline)
 {
-	struct drm_i915_private *i915 = timeline->i915;
+	struct intel_gt_timelines *gt = &timeline->gt->timelines;
-	struct i915_gt_timelines *gt = &i915->gt.timelines;
+	struct intel_timeline_hwsp *hwsp;
-	struct i915_timeline_hwsp *hwsp;
 	BUILD_BUG_ON(BITS_PER_TYPE(u64) * CACHELINE_BYTES > PAGE_SIZE);
 		if (!hwsp)
 			return ERR_PTR(-ENOMEM);
-		vma = __hwsp_alloc(i915);
+		vma = __hwsp_alloc(timeline->gt);
 		if (IS_ERR(vma)) {
 			kfree(hwsp);
 			return vma;
 		}
 		vma->private = hwsp;
+		hwsp->gt = timeline->gt;
 		hwsp->vma = vma;
 		hwsp->free_bitmap = ~0ull;
-		hwsp->gt = gt;
+		hwsp->gt_timelines = gt;
 		spin_lock_irq(&gt->hwsp_lock);
 		list_add(&hwsp->free_link, &gt->hwsp_free_list);
 	return hwsp->vma;
 }
-static void __idle_hwsp_free(struct i915_timeline_hwsp *hwsp, int cacheline)
+static void __idle_hwsp_free(struct intel_timeline_hwsp *hwsp, int cacheline)
 {
-	struct i915_gt_timelines *gt = hwsp->gt;
+	struct intel_gt_timelines *gt = hwsp->gt_timelines;
 	unsigned long flags;
 	spin_lock_irqsave(&gt->hwsp_lock, flags);
 	spin_unlock_irqrestore(&gt->hwsp_lock, flags);
 }
-static void __idle_cacheline_free(struct i915_timeline_cacheline *cl)
+static void __idle_cacheline_free(struct intel_timeline_cacheline *cl)
 {
 	GEM_BUG_ON(!i915_active_is_idle(&cl->active));
 static void __cacheline_retire(struct i915_active *active)
 {
-	struct i915_timeline_cacheline *cl =
+	struct intel_timeline_cacheline *cl =
 		container_of(active, typeof(*cl), active);
 	i915_vma_unpin(cl->hwsp->vma);
 		__idle_cacheline_free(cl);
 }
-static struct i915_timeline_cacheline *
+static int __cacheline_active(struct i915_active *active)
-cacheline_alloc(struct i915_timeline_hwsp *hwsp, unsigned int cacheline)
+{
+	struct intel_timeline_cacheline *cl =
+		container_of(active, typeof(*cl), active);
+	__i915_vma_pin(cl->hwsp->vma);
+	return 0;
+}
+static struct intel_timeline_cacheline *
+cacheline_alloc(struct intel_timeline_hwsp *hwsp, unsigned int cacheline)
 {
-	struct i915_timeline_cacheline *cl;
+	struct intel_timeline_cacheline *cl;
 	void *vaddr;
 	GEM_BUG_ON(cacheline >= BIT(CACHELINE_BITS));
 	cl->hwsp = hwsp;
 	cl->vaddr = page_pack_bits(vaddr, cacheline);
-	i915_active_init(hwsp_to_i915(hwsp), &cl->active, __cacheline_retire);
+	i915_active_init(hwsp->gt->i915, &cl->active,
+			 __cacheline_active, __cacheline_retire);
 	return cl;
 }
-static void cacheline_acquire(struct i915_timeline_cacheline *cl)
+static void cacheline_acquire(struct intel_timeline_cacheline *cl)
 {
-	if (cl && i915_active_acquire(&cl->active))
+	if (cl)
-		__i915_vma_pin(cl->hwsp->vma);
+		i915_active_acquire(&cl->active);
 }
-static void cacheline_release(struct i915_timeline_cacheline *cl)
+static void cacheline_release(struct intel_timeline_cacheline *cl)
 {
 	if (cl)
 		i915_active_release(&cl->active);
 }
-static void cacheline_free(struct i915_timeline_cacheline *cl)
+static void cacheline_free(struct intel_timeline_cacheline *cl)
 {
 	GEM_BUG_ON(ptr_test_bit(cl->vaddr, CACHELINE_FREE));
 	cl->vaddr = ptr_set_bit(cl->vaddr, CACHELINE_FREE);
 		__idle_cacheline_free(cl);
 }
-int i915_timeline_init(struct drm_i915_private *i915,
+int intel_timeline_init(struct intel_timeline *timeline,
-		       struct i915_timeline *timeline,
+			struct intel_gt *gt,
-		       struct i915_vma *hwsp)
+			struct i915_vma *hwsp)
 {
 	void *vaddr;
-	/*
+	kref_init(&timeline->kref);
-	 * Ideally we want a set of engines on a single leaf as we expect
-	 * to mostly be tracking synchronisation between engines. It is not
-	 * a huge issue if this is not the case, but we may want to mitigate
-	 * any page crossing penalties if they become an issue.
-	 *
-	 * Called during early_init before we know how many engines there are.
-	 */
-	BUILD_BUG_ON(KSYNCMAP < I915_NUM_ENGINES);
-	timeline->i915 = i915;
+	timeline->gt = gt;
 	timeline->pin_count = 0;
 	timeline->has_initial_breadcrumb = !hwsp;
 	timeline->hwsp_cacheline = NULL;
 	if (!hwsp) {
-		struct i915_timeline_cacheline *cl;
+		struct intel_timeline_cacheline *cl;
 		unsigned int cacheline;
 		hwsp = hwsp_alloc(timeline, &cacheline);
 	return 0;
 }
-void i915_timelines_init(struct drm_i915_private *i915)
+static void timelines_init(struct intel_gt *gt)
 {
-	struct i915_gt_timelines *gt = &i915->gt.timelines;
+	struct intel_gt_timelines *timelines = &gt->timelines;
-	mutex_init(&gt->mutex);
+	mutex_init(&timelines->mutex);
-	INIT_LIST_HEAD(&gt->active_list);
+	INIT_LIST_HEAD(&timelines->active_list);
-	spin_lock_init(&gt->hwsp_lock);
+	spin_lock_init(&timelines->hwsp_lock);
-	INIT_LIST_HEAD(&gt->hwsp_free_list);
+	INIT_LIST_HEAD(&timelines->hwsp_free_list);
+}
-	/* via i915_gem_wait_for_idle() */
+void intel_timelines_init(struct drm_i915_private *i915)
-	i915_gem_shrinker_taints_mutex(i915, &gt->mutex);
+{
+	timelines_init(&i915->gt);
 }
-static void timeline_add_to_active(struct i915_timeline *tl)
+static void timeline_add_to_active(struct intel_timeline *tl)
 {
-	struct i915_gt_timelines *gt = &tl->i915->gt.timelines;
+	struct intel_gt_timelines *gt = &tl->gt->timelines;
 	mutex_lock(&gt->mutex);
 	list_add(&tl->link, &gt->active_list);
 	mutex_unlock(&gt->mutex);
 }
-static void timeline_remove_from_active(struct i915_timeline *tl)
+static void timeline_remove_from_active(struct intel_timeline *tl)
 {
-	struct i915_gt_timelines *gt = &tl->i915->gt.timelines;
+	struct intel_gt_timelines *gt = &tl->gt->timelines;
 	mutex_lock(&gt->mutex);
 	list_del(&tl->link);
 	mutex_unlock(&gt->mutex);
 }
-/**
+static void timelines_park(struct intel_gt *gt)
- * i915_timelines_park - called when the driver idles
- * @i915: the drm_i915_private device
- *
- * When the driver is completely idle, we know that all of our sync points
- * have been signaled and our tracking is then entirely redundant. Any request
- * to wait upon an older sync point will be completed instantly as we know
- * the fence is signaled and therefore we will not even look them up in the
- * sync point map.
- */
-void i915_timelines_park(struct drm_i915_private *i915)
 {
-	struct i915_gt_timelines *gt = &i915->gt.timelines;
+	struct intel_gt_timelines *timelines = &gt->timelines;
-	struct i915_timeline *timeline;
+	struct intel_timeline *timeline;
-	mutex_lock(&gt->mutex);
+	mutex_lock(&timelines->mutex);
-	list_for_each_entry(timeline, &gt->active_list, link) {
+	list_for_each_entry(timeline, &timelines->active_list, link) {
 		/*
 		 * All known fences are completed so we can scrap
 		 * the current sync point tracking and start afresh,
 		 */
 		i915_syncmap_free(&timeline->sync);
 	}
-	mutex_unlock(&gt->mutex);
+	mutex_unlock(&timelines->mutex);
 }
-void i915_timeline_fini(struct i915_timeline *timeline)
+/**
+ * intel_timelines_park - called when the driver idles
+ * @i915: the drm_i915_private device
+ *
+ * When the driver is completely idle, we know that all of our sync points
+ * have been signaled and our tracking is then entirely redundant. Any request
+ * to wait upon an older sync point will be completed instantly as we know
+ * the fence is signaled and therefore we will not even look them up in the
+ * sync point map.
+ */
+void intel_timelines_park(struct drm_i915_private *i915)
+{
+	timelines_park(&i915->gt);
+}
+void intel_timeline_fini(struct intel_timeline *timeline)
 {
 	GEM_BUG_ON(timeline->pin_count);
 	GEM_BUG_ON(!list_empty(&timeline->requests));
 	i915_vma_put(timeline->hwsp_ggtt);
 }
-struct i915_timeline *
+struct intel_timeline *
-i915_timeline_create(struct drm_i915_private *i915,
+intel_timeline_create(struct intel_gt *gt, struct i915_vma *global_hwsp)
-		     struct i915_vma *global_hwsp)
 {
-	struct i915_timeline *timeline;
+	struct intel_timeline *timeline;
 	int err;
 	timeline = kzalloc(sizeof(*timeline), GFP_KERNEL);
 	if (!timeline)
 		return ERR_PTR(-ENOMEM);
-	err = i915_timeline_init(i915, timeline, global_hwsp);
+	err = intel_timeline_init(timeline, gt, global_hwsp);
 	if (err) {
 		kfree(timeline);
 		return ERR_PTR(err);
 	}
-	kref_init(&timeline->kref);
 	return timeline;
 }
-int i915_timeline_pin(struct i915_timeline *tl)
+int intel_timeline_pin(struct intel_timeline *tl)
 {
 	int err;
 	return err;
 }
-static u32 timeline_advance(struct i915_timeline *tl)
+static u32 timeline_advance(struct intel_timeline *tl)
 {
 	GEM_BUG_ON(!tl->pin_count);
 	GEM_BUG_ON(tl->seqno & tl->has_initial_breadcrumb);
 	return tl->seqno += 1 + tl->has_initial_breadcrumb;
 }
-static void timeline_rollback(struct i915_timeline *tl)
+static void timeline_rollback(struct intel_timeline *tl)
 {
 	tl->seqno -= 1 + tl->has_initial_breadcrumb;
 }
 static noinline int
-__i915_timeline_get_seqno(struct i915_timeline *tl,
+__intel_timeline_get_seqno(struct intel_timeline *tl,
-			  struct i915_request *rq,
+			   struct i915_request *rq,
-			  u32 *seqno)
+			   u32 *seqno)
 {
-	struct i915_timeline_cacheline *cl;
+	struct intel_timeline_cacheline *cl;
 	unsigned int cacheline;
 	struct i915_vma *vma;
 	void *vaddr;
 	return err;
 }
-int i915_timeline_get_seqno(struct i915_timeline *tl,
+int intel_timeline_get_seqno(struct intel_timeline *tl,
-			    struct i915_request *rq,
+			     struct i915_request *rq,
-			    u32 *seqno)
+			     u32 *seqno)
 {
 	*seqno = timeline_advance(tl);
 	/* Replace the HWSP on wraparound for HW semaphores */
 	if (unlikely(!*seqno && tl->hwsp_cacheline))
-		return __i915_timeline_get_seqno(tl, rq, seqno);
+		return __intel_timeline_get_seqno(tl, rq, seqno);
 	return 0;
 }
-static int cacheline_ref(struct i915_timeline_cacheline *cl,
+static int cacheline_ref(struct intel_timeline_cacheline *cl,
 			 struct i915_request *rq)
 {
 	return i915_active_ref(&cl->active, rq->fence.context, rq);
 }
-int i915_timeline_read_hwsp(struct i915_request *from,
+int intel_timeline_read_hwsp(struct i915_request *from,
-			    struct i915_request *to,
+			     struct i915_request *to,
-			    u32 *hwsp)
+			     u32 *hwsp)
 {
-	struct i915_timeline_cacheline *cl = from->hwsp_cacheline;
+	struct intel_timeline_cacheline *cl = from->hwsp_cacheline;
-	struct i915_timeline *tl = from->timeline;
+	struct intel_timeline *tl = from->timeline;
 	int err;
 	GEM_BUG_ON(to->timeline == tl);
 	return err;
 }
-void i915_timeline_unpin(struct i915_timeline *tl)
+void intel_timeline_unpin(struct intel_timeline *tl)
 {
 	GEM_BUG_ON(!tl->pin_count);
 	if (--tl->pin_count)
 	__i915_vma_unpin(tl->hwsp_ggtt);
 }
-void __i915_timeline_free(struct kref *kref)
+void __intel_timeline_free(struct kref *kref)
 {
-	struct i915_timeline *timeline =
+	struct intel_timeline *timeline =
 		container_of(kref, typeof(*timeline), kref);
-	i915_timeline_fini(timeline);
+	intel_timeline_fini(timeline);
 	kfree(timeline);
 }
-void i915_timelines_fini(struct drm_i915_private *i915)
+static void timelines_fini(struct intel_gt *gt)
 {
-	struct i915_gt_timelines *gt = &i915->gt.timelines;
+	struct intel_gt_timelines *timelines = &gt->timelines;
-	GEM_BUG_ON(!list_empty(&gt->active_list));
+	GEM_BUG_ON(!list_empty(&timelines->active_list));
-	GEM_BUG_ON(!list_empty(&gt->hwsp_free_list));
+	GEM_BUG_ON(!list_empty(&timelines->hwsp_free_list));
-	mutex_destroy(&gt->mutex);
+	mutex_destroy(&timelines->mutex);
+}
+void intel_timelines_fini(struct drm_i915_private *i915)
+{
+	timelines_fini(&i915->gt);
 }
 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
-#include "selftests/mock_timeline.c"
+#include "gt/selftests/mock_timeline.c"
-#include "selftests/i915_timeline.c"
+#include "gt/selftest_timeline.c"
 #endif

drivers/gpu/drm/i915/gt/intel_timeline.h+93−0

@@ -0,0 +1,93 @@
	1	/*
	2	* Copyright © 2016 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*
	23	*/
	24
	25	#ifndef I915_TIMELINE_H
	26	#define I915_TIMELINE_H
	27
	28	#include <linux/lockdep.h>
	29
	30	#include "i915_active.h"
	31	#include "i915_syncmap.h"
	32	#include "gt/intel_timeline_types.h"
	33
	34	int intel_timeline_init(struct intel_timeline *tl,
	35	struct intel_gt *gt,
	36	struct i915_vma *hwsp);
	37	void intel_timeline_fini(struct intel_timeline *tl);
	38
	39	struct intel_timeline *
	40	intel_timeline_create(struct intel_gt gt, struct i915_vma global_hwsp);
	41
	42	static inline struct intel_timeline *
	43	intel_timeline_get(struct intel_timeline *timeline)
	44	{
	45	kref_get(&timeline->kref);
	46	return timeline;
	47	}
	48
	49	void __intel_timeline_free(struct kref *kref);
	50	static inline void intel_timeline_put(struct intel_timeline *timeline)
	51	{
	52	kref_put(&timeline->kref, __intel_timeline_free);
	53	}
	54
	55	static inline int __intel_timeline_sync_set(struct intel_timeline *tl,
	56	u64 context, u32 seqno)
	57	{
	58	return i915_syncmap_set(&tl->sync, context, seqno);
	59	}
	60
	61	static inline int intel_timeline_sync_set(struct intel_timeline *tl,
	62	const struct dma_fence *fence)
	63	{
	64	return __intel_timeline_sync_set(tl, fence->context, fence->seqno);
	65	}
	66
	67	static inline bool __intel_timeline_sync_is_later(struct intel_timeline *tl,
	68	u64 context, u32 seqno)
	69	{
	70	return i915_syncmap_is_later(&tl->sync, context, seqno);
	71	}
	72
	73	static inline bool intel_timeline_sync_is_later(struct intel_timeline *tl,
	74	const struct dma_fence *fence)
	75	{
	76	return __intel_timeline_sync_is_later(tl, fence->context, fence->seqno);
	77	}
	78
	79	int intel_timeline_pin(struct intel_timeline *tl);
	80	int intel_timeline_get_seqno(struct intel_timeline *tl,
	81	struct i915_request *rq,
	82	u32 *seqno);
	83	void intel_timeline_unpin(struct intel_timeline *tl);
	84
	85	int intel_timeline_read_hwsp(struct i915_request *from,
	86	struct i915_request *until,
	87	u32 *hwsp_offset);
	88
	89	void intel_timelines_init(struct drm_i915_private *i915);
	90	void intel_timelines_park(struct drm_i915_private *i915);
	91	void intel_timelines_fini(struct drm_i915_private *i915);
	92
	93	#endif

drivers/gpu/drm/i915/gt/intel_timeline_types.hrenamed from drivers/gpu/drm/i915/i915_timeline_types.h+4−4

@@ -16,10 +16,10 @@ · 15 unmodified lines
16		16
17	struct drm_i915_private;	17	struct drm_i915_private;
18	struct i915_vma;	18	struct i915_vma;
19	struct i915_timeline_cacheline;	19	struct intel_timeline_cacheline;
20	struct i915_syncmap;	20	struct i915_syncmap;
21		21
22	struct i915_timeline {	22	struct intel_timeline {
23	u64 fence_context;	23	u64 fence_context;
24	u32 seqno;	24	u32 seqno;
25		25
@@ -30,7 +30,7 @@ struct i915_timeline { · 4 unmodified lines
30	struct i915_vma *hwsp_ggtt;	30	struct i915_vma *hwsp_ggtt;
31	u32 hwsp_offset;	31	u32 hwsp_offset;
32		32
33	struct i915_timeline_cacheline *hwsp_cacheline;	33	struct intel_timeline_cacheline *hwsp_cacheline;
34		34
35	bool has_initial_breadcrumb;	35	bool has_initial_breadcrumb;
36		36
@@ -59,7 +59,7 @@ struct i915_timeline { · 22 unmodified lines
59	struct i915_syncmap *sync;	59	struct i915_syncmap *sync;
60		60
61	struct list_head link;	61	struct list_head link;
62	struct drm_i915_private *i915;	62	struct intel_gt *gt;
63		63
64	struct kref kref;	64	struct kref kref;
65	};	65	};

drivers/gpu/drm/i915/gt/intel_workarounds.c+133−94

@@ -6,6 +6,7 @@ · 5 unmodified lines
6		6
7	#include "i915_drv.h"	7	#include "i915_drv.h"
8	#include "intel_context.h"	8	#include "intel_context.h"
		9	#include "intel_gt.h"
9	#include "intel_workarounds.h"	10	#include "intel_workarounds.h"
10		11
11	/**	12	/**
@@ -49,9 +50,10 @@ · 37 unmodified lines
49	* - Public functions to init or apply the given workaround type.	50	* - Public functions to init or apply the given workaround type.
50	*/	51	*/
51		52
52	static void wa_init_start(struct i915_wa_list wal, const char name)	53	static void wa_init_start(struct i915_wa_list wal, const char name, const char *engine_name)
53	{	54	{
54	wal->name = name;	55	wal->name = name;
		56	wal->engine_name = engine_name;
55	}	57	}
56		58
57	#define WA_LIST_CHUNK (1 << 4)	59	#define WA_LIST_CHUNK (1 << 4)
@@ -73,8 +75,8 @@ static void wa_init_finish(struct i915_wa_list *wal) · 15 unmodified lines
73	if (!wal->count)	75	if (!wal->count)
74	return;	76	return;
75		77
76	DRM_DEBUG_DRIVER("Initialized %u %s workarounds\n",	78	DRM_DEBUG_DRIVER("Initialized %u %s workarounds on %s\n",
77	wal->wa_count, wal->name);	79	wal->wa_count, wal->name, wal->engine_name);
78	}	80	}
79		81
80	static void _wa_add(struct i915_wa_list wal, const struct i915_wa wa)	82	static void _wa_add(struct i915_wa_list wal, const struct i915_wa wa)
@@ -175,19 +177,6 @@ wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 val) · 94 unmodified lines
175	wa_write_masked_or(wal, reg, val, val);	177	wa_write_masked_or(wal, reg, val, val);
176	}	178	}
177		179
178	static void
179	ignore_wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 mask, u32 val)
180	{
181	struct i915_wa wa = {
182	.reg = reg,
183	.mask = mask,
184	.val = val,
185	/* Bonkers HW, skip verifying */
186	};
187
188	_wa_add(wal, &wa);
189	}
190
191	#define WA_SET_BIT_MASKED(addr, mask) \	180	#define WA_SET_BIT_MASKED(addr, mask) \
192	wa_write_masked_or(wal, (addr), (mask), _MASKED_BIT_ENABLE(mask))	181	wa_write_masked_or(wal, (addr), (mask), _MASKED_BIT_ENABLE(mask))
193		182
@@ -530,12 +519,6 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, · 336 unmodified lines
530	{	519	{
531	struct drm_i915_private *i915 = engine->i915;	520	struct drm_i915_private *i915 = engine->i915;
532		521
533	/* WaDisableBankHangMode:icl */
534	wa_write(wal,
535	GEN8_L3CNTLREG,
536	intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) \|
537	GEN8_ERRDETBCTRL);
538
539	/* WaDisableBankHangMode:icl */	522	/* WaDisableBankHangMode:icl */
540	wa_write(wal,	523	wa_write(wal,
541	GEN8_L3CNTLREG,	524	GEN8_L3CNTLREG,
@@ -596,7 +579,7 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, · 54 unmodified lines
596	if (engine->class != RENDER_CLASS)	579	if (engine->class != RENDER_CLASS)
597	return;	580	return;
598		581
599	wa_init_start(wal, name);	582	wa_init_start(wal, name, engine->name);
600		583
601	if (IS_GEN(i915, 11))	584	if (IS_GEN(i915, 11))
602	icl_ctx_workarounds_init(engine, wal);	585	icl_ctx_workarounds_init(engine, wal);
@@ -766,7 +749,10 @@ static void · 163 unmodified lines
766	wa_init_mcr(struct drm_i915_private i915, struct i915_wa_list wal)	749	wa_init_mcr(struct drm_i915_private i915, struct i915_wa_list wal)
767	{	750	{
768	const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;	751	const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
769	u32 mcr_slice_subslice_mask;	752	unsigned int slice, subslice;
		753	u32 l3_en, mcr, mcr_mask;
		754
		755	GEM_BUG_ON(INTEL_GEN(i915) < 10);
770		756
771	/*	757	/*
772	* WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl	758	* WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl
@@ -774,42 +760,7 @@ wa_init_mcr(struct drm_i915_private i915, struct i915_wa_list wal) · 1 unmodified line
774	* the case, we might need to program MCR select to a valid L3Bank	760	* the case, we might need to program MCR select to a valid L3Bank
775	* by default, to make sure we correctly read certain registers	761	* by default, to make sure we correctly read certain registers
776	* later on (in the range 0xB100 - 0xB3FF).	762	* later on (in the range 0xB100 - 0xB3FF).
777	* This might be incompatible with	763	*
778	* WaProgramMgsrForCorrectSliceSpecificMmioReads.
779	* Fortunately, this should not happen in production hardware, so
780	* we only assert that this is the case (instead of implementing
781	* something more complex that requires checking the range of every
782	* MMIO read).
783	*/
784	if (INTEL_GEN(i915) >= 10 &&
785	is_power_of_2(sseu->slice_mask)) {
786	/*
787	* read FUSE3 for enabled L3 Bank IDs, if L3 Bank matches
788	* enabled subslice, no need to redirect MCR packet
789	*/
790	u32 slice = fls(sseu->slice_mask);
791	u32 fuse3 =
792	intel_uncore_read(&i915->uncore, GEN10_MIRROR_FUSE3);
793	u8 ss_mask = sseu->subslice_mask[slice];
794
795	u8 enabled_mask = (ss_mask \| ss_mask >>
796	GEN10_L3BANK_PAIR_COUNT) & GEN10_L3BANK_MASK;
797	u8 disabled_mask = fuse3 & GEN10_L3BANK_MASK;
798
799	/*
800	* Production silicon should have matched L3Bank and
801	* subslice enabled
802	*/
803	WARN_ON((enabled_mask & disabled_mask) != enabled_mask);
804	}
805
806	if (INTEL_GEN(i915) >= 11)
807	mcr_slice_subslice_mask = GEN11_MCR_SLICE_MASK \|
808	GEN11_MCR_SUBSLICE_MASK;
809	else
810	mcr_slice_subslice_mask = GEN8_MCR_SLICE_MASK \|
811	GEN8_MCR_SUBSLICE_MASK;
812	/*
813	* WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl	764	* WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl
814	* Before any MMIO read into slice/subslice specific registers, MCR	765	* Before any MMIO read into slice/subslice specific registers, MCR
815	* packet control register needs to be programmed to point to any	766	* packet control register needs to be programmed to point to any
@@ -819,11 +770,51 @@ wa_init_mcr(struct drm_i915_private i915, struct i915_wa_list wal) · 3 unmodified lines
819	* are consistent across s/ss in almost all cases. In the rare	770	* are consistent across s/ss in almost all cases. In the rare
820	* occasions, such as INSTDONE, where this value is dependent	771	* occasions, such as INSTDONE, where this value is dependent
821	* on s/ss combo, the read should be done with read_subslice_reg.	772	* on s/ss combo, the read should be done with read_subslice_reg.
		773	*
		774	* Since GEN8_MCR_SELECTOR contains dual-purpose bits which select both
		775	* to which subslice, or to which L3 bank, the respective mmio reads
		776	* will go, we have to find a common index which works for both
		777	* accesses.
		778	*
		779	* Case where we cannot find a common index fortunately should not
		780	* happen in production hardware, so we only emit a warning instead of
		781	* implementing something more complex that requires checking the range
		782	* of every MMIO read.
822	*/	783	*/
823	wa_write_masked_or(wal,	784
824	GEN8_MCR_SELECTOR,	785	if (INTEL_GEN(i915) >= 10 && is_power_of_2(sseu->slice_mask)) {
825	mcr_slice_subslice_mask,	786	u32 l3_fuse =
826	intel_calculate_mcr_s_ss_select(i915));	787	intel_uncore_read(&i915->uncore, GEN10_MIRROR_FUSE3) &
		788	GEN10_L3BANK_MASK;
		789
		790	DRM_DEBUG_DRIVER("L3 fuse = %x\n", l3_fuse);
		791	l3_en = ~(l3_fuse << GEN10_L3BANK_PAIR_COUNT \| l3_fuse);
		792	} else {
		793	l3_en = ~0;
		794	}
		795
		796	slice = fls(sseu->slice_mask) - 1;
		797	GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
		798	subslice = fls(l3_en & sseu->subslice_mask[slice]);
		799	if (!subslice) {
		800	DRM_WARN("No common index found between subslice mask %x and L3 bank mask %x!\n",
		801	sseu->subslice_mask[slice], l3_en);
		802	subslice = fls(l3_en);
		803	WARN_ON(!subslice);
		804	}
		805	subslice--;
		806
		807	if (INTEL_GEN(i915) >= 11) {
		808	mcr = GEN11_MCR_SLICE(slice) \| GEN11_MCR_SUBSLICE(subslice);
		809	mcr_mask = GEN11_MCR_SLICE_MASK \| GEN11_MCR_SUBSLICE_MASK;
		810	} else {
		811	mcr = GEN8_MCR_SLICE(slice) \| GEN8_MCR_SUBSLICE(subslice);
		812	mcr_mask = GEN8_MCR_SLICE_MASK \| GEN8_MCR_SUBSLICE_MASK;
		813	}
		814
		815	DRM_DEBUG_DRIVER("MCR slice/subslice = %x\n", mcr);
		816
		817	wa_write_masked_or(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr);
827	}	818	}
828		819
829	static void	820	static void
@@ -926,7 +917,7 @@ void intel_gt_init_workarounds(struct drm_i915_private *i915) · 96 unmodified lines
926	{	917	{
927	struct i915_wa_list *wal = &i915->gt_wa_list;	918	struct i915_wa_list *wal = &i915->gt_wa_list;
928		919
929	wa_init_start(wal, "GT");	920	wa_init_start(wal, "GT", "global");
930	gt_init_workarounds(i915, wal);	921	gt_init_workarounds(i915, wal);
931	wa_init_finish(wal);	922	wa_init_finish(wal);
932	}	923	}
@@ -990,9 +981,9 @@ wa_list_apply(struct intel_uncore uncore, const struct i915_wa_list wal) · 57 unmodified lines
990	spin_unlock_irqrestore(&uncore->lock, flags);	981	spin_unlock_irqrestore(&uncore->lock, flags);
991	}	982	}
992		983
993	void intel_gt_apply_workarounds(struct drm_i915_private *i915)	984	void intel_gt_apply_workarounds(struct intel_gt *gt)
994	{	985	{
995	wa_list_apply(&i915->uncore, &i915->gt_wa_list);	986	wa_list_apply(gt->uncore, &gt->i915->gt_wa_list);
996	}	987	}
997		988
998	static bool wa_list_verify(struct intel_uncore *uncore,	989	static bool wa_list_verify(struct intel_uncore *uncore,
@@ -1011,10 +1002,23 @@ static bool wa_list_verify(struct intel_uncore *uncore, · 12 unmodified lines
1011	return ok;	1002	return ok;
1012	}	1003	}
1013		1004
1014	bool intel_gt_verify_workarounds(struct drm_i915_private *i915,	1005	bool intel_gt_verify_workarounds(struct intel_gt gt, const char from)
1015	const char *from)	1006	{
		1007	return wa_list_verify(gt->uncore, &gt->i915->gt_wa_list, from);
		1008	}
		1009
		1010	static inline bool is_nonpriv_flags_valid(u32 flags)
1016	{	1011	{
1017	return wa_list_verify(&i915->uncore, &i915->gt_wa_list, from);	1012	/* Check only valid flag bits are set */
		1013	if (flags & ~RING_FORCE_TO_NONPRIV_MASK_VALID)
		1014	return false;
		1015
		1016	/* NB: Only 3 out of 4 enum values are valid for access field */
		1017	if ((flags & RING_FORCE_TO_NONPRIV_ACCESS_MASK) ==
		1018	RING_FORCE_TO_NONPRIV_ACCESS_INVALID)
		1019	return false;
		1020
		1021	return true;
1018	}	1022	}
1019		1023
1020	static void	1024	static void
@@ -1027,6 +1031,9 @@ whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags) · 6 unmodified lines
1027	if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS))	1031	if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS))
1028	return;	1032	return;
1029		1033
		1034	if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags)))
		1035	return;
		1036
1030	wa.reg.reg \|= flags;	1037	wa.reg.reg \|= flags;
1031	_wa_add(wal, &wa);	1038	_wa_add(wal, &wa);
1032	}	1039	}
@@ -1034,7 +1041,7 @@ whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags) · 1 unmodified line
1034	static void	1041	static void
1035	whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg)	1042	whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg)
1036	{	1043	{
1037	whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_RW);	1044	whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW);
1038	}	1045	}
1039		1046
1040	static void gen9_whitelist_build(struct i915_wa_list *w)	1047	static void gen9_whitelist_build(struct i915_wa_list *w)
@@ -1115,7 +1122,7 @@ static void cfl_whitelist_build(struct intel_engine_cs *engine) · 74 unmodified lines
1115	* - PS_DEPTH_COUNT_UDW	1122	* - PS_DEPTH_COUNT_UDW
1116	*/	1123	*/
1117	whitelist_reg_ext(w, PS_INVOCATION_COUNT,	1124	whitelist_reg_ext(w, PS_INVOCATION_COUNT,
1118	RING_FORCE_TO_NONPRIV_RD \|	1125	RING_FORCE_TO_NONPRIV_ACCESS_RD \|
1119	RING_FORCE_TO_NONPRIV_RANGE_4);	1126	RING_FORCE_TO_NONPRIV_RANGE_4);
1120	}	1127	}
1121		1128
@@ -1155,20 +1162,20 @@ static void icl_whitelist_build(struct intel_engine_cs *engine) · 33 unmodified lines
1155	* - PS_DEPTH_COUNT_UDW	1162	* - PS_DEPTH_COUNT_UDW
1156	*/	1163	*/
1157	whitelist_reg_ext(w, PS_INVOCATION_COUNT,	1164	whitelist_reg_ext(w, PS_INVOCATION_COUNT,
1158	RING_FORCE_TO_NONPRIV_RD \|	1165	RING_FORCE_TO_NONPRIV_ACCESS_RD \|
1159	RING_FORCE_TO_NONPRIV_RANGE_4);	1166	RING_FORCE_TO_NONPRIV_RANGE_4);
1160	break;	1167	break;
1161		1168
1162	case VIDEO_DECODE_CLASS:	1169	case VIDEO_DECODE_CLASS:
1163	/* hucStatusRegOffset */	1170	/* hucStatusRegOffset */
1164	whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base),	1171	whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base),
1165	RING_FORCE_TO_NONPRIV_RD);	1172	RING_FORCE_TO_NONPRIV_ACCESS_RD);
1166	/* hucUKernelHdrInfoRegOffset */	1173	/* hucUKernelHdrInfoRegOffset */
1167	whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base),	1174	whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base),
1168	RING_FORCE_TO_NONPRIV_RD);	1175	RING_FORCE_TO_NONPRIV_ACCESS_RD);
1169	/* hucStatus2RegOffset */	1176	/* hucStatus2RegOffset */
1170	whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base),	1177	whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base),
1171	RING_FORCE_TO_NONPRIV_RD);	1178	RING_FORCE_TO_NONPRIV_ACCESS_RD);
1172	break;	1179	break;
1173		1180
1174	default:	1181	default:
@@ -1181,7 +1188,7 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine) · 6 unmodified lines
1181	struct drm_i915_private *i915 = engine->i915;	1188	struct drm_i915_private *i915 = engine->i915;
1182	struct i915_wa_list *w = &engine->whitelist;	1189	struct i915_wa_list *w = &engine->whitelist;
1183		1190
1184	wa_init_start(w, "whitelist");	1191	wa_init_start(w, "whitelist", engine->name);
1185		1192
1186	if (IS_GEN(i915, 11))	1193	if (IS_GEN(i915, 11))
1187	icl_whitelist_build(engine);	1194	icl_whitelist_build(engine);
@@ -1240,10 +1247,9 @@ rcs_engine_wa_init(struct intel_engine_cs engine, struct i915_wa_list wal) · 52 unmodified lines
1240	_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE);	1247	_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE);
1241		1248
1242	/* WaPipelineFlushCoherentLines:icl */	1249	/* WaPipelineFlushCoherentLines:icl */
1243	ignore_wa_write_or(wal,	1250	wa_write_or(wal,
1244	GEN8_L3SQCREG4,	1251	GEN8_L3SQCREG4,
1245	GEN8_LQSC_FLUSH_COHERENT_LINES,	1252	GEN8_LQSC_FLUSH_COHERENT_LINES);
1246	GEN8_LQSC_FLUSH_COHERENT_LINES);
1247		1253
1248	/*	1254	/*
1249	* Wa_1405543622:icl	1255	* Wa_1405543622:icl
@@ -1270,10 +1276,9 @@ rcs_engine_wa_init(struct intel_engine_cs engine, struct i915_wa_list wal) · 20 unmodified lines
1270	* Wa_1405733216:icl	1276	* Wa_1405733216:icl
1271	* Formerly known as WaDisableCleanEvicts	1277	* Formerly known as WaDisableCleanEvicts
1272	*/	1278	*/
1273	ignore_wa_write_or(wal,	1279	wa_write_or(wal,
1274	GEN8_L3SQCREG4,	1280	GEN8_L3SQCREG4,
1275	GEN11_LQSC_CLEAN_EVICT_DISABLE,	1281	GEN11_LQSC_CLEAN_EVICT_DISABLE);
1276	GEN11_LQSC_CLEAN_EVICT_DISABLE);
1277		1282
1278	/* WaForwardProgressSoftReset:icl */	1283	/* WaForwardProgressSoftReset:icl */
1279	wa_write_or(wal,	1284	wa_write_or(wal,
@@ -1292,6 +1297,12 @@ rcs_engine_wa_init(struct intel_engine_cs engine, struct i915_wa_list wal) · 12 unmodified lines
1292	wa_write_or(wal,	1297	wa_write_or(wal,
1293	GEN7_SARCHKMD,	1298	GEN7_SARCHKMD,
1294	GEN7_DISABLE_SAMPLER_PREFETCH);	1299	GEN7_DISABLE_SAMPLER_PREFETCH);
		1300
		1301	/* Wa_1409178092:icl */
		1302	wa_write_masked_or(wal,
		1303	GEN11_SCRATCH2,
		1304	GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE,
		1305	0);
1295	}	1306	}
1296		1307
1297	if (IS_GEN_RANGE(i915, 9, 11)) {	1308	if (IS_GEN_RANGE(i915, 9, 11)) {
@@ -1360,7 +1371,7 @@ engine_init_workarounds(struct intel_engine_cs engine, struct i915_wa_list wal · 62 unmodified lines
1360	if (I915_SELFTEST_ONLY(INTEL_GEN(engine->i915) < 8))	1371	if (I915_SELFTEST_ONLY(INTEL_GEN(engine->i915) < 8))
1361	return;	1372	return;
1362		1373
1363	if (engine->id == RCS0)	1374	if (engine->class == RENDER_CLASS)
1364	rcs_engine_wa_init(engine, wal);	1375	rcs_engine_wa_init(engine, wal);
1365	else	1376	else
1366	xcs_engine_wa_init(engine, wal);	1377	xcs_engine_wa_init(engine, wal);
@@ -1370,10 +1381,10 @@ void intel_engine_init_workarounds(struct intel_engine_cs *engine) · 3 unmodified lines
1370	{	1381	{
1371	struct i915_wa_list *wal = &engine->wa_list;	1382	struct i915_wa_list *wal = &engine->wa_list;
1372		1383
1373	if (GEM_WARN_ON(INTEL_GEN(engine->i915) < 8))	1384	if (INTEL_GEN(engine->i915) < 8)
1374	return;	1385	return;
1375		1386
1376	wa_init_start(wal, engine->name);	1387	wa_init_start(wal, "engine", engine->name);
1377	engine_init_workarounds(engine, wal);	1388	engine_init_workarounds(engine, wal);
1378	wa_init_finish(wal);	1389	wa_init_finish(wal);
1379	}	1390	}
@@ -1416,26 +1427,50 @@ err_obj: · 36 unmodified lines
1416	return ERR_PTR(err);	1427	return ERR_PTR(err);
1417	}	1428	}
1418		1429
		1430	static bool mcr_range(struct drm_i915_private *i915, u32 offset)
		1431	{
		1432	/*
		1433	* Registers in this range are affected by the MCR selector
		1434	* which only controls CPU initiated MMIO. Routing does not
		1435	* work for CS access so we cannot verify them on this path.
		1436	*/
		1437	if (INTEL_GEN(i915) >= 8 && (offset >= 0xb100 && offset <= 0xb3ff))
		1438	return true;
		1439
		1440	return false;
		1441	}
		1442
1419	static int	1443	static int
1420	wa_list_srm(struct i915_request *rq,	1444	wa_list_srm(struct i915_request *rq,
1421	const struct i915_wa_list *wal,	1445	const struct i915_wa_list *wal,
1422	struct i915_vma *vma)	1446	struct i915_vma *vma)
1423	{	1447	{
		1448	struct drm_i915_private *i915 = rq->i915;
		1449	unsigned int i, count = 0;
1424	const struct i915_wa *wa;	1450	const struct i915_wa *wa;
1425	unsigned int i;
1426	u32 srm, *cs;	1451	u32 srm, *cs;
1427		1452
1428	srm = MI_STORE_REGISTER_MEM \| MI_SRM_LRM_GLOBAL_GTT;	1453	srm = MI_STORE_REGISTER_MEM \| MI_SRM_LRM_GLOBAL_GTT;
1429	if (INTEL_GEN(rq->i915) >= 8)	1454	if (INTEL_GEN(i915) >= 8)
1430	srm++;	1455	srm++;
1431		1456
1432	cs = intel_ring_begin(rq, 4 * wal->count);	1457	for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
		1458	if (!mcr_range(i915, i915_mmio_reg_offset(wa->reg)))
		1459	count++;
		1460	}
		1461
		1462	cs = intel_ring_begin(rq, 4 * count);
1433	if (IS_ERR(cs))	1463	if (IS_ERR(cs))
1434	return PTR_ERR(cs);	1464	return PTR_ERR(cs);
1435		1465
1436	for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {	1466	for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
		1467	u32 offset = i915_mmio_reg_offset(wa->reg);
		1468
		1469	if (mcr_range(i915, offset))
		1470	continue;
		1471
1437	*cs++ = srm;	1472	*cs++ = srm;
1438	*cs++ = i915_mmio_reg_offset(wa->reg);	1473	*cs++ = offset;
1439	cs++ = i915_ggtt_offset(vma) + sizeof(u32) i;	1474	cs++ = i915_ggtt_offset(vma) + sizeof(u32) i;
1440	*cs++ = 0;	1475	*cs++ = 0;
1441	}	1476	}
@@ -1458,7 +1493,7 @@ static int engine_wa_list_verify(struct intel_context *ce, · 16 unmodified lines
1458	if (!wal->count)	1493	if (!wal->count)
1459	return 0;	1494	return 0;
1460		1495
1461	vma = create_scratch(&ce->engine->i915->ggtt.vm, wal->count);	1496	vma = create_scratch(&ce->engine->gt->ggtt->vm, wal->count);
1462	if (IS_ERR(vma))	1497	if (IS_ERR(vma))
1463	return PTR_ERR(vma);	1498	return PTR_ERR(vma);
1464		1499
@@ -1485,9 +1520,13 @@ static int engine_wa_list_verify(struct intel_context *ce, · 20 unmodified lines
1485	}	1520	}
1486		1521
1487	err = 0;	1522	err = 0;
1488	for (i = 0, wa = wal->list; i < wal->count; i++, wa++)	1523	for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
		1524	if (mcr_range(rq->i915, i915_mmio_reg_offset(wa->reg)))
		1525	continue;
		1526
1489	if (!wa_verify(wa, results[i], wal->name, from))	1527	if (!wa_verify(wa, results[i], wal->name, from))
1490	err = -ENXIO;	1528	err = -ENXIO;
		1529	}
1491		1530
1492	i915_gem_object_unpin_map(vma->obj);	1531	i915_gem_object_unpin_map(vma->obj);
1493		1532

drivers/gpu/drm/i915/gt/intel_workarounds.h+3−3

 struct drm_i915_private;
 struct i915_request;
 struct intel_engine_cs;
+struct intel_gt;
 static inline void intel_wa_list_free(struct i915_wa_list *wal)
 {
 int intel_engine_emit_ctx_wa(struct i915_request *rq);
 void intel_gt_init_workarounds(struct drm_i915_private *i915);
-void intel_gt_apply_workarounds(struct drm_i915_private *i915);
+void intel_gt_apply_workarounds(struct intel_gt *gt);
-bool intel_gt_verify_workarounds(struct drm_i915_private *i915,
+bool intel_gt_verify_workarounds(struct intel_gt *gt, const char *from);
-				 const char *from);
 void intel_engine_init_whitelist(struct intel_engine_cs *engine);
 void intel_engine_apply_whitelist(struct intel_engine_cs *engine);

drivers/gpu/drm/i915/gt/intel_workarounds_types.h+1−0

@@ -20,6 +20,7 @@ struct i915_wa { · 19 unmodified lines
20		20
21	struct i915_wa_list {	21	struct i915_wa_list {
22	const char *name;	22	const char *name;
		23	const char *engine_name;
23	struct i915_wa *list;	24	struct i915_wa *list;
24	unsigned int count;	25	unsigned int count;
25	unsigned int wa_count;	26	unsigned int wa_count;

drivers/gpu/drm/i915/gt/mock_engine.c+8−6

 struct mock_ring {
 	struct intel_ring base;
-	struct i915_timeline timeline;
+	struct intel_timeline timeline;
 };
-static void mock_timeline_pin(struct i915_timeline *tl)
+static void mock_timeline_pin(struct intel_timeline *tl)
 {
 	tl->pin_count++;
 }
-static void mock_timeline_unpin(struct i915_timeline *tl)
+static void mock_timeline_unpin(struct intel_timeline *tl)
 {
 	GEM_BUG_ON(!tl->pin_count);
 	tl->pin_count--;
 	if (!ring)
 		return NULL;
-	if (i915_timeline_init(engine->i915, &ring->timeline, NULL)) {
+	if (intel_timeline_init(&ring->timeline, engine->gt, NULL)) {
 		kfree(ring);
 		return NULL;
 	}
 {
 	struct mock_ring *ring = container_of(base, typeof(*ring), base);
-	i915_timeline_fini(&ring->timeline);
+	intel_timeline_fini(&ring->timeline);
 	kfree(ring);
 }
 	if (ce->ring)
 		mock_ring_free(ce->ring);
+	intel_context_fini(ce);
 	intel_context_free(ce);
 }
 			return -ENOMEM;
 	}
-	ret = intel_context_active_acquire(ce, PIN_HIGH);
+	ret = intel_context_active_acquire(ce);
 	if (ret)
 		return ret;
 	/* minimal engine setup for requests */
 	engine->base.i915 = i915;
+	engine->base.gt = &i915->gt;
 	snprintf(engine->base.name, sizeof(engine->base.name), "%s", name);
 	engine->base.id = id;
 	engine->base.mask = BIT(id);

drivers/gpu/drm/i915/gt/selftest_hangcheck.c+252−259

@@ -25,13 +25,13 @@ · 24 unmodified lines
25	#include <linux/kthread.h>	25	#include <linux/kthread.h>
26		26
27	#include "gem/i915_gem_context.h"	27	#include "gem/i915_gem_context.h"
		28	#include "gt/intel_gt.h"
28	#include "intel_engine_pm.h"	29	#include "intel_engine_pm.h"
29		30
30	#include "i915_selftest.h"	31	#include "i915_selftest.h"
31	#include "selftests/i915_random.h"	32	#include "selftests/i915_random.h"
32	#include "selftests/igt_flush_test.h"	33	#include "selftests/igt_flush_test.h"
33	#include "selftests/igt_reset.h"	34	#include "selftests/igt_reset.h"
34	#include "selftests/igt_wedge_me.h"
35	#include "selftests/igt_atomic.h"	35	#include "selftests/igt_atomic.h"
36		36
37	#include "selftests/mock_drm.h"	37	#include "selftests/mock_drm.h"
@@ -42,7 +42,7 @@ · 4 unmodified lines
42	#define IGT_IDLE_TIMEOUT 50 /* ms; time to wait after flushing between tests */	42	#define IGT_IDLE_TIMEOUT 50 /* ms; time to wait after flushing between tests */
43		43
44	struct hang {	44	struct hang {
45	struct drm_i915_private *i915;	45	struct intel_gt *gt;
46	struct drm_i915_gem_object *hws;	46	struct drm_i915_gem_object *hws;
47	struct drm_i915_gem_object *obj;	47	struct drm_i915_gem_object *obj;
48	struct i915_gem_context *ctx;	48	struct i915_gem_context *ctx;
@@ -50,27 +50,27 @@ struct hang { · 1 unmodified line
50	u32 *batch;	50	u32 *batch;
51	};	51	};
52		52
53	static int hang_init(struct hang h, struct drm_i915_private i915)	53	static int hang_init(struct hang h, struct intel_gt gt)
54	{	54	{
55	void *vaddr;	55	void *vaddr;
56	int err;	56	int err;
57		57
58	memset(h, 0, sizeof(*h));	58	memset(h, 0, sizeof(*h));
59	h->i915 = i915;	59	h->gt = gt;
60		60
61	h->ctx = kernel_context(i915);	61	h->ctx = kernel_context(gt->i915);
62	if (IS_ERR(h->ctx))	62	if (IS_ERR(h->ctx))
63	return PTR_ERR(h->ctx);	63	return PTR_ERR(h->ctx);
64		64
65	GEM_BUG_ON(i915_gem_context_is_bannable(h->ctx));	65	GEM_BUG_ON(i915_gem_context_is_bannable(h->ctx));
66		66
67	h->hws = i915_gem_object_create_internal(i915, PAGE_SIZE);	67	h->hws = i915_gem_object_create_internal(gt->i915, PAGE_SIZE);
68	if (IS_ERR(h->hws)) {	68	if (IS_ERR(h->hws)) {
69	err = PTR_ERR(h->hws);	69	err = PTR_ERR(h->hws);
70	goto err_ctx;	70	goto err_ctx;
71	}	71	}
72		72
73	h->obj = i915_gem_object_create_internal(i915, PAGE_SIZE);	73	h->obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE);
74	if (IS_ERR(h->obj)) {	74	if (IS_ERR(h->obj)) {
75	err = PTR_ERR(h->obj);	75	err = PTR_ERR(h->obj);
76	goto err_hws;	76	goto err_hws;
@@ -85,7 +85,7 @@ static int hang_init(struct hang h, struct drm_i915_private i915) · 8 unmodified lines
85	h->seqno = memset(vaddr, 0xff, PAGE_SIZE);	85	h->seqno = memset(vaddr, 0xff, PAGE_SIZE);
86		86
87	vaddr = i915_gem_object_pin_map(h->obj,	87	vaddr = i915_gem_object_pin_map(h->obj,
88	i915_coherent_map_type(i915));	88	i915_coherent_map_type(gt->i915));
89	if (IS_ERR(vaddr)) {	89	if (IS_ERR(vaddr)) {
90	err = PTR_ERR(vaddr);	90	err = PTR_ERR(vaddr);
91	goto err_unpin_hws;	91	goto err_unpin_hws;
@@ -127,35 +127,31 @@ static int move_to_active(struct i915_vma *vma, · 35 unmodified lines
127	static struct i915_request *	127	static struct i915_request *
128	hang_create_request(struct hang h, struct intel_engine_cs engine)	128	hang_create_request(struct hang h, struct intel_engine_cs engine)
129	{	129	{
130	struct drm_i915_private *i915 = h->i915;	130	struct intel_gt *gt = h->gt;
131	struct i915_address_space *vm = h->ctx->vm ?: &i915->ggtt.vm;	131	struct i915_address_space *vm = h->ctx->vm ?: &engine->gt->ggtt->vm;
		132	struct drm_i915_gem_object *obj;
132	struct i915_request *rq = NULL;	133	struct i915_request *rq = NULL;
133	struct i915_vma hws, vma;	134	struct i915_vma hws, vma;
134	unsigned int flags;	135	unsigned int flags;
		136	void *vaddr;
135	u32 *batch;	137	u32 *batch;
136	int err;	138	int err;
137		139
138	if (i915_gem_object_is_active(h->obj)) {	140	obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE);
139	struct drm_i915_gem_object *obj;	141	if (IS_ERR(obj))
140	void *vaddr;	142	return ERR_CAST(obj);
141
142	obj = i915_gem_object_create_internal(h->i915, PAGE_SIZE);
143	if (IS_ERR(obj))
144	return ERR_CAST(obj);
145		143
146	vaddr = i915_gem_object_pin_map(obj,	144	vaddr = i915_gem_object_pin_map(obj, i915_coherent_map_type(gt->i915));
147	i915_coherent_map_type(h->i915));	145	if (IS_ERR(vaddr)) {
148	if (IS_ERR(vaddr)) {	146	i915_gem_object_put(obj);
149	i915_gem_object_put(obj);	147	return ERR_CAST(vaddr);
150	return ERR_CAST(vaddr);	148	}
151	}
152		149
153	i915_gem_object_unpin_map(h->obj);	150	i915_gem_object_unpin_map(h->obj);
154	i915_gem_object_put(h->obj);	151	i915_gem_object_put(h->obj);
155		152
156	h->obj = obj;	153	h->obj = obj;
157	h->batch = vaddr;	154	h->batch = vaddr;
158	}
159		155
160	vma = i915_vma_instance(h->obj, vm, NULL);	156	vma = i915_vma_instance(h->obj, vm, NULL);
161	if (IS_ERR(vma))	157	if (IS_ERR(vma))
@@ -188,7 +184,7 @@ hang_create_request(struct hang h, struct intel_engine_cs engine) · 26 unmodified lines
188	goto cancel_rq;	184	goto cancel_rq;
189		185
190	batch = h->batch;	186	batch = h->batch;
191	if (INTEL_GEN(i915) >= 8) {	187	if (INTEL_GEN(gt->i915) >= 8) {
192	*batch++ = MI_STORE_DWORD_IMM_GEN4;	188	*batch++ = MI_STORE_DWORD_IMM_GEN4;
193	*batch++ = lower_32_bits(hws_address(hws, rq));	189	*batch++ = lower_32_bits(hws_address(hws, rq));
194	*batch++ = upper_32_bits(hws_address(hws, rq));	190	*batch++ = upper_32_bits(hws_address(hws, rq));
@@ -202,7 +198,7 @@ hang_create_request(struct hang h, struct intel_engine_cs engine) · 7 unmodified lines
202	*batch++ = MI_BATCH_BUFFER_START \| 1 << 8 \| 1;	198	*batch++ = MI_BATCH_BUFFER_START \| 1 << 8 \| 1;
203	*batch++ = lower_32_bits(vma->node.start);	199	*batch++ = lower_32_bits(vma->node.start);
204	*batch++ = upper_32_bits(vma->node.start);	200	*batch++ = upper_32_bits(vma->node.start);
205	} else if (INTEL_GEN(i915) >= 6) {	201	} else if (INTEL_GEN(gt->i915) >= 6) {
206	*batch++ = MI_STORE_DWORD_IMM_GEN4;	202	*batch++ = MI_STORE_DWORD_IMM_GEN4;
207	*batch++ = 0;	203	*batch++ = 0;
208	*batch++ = lower_32_bits(hws_address(hws, rq));	204	*batch++ = lower_32_bits(hws_address(hws, rq));
@@ -215,7 +211,7 @@ hang_create_request(struct hang h, struct intel_engine_cs engine) · 6 unmodified lines
215	*batch++ = MI_ARB_CHECK;	211	*batch++ = MI_ARB_CHECK;
216	*batch++ = MI_BATCH_BUFFER_START \| 1 << 8;	212	*batch++ = MI_BATCH_BUFFER_START \| 1 << 8;
217	*batch++ = lower_32_bits(vma->node.start);	213	*batch++ = lower_32_bits(vma->node.start);
218	} else if (INTEL_GEN(i915) >= 4) {	214	} else if (INTEL_GEN(gt->i915) >= 4) {
219	*batch++ = MI_STORE_DWORD_IMM_GEN4 \| MI_USE_GGTT;	215	*batch++ = MI_STORE_DWORD_IMM_GEN4 \| MI_USE_GGTT;
220	*batch++ = 0;	216	*batch++ = 0;
221	*batch++ = lower_32_bits(hws_address(hws, rq));	217	*batch++ = lower_32_bits(hws_address(hws, rq));
@@ -242,7 +238,7 @@ hang_create_request(struct hang h, struct intel_engine_cs engine) · 20 unmodified lines
242	*batch++ = lower_32_bits(vma->node.start);	238	*batch++ = lower_32_bits(vma->node.start);
243	}	239	}
244	batch++ = MI_BATCH_BUFFER_END; / not reached */	240	batch++ = MI_BATCH_BUFFER_END; / not reached */
245	i915_gem_chipset_flush(h->i915);	241	intel_gt_chipset_flush(engine->gt);
246		242
247	if (rq->engine->emit_init_breadcrumb) {	243	if (rq->engine->emit_init_breadcrumb) {
248	err = rq->engine->emit_init_breadcrumb(rq);	244	err = rq->engine->emit_init_breadcrumb(rq);
@@ -251,7 +247,7 @@ hang_create_request(struct hang h, struct intel_engine_cs engine) · 2 unmodified lines
251	}	247	}
252		248
253	flags = 0;	249	flags = 0;
254	if (INTEL_GEN(vm->i915) <= 5)	250	if (INTEL_GEN(gt->i915) <= 5)
255	flags \|= I915_DISPATCH_SECURE;	251	flags \|= I915_DISPATCH_SECURE;
256		252
257	err = rq->engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, flags);	253	err = rq->engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, flags);
@@ -276,7 +272,7 @@ static u32 hws_seqno(const struct hang h, const struct i915_request rq) · 18 unmodified lines
276	static void hang_fini(struct hang *h)	272	static void hang_fini(struct hang *h)
277	{	273	{
278	*h->batch = MI_BATCH_BUFFER_END;	274	*h->batch = MI_BATCH_BUFFER_END;
279	i915_gem_chipset_flush(h->i915);	275	intel_gt_chipset_flush(h->gt);
280		276
281	i915_gem_object_unpin_map(h->obj);	277	i915_gem_object_unpin_map(h->obj);
282	i915_gem_object_put(h->obj);	278	i915_gem_object_put(h->obj);
@@ -286,7 +282,7 @@ static void hang_fini(struct hang *h) · 3 unmodified lines
286		282
287	kernel_context_close(h->ctx);	283	kernel_context_close(h->ctx);
288		284
289	igt_flush_test(h->i915, I915_WAIT_LOCKED);	285	igt_flush_test(h->gt->i915, I915_WAIT_LOCKED);
290	}	286	}
291		287
292	static bool wait_until_running(struct hang h, struct i915_request rq)	288	static bool wait_until_running(struct hang h, struct i915_request rq)
@@ -301,7 +297,7 @@ static bool wait_until_running(struct hang h, struct i915_request rq) · 8 unmodified lines
301		297
302	static int igt_hang_sanitycheck(void *arg)	298	static int igt_hang_sanitycheck(void *arg)
303	{	299	{
304	struct drm_i915_private *i915 = arg;	300	struct intel_gt *gt = arg;
305	struct i915_request *rq;	301	struct i915_request *rq;
306	struct intel_engine_cs *engine;	302	struct intel_engine_cs *engine;
307	enum intel_engine_id id;	303	enum intel_engine_id id;
@@ -310,13 +306,13 @@ static int igt_hang_sanitycheck(void *arg) · 2 unmodified lines
310		306
311	/* Basic check that we can execute our hanging batch */	307	/* Basic check that we can execute our hanging batch */
312		308
313	mutex_lock(&i915->drm.struct_mutex);	309	mutex_lock(&gt->i915->drm.struct_mutex);
314	err = hang_init(&h, i915);	310	err = hang_init(&h, gt);
315	if (err)	311	if (err)
316	goto unlock;	312	goto unlock;
317		313
318	for_each_engine(engine, i915, id) {	314	for_each_engine(engine, gt->i915, id) {
319	struct igt_wedge_me w;	315	struct intel_wedge_me w;
320	long timeout;	316	long timeout;
321		317
322	if (!intel_engine_can_store_dword(engine))	318	if (!intel_engine_can_store_dword(engine))
@@ -333,15 +329,15 @@ static int igt_hang_sanitycheck(void *arg) · 10 unmodified lines
333	i915_request_get(rq);	329	i915_request_get(rq);
334		330
335	*h.batch = MI_BATCH_BUFFER_END;	331	*h.batch = MI_BATCH_BUFFER_END;
336	i915_gem_chipset_flush(i915);	332	intel_gt_chipset_flush(engine->gt);
337		333
338	i915_request_add(rq);	334	i915_request_add(rq);
339		335
340	timeout = 0;	336	timeout = 0;
341	igt_wedge_on_timeout(&w, i915, HZ / 10 /* 100ms timeout*/)	337	intel_wedge_on_timeout(&w, gt, HZ / 10 /* 100ms */)
342	timeout = i915_request_wait(rq, 0,	338	timeout = i915_request_wait(rq, 0,
343	MAX_SCHEDULE_TIMEOUT);	339	MAX_SCHEDULE_TIMEOUT);
344	if (i915_reset_failed(i915))	340	if (intel_gt_is_wedged(gt))
345	timeout = -EIO;	341	timeout = -EIO;
346		342
347	i915_request_put(rq);	343	i915_request_put(rq);
@@ -357,7 +353,7 @@ static int igt_hang_sanitycheck(void *arg) · 9 unmodified lines
357	fini:	353	fini:
358	hang_fini(&h);	354	hang_fini(&h);
359	unlock:	355	unlock:
360	mutex_unlock(&i915->drm.struct_mutex);	356	mutex_unlock(&gt->i915->drm.struct_mutex);
361	return err;	357	return err;
362	}	358	}
363		359
@@ -368,37 +364,37 @@ static bool wait_for_idle(struct intel_engine_cs *engine) · 4 unmodified lines
368		364
369	static int igt_reset_nop(void *arg)	365	static int igt_reset_nop(void *arg)
370	{	366	{
371	struct drm_i915_private *i915 = arg;	367	struct intel_gt *gt = arg;
		368	struct i915_gpu_error *global = &gt->i915->gpu_error;
372	struct intel_engine_cs *engine;	369	struct intel_engine_cs *engine;
373	struct i915_gem_context *ctx;	370	struct i915_gem_context *ctx;
374	unsigned int reset_count, count;	371	unsigned int reset_count, count;
375	enum intel_engine_id id;	372	enum intel_engine_id id;
376	intel_wakeref_t wakeref;
377	struct drm_file *file;	373	struct drm_file *file;
378	IGT_TIMEOUT(end_time);	374	IGT_TIMEOUT(end_time);
379	int err = 0;	375	int err = 0;
380		376
381	/* Check that we can reset during non-user portions of requests */	377	/* Check that we can reset during non-user portions of requests */
382		378
383	file = mock_file(i915);	379	file = mock_file(gt->i915);
384	if (IS_ERR(file))	380	if (IS_ERR(file))
385	return PTR_ERR(file);	381	return PTR_ERR(file);
386		382
387	mutex_lock(&i915->drm.struct_mutex);	383	mutex_lock(&gt->i915->drm.struct_mutex);
388	ctx = live_context(i915, file);	384	ctx = live_context(gt->i915, file);
389	mutex_unlock(&i915->drm.struct_mutex);	385	mutex_unlock(&gt->i915->drm.struct_mutex);
390	if (IS_ERR(ctx)) {	386	if (IS_ERR(ctx)) {
391	err = PTR_ERR(ctx);	387	err = PTR_ERR(ctx);
392	goto out;	388	goto out;
393	}	389	}
394		390
395	i915_gem_context_clear_bannable(ctx);	391	i915_gem_context_clear_bannable(ctx);
396	wakeref = intel_runtime_pm_get(&i915->runtime_pm);	392	reset_count = i915_reset_count(global);
397	reset_count = i915_reset_count(&i915->gpu_error);
398	count = 0;	393	count = 0;
399	do {	394	do {
400	mutex_lock(&i915->drm.struct_mutex);	395	mutex_lock(&gt->i915->drm.struct_mutex);
401	for_each_engine(engine, i915, id) {	396
		397	for_each_engine(engine, gt->i915, id) {
402	int i;	398	int i;
403		399
404	for (i = 0; i < 16; i++) {	400	for (i = 0; i < 16; i++) {
@@ -413,82 +409,78 @@ static int igt_reset_nop(void *arg) · 8 unmodified lines
413	i915_request_add(rq);	409	i915_request_add(rq);
414	}	410	}
415	}	411	}
416	mutex_unlock(&i915->drm.struct_mutex);
417		412
418	igt_global_reset_lock(i915);	413	igt_global_reset_lock(gt);
419	i915_reset(i915, ALL_ENGINES, NULL);	414	intel_gt_reset(gt, ALL_ENGINES, NULL);
420	igt_global_reset_unlock(i915);	415	igt_global_reset_unlock(gt);
421	if (i915_reset_failed(i915)) {	416
		417	mutex_unlock(&gt->i915->drm.struct_mutex);
		418	if (intel_gt_is_wedged(gt)) {
422	err = -EIO;	419	err = -EIO;
423	break;	420	break;
424	}	421	}
425		422
426	if (i915_reset_count(&i915->gpu_error) !=	423	if (i915_reset_count(global) != reset_count + ++count) {
427	reset_count + ++count) {
428	pr_err("Full GPU reset not recorded!\n");	424	pr_err("Full GPU reset not recorded!\n");
429	err = -EINVAL;	425	err = -EINVAL;
430	break;	426	break;
431	}	427	}
432		428
433	err = igt_flush_test(i915, 0);	429	err = igt_flush_test(gt->i915, 0);
434	if (err)	430	if (err)
435	break;	431	break;
436	} while (time_before(jiffies, end_time));	432	} while (time_before(jiffies, end_time));
437	pr_info("%s: %d resets\n", __func__, count);	433	pr_info("%s: %d resets\n", __func__, count);
438		434
439	mutex_lock(&i915->drm.struct_mutex);	435	mutex_lock(&gt->i915->drm.struct_mutex);
440	err = igt_flush_test(i915, I915_WAIT_LOCKED);	436	err = igt_flush_test(gt->i915, I915_WAIT_LOCKED);
441	mutex_unlock(&i915->drm.struct_mutex);	437	mutex_unlock(&gt->i915->drm.struct_mutex);
442
443	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
444		438
445	out:	439	out:
446	mock_file_free(i915, file);	440	mock_file_free(gt->i915, file);
447	if (i915_reset_failed(i915))	441	if (intel_gt_is_wedged(gt))
448	err = -EIO;	442	err = -EIO;
449	return err;	443	return err;
450	}	444	}
451		445
452	static int igt_reset_nop_engine(void *arg)	446	static int igt_reset_nop_engine(void *arg)
453	{	447	{
454	struct drm_i915_private *i915 = arg;	448	struct intel_gt *gt = arg;
		449	struct i915_gpu_error *global = &gt->i915->gpu_error;
455	struct intel_engine_cs *engine;	450	struct intel_engine_cs *engine;
456	struct i915_gem_context *ctx;	451	struct i915_gem_context *ctx;
457	enum intel_engine_id id;	452	enum intel_engine_id id;
458	intel_wakeref_t wakeref;
459	struct drm_file *file;	453	struct drm_file *file;
460	int err = 0;	454	int err = 0;
461		455
462	/* Check that we can engine-reset during non-user portions */	456	/* Check that we can engine-reset during non-user portions */
463		457
464	if (!intel_has_reset_engine(i915))	458	if (!intel_has_reset_engine(gt->i915))
465	return 0;	459	return 0;
466		460
467	file = mock_file(i915);	461	file = mock_file(gt->i915);
468	if (IS_ERR(file))	462	if (IS_ERR(file))
469	return PTR_ERR(file);	463	return PTR_ERR(file);
470		464
471	mutex_lock(&i915->drm.struct_mutex);	465	mutex_lock(&gt->i915->drm.struct_mutex);
472	ctx = live_context(i915, file);	466	ctx = live_context(gt->i915, file);
473	mutex_unlock(&i915->drm.struct_mutex);	467	mutex_unlock(&gt->i915->drm.struct_mutex);
474	if (IS_ERR(ctx)) {	468	if (IS_ERR(ctx)) {
475	err = PTR_ERR(ctx);	469	err = PTR_ERR(ctx);
476	goto out;	470	goto out;
477	}	471	}
478		472
479	i915_gem_context_clear_bannable(ctx);	473	i915_gem_context_clear_bannable(ctx);
480	wakeref = intel_runtime_pm_get(&i915->runtime_pm);	474	for_each_engine(engine, gt->i915, id) {
481	for_each_engine(engine, i915, id) {
482	unsigned int reset_count, reset_engine_count;	475	unsigned int reset_count, reset_engine_count;
483	unsigned int count;	476	unsigned int count;
484	IGT_TIMEOUT(end_time);	477	IGT_TIMEOUT(end_time);
485		478
486	reset_count = i915_reset_count(&i915->gpu_error);	479	reset_count = i915_reset_count(global);
487	reset_engine_count = i915_reset_engine_count(&i915->gpu_error,	480	reset_engine_count = i915_reset_engine_count(global, engine);
488	engine);
489	count = 0;	481	count = 0;
490		482
491	set_bit(I915_RESET_ENGINE + id, &i915->gpu_error.flags);	483	set_bit(I915_RESET_ENGINE + id, &gt->reset.flags);
492	do {	484	do {
493	int i;	485	int i;
494		486
@@ -499,7 +491,7 @@ static int igt_reset_nop_engine(void *arg) · 4 unmodified lines
499	break;	491	break;
500	}	492	}
501		493
502	mutex_lock(&i915->drm.struct_mutex);	494	mutex_lock(&gt->i915->drm.struct_mutex);
503	for (i = 0; i < 16; i++) {	495	for (i = 0; i < 16; i++) {
504	struct i915_request *rq;	496	struct i915_request *rq;
505		497
@@ -511,21 +503,20 @@ static int igt_reset_nop_engine(void *arg) · 5 unmodified lines
511		503
512	i915_request_add(rq);	504	i915_request_add(rq);
513	}	505	}
514	mutex_unlock(&i915->drm.struct_mutex);	506	err = intel_engine_reset(engine, NULL);
515		507	mutex_unlock(&gt->i915->drm.struct_mutex);
516	err = i915_reset_engine(engine, NULL);
517	if (err) {	508	if (err) {
518	pr_err("i915_reset_engine failed\n");	509	pr_err("i915_reset_engine failed\n");
519	break;	510	break;
520	}	511	}
521		512
522	if (i915_reset_count(&i915->gpu_error) != reset_count) {	513	if (i915_reset_count(global) != reset_count) {
523	pr_err("Full GPU reset recorded! (engine reset expected)\n");	514	pr_err("Full GPU reset recorded! (engine reset expected)\n");
524	err = -EINVAL;	515	err = -EINVAL;
525	break;	516	break;
526	}	517	}
527		518
528	if (i915_reset_engine_count(&i915->gpu_error, engine) !=	519	if (i915_reset_engine_count(global, engine) !=
529	reset_engine_count + ++count) {	520	reset_engine_count + ++count) {
530	pr_err("%s engine reset not recorded!\n",	521	pr_err("%s engine reset not recorded!\n",
531	engine->name);	522	engine->name);
@@ -533,31 +524,31 @@ static int igt_reset_nop_engine(void *arg) · 1 unmodified line
533	break;	524	break;
534	}	525	}
535	} while (time_before(jiffies, end_time));	526	} while (time_before(jiffies, end_time));
536	clear_bit(I915_RESET_ENGINE + id, &i915->gpu_error.flags);	527	clear_bit(I915_RESET_ENGINE + id, &gt->reset.flags);
537	pr_info("%s(%s): %d resets\n", __func__, engine->name, count);	528	pr_info("%s(%s): %d resets\n", __func__, engine->name, count);
538		529
539	if (err)	530	if (err)
540	break;	531	break;
541		532
542	err = igt_flush_test(i915, 0);	533	err = igt_flush_test(gt->i915, 0);
543	if (err)	534	if (err)
544	break;	535	break;
545	}	536	}
546		537
547	mutex_lock(&i915->drm.struct_mutex);	538	mutex_lock(&gt->i915->drm.struct_mutex);
548	err = igt_flush_test(i915, I915_WAIT_LOCKED);	539	err = igt_flush_test(gt->i915, I915_WAIT_LOCKED);
549	mutex_unlock(&i915->drm.struct_mutex);	540	mutex_unlock(&gt->i915->drm.struct_mutex);
550		541
551	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
552	out:	542	out:
553	mock_file_free(i915, file);	543	mock_file_free(gt->i915, file);
554	if (i915_reset_failed(i915))	544	if (intel_gt_is_wedged(gt))
555	err = -EIO;	545	err = -EIO;
556	return err;	546	return err;
557	}	547	}
558		548
559	static int __igt_reset_engine(struct drm_i915_private *i915, bool active)	549	static int __igt_reset_engine(struct intel_gt *gt, bool active)
560	{	550	{
		551	struct i915_gpu_error *global = &gt->i915->gpu_error;
561	struct intel_engine_cs *engine;	552	struct intel_engine_cs *engine;
562	enum intel_engine_id id;	553	enum intel_engine_id id;
563	struct hang h;	554	struct hang h;
@@ -565,18 +556,18 @@ static int __igt_reset_engine(struct drm_i915_private *i915, bool active) · 1 unmodified line
565		556
566	/* Check that we can issue an engine reset on an idle engine (no-op) */	557	/* Check that we can issue an engine reset on an idle engine (no-op) */
567		558
568	if (!intel_has_reset_engine(i915))	559	if (!intel_has_reset_engine(gt->i915))
569	return 0;	560	return 0;
570		561
571	if (active) {	562	if (active) {
572	mutex_lock(&i915->drm.struct_mutex);	563	mutex_lock(&gt->i915->drm.struct_mutex);
573	err = hang_init(&h, i915);	564	err = hang_init(&h, gt);
574	mutex_unlock(&i915->drm.struct_mutex);	565	mutex_unlock(&gt->i915->drm.struct_mutex);
575	if (err)	566	if (err)
576	return err;	567	return err;
577	}	568	}
578		569
579	for_each_engine(engine, i915, id) {	570	for_each_engine(engine, gt->i915, id) {
580	unsigned int reset_count, reset_engine_count;	571	unsigned int reset_count, reset_engine_count;
581	IGT_TIMEOUT(end_time);	572	IGT_TIMEOUT(end_time);
582		573
@@ -590,30 +581,29 @@ static int __igt_reset_engine(struct drm_i915_private *i915, bool active) · 7 unmodified lines
590	break;	581	break;
591	}	582	}
592		583
593	reset_count = i915_reset_count(&i915->gpu_error);	584	reset_count = i915_reset_count(global);
594	reset_engine_count = i915_reset_engine_count(&i915->gpu_error,	585	reset_engine_count = i915_reset_engine_count(global, engine);
595	engine);
596		586
597	intel_engine_pm_get(engine);	587	intel_engine_pm_get(engine);
598	set_bit(I915_RESET_ENGINE + id, &i915->gpu_error.flags);	588	set_bit(I915_RESET_ENGINE + id, &gt->reset.flags);
599	do {	589	do {
600	if (active) {	590	if (active) {
601	struct i915_request *rq;	591	struct i915_request *rq;
602		592
603	mutex_lock(&i915->drm.struct_mutex);	593	mutex_lock(&gt->i915->drm.struct_mutex);
604	rq = hang_create_request(&h, engine);	594	rq = hang_create_request(&h, engine);
605	if (IS_ERR(rq)) {	595	if (IS_ERR(rq)) {
606	err = PTR_ERR(rq);	596	err = PTR_ERR(rq);
607	mutex_unlock(&i915->drm.struct_mutex);	597	mutex_unlock(&gt->i915->drm.struct_mutex);
608	break;	598	break;
609	}	599	}
610		600
611	i915_request_get(rq);	601	i915_request_get(rq);
612	i915_request_add(rq);	602	i915_request_add(rq);
613	mutex_unlock(&i915->drm.struct_mutex);	603	mutex_unlock(&gt->i915->drm.struct_mutex);
614		604
615	if (!wait_until_running(&h, rq)) {	605	if (!wait_until_running(&h, rq)) {
616	struct drm_printer p = drm_info_printer(i915->drm.dev);	606	struct drm_printer p = drm_info_printer(gt->i915->drm.dev);
617		607
618	pr_err("%s: Failed to start request %llx, at %x\n",	608	pr_err("%s: Failed to start request %llx, at %x\n",
619	__func__, rq->fence.seqno, hws_seqno(&h, rq));	609	__func__, rq->fence.seqno, hws_seqno(&h, rq));
@@ -628,19 +618,19 @@ static int __igt_reset_engine(struct drm_i915_private *i915, bool active) · 8 unmodified lines
628	i915_request_put(rq);	618	i915_request_put(rq);
629	}	619	}
630		620
631	err = i915_reset_engine(engine, NULL);	621	err = intel_engine_reset(engine, NULL);
632	if (err) {	622	if (err) {
633	pr_err("i915_reset_engine failed\n");	623	pr_err("i915_reset_engine failed\n");
634	break;	624	break;
635	}	625	}
636		626
637	if (i915_reset_count(&i915->gpu_error) != reset_count) {	627	if (i915_reset_count(global) != reset_count) {
638	pr_err("Full GPU reset recorded! (engine reset expected)\n");	628	pr_err("Full GPU reset recorded! (engine reset expected)\n");
639	err = -EINVAL;	629	err = -EINVAL;
640	break;	630	break;
641	}	631	}
642		632
643	if (i915_reset_engine_count(&i915->gpu_error, engine) !=	633	if (i915_reset_engine_count(global, engine) !=
644	++reset_engine_count) {	634	++reset_engine_count) {
645	pr_err("%s engine reset not recorded!\n",	635	pr_err("%s engine reset not recorded!\n",
646	engine->name);	636	engine->name);
@@ -648,24 +638,24 @@ static int __igt_reset_engine(struct drm_i915_private *i915, bool active) · 1 unmodified line
648	break;	638	break;
649	}	639	}
650	} while (time_before(jiffies, end_time));	640	} while (time_before(jiffies, end_time));
651	clear_bit(I915_RESET_ENGINE + id, &i915->gpu_error.flags);	641	clear_bit(I915_RESET_ENGINE + id, &gt->reset.flags);
652	intel_engine_pm_put(engine);	642	intel_engine_pm_put(engine);
653		643
654	if (err)	644	if (err)
655	break;	645	break;
656		646
657	err = igt_flush_test(i915, 0);	647	err = igt_flush_test(gt->i915, 0);
658	if (err)	648	if (err)
659	break;	649	break;
660	}	650	}
661		651
662	if (i915_reset_failed(i915))	652	if (intel_gt_is_wedged(gt))
663	err = -EIO;	653	err = -EIO;
664		654
665	if (active) {	655	if (active) {
666	mutex_lock(&i915->drm.struct_mutex);	656	mutex_lock(&gt->i915->drm.struct_mutex);
667	hang_fini(&h);	657	hang_fini(&h);
668	mutex_unlock(&i915->drm.struct_mutex);	658	mutex_unlock(&gt->i915->drm.struct_mutex);
669	}	659	}
670		660
671	return err;	661	return err;
@@ -707,7 +697,7 @@ static int active_request_put(struct i915_request *rq) · 35 unmodified lines
707	rq->fence.seqno);	697	rq->fence.seqno);
708	GEM_TRACE_DUMP();	698	GEM_TRACE_DUMP();
709		699
710	i915_gem_set_wedged(rq->i915);	700	intel_gt_set_wedged(rq->engine->gt);
711	err = -EIO;	701	err = -EIO;
712	}	702	}
713		703
@@ -784,10 +774,11 @@ err_file: · 70 unmodified lines
784	return err;	774	return err;
785	}	775	}
786		776
787	static int __igt_reset_engines(struct drm_i915_private *i915,	777	static int __igt_reset_engines(struct intel_gt *gt,
788	const char *test_name,	778	const char *test_name,
789	unsigned int flags)	779	unsigned int flags)
790	{	780	{
		781	struct i915_gpu_error *global = &gt->i915->gpu_error;
791	struct intel_engine_cs engine, other;	782	struct intel_engine_cs engine, other;
792	enum intel_engine_id id, tmp;	783	enum intel_engine_id id, tmp;
793	struct hang h;	784	struct hang h;
@@ -797,13 +788,13 @@ static int __igt_reset_engines(struct drm_i915_private *i915, · 3 unmodified lines
797	* with any other engine.	788	* with any other engine.
798	*/	789	*/
799		790
800	if (!intel_has_reset_engine(i915))	791	if (!intel_has_reset_engine(gt->i915))
801	return 0;	792	return 0;
802		793
803	if (flags & TEST_ACTIVE) {	794	if (flags & TEST_ACTIVE) {
804	mutex_lock(&i915->drm.struct_mutex);	795	mutex_lock(&gt->i915->drm.struct_mutex);
805	err = hang_init(&h, i915);	796	err = hang_init(&h, gt);
806	mutex_unlock(&i915->drm.struct_mutex);	797	mutex_unlock(&gt->i915->drm.struct_mutex);
807	if (err)	798	if (err)
808	return err;	799	return err;
809		800
@@ -811,9 +802,9 @@ static int __igt_reset_engines(struct drm_i915_private *i915, · 1 unmodified line
811	h.ctx->sched.priority = 1024;	802	h.ctx->sched.priority = 1024;
812	}	803	}
813		804
814	for_each_engine(engine, i915, id) {	805	for_each_engine(engine, gt->i915, id) {
815	struct active_engine threads[I915_NUM_ENGINES] = {};	806	struct active_engine threads[I915_NUM_ENGINES] = {};
816	unsigned long global = i915_reset_count(&i915->gpu_error);	807	unsigned long device = i915_reset_count(global);
817	unsigned long count = 0, reported;	808	unsigned long count = 0, reported;
818	IGT_TIMEOUT(end_time);	809	IGT_TIMEOUT(end_time);
819		810
@@ -829,12 +820,11 @@ static int __igt_reset_engines(struct drm_i915_private *i915, · 9 unmodified lines
829	}	820	}
830		821
831	memset(threads, 0, sizeof(threads));	822	memset(threads, 0, sizeof(threads));
832	for_each_engine(other, i915, tmp) {	823	for_each_engine(other, gt->i915, tmp) {
833	struct task_struct *tsk;	824	struct task_struct *tsk;
834		825
835	threads[tmp].resets =	826	threads[tmp].resets =
836	i915_reset_engine_count(&i915->gpu_error,	827	i915_reset_engine_count(global, other);
837	other);
838		828
839	if (!(flags & TEST_OTHERS))	829	if (!(flags & TEST_OTHERS))
840	continue;	830	continue;
@@ -857,25 +847,25 @@ static int __igt_reset_engines(struct drm_i915_private *i915, · 16 unmodified lines
857	}	847	}
858		848
859	intel_engine_pm_get(engine);	849	intel_engine_pm_get(engine);
860	set_bit(I915_RESET_ENGINE + id, &i915->gpu_error.flags);	850	set_bit(I915_RESET_ENGINE + id, &gt->reset.flags);
861	do {	851	do {
862	struct i915_request *rq = NULL;	852	struct i915_request *rq = NULL;
863		853
864	if (flags & TEST_ACTIVE) {	854	if (flags & TEST_ACTIVE) {
865	mutex_lock(&i915->drm.struct_mutex);	855	mutex_lock(&gt->i915->drm.struct_mutex);
866	rq = hang_create_request(&h, engine);	856	rq = hang_create_request(&h, engine);
867	if (IS_ERR(rq)) {	857	if (IS_ERR(rq)) {
868	err = PTR_ERR(rq);	858	err = PTR_ERR(rq);
869	mutex_unlock(&i915->drm.struct_mutex);	859	mutex_unlock(&gt->i915->drm.struct_mutex);
870	break;	860	break;
871	}	861	}
872		862
873	i915_request_get(rq);	863	i915_request_get(rq);
874	i915_request_add(rq);	864	i915_request_add(rq);
875	mutex_unlock(&i915->drm.struct_mutex);	865	mutex_unlock(&gt->i915->drm.struct_mutex);
876		866
877	if (!wait_until_running(&h, rq)) {	867	if (!wait_until_running(&h, rq)) {
878	struct drm_printer p = drm_info_printer(i915->drm.dev);	868	struct drm_printer p = drm_info_printer(gt->i915->drm.dev);
879		869
880	pr_err("%s: Failed to start request %llx, at %x\n",	870	pr_err("%s: Failed to start request %llx, at %x\n",
881	__func__, rq->fence.seqno, hws_seqno(&h, rq));	871	__func__, rq->fence.seqno, hws_seqno(&h, rq));
@@ -888,7 +878,7 @@ static int __igt_reset_engines(struct drm_i915_private *i915, · 6 unmodified lines
888	}	878	}
889	}	879	}
890		880
891	err = i915_reset_engine(engine, NULL);	881	err = intel_engine_reset(engine, NULL);
892	if (err) {	882	if (err) {
893	pr_err("i915_reset_engine(%s:%s): failed, err=%d\n",	883	pr_err("i915_reset_engine(%s:%s): failed, err=%d\n",
894	engine->name, test_name, err);	884	engine->name, test_name, err);
@@ -900,7 +890,7 @@ static int __igt_reset_engines(struct drm_i915_private *i915, · 5 unmodified lines
900	if (rq) {	890	if (rq) {
901	if (i915_request_wait(rq, 0, HZ / 5) < 0) {	891	if (i915_request_wait(rq, 0, HZ / 5) < 0) {
902	struct drm_printer p =	892	struct drm_printer p =
903	drm_info_printer(i915->drm.dev);	893	drm_info_printer(gt->i915->drm.dev);
904		894
905	pr_err("i915_reset_engine(%s:%s):"	895	pr_err("i915_reset_engine(%s:%s):"
906	" failed to complete request after reset\n",	896	" failed to complete request after reset\n",
@@ -910,7 +900,7 @@ static int __igt_reset_engines(struct drm_i915_private *i915, · 3 unmodified lines
910	i915_request_put(rq);	900	i915_request_put(rq);
911		901
912	GEM_TRACE_DUMP();	902	GEM_TRACE_DUMP();
913	i915_gem_set_wedged(i915);	903	intel_gt_set_wedged(gt);
914	err = -EIO;	904	err = -EIO;
915	break;	905	break;
916	}	906	}
@@ -920,7 +910,7 @@ static int __igt_reset_engines(struct drm_i915_private *i915, · 3 unmodified lines
920		910
921	if (!(flags & TEST_SELF) && !wait_for_idle(engine)) {	911	if (!(flags & TEST_SELF) && !wait_for_idle(engine)) {
922	struct drm_printer p =	912	struct drm_printer p =
923	drm_info_printer(i915->drm.dev);	913	drm_info_printer(gt->i915->drm.dev);
924		914
925	pr_err("i915_reset_engine(%s:%s):"	915	pr_err("i915_reset_engine(%s:%s):"
926	" failed to idle after reset\n",	916	" failed to idle after reset\n",
@@ -932,12 +922,12 @@ static int __igt_reset_engines(struct drm_i915_private *i915, · 5 unmodified lines
932	break;	922	break;
933	}	923	}
934	} while (time_before(jiffies, end_time));	924	} while (time_before(jiffies, end_time));
935	clear_bit(I915_RESET_ENGINE + id, &i915->gpu_error.flags);	925	clear_bit(I915_RESET_ENGINE + id, &gt->reset.flags);
936	intel_engine_pm_put(engine);	926	intel_engine_pm_put(engine);
937	pr_info("i915_reset_engine(%s:%s): %lu resets\n",	927	pr_info("i915_reset_engine(%s:%s): %lu resets\n",
938	engine->name, test_name, count);	928	engine->name, test_name, count);
939		929
940	reported = i915_reset_engine_count(&i915->gpu_error, engine);	930	reported = i915_reset_engine_count(global, engine);
941	reported -= threads[engine->id].resets;	931	reported -= threads[engine->id].resets;
942	if (reported != count) {	932	if (reported != count) {
943	pr_err("i915_reset_engine(%s:%s): reset %lu times, but reported %lu\n",	933	pr_err("i915_reset_engine(%s:%s): reset %lu times, but reported %lu\n",
@@ -947,7 +937,7 @@ static int __igt_reset_engines(struct drm_i915_private *i915, · 3 unmodified lines
947	}	937	}
948		938
949	unwind:	939	unwind:
950	for_each_engine(other, i915, tmp) {	940	for_each_engine(other, gt->i915, tmp) {
951	int ret;	941	int ret;
952		942
953	if (!threads[tmp].task)	943	if (!threads[tmp].task)
@@ -962,22 +952,21 @@ unwind: · 8 unmodified lines
962	}	952	}
963	put_task_struct(threads[tmp].task);	953	put_task_struct(threads[tmp].task);
964		954
965	if (other != engine &&	955	if (other->uabi_class != engine->uabi_class &&
966	threads[tmp].resets !=	956	threads[tmp].resets !=
967	i915_reset_engine_count(&i915->gpu_error, other)) {	957	i915_reset_engine_count(global, other)) {
968	pr_err("Innocent engine %s was reset (count=%ld)\n",	958	pr_err("Innocent engine %s was reset (count=%ld)\n",
969	other->name,	959	other->name,
970	i915_reset_engine_count(&i915->gpu_error,	960	i915_reset_engine_count(global, other) -
971	other) -
972	threads[tmp].resets);	961	threads[tmp].resets);
973	if (!err)	962	if (!err)
974	err = -EINVAL;	963	err = -EINVAL;
975	}	964	}
976	}	965	}
977		966
978	if (global != i915_reset_count(&i915->gpu_error)) {	967	if (device != i915_reset_count(global)) {
979	pr_err("Global reset (count=%ld)!\n",	968	pr_err("Global reset (count=%ld)!\n",
980	i915_reset_count(&i915->gpu_error) - global);	969	i915_reset_count(global) - device);
981	if (!err)	970	if (!err)
982	err = -EINVAL;	971	err = -EINVAL;
983	}	972	}
@@ -985,20 +974,20 @@ unwind: · 1 unmodified line
985	if (err)	974	if (err)
986	break;	975	break;
987		976
988	mutex_lock(&i915->drm.struct_mutex);	977	mutex_lock(&gt->i915->drm.struct_mutex);
989	err = igt_flush_test(i915, I915_WAIT_LOCKED);	978	err = igt_flush_test(gt->i915, I915_WAIT_LOCKED);
990	mutex_unlock(&i915->drm.struct_mutex);	979	mutex_unlock(&gt->i915->drm.struct_mutex);
991	if (err)	980	if (err)
992	break;	981	break;
993	}	982	}
994		983
995	if (i915_reset_failed(i915))	984	if (intel_gt_is_wedged(gt))
996	err = -EIO;	985	err = -EIO;
997		986
998	if (flags & TEST_ACTIVE) {	987	if (flags & TEST_ACTIVE) {
999	mutex_lock(&i915->drm.struct_mutex);	988	mutex_lock(&gt->i915->drm.struct_mutex);
1000	hang_fini(&h);	989	hang_fini(&h);
1001	mutex_unlock(&i915->drm.struct_mutex);	990	mutex_unlock(&gt->i915->drm.struct_mutex);
1002	}	991	}
1003		992
1004	return err;	993	return err;
@@ -1024,13 +1013,13 @@ static int igt_reset_engines(void *arg) · 19 unmodified lines
1024	},	1013	},
1025	{ }	1014	{ }
1026	};	1015	};
1027	struct drm_i915_private *i915 = arg;	1016	struct intel_gt *gt = arg;
1028	typeof(phases) p;	1017	typeof(phases) p;
1029	int err;	1018	int err;
1030		1019
1031	for (p = phases; p->name; p++) {	1020	for (p = phases; p->name; p++) {
1032	if (p->flags & TEST_PRIORITY) {	1021	if (p->flags & TEST_PRIORITY) {
1033	if (!(i915->caps.scheduler & I915_SCHEDULER_CAP_PRIORITY))	1022	if (!(gt->i915->caps.scheduler & I915_SCHEDULER_CAP_PRIORITY))
1034	continue;	1023	continue;
1035	}	1024	}
1036		1025
@@ -1042,38 +1031,39 @@ static int igt_reset_engines(void *arg) · 5 unmodified lines
1042	return 0;	1031	return 0;
1043	}	1032	}
1044		1033
1045	static u32 fake_hangcheck(struct drm_i915_private *i915,	1034	static u32 fake_hangcheck(struct intel_gt *gt, intel_engine_mask_t mask)
1046	intel_engine_mask_t mask)
1047	{	1035	{
1048	u32 count = i915_reset_count(&i915->gpu_error);	1036	u32 count = i915_reset_count(&gt->i915->gpu_error);
1049		1037
1050	i915_reset(i915, mask, NULL);	1038	intel_gt_reset(gt, mask, NULL);
1051		1039
1052	return count;	1040	return count;
1053	}	1041	}
1054		1042
1055	static int igt_reset_wait(void *arg)	1043	static int igt_reset_wait(void *arg)
1056	{	1044	{
1057	struct drm_i915_private *i915 = arg;	1045	struct intel_gt *gt = arg;
		1046	struct i915_gpu_error *global = &gt->i915->gpu_error;
		1047	struct intel_engine_cs *engine = gt->i915->engine[RCS0];
1058	struct i915_request *rq;	1048	struct i915_request *rq;
1059	unsigned int reset_count;	1049	unsigned int reset_count;
1060	struct hang h;	1050	struct hang h;
1061	long timeout;	1051	long timeout;
1062	int err;	1052	int err;
1063		1053
1064	if (!intel_engine_can_store_dword(i915->engine[RCS0]))	1054	if (!engine \|\| !intel_engine_can_store_dword(engine))
1065	return 0;	1055	return 0;
1066		1056
1067	/* Check that we detect a stuck waiter and issue a reset */	1057	/* Check that we detect a stuck waiter and issue a reset */
1068		1058
1069	igt_global_reset_lock(i915);	1059	igt_global_reset_lock(gt);
1070		1060
1071	mutex_lock(&i915->drm.struct_mutex);	1061	mutex_lock(&gt->i915->drm.struct_mutex);
1072	err = hang_init(&h, i915);	1062	err = hang_init(&h, gt);
1073	if (err)	1063	if (err)
1074	goto unlock;	1064	goto unlock;
1075		1065
1076	rq = hang_create_request(&h, i915->engine[RCS0]);	1066	rq = hang_create_request(&h, engine);
1077	if (IS_ERR(rq)) {	1067	if (IS_ERR(rq)) {
1078	err = PTR_ERR(rq);	1068	err = PTR_ERR(rq);
1079	goto fini;	1069	goto fini;
@@ -1083,19 +1073,19 @@ static int igt_reset_wait(void *arg) · 3 unmodified lines
1083	i915_request_add(rq);	1073	i915_request_add(rq);
1084		1074
1085	if (!wait_until_running(&h, rq)) {	1075	if (!wait_until_running(&h, rq)) {
1086	struct drm_printer p = drm_info_printer(i915->drm.dev);	1076	struct drm_printer p = drm_info_printer(gt->i915->drm.dev);
1087		1077
1088	pr_err("%s: Failed to start request %llx, at %x\n",	1078	pr_err("%s: Failed to start request %llx, at %x\n",
1089	__func__, rq->fence.seqno, hws_seqno(&h, rq));	1079	__func__, rq->fence.seqno, hws_seqno(&h, rq));
1090	intel_engine_dump(rq->engine, &p, "%s\n", rq->engine->name);	1080	intel_engine_dump(rq->engine, &p, "%s\n", rq->engine->name);
1091		1081
1092	i915_gem_set_wedged(i915);	1082	intel_gt_set_wedged(gt);
1093		1083
1094	err = -EIO;	1084	err = -EIO;
1095	goto out_rq;	1085	goto out_rq;
1096	}	1086	}
1097		1087
1098	reset_count = fake_hangcheck(i915, ALL_ENGINES);	1088	reset_count = fake_hangcheck(gt, ALL_ENGINES);
1099		1089
1100	timeout = i915_request_wait(rq, 0, 10);	1090	timeout = i915_request_wait(rq, 0, 10);
1101	if (timeout < 0) {	1091	if (timeout < 0) {
@@ -1105,7 +1095,7 @@ static int igt_reset_wait(void *arg) · 3 unmodified lines
1105	goto out_rq;	1095	goto out_rq;
1106	}	1096	}
1107		1097
1108	if (i915_reset_count(&i915->gpu_error) == reset_count) {	1098	if (i915_reset_count(global) == reset_count) {
1109	pr_err("No GPU reset recorded!\n");	1099	pr_err("No GPU reset recorded!\n");
1110	err = -EINVAL;	1100	err = -EINVAL;
1111	goto out_rq;	1101	goto out_rq;
@@ -1116,10 +1106,10 @@ out_rq: · 4 unmodified lines
1116	fini:	1106	fini:
1117	hang_fini(&h);	1107	hang_fini(&h);
1118	unlock:	1108	unlock:
1119	mutex_unlock(&i915->drm.struct_mutex);	1109	mutex_unlock(&gt->i915->drm.struct_mutex);
1120	igt_global_reset_unlock(i915);	1110	igt_global_reset_unlock(gt);
1121		1111
1122	if (i915_reset_failed(i915))	1112	if (intel_gt_is_wedged(gt))
1123	return -EIO;	1113	return -EIO;
1124		1114
1125	return err;	1115	return err;
@@ -1178,11 +1168,12 @@ out_unlock: · 52 unmodified lines
1178	return err;	1168	return err;
1179	}	1169	}
1180		1170
1181	static int __igt_reset_evict_vma(struct drm_i915_private *i915,	1171	static int __igt_reset_evict_vma(struct intel_gt *gt,
1182	struct i915_address_space *vm,	1172	struct i915_address_space *vm,
1183	int (fn)(void ),	1173	int (fn)(void ),
1184	unsigned int flags)	1174	unsigned int flags)
1185	{	1175	{
		1176	struct intel_engine_cs *engine = gt->i915->engine[RCS0];
1186	struct drm_i915_gem_object *obj;	1177	struct drm_i915_gem_object *obj;
1187	struct task_struct *tsk = NULL;	1178	struct task_struct *tsk = NULL;
1188	struct i915_request *rq;	1179	struct i915_request *rq;
@@ -1190,17 +1181,17 @@ static int __igt_reset_evict_vma(struct drm_i915_private *i915, · 1 unmodified line
1190	struct hang h;	1181	struct hang h;
1191	int err;	1182	int err;
1192		1183
1193	if (!intel_engine_can_store_dword(i915->engine[RCS0]))	1184	if (!engine \|\| !intel_engine_can_store_dword(engine))
1194	return 0;	1185	return 0;
1195		1186
1196	/* Check that we can recover an unbind stuck on a hanging request */	1187	/* Check that we can recover an unbind stuck on a hanging request */
1197		1188
1198	mutex_lock(&i915->drm.struct_mutex);	1189	mutex_lock(&gt->i915->drm.struct_mutex);
1199	err = hang_init(&h, i915);	1190	err = hang_init(&h, gt);
1200	if (err)	1191	if (err)
1201	goto unlock;	1192	goto unlock;
1202		1193
1203	obj = i915_gem_object_create_internal(i915, SZ_1M);	1194	obj = i915_gem_object_create_internal(gt->i915, SZ_1M);
1204	if (IS_ERR(obj)) {	1195	if (IS_ERR(obj)) {
1205	err = PTR_ERR(obj);	1196	err = PTR_ERR(obj);
1206	goto fini;	1197	goto fini;
@@ -1220,7 +1211,7 @@ static int __igt_reset_evict_vma(struct drm_i915_private *i915, · 13 unmodified lines
1220	goto out_obj;	1211	goto out_obj;
1221	}	1212	}
1222		1213
1223	rq = hang_create_request(&h, i915->engine[RCS0]);	1214	rq = hang_create_request(&h, engine);
1224	if (IS_ERR(rq)) {	1215	if (IS_ERR(rq)) {
1225	err = PTR_ERR(rq);	1216	err = PTR_ERR(rq);
1226	goto out_obj;	1217	goto out_obj;
@@ -1258,16 +1249,16 @@ static int __igt_reset_evict_vma(struct drm_i915_private *i915, · 31 unmodified lines
1258	if (err)	1249	if (err)
1259	goto out_rq;	1250	goto out_rq;
1260		1251
1261	mutex_unlock(&i915->drm.struct_mutex);	1252	mutex_unlock(&gt->i915->drm.struct_mutex);
1262		1253
1263	if (!wait_until_running(&h, rq)) {	1254	if (!wait_until_running(&h, rq)) {
1264	struct drm_printer p = drm_info_printer(i915->drm.dev);	1255	struct drm_printer p = drm_info_printer(gt->i915->drm.dev);
1265		1256
1266	pr_err("%s: Failed to start request %llx, at %x\n",	1257	pr_err("%s: Failed to start request %llx, at %x\n",
1267	__func__, rq->fence.seqno, hws_seqno(&h, rq));	1258	__func__, rq->fence.seqno, hws_seqno(&h, rq));
1268	intel_engine_dump(rq->engine, &p, "%s\n", rq->engine->name);	1259	intel_engine_dump(rq->engine, &p, "%s\n", rq->engine->name);
1269		1260
1270	i915_gem_set_wedged(i915);	1261	intel_gt_set_wedged(gt);
1271	goto out_reset;	1262	goto out_reset;
1272	}	1263	}
1273		1264
@@ -1284,31 +1275,31 @@ static int __igt_reset_evict_vma(struct drm_i915_private *i915, · 10 unmodified lines
1284	wait_for_completion(&arg.completion);	1275	wait_for_completion(&arg.completion);
1285		1276
1286	if (wait_for(!list_empty(&rq->fence.cb_list), 10)) {	1277	if (wait_for(!list_empty(&rq->fence.cb_list), 10)) {
1287	struct drm_printer p = drm_info_printer(i915->drm.dev);	1278	struct drm_printer p = drm_info_printer(gt->i915->drm.dev);
1288		1279
1289	pr_err("igt/evict_vma kthread did not wait\n");	1280	pr_err("igt/evict_vma kthread did not wait\n");
1290	intel_engine_dump(rq->engine, &p, "%s\n", rq->engine->name);	1281	intel_engine_dump(rq->engine, &p, "%s\n", rq->engine->name);
1291		1282
1292	i915_gem_set_wedged(i915);	1283	intel_gt_set_wedged(gt);
1293	goto out_reset;	1284	goto out_reset;
1294	}	1285	}
1295		1286
1296	out_reset:	1287	out_reset:
1297	igt_global_reset_lock(i915);	1288	igt_global_reset_lock(gt);
1298	fake_hangcheck(rq->i915, rq->engine->mask);	1289	fake_hangcheck(gt, rq->engine->mask);
1299	igt_global_reset_unlock(i915);	1290	igt_global_reset_unlock(gt);
1300		1291
1301	if (tsk) {	1292	if (tsk) {
1302	struct igt_wedge_me w;	1293	struct intel_wedge_me w;
1303		1294
1304	/* The reset, even indirectly, should take less than 10ms. */	1295	/* The reset, even indirectly, should take less than 10ms. */
1305	igt_wedge_on_timeout(&w, i915, HZ / 10 /* 100ms timeout*/)	1296	intel_wedge_on_timeout(&w, gt, HZ / 10 /* 100ms */)
1306	err = kthread_stop(tsk);	1297	err = kthread_stop(tsk);
1307		1298
1308	put_task_struct(tsk);	1299	put_task_struct(tsk);
1309	}	1300	}
1310		1301
1311	mutex_lock(&i915->drm.struct_mutex);	1302	mutex_lock(&gt->i915->drm.struct_mutex);
1312	out_rq:	1303	out_rq:
1313	i915_request_put(rq);	1304	i915_request_put(rq);
1314	out_obj:	1305	out_obj:
@@ -1316,9 +1307,9 @@ out_obj: · 1 unmodified line
1316	fini:	1307	fini:
1317	hang_fini(&h);	1308	hang_fini(&h);
1318	unlock:	1309	unlock:
1319	mutex_unlock(&i915->drm.struct_mutex);	1310	mutex_unlock(&gt->i915->drm.struct_mutex);
1320		1311
1321	if (i915_reset_failed(i915))	1312	if (intel_gt_is_wedged(gt))
1322	return -EIO;	1313	return -EIO;
1323		1314
1324	return err;	1315	return err;
@@ -1326,26 +1317,26 @@ unlock: · 1 unmodified line
1326		1317
1327	static int igt_reset_evict_ggtt(void *arg)	1318	static int igt_reset_evict_ggtt(void *arg)
1328	{	1319	{
1329	struct drm_i915_private *i915 = arg;	1320	struct intel_gt *gt = arg;
1330		1321
1331	return __igt_reset_evict_vma(i915, &i915->ggtt.vm,	1322	return __igt_reset_evict_vma(gt, &gt->ggtt->vm,
1332	evict_vma, EXEC_OBJECT_WRITE);	1323	evict_vma, EXEC_OBJECT_WRITE);
1333	}	1324	}
1334		1325
1335	static int igt_reset_evict_ppgtt(void *arg)	1326	static int igt_reset_evict_ppgtt(void *arg)
1336	{	1327	{
1337	struct drm_i915_private *i915 = arg;	1328	struct intel_gt *gt = arg;
1338	struct i915_gem_context *ctx;	1329	struct i915_gem_context *ctx;
1339	struct drm_file *file;	1330	struct drm_file *file;
1340	int err;	1331	int err;
1341		1332
1342	file = mock_file(i915);	1333	file = mock_file(gt->i915);
1343	if (IS_ERR(file))	1334	if (IS_ERR(file))
1344	return PTR_ERR(file);	1335	return PTR_ERR(file);
1345		1336
1346	mutex_lock(&i915->drm.struct_mutex);	1337	mutex_lock(&gt->i915->drm.struct_mutex);
1347	ctx = live_context(i915, file);	1338	ctx = live_context(gt->i915, file);
1348	mutex_unlock(&i915->drm.struct_mutex);	1339	mutex_unlock(&gt->i915->drm.struct_mutex);
1349	if (IS_ERR(ctx)) {	1340	if (IS_ERR(ctx)) {
1350	err = PTR_ERR(ctx);	1341	err = PTR_ERR(ctx);
1351	goto out;	1342	goto out;
@@ -1353,29 +1344,29 @@ static int igt_reset_evict_ppgtt(void *arg) · 1 unmodified line
1353		1344
1354	err = 0;	1345	err = 0;
1355	if (ctx->vm) /* aliasing == global gtt locking, covered above */	1346	if (ctx->vm) /* aliasing == global gtt locking, covered above */
1356	err = __igt_reset_evict_vma(i915, ctx->vm,	1347	err = __igt_reset_evict_vma(gt, ctx->vm,
1357	evict_vma, EXEC_OBJECT_WRITE);	1348	evict_vma, EXEC_OBJECT_WRITE);
1358		1349
1359	out:	1350	out:
1360	mock_file_free(i915, file);	1351	mock_file_free(gt->i915, file);
1361	return err;	1352	return err;
1362	}	1353	}
1363		1354
1364	static int igt_reset_evict_fence(void *arg)	1355	static int igt_reset_evict_fence(void *arg)
1365	{	1356	{
1366	struct drm_i915_private *i915 = arg;	1357	struct intel_gt *gt = arg;
1367		1358
1368	return __igt_reset_evict_vma(i915, &i915->ggtt.vm,	1359	return __igt_reset_evict_vma(gt, &gt->ggtt->vm,
1369	evict_fence, EXEC_OBJECT_NEEDS_FENCE);	1360	evict_fence, EXEC_OBJECT_NEEDS_FENCE);
1370	}	1361	}
1371		1362
1372	static int wait_for_others(struct drm_i915_private *i915,	1363	static int wait_for_others(struct intel_gt *gt,
1373	struct intel_engine_cs *exclude)	1364	struct intel_engine_cs *exclude)
1374	{	1365	{
1375	struct intel_engine_cs *engine;	1366	struct intel_engine_cs *engine;
1376	enum intel_engine_id id;	1367	enum intel_engine_id id;
1377		1368
1378	for_each_engine(engine, i915, id) {	1369	for_each_engine(engine, gt->i915, id) {
1379	if (engine == exclude)	1370	if (engine == exclude)
1380	continue;	1371	continue;
1381		1372
@@ -1388,7 +1379,8 @@ static int wait_for_others(struct drm_i915_private *i915, · 6 unmodified lines
1388		1379
1389	static int igt_reset_queue(void *arg)	1380	static int igt_reset_queue(void *arg)
1390	{	1381	{
1391	struct drm_i915_private *i915 = arg;	1382	struct intel_gt *gt = arg;
		1383	struct i915_gpu_error *global = &gt->i915->gpu_error;
1392	struct intel_engine_cs *engine;	1384	struct intel_engine_cs *engine;
1393	enum intel_engine_id id;	1385	enum intel_engine_id id;
1394	struct hang h;	1386	struct hang h;
@@ -1396,14 +1388,14 @@ static int igt_reset_queue(void *arg) · 1 unmodified line
1396		1388
1397	/* Check that we replay pending requests following a hang */	1389	/* Check that we replay pending requests following a hang */
1398		1390
1399	igt_global_reset_lock(i915);	1391	igt_global_reset_lock(gt);
1400		1392
1401	mutex_lock(&i915->drm.struct_mutex);	1393	mutex_lock(&gt->i915->drm.struct_mutex);
1402	err = hang_init(&h, i915);	1394	err = hang_init(&h, gt);
1403	if (err)	1395	if (err)
1404	goto unlock;	1396	goto unlock;
1405		1397
1406	for_each_engine(engine, i915, id) {	1398	for_each_engine(engine, gt->i915, id) {
1407	struct i915_request *prev;	1399	struct i915_request *prev;
1408	IGT_TIMEOUT(end_time);	1400	IGT_TIMEOUT(end_time);
1409	unsigned int count;	1401	unsigned int count;
@@ -1444,7 +1436,7 @@ static int igt_reset_queue(void *arg) · 34 unmodified lines
1444	* (hangcheck), or we focus on resetting just one	1436	* (hangcheck), or we focus on resetting just one
1445	* engine and so avoid repeatedly resetting innocents.	1437	* engine and so avoid repeatedly resetting innocents.
1446	*/	1438	*/
1447	err = wait_for_others(i915, engine);	1439	err = wait_for_others(gt, engine);
1448	if (err) {	1440	if (err) {
1449	pr_err("%s(%s): Failed to idle other inactive engines after device reset\n",	1441	pr_err("%s(%s): Failed to idle other inactive engines after device reset\n",
1450	__func__, engine->name);	1442	__func__, engine->name);
@@ -1452,12 +1444,12 @@ static int igt_reset_queue(void *arg) · 1 unmodified line
1452	i915_request_put(prev);	1444	i915_request_put(prev);
1453		1445
1454	GEM_TRACE_DUMP();	1446	GEM_TRACE_DUMP();
1455	i915_gem_set_wedged(i915);	1447	intel_gt_set_wedged(gt);
1456	goto fini;	1448	goto fini;
1457	}	1449	}
1458		1450
1459	if (!wait_until_running(&h, prev)) {	1451	if (!wait_until_running(&h, prev)) {
1460	struct drm_printer p = drm_info_printer(i915->drm.dev);	1452	struct drm_printer p = drm_info_printer(gt->i915->drm.dev);
1461		1453
1462	pr_err("%s(%s): Failed to start request %llx, at %x\n",	1454	pr_err("%s(%s): Failed to start request %llx, at %x\n",
1463	__func__, engine->name,	1455	__func__, engine->name,
@@ -1468,13 +1460,13 @@ static int igt_reset_queue(void *arg) · 4 unmodified lines
1468	i915_request_put(rq);	1460	i915_request_put(rq);
1469	i915_request_put(prev);	1461	i915_request_put(prev);
1470		1462
1471	i915_gem_set_wedged(i915);	1463	intel_gt_set_wedged(gt);
1472		1464
1473	err = -EIO;	1465	err = -EIO;
1474	goto fini;	1466	goto fini;
1475	}	1467	}
1476		1468
1477	reset_count = fake_hangcheck(i915, BIT(id));	1469	reset_count = fake_hangcheck(gt, BIT(id));
1478		1470
1479	if (prev->fence.error != -EIO) {	1471	if (prev->fence.error != -EIO) {
1480	pr_err("GPU reset not recorded on hanging request [fence.error=%d]!\n",	1472	pr_err("GPU reset not recorded on hanging request [fence.error=%d]!\n",
@@ -1494,7 +1486,7 @@ static int igt_reset_queue(void *arg) · 13 unmodified lines
1494	goto fini;	1486	goto fini;
1495	}	1487	}
1496		1488
1497	if (i915_reset_count(&i915->gpu_error) == reset_count) {	1489	if (i915_reset_count(global) == reset_count) {
1498	pr_err("No GPU reset recorded!\n");	1490	pr_err("No GPU reset recorded!\n");
1499	i915_request_put(rq);	1491	i915_request_put(rq);
1500	i915_request_put(prev);	1492	i915_request_put(prev);
@@ -1509,11 +1501,11 @@ static int igt_reset_queue(void *arg) · 8 unmodified lines
1509	pr_info("%s: Completed %d resets\n", engine->name, count);	1501	pr_info("%s: Completed %d resets\n", engine->name, count);
1510		1502
1511	*h.batch = MI_BATCH_BUFFER_END;	1503	*h.batch = MI_BATCH_BUFFER_END;
1512	i915_gem_chipset_flush(i915);	1504	intel_gt_chipset_flush(engine->gt);
1513		1505
1514	i915_request_put(prev);	1506	i915_request_put(prev);
1515		1507
1516	err = igt_flush_test(i915, I915_WAIT_LOCKED);	1508	err = igt_flush_test(gt->i915, I915_WAIT_LOCKED);
1517	if (err)	1509	if (err)
1518	break;	1510	break;
1519	}	1511	}
@@ -1521,10 +1513,10 @@ static int igt_reset_queue(void *arg) · 1 unmodified line
1521	fini:	1513	fini:
1522	hang_fini(&h);	1514	hang_fini(&h);
1523	unlock:	1515	unlock:
1524	mutex_unlock(&i915->drm.struct_mutex);	1516	mutex_unlock(&gt->i915->drm.struct_mutex);
1525	igt_global_reset_unlock(i915);	1517	igt_global_reset_unlock(gt);
1526		1518
1527	if (i915_reset_failed(i915))	1519	if (intel_gt_is_wedged(gt))
1528	return -EIO;	1520	return -EIO;
1529		1521
1530	return err;	1522	return err;
@@ -1532,8 +1524,9 @@ unlock: · 1 unmodified line
1532		1524
1533	static int igt_handle_error(void *arg)	1525	static int igt_handle_error(void *arg)
1534	{	1526	{
1535	struct drm_i915_private *i915 = arg;	1527	struct intel_gt *gt = arg;
1536	struct intel_engine_cs *engine = i915->engine[RCS0];	1528	struct i915_gpu_error *global = &gt->i915->gpu_error;
		1529	struct intel_engine_cs *engine = gt->i915->engine[RCS0];
1537	struct hang h;	1530	struct hang h;
1538	struct i915_request *rq;	1531	struct i915_request *rq;
1539	struct i915_gpu_state *error;	1532	struct i915_gpu_state *error;
@@ -1541,15 +1534,15 @@ static int igt_handle_error(void *arg) · 1 unmodified line
1541		1534
1542	/* Check that we can issue a global GPU and engine reset */	1535	/* Check that we can issue a global GPU and engine reset */
1543		1536
1544	if (!intel_has_reset_engine(i915))	1537	if (!intel_has_reset_engine(gt->i915))
1545	return 0;	1538	return 0;
1546		1539
1547	if (!engine \|\| !intel_engine_can_store_dword(engine))	1540	if (!engine \|\| !intel_engine_can_store_dword(engine))
1548	return 0;	1541	return 0;
1549		1542
1550	mutex_lock(&i915->drm.struct_mutex);	1543	mutex_lock(&gt->i915->drm.struct_mutex);
1551		1544
1552	err = hang_init(&h, i915);	1545	err = hang_init(&h, gt);
1553	if (err)	1546	if (err)
1554	goto err_unlock;	1547	goto err_unlock;
1555		1548
@@ -1563,28 +1556,28 @@ static int igt_handle_error(void *arg) · 7 unmodified lines
1563	i915_request_add(rq);	1556	i915_request_add(rq);
1564		1557
1565	if (!wait_until_running(&h, rq)) {	1558	if (!wait_until_running(&h, rq)) {
1566	struct drm_printer p = drm_info_printer(i915->drm.dev);	1559	struct drm_printer p = drm_info_printer(gt->i915->drm.dev);
1567		1560
1568	pr_err("%s: Failed to start request %llx, at %x\n",	1561	pr_err("%s: Failed to start request %llx, at %x\n",
1569	__func__, rq->fence.seqno, hws_seqno(&h, rq));	1562	__func__, rq->fence.seqno, hws_seqno(&h, rq));
1570	intel_engine_dump(rq->engine, &p, "%s\n", rq->engine->name);	1563	intel_engine_dump(rq->engine, &p, "%s\n", rq->engine->name);
1571		1564
1572	i915_gem_set_wedged(i915);	1565	intel_gt_set_wedged(gt);
1573		1566
1574	err = -EIO;	1567	err = -EIO;
1575	goto err_request;	1568	goto err_request;
1576	}	1569	}
1577		1570
1578	mutex_unlock(&i915->drm.struct_mutex);	1571	mutex_unlock(&gt->i915->drm.struct_mutex);
1579		1572
1580	/* Temporarily disable error capture */	1573	/* Temporarily disable error capture */
1581	error = xchg(&i915->gpu_error.first_error, (void *)-1);	1574	error = xchg(&global->first_error, (void *)-1);
1582		1575
1583	i915_handle_error(i915, engine->mask, 0, NULL);	1576	intel_gt_handle_error(gt, engine->mask, 0, NULL);
1584		1577
1585	xchg(&i915->gpu_error.first_error, error);	1578	xchg(&global->first_error, error);
1586		1579
1587	mutex_lock(&i915->drm.struct_mutex);	1580	mutex_lock(&gt->i915->drm.struct_mutex);
1588		1581
1589	if (rq->fence.error != -EIO) {	1582	if (rq->fence.error != -EIO) {
1590	pr_err("Guilty request not identified!\n");	1583	pr_err("Guilty request not identified!\n");
@@ -1597,7 +1590,7 @@ err_request: · 6 unmodified lines
1597	err_fini:	1590	err_fini:
1598	hang_fini(&h);	1591	hang_fini(&h);
1599	err_unlock:	1592	err_unlock:
1600	mutex_unlock(&i915->drm.struct_mutex);	1593	mutex_unlock(&gt->i915->drm.struct_mutex);
1601	return err;	1594	return err;
1602	}	1595	}
1603		1596
@@ -1614,7 +1607,7 @@ static int __igt_atomic_reset_engine(struct intel_engine_cs *engine, · 10 unmodified lines
1614	tasklet_disable_nosync(t);	1607	tasklet_disable_nosync(t);
1615	p->critical_section_begin();	1608	p->critical_section_begin();
1616		1609
1617	err = i915_reset_engine(engine, NULL);	1610	err = intel_engine_reset(engine, NULL);
1618		1611
1619	p->critical_section_end();	1612	p->critical_section_end();
1620	tasklet_enable(t);	1613	tasklet_enable(t);
@@ -1629,7 +1622,6 @@ static int __igt_atomic_reset_engine(struct intel_engine_cs *engine, · 8 unmodified lines
1629	static int igt_atomic_reset_engine(struct intel_engine_cs *engine,	1622	static int igt_atomic_reset_engine(struct intel_engine_cs *engine,
1630	const struct igt_atomic_section *p)	1623	const struct igt_atomic_section *p)
1631	{	1624	{
1632	struct drm_i915_private *i915 = engine->i915;
1633	struct i915_request *rq;	1625	struct i915_request *rq;
1634	struct hang h;	1626	struct hang h;
1635	int err;	1627	int err;
@@ -1638,7 +1630,7 @@ static int igt_atomic_reset_engine(struct intel_engine_cs *engine, · 2 unmodified lines
1638	if (err)	1630	if (err)
1639	return err;	1631	return err;
1640		1632
1641	err = hang_init(&h, i915);	1633	err = hang_init(&h, engine->gt);
1642	if (err)	1634	if (err)
1643	return err;	1635	return err;
1644		1636
@@ -1657,16 +1649,16 @@ static int igt_atomic_reset_engine(struct intel_engine_cs *engine, · 12 unmodified lines
1657	pr_err("%s(%s): Failed to start request %llx, at %x\n",	1649	pr_err("%s(%s): Failed to start request %llx, at %x\n",
1658	__func__, engine->name,	1650	__func__, engine->name,
1659	rq->fence.seqno, hws_seqno(&h, rq));	1651	rq->fence.seqno, hws_seqno(&h, rq));
1660	i915_gem_set_wedged(i915);	1652	intel_gt_set_wedged(engine->gt);
1661	err = -EIO;	1653	err = -EIO;
1662	}	1654	}
1663		1655
1664	if (err == 0) {	1656	if (err == 0) {
1665	struct igt_wedge_me w;	1657	struct intel_wedge_me w;
1666		1658
1667	igt_wedge_on_timeout(&w, i915, HZ / 20 /* 50ms timeout*/)	1659	intel_wedge_on_timeout(&w, engine->gt, HZ / 20 /* 50ms */)
1668	i915_request_wait(rq, 0, MAX_SCHEDULE_TIMEOUT);	1660	i915_request_wait(rq, 0, MAX_SCHEDULE_TIMEOUT);
1669	if (i915_reset_failed(i915))	1661	if (intel_gt_is_wedged(engine->gt))
1670	err = -EIO;	1662	err = -EIO;
1671	}	1663	}
1672		1664
@@ -1678,30 +1670,30 @@ out: · 5 unmodified lines
1678		1670
1679	static int igt_reset_engines_atomic(void *arg)	1671	static int igt_reset_engines_atomic(void *arg)
1680	{	1672	{
1681	struct drm_i915_private *i915 = arg;	1673	struct intel_gt *gt = arg;
1682	const typeof(igt_atomic_phases) p;	1674	const typeof(igt_atomic_phases) p;
1683	int err = 0;	1675	int err = 0;
1684		1676
1685	/* Check that the engines resets are usable from atomic context */	1677	/* Check that the engines resets are usable from atomic context */
1686		1678
1687	if (!intel_has_reset_engine(i915))	1679	if (!intel_has_reset_engine(gt->i915))
1688	return 0;	1680	return 0;
1689		1681
1690	if (USES_GUC_SUBMISSION(i915))	1682	if (USES_GUC_SUBMISSION(gt->i915))
1691	return 0;	1683	return 0;
1692		1684
1693	igt_global_reset_lock(i915);	1685	igt_global_reset_lock(gt);
1694	mutex_lock(&i915->drm.struct_mutex);	1686	mutex_lock(&gt->i915->drm.struct_mutex);
1695		1687
1696	/* Flush any requests before we get started and check basics */	1688	/* Flush any requests before we get started and check basics */
1697	if (!igt_force_reset(i915))	1689	if (!igt_force_reset(gt))
1698	goto unlock;	1690	goto unlock;
1699		1691
1700	for (p = igt_atomic_phases; p->name; p++) {	1692	for (p = igt_atomic_phases; p->name; p++) {
1701	struct intel_engine_cs *engine;	1693	struct intel_engine_cs *engine;
1702	enum intel_engine_id id;	1694	enum intel_engine_id id;
1703		1695
1704	for_each_engine(engine, i915, id) {	1696	for_each_engine(engine, gt->i915, id) {
1705	err = igt_atomic_reset_engine(engine, p);	1697	err = igt_atomic_reset_engine(engine, p);
1706	if (err)	1698	if (err)
1707	goto out;	1699	goto out;
@@ -1710,11 +1702,11 @@ static int igt_reset_engines_atomic(void *arg) · 2 unmodified lines
1710		1702
1711	out:	1703	out:
1712	/* As we poke around the guts, do a full reset before continuing. */	1704	/* As we poke around the guts, do a full reset before continuing. */
1713	igt_force_reset(i915);	1705	igt_force_reset(gt);
1714		1706
1715	unlock:	1707	unlock:
1716	mutex_unlock(&i915->drm.struct_mutex);	1708	mutex_unlock(&gt->i915->drm.struct_mutex);
1717	igt_global_reset_unlock(i915);	1709	igt_global_reset_unlock(gt);
1718		1710
1719	return err;	1711	return err;
1720	}	1712	}
@@ -1736,28 +1728,29 @@ int intel_hangcheck_live_selftests(struct drm_i915_private *i915) · 15 unmodified lines
1736	SUBTEST(igt_reset_evict_fence),	1728	SUBTEST(igt_reset_evict_fence),
1737	SUBTEST(igt_handle_error),	1729	SUBTEST(igt_handle_error),
1738	};	1730	};
		1731	struct intel_gt *gt = &i915->gt;
1739	intel_wakeref_t wakeref;	1732	intel_wakeref_t wakeref;
1740	bool saved_hangcheck;	1733	bool saved_hangcheck;
1741	int err;	1734	int err;
1742		1735
1743	if (!intel_has_gpu_reset(i915))	1736	if (!intel_has_gpu_reset(gt->i915))
1744	return 0;	1737	return 0;
1745		1738
1746	if (i915_terminally_wedged(i915))	1739	if (intel_gt_is_wedged(gt))
1747	return -EIO; /* we're long past hope of a successful reset */	1740	return -EIO; /* we're long past hope of a successful reset */
1748		1741
1749	wakeref = intel_runtime_pm_get(&i915->runtime_pm);	1742	wakeref = intel_runtime_pm_get(&gt->i915->runtime_pm);
1750	saved_hangcheck = fetch_and_zero(&i915_modparams.enable_hangcheck);	1743	saved_hangcheck = fetch_and_zero(&i915_modparams.enable_hangcheck);
1751	drain_delayed_work(&i915->gpu_error.hangcheck_work); /* flush param */	1744	drain_delayed_work(&gt->hangcheck.work); /* flush param */
1752		1745
1753	err = i915_subtests(tests, i915);	1746	err = intel_gt_live_subtests(tests, gt);
1754		1747
1755	mutex_lock(&i915->drm.struct_mutex);	1748	mutex_lock(&gt->i915->drm.struct_mutex);
1756	igt_flush_test(i915, I915_WAIT_LOCKED);	1749	igt_flush_test(gt->i915, I915_WAIT_LOCKED);
1757	mutex_unlock(&i915->drm.struct_mutex);	1750	mutex_unlock(&gt->i915->drm.struct_mutex);
1758		1751
1759	i915_modparams.enable_hangcheck = saved_hangcheck;	1752	i915_modparams.enable_hangcheck = saved_hangcheck;
1760	intel_runtime_pm_put(&i915->runtime_pm, wakeref);	1753	intel_runtime_pm_put(&gt->i915->runtime_pm, wakeref);
1761		1754
1762	return err;	1755	return err;
1763	}	1756	}

drivers/gpu/drm/i915/gt/selftest_lrc.c+361−30

@@ -55,7 +55,7 @@ static int live_sanitycheck(void *arg) · 54 unmodified lines
55	if (!igt_wait_for_spinner(&spin, rq)) {	55	if (!igt_wait_for_spinner(&spin, rq)) {
56	GEM_TRACE("spinner failed to start\n");	56	GEM_TRACE("spinner failed to start\n");
57	GEM_TRACE_DUMP();	57	GEM_TRACE_DUMP();
58	i915_gem_set_wedged(i915);	58	intel_gt_set_wedged(&i915->gt);
59	err = -EIO;	59	err = -EIO;
60	goto err_ctx;	60	goto err_ctx;
61	}	61	}
@@ -73,12 +73,231 @@ err_ctx: · 11 unmodified lines
73	err_spin:	73	err_spin:
74	igt_spinner_fini(&spin);	74	igt_spinner_fini(&spin);
75	err_unlock:	75	err_unlock:
76	igt_flush_test(i915, I915_WAIT_LOCKED);
77	intel_runtime_pm_put(&i915->runtime_pm, wakeref);	76	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
78	mutex_unlock(&i915->drm.struct_mutex);	77	mutex_unlock(&i915->drm.struct_mutex);
79	return err;	78	return err;
80	}	79	}
81		80
		81	static int
		82	emit_semaphore_chain(struct i915_request rq, struct i915_vma vma, int idx)
		83	{
		84	u32 *cs;
		85
		86	cs = intel_ring_begin(rq, 10);
		87	if (IS_ERR(cs))
		88	return PTR_ERR(cs);
		89
		90	*cs++ = MI_ARB_ON_OFF \| MI_ARB_ENABLE;
		91
		92	*cs++ = MI_SEMAPHORE_WAIT \|
		93	MI_SEMAPHORE_GLOBAL_GTT \|
		94	MI_SEMAPHORE_POLL \|
		95	MI_SEMAPHORE_SAD_NEQ_SDD;
		96	*cs++ = 0;
		97	cs++ = i915_ggtt_offset(vma) + 4 idx;
		98	*cs++ = 0;
		99
		100	if (idx > 0) {
		101	*cs++ = MI_STORE_DWORD_IMM_GEN4 \| MI_USE_GGTT;
		102	cs++ = i915_ggtt_offset(vma) + 4 (idx - 1);
		103	*cs++ = 0;
		104	*cs++ = 1;
		105	} else {
		106	*cs++ = MI_NOOP;
		107	*cs++ = MI_NOOP;
		108	*cs++ = MI_NOOP;
		109	*cs++ = MI_NOOP;
		110	}
		111
		112	*cs++ = MI_ARB_ON_OFF \| MI_ARB_DISABLE;
		113
		114	intel_ring_advance(rq, cs);
		115	return 0;
		116	}
		117
		118	static struct i915_request *
		119	semaphore_queue(struct intel_engine_cs engine, struct i915_vma vma, int idx)
		120	{
		121	struct i915_gem_context *ctx;
		122	struct i915_request *rq;
		123	int err;
		124
		125	ctx = kernel_context(engine->i915);
		126	if (!ctx)
		127	return ERR_PTR(-ENOMEM);
		128
		129	rq = igt_request_alloc(ctx, engine);
		130	if (IS_ERR(rq))
		131	goto out_ctx;
		132
		133	err = emit_semaphore_chain(rq, vma, idx);
		134	i915_request_add(rq);
		135	if (err)
		136	rq = ERR_PTR(err);
		137
		138	out_ctx:
		139	kernel_context_close(ctx);
		140	return rq;
		141	}
		142
		143	static int
		144	release_queue(struct intel_engine_cs *engine,
		145	struct i915_vma *vma,
		146	int idx)
		147	{
		148	struct i915_sched_attr attr = {
		149	.priority = I915_USER_PRIORITY(I915_PRIORITY_MAX),
		150	};
		151	struct i915_request *rq;
		152	u32 *cs;
		153
		154	rq = i915_request_create(engine->kernel_context);
		155	if (IS_ERR(rq))
		156	return PTR_ERR(rq);
		157
		158	cs = intel_ring_begin(rq, 4);
		159	if (IS_ERR(cs)) {
		160	i915_request_add(rq);
		161	return PTR_ERR(cs);
		162	}
		163
		164	*cs++ = MI_STORE_DWORD_IMM_GEN4 \| MI_USE_GGTT;
		165	cs++ = i915_ggtt_offset(vma) + 4 (idx - 1);
		166	*cs++ = 0;
		167	*cs++ = 1;
		168
		169	intel_ring_advance(rq, cs);
		170	i915_request_add(rq);
		171
		172	engine->schedule(rq, &attr);
		173
		174	return 0;
		175	}
		176
		177	static int
		178	slice_semaphore_queue(struct intel_engine_cs *outer,
		179	struct i915_vma *vma,
		180	int count)
		181	{
		182	struct intel_engine_cs *engine;
		183	struct i915_request *head;
		184	enum intel_engine_id id;
		185	int err, i, n = 0;
		186
		187	head = semaphore_queue(outer, vma, n++);
		188	if (IS_ERR(head))
		189	return PTR_ERR(head);
		190
		191	i915_request_get(head);
		192	for_each_engine(engine, outer->i915, id) {
		193	for (i = 0; i < count; i++) {
		194	struct i915_request *rq;
		195
		196	rq = semaphore_queue(engine, vma, n++);
		197	if (IS_ERR(rq)) {
		198	err = PTR_ERR(rq);
		199	goto out;
		200	}
		201	}
		202	}
		203
		204	err = release_queue(outer, vma, n);
		205	if (err)
		206	goto out;
		207
		208	if (i915_request_wait(head,
		209	I915_WAIT_LOCKED,
		210	2 * RUNTIME_INFO(outer->i915)->num_engines * (count + 2) * (count + 3)) < 0) {
		211	pr_err("Failed to slice along semaphore chain of length (%d, %d)!\n",
		212	count, n);
		213	GEM_TRACE_DUMP();
		214	intel_gt_set_wedged(outer->gt);
		215	err = -EIO;
		216	}
		217
		218	out:
		219	i915_request_put(head);
		220	return err;
		221	}
		222
		223	static int live_timeslice_preempt(void *arg)
		224	{
		225	struct drm_i915_private *i915 = arg;
		226	struct drm_i915_gem_object *obj;
		227	intel_wakeref_t wakeref;
		228	struct i915_vma *vma;
		229	void *vaddr;
		230	int err = 0;
		231	int count;
		232
		233	/*
		234	* If a request takes too long, we would like to give other users
		235	* a fair go on the GPU. In particular, users may create batches
		236	* that wait upon external input, where that input may even be
		237	* supplied by another GPU job. To avoid blocking forever, we
		238	* need to preempt the current task and replace it with another
		239	* ready task.
		240	*/
		241
		242	mutex_lock(&i915->drm.struct_mutex);
		243	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
		244
		245	obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
		246	if (IS_ERR(obj)) {
		247	err = PTR_ERR(obj);
		248	goto err_unlock;
		249	}
		250
		251	vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
		252	if (IS_ERR(vma)) {
		253	err = PTR_ERR(vma);
		254	goto err_obj;
		255	}
		256
		257	vaddr = i915_gem_object_pin_map(obj, I915_MAP_WC);
		258	if (IS_ERR(vaddr)) {
		259	err = PTR_ERR(vaddr);
		260	goto err_obj;
		261	}
		262
		263	err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL);
		264	if (err)
		265	goto err_map;
		266
		267	for_each_prime_number_from(count, 1, 16) {
		268	struct intel_engine_cs *engine;
		269	enum intel_engine_id id;
		270
		271	for_each_engine(engine, i915, id) {
		272	if (!intel_engine_has_preemption(engine))
		273	continue;
		274
		275	memset(vaddr, 0, PAGE_SIZE);
		276
		277	err = slice_semaphore_queue(engine, vma, count);
		278	if (err)
		279	goto err_pin;
		280
		281	if (igt_flush_test(i915, I915_WAIT_LOCKED)) {
		282	err = -EIO;
		283	goto err_pin;
		284	}
		285	}
		286	}
		287
		288	err_pin:
		289	i915_vma_unpin(vma);
		290	err_map:
		291	i915_gem_object_unpin_map(obj);
		292	err_obj:
		293	i915_gem_object_put(obj);
		294	err_unlock:
		295	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
		296	mutex_unlock(&i915->drm.struct_mutex);
		297
		298	return err;
		299	}
		300
82	static int live_busywait_preempt(void *arg)	301	static int live_busywait_preempt(void *arg)
83	{	302	{
84	struct drm_i915_private *i915 = arg;	303	struct drm_i915_private *i915 = arg;
@@ -138,6 +357,9 @@ static int live_busywait_preempt(void *arg) · 53 unmodified lines
138	struct igt_live_test t;	357	struct igt_live_test t;
139	u32 *cs;	358	u32 *cs;
140		359
		360	if (!intel_engine_has_preemption(engine))
		361	continue;
		362
141	if (!intel_engine_can_store_dword(engine))	363	if (!intel_engine_can_store_dword(engine))
142	continue;	364	continue;
143		365
@@ -229,7 +451,7 @@ static int live_busywait_preempt(void *arg) · 85 unmodified lines
229	intel_engine_dump(engine, &p, "%s\n", engine->name);	451	intel_engine_dump(engine, &p, "%s\n", engine->name);
230	GEM_TRACE_DUMP();	452	GEM_TRACE_DUMP();
231		453
232	i915_gem_set_wedged(i915);	454	intel_gt_set_wedged(&i915->gt);
233	err = -EIO;	455	err = -EIO;
234	goto err_vma;	456	goto err_vma;
235	}	457	}
@@ -253,8 +475,6 @@ err_ctx_lo: · 17 unmodified lines
253	err_ctx_hi:	475	err_ctx_hi:
254	kernel_context_close(ctx_hi);	476	kernel_context_close(ctx_hi);
255	err_unlock:	477	err_unlock:
256	if (igt_flush_test(i915, I915_WAIT_LOCKED))
257	err = -EIO;
258	intel_runtime_pm_put(&i915->runtime_pm, wakeref);	478	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
259	mutex_unlock(&i915->drm.struct_mutex);	479	mutex_unlock(&i915->drm.struct_mutex);
260	return err;	480	return err;
@@ -320,7 +540,7 @@ static int live_preempt(void *arg) · 59 unmodified lines
320	if (!igt_wait_for_spinner(&spin_lo, rq)) {	540	if (!igt_wait_for_spinner(&spin_lo, rq)) {
321	GEM_TRACE("lo spinner failed to start\n");	541	GEM_TRACE("lo spinner failed to start\n");
322	GEM_TRACE_DUMP();	542	GEM_TRACE_DUMP();
323	i915_gem_set_wedged(i915);	543	intel_gt_set_wedged(&i915->gt);
324	err = -EIO;	544	err = -EIO;
325	goto err_ctx_lo;	545	goto err_ctx_lo;
326	}	546	}
@@ -337,7 +557,7 @@ static int live_preempt(void *arg) · 10 unmodified lines
337	if (!igt_wait_for_spinner(&spin_hi, rq)) {	557	if (!igt_wait_for_spinner(&spin_hi, rq)) {
338	GEM_TRACE("hi spinner failed to start\n");	558	GEM_TRACE("hi spinner failed to start\n");
339	GEM_TRACE_DUMP();	559	GEM_TRACE_DUMP();
340	i915_gem_set_wedged(i915);	560	intel_gt_set_wedged(&i915->gt);
341	err = -EIO;	561	err = -EIO;
342	goto err_ctx_lo;	562	goto err_ctx_lo;
343	}	563	}
@@ -361,7 +581,6 @@ err_spin_lo: · 17 unmodified lines
361	err_spin_hi:	581	err_spin_hi:
362	igt_spinner_fini(&spin_hi);	582	igt_spinner_fini(&spin_hi);
363	err_unlock:	583	err_unlock:
364	igt_flush_test(i915, I915_WAIT_LOCKED);
365	intel_runtime_pm_put(&i915->runtime_pm, wakeref);	584	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
366	mutex_unlock(&i915->drm.struct_mutex);	585	mutex_unlock(&i915->drm.struct_mutex);
367	return err;	586	return err;

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drivers/gpu/drm/i915/gt/selftest_reset.c+96−37

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drivers/gpu/drm/i915/gt/selftest_timeline.crenamed from drivers/gpu/drm/i915/selftests/i915_timeline.c+65−66

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drivers/gpu/drm/i915/gt/selftest_workarounds.c+89−66

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drivers/gpu/drm/i915/gt/selftests/mock_timeline.crenamed from drivers/gpu/drm/i915/selftests/mock_timeline.c+4−4

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drivers/gpu/drm/i915/gt/selftests/mock_timeline.hrenamed from drivers/gpu/drm/i915/selftests/mock_timeline.h+3−3

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drivers/gpu/drm/i915/gt/uc/Makefile+5−0

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drivers/gpu/drm/i915/gt/uc/intel_guc.crenamed from drivers/gpu/drm/i915/intel_guc.c+118−172

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drivers/gpu/drm/i915/gt/uc/intel_guc.hrenamed from drivers/gpu/drm/i915/intel_guc.h+17−16

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drivers/gpu/drm/i915/gt/uc/intel_guc_ads.crenamed from drivers/gpu/drm/i915/intel_guc_ads.c+15−14

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drivers/gpu/drm/i915/gt/uc/intel_guc_ads.hrenamed from drivers/gpu/drm/i915/intel_guc_ads.h+0−0

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drivers/gpu/drm/i915/gt/uc/intel_guc_ct.crenamed from drivers/gpu/drm/i915/intel_guc_ct.c+4−18

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drivers/gpu/drm/i915/gt/uc/intel_guc_ct.hrenamed from drivers/gpu/drm/i915/intel_guc_ct.h+9−2

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drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c+181−0

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drivers/gpu/drm/i915/gt/uc/intel_guc_fw.hrenamed from drivers/gpu/drm/i915/intel_guc_fw.h+0−0

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drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.hrenamed from drivers/gpu/drm/i915/intel_guc_fwif.h+5−76

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drivers/gpu/drm/i915/gt/uc/intel_guc_log.crenamed from drivers/gpu/drm/i915/intel_guc_log.c+38−10

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drivers/gpu/drm/i915/gt/uc/intel_guc_log.hrenamed from drivers/gpu/drm/i915/intel_guc_log.h+0−1

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drivers/gpu/drm/i915/gt/uc/intel_guc_reg.hrenamed from drivers/gpu/drm/i915/intel_guc_reg.h+22−16

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drivers/gpu/drm/i915/gt/uc/intel_guc_submission.crenamed from drivers/gpu/drm/i915/intel_guc_submission.c+103−393

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drivers/gpu/drm/i915/gt/uc/intel_guc_submission.hrenamed from drivers/gpu/drm/i915/intel_guc_submission.h+0−2

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drivers/gpu/drm/i915/gt/uc/intel_huc.crenamed from drivers/gpu/drm/i915/intel_huc.c+41−28

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drivers/gpu/drm/i915/gt/uc/intel_huc.hrenamed from drivers/gpu/drm/i915/intel_huc.h+5−7

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drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c+53−0

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drivers/gpu/drm/i915/gt/uc/intel_huc_fw.hrenamed from drivers/gpu/drm/i915/intel_huc_fw.h+0−0

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drivers/gpu/drm/i915/gt/uc/intel_uc.c+570−0

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drivers/gpu/drm/i915/gt/uc/intel_uc.hrenamed from drivers/gpu/drm/i915/intel_uc.h+22−17

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drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c+540−0

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drivers/gpu/drm/i915/gt/uc/intel_uc_fw.hrenamed from drivers/gpu/drm/i915/intel_uc_fw.h+66−36

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drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h+82−0

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drivers/gpu/drm/i915/gt/uc/selftest_guc.crenamed from drivers/gpu/drm/i915/selftests/intel_guc.c+13−36

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drivers/gpu/drm/i915/gvt/gtt.h+7−6

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drivers/gpu/drm/i915/gvt/scheduler.c+1−1

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drivers/gpu/drm/i915/i915_active.c+215−106

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drivers/gpu/drm/i915/i915_active.h+16−12

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drivers/gpu/drm/i915/i915_debugfs.c+107−110

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drivers/gpu/drm/i915/i915_drv.c+105−95

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drivers/gpu/drm/i915/i915_drv.h+66−179

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drivers/gpu/drm/i915/i915_fixed.h+5−0

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drivers/gpu/drm/i915/i915_gem.c+119−199

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drivers/gpu/drm/i915/i915_gem_batch_pool.c+17−25

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drivers/gpu/drm/i915/i915_gem_fence_reg.c+32−0

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drivers/gpu/drm/i915/i915_gem_fence_reg.h+3−0

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drivers/gpu/drm/i915/i915_gem_gtt.c+844−1209

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drivers/gpu/drm/i915/i915_gem_gtt.h+53−147

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drivers/gpu/drm/i915/i915_gem_render_state.h+0−31

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drivers/gpu/drm/i915/i915_globals.h+2−0

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drivers/gpu/drm/i915/i915_gpu_error.c+262−326

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drivers/gpu/drm/i915/i915_gpu_error.h+4−67

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drivers/gpu/drm/i915/i915_irq.c+411−392

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drivers/gpu/drm/i915/i915_params.c+3−2

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drivers/gpu/drm/i915/i915_pci.c+37−6

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drivers/gpu/drm/i915/i915_perf.c+220−84

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drivers/gpu/drm/i915/i915_pmu.c+1−3

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drivers/gpu/drm/i915/i915_reg.h+158−73

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drivers/gpu/drm/i915/i915_request.c+69−57

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drivers/gpu/drm/i915/i915_request.h+19−5

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drivers/gpu/drm/i915/i915_scheduler.c+2−2

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drivers/gpu/drm/i915/i915_scheduler_types.h+1−0

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drivers/gpu/drm/i915/i915_selftest.h+26−1

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drivers/gpu/drm/i915/i915_timeline.h+0−94

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drivers/gpu/drm/i915/i915_trace.h+6−6

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drivers/gpu/drm/i915/i915_utils.h+12−0

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drivers/gpu/drm/i915/i915_vgpu.c+43−20

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drivers/gpu/drm/i915/i915_vgpu.h+4−3

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drivers/gpu/drm/i915/i915_vma.c+28−45

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drivers/gpu/drm/i915/intel_device_info.c+17−23

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drivers/gpu/drm/i915/intel_device_info.h+4−1

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drivers/gpu/drm/i915/intel_drv.h+32−5

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drivers/gpu/drm/i915/intel_guc_fw.c+0−308

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drivers/gpu/drm/i915/intel_gvt.c+4−3

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drivers/gpu/drm/i915/intel_gvt.h+4−3

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drivers/gpu/drm/i915/intel_huc_fw.c+0−215

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drivers/gpu/drm/i915/intel_pm.c+214−227

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drivers/gpu/drm/i915/intel_pm.h+2−2

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drivers/gpu/drm/i915/intel_runtime_pm.c+1−1

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drivers/gpu/drm/i915/intel_runtime_pm.h+1−1

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drivers/gpu/drm/i915/intel_uc.c+0−561

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drivers/gpu/drm/i915/intel_uc_fw.c+0−357

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drivers/gpu/drm/i915/intel_uncore.c+261−204

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drivers/gpu/drm/i915/intel_uncore.h+13−11

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drivers/gpu/drm/i915/intel_wakeref.c+5−4

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drivers/gpu/drm/i915/intel_wakeref.h+9−2

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drivers/gpu/drm/i915/intel_wopcm.c+22−18

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drivers/gpu/drm/i915/intel_wopcm.h+3−1

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drivers/gpu/drm/i915/oa/Makefile+0−0

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drivers/gpu/drm/i915/oa/i915_oa_bdw.crenamed from drivers/gpu/drm/i915/i915_oa_bdw.c+0−0

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drivers/gpu/drm/i915/oa/i915_oa_bdw.hrenamed from drivers/gpu/drm/i915/i915_oa_bdw.h+1−1

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drivers/gpu/drm/i915/oa/i915_oa_bxt.crenamed from drivers/gpu/drm/i915/i915_oa_bxt.c+0−0

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drivers/gpu/drm/i915/oa/i915_oa_bxt.hrenamed from drivers/gpu/drm/i915/i915_oa_bxt.h+1−1

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drivers/gpu/drm/i915/oa/i915_oa_cflgt2.crenamed from drivers/gpu/drm/i915/i915_oa_cflgt2.c+0−0

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drivers/gpu/drm/i915/oa/i915_oa_cflgt2.hrenamed from drivers/gpu/drm/i915/i915_oa_cflgt2.h+1−1

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drivers/gpu/drm/i915/oa/i915_oa_cflgt3.crenamed from drivers/gpu/drm/i915/i915_oa_cflgt3.c+0−0

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drivers/gpu/drm/i915/oa/i915_oa_cflgt3.hrenamed from drivers/gpu/drm/i915/i915_oa_cflgt3.h+1−1

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drivers/gpu/drm/i915/oa/i915_oa_chv.crenamed from drivers/gpu/drm/i915/i915_oa_chv.c+0−0

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drivers/gpu/drm/i915/oa/i915_oa_chv.hrenamed from drivers/gpu/drm/i915/i915_oa_chv.h+1−1

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drivers/gpu/drm/i915/oa/i915_oa_cnl.crenamed from drivers/gpu/drm/i915/i915_oa_cnl.c+0−0

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drivers/gpu/drm/i915/oa/i915_oa_cnl.hrenamed from drivers/gpu/drm/i915/i915_oa_cnl.h+1−1

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drivers/gpu/drm/i915/oa/i915_oa_glk.crenamed from drivers/gpu/drm/i915/i915_oa_glk.c+0−0

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drivers/gpu/drm/i915/oa/i915_oa_glk.hrenamed from drivers/gpu/drm/i915/i915_oa_glk.h+1−1

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drivers/gpu/drm/i915/oa/i915_oa_hsw.crenamed from drivers/gpu/drm/i915/i915_oa_hsw.c+0−0

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drivers/gpu/drm/i915/oa/i915_oa_hsw.hrenamed from drivers/gpu/drm/i915/i915_oa_hsw.h+1−1

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drivers/gpu/drm/i915/oa/i915_oa_icl.crenamed from drivers/gpu/drm/i915/i915_oa_icl.c+0−0

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drivers/gpu/drm/i915/oa/i915_oa_icl.hrenamed from drivers/gpu/drm/i915/i915_oa_icl.h+1−1

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drivers/gpu/drm/i915/oa/i915_oa_kblgt2.crenamed from drivers/gpu/drm/i915/i915_oa_kblgt2.c+0−0

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drivers/gpu/drm/i915/oa/i915_oa_kblgt2.hrenamed from drivers/gpu/drm/i915/i915_oa_kblgt2.h+1−1

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drivers/gpu/drm/i915/oa/i915_oa_kblgt3.crenamed from drivers/gpu/drm/i915/i915_oa_kblgt3.c+0−0

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drivers/gpu/drm/i915/oa/i915_oa_kblgt3.hrenamed from drivers/gpu/drm/i915/i915_oa_kblgt3.h+1−1

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drivers/gpu/drm/i915/oa/i915_oa_sklgt2.crenamed from drivers/gpu/drm/i915/i915_oa_sklgt2.c+0−0

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drivers/gpu/drm/i915/oa/i915_oa_sklgt2.hrenamed from drivers/gpu/drm/i915/i915_oa_sklgt2.h+1−1

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drivers/gpu/drm/i915/oa/i915_oa_sklgt3.crenamed from drivers/gpu/drm/i915/i915_oa_sklgt3.c+0−0

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drivers/gpu/drm/i915/oa/i915_oa_sklgt3.hrenamed from drivers/gpu/drm/i915/i915_oa_sklgt3.h+1−1

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drivers/gpu/drm/i915/oa/i915_oa_sklgt4.crenamed from drivers/gpu/drm/i915/i915_oa_sklgt4.c+0−0

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drivers/gpu/drm/i915/oa/i915_oa_sklgt4.hrenamed from drivers/gpu/drm/i915/i915_oa_sklgt4.h+1−1

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drivers/gpu/drm/i915/selftests/i915_active.c+97−27

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drivers/gpu/drm/i915/selftests/i915_gem.c+4−7

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drivers/gpu/drm/i915/selftests/i915_gem_evict.c+2−1

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drivers/gpu/drm/i915/selftests/i915_gem_gtt.c+1−3

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drivers/gpu/drm/i915/selftests/i915_live_selftests.h+1−1

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drivers/gpu/drm/i915/selftests/i915_mock_selftests.h+1−1

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drivers/gpu/drm/i915/selftests/i915_request.c+25−18

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drivers/gpu/drm/i915/selftests/i915_selftest.c+64−1

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drivers/gpu/drm/i915/selftests/i915_vma.c+10−0

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drivers/gpu/drm/i915/selftests/igt_flush_test.c+3−2

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drivers/gpu/drm/i915/selftests/igt_reset.c+18−20

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drivers/gpu/drm/i915/selftests/igt_reset.h+6−4

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drivers/gpu/drm/i915/selftests/igt_spinner.c+6−2

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drivers/gpu/drm/i915/selftests/igt_spinner.h+3−0

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drivers/gpu/drm/i915/selftests/igt_wedge_me.h+0−58

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drivers/gpu/drm/i915/selftests/mock_gem_device.c+5−13

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drivers/gpu/drm/i915/selftests/mock_gtt.c+3−0

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drivers/gpu/drm/i915/selftests/mock_uncore.c+2−2

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include/drm/i915_component.h+1−1

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include/drm/i915_drm.h+8−5

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include/drm/i915_pciids.h+12−1

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include/uapi/drm/i915_drm.h+1−0

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