MT8192 contains an experimental Accelerator Coherency Port implementation, which does not work correctly but was unintentionally enabled by default. For correct operation of the GPU, we must set a chicken bit disabling ACP on MT8192. Adapted from the following downstream change to the out-of-tree, legacy Mali GPU driver: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/2781271/5 Note this change is required for both Panfrost and the legacy kernel driver.
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| @@ -6,6 +6,7 @@ · 5 unmodified lines | ||
| 6 | 6 | #include <linux/export.h> |
| 7 | 7 | #include <linux/jiffies.h> |
| 8 | 8 | #include <linux/regmap.h> |
| 9 | +#include <linux/mfd/syscon.h> | |
| 9 | 10 | #include <linux/soc/mediatek/infracfg.h> |
| 10 | 11 | #include <asm/processor.h> |
| 11 | 12 | |
| @@ -72,3 +73,21 @@ int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask, · 60 unmodified lines | ||
| 72 | 73 | |
| 73 | 74 | return ret; |
| 74 | 75 | } |
| 76 | + | |
| 77 | +static int __init mtk_infracfg_init(void) | |
| 78 | +{ | |
| 79 | + struct regmap *infracfg; | |
| 80 | + | |
| 81 | + /* | |
| 82 | + * MT8192 has an experimental path to route GPU traffic to the DSU's | |
| 83 | + * Accelerator Coherency Port, which is inadvertently enabled by | |
| 84 | + * default. It turns out not to work, so disable it to prevent spurious | |
| 85 | + * GPU faults. | |
| 86 | + */ | |
| 87 | + infracfg = syscon_regmap_lookup_by_compatible("mediatek,mt8192-infracfg"); | |
| 88 | + if (!IS_ERR(infracfg)) | |
| 89 | + regmap_set_bits(infracfg, MT8192_INFRA_CTRL, | |
| 90 | + MT8192_INFRA_CTRL_DISABLE_MFG2ACP); | |
| 91 | + return 0; | |
| 92 | +} | |
| 93 | +postcore_initcall(mtk_infracfg_init); | |
| @@ -277,6 +277,9 @@ · 276 unmodified lines | ||
| 277 | 277 | #define INFRA_TOPAXI_PROTECTEN_SET 0x0260 |
| 278 | 278 | #define INFRA_TOPAXI_PROTECTEN_CLR 0x0264 |
| 279 | 279 | |
| 280 | +#define MT8192_INFRA_CTRL 0x290 | |
| 281 | +#define MT8192_INFRA_CTRL_DISABLE_MFG2ACP BIT(9) | |
| 282 | + | |
| 280 | 283 | #define REG_INFRA_MISC 0xf00 |
| 281 | 284 | #define F_DDR_4GB_SUPPORT_EN BIT(13) |
| 282 | 285 | |