| @@ -499,16 +499,14 @@ static int mce_usable_address(struct mce *m) · 498 unmodified lines |
| 499 | 499 | return 1; |
| 500 | 500 | } |
| 501 | 501 | |
| 502 | | −static bool memory_error(struct mce *m) |
| 502 | +bool mce_is_memory_error(struct mce *m) |
| 503 | 503 | { |
| 504 | | − struct cpuinfo_x86 *c = &boot_cpu_data; |
| 505 | | − |
| 506 | | − if (c->x86_vendor == X86_VENDOR_AMD) { |
| 504 | + if (m->cpuvendor == X86_VENDOR_AMD) { |
| 507 | 505 | /* ErrCodeExt[20:16] */ |
| 508 | 506 | u8 xec = (m->status >> 16) & 0x1f; |
| 509 | 507 | |
| 510 | 508 | return (xec == 0x0 || xec == 0x8); |
| 511 | | − } else if (c->x86_vendor == X86_VENDOR_INTEL) { |
| 509 | + } else if (m->cpuvendor == X86_VENDOR_INTEL) { |
| 512 | 510 | /* |
| 513 | 511 | * Intel SDM Volume 3B - 15.9.2 Compound Error Codes |
| 514 | 512 | * |
| @@ -529,6 +527,7 @@ static bool memory_error(struct mce *m) · 14 unmodified lines |
| 529 | 527 | |
| 530 | 528 | return false; |
| 531 | 529 | } |
| 530 | +EXPORT_SYMBOL_GPL(mce_is_memory_error); |
| 532 | 531 | |
| 533 | 532 | static bool cec_add_mce(struct mce *m) |
| 534 | 533 | { |
| @@ -536,7 +535,7 @@ static bool cec_add_mce(struct mce *m) · 1 unmodified line |
| 536 | 535 | return false; |
| 537 | 536 | |
| 538 | 537 | /* We eat only correctable DRAM errors with usable addresses. */ |
| 539 | | − if (memory_error(m) && |
| 538 | + if (mce_is_memory_error(m) && |
| 540 | 539 | !(m->status & MCI_STATUS_UC) && |
| 541 | 540 | mce_usable_address(m)) |
| 542 | 541 | if (!cec_add_elem(m->addr >> PAGE_SHIFT)) |
| @@ -713,7 +712,7 @@ bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b) · 170 unmodified lines |
| 713 | 712 | |
| 714 | 713 | severity = mce_severity(&m, mca_cfg.tolerant, NULL, false); |
| 715 | 714 | |
| 716 | | − if (severity == MCE_DEFERRED_SEVERITY && memory_error(&m)) |
| 715 | + if (severity == MCE_DEFERRED_SEVERITY && mce_is_memory_error(&m)) |
| 717 | 716 | if (m.status & MCI_STATUS_ADDRV) |
| 718 | 717 | m.severity = severity; |
| 719 | 718 | |