History

net: hns3: rename gl_adapt_enable in struct hns3_enet_coalesce

Besides GL(Gap Limiting), QL(Quantity Limiting) can be modified dynamically when DIM is supported. So rename gl_adapt_enable as adapt_enable in struct hns3_enet_coalesce.

Huazhong Tan committed 5 years ago

Commit de25bcc1 parent 5ac84b03 files · +11 −11Browse files

Unified · Split

3 files
  1. drivers/net/ethernet/hisilicon/hns3/hns3_enet.c +6 −6
  2. drivers/net/ethernet/hisilicon/hns3/hns3_enet.h +1 −1
  3. drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c +4 −4
drivers/net/ethernet/hisilicon/hns3/hns3_enet.c+6−6
@@ -211,8 +211,8 @@ void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector, · 210 unmodified lines
211211 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
212212 */
213213
214− if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable &&
215− !tqp_vector->rx_group.coal.gl_adapt_enable)
214+ if (rl_reg > 0 && !tqp_vector->tx_group.coal.adapt_enable &&
215+ !tqp_vector->rx_group.coal.adapt_enable)
216216 /* According to the hardware, the range of rl_reg is
217217 * 0-59 and the unit is 4.
218218 */
@@ -273,8 +273,8 @@ static void hns3_vector_coalesce_init(struct hns3_enet_tqp_vector *tqp_vector, · 54 unmodified lines
273273 *
274274 * Default: enable interrupt coalescing self-adaptive and GL
275275 */
276− tx_coal->gl_adapt_enable = 1;
277− rx_coal->gl_adapt_enable = 1;
276+ tx_coal->adapt_enable = 1;
277+ rx_coal->adapt_enable = 1;
278278
279279 tx_coal->int_gl = HNS3_INT_GL_50K;
280280 rx_coal->int_gl = HNS3_INT_GL_50K;
@@ -3384,14 +3384,14 @@ static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector) · 3103 unmodified lines
33843384 tqp_vector->last_jiffies + msecs_to_jiffies(1000)))
33853385 return;
33863386
3387− if (rx_group->coal.gl_adapt_enable) {
3387+ if (rx_group->coal.adapt_enable) {
33883388 rx_update = hns3_get_new_int_gl(rx_group);
33893389 if (rx_update)
33903390 hns3_set_vector_coalesce_rx_gl(tqp_vector,
33913391 rx_group->coal.int_gl);
33923392 }
33933393
3394− if (tx_group->coal.gl_adapt_enable) {
3394+ if (tx_group->coal.adapt_enable) {
33953395 tx_update = hns3_get_new_int_gl(tx_group);
33963396 if (tx_update)
33973397 hns3_set_vector_coalesce_tx_gl(tqp_vector,
drivers/net/ethernet/hisilicon/hns3/hns3_enet.h+1−1
@@ -436,7 +436,7 @@ struct hns3_enet_coalesce { · 435 unmodified lines
436436 u16 int_gl;
437437 u16 int_ql;
438438 u16 int_ql_max;
439− u8 gl_adapt_enable:1;
439+ u8 adapt_enable:1;
440440 u8 ql_enable:1;
441441 u8 unit_1us:1;
442442 enum hns3_flow_level_range flow_level;
drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c+4−4
@@ -1105,9 +1105,9 @@ static int hns3_get_coalesce_per_queue(struct net_device *netdev, u32 queue, · 1104 unmodified lines
11051105 rx_vector = priv->ring[queue_num + queue].tqp_vector;
11061106
11071107 cmd->use_adaptive_tx_coalesce =
1108− tx_vector->tx_group.coal.gl_adapt_enable;
1108+ tx_vector->tx_group.coal.adapt_enable;
11091109 cmd->use_adaptive_rx_coalesce =
1110− rx_vector->rx_group.coal.gl_adapt_enable;
1110+ rx_vector->rx_group.coal.adapt_enable;
11111111
11121112 cmd->tx_coalesce_usecs = tx_vector->tx_group.coal.int_gl;
11131113 cmd->rx_coalesce_usecs = rx_vector->rx_group.coal.int_gl;
@@ -1268,9 +1268,9 @@ static void hns3_set_coalesce_per_queue(struct net_device *netdev, · 154 unmodified lines
12681268 tx_vector = priv->ring[queue].tqp_vector;
12691269 rx_vector = priv->ring[queue_num + queue].tqp_vector;
12701270
1271− tx_vector->tx_group.coal.gl_adapt_enable =
1271+ tx_vector->tx_group.coal.adapt_enable =
12721272 cmd->use_adaptive_tx_coalesce;
1273− rx_vector->rx_group.coal.gl_adapt_enable =
1273+ rx_vector->rx_group.coal.adapt_enable =
12741274 cmd->use_adaptive_rx_coalesce;
12751275
12761276 tx_vector->tx_group.coal.int_gl = cmd->tx_coalesce_usecs;